From a147acd7914582819ac20ddd0c3ca7e4bc4fe093 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 2 Nov 2015 18:42:55 +0200
Subject: [PATCH 001/972] spi_engine: Add support for multiple SDI lines.

By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines.
The supported number of SDI lines are: 1, 2, 3 and 4.
---
 .../axi_spi_engine/axi_spi_engine.v           |   8 +-
 .../spi_engine_execution.v                    | 361 +++++++++---------
 .../spi_engine_interconnect.v                 |   8 +-
 .../spi_engine_offload/spi_engine_offload.v   |   7 +-
 4 files changed, 204 insertions(+), 180 deletions(-)

diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
index 35bf015e5..9e5980110 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
@@ -42,7 +42,7 @@ module axi_spi_engine (
 
 	output sdi_data_ready,
 	input sdi_data_valid,
-	input [7:0] sdi_data,
+	input [(SDI_DATA_WIDTH-1):0] sdi_data,
 
 	output sync_ready,
 	input sync_valid,
@@ -72,7 +72,9 @@ parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4;
 parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4;
 
 parameter ID = 'h00;
-localparam PCORE_VERSION = 'h010061;
+parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+
+localparam PCORE_VERSION = 'h010071;
 
 wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
 wire cmd_fifo_almost_empty;
@@ -307,7 +309,7 @@ assign sdi_fifo_almost_full =
 	`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
 
 util_axis_fifo #(
-	.DATA_WIDTH(8),
+	.DATA_WIDTH(SDI_DATA_WIDTH),
 	.ASYNC_CLK(ASYNC_SPI_CLK),
 	.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
 	.S_AXIS_REGISTERED(0)
diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
index 12173a6e7..223cadabc 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
@@ -1,39 +1,45 @@
 
 module spi_engine_execution (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	output reg active,
+  output reg active,
 
-	output cmd_ready,
-	input cmd_valid,
-	input [15:0] cmd,
+  output cmd_ready,
+  input cmd_valid,
+  input [15:0] cmd,
 
-	input sdo_data_valid,
-	output reg sdo_data_ready,
-	input [7:0] sdo_data,
+  input sdo_data_valid,
+  output reg sdo_data_ready,
+  input [7:0] sdo_data,
 
-	input sdi_data_ready,
-	output reg sdi_data_valid,
-	output [7:0] sdi_data,
+  input sdi_data_ready,
+  output reg sdi_data_valid,
+  output [(SDI_DATA_WIDTH-1):0] sdi_data,
 
-	input sync_ready,
-	output reg sync_valid,
-	output [7:0] sync,
+  input sync_ready,
+  output reg sync_valid,
+  output [7:0] sync,
 
-	output reg sclk,
-	output sdo,
-	output reg sdo_t,
-	input sdi,
-	output reg [NUM_OF_CS-1:0] cs,
-	output reg three_wire
+  output reg sclk,
+  output sdo,
+  output reg sdo_t,
+  input sdi,
+  input sdi_1,
+  input sdi_2,
+  input sdi_3,
+  output reg [NUM_OF_CS-1:0] cs,
+  output reg three_wire
 );
 
 parameter NUM_OF_CS = 1;
 parameter DEFAULT_SPI_CFG = 0;
 parameter DEFAULT_CLK_DIV = 0;
+parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
 
-localparam CMD_TRANSFER	= 2'b00;
+
+localparam NUM_OF_SDI = SDI_DATA_WIDTH >> 3;
+localparam CMD_TRANSFER = 2'b00;
 localparam CMD_CHIPSELECT = 2'b01;
 localparam CMD_WRITE = 2'b10;
 localparam CMD_MISC = 2'b11;
@@ -83,6 +89,9 @@ wire sdo_enabled = cmd_d1[8];
 wire sdi_enabled = cmd_d1[9];
 
 reg [8:0] data_shift = 'h0;
+reg [8:0] data_shift_1 = 'h0;
+reg [8:0] data_shift_2 = 'h0;
+reg [8:0] data_shift_3 = 'h0;
 
 wire [1:0] inst = cmd[13:12];
 wire [1:0] inst_d1 = cmd_d1[13:12];
@@ -97,54 +106,54 @@ wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
 assign cmd_ready = idle;
 
 always @(posedge clk) begin
-	if (cmd_ready)
-		cmd_d1 <= cmd;
+        if (cmd_ready)
+                cmd_d1 <= cmd;
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		active <= 1'b0;
-	end else begin
-		if (exec_cmd == 1'b1)
-			active <= 1'b1;
-		else if (sync_ready == 1'b1 && sync_valid == 1'b1)
-			active <= 1'b0;
-	end
+        if (resetn == 1'b0) begin
+                active <= 1'b0;
+        end else begin
+                if (exec_cmd == 1'b1)
+                        active <= 1'b1;
+                else if (sync_ready == 1'b1 && sync_valid == 1'b1)
+                        active <= 1'b0;
+        end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		cpha <= DEFAULT_SPI_CFG[0];
-		cpol <= DEFAULT_SPI_CFG[1];
-		three_wire <= DEFAULT_SPI_CFG[2];
-		clk_div <= DEFAULT_CLK_DIV;
-	end else if (exec_write_cmd == 1'b1) begin
-		 if (cmd[8] == REG_CONFIG) begin
-			cpha <= cmd[0];
-			cpol <= cmd[1];
-			three_wire <= cmd[2];
-		end else if (cmd[8] == REG_CLK_DIV) begin
-			clk_div <= cmd[7:0];
-		end
-	end
+        if (resetn == 1'b0) begin
+                cpha <= DEFAULT_SPI_CFG[0];
+                cpol <= DEFAULT_SPI_CFG[1];
+                three_wire <= DEFAULT_SPI_CFG[2];
+                clk_div <= DEFAULT_CLK_DIV;
+        end else if (exec_write_cmd == 1'b1) begin
+                 if (cmd[8] == REG_CONFIG) begin
+                        cpha <= cmd[0];
+                        cpol <= cmd[1];
+                        three_wire <= cmd[2];
+                end else if (cmd[8] == REG_CLK_DIV) begin
+                        clk_div <= cmd[7:0];
+                end
+        end
 end
 
 always @(posedge clk) begin
-	if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
-		clk_div_counter == 'h01) || clk_div == 'h00)
-		clk_div_last <= 1'b1;
-	else
-		clk_div_last <= 1'b0;
+        if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
+                clk_div_counter == 'h01) || clk_div == 'h00)
+                clk_div_last <= 1'b1;
+        else
+                clk_div_last <= 1'b0;
 end
 
 always @(posedge clk) begin
-	if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
-		clk_div_counter <= clk_div;
-		trigger <= 1'b1;
-	end else begin
-		clk_div_counter <= clk_div_counter - 1'b1;
-		trigger <= 1'b0;
-	end
+        if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
+                clk_div_counter <= clk_div;
+                trigger <= 1'b1;
+        end else begin
+                clk_div_counter <= clk_div_counter - 1'b1;
+                trigger <= 1'b0;
+        end
 end
 
 wire trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
@@ -155,159 +164,169 @@ wire cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last
 wire cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
 
 always @(posedge clk) begin
-	if (idle == 1'b1)
-		counter <= 'h00;
-	else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
-		counter <= counter + (transfer_active ? 'h1 : 'h10);
+        if (idle == 1'b1)
+                counter <= 'h00;
+        else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
+                counter <= counter + (transfer_active ? 'h1 : 'h10);
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		idle <= 1'b1;
-	end else begin
-		if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
-			idle <= 1'b0;
-		end else begin
-			case (inst_d1)
-			CMD_TRANSFER: begin
-				if (transfer_active == 1'b0 && wait_for_io == 1'b0)
-					idle <= 1'b1;
-			end
-			CMD_CHIPSELECT: begin
-				if (cs_sleep_counter_compare2)
-					idle <= 1'b1;
-			end
-			CMD_MISC: begin
-				case (cmd_d1[8])
-				MISC_SLEEP: begin
-					if (sleep_counter_compare)
-						idle <= 1'b1;
-				end
-				MISC_SYNC: begin
-					if (sync_ready)
-						idle <= 1'b1;
-				end
-				endcase
-			end
-			endcase
-		end
-	end
+        if (resetn == 1'b0) begin
+                idle <= 1'b1;
+        end else begin
+                if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
+                        idle <= 1'b0;
+                end else begin
+                        case (inst_d1)
+                        CMD_TRANSFER: begin
+                                if (transfer_active == 1'b0 && wait_for_io == 1'b0)
+                                        idle <= 1'b1;
+                        end
+                        CMD_CHIPSELECT: begin
+                                if (cs_sleep_counter_compare2)
+                                        idle <= 1'b1;
+                        end
+                        CMD_MISC: begin
+                                case (cmd_d1[8])
+                                MISC_SLEEP: begin
+                                        if (sleep_counter_compare)
+                                                idle <= 1'b1;
+                                end
+                                MISC_SYNC: begin
+                                        if (sync_ready)
+                                                idle <= 1'b1;
+                                end
+                                endcase
+                        end
+                        endcase
+                end
+        end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		cs <= 'hff;
-	end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
-		cs <= cmd_d1[NUM_OF_CS-1:0];
-	end
+        if (resetn == 1'b0) begin
+                cs <= 'hff;
+        end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
+                cs <= cmd_d1[NUM_OF_CS-1:0];
+        end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		sync_valid <= 1'b0;
-	end else begin
-		if (exec_sync_cmd == 1'b1) begin
-			sync_valid <= 1'b1;
-		end else if (sync_ready == 1'b1) begin
-			sync_valid <= 1'b0;
-		end
-	end
+        if (resetn == 1'b0) begin
+                sync_valid <= 1'b0;
+        end else begin
+                if (exec_sync_cmd == 1'b1) begin
+                        sync_valid <= 1'b1;
+                end else if (sync_ready == 1'b1) begin
+                        sync_valid <= 1'b0;
+                end
+        end
 end
 
 assign sync = cmd_d1[7:0];
 
 always @(posedge clk) begin
-	if (resetn == 1'b0)
-		sdo_data_ready <= 1'b0;
-	else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
-		transfer_active == 1'b1)
-		sdo_data_ready <= 1'b1;
-	else if (sdo_data_valid == 1'b1)
-		sdo_data_ready <= 1'b0;
+        if (resetn == 1'b0)
+                sdo_data_ready <= 1'b0;
+        else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
+                transfer_active == 1'b1)
+                sdo_data_ready <= 1'b1;
+        else if (sdo_data_valid == 1'b1)
+                sdo_data_ready <= 1'b0;
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0)
-		sdi_data_valid <= 1'b0;
-	else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 &&
-		transfer_active == 1'b1)
-		sdi_data_valid <= 1'b1;
-	else if (sdi_data_ready == 1'b1)
-		sdi_data_valid <= 1'b0;
+        if (resetn == 1'b0)
+                sdi_data_valid <= 1'b0;
+        else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 &&
+                transfer_active == 1'b1)
+                sdi_data_valid <= 1'b1;
+        else if (sdi_data_ready == 1'b1)
+                sdi_data_valid <= 1'b0;
 end
 
 wire io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
-	(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
+        (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
 wire io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
-	(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
+        (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
 
 always @(posedge clk) begin
-	if (idle == 1'b1) begin
-		last_transfer <= 1'b0;
-	end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
-		if (transfer_counter == cmd_d1[7:0])
-			last_transfer <= 1'b1;
-		else
-			last_transfer <= 1'b0;
-	end
+        if (idle == 1'b1) begin
+                last_transfer <= 1'b0;
+        end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
+                if (transfer_counter == cmd_d1[7:0])
+                        last_transfer <= 1'b1;
+                else
+                        last_transfer <= 1'b0;
+        end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		transfer_active <= 1'b0;
-		wait_for_io <= 1'b0;
-	end else begin
-		if (exec_transfer_cmd == 1'b1) begin
-			wait_for_io <= 1'b1;
-			transfer_active <= 1'b0;
-		end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
-			wait_for_io <= 1'b0;
-			if (last_transfer == 1'b0)
-				transfer_active <= 1'b1;
-			else
-				transfer_active <= 1'b0;
-		end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
-			if (last_transfer == 1'b1 || io_ready2 == 1'b0)
-				transfer_active <= 1'b0;
-			if (io_ready2 == 1'b0)
-				wait_for_io <= 1'b1;
-		end
-	end
+        if (resetn == 1'b0) begin
+                transfer_active <= 1'b0;
+                wait_for_io <= 1'b0;
+        end else begin
+                if (exec_transfer_cmd == 1'b1) begin
+                        wait_for_io <= 1'b1;
+                        transfer_active <= 1'b0;
+                end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
+                        wait_for_io <= 1'b0;
+                        if (last_transfer == 1'b0)
+                                transfer_active <= 1'b1;
+                        else
+                                transfer_active <= 1'b0;
+                end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
+                        if (last_transfer == 1'b1 || io_ready2 == 1'b0)
+                                transfer_active <= 1'b0;
+                        if (io_ready2 == 1'b0)
+                                wait_for_io <= 1'b1;
+                end
+        end
 end
 
 always @(posedge clk) begin
-	if (transfer_active == 1'b1 || wait_for_io == 1'b1)
-	begin
-		sdo_t <= ~sdo_enabled;
-	end else begin
-		sdo_t <= 1'b1;
-	end
+        if (transfer_active == 1'b1 || wait_for_io == 1'b1)
+        begin
+                sdo_t <= ~sdo_enabled;
+        end else begin
+                sdo_t <= 1'b1;
+        end
 end
 
 always @(posedge clk) begin
-	if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
-		if (first_bit == 1'b1)
-			data_shift[8:1] <= sdo_data;
-		else
-			data_shift[8:1] <= data_shift[7:0];
-	end
+        if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
+                if (first_bit == 1'b1)
+                        data_shift[8:1] <= sdo_data;
+                else
+                        data_shift[8:1] <= data_shift[7:0];
+            data_shift_1[8:1] <= data_shift_1[7:0];
+            data_shift_2[8:1] <= data_shift_2[7:0];
+            data_shift_3[8:1] <= data_shift_3[7:0];
+        end
 end
 
 assign sdo = data_shift[8];
-assign sdi_data = data_shift[7:0];
+assign sdi_data = (NUM_OF_SDI == 1) ? data_shift[7:0] :
+                  (NUM_OF_SDI == 2) ? {data_shift_1[7:0], data_shift[7:0]} :
+                  (NUM_OF_SDI == 3) ? {data_shift_2[7:0], data_shift_1[7:0], data_shift[7:0]} :
+                  (NUM_OF_SDI == 4) ? {data_shift_3[7:0], data_shift_2[7:0], data_shift_1[7:0], data_shift[7:0]} :
+                  data_shift[7:0];
 
 always @(posedge clk) begin
-	if (trigger_rx == 1'b1) begin
-		data_shift[0] <= sdi;
-	end
+        if (trigger_rx == 1'b1) begin
+                data_shift[0] <= sdi;
+        data_shift_1[0] <= sdi_1;
+        data_shift_2[0] <= sdi_2;
+        data_shift_3[0] <= sdi_3;
+        end
 end
 
 always @(posedge clk) begin
-	if (transfer_active == 1'b1) begin
-		sclk <= cpol ^ cpha ^ ntx_rx;
-	end else begin
-		sclk <= cpol;
-	end
+        if (transfer_active == 1'b1) begin
+                sclk <= cpol ^ cpha ^ ntx_rx;
+        end else begin
+                sclk <= cpol;
+        end
 end
 
 endmodule
diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
index 463073955..14cf70aeb 100644
--- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
+++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
@@ -14,7 +14,7 @@ module spi_engine_interconnect (
 
 	input m_sdi_valid,
 	output m_sdi_ready,
-	input [7:0] m_sdi_data,
+	input [(SDI_DATA_WIDTH-1):0] m_sdi_data,
 
 	input m_sync_valid,
 	output m_sync_ready,
@@ -31,7 +31,7 @@ module spi_engine_interconnect (
 
 	output s0_sdi_valid,
 	input s0_sdi_ready,
-	output [7:0] s0_sdi_data,
+	output [(SDI_DATA_WIDTH-1):0] s0_sdi_data,
 
 	output s0_sync_valid,
 	input s0_sync_ready,
@@ -48,13 +48,15 @@ module spi_engine_interconnect (
 
 	output s1_sdi_valid,
 	input s1_sdi_ready,
-	output [7:0] s1_sdi_data,
+	output [(SDI_DATA_WIDTH-1):0] s1_sdi_data,
 
 	output s1_sync_valid,
 	input s1_sync_ready,
 	output [7:0] s1_sync
 );
 
+parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+
 reg s_active = 1'b0;
 
 reg idle = 1'b1;
diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
index 862b869b1..0082bec04 100644
--- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v
+++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
@@ -27,7 +27,7 @@ module spi_engine_offload (
 
 	input sdi_data_valid,
 	output sdi_data_ready,
-	input [7:0] sdi_data,
+	input [(SDI_DATA_WIDTH-1):0] sdi_data,
 
 	input sync_valid,
 	output sync_ready,
@@ -35,12 +35,13 @@ module spi_engine_offload (
 
 	output offload_sdi_valid,
 	input offload_sdi_ready,
-	output [7:0] offload_sdi_data
+	output [(SDI_DATA_WIDTH-1):0] offload_sdi_data
 );
 
 parameter ASYNC_SPI_CLK = 0;
 parameter CMD_MEM_ADDRESS_WIDTH = 4;
 parameter SDO_MEM_ADDRESS_WIDTH = 4;
+parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
 
 reg spi_active = 1'b0;
 
@@ -92,7 +93,7 @@ end
 assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
 
 always @(posedge spi_clk) begin
-	spi_enabled <= spi_enable | spi_active;	
+	spi_enabled <= spi_enable | spi_active;
 end
 
 sync_bits # (

From 27266c59ee944f403f95010ab5dbfb4285062e05 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 3 Nov 2015 15:03:35 +0200
Subject: [PATCH 002/972] ad7616_sdz: Add project source files

---
 projects/ad7616_sdz/common/ad7616_bd.tcl      |  26 +++
 .../ad7616_sdz/zc706/parallel_if_cnstr.xdc    |  36 ++++
 projects/ad7616_sdz/zc706/serial_if_cnstr.xdc |  23 +++
 projects/ad7616_sdz/zc706/system_bd.tcl       |   4 +
 projects/ad7616_sdz/zc706/system_project.tcl  |  27 +++
 projects/ad7616_sdz/zc706/system_top.v        | 183 ++++++++++++++++++
 6 files changed, 299 insertions(+)
 create mode 100644 projects/ad7616_sdz/common/ad7616_bd.tcl
 create mode 100644 projects/ad7616_sdz/zc706/parallel_if_cnstr.xdc
 create mode 100644 projects/ad7616_sdz/zc706/serial_if_cnstr.xdc
 create mode 100644 projects/ad7616_sdz/zc706/system_bd.tcl
 create mode 100644 projects/ad7616_sdz/zc706/system_project.tcl
 create mode 100644 projects/ad7616_sdz/zc706/system_top.v

diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
new file mode 100644
index 000000000..c391af651
--- /dev/null
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -0,0 +1,26 @@
+
+# data interfaces
+
+create_bd_port -dir O sclk
+create_bd_port -dir O sdo
+create_bd_port -dir I sdi_0
+create_bd_port -dir I sdi_1
+
+create_bd_port -dir O -from 15 -to 0 db_o
+create_bd_port -dir I -from 15 -to 0 db_i
+create_bd_port -dir O rd_n
+create_bd_port -dir O wr_n
+
+# control lines
+
+create_bd_port -dri O reset_n
+create_bd_port -dir O cnvst
+create_bd_port -dir O cs_n
+create_bd_port -dir O busy
+create_bd_port -dir O seq_en
+create_bd_port -dir O -from 1 -to 0 hw_rngsel
+create_bd_port -dir O -from 2 -to 0 chsel
+
+# instantiation
+
+
diff --git a/projects/ad7616_sdz/zc706/parallel_if_cnstr.xdc b/projects/ad7616_sdz/zc706/parallel_if_cnstr.xdc
new file mode 100644
index 000000000..e7903fc5d
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/parallel_if_cnstr.xdc
@@ -0,0 +1,36 @@
+
+# ad7616
+
+set_property -dict {PACKAGE_PIN AC14     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[0] ]        ; ## FMC_LPC_LA10_P
+set_property -dict {PACKAGE_PIN AJ15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[1] ]        ; ## FMC_LPC_LA04_P
+set_property -dict {PACKAGE_PIN AH14     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[2] ]        ; ## FMC_LPC_LA09_P
+set_property -dict {PACKAGE_PIN AG12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[3] ]        ; ## FMC_LPC_LA03_P
+set_property -dict {PACKAGE_PIN AE15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[4] ]        ; ## FMC_LPC_LA05_N
+set_property -dict {PACKAGE_PIN AF12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[5] ]        ; ## FMC_LPC_LA02_N
+set_property -dict {PACKAGE_PIN AC12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[6] ]        ; ## FMC_LPC_LA06_N
+set_property -dict {PACKAGE_PIN AF13     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[7] ]        ; ## FMC_LPC_LA00_CC_N
+set_property -dict {PACKAGE_PIN AE16     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[8] ]        ; ## FMC_LPC_LA05_P
+set_property -dict {PACKAGE_PIN AE12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[9] ]        ; ## FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN AE17     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[10]]        ; ## FMC_LPC_LA16_N
+set_property -dict {PACKAGE_PIN AE13     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[11]]        ; ## FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN AG15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[12]]        ; ## FMC_LPC_LA01_CC_N
+set_property -dict {PACKAGE_PIN AG16     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[13]]        ; ## FMC_LPC_CLK0_M2C_N
+set_property -dict {PACKAGE_PIN AG17     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[14]]        ; ## FMC_LPC_CLK0_M2C_P
+set_property -dict {PACKAGE_PIN AF15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[15]]        ; ## FMC_LPC_LA01_CC_P
+
+set_property -dict {PACKAGE_PIN AH12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rd_n]          ; ## FMC_LPC_LA03_N
+set_property -dict {PACKAGE_PIN AH13     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports wr_n]          ; ## FMC_LPC_LA09_N
+
+# control lines
+
+set_property -dict {PACKAGE_PIN AF30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports convst]         ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN AH29    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[0]]       ; ## FMC_LPC_LA21_N
+set_property -dict {PACKAGE_PIN AK30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[1]]       ; ## FMC_LPC_LA26_N
+set_property -dict {PACKAGE_PIN AF29    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[2]]       ; ## FMC_LPC_LA25_P
+set_property -dict {PACKAGE_PIN AH28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports hw_rngsel[0]]   ; ## FMC_LPC_LA21_P
+set_property -dict {PACKAGE_PIN AJ30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports hw_rngsel[1]]   ; ## FMC_LPC_LA26_P
+set_property -dict {PACKAGE_PIN AC13    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports busy]           ; ## FMC_LPC_LA10_N
+set_property -dict {PACKAGE_PIN AJ28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports seq_en]         ; ## FMC_LPC_LA27_P
+set_property -dict {PACKAGE_PIN AK28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports reset_n]        ; ## FMC_LPC_LA22_N
+set_property -dict {PACKAGE_PIN AK15    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports cs_n]           ; ## FMC_LPC_LA04_N
+
diff --git a/projects/ad7616_sdz/zc706/serial_if_cnstr.xdc b/projects/ad7616_sdz/zc706/serial_if_cnstr.xdc
new file mode 100644
index 000000000..b977ea93f
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/serial_if_cnstr.xdc
@@ -0,0 +1,23 @@
+
+# ad7616
+
+# data interface
+
+set_property -dict {PACKAGE_PIN AH12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sclk]          ; ## FMC_LPC_LA03_N
+set_property -dict {PACKAGE_PIN AB12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sdo]           ; ## FMC_LPC_LA06_P
+set_property -dict {PACKAGE_PIN AE13     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sdi_0]         ; ## FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN AG15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sdi_1]         ; ## FMC_LPC_LA01_CC_N
+
+# control lines
+
+set_property -dict {PACKAGE_PIN AF30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports convst]         ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN AH29    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[0]]       ; ## FMC_LPC_LA21_N
+set_property -dict {PACKAGE_PIN AK30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[1]]       ; ## FMC_LPC_LA26_N
+set_property -dict {PACKAGE_PIN AF29    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[2]]       ; ## FMC_LPC_LA25_P
+set_property -dict {PACKAGE_PIN AH28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports hw_rngsel[0]]   ; ## FMC_LPC_LA21_P
+set_property -dict {PACKAGE_PIN AJ30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports hw_rngsel[1]]   ; ## FMC_LPC_LA26_P
+set_property -dict {PACKAGE_PIN AC13    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports busy]           ; ## FMC_LPC_LA10_N
+set_property -dict {PACKAGE_PIN AJ28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports seq_en]         ; ## FMC_LPC_LA27_P
+set_property -dict {PACKAGE_PIN AK28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports reset_n]        ; ## FMC_LPC_LA22_N
+set_property -dict {PACKAGE_PIN AK15    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports cs_n]           ; ## FMC_LPC_LA04_N
+
diff --git a/projects/ad7616_sdz/zc706/system_bd.tcl b/projects/ad7616_sdz/zc706/system_bd.tcl
new file mode 100644
index 000000000..74f34ef33
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
+source ../common/ad7616_bd.tcl
+
diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl
new file mode 100644
index 000000000..1890c021d
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/system_project.tcl
@@ -0,0 +1,27 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+set ad7616_interface "serial"
+#set ad7616_interface "parallel"
+
+adi_project_create ad7616_sdz_zc706
+
+if { $ad7616_interface eq "serial" } {
+  adi_project_files ad7616_sdz_zc706 [list \
+    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "system_top.v" \
+    "serial_if_constr.xdc" \
+    "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
+} else if { $ad7616_interface eq "parallel" } {
+  adi_project_files ad7616_sdz_zc706 [list \
+    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "system_top.v" \
+    "parallel_if_constr.xdc" \
+    "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
+
+} else {
+  return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."]
+}
+
diff --git a/projects/ad7616_sdz/zc706/system_top.v b/projects/ad7616_sdz/zc706/system_top.v
new file mode 100644
index 000000000..281f57ec4
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/system_top.v
@@ -0,0 +1,183 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  gpio_bd,
+
+  hdmi_out_clk,
+  hdmi_vsync,
+  hdmi_hsync,
+  hdmi_data_e,
+  hdmi_data,
+
+  spdif,
+
+  iic_scl,
+  iic_sda);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout   [14:0]  gpio_bd;
+
+  output          hdmi_out_clk;
+  output          hdmi_vsync;
+  output          hdmi_hsync;
+  output          hdmi_data_e;
+  output  [23:0]  hdmi_data;
+
+  output          spdif;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // instantiations
+
+  ad_iobuf #(
+    .DATA_WIDTH(15)
+  ) i_gpio_bd (
+    .dio_t(gpio_t[14:0]),
+    .dio_i(gpio_o[14:0]),
+    .dio_o(gpio_i[14:0]),
+    .dio_p(gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_12 (1'b0),
+    .ps_intr_13 (1'b0),
+    .spdif (spdif));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 214adbfd85800d6f3ff34f54c99d80048e199072 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 9 Nov 2015 10:51:46 +0200
Subject: [PATCH 003/972] ad7616_sdz_zc706: Add board related IO's to system
 top.

---
 projects/ad7616_sdz/zc706/system_top.v | 51 +++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 2 deletions(-)

diff --git a/projects/ad7616_sdz/zc706/system_top.v b/projects/ad7616_sdz/zc706/system_top.v
index 281f57ec4..04e5f13b1 100644
--- a/projects/ad7616_sdz/zc706/system_top.v
+++ b/projects/ad7616_sdz/zc706/system_top.v
@@ -75,7 +75,23 @@ module system_top (
   spdif,
 
   iic_scl,
-  iic_sda);
+  iic_sda,
+
+  spi_sdo,
+  spi_sdi_0,
+  spi_sdi_1,
+  spi_cs_n,
+
+  adc_db_o,
+  adc_db_i,
+  adc_rd_n,
+  adc_wr_n,
+  adc_reset_n,
+  adc_cnvst,
+  adc_busy,
+  adc_seq_en,
+  adc_hw_rngsel,
+  adc_chsel);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -113,6 +129,22 @@ module system_top (
   inout           iic_scl;
   inout           iic_sda;
 
+  output          spi_sdo;
+  input           spi_sdi_0;
+  input           spi_sdi_1;
+  output          spi_cs_n;
+
+  output  [15:0]  adc_db_o;
+  input   [15:0]  adc_db_i;
+  output          adc_rd_n;
+  output          adc_wr_n;
+  output          adc_reset_n;
+  output          adc_cnvst;
+  output          adc_busy;
+  output          adc_seq_en;
+  output  [ 1:0]  adc_hw_rngsel;
+  output  [ 2:0]  adc_chsel;
+
   // internal signals
 
   wire    [63:0]  gpio_i;
@@ -175,7 +207,22 @@ module system_top (
     .ps_intr_11 (1'b0),
     .ps_intr_12 (1'b0),
     .ps_intr_13 (1'b0),
-    .spdif (spdif));
+    .spdif (spdif),
+    .sclk (spi_sclk),
+    .sdo (spi_sdo),
+    .sdi_0 (spi_sdi_0),
+    .sdi_1 (spi_sdi_1),
+    .db_o (adc_db_o),
+    .db_i (adc_db_i),
+    .rd_n (adc_rd_n),
+    .wr_n (adc_wr_n),
+    .reset_n (adc_reset_n),
+    .cnvst (adc_cnvst),
+    .cs_n (spi_cs_n),
+    .busy (adc_busy),
+    .seq_en (adc_seq_en),
+    .hw_rngsel (adc_hw_rngsel),
+    .chsel (adc_chsel));
 
 endmodule
 

From 64d1948ea0c4d22f1e4dd8a5f89dbd11ff0d1f24 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 10 Nov 2015 13:32:56 +0200
Subject: [PATCH 004/972] axi_ad7616: Initial commit

---
 library/axi_ad7616/axi_ad7616.v      | 213 +++++++++++++++++++++++++++
 library/axi_ad7616/axi_ad7616_ip.tcl |  16 ++
 2 files changed, 229 insertions(+)
 create mode 100644 library/axi_ad7616/axi_ad7616.v
 create mode 100644 library/axi_ad7616/axi_ad7616_ip.tcl

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
new file mode 100644
index 000000000..4c7a05b33
--- /dev/null
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -0,0 +1,213 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad7616 (
+
+  // physical data interface
+
+  sclk,
+  cs_n,
+  sdo,
+  sdi_0,
+  sdi_1,
+
+  db_o,
+  db_i,
+  rd_n,
+  wr_n,
+
+  // physical control interface
+
+  reset_n,
+  cnvst,
+  busy,
+  seq_en,
+  hw_rngsel,
+  chsel,
+  crcen,
+  ser1w_n,
+  burst,
+  os,
+
+  // AXI Slave Memory Map
+
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awvalid,
+  s_axi_awaddr,
+  s_axi_awready,
+  s_axi_wvalid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wready,
+  s_axi_bvalid,
+  s_axi_bresp,
+  s_axi_bready,
+  s_axi_arvalid,
+  s_axi_araddr,
+  s_axi_arready,
+  s_axi_rvalid,
+  s_axi_rresp,
+  s_axi_rdata,
+  s_axi_rready,
+
+  // AXI-Stream Master
+
+  m_axis_tdata,
+  m_axis_tvalid,
+  m_axis_tready
+
+);
+
+  // parameters
+
+  parameter       ID = 0;
+  parameter       OP_MODE = 0;
+  parameter       IF_TYPE = 0;
+
+  localparam      PCORE_VERSION = 'h0001001;
+  localparam      SW = 0;
+  localparam      HW = 1;
+  localparam      SERIAL = 0;
+  localparam      PARALLEL = 1;
+
+  // IO definitions
+
+  output          sclk;
+  output          cs_n;
+  output          sdo;
+  input           sdi_0;
+  input           sdi_1;
+
+  output  [15:0]  db_o;
+  input   [15:0]  db_i;
+  output          rd_n;
+  output          wr_n;
+
+  output          reset_n;
+  output          cnvst;
+  output          busy;
+  output          seq_en;
+  output  [ 1:0]  hw_rngsel;
+  output  [ 2:0]  chsel;
+  output          crcen;
+  output          ser1w_n;
+  output          burst;
+  output  [ 2:0]  os;
+
+
+  input           s_axi_aclk;
+  input           s_axi_aresetn;
+  input           s_axi_awvalid;
+  input   [31:0]  s_axi_awaddr;
+  output          s_axi_awready;
+  input           s_axi_wvalid;
+  input   [31:0]  s_axi_wdata;
+  input   [ 3:0]  s_axi_wstrb;
+  output          s_axi_wready;
+  output          s_axi_bvalid;
+  output  [ 1:0]  s_axi_bresp;
+  input           s_axi_bready;
+  input           s_axi_arvalid;
+  input   [31:0]  s_axi_araddr;
+  output          s_axi_arready;
+  output          s_axi_rvalid;
+  output  [ 1:0]  s_axi_rresp;
+  output  [31:0]  s_axi_rdata;
+  input           s_axi_rready;
+
+  output  [31:0]  m_axis_tdata;
+  input           m_axis_tready;
+  output          m_axis_tvalid;
+
+  // internal registers
+
+  // internal signals
+
+  wire            up_rreq_s;
+  wire    [13:0]  up_raddr_s;
+  wire    [31:0]  up_rdata_s[0:2];
+  wire            up_rack_s[0:2];
+  wire            up_wack_s[0:2];
+  wire            up_wreq_s;
+  wire    [13:0]  up_waddr_s;
+  wire    [31:0]  up_wdata_s;
+
+  // defaults
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+
+  // up bus interface
+
+  up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad7616/axi_ad7616_ip.tcl b/library/axi_ad7616/axi_ad7616_ip.tcl
new file mode 100644
index 000000000..10a7c0825
--- /dev/null
+++ b/library/axi_ad7616/axi_ad7616_ip.tcl
@@ -0,0 +1,16 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_ad7616
+adi_ip_files axi_ad7616 [list \
+    "axi_ad7616.v" ]
+
+adi_ip_add_core_dependencies { \
+    analog.com:user:spi_engine_execution:1.0 \
+    analog.com:user:axi_spi_engine:1.0 \
+    analog.com:user:spi_engine_offload:1.0 \
+    analog.com:user:spi_engine_interconnect:1.0 \
+}
+

From 229cd079b9ea91fe1811df1b4957215b1caf255b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 10 Nov 2015 13:34:29 +0200
Subject: [PATCH 005/972] spi_engine: Fix to support multiple SDI lines

---
 library/spi_engine/axi_spi_engine/axi_spi_engine.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
index 9e5980110..793c5fa01 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
@@ -93,7 +93,7 @@ wire sdo_fifo_in_valid;
 wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
 wire sdi_fifo_almost_full;
 
-wire [7:0] sdi_fifo_out_data;
+wire [31:0] sdi_fifo_out_data;
 wire sdi_fifo_out_ready;
 wire sdi_fifo_out_valid;
 

From e4927887fd165060b5061b9ac183a1874c148f67 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 10 Nov 2015 13:35:15 +0200
Subject: [PATCH 006/972] spi_engine_offload: Add sync_bits to the IP files
 list

---
 library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
index 87d54e817..6124b5672 100644
--- a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
+++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
@@ -3,6 +3,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create spi_engine_offload
 adi_ip_files spi_engine_offload [list \
+        "$ad_hdl_dir/library/common/sync_bits.v" \
 	"spi_engine_offload.v" \
 ]
 

From 952a491f5904d58b50b133489ee6a090e4abd189 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 12 Nov 2015 16:12:16 +0200
Subject: [PATCH 007/972] axi_ad7616: Add spi engine to the core

---
 library/axi_ad7616/axi_ad7616.v | 152 ++++++++++++++++++++++++++++++++
 1 file changed, 152 insertions(+)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 4c7a05b33..28b9c6f61 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -160,6 +160,7 @@ module axi_ad7616 (
 
   // internal registers
 
+
   // internal signals
 
   wire            up_rreq_s;
@@ -176,6 +177,157 @@ module axi_ad7616 (
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
 
+  generate if (IF_TYPE == 0) begin
+
+    wire spi_resetn_s;
+
+    axi_spi_engine #(
+      .SDI_DATA_WIDTH(),
+      .NUM_OFFLOAD()
+    ) i_axi_spi_engine(
+      .s_axi_aclk (up_clk),
+      .s_axi_aresetn (up_rstn),
+      .s_axi_awvalid (s_axi_awvalid),
+      .s_axi_awaddr (s_axi_awaddr),
+      .s_axi_awready (s_axi_awready),
+      .s_axi_wvalid (s_axi_wvalid),
+      .s_axi_wdata (s_axi_wdata),
+      .s_axi_wstrb (s_axi_wstrb),
+      .s_axi_wready (s_axi_wready),
+      .s_axi_bvalid (s_axi_bvalid),
+      .s_axi_bresp (s_axi_bresp),
+      .s_axi_bready (s_axi_bready),
+      .s_axi_arvalid (s_axi_arvalid),
+      .s_axi_araddr (s_axi_araddr),
+      .s_axi_arready (s_axi_arready),
+      .s_axi_rvalid (s_axi_rvalid),
+      .s_axi_rready (s_axi_rready),
+      .s_axi_rresp (s_axi_rresp),
+      .s_axi_rdata (s_axi_rdata),
+      .irq (),
+      .spi_clk (up_clk),
+      .spi_resetn (spi_resetn_s),
+      .cmd_ready (),
+      .cmd_valid (),
+      .cmd_data (),
+      .sdo_data_ready (),
+      .sdo_data_valid (),
+      .sdo_data (),
+      .sdi_data_ready (),
+      .sdi_data_valid (),
+      .sdi_data (),
+      .sync_ready (),
+      .sync_valid (),
+      .sync_data (),
+      .offload0_cmd_wr_en (),
+      .offload0_cmd_wr_data (),
+      .offload0_sdo_wr_en (),
+      .offload0_sdo_wr_data (),
+      .offload0_mem_reset (),
+      .offload0_enable (),
+      .offload0_enabled());
+
+    spi_engine_offload #(
+      .SDI_DATA_WIDTH()
+    ) i_spi_engine_offload(
+      .ctrl_clk (),
+      .ctrl_cmd_wr_en (),
+      .ctrl_cmd_wr_data (),
+      .ctrl_sdo_wr_en (),
+      .ctrl_sdo_wr_data (),
+      .ctrl_enable (),
+      .ctrl_enabled (),
+      .ctrl_mem_reset (),
+      .spi_clk (up_clk),
+      .spi_resetn (spi_resetn_s),
+      .trigger (),
+      .cmd_valid (),
+      .cmd_ready (),
+      .cmd (),
+      .sdo_data_valid (),
+      .sdo_data_ready (),
+      .sdo_data (),
+      .sdi_data_ready (),
+      .sdi_data (),
+      .sync_valid (),
+      .sync_ready (),
+      .sync_data (),
+      .offload_sdi_valid (),
+      .offload_sdi_ready (),
+      .offload_sdi_data ());
+
+    spi_engine_interconnect #(
+      .SDI_DATA_WIDTH ()
+    ) i_spi_engine_interconnect (
+      .clk (up_clk),
+      .resetn (spi_resetn_s),
+      .m_cmd_valid (),
+      .m_cmd_ready (),
+      .m_cmd_data (),
+      .m_sdo_valid (),
+      .m_sdo_ready (),
+      .m_sdo_data (),
+      .m_sdi_valid (),
+      .m_sdi_ready (),
+      .m_sdi_data (),
+      .m_sync_valid (),
+      .m_sync_ready (),
+      .m_sync (),
+      .s0_cmd_valid (),
+      .s0_cmd_ready (),
+      .s0_cmd_data (),
+      .s0_sdo_valid (),
+      .s0_sdo_ready (),
+      .s0_sdo_data (),
+      .s0_sdi_valid (),
+      .s0_sdi_ready (),
+      .s0_sdi_data (),
+      .s0_sync_valid (),
+      .s0_sync_ready (),
+      .s0_sync (),
+      .s1_cmd_valid (),
+      .s1_cmd_ready (),
+      .s1_cmd_data (),
+      .s1_sdo_valid (),
+      .s1_sdo_ready (),
+      .s1_sdo_data (),
+      .s1_sdi_valid (),
+      .s1_sdi_ready (),
+      .s1_sdi_data (),
+      .s1_sync_valid (),
+      .s1_sync_ready (),
+      .s1_sync ());
+
+    spi_engine_execution #(
+      .SDI_DATA_WIDTH()
+    ) i_spi_engine_execution (
+      .clk (up_clk),
+      .resetn (spi_resetn_s),
+      .active (),
+      .cmd_ready (),
+      .cmd_valid (),
+      .cmd (),
+      .sdo_data_valid (),
+      .sdo_data_ready (),
+      .sdo_data (),
+      .sdi_data_ready (),
+      .sdi_data_valid (),
+      .sdi_data (),
+      .sync_ready (),
+      .sync_valid (),
+      .sync (),
+      .sclk (),
+      .sdo (),
+      .sdo_t (),
+      .sdi (),
+      .sdi_1 (),
+      .sdi_2 (),
+      .sdi_3 (),
+      .cs (),
+      .three_wire ());
+
+  end
+
   // up bus interface
 
   up_axi i_up_axi (

From d6eae81bc165f9995b4d1de8ed90a62ebdf1e2b5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 13 Nov 2015 18:14:21 +0200
Subject: [PATCH 008/972] axi_ad7616: Add the control module to the core,
 finish up SPI integration

---
 library/axi_ad7616/axi_ad7616.v         | 313 +++++++++++++++---------
 library/axi_ad7616/axi_ad7616_control.v | 240 ++++++++++++++++++
 library/common/ad_edge_detect.v         |  89 +++++++
 3 files changed, 531 insertions(+), 111 deletions(-)
 create mode 100644 library/axi_ad7616/axi_ad7616_control.v
 create mode 100644 library/common/ad_edge_detect.v

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 28b9c6f61..83f4abfde 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -93,8 +93,9 @@ module axi_ad7616 (
 
   m_axis_tdata,
   m_axis_tvalid,
-  m_axis_tready
+  m_axis_tready,
 
+  irq
 );
 
   // parameters
@@ -103,11 +104,12 @@ module axi_ad7616 (
   parameter       OP_MODE = 0;
   parameter       IF_TYPE = 0;
 
-  localparam      PCORE_VERSION = 'h0001001;
-  localparam      SW = 0;
-  localparam      HW = 1;
+  // local parameters
+
+  localparam      SDI_DATA_WIDTH = 16;
   localparam      SERIAL = 0;
   localparam      PARALLEL = 1;
+  localparam      NEG_EDGE = 1;
 
   // IO definitions
 
@@ -124,7 +126,7 @@ module axi_ad7616 (
 
   output          reset_n;
   output          cnvst;
-  output          busy;
+  input           busy;
   output          seq_en;
   output  [ 1:0]  hw_rngsel;
   output  [ 2:0]  chsel;
@@ -133,7 +135,6 @@ module axi_ad7616 (
   output          burst;
   output  [ 2:0]  os;
 
-
   input           s_axi_aclk;
   input           s_axi_aresetn;
   input           s_axi_awvalid;
@@ -158,11 +159,16 @@ module axi_ad7616 (
   input           m_axis_tready;
   output          m_axis_tvalid;
 
+  output          irq;
+
   // internal registers
 
 
   // internal signals
 
+  wire            up_clk;
+  wire            up_rstn;
+  wire            up_rst;
   wire            up_rreq_s;
   wire    [13:0]  up_raddr_s;
   wire    [31:0]  up_rdata_s[0:2];
@@ -176,14 +182,67 @@ module axi_ad7616 (
 
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
+  assign up_rst = ~s_axi_aresetn;
 
-  generate if (IF_TYPE == 0) begin
+  generate if (IF_TYPE == SERIAL) begin
 
-    wire spi_resetn_s;
+    // ground all parallel interface signals
+
+    assign db_o = 16'b0;
+    assign rd_n = 1'b0;
+    assign wr_n = 1'b0;
+
+    // all the SPI Framework instances and logic
+
+    wire                          spi_resetn_s;
+    wire                          s0_cmd_ready_s;
+    wire                          s0_cmd_valid_s;
+    wire  [15:0]                  s0_cmd_data_s;
+    wire                          s0_sdo_data_ready_s;
+    wire                          s0_sdo_data_valid_s;
+    wire  [ 7:0]                  s0_sdo_data_s;
+    wire                          s0_sdi_data_ready_s;
+    wire                          s0_sdi_data_valid_s;
+    wire  [(SDI_DATA_WIDTH-1):0]  s0_sdi_data_s;
+    wire                          s0_sync_ready_s;
+    wire                          s0_sync_valid_s;
+    wire  [ 7:0]                  s0_sync_data_s;
+    wire                          s1_cmd_ready_s;
+    wire                          s1_cmd_valid_s;
+    wire  [15:0]                  s1_cmd_data_s;
+    wire                          s1_sdo_data_ready_s;
+    wire                          s1_sdo_data_valid_s;
+    wire  [ 7:0]                  s1_sdo_data_s;
+    wire                          s1_sdi_data_ready_s;
+    wire                          s1_sdi_data_valid_s;
+    wire  [(SDI_DATA_WIDTH-1):0]  s1_sdi_data_s;
+    wire                          s1_sync_ready_s;
+    wire                          s1_sync_valid_s;
+    wire  [ 7:0]                  s1_sync_data_s;
+    wire                          m_cmd_ready_s;
+    wire                          m_cmd_valid_s;
+    wire  [15:0]                  m_cmd_data_s;
+    wire                          m_sdo_data_ready_s;
+    wire                          m_sdo_data_valid_s;
+    wire  [ 7:0]                  m_sdo_data_s;
+    wire                          m_sdi_data_ready_s;
+    wire                          m_sdi_data_valid_s;
+    wire  [(SDI_DATA_WIDTH-1):0]  m_sdi_data_s;
+    wire                          m_sync_ready_s;
+    wire                          m_sync_valid_s;
+    wire  [ 7:0]                  m_sync_data_s;
+    wire                          offload0_cmd_wr_en_s;
+    wire                          offload0_cmd_wr_data_s;
+    wire                          offload0_sdo_wr_en_s;
+    wire                          offload0_sdo_wr_data_s;
+    wire                          offload0_mem_reset_s;
+    wire                          offload0_enable_s;
+    wire                          offload0_enabled_s;
+    wire                          trigger_s;
 
     axi_spi_engine #(
-      .SDI_DATA_WIDTH(),
-      .NUM_OFFLOAD()
+      .SDI_DATA_WIDTH (SDI_DATA_WIDTH),
+      .NUM_OFFLOAD(1)
     ) i_axi_spi_engine(
       .s_axi_aclk (up_clk),
       .s_axi_aresetn (up_rstn),
@@ -204,130 +263,162 @@ module axi_ad7616 (
       .s_axi_rready (s_axi_rready),
       .s_axi_rresp (s_axi_rresp),
       .s_axi_rdata (s_axi_rdata),
-      .irq (),
+      .irq (irq),
       .spi_clk (up_clk),
       .spi_resetn (spi_resetn_s),
-      .cmd_ready (),
-      .cmd_valid (),
-      .cmd_data (),
-      .sdo_data_ready (),
-      .sdo_data_valid (),
-      .sdo_data (),
-      .sdi_data_ready (),
-      .sdi_data_valid (),
-      .sdi_data (),
-      .sync_ready (),
-      .sync_valid (),
-      .sync_data (),
-      .offload0_cmd_wr_en (),
-      .offload0_cmd_wr_data (),
-      .offload0_sdo_wr_en (),
-      .offload0_sdo_wr_data (),
-      .offload0_mem_reset (),
-      .offload0_enable (),
-      .offload0_enabled());
+      .cmd_ready (s0_cmd_ready_s),
+      .cmd_valid (s0_cmd_valid_s),
+      .cmd_data (s0_cmd_data_s),
+      .sdo_data_ready (s0_sdo_data_ready_s),
+      .sdo_data_valid (s0_sdo_data_valid_s),
+      .sdo_data (s0_sdo_data_s),
+      .sdi_data_ready (s0_sdi_data_ready_s),
+      .sdi_data_valid (s0_sdi_data_valid_s),
+      .sdi_data (s0_sdi_data_s),
+      .sync_ready (s0_sync_ready_s),
+      .sync_valid (s0_sync_valid_s),
+      .sync_data (s0_sync_data_s),
+      .offload0_cmd_wr_en (offload0_cmd_wr_en_s),
+      .offload0_cmd_wr_data (offload0_cmd_wr_data_s),
+      .offload0_sdo_wr_en (offload0_sdo_wr_en_s),
+      .offload0_sdo_wr_data (offload0_sdo_wr_data_s),
+      .offload0_mem_reset (offload0_mem_reset_s),
+      .offload0_enable (offload0_enable_s),
+      .offload0_enabled(offload0_enabled_s));
 
     spi_engine_offload #(
-      .SDI_DATA_WIDTH()
+      .SDI_DATA_WIDTH (SDI_DATA_WIDTH)
     ) i_spi_engine_offload(
-      .ctrl_clk (),
-      .ctrl_cmd_wr_en (),
-      .ctrl_cmd_wr_data (),
-      .ctrl_sdo_wr_en (),
-      .ctrl_sdo_wr_data (),
-      .ctrl_enable (),
-      .ctrl_enabled (),
-      .ctrl_mem_reset (),
+      .ctrl_clk (up_clk),
+      .ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
+      .ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
+      .ctrl_sdo_wr_en (offload0_sdo_wr_en_s),
+      .ctrl_sdo_wr_data (offload0_sdo_wr_data_s),
+      .ctrl_enable (offload0_enable_s),
+      .ctrl_enabled (offload0_enabled_s),
+      .ctrl_mem_reset (offload0_mem_reset_s),
       .spi_clk (up_clk),
       .spi_resetn (spi_resetn_s),
-      .trigger (),
-      .cmd_valid (),
-      .cmd_ready (),
-      .cmd (),
-      .sdo_data_valid (),
-      .sdo_data_ready (),
-      .sdo_data (),
-      .sdi_data_ready (),
-      .sdi_data (),
-      .sync_valid (),
-      .sync_ready (),
-      .sync_data (),
-      .offload_sdi_valid (),
-      .offload_sdi_ready (),
-      .offload_sdi_data ());
+      .trigger (trigger_s),
+      .cmd_valid (s1_cmd_valid_s),
+      .cmd_ready (s1_cmd_ready_s),
+      .cmd (s1_cmd_data_s),
+      .sdo_data_valid (s1_sdo_data_valid_s),
+      .sdo_data_ready (s1_sdo_data_ready_s),
+      .sdo_data (s1_sdo_data_s),
+      .sdi_data_valid (s1_sdi_data_valid_s),
+      .sdi_data_ready (s1_sdi_data_ready_s),
+      .sdi_data (s1_sdi_data_s),
+      .sync_valid (s1_sync_valid_s),
+      .sync_ready (s1_sync_ready_s),
+      .sync_data (s1_sync_data_s),
+      .offload_sdi_valid (m_axis_tvalid),
+      .offload_sdi_ready (m_axis_tready),
+      .offload_sdi_data (m_axis_tdata));
 
     spi_engine_interconnect #(
-      .SDI_DATA_WIDTH ()
+      .SDI_DATA_WIDTH (SDI_DATA_WIDTH)
     ) i_spi_engine_interconnect (
       .clk (up_clk),
       .resetn (spi_resetn_s),
-      .m_cmd_valid (),
-      .m_cmd_ready (),
-      .m_cmd_data (),
-      .m_sdo_valid (),
-      .m_sdo_ready (),
-      .m_sdo_data (),
-      .m_sdi_valid (),
-      .m_sdi_ready (),
-      .m_sdi_data (),
-      .m_sync_valid (),
-      .m_sync_ready (),
-      .m_sync (),
-      .s0_cmd_valid (),
-      .s0_cmd_ready (),
-      .s0_cmd_data (),
-      .s0_sdo_valid (),
-      .s0_sdo_ready (),
-      .s0_sdo_data (),
-      .s0_sdi_valid (),
-      .s0_sdi_ready (),
-      .s0_sdi_data (),
-      .s0_sync_valid (),
-      .s0_sync_ready (),
-      .s0_sync (),
-      .s1_cmd_valid (),
-      .s1_cmd_ready (),
-      .s1_cmd_data (),
-      .s1_sdo_valid (),
-      .s1_sdo_ready (),
-      .s1_sdo_data (),
-      .s1_sdi_valid (),
-      .s1_sdi_ready (),
-      .s1_sdi_data (),
-      .s1_sync_valid (),
-      .s1_sync_ready (),
-      .s1_sync ());
+      .m_cmd_valid (m_cmd_valid_s),
+      .m_cmd_ready (m_cmd_ready_s),
+      .m_cmd_data (m_cmd_data_s),
+      .m_sdo_valid (m_sdo_valid_s),
+      .m_sdo_ready (m_sdo_ready_s),
+      .m_sdo_data (m_sdo_data_s),
+      .m_sdi_valid (m_sdi_valid_s),
+      .m_sdi_ready (m_sdi_ready_s),
+      .m_sdi_data (m_sdi_data_s),
+      .m_sync_valid (m_sync_valid_s),
+      .m_sync_ready (m_sync_ready_s),
+      .m_sync (m_sync_s),
+      .s0_cmd_valid (s0_cmd_valid_s),
+      .s0_cmd_ready (s0_cmd_ready_s),
+      .s0_cmd_data (s0_cmd_data_s),
+      .s0_sdo_valid (s0_sdo_data_valid_s),
+      .s0_sdo_ready (s0_sdi_data_ready_s),
+      .s0_sdo_data (s0_sdo_data_s),
+      .s0_sdi_valid (s0_sdi_data_valid_s),
+      .s0_sdi_ready (s0_sdi_data_ready_s),
+      .s0_sdi_data (s0_sdi_data_s),
+      .s0_sync_valid (s0_sync_valid_s),
+      .s0_sync_ready (s0_sync_ready_s),
+      .s0_sync (s0_sync_data_s),
+      .s1_cmd_valid (s1_cmd_valid_s),
+      .s1_cmd_ready (s1_cmd_ready_s),
+      .s1_cmd_data (s1_cmd_data_s),
+      .s1_sdo_valid (s1_sdo_valid_s),
+      .s1_sdo_ready (s1_sdo_ready_s),
+      .s1_sdo_data (s1_sdo_data_s),
+      .s1_sdi_valid (s1_sdi_valid_s),
+      .s1_sdi_ready (s1_sdi_ready_s),
+      .s1_sdi_data (s1_sdi_data_s),
+      .s1_sync_valid (s1_sync_valid_s),
+      .s1_sync_ready (s1_sync_ready_s),
+      .s1_sync (s1_sync_s));
 
     spi_engine_execution #(
-      .SDI_DATA_WIDTH()
+      .SDI_DATA_WIDTH (SDI_DATA_WIDTH)
     ) i_spi_engine_execution (
       .clk (up_clk),
       .resetn (spi_resetn_s),
       .active (),
-      .cmd_ready (),
-      .cmd_valid (),
-      .cmd (),
-      .sdo_data_valid (),
-      .sdo_data_ready (),
-      .sdo_data (),
-      .sdi_data_ready (),
-      .sdi_data_valid (),
-      .sdi_data (),
-      .sync_ready (),
-      .sync_valid (),
-      .sync (),
-      .sclk (),
-      .sdo (),
+      .cmd_ready (m_cmd_ready_s),
+      .cmd_valid (m_cmd_valid_s),
+      .cmd (m_cmd_data_s),
+      .sdo_data_valid (m_sdo_data_valid_s),
+      .sdo_data_ready (m_sdo_data_ready_s),
+      .sdo_data (m_sdo_data_s),
+      .sdi_data_ready (m_sdi_data_ready_s),
+      .sdi_data_valid (m_sdi_data_valid_s),
+      .sdi_data (m_sdi_data_s),
+      .sync_ready (m_sync_ready_s),
+      .sync_valid (m_sync_valid_s),
+      .sync (m_sync_data_s),
+      .sclk (sclk),
+      .sdo (sdo),
       .sdo_t (),
-      .sdi (),
-      .sdi_1 (),
-      .sdi_2 (),
-      .sdi_3 (),
-      .cs (),
+      .sdi (sdi_0),
+      .sdi_1 (sdi_1),
+      .sdi_2 (1'b0),
+      .sdi_3 (1'b0),
+      .cs (cs_n),
       .three_wire ());
 
   end
 
+  generate if (IF_TYPE == PARALLEL) begin
+
+  end
+  endgenerate
+
+  axi_ad7616_control #(
+    .ID(ID),
+    .OP_MODE (OP_MODE)
+  ) i_ad7616_control (
+    .reset_n (reset_n),
+    .cnvst (cnvst),
+    .busy (busy),
+    .seq_en (seq_en),
+    .hw_rngsel (hw_rngsel),
+    .chsel (chsel),
+    .crcen (crcen),
+    .ser1w_n (ser1w_n),
+    .burst (burst),
+    .os (os),
+    .end_of_conv (trigger_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s),
+    .up_rack (up_rack_s));
+
   // up bus interface
 
   up_axi i_up_axi (
diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
new file mode 100644
index 000000000..4d396ebb8
--- /dev/null
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -0,0 +1,240 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad7616_control (
+
+  // control signals
+
+  reset_n,
+  cnvst,
+  busy,
+  seq_en,
+  hw_rngsel,
+  chsel,
+  crcen,
+  ser1w_n,
+  burst,
+  os,
+
+  end_of_conv,
+
+  // bus interface
+
+  up_rstn,
+  up_clk,
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack
+
+);
+
+  parameter   ID = 0;
+  parameter   OP_MODE = 0;
+
+  localparam  PCORE_VERSION = 'h0001001;
+  localparam  SW = 0;
+  localparam  HW = 1;
+
+  input           clk;
+  input           rst;
+
+  output          reset_n;
+  output          cnvst;
+  input           busy;
+  output          seq_en;
+  output  [ 1:0]  hw_rngsel;
+  output  [ 2:0]  chsel;
+  output          crcen;
+  output          ser1w_n;
+  output          burst;
+  output  [ 2:0]  os;
+
+  output          end_of_conv;
+
+  // bus interface
+
+  input           up_rstn;
+  input           up_clk;
+  input           up_wreq;
+  input   [13:0]  up_waddr;
+  input   [31:0]  up_wdata;
+  output          up_wack;
+  input           up_rreq;
+  input   [13:0]  up_raddr;
+  output  [31:0]  up_rdata;
+  output          up_rack;
+
+  // internal signals
+
+  reg     [31:0]  up_scratch = 'b0;
+  reg             up_resetn = 'b0;
+  reg             up_cnvst_en = 'b0;
+  reg             up_ser1w = 'b0;
+  reg     [ 7:0]  up_cnvst_high = 'b0;
+  reg     [31:0]  up_conv_rate = 'b0;
+  reg     [31:0]  cnvst_counter = 32'b0;
+  reg     [ 7:0]  pulse_counter = 8'b0;
+  reg             cnvst_buf = 1'b0;
+
+  // decode block select
+
+
+  // processor write interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 1'h0;
+      up_scratch <= 32'b0;
+      up_resetn <= 1'b0;
+      up_cnvst_en <= 1'b0;
+      up_ser1w <= 1'b0;
+      up_cnvst_high <= 8'b0;
+      up_conv_rate <= 32'b0;
+    end else begin
+      up_wack <= up_wreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
+        up_scratch <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
+        up_resetn <= up_wdata[0];
+        up_cnvst_en <= up_wdata[1];
+        up_ser1w <= up_wdata[2];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
+        up_cnvst_high <= up_wdata[7:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
+        up_conv_rate <= up_wdata;
+      end
+    end
+  end
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rack <= 1'b0;
+      up_rdata <= 32'b0;
+    end else begin
+      up_rack <= up_rreq_s;
+      if (up_rreq_s == 1'b1) begin
+        case (up_raddr[7:0])
+            8'h00 : up_rdata = PCORE_VERSION;
+            8'h01 : up_rdata = ID;
+            8'h02 : up_rdata = up_scratch;
+            8'h10 : up_rdata = {28'b0, up_ser1w, up_cnvst_en, up_resetn};
+            8'h11 : up_rdata = {24'b0, up_cnvst_high};
+            8'h12 : up_rdata = up_conv_rate;
+        endcase
+      end
+    end
+  end
+
+  // instantiations
+
+  ad_edge_detect #(
+    .EDGE(NEG_EDGE)
+  ) i_ad_edge_detect (
+    .clk (up_clk),
+    .rstn (up_rstn),
+    .in (busy),
+    .out (end_of_conv)
+  );
+
+  // convertion start generator
+  // NOTE: The minimum convertion cycle is 1 us and the
+  //       minimum CNVST high pulse width is 20 ns.
+  //       See the AD7616 datasheet for more information.
+
+  always @(posedge clk) begin
+    if(up_resetn == 0) begin
+      cnvst_counter <= 32'b0;
+    end else begin
+      cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
+    end
+  end
+
+  always @(cnvst_counter) begin
+    cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
+  end
+
+  always @(posedge clk) begin
+    if(up_resetn == 1'b0) begin
+      pulse_counter <= 8'b0;
+      cnvst_buf <= 1'b0;
+    end else begin
+      pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 8'b0;
+      if(cnvst_pulse == 1'b1) begin
+        cnvst_buf <= 1'b1;
+      end else if (pulse_counter == up_cnvst_high) begin
+        cnvst_buf <= 1'b0;
+      end
+    end
+  end
+
+  assign cnvst <= (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
+
+  // output logic
+
+  assign reset_n = up_resetn;       // device's reset
+  assign ser1w_n = ~up_ser1w;       // serial output operates over SDOA and SDOB OR just SDOA
+
+  generate if (OP_MODE == SW) begin
+
+    // ground all the unused control signals
+
+    assign seq_en = 1'b0;
+    assign hw_rngsel = 2'b0;
+    assign chsel = 3'b0;
+    assign crcen = 1'b0;
+    assign burst = 1'b0;
+    assign os = 3'b0;
+
+  end
+  endgenerate
+
+endmodule
+
diff --git a/library/common/ad_edge_detect.v b/library/common/ad_edge_detect.v
new file mode 100644
index 000000000..3671123c8
--- /dev/null
+++ b/library/common/ad_edge_detect.v
@@ -0,0 +1,89 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+// A simple edge detector circuit
+
+`timescale 1ns/100ps
+
+module ad_edge_detect (
+
+  clk,
+  rst,
+
+  in,
+  out
+);
+
+  parameter   EDGE = 0;
+
+  localparam  POS_EDGE = 0;
+  localparam  NEG_EDGE = 1;
+  localparam  ANY_EDGE = 2;
+
+  input       clk;
+  input       rstn;
+
+  input       in;
+  output      out;
+
+  reg         ff_m1 = 0;
+  reg         ff_m2 = 0;
+
+  always @(posedge clk) begin
+    if (rstn == 1) begin
+      ff_m1 <= 0;
+      ff_m2 <= 0;
+    end else begin
+      ff_m1 <= in;
+      ff_m2 <= ff_m1;
+    end
+  end
+
+  generate
+    if (EDGE == POS_EDGE) begin
+      assign out = ff_m1 & ~ff_m2;
+    end else if (EDGE == NEG_EDGE) begin
+      assign out = ~ff_m1 & ff_m2;
+    end else begin
+      assign out = ff_m1 ^ ff_m2;
+    end
+  endgenerate
+
+endmodule
+

From 5cf45b2978fee66b27f1cd1d7794b408bece1f11 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 2 Dec 2015 18:50:23 +0200
Subject: [PATCH 009/972] axi_clkgen: Added phase related parameters

---
 library/axi_clkgen/axi_clkgen.v |  6 +++++-
 library/common/ad_mmcm_drp.v    | 10 ++++++----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v
index eabe5564e..296f94b02 100644
--- a/library/axi_clkgen/axi_clkgen.v
+++ b/library/axi_clkgen/axi_clkgen.v
@@ -76,7 +76,9 @@ module axi_clkgen (
   parameter   VCO_DIV = 11;
   parameter   VCO_MUL = 49;
   parameter   CLK0_DIV = 6;
+  parameter   CLK0_PHASE = 0.000;
   parameter   CLK1_DIV = 6;
+  parameter   CLK1_PHASE = 0.000;
 
   // clocks
 
@@ -200,7 +202,9 @@ module axi_clkgen (
     .MMCM_VCO_DIV (VCO_DIV),
     .MMCM_VCO_MUL (VCO_MUL),
     .MMCM_CLK0_DIV (CLK0_DIV),
-    .MMCM_CLK1_DIV (CLK1_DIV))
+    .MMCM_CLK0_PHASE (CLK0_PHASE),
+    .MMCM_CLK1_DIV (CLK1_DIV),
+    .MMCM_CLK1_PHASE (CLK1_PHASE))
   i_mmcm_drp (
     .clk (clk),
     .clk2 (clk2),
diff --git a/library/common/ad_mmcm_drp.v b/library/common/ad_mmcm_drp.v
index e423ad03b..3c9cf2302 100644
--- a/library/common/ad_mmcm_drp.v
+++ b/library/common/ad_mmcm_drp.v
@@ -72,7 +72,9 @@ module ad_mmcm_drp (
   parameter   MMCM_VCO_DIV  = 6;
   parameter   MMCM_VCO_MUL = 12.000;
   parameter   MMCM_CLK0_DIV = 2.000;
+  parameter   MMCM_CLK0_PHASE = 0.000 ;
   parameter   MMCM_CLK1_DIV = 6;
+  parameter   MMCM_CLK1_PHASE = 0.000;
 
   // clocks
 
@@ -143,11 +145,11 @@ module ad_mmcm_drp (
     .CLKFBOUT_PHASE (0.000),
     .CLKFBOUT_USE_FINE_PS ("FALSE"),
     .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
-    .CLKOUT0_PHASE (0.000),
+    .CLKOUT0_PHASE (MMCM_CLK0_PHASE),
     .CLKOUT0_DUTY_CYCLE (0.500),
     .CLKOUT0_USE_FINE_PS ("FALSE"),
     .CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
-    .CLKOUT1_PHASE (0.000),
+    .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
     .CLKOUT1_DUTY_CYCLE (0.500),
     .CLKOUT1_USE_FINE_PS ("FALSE"),
     .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
@@ -200,11 +202,11 @@ module ad_mmcm_drp (
     .CLKFBOUT_PHASE (0.000),
     .CLKFBOUT_USE_FINE_PS ("FALSE"),
     .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
-    .CLKOUT0_PHASE (0.000),
+    .CLKOUT0_PHASE (MMCM_CLK0_PHASE),
     .CLKOUT0_DUTY_CYCLE (0.500),
     .CLKOUT0_USE_FINE_PS ("FALSE"),
     .CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
-    .CLKOUT1_PHASE (0.000),
+    .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
     .CLKOUT1_DUTY_CYCLE (0.500),
     .CLKOUT1_USE_FINE_PS ("FALSE"),
     .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),

From 12c95b059d3b19ebea76a9019418b08271ed6d1b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 3 Dec 2015 11:13:56 +0200
Subject: [PATCH 010/972] ad_tdd_control: Remove tdd_enable_synced control line

For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
---
 library/axi_ad9361/axi_ad9361.v     | 33 ++++++++++++++---
 library/axi_ad9361/axi_ad9361_tdd.v | 55 +++++++++++++++++++----------
 library/common/ad_tdd_control.v     | 11 ------
 3 files changed, 65 insertions(+), 34 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 4351f22b7..5e30d4840 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -284,6 +284,12 @@ module axi_ad9361 (
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
 
+  reg     [15:0]  adc_data_i0 = 16'b0;
+  reg     [15:0]  adc_data_q0 = 16'b0;
+  reg     [15:0]  adc_data_i1 = 16'b0;
+  reg     [15:0]  adc_data_q1 = 16'b0;
+
+
   // internal clocks and resets
 
   wire            up_clk;
@@ -333,6 +339,10 @@ module axi_ad9361 (
   wire            tdd_txnrx_s;
   wire            tdd_mode_s;
 
+  wire    [15:0]  adc_data_i0_s;
+  wire    [15:0]  adc_data_q0_s;
+  wire    [15:0]  adc_data_i1_s;
+  wire    [15:0]  adc_data_q1_s;
 
   // signal name changes
 
@@ -403,6 +413,21 @@ module axi_ad9361 (
 
   // TDD interface
 
+  // additional flop to keep control and data synced
+  always @(posedge clk) begin
+    if(rst == 1) begin
+      adc_data_i0 <= 16'b0;
+      adc_data_q0 <= 16'b0;
+      adc_data_i1 <= 16'b0;
+      adc_data_q1 <= 16'b0;
+    end else begin
+      adc_data_i0 <= adc_data_i0_s;
+      adc_data_q0 <= adc_data_q0_s;
+      adc_data_i1 <= adc_data_i1_s;
+      adc_data_q1 <= adc_data_q1_s;
+    end
+  end
+
   axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
     .clk (clk),
     .rst (rst),
@@ -478,16 +503,16 @@ module axi_ad9361 (
     .delay_locked (delay_locked_s),
     .adc_enable_i0 (adc_enable_i0),
     .adc_valid_i0 (adc_valid_i0_s),
-    .adc_data_i0 (adc_data_i0),
+    .adc_data_i0 (adc_data_i0_s),
     .adc_enable_q0 (adc_enable_q0),
     .adc_valid_q0 (adc_valid_q0_s),
-    .adc_data_q0 (adc_data_q0),
+    .adc_data_q0 (adc_data_q0_s),
     .adc_enable_i1 (adc_enable_i1),
     .adc_valid_i1 (adc_valid_i1_s),
-    .adc_data_i1 (adc_data_i1),
+    .adc_data_i1 (adc_data_i1_s),
     .adc_enable_q1 (adc_enable_q1),
     .adc_valid_q1 (adc_valid_q1_s),
-    .adc_data_q1 (adc_data_q1),
+    .adc_data_q1 (adc_data_q1_s),
     .adc_dovf (adc_dovf),
     .adc_dunf (adc_dunf),
     .up_adc_gpio_in (up_adc_gpio_in),
diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index 914ad1f6d..63771d9b3 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -160,11 +160,19 @@ module axi_ad9361_tdd (
 
   reg               tdd_slave_synced = 1'b0;
 
+  reg               tdd_tx_valid_i0 = 1'b0;
+  reg               tdd_tx_valid_q0 = 1'b0;
+  reg               tdd_tx_valid_i1 = 1'b0;
+  reg               tdd_tx_valid_q1 = 1'b0;
+  reg               tdd_rx_valid_i0 = 1'b0;
+  reg               tdd_rx_valid_q0 = 1'b0;
+  reg               tdd_rx_valid_i1 = 1'b0;
+  reg               tdd_rx_valid_q1 = 1'b0;
+
   // internal signals
 
   wire              rst;
   wire              tdd_enable_s;
-  wire              tdd_enable_synced_s;
   wire              tdd_secondary_s;
   wire    [ 7:0]    tdd_burst_count_s;
   wire              tdd_rx_only_s;
@@ -205,25 +213,35 @@ module axi_ad9361_tdd (
 
   // tx/rx data flow control
 
-  assign  tdd_tx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
-                                    (tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0;
-  assign  tdd_tx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
-                                    (tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0;
-  assign  tdd_tx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
-                                    (tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1;
-  assign  tdd_tx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
-                                    (tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1;
+  always @(posedge clk) begin
+    if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
+      tdd_tx_valid_i0 <= tx_valid_i0 & tdd_tx_dp_en_s;
+      tdd_tx_valid_q0 <= tx_valid_q0 & tdd_tx_dp_en_s;
+      tdd_tx_valid_i1 <= tx_valid_i1 & tdd_tx_dp_en_s;
+      tdd_tx_valid_q1 <= tx_valid_q1 & tdd_tx_dp_en_s;
+    end else begin
+      tdd_tx_valid_i0 <= tx_valid_i0;
+      tdd_tx_valid_q0 <= tx_valid_q0;
+      tdd_tx_valid_i1 <= tx_valid_i1;
+      tdd_tx_valid_q1 <= tx_valid_q1;
+    end
+  end
 
-  assign  tdd_rx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
-                                    (rx_valid_i0 & tdd_rx_rf_en) : rx_valid_i0;
-  assign  tdd_rx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
-                                    (rx_valid_q0 & tdd_rx_rf_en) : rx_valid_q0;
-  assign  tdd_rx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
-                                    (rx_valid_i1 & tdd_rx_rf_en) : rx_valid_i1;
-  assign  tdd_rx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
-                                    (rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1;
+  always @(posedge clk) begin
+    if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
+      tdd_rx_valid_i0 <= rx_valid_i0 & tdd_rx_rf_en;
+      tdd_rx_valid_q0 <= rx_valid_q0 & tdd_rx_rf_en;
+      tdd_rx_valid_i1 <= rx_valid_i1 & tdd_rx_rf_en;
+      tdd_rx_valid_q1 <= rx_valid_q1 & tdd_rx_rf_en;
+    end else begin
+      tdd_rx_valid_i0 <= rx_valid_i0;
+      tdd_rx_valid_q0 <= rx_valid_q0;
+      tdd_rx_valid_i1 <= rx_valid_i1;
+      tdd_rx_valid_q1 <= rx_valid_q1;
+    end
+  end
 
-  assign  tdd_enabled = tdd_enable_synced_s;
+  assign  tdd_enabled = tdd_enable_s;
   assign  tdd_terminal_type = ~tdd_terminal_type_s;
 
   // instantiations
@@ -284,7 +302,6 @@ module axi_ad9361_tdd (
     .clk(clk),
     .rst(rst),
     .tdd_enable(tdd_enable_s),
-    .tdd_enable_synced (tdd_enable_synced_s),
     .tdd_secondary(tdd_secondary_s),
     .tdd_counter_init(tdd_counter_init_s),
     .tdd_frame_length(tdd_frame_length_s),
diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v
index 328c9c6b0..b961e0cf2 100644
--- a/library/common/ad_tdd_control.v
+++ b/library/common/ad_tdd_control.v
@@ -49,7 +49,6 @@ module ad_tdd_control(
   // TDD timming signals
 
   tdd_enable,
-  tdd_enable_synced,
   tdd_secondary,
   tdd_tx_only,
   tdd_rx_only,
@@ -103,7 +102,6 @@ module ad_tdd_control(
   input           rst;
 
   input           tdd_enable;
-  output          tdd_enable_synced;
   input           tdd_secondary;
   input           tdd_tx_only;
   input           tdd_rx_only;
@@ -179,7 +177,6 @@ module ad_tdd_control(
   reg             counter_at_tdd_tx_dp_on_2 = 1'b0;
   reg             counter_at_tdd_tx_dp_off_2 = 1'b0;
 
-  reg             tdd_enable_synced = 1'h0;
   reg             tdd_last_burst = 1'b0;
 
   reg             tdd_sync_d1 = 1'b0;
@@ -232,14 +229,6 @@ module ad_tdd_control(
     end
   end
 
-  always @(posedge clk) begin
-    if (rst == 1'b1) begin
-      tdd_enable_synced <= 1'b0;
-    end else begin
-      tdd_enable_synced <= ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) ? tdd_enable : tdd_enable_synced;
-    end
-  end
-
   // ***************************************************************************
   // tdd counter (state machine)
   // ***************************************************************************

From 0938041d972713f2e956d089a006ca197c411c4c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 7 Dec 2015 13:07:03 -0500
Subject: [PATCH 011/972] ad7768evb: added

---
 projects/ad7768evb/Makefile                |  21 +
 projects/ad7768evb/common/ad7768_if.v      | 553 +++++++++++++++++++++
 projects/ad7768evb/common/ad7768evb_bd.tcl |  62 +++
 projects/ad7768evb/zed/Makefile            |  78 +++
 projects/ad7768evb/zed/system_bd.tcl       |   4 +
 projects/ad7768evb/zed/system_constr.xdc   |  29 ++
 projects/ad7768evb/zed/system_project.tcl  |  15 +
 projects/ad7768evb/zed/system_top.v        | 341 +++++++++++++
 8 files changed, 1103 insertions(+)
 create mode 100644 projects/ad7768evb/Makefile
 create mode 100644 projects/ad7768evb/common/ad7768_if.v
 create mode 100644 projects/ad7768evb/common/ad7768evb_bd.tcl
 create mode 100644 projects/ad7768evb/zed/Makefile
 create mode 100644 projects/ad7768evb/zed/system_bd.tcl
 create mode 100644 projects/ad7768evb/zed/system_constr.xdc
 create mode 100644 projects/ad7768evb/zed/system_project.tcl
 create mode 100644 projects/ad7768evb/zed/system_top.v

diff --git a/projects/ad7768evb/Makefile b/projects/ad7768evb/Makefile
new file mode 100644
index 000000000..141f88d2a
--- /dev/null
+++ b/projects/ad7768evb/Makefile
@@ -0,0 +1,21 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+.PHONY: all clean clean-all 
+all:
+	-make -C zed all
+
+
+clean: 
+	make -C zed clean
+
+
+clean-all:
+	make -C zed clean-all
+
+####################################################################################
+####################################################################################
diff --git a/projects/ad7768evb/common/ad7768_if.v b/projects/ad7768evb/common/ad7768_if.v
new file mode 100644
index 000000000..c51f44e04
--- /dev/null
+++ b/projects/ad7768evb/common/ad7768_if.v
@@ -0,0 +1,553 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad7768_if (
+
+  // device-interface
+
+  clk_in,
+  ready_in,
+  data_in,
+
+  // data path interface
+
+  adc_clk,
+  adc_valid,
+  adc_data,
+
+  // control interface
+
+  up_sshot,
+  up_format,
+  up_crc_enable,
+  up_crc_4_or_16_n,
+  up_status_clr,
+  up_status);
+
+  // device-interface
+
+  input             clk_in;
+  input             ready_in;
+  input   [  7:0]   data_in;
+
+  // data path interface
+
+  output            adc_clk;
+  output            adc_valid;
+  output  [ 31:0]   adc_data;
+
+  // control interface
+
+  input             up_sshot;
+  input   [  1:0]   up_format;
+  input             up_crc_enable;
+  input             up_crc_4_or_16_n;
+  input   [ 35:0]   up_status_clr;
+  output  [ 35:0]   up_status;
+
+  // internal registers
+
+  reg     [  1:0]   adc_status_8 = 'd0;
+  reg     [  2:0]   adc_status_7 = 'd0;
+  reg     [  2:0]   adc_status_6 = 'd0;
+  reg     [  2:0]   adc_status_5 = 'd0;
+  reg     [  2:0]   adc_status_4 = 'd0;
+  reg     [  2:0]   adc_status_3 = 'd0;
+  reg     [  2:0]   adc_status_2 = 'd0;
+  reg     [  2:0]   adc_status_1 = 'd0;
+  reg     [  2:0]   adc_status_0 = 'd0;
+  reg               adc_valid = 'd0;
+  reg     [ 31:0]   adc_data = 'd0;
+  reg     [  2:0]   adc_seq = 'd0;
+  reg     [  4:0]   adc_status = 'd0;
+  reg     [ 63:0]   adc_crc_8 = 'd0;
+  reg     [  7:0]   adc_crc_mismatch_int = 'd0;
+  reg               adc_crc_valid = 'd0;
+  reg     [  7:0]   adc_crc_data = 'd0;
+  reg     [  7:0]   adc_crc_mismatch_8 = 'd0;
+  reg               adc_valid_int = 'd0;
+  reg     [ 31:0]   adc_data_int = 'd0;
+  reg     [  2:0]   adc_seq_int = 'd0;
+  reg               adc_enable_int = 'd0;
+  reg     [  3:0]   adc_crc_scnt_int = 'd0;
+  reg     [  3:0]   adc_crc_scnt_8 = 'd0;
+  reg     [ 23:0]   adc_seq_data = 'd0;
+  reg               adc_seq_fmatch = 'd0;
+  reg     [ 23:0]   adc_seq_fdata = 'd0;
+  reg               adc_seq_foos = 'd0;
+  reg     [  7:0]   adc_enable_8 = 'd0;
+  reg     [ 23:0]   adc_seq_8 = 'd0;
+  reg               adc_valid_8 = 'd0;
+  reg     [ 31:0]   adc_data_8 = 'd0;
+  reg     [  7:0]   adc_ch_valid_d = 'd0;
+  reg     [255:0]   adc_ch_data_d0 = 'd0;
+  reg     [255:0]   adc_ch_data_d1 = 'd0;
+  reg     [255:0]   adc_ch_data_d2 = 'd0;
+  reg     [255:0]   adc_ch_data_d3 = 'd0;
+  reg     [255:0]   adc_ch_data_d4 = 'd0;
+  reg     [255:0]   adc_ch_data_d5 = 'd0;
+  reg     [255:0]   adc_ch_data_d6 = 'd0;
+  reg     [255:0]   adc_ch_data_d7 = 'd0;
+  reg               adc_ch_valid_0 = 'd0;
+  reg               adc_ch_valid_1 = 'd0;
+  reg               adc_ch_valid_2 = 'd0;
+  reg               adc_ch_valid_3 = 'd0;
+  reg               adc_ch_valid_4 = 'd0;
+  reg               adc_ch_valid_5 = 'd0;
+  reg               adc_ch_valid_6 = 'd0;
+  reg               adc_ch_valid_7 = 'd0;
+  reg     [ 31:0]   adc_ch_data_0 = 'd0;
+  reg     [ 31:0]   adc_ch_data_1 = 'd0;
+  reg     [ 31:0]   adc_ch_data_2 = 'd0;
+  reg     [ 31:0]   adc_ch_data_3 = 'd0;
+  reg     [ 31:0]   adc_ch_data_4 = 'd0;
+  reg     [ 31:0]   adc_ch_data_5 = 'd0;
+  reg     [ 31:0]   adc_ch_data_6 = 'd0;
+  reg     [ 31:0]   adc_ch_data_7 = 'd0;
+  reg               adc_ch_valid = 'd0;
+  reg     [255:0]   adc_ch_data = 'd0;
+  reg     [  8:0]   adc_cnt_p = 'd0;
+  reg               adc_valid_p = 'd0;
+  reg     [255:0]   adc_data_p = 'd0;
+  reg     [  7:0]   adc_data_d1 = 'd0;
+  reg     [  7:0]   adc_data_d2 = 'd0;
+  reg               adc_ready_d1 = 'd0;
+  reg               adc_ready = 'd0;
+  reg               adc_ready_d = 'd0;
+  reg               adc_sshot_m1 = 'd0;
+  reg               adc_sshot = 'd0;
+  reg     [  1:0]   adc_format_m1 = 'd0;
+  reg     [  1:0]   adc_format = 'd0;
+  reg               adc_crc_enable_m1 = 'd0;
+  reg               adc_crc_enable = 'd0;
+  reg               adc_crc_4_or_16_n_m1 = 'd0;
+  reg               adc_crc_4_or_16_n = 'd0;
+  reg     [ 35:0]   adc_status_clr_m1 = 'd0;
+  reg     [ 35:0]   adc_status_clr = 'd0;
+  reg     [ 35:0]   adc_status_clr_d = 'd0;
+
+  // internal signals
+
+  wire    [  7:0]   adc_crc_in_s;
+  wire    [  7:0]   adc_crc_s;
+  wire              adc_crc_mismatch_s;
+  wire              adc_seq_fmatch_s;
+  wire              adc_seq_fupdate_s;
+  wire    [  7:0]   adc_enable_8_s;
+  wire    [ 23:0]   adc_seq_8_s;
+  wire              adc_cnt_enable_1_s;
+  wire              adc_cnt_enable_4_s;
+  wire              adc_cnt_enable_8_s;
+  wire              adc_cnt_enable_s;
+  wire    [  7:0]   adc_data_in_s;
+  wire              adc_ready_in_s;
+  wire              adc_clk_in_s;
+  wire    [ 35:0]   adc_status_clr_s;
+
+  // function (crc)
+
+  function  [ 7:0]  crc8;
+    input   [23:0]  din;
+    input   [ 7:0]  cin;
+    reg     [ 7:0]  cout;
+    begin
+      cout[ 7] =  cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 6] ^ din[ 5] ^ din[ 6] ^ din[ 7] ^ din[11] ^
+                  din[13] ^ din[15] ^ din[17] ^ din[18] ^ din[20] ^ din[22];
+      cout[ 6] =  cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 5] ^ din[ 4] ^ din[ 5] ^ din[ 6] ^ din[10] ^
+                  din[12] ^ din[14] ^ din[16] ^ din[17] ^ din[19] ^ din[21];
+      cout[ 5] =  cin[ 0] ^ cin[ 2] ^ cin[ 4] ^ din[ 3] ^ din[ 4] ^ din[ 5] ^ din[ 9] ^ din[11] ^
+                  din[13] ^ din[15] ^ din[16] ^ din[18] ^ din[20];
+      cout[ 4] =  cin[ 1] ^ cin[ 3] ^ din[ 2] ^ din[ 3] ^ din[ 4] ^ din[ 8] ^ din[10] ^ din[12] ^
+                  din[14] ^ din[15] ^ din[17] ^ din[19];
+      cout[ 3] =  cin[ 0] ^ cin[ 2] ^ cin[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 9] ^
+                  din[11] ^ din[13] ^ din[14] ^ din[16] ^ din[18] ^ din[23];
+      cout[ 2] =  cin[ 1] ^ cin[ 6] ^ din[ 0] ^ din[ 1] ^ din[ 2] ^ din[ 6] ^ din[ 8] ^ din[10] ^
+                  din[12] ^ din[13] ^ din[15] ^ din[17] ^ din[22];
+      cout[ 1] =  cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 5] ^ cin[ 6] ^ cin[ 7] ^ din[ 0] ^
+                  din[ 1] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
+                  din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23];
+      cout[ 0] =  cin[ 0] ^ cin[ 2] ^ cin[ 3] ^ cin[ 5] ^ cin[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 7] ^
+                  din[ 8] ^ din[12] ^ din[14] ^ din[16] ^ din[18] ^ din[19] ^ din[21] ^ din[23];
+      crc8 = cout;
+    end
+  endfunction
+
+  // status
+
+  assign up_status[35:32] = {2'd0, adc_status_8};
+  assign up_status[31:28] = {1'd0, adc_status_7};
+  assign up_status[27:24] = {1'd0, adc_status_6};
+  assign up_status[23:20] = {1'd0, adc_status_5};
+  assign up_status[19:16] = {1'd0, adc_status_4};
+  assign up_status[15:12] = {1'd0, adc_status_3};
+  assign up_status[11: 8] = {1'd0, adc_status_2};
+  assign up_status[ 7: 4] = {1'd0, adc_status_1};
+  assign up_status[ 3: 0] = {1'd0, adc_status_0};
+
+  always @(posedge adc_clk) begin
+    if (adc_valid == 1'b1) begin
+      adc_status_8 <= adc_status_8 | adc_status[1:0];
+    end else begin
+      adc_status_8 <= adc_status_8 & ~adc_status_clr_s[33:32];
+    end
+    if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd7)) begin
+      adc_status_7 <= adc_status_7 | adc_status[4:2];
+    end else begin
+      adc_status_7 <= adc_status_7 & ~adc_status_clr_s[30:28];
+    end
+    if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd6)) begin
+      adc_status_6 <= adc_status_6 | adc_status[4:2];
+    end else begin
+      adc_status_6 <= adc_status_6 & ~adc_status_clr_s[26:24];
+    end
+    if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd5)) begin
+      adc_status_5 <= adc_status_5 | adc_status[4:2];
+    end else begin
+      adc_status_5 <= adc_status_5 & ~adc_status_clr_s[22:20];
+    end
+    if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd4)) begin
+      adc_status_4 <= adc_status_4 | adc_status[4:2];
+    end else begin
+      adc_status_4 <= adc_status_4 & ~adc_status_clr_s[18:16];
+    end
+    if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd3)) begin
+      adc_status_3 <= adc_status_3 | adc_status[4:2];
+    end else begin
+      adc_status_3 <= adc_status_3 & ~adc_status_clr_s[14:12];
+    end
+    if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd2)) begin
+      adc_status_2 <= adc_status_2 | adc_status[4:2];
+    end else begin
+      adc_status_2 <= adc_status_2 & ~adc_status_clr_s[10: 8];
+    end
+    if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd1)) begin
+      adc_status_1 <= adc_status_1 | adc_status[4:2];
+    end else begin
+      adc_status_1 <= adc_status_1 & ~adc_status_clr_s[ 6: 4];
+    end
+    if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd0)) begin
+      adc_status_0 <= adc_status_0 | adc_status[4:2];
+    end else begin
+      adc_status_0 <= adc_status_0 & ~adc_status_clr_s[ 2: 0];
+    end
+  end
+
+  // data & status
+
+  always @(posedge adc_clk) begin
+    adc_valid <= adc_valid_int & adc_enable_int;
+    adc_data <= {{8{adc_data_int[23]}}, adc_data_int[23:0]};
+    adc_seq <= adc_seq_int;
+    if ((adc_crc_enable == 1'b1) && (adc_crc_scnt_int == 4'd0)) begin
+      adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int;
+      adc_status[3] <= 1'b0;
+      adc_status[2] <= 1'b0;
+      adc_status[1] <= 1'b0;
+      adc_status[0] <= adc_seq_foos;
+    end else begin
+      adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int;
+      adc_status[3] <= adc_data_int[30] & adc_enable_int;
+      adc_status[2] <= adc_data_int[27] & adc_enable_int;
+      adc_status[1] <= adc_data_int[31] & adc_enable_int;
+      adc_status[0] <= adc_seq_foos;
+    end 
+  end
+
+  // crc- not much useful at the interface, since it is post-framing
+
+  assign adc_crc_in_s = (adc_crc_scnt_int == 4'd1) ? 8'hff : adc_crc_8[63:56];
+  assign adc_crc_s = crc8(adc_data_int[23:0], adc_crc_in_s);
+  assign adc_crc_mismatch_s = (adc_crc_data == adc_crc_8[7:0]) ? 1'b0 : adc_crc_enable;
+
+  always @(posedge adc_clk) begin
+    if (adc_valid_int == 1'b1) begin
+      adc_crc_8 <= {adc_crc_8[55:0], adc_crc_s};
+    end
+    if (adc_valid_int == 1'b1) begin
+      adc_crc_mismatch_int <= {adc_crc_mismatch_int[6:0], 1'd0};
+    end else begin
+      adc_crc_mismatch_int <= adc_crc_mismatch_8;
+    end
+    if (adc_crc_scnt_int == 4'd0) begin
+      adc_crc_valid <= adc_valid_int;
+    end else begin
+      adc_crc_valid <= 1'd0;
+    end
+    adc_crc_data <= adc_data_int[31:24];
+    if (adc_crc_valid == 1'b1) begin
+      adc_crc_mismatch_8 <= {adc_crc_mismatch_8[6:0], adc_crc_mismatch_s};
+    end
+  end
+
+  // data interleaved & all-aligned
+
+  always @(posedge adc_clk) begin
+    adc_valid_int <= adc_valid_8;
+    adc_data_int <= adc_data_8;
+    adc_seq_int <= adc_seq_8[23:21];
+    adc_enable_int <= adc_enable_8[7] & adc_valid_8;
+    adc_crc_scnt_int <= adc_crc_scnt_8;
+  end
+
+  // crc- count
+
+  always @(posedge adc_clk) begin
+    if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
+      if (adc_seq_fmatch_s == 1'b0) begin
+        adc_crc_scnt_8 <= 4'd1;
+      end else if ((adc_crc_4_or_16_n == 1'b1) && (adc_crc_scnt_8 == 4'h3)) begin
+        adc_crc_scnt_8 <= 4'd0;
+      end else begin
+        adc_crc_scnt_8 <= adc_crc_scnt_8 + 1'b1;
+      end
+    end
+  end
+
+  // three sample framing logic
+
+  always @(posedge adc_clk) begin
+    if (adc_ready == 1'b0) begin
+      adc_seq_data <= 24'd0;
+    end else if (adc_valid_8 == 1'b1) begin
+      adc_seq_data <= {adc_seq_data[20:0], adc_data_8[26:24]};
+    end
+  end
+
+  assign adc_seq_fmatch_s = (adc_seq_data == adc_seq_fdata) ? 1'b1 : 1'b0;
+  assign adc_seq_fupdate_s = adc_seq_fmatch_s ^ adc_seq_fmatch;
+
+  always @(posedge adc_clk) begin
+    if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
+      adc_seq_fmatch <= adc_seq_fmatch_s;
+      if (adc_seq_foos == 1'b1) begin
+        adc_seq_fdata <= adc_seq_data;
+      end
+      if (adc_seq_fupdate_s == 1'b0) begin
+        adc_seq_foos <= ~adc_seq_fmatch_s;
+      end
+    end
+  end
+
+  // we are cluless on 0 -- safe to compare all 32bits against 0x0?
+
+  assign adc_enable_8_s[7] = (adc_seq_8[23:21] == adc_seq_fdata[23:21]) ? 1'b1 : 1'b0;
+  assign adc_enable_8_s[6] = (adc_seq_8[20:18] == adc_seq_fdata[20:18]) ? 1'b1 : 1'b0;
+  assign adc_enable_8_s[5] = (adc_seq_8[17:15] == adc_seq_fdata[17:15]) ? 1'b1 : 1'b0;
+  assign adc_enable_8_s[4] = (adc_seq_8[14:12] == adc_seq_fdata[14:12]) ? 1'b1 : 1'b0;
+  assign adc_enable_8_s[3] = (adc_seq_8[11: 9] == adc_seq_fdata[11: 9]) ? 1'b1 : 1'b0;
+  assign adc_enable_8_s[2] = (adc_seq_8[ 8: 6] == adc_seq_fdata[ 8: 6]) ? 1'b1 : 1'b0;
+  assign adc_enable_8_s[1] = (adc_seq_8[ 5: 3] == adc_seq_fdata[ 5: 3]) ? 1'b1 : 1'b0;
+  assign adc_enable_8_s[0] = (adc_seq_8[ 2: 0] == adc_seq_fdata[ 2: 0]) ? 1'b1 : 1'b0;
+
+  always @(posedge adc_clk) begin
+    if (adc_ready_d == 1'b0) begin
+      adc_enable_8 <= adc_enable_8_s;
+    end else if (adc_valid_8 == 1'b1) begin
+      adc_enable_8 <= {adc_enable_8[6:0], 1'd0};
+    end
+  end
+
+  // channel-sequence
+
+  assign adc_seq_8_s[23:21] = (adc_format == 2'b01) ? 3'd0 : 3'd0;
+  assign adc_seq_8_s[20:18] = (adc_format == 2'b01) ? 3'd4 : 3'd1;
+  assign adc_seq_8_s[17:15] = (adc_format == 2'b01) ? 3'd1 : 3'd2;
+  assign adc_seq_8_s[14:12] = (adc_format == 2'b01) ? 3'd5 : 3'd3;
+  assign adc_seq_8_s[11: 9] = (adc_format == 2'b01) ? 3'd2 : 3'd4;
+  assign adc_seq_8_s[ 8: 6] = (adc_format == 2'b01) ? 3'd6 : 3'd5;
+  assign adc_seq_8_s[ 5: 3] = (adc_format == 2'b01) ? 3'd3 : 3'd6;
+  assign adc_seq_8_s[ 2: 0] = (adc_format == 2'b01) ? 3'd7 : 3'd7;
+
+  always @(posedge adc_clk) begin
+    if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
+      adc_seq_8 <= adc_seq_8_s;
+    end else if (adc_valid_8 == 1'b1) begin
+      adc_seq_8 <= {adc_seq_8[20:0], 3'd0};
+    end
+  end
+
+  // data (interleaving)
+
+  always @(posedge adc_clk) begin
+    adc_valid_8 <=  adc_ch_valid_0 | adc_ch_valid_1 | adc_ch_valid_2 | adc_ch_valid_3 |
+                    adc_ch_valid_4 | adc_ch_valid_5 | adc_ch_valid_6 | adc_ch_valid_7;
+    adc_data_8 <= adc_ch_data_0 | adc_ch_data_1 | adc_ch_data_2 | adc_ch_data_3 |
+                  adc_ch_data_4 | adc_ch_data_5 | adc_ch_data_6 | adc_ch_data_7;
+  end
+
+  always @(posedge adc_clk) begin
+    adc_ch_valid_d <= {adc_ch_valid_d[6:0], adc_ch_valid};
+    adc_ch_data_d0[((32*0)+31):(32*0)] <= adc_ch_data[((32*0)+31):(32*0)];
+    adc_ch_data_d0[((32*7)+31):(32*1)] <= adc_ch_data_d0[((32*6)+31):(32*0)];
+    adc_ch_data_d1[((32*0)+31):(32*0)] <= adc_ch_data[((32*1)+31):(32*1)];
+    adc_ch_data_d1[((32*7)+31):(32*1)] <= adc_ch_data_d1[((32*6)+31):(32*0)];
+    adc_ch_data_d2[((32*0)+31):(32*0)] <= adc_ch_data[((32*2)+31):(32*2)];
+    adc_ch_data_d2[((32*7)+31):(32*1)] <= adc_ch_data_d2[((32*6)+31):(32*0)];
+    adc_ch_data_d3[((32*0)+31):(32*0)] <= adc_ch_data[((32*3)+31):(32*3)];
+    adc_ch_data_d3[((32*7)+31):(32*1)] <= adc_ch_data_d3[((32*6)+31):(32*0)];
+    adc_ch_data_d4[((32*0)+31):(32*0)] <= adc_ch_data[((32*4)+31):(32*4)];
+    adc_ch_data_d4[((32*7)+31):(32*1)] <= adc_ch_data_d4[((32*6)+31):(32*0)];
+    adc_ch_data_d5[((32*0)+31):(32*0)] <= adc_ch_data[((32*5)+31):(32*5)];
+    adc_ch_data_d5[((32*7)+31):(32*1)] <= adc_ch_data_d5[((32*6)+31):(32*0)];
+    adc_ch_data_d6[((32*0)+31):(32*0)] <= adc_ch_data[((32*6)+31):(32*6)];
+    adc_ch_data_d6[((32*7)+31):(32*1)] <= adc_ch_data_d6[((32*6)+31):(32*0)];
+    adc_ch_data_d7[((32*0)+31):(32*0)] <= adc_ch_data[((32*7)+31):(32*7)];
+    adc_ch_data_d7[((32*7)+31):(32*1)] <= adc_ch_data_d7[((32*6)+31):(32*0)];
+  end
+
+  always @(posedge adc_clk) begin
+    adc_ch_valid_0 <= adc_ch_valid_d[0];
+    adc_ch_valid_1 <= adc_ch_valid_d[1] & ~adc_format[1];
+    adc_ch_valid_2 <= adc_ch_valid_d[2] & ~adc_format[1] & ~adc_format[0];
+    adc_ch_valid_3 <= adc_ch_valid_d[3] & ~adc_format[1] & ~adc_format[0];
+    adc_ch_valid_4 <= adc_ch_valid_d[4] & ~adc_format[1] & ~adc_format[0];
+    adc_ch_valid_5 <= adc_ch_valid_d[5] & ~adc_format[1] & ~adc_format[0];
+    adc_ch_valid_6 <= adc_ch_valid_d[6] & ~adc_format[1] & ~adc_format[0];
+    adc_ch_valid_7 <= adc_ch_valid_d[7] & ~adc_format[1] & ~adc_format[0];
+    adc_ch_data_0 <= adc_ch_data_d0[((32*0)+31):(32*0)];
+    adc_ch_data_1 <= adc_ch_data_d1[((32*1)+31):(32*1)];
+    adc_ch_data_2 <= adc_ch_data_d2[((32*2)+31):(32*2)];
+    adc_ch_data_3 <= adc_ch_data_d3[((32*3)+31):(32*3)];
+    adc_ch_data_4 <= adc_ch_data_d4[((32*4)+31):(32*4)];
+    adc_ch_data_5 <= adc_ch_data_d5[((32*5)+31):(32*5)];
+    adc_ch_data_6 <= adc_ch_data_d6[((32*6)+31):(32*6)];
+    adc_ch_data_7 <= adc_ch_data_d7[((32*7)+31):(32*7)];
+  end
+
+  always @(posedge adc_clk) begin
+    adc_ch_valid <= adc_valid_p;
+    if (adc_valid_p == 1'b1) begin
+      adc_ch_data <= adc_data_p;
+    end else begin
+      adc_ch_data <= 256'd0;
+    end
+  end
+
+  // data (common)
+
+  assign adc_cnt_enable_1_s = (adc_cnt_p <= 9'h01f) ? 1'b1 : 1'b0;
+  assign adc_cnt_enable_4_s = (adc_cnt_p <= 9'h07f) ? 1'b1 : 1'b0;
+  assign adc_cnt_enable_8_s = (adc_cnt_p <= 9'h0ff) ? 1'b1 : 1'b0;
+
+  assign adc_cnt_enable_s = (adc_format == 2'b00) ? adc_cnt_enable_1_s :
+    ((adc_format == 2'b01) ? adc_cnt_enable_4_s : adc_cnt_enable_8_s);
+
+  always @(posedge adc_clk) begin
+    if (adc_ready == 1'b0) begin
+      adc_cnt_p <= 9'h000;
+    end else if (adc_cnt_enable_s == 1'b1) begin
+      adc_cnt_p <= adc_cnt_p + 1'b1;
+    end
+    if (adc_cnt_p[4:0] == 5'h1f) begin
+      adc_valid_p <= 1'b1;
+    end else begin
+      adc_valid_p <= 1'b0;
+    end
+  end
+
+  // data (individual lanes)
+
+  genvar n;
+  generate
+  for (n = 0; n < 8; n = n + 1) begin: g_data
+
+  always @(posedge adc_clk) begin
+    if (adc_cnt_p[4:0] == 5'h00) begin
+      adc_data_p[((32*n)+31):(32*n)] <= {31'd0, adc_data_d2[n]};
+    end else begin
+      adc_data_p[((32*n)+31):(32*n)] <= {adc_data_p[((32*n)+30):(32*n)], adc_data_d2[n]};
+    end
+  end
+
+  always @(posedge adc_clk) begin
+    adc_data_d1[n] <= adc_data_in_s[n];
+    adc_data_d2[n] <= adc_data_d1[n];
+  end
+
+  IBUF i_ibuf_data (
+    .I (data_in[n]),
+    .O (adc_data_in_s[n]));
+
+  end
+  endgenerate
+
+  // ready (single shot or continous)
+
+  always @(posedge adc_clk) begin
+    adc_ready_d1 <= adc_ready_in_s;
+    adc_ready <= adc_sshot ~^ adc_ready_d1;
+    adc_ready_d <= adc_ready;
+  end
+
+  IBUF i_ibuf_ready (
+    .I (ready_in),
+    .O (adc_ready_in_s));
+
+  // clock (use bufg delay ~4ns on 29ns)
+
+  BUFG i_bufg_clk (
+    .I (adc_clk_in_s),
+    .O (adc_clk));
+
+  IBUFG i_ibufg_clk (
+    .I (clk_in),
+    .O (adc_clk_in_s));
+
+  // control signals
+
+  assign adc_status_clr_s = adc_status_clr & ~adc_status_clr_d;
+
+  always @(posedge adc_clk) begin
+    adc_sshot_m1 <= up_sshot;
+    adc_sshot <= adc_sshot_m1;
+    adc_format_m1 <= up_format;
+    adc_format <= adc_format_m1;
+    adc_crc_enable_m1 <= up_crc_enable;
+    adc_crc_enable <= adc_crc_enable_m1;
+    adc_crc_4_or_16_n_m1 <= up_crc_4_or_16_n;
+    adc_crc_4_or_16_n <= adc_crc_4_or_16_n_m1;
+    adc_status_clr_m1 <= up_status_clr;
+    adc_status_clr <= adc_status_clr_m1;
+    adc_status_clr_d <= adc_status_clr;
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/ad7768evb/common/ad7768evb_bd.tcl b/projects/ad7768evb/common/ad7768evb_bd.tcl
new file mode 100644
index 000000000..69369dc1f
--- /dev/null
+++ b/projects/ad7768evb/common/ad7768evb_bd.tcl
@@ -0,0 +1,62 @@
+
+# ad7768 interface
+
+create_bd_port -dir I adc_clk
+create_bd_port -dir I adc_valid
+create_bd_port -dir I -from 31 -to 0 adc_data
+create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i
+create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o
+create_bd_port -dir O -from 31 -to 0 adc_gpio_0_t
+create_bd_port -dir I -from 31 -to 0 adc_gpio_1_i
+create_bd_port -dir O -from 31 -to 0 adc_gpio_1_o
+create_bd_port -dir O -from 31 -to 0 adc_gpio_1_t
+
+# instances
+
+set ad7768_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad7768_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $ad7768_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $ad7768_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $ad7768_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $ad7768_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $ad7768_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $ad7768_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $ad7768_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad7768_dma
+
+# ps7-hp1
+
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
+
+# gpio
+
+set ad7768_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 ad7768_gpio]
+set_property -dict [list CONFIG.C_IS_DUAL {1}] $ad7768_gpio
+set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $ad7768_gpio
+set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $ad7768_gpio
+set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $ad7768_gpio
+
+# interconnects
+
+ad_connect  adc_clk ad7768_dma/fifo_wr_clk
+ad_connect  adc_valid ad7768_dma/fifo_wr_en
+ad_connect  adc_data ad7768_dma/fifo_wr_din
+ad_connect  adc_gpio_0_i ad7768_gpio/gpio_io_i
+ad_connect  adc_gpio_0_o ad7768_gpio/gpio_io_o
+ad_connect  adc_gpio_0_t ad7768_gpio/gpio_io_t
+ad_connect  adc_gpio_1_i ad7768_gpio/gpio2_io_i
+ad_connect  adc_gpio_1_o ad7768_gpio/gpio2_io_o
+ad_connect  adc_gpio_1_t ad7768_gpio/gpio2_io_t
+
+# interrupts
+
+ad_cpu_interrupt ps-13 mb-13  ad7768_dma/irq
+ad_cpu_interrupt ps-12 mb-12  ad7768_gpio/ip2intc_irpt
+
+# cpu / memory interconnects
+
+ad_cpu_interconnect 0x7C400000 ad7768_dma
+ad_cpu_interconnect 0x7C420000 ad7768_gpio
+
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma/m_dest_axi
+
diff --git a/projects/ad7768evb/zed/Makefile b/projects/ad7768evb/zed/Makefile
new file mode 100644
index 000000000..33231bac1
--- /dev/null
+++ b/projects/ad7768evb/zed/Makefile
@@ -0,0 +1,78 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/cftl_cip_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zed/zed_system_constr.xdc
+M_DEPS += ../../common/zed/zed_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
+M_DEPS += ../../../library/util_pmod_adc/util_pmod_adc.xpr
+M_DEPS += ../../../library/util_pmod_fmeter/util_pmod_fmeter.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib cftl_custom_zed.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_i2s_adi clean
+	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_i2c_mixer clean
+	make -C ../../../library/util_pmod_adc clean
+	make -C ../../../library/util_pmod_fmeter clean
+
+
+cftl_custom_zed.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> cftl_custom_zed_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_i2s_adi
+	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_i2c_mixer
+	make -C ../../../library/util_pmod_adc
+	make -C ../../../library/util_pmod_fmeter
+
+####################################################################################
+####################################################################################
diff --git a/projects/ad7768evb/zed/system_bd.tcl b/projects/ad7768evb/zed/system_bd.tcl
new file mode 100644
index 000000000..ec644da27
--- /dev/null
+++ b/projects/ad7768evb/zed/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
+source ../common/ad7768evb_bd.tcl
+
diff --git a/projects/ad7768evb/zed/system_constr.xdc b/projects/ad7768evb/zed/system_constr.xdc
new file mode 100644
index 000000000..0ecfe8c9d
--- /dev/null
+++ b/projects/ad7768evb/zed/system_constr.xdc
@@ -0,0 +1,29 @@
+
+
+set_property  -dict {PACKAGE_PIN L18  IOSTANDARD LVCMOS25}  [get_ports clk_in]              ; ## H04  FMC_LPC_CLK0_M2C_P IO_L12P_T1_MRCC_34 
+set_property  -dict {PACKAGE_PIN M19  IOSTANDARD LVCMOS25}  [get_ports ready_in]            ; ## G06  FMC_LPC_LA00_CC_P  IO_L13P_T2_MRCC_34 
+set_property  -dict {PACKAGE_PIN M20  IOSTANDARD LVCMOS25}  [get_ports data_in[0]]          ; ## G07  FMC_LPC_LA00_CC_N  IO_L13N_T2_MRCC_34 
+set_property  -dict {PACKAGE_PIN L22  IOSTANDARD LVCMOS25}  [get_ports data_in[1]]          ; ## C11  FMC_LPC_LA06_N     IO_L10N_T1_34      
+set_property  -dict {PACKAGE_PIN P17  IOSTANDARD LVCMOS25}  [get_ports data_in[2]]          ; ## H07  FMC_LPC_LA02_P     IO_L20P_T3_34      
+set_property  -dict {PACKAGE_PIN P18  IOSTANDARD LVCMOS25}  [get_ports data_in[3]]          ; ## H08  FMC_LPC_LA02_N     IO_L20N_T3_34      
+set_property  -dict {PACKAGE_PIN J21  IOSTANDARD LVCMOS25}  [get_ports data_in[4]]          ; ## G12  FMC_LPC_LA08_P     IO_L8P_T1_34       
+set_property  -dict {PACKAGE_PIN J22  IOSTANDARD LVCMOS25}  [get_ports data_in[5]]          ; ## G13  FMC_LPC_LA08_N     IO_L8N_T1_34       
+set_property  -dict {PACKAGE_PIN R20  IOSTANDARD LVCMOS25}  [get_ports data_in[6]]          ; ## D14  FMC_LPC_LA09_P     IO_L17P_T2_34      
+set_property  -dict {PACKAGE_PIN R21  IOSTANDARD LVCMOS25}  [get_ports data_in[7]]          ; ## D15  FMC_LPC_LA09_N     IO_L17N_T2_34      
+set_property  -dict {PACKAGE_PIN J18  IOSTANDARD LVCMOS25}  [get_ports spi_csn]             ; ## D11  FMC_LPC_LA05_P     IO_L7P_T1_34       
+set_property  -dict {PACKAGE_PIN N19  IOSTANDARD LVCMOS25}  [get_ports spi_clk]             ; ## D08  FMC_LPC_LA01_CC_P  IO_L14P_T2_SRCC_34 
+set_property  -dict {PACKAGE_PIN M22  IOSTANDARD LVCMOS25}  [get_ports spi_mosi]            ; ## H11  FMC_LPC_LA04_N     IO_L15N_T2_DQS_34  
+set_property  -dict {PACKAGE_PIN N22  IOSTANDARD LVCMOS25}  [get_ports spi_miso]            ; ## G09  FMC_LPC_LA03_P     IO_L16P_T2_34      
+set_property  -dict {PACKAGE_PIN T19  IOSTANDARD LVCMOS25}  [get_ports gpio_0_mode_0]       ; ## C15  FMC_LPC_LA10_N     IO_L22N_T3_34             
+set_property  -dict {PACKAGE_PIN T16  IOSTANDARD LVCMOS25}  [get_ports gpio_1_mode_1]       ; ## H13  FMC_LPC_LA07_P     IO_L21P_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN T17  IOSTANDARD LVCMOS25}  [get_ports gpio_2_mode_2]       ; ## H14  FMC_LPC_LA07_N     IO_L21N_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN N17  IOSTANDARD LVCMOS25}  [get_ports gpio_3_mode_3]       ; ## H16  FMC_LPC_LA11_P     IO_L5P_T0_34              
+set_property  -dict {PACKAGE_PIN R19  IOSTANDARD LVCMOS25}  [get_ports gpio_4_filter]       ; ## C14  FMC_LPC_LA10_P     IO_L22P_T3_34             
+set_property  -dict {PACKAGE_PIN L21  IOSTANDARD LVCMOS25}  [get_ports reset_n]             ; ## C10  FMC_LPC_LA06_P     IO_L10P_T1_34             
+set_property  -dict {PACKAGE_PIN P22  IOSTANDARD LVCMOS25}  [get_ports start_n]             ; ## G10  FMC_LPC_LA03_N     IO_L16N_T2_34             
+set_property  -dict {PACKAGE_PIN M21  IOSTANDARD LVCMOS25}  [get_ports sync_n]              ; ## H10  FMC_LPC_LA04_P     IO_L15P_T2_DQS_34         
+set_property  -dict {PACKAGE_PIN K18  IOSTANDARD LVCMOS25}  [get_ports sync_in_n]           ; ## D12  FMC_LPC_LA05_N     IO_L7N_T1_34              
+set_property  -dict {PACKAGE_PIN N20  IOSTANDARD LVCMOS25}  [get_ports mclk]                ; ## D09  FMC_LPC_LA01_CC_N  IO_L14N_T2_SRCC_34        
+
+create_clock -name adc_clk -period 20 [get_ports clk_in]
+
diff --git a/projects/ad7768evb/zed/system_project.tcl b/projects/ad7768evb/zed/system_project.tcl
new file mode 100644
index 000000000..76d299860
--- /dev/null
+++ b/projects/ad7768evb/zed/system_project.tcl
@@ -0,0 +1,15 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create ad7768evb_zed
+adi_project_files ad7768evb_zed [list \
+  "../common/ad7768_if.v" \
+  "system_top.v" \
+  "system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_iobuf.v" ]
+
+adi_project_run ad7768evb_zed
+
diff --git a/projects/ad7768evb/zed/system_top.v b/projects/ad7768evb/zed/system_top.v
new file mode 100644
index 000000000..64814dba9
--- /dev/null
+++ b/projects/ad7768evb/zed/system_top.v
@@ -0,0 +1,341 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  gpio_bd,
+
+  hdmi_out_clk,
+  hdmi_vsync,
+  hdmi_hsync,
+  hdmi_data_e,
+  hdmi_data,
+
+  i2s_mclk,
+  i2s_bclk,
+  i2s_lrclk,
+  i2s_sdata_out,
+  i2s_sdata_in,
+
+  spdif,
+
+  iic_scl,
+  iic_sda,
+  iic_mux_scl,
+  iic_mux_sda,
+
+  otg_vbusoc,
+
+  clk_in,
+  ready_in,
+  data_in,
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  gpio_0_mode_0,
+  gpio_1_mode_1,
+  gpio_2_mode_2,
+  gpio_3_mode_3,
+  gpio_4_filter,
+  reset_n,
+  start_n,
+  sync_n,
+  sync_in_n,
+  mclk);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout   [31:0]  gpio_bd;
+
+  output          hdmi_out_clk;
+  output          hdmi_vsync;
+  output          hdmi_hsync;
+  output          hdmi_data_e;
+  output  [15:0]  hdmi_data;
+
+  output          spdif;
+
+  output          i2s_mclk;
+  output          i2s_bclk;
+  output          i2s_lrclk;
+  output          i2s_sdata_out;
+  input           i2s_sdata_in;
+
+  inout           iic_scl;
+  inout           iic_sda;
+  inout   [ 1:0]  iic_mux_scl;
+  inout   [ 1:0]  iic_mux_sda;
+
+  input           otg_vbusoc;
+
+  input           clk_in;
+  input           ready_in;
+  input   [ 7:0]  data_in;
+
+  output          spi_csn;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  inout           gpio_0_mode_0;
+  inout           gpio_1_mode_1;
+  inout           gpio_2_mode_2;
+  inout           gpio_3_mode_3;
+  inout           gpio_4_filter;
+  inout           reset_n;
+  inout           start_n;
+  inout           sync_n;
+  inout           sync_in_n;
+  output          mclk;
+
+  // internal signals
+
+  wire            adc_clk;
+  wire            adc_valid;
+  wire    [31:0]  adc_data;
+  wire            up_sshot;
+  wire    [ 1:0]  up_format;
+  wire            up_crc_enable;
+  wire            up_crc_4_or_16_n;
+  wire    [63:0]  adc_gpio_i;
+  wire    [63:0]  adc_gpio_o;
+  wire    [63:0]  adc_gpio_t;
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire    [ 1:0]  iic_mux_scl_i_s;
+  wire    [ 1:0]  iic_mux_scl_o_s;
+  wire            iic_mux_scl_t_s;
+  wire    [ 1:0]  iic_mux_sda_i_s;
+  wire    [ 1:0]  iic_mux_sda_o_s;
+  wire            iic_mux_sda_t_s;
+
+  // use crystal
+
+  assign mclk = 1'b0;
+  assign up_sshot = gpio_o[36];
+  assign up_format = gpio_o[35:34];
+  assign up_crc_enable = gpio_o[33];
+  assign up_crc_4_or_16_n = gpio_o[32];
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
+    .dio_t ({gpio_t[52:48], gpio_t[43:40]}),
+    .dio_i ({gpio_o[52:48], gpio_o[43:40]}),
+    .dio_o ({gpio_i[52:48], gpio_i[43:40]}),
+    .dio_p ({ gpio_4_filter,        // 52
+              gpio_3_mode_3,        // 51
+              gpio_2_mode_2,        // 50
+              gpio_1_mode_1,        // 49
+              gpio_0_mode_0,        // 48
+              sync_in_n,            // 43
+              sync_n,               // 42 
+              start_n,              // 41
+              reset_n}));           // 40
+
+  ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd (
+    .dio_t (gpio_t[31:0]),
+    .dio_i (gpio_o[31:0]),
+    .dio_o (gpio_i[31:0]),
+    .dio_p (gpio_bd));
+
+  ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_scl (
+    .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}),
+    .dio_i (iic_mux_scl_o_s),
+    .dio_o (iic_mux_scl_i_s),
+    .dio_p (iic_mux_scl));
+
+  ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_sda (
+    .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}),
+    .dio_i (iic_mux_sda_o_s),
+    .dio_o (iic_mux_sda_i_s),
+    .dio_p (iic_mux_sda));
+
+  ad7768_if i_ad7768_if (
+    .clk_in (clk_in),
+    .ready_in (ready_in),
+    .data_in (data_in),
+    .adc_clk (adc_clk),
+    .adc_valid (adc_valid),
+    .adc_data (adc_data),
+    .up_sshot (up_sshot),
+    .up_format (up_format),
+    .up_crc_enable (up_crc_enable),
+    .up_crc_4_or_16_n (up_crc_4_or_16_n),
+    .up_status_clr (adc_gpio_o[32:0]),
+    .up_status (adc_gpio_i[32:0]));
+
+  system_wrapper i_system_wrapper (
+    .adc_clk (adc_clk),
+    .adc_data (adc_data),
+    .adc_gpio_0_i (adc_gpio_i[31:0]),
+    .adc_gpio_0_o (adc_gpio_o[31:0]),
+    .adc_gpio_0_t (adc_gpio_t[31:0]),
+    .adc_gpio_1_i (adc_gpio_i[63:32]),
+    .adc_gpio_1_o (adc_gpio_o[63:32]),
+    .adc_gpio_1_t (adc_gpio_t[63:32]),
+    .adc_valid (adc_valid),
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .i2s_bclk (i2s_bclk),
+    .i2s_lrclk (i2s_lrclk),
+    .i2s_mclk (i2s_mclk),
+    .i2s_sdata_in (i2s_sdata_in),
+    .i2s_sdata_out (i2s_sdata_out),
+    .iic_fmc_scl_io (iic_scl),
+    .iic_fmc_sda_io (iic_sda),
+    .iic_mux_scl_i (iic_mux_scl_i_s),
+    .iic_mux_scl_o (iic_mux_scl_o_s),
+    .iic_mux_scl_t (iic_mux_scl_t_s),
+    .iic_mux_sda_i (iic_mux_sda_i_s),
+    .iic_mux_sda_o (iic_mux_sda_o_s),
+    .iic_mux_sda_t (iic_mux_sda_t_s),
+    .otg_vbusoc (otg_vbusoc),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .spdif (spdif),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o ());
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From be075379df67721922407744cf69faff82e7b118 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 7 Dec 2015 13:11:24 -0500
Subject: [PATCH 012/972] hdlmake: updates

---
 projects/Makefile               |  3 +++
 projects/ad7768evb/zed/Makefile | 15 +++++----------
 projects/usdrx1/a5gt/Makefile   |  1 +
 3 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/projects/Makefile b/projects/Makefile
index 75ec31ca4..8170c81a4 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -8,6 +8,7 @@
 .PHONY: all clean clean_all
 all:
 	-make -C ad6676evb all
+	-make -C ad7768evb all
 	-make -C ad9265_fmc all
 	-make -C ad9434_fmc all
 	-make -C ad9467_fmc all
@@ -39,6 +40,7 @@ all:
 
 clean:
 	make -C ad6676evb clean
+	make -C ad7768evb clean
 	make -C ad9265_fmc clean
 	make -C ad9434_fmc clean
 	make -C ad9467_fmc clean
@@ -70,6 +72,7 @@ clean:
 
 clean-all:
 	make -C ad6676evb clean-all
+	make -C ad7768evb clean-all
 	make -C ad9265_fmc clean-all
 	make -C ad9434_fmc clean-all
 	make -C ad9467_fmc clean-all
diff --git a/projects/ad7768evb/zed/Makefile b/projects/ad7768evb/zed/Makefile
index 33231bac1..a9354819e 100644
--- a/projects/ad7768evb/zed/Makefile
+++ b/projects/ad7768evb/zed/Makefile
@@ -9,7 +9,8 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
-M_DEPS += ../common/cftl_cip_bd.tcl
+M_DEPS += ../common/ad7768evb_bd.tcl
+M_DEPS += ../common/ad7768_if.v
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
@@ -22,8 +23,6 @@ M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
-M_DEPS += ../../../library/util_pmod_adc/util_pmod_adc.xpr
-M_DEPS += ../../../library/util_pmod_fmeter/util_pmod_fmeter.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -41,7 +40,7 @@ M_FLIST += .Xil
 
 
 .PHONY: all lib clean clean-all
-all: lib cftl_custom_zed.sdk/system_top.hdf
+all: lib ad7768evb_zed.sdk/system_top.hdf
 
 
 clean: 
@@ -55,13 +54,11 @@ clean-all:clean
 	make -C ../../../library/axi_i2s_adi clean
 	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/util_i2c_mixer clean
-	make -C ../../../library/util_pmod_adc clean
-	make -C ../../../library/util_pmod_fmeter clean
 
 
-cftl_custom_zed.sdk/system_top.hdf: $(M_DEPS)
+ad7768evb_zed.sdk/system_top.hdf: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> cftl_custom_zed_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ad7768evb_zed_vivado.log 2>&1
 
 
 lib:
@@ -71,8 +68,6 @@ lib:
 	make -C ../../../library/axi_i2s_adi
 	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/util_i2c_mixer
-	make -C ../../../library/util_pmod_adc
-	make -C ../../../library/util_pmod_fmeter
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index 9be0289b1..d461204bb 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -8,6 +8,7 @@
 M_DEPS += system_project.tcl
 M_DEPS += ../common/usdrx1_spi.v
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
 M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v
 M_DEPS += ../../../library/common/altera/ad_jesd_align.v

From b0fef1122ece15900b02b48aaefce8e18ab2f307 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 09:41:37 -0500
Subject: [PATCH 013/972] daq3/a10gx: copy

---
 projects/daq3/a10gx/Makefile           | 139 ++++++
 projects/daq3/a10gx/system_bd.qsys     | 586 +++++++++++++++++++++++++
 projects/daq3/a10gx/system_constr.sdc  |  16 +
 projects/daq3/a10gx/system_project.tcl |  92 ++++
 projects/daq3/a10gx/system_top.v       | 274 ++++++++++++
 5 files changed, 1107 insertions(+)
 create mode 100644 projects/daq3/a10gx/Makefile
 create mode 100755 projects/daq3/a10gx/system_bd.qsys
 create mode 100644 projects/daq3/a10gx/system_constr.sdc
 create mode 100644 projects/daq3/a10gx/system_project.tcl
 create mode 100644 projects/daq3/a10gx/system_top.v

diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
new file mode 100644
index 000000000..51c24bfef
--- /dev/null
+++ b/projects/daq3/a10gx/Makefile
@@ -0,0 +1,139 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.sdc
+M_DEPS += system_bd.qsys
+M_DEPS += ../common/daq2_spi.v
+M_DEPS += ../common/daq2_bd.qsys
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
+M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_hw.tcl
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_if.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_mul.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/altera/MULT_MACRO.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_xcvr.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+
+
+M_ALTERA := quartus_sh --64bit -t 
+
+
+M_FLIST += *.log
+M_FLIST += *_INFO.txt
+M_FLIST += *_dump.txt
+M_FLIST += db
+M_FLIST += *.asm.rpt
+M_FLIST += *.done
+M_FLIST += *.eda.rpt
+M_FLIST += *.fit.*
+M_FLIST += *.map.*
+M_FLIST += *.sta.*
+M_FLIST += *.qsf
+M_FLIST += *.qpf
+M_FLIST += *.qws
+M_FLIST += *.sof
+M_FLIST += *.cdf
+M_FLIST += *.sld
+M_FLIST += *.qdf
+M_FLIST += hc_output
+M_FLIST += system_bd
+M_FLIST += hps_isw_handoff
+M_FLIST += hps_sdram_*.csv
+M_FLIST += *ddr3_*.csv
+M_FLIST += incremental_db
+M_FLIST += reconfig_mif
+M_FLIST += *.sopcinfo
+M_FLIST +=  *.jdi
+M_FLIST += *.pin
+
+
+
+.PHONY: all clean clean-all
+all: daq2_a10gx.sof
+
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+daq2_a10gx.sof: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_ALTERA) system_project.tcl  >> daq2_a10gx_quartus.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/projects/daq3/a10gx/system_bd.qsys b/projects/daq3/a10gx/system_bd.qsys
new file mode 100755
index 000000000..1a8f91dd9
--- /dev/null
+++ b/projects/daq3/a10gx/system_bd.qsys
@@ -0,0 +1,586 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element a10gx_base
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element a10gx_base.sys_mem_s_avl
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element daq2
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element daq2.axi_ad9144_core_s_axi
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9144_dma_s_axi
+   {
+      datum baseAddress
+      {
+         value = "212992";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9680_core_s_axi
+   {
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9680_dma_s_axi
+   {
+      datum baseAddress
+      {
+         value = "196608";
+         type = "String";
+      }
+   }
+   element daq2.axi_jesd_xcvr_s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="10AX115S3F45I2SGE2" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="daq2_a10gx.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_mem"
+   internal="a10gx_base.sys_ddr3_cntrl_mem"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_oct"
+   internal="a10gx_base.sys_ddr3_cntrl_oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_pll_ref_clk"
+   internal="a10gx_base.sys_ddr3_cntrl_pll_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_mdio"
+   internal="a10gx_base.sys_ethernet_mdio"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_ref_clk"
+   internal="a10gx_base.sys_ethernet_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_reset"
+   internal="a10gx_base.sys_ethernet_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="a10gx_base_sys_ethernet_sgmii"
+   internal="a10gx_base.sys_ethernet_sgmii"
+   type="conduit"
+   dir="end" />
+ <interface name="a10gx_base_sys_gpio" internal="a10gx_base.sys_gpio" />
+ <interface
+   name="a10gx_base_sys_gpio_bd"
+   internal="a10gx_base.sys_gpio_bd"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_gpio_in"
+   internal="a10gx_base.sys_gpio_in"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_gpio_out"
+   internal="a10gx_base.sys_gpio_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_spi"
+   internal="a10gx_base.sys_spi"
+   type="conduit"
+   dir="end" />
+ <interface name="daq2_rx_data" internal="daq2.rx_data" type="conduit" dir="end" />
+ <interface
+   name="daq2_rx_ref_clk"
+   internal="daq2.rx_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface name="daq2_rx_sync" internal="daq2.rx_sync" type="conduit" dir="end" />
+ <interface
+   name="daq2_rx_sysref"
+   internal="daq2.rx_sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="daq2_tx_data" internal="daq2.tx_data" type="conduit" dir="end" />
+ <interface
+   name="daq2_tx_ref_clk"
+   internal="daq2.tx_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface name="daq2_tx_sync" internal="daq2.tx_sync" type="conduit" dir="end" />
+ <interface
+   name="daq2_tx_sysref"
+   internal="daq2.tx_sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="sys_reset"
+   internal="sys_clk.clk_in_reset"
+   type="reset"
+   dir="end" />
+ <module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_RESET_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
+  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
+ </module>
+ <module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133333250" />
+  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
+  <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
+  <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_TX_REF_CLK_CLOCK_DOMAIN" value="5" />
+  <parameter name="AUTO_TX_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
+  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
+ </module>
+ <module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="daq2.axi_ad9144_dma_m_axi"
+   end="a10gx_base.sys_mem_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="daq2.axi_ad9680_dma_m_axi"
+   end="a10gx_base.sys_mem_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9144_core_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9144_dma_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00034000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9680_core_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9680_dma_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00030000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_jesd_xcvr_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.clk"
+   end="a10gx_base.sys_clk" />
+ <connection kind="clock" version="15.0" start="sys_clk.clk" end="daq2.sys_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="a10gx_base.mem_clk"
+   end="daq2.mem_clk" />
+ <connection
+   kind="interrupt"
+   version="15.0"
+   start="a10gx_base.sys_intr"
+   end="daq2.axi_ad9144_dma_intr">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.0"
+   start="a10gx_base.sys_intr"
+   end="daq2.axi_ad9680_dma_intr">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_clk.clk_reset"
+   end="a10gx_base.sys_rst" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_clk.clk_reset"
+   end="daq2.sys_rst" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="a10gx_base.mem_rst"
+   end="daq2.mem_rst" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+</system>
diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc
new file mode 100644
index 000000000..86ef79f85
--- /dev/null
+++ b/projects/daq3/a10gx/system_constr.sdc
@@ -0,0 +1,16 @@
+
+create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
+create_clock -period "2.000 ns"   -name rx_ref_clk_500mhz   [get_ports {rx_ref_clk}]
+create_clock -period "2.000 ns"   -name tx_ref_clk_500mhz   [get_ports {tx_ref_clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
+ 
diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl
new file mode 100644
index 000000000..664f75637
--- /dev/null
+++ b/projects/daq3/a10gx/system_project.tcl
@@ -0,0 +1,92 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new daq2_a10gx -overwrite
+
+source "../../common/a10gx/a10gx_system_assign.tcl"
+set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*"
+set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*"
+set_global_assignment -name QSYS_FILE system_bd.qsys
+
+set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
+set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
+set_global_assignment -name VERILOG_FILE system_top.v
+
+set_global_assignment -name SDC_FILE system_constr.sdc
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
+
+# lane interface
+
+set_location_assignment PIN_AJ8   -to rx_ref_clk            ; ## B20  FMCA_GBTCLK1_M2C_P
+set_location_assignment PIN_AJ7   -to "rx_ref_clk(n)"       ; ## B21  FMCA_GBTCLK1_M2C_N
+set_location_assignment PIN_AV5   -to rx_data[0]            ; ## A10  FMCA_DP3_M2C_P
+set_location_assignment PIN_AV6   -to "rx_data[0](n)"       ; ## A11  FMCA_DP3_M2C_N
+set_location_assignment PIN_AW7   -to rx_data[1]            ; ## C06  FMCA_DP0_M2C_P
+set_location_assignment PIN_AW8   -to "rx_data[1](n)"       ; ## C07  FMCA_DP0_M2C_N
+set_location_assignment PIN_AY5   -to rx_data[2]            ; ## A06  FMCA_DP2_M2C_P
+set_location_assignment PIN_AY6   -to "rx_data[2](n)"       ; ## A07  FMCA_DP2_M2C_N
+set_location_assignment PIN_BA7   -to rx_data[3]            ; ## A02  FMCA_DP1_M2C_P
+set_location_assignment PIN_BA8   -to "rx_data[3](n)"       ; ## A03  FMCA_DP1_M2C_N
+set_location_assignment PIN_AT10  -to rx_sync               ; ## D08  FMCA_LA01_CC_P
+set_location_assignment PIN_AR11  -to "rx_sync(n)"          ; ## D09  FMCA_LA01_CC_N
+set_location_assignment PIN_AR20  -to rx_sysref             ; ## G09  FMCA_LA03_P
+set_location_assignment PIN_AR19  -to "rx_sysref(n)"        ; ## G10  FMCA_LA03_N
+set_location_assignment PIN_AL8   -to tx_ref_clk            ; ## D04  FMCA_GBTCLK0_M2C_P
+set_location_assignment PIN_AL7   -to "tx_ref_clk(n)"       ; ## D05  FMCA_GBTCLK0_M2C_N
+set_location_assignment PIN_BC3   -to tx_data[0]            ; ## A30  FMCA_DP3_C2M_P (tx_data_p[0])
+set_location_assignment PIN_BC4   -to "tx_data[0](n)"       ; ## A31  FMCA_DP3_C2M_N (tx_data_n[0])
+set_location_assignment PIN_BC7   -to tx_data[1]            ; ## C02  FMCA_DP0_C2M_P (tx_data_p[3])
+set_location_assignment PIN_BC8   -to "tx_data[1](n)"       ; ## C03  FMCA_DP0_C2M_N (tx_data_n[3])
+set_location_assignment PIN_BB5   -to tx_data[2]            ; ## A26  FMCA_DP2_C2M_P (tx_data_p[1])
+set_location_assignment PIN_BB6   -to "tx_data[2](n)"       ; ## A27  FMCA_DP2_C2M_N (tx_data_n[1])
+set_location_assignment PIN_BD5   -to tx_data[3]            ; ## A22  FMCA_DP1_C2M_P (tx_data_p[2])
+set_location_assignment PIN_BD6   -to "tx_data[3](n)"       ; ## A23  FMCA_DP1_C2M_N (tx_data_n[2])
+set_location_assignment PIN_AR22  -to tx_sync               ; ## H07  FMCA_LA02_P
+set_location_assignment PIN_AT22  -to "tx_sync(n)"          ; ## H08  FMCA_LA02_N
+set_location_assignment PIN_AN20  -to tx_sysref             ; ## H10  FMCA_LA04_P
+set_location_assignment PIN_AP19  -to "tx_sysref(n)"        ; ## H11  FMCA_LA04_N
+
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
+
+# gpio
+
+set_location_assignment PIN_AT17  -to trig                  ; ## H13  FMCA_LA07_P
+set_location_assignment PIN_AU17  -to "trig(n)"             ; ## H14  FMCA_LA07_N
+set_location_assignment PIN_AR14  -to adc_fdb               ; ## H17  FMCA_LA11_N
+set_location_assignment PIN_AT14  -to adc_fda               ; ## H16  FMCA_LA11_P
+set_location_assignment PIN_AR16  -to dac_irq               ; ## G15  FMCA_LA12_P
+set_location_assignment PIN_AP17  -to clkd_status[1]        ; ## D18  FMCA_LA13_N
+set_location_assignment PIN_AR17  -to clkd_status[0]        ; ## D17  FMCA_LA13_P
+set_location_assignment PIN_AV14  -to adc_pd                ; ## C10  FMCA_LA06_P
+set_location_assignment PIN_AP16  -to dac_txen              ; ## G16  FMCA_LA12_N
+set_location_assignment PIN_AT15  -to dac_reset             ; ## C15  FMCA_LA10_N
+set_location_assignment PIN_AP18  -to clkd_sync             ; ## G12  FMCA_LA08_P
+
+set_instance_assignment -name IO_STANDARD LVDS -to trig
+
+# spi
+
+set_location_assignment PIN_AV11  -to spi_csn_clk           ; ## D11  FMCA_LA05_P
+set_location_assignment PIN_AR15  -to spi_csn_dac           ; ## C14  FMCA_LA10_P
+set_location_assignment PIN_AV13  -to spi_csn_adc           ; ## D15  FMCA_LA09_N
+set_location_assignment PIN_AW11  -to spi_clk               ; ## D12  FMCA_LA05_N
+set_location_assignment PIN_AW13  -to spi_sdio              ; ## D14  FMCA_LA09_P
+set_location_assignment PIN_AN19  -to spi_dir               ; ## G13  FMCA_LA08_N
+
+execute_flow -compile
+
diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v
new file mode 100644
index 000000000..9b16e7693
--- /dev/null
+++ b/projects/daq3/a10gx/system_top.v
@@ -0,0 +1,274 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  sys_clk,
+  sys_resetn,
+
+  // ddr3
+
+  ddr3_clk_p,
+  ddr3_clk_n,
+  ddr3_a,
+  ddr3_ba,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_odt,
+  ddr3_reset_n,
+  ddr3_we_n,
+  ddr3_ras_n,
+  ddr3_cas_n,
+  ddr3_dqs_p,
+  ddr3_dqs_n,
+  ddr3_dq,
+  ddr3_dm,
+  ddr3_rzq,
+  ddr3_ref_clk,
+
+  // ethernet
+
+  eth_ref_clk,
+  eth_rxd,
+  eth_txd,
+  eth_mdc,
+  eth_mdio,
+  eth_resetn,
+  eth_intn,
+
+  // board gpio
+
+  gpio_bd,
+
+  // lane interface
+
+  rx_ref_clk,
+  rx_sysref,
+  rx_sync,
+  rx_data,
+  tx_ref_clk,
+  tx_sysref,
+  tx_sync,
+  tx_data,
+
+  // gpio
+
+  trig,
+  adc_fdb,
+  adc_fda,
+  dac_irq,
+  clkd_status,
+  adc_pd,
+  dac_txen,
+  dac_reset,
+  clkd_sync,
+
+  // spi
+
+  spi_csn_clk,
+  spi_csn_dac,
+  spi_csn_adc,
+  spi_clk,
+  spi_sdio,
+  spi_dir);
+
+  // clock and resets
+
+  input             sys_clk;
+  input             sys_resetn;
+
+  // ddr3
+
+  output            ddr3_clk_p;
+  output            ddr3_clk_n;
+  output  [ 14:0]   ddr3_a;
+  output  [  2:0]   ddr3_ba;
+  output            ddr3_cke;
+  output            ddr3_cs_n;
+  output            ddr3_odt;
+  output            ddr3_reset_n;
+  output            ddr3_we_n;
+  output            ddr3_ras_n;
+  output            ddr3_cas_n;
+  inout   [  7:0]   ddr3_dqs_p;
+  inout   [  7:0]   ddr3_dqs_n;
+  inout   [ 63:0]   ddr3_dq;
+  output  [  7:0]   ddr3_dm;
+  input             ddr3_rzq;
+  input             ddr3_ref_clk;
+
+  // ethernet
+
+  input             eth_ref_clk;
+  input             eth_rxd;
+  output            eth_txd;
+  output            eth_mdc;
+  inout             eth_mdio;
+  output            eth_resetn;
+  input             eth_intn;
+
+  // board gpio
+
+  inout   [ 26:0]   gpio_bd;
+
+  // lane interface
+
+  input             rx_ref_clk;
+  input             rx_sysref;
+  output            rx_sync;
+  input   [  3:0]   rx_data;
+  input             tx_ref_clk;
+  input             tx_sysref;
+  input             tx_sync;
+  output  [  3:0]   tx_data;
+
+  // gpio
+
+  input             trig;
+  input             adc_fdb;
+  input             adc_fda;
+  input             dac_irq;
+  input   [  1:0]   clkd_status;
+  output            adc_pd;
+  output            dac_txen;
+  output            dac_reset;
+  output            clkd_sync;
+
+  // spi
+
+  output            spi_csn_clk;
+  output            spi_csn_dac;
+  output            spi_csn_adc;
+  output            spi_clk;
+  inout             spi_sdio;
+  output            spi_dir;
+
+  // internal signals
+
+  wire              eth_reset;
+  wire              eth_mdio_i;
+  wire              eth_mdio_o;
+  wire              eth_mdio_t;
+  wire    [ 31:0]   gpio_i;
+  wire    [ 31:0]   gpio_o;
+  wire              spi_miso_s;
+  wire              spi_mosi_s;
+  wire    [  7:0]   spi_csn_s;
+
+  // daq2
+
+  assign spi_csn_adc = spi_csn_s[2];
+  assign spi_csn_dac = spi_csn_s[1];
+  assign spi_csn_clk = spi_csn_s[0];
+
+  daq2_spi i_daq2_spi (
+    .spi_csn (spi_csn_s[2:0]),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi_s),
+    .spi_miso (spi_miso_s),
+    .spi_sdio (spi_sdio),
+    .spi_dir (spi_dir));
+
+  // board stuff
+
+  assign eth_resetn = ~eth_reset;
+  assign eth_mdio_i = eth_mdio;
+  assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
+
+  assign ddr3_a[14:12] = 3'd0;
+
+  assign gpio_i[31:27] = gpio_o[31:27];
+
+  ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
+    .dio_t ({11'h7ff, 16'h0}),
+    .dio_i (gpio_o[26:0]),
+    .dio_o (gpio_i[26:0]),
+    .dio_p (gpio_bd));
+
+  system_bd i_system_bd (
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
+    .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
+    .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc),
+    .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
+    .a10gx_base_sys_ethernet_reset_reset (eth_reset),
+    .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
+    .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
+    .a10gx_base_sys_gpio_in_export ({trig, adc_fdb, adc_fda, dac_irq, clkd_status[1], clkd_status[0]}),
+    .a10gx_base_sys_gpio_out_export ({adc_pd, dac_txen, dac_reset, clkd_sync}),
+    .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
+    .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
+    .a10gx_base_sys_spi_MISO (spi_miso_s),
+    .a10gx_base_sys_spi_MOSI (spi_mosi_s),
+    .a10gx_base_sys_spi_SCLK (spi_clk),
+    .a10gx_base_sys_spi_SS_n (spi_csn_s),
+    .daq2_rx_data_rx_serial_data (rx_data),
+    .daq2_rx_ref_clk_clk (rx_ref_clk),
+    .daq2_rx_sync_rx_sync (rx_sync),
+    .daq2_rx_sysref_rx_ext_sysref_in (rx_sysref),
+    .daq2_tx_data_tx_serial_data (tx_data),
+    .daq2_tx_ref_clk_clk (tx_ref_clk),
+    .daq2_tx_sync_tx_sync (tx_sync),
+    .daq2_tx_sysref_tx_ext_sysref_in (tx_sysref),
+    .sys_clk_clk (sys_clk),
+    .sys_reset_reset_n (sys_resetn));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 614babc18efdd20eeb8b927dd8c993c587bc02d5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 09:41:47 -0500
Subject: [PATCH 014/972] daq3/kcu105: copy

---
 projects/daq3/kcu105/Makefile           |  84 ++++++
 projects/daq3/kcu105/system_bd.tcl      |  14 +
 projects/daq3/kcu105/system_constr.xdc  |  69 +++++
 projects/daq3/kcu105/system_project.tcl |  21 ++
 projects/daq3/kcu105/system_top.v       | 359 ++++++++++++++++++++++++
 5 files changed, 547 insertions(+)
 create mode 100644 projects/daq3/kcu105/Makefile
 create mode 100644 projects/daq3/kcu105/system_bd.tcl
 create mode 100644 projects/daq3/kcu105/system_constr.xdc
 create mode 100644 projects/daq3/kcu105/system_project.tcl
 create mode 100644 projects/daq3/kcu105/system_top.v

diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
new file mode 100644
index 000000000..6c51e2d2d
--- /dev/null
+++ b/projects/daq3/kcu105/Makefile
@@ -0,0 +1,84 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/daq2_spi.v
+M_DEPS += ../common/daq2_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
+M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
+M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
+M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib daq2_kcu105.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9144 clean
+	make -C ../../../library/axi_ad9680 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_dacfifo clean
+	make -C ../../../library/util_jesd_gt clean
+	make -C ../../../library/util_upack clean
+
+
+daq2_kcu105.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> daq2_kcu105_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9144
+	make -C ../../../library/axi_ad9680
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/util_adcfifo
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_dacfifo
+	make -C ../../../library/util_jesd_gt
+	make -C ../../../library/util_upack
+
+####################################################################################
+####################################################################################
diff --git a/projects/daq3/kcu105/system_bd.tcl b/projects/daq3/kcu105/system_bd.tcl
new file mode 100644
index 000000000..644363e8d
--- /dev/null
+++ b/projects/daq3/kcu105/system_bd.tcl
@@ -0,0 +1,14 @@
+
+source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+
+p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
+p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
+
+source ../common/daq2_bd.tcl
+
+set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $axi_daq2_gt
+set_property -dict [list CONFIG.QPLL0_FBDIV {20}] $axi_daq2_gt
+set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_daq2_gt
+
+
diff --git a/projects/daq3/kcu105/system_constr.xdc b/projects/daq3/kcu105/system_constr.xdc
new file mode 100644
index 000000000..44a8f125c
--- /dev/null
+++ b/projects/daq3/kcu105/system_constr.xdc
@@ -0,0 +1,69 @@
+
+# daq2
+
+set_property  -dict {PACKAGE_PIN  H6} [get_ports rx_ref_clk_p]                                              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  H5} [get_ports rx_ref_clk_n]                                              ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  G9  IOSTANDARD LVDS} [get_ports rx_sync_p]                                ; ## D08  FMC_HPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  F9  IOSTANDARD LVDS} [get_ports rx_sync_n]                                ; ## D09  FMC_HPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  A13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p]       ; ## G09  FMC_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  A12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n]       ; ## G10  FMC_HPC_LA03_N
+
+set_property  -dict {PACKAGE_PIN  K6} [get_ports tx_ref_clk_p]                                              ; ## D04  FMC_HPC_GBTCLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  K5} [get_ports tx_ref_clk_n]                                              ; ## D05  FMC_HPC_GBTCLK0_M2C_N
+set_property  -dict {PACKAGE_PIN  K10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p]         ; ## H07  FMC_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  J10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n]         ; ## H08  FMC_HPC_LA02_N
+set_property  -dict {PACKAGE_PIN  L12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p]       ; ## H10  FMC_HPC_LA04_P
+set_property  -dict {PACKAGE_PIN  K12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n]       ; ## H11  FMC_HPC_LA04_N
+
+set_property  -dict {PACKAGE_PIN  L13 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk]                          ; ## D11  FMC_HPC_LA05_P
+set_property  -dict {PACKAGE_PIN  L8  IOSTANDARD LVCMOS18} [get_ports spi_csn_dac]                          ; ## C14  FMC_HPC_LA10_P
+set_property  -dict {PACKAGE_PIN  H9  IOSTANDARD LVCMOS18} [get_ports spi_csn_adc]                          ; ## D15  FMC_HPC_LA09_N
+set_property  -dict {PACKAGE_PIN  K13 IOSTANDARD LVCMOS18} [get_ports spi_clk]                              ; ## D12  FMC_HPC_LA05_N
+set_property  -dict {PACKAGE_PIN  J9  IOSTANDARD LVCMOS18} [get_ports spi_sdio]                             ; ## D14  FMC_HPC_LA09_P
+set_property  -dict {PACKAGE_PIN  H8  IOSTANDARD LVCMOS18} [get_ports spi_dir]                              ; ## G13  FMC_HPC_LA08_N
+
+set_property  -dict {PACKAGE_PIN  J8  IOSTANDARD LVCMOS18} [get_ports clkd_sync]                            ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  K8  IOSTANDARD LVCMOS18} [get_ports dac_reset]                            ; ## C15  FMC_HPC_LA10_N
+set_property  -dict {PACKAGE_PIN  D10 IOSTANDARD LVCMOS18} [get_ports dac_txen]                             ; ## G16  FMC_HPC_LA12_N
+set_property  -dict {PACKAGE_PIN  D13 IOSTANDARD LVCMOS18} [get_ports adc_pd]                               ; ## C10  FMC_HPC_LA06_P
+
+set_property  -dict {PACKAGE_PIN  D9  IOSTANDARD LVCMOS18} [get_ports clkd_status[0]]                       ; ## D17  FMC_HPC_LA13_P
+set_property  -dict {PACKAGE_PIN  C9  IOSTANDARD LVCMOS18} [get_ports clkd_status[1]]                       ; ## D18  FMC_HPC_LA13_N
+set_property  -dict {PACKAGE_PIN  E10 IOSTANDARD LVCMOS18} [get_ports dac_irq]                              ; ## G15  FMC_HPC_LA12_P
+set_property  -dict {PACKAGE_PIN  K11 IOSTANDARD LVCMOS18} [get_ports adc_fda]                              ; ## H16  FMC_HPC_LA11_P
+set_property  -dict {PACKAGE_PIN  J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb]                              ; ## H17  FMC_HPC_LA11_N
+
+set_property  -dict {PACKAGE_PIN  F8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p]            ; ## H13  FMC_HPC_LA07_P          
+set_property  -dict {PACKAGE_PIN  E8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n]            ; ## H14  FMC_HPC_LA07_N          
+
+# clocks
+
+create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
+create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/RXOUTCLK]
+
+# gt pin assignments below are for reference only and are ignored by the tool!
+
+##  set_property  -dict {PACKAGE_PIN  A4} [get_ports rx_data_p[0]] ; ## A10  FMC_HPC_DP3_M2C_P
+##  set_property  -dict {PACKAGE_PIN  A3} [get_ports rx_data_n[0]] ; ## A11  FMC_HPC_DP3_M2C_N
+##  set_property  -dict {PACKAGE_PIN  E4} [get_ports rx_data_p[1]] ; ## C06  FMC_HPC_DP0_M2C_P
+##  set_property  -dict {PACKAGE_PIN  E3} [get_ports rx_data_n[1]] ; ## C07  FMC_HPC_DP0_M2C_N
+##  set_property  -dict {PACKAGE_PIN  B2} [get_ports rx_data_p[2]] ; ## A06  FMC_HPC_DP2_M2C_P
+##  set_property  -dict {PACKAGE_PIN  B1} [get_ports rx_data_n[2]] ; ## A07  FMC_HPC_DP2_M2C_N
+##  set_property  -dict {PACKAGE_PIN  D2} [get_ports rx_data_p[3]] ; ## A02  FMC_HPC_DP1_M2C_P
+##  set_property  -dict {PACKAGE_PIN  D1} [get_ports rx_data_n[3]] ; ## A03  FMC_HPC_DP1_M2C_N
+##  set_property  -dict {PACKAGE_PIN  B6} [get_ports tx_data_p[0]] ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[0])
+##  set_property  -dict {PACKAGE_PIN  B5} [get_ports tx_data_n[0]] ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[0])
+##  set_property  -dict {PACKAGE_PIN  F6} [get_ports tx_data_p[1]] ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[3])
+##  set_property  -dict {PACKAGE_PIN  F5} [get_ports tx_data_n[1]] ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[3])
+##  set_property  -dict {PACKAGE_PIN  C4} [get_ports tx_data_p[2]] ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[1])
+##  set_property  -dict {PACKAGE_PIN  C3} [get_ports tx_data_n[2]] ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[1])
+##  set_property  -dict {PACKAGE_PIN  D6} [get_ports tx_data_p[3]] ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
+##  set_property  -dict {PACKAGE_PIN  D5} [get_ports tx_data_n[3]] ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
+
+set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[1].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[2].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[3].i_channel/i_gt/i_gthe3_channel}]
+
diff --git a/projects/daq3/kcu105/system_project.tcl b/projects/daq3/kcu105/system_project.tcl
new file mode 100644
index 000000000..5d2541fd6
--- /dev/null
+++ b/projects/daq3/kcu105/system_project.tcl
@@ -0,0 +1,21 @@
+
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create daq2_kcu105
+adi_project_files daq2_kcu105 [list \
+  "../common/daq2_spi.v" \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
+
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+
+adi_project_run daq2_kcu105
+
+
diff --git a/projects/daq3/kcu105/system_top.v b/projects/daq3/kcu105/system_top.v
new file mode 100644
index 000000000..fbf439919
--- /dev/null
+++ b/projects/daq3/kcu105/system_top.v
@@ -0,0 +1,359 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  sys_rst,
+  sys_clk_p,
+  sys_clk_n,
+
+  uart_sin,
+  uart_sout,
+
+  ddr4_act_n,
+  ddr4_addr,
+  ddr4_ba,
+  ddr4_bg,
+  ddr4_ck_p,
+  ddr4_ck_n,
+  ddr4_cke,
+  ddr4_cs_n,
+  ddr4_dm_n,
+  ddr4_dq,
+  ddr4_dqs_p,
+  ddr4_dqs_n,
+  ddr4_odt,
+  ddr4_reset_n,
+
+  mdio_mdc,
+  mdio_mdio,
+  phy_clk_p,
+  phy_clk_n,
+  phy_rst_n,
+  phy_rx_p,
+  phy_rx_n,
+  phy_tx_p,
+  phy_tx_n,
+
+  fan_pwm,
+
+  gpio_bd,
+
+  iic_scl,
+  iic_sda,
+
+  rx_ref_clk_p,
+  rx_ref_clk_n,
+  rx_sysref_p,
+  rx_sysref_n,
+  rx_sync_p,
+  rx_sync_n,
+  rx_data_p,
+  rx_data_n,
+
+  tx_ref_clk_p,
+  tx_ref_clk_n,
+  tx_sysref_p,
+  tx_sysref_n,
+  tx_sync_p,
+  tx_sync_n,
+  tx_data_p,
+  tx_data_n,
+
+  trig_p,
+  trig_n,
+
+  adc_fdb,
+  adc_fda,
+  dac_irq,
+  clkd_status,
+
+  adc_pd,
+  dac_txen,
+  dac_reset,
+  clkd_sync,
+
+  spi_csn_clk,
+  spi_csn_dac,
+  spi_csn_adc,
+  spi_clk,
+  spi_sdio,
+  spi_dir);
+
+  input           sys_rst;
+  input           sys_clk_p;
+  input           sys_clk_n;
+
+  input           uart_sin;
+  output          uart_sout;
+
+  output          ddr4_act_n;
+  output  [16:0]  ddr4_addr;
+  output  [ 1:0]  ddr4_ba;
+  output  [ 0:0]  ddr4_bg;
+  output          ddr4_ck_p;
+  output          ddr4_ck_n;
+  output  [ 0:0]  ddr4_cke;
+  output  [ 0:0]  ddr4_cs_n;
+  inout   [ 7:0]  ddr4_dm_n;
+  inout   [63:0]  ddr4_dq;
+  inout   [ 7:0]  ddr4_dqs_p;
+  inout   [ 7:0]  ddr4_dqs_n;
+  output  [ 0:0]  ddr4_odt;
+  output          ddr4_reset_n;
+
+  output          mdio_mdc;
+  inout           mdio_mdio;
+  input           phy_clk_p;
+  input           phy_clk_n;
+  output          phy_rst_n;
+  input           phy_rx_p;
+  input           phy_rx_n;
+  output          phy_tx_p;
+  output          phy_tx_n;
+
+  output          fan_pwm;
+
+  inout   [16:0]  gpio_bd;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  input           rx_ref_clk_p;
+  input           rx_ref_clk_n;
+  input           rx_sysref_p;
+  input           rx_sysref_n;
+  output          rx_sync_p;
+  output          rx_sync_n;
+  input   [ 3:0]  rx_data_p;
+  input   [ 3:0]  rx_data_n;
+
+  input           tx_ref_clk_p;
+  input           tx_ref_clk_n;
+  input           tx_sysref_p;
+  input           tx_sysref_n;
+  input           tx_sync_p;
+  input           tx_sync_n;
+  output  [ 3:0]  tx_data_p;
+  output  [ 3:0]  tx_data_n;
+
+  input           trig_p;
+  input           trig_n;
+
+  inout           adc_fdb;
+  inout           adc_fda;
+  inout           dac_irq;
+  inout   [ 1:0]  clkd_status;
+
+  inout           adc_pd;
+  inout           dac_txen;
+  inout           dac_reset;
+  inout           clkd_sync;
+
+  output          spi_csn_clk;
+  output          spi_csn_dac;
+  output          spi_csn_adc;
+  output          spi_clk;
+  inout           spi_sdio;
+  output          spi_dir;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire    [ 7:0]  spi_csn;
+  wire            spi_mosi;
+  wire            spi_miso;
+  wire            trig;
+  wire            rx_ref_clk;
+  wire            rx_sysref;
+  wire            rx_sync;
+  wire            tx_ref_clk;
+  wire            tx_sysref;
+  wire            tx_sync;
+
+  // spi
+
+  assign spi_csn_adc = spi_csn[2];
+  assign spi_csn_dac = spi_csn[1];
+  assign spi_csn_clk = spi_csn[0];
+
+  // default logic
+
+  assign fan_pwm = 1'b1;
+
+  // instantiations
+
+  IBUFDS_GTE3 i_ibufds_rx_ref_clk (
+    .CEB (1'd0),
+    .I (rx_ref_clk_p),
+    .IB (rx_ref_clk_n),
+    .O (rx_ref_clk),
+    .ODIV2 ());
+
+  IBUFDS i_ibufds_rx_sysref (
+    .I (rx_sysref_p),
+    .IB (rx_sysref_n),
+    .O (rx_sysref));
+
+  OBUFDS i_obufds_rx_sync (
+    .I (rx_sync),
+    .O (rx_sync_p),
+    .OB (rx_sync_n));
+
+  IBUFDS_GTE3 i_ibufds_tx_ref_clk (
+    .CEB (1'd0),
+    .I (tx_ref_clk_p),
+    .IB (tx_ref_clk_n),
+    .O (tx_ref_clk),
+    .ODIV2 ());
+
+  IBUFDS i_ibufds_tx_sysref (
+    .I (tx_sysref_p),
+    .IB (tx_sysref_n),
+    .O (tx_sysref));
+
+  IBUFDS i_ibufds_tx_sync (
+    .I (tx_sync_p),
+    .IB (tx_sync_n),
+    .O (tx_sync));
+
+  daq2_spi i_spi (
+    .spi_csn (spi_csn[2:0]),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_sdio (spi_sdio),
+    .spi_dir (spi_dir));
+
+  IBUFDS i_ibufds_trig (
+    .I (trig_p),
+    .IB (trig_n),
+    .O (trig));
+
+  assign gpio_i[43] = trig;
+
+  ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
+    .dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
+    .dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
+    .dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
+    .dio_p ({ adc_pd,           // 42
+              dac_txen,         // 41
+              dac_reset,        // 40
+              clkd_sync,        // 38
+              adc_fdb,          // 36
+              adc_fda,          // 35
+              dac_irq,          // 34
+              clkd_status}));   // 32
+
+  ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
+    .dio_t (gpio_t[16:0]),
+    .dio_i (gpio_o[16:0]),
+    .dio_o (gpio_i[16:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .c0_ddr4_act_n (ddr4_act_n),
+    .c0_ddr4_adr (ddr4_addr),
+    .c0_ddr4_ba (ddr4_ba),
+    .c0_ddr4_bg (ddr4_bg),
+    .c0_ddr4_ck_c (ddr4_ck_n),
+    .c0_ddr4_ck_t (ddr4_ck_p),
+    .c0_ddr4_cke (ddr4_cke),
+    .c0_ddr4_cs_n (ddr4_cs_n),
+    .c0_ddr4_dm_n (ddr4_dm_n),
+    .c0_ddr4_dq (ddr4_dq),
+    .c0_ddr4_dqs_c (ddr4_dqs_n),
+    .c0_ddr4_dqs_t (ddr4_dqs_p),
+    .c0_ddr4_odt (ddr4_odt),
+    .c0_ddr4_reset_n (ddr4_reset_n),
+    .gpio0_i (gpio_i[31:0]),
+    .gpio0_o (gpio_o[31:0]),
+    .gpio0_t (gpio_t[31:0]),
+    .gpio1_i (gpio_i[63:32]),
+    .gpio1_o (gpio_o[63:32]),
+    .gpio1_t (gpio_t[63:32]),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .mb_intr_05 (1'b0),
+    .mb_intr_06 (1'b0),
+    .mb_intr_07 (1'b0),
+    .mb_intr_08 (1'b0),
+    .mb_intr_14 (1'b0),
+    .mb_intr_15 (1'b0),
+    .mdio_mdc (mdio_mdc),
+    .mdio_mdio_io (mdio_mdio),
+    .phy_clk_clk_n (phy_clk_n),
+    .phy_clk_clk_p (phy_clk_p),
+    .phy_rst_n (phy_rst_n),
+    .phy_sd (1'b1),
+    .rx_data_n (rx_data_n),
+    .rx_data_p (rx_data_p),
+    .rx_ref_clk (rx_ref_clk),
+    .rx_sync (rx_sync),
+    .rx_sysref (rx_sysref),
+    .sgmii_rxn (phy_rx_n),
+    .sgmii_rxp (phy_rx_p),
+    .sgmii_txn (phy_tx_n),
+    .sgmii_txp (phy_tx_p),
+    .spi_clk_i (spi_clk),
+    .spi_clk_o (spi_clk),
+    .spi_csn_i (spi_csn),
+    .spi_csn_o (spi_csn),
+    .spi_sdi_i (spi_miso),
+    .spi_sdo_i (spi_mosi),
+    .spi_sdo_o (spi_mosi),
+    .sys_clk_clk_n (sys_clk_n),
+    .sys_clk_clk_p (sys_clk_p),
+    .sys_rst (sys_rst),
+    .tx_data_n (tx_data_n),
+    .tx_data_p (tx_data_p),
+    .tx_ref_clk (tx_ref_clk),
+    .tx_sync (tx_sync),
+    .tx_sysref (tx_sysref),
+    .uart_sin (uart_sin),
+    .uart_sout (uart_sout));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 1a38ea205da0612048af7ba7aceaba519061286a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 09:42:56 -0500
Subject: [PATCH 015/972] daq3/a10gx: copy

---
 projects/daq3/common/daq3_bd.qsys | 2258 +++++++++++++++++++++++++++++
 1 file changed, 2258 insertions(+)
 create mode 100755 projects/daq3/common/daq3_bd.qsys

diff --git a/projects/daq3/common/daq3_bd.qsys b/projects/daq3/common/daq3_bd.qsys
new file mode 100755
index 000000000..836c28c8e
--- /dev/null
+++ b/projects/daq3/common/daq3_bd.qsys
@@ -0,0 +1,2258 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element ad9680_adcfifo
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element axi_ad9144_core
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element axi_ad9144_core.s_axi
+   {
+      datum baseAddress
+      {
+         value = "269025280";
+         type = "String";
+      }
+   }
+   element axi_ad9144_dma
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element axi_ad9144_dma.s_axi
+   {
+      datum baseAddress
+      {
+         value = "269156352";
+         type = "String";
+      }
+   }
+   element axi_ad9680_core
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element axi_ad9680_core.s_axi
+   {
+      datum baseAddress
+      {
+         value = "269090816";
+         type = "String";
+      }
+   }
+   element axi_ad9680_dma
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_ad9680_dma.s_axi
+   {
+      datum baseAddress
+      {
+         value = "269172736";
+         type = "String";
+      }
+   }
+   element axi_jesd_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element axi_jesd_xcvr.s_axi
+   {
+      datum baseAddress
+      {
+         value = "268959744";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element daq2_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element mem_clk
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element mem_rst
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_rst
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element util_cpack_0
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element util_upack_0
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element xcvr_core
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element xcvr_rst_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element xcvr_rx_pll
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element xcvr_rx_ref_clk
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element xcvr_tx_lane_pll
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element xcvr_tx_pll
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element xcvr_tx_ref_clk
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="10AX115S3F45I2SGE2" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="axi_ad9144_core_s_axi"
+   internal="axi_ad9144_core.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_ad9144_dma_intr"
+   internal="axi_ad9144_dma.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_ad9144_dma_m_axi"
+   internal="axi_ad9144_dma.m_src_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_ad9144_dma_s_axi"
+   internal="axi_ad9144_dma.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_ad9680_core_s_axi"
+   internal="axi_ad9680_core.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_ad9680_dma_intr"
+   internal="axi_ad9680_dma.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_ad9680_dma_m_axi"
+   internal="axi_ad9680_dma.m_dest_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_ad9680_dma_s_axi"
+   internal="axi_ad9680_dma.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_jesd_xcvr_s_axi"
+   internal="axi_jesd_xcvr.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
+ <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
+ <interface
+   name="rx_data"
+   internal="xcvr_core.rx_serial_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ref_clk"
+   internal="xcvr_rx_ref_clk.in_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="rx_sync"
+   internal="axi_jesd_xcvr.if_rx_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_sysref"
+   internal="axi_jesd_xcvr.if_rx_ext_sysref_in"
+   type="conduit"
+   dir="end" />
+ <interface name="stp_trigger" internal="axi_jesd_xcvr.if_stp_trigger" />
+ <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
+ <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
+ <interface
+   name="tx_data"
+   internal="xcvr_core.tx_serial_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="tx_ref_clk"
+   internal="xcvr_tx_ref_clk.in_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="tx_sync"
+   internal="axi_jesd_xcvr.if_tx_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="tx_sysref"
+   internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
+   type="conduit"
+   dir="end" />
+ <module name="ad9680_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
+  <parameter name="ADC_DATA_WIDTH" value="128" />
+  <parameter name="DMA_ADDRESS_WIDTH" value="16" />
+  <parameter name="DMA_DATA_WIDTH" value="128" />
+  <parameter name="DMA_READY_ENABLE" value="1" />
+ </module>
+ <module name="axi_ad9144_core" kind="axi_ad9144" version="1.0" enabled="1">
+  <parameter name="ID" value="0" />
+  <parameter name="QUAD_OR_DUAL_N" value="0" />
+ </module>
+ <module name="axi_ad9144_dma" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="1" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
+  <parameter name="DMA_LENGTH_WIDTH" value="14" />
+  <parameter name="DMA_TYPE_DEST" value="2" />
+  <parameter name="DMA_TYPE_SRC" value="0" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="0" />
+ </module>
+ <module name="axi_ad9680_core" kind="axi_ad9680" version="1.0" enabled="1">
+  <parameter name="ID" value="0" />
+ </module>
+ <module name="axi_ad9680_dma" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="0" />
+  <parameter name="DMA_TYPE_SRC" value="1" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
+ </module>
+ <module name="axi_jesd_xcvr" kind="axi_jesd_xcvr" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="0" />
+  <parameter name="RX_NUM_OF_LANES" value="4" />
+  <parameter name="TX_NUM_OF_LANES" value="4" />
+ </module>
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="125000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="util_cpack_0" kind="util_cpack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="64" />
+  <parameter name="NUM_OF_CHANNELS" value="2" />
+ </module>
+ <module name="util_upack_0" kind="util_upack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="64" />
+  <parameter name="NUM_OF_CHANNELS" value="2" />
+ </module>
+ <module name="xcvr_core" kind="altera_jesd204" version="15.0" enabled="1">
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="BID" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="CS" value="0" />
+  <parameter name="DATA_PATH" value="RX_TX" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DID" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="GUI_CFG_F" value="1" />
+  <parameter name="GUI_EN_CFG_F" value="true" />
+  <parameter name="HD" value="1" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="K" value="32" />
+  <parameter name="L" value="4" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="M" value="2" />
+  <parameter name="N" value="16" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG2" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="REFCLK_FREQ" value="500.0" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="S" value="1" />
+  <parameter name="SCR" value="1" />
+  <parameter name="SUBCLASSV" value="1" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="bonded_mode" value="non_bonded" />
+  <parameter name="lane_rate" value="10000.0" />
+  <parameter name="part_trait_bd" value="NIGHTFURY5ES2" />
+  <parameter name="part_trait_dp" value="10AX115S3F45I2SGE2" />
+  <parameter name="pll_reconfig_enable" value="false" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="rcfg_jtag_enable" value="false" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="set_capability_reg_enable" value="false" />
+  <parameter name="set_csr_soft_logic_enable" value="false" />
+  <parameter name="set_prbs_soft_logic_enable" value="false" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="wrapper_opt" value="base_phy" />
+ </module>
+ <module
+   name="xcvr_rst_cntrl"
+   kind="altera_xcvr_reset_control"
+   version="15.0"
+   enabled="1">
+  <parameter name="CHANNELS" value="4" />
+  <parameter name="PLLS" value="1" />
+  <parameter name="REDUCED_SIM_TIME" value="1" />
+  <parameter name="RX_ENABLE" value="1" />
+  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+  <parameter name="SYNCHRONIZE_RESET" value="1" />
+  <parameter name="SYS_CLK_IN_MHZ" value="100" />
+  <parameter name="TX_ENABLE" value="1" />
+  <parameter name="TX_PER_CHANNEL" value="0" />
+  <parameter name="TX_PLL_ENABLE" value="1" />
+  <parameter name="T_PLL_LOCK_HYST" value="0" />
+  <parameter name="T_PLL_POWERDOWN" value="1000" />
+  <parameter name="T_RX_ANALOGRESET" value="40" />
+  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_DIGITALRESET" value="20" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="gui_pll_cal_busy" value="1" />
+  <parameter name="gui_rx_auto_reset" value="0" />
+  <parameter name="gui_split_interfaces" value="0" />
+  <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <module name="xcvr_rx_pll" kind="altera_iopll" version="15.0" enabled="1">
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_duty_cycle0" value="50.0" />
+  <parameter name="gui_actual_duty_cycle1" value="50.0" />
+  <parameter name="gui_actual_duty_cycle10" value="50.0" />
+  <parameter name="gui_actual_duty_cycle11" value="50.0" />
+  <parameter name="gui_actual_duty_cycle12" value="50.0" />
+  <parameter name="gui_actual_duty_cycle13" value="50.0" />
+  <parameter name="gui_actual_duty_cycle14" value="50.0" />
+  <parameter name="gui_actual_duty_cycle15" value="50.0" />
+  <parameter name="gui_actual_duty_cycle16" value="50.0" />
+  <parameter name="gui_actual_duty_cycle17" value="50.0" />
+  <parameter name="gui_actual_duty_cycle2" value="50.0" />
+  <parameter name="gui_actual_duty_cycle3" value="50.0" />
+  <parameter name="gui_actual_duty_cycle4" value="50.0" />
+  <parameter name="gui_actual_duty_cycle5" value="50.0" />
+  <parameter name="gui_actual_duty_cycle6" value="50.0" />
+  <parameter name="gui_actual_duty_cycle7" value="50.0" />
+  <parameter name="gui_actual_duty_cycle8" value="50.0" />
+  <parameter name="gui_actual_duty_cycle9" value="50.0" />
+  <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_actual_phase_shift0" value="0.0" />
+  <parameter name="gui_actual_phase_shift1" value="0.0" />
+  <parameter name="gui_actual_phase_shift10" value="0.0" />
+  <parameter name="gui_actual_phase_shift11" value="0.0" />
+  <parameter name="gui_actual_phase_shift12" value="0.0" />
+  <parameter name="gui_actual_phase_shift13" value="0.0" />
+  <parameter name="gui_actual_phase_shift14" value="0.0" />
+  <parameter name="gui_actual_phase_shift15" value="0.0" />
+  <parameter name="gui_actual_phase_shift16" value="0.0" />
+  <parameter name="gui_actual_phase_shift17" value="0.0" />
+  <parameter name="gui_actual_phase_shift2" value="0.0" />
+  <parameter name="gui_actual_phase_shift3" value="0.0" />
+  <parameter name="gui_actual_phase_shift4" value="0.0" />
+  <parameter name="gui_actual_phase_shift5" value="0.0" />
+  <parameter name="gui_actual_phase_shift6" value="0.0" />
+  <parameter name="gui_actual_phase_shift7" value="0.0" />
+  <parameter name="gui_actual_phase_shift8" value="0.0" />
+  <parameter name="gui_actual_phase_shift9" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_clock_name_global0" value="false" />
+  <parameter name="gui_clock_name_global1" value="false" />
+  <parameter name="gui_clock_name_global10" value="false" />
+  <parameter name="gui_clock_name_global11" value="false" />
+  <parameter name="gui_clock_name_global12" value="false" />
+  <parameter name="gui_clock_name_global13" value="false" />
+  <parameter name="gui_clock_name_global14" value="false" />
+  <parameter name="gui_clock_name_global15" value="false" />
+  <parameter name="gui_clock_name_global16" value="false" />
+  <parameter name="gui_clock_name_global17" value="false" />
+  <parameter name="gui_clock_name_global2" value="false" />
+  <parameter name="gui_clock_name_global3" value="false" />
+  <parameter name="gui_clock_name_global4" value="false" />
+  <parameter name="gui_clock_name_global5" value="false" />
+  <parameter name="gui_clock_name_global6" value="false" />
+  <parameter name="gui_clock_name_global7" value="false" />
+  <parameter name="gui_clock_name_global8" value="false" />
+  <parameter name="gui_clock_name_global9" value="false" />
+  <parameter name="gui_clock_name_string0" value="outclk0" />
+  <parameter name="gui_clock_name_string1" value="outclk1" />
+  <parameter name="gui_clock_name_string10" value="outclk10" />
+  <parameter name="gui_clock_name_string11" value="outclk11" />
+  <parameter name="gui_clock_name_string12" value="outclk12" />
+  <parameter name="gui_clock_name_string13" value="outclk13" />
+  <parameter name="gui_clock_name_string14" value="outclk14" />
+  <parameter name="gui_clock_name_string15" value="outclk15" />
+  <parameter name="gui_clock_name_string16" value="outclk16" />
+  <parameter name="gui_clock_name_string17" value="outclk17" />
+  <parameter name="gui_clock_name_string2" value="outclk2" />
+  <parameter name="gui_clock_name_string3" value="outclk3" />
+  <parameter name="gui_clock_name_string4" value="outclk4" />
+  <parameter name="gui_clock_name_string5" value="outclk5" />
+  <parameter name="gui_clock_name_string6" value="outclk6" />
+  <parameter name="gui_clock_name_string7" value="outclk7" />
+  <parameter name="gui_clock_name_string8" value="outclk8" />
+  <parameter name="gui_clock_name_string9" value="outclk9" />
+  <parameter name="gui_device_speed_grade" value="1" />
+  <parameter name="gui_divide_factor_c0" value="6" />
+  <parameter name="gui_divide_factor_c1" value="6" />
+  <parameter name="gui_divide_factor_c10" value="6" />
+  <parameter name="gui_divide_factor_c11" value="6" />
+  <parameter name="gui_divide_factor_c12" value="6" />
+  <parameter name="gui_divide_factor_c13" value="6" />
+  <parameter name="gui_divide_factor_c14" value="6" />
+  <parameter name="gui_divide_factor_c15" value="6" />
+  <parameter name="gui_divide_factor_c16" value="6" />
+  <parameter name="gui_divide_factor_c17" value="6" />
+  <parameter name="gui_divide_factor_c2" value="6" />
+  <parameter name="gui_divide_factor_c3" value="6" />
+  <parameter name="gui_divide_factor_c4" value="6" />
+  <parameter name="gui_divide_factor_c5" value="6" />
+  <parameter name="gui_divide_factor_c6" value="6" />
+  <parameter name="gui_divide_factor_c7" value="6" />
+  <parameter name="gui_divide_factor_c8" value="6" />
+  <parameter name="gui_divide_factor_c9" value="6" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50.0" />
+  <parameter name="gui_duty_cycle1" value="50.0" />
+  <parameter name="gui_duty_cycle10" value="50.0" />
+  <parameter name="gui_duty_cycle11" value="50.0" />
+  <parameter name="gui_duty_cycle12" value="50.0" />
+  <parameter name="gui_duty_cycle13" value="50.0" />
+  <parameter name="gui_duty_cycle14" value="50.0" />
+  <parameter name="gui_duty_cycle15" value="50.0" />
+  <parameter name="gui_duty_cycle16" value="50.0" />
+  <parameter name="gui_duty_cycle17" value="50.0" />
+  <parameter name="gui_duty_cycle2" value="50.0" />
+  <parameter name="gui_duty_cycle3" value="50.0" />
+  <parameter name="gui_duty_cycle4" value="50.0" />
+  <parameter name="gui_duty_cycle5" value="50.0" />
+  <parameter name="gui_duty_cycle6" value="50.0" />
+  <parameter name="gui_duty_cycle7" value="50.0" />
+  <parameter name="gui_duty_cycle8" value="50.0" />
+  <parameter name="gui_duty_cycle9" value="50.0" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_extclkout_ports" value="false" />
+  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_enable_output_counter_cascading" value="false" />
+  <parameter name="gui_extclkout_0_source" value="C0" />
+  <parameter name="gui_extclkout_1_source" value="C0" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_fix_vco_frequency" value="false" />
+  <parameter name="gui_fixed_vco_frequency" value="600.0" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="6" />
+  <parameter name="gui_number_of_clocks" value="1" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_output_clock_frequency0" value="250.0" />
+  <parameter name="gui_output_clock_frequency1" value="100.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0.0" />
+  <parameter name="gui_phase_shift1" value="0.0" />
+  <parameter name="gui_phase_shift10" value="0.0" />
+  <parameter name="gui_phase_shift11" value="0.0" />
+  <parameter name="gui_phase_shift12" value="0.0" />
+  <parameter name="gui_phase_shift13" value="0.0" />
+  <parameter name="gui_phase_shift14" value="0.0" />
+  <parameter name="gui_phase_shift15" value="0.0" />
+  <parameter name="gui_phase_shift16" value="0.0" />
+  <parameter name="gui_phase_shift17" value="0.0" />
+  <parameter name="gui_phase_shift2" value="0.0" />
+  <parameter name="gui_phase_shift3" value="0.0" />
+  <parameter name="gui_phase_shift4" value="0.0" />
+  <parameter name="gui_phase_shift5" value="0.0" />
+  <parameter name="gui_phase_shift6" value="0.0" />
+  <parameter name="gui_phase_shift7" value="0.0" />
+  <parameter name="gui_phase_shift8" value="0.0" />
+  <parameter name="gui_phase_shift9" value="0.0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="false" />
+  <parameter name="gui_pll_bandwidth_preset" value="Low" />
+  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="500.0" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_locked" value="false" />
+  <parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
+  <parameter name="system_info_device_family" value="Arria 10" />
+  <parameter name="system_info_device_speed_grade" value="2" />
+  <parameter name="system_part_trait_speed_grade" value="2" />
+ </module>
+ <module
+   name="xcvr_rx_ref_clk"
+   kind="altera_clock_bridge"
+   version="15.0"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module
+   name="xcvr_tx_lane_pll"
+   kind="altera_xcvr_atx_pll_a10"
+   version="15.0"
+   enabled="1">
+  <parameter name="base_device" value="NIGHTFURY5ES2" />
+  <parameter name="bw_sel" value="medium" />
+  <parameter name="device" value="10AX115S3F45I2SGE2" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="enable_16G_path" value="0" />
+  <parameter name="enable_8G_path" value="1" />
+  <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
+  <parameter name="enable_bonding_clks" value="1" />
+  <parameter name="enable_cascade_out" value="0" />
+  <parameter name="enable_debug_ports_parameters" value="0" />
+  <parameter name="enable_fb_comp_bonding" value="0" />
+  <parameter name="enable_fractional" value="0" />
+  <parameter name="enable_hfreq_clk" value="0" />
+  <parameter name="enable_hip_cal_done_port" value="0" />
+  <parameter name="enable_manual_configuration" value="1" />
+  <parameter name="enable_mcgb" value="0" />
+  <parameter name="enable_mcgb_pcie_clksw" value="0" />
+  <parameter name="enable_pcie_clk" value="0" />
+  <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+  <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+  <parameter name="enable_pll_reconfig" value="0" />
+  <parameter name="generate_add_hdl_instance_example" value="0" />
+  <parameter name="generate_docs" value="1" />
+  <parameter name="mcgb_aux_clkin_cnt" value="0" />
+  <parameter name="mcgb_div" value="1" />
+  <parameter name="message_level" value="error" />
+  <parameter name="pma_width" value="64" />
+  <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+  <parameter name="prot_mode" value="Basic" />
+  <parameter name="rcfg_debug" value="0" />
+  <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
+  <parameter name="rcfg_h_file_enable" value="0" />
+  <parameter name="rcfg_jtag_enable" value="0" />
+  <parameter name="rcfg_mif_file_enable" value="0" />
+  <parameter name="rcfg_multi_enable" value="0" />
+  <parameter name="rcfg_param_vals1" value="" />
+  <parameter name="rcfg_param_vals2" value="" />
+  <parameter name="rcfg_profile_cnt" value="2" />
+  <parameter name="rcfg_profile_select" value="1" />
+  <parameter name="rcfg_sv_file_enable" value="0" />
+  <parameter name="rcfg_txt_file_enable" value="0" />
+  <parameter name="refclk_cnt" value="1" />
+  <parameter name="refclk_index" value="0" />
+  <parameter name="select_manual_config" value="false" />
+  <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
+  <parameter name="set_auto_reference_clock_frequency" value="500.0" />
+  <parameter name="set_capability_reg_enable" value="0" />
+  <parameter name="set_csr_soft_logic_enable" value="0" />
+  <parameter name="set_fref_clock_frequency" value="100.0" />
+  <parameter name="set_hip_cal_en" value="0" />
+  <parameter name="set_k_counter" value="1" />
+  <parameter name="set_l_cascade_counter" value="4" />
+  <parameter name="set_l_counter" value="4" />
+  <parameter name="set_m_counter" value="50" />
+  <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+  <parameter name="set_output_clock_frequency" value="5000.0" />
+  <parameter name="set_ref_clk_div" value="1" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="silicon_rev" value="false" />
+  <parameter name="support_mode" value="user_mode" />
+  <parameter name="test_mode" value="0" />
+ </module>
+ <module name="xcvr_tx_pll" kind="altera_iopll" version="15.0" enabled="1">
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_duty_cycle0" value="50.0" />
+  <parameter name="gui_actual_duty_cycle1" value="50.0" />
+  <parameter name="gui_actual_duty_cycle10" value="50.0" />
+  <parameter name="gui_actual_duty_cycle11" value="50.0" />
+  <parameter name="gui_actual_duty_cycle12" value="50.0" />
+  <parameter name="gui_actual_duty_cycle13" value="50.0" />
+  <parameter name="gui_actual_duty_cycle14" value="50.0" />
+  <parameter name="gui_actual_duty_cycle15" value="50.0" />
+  <parameter name="gui_actual_duty_cycle16" value="50.0" />
+  <parameter name="gui_actual_duty_cycle17" value="50.0" />
+  <parameter name="gui_actual_duty_cycle2" value="50.0" />
+  <parameter name="gui_actual_duty_cycle3" value="50.0" />
+  <parameter name="gui_actual_duty_cycle4" value="50.0" />
+  <parameter name="gui_actual_duty_cycle5" value="50.0" />
+  <parameter name="gui_actual_duty_cycle6" value="50.0" />
+  <parameter name="gui_actual_duty_cycle7" value="50.0" />
+  <parameter name="gui_actual_duty_cycle8" value="50.0" />
+  <parameter name="gui_actual_duty_cycle9" value="50.0" />
+  <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_actual_phase_shift0" value="0.0" />
+  <parameter name="gui_actual_phase_shift1" value="0.0" />
+  <parameter name="gui_actual_phase_shift10" value="0.0" />
+  <parameter name="gui_actual_phase_shift11" value="0.0" />
+  <parameter name="gui_actual_phase_shift12" value="0.0" />
+  <parameter name="gui_actual_phase_shift13" value="0.0" />
+  <parameter name="gui_actual_phase_shift14" value="0.0" />
+  <parameter name="gui_actual_phase_shift15" value="0.0" />
+  <parameter name="gui_actual_phase_shift16" value="0.0" />
+  <parameter name="gui_actual_phase_shift17" value="0.0" />
+  <parameter name="gui_actual_phase_shift2" value="0.0" />
+  <parameter name="gui_actual_phase_shift3" value="0.0" />
+  <parameter name="gui_actual_phase_shift4" value="0.0" />
+  <parameter name="gui_actual_phase_shift5" value="0.0" />
+  <parameter name="gui_actual_phase_shift6" value="0.0" />
+  <parameter name="gui_actual_phase_shift7" value="0.0" />
+  <parameter name="gui_actual_phase_shift8" value="0.0" />
+  <parameter name="gui_actual_phase_shift9" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_clock_name_global0" value="false" />
+  <parameter name="gui_clock_name_global1" value="false" />
+  <parameter name="gui_clock_name_global10" value="false" />
+  <parameter name="gui_clock_name_global11" value="false" />
+  <parameter name="gui_clock_name_global12" value="false" />
+  <parameter name="gui_clock_name_global13" value="false" />
+  <parameter name="gui_clock_name_global14" value="false" />
+  <parameter name="gui_clock_name_global15" value="false" />
+  <parameter name="gui_clock_name_global16" value="false" />
+  <parameter name="gui_clock_name_global17" value="false" />
+  <parameter name="gui_clock_name_global2" value="false" />
+  <parameter name="gui_clock_name_global3" value="false" />
+  <parameter name="gui_clock_name_global4" value="false" />
+  <parameter name="gui_clock_name_global5" value="false" />
+  <parameter name="gui_clock_name_global6" value="false" />
+  <parameter name="gui_clock_name_global7" value="false" />
+  <parameter name="gui_clock_name_global8" value="false" />
+  <parameter name="gui_clock_name_global9" value="false" />
+  <parameter name="gui_clock_name_string0" value="outclk0" />
+  <parameter name="gui_clock_name_string1" value="outclk1" />
+  <parameter name="gui_clock_name_string10" value="outclk10" />
+  <parameter name="gui_clock_name_string11" value="outclk11" />
+  <parameter name="gui_clock_name_string12" value="outclk12" />
+  <parameter name="gui_clock_name_string13" value="outclk13" />
+  <parameter name="gui_clock_name_string14" value="outclk14" />
+  <parameter name="gui_clock_name_string15" value="outclk15" />
+  <parameter name="gui_clock_name_string16" value="outclk16" />
+  <parameter name="gui_clock_name_string17" value="outclk17" />
+  <parameter name="gui_clock_name_string2" value="outclk2" />
+  <parameter name="gui_clock_name_string3" value="outclk3" />
+  <parameter name="gui_clock_name_string4" value="outclk4" />
+  <parameter name="gui_clock_name_string5" value="outclk5" />
+  <parameter name="gui_clock_name_string6" value="outclk6" />
+  <parameter name="gui_clock_name_string7" value="outclk7" />
+  <parameter name="gui_clock_name_string8" value="outclk8" />
+  <parameter name="gui_clock_name_string9" value="outclk9" />
+  <parameter name="gui_device_speed_grade" value="1" />
+  <parameter name="gui_divide_factor_c0" value="6" />
+  <parameter name="gui_divide_factor_c1" value="6" />
+  <parameter name="gui_divide_factor_c10" value="6" />
+  <parameter name="gui_divide_factor_c11" value="6" />
+  <parameter name="gui_divide_factor_c12" value="6" />
+  <parameter name="gui_divide_factor_c13" value="6" />
+  <parameter name="gui_divide_factor_c14" value="6" />
+  <parameter name="gui_divide_factor_c15" value="6" />
+  <parameter name="gui_divide_factor_c16" value="6" />
+  <parameter name="gui_divide_factor_c17" value="6" />
+  <parameter name="gui_divide_factor_c2" value="6" />
+  <parameter name="gui_divide_factor_c3" value="6" />
+  <parameter name="gui_divide_factor_c4" value="6" />
+  <parameter name="gui_divide_factor_c5" value="6" />
+  <parameter name="gui_divide_factor_c6" value="6" />
+  <parameter name="gui_divide_factor_c7" value="6" />
+  <parameter name="gui_divide_factor_c8" value="6" />
+  <parameter name="gui_divide_factor_c9" value="6" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50.0" />
+  <parameter name="gui_duty_cycle1" value="50.0" />
+  <parameter name="gui_duty_cycle10" value="50.0" />
+  <parameter name="gui_duty_cycle11" value="50.0" />
+  <parameter name="gui_duty_cycle12" value="50.0" />
+  <parameter name="gui_duty_cycle13" value="50.0" />
+  <parameter name="gui_duty_cycle14" value="50.0" />
+  <parameter name="gui_duty_cycle15" value="50.0" />
+  <parameter name="gui_duty_cycle16" value="50.0" />
+  <parameter name="gui_duty_cycle17" value="50.0" />
+  <parameter name="gui_duty_cycle2" value="50.0" />
+  <parameter name="gui_duty_cycle3" value="50.0" />
+  <parameter name="gui_duty_cycle4" value="50.0" />
+  <parameter name="gui_duty_cycle5" value="50.0" />
+  <parameter name="gui_duty_cycle6" value="50.0" />
+  <parameter name="gui_duty_cycle7" value="50.0" />
+  <parameter name="gui_duty_cycle8" value="50.0" />
+  <parameter name="gui_duty_cycle9" value="50.0" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_extclkout_ports" value="false" />
+  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_enable_output_counter_cascading" value="false" />
+  <parameter name="gui_extclkout_0_source" value="C0" />
+  <parameter name="gui_extclkout_1_source" value="C0" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_fix_vco_frequency" value="false" />
+  <parameter name="gui_fixed_vco_frequency" value="600.0" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="6" />
+  <parameter name="gui_number_of_clocks" value="1" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_output_clock_frequency0" value="250.0" />
+  <parameter name="gui_output_clock_frequency1" value="100.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0.0" />
+  <parameter name="gui_phase_shift1" value="0.0" />
+  <parameter name="gui_phase_shift10" value="0.0" />
+  <parameter name="gui_phase_shift11" value="0.0" />
+  <parameter name="gui_phase_shift12" value="0.0" />
+  <parameter name="gui_phase_shift13" value="0.0" />
+  <parameter name="gui_phase_shift14" value="0.0" />
+  <parameter name="gui_phase_shift15" value="0.0" />
+  <parameter name="gui_phase_shift16" value="0.0" />
+  <parameter name="gui_phase_shift17" value="0.0" />
+  <parameter name="gui_phase_shift2" value="0.0" />
+  <parameter name="gui_phase_shift3" value="0.0" />
+  <parameter name="gui_phase_shift4" value="0.0" />
+  <parameter name="gui_phase_shift5" value="0.0" />
+  <parameter name="gui_phase_shift6" value="0.0" />
+  <parameter name="gui_phase_shift7" value="0.0" />
+  <parameter name="gui_phase_shift8" value="0.0" />
+  <parameter name="gui_phase_shift9" value="0.0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="false" />
+  <parameter name="gui_pll_bandwidth_preset" value="Low" />
+  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="500.0" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_locked" value="false" />
+  <parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
+  <parameter name="system_info_device_family" value="Arria 10" />
+  <parameter name="system_info_device_speed_grade" value="2" />
+  <parameter name="system_part_trait_speed_grade" value="2" />
+ </module>
+ <module
+   name="xcvr_tx_ref_clk"
+   kind="altera_clock_bridge"
+   version="15.0"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <connection
+   kind="avalon_streaming"
+   version="15.0"
+   start="axi_jesd_xcvr.if_tx_ip_avl"
+   end="xcvr_core.jesd204_tx_link" />
+ <connection
+   kind="avalon_streaming"
+   version="15.0"
+   start="xcvr_core.jesd204_rx_link"
+   end="axi_jesd_xcvr.if_rx_ip_avl" />
+ <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
+ <connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.out_clk"
+   end="xcvr_rst_cntrl.clock" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="mem_clk.out_clk"
+   end="ad9680_adcfifo.if_dma_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="mem_clk.out_clk"
+   end="axi_ad9680_dma.if_s_axis_aclk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.out_clk"
+   end="xcvr_core.jesd204_rx_avs_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.out_clk"
+   end="xcvr_core.jesd204_tx_avs_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="mem_clk.out_clk"
+   end="axi_ad9680_dma.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="mem_clk.out_clk"
+   end="axi_ad9144_dma.m_src_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_tx_ref_clk.out_clk"
+   end="xcvr_tx_lane_pll.pll_refclk0" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_tx_ref_clk.out_clk"
+   end="xcvr_tx_pll.refclk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_rx_ref_clk.out_clk"
+   end="xcvr_rx_pll.refclk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_rx_ref_clk.out_clk"
+   end="xcvr_core.rx_pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.out_clk"
+   end="axi_ad9680_dma.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.out_clk"
+   end="axi_ad9680_core.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.out_clk"
+   end="axi_ad9144_core.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.out_clk"
+   end="axi_jesd_xcvr.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.out_clk"
+   end="axi_ad9144_dma.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_rx_pll.outclk0"
+   end="util_cpack_0.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_rx_pll.outclk0"
+   end="ad9680_adcfifo.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_tx_pll.outclk0"
+   end="util_upack_0.if_dac_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_tx_pll.outclk0"
+   end="axi_ad9144_dma.if_fifo_rd_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_rx_pll.outclk0"
+   end="axi_ad9680_core.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_rx_pll.outclk0"
+   end="axi_jesd_xcvr.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_tx_pll.outclk0"
+   end="axi_ad9144_core.if_tx_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_tx_pll.outclk0"
+   end="axi_jesd_xcvr.if_tx_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_rx_pll.outclk0"
+   end="xcvr_core.rxlink_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="xcvr_tx_pll.outclk0"
+   end="xcvr_core.txlink_clk" />
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_core.alldev_lane_aligned"
+   end="xcvr_core.dev_lane_aligned">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_ad9680_core.fifo_ch_0"
+   end="util_cpack_0.fifo_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="util_cpack_0.fifo_ch_1"
+   end="axi_ad9680_core.fifo_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="util_cpack_0.if_adc_data"
+   end="ad9680_adcfifo.if_adc_wdata">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="util_cpack_0.if_adc_valid"
+   end="ad9680_adcfifo.if_adc_wr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="util_upack_0.if_dac_valid"
+   end="axi_ad9144_dma.if_fifo_rd_en">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="ad9680_adcfifo.if_dma_wdata"
+   end="axi_ad9680_dma.if_s_axis_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="ad9680_adcfifo.if_dma_wr"
+   end="axi_ad9680_dma.if_s_axis_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="ad9680_adcfifo.if_dma_wready"
+   end="axi_ad9680_dma.if_s_axis_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="ad9680_adcfifo.if_dma_xfer_req"
+   end="axi_ad9680_dma.if_s_axis_xfer_req">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_ad9144_dma.if_fifo_rd_dout"
+   end="util_upack_0.if_dac_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_ad9680_core.if_rx_data"
+   end="axi_jesd_xcvr.if_rx_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_jesd_xcvr.if_rx_ip_sof"
+   end="xcvr_core.rx_sof">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_jesd_xcvr.if_rx_ip_sync"
+   end="xcvr_core.rx_dev_sync_n">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_jesd_xcvr.if_rx_ip_sysref"
+   end="xcvr_core.rx_sysref">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_jesd_xcvr.if_rx_ready"
+   end="xcvr_rst_cntrl.rx_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_jesd_xcvr.if_tx_data"
+   end="axi_ad9144_core.if_tx_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_jesd_xcvr.if_tx_ip_sysref"
+   end="xcvr_core.tx_sysref">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_jesd_xcvr.if_tx_ready"
+   end="xcvr_rst_cntrl.tx_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_rst_cntrl.pll_cal_busy"
+   end="xcvr_tx_lane_pll.pll_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_tx_lane_pll.pll_locked"
+   end="xcvr_rst_cntrl.pll_locked">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_tx_lane_pll.pll_powerdown"
+   end="xcvr_rst_cntrl.pll_powerdown">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_rst_cntrl.rx_analogreset"
+   end="xcvr_core.rx_analogreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_core.rx_cal_busy"
+   end="xcvr_rst_cntrl.rx_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_core.rx_digitalreset"
+   end="xcvr_rst_cntrl.rx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_rst_cntrl.rx_is_lockedtodata"
+   end="xcvr_core.rx_islockedtodata">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_core.sync_n"
+   end="axi_jesd_xcvr.if_tx_ip_sync">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_rst_cntrl.tx_analogreset"
+   end="xcvr_core.tx_analogreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_rst_cntrl.tx_cal_busy"
+   end="xcvr_core.tx_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_core.tx_dev_sync_n"
+   end="xcvr_core.mdev_sync_n">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="xcvr_rst_cntrl.tx_digitalreset"
+   end="xcvr_core.tx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="hssi_serial_clock"
+   version="15.0"
+   start="xcvr_tx_lane_pll.tx_serial_clk"
+   end="xcvr_core.tx_serial_clk0_ch0" />
+ <connection
+   kind="hssi_serial_clock"
+   version="15.0"
+   start="xcvr_tx_lane_pll.tx_serial_clk"
+   end="xcvr_core.tx_serial_clk0_ch1" />
+ <connection
+   kind="hssi_serial_clock"
+   version="15.0"
+   start="xcvr_tx_lane_pll.tx_serial_clk"
+   end="xcvr_core.tx_serial_clk0_ch2" />
+ <connection
+   kind="hssi_serial_clock"
+   version="15.0"
+   start="xcvr_tx_lane_pll.tx_serial_clk"
+   end="xcvr_core.tx_serial_clk0_ch3" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="axi_jesd_xcvr.if_rst"
+   end="xcvr_tx_pll.reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="axi_jesd_xcvr.if_rst"
+   end="xcvr_rx_pll.reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="axi_jesd_xcvr.if_rst"
+   end="xcvr_rst_cntrl.reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="axi_jesd_xcvr.if_rx_rstn"
+   end="xcvr_core.rxlink_rst_n" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="axi_jesd_xcvr.if_tx_rstn"
+   end="xcvr_core.txlink_rst_n" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="util_cpack_0.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="mem_rst.out_reset"
+   end="util_cpack_0.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="ad9680_adcfifo.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="mem_rst.out_reset"
+   end="ad9680_adcfifo.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="xcvr_core.jesd204_rx_avs_rst_n" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="xcvr_core.jesd204_tx_avs_rst_n" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="mem_rst.out_reset"
+   end="axi_ad9680_dma.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="mem_rst.out_reset"
+   end="axi_ad9144_dma.m_src_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="xcvr_rst_cntrl.reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="xcvr_tx_pll.reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="xcvr_rx_pll.reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="axi_jesd_xcvr.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="axi_ad9144_core.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="axi_ad9680_core.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="axi_ad9680_dma.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_rst.out_reset"
+   end="axi_ad9144_dma.s_axi_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+</system>

From d94419821237f3238e5a75723f97f673f241ca94 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 09:45:20 -0500
Subject: [PATCH 016/972] daq3/a10gx: board updates

---
 projects/daq3/common/daq3_bd.qsys | 127 +++++++++++++++---------------
 1 file changed, 63 insertions(+), 64 deletions(-)

diff --git a/projects/daq3/common/daq3_bd.qsys b/projects/daq3/common/daq3_bd.qsys
index 836c28c8e..af63e6204 100755
--- a/projects/daq3/common/daq3_bd.qsys
+++ b/projects/daq3/common/daq3_bd.qsys
@@ -25,7 +25,7 @@
          type = "int";
       }
    }
-   element axi_ad9144_core
+   element axi_ad9152_core
    {
       datum _sortIndex
       {
@@ -33,7 +33,7 @@
          type = "int";
       }
    }
-   element axi_ad9144_core.s_axi
+   element axi_ad9152_core.s_axi
    {
       datum baseAddress
       {
@@ -41,7 +41,7 @@
          type = "String";
       }
    }
-   element axi_ad9144_dma
+   element axi_ad9152_dma
    {
       datum _sortIndex
       {
@@ -49,7 +49,7 @@
          type = "int";
       }
    }
-   element axi_ad9144_dma.s_axi
+   element axi_ad9152_dma.s_axi
    {
       datum baseAddress
       {
@@ -110,7 +110,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -118,7 +118,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -126,7 +126,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -134,7 +134,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -142,7 +142,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -150,7 +150,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -158,7 +158,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -166,7 +166,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -174,7 +174,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -182,7 +182,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -190,7 +190,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -198,7 +198,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -206,7 +206,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -214,7 +214,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -222,7 +222,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -230,7 +230,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -238,7 +238,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -246,7 +246,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -254,7 +254,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -262,7 +262,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -270,7 +270,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -278,7 +278,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -286,7 +286,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -294,7 +294,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -302,7 +302,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -310,7 +310,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -318,7 +318,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -326,7 +326,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -334,7 +334,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -342,7 +342,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -350,7 +350,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -358,7 +358,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -366,7 +366,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -374,7 +374,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -382,7 +382,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -390,7 +390,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -398,7 +398,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -406,7 +406,7 @@
          type = "String";
       }
    }
-   element daq2_bd
+   element daq3_bd
    {
       datum _originalDeviceFamily
       {
@@ -740,23 +740,23 @@
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
-   name="axi_ad9144_core_s_axi"
-   internal="axi_ad9144_core.s_axi"
+   name="axi_ad9152_core_s_axi"
+   internal="axi_ad9152_core.s_axi"
    type="axi4lite"
    dir="end" />
  <interface
-   name="axi_ad9144_dma_intr"
-   internal="axi_ad9144_dma.interrupt_sender"
+   name="axi_ad9152_dma_intr"
+   internal="axi_ad9152_dma.interrupt_sender"
    type="interrupt"
    dir="end" />
  <interface
-   name="axi_ad9144_dma_m_axi"
-   internal="axi_ad9144_dma.m_src_axi"
+   name="axi_ad9152_dma_m_axi"
+   internal="axi_ad9152_dma.m_src_axi"
    type="axi4"
    dir="start" />
  <interface
-   name="axi_ad9144_dma_s_axi"
-   internal="axi_ad9144_dma.s_axi"
+   name="axi_ad9152_dma_s_axi"
+   internal="axi_ad9152_dma.s_axi"
    type="axi4lite"
    dir="end" />
  <interface
@@ -835,11 +835,10 @@
   <parameter name="DMA_DATA_WIDTH" value="128" />
   <parameter name="DMA_READY_ENABLE" value="1" />
  </module>
- <module name="axi_ad9144_core" kind="axi_ad9144" version="1.0" enabled="1">
+ <module name="axi_ad9152_core" kind="axi_ad9152" version="1.0" enabled="1">
   <parameter name="ID" value="0" />
-  <parameter name="QUAD_OR_DUAL_N" value="0" />
  </module>
- <module name="axi_ad9144_dma" kind="axi_dmac" version="1.0" enabled="1">
+ <module name="axi_ad9152_dma" kind="axi_dmac" version="1.0" enabled="1">
   <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
   <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
   <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
@@ -1690,7 +1689,7 @@
    kind="clock"
    version="15.0"
    start="mem_clk.out_clk"
-   end="axi_ad9144_dma.m_src_axi_clock" />
+   end="axi_ad9152_dma.m_src_axi_clock" />
  <connection
    kind="clock"
    version="15.0"
@@ -1725,7 +1724,7 @@
    kind="clock"
    version="15.0"
    start="sys_clk.out_clk"
-   end="axi_ad9144_core.s_axi_clock" />
+   end="axi_ad9152_core.s_axi_clock" />
  <connection
    kind="clock"
    version="15.0"
@@ -1735,7 +1734,7 @@
    kind="clock"
    version="15.0"
    start="sys_clk.out_clk"
-   end="axi_ad9144_dma.s_axi_clock" />
+   end="axi_ad9152_dma.s_axi_clock" />
  <connection
    kind="clock"
    version="15.0"
@@ -1755,7 +1754,7 @@
    kind="clock"
    version="15.0"
    start="xcvr_tx_pll.outclk0"
-   end="axi_ad9144_dma.if_fifo_rd_clk" />
+   end="axi_ad9152_dma.if_fifo_rd_clk" />
  <connection
    kind="clock"
    version="15.0"
@@ -1770,7 +1769,7 @@
    kind="clock"
    version="15.0"
    start="xcvr_tx_pll.outclk0"
-   end="axi_ad9144_core.if_tx_clk" />
+   end="axi_ad9152_core.if_tx_clk" />
  <connection
    kind="clock"
    version="15.0"
@@ -1845,7 +1844,7 @@
    kind="conduit"
    version="15.0"
    start="util_upack_0.if_dac_valid"
-   end="axi_ad9144_dma.if_fifo_rd_en">
+   end="axi_ad9152_dma.if_fifo_rd_en">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1899,7 +1898,7 @@
  <connection
    kind="conduit"
    version="15.0"
-   start="axi_ad9144_dma.if_fifo_rd_dout"
+   start="axi_ad9152_dma.if_fifo_rd_dout"
    end="util_upack_0.if_dac_data">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
@@ -1966,7 +1965,7 @@
    kind="conduit"
    version="15.0"
    start="axi_jesd_xcvr.if_tx_data"
-   end="axi_ad9144_core.if_tx_data">
+   end="axi_ad9152_core.if_tx_data">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -2211,7 +2210,7 @@
    kind="reset"
    version="15.0"
    start="mem_rst.out_reset"
-   end="axi_ad9144_dma.m_src_axi_reset" />
+   end="axi_ad9152_dma.m_src_axi_reset" />
  <connection
    kind="reset"
    version="15.0"
@@ -2236,7 +2235,7 @@
    kind="reset"
    version="15.0"
    start="sys_rst.out_reset"
-   end="axi_ad9144_core.s_axi_reset" />
+   end="axi_ad9152_core.s_axi_reset" />
  <connection
    kind="reset"
    version="15.0"
@@ -2251,7 +2250,7 @@
    kind="reset"
    version="15.0"
    start="sys_rst.out_reset"
-   end="axi_ad9144_dma.s_axi_reset" />
+   end="axi_ad9152_dma.s_axi_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />

From ce906989d5d1deb238b92992b3cb26921ca4dd54 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 09:46:31 -0500
Subject: [PATCH 017/972] ad9152: qsys ip

---
 library/axi_ad9152/axi_ad9152_hw.tcl | 124 +++++++++++++++++++++++++++
 1 file changed, 124 insertions(+)
 create mode 100755 library/axi_ad9152/axi_ad9152_hw.tcl

diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl
new file mode 100755
index 000000000..b30788e08
--- /dev/null
+++ b/library/axi_ad9152/axi_ad9152_hw.tcl
@@ -0,0 +1,124 @@
+
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+set_module_property NAME axi_ad9144
+set_module_property DESCRIPTION "AXI AD9144 Interface"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME axi_ad9144
+set_module_property ELABORATION_CALLBACK p_axi_ad9144
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL axi_ad9144
+add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
+add_fileset_file MULT_MACRO.v         VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
+add_fileset_file ad_mul.v             VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
+add_fileset_file ad_dds_sine.v        VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
+add_fileset_file ad_dds_1.v           VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
+add_fileset_file ad_dds.v             VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
+add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
+add_fileset_file up_axi.v             VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
+add_fileset_file up_xfer_cntrl.v      VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
+add_fileset_file up_xfer_status.v     VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
+add_fileset_file up_clock_mon.v       VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
+add_fileset_file up_dac_common.v      VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
+add_fileset_file up_dac_channel.v     VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
+add_fileset_file axi_ad9144_channel.v VERILOG PATH axi_ad9144_channel.v
+add_fileset_file axi_ad9144_core.v    VERILOG PATH axi_ad9144_core.v
+add_fileset_file axi_ad9144_if.v      VERILOG PATH axi_ad9144_if.v
+add_fileset_file axi_ad9144.v         VERILOG PATH axi_ad9144.v TOP_LEVEL_FILE
+add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+
+# parameters
+
+add_parameter ID INTEGER 0
+set_parameter_property ID DEFAULT_VALUE 0
+set_parameter_property ID DISPLAY_NAME ID
+set_parameter_property ID TYPE INTEGER
+set_parameter_property ID UNITS None
+set_parameter_property ID HDL_PARAMETER true
+
+add_parameter QUAD_OR_DUAL_N INTEGER 0
+set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 0
+set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N
+set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
+set_parameter_property QUAD_OR_DUAL_N UNITS None
+set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
+
+# axi4 slave
+
+add_interface s_axi_clock clock end
+add_interface_port s_axi_clock s_axi_aclk clk Input 1
+
+add_interface s_axi_reset reset end
+set_interface_property s_axi_reset associatedClock s_axi_clock
+add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
+
+add_interface s_axi axi4lite end
+set_interface_property s_axi associatedClock s_axi_clock
+set_interface_property s_axi associatedReset s_axi_reset
+add_interface_port s_axi s_axi_awvalid awvalid Input 1
+add_interface_port s_axi s_axi_awaddr awaddr Input 16
+add_interface_port s_axi s_axi_awprot awprot Input 3
+add_interface_port s_axi s_axi_awready awready Output 1
+add_interface_port s_axi s_axi_wvalid wvalid Input 1
+add_interface_port s_axi s_axi_wdata wdata Input 32
+add_interface_port s_axi s_axi_wstrb wstrb Input 4
+add_interface_port s_axi s_axi_wready wready Output 1
+add_interface_port s_axi s_axi_bvalid bvalid Output 1
+add_interface_port s_axi s_axi_bresp bresp Output 2
+add_interface_port s_axi s_axi_bready bready Input 1
+add_interface_port s_axi s_axi_arvalid arvalid Input 1
+add_interface_port s_axi s_axi_araddr araddr Input 16
+add_interface_port s_axi s_axi_arprot arprot Input 3
+add_interface_port s_axi s_axi_arready arready Output 1
+add_interface_port s_axi s_axi_rvalid rvalid Output 1
+add_interface_port s_axi s_axi_rresp rresp Output 2
+add_interface_port s_axi s_axi_rdata rdata Output 32
+add_interface_port s_axi s_axi_rready rready Input 1
+
+# transceiver interface
+
+ad_alt_intf clock   tx_clk        input   1
+ad_alt_intf signal  tx_data       output  128*(QUAD_OR_DUAL_N+1) data
+
+# dma interface
+
+ad_alt_intf clock   dac_clk       output  1
+
+add_interface fifo_ch_0_out conduit end
+add_interface_port fifo_ch_0_out  dac_enable_0  enable   Output  1
+add_interface_port fifo_ch_0_out  dac_valid_0   valid    Output  1
+add_interface_port fifo_ch_0_out  dac_data_0    data     Input   64
+
+add_interface fifo_ch_1_out conduit end
+add_interface_port fifo_ch_1_out  dac_enable_1  enable   Output  1
+add_interface_port fifo_ch_1_out  dac_valid_1   valid    Output  1
+add_interface_port fifo_ch_1_out  dac_data_1    data     Input   64
+
+ad_alt_intf signal  dac_dovf      input   1
+ad_alt_intf signal  dac_dunf      input   1
+
+proc p_axi_ad9144 {} {
+
+  set p_pcore_quad_dual_n [get_parameter_value "QUAD_OR_DUAL_N"]
+
+  if {[get_parameter_value QUAD_OR_DUAL_N] == 1} {
+
+    add_interface fifo_ch_2_out conduit end
+    add_interface_port fifo_ch_2_out  dac_enable_2  enable   Output  1
+    add_interface_port fifo_ch_2_out  dac_valid_2   valid    Output  1
+    add_interface_port fifo_ch_2_out  dac_data_2    data     Input   64
+
+    add_interface fifo_ch_3_out conduit end
+    add_interface_port fifo_ch_3_out  dac_enable_3  enable   Output  1
+    add_interface_port fifo_ch_3_out  dac_valid_3   valid    Output  1
+    add_interface_port fifo_ch_3_out  dac_data_3    data     Input   64
+
+  }
+}

From ff1d98a0c74d6bd21db4c3a46ae0c81d24c4e24a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 16:02:35 -0500
Subject: [PATCH 018/972] ad9144: duplicate include

---
 library/axi_ad9144/axi_ad9144_hw.tcl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl
index b30788e08..2844d5a5d 100755
--- a/library/axi_ad9144/axi_ad9144_hw.tcl
+++ b/library/axi_ad9144/axi_ad9144_hw.tcl
@@ -15,7 +15,6 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9144
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9144
-add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file MULT_MACRO.v         VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
 add_fileset_file ad_mul.v             VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
 add_fileset_file ad_dds_sine.v        VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v

From bc93910ee5271de3630249fc51613412a064f3e9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 16:04:10 -0500
Subject: [PATCH 019/972] ad9152: qsys updates

---
 library/axi_ad9152/axi_ad9152.v      |  4 +++
 library/axi_ad9152/axi_ad9152_hw.tcl | 49 +++++++---------------------
 2 files changed, 15 insertions(+), 38 deletions(-)

diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v
index 2ab69a0ee..cc9c36e45 100644
--- a/library/axi_ad9152/axi_ad9152.v
+++ b/library/axi_ad9152/axi_ad9152.v
@@ -65,6 +65,7 @@ module axi_ad9152 (
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -75,6 +76,7 @@ module axi_ad9152 (
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rdata,
@@ -110,6 +112,7 @@ module axi_ad9152 (
   input             s_axi_aresetn;
   input             s_axi_awvalid;
   input   [ 31:0]   s_axi_awaddr;
+  input   [  2:0]                           s_axi_awprot;
   output            s_axi_awready;
   input             s_axi_wvalid;
   input   [ 31:0]   s_axi_wdata;
@@ -120,6 +123,7 @@ module axi_ad9152 (
   input             s_axi_bready;
   input             s_axi_arvalid;
   input   [ 31:0]   s_axi_araddr;
+  input   [  2:0]                           s_axi_arprot;
   output            s_axi_arready;
   output            s_axi_rvalid;
   output  [ 31:0]   s_axi_rdata;
diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl
index b30788e08..5cb74d354 100755
--- a/library/axi_ad9152/axi_ad9152_hw.tcl
+++ b/library/axi_ad9152/axi_ad9152_hw.tcl
@@ -4,18 +4,16 @@ package require -exact qsys 13.0
 source ../scripts/adi_env.tcl
 source ../scripts/adi_ip_alt.tcl
 
-set_module_property NAME axi_ad9144
-set_module_property DESCRIPTION "AXI AD9144 Interface"
+set_module_property NAME axi_ad9152
+set_module_property DESCRIPTION "AXI AD9152 Interface"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME axi_ad9144
-set_module_property ELABORATION_CALLBACK p_axi_ad9144
+set_module_property DISPLAY_NAME axi_ad9152
 
 # files
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
-set_fileset_property quartus_synth TOP_LEVEL axi_ad9144
-add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
+set_fileset_property quartus_synth TOP_LEVEL axi_ad9152
 add_fileset_file MULT_MACRO.v         VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
 add_fileset_file ad_mul.v             VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
 add_fileset_file ad_dds_sine.v        VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
@@ -28,10 +26,10 @@ add_fileset_file up_xfer_status.v     VERILOG PATH $ad_hdl_dir/library/common/up
 add_fileset_file up_clock_mon.v       VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
 add_fileset_file up_dac_common.v      VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
 add_fileset_file up_dac_channel.v     VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
-add_fileset_file axi_ad9144_channel.v VERILOG PATH axi_ad9144_channel.v
-add_fileset_file axi_ad9144_core.v    VERILOG PATH axi_ad9144_core.v
-add_fileset_file axi_ad9144_if.v      VERILOG PATH axi_ad9144_if.v
-add_fileset_file axi_ad9144.v         VERILOG PATH axi_ad9144.v TOP_LEVEL_FILE
+add_fileset_file axi_ad9152_channel.v VERILOG PATH axi_ad9152_channel.v
+add_fileset_file axi_ad9152_core.v    VERILOG PATH axi_ad9152_core.v
+add_fileset_file axi_ad9152_if.v      VERILOG PATH axi_ad9152_if.v
+add_fileset_file axi_ad9152.v         VERILOG PATH axi_ad9152.v TOP_LEVEL_FILE
 add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
 
 # parameters
@@ -43,13 +41,6 @@ set_parameter_property ID TYPE INTEGER
 set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
-add_parameter QUAD_OR_DUAL_N INTEGER 0
-set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 0
-set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N
-set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
-set_parameter_property QUAD_OR_DUAL_N UNITS None
-set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
-
 # axi4 slave
 
 add_interface s_axi_clock clock end
@@ -85,7 +76,7 @@ add_interface_port s_axi s_axi_rready rready Input 1
 # transceiver interface
 
 ad_alt_intf clock   tx_clk        input   1
-ad_alt_intf signal  tx_data       output  128*(QUAD_OR_DUAL_N+1) data
+ad_alt_intf signal  tx_data       output  128 data
 
 # dma interface
 
@@ -101,24 +92,6 @@ add_interface_port fifo_ch_1_out  dac_enable_1  enable   Output  1
 add_interface_port fifo_ch_1_out  dac_valid_1   valid    Output  1
 add_interface_port fifo_ch_1_out  dac_data_1    data     Input   64
 
-ad_alt_intf signal  dac_dovf      input   1
-ad_alt_intf signal  dac_dunf      input   1
+ad_alt_intf signal  dac_dovf      input   1 ovf
+ad_alt_intf signal  dac_dunf      input   1 unf
 
-proc p_axi_ad9144 {} {
-
-  set p_pcore_quad_dual_n [get_parameter_value "QUAD_OR_DUAL_N"]
-
-  if {[get_parameter_value QUAD_OR_DUAL_N] == 1} {
-
-    add_interface fifo_ch_2_out conduit end
-    add_interface_port fifo_ch_2_out  dac_enable_2  enable   Output  1
-    add_interface_port fifo_ch_2_out  dac_valid_2   valid    Output  1
-    add_interface_port fifo_ch_2_out  dac_data_2    data     Input   64
-
-    add_interface fifo_ch_3_out conduit end
-    add_interface_port fifo_ch_3_out  dac_enable_3  enable   Output  1
-    add_interface_port fifo_ch_3_out  dac_valid_3   valid    Output  1
-    add_interface_port fifo_ch_3_out  dac_data_3    data     Input   64
-
-  }
-}

From f1b6577447dd27324e500789c8baf51ad31fd561 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 16:04:54 -0500
Subject: [PATCH 020/972] a10gx/base: separate gpio in/out

---
 projects/common/a10gx/a10gx_system_assign.tcl | 108 +++++++++---------
 1 file changed, 54 insertions(+), 54 deletions(-)

diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl
index 106b99b48..3e685aefb 100755
--- a/projects/common/a10gx/a10gx_system_assign.tcl
+++ b/projects/common/a10gx/a10gx_system_assign.tcl
@@ -170,61 +170,61 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_ref_clk
 
 # leds
 
-set_location_assignment PIN_L28   -to gpio_bd[0]  ; ## led-g0-d10
-set_location_assignment PIN_K26   -to gpio_bd[1]  ; ## led-g1-d9
-set_location_assignment PIN_K25   -to gpio_bd[2]  ; ## led-g2-d8
-set_location_assignment PIN_L25   -to gpio_bd[3]  ; ## led-g3-d7
-set_location_assignment PIN_J24   -to gpio_bd[4]  ; ## led-g4-d6
-set_location_assignment PIN_A19   -to gpio_bd[5]  ; ## led-g5-d5
-set_location_assignment PIN_C18   -to gpio_bd[6]  ; ## led-g6-d4
-set_location_assignment PIN_D18   -to gpio_bd[7]  ; ## led-g7-d3
-set_location_assignment PIN_L27   -to gpio_bd[8]  ; ## led-r0-d10  
-set_location_assignment PIN_J26   -to gpio_bd[9]  ; ## led-r1-d9   
-set_location_assignment PIN_K24   -to gpio_bd[10] ; ## led-r2-d8
-set_location_assignment PIN_L23   -to gpio_bd[11] ; ## led-r3-d7
-set_location_assignment PIN_B20   -to gpio_bd[12] ; ## led-r4-d6
-set_location_assignment PIN_C19   -to gpio_bd[13] ; ## led-r5-d5
-set_location_assignment PIN_D19   -to gpio_bd[14] ; ## led-r6-d4
-set_location_assignment PIN_M23   -to gpio_bd[15] ; ## led-r7-d3
-set_location_assignment PIN_A24   -to gpio_bd[16] ; ## dipsw0
-set_location_assignment PIN_B23   -to gpio_bd[17] ; ## dipsw1
-set_location_assignment PIN_A23   -to gpio_bd[18] ; ## dipsw2
-set_location_assignment PIN_B22   -to gpio_bd[19] ; ## dipsw3
-set_location_assignment PIN_A22   -to gpio_bd[20] ; ## dipsw4
-set_location_assignment PIN_B21   -to gpio_bd[21] ; ## dipsw5
-set_location_assignment PIN_C21   -to gpio_bd[22] ; ## dipsw6
-set_location_assignment PIN_A20   -to gpio_bd[23] ; ## dipsw7
-set_location_assignment PIN_T12   -to gpio_bd[24] ; ## pb0-s3
-set_location_assignment PIN_U12   -to gpio_bd[25] ; ## pb1-s2
-set_location_assignment PIN_U11   -to gpio_bd[26] ; ## pb2-s1
+set_location_assignment PIN_L28   -to gpio_bd_o[0]  ; ## led-g0-d10
+set_location_assignment PIN_K26   -to gpio_bd_o[1]  ; ## led-g1-d9
+set_location_assignment PIN_K25   -to gpio_bd_o[2]  ; ## led-g2-d8
+set_location_assignment PIN_L25   -to gpio_bd_o[3]  ; ## led-g3-d7
+set_location_assignment PIN_J24   -to gpio_bd_o[4]  ; ## led-g4-d6
+set_location_assignment PIN_A19   -to gpio_bd_o[5]  ; ## led-g5-d5
+set_location_assignment PIN_C18   -to gpio_bd_o[6]  ; ## led-g6-d4
+set_location_assignment PIN_D18   -to gpio_bd_o[7]  ; ## led-g7-d3
+set_location_assignment PIN_L27   -to gpio_bd_o[8]  ; ## led-r0-d10  
+set_location_assignment PIN_J26   -to gpio_bd_o[9]  ; ## led-r1-d9   
+set_location_assignment PIN_K24   -to gpio_bd_o[10] ; ## led-r2-d8
+set_location_assignment PIN_L23   -to gpio_bd_o[11] ; ## led-r3-d7
+set_location_assignment PIN_B20   -to gpio_bd_o[12] ; ## led-r4-d6
+set_location_assignment PIN_C19   -to gpio_bd_o[13] ; ## led-r5-d5
+set_location_assignment PIN_D19   -to gpio_bd_o[14] ; ## led-r6-d4
+set_location_assignment PIN_M23   -to gpio_bd_o[15] ; ## led-r7-d3
+set_location_assignment PIN_A24   -to gpio_bd_i[0]  ; ## dipsw0
+set_location_assignment PIN_B23   -to gpio_bd_i[1]  ; ## dipsw1
+set_location_assignment PIN_A23   -to gpio_bd_i[2]  ; ## dipsw2
+set_location_assignment PIN_B22   -to gpio_bd_i[3]  ; ## dipsw3
+set_location_assignment PIN_A22   -to gpio_bd_i[4]  ; ## dipsw4
+set_location_assignment PIN_B21   -to gpio_bd_i[5]  ; ## dipsw5
+set_location_assignment PIN_C21   -to gpio_bd_i[6]  ; ## dipsw6
+set_location_assignment PIN_A20   -to gpio_bd_i[7]  ; ## dipsw7
+set_location_assignment PIN_T12   -to gpio_bd_i[8]  ; ## pb0-s3
+set_location_assignment PIN_U12   -to gpio_bd_i[9]  ; ## pb1-s2
+set_location_assignment PIN_U11   -to gpio_bd_i[10] ; ## pb2-s1
 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[0] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[1] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[2] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[3] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[4] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[5] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[6] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[7] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[8] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[9] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[10]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[11]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[12]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[13]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[14]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[15]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[16]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[17]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[18]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[19]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[20]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[21]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[22]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[23]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[24]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[25]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[26]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[4] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[5] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[6] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[7] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[8] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[9] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[11]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[12]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[13]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[14]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[15]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10]
 
 # globals
 

From dc84a9ad8210e888338fa123dff1bd18f1f0f79e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Dec 2015 16:06:14 -0500
Subject: [PATCH 021/972] daq3/a10gx: updates

---
 projects/daq3/a10gx/Makefile           | 10 ++--
 projects/daq3/a10gx/system_bd.qsys     | 74 +++++++++++++-------------
 projects/daq3/a10gx/system_project.tcl | 15 +++---
 projects/daq3/a10gx/system_top.v       | 58 +++++++++++---------
 projects/daq3/common/daq3_bd.qsys      | 52 ++++++++++++++++++
 projects/daq3/common/daq3_spi.v        |  7 +--
 6 files changed, 136 insertions(+), 80 deletions(-)

diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index 51c24bfef..8821ea258 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -9,8 +9,8 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += system_bd.qsys
-M_DEPS += ../common/daq2_spi.v
-M_DEPS += ../common/daq2_bd.qsys
+M_DEPS += ../common/daq3_spi.v
+M_DEPS += ../common/daq3_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
@@ -120,7 +120,7 @@ M_FLIST += *.pin
 
 
 .PHONY: all clean clean-all
-all: daq2_a10gx.sof
+all: daq3_a10gx.sof
 
 
 
@@ -131,9 +131,9 @@ clean-all:
 	rm -rf $(M_FLIST)
 
 
-daq2_a10gx.sof: $(M_DEPS)
+daq3_a10gx.sof: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_ALTERA) system_project.tcl  >> daq2_a10gx_quartus.log 2>&1
+	$(M_ALTERA) system_project.tcl  >> daq3_a10gx_quartus.log 2>&1
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/daq3/a10gx/system_bd.qsys b/projects/daq3/a10gx/system_bd.qsys
index 1a8f91dd9..94756fbd1 100755
--- a/projects/daq3/a10gx/system_bd.qsys
+++ b/projects/daq3/a10gx/system_bd.qsys
@@ -38,7 +38,7 @@
          type = "String";
       }
    }
-   element daq2
+   element daq3
    {
       datum _sortIndex
       {
@@ -46,7 +46,7 @@
          type = "int";
       }
    }
-   element daq2.axi_ad9144_core_s_axi
+   element daq3.axi_ad9152_core_s_axi
    {
       datum baseAddress
       {
@@ -54,7 +54,7 @@
          type = "String";
       }
    }
-   element daq2.axi_ad9144_dma_s_axi
+   element daq3.axi_ad9152_dma_s_axi
    {
       datum baseAddress
       {
@@ -62,7 +62,7 @@
          type = "String";
       }
    }
-   element daq2.axi_ad9680_core_s_axi
+   element daq3.axi_ad9680_core_s_axi
    {
       datum baseAddress
       {
@@ -70,7 +70,7 @@
          type = "String";
       }
    }
-   element daq2.axi_ad9680_dma_s_axi
+   element daq3.axi_ad9680_dma_s_axi
    {
       datum baseAddress
       {
@@ -78,7 +78,7 @@
          type = "String";
       }
    }
-   element daq2.axi_jesd_xcvr_s_axi
+   element daq3.axi_jesd_xcvr_s_axi
    {
       datum baseAddress
       {
@@ -332,7 +332,7 @@
  <parameter name="hideFromIPCatalog" value="false" />
  <parameter name="lockedInterfaceDefinition" value="" />
  <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="daq2_a10gx.qpf" />
+ <parameter name="projectName" value="daq3_a10gx.qpf" />
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="0" />
  <parameter name="testBenchDutName" value="" />
@@ -395,28 +395,28 @@
    internal="a10gx_base.sys_spi"
    type="conduit"
    dir="end" />
- <interface name="daq2_rx_data" internal="daq2.rx_data" type="conduit" dir="end" />
+ <interface name="daq3_rx_data" internal="daq3.rx_data" type="conduit" dir="end" />
  <interface
-   name="daq2_rx_ref_clk"
-   internal="daq2.rx_ref_clk"
+   name="daq3_rx_ref_clk"
+   internal="daq3.rx_ref_clk"
    type="clock"
    dir="end" />
- <interface name="daq2_rx_sync" internal="daq2.rx_sync" type="conduit" dir="end" />
+ <interface name="daq3_rx_sync" internal="daq3.rx_sync" type="conduit" dir="end" />
  <interface
-   name="daq2_rx_sysref"
-   internal="daq2.rx_sysref"
+   name="daq3_rx_sysref"
+   internal="daq3.rx_sysref"
    type="conduit"
    dir="end" />
- <interface name="daq2_tx_data" internal="daq2.tx_data" type="conduit" dir="end" />
+ <interface name="daq3_tx_data" internal="daq3.tx_data" type="conduit" dir="end" />
  <interface
-   name="daq2_tx_ref_clk"
-   internal="daq2.tx_ref_clk"
+   name="daq3_tx_ref_clk"
+   internal="daq3.tx_ref_clk"
    type="clock"
    dir="end" />
- <interface name="daq2_tx_sync" internal="daq2.tx_sync" type="conduit" dir="end" />
+ <interface name="daq3_tx_sync" internal="daq3.tx_sync" type="conduit" dir="end" />
  <interface
-   name="daq2_tx_sysref"
-   internal="daq2.tx_sysref"
+   name="daq3_tx_sysref"
+   internal="daq3.tx_sysref"
    type="conduit"
    dir="end" />
  <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
@@ -433,7 +433,7 @@
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq3_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq3_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq3_axi_ad9152_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq3_axi_ad9680_dma.s_axi' start='0x30000' end='0x34000' /><slave name='daq3_axi_ad9152_dma.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
   <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
   <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
@@ -444,10 +444,10 @@
   <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
   <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
  </module>
- <module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+ <module name="daq3" kind="daq3_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
   <parameter
-     name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
+     name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 29" />
   <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
   <parameter
@@ -469,7 +469,7 @@
   <parameter name="AUTO_TX_REF_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_TX_REF_CLK_CLOCK_RATE" value="0" />
   <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
+  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq3" />
  </module>
  <module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
@@ -480,7 +480,7 @@
  <connection
    kind="avalon"
    version="15.0"
-   start="daq2.axi_ad9144_dma_m_axi"
+   start="daq3.axi_ad9152_dma_m_axi"
    end="a10gx_base.sys_mem_s_avl">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
@@ -489,7 +489,7 @@
  <connection
    kind="avalon"
    version="15.0"
-   start="daq2.axi_ad9680_dma_m_axi"
+   start="daq3.axi_ad9680_dma_m_axi"
    end="a10gx_base.sys_mem_s_avl">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
@@ -499,7 +499,7 @@
    kind="avalon"
    version="15.0"
    start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9144_core_s_axi">
+   end="daq3.axi_ad9152_core_s_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00020000" />
   <parameter name="defaultConnection" value="false" />
@@ -508,7 +508,7 @@
    kind="avalon"
    version="15.0"
    start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9144_dma_s_axi">
+   end="daq3.axi_ad9152_dma_s_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00034000" />
   <parameter name="defaultConnection" value="false" />
@@ -517,7 +517,7 @@
    kind="avalon"
    version="15.0"
    start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9680_core_s_axi">
+   end="daq3.axi_ad9680_core_s_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00010000" />
   <parameter name="defaultConnection" value="false" />
@@ -526,7 +526,7 @@
    kind="avalon"
    version="15.0"
    start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9680_dma_s_axi">
+   end="daq3.axi_ad9680_dma_s_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00030000" />
   <parameter name="defaultConnection" value="false" />
@@ -535,7 +535,7 @@
    kind="avalon"
    version="15.0"
    start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_jesd_xcvr_s_axi">
+   end="daq3.axi_jesd_xcvr_s_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
@@ -545,24 +545,24 @@
    version="15.0"
    start="sys_clk.clk"
    end="a10gx_base.sys_clk" />
- <connection kind="clock" version="15.0" start="sys_clk.clk" end="daq2.sys_clk" />
+ <connection kind="clock" version="15.0" start="sys_clk.clk" end="daq3.sys_clk" />
  <connection
    kind="clock"
    version="15.0"
    start="a10gx_base.mem_clk"
-   end="daq2.mem_clk" />
+   end="daq3.mem_clk" />
  <connection
    kind="interrupt"
    version="15.0"
    start="a10gx_base.sys_intr"
-   end="daq2.axi_ad9144_dma_intr">
+   end="daq3.axi_ad9152_dma_intr">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
    version="15.0"
    start="a10gx_base.sys_intr"
-   end="daq2.axi_ad9680_dma_intr">
+   end="daq3.axi_ad9680_dma_intr">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
@@ -574,12 +574,12 @@
    kind="reset"
    version="15.0"
    start="sys_clk.clk_reset"
-   end="daq2.sys_rst" />
+   end="daq3.sys_rst" />
  <connection
    kind="reset"
    version="15.0"
    start="a10gx_base.mem_rst"
-   end="daq2.mem_rst" />
+   end="daq3.mem_rst" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl
index 664f75637..8c5b3e155 100644
--- a/projects/daq3/a10gx/system_project.tcl
+++ b/projects/daq3/a10gx/system_project.tcl
@@ -2,15 +2,14 @@
 load_package flow
 
 source ../../scripts/adi_env.tcl
-project_new daq2_a10gx -overwrite
+project_new daq3_a10gx -overwrite
 
 source "../../common/a10gx/a10gx_system_assign.tcl"
 set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*"
 set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*"
 set_global_assignment -name QSYS_FILE system_bd.qsys
 
-set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
-set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
+set_global_assignment -name VERILOG_FILE ../common/daq3_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
 
 set_global_assignment -name SDC_FILE system_constr.sdc
@@ -70,12 +69,12 @@ set_location_assignment PIN_AU17  -to "trig(n)"             ; ## H14  FMCA_LA07_
 set_location_assignment PIN_AR14  -to adc_fdb               ; ## H17  FMCA_LA11_N
 set_location_assignment PIN_AT14  -to adc_fda               ; ## H16  FMCA_LA11_P
 set_location_assignment PIN_AR16  -to dac_irq               ; ## G15  FMCA_LA12_P
-set_location_assignment PIN_AP17  -to clkd_status[1]        ; ## D18  FMCA_LA13_N
-set_location_assignment PIN_AR17  -to clkd_status[0]        ; ## D17  FMCA_LA13_P
+set_location_assignment PIN_AN19  -to clkd_status[1]        ; ## G13  FMCA_LA08_N
+set_location_assignment PIN_AP18  -to clkd_status[0]        ; ## G12  FMCA_LA08_P
 set_location_assignment PIN_AV14  -to adc_pd                ; ## C10  FMCA_LA06_P
 set_location_assignment PIN_AP16  -to dac_txen              ; ## G16  FMCA_LA12_N
-set_location_assignment PIN_AT15  -to dac_reset             ; ## C15  FMCA_LA10_N
-set_location_assignment PIN_AP18  -to clkd_sync             ; ## G12  FMCA_LA08_P
+set_location_assignment PIN_AR17  -to sysref                ; ## D17  FMCA_LA13_P
+set_location_assignment PIN_AP17  -to "sysref(n)"           ; ## D18  FMCA_LA13_N
 
 set_instance_assignment -name IO_STANDARD LVDS -to trig
 
@@ -86,7 +85,7 @@ set_location_assignment PIN_AR15  -to spi_csn_dac           ; ## C14  FMCA_LA10_
 set_location_assignment PIN_AV13  -to spi_csn_adc           ; ## D15  FMCA_LA09_N
 set_location_assignment PIN_AW11  -to spi_clk               ; ## D12  FMCA_LA05_N
 set_location_assignment PIN_AW13  -to spi_sdio              ; ## D14  FMCA_LA09_P
-set_location_assignment PIN_AN19  -to spi_dir               ; ## G13  FMCA_LA08_N
+set_location_assignment PIN_AW14  -to spi_dir               ; ## C11  FMCA_LA06_N
 
 execute_flow -compile
 
diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v
index 9b16e7693..92a14ccff 100644
--- a/projects/daq3/a10gx/system_top.v
+++ b/projects/daq3/a10gx/system_top.v
@@ -76,7 +76,8 @@ module system_top (
 
   // board gpio
 
-  gpio_bd,
+  gpio_bd_i,
+  gpio_bd_o,
 
   // lane interface
 
@@ -98,8 +99,7 @@ module system_top (
   clkd_status,
   adc_pd,
   dac_txen,
-  dac_reset,
-  clkd_sync,
+  sysref,
 
   // spi
 
@@ -147,7 +147,8 @@ module system_top (
 
   // board gpio
 
-  inout   [ 26:0]   gpio_bd;
+  inout   [ 10:0]   gpio_bd_i;
+  inout   [ 15:0]   gpio_bd_o;
 
   // lane interface
 
@@ -169,8 +170,7 @@ module system_top (
   input   [  1:0]   clkd_status;
   output            adc_pd;
   output            dac_txen;
-  output            dac_reset;
-  output            clkd_sync;
+  output            sysref;
 
   // spi
 
@@ -187,19 +187,29 @@ module system_top (
   wire              eth_mdio_i;
   wire              eth_mdio_o;
   wire              eth_mdio_t;
-  wire    [ 31:0]   gpio_i;
-  wire    [ 31:0]   gpio_o;
+  wire    [ 63:0]   gpio_i;
+  wire    [ 63:0]   gpio_o;
   wire              spi_miso_s;
   wire              spi_mosi_s;
   wire    [  7:0]   spi_csn_s;
 
-  // daq2
+  // daq3
+
+  assign sysref = gpio_o[40];
+  assign adc_pd = gpio_o[38:38];
+  assign dac_txen = gpio_o[37:37];
+
+  assign gpio_i[39:39] = trig;
+  assign gpio_i[36:36] = adc_fdb;
+  assign gpio_i[35:35] = adc_fda;
+  assign gpio_i[34:34] = dac_irq;
+  assign gpio_i[33:32] = clkd_status;
 
   assign spi_csn_adc = spi_csn_s[2];
   assign spi_csn_dac = spi_csn_s[1];
   assign spi_csn_clk = spi_csn_s[0];
 
-  daq2_spi i_daq2_spi (
+  daq3_spi i_daq3_spi (
     .spi_csn (spi_csn_s[2:0]),
     .spi_clk (spi_clk),
     .spi_mosi (spi_mosi_s),
@@ -216,12 +226,10 @@ module system_top (
   assign ddr3_a[14:12] = 3'd0;
 
   assign gpio_i[31:27] = gpio_o[31:27];
+  assign gpio_i[26:16] = gpio_bd_i;
+  assign gpio_i[15: 0] = gpio_o[15: 0];
 
-  ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
-    .dio_t ({11'h7ff, 16'h0}),
-    .dio_i (gpio_o[26:0]),
-    .dio_o (gpio_i[26:0]),
-    .dio_p (gpio_bd));
+  assign gpio_bd_o = gpio_o[15:0];
 
   system_bd i_system_bd (
     .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
@@ -249,22 +257,22 @@ module system_top (
     .a10gx_base_sys_ethernet_reset_reset (eth_reset),
     .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
     .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
-    .a10gx_base_sys_gpio_in_export ({trig, adc_fdb, adc_fda, dac_irq, clkd_status[1], clkd_status[0]}),
-    .a10gx_base_sys_gpio_out_export ({adc_pd, dac_txen, dac_reset, clkd_sync}),
+    .a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
+    .a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
     .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
     .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
     .a10gx_base_sys_spi_MISO (spi_miso_s),
     .a10gx_base_sys_spi_MOSI (spi_mosi_s),
     .a10gx_base_sys_spi_SCLK (spi_clk),
     .a10gx_base_sys_spi_SS_n (spi_csn_s),
-    .daq2_rx_data_rx_serial_data (rx_data),
-    .daq2_rx_ref_clk_clk (rx_ref_clk),
-    .daq2_rx_sync_rx_sync (rx_sync),
-    .daq2_rx_sysref_rx_ext_sysref_in (rx_sysref),
-    .daq2_tx_data_tx_serial_data (tx_data),
-    .daq2_tx_ref_clk_clk (tx_ref_clk),
-    .daq2_tx_sync_tx_sync (tx_sync),
-    .daq2_tx_sysref_tx_ext_sysref_in (tx_sysref),
+    .daq3_rx_data_rx_serial_data (rx_data),
+    .daq3_rx_ref_clk_clk (rx_ref_clk),
+    .daq3_rx_sync_rx_sync (rx_sync),
+    .daq3_rx_sysref_rx_ext_sysref_in (rx_sysref),
+    .daq3_tx_data_tx_serial_data (tx_data),
+    .daq3_tx_ref_clk_clk (tx_ref_clk),
+    .daq3_tx_sync_tx_sync (tx_sync),
+    .daq3_tx_sysref_tx_ext_sysref_in (tx_sysref),
     .sys_clk_clk (sys_clk),
     .sys_reset_reset_n (sys_resetn));
 
diff --git a/projects/daq3/common/daq3_bd.qsys b/projects/daq3/common/daq3_bd.qsys
index af63e6204..8edbb937f 100755
--- a/projects/daq3/common/daq3_bd.qsys
+++ b/projects/daq3/common/daq3_bd.qsys
@@ -414,6 +414,14 @@
          type = "String";
       }
    }
+   element daq3_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
    element mem_clk
    {
       datum _sortIndex
@@ -1807,6 +1815,17 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_ad9152_core.fifo_ch_0_out"
+   end="util_upack_0.fifo_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.0"
@@ -1818,6 +1837,17 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_ad9152_core.fifo_ch_1_out"
+   end="util_upack_0.fifo_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.0"
@@ -1840,6 +1870,28 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="ad9680_adcfifo.if_adc_wovf"
+   end="axi_ad9680_core.if_adc_dovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_ad9152_core.if_dac_dunf"
+   end="axi_ad9152_dma.if_fifo_rd_underflow">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.0"
diff --git a/projects/daq3/common/daq3_spi.v b/projects/daq3/common/daq3_spi.v
index 591a33e1c..d3affbe7c 100644
--- a/projects/daq3/common/daq3_spi.v
+++ b/projects/daq3/common/daq3_spi.v
@@ -100,11 +100,8 @@ module daq3_spi (
 
   // io butter
 
-  IOBUF i_iobuf_sdio (
-    .T (spi_enable_s),
-    .I (spi_mosi),
-    .O (spi_miso),
-    .IO (spi_sdio));
+  assign spi_miso = spi_sdio;
+  assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
 
 endmodule
 

From 650d426301d762d5ae67a862d63449a2765af0f0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Dec 2015 10:14:37 -0500
Subject: [PATCH 022/972] a10gx/base: set gpio to 32

---
 projects/common/a10gx/a10gx_system_bd.qsys | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys
index b3a3a70b5..16efb934f 100644
--- a/projects/common/a10gx/a10gx_system_bd.qsys
+++ b/projects/common/a10gx/a10gx_system_bd.qsys
@@ -620,7 +620,7 @@
  <parameter name="hideFromIPCatalog" value="false" />
  <parameter name="lockedInterfaceDefinition" value="" />
  <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="daq2_a10gx.qpf" />
+ <parameter name="projectName" value="" />
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="0" />
  <parameter name="testBenchDutName" value="" />
@@ -1794,7 +1794,7 @@
   <parameter name="resetValue" value="0" />
   <parameter name="simDoTestBenchWiring" value="false" />
   <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="6" />
+  <parameter name="width" value="32" />
  </module>
  <module
    name="sys_gpio_out"
@@ -1812,7 +1812,7 @@
   <parameter name="resetValue" value="0" />
   <parameter name="simDoTestBenchWiring" value="false" />
   <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="4" />
+  <parameter name="width" value="32" />
  </module>
  <module
    name="sys_id"

From da2e1bdc9affead1e0483b06a79bb1e7ae3029e9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Dec 2015 11:50:26 -0500
Subject: [PATCH 023/972] daq2/a10gx: 32bits generic gpio

---
 projects/daq2/a10gx/system_top.v | 36 ++++++++++++++++++++++----------
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v
index 9b16e7693..3ded5b0ee 100644
--- a/projects/daq2/a10gx/system_top.v
+++ b/projects/daq2/a10gx/system_top.v
@@ -76,7 +76,8 @@ module system_top (
 
   // board gpio
 
-  gpio_bd,
+  gpio_bd_i,
+  gpio_bd_o,
 
   // lane interface
 
@@ -147,7 +148,8 @@ module system_top (
 
   // board gpio
 
-  inout   [ 26:0]   gpio_bd;
+  inout   [ 10:0]   gpio_bd_i;
+  inout   [ 15:0]   gpio_bd_o;
 
   // lane interface
 
@@ -187,8 +189,8 @@ module system_top (
   wire              eth_mdio_i;
   wire              eth_mdio_o;
   wire              eth_mdio_t;
-  wire    [ 31:0]   gpio_i;
-  wire    [ 31:0]   gpio_o;
+  wire    [ 63:0]   gpio_i;
+  wire    [ 63:0]   gpio_o;
   wire              spi_miso_s;
   wire              spi_mosi_s;
   wire    [  7:0]   spi_csn_s;
@@ -207,6 +209,20 @@ module system_top (
     .spi_sdio (spi_sdio),
     .spi_dir (spi_dir));
 
+  // gpio in & out are separate cores
+
+  assign adc_pd = gpio_o[35];
+  assign dac_txen = gpio_o[34];
+  assign dac_reset = gpio_o[33];
+  assign clkd_sync = gpio_o[32];
+
+  assign gpio_i[63:38] = 26'd0;
+  assign gpio_i[37:37] = trig;
+  assign gpio_i[36:36] = adc_fdb;
+  assign gpio_i[35:35] = adc_fda;
+  assign gpio_i[34:34] = dac_irq;
+  assign gpio_i[33:32] = clkd_status;
+
   // board stuff
 
   assign eth_resetn = ~eth_reset;
@@ -216,12 +232,10 @@ module system_top (
   assign ddr3_a[14:12] = 3'd0;
 
   assign gpio_i[31:27] = gpio_o[31:27];
+  assign gpio_i[26:16] = gpio_bd_i;
+  assign gpio_i[15: 0] = gpio_o[15:0];
 
-  ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
-    .dio_t ({11'h7ff, 16'h0}),
-    .dio_i (gpio_o[26:0]),
-    .dio_o (gpio_i[26:0]),
-    .dio_p (gpio_bd));
+  assign gpio_bd_o = gpio_o[15:0];
 
   system_bd i_system_bd (
     .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
@@ -249,8 +263,8 @@ module system_top (
     .a10gx_base_sys_ethernet_reset_reset (eth_reset),
     .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
     .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
-    .a10gx_base_sys_gpio_in_export ({trig, adc_fdb, adc_fda, dac_irq, clkd_status[1], clkd_status[0]}),
-    .a10gx_base_sys_gpio_out_export ({adc_pd, dac_txen, dac_reset, clkd_sync}),
+    .a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
+    .a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
     .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
     .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
     .a10gx_base_sys_spi_MISO (spi_miso_s),

From 4c2d08a9be92c238b6b44f070d390666490576c5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Dec 2015 12:49:00 -0500
Subject: [PATCH 024/972] ad9152: altera syntax error

---
 library/axi_ad9152/axi_ad9152_hw.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl
index 5cb74d354..27c96ffd0 100755
--- a/library/axi_ad9152/axi_ad9152_hw.tcl
+++ b/library/axi_ad9152/axi_ad9152_hw.tcl
@@ -85,12 +85,12 @@ ad_alt_intf clock   dac_clk       output  1
 add_interface fifo_ch_0_out conduit end
 add_interface_port fifo_ch_0_out  dac_enable_0  enable   Output  1
 add_interface_port fifo_ch_0_out  dac_valid_0   valid    Output  1
-add_interface_port fifo_ch_0_out  dac_data_0    data     Input   64
+add_interface_port fifo_ch_0_out  dac_ddata_0   data     Input   64
 
 add_interface fifo_ch_1_out conduit end
 add_interface_port fifo_ch_1_out  dac_enable_1  enable   Output  1
 add_interface_port fifo_ch_1_out  dac_valid_1   valid    Output  1
-add_interface_port fifo_ch_1_out  dac_data_1    data     Input   64
+add_interface_port fifo_ch_1_out  dac_ddata_1   data     Input   64
 
 ad_alt_intf signal  dac_dovf      input   1 ovf
 ad_alt_intf signal  dac_dunf      input   1 unf

From 6a9d1c431af03789d08a3e8d4f17e81bec6fc38c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Dec 2015 12:49:25 -0500
Subject: [PATCH 025/972] daq3/a10gx: updated to a10gx/quartus

---
 projects/daq3/a10gx/system_top.v | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v
index 92a14ccff..8524d6ead 100644
--- a/projects/daq3/a10gx/system_top.v
+++ b/projects/daq3/a10gx/system_top.v
@@ -195,16 +195,6 @@ module system_top (
 
   // daq3
 
-  assign sysref = gpio_o[40];
-  assign adc_pd = gpio_o[38:38];
-  assign dac_txen = gpio_o[37:37];
-
-  assign gpio_i[39:39] = trig;
-  assign gpio_i[36:36] = adc_fdb;
-  assign gpio_i[35:35] = adc_fda;
-  assign gpio_i[34:34] = dac_irq;
-  assign gpio_i[33:32] = clkd_status;
-
   assign spi_csn_adc = spi_csn_s[2];
   assign spi_csn_dac = spi_csn_s[1];
   assign spi_csn_clk = spi_csn_s[0];
@@ -217,6 +207,19 @@ module system_top (
     .spi_sdio (spi_sdio),
     .spi_dir (spi_dir));
 
+  // gpio in & out are separate cores
+
+  assign sysref = gpio_o[36];
+  assign adc_pd = gpio_o[35];
+  assign dac_txen = gpio_o[34];
+
+  assign gpio_i[63:38] = 26'd0;
+  assign gpio_i[37:37] = trig;
+  assign gpio_i[36:36] = adc_fdb;
+  assign gpio_i[35:35] = adc_fda;
+  assign gpio_i[34:34] = dac_irq;
+  assign gpio_i[33:32] = clkd_status;
+
   // board stuff
 
   assign eth_resetn = ~eth_reset;
@@ -227,7 +230,7 @@ module system_top (
 
   assign gpio_i[31:27] = gpio_o[31:27];
   assign gpio_i[26:16] = gpio_bd_i;
-  assign gpio_i[15: 0] = gpio_o[15: 0];
+  assign gpio_i[15: 0] = gpio_o[15:0];
 
   assign gpio_bd_o = gpio_o[15:0];
 

From f4e352339070560053378554c27885eca3015ed7 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 14 Dec 2015 15:34:56 +0200
Subject: [PATCH 026/972] ad7616_sdz: Update IO constraints

---
 .../ad7616_sdz/zc706/parallel_if_cnstr.xdc    | 36 -------------------
 .../ad7616_sdz/zc706/parallel_if_constr.xdc   | 36 +++++++++++++++++++
 projects/ad7616_sdz/zc706/serial_if_cnstr.xdc | 23 ------------
 .../ad7616_sdz/zc706/serial_if_constr.xdc     | 29 +++++++++++++++
 4 files changed, 65 insertions(+), 59 deletions(-)
 delete mode 100644 projects/ad7616_sdz/zc706/parallel_if_cnstr.xdc
 create mode 100644 projects/ad7616_sdz/zc706/parallel_if_constr.xdc
 delete mode 100644 projects/ad7616_sdz/zc706/serial_if_cnstr.xdc
 create mode 100644 projects/ad7616_sdz/zc706/serial_if_constr.xdc

diff --git a/projects/ad7616_sdz/zc706/parallel_if_cnstr.xdc b/projects/ad7616_sdz/zc706/parallel_if_cnstr.xdc
deleted file mode 100644
index e7903fc5d..000000000
--- a/projects/ad7616_sdz/zc706/parallel_if_cnstr.xdc
+++ /dev/null
@@ -1,36 +0,0 @@
-
-# ad7616
-
-set_property -dict {PACKAGE_PIN AC14     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[0] ]        ; ## FMC_LPC_LA10_P
-set_property -dict {PACKAGE_PIN AJ15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[1] ]        ; ## FMC_LPC_LA04_P
-set_property -dict {PACKAGE_PIN AH14     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[2] ]        ; ## FMC_LPC_LA09_P
-set_property -dict {PACKAGE_PIN AG12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[3] ]        ; ## FMC_LPC_LA03_P
-set_property -dict {PACKAGE_PIN AE15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[4] ]        ; ## FMC_LPC_LA05_N
-set_property -dict {PACKAGE_PIN AF12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[5] ]        ; ## FMC_LPC_LA02_N
-set_property -dict {PACKAGE_PIN AC12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[6] ]        ; ## FMC_LPC_LA06_N
-set_property -dict {PACKAGE_PIN AF13     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[7] ]        ; ## FMC_LPC_LA00_CC_N
-set_property -dict {PACKAGE_PIN AE16     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[8] ]        ; ## FMC_LPC_LA05_P
-set_property -dict {PACKAGE_PIN AE12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[9] ]        ; ## FMC_LPC_LA02_P
-set_property -dict {PACKAGE_PIN AE17     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[10]]        ; ## FMC_LPC_LA16_N
-set_property -dict {PACKAGE_PIN AE13     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[11]]        ; ## FMC_LPC_LA00_CC_P
-set_property -dict {PACKAGE_PIN AG15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[12]]        ; ## FMC_LPC_LA01_CC_N
-set_property -dict {PACKAGE_PIN AG16     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[13]]        ; ## FMC_LPC_CLK0_M2C_N
-set_property -dict {PACKAGE_PIN AG17     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[14]]        ; ## FMC_LPC_CLK0_M2C_P
-set_property -dict {PACKAGE_PIN AF15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db[15]]        ; ## FMC_LPC_LA01_CC_P
-
-set_property -dict {PACKAGE_PIN AH12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rd_n]          ; ## FMC_LPC_LA03_N
-set_property -dict {PACKAGE_PIN AH13     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports wr_n]          ; ## FMC_LPC_LA09_N
-
-# control lines
-
-set_property -dict {PACKAGE_PIN AF30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports convst]         ; ## FMC_LPC_LA24_P
-set_property -dict {PACKAGE_PIN AH29    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[0]]       ; ## FMC_LPC_LA21_N
-set_property -dict {PACKAGE_PIN AK30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[1]]       ; ## FMC_LPC_LA26_N
-set_property -dict {PACKAGE_PIN AF29    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[2]]       ; ## FMC_LPC_LA25_P
-set_property -dict {PACKAGE_PIN AH28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports hw_rngsel[0]]   ; ## FMC_LPC_LA21_P
-set_property -dict {PACKAGE_PIN AJ30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports hw_rngsel[1]]   ; ## FMC_LPC_LA26_P
-set_property -dict {PACKAGE_PIN AC13    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports busy]           ; ## FMC_LPC_LA10_N
-set_property -dict {PACKAGE_PIN AJ28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports seq_en]         ; ## FMC_LPC_LA27_P
-set_property -dict {PACKAGE_PIN AK28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports reset_n]        ; ## FMC_LPC_LA22_N
-set_property -dict {PACKAGE_PIN AK15    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports cs_n]           ; ## FMC_LPC_LA04_N
-
diff --git a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
new file mode 100644
index 000000000..af2f8f3f9
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
@@ -0,0 +1,36 @@
+
+# ad7616
+
+set_property -dict {PACKAGE_PIN AC14     IOSTANDARD LVCMOS25} [get_ports db[0] ]         ; ## FMC_LPC_LA10_P
+set_property -dict {PACKAGE_PIN AJ15     IOSTANDARD LVCMOS25} [get_ports db[1] ]         ; ## FMC_LPC_LA04_P
+set_property -dict {PACKAGE_PIN AH14     IOSTANDARD LVCMOS25} [get_ports db[2] ]         ; ## FMC_LPC_LA09_P
+set_property -dict {PACKAGE_PIN AG12     IOSTANDARD LVCMOS25} [get_ports db[3] ]         ; ## FMC_LPC_LA03_P
+set_property -dict {PACKAGE_PIN AE15     IOSTANDARD LVCMOS25} [get_ports db[4] ]         ; ## FMC_LPC_LA05_N
+set_property -dict {PACKAGE_PIN AF12     IOSTANDARD LVCMOS25} [get_ports db[5] ]         ; ## FMC_LPC_LA02_N
+set_property -dict {PACKAGE_PIN AC12     IOSTANDARD LVCMOS25} [get_ports db[6] ]         ; ## FMC_LPC_LA06_N
+set_property -dict {PACKAGE_PIN AF13     IOSTANDARD LVCMOS25} [get_ports db[7] ]         ; ## FMC_LPC_LA00_CC_N
+set_property -dict {PACKAGE_PIN AE16     IOSTANDARD LVCMOS25} [get_ports db[8] ]         ; ## FMC_LPC_LA05_P
+set_property -dict {PACKAGE_PIN AE12     IOSTANDARD LVCMOS25} [get_ports db[9] ]         ; ## FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN AE17     IOSTANDARD LVCMOS25} [get_ports db[10]]         ; ## FMC_LPC_LA16_N
+set_property -dict {PACKAGE_PIN AE13     IOSTANDARD LVCMOS25} [get_ports db[11]]         ; ## FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN AG15     IOSTANDARD LVCMOS25} [get_ports db[12]]         ; ## FMC_LPC_LA01_CC_N
+set_property -dict {PACKAGE_PIN AG16     IOSTANDARD LVCMOS25} [get_ports db[13]]         ; ## FMC_LPC_CLK0_M2C_N
+set_property -dict {PACKAGE_PIN AG17     IOSTANDARD LVCMOS25} [get_ports db[14]]         ; ## FMC_LPC_CLK0_M2C_P
+set_property -dict {PACKAGE_PIN AF15     IOSTANDARD LVCMOS25} [get_ports db[15]]         ; ## FMC_LPC_LA01_CC_P
+
+set_property -dict {PACKAGE_PIN AH12     IOSTANDARD LVCMOS25} [get_ports rd_n]           ; ## FMC_LPC_LA03_N
+set_property -dict {PACKAGE_PIN AH13     IOSTANDARD LVCMOS25} [get_ports wr_n]           ; ## FMC_LPC_LA09_N
+
+# control lines
+
+set_property -dict {PACKAGE_PIN AF30     IOSTANDARD LVCOMS25} [get_ports convst]         ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN AH29     IOSTANDARD LVCOMS25} [get_ports chsel[0]]       ; ## FMC_LPC_LA21_N
+set_property -dict {PACKAGE_PIN AK30     IOSTANDARD LVCOMS25} [get_ports chsel[1]]       ; ## FMC_LPC_LA26_N
+set_property -dict {PACKAGE_PIN AF29     IOSTANDARD LVCOMS25} [get_ports chsel[2]]       ; ## FMC_LPC_LA25_P
+set_property -dict {PACKAGE_PIN AH28     IOSTANDARD LVCOMS25} [get_ports hw_rngsel[0]]   ; ## FMC_LPC_LA21_P
+set_property -dict {PACKAGE_PIN AJ30     IOSTANDARD LVCOMS25} [get_ports hw_rngsel[1]]   ; ## FMC_LPC_LA26_P
+set_property -dict {PACKAGE_PIN AC13     IOSTANDARD LVCOMS25} [get_ports busy]           ; ## FMC_LPC_LA10_N
+set_property -dict {PACKAGE_PIN AJ28     IOSTANDARD LVCOMS25} [get_ports seq_en]         ; ## FMC_LPC_LA27_P
+set_property -dict {PACKAGE_PIN AK28     IOSTANDARD LVCOMS25} [get_ports reset_n]        ; ## FMC_LPC_LA22_N
+set_property -dict {PACKAGE_PIN AK15     IOSTANDARD LVCOMS25} [get_ports cs_n]           ; ## FMC_LPC_LA04_N
+
diff --git a/projects/ad7616_sdz/zc706/serial_if_cnstr.xdc b/projects/ad7616_sdz/zc706/serial_if_cnstr.xdc
deleted file mode 100644
index b977ea93f..000000000
--- a/projects/ad7616_sdz/zc706/serial_if_cnstr.xdc
+++ /dev/null
@@ -1,23 +0,0 @@
-
-# ad7616
-
-# data interface
-
-set_property -dict {PACKAGE_PIN AH12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sclk]          ; ## FMC_LPC_LA03_N
-set_property -dict {PACKAGE_PIN AB12     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sdo]           ; ## FMC_LPC_LA06_P
-set_property -dict {PACKAGE_PIN AE13     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sdi_0]         ; ## FMC_LPC_LA00_CC_P
-set_property -dict {PACKAGE_PIN AG15     IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sdi_1]         ; ## FMC_LPC_LA01_CC_N
-
-# control lines
-
-set_property -dict {PACKAGE_PIN AF30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports convst]         ; ## FMC_LPC_LA24_P
-set_property -dict {PACKAGE_PIN AH29    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[0]]       ; ## FMC_LPC_LA21_N
-set_property -dict {PACKAGE_PIN AK30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[1]]       ; ## FMC_LPC_LA26_N
-set_property -dict {PACKAGE_PIN AF29    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports chsel[2]]       ; ## FMC_LPC_LA25_P
-set_property -dict {PACKAGE_PIN AH28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports hw_rngsel[0]]   ; ## FMC_LPC_LA21_P
-set_property -dict {PACKAGE_PIN AJ30    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports hw_rngsel[1]]   ; ## FMC_LPC_LA26_P
-set_property -dict {PACKAGE_PIN AC13    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports busy]           ; ## FMC_LPC_LA10_N
-set_property -dict {PACKAGE_PIN AJ28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports seq_en]         ; ## FMC_LPC_LA27_P
-set_property -dict {PACKAGE_PIN AK28    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports reset_n]        ; ## FMC_LPC_LA22_N
-set_property -dict {PACKAGE_PIN AK15    IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports cs_n]           ; ## FMC_LPC_LA04_N
-
diff --git a/projects/ad7616_sdz/zc706/serial_if_constr.xdc b/projects/ad7616_sdz/zc706/serial_if_constr.xdc
new file mode 100644
index 000000000..e360f98d3
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/serial_if_constr.xdc
@@ -0,0 +1,29 @@
+
+# ad7616
+
+# data interface
+
+set_property -dict {PACKAGE_PIN AH12      IOSTANDARD LVCMOS25} [get_ports spi_sclk]            ; ## FMC_LPC_LA03_N
+set_property -dict {PACKAGE_PIN AB12      IOSTANDARD LVCMOS25} [get_ports spi_sdo]             ; ## FMC_LPC_LA06_P
+set_property -dict {PACKAGE_PIN AE13      IOSTANDARD LVCMOS25} [get_ports spi_sdi_0]           ; ## FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN AG15      IOSTANDARD LVCMOS25} [get_ports spi_sdi_1]           ; ## FMC_LPC_LA01_CC_N
+set_property -dict {PACKAGE_PIN AK15      IOSTANDARD LVCMOS25} [get_ports spi_cs_n]            ; ## FMC_LPC_LA04_N
+
+# control lines
+
+set_property -dict {PACKAGE_PIN AF30      IOSTANDARD LVCMOS25} [get_ports adc_convst]          ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN AH29      IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]]        ; ## FMC_LPC_LA21_N
+set_property -dict {PACKAGE_PIN AK30      IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]]        ; ## FMC_LPC_LA26_N
+set_property -dict {PACKAGE_PIN AF29      IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]]        ; ## FMC_LPC_LA25_P
+set_property -dict {PACKAGE_PIN AH28      IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]]    ; ## FMC_LPC_LA21_P
+set_property -dict {PACKAGE_PIN AJ30      IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]]    ; ## FMC_LPC_LA26_P
+set_property -dict {PACKAGE_PIN AC13      IOSTANDARD LVCMOS25} [get_ports adc_busy]            ; ## FMC_LPC_LA10_N
+set_property -dict {PACKAGE_PIN AJ28      IOSTANDARD LVCMOS25} [get_ports adc_seq_en]          ; ## FMC_LPC_LA27_P
+set_property -dict {PACKAGE_PIN AK28      IOSTANDARD LVCMOS25} [get_ports adc_reset_n]         ; ## FMC_LPC_LA22_N
+
+set_property -dict {PACKAGE_PIN AG16      IOSTANDARD LVCMOS25} [get_ports adc_os[0]]           ; ## FMC_LPC_CLK0_M2C_N
+set_property -dict {PACKAGE_PIN AG17      IOSTANDARD LVCMOS25} [get_ports adc_os[1]]           ; ## FMC_LPC_CLK0_M2C_P
+set_property -dict {PACKAGE_PIN AF15      IOSTANDARD LVCMOS25} [get_ports adc_os[2]]           ; ## FMC_LPC_LA01_CC_P
+set_property -dict {PACKAGE_PIN AH13      IOSTANDARD LVCMOS25} [get_ports adc_burst]           ; ## FMC_LPC_LA09_N
+set_property -dict {PACKAGE_PIN AF12      IOSTANDARD LVCMOS25} [get_ports adc_crcen]           ; ## FMC_LPC_LA02_N
+

From 29a0f27cd1c0944cb170b4ca933bf1f145eb589b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 14 Dec 2015 15:40:29 +0200
Subject: [PATCH 027/972] ad_edge_detect: Add a flop to output, reset is active
 high

---
 library/common/ad_edge_detect.v | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/library/common/ad_edge_detect.v b/library/common/ad_edge_detect.v
index 3671123c8..6c15454b4 100644
--- a/library/common/ad_edge_detect.v
+++ b/library/common/ad_edge_detect.v
@@ -57,7 +57,7 @@ module ad_edge_detect (
   localparam  ANY_EDGE = 2;
 
   input       clk;
-  input       rstn;
+  input       rst;
 
   input       in;
   output      out;
@@ -65,8 +65,10 @@ module ad_edge_detect (
   reg         ff_m1 = 0;
   reg         ff_m2 = 0;
 
+  reg         out = 0;
+
   always @(posedge clk) begin
-    if (rstn == 1) begin
+    if (rst == 1) begin
       ff_m1 <= 0;
       ff_m2 <= 0;
     end else begin
@@ -75,15 +77,19 @@ module ad_edge_detect (
     end
   end
 
-  generate
-    if (EDGE == POS_EDGE) begin
-      assign out = ff_m1 & ~ff_m2;
-    end else if (EDGE == NEG_EDGE) begin
-      assign out = ~ff_m1 & ff_m2;
+  always @(posedge clk) begin
+    if (rst == 1) begin
+      out <= 1'b0;
     end else begin
-      assign out = ff_m1 ^ ff_m2;
+      if (EDGE == POS_EDGE) begin
+        out <= ff_m1 & ~ff_m2;
+      end else if (EDGE == NEG_EDGE) begin
+        out <= ~ff_m1 & ff_m2;
+      end else begin
+        out <= ff_m1 ^ ff_m2;
+      end
     end
-  endgenerate
+  end
 
 endmodule
 

From 4e57170384273907267ec514634ad9ef9189673d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 14 Dec 2015 15:57:54 +0200
Subject: [PATCH 028/972] spi_engine: Update SPI Engine frame work

+ data width and number of SDI lines are configurable
+ axi_spi_engine module can have two different type of memory map interface (S_AXI or UP)
---
 .../axi_spi_engine/axi_spi_engine.v           | 495 ++++++++++--------
 .../spi_engine_execution.v                    |  54 +-
 .../spi_engine_interconnect.v                 |  15 +-
 .../spi_engine_offload/spi_engine_offload.v   |  13 +-
 4 files changed, 318 insertions(+), 259 deletions(-)

diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
index 793c5fa01..9cff99264 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
@@ -1,68 +1,82 @@
 
 module axi_spi_engine (
-	// Slave AXI interface
-	input s_axi_aclk,
-	input s_axi_aresetn,
+        // Slave AXI interface
 
-	input         s_axi_awvalid,
-	input  [31:0] s_axi_awaddr,
-	output        s_axi_awready,
-	input   [2:0] s_axi_awprot,
-	input         s_axi_wvalid,
-	input  [31:0] s_axi_wdata,
-	input  [ 3:0] s_axi_wstrb,
-	output        s_axi_wready,
-	output        s_axi_bvalid,
-	output [ 1:0] s_axi_bresp,
-	input         s_axi_bready,
-	input         s_axi_arvalid,
-	input  [31:0] s_axi_araddr,
-	output        s_axi_arready,
-	input   [2:0] s_axi_arprot,
-	output        s_axi_rvalid,
-	input         s_axi_rready,
-	output [ 1:0] s_axi_rresp,
-	output [31:0] s_axi_rdata,
+        input         s_axi_aclk,
+        input         s_axi_aresetn,
+        input         s_axi_awvalid,
+        input  [31:0] s_axi_awaddr,
+        output        s_axi_awready,
+        input   [2:0] s_axi_awprot,
+        input         s_axi_wvalid,
+        input  [31:0] s_axi_wdata,
+        input  [ 3:0] s_axi_wstrb,
+        output        s_axi_wready,
+        output        s_axi_bvalid,
+        output [ 1:0] s_axi_bresp,
+        input         s_axi_bready,
+        input         s_axi_arvalid,
+        input  [31:0] s_axi_araddr,
+        output        s_axi_arready,
+        input   [2:0] s_axi_arprot,
+        output        s_axi_rvalid,
+        input         s_axi_rready,
+        output [ 1:0] s_axi_rresp,
+        output [31:0] s_axi_rdata,
 
-	output reg irq,
+        // up interface
 
+        input                           up_clk,
+        input                           up_rstn,
+        input                           up_wreq,
+        input  [(UP_ADDRESS_WIDTH-1):0] up_waddr,
+        input  [31:0]                   up_wdata,
+        output                          up_wack,
+        input                           up_rreq,
+        input  [(UP_ADDRESS_WIDTH-1):0] up_raddr,
+        output [31:0]                   up_rdata,
+        output                          up_rack,
 
-	// SPI signals
-	input spi_clk,
+        output reg irq,
 
-	output spi_resetn,
+        // SPI signals
+        input spi_clk,
 
-	input cmd_ready,
-	output cmd_valid,
-	output [15:0] cmd_data,
+        output spi_resetn,
 
-	input sdo_data_ready,
-	output sdo_data_valid,
-	output [7:0] sdo_data,
+        input cmd_ready,
+        output cmd_valid,
+        output [15:0] cmd_data,
 
-	output sdi_data_ready,
-	input sdi_data_valid,
-	input [(SDI_DATA_WIDTH-1):0] sdi_data,
+        input sdo_data_ready,
+        output sdo_data_valid,
+        output [(DATA_WIDTH-1):0] sdo_data,
 
-	output sync_ready,
-	input sync_valid,
-	input [7:0] sync_data,
+        output sdi_data_ready,
+        input sdi_data_valid,
+        input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
 
-	// Offload ctrl signals
-	output offload0_cmd_wr_en,
-	output [15:0] offload0_cmd_wr_data,
+        output sync_ready,
+        input sync_valid,
+        input [7:0] sync_data,
 
-	output offload0_sdo_wr_en,
-	output [7:0] offload0_sdo_wr_data,
+        // Offload ctrl signals
+        output offload0_cmd_wr_en,
+        output [15:0] offload0_cmd_wr_data,
 
-	output reg offload0_mem_reset,
-	output reg offload0_enable,
-	input offload0_enabled
+        output offload0_sdo_wr_en,
+        output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
+
+        output reg offload0_mem_reset,
+        output reg offload0_enable,
+        input offload0_enabled
 );
 
 parameter CMD_FIFO_ADDRESS_WIDTH = 4;
 parameter SDO_FIFO_ADDRESS_WIDTH = 5;
 parameter SDI_FIFO_ADDRESS_WIDTH = 5;
+parameter MM_IF_TYPE = 0;
+parameter UP_ADDRESS_WIDTH = 14;
 
 parameter ASYNC_SPI_CLK = 0;
 
@@ -72,9 +86,15 @@ parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4;
 parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4;
 
 parameter ID = 'h00;
-parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+parameter DATA_WIDTH = 8;
+parameter NUM_OF_SDI = 1;
 
 localparam PCORE_VERSION = 'h010071;
+localparam S_AXI = 0;
+localparam UP_FIFO = 1;
+
+wire clk;
+wire rstn;
 
 wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
 wire cmd_fifo_almost_empty;
@@ -86,66 +106,103 @@ wire cmd_fifo_in_valid;
 wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;
 wire sdo_fifo_almost_empty;
 
-wire [7:0] sdo_fifo_in_data;
+wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
 wire sdo_fifo_in_ready;
 wire sdo_fifo_in_valid;
 
 wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
 wire sdi_fifo_almost_full;
 
-wire [31:0] sdi_fifo_out_data;
+wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
 wire sdi_fifo_out_ready;
 wire sdi_fifo_out_valid;
 
-reg up_reset = 1'b1;
-wire up_resetn = ~up_reset;
+reg up_sw_reset = 1'b1;
+wire up_sw_resetn = ~up_sw_reset;
 
-reg  [31:0]  up_rdata = 'd0;
-reg          up_wack = 1'b0;
-reg          up_rack = 1'b0;
-wire         up_wreq;
-wire         up_rreq;
-wire [31:0]  up_wdata;
-wire [ 7:0]  up_waddr;
-wire [ 7:0]  up_raddr;
+reg  [31:0]                     up_rdata_ff = 'd0;
+reg                             up_wack_ff = 1'b0;
+reg                             up_rack_ff = 1'b0;
+wire                            up_wreq_s;
+wire                            up_rreq_s;
+wire [31:0]                     up_wdata_s;
+wire [(UP_ADDRESS_WIDTH-1):0]   up_waddr_s;
+wire [(UP_ADDRESS_WIDTH-1):0]   up_raddr_s;
 
 // Scratch register
 reg [31:0] up_scratch = 'h00;
 
 reg  [7:0] sync_id = 'h00;
-reg	   sync_id_pending = 1'b0;
+reg        sync_id_pending = 1'b0;
+
+generate if (MM_IF_TYPE == S_AXI) begin
+
+  // assign clock and reset
+
+  assign clk = s_axi_aclk;
+  assign rstn = s_axi_aresetn;
+
+  // interface wrapper
+
+  up_axi #(
+        .ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
+  ) i_up_axi (
+        .up_rstn(rstn),
+        .up_clk(clk),
+        .up_axi_awvalid(s_axi_awvalid),
+        .up_axi_awaddr(s_axi_awaddr),
+        .up_axi_awready(s_axi_awready),
+        .up_axi_wvalid(s_axi_wvalid),
+        .up_axi_wdata(s_axi_wdata),
+        .up_axi_wstrb(s_axi_wstrb),
+        .up_axi_wready(s_axi_wready),
+        .up_axi_bvalid(s_axi_bvalid),
+        .up_axi_bresp(s_axi_bresp),
+        .up_axi_bready(s_axi_bready),
+        .up_axi_arvalid(s_axi_arvalid),
+        .up_axi_araddr(s_axi_araddr),
+        .up_axi_arready(s_axi_arready),
+        .up_axi_rvalid(s_axi_rvalid),
+        .up_axi_rresp(s_axi_rresp),
+        .up_axi_rdata(s_axi_rdata),
+        .up_axi_rready(s_axi_rready),
+        .up_wreq(up_wreq_s),
+        .up_waddr(up_waddr_s),
+        .up_wdata(up_wdata_s),
+        .up_wack(up_wack_ff),
+        .up_rreq(up_rreq_s),
+        .up_raddr(up_raddr_s),
+        .up_rdata(up_rdata_ff),
+        .up_rack(up_rack_ff)
+  );
+
+  assign up_rdata = 32'b0;
+  assign up_rack = 1'b0;
+  assign up_wack = 1'b0;
+
+end
+endgenerate
+
+generate if (MM_IF_TYPE == UP_FIFO) begin
+
+  // assign clock and reset
+
+  assign clk = up_clk;
+  assign rstn = up_rstn;
+
+  assign up_wreq_s = up_wreq;
+  assign up_waddr_s = up_waddr;
+  assign up_wdata_s = up_wdata;
+  assign up_wack = up_wack_ff;
+  assign up_rreq_s = up_rreq;
+  assign up_raddr_s = up_raddr;
+  assign up_rdata = up_rdata_ff;
+  assign up_rack = up_rack_ff;
+
+end
+endgenerate
+
 
-up_axi #(
-	.ADDRESS_WIDTH (8)
-) i_up_axi (
-	.up_rstn(s_axi_aresetn),
-	.up_clk(s_axi_aclk),
-	.up_axi_awvalid(s_axi_awvalid),
-	.up_axi_awaddr(s_axi_awaddr),
-	.up_axi_awready(s_axi_awready),
-	.up_axi_wvalid(s_axi_wvalid),
-	.up_axi_wdata(s_axi_wdata),
-	.up_axi_wstrb(s_axi_wstrb),
-	.up_axi_wready(s_axi_wready),
-	.up_axi_bvalid(s_axi_bvalid),
-	.up_axi_bresp(s_axi_bresp),
-	.up_axi_bready(s_axi_bready),
-	.up_axi_arvalid(s_axi_arvalid),
-	.up_axi_araddr(s_axi_araddr),
-	.up_axi_arready(s_axi_arready),
-	.up_axi_rvalid(s_axi_rvalid),
-	.up_axi_rresp(s_axi_rresp),
-	.up_axi_rdata(s_axi_rdata),
-	.up_axi_rready(s_axi_rready),
-	.up_wreq(up_wreq),
-	.up_waddr(up_waddr),
-	.up_wdata(up_wdata),
-	.up_wack(up_wack),
-	.up_rreq(up_rreq),
-	.up_raddr(up_raddr),
-	.up_rdata(up_rdata),
-	.up_rack(up_rack)
-);
 
 // IRQ handling
 reg [3:0] up_irq_mask = 'h0;
@@ -153,85 +210,85 @@ wire [3:0] up_irq_source;
 wire [3:0] up_irq_pending;
 
 assign up_irq_source = {
-	sync_id_pending,
-	sdi_fifo_almost_full,
-	sdo_fifo_almost_empty,
-	cmd_fifo_almost_empty
+        sync_id_pending,
+        sdi_fifo_almost_full,
+        sdo_fifo_almost_empty,
+        cmd_fifo_almost_empty
 };
 
 assign up_irq_pending = up_irq_mask & up_irq_source;
 
-always @(posedge s_axi_aclk) begin
-	if (s_axi_aresetn == 1'b0)
-		irq <= 1'b0;
-	else
-		irq <= |up_irq_pending;
+always @(posedge clk) begin
+        if (rstn == 1'b0)
+                irq <= 1'b0;
+        else
+                irq <= |up_irq_pending;
 end
 
-always @(posedge s_axi_aclk) begin
-	if (s_axi_aresetn == 1'b0) begin
-		up_wack <= 1'b0;
-		up_scratch <= 'h00;
-		up_reset <= 1'b1;
-		up_irq_mask <= 'h00;
-		offload0_enable <= 1'b0;
-		offload0_mem_reset <= 1'b0;
-	end else begin
-		up_wack <= up_wreq;
-		offload0_mem_reset <= 1'b0;
-		if (up_wreq) begin
-			case (up_waddr)
-			8'h02: up_scratch <= up_wdata;
-			8'h10: up_reset <= up_wdata;
-			8'h20: up_irq_mask <= up_wdata;
-			8'h40: offload0_enable <= up_wdata[0];
-			8'h42: offload0_mem_reset <= up_wdata[0];
-			endcase
-		end
-	end
+always @(posedge clk) begin
+        if (rstn == 1'b0) begin
+                up_wack_ff <= 1'b0;
+                up_scratch <= 'h00;
+                up_sw_reset <= 1'b1;
+                up_irq_mask <= 'h00;
+                offload0_enable <= 1'b0;
+                offload0_mem_reset <= 1'b0;
+        end else begin
+                up_wack_ff <= up_wreq_s;
+                offload0_mem_reset <= 1'b0;
+                if (up_wreq_s) begin
+                        case (up_waddr_s)
+                        8'h02: up_scratch <= up_wdata_s;
+                        8'h10: up_sw_reset <= up_wdata_s;
+                        8'h20: up_irq_mask <= up_wdata_s;
+                        8'h40: offload0_enable <= up_wdata_s[0];
+                        8'h42: offload0_mem_reset <= up_wdata_s[0];
+                        endcase
+                end
+        end
 end
 
-always @(posedge s_axi_aclk) begin
-	if (s_axi_aresetn == 1'b0) begin
-		up_rack <= 'd0;
-	end else begin
-		up_rack <= up_rreq;
-	end
+always @(posedge clk) begin
+        if (rstn == 1'b0) begin
+                up_rack_ff <= 'd0;
+        end else begin
+                up_rack_ff <= up_rreq_s;
+        end
 end
 
-always @(posedge s_axi_aclk) begin
-	case (up_raddr)
-	8'h00: up_rdata <= PCORE_VERSION;
-	8'h01: up_rdata <= ID;
-	8'h02: up_rdata <= up_scratch;
-	8'h10: up_rdata <= up_reset;
-	8'h20: up_rdata <= up_irq_mask;
-	8'h21: up_rdata <= up_irq_pending;
-	8'h22: up_rdata <= up_irq_source;
-	8'h30: up_rdata <= sync_id;
-	8'h34: up_rdata <= cmd_fifo_room;
-	8'h35: up_rdata <= sdo_fifo_room;
-	8'h36: up_rdata <= sdi_fifo_level;
-	8'h3a: up_rdata <= sdi_fifo_out_data;
-	8'h3c: up_rdata <= sdi_fifo_out_data; /* PEEK register */
-	8'h40: up_rdata <= {offload0_enable};
-	8'h41: up_rdata <= {offload0_enabled};
-	default: up_rdata <= 'h00;
-	endcase
+always @(posedge clk) begin
+        case (up_raddr_s)
+        8'h00: up_rdata_ff <= PCORE_VERSION;
+        8'h01: up_rdata_ff <= ID;
+        8'h02: up_rdata_ff <= up_scratch;
+        8'h10: up_rdata_ff <= up_sw_reset;
+        8'h20: up_rdata_ff <= up_irq_mask;
+        8'h21: up_rdata_ff <= up_irq_pending;
+        8'h22: up_rdata_ff <= up_irq_source;
+        8'h30: up_rdata_ff <= sync_id;
+        8'h34: up_rdata_ff <= cmd_fifo_room;
+        8'h35: up_rdata_ff <= sdo_fifo_room;
+        8'h36: up_rdata_ff <= sdi_fifo_level;
+        8'h3a: up_rdata_ff <= sdi_fifo_out_data;
+        8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
+        8'h40: up_rdata_ff <= {offload0_enable};
+        8'h41: up_rdata_ff <= {offload0_enabled};
+        default: up_rdata_ff <= 'h00;
+        endcase
 end
 
-always @(posedge s_axi_aclk) begin
-	if (up_resetn == 1'b0) begin
-		sync_id <= 'h00;
-		sync_id_pending <= 1'b0;
-	end else begin
-		if (sync_valid == 1'b1) begin
-			sync_id <= sync_data;
-			sync_id_pending <= 1'b1;
-		end else if (up_wreq == 1'b1 && up_waddr == 8'h21 && up_wdata[3] == 1'b1) begin
-			sync_id_pending <= 1'b0;
-		end
-	end
+always @(posedge clk) begin
+        if (up_sw_resetn == 1'b0) begin
+                sync_id <= 'h00;
+                sync_id_pending <= 1'b0;
+        end else begin
+                if (sync_valid == 1'b1) begin
+                        sync_id <= sync_data;
+                        sync_id_pending <= 1'b1;
+                end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
+                        sync_id_pending <= 1'b0;
+                end
+        end
 end
 
 assign sync_ready = 1'b1;
@@ -240,98 +297,98 @@ generate if (ASYNC_SPI_CLK) begin
 
 wire spi_reset;
 ad_rst i_spi_resetn (
-	.preset(up_reset),
-	.clk(spi_clk),
-	.rst(spi_reset)
+        .preset(up_sw_reset),
+        .clk(spi_clk),
+        .rst(spi_reset)
 );
 assign spi_resetn = ~spi_reset;
 end else begin
-assign spi_resetn = ~up_reset;
+assign spi_resetn = ~up_sw_reset;
 end
 endgenerate
 
 /* Evaluates to true if FIFO level/room is 3/4 or above */
 `define axi_spi_engine_check_watermark(x, n) \
-	(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
+        (x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
 
 assign cmd_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h38;
-assign cmd_fifo_in_data = up_wdata[15:0];
+assign cmd_fifo_in_data = up_wdata_s[15:0];
 assign cmd_fifo_almost_empty =
-	`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
+        `axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
 
 util_axis_fifo #(
-	.DATA_WIDTH(16),
-	.ASYNC_CLK(ASYNC_SPI_CLK),
-	.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
-	.S_AXIS_REGISTERED(0)
+        .DATA_WIDTH(16),
+        .ASYNC_CLK(ASYNC_SPI_CLK),
+        .ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
+        .S_AXIS_REGISTERED(0)
 ) i_cmd_fifo (
-	.s_axis_aclk(s_axi_aclk),
-	.s_axis_aresetn(up_resetn),
-	.s_axis_ready(cmd_fifo_in_ready),
-	.s_axis_valid(cmd_fifo_in_valid),
-	.s_axis_data(cmd_fifo_in_data),
-	.s_axis_room(cmd_fifo_room),
+        .s_axis_aclk(clk),
+        .s_axis_aresetn(up_sw_resetn),
+        .s_axis_ready(cmd_fifo_in_ready),
+        .s_axis_valid(cmd_fifo_in_valid),
+        .s_axis_data(cmd_fifo_in_data),
+        .s_axis_room(cmd_fifo_room),
 
-	.m_axis_aclk(spi_clk),
-	.m_axis_aresetn(spi_resetn),
-	.m_axis_ready(cmd_ready),
-	.m_axis_valid(cmd_valid),
-	.m_axis_data(cmd_data)
+        .m_axis_aclk(spi_clk),
+        .m_axis_aresetn(spi_resetn),
+        .m_axis_ready(cmd_ready),
+        .m_axis_valid(cmd_valid),
+        .m_axis_data(cmd_data)
 );
 
-assign sdo_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h39;
-assign sdo_fifo_in_data = up_wdata[7:0];
+assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
+assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
 assign sdo_fifo_almost_empty =
-	`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
+        `axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
 
 util_axis_fifo #(
-	.DATA_WIDTH(8),
-	.ASYNC_CLK(ASYNC_SPI_CLK),
-	.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
-	.S_AXIS_REGISTERED(0)
+        .DATA_WIDTH(DATA_WIDTH),
+        .ASYNC_CLK(ASYNC_SPI_CLK),
+        .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
+        .S_AXIS_REGISTERED(0)
 ) i_sdo_fifo (
-	.s_axis_aclk(s_axi_aclk),
-	.s_axis_aresetn(up_resetn),
-	.s_axis_ready(sdo_fifo_in_ready),
-	.s_axis_valid(sdo_fifo_in_valid),
-	.s_axis_data(sdo_fifo_in_data),
-	.s_axis_room(sdo_fifo_room),
+        .s_axis_aclk(clk),
+        .s_axis_aresetn(up_sw_resetn),
+        .s_axis_ready(sdo_fifo_in_ready),
+        .s_axis_valid(sdo_fifo_in_valid),
+        .s_axis_data(sdo_fifo_in_data),
+        .s_axis_room(sdo_fifo_room),
 
-	.m_axis_aclk(spi_clk),
-	.m_axis_aresetn(spi_resetn),
-	.m_axis_ready(sdo_data_ready),
-	.m_axis_valid(sdo_data_valid),
-	.m_axis_data(sdo_data)
+        .m_axis_aclk(spi_clk),
+        .m_axis_aresetn(spi_resetn),
+        .m_axis_ready(sdo_data_ready),
+        .m_axis_valid(sdo_data_valid),
+        .m_axis_data(sdo_data)
 );
 
-assign sdi_fifo_out_ready = up_rreq == 1'b1 && up_raddr == 8'h3a;
+assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
 assign sdi_fifo_almost_full =
-	`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
+        `axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
 
 util_axis_fifo #(
-	.DATA_WIDTH(SDI_DATA_WIDTH),
-	.ASYNC_CLK(ASYNC_SPI_CLK),
-	.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
-	.S_AXIS_REGISTERED(0)
+        .DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
+        .ASYNC_CLK(ASYNC_SPI_CLK),
+        .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
+        .S_AXIS_REGISTERED(0)
 ) i_sdi_fifo (
-	.s_axis_aclk(spi_clk),
-	.s_axis_aresetn(spi_resetn),
-	.s_axis_ready(sdi_data_ready),
-	.s_axis_valid(sdi_data_valid),
-	.s_axis_data(sdi_data),
+        .s_axis_aclk(spi_clk),
+        .s_axis_aresetn(spi_resetn),
+        .s_axis_ready(sdi_data_ready),
+        .s_axis_valid(sdi_data_valid),
+        .s_axis_data(sdi_data),
 
-	.m_axis_aclk(s_axi_aclk),
-	.m_axis_aresetn(up_resetn),
-	.m_axis_ready(sdi_fifo_out_ready),
-	.m_axis_valid(sdi_fifo_out_valid),
-	.m_axis_data(sdi_fifo_out_data),
-	.m_axis_level(sdi_fifo_level)
+        .m_axis_aclk(clk),
+        .m_axis_aresetn(up_sw_resetn),
+        .m_axis_ready(sdi_fifo_out_ready),
+        .m_axis_valid(sdi_fifo_out_valid),
+        .m_axis_data(sdi_fifo_out_data),
+        .m_axis_level(sdi_fifo_level)
 );
 
-assign offload0_cmd_wr_en = up_wreq == 1'b1 && up_waddr == 8'h44;
-assign offload0_cmd_wr_data = up_wdata[15:0];
+assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
+assign offload0_cmd_wr_data = up_wdata_s[15:0];
 
-assign offload0_sdo_wr_en = up_wreq == 1'b1 && up_waddr == 8'h45;
-assign offload0_sdo_wr_data = up_wdata[7:0];
+assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
+assign offload0_sdo_wr_data = up_wdata_s[7:0];
 
 endmodule
diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
index 223cadabc..b3a092bef 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
@@ -11,11 +11,12 @@ module spi_engine_execution (
 
   input sdo_data_valid,
   output reg sdo_data_ready,
-  input [7:0] sdo_data,
+  input [(DATA_WIDTH-1):0] sdo_data,
+
 
   input sdi_data_ready,
   output reg sdi_data_valid,
-  output [(SDI_DATA_WIDTH-1):0] sdi_data,
+  output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
 
   input sync_ready,
   output reg sync_valid,
@@ -35,10 +36,9 @@ module spi_engine_execution (
 parameter NUM_OF_CS = 1;
 parameter DEFAULT_SPI_CFG = 0;
 parameter DEFAULT_CLK_DIV = 0;
-parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+parameter DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+parameter NUM_OF_SDI = 1;
 
-
-localparam NUM_OF_SDI = SDI_DATA_WIDTH >> 3;
 localparam CMD_TRANSFER = 2'b00;
 localparam CMD_CHIPSELECT = 2'b01;
 localparam CMD_WRITE = 2'b10;
@@ -88,10 +88,10 @@ reg [7:0] clk_div = DEFAULT_CLK_DIV;
 wire sdo_enabled = cmd_d1[8];
 wire sdi_enabled = cmd_d1[9];
 
-reg [8:0] data_shift = 'h0;
-reg [8:0] data_shift_1 = 'h0;
-reg [8:0] data_shift_2 = 'h0;
-reg [8:0] data_shift_3 = 'h0;
+reg [(DATA_WIDTH):0] data_shift = 'h0;
+reg [(DATA_WIDTH):0] data_shift_1 = 'h0;
+reg [(DATA_WIDTH):0] data_shift_2 = 'h0;
+reg [(DATA_WIDTH):0] data_shift_3 = 'h0;
 
 wire [1:0] inst = cmd[13:12];
 wire [1:0] inst_d1 = cmd_d1[13:12];
@@ -287,45 +287,45 @@ end
 always @(posedge clk) begin
         if (transfer_active == 1'b1 || wait_for_io == 1'b1)
         begin
-                sdo_t <= ~sdo_enabled;
+          sdo_t <= ~sdo_enabled;
         end else begin
-                sdo_t <= 1'b1;
+          sdo_t <= 1'b1;
         end
 end
 
 always @(posedge clk) begin
         if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
                 if (first_bit == 1'b1)
-                        data_shift[8:1] <= sdo_data;
+                  data_shift[DATA_WIDTH:1] <= sdo_data;
                 else
-                        data_shift[8:1] <= data_shift[7:0];
-            data_shift_1[8:1] <= data_shift_1[7:0];
-            data_shift_2[8:1] <= data_shift_2[7:0];
-            data_shift_3[8:1] <= data_shift_3[7:0];
+                  data_shift[DATA_WIDTH:1] <= data_shift[(DATA_WIDTH-1):0];
+                  data_shift_1[DATA_WIDTH:1] <= data_shift_1[(DATA_WIDTH-1):0];
+                  data_shift_2[DATA_WIDTH:1] <= data_shift_2[(DATA_WIDTH-1):0];
+                  data_shift_3[DATA_WIDTH:1] <= data_shift_3[(DATA_WIDTH-1):0];
         end
 end
 
-assign sdo = data_shift[8];
-assign sdi_data = (NUM_OF_SDI == 1) ? data_shift[7:0] :
-                  (NUM_OF_SDI == 2) ? {data_shift_1[7:0], data_shift[7:0]} :
-                  (NUM_OF_SDI == 3) ? {data_shift_2[7:0], data_shift_1[7:0], data_shift[7:0]} :
-                  (NUM_OF_SDI == 4) ? {data_shift_3[7:0], data_shift_2[7:0], data_shift_1[7:0], data_shift[7:0]} :
+assign sdo = data_shift[DATA_WIDTH];
+assign sdi_data = (NUM_OF_SDI == 1) ? data_shift[(DATA_WIDTH-1):0] :
+                  (NUM_OF_SDI == 2) ? {data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
+                  (NUM_OF_SDI == 3) ? {data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
+                  (NUM_OF_SDI == 4) ? {data_shift_3[(DATA_WIDTH-1):0], data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
                   data_shift[7:0];
 
 always @(posedge clk) begin
         if (trigger_rx == 1'b1) begin
-                data_shift[0] <= sdi;
-        data_shift_1[0] <= sdi_1;
-        data_shift_2[0] <= sdi_2;
-        data_shift_3[0] <= sdi_3;
+          data_shift[0] <= sdi;
+          data_shift_1[0] <= sdi_1;
+          data_shift_2[0] <= sdi_2;
+          data_shift_3[0] <= sdi_3;
         end
 end
 
 always @(posedge clk) begin
         if (transfer_active == 1'b1) begin
-                sclk <= cpol ^ cpha ^ ntx_rx;
+          sclk <= cpol ^ cpha ^ ntx_rx;
         end else begin
-                sclk <= cpol;
+          sclk <= cpol;
         end
 end
 
diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
index 14cf70aeb..bd8cc6c48 100644
--- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
+++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
@@ -10,11 +10,11 @@ module spi_engine_interconnect (
 
 	output m_sdo_valid,
 	input m_sdo_ready,
-	output [7:0] m_sdo_data,
+	output [(DATA_WIDTH-1):0] m_sdo_data,
 
 	input m_sdi_valid,
 	output m_sdi_ready,
-	input [(SDI_DATA_WIDTH-1):0] m_sdi_data,
+	input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
 
 	input m_sync_valid,
 	output m_sync_ready,
@@ -27,11 +27,11 @@ module spi_engine_interconnect (
 
 	input s0_sdo_valid,
 	output s0_sdo_ready,
-	input [7:0] s0_sdo_data,
+	input [(DATA_WIDTH-1):0] s0_sdo_data,
 
 	output s0_sdi_valid,
 	input s0_sdi_ready,
-	output [(SDI_DATA_WIDTH-1):0] s0_sdi_data,
+	output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
 
 	output s0_sync_valid,
 	input s0_sync_ready,
@@ -44,18 +44,19 @@ module spi_engine_interconnect (
 
 	input s1_sdo_valid,
 	output s1_sdo_ready,
-	input [7:0] s1_sdo_data,
+	input [(DATA_WIDTH-1):0] s1_sdo_data,
 
 	output s1_sdi_valid,
 	input s1_sdi_ready,
-	output [(SDI_DATA_WIDTH-1):0] s1_sdi_data,
+	output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
 
 	output s1_sync_valid,
 	input s1_sync_ready,
 	output [7:0] s1_sync
 );
 
-parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+parameter DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+parameter NUM_OF_SDI = 1;
 
 reg s_active = 1'b0;
 
diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
index 0082bec04..80563a17f 100644
--- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v
+++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
@@ -6,7 +6,7 @@ module spi_engine_offload (
 	input [15:0] ctrl_cmd_wr_data,
 
 	input ctrl_sdo_wr_en,
-	input [7:0] ctrl_sdo_wr_data,
+	input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
 
 	input ctrl_enable,
 	output ctrl_enabled,
@@ -23,11 +23,11 @@ module spi_engine_offload (
 
 	output sdo_data_valid,
 	input sdo_data_ready,
-	output [7:0] sdo_data,
+	output [(DATA_WIDTH-1):0] sdo_data,
 
 	input sdi_data_valid,
 	output sdi_data_ready,
-	input [(SDI_DATA_WIDTH-1):0] sdi_data,
+	input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
 
 	input sync_valid,
 	output sync_ready,
@@ -35,13 +35,14 @@ module spi_engine_offload (
 
 	output offload_sdi_valid,
 	input offload_sdi_ready,
-	output [(SDI_DATA_WIDTH-1):0] offload_sdi_data
+	output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
 );
 
 parameter ASYNC_SPI_CLK = 0;
 parameter CMD_MEM_ADDRESS_WIDTH = 4;
 parameter SDO_MEM_ADDRESS_WIDTH = 4;
-parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+parameter DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+parameter NUM_OF_SDI = 1;
 
 reg spi_active = 1'b0;
 
@@ -51,7 +52,7 @@ reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
 reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
 
 reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
-reg [7:0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
+reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
 
 wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
 wire spi_enable;

From 8ae9de8fbaf464eb7745cb01ddf97bcf333d74b6 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 14 Dec 2015 16:00:56 +0200
Subject: [PATCH 029/972] axi_ad7616: Update core

+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
---
 library/axi_ad7616/axi_ad7616.v         | 233 +++++++++++++-----------
 library/axi_ad7616/axi_ad7616_control.v | 124 +++++++++----
 2 files changed, 218 insertions(+), 139 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 83f4abfde..d09eabc5f 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -63,7 +63,6 @@ module axi_ad7616 (
   hw_rngsel,
   chsel,
   crcen,
-  ser1w_n,
   burst,
   os,
 
@@ -106,10 +105,12 @@ module axi_ad7616 (
 
   // local parameters
 
-  localparam      SDI_DATA_WIDTH = 16;
+  localparam      DATA_WIDTH = 16;
+  localparam      NUM_OF_SDI = 2;
   localparam      SERIAL = 0;
   localparam      PARALLEL = 1;
   localparam      NEG_EDGE = 1;
+  localparam      UP_ADDRESS_WIDTH = 14;
 
   // IO definitions
 
@@ -131,7 +132,6 @@ module axi_ad7616 (
   output  [ 1:0]  hw_rngsel;
   output  [ 2:0]  chsel;
   output          crcen;
-  output          ser1w_n;
   output          burst;
   output  [ 2:0]  os;
 
@@ -163,20 +163,31 @@ module axi_ad7616 (
 
   // internal registers
 
-
   // internal signals
 
-  wire            up_clk;
-  wire            up_rstn;
-  wire            up_rst;
-  wire            up_rreq_s;
-  wire    [13:0]  up_raddr_s;
-  wire    [31:0]  up_rdata_s[0:2];
-  wire            up_rack_s[0:2];
-  wire            up_wack_s[0:2];
-  wire            up_wreq_s;
-  wire    [13:0]  up_waddr_s;
-  wire    [31:0]  up_wdata_s;
+  wire                              up_clk;
+  wire                              up_rstn;
+  wire                              up_rst;
+  wire                              up_rreq_s;
+  wire    [(UP_ADDRESS_WIDTH-1):0]  up_raddr_s;
+  wire                              up_wreq_s;
+  wire    [(UP_ADDRESS_WIDTH-1):0]  up_waddr_s;
+  wire    [31:0]                    up_wdata_s;
+
+  wire                              up_wack_if_s;
+  wire                              up_rack_if_s;
+  wire    [31:0]                    up_rdata_if_s;
+  wire                              up_wack_cntrl_s;
+  wire                              up_rack_cntrl_s;
+  wire    [31:0]                    up_rdata_cntrl_s;
+
+  wire                              trigger_s;
+
+  // internal registers
+
+  reg                               up_wack = 1'b0;
+  reg                               up_rack = 1'b0;
+  reg     [31:0]                    up_rdata = 32'b0;
 
   // defaults
 
@@ -184,6 +195,20 @@ module axi_ad7616 (
   assign up_rstn = s_axi_aresetn;
   assign up_rst = ~s_axi_aresetn;
 
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_wack <= up_wack_if_s | up_wack_cntrl_s;
+      up_rack <= up_rack_if_s | up_rack_cntrl_s;
+      up_rdata <= up_rdata_if_s | up_rdata_cntrl_s;
+    end
+  end
+
   generate if (IF_TYPE == SERIAL) begin
 
     // ground all parallel interface signals
@@ -192,77 +217,70 @@ module axi_ad7616 (
     assign rd_n = 1'b0;
     assign wr_n = 1'b0;
 
-    // all the SPI Framework instances and logic
+    // SPI Framework instances and logic
 
-    wire                          spi_resetn_s;
-    wire                          s0_cmd_ready_s;
-    wire                          s0_cmd_valid_s;
-    wire  [15:0]                  s0_cmd_data_s;
-    wire                          s0_sdo_data_ready_s;
-    wire                          s0_sdo_data_valid_s;
-    wire  [ 7:0]                  s0_sdo_data_s;
-    wire                          s0_sdi_data_ready_s;
-    wire                          s0_sdi_data_valid_s;
-    wire  [(SDI_DATA_WIDTH-1):0]  s0_sdi_data_s;
-    wire                          s0_sync_ready_s;
-    wire                          s0_sync_valid_s;
-    wire  [ 7:0]                  s0_sync_data_s;
-    wire                          s1_cmd_ready_s;
-    wire                          s1_cmd_valid_s;
-    wire  [15:0]                  s1_cmd_data_s;
-    wire                          s1_sdo_data_ready_s;
-    wire                          s1_sdo_data_valid_s;
-    wire  [ 7:0]                  s1_sdo_data_s;
-    wire                          s1_sdi_data_ready_s;
-    wire                          s1_sdi_data_valid_s;
-    wire  [(SDI_DATA_WIDTH-1):0]  s1_sdi_data_s;
-    wire                          s1_sync_ready_s;
-    wire                          s1_sync_valid_s;
-    wire  [ 7:0]                  s1_sync_data_s;
-    wire                          m_cmd_ready_s;
-    wire                          m_cmd_valid_s;
-    wire  [15:0]                  m_cmd_data_s;
-    wire                          m_sdo_data_ready_s;
-    wire                          m_sdo_data_valid_s;
-    wire  [ 7:0]                  m_sdo_data_s;
-    wire                          m_sdi_data_ready_s;
-    wire                          m_sdi_data_valid_s;
-    wire  [(SDI_DATA_WIDTH-1):0]  m_sdi_data_s;
-    wire                          m_sync_ready_s;
-    wire                          m_sync_valid_s;
-    wire  [ 7:0]                  m_sync_data_s;
-    wire                          offload0_cmd_wr_en_s;
-    wire                          offload0_cmd_wr_data_s;
-    wire                          offload0_sdo_wr_en_s;
-    wire                          offload0_sdo_wr_data_s;
-    wire                          offload0_mem_reset_s;
-    wire                          offload0_enable_s;
-    wire                          offload0_enabled_s;
-    wire                          trigger_s;
+    wire                                    spi_resetn_s;
+    wire                                    s0_cmd_ready_s;
+    wire                                    s0_cmd_valid_s;
+    wire  [15:0]                            s0_cmd_data_s;
+    wire                                    s0_sdo_data_ready_s;
+    wire                                    s0_sdo_data_valid_s;
+    wire  [(DATA_WIDTH-1):0]                s0_sdo_data_s;
+    wire                                    s0_sdi_data_ready_s;
+    wire                                    s0_sdi_data_valid_s;
+    wire  [(NUM_OF_SDI * DATA_WIDTH-1):0]   s0_sdi_data_s;
+    wire                                    s0_sync_ready_s;
+    wire                                    s0_sync_valid_s;
+    wire  [ 7:0]                            s0_sync_s;
+    wire                                    s1_cmd_ready_s;
+    wire                                    s1_cmd_valid_s;
+    wire  [15:0]                            s1_cmd_data_s;
+    wire                                    s1_sdo_data_ready_s;
+    wire                                    s1_sdo_data_valid_s;
+    wire  [(DATA_WIDTH-1):0]                s1_sdo_data_s;
+    wire                                    s1_sdi_data_ready_s;
+    wire                                    s1_sdi_data_valid_s;
+    wire  [(NUM_OF_SDI * DATA_WIDTH-1):0]   s1_sdi_data_s;
+    wire                                    s1_sync_ready_s;
+    wire                                    s1_sync_valid_s;
+    wire  [ 7:0]                            s1_sync_s;
+    wire                                    m_cmd_ready_s;
+    wire                                    m_cmd_valid_s;
+    wire  [15:0]                            m_cmd_data_s;
+    wire                                    m_sdo_data_ready_s;
+    wire                                    m_sdo_data_valid_s;
+    wire  [(DATA_WIDTH-1):0]                m_sdo_data_s;
+    wire                                    m_sdi_data_ready_s;
+    wire                                    m_sdi_data_valid_s;
+    wire  [(NUM_OF_SDI * DATA_WIDTH-1):0]   m_sdi_data_s;
+    wire                                    m_sync_ready_s;
+    wire                                    m_sync_valid_s;
+    wire  [ 7:0]                            m_sync_s;
+    wire                                    offload0_cmd_wr_en_s;
+    wire  [15:0]                            offload0_cmd_wr_data_s;
+    wire                                    offload0_sdo_wr_en_s;
+    wire  [(DATA_WIDTH-1):0]                offload0_sdo_wr_data_s;
+    wire                                    offload0_mem_reset_s;
+    wire                                    offload0_enable_s;
+    wire                                    offload0_enabled_s;
 
     axi_spi_engine #(
-      .SDI_DATA_WIDTH (SDI_DATA_WIDTH),
-      .NUM_OFFLOAD(1)
+      .DATA_WIDTH (DATA_WIDTH),
+      .NUM_OF_SDI (NUM_OF_SDI),
+      .NUM_OFFLOAD(1),
+      .MM_IF_TYPE(1),
+      .UP_ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
     ) i_axi_spi_engine(
-      .s_axi_aclk (up_clk),
-      .s_axi_aresetn (up_rstn),
-      .s_axi_awvalid (s_axi_awvalid),
-      .s_axi_awaddr (s_axi_awaddr),
-      .s_axi_awready (s_axi_awready),
-      .s_axi_wvalid (s_axi_wvalid),
-      .s_axi_wdata (s_axi_wdata),
-      .s_axi_wstrb (s_axi_wstrb),
-      .s_axi_wready (s_axi_wready),
-      .s_axi_bvalid (s_axi_bvalid),
-      .s_axi_bresp (s_axi_bresp),
-      .s_axi_bready (s_axi_bready),
-      .s_axi_arvalid (s_axi_arvalid),
-      .s_axi_araddr (s_axi_araddr),
-      .s_axi_arready (s_axi_arready),
-      .s_axi_rvalid (s_axi_rvalid),
-      .s_axi_rready (s_axi_rready),
-      .s_axi_rresp (s_axi_rresp),
-      .s_axi_rdata (s_axi_rdata),
+      .up_clk (up_clk),
+      .up_rstn (up_rstn),
+      .up_wreq (up_wreq_s),
+      .up_waddr (up_waddr_s),
+      .up_wdata (up_wdata_s),
+      .up_wack (up_wack_if_s),
+      .up_rreq (up_rreq_s),
+      .up_raddr (up_raddr_s),
+      .up_rdata (up_rdata_if_s),
+      .up_rack (up_rack_if_s),
       .irq (irq),
       .spi_clk (up_clk),
       .spi_resetn (spi_resetn_s),
@@ -277,7 +295,7 @@ module axi_ad7616 (
       .sdi_data (s0_sdi_data_s),
       .sync_ready (s0_sync_ready_s),
       .sync_valid (s0_sync_valid_s),
-      .sync_data (s0_sync_data_s),
+      .sync_data (s0_sync_s),
       .offload0_cmd_wr_en (offload0_cmd_wr_en_s),
       .offload0_cmd_wr_data (offload0_cmd_wr_data_s),
       .offload0_sdo_wr_en (offload0_sdo_wr_en_s),
@@ -287,7 +305,8 @@ module axi_ad7616 (
       .offload0_enabled(offload0_enabled_s));
 
     spi_engine_offload #(
-      .SDI_DATA_WIDTH (SDI_DATA_WIDTH)
+      .DATA_WIDTH (DATA_WIDTH),
+      .NUM_OF_SDI (NUM_OF_SDI)
     ) i_spi_engine_offload(
       .ctrl_clk (up_clk),
       .ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
@@ -311,24 +330,25 @@ module axi_ad7616 (
       .sdi_data (s1_sdi_data_s),
       .sync_valid (s1_sync_valid_s),
       .sync_ready (s1_sync_ready_s),
-      .sync_data (s1_sync_data_s),
+      .sync_data (s1_sync_s),
       .offload_sdi_valid (m_axis_tvalid),
       .offload_sdi_ready (m_axis_tready),
       .offload_sdi_data (m_axis_tdata));
 
     spi_engine_interconnect #(
-      .SDI_DATA_WIDTH (SDI_DATA_WIDTH)
+      .DATA_WIDTH (DATA_WIDTH),
+      .NUM_OF_SDI (NUM_OF_SDI)
     ) i_spi_engine_interconnect (
       .clk (up_clk),
       .resetn (spi_resetn_s),
       .m_cmd_valid (m_cmd_valid_s),
       .m_cmd_ready (m_cmd_ready_s),
       .m_cmd_data (m_cmd_data_s),
-      .m_sdo_valid (m_sdo_valid_s),
-      .m_sdo_ready (m_sdo_ready_s),
+      .m_sdo_valid (m_sdo_data_valid_s),
+      .m_sdo_ready (m_sdo_data_ready_s),
       .m_sdo_data (m_sdo_data_s),
-      .m_sdi_valid (m_sdi_valid_s),
-      .m_sdi_ready (m_sdi_ready_s),
+      .m_sdi_valid (m_sdi_data_valid_s),
+      .m_sdi_ready (m_sdi_data_ready_s),
       .m_sdi_data (m_sdi_data_s),
       .m_sync_valid (m_sync_valid_s),
       .m_sync_ready (m_sync_ready_s),
@@ -337,29 +357,30 @@ module axi_ad7616 (
       .s0_cmd_ready (s0_cmd_ready_s),
       .s0_cmd_data (s0_cmd_data_s),
       .s0_sdo_valid (s0_sdo_data_valid_s),
-      .s0_sdo_ready (s0_sdi_data_ready_s),
+      .s0_sdo_ready (s0_sdo_data_ready_s),
       .s0_sdo_data (s0_sdo_data_s),
       .s0_sdi_valid (s0_sdi_data_valid_s),
       .s0_sdi_ready (s0_sdi_data_ready_s),
       .s0_sdi_data (s0_sdi_data_s),
       .s0_sync_valid (s0_sync_valid_s),
       .s0_sync_ready (s0_sync_ready_s),
-      .s0_sync (s0_sync_data_s),
+      .s0_sync (s0_sync_s),
       .s1_cmd_valid (s1_cmd_valid_s),
       .s1_cmd_ready (s1_cmd_ready_s),
       .s1_cmd_data (s1_cmd_data_s),
-      .s1_sdo_valid (s1_sdo_valid_s),
-      .s1_sdo_ready (s1_sdo_ready_s),
+      .s1_sdo_valid (s1_sdo_data_valid_s),
+      .s1_sdo_ready (s1_sdo_data_ready_s),
       .s1_sdo_data (s1_sdo_data_s),
-      .s1_sdi_valid (s1_sdi_valid_s),
-      .s1_sdi_ready (s1_sdi_ready_s),
+      .s1_sdi_valid (s1_sdi_data_valid_s),
+      .s1_sdi_ready (s1_sdi_data_ready_s),
       .s1_sdi_data (s1_sdi_data_s),
       .s1_sync_valid (s1_sync_valid_s),
       .s1_sync_ready (s1_sync_ready_s),
       .s1_sync (s1_sync_s));
 
     spi_engine_execution #(
-      .SDI_DATA_WIDTH (SDI_DATA_WIDTH)
+      .DATA_WIDTH (DATA_WIDTH),
+      .NUM_OF_SDI (NUM_OF_SDI)
     ) i_spi_engine_execution (
       .clk (up_clk),
       .resetn (spi_resetn_s),
@@ -375,7 +396,7 @@ module axi_ad7616 (
       .sdi_data (m_sdi_data_s),
       .sync_ready (m_sync_ready_s),
       .sync_valid (m_sync_valid_s),
-      .sync (m_sync_data_s),
+      .sync (m_sync_s),
       .sclk (sclk),
       .sdo (sdo),
       .sdo_t (),
@@ -387,9 +408,10 @@ module axi_ad7616 (
       .three_wire ());
 
   end
+  endgenerate
 
   generate if (IF_TYPE == PARALLEL) begin
-
+    //assign trigger_s = 1'b0;
   end
   endgenerate
 
@@ -404,7 +426,6 @@ module axi_ad7616 (
     .hw_rngsel (hw_rngsel),
     .chsel (chsel),
     .crcen (crcen),
-    .ser1w_n (ser1w_n),
     .burst (burst),
     .os (os),
     .end_of_conv (trigger_s),
@@ -412,16 +433,18 @@ module axi_ad7616 (
     .up_clk (up_clk),
     .up_wreq (up_wreq_s),
     .up_waddr (up_waddr_s),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_cntrl_s),
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
-    .up_rdata (up_rdata_s),
-    .up_rack (up_rack_s));
+    .up_rdata (up_rdata_cntrl_s),
+    .up_rack (up_rack_cntrl_s));
 
   // up bus interface
 
-  up_axi i_up_axi (
+  up_axi #(
+    .ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index 4d396ebb8..36d91de84 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -50,7 +50,6 @@ module axi_ad7616_control (
   hw_rngsel,
   chsel,
   crcen,
-  ser1w_n,
   burst,
   os,
 
@@ -77,9 +76,8 @@ module axi_ad7616_control (
   localparam  PCORE_VERSION = 'h0001001;
   localparam  SW = 0;
   localparam  HW = 1;
-
-  input           clk;
-  input           rst;
+  localparam  POS_EDGE = 0;
+  localparam  NEG_EDGE = 1;
 
   output          reset_n;
   output          cnvst;
@@ -88,7 +86,6 @@ module axi_ad7616_control (
   output  [ 1:0]  hw_rngsel;
   output  [ 2:0]  chsel;
   output          crcen;
-  output          ser1w_n;
   output          burst;
   output  [ 2:0]  os;
 
@@ -109,18 +106,39 @@ module axi_ad7616_control (
 
   // internal signals
 
-  reg     [31:0]  up_scratch = 'b0;
-  reg             up_resetn = 'b0;
-  reg             up_cnvst_en = 'b0;
-  reg             up_ser1w = 'b0;
-  reg     [ 7:0]  up_cnvst_high = 'b0;
-  reg     [31:0]  up_conv_rate = 'b0;
+  reg     [31:0]  up_scratch = 32'b0;
+  reg             up_resetn = 1'b0;
+  reg             up_cnvst_en = 1'b0;
+  reg             up_wack = 1'b0;
+  reg             up_rack = 1'b0;
+  reg     [31:0]  up_rdata = 32'b0;
+  reg     [31:0]  up_conv_rate = 32'b0;
+
   reg     [31:0]  cnvst_counter = 32'b0;
-  reg     [ 7:0]  pulse_counter = 8'b0;
+  reg     [ 3:0]  pulse_counter = 8'b0;
   reg             cnvst_buf = 1'b0;
+  reg             cnvst_pulse = 1'b0;
+  reg     [ 2:0]  chsel_ff = 3'b0;
+
+  reg     [ 1:0]  up_hw_rngsel = 2'b0;
+  reg     [ 2:0]  up_chsel = 3'b0;
+  reg             up_crcen = 1'b0;
+  reg             up_burst = 1'b0;
+  reg     [ 2:0]  up_os = 3'b0;
+  reg             up_seq_en = 1'b0;
+
+
+  wire            up_rst;
+  wire            up_rreq_s;
+  wire            up_wreq_s;
+  wire            end_of_conv_s;
 
   // decode block select
 
+  assign up_wreq_s = (up_waddr[13:8] == 6'h01) ? up_wreq : 1'b0;
+  assign up_rreq_s = (up_raddr[13:8] == 6'h01) ? up_rreq : 1'b0;
+
+  assign end_of_conv = end_of_conv_s;
 
   // processor write interface
 
@@ -130,9 +148,13 @@ module axi_ad7616_control (
       up_scratch <= 32'b0;
       up_resetn <= 1'b0;
       up_cnvst_en <= 1'b0;
-      up_ser1w <= 1'b0;
-      up_cnvst_high <= 8'b0;
       up_conv_rate <= 32'b0;
+      up_hw_rngsel <= 2'b0;
+      up_chsel <= 3'b0;
+      up_crcen <= 1'b0;
+      up_burst <= 1'b0;
+      up_os <= 3'b0;
+      up_seq_en <= 1'b0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@@ -141,13 +163,21 @@ module axi_ad7616_control (
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
         up_resetn <= up_wdata[0];
         up_cnvst_en <= up_wdata[1];
-        up_ser1w <= up_wdata[2];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
-        up_cnvst_high <= up_wdata[7:0];
+        up_conv_rate <= up_wdata;
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
-        up_conv_rate <= up_wdata;
+        up_hw_rngsel <= up_wdata[1:0];
+        up_os <= up_wdata[4:2];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
+        up_seq_en <= up_wdata[0];
+        up_burst <= up_wdata[1];
+        up_chsel <= up_wdata[4:2];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
+        up_crcen <= up_wdata[0];
       end
     end
   end
@@ -165,9 +195,11 @@ module axi_ad7616_control (
             8'h00 : up_rdata = PCORE_VERSION;
             8'h01 : up_rdata = ID;
             8'h02 : up_rdata = up_scratch;
-            8'h10 : up_rdata = {28'b0, up_ser1w, up_cnvst_en, up_resetn};
-            8'h11 : up_rdata = {24'b0, up_cnvst_high};
-            8'h12 : up_rdata = up_conv_rate;
+            8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
+            8'h11 : up_rdata = up_conv_rate;
+            8'h12 : up_rdata = {27'b0, up_os, up_hw_rngsel};
+            8'h13 : up_rdata = {27'b0, up_chsel, up_burst, up_seq_en};
+            8'h14 : up_rdata = {30'b0, up_crcen};
         endcase
       end
     end
@@ -175,52 +207,54 @@ module axi_ad7616_control (
 
   // instantiations
 
+  assign up_rst = ~up_rstn;
+
   ad_edge_detect #(
     .EDGE(NEG_EDGE)
   ) i_ad_edge_detect (
     .clk (up_clk),
-    .rstn (up_rstn),
+    .rst (up_rst),
     .in (busy),
-    .out (end_of_conv)
+    .out (end_of_conv_s)
   );
 
   // convertion start generator
-  // NOTE: The minimum convertion cycle is 1 us and the
-  //       minimum CNVST high pulse width is 20 ns.
-  //       See the AD7616 datasheet for more information.
+  // NOTE: + The minimum convertion cycle is 1 us
+  //       + The rate of the cnvst must be defined in a way,
+  //          to not lose any data. cnvst_rate >= t_conversion + t_aquisition
+  //  See the AD7616 datasheet for more information.
 
-  always @(posedge clk) begin
-    if(up_resetn == 0) begin
+  always @(posedge up_clk) begin
+    if(up_resetn == 1'b0) begin
       cnvst_counter <= 32'b0;
     end else begin
       cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
     end
   end
 
-  always @(cnvst_counter) begin
+  always @(cnvst_counter, up_conv_rate) begin
     cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
   end
 
-  always @(posedge clk) begin
+  always @(posedge up_clk) begin
     if(up_resetn == 1'b0) begin
-      pulse_counter <= 8'b0;
+      pulse_counter <= 3'b0;
       cnvst_buf <= 1'b0;
     end else begin
-      pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 8'b0;
+      pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0;
       if(cnvst_pulse == 1'b1) begin
         cnvst_buf <= 1'b1;
-      end else if (pulse_counter == up_cnvst_high) begin
+      end else if (pulse_counter[2] == 1'b1) begin
         cnvst_buf <= 1'b0;
       end
     end
   end
 
-  assign cnvst <= (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
+  assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
 
   // output logic
 
   assign reset_n = up_resetn;       // device's reset
-  assign ser1w_n = ~up_ser1w;       // serial output operates over SDOA and SDOB OR just SDOA
 
   generate if (OP_MODE == SW) begin
 
@@ -236,5 +270,27 @@ module axi_ad7616_control (
   end
   endgenerate
 
+  generate if (OP_MODE == HW) begin
+
+    assign hw_rngsel = up_hw_rngsel;
+    assign crcen = up_crcen;
+    assign burst = up_burst;
+    assign os = up_os;
+    assign seq_en = up_seq_en;
+    assign chsel = chsel_ff;
+
+    // CHSEL is updated after BUSY deasserts
+
+    always @(posedge up_clk) begin
+      if (up_rstn == 1'b0) begin
+        chsel_ff <= 3'b0;
+      end else begin
+        chsel_ff <= (end_of_conv_s == 1'b1) ? up_chsel : chsel_ff;
+      end
+    end
+
+  end
+  endgenerate
+
 endmodule
 

From ee4d5af12e93ce0150080a6f72155dda73b03c50 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 14 Dec 2015 16:02:38 +0200
Subject: [PATCH 030/972] ad7616_sdz: Update the project

+ Fix system_top.v
+ Finish up the common block design
+ Fix system_project.tcl
---
 projects/ad7616_sdz/common/ad7616_bd.tcl     | 84 +++++++++++++++++++-
 projects/ad7616_sdz/zc706/system_project.tcl |  9 ++-
 projects/ad7616_sdz/zc706/system_top.v       | 35 ++++----
 3 files changed, 106 insertions(+), 22 deletions(-)

diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index c391af651..aaca1734f 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -1,4 +1,24 @@
 
+##--------------------------------------------------------------
+# IMPORTANT: Set AD7616 operation and interface mode
+#
+#    ad7616_opm - Defines the operation mode (software OR hardware)
+#    ad7616_if  - Defines the interface type (serial OR parallel)
+#
+# LEGEND: Software  - 0
+#         Hardware  - 1
+#         Serial    - 0
+#         Parallel  - 1
+#
+# NOTE : These switches are 'hardware' switches. User needs to
+# reimplement the design each and every time, after these variables
+# were changed.
+
+set ad7616_opm  0
+set ad7616_if   0
+
+##--------------------------------------------------------------
+
 # data interfaces
 
 create_bd_port -dir O sclk
@@ -13,14 +33,74 @@ create_bd_port -dir O wr_n
 
 # control lines
 
-create_bd_port -dri O reset_n
+create_bd_port -dir O reset_n
 create_bd_port -dir O cnvst
 create_bd_port -dir O cs_n
-create_bd_port -dir O busy
+create_bd_port -dir I busy
 create_bd_port -dir O seq_en
 create_bd_port -dir O -from 1 -to 0 hw_rngsel
 create_bd_port -dir O -from 2 -to 0 chsel
+create_bd_port -dir O crcen
+create_bd_port -dir O burst
+create_bd_port -dir O -from 2 -to 0 os
 
 # instantiation
 
+set axi_ad7616 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad7616:1.0 axi_ad7616]
+set_property -dict [list CONFIG.OP_MODE $ad7616_opm] $axi_ad7616
+set_property -dict [list CONFIG.IF_TYPE $ad7616_if] $axi_ad7616
+
+set axi_ad7616_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad7616_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad7616_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad7616_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad7616_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad7616_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $axi_ad7616_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad7616_dma
+
+# interface connections
+if {$ad7616_if == 0} {
+
+  ad_connect  sclk axi_ad7616/sclk
+  ad_connect  sdo axi_ad7616/sdo
+  ad_connect  sdi_0 axi_ad7616/sdi_0
+  ad_connect  sdi_1 axi_ad7616/sdi_1
+  ad_connect  cs_n axi_ad7616/cs_n
+
+  ad_connect  reset_n axi_ad7616/reset_n
+  ad_connect  cnvst axi_ad7616/cnvst
+  ad_connect  busy axi_ad7616/busy
+  ad_connect  seq_en axi_ad7616/seq_en
+  ad_connect  hw_rngsel axi_ad7616/hw_rngsel
+  ad_connect  chsel axi_ad7616/chsel
+  ad_connect  crcen axi_ad7616/crcen
+  ad_connect  burst axi_ad7616/burst
+  ad_connect  os axi_ad7616/os
+
+  ad_connect  db_o GND
+  ad_connect  wr_n GND
+  ad_connect  rd_n GND
+
+} else {
+
+}
+
+ad_connect  axi_ad7616/m_axis axi_ad7616_dma/s_axis
+ad_connect  sys_cpu_clk axi_ad7616_dma/s_axis_aclk
+
+# interconnect
+
+ad_cpu_interconnect  0x44A00000 axi_ad7616
+ad_cpu_interconnect  0x44A30000 axi_ad7616_dma
+
+# memory interconnect
+
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk axi_ad7616_dma/m_dest_axi
+ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn
+
+# interrupts
+
+ad_cpu_interrupt ps-13 mb-12 axi_ad7616_dma/irq
+ad_cpu_interrupt ps-12 mb-13 axi_ad7616/irq
 
diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl
index 1890c021d..f13fb9e90 100644
--- a/projects/ad7616_sdz/zc706/system_project.tcl
+++ b/projects/ad7616_sdz/zc706/system_project.tcl
@@ -9,12 +9,15 @@ set ad7616_interface "serial"
 adi_project_create ad7616_sdz_zc706
 
 if { $ad7616_interface eq "serial" } {
+
   adi_project_files ad7616_sdz_zc706 [list \
     "$ad_hdl_dir/library/common/ad_iobuf.v" \
     "system_top.v" \
     "serial_if_constr.xdc" \
     "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
-} else if { $ad7616_interface eq "parallel" } {
+
+} elseif { $ad7616_interface eq "parallel" } {
+
   adi_project_files ad7616_sdz_zc706 [list \
     "$ad_hdl_dir/library/common/ad_iobuf.v" \
     "system_top.v" \
@@ -22,6 +25,10 @@ if { $ad7616_interface eq "serial" } {
     "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
 
 } else {
+
   return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."]
+
 }
 
+adi_project_run ad7616_sdz_zc706
+
diff --git a/projects/ad7616_sdz/zc706/system_top.v b/projects/ad7616_sdz/zc706/system_top.v
index 04e5f13b1..1e1d26bee 100644
--- a/projects/ad7616_sdz/zc706/system_top.v
+++ b/projects/ad7616_sdz/zc706/system_top.v
@@ -77,21 +77,21 @@ module system_top (
   iic_scl,
   iic_sda,
 
+  spi_sclk,
   spi_sdo,
   spi_sdi_0,
   spi_sdi_1,
   spi_cs_n,
 
-  adc_db_o,
-  adc_db_i,
-  adc_rd_n,
-  adc_wr_n,
   adc_reset_n,
-  adc_cnvst,
+  adc_convst,
   adc_busy,
   adc_seq_en,
   adc_hw_rngsel,
-  adc_chsel);
+  adc_chsel,
+  adc_crcen,
+  adc_burst,
+  adc_os);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -129,21 +129,21 @@ module system_top (
   inout           iic_scl;
   inout           iic_sda;
 
+  output          spi_sclk;
   output          spi_sdo;
   input           spi_sdi_0;
   input           spi_sdi_1;
   output          spi_cs_n;
 
-  output  [15:0]  adc_db_o;
-  input   [15:0]  adc_db_i;
-  output          adc_rd_n;
-  output          adc_wr_n;
   output          adc_reset_n;
-  output          adc_cnvst;
+  output          adc_convst;
   output          adc_busy;
   output          adc_seq_en;
   output  [ 1:0]  adc_hw_rngsel;
   output  [ 2:0]  adc_chsel;
+  output          adc_crcen;
+  output          adc_burst;
+  output  [ 2:0]  adc_os;
 
   // internal signals
 
@@ -205,24 +205,21 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
-    .ps_intr_12 (1'b0),
-    .ps_intr_13 (1'b0),
     .spdif (spdif),
     .sclk (spi_sclk),
     .sdo (spi_sdo),
     .sdi_0 (spi_sdi_0),
     .sdi_1 (spi_sdi_1),
-    .db_o (adc_db_o),
-    .db_i (adc_db_i),
-    .rd_n (adc_rd_n),
-    .wr_n (adc_wr_n),
     .reset_n (adc_reset_n),
-    .cnvst (adc_cnvst),
+    .cnvst (adc_convst),
     .cs_n (spi_cs_n),
     .busy (adc_busy),
     .seq_en (adc_seq_en),
     .hw_rngsel (adc_hw_rngsel),
-    .chsel (adc_chsel));
+    .chsel (adc_chsel),
+    .crcen (adc_crcen),
+    .burst (adc_burst),
+    .os (adc_os));
 
 endmodule
 

From 07316a905ef9c23c930bad10ed72b242a489c563 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 14 Dec 2015 09:29:10 -0500
Subject: [PATCH 031/972] daq3/a10gx: sysref is lvds

---
 projects/daq3/a10gx/system_project.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl
index 8c5b3e155..a28b59e65 100644
--- a/projects/daq3/a10gx/system_project.tcl
+++ b/projects/daq3/a10gx/system_project.tcl
@@ -77,6 +77,7 @@ set_location_assignment PIN_AR17  -to sysref                ; ## D17  FMCA_LA13_
 set_location_assignment PIN_AP17  -to "sysref(n)"           ; ## D18  FMCA_LA13_N
 
 set_instance_assignment -name IO_STANDARD LVDS -to trig
+set_instance_assignment -name IO_STANDARD LVDS -to sysref
 
 # spi
 

From 83fd4a53a74c6ccf47348f6fda6d7ca42f6fd4a0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 14 Dec 2015 09:29:48 -0500
Subject: [PATCH 032/972] daq3/kcu105: updates

---
 projects/daq3/kcu105/system_bd.tcl      | 10 ++++----
 projects/daq3/kcu105/system_constr.xdc  | 24 +++++++++----------
 projects/daq3/kcu105/system_project.tcl |  8 +++----
 projects/daq3/kcu105/system_top.v       | 31 ++++++++++++++-----------
 4 files changed, 38 insertions(+), 35 deletions(-)

diff --git a/projects/daq3/kcu105/system_bd.tcl b/projects/daq3/kcu105/system_bd.tcl
index 644363e8d..6852ec9ae 100644
--- a/projects/daq3/kcu105/system_bd.tcl
+++ b/projects/daq3/kcu105/system_bd.tcl
@@ -3,12 +3,12 @@ source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
 
 p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
-p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
+p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
 
-source ../common/daq2_bd.tcl
+source ../common/daq3_bd.tcl
 
-set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $axi_daq2_gt
-set_property -dict [list CONFIG.QPLL0_FBDIV {20}] $axi_daq2_gt
-set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_daq2_gt
+set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $axi_daq3_gt
+set_property -dict [list CONFIG.QPLL0_FBDIV {20}] $axi_daq3_gt
+set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_daq3_gt
 
 
diff --git a/projects/daq3/kcu105/system_constr.xdc b/projects/daq3/kcu105/system_constr.xdc
index 44a8f125c..1a8301883 100644
--- a/projects/daq3/kcu105/system_constr.xdc
+++ b/projects/daq3/kcu105/system_constr.xdc
@@ -1,5 +1,5 @@
 
-# daq2
+# daq3
 
 set_property  -dict {PACKAGE_PIN  H6} [get_ports rx_ref_clk_p]                                              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
 set_property  -dict {PACKAGE_PIN  H5} [get_ports rx_ref_clk_n]                                              ; ## B21  FMC_HPC_GBTCLK1_M2C_N
@@ -20,15 +20,15 @@ set_property  -dict {PACKAGE_PIN  L8  IOSTANDARD LVCMOS18} [get_ports spi_csn_da
 set_property  -dict {PACKAGE_PIN  H9  IOSTANDARD LVCMOS18} [get_ports spi_csn_adc]                          ; ## D15  FMC_HPC_LA09_N
 set_property  -dict {PACKAGE_PIN  K13 IOSTANDARD LVCMOS18} [get_ports spi_clk]                              ; ## D12  FMC_HPC_LA05_N
 set_property  -dict {PACKAGE_PIN  J9  IOSTANDARD LVCMOS18} [get_ports spi_sdio]                             ; ## D14  FMC_HPC_LA09_P
-set_property  -dict {PACKAGE_PIN  H8  IOSTANDARD LVCMOS18} [get_ports spi_dir]                              ; ## G13  FMC_HPC_LA08_N
+set_property  -dict {PACKAGE_PIN  C13 IOSTANDARD LVCMOS18} [get_ports spi_dir]                              ; ## C11  FMC_HPC_LA06_N
 
-set_property  -dict {PACKAGE_PIN  J8  IOSTANDARD LVCMOS18} [get_ports clkd_sync]                            ; ## G12  FMC_HPC_LA08_P
-set_property  -dict {PACKAGE_PIN  K8  IOSTANDARD LVCMOS18} [get_ports dac_reset]                            ; ## C15  FMC_HPC_LA10_N
+set_property  -dict {PACKAGE_PIN  D9  IOSTANDARD LVDS} [get_ports sysref_p]                                 ; ## D17  FMC_HPC_LA13_P
+set_property  -dict {PACKAGE_PIN  C9  IOSTANDARD LVDS} [get_ports sysref_n]                                 ; ## D18  FMC_HPC_LA13_N
 set_property  -dict {PACKAGE_PIN  D10 IOSTANDARD LVCMOS18} [get_ports dac_txen]                             ; ## G16  FMC_HPC_LA12_N
 set_property  -dict {PACKAGE_PIN  D13 IOSTANDARD LVCMOS18} [get_ports adc_pd]                               ; ## C10  FMC_HPC_LA06_P
 
-set_property  -dict {PACKAGE_PIN  D9  IOSTANDARD LVCMOS18} [get_ports clkd_status[0]]                       ; ## D17  FMC_HPC_LA13_P
-set_property  -dict {PACKAGE_PIN  C9  IOSTANDARD LVCMOS18} [get_ports clkd_status[1]]                       ; ## D18  FMC_HPC_LA13_N
+set_property  -dict {PACKAGE_PIN  J8  IOSTANDARD LVCMOS18} [get_ports clkd_status[0]]                       ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  H8  IOSTANDARD LVCMOS18} [get_ports clkd_status[1]]                       ; ## G13  FMC_HPC_LA08_N
 set_property  -dict {PACKAGE_PIN  E10 IOSTANDARD LVCMOS18} [get_ports dac_irq]                              ; ## G15  FMC_HPC_LA12_P
 set_property  -dict {PACKAGE_PIN  K11 IOSTANDARD LVCMOS18} [get_ports adc_fda]                              ; ## H16  FMC_HPC_LA11_P
 set_property  -dict {PACKAGE_PIN  J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb]                              ; ## H17  FMC_HPC_LA11_N
@@ -40,8 +40,8 @@ set_property  -dict {PACKAGE_PIN  E8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [g
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/RXOUTCLK]
 
 # gt pin assignments below are for reference only and are ignored by the tool!
 
@@ -62,8 +62,8 @@ create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_
 ##  set_property  -dict {PACKAGE_PIN  D6} [get_ports tx_data_p[3]] ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
 ##  set_property  -dict {PACKAGE_PIN  D5} [get_ports tx_data_n[3]] ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
 
-set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[1].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[2].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[3].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *axi_daq3_gt/inst/g_lane_1[1].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *axi_daq3_gt/inst/g_lane_1[2].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *axi_daq3_gt/inst/g_lane_1[3].i_channel/i_gt/i_gthe3_channel}]
 
diff --git a/projects/daq3/kcu105/system_project.tcl b/projects/daq3/kcu105/system_project.tcl
index 5d2541fd6..1d0b428b7 100644
--- a/projects/daq3/kcu105/system_project.tcl
+++ b/projects/daq3/kcu105/system_project.tcl
@@ -5,9 +5,9 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create daq2_kcu105
-adi_project_files daq2_kcu105 [list \
-  "../common/daq2_spi.v" \
+adi_project_create daq3_kcu105
+adi_project_files daq3_kcu105 [list \
+  "../common/daq3_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
@@ -16,6 +16,6 @@ adi_project_files daq2_kcu105 [list \
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
-adi_project_run daq2_kcu105
+adi_project_run daq3_kcu105
 
 
diff --git a/projects/daq3/kcu105/system_top.v b/projects/daq3/kcu105/system_top.v
index fbf439919..41b045656 100644
--- a/projects/daq3/kcu105/system_top.v
+++ b/projects/daq3/kcu105/system_top.v
@@ -108,8 +108,8 @@ module system_top (
 
   adc_pd,
   dac_txen,
-  dac_reset,
-  clkd_sync,
+  sysref_p,
+  sysref_n,
 
   spi_csn_clk,
   spi_csn_dac,
@@ -185,8 +185,8 @@ module system_top (
 
   inout           adc_pd;
   inout           dac_txen;
-  inout           dac_reset;
-  inout           clkd_sync;
+  output          sysref_p;
+  output          sysref_n;
 
   output          spi_csn_clk;
   output          spi_csn_dac;
@@ -257,7 +257,7 @@ module system_top (
     .IB (tx_sync_n),
     .O (tx_sync));
 
-  daq2_spi i_spi (
+  daq3_spi i_spi (
     .spi_csn (spi_csn[2:0]),
     .spi_clk (spi_clk),
     .spi_mosi (spi_mosi),
@@ -265,21 +265,24 @@ module system_top (
     .spi_sdio (spi_sdio),
     .spi_dir (spi_dir));
 
+  OBUFDS i_obufds_sysref (
+    .I (gpio_o[40]),
+    .O (sysref_p),
+    .OB (sysref_n));
+
   IBUFDS i_ibufds_trig (
     .I (trig_p),
     .IB (trig_n),
     .O (trig));
 
-  assign gpio_i[43] = trig;
+  assign gpio_i[39] = trig;
 
-  ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
-    .dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
-    .dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
-    .dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
-    .dio_p ({ adc_pd,           // 42
-              dac_txen,         // 41
-              dac_reset,        // 40
-              clkd_sync,        // 38
+  ad_iobuf #(.DATA_WIDTH(7)) i_iobuf (
+    .dio_t (gpio_t[38:32]),
+    .dio_i (gpio_o[38:32]),
+    .dio_o (gpio_i[38:32]),
+    .dio_p ({ adc_pd,           // 38
+              dac_txen,         // 37
               adc_fdb,          // 36
               adc_fda,          // 35
               dac_irq,          // 34

From 40ab2f5e6a4bbe594d97976f985a169193dcfd29 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Dec 2015 11:37:57 -0500
Subject: [PATCH 033/972] ccfmc: tdd/gpio bit moved to the top

---
 projects/pzsdr/ccfmc/system_top.v | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/projects/pzsdr/ccfmc/system_top.v b/projects/pzsdr/ccfmc/system_top.v
index 7283406a5..62786b4a8 100644
--- a/projects/pzsdr/ccfmc/system_top.v
+++ b/projects/pzsdr/ccfmc/system_top.v
@@ -338,19 +338,17 @@ module system_top (
     .O (gt_ref_clk_1),
     .ODIV2 ());
 
-  assign gp_out_0 = gp_out_s[58:58];
-  assign gp_out[56:35] = gp_out_s[57:36];
-  assign gp_out[34: 0] = gp_out_s[34: 0];
+  assign gp_out_0 = 1'd0;
+  assign gp_out[56:0] = gp_out_s[56:0];
 
   assign gp_in_s[63:63] = gp_in_0;
-  assign gp_in_s[58:58] = 1'd0;
-  assign gp_in_s[57:36] = gp_in[56:35];
-  assign gp_in_s[35:35] = gp_out_s[62] & gpio_tdd_sync_i;
-  assign gp_in_s[34: 0] = gp_in[34: 0];
+  assign gp_in_s[62:58] = gp_out_s[62:58];
+  assign gp_in_s[57:57] = gp_out_s[62] & gpio_tdd_sync_i;
+  assign gp_in_s[56: 0] = gp_in[56:0];
 
   ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_35_0 (
     .dio_t (1'b0),
-    .dio_i (gp_out_s[35]),
+    .dio_i (gp_out_s[57]),
     .dio_o (),
     .dio_p (gp_inout_0));
 

From ea045a3f9af54edb2173a40d978c915a871286f9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Dec 2015 12:34:47 -0500
Subject: [PATCH 034/972] fmcadc4: change qpll to receive

---
 projects/fmcadc4/common/fmcadc4_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl
index a18f2ca6d..0129b4031 100644
--- a/projects/fmcadc4/common/fmcadc4_bd.tcl
+++ b/projects/fmcadc4/common/fmcadc4_bd.tcl
@@ -46,6 +46,7 @@ set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc4_gt
 set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcadc4_gt
 
 set util_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc4_gt]
+set_property -dict [list CONFIG.QPLL_TX_OR_RX_N {0}] $util_fmcadc4_gt
 set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_fmcadc4_gt
 set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $util_fmcadc4_gt
 set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc4_gt

From f3fe16a1029c802e690973c0ccc5b9250095d1c4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Dec 2015 16:17:24 -0500
Subject: [PATCH 035/972] pzsdr/ccfmc: camera/sfp pin changes

---
 projects/pzsdr/ccfmc/system_constr.xdc | 82 +++++++++++++-------------
 projects/pzsdr/ccfmc/system_top.v      | 32 ++++++----
 2 files changed, 61 insertions(+), 53 deletions(-)

diff --git a/projects/pzsdr/ccfmc/system_constr.xdc b/projects/pzsdr/ccfmc/system_constr.xdc
index 114de9c10..ac6233513 100644
--- a/projects/pzsdr/ccfmc/system_constr.xdc
+++ b/projects/pzsdr/ccfmc/system_constr.xdc
@@ -191,48 +191,48 @@ set_property  -dict {PACKAGE_PIN  AF3}  [get_ports gt_tx_1_n]
 set_property  -dict {PACKAGE_PIN  AE6}  [get_ports gt_rx_1_p]                                             ; ## MGTXRXP1_111      (sfp_gt_rx_p)
 set_property  -dict {PACKAGE_PIN  AE5}  [get_ports gt_rx_1_n]                                             ; ## MGTXRXN1_111      (sfp_gt_rx_n)
 
-set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD LVCMOS18} [get_ports gp_out[37]]                       ; ## IO_L13P_T2_MRCC_33      (cam_gpio[ 0])     
-set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD LVCMOS18} [get_ports gp_out[38]]                       ; ## IO_L13N_T2_MRCC_33      (cam_gpio[ 1])     
-set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD LVCMOS18} [get_ports gp_out[39]]                       ; ## IO_L14P_T2_SRCC_33      (cam_gpio[ 2])     
-set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD LVCMOS18} [get_ports gp_out[40]]                       ; ## IO_L14N_T2_SRCC_33      (cam_gpio[ 3])     
-set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD LVCMOS18} [get_ports gp_out[41]]                       ; ## IO_L15P_T2_DQS_33       (cam_gpio[ 4])     
-set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD LVCMOS18} [get_ports gp_out[42]]                       ; ## IO_L15N_T2_DQS_33       (cam_gpio[ 5])     
-set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD LVCMOS18} [get_ports gp_out[43]]                       ; ## IO_L16P_T2_33           (cam_gpio[ 6])     
-set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD LVCMOS18} [get_ports gp_out[44]]                       ; ## IO_L16N_T2_33           (cam_gpio[ 7])     
-set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD LVCMOS18} [get_ports gp_out[45]]                       ; ## IO_L17P_T2_33           (cam_gpio[ 8])     
-set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD LVCMOS18} [get_ports gp_out[46]]                       ; ## IO_L17N_T2_33           (cam_gpio[ 9])     
-set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD LVCMOS18} [get_ports gp_out[47]]                       ; ## IO_L18P_T2_33           (cam_gpio[10])     
-set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD LVCMOS18} [get_ports gp_out[48]]                       ; ## IO_L18N_T2_33           (cam_gpio[11])     
-set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD LVCMOS18} [get_ports gp_out[49]]                       ; ## IO_L19P_T3_33           (cam_gpio[12])     
-set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD LVCMOS18} [get_ports gp_out[50]]                       ; ## IO_L19N_T3_VREF_33      (cam_gpio[13])     
-set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD LVCMOS18} [get_ports gp_out[51]]                       ; ## IO_L20P_T3_33           (cam_gpio[14])     
-set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD LVCMOS18} [get_ports gp_out[52]]                       ; ## IO_L20N_T3_33           (cam_gpio[15])     
-set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD LVCMOS18} [get_ports gp_out[53]]                       ; ## IO_L21P_T3_DQS_33       (cam_gpio[16])     
-set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD LVCMOS18} [get_ports gp_in[37]]                        ; ## IO_L21N_T3_DQS_33       (cam_gpio[17]) 
-set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD LVCMOS18} [get_ports gp_in[38]]                        ; ## IO_L22P_T3_33           (cam_gpio[18]) 
-set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD LVCMOS18} [get_ports gp_in[39]]                        ; ## IO_L22N_T3_33           (cam_gpio[19]) 
-set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD LVCMOS18} [get_ports gp_in[40]]                        ; ## IO_L23P_T3_33           (cam_gpio[20]) 
-set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD LVCMOS18} [get_ports gp_in[41]]                        ; ## IO_L23N_T3_33           (cam_gpio[21]) 
-set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD LVCMOS18} [get_ports gp_in[42]]                        ; ## IO_L24P_T3_33           (cam_gpio[22]) 
-set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD LVCMOS18} [get_ports gp_in[43]]                        ; ## IO_L24N_T3_33           (cam_gpio[23]) 
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports gp_in[44]]                        ; ## IO_L1P_T0_34            (cam_gpio[24]) 
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports gp_in[45]]                        ; ## IO_L1N_T0_34            (cam_gpio[25]) 
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports gp_in[46]]                        ; ## IO_L2P_T0_34            (cam_gpio[26]) 
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports gp_in[47]]                        ; ## IO_L2N_T0_34            (cam_gpio[27]) 
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports gp_in[48]]                        ; ## IO_L3P_T0_DQS_PUDC_B_34 (cam_gpio[28]) 
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports gp_in[49]]                        ; ## IO_L3N_T0_DQS_34        (cam_gpio[29]) 
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports gp_in[50]]                        ; ## IO_L4P_T0_34            (cam_gpio[30]) 
-set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD LVCMOS18} [get_ports gp_in[51]]                        ; ## IO_L4N_T0_34            (cam_gpio[31]) 
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports gp_in[52]]                        ; ## IO_L5P_T0_34            (cam_gpio[32]) 
-set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD LVCMOS18} [get_ports gp_in[53]]                        ; ## IO_L12P_T1_MRCC_33      (cam_gpio[33]) 
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports gp_in[37]]                        ; ## IO_L1P_T0_34            (CAM_GPIO_0  ) 
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports gp_in[38]]                        ; ## IO_L1N_T0_34            (CAM_GPIO_1  ) 
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports gp_in[39]]                        ; ## IO_L3P_T0_DQS_PUDC_B_34 (CAM_GPIO_4  ) 
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports gp_in[40]]                        ; ## IO_L3N_T0_DQS_34        (CAM_GPIO_5  ) 
+set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD LVCMOS18} [get_ports gp_in[41]]                        ; ## IO_L13P_T2_MRCC_33      (CAM_CLK_P   )     
+set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD LVCMOS18} [get_ports gp_in[42]]                        ; ## IO_L13N_T2_MRCC_33      (CAM_CLK_N   )     
+set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD LVCMOS18} [get_ports gp_in[43]]                        ; ## IO_L16P_T2_33           (CAM_DATA1_P )     
+set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD LVCMOS18} [get_ports gp_in[44]]                        ; ## IO_L16N_T2_33           (CAM_DATA1_N )     
+set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD LVCMOS18} [get_ports gp_in[45]]                        ; ## IO_L18P_T2_33           (CAM_DATA3_P )     
+set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD LVCMOS18} [get_ports gp_in[46]]                        ; ## IO_L18N_T2_33           (CAM_DATA3_N )     
+set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD LVCMOS18} [get_ports gp_in[47]]                        ; ## IO_L20P_T3_33           (CAM_DATA5_P )     
+set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD LVCMOS18} [get_ports gp_in[48]]                        ; ## IO_L20N_T3_33           (CAM_DATA5_N )     
+set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD LVCMOS18} [get_ports gp_in[49]]                        ; ## IO_L22P_T3_33           (CAM_DATA7_P ) 
+set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD LVCMOS18} [get_ports gp_in[50]]                        ; ## IO_L22N_T3_33           (CAM_DATA7_N ) 
+set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD LVCMOS18} [get_ports gp_in[51]]                        ; ## IO_L23P_T3_33           (CAM_SPI_CSN ) 
+set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD LVCMOS18} [get_ports gp_in[52]]                        ; ## IO_L23N_T3_33           (CAM_SPI_CLK ) 
+set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD LVCMOS18} [get_ports gp_in[53]]                        ; ## IO_L12P_T1_MRCC_33      (CAM_REFCLK  ) 
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports gp_out[37]]                       ; ## IO_L2P_T0_34            (CAM_GPIO_2  ) 
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports gp_out[38]]                       ; ## IO_L2N_T0_34            (CAM_GPIO_3  ) 
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports gp_out[39]]                       ; ## IO_L4P_T0_34            (CAM_GPIO_6  ) 
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD LVCMOS18} [get_ports gp_out[40]]                       ; ## IO_L4N_T0_34            (CAM_GPIO_7  ) 
+set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD LVCMOS18} [get_ports gp_out[41]]                       ; ## IO_L15P_T2_DQS_33       (CAM_DATA0_P )     
+set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD LVCMOS18} [get_ports gp_out[42]]                       ; ## IO_L15N_T2_DQS_33       (CAM_DATA0_N )     
+set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD LVCMOS18} [get_ports gp_out[43]]                       ; ## IO_L17P_T2_33           (CAM_DATA2_P )     
+set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD LVCMOS18} [get_ports gp_out[44]]                       ; ## IO_L17N_T2_33           (CAM_DATA2_N )     
+set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD LVCMOS18} [get_ports gp_out[45]]                       ; ## IO_L19P_T3_33           (CAM_DATA4_P )     
+set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD LVCMOS18} [get_ports gp_out[46]]                       ; ## IO_L19N_T3_VREF_33      (CAM_DATA4_N )     
+set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD LVCMOS18} [get_ports gp_out[47]]                       ; ## IO_L21P_T3_DQS_33       (CAM_DATA6_P )     
+set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD LVCMOS18} [get_ports gp_out[48]]                       ; ## IO_L21N_T3_DQS_33       (CAM_DATA6_N ) 
+set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD LVCMOS18} [get_ports gp_out[49]]                       ; ## IO_L14P_T2_SRCC_33      (CAM_SYNC_P  )     
+set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD LVCMOS18} [get_ports gp_out[50]]                       ; ## IO_L14N_T2_SRCC_33      (CAM_SYNC_N  )     
+set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD LVCMOS18} [get_ports gp_out[51]]                       ; ## IO_L24P_T3_33           (CAM_SPI_MISO) 
+set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD LVCMOS18} [get_ports gp_out[52]]                       ; ## IO_L24N_T3_33           (CAM_SPI_MOSI) 
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports gp_out[53]]                       ; ## IO_L5P_T0_34            (CAM_GPIO_8  ) 
 
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD LVCMOS25} [get_ports gp_out[54]]                       ; ## IO_L19P_T3_12           (sfp_gpio[0])
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS25} [get_ports gp_out[55]]                       ; ## IO_L19N_T3_VREF_12      (sfp_gpio[1])
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gp_out[56]]                       ; ## IO_L20P_T3_12           (sfp_gpio[2])
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS25} [get_ports gp_out_0]                         ; ## IO_L20N_T3_12           (sfp_gpio[3])
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gp_in[54]]                        ; ## IO_L21P_T3_DQS_12       (sfp_gpio[4])
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gp_in[55]]                        ; ## IO_L21N_T3_DQS_12       (sfp_gpio[5])
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVCMOS25} [get_ports gp_in[56]]                        ; ## IO_L22P_T3_12           (sfp_gpio[6])
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD LVCMOS25} [get_ports gp_inout[0]]                      ; ## IO_L19P_T3_12           (sfp_gpio[0])
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS25} [get_ports gp_inout[1]]                      ; ## IO_L19N_T3_VREF_12      (sfp_gpio[1])
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gp_inout[2]]                      ; ## IO_L20P_T3_12           (sfp_gpio[2])
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS25} [get_ports gp_inout[3]]                      ; ## IO_L20N_T3_12           (sfp_gpio[3])
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gp_inout[4]]                      ; ## IO_L21P_T3_DQS_12       (sfp_gpio[4])
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gp_inout[5]]                      ; ## IO_L21N_T3_DQS_12       (sfp_gpio[5])
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVCMOS25} [get_ports gp_inout[6]]                      ; ## IO_L22P_T3_12           (sfp_gpio[6])
 
 # clocks
 
diff --git a/projects/pzsdr/ccfmc/system_top.v b/projects/pzsdr/ccfmc/system_top.v
index 62786b4a8..a9a748a02 100644
--- a/projects/pzsdr/ccfmc/system_top.v
+++ b/projects/pzsdr/ccfmc/system_top.v
@@ -98,9 +98,9 @@ module system_top (
   clk_1_p,
   clk_1_n,
   gp_in_0,
-  gp_out_0,
   gp_inout_0,
   gp_inout_1,
+  gp_inout,
   gp_out,
   gp_in,
 
@@ -220,11 +220,11 @@ module system_top (
   input           clk_1_p;
   input           clk_1_n;
   input           gp_in_0;
-  output          gp_out_0;
   inout           gp_inout_0;
   inout           gp_inout_1;
-  output  [56:0]  gp_out;
-  input   [56:0]  gp_in;
+  inout   [ 6:0]  gp_inout;
+  output  [53:0]  gp_out;
+  input   [53:0]  gp_in;
 
   input           gt_ref_clk_0_p;
   input           gt_ref_clk_0_n;
@@ -292,6 +292,7 @@ module system_top (
   wire            clk_1;
   wire            gt_ref_clk_0;
   wire            gt_ref_clk_1;
+  wire    [63:0]  gp_ioenb_s;
   wire    [63:0]  gp_out_s;
   wire    [63:0]  gp_in_s;
   wire    [63:0]  gpio_i;
@@ -338,21 +339,26 @@ module system_top (
     .O (gt_ref_clk_1),
     .ODIV2 ());
 
-  assign gp_out_0 = 1'd0;
-  assign gp_out[56:0] = gp_out_s[56:0];
+  assign gp_out[53:0] = gp_out_s[53:0];
+  assign gp_in_s[53:0] = gp_in[53:0];
 
   assign gp_in_s[63:63] = gp_in_0;
-  assign gp_in_s[62:58] = gp_out_s[62:58];
-  assign gp_in_s[57:57] = gp_out_s[62] & gpio_tdd_sync_i;
-  assign gp_in_s[56: 0] = gp_in[56:0];
+  assign gp_in_s[62:62] = gp_out_s[62];
+  assign gp_in_s[54:54] = gp_out_s[62] & gpio_tdd_sync_i;
 
-  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_35_0 (
+  ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_61_55 (
+    .dio_t (gp_ioenb_s[61:55]),
+    .dio_i (gp_out_s[61:55]),
+    .dio_o (gp_in_s[61:55]),
+    .dio_p (gp_inout));
+
+  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_0 (
     .dio_t (1'b0),
-    .dio_i (gp_out_s[57]),
+    .dio_i (gp_out_s[54]),
     .dio_o (),
     .dio_p (gp_inout_0));
 
-  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_35_1 (
+  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_1 (
     .dio_t (gpio_tdd_sync_t),
     .dio_i (gpio_tdd_sync_o),
     .dio_o (gpio_tdd_sync_i),
@@ -432,6 +438,8 @@ module system_top (
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
     .gp_in_0 (gp_in_s[31:0]),
     .gp_in_1 (gp_in_s[63:32]),
+    .gp_ioenb_0 (gp_ioenb_s[31:0]),
+    .gp_ioenb_1 (gp_ioenb_s[63:32]),
     .gp_out_0 (gp_out_s[31:0]),
     .gp_out_1 (gp_out_s[63:32]),
     .gpio_i (gpio_i),

From 2bb19be3d350baf20dc43c8cbc7c6249ef57facd Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Dec 2015 16:18:06 -0500
Subject: [PATCH 036/972] pzsdr/ccfmc: sfp io control

---
 projects/pzsdr/common/ccfmc_bd.tcl | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr/common/ccfmc_bd.tcl
index 76ca44c2d..96ca5123f 100644
--- a/projects/pzsdr/common/ccfmc_bd.tcl
+++ b/projects/pzsdr/common/ccfmc_bd.tcl
@@ -260,11 +260,15 @@ create_bd_port -dir I -from 31 -to 0 gp_in_0
 create_bd_port -dir I -from 31 -to 0 gp_in_1
 create_bd_port -dir O -from 31 -to 0 gp_out_0
 create_bd_port -dir O -from 31 -to 0 gp_out_1
+create_bd_port -dir O -from 31 -to 0 gp_ioenb_0
+create_bd_port -dir O -from 31 -to 0 gp_ioenb_1
 
 ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
 ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
 ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
 ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
+ad_connect  gp_ioenb_0 axi_gpreg/up_gp_ioenb_0
+ad_connect  gp_ioenb_1 axi_gpreg/up_gp_ioenb_1
 ad_connect  axi_gpreg/up_gp_in_2 util_pzslb_gtlb_0/up_gp_out
 ad_connect  axi_gpreg/up_gp_out_2 util_pzslb_gtlb_0/up_gp_in
 ad_connect  axi_gpreg/up_gp_in_3 util_pzslb_gtlb_1/up_gp_out

From 17e7d1b86ffb1669204873c0be4a4c0079d2ceb4 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 21 Dec 2015 17:09:42 +0200
Subject: [PATCH 037/972] ad7616: Add Makefiles

---
 library/Makefile                   |  4 ++
 library/axi_ad7616/Makefile        | 53 +++++++++++++++++++++
 projects/Makefile                  |  3 ++
 projects/ad7616_sdz/Makefile       | 21 +++++++++
 projects/ad7616_sdz/zc706/Makefile | 75 ++++++++++++++++++++++++++++++
 5 files changed, 156 insertions(+)
 create mode 100644 library/axi_ad7616/Makefile
 create mode 100644 projects/ad7616_sdz/Makefile
 create mode 100644 projects/ad7616_sdz/zc706/Makefile

diff --git a/library/Makefile b/library/Makefile
index fdd46d564..18adebd7b 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -11,6 +11,7 @@ all: lib
 
 clean:
 	make -C axi_ad6676 clean
+	make -C axi_ad7616 clean
 	make -C axi_ad9122 clean
 	make -C axi_ad9144 clean
 	make -C axi_ad9152 clean
@@ -61,6 +62,7 @@ clean:
 	make -C util_gtlb clean
 	make -C util_i2c_mixer clean
 	make -C util_jesd_gt clean
+	make -C util_mfifo clean
 	make -C util_pmod_adc clean
 	make -C util_pmod_fmeter clean
 	make -C util_rfifo clean
@@ -74,6 +76,7 @@ clean-all:clean
 
 lib:
 	-make -C axi_ad6676
+	-make -C axi_ad7616
 	-make -C axi_ad9122
 	-make -C axi_ad9144
 	-make -C axi_ad9152
@@ -124,6 +127,7 @@ lib:
 	-make -C util_gtlb
 	-make -C util_i2c_mixer
 	-make -C util_jesd_gt
+	-make -C util_mfifo
 	-make -C util_pmod_adc
 	-make -C util_pmod_fmeter
 	-make -C util_rfifo
diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile
new file mode 100644
index 000000000..5b2377ffa
--- /dev/null
+++ b/library/axi_ad7616/Makefile
@@ -0,0 +1,53 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := axi_ad7616_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += axi_ad7616.v
+M_DEPS += ../spi_engine_execution/spi_engine_execution.xpr
+M_DEPS += ../axi_spi_engine/axi_spi_engine.xpr
+M_DEPS += ../spi_engine_offload/spi_engine_offload.xpr
+M_DEPS += ../spi_engine_interconnect/spi_engine_interconnect.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += .Xil
+M_FLIST += *.hw
+M_FLIST += *.sim
+
+
+
+.PHONY: all dep clean clean-all
+all: dep axi_ad7616.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_ad7616.xpr: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_ad7616_ip.tcl  >> axi_ad7616_ip.log 2>&1
+
+dep:
+	make -C ../spi_engine_execution
+	make -C ../axi_spi_engine
+	make -C ../spi_engine_offload
+	make -C ../spi_engine_interconnect
+####################################################################################
+####################################################################################
diff --git a/projects/Makefile b/projects/Makefile
index 75ec31ca4..58ebda31b 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -8,6 +8,7 @@
 .PHONY: all clean clean_all
 all:
 	-make -C ad6676evb all
+	-make -C ad7616_sdz all
 	-make -C ad9265_fmc all
 	-make -C ad9434_fmc all
 	-make -C ad9467_fmc all
@@ -39,6 +40,7 @@ all:
 
 clean:
 	make -C ad6676evb clean
+	make -C ad7616_sdz clean
 	make -C ad9265_fmc clean
 	make -C ad9434_fmc clean
 	make -C ad9467_fmc clean
@@ -70,6 +72,7 @@ clean:
 
 clean-all:
 	make -C ad6676evb clean-all
+	make -C ad7616_sdz clean-all
 	make -C ad9265_fmc clean-all
 	make -C ad9434_fmc clean-all
 	make -C ad9467_fmc clean-all
diff --git a/projects/ad7616_sdz/Makefile b/projects/ad7616_sdz/Makefile
new file mode 100644
index 000000000..5b866a1ac
--- /dev/null
+++ b/projects/ad7616_sdz/Makefile
@@ -0,0 +1,21 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+.PHONY: all clean clean-all 
+all:
+	-make -C zc706 all
+
+
+clean: 
+	make -C zc706 clean
+
+
+clean-all:
+	make -C zc706 clean-all
+
+####################################################################################
+####################################################################################
diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile
new file mode 100644
index 000000000..c98945b51
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/Makefile
@@ -0,0 +1,75 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_bd.tcl
+M_DEPS += serial_if_constr.xdc
+M_DEPS += parallel_if_constr.xdc
+M_DEPS += ../common/ad7616_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zc706/zc706_system_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += .Xil
+M_FLIST += *.hw
+M_FLIST += *.sim
+
+
+
+.PHONY: all lib clean clean-all
+all: lib ad7616_sdz_zc706.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad7616 clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_spdif_tx clean
+
+
+ad7616_sdz_zc706.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> ad7616_sdz_zc706_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad7616
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_spdif_tx
+
+####################################################################################
+####################################################################################

From 0b55325db9422c71e2db4e71453dc121933cc928 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 21 Dec 2015 19:39:14 +0200
Subject: [PATCH 038/972] axi_ad7616: Fix IP packaging script

---
 library/axi_ad7616/axi_ad7616_ip.tcl | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/library/axi_ad7616/axi_ad7616_ip.tcl b/library/axi_ad7616/axi_ad7616_ip.tcl
index 10a7c0825..1ebd172e6 100644
--- a/library/axi_ad7616/axi_ad7616_ip.tcl
+++ b/library/axi_ad7616/axi_ad7616_ip.tcl
@@ -5,7 +5,12 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create axi_ad7616
 adi_ip_files axi_ad7616 [list \
-    "axi_ad7616.v" ]
+    "axi_ad7616.v" \
+    "axi_ad7616_control.v" \
+    "$ad_hdl_dir/library/common/ad_edge_detect.v" \
+    "$ad_hdl_dir/library/common/up_axi.v"]
+
+adi_ip_properties axi_ad7616
 
 adi_ip_add_core_dependencies { \
     analog.com:user:spi_engine_execution:1.0 \
@@ -14,3 +19,5 @@ adi_ip_add_core_dependencies { \
     analog.com:user:spi_engine_interconnect:1.0 \
 }
 
+ipx::save_core [ipx::current_core]
+

From c29dd8fad565df92123af49a84caac6814d4e6a3 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 21 Dec 2015 19:39:58 +0200
Subject: [PATCH 039/972] axi_ad7616: Fix Makefile

---
 library/axi_ad7616/Makefile | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile
index 5b2377ffa..82f6c7bd0 100644
--- a/library/axi_ad7616/Makefile
+++ b/library/axi_ad7616/Makefile
@@ -9,10 +9,11 @@ M_DEPS := axi_ad7616_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_ad7616.v
-M_DEPS += ../spi_engine_execution/spi_engine_execution.xpr
-M_DEPS += ../axi_spi_engine/axi_spi_engine.xpr
-M_DEPS += ../spi_engine_offload/spi_engine_offload.xpr
-M_DEPS += ../spi_engine_interconnect/spi_engine_interconnect.xpr
+M_DEPS += axi_ad7616_control.v
+M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
+M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
+M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
+M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -45,9 +46,9 @@ axi_ad7616.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_ad7616_ip.tcl  >> axi_ad7616_ip.log 2>&1
 
 dep:
-	make -C ../spi_engine_execution
-	make -C ../axi_spi_engine
-	make -C ../spi_engine_offload
-	make -C ../spi_engine_interconnect
+	make -C ../spi_engine/spi_engine_execution
+	make -C ../spi_engine/axi_spi_engine
+	make -C ../spi_engine/spi_engine_offload
+	make -C ../spi_engine/spi_engine_interconnect
 ####################################################################################
 ####################################################################################

From 02cc926275777a461f48b02cab60678e906889d1 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 4 Jan 2016 18:10:46 +0200
Subject: [PATCH 040/972] daq1: Add CPLD logic and IO constraints

---
 projects/daq1/cpld/daq1_cpld.ucf |  30 ++++
 projects/daq1/cpld/daq1_cpld.v   | 271 +++++++++++++++++++++++++++++++
 2 files changed, 301 insertions(+)
 create mode 100644 projects/daq1/cpld/daq1_cpld.ucf
 create mode 100644 projects/daq1/cpld/daq1_cpld.v

diff --git a/projects/daq1/cpld/daq1_cpld.ucf b/projects/daq1/cpld/daq1_cpld.ucf
new file mode 100644
index 000000000..09013707c
--- /dev/null
+++ b/projects/daq1/cpld/daq1_cpld.ucf
@@ -0,0 +1,30 @@
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_fda"  LOC = "P6" | IOSTANDARD = LVCMOS33 ; 
+NET "adc_fdb"  LOC = "P7" | IOSTANDARD = LVCMOS33 ; 
+NET "adc_pwdn_stby"  LOC = "P10" | IOSTANDARD = LVCMOS33 ; 
+NET "adc_spicsn"  LOC = "P13" | IOSTANDARD = LVCMOS33 ; 
+NET "adc_status_n"  LOC = "P9" | IOSTANDARD = LVCMOS33 ; 
+NET "adc_status_p"  LOC = "P8" | IOSTANDARD = LVCMOS33 ; 
+NET "clk_pwdnn"  LOC = "P20" | IOSTANDARD = LVCMOS33 ; 
+NET "clk_resetn"  LOC = "P25" | IOSTANDARD = LVCMOS33 ; 
+NET "clk_spicsn"  LOC = "P15" | IOSTANDARD = LVCMOS33 ; 
+NET "clk_status1"  LOC = "P17" | IOSTANDARD = LVCMOS33 ; 
+NET "clk_status2"  LOC = "P18" | IOSTANDARD = LVCMOS33 ; 
+NET "clk_syncn"  LOC = "P24" | IOSTANDARD = LVCMOS33 ; 
+NET "dac_irqn"  LOC = "P26" | IOSTANDARD = LVCMOS33 ; 
+NET "dac_resetn"  LOC = "P27" | IOSTANDARD = LVCMOS33 ; 
+NET "dac_spicsn"  LOC = "P14" | IOSTANDARD = LVCMOS33 ; 
+NET "fmc_irq"  LOC = "P5" | IOSTANDARD = LVCMOS25 ; 
+NET "fmc_spi_csn"  LOC = "P2" | IOSTANDARD = LVCMOS25 ; 
+NET "fmc_spi_sclk"  LOC = "P1" | IOSTANDARD = LVCMOS25; 
+NET "fmc_spi_sdio"  LOC = "P4" | IOSTANDARD = LVCMOS25 ; 
+NET "sclk"  LOC = "P30" | IOSTANDARD = LVCMOS33 ; 
+NET "sdio"  LOC = "P28" | IOSTANDARD = LVCMOS33 ; 
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
new file mode 100644
index 000000000..8f77b4d4f
--- /dev/null
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -0,0 +1,271 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module daq1_cpld (
+
+  // FMC SPI interface
+
+  fmc_spi_sclk,
+  fmc_spi_csn,
+  fmc_spi_sdio,
+  fmc_irq,
+
+  // on board SPI interface
+
+  adc_spicsn,
+  dac_spicsn,
+  clk_spicsn,
+  sclk,
+  sdio,
+
+  // control and status lines
+
+  adc_fda,
+  adc_fdb,
+  adc_status_p,
+  adc_status_n,
+  adc_pwdn_stby,
+
+  dac_irqn,
+  dac_resetn,
+
+  clk_status1,
+  clk_status2,
+  clk_pwdnn,
+  clk_syncn,
+  clk_resetn
+
+);
+
+  input   fmc_spi_csn;
+  input   fmc_spi_sclk;
+  inout   fmc_spi_sdio;
+  output  fmc_irq;
+
+  output  adc_spicsn;
+  output  dac_spicsn;
+  output  clk_spicsn;
+  output  sclk;
+  inout   sdio;
+
+  // control and status lines
+
+  input   adc_fda;
+  input   adc_fdb;
+  input   adc_status_p;
+  input   adc_status_n;
+  output  adc_pwdn_stby;
+
+  input   dac_irqn;
+  output  dac_resetn;
+
+  input   clk_status1;
+  input   clk_status2;
+  output  clk_pwdnn;
+  output  clk_syncn;
+  output  clk_resetn;
+
+  // FMC SPI Selects
+
+  localparam  [ 7:0]  FMC_SPI_SEL_AD9684  = 8'h80;
+  localparam  [ 7:0]  FMC_SPI_SEL_AD9122  = 8'h81;
+  localparam  [ 7:0]  FMC_SPI_SEL_AD9523  = 8'h82;
+  localparam  [ 7:0]  FMC_SPI_SEL_CPLD    = 8'h83;
+
+  // CPLD Register Map Addresses
+
+  localparam  [ 6:0]  ADC_CONTROL_ADDR    = 7'h00;
+  localparam  [ 6:0]  DAC_CONTROL_ADDR    = 7'h01;
+  localparam  [ 6:0]  CLK_CONTROL_ADDR    = 7'h02;
+  localparam  [ 6:0]  ADC_STATUS_ADDR     = 7'h10;
+  localparam  [ 6:0]  DAC_STATUS_ADDR     = 7'h11;
+  localparam  [ 6:0]  CLK_STATUS_ADDR     = 7'h12;
+
+  // Internal Registers/Signals
+
+  reg   [ 7:0]  fmc_spi_dev_sel = 8'b0;
+  reg   [ 7:0]  fmc_cpld_addr = 8'b0;
+  reg   [ 5:0]  fmc_spi_counter = 6'b0;
+  reg           fmc_spi_csn_enb = 1'b1;
+
+  reg   [ 7:0]  adc_control = 8'b0;
+  reg   [ 7:0]  dac_control = 8'b0;
+  reg   [ 7:0]  clk_control = 8'b0;
+
+  reg   [ 7:0]  adc_status = 8'b0;
+  reg   [ 7:0]  dac_status = 8'b0;
+  reg   [ 7:0]  clk_status = 8'b0;
+
+  reg           fpga_to_cpld = 1'b1;
+  reg    [ 7:0] cpld_rdata = 8'b0;
+  reg           cpld_rdata_bit = 1'b0;
+  reg    [ 2:0] cpld_rdata_index = 3'h0;
+  reg    [ 7:0] cpld_wdata = 8'b0;
+
+  wire          rdnwr;
+  wire          cpld_rdata_s;
+
+  // SCLK counter for control signals
+
+  always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
+    if (fmc_spi_csn == 1'b1) begin
+      fmc_spi_counter <= 6'h0;
+      fmc_spi_dev_sel <= 8'h0;
+      fmc_cpld_addr <= 8'h0;
+    end else begin
+      fmc_spi_counter <= fmc_spi_counter + 1;
+      if (fmc_spi_counter <= 7) begin
+        fmc_spi_dev_sel <= {fmc_spi_dev_sel[6:0], fmc_spi_sdio};
+      end
+      if (fmc_spi_counter <= 15) begin
+        fmc_cpld_addr <= {fmc_cpld_addr[6:0], fmc_spi_sdio};
+      end
+    end
+  end
+
+  // chip select control
+
+  assign adc_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9684) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
+  assign dac_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9122) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
+  assign clk_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9523) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
+  assign cpld_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_CPLD) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
+
+  // SPI control and data
+
+  assign sclk = fmc_spi_sclk;
+  assign sdio = fpga_to_cpld ? fmc_spi_sdio : 1'bZ;
+  assign fmc_spi_sdio = fpga_to_cpld ? 1'bZ : cpld_rdata_s;
+  assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
+
+  assign rdnwr = ~fmc_cpld_addr[7];
+
+  always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
+    if (fmc_spi_csn == 1'b1) begin
+      fpga_to_cpld <= 1'b1;
+      fmc_spi_csn_enb <= 1'b1;
+    end else begin
+      fmc_spi_csn_enb <= (fmc_spi_counter <= 7) ? 1'b1 : 1'b0;
+      if (adc_spicsn & clk_spicsn) begin
+        fpga_to_cpld <= (fmc_spi_counter >= 16) ? rdnwr : 1'b1;
+      end else begin
+        fpga_to_cpld <= (fmc_spi_counter >= 24) ? rdnwr : 1'b1;
+      end
+    end
+  end
+
+  // Internal register read access
+
+  always @(fmc_cpld_addr) begin
+    case (fmc_cpld_addr[6:0])
+      ADC_CONTROL_ADDR :
+        cpld_rdata <= adc_pwdn_stby;
+      DAC_CONTROL_ADDR :
+        cpld_rdata <= dac_resetn;
+      CLK_CONTROL_ADDR :
+        cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn};
+      ADC_STATUS_ADDR  :
+        cpld_rdata <= {adc_status_p, adc_fdb, adc_fda};
+      DAC_STATUS_ADDR  :
+        cpld_rdata <= dac_irqn;
+      CLK_STATUS_ADDR  :
+        cpld_rdata <= {clk_status2, clk_status1};
+      default:
+        cpld_rdata <= 8'hFA;
+    endcase
+  end
+
+  always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
+    if (fmc_spi_csn == 1'b1) begin
+      cpld_rdata_bit <= 1'b0;
+      cpld_rdata_index <= 3'h0;
+    end else begin
+      if (fpga_to_cpld == 1'b0) begin
+        cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];
+        cpld_rdata_index <= cpld_rdata_index + 1;
+      end
+    end
+  end
+
+  // Internal register write access
+
+  always @(negedge fmc_spi_sclk) begin
+    if ((fpga_to_cpld == 1'b1) &&
+        (cpld_spicsn == 1'b0) &&
+        (fmc_spi_counter == 8'h18)) begin
+      case (fmc_cpld_addr[6:0])
+        ADC_CONTROL_ADDR :
+          adc_control <= cpld_wdata;
+        DAC_CONTROL_ADDR :
+          dac_control <= cpld_wdata;
+        CLK_CONTROL_ADDR :
+          clk_control <= cpld_wdata;
+      endcase
+    end
+  end
+
+  always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
+    if (fmc_spi_csn == 1'b1) begin
+      cpld_wdata <= 8'h0;
+    end else begin
+      if (fmc_spi_counter >= 16) begin
+        cpld_wdata <= {cpld_wdata[6:0], fmc_spi_sdio};
+      end
+    end
+  end
+
+  // input/output logic
+
+  // AD9648
+
+  assign adc_pwdn_stby = adc_control[0];
+
+  // AD9122
+
+  assign dac_resetn = dac_control[0];
+
+  // AD9523-1
+
+  assign clk_pwdnn = clk_control[0];
+  assign clk_resetn = clk_control[1];
+  assign clk_syncn = clk_control[2];
+
+  assign fmc_irq = dac_irqn;
+
+endmodule
+

From a610ebb41388c67dc26dc8806494111ae598ba44 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Jan 2016 13:53:22 -0500
Subject: [PATCH 041/972] uzed: zed-copy

---
 projects/common/uzed/uzed_system_bd.tcl     | 278 ++++++++++++++++++++
 projects/common/uzed/uzed_system_constr.xdc |  89 +++++++
 projects/common/uzed/uzed_system_ps7.tcl    | 110 ++++++++
 3 files changed, 477 insertions(+)
 create mode 100644 projects/common/uzed/uzed_system_bd.tcl
 create mode 100644 projects/common/uzed/uzed_system_constr.xdc
 create mode 100755 projects/common/uzed/uzed_system_ps7.tcl

diff --git a/projects/common/uzed/uzed_system_bd.tcl b/projects/common/uzed/uzed_system_bd.tcl
new file mode 100644
index 000000000..09bed96d4
--- /dev/null
+++ b/projects/common/uzed/uzed_system_bd.tcl
@@ -0,0 +1,278 @@
+
+# create board design
+# interface ports
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
+create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fmc
+
+create_bd_port -dir O spi0_csn_2_o
+create_bd_port -dir O spi0_csn_1_o
+create_bd_port -dir O spi0_csn_0_o
+create_bd_port -dir I spi0_csn_i
+create_bd_port -dir I spi0_clk_i
+create_bd_port -dir O spi0_clk_o
+create_bd_port -dir I spi0_sdo_i
+create_bd_port -dir O spi0_sdo_o
+create_bd_port -dir I spi0_sdi_i
+
+create_bd_port -dir O spi1_csn_2_o
+create_bd_port -dir O spi1_csn_1_o
+create_bd_port -dir O spi1_csn_0_o
+create_bd_port -dir I spi1_csn_i
+create_bd_port -dir I spi1_clk_i
+create_bd_port -dir O spi1_clk_o
+create_bd_port -dir I spi1_sdo_i
+create_bd_port -dir O spi1_sdo_o
+create_bd_port -dir I spi1_sdi_i
+
+create_bd_port -dir I -from 63 -to 0 gpio_i
+create_bd_port -dir O -from 63 -to 0 gpio_o
+create_bd_port -dir O -from 63 -to 0 gpio_t
+
+# hdmi interface
+
+create_bd_port -dir O hdmi_out_clk
+create_bd_port -dir O hdmi_hsync
+create_bd_port -dir O hdmi_vsync
+create_bd_port -dir O hdmi_data_e
+create_bd_port -dir O -from 15 -to 0 hdmi_data
+
+# i2s
+
+create_bd_port -dir O -type clk i2s_mclk
+create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
+
+# iic mux
+
+create_bd_port -dir I -from 1 -to 0 iic_mux_scl_i
+create_bd_port -dir O -from 1 -to 0 iic_mux_scl_o
+create_bd_port -dir O iic_mux_scl_t
+create_bd_port -dir I -from 1 -to 0 iic_mux_sda_i
+create_bd_port -dir O -from 1 -to 0 iic_mux_sda_o
+create_bd_port -dir O iic_mux_sda_t
+
+create_bd_port -dir I otg_vbusoc
+
+# spdif audio
+
+create_bd_port -dir O spdif
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZedBoard}] $sys_ps7
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true} ] $axi_iic_main
+set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
+
+set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
+set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
+set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
+
+# hdmi peripherals
+
+set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
+set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+
+set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
+set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
+set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
+set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
+
+# audio peripherals
+
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
+set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
+
+set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
+set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
+
+set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
+set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
+set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
+
+# iic (fmc)
+
+set axi_iic_fmc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_fmc]
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+
+# interface connections
+
+ad_connect  ddr           sys_ps7/DDR
+ad_connect  gpio_i        sys_ps7/GPIO_I
+ad_connect  gpio_o        sys_ps7/GPIO_O
+ad_connect  gpio_t        sys_ps7/GPIO_T
+ad_connect  fixed_io      sys_ps7/FIXED_IO
+ad_connect  iic_fmc       axi_iic_fmc/iic
+ad_connect  sys_200m_clk  axi_hdmi_clkgen/clk
+
+ad_connect  axi_iic_main/IIC sys_i2c_mixer/upstream
+
+ad_connect  iic_mux_scl_i   sys_i2c_mixer/downstream_scl_i
+ad_connect  iic_mux_scl_o   sys_i2c_mixer/downstream_scl_o
+ad_connect  iic_mux_scl_t   sys_i2c_mixer/downstream_scl_t
+ad_connect  iic_mux_sda_i   sys_i2c_mixer/downstream_sda_i
+ad_connect  iic_mux_sda_o   sys_i2c_mixer/downstream_sda_o
+ad_connect  iic_mux_sda_t   sys_i2c_mixer/downstream_sda_t
+
+ad_connect  sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
+ad_connect  otg_vbusoc  sys_logic_inv/Op1
+
+# spi connections
+
+ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
+ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
+ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
+ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
+ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
+ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
+ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
+ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
+ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+
+ad_connect  spi1_csn_2_o sys_ps7/SPI1_SS2_O
+ad_connect  spi1_csn_1_o sys_ps7/SPI1_SS1_O
+ad_connect  spi1_csn_0_o sys_ps7/SPI1_SS_O
+ad_connect  spi1_csn_i sys_ps7/SPI1_SS_I
+ad_connect  spi1_clk_i sys_ps7/SPI1_SCLK_I
+ad_connect  spi1_clk_o sys_ps7/SPI1_SCLK_O
+ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
+ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
+ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
+
+# hdmi
+
+ad_connect  sys_cpu_clk axi_hdmi_core/vdma_clk
+ad_connect  sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
+ad_connect  axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
+ad_connect  axi_hdmi_core/hdmi_out_clk hdmi_out_clk
+ad_connect  axi_hdmi_core/hdmi_16_hsync hdmi_hsync
+ad_connect  axi_hdmi_core/hdmi_16_vsync hdmi_vsync
+ad_connect  axi_hdmi_core/hdmi_16_data_e hdmi_data_e
+ad_connect  axi_hdmi_core/hdmi_16_data hdmi_data
+ad_connect  axi_hdmi_core/vdma_valid axi_hdmi_dma/m_axis_mm2s_tvalid
+ad_connect  axi_hdmi_core/vdma_data axi_hdmi_dma/m_axis_mm2s_tdata
+ad_connect  axi_hdmi_core/vdma_ready axi_hdmi_dma/m_axis_mm2s_tready
+ad_connect  axi_hdmi_core/vdma_fs axi_hdmi_dma/mm2s_fsync
+ad_connect  axi_hdmi_core/vdma_fs axi_hdmi_core/vdma_fs_ret
+
+# spdif audio
+
+ad_connect  sys_cpu_clk   axi_spdif_tx_core/DMA_REQ_ACLK
+ad_connect  sys_cpu_clk   sys_ps7/DMA0_ACLK
+
+ad_connect  sys_ps7/DMA0_REQ  axi_spdif_tx_core/DMA_REQ
+ad_connect  sys_ps7/DMA0_ACK  axi_spdif_tx_core/DMA_ACK
+ad_connect  sys_cpu_resetn    axi_spdif_tx_core/DMA_REQ_RSTN
+ad_connect  sys_200m_clk      sys_audio_clkgen/clk_in1
+ad_connect  sys_cpu_resetn    sys_audio_clkgen/resetn
+ad_connect  sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
+ad_connect  spdif             axi_spdif_tx_core/spdif_tx_o
+
+# i2s audio
+
+ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
+ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA1_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA2_ACLK
+
+ad_connect  sys_audio_clkgen/clk_out1   i2s_mclk
+ad_connect  sys_audio_clkgen/clk_out1   axi_i2s_adi/DATA_CLK_I
+
+ad_connect  i2s axi_i2s_adi/I2S
+
+ad_connect  sys_ps7/DMA1_REQ   axi_i2s_adi/DMA_REQ_TX
+ad_connect  sys_ps7/DMA1_ACK   axi_i2s_adi/DMA_ACK_TX
+ad_connect  sys_cpu_resetn     axi_i2s_adi/DMA_REQ_TX_RSTN
+ad_connect  sys_ps7/DMA2_REQ   axi_i2s_adi/DMA_REQ_RX
+ad_connect  sys_ps7/DMA2_ACK   axi_i2s_adi/DMA_ACK_RX
+ad_connect  sys_cpu_resetn     axi_i2s_adi/DMA_REQ_RX_RSTN
+
+# interrupts
+
+ad_connect  sys_concat_intc/dout  sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15  axi_hdmi_dma/mm2s_introut
+ad_connect  sys_concat_intc/In14  axi_iic_main/iic2intc_irpt
+ad_connect  sys_concat_intc/In13  ps_intr_13
+ad_connect  sys_concat_intc/In12  ps_intr_12
+ad_connect  sys_concat_intc/In11  axi_iic_fmc/iic2intc_irpt
+ad_connect  sys_concat_intc/In10  ps_intr_10
+ad_connect  sys_concat_intc/In9   ps_intr_09
+ad_connect  sys_concat_intc/In8   ps_intr_08
+ad_connect  sys_concat_intc/In7   ps_intr_07
+ad_connect  sys_concat_intc/In6   ps_intr_06
+ad_connect  sys_concat_intc/In5   ps_intr_05
+ad_connect  sys_concat_intc/In4   ps_intr_04
+ad_connect  sys_concat_intc/In3   ps_intr_03
+ad_connect  sys_concat_intc/In2   ps_intr_02
+ad_connect  sys_concat_intc/In1   ps_intr_01
+ad_connect  sys_concat_intc/In0   ps_intr_00
+
+# interconnects and address mapping
+
+ad_cpu_interconnect 0x41600000 axi_iic_main
+ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
+ad_cpu_interconnect 0x43000000 axi_hdmi_dma
+ad_cpu_interconnect 0x70e00000 axi_hdmi_core
+ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
+ad_cpu_interconnect 0x77600000 axi_i2s_adi
+ad_cpu_interconnect 0x41620000 axi_iic_fmc
+ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
+ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
+
diff --git a/projects/common/uzed/uzed_system_constr.xdc b/projects/common/uzed/uzed_system_constr.xdc
new file mode 100644
index 000000000..07de0b2fe
--- /dev/null
+++ b/projects/common/uzed/uzed_system_constr.xdc
@@ -0,0 +1,89 @@
+
+# constraints
+# hdmi
+
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS33}           [get_ports hdmi_out_clk]
+set_property  -dict {PACKAGE_PIN  W17   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_vsync]
+set_property  -dict {PACKAGE_PIN  V17   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_hsync]
+set_property  -dict {PACKAGE_PIN  U16   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data_e]
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[0]]
+set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[1]]
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[2]]
+set_property  -dict {PACKAGE_PIN  Y14   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[3]]
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[4]]
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[5]]
+set_property  -dict {PACKAGE_PIN  AA16  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[6]]
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[7]]
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[8]]
+set_property  -dict {PACKAGE_PIN  Y15   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[9]]
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[10]]
+set_property  -dict {PACKAGE_PIN  W15   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[11]]
+set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[12]]
+set_property  -dict {PACKAGE_PIN  U17   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[13]]
+set_property  -dict {PACKAGE_PIN  V14   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[14]]
+set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[15]]
+
+# spdif
+
+set_property  -dict {PACKAGE_PIN  U15   IOSTANDARD LVCMOS33} [get_ports spdif]
+
+# i2s
+
+set_property  -dict {PACKAGE_PIN  AB2   IOSTANDARD LVCMOS33} [get_ports i2s_mclk]
+set_property  -dict {PACKAGE_PIN  AA6   IOSTANDARD LVCMOS33} [get_ports i2s_bclk]
+set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD LVCMOS33} [get_ports i2s_lrclk]
+set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD LVCMOS33} [get_ports i2s_sdata_out]
+set_property  -dict {PACKAGE_PIN  AA7   IOSTANDARD LVCMOS33} [get_ports i2s_sdata_in]
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  R7    IOSTANDARD LVCMOS33} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD LVCMOS33} [get_ports iic_sda]
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[1]]
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[1]]
+set_property  -dict {PACKAGE_PIN  AB4   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[0]]
+set_property  -dict {PACKAGE_PIN  AB5   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[0]]
+
+# otg
+
+set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD LVCMOS25} [get_ports otg_vbusoc]
+
+# gpio (switches, leds and such)
+
+set_property  -dict {PACKAGE_PIN  P16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]       ; ## BTNC
+set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]       ; ## BTND
+set_property  -dict {PACKAGE_PIN  N15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]       ; ## BTNL
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]       ; ## BTNR
+set_property  -dict {PACKAGE_PIN  T18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]       ; ## BTNU
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]]       ; ## OLED-DC
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]]       ; ## OLED-RES
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVCMOS33} [get_ports gpio_bd[7]]       ; ## OLED-SCLK
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS33} [get_ports gpio_bd[8]]       ; ## OLED-SDIN
+set_property  -dict {PACKAGE_PIN  U11   IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]]       ; ## OLED-VBAT
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]]      ; ## OLED-VDD
+
+set_property  -dict {PACKAGE_PIN  F22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]      ; ## SW0
+set_property  -dict {PACKAGE_PIN  G22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]]      ; ## SW1
+set_property  -dict {PACKAGE_PIN  H22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]]      ; ## SW2
+set_property  -dict {PACKAGE_PIN  F21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]]      ; ## SW3
+set_property  -dict {PACKAGE_PIN  H19   IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]]      ; ## SW4
+set_property  -dict {PACKAGE_PIN  H18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]]      ; ## SW5
+set_property  -dict {PACKAGE_PIN  H17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]]      ; ## SW6
+set_property  -dict {PACKAGE_PIN  M15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]]      ; ## SW7
+
+set_property  -dict {PACKAGE_PIN  T22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[19]]      ; ## LD0
+set_property  -dict {PACKAGE_PIN  T21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[20]]      ; ## LD1
+set_property  -dict {PACKAGE_PIN  U22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[21]]      ; ## LD2
+set_property  -dict {PACKAGE_PIN  U21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[22]]      ; ## LD3
+set_property  -dict {PACKAGE_PIN  V22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[23]]      ; ## LD4
+set_property  -dict {PACKAGE_PIN  W22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[24]]      ; ## LD5
+set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD LVCMOS33} [get_ports gpio_bd[25]]      ; ## LD6
+set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD LVCMOS33} [get_ports gpio_bd[26]]      ; ## LD7
+
+set_property  -dict {PACKAGE_PIN  H15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[27]]      ; ## XADC-GIO0
+set_property  -dict {PACKAGE_PIN  R15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[28]]      ; ## XADC-GIO1
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[29]]      ; ## XADC-GIO2
+set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[30]]      ; ## XADC-GIO3
+
+set_property  -dict {PACKAGE_PIN  G17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[31]]      ; ## OTG-RESETN
+
diff --git a/projects/common/uzed/uzed_system_ps7.tcl b/projects/common/uzed/uzed_system_ps7.tcl
new file mode 100755
index 000000000..770cd0199
--- /dev/null
+++ b/projects/common/uzed/uzed_system_ps7.tcl
@@ -0,0 +1,110 @@
+
+set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE                      {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_ENET0_IO                            {MIO 16 .. 27}          [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE                     {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_GRP_MDIO_IO                         {MIO 52 .. 53}          [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_RESET_ENABLE                        {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_RESET_IO                            {MIO 47}                [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USB0_RESET_ENABLE                         {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USB0_RESET_IO                             {MIO 7}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_I2C0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_I2C0_I2C0_IO                              {MIO 50 .. 51}          [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_I2C0_RESET_ENABLE                         {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_I2C0_RESET_IO                             {MIO 46}                [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE                     {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SD0_GRP_CD_ENABLE                         {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SD0_GRP_CD_IO                             {MIO 14}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SD0_GRP_WP_ENABLE                         {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ                   {50}                    [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UART_PERIPHERAL_FREQMHZ                   {50}                    [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE                 {0}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_QSPI_GRP_IO1_ENABLE                       {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE                     {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_TTC0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_UIPARAM_DDR_PARTNO                        {Custom}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH                     {32 Bit}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF             {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH                    {16 Bits}               [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY               {4096 MBits}            [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_SPEED_BIN                     {DDR3_1066F}            [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT                {10}                    [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_CL                            {7}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_CWL                           {5}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_T_RCD                         {7}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_T_RP                          {7}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_T_RC                          {49.5}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN                     {36.0}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_T_FAW                         {45.0}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL             {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE               {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE                {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {0.078}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {0.074}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {-0.059}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {-0.055}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.482}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.484}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.417}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.416}                 [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_MIO_16_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_16_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_17_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_17_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_18_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_18_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_19_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_19_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_20_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_20_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_21_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_21_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_22_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_22_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_23_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_23_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_24_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_24_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_25_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_25_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_26_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_26_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_27_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_27_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_MIO_28_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_29_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_30_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_31_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_32_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_33_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_34_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_35_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_36_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_37_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_38_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_39_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_40_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_41_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_42_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_43_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_44_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_45_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_48_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_49_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_52_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_53_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+
+

From c3977870012b3207cf2dd63c7ebb60bc2a9e9ace Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Jan 2016 15:36:01 -0500
Subject: [PATCH 042/972] uzed: updates

---
 projects/common/uzed/uzed_system_bd.tcl     | 206 +-------------------
 projects/common/uzed/uzed_system_constr.xdc |  86 --------
 projects/common/uzed/uzed_system_ps7.tcl    | 125 +++++++-----
 3 files changed, 81 insertions(+), 336 deletions(-)

diff --git a/projects/common/uzed/uzed_system_bd.tcl b/projects/common/uzed/uzed_system_bd.tcl
index 09bed96d4..4d6212336 100644
--- a/projects/common/uzed/uzed_system_bd.tcl
+++ b/projects/common/uzed/uzed_system_bd.tcl
@@ -4,7 +4,6 @@
 
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
 create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fmc
 
 create_bd_port -dir O spi0_csn_2_o
 create_bd_port -dir O spi0_csn_1_o
@@ -30,128 +29,18 @@ create_bd_port -dir I -from 63 -to 0 gpio_i
 create_bd_port -dir O -from 63 -to 0 gpio_o
 create_bd_port -dir O -from 63 -to 0 gpio_t
 
-# hdmi interface
-
-create_bd_port -dir O hdmi_out_clk
-create_bd_port -dir O hdmi_hsync
-create_bd_port -dir O hdmi_vsync
-create_bd_port -dir O hdmi_data_e
-create_bd_port -dir O -from 15 -to 0 hdmi_data
-
-# i2s
-
-create_bd_port -dir O -type clk i2s_mclk
-create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
-
-# iic mux
-
-create_bd_port -dir I -from 1 -to 0 iic_mux_scl_i
-create_bd_port -dir O -from 1 -to 0 iic_mux_scl_o
-create_bd_port -dir O iic_mux_scl_t
-create_bd_port -dir I -from 1 -to 0 iic_mux_sda_i
-create_bd_port -dir O -from 1 -to 0 iic_mux_sda_o
-create_bd_port -dir O iic_mux_sda_t
-
-create_bd_port -dir I otg_vbusoc
-
-# spdif audio
-
-create_bd_port -dir O spdif
-
-# interrupts
-
-create_bd_port -dir I -type intr ps_intr_00
-create_bd_port -dir I -type intr ps_intr_01
-create_bd_port -dir I -type intr ps_intr_02
-create_bd_port -dir I -type intr ps_intr_03
-create_bd_port -dir I -type intr ps_intr_04
-create_bd_port -dir I -type intr ps_intr_05
-create_bd_port -dir I -type intr ps_intr_06
-create_bd_port -dir I -type intr ps_intr_07
-create_bd_port -dir I -type intr ps_intr_08
-create_bd_port -dir I -type intr ps_intr_09
-create_bd_port -dir I -type intr ps_intr_10
-create_bd_port -dir I -type intr ps_intr_12
-create_bd_port -dir I -type intr ps_intr_13
-
 # instance: sys_ps7
 
 set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
-set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZedBoard}] $sys_ps7
+source $ad_hdl_dir/projects/common/uzed/uzed_system_ps7.tcl
 set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
 
-set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true} ] $axi_iic_main
-set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
-
-set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]
-
-set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
-set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
-
-set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
-set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
-
-set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
-set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
-set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
-
-# hdmi peripherals
-
-set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
-set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
-
-set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
-set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
-set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
-set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
-
-# audio peripherals
-
-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
-set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
-set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
-set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
-set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
-
-set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
-set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
-set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
-
-set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
-set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
-set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
-
-# iic (fmc)
-
-set axi_iic_fmc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_fmc]
-
-# system reset/clock definitions
-
-ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
-ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
-ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
-ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
-ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
-ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
-
 # interface connections
 
 ad_connect  ddr           sys_ps7/DDR
@@ -159,20 +48,6 @@ ad_connect  gpio_i        sys_ps7/GPIO_I
 ad_connect  gpio_o        sys_ps7/GPIO_O
 ad_connect  gpio_t        sys_ps7/GPIO_T
 ad_connect  fixed_io      sys_ps7/FIXED_IO
-ad_connect  iic_fmc       axi_iic_fmc/iic
-ad_connect  sys_200m_clk  axi_hdmi_clkgen/clk
-
-ad_connect  axi_iic_main/IIC sys_i2c_mixer/upstream
-
-ad_connect  iic_mux_scl_i   sys_i2c_mixer/downstream_scl_i
-ad_connect  iic_mux_scl_o   sys_i2c_mixer/downstream_scl_o
-ad_connect  iic_mux_scl_t   sys_i2c_mixer/downstream_scl_t
-ad_connect  iic_mux_sda_i   sys_i2c_mixer/downstream_sda_i
-ad_connect  iic_mux_sda_o   sys_i2c_mixer/downstream_sda_o
-ad_connect  iic_mux_sda_t   sys_i2c_mixer/downstream_sda_t
-
-ad_connect  sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
-ad_connect  otg_vbusoc  sys_logic_inv/Op1
 
 # spi connections
 
@@ -196,83 +71,4 @@ ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
 ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
 ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
 
-# hdmi
-
-ad_connect  sys_cpu_clk axi_hdmi_core/vdma_clk
-ad_connect  sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
-ad_connect  axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
-ad_connect  axi_hdmi_core/hdmi_out_clk hdmi_out_clk
-ad_connect  axi_hdmi_core/hdmi_16_hsync hdmi_hsync
-ad_connect  axi_hdmi_core/hdmi_16_vsync hdmi_vsync
-ad_connect  axi_hdmi_core/hdmi_16_data_e hdmi_data_e
-ad_connect  axi_hdmi_core/hdmi_16_data hdmi_data
-ad_connect  axi_hdmi_core/vdma_valid axi_hdmi_dma/m_axis_mm2s_tvalid
-ad_connect  axi_hdmi_core/vdma_data axi_hdmi_dma/m_axis_mm2s_tdata
-ad_connect  axi_hdmi_core/vdma_ready axi_hdmi_dma/m_axis_mm2s_tready
-ad_connect  axi_hdmi_core/vdma_fs axi_hdmi_dma/mm2s_fsync
-ad_connect  axi_hdmi_core/vdma_fs axi_hdmi_core/vdma_fs_ret
-
-# spdif audio
-
-ad_connect  sys_cpu_clk   axi_spdif_tx_core/DMA_REQ_ACLK
-ad_connect  sys_cpu_clk   sys_ps7/DMA0_ACLK
-
-ad_connect  sys_ps7/DMA0_REQ  axi_spdif_tx_core/DMA_REQ
-ad_connect  sys_ps7/DMA0_ACK  axi_spdif_tx_core/DMA_ACK
-ad_connect  sys_cpu_resetn    axi_spdif_tx_core/DMA_REQ_RSTN
-ad_connect  sys_200m_clk      sys_audio_clkgen/clk_in1
-ad_connect  sys_cpu_resetn    sys_audio_clkgen/resetn
-ad_connect  sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
-ad_connect  spdif             axi_spdif_tx_core/spdif_tx_o
-
-# i2s audio
-
-ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
-ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
-ad_connect  sys_cpu_clk sys_ps7/DMA1_ACLK
-ad_connect  sys_cpu_clk sys_ps7/DMA2_ACLK
-
-ad_connect  sys_audio_clkgen/clk_out1   i2s_mclk
-ad_connect  sys_audio_clkgen/clk_out1   axi_i2s_adi/DATA_CLK_I
-
-ad_connect  i2s axi_i2s_adi/I2S
-
-ad_connect  sys_ps7/DMA1_REQ   axi_i2s_adi/DMA_REQ_TX
-ad_connect  sys_ps7/DMA1_ACK   axi_i2s_adi/DMA_ACK_TX
-ad_connect  sys_cpu_resetn     axi_i2s_adi/DMA_REQ_TX_RSTN
-ad_connect  sys_ps7/DMA2_REQ   axi_i2s_adi/DMA_REQ_RX
-ad_connect  sys_ps7/DMA2_ACK   axi_i2s_adi/DMA_ACK_RX
-ad_connect  sys_cpu_resetn     axi_i2s_adi/DMA_REQ_RX_RSTN
-
-# interrupts
-
-ad_connect  sys_concat_intc/dout  sys_ps7/IRQ_F2P
-ad_connect  sys_concat_intc/In15  axi_hdmi_dma/mm2s_introut
-ad_connect  sys_concat_intc/In14  axi_iic_main/iic2intc_irpt
-ad_connect  sys_concat_intc/In13  ps_intr_13
-ad_connect  sys_concat_intc/In12  ps_intr_12
-ad_connect  sys_concat_intc/In11  axi_iic_fmc/iic2intc_irpt
-ad_connect  sys_concat_intc/In10  ps_intr_10
-ad_connect  sys_concat_intc/In9   ps_intr_09
-ad_connect  sys_concat_intc/In8   ps_intr_08
-ad_connect  sys_concat_intc/In7   ps_intr_07
-ad_connect  sys_concat_intc/In6   ps_intr_06
-ad_connect  sys_concat_intc/In5   ps_intr_05
-ad_connect  sys_concat_intc/In4   ps_intr_04
-ad_connect  sys_concat_intc/In3   ps_intr_03
-ad_connect  sys_concat_intc/In2   ps_intr_02
-ad_connect  sys_concat_intc/In1   ps_intr_01
-ad_connect  sys_concat_intc/In0   ps_intr_00
-
-# interconnects and address mapping
-
-ad_cpu_interconnect 0x41600000 axi_iic_main
-ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
-ad_cpu_interconnect 0x43000000 axi_hdmi_dma
-ad_cpu_interconnect 0x70e00000 axi_hdmi_core
-ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
-ad_cpu_interconnect 0x77600000 axi_i2s_adi
-ad_cpu_interconnect 0x41620000 axi_iic_fmc
-ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
-ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
 
diff --git a/projects/common/uzed/uzed_system_constr.xdc b/projects/common/uzed/uzed_system_constr.xdc
index 07de0b2fe..1f118304a 100644
--- a/projects/common/uzed/uzed_system_constr.xdc
+++ b/projects/common/uzed/uzed_system_constr.xdc
@@ -1,89 +1,3 @@
 
 # constraints
-# hdmi
-
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS33}           [get_ports hdmi_out_clk]
-set_property  -dict {PACKAGE_PIN  W17   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_vsync]
-set_property  -dict {PACKAGE_PIN  V17   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_hsync]
-set_property  -dict {PACKAGE_PIN  U16   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data_e]
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[0]]
-set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[1]]
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[2]]
-set_property  -dict {PACKAGE_PIN  Y14   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[3]]
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[4]]
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[5]]
-set_property  -dict {PACKAGE_PIN  AA16  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[6]]
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[7]]
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[8]]
-set_property  -dict {PACKAGE_PIN  Y15   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[9]]
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[10]]
-set_property  -dict {PACKAGE_PIN  W15   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[11]]
-set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[12]]
-set_property  -dict {PACKAGE_PIN  U17   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[13]]
-set_property  -dict {PACKAGE_PIN  V14   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[14]]
-set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD LVCMOS33  IOB TRUE} [get_ports hdmi_data[15]]
-
-# spdif
-
-set_property  -dict {PACKAGE_PIN  U15   IOSTANDARD LVCMOS33} [get_ports spdif]
-
-# i2s
-
-set_property  -dict {PACKAGE_PIN  AB2   IOSTANDARD LVCMOS33} [get_ports i2s_mclk]
-set_property  -dict {PACKAGE_PIN  AA6   IOSTANDARD LVCMOS33} [get_ports i2s_bclk]
-set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD LVCMOS33} [get_ports i2s_lrclk]
-set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD LVCMOS33} [get_ports i2s_sdata_out]
-set_property  -dict {PACKAGE_PIN  AA7   IOSTANDARD LVCMOS33} [get_ports i2s_sdata_in]
-
-# iic
-
-set_property  -dict {PACKAGE_PIN  R7    IOSTANDARD LVCMOS33} [get_ports iic_scl]
-set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD LVCMOS33} [get_ports iic_sda]
-set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[1]]
-set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[1]]
-set_property  -dict {PACKAGE_PIN  AB4   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[0]]
-set_property  -dict {PACKAGE_PIN  AB5   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[0]]
-
-# otg
-
-set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD LVCMOS25} [get_ports otg_vbusoc]
-
-# gpio (switches, leds and such)
-
-set_property  -dict {PACKAGE_PIN  P16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]       ; ## BTNC
-set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]       ; ## BTND
-set_property  -dict {PACKAGE_PIN  N15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]       ; ## BTNL
-set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]       ; ## BTNR
-set_property  -dict {PACKAGE_PIN  T18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]       ; ## BTNU
-set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]]       ; ## OLED-DC
-set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]]       ; ## OLED-RES
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVCMOS33} [get_ports gpio_bd[7]]       ; ## OLED-SCLK
-set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS33} [get_ports gpio_bd[8]]       ; ## OLED-SDIN
-set_property  -dict {PACKAGE_PIN  U11   IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]]       ; ## OLED-VBAT
-set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]]      ; ## OLED-VDD
-
-set_property  -dict {PACKAGE_PIN  F22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]      ; ## SW0
-set_property  -dict {PACKAGE_PIN  G22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]]      ; ## SW1
-set_property  -dict {PACKAGE_PIN  H22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]]      ; ## SW2
-set_property  -dict {PACKAGE_PIN  F21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]]      ; ## SW3
-set_property  -dict {PACKAGE_PIN  H19   IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]]      ; ## SW4
-set_property  -dict {PACKAGE_PIN  H18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]]      ; ## SW5
-set_property  -dict {PACKAGE_PIN  H17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]]      ; ## SW6
-set_property  -dict {PACKAGE_PIN  M15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]]      ; ## SW7
-
-set_property  -dict {PACKAGE_PIN  T22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[19]]      ; ## LD0
-set_property  -dict {PACKAGE_PIN  T21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[20]]      ; ## LD1
-set_property  -dict {PACKAGE_PIN  U22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[21]]      ; ## LD2
-set_property  -dict {PACKAGE_PIN  U21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[22]]      ; ## LD3
-set_property  -dict {PACKAGE_PIN  V22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[23]]      ; ## LD4
-set_property  -dict {PACKAGE_PIN  W22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[24]]      ; ## LD5
-set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD LVCMOS33} [get_ports gpio_bd[25]]      ; ## LD6
-set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD LVCMOS33} [get_ports gpio_bd[26]]      ; ## LD7
-
-set_property  -dict {PACKAGE_PIN  H15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[27]]      ; ## XADC-GIO0
-set_property  -dict {PACKAGE_PIN  R15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[28]]      ; ## XADC-GIO1
-set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[29]]      ; ## XADC-GIO2
-set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[30]]      ; ## XADC-GIO3
-
-set_property  -dict {PACKAGE_PIN  G17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[31]]      ; ## OTG-RESETN
 
diff --git a/projects/common/uzed/uzed_system_ps7.tcl b/projects/common/uzed/uzed_system_ps7.tcl
index 770cd0199..9aac962c6 100755
--- a/projects/common/uzed/uzed_system_ps7.tcl
+++ b/projects/common/uzed/uzed_system_ps7.tcl
@@ -1,5 +1,5 @@
 
-set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE                      {LVCMOS 3.3V}           [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
 
 set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE                      {1}                     [get_bd_cells sys_ps7]
@@ -7,83 +7,61 @@ set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE                   {1}
 set_property CONFIG.PCW_ENET0_ENET0_IO                            {MIO 16 .. 27}          [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE                     {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_ENET0_GRP_MDIO_IO                         {MIO 52 .. 53}          [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_RESET_ENABLE                        {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_RESET_IO                            {MIO 47}                [get_bd_cells sys_ps7]
 
 set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_USB0_RESET_ENABLE                         {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_USB0_RESET_IO                             {MIO 7}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_I2C0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_I2C0_I2C0_IO                              {MIO 50 .. 51}          [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_I2C0_RESET_ENABLE                         {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_I2C0_RESET_IO                             {MIO 46}                [get_bd_cells sys_ps7]
 
 set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE                     {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_SD0_GRP_CD_ENABLE                         {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_SD0_GRP_CD_IO                             {MIO 14}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SD0_GRP_CD_IO                             {MIO 46}                [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_SD0_GRP_WP_ENABLE                         {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SD0_GRP_WP_IO                             {MIO 50}                [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ                   {50}                    [get_bd_cells sys_ps7]
 
 set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UART_PERIPHERAL_FREQMHZ                   {50}                    [get_bd_cells sys_ps7]
 
 set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE                 {0}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_QSPI_GRP_IO1_ENABLE                       {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE                 {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE                     {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_TTC0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
 
-set_property CONFIG.PCW_UIPARAM_DDR_PARTNO                        {Custom}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH                     {32 Bit}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_PARTNO                        {MT41K256M16 RE-125}    [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF             {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH                    {16 Bits}               [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY               {4096 MBits}            [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_SPEED_BIN                     {DDR3_1066F}            [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT                {10}                    [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_CL                            {7}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_CWL                           {5}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_T_RCD                         {7}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_T_RP                          {7}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_T_RC                          {49.5}                  [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN                     {36.0}                  [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_T_FAW                         {45.0}                  [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL             {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE               {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE                {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {0.078}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {0.074}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {-0.059}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {-0.055}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.482}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.484}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.417}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.416}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {-0.073}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {-0.072}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {0.024}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {0.023}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.294}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.298}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.338}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.334}                 [get_bd_cells sys_ps7]
 
-set_property CONFIG.PCW_MIO_16_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_0_PULLUP                              {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_1_PULLUP                              {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_9_PULLUP                              {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_10_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_11_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_12_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_13_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_14_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_15_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_16_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_17_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_17_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_18_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_18_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_19_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_19_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_20_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_20_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_21_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_21_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_22_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_22_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_23_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_23_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_24_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_24_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_25_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_25_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_26_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_26_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_MIO_27_IOTYPE                             {HSTL 1.8V}             [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_27_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-
 set_property CONFIG.PCW_MIO_28_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_29_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_30_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
@@ -102,9 +80,66 @@ set_property CONFIG.PCW_MIO_42_PULLUP                             {disabled}
 set_property CONFIG.PCW_MIO_43_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_44_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_45_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_46_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_47_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_48_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_49_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_50_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_51_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_52_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_MIO_53_PULLUP                             {disabled}              [get_bd_cells sys_ps7]
-
+set_property CONFIG.PCW_MIO_0_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_1_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_2_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_3_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_4_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_5_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_6_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_7_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_8_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_9_SLEW                                {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_10_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_11_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_12_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_13_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_14_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_15_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_16_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_17_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_18_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_19_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_20_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_21_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_22_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_23_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_24_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_25_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_26_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_27_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_28_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_29_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_30_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_31_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_32_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_33_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_34_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_35_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_36_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_37_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_38_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_39_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_40_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_41_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_42_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_43_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_44_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_45_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_46_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_47_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_48_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_49_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_50_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_51_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_52_SLEW                               {slow}                  [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_MIO_53_SLEW                               {slow}                  [get_bd_cells sys_ps7]
 

From 2dcd9136aacb7b60330bcd9d529723cbfb448b53 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Wed, 13 Jan 2016 10:20:18 +0200
Subject: [PATCH 043/972] axi_ad6676: Delete confusing comment

---
 library/axi_ad6676/axi_ad6676_if.v | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/axi_ad6676/axi_ad6676_if.v b/library/axi_ad6676/axi_ad6676_if.v
index dff2757fe..b0ddedbb1 100755
--- a/library/axi_ad6676/axi_ad6676_if.v
+++ b/library/axi_ad6676/axi_ad6676_if.v
@@ -36,7 +36,6 @@
 // ***************************************************************************
 // ***************************************************************************
 // ***************************************************************************
-// This is the LVDS/DDR interface
 
 `timescale 1ns/100ps
 

From 838b55817672ccfc1b1b14c034a7832b6c174ecd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Wed, 13 Jan 2016 12:21:42 +0200
Subject: [PATCH 044/972] axi_ad9434: Fix adc_status

adc_status was not driven by anything. Should be driven by adc_status_m1.
---
 library/axi_ad9434/axi_ad9434_if.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v
index ccfa4b86e..3475665af 100644
--- a/library/axi_ad9434/axi_ad9434_if.v
+++ b/library/axi_ad9434/axi_ad9434_if.v
@@ -242,6 +242,7 @@ module axi_ad9434_if (
       adc_status <= 1'b0;
     end else begin
       adc_status_m1 <= up_drp_locked & delay_locked;
+      adc_status <= adc_status_m1;
     end
   end
 

From 4f2b999999515414cd006f7c7d8e5364ff365968 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Wed, 13 Jan 2016 16:26:22 +0200
Subject: [PATCH 045/972] axi_ad9680: Q_OR_I_N is not used in this channel

---
 library/axi_ad9680/axi_ad9680_channel.v | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/axi_ad9680/axi_ad9680_channel.v b/library/axi_ad9680/axi_ad9680_channel.v
index 0192f7e61..de0b8094a 100644
--- a/library/axi_ad9680/axi_ad9680_channel.v
+++ b/library/axi_ad9680/axi_ad9680_channel.v
@@ -72,7 +72,6 @@ module axi_ad9680_channel (
 
   // parameters
 
-  parameter Q_OR_I_N = 0;
   parameter CHANNEL_ID = 0;
 
   // adc interface

From 426490c394c5a2516bb9b65abb48f7bbc81eb98c Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Wed, 13 Jan 2016 20:18:09 +0100
Subject: [PATCH 046/972] common: Rename uzed to microzed

Everybody calls the MicroZed microzed in their projects. Don't deviate from
that to avoid potential confusion.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 .../uzed_system_bd.tcl => microzed/microzed_system_bd.tcl}      | 2 +-
 .../microzed_system_constr.xdc}                                 | 0
 .../uzed_system_ps7.tcl => microzed/microzed_system_ps7.tcl}    | 0
 3 files changed, 1 insertion(+), 1 deletion(-)
 rename projects/common/{uzed/uzed_system_bd.tcl => microzed/microzed_system_bd.tcl} (97%)
 rename projects/common/{uzed/uzed_system_constr.xdc => microzed/microzed_system_constr.xdc} (100%)
 rename projects/common/{uzed/uzed_system_ps7.tcl => microzed/microzed_system_ps7.tcl} (100%)

diff --git a/projects/common/uzed/uzed_system_bd.tcl b/projects/common/microzed/microzed_system_bd.tcl
similarity index 97%
rename from projects/common/uzed/uzed_system_bd.tcl
rename to projects/common/microzed/microzed_system_bd.tcl
index 4d6212336..304e9b23f 100644
--- a/projects/common/uzed/uzed_system_bd.tcl
+++ b/projects/common/microzed/microzed_system_bd.tcl
@@ -32,7 +32,7 @@ create_bd_port -dir O -from 63 -to 0 gpio_t
 # instance: sys_ps7
 
 set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
-source $ad_hdl_dir/projects/common/uzed/uzed_system_ps7.tcl
+source $ad_hdl_dir/projects/common/microzed/microzed_system_ps7.tcl
 set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
diff --git a/projects/common/uzed/uzed_system_constr.xdc b/projects/common/microzed/microzed_system_constr.xdc
similarity index 100%
rename from projects/common/uzed/uzed_system_constr.xdc
rename to projects/common/microzed/microzed_system_constr.xdc
diff --git a/projects/common/uzed/uzed_system_ps7.tcl b/projects/common/microzed/microzed_system_ps7.tcl
similarity index 100%
rename from projects/common/uzed/uzed_system_ps7.tcl
rename to projects/common/microzed/microzed_system_ps7.tcl

From 51d20b1a6158ad00ee9b7acb1d133313ad96e12a Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Wed, 13 Jan 2016 20:07:38 +0100
Subject: [PATCH 047/972] adi_project.tcl: Add MicroZed support

Handle the projects for the MicroZed and set up the FPGA part accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/scripts/adi_project.tcl | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index 92d64577a..dbe5a5403 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -55,6 +55,11 @@ proc adi_project_create {project_name {mode 0}} {
     set p_board "em.avnet.com:zed:part0:1.3"
     set sys_zynq 1
   }
+  if [regexp "_microzed$" $project_name] {
+    set p_device "xc7z010clg400-1"
+    set p_board "not-applicable"
+    set sys_zynq 1
+  }
   if [regexp "_zc702$" $project_name] {
     set p_device "xc7z020clg484-1"
     set p_board "xilinx.com:zc702:part0:1.2"

From d2b26720e60a6e65cb41f929550365d46040ce03 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Wed, 13 Jan 2016 20:09:35 +0100
Subject: [PATCH 048/972] common: microzed: Add clock, reset and interrupt
 support

In order for the base project to be usable by other projects it needs to
create the clock, reset and interrupt signals that are expected to exist.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 .../common/microzed/microzed_system_bd.tcl    | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/projects/common/microzed/microzed_system_bd.tcl b/projects/common/microzed/microzed_system_bd.tcl
index 304e9b23f..f0d3eb673 100644
--- a/projects/common/microzed/microzed_system_bd.tcl
+++ b/projects/common/microzed/microzed_system_bd.tcl
@@ -40,6 +40,43 @@ set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_11
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+create_bd_port -dir I -type intr ps_intr_14
+create_bd_port -dir I -type intr ps_intr_15
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
 
 # interface connections
 
@@ -71,4 +108,22 @@ ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
 ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
 ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
 
+# interrupts
 
+ad_connect  sys_concat_intc/dout  sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15  ps_intr_15
+ad_connect  sys_concat_intc/In14  ps_intr_14
+ad_connect  sys_concat_intc/In13  ps_intr_13
+ad_connect  sys_concat_intc/In12  ps_intr_12
+ad_connect  sys_concat_intc/In11  ps_intr_11
+ad_connect  sys_concat_intc/In10  ps_intr_10
+ad_connect  sys_concat_intc/In9   ps_intr_09
+ad_connect  sys_concat_intc/In8   ps_intr_08
+ad_connect  sys_concat_intc/In7   ps_intr_07
+ad_connect  sys_concat_intc/In6   ps_intr_06
+ad_connect  sys_concat_intc/In5   ps_intr_05
+ad_connect  sys_concat_intc/In4   ps_intr_04
+ad_connect  sys_concat_intc/In3   ps_intr_03
+ad_connect  sys_concat_intc/In2   ps_intr_02
+ad_connect  sys_concat_intc/In1   ps_intr_01
+ad_connect  sys_concat_intc/In0   ps_intr_00

From 514eb688764415a32eeef11f4d93e11fc10bb8ce Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Wed, 13 Jan 2016 20:13:28 +0100
Subject: [PATCH 049/972] cn0363: Factor out common parts

Factor out the common parts of the cn0363 design so we can use it to add
support for other carriers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/cn0363/common/cn0363_bd.tcl          | 294 ++++++++++++++++++
 .../cn0363/{zed => common}/filters/hpf.mat    |   0
 .../cn0363/{zed => common}/filters/lpf.mat    |   0
 projects/cn0363/zed/system_bd.tcl             | 290 +----------------
 4 files changed, 295 insertions(+), 289 deletions(-)
 create mode 100644 projects/cn0363/common/cn0363_bd.tcl
 rename projects/cn0363/{zed => common}/filters/hpf.mat (100%)
 rename projects/cn0363/{zed => common}/filters/lpf.mat (100%)

diff --git a/projects/cn0363/common/cn0363_bd.tcl b/projects/cn0363/common/cn0363_bd.tcl
new file mode 100644
index 000000000..ac70789a5
--- /dev/null
+++ b/projects/cn0363/common/cn0363_bd.tcl
@@ -0,0 +1,294 @@
+proc load_fir_filter_vector {filter_file} {
+	set fp [open $filter_file r]
+	set data [split [read $fp] "\n"]
+	set filter ""
+	close $fp
+	foreach line $data {
+		set line [string trim $line]
+		if {[string equal -length 1 $line "#"] || $line eq ""} {
+			continue
+		}
+		if {$filter ne ""} {
+			append filter ","
+		}
+		append filter $line
+	}
+
+	return $filter
+}
+
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7
+
+set_property LEFT 34 [get_bd_ports GPIO_I]
+set_property LEFT 34 [get_bd_ports GPIO_O]
+set_property LEFT 34 [get_bd_ports GPIO_T]
+
+set axi_dma  [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_dma]
+set_property -dict [list \
+		CONFIG.FIFO_SIZE 2 \
+		CONFIG.DMA_TYPE_SRC 2 \
+		CONFIG.DMA_TYPE_DEST 0 \
+		CONFIG.CYCLIC 0 \
+		CONFIG.SYNC_TRANSFER_START 1 \
+		CONFIG.AXI_SLICE_SRC 0 \
+		CONFIG.AXI_SLICE_DEST 0 \
+		CONFIG.DMA_2D_TRANSFER 0 \
+		CONFIG.DMA_DATA_WIDTH_SRC 32 \
+		CONFIG.DMA_DATA_WIDTH_DEST 64 \
+		CONFIG.DMA_AXI_PROTOCOL_DEST 1 \
+	] $axi_dma
+
+# Create SPI engine controller with offload
+create_bd_cell -type hier spi
+current_bd_instance /spi
+
+	create_bd_pin -dir I -type clk clk
+	create_bd_pin -dir I -type rst resetn
+	create_bd_pin -dir O conv_done
+	create_bd_pin -dir O irq
+	create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
+	create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
+
+	set spi_engine [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 execution]
+	set axi_spi_engine [create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi]
+	set spi_engine_offload [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_offload:1.0 offload]
+	set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect]
+	set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi]
+
+	set_property -dict [list CONFIG.NUM_OF_CS 2] $spi_engine
+
+	set_property -dict [list CONFIG.NUM_OF_CS 2] $util_sigma_delta_spi
+
+	ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
+	ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
+	ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
+	ad_connect interconnect/m_ctrl execution/ctrl
+	ad_connect offload/offload_sdi M_AXIS_SAMPLE
+
+	ad_connect util_sigma_delta_spi/data_ready offload/trigger
+	ad_connect util_sigma_delta_spi/data_ready conv_done
+
+	ad_connect execution/active util_sigma_delta_spi/spi_active
+	ad_connect execution/spi util_sigma_delta_spi/s_spi
+	ad_connect util_sigma_delta_spi/m_spi m_spi
+
+	connect_bd_net \
+		[get_bd_pins clk] \
+		[get_bd_pins offload/spi_clk] \
+		[get_bd_pins offload/ctrl_clk] \
+		[get_bd_pins execution/clk] \
+		[get_bd_pins axi/s_axi_aclk] \
+		[get_bd_pins axi/spi_clk] \
+		[get_bd_pins interconnect/clk] \
+		[get_bd_pins util_sigma_delta_spi/clk]
+
+	connect_bd_net \
+		[get_bd_pins axi/spi_resetn] \
+		[get_bd_pins offload/spi_resetn] \
+		[get_bd_pins execution/resetn] \
+		[get_bd_pins interconnect/resetn] \
+		[get_bd_pins util_sigma_delta_spi/resetn]
+
+	connect_bd_net [get_bd_pins resetn] [get_bd_pins axi/s_axi_aresetn]
+	ad_connect irq axi/irq
+
+current_bd_instance /
+
+create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
+ad_connect spi/m_spi spi
+
+set phase_gen [create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 phase_gen]
+set phase_slice [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 phase_slice]
+create_bd_port -dir O excitation
+
+set excitation_freq 1020
+
+set_property -dict [list \
+		CONFIG.Output_Width 32 \
+		CONFIG.Increment_Value [format "%x" [expr $excitation_freq * (1<<32) / 100000000]] \
+	] $phase_gen
+
+set_property -dict [list \
+		CONFIG.DIN_TO {31} \
+		CONFIG.DIN_FROM {31} \
+		CONFIG.DOUT_WIDTH {1} \
+	] $phase_slice
+
+ad_connect /phase_gen/Q /phase_slice/Din
+ad_connect /phase_slice/Dout excitation
+
+create_bd_cell -type hier processing
+current_bd_instance /processing
+
+	create_bd_pin -dir I -type clk clk
+	create_bd_pin -dir I -type rst resetn
+	create_bd_pin -dir I conv_done
+	create_bd_pin -dir I -from 31 -to 0 phase
+	create_bd_pin -dir O overflow
+	create_bd_pin -dir I -from 13 -to 0 channel_enable
+	create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SAMPLE
+	create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR
+
+	create_bd_cell -type ip -vlnv analog.com:user:cn0363_phase_data_sync:1.0 phase_data_sync
+	create_bd_cell -type ip -vlnv analog.com:user:cn0363_dma_sequencer:1.0 sequencer
+	create_bd_cell -type ip -vlnv analog.com:user:cordic_demod:1.0 cordic_demod
+
+	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 phase_broadcast
+	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_broadcast
+	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_filtered_broadcast
+	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 i_q_broadcast
+	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_combiner:1.1 phase_sample_combine
+	set i_q_resize [create_bd_cell -type ip -vlnv analog.com:user:util_axis_resize:1.0 i_q_resize]
+
+	set_property -dict [list \
+		CONFIG.MASTER_DATA_WIDTH 32 \
+		CONFIG.SLAVE_DATA_WIDTH 64 \
+	] $i_q_resize
+
+	set hpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 hpf]
+	set lpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 lpf]
+
+	set_property -dict [list \
+		CONFIG.Data_Fractional_Bits.VALUE_SRC USER \
+		CONFIG.Data_Sign.VALUE_SRC USER \
+		CONFIG.Data_Width.VALUE_SRC USER \
+		CONFIG.M_DATA_Has_TREADY true \
+		CONFIG.Number_Channels 2 \
+		CONFIG.Sample_Frequency 0.025 \
+		CONFIG.Clock_Frequency 100 \
+		CONFIG.Coefficient_Width 16 \
+		CONFIG.Data_Width 24 \
+		CONFIG.Output_Width 32 \
+		CONFIG.Output_Rounding_Mode Truncate_LSBs \
+		CONFIG.Has_ARESETn true \
+		CONFIG.Reset_Data_Vector false \
+		CONFIG.CoefficientVector [load_fir_filter_vector "../common/filters/hpf.mat"] \
+	] $hpf
+
+	set_property -dict [list \
+		CONFIG.Data_Fractional_Bits.VALUE_SRC USER \
+		CONFIG.Data_Sign.VALUE_SRC USER \
+		CONFIG.Data_Width.VALUE_SRC USER \
+		CONFIG.M_DATA_Has_TREADY true \
+		CONFIG.Number_Channels 4 \
+		CONFIG.Sample_Frequency 0.025 \
+		CONFIG.Clock_Frequency 100 \
+		CONFIG.Coefficient_Width 24 \
+		CONFIG.Data_Width 32 \
+		CONFIG.Output_Width 32 \
+		CONFIG.Output_Rounding_Mode Truncate_LSBs \
+		CONFIG.Has_ARESETn true \
+		CONFIG.Reset_Data_Vector false \
+		CONFIG.CoefficientVector [load_fir_filter_vector "../common/filters/lpf.mat"] \
+	] $lpf
+
+	set overflow_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 overflow_or]
+	set_property -dict [list \
+		CONFIG.C_SIZE 1 \
+		CONFIG.C_OPERATION {or} \
+	] $overflow_or
+
+	ad_connect S_AXIS_SAMPLE phase_data_sync/S_AXIS_SAMPLE
+	ad_connect conv_done phase_data_sync/conv_done
+	ad_connect phase phase_data_sync/phase
+
+	ad_connect phase_data_sync/M_AXIS_PHASE phase_broadcast/S_AXIS
+	ad_connect phase_broadcast/M00_AXIS sequencer/phase
+	ad_connect phase_broadcast/M01_AXIS phase_sample_combine/S01_AXIS
+
+	ad_connect phase_data_sync/M_AXIS_SAMPLE sample_broadcast/S_AXIS
+	ad_connect sample_broadcast/M00_AXIS sequencer/data
+	ad_connect sample_broadcast/M01_AXIS hpf/S_AXIS_DATA
+
+	ad_connect hpf/M_AXIS_DATA sample_filtered_broadcast/S_AXIS
+	ad_connect sample_filtered_broadcast/M00_AXIS sequencer/data_filtered
+	ad_connect sample_filtered_broadcast/M01_AXIS phase_sample_combine/S00_AXIS
+
+	ad_connect phase_sample_combine/M_AXIS cordic_demod/S_AXIS
+	ad_connect cordic_demod/M_AXIS i_q_resize/s_axis
+
+	ad_connect i_q_resize/m_axis i_q_broadcast/S_AXIS
+	ad_connect i_q_broadcast/M00_AXIS sequencer/i_q
+	ad_connect i_q_broadcast/M01_AXIS lpf/S_AXIS_DATA
+
+	ad_connect lpf/M_AXIS_DATA sequencer/i_q_filtered
+
+	connect_bd_net \
+		[get_bd_pins clk] \
+		[get_bd_pins phase_data_sync/clk] \
+		[get_bd_pins sequencer/clk] \
+		[get_bd_pins cordic_demod/clk] \
+		[get_bd_pins phase_broadcast/aclk] \
+		[get_bd_pins sample_broadcast/aclk] \
+		[get_bd_pins sample_filtered_broadcast/aclk] \
+		[get_bd_pins i_q_broadcast/aclk] \
+		[get_bd_pins phase_sample_combine/aclk] \
+		[get_bd_pins i_q_resize/clk] \
+		[get_bd_pins hpf/aclk] \
+		[get_bd_pins lpf/aclk]
+
+	connect_bd_net \
+		[get_bd_pins resetn] \
+		[get_bd_pins sequencer/resetn] \
+		[get_bd_pins phase_data_sync/resetn] \
+
+	connect_bd_net \
+		[get_bd_pins sequencer/processing_resetn] \
+		[get_bd_pins phase_data_sync/processing_resetn] \
+		[get_bd_pins cordic_demod/resetn] \
+		[get_bd_pins phase_broadcast/aresetn] \
+		[get_bd_pins sample_broadcast/aresetn] \
+		[get_bd_pins sample_filtered_broadcast/aresetn] \
+		[get_bd_pins i_q_broadcast/aresetn] \
+		[get_bd_pins phase_sample_combine/aresetn] \
+		[get_bd_pins i_q_resize/resetn] \
+		[get_bd_pins hpf/aresetn] \
+		[get_bd_pins lpf/aresetn]
+
+	ad_connect channel_enable sequencer/channel_enable
+	ad_connect sequencer/dma_wr DMA_WR
+
+	ad_connect phase_data_sync/overflow overflow_or/Op1
+	ad_connect sequencer/overflow overflow_or/Op2
+	ad_connect overflow_or/Res overflow
+
+	ad_connect phase_data_sync/sample_has_stat GND
+
+current_bd_instance /
+
+ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE
+ad_connect /spi/conv_done /processing/conv_done
+ad_connect /phase_gen/Q /processing/phase
+
+set axi_adc [create_bd_cell -type ip -vlnv analog.com:user:axi_generic_adc:1.0 axi_adc]
+set_property -dict [list \
+		CONFIG.NUM_OF_CHANNELS 14 \
+	] $axi_adc
+
+ad_connect processing/overflow axi_adc/adc_dovf
+ad_connect axi_adc/adc_enable processing/channel_enable
+
+connect_bd_net -net sys_cpu_clk \
+	[get_bd_pins /spi/clk] \
+	[get_bd_pins /processing/clk] \
+	[get_bd_pins /axi_dma/m_dest_axi_aclk] \
+	[get_bd_pins /axi_dma/fifo_wr_clk] \
+	[get_bd_pins /phase_gen/CLK] \
+	[get_bd_pins /axi_adc/adc_clk]
+
+connect_bd_net -net sys_cpu_resetn \
+	[get_bd_pins /spi/resetn] \
+	[get_bd_pins /processing/resetn] \
+	[get_bd_pins /axi_dma/m_dest_axi_aresetn]
+
+ad_connect /processing/dma_wr /axi_dma/fifo_wr
+
+ad_cpu_interconnect 0x43c00000 /axi_adc
+ad_cpu_interconnect 0x44a00000 /spi/axi
+ad_cpu_interconnect 0x44a30000 /axi_dma
+
+ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq
+ad_cpu_interrupt "ps-12" "mb-12" /spi/irq
+
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk axi_dma/m_dest_axi
diff --git a/projects/cn0363/zed/filters/hpf.mat b/projects/cn0363/common/filters/hpf.mat
similarity index 100%
rename from projects/cn0363/zed/filters/hpf.mat
rename to projects/cn0363/common/filters/hpf.mat
diff --git a/projects/cn0363/zed/filters/lpf.mat b/projects/cn0363/common/filters/lpf.mat
similarity index 100%
rename from projects/cn0363/zed/filters/lpf.mat
rename to projects/cn0363/common/filters/lpf.mat
diff --git a/projects/cn0363/zed/system_bd.tcl b/projects/cn0363/zed/system_bd.tcl
index 3ccb75fa9..626e401e3 100644
--- a/projects/cn0363/zed/system_bd.tcl
+++ b/projects/cn0363/zed/system_bd.tcl
@@ -1,297 +1,9 @@
 
 source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
-
-proc load_fir_filter_vector {filter_file} {
-	set fp [open $filter_file r]
-	set data [split [read $fp] "\n"]
-	set filter ""
-	close $fp
-	foreach line $data {
-		set line [string trim $line]
-		if {[string equal -length 1 $line "#"] || $line eq ""} {
-			continue
-		}
-		if {$filter ne ""} {
-			append filter ","
-		}
-		append filter $line
-	}
-
-	return $filter
-}
+source ../common/cn0363_bd.tcl
 
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7
 
 set_property LEFT 34 [get_bd_ports GPIO_I]
 set_property LEFT 34 [get_bd_ports GPIO_O]
 set_property LEFT 34 [get_bd_ports GPIO_T]
-
-set axi_dma  [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_dma]
-set_property -dict [list \
-		CONFIG.FIFO_SIZE 2 \
-		CONFIG.DMA_TYPE_SRC 2 \
-		CONFIG.DMA_TYPE_DEST 0 \
-		CONFIG.CYCLIC 0 \
-		CONFIG.SYNC_TRANSFER_START 1 \
-		CONFIG.AXI_SLICE_SRC 0 \
-		CONFIG.AXI_SLICE_DEST 0 \
-		CONFIG.DMA_2D_TRANSFER 0 \
-		CONFIG.DMA_DATA_WIDTH_SRC 32 \
-		CONFIG.DMA_DATA_WIDTH_DEST 64 \
-		CONFIG.DMA_AXI_PROTOCOL_DEST 1 \
-	] $axi_dma
-
-# Create SPI engine controller with offload
-create_bd_cell -type hier spi
-current_bd_instance /spi
-
-	create_bd_pin -dir I -type clk clk
-	create_bd_pin -dir I -type rst resetn
-	create_bd_pin -dir O conv_done
-	create_bd_pin -dir O irq
-	create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
-	create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
-
-	set spi_engine [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 execution]
-	set axi_spi_engine [create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi]
-	set spi_engine_offload [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_offload:1.0 offload]
-	set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect]
-	set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi]
-
-	set_property -dict [list CONFIG.NUM_OF_CS 2] $spi_engine
-
-	set_property -dict [list CONFIG.NUM_OF_CS 2] $util_sigma_delta_spi
-
-	ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
-	ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
-	ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
-	ad_connect interconnect/m_ctrl execution/ctrl
-	ad_connect offload/offload_sdi M_AXIS_SAMPLE
-
-	ad_connect util_sigma_delta_spi/data_ready offload/trigger
-	ad_connect util_sigma_delta_spi/data_ready conv_done
-
-	ad_connect execution/active util_sigma_delta_spi/spi_active
-	ad_connect execution/spi util_sigma_delta_spi/s_spi
-	ad_connect util_sigma_delta_spi/m_spi m_spi
-
-	connect_bd_net \
-		[get_bd_pins clk] \
-		[get_bd_pins offload/spi_clk] \
-		[get_bd_pins offload/ctrl_clk] \
-		[get_bd_pins execution/clk] \
-		[get_bd_pins axi/s_axi_aclk] \
-		[get_bd_pins axi/spi_clk] \
-		[get_bd_pins interconnect/clk] \
-		[get_bd_pins util_sigma_delta_spi/clk]
-
-	connect_bd_net \
-		[get_bd_pins axi/spi_resetn] \
-		[get_bd_pins offload/spi_resetn] \
-		[get_bd_pins execution/resetn] \
-		[get_bd_pins interconnect/resetn] \
-		[get_bd_pins util_sigma_delta_spi/resetn]
-
-	connect_bd_net [get_bd_pins resetn] [get_bd_pins axi/s_axi_aresetn]
-	ad_connect irq axi/irq
-
-current_bd_instance /
-
-create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
-ad_connect spi/m_spi spi
-
-set phase_gen [create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 phase_gen]
-set phase_slice [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 phase_slice]
-create_bd_port -dir O excitation
-
-set excitation_freq 1020
-
-set_property -dict [list \
-		CONFIG.Output_Width 32 \
-		CONFIG.Increment_Value [format "%x" [expr $excitation_freq * (1<<32) / 100000000]] \
-	] $phase_gen
-
-set_property -dict [list \
-		CONFIG.DIN_TO {31} \
-		CONFIG.DIN_FROM {31} \
-		CONFIG.DOUT_WIDTH {1} \
-	] $phase_slice
-
-ad_connect /phase_gen/Q /phase_slice/Din
-ad_connect /phase_slice/Dout excitation
-
-create_bd_cell -type hier processing
-current_bd_instance /processing
-
-	create_bd_pin -dir I -type clk clk
-	create_bd_pin -dir I -type rst resetn
-	create_bd_pin -dir I conv_done
-	create_bd_pin -dir I -from 31 -to 0 phase
-	create_bd_pin -dir O overflow
-	create_bd_pin -dir I -from 13 -to 0 channel_enable
-	create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SAMPLE
-	create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR
-
-	create_bd_cell -type ip -vlnv analog.com:user:cn0363_phase_data_sync:1.0 phase_data_sync
-	create_bd_cell -type ip -vlnv analog.com:user:cn0363_dma_sequencer:1.0 sequencer
-	create_bd_cell -type ip -vlnv analog.com:user:cordic_demod:1.0 cordic_demod
-
-	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 phase_broadcast
-	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_broadcast
-	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_filtered_broadcast
-	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 i_q_broadcast
-	create_bd_cell -type ip -vlnv xilinx.com:ip:axis_combiner:1.1 phase_sample_combine
-	set i_q_resize [create_bd_cell -type ip -vlnv analog.com:user:util_axis_resize:1.0 i_q_resize]
-
-	set_property -dict [list \
-		CONFIG.MASTER_DATA_WIDTH 32 \
-		CONFIG.SLAVE_DATA_WIDTH 64 \
-	] $i_q_resize
-
-	set hpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 hpf]
-	set lpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 lpf]
-
-	set_property -dict [list \
-		CONFIG.Data_Fractional_Bits.VALUE_SRC USER \
-		CONFIG.Data_Sign.VALUE_SRC USER \
-		CONFIG.Data_Width.VALUE_SRC USER \
-		CONFIG.M_DATA_Has_TREADY true \
-		CONFIG.Number_Channels 2 \
-		CONFIG.Sample_Frequency 0.025 \
-		CONFIG.Clock_Frequency 100 \
-		CONFIG.Coefficient_Width 16 \
-		CONFIG.Data_Width 24 \
-		CONFIG.Output_Width 32 \
-		CONFIG.Output_Rounding_Mode Truncate_LSBs \
-		CONFIG.Has_ARESETn true \
-		CONFIG.Reset_Data_Vector false \
-		CONFIG.CoefficientVector [load_fir_filter_vector "filters/hpf.mat"] \
-	] $hpf
-
-	set_property -dict [list \
-		CONFIG.Data_Fractional_Bits.VALUE_SRC USER \
-		CONFIG.Data_Sign.VALUE_SRC USER \
-		CONFIG.Data_Width.VALUE_SRC USER \
-		CONFIG.M_DATA_Has_TREADY true \
-		CONFIG.Number_Channels 4 \
-		CONFIG.Sample_Frequency 0.025 \
-		CONFIG.Clock_Frequency 100 \
-		CONFIG.Coefficient_Width 24 \
-		CONFIG.Data_Width 32 \
-		CONFIG.Output_Width 32 \
-		CONFIG.Output_Rounding_Mode Truncate_LSBs \
-		CONFIG.Has_ARESETn true \
-		CONFIG.Reset_Data_Vector false \
-		CONFIG.CoefficientVector [load_fir_filter_vector "filters/lpf.mat"] \
-	] $lpf
-
-	set overflow_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 overflow_or]
-	set_property -dict [list \
-		CONFIG.C_SIZE 1 \
-		CONFIG.C_OPERATION {or} \
-	] $overflow_or
-
-	ad_connect S_AXIS_SAMPLE phase_data_sync/S_AXIS_SAMPLE
-	ad_connect conv_done phase_data_sync/conv_done
-	ad_connect phase phase_data_sync/phase
-
-	ad_connect phase_data_sync/M_AXIS_PHASE phase_broadcast/S_AXIS
-	ad_connect phase_broadcast/M00_AXIS sequencer/phase
-	ad_connect phase_broadcast/M01_AXIS phase_sample_combine/S01_AXIS
-
-	ad_connect phase_data_sync/M_AXIS_SAMPLE sample_broadcast/S_AXIS
-	ad_connect sample_broadcast/M00_AXIS sequencer/data
-	ad_connect sample_broadcast/M01_AXIS hpf/S_AXIS_DATA
-
-	ad_connect hpf/M_AXIS_DATA sample_filtered_broadcast/S_AXIS
-	ad_connect sample_filtered_broadcast/M00_AXIS sequencer/data_filtered
-	ad_connect sample_filtered_broadcast/M01_AXIS phase_sample_combine/S00_AXIS
-
-	ad_connect phase_sample_combine/M_AXIS cordic_demod/S_AXIS
-	ad_connect cordic_demod/M_AXIS i_q_resize/s_axis
-
-	ad_connect i_q_resize/m_axis i_q_broadcast/S_AXIS
-	ad_connect i_q_broadcast/M00_AXIS sequencer/i_q
-	ad_connect i_q_broadcast/M01_AXIS lpf/S_AXIS_DATA
-
-	ad_connect lpf/M_AXIS_DATA sequencer/i_q_filtered
-
-	connect_bd_net \
-		[get_bd_pins clk] \
-		[get_bd_pins phase_data_sync/clk] \
-		[get_bd_pins sequencer/clk] \
-		[get_bd_pins cordic_demod/clk] \
-		[get_bd_pins phase_broadcast/aclk] \
-		[get_bd_pins sample_broadcast/aclk] \
-		[get_bd_pins sample_filtered_broadcast/aclk] \
-		[get_bd_pins i_q_broadcast/aclk] \
-		[get_bd_pins phase_sample_combine/aclk] \
-		[get_bd_pins i_q_resize/clk] \
-		[get_bd_pins hpf/aclk] \
-		[get_bd_pins lpf/aclk]
-
-	connect_bd_net \
-		[get_bd_pins resetn] \
-		[get_bd_pins sequencer/resetn] \
-		[get_bd_pins phase_data_sync/resetn] \
-
-	connect_bd_net \
-		[get_bd_pins sequencer/processing_resetn] \
-		[get_bd_pins phase_data_sync/processing_resetn] \
-		[get_bd_pins cordic_demod/resetn] \
-		[get_bd_pins phase_broadcast/aresetn] \
-		[get_bd_pins sample_broadcast/aresetn] \
-		[get_bd_pins sample_filtered_broadcast/aresetn] \
-		[get_bd_pins i_q_broadcast/aresetn] \
-		[get_bd_pins phase_sample_combine/aresetn] \
-		[get_bd_pins i_q_resize/resetn] \
-		[get_bd_pins hpf/aresetn] \
-		[get_bd_pins lpf/aresetn]
-
-	ad_connect channel_enable sequencer/channel_enable
-	ad_connect sequencer/dma_wr DMA_WR
-
-	ad_connect phase_data_sync/overflow overflow_or/Op1
-	ad_connect sequencer/overflow overflow_or/Op2
-	ad_connect overflow_or/Res overflow
-
-	ad_connect phase_data_sync/sample_has_stat GND
-
-current_bd_instance /
-
-ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE
-ad_connect /spi/conv_done /processing/conv_done
-ad_connect /phase_gen/Q /processing/phase
-
-set axi_adc [create_bd_cell -type ip -vlnv analog.com:user:axi_generic_adc:1.0 axi_adc]
-set_property -dict [list \
-		CONFIG.NUM_OF_CHANNELS 14 \
-	] $axi_adc
-
-ad_connect processing/overflow axi_adc/adc_dovf
-ad_connect axi_adc/adc_enable processing/channel_enable
-
-connect_bd_net -net sys_cpu_clk \
-	[get_bd_pins /spi/clk] \
-	[get_bd_pins /processing/clk] \
-	[get_bd_pins /axi_dma/m_dest_axi_aclk] \
-	[get_bd_pins /axi_dma/fifo_wr_clk] \
-	[get_bd_pins /phase_gen/CLK] \
-	[get_bd_pins /axi_adc/adc_clk]
-
-connect_bd_net -net sys_cpu_resetn \
-	[get_bd_pins /spi/resetn] \
-	[get_bd_pins /processing/resetn] \
-	[get_bd_pins /axi_dma/m_dest_axi_aresetn]
-
-ad_connect /processing/dma_wr /axi_dma/fifo_wr
-
-ad_cpu_interconnect 0x43c00000 /axi_adc
-ad_cpu_interconnect 0x44a00000 /spi/axi
-ad_cpu_interconnect 0x44a30000 /axi_dma
-
-ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq
-ad_cpu_interrupt "ps-12" "mb-12" /spi/irq
-
-ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
-ad_mem_hp2_interconnect sys_cpu_clk axi_dma/m_dest_axi

From c094ab8b526356a957710a6d9ab4a85e4131e791 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Wed, 13 Jan 2016 20:14:33 +0100
Subject: [PATCH 050/972] cn0363: Add support for the MicroZed

Add support for connecting the CN0363 to the MicroZed. This works in
combination with the MicroZed Arduino carrier board. The CN0363 needs to be
connected to the PLPMOD header.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/cn0363/Makefile                    |   3 +
 projects/cn0363/microzed/Makefile           | 101 +++++++++++
 projects/cn0363/microzed/system_bd.tcl      |   3 +
 projects/cn0363/microzed/system_constr.xdc  |  23 +++
 projects/cn0363/microzed/system_project.tcl |  12 ++
 projects/cn0363/microzed/system_top.v       | 180 ++++++++++++++++++++
 6 files changed, 322 insertions(+)
 create mode 100644 projects/cn0363/microzed/Makefile
 create mode 100644 projects/cn0363/microzed/system_bd.tcl
 create mode 100644 projects/cn0363/microzed/system_constr.xdc
 create mode 100644 projects/cn0363/microzed/system_project.tcl
 create mode 100644 projects/cn0363/microzed/system_top.v

diff --git a/projects/cn0363/Makefile b/projects/cn0363/Makefile
index 141f88d2a..97649c5b4 100644
--- a/projects/cn0363/Makefile
+++ b/projects/cn0363/Makefile
@@ -8,14 +8,17 @@
 .PHONY: all clean clean-all 
 all:
 	-make -C zed all
+	-make -C microzed all
 
 
 clean: 
 	make -C zed clean
+	make -C microzed clean
 
 
 clean-all:
 	make -C zed clean-all
+	make -C microzed clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile
new file mode 100644
index 000000000..103980135
--- /dev/null
+++ b/projects/cn0363/microzed/Makefile
@@ -0,0 +1,101 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/microzed/microzed_system_constr.xdc
+M_DEPS += ../../common/microzed/microzed_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_generic_adc/axi_generic_adc.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
+M_DEPS += ../../../library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr
+M_DEPS += ../../../library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr
+M_DEPS += ../../../library/cordic_demod/cordic_demod.xpr
+M_DEPS += ../../../library/spi_engine/spi_engine_execution/spi_engine_execution.xpr
+M_DEPS += ../../../library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
+M_DEPS += ../../../library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.xpr
+M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
+M_DEPS += ../../../library/util_sigma_delta_spi/util_sigma_delta_spi.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib cn0363_microzed.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_generic_adc clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_i2s_adi clean
+	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/spi_engine/axi_spi_engine clean
+	make -C ../../../library/cn0363/cn0363_dma_sequencer clean
+	make -C ../../../library/cn0363/cn0363_phase_data_sync clean
+	make -C ../../../library/cordic_demod clean
+	make -C ../../../library/spi_engine/spi_engine_execution clean
+	make -C ../../../library/spi_engine/spi_engine_interconnect clean
+	make -C ../../../library/spi_engine/spi_engine_offload clean
+	make -C ../../../library/util_axis_resize clean
+	make -C ../../../library/util_i2c_mixer clean
+	make -C ../../../library/util_sigma_delta_spi clean
+
+
+cn0363_microzed.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> cn0363_microzed_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_generic_adc
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_i2s_adi
+	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/spi_engine/axi_spi_engine
+	make -C ../../../library/cn0363/cn0363_dma_sequencer
+	make -C ../../../library/cn0363/cn0363_phase_data_sync
+	make -C ../../../library/cordic_demod
+	make -C ../../../library/spi_engine/spi_engine_execution
+	make -C ../../../library/spi_engine/spi_engine_interconnect
+	make -C ../../../library/spi_engine/spi_engine_offload
+	make -C ../../../library/util_axis_resize
+	make -C ../../../library/util_i2c_mixer
+	make -C ../../../library/util_sigma_delta_spi
+
+####################################################################################
+####################################################################################
diff --git a/projects/cn0363/microzed/system_bd.tcl b/projects/cn0363/microzed/system_bd.tcl
new file mode 100644
index 000000000..6c09795d3
--- /dev/null
+++ b/projects/cn0363/microzed/system_bd.tcl
@@ -0,0 +1,3 @@
+
+source $ad_hdl_dir/projects/common/microzed/microzed_system_bd.tcl
+source ../common/cn0363_bd.tcl
diff --git a/projects/cn0363/microzed/system_constr.xdc b/projects/cn0363/microzed/system_constr.xdc
new file mode 100644
index 000000000..0816b1b0a
--- /dev/null
+++ b/projects/cn0363/microzed/system_constr.xdc
@@ -0,0 +1,23 @@
+
+# PL PMOD
+
+set_property PACKAGE_PIN G17 [get_ports gain0_o]
+set_property IOSTANDARD LVCMOS33 [get_ports gain0_o]
+set_property PACKAGE_PIN G18 [get_ports gain1_o]
+set_property IOSTANDARD LVCMOS33 [get_ports gain1_o]
+set_property PACKAGE_PIN F19 [get_ports {spi_cs[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[1]}]
+set_property PACKAGE_PIN F20 [get_ports led_clk_o]
+set_property IOSTANDARD LVCMOS33 [get_ports led_clk_o]
+
+set_property PACKAGE_PIN N15 [get_ports {spi_cs[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[0]}]
+set_property PACKAGE_PIN N16 [get_ports spi_sdo]
+set_property IOSTANDARD LVCMOS33 [get_ports spi_sdo]
+set_property PULLUP true [get_ports spi_sdo]
+set_property PACKAGE_PIN L14 [get_ports spi_sdi]
+set_property IOSTANDARD LVCMOS33 [get_ports spi_sdi]
+set_property PULLUP true [get_ports spi_sdi]
+set_property PACKAGE_PIN L15 [get_ports spi_sclk]
+set_property IOSTANDARD LVCMOS33 [get_ports spi_sclk]
+
diff --git a/projects/cn0363/microzed/system_project.tcl b/projects/cn0363/microzed/system_project.tcl
new file mode 100644
index 000000000..a66ba45b8
--- /dev/null
+++ b/projects/cn0363/microzed/system_project.tcl
@@ -0,0 +1,12 @@
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create cn0363_microzed
+adi_project_files cn0363_microzed [list \
+  "system_top.v" \
+  "system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/microzed/microzed_system_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_iobuf.v"]
+
+adi_project_run cn0363_microzed
diff --git a/projects/cn0363/microzed/system_top.v b/projects/cn0363/microzed/system_top.v
new file mode 100644
index 000000000..f6ea4ce35
--- /dev/null
+++ b/projects/cn0363/microzed/system_top.v
@@ -0,0 +1,180 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  spi_sdo,
+  spi_sdi,
+  spi_cs,
+  spi_sclk,
+  led_clk_o,
+  gain0_o,
+  gain1_o,
+  
+  otg_vbusoc);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  input           spi_sdi;
+  inout           spi_sdo;
+  output          spi_sclk;
+  output  [ 1:0]  spi_cs;
+  output          led_clk_o;
+  output          gain0_o;
+  output          gain1_o;
+
+  input           otg_vbusoc;
+
+  // internal signals
+
+  wire    [34:0]  gpio_i;
+  wire    [34:0]  gpio_o;
+  wire    [34:0]  gpio_t;
+  wire    [23:0]  offload_sdi_data;
+
+  wire spi_sdo_o;
+  wire spi_sdo_t;
+  wire excitation;
+
+  assign gain0_o = gpio_o[32];
+  assign gain1_o = gpio_o[33];
+  
+  assign gpio_i[34] = spi_sdi; // Interrupt
+  assign led_clk_o = excitation;
+
+  ad_iobuf #(
+    .DATA_WIDTH(1)
+  ) i_sdo_iobuf (
+    .dio_t(spi_sdo_t),
+    .dio_i(spi_sdo_o),
+    .dio_p(spi_sdo)
+  );
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .spi_sdo (spi_sdo_o),
+    .spi_sdo_t (spi_sdo_t),
+    .spi_sdi (spi_sdi),
+    .spi_cs (spi_cs),
+    .spi_sclk (spi_sclk),
+    .excitation (excitation));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From ab99c4456a02ea0c0f67aca972ab7a443186b782 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Thu, 14 Jan 2016 15:41:23 +0200
Subject: [PATCH 051/972] ad9434_fmc: Delete unnecessary set_property call

HPx interface is activated by the ad_mem_hpx_interconnect process
---
 projects/ad9434_fmc/common/ad9434_bd.tcl | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/projects/ad9434_fmc/common/ad9434_bd.tcl b/projects/ad9434_fmc/common/ad9434_bd.tcl
index 8529e8f24..a15381c2a 100644
--- a/projects/ad9434_fmc/common/ad9434_bd.tcl
+++ b/projects/ad9434_fmc/common/ad9434_bd.tcl
@@ -23,10 +23,6 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9434_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9434_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}]  $axi_ad9434_dma
 
-# additions to default configuration
-
-set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
-
 # ad9434 connections
 
 ad_connect  sys_200m_clk axi_ad9434/delay_clk

From c6cfd1a2b656e698854a56a94b13d6cbe6dbe501 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 14 Jan 2016 14:37:56 +0200
Subject: [PATCH 052/972] axi_ad9684: Initial check in

---
 library/axi_ad9684/axi_ad9684.v          | 404 +++++++++++++++++++++++
 library/axi_ad9684/axi_ad9684_channel.v  | 191 +++++++++++
 library/axi_ad9684/axi_ad9684_constr.xdc |   2 +
 library/axi_ad9684/axi_ad9684_if.v       | 287 ++++++++++++++++
 library/axi_ad9684/axi_ad9684_ip.tcl     |  38 +++
 library/axi_ad9684/axi_ad9684_pnmon.v    | 186 +++++++++++
 6 files changed, 1108 insertions(+)
 create mode 100644 library/axi_ad9684/axi_ad9684.v
 create mode 100644 library/axi_ad9684/axi_ad9684_channel.v
 create mode 100644 library/axi_ad9684/axi_ad9684_constr.xdc
 create mode 100644 library/axi_ad9684/axi_ad9684_if.v
 create mode 100644 library/axi_ad9684/axi_ad9684_ip.tcl
 create mode 100644 library/axi_ad9684/axi_ad9684_pnmon.v

diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v
new file mode 100644
index 000000000..be1072b71
--- /dev/null
+++ b/library/axi_ad9684/axi_ad9684.v
@@ -0,0 +1,404 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2015(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9684 (
+
+  // device interface ports
+
+  adc_clk_in_p,
+  adc_clk_in_n,
+  adc_data_in_p,
+  adc_data_in_n,
+  adc_data_or_p,
+  adc_data_or_n,
+
+  // dma interface ports
+
+  adc_clk,
+  adc_rst,
+  adc_valid_0,
+  adc_enable_0,
+  adc_data_0,
+  adc_valid_1,
+  adc_enable_1,
+  adc_data_1,
+  adc_dovf,
+  adc_dunf,
+
+  // delay clock ports
+
+  delay_clk,
+
+  // axi slave interface ports
+
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awvalid,
+  s_axi_awaddr,
+  s_axi_awready,
+  s_axi_wvalid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wready,
+  s_axi_bvalid,
+  s_axi_bresp,
+  s_axi_bready,
+  s_axi_arvalid,
+  s_axi_araddr,
+  s_axi_arready,
+  s_axi_rvalid,
+  s_axi_rresp,
+  s_axi_rdata,
+  s_axi_rready
+);
+
+  // parameters
+
+  parameter ID = 0;
+  parameter DEVICE_TYPE = 0;
+  parameter IO_DELAY_GROUP = "dev_if_delay_group";
+  parameter OR_STATUS = 1;
+
+  // IO definitions
+
+  input           adc_clk_in_p;
+  input           adc_clk_in_n;
+  input   [13:0]  adc_data_in_p;
+  input   [13:0]  adc_data_in_n;
+  input           adc_data_or_p;
+  input           adc_data_or_n;
+
+  output          adc_clk;
+  output          adc_rst;
+  output          adc_valid_0;
+  output          adc_enable_0;
+  output  [31:0]  adc_data_0;
+  output          adc_valid_1;
+  output          adc_enable_1;
+  output  [31:0]  adc_data_1;
+  input           adc_dovf;
+  input           adc_dunf;
+
+  input           delay_clk;
+
+  input           s_axi_aclk;
+  input           s_axi_aresetn;
+  input           s_axi_awvalid;
+  input   [31:0]  s_axi_awaddr;
+  output          s_axi_awready;
+  input           s_axi_wvalid;
+  input   [31:0]  s_axi_wdata;
+  input   [ 3:0]  s_axi_wstrb;
+  output          s_axi_wready;
+  output          s_axi_bvalid;
+  output  [ 1:0]  s_axi_bresp;
+  input           s_axi_bready;
+  input           s_axi_arvalid;
+  input   [31:0]  s_axi_araddr;
+  output          s_axi_arready;
+  output          s_axi_rvalid;
+  output  [ 1:0]  s_axi_rresp;
+  output  [31:0]  s_axi_rdata;
+  input           s_axi_rready;
+
+  // internal registers
+
+  reg             up_wack = 1'b0;
+  reg     [31:0]  up_rdata = 32'b0;
+  reg             up_rack = 1'b0;
+
+  // internal clocks & resets
+
+  wire            up_clk;
+  wire            up_rstn;
+  wire            delay_rst;
+
+  // internal signals
+
+  wire    [55:0]  adc_rawdata_s;
+  wire    [27:0]  adc_rawdata_0_s;
+  wire    [27:0]  adc_rawdata_1_s;
+  wire            adc_or_0_s;
+  wire            adc_or_1_s;
+  wire            adc_status_s;
+  wire            adc_or_s;
+  wire    [14:0]  up_dld_s;
+  wire    [74:0]  up_dwdata_s;
+  wire    [74:0]  up_drdata_s;
+  wire            delay_locked_s;
+  wire            up_status_pn_err_s;
+  wire            up_status_pn_oos_s;
+  wire            up_status_or_s;
+  wire    [ 1:0]  up_adc_pn_err_s;
+  wire    [ 1:0]  up_adc_pn_oos_s;
+  wire    [ 1:0]  up_adc_or_s;
+  wire            up_rreq_s;
+  wire    [13:0]  up_raddr_s;
+  wire    [31:0]  up_rdata_s[0:3];
+  wire            up_rack_s[0:3];
+  wire            up_wack_s[0:3];
+  wire            up_wreq_s;
+  wire    [13:0]  up_waddr_s;
+  wire    [31:0]  up_wdata_s;
+  wire            up_drp_sel_s;
+  wire            up_drp_wr_s;
+  wire    [11:0]  up_drp_addr_s;
+  wire    [15:0]  up_drp_wdata_s;
+  wire    [15:0]  up_drp_rdata_s;
+  wire            up_drp_ready_s;
+  wire            up_drp_locked_s;
+  wire            mmcm_rst_s;
+
+  //defaults
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+  assign adc_valid = 1'b1;
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rdata <= 32'd0;
+      up_rack <= 1'd0;
+      up_wack <= 1'd0;
+    end else begin
+      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
+      up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
+      up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
+    end
+  end
+
+  // device interface instance
+
+  axi_ad9684_if #(
+    .DEVICE_TYPE(DEVICE_TYPE),
+    .IO_DELAY_GROUP(IO_DELAY_GROUP),
+    .OR_STATUS (OR_STATUS))
+  i_ad9684_if (
+    .adc_clk_in_p (adc_clk_in_p),
+    .adc_clk_in_n (adc_clk_in_n),
+    .adc_data_in_p (adc_data_in_p),
+    .adc_data_in_n (adc_data_in_n),
+    .adc_data_or_p (adc_data_or_p),
+    .adc_data_or_n (adc_data_or_n),
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_data_a (adc_rawdata_0_s),
+    .adc_or_a (adc_or_0_s),
+    .adc_data_b (adc_rawdata_1_s),
+    .adc_or_b (adc_or_1_s),
+    .adc_status (adc_status_s),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_dload (up_dld_s),
+    .delay_wdata (up_dwdata_s),
+    .delay_rdata (up_drdata_s),
+    .delay_locked (delay_locked_s),
+    .mmcm_rst (mmcm_rst_s),
+    .up_clk (up_clk),
+    .up_rstn (up_rstn),
+    .up_drp_sel (up_drp_sel_s),
+    .up_drp_wr (up_drp_wr_s),
+    .up_drp_addr (up_drp_addr_s),
+    .up_drp_wdata (up_drp_wdata_s),
+    .up_drp_rdata (up_drp_rdata_s),
+    .up_drp_ready (up_drp_ready_s),
+    .up_drp_locked (up_drp_locked_s));
+
+  // common processor control instance
+
+  assign up_status_pn_err_s = up_adc_pn_err_s[0] | up_adc_pn_err_s[1];
+  assign up_status_pn_oos_s = up_adc_pn_oos_s[0] | up_adc_pn_oos_s[1];
+  assign up_status_or_s = up_adc_or_s[0] | up_adc_or_s[1];
+
+  up_adc_common #(
+    .ID(ID))
+  i_up_adc_common (
+    .mmcm_rst (mmcm_rst_s),
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_r1_mode (),
+    .adc_ddr_edgesel (),
+    .adc_pin_mode (),
+    .adc_status (adc_status_s),
+    .adc_sync_status (1'd0),
+    .adc_status_ovf (adc_dovf),
+    .adc_status_unf (adc_dunf),
+    .adc_clk_ratio (32'b1),
+    .adc_start_code (),
+    .adc_sync (),
+    .up_status_pn_err (up_status_pn_err_s),
+    .up_status_pn_oos (up_status_pn_oos_s),
+    .up_status_or (up_status_or_s),
+    .up_drp_sel (up_drp_sel_s),
+    .up_drp_wr (up_drp_wr_s),
+    .up_drp_addr (up_drp_addr_s),
+    .up_drp_wdata (up_drp_wdata_s),
+    .up_drp_rdata (up_drp_rdata_s),
+    .up_drp_ready (up_drp_ready_s),
+    .up_drp_locked (up_drp_locked_s),
+    .up_usr_chanmax (),
+    .adc_usr_chanmax (8'd1),
+    .up_adc_gpio_in (32'd0),
+    .up_adc_gpio_out (),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  // adc channel 0 instance
+
+  axi_ad9684_channel #(
+    .CHANNEL_ID (0),
+    .Q_OR_I_N (0))
+  i_channel_0 (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_data (adc_rawdata_0_s),
+    .adc_data_q (adc_rawdata_1_s),
+    .adc_or (adc_or_0_s),
+    .adc_dfmt_data (adc_data_0),
+    .adc_valid (adc_valid_0),
+    .adc_enable (adc_enable_0),
+    .up_adc_pn_err (up_adc_pn_err_s[0]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[0]),
+    .up_adc_or (up_adc_or_s[0]),
+    .up_clk (up_clk),
+    .up_rstn (up_rstn),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[1]),
+    .up_rack (up_rack_s[1]));
+
+  // adc channel 1 instance
+
+  axi_ad9684_channel #(
+    .CHANNEL_ID (1),
+    .Q_OR_I_N (1))
+  i_channel_1 (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_data (adc_rawdata_1_s),
+    .adc_data_q (adc_rawdata_0_s),
+    .adc_or (adc_or_1_s),
+    .adc_dfmt_data (adc_data_1),
+    .adc_valid (adc_valid_1),
+    .adc_enable (adc_enable_1),
+    .up_adc_pn_err (up_adc_pn_err_s[1]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[1]),
+    .up_adc_or (up_adc_or_s[1] ),
+    .up_clk (up_clk),
+    .up_rstn (up_rstn),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[2]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[2]),
+    .up_rack (up_rack_s[2]));
+
+  // adc delay control instance
+
+  up_delay_cntrl #(
+    .DATA_WIDTH(15))
+  i_delay_cntrl (
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked_s),
+    .up_dld (up_dld_s),
+    .up_dwdata (up_dwdata_s),
+    .up_drdata (up_drdata_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[3]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[3]),
+    .up_rack (up_rack_s[3]));
+
+  // uP bus interface instance
+
+  up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
diff --git a/library/axi_ad9684/axi_ad9684_channel.v b/library/axi_ad9684/axi_ad9684_channel.v
new file mode 100644
index 000000000..fe0de9d22
--- /dev/null
+++ b/library/axi_ad9684/axi_ad9684_channel.v
@@ -0,0 +1,191 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2015(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9684_channel (
+
+  // adc data interface
+
+  adc_clk,
+  adc_rst,
+  adc_data,
+  adc_data_q,
+  adc_or,
+
+  // channel interface
+
+  adc_dfmt_data,
+  adc_valid,
+  adc_enable,
+  up_adc_pn_err,
+  up_adc_pn_oos,
+  up_adc_or,
+
+  // up interface
+
+  up_clk,
+  up_rstn,
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack
+);
+
+  // parameters
+
+  parameter Q_OR_I_N = 0;
+  parameter CHANNEL_ID = 0;
+  parameter DATAPATH_DISABLE = 0;
+
+  // IO definitions
+
+  input           adc_clk;
+  input           adc_rst;
+  input   [27:0]  adc_data;
+  input   [27:0]  adc_data_q;
+  input           adc_or;
+
+  output  [31:0]  adc_dfmt_data;
+  output          adc_enable;
+  output          adc_valid;
+  output          up_adc_pn_err;
+  output          up_adc_pn_oos;
+  output          up_adc_or;
+
+  input           up_clk;
+  input           up_rstn;
+  input           up_wreq;
+  input   [13:0]  up_waddr;
+  input   [31:0]  up_wdata;
+  output          up_wack;
+  input           up_rreq;
+  input   [13:0]  up_raddr;
+  output  [31:0]  up_rdata;
+  output          up_rack;
+
+  // internal signals
+
+  wire            adc_pn_oos_s;
+  wire            adc_pn_err_s;
+  wire            adc_dfmt_enable_s;
+  wire            adc_dfmt_type_s;
+  wire            adc_dfmt_se_s;
+  wire    [ 1:0]  adc_dfmt_valid_s;
+  wire    [ 3:0]  adc_pnseq_sel_s;
+
+  // instantiations
+
+  axi_ad9684_pnmon i_pnmon (
+    .adc_clk (adc_clk),
+    .adc_data (adc_data),
+    .adc_pn_oos (adc_pn_oos_s),
+    .adc_pn_err (adc_pn_err_s),
+    .adc_pnseq_sel (adc_pnseq_sel_s));
+
+  genvar n;
+  generate
+  for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1
+  ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
+    .clk (adc_clk),
+    .valid (1'b1),
+    .data (adc_data[n*14+13:n*14]),
+    .valid_out (adc_dfmt_valid_s[n]),
+    .data_out (adc_dfmt_data[n*16+15:n*16]),
+    .dfmt_enable (adc_dfmt_enable_s),
+    .dfmt_type (adc_dfmt_type_s),
+    .dfmt_se (adc_dfmt_se_s));
+  end
+  endgenerate
+
+  assign adc_valid = adc_dfmt_valid_s[0] | adc_dfmt_valid_s[1];
+
+  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_enable (adc_enable),
+    .adc_iqcor_enb (),
+    .adc_dcfilt_enb (),
+    .adc_dfmt_se (adc_dfmt_se_s),
+    .adc_dfmt_type (adc_dfmt_type_s),
+    .adc_dfmt_enable (adc_dfmt_enable_s),
+    .adc_dcfilt_offset (),
+    .adc_dcfilt_coeff (),
+    .adc_iqcor_coeff_1 (),
+    .adc_iqcor_coeff_2 (),
+    .adc_pnseq_sel (adc_pnseq_sel_s),
+    .adc_data_sel (),
+    .adc_pn_err (adc_pn_err_s),
+    .adc_pn_oos (adc_pn_oos_s),
+    .adc_or (adc_or),
+    .up_adc_pn_err (up_adc_pn_err),
+    .up_adc_pn_oos (up_adc_pn_oos),
+    .up_adc_or (up_adc_or),
+    .up_usr_datatype_be (),
+    .up_usr_datatype_signed (),
+    .up_usr_datatype_shift (),
+    .up_usr_datatype_total_bits (),
+    .up_usr_datatype_bits (),
+    .up_usr_decimation_m (),
+    .up_usr_decimation_n (),
+    .adc_usr_datatype_be (1'b0),
+    .adc_usr_datatype_signed (1'b1),
+    .adc_usr_datatype_shift (8'd0),
+    .adc_usr_datatype_total_bits (8'd16),
+    .adc_usr_datatype_bits (8'd16),
+    .adc_usr_decimation_m (16'd1),
+    .adc_usr_decimation_n (16'd1),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
diff --git a/library/axi_ad9684/axi_ad9684_constr.xdc b/library/axi_ad9684/axi_ad9684_constr.xdc
new file mode 100644
index 000000000..3d94bab25
--- /dev/null
+++ b/library/axi_ad9684/axi_ad9684_constr.xdc
@@ -0,0 +1,2 @@
+set_false_path  -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}]
+                -to   [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]
diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v
new file mode 100644
index 000000000..530a6631c
--- /dev/null
+++ b/library/axi_ad9684/axi_ad9684_if.v
@@ -0,0 +1,287 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2015(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9684_if (
+
+  // device interface
+  adc_clk_in_p,
+  adc_clk_in_n,
+  adc_data_in_p,
+  adc_data_in_n,
+  adc_data_or_p,
+  adc_data_or_n,
+
+  // data interface
+  adc_clk,
+  adc_rst,
+  adc_data_a,
+  adc_or_a,
+  adc_data_b,
+  adc_or_b,
+  adc_status,
+
+  // delay interface
+  delay_clk,
+  delay_rst,
+  delay_dload,
+  delay_wdata,
+  delay_rdata,
+  delay_locked,
+
+  // mmcm_rst
+  mmcm_rst,
+
+  // drp interface
+  up_clk,
+  up_rstn,
+  up_drp_sel,
+  up_drp_wr,
+  up_drp_addr,
+  up_drp_wdata,
+  up_drp_rdata,
+  up_drp_ready,
+  up_drp_locked
+);
+
+  // parameters
+  parameter DEVICE_TYPE = 0;                  // 0 - 7Series / 1 - 6Series
+  parameter IO_DELAY_GROUP = "dev_if_delay_group";
+  parameter OR_STATUS = 0;
+
+  // buffer type based on the target device
+  localparam DDR_OR_SDR_N = 1;
+
+  // IO definitions
+
+  input           adc_clk_in_p;
+  input           adc_clk_in_n;
+  input   [13:0]  adc_data_in_p;
+  input   [13:0]  adc_data_in_n;
+  input           adc_data_or_p;
+  input           adc_data_or_n;
+
+  output          adc_clk;
+  input           adc_rst;
+  output  [27:0]  adc_data_a;
+  output          adc_or_a;
+  output  [27:0]  adc_data_b;
+  output          adc_or_b;
+  output          adc_status;
+
+  input           delay_clk;
+  input           delay_rst;
+  input   [14:0]  delay_dload;
+  input   [74:0]  delay_wdata;
+  output  [74:0]  delay_rdata;
+  output          delay_locked;
+
+  input           mmcm_rst;
+
+  input           up_clk;
+  input           up_rstn;
+  input           up_drp_sel;
+  input           up_drp_wr;
+  input   [11:0]  up_drp_addr;
+  input   [15:0]  up_drp_wdata;
+  output  [15:0]  up_drp_rdata;
+  output          up_drp_ready;
+  output          up_drp_locked;
+
+  // internal registers
+
+  reg             adc_status    = 'd0;
+  reg             adc_status_m1 = 'd0;
+
+  // internal signals
+
+  wire            adc_clk_in;
+  wire            adc_div_clk;
+  wire  [ 1:0]    adc_data_or_a_s;
+  wire  [ 1:0]    adc_data_or_b_s;
+
+  genvar          l_inst;
+
+  // adc_clk is 1:2 of the sampling clock
+  // f_max = 250 MHz
+
+  assign  adc_clk = adc_div_clk;
+
+  // data interface
+
+  ad_serdes_in #(
+    .DEVICE_TYPE(DEVICE_TYPE),
+    .IODELAY_CTRL(1),
+    .IODELAY_GROUP(IO_DELAY_GROUP),
+    .DDR_OR_SDR_N(DDR_OR_SDR_N),
+    .DATA_WIDTH(4))
+  i_adc_data (
+    .rst(adc_rst),
+    .clk(adc_clk_in),
+    .div_clk(adc_div_clk),
+    .data_s0(adc_data_b[(1*14)]),
+    .data_s1(adc_data_a[(1*14)]),
+    .data_s2(adc_data_b[(0*14)]),
+    .data_s3(adc_data_a[(0*14)]),
+    .data_s4(),
+    .data_s5(),
+    .data_s6(),
+    .data_s7(),
+    .data_in_p(adc_data_in_p[0]),
+    .data_in_n(adc_data_in_n[0]),
+    .up_clk (up_clk),
+    .up_dld (delay_dload[0]),
+    .up_dwdata (delay_wdata[4:0]),
+    .up_drdata (delay_rdata[4:0]),
+    .delay_clk(delay_clk),
+    .delay_rst(delay_rst),
+    .delay_locked(delay_locked));
+
+  generate
+  for (l_inst = 1; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
+    ad_serdes_in #(
+      .DEVICE_TYPE(DEVICE_TYPE),
+      .IODELAY_CTRL(0),
+      .IODELAY_GROUP(IO_DELAY_GROUP),
+      .DDR_OR_SDR_N(DDR_OR_SDR_N),
+      .DATA_WIDTH(4))
+    i_adc_data (
+      .rst(adc_rst),
+      .clk(adc_clk_in),
+      .div_clk(adc_div_clk),
+      .data_s0(adc_data_b[(1*14)+l_inst]),
+      .data_s1(adc_data_a[(1*14)+l_inst]),
+      .data_s2(adc_data_b[(0*14)+l_inst]),
+      .data_s3(adc_data_a[(0*14)+l_inst]),
+      .data_s4(),
+      .data_s5(),
+      .data_s6(),
+      .data_s7(),
+      .data_in_p(adc_data_in_p[l_inst]),
+      .data_in_n(adc_data_in_n[l_inst]),
+      .up_clk (up_clk),
+      .up_dld (delay_dload[l_inst]),
+      .up_dwdata (delay_wdata[((l_inst*5)+4):(l_inst*5)]),
+      .up_drdata (delay_rdata[((l_inst*5)+4):(l_inst*5)]),
+      .delay_clk(delay_clk),
+      .delay_rst(delay_rst),
+      .delay_locked());
+    end
+  endgenerate
+
+  generate if (OR_STATUS == 1) begin
+
+    ad_serdes_in #(
+      .DEVICE_TYPE(DEVICE_TYPE),
+      .IODELAY_CTRL(0),
+      .IODELAY_GROUP(IO_DELAY_GROUP),
+      .DDR_OR_SDR_N(DDR_OR_SDR_N),
+      .DATA_WIDTH(4))
+    i_adc_or (
+      .rst(adc_rst),
+      .clk(adc_clk_in),
+      .div_clk(adc_div_clk),
+      .data_s0(adc_data_or_b_s[1]),
+      .data_s1(adc_data_or_a_s[1]),
+      .data_s2(adc_data_or_b_s[0]),
+      .data_s3(adc_data_or_a_s[0]),
+      .data_s4(),
+      .data_s5(),
+      .data_s6(),
+      .data_s7(),
+      .data_in_p(adc_data_or_p),
+      .data_in_n(adc_data_or_n),
+      .up_clk (up_clk),
+      .up_dld (delay_dload[14]),
+      .up_dwdata (delay_wdata[74:70]),
+      .up_drdata (delay_rdata[74:70]),
+      .delay_clk(delay_clk),
+      .delay_rst(delay_rst),
+      .delay_locked());
+
+    assign adc_or_a = adc_data_or_a_s[0] | adc_data_or_a_s[1];
+    assign adc_or_b = adc_data_or_b_s[0] | adc_data_or_b_s[1];
+
+  end else begin
+
+    assign adc_or_a = 1'b0;
+    assign adc_or_b = 1'b0;
+
+  end
+  endgenerate
+
+  // clock input buffers and MMCM_OR_BUFR_N
+
+  ad_serdes_clk #(
+    .MMCM_DEVICE_TYPE (DEVICE_TYPE),
+    .MMCM_CLKIN_PERIOD (2),
+    .MMCM_VCO_DIV (6),
+    .MMCM_VCO_MUL (12),
+    .MMCM_CLK0_DIV (2),
+    .MMCM_CLK1_DIV (4))
+  i_serdes_clk (
+    .mmcm_rst (mmcm_rst),
+    .clk_in_p (adc_clk_in_p),
+    .clk_in_n (adc_clk_in_n),
+    .clk (adc_clk_in),
+    .div_clk (adc_div_clk),
+    .up_clk (up_clk),
+    .up_rstn (up_rstn),
+    .up_drp_sel (up_drp_sel),
+    .up_drp_wr (up_drp_wr),
+    .up_drp_addr (up_drp_addr),
+    .up_drp_wdata (up_drp_wdata),
+    .up_drp_rdata (up_drp_rdata),
+    .up_drp_ready (up_drp_ready),
+    .up_drp_locked (up_drp_locked));
+
+  // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
+  always @(posedge adc_div_clk) begin
+    if(adc_rst == 1'b1) begin
+      adc_status_m1 <= 1'b0;
+      adc_status <= 1'b0;
+    end else begin
+      adc_status_m1 <= up_drp_locked;
+      adc_status <= adc_status_m1;
+    end
+  end
+
+endmodule
diff --git a/library/axi_ad9684/axi_ad9684_ip.tcl b/library/axi_ad9684/axi_ad9684_ip.tcl
new file mode 100644
index 000000000..828ce234b
--- /dev/null
+++ b/library/axi_ad9684/axi_ad9684_ip.tcl
@@ -0,0 +1,38 @@
+
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_ad9684
+adi_ip_files axi_ad9684 [list \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/ad_serdes_in.v" \
+  "$ad_hdl_dir/library/common/ad_serdes_clk.v" \
+  "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
+  "$ad_hdl_dir/library/common/ad_datafmt.v" \
+  "$ad_hdl_dir/library/common/ad_pnmon.v" \
+  "$ad_hdl_dir/library/common/up_xfer_status.v" \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_clock_mon.v" \
+  "$ad_hdl_dir/library/common/up_delay_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_adc_common.v" \
+  "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
+  "axi_ad9684_pnmon.v" \
+  "axi_ad9684_if.v" \
+  "axi_ad9684_channel.v" \
+  "axi_ad9684_constr.xdc" \
+  "axi_ad9684.v"]
+
+adi_ip_properties axi_ad9684
+
+adi_ip_constraints axi_ad9684 [list \
+  "axi_ad9684_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc"]
+
+set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
+
+ipx::save_core [ipx::current_core]
diff --git a/library/axi_ad9684/axi_ad9684_pnmon.v b/library/axi_ad9684/axi_ad9684_pnmon.v
new file mode 100644
index 000000000..2936c2cb4
--- /dev/null
+++ b/library/axi_ad9684/axi_ad9684_pnmon.v
@@ -0,0 +1,186 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2015(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// PN monitors
+
+`timescale 1ns/100ps
+
+module axi_ad9684_pnmon (
+
+  // adc interface
+
+  adc_clk,
+  adc_data,
+
+  // pn out of sync and error
+
+  adc_pn_oos,
+  adc_pn_err,
+
+  // processor interface PN9 (0x0), PN23 (0x1)
+
+  adc_pnseq_sel);
+
+  // adc interface
+
+  input           adc_clk;
+  input   [27:0]  adc_data;
+
+  // pn out of sync and error
+
+  output          adc_pn_oos;
+  output          adc_pn_err;
+
+  // processor interface PN9 (0x0), PN23 (0x1)
+
+  input   [ 3:0]  adc_pnseq_sel;
+
+  // internal registers
+
+  reg     [27:0]  adc_pn_data_in = 'd0;
+  reg     [27:0]  adc_pn_data_pn = 'd0;
+
+  // internal signals
+
+  wire    [27:0]  adc_pn_data_pn_s;
+
+  // PN23 function
+
+  function [27:0] pn23;
+    input [27:0] din;
+    reg   [27:0] dout;
+    begin
+      dout[27] = din[22] ^ din[17];
+      dout[26] = din[21] ^ din[16];
+      dout[25] = din[20] ^ din[15];
+      dout[24] = din[19] ^ din[14];
+      dout[23] = din[18] ^ din[13];
+      dout[22] = din[17] ^ din[12];
+      dout[21] = din[16] ^ din[11];
+      dout[20] = din[15] ^ din[10];
+      dout[19] = din[14] ^ din[ 9];
+      dout[18] = din[13] ^ din[ 8];
+      dout[17] = din[12] ^ din[ 7];
+      dout[16] = din[11] ^ din[ 6];
+      dout[15] = din[10] ^ din[ 5];
+      dout[14] = din[ 9] ^ din[ 4];
+      dout[13] = din[ 8] ^ din[ 3];
+      dout[12] = din[ 7] ^ din[ 2];
+      dout[11] = din[ 6] ^ din[ 1];
+      dout[10] = din[ 5] ^ din[ 0];
+      dout[ 9] = din[ 4] ^ din[22] ^ din[17];
+      dout[ 8] = din[ 3] ^ din[21] ^ din[16];
+      dout[ 7] = din[ 2] ^ din[20] ^ din[15];
+      dout[ 6] = din[ 1] ^ din[19] ^ din[14];
+      dout[ 5] = din[ 0] ^ din[18] ^ din[13];
+      dout[ 4] = din[22] ^ din[12];
+      dout[ 3] = din[21] ^ din[11];
+      dout[ 2] = din[20] ^ din[10];
+      dout[ 1] = din[19] ^ din[ 9];
+      dout[ 0] = din[18] ^ din[ 8];
+      pn23 = dout;
+    end
+  endfunction
+
+  // PN9 function
+
+  function [27:0] pn9;
+    input [27:0] din;
+    reg   [27:0] dout;
+    begin
+      dout[27] = din[ 8] ^ din[ 4];
+      dout[26] = din[ 7] ^ din[ 3];
+      dout[25] = din[ 6] ^ din[ 2];
+      dout[24] = din[ 5] ^ din[ 1];
+      dout[23] = din[ 4] ^ din[ 0];
+      dout[22] = din[ 3] ^ din[ 8] ^ din[ 4];
+      dout[21] = din[ 2] ^ din[ 7] ^ din[ 3];
+      dout[20] = din[ 1] ^ din[ 6] ^ din[ 2];
+      dout[19] = din[ 0] ^ din[ 5] ^ din[ 1];
+      dout[18] = din[ 8] ^ din[ 0];
+      dout[17] = din[ 7] ^ din[ 8] ^ din[ 4];
+      dout[16] = din[ 6] ^ din[ 7] ^ din[ 3];
+      dout[15] = din[ 5] ^ din[ 6] ^ din[ 2];
+      dout[14] = din[ 4] ^ din[ 5] ^ din[ 1];
+      dout[13] = din[ 3] ^ din[ 4] ^ din[ 0];
+      dout[12] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
+      dout[11] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
+      dout[10] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
+      dout[ 9] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
+      dout[ 8] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
+      dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
+      dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
+      dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
+      dout[ 4] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
+      dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
+      dout[ 2] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
+      dout[ 1] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
+      dout[ 0] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
+      pn9 = dout;
+    end
+  endfunction
+
+  // pn sequence select
+
+  assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
+
+  always @(posedge adc_clk) begin
+    adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0],
+                        ~adc_data[27], adc_data[26:14]};
+    if (adc_pnseq_sel == 4'd0) begin
+      adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
+    end else begin
+      adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
+    end
+  end
+
+  // pn oos & pn err
+
+  ad_pnmon #(.DATA_WIDTH(28)) i_pnmon (
+    .adc_clk (adc_clk),
+    .adc_valid_in (1'b1),
+    .adc_data_in (adc_pn_data_in),
+    .adc_data_pn (adc_pn_data_pn),
+    .adc_pn_oos (adc_pn_oos),
+    .adc_pn_err (adc_pn_err));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+

From d1e638349b129d324b4f15e7b99a3084cfbace0b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 19 Jan 2016 11:18:00 +0200
Subject: [PATCH 053/972] ad_serdes_clk : The reference clock selection line
 should by tied to 1

Just the CLKIN1 is used in the MMCM.
---
 library/common/ad_serdes_clk.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/common/ad_serdes_clk.v b/library/common/ad_serdes_clk.v
index 6adb1811f..7022ae785 100644
--- a/library/common/ad_serdes_clk.v
+++ b/library/common/ad_serdes_clk.v
@@ -115,6 +115,7 @@ module ad_serdes_clk (
     .MMCM_CLK1_DIV (MMCM_CLK1_DIV))
   i_mmcm_drp (
     .clk (clk_in_s),
+    .clk_sel (1'b1),
     .mmcm_rst (mmcm_rst),
     .mmcm_clk_0 (clk),
     .mmcm_clk_1 (div_clk),

From 8c69c9d2ce821116aecc640a64992e5aedf872ca Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 19 Jan 2016 11:20:35 +0200
Subject: [PATCH 054/972] daq1_zc706 : Update the project

+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
---
 projects/daq1/common/daq1_bd.tcl      | 314 +++++++++-----------------
 projects/daq1/common/daq1_spi.v       |  45 ++--
 projects/daq1/cpld/daq1_cpld.v        |  15 +-
 projects/daq1/zc706/system_constr.xdc | 139 ++++++------
 projects/daq1/zc706/system_top.v      | 291 ++++++------------------
 5 files changed, 291 insertions(+), 513 deletions(-)

diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl
index 1dd1448a8..ddb6557e1 100644
--- a/projects/daq1/common/daq1_bd.tcl
+++ b/projects/daq1/common/daq1_bd.tcl
@@ -1,234 +1,138 @@
 
-# daq1
+# ad9122 interface
 
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir I rx_sysref
-create_bd_port -dir I -from 1 -to 0 rx_data_p
-create_bd_port -dir I -from 1 -to 0 rx_data_n
+create_bd_port -dir I dac_clk_in_p
+create_bd_port -dir I dac_clk_in_n
+create_bd_port -dir O dac_clk_out_p
+create_bd_port -dir O dac_clk_out_n
+create_bd_port -dir O dac_frame_out_p
+create_bd_port -dir O dac_frame_out_n
+create_bd_port -dir O -from 15 -to 0 dac_data_out_p
+create_bd_port -dir O -from 15 -to 0 dac_data_out_n
 
-create_bd_port -dir O dac_clk
-create_bd_port -dir O dac_valid_0
-create_bd_port -dir O dac_enable_0
-create_bd_port -dir I -from 63 -to 0 dac_ddata_0
-create_bd_port -dir O dac_valid_1
-create_bd_port -dir O dac_enable_1
-create_bd_port -dir I -from 63 -to 0 dac_ddata_1
-create_bd_port -dir I dac_drd
-create_bd_port -dir O -from 127 -to 0 dac_ddata
+# ad9684 interface
 
-create_bd_port -dir O adc_clk
-create_bd_port -dir O adc_enable_a
-create_bd_port -dir O adc_valid_a
-create_bd_port -dir O -from 31 -to 0 adc_data_a
-create_bd_port -dir O adc_enable_b
-create_bd_port -dir O adc_valid_b
-create_bd_port -dir O -from 31 -to 0 adc_data_b
-create_bd_port -dir I adc_dwr
-create_bd_port -dir I adc_dsync
-create_bd_port -dir I -from 63 -to 0 adc_ddata
+create_bd_port -dir I adc_clk_in_p
+create_bd_port -dir I adc_clk_in_n
+create_bd_port -dir I -from 13 -to 0 adc_data_in_p
+create_bd_port -dir I -from 13 -to 0 adc_data_in_n
 
-create_bd_port -dir I tx_ref_clk_p
-create_bd_port -dir I tx_ref_clk_n
-create_bd_port -dir O tx_clk_p
-create_bd_port -dir O tx_clk_n
-create_bd_port -dir O tx_frame_p
-create_bd_port -dir O tx_frame_n
-create_bd_port -dir O -from 15 -to 0 tx_data_p
-create_bd_port -dir O -from 15 -to 0 tx_data_n
+# daq1 irq
+
+create_bd_port -dir I daq1_irq
 
 # dac peripherals
 
-create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core
+set axi_ad9122_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core]
 
-create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma
-set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.ID {1}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_CYCLIC {1}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_ad9122_dma]
+set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma
+set_property -dict [list CONFIG.ID {0}] $axi_ad9122_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9122_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9122_dma
+set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9122_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma
+set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9122_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma
+
+set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $util_upack_ad9122
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_upack_ad9122
 
 # adc peripherals
 
-set axi_ad9250_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_core]
+set axi_ad9684_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9684:1.0 axi_ad9684_core]
+set_property -dict [list CONFIG.OR_STATUS {0}] $axi_ad9684_core
 
-set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9250_jesd]
-set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
-set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd
+set axi_ad9684_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9684_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9684_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9684_dma
+set_property -dict [list CONFIG.ID {1}] $axi_ad9684_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9684_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9684_dma
+set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9684_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9684_dma
+set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9684_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9684_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9684_dma
 
-set axi_ad9250_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_dma]
-set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_dma
-set_property -dict [list CONFIG.ID {0}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_dma
-
-# dac/adc common gt/gpio
-
-set axi_daq1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq1_gt]
-set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {2}] $axi_daq1_gt
-set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {2}] $axi_daq1_gt
-set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {2}] $axi_daq1_gt
-set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_daq1_gt
-set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_daq1_gt
-set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {10}] $axi_daq1_gt
-set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {10}] $axi_daq1_gt
-set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_daq1_gt
-set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_daq1_gt
-
-# additions to default configuration
-
-set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-
-# connections (gt)
-
-ad_connect  rx_ref_clk  axi_daq1_gt/ref_clk_c
-ad_connect  rx_data_p   axi_daq1_gt/rx_data_p
-ad_connect  rx_data_n   axi_daq1_gt/rx_data_n
-ad_connect  rx_sync     axi_daq1_gt/rx_sync
-ad_connect  rx_sysref   axi_daq1_gt/rx_ext_sysref
-
-ad_connect  axi_daq1_gt/tx_clk  axi_daq1_gt/tx_clk_g
-
-# connections (adc)
-
-ad_connect  axi_daq1_gt/rx_clk_g axi_daq1_gt/rx_clk
-ad_connect  axi_daq1_gt/rx_clk_g axi_ad9250_core/rx_clk
-ad_connect  axi_daq1_gt/rx_clk_g axi_ad9250_jesd/rx_core_clk
-
-set util_bsplit_rx_gt_charisk [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_charisk]
-ad_connect  util_bsplit_rx_gt_charisk/data axi_daq1_gt/rx_gt_charisk
-ad_connect  util_bsplit_rx_gt_charisk/split_data_0 axi_ad9250_jesd/gt0_rxcharisk
-ad_connect  util_bsplit_rx_gt_charisk/split_data_1 axi_ad9250_jesd/gt1_rxcharisk
-
-set util_bsplit_gt_rxdisperr [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_gt_rxdisperr]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_gt_rxdisperr]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_gt_rxdisperr]
-ad_connect  util_bsplit_gt_rxdisperr/data axi_daq1_gt/rx_gt_disperr
-ad_connect  util_bsplit_gt_rxdisperr/split_data_0 axi_ad9250_jesd/gt0_rxdisperr
-ad_connect  util_bsplit_gt_rxdisperr/split_data_1 axi_ad9250_jesd/gt1_rxdisperr
-
-set util_bsplit_rx_gt_notintable [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_notintable]
-ad_connect  util_bsplit_rx_gt_notintable/data axi_daq1_gt/rx_gt_notintable
-ad_connect  util_bsplit_rx_gt_notintable/split_data_0 axi_ad9250_jesd/gt0_rxnotintable
-ad_connect  util_bsplit_rx_gt_notintable/split_data_1 axi_ad9250_jesd/gt1_rxnotintable
-
-set util_bsplit_rx_gt_data [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_data]
-ad_connect  util_bsplit_rx_gt_data/data axi_daq1_gt/rx_gt_data
-ad_connect  util_bsplit_rx_gt_data/split_data_0 axi_ad9250_jesd/gt0_rxdata
-ad_connect  util_bsplit_rx_gt_data/split_data_1 axi_ad9250_jesd/gt1_rxdata
-
-ad_connect  axi_daq1_gt/rx_jesd_rst  axi_ad9250_jesd/rx_reset
-ad_connect  axi_daq1_gt/rx_sysref  axi_ad9250_jesd/rx_sysref
-ad_connect  axi_daq1_gt/rx_rst_done  axi_ad9250_jesd/rx_reset_done
-ad_connect  axi_daq1_gt/rx_ip_comma_align  axi_ad9250_jesd/rxencommaalign_out
-ad_connect  axi_daq1_gt/rx_ip_sync  axi_ad9250_jesd/rx_sync
-ad_connect  axi_daq1_gt/rx_ip_sof  axi_ad9250_jesd/rx_start_of_frame
-ad_connect  axi_daq1_gt/rx_ip_data  axi_ad9250_jesd/rx_tdata
-ad_connect  axi_daq1_gt/rx_data  axi_ad9250_core/rx_data
-ad_connect  adc_clk  axi_ad9250_core/adc_clk
-ad_connect  axi_ad9250_core/adc_clk  axi_ad9250_dma/fifo_wr_clk
-ad_connect  adc_enable_a  axi_ad9250_core/adc_enable_a
-ad_connect  adc_valid_a  axi_ad9250_core/adc_valid_a
-ad_connect  adc_data_a  axi_ad9250_core/adc_data_a
-ad_connect  adc_enable_b  axi_ad9250_core/adc_enable_b
-ad_connect  adc_valid_b  axi_ad9250_core/adc_valid_b
-ad_connect  adc_data_b  axi_ad9250_core/adc_data_b
-ad_connect  axi_ad9250_core/adc_dovf  axi_ad9250_dma/fifo_wr_overflow
-ad_connect  adc_dwr  axi_ad9250_dma/fifo_wr_en
-ad_connect  adc_dsync  axi_ad9250_dma/fifo_wr_sync
-ad_connect  adc_ddata  axi_ad9250_dma/fifo_wr_din
+set util_cpack_ad9684 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9684]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_cpack_ad9684
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9684
 
 # connections (dac)
 
-ad_connect  tx_ref_clk_p  axi_ad9122_core/dac_clk_in_p
-ad_connect  tx_ref_clk_n  axi_ad9122_core/dac_clk_in_n
-ad_connect  tx_clk_p  axi_ad9122_core/dac_clk_out_p
-ad_connect  tx_clk_n  axi_ad9122_core/dac_clk_out_n
-ad_connect  tx_frame_p  axi_ad9122_core/dac_frame_out_p
-ad_connect  tx_frame_n  axi_ad9122_core/dac_frame_out_n
-ad_connect  tx_data_p  axi_ad9122_core/dac_data_out_p
-ad_connect  tx_data_n  axi_ad9122_core/dac_data_out_n
-ad_connect  dac_clk  axi_ad9122_core/dac_div_clk
-ad_connect  axi_ad9122_core/dac_div_clk  axi_ad9122_dma/fifo_rd_clk
-ad_connect  dac_valid_0  axi_ad9122_core/dac_valid_0
-ad_connect  dac_enable_0  axi_ad9122_core/dac_enable_0
-ad_connect  dac_ddata_0  axi_ad9122_core/dac_ddata_0
-ad_connect  dac_valid_1  axi_ad9122_core/dac_valid_1
-ad_connect  dac_enable_1  axi_ad9122_core/dac_enable_1
-ad_connect  dac_ddata_1  axi_ad9122_core/dac_ddata_1
-ad_connect  dac_drd  axi_ad9122_dma/fifo_rd_en
-ad_connect  dac_ddata  axi_ad9122_dma/fifo_rd_dout
-ad_connect  axi_ad9122_core/dac_dunf  axi_ad9122_dma/fifo_rd_underflow
+ad_connect  dac_clk axi_ad9122_core/dac_div_clk
+ad_connect  dac_clk axi_ad9122_dma/fifo_rd_clk
+ad_connect  dac_clk util_upack_ad9122/dac_clk
 
-ad_connect  sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
-ad_connect  sys_cpu_resetn axi_ad9250_dma/m_dest_axi_aresetn
+ad_connect  dac_clk_in_p axi_ad9122_core/dac_clk_in_p
+ad_connect  dac_clk_in_n axi_ad9122_core/dac_clk_in_n
+ad_connect  dac_clk_out_p axi_ad9122_core/dac_clk_out_p
+ad_connect  dac_clk_out_n axi_ad9122_core/dac_clk_out_n
+ad_connect  dac_frame_out_p axi_ad9122_core/dac_frame_out_p
+ad_connect  dac_frame_out_n axi_ad9122_core/dac_frame_out_n
+ad_connect  dac_data_out_p axi_ad9122_core/dac_data_out_p
+ad_connect  dac_data_out_n axi_ad9122_core/dac_data_out_n
 
+ad_connect  axi_ad9122_core/dac_enable_0 util_upack_ad9122/dac_enable_0
+ad_connect  axi_ad9122_core/dac_ddata_0 util_upack_ad9122/dac_data_0
+ad_connect  axi_ad9122_core/dac_valid_0 util_upack_ad9122/dac_valid_0
+ad_connect  axi_ad9122_core/dac_enable_1 util_upack_ad9122/dac_enable_1
+ad_connect  axi_ad9122_core/dac_ddata_1 util_upack_ad9122/dac_data_1
+ad_connect  axi_ad9122_core/dac_valid_1 util_upack_ad9122/dac_valid_1
+ad_connect  axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow
 
-# interconnect (cpu)
+ad_connect  util_upack_ad9122/dac_valid axi_ad9122_dma/fifo_rd_en
+ad_connect  util_upack_ad9122/dac_data axi_ad9122_dma/fifo_rd_dout
+ad_connect  util_upack_ad9122/dac_sync axi_ad9122_core/dac_sync_in
 
-ad_cpu_interconnect   0x44A60000 axi_daq1_gt
-ad_cpu_interconnect   0x44A00000 axi_ad9122_core
-ad_cpu_interconnect   0x7c400000 axi_ad9122_dma
-ad_cpu_interconnect   0x44A10000 axi_ad9250_core
-ad_cpu_interconnect   0x7c420000 axi_ad9250_dma
-ad_cpu_interconnect   0x44A91000 axi_ad9250_jesd
+# connections (adc)
 
-# memory interconnects
+ad_connect  adc_clk axi_ad9684_core/adc_clk
+ad_connect  sys_200m_clk axi_ad9684_core/delay_clk
+ad_connect  adc_clk axi_ad9684_dma/fifo_wr_clk
+ad_connect  adc_clk util_cpack_ad9684/adc_clk
 
+ad_connect  adc_clk_in_p axi_ad9684_core/adc_clk_in_p
+ad_connect  adc_clk_in_n axi_ad9684_core/adc_clk_in_n
+ad_connect  axi_ad9684_core/adc_data_or_p GND
+ad_connect  axi_ad9684_core/adc_data_or_n GND
+ad_connect  adc_data_in_p axi_ad9684_core/adc_data_in_p
+ad_connect  adc_data_in_n axi_ad9684_core/adc_data_in_n
+
+ad_connect  axi_ad9684_core/adc_rst util_cpack_ad9684/adc_rst
+ad_connect  axi_ad9684_core/adc_enable_0 util_cpack_ad9684/adc_enable_0
+ad_connect  axi_ad9684_core/adc_valid_0 util_cpack_ad9684/adc_valid_0
+ad_connect  axi_ad9684_core/adc_data_0 util_cpack_ad9684/adc_data_0
+ad_connect  axi_ad9684_core/adc_enable_1 util_cpack_ad9684/adc_enable_1
+ad_connect  axi_ad9684_core/adc_valid_1 util_cpack_ad9684/adc_valid_1
+ad_connect  axi_ad9684_core/adc_data_1 util_cpack_ad9684/adc_data_1
+ad_connect  axi_ad9684_core/adc_dovf axi_ad9684_dma/fifo_wr_overflow
+
+ad_connect  util_cpack_ad9684/adc_valid axi_ad9684_dma/fifo_wr_en
+ad_connect  util_cpack_ad9684/adc_data axi_ad9684_dma/fifo_wr_din
+ad_connect  util_cpack_ad9684/adc_sync axi_ad9684_dma/fifo_wr_sync
+
+# memory interconnect
+
+ad_cpu_interconnect 0x44A00000 axi_ad9122_core
+ad_cpu_interconnect 0x44A20000 axi_ad9684_core
+ad_cpu_interconnect 0x44A40000 axi_ad9122_dma
+ad_cpu_interconnect 0x44A60000 axi_ad9684_dma
 ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
-ad_mem_hp1_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
+ad_mem_hp1_interconnect sys_200m_clk axi_ad9684_dma/m_dest_axi
 ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
-ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_dma/m_dest_axi
-ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_daq1_gt/m_axi
+ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
+
+ad_connect  sys_cpu_resetn axi_ad9684_dma/m_dest_axi_aresetn
+ad_connect  sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
 
 # interrupts
 
-ad_cpu_interrupt ps-13 mb-12  axi_ad9250_dma/irq
-ad_cpu_interrupt ps-12 mb-13  axi_ad9122_dma/irq
-
-# ila
-
-set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_jesd_rx_mon]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {7}   ] $ila_jesd_rx_mon
-set_property -dict [list CONFIG.C_PROBE0_WIDTH  {64}  ] $ila_jesd_rx_mon
-set_property -dict [list CONFIG.C_PROBE1_WIDTH  {1}   ] $ila_jesd_rx_mon
-set_property -dict [list CONFIG.C_PROBE2_WIDTH  {1}   ] $ila_jesd_rx_mon
-set_property -dict [list CONFIG.C_PROBE3_WIDTH  {32}  ] $ila_jesd_rx_mon
-set_property -dict [list CONFIG.C_PROBE4_WIDTH  {1}   ] $ila_jesd_rx_mon
-set_property -dict [list CONFIG.C_PROBE5_WIDTH  {1}   ] $ila_jesd_rx_mon
-set_property -dict [list CONFIG.C_PROBE6_WIDTH  {32}  ] $ila_jesd_rx_mon
-
-ad_connect  axi_daq1_gt/rx_clk_g  ila_jesd_rx_mon/CLK
-ad_connect  axi_daq1_gt/rx_data  ila_jesd_rx_mon/PROBE0
-ad_connect  axi_ad9250_core/adc_valid_a  ila_jesd_rx_mon/PROBE1
-ad_connect  axi_ad9250_core/adc_enable_a  ila_jesd_rx_mon/PROBE2
-ad_connect  axi_ad9250_core/adc_data_a  ila_jesd_rx_mon/PROBE3
-ad_connect  axi_ad9250_core/adc_valid_b  ila_jesd_rx_mon/PROBE4
-ad_connect  axi_ad9250_core/adc_enable_a  ila_jesd_rx_mon/PROBE5
-ad_connect  axi_ad9250_core/adc_data_a  ila_jesd_rx_mon/PROBE6
+ad_cpu_interrupt ps-13 mb-12 axi_ad9122_dma/irq
+ad_cpu_interrupt ps-12 mb-13 axi_ad9684_dma/irq
+ad_cpu_interrupt ps-11 mb-14 daq1_irq
 
diff --git a/projects/daq1/common/daq1_spi.v b/projects/daq1/common/daq1_spi.v
index 4153f67bf..c9dd27123 100644
--- a/projects/daq1/common/daq1_spi.v
+++ b/projects/daq1/common/daq1_spi.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
+// Copyright 2016(c) Analog Devices, Inc.
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -48,7 +48,7 @@ module daq1_spi (
 
   // 4 wire
 
-  input   [ 2:0]  spi_csn;
+  input           spi_csn;
   input           spi_clk;
   input           spi_mosi;
   output          spi_miso;
@@ -57,11 +57,19 @@ module daq1_spi (
 
   inout           spi_sdio;
 
+  // device address
+
+  localparam  [ 7:0]  SPI_SEL_AD9684  = 8'h80;
+  localparam  [ 7:0]  SPI_SEL_AD9122  = 8'h81;
+  localparam  [ 7:0]  SPI_SEL_AD9523  = 8'h82;
+  localparam  [ 7:0]  SPI_SEL_CPLD    = 8'h83;
+
   // internal registers
 
-  reg     [ 5:0]  spi_count = 'd0;
-  reg             spi_rd_wr_n = 'd0;
-  reg             spi_enable = 'd0;
+  reg     [ 5:0]  spi_count = 6'b0;
+  reg             spi_rd_wr_n = 1'b0;
+  reg             spi_enable = 1'b0;
+  reg     [ 7:0]  spi_device_addr = 8'b0;
 
   // internal signals
 
@@ -75,11 +83,15 @@ module daq1_spi (
 
   always @(posedge spi_clk or posedge spi_csn_s) begin
     if (spi_csn_s == 1'b1) begin
-      spi_count <= 6'd0;
-      spi_rd_wr_n <= 1'd0;
+      spi_count <= 6'b0000000;
+      spi_rd_wr_n <= 1'b0;
+      spi_device_addr <= 8'b00000000;
     end else begin
       spi_count <= spi_count + 1'b1;
-      if (spi_count == 6'd0) begin
+      if (spi_count <= 6'd7) begin
+        spi_device_addr <= {spi_device_addr[6:0], spi_mosi};
+      end
+      if (spi_count == 6'd8) begin
         spi_rd_wr_n <= spi_mosi;
       end
     end
@@ -89,9 +101,10 @@ module daq1_spi (
     if (spi_csn_s == 1'b1) begin
       spi_enable <= 1'b0;
     end else begin
-      if (((spi_count == 6'd16) && (spi_csn[2] == 1'b0)) ||
-          ((spi_count == 6'd8)  && (spi_csn[1] == 1'b0)) ||
-          ((spi_count == 6'd16) && (spi_csn[0] == 1'b0))) begin
+      if (((spi_device_addr == SPI_SEL_AD9684) && (spi_count == 6'd24)) ||
+          ((spi_device_addr == SPI_SEL_AD9122) && (spi_count == 6'd16)) ||
+          ((spi_device_addr == SPI_SEL_AD9523) && (spi_count == 6'd24)) ||
+          ((spi_device_addr == SPI_SEL_CPLD)   && (spi_count == 6'd16))) begin
         spi_enable <= spi_rd_wr_n;
       end
     end
diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
index 8f77b4d4f..550780a78 100644
--- a/projects/daq1/cpld/daq1_cpld.v
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -113,6 +113,7 @@ module daq1_cpld (
   localparam  [ 6:0]  ADC_CONTROL_ADDR    = 7'h00;
   localparam  [ 6:0]  DAC_CONTROL_ADDR    = 7'h01;
   localparam  [ 6:0]  CLK_CONTROL_ADDR    = 7'h02;
+  localparam  [ 6:0]  IRQ_MASK_ADDR       = 7'h03;
   localparam  [ 6:0]  ADC_STATUS_ADDR     = 7'h10;
   localparam  [ 6:0]  DAC_STATUS_ADDR     = 7'h11;
   localparam  [ 6:0]  CLK_STATUS_ADDR     = 7'h12;
@@ -137,6 +138,8 @@ module daq1_cpld (
   reg           cpld_rdata_bit = 1'b0;
   reg    [ 2:0] cpld_rdata_index = 3'h0;
   reg    [ 7:0] cpld_wdata = 8'b0;
+  reg    [ 7:0] cpld_irq_mask = 8'b0;
+  reg    [ 7:0] cpld_irq = 8'b0;
 
   wire          rdnwr;
   wire          cpld_rdata_s;
@@ -199,6 +202,8 @@ module daq1_cpld (
         cpld_rdata <= dac_resetn;
       CLK_CONTROL_ADDR :
         cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn};
+      IRQ_MASK_ADDR:
+        cpld_rdata <= cpld_irq_mask;
       ADC_STATUS_ADDR  :
         cpld_rdata <= {adc_status_p, adc_fdb, adc_fda};
       DAC_STATUS_ADDR  :
@@ -235,6 +240,8 @@ module daq1_cpld (
           dac_control <= cpld_wdata;
         CLK_CONTROL_ADDR :
           clk_control <= cpld_wdata;
+        IRQ_MASK_ADDR:
+          cpld_irq_mask <= cpld_wdata;
       endcase
     end
   end
@@ -265,7 +272,13 @@ module daq1_cpld (
   assign clk_resetn = clk_control[1];
   assign clk_syncn = clk_control[2];
 
-  assign fmc_irq = dac_irqn;
+  // interrupt logic
+
+  always @(*) begin
+    cpld_irq <= {2'b00, dac_irqn, clk_status2, clk_status1, adc_status_p, adc_fdb, adc_fda};
+  end
+  
+  assign fmc_irq = |(~cpld_irq_mask & cpld_irq);
 
 endmodule
 
diff --git a/projects/daq1/zc706/system_constr.xdc b/projects/daq1/zc706/system_constr.xdc
index a4e66106a..86a25c8bc 100644
--- a/projects/daq1/zc706/system_constr.xdc
+++ b/projects/daq1/zc706/system_constr.xdc
@@ -1,77 +1,86 @@
 
 # daq1
 
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports tx_ref_clk_p]       ; ##  G06  FMC_HPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN  AG20  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports tx_ref_clk_n]       ; ##  G07  FMC_HPC_LA00_CC_N
+set_property  -dict {PACKAGE_PIN  AC28  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports dac_clk_in_p]            ; ##  G02  FMC_LPC_CLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  AD28  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports dac_clk_in_n]            ; ##  G03  FMC_LPC_CLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  AG17  IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p]                          ; ##  H4   FMC_LPC_CLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  AG16  IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n]                          ; ##  H5   FMC_LPC_CLK0_M2C_N
 
-set_property  -dict {PACKAGE_PIN  V23   IOSTANDARD LVDS_25} [get_ports tx_clk_p]                           ; ##  D20  FMC_HPC_LA17_CC_P
-set_property  -dict {PACKAGE_PIN  W24   IOSTANDARD LVDS_25} [get_ports tx_clk_n]                           ; ##  D21  FMC_HPC_LA17_CC_N
-set_property  -dict {PACKAGE_PIN  W25   IOSTANDARD LVDS_25} [get_ports tx_frame_p]                         ; ##  C22  FMC_HPC_LA18_CC_P
-set_property  -dict {PACKAGE_PIN  W26   IOSTANDARD LVDS_25} [get_ports tx_frame_n]                         ; ##  C23  FMC_HPC_LA18_CC_N
-set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVDS_25} [get_ports tx_data_p[0]]                       ; ##  H10  FMC_HPC_LA04_P
-set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVDS_25} [get_ports tx_data_n[0]]                       ; ##  H11  FMC_HPC_LA04_N
-set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVDS_25} [get_ports tx_data_p[1]]                       ; ##  D11  FMC_HPC_LA05_P
-set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVDS_25} [get_ports tx_data_n[1]]                       ; ##  D12  FMC_HPC_LA05_N
-set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVDS_25} [get_ports tx_data_p[2]]                       ; ##  C10  FMC_HPC_LA06_P
-set_property  -dict {PACKAGE_PIN  AH22  IOSTANDARD LVDS_25} [get_ports tx_data_n[2]]                       ; ##  C11  FMC_HPC_LA06_N
-set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVDS_25} [get_ports tx_data_p[3]]                       ; ##  H13  FMC_HPC_LA07_P
-set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25} [get_ports tx_data_n[3]]                       ; ##  H14  FMC_HPC_LA07_N
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVDS_25} [get_ports tx_data_p[4]]                       ; ##  G12  FMC_HPC_LA08_P
-set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVDS_25} [get_ports tx_data_n[4]]                       ; ##  G13  FMC_HPC_LA08_N
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVDS_25} [get_ports tx_data_p[5]]                       ; ##  D14  FMC_HPC_LA09_P
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVDS_25} [get_ports tx_data_n[5]]                       ; ##  D15  FMC_HPC_LA09_N
-set_property  -dict {PACKAGE_PIN  AG24  IOSTANDARD LVDS_25} [get_ports tx_data_p[6]]                       ; ##  C14  FMC_HPC_LA10_P
-set_property  -dict {PACKAGE_PIN  AG25  IOSTANDARD LVDS_25} [get_ports tx_data_n[6]]                       ; ##  C15  FMC_HPC_LA10_N
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVDS_25} [get_ports tx_data_p[7]]                       ; ##  H16  FMC_HPC_LA11_P
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVDS_25} [get_ports tx_data_n[7]]                       ; ##  H17  FMC_HPC_LA11_N
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVDS_25} [get_ports tx_data_p[8]]                       ; ##  G15  FMC_HPC_LA12_P
-set_property  -dict {PACKAGE_PIN  AF24  IOSTANDARD LVDS_25} [get_ports tx_data_n[8]]                       ; ##  G16  FMC_HPC_LA12_N
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVDS_25} [get_ports tx_data_p[9]]                       ; ##  D17  FMC_HPC_LA13_P
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVDS_25} [get_ports tx_data_n[9]]                       ; ##  D18  FMC_HPC_LA13_N
-set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD LVDS_25} [get_ports tx_data_p[10]]                      ; ##  C18  FMC_HPC_LA14_P
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVDS_25} [get_ports tx_data_n[10]]                      ; ##  C19  FMC_HPC_LA14_N
-set_property  -dict {PACKAGE_PIN  Y22   IOSTANDARD LVDS_25} [get_ports tx_data_p[11]]                      ; ##  H19  FMC_HPC_LA15_P
-set_property  -dict {PACKAGE_PIN  Y23   IOSTANDARD LVDS_25} [get_ports tx_data_n[11]]                      ; ##  H20  FMC_HPC_LA15_N
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVDS_25} [get_ports tx_data_p[12]]                      ; ##  G18  FMC_HPC_LA16_P
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVDS_25} [get_ports tx_data_n[12]]                      ; ##  G19  FMC_HPC_LA16_N
-set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVDS_25} [get_ports tx_data_p[13]]                      ; ##  H07  FMC_HPC_LA02_P
-set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVDS_25} [get_ports tx_data_n[13]]                      ; ##  H08  FMC_HPC_LA02_N
-set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVDS_25} [get_ports tx_data_p[14]]                      ; ##  D08  FMC_HPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVDS_25} [get_ports tx_data_n[14]]                      ; ##  D09  FMC_HPC_LA01_CC_N
-set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25} [get_ports tx_data_p[15]]                      ; ##  G09  FMC_HPC_LA03_P
-set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25} [get_ports tx_data_n[15]]                      ; ##  G10  FMC_HPC_LA03_N
+set_property  -dict {PACKAGE_PIN  AB27  IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p]                        ; ##  D20  FMC_LPC_LA17_CC_P
+set_property  -dict {PACKAGE_PIN  AC27  IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n]                        ; ##  D21  FMC_LPC_LA17_CC_N
 
-set_property  -dict {PACKAGE_PIN  AD10  } [get_ports rx_ref_clk_p]                                         ; ##  D04  FMC_HPC_GBTCLK0_M2C_P
-set_property  -dict {PACKAGE_PIN  AD9   } [get_ports rx_ref_clk_n]                                         ; ##  D05  FMC_HPC_GBTCLK0_M2C_N
-set_property  -dict {PACKAGE_PIN  AH10  } [get_ports rx_data_p[0]]                                         ; ##  C06  FMC_HPC_DP0_M2C_P
-set_property  -dict {PACKAGE_PIN  AH9   } [get_ports rx_data_n[0]]                                         ; ##  C07  FMC_HPC_DP0_M2C_N
-set_property  -dict {PACKAGE_PIN  AJ8   } [get_ports rx_data_p[1]]                                         ; ##  A02  FMC_HPC_DP1_M2C_P
-set_property  -dict {PACKAGE_PIN  AJ7   } [get_ports rx_data_n[1]]                                         ; ##  A03  FMC_HPC_DP1_M2C_N
-set_property  -dict {PACKAGE_PIN  T24   IOSTANDARD LVDS_25} [get_ports rx_sync_p]                          ; ##  H22  FMC_HPC_LA19_P
-set_property  -dict {PACKAGE_PIN  T25   IOSTANDARD LVDS_25} [get_ports rx_sync_n]                          ; ##  H23  FMC_HPC_LA19_N
-set_property  -dict {PACKAGE_PIN  W29   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]         ; ##  H25  FMC_HPC_LA21_P
-set_property  -dict {PACKAGE_PIN  W30   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]         ; ##  H26  FMC_HPC_LA21_N
+set_property  -dict {PACKAGE_PIN  AE27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]]                      ; ##  C22  FMC_LPC_LA18_CC_P
+set_property  -dict {PACKAGE_PIN  AF27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]]                      ; ##  C23  FMC_LPC_LA18_CC_N
+set_property  -dict {PACKAGE_PIN  AG26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]]                      ; ##  G21  FMC_LPC_LA20_P
+set_property  -dict {PACKAGE_PIN  AG27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[1]]                      ; ##  G22  FMC_LPC_LA20_N
+set_property  -dict {PACKAGE_PIN  AH26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[2]]                      ; ##  H22  FMC_LPC_LA19_P
+set_property  -dict {PACKAGE_PIN  AH27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[2]]                      ; ##  H23  FMC_LPC_LA19_N
+set_property  -dict {PACKAGE_PIN  AJ26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]]                      ; ##  D23  FMC_LPC_LA23_P
+set_property  -dict {PACKAGE_PIN  AK26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]]                      ; ##  D24  FMC_LPC_LA23_N
+set_property  -dict {PACKAGE_PIN  AK27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]]                      ; ##  G24  FMC_LPC_LA22_P
+set_property  -dict {PACKAGE_PIN  AK28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]]                      ; ##  G25  FMC_LPC_LA22_N
+set_property  -dict {PACKAGE_PIN  AH28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]]                      ; ##  H25  FMC_LPC_LA21_P
+set_property  -dict {PACKAGE_PIN  AH29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]]                      ; ##  H26  FMC_LPC_LA21_N
+set_property  -dict {PACKAGE_PIN  AJ30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]]                      ; ##  D26  FMC_LPC_LA26_P
+set_property  -dict {PACKAGE_PIN  AK30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]]                      ; ##  D27  FMC_LPC_LA26_N
+set_property  -dict {PACKAGE_PIN  AF29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]]                      ; ##  G27  FMC_LPC_LA25_P
+set_property  -dict {PACKAGE_PIN  AG29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]]                      ; ##  G28  FMC_LPC_LA25_N
+set_property  -dict {PACKAGE_PIN  AF30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]]                      ; ##  H28  FMC_LPC_LA24_P
+set_property  -dict {PACKAGE_PIN  AG30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]]                      ; ##  H29  FMC_LPC_LA24_N
+set_property  -dict {PACKAGE_PIN  AJ28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]]                      ; ##  C26  FMC_LPC_LA27_P
+set_property  -dict {PACKAGE_PIN  AJ29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]]                      ; ##  C27  FMC_LPC_LA27_N
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]]                     ; ##  G30  FMC_LPC_LA29_P
+set_property  -dict {PACKAGE_PIN  AF25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]]                     ; ##  G31  FMC_LPC_LA29_N
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]]                     ; ##  H31  FMC_LPC_LA28_P
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]]                     ; ##  H32  FMC_LPC_LA28_N
+set_property  -dict {PACKAGE_PIN  AC29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]]                     ; ##  G33  FMC_LPC_LA31_P
+set_property  -dict {PACKAGE_PIN  AD29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]]                     ; ##  G34  FMC_LPC_LA31_N
+set_property  -dict {PACKAGE_PIN  AB29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]]                     ; ##  H34  FMC_LPC_LA30_P
+set_property  -dict {PACKAGE_PIN  AB30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]]                     ; ##  H35  FMC_LPC_LA30_N
+set_property  -dict {PACKAGE_PIN   Y30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]]                     ; ##  G09  FMC_LPC_LA33_P
+set_property  -dict {PACKAGE_PIN  AA30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]]                     ; ##  G10  FMC_LPC_LA33_N
+set_property  -dict {PACKAGE_PIN   Y26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]]                     ; ##  H37  FMC_LPC_LA32_P
+set_property  -dict {PACKAGE_PIN   Y27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]]                     ; ##  H38  FMC_LPC_LA32_N
 
-set_property  -dict {PACKAGE_PIN  U29   IOSTANDARD LVCMOS25} [get_ports spi_csn_clk]                       ; ##  G28  FMC_HPC_LA25_N
-set_property  -dict {PACKAGE_PIN  T29   IOSTANDARD LVCMOS25} [get_ports spi_csn_dac]                       ; ##  G27  FMC_HPC_LA25_P
-set_property  -dict {PACKAGE_PIN  U30   IOSTANDARD LVCMOS25} [get_ports spi_csn_adc]                       ; ##  H29  FMC_HPC_LA24_N
-set_property  -dict {PACKAGE_PIN  P26   IOSTANDARD LVCMOS25} [get_ports spi_clk]                           ; ##  D24  FMC_HPC_LA23_N
-set_property  -dict {PACKAGE_PIN  P25   IOSTANDARD LVCMOS25} [get_ports spi_sdio]                          ; ##  D23  FMC_HPC_LA23_P
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_clk_in_p]            ; ##  G06  FMC_LPC_LA00_CC_P
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_clk_in_n]            ; ##  G07  FMC_LPC_LA00_CC_N
 
-set_property  -dict {PACKAGE_PIN  W28   IOSTANDARD LVCMOS25} [get_ports gpio_resetn]                       ; ##  G25  FMC_HPC_LA22_N
-set_property  -dict {PACKAGE_PIN  R30   IOSTANDARD LVCMOS25} [get_ports gpio_clkd_syncn]                   ; ##  H32  FMC_HPC_LA28_N
-set_property  -dict {PACKAGE_PIN  P30   IOSTANDARD LVCMOS25} [get_ports gpio_clkd_pdn]                     ; ##  H31  FMC_HPC_LA28_P
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]        ; ##  G12  FMC_LPC_LA08_P
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]        ; ##  G13  FMC_LPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]        ; ##  C18  FMC_LPC_LA14_P
+set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[1]]        ; ##  C19  FMC_LPC_LA14_N
+set_property  -dict {PACKAGE_PIN  AH17  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[2]]        ; ##  D17  FMC_LPC_LA13_P
+set_property  -dict {PACKAGE_PIN  AH16  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[2]]        ; ##  D18  FMC_LPC_LA13_N
+set_property  -dict {PACKAGE_PIN  AJ16  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[3]]        ; ##  H16  FMC_LPC_LA11_P
+set_property  -dict {PACKAGE_PIN  AK16  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[3]]        ; ##  H17  FMC_LPC_LA11_N
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[4]]        ; ##  G15  FMC_LPC_LA12_P
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[4]]        ; ##  G16  FMC_LPC_LA12_N
+set_property  -dict {PACKAGE_PIN  AH14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[5]]        ; ##  D14  FMC_LPC_LA09_P
+set_property  -dict {PACKAGE_PIN  AH13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[5]]        ; ##  D15  FMC_LPC_LA09_N
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[6]]        ; ##  H13  FMC_LPC_LA07_P
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[6]]        ; ##  H14  FMC_LPC_LA07_N
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]        ; ##  C14  FMC_LPC_LA10_P
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]        ; ##  C15  FMC_LPC_LA10_N
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[8]]        ; ##  D11  FMC_LPC_LA05_P
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[8]]        ; ##  D12  FMC_LPC_LA05_N
+set_property  -dict {PACKAGE_PIN  AJ15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[9]]        ; ##  H10  FMC_LPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AK15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[9]]        ; ##  H11  FMC_LPC_LA04_N
+set_property  -dict {PACKAGE_PIN  AG12  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[10]]       ; ##  G09  FMC_LPC_LA03_P
+set_property  -dict {PACKAGE_PIN  AH12  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[10]]       ; ##  G10  FMC_LPC_LA03_N
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[11]]       ; ##  C10  FMC_LPC_LA06_P
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[11]]       ; ##  C11  FMC_LPC_LA06_N
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[12]]       ; ##  H07  FMC_LPC_LA02_P
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[12]]       ; ##  H08  FMC_LPC_LA02_N
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]       ; ##  D08  FMC_LPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  AG15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]       ; ##  D09  FMC_LPC_LA01_CC_N
 
-set_property  -dict {PACKAGE_PIN  T28   IOSTANDARD LVCMOS25} [get_ports gpio_clkd_status[1]]               ; ##  D27  FMC_HPC_LA26_N
-set_property  -dict {PACKAGE_PIN  R28   IOSTANDARD LVCMOS25} [get_ports gpio_clkd_status[0]]               ; ##  D26  FMC_HPC_LA26_P
-set_property  -dict {PACKAGE_PIN  V27   IOSTANDARD LVCMOS25} [get_ports gpio_dac_irqn]                     ; ##  G24  FMC_HPC_LA22_P
-set_property  -dict {PACKAGE_PIN  V28   IOSTANDARD LVCMOS25} [get_ports gpio_adc_fda]                      ; ##  C26  FMC_HPC_LA27_P
-set_property  -dict {PACKAGE_PIN  V29   IOSTANDARD LVCMOS25} [get_ports gpio_adc_fdb]                      ; ##  C27  FMC_HPC_LA27_N
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25} [get_ports cpld_sclk]                              ; ##  H19  FMC_LPC_LA15_P
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25} [get_ports cpld_csn]                               ; ##  H20  FMC_LPC_LA15_N
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports cpld_sdio]                              ; ##  G18  FMC_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports daq1_irq]                               ; ##  G19  FMC_LPC_LA16_N
 
 # clocks
 
-create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
-create_clock -name rx_ref_clk   -period  4.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  8.00 [get_nets i_system_wrapper/system_i/axi_ad9122_dac_div_clk]
-create_clock -name rx_div_clk   -period  8.00 [get_nets i_system_wrapper/system_i/axi_daq1_gt_rx_clk]
+create_clock -name dac_clk_in   -period  2.00 [get_ports dac_clk_in_p]
+create_clock -name adc_clk_in   -period  2.00 [get_ports adc_clk_in_p]
 
diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v
index 08e1d63e8..c3d8dfcdc 100644
--- a/projects/daq1/zc706/system_top.v
+++ b/projects/daq1/zc706/system_top.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
+// Copyright 2016(c) Analog Devices, Inc.
 //
 // All rights reserved.
 //
@@ -77,38 +77,26 @@ module system_top (
   iic_scl,
   iic_sda,
 
-  rx_ref_clk_p,
-  rx_ref_clk_n,
-  rx_sysref_p,
-  rx_sysref_n,
-  rx_sync_p,
-  rx_sync_n,
-  rx_data_p,
-  rx_data_n,
+  dac_clk_in_p,
+  dac_clk_in_n,
+  dac_clk_out_p,
+  dac_clk_out_n,
+  dac_frame_out_p,
+  dac_frame_out_n,
+  dac_data_out_p,
+  dac_data_out_n,
 
-  tx_ref_clk_p,
-  tx_ref_clk_n,
-  tx_clk_p,
-  tx_clk_n,
-  tx_frame_p,
-  tx_frame_n,
-  tx_data_p,
-  tx_data_n,
+  adc_clk_in_p,
+  adc_clk_in_n,
+  adc_data_in_p,
+  adc_data_in_n,
 
-  gpio_adc_fdb,
-  gpio_adc_fda,
-  gpio_dac_irqn,
-  gpio_clkd_status,
+  daq1_irq,
 
-  gpio_clkd_pdn,
-  gpio_clkd_syncn,
-  gpio_resetn,
-
-  spi_csn_clk,
-  spi_csn_dac,
-  spi_csn_adc,
-  spi_clk,
-  spi_sdio);
+  cpld_sclk,
+  cpld_csn,
+  cpld_sdio
+);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -146,176 +134,49 @@ module system_top (
   inout           iic_scl;
   inout           iic_sda;
 
-  input           rx_ref_clk_p;
-  input           rx_ref_clk_n;
-  input           rx_sysref_p;
-  input           rx_sysref_n;
-  output          rx_sync_p;
-  output          rx_sync_n;
-  input   [ 1:0]  rx_data_p;
-  input   [ 1:0]  rx_data_n;
+  input           dac_clk_in_p;
+  input           dac_clk_in_n;
+  output          dac_clk_out_p;
+  output          dac_clk_out_n;
+  output          dac_frame_out_p;
+  output          dac_frame_out_n;
+  output  [15:0]  dac_data_out_p;
+  output  [15:0]  dac_data_out_n;
 
-  input           tx_ref_clk_p;
-  input           tx_ref_clk_n;
-  output          tx_clk_p;
-  output          tx_clk_n;
-  output          tx_frame_p;
-  output          tx_frame_n;
-  output  [15:0]  tx_data_p;
-  output  [15:0]  tx_data_n;
+  input           adc_clk_in_p;
+  input           adc_clk_in_n;
+  input  [13:0]   adc_data_in_p;
+  input  [13:0]   adc_data_in_n;
 
-  inout           gpio_adc_fdb;
-  inout           gpio_adc_fda;
-  inout           gpio_dac_irqn;
-  inout   [ 1:0]  gpio_clkd_status;
+  input           daq1_irq;
 
-  inout           gpio_clkd_pdn;
-  inout           gpio_clkd_syncn;
-  inout           gpio_resetn;
-
-  output          spi_csn_clk;
-  output          spi_csn_dac;
-  output          spi_csn_adc;
-  output          spi_clk;
-  inout           spi_sdio;
-
-  // internal registers
-
-  reg             dac_drd = 'd0;
-  reg    [63:0]   dac_ddata_0 = 'd0;
-  reg    [63:0]   dac_ddata_1 = 'd0;
-  reg             adc_dwr    = 'd0;
-  reg    [63:0]   adc_ddata  = 'd0;
+  output          cpld_sclk;
+  output          cpld_csn;
+  inout           cpld_sdio;
 
   // internal signals
 
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
-  wire            rx_ref_clk;
-  wire            rx_sysref;
-  wire            rx_sync;
-  wire    [ 2:0]  spi_csn;
-  wire            adc_clk;
-  wire    [31:0]  adc_data_a;
-  wire    [31:0]  adc_data_b;
-  wire            adc_enable_a;
-  wire            adc_enable_b;
-  wire            dac_clk;
-  wire   [127:0]  dac_ddata;
-  wire            dac_enable_0;
-  wire            dac_enable_1;
-
-  // pack & unpack data
-
-  always @(posedge dac_clk) begin
-    case ({dac_enable_1, dac_enable_0})
-      2'b11: begin
-        dac_drd <= 1'b1;
-        dac_ddata_1[63:48] <= dac_ddata[127:112];
-        dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
-        dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
-        dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
-        dac_ddata_0[63:48] <= dac_ddata[111: 96];
-        dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
-        dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
-        dac_ddata_0[15: 0] <= dac_ddata[ 15:  0];
-      end
-      2'b01: begin
-        dac_drd <= ~dac_drd;
-        dac_ddata_1 <= 64'd0;
-        dac_ddata_0 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0];
-      end
-      2'b10: begin
-        dac_drd <= ~dac_drd;
-        dac_ddata_1 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0];
-        dac_ddata_0 <= 64'd0;
-      end
-      default: begin
-        dac_drd <= 1'b0;
-        dac_ddata_1 <= 64'd0;
-        dac_ddata_0 <= 64'd0;
-      end
-    endcase
-  end
-
-  always @(posedge adc_clk) begin
-    case ({adc_enable_b, adc_enable_a})
-      2'b11: begin
-        adc_dwr <= 1'b1;
-        adc_ddata[63:48] <= adc_data_b[31:16];
-        adc_ddata[47:32] <= adc_data_a[31:16];
-        adc_ddata[31:16] <= adc_data_b[15: 0];
-        adc_ddata[15: 0] <= adc_data_a[15: 0];
-      end
-      2'b10: begin
-        adc_dwr <= ~adc_dwr;
-        adc_ddata[63:48] <= adc_data_b[31:16];
-        adc_ddata[47:32] <= adc_data_b[15: 0];
-        adc_ddata[31:16] <= adc_ddata[63:48];
-        adc_ddata[15: 0] <= adc_ddata[47:32];
-      end
-      2'b01: begin
-        adc_dwr <= ~adc_dwr;
-        adc_ddata[63:48] <= adc_data_a[31:16];
-        adc_ddata[47:32] <= adc_data_a[15: 0];
-        adc_ddata[31:16] <= adc_ddata[63:48];
-        adc_ddata[15: 0] <= adc_ddata[47:32];
-      end
-      default: begin
-        adc_dwr <= 1'b0;
-        adc_ddata[63:48] <= 16'd0;
-        adc_ddata[47:32] <= 16'd0;
-        adc_ddata[31:16] <= 16'd0;
-        adc_ddata[15: 0] <= 16'd0;
-      end
-    endcase
-  end
 
   // instantiations
 
-  assign spi_csn_adc = spi_csn[2];
-  assign spi_csn_dac = spi_csn[1];
-  assign spi_csn_clk = spi_csn[0];
-
-  // instantiations
-
-  IBUFDS_GTE2 i_ibufds_rx_ref_clk (
-    .CEB (1'd0),
-    .I (rx_ref_clk_p),
-    .IB (rx_ref_clk_n),
-    .O (rx_ref_clk),
-    .ODIV2 ());
-
-  IBUFDS i_ibufds_rx_sysref (
-    .I (rx_sysref_p),
-    .IB (rx_sysref_n),
-    .O (rx_sysref));
-
-  OBUFDS i_obufds_rx_sync (
-    .I (rx_sync),
-    .O (rx_sync_p),
-    .OB (rx_sync_n));
+  ad_iobuf #(
+    .DATA_WIDTH(15)
+  ) i_gpio_bd (
+    .dio_t(gpio_t[14:0]),
+    .dio_i(gpio_o[14:0]),
+    .dio_o(gpio_i[14:0]),
+    .dio_p(gpio_bd));
 
   daq1_spi i_spi (
-    .spi_csn (spi_csn),
-    .spi_clk (spi_clk),
-    .spi_mosi (spi_mosi),
-    .spi_miso (spi_miso),
-    .spi_sdio (spi_sdio));
-
-  ad_iobuf #(.DATA_WIDTH(23)) i_iobuf (
-    .dio_t({gpio_t[39:32], gpio_t[14:0]}),
-    .dio_i({gpio_o[39:32], gpio_o[14:0]}),
-    .dio_o({gpio_i[39:32], gpio_i[14:0]}),
-    .dio_p({gpio_adc_fdb,     // 39
-            gpio_adc_fda,     // 38
-            gpio_dac_irqn,    // 37
-            gpio_clkd_status, // 36:35
-            gpio_clkd_pdn,    // 34
-            gpio_clkd_syncn,  // 33
-            gpio_resetn,      // 32
-            gpio_bd}));       // 14:0
+    .spi_csn(cpld_csn),
+    .spi_clk(cpld_sclk),
+    .spi_mosi(cpld_mosi),
+    .spi_miso(cpld_miso),
+    .spi_sdio(cpld_sdio)
+  );
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
@@ -342,25 +203,6 @@ module system_top (
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .adc_clk (adc_clk),
-    .adc_data_a (adc_data_a),
-    .adc_data_b (adc_data_b),
-    .adc_ddata (adc_ddata),
-    .adc_dsync (1'b1),
-    .adc_dwr (adc_dwr),
-    .adc_enable_a (adc_enable_a),
-    .adc_enable_b (adc_enable_b),
-    .adc_valid_a (),
-    .adc_valid_b (),
-    .dac_clk (dac_clk),
-    .dac_ddata (dac_ddata),
-    .dac_ddata_0 (dac_ddata_0),
-    .dac_ddata_1 (dac_ddata_1),
-    .dac_drd (dac_drd),
-    .dac_enable_0 (dac_enable_0),
-    .dac_enable_1 (dac_enable_1),
-    .dac_valid_0 (),
-    .dac_valid_1 (),
     .hdmi_data (hdmi_data),
     .hdmi_data_e (hdmi_data_e),
     .hdmi_hsync (hdmi_hsync),
@@ -370,8 +212,6 @@ module system_top (
     .iic_main_sda_io (iic_sda),
     .ps_intr_00 (1'b0),
     .ps_intr_01 (1'b0),
-    .ps_intr_10 (1'b0),
-    .ps_intr_11 (1'b0),
     .ps_intr_02 (1'b0),
     .ps_intr_03 (1'b0),
     .ps_intr_04 (1'b0),
@@ -380,29 +220,28 @@ module system_top (
     .ps_intr_07 (1'b0),
     .ps_intr_08 (1'b0),
     .ps_intr_09 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .ps_intr_10 (1'b0),
     .spdif (spdif),
     .spi0_clk_i (1'b0),
-    .spi0_clk_o (spi_clk),
-    .spi0_csn_0_o (spi_csn[0]),
-    .spi0_csn_1_o (spi_csn[1]),
-    .spi0_csn_2_o (spi_csn[2]),
+    .spi0_clk_o (cpld_sclk),
+    .spi0_csn_0_o (cpld_csn),
     .spi0_csn_i (1'b1),
-    .spi0_sdi_i (spi_miso),
+    .spi0_sdi_i (cpld_miso),
     .spi0_sdo_i (1'b0),
-    .spi0_sdo_o (spi_mosi),
-    .tx_clk_n (tx_clk_n),
-    .tx_clk_p (tx_clk_p),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
-    .tx_frame_n (tx_frame_n),
-    .tx_frame_p (tx_frame_p),
-    .tx_ref_clk_n (tx_ref_clk_n),
-    .tx_ref_clk_p (tx_ref_clk_p));
+    .spi0_sdo_o (cpld_mosi),
+    .dac_clk_in_p (dac_clk_in_p),
+    .dac_clk_in_n (dac_clk_in_n),
+    .dac_clk_out_p (dac_clk_out_p),
+    .dac_clk_out_n (dac_clk_out_n),
+    .dac_frame_out_p (dac_frame_out_p),
+    .dac_frame_out_n (dac_frame_out_n),
+    .dac_data_out_p (dac_data_out_p),
+    .dac_data_out_n (dac_data_out_n),
+    .adc_clk_in_p (adc_clk_in_p),
+    .adc_clk_in_n (adc_clk_in_n),
+    .adc_data_in_p (adc_data_in_p),
+    .adc_data_in_n (adc_data_in_n),
+    .daq1_irq (daq1_irq));
 
 endmodule
 

From 14f7027793d87937ad2f5b2a862f3e11e65ff860 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 19 Jan 2016 11:34:28 +0200
Subject: [PATCH 055/972] ad7616_sdz: Move the context switching to
 system_project.tcl

---
 projects/ad7616_sdz/common/ad7616_bd.tcl     | 25 ++------------------
 projects/ad7616_sdz/zc706/system_project.tcl | 25 ++++++++++++++++----
 2 files changed, 23 insertions(+), 27 deletions(-)

diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index aaca1734f..e550aef16 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -1,23 +1,6 @@
 
-##--------------------------------------------------------------
-# IMPORTANT: Set AD7616 operation and interface mode
-#
-#    ad7616_opm - Defines the operation mode (software OR hardware)
-#    ad7616_if  - Defines the interface type (serial OR parallel)
-#
-# LEGEND: Software  - 0
-#         Hardware  - 1
-#         Serial    - 0
-#         Parallel  - 1
-#
-# NOTE : These switches are 'hardware' switches. User needs to
-# reimplement the design each and every time, after these variables
-# were changed.
-
-set ad7616_opm  0
-set ad7616_if   0
-
-##--------------------------------------------------------------
+global ad7616_if
+global ad7616_opm
 
 # data interfaces
 
@@ -77,10 +60,6 @@ if {$ad7616_if == 0} {
   ad_connect  burst axi_ad7616/burst
   ad_connect  os axi_ad7616/os
 
-  ad_connect  db_o GND
-  ad_connect  wr_n GND
-  ad_connect  rd_n GND
-
 } else {
 
 }
diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl
index f13fb9e90..06b3ccf1b 100644
--- a/projects/ad7616_sdz/zc706/system_project.tcl
+++ b/projects/ad7616_sdz/zc706/system_project.tcl
@@ -3,12 +3,29 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-set ad7616_interface "serial"
-#set ad7616_interface "parallel"
+##--------------------------------------------------------------
+# IMPORTANT: Set AD7616 operation and interface mode
+#
+#    ad7616_opm - Defines the operation mode (software OR hardware)
+#    ad7616_if  - Defines the interface type (serial OR parallel)
+#
+# LEGEND: Software  - 0
+#         Hardware  - 1
+#         Serial    - 0
+#         Parallel  - 1
+#
+# NOTE : These switches are 'hardware' switches. User needs to
+# reimplement the design each and every time, after these variables
+# were changed.
+#
+##--------------------------------------------------------------
+
+set ad7616_if   0
+set ad7616_opm  0
 
 adi_project_create ad7616_sdz_zc706
 
-if { $ad7616_interface eq "serial" } {
+if { $ad7616_if == 0 } {
 
   adi_project_files ad7616_sdz_zc706 [list \
     "$ad_hdl_dir/library/common/ad_iobuf.v" \
@@ -16,7 +33,7 @@ if { $ad7616_interface eq "serial" } {
     "serial_if_constr.xdc" \
     "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
 
-} elseif { $ad7616_interface eq "parallel" } {
+} elseif { $ad7616_if == 1 } {
 
   adi_project_files ad7616_sdz_zc706 [list \
     "$ad_hdl_dir/library/common/ad_iobuf.v" \

From df3eefdca10e6316e05d3b2b4934934873bf3d57 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Tue, 19 Jan 2016 12:43:05 +0200
Subject: [PATCH 056/972] axi_ad9434: Update constraint file

---
 library/axi_ad9434/axi_ad9434_constr.xdc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/library/axi_ad9434/axi_ad9434_constr.xdc b/library/axi_ad9434/axi_ad9434_constr.xdc
index 8b1378917..3d94bab25 100644
--- a/library/axi_ad9434/axi_ad9434_constr.xdc
+++ b/library/axi_ad9434/axi_ad9434_constr.xdc
@@ -1 +1,2 @@
-
+set_false_path  -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}]
+                -to   [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]

From c865dbf3539a4788d4dabe963e3f724daedfb005 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Tue, 19 Jan 2016 12:49:45 +0200
Subject: [PATCH 057/972] axi_ad9680: Fix channel instantiation

---
 library/axi_ad9680/axi_ad9680.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v
index 0e8b5125b..a32e442cb 100644
--- a/library/axi_ad9680/axi_ad9680.v
+++ b/library/axi_ad9680/axi_ad9680.v
@@ -206,7 +206,7 @@ module axi_ad9680 (
 
   // channel
 
-  axi_ad9680_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
+  axi_ad9680_channel #(.CHANNEL_ID(0)) i_channel_0 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_data (adc_data_a_s),
@@ -229,7 +229,7 @@ module axi_ad9680 (
 
   // channel
 
-  axi_ad9680_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
+  axi_ad9680_channel #(.CHANNEL_ID(1)) i_channel_1 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_data (adc_data_b_s),

From 4cc69c0cacbefea404cb328f3f94ae2dff1979e3 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 19 Jan 2016 18:27:33 +0200
Subject: [PATCH 058/972] axi_ad9684: Add Makefile

---
 library/Makefile            |  2 ++
 library/axi_ad9684/Makefile | 60 +++++++++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)
 create mode 100644 library/axi_ad9684/Makefile

diff --git a/library/Makefile b/library/Makefile
index e8d89e0be..f6e88a083 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -25,6 +25,7 @@ clean:
 	make -C axi_ad9652 clean
 	make -C axi_ad9671 clean
 	make -C axi_ad9680 clean
+	make -C axi_ad9684 clean
 	make -C axi_ad9739a clean
 	make -C axi_adcfifo clean
 	make -C axi_clkgen clean
@@ -91,6 +92,7 @@ lib:
 	-make -C axi_ad9652
 	-make -C axi_ad9671
 	-make -C axi_ad9680
+	-make -C axi_ad9684
 	-make -C axi_ad9739a
 	-make -C axi_adcfifo
 	-make -C axi_clkgen
diff --git a/library/axi_ad9684/Makefile b/library/axi_ad9684/Makefile
new file mode 100644
index 000000000..3fbb3114b
--- /dev/null
+++ b/library/axi_ad9684/Makefile
@@ -0,0 +1,60 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := axi_ad9684_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_serdes_in.v
+M_DEPS += ../common/ad_serdes_clk.v
+M_DEPS += ../common/ad_mmcm_drp.v
+M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_delay_cntrl.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += axi_ad9684_pnmon.v
+M_DEPS += axi_ad9684_if.v
+M_DEPS += axi_ad9684_channel.v
+M_DEPS += axi_ad9684_constr.xdc
+M_DEPS += axi_ad9684.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_ad9684.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_ad9684.xpr: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_ad9684_ip.tcl  >> axi_ad9684_ip.log 2>&1
+
+####################################################################################
+####################################################################################

From 4b962e8d723f3498766744ad08561ce88e2a4e52 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jan 2016 15:44:06 +0200
Subject: [PATCH 059/972] spi_engine: The width of the counters depend on the
 current DATA_WIDTH

---
 .../spi_engine_execution/spi_engine_execution.v | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
index b3a092bef..ed743f376 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
@@ -50,19 +50,22 @@ localparam MISC_SLEEP = 1'b1;
 localparam REG_CLK_DIV = 1'b0;
 localparam REG_CONFIG = 1'b1;
 
+localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
+                               DATA_WIDTH > 8  ? 4 : 3;
+
 reg idle;
 
 reg [7:0] clk_div_counter = 'h00;
 reg [7:0] clk_div_counter_next = 'h00;
 reg clk_div_last;
 
-reg [11:0] counter = 'h00;
+reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
 
-wire [7:0] sleep_counter = counter[11:4];
-wire [1:0] cs_sleep_counter = counter[5:4];
-wire [2:0] cs_sleep_counter2 = counter[6:4];
-wire [2:0] bit_counter = counter[3:1];
-wire [7:0] transfer_counter = counter[11:4];
+wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
+wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
+wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];
+wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
+wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
 wire ntx_rx = counter[0];
 
 reg trigger = 1'b0;
@@ -76,7 +79,7 @@ reg last_transfer;
 wire end_of_word;
 
 assign first_bit = bit_counter == 'h0;
-assign last_bit = bit_counter == 'h7;
+assign last_bit = bit_counter == DATA_WIDTH - 1;
 assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
 
 reg [15:0] cmd_d1;

From aa77af6bdfe1bff6b51a131cc8487abf73a4ce07 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 21 Jan 2016 18:05:59 +0200
Subject: [PATCH 060/972] daq1_cpld: Add ISE project file

This file, along with the project source files, is sufficient to open and implement in ISE Project Navigator.
---
 projects/daq1/cpld/daq1_cpld.xise | 241 ++++++++++++++++++++++++++++++
 1 file changed, 241 insertions(+)
 create mode 100644 projects/daq1/cpld/daq1_cpld.xise

diff --git a/projects/daq1/cpld/daq1_cpld.xise b/projects/daq1/cpld/daq1_cpld.xise
new file mode 100644
index 000000000..bd926f9fe
--- /dev/null
+++ b/projects/daq1/cpld/daq1_cpld.xise
@@ -0,0 +1,241 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="daq1_cpld.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="daq1_cpld.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc2c64a" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="CoolRunner2 CPLDs" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|daq1_cpld" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="daq1_cpld.v" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/daq1_cpld" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="daq1_cpld" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="QFG48" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="daq1_cpld_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="daq1_cpld_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="daq1_cpld_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="daq1_cpld_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/daq1_cpld_test" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.daq1_cpld_test" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.daq1_cpld_test" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target UCF File Name" xil_pn:value="daq1_cpld.ucf" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Ground" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|daq1_cpld_test" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="daq1_cpld" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xbr" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-12-22T16:59:48" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E3A619140B8D441CB02D709A04E40C60" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>

From 2a17ce275c492ed06ef74a9721bc8690e55c0963 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 25 Jan 2016 17:50:50 +0200
Subject: [PATCH 061/972] axi_ad7616: Control inputs are controlled through
 GPIO

The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
---
 library/axi_ad7616/axi_ad7616.v          | 23 +------
 library/axi_ad7616/axi_ad7616_control.v  | 83 ------------------------
 projects/ad7616_sdz/common/ad7616_bd.tcl | 14 ----
 projects/ad7616_sdz/zc706/system_top.v   | 21 +++---
 4 files changed, 15 insertions(+), 126 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index d09eabc5f..a5813fae0 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -51,20 +51,14 @@ module axi_ad7616 (
 
   db_o,
   db_i,
+  db_t,
   rd_n,
   wr_n,
 
   // physical control interface
 
-  reset_n,
   cnvst,
   busy,
-  seq_en,
-  hw_rngsel,
-  chsel,
-  crcen,
-  burst,
-  os,
 
   // AXI Slave Memory Map
 
@@ -122,18 +116,12 @@ module axi_ad7616 (
 
   output  [15:0]  db_o;
   input   [15:0]  db_i;
+  output          db_t;
   output          rd_n;
   output          wr_n;
 
-  output          reset_n;
   output          cnvst;
   input           busy;
-  output          seq_en;
-  output  [ 1:0]  hw_rngsel;
-  output  [ 2:0]  chsel;
-  output          crcen;
-  output          burst;
-  output  [ 2:0]  os;
 
   input           s_axi_aclk;
   input           s_axi_aresetn;
@@ -419,15 +407,8 @@ module axi_ad7616 (
     .ID(ID),
     .OP_MODE (OP_MODE)
   ) i_ad7616_control (
-    .reset_n (reset_n),
     .cnvst (cnvst),
     .busy (busy),
-    .seq_en (seq_en),
-    .hw_rngsel (hw_rngsel),
-    .chsel (chsel),
-    .crcen (crcen),
-    .burst (burst),
-    .os (os),
     .end_of_conv (trigger_s),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index 36d91de84..37a0fa2f5 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -43,15 +43,8 @@ module axi_ad7616_control (
 
   // control signals
 
-  reset_n,
   cnvst,
   busy,
-  seq_en,
-  hw_rngsel,
-  chsel,
-  crcen,
-  burst,
-  os,
 
   end_of_conv,
 
@@ -79,15 +72,8 @@ module axi_ad7616_control (
   localparam  POS_EDGE = 0;
   localparam  NEG_EDGE = 1;
 
-  output          reset_n;
   output          cnvst;
   input           busy;
-  output          seq_en;
-  output  [ 1:0]  hw_rngsel;
-  output  [ 2:0]  chsel;
-  output          crcen;
-  output          burst;
-  output  [ 2:0]  os;
 
   output          end_of_conv;
 
@@ -120,14 +106,6 @@ module axi_ad7616_control (
   reg             cnvst_pulse = 1'b0;
   reg     [ 2:0]  chsel_ff = 3'b0;
 
-  reg     [ 1:0]  up_hw_rngsel = 2'b0;
-  reg     [ 2:0]  up_chsel = 3'b0;
-  reg             up_crcen = 1'b0;
-  reg             up_burst = 1'b0;
-  reg     [ 2:0]  up_os = 3'b0;
-  reg             up_seq_en = 1'b0;
-
-
   wire            up_rst;
   wire            up_rreq_s;
   wire            up_wreq_s;
@@ -149,12 +127,6 @@ module axi_ad7616_control (
       up_resetn <= 1'b0;
       up_cnvst_en <= 1'b0;
       up_conv_rate <= 32'b0;
-      up_hw_rngsel <= 2'b0;
-      up_chsel <= 3'b0;
-      up_crcen <= 1'b0;
-      up_burst <= 1'b0;
-      up_os <= 3'b0;
-      up_seq_en <= 1'b0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@@ -167,18 +139,6 @@ module axi_ad7616_control (
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
         up_conv_rate <= up_wdata;
       end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
-        up_hw_rngsel <= up_wdata[1:0];
-        up_os <= up_wdata[4:2];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
-        up_seq_en <= up_wdata[0];
-        up_burst <= up_wdata[1];
-        up_chsel <= up_wdata[4:2];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
-        up_crcen <= up_wdata[0];
-      end
     end
   end
 
@@ -197,9 +157,6 @@ module axi_ad7616_control (
             8'h02 : up_rdata = up_scratch;
             8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
             8'h11 : up_rdata = up_conv_rate;
-            8'h12 : up_rdata = {27'b0, up_os, up_hw_rngsel};
-            8'h13 : up_rdata = {27'b0, up_chsel, up_burst, up_seq_en};
-            8'h14 : up_rdata = {30'b0, up_crcen};
         endcase
       end
     end
@@ -252,45 +209,5 @@ module axi_ad7616_control (
 
   assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
 
-  // output logic
-
-  assign reset_n = up_resetn;       // device's reset
-
-  generate if (OP_MODE == SW) begin
-
-    // ground all the unused control signals
-
-    assign seq_en = 1'b0;
-    assign hw_rngsel = 2'b0;
-    assign chsel = 3'b0;
-    assign crcen = 1'b0;
-    assign burst = 1'b0;
-    assign os = 3'b0;
-
-  end
-  endgenerate
-
-  generate if (OP_MODE == HW) begin
-
-    assign hw_rngsel = up_hw_rngsel;
-    assign crcen = up_crcen;
-    assign burst = up_burst;
-    assign os = up_os;
-    assign seq_en = up_seq_en;
-    assign chsel = chsel_ff;
-
-    // CHSEL is updated after BUSY deasserts
-
-    always @(posedge up_clk) begin
-      if (up_rstn == 1'b0) begin
-        chsel_ff <= 3'b0;
-      end else begin
-        chsel_ff <= (end_of_conv_s == 1'b1) ? up_chsel : chsel_ff;
-      end
-    end
-
-  end
-  endgenerate
-
 endmodule
 
diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index e550aef16..649b19680 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -16,16 +16,9 @@ create_bd_port -dir O wr_n
 
 # control lines
 
-create_bd_port -dir O reset_n
 create_bd_port -dir O cnvst
 create_bd_port -dir O cs_n
 create_bd_port -dir I busy
-create_bd_port -dir O seq_en
-create_bd_port -dir O -from 1 -to 0 hw_rngsel
-create_bd_port -dir O -from 2 -to 0 chsel
-create_bd_port -dir O crcen
-create_bd_port -dir O burst
-create_bd_port -dir O -from 2 -to 0 os
 
 # instantiation
 
@@ -50,15 +43,8 @@ if {$ad7616_if == 0} {
   ad_connect  sdi_1 axi_ad7616/sdi_1
   ad_connect  cs_n axi_ad7616/cs_n
 
-  ad_connect  reset_n axi_ad7616/reset_n
   ad_connect  cnvst axi_ad7616/cnvst
   ad_connect  busy axi_ad7616/busy
-  ad_connect  seq_en axi_ad7616/seq_en
-  ad_connect  hw_rngsel axi_ad7616/hw_rngsel
-  ad_connect  chsel axi_ad7616/chsel
-  ad_connect  crcen axi_ad7616/crcen
-  ad_connect  burst axi_ad7616/burst
-  ad_connect  os axi_ad7616/os
 
 } else {
 
diff --git a/projects/ad7616_sdz/zc706/system_top.v b/projects/ad7616_sdz/zc706/system_top.v
index 1e1d26bee..c75069a04 100644
--- a/projects/ad7616_sdz/zc706/system_top.v
+++ b/projects/ad7616_sdz/zc706/system_top.v
@@ -153,6 +153,18 @@ module system_top (
 
   // instantiations
 
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
+    .dio_t (gpio_t[43:32]),
+    .dio_i (gpio_o[43:32]),
+    .dio_o (gpio_i[43:32]),
+    .dio_p ({adc_reset_n,        // 43
+             adc_hw_rngsel,      // 42:41
+             adc_os,             // 40:38
+             adc_seq_en,         // 37
+             adc_burst,          // 36
+             adc_chsel,          // 35:33
+             adc_crcen}));       // 32
+
   ad_iobuf #(
     .DATA_WIDTH(15)
   ) i_gpio_bd (
@@ -210,16 +222,9 @@ module system_top (
     .sdo (spi_sdo),
     .sdi_0 (spi_sdi_0),
     .sdi_1 (spi_sdi_1),
-    .reset_n (adc_reset_n),
     .cnvst (adc_convst),
     .cs_n (spi_cs_n),
-    .busy (adc_busy),
-    .seq_en (adc_seq_en),
-    .hw_rngsel (adc_hw_rngsel),
-    .chsel (adc_chsel),
-    .crcen (adc_crcen),
-    .burst (adc_burst),
-    .os (adc_os));
+    .busy (adc_busy));
 
 endmodule
 

From 44a382fc69a66c94a61ee7c9fd6c0f42266e6c1e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 25 Jan 2016 15:33:34 -0500
Subject: [PATCH 062/972] pzsdr1-added

---
 projects/common/pzsdr1/pzsdr1_system_bd.tcl   | 163 ++++++++++++++++++
 .../common/pzsdr1/pzsdr1_system_constr.xdc    |  88 ++++++++++
 projects/common/pzsdr1/pzsdr1_system_ps7.tcl  |  43 +++++
 3 files changed, 294 insertions(+)
 create mode 100644 projects/common/pzsdr1/pzsdr1_system_bd.tcl
 create mode 100644 projects/common/pzsdr1/pzsdr1_system_constr.xdc
 create mode 100755 projects/common/pzsdr1/pzsdr1_system_ps7.tcl

diff --git a/projects/common/pzsdr1/pzsdr1_system_bd.tcl b/projects/common/pzsdr1/pzsdr1_system_bd.tcl
new file mode 100644
index 000000000..6c442708f
--- /dev/null
+++ b/projects/common/pzsdr1/pzsdr1_system_bd.tcl
@@ -0,0 +1,163 @@
+
+# create board design
+# default ports
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
+create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+
+create_bd_port -dir O spi0_csn_2_o
+create_bd_port -dir O spi0_csn_1_o
+create_bd_port -dir O spi0_csn_0_o
+create_bd_port -dir I spi0_csn_i
+create_bd_port -dir I spi0_clk_i
+create_bd_port -dir O spi0_clk_o
+create_bd_port -dir I spi0_sdo_i
+create_bd_port -dir O spi0_sdo_o
+create_bd_port -dir I spi0_sdi_i
+
+create_bd_port -dir O spi1_csn_2_o
+create_bd_port -dir O spi1_csn_1_o
+create_bd_port -dir O spi1_csn_0_o
+create_bd_port -dir I spi1_csn_i
+create_bd_port -dir I spi1_clk_i
+create_bd_port -dir O spi1_clk_o
+create_bd_port -dir I spi1_sdo_i
+create_bd_port -dir O spi1_sdo_o
+create_bd_port -dir I spi1_sdi_i
+
+create_bd_port -dir I -from 63 -to 0 gpio_i
+create_bd_port -dir O -from 63 -to 0 gpio_o
+create_bd_port -dir O -from 63 -to 0 gpio_t
+
+# otg
+
+set otg_vbusoc      [create_bd_port -dir I otg_vbusoc]
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_11
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+create_bd_port -dir I -type intr ps_intr_15
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_ps7.tcl
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
+set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
+set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
+set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+
+# interface connections
+
+ad_connect  ddr sys_ps7/DDR
+ad_connect  gpio_i sys_ps7/GPIO_I
+ad_connect  gpio_o sys_ps7/GPIO_O
+ad_connect  gpio_t sys_ps7/GPIO_T
+ad_connect  fixed_io sys_ps7/FIXED_IO
+ad_connect  iic_main axi_iic_main/iic
+ad_connect  sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
+ad_connect  sys_logic_inv/Op1 otg_vbusoc
+
+# spi connections
+
+ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
+ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
+ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
+ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
+ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
+ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
+ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
+ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
+ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+
+ad_connect  spi1_csn_2_o sys_ps7/SPI1_SS2_O
+ad_connect  spi1_csn_1_o sys_ps7/SPI1_SS1_O
+ad_connect  spi1_csn_0_o sys_ps7/SPI1_SS_O
+ad_connect  spi1_csn_i sys_ps7/SPI1_SS_I
+ad_connect  spi1_clk_i sys_ps7/SPI1_SCLK_I
+ad_connect  spi1_clk_o sys_ps7/SPI1_SCLK_O
+ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
+ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
+ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
+
+# interrupts
+
+ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15 ps_intr_15
+ad_connect  sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
+ad_connect  sys_concat_intc/In13 ps_intr_13
+ad_connect  sys_concat_intc/In12 ps_intr_12
+ad_connect  sys_concat_intc/In11 ps_intr_11
+ad_connect  sys_concat_intc/In10 ps_intr_10
+ad_connect  sys_concat_intc/In9 ps_intr_09
+ad_connect  sys_concat_intc/In8 ps_intr_08
+ad_connect  sys_concat_intc/In7 ps_intr_07
+ad_connect  sys_concat_intc/In6 ps_intr_06
+ad_connect  sys_concat_intc/In5 ps_intr_05
+ad_connect  sys_concat_intc/In4 ps_intr_04
+ad_connect  sys_concat_intc/In3 ps_intr_03
+ad_connect  sys_concat_intc/In2 ps_intr_02
+ad_connect  sys_concat_intc/In1 ps_intr_01
+ad_connect  sys_concat_intc/In0 ps_intr_00
+
+# interconnects
+
+ad_cpu_interconnect 0x41600000 axi_iic_main
+
+# module ad9361
+
+source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
+source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
+
+set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361
+
diff --git a/projects/common/pzsdr1/pzsdr1_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
new file mode 100644
index 000000000..ef43a4869
--- /dev/null
+++ b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
@@ -0,0 +1,88 @@
+
+# constraints
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35
+set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35
+set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35
+set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35
+set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35
+set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35
+set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35
+set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35
+set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVDS}     [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVDS}     [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVDS}     [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVDS}     [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35
+set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVDS}     [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35
+set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35
+set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35
+set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35
+set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35
+set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35
+set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35
+set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35
+set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35
+set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVDS}     [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35
+set_property  -dict {PACKAGE_PIN  F14  IOSTANDARD LVCMOS18} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35
+
+set_property  -dict {PACKAGE_PIN  D13  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35
+set_property  -dict {PACKAGE_PIN  C13  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35
+set_property  -dict {PACKAGE_PIN  C14  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35
+set_property  -dict {PACKAGE_PIN  B14  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35
+set_property  -dict {PACKAGE_PIN  A15  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35
+set_property  -dict {PACKAGE_PIN  A14  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35
+set_property  -dict {PACKAGE_PIN  C12  IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35
+set_property  -dict {PACKAGE_PIN  B12  IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35
+set_property  -dict {PACKAGE_PIN  C2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34
+set_property  -dict {PACKAGE_PIN  B1   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34
+set_property  -dict {PACKAGE_PIN  B2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34
+set_property  -dict {PACKAGE_PIN  A2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34
+set_property  -dict {PACKAGE_PIN  G16  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS18} [get_ports gpio_resetb]                       ; ## IO_0_VRN_35
+set_property  -dict {PACKAGE_PIN  K11  IOSTANDARD LVCMOS18} [get_ports gpio_clksel]                       ; ## IO_0_VRN_34
+
+set_property  -dict {PACKAGE_PIN  C11  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35
+set_property  -dict {PACKAGE_PIN  B11  IOSTANDARD LVCMOS18} [get_ports spi_clk]                           ; ## IO_L23N_T3_35
+set_property  -dict {PACKAGE_PIN  A13  IOSTANDARD LVCMOS18} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35
+set_property  -dict {PACKAGE_PIN  A12  IOSTANDARD LVCMOS18} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35
+
+set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports clk_out]                           ; ## IO_25_VRP_35
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L5P_T0_13             
+set_property  -dict {PACKAGE_PIN  AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L5N_T0_13             
+
+# gpio
+
+set_property  -dict {PACKAGE_PIN  J3   IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L12N_T1_MRCC_33       
+set_property  -dict {PACKAGE_PIN  D8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L8N_T1_34             
+set_property  -dict {PACKAGE_PIN  F9   IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9P_T1_DQS_34         
+set_property  -dict {PACKAGE_PIN  E8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]                        ; ## (pb)  IO_L9N_T1_DQS_34         
+set_property  -dict {PACKAGE_PIN  A8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]]                        ; ## (led) IO_L17N_T2_34            
+set_property  -dict {PACKAGE_PIN  W14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]]                        ; ## (led) IO_0_12                  
+set_property  -dict {PACKAGE_PIN  W17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]                        ; ## (led) IO_25_12                 
+set_property  -dict {PACKAGE_PIN  Y16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]                        ; ## (led) IO_L23P_T3_12            
+set_property  -dict {PACKAGE_PIN  Y15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]]                        ; ## (dip) IO_L23N_T3_12            
+set_property  -dict {PACKAGE_PIN  W16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]                        ; ## (dip) IO_L24P_T3_12            
+set_property  -dict {PACKAGE_PIN  W15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]]                       ; ## (dip) IO_L24N_T3_12            
+set_property  -dict {PACKAGE_PIN  V19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]                       ; ## (dip) IO_0_13                  
+
+# clocks
+
+create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+
diff --git a/projects/common/pzsdr1/pzsdr1_system_ps7.tcl b/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
new file mode 100755
index 000000000..fd86195cf
--- /dev/null
+++ b/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
@@ -0,0 +1,43 @@
+
+set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_PACKAGE_NAME                              {fbg676}                [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE                      {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_ENET0_IO                            {MIO 16 .. 27}          [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE                     {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET1_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7] 
+set_property CONFIG.PCW_ENET_RESET_SELECT                         {Separate reset pins}   [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_RESET_ENABLE                        {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET0_RESET_IO                            {MIO 8}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET1_RESET_ENABLE                        {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_ENET1_RESET_IO                            {MIO 51}                [get_bd_cells sys_ps7]
+
+set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE                     {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SD0_GRP_CD_ENABLE                         {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SD0_GRP_CD_IO                             {MIO 50}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ                   {50}                    [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USB0_RESET_ENABLE                         {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USB0_RESET_IO                             {MIO 7}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
+
+## DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
+
+set_property CONFIG.PCW_UIPARAM_DDR_PARTNO                        {MT41K256M16 RE-125}    [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH                     {32 Bit}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF             {0}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL             {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE               {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE                {1}                     [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {-0.053}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {-0.059}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {0.065}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {0.066}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.264}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.265}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.330}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.330}                 [get_bd_cells sys_ps7]
+

From bcac3eef4dd4ef6efd1c097995383e36b99954d9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 25 Jan 2016 16:07:33 -0500
Subject: [PATCH 063/972] pzsdr1- initial commit

---
 projects/pzsdr1/Makefile                 |  27 ++
 projects/pzsdr1/ccbrk/Makefile           |  84 ++++++
 projects/pzsdr1/ccbrk/system_bd.tcl      |   4 +
 projects/pzsdr1/ccbrk/system_constr.xdc  | 258 ++++++++++++++++++
 projects/pzsdr1/ccbrk/system_project.tcl |  20 ++
 projects/pzsdr1/ccbrk/system_top.v       | 331 +++++++++++++++++++++++
 projects/pzsdr1/common/ccbrk_bd.tcl      | 191 +++++++++++++
 projects/scripts/adi_project.tcl         |   5 +
 8 files changed, 920 insertions(+)
 create mode 100644 projects/pzsdr1/Makefile
 create mode 100644 projects/pzsdr1/ccbrk/Makefile
 create mode 100644 projects/pzsdr1/ccbrk/system_bd.tcl
 create mode 100644 projects/pzsdr1/ccbrk/system_constr.xdc
 create mode 100644 projects/pzsdr1/ccbrk/system_project.tcl
 create mode 100644 projects/pzsdr1/ccbrk/system_top.v
 create mode 100644 projects/pzsdr1/common/ccbrk_bd.tcl

diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile
new file mode 100644
index 000000000..f6284afab
--- /dev/null
+++ b/projects/pzsdr1/Makefile
@@ -0,0 +1,27 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+.PHONY: all clean clean-all 
+all:
+	-make -C ccbrk all
+	-make -C ccfmc all
+	-make -C ccpci all
+
+
+clean: 
+	make -C ccbrk clean
+	make -C ccfmc clean
+	make -C ccpci clean
+
+
+clean-all:
+	make -C ccbrk clean-all
+	make -C ccfmc clean-all
+	make -C ccpci clean-all
+
+####################################################################################
+####################################################################################
diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
new file mode 100644
index 000000000..49d742665
--- /dev/null
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -0,0 +1,84 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
+M_DEPS += ../../common/xilinx/sys_wfifo.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
+M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib ccbrk_pzsdr.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_gtlb clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_gpreg
+	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_gtlb
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/pzsdr1/ccbrk/system_bd.tcl b/projects/pzsdr1/ccbrk/system_bd.tcl
new file mode 100644
index 000000000..4907eef1b
--- /dev/null
+++ b/projects/pzsdr1/ccbrk/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/ccbrk_bd.tcl
+
diff --git a/projects/pzsdr1/ccbrk/system_constr.xdc b/projects/pzsdr1/ccbrk/system_constr.xdc
new file mode 100644
index 000000000..05083fdc9
--- /dev/null
+++ b/projects/pzsdr1/ccbrk/system_constr.xdc
@@ -0,0 +1,258 @@
+
+## constraints
+## loopback
+## p4
+
+set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33              
+set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33              
+set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33              
+set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33              
+set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33              
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33          
+set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33              
+set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33          
+set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33              
+set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33              
+set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33         
+set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33              
+set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33              
+set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33              
+set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33              
+set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33              
+set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33             
+set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33          
+set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33             
+set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33          
+set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33        
+set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33        
+
+## p5
+
+set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33             
+set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33             
+set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33             
+set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33             
+set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33             
+set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33             
+set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33        
+set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33             
+set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33             
+set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33         
+set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33             
+set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33         
+set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33             
+set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33             
+set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33             
+set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33             
+set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34              
+set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34             
+set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33        
+set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33             
+set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33        
+set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33             
+set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33        
+set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33         
+set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33        
+set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33         
+
+## p6
+
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34              
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34              
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34              
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34              
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34              
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34   
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34              
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34          
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34              
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34              
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34         
+set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34              
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34              
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34              
+set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34        
+set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34        
+set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34        
+set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34        
+
+## p7
+
+set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34        
+set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34        
+set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34        
+set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34        
+set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34             
+set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34         
+set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34             
+set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34         
+set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34             
+set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34             
+set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34             
+set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34        
+set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34             
+set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34             
+set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33               
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34             
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34             
+set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33              
+
+## p13
+
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12             
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12         
+set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12             
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12         
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12             
+set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12          
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12             
+set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12          
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12              
+set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12              
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12              
+set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12              
+set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12              
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12              
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12         
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12              
+set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12              
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12          
+set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12              
+set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12          
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12              
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12              
+set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12              
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12              
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12             
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12             
+set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12             
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12             
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12             
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12             
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12             
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12        
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12             
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12         
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12             
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12         
+
+## p2
+
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13                  
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13              
+set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13              
+set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13              
+set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13              
+set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13              
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13              
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13          
+set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13              
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13          
+set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13              
+set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13              
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13              
+set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13              
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13             
+set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13          
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13             
+set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13          
+set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13             
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13         
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13             
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13         
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13             
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13             
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13             
+set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13             
+set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13             
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13             
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13             
+set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13        
+set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13             
+set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13         
+set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13             
+set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13         
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13             
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13             
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13             
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13             
+
+## vcc
+
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13         
+
+## on board
+
+set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111           
+set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111           
+set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111              
+set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111              
+set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111              
+set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111              
+set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111              
+set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111              
+set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111              
+set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111              
+set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111              
+set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111              
+set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111              
+set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111              
+set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111              
+set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111              
+set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111              
+set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111              
+
+## clocks
+
+create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+
+## MIO loopbacks (fixed-io)
+## the following are connected to AD9361 GPIO
+
+##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
+##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
+##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
+##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
+
+## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
+
+##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
+
+## the following are mio-to-pl loopback
+
+##  JX4.97    E26   PS_MIO00_500_JX4    <==>  JX1.76    K3    IO_L11N_T1_SRCC_33        
+##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
+##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
+##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
+
+set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33        
+set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34             
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34              
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34             
+
diff --git a/projects/pzsdr1/ccbrk/system_project.tcl b/projects/pzsdr1/ccbrk/system_project.tcl
new file mode 100644
index 000000000..3d182ce37
--- /dev/null
+++ b/projects/pzsdr1/ccbrk/system_project.tcl
@@ -0,0 +1,20 @@
+
+
+
+source ../../scripts/adi_env.tcl 
+source $ad_hdl_dir/projects/scripts/adi_project.tcl 
+source $ad_hdl_dir/projects/scripts/adi_board.tcl 
+
+adi_project_create ccbrk_pzsdr
+adi_project_files ccbrk_pzsdr [list \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ]
+
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+
+adi_project_run ccbrk_pzsdr
+
+
diff --git a/projects/pzsdr1/ccbrk/system_top.v b/projects/pzsdr1/ccbrk/system_top.v
new file mode 100644
index 000000000..585b2022d
--- /dev/null
+++ b/projects/pzsdr1/ccbrk/system_top.v
@@ -0,0 +1,331 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  iic_scl,
+  iic_sda,
+
+  gpio_bd,
+
+  rx_clk_in_p,
+  rx_clk_in_n,
+  rx_frame_in_p,
+  rx_frame_in_n,
+  rx_data_in_p,
+  rx_data_in_n,
+  tx_clk_out_p,
+  tx_clk_out_n,
+  tx_frame_out_p,
+  tx_frame_out_n,
+  tx_data_out_p,
+  tx_data_out_n,
+
+  enable,
+  txnrx,
+  clk_out,
+
+  gpio_clksel,
+  gpio_resetb,
+  gpio_sync,
+  gpio_en_agc,
+  gpio_ctl,
+  gpio_status,
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  gp_out,
+  gp_in,
+  gp_in_mio,
+  gp_in_1,
+
+  gt_ref_clk_p,
+  gt_ref_clk_n,
+  gt_tx_p,
+  gt_tx_n,
+  gt_rx_p,
+  gt_rx_n);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  inout   [11:0]  gpio_bd;
+
+  input           rx_clk_in_p;
+  input           rx_clk_in_n;
+  input           rx_frame_in_p;
+  input           rx_frame_in_n;
+  input   [ 5:0]  rx_data_in_p;
+  input   [ 5:0]  rx_data_in_n;
+  output          tx_clk_out_p;
+  output          tx_clk_out_n;
+  output          tx_frame_out_p;
+  output          tx_frame_out_n;
+  output  [ 5:0]  tx_data_out_p;
+  output  [ 5:0]  tx_data_out_n;
+
+  output          enable;
+  output          txnrx;
+  input           clk_out;
+
+  inout           gpio_clksel;
+  inout           gpio_resetb;
+  inout           gpio_sync;
+  inout           gpio_en_agc;
+  inout   [ 3:0]  gpio_ctl;
+  inout   [ 7:0]  gpio_status;
+
+  output          spi_csn;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  output  [87:0]  gp_out;
+  input   [87:0]  gp_in;
+  input   [ 3:0]  gp_in_mio;
+  input           gp_in_1;
+
+  input           gt_ref_clk_p;
+  input           gt_ref_clk_n;
+  output  [ 3:0]  gt_tx_p;
+  output  [ 3:0]  gt_tx_n;
+  input   [ 3:0]  gt_rx_p;
+  input   [ 3:0]  gt_rx_n;
+
+  // internal signals
+
+  wire            gt_ref_clk;
+  wire    [95:0]  gp_out_s;
+  wire    [95:0]  gp_in_s;
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+
+  assign gp_out[87:43] = gp_out_s[87:43];
+  assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
+  assign gp_out[41: 0] = gp_out_s[41: 0];
+
+  assign gp_in_s[95:93] = 3'd0;
+  assign gp_in_s[92:92] = gp_in_1;
+  assign gp_in_s[91:88] = gp_in_mio;
+  assign gp_in_s[87: 0] = gp_in;
+
+  // instantiations
+
+  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
+    .CEB (1'd0),
+    .I (gt_ref_clk_p),
+    .IB (gt_ref_clk_n),
+    .O (gt_ref_clk),
+    .ODIV2 ());
+
+  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
+    .dio_t ({gpio_t[51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[51], gpio_i[46:32]}),
+    .dio_p ({ gpio_clksel,        // 51:51
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
+    .dio_t (gpio_t[11:0]),
+    .dio_i (gpio_o[11:0]),
+    .dio_o (gpio_i[11:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gp_in_0 (gp_in_s[31:0]),
+    .gp_in_1 (gp_in_s[63:32]),
+    .gp_in_2 (gp_in_s[95:64]),
+    .gp_out_0 (gp_out_s[31:0]),
+    .gp_out_1 (gp_out_s[63:32]),
+    .gp_out_2 (gp_out_s[95:64]),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .gt_ref_clk (gt_ref_clk),
+    .gt_rx_0_n (gt_rx_n[0]),
+    .gt_rx_0_p (gt_rx_p[0]),
+    .gt_rx_1_n (gt_rx_n[1]),
+    .gt_rx_1_p (gt_rx_p[1]),
+    .gt_rx_2_n (gt_rx_n[2]),
+    .gt_rx_2_p (gt_rx_p[2]),
+    .gt_rx_3_n (gt_rx_n[3]),
+    .gt_rx_3_p (gt_rx_p[3]),
+    .gt_tx_0_n (gt_tx_n[0]),
+    .gt_tx_0_p (gt_tx_p[0]),
+    .gt_tx_1_n (gt_tx_n[1]),
+    .gt_tx_1_p (gt_tx_p[1]),
+    .gt_tx_2_n (gt_tx_n[2]),
+    .gt_tx_2_p (gt_tx_p[2]),
+    .gt_tx_3_n (gt_tx_n[3]),
+    .gt_tx_3_p (gt_tx_p[3]),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .otg_vbusoc (1'b0),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/pzsdr1/common/ccbrk_bd.tcl b/projects/pzsdr1/common/ccbrk_bd.tcl
new file mode 100644
index 000000000..a91b0dafe
--- /dev/null
+++ b/projects/pzsdr1/common/ccbrk_bd.tcl
@@ -0,0 +1,191 @@
+
+# lbfmc
+
+ad_connect  sys_ps7/ENET1_GMII_RX_CLK GND
+ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
+
+# un-used io (gt)
+
+set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_pzslb_gt
+set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt
+set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt
+set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_2 {2}] $axi_pzslb_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_pzslb_gt
+set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_3 {3}] $axi_pzslb_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_pzslb_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_pzslb_gt
+set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_pzslb_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_pzslb_gt
+
+set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0]
+set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1]
+set util_pzslb_gtlb_2 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_2]
+set util_pzslb_gtlb_3 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_3]
+
+ad_cpu_interconnect 0x44A60000 axi_pzslb_gt
+ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
+ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi
+
+create_bd_port -dir I gt_ref_clk
+create_bd_port -dir I gt_rx_0_p
+create_bd_port -dir I gt_rx_0_n
+create_bd_port -dir O gt_tx_0_p
+create_bd_port -dir O gt_tx_0_n
+create_bd_port -dir I gt_rx_1_p
+create_bd_port -dir I gt_rx_1_n
+create_bd_port -dir O gt_tx_1_p
+create_bd_port -dir O gt_tx_1_n
+create_bd_port -dir I gt_rx_2_p
+create_bd_port -dir I gt_rx_2_n
+create_bd_port -dir O gt_tx_2_p
+create_bd_port -dir O gt_tx_2_n
+create_bd_port -dir I gt_rx_3_p
+create_bd_port -dir I gt_rx_3_n
+create_bd_port -dir O gt_tx_3_p
+create_bd_port -dir O gt_tx_3_n
+
+ad_connect  sys_cpu_clk util_pzslb_gtlb_0/up_clk
+ad_connect  sys_cpu_resetn util_pzslb_gtlb_0/up_rstn
+ad_connect  util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk
+ad_connect  util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk
+ad_connect  util_pzslb_gtlb_0/rx_p gt_rx_0_p
+ad_connect  util_pzslb_gtlb_0/rx_n gt_rx_0_n
+ad_connect  util_pzslb_gtlb_0/tx_p gt_tx_0_p
+ad_connect  util_pzslb_gtlb_0/tx_n gt_tx_0_n
+ad_connect  sys_cpu_clk util_pzslb_gtlb_1/up_clk
+ad_connect  sys_cpu_resetn util_pzslb_gtlb_1/up_rstn
+ad_connect  util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk
+ad_connect  util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk
+ad_connect  util_pzslb_gtlb_1/rx_p gt_rx_1_p
+ad_connect  util_pzslb_gtlb_1/rx_n gt_rx_1_n
+ad_connect  util_pzslb_gtlb_1/tx_p gt_tx_1_p
+ad_connect  util_pzslb_gtlb_1/tx_n gt_tx_1_n
+ad_connect  sys_cpu_clk util_pzslb_gtlb_2/up_clk
+ad_connect  sys_cpu_resetn util_pzslb_gtlb_2/up_rstn
+ad_connect  util_pzslb_gtlb_2/qpll_ref_clk gt_ref_clk
+ad_connect  util_pzslb_gtlb_2/cpll_ref_clk gt_ref_clk
+ad_connect  util_pzslb_gtlb_2/rx_p gt_rx_2_p
+ad_connect  util_pzslb_gtlb_2/rx_n gt_rx_2_n
+ad_connect  util_pzslb_gtlb_2/tx_p gt_tx_2_p
+ad_connect  util_pzslb_gtlb_2/tx_n gt_tx_2_n
+ad_connect  sys_cpu_clk util_pzslb_gtlb_3/up_clk
+ad_connect  sys_cpu_resetn util_pzslb_gtlb_3/up_rstn
+ad_connect  util_pzslb_gtlb_3/qpll_ref_clk gt_ref_clk
+ad_connect  util_pzslb_gtlb_3/cpll_ref_clk gt_ref_clk
+ad_connect  util_pzslb_gtlb_3/rx_p gt_rx_3_p
+ad_connect  util_pzslb_gtlb_3/rx_n gt_rx_3_n
+ad_connect  util_pzslb_gtlb_3/tx_p gt_tx_3_p
+ad_connect  util_pzslb_gtlb_3/tx_n gt_tx_3_n
+ad_connect  axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0
+ad_connect  axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0
+ad_connect  axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0
+ad_connect  axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0
+ad_connect  axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0
+ad_connect  axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0
+ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0 
+ad_connect  axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0
+ad_connect  axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0
+ad_connect  axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0
+ad_connect  axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
+ad_connect  axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
+ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0 
+ad_connect  axi_pzslb_gt/gt_pll_2 util_pzslb_gtlb_2/gt_pll_0
+ad_connect  axi_pzslb_gt/gt_rx_2 util_pzslb_gtlb_2/gt_rx_0
+ad_connect  axi_pzslb_gt/gt_tx_2 util_pzslb_gtlb_2/gt_tx_0
+ad_connect  axi_pzslb_gt/gt_rx_ip_2 util_pzslb_gtlb_2/gt_rx_ip_0
+ad_connect  axi_pzslb_gt/gt_tx_ip_2 util_pzslb_gtlb_2/gt_tx_ip_0
+ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_2 util_pzslb_gtlb_2/rx_gt_comma_align_enb_0 
+ad_connect  axi_pzslb_gt/gt_pll_3 util_pzslb_gtlb_3/gt_pll_0
+ad_connect  axi_pzslb_gt/gt_rx_3 util_pzslb_gtlb_3/gt_rx_0
+ad_connect  axi_pzslb_gt/gt_tx_3 util_pzslb_gtlb_3/gt_tx_0
+ad_connect  axi_pzslb_gt/gt_rx_ip_3 util_pzslb_gtlb_3/gt_rx_ip_0
+ad_connect  axi_pzslb_gt/gt_tx_ip_3 util_pzslb_gtlb_3/gt_tx_ip_0
+ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_3 util_pzslb_gtlb_3/rx_gt_comma_align_enb_0 
+
+# un-used io (regular)
+
+set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
+set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg
+set_property -dict [list CONFIG.BUF_ENABLE_0 {0}] $axi_gpreg
+set_property -dict [list CONFIG.BUF_ENABLE_1 {0}] $axi_gpreg
+set_property -dict [list CONFIG.BUF_ENABLE_2 {0}] $axi_gpreg
+set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg
+set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg
+set_property -dict [list CONFIG.BUF_ENABLE_5 {0}] $axi_gpreg
+set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg
+set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_IO {7}] $axi_gpreg
+
+ad_cpu_interconnect 0x41200000 axi_gpreg
+
+ad_connect  util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_0
+ad_connect  util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_1
+ad_connect  util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_2
+ad_connect  util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_3
+ad_connect  util_pzslb_gtlb_2/rx_clk axi_gpreg/d_clk_4
+ad_connect  util_pzslb_gtlb_2/tx_clk axi_gpreg/d_clk_5
+ad_connect  util_pzslb_gtlb_3/rx_clk axi_gpreg/d_clk_6
+ad_connect  util_pzslb_gtlb_3/tx_clk axi_gpreg/d_clk_7
+
+create_bd_port -dir I -from 31 -to 0 gp_in_0
+create_bd_port -dir I -from 31 -to 0 gp_in_1
+create_bd_port -dir I -from 31 -to 0 gp_in_2
+create_bd_port -dir O -from 31 -to 0 gp_out_0
+create_bd_port -dir O -from 31 -to 0 gp_out_1
+create_bd_port -dir O -from 31 -to 0 gp_out_2
+
+ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
+ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
+ad_connect  gp_in_2 axi_gpreg/up_gp_in_2
+ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
+ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
+ad_connect  gp_out_2 axi_gpreg/up_gp_out_2
+ad_connect  axi_gpreg/up_gp_in_3 util_pzslb_gtlb_0/up_gp_out
+ad_connect  axi_gpreg/up_gp_out_3 util_pzslb_gtlb_0/up_gp_in
+ad_connect  axi_gpreg/up_gp_in_4 util_pzslb_gtlb_1/up_gp_out
+ad_connect  axi_gpreg/up_gp_out_4 util_pzslb_gtlb_1/up_gp_in
+ad_connect  axi_gpreg/up_gp_in_5 util_pzslb_gtlb_2/up_gp_out
+ad_connect  axi_gpreg/up_gp_out_5 util_pzslb_gtlb_2/up_gp_in
+ad_connect  axi_gpreg/up_gp_in_6 util_pzslb_gtlb_3/up_gp_out
+ad_connect  axi_gpreg/up_gp_out_6 util_pzslb_gtlb_3/up_gp_in
+
+## temporary (remove ila indirectly)
+
+delete_bd_objs [get_bd_cells ila_adc]
+delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
+
diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index dbe5a5403..13d3c9715 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -80,6 +80,11 @@ proc adi_project_create {project_name {mode 0}} {
     set p_board "not-applicable"
     set sys_zynq 1
   }
+  if [regexp "_pzsdr1$" $project_name] {
+    set p_device "xc7z020ifbg676-1L"
+    set p_board "not-applicable"
+    set sys_zynq 1
+  }
 
   if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} {
     return -code error [format "ERROR: This project requires Vivado %s." $REQUIRED_VIVADO_VERSION]

From cd43ebd8bc1cfbf4520d95da36b13250ed17b275 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 26 Jan 2016 11:05:33 +0200
Subject: [PATCH 064/972] axi_ad7616: The OP_MODE parameter is no longer
 required

---
 library/axi_ad7616/axi_ad7616.v              | 4 +---
 library/axi_ad7616/axi_ad7616_control.v      | 1 -
 projects/ad7616_sdz/common/ad7616_bd.tcl     | 2 --
 projects/ad7616_sdz/zc706/system_project.tcl | 1 -
 4 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index a5813fae0..cb9e23293 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -94,7 +94,6 @@ module axi_ad7616 (
   // parameters
 
   parameter       ID = 0;
-  parameter       OP_MODE = 0;
   parameter       IF_TYPE = 0;
 
   // local parameters
@@ -404,8 +403,7 @@ module axi_ad7616 (
   endgenerate
 
   axi_ad7616_control #(
-    .ID(ID),
-    .OP_MODE (OP_MODE)
+    .ID(ID)
   ) i_ad7616_control (
     .cnvst (cnvst),
     .busy (busy),
diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index 37a0fa2f5..8e66a696a 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -64,7 +64,6 @@ module axi_ad7616_control (
 );
 
   parameter   ID = 0;
-  parameter   OP_MODE = 0;
 
   localparam  PCORE_VERSION = 'h0001001;
   localparam  SW = 0;
diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index 649b19680..cd5efc405 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -1,6 +1,5 @@
 
 global ad7616_if
-global ad7616_opm
 
 # data interfaces
 
@@ -23,7 +22,6 @@ create_bd_port -dir I busy
 # instantiation
 
 set axi_ad7616 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad7616:1.0 axi_ad7616]
-set_property -dict [list CONFIG.OP_MODE $ad7616_opm] $axi_ad7616
 set_property -dict [list CONFIG.IF_TYPE $ad7616_if] $axi_ad7616
 
 set axi_ad7616_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad7616_dma]
diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl
index 06b3ccf1b..9674b8585 100644
--- a/projects/ad7616_sdz/zc706/system_project.tcl
+++ b/projects/ad7616_sdz/zc706/system_project.tcl
@@ -21,7 +21,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 ##--------------------------------------------------------------
 
 set ad7616_if   0
-set ad7616_opm  0
 
 adi_project_create ad7616_sdz_zc706
 

From 170295161f78154fdf2d3986809a90893c675313 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 26 Jan 2016 11:19:00 -0500
Subject: [PATCH 065/972] pzsdr1- xdc

---
 .../common/pzsdr1/pzsdr1_system_constr.xdc    | 130 ++++++++----------
 1 file changed, 61 insertions(+), 69 deletions(-)

diff --git a/projects/common/pzsdr1/pzsdr1_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
index ef43a4869..78d73e959 100644
--- a/projects/common/pzsdr1/pzsdr1_system_constr.xdc
+++ b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
@@ -2,84 +2,76 @@
 # constraints
 # ad9361
 
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35
-set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35
-set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35
-set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35
-set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35
-set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35
-set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35
-set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35
-set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35
-set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35
-set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35
-set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35
-set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35
-set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35
-set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVDS}     [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35
-set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVDS}     [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35
-set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVDS}     [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVDS}     [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35
-set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVDS}     [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35
-set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35
-set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35
-set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35
-set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35
-set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35
-set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35
-set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35
-set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35
-set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVDS}     [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35
-set_property  -dict {PACKAGE_PIN  F14  IOSTANDARD LVCMOS18} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35
+set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35        
+set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35        
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35        
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35        
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35        
+set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35        
+set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35    
+set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35    
+set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35             
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35             
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35        
+set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35        
+set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35             
+set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35        
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS}     [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35       
+set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS}     [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35       
+set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS}     [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35    
+set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS}     [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35    
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS}     [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS}     [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35  
+set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS}     [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35  
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS}     [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35  
+set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS}     [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35  
+set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35            
+set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS}     [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35            
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS}     [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35       
+set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS}     [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS}     [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS}     [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
+set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS18} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
+set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS18} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
 
-set_property  -dict {PACKAGE_PIN  D13  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35
-set_property  -dict {PACKAGE_PIN  C13  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35
-set_property  -dict {PACKAGE_PIN  C14  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35
-set_property  -dict {PACKAGE_PIN  B14  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35
-set_property  -dict {PACKAGE_PIN  A15  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35
-set_property  -dict {PACKAGE_PIN  A14  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35
-set_property  -dict {PACKAGE_PIN  C12  IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35
-set_property  -dict {PACKAGE_PIN  B12  IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35
-set_property  -dict {PACKAGE_PIN  C2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34
-set_property  -dict {PACKAGE_PIN  B1   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34
-set_property  -dict {PACKAGE_PIN  B2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34
-set_property  -dict {PACKAGE_PIN  A2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34
-set_property  -dict {PACKAGE_PIN  G16  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35
-set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35
-set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS18} [get_ports gpio_resetb]                       ; ## IO_0_VRN_35
-set_property  -dict {PACKAGE_PIN  K11  IOSTANDARD LVCMOS18} [get_ports gpio_clksel]                       ; ## IO_0_VRN_34
+set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35            
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35       
+set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35       
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35       
+set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35  
+set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35  
+set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35       
+set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35       
+set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34            
+set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34            
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34            
+set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34            
+set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35      
+set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS18} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35      
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports gpio_resetb]                       ; ## IO_0_35                  
+set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS18} [get_ports gpio_clksel]                       ; ## IO_0_34                  
 
-set_property  -dict {PACKAGE_PIN  C11  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35
-set_property  -dict {PACKAGE_PIN  B11  IOSTANDARD LVCMOS18} [get_ports spi_clk]                           ; ## IO_L23N_T3_35
-set_property  -dict {PACKAGE_PIN  A13  IOSTANDARD LVCMOS18} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35
-set_property  -dict {PACKAGE_PIN  A12  IOSTANDARD LVCMOS18} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35
+set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35        
+set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS18} [get_ports spi_clk]                           ; ## IO_L23N_T3_35        
+set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS18} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35  
+set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS18} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35  
 
-set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports clk_out]                           ; ## IO_25_VRP_35
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports clk_out]                           ; ## IO_25_35
 
 # iic
 
-set_property  -dict {PACKAGE_PIN  AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L5P_T0_13             
-set_property  -dict {PACKAGE_PIN  AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L5N_T0_13             
+set_property  -dict {PACKAGE_PIN  W6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L22N_T3_13              
+set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L22P_T3_13              
 
 # gpio
 
-set_property  -dict {PACKAGE_PIN  J3   IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L12N_T1_MRCC_33       
-set_property  -dict {PACKAGE_PIN  D8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L8N_T1_34             
-set_property  -dict {PACKAGE_PIN  F9   IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9P_T1_DQS_34         
-set_property  -dict {PACKAGE_PIN  E8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]                        ; ## (pb)  IO_L9N_T1_DQS_34         
-set_property  -dict {PACKAGE_PIN  A8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]]                        ; ## (led) IO_L17N_T2_34            
-set_property  -dict {PACKAGE_PIN  W14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]]                        ; ## (led) IO_0_12                  
-set_property  -dict {PACKAGE_PIN  W17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]                        ; ## (led) IO_25_12                 
-set_property  -dict {PACKAGE_PIN  Y16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]                        ; ## (led) IO_L23P_T3_12            
-set_property  -dict {PACKAGE_PIN  Y15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]]                        ; ## (dip) IO_L23N_T3_12            
-set_property  -dict {PACKAGE_PIN  W16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]                        ; ## (dip) IO_L24P_T3_12            
-set_property  -dict {PACKAGE_PIN  W15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]]                       ; ## (dip) IO_L24N_T3_12            
-set_property  -dict {PACKAGE_PIN  V19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]                       ; ## (dip) IO_0_13                  
+set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
+set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
 
 # clocks
 

From fbb0d368bfed95c061869691db6ad269aa0b8855 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 28 Jan 2016 12:37:22 +0200
Subject: [PATCH 066/972] axi_ad7616: Add support for parallel interface

---
 library/axi_ad7616/axi_ad7616.v         |  53 ++++-
 library/axi_ad7616/axi_ad7616_control.v |  47 ++++-
 library/axi_ad7616/axi_ad7616_ip.tcl    |   1 +
 library/axi_ad7616/axi_ad7616_pif.v     | 254 ++++++++++++++++++++++++
 4 files changed, 347 insertions(+), 8 deletions(-)
 create mode 100644 library/axi_ad7616/axi_ad7616_pif.v

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index cb9e23293..efe33ec69 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -87,6 +87,7 @@ module axi_ad7616 (
   m_axis_tdata,
   m_axis_tvalid,
   m_axis_tready,
+  m_axis_xfer_req,
 
   irq
 );
@@ -94,7 +95,7 @@ module axi_ad7616 (
   // parameters
 
   parameter       ID = 0;
-  parameter       IF_TYPE = 0;
+  parameter       IF_TYPE = 1;
 
   // local parameters
 
@@ -145,6 +146,7 @@ module axi_ad7616 (
   output  [31:0]  m_axis_tdata;
   input           m_axis_tready;
   output          m_axis_tvalid;
+  input           m_axis_xfer_req;
 
   output          irq;
 
@@ -170,6 +172,13 @@ module axi_ad7616 (
 
   wire                              trigger_s;
 
+  wire                              rd_req_s;
+  wire                              wr_req_s;
+  wire    [15:0]                    wr_data_s;
+  wire    [15:0]                    rd_data_s;
+  wire                              rd_dvalid_s;
+  wire    [ 4:0]                    burst_length_s;
+
   // internal registers
 
   reg                               up_wack = 1'b0;
@@ -395,18 +404,56 @@ module axi_ad7616 (
       .three_wire ());
 
   end
+
   endgenerate
 
   generate if (IF_TYPE == PARALLEL) begin
-    //assign trigger_s = 1'b0;
+
+    assign sclk = 1'h0;
+    assign sdo = 1'h0;
+    assign irq = 1'h0;
+
+    assign up_wack_if_s = 1'h0;
+    assign up_rack_if_s = 1'h0;
+    assign up_rdata_if_s = 1'h0;
+
+    axi_ad7616_pif i_ad7616_parallel_interface (
+      .cs_n(cs_n),
+      .db_o(db_o),
+      .db_i(db_i),
+      .db_t(db_t),
+      .rd_n(rd_n),
+      .wr_n(wr_n),
+      .m_axis_tdata(m_axis_tdata),
+      .m_axis_tvalid(m_axis_tvalid),
+      .m_axis_tready(m_axis_tready),
+      .m_axis_xfer_req(m_axis_xfer_req),
+      .end_of_conv(trigger_s),
+      .burst_length(burst_length_s),
+      .clk(up_clk),
+      .rstn(up_rstn),
+      .rd_req(rd_req_s),
+      .wr_req(wr_req_s),
+      .wr_data(wr_data_s),
+      .rd_data(rd_data_s),
+      .rd_dvalid(rd_dvalid_s)
+    );
+
   end
   endgenerate
 
   axi_ad7616_control #(
-    .ID(ID)
+    .ID(ID),
+    .IF_TYPE(IF_TYPE)
   ) i_ad7616_control (
     .cnvst (cnvst),
     .busy (busy),
+    .up_burst_length (burst_length_s),
+    .up_read_data (rd_data_s),
+    .up_read_valid (rd_dvalid_s),
+    .up_write_data (wr_data_s),
+    .up_read_req (rd_req_s),
+    .up_write_req (wr_req_s),
     .end_of_conv (trigger_s),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index 8e66a696a..df101a1b8 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2013(c) Analog Devices, Inc.
+// Copyright 2015(c) Analog Devices, Inc.
 //
 // All rights reserved.
 //
@@ -46,6 +46,13 @@ module axi_ad7616_control (
   cnvst,
   busy,
 
+  up_read_data,
+  up_read_valid,
+  up_write_data,
+  up_read_req,
+  up_write_req,
+
+  up_burst_length,
   end_of_conv,
 
   // bus interface
@@ -64,17 +71,25 @@ module axi_ad7616_control (
 );
 
   parameter   ID = 0;
+  parameter   IF_TYPE = 0;
 
   localparam  PCORE_VERSION = 'h0001001;
-  localparam  SW = 0;
-  localparam  HW = 1;
   localparam  POS_EDGE = 0;
   localparam  NEG_EDGE = 1;
+  localparam  SERIAL = 0;
+  localparam  PARALLEL = 1;
 
   output          cnvst;
   input           busy;
 
   output          end_of_conv;
+  output  [ 4:0]  up_burst_length;
+
+  input   [15:0]  up_read_data;
+  input           up_read_valid;
+  output  [15:0]  up_write_data;
+  output          up_read_req;
+  output          up_write_req;
 
   // bus interface
 
@@ -98,6 +113,8 @@ module axi_ad7616_control (
   reg             up_rack = 1'b0;
   reg     [31:0]  up_rdata = 32'b0;
   reg     [31:0]  up_conv_rate = 32'b0;
+  reg     [ 4:0]  up_burst_length = 5'h0;
+  reg     [15:0]  up_write_data = 16'h0;
 
   reg     [31:0]  cnvst_counter = 32'b0;
   reg     [ 3:0]  pulse_counter = 8'b0;
@@ -110,12 +127,18 @@ module axi_ad7616_control (
   wire            up_wreq_s;
   wire            end_of_conv_s;
 
+  wire    [31:0]  up_read_data_s;
+  wire            up_read_valid_s;
+
   // decode block select
 
   assign up_wreq_s = (up_waddr[13:8] == 6'h01) ? up_wreq : 1'b0;
   assign up_rreq_s = (up_raddr[13:8] == 6'h01) ? up_rreq : 1'b0;
 
-  assign end_of_conv = end_of_conv_s;
+  // the up_[read/write]_data interfaces are valid just in parallel mode
+
+  assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
+  assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : 32'hDEAD;
 
   // processor write interface
 
@@ -126,6 +149,7 @@ module axi_ad7616_control (
       up_resetn <= 1'b0;
       up_cnvst_en <= 1'b0;
       up_conv_rate <= 32'b0;
+      up_burst_length <= 5'h0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@@ -138,9 +162,17 @@ module axi_ad7616_control (
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
         up_conv_rate <= up_wdata;
       end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
+        up_burst_length <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
+        up_write_data <= up_wdata;
+      end
     end
   end
 
+  assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0;
+
   // processor read interface
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -148,7 +180,7 @@ module axi_ad7616_control (
       up_rack <= 1'b0;
       up_rdata <= 32'b0;
     end else begin
-      up_rack <= up_rreq_s;
+      up_rack <= (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
       if (up_rreq_s == 1'b1) begin
         case (up_raddr[7:0])
             8'h00 : up_rdata = PCORE_VERSION;
@@ -156,11 +188,15 @@ module axi_ad7616_control (
             8'h02 : up_rdata = up_scratch;
             8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
             8'h11 : up_rdata = up_conv_rate;
+            8'h12 : up_rdata = up_burst_length;
+            8'h13 : up_rdata = up_read_data_s;
         endcase
       end
     end
   end
 
+  assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0;
+
   // instantiations
 
   assign up_rst = ~up_rstn;
@@ -207,6 +243,7 @@ module axi_ad7616_control (
   end
 
   assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
+  assign end_of_conv = end_of_conv_s;
 
 endmodule
 
diff --git a/library/axi_ad7616/axi_ad7616_ip.tcl b/library/axi_ad7616/axi_ad7616_ip.tcl
index 1ebd172e6..a9cf3a196 100644
--- a/library/axi_ad7616/axi_ad7616_ip.tcl
+++ b/library/axi_ad7616/axi_ad7616_ip.tcl
@@ -7,6 +7,7 @@ adi_ip_create axi_ad7616
 adi_ip_files axi_ad7616 [list \
     "axi_ad7616.v" \
     "axi_ad7616_control.v" \
+    "axi_ad7616_pif.v" \
     "$ad_hdl_dir/library/common/ad_edge_detect.v" \
     "$ad_hdl_dir/library/common/up_axi.v"]
 
diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v
new file mode 100644
index 000000000..75a8618f9
--- /dev/null
+++ b/library/axi_ad7616/axi_ad7616_pif.v
@@ -0,0 +1,254 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2015(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad7616_pif (
+
+  // physical interface
+
+  cs_n,
+  db_o,
+  db_i,
+  db_t,
+  rd_n,
+  wr_n,
+
+  // axi stream master
+
+  m_axis_tdata,
+  m_axis_tvalid,
+  m_axis_tready,
+  m_axis_xfer_req,
+
+  // end of convertion
+
+  end_of_conv,
+  burst_length,
+
+  // register access
+
+  clk,
+  rstn,
+  rd_req,
+  wr_req,
+  wr_data,
+  rd_data,
+  rd_dvalid
+);
+
+  parameter UP_ADDRESS_WIDTH = 14;
+
+  // IO definitions
+
+  output                          cs_n;
+  output  [15:0]                  db_o;
+  input   [15:0]                  db_i;
+  output                          db_t;
+  output                          rd_n;
+  output                          wr_n;
+
+  input                           end_of_conv;
+  input   [ 4:0]                  burst_length;
+
+  input                           clk;
+  input                           rstn;
+  input                           rd_req;
+  input                           wr_req;
+  input   [15:0]                  wr_data;
+  output  [15:0]                  rd_data;
+  output                          rd_dvalid;
+
+  output  [31:0]                  m_axis_tdata;
+  input                           m_axis_tready;
+  output                          m_axis_tvalid;
+  input                           m_axis_xfer_req;
+
+  // state registers
+
+  localparam  [ 2:0]    IDLE = 3'h0,
+                        CS_LOW = 3'h1,
+                        CNTRL0_LOW = 3'h2,
+                        CNTRL0_HIGH = 3'h3,
+                        CNTRL1_LOW = 3'h4,
+                        CNTRL1_HIGH = 3'h5,
+                        CS_HIGH = 3'h6;
+
+  // internal registers
+
+  reg     [ 2:0]                  transfer_state = 3'h0;
+  reg     [ 2:0]                  transfer_state_next = 3'h0;
+  reg     [ 1:0]                  counter = 2'h0;
+  reg     [ 4:0]                  burst_counter = 5'h0;
+
+  reg                             wr_req_d = 1'h0;
+  reg                             rd_req_d = 1'h0;
+  reg                             rd_conv_d = 1'h0;
+
+  reg                             xfer_req_d = 1'h0;
+
+  reg     [15:0]                  data_out_a = 16'h0;
+  reg     [15:0]                  data_out_b = 16'h0;
+  reg                             rd_db_valid_div2 = 1'h0;
+
+  // internal wires
+
+  wire                            start_transfer;
+  wire                            rd_db_valid;
+
+  // FSM state register
+
+  always @(posedge clk) begin
+    if (rstn == 1'b0) begin
+      transfer_state <= 3'h0;
+    end else begin
+      transfer_state <= transfer_state_next;
+    end
+  end
+
+  // counters to control the RD_N and WR_N lines
+
+  assign start_transfer = end_of_conv | rd_req | wr_req;
+
+  always @(posedge clk) begin
+    if (rstn == 1'b0) begin
+      counter <= 2'h0;
+    end else begin
+      if((transfer_state == CNTRL0_LOW) || (transfer_state == CNTRL0_HIGH) ||
+         (transfer_state == CNTRL1_LOW) || (transfer_state == CNTRL1_HIGH))
+        counter <= counter + 1;
+      else
+        counter <= 2'h0;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (rstn == 1'b0) begin
+      burst_counter <= 2'h0;
+    end else begin
+      if((transfer_state == CS_HIGH) && (rd_conv_d == 1'b1))
+        burst_counter <= burst_counter + 1;
+      else if (transfer_state == IDLE)
+        burst_counter <= 5'h0;
+    end
+  end
+
+  always @(negedge clk) begin
+    if (transfer_state == IDLE) begin
+      wr_req_d <= wr_req;
+      rd_req_d <= rd_req;
+      rd_conv_d <= end_of_conv;
+    end
+  end
+
+  // FSM next state logic
+
+  always @(*) begin
+    case (transfer_state)
+      IDLE : begin
+        transfer_state_next <= (start_transfer == 1'b1) ? CS_LOW : IDLE;
+      end
+      CS_LOW : begin
+        transfer_state_next <= CNTRL0_LOW;
+      end
+      CNTRL0_LOW : begin
+        transfer_state_next <= (counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH;
+      end
+      CNTRL0_HIGH : begin
+        transfer_state_next <= (counter != 2'b11) ? CNTRL0_HIGH :
+                               ((wr_req_d == 1'b1) || (rd_req_d == 1'b1)) ? CS_HIGH : CNTRL1_LOW;
+      end
+      CNTRL1_LOW : begin
+        transfer_state_next <= (counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH;
+      end
+      CNTRL1_HIGH : begin
+        transfer_state_next <= (counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
+      end
+      CS_HIGH : begin
+        transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW;
+      end
+      default : begin
+        transfer_state_next <= IDLE;
+      end
+    endcase
+  end
+
+  // data valid for the register access and m_axis interface
+
+  assign rd_db_valid = ((counter == 2'b0) && ((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH))) ? 1'b1 : 1'b0;
+
+  always @(posedge clk) begin
+    if (cs_n) begin
+      rd_db_valid_div2 <= 1'h0;
+    end else begin
+      rd_db_valid_div2 <= (rd_db_valid) ? ~rd_db_valid_div2 : rd_db_valid_div2;
+    end
+  end
+
+  // FSM output logic
+
+  assign db_o = wr_data;
+
+  always @(posedge clk) begin
+    data_out_a <= (rd_db_valid) ? db_i : data_out_a;
+    data_out_b <= (rd_db_valid) ? data_out_a : data_out_b;
+  end
+
+  assign rd_data = data_out_a;
+  assign rd_dvalid = rd_db_valid;
+
+  assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
+  assign db_t = ~wr_req_d;
+  assign rd_n = (((transfer_state == CNTRL0_LOW) && ((rd_conv_d == 1'b1) || rd_req_d == 1'b1)) ||
+                  (transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1;
+  assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1;
+
+  // Master AXI stream output logic with additional xfer_req signal
+  // The first valid data is ALWAYS the first sample of a convertion
+
+  always @(negedge clk) begin
+    if (end_of_conv == 1'b1)
+      xfer_req_d <= m_axis_xfer_req;
+  end
+
+  assign m_axis_tdata = rd_data;
+  assign m_axis_tvalid = xfer_req_d & rd_db_valid & rd_db_valid_div2;
+
+endmodule
+

From 118577f64fff08f3fee315a46e4852de99b6d818 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 28 Jan 2016 12:38:22 +0200
Subject: [PATCH 067/972] ad7616_sdz: Add support for parallel interface

---
 projects/ad7616_sdz/common/ad7616_bd.tcl      |  15 +-
 .../ad7616_sdz/zc706/parallel_if_constr.xdc   |  56 ++--
 projects/ad7616_sdz/zc706/system_project.tcl  |   9 +-
 projects/ad7616_sdz/zc706/system_top_pi.v     | 248 ++++++++++++++++++
 .../zc706/{system_top.v => system_top_si.v}   |   0
 5 files changed, 293 insertions(+), 35 deletions(-)
 create mode 100644 projects/ad7616_sdz/zc706/system_top_pi.v
 rename projects/ad7616_sdz/zc706/{system_top.v => system_top_si.v} (100%)

diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index cd5efc405..0cf4e3178 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -10,6 +10,7 @@ create_bd_port -dir I sdi_1
 
 create_bd_port -dir O -from 15 -to 0 db_o
 create_bd_port -dir I -from 15 -to 0 db_i
+create_bd_port -dir O db_t
 create_bd_port -dir O rd_n
 create_bd_port -dir O wr_n
 
@@ -46,10 +47,22 @@ if {$ad7616_if == 0} {
 
 } else {
 
+  ad_connect  db_o axi_ad7616/db_o
+  ad_connect  db_i axi_ad7616/db_i
+  ad_connect  db_t axi_ad7616/db_t
+  ad_connect  rd_n axi_ad7616/rd_n
+  ad_connect  wr_n axi_ad7616/wr_n
+
+  ad_connect  cs_n axi_ad7616/cs_n
+  ad_connect  cnvst axi_ad7616/cnvst
+  ad_connect  busy axi_ad7616/busy
+
+
 }
 
-ad_connect  axi_ad7616/m_axis axi_ad7616_dma/s_axis
 ad_connect  sys_cpu_clk axi_ad7616_dma/s_axis_aclk
+ad_connect  axi_ad7616/m_axis axi_ad7616_dma/s_axis
+ad_connect  axi_ad7616/m_axis_xfer_req axi_ad7616_dma/s_axis_xfer_req
 
 # interconnect
 
diff --git a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
index af2f8f3f9..58144b770 100644
--- a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
+++ b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
@@ -1,36 +1,36 @@
 
 # ad7616
 
-set_property -dict {PACKAGE_PIN AC14     IOSTANDARD LVCMOS25} [get_ports db[0] ]         ; ## FMC_LPC_LA10_P
-set_property -dict {PACKAGE_PIN AJ15     IOSTANDARD LVCMOS25} [get_ports db[1] ]         ; ## FMC_LPC_LA04_P
-set_property -dict {PACKAGE_PIN AH14     IOSTANDARD LVCMOS25} [get_ports db[2] ]         ; ## FMC_LPC_LA09_P
-set_property -dict {PACKAGE_PIN AG12     IOSTANDARD LVCMOS25} [get_ports db[3] ]         ; ## FMC_LPC_LA03_P
-set_property -dict {PACKAGE_PIN AE15     IOSTANDARD LVCMOS25} [get_ports db[4] ]         ; ## FMC_LPC_LA05_N
-set_property -dict {PACKAGE_PIN AF12     IOSTANDARD LVCMOS25} [get_ports db[5] ]         ; ## FMC_LPC_LA02_N
-set_property -dict {PACKAGE_PIN AC12     IOSTANDARD LVCMOS25} [get_ports db[6] ]         ; ## FMC_LPC_LA06_N
-set_property -dict {PACKAGE_PIN AF13     IOSTANDARD LVCMOS25} [get_ports db[7] ]         ; ## FMC_LPC_LA00_CC_N
-set_property -dict {PACKAGE_PIN AE16     IOSTANDARD LVCMOS25} [get_ports db[8] ]         ; ## FMC_LPC_LA05_P
-set_property -dict {PACKAGE_PIN AE12     IOSTANDARD LVCMOS25} [get_ports db[9] ]         ; ## FMC_LPC_LA02_P
-set_property -dict {PACKAGE_PIN AE17     IOSTANDARD LVCMOS25} [get_ports db[10]]         ; ## FMC_LPC_LA16_N
-set_property -dict {PACKAGE_PIN AE13     IOSTANDARD LVCMOS25} [get_ports db[11]]         ; ## FMC_LPC_LA00_CC_P
-set_property -dict {PACKAGE_PIN AG15     IOSTANDARD LVCMOS25} [get_ports db[12]]         ; ## FMC_LPC_LA01_CC_N
-set_property -dict {PACKAGE_PIN AG16     IOSTANDARD LVCMOS25} [get_ports db[13]]         ; ## FMC_LPC_CLK0_M2C_N
-set_property -dict {PACKAGE_PIN AG17     IOSTANDARD LVCMOS25} [get_ports db[14]]         ; ## FMC_LPC_CLK0_M2C_P
-set_property -dict {PACKAGE_PIN AF15     IOSTANDARD LVCMOS25} [get_ports db[15]]         ; ## FMC_LPC_LA01_CC_P
+set_property -dict {PACKAGE_PIN AC14     IOSTANDARD LVCMOS25} [get_ports adc_db[0] ]         ; ## FMC_LPC_LA10_P
+set_property -dict {PACKAGE_PIN AJ15     IOSTANDARD LVCMOS25} [get_ports adc_db[1] ]         ; ## FMC_LPC_LA04_P
+set_property -dict {PACKAGE_PIN AH14     IOSTANDARD LVCMOS25} [get_ports adc_db[2] ]         ; ## FMC_LPC_LA09_P
+set_property -dict {PACKAGE_PIN AG12     IOSTANDARD LVCMOS25} [get_ports adc_db[3] ]         ; ## FMC_LPC_LA03_P
+set_property -dict {PACKAGE_PIN AE15     IOSTANDARD LVCMOS25} [get_ports adc_db[4] ]         ; ## FMC_LPC_LA05_N
+set_property -dict {PACKAGE_PIN AF12     IOSTANDARD LVCMOS25} [get_ports adc_db[5] ]         ; ## FMC_LPC_LA02_N
+set_property -dict {PACKAGE_PIN AC12     IOSTANDARD LVCMOS25} [get_ports adc_db[6] ]         ; ## FMC_LPC_LA06_N
+set_property -dict {PACKAGE_PIN AF13     IOSTANDARD LVCMOS25} [get_ports adc_db[7] ]         ; ## FMC_LPC_LA00_CC_N
+set_property -dict {PACKAGE_PIN AE16     IOSTANDARD LVCMOS25} [get_ports adc_db[8] ]         ; ## FMC_LPC_LA05_P
+set_property -dict {PACKAGE_PIN AE12     IOSTANDARD LVCMOS25} [get_ports adc_db[9] ]         ; ## FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN AE17     IOSTANDARD LVCMOS25} [get_ports adc_db[10]]         ; ## FMC_LPC_LA16_N
+set_property -dict {PACKAGE_PIN AE13     IOSTANDARD LVCMOS25} [get_ports adc_db[11]]         ; ## FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN AG15     IOSTANDARD LVCMOS25} [get_ports adc_db[12]]         ; ## FMC_LPC_LA01_CC_N
+set_property -dict {PACKAGE_PIN AG16     IOSTANDARD LVCMOS25} [get_ports adc_db[13]]         ; ## FMC_LPC_CLK0_M2C_N
+set_property -dict {PACKAGE_PIN AG17     IOSTANDARD LVCMOS25} [get_ports adc_db[14]]         ; ## FMC_LPC_CLK0_M2C_P
+set_property -dict {PACKAGE_PIN AF15     IOSTANDARD LVCMOS25} [get_ports adc_db[15]]         ; ## FMC_LPC_LA01_CC_P
 
-set_property -dict {PACKAGE_PIN AH12     IOSTANDARD LVCMOS25} [get_ports rd_n]           ; ## FMC_LPC_LA03_N
-set_property -dict {PACKAGE_PIN AH13     IOSTANDARD LVCMOS25} [get_ports wr_n]           ; ## FMC_LPC_LA09_N
+set_property -dict {PACKAGE_PIN AH12     IOSTANDARD LVCMOS25} [get_ports adc_rd_n]           ; ## FMC_LPC_LA03_N
+set_property -dict {PACKAGE_PIN AH13     IOSTANDARD LVCMOS25} [get_ports adc_wr_n]           ; ## FMC_LPC_LA09_N
 
 # control lines
 
-set_property -dict {PACKAGE_PIN AF30     IOSTANDARD LVCOMS25} [get_ports convst]         ; ## FMC_LPC_LA24_P
-set_property -dict {PACKAGE_PIN AH29     IOSTANDARD LVCOMS25} [get_ports chsel[0]]       ; ## FMC_LPC_LA21_N
-set_property -dict {PACKAGE_PIN AK30     IOSTANDARD LVCOMS25} [get_ports chsel[1]]       ; ## FMC_LPC_LA26_N
-set_property -dict {PACKAGE_PIN AF29     IOSTANDARD LVCOMS25} [get_ports chsel[2]]       ; ## FMC_LPC_LA25_P
-set_property -dict {PACKAGE_PIN AH28     IOSTANDARD LVCOMS25} [get_ports hw_rngsel[0]]   ; ## FMC_LPC_LA21_P
-set_property -dict {PACKAGE_PIN AJ30     IOSTANDARD LVCOMS25} [get_ports hw_rngsel[1]]   ; ## FMC_LPC_LA26_P
-set_property -dict {PACKAGE_PIN AC13     IOSTANDARD LVCOMS25} [get_ports busy]           ; ## FMC_LPC_LA10_N
-set_property -dict {PACKAGE_PIN AJ28     IOSTANDARD LVCOMS25} [get_ports seq_en]         ; ## FMC_LPC_LA27_P
-set_property -dict {PACKAGE_PIN AK28     IOSTANDARD LVCOMS25} [get_ports reset_n]        ; ## FMC_LPC_LA22_N
-set_property -dict {PACKAGE_PIN AK15     IOSTANDARD LVCOMS25} [get_ports cs_n]           ; ## FMC_LPC_LA04_N
+set_property -dict {PACKAGE_PIN AF30     IOSTANDARD LVCMOS25} [get_ports adc_convst]         ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN AH29     IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]]       ; ## FMC_LPC_LA21_N
+set_property -dict {PACKAGE_PIN AK30     IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]]       ; ## FMC_LPC_LA26_N
+set_property -dict {PACKAGE_PIN AF29     IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]]       ; ## FMC_LPC_LA25_P
+set_property -dict {PACKAGE_PIN AH28     IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]]   ; ## FMC_LPC_LA21_P
+set_property -dict {PACKAGE_PIN AJ30     IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]]   ; ## FMC_LPC_LA26_P
+set_property -dict {PACKAGE_PIN AC13     IOSTANDARD LVCMOS25} [get_ports adc_busy]           ; ## FMC_LPC_LA10_N
+set_property -dict {PACKAGE_PIN AJ28     IOSTANDARD LVCMOS25} [get_ports adc_seq_en]         ; ## FMC_LPC_LA27_P
+set_property -dict {PACKAGE_PIN AK28     IOSTANDARD LVCMOS25} [get_ports adc_reset_n]        ; ## FMC_LPC_LA22_N
+set_property -dict {PACKAGE_PIN AK15     IOSTANDARD LVCMOS25} [get_ports adc_cs_n]           ; ## FMC_LPC_LA04_N
 
diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl
index 9674b8585..f94873678 100644
--- a/projects/ad7616_sdz/zc706/system_project.tcl
+++ b/projects/ad7616_sdz/zc706/system_project.tcl
@@ -6,12 +6,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 ##--------------------------------------------------------------
 # IMPORTANT: Set AD7616 operation and interface mode
 #
-#    ad7616_opm - Defines the operation mode (software OR hardware)
 #    ad7616_if  - Defines the interface type (serial OR parallel)
 #
-# LEGEND: Software  - 0
-#         Hardware  - 1
-#         Serial    - 0
+# LEGEND: Serial    - 0
 #         Parallel  - 1
 #
 # NOTE : These switches are 'hardware' switches. User needs to
@@ -28,7 +25,7 @@ if { $ad7616_if == 0 } {
 
   adi_project_files ad7616_sdz_zc706 [list \
     "$ad_hdl_dir/library/common/ad_iobuf.v" \
-    "system_top.v" \
+    "system_top_si.v" \
     "serial_if_constr.xdc" \
     "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
 
@@ -36,7 +33,7 @@ if { $ad7616_if == 0 } {
 
   adi_project_files ad7616_sdz_zc706 [list \
     "$ad_hdl_dir/library/common/ad_iobuf.v" \
-    "system_top.v" \
+    "system_top_pi.v" \
     "parallel_if_constr.xdc" \
     "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
 
diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v
new file mode 100644
index 000000000..2f80c97d8
--- /dev/null
+++ b/projects/ad7616_sdz/zc706/system_top_pi.v
@@ -0,0 +1,248 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  gpio_bd,
+
+  hdmi_out_clk,
+  hdmi_vsync,
+  hdmi_hsync,
+  hdmi_data_e,
+  hdmi_data,
+
+  spdif,
+
+  iic_scl,
+  iic_sda,
+
+  adc_db,
+  adc_rd_n,
+  adc_wr_n,
+
+  adc_cs_n,
+  adc_reset_n,
+  adc_convst,
+  adc_busy,
+  adc_seq_en,
+  adc_hw_rngsel,
+  adc_chsel,
+  adc_crcen,
+  adc_burst,
+  adc_os);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout   [14:0]  gpio_bd;
+
+  output          hdmi_out_clk;
+  output          hdmi_vsync;
+  output          hdmi_hsync;
+  output          hdmi_data_e;
+  output  [23:0]  hdmi_data;
+
+  output          spdif;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  inout   [15:0]  adc_db;
+  output          adc_rd_n;
+  output          adc_wr_n;
+
+  output          adc_cs_n;
+  output          adc_reset_n;
+  output          adc_convst;
+  output          adc_busy;
+  output          adc_seq_en;
+  output  [ 1:0]  adc_hw_rngsel;
+  output  [ 2:0]  adc_chsel;
+  output          adc_crcen;
+  output          adc_burst;
+  output  [ 2:0]  adc_os;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  wire            adc_db_t;
+  wire    [15:0]  adc_db_o;
+  wire    [15:0]  adc_db_i;
+
+  genvar i;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
+    .dio_t (gpio_t[43:32]),
+    .dio_i (gpio_o[43:32]),
+    .dio_o (gpio_i[43:32]),
+    .dio_p ({adc_reset_n,        // 43
+             adc_hw_rngsel,      // 42:41
+             adc_os,             // 40:38
+             adc_seq_en,         // 37
+             adc_burst,          // 36
+             adc_chsel,          // 35:33
+             adc_crcen}));       // 32
+
+  generate
+    for (i = 0; i < 16; i = i + 1) begin: adc_db_io
+      ad_iobuf i_adc_db (
+        .dio_t(adc_db_t),
+        .dio_i(adc_db_o[i]),
+        .dio_o(adc_db_i[i]),
+        .dio_p(adc_db[i]));
+    end
+  endgenerate
+
+  ad_iobuf #(
+    .DATA_WIDTH(15)
+  ) i_gpio_bd (
+    .dio_t(gpio_t[14:0]),
+    .dio_i(gpio_o[14:0]),
+    .dio_o(gpio_i[14:0]),
+    .dio_p(gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .spdif (spdif),
+    .cnvst (adc_convst),
+    .cs_n (adc_cs_n),
+    .busy (adc_busy),
+    .db_o (adc_db_o),
+    .db_i (adc_db_i),
+    .db_t (adc_db_t),
+    .rd_n (adc_rd_n),
+    .wr_n (adc_wr_n)
+  );
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/ad7616_sdz/zc706/system_top.v b/projects/ad7616_sdz/zc706/system_top_si.v
similarity index 100%
rename from projects/ad7616_sdz/zc706/system_top.v
rename to projects/ad7616_sdz/zc706/system_top_si.v

From 122667259f97a47b8028996bfd600a321c1b5ee4 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 28 Jan 2016 14:48:44 +0200
Subject: [PATCH 068/972] ad7616_sdz: Update Make file

---
 library/axi_ad7616/Makefile                    | 3 +++
 library/spi_engine/spi_engine_offload/Makefile | 1 +
 projects/ad7616_sdz/zc706/Makefile             | 6 ++----
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile
index 82f6c7bd0..0e1c103ae 100644
--- a/library/axi_ad7616/Makefile
+++ b/library/axi_ad7616/Makefile
@@ -10,6 +10,9 @@ M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_ad7616.v
 M_DEPS += axi_ad7616_control.v
+M_DEPS += axi_ad7616_pif.v
+M_DEPS += ../common/ad_edge_detect.v
+M_DEPS += ../common/up_axi.v
 M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
 M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
 M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
diff --git a/library/spi_engine/spi_engine_offload/Makefile b/library/spi_engine/spi_engine_offload/Makefile
index f48f54660..792b3ccd4 100644
--- a/library/spi_engine/spi_engine_offload/Makefile
+++ b/library/spi_engine/spi_engine_offload/Makefile
@@ -8,6 +8,7 @@
 M_DEPS := spi_engine_offload_ip.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
+M_DEPS += ../../common/sync_bits.v
 M_DEPS += spi_engine_offload.v
 
 M_VIVADO := vivado -mode batch -source
diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile
index c98945b51..fa9f0c96a 100644
--- a/projects/ad7616_sdz/zc706/Makefile
+++ b/projects/ad7616_sdz/zc706/Makefile
@@ -5,8 +5,8 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS += system_top.v
-M_DEPS += system_top.v
+M_DEPS += system_top_si.v
+M_DEPS += system_top_pi.v
 M_DEPS += system_project.tcl
 M_DEPS += system_bd.tcl
 M_DEPS += serial_if_constr.xdc
@@ -38,8 +38,6 @@ M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
 M_FLIST += .Xil
-M_FLIST += *.hw
-M_FLIST += *.sim
 
 
 

From 3d3d1098b4ff5d4d52c8915bddc881d99caa3628 Mon Sep 17 00:00:00 2001
From: Dragos Bogdan <dragos.bogdan@analog.com>
Date: Thu, 28 Jan 2016 16:02:01 +0200
Subject: [PATCH 069/972] axi_ad7616: Default DATA_WIDTH is 8 bits

---
 library/axi_ad7616/axi_ad7616.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index efe33ec69..ec85161a2 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -99,7 +99,7 @@ module axi_ad7616 (
 
   // local parameters
 
-  localparam      DATA_WIDTH = 16;
+  localparam      DATA_WIDTH = 8;
   localparam      NUM_OF_SDI = 2;
   localparam      SERIAL = 0;
   localparam      PARALLEL = 1;

From 59783f6cffe8095fdaa9ec41d6289cbc96aefa94 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 29 Jan 2016 15:28:06 +0200
Subject: [PATCH 070/972] ad7616_sdz: Add support for Zedboard

---
 projects/ad7616_sdz/Makefile                  |   3 +
 projects/ad7616_sdz/zed/Makefile              |  79 +++++
 .../ad7616_sdz/zed/parallel_if_constr.xdc     |  37 +++
 projects/ad7616_sdz/zed/serial_if_constr.xdc  |  29 ++
 projects/ad7616_sdz/zed/system_bd.tcl         |   4 +
 projects/ad7616_sdz/zed/system_project.tcl    |  47 +++
 projects/ad7616_sdz/zed/system_top_pi.v       | 302 ++++++++++++++++++
 projects/ad7616_sdz/zed/system_top_si.v       | 287 +++++++++++++++++
 8 files changed, 788 insertions(+)
 create mode 100644 projects/ad7616_sdz/zed/Makefile
 create mode 100644 projects/ad7616_sdz/zed/parallel_if_constr.xdc
 create mode 100644 projects/ad7616_sdz/zed/serial_if_constr.xdc
 create mode 100644 projects/ad7616_sdz/zed/system_bd.tcl
 create mode 100644 projects/ad7616_sdz/zed/system_project.tcl
 create mode 100644 projects/ad7616_sdz/zed/system_top_pi.v
 create mode 100644 projects/ad7616_sdz/zed/system_top_si.v

diff --git a/projects/ad7616_sdz/Makefile b/projects/ad7616_sdz/Makefile
index 5b866a1ac..8c0cfc6f5 100644
--- a/projects/ad7616_sdz/Makefile
+++ b/projects/ad7616_sdz/Makefile
@@ -8,14 +8,17 @@
 .PHONY: all clean clean-all 
 all:
 	-make -C zc706 all
+	-make -C zed all
 
 
 clean: 
 	make -C zc706 clean
+	make -C zed clean
 
 
 clean-all:
 	make -C zc706 clean-all
+	make -C zed clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile
new file mode 100644
index 000000000..2923b2ef6
--- /dev/null
+++ b/projects/ad7616_sdz/zed/Makefile
@@ -0,0 +1,79 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top_si.v
+M_DEPS += system_top_pi.v
+M_DEPS += system_project.tcl
+M_DEPS += system_bd.tcl
+M_DEPS += serial_if_constr.xdc
+M_DEPS += parallel_if_constr.xdc
+M_DEPS += ../common/ad7616_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zed/zed_system_constr.xdc
+M_DEPS += ../../common/zed/zed_system_constr.xdc
+M_DEPS += ../../common/zed/zed_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib ad7616_sdz_zed.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad7616 clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_i2s_adi clean
+	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_i2c_mixer clean
+
+
+ad7616_sdz_zed.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> ad7616_sdz_zed_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad7616
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_i2s_adi
+	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_i2c_mixer
+
+####################################################################################
+####################################################################################
diff --git a/projects/ad7616_sdz/zed/parallel_if_constr.xdc b/projects/ad7616_sdz/zed/parallel_if_constr.xdc
new file mode 100644
index 000000000..914a15002
--- /dev/null
+++ b/projects/ad7616_sdz/zed/parallel_if_constr.xdc
@@ -0,0 +1,37 @@
+
+# ad7616
+
+set_property -dict {PACKAGE_PIN R19     IOSTANDARD LVCMOS25} [get_ports adc_db[0] ]         ; ## FMC_LPC_LA10_P
+set_property -dict {PACKAGE_PIN M21     IOSTANDARD LVCMOS25} [get_ports adc_db[1] ]         ; ## FMC_LPC_LA04_P
+set_property -dict {PACKAGE_PIN R20     IOSTANDARD LVCMOS25} [get_ports adc_db[2] ]         ; ## FMC_LPC_LA09_P
+set_property -dict {PACKAGE_PIN N22     IOSTANDARD LVCMOS25} [get_ports adc_db[3] ]         ; ## FMC_LPC_LA03_P
+
+set_property -dict {PACKAGE_PIN K18     IOSTANDARD LVCMOS25} [get_ports adc_db[4] ]         ; ## FMC_LPC_LA05_N
+set_property -dict {PACKAGE_PIN P18     IOSTANDARD LVCMOS25} [get_ports adc_db[5] ]         ; ## FMC_LPC_LA02_N
+set_property -dict {PACKAGE_PIN L22     IOSTANDARD LVCMOS25} [get_ports adc_db[6] ]         ; ## FMC_LPC_LA06_N
+set_property -dict {PACKAGE_PIN M20     IOSTANDARD LVCMOS25} [get_ports adc_db[7] ]         ; ## FMC_LPC_LA00_CC_N
+set_property -dict {PACKAGE_PIN J18     IOSTANDARD LVCMOS25} [get_ports adc_db[8] ]         ; ## FMC_LPC_LA05_P
+set_property -dict {PACKAGE_PIN P17     IOSTANDARD LVCMOS25} [get_ports adc_db[9] ]         ; ## FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN K21     IOSTANDARD LVCMOS25} [get_ports adc_db[10]]         ; ## FMC_LPC_LA16_N
+set_property -dict {PACKAGE_PIN M19     IOSTANDARD LVCMOS25} [get_ports adc_db[11]]         ; ## FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN N20     IOSTANDARD LVCMOS25} [get_ports adc_db[12]]         ; ## FMC_LPC_LA01_CC_N
+set_property -dict {PACKAGE_PIN L19     IOSTANDARD LVCMOS25} [get_ports adc_db[13]]         ; ## FMC_LPC_CLK0_M2C_N
+set_property -dict {PACKAGE_PIN L18     IOSTANDARD LVCMOS25} [get_ports adc_db[14]]         ; ## FMC_LPC_CLK0_M2C_P
+set_property -dict {PACKAGE_PIN N19     IOSTANDARD LVCMOS25} [get_ports adc_db[15]]         ; ## FMC_LPC_LA01_CC_P
+
+set_property -dict {PACKAGE_PIN P22     IOSTANDARD LVCMOS25} [get_ports adc_rd_n]           ; ## FMC_LPC_LA03_N
+set_property -dict {PACKAGE_PIN R21     IOSTANDARD LVCMOS25} [get_ports adc_wr_n]           ; ## FMC_LPC_LA09_N
+
+# control lines
+
+set_property -dict {PACKAGE_PIN A18     IOSTANDARD LVCMOS25} [get_ports adc_convst]         ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN E20     IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]]       ; ## FMC_LPC_LA21_N
+set_property -dict {PACKAGE_PIN E18     IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]]       ; ## FMC_LPC_LA26_N
+set_property -dict {PACKAGE_PIN D22     IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]]       ; ## FMC_LPC_LA25_P
+set_property -dict {PACKAGE_PIN E19     IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]]   ; ## FMC_LPC_LA21_P
+set_property -dict {PACKAGE_PIN F18     IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]]   ; ## FMC_LPC_LA26_P
+set_property -dict {PACKAGE_PIN T19     IOSTANDARD LVCMOS25} [get_ports adc_busy]           ; ## FMC_LPC_LA10_N
+set_property -dict {PACKAGE_PIN E21     IOSTANDARD LVCMOS25} [get_ports adc_seq_en]         ; ## FMC_LPC_LA27_P
+set_property -dict {PACKAGE_PIN F19     IOSTANDARD LVCMOS25} [get_ports adc_reset_n]        ; ## FMC_LPC_LA22_N
+set_property -dict {PACKAGE_PIN M22     IOSTANDARD LVCMOS25} [get_ports adc_cs_n]           ; ## FMC_LPC_LA04_N
+
diff --git a/projects/ad7616_sdz/zed/serial_if_constr.xdc b/projects/ad7616_sdz/zed/serial_if_constr.xdc
new file mode 100644
index 000000000..ab6704dba
--- /dev/null
+++ b/projects/ad7616_sdz/zed/serial_if_constr.xdc
@@ -0,0 +1,29 @@
+
+# ad7616
+
+# data interface
+
+set_property -dict {PACKAGE_PIN P22      IOSTANDARD LVCMOS25} [get_ports spi_sclk]            ; ## FMC_LPC_LA03_N
+set_property -dict {PACKAGE_PIN L21      IOSTANDARD LVCMOS25} [get_ports spi_sdo]             ; ## FMC_LPC_LA06_P
+set_property -dict {PACKAGE_PIN M19      IOSTANDARD LVCMOS25} [get_ports spi_sdi_0]           ; ## FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN N20      IOSTANDARD LVCMOS25} [get_ports spi_sdi_1]           ; ## FMC_LPC_LA01_CC_N
+set_property -dict {PACKAGE_PIN M22      IOSTANDARD LVCMOS25} [get_ports spi_cs_n]            ; ## FMC_LPC_LA04_N
+
+# control lines
+
+set_property -dict {PACKAGE_PIN A18      IOSTANDARD LVCMOS25} [get_ports adc_convst]          ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN E20      IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]]        ; ## FMC_LPC_LA21_N
+set_property -dict {PACKAGE_PIN E18      IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]]        ; ## FMC_LPC_LA26_N
+set_property -dict {PACKAGE_PIN D22      IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]]        ; ## FMC_LPC_LA25_P
+set_property -dict {PACKAGE_PIN E19      IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]]    ; ## FMC_LPC_LA21_P
+set_property -dict {PACKAGE_PIN F18      IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]]    ; ## FMC_LPC_LA26_P
+set_property -dict {PACKAGE_PIN T19      IOSTANDARD LVCMOS25} [get_ports adc_busy]            ; ## FMC_LPC_LA10_N
+set_property -dict {PACKAGE_PIN E21      IOSTANDARD LVCMOS25} [get_ports adc_seq_en]          ; ## FMC_LPC_LA27_P
+set_property -dict {PACKAGE_PIN F19      IOSTANDARD LVCMOS25} [get_ports adc_reset_n]         ; ## FMC_LPC_LA22_N
+
+set_property -dict {PACKAGE_PIN L19      IOSTANDARD LVCMOS25} [get_ports adc_os[0]]           ; ## FMC_LPC_CLK0_M2C_N
+set_property -dict {PACKAGE_PIN L18      IOSTANDARD LVCMOS25} [get_ports adc_os[1]]           ; ## FMC_LPC_CLK0_M2C_P
+set_property -dict {PACKAGE_PIN N19      IOSTANDARD LVCMOS25} [get_ports adc_os[2]]           ; ## FMC_LPC_LA01_CC_P
+set_property -dict {PACKAGE_PIN R21      IOSTANDARD LVCMOS25} [get_ports adc_burst]           ; ## FMC_LPC_LA09_N
+set_property -dict {PACKAGE_PIN P18      IOSTANDARD LVCMOS25} [get_ports adc_crcen]           ; ## FMC_LPC_LA02_N
+
diff --git a/projects/ad7616_sdz/zed/system_bd.tcl b/projects/ad7616_sdz/zed/system_bd.tcl
new file mode 100644
index 000000000..cf4941e23
--- /dev/null
+++ b/projects/ad7616_sdz/zed/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
+source ../common/ad7616_bd.tcl
+
diff --git a/projects/ad7616_sdz/zed/system_project.tcl b/projects/ad7616_sdz/zed/system_project.tcl
new file mode 100644
index 000000000..1641f5ff2
--- /dev/null
+++ b/projects/ad7616_sdz/zed/system_project.tcl
@@ -0,0 +1,47 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+##--------------------------------------------------------------
+# IMPORTANT: Set AD7616 operation and interface mode
+#
+#    ad7616_if  - Defines the interface type (serial OR parallel)
+#
+# LEGEND: Serial    - 0
+#         Parallel  - 1
+#
+# NOTE : These switches are 'hardware' switches. User needs to
+# reimplement the design each and every time, after these variables
+# were changed.
+#
+##--------------------------------------------------------------
+
+set ad7616_if   0
+
+adi_project_create ad7616_sdz_zed
+
+if { $ad7616_if == 0 } {
+
+  adi_project_files ad7616_sdz_zed [list \
+    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "system_top_si.v" \
+    "serial_if_constr.xdc" \
+    "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
+
+} elseif { $ad7616_if == 1 } {
+
+  adi_project_files ad7616_sdz_zed [list \
+    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "system_top_pi.v" \
+    "parallel_if_constr.xdc" \
+    "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
+
+} else {
+
+  return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."]
+
+}
+
+adi_project_run ad7616_sdz_zed
+
diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v
new file mode 100644
index 000000000..62a1d6023
--- /dev/null
+++ b/projects/ad7616_sdz/zed/system_top_pi.v
@@ -0,0 +1,302 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  gpio_bd,
+
+  hdmi_out_clk,
+  hdmi_vsync,
+  hdmi_hsync,
+  hdmi_data_e,
+  hdmi_data,
+
+  i2s_mclk,
+  i2s_bclk,
+  i2s_lrclk,
+  i2s_sdata_out,
+  i2s_sdata_in,
+
+  spdif,
+
+  iic_scl,
+  iic_sda,
+  iic_mux_scl,
+  iic_mux_sda,
+
+  otg_vbusoc,
+
+  adc_db,
+  adc_rd_n,
+  adc_wr_n,
+
+  adc_cs_n,
+  adc_reset_n,
+  adc_convst,
+  adc_busy,
+  adc_seq_en,
+  adc_hw_rngsel,
+  adc_chsel,
+  adc_crcen,
+  adc_burst,
+  adc_os);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout   [31:0]  gpio_bd;
+
+  output          hdmi_out_clk;
+  output          hdmi_vsync;
+  output          hdmi_hsync;
+  output          hdmi_data_e;
+  output  [15:0]  hdmi_data;
+
+  output          spdif;
+
+  output          i2s_mclk;
+  output          i2s_bclk;
+  output          i2s_lrclk;
+  output          i2s_sdata_out;
+  input           i2s_sdata_in;
+
+
+  inout           iic_scl;
+  inout           iic_sda;
+  inout   [ 1:0]  iic_mux_scl;
+  inout   [ 1:0]  iic_mux_sda;
+
+  input           otg_vbusoc;
+
+  inout   [15:0]  adc_db;
+  output          adc_rd_n;
+  output          adc_wr_n;
+
+  output          adc_cs_n;
+  output          adc_reset_n;
+  output          adc_convst;
+  output          adc_busy;
+  output          adc_seq_en;
+  output  [ 1:0]  adc_hw_rngsel;
+  output  [ 2:0]  adc_chsel;
+  output          adc_crcen;
+  output          adc_burst;
+  output  [ 2:0]  adc_os;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire    [ 1:0]  iic_mux_scl_i_s;
+  wire    [ 1:0]  iic_mux_scl_o_s;
+  wire            iic_mux_scl_t_s;
+  wire    [ 1:0]  iic_mux_sda_i_s;
+  wire    [ 1:0]  iic_mux_sda_o_s;
+  wire            iic_mux_sda_t_s;
+
+  wire            adc_db_t;
+  wire    [15:0]  adc_db_o;
+  wire    [15:0]  adc_db_i;
+
+  genvar i;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
+    .dio_t (gpio_t[43:32]),
+    .dio_i (gpio_o[43:32]),
+    .dio_o (gpio_i[43:32]),
+    .dio_p ({adc_reset_n,        // 43
+             adc_hw_rngsel,      // 42:41
+             adc_os,             // 40:38
+             adc_seq_en,         // 37
+             adc_burst,          // 36
+             adc_chsel,          // 35:33
+             adc_crcen}));       // 32
+
+  generate
+    for (i = 0; i < 16; i = i + 1) begin: adc_db_io
+      ad_iobuf i_adc_db (
+        .dio_t(adc_db_t),
+        .dio_i(adc_db_o[i]),
+        .dio_o(adc_db_i[i]),
+        .dio_p(adc_db[i]));
+    end
+  endgenerate
+
+  ad_iobuf #(
+    .DATA_WIDTH(32)
+  ) i_iobuf (
+    .dio_t(gpio_t[31:0]),
+    .dio_i(gpio_o[31:0]),
+    .dio_o(gpio_i[31:0]),
+    .dio_p(gpio_bd));
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_iic_mux_scl (
+    .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
+    .dio_i(iic_mux_scl_o_s),
+    .dio_o(iic_mux_scl_i_s),
+    .dio_p(iic_mux_scl));
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_iic_mux_sda (
+    .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
+    .dio_i(iic_mux_sda_o_s),
+    .dio_o(iic_mux_sda_i_s),
+    .dio_p(iic_mux_sda));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .i2s_bclk (i2s_bclk),
+    .i2s_lrclk (i2s_lrclk),
+    .i2s_mclk (i2s_mclk),
+    .i2s_sdata_in (i2s_sdata_in),
+    .i2s_sdata_out (i2s_sdata_out),
+    .iic_fmc_scl_io (iic_scl),
+    .iic_fmc_sda_io (iic_sda),
+    .iic_mux_scl_i (iic_mux_scl_i_s),
+    .iic_mux_scl_o (iic_mux_scl_o_s),
+    .iic_mux_scl_t (iic_mux_scl_t_s),
+    .iic_mux_sda_i (iic_mux_sda_i_s),
+    .iic_mux_sda_o (iic_mux_sda_o_s),
+    .iic_mux_sda_t (iic_mux_sda_t_s),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .otg_vbusoc (otg_vbusoc),
+    .spdif (spdif),
+    .cnvst (adc_convst),
+    .cs_n (adc_cs_n),
+    .busy (adc_busy),
+    .db_o (adc_db_o),
+    .db_i (adc_db_i),
+    .db_t (adc_db_t),
+    .rd_n (adc_rd_n),
+    .wr_n (adc_wr_n)
+  );
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/ad7616_sdz/zed/system_top_si.v b/projects/ad7616_sdz/zed/system_top_si.v
new file mode 100644
index 000000000..4d6153b57
--- /dev/null
+++ b/projects/ad7616_sdz/zed/system_top_si.v
@@ -0,0 +1,287 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  gpio_bd,
+
+  hdmi_out_clk,
+  hdmi_vsync,
+  hdmi_hsync,
+  hdmi_data_e,
+  hdmi_data,
+
+  i2s_mclk,
+  i2s_bclk,
+  i2s_lrclk,
+  i2s_sdata_out,
+  i2s_sdata_in,
+
+  spdif,
+
+  iic_scl,
+  iic_sda,
+  iic_mux_scl,
+  iic_mux_sda,
+
+  otg_vbusoc,
+
+  spi_sclk,
+  spi_sdo,
+  spi_sdi_0,
+  spi_sdi_1,
+  spi_cs_n,
+
+  adc_reset_n,
+  adc_convst,
+  adc_busy,
+  adc_seq_en,
+  adc_hw_rngsel,
+  adc_chsel,
+  adc_crcen,
+  adc_burst,
+  adc_os);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout   [31:0]  gpio_bd;
+
+  output          hdmi_out_clk;
+  output          hdmi_vsync;
+  output          hdmi_hsync;
+  output          hdmi_data_e;
+  output  [15:0]  hdmi_data;
+
+  output          spdif;
+
+  output          i2s_mclk;
+  output          i2s_bclk;
+  output          i2s_lrclk;
+  output          i2s_sdata_out;
+  input           i2s_sdata_in;
+
+
+  inout           iic_scl;
+  inout           iic_sda;
+  inout   [ 1:0]  iic_mux_scl;
+  inout   [ 1:0]  iic_mux_sda;
+
+  input           otg_vbusoc;
+
+  output          spi_sclk;
+  output          spi_sdo;
+  input           spi_sdi_0;
+  input           spi_sdi_1;
+  output          spi_cs_n;
+
+  output          adc_reset_n;
+  output          adc_convst;
+  output          adc_busy;
+  output          adc_seq_en;
+  output  [ 1:0]  adc_hw_rngsel;
+  output  [ 2:0]  adc_chsel;
+  output          adc_crcen;
+  output          adc_burst;
+  output  [ 2:0]  adc_os;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire    [ 1:0]  iic_mux_scl_i_s;
+  wire    [ 1:0]  iic_mux_scl_o_s;
+  wire            iic_mux_scl_t_s;
+  wire    [ 1:0]  iic_mux_sda_i_s;
+  wire    [ 1:0]  iic_mux_sda_o_s;
+  wire            iic_mux_sda_t_s;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(12)) i_adc_iobuf (
+    .dio_t (gpio_t[43:32]),
+    .dio_i (gpio_o[43:32]),
+    .dio_o (gpio_i[43:32]),
+    .dio_p ({adc_reset_n,        // 43
+             adc_hw_rngsel,      // 42:41
+             adc_os,             // 40:38
+             adc_seq_en,         // 37
+             adc_burst,          // 36
+             adc_chsel,          // 35:33
+             adc_crcen}));       // 32
+
+  ad_iobuf #(
+    .DATA_WIDTH(32)
+  ) i_gpio_iobuf (
+    .dio_t(gpio_t[31:0]),
+    .dio_i(gpio_o[31:0]),
+    .dio_o(gpio_i[31:0]),
+    .dio_p(gpio_bd));
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_iic_mux_scl (
+    .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
+    .dio_i(iic_mux_scl_o_s),
+    .dio_o(iic_mux_scl_i_s),
+    .dio_p(iic_mux_scl));
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_iic_mux_sda (
+    .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
+    .dio_i(iic_mux_sda_o_s),
+    .dio_o(iic_mux_sda_i_s),
+    .dio_p(iic_mux_sda));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .i2s_bclk (i2s_bclk),
+    .i2s_lrclk (i2s_lrclk),
+    .i2s_mclk (i2s_mclk),
+    .i2s_sdata_in (i2s_sdata_in),
+    .i2s_sdata_out (i2s_sdata_out),
+    .iic_fmc_scl_io (iic_scl),
+    .iic_fmc_sda_io (iic_sda),
+    .iic_mux_scl_i (iic_mux_scl_i_s),
+    .iic_mux_scl_o (iic_mux_scl_o_s),
+    .iic_mux_scl_t (iic_mux_scl_t_s),
+    .iic_mux_sda_i (iic_mux_sda_i_s),
+    .iic_mux_sda_o (iic_mux_sda_o_s),
+    .iic_mux_sda_t (iic_mux_sda_t_s),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .otg_vbusoc (otg_vbusoc),
+    .spdif (spdif),
+    .cnvst (adc_convst),
+    .sclk (spi_sclk),
+    .sdo (spi_sdo),
+    .sdi_0 (spi_sdi_0),
+    .sdi_1 (spi_sdi_1),
+    .cs_n (spi_cs_n),
+    .busy (adc_busy)
+  );
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From b147e9c94adee79def8f2afacffba3e4856676ec Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 2 Feb 2016 12:33:01 -0500
Subject: [PATCH 071/972] pzsdr1- updates

---
 projects/common/pzsdr1/pzsdr1_system_bd.tcl   |   2 +-
 .../common/pzsdr1/pzsdr1_system_constr.xdc    | 118 +++++++++---------
 projects/scripts/adi_project.tcl              |   2 +-
 3 files changed, 61 insertions(+), 61 deletions(-)

diff --git a/projects/common/pzsdr1/pzsdr1_system_bd.tcl b/projects/common/pzsdr1/pzsdr1_system_bd.tcl
index 6c442708f..96c08cb92 100644
--- a/projects/common/pzsdr1/pzsdr1_system_bd.tcl
+++ b/projects/common/pzsdr1/pzsdr1_system_bd.tcl
@@ -159,5 +159,5 @@ ad_cpu_interconnect 0x41600000 axi_iic_main
 source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
 source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
 
-set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361
+set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {0}] $axi_ad9361
 
diff --git a/projects/common/pzsdr1/pzsdr1_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
index 78d73e959..e5b625de0 100644
--- a/projects/common/pzsdr1/pzsdr1_system_constr.xdc
+++ b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
@@ -2,64 +2,64 @@
 # constraints
 # ad9361
 
-set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35        
-set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35        
-set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35        
-set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35        
-set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35        
-set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35        
-set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35    
-set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35    
-set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35             
-set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35             
-set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35        
-set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35        
-set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35             
-set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35        
-set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS}     [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35       
-set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS}     [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35       
-set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS}     [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35    
-set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS}     [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35    
-set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS}     [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS}     [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35  
-set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS}     [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35  
-set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS}     [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35  
-set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS}     [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35  
-set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35            
-set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS}     [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35            
-set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS}     [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35       
-set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS}     [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
-set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS}     [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
-set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS}     [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
-set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS18} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
-set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS18} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
+set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35        
+set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35        
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35        
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35        
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35        
+set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35        
+set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35    
+set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35    
+set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35             
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35             
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35        
+set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35        
+set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35             
+set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35        
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35       
+set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35       
+set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35    
+set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35    
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35  
+set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35  
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35  
+set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35  
+set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35            
+set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35            
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35       
+set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
+set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
+set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
 
-set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35            
-set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35       
-set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35       
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35       
-set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35  
-set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35  
-set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35       
-set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35       
-set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34            
-set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34            
-set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34            
-set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34            
-set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35      
-set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS18} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35      
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports gpio_resetb]                       ; ## IO_0_35                  
-set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS18} [get_ports gpio_clksel]                       ; ## IO_0_34                  
+set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35            
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35       
+set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35       
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35       
+set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35  
+set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35  
+set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35       
+set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35       
+set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34            
+set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34            
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34            
+set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34            
+set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35      
+set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35      
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                       ; ## IO_0_35                  
+set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS25} [get_ports gpio_clksel]                       ; ## IO_0_34                  
 
-set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35        
-set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS18} [get_ports spi_clk]                           ; ## IO_L23N_T3_35        
-set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS18} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35  
-set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS18} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35  
+set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35        
+set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS25} [get_ports spi_clk]                           ; ## IO_L23N_T3_35        
+set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35  
+set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS25} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35  
 
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports clk_out]                           ; ## IO_25_35
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS25} [get_ports clk_out]                           ; ## IO_25_35
 
 # iic
 
@@ -68,10 +68,10 @@ set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get
 
 # gpio
 
-set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
-set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
+set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
+set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
 
 # clocks
 
diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index 13d3c9715..d0c8a5242 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -81,7 +81,7 @@ proc adi_project_create {project_name {mode 0}} {
     set sys_zynq 1
   }
   if [regexp "_pzsdr1$" $project_name] {
-    set p_device "xc7z020ifbg676-1L"
+    set p_device "xc7z020clg400-1"
     set p_board "not-applicable"
     set sys_zynq 1
   }

From 41b6ebeeafa7c9f6a956a0bf3c146955860fc069 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 2 Feb 2016 12:33:55 -0500
Subject: [PATCH 072/972] pzsdr1- updates

---
 projects/pzsdr1/ccbrk/Makefile           |  12 +-
 projects/pzsdr1/ccbrk/system_bd.tcl      |   2 +-
 projects/pzsdr1/ccbrk/system_constr.xdc  | 287 +++++------------------
 projects/pzsdr1/ccbrk/system_project.tcl |  10 +-
 projects/pzsdr1/ccbrk/system_top.v       |  76 ++----
 5 files changed, 91 insertions(+), 296 deletions(-)

diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
index 49d742665..ce0099658 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -15,9 +15,9 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
 M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../common/pzsdr1/pzsdr1_system_ps7.tcl
+M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
+M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -45,7 +45,7 @@ M_FLIST += .Xil
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_pzsdr.sdk/system_top.hdf
+all: lib ccbrk_pzsdr1.sdk/system_top.hdf
 
 
 clean: 
@@ -64,9 +64,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+ccbrk_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr1_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr1/ccbrk/system_bd.tcl b/projects/pzsdr1/ccbrk/system_bd.tcl
index 4907eef1b..aa8108693 100644
--- a/projects/pzsdr1/ccbrk/system_bd.tcl
+++ b/projects/pzsdr1/ccbrk/system_bd.tcl
@@ -1,4 +1,4 @@
 
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_bd.tcl
 source ../common/ccbrk_bd.tcl
 
diff --git a/projects/pzsdr1/ccbrk/system_constr.xdc b/projects/pzsdr1/ccbrk/system_constr.xdc
index 05083fdc9..e54ad79c8 100644
--- a/projects/pzsdr1/ccbrk/system_constr.xdc
+++ b/projects/pzsdr1/ccbrk/system_constr.xdc
@@ -1,236 +1,76 @@
 
 ## constraints
 ## loopback
-## p4
-
-set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33              
-set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33              
-set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33              
-set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33              
-set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33              
-set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33          
-set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33              
-set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33          
-set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33              
-set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33              
-set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33         
-set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33              
-set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33              
-set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33              
-set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33              
-set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33              
-set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33             
-set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33          
-set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33             
-set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33          
-set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33        
-set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33        
-
-## p5
-
-set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33             
-set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33             
-set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33             
-set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33             
-set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33             
-set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33             
-set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33        
-set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33             
-set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33             
-set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33         
-set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33             
-set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33         
-set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33             
-set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33             
-set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33             
-set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33             
-set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34              
-set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34             
-set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33        
-set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33             
-set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33        
-set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33             
-set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33        
-set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33         
-set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33        
-set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33         
-
 ## p6
 
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34              
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34              
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34              
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34              
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34              
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34   
-set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34              
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34          
-set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34              
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34              
-set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34         
-set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34              
-set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34              
-set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34              
-set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34        
-set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34        
-set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34        
-set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34        
+set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[0]]        ; ## JX4.20  IO_L2P_T0_34                  
+set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[0]]         ; ## JX4.19  IO_L1P_T0_34                  
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[1]]        ; ## JX4.22  IO_L2N_T0_34                  
+set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[1]]         ; ## JX4.21  IO_L1N_T0_34                  
+set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[2]]        ; ## JX4.26  IO_L4P_T0_34                  
+set_property  -dict {PACKAGE_PIN  U13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[2]]         ; ## JX4.25  IO_L3P_T0_DQS_PUDC_B_34       
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_out[3]]        ; ## JX4.28  IO_L4N_T0_34                  
+set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[3]]         ; ## JX4.27  IO_L3N_T0_DQS_34              
+set_property  -dict {PACKAGE_PIN  P14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[4]]        ; ## JX4.32  IO_L6P_T0_34                  
+set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD  LVCMOS25} [get_ports  gp_in[4]]         ; ## JX4.31  IO_L5P_T0_34                  
+set_property  -dict {PACKAGE_PIN  R14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[5]]        ; ## JX4.34  IO_L6N_T0_VREF_34             
+set_property  -dict {PACKAGE_PIN  T15   IOSTANDARD  LVCMOS25} [get_ports  gp_in[5]]         ; ## JX4.33  IO_L5N_T0_34                  
+set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[6]]        ; ## JX4.36  IO_L8P_T1_34                  
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD  LVCMOS25} [get_ports  gp_in[6]]         ; ## JX4.35  IO_L7P_T1_34                  
+set_property  -dict {PACKAGE_PIN  U18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[7]]        ; ## JX4.46  IO_L12P_T1_MRCC_34            
+set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD  LVCMOS25} [get_ports  gp_in[7]]         ; ## JX4.45  IO_L11P_T1_SRCC_34            
+set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD  LVCMOS25} [get_ports  gp_out[8]]        ; ## JX4.48  IO_L12N_T1_MRCC_34            
+set_property  -dict {PACKAGE_PIN  U15   IOSTANDARD  LVCMOS25} [get_ports  gp_in[8]]         ; ## JX4.47  IO_L11N_T1_SRCC_34            
 
 ## p7
 
-set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34        
-set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34        
-set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34        
-set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34        
-set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34             
-set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34         
-set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34             
-set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34         
-set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34             
-set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34             
-set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34             
-set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34        
-set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34             
-set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34             
-set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33               
-set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34             
-set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34             
-set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33              
-
-## p13
-
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12             
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12         
-set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12             
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12         
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12             
-set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12          
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12             
-set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12          
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12              
-set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12              
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12              
-set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12              
-set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12              
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12              
-set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12         
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12              
-set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12              
-set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12          
-set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12              
-set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12          
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12              
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12              
-set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12              
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12              
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12             
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12             
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12             
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12             
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12             
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12             
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12             
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12        
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12             
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12         
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12             
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12         
+set_property  -dict {PACKAGE_PIN  N20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[9]]        ; ## JX4.52  IO_L14P_T2_SRCC_34            
+set_property  -dict {PACKAGE_PIN  N18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[9]]         ; ## JX4.51  IO_L13P_T2_MRCC_34            
+set_property  -dict {PACKAGE_PIN  P20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[10]]       ; ## JX4.54  IO_L14N_T2_SRCC_34            
+set_property  -dict {PACKAGE_PIN  P19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[10]]        ; ## JX4.53  IO_L13N_T2_MRCC_34            
+set_property  -dict {PACKAGE_PIN  V20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[11]]       ; ## JX4.58  IO_L16P_T2_34                 
+set_property  -dict {PACKAGE_PIN  T20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[11]]        ; ## JX4.57  IO_L15P_T2_DQS_34             
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[12]]       ; ## JX4.60  IO_L16N_T2_34                 
+set_property  -dict {PACKAGE_PIN  U20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[12]]        ; ## JX4.59  IO_L15N_T2_DQS_34             
+set_property  -dict {PACKAGE_PIN  T17   IOSTANDARD  LVCMOS25} [get_ports  gp_out[13]]       ; ## JX4.74  IO_L20P_T3_34                 
+set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD  LVCMOS25} [get_ports  gp_in[13]]        ; ## JX4.73  IO_L19P_T3_34                 
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[14]]       ; ## JX4.76  IO_L20N_T3_34                 
+set_property  -dict {PACKAGE_PIN  R17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[14]]        ; ## JX4.75  IO_L19N_T3_VREF_34            
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[15]]       ; ## JX4.78  IO_L22P_T3_34                 
+set_property  -dict {PACKAGE_PIN  V17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[15]]        ; ## JX4.77  IO_L21P_T3_DQS_34             
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_out[16]]       ; ## JX4.80  IO_L22N_T3_34                 
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[16]]        ; ## JX4.79  IO_L21N_T3_DQS_34             
 
 ## p2
 
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13                  
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13              
-set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13              
-set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13              
-set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13              
-set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13              
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13              
-set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13          
-set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13              
-set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13          
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13              
-set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13              
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13              
-set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13              
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13             
-set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13          
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13             
-set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13          
-set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13             
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13         
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13             
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13         
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13             
-set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13             
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13             
-set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13             
-set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13             
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13             
-set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13             
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13        
-set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13             
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13         
-set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13             
-set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13         
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13             
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13             
-set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13             
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13             
+set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[17]]       ; ## JX2.36  IO_L12P_T1_MRCC_13            
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[17]]        ; ## JX2.35  IO_L11P_T1_SRCC_13            
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  gp_out[18]]       ; ## JX2.38  IO_L12N_T1_MRCC_13            
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[18]]        ; ## JX2.37  IO_L11N_T1_SRCC_13            
+set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[19]]       ; ## JX2.42  IO_L14P_T2_SRCC_13            
+set_property  -dict {PACKAGE_PIN  Y7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[19]]        ; ## JX2.41  IO_L13P_T2_MRCC_13            
+set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD  LVCMOS25} [get_ports  gp_out[20]]       ; ## JX2.44  IO_L14N_T2_SRCC_13            
+set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD  LVCMOS25} [get_ports  gp_in[20]]        ; ## JX2.43  IO_L13N_T2_MRCC_13            
+set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  gp_out[21]]       ; ## JX2.48  IO_L16P_T2_13                 
+set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[21]]        ; ## JX2.47  IO_L15P_T2_DQS_13             
+set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[22]]       ; ## JX2.50  IO_L16N_T2_13                 
+set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[22]]        ; ## JX2.49  IO_L15N_T2_DQS_13             
+set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD  LVCMOS25} [get_ports  gp_out[23]]       ; ## JX2.54  IO_L18P_T2_13                 
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  gp_in[23]]        ; ## JX2.53  IO_L17P_T2_13                 
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_out[24]]       ; ## JX2.56  IO_L18N_T2_13                 
+set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[24]]        ; ## JX2.55  IO_L17N_T2_13                 
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[25]]       ; ## JX2.62  IO_L20P_T3_13                 
+set_property  -dict {PACKAGE_PIN  T5    IOSTANDARD  LVCMOS25} [get_ports  gp_in[25]]        ; ## JX2.61  IO_L19P_T3_13                 
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_out[26]]       ; ## JX2.64  IO_L20N_T3_13                 
+set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD  LVCMOS25} [get_ports  gp_in[26]]        ; ## JX2.63  IO_L19N_T3_VREF_13            
 
 ## vcc
 
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13         
-
-## on board
-
-set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111           
-set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111           
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111              
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111              
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111              
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111              
-set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111              
-set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111              
-set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111              
-set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111              
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111              
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111              
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111              
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111              
-set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111              
-set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111              
-set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111              
-set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111              
-
-## clocks
-
-create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[0]]    ; ## JX2.18  IO_L6N_T0_VREF_13 
+set_property  -dict {PACKAGE_PIN  V16   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[1]]    ; ## JX4.68  IO_L18P_T2_34                 
+set_property  -dict {PACKAGE_PIN  W16   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[2]]    ; ## JX4.70  IO_L18N_T2_34                 
+set_property  -dict {PACKAGE_PIN  V11   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[3]]    ; ## JX2.67  IO_L21P_T3_DQS_13             
+set_property  -dict {PACKAGE_PIN  V10   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[4]]    ; ## JX2.69  IO_L21N_T3_DQS_13             
 
 ## MIO loopbacks (fixed-io)
 ## the following are connected to AD9361 GPIO
@@ -246,13 +86,12 @@ create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_
 
 ## the following are mio-to-pl loopback
 
-##  JX4.97    E26   PS_MIO00_500_JX4    <==>  JX1.76    K3    IO_L11N_T1_SRCC_33        
 ##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
 ##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
 ##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
 
-set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33        
-set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34             
-set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34              
-set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34             
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[0]]     ; ## JX4.67  IO_L17P_T2_34                 
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[1]]     ; ## JX4.37  IO_L7N_T1_34                  
+set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[2]]     ; ## JX4.42  IO_L10P_T1_34                 
+
 
diff --git a/projects/pzsdr1/ccbrk/system_project.tcl b/projects/pzsdr1/ccbrk/system_project.tcl
index 3d182ce37..2bab986f0 100644
--- a/projects/pzsdr1/ccbrk/system_project.tcl
+++ b/projects/pzsdr1/ccbrk/system_project.tcl
@@ -5,16 +5,16 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
 
-adi_project_create ccbrk_pzsdr
-adi_project_files ccbrk_pzsdr [list \
+adi_project_create ccbrk_pzsdr1
+adi_project_files ccbrk_pzsdr1 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
-adi_project_run ccbrk_pzsdr
+adi_project_run ccbrk_pzsdr1
 
 
diff --git a/projects/pzsdr1/ccbrk/system_top.v b/projects/pzsdr1/ccbrk/system_top.v
index 585b2022d..643b39163 100644
--- a/projects/pzsdr1/ccbrk/system_top.v
+++ b/projects/pzsdr1/ccbrk/system_top.v
@@ -99,14 +99,8 @@ module system_top (
   gp_out,
   gp_in,
   gp_in_mio,
-  gp_in_1,
+  gp_in_open);
 
-  gt_ref_clk_p,
-  gt_ref_clk_n,
-  gt_tx_p,
-  gt_tx_n,
-  gt_rx_p,
-  gt_rx_n);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -134,7 +128,7 @@ module system_top (
   inout           iic_scl;
   inout           iic_sda;
 
-  inout   [11:0]  gpio_bd;
+  inout   [ 3:0]  gpio_bd;
 
   input           rx_clk_in_p;
   input           rx_clk_in_n;
@@ -165,47 +159,28 @@ module system_top (
   output          spi_mosi;
   input           spi_miso;
 
-  output  [87:0]  gp_out;
-  input   [87:0]  gp_in;
-  input   [ 3:0]  gp_in_mio;
-  input           gp_in_1;
-
-  input           gt_ref_clk_p;
-  input           gt_ref_clk_n;
-  output  [ 3:0]  gt_tx_p;
-  output  [ 3:0]  gt_tx_n;
-  input   [ 3:0]  gt_rx_p;
-  input   [ 3:0]  gt_rx_n;
+  output  [26:0]  gp_out;
+  input   [26:0]  gp_in;
+  input   [ 2:0]  gp_in_mio;
+  input   [ 4:0]  gp_in_open;
 
   // internal signals
 
-  wire            gt_ref_clk;
-  wire    [95:0]  gp_out_s;
-  wire    [95:0]  gp_in_s;
+  wire    [63:0]  gp_out_s;
+  wire    [63:0]  gp_in_s;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
   // assignments
 
-  assign gp_out[87:43] = gp_out_s[87:43];
-  assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
-  assign gp_out[41: 0] = gp_out_s[41: 0];
-
-  assign gp_in_s[95:93] = 3'd0;
-  assign gp_in_s[92:92] = gp_in_1;
-  assign gp_in_s[91:88] = gp_in_mio;
-  assign gp_in_s[87: 0] = gp_in;
+  assign gp_out[26:0] = gp_out_s[26:0];
+  assign gp_in_s[34:30] = gp_in_open;
+  assign gp_in_s[29:27] = gp_in_mio;
+  assign gp_in_s[26: 0] = gp_in;
 
   // instantiations
 
-  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
-    .CEB (1'd0),
-    .I (gt_ref_clk_p),
-    .IB (gt_ref_clk_n),
-    .O (gt_ref_clk),
-    .ODIV2 ());
-
   ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
     .dio_t ({gpio_t[51], gpio_t[46:32]}),
     .dio_i ({gpio_o[51], gpio_o[46:32]}),
@@ -217,10 +192,10 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
-    .dio_t (gpio_t[11:0]),
-    .dio_i (gpio_o[11:0]),
-    .dio_o (gpio_i[11:0]),
+  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_bd (
+    .dio_t (gpio_t[3:0]),
+    .dio_i (gpio_o[3:0]),
+    .dio_o (gpio_i[3:0]),
     .dio_p (gpio_bd));
 
   system_wrapper i_system_wrapper (
@@ -248,30 +223,11 @@ module system_top (
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
     .gp_in_0 (gp_in_s[31:0]),
     .gp_in_1 (gp_in_s[63:32]),
-    .gp_in_2 (gp_in_s[95:64]),
     .gp_out_0 (gp_out_s[31:0]),
     .gp_out_1 (gp_out_s[63:32]),
-    .gp_out_2 (gp_out_s[95:64]),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .gt_ref_clk (gt_ref_clk),
-    .gt_rx_0_n (gt_rx_n[0]),
-    .gt_rx_0_p (gt_rx_p[0]),
-    .gt_rx_1_n (gt_rx_n[1]),
-    .gt_rx_1_p (gt_rx_p[1]),
-    .gt_rx_2_n (gt_rx_n[2]),
-    .gt_rx_2_p (gt_rx_p[2]),
-    .gt_rx_3_n (gt_rx_n[3]),
-    .gt_rx_3_p (gt_rx_p[3]),
-    .gt_tx_0_n (gt_tx_n[0]),
-    .gt_tx_0_p (gt_tx_p[0]),
-    .gt_tx_1_n (gt_tx_n[1]),
-    .gt_tx_1_p (gt_tx_p[1]),
-    .gt_tx_2_n (gt_tx_n[2]),
-    .gt_tx_2_p (gt_tx_p[2]),
-    .gt_tx_3_n (gt_tx_n[3]),
-    .gt_tx_3_p (gt_tx_p[3]),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),

From bb62f6d225ae7d2c60819919af5b8d9c00923725 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 2 Feb 2016 12:34:09 -0500
Subject: [PATCH 073/972] pzsdr1- updates

---
 projects/pzsdr1/common/ccbrk_bd.tcl | 168 +---------------------------
 1 file changed, 3 insertions(+), 165 deletions(-)

diff --git a/projects/pzsdr1/common/ccbrk_bd.tcl b/projects/pzsdr1/common/ccbrk_bd.tcl
index a91b0dafe..204545923 100644
--- a/projects/pzsdr1/common/ccbrk_bd.tcl
+++ b/projects/pzsdr1/common/ccbrk_bd.tcl
@@ -4,185 +4,23 @@
 ad_connect  sys_ps7/ENET1_GMII_RX_CLK GND
 ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
 
-# un-used io (gt)
-
-set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_pzslb_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_2 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_3 {3}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_pzslb_gt
-
-set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0]
-set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1]
-set util_pzslb_gtlb_2 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_2]
-set util_pzslb_gtlb_3 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_3]
-
-ad_cpu_interconnect 0x44A60000 axi_pzslb_gt
-ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi
-
-create_bd_port -dir I gt_ref_clk
-create_bd_port -dir I gt_rx_0_p
-create_bd_port -dir I gt_rx_0_n
-create_bd_port -dir O gt_tx_0_p
-create_bd_port -dir O gt_tx_0_n
-create_bd_port -dir I gt_rx_1_p
-create_bd_port -dir I gt_rx_1_n
-create_bd_port -dir O gt_tx_1_p
-create_bd_port -dir O gt_tx_1_n
-create_bd_port -dir I gt_rx_2_p
-create_bd_port -dir I gt_rx_2_n
-create_bd_port -dir O gt_tx_2_p
-create_bd_port -dir O gt_tx_2_n
-create_bd_port -dir I gt_rx_3_p
-create_bd_port -dir I gt_rx_3_n
-create_bd_port -dir O gt_tx_3_p
-create_bd_port -dir O gt_tx_3_n
-
-ad_connect  sys_cpu_clk util_pzslb_gtlb_0/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_0/up_rstn
-ad_connect  util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_0/rx_p gt_rx_0_p
-ad_connect  util_pzslb_gtlb_0/rx_n gt_rx_0_n
-ad_connect  util_pzslb_gtlb_0/tx_p gt_tx_0_p
-ad_connect  util_pzslb_gtlb_0/tx_n gt_tx_0_n
-ad_connect  sys_cpu_clk util_pzslb_gtlb_1/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_1/up_rstn
-ad_connect  util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_1/rx_p gt_rx_1_p
-ad_connect  util_pzslb_gtlb_1/rx_n gt_rx_1_n
-ad_connect  util_pzslb_gtlb_1/tx_p gt_tx_1_p
-ad_connect  util_pzslb_gtlb_1/tx_n gt_tx_1_n
-ad_connect  sys_cpu_clk util_pzslb_gtlb_2/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_2/up_rstn
-ad_connect  util_pzslb_gtlb_2/qpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_2/cpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_2/rx_p gt_rx_2_p
-ad_connect  util_pzslb_gtlb_2/rx_n gt_rx_2_n
-ad_connect  util_pzslb_gtlb_2/tx_p gt_tx_2_p
-ad_connect  util_pzslb_gtlb_2/tx_n gt_tx_2_n
-ad_connect  sys_cpu_clk util_pzslb_gtlb_3/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_3/up_rstn
-ad_connect  util_pzslb_gtlb_3/qpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_3/cpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_3/rx_p gt_rx_3_p
-ad_connect  util_pzslb_gtlb_3/rx_n gt_rx_3_n
-ad_connect  util_pzslb_gtlb_3/tx_p gt_tx_3_p
-ad_connect  util_pzslb_gtlb_3/tx_n gt_tx_3_n
-ad_connect  axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0
-ad_connect  axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0 
-ad_connect  axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0 
-ad_connect  axi_pzslb_gt/gt_pll_2 util_pzslb_gtlb_2/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_2 util_pzslb_gtlb_2/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_2 util_pzslb_gtlb_2/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_2 util_pzslb_gtlb_2/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_2 util_pzslb_gtlb_2/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_2 util_pzslb_gtlb_2/rx_gt_comma_align_enb_0 
-ad_connect  axi_pzslb_gt/gt_pll_3 util_pzslb_gtlb_3/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_3 util_pzslb_gtlb_3/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_3 util_pzslb_gtlb_3/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_3 util_pzslb_gtlb_3/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_3 util_pzslb_gtlb_3/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_3 util_pzslb_gtlb_3/rx_gt_comma_align_enb_0 
-
-# un-used io (regular)
+# un-used io
 
 set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
-set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_0 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_1 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_2 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_5 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg
-set_property -dict [list CONFIG.NUM_OF_IO {7}] $axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg
 
 ad_cpu_interconnect 0x41200000 axi_gpreg
 
-ad_connect  util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_0
-ad_connect  util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_1
-ad_connect  util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_2
-ad_connect  util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_3
-ad_connect  util_pzslb_gtlb_2/rx_clk axi_gpreg/d_clk_4
-ad_connect  util_pzslb_gtlb_2/tx_clk axi_gpreg/d_clk_5
-ad_connect  util_pzslb_gtlb_3/rx_clk axi_gpreg/d_clk_6
-ad_connect  util_pzslb_gtlb_3/tx_clk axi_gpreg/d_clk_7
-
 create_bd_port -dir I -from 31 -to 0 gp_in_0
 create_bd_port -dir I -from 31 -to 0 gp_in_1
-create_bd_port -dir I -from 31 -to 0 gp_in_2
 create_bd_port -dir O -from 31 -to 0 gp_out_0
 create_bd_port -dir O -from 31 -to 0 gp_out_1
-create_bd_port -dir O -from 31 -to 0 gp_out_2
 
 ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
 ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
-ad_connect  gp_in_2 axi_gpreg/up_gp_in_2
 ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
 ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
-ad_connect  gp_out_2 axi_gpreg/up_gp_out_2
-ad_connect  axi_gpreg/up_gp_in_3 util_pzslb_gtlb_0/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_3 util_pzslb_gtlb_0/up_gp_in
-ad_connect  axi_gpreg/up_gp_in_4 util_pzslb_gtlb_1/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_4 util_pzslb_gtlb_1/up_gp_in
-ad_connect  axi_gpreg/up_gp_in_5 util_pzslb_gtlb_2/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_5 util_pzslb_gtlb_2/up_gp_in
-ad_connect  axi_gpreg/up_gp_in_6 util_pzslb_gtlb_3/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_6 util_pzslb_gtlb_3/up_gp_in
 
 ## temporary (remove ila indirectly)
 

From a74e2061e90d22ce959406d42bd9763d77ac0123 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 3 Feb 2016 14:12:00 +0200
Subject: [PATCH 074/972] ad7616_sdz: BUSY is input for the FPGA

---
 projects/ad7616_sdz/zc706/system_top_pi.v | 2 +-
 projects/ad7616_sdz/zc706/system_top_si.v | 2 +-
 projects/ad7616_sdz/zed/system_top_pi.v   | 2 +-
 projects/ad7616_sdz/zed/system_top_si.v   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v
index 2f80c97d8..b3c8ae8f8 100644
--- a/projects/ad7616_sdz/zc706/system_top_pi.v
+++ b/projects/ad7616_sdz/zc706/system_top_pi.v
@@ -135,7 +135,7 @@ module system_top (
   output          adc_cs_n;
   output          adc_reset_n;
   output          adc_convst;
-  output          adc_busy;
+  input           adc_busy;
   output          adc_seq_en;
   output  [ 1:0]  adc_hw_rngsel;
   output  [ 2:0]  adc_chsel;
diff --git a/projects/ad7616_sdz/zc706/system_top_si.v b/projects/ad7616_sdz/zc706/system_top_si.v
index c75069a04..239803d13 100644
--- a/projects/ad7616_sdz/zc706/system_top_si.v
+++ b/projects/ad7616_sdz/zc706/system_top_si.v
@@ -137,7 +137,7 @@ module system_top (
 
   output          adc_reset_n;
   output          adc_convst;
-  output          adc_busy;
+  input           adc_busy;
   output          adc_seq_en;
   output  [ 1:0]  adc_hw_rngsel;
   output  [ 2:0]  adc_chsel;
diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v
index 62a1d6023..9337f60e7 100644
--- a/projects/ad7616_sdz/zed/system_top_pi.v
+++ b/projects/ad7616_sdz/zed/system_top_pi.v
@@ -156,7 +156,7 @@ module system_top (
   output          adc_cs_n;
   output          adc_reset_n;
   output          adc_convst;
-  output          adc_busy;
+  input           adc_busy;
   output          adc_seq_en;
   output  [ 1:0]  adc_hw_rngsel;
   output  [ 2:0]  adc_chsel;
diff --git a/projects/ad7616_sdz/zed/system_top_si.v b/projects/ad7616_sdz/zed/system_top_si.v
index 4d6153b57..fb168685e 100644
--- a/projects/ad7616_sdz/zed/system_top_si.v
+++ b/projects/ad7616_sdz/zed/system_top_si.v
@@ -158,7 +158,7 @@ module system_top (
 
   output          adc_reset_n;
   output          adc_convst;
-  output          adc_busy;
+  input           adc_busy;
   output          adc_seq_en;
   output  [ 1:0]  adc_hw_rngsel;
   output  [ 2:0]  adc_chsel;

From 1c3795ad0278894ed5e253557eb4621ff5005069 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 4 Feb 2016 15:59:47 +0200
Subject: [PATCH 075/972] Update .gitattributes

Add xise file extension to .gitattributes
---
 .gitattributes | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitattributes b/.gitattributes
index 3d7ee6dd4..96ff5a1f3 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -11,4 +11,5 @@
 *.xdc text
 *.xml text
 *.qsys text
+*.xise text
 Makefile text

From e381d5170cc8154b1ff5a15c20dcc2555e90fd13 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 10 Feb 2016 12:43:16 +0200
Subject: [PATCH 076/972] util_tdd_sync: Update the synchronization interface

Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
---
 library/axi_ad9361/axi_ad9361.v               | 24 +++--------
 library/axi_ad9361/axi_ad9361_tdd.v           | 13 +++---
 library/common/ad_tdd_control.v               |  6 ---
 library/common/up_tdd_cntrl.v                 | 20 +++------
 library/util_tdd_sync/util_tdd_sync.v         | 43 +++++++++----------
 .../util_tdd_sync/util_tdd_sync_constr.xdc    |  3 +-
 projects/fmcomms2/common/fmcomms2_bd.tcl      |  6 +--
 7 files changed, 42 insertions(+), 73 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 5e30d4840..544bf9007 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -70,8 +70,7 @@ module axi_ad9361 (
   // tdd sync (1s pulse)
 
   tdd_sync,
-  tdd_sync_en,
-  tdd_terminal_type,
+  tdd_sync_cntr,
 
   // delay clock
 
@@ -194,8 +193,7 @@ module axi_ad9361 (
   // tdd sync
 
   input           tdd_sync;
-  output          tdd_sync_en;
-  output          tdd_terminal_type;
+  output          tdd_sync_cntr;
 
   // delay clock
 
@@ -415,17 +413,10 @@ module axi_ad9361 (
 
   // additional flop to keep control and data synced
   always @(posedge clk) begin
-    if(rst == 1) begin
-      adc_data_i0 <= 16'b0;
-      adc_data_q0 <= 16'b0;
-      adc_data_i1 <= 16'b0;
-      adc_data_q1 <= 16'b0;
-    end else begin
-      adc_data_i0 <= adc_data_i0_s;
-      adc_data_q0 <= adc_data_q0_s;
-      adc_data_i1 <= adc_data_i1_s;
-      adc_data_q1 <= adc_data_q1_s;
-    end
+    adc_data_i0 <= adc_data_i0_s;
+    adc_data_q0 <= adc_data_q0_s;
+    adc_data_i1 <= adc_data_i1_s;
+    adc_data_q1 <= adc_data_q1_s;
   end
 
   axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
@@ -451,8 +442,7 @@ module axi_ad9361 (
     .tdd_enabled (tdd_mode_s),
     .tdd_status (tdd_status_s),
     .tdd_sync (tdd_sync),
-    .tdd_sync_en (tdd_sync_en),
-    .tdd_terminal_type (tdd_terminal_type),
+    .tdd_sync_cntr (tdd_sync_cntr),
     .tx_valid_i0 (dac_valid_i0_s),
     .tx_valid_q0 (dac_valid_q0_s),
     .tx_valid_i1 (dac_valid_i1_s),
diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index 63771d9b3..27c008d6c 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -61,8 +61,7 @@ module axi_ad9361_tdd (
   // sync signal
 
   tdd_sync,
-  tdd_sync_en,
-  tdd_terminal_type,
+  tdd_sync_cntr,
 
   // tx/rx data flow control
 
@@ -116,8 +115,7 @@ module axi_ad9361_tdd (
   input   [ 7:0]    tdd_status;
 
   input             tdd_sync;
-  output            tdd_sync_en;
-  output            tdd_terminal_type;
+  output            tdd_sync_cntr;
 
   // tx data flow control
 
@@ -211,6 +209,9 @@ module axi_ad9361_tdd (
   assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_sync, tdd_tx_dp_en_s,
                     tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
 
+  assign  tdd_enabled = tdd_enable_s;
+  assign  tdd_sync_cntr = ~(tdd_enable_s & tdd_terminal_type_s);
+
   // tx/rx data flow control
 
   always @(posedge clk) begin
@@ -241,8 +242,6 @@ module axi_ad9361_tdd (
     end
   end
 
-  assign  tdd_enabled = tdd_enable_s;
-  assign  tdd_terminal_type = ~tdd_terminal_type_s;
 
   // instantiations
 
@@ -259,7 +258,6 @@ module axi_ad9361_tdd (
     .tdd_counter_init(tdd_counter_init_s),
     .tdd_frame_length(tdd_frame_length_s),
     .tdd_terminal_type(tdd_terminal_type_s),
-    .tdd_sync_enable(tdd_sync_enable_s),
     .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
     .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
     .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
@@ -309,7 +307,6 @@ module axi_ad9361_tdd (
     .tdd_rx_only(tdd_rx_only_s),
     .tdd_tx_only(tdd_tx_only_s),
     .tdd_sync (tdd_sync),
-    .tdd_sync_en (tdd_sync_en),
     .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
     .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
     .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v
index b961e0cf2..af9b6b61e 100644
--- a/library/common/ad_tdd_control.v
+++ b/library/common/ad_tdd_control.v
@@ -76,7 +76,6 @@ module ad_tdd_control(
   tdd_tx_dp_on_2,
   tdd_tx_dp_off_2,
   tdd_sync,
-  tdd_sync_en,
 
   // TDD control signals
 
@@ -130,7 +129,6 @@ module ad_tdd_control(
   input  [23:0]   tdd_tx_dp_off_2;
 
   input           tdd_sync;
-  output          tdd_sync_en;
 
   output          tdd_tx_dp_en;       // initiate vco tx2rx switch
   output          tdd_rx_vco_en;      // initiate vco rx2tx switch
@@ -183,8 +181,6 @@ module ad_tdd_control(
   reg             tdd_sync_d2 = 1'b0;
   reg             tdd_sync_d3 = 1'b0;
 
-  reg             tdd_sync_en = 1'b0;
-
   // internal signals
 
   wire   [23:0]   tdd_vco_rx_on_1_s;
@@ -217,12 +213,10 @@ module ad_tdd_control(
   // synchronization of tdd_sync
   always @(posedge clk) begin
     if (rst == 1'b1) begin
-      tdd_sync_en <= 1'b0;
       tdd_sync_d1 <= 1'b0;
       tdd_sync_d2 <= 1'b0;
       tdd_sync_d3 <= 1'b0;
     end else begin
-      tdd_sync_en <= tdd_enable;
       tdd_sync_d1 <= tdd_sync;
       tdd_sync_d2 <= tdd_sync_d1;
       tdd_sync_d3 <= tdd_sync_d2;
diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v
index 98f2cf9a5..c77da4ff4 100644
--- a/library/common/up_tdd_cntrl.v
+++ b/library/common/up_tdd_cntrl.v
@@ -55,7 +55,6 @@ module up_tdd_cntrl (
   tdd_counter_init,
   tdd_frame_length,
   tdd_terminal_type,
-  tdd_sync_enable,
   tdd_vco_rx_on_1,
   tdd_vco_rx_off_1,
   tdd_vco_tx_on_1,
@@ -110,7 +109,6 @@ module up_tdd_cntrl (
   output  [23:0]  tdd_counter_init;
   output  [23:0]  tdd_frame_length;
   output          tdd_terminal_type;
-  output          tdd_sync_enable;
   output  [23:0]  tdd_vco_rx_on_1;
   output  [23:0]  tdd_vco_rx_off_1;
   output  [23:0]  tdd_vco_tx_on_1;
@@ -161,7 +159,6 @@ module up_tdd_cntrl (
   reg             up_tdd_gated_tx_dmapath = 1'h0;
   reg             up_tdd_gated_rx_dmapath = 1'h0;
   reg             up_tdd_terminal_type = 1'h0;
-  reg             up_tdd_sync_enable = 1'h0;
 
   reg     [ 7:0]  up_tdd_burst_count = 8'h0;
   reg     [23:0]  up_tdd_counter_init = 24'h0;
@@ -213,7 +210,6 @@ module up_tdd_cntrl (
       up_tdd_gated_tx_dmapath <= 1'h0;
       up_tdd_gated_rx_dmapath <= 1'h0;
       up_tdd_terminal_type <= 1'h0;
-      up_tdd_sync_enable <= 1'h0;
       up_tdd_counter_init <= 24'h0;
       up_tdd_frame_length <= 24'h0;
       up_tdd_burst_count <= 8'h0;
@@ -258,8 +254,7 @@ module up_tdd_cntrl (
         up_tdd_frame_length <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
-        up_tdd_terminal_type <= up_wdata[1];
-        up_tdd_sync_enable <= up_wdata[0];
+        up_tdd_terminal_type <= up_wdata[0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
         up_tdd_vco_rx_on_1 <= up_wdata[23:0];
@@ -346,8 +341,7 @@ module up_tdd_cntrl (
           8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
           8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
           8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
-          8'h14: up_rdata <= {30'h0, up_tdd_terminal_type,
-                                     up_tdd_sync_enable};
+          8'h14: up_rdata <= {31'h0, up_tdd_terminal_type};
           8'h18: up_rdata <= {24'h0, up_tdd_status_s};
           8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
           8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
@@ -377,7 +371,7 @@ module up_tdd_cntrl (
 
   // rf tdd control signal CDC
 
-  up_xfer_cntrl #(.DATA_WIDTH(16)) i_xfer_tdd_control (
+  up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_tdd_control (
     .up_rstn(up_rstn),
     .up_clk(up_clk),
     .up_data_cntrl({up_tdd_enable,
@@ -387,9 +381,8 @@ module up_tdd_cntrl (
                     up_tdd_gated_rx_dmapath,
                     up_tdd_gated_tx_dmapath,
                     up_tdd_burst_count,
-                    up_tdd_terminal_type,
-                    up_tdd_sync_enable
-    }),
+                    up_tdd_terminal_type
+                  }),
     .up_xfer_done(),
     .d_rst(rst),
     .d_clk(clk),
@@ -400,8 +393,7 @@ module up_tdd_cntrl (
                    tdd_gated_rx_dmapath,
                    tdd_gated_tx_dmapath,
                    tdd_burst_count,
-                   tdd_terminal_type,
-                   tdd_sync_enable
+                   tdd_terminal_type
     }));
 
   up_xfer_cntrl #(.DATA_WIDTH(528)) i_xfer_tdd_counter_values (
diff --git a/library/util_tdd_sync/util_tdd_sync.v b/library/util_tdd_sync/util_tdd_sync.v
index a687e9381..1fa21bd46 100644
--- a/library/util_tdd_sync/util_tdd_sync.v
+++ b/library/util_tdd_sync/util_tdd_sync.v
@@ -36,14 +36,20 @@
 // ***************************************************************************
 // ***************************************************************************
 // ***************************************************************************
+//
+// Simple pulse generator for TDD control
+// The module has two modes. In function of the state of sync_mode,
+// the syncronization signal (sync_out) can get its value from an external
+// source or from its internal generator.
+//
+
 `timescale 1ns/1ps
 
 module util_tdd_sync (
   clk,
   rstn,
 
-  sync_en,
-  sync_type,
+  sync_mode,
 
   sync_in,
   sync_out
@@ -52,21 +58,19 @@ module util_tdd_sync (
   input         clk;
   input         rstn;
 
-  input         sync_en;
-  input         sync_type;
+  input         sync_mode;
 
   input         sync_in;
   output        sync_out;
 
   parameter TDD_SYNC_PERIOD     = 100000000;
 
-  reg           sync_en_d1  = 1'b0;
-  reg           sync_en_d2  = 1'b0;
-  reg           sync_type_d1 = 1'b0;
-  reg           sync_type_d2 = 1'b0;
+  reg           sync_mode_d1  = 1'b0;
+  reg           sync_mode_d2  = 1'b0;
   reg           sync_out = 1'b0;
 
-  wire          sync_gen;
+  wire          sync_internal;
+  wire          sync_external;
 
   // pulse generator
 
@@ -76,36 +80,29 @@ module util_tdd_sync (
     i_tdd_sync (
     .clk (clk),
     .rstn (rstn),
-    .sync (sync_gen)
+    .sync (sync_internal)
   );
 
   // synchronization logic
 
   always @(posedge clk) begin
     if(rstn == 1'b0) begin
-      sync_en_d1 <= 1'b0;
-      sync_en_d2 <= 1'b0;
-      sync_type_d1 <= 1'b0;
-      sync_type_d2 <= 1'b0;
+      sync_mode_d1 <= 1'b0;
+      sync_mode_d2 <= 1'b0;
     end else begin
-      sync_en_d1 <= sync_en;
-      sync_en_d2 <= sync_en_d1;
-      sync_type_d1 <= sync_type;
-      sync_type_d2 <= sync_type_d1;
+      sync_mode_d1 <= sync_mode;
+      sync_mode_d2 <= sync_mode_d1;
     end
   end
 
   // output logic
 
+  assign sync_external = sync_in;
   always @(posedge clk) begin
     if(rstn == 1'b0) begin
       sync_out <= 1'b0;
     end else begin
-      if(sync_en_d2 == 1'b1) begin
-        sync_out <= (sync_type_d2 == 1'b0) ? sync_gen : sync_in;
-      end else begin
-        sync_out <= 1'b0;
-      end
+      sync_out <= (sync_mode_d2 == 1'b0) ? sync_internal : sync_external;
     end
   end
 
diff --git a/library/util_tdd_sync/util_tdd_sync_constr.xdc b/library/util_tdd_sync/util_tdd_sync_constr.xdc
index 775e3e043..1685985a5 100644
--- a/library/util_tdd_sync/util_tdd_sync_constr.xdc
+++ b/library/util_tdd_sync/util_tdd_sync_constr.xdc
@@ -1,5 +1,4 @@
 
-set_false_path -to [get_cells -hier -filter {NAME =~ *sync_en_d1* && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {NAME =~ *sync_type_d1* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {NAME =~ *sync_mode_d1* && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {NAME =~ *sync_out_reg* && IS_SEQUENTIAL}]
 
diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl
index 17419f02f..5e35d8875 100644
--- a/projects/fmcomms2/common/fmcomms2_bd.tcl
+++ b/projects/fmcomms2/common/fmcomms2_bd.tcl
@@ -64,6 +64,7 @@ set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
 set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
 
 set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
+set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
 
 # connections
 
@@ -143,9 +144,8 @@ ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
 ad_connect  sys_cpu_clk util_ad9361_tdd_sync/clk
 ad_connect  sys_cpu_resetn util_ad9361_tdd_sync/rstn
 ad_connect  util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
-ad_connect  util_ad9361_tdd_sync/sync_en axi_ad9361/tdd_sync_en
-ad_connect  util_ad9361_tdd_sync/sync_type axi_ad9361/tdd_terminal_type
-ad_connect  tdd_sync_t axi_ad9361/tdd_terminal_type
+ad_connect  util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
+ad_connect  tdd_sync_t axi_ad9361/tdd_sync_cntr
 ad_connect  tdd_sync_o util_ad9361_tdd_sync/sync_out
 ad_connect  tdd_sync_i util_ad9361_tdd_sync/sync_in
 

From a747fad54046cd623c94583ab54373a2fe4cf3b0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 12 Feb 2016 14:33:34 +0200
Subject: [PATCH 077/972] axi_ad9361: tx_valid must be controlled by the TDD
 controller

---
 library/axi_ad9361/axi_ad9361.v     | 5 ++++-
 library/axi_ad9361/axi_ad9361_tdd.v | 7 +++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 544bf9007..bc96169d7 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -301,6 +301,7 @@ module axi_ad9361 (
   wire    [47:0]  adc_data_s;
   wire            adc_status_s;
   wire            dac_valid_s;
+  wire            g_dac_valid_s;
   wire    [47:0]  dac_data_s;
   wire            dac_valid_i0_s;
   wire            dac_valid_q0_s;
@@ -390,7 +391,7 @@ module axi_ad9361 (
     .adc_status (adc_status_s),
     .adc_r1_mode (adc_r1_mode),
     .adc_ddr_edgesel (adc_ddr_edgesel),
-    .dac_valid (dac_valid_s),
+    .dac_valid (g_dac_valid_s),
     .dac_data (dac_data_s),
     .dac_r1_mode (dac_r1_mode),
     .tdd_enable (tdd_enable_s),
@@ -443,10 +444,12 @@ module axi_ad9361 (
     .tdd_status (tdd_status_s),
     .tdd_sync (tdd_sync),
     .tdd_sync_cntr (tdd_sync_cntr),
+    .tx_valid (dac_valid_s),
     .tx_valid_i0 (dac_valid_i0_s),
     .tx_valid_q0 (dac_valid_q0_s),
     .tx_valid_i1 (dac_valid_i1_s),
     .tx_valid_q1 (dac_valid_q1_s),
+    .tdd_tx_valid (g_dac_valid_s),
     .tdd_tx_valid_i0 (dac_valid_i0),
     .tdd_tx_valid_q0 (dac_valid_q0),
     .tdd_tx_valid_i1 (dac_valid_i1),
diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index 27c008d6c..d32984860 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -65,11 +65,13 @@ module axi_ad9361_tdd (
 
   // tx/rx data flow control
 
+  tx_valid,
   tx_valid_i0,
   tx_valid_q0,
   tx_valid_i1,
   tx_valid_q1,
 
+  tdd_tx_valid,
   tdd_tx_valid_i0,
   tdd_tx_valid_q0,
   tdd_tx_valid_i1,
@@ -119,11 +121,13 @@ module axi_ad9361_tdd (
 
   // tx data flow control
 
+  input             tx_valid;
   input             tx_valid_i0;
   input             tx_valid_q0;
   input             tx_valid_i1;
   input             tx_valid_q1;
 
+  output            tdd_tx_valid;
   output            tdd_tx_valid_i0;
   output            tdd_tx_valid_q0;
   output            tdd_tx_valid_i1;
@@ -158,6 +162,7 @@ module axi_ad9361_tdd (
 
   reg               tdd_slave_synced = 1'b0;
 
+  reg               tdd_tx_valid    = 1'b0;
   reg               tdd_tx_valid_i0 = 1'b0;
   reg               tdd_tx_valid_q0 = 1'b0;
   reg               tdd_tx_valid_i1 = 1'b0;
@@ -216,11 +221,13 @@ module axi_ad9361_tdd (
 
   always @(posedge clk) begin
     if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
+      tdd_tx_valid    <= tx_valid & tdd_tx_dp_en_s;
       tdd_tx_valid_i0 <= tx_valid_i0 & tdd_tx_dp_en_s;
       tdd_tx_valid_q0 <= tx_valid_q0 & tdd_tx_dp_en_s;
       tdd_tx_valid_i1 <= tx_valid_i1 & tdd_tx_dp_en_s;
       tdd_tx_valid_q1 <= tx_valid_q1 & tdd_tx_dp_en_s;
     end else begin
+      tdd_tx_valid    <= tx_valid;
       tdd_tx_valid_i0 <= tx_valid_i0;
       tdd_tx_valid_q0 <= tx_valid_q0;
       tdd_tx_valid_i1 <= tx_valid_i1;

From 9675df15c6c27613f1970db2140276316e81a753 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 12 Feb 2016 14:37:02 +0200
Subject: [PATCH 078/972] daq1_zc706: Update constraints file

---
 projects/daq1/zc706/system_constr.xdc | 76 +++++++++++++--------------
 1 file changed, 38 insertions(+), 38 deletions(-)

diff --git a/projects/daq1/zc706/system_constr.xdc b/projects/daq1/zc706/system_constr.xdc
index 86a25c8bc..f00fd103b 100644
--- a/projects/daq1/zc706/system_constr.xdc
+++ b/projects/daq1/zc706/system_constr.xdc
@@ -3,50 +3,50 @@
 
 set_property  -dict {PACKAGE_PIN  AC28  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports dac_clk_in_p]            ; ##  G02  FMC_LPC_CLK1_M2C_P
 set_property  -dict {PACKAGE_PIN  AD28  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports dac_clk_in_n]            ; ##  G03  FMC_LPC_CLK1_M2C_N
-set_property  -dict {PACKAGE_PIN  AG17  IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p]                          ; ##  H4   FMC_LPC_CLK0_M2C_P
-set_property  -dict {PACKAGE_PIN  AG16  IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n]                          ; ##  H5   FMC_LPC_CLK0_M2C_N
+set_property  -dict {PACKAGE_PIN  AF29  IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p]                          ; ##  G27  FMC_LPC_LA25_P
+set_property  -dict {PACKAGE_PIN  AG29  IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n]                          ; ##  G28  FMC_LPC_LA25_N
 
-set_property  -dict {PACKAGE_PIN  AB27  IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p]                        ; ##  D20  FMC_LPC_LA17_CC_P
-set_property  -dict {PACKAGE_PIN  AC27  IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n]                        ; ##  D21  FMC_LPC_LA17_CC_N
+set_property  -dict {PACKAGE_PIN  Y26   IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p]                        ; ##  H37  FMC_LPC_LA32_P
+set_property  -dict {PACKAGE_PIN  Y27   IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n]                        ; ##  H38  FMC_LPC_LA32_N
 
-set_property  -dict {PACKAGE_PIN  AE27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]]                      ; ##  C22  FMC_LPC_LA18_CC_P
-set_property  -dict {PACKAGE_PIN  AF27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]]                      ; ##  C23  FMC_LPC_LA18_CC_N
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]]                      ; ##  H19  FMC_LPC_LA15_P
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]]                      ; ##  H20  FMC_LPC_LA15_N
 set_property  -dict {PACKAGE_PIN  AG26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]]                      ; ##  G21  FMC_LPC_LA20_P
 set_property  -dict {PACKAGE_PIN  AG27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[1]]                      ; ##  G22  FMC_LPC_LA20_N
 set_property  -dict {PACKAGE_PIN  AH26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[2]]                      ; ##  H22  FMC_LPC_LA19_P
 set_property  -dict {PACKAGE_PIN  AH27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[2]]                      ; ##  H23  FMC_LPC_LA19_N
-set_property  -dict {PACKAGE_PIN  AJ26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]]                      ; ##  D23  FMC_LPC_LA23_P
-set_property  -dict {PACKAGE_PIN  AK26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]]                      ; ##  D24  FMC_LPC_LA23_N
-set_property  -dict {PACKAGE_PIN  AK27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]]                      ; ##  G24  FMC_LPC_LA22_P
-set_property  -dict {PACKAGE_PIN  AK28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]]                      ; ##  G25  FMC_LPC_LA22_N
-set_property  -dict {PACKAGE_PIN  AH28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]]                      ; ##  H25  FMC_LPC_LA21_P
-set_property  -dict {PACKAGE_PIN  AH29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]]                      ; ##  H26  FMC_LPC_LA21_N
-set_property  -dict {PACKAGE_PIN  AJ30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]]                      ; ##  D26  FMC_LPC_LA26_P
-set_property  -dict {PACKAGE_PIN  AK30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]]                      ; ##  D27  FMC_LPC_LA26_N
-set_property  -dict {PACKAGE_PIN  AF29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]]                      ; ##  G27  FMC_LPC_LA25_P
-set_property  -dict {PACKAGE_PIN  AG29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]]                      ; ##  G28  FMC_LPC_LA25_N
-set_property  -dict {PACKAGE_PIN  AF30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]]                      ; ##  H28  FMC_LPC_LA24_P
-set_property  -dict {PACKAGE_PIN  AG30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]]                      ; ##  H29  FMC_LPC_LA24_N
-set_property  -dict {PACKAGE_PIN  AJ28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]]                      ; ##  C26  FMC_LPC_LA27_P
-set_property  -dict {PACKAGE_PIN  AJ29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]]                      ; ##  C27  FMC_LPC_LA27_N
-set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]]                     ; ##  G30  FMC_LPC_LA29_P
-set_property  -dict {PACKAGE_PIN  AF25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]]                     ; ##  G31  FMC_LPC_LA29_N
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]]                     ; ##  H31  FMC_LPC_LA28_P
-set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]]                     ; ##  H32  FMC_LPC_LA28_N
-set_property  -dict {PACKAGE_PIN  AC29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]]                     ; ##  G33  FMC_LPC_LA31_P
-set_property  -dict {PACKAGE_PIN  AD29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]]                     ; ##  G34  FMC_LPC_LA31_N
-set_property  -dict {PACKAGE_PIN  AB29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]]                     ; ##  H34  FMC_LPC_LA30_P
-set_property  -dict {PACKAGE_PIN  AB30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]]                     ; ##  H35  FMC_LPC_LA30_N
-set_property  -dict {PACKAGE_PIN   Y30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]]                     ; ##  G09  FMC_LPC_LA33_P
-set_property  -dict {PACKAGE_PIN  AA30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]]                     ; ##  G10  FMC_LPC_LA33_N
-set_property  -dict {PACKAGE_PIN   Y26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]]                     ; ##  H37  FMC_LPC_LA32_P
-set_property  -dict {PACKAGE_PIN   Y27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]]                     ; ##  H38  FMC_LPC_LA32_N
+set_property  -dict {PACKAGE_PIN  AB27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]]                      ; ##  D20  FMC_LPC_LA17_CC_P
+set_property  -dict {PACKAGE_PIN  AC27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]]                      ; ##  D21  FMC_LPC_LA17_CC_N
+set_property  -dict {PACKAGE_PIN  AJ26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]]                      ; ##  D23  FMC_LPC_LA23_P
+set_property  -dict {PACKAGE_PIN  AK26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]]                      ; ##  D24  FMC_LPC_LA23_N
+set_property  -dict {PACKAGE_PIN  AK27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]]                      ; ##  G24  FMC_LPC_LA22_P
+set_property  -dict {PACKAGE_PIN  AK28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]]                      ; ##  G25  FMC_LPC_LA22_N
+set_property  -dict {PACKAGE_PIN  AE27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]]                      ; ##  C22  FMC_LPC_LA18_CC_P
+set_property  -dict {PACKAGE_PIN  AF27  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]]                      ; ##  C23  FMC_LPC_LA18_CC_N
+set_property  -dict {PACKAGE_PIN  AH28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]]                      ; ##  H25  FMC_LPC_LA21_P
+set_property  -dict {PACKAGE_PIN  AH29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]]                      ; ##  H26  FMC_LPC_LA21_N
+set_property  -dict {PACKAGE_PIN  AJ30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]]                      ; ##  D26  FMC_LPC_LA26_P
+set_property  -dict {PACKAGE_PIN  AK30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]]                      ; ##  D27  FMC_LPC_LA26_N
+set_property  -dict {PACKAGE_PIN  AF30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]]                      ; ##  H28  FMC_LPC_LA24_P
+set_property  -dict {PACKAGE_PIN  AG30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]]                      ; ##  H29  FMC_LPC_LA24_N
+set_property  -dict {PACKAGE_PIN  AJ28  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]]                     ; ##  C26  FMC_LPC_LA27_P
+set_property  -dict {PACKAGE_PIN  AJ29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]]                     ; ##  C27  FMC_LPC_LA27_N
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]]                     ; ##  G30  FMC_LPC_LA29_P
+set_property  -dict {PACKAGE_PIN  AF25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]]                     ; ##  G31  FMC_LPC_LA29_N
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]]                     ; ##  H31  FMC_LPC_LA28_P
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]]                     ; ##  H32  FMC_LPC_LA28_N
+set_property  -dict {PACKAGE_PIN  AC29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]]                     ; ##  G33  FMC_LPC_LA31_P
+set_property  -dict {PACKAGE_PIN  AD29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]]                     ; ##  G34  FMC_LPC_LA31_N
+set_property  -dict {PACKAGE_PIN  AB29  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]]                     ; ##  H34  FMC_LPC_LA30_P
+set_property  -dict {PACKAGE_PIN  AB30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]]                     ; ##  H35  FMC_LPC_LA30_N
+set_property  -dict {PACKAGE_PIN  Y30   IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]]                     ; ##  G36  FMC_LPC_LA33_P
+set_property  -dict {PACKAGE_PIN  AA30  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]]                     ; ##  G37  FMC_LPC_LA33_N
 
 set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_clk_in_p]            ; ##  G06  FMC_LPC_LA00_CC_P
 set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_clk_in_n]            ; ##  G07  FMC_LPC_LA00_CC_N
 
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]        ; ##  G12  FMC_LPC_LA08_P
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]        ; ##  G13  FMC_LPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]        ; ##  C14  FMC_LPC_LA10_P
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]        ; ##  C15  FMC_LPC_LA10_N
 set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]        ; ##  C18  FMC_LPC_LA14_P
 set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[1]]        ; ##  C19  FMC_LPC_LA14_N
 set_property  -dict {PACKAGE_PIN  AH17  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[2]]        ; ##  D17  FMC_LPC_LA13_P
@@ -59,8 +59,8 @@ set_property  -dict {PACKAGE_PIN  AH14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get
 set_property  -dict {PACKAGE_PIN  AH13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[5]]        ; ##  D15  FMC_LPC_LA09_N
 set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[6]]        ; ##  H13  FMC_LPC_LA07_P
 set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[6]]        ; ##  H14  FMC_LPC_LA07_N
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]        ; ##  C14  FMC_LPC_LA10_P
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]        ; ##  C15  FMC_LPC_LA10_N
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]        ; ##  G12  FMC_LPC_LA08_P
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]        ; ##  G13  FMC_LPC_LA08_N
 set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[8]]        ; ##  D11  FMC_LPC_LA05_P
 set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[8]]        ; ##  D12  FMC_LPC_LA05_N
 set_property  -dict {PACKAGE_PIN  AJ15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[9]]        ; ##  H10  FMC_LPC_LA04_P
@@ -74,8 +74,8 @@ set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get
 set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]       ; ##  D08  FMC_LPC_LA01_CC_P
 set_property  -dict {PACKAGE_PIN  AG15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]       ; ##  D09  FMC_LPC_LA01_CC_N
 
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25} [get_ports cpld_sclk]                              ; ##  H19  FMC_LPC_LA15_P
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25} [get_ports cpld_csn]                               ; ##  H20  FMC_LPC_LA15_N
+set_property  -dict {PACKAGE_PIN  AG17  IOSTANDARD LVCMOS25} [get_ports cpld_sclk]                              ; ##  H04  FMC_LPC_CLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  AG16  IOSTANDARD LVCMOS25} [get_ports cpld_csn]                               ; ##  H05  FMC_LPC_CLK0_M2C_N
 set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports cpld_sdio]                              ; ##  G18  FMC_LPC_LA16_P
 set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports daq1_irq]                               ; ##  G19  FMC_LPC_LA16_N
 

From c32d7147d5719705467d9583da37c98495b05bb2 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 12 Feb 2016 14:38:32 +0200
Subject: [PATCH 079/972] daq1 : There is a single CSN from master

---
 projects/daq1/common/daq1_spi.v | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/projects/daq1/common/daq1_spi.v b/projects/daq1/common/daq1_spi.v
index c9dd27123..e699f37da 100644
--- a/projects/daq1/common/daq1_spi.v
+++ b/projects/daq1/common/daq1_spi.v
@@ -73,13 +73,11 @@ module daq1_spi (
 
   // internal signals
 
-  wire            spi_csn_s;
   wire            spi_enable_s;
 
   // check on rising edge and change on falling edge
 
-  assign spi_csn_s = & spi_csn;
-  assign spi_enable_s = spi_enable & ~spi_csn_s;
+  assign spi_enable_s = spi_enable & ~spi_csn;
 
   always @(posedge spi_clk or posedge spi_csn_s) begin
     if (spi_csn_s == 1'b1) begin

From e1c5d6a8f7ba50ac4997b945c30a2ac44b7b0406 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 12 Feb 2016 14:38:59 +0200
Subject: [PATCH 080/972] axi_ad9684: Fix constraint file

---
 library/axi_ad9684/axi_ad9684_constr.xdc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/library/axi_ad9684/axi_ad9684_constr.xdc b/library/axi_ad9684/axi_ad9684_constr.xdc
index 3d94bab25..fa9ce5ae5 100644
--- a/library/axi_ad9684/axi_ad9684_constr.xdc
+++ b/library/axi_ad9684/axi_ad9684_constr.xdc
@@ -1,2 +1 @@
-set_false_path  -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}]
-                -to   [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]
+set_false_path  -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to   [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]

From aa2ff0223a94916e5f0a61fc245fa6c54f68443e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 12 Feb 2016 14:45:18 +0200
Subject: [PATCH 081/972] daq1: Update CPLD design

+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
---
 projects/daq1/cpld/daq1_cpld.v | 35 +++++++++++++++++++---------------
 1 file changed, 20 insertions(+), 15 deletions(-)

diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
index 550780a78..75724d0fc 100644
--- a/projects/daq1/cpld/daq1_cpld.v
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -110,13 +110,16 @@ module daq1_cpld (
 
   // CPLD Register Map Addresses
 
-  localparam  [ 6:0]  ADC_CONTROL_ADDR    = 7'h00;
-  localparam  [ 6:0]  DAC_CONTROL_ADDR    = 7'h01;
-  localparam  [ 6:0]  CLK_CONTROL_ADDR    = 7'h02;
-  localparam  [ 6:0]  IRQ_MASK_ADDR       = 7'h03;
-  localparam  [ 6:0]  ADC_STATUS_ADDR     = 7'h10;
-  localparam  [ 6:0]  DAC_STATUS_ADDR     = 7'h11;
-  localparam  [ 6:0]  CLK_STATUS_ADDR     = 7'h12;
+  localparam  [ 6:0]  CPLD_VERSION_ADDR   = 7'h00;
+  localparam  [ 6:0]  ADC_CONTROL_ADDR    = 7'h10;
+  localparam  [ 6:0]  DAC_CONTROL_ADDR    = 7'h11;
+  localparam  [ 6:0]  CLK_CONTROL_ADDR    = 7'h12;
+  localparam  [ 6:0]  IRQ_MASK_ADDR       = 7'h13;
+  localparam  [ 6:0]  ADC_STATUS_ADDR     = 7'h20;
+  localparam  [ 6:0]  DAC_STATUS_ADDR     = 7'h21;
+  localparam  [ 6:0]  CLK_STATUS_ADDR     = 7'h22;
+
+  localparam  [ 7:0]  CPLD_VERSION        = 8'hDAC10101;
 
   // Internal Registers/Signals
 
@@ -148,11 +151,9 @@ module daq1_cpld (
 
   always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
     if (fmc_spi_csn == 1'b1) begin
-      fmc_spi_counter <= 6'h0;
       fmc_spi_dev_sel <= 8'h0;
       fmc_cpld_addr <= 8'h0;
     end else begin
-      fmc_spi_counter <= fmc_spi_counter + 1;
       if (fmc_spi_counter <= 7) begin
         fmc_spi_dev_sel <= {fmc_spi_dev_sel[6:0], fmc_spi_sdio};
       end
@@ -180,14 +181,16 @@ module daq1_cpld (
 
   always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
     if (fmc_spi_csn == 1'b1) begin
+      fmc_spi_counter <= 6'h0;
       fpga_to_cpld <= 1'b1;
       fmc_spi_csn_enb <= 1'b1;
     end else begin
+      fmc_spi_counter <= fmc_spi_counter + 1;
       fmc_spi_csn_enb <= (fmc_spi_counter <= 7) ? 1'b1 : 1'b0;
       if (adc_spicsn & clk_spicsn) begin
-        fpga_to_cpld <= (fmc_spi_counter >= 16) ? rdnwr : 1'b1;
+        fpga_to_cpld <= (fmc_spi_counter >= 15) ? rdnwr : 1'b1;
       end else begin
-        fpga_to_cpld <= (fmc_spi_counter >= 24) ? rdnwr : 1'b1;
+        fpga_to_cpld <= (fmc_spi_counter >= 23) ? rdnwr : 1'b1;
       end
     end
   end
@@ -196,6 +199,8 @@ module daq1_cpld (
 
   always @(fmc_cpld_addr) begin
     case (fmc_cpld_addr[6:0])
+      CPLD_VERSION_ADDR :
+        cpld_rdata <= CPLD_VERSION;
       ADC_CONTROL_ADDR :
         cpld_rdata <= adc_pwdn_stby;
       DAC_CONTROL_ADDR :
@@ -218,18 +223,18 @@ module daq1_cpld (
   always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
     if (fmc_spi_csn == 1'b1) begin
       cpld_rdata_bit <= 1'b0;
-      cpld_rdata_index <= 3'h0;
+      cpld_rdata_index <= 3'h7;
     end else begin
       if (fpga_to_cpld == 1'b0) begin
         cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];
-        cpld_rdata_index <= cpld_rdata_index + 1;
+        cpld_rdata_index <= cpld_rdata_index - 1;
       end
     end
   end
 
   // Internal register write access
 
-  always @(negedge fmc_spi_sclk) begin
+  always @(fpga_to_cpld, cpld_spicsn, fmc_spi_counter) begin
     if ((fpga_to_cpld == 1'b1) &&
         (cpld_spicsn == 1'b0) &&
         (fmc_spi_counter == 8'h18)) begin
@@ -277,7 +282,7 @@ module daq1_cpld (
   always @(*) begin
     cpld_irq <= {2'b00, dac_irqn, clk_status2, clk_status1, adc_status_p, adc_fdb, adc_fda};
   end
-  
+
   assign fmc_irq = |(~cpld_irq_mask & cpld_irq);
 
 endmodule

From 5ed2c0b599e9872d3c5f96e7b0bcfb90d7f45415 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 12 Feb 2016 16:54:36 +0200
Subject: [PATCH 082/972] daq1: Update CPLD constraints file

---
 projects/daq1/cpld/daq1_cpld.ucf | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/projects/daq1/cpld/daq1_cpld.ucf b/projects/daq1/cpld/daq1_cpld.ucf
index 09013707c..67a31e5d4 100644
--- a/projects/daq1/cpld/daq1_cpld.ucf
+++ b/projects/daq1/cpld/daq1_cpld.ucf
@@ -16,10 +16,10 @@ NET "clk_syncn"  LOC = "P24" | IOSTANDARD = LVCMOS33 ;
 NET "dac_irqn"  LOC = "P26" | IOSTANDARD = LVCMOS33 ; 
 NET "dac_resetn"  LOC = "P27" | IOSTANDARD = LVCMOS33 ; 
 NET "dac_spicsn"  LOC = "P14" | IOSTANDARD = LVCMOS33 ; 
-NET "fmc_irq"  LOC = "P5" | IOSTANDARD = LVCMOS25 ; 
-NET "fmc_spi_csn"  LOC = "P2" | IOSTANDARD = LVCMOS25 ; 
-NET "fmc_spi_sclk"  LOC = "P1" | IOSTANDARD = LVCMOS25; 
-NET "fmc_spi_sdio"  LOC = "P4" | IOSTANDARD = LVCMOS25 ; 
+NET "fmc_irq"  LOC = "P2" | IOSTANDARD = LVCMOS25; 
+NET "fmc_spi_csn"  LOC = "P5" | IOSTANDARD = LVCMOS25 ; 
+NET "fmc_spi_sclk"  LOC = "P4" | IOSTANDARD = LVCMOS25 ; 
+NET "fmc_spi_sdio"  LOC = "P1" | IOSTANDARD = LVCMOS25 ; 
 NET "sclk"  LOC = "P30" | IOSTANDARD = LVCMOS33 ; 
 NET "sdio"  LOC = "P28" | IOSTANDARD = LVCMOS33 ; 
 

From 9370246cfa5bb7ea69e3c405f67f1765fb7b867c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 12 Feb 2016 16:59:09 +0200
Subject: [PATCH 083/972] daq1: Fix bugs on CPLD design

Fix the CSN forwarding.
---
 projects/daq1/cpld/daq1_cpld.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
index 75724d0fc..b2bcdd628 100644
--- a/projects/daq1/cpld/daq1_cpld.v
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -186,7 +186,7 @@ module daq1_cpld (
       fmc_spi_csn_enb <= 1'b1;
     end else begin
       fmc_spi_counter <= fmc_spi_counter + 1;
-      fmc_spi_csn_enb <= (fmc_spi_counter <= 7) ? 1'b1 : 1'b0;
+      fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0;
       if (adc_spicsn & clk_spicsn) begin
         fpga_to_cpld <= (fmc_spi_counter >= 15) ? rdnwr : 1'b1;
       end else begin

From 051ac307e606e8d8a88aeec67777022f63c335f9 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 15 Feb 2016 19:26:58 +0200
Subject: [PATCH 084/972] daq1_cpld: Do not forward the first eight clock
 cycles of fmc_spi_sclk  to sclk

---
 projects/daq1/cpld/daq1_cpld.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
index b2bcdd628..642e3a353 100644
--- a/projects/daq1/cpld/daq1_cpld.v
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -119,7 +119,7 @@ module daq1_cpld (
   localparam  [ 6:0]  DAC_STATUS_ADDR     = 7'h21;
   localparam  [ 6:0]  CLK_STATUS_ADDR     = 7'h22;
 
-  localparam  [ 7:0]  CPLD_VERSION        = 8'hDAC10101;
+  localparam  [ 7:0]  CPLD_VERSION        = 8'h0101;
 
   // Internal Registers/Signals
 
@@ -172,13 +172,13 @@ module daq1_cpld (
 
   // SPI control and data
 
-  assign sclk = fmc_spi_sclk;
   assign sdio = fpga_to_cpld ? fmc_spi_sdio : 1'bZ;
   assign fmc_spi_sdio = fpga_to_cpld ? 1'bZ : cpld_rdata_s;
   assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
-
   assign rdnwr = ~fmc_cpld_addr[7];
 
+  assign    sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0;
+
   always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
     if (fmc_spi_csn == 1'b1) begin
       fmc_spi_counter <= 6'h0;

From 5518c47ca4b49e025bd6a25a6015ac49543aa7dd Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 15 Feb 2016 19:27:59 +0200
Subject: [PATCH 085/972] daq1_cpld: Set Input and tristate I/O termination
 mode to FLOAT

---
 projects/daq1/cpld/daq1_cpld.xise | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq1/cpld/daq1_cpld.xise b/projects/daq1/cpld/daq1_cpld.xise
index bd926f9fe..883441fe6 100644
--- a/projects/daq1/cpld/daq1_cpld.xise
+++ b/projects/daq1/cpld/daq1_cpld.xise
@@ -86,7 +86,7 @@
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Float" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>

From a8e9d7227361719e663a8952f7ccb597c29681c3 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 17 Feb 2016 14:16:04 -0500
Subject: [PATCH 086/972] adc/dac - prefix parameters

---
 library/common/up_adc_channel.v | 5 +++--
 library/common/up_adc_common.v  | 5 +++--
 library/common/up_dac_channel.v | 5 +++--
 library/common/up_dac_common.v  | 5 +++--
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/library/common/up_adc_channel.v b/library/common/up_adc_channel.v
index b6d85dfd4..f52319ab9 100644
--- a/library/common/up_adc_channel.v
+++ b/library/common/up_adc_channel.v
@@ -96,6 +96,7 @@ module up_adc_channel (
 
   // parameters
 
+  parameter ADC_COMMON_ID = 6'h01;
   parameter ADC_CHANNEL_ID = 4'h0;
 
   // adc interface
@@ -211,8 +212,8 @@ module up_adc_channel (
 
   // decode block select
 
-  assign up_wreq_s = ((up_waddr[13:8] == 6'h01) && (up_waddr[7:4] == ADC_CHANNEL_ID)) ? up_wreq : 1'b0;
-  assign up_rreq_s = ((up_raddr[13:8] == 6'h01) && (up_raddr[7:4] == ADC_CHANNEL_ID)) ? up_rreq : 1'b0;
+  assign up_wreq_s = ((up_waddr[13:8] == ADC_COMMON_ID) && (up_waddr[7:4] == ADC_CHANNEL_ID)) ? up_wreq : 1'b0;
+  assign up_rreq_s = ((up_raddr[13:8] == ADC_COMMON_ID) && (up_raddr[7:4] == ADC_CHANNEL_ID)) ? up_rreq : 1'b0;
 
   // processor write interface
 
diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index 29ccd571f..2a9738b8d 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -98,6 +98,7 @@ module up_adc_common (
 
   localparam  PCORE_VERSION = 32'h00090062;
   parameter   ID = 0;
+  parameter   ADC_COMMON_ID = 6'h00;
 
   // clock reset
 
@@ -194,8 +195,8 @@ module up_adc_common (
 
   // decode block select
 
-  assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
-  assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
+  assign up_wreq_s = (up_waddr[13:8] == ADC_COMMON_ID) ? up_wreq : 1'b0;
+  assign up_rreq_s = (up_raddr[13:8] == ADC_COMMON_ID) ? up_rreq : 1'b0;
 
   // processor write interface
 
diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v
index 24e9437e7..e42f2fc08 100644
--- a/library/common/up_dac_channel.v
+++ b/library/common/up_dac_channel.v
@@ -90,6 +90,7 @@ module up_dac_channel (
 
   // parameters
 
+  parameter DAC_COMMON_ID = 6'h11;
   parameter DAC_CHANNEL_ID = 4'h0;
 
   // dac interface
@@ -193,8 +194,8 @@ module up_dac_channel (
 
   // decode block select
 
-  assign up_wreq_s = ((up_waddr[13:8] == 6'h11) && (up_waddr[7:4] == DAC_CHANNEL_ID)) ? up_wreq : 1'b0;
-  assign up_rreq_s = ((up_raddr[13:8] == 6'h11) && (up_raddr[7:4] == DAC_CHANNEL_ID)) ? up_rreq : 1'b0;
+  assign up_wreq_s = ((up_waddr[13:8] == DAC_COMMON_ID) && (up_waddr[7:4] == DAC_CHANNEL_ID)) ? up_wreq : 1'b0;
+  assign up_rreq_s = ((up_raddr[13:8] == DAC_COMMON_ID) && (up_raddr[7:4] == DAC_CHANNEL_ID)) ? up_rreq : 1'b0;
 
   // processor write interface
 
diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index 2b1f76280..1b6013585 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -93,6 +93,7 @@ module up_dac_common (
 
   localparam  PCORE_VERSION = 32'h00080062;
   parameter   ID = 0;
+  parameter   DAC_COMMON_ID = 6'h10;
 
   // mmcm reset
 
@@ -194,8 +195,8 @@ module up_dac_common (
 
   // decode block select
 
-  assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0;
-  assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0;
+  assign up_wreq_s = (up_waddr[13:8] == DAC_COMMON_ID) ? up_wreq : 1'b0;
+  assign up_rreq_s = (up_raddr[13:8] == DAC_COMMON_ID) ? up_rreq : 1'b0;
 
   // processor write interface
 

From ce760eb69128b2a28ede42c13e9aea066749a652 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 18 Feb 2016 16:17:33 -0500
Subject: [PATCH 087/972] fmcadc2- add adf4355 access

---
 projects/fmcadc2/common/fmcadc2_spi.v    | 71 ++++++++++++++----------
 projects/fmcadc2/zc706/system_constr.xdc |  8 +--
 projects/fmcadc2/zc706/system_top.v      | 46 +++++++--------
 3 files changed, 69 insertions(+), 56 deletions(-)

diff --git a/projects/fmcadc2/common/fmcadc2_spi.v b/projects/fmcadc2/common/fmcadc2_spi.v
index 6434eef4f..f387d8a0b 100644
--- a/projects/fmcadc2/common/fmcadc2_spi.v
+++ b/projects/fmcadc2/common/fmcadc2_spi.v
@@ -39,33 +39,47 @@
 
 module fmcadc2_spi (
 
+  spi_adf4355,
+  spi_adf4355_ce,
+
   spi_clk,
-
-  spi_adc_csn,
-  spi_ext_csn_0,
-  spi_ext_csn_1,
-
+  spi_csn,
   spi_mosi,
   spi_miso,
 
+  spi_adc_csn,
+  spi_adc_clk,
   spi_adc_sdio,
-  spi_ext_sdio);
+
+  spi_adf4355_data_or_csn_0,
+  spi_adf4355_clk_or_csn_1,
+  spi_adf4355_le_or_clk,
+  spi_adf4355_ce_or_sdio);
+
+  // select (adf4355 = 0x1), (normal = 0x0)
+
+  input           spi_adf4355;
+  input           spi_adf4355_ce;
 
   // 4 wire
 
   input           spi_clk;
-
-  input           spi_adc_csn;
-  input           spi_ext_csn_0;
-  input           spi_ext_csn_1;
-
+  input   [ 2:0]  spi_csn;
   input           spi_mosi;
   output          spi_miso;
 
-  // 3 wire
+  // adc interface (3 wire)
 
+  output          spi_adc_csn;
+  output          spi_adc_clk;
   inout           spi_adc_sdio;
-  inout           spi_ext_sdio;
+
+  // adf4355 or normal (AMP/EXT)
+
+  output          spi_adf4355_data_or_csn_0;
+  output          spi_adf4355_clk_or_csn_1;
+  output          spi_adf4355_le_or_clk;
+  inout           spi_adf4355_ce_or_sdio;
 
   // internal registers
 
@@ -77,12 +91,10 @@ module fmcadc2_spi (
 
   wire            spi_csn_s;
   wire            spi_enable_s;
-  wire            spi_adc_miso_s;
-  wire            spi_ext_miso_s;
 
   // check on rising edge and change on falling edge
 
-  assign spi_csn_s = spi_adc_csn & spi_ext_csn_0 & spi_ext_csn_1;
+  assign spi_csn_s = & spi_csn;
   assign spi_enable_s = spi_enable & ~spi_csn_s;
 
   always @(posedge spi_clk or posedge spi_csn_s) begin
@@ -107,23 +119,22 @@ module fmcadc2_spi (
     end
   end
 
-  assign spi_miso = ((spi_adc_miso_s & ~spi_adc_csn) |
-                     (spi_ext_miso_s & ~spi_ext_csn_0) |
-                     (spi_ext_miso_s & ~spi_ext_csn_1));
+  assign spi_miso = ((spi_adc_sdio & ~spi_csn[0]) | (~spi_adf4355 &
+    spi_adf4355_ce_or_sdio & ~(spi_csn[1] & spi_csn[2])));
 
-  // io butter
+  // adc interface (3 wire)
 
-  IOBUF i_iobuf_adc_sdio (
-    .T (spi_enable_s),
-    .I (spi_mosi),
-    .O (spi_adc_miso_s),
-    .IO (spi_adc_sdio));
+  assign spi_adc_csn = spi_csn[0];
+  assign spi_adc_clk = spi_clk;
+  assign spi_adc_sdio = (spi_enable_s == 1'b0) ? spi_mosi : 1'bz;
 
-  IOBUF i_iobuf_clk_sdio (
-    .T (spi_enable_s),
-    .I (spi_mosi),
-    .O (spi_ext_miso_s),
-    .IO (spi_ext_sdio));
+  // adf4355 or normal (AMP/EXT)
+
+  assign spi_adf4355_data_or_csn_0 = (spi_adf4355 == 1'b1) ? spi_mosi : spi_csn[1];
+  assign spi_adf4355_clk_or_csn_1 = (spi_adf4355 == 1'b1) ? spi_clk : spi_csn[2];
+  assign spi_adf4355_le_or_clk = (spi_adf4355 == 1'b1) ? spi_csn[1] : spi_clk;
+  assign spi_adf4355_ce_or_sdio = (spi_adf4355 == 1'b1) ? spi_adf4355_ce :
+    ((spi_enable_s == 1'b0) ? spi_mosi : 1'bz);
 
 endmodule
 
diff --git a/projects/fmcadc2/zc706/system_constr.xdc b/projects/fmcadc2/zc706/system_constr.xdc
index bce5b3159..1543f7f93 100644
--- a/projects/fmcadc2/zc706/system_constr.xdc
+++ b/projects/fmcadc2/zc706/system_constr.xdc
@@ -27,10 +27,10 @@ set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
 set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVCMOS25} [get_ports spi_adc_csn]                  ; ## H08  FMC_HPC_LA02_N
 set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVCMOS25} [get_ports spi_adc_clk]                  ; ## D08  FMC_HPC_LA01_CC_P
 set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVCMOS25} [get_ports spi_adc_sdio]                 ; ## D09  FMC_HPC_LA01_CC_N
-set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVCMOS25} [get_ports spi_ext_csn_0]                ; ## H07  FMC_HPC_LA02_P
-set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports spi_ext_csn_1]                ; ## C10  FMC_HPC_LA06_P
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVCMOS25} [get_ports spi_ext_clk]                  ; ## G06  FMC_HPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN  AG20  IOSTANDARD LVCMOS25} [get_ports spi_ext_sdio]                 ; ## G07  FMC_HPC_LA00_CC_N
+set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVCMOS25} [get_ports spi_adf4355_data_or_csn_0]    ; ## H07  FMC_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports spi_adf4355_clk_or_csn_1]     ; ## C10  FMC_HPC_LA06_P
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVCMOS25} [get_ports spi_adf4355_le_or_clk]        ; ## G06  FMC_HPC_LA00_CC_P
+set_property  -dict {PACKAGE_PIN  AG20  IOSTANDARD LVCMOS25} [get_ports spi_adf4355_ce_or_sdio]       ; ## G07  FMC_HPC_LA00_CC_N
 
 set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVCMOS25} [get_ports adc_irq]                      ; ## G09  FMC_HPC_LA03_P
 set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVCMOS25} [get_ports adc_fd]                       ; ## G10  FMC_HPC_LA03_N
diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v
index f85bab7d4..69025e3bc 100644
--- a/projects/fmcadc2/zc706/system_top.v
+++ b/projects/fmcadc2/zc706/system_top.v
@@ -112,10 +112,11 @@ module system_top (
   spi_adc_csn,
   spi_adc_clk,
   spi_adc_sdio,
-  spi_ext_csn_0,
-  spi_ext_csn_1,
-  spi_ext_clk,
-  spi_ext_sdio);
+
+  spi_adf4355_data_or_csn_0,
+  spi_adf4355_clk_or_csn_1,
+  spi_adf4355_le_or_clk,
+  spi_adf4355_ce_or_sdio);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -188,10 +189,11 @@ module system_top (
   output          spi_adc_csn;
   output          spi_adc_clk;
   inout           spi_adc_sdio;
-  output          spi_ext_csn_0;
-  output          spi_ext_csn_1;
-  output          spi_ext_clk;
-  inout           spi_ext_sdio;
+
+  output          spi_adf4355_data_or_csn_0;
+  output          spi_adf4355_clk_or_csn_1;
+  output          spi_adf4355_le_or_clk;
+  inout           spi_adf4355_ce_or_sdio;
 
   // internal signals
 
@@ -210,14 +212,6 @@ module system_top (
   wire            rx_sysref;
   wire            rx_sync;
 
-  // spi
-
-  assign spi_adc_csn = spi0_csn[0];
-  assign spi_adc_clk = spi0_clk;
-  assign spi_ext_csn_0 = spi0_csn[1];
-  assign spi_ext_csn_1 = spi0_csn[2];
-  assign spi_ext_clk = spi0_clk;
-
   // instantiations
 
   IBUFDS_GTE2 i_ibufds_rx_ref_clk (
@@ -237,22 +231,30 @@ module system_top (
     .O (rx_sync_p),
     .OB (rx_sync_n));
 
+  // spi
+
+  assign gpio_i[37:36] = gpio_o[37:36];
+
   fmcadc2_spi i_fmcadc2_spi (
-    .spi_adc_csn (spi_adc_csn),
-    .spi_ext_csn_0 (spi_ext_csn_0),
-    .spi_ext_csn_1 (spi_ext_csn_1),
+    .spi_adf4355 (gpio_o[36]),
+    .spi_adf4355_ce (gpio_o[37]),
     .spi_clk (spi0_clk),
+    .spi_csn (spi0_csn),
     .spi_mosi (spi0_mosi),
     .spi_miso (spi0_miso),
+    .spi_adc_csn (spi_adc_csn),
+    .spi_adc_clk (spi_adc_clk),
     .spi_adc_sdio (spi_adc_sdio),
-    .spi_ext_sdio (spi_ext_sdio));
+    .spi_adf4355_data_or_csn_0 (spi_adf4355_data_or_csn_0),
+    .spi_adf4355_clk_or_csn_1 (spi_adf4355_clk_or_csn_1),
+    .spi_adf4355_le_or_clk (spi_adf4355_le_or_clk),
+    .spi_adf4355_ce_or_sdio (spi_adf4355_ce_or_sdio));
 
   ad_iobuf #(.DATA_WIDTH(2)) i_iobuf (
     .dio_t (gpio_t[33:32]),
     .dio_i (gpio_o[33:32]),
     .dio_o (gpio_i[33:32]),
-    .dio_p ({ adc_irq,    // 33
-              adc_fd}));  // 32
+    .dio_p ({adc_irq, adc_fd}));
 
   ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
     .dio_t (gpio_t[14:0]),

From 4fb6589b2d0378f9eca99c9ddcdec819d07cfbe9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 19 Feb 2016 16:40:54 -0500
Subject: [PATCH 088/972] pzsdr/ccfmc: add fan controls

---
 projects/pzsdr/ccfmc/system_constr.xdc | 4 ++++
 projects/pzsdr/ccfmc/system_top.v      | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/projects/pzsdr/ccfmc/system_constr.xdc b/projects/pzsdr/ccfmc/system_constr.xdc
index ac6233513..8ddea307b 100644
--- a/projects/pzsdr/ccfmc/system_constr.xdc
+++ b/projects/pzsdr/ccfmc/system_constr.xdc
@@ -88,6 +88,10 @@ set_property IODELAY_GROUP gmii2rgmii_iodelay_group\
   [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \
   [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}]
 
+# fan control/sense
+
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD LVCMOS18} [get_ports fan_pwm]    ; ## IO_L18P_T2_34
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD LVCMOS18} [get_ports fan_tach]   ; ## IO_L18N_T2_34
 
 # unused io (gpio/gt)
 
diff --git a/projects/pzsdr/ccfmc/system_top.v b/projects/pzsdr/ccfmc/system_top.v
index a9a748a02..95a24d9a1 100644
--- a/projects/pzsdr/ccfmc/system_top.v
+++ b/projects/pzsdr/ccfmc/system_top.v
@@ -93,6 +93,9 @@ module system_top (
 
   gpio_bd,
 
+  fan_pwm,
+  fan_tach,
+
   clk_0_p,
   clk_0_n,
   clk_1_p,
@@ -215,6 +218,9 @@ module system_top (
 
   inout   [11:0]  gpio_bd;
 
+  output          fan_pwm;
+  input           fan_tach;
+
   input           clk_0_p;
   input           clk_0_n;
   input           clk_1_p;
@@ -304,6 +310,7 @@ module system_top (
 
   // assignments
 
+  assign fan_pwm = 1'b1;
   assign hdmi_pd = 1'b0;
   assign spi_csn = spi_csn_s[0];
   assign spi_clk = spi_clk_s;

From c0a559a9b12865efad788afc73be943bb3e15db2 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 24 Feb 2016 14:31:56 +0200
Subject: [PATCH 089/972] daq1: Fix some typos in the SPI wrapper

---
 projects/daq1/common/daq1_spi.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/projects/daq1/common/daq1_spi.v b/projects/daq1/common/daq1_spi.v
index e699f37da..9ad1b84c0 100644
--- a/projects/daq1/common/daq1_spi.v
+++ b/projects/daq1/common/daq1_spi.v
@@ -79,8 +79,8 @@ module daq1_spi (
 
   assign spi_enable_s = spi_enable & ~spi_csn;
 
-  always @(posedge spi_clk or posedge spi_csn_s) begin
-    if (spi_csn_s == 1'b1) begin
+  always @(posedge spi_clk or posedge spi_csn) begin
+    if (spi_csn == 1'b1) begin
       spi_count <= 6'b0000000;
       spi_rd_wr_n <= 1'b0;
       spi_device_addr <= 8'b00000000;
@@ -95,8 +95,8 @@ module daq1_spi (
     end
   end
 
-  always @(negedge spi_clk or posedge spi_csn_s) begin
-    if (spi_csn_s == 1'b1) begin
+  always @(negedge spi_clk or posedge spi_csn) begin
+    if (spi_csn == 1'b1) begin
       spi_enable <= 1'b0;
     end else begin
       if (((spi_device_addr == SPI_SEL_AD9684) && (spi_count == 6'd24)) ||

From 59313f3c90d5c8a9c59a4eefdfe57b3b6c71d43f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 24 Feb 2016 14:37:19 +0200
Subject: [PATCH 090/972] daq1: ADC DMA must be in none-cyclic mode

---
 projects/daq1/common/daq1_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl
index ddb6557e1..b86268444 100644
--- a/projects/daq1/common/daq1_bd.tcl
+++ b/projects/daq1/common/daq1_bd.tcl
@@ -54,7 +54,7 @@ set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9684_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9684_dma
-set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9684_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9684_dma
 

From f7e490c2b3b12198dfb8eb929b76d2a83e9b2c30 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 26 Feb 2016 13:46:11 -0500
Subject: [PATCH 091/972] hdlmake.pl updates

---
 projects/Makefile                 |  3 +++
 projects/cn0363/Makefile          |  6 +++---
 projects/cn0363/microzed/Makefile | 17 ++---------------
 projects/cn0363/zed/Makefile      |  1 +
 projects/daq1/zc706/Makefile      | 18 +++++++++---------
 projects/daq3/Makefile            |  6 ++++++
 projects/daq3/a10gx/Makefile      | 11 +++++------
 projects/daq3/kcu105/Makefile     | 16 ++++++++--------
 projects/pzsdr/Makefile           |  3 +++
 projects/pzsdr1/Makefile          |  6 ------
 projects/pzsdr1/ccbrk/Makefile    |  8 +-------
 11 files changed, 41 insertions(+), 54 deletions(-)

diff --git a/projects/Makefile b/projects/Makefile
index 8170c81a4..b326e0903 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -34,6 +34,7 @@ all:
 	-make -C imageon all
 	-make -C motcon2_fmc all
 	-make -C pzsdr all
+	-make -C pzsdr1 all
 	-make -C usb_fx3 all
 	-make -C usdrx1 all
 
@@ -66,6 +67,7 @@ clean:
 	make -C imageon clean
 	make -C motcon2_fmc clean
 	make -C pzsdr clean
+	make -C pzsdr1 clean
 	make -C usb_fx3 clean
 	make -C usdrx1 clean
 
@@ -98,6 +100,7 @@ clean-all:
 	make -C imageon clean-all
 	make -C motcon2_fmc clean-all
 	make -C pzsdr clean-all
+	make -C pzsdr1 clean-all
 	make -C usb_fx3 clean-all
 	make -C usdrx1 clean-all
 
diff --git a/projects/cn0363/Makefile b/projects/cn0363/Makefile
index 97649c5b4..da85fadb8 100644
--- a/projects/cn0363/Makefile
+++ b/projects/cn0363/Makefile
@@ -7,18 +7,18 @@
 
 .PHONY: all clean clean-all 
 all:
-	-make -C zed all
 	-make -C microzed all
+	-make -C zed all
 
 
 clean: 
-	make -C zed clean
 	make -C microzed clean
+	make -C zed clean
 
 
 clean-all:
-	make -C zed clean-all
 	make -C microzed clean-all
+	make -C zed clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile
index 103980135..db68800f7 100644
--- a/projects/cn0363/microzed/Makefile
+++ b/projects/cn0363/microzed/Makefile
@@ -9,18 +9,16 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/cn0363_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/microzed/microzed_system_ps7.tcl
 M_DEPS += ../../common/microzed/microzed_system_constr.xdc
 M_DEPS += ../../common/microzed/microzed_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_generic_adc/axi_generic_adc.xpr
-M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
-M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
 M_DEPS += ../../../library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr
 M_DEPS += ../../../library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr
@@ -29,7 +27,6 @@ M_DEPS += ../../../library/spi_engine/spi_engine_execution/spi_engine_execution.
 M_DEPS += ../../../library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
 M_DEPS += ../../../library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
 M_DEPS += ../../../library/util_axis_resize/util_axis_resize.xpr
-M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
 M_DEPS += ../../../library/util_sigma_delta_spi/util_sigma_delta_spi.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -56,12 +53,8 @@ clean:
 
 
 clean-all:clean
-	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_generic_adc clean
-	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_i2s_adi clean
-	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/spi_engine/axi_spi_engine clean
 	make -C ../../../library/cn0363/cn0363_dma_sequencer clean
 	make -C ../../../library/cn0363/cn0363_phase_data_sync clean
@@ -70,7 +63,6 @@ clean-all:clean
 	make -C ../../../library/spi_engine/spi_engine_interconnect clean
 	make -C ../../../library/spi_engine/spi_engine_offload clean
 	make -C ../../../library/util_axis_resize clean
-	make -C ../../../library/util_i2c_mixer clean
 	make -C ../../../library/util_sigma_delta_spi clean
 
 
@@ -80,12 +72,8 @@ cn0363_microzed.sdk/system_top.hdf: $(M_DEPS)
 
 
 lib:
-	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_generic_adc
-	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_i2s_adi
-	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/spi_engine/axi_spi_engine
 	make -C ../../../library/cn0363/cn0363_dma_sequencer
 	make -C ../../../library/cn0363/cn0363_phase_data_sync
@@ -94,7 +82,6 @@ lib:
 	make -C ../../../library/spi_engine/spi_engine_interconnect
 	make -C ../../../library/spi_engine/spi_engine_offload
 	make -C ../../../library/util_axis_resize
-	make -C ../../../library/util_i2c_mixer
 	make -C ../../../library/util_sigma_delta_spi
 
 ####################################################################################
diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile
index 7d982d5dd..0612b089f 100644
--- a/projects/cn0363/zed/Makefile
+++ b/projects/cn0363/zed/Makefile
@@ -9,6 +9,7 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/cn0363_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile
index bcb19e751..5e1f57ca2 100644
--- a/projects/daq1/zc706/Makefile
+++ b/projects/daq1/zc706/Makefile
@@ -18,13 +18,13 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
-M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
+M_DEPS += ../../../library/axi_ad9684/axi_ad9684.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -51,13 +51,13 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9122 clean
-	make -C ../../../library/axi_ad9250 clean
+	make -C ../../../library/axi_ad9684 clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_bsplit clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_upack clean
 
 
 daq1_zc706.sdk/system_top.hdf: $(M_DEPS)
@@ -67,13 +67,13 @@ daq1_zc706.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9122
-	make -C ../../../library/axi_ad9250
+	make -C ../../../library/axi_ad9684
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_bsplit
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_upack
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/daq3/Makefile b/projects/daq3/Makefile
index 5b866a1ac..007fae804 100644
--- a/projects/daq3/Makefile
+++ b/projects/daq3/Makefile
@@ -7,14 +7,20 @@
 
 .PHONY: all clean clean-all 
 all:
+	-make -C a10gx all
+	-make -C kcu105 all
 	-make -C zc706 all
 
 
 clean: 
+	make -C a10gx clean
+	make -C kcu105 clean
 	make -C zc706 clean
 
 
 clean-all:
+	make -C a10gx clean-all
+	make -C kcu105 clean-all
 	make -C zc706 clean-all
 
 ####################################################################################
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index 8821ea258..f5526e19e 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -14,12 +14,11 @@ M_DEPS += ../common/daq3_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144_hw.tcl
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144_if.v
+M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
+M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
+M_DEPS += ../../../library/axi_ad9152/axi_ad9152_core.v
+M_DEPS += ../../../library/axi_ad9152/axi_ad9152_hw.tcl
+M_DEPS += ../../../library/axi_ad9152/axi_ad9152_if.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
index 6c51e2d2d..160a6170e 100644
--- a/projects/daq3/kcu105/Makefile
+++ b/projects/daq3/kcu105/Makefile
@@ -9,8 +9,8 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
-M_DEPS += ../common/daq2_spi.v
-M_DEPS += ../common/daq2_bd.tcl
+M_DEPS += ../common/daq3_spi.v
+M_DEPS += ../common/daq3_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
@@ -19,7 +19,7 @@ M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
+M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -45,7 +45,7 @@ M_FLIST += .Xil
 
 
 .PHONY: all lib clean clean-all
-all: lib daq2_kcu105.sdk/system_top.hdf
+all: lib daq3_kcu105.sdk/system_top.hdf
 
 
 clean: 
@@ -53,7 +53,7 @@ clean:
 
 
 clean-all:clean
-	make -C ../../../library/axi_ad9144 clean
+	make -C ../../../library/axi_ad9152 clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -64,13 +64,13 @@ clean-all:clean
 	make -C ../../../library/util_upack clean
 
 
-daq2_kcu105.sdk/system_top.hdf: $(M_DEPS)
+daq3_kcu105.sdk/system_top.hdf: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> daq2_kcu105_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> daq3_kcu105_vivado.log 2>&1
 
 
 lib:
-	make -C ../../../library/axi_ad9144
+	make -C ../../../library/axi_ad9152
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/pzsdr/Makefile b/projects/pzsdr/Makefile
index f6284afab..924f12685 100644
--- a/projects/pzsdr/Makefile
+++ b/projects/pzsdr/Makefile
@@ -10,18 +10,21 @@ all:
 	-make -C ccbrk all
 	-make -C ccfmc all
 	-make -C ccpci all
+	-make -C ccbrk all
 
 
 clean: 
 	make -C ccbrk clean
 	make -C ccfmc clean
 	make -C ccpci clean
+	make -C ccbrk clean
 
 
 clean-all:
 	make -C ccbrk clean-all
 	make -C ccfmc clean-all
 	make -C ccpci clean-all
+	make -C ccbrk clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile
index f6284afab..fb1938e2f 100644
--- a/projects/pzsdr1/Makefile
+++ b/projects/pzsdr1/Makefile
@@ -8,20 +8,14 @@
 .PHONY: all clean clean-all 
 all:
 	-make -C ccbrk all
-	-make -C ccfmc all
-	-make -C ccpci all
 
 
 clean: 
 	make -C ccbrk clean
-	make -C ccfmc clean
-	make -C ccpci clean
 
 
 clean-all:
 	make -C ccbrk clean-all
-	make -C ccfmc clean-all
-	make -C ccpci clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
index ce0099658..9c23f8e0a 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -15,16 +15,14 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
 M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr1/pzsdr1_system_ps7.tcl
 M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
 M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -56,9 +54,7 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_gpreg clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_gtlb clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -73,9 +69,7 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_gpreg
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_gtlb
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo

From 7d2939be92762e507e57acba003e2580b7b84fde Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 3 Mar 2016 12:56:06 -0500
Subject: [PATCH 092/972] ad9361- cmos mode initial commit

---
 library/axi_ad9361/axi_ad9361_cmos_if.v | 562 ++++++++++++++++++++++++
 library/common/ad_cmos_clk.v            |  79 ++++
 library/common/ad_cmos_in.v             | 196 +++++++++
 library/common/ad_cmos_out.v            | 164 +++++++
 4 files changed, 1001 insertions(+)
 create mode 100644 library/axi_ad9361/axi_ad9361_cmos_if.v
 create mode 100644 library/common/ad_cmos_clk.v
 create mode 100644 library/common/ad_cmos_in.v
 create mode 100644 library/common/ad_cmos_out.v

diff --git a/library/axi_ad9361/axi_ad9361_cmos_if.v b/library/axi_ad9361/axi_ad9361_cmos_if.v
new file mode 100644
index 000000000..609dcc226
--- /dev/null
+++ b/library/axi_ad9361/axi_ad9361_cmos_if.v
@@ -0,0 +1,562 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9361_cmos_if (
+
+  // physical interface (receive)
+
+  rx_clk_in,
+  rx_frame_in,
+  rx_data_in,
+
+  // physical interface (transmit)
+
+  tx_clk_out,
+  tx_frame_out,
+  tx_data_out,
+
+  // ensm control
+
+  enable,
+  txnrx,
+
+  // clock (common to both receive and transmit)
+
+  rst,
+  clk,
+  l_clk,
+
+  // receive data path interface
+
+  adc_valid,
+  adc_data,
+  adc_status,
+  adc_r1_mode,
+  adc_ddr_edgesel,
+
+  // transmit data path interface
+
+  dac_valid,
+  dac_data,
+  dac_r1_mode,
+
+  // tdd interface
+
+  tdd_enable,
+  tdd_txnrx,
+  tdd_mode,
+
+  // delay interface
+
+  up_clk,
+  up_enable,
+  up_txnrx,
+  up_adc_dld,
+  up_adc_dwdata,
+  up_adc_drdata,
+  up_dac_dld,
+  up_dac_dwdata,
+  up_dac_drdata,
+  delay_clk,
+  delay_rst,
+  delay_locked);
+
+  // this parameter controls the buffer type based on the target device.
+
+  parameter   DEVICE_TYPE = 0;
+  parameter   DAC_IODELAY_ENABLE = 0;
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group";
+
+  // physical interface (receive)
+
+  input           rx_clk_in;
+  input           rx_frame_in;
+  input   [11:0]  rx_data_in;
+
+  // physical interface (transmit)
+
+  output          tx_clk_out;
+  output          tx_frame_out;
+  output  [11:0]  tx_data_out;
+
+  // ensm control
+
+  output          enable;
+  output          txnrx;
+
+  // clock (common to both receive and transmit)
+
+  input           rst;
+  input           clk;
+  output          l_clk;
+
+  // receive data path interface
+
+  output          adc_valid;
+  output  [47:0]  adc_data;
+  output          adc_status;
+  input           adc_r1_mode;
+  input           adc_ddr_edgesel;
+
+  // transmit data path interface
+
+  input           dac_valid;
+  input   [47:0]  dac_data;
+  input           dac_r1_mode;
+
+  // tdd interface
+
+  input           tdd_enable;
+  input           tdd_txnrx;
+  input           tdd_mode;
+
+  // delay interface
+
+  input           up_clk;
+  input           up_enable;
+  input           up_txnrx;
+  input   [12:0]  up_adc_dld;
+  input   [64:0]  up_adc_dwdata;
+  output  [64:0]  up_adc_drdata;
+  input   [15:0]  up_dac_dld;
+  input   [79:0]  up_dac_dwdata;
+  output  [79:0]  up_dac_drdata;
+  input           delay_clk;
+  input           delay_rst;
+  output          delay_locked;
+
+  // internal registers
+
+  reg     [ 1:0]  rx_frame = 0;
+  reg     [11:0]  rx_data_p = 0;
+  reg             rx_error_r1 = 'd0;
+  reg             rx_valid_r1 = 'd0;
+  reg     [23:0]  rx_data_r1 = 'd0;
+  reg             rx_error_r2 = 'd0;
+  reg             rx_valid_r2 = 'd0;
+  reg     [47:0]  rx_data_r2 = 'd0;
+  reg             adc_p_valid = 'd0;
+  reg     [47:0]  adc_p_data = 'd0;
+  reg             adc_p_status = 'd0;
+  reg             adc_n_valid = 'd0;
+  reg     [47:0]  adc_n_data = 'd0;
+  reg             adc_n_status = 'd0;
+  reg             adc_valid_int = 'd0;
+  reg     [47:0]  adc_data_int = 'd0;
+  reg             adc_status_int = 'd0;
+  reg             adc_valid = 'd0;
+  reg     [47:0]  adc_data = 'd0;
+  reg             adc_status = 'd0;
+  reg     [ 1:0]  tx_data_cnt = 'd0;
+  reg     [47:0]  tx_data = 'd0;
+  reg             tx_frame_p = 'd0;
+  reg             tx_frame_n = 'd0;
+  reg     [11:0]  tx_data_p = 'd0;
+  reg     [11:0]  tx_data_n = 'd0;
+  reg             tx_n_frame_p = 'd0;
+  reg             tx_n_frame_n = 'd0;
+  reg     [11:0]  tx_n_data_p = 'd0;
+  reg     [11:0]  tx_n_data_n = 'd0;
+  reg             tx_p_frame_p = 'd0;
+  reg             tx_p_frame_n = 'd0;
+  reg     [11:0]  tx_p_data_p = 'd0;
+  reg     [11:0]  tx_p_data_n = 'd0;
+  reg             up_enable_int = 'd0;
+  reg             up_txnrx_int = 'd0;
+  reg             enable_up_m1 = 'd0;
+  reg             txnrx_up_m1 = 'd0;
+  reg             enable_up = 'd0;
+  reg             txnrx_up = 'd0;
+  reg             enable_int = 'd0;
+  reg             txnrx_int = 'd0;
+  reg             enable_n_int = 'd0;
+  reg             txnrx_n_int = 'd0;
+  reg             enable_p_int = 'd0;
+  reg             txnrx_p_int = 'd0;
+
+  // internal signals
+
+  wire    [ 1:0]  rx_frame_s;
+  wire    [ 3:0]  rx_frame_4_s;
+  wire    [ 2:0]  tx_data_sel_s;
+  wire    [11:0]  rx_data_p_s;
+  wire    [11:0]  rx_data_n_s;
+  wire            rx_frame_p_s;
+  wire            rx_frame_n_s;
+
+  genvar          l_inst;
+
+  // receive data path interface
+
+  assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s};
+  assign rx_frame_4_s = {rx_frame_s, rx_frame};
+
+  always @(posedge l_clk) begin
+    rx_frame <= rx_frame_s;
+    rx_data_p <= rx_data_p_s;
+  end
+
+  // receive data path for single rf, frame is expected to qualify i only
+
+  always @(posedge l_clk) begin
+    rx_error_r1 <= ~^ rx_frame_s;
+    rx_valid_r1 <= ^ rx_frame_s;
+    case (rx_frame_s)
+      2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s};
+      2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p};
+      default: rx_data_r1 <= 24'd0;
+    endcase
+  end
+
+  // receive data path for dual rf, frame is expected to qualify iq for rf-1 only
+
+  always @(posedge l_clk) begin
+    rx_error_r2 <= ((rx_frame_4_s == 4'b0011) ||
+      (rx_frame_4_s == 4'b1001)) ? 1'b0 : 1'b1;
+    rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) ||
+      (rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0;
+    case (rx_frame_s)
+      2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s};
+      2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p};
+      default: rx_data_r2[23: 0] <= rx_data_r2[23: 0];
+    endcase
+    case (rx_frame_s)
+      2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s};
+      2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p};
+      default: rx_data_r2[47:24] <= rx_data_r2[47:24];
+    endcase
+  end
+
+  // receive data path mux
+
+  always @(posedge l_clk) begin
+    if (adc_r1_mode == 1'b1) begin
+      adc_p_valid <= rx_valid_r1;
+      adc_p_data <= {24'd0, rx_data_r1};
+      adc_p_status <= ~rx_error_r1;
+    end else begin
+      adc_p_valid <= rx_valid_r2;
+      adc_p_data <= rx_data_r2;
+      adc_p_status <= ~rx_error_r2;
+    end
+  end
+
+  // transfer to a synchronous common clock
+
+  always @(negedge l_clk) begin
+    adc_n_valid <= adc_p_valid;
+    adc_n_data <= adc_p_data;
+    adc_n_status <= adc_p_status;
+  end
+
+  always @(posedge clk) begin
+    adc_valid_int <= adc_n_valid;
+    adc_data_int <= adc_n_data;
+    adc_status_int <= adc_n_status;
+    adc_valid <= adc_valid_int;
+    if (adc_valid_int == 1'b1) begin
+      adc_data <= adc_data_int;
+    end
+    adc_status <= adc_status_int;
+  end
+
+  // transmit data path mux (reverse of what receive does above)
+  // the count simply selets the data muxing on the ddr outputs
+
+  assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]};
+
+  always @(posedge clk) begin
+    if (dac_valid == 1'b1) begin
+      tx_data_cnt <= 2'b10;
+    end else if (tx_data_cnt[1] == 1'b1) begin
+      tx_data_cnt <= tx_data_cnt + 1'b1;
+    end
+    if (dac_valid == 1'b1) begin
+      tx_data <= dac_data;
+    end
+    case (tx_data_sel_s)
+      3'b100: begin
+        tx_frame_p <= 1'b0;
+        tx_frame_n <= 1'b0;
+        tx_data_p <= tx_data[35:24];
+        tx_data_n <= tx_data[47:36];
+      end
+      3'b101: begin
+        tx_frame_p <= 1'b1;
+        tx_frame_n <= 1'b1;
+        tx_data_p <= tx_data[11: 0];
+        tx_data_n <= tx_data[23:12];
+      end
+      3'b110: begin
+        tx_frame_p <= 1'b1;
+        tx_frame_n <= 1'b0;
+        tx_data_p <= tx_data[11: 0];
+        tx_data_n <= tx_data[23:12];
+      end
+      default: begin
+        tx_frame_p <= 1'd0;
+        tx_frame_n <= 1'd0;
+        tx_data_p <= 12'd0;
+        tx_data_n <= 12'd0;
+      end
+    endcase
+  end
+
+  // transfer data from a synchronous clock (skew less than 2ns)
+
+  always @(negedge clk) begin
+    tx_n_frame_p <= tx_frame_p;
+    tx_n_frame_n <= tx_frame_n;
+    tx_n_data_p <= tx_data_p;
+    tx_n_data_n <= tx_data_n;
+  end
+
+  always @(posedge l_clk) begin
+    tx_p_frame_p <= tx_n_frame_p;
+    tx_p_frame_n <= tx_n_frame_n;
+    tx_p_data_p <= tx_n_data_p;
+    tx_p_data_n <= tx_n_data_n;
+  end
+
+  // tdd/ensm control
+
+  always @(posedge up_clk) begin
+    up_enable_int <= up_enable;
+    up_txnrx_int <= up_txnrx;
+  end
+
+  always @(posedge clk or posedge rst) begin
+    if (rst == 1'b1) begin
+      enable_up_m1 <= 1'b0;
+      txnrx_up_m1 <= 1'b0;
+      enable_up <= 1'b0;
+      txnrx_up <= 1'b0;
+    end else begin
+      enable_up_m1 <= up_enable_int;
+      txnrx_up_m1 <= up_txnrx_int;
+      enable_up <= enable_up_m1;
+      txnrx_up <= txnrx_up_m1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (tdd_mode == 1'b1) begin
+      enable_int <= tdd_enable;
+      txnrx_int <= tdd_txnrx;
+    end else begin
+      enable_int <= enable_up;
+      txnrx_int <= txnrx_up;
+    end
+  end
+
+  always @(negedge clk) begin
+    enable_n_int <= enable_int;
+    txnrx_n_int <= txnrx_int;
+  end
+
+  always @(posedge l_clk) begin
+    enable_p_int <= enable_n_int;
+    txnrx_p_int <= txnrx_n_int;
+  end
+
+  // receive data interface, ibuf -> idelay -> iddr
+
+  generate
+  for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
+  ad_cmos_in #(
+    .SINGLE_ENDED (1),
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_rx_data (
+    .rx_clk (l_clk),
+    .rx_data_in (rx_data_in[l_inst]),
+    .rx_data_p (rx_data_p_s[l_inst]),
+    .rx_data_n (rx_data_n_s[l_inst]),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[l_inst]),
+    .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+  end
+  endgenerate
+
+  // receive frame interface, ibuf -> idelay -> iddr
+
+  ad_cmos_in #(
+    .SINGLE_ENDED (1),
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .IODELAY_CTRL (1),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_rx_frame (
+    .rx_clk (l_clk),
+    .rx_data_in_p (rx_frame_in),
+    .rx_data_p (rx_frame_p_s),
+    .rx_data_n (rx_frame_n_s),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[12]),
+    .up_dwdata (up_adc_dwdata[64:60]),
+    .up_drdata (up_adc_drdata[64:60]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked));
+
+  // transmit data interface, oddr -> obuf
+
+  generate
+  for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_data (
+    .tx_clk (l_clk),
+    .tx_data_p (tx_p_data_p[l_inst]),
+    .tx_data_n (tx_p_data_n[l_inst]),
+    .tx_data_out (tx_data_out[l_inst]),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[l_inst]),
+    .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+  end
+  endgenerate
+
+  // transmit frame interface, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_frame (
+    .tx_clk (l_clk),
+    .tx_data_p (tx_p_frame_p),
+    .tx_data_n (tx_p_frame_n),
+    .tx_data_out (tx_frame_out),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[12]),
+    .up_dwdata (up_dac_dwdata[64:60]),
+    .up_drdata (up_dac_drdata[64:60]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // transmit clock interface, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_clk (
+    .tx_clk (l_clk),
+    .tx_data_p (1'b0),
+    .tx_data_n (1'b1),
+    .tx_data_out (tx_clk_out),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[13]),
+    .up_dwdata (up_dac_dwdata[69:65]),
+    .up_drdata (up_dac_drdata[69:65]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // enable, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_enable (
+    .tx_clk (l_clk),
+    .tx_data_p (enable_p_int),
+    .tx_data_n (enable_p_int),
+    .tx_data_out (enable),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[14]),
+    .up_dwdata (up_dac_dwdata[74:70]),
+    .up_drdata (up_dac_drdata[74:70]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // txnrx, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_txnrx (
+    .tx_clk (l_clk),
+    .tx_data_p (txnrx_p_int),
+    .tx_data_n (txnrx_p_int),
+    .tx_data_out (txnrx),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[15]),
+    .up_dwdata (up_dac_dwdata[79:75]),
+    .up_drdata (up_dac_drdata[79:75]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // device clock interface (receive clock)
+
+  ad_cmos_clk #(
+    .DEVICE_TYPE (DEVICE_TYPE))
+  i_clk (
+    .clk_in (rx_clk_in),
+    .clk (l_clk));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/common/ad_cmos_clk.v b/library/common/ad_cmos_clk.v
new file mode 100644
index 000000000..f5a344f65
--- /dev/null
+++ b/library/common/ad_cmos_clk.v
@@ -0,0 +1,79 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_cmos_clk (
+
+  clk_in,
+  clk);
+
+  parameter   DEVICE_TYPE   = 0;
+  localparam  SERIES7       = 0;
+  localparam  VIRTEX6       = 1;
+
+  input     clk_in;
+  output    clk;
+
+  // wires
+
+  wire      clk_ibuf_s;
+
+  // instantiations
+
+  IBUFG i_rx_clk_ibuf (
+    .I (clk_in),
+    .O (clk_ibuf_s));
+
+  generate
+  if (DEVICE_TYPE == VIRTEX6) begin
+  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
+    .CLR (1'b0),
+    .CE (1'b1),
+    .I (clk_ibuf_s),
+    .O (clk));
+  end else begin
+  BUFG i_clk_gbuf (
+    .I (clk_ibuf_s),
+    .O (clk));
+  end
+  endgenerate
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/common/ad_cmos_in.v b/library/common/ad_cmos_in.v
new file mode 100644
index 000000000..cf2081778
--- /dev/null
+++ b/library/common/ad_cmos_in.v
@@ -0,0 +1,196 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_cmos_in (
+
+  // data interface
+
+  rx_clk,
+  rx_data_in,
+  rx_data_p,
+  rx_data_n,
+
+  // delay-data interface
+
+  up_clk,
+  up_dld,
+  up_dwdata,
+  up_drdata,
+
+  // delay-cntrl interface
+
+  delay_clk,
+  delay_rst,
+  delay_locked);
+
+  // parameters
+
+  parameter   SINGLE_ENDED = 0;
+  parameter   DEVICE_TYPE = 0;
+  parameter   IODELAY_CTRL = 0;
+  parameter   IODELAY_GROUP = "dev_if_delay_group";
+  localparam  SERIES7 = 0;
+  localparam  VIRTEX6 = 1;
+
+  // data interface
+
+  input               rx_clk;
+  input               rx_data_in;
+  output              rx_data_p;
+  output              rx_data_n;
+
+  // delay-data interface
+
+  input               up_clk;
+  input               up_dld;
+  input       [ 4:0]  up_dwdata;
+  output      [ 4:0]  up_drdata;
+
+  // delay-cntrl interface
+
+  input               delay_clk;
+  input               delay_rst;
+  output              delay_locked;
+
+  // internal registers
+
+  reg                 rx_data_n;
+
+  // internal signals
+
+  wire                rx_data_n_s;
+  wire                rx_data_ibuf_s;
+  wire                rx_data_idelay_s;
+
+  // delay controller
+
+  generate
+  if (IODELAY_CTRL == 1) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYCTRL i_delay_ctrl (
+    .RST (delay_rst),
+    .REFCLK (delay_clk),
+    .RDY (delay_locked));
+  end else begin
+  assign delay_locked = 1'b1;
+  end
+  endgenerate
+
+  // receive data interface, ibuf -> idelay -> iddr
+
+  IBUF i_rx_data_ibuf (
+    .I (rx_data_in),
+    .O (rx_data_ibuf_s));
+
+  generate
+  if (DEVICE_TYPE == VIRTEX6) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IODELAYE1 #(
+    .CINVCTRL_SEL ("FALSE"),
+    .DELAY_SRC ("I"),
+    .HIGH_PERFORMANCE_MODE ("TRUE"),
+    .IDELAY_TYPE ("VAR_LOADABLE"),
+    .IDELAY_VALUE (0),
+    .ODELAY_TYPE ("FIXED"),
+    .ODELAY_VALUE (0),
+    .REFCLK_FREQUENCY (200.0),
+    .SIGNAL_PATTERN ("DATA"))
+  i_rx_data_idelay (
+    .T (1'b1),
+    .CE (1'b0),
+    .INC (1'b0),
+    .CLKIN (1'b0),
+    .DATAIN (1'b0),
+    .ODATAIN (1'b0),
+    .CINVCTRL (1'b0),
+    .C (up_clk),
+    .IDATAIN (rx_data_ibuf_s),
+    .DATAOUT (rx_data_idelay_s),
+    .RST (up_dld),
+    .CNTVALUEIN (up_dwdata),
+    .CNTVALUEOUT (up_drdata));
+  end else begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYE2 #(
+    .CINVCTRL_SEL ("FALSE"),
+    .DELAY_SRC ("IDATAIN"),
+    .HIGH_PERFORMANCE_MODE ("FALSE"),
+    .IDELAY_TYPE ("VAR_LOAD"),
+    .IDELAY_VALUE (0),
+    .REFCLK_FREQUENCY (200.0),
+    .PIPE_SEL ("FALSE"),
+    .SIGNAL_PATTERN ("DATA"))
+  i_rx_data_idelay (
+    .CE (1'b0),
+    .INC (1'b0),
+    .DATAIN (1'b0),
+    .LDPIPEEN (1'b0),
+    .CINVCTRL (1'b0),
+    .REGRST (1'b0),
+    .C (up_clk),
+    .IDATAIN (rx_data_ibuf_s),
+    .DATAOUT (rx_data_idelay_s),
+    .LD (up_dld),
+    .CNTVALUEIN (up_dwdata),
+    .CNTVALUEOUT (up_drdata));
+  end
+  endgenerate
+
+  IDDR #(
+    .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
+    .INIT_Q1 (1'b0),
+    .INIT_Q2 (1'b0),
+    .SRTYPE ("ASYNC"))
+  i_rx_data_iddr (
+    .CE (1'b1),
+    .R (1'b0),
+    .S (1'b0),
+    .C (rx_clk),
+    .D (rx_data_idelay_s),
+    .Q1 (rx_data_p),
+    .Q2 (rx_data_n_s));
+
+  always @(posedge rx_clk) begin
+    rx_data_n <= rx_data_n_s;
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/common/ad_cmos_out.v b/library/common/ad_cmos_out.v
new file mode 100644
index 000000000..9537d6dd1
--- /dev/null
+++ b/library/common/ad_cmos_out.v
@@ -0,0 +1,164 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_cmos_out (
+
+  // data interface
+
+  tx_clk,
+  tx_data_p,
+  tx_data_n,
+  tx_data_out,
+
+  // delay-data interface
+
+  up_clk,
+  up_dld,
+  up_dwdata,
+  up_drdata,
+
+  // delay-cntrl interface
+
+  delay_clk,
+  delay_rst,
+  delay_locked);
+
+  // parameters
+
+  parameter   DEVICE_TYPE = 0;
+  parameter   SINGLE_ENDED = 0;
+  parameter   IODELAY_ENABLE = 0;
+  parameter   IODELAY_CTRL = 0;
+  parameter   IODELAY_GROUP = "dev_if_delay_group";
+  localparam  SERIES7 = 0;
+  localparam  VIRTEX6 = 1;
+
+  // data interface
+
+  input               tx_clk;
+  input               tx_data_p;
+  input               tx_data_n;
+  output              tx_data_out;
+
+  // delay-data interface
+
+  input               up_clk;
+  input               up_dld;
+  input       [ 4:0]  up_dwdata;
+  output      [ 4:0]  up_drdata;
+
+  // delay-cntrl interface
+
+  input               delay_clk;
+  input               delay_rst;
+  output              delay_locked;
+
+  // internal signals
+
+  wire                tx_data_oddr_s;
+  wire                tx_data_odelay_s;
+
+  // delay controller
+
+  generate
+  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYCTRL i_delay_ctrl (
+    .RST (delay_rst),
+    .REFCLK (delay_clk),
+    .RDY (delay_locked));
+  end else begin
+  assign delay_locked = 1'b1;
+  end
+  endgenerate
+
+  // transmit data interface, oddr -> odelay -> obuf
+
+  ODDR #(
+    .DDR_CLK_EDGE ("SAME_EDGE"),
+    .INIT (1'b0),
+    .SRTYPE ("ASYNC"))
+  i_tx_data_oddr (
+    .CE (1'b1),
+    .R (1'b0),
+    .S (1'b0),
+    .C (tx_clk),
+    .D1 (tx_data_p),
+    .D2 (tx_data_n),
+    .Q (tx_data_oddr_s));
+
+  generate
+  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  ODELAYE2 #(
+    .CINVCTRL_SEL ("FALSE"),
+    .DELAY_SRC ("ODATAIN"),
+    .HIGH_PERFORMANCE_MODE ("FALSE"),
+    .ODELAY_TYPE ("VAR_LOAD"),
+    .ODELAY_VALUE (0),
+    .REFCLK_FREQUENCY (200.0),
+    .PIPE_SEL ("FALSE"),
+    .SIGNAL_PATTERN ("DATA"))
+  i_tx_data_odelay (
+    .CE (1'b0),
+    .CLKIN (1'b0),
+    .INC (1'b0),
+    .LDPIPEEN (1'b0),
+    .CINVCTRL (1'b0),
+    .REGRST (1'b0),
+    .C (up_clk),
+    .ODATAIN (tx_data_oddr_s),
+    .DATAOUT (tx_data_odelay_s),
+    .LD (up_dld),
+    .CNTVALUEIN (up_dwdata),
+    .CNTVALUEOUT (up_drdata));
+  end else begin
+  assign up_drdata = 5'd0;
+  assign tx_data_odelay_s = tx_data_oddr_s;
+  end
+  endgenerate
+
+  OBUF i_tx_data_obuf (
+    .I (tx_data_odelay_s),
+    .O (tx_data_out));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From a2374f64bf2998d691d173a0d178e3fef67a20ed Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Mar 2016 10:34:58 -0500
Subject: [PATCH 093/972] pzsdr- cmos/lvds split

---
 .../common/pzsdr/pzsdr_cmos_system_constr.xdc | 42 +++++++++++++++++++
 .../common/pzsdr/pzsdr_lvds_system_constr.xdc | 42 +++++++++++++++++++
 2 files changed, 84 insertions(+)
 create mode 100644 projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
 create mode 100644 projects/common/pzsdr/pzsdr_lvds_system_constr.xdc

diff --git a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
new file mode 100644
index 000000000..2d7cd3ebe
--- /dev/null
+++ b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
@@ -0,0 +1,42 @@
+
+# constraints
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports rx_clk_in]       ; ## IO_L12P_T1_MRCC_35
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18} [get_ports rx_frame_in]     ; ## IO_L7P_T1_AD2P_35
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]   ; ## IO_L1N_T0_AD0N_35
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]   ; ## IO_L1P_T0_AD0P_35
+set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]   ; ## IO_L2N_T0_AD8N_35
+set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]   ; ## IO_L2P_T0_AD8P_35
+set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]   ; ## IO_L3N_T0_DQS_AD1N_35
+set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]   ; ## IO_L3P_T0_DQS_AD1P_35
+set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]   ; ## IO_L4N_T0_35
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]   ; ## IO_L4P_T0_35
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]   ; ## IO_L5N_T0_AD9N_35
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]   ; ## IO_L5P_T0_AD9P_35
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]  ; ## IO_L6N_T0_VREF_35
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]  ; ## IO_L6P_T0_35
+
+set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]      ; ## IO_L8P_T1_AD10P_35
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]    ; ## IO_L9P_T1_DQS_AD3P_35
+set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]  ; ## IO_L13N_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]  ; ## IO_L13P_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]  ; ## IO_L14N_T2_AD4N_SRCC_35
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]  ; ## IO_L14P_T2_AD4P_SRCC_35
+set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]  ; ## IO_L15N_T2_DQS_AD12N_35
+set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]  ; ## IO_L15P_T2_DQS_AD12P_35
+set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]  ; ## IO_L16N_T2_35
+set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]  ; ## IO_L16P_T2_35
+set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]  ; ## IO_L17N_T2_AD5N_35
+set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]  ; ## IO_L17P_T2_AD5P_35
+set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L18N_T2_AD13N_35
+set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L18P_T2_AD13P_35
+
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]]       ; ## IO_L8N_T1_AD10N_35
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]]       ; ## IO_L9N_T1_DQS_AD3N_35
+
+# clocks
+
+create_clock -name rx_clk       -period  8 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+
diff --git a/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc b/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc
new file mode 100644
index 000000000..0d471c6c8
--- /dev/null
+++ b/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc
@@ -0,0 +1,42 @@
+
+# constraints
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35
+set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35
+set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35
+set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35
+set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35
+set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35
+set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35
+set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35
+set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVDS}     [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVDS}     [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVDS}     [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVDS}     [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35
+set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVDS}     [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35
+set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35
+set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35
+set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35
+set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35
+set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35
+set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35
+set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35
+set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35
+set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVDS}     [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35
+
+# clocks
+
+create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+

From 18f30c8dc8e8f0d7cac79e8931bf9213659d423d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Mar 2016 10:35:43 -0500
Subject: [PATCH 094/972] pzsdr- cmos/lvds split

---
 projects/common/pzsdr/pzsdr_system_constr.xdc | 37 -------------------
 1 file changed, 37 deletions(-)

diff --git a/projects/common/pzsdr/pzsdr_system_constr.xdc b/projects/common/pzsdr/pzsdr_system_constr.xdc
index ef43a4869..05e510ba8 100644
--- a/projects/common/pzsdr/pzsdr_system_constr.xdc
+++ b/projects/common/pzsdr/pzsdr_system_constr.xdc
@@ -2,38 +2,6 @@
 # constraints
 # ad9361
 
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35
-set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35
-set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35
-set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35
-set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35
-set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35
-set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35
-set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35
-set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35
-set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35
-set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35
-set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35
-set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35
-set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35
-set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVDS}     [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35
-set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVDS}     [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35
-set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVDS}     [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVDS}     [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35
-set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVDS}     [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35
-set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35
-set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35
-set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35
-set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35
-set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35
-set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35
-set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35
-set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35
-set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVDS}     [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35
 set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35
 set_property  -dict {PACKAGE_PIN  F14  IOSTANDARD LVCMOS18} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35
 
@@ -81,8 +49,3 @@ set_property  -dict {PACKAGE_PIN  W16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[9
 set_property  -dict {PACKAGE_PIN  W15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]]                       ; ## (dip) IO_L24N_T3_12            
 set_property  -dict {PACKAGE_PIN  V19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]                       ; ## (dip) IO_0_13                  
 
-# clocks
-
-create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
-create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
-

From 3466f21f8e63ec7b997e9c4dbc4a08b6cda341d5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Mar 2016 10:36:15 -0500
Subject: [PATCH 095/972] pzsdr add cmos/lvds support

---
 projects/pzsdr/ccbrk/system_project.tcl | 3 ++-
 projects/pzsdr/ccfmc/system_project.tcl | 3 ++-
 projects/pzsdr/ccpci/system_project.tcl | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/projects/pzsdr/ccbrk/system_project.tcl b/projects/pzsdr/ccbrk/system_project.tcl
index 3d182ce37..bcfeb1f4a 100644
--- a/projects/pzsdr/ccbrk/system_project.tcl
+++ b/projects/pzsdr/ccbrk/system_project.tcl
@@ -10,7 +10,8 @@ adi_project_files ccbrk_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
diff --git a/projects/pzsdr/ccfmc/system_project.tcl b/projects/pzsdr/ccfmc/system_project.tcl
index 06d99afc3..5b6abc180 100644
--- a/projects/pzsdr/ccfmc/system_project.tcl
+++ b/projects/pzsdr/ccfmc/system_project.tcl
@@ -10,7 +10,8 @@ adi_project_files ccfmc_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
diff --git a/projects/pzsdr/ccpci/system_project.tcl b/projects/pzsdr/ccpci/system_project.tcl
index e09c5a1d0..10d4a8281 100644
--- a/projects/pzsdr/ccpci/system_project.tcl
+++ b/projects/pzsdr/ccpci/system_project.tcl
@@ -10,7 +10,8 @@ adi_project_files ccpci_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
 set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]

From 7a320a3d3426bde670db4e006f7ad7bcf58e5272 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Mar 2016 10:38:11 -0500
Subject: [PATCH 096/972] ad_lvds* - updates

---
 library/common/ad_lvds_clk.v | 2 +-
 library/common/ad_lvds_in.v  | 9 ++++-----
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/library/common/ad_lvds_clk.v b/library/common/ad_lvds_clk.v
index e65ea434f..5bcb66241 100644
--- a/library/common/ad_lvds_clk.v
+++ b/library/common/ad_lvds_clk.v
@@ -45,7 +45,7 @@ module ad_lvds_clk (
   clk_in_n,
   clk);
 
-  parameter   DEVICE_TYPE       = 0;
+  parameter   DEVICE_TYPE   = 0;
   localparam  SERIES7       = 0;
   localparam  VIRTEX6       = 1;
 
diff --git a/library/common/ad_lvds_in.v b/library/common/ad_lvds_in.v
index 9e977b193..4d53c3e0c 100644
--- a/library/common/ad_lvds_in.v
+++ b/library/common/ad_lvds_in.v
@@ -120,12 +120,11 @@ module ad_lvds_in (
 
   generate
   if (SINGLE_ENDED == 1) begin
-    assign tx_data_out_n = 1'b0;
-    IBUF i_rx_data_ibuf (
-      .I (rx_data_in_p),
-      .O (rx_data_ibuf_s));
+  IBUF i_rx_data_ibuf (
+    .I (rx_data_in_p),
+    .O (rx_data_ibuf_s));
   end else begin
-     IBUFDS i_rx_data_ibuf (
+  IBUFDS i_rx_data_ibuf (
     .I (rx_data_in_p),
     .IB (rx_data_in_n),
     .O (rx_data_ibuf_s));

From 583ef82fd0c3432722a325bf9e9b6458587e5dfd Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Mar 2016 10:38:58 -0500
Subject: [PATCH 097/972] ad9361- cmos mode

---
 library/axi_ad9361/axi_ad9361.v         | 124 ++++++++++++++++++++----
 library/axi_ad9361/axi_ad9361_cmos_if.v |  14 +--
 library/axi_ad9361/axi_ad9361_ip.tcl    |  29 ++++++
 library/axi_ad9361/axi_ad9361_rx.v      |  10 +-
 library/axi_ad9361/axi_ad9361_tx.v      |   8 +-
 5 files changed, 149 insertions(+), 36 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index bc96169d7..9d2365831 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -39,7 +39,7 @@
 
 module axi_ad9361 (
 
-  // physical interface (receive)
+  // physical interface (receive-lvds)
 
   rx_clk_in_p,
   rx_clk_in_n,
@@ -48,7 +48,13 @@ module axi_ad9361 (
   rx_data_in_p,
   rx_data_in_n,
 
-  // physical interface (transmit)
+  // physical interface (receive-cmos)
+
+  rx_clk_in,
+  rx_frame_in,
+  rx_data_in,
+
+  // physical interface (transmit-lvds)
 
   tx_clk_out_p,
   tx_clk_out_n,
@@ -57,6 +63,12 @@ module axi_ad9361 (
   tx_data_out_p,
   tx_data_out_n,
 
+  // physical interface (transmit-cmos)
+
+  tx_clk_out,
+  tx_frame_out,
+  tx_data_out,
+
   // ensm control
 
   enable,
@@ -157,12 +169,13 @@ module axi_ad9361 (
 
   parameter   ID = 0;
   parameter   DEVICE_TYPE = 0;
+  parameter   CMOS_OR_LVDS_N = 0;
   parameter   DAC_IODELAY_ENABLE = 0;
   parameter   IO_DELAY_GROUP = "dev_if_delay_group";
   parameter   DAC_DATAPATH_DISABLE = 0;
   parameter   ADC_DATAPATH_DISABLE = 0;
 
-  // physical interface (receive)
+  // physical interface (receive-lvds)
 
   input           rx_clk_in_p;
   input           rx_clk_in_n;
@@ -171,7 +184,13 @@ module axi_ad9361 (
   input   [ 5:0]  rx_data_in_p;
   input   [ 5:0]  rx_data_in_n;
 
-  // physical interface (transmit)
+  // physical interface (receive-cmos)
+
+  input           rx_clk_in;
+  input           rx_frame_in;
+  input   [11:0]  rx_data_in;
+
+  // physical interface (transmit-lvds)
 
   output          tx_clk_out_p;
   output          tx_clk_out_n;
@@ -180,6 +199,12 @@ module axi_ad9361 (
   output  [ 5:0]  tx_data_out_p;
   output  [ 5:0]  tx_data_out_n;
 
+  // physical interface (transmit-cmos)
+
+  output          tx_clk_out;
+  output          tx_frame_out;
+  output  [11:0]  tx_data_out;
+
   // ensm control
 
   output          enable;
@@ -281,13 +306,11 @@ module axi_ad9361 (
   reg             up_wack = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
-
   reg     [15:0]  adc_data_i0 = 16'b0;
   reg     [15:0]  adc_data_q0 = 16'b0;
   reg     [15:0]  adc_data_i1 = 16'b0;
   reg     [15:0]  adc_data_q1 = 16'b0;
 
-
   // internal clocks and resets
 
   wire            up_clk;
@@ -307,12 +330,12 @@ module axi_ad9361 (
   wire            dac_valid_q0_s;
   wire            dac_valid_i1_s;
   wire            dac_valid_q1_s;
-  wire    [ 6:0]  up_adc_dld_s;
-  wire    [34:0]  up_adc_dwdata_s;
-  wire    [34:0]  up_adc_drdata_s;
-  wire    [ 9:0]  up_dac_dld_s;
-  wire    [49:0]  up_dac_dwdata_s;
-  wire    [49:0]  up_dac_drdata_s;
+  wire    [12:0]  up_adc_dld_s;
+  wire    [64:0]  up_adc_dwdata_s;
+  wire    [64:0]  up_adc_drdata_s;
+  wire    [15:0]  up_dac_dld_s;
+  wire    [79:0]  up_dac_dwdata_s;
+  wire    [79:0]  up_dac_drdata_s;
   wire            delay_locked_s;
   wire            up_wreq_s;
   wire    [13:0]  up_waddr_s;
@@ -337,7 +360,6 @@ module axi_ad9361 (
   wire            tdd_enable_s;
   wire            tdd_txnrx_s;
   wire            tdd_mode_s;
-
   wire    [15:0]  adc_data_i0_s;
   wire    [15:0]  adc_data_q0_s;
   wire    [15:0]  adc_data_i1_s;
@@ -364,6 +386,67 @@ module axi_ad9361 (
 
   // device interface
 
+  generate
+  if (CMOS_OR_LVDS_N == 1) begin
+
+  assign tx_clk_out_p = 1'd0;
+  assign tx_clk_out_n = 1'd1;
+  assign tx_frame_out_p = 1'd0;
+  assign tx_frame_out_n = 1'd0;
+  assign tx_data_out_p = 6'h00;
+  assign tx_data_out_n = 6'h3f;
+
+  axi_ad9361_cmos_if #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IO_DELAY_GROUP (IO_DELAY_GROUP))
+  i_dev_if (
+    .rx_clk_in (rx_clk_in),
+    .rx_frame_in (rx_frame_in),
+    .rx_data_in (rx_data_in),
+    .tx_clk_out (tx_clk_out),
+    .tx_frame_out (tx_frame_out),
+    .tx_data_out (tx_data_out),
+    .enable (enable),
+    .txnrx (txnrx),
+    .rst (rst),
+    .clk (clk),
+    .l_clk (l_clk),
+    .adc_valid (adc_valid_s),
+    .adc_data (adc_data_s),
+    .adc_status (adc_status_s),
+    .adc_r1_mode (adc_r1_mode),
+    .adc_ddr_edgesel (adc_ddr_edgesel),
+    .dac_valid (g_dac_valid_s),
+    .dac_data (dac_data_s),
+    .dac_r1_mode (dac_r1_mode),
+    .tdd_enable (tdd_enable_s),
+    .tdd_txnrx (tdd_txnrx_s),
+    .tdd_mode (tdd_mode_s),
+    .up_clk (up_clk),
+    .up_enable (up_enable),
+    .up_txnrx (up_txnrx),
+    .up_adc_dld (up_adc_dld_s),
+    .up_adc_dwdata (up_adc_dwdata_s),
+    .up_adc_drdata (up_adc_drdata_s),
+    .up_dac_dld (up_dac_dld_s),
+    .up_dac_dwdata (up_dac_dwdata_s),
+    .up_dac_drdata (up_dac_drdata_s),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked_s));
+  end
+  endgenerate
+
+  generate
+  if (CMOS_OR_LVDS_N == 0) begin
+
+  assign tx_clk_out = 1'd0;
+  assign tx_frame_out = 1'd0;
+  assign tx_data_out = 12'd0;
+  assign up_adc_drdata_s[64:35] = 30'd0;
+  assign up_dac_drdata_s[79:50] = 30'd0;
+
   axi_ad9361_dev_if #(
     .DEVICE_TYPE (DEVICE_TYPE),
     .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
@@ -400,19 +483,22 @@ module axi_ad9361 (
     .up_clk (up_clk),
     .up_enable (up_enable),
     .up_txnrx (up_txnrx),
-    .up_adc_dld (up_adc_dld_s),
-    .up_adc_dwdata (up_adc_dwdata_s),
-    .up_adc_drdata (up_adc_drdata_s),
-    .up_dac_dld (up_dac_dld_s),
-    .up_dac_dwdata (up_dac_dwdata_s),
-    .up_dac_drdata (up_dac_drdata_s),
+    .up_adc_dld (up_adc_dld_s[6:0]),
+    .up_adc_dwdata (up_adc_dwdata_s[34:0]),
+    .up_adc_drdata (up_adc_drdata_s[34:0]),
+    .up_dac_dld (up_dac_dld_s[9:0]),
+    .up_dac_dwdata (up_dac_dwdata_s[49:0]),
+    .up_dac_drdata (up_dac_drdata_s[49:0]),
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked_s));
+  end
+  endgenerate
 
   // TDD interface
 
   // additional flop to keep control and data synced
+
   always @(posedge clk) begin
     adc_data_i0 <= adc_data_i0_s;
     adc_data_q0 <= adc_data_q0_s;
diff --git a/library/axi_ad9361/axi_ad9361_cmos_if.v b/library/axi_ad9361/axi_ad9361_cmos_if.v
index 609dcc226..a3dcf6f59 100644
--- a/library/axi_ad9361/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/axi_ad9361_cmos_if.v
@@ -247,8 +247,8 @@ module axi_ad9361_cmos_if (
   // receive data path for dual rf, frame is expected to qualify iq for rf-1 only
 
   always @(posedge l_clk) begin
-    rx_error_r2 <= ((rx_frame_4_s == 4'b0011) ||
-      (rx_frame_4_s == 4'b1001)) ? 1'b0 : 1'b1;
+    rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) ||
+      (rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1;
     rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) ||
       (rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0;
     case (rx_frame_s)
@@ -311,13 +311,13 @@ module axi_ad9361_cmos_if (
       tx_data <= dac_data;
     end
     case (tx_data_sel_s)
-      3'b100: begin
+      3'b101: begin
         tx_frame_p <= 1'b0;
         tx_frame_n <= 1'b0;
         tx_data_p <= tx_data[35:24];
         tx_data_n <= tx_data[47:36];
       end
-      3'b101: begin
+      3'b100: begin
         tx_frame_p <= 1'b1;
         tx_frame_n <= 1'b1;
         tx_data_p <= tx_data[11: 0];
@@ -428,7 +428,7 @@ module axi_ad9361_cmos_if (
     .IODELAY_GROUP (IO_DELAY_GROUP))
   i_rx_frame (
     .rx_clk (l_clk),
-    .rx_data_in_p (rx_frame_in),
+    .rx_data_in (rx_frame_in),
     .rx_data_p (rx_frame_p_s),
     .rx_data_n (rx_frame_n_s),
     .up_clk (up_clk),
@@ -495,8 +495,8 @@ module axi_ad9361_cmos_if (
     .IODELAY_GROUP (IO_DELAY_GROUP))
   i_tx_clk (
     .tx_clk (l_clk),
-    .tx_data_p (1'b0),
-    .tx_data_n (1'b1),
+    .tx_data_p (1'b1),
+    .tx_data_n (1'b0),
     .tx_data_out (tx_clk_out),
     .up_clk (up_clk),
     .up_dld (up_dac_dld[13]),
diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl
index 72f0c8e60..9a3d0c65c 100755
--- a/library/axi_ad9361/axi_ad9361_ip.tcl
+++ b/library/axi_ad9361/axi_ad9361_ip.tcl
@@ -10,6 +10,9 @@ adi_ip_files axi_ad9361 [list \
   "$ad_hdl_dir/library/common/ad_lvds_clk.v" \
   "$ad_hdl_dir/library/common/ad_lvds_in.v" \
   "$ad_hdl_dir/library/common/ad_lvds_out.v" \
+  "$ad_hdl_dir/library/common/ad_cmos_clk.v" \
+  "$ad_hdl_dir/library/common/ad_cmos_in.v" \
+  "$ad_hdl_dir/library/common/ad_cmos_out.v" \
   "$ad_hdl_dir/library/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
@@ -32,6 +35,7 @@ adi_ip_files axi_ad9361 [list \
   "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
   "axi_ad9361_constr.xdc" \
   "axi_ad9361_dev_if.v" \
+  "axi_ad9361_cmos_if.v" \
   "axi_ad9361_rx_pnmon.v" \
   "axi_ad9361_rx_channel.v" \
   "axi_ad9361_rx.v" \
@@ -46,11 +50,36 @@ adi_ip_constraints axi_ad9361 [list \
   "axi_ad9361_constr.xdc" \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
 
+set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]]
 
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \
+  [ipx::get_ports rx_clk_in_p     -of_objects [ipx::current_core]] \
+  [ipx::get_ports rx_clk_in_n     -of_objects [ipx::current_core]] \
+  [ipx::get_ports rx_frame_in_p   -of_objects [ipx::current_core]] \
+  [ipx::get_ports rx_frame_in_n   -of_objects [ipx::current_core]] \
+  [ipx::get_ports rx_data_in_p    -of_objects [ipx::current_core]] \
+  [ipx::get_ports rx_data_in_n    -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_clk_out_p    -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_clk_out_n    -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_frame_out_p  -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_frame_out_n  -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_data_out_p   -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_data_out_n   -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \
+  [ipx::get_ports rx_clk_in       -of_objects [ipx::current_core]] \
+  [ipx::get_ports rx_frame_in     -of_objects [ipx::current_core]] \
+  [ipx::get_ports rx_data_in      -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_clk_out      -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_frame_out    -of_objects [ipx::current_core]] \
+  [ipx::get_ports tx_data_out     -of_objects [ipx::current_core]]
+
 ipx::remove_bus_interface rst [ipx::current_core]
 ipx::remove_bus_interface clk [ipx::current_core]
 ipx::remove_bus_interface l_clk [ipx::current_core]
diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v
index e28ee0978..22a699616 100644
--- a/library/axi_ad9361/axi_ad9361_rx.v
+++ b/library/axi_ad9361/axi_ad9361_rx.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 // ADC channel-need to work on dual mode for pn sequence
 
 `timescale 1ns/100ps
@@ -115,9 +113,9 @@ module axi_ad9361_rx (
 
   // delay interface
 
-  output  [ 6:0]  up_dld;
-  output  [34:0]  up_dwdata;
-  input   [34:0]  up_drdata;
+  output  [12:0]  up_dld;
+  output  [64:0]  up_dwdata;
+  input   [64:0]  up_drdata;
   input           delay_clk;
   output          delay_rst;
   input           delay_locked;
@@ -377,7 +375,7 @@ module axi_ad9361_rx (
 
   // adc delay control
 
-  up_delay_cntrl #(.DATA_WIDTH(7), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
+  up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked),
diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v
index 6c36e28b6..2b788d476 100644
--- a/library/axi_ad9361/axi_ad9361_tx.v
+++ b/library/axi_ad9361/axi_ad9361_tx.v
@@ -111,9 +111,9 @@ module axi_ad9361_tx (
   
   // delay interface
 
-  output  [ 9:0]  up_dld;
-  output  [49:0]  up_dwdata;
-  input   [49:0]  up_drdata;
+  output  [15:0]  up_dld;
+  output  [79:0]  up_dwdata;
+  input   [79:0]  up_drdata;
   input           delay_clk;
   output          delay_rst;
   input           delay_locked;
@@ -387,7 +387,7 @@ module axi_ad9361_tx (
   
   // dac delay control
 
-  up_delay_cntrl #(.DATA_WIDTH(10), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
+  up_delay_cntrl #(.DATA_WIDTH(16), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked),

From 9439862301bf701e5efb3e8b643aa1ea02a7f472 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 4 Mar 2016 18:48:52 +0200
Subject: [PATCH 098/972] daq1/cpld: Update CPLD

Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
---
 projects/daq1/cpld/daq1_cpld.v | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
index 642e3a353..b99aae8ce 100644
--- a/projects/daq1/cpld/daq1_cpld.v
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -136,7 +136,7 @@ module daq1_cpld (
   reg   [ 7:0]  dac_status = 8'b0;
   reg   [ 7:0]  clk_status = 8'b0;
 
-  reg           fpga_to_cpld = 1'b1;
+  reg           cpld_to_fpga = 1'b0;
   reg    [ 7:0] cpld_rdata = 8'b0;
   reg           cpld_rdata_bit = 1'b0;
   reg    [ 2:0] cpld_rdata_index = 3'h0;
@@ -172,25 +172,25 @@ module daq1_cpld (
 
   // SPI control and data
 
-  assign sdio = fpga_to_cpld ? fmc_spi_sdio : 1'bZ;
-  assign fmc_spi_sdio = fpga_to_cpld ? 1'bZ : cpld_rdata_s;
+  assign sdio = cpld_to_fpga ? 1'bZ : fmc_spi_sdio;
+  assign fmc_spi_sdio = cpld_to_fpga ? cpld_rdata_s : 1'bZ ;
   assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
-  assign rdnwr = ~fmc_cpld_addr[7];
+  assign rdnwr = fmc_cpld_addr[7];
 
   assign    sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0;
 
   always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
     if (fmc_spi_csn == 1'b1) begin
       fmc_spi_counter <= 6'h0;
-      fpga_to_cpld <= 1'b1;
+      cpld_to_fpga <= 1'b0;
       fmc_spi_csn_enb <= 1'b1;
     end else begin
       fmc_spi_counter <= fmc_spi_counter + 1;
       fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0;
       if (adc_spicsn & clk_spicsn) begin
-        fpga_to_cpld <= (fmc_spi_counter >= 15) ? rdnwr : 1'b1;
+        cpld_to_fpga <= (fmc_spi_counter >= 15) ? rdnwr : 1'b0;
       end else begin
-        fpga_to_cpld <= (fmc_spi_counter >= 23) ? rdnwr : 1'b1;
+        cpld_to_fpga <= (fmc_spi_counter >= 23) ? rdnwr : 1'b0;
       end
     end
   end
@@ -225,7 +225,7 @@ module daq1_cpld (
       cpld_rdata_bit <= 1'b0;
       cpld_rdata_index <= 3'h7;
     end else begin
-      if (fpga_to_cpld == 1'b0) begin
+      if (cpld_to_fpga == 1'b1) begin
         cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];
         cpld_rdata_index <= cpld_rdata_index - 1;
       end
@@ -234,8 +234,8 @@ module daq1_cpld (
 
   // Internal register write access
 
-  always @(fpga_to_cpld, cpld_spicsn, fmc_spi_counter) begin
-    if ((fpga_to_cpld == 1'b1) &&
+  always @(cpld_to_fpga, cpld_spicsn, fmc_spi_counter) begin
+    if ((cpld_to_fpga == 1'b0) &&
         (cpld_spicsn == 1'b0) &&
         (fmc_spi_counter == 8'h18)) begin
       case (fmc_cpld_addr[6:0])

From 262a42c67613e758ce4ab3028bc4e6a5050f6456 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 4 Mar 2016 18:51:20 +0200
Subject: [PATCH 099/972] daq1/cpld: Update CPLD_VERSION value

---
 projects/daq1/cpld/daq1_cpld.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
index b99aae8ce..712c8b43c 100644
--- a/projects/daq1/cpld/daq1_cpld.v
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -119,7 +119,7 @@ module daq1_cpld (
   localparam  [ 6:0]  DAC_STATUS_ADDR     = 7'h21;
   localparam  [ 6:0]  CLK_STATUS_ADDR     = 7'h22;
 
-  localparam  [ 7:0]  CPLD_VERSION        = 8'h0101;
+  localparam  [ 7:0]  CPLD_VERSION        = 8'h11;
 
   // Internal Registers/Signals
 

From 7e607957ee2616031809517bfc14563244dc517e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 4 Mar 2016 18:55:23 +0200
Subject: [PATCH 100/972] daq1.cpld: Prevent the spi_counter to roll over.

---
 projects/daq1/cpld/daq1_cpld.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
index 712c8b43c..6306a9316 100644
--- a/projects/daq1/cpld/daq1_cpld.v
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -185,7 +185,7 @@ module daq1_cpld (
       cpld_to_fpga <= 1'b0;
       fmc_spi_csn_enb <= 1'b1;
     end else begin
-      fmc_spi_counter <= fmc_spi_counter + 1;
+      fmc_spi_counter <= (fmc_spi_counter <= 6'h3F) ? fmc_spi_counter + 1 : fmc_spi_counter;
       fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0;
       if (adc_spicsn & clk_spicsn) begin
         cpld_to_fpga <= (fmc_spi_counter >= 15) ? rdnwr : 1'b0;

From b0f90bd0e8a37b80b80e3bacd869225e0aa69147 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 4 Mar 2016 18:56:21 +0200
Subject: [PATCH 101/972] daq1/cpld: Read interface fix

---
 projects/daq1/cpld/daq1_cpld.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v
index 6306a9316..6671ae029 100644
--- a/projects/daq1/cpld/daq1_cpld.v
+++ b/projects/daq1/cpld/daq1_cpld.v
@@ -177,7 +177,7 @@ module daq1_cpld (
   assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
   assign rdnwr = fmc_cpld_addr[7];
 
-  assign    sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0;
+  assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0;
 
   always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
     if (fmc_spi_csn == 1'b1) begin
@@ -222,8 +222,8 @@ module daq1_cpld (
 
   always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
     if (fmc_spi_csn == 1'b1) begin
-      cpld_rdata_bit <= 1'b0;
-      cpld_rdata_index <= 3'h7;
+      cpld_rdata_bit <= cpld_rdata[7];
+      cpld_rdata_index <= 3'h6;
     end else begin
       if (cpld_to_fpga == 1'b1) begin
         cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];

From 287770a201f87fb212df41dd4db758cb06171836 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Tue, 8 Mar 2016 10:44:58 +0100
Subject: [PATCH 102/972] axi_dmac: Fix tlast generation on AXI stream master

For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_dmac/data_mover.v      | 4 +++-
 library/axi_dmac/dest_axi_stream.v | 3 ++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v
index 0c883d5fd..714e28cb2 100644
--- a/library/axi_dmac/data_mover.v
+++ b/library/axi_dmac/data_mover.v
@@ -68,6 +68,8 @@ parameter ID_WIDTH = 3;
 parameter DATA_WIDTH = 64;
 parameter DISABLE_WAIT_FOR_ID = 1;
 parameter BEATS_PER_BURST_WIDTH = 4;
+parameter LAST = 0; /* 0 = last asserted at the end of each burst, 1 = last only asserted at the end of the transfer */
+
 localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH);
 
 `include "inc_id.h"
@@ -94,7 +96,7 @@ assign last = eot ? last_eot : last_non_eot;
 assign s_axi_ready = m_axi_ready & pending_burst & active;
 assign m_axi_valid = s_axi_valid & pending_burst & active;
 assign m_axi_data = s_axi_data;
-assign m_axi_last = last;
+assign m_axi_last = LAST ? (last_eot & eot) : last;
 
 // If we want to support zero delay between transfers we have to assert
 // req_ready on the same cycle on which the last load happens.
diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v
index a72a24e80..48c5dea55 100644
--- a/library/axi_dmac/dest_axi_stream.v
+++ b/library/axi_dmac/dest_axi_stream.v
@@ -100,7 +100,8 @@ dmac_data_mover # (
 	.ID_WIDTH(ID_WIDTH),
 	.DATA_WIDTH(S_AXIS_DATA_WIDTH),
 	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
-	.DISABLE_WAIT_FOR_ID(0)
+	.DISABLE_WAIT_FOR_ID(0),
+	.LAST(1)
 ) i_data_mover (
 	.clk(s_axis_aclk),
 	.resetn(s_axis_aresetn),

From 573146aa9614e677702d7e5ac446bc0f4181a47f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 10 Mar 2016 16:38:53 +0200
Subject: [PATCH 103/972] axi_ad7616: Fix the data width of the AXI stream
 interface

---
 library/axi_ad7616/axi_ad7616.v          | 2 +-
 projects/ad7616_sdz/common/ad7616_bd.tcl | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index ec85161a2..e18708ea0 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -143,7 +143,7 @@ module axi_ad7616 (
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
 
-  output  [31:0]  m_axis_tdata;
+  output  [(NUM_OF_SDI * DATA_WIDTH-1):0]  m_axis_tdata;
   input           m_axis_tready;
   output          m_axis_tvalid;
   input           m_axis_xfer_req;
diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index 0cf4e3178..858459e44 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -30,7 +30,7 @@ set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad7616_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad7616_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad7616_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad7616_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $axi_ad7616_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad7616_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad7616_dma
 
 # interface connections
@@ -57,7 +57,6 @@ if {$ad7616_if == 0} {
   ad_connect  cnvst axi_ad7616/cnvst
   ad_connect  busy axi_ad7616/busy
 
-
 }
 
 ad_connect  sys_cpu_clk axi_ad7616_dma/s_axis_aclk

From c566784ba9407f9c4821102d6c54198211824492 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Mar 2016 11:19:30 -0500
Subject: [PATCH 104/972] ccbrk_cmos: ccbrk copy

---
 projects/pzsdr/ccbrk_cmos/Makefile           |  84 +++++
 projects/pzsdr/ccbrk_cmos/system_bd.tcl      |   4 +
 projects/pzsdr/ccbrk_cmos/system_constr.xdc  | 258 +++++++++++++++
 projects/pzsdr/ccbrk_cmos/system_project.tcl |  21 ++
 projects/pzsdr/ccbrk_cmos/system_top.v       | 331 +++++++++++++++++++
 5 files changed, 698 insertions(+)
 create mode 100644 projects/pzsdr/ccbrk_cmos/Makefile
 create mode 100644 projects/pzsdr/ccbrk_cmos/system_bd.tcl
 create mode 100644 projects/pzsdr/ccbrk_cmos/system_constr.xdc
 create mode 100644 projects/pzsdr/ccbrk_cmos/system_project.tcl
 create mode 100644 projects/pzsdr/ccbrk_cmos/system_top.v

diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
new file mode 100644
index 000000000..49d742665
--- /dev/null
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -0,0 +1,84 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
+M_DEPS += ../../common/xilinx/sys_wfifo.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
+M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib ccbrk_pzsdr.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_gtlb clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_gpreg
+	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_gtlb
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/pzsdr/ccbrk_cmos/system_bd.tcl b/projects/pzsdr/ccbrk_cmos/system_bd.tcl
new file mode 100644
index 000000000..4907eef1b
--- /dev/null
+++ b/projects/pzsdr/ccbrk_cmos/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/ccbrk_bd.tcl
+
diff --git a/projects/pzsdr/ccbrk_cmos/system_constr.xdc b/projects/pzsdr/ccbrk_cmos/system_constr.xdc
new file mode 100644
index 000000000..05083fdc9
--- /dev/null
+++ b/projects/pzsdr/ccbrk_cmos/system_constr.xdc
@@ -0,0 +1,258 @@
+
+## constraints
+## loopback
+## p4
+
+set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33              
+set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33              
+set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33              
+set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33              
+set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33              
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33          
+set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33              
+set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33          
+set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33              
+set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33              
+set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33         
+set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33              
+set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33              
+set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33              
+set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33              
+set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33              
+set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33             
+set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33          
+set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33             
+set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33          
+set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33        
+set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33        
+
+## p5
+
+set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33             
+set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33             
+set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33             
+set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33             
+set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33             
+set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33             
+set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33        
+set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33             
+set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33             
+set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33         
+set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33             
+set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33         
+set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33             
+set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33             
+set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33             
+set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33             
+set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34              
+set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34             
+set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33        
+set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33             
+set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33        
+set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33             
+set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33        
+set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33         
+set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33        
+set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33         
+
+## p6
+
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34              
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34              
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34              
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34              
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34              
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34   
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34              
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34          
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34              
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34              
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34         
+set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34              
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34              
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34              
+set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34        
+set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34        
+set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34        
+set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34        
+
+## p7
+
+set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34        
+set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34        
+set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34        
+set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34        
+set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34             
+set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34         
+set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34             
+set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34         
+set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34             
+set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34             
+set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34             
+set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34        
+set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34             
+set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34             
+set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33               
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34             
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34             
+set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33              
+
+## p13
+
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12             
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12         
+set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12             
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12         
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12             
+set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12          
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12             
+set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12          
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12              
+set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12              
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12              
+set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12              
+set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12              
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12              
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12         
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12              
+set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12              
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12          
+set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12              
+set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12          
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12              
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12              
+set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12              
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12              
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12             
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12             
+set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12             
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12             
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12             
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12             
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12             
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12        
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12             
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12         
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12             
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12         
+
+## p2
+
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13                  
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13              
+set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13              
+set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13              
+set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13              
+set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13              
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13              
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13          
+set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13              
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13          
+set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13              
+set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13              
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13              
+set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13              
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13             
+set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13          
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13             
+set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13          
+set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13             
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13         
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13             
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13         
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13             
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13             
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13             
+set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13             
+set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13             
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13             
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13             
+set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13        
+set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13             
+set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13         
+set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13             
+set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13         
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13             
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13             
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13             
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13             
+
+## vcc
+
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13         
+
+## on board
+
+set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111           
+set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111           
+set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111              
+set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111              
+set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111              
+set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111              
+set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111              
+set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111              
+set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111              
+set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111              
+set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111              
+set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111              
+set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111              
+set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111              
+set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111              
+set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111              
+set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111              
+set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111              
+
+## clocks
+
+create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+
+## MIO loopbacks (fixed-io)
+## the following are connected to AD9361 GPIO
+
+##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
+##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
+##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
+##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
+
+## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
+
+##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
+
+## the following are mio-to-pl loopback
+
+##  JX4.97    E26   PS_MIO00_500_JX4    <==>  JX1.76    K3    IO_L11N_T1_SRCC_33        
+##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
+##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
+##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
+
+set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33        
+set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34             
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34              
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34             
+
diff --git a/projects/pzsdr/ccbrk_cmos/system_project.tcl b/projects/pzsdr/ccbrk_cmos/system_project.tcl
new file mode 100644
index 000000000..bcfeb1f4a
--- /dev/null
+++ b/projects/pzsdr/ccbrk_cmos/system_project.tcl
@@ -0,0 +1,21 @@
+
+
+
+source ../../scripts/adi_env.tcl 
+source $ad_hdl_dir/projects/scripts/adi_project.tcl 
+source $ad_hdl_dir/projects/scripts/adi_board.tcl 
+
+adi_project_create ccbrk_pzsdr
+adi_project_files ccbrk_pzsdr [list \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
+
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+
+adi_project_run ccbrk_pzsdr
+
+
diff --git a/projects/pzsdr/ccbrk_cmos/system_top.v b/projects/pzsdr/ccbrk_cmos/system_top.v
new file mode 100644
index 000000000..585b2022d
--- /dev/null
+++ b/projects/pzsdr/ccbrk_cmos/system_top.v
@@ -0,0 +1,331 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  iic_scl,
+  iic_sda,
+
+  gpio_bd,
+
+  rx_clk_in_p,
+  rx_clk_in_n,
+  rx_frame_in_p,
+  rx_frame_in_n,
+  rx_data_in_p,
+  rx_data_in_n,
+  tx_clk_out_p,
+  tx_clk_out_n,
+  tx_frame_out_p,
+  tx_frame_out_n,
+  tx_data_out_p,
+  tx_data_out_n,
+
+  enable,
+  txnrx,
+  clk_out,
+
+  gpio_clksel,
+  gpio_resetb,
+  gpio_sync,
+  gpio_en_agc,
+  gpio_ctl,
+  gpio_status,
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  gp_out,
+  gp_in,
+  gp_in_mio,
+  gp_in_1,
+
+  gt_ref_clk_p,
+  gt_ref_clk_n,
+  gt_tx_p,
+  gt_tx_n,
+  gt_rx_p,
+  gt_rx_n);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  inout   [11:0]  gpio_bd;
+
+  input           rx_clk_in_p;
+  input           rx_clk_in_n;
+  input           rx_frame_in_p;
+  input           rx_frame_in_n;
+  input   [ 5:0]  rx_data_in_p;
+  input   [ 5:0]  rx_data_in_n;
+  output          tx_clk_out_p;
+  output          tx_clk_out_n;
+  output          tx_frame_out_p;
+  output          tx_frame_out_n;
+  output  [ 5:0]  tx_data_out_p;
+  output  [ 5:0]  tx_data_out_n;
+
+  output          enable;
+  output          txnrx;
+  input           clk_out;
+
+  inout           gpio_clksel;
+  inout           gpio_resetb;
+  inout           gpio_sync;
+  inout           gpio_en_agc;
+  inout   [ 3:0]  gpio_ctl;
+  inout   [ 7:0]  gpio_status;
+
+  output          spi_csn;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  output  [87:0]  gp_out;
+  input   [87:0]  gp_in;
+  input   [ 3:0]  gp_in_mio;
+  input           gp_in_1;
+
+  input           gt_ref_clk_p;
+  input           gt_ref_clk_n;
+  output  [ 3:0]  gt_tx_p;
+  output  [ 3:0]  gt_tx_n;
+  input   [ 3:0]  gt_rx_p;
+  input   [ 3:0]  gt_rx_n;
+
+  // internal signals
+
+  wire            gt_ref_clk;
+  wire    [95:0]  gp_out_s;
+  wire    [95:0]  gp_in_s;
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+
+  assign gp_out[87:43] = gp_out_s[87:43];
+  assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
+  assign gp_out[41: 0] = gp_out_s[41: 0];
+
+  assign gp_in_s[95:93] = 3'd0;
+  assign gp_in_s[92:92] = gp_in_1;
+  assign gp_in_s[91:88] = gp_in_mio;
+  assign gp_in_s[87: 0] = gp_in;
+
+  // instantiations
+
+  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
+    .CEB (1'd0),
+    .I (gt_ref_clk_p),
+    .IB (gt_ref_clk_n),
+    .O (gt_ref_clk),
+    .ODIV2 ());
+
+  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
+    .dio_t ({gpio_t[51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[51], gpio_i[46:32]}),
+    .dio_p ({ gpio_clksel,        // 51:51
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
+    .dio_t (gpio_t[11:0]),
+    .dio_i (gpio_o[11:0]),
+    .dio_o (gpio_i[11:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gp_in_0 (gp_in_s[31:0]),
+    .gp_in_1 (gp_in_s[63:32]),
+    .gp_in_2 (gp_in_s[95:64]),
+    .gp_out_0 (gp_out_s[31:0]),
+    .gp_out_1 (gp_out_s[63:32]),
+    .gp_out_2 (gp_out_s[95:64]),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .gt_ref_clk (gt_ref_clk),
+    .gt_rx_0_n (gt_rx_n[0]),
+    .gt_rx_0_p (gt_rx_p[0]),
+    .gt_rx_1_n (gt_rx_n[1]),
+    .gt_rx_1_p (gt_rx_p[1]),
+    .gt_rx_2_n (gt_rx_n[2]),
+    .gt_rx_2_p (gt_rx_p[2]),
+    .gt_rx_3_n (gt_rx_n[3]),
+    .gt_rx_3_p (gt_rx_p[3]),
+    .gt_tx_0_n (gt_tx_n[0]),
+    .gt_tx_0_p (gt_tx_p[0]),
+    .gt_tx_1_n (gt_tx_n[1]),
+    .gt_tx_1_p (gt_tx_p[1]),
+    .gt_tx_2_n (gt_tx_n[2]),
+    .gt_tx_2_p (gt_tx_p[2]),
+    .gt_tx_3_n (gt_tx_n[3]),
+    .gt_tx_3_p (gt_tx_p[3]),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .otg_vbusoc (1'b0),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From c7ee15d4f41b7b6d149c8794a9b111af022e32be Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Mar 2016 11:24:35 -0500
Subject: [PATCH 105/972] ccbrk_cmos: cmos mode

---
 projects/pzsdr/ccbrk_cmos/system_bd.tcl      |  44 ++++
 projects/pzsdr/ccbrk_cmos/system_constr.xdc  | 258 -------------------
 projects/pzsdr/ccbrk_cmos/system_project.tcl |  13 +-
 projects/pzsdr/ccbrk_cmos/system_top.v       |  58 ++---
 4 files changed, 71 insertions(+), 302 deletions(-)
 delete mode 100644 projects/pzsdr/ccbrk_cmos/system_constr.xdc

diff --git a/projects/pzsdr/ccbrk_cmos/system_bd.tcl b/projects/pzsdr/ccbrk_cmos/system_bd.tcl
index 4907eef1b..0214a7513 100644
--- a/projects/pzsdr/ccbrk_cmos/system_bd.tcl
+++ b/projects/pzsdr/ccbrk_cmos/system_bd.tcl
@@ -2,3 +2,47 @@
 source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
 source ../common/ccbrk_bd.tcl
 
+# CMOS Mode 
+
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_n]]]
+
+delete_bd_objs [get_bd_ports tx_clk_out_p]
+delete_bd_objs [get_bd_ports tx_clk_out_n]
+delete_bd_objs [get_bd_ports tx_frame_out_p]
+delete_bd_objs [get_bd_ports tx_frame_out_n]
+delete_bd_objs [get_bd_ports tx_data_out_p]
+delete_bd_objs [get_bd_ports tx_data_out_n]
+delete_bd_objs [get_bd_ports rx_clk_in_p]
+delete_bd_objs [get_bd_ports rx_clk_in_n]
+delete_bd_objs [get_bd_ports rx_frame_in_p]
+delete_bd_objs [get_bd_ports rx_frame_in_n]
+delete_bd_objs [get_bd_ports rx_data_in_p]
+delete_bd_objs [get_bd_ports rx_data_in_n]
+
+create_bd_port -dir I rx_clk_in
+create_bd_port -dir I rx_frame_in
+create_bd_port -dir I -from 11 -to 0 rx_data_in
+create_bd_port -dir O tx_clk_out
+create_bd_port -dir O tx_frame_out
+create_bd_port -dir O -from 11 -to 0 tx_data_out
+
+set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
+
+ad_connect  rx_clk_in axi_ad9361/rx_clk_in
+ad_connect  rx_frame_in axi_ad9361/rx_frame_in
+ad_connect  rx_data_in axi_ad9361/rx_data_in
+ad_connect  tx_clk_out axi_ad9361/tx_clk_out
+ad_connect  tx_frame_out axi_ad9361/tx_frame_out
+ad_connect  tx_data_out axi_ad9361/tx_data_out
+
diff --git a/projects/pzsdr/ccbrk_cmos/system_constr.xdc b/projects/pzsdr/ccbrk_cmos/system_constr.xdc
deleted file mode 100644
index 05083fdc9..000000000
--- a/projects/pzsdr/ccbrk_cmos/system_constr.xdc
+++ /dev/null
@@ -1,258 +0,0 @@
-
-## constraints
-## loopback
-## p4
-
-set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33              
-set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33              
-set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33              
-set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33              
-set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33              
-set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33          
-set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33              
-set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33          
-set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33              
-set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33              
-set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33         
-set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33              
-set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33              
-set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33              
-set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33              
-set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33              
-set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33             
-set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33          
-set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33             
-set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33          
-set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33        
-set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33        
-
-## p5
-
-set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33             
-set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33             
-set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33             
-set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33             
-set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33             
-set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33             
-set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33        
-set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33             
-set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33             
-set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33         
-set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33             
-set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33         
-set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33             
-set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33             
-set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33             
-set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33             
-set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34              
-set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34             
-set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33        
-set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33             
-set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33        
-set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33             
-set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33        
-set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33         
-set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33        
-set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33         
-
-## p6
-
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34              
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34              
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34              
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34              
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34              
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34   
-set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34              
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34          
-set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34              
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34              
-set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34         
-set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34              
-set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34              
-set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34              
-set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34        
-set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34        
-set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34        
-set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34        
-
-## p7
-
-set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34        
-set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34        
-set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34        
-set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34        
-set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34             
-set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34         
-set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34             
-set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34         
-set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34             
-set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34             
-set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34             
-set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34        
-set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34             
-set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34             
-set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33               
-set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34             
-set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34             
-set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33              
-
-## p13
-
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12             
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12         
-set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12             
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12         
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12             
-set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12          
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12             
-set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12          
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12              
-set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12              
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12              
-set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12              
-set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12              
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12              
-set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12         
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12              
-set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12              
-set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12          
-set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12              
-set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12          
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12              
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12              
-set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12              
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12              
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12             
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12             
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12             
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12             
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12             
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12             
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12             
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12        
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12             
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12         
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12             
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12         
-
-## p2
-
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13                  
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13              
-set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13              
-set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13              
-set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13              
-set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13              
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13              
-set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13          
-set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13              
-set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13          
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13              
-set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13              
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13              
-set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13              
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13             
-set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13          
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13             
-set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13          
-set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13             
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13         
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13             
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13         
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13             
-set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13             
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13             
-set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13             
-set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13             
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13             
-set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13             
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13        
-set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13             
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13         
-set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13             
-set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13         
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13             
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13             
-set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13             
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13             
-
-## vcc
-
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13         
-
-## on board
-
-set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111           
-set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111           
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111              
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111              
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111              
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111              
-set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111              
-set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111              
-set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111              
-set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111              
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111              
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111              
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111              
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111              
-set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111              
-set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111              
-set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111              
-set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111              
-
-## clocks
-
-create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-
-## MIO loopbacks (fixed-io)
-## the following are connected to AD9361 GPIO
-
-##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
-##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
-##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
-##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
-
-## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
-
-##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
-
-## the following are mio-to-pl loopback
-
-##  JX4.97    E26   PS_MIO00_500_JX4    <==>  JX1.76    K3    IO_L11N_T1_SRCC_33        
-##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
-##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
-##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
-
-set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33        
-set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34             
-set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34              
-set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34             
-
diff --git a/projects/pzsdr/ccbrk_cmos/system_project.tcl b/projects/pzsdr/ccbrk_cmos/system_project.tcl
index bcfeb1f4a..2912aaa6b 100644
--- a/projects/pzsdr/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr/ccbrk_cmos/system_project.tcl
@@ -5,17 +5,14 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
 
-adi_project_create ccbrk_pzsdr
-adi_project_files ccbrk_pzsdr [list \
+adi_project_create ccbrk_cmos_pzsdr
+adi_project_files ccbrk_cmos_pzsdr [list \
   "system_top.v" \
-  "system_constr.xdc"\
+  "../ccbrk/system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run ccbrk_pzsdr
+adi_project_run ccbrk_cmos_pzsdr
 
 
diff --git a/projects/pzsdr/ccbrk_cmos/system_top.v b/projects/pzsdr/ccbrk_cmos/system_top.v
index 585b2022d..a45ae66eb 100644
--- a/projects/pzsdr/ccbrk_cmos/system_top.v
+++ b/projects/pzsdr/ccbrk_cmos/system_top.v
@@ -67,18 +67,13 @@ module system_top (
 
   gpio_bd,
 
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
+  rx_clk_in,
+  rx_frame_in,
+  rx_data_in,
+  tx_clk_out,
+  tx_frame_out,
+  tx_data_out,
+  tx_gnd,
 
   enable,
   txnrx,
@@ -136,18 +131,13 @@ module system_top (
 
   inout   [11:0]  gpio_bd;
 
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
+  input           rx_clk_in;
+  input           rx_frame_in;
+  input   [11:0]  rx_data_in;
+  output          tx_clk_out;
+  output          tx_frame_out;
+  output  [11:0]  tx_data_out;
+  output  [ 1:0]  tx_gnd;
 
   output          enable;
   output          txnrx;
@@ -188,6 +178,8 @@ module system_top (
 
   // assignments
 
+  assign tx_gnd = 2'd0;
+
   assign gp_out[87:43] = gp_out_s[87:43];
   assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
   assign gp_out[41: 0] = gp_out_s[41: 0];
@@ -288,12 +280,9 @@ module system_top (
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
     .ps_intr_15 (1'b0),
-    .rx_clk_in_n (rx_clk_in_n),
-    .rx_clk_in_p (rx_clk_in_p),
-    .rx_data_in_n (rx_data_in_n),
-    .rx_data_in_p (rx_data_in_p),
-    .rx_frame_in_n (rx_frame_in_n),
-    .rx_frame_in_p (rx_frame_in_p),
+    .rx_clk_in (rx_clk_in),
+    .rx_data_in (rx_data_in),
+    .rx_frame_in (rx_frame_in),
     .spi0_clk_i (1'b0),
     .spi0_clk_o (spi_clk),
     .spi0_csn_0_o (spi_csn),
@@ -315,12 +304,9 @@ module system_top (
     .tdd_sync_i (1'b0),
     .tdd_sync_o (),
     .tdd_sync_t (),
-    .tx_clk_out_n (tx_clk_out_n),
-    .tx_clk_out_p (tx_clk_out_p),
-    .tx_data_out_n (tx_data_out_n),
-    .tx_data_out_p (tx_data_out_p),
-    .tx_frame_out_n (tx_frame_out_n),
-    .tx_frame_out_p (tx_frame_out_p),
+    .tx_clk_out (tx_clk_out),
+    .tx_data_out (tx_data_out),
+    .tx_frame_out (tx_frame_out),
     .txnrx (txnrx),
     .up_enable (gpio_o[47]),
     .up_txnrx (gpio_o[48]));

From 561412e322336354e8c78dfa17dd04a7aa718c3e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Mar 2016 11:25:37 -0500
Subject: [PATCH 106/972] pzsdr-cmos swap

---
 .../common/pzsdr/pzsdr_cmos_system_constr.xdc | 50 +++++++++----------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
index 2d7cd3ebe..05bed7714 100644
--- a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
+++ b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
@@ -4,39 +4,39 @@
 
 set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports rx_clk_in]       ; ## IO_L12P_T1_MRCC_35
 set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18} [get_ports rx_frame_in]     ; ## IO_L7P_T1_AD2P_35
-set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]   ; ## IO_L1N_T0_AD0N_35
-set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]   ; ## IO_L1P_T0_AD0P_35
-set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]   ; ## IO_L2N_T0_AD8N_35
-set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]   ; ## IO_L2P_T0_AD8P_35
-set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]   ; ## IO_L3N_T0_DQS_AD1N_35
-set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]   ; ## IO_L3P_T0_DQS_AD1P_35
-set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]   ; ## IO_L4N_T0_35
-set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]   ; ## IO_L4P_T0_35
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]   ; ## IO_L5N_T0_AD9N_35
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]   ; ## IO_L5P_T0_AD9P_35
-set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]  ; ## IO_L6N_T0_VREF_35
-set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]  ; ## IO_L6P_T0_35
+set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]   ; ## IO_L13N_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]   ; ## IO_L13P_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]   ; ## IO_L14N_T2_AD4N_SRCC_35
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]   ; ## IO_L14P_T2_AD4P_SRCC_35
+set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]   ; ## IO_L15N_T2_DQS_AD12N_35
+set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]   ; ## IO_L15P_T2_DQS_AD12P_35
+set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]   ; ## IO_L16N_T2_35
+set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]   ; ## IO_L16P_T2_35
+set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]   ; ## IO_L17N_T2_AD5N_35
+set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]   ; ## IO_L17P_T2_AD5P_35
+set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]  ; ## IO_L18N_T2_AD13N_35
+set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]  ; ## IO_L18P_T2_AD13P_35
 
 set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]      ; ## IO_L8P_T1_AD10P_35
 set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]    ; ## IO_L9P_T1_DQS_AD3P_35
-set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]  ; ## IO_L13N_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]  ; ## IO_L13P_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]  ; ## IO_L14N_T2_AD4N_SRCC_35
-set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]  ; ## IO_L14P_T2_AD4P_SRCC_35
-set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]  ; ## IO_L15N_T2_DQS_AD12N_35
-set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]  ; ## IO_L15P_T2_DQS_AD12P_35
-set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]  ; ## IO_L16N_T2_35
-set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]  ; ## IO_L16P_T2_35
-set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]  ; ## IO_L17N_T2_AD5N_35
-set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]  ; ## IO_L17P_T2_AD5P_35
-set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L18N_T2_AD13N_35
-set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L18P_T2_AD13P_35
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]  ; ## IO_L1N_T0_AD0N_35    
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]  ; ## IO_L1P_T0_AD0P_35    
+set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]  ; ## IO_L2N_T0_AD8N_35    
+set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]  ; ## IO_L2P_T0_AD8P_35    
+set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]  ; ## IO_L3N_T0_DQS_AD1N_35
+set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]  ; ## IO_L3P_T0_DQS_AD1P_35
+set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]  ; ## IO_L4N_T0_35         
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]  ; ## IO_L4P_T0_35         
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]  ; ## IO_L5N_T0_AD9N_35    
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]  ; ## IO_L5P_T0_AD9P_35    
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L6N_T0_VREF_35    
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L6P_T0_35         
 
 set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]]       ; ## IO_L8N_T1_AD10N_35
 set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]]       ; ## IO_L9N_T1_DQS_AD3N_35
 
 # clocks
 
-create_clock -name rx_clk       -period  8 [get_ports rx_clk_in_p]
+create_clock -name rx_clk       -period  8 [get_ports rx_clk_in]
 create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
 

From 33b265a7427b44dd43c12bbd44ee69d4fe93a563 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 14 Mar 2016 09:31:17 +0200
Subject: [PATCH 107/972] Makefile: Update Makefiles

---
 library/axi_ad9361/Makefile        |  4 +++
 library/axi_jesd_gt/Makefile       | 16 +++++++--
 library/interfaces/Makefile        | 55 ++++++++++++++++++++++--------
 library/util_gtlb/Makefile         | 14 ++++++--
 library/util_jesd_gt/Makefile      | 14 ++++++--
 projects/pzsdr/Makefile            |  3 ++
 projects/pzsdr/ccbrk/Makefile      |  1 +
 projects/pzsdr/ccbrk_cmos/Makefile |  9 ++---
 projects/pzsdr/ccfmc/Makefile      |  1 +
 projects/pzsdr/ccpci/Makefile      |  1 +
 projects/usdrx1/a5gt/Makefile      | 47 +++++++++++++++++++++++++
 11 files changed, 141 insertions(+), 24 deletions(-)

diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile
index 702aba3f2..eb79b9900 100644
--- a/library/axi_ad9361/Makefile
+++ b/library/axi_ad9361/Makefile
@@ -13,6 +13,9 @@ M_DEPS += ../common/ad_rst.v
 M_DEPS += ../common/ad_lvds_clk.v
 M_DEPS += ../common/ad_lvds_in.v
 M_DEPS += ../common/ad_lvds_out.v
+M_DEPS += ../common/ad_cmos_clk.v
+M_DEPS += ../common/ad_cmos_in.v
+M_DEPS += ../common/ad_cmos_out.v
 M_DEPS += ../common/ad_mul.v
 M_DEPS += ../common/ad_pnmon.v
 M_DEPS += ../common/ad_dds_sine.v
@@ -35,6 +38,7 @@ M_DEPS += ../common/up_dac_channel.v
 M_DEPS += ../common/up_tdd_cntrl.v
 M_DEPS += axi_ad9361_constr.xdc
 M_DEPS += axi_ad9361_dev_if.v
+M_DEPS += axi_ad9361_cmos_if.v
 M_DEPS += axi_ad9361_rx_pnmon.v
 M_DEPS += axi_ad9361_rx_channel.v
 M_DEPS += axi_ad9361_rx.v
diff --git a/library/axi_jesd_gt/Makefile b/library/axi_jesd_gt/Makefile
index 3ac3a89de..e8fdc5069 100644
--- a/library/axi_jesd_gt/Makefile
+++ b/library/axi_jesd_gt/Makefile
@@ -21,6 +21,16 @@ M_DEPS += ../common/up_gt_channel.v
 M_DEPS += ../common/up_gt.v
 M_DEPS += axi_jesd_gt_constr.xdc
 M_DEPS += axi_jesd_gt.v
+M_DEPS += ../interfaces/if_gt_qpll.xml
+M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
+M_DEPS += ../interfaces/if_gt_pll.xml
+M_DEPS += ../interfaces/if_gt_pll_rtl.xml
+M_DEPS += ../interfaces/if_gt_rx.xml
+M_DEPS += ../interfaces/if_gt_rx_rtl.xml
+M_DEPS += ../interfaces/if_gt_rx_ksig.xml
+M_DEPS += ../interfaces/if_gt_rx_ksig_rtl.xml
+M_DEPS += ../interfaces/if_gt_tx.xml
+M_DEPS += ../interfaces/if_gt_tx_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
@@ -35,8 +45,8 @@ M_FLIST += .Xil
 
 
 
-.PHONY: all clean clean-all
-all: axi_jesd_gt.xpr
+.PHONY: all dep clean clean-all
+all: dep axi_jesd_gt.xpr
 
 
 clean:clean-all
@@ -50,5 +60,7 @@ axi_jesd_gt.xpr: $(M_DEPS)
 	rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_jesd_gt_ip.tcl  >> axi_jesd_gt_ip.log 2>&1
 
+dep:
+	make -C ../interfaces
 ####################################################################################
 ####################################################################################
diff --git a/library/interfaces/Makefile b/library/interfaces/Makefile
index cb50c9c27..996cec8d9 100644
--- a/library/interfaces/Makefile
+++ b/library/interfaces/Makefile
@@ -11,31 +11,58 @@ M_DEPS += ../scripts/adi_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += component.xml
+M_FLIST := *.log
 M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += .Xil
-
+M_FLIST += if_gt_qpll.xml
+M_FLIST += if_gt_qpll_rtl.xml
+M_FLIST += if_gt_pll.xml
+M_FLIST += if_gt_pll_rtl.xml
+M_FLIST += if_gt_rx.xml
+M_FLIST += if_gt_rx_rtl.xml
+M_FLIST += if_gt_tx.xml
+M_FLIST += if_gt_tx_rtl.xml
+M_FLIST += if_gt_rx_ksig.xml
+M_FLIST += if_gt_rx_ksig_rtl.xml
 
 
 .PHONY: all clean clean-all
-all: interfaces.xpr
-
+all: if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml 
 
 clean:clean-all
 
-
 clean-all:
 	rm -rf $(M_FLIST)
 
+if_gt_qpll.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_qpll_rtl.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_pll.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_pll_rtl.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_rx.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_rx_rtl.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_tx.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_tx_rtl.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_rx_ksig.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_gt_rx_ksig_rtl.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
 
-interfaces.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
-	$(M_VIVADO) interfaces_ip.tcl  >> interfaces_ip.log 2>&1
 
 ####################################################################################
 ####################################################################################
diff --git a/library/util_gtlb/Makefile b/library/util_gtlb/Makefile
index 3f3542448..8dc22b792 100644
--- a/library/util_gtlb/Makefile
+++ b/library/util_gtlb/Makefile
@@ -11,6 +11,14 @@ M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/up_xfer_status.v
 M_DEPS += util_gtlb_constr.xdc
 M_DEPS += util_gtlb.v
+M_DEPS += ../interfaces/if_gt_qpll.xml
+M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
+M_DEPS += ../interfaces/if_gt_pll.xml
+M_DEPS += ../interfaces/if_gt_pll_rtl.xml
+M_DEPS += ../interfaces/if_gt_rx.xml
+M_DEPS += ../interfaces/if_gt_rx_rtl.xml
+M_DEPS += ../interfaces/if_gt_tx.xml
+M_DEPS += ../interfaces/if_gt_tx_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
@@ -25,8 +33,8 @@ M_FLIST += .Xil
 
 
 
-.PHONY: all clean clean-all
-all: util_gtlb.xpr
+.PHONY: all dep clean clean-all
+all: dep util_gtlb.xpr
 
 
 clean:clean-all
@@ -40,5 +48,7 @@ util_gtlb.xpr: $(M_DEPS)
 	rm -rf $(M_FLIST)
 	$(M_VIVADO) util_gtlb_ip.tcl  >> util_gtlb_ip.log 2>&1
 
+dep:
+	make -C ../interfaces
 ####################################################################################
 ####################################################################################
diff --git a/library/util_jesd_gt/Makefile b/library/util_jesd_gt/Makefile
index 618434618..c78666c37 100644
--- a/library/util_jesd_gt/Makefile
+++ b/library/util_jesd_gt/Makefile
@@ -9,6 +9,14 @@ M_DEPS := util_jesd_gt_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_jesd_gt.v
+M_DEPS += ../interfaces/if_gt_qpll.xml
+M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
+M_DEPS += ../interfaces/if_gt_pll.xml
+M_DEPS += ../interfaces/if_gt_pll_rtl.xml
+M_DEPS += ../interfaces/if_gt_rx.xml
+M_DEPS += ../interfaces/if_gt_rx_rtl.xml
+M_DEPS += ../interfaces/if_gt_tx.xml
+M_DEPS += ../interfaces/if_gt_tx_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
@@ -23,8 +31,8 @@ M_FLIST += .Xil
 
 
 
-.PHONY: all clean clean-all
-all: util_jesd_gt.xpr
+.PHONY: all dep clean clean-all
+all: dep util_jesd_gt.xpr
 
 
 clean:clean-all
@@ -38,5 +46,7 @@ util_jesd_gt.xpr: $(M_DEPS)
 	rm -rf $(M_FLIST)
 	$(M_VIVADO) util_jesd_gt_ip.tcl  >> util_jesd_gt_ip.log 2>&1
 
+dep:
+	make -C ../interfaces
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr/Makefile b/projects/pzsdr/Makefile
index 924f12685..70c685d18 100644
--- a/projects/pzsdr/Makefile
+++ b/projects/pzsdr/Makefile
@@ -8,6 +8,7 @@
 .PHONY: all clean clean-all 
 all:
 	-make -C ccbrk all
+	-make -C ccbrk_cmos all
 	-make -C ccfmc all
 	-make -C ccpci all
 	-make -C ccbrk all
@@ -15,6 +16,7 @@ all:
 
 clean: 
 	make -C ccbrk clean
+	make -C ccbrk_cmos clean
 	make -C ccfmc clean
 	make -C ccpci clean
 	make -C ccbrk clean
@@ -22,6 +24,7 @@ clean:
 
 clean-all:
 	make -C ccbrk clean-all
+	make -C ccbrk_cmos clean-all
 	make -C ccfmc clean-all
 	make -C ccpci clean-all
 	make -C ccbrk clean-all
diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile
index 49d742665..7a8f44653 100644
--- a/projects/pzsdr/ccbrk/Makefile
+++ b/projects/pzsdr/ccbrk/Makefile
@@ -18,6 +18,7 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
index 49d742665..3f52934bb 100644
--- a/projects/pzsdr/ccbrk_cmos/Makefile
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -7,9 +7,9 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
 M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../ccbrk/system_constr.xdc
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
@@ -18,6 +18,7 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_cmos_system_constr.xdc
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -45,7 +46,7 @@ M_FLIST += .Xil
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_pzsdr.sdk/system_top.hdf
+all: lib ccbrk_cmos_pzsdr.sdk/system_top.hdf
 
 
 clean: 
@@ -64,9 +65,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+ccbrk_cmos_pzsdr.sdk/system_top.hdf: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ccbrk_cmos_pzsdr_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile
index a29f3d69a..9f93d9e5b 100644
--- a/projects/pzsdr/ccfmc/Makefile
+++ b/projects/pzsdr/ccfmc/Makefile
@@ -18,6 +18,7 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci/Makefile
index 5668a66a3..5cdeb0619 100644
--- a/projects/pzsdr/ccpci/Makefile
+++ b/projects/pzsdr/ccpci/Makefile
@@ -18,6 +18,7 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index d461204bb..e69a48ede 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -7,11 +7,58 @@
 
 M_DEPS += system_project.tcl
 M_DEPS += ../common/usdrx1_spi.v
+M_DEPS += ../common/usdrx1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
 M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v
 M_DEPS += ../../../library/common/altera/ad_jesd_align.v
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671.v
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671_channel.v
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671_hw.tcl
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671_if.v
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671_pnmon.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_mem.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_xcvr.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
 
 
 M_ALTERA := quartus_sh --64bit -t 

From 8ecf5edaf840dafeba241fb0b1c878a82e5f412d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 14 Mar 2016 11:14:17 -0400
Subject: [PATCH 108/972] ad9122- pat modes

---
 library/axi_ad9122/axi_ad9122_channel.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v
index 7b64d2d32..93bb5a3e8 100644
--- a/library/axi_ad9122/axi_ad9122_channel.v
+++ b/library/axi_ad9122/axi_ad9122_channel.v
@@ -141,8 +141,8 @@ module axi_ad9122_channel (
     dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
     case (dac_data_sel_s)
       4'h2: dac_data <= dma_data;
-      4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
-                          dac_pat_data_2_s, dac_pat_data_1_s};
+      4'ha, 4'h1: dac_data <= {dac_pat_data_2_s, dac_pat_data_1_s,
+        dac_pat_data_2_s, dac_pat_data_1_s};
       default: dac_data <= dac_dds_data;
     endcase
     if (dac_data_sel_s == 4'h1) begin

From 665bfbc991a753a6fc2eceb7204a5a25996157bb Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 15 Mar 2016 18:38:55 +0200
Subject: [PATCH 109/972] axi_ad7616: Add M_AXIS_READY_ENABLE parameter

m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
---
 library/axi_ad7616/axi_ad7616.v | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index e18708ea0..600a48533 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -96,6 +96,7 @@ module axi_ad7616 (
 
   parameter       ID = 0;
   parameter       IF_TYPE = 1;
+  parameter       M_AXIS_READY_ENABLE = 0;
 
   // local parameters
 
@@ -179,6 +180,8 @@ module axi_ad7616 (
   wire                              rd_dvalid_s;
   wire    [ 4:0]                    burst_length_s;
 
+  wire                              m_axis_ready_s;
+
   // internal registers
 
   reg                               up_wack = 1'b0;
@@ -205,6 +208,8 @@ module axi_ad7616 (
     end
   end
 
+  assign m_axis_ready_s = (M_AXIS_READY_ENABLE) ? m_axis_tready : 1'b1;
+
   generate if (IF_TYPE == SERIAL) begin
 
     // ground all parallel interface signals
@@ -328,7 +333,7 @@ module axi_ad7616 (
       .sync_ready (s1_sync_ready_s),
       .sync_data (s1_sync_s),
       .offload_sdi_valid (m_axis_tvalid),
-      .offload_sdi_ready (m_axis_tready),
+      .offload_sdi_ready (m_axis_ready_s),
       .offload_sdi_data (m_axis_tdata));
 
     spi_engine_interconnect #(
@@ -426,7 +431,7 @@ module axi_ad7616 (
       .wr_n(wr_n),
       .m_axis_tdata(m_axis_tdata),
       .m_axis_tvalid(m_axis_tvalid),
-      .m_axis_tready(m_axis_tready),
+      .m_axis_tready(m_axis_ready_s),
       .m_axis_xfer_req(m_axis_xfer_req),
       .end_of_conv(trigger_s),
       .burst_length(burst_length_s),

From 697469ee28bd8c4e65713f5db797f4fe05f34f20 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 15 Mar 2016 12:39:38 -0400
Subject: [PATCH 110/972] daq1- updates

---
 projects/daq1/common/daq1_bd.tcl      |  8 +--
 projects/daq1/zc706/system_constr.xdc | 11 ++--
 projects/daq1/zc706/system_top.v      | 91 ++++++++++++++-------------
 3 files changed, 56 insertions(+), 54 deletions(-)

diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl
index b86268444..74b8ad4f9 100644
--- a/projects/daq1/common/daq1_bd.tcl
+++ b/projects/daq1/common/daq1_bd.tcl
@@ -19,7 +19,7 @@ create_bd_port -dir I -from 13 -to 0 adc_data_in_n
 
 # daq1 irq
 
-create_bd_port -dir I daq1_irq
+create_bd_port -dir I spi_int
 
 # dac peripherals
 
@@ -132,7 +132,7 @@ ad_connect  sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
 
 # interrupts
 
-ad_cpu_interrupt ps-13 mb-12 axi_ad9122_dma/irq
-ad_cpu_interrupt ps-12 mb-13 axi_ad9684_dma/irq
-ad_cpu_interrupt ps-11 mb-14 daq1_irq
+ad_cpu_interrupt ps-11 mb-11 spi_int
+ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq
+ad_cpu_interrupt ps-13 mb-13 axi_ad9684_dma/irq
 
diff --git a/projects/daq1/zc706/system_constr.xdc b/projects/daq1/zc706/system_constr.xdc
index f00fd103b..6cdaa0e7f 100644
--- a/projects/daq1/zc706/system_constr.xdc
+++ b/projects/daq1/zc706/system_constr.xdc
@@ -5,10 +5,8 @@ set_property  -dict {PACKAGE_PIN  AC28  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get
 set_property  -dict {PACKAGE_PIN  AD28  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports dac_clk_in_n]            ; ##  G03  FMC_LPC_CLK1_M2C_N
 set_property  -dict {PACKAGE_PIN  AF29  IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p]                          ; ##  G27  FMC_LPC_LA25_P
 set_property  -dict {PACKAGE_PIN  AG29  IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n]                          ; ##  G28  FMC_LPC_LA25_N
-
 set_property  -dict {PACKAGE_PIN  Y26   IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p]                        ; ##  H37  FMC_LPC_LA32_P
 set_property  -dict {PACKAGE_PIN  Y27   IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n]                        ; ##  H38  FMC_LPC_LA32_N
-
 set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]]                      ; ##  H19  FMC_LPC_LA15_P
 set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]]                      ; ##  H20  FMC_LPC_LA15_N
 set_property  -dict {PACKAGE_PIN  AG26  IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]]                      ; ##  G21  FMC_LPC_LA20_P
@@ -44,7 +42,6 @@ set_property  -dict {PACKAGE_PIN  AA30  IOSTANDARD LVDS_25 } [get_ports dac_data
 
 set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_clk_in_p]            ; ##  G06  FMC_LPC_LA00_CC_P
 set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_clk_in_n]            ; ##  G07  FMC_LPC_LA00_CC_N
-
 set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]        ; ##  C14  FMC_LPC_LA10_P
 set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]        ; ##  C15  FMC_LPC_LA10_N
 set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]        ; ##  C18  FMC_LPC_LA14_P
@@ -74,10 +71,10 @@ set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get
 set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]       ; ##  D08  FMC_LPC_LA01_CC_P
 set_property  -dict {PACKAGE_PIN  AG15  IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]       ; ##  D09  FMC_LPC_LA01_CC_N
 
-set_property  -dict {PACKAGE_PIN  AG17  IOSTANDARD LVCMOS25} [get_ports cpld_sclk]                              ; ##  H04  FMC_LPC_CLK0_M2C_P
-set_property  -dict {PACKAGE_PIN  AG16  IOSTANDARD LVCMOS25} [get_ports cpld_csn]                               ; ##  H05  FMC_LPC_CLK0_M2C_N
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports cpld_sdio]                              ; ##  G18  FMC_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports daq1_irq]                               ; ##  G19  FMC_LPC_LA16_N
+set_property  -dict {PACKAGE_PIN  AG16  IOSTANDARD LVCMOS25} [get_ports spi_csn]                                ; ##  H05  FMC_LPC_CLK0_M2C_N
+set_property  -dict {PACKAGE_PIN  AG17  IOSTANDARD LVCMOS25} [get_ports spi_clk]                                ; ##  H04  FMC_LPC_CLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports spi_sdio]                               ; ##  G18  FMC_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports spi_int]                                ; ##  G19  FMC_LPC_LA16_N
 
 # clocks
 
diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v
index c3d8dfcdc..109232e4a 100644
--- a/projects/daq1/zc706/system_top.v
+++ b/projects/daq1/zc706/system_top.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -91,12 +89,10 @@ module system_top (
   adc_data_in_p,
   adc_data_in_n,
 
-  daq1_irq,
-
-  cpld_sclk,
-  cpld_csn,
-  cpld_sdio
-);
+  spi_clk,
+  spi_csn,
+  spi_sdio,
+  spi_int);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -148,37 +144,47 @@ module system_top (
   input  [13:0]   adc_data_in_p;
   input  [13:0]   adc_data_in_n;
 
-  input           daq1_irq;
-
-  output          cpld_sclk;
-  output          cpld_csn;
-  inout           cpld_sdio;
+  output          spi_clk;
+  output          spi_csn;
+  inout           spi_sdio;
+  input           spi_int;
 
   // internal signals
 
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
+  wire            spi_mosi;
+  wire            spi_miso;
 
   // instantiations
 
-  ad_iobuf #(
-    .DATA_WIDTH(15)
-  ) i_gpio_bd (
-    .dio_t(gpio_t[14:0]),
-    .dio_i(gpio_o[14:0]),
-    .dio_o(gpio_i[14:0]),
-    .dio_p(gpio_bd));
+  ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd (
+    .dio_t (gpio_t[14:0]),
+    .dio_i (gpio_o[14:0]),
+    .dio_o (gpio_i[14:0]),
+    .dio_p (gpio_bd));
 
   daq1_spi i_spi (
-    .spi_csn(cpld_csn),
-    .spi_clk(cpld_sclk),
-    .spi_mosi(cpld_mosi),
-    .spi_miso(cpld_miso),
-    .spi_sdio(cpld_sdio)
-  );
+    .spi_csn (spi_csn),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_sdio (spi_sdio));
 
   system_wrapper i_system_wrapper (
+    .adc_clk_in_n (adc_clk_in_n),
+    .adc_clk_in_p (adc_clk_in_p),
+    .adc_data_in_n (adc_data_in_n),
+    .adc_data_in_p (adc_data_in_p),
+    .dac_clk_in_n (dac_clk_in_n),
+    .dac_clk_in_p (dac_clk_in_p),
+    .dac_clk_out_n (dac_clk_out_n),
+    .dac_clk_out_p (dac_clk_out_p),
+    .dac_data_out_n (dac_data_out_n),
+    .dac_data_out_p (dac_data_out_p),
+    .dac_frame_out_n (dac_frame_out_n),
+    .dac_frame_out_p (dac_frame_out_p),
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),
     .ddr_cas_n (ddr_cas_n),
@@ -223,25 +229,24 @@ module system_top (
     .ps_intr_10 (1'b0),
     .spdif (spdif),
     .spi0_clk_i (1'b0),
-    .spi0_clk_o (cpld_sclk),
-    .spi0_csn_0_o (cpld_csn),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
     .spi0_csn_i (1'b1),
-    .spi0_sdi_i (cpld_miso),
+    .spi0_sdi_i (spi_miso),
     .spi0_sdo_i (1'b0),
-    .spi0_sdo_o (cpld_mosi),
-    .dac_clk_in_p (dac_clk_in_p),
-    .dac_clk_in_n (dac_clk_in_n),
-    .dac_clk_out_p (dac_clk_out_p),
-    .dac_clk_out_n (dac_clk_out_n),
-    .dac_frame_out_p (dac_frame_out_p),
-    .dac_frame_out_n (dac_frame_out_n),
-    .dac_data_out_p (dac_data_out_p),
-    .dac_data_out_n (dac_data_out_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .daq1_irq (daq1_irq));
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .spi_int (spi_int));
 
 endmodule
 

From 0905755db7ee1aa3eb104713b3425da2baa059f4 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 11 Mar 2016 12:04:46 +0200
Subject: [PATCH 111/972] Update .gitignore file

---
 .gitignore | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/.gitignore b/.gitignore
index e88b6e59c..cb9d2a3cd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,6 +2,39 @@
 *.data
 *.xpr
 *.log
+*.bld
+*.chk
+*.cmd_log
+*.cxt
+*.gise
+*.gyd
+*.jed
+*.lso
+*.mfd
+*.nga
+*.ngc
+*.ngd
+*.ngr
+*.pad
+*.pnx
+*.prj
+*.rpt
+*.stx
+*.syr
+*.tim
+*.tspec
+*.vm6
+*.xst
+*.html
+*.xrpt
+*.err
+*_html
+xst
+netgen
+iseconfig
+xlnx_auto*
+_ngo
+_xmsgs
 component.xml
 *.jou
 xgui

From a3cb8cac452898baf70aa7b3294fc0829fe8d6ad Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 18 Mar 2016 11:51:13 +0200
Subject: [PATCH 112/972] foobar

---
 library/axi_dacfifo/axi_dacfifo.v     | 186 ++++++++++++++++++++++++++
 library/axi_dacfifo/axi_dacfifo_dma.v |  68 ++++++++++
 2 files changed, 254 insertions(+)
 create mode 100644 library/axi_dacfifo/axi_dacfifo.v
 create mode 100644 library/axi_dacfifo/axi_dacfifo_dma.v

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
new file mode 100644
index 000000000..733e9cf11
--- /dev/null
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -0,0 +1,186 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dacfifo (
+
+  // dma interface
+
+  dma_clk,
+  dma_rst,
+  dma_valid,
+  dma_data,
+  dma_ready,
+  dma_xfer_req,
+  dma_xfer_last,
+
+  // dac interface
+
+  dac_clk,
+  dac_valid,
+  dac_data
+
+  // axi interface
+
+  axi_clk,
+  axi_resetn,
+  axi_awvalid,
+  axi_awid,
+  axi_awburst,
+  axi_awlock,
+  axi_awcache,
+  axi_awprot,
+  axi_awqos,
+  axi_awuser,
+  axi_awlen,
+  axi_awsize,
+  axi_awaddr,
+  axi_awready,
+  axi_wvalid,
+  axi_wdata,
+  axi_wstrb,
+  axi_wlast,
+  axi_wuser,
+  axi_wready,
+  axi_bvalid,
+  axi_bid,
+  axi_bresp,
+  axi_buser,
+  axi_bready,
+  axi_arvalid,
+  axi_arid,
+  axi_arburst,
+  axi_arlock,
+  axi_arcache,
+  axi_arprot,
+  axi_arqos,
+  axi_aruser,
+  axi_arlen,
+  axi_arsize,
+  axi_araddr,
+  axi_arready,
+  axi_rvalid,
+  axi_rid,
+  axi_ruser,
+  axi_rresp,
+  axi_rlast,
+  axi_rdata,
+  axi_rready);
+
+  // parameters
+
+  parameter   ADC_DATA_WIDTH = 128;
+  parameter   DMA_DATA_WIDTH = 64;
+  parameter   AXI_DATA_WIDTH = 512;
+  parameter   DMA_READY_ENABLE = 1;
+  parameter   AXI_SIZE = 2;
+  parameter   AXI_LENGTH = 16;
+  parameter   AXI_ADDRESS = 32'h00000000;
+  parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
+  parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
+
+  // dma interface
+
+  input                               dma_clk;
+  input                               dma_rst;
+  input                               dma_valid;
+  input   [(DMA_DATA_WIDTH-1):0]      dma_data;
+  output                              dma_ready;
+  input                               dma_xfer_req;
+  input                               dma_xfer_last;
+
+  // dac interface
+
+  input                               dac_clk;
+  input                               dac_valid;
+  output  [(DMA_DATA_WIDTH-1):0]      dac_data;
+
+
+  // axi interface
+
+  input                               axi_clk;
+  input                               axi_resetn;
+  output                              axi_awvalid;
+  output  [  3:0]                     axi_awid;
+  output  [  1:0]                     axi_awburst;
+  output                              axi_awlock;
+  output  [  3:0]                     axi_awcache;
+  output  [  2:0]                     axi_awprot;
+  output  [  3:0]                     axi_awqos;
+  output  [  3:0]                     axi_awuser;
+  output  [  7:0]                     axi_awlen;
+  output  [  2:0]                     axi_awsize;
+  output  [ 31:0]                     axi_awaddr;
+  input                               axi_awready;
+  output                              axi_wvalid;
+  output  [AXI_DATA_WIDTH-1:0]        axi_wdata;
+  output  [AXI_BYTE_WIDTH-1:0]        axi_wstrb;
+  output                              axi_wlast;
+  output  [  3:0]                     axi_wuser;
+  input                               axi_wready;
+  input                               axi_bvalid;
+  input   [  3:0]                     axi_bid;
+  input   [  1:0]                     axi_bresp;
+  input   [  3:0]                     axi_buser;
+  output                              axi_bready;
+  output                              axi_arvalid;
+  output  [  3:0]                     axi_arid;
+  output  [  1:0]                     axi_arburst;
+  output                              axi_arlock;
+  output  [  3:0]                     axi_arcache;
+  output  [  2:0]                     axi_arprot;
+  output  [  3:0]                     axi_arqos;
+  output  [  3:0]                     axi_aruser;
+  output  [  7:0]                     axi_arlen;
+  output  [  2:0]                     axi_arsize;
+  output  [ 31:0]                     axi_araddr;
+  input                               axi_arready;
+  input                               axi_rvalid;
+  input   [  3:0]                     axi_rid;
+  input   [  3:0]                     axi_ruser;
+  input   [  1:0]                     axi_rresp;
+  input                               axi_rlast;
+  input   [AXI_DATA_WIDTH-1:0]        axi_rdata;
+  output                              axi_rready;
+
+
+
+endmodule
+
diff --git a/library/axi_dacfifo/axi_dacfifo_dma.v b/library/axi_dacfifo/axi_dacfifo_dma.v
new file mode 100644
index 000000000..abc29bac9
--- /dev/null
+++ b/library/axi_dacfifo/axi_dacfifo_dma.v
@@ -0,0 +1,68 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dacfifo_dma (
+
+  // dma interface
+
+  dma_clk,
+  dma_rst,
+  dma_valid,
+  dma_data,
+  dma_ready,
+
+  axi_ddata,
+
+);
+
+
+
+  // dma interface
+
+  input                               dma_clk;
+  input                               dma_rst;
+  input                               dma_valid;
+  input   [(DMA_DATA_WIDTH-1):0]      dma_data;
+  output                              dma_ready;
+
+
+
+endmodule

From 896c734792e245a45f17b4502e9ad11160310079 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 18 Mar 2016 13:23:02 +0200
Subject: [PATCH 113/972] Revert "foobar"

This reverts commit a3cb8cac452898baf70aa7b3294fc0829fe8d6ad.
---
 library/axi_dacfifo/axi_dacfifo.v     | 186 --------------------------
 library/axi_dacfifo/axi_dacfifo_dma.v |  68 ----------
 2 files changed, 254 deletions(-)
 delete mode 100644 library/axi_dacfifo/axi_dacfifo.v
 delete mode 100644 library/axi_dacfifo/axi_dacfifo_dma.v

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
deleted file mode 100644
index 733e9cf11..000000000
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ /dev/null
@@ -1,186 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module axi_dacfifo (
-
-  // dma interface
-
-  dma_clk,
-  dma_rst,
-  dma_valid,
-  dma_data,
-  dma_ready,
-  dma_xfer_req,
-  dma_xfer_last,
-
-  // dac interface
-
-  dac_clk,
-  dac_valid,
-  dac_data
-
-  // axi interface
-
-  axi_clk,
-  axi_resetn,
-  axi_awvalid,
-  axi_awid,
-  axi_awburst,
-  axi_awlock,
-  axi_awcache,
-  axi_awprot,
-  axi_awqos,
-  axi_awuser,
-  axi_awlen,
-  axi_awsize,
-  axi_awaddr,
-  axi_awready,
-  axi_wvalid,
-  axi_wdata,
-  axi_wstrb,
-  axi_wlast,
-  axi_wuser,
-  axi_wready,
-  axi_bvalid,
-  axi_bid,
-  axi_bresp,
-  axi_buser,
-  axi_bready,
-  axi_arvalid,
-  axi_arid,
-  axi_arburst,
-  axi_arlock,
-  axi_arcache,
-  axi_arprot,
-  axi_arqos,
-  axi_aruser,
-  axi_arlen,
-  axi_arsize,
-  axi_araddr,
-  axi_arready,
-  axi_rvalid,
-  axi_rid,
-  axi_ruser,
-  axi_rresp,
-  axi_rlast,
-  axi_rdata,
-  axi_rready);
-
-  // parameters
-
-  parameter   ADC_DATA_WIDTH = 128;
-  parameter   DMA_DATA_WIDTH = 64;
-  parameter   AXI_DATA_WIDTH = 512;
-  parameter   DMA_READY_ENABLE = 1;
-  parameter   AXI_SIZE = 2;
-  parameter   AXI_LENGTH = 16;
-  parameter   AXI_ADDRESS = 32'h00000000;
-  parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
-  parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
-
-  // dma interface
-
-  input                               dma_clk;
-  input                               dma_rst;
-  input                               dma_valid;
-  input   [(DMA_DATA_WIDTH-1):0]      dma_data;
-  output                              dma_ready;
-  input                               dma_xfer_req;
-  input                               dma_xfer_last;
-
-  // dac interface
-
-  input                               dac_clk;
-  input                               dac_valid;
-  output  [(DMA_DATA_WIDTH-1):0]      dac_data;
-
-
-  // axi interface
-
-  input                               axi_clk;
-  input                               axi_resetn;
-  output                              axi_awvalid;
-  output  [  3:0]                     axi_awid;
-  output  [  1:0]                     axi_awburst;
-  output                              axi_awlock;
-  output  [  3:0]                     axi_awcache;
-  output  [  2:0]                     axi_awprot;
-  output  [  3:0]                     axi_awqos;
-  output  [  3:0]                     axi_awuser;
-  output  [  7:0]                     axi_awlen;
-  output  [  2:0]                     axi_awsize;
-  output  [ 31:0]                     axi_awaddr;
-  input                               axi_awready;
-  output                              axi_wvalid;
-  output  [AXI_DATA_WIDTH-1:0]        axi_wdata;
-  output  [AXI_BYTE_WIDTH-1:0]        axi_wstrb;
-  output                              axi_wlast;
-  output  [  3:0]                     axi_wuser;
-  input                               axi_wready;
-  input                               axi_bvalid;
-  input   [  3:0]                     axi_bid;
-  input   [  1:0]                     axi_bresp;
-  input   [  3:0]                     axi_buser;
-  output                              axi_bready;
-  output                              axi_arvalid;
-  output  [  3:0]                     axi_arid;
-  output  [  1:0]                     axi_arburst;
-  output                              axi_arlock;
-  output  [  3:0]                     axi_arcache;
-  output  [  2:0]                     axi_arprot;
-  output  [  3:0]                     axi_arqos;
-  output  [  3:0]                     axi_aruser;
-  output  [  7:0]                     axi_arlen;
-  output  [  2:0]                     axi_arsize;
-  output  [ 31:0]                     axi_araddr;
-  input                               axi_arready;
-  input                               axi_rvalid;
-  input   [  3:0]                     axi_rid;
-  input   [  3:0]                     axi_ruser;
-  input   [  1:0]                     axi_rresp;
-  input                               axi_rlast;
-  input   [AXI_DATA_WIDTH-1:0]        axi_rdata;
-  output                              axi_rready;
-
-
-
-endmodule
-
diff --git a/library/axi_dacfifo/axi_dacfifo_dma.v b/library/axi_dacfifo/axi_dacfifo_dma.v
deleted file mode 100644
index abc29bac9..000000000
--- a/library/axi_dacfifo/axi_dacfifo_dma.v
+++ /dev/null
@@ -1,68 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module axi_dacfifo_dma (
-
-  // dma interface
-
-  dma_clk,
-  dma_rst,
-  dma_valid,
-  dma_data,
-  dma_ready,
-
-  axi_ddata,
-
-);
-
-
-
-  // dma interface
-
-  input                               dma_clk;
-  input                               dma_rst;
-  input                               dma_valid;
-  input   [(DMA_DATA_WIDTH-1):0]      dma_data;
-  output                              dma_ready;
-
-
-
-endmodule

From 373481360b0eac0f599565b69b8b0c490ae2546e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 21 Mar 2016 14:14:43 +0200
Subject: [PATCH 114/972] util_dacfifo: Add a bypass option to the FIFO

---
 library/util_dacfifo/util_dacfifo.v    | 20 +++++++++++++-------
 projects/common/xilinx/sys_dmafifo.tcl |  2 ++
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v
index a229aeacf..d08c8b833 100644
--- a/library/util_dacfifo/util_dacfifo.v
+++ b/library/util_dacfifo/util_dacfifo.v
@@ -55,7 +55,9 @@ module util_dacfifo (
 
   dac_clk,
   dac_valid,
-  dac_data
+  dac_data,
+
+  dac_fifo_bypass
 );
 
   // depth of the FIFO
@@ -80,6 +82,8 @@ module util_dacfifo (
   input                               dac_valid;
   output  [(DATA_WIDTH-1):0]          dac_data;
 
+  input                               dac_fifo_bypass;
+
   // internal registers
 
   reg     [(ADDRESS_WIDTH-1):0]       dma_waddr = 'b0;
@@ -87,10 +91,9 @@ module util_dacfifo (
   reg     [(ADDRESS_WIDTH-1):0]       dma_lastaddr_d = 'b0;
   reg     [(ADDRESS_WIDTH-1):0]       dma_lastaddr_2d = 'b0;
   reg                                 dma_xfer_req_ff = 1'b0;
-  reg                                 dma_ready = 1'b0;
+  reg                                 dma_ready_d = 1'b0;
 
   reg     [(ADDRESS_WIDTH-1):0]       dac_raddr = 'b0;
-  reg     [(DATA_WIDTH-1):0]          dac_data = 'b0;
 
   // internal wires
   wire                                dma_wren;
@@ -99,10 +102,10 @@ module util_dacfifo (
   // write interface
   always @(posedge dma_clk) begin
     if(dma_rst == 1'b1) begin
-      dma_ready <= 1'b0;
+      dma_ready_d <= 1'b0;
       dma_xfer_req_ff <= 1'b0;
     end else begin
-      dma_ready <= 1'b1;                                // Fifo is always ready
+      dma_ready_d <= 1'b1;                                // Fifo is always ready
       dma_xfer_req_ff <= dma_xfer_req;
     end
   end
@@ -141,10 +144,8 @@ module util_dacfifo (
         dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
       end
     end
-    dac_data <= dac_data_s;
   end
 
-
   // memory instantiation
 
   ad_mem #(
@@ -159,5 +160,10 @@ module util_dacfifo (
     .addrb (dac_raddr),
     .doutb (dac_data_s));
 
+  // output logic
+
+  assign dac_data = (dac_fifo_bypass) ? dma_data : dac_data_s;
+  assign dma_ready = (dac_fifo_bypass) ? dac_valid : dma_ready_d;
+
 endmodule
 
diff --git a/projects/common/xilinx/sys_dmafifo.tcl b/projects/common/xilinx/sys_dmafifo.tcl
index dec208f4f..671b781bb 100644
--- a/projects/common/xilinx/sys_dmafifo.tcl
+++ b/projects/common/xilinx/sys_dmafifo.tcl
@@ -67,6 +67,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
   create_bd_pin -dir I  -from [expr ($data_width-1)] -to 0 dma_data
   create_bd_pin -dir I  dma_xfer_req
   create_bd_pin -dir I  dma_xfer_last
+  create_bd_pin -dir I  dac_fifo_bypass
 
   create_bd_pin -dir I  dac_clk
   create_bd_pin -dir I  dac_valid
@@ -86,6 +87,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
   ad_connect  dma_xfer_last util_dacfifo/dma_xfer_last
   ad_connect  dac_valid util_dacfifo/dac_valid
   ad_connect  dac_data util_dacfifo/dac_data
+  ad_connect  dac_fifo_bypass util_dacfifo/dac_fifo_bypass
 
   current_bd_instance $c_instance
 }

From 65b2e5195821e7f6a42d55fe5e45cc8452109004 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Mar 2016 12:49:30 -0400
Subject: [PATCH 115/972] common/mmcm: add another clock

---
 library/common/ad_mmcm_drp.v   | 24 +++++++++++++++++++-----
 library/common/ad_serdes_clk.v | 18 +++++++++++++++---
 2 files changed, 34 insertions(+), 8 deletions(-)

diff --git a/library/common/ad_mmcm_drp.v b/library/common/ad_mmcm_drp.v
index 3c9cf2302..e9d5f0e37 100644
--- a/library/common/ad_mmcm_drp.v
+++ b/library/common/ad_mmcm_drp.v
@@ -44,10 +44,11 @@ module ad_mmcm_drp (
 
   clk,
   clk2,
-  mmcm_rst,
   clk_sel,
+  mmcm_rst,
   mmcm_clk_0,
   mmcm_clk_1,
+  mmcm_clk_2,
 
   // drp interface
 
@@ -72,18 +73,21 @@ module ad_mmcm_drp (
   parameter   MMCM_VCO_DIV  = 6;
   parameter   MMCM_VCO_MUL = 12.000;
   parameter   MMCM_CLK0_DIV = 2.000;
-  parameter   MMCM_CLK0_PHASE = 0.000 ;
+  parameter   MMCM_CLK0_PHASE = 0.000;
   parameter   MMCM_CLK1_DIV = 6;
   parameter   MMCM_CLK1_PHASE = 0.000;
+  parameter   MMCM_CLK2_DIV = 2.000;
+  parameter   MMCM_CLK2_PHASE = 0.000;
 
   // clocks
 
   input           clk;
   input           clk2;
-  input           mmcm_rst;
   input           clk_sel;
+  input           mmcm_rst;
   output          mmcm_clk_0;
   output          mmcm_clk_1;
+  output          mmcm_clk_2;
 
   // drp interface
 
@@ -110,6 +114,7 @@ module ad_mmcm_drp (
   wire            mmcm_fb_clk_s;
   wire            mmcm_clk_0_s;
   wire            mmcm_clk_1_s;
+  wire            mmcm_clk_2_s;
   wire            mmcm_locked_s;
   wire    [15:0]  up_drp_rdata_s;
   wire            up_drp_ready_s;
@@ -152,6 +157,10 @@ module ad_mmcm_drp (
     .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
     .CLKOUT1_DUTY_CYCLE (0.500),
     .CLKOUT1_USE_FINE_PS ("FALSE"),
+    .CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
+    .CLKOUT2_PHASE (MMCM_CLK2_PHASE),
+    .CLKOUT2_DUTY_CYCLE (0.500),
+    .CLKOUT2_USE_FINE_PS ("FALSE"),
     .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
     .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
     .REF_JITTER1 (0.010))
@@ -161,6 +170,7 @@ module ad_mmcm_drp (
     .CLKFBOUT (mmcm_fb_clk_s),
     .CLKOUT0 (mmcm_clk_0_s),
     .CLKOUT1 (mmcm_clk_1_s),
+    .CLKOUT2 (mmcm_clk_2_s),
     .LOCKED (mmcm_locked_s),
     .DCLK (up_clk),
     .DEN (up_drp_sel),
@@ -172,7 +182,6 @@ module ad_mmcm_drp (
     .CLKFBOUTB (),
     .CLKOUT0B (),
     .CLKOUT1B (),
-    .CLKOUT2 (),
     .CLKOUT2B (),
     .CLKOUT3 (),
     .CLKOUT3B (),
@@ -209,6 +218,10 @@ module ad_mmcm_drp (
     .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
     .CLKOUT1_DUTY_CYCLE (0.500),
     .CLKOUT1_USE_FINE_PS ("FALSE"),
+    .CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
+    .CLKOUT2_PHASE (MMCM_CLK2_PHASE),
+    .CLKOUT2_DUTY_CYCLE (0.500),
+    .CLKOUT2_USE_FINE_PS ("FALSE"),
     .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
     .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
     .REF_JITTER1 (0.010))
@@ -218,6 +231,7 @@ module ad_mmcm_drp (
     .CLKFBOUT (mmcm_fb_clk_s),
     .CLKOUT0 (mmcm_clk_0_s),
     .CLKOUT1 (mmcm_clk_1_s),
+    .CLKOUT2 (mmcm_clk_2_s),
     .LOCKED (mmcm_locked_s),
     .DCLK (up_clk),
     .DEN (up_drp_sel),
@@ -229,7 +243,6 @@ module ad_mmcm_drp (
     .CLKFBOUTB (),
     .CLKOUT0B (),
     .CLKOUT1B (),
-    .CLKOUT2 (),
     .CLKOUT2B (),
     .CLKOUT3 (),
     .CLKOUT3B (),
@@ -252,6 +265,7 @@ module ad_mmcm_drp (
   BUFG i_fb_clk_bufg  (.I (mmcm_fb_clk_s),  .O (bufg_fb_clk_s));
   BUFG i_clk_0_bufg   (.I (mmcm_clk_0_s),   .O (mmcm_clk_0)); 
   BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
+  BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
 
 endmodule
 
diff --git a/library/common/ad_serdes_clk.v b/library/common/ad_serdes_clk.v
index 7022ae785..bbcd0c8ef 100644
--- a/library/common/ad_serdes_clk.v
+++ b/library/common/ad_serdes_clk.v
@@ -48,6 +48,7 @@ module ad_serdes_clk (
 
   clk,
   div_clk,
+  out_clk,
 
   // drp interface
 
@@ -80,6 +81,7 @@ module ad_serdes_clk (
 
   output          clk;
   output          div_clk;
+  output          out_clk;
 
   // drp interface
 
@@ -108,17 +110,24 @@ module ad_serdes_clk (
   if (MMCM_OR_BUFR_N == 1) begin
   ad_mmcm_drp #(
     .MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE),
-    .MMCM_CLKIN_PERIOD  (MMCM_CLKIN_PERIOD),
-    .MMCM_VCO_DIV  (MMCM_VCO_DIV),
+    .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
+    .MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD),
+    .MMCM_VCO_DIV (MMCM_VCO_DIV),
     .MMCM_VCO_MUL (MMCM_VCO_MUL),
     .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
-    .MMCM_CLK1_DIV (MMCM_CLK1_DIV))
+    .MMCM_CLK0_PHASE (0.0),
+    .MMCM_CLK1_DIV (MMCM_CLK1_DIV),
+    .MMCM_CLK1_PHASE (0.0),
+    .MMCM_CLK2_DIV (MMCM_CLK0_DIV),
+    .MMCM_CLK2_PHASE (90.0))
   i_mmcm_drp (
     .clk (clk_in_s),
+    .clk2 (1'b0),
     .clk_sel (1'b1),
     .mmcm_rst (mmcm_rst),
     .mmcm_clk_0 (clk),
     .mmcm_clk_1 (div_clk),
+    .mmcm_clk_2 (out_clk),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),
@@ -138,6 +147,7 @@ module ad_serdes_clk (
     .O (clk));
 
   assign div_clk = clk;
+  assign out_clk = clk;
   end
 
   if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 1)) begin
@@ -150,6 +160,8 @@ module ad_serdes_clk (
     .CE (1'b1),
     .I (clk_in_s),
     .O (div_clk));
+
+  assign out_clk = clk;
   end
   endgenerate
 

From 74408881c6d5b11b6a0b6fbb693481b11c3b4406 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Mar 2016 12:50:02 -0400
Subject: [PATCH 116/972] axi_ad9122: optional clock out control

---
 library/axi_ad9122/axi_ad9122.v    | 12 ++++++++++-
 library/axi_ad9122/axi_ad9122_if.v | 34 +++++++++++++++++++-----------
 2 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v
index 4ac740ae0..9239c0575 100644
--- a/library/axi_ad9122/axi_ad9122.v
+++ b/library/axi_ad9122/axi_ad9122.v
@@ -95,6 +95,11 @@ module axi_ad9122 (
   parameter   DEVICE_TYPE = 0;
   parameter   SERDES_OR_DDR_N = 1;
   parameter   MMCM_OR_BUFIO_N = 1;
+  parameter   MMCM_CLKIN_PERIOD = 1.667;
+  parameter   MMCM_VCO_DIV = 2;
+  parameter   MMCM_VCO_MUL = 4;
+  parameter   MMCM_CLK0_DIV = 2;
+  parameter   MMCM_CLK1_DIV = 8;
   parameter   DAC_DATAPATH_DISABLE = 0;
   parameter   IO_DELAY_GROUP = "dev_if_delay_group";
 
@@ -200,7 +205,12 @@ module axi_ad9122 (
   axi_ad9122_if #(
     .DEVICE_TYPE (DEVICE_TYPE),
     .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
-    .MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N))
+    .MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N),
+    .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
+    .MMCM_VCO_DIV (MMCM_VCO_DIV),
+    .MMCM_VCO_MUL (MMCM_VCO_MUL),
+    .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
+    .MMCM_CLK1_DIV (MMCM_CLK1_DIV))
   i_if (
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_in_n (dac_clk_in_n),
diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v
index cb7a437d7..598978c47 100644
--- a/library/axi_ad9122/axi_ad9122_if.v
+++ b/library/axi_ad9122/axi_ad9122_if.v
@@ -100,6 +100,11 @@ module axi_ad9122_if (
   parameter   DEVICE_TYPE = 0;
   parameter   SERDES_OR_DDR_N = 1;
   parameter   MMCM_OR_BUFIO_N = 1;
+  parameter   MMCM_CLKIN_PERIOD = 1.667;
+  parameter   MMCM_VCO_DIV = 6;
+  parameter   MMCM_VCO_MUL = 12;
+  parameter   MMCM_CLK0_DIV = 2;
+  parameter   MMCM_CLK1_DIV = 8;
   parameter   IO_DELAY_GROUP = "dac_if_delay_group";
 
   // dac interface
@@ -161,6 +166,10 @@ module axi_ad9122_if (
   reg             dac_status_m1 = 'd0;
   reg             dac_status = 'd0;
 
+  // internal signals
+
+  wire            dac_out_clk;
+
   // dac status
 
   always @(posedge dac_div_clk) begin
@@ -177,8 +186,8 @@ module axi_ad9122_if (
 
   ad_serdes_out #(
     .DEVICE_TYPE (DEVICE_TYPE),
-    .SERDES_OR_DDR_N(SERDES_OR_DDR_N),
-    .DATA_WIDTH(16))
+    .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
+    .DATA_WIDTH (16))
   i_serdes_out_data (
     .rst (dac_rst),
     .clk (dac_clk),
@@ -198,8 +207,8 @@ module axi_ad9122_if (
   
   ad_serdes_out #(
     .DEVICE_TYPE (DEVICE_TYPE),
-    .SERDES_OR_DDR_N(SERDES_OR_DDR_N),
-    .DATA_WIDTH(1))
+    .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
+    .DATA_WIDTH (1))
   i_serdes_out_frame (
     .rst (dac_rst),
     .clk (dac_clk),
@@ -219,11 +228,11 @@ module axi_ad9122_if (
   
   ad_serdes_out #(
     .DEVICE_TYPE (DEVICE_TYPE),
-    .SERDES_OR_DDR_N(SERDES_OR_DDR_N),
-    .DATA_WIDTH(1))
+    .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
+    .DATA_WIDTH (1))
   i_serdes_out_clk (
     .rst (dac_rst),
-    .clk (dac_clk),
+    .clk (dac_out_clk),
     .div_clk (dac_div_clk),
     .data_s0 (1'b1),
     .data_s1 (1'b0),
@@ -242,17 +251,18 @@ module axi_ad9122_if (
     .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
     .MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N),
     .MMCM_DEVICE_TYPE (DEVICE_TYPE),
-    .MMCM_CLKIN_PERIOD (1.667),
-    .MMCM_VCO_DIV (6),
-    .MMCM_VCO_MUL (12),
-    .MMCM_CLK0_DIV (2),
-    .MMCM_CLK1_DIV (8))
+    .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
+    .MMCM_VCO_DIV (MMCM_VCO_DIV),
+    .MMCM_VCO_MUL (MMCM_VCO_MUL),
+    .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
+    .MMCM_CLK1_DIV (MMCM_CLK1_DIV))
   i_serdes_clk (
     .mmcm_rst (mmcm_rst),
     .clk_in_p (dac_clk_in_p),
     .clk_in_n (dac_clk_in_n),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
+    .out_clk (dac_out_clk),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),

From de4da6726b8b1e0569dd0afa4309922a73640b3d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Mar 2016 12:50:29 -0400
Subject: [PATCH 117/972] axi_clkgen: port updates on mmcm

---
 library/axi_clkgen/axi_clkgen.v | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v
index 296f94b02..8d18ee7c7 100644
--- a/library/axi_clkgen/axi_clkgen.v
+++ b/library/axi_clkgen/axi_clkgen.v
@@ -79,6 +79,8 @@ module axi_clkgen (
   parameter   CLK0_PHASE = 0.000;
   parameter   CLK1_DIV = 6;
   parameter   CLK1_PHASE = 0.000;
+  parameter   CLK2_DIV = 6;
+  parameter   CLK2_PHASE = 0.000;
 
   // clocks
 
@@ -208,10 +210,11 @@ module axi_clkgen (
   i_mmcm_drp (
     .clk (clk),
     .clk2 (clk2),
-    .mmcm_rst (mmcm_rst),
     .clk_sel(clk_sel),
+    .mmcm_rst (mmcm_rst),
     .mmcm_clk_0 (clk_0),
     .mmcm_clk_1 (clk_1),
+    .mmcm_clk_2 (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel_s),

From 46eddd04bebced9a557813130f4f0f797248c25f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Mar 2016 12:50:48 -0400
Subject: [PATCH 118/972] library: port updates on mmcm

---
 library/axi_ad9434/axi_ad9434_if.v | 1 +
 library/axi_ad9684/axi_ad9684_if.v | 1 +
 2 files changed, 2 insertions(+)

diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v
index 3475665af..88eaff972 100644
--- a/library/axi_ad9434/axi_ad9434_if.v
+++ b/library/axi_ad9434/axi_ad9434_if.v
@@ -222,6 +222,7 @@ module axi_ad9434_if (
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk_in),
     .div_clk (adc_div_clk),
+    .out_clk (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),
diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v
index 530a6631c..14f49babe 100644
--- a/library/axi_ad9684/axi_ad9684_if.v
+++ b/library/axi_ad9684/axi_ad9684_if.v
@@ -263,6 +263,7 @@ module axi_ad9684_if (
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk_in),
     .div_clk (adc_div_clk),
+    .out_clk (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),

From a1c2c61884f3f2ae7a7bb7a8df5c57ad0316f758 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 24 Mar 2016 11:46:33 +0200
Subject: [PATCH 119/972] ad7616_sdz: Update the IOBUF instance names

---
 projects/ad7616_sdz/zc706/system_top_pi.v |  6 +++---
 projects/ad7616_sdz/zc706/system_top_si.v |  4 ++--
 projects/ad7616_sdz/zed/system_top_pi.v   | 10 +++++-----
 projects/ad7616_sdz/zed/system_top_si.v   |  8 ++++----
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v
index b3c8ae8f8..39cd1e6ed 100644
--- a/projects/ad7616_sdz/zc706/system_top_pi.v
+++ b/projects/ad7616_sdz/zc706/system_top_pi.v
@@ -157,7 +157,7 @@ module system_top (
 
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
     .dio_t (gpio_t[43:32]),
     .dio_i (gpio_o[43:32]),
     .dio_o (gpio_i[43:32]),
@@ -171,7 +171,7 @@ module system_top (
 
   generate
     for (i = 0; i < 16; i = i + 1) begin: adc_db_io
-      ad_iobuf i_adc_db (
+      ad_iobuf i_iobuf_adc_db (
         .dio_t(adc_db_t),
         .dio_i(adc_db_o[i]),
         .dio_o(adc_db_i[i]),
@@ -181,7 +181,7 @@ module system_top (
 
   ad_iobuf #(
     .DATA_WIDTH(15)
-  ) i_gpio_bd (
+  ) i_iobuf_gpio (
     .dio_t(gpio_t[14:0]),
     .dio_i(gpio_o[14:0]),
     .dio_o(gpio_i[14:0]),
diff --git a/projects/ad7616_sdz/zc706/system_top_si.v b/projects/ad7616_sdz/zc706/system_top_si.v
index 239803d13..a16b522d8 100644
--- a/projects/ad7616_sdz/zc706/system_top_si.v
+++ b/projects/ad7616_sdz/zc706/system_top_si.v
@@ -153,7 +153,7 @@ module system_top (
 
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
     .dio_t (gpio_t[43:32]),
     .dio_i (gpio_o[43:32]),
     .dio_o (gpio_i[43:32]),
@@ -167,7 +167,7 @@ module system_top (
 
   ad_iobuf #(
     .DATA_WIDTH(15)
-  ) i_gpio_bd (
+  ) i_iobuf_gpio (
     .dio_t(gpio_t[14:0]),
     .dio_i(gpio_o[14:0]),
     .dio_o(gpio_i[14:0]),
diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v
index 9337f60e7..8db22ae45 100644
--- a/projects/ad7616_sdz/zed/system_top_pi.v
+++ b/projects/ad7616_sdz/zed/system_top_pi.v
@@ -184,7 +184,7 @@ module system_top (
 
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
     .dio_t (gpio_t[43:32]),
     .dio_i (gpio_o[43:32]),
     .dio_o (gpio_i[43:32]),
@@ -198,7 +198,7 @@ module system_top (
 
   generate
     for (i = 0; i < 16; i = i + 1) begin: adc_db_io
-      ad_iobuf i_adc_db (
+      ad_iobuf i_iobuf_adc_db (
         .dio_t(adc_db_t),
         .dio_i(adc_db_o[i]),
         .dio_o(adc_db_i[i]),
@@ -208,7 +208,7 @@ module system_top (
 
   ad_iobuf #(
     .DATA_WIDTH(32)
-  ) i_iobuf (
+  ) i_iobuf_gpio (
     .dio_t(gpio_t[31:0]),
     .dio_i(gpio_o[31:0]),
     .dio_o(gpio_i[31:0]),
@@ -216,7 +216,7 @@ module system_top (
 
   ad_iobuf #(
     .DATA_WIDTH(2)
-  ) i_iic_mux_scl (
+  ) i_iobuf_iic_mux_scl (
     .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
     .dio_i(iic_mux_scl_o_s),
     .dio_o(iic_mux_scl_i_s),
@@ -224,7 +224,7 @@ module system_top (
 
   ad_iobuf #(
     .DATA_WIDTH(2)
-  ) i_iic_mux_sda (
+  ) i_iobuf_iic_mux_sda (
     .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
     .dio_i(iic_mux_sda_o_s),
     .dio_o(iic_mux_sda_i_s),
diff --git a/projects/ad7616_sdz/zed/system_top_si.v b/projects/ad7616_sdz/zed/system_top_si.v
index fb168685e..25406e7ae 100644
--- a/projects/ad7616_sdz/zed/system_top_si.v
+++ b/projects/ad7616_sdz/zed/system_top_si.v
@@ -180,7 +180,7 @@ module system_top (
 
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_adc_iobuf (
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
     .dio_t (gpio_t[43:32]),
     .dio_i (gpio_o[43:32]),
     .dio_o (gpio_i[43:32]),
@@ -194,7 +194,7 @@ module system_top (
 
   ad_iobuf #(
     .DATA_WIDTH(32)
-  ) i_gpio_iobuf (
+  ) i_iobuf_gpio (
     .dio_t(gpio_t[31:0]),
     .dio_i(gpio_o[31:0]),
     .dio_o(gpio_i[31:0]),
@@ -202,7 +202,7 @@ module system_top (
 
   ad_iobuf #(
     .DATA_WIDTH(2)
-  ) i_iic_mux_scl (
+  ) i_iobuf_iic_mux_scl (
     .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
     .dio_i(iic_mux_scl_o_s),
     .dio_o(iic_mux_scl_i_s),
@@ -210,7 +210,7 @@ module system_top (
 
   ad_iobuf #(
     .DATA_WIDTH(2)
-  ) i_iic_mux_sda (
+  ) i_iobuf_iic_mux_sda (
     .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
     .dio_i(iic_mux_sda_o_s),
     .dio_o(iic_mux_sda_i_s),

From 7ce3f6e274450c2f3ad7115aa890d6c7415b10a7 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 24 Mar 2016 13:49:30 +0200
Subject: [PATCH 120/972] ad7616_sdz: Fix system top for parallel interface
 mode.

---
 projects/ad7616_sdz/zc706/system_top_pi.v | 19 +++++--------------
 projects/ad7616_sdz/zed/system_top_pi.v   | 19 +++++--------------
 2 files changed, 10 insertions(+), 28 deletions(-)

diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v
index 39cd1e6ed..eb3987837 100644
--- a/projects/ad7616_sdz/zc706/system_top_pi.v
+++ b/projects/ad7616_sdz/zc706/system_top_pi.v
@@ -87,10 +87,7 @@ module system_top (
   adc_busy,
   adc_seq_en,
   adc_hw_rngsel,
-  adc_chsel,
-  adc_crcen,
-  adc_burst,
-  adc_os);
+  adc_chsel);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -139,9 +136,6 @@ module system_top (
   output          adc_seq_en;
   output  [ 1:0]  adc_hw_rngsel;
   output  [ 2:0]  adc_chsel;
-  output          adc_crcen;
-  output          adc_burst;
-  output  [ 2:0]  adc_os;
 
   // internal signals
 
@@ -158,16 +152,13 @@ module system_top (
   // instantiations
 
   ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
-    .dio_t (gpio_t[43:32]),
-    .dio_i (gpio_o[43:32]),
-    .dio_o (gpio_i[43:32]),
+    .dio_t (gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
+    .dio_i (gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
+    .dio_o (gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
     .dio_p ({adc_reset_n,        // 43
              adc_hw_rngsel,      // 42:41
-             adc_os,             // 40:38
              adc_seq_en,         // 37
-             adc_burst,          // 36
-             adc_chsel,          // 35:33
-             adc_crcen}));       // 32
+             adc_chsel}));       // 35:33
 
   generate
     for (i = 0; i < 16; i = i + 1) begin: adc_db_io
diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v
index 8db22ae45..916f68b50 100644
--- a/projects/ad7616_sdz/zed/system_top_pi.v
+++ b/projects/ad7616_sdz/zed/system_top_pi.v
@@ -97,10 +97,7 @@ module system_top (
   adc_busy,
   adc_seq_en,
   adc_hw_rngsel,
-  adc_chsel,
-  adc_crcen,
-  adc_burst,
-  adc_os);
+  adc_chsel);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -160,9 +157,6 @@ module system_top (
   output          adc_seq_en;
   output  [ 1:0]  adc_hw_rngsel;
   output  [ 2:0]  adc_chsel;
-  output          adc_crcen;
-  output          adc_burst;
-  output  [ 2:0]  adc_os;
 
   // internal signals
 
@@ -185,16 +179,13 @@ module system_top (
   // instantiations
 
   ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
-    .dio_t (gpio_t[43:32]),
-    .dio_i (gpio_o[43:32]),
-    .dio_o (gpio_i[43:32]),
+    .dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
+    .dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
+    .dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
     .dio_p ({adc_reset_n,        // 43
              adc_hw_rngsel,      // 42:41
-             adc_os,             // 40:38
              adc_seq_en,         // 37
-             adc_burst,          // 36
-             adc_chsel,          // 35:33
-             adc_crcen}));       // 32
+             adc_chsel}));       // 35:33
 
   generate
     for (i = 0; i < 16; i = i + 1) begin: adc_db_io

From 255b0ebd40609996d33c552b0211aec2e8df9e3c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 29 Mar 2016 16:50:00 +0300
Subject: [PATCH 121/972] util_dacfifo: Add dac_xfer_out control

The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
---
 library/util_dacfifo/util_dacfifo.v    | 17 +++++++++++++++--
 projects/common/xilinx/sys_dmafifo.tcl |  2 ++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v
index d08c8b833..e73eb0091 100644
--- a/library/util_dacfifo/util_dacfifo.v
+++ b/library/util_dacfifo/util_dacfifo.v
@@ -56,11 +56,13 @@ module util_dacfifo (
   dac_clk,
   dac_valid,
   dac_data,
+  dac_xfer_out,
 
   dac_fifo_bypass
 );
 
   // depth of the FIFO
+
   parameter       ADDRESS_WIDTH = 6;
   parameter       DATA_WIDTH = 128;
 
@@ -81,6 +83,7 @@ module util_dacfifo (
   input                               dac_clk;
   input                               dac_valid;
   output  [(DATA_WIDTH-1):0]          dac_data;
+  output                              dac_xfer_out;
 
   input                               dac_fifo_bypass;
 
@@ -94,12 +97,16 @@ module util_dacfifo (
   reg                                 dma_ready_d = 1'b0;
 
   reg     [(ADDRESS_WIDTH-1):0]       dac_raddr = 'b0;
+  reg                                 dma_xfer_out = 1'b0;
+  reg     [ 2:0]                      dac_xfer_out_m = 3'b0;
 
   // internal wires
+
   wire                                dma_wren;
   wire    [(DATA_WIDTH-1):0]          dac_data_s;
 
   // write interface
+
   always @(posedge dma_clk) begin
     if(dma_rst == 1'b1) begin
       dma_ready_d <= 1'b0;
@@ -114,28 +121,34 @@ module util_dacfifo (
     if(dma_rst == 1'b1) begin
       dma_waddr <= 'b0;
       dma_lastaddr <= 'b0;
+      dma_xfer_out <= 1'b0;
     end else begin
       if (dma_valid && dma_xfer_req) begin
         dma_waddr <= dma_waddr + 1;
+        dma_xfer_out <= 1'b0;
       end
       if (dma_xfer_last) begin
         dma_lastaddr <= dma_waddr;
         dma_waddr <= 'b0;
+        dma_xfer_out <= 1'b1;
       end
     end
   end
 
   assign dma_wren = dma_valid & dma_xfer_req;
 
-  // read interface
-
   // sync lastaddr to dac clock domain
+
   always @(posedge dac_clk) begin
     dma_lastaddr_d <= dma_lastaddr;
     dma_lastaddr_2d <= dma_lastaddr_d;
+    dac_xfer_out_m <= {dac_xfer_out_m[1:0], dma_xfer_out};
   end
 
+  assign dac_xfer_out = dac_xfer_out_m[2];
+
   // generate dac read address
+
   always @(posedge dac_clk) begin
     if(dac_valid == 1'b1) begin
       if (dma_lastaddr_2d == 'h0) begin
diff --git a/projects/common/xilinx/sys_dmafifo.tcl b/projects/common/xilinx/sys_dmafifo.tcl
index 671b781bb..f6876fd9b 100644
--- a/projects/common/xilinx/sys_dmafifo.tcl
+++ b/projects/common/xilinx/sys_dmafifo.tcl
@@ -72,6 +72,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
   create_bd_pin -dir I  dac_clk
   create_bd_pin -dir I  dac_valid
   create_bd_pin -dir O  -from [expr ($data_width - 1)] -to 0 dac_data
+  create_bd_pin -dir O dac_xfer_out
 
   set util_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:util_dacfifo:1.0 util_dacfifo]
   set_property -dict [list CONFIG.DATA_WIDTH $data_width] $util_dacfifo
@@ -87,6 +88,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
   ad_connect  dma_xfer_last util_dacfifo/dma_xfer_last
   ad_connect  dac_valid util_dacfifo/dac_valid
   ad_connect  dac_data util_dacfifo/dac_data
+  ad_connect  dac_xfer_out util_dacfifo/dac_xfer_out
   ad_connect  dac_fifo_bypass util_dacfifo/dac_fifo_bypass
 
   current_bd_instance $c_instance

From 1fab6ce47742c3582131244b0f5f5e6acdb7f929 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 29 Mar 2016 16:55:33 +0300
Subject: [PATCH 122/972] daq2/common: Add util_dacfifo/dac_xfer_out control

---
 projects/daq2/common/daq2_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index 794f33c09..b84a71984 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -142,6 +142,7 @@ ad_connect  axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1
 ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk
 ad_connect  axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
 ad_connect  axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
+ad_connect  axi_ad9144_upack/dma_xfer_in axi_ad9144_fifo/dac_xfer_out
 ad_connect  sys_cpu_clk axi_ad9144_fifo/dma_clk
 ad_connect  sys_cpu_reset axi_ad9144_fifo/dma_rst
 ad_connect  sys_cpu_clk axi_ad9144_dma/m_axis_aclk

From 7b01cd9ecada5d510af67d3882dff2c1d213d5ff Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 31 Mar 2016 19:42:52 +0300
Subject: [PATCH 123/972] README.md: Update the README

---
 README.md | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/README.md b/README.md
index 7e922767e..d384a3bda 100644
--- a/README.md
+++ b/README.md
@@ -1,18 +1,19 @@
-#HDL Reference Designs
+# HDL Reference Designs
 
-Analog Devices HDL libraries and projects
+[Analog Devices Inc.] HDL libraries and projects
 
-###Tools version:
-- **Xilinx** : [Vivado 2015.2.1]
-- **Altera** : [Quartus 15.0]
+### Branches
 
-###Documentation and support
+Each release has its own branch and master always synced with the latest release. 
+To find out more information about the latest release please check the release notes.
+Every branch, which has **dev** in its name, is a development branch and should handle it accordingly. 
 
-For first time users, it is **highly recommended** to go through our [HDL user guide].
+### [Latest Release Notes]
+### [HDL User Guide]
+### [HDL Help & Support]
 
-For support please visit our [FPGA Reference Designs Support Community] on EngineerZone.
+[HDL User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl
+[HDL Help & Support]:http://ez.analog.com/community/fpga
+[Latest Release Notes]:https://github.com/analogdevicesinc/hdl/releases
+[Analog Devices Inc.]:http://www.analog.com/en/index.html
 
-[Vivado 2015.2.1]:http://www.xilinx.com/content/xilinx/en/downloadNav/vivado-design-tools/2015-2.html
-[Quartus 15.0]:http://dl.altera.com/15.0/?edition=subscription
-[HDL user guide]:http://wiki.analog.com/resources/fpga/docs/hdl
-[FPGA Reference Designs Support Community]:http://ez.analog.com/community/fpga

From 68bc647472ccc0ad79a168f0ea05beb732b91030 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 6 Apr 2016 15:30:27 -0400
Subject: [PATCH 124/972] pzsdr1- ddr board delays update

---
 projects/common/pzsdr1/pzsdr1_system_ps7.tcl | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/projects/common/pzsdr1/pzsdr1_system_ps7.tcl b/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
index fd86195cf..916b5c86b 100755
--- a/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
+++ b/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
@@ -32,12 +32,12 @@ set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF             {0}
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL             {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE               {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE                {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {-0.053}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {-0.059}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {0.065}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {0.066}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.264}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.265}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.330}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.330}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {0.066}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {0.029}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {-0.017}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {-0.038}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.301}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.330}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.314}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.333}                 [get_bd_cells sys_ps7]
 

From bf6ef4e5f314e2ba173b0d74da247f4cb797262c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Apr 2016 15:33:00 -0400
Subject: [PATCH 125/972] board- add disconnect

---
 projects/scripts/adi_board.tcl | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index ea905c85a..c5a5762d8 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -94,6 +94,18 @@ proc ad_connect {p_name_1 p_name_2} {
   }
 }
 
+proc ad_disconnect {p_name_1 p_name_2} {
+
+  set m_name_1 [ad_connect_type $p_name_1]
+  set m_name_2 [ad_connect_type $p_name_2]
+
+  if {[get_property CLASS $m_name_1] eq "bd_net"} {
+    puts "disconnect_bd_net $m_name_1 $m_name_2"
+    disconnect_bd_net $m_name_1 $m_name_2
+    return
+  }
+}
+
 ###################################################################################################
 ###################################################################################################
 

From 7e807d83b16cd58c1e78b78c52de1d8bc2546a22 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Apr 2016 15:58:29 -0400
Subject: [PATCH 126/972] pzsdr1- cmos mode

---
 projects/pzsdr1/ccbrk_cmos/Makefile           |  78 +++++
 projects/pzsdr1/ccbrk_cmos/system_bd.tcl      |  48 +++
 projects/pzsdr1/ccbrk_cmos/system_project.tcl |  18 ++
 projects/pzsdr1/ccbrk_cmos/system_top.v       | 273 ++++++++++++++++++
 4 files changed, 417 insertions(+)
 create mode 100644 projects/pzsdr1/ccbrk_cmos/Makefile
 create mode 100644 projects/pzsdr1/ccbrk_cmos/system_bd.tcl
 create mode 100644 projects/pzsdr1/ccbrk_cmos/system_project.tcl
 create mode 100644 projects/pzsdr1/ccbrk_cmos/system_top.v

diff --git a/projects/pzsdr1/ccbrk_cmos/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile
new file mode 100644
index 000000000..9c23f8e0a
--- /dev/null
+++ b/projects/pzsdr1/ccbrk_cmos/Makefile
@@ -0,0 +1,78 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
+M_DEPS += ../../common/xilinx/sys_wfifo.tcl
+M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
+M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib ccbrk_pzsdr1.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+ccbrk_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr1_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_gpreg
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/pzsdr1/ccbrk_cmos/system_bd.tcl b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
new file mode 100644
index 000000000..4b39a6ded
--- /dev/null
+++ b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
@@ -0,0 +1,48 @@
+
+source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_bd.tcl
+source ../common/ccbrk_bd.tcl
+
+# CMOS Mode 
+
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_n]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_p]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_n]]]
+
+delete_bd_objs [get_bd_ports tx_clk_out_p]
+delete_bd_objs [get_bd_ports tx_clk_out_n]
+delete_bd_objs [get_bd_ports tx_frame_out_p]
+delete_bd_objs [get_bd_ports tx_frame_out_n]
+delete_bd_objs [get_bd_ports tx_data_out_p]
+delete_bd_objs [get_bd_ports tx_data_out_n]
+delete_bd_objs [get_bd_ports rx_clk_in_p]
+delete_bd_objs [get_bd_ports rx_clk_in_n]
+delete_bd_objs [get_bd_ports rx_frame_in_p]
+delete_bd_objs [get_bd_ports rx_frame_in_n]
+delete_bd_objs [get_bd_ports rx_data_in_p]
+delete_bd_objs [get_bd_ports rx_data_in_n]
+
+create_bd_port -dir I rx_clk_in
+create_bd_port -dir I rx_frame_in
+create_bd_port -dir I -from 11 -to 0 rx_data_in
+create_bd_port -dir O tx_clk_out
+create_bd_port -dir O tx_frame_out
+create_bd_port -dir O -from 11 -to 0 tx_data_out
+
+set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
+
+ad_connect  rx_clk_in axi_ad9361/rx_clk_in
+ad_connect  rx_frame_in axi_ad9361/rx_frame_in
+ad_connect  rx_data_in axi_ad9361/rx_data_in
+ad_connect  tx_clk_out axi_ad9361/tx_clk_out
+ad_connect  tx_frame_out axi_ad9361/tx_frame_out
+ad_connect  tx_data_out axi_ad9361/tx_data_out
+
diff --git a/projects/pzsdr1/ccbrk_cmos/system_project.tcl b/projects/pzsdr1/ccbrk_cmos/system_project.tcl
new file mode 100644
index 000000000..e251c533c
--- /dev/null
+++ b/projects/pzsdr1/ccbrk_cmos/system_project.tcl
@@ -0,0 +1,18 @@
+
+
+
+source ../../scripts/adi_env.tcl 
+source $ad_hdl_dir/projects/scripts/adi_project.tcl 
+source $ad_hdl_dir/projects/scripts/adi_board.tcl 
+
+adi_project_create ccbrk_cmos_pzsdr1
+adi_project_files ccbrk_cmos_pzsdr1 [list \
+  "system_top.v" \
+  "../ccbrk/system_constr.xdc"\
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc" ]
+
+adi_project_run ccbrk_cmos_pzsdr1
+
+
diff --git a/projects/pzsdr1/ccbrk_cmos/system_top.v b/projects/pzsdr1/ccbrk_cmos/system_top.v
new file mode 100644
index 000000000..5407b1081
--- /dev/null
+++ b/projects/pzsdr1/ccbrk_cmos/system_top.v
@@ -0,0 +1,273 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  iic_scl,
+  iic_sda,
+
+  gpio_bd,
+
+  rx_clk_in,
+  rx_frame_in,
+  rx_data_in,
+  tx_clk_out,
+  tx_frame_out,
+  tx_data_out,
+  tx_gnd,
+
+  enable,
+  txnrx,
+  clk_out,
+
+  gpio_clksel,
+  gpio_resetb,
+  gpio_sync,
+  gpio_en_agc,
+  gpio_ctl,
+  gpio_status,
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  gp_out,
+  gp_in,
+  gp_in_mio,
+  gp_in_open);
+
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  inout   [ 3:0]  gpio_bd;
+
+  input           rx_clk_in;
+  input           rx_frame_in;
+  input   [11:0]  rx_data_in;
+  output          tx_clk_out;
+  output          tx_frame_out;
+  output  [11:0]  tx_data_out;
+  output  [ 1:0]  tx_gnd;
+
+  output          enable;
+  output          txnrx;
+  input           clk_out;
+
+  inout           gpio_clksel;
+  inout           gpio_resetb;
+  inout           gpio_sync;
+  inout           gpio_en_agc;
+  inout   [ 3:0]  gpio_ctl;
+  inout   [ 7:0]  gpio_status;
+
+  output          spi_csn;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  output  [26:0]  gp_out;
+  input   [26:0]  gp_in;
+  input   [ 2:0]  gp_in_mio;
+  input   [ 4:0]  gp_in_open;
+
+  // internal signals
+
+  wire    [63:0]  gp_out_s;
+  wire    [63:0]  gp_in_s;
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+
+  assign tx_gnd = 2'd0;
+
+  assign gp_out[26:0] = gp_out_s[26:0];
+  assign gp_in_s[34:30] = gp_in_open;
+  assign gp_in_s[29:27] = gp_in_mio;
+  assign gp_in_s[26: 0] = gp_in;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
+    .dio_t ({gpio_t[51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[51], gpio_i[46:32]}),
+    .dio_p ({ gpio_clksel,        // 51:51
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_bd (
+    .dio_t (gpio_t[3:0]),
+    .dio_i (gpio_o[3:0]),
+    .dio_o (gpio_i[3:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gp_in_0 (gp_in_s[31:0]),
+    .gp_in_1 (gp_in_s[63:32]),
+    .gp_out_0 (gp_out_s[31:0]),
+    .gp_out_1 (gp_out_s[63:32]),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .otg_vbusoc (1'b0),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in (rx_clk_in),
+    .rx_data_in (rx_data_in),
+    .rx_frame_in (rx_frame_in),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
+    .tx_clk_out (tx_clk_out),
+    .tx_data_out (tx_data_out),
+    .tx_frame_out (tx_frame_out),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 8e689f459435db05508dd48cc51171117c8c32bb Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Apr 2016 16:00:18 -0400
Subject: [PATCH 127/972] pzsdr1- lvds/cmos constraints

---
 .../pzsdr1/pzsdr1_cmos_system_constr.xdc      | 80 +++++++++++++++++++
 .../pzsdr1/pzsdr1_lvds_system_constr.xdc      | 80 +++++++++++++++++++
 2 files changed, 160 insertions(+)
 create mode 100644 projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
 create mode 100644 projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc

diff --git a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
new file mode 100644
index 000000000..e5b625de0
--- /dev/null
+++ b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
@@ -0,0 +1,80 @@
+
+# constraints
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35        
+set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35        
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35        
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35        
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35        
+set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35        
+set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35    
+set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35    
+set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35             
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35             
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35        
+set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35        
+set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35             
+set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35        
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35       
+set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35       
+set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35    
+set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35    
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35  
+set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35  
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35  
+set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35  
+set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35            
+set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35            
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35       
+set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
+set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
+set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
+
+set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35            
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35       
+set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35       
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35       
+set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35  
+set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35  
+set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35       
+set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35       
+set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34            
+set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34            
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34            
+set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34            
+set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35      
+set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35      
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                       ; ## IO_0_35                  
+set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS25} [get_ports gpio_clksel]                       ; ## IO_0_34                  
+
+set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35        
+set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS25} [get_ports spi_clk]                           ; ## IO_L23N_T3_35        
+set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35  
+set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS25} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35  
+
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS25} [get_ports clk_out]                           ; ## IO_25_35
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  W6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L22N_T3_13              
+set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L22P_T3_13              
+
+# gpio
+
+set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
+set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
+
+# clocks
+
+create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+
diff --git a/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc
new file mode 100644
index 000000000..e5b625de0
--- /dev/null
+++ b/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc
@@ -0,0 +1,80 @@
+
+# constraints
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35        
+set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35        
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35        
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35        
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35        
+set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35        
+set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35    
+set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35    
+set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35             
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35             
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35        
+set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35        
+set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35             
+set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35        
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35       
+set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35       
+set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35    
+set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35    
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35  
+set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35  
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35  
+set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35  
+set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35            
+set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35            
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35       
+set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
+set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
+set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
+
+set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35            
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35       
+set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35       
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35       
+set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35  
+set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35  
+set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35       
+set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35       
+set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34            
+set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34            
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34            
+set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34            
+set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35      
+set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35      
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                       ; ## IO_0_35                  
+set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS25} [get_ports gpio_clksel]                       ; ## IO_0_34                  
+
+set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35        
+set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS25} [get_ports spi_clk]                           ; ## IO_L23N_T3_35        
+set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35  
+set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS25} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35  
+
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS25} [get_ports clk_out]                           ; ## IO_25_35
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  W6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L22N_T3_13              
+set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L22P_T3_13              
+
+# gpio
+
+set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
+set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
+
+# clocks
+
+create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+

From 8a5a5082f35d46bdc033e76e84f259854e25268d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Apr 2016 16:12:09 -0400
Subject: [PATCH 128/972] pzsdr1- io updates

---
 .../pzsdr1/pzsdr1_cmos_system_constr.xdc      | 103 ++++++------------
 .../pzsdr1/pzsdr1_lvds_system_constr.xdc      |  38 -------
 2 files changed, 32 insertions(+), 109 deletions(-)

diff --git a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
index e5b625de0..3f2dddbad 100644
--- a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
+++ b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
@@ -2,79 +2,40 @@
 # constraints
 # ad9361
 
-set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35        
-set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35        
-set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35        
-set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35        
-set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35        
-set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35        
-set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35    
-set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35    
-set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35             
-set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35             
-set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35        
-set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35        
-set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35             
-set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35        
-set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35       
-set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35       
-set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35    
-set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35    
-set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35  
-set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35  
-set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35  
-set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35  
-set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35            
-set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35            
-set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35       
-set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
-set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
-set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
-set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
-set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
+set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVCMOS18} [get_ports rx_clk_in]                         ; ## IO_L12P_T1_MRCC_35       
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVCMOS18} [get_ports rx_frame_in]                       ; ## IO_L7P_T1_AD2P_35        
+set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]                     ; ## IO_L13N_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]                     ; ## IO_L13P_T2_MRCC_35       
+set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]                     ; ## IO_L14N_T2_AD4N_SRCC_35  
+set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]                     ; ## IO_L14P_T2_AD4P_SRCC_35  
+set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]                     ; ## IO_L15N_T2_DQS_AD12N_35  
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]                     ; ## IO_L15P_T2_DQS_AD12P_35  
+set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]                     ; ## IO_L16N_T2_35            
+set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]                     ; ## IO_L16P_T2_35            
+set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]                     ; ## IO_L17N_T2_AD5N_35       
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]                     ; ## IO_L17P_T2_AD5P_35       
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]                    ; ## IO_L18N_T2_AD13N_35      
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]                    ; ## IO_L18P_T2_AD13P_35      
 
-set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35            
-set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35       
-set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35       
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35       
-set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35  
-set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35  
-set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35       
-set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35       
-set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34            
-set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34            
-set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34            
-set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34            
-set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35      
-set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35      
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                       ; ## IO_0_35                  
-set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS25} [get_ports gpio_clksel]                       ; ## IO_0_34                  
-
-set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35        
-set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS25} [get_ports spi_clk]                           ; ## IO_L23N_T3_35        
-set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35  
-set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS25} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35  
-
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS25} [get_ports clk_out]                           ; ## IO_25_35
-
-# iic
-
-set_property  -dict {PACKAGE_PIN  W6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L22N_T3_13              
-set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L22P_T3_13              
-
-# gpio
-
-set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
-set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]                        ; ## IO_L8P_T1_AD10P_35       
+set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]                      ; ## IO_L9P_T1_DQS_AD3P_35    
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]                    ; ## IO_L1N_T0_AD0N_35        
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]                    ; ## IO_L1P_T0_AD0P_35        
+set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]                    ; ## IO_L2N_T0_AD8N_35        
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]                    ; ## IO_L2P_T0_AD8P_35        
+set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]                    ; ## IO_L3N_T0_DQS_AD1N_35    
+set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]                    ; ## IO_L3P_T0_DQS_AD1P_35    
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]                    ; ## IO_L4N_T0_35             
+set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]                    ; ## IO_L4P_T0_35             
+set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]                    ; ## IO_L5N_T0_AD9N_35        
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]                    ; ## IO_L5P_T0_AD9P_35        
+set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]                   ; ## IO_L6N_T0_VREF_35        
+set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]                   ; ## IO_L6P_T0_35             
 
+set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]]                         ; ## IO_L8N_T1_AD10N_35       
+set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]]                         ; ## IO_L9N_T1_DQS_AD3N_35    
 # clocks
 
-create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
-create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+create_clock -name rx_clk       -period  8 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
 
diff --git a/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc
index e5b625de0..73bd9923e 100644
--- a/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc
+++ b/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc
@@ -34,44 +34,6 @@ set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS_25}  [get_ports tx_data_o
 set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
 set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
 set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
-set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
-set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
-
-set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35            
-set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35       
-set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35       
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35       
-set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35  
-set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35  
-set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35       
-set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35       
-set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34            
-set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34            
-set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34            
-set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34            
-set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35      
-set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35      
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                       ; ## IO_0_35                  
-set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS25} [get_ports gpio_clksel]                       ; ## IO_0_34                  
-
-set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35        
-set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS25} [get_ports spi_clk]                           ; ## IO_L23N_T3_35        
-set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35  
-set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS25} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35  
-
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS25} [get_ports clk_out]                           ; ## IO_25_35
-
-# iic
-
-set_property  -dict {PACKAGE_PIN  W6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L22N_T3_13              
-set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L22P_T3_13              
-
-# gpio
-
-set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
-set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
 
 # clocks
 

From 736bbdd95a2a3a41d4961a864c21609c5a508106 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Apr 2016 16:12:21 -0400
Subject: [PATCH 129/972] pzsdr1- io updates

---
 .../common/pzsdr1/pzsdr1_system_constr.xdc    | 37 -------------------
 1 file changed, 37 deletions(-)

diff --git a/projects/common/pzsdr1/pzsdr1_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
index e5b625de0..7bf9c821c 100644
--- a/projects/common/pzsdr1/pzsdr1_system_constr.xdc
+++ b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
@@ -2,38 +2,6 @@
 # constraints
 # ad9361
 
-set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35        
-set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35        
-set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35        
-set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35        
-set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35        
-set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35        
-set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35    
-set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35    
-set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35             
-set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35             
-set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35        
-set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35        
-set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35             
-set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35        
-set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35       
-set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35       
-set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35    
-set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35    
-set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35  
-set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35  
-set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35  
-set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35  
-set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35            
-set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35            
-set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35       
-set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
-set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
-set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
 set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
 set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
 
@@ -73,8 +41,3 @@ set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1
 set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
 set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
 
-# clocks
-
-create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
-create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
-

From 3006c5a2233df2e7099e12c5a724e3dd7b87ec98 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Apr 2016 16:14:59 -0400
Subject: [PATCH 130/972] make updates

---
 projects/ad6676evb/vc707/Makefile   |  2 ++
 projects/ad6676evb/zc706/Makefile   |  2 ++
 projects/ad7768evb/zed/Makefile     |  2 ++
 projects/ad9265_fmc/zc706/Makefile  |  2 ++
 projects/ad9434_fmc/zc706/Makefile  |  2 ++
 projects/ad9467_fmc/kc705/Makefile  |  2 ++
 projects/ad9467_fmc/zed/Makefile    |  2 ++
 projects/ad9739a_fmc/zc706/Makefile |  2 ++
 projects/adv7511/ac701/Makefile     |  2 ++
 projects/adv7511/kc705/Makefile     |  2 ++
 projects/adv7511/kcu105/Makefile    |  2 ++
 projects/adv7511/mitx045/Makefile   |  2 ++
 projects/adv7511/vc707/Makefile     |  2 ++
 projects/adv7511/zc702/Makefile     |  2 ++
 projects/adv7511/zc706/Makefile     |  2 ++
 projects/adv7511/zed/Makefile       |  2 ++
 projects/cftl_cip/zed/Makefile      |  2 ++
 projects/cftl_std/zed/Makefile      |  2 ++
 projects/cn0363/microzed/Makefile   |  2 ++
 projects/cn0363/zed/Makefile        |  2 ++
 projects/daq1/zc706/Makefile        |  2 ++
 projects/daq2/kc705/Makefile        |  2 ++
 projects/daq2/kcu105/Makefile       |  2 ++
 projects/daq2/vc707/Makefile        |  2 ++
 projects/daq2/zc706/Makefile        |  2 ++
 projects/daq3/kcu105/Makefile       |  2 ++
 projects/daq3/zc706/Makefile        |  2 ++
 projects/fmcadc2/vc707/Makefile     |  2 ++
 projects/fmcadc2/zc706/Makefile     |  2 ++
 projects/fmcadc4/zc706/Makefile     |  2 ++
 projects/fmcadc5/vc707/Makefile     |  2 ++
 projects/fmcjesdadc1/kc705/Makefile |  2 ++
 projects/fmcjesdadc1/vc707/Makefile |  2 ++
 projects/fmcjesdadc1/zc706/Makefile |  2 ++
 projects/fmcomms1/ac701/Makefile    |  2 ++
 projects/fmcomms1/kc705/Makefile    |  2 ++
 projects/fmcomms1/vc707/Makefile    |  2 ++
 projects/fmcomms1/zc702/Makefile    |  2 ++
 projects/fmcomms1/zc706/Makefile    |  2 ++
 projects/fmcomms1/zed/Makefile      |  2 ++
 projects/fmcomms2/ac701/Makefile    |  2 ++
 projects/fmcomms2/kc705/Makefile    |  2 ++
 projects/fmcomms2/mitx045/Makefile  |  2 ++
 projects/fmcomms2/vc707/Makefile    |  2 ++
 projects/fmcomms2/zc702/Makefile    |  2 ++
 projects/fmcomms2/zc706/Makefile    |  2 ++
 projects/fmcomms2/zed/Makefile      |  2 ++
 projects/fmcomms5/zc702/Makefile    |  2 ++
 projects/fmcomms5/zc706/Makefile    |  2 ++
 projects/fmcomms6/zc706/Makefile    |  2 ++
 projects/fmcomms7/zc706/Makefile    |  2 ++
 projects/imageon/zc706/Makefile     |  2 ++
 projects/imageon/zed/Makefile       |  2 ++
 projects/motcon2_fmc/zed/Makefile   |  2 ++
 projects/pzsdr/Makefile             |  3 ++
 projects/pzsdr/ccbrk/Makefile       |  2 ++
 projects/pzsdr/ccbrk_cmos/Makefile  |  2 ++
 projects/pzsdr/ccfmc/Makefile       |  2 ++
 projects/pzsdr/ccpci/Makefile       |  2 ++
 projects/pzsdr1/Makefile            |  3 ++
 projects/pzsdr1/ccbrk/Makefile      |  2 ++
 projects/pzsdr1/ccbrk_cmos/Makefile | 11 ++++---
 projects/usb_fx3/zc706/Makefile     |  2 ++
 projects/usdrx1/a5gt/Makefile       | 47 -----------------------------
 projects/usdrx1/zc706/Makefile      |  2 ++
 65 files changed, 135 insertions(+), 51 deletions(-)

diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile
index 789699d30..5e0c9487c 100644
--- a/projects/ad6676evb/vc707/Makefile
+++ b/projects/ad6676evb/vc707/Makefile
@@ -34,6 +34,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile
index a6cbba810..b11811429 100644
--- a/projects/ad6676evb/zc706/Makefile
+++ b/projects/ad6676evb/zc706/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/ad7768evb/zed/Makefile b/projects/ad7768evb/zed/Makefile
index a9354819e..b14ce41b3 100644
--- a/projects/ad7768evb/zed/Makefile
+++ b/projects/ad7768evb/zed/Makefile
@@ -35,6 +35,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/ad9265_fmc/zc706/Makefile b/projects/ad9265_fmc/zc706/Makefile
index d1dc365b9..9ad95e317 100644
--- a/projects/ad9265_fmc/zc706/Makefile
+++ b/projects/ad9265_fmc/zc706/Makefile
@@ -34,6 +34,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/ad9434_fmc/zc706/Makefile b/projects/ad9434_fmc/zc706/Makefile
index 3f18dcb7a..70d247f5c 100644
--- a/projects/ad9434_fmc/zc706/Makefile
+++ b/projects/ad9434_fmc/zc706/Makefile
@@ -34,6 +34,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/ad9467_fmc/kc705/Makefile b/projects/ad9467_fmc/kc705/Makefile
index b9b6a3516..887838189 100644
--- a/projects/ad9467_fmc/kc705/Makefile
+++ b/projects/ad9467_fmc/kc705/Makefile
@@ -32,6 +32,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/ad9467_fmc/zed/Makefile b/projects/ad9467_fmc/zed/Makefile
index a08832b57..0eee2b11c 100644
--- a/projects/ad9467_fmc/zed/Makefile
+++ b/projects/ad9467_fmc/zed/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/ad9739a_fmc/zc706/Makefile b/projects/ad9739a_fmc/zc706/Makefile
index f9e98a2b3..481327975 100644
--- a/projects/ad9739a_fmc/zc706/Makefile
+++ b/projects/ad9739a_fmc/zc706/Makefile
@@ -33,6 +33,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile
index 16e4a1588..0dfca3289 100644
--- a/projects/adv7511/ac701/Makefile
+++ b/projects/adv7511/ac701/Makefile
@@ -32,6 +32,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adv7511/kc705/Makefile b/projects/adv7511/kc705/Makefile
index 970c44988..69dea3d47 100644
--- a/projects/adv7511/kc705/Makefile
+++ b/projects/adv7511/kc705/Makefile
@@ -32,6 +32,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile
index 7793cadb1..9a09b9f4f 100644
--- a/projects/adv7511/kcu105/Makefile
+++ b/projects/adv7511/kcu105/Makefile
@@ -32,6 +32,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile
index 3c03e7595..80c65e379 100644
--- a/projects/adv7511/mitx045/Makefile
+++ b/projects/adv7511/mitx045/Makefile
@@ -31,6 +31,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adv7511/vc707/Makefile b/projects/adv7511/vc707/Makefile
index 9fd0f4623..b347dcd33 100644
--- a/projects/adv7511/vc707/Makefile
+++ b/projects/adv7511/vc707/Makefile
@@ -32,6 +32,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adv7511/zc702/Makefile b/projects/adv7511/zc702/Makefile
index 6c520c266..876158ecd 100644
--- a/projects/adv7511/zc702/Makefile
+++ b/projects/adv7511/zc702/Makefile
@@ -29,6 +29,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adv7511/zc706/Makefile b/projects/adv7511/zc706/Makefile
index 3c4655c04..d00baa5e9 100644
--- a/projects/adv7511/zc706/Makefile
+++ b/projects/adv7511/zc706/Makefile
@@ -29,6 +29,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adv7511/zed/Makefile b/projects/adv7511/zed/Makefile
index d0360c3ce..26d233c0b 100644
--- a/projects/adv7511/zed/Makefile
+++ b/projects/adv7511/zed/Makefile
@@ -31,6 +31,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/cftl_cip/zed/Makefile b/projects/cftl_cip/zed/Makefile
index 33231bac1..687b6a0e0 100644
--- a/projects/cftl_cip/zed/Makefile
+++ b/projects/cftl_cip/zed/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/cftl_std/zed/Makefile b/projects/cftl_std/zed/Makefile
index ad3de3c44..55923a3eb 100644
--- a/projects/cftl_std/zed/Makefile
+++ b/projects/cftl_std/zed/Makefile
@@ -33,6 +33,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile
index db68800f7..81bbb9aff 100644
--- a/projects/cn0363/microzed/Makefile
+++ b/projects/cn0363/microzed/Makefile
@@ -40,6 +40,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile
index 0612b089f..e5a811c0c 100644
--- a/projects/cn0363/zed/Makefile
+++ b/projects/cn0363/zed/Makefile
@@ -44,6 +44,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile
index 5e1f57ca2..f0387db04 100644
--- a/projects/daq1/zc706/Makefile
+++ b/projects/daq1/zc706/Makefile
@@ -37,6 +37,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile
index 62d217be4..f5349f760 100644
--- a/projects/daq2/kc705/Makefile
+++ b/projects/daq2/kc705/Makefile
@@ -40,6 +40,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile
index 6c51e2d2d..82e1efb04 100644
--- a/projects/daq2/kcu105/Makefile
+++ b/projects/daq2/kcu105/Makefile
@@ -40,6 +40,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile
index 5ea067321..879592ecc 100644
--- a/projects/daq2/vc707/Makefile
+++ b/projects/daq2/vc707/Makefile
@@ -40,6 +40,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index 710142553..14e469a0c 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -46,6 +46,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
index 160a6170e..256432946 100644
--- a/projects/daq3/kcu105/Makefile
+++ b/projects/daq3/kcu105/Makefile
@@ -40,6 +40,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index 260244908..2e77582c0 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -47,6 +47,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index 261bcba5c..3ae995270 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -37,6 +37,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 034ea3b33..352efb7bc 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -40,6 +40,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index eddeba7f9..e3d0a21a2 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -43,6 +43,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile
index 0b5ddbfe3..38905f714 100644
--- a/projects/fmcadc5/vc707/Makefile
+++ b/projects/fmcadc5/vc707/Makefile
@@ -41,6 +41,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile
index 71ce938e1..7050c879e 100644
--- a/projects/fmcjesdadc1/kc705/Makefile
+++ b/projects/fmcjesdadc1/kc705/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile
index dcfd2dbef..379caa28b 100644
--- a/projects/fmcjesdadc1/vc707/Makefile
+++ b/projects/fmcjesdadc1/vc707/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile
index 72db888ec..e3c623304 100644
--- a/projects/fmcjesdadc1/zc706/Makefile
+++ b/projects/fmcjesdadc1/zc706/Makefile
@@ -38,6 +38,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms1/ac701/Makefile
index 238362c27..9c8a6771c 100644
--- a/projects/fmcomms1/ac701/Makefile
+++ b/projects/fmcomms1/ac701/Makefile
@@ -35,6 +35,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms1/kc705/Makefile b/projects/fmcomms1/kc705/Makefile
index 8a42ea764..5d00e2573 100644
--- a/projects/fmcomms1/kc705/Makefile
+++ b/projects/fmcomms1/kc705/Makefile
@@ -35,6 +35,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms1/vc707/Makefile b/projects/fmcomms1/vc707/Makefile
index fcb4df7c3..8b7b14948 100644
--- a/projects/fmcomms1/vc707/Makefile
+++ b/projects/fmcomms1/vc707/Makefile
@@ -35,6 +35,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms1/zc702/Makefile b/projects/fmcomms1/zc702/Makefile
index 50e606602..c5faab08a 100644
--- a/projects/fmcomms1/zc702/Makefile
+++ b/projects/fmcomms1/zc702/Makefile
@@ -37,6 +37,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms1/zc706/Makefile b/projects/fmcomms1/zc706/Makefile
index db02e1958..5170046cd 100644
--- a/projects/fmcomms1/zc706/Makefile
+++ b/projects/fmcomms1/zc706/Makefile
@@ -37,6 +37,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms1/zed/Makefile b/projects/fmcomms1/zed/Makefile
index 133c9cef9..79e54721f 100644
--- a/projects/fmcomms1/zed/Makefile
+++ b/projects/fmcomms1/zed/Makefile
@@ -39,6 +39,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile
index 5824fd77f..03282725e 100644
--- a/projects/fmcomms2/ac701/Makefile
+++ b/projects/fmcomms2/ac701/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile
index 8a038d42e..ab24ca35e 100644
--- a/projects/fmcomms2/kc705/Makefile
+++ b/projects/fmcomms2/kc705/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile
index 6a2874776..ca53855ce 100644
--- a/projects/fmcomms2/mitx045/Makefile
+++ b/projects/fmcomms2/mitx045/Makefile
@@ -40,6 +40,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile
index a6db3e1a1..46327e71d 100644
--- a/projects/fmcomms2/vc707/Makefile
+++ b/projects/fmcomms2/vc707/Makefile
@@ -35,6 +35,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile
index 5fb3b22c3..439cfe22c 100644
--- a/projects/fmcomms2/zc702/Makefile
+++ b/projects/fmcomms2/zc702/Makefile
@@ -38,6 +38,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile
index cdc3bd188..d3c52de44 100644
--- a/projects/fmcomms2/zc706/Makefile
+++ b/projects/fmcomms2/zc706/Makefile
@@ -37,6 +37,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile
index 03edb148a..9fd8dcfc5 100644
--- a/projects/fmcomms2/zed/Makefile
+++ b/projects/fmcomms2/zed/Makefile
@@ -40,6 +40,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile
index 8bfcc6aeb..bba74f74a 100644
--- a/projects/fmcomms5/zc702/Makefile
+++ b/projects/fmcomms5/zc702/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile
index bac1ce596..5aee574f5 100644
--- a/projects/fmcomms5/zc706/Makefile
+++ b/projects/fmcomms5/zc706/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms6/zc706/Makefile b/projects/fmcomms6/zc706/Makefile
index 15699ccfb..3846e87f0 100644
--- a/projects/fmcomms6/zc706/Makefile
+++ b/projects/fmcomms6/zc706/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index 95fc249f4..2caa37ee7 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -46,6 +46,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile
index 7e0d311db..c4981bb84 100644
--- a/projects/imageon/zc706/Makefile
+++ b/projects/imageon/zc706/Makefile
@@ -34,6 +34,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile
index dc58dca51..1148228ee 100644
--- a/projects/imageon/zed/Makefile
+++ b/projects/imageon/zed/Makefile
@@ -36,6 +36,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/motcon2_fmc/zed/Makefile b/projects/motcon2_fmc/zed/Makefile
index e891adcde..e214e56d0 100644
--- a/projects/motcon2_fmc/zed/Makefile
+++ b/projects/motcon2_fmc/zed/Makefile
@@ -39,6 +39,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/pzsdr/Makefile b/projects/pzsdr/Makefile
index 70c685d18..d1fa90bc2 100644
--- a/projects/pzsdr/Makefile
+++ b/projects/pzsdr/Makefile
@@ -12,6 +12,7 @@ all:
 	-make -C ccfmc all
 	-make -C ccpci all
 	-make -C ccbrk all
+	-make -C ccbrk_cmos all
 
 
 clean: 
@@ -20,6 +21,7 @@ clean:
 	make -C ccfmc clean
 	make -C ccpci clean
 	make -C ccbrk clean
+	make -C ccbrk_cmos clean
 
 
 clean-all:
@@ -28,6 +30,7 @@ clean-all:
 	make -C ccfmc clean-all
 	make -C ccpci clean-all
 	make -C ccbrk clean-all
+	make -C ccbrk_cmos clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile
index 7a8f44653..c9b8d0aa0 100644
--- a/projects/pzsdr/ccbrk/Makefile
+++ b/projects/pzsdr/ccbrk/Makefile
@@ -41,6 +41,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
index 3f52934bb..bc6539695 100644
--- a/projects/pzsdr/ccbrk_cmos/Makefile
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -41,6 +41,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile
index 9f93d9e5b..643a619e6 100644
--- a/projects/pzsdr/ccfmc/Makefile
+++ b/projects/pzsdr/ccfmc/Makefile
@@ -45,6 +45,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci/Makefile
index 5cdeb0619..08fce8aaf 100644
--- a/projects/pzsdr/ccpci/Makefile
+++ b/projects/pzsdr/ccpci/Makefile
@@ -38,6 +38,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile
index fb1938e2f..1f80db157 100644
--- a/projects/pzsdr1/Makefile
+++ b/projects/pzsdr1/Makefile
@@ -8,14 +8,17 @@
 .PHONY: all clean clean-all 
 all:
 	-make -C ccbrk all
+	-make -C ccbrk_cmos all
 
 
 clean: 
 	make -C ccbrk clean
+	make -C ccbrk_cmos clean
 
 
 clean-all:
 	make -C ccbrk clean-all
+	make -C ccbrk_cmos clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
index 9c23f8e0a..9440002db 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -38,6 +38,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/pzsdr1/ccbrk_cmos/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile
index 9c23f8e0a..033e96bfd 100644
--- a/projects/pzsdr1/ccbrk_cmos/Makefile
+++ b/projects/pzsdr1/ccbrk_cmos/Makefile
@@ -7,9 +7,9 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
 M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../ccbrk/system_constr.xdc
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
@@ -17,6 +17,7 @@ M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
 M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
 M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
+M_DEPS += ../../common/pzsdr1/pzsdr1_cmos_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
@@ -38,12 +39,14 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_pzsdr1.sdk/system_top.hdf
+all: lib ccbrk_cmos_pzsdr1.sdk/system_top.hdf
 
 
 clean: 
@@ -60,9 +63,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
+ccbrk_cmos_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr1_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ccbrk_cmos_pzsdr1_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile
index f16d3c455..eb786cf55 100644
--- a/projects/usb_fx3/zc706/Makefile
+++ b/projects/usb_fx3/zc706/Makefile
@@ -32,6 +32,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index e69a48ede..d461204bb 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -7,58 +7,11 @@
 
 M_DEPS += system_project.tcl
 M_DEPS += ../common/usdrx1_spi.v
-M_DEPS += ../common/usdrx1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
 M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v
 M_DEPS += ../../../library/common/altera/ad_jesd_align.v
-M_DEPS += ../../../library/axi_ad9671/axi_ad9671.v
-M_DEPS += ../../../library/axi_ad9671/axi_ad9671_channel.v
-M_DEPS += ../../../library/axi_ad9671/axi_ad9671_hw.tcl
-M_DEPS += ../../../library/axi_ad9671/axi_ad9671_if.v
-M_DEPS += ../../../library/axi_ad9671/axi_ad9671_pnmon.v
-M_DEPS += ../../../library/axi_dmac/2d_transfer.v
-M_DEPS += ../../../library/axi_dmac/address_generator.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
-M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
-M_DEPS += ../../../library/axi_dmac/data_mover.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
-M_DEPS += ../../../library/axi_dmac/inc_id.h
-M_DEPS += ../../../library/axi_dmac/request_arb.v
-M_DEPS += ../../../library/axi_dmac/request_generator.v
-M_DEPS += ../../../library/axi_dmac/resp.h
-M_DEPS += ../../../library/axi_dmac/response_generator.v
-M_DEPS += ../../../library/axi_dmac/response_handler.v
-M_DEPS += ../../../library/axi_dmac/splitter.v
-M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
-M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_jesd_align.v
-M_DEPS += ../../../library/common/ad_mem.v
-M_DEPS += ../../../library/common/ad_pnmon.v
-M_DEPS += ../../../library/common/ad_rst.v
-M_DEPS += ../../../library/common/sync_bits.v
-M_DEPS += ../../../library/common/sync_gray.v
-M_DEPS += ../../../library/common/up_adc_channel.v
-M_DEPS += ../../../library/common/up_adc_common.v
-M_DEPS += ../../../library/common/up_axi.v
-M_DEPS += ../../../library/common/up_clock_mon.v
-M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_xcvr.v
-M_DEPS += ../../../library/common/up_xfer_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
-M_DEPS += ../../../library/util_axis_fifo/address_sync.v
-M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
-M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index 4a0ec0f19..936fbbcfe 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -39,6 +39,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 

From a88ced81362dad9bf3e4cf764df979baa70649c2 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Apr 2016 16:18:29 -0400
Subject: [PATCH 131/972] pzsdr1: lvds/cmos updates

---
 projects/pzsdr1/ccbrk/Makefile           | 1 +
 projects/pzsdr1/ccbrk/system_project.tcl | 6 ++----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
index 9440002db..8c9589b67 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -17,6 +17,7 @@ M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
 M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
 M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
+M_DEPS += ../../common/pzsdr1/pzsdr1_lvds_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
diff --git a/projects/pzsdr1/ccbrk/system_project.tcl b/projects/pzsdr1/ccbrk/system_project.tcl
index 2bab986f0..304860343 100644
--- a/projects/pzsdr1/ccbrk/system_project.tcl
+++ b/projects/pzsdr1/ccbrk/system_project.tcl
@@ -10,10 +10,8 @@ adi_project_files ccbrk_pzsdr1 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
 
 adi_project_run ccbrk_pzsdr1
 

From 69d721526a524acf309f5ec3cbd8d52b581d7330 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 12 Apr 2016 13:21:50 +0300
Subject: [PATCH 132/972] util_dacfifo: Add constraints file

---
 library/util_dacfifo/util_dacfifo_constr.xdc | 2 ++
 library/util_dacfifo/util_dacfifo_ip.tcl     | 5 ++++-
 2 files changed, 6 insertions(+), 1 deletion(-)
 create mode 100644 library/util_dacfifo/util_dacfifo_constr.xdc

diff --git a/library/util_dacfifo/util_dacfifo_constr.xdc b/library/util_dacfifo/util_dacfifo_constr.xdc
new file mode 100644
index 000000000..c8c0111d1
--- /dev/null
+++ b/library/util_dacfifo/util_dacfifo_constr.xdc
@@ -0,0 +1,2 @@
+set_false_path -from [get_cells *dma_lastaddr_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *dma_lastaddr_d_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
diff --git a/library/util_dacfifo/util_dacfifo_ip.tcl b/library/util_dacfifo/util_dacfifo_ip.tcl
index 5bb5d6c1d..50b7f1a08 100644
--- a/library/util_dacfifo/util_dacfifo_ip.tcl
+++ b/library/util_dacfifo/util_dacfifo_ip.tcl
@@ -6,9 +6,12 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create util_dacfifo
 adi_ip_files util_dacfifo [list \
   "$ad_hdl_dir/library/common/ad_mem.v" \
-  "util_dacfifo.v" ]
+  "util_dacfifo.v" \
+  "util_dacfifo_constr.xdc"]
 
 adi_ip_properties_lite util_dacfifo
+adi_ip_constraints util_dacfifo [list \
+  "util_dacfifo_constr.xdc" ]
 
 ipx::remove_all_bus_interface [ipx::current_core]
 ipx::save_core [ipx::current_core]

From 42cd05ab1930fe33b95eeb7c08f4c79483f64e44 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 19 Apr 2016 11:18:30 +0300
Subject: [PATCH 133/972] ad_mem_asym: Add support for more ratios.

Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
---
 library/common/ad_mem_asym.v | 174 ++++++++++++++++++++++-------------
 1 file changed, 108 insertions(+), 66 deletions(-)

diff --git a/library/common/ad_mem_asym.v b/library/common/ad_mem_asym.v
index c4fec8ee6..eb86ab21c 100644
--- a/library/common/ad_mem_asym.v
+++ b/library/common/ad_mem_asym.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,22 +21,25 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
 // ***************************************************************************
 // ***************************************************************************
 
+// A simple asymetric memory. The write and read memory space must have the same size.
+// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH
+
 `timescale 1ns/100ps
 
 module ad_mem_asym (
@@ -50,86 +53,125 @@ module ad_mem_asym (
   addrb,
   doutb);
 
-  parameter   A_ADDRESS_WIDTH =  10;
+  parameter   A_ADDRESS_WIDTH =  8;
   parameter   A_DATA_WIDTH = 256;
-  parameter   B_ADDRESS_WIDTH =   8; 
+  parameter   B_ADDRESS_WIDTH =   10;
   parameter   B_DATA_WIDTH =  64;
 
-  localparam  MEM_SIZE_A = 2**A_ADDRESS_WIDTH;
-  localparam  MEM_SIZE_B = 2**B_ADDRESS_WIDTH;
-  localparam  MEM_SIZE = (MEM_SIZE_A > MEM_SIZE_B) ? MEM_SIZE_A : MEM_SIZE_B;
-  localparam  MEM_RATIO = A_DATA_WIDTH/B_DATA_WIDTH;
+  localparam  MEM_ADDRESS_WIDTH = (A_ADDRESS_WIDTH > B_ADDRESS_WIDTH) ? A_ADDRESS_WIDTH : B_ADDRESS_WIDTH;
+  localparam  MEM_DATA_WIDTH = (A_DATA_WIDTH > B_DATA_WIDTH) ? B_DATA_WIDTH : A_DATA_WIDTH;
+  localparam  MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH;
+  // suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
+  localparam  MEM_RATIO = (A_DATA_WIDTH > B_DATA_WIDTH) ? A_DATA_WIDTH/B_DATA_WIDTH : B_DATA_WIDTH/A_DATA_WIDTH;
+  localparam  MEM_IO_COMP = (A_DATA_WIDTH > B_DATA_WIDTH) ? 1'b1 : 1'b0;
 
   // write interface
 
-  input                       clka;
-  input                       wea;
-  input   [A_ADDRESS_WIDTH-1:0]  addra;
-  input   [A_DATA_WIDTH-1:0]  dina;
+  input                           clka;
+  input                           wea;
+  input   [A_ADDRESS_WIDTH-1:0]   addra;
+  input   [A_DATA_WIDTH-1:0]      dina;
 
   // read interface
 
-  input                       clkb;
-  input   [B_ADDRESS_WIDTH-1:0]  addrb;
-  output  [B_DATA_WIDTH-1:0]  doutb;
+  input                           clkb;
+  input   [B_ADDRESS_WIDTH-1:0]   addrb;
+  output  [B_DATA_WIDTH-1:0]      doutb;
 
   // internal registers
 
-  reg     [B_DATA_WIDTH-1:0]  m_ram[0:MEM_SIZE-1];
-  reg     [B_DATA_WIDTH-1:0]  doutb;
+  reg     [MEM_DATA_WIDTH-1:0]    m_ram[0:MEM_SIZE-1];
+  reg     [B_DATA_WIDTH-1:0]      doutb;
 
-  // write interface
+  // write interface options
 
-  generate
-  if (MEM_RATIO == 1) begin
-  always @(posedge clka) begin
-    if (wea == 1'b1) begin
-      m_ram[addra] <= dina;
+  generate if (MEM_IO_COMP == 0) begin
+    always @(posedge clka) begin
+      if (wea == 1'b1) begin
+        m_ram[addra] <= dina;
+      end
     end
   end
-  end
-
-  if (MEM_RATIO == 2) begin
-  always @(posedge clka) begin
-    if (wea == 1'b1) begin
-      m_ram[{addra, 1'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
-      m_ram[{addra, 1'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
-    end
-  end
-  end
-
-  if (MEM_RATIO == 4) begin
-  always @(posedge clka) begin
-    if (wea == 1'b1) begin
-      m_ram[{addra, 2'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
-      m_ram[{addra, 2'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
-      m_ram[{addra, 2'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)];
-      m_ram[{addra, 2'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)];
-    end
-  end
-  end
-
-  if (MEM_RATIO == 8) begin
-  always @(posedge clka) begin
-    if (wea == 1'b1) begin
-      m_ram[{addra, 3'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
-      m_ram[{addra, 3'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
-      m_ram[{addra, 3'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)];
-      m_ram[{addra, 3'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)];
-      m_ram[{addra, 3'd4}] <= dina[((5*B_DATA_WIDTH)-1):(B_DATA_WIDTH*4)];
-      m_ram[{addra, 3'd5}] <= dina[((6*B_DATA_WIDTH)-1):(B_DATA_WIDTH*5)];
-      m_ram[{addra, 3'd6}] <= dina[((7*B_DATA_WIDTH)-1):(B_DATA_WIDTH*6)];
-      m_ram[{addra, 3'd7}] <= dina[((8*B_DATA_WIDTH)-1):(B_DATA_WIDTH*7)];
-    end
-  end
-  end
   endgenerate
 
-  // read interface
-
-  always @(posedge clkb) begin
-    doutb <= m_ram[addrb];
+  generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 2)) begin
+    always @(posedge clka) begin
+      if (wea == 1'b1) begin
+        m_ram[{addra, 1'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
+        m_ram[{addra, 1'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
+      end
+    end
   end
+  endgenerate
+
+  generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 4)) begin
+    always @(posedge clka) begin
+      if (wea == 1'b1) begin
+        m_ram[{addra, 2'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
+        m_ram[{addra, 2'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
+        m_ram[{addra, 2'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)];
+        m_ram[{addra, 2'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)];
+      end
+    end
+  end
+  endgenerate
+
+  generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 8)) begin
+    always @(posedge clka) begin
+      if (wea == 1'b1) begin
+        m_ram[{addra, 3'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
+        m_ram[{addra, 3'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
+        m_ram[{addra, 3'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)];
+        m_ram[{addra, 3'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)];
+        m_ram[{addra, 3'd4}] <= dina[((5*B_DATA_WIDTH)-1):(B_DATA_WIDTH*4)];
+        m_ram[{addra, 3'd5}] <= dina[((6*B_DATA_WIDTH)-1):(B_DATA_WIDTH*5)];
+        m_ram[{addra, 3'd6}] <= dina[((7*B_DATA_WIDTH)-1):(B_DATA_WIDTH*6)];
+        m_ram[{addra, 3'd7}] <= dina[((8*B_DATA_WIDTH)-1):(B_DATA_WIDTH*7)];
+      end
+    end
+  end
+  endgenerate
+
+  // read interface options
+
+  generate if ((MEM_IO_COMP == 1) || (MEM_RATIO == 1)) begin
+    always @(posedge clkb) begin
+      doutb <= m_ram[addrb];
+    end
+  end
+  endgenerate
+
+  generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 2)) begin
+    always @(posedge clkb) begin
+      doutb <= {m_ram[{addrb, 1'd1}],
+                m_ram[{addrb, 1'd0}]};
+    end
+  end
+  endgenerate
+
+  generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 4)) begin
+    always @(posedge clkb) begin
+      doutb <= {m_ram[{addrb, 2'd3}],
+                m_ram[{addrb, 2'd2}],
+                m_ram[{addrb, 2'd1}],
+                m_ram[{addrb, 2'd0}]};
+    end
+  end
+  endgenerate
+
+  generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 8)) begin
+    always @(posedge clkb) begin
+      doutb <= {m_ram[{addrb, 3'd7}],
+                m_ram[{addrb, 3'd6}],
+                m_ram[{addrb, 3'd5}],
+                m_ram[{addrb, 3'd4}],
+                m_ram[{addrb, 3'd3}],
+                m_ram[{addrb, 3'd2}],
+                m_ram[{addrb, 3'd1}],
+                m_ram[{addrb, 3'd0}]};
+    end
+  end
+  endgenerate
 
 endmodule
 

From e855ef38f4b6958e74122bdac257c211d1a98445 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 19 Apr 2016 11:28:33 +0300
Subject: [PATCH 134/972] axi_dacfifo: Initial commit

AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
---
 library/Makefile                           |   2 +
 library/axi_dacfifo/Makefile               |  48 +++
 library/axi_dacfifo/axi_dacfifo.v          | 310 +++++++++++++++
 library/axi_dacfifo/axi_dacfifo_constr.xdc |  11 +
 library/axi_dacfifo/axi_dacfifo_dac.v      | 279 ++++++++++++++
 library/axi_dacfifo/axi_dacfifo_ip.tcl     |  24 ++
 library/axi_dacfifo/axi_dacfifo_rd.v       | 240 ++++++++++++
 library/axi_dacfifo/axi_dacfifo_wr.v       | 424 +++++++++++++++++++++
 8 files changed, 1338 insertions(+)
 create mode 100644 library/axi_dacfifo/Makefile
 create mode 100644 library/axi_dacfifo/axi_dacfifo.v
 create mode 100644 library/axi_dacfifo/axi_dacfifo_constr.xdc
 create mode 100644 library/axi_dacfifo/axi_dacfifo_dac.v
 create mode 100644 library/axi_dacfifo/axi_dacfifo_ip.tcl
 create mode 100644 library/axi_dacfifo/axi_dacfifo_rd.v
 create mode 100644 library/axi_dacfifo/axi_dacfifo_wr.v

diff --git a/library/Makefile b/library/Makefile
index f6e88a083..983870d4f 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -29,6 +29,7 @@ clean:
 	make -C axi_ad9739a clean
 	make -C axi_adcfifo clean
 	make -C axi_clkgen clean
+	make -C axi_dacfifo clean
 	make -C axi_dmac clean
 	make -C axi_generic_adc clean
 	make -C axi_gpreg clean
@@ -96,6 +97,7 @@ lib:
 	-make -C axi_ad9739a
 	-make -C axi_adcfifo
 	-make -C axi_clkgen
+	-make -C axi_dacfifo
 	-make -C axi_dmac
 	-make -C axi_generic_adc
 	-make -C axi_gpreg
diff --git a/library/axi_dacfifo/Makefile b/library/axi_dacfifo/Makefile
new file mode 100644
index 000000000..f84dfb477
--- /dev/null
+++ b/library/axi_dacfifo/Makefile
@@ -0,0 +1,48 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := axi_dacfifo_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../common/ad_mem_asym.v
+M_DEPS += ../common/ad_axis_inf_rx.v
+M_DEPS += axi_dacfifo_dac.v
+M_DEPS += axi_dacfifo_wr.v
+M_DEPS += axi_dacfifo_rd.v
+M_DEPS += axi_dacfifo.v
+M_DEPS += axi_dacfifo_constr.xdc
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_dacfifo.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_dacfifo.xpr: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_dacfifo_ip.tcl  >> axi_dacfifo_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
new file mode 100644
index 000000000..c949dcb6c
--- /dev/null
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -0,0 +1,310 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2016(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dacfifo (
+
+  // dma interface (AXI Stream)
+
+  dma_clk,
+  dma_valid,
+  dma_data,
+  dma_ready,
+  dma_xfer_req,
+  dma_xfer_last,
+
+  // dac interface
+
+  dac_clk,
+  dac_reset,
+  dac_valid,
+  dac_data,
+  dac_dunf,
+  dac_dovf,
+  dac_xfer_out,
+
+  // axi interface
+
+  axi_clk,
+  axi_resetn,
+  axi_awvalid,
+  axi_awid,
+  axi_awburst,
+  axi_awlock,
+  axi_awcache,
+  axi_awprot,
+  axi_awqos,
+  axi_awuser,
+  axi_awlen,
+  axi_awsize,
+  axi_awaddr,
+  axi_awready,
+  axi_wvalid,
+  axi_wdata,
+  axi_wstrb,
+  axi_wlast,
+  axi_wuser,
+  axi_wready,
+  axi_bvalid,
+  axi_bid,
+  axi_bresp,
+  axi_buser,
+  axi_bready,
+  axi_arvalid,
+  axi_arid,
+  axi_arburst,
+  axi_arlock,
+  axi_arcache,
+  axi_arprot,
+  axi_arqos,
+  axi_aruser,
+  axi_arlen,
+  axi_arsize,
+  axi_araddr,
+  axi_arready,
+  axi_rvalid,
+  axi_rid,
+  axi_ruser,
+  axi_rresp,
+  axi_rlast,
+  axi_rdata,
+  axi_rready);
+
+  // parameters
+
+  parameter   DAC_DATA_WIDTH = 128;
+  parameter   DMA_DATA_WIDTH = 64;
+  parameter   AXI_DATA_WIDTH = 512;
+  parameter   AXI_RD_SIZE = 2;
+  parameter   AXI_RD_LENGTH = 32;
+  parameter   AXI_WR_SIZE = 2;
+  parameter   AXI_WR_LENGTH = 32;
+  parameter   AXI_ADDRESS = 32'h00000000;
+  parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
+  parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
+
+  // dma interface
+
+  input                               dma_clk;
+  input                               dma_valid;
+  input   [(DMA_DATA_WIDTH-1):0]      dma_data;
+  output                              dma_ready;
+  input                               dma_xfer_req;
+  input                               dma_xfer_last;
+
+  // dac interface
+
+  input                               dac_clk;
+  input                               dac_reset;
+  input                               dac_valid;
+  output  [(DAC_DATA_WIDTH-1):0]      dac_data;
+  output                              dac_dunf;
+  output                              dac_dovf;
+  output                              dac_xfer_out;
+
+  // axi interface
+
+  input                               axi_clk;
+  input                               axi_resetn;
+  output                              axi_awvalid;
+  output  [  3:0]                     axi_awid;
+  output  [  1:0]                     axi_awburst;
+  output                              axi_awlock;
+  output  [  3:0]                     axi_awcache;
+  output  [  2:0]                     axi_awprot;
+  output  [  3:0]                     axi_awqos;
+  output  [  3:0]                     axi_awuser;
+  output  [  7:0]                     axi_awlen;
+  output  [  2:0]                     axi_awsize;
+  output  [ 31:0]                     axi_awaddr;
+  input                               axi_awready;
+  output                              axi_wvalid;
+  output  [(AXI_DATA_WIDTH-1):0]      axi_wdata;
+  output  [(AXI_BYTE_WIDTH-1):0]      axi_wstrb;
+  output                              axi_wlast;
+  output  [  3:0]                     axi_wuser;
+  input                               axi_wready;
+  input                               axi_bvalid;
+  input   [  3:0]                     axi_bid;
+  input   [  1:0]                     axi_bresp;
+  input   [  3:0]                     axi_buser;
+  output                              axi_bready;
+  output                              axi_arvalid;
+  output  [  3:0]                     axi_arid;
+  output  [  1:0]                     axi_arburst;
+  output                              axi_arlock;
+  output  [  3:0]                     axi_arcache;
+  output  [  2:0]                     axi_arprot;
+  output  [  3:0]                     axi_arqos;
+  output  [  3:0]                     axi_aruser;
+  output  [  7:0]                     axi_arlen;
+  output  [  2:0]                     axi_arsize;
+  output  [ 31:0]                     axi_araddr;
+  input                               axi_arready;
+  input                               axi_rvalid;
+  input   [  3:0]                     axi_rid;
+  input   [  3:0]                     axi_ruser;
+  input   [  1:0]                     axi_rresp;
+  input                               axi_rlast;
+  input   [(AXI_DATA_WIDTH-1):0]      axi_rdata;
+  output                              axi_rready;
+
+  // internal registers
+  reg                                 dma_dacrst_m1 = 1'b0;
+  reg                                 dma_dacrst_m2 = 1'b0;
+
+  // internal signals
+
+  wire    [(AXI_DATA_WIDTH-1):0]      axi_wr_data_s;
+  wire                                axi_wr_ready_s;
+  wire                                axi_wr_valid_s;
+  wire    [(AXI_DATA_WIDTH-1):0]      axi_rd_data_s;
+  wire                                axi_rd_ready_s;
+  wire                                axi_rd_valid_s;
+  wire    [31:0]                      axi_rd_lastaddr_s;
+  wire                                axi_xfer_req_s;
+  wire                                dma_rst_s;
+
+  // DAC reset the DMA side too
+
+  always @(posedge dma_clk) begin
+    dma_dacrst_m1 <= dac_reset;
+    dma_dacrst_m2 <= dma_dacrst_m1;
+  end
+  assign dma_rst_s = dma_dacrst_m2;
+
+  // instantiations
+
+  axi_dacfifo_wr #(
+    .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
+    .DMA_DATA_WIDTH (DMA_DATA_WIDTH),
+    .AXI_SIZE (AXI_WR_SIZE),
+    .AXI_LENGTH (AXI_WR_LENGTH),
+    .AXI_ADDRESS (AXI_ADDRESS),
+    .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
+  ) i_wr (
+    .dma_clk (dma_clk),
+    .dma_rst (dma_rst_s),
+    .dma_data (dma_data),
+    .dma_ready (dma_ready),
+    .dma_valid (dma_valid),
+    .dma_xfer_req (dma_xfer_req),
+    .dma_xfer_last (dma_xfer_last),
+    .axi_last_raddr (axi_rd_lastaddr_s),
+    .axi_xfer_out (axi_xfer_req_s),
+    .axi_clk (axi_clk),
+    .axi_resetn (axi_resetn),
+    .axi_awvalid (axi_awvalid),
+    .axi_awid (axi_awid),
+    .axi_awburst (axi_awburst),
+    .axi_awlock (axi_awlock),
+    .axi_awcache (axi_awcache),
+    .axi_awprot (axi_awprot),
+    .axi_awqos (axi_awqos),
+    .axi_awuser (axi_awuser),
+    .axi_awlen (axi_awlen),
+    .axi_awsize (axi_awsize),
+    .axi_awaddr (axi_awaddr),
+    .axi_awready (axi_awready),
+    .axi_wvalid (axi_wvalid),
+    .axi_wdata (axi_wdata),
+    .axi_wstrb (axi_wstrb),
+    .axi_wlast (axi_wlast),
+    .axi_wuser (axi_wuser),
+    .axi_wready (axi_wready),
+    .axi_bvalid (axi_bvalid),
+    .axi_bid (axi_bid),
+    .axi_bresp (axi_bresp),
+    .axi_buser (axi_buser),
+    .axi_bready (axi_bready),
+    .axi_werror (axi_werror));
+
+  axi_dacfifo_rd #(
+    .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
+    .AXI_SIZE (AXI_RD_SIZE),
+    .AXI_LENGTH (AXI_RD_LENGTH),
+    .AXI_ADDRESS (AXI_ADDRESS)
+  ) i_rd (
+    .axi_rd_lastaddr (axi_rd_lastaddr_s),
+    .axi_xfer_req (axi_xfer_req_s),
+    .axi_clk (axi_clk),
+    .axi_resetn (axi_resetn),
+    .axi_arvalid (axi_arvalid),
+    .axi_arid (axi_arid),
+    .axi_arburst (axi_arburst),
+    .axi_arlock (axi_arlock),
+    .axi_arcache (axi_arcache),
+    .axi_arprot (axi_arprot),
+    .axi_arqos (axi_arqos),
+    .axi_aruser (axi_aruser),
+    .axi_arlen (axi_arlen),
+    .axi_arsize (axi_arsize),
+    .axi_araddr (axi_araddr),
+    .axi_arready (axi_arready),
+    .axi_rvalid (axi_rvalid),
+    .axi_rid (axi_rid),
+    .axi_ruser (axi_ruser),
+    .axi_rresp (axi_rresp),
+    .axi_rlast (axi_rlast),
+    .axi_rdata (axi_rdata),
+    .axi_rready (axi_rready),
+    .axi_rerror (axi_rerror),
+    .axi_dvalid (axi_rd_valid_s),
+    .axi_ddata (axi_rd_data_s),
+    .axi_dready (axi_rd_ready_s));
+
+  axi_dacfifo_dac #(
+    .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
+    .DAC_DATA_WIDTH (DAC_DATA_WIDTH)
+  ) i_dac (
+    .axi_clk (axi_clk),
+    .axi_dvalid (axi_rd_valid_s),
+    .axi_ddata (axi_rd_data_s),
+    .axi_dready (axi_rd_ready_s),
+    .axi_xfer_req (axi_xfer_req_s),
+    .dac_clk (dac_clk),
+    .dac_valid (dac_valid),
+    .dac_data (dac_data),
+    .dac_xfer_out (dac_xfer_out),
+    .dac_dunf (dac_dunf),
+    .dac_dovf (dac_dovf));
+
+endmodule
+
diff --git a/library/axi_dacfifo/axi_dacfifo_constr.xdc b/library/axi_dacfifo/axi_dacfifo_constr.xdc
new file mode 100644
index 000000000..0343601bc
--- /dev/null
+++ b/library/axi_dacfifo/axi_dacfifo_constr.xdc
@@ -0,0 +1,11 @@
+
+set_property ASYNC_REG TRUE \
+  [get_cells -hier *dac_dovf_m_reg*] \
+  [get_cells -hier *dac_xfer_req_m_reg*] \
+  [get_cells -hier *dac_dunf_m_reg*]
+
+set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
new file mode 100644
index 000000000..37f725a01
--- /dev/null
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -0,0 +1,279 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2016(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dacfifo_dac (
+
+  axi_clk,
+  axi_dvalid,
+  axi_ddata,
+  axi_dready,
+  axi_xfer_req,
+
+  dac_clk,
+  dac_valid,
+  dac_data,
+  dac_xfer_out,
+  dac_dunf,
+  dac_dovf
+
+);
+
+  // parameters
+
+  parameter   AXI_DATA_WIDTH = 512;
+  parameter   DAC_DATA_WIDTH =  64;
+
+  localparam  MEM_RATIO = AXI_DATA_WIDTH/DAC_DATA_WIDTH;
+  localparam  DAC_ADDRESS_WIDTH = 8;
+  localparam  AXI_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
+                                  (MEM_RATIO == 2) ? (DAC_ADDRESS_WIDTH - 1) :
+                                  (MEM_RATIO == 4) ? (DAC_ADDRESS_WIDTH - 2) :
+                                                     (DAC_ADDRESS_WIDTH - 3);
+  localparam  BUF_THRESHOLD_LO = 8'd32;
+  localparam  BUF_THRESHOLD_HI = 8'd240;
+
+  // dma write
+
+  input                               axi_clk;
+  input                               axi_dvalid;
+  input   [(AXI_DATA_WIDTH-1):0]      axi_ddata;
+  output                              axi_dready;
+  input                               axi_xfer_req;
+
+  // dac read
+
+  input                               dac_clk;
+  input                               dac_valid;
+  output  [(DAC_DATA_WIDTH-1):0]      dac_data;
+  output                              dac_xfer_out;
+  output                              dac_dunf;
+  output                              dac_dovf;
+
+  // internal registers
+
+  reg     [(AXI_ADDRESS_WIDTH-1):0]   axi_waddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_waddr_g = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_raddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_raddr_m = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_addr_diff = 'd0;
+  reg                                 axi_dready = 'd0;
+  reg                                 axi_almost_full = 1'b0;
+  reg                                 axi_dwunf = 1'b0;
+  reg                                 axi_almost_empty  = 1'b0;
+  reg                                 axi_dwovf = 1'b0;
+
+  reg                                 dac_rst = 'd0;
+  reg                                 dac_rd = 'd0;
+  reg                                 dac_rd_d = 'd0;
+  reg     [(DAC_DATA_WIDTH-1):0]      dac_rdata_d = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_raddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_raddr_g = 'd0;
+
+  reg     [ 2:0]                      dac_dunf_m = 3'b0;
+  reg     [ 2:0]                      dac_dovf_m = 3'b0;
+  reg     [ 2:0]                      dac_xfer_req_m = 3'b0;
+
+  // internal signals
+
+  wire    [DAC_ADDRESS_WIDTH:0]       axi_addr_diff_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]   axi_waddr_s;
+  wire                                dac_wready_s;
+  wire                                dac_rd_s;
+  wire    [(DAC_DATA_WIDTH-1):0]      dac_rdata_s;
+
+  wire                                dac_valid_s;
+
+  // binary to grey conversion
+
+  function [7:0] b2g;
+    input [7:0] b;
+    reg   [7:0] g;
+    begin
+      g[7] = b[7];
+      g[6] = b[7] ^ b[6];
+      g[5] = b[6] ^ b[5];
+      g[4] = b[5] ^ b[4];
+      g[3] = b[4] ^ b[3];
+      g[2] = b[3] ^ b[2];
+      g[1] = b[2] ^ b[1];
+      g[0] = b[1] ^ b[0];
+      b2g = g;
+    end
+  endfunction
+
+  // grey to binary conversion
+
+  function [7:0] g2b;
+    input [7:0] g;
+    reg   [7:0] b;
+    begin
+      b[7] = g[7];
+      b[6] = b[7] ^ g[6];
+      b[5] = b[6] ^ g[5];
+      b[4] = b[5] ^ g[4];
+      b[3] = b[4] ^ g[3];
+      b[2] = b[3] ^ g[2];
+      b[1] = b[2] ^ g[1];
+      b[0] = b[1] ^ g[0];
+      g2b = b;
+    end
+  endfunction
+
+  // write interface
+
+  always @(posedge axi_clk) begin
+    if (axi_xfer_req == 1'b0) begin
+      axi_waddr <= 'd0;
+      axi_waddr_g <= 'd0;
+    end else begin
+      if (axi_dvalid == 1'b1) begin
+        axi_waddr <= axi_waddr + 1'b1;
+      end
+      axi_waddr_g <= b2g(axi_waddr_s);
+    end
+  end
+
+  // underflow / overflow
+
+  assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr;
+  assign axi_waddr_s = (MEM_RATIO == 1) ? axi_waddr :
+                       (MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
+                       (MEM_RATIO == 4) ? {axi_waddr, 2'd0} :
+                                          {axi_waddr, 3'd0};
+
+  always @(posedge axi_clk) begin
+    if (axi_xfer_req == 1'b0) begin
+      axi_addr_diff <= 'd0;
+      axi_raddr <= 'd0;
+      axi_raddr_m <= 'd0;
+      axi_dready <= 'd0;
+      axi_almost_full <= 1'b0;
+      axi_dwunf <= 1'b0;
+      axi_almost_empty <= 1'b0;
+      axi_dwovf <= 1'b0;
+    end else begin
+      axi_raddr_m <= g2b(dac_raddr_g);
+      axi_raddr <= axi_raddr_m;
+      axi_addr_diff <= axi_addr_diff_s[DAC_ADDRESS_WIDTH-1:0];
+      if (axi_addr_diff >= BUF_THRESHOLD_HI) begin
+        axi_dready <= 1'b0;
+      end else if (axi_addr_diff <= BUF_THRESHOLD_LO) begin
+        axi_dready <= 1'b1;
+      end
+      if (axi_addr_diff > BUF_THRESHOLD_HI) begin
+        axi_almost_full <= 1'b1;
+      end else begin
+        axi_almost_full <= 1'b0;
+      end
+      if (axi_addr_diff < BUF_THRESHOLD_LO) begin
+        axi_almost_empty <= 1'b1;
+      end else begin
+        axi_almost_empty <= 1'b0;
+      end
+      axi_dwunf <= (axi_addr_diff == 0) ? 1'b1 : 1'b0;
+      axi_dwovf <= (axi_addr_diff == {(DAC_ADDRESS_WIDTH){1'b1}}) ? 1'b1 : 1'b0;
+    end
+  end
+
+  always @(posedge dac_clk) begin
+    dac_dunf_m <= {dac_dunf_m[1:0], axi_dwunf};
+    dac_dovf_m <= {dac_dovf_m[1:0], axi_dwovf};
+    dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
+  end
+
+  assign dac_dovf = dac_dovf_m[2];
+  assign dac_dunf = dac_dunf_m[2];
+  assign dac_xfer_out = dac_xfer_req_m[2];
+
+  // read interface
+
+  assign dac_rd_s = dac_xfer_out & dac_valid;
+
+  always @(posedge dac_clk) begin
+    if (dac_xfer_out == 1'b0) begin
+      dac_rd <= 'd0;
+      dac_rd_d <= 'd0;
+      dac_rdata_d <= 'd0;
+      dac_raddr <= 'd0;
+      dac_raddr_g <= 'd0;
+    end else begin
+      dac_rd <= dac_rd_s;
+      dac_rd_d <= dac_rd;
+      dac_rdata_d <= dac_rdata_s;
+      if (dac_rd_s == 1'b1) begin
+        dac_raddr <= dac_raddr + 1'b1;
+      end
+      dac_raddr_g <= b2g(dac_raddr);
+    end
+  end
+
+  // instantiations
+
+  ad_mem_asym #(
+    .A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH),
+    .A_DATA_WIDTH (AXI_DATA_WIDTH),
+    .B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH),
+    .B_DATA_WIDTH (DAC_DATA_WIDTH))
+  i_mem_asym (
+    .clka (axi_clk),
+    .wea (axi_dvalid),
+    .addra (axi_waddr),
+    .dina (axi_ddata),
+    .clkb (dac_clk),
+    .addrb (dac_raddr),
+    .doutb (dac_rdata_s));
+
+  ad_axis_inf_rx #(.DATA_WIDTH(DAC_DATA_WIDTH)) i_axis_inf (
+    .clk (dac_clk),
+    .rst (dac_rst),
+    .valid (dac_rd_d),
+    .last (1'd0),
+    .data (dac_rdata_d),
+    .inf_valid (dac_valid_s),
+    .inf_last (),
+    .inf_data (dac_data),
+    .inf_ready (dac_valid));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_dacfifo/axi_dacfifo_ip.tcl b/library/axi_dacfifo/axi_dacfifo_ip.tcl
new file mode 100644
index 000000000..905139739
--- /dev/null
+++ b/library/axi_dacfifo/axi_dacfifo_ip.tcl
@@ -0,0 +1,24 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_dacfifo
+
+adi_ip_files axi_dacfifo [list \
+  "$ad_hdl_dir/library/common/ad_mem_asym.v" \
+  "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
+  "axi_dacfifo_dac.v" \
+  "axi_dacfifo_wr.v" \
+  "axi_dacfifo_rd.v" \
+  "axi_dacfifo.v" \
+  "axi_dacfifo_constr.xdc" ]
+
+adi_ip_properties_lite axi_dacfifo
+adi_ip_constraints axi_dacfifo [list \
+  "axi_dacfifo_constr.xdc" ]
+
+ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+
diff --git a/library/axi_dacfifo/axi_dacfifo_rd.v b/library/axi_dacfifo/axi_dacfifo_rd.v
new file mode 100644
index 000000000..b3ec1388f
--- /dev/null
+++ b/library/axi_dacfifo/axi_dacfifo_rd.v
@@ -0,0 +1,240 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2016(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dacfifo_rd (
+
+ // xfer last for read/write synchronization
+
+  axi_xfer_req,
+  axi_rd_lastaddr,
+
+  // axi read address and read data channels
+
+  axi_clk,
+  axi_resetn,
+  axi_arvalid,
+  axi_arid,
+  axi_arburst,
+  axi_arlock,
+  axi_arcache,
+  axi_arprot,
+  axi_arqos,
+  axi_aruser,
+  axi_arlen,
+  axi_arsize,
+  axi_araddr,
+  axi_arready,
+  axi_rvalid,
+  axi_rid,
+  axi_ruser,
+  axi_rresp,
+  axi_rlast,
+  axi_rdata,
+  axi_rready,
+
+  // axi status
+
+  axi_rerror,
+
+  // fifo interface
+
+  axi_dvalid,
+  axi_ddata,
+  axi_dready);
+
+  // parameters
+
+  parameter   AXI_DATA_WIDTH = 512;
+  parameter   AXI_SIZE = 2;
+  parameter   AXI_LENGTH = 15;
+  parameter   AXI_ADDRESS = 32'h00000000;
+  localparam  AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
+  localparam  AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;
+
+  // xfer last for read/write synchronization
+
+  input                           axi_xfer_req;
+  input   [ 31:0]                 axi_rd_lastaddr;
+
+  // axi interface
+
+  input                           axi_clk;
+  input                           axi_resetn;
+  output                          axi_arvalid;
+  output  [  3:0]                 axi_arid;
+  output  [  1:0]                 axi_arburst;
+  output                          axi_arlock;
+  output  [  3:0]                 axi_arcache;
+  output  [  2:0]                 axi_arprot;
+  output  [  3:0]                 axi_arqos;
+  output  [  3:0]                 axi_aruser;
+  output  [  7:0]                 axi_arlen;
+  output  [  2:0]                 axi_arsize;
+  output  [ 31:0]                 axi_araddr;
+  input                           axi_arready;
+  input                           axi_rvalid;
+  input   [  3:0]                 axi_rid;
+  input   [  3:0]                 axi_ruser;
+  input   [  1:0]                 axi_rresp;
+  input                           axi_rlast;
+  input   [(AXI_DATA_WIDTH-1):0]  axi_rdata;
+  output                          axi_rready;
+
+  // axi status
+
+  output                          axi_rerror;
+
+  // fifo interface
+
+  output                          axi_dvalid;
+  output  [(AXI_DATA_WIDTH-1):0]  axi_ddata;
+  input                           axi_dready;
+
+  // internal registers
+
+  reg     [ 31:0]                 axi_rd_addr_h = 32'b0;
+  reg                             axi_rd = 1'b0;
+  reg                             axi_rd_active = 1'b0;
+  reg                             axi_arvalid = 1'b0;
+  reg     [ 31:0]                 axi_araddr = 32'b0;
+  reg     [(AXI_DATA_WIDTH-1):0]  axi_ddata = 'b0;
+  reg                             axi_dvalid = 1'b0;
+  reg                             axi_rready = 1'b0;
+  reg                             axi_rerror = 1'b0;
+  reg     [ 1:0]                  axi_xfer_req_m = 2'b0;
+
+  // internal signals
+
+  wire                            axi_ready_s;
+  wire                            axi_xfer_req_init;
+  wire                            axi_dvalid_s;
+
+  assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_rd <= 1'b0;
+      axi_rd_active <= 1'b0;
+      axi_xfer_req_m <= 2'b0;
+    end else begin
+      if (axi_rd_active == 1'b1) begin
+        axi_rd <= 1'b0;
+        if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
+          axi_rd_active <= 1'b0;
+        end
+      end else if ((axi_ready_s == 1'b1)) begin
+        axi_rd <= axi_xfer_req;
+        axi_rd_active <= axi_xfer_req;
+      end
+    axi_xfer_req_m <= {axi_xfer_req_m[0], axi_xfer_req};
+    end
+  end
+
+  assign axi_xfer_req_init = axi_xfer_req_m[0] & ~axi_xfer_req_m[1];
+
+  // address channel
+
+  assign axi_arid = 4'b0000;
+  assign axi_arburst = 2'b01;
+  assign axi_arlock = 1'b0;
+  assign axi_arcache = 4'b0010;
+  assign axi_arprot = 3'b000;
+  assign axi_arqos = 4'b0000;
+  assign axi_aruser = 4'b0001;
+  assign axi_arlen = AXI_LENGTH;
+  assign axi_arsize = AXI_SIZE;
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_arvalid <= 'd0;
+      axi_araddr <= 'd0;
+    end else begin
+      if (axi_arvalid == 1'b1) begin
+        if (axi_arready == 1'b1) begin
+          axi_arvalid <= 1'b0;
+        end
+      end else begin
+        if (axi_rd == 1'b1) begin
+          axi_arvalid <= 1'b1;
+        end
+      end
+      if ((axi_xfer_req_init == 1'b1)) begin
+        axi_araddr <= AXI_ADDRESS;
+        axi_rd_addr_h <= axi_rd_lastaddr;
+      end else if ((axi_xfer_req == 1'b1) &&
+                   (axi_arvalid == 1'b1) &&
+                   (axi_arready == 1'b1)) begin
+        axi_araddr <= ((axi_araddr + AXI_AWINCR) >= axi_rd_addr_h) ? AXI_ADDRESS : axi_araddr + AXI_AWINCR;
+      end
+    end
+  end
+
+  // read data channel
+
+  assign axi_dvalid_s = axi_rvalid & axi_rready;
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_ddata <= 'd0;
+      axi_rready <= 1'b0;
+      axi_dvalid <= 1'b0;
+    end else begin
+      axi_ddata <= axi_rdata;
+      axi_dvalid <= axi_dvalid_s;
+      if (axi_xfer_req == 1) begin
+        axi_rready <= axi_rvalid;
+      end
+    end
+  end
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_rerror <= 'd0;
+    end else begin
+      axi_rerror <= axi_rvalid & axi_rresp[1];
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
new file mode 100644
index 000000000..7111200cf
--- /dev/null
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -0,0 +1,424 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2016(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dacfifo_wr (
+
+  // dma fifo interface
+
+  dma_clk,
+  dma_rst,
+  dma_data,
+  dma_ready,
+  dma_valid,
+
+  // request and syncronizaiton
+
+  dma_xfer_req,
+  dma_xfer_last,
+
+  // syncronization for the read side
+
+  axi_last_raddr,
+  axi_xfer_out,
+
+  // axi write address, write data and write response channels
+
+  axi_clk,
+  axi_resetn,
+  axi_awvalid,
+  axi_awid,
+  axi_awburst,
+  axi_awlock,
+  axi_awcache,
+  axi_awprot,
+  axi_awqos,
+  axi_awuser,
+  axi_awlen,
+  axi_awsize,
+  axi_awaddr,
+  axi_awready,
+  axi_wvalid,
+  axi_wdata,
+  axi_wstrb,
+  axi_wlast,
+  axi_wuser,
+  axi_wready,
+  axi_bvalid,
+  axi_bid,
+  axi_bresp,
+  axi_buser,
+  axi_bready,
+
+  axi_werror);
+
+  // parameters
+
+  parameter       AXI_DATA_WIDTH = 512;
+  parameter       DMA_DATA_WIDTH = 64;
+  parameter       AXI_SIZE = 2;
+  parameter       AXI_LENGTH = 15;
+  parameter       AXI_ADDRESS = 32'h00000000;
+  parameter       AXI_ADDRESS_LIMIT = 32'h00000000;
+
+  // for the syncronization buffer
+
+  localparam      MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
+  localparam      DMA_MADDRESS_WIDTH = 8;
+  localparam      AXI_MADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MADDRESS_WIDTH :
+                                       (MEM_RATIO == 2) ? (DMA_MADDRESS_WIDTH - 1) :
+                                       (MEM_RATIO == 4) ? (DMA_MADDRESS_WIDTH - 2) :
+                                       (DMA_MADDRESS_WIDTH - 3);
+
+  // for the AXI interface
+
+  localparam      AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
+  localparam      AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;
+
+  // dma fifo interface
+
+  input                                     dma_clk;
+  input                                     dma_rst;
+  input   [(DMA_DATA_WIDTH-1):0]            dma_data;
+  output                                    dma_ready;
+  input                                     dma_valid;
+
+  input                                     dma_xfer_req;
+  input                                     dma_xfer_last;
+
+  output  [31:0]                            axi_last_raddr;
+  output                                    axi_xfer_out;
+
+  // axi interface
+
+  input                                     axi_clk;
+  input                                     axi_resetn;
+  output                                    axi_awvalid;
+  output  [ 3:0]                            axi_awid;
+  output  [ 1:0]                            axi_awburst;
+  output                                    axi_awlock;
+  output  [ 3:0]                            axi_awcache;
+  output  [ 2:0]                            axi_awprot;
+  output  [ 3:0]                            axi_awqos;
+  output  [ 3:0]                            axi_awuser;
+  output  [ 7:0]                            axi_awlen;
+  output  [ 2:0]                            axi_awsize;
+  output  [31:0]                            axi_awaddr;
+  input                                     axi_awready;
+  output                                    axi_wvalid;
+  output  [(AXI_DATA_WIDTH-1):0]            axi_wdata;
+  output  [(AXI_BYTE_WIDTH-1):0]            axi_wstrb;
+  output                                    axi_wlast;
+  output  [ 3:0]                            axi_wuser;
+  input                                     axi_wready;
+  input                                     axi_bvalid;
+  input   [ 3:0]                            axi_bid;
+  input   [ 1:0]                            axi_bresp;
+  input   [ 3:0]                            axi_buser;
+  output                                    axi_bready;
+
+  output                                    axi_werror;
+
+  // internal register
+
+  reg     [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_waddr = 'd0;
+  reg     [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_waddr_g = 'd0;
+  reg     [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_addr_diff = 'd0;
+  reg     [(AXI_MADDRESS_WIDTH-1):0]        dma_mem_raddr_m1 = 'd0;
+  reg     [(AXI_MADDRESS_WIDTH-1):0]        dma_mem_raddr_m2 = 'd0;
+  reg     [(AXI_MADDRESS_WIDTH-1):0]        dma_mem_raddr = 'd0;
+  reg                                       dma_ready = 'd0;
+
+  reg     [ 2:0]                            axi_xfer_req_m = 3'b0;
+  reg     [ 2:0]                            axi_xfer_last_m = 3'b0;
+  reg     [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr_m1 = 'b0;
+  reg     [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr_m2 = 'b0;
+  reg     [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr = 'b0;
+  reg                                       axi_mem_ready = 'b0;
+  reg                                       axi_mem_ready_d = 'b0;
+  reg     [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata_d = 'b0;
+  reg     [(AXI_MADDRESS_WIDTH-1):0]        axi_mem_raddr = 'd0;
+  reg     [(AXI_MADDRESS_WIDTH-1):0]        axi_mem_raddr_g = 'd0;
+
+  reg                                       axi_reset = 1'b0;
+  reg                                       axi_xfer_out = 1'b0;
+  reg     [31:0]                            axi_last_raddr = 'b0;
+  reg                                       axi_awvalid = 1'b0;
+  reg     [31:0]                            axi_awaddr = 32'b0;
+  reg                                       axi_xfer_init = 1'b0;
+  reg                                       axi_werror = 1'b0;
+  reg                                       axi_mem_last = 1'b0;
+  reg                                       axi_mem_last_d = 1'b0;
+  reg     [ 3:0]                            axi_wvalid_cntr = 4'b0;
+
+  // internal signal
+
+  wire    [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_addr_diff_s;
+  wire    [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_raddr_s;
+  wire    [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr_s;
+  wire                                      axi_req_s;
+  wire    [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata_s;
+  wire                                      axi_wready_s;
+  wire                                      axi_mem_last_s;
+
+  // binary to grey conversion
+
+  function [7:0] b2g;
+    input [7:0] b;
+    reg   [7:0] g;
+    begin
+      g[7] = b[7];
+      g[6] = b[7] ^ b[6];
+      g[5] = b[6] ^ b[5];
+      g[4] = b[5] ^ b[4];
+      g[3] = b[4] ^ b[3];
+      g[2] = b[3] ^ b[2];
+      g[1] = b[2] ^ b[1];
+      g[0] = b[1] ^ b[0];
+      b2g = g;
+    end
+  endfunction
+
+  // grey to binary conversion
+
+  function [7:0] g2b;
+    input [7:0] g;
+    reg   [7:0] b;
+    begin
+      b[7] = g[7];
+      b[6] = b[7] ^ g[6];
+      b[5] = b[6] ^ g[5];
+      b[4] = b[5] ^ g[4];
+      b[3] = b[4] ^ g[3];
+      b[2] = b[3] ^ g[2];
+      b[1] = b[2] ^ g[1];
+      b[0] = b[1] ^ g[0];
+      g2b = b;
+    end
+  endfunction
+
+  // write address generation for the asymetric memory
+
+  always @(posedge dma_clk) begin
+    if (dma_rst == 1'b1) begin
+      dma_mem_waddr <= 8'h0;
+      dma_mem_waddr_g <= 8'h0;
+    end else begin
+      if ((dma_ready == 1'b1) && (dma_valid == 1'b1)) begin
+        dma_mem_waddr <= dma_mem_waddr + 1;
+      end
+      dma_mem_waddr_g <= b2g(dma_mem_waddr);
+    end
+  end
+
+  assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
+  assign dma_mem_raddr_s = (MEM_RATIO == 1) ?  dma_mem_raddr :
+                           (MEM_RATIO == 2) ? {dma_mem_raddr, 1'b0} :
+                           (MEM_RATIO == 4) ? {dma_mem_raddr, 2'b0} :
+                                              {dma_mem_raddr, 3'b0};
+
+  always @(posedge dma_clk) begin
+    if (dma_rst == 1'b1) begin
+      dma_mem_addr_diff <= 'b0;
+      dma_mem_raddr_m1 <= 'b0;
+      dma_mem_raddr_m2 <= 'b0;
+      dma_mem_raddr <= 'b0;
+    end else begin
+      dma_mem_raddr_m1 <= g2b(axi_mem_raddr_g);
+      dma_mem_raddr_m2 <= dma_mem_raddr_m1;
+      dma_mem_raddr <= dma_mem_raddr_m2;
+      dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MADDRESS_WIDTH-1:0];
+      if (dma_mem_addr_diff >= 180) begin
+        dma_ready <= 1'b0;
+      end else begin
+        dma_ready <= 1'b1;
+      end
+    end
+  end
+
+  // read address generation for the asymetric memory
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_xfer_req_m <= 3'b0;
+      axi_xfer_last_m <= 3'b0;
+      axi_mem_waddr_m1 <= 'b0;
+      axi_mem_waddr_m2 <= 'b0;
+      axi_mem_waddr <= 'b0;
+      axi_xfer_init <= 1'b0;
+    end else begin
+      axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
+      axi_xfer_last_m <= {axi_xfer_last_m[1:0], dma_xfer_last};
+      axi_mem_waddr_m1 <= g2b(dma_mem_waddr_g);
+      axi_mem_waddr_m2 <= axi_mem_waddr_m1;
+      axi_mem_waddr <= axi_mem_waddr_m2;
+      axi_xfer_init = ~axi_xfer_req_m[2] & axi_xfer_req_m[1];
+    end
+  end
+
+  assign axi_wready_s = ~axi_wvalid | axi_wready;
+  assign axi_mem_ready_s = (axi_mem_raddr == axi_mem_waddr_s) ? 1'b0 : axi_wready_s;
+  assign axi_req_s = (axi_mem_raddr[1:0] == 2'h0) ? axi_mem_ready_s : 1'b0;
+  assign axi_mem_last_s = (axi_wvalid_cntr == AXI_LENGTH) ? axi_mem_ready_s : 1'b0;
+  assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr :
+                           (MEM_RATIO == 2) ? axi_mem_waddr[(DMA_MADDRESS_WIDTH-1):1] :
+                           (MEM_RATIO == 4) ? axi_mem_waddr[(DMA_MADDRESS_WIDTH-1):2] :
+                                              axi_mem_waddr[(DMA_MADDRESS_WIDTH-1):3];
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_mem_ready <= 1'b0;
+      axi_mem_ready_d <= 1'b0;
+      axi_mem_rdata_d <= 'b0;
+      axi_mem_raddr <= 'b0;
+      axi_wvalid_cntr <= 4'b0;
+    end else begin
+      axi_mem_ready <= axi_mem_ready_s;
+      axi_mem_last <= axi_mem_last_s;
+      axi_mem_last_d <= axi_mem_last;
+      axi_mem_ready_d <= axi_mem_ready;
+      axi_mem_rdata_d <= axi_mem_rdata_s;
+      if (axi_mem_ready_s == 1'b1) begin
+        axi_mem_raddr <= axi_mem_raddr + 1;
+        axi_wvalid_cntr <= (axi_wvalid_cntr == AXI_LENGTH) ? 4'b0 : axi_wvalid_cntr + 1;
+      end
+      axi_mem_raddr_g <= b2g(axi_mem_raddr);
+    end
+  end
+
+  // write address generation for AXI MEMORY MAP interface
+
+  // address channel
+
+  assign axi_awid = 4'b0000;
+  assign axi_awburst = 2'b01;
+  assign axi_awlock = 1'b0;
+  assign axi_awcache = 4'b0010;
+  assign axi_awprot = 3'b000;
+  assign axi_awqos = 4'b0000;
+  assign axi_awuser = 4'b0001;
+  assign axi_awlen = AXI_LENGTH;
+  assign axi_awsize = AXI_SIZE;
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_awvalid <= 'd0;
+      axi_awaddr <= AXI_ADDRESS;
+      axi_last_raddr <= AXI_ADDRESS;
+      axi_xfer_out <= 1'b0;
+    end else begin
+      if (axi_awvalid == 1'b1) begin
+        if (axi_awready == 1'b1) begin
+          axi_awvalid <= 1'b0;
+        end
+      end else begin
+        if (axi_req_s == 1'b1) begin
+          axi_awvalid <= 1'b1;
+        end
+      end
+      if (axi_xfer_init == 1'b1) begin
+        axi_awaddr <= (axi_xfer_out == 1'b1) ? AXI_ADDRESS : axi_last_raddr;
+        axi_xfer_out <= 1'b0;
+      end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
+        axi_awaddr <= axi_awaddr + AXI_AWINCR;
+      end
+      if(axi_xfer_last_m[2] == 1) begin
+        axi_last_raddr <= axi_awaddr;
+        axi_xfer_out <= 1'b1;
+      end
+    end
+  end
+
+  // write channel
+
+  assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
+  assign axi_wuser = 4'b0000;
+
+  // response channel
+
+  assign axi_bready = 1'b1;
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_werror <= 'd0;
+    end else begin
+      axi_werror <= axi_bvalid & axi_bresp[1];
+    end
+  end
+
+  // fifo needs a reset
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_reset <= 1'b1;
+    end else begin
+      axi_reset <= 1'b0;
+    end
+  end
+
+  // instantiations
+
+  ad_mem_asym #(
+    .A_ADDRESS_WIDTH (DMA_MADDRESS_WIDTH),
+    .A_DATA_WIDTH (DMA_DATA_WIDTH),
+    .B_ADDRESS_WIDTH (AXI_MADDRESS_WIDTH),
+    .B_DATA_WIDTH (AXI_DATA_WIDTH))
+  i_mem_asym (
+    .clka (dma_clk),
+    .wea (dma_valid),
+    .addra (dma_mem_waddr),
+    .dina (dma_data),
+    .clkb (axi_clk),
+    .addrb (axi_mem_raddr),
+    .doutb (axi_mem_rdata_s));
+
+  ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
+    .clk (axi_clk),
+    .rst (axi_reset),
+    .valid (axi_mem_ready_d),
+    .last (axi_mem_last_d),
+    .data (axi_mem_rdata_d),
+    .inf_valid (axi_wvalid),
+    .inf_last (axi_wlast),
+    .inf_data (axi_wdata),
+    .inf_ready (axi_wready));
+
+endmodule
+

From 8a574cd8ba6fb65db1d787f6413d245e2ebc5ac0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 19 Apr 2016 11:30:52 +0300
Subject: [PATCH 135/972] zc706_system_plddr3.tcl : Add integration process for
 the AXI_DAC_FIFO

---
 projects/common/zc706/zc706_system_plddr3.tcl | 94 ++++++++++++++++++-
 1 file changed, 92 insertions(+), 2 deletions(-)

diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl
index 38bc92777..1b634937f 100644
--- a/projects/common/zc706/zc706_system_plddr3.tcl
+++ b/projects/common/zc706/zc706_system_plddr3.tcl
@@ -57,8 +57,8 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} {
   ad_connect  axi_ddr_cntrl/S_AXI axi_adcfifo/axi
   ad_connect  adc_rst axi_adcfifo/adc_rst
   ad_connect  adc_rst axi_rstgen/ext_reset_in
-  ad_connect  adc_clk axi_adcfifo/adc_clk 
-  ad_connect  adc_wr axi_adcfifo/adc_wr 
+  ad_connect  adc_clk axi_adcfifo/adc_clk
+  ad_connect  adc_wr axi_adcfifo/adc_wr
   ad_connect  adc_wdata axi_adcfifo/adc_wdata
   ad_connect  adc_wovf axi_adcfifo/adc_wovf
   ad_connect  dma_clk axi_adcfifo/dma_clk
@@ -79,3 +79,93 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} {
   current_bd_instance $c_instance
 }
 
+
+proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
+
+  global ad_hdl_dir
+
+  set p_instance [get_bd_cells $p_name]
+  set c_instance [current_bd_instance .]
+
+  current_bd_instance $p_instance
+
+  set m_instance [create_bd_cell -type hier $m_name]
+  current_bd_instance $m_instance
+
+  create_bd_pin -dir I -type rst sys_rst
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
+
+  create_bd_pin -dir I dac_rst
+  create_bd_pin -dir I -type clk dac_clk
+  create_bd_pin -dir I dac_valid
+  create_bd_pin -dir O -from [expr ($dac_data_width-1)] -to 0 dac_data
+  create_bd_pin -dir O dac_dunf
+  create_bd_pin -dir O dac_dovf
+  create_bd_pin -dir O dac_xfer_out
+
+  create_bd_pin -dir I -type clk dma_clk
+  create_bd_pin -dir I dma_rvalid
+  create_bd_pin -dir I -from [expr ($dma_data_width-1)] -to 0 dma_rdata
+  create_bd_pin -dir O dma_rready
+  create_bd_pin -dir I dma_xfer_req
+  create_bd_pin -dir I dma_xfer_last
+
+  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
+  set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
+  file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
+  set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
+
+  set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
+  set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
+  set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
+
+  set axi_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_dacfifo:1.0 axi_dacfifo]
+  set_property -dict [list CONFIG.DAC_DATA_WIDTH $dac_data_width] $axi_dacfifo
+  set_property -dict [list CONFIG.DMA_DATA_WIDTH $dma_data_width] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_WR_SIZE {6}] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_WR_LENGTH {3}] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_RD_SIZE {6}] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_RD_LENGTH {15}] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo
+
+  ## clock and reset
+
+  ad_connect  sys_clk axi_ddr_cntrl/SYS_CLK
+  ad_connect  sys_rst axi_ddr_cntrl/sys_rst
+  ad_connect  axi_clk axi_ddr_cntrl/ui_clk
+  ad_connect  axi_clk axi_dacfifo/axi_clk
+  ad_connect  axi_clk axi_rstgen/slowest_sync_clk
+  ad_connect  dac_clk axi_dacfifo/dac_clk
+  ad_connect  dma_clk axi_dacfifo/dma_clk
+
+  ad_connect  axi_resetn axi_rstgen/peripheral_aresetn
+  ad_connect  axi_resetn axi_dacfifo/axi_resetn
+  ad_connect  axi_resetn axi_ddr_cntrl/aresetn
+  ad_connect  dac_rst axi_dacfifo/dac_reset
+  ad_connect  dac_rst axi_rstgen/ext_reset_in
+
+  ## interfaces
+
+  ad_connect  ddr3 axi_ddr_cntrl/DDR3
+  ad_connect  axi_ddr_cntrl/S_AXI axi_dacfifo/axi
+
+  ad_connect  dma_rvalid axi_dacfifo/dma_valid
+  ad_connect  dma_rready axi_dacfifo/dma_ready
+  ad_connect  dma_rdata axi_dacfifo/dma_data
+  ad_connect  dma_xfer_req axi_dacfifo/dma_xfer_req
+  ad_connect  dma_xfer_last axi_dacfifo/dma_xfer_last
+
+  ad_connect  dac_valid axi_dacfifo/dac_valid
+  ad_connect  dac_data axi_dacfifo/dac_data
+  ad_connect  dac_dunf axi_dacfifo/dac_dunf
+  ad_connect  dac_dovf axi_dacfifo/dac_dovf
+  ad_connect  dac_xfer_out axi_dacfifo/dac_xfer_out
+
+  ad_connect  axi_ddr_cntrl/device_temp_i GND
+
+  current_bd_instance $c_instance
+}
+

From d7d8b2cf1c728918a0c42408ae6b6488adc76276 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 19 Apr 2016 14:38:26 +0300
Subject: [PATCH 136/972] axi_usb_fx3: Integrated actual GPIF II interface,
 with 2 address lines

---
 library/axi_usb_fx3/axi_usb_fx3.v      |  31 +-
 library/axi_usb_fx3/axi_usb_fx3_core.v | 431 ++++++++++++++-----------
 library/axi_usb_fx3/axi_usb_fx3_if.v   | 384 ++++++++++++----------
 3 files changed, 471 insertions(+), 375 deletions(-)

diff --git a/library/axi_usb_fx3/axi_usb_fx3.v b/library/axi_usb_fx3/axi_usb_fx3.v
index f6e19cbdf..65cfbb2a1 100644
--- a/library/axi_usb_fx3/axi_usb_fx3.v
+++ b/library/axi_usb_fx3/axi_usb_fx3.v
@@ -112,12 +112,12 @@ module axi_usb_fx3 (
   input           dma_rdy;
   input           dma_wmk;
 
-  input  [10:0]   fifo_rdy;
+  input  [ 3:0]   fifo_rdy;
 
   output          pclk;
 
-  output  [31:0]  data;
-  output  [4:0]   addr;
+  inout   [31:0]  data;
+  output  [ 1:0]  addr;
 
   output          slcs_n;
   output          slrd_n;
@@ -127,8 +127,8 @@ module axi_usb_fx3 (
   output          epswitch_n;
 
   // DEBUG
-  output  [35:0]  debug_fx32dma;
-  output  [34:0]  debug_dma2fx3;
+  output  [74:0]  debug_fx32dma;
+  output  [73:0]  debug_dma2fx3;
   output  [14:0]  debug_status;
 
   // irq
@@ -223,6 +223,7 @@ module axi_usb_fx3 (
   wire            fifo8_direction;
   wire            fifo9_direction;
   wire            fifoa_direction;
+  wire    [10:0]  fifo_direction;
 
   wire            fx32dma_valid;
   wire            fx32dma_ready;
@@ -251,11 +252,13 @@ module axi_usb_fx3 (
   assign pclk     = s_axi_aclk;
   assign up_rstn  = s_axi_aresetn;
 
+  assign fifo_direction = {fifo9_direction, fifo8_direction, fifo7_direction, fifo6_direction, fifo5_direction, fifo4_direction, fifo3_direction, fifo2_direction, fifo1_direction, fifo0_direction};
+
   // DEBUG
 
-  assign debug_dma2fx3 = {dma2fx3_ready, dma2fx3_valid, dma2fx3_data, dma2fx3_eop};
-  assign debug_fx32dma = {fx32dma_eop,fx32dma_ready, fx32dma_valid, fx32dma_data, fx32dma_sop};
-  assign debug_status = {irq, error, monitor_error, test_mode_tpg, test_mode_tpm, trig, fifo_num};
+  assign debug_dma2fx3  = {s_axis_tdata, dma2fx3_data, s_axis_tkeep, s_axis_tlast, s_axis_tvalid, s_axis_tready, dma2fx3_ready, dma2fx3_valid, dma2fx3_eop};
+  assign debug_fx32dma  = {fx32dma_eop, m_axis_tdata, fx32dma_data, m_axis_tkeep, m_axis_tlast, m_axis_tvalid, m_axis_tready, fx32dma_ready, fx32dma_valid, fx32dma_sop};
+  assign debug_status   = {irq, error, monitor_error, test_mode_tpg, test_mode_tpm, trig, fifo_num};
 
   // packetizer, TPM/TPG and DMA interface
 
@@ -397,10 +400,12 @@ module axi_usb_fx3 (
 
   axi_usb_fx3_if fx3_if(
 
+    .pclk(pclk),              //output clk 100 Mhz and 180 phase shift
+    .reset_n(up_rstn),
+
     .dma_rdy(dma_rdy),
     .dma_wmk(dma_wmk),
     .fifo_rdy(fifo_rdy),
-    .pclk(pclk),              //output clk 100 Mhz and 180 phase shift
     .data(data),
     .addr(addr),              //output fifo address
     .slcs_n(slcs_n),          //output chip select
@@ -409,11 +414,13 @@ module axi_usb_fx3 (
     .slwr_n(slwr_n),          //output write select
     .pktend_n(pktend_n),      //output pkt end
     .epswitch_n(epswitch_n),  //output pkt end
-    .fifo_num(fifo_num),
-    .trig(trig),
-    .test_mode_tpm(test_mode_tpm),
+
     .fifo_ready(fifo_ready),
 
+    .fifo_num(fifo_num),
+    .fifo_direction(fifo_direction),
+    .trig(trig),
+
     .fx32dma_valid(fx32dma_valid),
     .fx32dma_ready(fx32dma_ready),
     .fx32dma_data(fx32dma_data),
diff --git a/library/axi_usb_fx3/axi_usb_fx3_core.v b/library/axi_usb_fx3/axi_usb_fx3_core.v
index e0ed6114e..e8fe956b8 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_core.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_core.v
@@ -268,12 +268,13 @@ module axi_usb_fx3_core (
   reg     [ 7:0]  header_pointer = 8'h0;
   reg             header_read = 1'b0;
 
-  reg     [31:0]  dma2fx3_counter = 1'b0;
-  reg     [31:0]  footer_pointer = 1'b0;
+  reg     [31:0]  dma2fx3_counter = 32'h0;
+  reg     [ 7:0]  footer_pointer = 8'h0;
 
   reg             s_axis_tready = 1'b0;
   reg             dma2fx3_valid = 1'b0;
   reg     [31:0]  dma2fx3_data = 32'h0;
+  reg     [31:0]  dma2fx3_data_reg = 32'h0;
   reg             dma2fx3_eop = 1'b0;
 
   reg     [31:0]  expected_data = 32'h0;
@@ -369,132 +370,6 @@ module axi_usb_fx3_core (
 
   assign fx32dma_ready = m_axis_tready;
 
-  // state machine
-
-  always @(posedge clk) begin
-    if (reset == 1'b1 || error_fx32dma == 1'b1) begin
-      state_fx32dma <= IDLE;
-    end else begin
-      state_fx32dma <= next_state_fx32dma;
-    end
-  end
-
-  always @(*) begin
-    case(state_fx32dma)
-      IDLE:
-      if(fx32dma_sop == 1'b1) begin
-        next_state_fx32dma = READ_HEADER;
-      end else begin
-        next_state_fx32dma = state_fx32dma;
-      end
-      READ_HEADER:
-      if(header_read == 1'b1) begin
-        next_state_fx32dma = READ_DATA;
-      end else begin
-        next_state_fx32dma = state_fx32dma;
-      end
-      READ_DATA:
-      if(data_size_transaction <= 4) begin
-        next_state_fx32dma = IDLE;
-      end else begin
-        next_state_fx32dma = state_fx32dma;
-      end
-      default: next_state_fx32dma = IDLE;
-    endcase
-  end
-
-  always @(posedge clk) begin
-    case(state_fx32dma)
-      IDLE: begin
-        m_axis_tvalid <= 1'b0;
-        m_axis_tkeep <= 4'h0;
-        m_axis_tlast <= 1'b0;
-        error_fx32dma <= 1'b0;
-        eot_fx32dma <= 1'b0;
-        header_read <= 1'b0;
-        header_pointer <= 8'h4;
-        first_transfer <= 1'b1;
-        monitor_error <= 1'b0;
-        if (fx32dma_sop == 1'b1) begin
-          if(fx32dma_valid == 1'b1) begin
-            if(fx32dma_data != 32'hf00ff00f) begin
-              error_fx32dma <= 1'b1;
-            end else begin
-              error_fx32dma <= 1'b0;
-            end
-          end
-        end
-        case (test_mode_tpm)
-          4'h1: expected_data <= 32'haaaaaaaa;
-          default:  expected_data <= 32'hffffffff;
-        endcase
-      end
-      READ_HEADER: begin
-        m_axis_tvalid <= 1'b0;
-        m_axis_tkeep <= 4'h0;
-        m_axis_tlast <= 1'b0;
-        error_fx32dma <= 1'b0;
-        eot_fx32dma <= 1'b0;
-        first_transfer <= 1'b1;
-        monitor_error <= 1'b0;
-        if( fx32dma_valid == 1'b1) begin
-          if(header_pointer < header_size_current - 8) begin
-            header_pointer <= header_pointer + 4;
-          end else begin
-            header_read <= 1'b1;
-          end
-          if (header_pointer == 4) begin
-            data_size_transaction <= fx32dma_data;
-            if (fx32dma_data > buffer_size_current) begin
-              error_fx32dma <= 1'b1;
-            end
-          end
-        end
-      end
-      READ_DATA: begin
-        m_axis_tvalid <= fx32dma_valid;
-        m_axis_tdata <= fx32dma_data;
-        if (fx32dma_valid == 1'b1) begin
-          first_transfer <= 1'b0;
-          if (data_size_transaction > 4) begin
-            m_axis_tkeep <= 4'hf;
-            m_axis_tlast <= 1'b0;
-            data_size_transaction <= data_size_transaction - 4;
-          end else begin
-            m_axis_tlast <= 1'b1;
-            eot_fx32dma <= 1'b1;
-            case (data_size_transaction)
-              1: m_axis_tkeep <= 4'h1;
-              2: m_axis_tkeep <= 4'h3;
-              3: m_axis_tkeep <= 4'h7;
-              default: m_axis_tkeep <= 4'hf;
-            endcase
-          end
-        end
-        // monitor
-        if (test_mode_active_tpm == 1'b1) begin
-          if (first_transfer == 1) begin
-            expected_data <= fx32dma_data;
-          end else begin
-            case (test_mode_tpm)
-              4'h1: expected_data <= ~expected_data;
-              4'h2: expected_data <= ~expected_data;
-              4'h3: expected_data <= pn9(expected_data);
-              4'h4: expected_data <= pn23(expected_data);
-              4'h7: expected_data <= expected_data + 1;
-              default:  expected_data <= 0;
-            endcase
-            if (expected_data != m_axis_tdata) begin
-              monitor_error <= 1'b1;
-            end else begin
-              monitor_error <= 1'b0;
-            end
-          end
-        end
-      end
-    endcase
-  end
-
   always @(*) begin
     case (fifo_num)
       5'h0: buffer_size_current = fifo0_buffer_size;
@@ -536,6 +411,148 @@ module axi_usb_fx3_core (
     endcase
   end
 
+  // state machine
+
+  always @(posedge clk) begin
+    if (reset == 1'b1 || error_fx32dma == 1'b1) begin
+      state_fx32dma <= IDLE;
+    end else begin
+      state_fx32dma <= next_state_fx32dma;
+    end
+  end
+
+  always @(*) begin
+    case(state_fx32dma)
+      IDLE:
+      if(fx32dma_sop == 1'b1) begin
+        next_state_fx32dma = READ_HEADER;
+      end else begin
+        next_state_fx32dma = state_fx32dma;
+      end
+      READ_HEADER:
+      if(header_read == 1'b1) begin
+        next_state_fx32dma = READ_DATA;
+      end else begin
+        next_state_fx32dma = state_fx32dma;
+      end
+      READ_DATA:
+      if(data_size_transaction <= 4) begin
+        next_state_fx32dma = IDLE;
+      end else begin
+        next_state_fx32dma = state_fx32dma;
+      end
+      default: next_state_fx32dma = IDLE;
+    endcase
+  end
+
+  always @(*) begin
+    m_axis_tdata = fx32dma_data;
+    case(state_fx32dma)
+      IDLE: begin
+        m_axis_tvalid = 1'b0;
+        m_axis_tkeep = 4'h0;
+        m_axis_tlast = 1'b0;
+        eot_fx32dma  = 1'b0;
+      end
+      READ_HEADER: begin
+        m_axis_tvalid = 1'b0;
+        m_axis_tkeep = 4'h0;
+        m_axis_tlast = 1'b0;
+        eot_fx32dma  = 1'b0;
+      end
+      READ_DATA: begin
+        m_axis_tvalid = fx32dma_valid;
+        m_axis_tlast = fx32dma_eop;
+        eot_fx32dma = fx32dma_eop;
+        if (fx32dma_valid == 1'b1) begin
+          if (data_size_transaction > 4) begin
+            m_axis_tkeep = 4'hf;
+            eot_fx32dma  = 1'b0;
+          end else begin
+            eot_fx32dma  = 1'b1;
+            m_axis_tlast = 1'b1;
+            case (data_size_transaction)
+              1: m_axis_tkeep = 4'h1;
+              2: m_axis_tkeep = 4'h3;
+              3: m_axis_tkeep = 4'h7;
+              default: m_axis_tkeep = 4'hf;
+            endcase
+          end
+        end else begin
+          m_axis_tkeep = 4'h0;
+          eot_fx32dma  = 1'b0;
+        end
+      end
+      default: begin
+        m_axis_tvalid = 1'b0;
+        m_axis_tkeep = 4'h0;
+        m_axis_tlast = 1'b0;
+        eot_fx32dma  = 1'b0;
+      end
+    endcase
+  end
+  always @(posedge clk) begin
+    header_read <= 1'b0;
+    if (state_fx32dma == IDLE) begin
+      if (fx32dma_sop == 1'b1) begin
+        header_pointer <= 8'h4;
+        if (fx32dma_data != 32'hf00ff00f) begin
+          error_fx32dma <= 1'b1;
+        end else begin
+          error_fx32dma <= 1'b0;
+        end
+      end
+      case (test_mode_tpm)
+        4'h1: expected_data <= 32'haaaaaaaa;
+        default: expected_data <= 32'hffffffff;
+      endcase
+    end
+    if (state_fx32dma == READ_HEADER) begin
+      if (fx32dma_valid == 1'b1) begin
+        if(header_pointer < header_size_current - 4) begin
+          header_pointer <= header_pointer + 8;
+        end else begin
+          header_read <= 1'b1;
+        end
+        if (header_pointer == 4) begin
+          data_size_transaction <= fx32dma_data;
+          if (fx32dma_data > buffer_size_current) begin
+            error_fx32dma <= 1'b1;
+          end
+        end
+      end
+    end
+    if (state_fx32dma == READ_DATA) begin
+      first_transfer <= 1'b1;
+      if (fx32dma_valid == 1'b1) begin
+        first_transfer <= 1'b0;
+        if (data_size_transaction > 4) begin
+          data_size_transaction <= data_size_transaction - 4;
+        end
+      end
+      // monitor
+      if (test_mode_active_tpm == 1'b1) begin
+        if (first_transfer == 1) begin
+          expected_data <= fx32dma_data;
+        end else begin
+          case (test_mode_tpm)
+            4'h1: expected_data <= ~expected_data;
+            4'h2: expected_data <= ~expected_data;
+            4'h3: expected_data <= pn9(expected_data);
+            4'h4: expected_data <= pn23(expected_data);
+            4'h7: expected_data <= expected_data + 1;
+            default:  expected_data <= 0;
+          endcase
+          if (expected_data != m_axis_tdata) begin
+            monitor_error <= 1'b1;
+          end else begin
+            monitor_error <= 1'b0;
+          end
+        end
+      end
+    end
+  end
+
   // dma2fx3
 
   always @(posedge clk) begin
@@ -552,92 +569,120 @@ module axi_usb_fx3_core (
         if(dma2fx3_ready == 1'b1) begin
           next_state_dma2fx3 = READ_DATA;
         end else begin
-          next_state_dma2fx3 = state_dma2fx3;
+          next_state_dma2fx3 = IDLE;
         end
       READ_DATA:
         if(s_axis_tlast == 1'b1 || dma2fx3_counter >= buffer_size_current - 4) begin
           next_state_dma2fx3 = ADD_FOOTER;
         end else begin
-          next_state_dma2fx3 = state_dma2fx3;
+          next_state_dma2fx3 = READ_DATA;
         end
       ADD_FOOTER:
         if(dma2fx3_eop == 1'b1) begin
           next_state_dma2fx3 = IDLE;
         end else begin
-          next_state_dma2fx3 = state_dma2fx3;
+          next_state_dma2fx3 = ADD_FOOTER;
         end
-        default: next_state_dma2fx3 = IDLE;
+      default: next_state_dma2fx3 = IDLE;
+    endcase
+  end
+
+  always @(*) begin
+    case(state_dma2fx3)
+      IDLE: begin
+        s_axis_tready = 1'b0;
+        dma2fx3_valid = 1'b0;
+        eot_dma2fx3 = 1'b0;
+        dma2fx3_eop = 1'b0;
+        dma2fx3_data = dma2fx3_data_reg;
+      end
+      READ_DATA: begin
+        eot_dma2fx3 = 1'b0;
+        if (test_mode_active_tpg == 1'b1) begin
+          s_axis_tready = 1'b0;
+          dma2fx3_valid = 1'b1;
+        end else begin
+          dma2fx3_valid = s_axis_tvalid & s_axis_tready;
+          s_axis_tready = dma2fx3_ready;
+        end
+        dma2fx3_eop = 1'b0;
+        if (test_mode_active_tpg == 1'b1) begin
+          dma2fx3_data = dma2fx3_data_reg;
+        end else begin
+          dma2fx3_data = s_axis_tdata;
+        end
+      end
+      ADD_FOOTER: begin
+        s_axis_tready = 1'b0;
+        dma2fx3_valid = 1'b1;
+        if (footer_pointer == header_size_current) begin
+          dma2fx3_eop = 1'b1;
+          eot_dma2fx3 = 1'b1;
+        end else begin
+          dma2fx3_eop = 1'b0;
+          eot_dma2fx3 = 1'b0;
+        end
+        dma2fx3_data = dma2fx3_data_reg;
+      end
+      default: begin
+        s_axis_tready = 1'b0;
+        dma2fx3_valid = 1'b0;
+        eot_dma2fx3 = 1'b0;
+        dma2fx3_eop = 1'b0;
+        dma2fx3_data = dma2fx3_data_reg;
+      end
     endcase
   end
 
   always @(posedge clk) begin
-    case(state_dma2fx3)
-      IDLE: begin
-        dma2fx3_eop <= 1'b0;
-        eot_dma2fx3 <= 1'b0;
-        s_axis_tready <= 1'b0;
-        footer_pointer <= 0;
-        dma2fx3_counter <= 0;
-        dma2fx3_valid <= 1'b0;
-        case (test_mode_tpg)
-          4'h1: dma2fx3_data <= 32'haaaaaaaa;
-          default:  dma2fx3_data <= 32'hffffffff;
-        endcase
-      end
-      READ_DATA: begin
-        dma2fx3_eop <= 1'b0;
-        eot_dma2fx3 <= 1'b0;
-        footer_pointer <= 0;
-        if (test_mode_active_tpg == 1'b1) begin
-          s_axis_tready <= 1'b0;
-          dma2fx3_valid <= 1'b1;
-          if (dma2fx3_ready == 1'b1) begin
-            dma2fx3_counter <= dma2fx3_counter + 4;
-            case (test_mode_tpg)
-              4'h1: dma2fx3_data <= ~dma2fx3_data;
-              4'h2: dma2fx3_data <= ~dma2fx3_data;
-              4'h3: dma2fx3_data <= pn9(dma2fx3_data);
-              4'h4: dma2fx3_data <= pn23(dma2fx3_data);
-              4'h7: dma2fx3_data <= dma2fx3_data + 1;
-              default:  dma2fx3_data <= 0;
-            endcase
-          end
-        end else begin
-          dma2fx3_data <= s_axis_tdata;
-          if (s_axis_tlast == 1'b0) begin
-            s_axis_tready <= dma2fx3_ready;
+    if(state_dma2fx3 == IDLE) begin
+      footer_pointer <= 0;
+      dma2fx3_counter <= 0;
+      case (test_mode_tpg)
+        4'h1: dma2fx3_data_reg <= 32'haaaaaaaa;
+        default:  dma2fx3_data_reg <= 32'hffffffff;
+      endcase
+    end
+
+    if(state_dma2fx3 == READ_DATA) begin
+      footer_pointer <= 4;
+      if (test_mode_active_tpg == 1'b1) begin
+        if (dma2fx3_ready == 1'b1) begin
+          dma2fx3_counter <= dma2fx3_counter + 4;
+          if (dma2fx3_counter >= buffer_size_current - 4) begin
+            dma2fx3_data_reg <= 32'hf00ff00f;
           end else begin
-            s_axis_tready <= 1'b0;
-          end
-          dma2fx3_valid <= s_axis_tvalid & s_axis_tready;
-          if (s_axis_tvalid== 1'b1 && s_axis_tready == 1'b1) begin
-            case (s_axis_tkeep)
-              1: dma2fx3_counter <= dma2fx3_counter + 1;
-              3: dma2fx3_counter <= dma2fx3_counter + 2;
-              7: dma2fx3_counter <= dma2fx3_counter + 3;
-              default: dma2fx3_counter <= dma2fx3_counter + 4;
+            case (test_mode_tpg)
+              4'h1: dma2fx3_data_reg <= ~dma2fx3_data_reg;
+              4'h2: dma2fx3_data_reg <= ~dma2fx3_data_reg;
+              4'h3: dma2fx3_data_reg <= pn9(dma2fx3_data_reg);
+              4'h4: dma2fx3_data_reg <= pn23(dma2fx3_data_reg);
+              4'h7: dma2fx3_data_reg <= dma2fx3_data_reg + 1;
+              default:  dma2fx3_data_reg <= 0;
             endcase
           end
         end
-      end
-      ADD_FOOTER: begin
-        dma2fx3_valid <= ~eot_dma2fx3;
-        dma2fx3_eop <= 1'b0;
-        eot_dma2fx3 <= 1'b0;
-        s_axis_tready <= 1'b0;
-        footer_pointer <= footer_pointer + 4;
-        case(footer_pointer)
-          32'h0: dma2fx3_data <= 32'hf00ff00f;
-          32'h4: dma2fx3_data <= dma2fx3_counter;
-          32'h8: dma2fx3_data <= 32'h0;
-          default: dma2fx3_data <= 32'h0;
-        endcase
-        if (footer_pointer == header_size_current - 4) begin
-          dma2fx3_eop <= 1'b1;
-          eot_dma2fx3 <= 1'b1;
+      end else begin
+          dma2fx3_data_reg <= 32'hf00ff00f;
+        if (s_axis_tvalid== 1'b1 && s_axis_tready == 1'b1) begin
+          case (s_axis_tkeep)
+            1: dma2fx3_counter <= dma2fx3_counter + 1;
+            3: dma2fx3_counter <= dma2fx3_counter + 2;
+            7: dma2fx3_counter <= dma2fx3_counter + 3;
+            default: dma2fx3_counter <= dma2fx3_counter + 4;
+          endcase
         end
       end
-    endcase
+    end
+
+    if(state_dma2fx3 == ADD_FOOTER) begin
+      footer_pointer <= footer_pointer + 4;
+      case(footer_pointer)
+        32'h4: dma2fx3_data_reg <= dma2fx3_counter;
+        32'h8: dma2fx3_data_reg <= 32'h0;
+        default: dma2fx3_data_reg <= 32'h0;
+      endcase
+    end
   end
 
 endmodule
diff --git a/library/axi_usb_fx3/axi_usb_fx3_if.v b/library/axi_usb_fx3/axi_usb_fx3_if.v
index 7e1a1f6aa..088e4a01e 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_if.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_if.v
@@ -45,6 +45,7 @@ module axi_usb_fx3_if (
   fifo_rdy,
 
   pclk,          //output clk 100 Mhz and 180 phase shift
+  reset_n,
 
   data,
   addr,          //output fifo address
@@ -57,11 +58,10 @@ module axi_usb_fx3_if (
   epswitch_n,    //output pkt end
 
   fifo_num,
+  fifo_direction,
   trig,
   fifo_ready,
 
-  test_mode_tpm,
-
   fx32dma_valid,
   fx32dma_ready,
   fx32dma_data,
@@ -73,15 +73,16 @@ module axi_usb_fx3_if (
   dma2fx3_data,
   dma2fx3_eop);
 
+  input           pclk;
+  input           reset_n;
+
   input           dma_rdy;
   input           dma_wmk;
 
-  input  [10:0]   fifo_rdy;
+  input   [ 3:0]  fifo_rdy;
 
-  input           pclk;
-
-  output  [31:0]  data;
-  output  [4:0]   addr;
+  inout   [31:0]  data;
+  output  [ 1:0]  addr;
 
   output          slcs_n;
   output          slrd_n;
@@ -92,9 +93,8 @@ module axi_usb_fx3_if (
 
   output  [10:0]  fifo_ready;
 
-  input   [ 2:0]  test_mode_tpm;
-
-  input   [4:0]   fifo_num;
+  input   [ 4:0]  fifo_num;
+  input   [10:0]  fifo_direction;
   input           trig;
 
   output          fx32dma_valid;
@@ -108,183 +108,227 @@ module axi_usb_fx3_if (
   input   [31:0]  dma2fx3_data;
   input           dma2fx3_eop;
 
-  // internal wires
-
-  wire          fx32dma_sop;
-
   // internal registers
 
-  wire          fx32dma_valid;
 
-  reg   [10:0]  fifo_ready;
+  reg [10:0]  fifo_ready;
 
-  reg           internal_trig = 0;
-  reg           trig_d = 0;
-  reg   [31:0]  internal_counter = 0;
-  reg   [ 2:0]  packet_number = 0;
-  reg   [31:0]  data_size = 0;
-  reg   [31:0]  fx32dma_data = 0;
-  reg   [31:0]  generated_data = 0;
-  reg           fx32dma_eop;
+  reg [31:0]  fx32dma_data = 0;
+  reg         fx32dma_eop;
 
-  reg           transaction_in_progress = 0;
+  reg [ 1:0]  rd_oe_delay;
 
-  assign fx32dma_sop   = internal_trig ;
-  assign fx32dma_valid = transaction_in_progress;
- function [31:0] pn23;
-    input [31:0] din;
-    reg   [31:0] dout;
-    begin
-      dout[31] = din[22] ^ din[17];
-      dout[30] = din[21] ^ din[16];
-      dout[29] = din[20] ^ din[15];
-      dout[28] = din[19] ^ din[14];
-      dout[27] = din[18] ^ din[13];
-      dout[26] = din[17] ^ din[12];
-      dout[25] = din[16] ^ din[11];
-      dout[24] = din[15] ^ din[10];
-      dout[23] = din[14] ^ din[ 9];
-      dout[22] = din[13] ^ din[ 8];
-      dout[21] = din[12] ^ din[ 7];
-      dout[20] = din[11] ^ din[ 6];
-      dout[19] = din[10] ^ din[ 5];
-      dout[18] = din[ 9] ^ din[ 4];
-      dout[17] = din[ 8] ^ din[ 3];
-      dout[16] = din[ 7] ^ din[ 2];
-      dout[15] = din[ 6] ^ din[ 1];
-      dout[14] = din[ 5] ^ din[ 0];
-      dout[13] = din[ 4] ^ din[22] ^ din[17];
-      dout[12] = din[ 3] ^ din[21] ^ din[16];
-      dout[11] = din[ 2] ^ din[20] ^ din[15];
-      dout[10] = din[ 1] ^ din[19] ^ din[14];
-      dout[ 9] = din[ 0] ^ din[18] ^ din[13];
-      dout[ 8] = din[22] ^ din[12];
-      dout[ 7] = din[21] ^ din[11];
-      dout[ 6] = din[20] ^ din[10];
-      dout[ 5] = din[19] ^ din[ 9];
-      dout[ 4] = din[18] ^ din[ 8];
-      dout[ 3] = din[17] ^ din[ 7];
-      dout[ 2] = din[16] ^ din[ 6];
-      dout[ 1] = din[15] ^ din[ 5];
-      dout[ 0] = din[14] ^ din[ 4];
-      pn23 = dout;
-    end
-  endfunction
+  reg [ 3:0]  state_gpif_ii = 4'h0;
+  reg [ 3:0]  next_state_gpif_ii = 4'h0;
 
-  function [31:0] pn9;
-    input [31:0] din;
-    reg   [31:0] dout;
-    begin
-      dout[31] = din[ 8] ^ din[ 4];
-      dout[30] = din[ 7] ^ din[ 3];
-      dout[29] = din[ 6] ^ din[ 2];
-      dout[28] = din[ 5] ^ din[ 1];
-      dout[27] = din[ 4] ^ din[ 0];
-      dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
-      dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
-      dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
-      dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
-      dout[22] = din[ 8] ^ din[ 0];
-      dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
-      dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
-      dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
-      dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
-      dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
-      dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
-      dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
-      dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
-      dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
-      dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
-      dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
-      dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
-      dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
-      dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
-      dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
-      dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
-      dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
-      dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
-      dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
-      dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
-      dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4];
-      dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3];
-      pn9 = dout;
-    end
-  endfunction
+  reg         current_direction;
+  reg         current_fifo;
+  reg         current_fifo_d1;
+  reg         current_fifo_d2;
+  reg         current_fifo_d3;
+  reg         slcs_n;
+  reg         slrd_n;
+  reg         sloe_n;
+  reg [ 1:0]  addr;
+  reg         sloe_n_d1;
+  reg         sloe_n_d2;
+  reg         sloe_n_d3;
+  reg         slwr_n;
+  reg         fx32dma_valid;
+  reg         dma2fx3_ready;
+  reg         fx32dma_sop;
+  reg         fx32dma_sop_d1;
+  reg         pktend_n;
 
-  always @(posedge pclk) begin
-    trig_d <= trig;
-    fx32dma_eop <= 1'b0;
-    internal_trig <= trig & ~trig_d;
-    if (transaction_in_progress == 1'b0) begin
-      transaction_in_progress <= trig & ~trig_d;
-    end else begin
-      if (internal_counter >= data_size + 12) begin
-        transaction_in_progress = 1'b0;
-        fx32dma_eop <= 1'b1;
+  localparam IDLE         = 4'b0001;
+  localparam READ_START   = 4'b0010;
+  localparam READ_DATA    = 4'b0100;
+  localparam WRITE_DATA   = 4'b1000;
+
+  assign data = (state_gpif_ii == WRITE_DATA && dma2fx3_valid && current_fifo) ? {dma2fx3_data[7:0],dma2fx3_data[15:8],dma2fx3_data[23:16], dma2fx3_data[31:24]}  : 32'hz;
+  assign epswitch_n = 1'b1;
+
+  always @(fifo_num, fifo_rdy, fifo_direction) begin
+    case(fifo_num)
+      5'h0: begin
+        current_direction = fifo_direction[0];
+        current_fifo      = fifo_rdy[0];
+      end
+      5'h1: begin
+        current_direction = fifo_direction[1];
+        current_fifo      = fifo_rdy[1];
+      end
+      5'h2: begin
+        current_direction = fifo_direction[2];
+        current_fifo      = fifo_rdy[2];
+      end
+      5'h3: begin
+        current_direction = fifo_direction[3];
+        current_fifo      = fifo_rdy[3];
+      end
+      5'h4: begin
+        current_direction = fifo_direction[4];
+        current_fifo      = fifo_rdy[0];
+      end
+      5'h5: begin
+        current_direction = fifo_direction[5];
+        current_fifo      = fifo_rdy[0];
+      end
+      5'h6: begin
+        current_direction = fifo_direction[6];
+        current_fifo      = fifo_rdy[0];
+      end
+      5'h7: begin
+        current_direction = fifo_direction[7];
+        current_fifo      = fifo_rdy[0];
+      end
+      5'h8: begin
+        current_direction = fifo_direction[8];
+        current_fifo      = fifo_rdy[0];
+      end
+      5'h9: begin
+        current_direction = fifo_direction[9];
+        current_fifo      = fifo_rdy[0];
+      end
+      default: begin
+        current_direction = 0;
+        current_fifo      = fifo_rdy[0];
       end
-    end
-  end
-
-  always @(posedge pclk) begin
-    if (internal_trig == 1'b1 )begin
-      internal_counter <= 4;
-      packet_number <= packet_number + 1;
-    end else if (transaction_in_progress == 1'b1) begin
-      internal_counter <= internal_counter + 4;
-    end else begin
-      internal_counter <= 0;
-    end
-  end
-
-  always @(packet_number) begin
-    case (packet_number)
-      0: data_size = 1;
-      1: data_size = 2;
-      2: data_size = 3;
-      3: data_size = 4;
-      4: data_size = 512;
-      5: data_size = 1024;
-      6: data_size = 32767;
-      7: data_size = 32768;
-      default: data_size = 16;
-    endcase
-  end
-
-  always@(internal_counter, data_size, internal_counter, generated_data) begin
-    case (internal_counter)
-      5'h0: fx32dma_data <= 32'hf00ff00f;
-      5'h4: fx32dma_data <= data_size;
-      5'h8: fx32dma_data <= 0;
-      5'hc: fx32dma_data <= 32'hffffffff;
-      default: fx32dma_data <= generated_data;
     endcase
   end
 
   always @(posedge pclk) begin
-    if (fx32dma_sop == 1'b1) begin
-      if (test_mode_tpm == 3'h1) begin
-        generated_data <= 32'haaaaaaaa;
-      end else begin
-        generated_data <= 32'hffffffff;
-      end
+    if (reset_n == 1'b0) begin
+      state_gpif_ii <= IDLE;
     end else begin
-      case(test_mode_tpm)
-        4'h0: generated_data <= generated_data + 32'h10;
-        4'h1: generated_data <= ~generated_data;
-        4'h2: generated_data <= ~generated_data;
-        4'h3: generated_data <= pn9(generated_data);
-        4'h4: generated_data <= pn23(generated_data);
-        4'h7: generated_data <= generated_data + 1;
-        default: generated_data <= generated_data + 32'h10;
-      endcase
+      state_gpif_ii <= next_state_gpif_ii;
     end
   end
-  // dma2fx3
 
-  assign dma2fx3_ready = 1'b1;
-  assign data = dma2fx3_data;
-  assign pktend_n = ~dma2fx3_eop;
-  assign slwr_n = ~dma2fx3_valid;
+  always @(*) begin
+    case(state_gpif_ii)
+      IDLE:
+        if(trig == 1'b1 && current_fifo == 1'b1) begin
+          if (current_direction == 0) begin
+            next_state_gpif_ii = READ_START;
+          end else begin
+            next_state_gpif_ii = WRITE_DATA;
+          end
+        end else begin
+          next_state_gpif_ii = IDLE;
+        end
+      READ_START:
+        if(rd_oe_delay == 2'h3) begin
+          next_state_gpif_ii = READ_DATA;
+        end else begin
+          next_state_gpif_ii = READ_START;
+        end
+      READ_DATA:
+        if (sloe_n == 1'b1) begin
+          next_state_gpif_ii = IDLE;
+        end else begin
+          next_state_gpif_ii = READ_DATA;
+        end
+      WRITE_DATA:
+        if(dma2fx3_eop == 1'b1) begin
+          next_state_gpif_ii = IDLE;
+        end else begin
+          next_state_gpif_ii = WRITE_DATA;
+        end
+      default: next_state_gpif_ii = IDLE;
+    endcase
+  end
+
+  always @(*) begin
+    case(state_gpif_ii)
+      IDLE: begin
+        slcs_n        = 1'b1;
+        sloe_n        = 1'b1;
+        slrd_n        = 1'b1;
+        fx32dma_valid = 1'b0;
+        fx32dma_sop   = 1'b0;
+        fx32dma_data  = 32'h0;
+        slwr_n        = 1'b1;
+        pktend_n      = 1'b1;
+        dma2fx3_ready = 1'b0;
+        fx32dma_eop   = 1'b0;
+      end
+      READ_START: begin
+        slcs_n        = 1'b0;
+        sloe_n        = 1'b0;
+        slrd_n        = 1'b0;
+        fx32dma_valid = 1'b0;
+        fx32dma_sop   = 1'b0;
+        fx32dma_data  = 32'h0;
+        slwr_n        = 1'b1;
+        pktend_n      = 1'b1;
+        dma2fx3_ready = 1'b0;
+        fx32dma_eop   = 1'b0;
+      end
+      READ_DATA: begin
+        slcs_n        = 1'b0;
+        sloe_n        = sloe_n_d2;
+        slrd_n        = !current_fifo_d3;
+        fx32dma_valid = !sloe_n_d3;
+        fx32dma_sop   = fx32dma_sop_d1;
+        fx32dma_data  = {data[7:0],data[15:8],data[23:16], data[31:24]};
+        //fx32dma_data  =  data;
+        slwr_n        = 1'b1;
+        pktend_n      = 1'b1;
+        dma2fx3_ready = 1'b0;
+        fx32dma_eop   = sloe_n_d2;
+      end
+      WRITE_DATA: begin
+        slcs_n        = 1'b0;
+        sloe_n        = 1'b1;
+        slrd_n        = 1'b1;
+        fx32dma_valid = 1'b0;
+        fx32dma_sop   = 1'b0;
+        fx32dma_data  = 32'h0;
+        slwr_n = (state_gpif_ii == WRITE_DATA) ? (!dma2fx3_valid | !current_fifo) : 1'b1;
+        dma2fx3_ready = current_fifo;
+        pktend_n = (state_gpif_ii == WRITE_DATA ) ? !dma2fx3_eop : 1'b1;
+        fx32dma_eop   = 1'b0;
+      end
+      default: begin
+        slcs_n        = 1'b1;
+        sloe_n        = 1'b1;
+        slrd_n        = 1'b1;
+        fx32dma_valid = 1'b0;
+        fx32dma_sop   = 1'b0;
+        fx32dma_data  = 32'h0;
+        slwr_n        = 1'b1;
+        pktend_n      = 1'b1;
+        dma2fx3_ready = 1'b0;
+        fx32dma_eop   = 1'b0;
+      end
+    endcase
+  end
+
+  always @(posedge pclk) begin
+    current_fifo_d1 <= current_fifo;
+    current_fifo_d2 <= current_fifo_d1;
+    current_fifo_d3 <= current_fifo_d2;
+    fifo_ready <= {7'h0,fifo_rdy};
+    if(state_gpif_ii == READ_DATA) begin
+      fx32dma_sop_d1 <= 1'b0;
+    end else begin
+      fx32dma_sop_d1 <= 1'b1;
+    end
+
+    sloe_n_d1     <= slrd_n;
+    sloe_n_d2     <= sloe_n_d1;
+    sloe_n_d3     <= sloe_n_d2;
+
+    addr          <= fifo_num[1:0];
+
+    if(state_gpif_ii == READ_START) begin
+      rd_oe_delay   <= rd_oe_delay + 1'b1;
+    end else begin
+      rd_oe_delay   <= 2'h0;
+    end
+
+  end
 
 endmodule
 

From 402253d308d301d0972bf3ec30aff1cb21aadcb0 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 19 Apr 2016 15:52:30 +0300
Subject: [PATCH 137/972] usb_fx3: Updated design to include the GPIF II
 interface

---
 projects/usb_fx3/common/usb_fx3_bd.tcl   |  24 ++++--
 projects/usb_fx3/zc706/system_constr.xdc | 102 ++++++++++++-----------
 projects/usb_fx3/zc706/system_top.v      |  50 +++++++----
 3 files changed, 104 insertions(+), 72 deletions(-)

diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl
index 31f75ad6b..9d8a9af56 100644
--- a/projects/usb_fx3/common/usb_fx3_bd.tcl
+++ b/projects/usb_fx3/common/usb_fx3_bd.tcl
@@ -4,10 +4,10 @@ create_bd_port -dir O usb_fx3_uart_rx
 
 create_bd_port -dir I dma_rdy
 create_bd_port -dir I dma_wmk
-create_bd_port -dir I -from 10 -to 0 fifo_rdy
+create_bd_port -dir I -from 3 -to 0 fifo_rdy
 create_bd_port -dir O pclk
-create_bd_port -dir O -from 31 -to 0 data
-create_bd_port -dir O -from 4 -to 0 addr
+create_bd_port -dir IO -from 31 -to 0 data
+create_bd_port -dir O -from 1 -to 0 addr
 create_bd_port -dir O slcs_n
 create_bd_port -dir O slrd_n
 create_bd_port -dir O sloe_n
@@ -21,6 +21,9 @@ set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 a
 
 set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma]
 set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
 
 ad_connect axi_usb_fx3_dma/S_AXIS_S2MM axi_usb_fx3/m_axis
 ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
@@ -57,12 +60,11 @@ ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM
 
 # test
 
-set vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc]
-#ad_connect vcc/dout axi_usb_fx3/m_axis_tready
-
 set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila
+set_property -dict [list CONFIG.C_NUM_OF_PROBES {11}] $ila
+set_property -dict [list CONFIG.C_PROBE10_WIDTH {4}] $ila
+set_property -dict [list CONFIG.C_PROBE3_WIDTH {2}] $ila
 set_property -dict [list CONFIG.C_PROBE2_WIDTH {15}] $ila
 set_property -dict [list CONFIG.C_PROBE1_WIDTH {74}] $ila
 set_property -dict [list CONFIG.C_PROBE0_WIDTH {75}] $ila
@@ -78,3 +80,11 @@ ad_connect ila/clk axi_usb_fx3/pclk
 ad_connect ila/probe0 axi_usb_fx3/debug_fx32dma
 ad_connect ila/probe1 axi_usb_fx3/debug_dma2fx3
 ad_connect ila/probe2 axi_usb_fx3/debug_status
+ad_connect ila/probe3 axi_usb_fx3/addr
+ad_connect ila/probe4 axi_usb_fx3/epswitch_n
+ad_connect ila/probe5 axi_usb_fx3/slcs_n
+ad_connect ila/probe6 axi_usb_fx3/slrd_n
+ad_connect ila/probe7 axi_usb_fx3/sloe_n
+ad_connect ila/probe8 axi_usb_fx3/slwr_n
+ad_connect ila/probe9 axi_usb_fx3/pktend_n
+ad_connect ila/probe10 fifo_rdy
diff --git a/projects/usb_fx3/zc706/system_constr.xdc b/projects/usb_fx3/zc706/system_constr.xdc
index c425d3f2d..e09775cbb 100644
--- a/projects/usb_fx3/zc706/system_constr.xdc
+++ b/projects/usb_fx3/zc706/system_constr.xdc
@@ -2,64 +2,66 @@
 # constraints
 # USB_FX3
 
-#set_property  -dict {PACKAGE_PIN  AG17  IOSTANDARD LVCMOS33} [get_ports data[0]]        ; ## H04   FMC_LPC_CLK0_M2C_P
-#set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVCMOS33} [get_ports data[1]]        ; ## H07   FMC_LPC_LA02_P
-#set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVCMOS33} [get_ports data[2]]        ; ## H08   FMC_LPC_LA02_N
-#set_property  -dict {PACKAGE_PIN  AJ15  IOSTANDARD LVCMOS33} [get_ports data[3]]        ; ## H10   FMC_LPC_LA04_P
-#set_property  -dict {PACKAGE_PIN  AK15  IOSTANDARD LVCMOS33} [get_ports data[4]]        ; ## H11   FMC_LPC_LA04_N
-#set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVCMOS33} [get_ports data[5]]        ; ## H13   FMC_LPC_LA07_P
-#set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS33} [get_ports data[6]]        ; ## H14   FMC_LPC_LA07_N
-#set_property  -dict {PACKAGE_PIN  AJ16  IOSTANDARD LVCMOS33} [get_ports data[7]]        ; ## H16   FMC_LPC_LA11_P
-#set_property  -dict {PACKAGE_PIN  AK16  IOSTANDARD LVCMOS33} [get_ports data[8]]        ; ## H17   FMC_LPC_LA11_N
-#set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS33} [get_ports data[9]]        ; ## H19   FMC_LPC_LA15_P
-#set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS33} [get_ports data[10]]       ; ## H20   FMC_LPC_LA15_N
-#set_property  -dict {PACKAGE_PIN  AH26  IOSTANDARD LVCMOS33} [get_ports data[11]]       ; ## H22   FMC_LPC_LA19_P
-#set_property  -dict {PACKAGE_PIN  AH27  IOSTANDARD LVCMOS33} [get_ports data[12]]       ; ## H23   FMC_LPC_LA19_N
-#set_property  -dict {PACKAGE_PIN  AH28  IOSTANDARD LVCMOS33} [get_ports data[13]]       ; ## H25   FMC_LPC_LA21_P
-#set_property  -dict {PACKAGE_PIN  AH29  IOSTANDARD LVCMOS33} [get_ports data[14]]       ; ## H26   FMC_LPC_LA21_N
-#set_property  -dict {PACKAGE_PIN  AF30  IOSTANDARD LVCMOS33} [get_ports data[15]]       ; ## H28   FMC_LPC_LA24_P
-#set_property  -dict {PACKAGE_PIN  AG30  IOSTANDARD LVCMOS33} [get_ports data[16]]       ; ## H29   FMC_LPC_LA24_N
-#set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVCMOS33} [get_ports data[17]]       ; ## H31   FMC_LPC_LA28_P
-#set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVCMOS33} [get_ports data[18]]       ; ## H32   FMC_LPC_LA28_N
-#set_property  -dict {PACKAGE_PIN  AB29  IOSTANDARD LVCMOS33} [get_ports data[19]]       ; ## H34   FMC_LPC_LA30_P
-#set_property  -dict {PACKAGE_PIN  AB30  IOSTANDARD LVCMOS33} [get_ports data[20]]       ; ## H35   FMC_LPC_LA30_N
-#set_property  -dict {PACKAGE_PIN  Y26   IOSTANDARD LVCMOS33} [get_ports data[21]]       ; ## H37   FMC_LPC_LA32_P
-#set_property  -dict {PACKAGE_PIN  Y27   IOSTANDARD LVCMOS33} [get_ports data[22]]       ; ## H38   FMC_LPC_LA32_N
-#set_property  -dict {PACKAGE_PIN  AC28  IOSTANDARD LVCMOS33} [get_ports data[23]]       ; ## G02   FMC_LPC_CLK1_M2C_P
-#set_property  -dict {PACKAGE_PIN  AD28  IOSTANDARD LVCMOS33} [get_ports data[24]]       ; ## G03   FMC_LPC_CLK1_M2C_N
-#set_property  -dict {PACKAGE_PIN  AG12  IOSTANDARD LVCMOS33} [get_ports data[25]]       ; ## G09   FMC_LPC_LA03_P
-#set_property  -dict {PACKAGE_PIN  AH12  IOSTANDARD LVCMOS33} [get_ports data[26]]       ; ## G10   FMC_LPC_LA03_N
-#set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVCMOS33} [get_ports data[27]]       ; ## G12   FMC_LPC_LA08_P
-#set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVCMOS33} [get_ports data[28]]       ; ## G13   FMC_LPC_LA08_N
-#set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVCMOS33} [get_ports data[29]]       ; ## G15   FMC_LPC_LA12_P
-#set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVCMOS33} [get_ports data[30]]       ; ## G16   FMC_LPC_LA12_N
-#set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports data[31]]       ; ## G18   FMC_LPC_LA16_P
-#
-#set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVCMOS33} [get_ports pclk]           ; ## G06   FMC_LPC_LA00_CC_P
-#
-#set_property  -dict {PACKAGE_PIN  AA30  IOSTANDARD LVCMOS33} [get_ports addr[0]]        ; ## G37   FMC_LPC_LA33_N
-#set_property  -dict {PACKAGE_PIN  Y30   IOSTANDARD LVCMOS33} [get_ports addr[1]]        ; ## G36   FMC_LPC_LA33_P
-#set_property  -dict {PACKAGE_PIN  AD29  IOSTANDARD LVCMOS33} [get_ports addr[2]]        ; ## G34   FMC_LPC_LA31_N
-#set_property  -dict {PACKAGE_PIN  AC29  IOSTANDARD LVCMOS33} [get_ports addr[3]]        ; ## G33   FMC_LPC_LA31_P
+set_property  -dict {PACKAGE_PIN  AG17  IOSTANDARD LVCMOS25} [get_ports data[0]]        ; ## H04   FMC_LPC_CLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVCMOS25} [get_ports data[1]]        ; ## H07   FMC_LPC_LA02_P
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVCMOS25} [get_ports data[2]]        ; ## H08   FMC_LPC_LA02_N
+set_property  -dict {PACKAGE_PIN  AJ15  IOSTANDARD LVCMOS25} [get_ports data[3]]        ; ## H10   FMC_LPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AK15  IOSTANDARD LVCMOS25} [get_ports data[4]]        ; ## H11   FMC_LPC_LA04_N
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVCMOS25} [get_ports data[5]]        ; ## H13   FMC_LPC_LA07_P
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS25} [get_ports data[6]]        ; ## H14   FMC_LPC_LA07_N
+set_property  -dict {PACKAGE_PIN  AJ16  IOSTANDARD LVCMOS25} [get_ports data[7]]        ; ## H16   FMC_LPC_LA11_P
+set_property  -dict {PACKAGE_PIN  AK16  IOSTANDARD LVCMOS25} [get_ports data[8]]        ; ## H17   FMC_LPC_LA11_N
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25} [get_ports data[9]]        ; ## H19   FMC_LPC_LA15_P
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25} [get_ports data[10]]       ; ## H20   FMC_LPC_LA15_N
+set_property  -dict {PACKAGE_PIN  AH26  IOSTANDARD LVCMOS25} [get_ports data[11]]       ; ## H22   FMC_LPC_LA19_P
+set_property  -dict {PACKAGE_PIN  AH27  IOSTANDARD LVCMOS25} [get_ports data[12]]       ; ## H23   FMC_LPC_LA19_N
+set_property  -dict {PACKAGE_PIN  AH28  IOSTANDARD LVCMOS25} [get_ports data[13]]       ; ## H25   FMC_LPC_LA21_P
+set_property  -dict {PACKAGE_PIN  AH29  IOSTANDARD LVCMOS25} [get_ports data[14]]       ; ## H26   FMC_LPC_LA21_N
+set_property  -dict {PACKAGE_PIN  AF30  IOSTANDARD LVCMOS25} [get_ports data[15]]       ; ## H28   FMC_LPC_LA24_P
+set_property  -dict {PACKAGE_PIN  AG30  IOSTANDARD LVCMOS25} [get_ports data[16]]       ; ## H29   FMC_LPC_LA24_N
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVCMOS25} [get_ports data[17]]       ; ## H31   FMC_LPC_LA28_P
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVCMOS25} [get_ports data[18]]       ; ## H32   FMC_LPC_LA28_N
+set_property  -dict {PACKAGE_PIN  AB29  IOSTANDARD LVCMOS25} [get_ports data[19]]       ; ## H34   FMC_LPC_LA30_P
+set_property  -dict {PACKAGE_PIN  AB30  IOSTANDARD LVCMOS25} [get_ports data[20]]       ; ## H35   FMC_LPC_LA30_N
+set_property  -dict {PACKAGE_PIN  Y26   IOSTANDARD LVCMOS25} [get_ports data[21]]       ; ## H37   FMC_LPC_LA32_P
+set_property  -dict {PACKAGE_PIN  Y27   IOSTANDARD LVCMOS25} [get_ports data[22]]       ; ## H38   FMC_LPC_LA32_N
+set_property  -dict {PACKAGE_PIN  AC28  IOSTANDARD LVCMOS25} [get_ports data[23]]       ; ## G02   FMC_LPC_CLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  AD28  IOSTANDARD LVCMOS25} [get_ports data[24]]       ; ## G03   FMC_LPC_CLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  AG12  IOSTANDARD LVCMOS25} [get_ports data[25]]       ; ## G09   FMC_LPC_LA03_P
+set_property  -dict {PACKAGE_PIN  AH12  IOSTANDARD LVCMOS25} [get_ports data[26]]       ; ## G10   FMC_LPC_LA03_N
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVCMOS25} [get_ports data[27]]       ; ## G12   FMC_LPC_LA08_P
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVCMOS25} [get_ports data[28]]       ; ## G13   FMC_LPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVCMOS25} [get_ports data[29]]       ; ## G15   FMC_LPC_LA12_P
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVCMOS25} [get_ports data[30]]       ; ## G16   FMC_LPC_LA12_N
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports data[31]]       ; ## G18   FMC_LPC_LA16_P
+
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVCMOS25} [get_ports pclk]           ; ## G06   FMC_LPC_LA00_CC_P
+
+set_property  -dict {PACKAGE_PIN  AA30  IOSTANDARD LVCMOS25} [get_ports addr[0]]        ; ## G37   FMC_LPC_LA33_N
+set_property  -dict {PACKAGE_PIN  Y30   IOSTANDARD LVCMOS25} [get_ports addr[1]]        ; ## G36   FMC_LPC_LA33_P
+#set_property  -dict {PACKAGE_PIN  AD29  IOSTANDARD LVCMOS25} [get_ports addr[2]]        ; ## G34   FMC_LPC_LA31_N
+#set_property  -dict {PACKAGE_PIN  AC29  IOSTANDARD LVCMOS25} [get_ports addr[3]]        ; ## G33   FMC_LPC_LA31_P
 #set_property  -dict {PACKAGE_PIN  AF25  IOSTANDARD LVCMOS33} [get_ports addr[4]]        ; ## G31   FMC_LPC_LA29_N
-#
-#set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS33} [get_ports slcs_n]         ; ## G19   FMC_LPC_LA16_N
-#set_property  -dict {PACKAGE_PIN  AG26  IOSTANDARD LVCMOS33} [get_ports slwr_n]         ; ## G21   FMC_LPC_LA20_P
-#set_property  -dict {PACKAGE_PIN  AG27  IOSTANDARD LVCMOS33} [get_ports sloe_n]         ; ## G22   FMC_LPC_LA20_N
-#set_property  -dict {PACKAGE_PIN  AK27  IOSTANDARD LVCMOS33} [get_ports slrd_n]         ; ## G24   FMC_LPC_LA22_P
-#set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVCMOS33} [get_ports pktend_n]       ; ## G30   FMC_LPC_LA29_P
+
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports slcs_n]         ; ## G19   FMC_LPC_LA16_N
+set_property  -dict {PACKAGE_PIN  AG26  IOSTANDARD LVCMOS25} [get_ports slwr_n]         ; ## G21   FMC_LPC_LA20_P
+set_property  -dict {PACKAGE_PIN  AG27  IOSTANDARD LVCMOS25} [get_ports sloe_n]         ; ## G22   FMC_LPC_LA20_N
+set_property  -dict {PACKAGE_PIN  AK27  IOSTANDARD LVCMOS25} [get_ports slrd_n]         ; ## G24   FMC_LPC_LA22_P
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVCMOS25} [get_ports pktend_n]       ; ## G30   FMC_LPC_LA29_P
 
 set_property  -dict {PACKAGE_PIN  AJ21  IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_tx] ; ## PMOD1_0, Connector J58 pin 1, 3.3V through level shifter
 set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_rx] ; ## PMOD1_4, Connector J58 pin 2, 3.3V through level shifter
 
-#set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[0]]       ; ## G18   FMC_LPC_LA16_P
-#set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[1]]       ; ## G18   FMC_LPC_LA16_P
-#set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[2]]       ; ## G18   FMC_LPC_LA16_P
-#set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[3]]       ; ## G18   FMC_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AK28  IOSTANDARD LVCMOS25} [get_ports fifo_rdy[0]]       ; ## G25   FMC_LPC_LA22_N
+set_property  -dict {PACKAGE_PIN  AF29  IOSTANDARD LVCMOS25} [get_ports fifo_rdy[1]]       ; ## G27   FMC_LPC_LA25_P
+set_property  -dict {PACKAGE_PIN  AG29  IOSTANDARD LVCMOS25} [get_ports fifo_rdy[2]]       ; ## G28   FMC_LPC_LA25_N
+set_property  -dict {PACKAGE_PIN  AF25  IOSTANDARD LVCMOS25} [get_ports fifo_rdy[3]]       ; ## G31   FMC_LPC_LA29_N
 #set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[4]]       ; ## G18   FMC_LPC_LA16_P
 #set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[5]]       ; ## G18   FMC_LPC_LA16_P
 #set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[6]]       ; ## G18   FMC_LPC_LA16_P
 #set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[7]]       ; ## G18   FMC_LPC_LA16_P
 #set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[8]]       ; ## G18   FMC_LPC_LA16_P
 #set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[9]]       ; ## G18   FMC_LPC_LA16_P
-#set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[10]]       ; ## G18   FMC_LPC_LA16_P
+#set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS33} [get_ports fifo_rdy[10]]      ; ## G18   FMC_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVCMOS25} [get_ports pmode[0]]       ; ## D11   FMC_LPC_LA05_P
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVCMOS25} [get_ports pmode[1]]       ; ## D12   FMC_LPC_LA05_N
diff --git a/projects/usb_fx3/zc706/system_top.v b/projects/usb_fx3/zc706/system_top.v
index d21458d0f..4b9eb12b7 100644
--- a/projects/usb_fx3/zc706/system_top.v
+++ b/projects/usb_fx3/zc706/system_top.v
@@ -69,6 +69,22 @@ module system_top (
   usb_fx3_uart_tx,
   usb_fx3_uart_rx,
 
+//  dma_rdy,
+//  dma_wmk,
+  fifo_rdy,
+
+  data,
+  addr,
+  pclk,
+  slcs_n,
+  slrd_n,
+  sloe_n,
+  slwr_n,
+  //epswitch_n,
+  pktend_n,
+
+  pmode,
+
   hdmi_out_clk,
   hdmi_vsync,
   hdmi_hsync,
@@ -108,6 +124,22 @@ module system_top (
   input           usb_fx3_uart_tx;
   output          usb_fx3_uart_rx;
 
+//  input           dma_rdy;
+//  input           dma_wmk;
+  input   [ 3:0]  fifo_rdy;
+
+  inout   [31:0]  data;
+  output  [1:0]   addr;
+  output          pclk;
+  output          slcs_n;
+  output          slrd_n;
+  output          sloe_n;
+  output          slwr_n;
+  //output          epswitch_n;
+  output          pktend_n;
+
+  output  [ 1:0]  pmode;
+
   output          hdmi_out_clk;
   output          hdmi_vsync;
   output          hdmi_hsync;
@@ -125,20 +157,8 @@ module system_top (
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
-  wire            usb_fx3_uart_tx;
-  wire            usb_fx3_uart_rx;
-  wire            dma_rdy;
-  wire            dma_wmk;
-  wire    [10:0]  fifo_rdy;
-  wire            pclk;
-  wire    [31:0]  data;
-  wire    [4:0]   addr;
-  wire            slcs_n;
-  wire            slrd_n;
-  wire            sloe_n;
-  wire            slwr_n;
-  wire            epswitch_n;
-  wire            pktend_n;
+
+  assign pmode = 2'b11;
 
   // instantiations
 
@@ -194,7 +214,7 @@ module system_top (
     .slrd_n(slrd_n),
     .sloe_n(sloe_n),
     .slwr_n(slwr_n),
-    .epswitch_n(epswitch_n),
+  // .epswitch_n(epswitch_n),
     .pktend_n(pktend_n),
     .ps_intr_00 (1'b0),
     .ps_intr_01 (1'b0),

From e9b199959a1c0fcd9a7da72e0df78df8d420f393 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 20 Apr 2016 15:57:25 -0400
Subject: [PATCH 138/972] library/adcfifo- constraints update

---
 library/util_adcfifo/util_adcfifo_constr.sdc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/util_adcfifo/util_adcfifo_constr.sdc b/library/util_adcfifo/util_adcfifo_constr.sdc
index 70249724e..1edeab40d 100755
--- a/library/util_adcfifo/util_adcfifo_constr.sdc
+++ b/library/util_adcfifo/util_adcfifo_constr.sdc
@@ -1,4 +1,4 @@
 
 set_false_path -from [get_registers *adc_waddr*] -to [get_registers *dma_waddr*]
-set_false_path -from [get_registers *dma_xfer*] -to [get_registers *adc_xfer*]
-set_false_path -to [get_registers *adc_xfer_req_m*]
+set_false_path -to [get_registers *adc_xfer_req_m[0]*]
+

From 8b2542b181e4b0e6c582fadeb8e14e38f3951ed8 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 20 Apr 2016 16:01:12 -0400
Subject: [PATCH 139/972] daq2/a10gx: 10AX115S3F45E2SGE3 version

---
 projects/common/a10gx/a10gx_system_assign.tcl |  7 ++++---
 projects/common/a10gx/a10gx_system_bd.qsys    | 14 +++++++-------
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl
index 0bb026b18..145c90666 100755
--- a/projects/common/a10gx/a10gx_system_assign.tcl
+++ b/projects/common/a10gx/a10gx_system_assign.tcl
@@ -2,13 +2,14 @@
 # device settings
 
 set_global_assignment -name FAMILY "Arria 10"
-set_global_assignment -name DEVICE 10AX115S2F45I2SG
+set_global_assignment -name DEVICE 10AX115S3F45E2SGE3
 
 # clocks and resets
 
-set_location_assignment PIN_BD32  -to sys_clk
+set_location_assignment PIN_AR36  -to sys_clk
+set_location_assignment PIN_AR37  -to "sys_clk(n)"
 set_location_assignment PIN_BD27  -to sys_resetn
-set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_clk
+set_instance_assignment -name IO_STANDARD LVDS -to sys_clk
 set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn
 
 # ddr3
diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys
index edbe253f0..7bdd08068 100644
--- a/projects/common/a10gx/a10gx_system_bd.qsys
+++ b/projects/common/a10gx/a10gx_system_bd.qsys
@@ -601,7 +601,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S2F45I2SG" />
+ <parameter name="device" value="10AX115S3F45E2SGE3" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -733,7 +733,7 @@
  <module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
   <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
   <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
-  <parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="bht_ramBlockType" value="Automatic" />
   <parameter name="breakOffset" value="32" />
@@ -803,7 +803,7 @@
   <parameter name="mmu_TLBMissExcOffset" value="4096" />
   <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
   <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="true" />
+  <parameter name="mmu_enabled" value="false" />
   <parameter name="mmu_processIDNumBits" value="8" />
   <parameter name="mmu_ramBlockType" value="Automatic" />
   <parameter name="mmu_tlbNumWays" value="16" />
@@ -1862,14 +1862,14 @@
   <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
   <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR3" />
   <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
-  <parameter name="SYS_INFO_DEVICE" value="10AX115S2F45I2SG" />
+  <parameter name="SYS_INFO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
   <parameter name="TRAIT_SUPPORTS_VID" value="0" />
  </module>
  <module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="core_variation" value="MAC_PCS" />
   <parameter name="deviceFamilyName" value="Arria 10" />
@@ -1922,7 +1922,7 @@
   <parameter
      name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
      value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
@@ -1968,7 +1968,7 @@
   <parameter
      name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
      value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>

From e00236e5fd19ada1dd8235901c0282d0aa9b6214 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 20 Apr 2016 16:04:46 -0400
Subject: [PATCH 140/972] daq2/a10gx: 10AX115S3F45E2SGE3 version

---
 projects/daq2/common/daq2_bd.qsys | 332 ++++++++++++++++++++++--------
 1 file changed, 243 insertions(+), 89 deletions(-)

diff --git a/projects/daq2/common/daq2_bd.qsys b/projects/daq2/common/daq2_bd.qsys
index fcabfb523..d61b9f7ba 100755
--- a/projects/daq2/common/daq2_bd.qsys
+++ b/projects/daq2/common/daq2_bd.qsys
@@ -13,7 +13,7 @@
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "11";
          type = "int";
       }
    }
@@ -21,7 +21,7 @@
    {
       datum _sortIndex
       {
-         value = "14";
+         value = "16";
          type = "int";
       }
    }
@@ -37,7 +37,7 @@
    {
       datum _sortIndex
       {
-         value = "12";
+         value = "14";
          type = "int";
       }
    }
@@ -53,7 +53,7 @@
    {
       datum _sortIndex
       {
-         value = "11";
+         value = "13";
          type = "int";
       }
    }
@@ -69,7 +69,7 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "10";
          type = "int";
       }
       datum sopceditor_expanded
@@ -90,7 +90,7 @@
    {
       datum _sortIndex
       {
-         value = "15";
+         value = "17";
          type = "int";
       }
    }
@@ -413,11 +413,6 @@
          value = "2";
          type = "int";
       }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
    }
    element mem_rst
    {
@@ -426,11 +421,6 @@
          value = "3";
          type = "int";
       }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
    }
    element sys_clk
    {
@@ -439,11 +429,6 @@
          value = "0";
          type = "int";
       }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
    }
    element sys_rst
    {
@@ -452,11 +437,6 @@
          value = "1";
          type = "int";
       }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
    }
    element system_bd
    {
@@ -662,7 +642,7 @@
    {
       datum _sortIndex
       {
-         value = "10";
+         value = "12";
          type = "int";
       }
    }
@@ -670,7 +650,7 @@
    {
       datum _sortIndex
       {
-         value = "13";
+         value = "15";
          type = "int";
       }
    }
@@ -678,7 +658,7 @@
    {
       datum _sortIndex
       {
-         value = "18";
+         value = "20";
          type = "int";
       }
    }
@@ -686,7 +666,7 @@
    {
       datum _sortIndex
       {
-         value = "16";
+         value = "18";
          type = "int";
       }
    }
@@ -694,7 +674,15 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "8";
+         type = "int";
+      }
+   }
+   element xcvr_rx_pll_reconfig
+   {
+      datum _sortIndex
+      {
+         value = "9";
          type = "int";
       }
    }
@@ -702,7 +690,7 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "7";
          type = "int";
       }
    }
@@ -710,7 +698,7 @@
    {
       datum _sortIndex
       {
-         value = "17";
+         value = "19";
          type = "int";
       }
    }
@@ -722,6 +710,14 @@
          type = "int";
       }
    }
+   element xcvr_tx_pll_reconfig
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
    element xcvr_tx_ref_clk
    {
       datum _sortIndex
@@ -729,16 +725,11 @@
          value = "4";
          type = "int";
       }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
    }
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S2F45I2SG" />
+ <parameter name="device" value="10AX115S3F45E2SGE3" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -846,6 +837,36 @@
    internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
    type="conduit"
    dir="end" />
+ <interface
+   name="xcvr_core_jesd204_rx_s_avl"
+   internal="xcvr_core.jesd204_rx_avs"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_core_jesd204_tx_s_avl"
+   internal="xcvr_core.jesd204_tx_avs"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_core_reconfig_s_avl"
+   internal="xcvr_core.reconfig_avmm"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_rx_pll_reconfig_s_avl"
+   internal="xcvr_rx_pll_reconfig.mgmt_avalon_slave"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_tx_lane_pll_s_avl"
+   internal="xcvr_tx_lane_pll.reconfig_avmm0"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_tx_pll_reconfig_s_avl"
+   internal="xcvr_tx_pll_reconfig.mgmt_avalon_slave"
+   type="avalon"
+   dir="end" />
  <module name="ad9680_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
   <parameter name="ADC_DATA_WIDTH" value="128" />
   <parameter name="DMA_ADDRESS_WIDTH" value="16" />
@@ -934,7 +955,7 @@
  <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
   <parameter name="ADJCNT" value="0" />
   <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="BID" value="0" />
   <parameter name="CF" value="0" />
@@ -983,13 +1004,13 @@
   <parameter name="bonded_mode" value="non_bonded" />
   <parameter name="lane_rate" value="10000.0" />
   <parameter name="part_trait_bd" value="NIGHTFURY5" />
-  <parameter name="part_trait_dp" value="10AX115S2F45I2SG" />
-  <parameter name="pll_reconfig_enable" value="false" />
+  <parameter name="part_trait_dp" value="10AX115S3F45E2SGE3" />
+  <parameter name="pll_reconfig_enable" value="true" />
   <parameter name="pll_type" value="CMU" />
   <parameter name="rcfg_jtag_enable" value="false" />
   <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="false" />
-  <parameter name="set_csr_soft_logic_enable" value="false" />
+  <parameter name="set_capability_reg_enable" value="true" />
+  <parameter name="set_csr_soft_logic_enable" value="true" />
   <parameter name="set_prbs_soft_logic_enable" value="false" />
   <parameter name="set_user_identifier" value="0" />
   <parameter name="wrapper_opt" value="base_phy" />
@@ -1003,19 +1024,19 @@
   <parameter name="PLLS" value="1" />
   <parameter name="REDUCED_SIM_TIME" value="1" />
   <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="1" />
+  <parameter name="RX_PER_CHANNEL" value="0" />
   <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
   <parameter name="SYNCHRONIZE_RESET" value="1" />
   <parameter name="SYS_CLK_IN_MHZ" value="100" />
   <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="1" />
+  <parameter name="TX_PER_CHANNEL" value="0" />
   <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="1000" />
+  <parameter name="T_PLL_LOCK_HYST" value="0" />
   <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="100000" />
-  <parameter name="T_RX_DIGITALRESET" value="100000" />
-  <parameter name="T_TX_ANALOGRESET" value="100000" />
-  <parameter name="T_TX_DIGITALRESET" value="100000" />
+  <parameter name="T_RX_ANALOGRESET" value="70000" />
+  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_ANALOGRESET" value="70000" />
+  <parameter name="T_TX_DIGITALRESET" value="70000" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="gui_pll_cal_busy" value="1" />
   <parameter name="gui_rx_auto_reset" value="0" />
@@ -1199,7 +1220,7 @@
   <parameter name="gui_en_extclkout_ports" value="false" />
   <parameter name="gui_en_lvds_ports" value="Disabled" />
   <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_en_reconf" value="true" />
   <parameter name="gui_enable_cascade_in" value="false" />
   <parameter name="gui_enable_cascade_out" value="false" />
   <parameter name="gui_enable_mif_dps" value="false" />
@@ -1300,11 +1321,21 @@
   <parameter name="gui_use_NDFB_modes" value="false" />
   <parameter name="gui_use_locked" value="false" />
   <parameter name="gui_vco_frequency" value="600.0" />
-  <parameter name="system_info_device_component" value="10AX115S2F45I2SG" />
+  <parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
   <parameter name="system_info_device_family" value="Arria 10" />
   <parameter name="system_info_device_speed_grade" value="2" />
   <parameter name="system_part_trait_speed_grade" value="2" />
  </module>
+ <module
+   name="xcvr_rx_pll_reconfig"
+   kind="altera_pll_reconfig"
+   version="15.1"
+   enabled="1">
+  <parameter name="ENABLE_BYTEENABLE" value="false" />
+  <parameter name="ENABLE_MIF" value="false" />
+  <parameter name="MIF_FILE_NAME" value="" />
+  <parameter name="device_family" value="Arria 10" />
+ </module>
  <module
    name="xcvr_rx_ref_clk"
    kind="altera_clock_bridge"
@@ -1316,29 +1347,42 @@
  </module>
  <module
    name="xcvr_tx_lane_pll"
-   kind="altera_xcvr_cdr_pll_a10"
+   kind="altera_xcvr_atx_pll_a10"
    version="15.1"
    enabled="1">
   <parameter name="base_device" value="NIGHTFURY5" />
-  <parameter name="bw_sel" value="Medium" />
-  <parameter name="cdr_pll_cgb_div" value="1" />
-  <parameter name="cdr_pll_initial_settings" value="true" />
-  <parameter name="cdr_pll_is_cascaded_pll" value="false" />
-  <parameter name="cdr_pll_optimal" value="false" />
-  <parameter name="device" value="10AX115S2F45I2SG" />
+  <parameter name="bw_sel" value="medium" />
+  <parameter name="device" value="10AX115S3F45E2SGE3" />
   <parameter name="device_family" value="Arria 10" />
-  <parameter name="diag_loopback_enable" value="false" />
+  <parameter name="enable_16G_path" value="0" />
+  <parameter name="enable_8G_path" value="1" />
   <parameter name="enable_analog_resets" value="0" />
-  <parameter name="enable_pll_reconfig" value="0" />
+  <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
+  <parameter name="enable_bonding_clks" value="0" />
+  <parameter name="enable_cascade_out" value="0" />
+  <parameter name="enable_debug_ports_parameters" value="0" />
+  <parameter name="enable_fb_comp_bonding" value="0" />
+  <parameter name="enable_fractional" value="0" />
+  <parameter name="enable_hfreq_clk" value="0" />
+  <parameter name="enable_hip_cal_done_port" value="0" />
+  <parameter name="enable_manual_configuration" value="1" />
+  <parameter name="enable_mcgb" value="0" />
+  <parameter name="enable_mcgb_pcie_clksw" value="0" />
+  <parameter name="enable_pcie_clk" value="0" />
+  <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+  <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+  <parameter name="enable_pll_reconfig" value="1" />
   <parameter name="generate_add_hdl_instance_example" value="0" />
   <parameter name="generate_docs" value="1" />
-  <parameter name="gui_tx_pll_prot_mode" value="Basic" />
-  <parameter name="manual_counters" value="" />
+  <parameter name="mcgb_aux_clkin_cnt" value="0" />
+  <parameter name="mcgb_div" value="1" />
   <parameter name="message_level" value="error" />
-  <parameter name="output_clock_frequency" value="5000" />
+  <parameter name="pma_width" value="64" />
+  <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+  <parameter name="prot_mode" value="Basic" />
   <parameter name="rcfg_debug" value="0" />
   <parameter name="rcfg_enable_avmm_busy_port" value="0" />
-  <parameter name="rcfg_file_prefix">altera_xcvr_cdr_pll_a10</parameter>
+  <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
   <parameter name="rcfg_h_file_enable" value="0" />
   <parameter name="rcfg_jtag_enable" value="0" />
   <parameter name="rcfg_mif_file_enable" value="0" />
@@ -1347,19 +1391,30 @@
   <parameter name="rcfg_param_vals2" value="" />
   <parameter name="rcfg_profile_cnt" value="2" />
   <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_separate_avmm_busy" value="0" />
+  <parameter name="rcfg_separate_avmm_busy" value="1" />
   <parameter name="rcfg_sv_file_enable" value="0" />
   <parameter name="rcfg_txt_file_enable" value="0" />
   <parameter name="refclk_cnt" value="1" />
   <parameter name="refclk_index" value="0" />
-  <parameter name="refclk_select_mux_powerdown_mode" value="powerup" />
-  <parameter name="reference_clock_frequency" value="500.0" />
   <parameter name="select_manual_config" value="false" />
-  <parameter name="set_altera_xcvr_cdr_pll_a10_calibration_en" value="1" />
-  <parameter name="set_capability_reg_enable" value="0" />
-  <parameter name="set_csr_soft_logic_enable" value="0" />
+  <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
+  <parameter name="set_auto_reference_clock_frequency" value="500.0" />
+  <parameter name="set_capability_reg_enable" value="1" />
+  <parameter name="set_csr_soft_logic_enable" value="1" />
+  <parameter name="set_fref_clock_frequency" value="156.25" />
+  <parameter name="set_hip_cal_en" value="0" />
+  <parameter name="set_k_counter" value="2000000000" />
+  <parameter name="set_l_cascade_counter" value="15" />
+  <parameter name="set_l_cascade_predivider" value="1" />
+  <parameter name="set_l_counter" value="16" />
+  <parameter name="set_m_counter" value="24" />
+  <parameter name="set_manual_reference_clock_frequency" value="200.0" />
+  <parameter name="set_output_clock_frequency" value="5000.0" />
+  <parameter name="set_ref_clk_div" value="1" />
   <parameter name="set_user_identifier" value="0" />
+  <parameter name="silicon_rev" value="false" />
   <parameter name="support_mode" value="user_mode" />
+  <parameter name="test_mode" value="0" />
  </module>
  <module name="xcvr_tx_pll" kind="altera_iopll" version="15.1" enabled="1">
   <parameter name="gui_active_clk" value="false" />
@@ -1538,7 +1593,7 @@
   <parameter name="gui_en_extclkout_ports" value="false" />
   <parameter name="gui_en_lvds_ports" value="Disabled" />
   <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_en_reconf" value="true" />
   <parameter name="gui_enable_cascade_in" value="false" />
   <parameter name="gui_enable_cascade_out" value="false" />
   <parameter name="gui_enable_mif_dps" value="false" />
@@ -1639,11 +1694,21 @@
   <parameter name="gui_use_NDFB_modes" value="false" />
   <parameter name="gui_use_locked" value="false" />
   <parameter name="gui_vco_frequency" value="600.0" />
-  <parameter name="system_info_device_component" value="10AX115S2F45I2SG" />
+  <parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
   <parameter name="system_info_device_family" value="Arria 10" />
   <parameter name="system_info_device_speed_grade" value="2" />
   <parameter name="system_part_trait_speed_grade" value="2" />
  </module>
+ <module
+   name="xcvr_tx_pll_reconfig"
+   kind="altera_pll_reconfig"
+   version="15.1"
+   enabled="1">
+  <parameter name="ENABLE_BYTEENABLE" value="false" />
+  <parameter name="ENABLE_MIF" value="false" />
+  <parameter name="MIF_FILE_NAME" value="" />
+  <parameter name="device_family" value="Arria 10" />
+ </module>
  <module
    name="xcvr_tx_ref_clk"
    kind="altera_clock_bridge"
@@ -1700,11 +1765,31 @@
    version="15.1"
    start="mem_clk.out_clk"
    end="axi_ad9144_dma.m_src_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_tx_pll_reconfig.mgmt_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_rx_pll_reconfig.mgmt_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="xcvr_tx_ref_clk.out_clk"
    end="xcvr_tx_lane_pll.pll_refclk0" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_core.reconfig_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_tx_lane_pll.reconfig_clk0" />
  <connection
    kind="clock"
    version="15.1"
@@ -1993,17 +2078,6 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_ready"
-   end="xcvr_rst_cntrl.tx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
  <connection
    kind="conduit"
    version="15.1"
@@ -2029,8 +2103,52 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="xcvr_tx_lane_pll.pll_powerdown"
-   end="xcvr_rst_cntrl.pll_powerdown">
+   start="xcvr_rst_cntrl.pll_powerdown"
+   end="xcvr_tx_lane_pll.pll_powerdown">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_pll_reconfig.reconfig_from_pll"
+   end="xcvr_tx_pll.reconfig_from_pll">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_pll.reconfig_from_pll"
+   end="xcvr_rx_pll_reconfig.reconfig_from_pll">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_pll.reconfig_to_pll"
+   end="xcvr_tx_pll_reconfig.reconfig_to_pll">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_pll_reconfig.reconfig_to_pll"
+   end="xcvr_rx_pll.reconfig_to_pll">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -2128,8 +2246,19 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="xcvr_rst_cntrl.tx_digitalreset"
-   end="xcvr_core.tx_digitalreset">
+   start="xcvr_core.tx_digitalreset"
+   end="xcvr_rst_cntrl.tx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rst_cntrl.tx_ready"
+   end="axi_jesd_xcvr.if_tx_ready">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -2221,6 +2350,26 @@
    version="15.1"
    start="mem_rst.out_reset"
    end="axi_ad9144_dma.m_src_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_tx_pll_reconfig.mgmt_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_rx_pll_reconfig.mgmt_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_core.reconfig_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_tx_lane_pll.reconfig_reset0" />
  <connection
    kind="reset"
    version="15.1"
@@ -2231,6 +2380,11 @@
    version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_rx_pll.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_rst_cntrl.reset" />
  <connection
    kind="reset"
    version="15.1"

From 7a4a7edfba4c55ac61c75cb3b9069e6c20a48a1d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 20 Apr 2016 16:07:41 -0400
Subject: [PATCH 141/972] daq2/a10gx: 10AX115S3F45E2SGE3 version

---
 projects/daq2/a10gx/system_bd.qsys    | 118 ++++++++++++++++++++++++--
 projects/daq2/a10gx/system_constr.sdc |  27 +++++-
 projects/daq2/a10gx/system_top.v      |  14 +--
 3 files changed, 143 insertions(+), 16 deletions(-)

diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys
index 404b3413b..fac722018 100755
--- a/projects/daq2/a10gx/system_bd.qsys
+++ b/projects/daq2/a10gx/system_bd.qsys
@@ -50,7 +50,7 @@
    {
       datum baseAddress
       {
-         value = "212992";
+         value = "229376";
          type = "String";
       }
    }
@@ -66,7 +66,7 @@
    {
       datum baseAddress
       {
-         value = "196608";
+         value = "212992";
          type = "String";
       }
    }
@@ -78,6 +78,54 @@
          type = "String";
       }
    }
+   element daq2.xcvr_core_jesd204_rx_s_avl
+   {
+      datum baseAddress
+      {
+         value = "254976";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_core_jesd204_tx_s_avl
+   {
+      datum baseAddress
+      {
+         value = "253952";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_core_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "196608";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_rx_pll_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "251904";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_tx_lane_pll_s_avl
+   {
+      datum baseAddress
+      {
+         value = "245760";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_tx_pll_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "249856";
+         type = "String";
+      }
+   }
    element sys_clk
    {
       datum _sortIndex
@@ -313,7 +361,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S2F45I2SG" />
+ <parameter name="device" value="10AX115S3F45E2SGE3" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -418,14 +466,14 @@
    type="reset"
    dir="end" />
  <module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq2_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq2_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq2_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq2_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq2_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
   <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
   <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
@@ -445,7 +493,7 @@
   <parameter
      name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 29" />
-  <parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
@@ -502,7 +550,7 @@
    start="a10gx_base.sys_cpu_m_avl"
    end="daq2.axi_ad9144_dma_s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00034000" />
+  <parameter name="baseAddress" value="0x00038000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -520,7 +568,7 @@
    start="a10gx_base.sys_cpu_m_avl"
    end="daq2.axi_ad9680_dma_s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
+  <parameter name="baseAddress" value="0x00034000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -532,6 +580,60 @@
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_core_jesd204_rx_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003e400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_core_jesd204_tx_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003e000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_core_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00030000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_rx_pll_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003d800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_tx_lane_pll_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003c000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_tx_pll_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003d000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="clock"
    version="15.1"
diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc
index c55dd576c..7ec6b3f16 100644
--- a/projects/daq2/a10gx/system_constr.sdc
+++ b/projects/daq2/a10gx/system_constr.sdc
@@ -15,4 +15,29 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
   i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
  
 set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
\ No newline at end of file
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]
+
+set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v
index 3ded5b0ee..7e3d0bfb1 100644
--- a/projects/daq2/a10gx/system_top.v
+++ b/projects/daq2/a10gx/system_top.v
@@ -148,8 +148,8 @@ module system_top (
 
   // board gpio
 
-  inout   [ 10:0]   gpio_bd_i;
-  inout   [ 15:0]   gpio_bd_o;
+  input   [ 10:0]   gpio_bd_i;
+  output  [ 15:0]   gpio_bd_o;
 
   // lane interface
 
@@ -211,12 +211,12 @@ module system_top (
 
   // gpio in & out are separate cores
 
-  assign adc_pd = gpio_o[35];
-  assign dac_txen = gpio_o[34];
-  assign dac_reset = gpio_o[33];
-  assign clkd_sync = gpio_o[32];
+  assign adc_pd = gpio_o[42];
+  assign dac_txen = gpio_o[41];
+  assign dac_reset = gpio_o[40];
+  assign clkd_sync = gpio_o[38];
 
-  assign gpio_i[63:38] = 26'd0;
+  assign gpio_i[63:38] = gpio_o[63:38];
   assign gpio_i[37:37] = trig;
   assign gpio_i[36:36] = adc_fdb;
   assign gpio_i[35:35] = adc_fda;

From 82c4f75f13c9f6fd3bd4af25e4c8f361c9350ca1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 22 Apr 2016 10:39:21 -0400
Subject: [PATCH 142/972] a10soc- a10gx copy

---
 .../common/a10soc/a10soc_system_assign.tcl    |  240 ++
 projects/common/a10soc/a10soc_system_bd.qsys  | 2801 +++++++++++++++++
 2 files changed, 3041 insertions(+)
 create mode 100755 projects/common/a10soc/a10soc_system_assign.tcl
 create mode 100644 projects/common/a10soc/a10soc_system_bd.qsys

diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
new file mode 100755
index 000000000..145c90666
--- /dev/null
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -0,0 +1,240 @@
+
+# device settings
+
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115S3F45E2SGE3
+
+# clocks and resets
+
+set_location_assignment PIN_AR36  -to sys_clk
+set_location_assignment PIN_AR37  -to "sys_clk(n)"
+set_location_assignment PIN_BD27  -to sys_resetn
+set_instance_assignment -name IO_STANDARD LVDS -to sys_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn
+
+# ddr3
+
+set_location_assignment PIN_F34   -to ddr3_ref_clk
+set_location_assignment PIN_F35   -to "ddr3_ref_clk(n)"
+
+set_instance_assignment -name IO_STANDARD LVDS -to ddr3_ref_clk
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ddr3_ref_clk -disable
+
+set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[14]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[13]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[12]
+
+set_location_assignment PIN_R30   -to ddr3_clk_p      ; ## 1.5 V   V1  MEM_CLK_P          
+set_location_assignment PIN_R31   -to ddr3_clk_n      ; ## 1.5 V   V2  MEM_CLK_N          
+set_location_assignment PIN_M32   -to ddr3_a[0]       ; ## 1.5 V   F1  MEM_ADDR_CMD0      
+set_location_assignment PIN_L32   -to ddr3_a[1]       ; ## 1.5 V   H1  MEM_ADDR_CMD1      
+set_location_assignment PIN_N34   -to ddr3_a[2]       ; ## 1.5 V   F2  MEM_ADDR_CMD2      
+set_location_assignment PIN_M35   -to ddr3_a[3]       ; ## 1.5 V   G2  MEM_ADDR_CMD3      
+set_location_assignment PIN_L34   -to ddr3_a[4]       ; ## 1.5 V   H2  MEM_ADDR_CMD4      
+set_location_assignment PIN_K34   -to ddr3_a[5]       ; ## 1.5 V   J2  MEM_ADDR_CMD5      
+set_location_assignment PIN_M33   -to ddr3_a[6]       ; ## 1.5 V   K2  MEM_ADDR_CMD6      
+set_location_assignment PIN_L33   -to ddr3_a[7]       ; ## 1.5 V   G3  MEM_ADDR_CMD7      
+set_location_assignment PIN_J33   -to ddr3_a[8]       ; ## 1.5 V   J3  MEM_ADDR_CMD8      
+set_location_assignment PIN_J32   -to ddr3_a[9]       ; ## 1.5 V   L3  MEM_ADDR_CMD9      
+set_location_assignment PIN_H31   -to ddr3_a[10]      ; ## 1.5 V   E4  MEM_ADDR_CMD10     
+set_location_assignment PIN_J31   -to ddr3_a[11]      ; ## 1.5 V   F4  MEM_ADDR_CMD11     
+set_location_assignment PIN_H34   -to ddr3_a[12]      ; ## 1.5 V   G4  MEM_ADDR_CMD12     
+set_location_assignment PIN_H33   -to ddr3_a[13]      ; ## 1.5 V   H4  MEM_ADDR_CMD13     
+set_location_assignment PIN_G32   -to ddr3_a[14]      ; ## 1.5 V   J4  MEM_ADDR_CMD14     
+set_location_assignment PIN_F33   -to ddr3_ba[0]      ; ## 1.5 V   M1  MEM_ADDR_CMD16     
+set_location_assignment PIN_G35   -to ddr3_ba[1]      ; ## 1.5 V   M2  MEM_ADDR_CMD17     
+set_location_assignment PIN_H35   -to ddr3_ba[2]      ; ## 1.5 V   N2  MEM_ADDR_CMD18     
+set_location_assignment PIN_U33   -to ddr3_cke        ; ## 1.5 V   P5  MEM_ADDR_CMD20     
+set_location_assignment PIN_R34   -to ddr3_cs_n       ; ## 1.5 V   P1  MEM_ADDR_CMD22     
+set_location_assignment PIN_N33   -to ddr3_odt        ; ## 1.5 V   M4  MEM_ADDR_CMD24     
+set_location_assignment PIN_T35   -to ddr3_reset_n    ; ## 1.5 V   K1  MEM_ADDR_CMD27     
+set_location_assignment PIN_T34   -to ddr3_we_n       ; ## 1.5 V   P2  MEM_ADDR_CMD28     
+set_location_assignment PIN_F32   -to ddr3_ras_n      ; ## 1.5 V   L2  MEM_ADDR_CMD26     
+set_location_assignment PIN_G33   -to ddr3_cas_n      ; ## 1.5 V   L4  MEM_ADDR_CMD19     
+set_location_assignment PIN_B26   -to ddr3_dqs_p[0]   ; ## 1.5 V   A6  MEM_DQSA_P0        
+set_location_assignment PIN_C26   -to ddr3_dqs_n[0]   ; ## 1.5 V   A7  MEM_DQSA_N0        
+set_location_assignment PIN_H28   -to ddr3_dqs_p[1]   ; ## 1.5 V   A2  MEM_DQSA_P1        
+set_location_assignment PIN_J27   -to ddr3_dqs_n[1]   ; ## 1.5 V   A3  MEM_DQSA_N1        
+set_location_assignment PIN_C30   -to ddr3_dqs_p[2]   ; ## 1.5 V   A14 MEM_DQSA_P2        
+set_location_assignment PIN_C29   -to ddr3_dqs_n[2]   ; ## 1.5 V   A15 MEM_DQSA_N2        
+set_location_assignment PIN_L30   -to ddr3_dqs_p[3]   ; ## 1.5 V   F18 MEM_DQSA_P3        
+set_location_assignment PIN_L29   -to ddr3_dqs_n[3]   ; ## 1.5 V   G18 MEM_DQSA_N3        
+set_location_assignment PIN_Y32   -to ddr3_dqs_p[4]   ; ## 1.5 V   H18 MEM_DQSB_P0        
+set_location_assignment PIN_AA32  -to ddr3_dqs_n[4]   ; ## 1.5 V   J18 MEM_DQSB_N0        
+set_location_assignment PIN_AJ32  -to ddr3_dqs_p[5]   ; ## 1.5 V   U18 MEM_DQSB_P1        
+set_location_assignment PIN_AJ31  -to ddr3_dqs_n[5]   ; ## 1.5 V   V18 MEM_DQSB_N1        
+set_location_assignment PIN_AA34  -to ddr3_dqs_p[6]   ; ## 1.5 V   V16 MEM_DQSB_P2        
+set_location_assignment PIN_AA33  -to ddr3_dqs_n[6]   ; ## 1.5 V   V17 MEM_DQSB_N2        
+set_location_assignment PIN_AF33  -to ddr3_dqs_p[7]   ; ## 1.5 V   V8  MEM_DQSB_P3        
+set_location_assignment PIN_AF34  -to ddr3_dqs_n[7]   ; ## 1.5 V   V9  MEM_DQSB_N3        
+set_location_assignment PIN_B28   -to ddr3_dq[0]      ; ## 1.5 V   A4  MEM_DQA0           
+set_location_assignment PIN_A28   -to ddr3_dq[1]      ; ## 1.5 V   B4  MEM_DQA1           
+set_location_assignment PIN_A27   -to ddr3_dq[2]      ; ## 1.5 V   B5  MEM_DQA2           
+set_location_assignment PIN_B27   -to ddr3_dq[3]      ; ## 1.5 V   B6  MEM_DQA3           
+set_location_assignment PIN_D27   -to ddr3_dq[4]      ; ## 1.5 V   A8  MEM_DQA4           
+set_location_assignment PIN_E27   -to ddr3_dq[5]      ; ## 1.5 V   B8  MEM_DQA5           
+set_location_assignment PIN_D26   -to ddr3_dq[6]      ; ## 1.5 V   B9  MEM_DQA6           
+set_location_assignment PIN_D28   -to ddr3_dq[7]      ; ## 1.5 V   A10 MEM_DQA7           
+set_location_assignment PIN_G25   -to ddr3_dq[8]      ; ## 1.5 V   B1  MEM_DQA8           
+set_location_assignment PIN_H25   -to ddr3_dq[9]      ; ## 1.5 V   B2  MEM_DQA9           
+set_location_assignment PIN_G26   -to ddr3_dq[10]     ; ## 1.5 V   C2  MEM_DQA10          
+set_location_assignment PIN_H26   -to ddr3_dq[11]     ; ## 1.5 V   C3  MEM_DQA11          
+set_location_assignment PIN_G28   -to ddr3_dq[12]     ; ## 1.5 V   E3  MEM_DQA12          
+set_location_assignment PIN_F27   -to ddr3_dq[13]     ; ## 1.5 V   D4  MEM_DQA13          
+set_location_assignment PIN_K27   -to ddr3_dq[14]     ; ## 1.5 V   D1  MEM_DQA14          
+set_location_assignment PIN_F28   -to ddr3_dq[15]     ; ## 1.5 V   D2  MEM_DQA15          
+set_location_assignment PIN_D31   -to ddr3_dq[16]     ; ## 1.5 V   A12 MEM_DQA16          
+set_location_assignment PIN_E31   -to ddr3_dq[17]     ; ## 1.5 V   B12 MEM_DQA17          
+set_location_assignment PIN_B31   -to ddr3_dq[18]     ; ## 1.5 V   B13 MEM_DQA18          
+set_location_assignment PIN_C31   -to ddr3_dq[19]     ; ## 1.5 V   B14 MEM_DQA19          
+set_location_assignment PIN_A30   -to ddr3_dq[20]     ; ## 1.5 V   C15 MEM_DQA20          
+set_location_assignment PIN_E30   -to ddr3_dq[21]     ; ## 1.5 V   A16 MEM_DQA21          
+set_location_assignment PIN_B30   -to ddr3_dq[22]     ; ## 1.5 V   B16 MEM_DQA22          
+set_location_assignment PIN_D29   -to ddr3_dq[23]     ; ## 1.5 V   A18 MEM_DQA23          
+set_location_assignment PIN_K30   -to ddr3_dq[24]     ; ## 1.5 V   C16 MEM_DQA24          
+set_location_assignment PIN_H30   -to ddr3_dq[25]     ; ## 1.5 V   D16 MEM_DQA25          
+set_location_assignment PIN_G30   -to ddr3_dq[26]     ; ## 1.5 V   E16 MEM_DQA26          
+set_location_assignment PIN_K31   -to ddr3_dq[27]     ; ## 1.5 V   F16 MEM_DQA27          
+set_location_assignment PIN_H29   -to ddr3_dq[28]     ; ## 1.5 V   D17 MEM_DQA28          
+set_location_assignment PIN_K29   -to ddr3_dq[29]     ; ## 1.5 V   C18 MEM_DQA29          
+set_location_assignment PIN_J29   -to ddr3_dq[30]     ; ## 1.5 V   D18 MEM_DQA30          
+set_location_assignment PIN_F29   -to ddr3_dq[31]     ; ## 1.5 V   E18 MEM_DQA31          
+set_location_assignment PIN_AC31  -to ddr3_dq[32]     ; ## 1.5 V   H16 MEM_DQB0           
+set_location_assignment PIN_AB31  -to ddr3_dq[33]     ; ## 1.5 V   J16 MEM_DQB1           
+set_location_assignment PIN_W31   -to ddr3_dq[34]     ; ## 1.5 V   K16 MEM_DQB2           
+set_location_assignment PIN_Y31   -to ddr3_dq[35]     ; ## 1.5 V   L16 MEM_DQB3           
+set_location_assignment PIN_AD31  -to ddr3_dq[36]     ; ## 1.5 V   H17 MEM_DQB4           
+set_location_assignment PIN_AD32  -to ddr3_dq[37]     ; ## 1.5 V   K17 MEM_DQB5           
+set_location_assignment PIN_AD33  -to ddr3_dq[38]     ; ## 1.5 V   K18 MEM_DQB6           
+set_location_assignment PIN_AA30  -to ddr3_dq[39]     ; ## 1.5 V   L18 MEM_DQB7           
+set_location_assignment PIN_AE31  -to ddr3_dq[40]     ; ## 1.5 V   M17 MEM_DQB8           
+set_location_assignment PIN_AE32  -to ddr3_dq[41]     ; ## 1.5 V   N18 MEM_DQB9           
+set_location_assignment PIN_AE30  -to ddr3_dq[42]     ; ## 1.5 V   P17 MEM_DQB10          
+set_location_assignment PIN_AF30  -to ddr3_dq[43]     ; ## 1.5 V   P18 MEM_DQB11          
+set_location_assignment PIN_AG33  -to ddr3_dq[44]     ; ## 1.5 V   R18 MEM_DQB12          
+set_location_assignment PIN_AG32  -to ddr3_dq[45]     ; ## 1.5 V   T16 MEM_DQB13          
+set_location_assignment PIN_AH33  -to ddr3_dq[46]     ; ## 1.5 V   T17 MEM_DQB14          
+set_location_assignment PIN_AH31  -to ddr3_dq[47]     ; ## 1.5 V   T18 MEM_DQB15          
+set_location_assignment PIN_U31   -to ddr3_dq[48]     ; ## 1.5 V   U15 MEM_DQB16          
+set_location_assignment PIN_W33   -to ddr3_dq[49]     ; ## 1.5 V   T14 MEM_DQB17          
+set_location_assignment PIN_W32   -to ddr3_dq[50]     ; ## 1.5 V   U14 MEM_DQB18          
+set_location_assignment PIN_V31   -to ddr3_dq[51]     ; ## 1.5 V   V14 MEM_DQB19          
+set_location_assignment PIN_Y34   -to ddr3_dq[52]     ; ## 1.5 V   T13 MEM_DQB20          
+set_location_assignment PIN_W35   -to ddr3_dq[53]     ; ## 1.5 V   T12 MEM_DQB21          
+set_location_assignment PIN_W34   -to ddr3_dq[54]     ; ## 1.5 V   U12 MEM_DQB22          
+set_location_assignment PIN_V34   -to ddr3_dq[55]     ; ## 1.5 V   V12 MEM_DQB23          
+set_location_assignment PIN_AH35  -to ddr3_dq[56]     ; ## 1.5 V   T10 MEM_DQB24          
+set_location_assignment PIN_AJ34  -to ddr3_dq[57]     ; ## 1.5 V   U10 MEM_DQB25          
+set_location_assignment PIN_AJ33  -to ddr3_dq[58]     ; ## 1.5 V   V10 MEM_DQB26          
+set_location_assignment PIN_AH34  -to ddr3_dq[59]     ; ## 1.5 V   T9  MEM_DQB27          
+set_location_assignment PIN_AD35  -to ddr3_dq[60]     ; ## 1.5 V   T8  MEM_DQB28          
+set_location_assignment PIN_AE34  -to ddr3_dq[61]     ; ## 1.5 V   U8  MEM_DQB29          
+set_location_assignment PIN_AC33  -to ddr3_dq[62]     ; ## 1.5 V   U7  MEM_DQB30          
+set_location_assignment PIN_AD34  -to ddr3_dq[63]     ; ## 1.5 V   V6  MEM_DQB31          
+set_location_assignment PIN_E26   -to ddr3_dm[0]      ; ## 1.5 V   B10 MEM_DMA0           
+set_location_assignment PIN_G27   -to ddr3_dm[1]      ; ## 1.5 V   C4  MEM_DMA1           
+set_location_assignment PIN_A29   -to ddr3_dm[2]      ; ## 1.5 V   B17 MEM_DMA2           
+set_location_assignment PIN_F30   -to ddr3_dm[3]      ; ## 1.5 V   F17 MEM_DMA3           
+set_location_assignment PIN_AB32  -to ddr3_dm[4]      ; ## 1.5 V   M16 MEM_DMB0           
+set_location_assignment PIN_AG31  -to ddr3_dm[5]      ; ## 1.5 V   U16 MEM_DMB1           
+set_location_assignment PIN_Y35   -to ddr3_dm[6]      ; ## 1.5 V   U11 MEM_DMB2           
+set_location_assignment PIN_AC34  -to ddr3_dm[7]      ; ## 1.5 V   U6  MEM_DMB3           
+set_location_assignment PIN_J34   -to ddr3_rzq        ; ## RZQ
+
+# ethernet interface
+
+set_location_assignment PIN_BD24 -to eth_ref_clk
+set_location_assignment PIN_BC24 -to "eth_ref_clk(n)"
+set_location_assignment PIN_AV24 -to eth_rxd
+set_location_assignment PIN_AW24 -to "eth_rxd(n)"
+set_location_assignment PIN_BC23 -to eth_txd
+set_location_assignment PIN_BD23 -to "eth_txd(n)"
+
+set_instance_assignment -name IO_STANDARD LVDS -to eth_ref_clk
+set_instance_assignment -name IO_STANDARD LVDS -to eth_rxd
+set_instance_assignment -name IO_STANDARD LVDS -to eth_txd
+
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_ref_clk -disable
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rxd -disable
+
+set_location_assignment PIN_AW23 -to eth_resetn
+set_location_assignment PIN_AF13 -to eth_mdc
+set_location_assignment PIN_AL18 -to eth_mdio
+set_location_assignment PIN_AG13 -to eth_intn
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_resetn
+set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_mdc
+set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_mdio
+set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_intn
+
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_ref_clk
+
+# leds
+
+set_location_assignment PIN_L28   -to gpio_bd_o[0]  ; ## led-g0-d10
+set_location_assignment PIN_K26   -to gpio_bd_o[1]  ; ## led-g1-d9
+set_location_assignment PIN_K25   -to gpio_bd_o[2]  ; ## led-g2-d8
+set_location_assignment PIN_L25   -to gpio_bd_o[3]  ; ## led-g3-d7
+set_location_assignment PIN_J24   -to gpio_bd_o[4]  ; ## led-g4-d6
+set_location_assignment PIN_A19   -to gpio_bd_o[5]  ; ## led-g5-d5
+set_location_assignment PIN_C18   -to gpio_bd_o[6]  ; ## led-g6-d4
+set_location_assignment PIN_D18   -to gpio_bd_o[7]  ; ## led-g7-d3
+set_location_assignment PIN_L27   -to gpio_bd_o[8]  ; ## led-r0-d10  
+set_location_assignment PIN_J26   -to gpio_bd_o[9]  ; ## led-r1-d9   
+set_location_assignment PIN_K24   -to gpio_bd_o[10] ; ## led-r2-d8
+set_location_assignment PIN_L23   -to gpio_bd_o[11] ; ## led-r3-d7
+set_location_assignment PIN_B20   -to gpio_bd_o[12] ; ## led-r4-d6
+set_location_assignment PIN_C19   -to gpio_bd_o[13] ; ## led-r5-d5
+set_location_assignment PIN_D19   -to gpio_bd_o[14] ; ## led-r6-d4
+set_location_assignment PIN_M23   -to gpio_bd_o[15] ; ## led-r7-d3
+set_location_assignment PIN_A24   -to gpio_bd_i[0]  ; ## dipsw0
+set_location_assignment PIN_B23   -to gpio_bd_i[1]  ; ## dipsw1
+set_location_assignment PIN_A23   -to gpio_bd_i[2]  ; ## dipsw2
+set_location_assignment PIN_B22   -to gpio_bd_i[3]  ; ## dipsw3
+set_location_assignment PIN_A22   -to gpio_bd_i[4]  ; ## dipsw4
+set_location_assignment PIN_B21   -to gpio_bd_i[5]  ; ## dipsw5
+set_location_assignment PIN_C21   -to gpio_bd_i[6]  ; ## dipsw6
+set_location_assignment PIN_A20   -to gpio_bd_i[7]  ; ## dipsw7
+set_location_assignment PIN_T12   -to gpio_bd_i[8]  ; ## pb0-s3
+set_location_assignment PIN_U12   -to gpio_bd_i[9]  ; ## pb1-s2
+set_location_assignment PIN_U11   -to gpio_bd_i[10] ; ## pb2-s1
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[4] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[5] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[6] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[7] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[8] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[9] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[11]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[12]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[13]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[14]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[15]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10]
+
+# globals
+
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+
+
diff --git a/projects/common/a10soc/a10soc_system_bd.qsys b/projects/common/a10soc/a10soc_system_bd.qsys
new file mode 100644
index 000000000..7bdd08068
--- /dev/null
+++ b/projects/common/a10soc/a10soc_system_bd.qsys
@@ -0,0 +1,2801 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element a10gx_system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element mem_clk
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element mem_rst
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_cpu
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_cpu.debug_mem_slave
+   {
+      datum baseAddress
+      {
+         value = "270010368";
+         type = "String";
+      }
+   }
+   element sys_cpu_interconnect
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element sys_cpu_interconnect.s0
+   {
+      datum baseAddress
+      {
+         value = "268435456";
+         type = "String";
+      }
+   }
+   element sys_ddr3_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element sys_ethernet
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_ethernet.control_port
+   {
+      datum baseAddress
+      {
+         value = "270012416";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_rx
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element sys_ethernet_dma_rx.csr
+   {
+      datum baseAddress
+      {
+         value = "270013600";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_rx.descriptor_slave
+   {
+      datum baseAddress
+      {
+         value = "270013504";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_rx.response
+   {
+      datum baseAddress
+      {
+         value = "270013664";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_tx
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element sys_ethernet_dma_tx.csr
+   {
+      datum baseAddress
+      {
+         value = "270013568";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_tx.descriptor_slave
+   {
+      datum baseAddress
+      {
+         value = "270013536";
+         type = "String";
+      }
+   }
+   element sys_ethernet_reset
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element sys_gpio_bd
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_gpio_bd.s1
+   {
+      datum baseAddress
+      {
+         value = "270013648";
+         type = "String";
+      }
+   }
+   element sys_gpio_in
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element sys_gpio_in.s1
+   {
+      datum baseAddress
+      {
+         value = "270013632";
+         type = "String";
+      }
+   }
+   element sys_gpio_out
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element sys_gpio_out.s1
+   {
+      datum baseAddress
+      {
+         value = "270013696";
+         type = "String";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_id.control_slave
+   {
+      datum baseAddress
+      {
+         value = "270013672";
+         type = "String";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_int_mem.s1
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "269746176";
+         type = "String";
+      }
+   }
+   element sys_irq
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element sys_mem_interconnect
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element sys_rst
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element sys_spi
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_spi.spi_control_port
+   {
+      datum baseAddress
+      {
+         value = "270013440";
+         type = "String";
+      }
+   }
+   element sys_timer
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "270013472";
+         type = "String";
+      }
+   }
+   element sys_timer_2nd
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element sys_timer_2nd.s1
+   {
+      datum baseAddress
+      {
+         value = "270013728";
+         type = "String";
+      }
+   }
+   element sys_tlb_mem
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element sys_tlb_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "270532608";
+         type = "String";
+      }
+   }
+   element sys_tlb_mem.s2
+   {
+      datum baseAddress
+      {
+         value = "270532608";
+         type = "String";
+      }
+   }
+   element sys_uart
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_uart.avalon_jtag_slave
+   {
+      datum baseAddress
+      {
+         value = "270013680";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="10AX115S3F45E2SGE3" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
+ <interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
+ <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
+ <interface
+   name="sys_cpu_m_avl"
+   internal="sys_cpu_interconnect.m0"
+   type="avalon"
+   dir="start" />
+ <interface
+   name="sys_ddr3_cntrl_mem"
+   internal="sys_ddr3_cntrl.mem"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_mem_conduit_end"
+   internal="sys_ddr3_cntrl.mem_conduit_end" />
+ <interface
+   name="sys_ddr3_cntrl_oct"
+   internal="sys_ddr3_cntrl.oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_oct_conduit_end"
+   internal="sys_ddr3_cntrl.oct_conduit_end" />
+ <interface
+   name="sys_ddr3_cntrl_pll_ref_clk"
+   internal="sys_ddr3_cntrl.pll_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_ref_clk"
+   internal="sys_ddr3_cntrl.pll_ref_clk_clock_sink" />
+ <interface
+   name="sys_ddr3_cntrl_status_conduit_end"
+   internal="sys_ddr3_cntrl.status_conduit_end" />
+ <interface
+   name="sys_ethernet_mdio"
+   internal="sys_ethernet.mac_mdio_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_ref_clk"
+   internal="sys_ethernet.pcs_ref_clk_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_ethernet_reset"
+   internal="sys_ethernet_reset.out_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="sys_ethernet_rgmii"
+   internal="sys_ethernet.mac_rgmii_connection" />
+ <interface
+   name="sys_ethernet_rx_clk"
+   internal="sys_ethernet.pcs_mac_rx_clock_connection" />
+ <interface
+   name="sys_ethernet_sgmii"
+   internal="sys_ethernet.serial_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_status"
+   internal="sys_ethernet.mac_status_connection" />
+ <interface
+   name="sys_ethernet_tx_clk"
+   internal="sys_ethernet.pcs_mac_tx_clock_connection" />
+ <interface
+   name="sys_gpio_bd"
+   internal="sys_gpio_bd.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_in"
+   internal="sys_gpio_in.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_out"
+   internal="sys_gpio_out.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_intr"
+   internal="sys_irq.receiver_irq"
+   type="interrupt"
+   dir="start" />
+ <interface
+   name="sys_mem_s_avl"
+   internal="sys_mem_interconnect.s0"
+   type="avalon"
+   dir="end" />
+ <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
+ <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="133333250" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_cpu_interconnect.s0' start='0x10000000' end='0x10100000' type='altera_avalon_mm_bridge.s0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2nd.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="1" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="32768" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="Arria 10" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="exceptionSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="1" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="32768" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="65535" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="4096" />
+  <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="3" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="0" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+   name="sys_cpu_interconnect"
+   kind="altera_avalon_mm_bridge"
+   version="15.1"
+   enabled="1">
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="ADDRESS_WIDTH" value="20" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="LINEWRAPBURSTS" value="0" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="MAX_PENDING_RESPONSES" value="4" />
+  <parameter name="PIPELINE_COMMAND" value="1" />
+  <parameter name="PIPELINE_RESPONSE" value="1" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="USE_RESPONSE" value="0" />
+ </module>
+ <module name="sys_ddr3_cntrl" kind="altera_emif" version="15.1" enabled="1">
+  <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+  <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+  <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
+  <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+  <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+  <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+  <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+  <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="3.5" />
+  <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+  <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+  <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
+  <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+  <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+  <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+  <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+  <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+  <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+  <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
+  <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+  <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+  <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+  <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+  <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+  <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+  <parameter name="CTRL_DDR4_MMR_EN" value="false" />
+  <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+  <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
+  <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+  <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+  <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+  <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+  <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+  <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+  <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+  <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
+  <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+  <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+  <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+  <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+  <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+  <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+  <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+  <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+  <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+  <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+  <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+  <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+  <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
+  <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+  <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+  <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="false" />
+  <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+  <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
+  <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+  <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
+  <parameter name="DIAG_EXPORT_VJI" value="false" />
+  <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+  <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+  <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+  <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+  <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+  <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+  <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
+  <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
+  <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+  <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+  <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
+  <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+  <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
+  <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+  <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="DIAG_USE_RS232_UART" value="false" />
+  <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter
+     name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+     value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="INTERNAL_TESTING_MODE" value="false" />
+  <parameter name="IS_ED_SLAVE" value="false" />
+  <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+  <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+  <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+  <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+  <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+  <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+  <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+  <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
+  <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
+  <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+  <parameter name="MEM_DDR3_DLL_EN" value="true" />
+  <parameter name="MEM_DDR3_DM_EN" value="true" />
+  <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DDR3_DQ_WIDTH" value="64" />
+  <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
+  <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+  <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="0x0" />
+  <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
+  <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
+  <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
+  <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0" />
+  <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="12" />
+  <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
+  <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
+  <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
+  <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
+  <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+  <parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
+  <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
+  <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
+  <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+  <parameter name="MEM_DDR3_TCL" value="13" />
+  <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
+  <parameter name="MEM_DDR3_TDH_PS" value="55" />
+  <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+  <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
+  <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
+  <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
+  <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+  <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+  <parameter name="MEM_DDR3_TDS_PS" value="53" />
+  <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+  <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+  <parameter name="MEM_DDR3_TIH_PS" value="95" />
+  <parameter name="MEM_DDR3_TINIT_US" value="500" />
+  <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+  <parameter name="MEM_DDR3_TIS_PS" value="60" />
+  <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+  <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+  <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
+  <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
+  <parameter name="MEM_DDR3_TRCD_NS" value="10.285" />
+  <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
+  <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
+  <parameter name="MEM_DDR3_TRP_NS" value="10.285" />
+  <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
+  <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
+  <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+  <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+  <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+  <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
+  <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+  <parameter name="MEM_DDR3_WTCL" value="9" />
+  <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+  <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
+  <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
+  <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+  <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+  <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+  <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+  <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+  <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_AUTO</parameter>
+  <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+  <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+  <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
+  <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
+  <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+  <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+  <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+  <parameter name="MEM_DDR4_CAL_MODE" value="0" />
+  <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+  <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+  <parameter name="MEM_DDR4_CK_WIDTH" value="1" />
+  <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="true" />
+  <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+  <parameter name="MEM_DDR4_DLL_EN" value="true" />
+  <parameter name="MEM_DDR4_DM_EN" value="true" />
+  <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+  <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
+  <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
+  <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+  <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
+  <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
+  <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG" value="0000000000000000" />
+  <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
+  <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+  <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
+  <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+  <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+  <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+  <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+  <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_DDR4_RDIMM_CONFIG">0000000000000000000000000000000F000000</parameter>
+  <parameter name="MEM_DDR4_READ_DBI" value="false" />
+  <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
+  <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+  <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
+  <parameter name="MEM_DDR4_RTT_NOM_ENUM">DDR4_RTT_NOM_ODT_DISABLED</parameter>
+  <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
+  <parameter name="MEM_DDR4_RTT_WR_ENUM" value="DDR4_RTT_WR_RZQ_1" />
+  <parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
+  <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,off" />
+  <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+  <parameter name="MEM_DDR4_R_ODT1_2X2" value="off,off" />
+  <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
+  <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
+  <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
+  <parameter name="MEM_DDR4_TCCD_L_CYC" value="6" />
+  <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+  <parameter name="MEM_DDR4_TCL" value="18" />
+  <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+  <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
+  <parameter name="MEM_DDR4_TDQSCK_PS" value="165" />
+  <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+  <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
+  <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
+  <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
+  <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
+  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+  <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+  <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
+  <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+  <parameter name="MEM_DDR4_TIH_PS" value="95" />
+  <parameter name="MEM_DDR4_TINIT_US" value="500" />
+  <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+  <parameter name="MEM_DDR4_TIS_PS" value="60" />
+  <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+  <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+  <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
+  <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
+  <parameter name="MEM_DDR4_TRAS_NS" value="32.0" />
+  <parameter name="MEM_DDR4_TRCD_NS" value="15.0" />
+  <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
+  <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
+  <parameter name="MEM_DDR4_TRP_NS" value="15.0" />
+  <parameter name="MEM_DDR4_TRRD_L_CYC" value="6" />
+  <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+  <parameter name="MEM_DDR4_TWLH_PS" value="108.0" />
+  <parameter name="MEM_DDR4_TWLS_PS" value="108.0" />
+  <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
+  <parameter name="MEM_DDR4_TWTR_L_CYC" value="9" />
+  <parameter name="MEM_DDR4_TWTR_S_CYC" value="3" />
+  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="60.0" />
+  <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
+  <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+  <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+  <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+  <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+  <parameter name="MEM_DDR4_WTCL" value="12" />
+  <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+  <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
+  <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
+  <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+  <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+  <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+  <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+  <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+  <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+  <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+  <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+  <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
+  <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+  <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+  <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+  <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+  <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+  <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+  <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+  <parameter name="MEM_LPDDR3_TDQSCK_PS" value="614" />
+  <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+  <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+  <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+  <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+  <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+  <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+  <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+  <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+  <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+  <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+  <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+  <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+  <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+  <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+  <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+  <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+  <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+  <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+  <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+  <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+  <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+  <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+  <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+  <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+  <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+  <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+  <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+  <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+  <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+  <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+  <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
+  <parameter name="MEM_QDR2_BL" value="4" />
+  <parameter name="MEM_QDR2_BWS_EN" value="true" />
+  <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+  <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
+  <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+  <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+  <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+  <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+  <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+  <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+  <parameter name="MEM_QDR2_THD_NS" value="0.18" />
+  <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
+  <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
+  <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
+  <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+  <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+  <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+  <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+  <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+  <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+  <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+  <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+  <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+  <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+  <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+  <parameter name="MEM_QDR4_TAH_PS" value="125" />
+  <parameter name="MEM_QDR4_TAS_PS" value="125" />
+  <parameter name="MEM_QDR4_TCH_PS" value="150" />
+  <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+  <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+  <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+  <parameter name="MEM_QDR4_TCS_PS" value="150" />
+  <parameter name="MEM_QDR4_TIH_PS" value="125" />
+  <parameter name="MEM_QDR4_TIS_PS" value="125" />
+  <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+  <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+  <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
+  <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
+  <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
+  <parameter name="MEM_RLD2_BL" value="4" />
+  <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+  <parameter name="MEM_RLD2_DM_EN" value="true" />
+  <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+  <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
+  <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
+  <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
+  <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
+  <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
+  <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+  <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
+  <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+  <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
+  <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
+  <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+  <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+  <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+  <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+  <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+  <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
+  <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+  <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
+  <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
+  <parameter name="MEM_RLD3_BL" value="2" />
+  <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
+  <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+  <parameter name="MEM_RLD3_DM_EN" value="true" />
+  <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+  <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
+  <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+  <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
+  <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
+  <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
+  <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+  <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
+  <parameter name="MEM_RLD3_TDH_PS" value="5" />
+  <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
+  <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+  <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
+  <parameter name="MEM_RLD3_TIH_PS" value="65" />
+  <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
+  <parameter name="MEM_RLD3_TIS_PS" value="85" />
+  <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+  <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+  <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+  <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+  <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+  <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+  <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+  <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+  <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+  <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_DDR3_DEFAULT_IO" value="false" />
+  <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
+  <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="533.333" />
+  <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_15_C1" />
+  <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="CURRENT_ST_12" />
+  <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_15_C1" />
+  <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="CURRENT_ST_12" />
+  <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="IN_OCT_40_CAL" />
+  <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="IO_STD_SSTL_15" />
+  <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
+  <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_LVDS" />
+  <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
+  <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_15" />
+  <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+  <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
+  <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
+  <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
+  <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+  <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+  <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+  <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+  <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+  <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+  <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+  <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+  <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+  <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+  <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+  <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
+  <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+  <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+  <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+  <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+  <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+  <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+  <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+  <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+  <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+  <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
+  <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR3" />
+  <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
+  <parameter name="SYS_INFO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
+  <parameter name="TRAIT_SUPPORTS_VID" value="0" />
+ </module>
+ <module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="core_variation" value="MAC_PCS" />
+  <parameter name="deviceFamilyName" value="Arria 10" />
+  <parameter name="eg_addr" value="12" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="enable_gmii_loopback" value="false" />
+  <parameter name="enable_hd_logic" value="false" />
+  <parameter name="enable_mac_flow_ctrl" value="false" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="enable_sgmii" value="true" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="ifGMII" value="MII_GMII" />
+  <parameter name="ing_addr" value="12" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="mdio_clk_div" value="40" />
+  <parameter name="nf_phyip_rcfg_enable" value="false" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="transceiver_type" value="LVDS_IO" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module
+   name="sys_ethernet_dma_rx"
+   kind="altera_msgdma"
+   version="15.1"
+   enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="BURST_ENABLE" value="1" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="256" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
+  <parameter name="ENHANCED_FEATURES" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="64" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="2" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="0" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="sys_ethernet_dma_tx"
+   kind="altera_msgdma"
+   version="15.1"
+   enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="BURST_ENABLE" value="1" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="256" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
+  <parameter name="ENHANCED_FEATURES" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="64" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="sys_ethernet_reset"
+   kind="altera_reset_bridge"
+   version="15.1"
+   enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module
+   name="sys_gpio_bd"
+   kind="altera_avalon_pio"
+   version="15.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_in"
+   kind="altera_avalon_pio"
+   version="15.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_out"
+   kind="altera_avalon_pio"
+   version="15.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_id"
+   kind="altera_avalon_sysid_qsys"
+   version="15.1"
+   enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="id" value="182193580" />
+ </module>
+ <module
+   name="sys_int_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="15.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="deviceFamily" value="Arria 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="163840" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="sys_irq" kind="altera_irq_bridge" version="15.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
+  <parameter name="IRQ_N" value="0" />
+  <parameter name="IRQ_WIDTH" value="8" />
+ </module>
+ <module
+   name="sys_mem_interconnect"
+   kind="altera_avalon_mm_bridge"
+   version="15.1"
+   enabled="1">
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="ADDRESS_WIDTH" value="29" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DATA_WIDTH" value="512" />
+  <parameter name="LINEWRAPBURSTS" value="0" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="MAX_PENDING_RESPONSES" value="4" />
+  <parameter name="PIPELINE_COMMAND" value="1" />
+  <parameter name="PIPELINE_RESPONSE" value="1" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="28" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="USE_RESPONSE" value="0" />
+ </module>
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="sys_spi" kind="altera_avalon_spi" version="15.1" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="0" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="100000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="8" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="128000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
+ <module
+   name="sys_timer"
+   kind="altera_avalon_timer"
+   version="15.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_timer_2nd"
+   kind="altera_avalon_timer"
+   version="15.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_tlb_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="15.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tlb_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="deviceFamily" value="Arria 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="dualPort" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="163840" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module
+   name="sys_uart"
+   kind="altera_avalon_jtag_uart"
+   version="15.1"
+   enabled="1">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clkFreq" value="100000000" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814f0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet.control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814e8" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181480" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10180800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.descriptor_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181460" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.descriptor_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181440" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.response">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_cpu_interconnect.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181420" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_gpio_bd.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_gpio_in.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_gpio_out.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181500" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_timer_2nd.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181520" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_spi.spi_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.instruction_master"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.instruction_master"
+   end="sys_cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10180800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.instruction_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_mem_interconnect.m0"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_ethernet_dma_tx.mm_read"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_ethernet_dma_rx.mm_write"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.tightly_coupled_data_master_0"
+   end="sys_tlb_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.tightly_coupled_instruction_master_0"
+   end="sys_tlb_mem.s2">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="15.1"
+   start="sys_ethernet.receive"
+   end="sys_ethernet_dma_rx.st_sink" />
+ <connection
+   kind="avalon_streaming"
+   version="15.1"
+   start="sys_ethernet_dma_tx.st_source"
+   end="sys_ethernet.transmit" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_clk"
+   end="sys_mem_interconnect.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_clk"
+   end="mem_rst.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_clk"
+   end="mem_clk.in_clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_cpu.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_uart.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_timer.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_id.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_gpio_bd.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_spi.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_cpu_interconnect.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_irq.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet_reset.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_gpio_in.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_gpio_out.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_timer_2nd.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_tlb_mem.clk1" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_tlb_mem.clk2" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet_dma_rx.clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet_dma_tx.clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet.control_port_clock_connection" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet.receive_clock_connection" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet.transmit_clock_connection" />
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_ethernet_dma_rx.csr_irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_ethernet_dma_tx.csr_irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_uart.irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_timer.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="15.1" start="sys_cpu.irq" end="sys_spi.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_gpio_bd.irq">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_gpio_in.irq">
+  <parameter name="irqNumber" value="8" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_timer_2nd.irq">
+  <parameter name="irqNumber" value="15" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender0_irq">
+  <parameter name="irqNumber" value="6" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender1_irq">
+  <parameter name="irqNumber" value="7" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender2_irq">
+  <parameter name="irqNumber" value="9" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender3_irq">
+  <parameter name="irqNumber" value="10" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender4_irq">
+  <parameter name="irqNumber" value="11" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender5_irq">
+  <parameter name="irqNumber" value="12" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender6_irq">
+  <parameter name="irqNumber" value="13" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender7_irq">
+  <parameter name="irqNumber" value="14" />
+ </connection>
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_cpu.debug_reset_request"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_reset_n"
+   end="mem_rst.in_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_reset_n"
+   end="sys_mem_interconnect.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_irq.clk_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ddr3_cntrl.global_reset_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ethernet_reset.in_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_uart.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_timer.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_id.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_gpio_bd.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_spi.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_cpu_interconnect.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_gpio_in.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_gpio_out.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_timer_2nd.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_int_mem.reset1" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_tlb_mem.reset1" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_tlb_mem.reset2" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ethernet.reset_connection" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ethernet_dma_rx.reset_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ethernet_dma_tx.reset_n" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+</system>

From 2a5f31d26b59e2e46ad35bb4ccdba1b1be5b3b8f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 22 Apr 2016 15:15:44 -0400
Subject: [PATCH 143/972] fmcomms2/a10soc- copy

---
 projects/fmcomms2/a10soc/Makefile           | 139 ++++
 projects/fmcomms2/a10soc/system_bd.qsys     | 680 ++++++++++++++++++++
 projects/fmcomms2/a10soc/system_constr.sdc  |  43 ++
 projects/fmcomms2/a10soc/system_project.tcl |  92 +++
 projects/fmcomms2/a10soc/system_top.v       | 288 +++++++++
 5 files changed, 1242 insertions(+)
 create mode 100644 projects/fmcomms2/a10soc/Makefile
 create mode 100755 projects/fmcomms2/a10soc/system_bd.qsys
 create mode 100644 projects/fmcomms2/a10soc/system_constr.sdc
 create mode 100644 projects/fmcomms2/a10soc/system_project.tcl
 create mode 100644 projects/fmcomms2/a10soc/system_top.v

diff --git a/projects/fmcomms2/a10soc/Makefile b/projects/fmcomms2/a10soc/Makefile
new file mode 100644
index 000000000..51c24bfef
--- /dev/null
+++ b/projects/fmcomms2/a10soc/Makefile
@@ -0,0 +1,139 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.sdc
+M_DEPS += system_bd.qsys
+M_DEPS += ../common/daq2_spi.v
+M_DEPS += ../common/daq2_bd.qsys
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
+M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_hw.tcl
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_if.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_mul.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/altera/MULT_MACRO.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_xcvr.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+
+
+M_ALTERA := quartus_sh --64bit -t 
+
+
+M_FLIST += *.log
+M_FLIST += *_INFO.txt
+M_FLIST += *_dump.txt
+M_FLIST += db
+M_FLIST += *.asm.rpt
+M_FLIST += *.done
+M_FLIST += *.eda.rpt
+M_FLIST += *.fit.*
+M_FLIST += *.map.*
+M_FLIST += *.sta.*
+M_FLIST += *.qsf
+M_FLIST += *.qpf
+M_FLIST += *.qws
+M_FLIST += *.sof
+M_FLIST += *.cdf
+M_FLIST += *.sld
+M_FLIST += *.qdf
+M_FLIST += hc_output
+M_FLIST += system_bd
+M_FLIST += hps_isw_handoff
+M_FLIST += hps_sdram_*.csv
+M_FLIST += *ddr3_*.csv
+M_FLIST += incremental_db
+M_FLIST += reconfig_mif
+M_FLIST += *.sopcinfo
+M_FLIST +=  *.jdi
+M_FLIST += *.pin
+
+
+
+.PHONY: all clean clean-all
+all: daq2_a10gx.sof
+
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+daq2_a10gx.sof: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_ALTERA) system_project.tcl  >> daq2_a10gx_quartus.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/projects/fmcomms2/a10soc/system_bd.qsys b/projects/fmcomms2/a10soc/system_bd.qsys
new file mode 100755
index 000000000..fac722018
--- /dev/null
+++ b/projects/fmcomms2/a10soc/system_bd.qsys
@@ -0,0 +1,680 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element a10gx_base
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element a10gx_base.sys_mem_s_avl
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element daq2
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element daq2.axi_ad9144_core_s_axi
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9144_dma_s_axi
+   {
+      datum baseAddress
+      {
+         value = "229376";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9680_core_s_axi
+   {
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9680_dma_s_axi
+   {
+      datum baseAddress
+      {
+         value = "212992";
+         type = "String";
+      }
+   }
+   element daq2.axi_jesd_xcvr_s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_core_jesd204_rx_s_avl
+   {
+      datum baseAddress
+      {
+         value = "254976";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_core_jesd204_tx_s_avl
+   {
+      datum baseAddress
+      {
+         value = "253952";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_core_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "196608";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_rx_pll_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "251904";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_tx_lane_pll_s_avl
+   {
+      datum baseAddress
+      {
+         value = "245760";
+         type = "String";
+      }
+   }
+   element daq2.xcvr_tx_pll_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "249856";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="10AX115S3F45E2SGE3" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="daq2_a10gx.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_mem"
+   internal="a10gx_base.sys_ddr3_cntrl_mem"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_oct"
+   internal="a10gx_base.sys_ddr3_cntrl_oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_pll_ref_clk"
+   internal="a10gx_base.sys_ddr3_cntrl_pll_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_mdio"
+   internal="a10gx_base.sys_ethernet_mdio"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_ref_clk"
+   internal="a10gx_base.sys_ethernet_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_reset"
+   internal="a10gx_base.sys_ethernet_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="a10gx_base_sys_ethernet_sgmii"
+   internal="a10gx_base.sys_ethernet_sgmii"
+   type="conduit"
+   dir="end" />
+ <interface name="a10gx_base_sys_gpio" internal="a10gx_base.sys_gpio" />
+ <interface
+   name="a10gx_base_sys_gpio_bd"
+   internal="a10gx_base.sys_gpio_bd"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_gpio_in"
+   internal="a10gx_base.sys_gpio_in"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_gpio_out"
+   internal="a10gx_base.sys_gpio_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_spi"
+   internal="a10gx_base.sys_spi"
+   type="conduit"
+   dir="end" />
+ <interface name="daq2_rx_data" internal="daq2.rx_data" type="conduit" dir="end" />
+ <interface
+   name="daq2_rx_ref_clk"
+   internal="daq2.rx_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface name="daq2_rx_sync" internal="daq2.rx_sync" type="conduit" dir="end" />
+ <interface
+   name="daq2_rx_sysref"
+   internal="daq2.rx_sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="daq2_tx_data" internal="daq2.tx_data" type="conduit" dir="end" />
+ <interface
+   name="daq2_tx_ref_clk"
+   internal="daq2.tx_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface name="daq2_tx_sync" internal="daq2.tx_sync" type="conduit" dir="end" />
+ <interface
+   name="daq2_tx_sysref"
+   internal="daq2.tx_sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="sys_reset"
+   internal="sys_clk.clk_in_reset"
+   type="reset"
+   dir="end" />
+ <module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq2_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq2_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq2_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq2_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq2_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_RESET_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
+  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
+ </module>
+ <module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133333250" />
+  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
+  <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
+  <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_TX_REF_CLK_CLOCK_DOMAIN" value="5" />
+  <parameter name="AUTO_TX_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
+  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
+ </module>
+ <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="daq2.axi_ad9144_dma_m_axi"
+   end="a10gx_base.sys_mem_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="daq2.axi_ad9680_dma_m_axi"
+   end="a10gx_base.sys_mem_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9144_core_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9144_dma_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00038000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9680_core_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9680_dma_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00034000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_jesd_xcvr_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_core_jesd204_rx_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003e400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_core_jesd204_tx_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003e000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_core_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00030000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_rx_pll_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003d800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_tx_lane_pll_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003c000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.xcvr_tx_pll_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003d000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.clk"
+   end="a10gx_base.sys_clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.clk" end="daq2.sys_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="a10gx_base.mem_clk"
+   end="daq2.mem_clk" />
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10gx_base.sys_intr"
+   end="daq2.axi_ad9144_dma_intr">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10gx_base.sys_intr"
+   end="daq2.axi_ad9680_dma_intr">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_clk.clk_reset"
+   end="a10gx_base.sys_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_clk.clk_reset"
+   end="daq2.sys_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="a10gx_base.mem_rst"
+   end="daq2.mem_rst" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+</system>
diff --git a/projects/fmcomms2/a10soc/system_constr.sdc b/projects/fmcomms2/a10soc/system_constr.sdc
new file mode 100644
index 000000000..7ec6b3f16
--- /dev/null
+++ b/projects/fmcomms2/a10soc/system_constr.sdc
@@ -0,0 +1,43 @@
+
+create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
+create_clock -period "2.000 ns"   -name rx_ref_clk_500mhz   [get_ports {rx_ref_clk}]
+create_clock -period "2.000 ns"   -name tx_ref_clk_500mhz   [get_ports {tx_ref_clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
+ 
+set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]
+
+set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
diff --git a/projects/fmcomms2/a10soc/system_project.tcl b/projects/fmcomms2/a10soc/system_project.tcl
new file mode 100644
index 000000000..664f75637
--- /dev/null
+++ b/projects/fmcomms2/a10soc/system_project.tcl
@@ -0,0 +1,92 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new daq2_a10gx -overwrite
+
+source "../../common/a10gx/a10gx_system_assign.tcl"
+set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*"
+set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*"
+set_global_assignment -name QSYS_FILE system_bd.qsys
+
+set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
+set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
+set_global_assignment -name VERILOG_FILE system_top.v
+
+set_global_assignment -name SDC_FILE system_constr.sdc
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
+
+# lane interface
+
+set_location_assignment PIN_AJ8   -to rx_ref_clk            ; ## B20  FMCA_GBTCLK1_M2C_P
+set_location_assignment PIN_AJ7   -to "rx_ref_clk(n)"       ; ## B21  FMCA_GBTCLK1_M2C_N
+set_location_assignment PIN_AV5   -to rx_data[0]            ; ## A10  FMCA_DP3_M2C_P
+set_location_assignment PIN_AV6   -to "rx_data[0](n)"       ; ## A11  FMCA_DP3_M2C_N
+set_location_assignment PIN_AW7   -to rx_data[1]            ; ## C06  FMCA_DP0_M2C_P
+set_location_assignment PIN_AW8   -to "rx_data[1](n)"       ; ## C07  FMCA_DP0_M2C_N
+set_location_assignment PIN_AY5   -to rx_data[2]            ; ## A06  FMCA_DP2_M2C_P
+set_location_assignment PIN_AY6   -to "rx_data[2](n)"       ; ## A07  FMCA_DP2_M2C_N
+set_location_assignment PIN_BA7   -to rx_data[3]            ; ## A02  FMCA_DP1_M2C_P
+set_location_assignment PIN_BA8   -to "rx_data[3](n)"       ; ## A03  FMCA_DP1_M2C_N
+set_location_assignment PIN_AT10  -to rx_sync               ; ## D08  FMCA_LA01_CC_P
+set_location_assignment PIN_AR11  -to "rx_sync(n)"          ; ## D09  FMCA_LA01_CC_N
+set_location_assignment PIN_AR20  -to rx_sysref             ; ## G09  FMCA_LA03_P
+set_location_assignment PIN_AR19  -to "rx_sysref(n)"        ; ## G10  FMCA_LA03_N
+set_location_assignment PIN_AL8   -to tx_ref_clk            ; ## D04  FMCA_GBTCLK0_M2C_P
+set_location_assignment PIN_AL7   -to "tx_ref_clk(n)"       ; ## D05  FMCA_GBTCLK0_M2C_N
+set_location_assignment PIN_BC3   -to tx_data[0]            ; ## A30  FMCA_DP3_C2M_P (tx_data_p[0])
+set_location_assignment PIN_BC4   -to "tx_data[0](n)"       ; ## A31  FMCA_DP3_C2M_N (tx_data_n[0])
+set_location_assignment PIN_BC7   -to tx_data[1]            ; ## C02  FMCA_DP0_C2M_P (tx_data_p[3])
+set_location_assignment PIN_BC8   -to "tx_data[1](n)"       ; ## C03  FMCA_DP0_C2M_N (tx_data_n[3])
+set_location_assignment PIN_BB5   -to tx_data[2]            ; ## A26  FMCA_DP2_C2M_P (tx_data_p[1])
+set_location_assignment PIN_BB6   -to "tx_data[2](n)"       ; ## A27  FMCA_DP2_C2M_N (tx_data_n[1])
+set_location_assignment PIN_BD5   -to tx_data[3]            ; ## A22  FMCA_DP1_C2M_P (tx_data_p[2])
+set_location_assignment PIN_BD6   -to "tx_data[3](n)"       ; ## A23  FMCA_DP1_C2M_N (tx_data_n[2])
+set_location_assignment PIN_AR22  -to tx_sync               ; ## H07  FMCA_LA02_P
+set_location_assignment PIN_AT22  -to "tx_sync(n)"          ; ## H08  FMCA_LA02_N
+set_location_assignment PIN_AN20  -to tx_sysref             ; ## H10  FMCA_LA04_P
+set_location_assignment PIN_AP19  -to "tx_sysref(n)"        ; ## H11  FMCA_LA04_N
+
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
+
+# gpio
+
+set_location_assignment PIN_AT17  -to trig                  ; ## H13  FMCA_LA07_P
+set_location_assignment PIN_AU17  -to "trig(n)"             ; ## H14  FMCA_LA07_N
+set_location_assignment PIN_AR14  -to adc_fdb               ; ## H17  FMCA_LA11_N
+set_location_assignment PIN_AT14  -to adc_fda               ; ## H16  FMCA_LA11_P
+set_location_assignment PIN_AR16  -to dac_irq               ; ## G15  FMCA_LA12_P
+set_location_assignment PIN_AP17  -to clkd_status[1]        ; ## D18  FMCA_LA13_N
+set_location_assignment PIN_AR17  -to clkd_status[0]        ; ## D17  FMCA_LA13_P
+set_location_assignment PIN_AV14  -to adc_pd                ; ## C10  FMCA_LA06_P
+set_location_assignment PIN_AP16  -to dac_txen              ; ## G16  FMCA_LA12_N
+set_location_assignment PIN_AT15  -to dac_reset             ; ## C15  FMCA_LA10_N
+set_location_assignment PIN_AP18  -to clkd_sync             ; ## G12  FMCA_LA08_P
+
+set_instance_assignment -name IO_STANDARD LVDS -to trig
+
+# spi
+
+set_location_assignment PIN_AV11  -to spi_csn_clk           ; ## D11  FMCA_LA05_P
+set_location_assignment PIN_AR15  -to spi_csn_dac           ; ## C14  FMCA_LA10_P
+set_location_assignment PIN_AV13  -to spi_csn_adc           ; ## D15  FMCA_LA09_N
+set_location_assignment PIN_AW11  -to spi_clk               ; ## D12  FMCA_LA05_N
+set_location_assignment PIN_AW13  -to spi_sdio              ; ## D14  FMCA_LA09_P
+set_location_assignment PIN_AN19  -to spi_dir               ; ## G13  FMCA_LA08_N
+
+execute_flow -compile
+
diff --git a/projects/fmcomms2/a10soc/system_top.v b/projects/fmcomms2/a10soc/system_top.v
new file mode 100644
index 000000000..7e3d0bfb1
--- /dev/null
+++ b/projects/fmcomms2/a10soc/system_top.v
@@ -0,0 +1,288 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  sys_clk,
+  sys_resetn,
+
+  // ddr3
+
+  ddr3_clk_p,
+  ddr3_clk_n,
+  ddr3_a,
+  ddr3_ba,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_odt,
+  ddr3_reset_n,
+  ddr3_we_n,
+  ddr3_ras_n,
+  ddr3_cas_n,
+  ddr3_dqs_p,
+  ddr3_dqs_n,
+  ddr3_dq,
+  ddr3_dm,
+  ddr3_rzq,
+  ddr3_ref_clk,
+
+  // ethernet
+
+  eth_ref_clk,
+  eth_rxd,
+  eth_txd,
+  eth_mdc,
+  eth_mdio,
+  eth_resetn,
+  eth_intn,
+
+  // board gpio
+
+  gpio_bd_i,
+  gpio_bd_o,
+
+  // lane interface
+
+  rx_ref_clk,
+  rx_sysref,
+  rx_sync,
+  rx_data,
+  tx_ref_clk,
+  tx_sysref,
+  tx_sync,
+  tx_data,
+
+  // gpio
+
+  trig,
+  adc_fdb,
+  adc_fda,
+  dac_irq,
+  clkd_status,
+  adc_pd,
+  dac_txen,
+  dac_reset,
+  clkd_sync,
+
+  // spi
+
+  spi_csn_clk,
+  spi_csn_dac,
+  spi_csn_adc,
+  spi_clk,
+  spi_sdio,
+  spi_dir);
+
+  // clock and resets
+
+  input             sys_clk;
+  input             sys_resetn;
+
+  // ddr3
+
+  output            ddr3_clk_p;
+  output            ddr3_clk_n;
+  output  [ 14:0]   ddr3_a;
+  output  [  2:0]   ddr3_ba;
+  output            ddr3_cke;
+  output            ddr3_cs_n;
+  output            ddr3_odt;
+  output            ddr3_reset_n;
+  output            ddr3_we_n;
+  output            ddr3_ras_n;
+  output            ddr3_cas_n;
+  inout   [  7:0]   ddr3_dqs_p;
+  inout   [  7:0]   ddr3_dqs_n;
+  inout   [ 63:0]   ddr3_dq;
+  output  [  7:0]   ddr3_dm;
+  input             ddr3_rzq;
+  input             ddr3_ref_clk;
+
+  // ethernet
+
+  input             eth_ref_clk;
+  input             eth_rxd;
+  output            eth_txd;
+  output            eth_mdc;
+  inout             eth_mdio;
+  output            eth_resetn;
+  input             eth_intn;
+
+  // board gpio
+
+  input   [ 10:0]   gpio_bd_i;
+  output  [ 15:0]   gpio_bd_o;
+
+  // lane interface
+
+  input             rx_ref_clk;
+  input             rx_sysref;
+  output            rx_sync;
+  input   [  3:0]   rx_data;
+  input             tx_ref_clk;
+  input             tx_sysref;
+  input             tx_sync;
+  output  [  3:0]   tx_data;
+
+  // gpio
+
+  input             trig;
+  input             adc_fdb;
+  input             adc_fda;
+  input             dac_irq;
+  input   [  1:0]   clkd_status;
+  output            adc_pd;
+  output            dac_txen;
+  output            dac_reset;
+  output            clkd_sync;
+
+  // spi
+
+  output            spi_csn_clk;
+  output            spi_csn_dac;
+  output            spi_csn_adc;
+  output            spi_clk;
+  inout             spi_sdio;
+  output            spi_dir;
+
+  // internal signals
+
+  wire              eth_reset;
+  wire              eth_mdio_i;
+  wire              eth_mdio_o;
+  wire              eth_mdio_t;
+  wire    [ 63:0]   gpio_i;
+  wire    [ 63:0]   gpio_o;
+  wire              spi_miso_s;
+  wire              spi_mosi_s;
+  wire    [  7:0]   spi_csn_s;
+
+  // daq2
+
+  assign spi_csn_adc = spi_csn_s[2];
+  assign spi_csn_dac = spi_csn_s[1];
+  assign spi_csn_clk = spi_csn_s[0];
+
+  daq2_spi i_daq2_spi (
+    .spi_csn (spi_csn_s[2:0]),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi_s),
+    .spi_miso (spi_miso_s),
+    .spi_sdio (spi_sdio),
+    .spi_dir (spi_dir));
+
+  // gpio in & out are separate cores
+
+  assign adc_pd = gpio_o[42];
+  assign dac_txen = gpio_o[41];
+  assign dac_reset = gpio_o[40];
+  assign clkd_sync = gpio_o[38];
+
+  assign gpio_i[63:38] = gpio_o[63:38];
+  assign gpio_i[37:37] = trig;
+  assign gpio_i[36:36] = adc_fdb;
+  assign gpio_i[35:35] = adc_fda;
+  assign gpio_i[34:34] = dac_irq;
+  assign gpio_i[33:32] = clkd_status;
+
+  // board stuff
+
+  assign eth_resetn = ~eth_reset;
+  assign eth_mdio_i = eth_mdio;
+  assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
+
+  assign ddr3_a[14:12] = 3'd0;
+
+  assign gpio_i[31:27] = gpio_o[31:27];
+  assign gpio_i[26:16] = gpio_bd_i;
+  assign gpio_i[15: 0] = gpio_o[15:0];
+
+  assign gpio_bd_o = gpio_o[15:0];
+
+  system_bd i_system_bd (
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
+    .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
+    .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc),
+    .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
+    .a10gx_base_sys_ethernet_reset_reset (eth_reset),
+    .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
+    .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
+    .a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
+    .a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
+    .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
+    .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
+    .a10gx_base_sys_spi_MISO (spi_miso_s),
+    .a10gx_base_sys_spi_MOSI (spi_mosi_s),
+    .a10gx_base_sys_spi_SCLK (spi_clk),
+    .a10gx_base_sys_spi_SS_n (spi_csn_s),
+    .daq2_rx_data_rx_serial_data (rx_data),
+    .daq2_rx_ref_clk_clk (rx_ref_clk),
+    .daq2_rx_sync_rx_sync (rx_sync),
+    .daq2_rx_sysref_rx_ext_sysref_in (rx_sysref),
+    .daq2_tx_data_tx_serial_data (tx_data),
+    .daq2_tx_ref_clk_clk (tx_ref_clk),
+    .daq2_tx_sync_tx_sync (tx_sync),
+    .daq2_tx_sysref_tx_ext_sysref_in (tx_sysref),
+    .sys_clk_clk (sys_clk),
+    .sys_reset_reset_n (sys_resetn));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From ad227c1af0a590459d9e369ffb98d11ac126221b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 25 Apr 2016 10:34:17 +0300
Subject: [PATCH 144/972] up_axi: Wait more to a valid read acknowledge.

---
 library/common/up_axi.v | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/library/common/up_axi.v b/library/common/up_axi.v
index 91e1e7c1b..681a49f94 100644
--- a/library/common/up_axi.v
+++ b/library/common/up_axi.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -135,14 +135,14 @@ module up_axi (
   reg             up_rsel = 'd0;
   reg             up_rreq = 'd0;
   reg     [AW:0]  up_raddr = 'd0;
-  reg     [ 3:0]  up_rcount = 'd0;
+  reg     [ 4:0]  up_rcount = 'd0;
   reg             up_rack_int = 'd0;
   reg     [31:0]  up_rdata_int = 'd0;
   reg             up_rack_int_d = 'd0;
   reg     [31:0]  up_rdata_int_d = 'd0;
 
   // write channel interface
- 
+
   assign up_axi_bresp = 2'd0;
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -167,7 +167,7 @@ module up_axi (
         up_axi_bvalid <= 1'b1;
       end
     end
-  end       
+  end
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
@@ -230,7 +230,7 @@ module up_axi (
         up_axi_rdata <= up_rdata_int_d;
       end
     end
-  end       
+  end
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
@@ -251,11 +251,11 @@ module up_axi (
         up_raddr <= up_axi_araddr[AW+2:2];
       end
       if (up_rack_int == 1'b1) begin
-        up_rcount <= 4'd0;
-      end else if (up_rcount[3] == 1'b1) begin
+        up_rcount <= 5'd0;
+      end else if (up_rcount[4] == 1'b1) begin
         up_rcount <= up_rcount + 1'b1;
       end else if (up_rreq == 1'b1) begin
-        up_rcount <= 4'd8;
+        up_rcount <= 5'd16;
       end
     end
   end
@@ -267,7 +267,7 @@ module up_axi (
       up_rack_int_d <= 'd0;
       up_rdata_int_d <= 'd0;
     end else begin
-      if ((up_rcount == 4'hf) && (up_rack == 1'b0)) begin
+      if ((up_rcount == 5'h1f) && (up_rack == 1'b0)) begin
         up_rack_int <= 1'b1;
         up_rdata_int <= {2{16'hdead}};
       end else begin

From 6de356e8fc1f522a67979bc67f61ba59b138995c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 25 Apr 2016 10:55:37 +0300
Subject: [PATCH 145/972] ad7616_sdz: Fix the data width at i_iobuf_adc_cntrl

---
 projects/ad7616_sdz/zc706/system_top_pi.v | 2 +-
 projects/ad7616_sdz/zed/system_top_pi.v   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v
index eb3987837..3a1800ef5 100644
--- a/projects/ad7616_sdz/zc706/system_top_pi.v
+++ b/projects/ad7616_sdz/zc706/system_top_pi.v
@@ -151,7 +151,7 @@ module system_top (
 
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
+  ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl (
     .dio_t (gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
     .dio_i (gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
     .dio_o (gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v
index 916f68b50..f085ca86c 100644
--- a/projects/ad7616_sdz/zed/system_top_pi.v
+++ b/projects/ad7616_sdz/zed/system_top_pi.v
@@ -178,7 +178,7 @@ module system_top (
 
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
+  ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl (
     .dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
     .dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
     .dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),

From 1fd5c0f28b14ae13324363e13b171404bcb04271 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 25 Apr 2016 10:56:45 +0300
Subject: [PATCH 146/972] ad7616_sdz: Fix IO definitions for the parallel
 interface.

---
 projects/ad7616_sdz/zc706/parallel_if_constr.xdc | 2 +-
 projects/ad7616_sdz/zed/parallel_if_constr.xdc   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
index 58144b770..97007b624 100644
--- a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
+++ b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
@@ -11,7 +11,7 @@ set_property -dict {PACKAGE_PIN AC12     IOSTANDARD LVCMOS25} [get_ports adc_db[
 set_property -dict {PACKAGE_PIN AF13     IOSTANDARD LVCMOS25} [get_ports adc_db[7] ]         ; ## FMC_LPC_LA00_CC_N
 set_property -dict {PACKAGE_PIN AE16     IOSTANDARD LVCMOS25} [get_ports adc_db[8] ]         ; ## FMC_LPC_LA05_P
 set_property -dict {PACKAGE_PIN AE12     IOSTANDARD LVCMOS25} [get_ports adc_db[9] ]         ; ## FMC_LPC_LA02_P
-set_property -dict {PACKAGE_PIN AE17     IOSTANDARD LVCMOS25} [get_ports adc_db[10]]         ; ## FMC_LPC_LA16_N
+set_property -dict {PACKAGE_PIN AA15     IOSTANDARD LVCMOS25} [get_ports adc_db[10]]         ; ## FMC_LPC_LA06_P
 set_property -dict {PACKAGE_PIN AE13     IOSTANDARD LVCMOS25} [get_ports adc_db[11]]         ; ## FMC_LPC_LA00_CC_P
 set_property -dict {PACKAGE_PIN AG15     IOSTANDARD LVCMOS25} [get_ports adc_db[12]]         ; ## FMC_LPC_LA01_CC_N
 set_property -dict {PACKAGE_PIN AG16     IOSTANDARD LVCMOS25} [get_ports adc_db[13]]         ; ## FMC_LPC_CLK0_M2C_N
diff --git a/projects/ad7616_sdz/zed/parallel_if_constr.xdc b/projects/ad7616_sdz/zed/parallel_if_constr.xdc
index 914a15002..4c2e01de6 100644
--- a/projects/ad7616_sdz/zed/parallel_if_constr.xdc
+++ b/projects/ad7616_sdz/zed/parallel_if_constr.xdc
@@ -12,7 +12,7 @@ set_property -dict {PACKAGE_PIN L22     IOSTANDARD LVCMOS25} [get_ports adc_db[6
 set_property -dict {PACKAGE_PIN M20     IOSTANDARD LVCMOS25} [get_ports adc_db[7] ]         ; ## FMC_LPC_LA00_CC_N
 set_property -dict {PACKAGE_PIN J18     IOSTANDARD LVCMOS25} [get_ports adc_db[8] ]         ; ## FMC_LPC_LA05_P
 set_property -dict {PACKAGE_PIN P17     IOSTANDARD LVCMOS25} [get_ports adc_db[9] ]         ; ## FMC_LPC_LA02_P
-set_property -dict {PACKAGE_PIN K21     IOSTANDARD LVCMOS25} [get_ports adc_db[10]]         ; ## FMC_LPC_LA16_N
+set_property -dict {PACKAGE_PIN L21     IOSTANDARD LVCMOS25} [get_ports adc_db[10]]         ; ## FMC_LPC_LA06_P
 set_property -dict {PACKAGE_PIN M19     IOSTANDARD LVCMOS25} [get_ports adc_db[11]]         ; ## FMC_LPC_LA00_CC_P
 set_property -dict {PACKAGE_PIN N20     IOSTANDARD LVCMOS25} [get_ports adc_db[12]]         ; ## FMC_LPC_LA01_CC_N
 set_property -dict {PACKAGE_PIN L19     IOSTANDARD LVCMOS25} [get_ports adc_db[13]]         ; ## FMC_LPC_CLK0_M2C_N

From 2ccdd426ecbbe5902d56e3b897dcdbedb048224b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 25 Apr 2016 11:28:22 +0300
Subject: [PATCH 147/972] axi_ad7616: Fix the rd_db_valid generation and do
 some cosmetic changes.

---
 library/axi_ad7616/axi_ad7616.v     |  6 +++---
 library/axi_ad7616/axi_ad7616_pif.v | 26 ++++++++++++++------------
 2 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 600a48533..36db38179 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -177,7 +177,7 @@ module axi_ad7616 (
   wire                              wr_req_s;
   wire    [15:0]                    wr_data_s;
   wire    [15:0]                    rd_data_s;
-  wire                              rd_dvalid_s;
+  wire                              rd_valid_s;
   wire    [ 4:0]                    burst_length_s;
 
   wire                              m_axis_ready_s;
@@ -441,7 +441,7 @@ module axi_ad7616 (
       .wr_req(wr_req_s),
       .wr_data(wr_data_s),
       .rd_data(rd_data_s),
-      .rd_dvalid(rd_dvalid_s)
+      .rd_valid(rd_valid_s)
     );
 
   end
@@ -455,7 +455,7 @@ module axi_ad7616 (
     .busy (busy),
     .up_burst_length (burst_length_s),
     .up_read_data (rd_data_s),
-    .up_read_valid (rd_dvalid_s),
+    .up_read_valid (rd_valid_s),
     .up_write_data (wr_data_s),
     .up_read_req (rd_req_s),
     .up_write_req (wr_req_s),
diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v
index 75a8618f9..a3ca9a098 100644
--- a/library/axi_ad7616/axi_ad7616_pif.v
+++ b/library/axi_ad7616/axi_ad7616_pif.v
@@ -70,7 +70,7 @@ module axi_ad7616_pif (
   wr_req,
   wr_data,
   rd_data,
-  rd_dvalid
+  rd_valid
 );
 
   parameter UP_ADDRESS_WIDTH = 14;
@@ -93,7 +93,7 @@ module axi_ad7616_pif (
   input                           wr_req;
   input   [15:0]                  wr_data;
   output  [15:0]                  rd_data;
-  output                          rd_dvalid;
+  output                          rd_valid;
 
   output  [31:0]                  m_axis_tdata;
   input                           m_axis_tready;
@@ -114,7 +114,7 @@ module axi_ad7616_pif (
 
   reg     [ 2:0]                  transfer_state = 3'h0;
   reg     [ 2:0]                  transfer_state_next = 3'h0;
-  reg     [ 1:0]                  counter = 2'h0;
+  reg     [ 1:0]                  width_counter = 2'h0;
   reg     [ 4:0]                  burst_counter = 5'h0;
 
   reg                             wr_req_d = 1'h0;
@@ -126,6 +126,7 @@ module axi_ad7616_pif (
   reg     [15:0]                  data_out_a = 16'h0;
   reg     [15:0]                  data_out_b = 16'h0;
   reg                             rd_db_valid_div2 = 1'h0;
+  reg                             rd_valid = 1'h0;
 
   // internal wires
 
@@ -148,13 +149,13 @@ module axi_ad7616_pif (
 
   always @(posedge clk) begin
     if (rstn == 1'b0) begin
-      counter <= 2'h0;
+      width_counter <= 2'h0;
     end else begin
       if((transfer_state == CNTRL0_LOW) || (transfer_state == CNTRL0_HIGH) ||
          (transfer_state == CNTRL1_LOW) || (transfer_state == CNTRL1_HIGH))
-        counter <= counter + 1;
+        width_counter <= width_counter + 1;
       else
-        counter <= 2'h0;
+        width_counter <= 2'h0;
     end
   end
 
@@ -188,17 +189,17 @@ module axi_ad7616_pif (
         transfer_state_next <= CNTRL0_LOW;
       end
       CNTRL0_LOW : begin
-        transfer_state_next <= (counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH;
+        transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH;
       end
       CNTRL0_HIGH : begin
-        transfer_state_next <= (counter != 2'b11) ? CNTRL0_HIGH :
+        transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_HIGH :
                                ((wr_req_d == 1'b1) || (rd_req_d == 1'b1)) ? CS_HIGH : CNTRL1_LOW;
       end
       CNTRL1_LOW : begin
-        transfer_state_next <= (counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH;
+        transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH;
       end
       CNTRL1_HIGH : begin
-        transfer_state_next <= (counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
+        transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
       end
       CS_HIGH : begin
         transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW;
@@ -211,7 +212,8 @@ module axi_ad7616_pif (
 
   // data valid for the register access and m_axis interface
 
-  assign rd_db_valid = ((counter == 2'b0) && ((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH))) ? 1'b1 : 1'b0;
+  assign rd_db_valid = ((transfer_state == CS_HIGH) &&
+                       ((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0;
 
   always @(posedge clk) begin
     if (cs_n) begin
@@ -228,10 +230,10 @@ module axi_ad7616_pif (
   always @(posedge clk) begin
     data_out_a <= (rd_db_valid) ? db_i : data_out_a;
     data_out_b <= (rd_db_valid) ? data_out_a : data_out_b;
+    rd_valid <= rd_db_valid;
   end
 
   assign rd_data = data_out_a;
-  assign rd_dvalid = rd_db_valid;
 
   assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
   assign db_t = ~wr_req_d;

From d5d7c12f0e7c2d1d93ce79db5eb63b31d61db501 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 25 Apr 2016 11:36:39 +0300
Subject: [PATCH 148/972] axi_ad7616: Fix the register map

---
 library/axi_ad7616/axi_ad7616_control.v | 27 +++++++++++++------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index df101a1b8..787f74a8f 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -124,8 +124,8 @@ module axi_ad7616_control (
 
   wire            up_rst;
   wire            up_rreq_s;
+  wire            up_rack_s;
   wire            up_wreq_s;
-  wire            end_of_conv_s;
 
   wire    [31:0]  up_read_data_s;
   wire            up_read_valid_s;
@@ -138,7 +138,7 @@ module axi_ad7616_control (
   // the up_[read/write]_data interfaces are valid just in parallel mode
 
   assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
-  assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : 32'hDEAD;
+  assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
 
   // processor write interface
 
@@ -175,21 +175,23 @@ module axi_ad7616_control (
 
   // processor read interface
 
+  assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_rack <= 1'b0;
       up_rdata <= 32'b0;
     end else begin
-      up_rack <= (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
-      if (up_rreq_s == 1'b1) begin
+      up_rack <= up_rack_s;
+      if (up_rack_s == 1'b1) begin
         case (up_raddr[7:0])
-            8'h00 : up_rdata = PCORE_VERSION;
-            8'h01 : up_rdata = ID;
-            8'h02 : up_rdata = up_scratch;
-            8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
-            8'h11 : up_rdata = up_conv_rate;
-            8'h12 : up_rdata = up_burst_length;
-            8'h13 : up_rdata = up_read_data_s;
+          8'h00 : up_rdata = PCORE_VERSION;
+          8'h01 : up_rdata = ID;
+          8'h02 : up_rdata = up_scratch;
+          8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
+          8'h11 : up_rdata = up_conv_rate;
+          8'h12 : up_rdata = {27'b0, up_burst_length};
+          8'h13 : up_rdata = up_read_data_s;
         endcase
       end
     end
@@ -207,7 +209,7 @@ module axi_ad7616_control (
     .clk (up_clk),
     .rst (up_rst),
     .in (busy),
-    .out (end_of_conv_s)
+    .out (end_of_conv)
   );
 
   // convertion start generator
@@ -243,7 +245,6 @@ module axi_ad7616_control (
   end
 
   assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
-  assign end_of_conv = end_of_conv_s;
 
 endmodule
 

From d36d1263c54f3a5f48ac4b3d4866127e9c286e77 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 25 Apr 2016 10:50:09 -0400
Subject: [PATCH 149/972] a10soc- updates

---
 .../common/a10soc/a10soc_system_assign.tcl    |  461 ++--
 projects/common/a10soc/a10soc_system_bd.qsys  | 1978 ++++-------------
 projects/fmcomms2/a10soc/Makefile             |   82 +-
 projects/fmcomms2/a10soc/system_project.tcl   |   83 +-
 4 files changed, 691 insertions(+), 1913 deletions(-)

diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
index 145c90666..913fe193b 100755
--- a/projects/common/a10soc/a10soc_system_assign.tcl
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -2,230 +2,285 @@
 # device settings
 
 set_global_assignment -name FAMILY "Arria 10"
-set_global_assignment -name DEVICE 10AX115S3F45E2SGE3
+set_global_assignment -name DEVICE 10AS066N3F40I2LG
 
 # clocks and resets
 
-set_location_assignment PIN_AR36  -to sys_clk
-set_location_assignment PIN_AR37  -to "sys_clk(n)"
-set_location_assignment PIN_BD27  -to sys_resetn
+set_location_assignment PIN_AM10  -to sys_clk
+set_location_assignment PIN_AL10  -to "sys_clk(n)"
+set_location_assignment PIN_AV21  -to sys_resetn
 set_instance_assignment -name IO_STANDARD LVDS -to sys_clk
 set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn
 
-# ddr3
+# hps-ddr4 (32)
 
-set_location_assignment PIN_F34   -to ddr3_ref_clk
-set_location_assignment PIN_F35   -to "ddr3_ref_clk(n)"
+set_location_assignment PIN_F25   -to hps_ddr_ref_clk
+set_location_assignment PIN_G24   -to "hps_ddr_ref_clk(n)"
 
-set_instance_assignment -name IO_STANDARD LVDS -to ddr3_ref_clk
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ddr3_ref_clk -disable
+set_instance_assignment -name IO_STANDARD LVDS -to hps_ddr_ref_clk
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to hps_ddr_ref_clk -disable
 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[14]
-set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[13]
-set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[12]
+set_location_assignment PIN_B20   -to hps_ddr_clk_p     
+set_location_assignment PIN_B19   -to hps_ddr_clk_n     
+set_location_assignment PIN_B26   -to hps_ddr_a[0]
+set_location_assignment PIN_C26   -to hps_ddr_a[1]
+set_location_assignment PIN_C22   -to hps_ddr_a[2]
+set_location_assignment PIN_C21   -to hps_ddr_a[3]
+set_location_assignment PIN_C25   -to hps_ddr_a[4]
+set_location_assignment PIN_B24   -to hps_ddr_a[5]
+set_location_assignment PIN_B22   -to hps_ddr_a[6]
+set_location_assignment PIN_C23   -to hps_ddr_a[7]
+set_location_assignment PIN_D23   -to hps_ddr_a[8]
+set_location_assignment PIN_E23   -to hps_ddr_a[9]
+set_location_assignment PIN_C24   -to hps_ddr_a[10]
+set_location_assignment PIN_D24   -to hps_ddr_a[11]
+set_location_assignment PIN_F26   -to hps_ddr_a[12]
+set_location_assignment PIN_G26   -to hps_ddr_a[13]
+set_location_assignment PIN_G25   -to hps_ddr_a[14]
+set_location_assignment PIN_F24   -to hps_ddr_a[15]
+set_location_assignment PIN_F23   -to hps_ddr_a[16]
+set_location_assignment PIN_E25   -to hps_ddr_ba[0]
+set_location_assignment PIN_H24   -to hps_ddr_ba[1]
+set_location_assignment PIN_J24   -to hps_ddr_bg
+set_location_assignment PIN_A24   -to hps_ddr_cke
+set_location_assignment PIN_A22   -to hps_ddr_cs_n
+set_location_assignment PIN_A26   -to hps_ddr_odt
+set_location_assignment PIN_A19   -to hps_ddr_reset_n
+set_location_assignment PIN_B21   -to hps_ddr_act_n
+set_location_assignment PIN_A18   -to hps_ddr_par
+set_location_assignment PIN_AG24  -to hps_ddr_alert_n
+set_location_assignment PIN_AM25  -to hps_ddr_dqs_p[0]
+set_location_assignment PIN_AL25  -to hps_ddr_dqs_n[0]
+set_location_assignment PIN_AT25  -to hps_ddr_dqs_p[1]
+set_location_assignment PIN_AT24  -to hps_ddr_dqs_n[1]
+set_location_assignment PIN_AW26  -to hps_ddr_dqs_p[2]
+set_location_assignment PIN_AW25  -to hps_ddr_dqs_n[2]
+set_location_assignment PIN_AK25  -to hps_ddr_dqs_p[3]
+set_location_assignment PIN_AJ25  -to hps_ddr_dqs_n[3]
+set_location_assignment PIN_AP26  -to hps_ddr_dq[0]
+set_location_assignment PIN_AN24  -to hps_ddr_dq[1]
+set_location_assignment PIN_AN23  -to hps_ddr_dq[2]
+set_location_assignment PIN_AM24  -to hps_ddr_dq[3]
+set_location_assignment PIN_AK26  -to hps_ddr_dq[4]
+set_location_assignment PIN_AL23  -to hps_ddr_dq[5]
+set_location_assignment PIN_AL26  -to hps_ddr_dq[6]
+set_location_assignment PIN_AK23  -to hps_ddr_dq[7]
+set_location_assignment PIN_AP23  -to hps_ddr_dq[8]
+set_location_assignment PIN_AT26  -to hps_ddr_dq[9]
+set_location_assignment PIN_AR26  -to hps_ddr_dq[10]
+set_location_assignment PIN_AR25  -to hps_ddr_dq[11]
+set_location_assignment PIN_AT23  -to hps_ddr_dq[12]
+set_location_assignment PIN_AP25  -to hps_ddr_dq[13]
+set_location_assignment PIN_AU24  -to hps_ddr_dq[14]
+set_location_assignment PIN_AU26  -to hps_ddr_dq[15]
+set_location_assignment PIN_AU28  -to hps_ddr_dq[16]
+set_location_assignment PIN_AU27  -to hps_ddr_dq[17]
+set_location_assignment PIN_AV23  -to hps_ddr_dq[18]
+set_location_assignment PIN_AW28  -to hps_ddr_dq[19]
+set_location_assignment PIN_AV24  -to hps_ddr_dq[20]
+set_location_assignment PIN_AW24  -to hps_ddr_dq[21]
+set_location_assignment PIN_AV28  -to hps_ddr_dq[22]
+set_location_assignment PIN_AV27  -to hps_ddr_dq[23]
+set_location_assignment PIN_AH24  -to hps_ddr_dq[24]
+set_location_assignment PIN_AH23  -to hps_ddr_dq[25]
+set_location_assignment PIN_AG25  -to hps_ddr_dq[26]
+set_location_assignment PIN_AF24  -to hps_ddr_dq[27]
+set_location_assignment PIN_AF25  -to hps_ddr_dq[28]
+set_location_assignment PIN_AJ24  -to hps_ddr_dq[29]
+set_location_assignment PIN_AJ23  -to hps_ddr_dq[30]
+set_location_assignment PIN_AJ26  -to hps_ddr_dq[31]
+set_location_assignment PIN_AN26  -to hps_ddr_dbi_n[0]
+set_location_assignment PIN_AU25  -to hps_ddr_dbi_n[1]
+set_location_assignment PIN_AV26  -to hps_ddr_dbi_n[2]
+set_location_assignment PIN_AH25  -to hps_ddr_dbi_n[3]
+set_location_assignment PIN_E26   -to hps_ddr_rzq
 
-set_location_assignment PIN_R30   -to ddr3_clk_p      ; ## 1.5 V   V1  MEM_CLK_P          
-set_location_assignment PIN_R31   -to ddr3_clk_n      ; ## 1.5 V   V2  MEM_CLK_N          
-set_location_assignment PIN_M32   -to ddr3_a[0]       ; ## 1.5 V   F1  MEM_ADDR_CMD0      
-set_location_assignment PIN_L32   -to ddr3_a[1]       ; ## 1.5 V   H1  MEM_ADDR_CMD1      
-set_location_assignment PIN_N34   -to ddr3_a[2]       ; ## 1.5 V   F2  MEM_ADDR_CMD2      
-set_location_assignment PIN_M35   -to ddr3_a[3]       ; ## 1.5 V   G2  MEM_ADDR_CMD3      
-set_location_assignment PIN_L34   -to ddr3_a[4]       ; ## 1.5 V   H2  MEM_ADDR_CMD4      
-set_location_assignment PIN_K34   -to ddr3_a[5]       ; ## 1.5 V   J2  MEM_ADDR_CMD5      
-set_location_assignment PIN_M33   -to ddr3_a[6]       ; ## 1.5 V   K2  MEM_ADDR_CMD6      
-set_location_assignment PIN_L33   -to ddr3_a[7]       ; ## 1.5 V   G3  MEM_ADDR_CMD7      
-set_location_assignment PIN_J33   -to ddr3_a[8]       ; ## 1.5 V   J3  MEM_ADDR_CMD8      
-set_location_assignment PIN_J32   -to ddr3_a[9]       ; ## 1.5 V   L3  MEM_ADDR_CMD9      
-set_location_assignment PIN_H31   -to ddr3_a[10]      ; ## 1.5 V   E4  MEM_ADDR_CMD10     
-set_location_assignment PIN_J31   -to ddr3_a[11]      ; ## 1.5 V   F4  MEM_ADDR_CMD11     
-set_location_assignment PIN_H34   -to ddr3_a[12]      ; ## 1.5 V   G4  MEM_ADDR_CMD12     
-set_location_assignment PIN_H33   -to ddr3_a[13]      ; ## 1.5 V   H4  MEM_ADDR_CMD13     
-set_location_assignment PIN_G32   -to ddr3_a[14]      ; ## 1.5 V   J4  MEM_ADDR_CMD14     
-set_location_assignment PIN_F33   -to ddr3_ba[0]      ; ## 1.5 V   M1  MEM_ADDR_CMD16     
-set_location_assignment PIN_G35   -to ddr3_ba[1]      ; ## 1.5 V   M2  MEM_ADDR_CMD17     
-set_location_assignment PIN_H35   -to ddr3_ba[2]      ; ## 1.5 V   N2  MEM_ADDR_CMD18     
-set_location_assignment PIN_U33   -to ddr3_cke        ; ## 1.5 V   P5  MEM_ADDR_CMD20     
-set_location_assignment PIN_R34   -to ddr3_cs_n       ; ## 1.5 V   P1  MEM_ADDR_CMD22     
-set_location_assignment PIN_N33   -to ddr3_odt        ; ## 1.5 V   M4  MEM_ADDR_CMD24     
-set_location_assignment PIN_T35   -to ddr3_reset_n    ; ## 1.5 V   K1  MEM_ADDR_CMD27     
-set_location_assignment PIN_T34   -to ddr3_we_n       ; ## 1.5 V   P2  MEM_ADDR_CMD28     
-set_location_assignment PIN_F32   -to ddr3_ras_n      ; ## 1.5 V   L2  MEM_ADDR_CMD26     
-set_location_assignment PIN_G33   -to ddr3_cas_n      ; ## 1.5 V   L4  MEM_ADDR_CMD19     
-set_location_assignment PIN_B26   -to ddr3_dqs_p[0]   ; ## 1.5 V   A6  MEM_DQSA_P0        
-set_location_assignment PIN_C26   -to ddr3_dqs_n[0]   ; ## 1.5 V   A7  MEM_DQSA_N0        
-set_location_assignment PIN_H28   -to ddr3_dqs_p[1]   ; ## 1.5 V   A2  MEM_DQSA_P1        
-set_location_assignment PIN_J27   -to ddr3_dqs_n[1]   ; ## 1.5 V   A3  MEM_DQSA_N1        
-set_location_assignment PIN_C30   -to ddr3_dqs_p[2]   ; ## 1.5 V   A14 MEM_DQSA_P2        
-set_location_assignment PIN_C29   -to ddr3_dqs_n[2]   ; ## 1.5 V   A15 MEM_DQSA_N2        
-set_location_assignment PIN_L30   -to ddr3_dqs_p[3]   ; ## 1.5 V   F18 MEM_DQSA_P3        
-set_location_assignment PIN_L29   -to ddr3_dqs_n[3]   ; ## 1.5 V   G18 MEM_DQSA_N3        
-set_location_assignment PIN_Y32   -to ddr3_dqs_p[4]   ; ## 1.5 V   H18 MEM_DQSB_P0        
-set_location_assignment PIN_AA32  -to ddr3_dqs_n[4]   ; ## 1.5 V   J18 MEM_DQSB_N0        
-set_location_assignment PIN_AJ32  -to ddr3_dqs_p[5]   ; ## 1.5 V   U18 MEM_DQSB_P1        
-set_location_assignment PIN_AJ31  -to ddr3_dqs_n[5]   ; ## 1.5 V   V18 MEM_DQSB_N1        
-set_location_assignment PIN_AA34  -to ddr3_dqs_p[6]   ; ## 1.5 V   V16 MEM_DQSB_P2        
-set_location_assignment PIN_AA33  -to ddr3_dqs_n[6]   ; ## 1.5 V   V17 MEM_DQSB_N2        
-set_location_assignment PIN_AF33  -to ddr3_dqs_p[7]   ; ## 1.5 V   V8  MEM_DQSB_P3        
-set_location_assignment PIN_AF34  -to ddr3_dqs_n[7]   ; ## 1.5 V   V9  MEM_DQSB_N3        
-set_location_assignment PIN_B28   -to ddr3_dq[0]      ; ## 1.5 V   A4  MEM_DQA0           
-set_location_assignment PIN_A28   -to ddr3_dq[1]      ; ## 1.5 V   B4  MEM_DQA1           
-set_location_assignment PIN_A27   -to ddr3_dq[2]      ; ## 1.5 V   B5  MEM_DQA2           
-set_location_assignment PIN_B27   -to ddr3_dq[3]      ; ## 1.5 V   B6  MEM_DQA3           
-set_location_assignment PIN_D27   -to ddr3_dq[4]      ; ## 1.5 V   A8  MEM_DQA4           
-set_location_assignment PIN_E27   -to ddr3_dq[5]      ; ## 1.5 V   B8  MEM_DQA5           
-set_location_assignment PIN_D26   -to ddr3_dq[6]      ; ## 1.5 V   B9  MEM_DQA6           
-set_location_assignment PIN_D28   -to ddr3_dq[7]      ; ## 1.5 V   A10 MEM_DQA7           
-set_location_assignment PIN_G25   -to ddr3_dq[8]      ; ## 1.5 V   B1  MEM_DQA8           
-set_location_assignment PIN_H25   -to ddr3_dq[9]      ; ## 1.5 V   B2  MEM_DQA9           
-set_location_assignment PIN_G26   -to ddr3_dq[10]     ; ## 1.5 V   C2  MEM_DQA10          
-set_location_assignment PIN_H26   -to ddr3_dq[11]     ; ## 1.5 V   C3  MEM_DQA11          
-set_location_assignment PIN_G28   -to ddr3_dq[12]     ; ## 1.5 V   E3  MEM_DQA12          
-set_location_assignment PIN_F27   -to ddr3_dq[13]     ; ## 1.5 V   D4  MEM_DQA13          
-set_location_assignment PIN_K27   -to ddr3_dq[14]     ; ## 1.5 V   D1  MEM_DQA14          
-set_location_assignment PIN_F28   -to ddr3_dq[15]     ; ## 1.5 V   D2  MEM_DQA15          
-set_location_assignment PIN_D31   -to ddr3_dq[16]     ; ## 1.5 V   A12 MEM_DQA16          
-set_location_assignment PIN_E31   -to ddr3_dq[17]     ; ## 1.5 V   B12 MEM_DQA17          
-set_location_assignment PIN_B31   -to ddr3_dq[18]     ; ## 1.5 V   B13 MEM_DQA18          
-set_location_assignment PIN_C31   -to ddr3_dq[19]     ; ## 1.5 V   B14 MEM_DQA19          
-set_location_assignment PIN_A30   -to ddr3_dq[20]     ; ## 1.5 V   C15 MEM_DQA20          
-set_location_assignment PIN_E30   -to ddr3_dq[21]     ; ## 1.5 V   A16 MEM_DQA21          
-set_location_assignment PIN_B30   -to ddr3_dq[22]     ; ## 1.5 V   B16 MEM_DQA22          
-set_location_assignment PIN_D29   -to ddr3_dq[23]     ; ## 1.5 V   A18 MEM_DQA23          
-set_location_assignment PIN_K30   -to ddr3_dq[24]     ; ## 1.5 V   C16 MEM_DQA24          
-set_location_assignment PIN_H30   -to ddr3_dq[25]     ; ## 1.5 V   D16 MEM_DQA25          
-set_location_assignment PIN_G30   -to ddr3_dq[26]     ; ## 1.5 V   E16 MEM_DQA26          
-set_location_assignment PIN_K31   -to ddr3_dq[27]     ; ## 1.5 V   F16 MEM_DQA27          
-set_location_assignment PIN_H29   -to ddr3_dq[28]     ; ## 1.5 V   D17 MEM_DQA28          
-set_location_assignment PIN_K29   -to ddr3_dq[29]     ; ## 1.5 V   C18 MEM_DQA29          
-set_location_assignment PIN_J29   -to ddr3_dq[30]     ; ## 1.5 V   D18 MEM_DQA30          
-set_location_assignment PIN_F29   -to ddr3_dq[31]     ; ## 1.5 V   E18 MEM_DQA31          
-set_location_assignment PIN_AC31  -to ddr3_dq[32]     ; ## 1.5 V   H16 MEM_DQB0           
-set_location_assignment PIN_AB31  -to ddr3_dq[33]     ; ## 1.5 V   J16 MEM_DQB1           
-set_location_assignment PIN_W31   -to ddr3_dq[34]     ; ## 1.5 V   K16 MEM_DQB2           
-set_location_assignment PIN_Y31   -to ddr3_dq[35]     ; ## 1.5 V   L16 MEM_DQB3           
-set_location_assignment PIN_AD31  -to ddr3_dq[36]     ; ## 1.5 V   H17 MEM_DQB4           
-set_location_assignment PIN_AD32  -to ddr3_dq[37]     ; ## 1.5 V   K17 MEM_DQB5           
-set_location_assignment PIN_AD33  -to ddr3_dq[38]     ; ## 1.5 V   K18 MEM_DQB6           
-set_location_assignment PIN_AA30  -to ddr3_dq[39]     ; ## 1.5 V   L18 MEM_DQB7           
-set_location_assignment PIN_AE31  -to ddr3_dq[40]     ; ## 1.5 V   M17 MEM_DQB8           
-set_location_assignment PIN_AE32  -to ddr3_dq[41]     ; ## 1.5 V   N18 MEM_DQB9           
-set_location_assignment PIN_AE30  -to ddr3_dq[42]     ; ## 1.5 V   P17 MEM_DQB10          
-set_location_assignment PIN_AF30  -to ddr3_dq[43]     ; ## 1.5 V   P18 MEM_DQB11          
-set_location_assignment PIN_AG33  -to ddr3_dq[44]     ; ## 1.5 V   R18 MEM_DQB12          
-set_location_assignment PIN_AG32  -to ddr3_dq[45]     ; ## 1.5 V   T16 MEM_DQB13          
-set_location_assignment PIN_AH33  -to ddr3_dq[46]     ; ## 1.5 V   T17 MEM_DQB14          
-set_location_assignment PIN_AH31  -to ddr3_dq[47]     ; ## 1.5 V   T18 MEM_DQB15          
-set_location_assignment PIN_U31   -to ddr3_dq[48]     ; ## 1.5 V   U15 MEM_DQB16          
-set_location_assignment PIN_W33   -to ddr3_dq[49]     ; ## 1.5 V   T14 MEM_DQB17          
-set_location_assignment PIN_W32   -to ddr3_dq[50]     ; ## 1.5 V   U14 MEM_DQB18          
-set_location_assignment PIN_V31   -to ddr3_dq[51]     ; ## 1.5 V   V14 MEM_DQB19          
-set_location_assignment PIN_Y34   -to ddr3_dq[52]     ; ## 1.5 V   T13 MEM_DQB20          
-set_location_assignment PIN_W35   -to ddr3_dq[53]     ; ## 1.5 V   T12 MEM_DQB21          
-set_location_assignment PIN_W34   -to ddr3_dq[54]     ; ## 1.5 V   U12 MEM_DQB22          
-set_location_assignment PIN_V34   -to ddr3_dq[55]     ; ## 1.5 V   V12 MEM_DQB23          
-set_location_assignment PIN_AH35  -to ddr3_dq[56]     ; ## 1.5 V   T10 MEM_DQB24          
-set_location_assignment PIN_AJ34  -to ddr3_dq[57]     ; ## 1.5 V   U10 MEM_DQB25          
-set_location_assignment PIN_AJ33  -to ddr3_dq[58]     ; ## 1.5 V   V10 MEM_DQB26          
-set_location_assignment PIN_AH34  -to ddr3_dq[59]     ; ## 1.5 V   T9  MEM_DQB27          
-set_location_assignment PIN_AD35  -to ddr3_dq[60]     ; ## 1.5 V   T8  MEM_DQB28          
-set_location_assignment PIN_AE34  -to ddr3_dq[61]     ; ## 1.5 V   U8  MEM_DQB29          
-set_location_assignment PIN_AC33  -to ddr3_dq[62]     ; ## 1.5 V   U7  MEM_DQB30          
-set_location_assignment PIN_AD34  -to ddr3_dq[63]     ; ## 1.5 V   V6  MEM_DQB31          
-set_location_assignment PIN_E26   -to ddr3_dm[0]      ; ## 1.5 V   B10 MEM_DMA0           
-set_location_assignment PIN_G27   -to ddr3_dm[1]      ; ## 1.5 V   C4  MEM_DMA1           
-set_location_assignment PIN_A29   -to ddr3_dm[2]      ; ## 1.5 V   B17 MEM_DMA2           
-set_location_assignment PIN_F30   -to ddr3_dm[3]      ; ## 1.5 V   F17 MEM_DMA3           
-set_location_assignment PIN_AB32  -to ddr3_dm[4]      ; ## 1.5 V   M16 MEM_DMB0           
-set_location_assignment PIN_AG31  -to ddr3_dm[5]      ; ## 1.5 V   U16 MEM_DMB1           
-set_location_assignment PIN_Y35   -to ddr3_dm[6]      ; ## 1.5 V   U11 MEM_DMB2           
-set_location_assignment PIN_AC34  -to ddr3_dm[7]      ; ## 1.5 V   U6  MEM_DMB3           
-set_location_assignment PIN_J34   -to ddr3_rzq        ; ## RZQ
+# hps-ethernet
 
-# ethernet interface
+set_location_assignment PIN_F18   -to hps_eth_rxclk
+set_location_assignment PIN_G17   -to hps_eth_rxctl
+set_location_assignment PIN_G20   -to hps_eth_rxd0
+set_location_assignment PIN_G21   -to hps_eth_rxd1
+set_location_assignment PIN_F22   -to hps_eth_rxd2
+set_location_assignment PIN_G22   -to hps_eth_rxd3
+set_location_assignment PIN_H18   -to hps_eth_txclk
+set_location_assignment PIN_H19   -to hps_eth_txctl
+set_location_assignment PIN_E20   -to hps_eth_txd0
+set_location_assignment PIN_F20   -to hps_eth_txd1
+set_location_assignment PIN_F19   -to hps_eth_txd2
+set_location_assignment PIN_G19   -to hps_eth_txd3
+set_location_assignment PIN_K20   -to hps_eth_mdc
+set_location_assignment PIN_K21   -to hps_eth_mdio
 
-set_location_assignment PIN_BD24 -to eth_ref_clk
-set_location_assignment PIN_BC24 -to "eth_ref_clk(n)"
-set_location_assignment PIN_AV24 -to eth_rxd
-set_location_assignment PIN_AW24 -to "eth_rxd(n)"
-set_location_assignment PIN_BC23 -to eth_txd
-set_location_assignment PIN_BD23 -to "eth_txd(n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxclk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxctl
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd0
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd1
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd2
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd3
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txclk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txctl
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd0
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd1
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd2
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd3
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_mdc
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_mdio
 
-set_instance_assignment -name IO_STANDARD LVDS -to eth_ref_clk
-set_instance_assignment -name IO_STANDARD LVDS -to eth_rxd
-set_instance_assignment -name IO_STANDARD LVDS -to eth_txd
+set_instance_assignment -name OUTPUT_DELAY_CHAIN 8 -to hps_eth_txclk
 
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_ref_clk -disable
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rxd -disable
+# hps-sdio
 
-set_location_assignment PIN_AW23 -to eth_resetn
-set_location_assignment PIN_AF13 -to eth_mdc
-set_location_assignment PIN_AL18 -to eth_mdio
-set_location_assignment PIN_AG13 -to eth_intn
+set_location_assignment PIN_K16   -to hps_sdio_clk
+set_location_assignment PIN_H16   -to hps_sdio_cmd
+set_location_assignment PIN_E16   -to hps_sdio_d0
+set_location_assignment PIN_G16   -to hps_sdio_d1
+set_location_assignment PIN_H17   -to hps_sdio_d2
+set_location_assignment PIN_F15   -to hps_sdio_d3
+set_location_assignment PIN_M19   -to hps_sdio_d4
+set_location_assignment PIN_E15   -to hps_sdio_d5
+set_location_assignment PIN_J16   -to hps_sdio_d6
+set_location_assignment PIN_L18   -to hps_sdio_d7
 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_resetn
-set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_mdc
-set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_mdio
-set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_intn
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_cmd
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d0
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d1
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d2
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d3
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d4
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d5
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d6
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d7
 
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_ref_clk
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_clk
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_cmd
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d1
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d2
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d3
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d4
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d5
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d6
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d7
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_clk
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_cmd
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d0
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d1
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d2
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d3
 
-# leds
+# hps-usb
 
-set_location_assignment PIN_L28   -to gpio_bd_o[0]  ; ## led-g0-d10
-set_location_assignment PIN_K26   -to gpio_bd_o[1]  ; ## led-g1-d9
-set_location_assignment PIN_K25   -to gpio_bd_o[2]  ; ## led-g2-d8
-set_location_assignment PIN_L25   -to gpio_bd_o[3]  ; ## led-g3-d7
-set_location_assignment PIN_J24   -to gpio_bd_o[4]  ; ## led-g4-d6
-set_location_assignment PIN_A19   -to gpio_bd_o[5]  ; ## led-g5-d5
-set_location_assignment PIN_C18   -to gpio_bd_o[6]  ; ## led-g6-d4
-set_location_assignment PIN_D18   -to gpio_bd_o[7]  ; ## led-g7-d3
-set_location_assignment PIN_L27   -to gpio_bd_o[8]  ; ## led-r0-d10  
-set_location_assignment PIN_J26   -to gpio_bd_o[9]  ; ## led-r1-d9   
-set_location_assignment PIN_K24   -to gpio_bd_o[10] ; ## led-r2-d8
-set_location_assignment PIN_L23   -to gpio_bd_o[11] ; ## led-r3-d7
-set_location_assignment PIN_B20   -to gpio_bd_o[12] ; ## led-r4-d6
-set_location_assignment PIN_C19   -to gpio_bd_o[13] ; ## led-r5-d5
-set_location_assignment PIN_D19   -to gpio_bd_o[14] ; ## led-r6-d4
-set_location_assignment PIN_M23   -to gpio_bd_o[15] ; ## led-r7-d3
-set_location_assignment PIN_A24   -to gpio_bd_i[0]  ; ## dipsw0
-set_location_assignment PIN_B23   -to gpio_bd_i[1]  ; ## dipsw1
-set_location_assignment PIN_A23   -to gpio_bd_i[2]  ; ## dipsw2
-set_location_assignment PIN_B22   -to gpio_bd_i[3]  ; ## dipsw3
-set_location_assignment PIN_A22   -to gpio_bd_i[4]  ; ## dipsw4
-set_location_assignment PIN_B21   -to gpio_bd_i[5]  ; ## dipsw5
-set_location_assignment PIN_C21   -to gpio_bd_i[6]  ; ## dipsw6
-set_location_assignment PIN_A20   -to gpio_bd_i[7]  ; ## dipsw7
-set_location_assignment PIN_T12   -to gpio_bd_i[8]  ; ## pb0-s3
-set_location_assignment PIN_U12   -to gpio_bd_i[9]  ; ## pb1-s2
-set_location_assignment PIN_U11   -to gpio_bd_i[10] ; ## pb2-s1
+set_location_assignment PIN_D18   -to hps_usb_clk
+set_location_assignment PIN_C19   -to hps_usb_dir
+set_location_assignment PIN_F17   -to hps_usb_nxt
+set_location_assignment PIN_E18   -to hps_usb_stp
+set_location_assignment PIN_D19   -to hps_usb_d0
+set_location_assignment PIN_E17   -to hps_usb_d1
+set_location_assignment PIN_C17   -to hps_usb_d2
+set_location_assignment PIN_C18   -to hps_usb_d3
+set_location_assignment PIN_D21   -to hps_usb_d4
+set_location_assignment PIN_D20   -to hps_usb_d5
+set_location_assignment PIN_E21   -to hps_usb_d6
+set_location_assignment PIN_E22   -to hps_usb_d7
 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[4] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[5] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[6] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[7] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[8] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[9] 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[10]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[11]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[12]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[13]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[14]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[15]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_dir
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_nxt
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_stp
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d0
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d1
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d2
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d3
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d4
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d5
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d6
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d7
+
+# hps-uart
+
+set_location_assignment PIN_M17   -to hps_uart_tx
+set_location_assignment PIN_K17   -to hps_uart_rx
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_uart_tx
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_uart_rx
+
+# hps-i2c (shared w fmc-a, fmc-b)
+
+set_location_assignment PIN_M20   -to hps_i2c_scl
+set_location_assignment PIN_L20   -to hps_i2c_sda
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c_scl
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c_sda
+
+# hps-spi (max-v-u16)
+
+set_location_assignment PIN_H21   -to hps_spi_cs0_n
+set_location_assignment PIN_J21   -to hps_spi_cs1_n
+set_location_assignment PIN_K18   -to hps_spi_clk
+set_location_assignment PIN_L19   -to hps_spi_mosi
+set_location_assignment PIN_H22   -to hps_spi_miso
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_cs0_n
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_cs1_n
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_mosi
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_miso
+
+# gpio (max-v-u21)
+
+set_location_assignment PIN_AR23  -to gpio_bd_o[0]  ; ## led[0]
+set_location_assignment PIN_AR22  -to gpio_bd_o[1]  ; ## led[1]
+set_location_assignment PIN_AM21  -to gpio_bd_o[2]  ; ## led[2]
+set_location_assignment PIN_AL20  -to gpio_bd_o[3]  ; ## led[3]
+set_location_assignment PIN_P3    -to gpio_bd_i[0]  ; ## dipsw[0]
+set_location_assignment PIN_P4    -to gpio_bd_i[1]  ; ## dipsw[1]
+set_location_assignment PIN_P1    -to gpio_bd_i[2]  ; ## dipsw[2]
+set_location_assignment PIN_R1    -to gpio_bd_i[3]  ; ## dipsw[3]
+set_location_assignment PIN_R5    -to gpio_bd_i[4]  ; ## pb[0]
+set_location_assignment PIN_T5    -to gpio_bd_i[5]  ; ## pb[1]
+set_location_assignment PIN_P5    -to gpio_bd_i[6]  ; ## pb[2]
+set_location_assignment PIN_P6    -to gpio_bd_i[7]  ; ## pb[3]
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[6]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[7]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3]
+
+# hps-gpio (max-v-u16)
+
+set_location_assignment PIN_J20   -to hps_gpio[0]
+set_location_assignment PIN_N20   -to hps_gpio[1]
+set_location_assignment PIN_K23   -to hps_gpio[2]
+set_location_assignment PIN_L23   -to hps_gpio[3]
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[3]
+
+# hps-trace
+
+set_location_assignment PIN_P20   -to hps_trace_clk
+set_location_assignment PIN_K22   -to hps_trace_d0
+set_location_assignment PIN_L22   -to hps_trace_d1
+set_location_assignment PIN_M22   -to hps_trace_d2
+set_location_assignment PIN_M21   -to hps_trace_d3
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_d0
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_d1
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_d2
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_d3
 
 # globals
 
@@ -237,4 +292,10 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
 set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
+# set libraries
+
+set ad_lib_folders "../common/;../../common/a10soc/;../../../library/**/*"
+
+set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
+set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
 
diff --git a/projects/common/a10soc/a10soc_system_bd.qsys b/projects/common/a10soc/a10soc_system_bd.qsys
index 7bdd08068..7eeb3ca66 100644
--- a/projects/common/a10soc/a10soc_system_bd.qsys
+++ b/projects/common/a10soc/a10soc_system_bd.qsys
@@ -17,19 +17,19 @@
          type = "String";
       }
    }
-   element mem_clk
+   element arria10_hps_0
    {
       datum _sortIndex
       {
-         value = "2";
+         value = "4";
          type = "int";
       }
    }
-   element mem_rst
+   element emif_a10_hps_0
    {
       datum _sortIndex
       {
-         value = "3";
+         value = "5";
          type = "int";
       }
    }
@@ -41,253 +41,31 @@
          type = "int";
       }
    }
-   element sys_cpu
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_cpu.debug_mem_slave
-   {
-      datum baseAddress
-      {
-         value = "270010368";
-         type = "String";
-      }
-   }
    element sys_cpu_interconnect
    {
       datum _sortIndex
       {
-         value = "20";
+         value = "3";
          type = "int";
       }
    }
    element sys_cpu_interconnect.s0
    {
       datum baseAddress
-      {
-         value = "268435456";
-         type = "String";
-      }
-   }
-   element sys_ddr3_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element sys_ethernet
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-      datum sopceditor_expanded
       {
          value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet.control_port
-   {
-      datum baseAddress
-      {
-         value = "270012416";
          type = "String";
       }
    }
-   element sys_ethernet_dma_rx
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-   }
-   element sys_ethernet_dma_rx.csr
-   {
-      datum baseAddress
-      {
-         value = "270013600";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx.descriptor_slave
-   {
-      datum baseAddress
-      {
-         value = "270013504";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx.response
-   {
-      datum baseAddress
-      {
-         value = "270013664";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_tx
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element sys_ethernet_dma_tx.csr
-   {
-      datum baseAddress
-      {
-         value = "270013568";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_tx.descriptor_slave
-   {
-      datum baseAddress
-      {
-         value = "270013536";
-         type = "String";
-      }
-   }
-   element sys_ethernet_reset
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element sys_gpio_bd
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_gpio_bd.s1
-   {
-      datum baseAddress
-      {
-         value = "270013648";
-         type = "String";
-      }
-   }
-   element sys_gpio_in
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-   }
-   element sys_gpio_in.s1
-   {
-      datum baseAddress
-      {
-         value = "270013632";
-         type = "String";
-      }
-   }
-   element sys_gpio_out
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-   }
-   element sys_gpio_out.s1
-   {
-      datum baseAddress
-      {
-         value = "270013696";
-         type = "String";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_id.control_slave
-   {
-      datum baseAddress
-      {
-         value = "270013672";
-         type = "String";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_int_mem.s1
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "269746176";
-         type = "String";
-      }
-   }
-   element sys_irq
-   {
-      datum _sortIndex
-      {
-         value = "22";
-         type = "int";
-      }
-   }
-   element sys_mem_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "21";
-         type = "int";
-      }
-   }
    element sys_rst
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element sys_rst_in
    {
       datum _sortIndex
       {
@@ -295,109 +73,6 @@
          type = "int";
       }
    }
-   element sys_spi
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_spi.spi_control_port
-   {
-      datum baseAddress
-      {
-         value = "270013440";
-         type = "String";
-      }
-   }
-   element sys_timer
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_timer.s1
-   {
-      datum baseAddress
-      {
-         value = "270013472";
-         type = "String";
-      }
-   }
-   element sys_timer_2nd
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element sys_timer_2nd.s1
-   {
-      datum baseAddress
-      {
-         value = "270013728";
-         type = "String";
-      }
-   }
-   element sys_tlb_mem
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element sys_tlb_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "270532608";
-         type = "String";
-      }
-   }
-   element sys_tlb_mem.s2
-   {
-      datum baseAddress
-      {
-         value = "270532608";
-         type = "String";
-      }
-   }
-   element sys_uart
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_uart.avalon_jtag_slave
-   {
-      datum baseAddress
-      {
-         value = "270013680";
-         type = "String";
-      }
-   }
    element system_bd
    {
       datum _originalDeviceFamily
@@ -601,7 +276,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45E2SGE3" />
+ <parameter name="device" value="10AS066N3F40I2LG" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -619,314 +294,313 @@
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
- <interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
- <interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
+ <interface
+   name="hps_ddr"
+   internal="emif_a10_hps_0.mem_conduit_end"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hps_ddr_oct"
+   internal="emif_a10_hps_0.oct_conduit_end"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hps_ddr_ref_clk"
+   internal="emif_a10_hps_0.pll_ref_clk_clock_sink"
+   type="clock"
+   dir="end" />
+ <interface
+   name="hps_gpio"
+   internal="arria10_hps_0.h2f_gp"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hps_io"
+   internal="arria10_hps_0.hps_io"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hps_irq0"
+   internal="arria10_hps_0.f2h_irq0"
+   type="interrupt"
+   dir="start" />
+ <interface
+   name="hps_irq1"
+   internal="arria10_hps_0.f2h_irq1"
+   type="interrupt"
+   dir="start" />
+ <interface
+   name="hps_s0_axi"
+   internal="arria10_hps_0.f2sdram0_data"
+   type="axi"
+   dir="end" />
+ <interface
+   name="hps_s1_axi"
+   internal="arria10_hps_0.f2sdram1_data"
+   type="axi"
+   dir="end" />
+ <interface
+   name="hps_s2_axi"
+   internal="arria10_hps_0.f2sdram2_data"
+   type="axi"
+   dir="end" />
+ <interface
+   name="hps_spi0"
+   internal="arria10_hps_0.spim0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hps_spi0_sclk"
+   internal="arria10_hps_0.spim0_sclk_out"
+   type="clock"
+   dir="start" />
+ <interface
+   name="hps_spi1"
+   internal="arria10_hps_0.spim1"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hps_spi1_sclk"
+   internal="arria10_hps_0.spim1_sclk_out"
+   type="clock"
+   dir="start" />
  <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
  <interface
    name="sys_cpu_m_avl"
    internal="sys_cpu_interconnect.m0"
    type="avalon"
    dir="start" />
+ <interface name="sys_rst" internal="sys_rst.out_reset" type="reset" dir="start" />
  <interface
-   name="sys_ddr3_cntrl_mem"
-   internal="sys_ddr3_cntrl.mem"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ddr3_cntrl_mem_conduit_end"
-   internal="sys_ddr3_cntrl.mem_conduit_end" />
- <interface
-   name="sys_ddr3_cntrl_oct"
-   internal="sys_ddr3_cntrl.oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ddr3_cntrl_oct_conduit_end"
-   internal="sys_ddr3_cntrl.oct_conduit_end" />
- <interface
-   name="sys_ddr3_cntrl_pll_ref_clk"
-   internal="sys_ddr3_cntrl.pll_ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_ddr3_cntrl_ref_clk"
-   internal="sys_ddr3_cntrl.pll_ref_clk_clock_sink" />
- <interface
-   name="sys_ddr3_cntrl_status_conduit_end"
-   internal="sys_ddr3_cntrl.status_conduit_end" />
- <interface
-   name="sys_ethernet_mdio"
-   internal="sys_ethernet.mac_mdio_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_ref_clk"
-   internal="sys_ethernet.pcs_ref_clk_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_ethernet_reset"
-   internal="sys_ethernet_reset.out_reset"
+   name="sys_rst_in"
+   internal="sys_rst_in.in_reset"
    type="reset"
-   dir="start" />
- <interface
-   name="sys_ethernet_rgmii"
-   internal="sys_ethernet.mac_rgmii_connection" />
- <interface
-   name="sys_ethernet_rx_clk"
-   internal="sys_ethernet.pcs_mac_rx_clock_connection" />
- <interface
-   name="sys_ethernet_sgmii"
-   internal="sys_ethernet.serial_connection"
-   type="conduit"
    dir="end" />
- <interface
-   name="sys_ethernet_status"
-   internal="sys_ethernet.mac_status_connection" />
- <interface
-   name="sys_ethernet_tx_clk"
-   internal="sys_ethernet.pcs_mac_tx_clock_connection" />
- <interface
-   name="sys_gpio_bd"
-   internal="sys_gpio_bd.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_in"
-   internal="sys_gpio_in.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_out"
-   internal="sys_gpio_out.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_intr"
-   internal="sys_irq.receiver_irq"
-   type="interrupt"
-   dir="start" />
- <interface
-   name="sys_mem_s_avl"
-   internal="sys_mem_interconnect.s0"
-   type="avalon"
-   dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="133333250" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="bht_ramBlockType" value="Automatic" />
-  <parameter name="breakOffset" value="32" />
-  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
-  <parameter name="cdx_enabled" value="false" />
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="cpuArchRev" value="1" />
-  <parameter name="cpuID" value="0" />
-  <parameter name="cpuReset" value="false" />
-  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
-  <parameter name="dataAddrWidth" value="29" />
-  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_cpu_interconnect.s0' start='0x10000000' end='0x10100000' type='altera_avalon_mm_bridge.s0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2nd.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
-  <parameter name="data_master_high_performance_paddr_base" value="0" />
-  <parameter name="data_master_high_performance_paddr_size" value="0" />
-  <parameter name="data_master_paddr_base" value="0" />
-  <parameter name="data_master_paddr_size" value="0" />
-  <parameter name="dcache_bursts" value="false" />
-  <parameter name="dcache_numTCDM" value="1" />
-  <parameter name="dcache_ramBlockType" value="Automatic" />
-  <parameter name="dcache_size" value="32768" />
-  <parameter name="dcache_tagramBlockType" value="Automatic" />
-  <parameter name="dcache_victim_buf_impl" value="ram" />
-  <parameter name="debug_OCIOnchipTrace" value="_128" />
-  <parameter name="debug_assignJtagInstanceID" value="false" />
-  <parameter name="debug_datatrigger" value="0" />
-  <parameter name="debug_debugReqSignals" value="false" />
-  <parameter name="debug_enabled" value="true" />
-  <parameter name="debug_hwbreakpoint" value="0" />
-  <parameter name="debug_jtagInstanceID" value="0" />
-  <parameter name="debug_traceStorage" value="onchip_trace" />
-  <parameter name="debug_traceType" value="none" />
-  <parameter name="debug_triggerArming" value="true" />
-  <parameter name="deviceFamilyName" value="Arria 10" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
-  <parameter name="dividerType" value="no_div" />
-  <parameter name="exceptionOffset" value="32" />
-  <parameter name="exceptionSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
-  <parameter name="faAddrWidth" value="1" />
-  <parameter name="faSlaveMapParam" value="" />
-  <parameter name="fa_cache_line" value="2" />
-  <parameter name="fa_cache_linesize" value="0" />
-  <parameter name="flash_instruction_master_paddr_base" value="0" />
-  <parameter name="flash_instruction_master_paddr_size" value="0" />
-  <parameter name="icache_burstType" value="None" />
-  <parameter name="icache_numTCIM" value="1" />
-  <parameter name="icache_ramBlockType" value="Automatic" />
-  <parameter name="icache_size" value="32768" />
-  <parameter name="icache_tagramBlockType" value="Automatic" />
-  <parameter name="impl" value="Fast" />
-  <parameter name="instAddrWidth" value="29" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
-  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
-  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
-  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
-  <parameter name="instruction_master_paddr_base" value="0" />
-  <parameter name="instruction_master_paddr_size" value="0" />
-  <parameter name="internalIrqMaskSystemInfo" value="65535" />
-  <parameter name="io_regionbase" value="0" />
-  <parameter name="io_regionsize" value="0" />
-  <parameter name="master_addr_map" value="false" />
-  <parameter name="mmu_TLBMissExcOffset" value="4096" />
-  <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
-  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="false" />
-  <parameter name="mmu_processIDNumBits" value="8" />
-  <parameter name="mmu_ramBlockType" value="Automatic" />
-  <parameter name="mmu_tlbNumWays" value="16" />
-  <parameter name="mmu_tlbPtrSz" value="7" />
-  <parameter name="mmu_udtlbNumEntries" value="6" />
-  <parameter name="mmu_uitlbNumEntries" value="4" />
-  <parameter name="mpu_enabled" value="false" />
-  <parameter name="mpu_minDataRegionSize" value="12" />
-  <parameter name="mpu_minInstRegionSize" value="12" />
-  <parameter name="mpu_numOfDataRegion" value="8" />
-  <parameter name="mpu_numOfInstRegion" value="8" />
-  <parameter name="mpu_useLimit" value="false" />
-  <parameter name="mpx_enabled" value="false" />
-  <parameter name="mul_32_impl" value="3" />
-  <parameter name="mul_64_impl" value="0" />
-  <parameter name="mul_shift_choice" value="0" />
-  <parameter name="ocimem_ramBlockType" value="Automatic" />
-  <parameter name="ocimem_ramInit" value="false" />
-  <parameter name="regfile_ramBlockType" value="Automatic" />
-  <parameter name="resetOffset" value="0" />
-  <parameter name="resetSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="setting_HBreakTest" value="false" />
-  <parameter name="setting_HDLSimCachesCleared" value="true" />
-  <parameter name="setting_activateMonitors" value="true" />
-  <parameter name="setting_activateTestEndChecker" value="false" />
-  <parameter name="setting_activateTrace" value="true" />
-  <parameter name="setting_allow_break_inst" value="false" />
-  <parameter name="setting_alwaysEncrypt" value="true" />
-  <parameter name="setting_asic_add_scan_mode_input" value="false" />
-  <parameter name="setting_asic_enabled" value="false" />
-  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
-  <parameter name="setting_asic_third_party_synthesis" value="false" />
-  <parameter name="setting_avalonDebugPortPresent" value="false" />
-  <parameter name="setting_bhtPtrSz" value="8" />
-  <parameter name="setting_bigEndian" value="false" />
-  <parameter name="setting_branchpredictiontype" value="Dynamic" />
-  <parameter name="setting_breakslaveoveride" value="false" />
-  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
-  <parameter name="setting_dc_ecc_present" value="false" />
-  <parameter name="setting_disable_tmr_inj" value="false" />
-  <parameter name="setting_disableocitrace" value="false" />
-  <parameter name="setting_dtcm_ecc_present" value="false" />
-  <parameter name="setting_ecc_present" value="false" />
-  <parameter name="setting_ecc_sim_test_ports" value="false" />
-  <parameter name="setting_exportHostDebugPort" value="false" />
-  <parameter name="setting_exportPCB" value="false" />
-  <parameter name="setting_export_large_RAMs" value="false" />
-  <parameter name="setting_exportdebuginfo" value="false" />
-  <parameter name="setting_exportvectors" value="false" />
-  <parameter name="setting_fast_register_read" value="false" />
-  <parameter name="setting_ic_ecc_present" value="true" />
-  <parameter name="setting_interruptControllerType" value="Internal" />
-  <parameter name="setting_itcm_ecc_present" value="false" />
-  <parameter name="setting_mmu_ecc_present" value="true" />
-  <parameter name="setting_oci_export_jtag_signals" value="false" />
-  <parameter name="setting_oci_version" value="1" />
-  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
-  <parameter name="setting_removeRAMinit" value="false" />
-  <parameter name="setting_rf_ecc_present" value="true" />
-  <parameter name="setting_shadowRegisterSets" value="0" />
-  <parameter name="setting_showInternalSettings" value="false" />
-  <parameter name="setting_showUnpublishedSettings" value="false" />
-  <parameter name="setting_support31bitdcachebypass" value="false" />
-  <parameter name="setting_usedesignware" value="false" />
-  <parameter name="shift_rot_impl" value="0" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
-  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
-  <parameter name="tmr_enabled" value="false" />
-  <parameter name="tracefilename" value="" />
-  <parameter name="userDefinedSettings" value="" />
- </module>
  <module
-   name="sys_cpu_interconnect"
-   kind="altera_avalon_mm_bridge"
+   name="arria10_hps_0"
+   kind="altera_arria10_hps"
    version="15.1"
    enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="20" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DATA_WIDTH" value="32" />
-  <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="MAX_PENDING_RESPONSES" value="4" />
-  <parameter name="PIPELINE_COMMAND" value="1" />
-  <parameter name="PIPELINE_RESPONSE" value="1" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
-  <parameter name="USE_RESPONSE" value="0" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="BOOT_FROM_FPGA_Enable" value="false" />
+  <parameter name="BSEL" value="1" />
+  <parameter name="BSEL_EN" value="false" />
+  <parameter name="CLK_EMACA_SOURCE" value="1" />
+  <parameter name="CLK_EMACB_SOURCE" value="1" />
+  <parameter name="CLK_EMAC_PTP_SOURCE" value="1" />
+  <parameter name="CLK_GPIO_SOURCE" value="1" />
+  <parameter name="CLK_HMC_PLL_SOURCE" value="0" />
+  <parameter name="CLK_MAIN_PLL_SOURCE2" value="0" />
+  <parameter name="CLK_MPU_CNT" value="0" />
+  <parameter name="CLK_MPU_SOURCE" value="0" />
+  <parameter name="CLK_NOC_CNT" value="0" />
+  <parameter name="CLK_NOC_SOURCE" value="0" />
+  <parameter name="CLK_PERI_PLL_SOURCE2" value="0" />
+  <parameter name="CLK_S2F_USER0_SOURCE" value="0" />
+  <parameter name="CLK_S2F_USER1_SOURCE" value="0" />
+  <parameter name="CLK_SDMMC_SOURCE" value="1" />
+  <parameter name="CM_Mode" value="N/A" />
+  <parameter name="CM_PinMuxing" value="Unused" />
+  <parameter name="CTI_Enable" value="false" />
+  <parameter name="CUSTOM_MPU_CLK" value="800" />
+  <parameter name="DEBUG_APB_Enable" value="false" />
+  <parameter name="DISABLE_PERI_PLL" value="false" />
+  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
+  <parameter name="EMAC0_CLK" value="250" />
+  <parameter name="EMAC0_Mode" value="RGMII_with_MDIO" />
+  <parameter name="EMAC0_PTP" value="false" />
+  <parameter name="EMAC0_PinMuxing" value="IO" />
+  <parameter name="EMAC0_SWITCH_Enable" value="false" />
+  <parameter name="EMAC1_CLK" value="250" />
+  <parameter name="EMAC1_Mode" value="N/A" />
+  <parameter name="EMAC1_PTP" value="false" />
+  <parameter name="EMAC1_PinMuxing" value="Unused" />
+  <parameter name="EMAC1_SWITCH_Enable" value="false" />
+  <parameter name="EMAC2_CLK" value="250" />
+  <parameter name="EMAC2_Mode" value="N/A" />
+  <parameter name="EMAC2_PTP" value="false" />
+  <parameter name="EMAC2_PinMuxing" value="Unused" />
+  <parameter name="EMAC2_SWITCH_Enable" value="false" />
+  <parameter name="EMAC_PTP_REF_CLK" value="100" />
+  <parameter name="EMIF_CONDUIT_Enable" value="true" />
+  <parameter name="F2H_AXI_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_COLD_RST_Enable" value="true" />
+  <parameter name="F2H_DBG_RST_Enable" value="false" />
+  <parameter name="F2H_FREE_CLK_Enable" value="false" />
+  <parameter name="F2H_FREE_CLK_FREQ" value="200" />
+  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_WARM_RST_Enable" value="false" />
+  <parameter name="F2SDRAM0_ENABLED" value="true" />
+  <parameter name="F2SDRAM1_ENABLED" value="true" />
+  <parameter name="F2SDRAM2_ENABLED" value="true" />
+  <parameter name="F2SDRAM_ADDRESS_WIDTH" value="32" />
+  <parameter name="F2SDRAM_PORT_CONFIG" value="5" />
+  <parameter name="F2SDRAM_READY_LATENCY" value="false" />
+  <parameter name="F2SINTERRUPT_Enable" value="true" />
+  <parameter name="F2S_Width" value="0" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_TX_CLK_IN" value="100" />
+  <parameter
+     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
+     value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC0_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC1_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC2_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDMMC_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="2.5" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="2.5" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK" value="2.5" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
+  <parameter name="GPIO_REF_CLK" value="4" />
+  <parameter name="GP_Enable" value="true" />
+  <parameter name="H2F_AXI_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_COLD_RST_Enable" value="false" />
+  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="100000000" />
+  <parameter name="H2F_PENDING_RST_Enable" value="false" />
+  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
+  <parameter name="H2F_USER0_CLK_Enable" value="false" />
+  <parameter name="H2F_USER0_CLK_FREQ" value="400" />
+  <parameter name="H2F_USER1_CLK_Enable" value="false" />
+  <parameter name="H2F_USER1_CLK_FREQ" value="400" />
+  <parameter name="HMC_PLL_REF_CLK" value="800" />
+  <parameter name="HPS_DIV_GPIO_FREQ" value="125" />
+  <parameter name="HPS_IO_Enable">SDMMC:D0,SDMMC:CMD,SDMMC:CCLK,SDMMC:D1,SDMMC:D2,SDMMC:D3,NONE,NONE,SDMMC:D4,SDMMC:D5,SDMMC:D6,SDMMC:D7,UART1:TX,UART1:RX,USB0:CLK,USB0:STP,USB0:DIR,USB0:DATA0,USB0:DATA1,USB0:NXT,USB0:DATA2,USB0:DATA3,USB0:DATA4,USB0:DATA5,USB0:DATA6,USB0:DATA7,EMAC0:TX_CLK,EMAC0:TX_CTL,EMAC0:RX_CLK,EMAC0:RX_CTL,EMAC0:TXD0,EMAC0:TXD1,EMAC0:RXD0,EMAC0:RXD1,EMAC0:TXD2,EMAC0:TXD3,EMAC0:RXD2,EMAC0:RXD3,NONE,NONE,NONE,NONE,NONE,GPIO,NONE,NONE,NONE,NONE,MDIO0:MDIO,MDIO0:MDC,I2C1:SDA,I2C1:SCL,GPIO,NONE,GPIO,GPIO,NONE,NONE,NONE,NONE,NONE,NONE</parameter>
+  <parameter name="I2C0_Mode" value="N/A" />
+  <parameter name="I2C0_PinMuxing" value="Unused" />
+  <parameter name="I2C1_Mode" value="default" />
+  <parameter name="I2C1_PinMuxing" value="IO" />
+  <parameter name="I2CEMAC0_Mode" value="N/A" />
+  <parameter name="I2CEMAC0_PinMuxing" value="Unused" />
+  <parameter name="I2CEMAC1_Mode" value="N/A" />
+  <parameter name="I2CEMAC1_PinMuxing" value="Unused" />
+  <parameter name="I2CEMAC2_Mode" value="N/A" />
+  <parameter name="I2CEMAC2_PinMuxing" value="Unused" />
+  <parameter name="INTERNAL_OSCILLATOR_ENABLE" value="60" />
+  <parameter name="JTAG_Enable" value="false" />
+  <parameter name="L3_MAIN_FREE_CLK" value="400" />
+  <parameter name="L4_SYS_FREE_CLK" value="1" />
+  <parameter name="LWH2F_Enable" value="1" />
+  <parameter name="MPU_CLK_VCCL" value="0" />
+  <parameter name="MPU_EVENTS_Enable" value="false" />
+  <parameter name="NAND_Mode" value="N/A" />
+  <parameter name="NAND_PinMuxing" value="Unused" />
+  <parameter name="NOCDIV_CS_ATCLK" value="0" />
+  <parameter name="NOCDIV_CS_PDBGCLK" value="1" />
+  <parameter name="NOCDIV_CS_TRACECLK" value="0" />
+  <parameter name="NOCDIV_L4MAINCLK" value="0" />
+  <parameter name="NOCDIV_L4MPCLK" value="1" />
+  <parameter name="NOCDIV_L4SPCLK" value="2" />
+  <parameter name="OVERIDE_PERI_PLL" value="false" />
+  <parameter name="PERI_PLL_MANUAL_VCO_FREQ" value="2000" />
+  <parameter name="PLL_CLK0" value="Unused" />
+  <parameter name="PLL_CLK1" value="Unused" />
+  <parameter name="PLL_CLK2" value="Unused" />
+  <parameter name="PLL_CLK3" value="Unused" />
+  <parameter name="PLL_CLK4" value="Unused" />
+  <parameter name="QSPI_Mode" value="N/A" />
+  <parameter name="QSPI_PinMuxing" value="Unused" />
+  <parameter name="RUN_INTERNAL_BUILD_CHECKS" value="0" />
+  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_EMAC0_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_EMAC1_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_EMAC2_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_HMC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2C0_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2C1_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CEMAC0_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CEMAC1_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CEMAC2_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPIM0_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPIM1_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPIS0_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPIS1_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SYSTEMMANAGER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SYSTIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_UART0_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_UART1_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_USB0_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_USB1_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
+  <parameter name="S2F_Width" value="0" />
+  <parameter name="SDMMC_Mode" value="8-bit" />
+  <parameter name="SDMMC_PinMuxing" value="IO" />
+  <parameter name="SDMMC_REF_CLK" value="200" />
+  <parameter name="SECURITY_MODULE_Enable" value="false" />
+  <parameter name="SPIM0_Mode">Single_slave_selects</parameter>
+  <parameter name="SPIM0_PinMuxing" value="FPGA" />
+  <parameter name="SPIM1_Mode">Single_slave_selects</parameter>
+  <parameter name="SPIM1_PinMuxing" value="FPGA" />
+  <parameter name="SPIS0_Mode" value="N/A" />
+  <parameter name="SPIS0_PinMuxing" value="Unused" />
+  <parameter name="SPIS1_Mode" value="N/A" />
+  <parameter name="SPIS1_PinMuxing" value="Unused" />
+  <parameter name="STM_Enable" value="false" />
+  <parameter name="TESTIOCTRL_DEBUGCLKSEL" value="16" />
+  <parameter name="TESTIOCTRL_MAINCLKSEL" value="8" />
+  <parameter name="TESTIOCTRL_PERICLKSEL" value="8" />
+  <parameter name="TEST_Enable" value="false" />
+  <parameter name="TRACE_Mode" value="N/A" />
+  <parameter name="TRACE_PinMuxing" value="Unused" />
+  <parameter name="UART0_Mode" value="N/A" />
+  <parameter name="UART0_PinMuxing" value="Unused" />
+  <parameter name="UART1_Mode" value="No_flow_control" />
+  <parameter name="UART1_PinMuxing" value="IO" />
+  <parameter name="USB0_Mode" value="default" />
+  <parameter name="USB0_PinMuxing" value="IO" />
+  <parameter name="USB1_Mode" value="N/A" />
+  <parameter name="USB1_PinMuxing" value="Unused" />
+  <parameter name="USE_DEFAULT_MPU_CLK" value="false" />
+  <parameter name="device_name" value="10AS066N3F40I2LG" />
+  <parameter name="eosc1_clk_mhz" value="25.0" />
+  <parameter name="quartus_ini_hps_ip_boot_from_fpga_ready" value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_a10_advanced_options" value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_emac_switch" value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_jtag" value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_sdmmc_clk_in" value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
+  <parameter name="quartus_ini_hps_ip_override_sdmmc_4bit" value="false" />
  </module>
- <module name="sys_ddr3_cntrl" kind="altera_emif" version="15.1" enabled="1">
+ <module
+   name="emif_a10_hps_0"
+   kind="altera_emif_a10_hps"
+   version="15.1"
+   enabled="1">
   <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
   <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
   <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
@@ -943,7 +617,7 @@
   <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
   <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
   <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="5.0" />
   <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
   <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
   <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
@@ -968,7 +642,7 @@
   <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
   <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
   <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="8.0" />
   <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
   <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
   <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
@@ -1017,7 +691,7 @@
   <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
   <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
   <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="4.0" />
   <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
   <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
   <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
@@ -1041,9 +715,9 @@
   <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
   <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
   <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="5.0" />
   <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="3.5" />
+  <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="2.5" />
   <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
   <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
   <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
@@ -1066,7 +740,7 @@
   <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
   <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
   <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="7.0" />
   <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
   <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
   <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
@@ -1080,7 +754,7 @@
   <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
   <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
   <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
   <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
   <parameter name="CTRL_DDR3_ECC_EN" value="false" />
   <parameter name="CTRL_DDR3_MMR_EN" value="false" />
@@ -1099,7 +773,7 @@
   <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
   <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
   <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
   <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
   <parameter name="CTRL_DDR4_ECC_EN" value="false" />
   <parameter name="CTRL_DDR4_MMR_EN" value="false" />
@@ -1118,7 +792,7 @@
   <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
   <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
   <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
   <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
   <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
   <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
@@ -1152,7 +826,7 @@
   <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
   <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
   <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
   <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
   <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
@@ -1169,14 +843,14 @@
   <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
   <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
   <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
   <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
   <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
   <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
   <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
   <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
-  <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+  <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="true" />
   <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="false" />
   <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
@@ -1209,7 +883,7 @@
   <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
   <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
   <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="false" />
   <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
   <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
@@ -1222,7 +896,7 @@
   <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
   <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
   <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
   <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
   <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
@@ -1236,7 +910,7 @@
   <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
   <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
   <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="false" />
   <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
   <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
@@ -1249,7 +923,7 @@
   <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
   <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
   <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="false" />
   <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
   <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
@@ -1328,16 +1002,16 @@
   <parameter name="MEM_DDR3_DLL_EN" value="true" />
   <parameter name="MEM_DDR3_DM_EN" value="true" />
   <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DDR3_DQ_WIDTH" value="64" />
+  <parameter name="MEM_DDR3_DQ_WIDTH" value="32" />
   <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
   <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
-  <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="0x0" />
+  <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="000000000000000000" />
   <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
   <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
   <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
   <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0" />
-  <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="12" />
+  <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="15" />
   <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
   <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
   <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
@@ -1355,7 +1029,7 @@
   <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
   <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
   <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
-  <parameter name="MEM_DDR3_TCL" value="13" />
+  <parameter name="MEM_DDR3_TCL" value="14" />
   <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
   <parameter name="MEM_DDR3_TDH_PS" value="55" />
   <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
@@ -1375,10 +1049,10 @@
   <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
   <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
   <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
-  <parameter name="MEM_DDR3_TRCD_NS" value="10.285" />
+  <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
   <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
   <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
-  <parameter name="MEM_DDR3_TRP_NS" value="10.285" />
+  <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
   <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
   <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
   <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
@@ -1386,7 +1060,7 @@
   <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
   <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
   <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_DDR3_WTCL" value="9" />
+  <parameter name="MEM_DDR3_WTCL" value="10" />
   <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
   <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
   <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
@@ -1404,13 +1078,13 @@
   <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
   <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
   <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_AUTO</parameter>
+  <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="3" />
+  <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
   <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
   <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
   <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
   <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
-  <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+  <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="1" />
   <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
   <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
   <parameter name="MEM_DDR4_CAL_MODE" value="0" />
@@ -1423,7 +1097,7 @@
   <parameter name="MEM_DDR4_DLL_EN" value="true" />
   <parameter name="MEM_DDR4_DM_EN" value="true" />
   <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+  <parameter name="MEM_DDR4_DQ_WIDTH" value="32" />
   <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
   <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
   <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
@@ -1438,14 +1112,14 @@
   <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
   <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
   <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR4_RDIMM_CONFIG">0000000000000000000000000000000F000000</parameter>
-  <parameter name="MEM_DDR4_READ_DBI" value="false" />
+  <parameter name="MEM_DDR4_RDIMM_CONFIG">00000000000000000000000000000000000000</parameter>
+  <parameter name="MEM_DDR4_READ_DBI" value="true" />
   <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
   <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
   <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_DDR4_RTT_NOM_ENUM">DDR4_RTT_NOM_ODT_DISABLED</parameter>
+  <parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_6" />
   <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR4_RTT_WR_ENUM" value="DDR4_RTT_WR_RZQ_1" />
+  <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
   <parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
   <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,off" />
   <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
@@ -1460,10 +1134,10 @@
   <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
   <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
   <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
-  <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
+  <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2666" />
   <parameter name="MEM_DDR4_TCCD_L_CYC" value="6" />
   <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
-  <parameter name="MEM_DDR4_TCL" value="18" />
+  <parameter name="MEM_DDR4_TCL" value="20" />
   <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
   <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
   <parameter name="MEM_DDR4_TDQSCK_PS" value="165" />
@@ -1475,7 +1149,7 @@
   <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
   <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
   <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
-  <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
+  <parameter name="MEM_DDR4_TFAW_NS" value="30.0" />
   <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
   <parameter name="MEM_DDR4_TIH_PS" value="95" />
   <parameter name="MEM_DDR4_TINIT_US" value="500" />
@@ -1486,25 +1160,25 @@
   <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
   <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
   <parameter name="MEM_DDR4_TRAS_NS" value="32.0" />
-  <parameter name="MEM_DDR4_TRCD_NS" value="15.0" />
+  <parameter name="MEM_DDR4_TRCD_NS" value="14.25" />
   <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
   <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
-  <parameter name="MEM_DDR4_TRP_NS" value="15.0" />
-  <parameter name="MEM_DDR4_TRRD_L_CYC" value="6" />
-  <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+  <parameter name="MEM_DDR4_TRP_NS" value="14.25" />
+  <parameter name="MEM_DDR4_TRRD_L_CYC" value="8" />
+  <parameter name="MEM_DDR4_TRRD_S_CYC" value="7" />
   <parameter name="MEM_DDR4_TWLH_PS" value="108.0" />
   <parameter name="MEM_DDR4_TWLS_PS" value="108.0" />
   <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
-  <parameter name="MEM_DDR4_TWTR_L_CYC" value="9" />
-  <parameter name="MEM_DDR4_TWTR_S_CYC" value="3" />
+  <parameter name="MEM_DDR4_TWTR_L_CYC" value="10" />
+  <parameter name="MEM_DDR4_TWTR_S_CYC" value="4" />
   <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
-  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="60.0" />
+  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="56.0" />
   <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
   <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
   <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
   <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
   <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
-  <parameter name="MEM_DDR4_WTCL" value="12" />
+  <parameter name="MEM_DDR4_WTCL" value="18" />
   <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
   <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
   <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
@@ -1674,54 +1348,54 @@
   <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
   <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
   <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_DDR3_DEFAULT_IO" value="false" />
+  <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
   <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
   <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
-  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="533.333" />
-  <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+  <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_HALF" />
   <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_15_C1" />
-  <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="CURRENT_ST_12" />
+  <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
   <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_15_C1" />
-  <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="CURRENT_ST_12" />
+  <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
   <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="IN_OCT_40_CAL" />
-  <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="IO_STD_SSTL_15" />
-  <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
+  <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
   <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_LVDS" />
+  <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
   <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
-  <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_15" />
+  <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
   <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
   <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
-  <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_DDR4_DEFAULT_IO" value="false" />
+  <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
   <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
-  <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+  <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_HALF" />
   <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
   <parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
-  <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+  <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="OUT_OCT_40_CAL" />
   <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+  <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
   <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_60_CAL" />
+  <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
+  <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
   <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+  <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="133.333" />
+  <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_12" />
   <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
   <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
   <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
   <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
   <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
   <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
-  <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_HALF" />
   <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
   <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
   <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
@@ -1860,273 +1534,36 @@
   <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
   <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
   <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
-  <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR3" />
-  <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
-  <parameter name="SYS_INFO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+  <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
+  <parameter name="SYS_INFO_DEVICE" value="10AS066N3F40I2LG" />
   <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
+  <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_emif_a10_hps_0</parameter>
   <parameter name="TRAIT_SUPPORTS_VID" value="0" />
  </module>
- <module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="core_variation" value="MAC_PCS" />
-  <parameter name="deviceFamilyName" value="Arria 10" />
-  <parameter name="eg_addr" value="12" />
-  <parameter name="ena_hash" value="false" />
-  <parameter name="enable_alt_reconfig" value="false" />
-  <parameter name="enable_ecc" value="false" />
-  <parameter name="enable_ena" value="32" />
-  <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_hd_logic" value="false" />
-  <parameter name="enable_mac_flow_ctrl" value="false" />
-  <parameter name="enable_mac_vlan" value="false" />
-  <parameter name="enable_magic_detect" value="true" />
-  <parameter name="enable_ptp_1step" value="false" />
-  <parameter name="enable_sgmii" value="true" />
-  <parameter name="enable_shift16" value="true" />
-  <parameter name="enable_sup_addr" value="false" />
-  <parameter name="enable_timestamping" value="false" />
-  <parameter name="enable_use_internal_fifo" value="true" />
-  <parameter name="export_pwrdn" value="false" />
-  <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ifGMII" value="MII_GMII" />
-  <parameter name="ing_addr" value="12" />
-  <parameter name="max_channels" value="1" />
-  <parameter name="mdio_clk_div" value="40" />
-  <parameter name="nf_phyip_rcfg_enable" value="false" />
-  <parameter name="phy_identifier" value="0" />
-  <parameter name="phyip_en_synce_support" value="false" />
-  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
-  <parameter name="phyip_pll_type" value="CMU" />
-  <parameter name="phyip_pma_bonding_mode" value="x1" />
-  <parameter name="starting_channel_number" value="0" />
-  <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="transceiver_type" value="LVDS_IO" />
-  <parameter name="tstamp_fp_width" value="4" />
-  <parameter name="useMDIO" value="true" />
-  <parameter name="use_mac_clken" value="false" />
-  <parameter name="use_misc_ports" value="true" />
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
  <module
-   name="sys_ethernet_dma_rx"
-   kind="altera_msgdma"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="6" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="2" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="0" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_ethernet_dma_tx"
-   kind="altera_msgdma"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="1" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="1" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="2" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_ethernet_reset"
-   kind="altera_reset_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module
-   name="sys_gpio_bd"
-   kind="altera_avalon_pio"
-   version="15.1"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_in"
-   kind="altera_avalon_pio"
-   version="15.1"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_out"
-   kind="altera_avalon_pio"
-   version="15.1"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="id" value="182193580" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria 10" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="false" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="163840" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module name="sys_irq" kind="altera_irq_bridge" version="15.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
-  <parameter name="IRQ_N" value="0" />
-  <parameter name="IRQ_WIDTH" value="8" />
- </module>
- <module
-   name="sys_mem_interconnect"
+   name="sys_cpu_interconnect"
    kind="altera_avalon_mm_bridge"
    version="15.1"
    enabled="1">
   <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="29" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
+  <parameter name="ADDRESS_WIDTH" value="32" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DATA_WIDTH" value="512" />
+  <parameter name="DATA_WIDTH" value="32" />
   <parameter name="LINEWRAPBURSTS" value="0" />
   <parameter name="MAX_BURST_SIZE" value="1" />
   <parameter name="MAX_PENDING_RESPONSES" value="4" />
   <parameter name="PIPELINE_COMMAND" value="1" />
   <parameter name="PIPELINE_RESPONSE" value="1" />
   <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="28" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
   <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
   <parameter name="USE_RESPONSE" value="0" />
  </module>
@@ -2137,664 +1574,93 @@
   <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="15.1" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="0" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="100000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="8" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="128000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
  <module
-   name="sys_timer"
-   kind="altera_avalon_timer"
+   name="sys_rst_in"
+   kind="altera_reset_bridge"
    version="15.1"
    enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_timer_2nd"
-   kind="altera_avalon_timer"
-   version="15.1"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_tlb_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tlb_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria 10" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="163840" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sys_uart"
-   kind="altera_avalon_jtag_uart"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowMultipleConnections" value="false" />
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="100000000" />
-  <parameter name="hubInstanceID" value="0" />
-  <parameter name="readBufferDepth" value="64" />
-  <parameter name="readIRQThreshold" value="8" />
-  <parameter name="simInputCharacterStream" value="" />
-  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
-  <parameter name="useRegistersForReadBuffer" value="false" />
-  <parameter name="useRegistersForWriteBuffer" value="false" />
-  <parameter name="useRelativePathForSimFile" value="false" />
-  <parameter name="writeBufferDepth" value="64" />
-  <parameter name="writeIRQThreshold" value="8" />
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
  <connection
    kind="avalon"
    version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_uart.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814f0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet.control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814e8" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814a0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181480" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10180800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181460" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181440" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.response">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814e0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
+   start="arria10_hps_0.h2f_lw_axi_master"
    end="sys_cpu_interconnect.s0">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10140000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_timer.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181420" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio_bd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814d0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio_in.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio_out.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181500" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_timer_2nd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181520" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_spi.spi_control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10180800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10140000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_mem_interconnect.m0"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_ethernet_dma_tx.mm_read"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_ethernet_dma_rx.mm_write"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.tightly_coupled_data_master_0"
-   end="sys_tlb_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.tightly_coupled_instruction_master_0"
-   end="sys_tlb_mem.s2">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="sys_ethernet.receive"
-   end="sys_ethernet_dma_rx.st_sink" />
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="sys_ethernet_dma_tx.st_source"
-   end="sys_ethernet.transmit" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_clk"
-   end="sys_mem_interconnect.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_clk"
-   end="mem_rst.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_clk"
-   end="mem_clk.in_clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_cpu.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="sys_uart.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_timer.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_id.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_gpio_bd.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_spi.clk" />
+   end="sys_rst_in.clk" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
    end="sys_cpu_interconnect.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_irq.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="sys_ethernet_reset.clk" />
+   end="arria10_hps_0.f2sdram0_clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="sys_gpio_in.clk" />
+   end="arria10_hps_0.f2sdram1_clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="sys_gpio_out.clk" />
+   end="arria10_hps_0.f2sdram2_clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="sys_timer_2nd.clk" />
+   end="arria10_hps_0.h2f_lw_axi_clock" />
  <connection
-   kind="clock"
+   kind="conduit"
    version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_tlb_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_tlb_mem.clk2" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet_dma_rx.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet_dma_tx.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet.control_port_clock_connection" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet.receive_clock_connection" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet.transmit_clock_connection" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_rx.csr_irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_tx.csr_irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_uart.irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_timer.irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection kind="interrupt" version="15.1" start="sys_cpu.irq" end="sys_spi.irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_gpio_bd.irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_gpio_in.irq">
-  <parameter name="irqNumber" value="8" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_timer_2nd.irq">
-  <parameter name="irqNumber" value="15" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender0_irq">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender1_irq">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender2_irq">
-  <parameter name="irqNumber" value="9" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender3_irq">
-  <parameter name="irqNumber" value="10" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender4_irq">
-  <parameter name="irqNumber" value="11" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender5_irq">
-  <parameter name="irqNumber" value="12" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender6_irq">
-  <parameter name="irqNumber" value="13" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender7_irq">
-  <parameter name="irqNumber" value="14" />
+   start="emif_a10_hps_0.hps_emif_conduit_end"
+   end="arria10_hps_0.emif">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
  </connection>
  <connection
    kind="reset"
    version="15.1"
-   start="sys_cpu.debug_reset_request"
-   end="sys_cpu.reset" />
+   start="arria10_hps_0.h2f_reset"
+   end="sys_rst.in_reset" />
  <connection
    kind="reset"
    version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_reset_n"
-   end="mem_rst.in_reset" />
+   start="sys_rst_in.out_reset"
+   end="arria10_hps_0.f2h_cold_reset_req" />
  <connection
    kind="reset"
    version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_reset_n"
-   end="sys_mem_interconnect.reset" />
+   start="sys_rst_in.out_reset"
+   end="emif_a10_hps_0.global_reset_reset_sink" />
  <connection
    kind="reset"
    version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_irq.clk_reset" />
+   start="sys_rst_in.out_reset"
+   end="sys_rst.in_reset" />
  <connection
    kind="reset"
    version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ddr3_cntrl.global_reset_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet_reset.in_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_uart.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_timer.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio_bd.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_spi.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
+   start="sys_rst_in.out_reset"
    end="sys_cpu_interconnect.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio_in.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio_out.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_timer_2nd.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_int_mem.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_tlb_mem.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_tlb_mem.reset2" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet.reset_connection" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet_dma_rx.reset_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet_dma_tx.reset_n" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
diff --git a/projects/fmcomms2/a10soc/Makefile b/projects/fmcomms2/a10soc/Makefile
index 51c24bfef..77133e4f4 100644
--- a/projects/fmcomms2/a10soc/Makefile
+++ b/projects/fmcomms2/a10soc/Makefile
@@ -9,81 +9,9 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += system_bd.qsys
-M_DEPS += ../common/daq2_spi.v
-M_DEPS += ../common/daq2_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
-M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144_hw.tcl
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144_if.v
-M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
-M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
-M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
-M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
-M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
-M_DEPS += ../../../library/axi_dmac/2d_transfer.v
-M_DEPS += ../../../library/axi_dmac/address_generator.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
-M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
-M_DEPS += ../../../library/axi_dmac/data_mover.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
-M_DEPS += ../../../library/axi_dmac/inc_id.h
-M_DEPS += ../../../library/axi_dmac/request_arb.v
-M_DEPS += ../../../library/axi_dmac/request_generator.v
-M_DEPS += ../../../library/axi_dmac/resp.h
-M_DEPS += ../../../library/axi_dmac/response_generator.v
-M_DEPS += ../../../library/axi_dmac/response_handler.v
-M_DEPS += ../../../library/axi_dmac/splitter.v
-M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
-M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_dds.v
-M_DEPS += ../../../library/common/ad_dds_1.v
-M_DEPS += ../../../library/common/ad_dds_sine.v
-M_DEPS += ../../../library/common/ad_jesd_align.v
-M_DEPS += ../../../library/common/ad_mul.v
-M_DEPS += ../../../library/common/ad_pnmon.v
-M_DEPS += ../../../library/common/ad_rst.v
-M_DEPS += ../../../library/common/altera/MULT_MACRO.v
-M_DEPS += ../../../library/common/sync_bits.v
-M_DEPS += ../../../library/common/sync_gray.v
-M_DEPS += ../../../library/common/up_adc_channel.v
-M_DEPS += ../../../library/common/up_adc_common.v
-M_DEPS += ../../../library/common/up_axi.v
-M_DEPS += ../../../library/common/up_clock_mon.v
-M_DEPS += ../../../library/common/up_dac_channel.v
-M_DEPS += ../../../library/common/up_dac_common.v
-M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_xcvr.v
-M_DEPS += ../../../library/common/up_xfer_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
-M_DEPS += ../../../library/util_axis_fifo/address_gray.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
-M_DEPS += ../../../library/util_axis_fifo/address_sync.v
-M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
-M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
-M_DEPS += ../../../library/util_cpack/util_cpack.v
-M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
-M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
-M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
-M_DEPS += ../../../library/util_upack/util_upack.v
-M_DEPS += ../../../library/util_upack/util_upack_dmx.v
-M_DEPS += ../../../library/util_upack/util_upack_dsf.v
-M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
+M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
@@ -120,7 +48,7 @@ M_FLIST += *.pin
 
 
 .PHONY: all clean clean-all
-all: daq2_a10gx.sof
+all: fmcomms2_a10soc.sof
 
 
 
@@ -131,9 +59,9 @@ clean-all:
 	rm -rf $(M_FLIST)
 
 
-daq2_a10gx.sof: $(M_DEPS)
+fmcomms2_a10soc.sof: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_ALTERA) system_project.tcl  >> daq2_a10gx_quartus.log 2>&1
+	$(M_ALTERA) system_project.tcl  >> fmcomms2_a10soc_quartus.log 2>&1
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcomms2/a10soc/system_project.tcl b/projects/fmcomms2/a10soc/system_project.tcl
index 664f75637..561871428 100644
--- a/projects/fmcomms2/a10soc/system_project.tcl
+++ b/projects/fmcomms2/a10soc/system_project.tcl
@@ -2,91 +2,14 @@
 load_package flow
 
 source ../../scripts/adi_env.tcl
-project_new daq2_a10gx -overwrite
+project_new fmcomms2_a10soc -overwrite
+
+source "../../common/a10soc/a10soc_system_assign.tcl"
 
-source "../../common/a10gx/a10gx_system_assign.tcl"
-set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*"
-set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*"
 set_global_assignment -name QSYS_FILE system_bd.qsys
-
-set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
-set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
-
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
 
-# lane interface
-
-set_location_assignment PIN_AJ8   -to rx_ref_clk            ; ## B20  FMCA_GBTCLK1_M2C_P
-set_location_assignment PIN_AJ7   -to "rx_ref_clk(n)"       ; ## B21  FMCA_GBTCLK1_M2C_N
-set_location_assignment PIN_AV5   -to rx_data[0]            ; ## A10  FMCA_DP3_M2C_P
-set_location_assignment PIN_AV6   -to "rx_data[0](n)"       ; ## A11  FMCA_DP3_M2C_N
-set_location_assignment PIN_AW7   -to rx_data[1]            ; ## C06  FMCA_DP0_M2C_P
-set_location_assignment PIN_AW8   -to "rx_data[1](n)"       ; ## C07  FMCA_DP0_M2C_N
-set_location_assignment PIN_AY5   -to rx_data[2]            ; ## A06  FMCA_DP2_M2C_P
-set_location_assignment PIN_AY6   -to "rx_data[2](n)"       ; ## A07  FMCA_DP2_M2C_N
-set_location_assignment PIN_BA7   -to rx_data[3]            ; ## A02  FMCA_DP1_M2C_P
-set_location_assignment PIN_BA8   -to "rx_data[3](n)"       ; ## A03  FMCA_DP1_M2C_N
-set_location_assignment PIN_AT10  -to rx_sync               ; ## D08  FMCA_LA01_CC_P
-set_location_assignment PIN_AR11  -to "rx_sync(n)"          ; ## D09  FMCA_LA01_CC_N
-set_location_assignment PIN_AR20  -to rx_sysref             ; ## G09  FMCA_LA03_P
-set_location_assignment PIN_AR19  -to "rx_sysref(n)"        ; ## G10  FMCA_LA03_N
-set_location_assignment PIN_AL8   -to tx_ref_clk            ; ## D04  FMCA_GBTCLK0_M2C_P
-set_location_assignment PIN_AL7   -to "tx_ref_clk(n)"       ; ## D05  FMCA_GBTCLK0_M2C_N
-set_location_assignment PIN_BC3   -to tx_data[0]            ; ## A30  FMCA_DP3_C2M_P (tx_data_p[0])
-set_location_assignment PIN_BC4   -to "tx_data[0](n)"       ; ## A31  FMCA_DP3_C2M_N (tx_data_n[0])
-set_location_assignment PIN_BC7   -to tx_data[1]            ; ## C02  FMCA_DP0_C2M_P (tx_data_p[3])
-set_location_assignment PIN_BC8   -to "tx_data[1](n)"       ; ## C03  FMCA_DP0_C2M_N (tx_data_n[3])
-set_location_assignment PIN_BB5   -to tx_data[2]            ; ## A26  FMCA_DP2_C2M_P (tx_data_p[1])
-set_location_assignment PIN_BB6   -to "tx_data[2](n)"       ; ## A27  FMCA_DP2_C2M_N (tx_data_n[1])
-set_location_assignment PIN_BD5   -to tx_data[3]            ; ## A22  FMCA_DP1_C2M_P (tx_data_p[2])
-set_location_assignment PIN_BD6   -to "tx_data[3](n)"       ; ## A23  FMCA_DP1_C2M_N (tx_data_n[2])
-set_location_assignment PIN_AR22  -to tx_sync               ; ## H07  FMCA_LA02_P
-set_location_assignment PIN_AT22  -to "tx_sync(n)"          ; ## H08  FMCA_LA02_N
-set_location_assignment PIN_AN20  -to tx_sysref             ; ## H10  FMCA_LA04_P
-set_location_assignment PIN_AP19  -to "tx_sysref(n)"        ; ## H11  FMCA_LA04_N
-
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
-set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
-set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
-set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
-set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
-
-# gpio
-
-set_location_assignment PIN_AT17  -to trig                  ; ## H13  FMCA_LA07_P
-set_location_assignment PIN_AU17  -to "trig(n)"             ; ## H14  FMCA_LA07_N
-set_location_assignment PIN_AR14  -to adc_fdb               ; ## H17  FMCA_LA11_N
-set_location_assignment PIN_AT14  -to adc_fda               ; ## H16  FMCA_LA11_P
-set_location_assignment PIN_AR16  -to dac_irq               ; ## G15  FMCA_LA12_P
-set_location_assignment PIN_AP17  -to clkd_status[1]        ; ## D18  FMCA_LA13_N
-set_location_assignment PIN_AR17  -to clkd_status[0]        ; ## D17  FMCA_LA13_P
-set_location_assignment PIN_AV14  -to adc_pd                ; ## C10  FMCA_LA06_P
-set_location_assignment PIN_AP16  -to dac_txen              ; ## G16  FMCA_LA12_N
-set_location_assignment PIN_AT15  -to dac_reset             ; ## C15  FMCA_LA10_N
-set_location_assignment PIN_AP18  -to clkd_sync             ; ## G12  FMCA_LA08_P
-
-set_instance_assignment -name IO_STANDARD LVDS -to trig
-
-# spi
-
-set_location_assignment PIN_AV11  -to spi_csn_clk           ; ## D11  FMCA_LA05_P
-set_location_assignment PIN_AR15  -to spi_csn_dac           ; ## C14  FMCA_LA10_P
-set_location_assignment PIN_AV13  -to spi_csn_adc           ; ## D15  FMCA_LA09_N
-set_location_assignment PIN_AW11  -to spi_clk               ; ## D12  FMCA_LA05_N
-set_location_assignment PIN_AW13  -to spi_sdio              ; ## D14  FMCA_LA09_P
-set_location_assignment PIN_AN19  -to spi_dir               ; ## G13  FMCA_LA08_N
-
 execute_flow -compile
 

From 0a3967b8863ad585ec322b7943173ddbb22bff95 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 25 Apr 2016 10:53:26 -0400
Subject: [PATCH 150/972] a10soc- updates

---
 projects/fmcomms2/common/fmcomms2_bd.qsys | 756 ++++++++++++++++++++++
 1 file changed, 756 insertions(+)
 create mode 100755 projects/fmcomms2/common/fmcomms2_bd.qsys

diff --git a/projects/fmcomms2/common/fmcomms2_bd.qsys b/projects/fmcomms2/common/fmcomms2_bd.qsys
new file mode 100755
index 000000000..ffbb1cae5
--- /dev/null
+++ b/projects/fmcomms2/common/fmcomms2_bd.qsys
@@ -0,0 +1,756 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element ad9361_clk_bridge
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element adc_pack
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element axi_ad9361
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_ad9361.s_axi
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element axi_dmac_adc
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_dmac_adc.s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element axi_dmac_dac
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_dmac_dac.s_axi
+   {
+      datum baseAddress
+      {
+         value = "16384";
+         type = "String";
+      }
+   }
+   element dac_upack
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element gpio
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element mem_clk
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element mem_rst
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element spi_ad9361
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element spi_ad9361.spi_control_port
+   {
+      datum baseAddress
+      {
+         value = "32768";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_rst
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="5CSXFC6D6F31C8ES" />
+ <parameter name="deviceFamily" value="Cyclone V" />
+ <parameter name="deviceSpeedGrade" value="8_H6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="axi_ad9361_device_clock"
+   internal="axi_ad9361.device_clock"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_ad9361_device_if"
+   internal="axi_ad9361.device_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9361_l_clk"
+   internal="ad9361_clk_bridge.out_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="axi_ad9361_s_axi"
+   internal="axi_ad9361.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_dmac_adc_fifo_wr_clock"
+   internal="axi_dmac_adc.fifo_wr_clock" />
+ <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
+ <interface
+   name="axi_dmac_adc_intr"
+   internal="axi_dmac_adc.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_dmac_adc_m_dest_axi"
+   internal="axi_dmac_adc.m_dest_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_dmac_adc_s_axi"
+   internal="axi_dmac_adc.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_dmac_dac_fifo_rd_clock"
+   internal="axi_dmac_dac.fifo_rd_clock" />
+ <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
+ <interface
+   name="axi_dmac_dac_intr"
+   internal="axi_dmac_dac.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_dmac_dac_m_src_axi"
+   internal="axi_dmac_dac.m_src_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_dmac_dac_s_axi"
+   internal="axi_dmac_dac.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="gpio_external_connection"
+   internal="gpio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="gpio_s1" internal="gpio.s1" type="avalon" dir="end" />
+ <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
+ <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
+ <interface
+   name="spi_ad9361_external"
+   internal="spi_ad9361.external"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="spi_ad9361_irq"
+   internal="spi_ad9361.irq"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="spi_ad9361_spi_control_port"
+   internal="spi_ad9361.spi_control_port"
+   type="avalon"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
+ <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
+ <module
+   name="ad9361_clk_bridge"
+   kind="altera_clock_bridge"
+   version="15.1"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="0" />
+ </module>
+ <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="0" />
+  <parameter name="DMA_TYPE_SRC" value="2" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
+ </module>
+ <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="1" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="2" />
+  <parameter name="DMA_TYPE_SRC" value="0" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="0" />
+ </module>
+ <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="5" />
+ </module>
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="1" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="50000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="1" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="50000000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <connection
+   kind="clock"
+   version="15.1"
+   start="axi_ad9361.if_l_clk"
+   end="adc_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="axi_ad9361.if_l_clk"
+   end="dac_upack.if_dac_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="axi_ad9361.if_l_clk"
+   end="axi_dmac_dac.if_fifo_rd_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="axi_ad9361.if_l_clk"
+   end="axi_dmac_adc.if_fifo_wr_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="axi_ad9361.if_l_clk"
+   end="ad9361_clk_bridge.in_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="spi_ad9361.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_ad9361.delay_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="mem_clk.out_clk"
+   end="axi_dmac_adc.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="mem_clk.out_clk"
+   end="axi_dmac_dac.m_src_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_ad9361.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_dmac_adc.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_dmac_dac.s_axi_clock" />
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="dac_upack.fifo_ch_0"
+   end="axi_ad9361.fifo_ch_0_out">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.fifo_ch_0_in"
+   end="adc_pack.fifo_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.fifo_ch_1_in"
+   end="adc_pack.fifo_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.fifo_ch_1_out"
+   end="dac_upack.fifo_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.fifo_ch_2_in"
+   end="adc_pack.fifo_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.fifo_ch_2_out"
+   end="dac_upack.fifo_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.fifo_ch_3_in"
+   end="adc_pack.fifo_ch_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.fifo_ch_3_out"
+   end="dac_upack.fifo_ch_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_pack.if_adc_data"
+   end="axi_dmac_adc.if_fifo_wr_din">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_pack.if_adc_sync"
+   end="axi_dmac_adc.if_fifo_wr_sync">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_pack.if_adc_valid"
+   end="axi_dmac_adc.if_fifo_wr_en">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="dac_upack.if_dac_data"
+   end="axi_dmac_dac.if_fifo_rd_dout">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="dac_upack.if_dma_xfer_in"
+   end="axi_dmac_dac.if_fifo_rd_xfer_req">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_dmac_dac.if_fifo_rd_en"
+   end="dac_upack.if_dac_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_dmac_dac.if_fifo_rd_underflow"
+   end="axi_ad9361.if_dac_dunf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_dmac_adc.if_fifo_wr_overflow"
+   end="axi_ad9361.if_adc_dovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="15.1"
+   start="axi_ad9361.if_rst"
+   end="adc_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="adc_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="mem_rst.out_reset"
+   end="adc_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="mem_rst.out_reset"
+   end="axi_dmac_adc.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="mem_rst.out_reset"
+   end="axi_dmac_dac.m_src_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="spi_ad9361.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="gpio.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_ad9361.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_dmac_adc.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_dmac_dac.s_axi_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+ <interconnectRequirement
+   for="mm_interconnect_0|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_2|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+</system>

From 28159aeec921f9c332d906114d271331b1e617cb Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 25 Apr 2016 11:11:46 -0400
Subject: [PATCH 151/972] a10soc- updates

---
 projects/fmcomms2/a10soc/system_bd.qsys   | 351 +++++++++-------------
 projects/fmcomms2/common/fmcomms2_bd.qsys | 157 +---------
 2 files changed, 148 insertions(+), 360 deletions(-)

diff --git a/projects/fmcomms2/a10soc/system_bd.qsys b/projects/fmcomms2/a10soc/system_bd.qsys
index fac722018..8421219c0 100755
--- a/projects/fmcomms2/a10soc/system_bd.qsys
+++ b/projects/fmcomms2/a10soc/system_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element a10gx_base
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
    element a10gx_base.sys_mem_s_avl
    {
       datum _lockedAddress
@@ -30,14 +22,30 @@
          type = "String";
       }
    }
-   element daq2
+   element a10soc
    {
       datum _sortIndex
       {
-         value = "2";
+         value = "1";
          type = "int";
       }
    }
+   element a10soc.hps_s0_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element a10soc.hps_s1_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
    element daq2.axi_ad9144_core_s_axi
    {
       datum baseAddress
@@ -126,6 +134,38 @@
          type = "String";
       }
    }
+   element fmcomms2
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element fmcomms2.axi_ad9361_s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element fmcomms2.axi_dmac_adc_s_axi
+   {
+      datum baseAddress
+      {
+         value = "81920";
+         type = "String";
+      }
+   }
+   element fmcomms2.axi_dmac_dac_s_axi
+   {
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
    element sys_clk
    {
       datum _sortIndex
@@ -361,7 +401,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45E2SGE3" />
+ <parameter name="device" value="10AS066N3F40I2LG" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -372,7 +412,7 @@
  <parameter name="hideFromIPCatalog" value="false" />
  <parameter name="lockedInterfaceDefinition" value="" />
  <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="daq2_a10gx.qpf" />
+ <parameter name="projectName" value="fmcomms2_a10soc.qpf" />
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="0" />
  <parameter name="testBenchDutName" value="" />
@@ -380,136 +420,78 @@
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
-   name="a10gx_base_sys_ddr3_cntrl_mem"
-   internal="a10gx_base.sys_ddr3_cntrl_mem"
+   name="ad9361_if"
+   internal="fmcomms2.axi_ad9361_device_if"
+   type="conduit"
+   dir="end" />
+ <interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
+ <interface
+   name="hps_ddr_oct"
+   internal="a10soc.hps_ddr_oct"
    type="conduit"
    dir="end" />
  <interface
-   name="a10gx_base_sys_ddr3_cntrl_oct"
-   internal="a10gx_base.sys_ddr3_cntrl_oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ddr3_cntrl_pll_ref_clk"
-   internal="a10gx_base.sys_ddr3_cntrl_pll_ref_clk"
+   name="hps_ddr_ref_clk"
+   internal="a10soc.hps_ddr_ref_clk"
    type="clock"
    dir="end" />
+ <interface name="hps_gpio" internal="a10soc.hps_gpio" type="conduit" dir="end" />
+ <interface name="hps_io" internal="a10soc.hps_io" type="conduit" dir="end" />
+ <interface name="hps_spi0" internal="a10soc.hps_spi0" type="conduit" dir="end" />
  <interface
-   name="a10gx_base_sys_ethernet_mdio"
-   internal="a10gx_base.sys_ethernet_mdio"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ethernet_ref_clk"
-   internal="a10gx_base.sys_ethernet_ref_clk"
+   name="hps_spi0_sclk"
+   internal="a10soc.hps_spi0_sclk"
    type="clock"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ethernet_reset"
-   internal="a10gx_base.sys_ethernet_reset"
-   type="reset"
    dir="start" />
+ <interface name="hps_spi1" internal="a10soc.hps_spi1" type="conduit" dir="end" />
  <interface
-   name="a10gx_base_sys_ethernet_sgmii"
-   internal="a10gx_base.sys_ethernet_sgmii"
-   type="conduit"
-   dir="end" />
- <interface name="a10gx_base_sys_gpio" internal="a10gx_base.sys_gpio" />
- <interface
-   name="a10gx_base_sys_gpio_bd"
-   internal="a10gx_base.sys_gpio_bd"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_gpio_in"
-   internal="a10gx_base.sys_gpio_in"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_gpio_out"
-   internal="a10gx_base.sys_gpio_out"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_spi"
-   internal="a10gx_base.sys_spi"
-   type="conduit"
-   dir="end" />
- <interface name="daq2_rx_data" internal="daq2.rx_data" type="conduit" dir="end" />
- <interface
-   name="daq2_rx_ref_clk"
-   internal="daq2.rx_ref_clk"
+   name="hps_spi1_sclk"
+   internal="a10soc.hps_spi1_sclk"
    type="clock"
-   dir="end" />
- <interface name="daq2_rx_sync" internal="daq2.rx_sync" type="conduit" dir="end" />
- <interface
-   name="daq2_rx_sysref"
-   internal="daq2.rx_sysref"
-   type="conduit"
-   dir="end" />
- <interface name="daq2_tx_data" internal="daq2.tx_data" type="conduit" dir="end" />
- <interface
-   name="daq2_tx_ref_clk"
-   internal="daq2.tx_ref_clk"
-   type="clock"
-   dir="end" />
- <interface name="daq2_tx_sync" internal="daq2.tx_sync" type="conduit" dir="end" />
- <interface
-   name="daq2_tx_sysref"
-   internal="daq2.tx_sysref"
-   type="conduit"
-   dir="end" />
+   dir="start" />
  <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
  <interface
    name="sys_reset"
    internal="sys_clk.clk_in_reset"
    type="reset"
    dir="end" />
- <module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+ <module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40I2LG" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
+  <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="4" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq2_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq2_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq2_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq2_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq2_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_RESET_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="4" />
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
+  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
  </module>
- <module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+ <module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram0_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
   <parameter
-     name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 29" />
-  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+     name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 32" />
+  <parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
   <parameter
-     name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 29" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+     name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 32" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40I2LG" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133333250" />
-  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="4" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_TX_REF_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_TX_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="4" />
+  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
  </module>
  <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
@@ -520,8 +502,8 @@
  <connection
    kind="avalon"
    version="15.1"
-   start="daq2.axi_ad9144_dma_m_axi"
-   end="a10gx_base.sys_mem_s_avl">
+   start="fmcomms2.axi_dmac_adc_m_dest_axi"
+   end="a10soc.hps_s0_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
@@ -529,8 +511,8 @@
  <connection
    kind="avalon"
    version="15.1"
-   start="daq2.axi_ad9680_dma_m_axi"
-   end="a10gx_base.sys_mem_s_avl">
+   start="fmcomms2.axi_dmac_dac_m_src_axi"
+   end="a10soc.hps_s1_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
@@ -538,142 +520,79 @@
  <connection
    kind="avalon"
    version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9144_core_s_axi">
+   start="a10soc.sys_cpu_m_avl"
+   end="fmcomms2.axi_ad9361_s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9144_dma_s_axi">
+   start="a10soc.sys_cpu_m_avl"
+   end="fmcomms2.axi_dmac_adc_s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00038000" />
+  <parameter name="baseAddress" value="0x00014000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9680_core_s_axi">
+   start="a10soc.sys_cpu_m_avl"
+   end="fmcomms2.axi_dmac_dac_s_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00010000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
-   kind="avalon"
+   kind="clock"
    version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9680_dma_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00034000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_jesd_xcvr_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_core_jesd204_rx_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003e400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_core_jesd204_tx_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003e000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_core_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_rx_pll_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003d800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_tx_lane_pll_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003c000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_tx_pll_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003d000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
+   start="fmcomms2.axi_ad9361_l_clk"
+   end="fmcomms2.axi_ad9361_device_clock" />
+ <connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.clk"
-   end="a10gx_base.sys_clk" />
- <connection kind="clock" version="15.1" start="sys_clk.clk" end="daq2.sys_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="a10gx_base.mem_clk"
-   end="daq2.mem_clk" />
+   end="fmcomms2.sys_clk" />
  <connection
    kind="interrupt"
    version="15.1"
-   start="a10gx_base.sys_intr"
-   end="daq2.axi_ad9144_dma_intr">
+   start="a10soc.hps_irq0"
+   end="fmcomms2.axi_dmac_adc_intr">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10soc.hps_irq0"
+   end="fmcomms2.axi_dmac_dac_intr">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
    version="15.1"
-   start="a10gx_base.sys_intr"
-   end="daq2.axi_ad9680_dma_intr">
+   start="a10soc.hps_irq1"
+   end="fmcomms2.axi_dmac_adc_intr">
   <parameter name="irqNumber" value="0" />
  </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10soc.hps_irq1"
+   end="fmcomms2.axi_dmac_dac_intr">
+  <parameter name="irqNumber" value="1" />
+ </connection>
  <connection
    kind="reset"
    version="15.1"
    start="sys_clk.clk_reset"
-   end="a10gx_base.sys_rst" />
+   end="a10soc.sys_rst_in" />
  <connection
    kind="reset"
    version="15.1"
-   start="sys_clk.clk_reset"
-   end="daq2.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="a10gx_base.mem_rst"
-   end="daq2.mem_rst" />
+   start="a10soc.sys_rst"
+   end="fmcomms2.sys_rst" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
diff --git a/projects/fmcomms2/common/fmcomms2_bd.qsys b/projects/fmcomms2/common/fmcomms2_bd.qsys
index ffbb1cae5..4faf07863 100755
--- a/projects/fmcomms2/common/fmcomms2_bd.qsys
+++ b/projects/fmcomms2/common/fmcomms2_bd.qsys
@@ -13,7 +13,7 @@
    {
       datum _sortIndex
       {
-         value = "4";
+         value = "2";
          type = "int";
       }
    }
@@ -21,7 +21,7 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "4";
          type = "int";
       }
       datum sopceditor_expanded
@@ -90,7 +90,7 @@
    {
       datum _sortIndex
       {
-         value = "5";
+         value = "3";
          type = "int";
       }
       datum sopceditor_expanded
@@ -111,7 +111,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "5";
          type = "int";
       }
       datum sopceditor_expanded
@@ -132,7 +132,7 @@
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "7";
          type = "int";
       }
       datum sopceditor_expanded
@@ -153,7 +153,7 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "6";
          type = "int";
       }
       datum sopceditor_expanded
@@ -162,51 +162,6 @@
          type = "boolean";
       }
    }
-   element gpio
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element mem_clk
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element mem_rst
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element spi_ad9361
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element spi_ad9361.spi_control_port
-   {
-      datum baseAddress
-      {
-         value = "32768";
-         type = "String";
-      }
-   }
    element sys_clk
    {
       datum _sortIndex
@@ -226,9 +181,9 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5CSXFC6D6F31C8ES" />
- <parameter name="deviceFamily" value="Cyclone V" />
- <parameter name="deviceSpeedGrade" value="8_H6" />
+ <parameter name="device" value="10AS066N3F40I2LG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
  <parameter name="generateLegacySim" value="false" />
  <parameter name="generationId" value="0" />
@@ -302,29 +257,6 @@
    internal="axi_dmac_dac.s_axi"
    type="axi4lite"
    dir="end" />
- <interface
-   name="gpio_external_connection"
-   internal="gpio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface name="gpio_s1" internal="gpio.s1" type="avalon" dir="end" />
- <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
- <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="spi_ad9361_external"
-   internal="spi_ad9361.external"
-   type="conduit"
-   dir="end" />
- <interface
-   name="spi_ad9361_irq"
-   internal="spi_ad9361.irq"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="spi_ad9361_spi_control_port"
-   internal="spi_ad9361.spi_control_port"
-   type="avalon"
-   dir="end" />
  <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
  <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
  <module
@@ -382,48 +314,6 @@
   <parameter name="CHANNEL_DATA_WIDTH" value="16" />
   <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
- <module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="50000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="5" />
- </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="1" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="50000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="1" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="50000000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
  <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
@@ -461,12 +351,6 @@
    version="15.1"
    start="axi_ad9361.if_l_clk"
    end="ad9361_clk_bridge.in_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="spi_ad9361.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -475,12 +359,12 @@
  <connection
    kind="clock"
    version="15.1"
-   start="mem_clk.out_clk"
+   start="sys_clk.out_clk"
    end="axi_dmac_adc.m_dest_axi_clock" />
  <connection
    kind="clock"
    version="15.1"
-   start="mem_clk.out_clk"
+   start="sys_clk.out_clk"
    end="axi_dmac_dac.m_src_axi_clock" />
  <connection
    kind="clock"
@@ -686,28 +570,13 @@
  <connection
    kind="reset"
    version="15.1"
-   start="mem_rst.out_reset"
-   end="adc_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
+   start="sys_rst.out_reset"
    end="axi_dmac_adc.m_dest_axi_reset" />
  <connection
    kind="reset"
    version="15.1"
-   start="mem_rst.out_reset"
+   start="sys_rst.out_reset"
    end="axi_dmac_dac.m_src_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="spi_ad9361.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="gpio.reset" />
  <connection
    kind="reset"
    version="15.1"

From bfa6fe2a409c0710b1355e7822cb08b91f7477ed Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 25 Apr 2016 11:23:16 -0400
Subject: [PATCH 152/972] a10soc- updates

---
 projects/fmcomms2/a10soc/system_bd.qsys | 101 ------------------------
 1 file changed, 101 deletions(-)

diff --git a/projects/fmcomms2/a10soc/system_bd.qsys b/projects/fmcomms2/a10soc/system_bd.qsys
index 8421219c0..b5ef80675 100755
--- a/projects/fmcomms2/a10soc/system_bd.qsys
+++ b/projects/fmcomms2/a10soc/system_bd.qsys
@@ -9,19 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element a10gx_base.sys_mem_s_avl
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
    element a10soc
    {
       datum _sortIndex
@@ -46,94 +33,6 @@
          type = "String";
       }
    }
-   element daq2.axi_ad9144_core_s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element daq2.axi_ad9144_dma_s_axi
-   {
-      datum baseAddress
-      {
-         value = "229376";
-         type = "String";
-      }
-   }
-   element daq2.axi_ad9680_core_s_axi
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element daq2.axi_ad9680_dma_s_axi
-   {
-      datum baseAddress
-      {
-         value = "212992";
-         type = "String";
-      }
-   }
-   element daq2.axi_jesd_xcvr_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_core_jesd204_rx_s_avl
-   {
-      datum baseAddress
-      {
-         value = "254976";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_core_jesd204_tx_s_avl
-   {
-      datum baseAddress
-      {
-         value = "253952";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_core_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "196608";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_rx_pll_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "251904";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_tx_lane_pll_s_avl
-   {
-      datum baseAddress
-      {
-         value = "245760";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_tx_pll_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "249856";
-         type = "String";
-      }
-   }
    element fmcomms2
    {
       datum _sortIndex

From e790e4c3aeae9e37ffc766df61e4b5c87d4dff08 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 25 Apr 2016 12:56:19 -0400
Subject: [PATCH 153/972] a10soc- complete qsys

---
 .../common/a10soc/a10soc_system_assign.tcl    |  2 +-
 projects/common/a10soc/a10soc_system_bd.qsys  | 32 ++++------------
 projects/fmcomms2/a10soc/system_bd.qsys       | 38 ++++++++-----------
 projects/fmcomms2/common/fmcomms2_bd.qsys     |  2 +-
 4 files changed, 24 insertions(+), 50 deletions(-)

diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
index 913fe193b..fe465eb13 100755
--- a/projects/common/a10soc/a10soc_system_assign.tcl
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -2,7 +2,7 @@
 # device settings
 
 set_global_assignment -name FAMILY "Arria 10"
-set_global_assignment -name DEVICE 10AS066N3F40I2LG
+set_global_assignment -name DEVICE 10AS066N3F40E2SGE2
 
 # clocks and resets
 
diff --git a/projects/common/a10soc/a10soc_system_bd.qsys b/projects/common/a10soc/a10soc_system_bd.qsys
index 7eeb3ca66..e999e15d9 100644
--- a/projects/common/a10soc/a10soc_system_bd.qsys
+++ b/projects/common/a10soc/a10soc_system_bd.qsys
@@ -276,7 +276,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40I2LG" />
+ <parameter name="device" value="10AS066N3F40I2SGES" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -329,21 +329,13 @@
    internal="arria10_hps_0.f2h_irq1"
    type="interrupt"
    dir="start" />
- <interface
-   name="hps_s0_axi"
-   internal="arria10_hps_0.f2sdram0_data"
-   type="axi"
-   dir="end" />
+ <interface name="hps_s0_axi" internal="arria10_hps_0.f2sdram0_data" />
  <interface
    name="hps_s1_axi"
    internal="arria10_hps_0.f2sdram1_data"
    type="axi"
    dir="end" />
- <interface
-   name="hps_s2_axi"
-   internal="arria10_hps_0.f2sdram2_data"
-   type="axi"
-   dir="end" />
+ <interface name="hps_s2_axi" internal="arria10_hps_0.f2sdram2_data" />
  <interface
    name="hps_spi0"
    internal="arria10_hps_0.spim0"
@@ -435,9 +427,9 @@
   <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
   <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
   <parameter name="F2H_WARM_RST_Enable" value="false" />
-  <parameter name="F2SDRAM0_ENABLED" value="true" />
+  <parameter name="F2SDRAM0_ENABLED" value="false" />
   <parameter name="F2SDRAM1_ENABLED" value="true" />
-  <parameter name="F2SDRAM2_ENABLED" value="true" />
+  <parameter name="F2SDRAM2_ENABLED" value="false" />
   <parameter name="F2SDRAM_ADDRESS_WIDTH" value="32" />
   <parameter name="F2SDRAM_PORT_CONFIG" value="5" />
   <parameter name="F2SDRAM_READY_LATENCY" value="false" />
@@ -586,7 +578,7 @@
   <parameter name="USB1_Mode" value="N/A" />
   <parameter name="USB1_PinMuxing" value="Unused" />
   <parameter name="USE_DEFAULT_MPU_CLK" value="false" />
-  <parameter name="device_name" value="10AS066N3F40I2LG" />
+  <parameter name="device_name" value="10AS066N3F40I2SGES" />
   <parameter name="eosc1_clk_mhz" value="25.0" />
   <parameter name="quartus_ini_hps_ip_boot_from_fpga_ready" value="false" />
   <parameter name="quartus_ini_hps_ip_enable_a10_advanced_options" value="false" />
@@ -1536,7 +1528,7 @@
   <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
   <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
   <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
-  <parameter name="SYS_INFO_DEVICE" value="10AS066N3F40I2LG" />
+  <parameter name="SYS_INFO_DEVICE" value="10AS066N3F40I2SGES" />
   <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_emif_a10_hps_0</parameter>
@@ -1605,21 +1597,11 @@
    start="sys_clk.out_clk"
    end="sys_cpu_interconnect.clk" />
  <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="arria10_hps_0.f2sdram0_clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
    end="arria10_hps_0.f2sdram1_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="arria10_hps_0.f2sdram2_clock" />
  <connection
    kind="clock"
    version="15.1"
diff --git a/projects/fmcomms2/a10soc/system_bd.qsys b/projects/fmcomms2/a10soc/system_bd.qsys
index b5ef80675..907e4c349 100755
--- a/projects/fmcomms2/a10soc/system_bd.qsys
+++ b/projects/fmcomms2/a10soc/system_bd.qsys
@@ -17,14 +17,6 @@
          type = "int";
       }
    }
-   element a10soc.hps_s0_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
    element a10soc.hps_s1_axi
    {
       datum baseAddress
@@ -300,7 +292,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40I2LG" />
+ <parameter name="device" value="10AS066N3F40I2SGES" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -355,27 +347,27 @@
    type="reset"
    dir="end" />
  <module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40I2LG" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40I2SGES" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="4" />
   <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="4" />
   <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
   <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="4" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="4" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
-  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
+  <parameter name="AUTO_UNIQUE_ID" value="system_bd_a10soc" />
  </module>
  <module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_DOMAIN" value="2" />
   <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram0_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_RESET_DOMAIN" value="2" />
+  <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 32" />
@@ -383,14 +375,14 @@
   <parameter
      name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 32" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40I2LG" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40I2SGES" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="4" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="4" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_UNIQUE_ID" value="system_bd_fmcomms2" />
  </module>
  <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
@@ -402,7 +394,7 @@
    kind="avalon"
    version="15.1"
    start="fmcomms2.axi_dmac_adc_m_dest_axi"
-   end="a10soc.hps_s0_axi">
+   end="a10soc.hps_s1_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
diff --git a/projects/fmcomms2/common/fmcomms2_bd.qsys b/projects/fmcomms2/common/fmcomms2_bd.qsys
index 4faf07863..8656a32da 100755
--- a/projects/fmcomms2/common/fmcomms2_bd.qsys
+++ b/projects/fmcomms2/common/fmcomms2_bd.qsys
@@ -181,7 +181,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40I2LG" />
+ <parameter name="device" value="10AS066N3F40E2SGE2" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />

From 664ea16a0f60bbc3c2a15080aa20278d1d3f1d33 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 27 Apr 2016 16:26:11 -0400
Subject: [PATCH 154/972] ccpci- carrier changes

---
 projects/pzsdr/ccpci/system_constr.xdc | 43 ++++++++++++--------------
 projects/pzsdr/ccpci/system_top.v      |  8 -----
 2 files changed, 20 insertions(+), 31 deletions(-)

diff --git a/projects/pzsdr/ccpci/system_constr.xdc b/projects/pzsdr/ccpci/system_constr.xdc
index 0f21e007d..338bd4d3a 100644
--- a/projects/pzsdr/ccpci/system_constr.xdc
+++ b/projects/pzsdr/ccpci/system_constr.xdc
@@ -3,34 +3,31 @@
 
 set_property  -dict {PACKAGE_PIN  AA6}  [get_ports pcie_ref_clk_p]                                      ; ## MGTREFCLK1P_111
 set_property  -dict {PACKAGE_PIN  AA5}  [get_ports pcie_ref_clk_n]                                      ; ## MGTREFCLK1N_111
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports pcie_data_rx_p[0]]                                   ; ## MGTXRXP0_111
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports pcie_data_rx_n[0]]                                   ; ## MGTXRXN0_111
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports pcie_data_rx_p[1]]                                   ; ## MGTXRXP1_111
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports pcie_data_rx_n[1]]                                   ; ## MGTXRXN1_111
-set_property  -dict {PACKAGE_PIN  AC6}  [get_ports pcie_data_rx_p[2]]                                   ; ## MGTXRXP2_111
-set_property  -dict {PACKAGE_PIN  AC5}  [get_ports pcie_data_rx_n[2]]                                   ; ## MGTXRXN2_111
-set_property  -dict {PACKAGE_PIN  AD4}  [get_ports pcie_data_rx_p[3]]                                   ; ## MGTXRXP3_111
-set_property  -dict {PACKAGE_PIN  AD3}  [get_ports pcie_data_rx_n[3]]                                   ; ## MGTXRXN3_111
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports pcie_data_tx_p[0]]                                   ; ## MGTXTXP0_111
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports pcie_data_tx_n[0]]                                   ; ## MGTXTXN0_111
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports pcie_data_tx_p[1]]                                   ; ## MGTXTXP1_111
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports pcie_data_tx_n[1]]                                   ; ## MGTXTXN1_111
-set_property  -dict {PACKAGE_PIN  AE2}  [get_ports pcie_data_tx_p[2]]                                   ; ## MGTXTXP2_111
-set_property  -dict {PACKAGE_PIN  AE1}  [get_ports pcie_data_tx_n[2]]                                   ; ## MGTXTXN2_111
-set_property  -dict {PACKAGE_PIN  AC2}  [get_ports pcie_data_tx_p[3]]                                   ; ## MGTXTXP3_111
-set_property  -dict {PACKAGE_PIN  AC1}  [get_ports pcie_data_tx_n[3]]                                   ; ## MGTXTXN3_111
+set_property  -dict {PACKAGE_PIN  AD4}  [get_ports pcie_data_rx_p[0]]                                   ; ## MGTXRXP3_111
+set_property  -dict {PACKAGE_PIN  AD3}  [get_ports pcie_data_rx_n[0]]                                   ; ## MGTXRXN3_111
+set_property  -dict {PACKAGE_PIN  AC6}  [get_ports pcie_data_rx_p[1]]                                   ; ## MGTXRXP2_111
+set_property  -dict {PACKAGE_PIN  AC5}  [get_ports pcie_data_rx_n[1]]                                   ; ## MGTXRXN2_111
+set_property  -dict {PACKAGE_PIN  AE6}  [get_ports pcie_data_rx_p[2]]                                   ; ## MGTXRXP1_111
+set_property  -dict {PACKAGE_PIN  AE5}  [get_ports pcie_data_rx_n[2]]                                   ; ## MGTXRXN1_111
+set_property  -dict {PACKAGE_PIN  AD8}  [get_ports pcie_data_rx_p[3]]                                   ; ## MGTXRXP0_111
+set_property  -dict {PACKAGE_PIN  AD7}  [get_ports pcie_data_rx_n[3]]                                   ; ## MGTXRXN0_111
+set_property  -dict {PACKAGE_PIN  AC2}  [get_ports pcie_data_tx_p[0]]                                   ; ## MGTXTXP3_111
+set_property  -dict {PACKAGE_PIN  AC1}  [get_ports pcie_data_tx_n[0]]                                   ; ## MGTXTXN3_111
+set_property  -dict {PACKAGE_PIN  AE2}  [get_ports pcie_data_tx_p[1]]                                   ; ## MGTXTXP2_111
+set_property  -dict {PACKAGE_PIN  AE1}  [get_ports pcie_data_tx_n[1]]                                   ; ## MGTXTXN2_111
+set_property  -dict {PACKAGE_PIN  AF4}  [get_ports pcie_data_tx_p[2]]                                   ; ## MGTXTXP1_111
+set_property  -dict {PACKAGE_PIN  AF3}  [get_ports pcie_data_tx_n[2]]                                   ; ## MGTXTXN1_111
+set_property  -dict {PACKAGE_PIN  AF8}  [get_ports pcie_data_tx_p[3]]                                   ; ## MGTXTXP0_111
+set_property  -dict {PACKAGE_PIN  AF7}  [get_ports pcie_data_tx_n[3]]                                   ; ## MGTXTXN0_111
 set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports pcie_rstn]                      ; ## IO_L19P_T3_13      
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD LVCMOS25} [get_ports pcie_prsntn]                    ; ## IO_L19N_T3_VREF_13 
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD LVCMOS25} [get_ports pcie_prsnt1n]                   ; ## IO_L21P_T3_DQS_13  
-set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD LVCMOS25} [get_ports pcie_prsnt4n]                   ; ## IO_L21N_T3_DQS_13  
 set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS25} [get_ports pcie_waken]                     ; ## IO_L20N_T3_13      
 
 set_property PULLUP true [get_ports pcie_rstn]
 set_property LOC IBUFDS_GTE2_X0Y5 [get_cells i_ibufds_pcie_ref_clk]
 create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p]
 
-set_property LOC GTXE2_CHANNEL_X0Y8  [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
-set_property LOC GTXE2_CHANNEL_X0Y9  [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
-set_property LOC GTXE2_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
-set_property LOC GTXE2_CHANNEL_X0Y11 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
+set_property LOC GTXE2_CHANNEL_X0Y8  [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
+set_property LOC GTXE2_CHANNEL_X0Y9  [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
+set_property LOC GTXE2_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
+set_property LOC GTXE2_CHANNEL_X0Y11 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
 
diff --git a/projects/pzsdr/ccpci/system_top.v b/projects/pzsdr/ccpci/system_top.v
index d3ebba2ff..84eaa8f7d 100644
--- a/projects/pzsdr/ccpci/system_top.v
+++ b/projects/pzsdr/ccpci/system_top.v
@@ -97,9 +97,6 @@ module system_top (
   spi_miso,
 
   pcie_rstn,
-  pcie_prsntn,
-  pcie_prsnt1n,
-  pcie_prsnt4n,
   pcie_waken,
   pcie_ref_clk_p,
   pcie_ref_clk_n,
@@ -166,9 +163,6 @@ module system_top (
   input           spi_miso;
 
   input           pcie_rstn;
-  input           pcie_prsntn;
-  output          pcie_prsnt1n;
-  output          pcie_prsnt4n;
   inout           pcie_waken;
   input           pcie_ref_clk_p;
   input           pcie_ref_clk_n;
@@ -187,8 +181,6 @@ module system_top (
   // assignments
 
   assign pcie_waken = 1'bz;
-  assign pcie_prsnt1n = 1'b1;
-  assign pcie_prsnt4n = pcie_prsntn;
 
   // instantiations
 

From 33199263e1c792f07c1efae95004358c1b2fcdb1 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 29 Apr 2016 16:28:48 +0300
Subject: [PATCH 155/972] axi_ad7616: Delete burst_length register

This was an unnecessary feature of the hdl core.
---
 library/axi_ad7616/axi_ad7616.v         |  3 ---
 library/axi_ad7616/axi_ad7616_control.v | 19 +++++--------------
 library/axi_ad7616/axi_ad7616_pif.v     | 16 +---------------
 3 files changed, 6 insertions(+), 32 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 36db38179..8a95b9992 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -178,7 +178,6 @@ module axi_ad7616 (
   wire    [15:0]                    wr_data_s;
   wire    [15:0]                    rd_data_s;
   wire                              rd_valid_s;
-  wire    [ 4:0]                    burst_length_s;
 
   wire                              m_axis_ready_s;
 
@@ -434,7 +433,6 @@ module axi_ad7616 (
       .m_axis_tready(m_axis_ready_s),
       .m_axis_xfer_req(m_axis_xfer_req),
       .end_of_conv(trigger_s),
-      .burst_length(burst_length_s),
       .clk(up_clk),
       .rstn(up_rstn),
       .rd_req(rd_req_s),
@@ -453,7 +451,6 @@ module axi_ad7616 (
   ) i_ad7616_control (
     .cnvst (cnvst),
     .busy (busy),
-    .up_burst_length (burst_length_s),
     .up_read_data (rd_data_s),
     .up_read_valid (rd_valid_s),
     .up_write_data (wr_data_s),
diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index 787f74a8f..50450023e 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -52,7 +52,6 @@ module axi_ad7616_control (
   up_read_req,
   up_write_req,
 
-  up_burst_length,
   end_of_conv,
 
   // bus interface
@@ -83,7 +82,6 @@ module axi_ad7616_control (
   input           busy;
 
   output          end_of_conv;
-  output  [ 4:0]  up_burst_length;
 
   input   [15:0]  up_read_data;
   input           up_read_valid;
@@ -113,7 +111,6 @@ module axi_ad7616_control (
   reg             up_rack = 1'b0;
   reg     [31:0]  up_rdata = 32'b0;
   reg     [31:0]  up_conv_rate = 32'b0;
-  reg     [ 4:0]  up_burst_length = 5'h0;
   reg     [15:0]  up_write_data = 16'h0;
 
   reg     [31:0]  cnvst_counter = 32'b0;
@@ -149,7 +146,6 @@ module axi_ad7616_control (
       up_resetn <= 1'b0;
       up_cnvst_en <= 1'b0;
       up_conv_rate <= 32'b0;
-      up_burst_length <= 5'h0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@@ -162,20 +158,18 @@ module axi_ad7616_control (
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
         up_conv_rate <= up_wdata;
       end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
-        up_burst_length <= up_wdata;
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
         up_write_data <= up_wdata;
       end
     end
   end
 
-  assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0;
+  assign up_write_req = (up_waddr[7:0] == 8'h13) ? up_wreq_s : 1'h0;
 
   // processor read interface
 
-  assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
+  assign up_rack_s = (up_raddr[7:0] == 8'h12) ? up_read_valid_s : up_rreq_s;
+  assign up_read_req = (up_raddr[7:0] == 8'h12) ? up_rreq_s : 1'b0;
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
@@ -190,15 +184,12 @@ module axi_ad7616_control (
           8'h02 : up_rdata = up_scratch;
           8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
           8'h11 : up_rdata = up_conv_rate;
-          8'h12 : up_rdata = {27'b0, up_burst_length};
-          8'h13 : up_rdata = up_read_data_s;
+          8'h12 : up_rdata = up_read_data_s;
         endcase
       end
     end
   end
 
-  assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0;
-
   // instantiations
 
   assign up_rst = ~up_rstn;
diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v
index a3ca9a098..4a114f147 100644
--- a/library/axi_ad7616/axi_ad7616_pif.v
+++ b/library/axi_ad7616/axi_ad7616_pif.v
@@ -60,7 +60,6 @@ module axi_ad7616_pif (
   // end of convertion
 
   end_of_conv,
-  burst_length,
 
   // register access
 
@@ -85,7 +84,6 @@ module axi_ad7616_pif (
   output                          wr_n;
 
   input                           end_of_conv;
-  input   [ 4:0]                  burst_length;
 
   input                           clk;
   input                           rstn;
@@ -115,7 +113,6 @@ module axi_ad7616_pif (
   reg     [ 2:0]                  transfer_state = 3'h0;
   reg     [ 2:0]                  transfer_state_next = 3'h0;
   reg     [ 1:0]                  width_counter = 2'h0;
-  reg     [ 4:0]                  burst_counter = 5'h0;
 
   reg                             wr_req_d = 1'h0;
   reg                             rd_req_d = 1'h0;
@@ -159,17 +156,6 @@ module axi_ad7616_pif (
     end
   end
 
-  always @(posedge clk) begin
-    if (rstn == 1'b0) begin
-      burst_counter <= 2'h0;
-    end else begin
-      if((transfer_state == CS_HIGH) && (rd_conv_d == 1'b1))
-        burst_counter <= burst_counter + 1;
-      else if (transfer_state == IDLE)
-        burst_counter <= 5'h0;
-    end
-  end
-
   always @(negedge clk) begin
     if (transfer_state == IDLE) begin
       wr_req_d <= wr_req;
@@ -202,7 +188,7 @@ module axi_ad7616_pif (
         transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
       end
       CS_HIGH : begin
-        transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW;
+        transfer_state_next <= IDLE;
       end
       default : begin
         transfer_state_next <= IDLE;

From 427f85959c466d4e36dc73094e76d334f6f161f3 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 29 Apr 2016 16:34:34 +0300
Subject: [PATCH 156/972] axi_ad7616: Fix the AXI stream interface

---
 library/axi_ad7616/axi_ad7616_pif.v | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v
index 4a114f147..ea04d5ad4 100644
--- a/library/axi_ad7616/axi_ad7616_pif.v
+++ b/library/axi_ad7616/axi_ad7616_pif.v
@@ -214,8 +214,8 @@ module axi_ad7616_pif (
   assign db_o = wr_data;
 
   always @(posedge clk) begin
-    data_out_a <= (rd_db_valid) ? db_i : data_out_a;
-    data_out_b <= (rd_db_valid) ? data_out_a : data_out_b;
+    data_out_a <= (transfer_state == CNTRL0_HIGH) ? db_i : data_out_a;
+    data_out_b <= (transfer_state == CNTRL1_HIGH) ? db_i : data_out_b;
     rd_valid <= rd_db_valid;
   end
 
@@ -231,12 +231,13 @@ module axi_ad7616_pif (
   // The first valid data is ALWAYS the first sample of a convertion
 
   always @(negedge clk) begin
-    if (end_of_conv == 1'b1)
+    if (end_of_conv == 1'b1) begin
       xfer_req_d <= m_axis_xfer_req;
+    end
   end
 
-  assign m_axis_tdata = rd_data;
-  assign m_axis_tvalid = xfer_req_d & rd_db_valid & rd_db_valid_div2;
+  assign m_axis_tdata = {data_out_b, data_out_a};
+  assign m_axis_tvalid = xfer_req_d & rd_valid & rd_db_valid_div2;
 
 endmodule
 

From 7ec4c00f9f89e237a6f6c9b8296099f58bdbb653 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 29 Apr 2016 16:36:33 +0300
Subject: [PATCH 157/972] axi_ad7616: DMA is always ready

---
 library/axi_ad7616/axi_ad7616.v     | 1 -
 library/axi_ad7616/axi_ad7616_pif.v | 2 --
 2 files changed, 3 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 8a95b9992..3d82ae8cc 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -430,7 +430,6 @@ module axi_ad7616 (
       .wr_n(wr_n),
       .m_axis_tdata(m_axis_tdata),
       .m_axis_tvalid(m_axis_tvalid),
-      .m_axis_tready(m_axis_ready_s),
       .m_axis_xfer_req(m_axis_xfer_req),
       .end_of_conv(trigger_s),
       .clk(up_clk),
diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v
index ea04d5ad4..a983406ce 100644
--- a/library/axi_ad7616/axi_ad7616_pif.v
+++ b/library/axi_ad7616/axi_ad7616_pif.v
@@ -54,7 +54,6 @@ module axi_ad7616_pif (
 
   m_axis_tdata,
   m_axis_tvalid,
-  m_axis_tready,
   m_axis_xfer_req,
 
   // end of convertion
@@ -94,7 +93,6 @@ module axi_ad7616_pif (
   output                          rd_valid;
 
   output  [31:0]                  m_axis_tdata;
-  input                           m_axis_tready;
   output                          m_axis_tvalid;
   input                           m_axis_xfer_req;
 

From 160d54f311561c6b20663c5524f5404e94cbcccd Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 29 Apr 2016 16:41:35 +0300
Subject: [PATCH 158/972] ad7616_sdz: Some comment rephrase

---
 projects/ad7616_sdz/zc706/system_project.tcl | 5 ++---
 projects/ad7616_sdz/zed/system_project.tcl   | 5 ++---
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl
index f94873678..d36937e08 100644
--- a/projects/ad7616_sdz/zc706/system_project.tcl
+++ b/projects/ad7616_sdz/zc706/system_project.tcl
@@ -11,9 +11,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 # LEGEND: Serial    - 0
 #         Parallel  - 1
 #
-# NOTE : These switches are 'hardware' switches. User needs to
-# reimplement the design each and every time, after these variables
-# were changed.
+# NOTE : This switch is a 'hardware' switch. Please reimplenent the
+# design if the variable has been changed.
 #
 ##--------------------------------------------------------------
 
diff --git a/projects/ad7616_sdz/zed/system_project.tcl b/projects/ad7616_sdz/zed/system_project.tcl
index 1641f5ff2..f46ea4c76 100644
--- a/projects/ad7616_sdz/zed/system_project.tcl
+++ b/projects/ad7616_sdz/zed/system_project.tcl
@@ -11,9 +11,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 # LEGEND: Serial    - 0
 #         Parallel  - 1
 #
-# NOTE : These switches are 'hardware' switches. User needs to
-# reimplement the design each and every time, after these variables
-# were changed.
+# NOTE : This switch is a 'hardware' switch. Please reimplenent the
+# design if the variable has been changed.
 #
 ##--------------------------------------------------------------
 

From 779d01475093dc086e62a8bb2c783033c5c20fb7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 27 Apr 2016 16:41:08 -0400
Subject: [PATCH 159/972] ad9361-common alt/xil interface

---
 library/axi_ad9361/axi_ad9361_lvds_if.v | 618 ++++++++++++++++++++++++
 1 file changed, 618 insertions(+)
 create mode 100644 library/axi_ad9361/axi_ad9361_lvds_if.v

diff --git a/library/axi_ad9361/axi_ad9361_lvds_if.v b/library/axi_ad9361/axi_ad9361_lvds_if.v
new file mode 100644
index 000000000..d598d704e
--- /dev/null
+++ b/library/axi_ad9361/axi_ad9361_lvds_if.v
@@ -0,0 +1,618 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9361_dev_if (
+
+  // physical interface (receive)
+
+  rx_clk_in_p,
+  rx_clk_in_n,
+  rx_frame_in_p,
+  rx_frame_in_n,
+  rx_data_in_p,
+  rx_data_in_n,
+
+  // physical interface (transmit)
+
+  tx_clk_out_p,
+  tx_clk_out_n,
+  tx_frame_out_p,
+  tx_frame_out_n,
+  tx_data_out_p,
+  tx_data_out_n,
+
+  // ensm control
+
+  enable,
+  txnrx,
+
+  // clock (common to both receive and transmit)
+
+  rst,
+  clk,
+  l_clk,
+
+  // receive data path interface
+
+  adc_valid,
+  adc_data,
+  adc_status,
+  adc_r1_mode,
+  adc_ddr_edgesel,
+
+  // transmit data path interface
+
+  dac_valid,
+  dac_data,
+  dac_r1_mode,
+
+  // tdd interface
+
+  tdd_enable,
+  tdd_txnrx,
+  tdd_mode,
+
+  // delay interface
+
+  up_clk,
+  up_enable,
+  up_txnrx,
+  up_adc_dld,
+  up_adc_dwdata,
+  up_adc_drdata,
+  up_dac_dld,
+  up_dac_dwdata,
+  up_dac_drdata,
+  delay_clk,
+  delay_rst,
+  delay_locked);
+
+  // this parameter controls the buffer type based on the target device.
+
+  parameter   DEVICE_TYPE = 0;
+  parameter   DAC_IODELAY_ENABLE = 0;
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group";
+
+  // physical interface (receive)
+
+  input           rx_clk_in_p;
+  input           rx_clk_in_n;
+  input           rx_frame_in_p;
+  input           rx_frame_in_n;
+  input   [ 5:0]  rx_data_in_p;
+  input   [ 5:0]  rx_data_in_n;
+
+  // physical interface (transmit)
+
+  output          tx_clk_out_p;
+  output          tx_clk_out_n;
+  output          tx_frame_out_p;
+  output          tx_frame_out_n;
+  output  [ 5:0]  tx_data_out_p;
+  output  [ 5:0]  tx_data_out_n;
+
+  // ensm control
+
+  output          enable;
+  output          txnrx;
+
+  // clock (common to both receive and transmit)
+
+  input           rst;
+  input           clk;
+  output          l_clk;
+
+  // receive data path interface
+
+  output          adc_valid;
+  output  [47:0]  adc_data;
+  output          adc_status;
+  input           adc_r1_mode;
+  input           adc_ddr_edgesel;
+
+  // transmit data path interface
+
+  input           dac_valid;
+  input   [47:0]  dac_data;
+  input           dac_r1_mode;
+
+  // tdd interface
+
+  input           tdd_enable;
+  input           tdd_txnrx;
+  input           tdd_mode;
+
+  // delay interface
+
+  input           up_clk;
+  input           up_enable;
+  input           up_txnrx;
+  input   [ 6:0]  up_adc_dld;
+  input   [34:0]  up_adc_dwdata;
+  output  [34:0]  up_adc_drdata;
+  input   [ 9:0]  up_dac_dld;
+  input   [49:0]  up_dac_dwdata;
+  output  [49:0]  up_dac_drdata;
+  input           delay_clk;
+  input           delay_rst;
+  output          delay_locked;
+
+  // internal registers
+
+  reg     [ 5:0]  rx_data_p = 0;
+  reg             rx_frame_p = 0;
+  reg     [ 1:0]  rx_ccnt = 0;
+  reg             rx_calign = 0;
+  reg             rx_align = 0;
+  reg     [11:0]  rx_data = 'd0;
+  reg     [ 1:0]  rx_frame = 'd0;
+  reg     [11:0]  rx_data_d = 'd0;
+  reg     [ 1:0]  rx_frame_d = 'd0;
+  reg             rx_error_r1 = 'd0;
+  reg             rx_valid_r1 = 'd0;
+  reg     [23:0]  rx_data_r1 = 'd0;
+  reg             rx_error_r2 = 'd0;
+  reg             rx_valid_r2 = 'd0;
+  reg     [47:0]  rx_data_r2 = 'd0;
+  reg             adc_p_valid = 'd0;
+  reg     [47:0]  adc_p_data = 'd0;
+  reg             adc_p_status = 'd0;
+  reg             adc_n_valid = 'd0;
+  reg     [47:0]  adc_n_data = 'd0;
+  reg             adc_n_status = 'd0;
+  reg             adc_valid_int = 'd0;
+  reg     [47:0]  adc_data_int = 'd0;
+  reg             adc_status_int = 'd0;
+  reg             adc_valid = 'd0;
+  reg     [47:0]  adc_data = 'd0;
+  reg             adc_status = 'd0;
+  reg     [ 2:0]  tx_data_cnt = 'd0;
+  reg     [47:0]  tx_data = 'd0;
+  reg             tx_frame = 'd0;
+  reg     [ 5:0]  tx_data_p = 'd0;
+  reg     [ 5:0]  tx_data_n = 'd0;
+  reg             tx_n_frame = 'd0;
+  reg     [ 5:0]  tx_n_data_p = 'd0;
+  reg     [ 5:0]  tx_n_data_n = 'd0;
+  reg             tx_p_frame = 'd0;
+  reg     [ 5:0]  tx_p_data_p = 'd0;
+  reg     [ 5:0]  tx_p_data_n = 'd0;
+  reg             up_enable_int = 'd0;
+  reg             up_txnrx_int = 'd0;
+  reg             enable_up_m1 = 'd0;
+  reg             txnrx_up_m1 = 'd0;
+  reg             enable_up = 'd0;
+  reg             txnrx_up = 'd0;
+  reg             enable_int = 'd0;
+  reg             txnrx_int = 'd0;
+  reg             enable_n_int = 'd0;
+  reg             txnrx_n_int = 'd0;
+  reg             enable_p_int = 'd0;
+  reg             txnrx_p_int = 'd0;
+
+  // internal signals
+
+  wire            rx_align_s;
+  wire    [ 3:0]  rx_frame_s;
+  wire    [ 3:0]  tx_data_sel_s;
+  wire    [ 5:0]  rx_data_p_s;
+  wire    [ 5:0]  rx_data_n_s;
+  wire            rx_frame_p_s;
+  wire            rx_frame_n_s;
+
+  genvar          l_inst;
+
+  // receive data path interface
+
+  assign rx_align_s = rx_frame_n_s ^ rx_frame_p_s;
+
+  always @(posedge l_clk) begin
+    rx_data_p <= rx_data_p_s;
+    rx_frame_p <= rx_frame_p_s;
+    rx_ccnt <= rx_ccnt + 1'b1;
+    if (rx_ccnt == 2'd0) begin
+      rx_calign <= rx_align;
+      rx_align <= rx_align_s;
+    end else begin
+      rx_calign <= rx_calign;
+      rx_align <= rx_align | rx_align_s;
+    end
+  end
+
+  assign rx_frame_s = {rx_frame_d, rx_frame};
+
+  always @(posedge l_clk) begin
+    if (rx_calign == 1'b1) begin
+      rx_data <= {rx_data_p, rx_data_n_s};
+      rx_frame <= {rx_frame_p, rx_frame_n_s};
+    end else begin
+      rx_data <= {rx_data_n_s, rx_data_p_s};
+      rx_frame <= {rx_frame_n_s, rx_frame_p_s};
+    end
+    rx_data_d <= rx_data;
+    rx_frame_d <= rx_frame;
+  end
+
+  // receive data path for single rf, frame is expected to qualify i/q msb only
+
+  always @(posedge l_clk) begin
+    rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
+    rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0;
+    if (rx_frame_s == 4'b1100) begin
+      rx_data_r1[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};
+      rx_data_r1[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
+    end
+  end
+
+  // receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only
+
+  always @(posedge l_clk) begin
+    rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
+      (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
+    rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0;
+    if (rx_frame_s == 4'b1111) begin
+      rx_data_r2[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};
+      rx_data_r2[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
+    end
+    if (rx_frame_s == 4'b0000) begin
+      rx_data_r2[35:24] <= {rx_data_d[11:6], rx_data[11:6]};
+      rx_data_r2[47:36] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
+    end
+  end
+
+  // receive data path mux
+
+  always @(posedge l_clk) begin
+    if (adc_r1_mode == 1'b1) begin
+      adc_p_valid <= rx_valid_r1;
+      adc_p_data <= {24'd0, rx_data_r1};
+      adc_p_status <= ~rx_error_r1;
+    end else begin
+      adc_p_valid <= rx_valid_r2;
+      adc_p_data <= rx_data_r2;
+      adc_p_status <= ~rx_error_r2;
+    end
+  end
+
+  // transfer to a synchronous common clock
+
+  always @(negedge l_clk) begin
+    adc_n_valid <= adc_p_valid;
+    adc_n_data <= adc_p_data;
+    adc_n_status <= adc_p_status;
+  end
+
+  always @(posedge clk) begin
+    adc_valid_int <= adc_n_valid;
+    adc_data_int <= adc_n_data;
+    adc_status_int <= adc_n_status;
+    adc_valid <= adc_valid_int;
+    if (adc_valid_int == 1'b1) begin
+      adc_data <= adc_data_int;
+    end
+    adc_status <= adc_status_int;
+  end
+
+  // transmit data path mux (reverse of what receive does above)
+  // the count simply selets the data muxing on the ddr outputs
+
+  assign tx_data_sel_s = {tx_data_cnt[2], dac_r1_mode, tx_data_cnt[1:0]};
+
+  always @(posedge clk) begin
+    if (dac_valid == 1'b1) begin
+      tx_data_cnt <= 3'b100;
+    end else if (tx_data_cnt[2] == 1'b1) begin
+      tx_data_cnt <= tx_data_cnt + 1'b1;
+    end
+    if (dac_valid == 1'b1) begin
+      tx_data <= dac_data;
+    end
+    case (tx_data_sel_s)
+      4'b1111: begin
+        tx_frame <= 1'b0;
+        tx_data_p <= tx_data[ 5: 0];
+        tx_data_n <= tx_data[17:12];
+      end
+      4'b1110: begin
+        tx_frame <= 1'b1;
+        tx_data_p <= tx_data[11: 6];
+        tx_data_n <= tx_data[23:18];
+      end
+      4'b1101: begin
+        tx_frame <= 1'b0;
+        tx_data_p <= tx_data[ 5: 0];
+        tx_data_n <= tx_data[17:12];
+      end
+      4'b1100: begin
+        tx_frame <= 1'b1;
+        tx_data_p <= tx_data[11: 6];
+        tx_data_n <= tx_data[23:18];
+      end
+      4'b1011: begin
+        tx_frame <= 1'b0;
+        tx_data_p <= tx_data[29:24];
+        tx_data_n <= tx_data[41:36];
+      end
+      4'b1010: begin
+        tx_frame <= 1'b0;
+        tx_data_p <= tx_data[35:30];
+        tx_data_n <= tx_data[47:42];
+      end
+      4'b1001: begin
+        tx_frame <= 1'b1;
+        tx_data_p <= tx_data[ 5: 0];
+        tx_data_n <= tx_data[17:12];
+      end
+      4'b1000: begin
+        tx_frame <= 1'b1;
+        tx_data_p <= tx_data[11: 6];
+        tx_data_n <= tx_data[23:18];
+      end
+      default: begin
+        tx_frame <= 1'b0;
+        tx_data_p <= 6'd0;
+        tx_data_n <= 6'd0;
+      end
+    endcase
+  end
+
+  // transfer data from a synchronous clock (skew less than 2ns)
+
+  always @(negedge clk) begin
+    tx_n_frame <= tx_frame;
+    tx_n_data_p <= tx_data_p;
+    tx_n_data_n <= tx_data_n;
+  end
+
+  always @(posedge l_clk) begin
+    tx_p_frame <= tx_n_frame;
+    tx_p_data_p <= tx_n_data_p;
+    tx_p_data_n <= tx_n_data_n;
+  end
+
+  // tdd/ensm control
+
+  always @(posedge up_clk) begin
+    up_enable_int <= up_enable;
+    up_txnrx_int <= up_txnrx;
+  end
+
+  always @(posedge clk or posedge rst) begin
+    if (rst == 1'b1) begin
+      enable_up_m1 <= 1'b0;
+      txnrx_up_m1 <= 1'b0;
+      enable_up <= 1'b0;
+      txnrx_up <= 1'b0;
+    end else begin
+      enable_up_m1 <= up_enable_int;
+      txnrx_up_m1 <= up_txnrx_int;
+      enable_up <= enable_up_m1;
+      txnrx_up <= txnrx_up_m1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (tdd_mode == 1'b1) begin
+      enable_int <= tdd_enable;
+      txnrx_int <= tdd_txnrx;
+    end else begin
+      enable_int <= enable_up;
+      txnrx_int <= txnrx_up;
+    end
+  end
+
+  always @(negedge clk) begin
+    enable_n_int <= enable_int;
+    txnrx_n_int <= txnrx_int;
+  end
+
+  always @(posedge l_clk) begin
+    enable_p_int <= enable_n_int;
+    txnrx_p_int <= txnrx_n_int;
+  end
+
+  // receive data interface, ibuf -> idelay -> iddr
+
+  generate
+  for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data
+  ad_lvds_in #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_rx_data (
+    .rx_clk (l_clk),
+    .rx_data_in_p (rx_data_in_p[l_inst]),
+    .rx_data_in_n (rx_data_in_n[l_inst]),
+    .rx_data_p (rx_data_p_s[l_inst]),
+    .rx_data_n (rx_data_n_s[l_inst]),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[l_inst]),
+    .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+  end
+  endgenerate
+
+  // receive frame interface, ibuf -> idelay -> iddr
+
+  ad_lvds_in #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .IODELAY_CTRL (1),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_rx_frame (
+    .rx_clk (l_clk),
+    .rx_data_in_p (rx_frame_in_p),
+    .rx_data_in_n (rx_frame_in_n),
+    .rx_data_p (rx_frame_p_s),
+    .rx_data_n (rx_frame_n_s),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[6]),
+    .up_dwdata (up_adc_dwdata[34:30]),
+    .up_drdata (up_adc_drdata[34:30]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked));
+
+  // transmit data interface, oddr -> obuf
+
+  generate
+  for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
+  ad_lvds_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (0),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_data (
+    .tx_clk (l_clk),
+    .tx_data_p (tx_p_data_p[l_inst]),
+    .tx_data_n (tx_p_data_n[l_inst]),
+    .tx_data_out_p (tx_data_out_p[l_inst]),
+    .tx_data_out_n (tx_data_out_n[l_inst]),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[l_inst]),
+    .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+  end
+  endgenerate
+
+  // transmit frame interface, oddr -> obuf
+
+  ad_lvds_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (0),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_frame (
+    .tx_clk (l_clk),
+    .tx_data_p (tx_p_frame),
+    .tx_data_n (tx_p_frame),
+    .tx_data_out_p (tx_frame_out_p),
+    .tx_data_out_n (tx_frame_out_n),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[6]),
+    .up_dwdata (up_dac_dwdata[34:30]),
+    .up_drdata (up_dac_drdata[34:30]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // transmit clock interface, oddr -> obuf
+
+  ad_lvds_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (0),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_clk (
+    .tx_clk (l_clk),
+    .tx_data_p (1'b0),
+    .tx_data_n (1'b1),
+    .tx_data_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_clk_out_n),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[7]),
+    .up_dwdata (up_dac_dwdata[39:35]),
+    .up_drdata (up_dac_drdata[39:35]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // enable, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_enable (
+    .tx_clk (l_clk),
+    .tx_data_p (enable_p_int),
+    .tx_data_n (enable_p_int),
+    .tx_data_out (enable),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[8]),
+    .up_dwdata (up_dac_dwdata[44:40]),
+    .up_drdata (up_dac_drdata[44:40]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // txnrx, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_txnrx (
+    .tx_clk (l_clk),
+    .tx_data_p (txnrx_p_int),
+    .tx_data_n (txnrx_p_int),
+    .tx_data_out (txnrx),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[9]),
+    .up_dwdata (up_dac_dwdata[49:45]),
+    .up_drdata (up_dac_drdata[49:45]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // device clock interface (receive clock)
+
+  ad_lvds_clk #(
+    .DEVICE_TYPE (DEVICE_TYPE))
+  i_clk (
+    .clk_in_p (rx_clk_in_p),
+    .clk_in_n (rx_clk_in_n),
+    .clk (l_clk));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From ed62101308deb226bb84f09f212819f5f268728e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 10:10:07 -0400
Subject: [PATCH 160/972] common/altera: primitives

---
 library/common/altera/ad_cmos_clk.v |  79 +++++++++++
 library/common/altera/ad_cmos_in.v  | 196 ++++++++++++++++++++++++++++
 library/common/altera/ad_cmos_out.v | 164 +++++++++++++++++++++++
 3 files changed, 439 insertions(+)
 create mode 100644 library/common/altera/ad_cmos_clk.v
 create mode 100644 library/common/altera/ad_cmos_in.v
 create mode 100644 library/common/altera/ad_cmos_out.v

diff --git a/library/common/altera/ad_cmos_clk.v b/library/common/altera/ad_cmos_clk.v
new file mode 100644
index 000000000..f5a344f65
--- /dev/null
+++ b/library/common/altera/ad_cmos_clk.v
@@ -0,0 +1,79 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_cmos_clk (
+
+  clk_in,
+  clk);
+
+  parameter   DEVICE_TYPE   = 0;
+  localparam  SERIES7       = 0;
+  localparam  VIRTEX6       = 1;
+
+  input     clk_in;
+  output    clk;
+
+  // wires
+
+  wire      clk_ibuf_s;
+
+  // instantiations
+
+  IBUFG i_rx_clk_ibuf (
+    .I (clk_in),
+    .O (clk_ibuf_s));
+
+  generate
+  if (DEVICE_TYPE == VIRTEX6) begin
+  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
+    .CLR (1'b0),
+    .CE (1'b1),
+    .I (clk_ibuf_s),
+    .O (clk));
+  end else begin
+  BUFG i_clk_gbuf (
+    .I (clk_ibuf_s),
+    .O (clk));
+  end
+  endgenerate
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/common/altera/ad_cmos_in.v b/library/common/altera/ad_cmos_in.v
new file mode 100644
index 000000000..cf2081778
--- /dev/null
+++ b/library/common/altera/ad_cmos_in.v
@@ -0,0 +1,196 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_cmos_in (
+
+  // data interface
+
+  rx_clk,
+  rx_data_in,
+  rx_data_p,
+  rx_data_n,
+
+  // delay-data interface
+
+  up_clk,
+  up_dld,
+  up_dwdata,
+  up_drdata,
+
+  // delay-cntrl interface
+
+  delay_clk,
+  delay_rst,
+  delay_locked);
+
+  // parameters
+
+  parameter   SINGLE_ENDED = 0;
+  parameter   DEVICE_TYPE = 0;
+  parameter   IODELAY_CTRL = 0;
+  parameter   IODELAY_GROUP = "dev_if_delay_group";
+  localparam  SERIES7 = 0;
+  localparam  VIRTEX6 = 1;
+
+  // data interface
+
+  input               rx_clk;
+  input               rx_data_in;
+  output              rx_data_p;
+  output              rx_data_n;
+
+  // delay-data interface
+
+  input               up_clk;
+  input               up_dld;
+  input       [ 4:0]  up_dwdata;
+  output      [ 4:0]  up_drdata;
+
+  // delay-cntrl interface
+
+  input               delay_clk;
+  input               delay_rst;
+  output              delay_locked;
+
+  // internal registers
+
+  reg                 rx_data_n;
+
+  // internal signals
+
+  wire                rx_data_n_s;
+  wire                rx_data_ibuf_s;
+  wire                rx_data_idelay_s;
+
+  // delay controller
+
+  generate
+  if (IODELAY_CTRL == 1) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYCTRL i_delay_ctrl (
+    .RST (delay_rst),
+    .REFCLK (delay_clk),
+    .RDY (delay_locked));
+  end else begin
+  assign delay_locked = 1'b1;
+  end
+  endgenerate
+
+  // receive data interface, ibuf -> idelay -> iddr
+
+  IBUF i_rx_data_ibuf (
+    .I (rx_data_in),
+    .O (rx_data_ibuf_s));
+
+  generate
+  if (DEVICE_TYPE == VIRTEX6) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IODELAYE1 #(
+    .CINVCTRL_SEL ("FALSE"),
+    .DELAY_SRC ("I"),
+    .HIGH_PERFORMANCE_MODE ("TRUE"),
+    .IDELAY_TYPE ("VAR_LOADABLE"),
+    .IDELAY_VALUE (0),
+    .ODELAY_TYPE ("FIXED"),
+    .ODELAY_VALUE (0),
+    .REFCLK_FREQUENCY (200.0),
+    .SIGNAL_PATTERN ("DATA"))
+  i_rx_data_idelay (
+    .T (1'b1),
+    .CE (1'b0),
+    .INC (1'b0),
+    .CLKIN (1'b0),
+    .DATAIN (1'b0),
+    .ODATAIN (1'b0),
+    .CINVCTRL (1'b0),
+    .C (up_clk),
+    .IDATAIN (rx_data_ibuf_s),
+    .DATAOUT (rx_data_idelay_s),
+    .RST (up_dld),
+    .CNTVALUEIN (up_dwdata),
+    .CNTVALUEOUT (up_drdata));
+  end else begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYE2 #(
+    .CINVCTRL_SEL ("FALSE"),
+    .DELAY_SRC ("IDATAIN"),
+    .HIGH_PERFORMANCE_MODE ("FALSE"),
+    .IDELAY_TYPE ("VAR_LOAD"),
+    .IDELAY_VALUE (0),
+    .REFCLK_FREQUENCY (200.0),
+    .PIPE_SEL ("FALSE"),
+    .SIGNAL_PATTERN ("DATA"))
+  i_rx_data_idelay (
+    .CE (1'b0),
+    .INC (1'b0),
+    .DATAIN (1'b0),
+    .LDPIPEEN (1'b0),
+    .CINVCTRL (1'b0),
+    .REGRST (1'b0),
+    .C (up_clk),
+    .IDATAIN (rx_data_ibuf_s),
+    .DATAOUT (rx_data_idelay_s),
+    .LD (up_dld),
+    .CNTVALUEIN (up_dwdata),
+    .CNTVALUEOUT (up_drdata));
+  end
+  endgenerate
+
+  IDDR #(
+    .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
+    .INIT_Q1 (1'b0),
+    .INIT_Q2 (1'b0),
+    .SRTYPE ("ASYNC"))
+  i_rx_data_iddr (
+    .CE (1'b1),
+    .R (1'b0),
+    .S (1'b0),
+    .C (rx_clk),
+    .D (rx_data_idelay_s),
+    .Q1 (rx_data_p),
+    .Q2 (rx_data_n_s));
+
+  always @(posedge rx_clk) begin
+    rx_data_n <= rx_data_n_s;
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/common/altera/ad_cmos_out.v b/library/common/altera/ad_cmos_out.v
new file mode 100644
index 000000000..9537d6dd1
--- /dev/null
+++ b/library/common/altera/ad_cmos_out.v
@@ -0,0 +1,164 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_cmos_out (
+
+  // data interface
+
+  tx_clk,
+  tx_data_p,
+  tx_data_n,
+  tx_data_out,
+
+  // delay-data interface
+
+  up_clk,
+  up_dld,
+  up_dwdata,
+  up_drdata,
+
+  // delay-cntrl interface
+
+  delay_clk,
+  delay_rst,
+  delay_locked);
+
+  // parameters
+
+  parameter   DEVICE_TYPE = 0;
+  parameter   SINGLE_ENDED = 0;
+  parameter   IODELAY_ENABLE = 0;
+  parameter   IODELAY_CTRL = 0;
+  parameter   IODELAY_GROUP = "dev_if_delay_group";
+  localparam  SERIES7 = 0;
+  localparam  VIRTEX6 = 1;
+
+  // data interface
+
+  input               tx_clk;
+  input               tx_data_p;
+  input               tx_data_n;
+  output              tx_data_out;
+
+  // delay-data interface
+
+  input               up_clk;
+  input               up_dld;
+  input       [ 4:0]  up_dwdata;
+  output      [ 4:0]  up_drdata;
+
+  // delay-cntrl interface
+
+  input               delay_clk;
+  input               delay_rst;
+  output              delay_locked;
+
+  // internal signals
+
+  wire                tx_data_oddr_s;
+  wire                tx_data_odelay_s;
+
+  // delay controller
+
+  generate
+  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYCTRL i_delay_ctrl (
+    .RST (delay_rst),
+    .REFCLK (delay_clk),
+    .RDY (delay_locked));
+  end else begin
+  assign delay_locked = 1'b1;
+  end
+  endgenerate
+
+  // transmit data interface, oddr -> odelay -> obuf
+
+  ODDR #(
+    .DDR_CLK_EDGE ("SAME_EDGE"),
+    .INIT (1'b0),
+    .SRTYPE ("ASYNC"))
+  i_tx_data_oddr (
+    .CE (1'b1),
+    .R (1'b0),
+    .S (1'b0),
+    .C (tx_clk),
+    .D1 (tx_data_p),
+    .D2 (tx_data_n),
+    .Q (tx_data_oddr_s));
+
+  generate
+  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  ODELAYE2 #(
+    .CINVCTRL_SEL ("FALSE"),
+    .DELAY_SRC ("ODATAIN"),
+    .HIGH_PERFORMANCE_MODE ("FALSE"),
+    .ODELAY_TYPE ("VAR_LOAD"),
+    .ODELAY_VALUE (0),
+    .REFCLK_FREQUENCY (200.0),
+    .PIPE_SEL ("FALSE"),
+    .SIGNAL_PATTERN ("DATA"))
+  i_tx_data_odelay (
+    .CE (1'b0),
+    .CLKIN (1'b0),
+    .INC (1'b0),
+    .LDPIPEEN (1'b0),
+    .CINVCTRL (1'b0),
+    .REGRST (1'b0),
+    .C (up_clk),
+    .ODATAIN (tx_data_oddr_s),
+    .DATAOUT (tx_data_odelay_s),
+    .LD (up_dld),
+    .CNTVALUEIN (up_dwdata),
+    .CNTVALUEOUT (up_drdata));
+  end else begin
+  assign up_drdata = 5'd0;
+  assign tx_data_odelay_s = tx_data_oddr_s;
+  end
+  endgenerate
+
+  OBUF i_tx_data_obuf (
+    .I (tx_data_odelay_s),
+    .O (tx_data_out));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 0260280db18b0dcf599e0295b252431407a6318f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 11:37:46 -0400
Subject: [PATCH 161/972] common/altera- data path

---
 library/common/altera/ad_cmos_in.v  | 106 ++--------------------------
 library/common/altera/ad_cmos_out.v |  75 +++-----------------
 library/common/altera/ad_lvds_in.v  |  52 ++++++--------
 library/common/altera/ad_lvds_out.v |  65 ++++++++++-------
 4 files changed, 76 insertions(+), 222 deletions(-)

diff --git a/library/common/altera/ad_cmos_in.v b/library/common/altera/ad_cmos_in.v
index cf2081778..9737e4021 100644
--- a/library/common/altera/ad_cmos_in.v
+++ b/library/common/altera/ad_cmos_in.v
@@ -65,8 +65,6 @@ module ad_cmos_in (
   parameter   DEVICE_TYPE = 0;
   parameter   IODELAY_CTRL = 0;
   parameter   IODELAY_GROUP = "dev_if_delay_group";
-  localparam  SERIES7 = 0;
-  localparam  VIRTEX6 = 1;
 
   // data interface
 
@@ -88,107 +86,17 @@ module ad_cmos_in (
   input               delay_rst;
   output              delay_locked;
 
-  // internal registers
+  // defaults
 
-  reg                 rx_data_n;
-
-  // internal signals
-
-  wire                rx_data_n_s;
-  wire                rx_data_ibuf_s;
-  wire                rx_data_idelay_s;
-
-  // delay controller
-
-  generate
-  if (IODELAY_CTRL == 1) begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYCTRL i_delay_ctrl (
-    .RST (delay_rst),
-    .REFCLK (delay_clk),
-    .RDY (delay_locked));
-  end else begin
+  assign up_drdata = 5'd0;
   assign delay_locked = 1'b1;
-  end
-  endgenerate
 
-  // receive data interface, ibuf -> idelay -> iddr
+  // instantiations
 
-  IBUF i_rx_data_ibuf (
-    .I (rx_data_in),
-    .O (rx_data_ibuf_s));
-
-  generate
-  if (DEVICE_TYPE == VIRTEX6) begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IODELAYE1 #(
-    .CINVCTRL_SEL ("FALSE"),
-    .DELAY_SRC ("I"),
-    .HIGH_PERFORMANCE_MODE ("TRUE"),
-    .IDELAY_TYPE ("VAR_LOADABLE"),
-    .IDELAY_VALUE (0),
-    .ODELAY_TYPE ("FIXED"),
-    .ODELAY_VALUE (0),
-    .REFCLK_FREQUENCY (200.0),
-    .SIGNAL_PATTERN ("DATA"))
-  i_rx_data_idelay (
-    .T (1'b1),
-    .CE (1'b0),
-    .INC (1'b0),
-    .CLKIN (1'b0),
-    .DATAIN (1'b0),
-    .ODATAIN (1'b0),
-    .CINVCTRL (1'b0),
-    .C (up_clk),
-    .IDATAIN (rx_data_ibuf_s),
-    .DATAOUT (rx_data_idelay_s),
-    .RST (up_dld),
-    .CNTVALUEIN (up_dwdata),
-    .CNTVALUEOUT (up_drdata));
-  end else begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYE2 #(
-    .CINVCTRL_SEL ("FALSE"),
-    .DELAY_SRC ("IDATAIN"),
-    .HIGH_PERFORMANCE_MODE ("FALSE"),
-    .IDELAY_TYPE ("VAR_LOAD"),
-    .IDELAY_VALUE (0),
-    .REFCLK_FREQUENCY (200.0),
-    .PIPE_SEL ("FALSE"),
-    .SIGNAL_PATTERN ("DATA"))
-  i_rx_data_idelay (
-    .CE (1'b0),
-    .INC (1'b0),
-    .DATAIN (1'b0),
-    .LDPIPEEN (1'b0),
-    .CINVCTRL (1'b0),
-    .REGRST (1'b0),
-    .C (up_clk),
-    .IDATAIN (rx_data_ibuf_s),
-    .DATAOUT (rx_data_idelay_s),
-    .LD (up_dld),
-    .CNTVALUEIN (up_dwdata),
-    .CNTVALUEOUT (up_drdata));
-  end
-  endgenerate
-
-  IDDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
-    .INIT_Q1 (1'b0),
-    .INIT_Q2 (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_rx_data_iddr (
-    .CE (1'b1),
-    .R (1'b0),
-    .S (1'b0),
-    .C (rx_clk),
-    .D (rx_data_idelay_s),
-    .Q1 (rx_data_p),
-    .Q2 (rx_data_n_s));
-
-  always @(posedge rx_clk) begin
-    rx_data_n <= rx_data_n_s;
-  end
+  alt_cmos_in i_rx_data_iddr (
+    .ck (rx_clk),
+    .pad_in (rx_data_in),
+    .dout ({rx_data_p, rx_data_n}));
 
 endmodule
 
diff --git a/library/common/altera/ad_cmos_out.v b/library/common/altera/ad_cmos_out.v
index 9537d6dd1..4f877f0bb 100644
--- a/library/common/altera/ad_cmos_out.v
+++ b/library/common/altera/ad_cmos_out.v
@@ -66,8 +66,6 @@ module ad_cmos_out (
   parameter   IODELAY_ENABLE = 0;
   parameter   IODELAY_CTRL = 0;
   parameter   IODELAY_GROUP = "dev_if_delay_group";
-  localparam  SERIES7 = 0;
-  localparam  VIRTEX6 = 1;
 
   // data interface
 
@@ -89,74 +87,17 @@ module ad_cmos_out (
   input               delay_rst;
   output              delay_locked;
 
-  // internal signals
+  // defaults
 
-  wire                tx_data_oddr_s;
-  wire                tx_data_odelay_s;
-
-  // delay controller
-
-  generate
-  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYCTRL i_delay_ctrl (
-    .RST (delay_rst),
-    .REFCLK (delay_clk),
-    .RDY (delay_locked));
-  end else begin
-  assign delay_locked = 1'b1;
-  end
-  endgenerate
-
-  // transmit data interface, oddr -> odelay -> obuf
-
-  ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_tx_data_oddr (
-    .CE (1'b1),
-    .R (1'b0),
-    .S (1'b0),
-    .C (tx_clk),
-    .D1 (tx_data_p),
-    .D2 (tx_data_n),
-    .Q (tx_data_oddr_s));
-
-  generate
-  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  ODELAYE2 #(
-    .CINVCTRL_SEL ("FALSE"),
-    .DELAY_SRC ("ODATAIN"),
-    .HIGH_PERFORMANCE_MODE ("FALSE"),
-    .ODELAY_TYPE ("VAR_LOAD"),
-    .ODELAY_VALUE (0),
-    .REFCLK_FREQUENCY (200.0),
-    .PIPE_SEL ("FALSE"),
-    .SIGNAL_PATTERN ("DATA"))
-  i_tx_data_odelay (
-    .CE (1'b0),
-    .CLKIN (1'b0),
-    .INC (1'b0),
-    .LDPIPEEN (1'b0),
-    .CINVCTRL (1'b0),
-    .REGRST (1'b0),
-    .C (up_clk),
-    .ODATAIN (tx_data_oddr_s),
-    .DATAOUT (tx_data_odelay_s),
-    .LD (up_dld),
-    .CNTVALUEIN (up_dwdata),
-    .CNTVALUEOUT (up_drdata));
-  end else begin
   assign up_drdata = 5'd0;
-  assign tx_data_odelay_s = tx_data_oddr_s;
-  end
-  endgenerate
+  assign delay_locked = 1'b1;
 
-  OBUF i_tx_data_obuf (
-    .I (tx_data_odelay_s),
-    .O (tx_data_out));
+  // instantiations
+
+  alt_cmos_out i_tx_data_oddr (
+    .ck (tx_clk),
+    .din ({tx_data_p, tx_data_n}),
+    .pad_out (tx_data_out));
 
 endmodule
 
diff --git a/library/common/altera/ad_lvds_in.v b/library/common/altera/ad_lvds_in.v
index 7ab54045e..1313e52f8 100644
--- a/library/common/altera/ad_lvds_in.v
+++ b/library/common/altera/ad_lvds_in.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -49,22 +47,25 @@ module ad_lvds_in (
   rx_data_p,
   rx_data_n,
 
-  // delay interface
+  // delay-data interface
+
+  up_clk,
+  up_dld,
+  up_dwdata,
+  up_drdata,
+
+  // delay-cntrl interface
 
   delay_clk,
   delay_rst,
-  delay_ld,
-  delay_wdata,
-  delay_rdata,
   delay_locked);
 
   // parameters
 
+  parameter   SINGLE_ENDED = 0;
   parameter   DEVICE_TYPE = 0;
   parameter   IODELAY_CTRL = 0;
   parameter   IODELAY_GROUP = "dev_if_delay_group";
-  localparam  SERIES7 = 0;
-  localparam  VIRTEX6 = 1;
 
   // data interface
 
@@ -74,38 +75,31 @@ module ad_lvds_in (
   output              rx_data_p;
   output              rx_data_n;
 
-  // delay interface
+  // delay-data interface
+
+  input               up_clk;
+  input               up_dld;
+  input       [ 4:0]  up_dwdata;
+  output      [ 4:0]  up_drdata;
+
+  // delay-cntrl interface
 
   input               delay_clk;
   input               delay_rst;
-  input               delay_ld;
-  input       [ 4:0]  delay_wdata;
-  output      [ 4:0]  delay_rdata;
   output              delay_locked;
 
   // defaults
 
-  assign delay_rdata = 5'd0;
+  assign up_drdata = 5'd0;
   assign delay_locked = 1'b1;
 
   // instantiations
 
-  altddio_in #(
-    .invert_input_clocks("OFF"),
-    .lpm_hint("UNUSED"),
-    .lpm_type("altddio_in"),
-    .power_up_high("OFF"),
-    .width(1))
-  i_rx_data_iddr (
-    .aclr (1'b0),
-    .aset (1'b0),
-    .sclr (1'b0),
-    .sset (1'b0),
-    .inclocken (1'b1),
-    .inclock (rx_clk),
-    .datain (rx_data_in_p),
-    .dataout_h (rx_data_p),
-    .dataout_l (rx_data_n));
+  alt_lvds_in i_rx_data_iddr (
+    .ck (rx_clk),
+    .pad_in (rx_data_in_p),
+    .pad_in_b (rx_data_in_n),
+    .dout ({rx_data_p, rx_data_n}));
 
 endmodule
 
diff --git a/library/common/altera/ad_lvds_out.v b/library/common/altera/ad_lvds_out.v
index edc756114..05e8a87bc 100644
--- a/library/common/altera/ad_lvds_out.v
+++ b/library/common/altera/ad_lvds_out.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -47,13 +45,28 @@ module ad_lvds_out (
   tx_data_p,
   tx_data_n,
   tx_data_out_p,
-  tx_data_out_n);
+  tx_data_out_n,
+
+  // delay-data interface
+
+  up_clk,
+  up_dld,
+  up_dwdata,
+  up_drdata,
+
+  // delay-cntrl interface
+
+  delay_clk,
+  delay_rst,
+  delay_locked);
 
   // parameters
 
   parameter   DEVICE_TYPE = 0;
-  localparam  SERIES7 = 0;
-  localparam  VIRTEX6 = 1;
+  parameter   SINGLE_ENDED = 0;
+  parameter   IODELAY_ENABLE = 0;
+  parameter   IODELAY_CTRL = 0;
+  parameter   IODELAY_GROUP = "dev_if_delay_group";
 
   // data interface
 
@@ -63,33 +76,31 @@ module ad_lvds_out (
   output              tx_data_out_p;
   output              tx_data_out_n;
 
+  // delay-data interface
+
+  input               up_clk;
+  input               up_dld;
+  input       [ 4:0]  up_dwdata;
+  output      [ 4:0]  up_drdata;
+
+  // delay-cntrl interface
+
+  input               delay_clk;
+  input               delay_rst;
+  output              delay_locked;
+
   // defaults
 
-  assign tx_data_out_n = 1'd0;
+  assign up_drdata = 5'd0;
+  assign delay_locked = 1'b1;
 
   // instantiations
 
-  altddio_out #(
-    .extend_oe_disable("OFF"),
-    .intended_device_family("Cyclone V"),
-    .invert_output("OFF"),
-    .lpm_hint("UNUSED"),
-    .lpm_type("altddio_out"),
-    .oe_reg("UNREGISTERED"),
-    .power_up_high("OFF"),
-    .width(1))
-  i_tx_data_oddr (
-    .aclr (1'b0),
-    .aset (1'b0),
-    .sclr (1'b0),
-    .sset (1'b0),
-    .oe (1'b1),
-    .oe_out (),
-    .outclocken (1'b1),
-    .outclock (tx_clk),
-    .datain_h (tx_data_p),
-    .datain_l (tx_data_n),
-    .dataout (tx_data_out_p));
+  alt_lvds_out i_tx_data_oddr (
+    .ck (tx_clk),
+    .din ({tx_data_p, tx_data_n}),
+    .pad_out (tx_data_out_p),
+    .pad_out_b (tx_data_out_n));
 
 endmodule
 

From 3563c2212ca63f2af180ee6dd293690a316d1b5f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 11:38:20 -0400
Subject: [PATCH 162/972] common/altera- removed dcfilt/mul

---
 library/common/altera/ad_dcfilter_alt.v | 106 ----------------------
 library/common/altera/ad_mul_u16_alt.v  | 112 ------------------------
 2 files changed, 218 deletions(-)
 delete mode 100644 library/common/altera/ad_dcfilter_alt.v
 delete mode 100644 library/common/altera/ad_mul_u16_alt.v

diff --git a/library/common/altera/ad_dcfilter_alt.v b/library/common/altera/ad_dcfilter_alt.v
deleted file mode 100644
index 457cbb38d..000000000
--- a/library/common/altera/ad_dcfilter_alt.v
+++ /dev/null
@@ -1,106 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2014(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
-
-`timescale 1ps/1ps
-
-module ad_dcfilter (
-
-  // data interface
-
-  clk,
-  valid,
-  data,
-  valid_out,
-  data_out,
-
-  // control interface
-
-  dcfilt_enb,
-  dcfilt_coeff,
-  dcfilt_offset);
-
-  // data interface
-
-  input           clk;
-  input           valid;
-  input   [15:0]  data;
-  output          valid_out;
-  output  [15:0]  data_out;
-
-  // control interface
-
-  input           dcfilt_enb;
-  input   [15:0]  dcfilt_coeff;
-  input   [15:0]  dcfilt_offset;
-
-  // internal registers
-
-  reg             valid_d = 'd0;
-  reg     [15:0]  data_d = 'd0;
-  reg             valid_2d = 'd0;
-  reg     [15:0]  data_2d = 'd0;
-  reg             valid_out = 'd0;
-  reg     [15:0]  data_out = 'd0;
-
-
-
-  // cancelling the dc offset
-
-  always @(posedge clk) begin
-    dc_offset <= 16'h0;
-    valid_d <= valid;
-    if (valid == 1'b1) begin
-      data_d <= data + dcfilt_offset;
-    end
-    valid_2d <= valid_d;
-    data_2d <= data_d - dc_offset;
-    if (dcfilt_enb == 1'b1) begin
-      valid_out <= valid_2d;
-      data_out <= data_d; // DC filter not implemented in this version
-    end else begin
-      valid_out <= valid_d;
-      data_out <= data_d;
-    end
-  end
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/altera/ad_mul_u16_alt.v b/library/common/altera/ad_mul_u16_alt.v
deleted file mode 100644
index 923944a57..000000000
--- a/library/common/altera/ad_mul_u16_alt.v
+++ /dev/null
@@ -1,112 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2014(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// both inputs are considered unsigned 16 bits-
-// ddata is delay matched generic data
-
-`timescale 1ps/1ps
-
-module ad_mul_u16 (
-
-  // data_p = data_a * data_b;
-
-  clk,
-  data_a,
-  data_b,
-  data_p,
-
-  // delay interface
-
-  ddata_in,
-  ddata_out);
-
-  // delayed data bus width
-
-  parameter   DELAY_DATA_WIDTH = 16;
-  localparam  DW = DELAY_DATA_WIDTH - 1;
-
-  // data_p = data_a * data_b;
-
-  input           clk;
-  input   [15:0]  data_a;
-  input   [15:0]  data_b;
-  output  [31:0]  data_p;
-
-  // delay interface
-
-  input   [DW:0]  ddata_in;
-  output  [DW:0]  ddata_out;
-
-  // internal registers
-
-  reg     [DW:0]  p1_ddata = 'd0;
-  reg     [DW:0]  p2_ddata = 'd0;
-  reg     [DW:0]  ddata_out = 'd0;
-
-  // internal signals
-
-
-  // a/b reg, m-reg, p-reg delay match
-
-  always @(posedge clk) begin
-    p1_ddata <= ddata_in;
-    p2_ddata <= p1_ddata;
-    ddata_out <= p2_ddata;
-  end
-
-  lpm_mult  i_mult_macro (
-        .clock (clk),
-        .dataa (data_a),
-        .datab (data_b),
-        .result (data_p),
-        .aclr (1'b0),
-        .clken (1'b1),
-        .sum (1'b0));
-  defparam
-    lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
-    lpm_mult_component.lpm_pipeline = 3,
-    lpm_mult_component.lpm_representation = "UNSIGNED",
-    lpm_mult_component.lpm_type = "LPM_MULT",
-    lpm_mult_component.lpm_widtha = 16,
-    lpm_mult_component.lpm_widthb = 16,
-    lpm_mult_component.lpm_widthp = 32;
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From f411d29e308245ca9bbfc94a1e3f7578170fb898 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 15:36:44 -0400
Subject: [PATCH 163/972] ad9361- a10soc changes

---
 library/axi_ad9361/axi_ad9361_hw.tcl | 85 ++++++++++++++++++++++------
 library/axi_ad9361/axi_ad9361_ip.tcl |  2 +-
 2 files changed, 70 insertions(+), 17 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 5d22fc708..587edf10f 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -9,17 +9,21 @@ set_module_property DESCRIPTION "AXI AD9361 Interface"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
 set_module_property DISPLAY_NAME axi_ad9361
+set_module_property ELABORATION_CALLBACK p_axi_ad9361
 
 # files
 
-add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
+add_fileset_file MULT_MACRO.v             VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
+add_fileset_file DSP48E1.v                VERILOG PATH $ad_hdl_dir/library/common/altera/DSP48E1.v
 add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_lvds_clk.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_clk.v
 add_fileset_file ad_lvds_in.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_in.v
 add_fileset_file ad_lvds_out.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_out.v
-add_fileset_file MULT_MACRO.v             VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
-add_fileset_file DSP48E1.v                VERILOG PATH $ad_hdl_dir/library/common/altera/DSP48E1.v
+add_fileset_file ad_cmos_clk.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_cmos_clk.v
+add_fileset_file ad_cmos_in.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_cmos_in.v
+add_fileset_file ad_cmos_out.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_cmos_out.v
 add_fileset_file ad_mul.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
 add_fileset_file ad_pnmon.v               VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
 add_fileset_file ad_dds_sine.v            VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
@@ -28,6 +32,8 @@ add_fileset_file ad_dds.v                 VERILOG PATH $ad_hdl_dir/library/commo
 add_fileset_file ad_datafmt.v             VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
 add_fileset_file ad_dcfilter.v            VERILOG PATH $ad_hdl_dir/library/common/ad_dcfilter.v
 add_fileset_file ad_iqcor.v               VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
+add_fileset_file ad_addsub.v              VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v
+add_fileset_file ad_tdd_control.v         VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v
 add_fileset_file up_axi.v                 VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
 add_fileset_file up_xfer_cntrl.v          VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
 add_fileset_file up_xfer_status.v         VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
@@ -38,11 +44,8 @@ add_fileset_file up_adc_channel.v         VERILOG PATH $ad_hdl_dir/library/commo
 add_fileset_file up_dac_common.v          VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
 add_fileset_file up_dac_channel.v         VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
 add_fileset_file up_tdd_cntrl.v           VERILOG PATH $ad_hdl_dir/library/common/up_tdd_cntrl.v
-add_fileset_file ad_tdd_control.v         VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v
-add_fileset_file ad_addsub.v              VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v
-add_fileset_file axi_ad9361_alt_lvds_tx.v VERILOG PATH axi_ad9361_alt_lvds_tx.v
-add_fileset_file axi_ad9361_alt_lvds_rx.v VERILOG PATH axi_ad9361_alt_lvds_rx.v
-add_fileset_file axi_ad9361_dev_if_alt.v  VERILOG PATH axi_ad9361_dev_if_alt.v
+add_fileset_file axi_ad9361_lvds_if.v     VERILOG PATH axi_ad9361_lvds_if.v
+add_fileset_file axi_ad9361_cmos_if.v     VERILOG PATH axi_ad9361_cmos_if.v
 add_fileset_file axi_ad9361_rx_pnmon.v    VERILOG PATH axi_ad9361_rx_pnmon.v
 add_fileset_file axi_ad9361_rx_channel.v  VERILOG PATH axi_ad9361_rx_channel.v
 add_fileset_file axi_ad9361_rx.v          VERILOG PATH axi_ad9361_rx.v
@@ -68,6 +71,12 @@ set_parameter_property DEVICE_TYPE TYPE INTEGER
 set_parameter_property DEVICE_TYPE UNITS None
 set_parameter_property DEVICE_TYPE HDL_PARAMETER true
 
+add_parameter DEVICE_FAMILY STRING 
+set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
+set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
+set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
+set_parameter_property DEVICE_FAMILY ENABLED false
+
 # axi4 slave
 
 add_interface s_axi_clock clock end
@@ -126,26 +135,24 @@ ad_alt_intf signal  dac_sync_out    output  1   sync
 ad_alt_intf clock   l_clk           output  1
 ad_alt_intf reset   rst             output  1   if_l_clk
 
+set_interface_property if_rst associatedResetSinks none
+
 add_interface fifo_ch_0_in conduit end
-#set_interface_property fifo_ch_0_in associatedClock if_l_clk
 add_interface_port fifo_ch_0_in  adc_enable_i0 enable   Output  1
 add_interface_port fifo_ch_0_in  adc_valid_i0  valid    Output  1
 add_interface_port fifo_ch_0_in  adc_data_i0   data     Output  16
 
 add_interface fifo_ch_1_in conduit end
-#set_interface_property fifo_ch_1_in associatedClock if_l_clk
 add_interface_port fifo_ch_1_in  adc_enable_q0 enable   Output  1
 add_interface_port fifo_ch_1_in  adc_valid_q0  valid    Output  1
 add_interface_port fifo_ch_1_in  adc_data_q0   data     Output  16
 
 add_interface fifo_ch_2_in conduit end
-#set_interface_property fifo_ch_2_in associatedClock if_l_clk
 add_interface_port fifo_ch_2_in  adc_enable_i1 enable   Output  1
 add_interface_port fifo_ch_2_in  adc_valid_i1  valid    Output  1
 add_interface_port fifo_ch_2_in  adc_data_i1   data     Output  16
 
 add_interface fifo_ch_3_in conduit end
-#set_interface_property fifo_ch_3_in associatedClock if_l_clk
 add_interface_port fifo_ch_3_in  adc_enable_q1 enable   Output  1
 add_interface_port fifo_ch_3_in  adc_valid_q1  valid    Output  1
 add_interface_port fifo_ch_3_in  adc_data_q1   data     Output  16
@@ -154,25 +161,21 @@ ad_alt_intf signal  adc_dovf        input  1   ovf
 ad_alt_intf signal  adc_dunf        input  1   unf
 
 add_interface fifo_ch_0_out conduit end
-#set_interface_property fifo_ch_0_out associatedClock if_l_clk
 add_interface_port fifo_ch_0_out  dac_enable_i0 enable   Output  1
 add_interface_port fifo_ch_0_out  dac_valid_i0  valid    Output  1
 add_interface_port fifo_ch_0_out  dac_data_i0   data     Input   16
 
 add_interface fifo_ch_1_out conduit end
-#set_interface_property fifo_ch_1_out associatedClock if_l_clk
 add_interface_port fifo_ch_1_out  dac_enable_q0 enable   Output  1
 add_interface_port fifo_ch_1_out  dac_valid_q0  valid    Output  1
 add_interface_port fifo_ch_1_out  dac_data_q0   data     Input   16
 
 add_interface fifo_ch_2_out conduit end
-#set_interface_property fifo_ch_2_out associatedClock if_l_clk
 add_interface_port fifo_ch_2_out  dac_enable_i1 enable   Output  1
 add_interface_port fifo_ch_2_out  dac_valid_i1  valid    Output  1
 add_interface_port fifo_ch_2_out  dac_data_i1   data     Input   16
 
 add_interface fifo_ch_3_out conduit end
-#set_interface_property fifo_ch_3_out associatedClock if_l_clk
 add_interface_port fifo_ch_3_out  dac_enable_q1 enable   Output  1
 add_interface_port fifo_ch_3_out  dac_valid_q1  valid    Output  1
 add_interface_port fifo_ch_3_out  dac_data_q1   data     Input   16
@@ -183,3 +186,53 @@ ad_alt_intf signal  dac_dunf       input   1 unf
 add_interface delay_clock clock end
 add_interface_port delay_clock delay_clk clk Input 1
 
+add_hdl_instance alt_lvds_in altera_gpio
+set_instance_parameter_value alt_lvds_in {PIN_TYPE_GUI} {Input}
+set_instance_parameter_value alt_lvds_in {SIZE} {1}
+set_instance_parameter_value alt_lvds_in {gui_diff_buff} {1}
+set_instance_parameter_value alt_lvds_in {gui_pseudo_diff} {0}
+set_instance_parameter_value alt_lvds_in {gui_io_reg_mode} {DDIO}
+
+add_hdl_instance alt_lvds_out altera_gpio
+set_instance_parameter_value alt_lvds_out {PIN_TYPE_GUI} {Output}
+set_instance_parameter_value alt_lvds_out {SIZE} {1}
+set_instance_parameter_value alt_lvds_out {gui_diff_buff} {1}
+set_instance_parameter_value alt_lvds_out {gui_pseudo_diff} {0}
+set_instance_parameter_value alt_lvds_out {gui_io_reg_mode} {DDIO}
+
+add_hdl_instance alt_cmos_in altera_gpio
+set_instance_parameter_value alt_cmos_in {PIN_TYPE_GUI} {Input}
+set_instance_parameter_value alt_cmos_in {SIZE} {1}
+set_instance_parameter_value alt_cmos_in {gui_diff_buff} {0}
+set_instance_parameter_value alt_cmos_in {gui_pseudo_diff} {0}
+set_instance_parameter_value alt_cmos_in {gui_io_reg_mode} {DDIO}
+
+add_hdl_instance alt_cmos_out altera_gpio
+set_instance_parameter_value alt_cmos_out {PIN_TYPE_GUI} {Output}
+set_instance_parameter_value alt_cmos_out {SIZE} {1}
+set_instance_parameter_value alt_cmos_out {gui_diff_buff} {0}
+set_instance_parameter_value alt_cmos_out {gui_pseudo_diff} {0}
+set_instance_parameter_value alt_cmos_out {gui_io_reg_mode} {DDIO}
+
+proc p_axi_ad9361 {} {
+
+  set ALTERA_DEVICE_TYPE [get_parameter_value DEVICE_TYPE]
+  set ALTERA_DEVICE_FAMILY [get_parameter_value DEVICE_FAMILY]
+
+  if {$ALTERA_DEVICE_TYPE == 1} {
+  }
+
+  if {$ALTERA_DEVICE_TYPE == 0} {
+
+    add_hdl_instance alt_clk altera_iopll
+    set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
+    set_instance_parameter_value alt_clk {gui_use_locked} {1}
+    set_instance_parameter_value alt_clk {gui_operation_mode} {source synchronous}
+    set_instance_parameter_value alt_clk {gui_number_of_clocks} {1}
+    set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
+    set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
+    set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
+    set_instance_parameter_value alt_clk {system_info_device_family} $ALTERA_DEVICE_FAMILY
+  }
+}
+
diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl
index 9a3d0c65c..470b780d3 100755
--- a/library/axi_ad9361/axi_ad9361_ip.tcl
+++ b/library/axi_ad9361/axi_ad9361_ip.tcl
@@ -34,7 +34,7 @@ adi_ip_files axi_ad9361 [list \
   "$ad_hdl_dir/library/common/up_dac_channel.v" \
   "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
   "axi_ad9361_constr.xdc" \
-  "axi_ad9361_dev_if.v" \
+  "axi_ad9361_lvds_if.v" \
   "axi_ad9361_cmos_if.v" \
   "axi_ad9361_rx_pnmon.v" \
   "axi_ad9361_rx_channel.v" \

From aa2aa902bfa88c5d1cb7ae33e38ff1aeea551514 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 15:38:05 -0400
Subject: [PATCH 164/972] ad9361- a10soc updates

---
 library/axi_ad9361/axi_ad9361_alt_lvds_rx.v | 202 -------
 library/axi_ad9361/axi_ad9361_alt_lvds_tx.v | 186 ------
 library/axi_ad9361/axi_ad9361_dev_if.v      | 622 --------------------
 library/axi_ad9361/axi_ad9361_dev_if_alt.v  | 349 -----------
 4 files changed, 1359 deletions(-)
 delete mode 100644 library/axi_ad9361/axi_ad9361_alt_lvds_rx.v
 delete mode 100644 library/axi_ad9361/axi_ad9361_alt_lvds_tx.v
 delete mode 100644 library/axi_ad9361/axi_ad9361_dev_if.v
 delete mode 100644 library/axi_ad9361/axi_ad9361_dev_if_alt.v

diff --git a/library/axi_ad9361/axi_ad9361_alt_lvds_rx.v b/library/axi_ad9361/axi_ad9361_alt_lvds_rx.v
deleted file mode 100644
index 9f48dd55a..000000000
--- a/library/axi_ad9361/axi_ad9361_alt_lvds_rx.v
+++ /dev/null
@@ -1,202 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module axi_ad9361_alt_lvds_rx (
-
-  // physical interface (receive)
-
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-
-  // data interface
-
-  clk,
-  rx_frame,
-  rx_data_0,
-  rx_data_1,
-  rx_data_2,
-  rx_data_3,
-  rx_locked);
-
-  // physical interface (receive)
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-
-  // data interface
-
-  output          clk;
-  output  [ 3:0]  rx_frame;
-  output  [ 5:0]  rx_data_0;
-  output  [ 5:0]  rx_data_1;
-  output  [ 5:0]  rx_data_2;
-  output  [ 5:0]  rx_data_3;
-  output          rx_locked;
-
-  // internal signals
-
-  wire    [27:0]  rx_data_s;
- 
-  // instantiations
-
-  assign rx_frame[3] = rx_data_s[24];
-  assign rx_frame[2] = rx_data_s[25];
-  assign rx_frame[1] = rx_data_s[26];
-  assign rx_frame[0] = rx_data_s[27];
-  assign rx_data_3[5] = rx_data_s[20];
-  assign rx_data_3[4] = rx_data_s[16];
-  assign rx_data_3[3] = rx_data_s[12];
-  assign rx_data_3[2] = rx_data_s[ 8];
-  assign rx_data_3[1] = rx_data_s[ 4];
-  assign rx_data_3[0] = rx_data_s[ 0];
-  assign rx_data_2[5] = rx_data_s[21];
-  assign rx_data_2[4] = rx_data_s[17];
-  assign rx_data_2[3] = rx_data_s[13];
-  assign rx_data_2[2] = rx_data_s[ 9];
-  assign rx_data_2[1] = rx_data_s[ 5];
-  assign rx_data_2[0] = rx_data_s[ 1];
-  assign rx_data_1[5] = rx_data_s[22];
-  assign rx_data_1[4] = rx_data_s[18];
-  assign rx_data_1[3] = rx_data_s[14];
-  assign rx_data_1[2] = rx_data_s[10];
-  assign rx_data_1[1] = rx_data_s[ 6];
-  assign rx_data_1[0] = rx_data_s[ 2];
-  assign rx_data_0[5] = rx_data_s[23];
-  assign rx_data_0[4] = rx_data_s[19];
-  assign rx_data_0[3] = rx_data_s[15];
-  assign rx_data_0[2] = rx_data_s[11];
-  assign rx_data_0[1] = rx_data_s[ 7];
-  assign rx_data_0[0] = rx_data_s[ 3];
-
-  altlvds_rx #(
-    .buffer_implementation ("RAM"),
-    .cds_mode ("UNUSED"),
-    .common_rx_tx_pll ("ON"),
-    .data_align_rollover (4),
-    .data_rate ("500.0 Mbps"),
-    .deserialization_factor (4),
-    .dpa_initial_phase_value (0),
-    .dpll_lock_count (0),
-    .dpll_lock_window (0),
-    .enable_clock_pin_mode ("UNUSED"),
-    .enable_dpa_align_to_rising_edge_only ("OFF"),
-    .enable_dpa_calibration ("ON"),
-    .enable_dpa_fifo ("UNUSED"),
-    .enable_dpa_initial_phase_selection ("OFF"),
-    .enable_dpa_mode ("OFF"),
-    .enable_dpa_pll_calibration ("OFF"),
-    .enable_soft_cdr_mode ("OFF"),
-    .implement_in_les ("OFF"),
-    .inclock_boost (0),
-    .inclock_data_alignment ("EDGE_ALIGNED"),
-    .inclock_period (4000),
-    .inclock_phase_shift (0),
-    .input_data_rate (500),
-    .intended_device_family ("Cyclone V"),
-    .lose_lock_on_one_change ("UNUSED"),
-    .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"),
-    .lpm_type ("altlvds_rx"),
-    .number_of_channels (7),
-    .outclock_resource ("Regional clock"),
-    .pll_operation_mode ("NORMAL"),
-    .pll_self_reset_on_loss_lock ("UNUSED"),
-    .port_rx_channel_data_align ("PORT_UNUSED"),
-    .port_rx_data_align ("PORT_UNUSED"),
-    .refclk_frequency ("250.000000 MHz"),
-    .registered_data_align_input ("UNUSED"),
-    .registered_output ("ON"),
-    .reset_fifo_at_first_lock ("UNUSED"),
-    .rx_align_data_reg ("RISING_EDGE"),
-    .sim_dpa_is_negative_ppm_drift ("OFF"),
-    .sim_dpa_net_ppm_variation (0),
-    .sim_dpa_output_clock_phase_shift (0),
-    .use_coreclock_input ("OFF"),
-    .use_dpll_rawperror ("OFF"),
-    .use_external_pll ("OFF"),
-    .use_no_phase_shift ("ON"),
-    .x_on_bitslip ("ON"),
-    .clk_src_is_pll ("off"))
-  i_altlvds_rx (
-    .rx_inclock (rx_clk_in_p),
-    .rx_in ({rx_frame_in_p, rx_data_in_p}),
-    .rx_outclock (clk),
-    .rx_out (rx_data_s),
-    .rx_locked (rx_locked),
-    .dpa_pll_cal_busy (),
-    .dpa_pll_recal (1'b0),
-    .pll_areset (1'b0),
-    .pll_phasecounterselect (),
-    .pll_phasedone (1'b1),
-    .pll_phasestep (),
-    .pll_phaseupdown (),
-    .pll_scanclk (),
-    .rx_cda_max (),
-    .rx_cda_reset ({7{1'b0}}),
-    .rx_channel_data_align ({7{1'b0}}),
-    .rx_coreclk ({7{1'b1}}),
-    .rx_data_align (1'b0),
-    .rx_data_align_reset (1'b0),
-    .rx_data_reset (1'b0),
-    .rx_deskew (1'b0),
-    .rx_divfwdclk (),
-    .rx_dpa_lock_reset ({7{1'b0}}),
-    .rx_dpa_locked (),
-    .rx_dpaclock (1'b0),
-    .rx_dpll_enable ({7{1'b1}}),
-    .rx_dpll_hold ({7{1'b0}}),
-    .rx_dpll_reset ({7{1'b0}}),
-    .rx_enable (1'b1),
-    .rx_fifo_reset ({7{1'b0}}),
-    .rx_pll_enable (1'b1),
-    .rx_readclock (1'b0),
-    .rx_reset ({7{1'b0}}),
-    .rx_syncclock (1'b0));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/axi_ad9361_alt_lvds_tx.v b/library/axi_ad9361/axi_ad9361_alt_lvds_tx.v
deleted file mode 100644
index 2b96fccb6..000000000
--- a/library/axi_ad9361/axi_ad9361_alt_lvds_tx.v
+++ /dev/null
@@ -1,186 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module axi_ad9361_alt_lvds_tx (
-
-  // physical interface (transmit)
-
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
-
-  // data interface
-
-  tx_clk,
-  clk,
-  tx_frame,
-  tx_data_0,
-  tx_data_1,
-  tx_data_2,
-  tx_data_3,
-  tx_locked);
-
-  // physical interface (transmit)
-
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  // data interface
-
-  input           tx_clk;
-  input           clk;
-  input   [ 3:0]  tx_frame;
-  input   [ 5:0]  tx_data_0;
-  input   [ 5:0]  tx_data_1;
-  input   [ 5:0]  tx_data_2;
-  input   [ 5:0]  tx_data_3;
-  output          tx_locked;
-
-  // internal registers
-
-  reg     [27:0]  tx_data_n = 'd0;
-  reg     [27:0]  tx_data_p = 'd0;
-
-  // internal signals
-
-  wire            core_clk;
-  wire    [27:0]  tx_data_s;
- 
-  // instantiations
-
-  assign tx_clk_out_n = 1'd0;
-  assign tx_frame_out_n = 1'd0;
-  assign tx_data_out_n = 6'd0;
-
-  assign tx_data_s[24] = tx_frame[3];
-  assign tx_data_s[25] = tx_frame[2];
-  assign tx_data_s[26] = tx_frame[1];
-  assign tx_data_s[27] = tx_frame[0];
-  assign tx_data_s[20] = tx_data_3[5];
-  assign tx_data_s[16] = tx_data_3[4];
-  assign tx_data_s[12] = tx_data_3[3];
-  assign tx_data_s[ 8] = tx_data_3[2];
-  assign tx_data_s[ 4] = tx_data_3[1];
-  assign tx_data_s[ 0] = tx_data_3[0];
-  assign tx_data_s[21] = tx_data_2[5];
-  assign tx_data_s[17] = tx_data_2[4];
-  assign tx_data_s[13] = tx_data_2[3];
-  assign tx_data_s[ 9] = tx_data_2[2];
-  assign tx_data_s[ 5] = tx_data_2[1];
-  assign tx_data_s[ 1] = tx_data_2[0];
-  assign tx_data_s[22] = tx_data_1[5];
-  assign tx_data_s[18] = tx_data_1[4];
-  assign tx_data_s[14] = tx_data_1[3];
-  assign tx_data_s[10] = tx_data_1[2];
-  assign tx_data_s[ 6] = tx_data_1[1];
-  assign tx_data_s[ 2] = tx_data_1[0];
-  assign tx_data_s[23] = tx_data_0[5];
-  assign tx_data_s[19] = tx_data_0[4];
-  assign tx_data_s[15] = tx_data_0[3];
-  assign tx_data_s[11] = tx_data_0[2];
-  assign tx_data_s[ 7] = tx_data_0[1];
-  assign tx_data_s[ 3] = tx_data_0[0];
-
-  always @(negedge clk) begin
-    tx_data_n <= tx_data_s;
-  end
-
-  always @(posedge core_clk) begin
-    tx_data_p <= tx_data_n;
-  end
-
-  altlvds_tx #(
-    .center_align_msb ("UNUSED"),
-    .common_rx_tx_pll ("ON"),
-    .coreclock_divide_by (1),
-    .data_rate ("500.0 Mbps"),
-    .deserialization_factor (4),
-    .differential_drive (0),
-    .enable_clock_pin_mode ("UNUSED"),
-    .implement_in_les ("OFF"),
-    .inclock_boost (0),
-    .inclock_data_alignment ("EDGE_ALIGNED"),
-    .inclock_period (4000),
-    .inclock_phase_shift (0),
-    .intended_device_family ("Cyclone V"),
-    .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"),
-    .lpm_type ("altlvds_tx"),
-    .multi_clock ("OFF"),
-    .number_of_channels (7),
-    .outclock_alignment ("EDGE_ALIGNED"),
-    .outclock_divide_by (2),
-    .outclock_duty_cycle (50),
-    .outclock_multiply_by (1),
-    .outclock_phase_shift (0),
-    .outclock_resource ("Regional clock"),
-    .output_data_rate (500),
-    .pll_compensation_mode ("AUTO"),
-    .pll_self_reset_on_loss_lock ("OFF"),
-    .preemphasis_setting (0),
-    .refclk_frequency ("250.000000 MHz"),
-    .registered_input ("TX_CORECLK"),
-    .use_external_pll ("OFF"),
-    .use_no_phase_shift ("ON"),
-    .vod_setting (0),
-    .clk_src_is_pll ("off"))
-  i_altlvds_tx (
-    .tx_inclock (tx_clk),
-    .tx_coreclock (core_clk),
-    .tx_in (tx_data_p),
-    .tx_outclock (tx_clk_out_p),
-    .tx_out ({tx_frame_out_p, tx_data_out_p}),
-    .tx_locked (tx_locked),
-    .pll_areset (1'b0),
-    .sync_inclock (1'b0),
-    .tx_data_reset (1'b0),
-    .tx_enable (1'b1),
-    .tx_pll_enable (1'b1),
-    .tx_syncclock (1'b0));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/axi_ad9361_dev_if.v b/library/axi_ad9361/axi_ad9361_dev_if.v
deleted file mode 100644
index d5b416fc9..000000000
--- a/library/axi_ad9361/axi_ad9361_dev_if.v
+++ /dev/null
@@ -1,622 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// This interface includes both the transmit and receive components -
-// They both uses the same clock (sourced from the receiving side).
-
-`timescale 1ns/100ps
-
-module axi_ad9361_dev_if (
-
-  // physical interface (receive)
-
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-
-  // physical interface (transmit)
-
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
-
-  // ensm control
-
-  enable,
-  txnrx,
-
-  // clock (common to both receive and transmit)
-
-  rst,
-  clk,
-  l_clk,
-
-  // receive data path interface
-
-  adc_valid,
-  adc_data,
-  adc_status,
-  adc_r1_mode,
-  adc_ddr_edgesel,
-
-  // transmit data path interface
-
-  dac_valid,
-  dac_data,
-  dac_r1_mode,
-
-  // tdd interface
-
-  tdd_enable,
-  tdd_txnrx,
-  tdd_mode,
-
-  // delay interface
-
-  up_clk,
-  up_enable,
-  up_txnrx,
-  up_adc_dld,
-  up_adc_dwdata,
-  up_adc_drdata,
-  up_dac_dld,
-  up_dac_dwdata,
-  up_dac_drdata,
-  delay_clk,
-  delay_rst,
-  delay_locked);
-
-  // this parameter controls the buffer type based on the target device.
-
-  parameter   DEVICE_TYPE = 0;
-  parameter   DAC_IODELAY_ENABLE = 0;
-  parameter   IO_DELAY_GROUP = "dev_if_delay_group";
-
-  // physical interface (receive)
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-
-  // physical interface (transmit)
-
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  // ensm control
-
-  output          enable;
-  output          txnrx;
-
-  // clock (common to both receive and transmit)
-
-  input           rst;
-  input           clk;
-  output          l_clk;
-
-  // receive data path interface
-
-  output          adc_valid;
-  output  [47:0]  adc_data;
-  output          adc_status;
-  input           adc_r1_mode;
-  input           adc_ddr_edgesel;
-
-  // transmit data path interface
-
-  input           dac_valid;
-  input   [47:0]  dac_data;
-  input           dac_r1_mode;
-
-  // tdd interface
-
-  input           tdd_enable;
-  input           tdd_txnrx;
-  input           tdd_mode;
-
-  // delay interface
-
-  input           up_clk;
-  input           up_enable;
-  input           up_txnrx;
-  input   [ 6:0]  up_adc_dld;
-  input   [34:0]  up_adc_dwdata;
-  output  [34:0]  up_adc_drdata;
-  input   [ 9:0]  up_dac_dld;
-  input   [49:0]  up_dac_dwdata;
-  output  [49:0]  up_dac_drdata;
-  input           delay_clk;
-  input           delay_rst;
-  output          delay_locked;
-
-  // internal registers
-
-  reg     [ 5:0]  rx_data_p = 0;
-  reg             rx_frame_p = 0;
-  reg     [ 1:0]  rx_ccnt = 0;
-  reg             rx_calign = 0;
-  reg             rx_align = 0;
-  reg     [11:0]  rx_data = 'd0;
-  reg     [ 1:0]  rx_frame = 'd0;
-  reg     [11:0]  rx_data_d = 'd0;
-  reg     [ 1:0]  rx_frame_d = 'd0;
-  reg             rx_error_r1 = 'd0;
-  reg             rx_valid_r1 = 'd0;
-  reg     [23:0]  rx_data_r1 = 'd0;
-  reg             rx_error_r2 = 'd0;
-  reg             rx_valid_r2 = 'd0;
-  reg     [47:0]  rx_data_r2 = 'd0;
-  reg             adc_p_valid = 'd0;
-  reg     [47:0]  adc_p_data = 'd0;
-  reg             adc_p_status = 'd0;
-  reg             adc_n_valid = 'd0;
-  reg     [47:0]  adc_n_data = 'd0;
-  reg             adc_n_status = 'd0;
-  reg             adc_valid_int = 'd0;
-  reg     [47:0]  adc_data_int = 'd0;
-  reg             adc_status_int = 'd0;
-  reg             adc_valid = 'd0;
-  reg     [47:0]  adc_data = 'd0;
-  reg             adc_status = 'd0;
-  reg     [ 2:0]  tx_data_cnt = 'd0;
-  reg     [47:0]  tx_data = 'd0;
-  reg             tx_frame = 'd0;
-  reg     [ 5:0]  tx_data_p = 'd0;
-  reg     [ 5:0]  tx_data_n = 'd0;
-  reg             tx_n_frame = 'd0;
-  reg     [ 5:0]  tx_n_data_p = 'd0;
-  reg     [ 5:0]  tx_n_data_n = 'd0;
-  reg             tx_p_frame = 'd0;
-  reg     [ 5:0]  tx_p_data_p = 'd0;
-  reg     [ 5:0]  tx_p_data_n = 'd0;
-  reg             up_enable_int = 'd0;
-  reg             up_txnrx_int = 'd0;
-  reg             enable_up_m1 = 'd0;
-  reg             txnrx_up_m1 = 'd0;
-  reg             enable_up = 'd0;
-  reg             txnrx_up = 'd0;
-  reg             enable_int = 'd0;
-  reg             txnrx_int = 'd0;
-  reg             enable_n_int = 'd0;
-  reg             txnrx_n_int = 'd0;
-  reg             enable_p_int = 'd0;
-  reg             txnrx_p_int = 'd0;
-
-  // internal signals
-
-  wire            rx_align_s;
-  wire    [ 3:0]  rx_frame_s;
-  wire    [ 3:0]  tx_data_sel_s;
-  wire    [ 5:0]  rx_data_p_s;
-  wire    [ 5:0]  rx_data_n_s;
-  wire            rx_frame_p_s;
-  wire            rx_frame_n_s;
-
-  genvar          l_inst;
-
-  // receive data path interface
-
-  assign rx_align_s = rx_frame_n_s ^ rx_frame_p_s;
-
-  always @(posedge l_clk) begin
-    rx_data_p <= rx_data_p_s;
-    rx_frame_p <= rx_frame_p_s;
-    rx_ccnt <= rx_ccnt + 1'b1;
-    if (rx_ccnt == 2'd0) begin
-      rx_calign <= rx_align;
-      rx_align <= rx_align_s;
-    end else begin
-      rx_calign <= rx_calign;
-      rx_align <= rx_align | rx_align_s;
-    end
-  end
-
-  assign rx_frame_s = {rx_frame_d, rx_frame};
-
-  always @(posedge l_clk) begin
-    if (rx_calign == 1'b1) begin
-      rx_data <= {rx_data_p, rx_data_n_s};
-      rx_frame <= {rx_frame_p, rx_frame_n_s};
-    end else begin
-      rx_data <= {rx_data_n_s, rx_data_p_s};
-      rx_frame <= {rx_frame_n_s, rx_frame_p_s};
-    end
-    rx_data_d <= rx_data;
-    rx_frame_d <= rx_frame;
-  end
-
-  // receive data path for single rf, frame is expected to qualify i/q msb only
-
-  always @(posedge l_clk) begin
-    rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
-    rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0;
-    if (rx_frame_s == 4'b1100) begin
-      rx_data_r1[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};
-      rx_data_r1[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
-    end
-  end
-
-  // receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only
-
-  always @(posedge l_clk) begin
-    rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
-      (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
-    rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0;
-    if (rx_frame_s == 4'b1111) begin
-      rx_data_r2[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};
-      rx_data_r2[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
-    end
-    if (rx_frame_s == 4'b0000) begin
-      rx_data_r2[35:24] <= {rx_data_d[11:6], rx_data[11:6]};
-      rx_data_r2[47:36] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
-    end
-  end
-
-  // receive data path mux
-
-  always @(posedge l_clk) begin
-    if (adc_r1_mode == 1'b1) begin
-      adc_p_valid <= rx_valid_r1;
-      adc_p_data <= {24'd0, rx_data_r1};
-      adc_p_status <= ~rx_error_r1;
-    end else begin
-      adc_p_valid <= rx_valid_r2;
-      adc_p_data <= rx_data_r2;
-      adc_p_status <= ~rx_error_r2;
-    end
-  end
-
-  // transfer to a synchronous common clock
-
-  always @(negedge l_clk) begin
-    adc_n_valid <= adc_p_valid;
-    adc_n_data <= adc_p_data;
-    adc_n_status <= adc_p_status;
-  end
-
-  always @(posedge clk) begin
-    adc_valid_int <= adc_n_valid;
-    adc_data_int <= adc_n_data;
-    adc_status_int <= adc_n_status;
-    adc_valid <= adc_valid_int;
-    if (adc_valid_int == 1'b1) begin
-      adc_data <= adc_data_int;
-    end
-    adc_status <= adc_status_int;
-  end
-
-  // transmit data path mux (reverse of what receive does above)
-  // the count simply selets the data muxing on the ddr outputs
-
-  assign tx_data_sel_s = {tx_data_cnt[2], dac_r1_mode, tx_data_cnt[1:0]};
-
-  always @(posedge clk) begin
-    if (dac_valid == 1'b1) begin
-      tx_data_cnt <= 3'b100;
-    end else if (tx_data_cnt[2] == 1'b1) begin
-      tx_data_cnt <= tx_data_cnt + 1'b1;
-    end
-    if (dac_valid == 1'b1) begin
-      tx_data <= dac_data;
-    end
-    case (tx_data_sel_s)
-      4'b1111: begin
-        tx_frame <= 1'b0;
-        tx_data_p <= tx_data[ 5: 0];
-        tx_data_n <= tx_data[17:12];
-      end
-      4'b1110: begin
-        tx_frame <= 1'b1;
-        tx_data_p <= tx_data[11: 6];
-        tx_data_n <= tx_data[23:18];
-      end
-      4'b1101: begin
-        tx_frame <= 1'b0;
-        tx_data_p <= tx_data[ 5: 0];
-        tx_data_n <= tx_data[17:12];
-      end
-      4'b1100: begin
-        tx_frame <= 1'b1;
-        tx_data_p <= tx_data[11: 6];
-        tx_data_n <= tx_data[23:18];
-      end
-      4'b1011: begin
-        tx_frame <= 1'b0;
-        tx_data_p <= tx_data[29:24];
-        tx_data_n <= tx_data[41:36];
-      end
-      4'b1010: begin
-        tx_frame <= 1'b0;
-        tx_data_p <= tx_data[35:30];
-        tx_data_n <= tx_data[47:42];
-      end
-      4'b1001: begin
-        tx_frame <= 1'b1;
-        tx_data_p <= tx_data[ 5: 0];
-        tx_data_n <= tx_data[17:12];
-      end
-      4'b1000: begin
-        tx_frame <= 1'b1;
-        tx_data_p <= tx_data[11: 6];
-        tx_data_n <= tx_data[23:18];
-      end
-      default: begin
-        tx_frame <= 1'b0;
-        tx_data_p <= 6'd0;
-        tx_data_n <= 6'd0;
-      end
-    endcase
-  end
-
-  // transfer data from a synchronous clock (skew less than 2ns)
-
-  always @(negedge clk) begin
-    tx_n_frame <= tx_frame;
-    tx_n_data_p <= tx_data_p;
-    tx_n_data_n <= tx_data_n;
-  end
-
-  always @(posedge l_clk) begin
-    tx_p_frame <= tx_n_frame;
-    tx_p_data_p <= tx_n_data_p;
-    tx_p_data_n <= tx_n_data_n;
-  end
-
-  // tdd/ensm control
-
-  always @(posedge up_clk) begin
-    up_enable_int <= up_enable;
-    up_txnrx_int <= up_txnrx;
-  end
-
-  always @(posedge clk or posedge rst) begin
-    if (rst == 1'b1) begin
-      enable_up_m1 <= 1'b0;
-      txnrx_up_m1 <= 1'b0;
-      enable_up <= 1'b0;
-      txnrx_up <= 1'b0;
-    end else begin
-      enable_up_m1 <= up_enable_int;
-      txnrx_up_m1 <= up_txnrx_int;
-      enable_up <= enable_up_m1;
-      txnrx_up <= txnrx_up_m1;
-    end
-  end
-
-  always @(posedge clk) begin
-    if (tdd_mode == 1'b1) begin
-      enable_int <= tdd_enable;
-      txnrx_int <= tdd_txnrx;
-    end else begin
-      enable_int <= enable_up;
-      txnrx_int <= txnrx_up;
-    end
-  end
-
-  always @(negedge clk) begin
-    enable_n_int <= enable_int;
-    txnrx_n_int <= txnrx_int;
-  end
-
-  always @(posedge l_clk) begin
-    enable_p_int <= enable_n_int;
-    txnrx_p_int <= txnrx_n_int;
-  end
-
-  // receive data interface, ibuf -> idelay -> iddr
-
-  generate
-  for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data
-  ad_lvds_in #(
-    .DEVICE_TYPE (DEVICE_TYPE),
-    .IODELAY_CTRL (0),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_rx_data (
-    .rx_clk (l_clk),
-    .rx_data_in_p (rx_data_in_p[l_inst]),
-    .rx_data_in_n (rx_data_in_n[l_inst]),
-    .rx_data_p (rx_data_p_s[l_inst]),
-    .rx_data_n (rx_data_n_s[l_inst]),
-    .up_clk (up_clk),
-    .up_dld (up_adc_dld[l_inst]),
-    .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
-    .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked ());
-  end
-  endgenerate
-
-  // receive frame interface, ibuf -> idelay -> iddr
-
-  ad_lvds_in #(
-    .DEVICE_TYPE (DEVICE_TYPE),
-    .IODELAY_CTRL (1),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_rx_frame (
-    .rx_clk (l_clk),
-    .rx_data_in_p (rx_frame_in_p),
-    .rx_data_in_n (rx_frame_in_n),
-    .rx_data_p (rx_frame_p_s),
-    .rx_data_n (rx_frame_n_s),
-    .up_clk (up_clk),
-    .up_dld (up_adc_dld[6]),
-    .up_dwdata (up_adc_dwdata[34:30]),
-    .up_drdata (up_adc_drdata[34:30]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked (delay_locked));
-
-  // transmit data interface, oddr -> obuf
-
-  generate
-  for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
-  ad_lvds_out #(
-    .DEVICE_TYPE (DEVICE_TYPE),
-    .SINGLE_ENDED (0),
-    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
-    .IODELAY_CTRL (0),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_tx_data (
-    .tx_clk (l_clk),
-    .tx_data_p (tx_p_data_p[l_inst]),
-    .tx_data_n (tx_p_data_n[l_inst]),
-    .tx_data_out_p (tx_data_out_p[l_inst]),
-    .tx_data_out_n (tx_data_out_n[l_inst]),
-    .up_clk (up_clk),
-    .up_dld (up_dac_dld[l_inst]),
-    .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
-    .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked ());
-  end
-  endgenerate
-
-  // transmit frame interface, oddr -> obuf
-
-  ad_lvds_out #(
-    .DEVICE_TYPE (DEVICE_TYPE),
-    .SINGLE_ENDED (0),
-    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
-    .IODELAY_CTRL (0),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_tx_frame (
-    .tx_clk (l_clk),
-    .tx_data_p (tx_p_frame),
-    .tx_data_n (tx_p_frame),
-    .tx_data_out_p (tx_frame_out_p),
-    .tx_data_out_n (tx_frame_out_n),
-    .up_clk (up_clk),
-    .up_dld (up_dac_dld[6]),
-    .up_dwdata (up_dac_dwdata[34:30]),
-    .up_drdata (up_dac_drdata[34:30]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked ());
-
-  // transmit clock interface, oddr -> obuf
-
-  ad_lvds_out #(
-    .DEVICE_TYPE (DEVICE_TYPE),
-    .SINGLE_ENDED (0),
-    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
-    .IODELAY_CTRL (0),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_tx_clk (
-    .tx_clk (l_clk),
-    .tx_data_p (1'b0),
-    .tx_data_n (1'b1),
-    .tx_data_out_p (tx_clk_out_p),
-    .tx_data_out_n (tx_clk_out_n),
-    .up_clk (up_clk),
-    .up_dld (up_dac_dld[7]),
-    .up_dwdata (up_dac_dwdata[39:35]),
-    .up_drdata (up_dac_drdata[39:35]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked ());
-
-  // enable, oddr -> obuf
-
-  ad_lvds_out #(
-    .DEVICE_TYPE (DEVICE_TYPE),
-    .SINGLE_ENDED (1),
-    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
-    .IODELAY_CTRL (0),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_enable (
-    .tx_clk (l_clk),
-    .tx_data_p (enable_p_int),
-    .tx_data_n (enable_p_int),
-    .tx_data_out_p (enable),
-    .tx_data_out_n (),
-    .up_clk (up_clk),
-    .up_dld (up_dac_dld[8]),
-    .up_dwdata (up_dac_dwdata[44:40]),
-    .up_drdata (up_dac_drdata[44:40]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked ());
-
-  // txnrx, oddr -> obuf
-
-  ad_lvds_out #(
-    .DEVICE_TYPE (DEVICE_TYPE),
-    .SINGLE_ENDED (1),
-    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
-    .IODELAY_CTRL (0),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_txnrx (
-    .tx_clk (l_clk),
-    .tx_data_p (txnrx_p_int),
-    .tx_data_n (txnrx_p_int),
-    .tx_data_out_p (txnrx),
-    .tx_data_out_n (),
-    .up_clk (up_clk),
-    .up_dld (up_dac_dld[9]),
-    .up_dwdata (up_dac_dwdata[49:45]),
-    .up_drdata (up_dac_drdata[49:45]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked ());
-
-  // device clock interface (receive clock)
-
-  ad_lvds_clk #(
-    .DEVICE_TYPE (DEVICE_TYPE))
-  i_clk (
-    .clk_in_p (rx_clk_in_p),
-    .clk_in_n (rx_clk_in_n),
-    .clk (l_clk));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/axi_ad9361_dev_if_alt.v b/library/axi_ad9361/axi_ad9361_dev_if_alt.v
deleted file mode 100644
index fd91e4dd1..000000000
--- a/library/axi_ad9361/axi_ad9361_dev_if_alt.v
+++ /dev/null
@@ -1,349 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// This interface includes both the transmit and receive components -
-// They both uses the same clock (sourced from the receiving side).
-
-`timescale 1ns/100ps
-
-module axi_ad9361_dev_if (
-
-  // physical interface (receive)
-
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-
-  // physical interface (transmit)
-
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
-
-  // ensm control
-
-  enable,
-  txnrx,
-
-  // clock (common to both receive and transmit)
-
-  rst,
-  clk,
-  l_clk,
-
-  // receive data path interface
-
-  adc_valid,
-  adc_data,
-  adc_status,
-  adc_r1_mode,
-  adc_ddr_edgesel,
-
-  // transmit data path interface
-
-  dac_valid,
-  dac_data,
-  dac_r1_mode,
-
-  // tdd interface
-
-  tdd_enable,
-  tdd_txnrx,
-  tdd_mode,
-
-  // delay interface
-
-  up_clk,
-  up_enable,
-  up_txnrx,
-  up_adc_dld,
-  up_adc_dwdata,
-  up_adc_drdata,
-  up_dac_dld,
-  up_dac_dwdata,
-  up_dac_drdata,
-  delay_clk,
-  delay_rst,
-  delay_locked);
-
-  // this parameter controls the buffer type based on the target device.
-
-  parameter   DEVICE_TYPE = 0;
-  parameter   DAC_IODELAY_ENABLE = 0;
-  parameter   IO_DELAY_GROUP = "dev_if_delay_group";
-
-  // physical interface (receive)
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-
-  // physical interface (transmit)
-
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  // ensm control
-
-  output          enable;
-  output          txnrx;
-
-  // clock (common to both receive and transmit)
-
-  input           rst;
-  input           clk;
-  output          l_clk;
-
-  // receive data path interface
-
-  output          adc_valid;
-  output  [47:0]  adc_data;
-  output          adc_status;
-  input           adc_r1_mode;
-  input           adc_ddr_edgesel;
-
-  // transmit data path interface
-
-  input           dac_valid;
-  input   [47:0]  dac_data;
-  input           dac_r1_mode;
-
-  // tdd interface
-
-  input           tdd_enable;
-  input           tdd_txnrx;
-  input           tdd_mode;
-
-  // delay interface
-
-  input           up_clk;
-  input           up_enable;
-  input           up_txnrx;
-  input   [ 6:0]  up_adc_dld;
-  input   [34:0]  up_adc_dwdata;
-  output  [34:0]  up_adc_drdata;
-  input   [ 9:0]  up_dac_dld;
-  input   [49:0]  up_dac_dwdata;
-  output  [49:0]  up_dac_drdata;
-  input           delay_clk;
-  input           delay_rst;
-  output          delay_locked;
-
-  // internal registers
-
-  reg     [ 3:0]  rx_frame = 'd0;
-  reg     [ 5:0]  rx_data_3 = 'd0;
-  reg     [ 5:0]  rx_data_2 = 'd0;
-  reg     [ 5:0]  rx_data_1 = 'd0;
-  reg     [ 5:0]  rx_data_0 = 'd0;
-  reg             rx_error_r2 = 'd0;
-  reg             rx_valid_r2 = 'd0;
-  reg     [23:0]  rx_data_r2 = 'd0;
-  reg             adc_valid = 'd0;
-  reg     [47:0]  adc_data = 'd0;
-  reg             adc_status = 'd0;
-  reg             tx_data_sel = 'd0;
-  reg     [47:0]  tx_data = 'd0;
-  reg     [ 3:0]  tx_frame = 'd0;
-  reg     [ 5:0]  tx_data_0 = 'd0;
-  reg     [ 5:0]  tx_data_1 = 'd0;
-  reg     [ 5:0]  tx_data_2 = 'd0;
-  reg     [ 5:0]  tx_data_3 = 'd0;
-
-  // internal signals
-
-  wire    [ 3:0]  rx_frame_inv_s;
-  wire            tx_locked_s;
-  wire    [ 3:0]  rx_frame_s;
-  wire    [ 5:0]  rx_data_0_s;
-  wire    [ 5:0]  rx_data_1_s;
-  wire    [ 5:0]  rx_data_2_s;
-  wire    [ 5:0]  rx_data_3_s;
-  wire            rx_locked_s;
-
-  // tdd support-
-
-  assign enable = up_enable;
-  assign txnrx = up_txnrx;
-
-  // defaults
-
-  assign delay_locked = 1'd1;
-
-  // receive data path interface
-
-  assign rx_frame_inv_s = ~rx_frame;
-
-  always @(posedge l_clk) begin
-    rx_frame <= rx_frame_s;
-    rx_data_3 <= rx_data_3_s;
-    rx_data_2 <= rx_data_2_s;
-    rx_data_1 <= rx_data_1_s;
-    rx_data_0 <= rx_data_0_s;
-    if (rx_frame_inv_s == rx_frame_s) begin
-      rx_error_r2 <= 1'b0;
-    end else begin
-      rx_error_r2 <= 1'b1;
-    end
-    case (rx_frame)
-      4'b1111: begin
-        rx_valid_r2 <= 1'b1;
-        rx_data_r2[23:12] <= {rx_data_1,   rx_data_3};
-        rx_data_r2[11: 0] <= {rx_data_0,   rx_data_2};
-      end
-      4'b1110: begin
-        rx_valid_r2 <= 1'b1;
-        rx_data_r2[23:12] <= {rx_data_2,   rx_data_0_s};
-        rx_data_r2[11: 0] <= {rx_data_1,   rx_data_3};
-      end
-      4'b1100: begin
-        rx_valid_r2 <= 1'b1;
-        rx_data_r2[23:12] <= {rx_data_3,   rx_data_1_s};
-        rx_data_r2[11: 0] <= {rx_data_2,   rx_data_0_s};
-      end
-      4'b1000: begin
-        rx_valid_r2 <= 1'b1;
-        rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s};
-        rx_data_r2[11: 0] <= {rx_data_3,   rx_data_1_s};
-      end
-      4'b0000: begin
-        rx_valid_r2 <= 1'b0;
-        rx_data_r2[23:12] <= {rx_data_1,   rx_data_3};
-        rx_data_r2[11: 0] <= {rx_data_0,   rx_data_2};
-      end
-      4'b0001: begin
-        rx_valid_r2 <= 1'b0;
-        rx_data_r2[23:12] <= {rx_data_2,   rx_data_0_s};
-        rx_data_r2[11: 0] <= {rx_data_1,   rx_data_3};
-      end
-      4'b0011: begin
-        rx_valid_r2 <= 1'b0;
-        rx_data_r2[23:12] <= {rx_data_3,   rx_data_1_s};
-        rx_data_r2[11: 0] <= {rx_data_2,   rx_data_0_s};
-      end
-      4'b0111: begin
-        rx_valid_r2 <= 1'b0;
-        rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s};
-        rx_data_r2[11: 0] <= {rx_data_3,   rx_data_1_s};
-      end
-      default: begin
-        rx_valid_r2 <= 1'b0;
-        rx_data_r2[23:12] <= 12'd0;
-        rx_data_r2[11: 0] <= 12'd0;
-      end
-    endcase
-    if (rx_valid_r2 == 1'b1) begin
-      adc_valid <= 1'b0;
-      adc_data <= {24'd0, rx_data_r2};
-    end else begin
-      adc_valid <= 1'b1;
-      adc_data <= {rx_data_r2, adc_data[23:0]};
-    end
-    adc_status <= ~rx_error_r2 & rx_locked_s & tx_locked_s;
-  end
-
-  // transmit data path mux
-
-  always @(posedge l_clk) begin
-    tx_data_sel <= dac_valid;
-    tx_data <= dac_data;
-    if (tx_data_sel == 1'b1) begin
-      tx_frame <= 4'b1111;
-      tx_data_0 <= tx_data[11: 6];
-      tx_data_1 <= tx_data[23:18];
-      tx_data_2 <= tx_data[ 5: 0];
-      tx_data_3 <= tx_data[17:12];
-    end else begin
-      tx_frame <= 4'b0000;
-      tx_data_0 <= tx_data[35:30];
-      tx_data_1 <= tx_data[47:42];
-      tx_data_2 <= tx_data[29:24];
-      tx_data_3 <= tx_data[41:36];
-    end
-  end
-
-  // interface (transmit)
-
-  axi_ad9361_alt_lvds_tx i_tx (
-    .tx_clk_out_p (tx_clk_out_p),
-    .tx_clk_out_n (tx_clk_out_n),
-    .tx_frame_out_p (tx_frame_out_p),
-    .tx_frame_out_n (tx_frame_out_n),
-    .tx_data_out_p (tx_data_out_p),
-    .tx_data_out_n (tx_data_out_n),
-    .tx_clk (rx_clk_in_p),
-    .clk (l_clk),
-    .tx_frame (tx_frame),
-    .tx_data_0 (tx_data_0),
-    .tx_data_1 (tx_data_1),
-    .tx_data_2 (tx_data_2),
-    .tx_data_3 (tx_data_3),
-    .tx_locked (tx_locked_s));
-
-  // interface (receive)
-
-  axi_ad9361_alt_lvds_rx i_rx (
-    .rx_clk_in_p (rx_clk_in_p),
-    .rx_clk_in_n (rx_clk_in_n),
-    .rx_frame_in_p (rx_frame_in_p),
-    .rx_frame_in_n (rx_frame_in_n),
-    .rx_data_in_p (rx_data_in_p),
-    .rx_data_in_n (rx_data_in_n),
-    .clk (l_clk),
-    .rx_frame (rx_frame_s),
-    .rx_data_0 (rx_data_0_s),
-    .rx_data_1 (rx_data_1_s),
-    .rx_data_2 (rx_data_2_s),
-    .rx_data_3 (rx_data_3_s),
-    .rx_locked (rx_locked_s));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From 243d3e6e41922e06c9b5ad778d7e8eb25c5447ff Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 15:44:55 -0400
Subject: [PATCH 165/972] ad9361- a10soc sdc files

---
 library/axi_ad9361/axi_ad9361.v          | 2 +-
 library/axi_ad9361/axi_ad9361_constr.sdc | 4 ++++
 library/axi_ad9361/axi_ad9361_hw.tcl     | 2 ++
 3 files changed, 7 insertions(+), 1 deletion(-)
 create mode 100644 library/axi_ad9361/axi_ad9361_constr.sdc

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 9d2365831..a242ab42e 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -447,7 +447,7 @@ module axi_ad9361 (
   assign up_adc_drdata_s[64:35] = 30'd0;
   assign up_dac_drdata_s[79:50] = 30'd0;
 
-  axi_ad9361_dev_if #(
+  axi_ad9361_lvds_if #(
     .DEVICE_TYPE (DEVICE_TYPE),
     .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IO_DELAY_GROUP (IO_DELAY_GROUP))
diff --git a/library/axi_ad9361/axi_ad9361_constr.sdc b/library/axi_ad9361/axi_ad9361_constr.sdc
new file mode 100644
index 000000000..158259284
--- /dev/null
+++ b/library/axi_ad9361/axi_ad9361_constr.sdc
@@ -0,0 +1,4 @@
+
+set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*]
+set_false_path -from [get_registers *i_dev_if|up_txnrx_int*]  -to [get_registers *i_dev_if|txnrx_up_m1*]
+
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 587edf10f..b1b4c1e3d 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -54,6 +54,8 @@ add_fileset_file axi_ad9361_tx.v          VERILOG PATH axi_ad9361_tx.v
 add_fileset_file axi_ad9361_tdd.v         VERILOG PATH axi_ad9361_tdd.v
 add_fileset_file axi_ad9361_tdd_if.v      VERILOG PATH axi_ad9361_tdd_if.v
 add_fileset_file axi_ad9361.v             VERILOG PATH axi_ad9361.v TOP_LEVEL_FILE
+add_fileset_file ad_axi_ip_constr.sdc     SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file axi_ad9361_constr.sdc    SDC     PATH axi_ad9361_constr.sdc
 
 # parameters
 

From 89f5d2394e9803595499d11c25dfe1dabfaa32fb Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 15:46:27 -0400
Subject: [PATCH 166/972] altera- clock variations

---
 library/common/altera/ad_cmos_clk.v | 26 +++++---------------------
 library/common/altera/ad_lvds_clk.v | 12 +++++++-----
 2 files changed, 12 insertions(+), 26 deletions(-)

diff --git a/library/common/altera/ad_cmos_clk.v b/library/common/altera/ad_cmos_clk.v
index f5a344f65..652a9dd75 100644
--- a/library/common/altera/ad_cmos_clk.v
+++ b/library/common/altera/ad_cmos_clk.v
@@ -49,29 +49,13 @@ module ad_cmos_clk (
   input     clk_in;
   output    clk;
 
-  // wires
-
-  wire      clk_ibuf_s;
-
   // instantiations
 
-  IBUFG i_rx_clk_ibuf (
-    .I (clk_in),
-    .O (clk_ibuf_s));
-
-  generate
-  if (DEVICE_TYPE == VIRTEX6) begin
-  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
-    .CLR (1'b0),
-    .CE (1'b1),
-    .I (clk_ibuf_s),
-    .O (clk));
-  end else begin
-  BUFG i_clk_gbuf (
-    .I (clk_ibuf_s),
-    .O (clk));
-  end
-  endgenerate
+  alt_clk i_clk (
+    .rst (1'b0),
+    .refclk (clk_in),
+    .outclk_0 (clk),
+    .locked ());
 
 endmodule
 
diff --git a/library/common/altera/ad_lvds_clk.v b/library/common/altera/ad_lvds_clk.v
index eab93e029..12937f03e 100644
--- a/library/common/altera/ad_lvds_clk.v
+++ b/library/common/altera/ad_lvds_clk.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -46,14 +44,18 @@ module ad_lvds_clk (
   clk);
 
   parameter   DEVICE_TYPE       = 0;
-  localparam  SERIES7       = 0;
-  localparam  VIRTEX6       = 1;
 
   input     clk_in_p;
   input     clk_in_n;
   output    clk;
   
-  assign clk = clk_in_p;
+  // instantiations
+
+  alt_clk i_clk (
+    .rst (1'b0),
+    .refclk (clk_in_p),
+    .outclk_0 (clk),
+    .locked ());
 
 endmodule
 

From 61b531b1c1b906cb6ef25e9cd42d3c77f4cf3952 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 15:46:44 -0400
Subject: [PATCH 167/972] a10soc device update

---
 projects/fmcomms2/a10soc/system_bd.qsys | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/fmcomms2/a10soc/system_bd.qsys b/projects/fmcomms2/a10soc/system_bd.qsys
index 907e4c349..97b293a4e 100755
--- a/projects/fmcomms2/a10soc/system_bd.qsys
+++ b/projects/fmcomms2/a10soc/system_bd.qsys
@@ -292,7 +292,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40I2SGES" />
+ <parameter name="device" value="10AS066N3F40E2SGE2" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -347,7 +347,7 @@
    type="reset"
    dir="end" />
  <module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40I2SGES" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
@@ -375,7 +375,7 @@
   <parameter
      name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 32" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40I2SGES" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />

From 3f5e1e12038c2a2a16976480c81a12d044c53821 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 29 Apr 2016 10:16:38 -0400
Subject: [PATCH 168/972] ad9361- dev_if module name change

---
 library/axi_ad9361/axi_ad9361_lvds_if.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_ad9361/axi_ad9361_lvds_if.v b/library/axi_ad9361/axi_ad9361_lvds_if.v
index d598d704e..e9a11cf07 100644
--- a/library/axi_ad9361/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/axi_ad9361_lvds_if.v
@@ -37,7 +37,7 @@
 
 `timescale 1ns/100ps
 
-module axi_ad9361_dev_if (
+module axi_ad9361_lvds_if (
 
   // physical interface (receive)
 

From 385ed31a4577e205c9b92fa314381a1a7ab7e8f5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 29 Apr 2016 10:17:18 -0400
Subject: [PATCH 169/972] make files update

---
 library/axi_ad9361/Makefile       |  2 +-
 library/util_dacfifo/Makefile     |  1 +
 projects/daq2/zc706/Makefile      |  4 ++
 projects/daq3/zc706/Makefile      |  4 ++
 projects/fmcadc2/zc706/Makefile   |  4 ++
 projects/fmcadc4/zc706/Makefile   |  4 ++
 projects/fmcomms2/Makefile        |  3 ++
 projects/fmcomms2/a10soc/Makefile | 75 +++++++++++++++++++++++++++++++
 projects/fmcomms7/zc706/Makefile  |  4 ++
 projects/usdrx1/zc706/Makefile    |  4 ++
 10 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile
index eb79b9900..ab8ddbc6d 100644
--- a/library/axi_ad9361/Makefile
+++ b/library/axi_ad9361/Makefile
@@ -37,7 +37,7 @@ M_DEPS += ../common/up_dac_common.v
 M_DEPS += ../common/up_dac_channel.v
 M_DEPS += ../common/up_tdd_cntrl.v
 M_DEPS += axi_ad9361_constr.xdc
-M_DEPS += axi_ad9361_dev_if.v
+M_DEPS += axi_ad9361_lvds_if.v
 M_DEPS += axi_ad9361_cmos_if.v
 M_DEPS += axi_ad9361_rx_pnmon.v
 M_DEPS += axi_ad9361_rx_channel.v
diff --git a/library/util_dacfifo/Makefile b/library/util_dacfifo/Makefile
index 0cf20b4bd..9c7ce6257 100644
--- a/library/util_dacfifo/Makefile
+++ b/library/util_dacfifo/Makefile
@@ -10,6 +10,7 @@ M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_mem.v
 M_DEPS += util_dacfifo.v
+M_DEPS += util_dacfifo_constr.xdc
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index 14e469a0c..3bc213b4f 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -17,6 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
@@ -25,6 +26,7 @@ M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -65,6 +67,7 @@ clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -86,6 +89,7 @@ lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index 2e77582c0..cdf156482 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -17,6 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
@@ -25,6 +26,7 @@ M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -66,6 +68,7 @@ clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -88,6 +91,7 @@ lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 352efb7bc..d3305cc22 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -17,12 +17,14 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -58,6 +60,7 @@ clean-all:clean
 	make -C ../../../library/axi_ad9625 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -74,6 +77,7 @@ lib:
 	make -C ../../../library/axi_ad9625
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index e3d0a21a2..b646b7ad8 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -17,12 +17,14 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -61,6 +63,7 @@ clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -80,6 +83,7 @@ lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/fmcomms2/Makefile b/projects/fmcomms2/Makefile
index 9e2211814..7da011a70 100644
--- a/projects/fmcomms2/Makefile
+++ b/projects/fmcomms2/Makefile
@@ -7,6 +7,7 @@
 
 .PHONY: all clean clean-all 
 all:
+	-make -C a10soc all
 	-make -C ac701 all
 	-make -C kc705 all
 	-make -C mitx045 all
@@ -17,6 +18,7 @@ all:
 
 
 clean: 
+	make -C a10soc clean
 	make -C ac701 clean
 	make -C kc705 clean
 	make -C mitx045 clean
@@ -27,6 +29,7 @@ clean:
 
 
 clean-all:
+	make -C a10soc clean-all
 	make -C ac701 clean-all
 	make -C kc705 clean-all
 	make -C mitx045 clean-all
diff --git a/projects/fmcomms2/a10soc/Makefile b/projects/fmcomms2/a10soc/Makefile
index 77133e4f4..ed286a1c4 100644
--- a/projects/fmcomms2/a10soc/Makefile
+++ b/projects/fmcomms2/a10soc/Makefile
@@ -9,9 +9,84 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += system_bd.qsys
+M_DEPS += ../common/fmcomms2_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_addsub.v
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dcfilter.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_iqcor.v
+M_DEPS += ../../../library/common/ad_mul.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_tdd_control.v
+M_DEPS += ../../../library/common/altera/DSP48E1.v
+M_DEPS += ../../../library/common/altera/MULT_MACRO.v
+M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
+M_DEPS += ../../../library/common/altera/ad_cmos_in.v
+M_DEPS += ../../../library/common/altera/ad_cmos_out.v
+M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
+M_DEPS += ../../../library/common/altera/ad_lvds_in.v
+M_DEPS += ../../../library/common/altera/ad_lvds_out.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_tdd_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index 2caa37ee7..f42098826 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -17,6 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
@@ -25,6 +26,7 @@ M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -65,6 +67,7 @@ clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -86,6 +89,7 @@ lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index 936fbbcfe..d653e20b8 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -17,11 +17,13 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -57,6 +59,7 @@ clean-all:clean
 	make -C ../../../library/axi_ad9671 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -73,6 +76,7 @@ lib:
 	make -C ../../../library/axi_ad9671
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt

From 583bafd17a0821c2fa92207e91a5f9c7c3b5fd34 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Wed, 4 May 2016 16:14:29 +0300
Subject: [PATCH 170/972] axi_ad7616: Add a new register for IF_TYPE

Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode.
---
 library/axi_ad7616/axi_ad7616_control.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index 50450023e..22198be1f 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -182,6 +182,7 @@ module axi_ad7616_control (
           8'h00 : up_rdata = PCORE_VERSION;
           8'h01 : up_rdata = ID;
           8'h02 : up_rdata = up_scratch;
+          8'h03 : up_rdata = IF_TYPE;
           8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
           8'h11 : up_rdata = up_conv_rate;
           8'h12 : up_rdata = up_read_data_s;

From 9104b2cc609cafe3e3e35355fa6e65f8688c07cb Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Wed, 4 May 2016 19:13:25 +0300
Subject: [PATCH 171/972] ad6676evb, fmcadc2, fmcadc4, fmcadc5,...

ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
---
 projects/ad6676evb/vc707/system_project.tcl | 2 --
 projects/ad6676evb/zc706/system_project.tcl | 2 --
 projects/fmcadc2/vc707/system_project.tcl   | 2 --
 projects/fmcadc2/zc706/system_project.tcl   | 2 --
 projects/fmcadc4/zc706/system_project.tcl   | 2 --
 projects/fmcadc5/vc707/system_project.tcl   | 2 --
 6 files changed, 12 deletions(-)

diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl
index 2d69b5316..4a0373b6c 100644
--- a/projects/ad6676evb/vc707/system_project.tcl
+++ b/projects/ad6676evb/vc707/system_project.tcl
@@ -12,8 +12,6 @@ adi_project_files ad6676evb_vc707 [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run ad6676evb_vc707
 
diff --git a/projects/ad6676evb/zc706/system_project.tcl b/projects/ad6676evb/zc706/system_project.tcl
index f7b46e8ac..0f2ab2ec9 100644
--- a/projects/ad6676evb/zc706/system_project.tcl
+++ b/projects/ad6676evb/zc706/system_project.tcl
@@ -12,8 +12,6 @@ adi_project_files ad6676evb_zc706 [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run ad6676evb_zc706
 
diff --git a/projects/fmcadc2/vc707/system_project.tcl b/projects/fmcadc2/vc707/system_project.tcl
index 7941890e5..7628b4798 100644
--- a/projects/fmcadc2/vc707/system_project.tcl
+++ b/projects/fmcadc2/vc707/system_project.tcl
@@ -13,8 +13,6 @@ adi_project_files fmcadc2_vc707 [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run fmcadc2_vc707
 
diff --git a/projects/fmcadc2/zc706/system_project.tcl b/projects/fmcadc2/zc706/system_project.tcl
index 029d6c139..b9075b00d 100644
--- a/projects/fmcadc2/zc706/system_project.tcl
+++ b/projects/fmcadc2/zc706/system_project.tcl
@@ -14,8 +14,6 @@ adi_project_files fmcadc2_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run fmcadc2_zc706
 
diff --git a/projects/fmcadc4/zc706/system_project.tcl b/projects/fmcadc4/zc706/system_project.tcl
index 6c4b2df86..bc6a20613 100644
--- a/projects/fmcadc4/zc706/system_project.tcl
+++ b/projects/fmcadc4/zc706/system_project.tcl
@@ -14,8 +14,6 @@ adi_project_files fmcadc4_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run fmcadc4_zc706
 
diff --git a/projects/fmcadc5/vc707/system_project.tcl b/projects/fmcadc5/vc707/system_project.tcl
index b3c7ab290..ba8ccb686 100644
--- a/projects/fmcadc5/vc707/system_project.tcl
+++ b/projects/fmcadc5/vc707/system_project.tcl
@@ -15,8 +15,6 @@ adi_project_files fmcadc5_vc707 [list \
   "$ad_hdl_dir/library/common/ad_lvds_out.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run fmcadc5_vc707
 

From 3ca3414522f30bc7a12f0551aea85502f5e4d415 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Wed, 4 May 2016 19:20:01 +0300
Subject: [PATCH 172/972] fmcadc2: Fixed bus data width

---
 projects/fmcadc2/vc707/system_top.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v
index e00f5dc61..1ce119e2a 100644
--- a/projects/fmcadc2/vc707/system_top.v
+++ b/projects/fmcadc2/vc707/system_top.v
@@ -233,7 +233,7 @@ module system_top (
     .spi_adc_sdio (spi_adc_sdio),
     .spi_ext_sdio (spi_ext_sdio));
 
-  ad_iobuf #(.DATA_WIDTH(3)) i_iobuf (
+  ad_iobuf #(.DATA_WIDTH(2)) i_iobuf (
     .dio_t (gpio_t[33:32]),
     .dio_i (gpio_o[33:32]),
     .dio_o (gpio_i[33:32]),

From b6b68e9ab7804e7ba83e3b8e3ace42520e2c5d20 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Wed, 4 May 2016 19:32:06 +0300
Subject: [PATCH 173/972] axi_jesd_gt: Split the constraint file

-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
---
 library/axi_jesd_gt/axi_jesd_gt_constr.xdc    | 30 -------------------
 library/axi_jesd_gt/axi_jesd_gt_ip.tcl        |  4 +++
 library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc | 19 ++++++++++++
 library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc | 19 ++++++++++++
 4 files changed, 42 insertions(+), 30 deletions(-)
 create mode 100644 library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc
 create mode 100644 library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc

diff --git a/library/axi_jesd_gt/axi_jesd_gt_constr.xdc b/library/axi_jesd_gt/axi_jesd_gt_constr.xdc
index 65112d6ce..4aca3cd05 100644
--- a/library/axi_jesd_gt/axi_jesd_gt_constr.xdc
+++ b/library/axi_jesd_gt/axi_jesd_gt_constr.xdc
@@ -1,35 +1,5 @@
 
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync*}]
 set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
 
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync_m1_reg && IS_SEQUENTIAL}]
 
-set_false_path -from [get_cells -hier -filter {name =~ *up_rx_preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *up_tx_preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
 
diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
index 79688653b..e85b0ba1a 100644
--- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
+++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
@@ -16,12 +16,16 @@ adi_ip_files axi_jesd_gt [list \
   "$ad_hdl_dir/library/common/up_axi.v" \
   "$ad_hdl_dir/library/common/up_gt_channel.v" \
   "$ad_hdl_dir/library/common/up_gt.v" \
+  "axi_jesd_gt_tx_constr.xdc" \
+  "axi_jesd_gt_rx_constr.xdc" \
   "axi_jesd_gt_constr.xdc" \
   "axi_jesd_gt.v" ]
 
 adi_ip_properties axi_jesd_gt
 
 adi_ip_constraints axi_jesd_gt [list \
+  "axi_jesd_gt_tx_constr.xdc" \
+  "axi_jesd_gt_rx_constr.xdc" \
   "axi_jesd_gt_constr.xdc" ]
 
 ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core]
diff --git a/library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc b/library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc
new file mode 100644
index 000000000..cd93336dc
--- /dev/null
+++ b/library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc
@@ -0,0 +1,19 @@
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync*}]
+
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync_m1_reg && IS_SEQUENTIAL}]
+
+set_false_path -from [get_cells -hier -filter {name =~ *up_rx_preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
+
diff --git a/library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc b/library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc
new file mode 100644
index 000000000..cf1ba45a8
--- /dev/null
+++ b/library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc
@@ -0,0 +1,19 @@
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync*}]
+
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync_m1_reg && IS_SEQUENTIAL}]
+
+set_false_path -from [get_cells -hier -filter {name =~ *up_tx_preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
+

From be74db656c0fe51b940890d3421fa4c52e6489c3 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Wed, 4 May 2016 19:37:33 +0300
Subject: [PATCH 174/972] ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:

Update system_project.tcl scripts to correctly select the necessary
constraint files
---
 projects/ad6676evb/vc707/system_project.tcl   | 1 +
 projects/ad6676evb/zc706/system_project.tcl   | 1 +
 projects/fmcadc2/vc707/system_project.tcl     | 1 +
 projects/fmcadc2/zc706/system_project.tcl     | 1 +
 projects/fmcadc4/zc706/system_project.tcl     | 1 +
 projects/fmcadc5/vc707/system_project.tcl     | 1 +
 projects/fmcjesdadc1/kc705/system_project.tcl | 2 ++
 projects/fmcjesdadc1/vc707/system_project.tcl | 2 ++
 projects/fmcjesdadc1/zc706/system_project.tcl | 2 ++
 9 files changed, 12 insertions(+)

diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl
index 4a0373b6c..5439f1a91 100644
--- a/projects/ad6676evb/vc707/system_project.tcl
+++ b/projects/ad6676evb/vc707/system_project.tcl
@@ -12,6 +12,7 @@ adi_project_files ad6676evb_vc707 [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
 
 adi_project_run ad6676evb_vc707
 
diff --git a/projects/ad6676evb/zc706/system_project.tcl b/projects/ad6676evb/zc706/system_project.tcl
index 0f2ab2ec9..b505e455c 100644
--- a/projects/ad6676evb/zc706/system_project.tcl
+++ b/projects/ad6676evb/zc706/system_project.tcl
@@ -12,6 +12,7 @@ adi_project_files ad6676evb_zc706 [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
 
 adi_project_run ad6676evb_zc706
 
diff --git a/projects/fmcadc2/vc707/system_project.tcl b/projects/fmcadc2/vc707/system_project.tcl
index 7628b4798..cdbb502bc 100644
--- a/projects/fmcadc2/vc707/system_project.tcl
+++ b/projects/fmcadc2/vc707/system_project.tcl
@@ -13,6 +13,7 @@ adi_project_files fmcadc2_vc707 [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
 
 adi_project_run fmcadc2_vc707
 
diff --git a/projects/fmcadc2/zc706/system_project.tcl b/projects/fmcadc2/zc706/system_project.tcl
index b9075b00d..406afe7d3 100644
--- a/projects/fmcadc2/zc706/system_project.tcl
+++ b/projects/fmcadc2/zc706/system_project.tcl
@@ -14,6 +14,7 @@ adi_project_files fmcadc2_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
 
 adi_project_run fmcadc2_zc706
 
diff --git a/projects/fmcadc4/zc706/system_project.tcl b/projects/fmcadc4/zc706/system_project.tcl
index bc6a20613..d14bc56c9 100644
--- a/projects/fmcadc4/zc706/system_project.tcl
+++ b/projects/fmcadc4/zc706/system_project.tcl
@@ -14,6 +14,7 @@ adi_project_files fmcadc4_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
 
 adi_project_run fmcadc4_zc706
 
diff --git a/projects/fmcadc5/vc707/system_project.tcl b/projects/fmcadc5/vc707/system_project.tcl
index ba8ccb686..8611d77cf 100644
--- a/projects/fmcadc5/vc707/system_project.tcl
+++ b/projects/fmcadc5/vc707/system_project.tcl
@@ -15,6 +15,7 @@ adi_project_files fmcadc5_vc707 [list \
   "$ad_hdl_dir/library/common/ad_lvds_out.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
 
 adi_project_run fmcadc5_vc707
 
diff --git a/projects/fmcjesdadc1/kc705/system_project.tcl b/projects/fmcjesdadc1/kc705/system_project.tcl
index c8bb0ab9c..f5c371353 100644
--- a/projects/fmcjesdadc1/kc705/system_project.tcl
+++ b/projects/fmcjesdadc1/kc705/system_project.tcl
@@ -11,4 +11,6 @@ adi_project_files fmcjesdadc1_kc705 [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
+  
 adi_project_run fmcjesdadc1_kc705
diff --git a/projects/fmcjesdadc1/vc707/system_project.tcl b/projects/fmcjesdadc1/vc707/system_project.tcl
index 49573956e..07b5f24af 100644
--- a/projects/fmcjesdadc1/vc707/system_project.tcl
+++ b/projects/fmcjesdadc1/vc707/system_project.tcl
@@ -11,4 +11,6 @@ adi_project_files fmcjesdadc1_vc707 [list \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
+  
 adi_project_run fmcjesdadc1_vc707
diff --git a/projects/fmcjesdadc1/zc706/system_project.tcl b/projects/fmcjesdadc1/zc706/system_project.tcl
index 3177a47eb..28443abc5 100644
--- a/projects/fmcjesdadc1/zc706/system_project.tcl
+++ b/projects/fmcjesdadc1/zc706/system_project.tcl
@@ -13,6 +13,8 @@ adi_project_files fmcjesdadc1_zc706 [list \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
+  
 adi_project_run fmcjesdadc1_zc706
 
 

From d82ca5dc3c3d7412aca1715d1be9fb76ea721caa Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:37:22 -0400
Subject: [PATCH 175/972] library/common- altera variations

---
 library/common/ad_cmos_clk.v        | 10 ++++++++++
 library/common/ad_lvds_clk.v        | 10 ++++++++++
 library/common/altera/ad_cmos_clk.v | 10 ++++++++--
 library/common/altera/ad_cmos_in.v  |  2 +-
 library/common/altera/ad_cmos_out.v |  2 +-
 library/common/altera/ad_lvds_clk.v | 10 ++++++++--
 library/common/altera/ad_lvds_in.v  |  3 +--
 library/common/altera/ad_lvds_out.v |  5 ++---
 8 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/library/common/ad_cmos_clk.v b/library/common/ad_cmos_clk.v
index f5a344f65..bbd9d8e1f 100644
--- a/library/common/ad_cmos_clk.v
+++ b/library/common/ad_cmos_clk.v
@@ -39,6 +39,9 @@
 
 module ad_cmos_clk (
 
+  rst,
+  locked,
+
   clk_in,
   clk);
 
@@ -46,6 +49,9 @@ module ad_cmos_clk (
   localparam  SERIES7       = 0;
   localparam  VIRTEX6       = 1;
 
+  input     rst;
+  output    locked;
+
   input     clk_in;
   output    clk;
 
@@ -53,6 +59,10 @@ module ad_cmos_clk (
 
   wire      clk_ibuf_s;
 
+  // defaults
+
+  assign locked = 1'b1;
+
   // instantiations
 
   IBUFG i_rx_clk_ibuf (
diff --git a/library/common/ad_lvds_clk.v b/library/common/ad_lvds_clk.v
index 5bcb66241..2bacd6d9c 100644
--- a/library/common/ad_lvds_clk.v
+++ b/library/common/ad_lvds_clk.v
@@ -41,6 +41,9 @@
 
 module ad_lvds_clk (
 
+  rst,
+  locked,
+
   clk_in_p,
   clk_in_n,
   clk);
@@ -49,6 +52,9 @@ module ad_lvds_clk (
   localparam  SERIES7       = 0;
   localparam  VIRTEX6       = 1;
 
+  input     rst;
+  output    locked;
+
   input     clk_in_p;
   input     clk_in_n;
   output    clk;
@@ -57,6 +63,10 @@ module ad_lvds_clk (
 
   wire      clk_ibuf_s;
 
+  // defaults
+
+  assign locked <= 1'b1;
+
   // instantiations
 
   IBUFGDS i_rx_clk_ibuf (
diff --git a/library/common/altera/ad_cmos_clk.v b/library/common/altera/ad_cmos_clk.v
index 652a9dd75..fcedeb324 100644
--- a/library/common/altera/ad_cmos_clk.v
+++ b/library/common/altera/ad_cmos_clk.v
@@ -39,6 +39,9 @@
 
 module ad_cmos_clk (
 
+  rst,
+  locked,
+
   clk_in,
   clk);
 
@@ -46,16 +49,19 @@ module ad_cmos_clk (
   localparam  SERIES7       = 0;
   localparam  VIRTEX6       = 1;
 
+  input     rst;
+  output    locked;
+
   input     clk_in;
   output    clk;
 
   // instantiations
 
   alt_clk i_clk (
-    .rst (1'b0),
+    .rst (rst),
     .refclk (clk_in),
     .outclk_0 (clk),
-    .locked ());
+    .locked (locked));
 
 endmodule
 
diff --git a/library/common/altera/ad_cmos_in.v b/library/common/altera/ad_cmos_in.v
index 9737e4021..85b791926 100644
--- a/library/common/altera/ad_cmos_in.v
+++ b/library/common/altera/ad_cmos_in.v
@@ -93,7 +93,7 @@ module ad_cmos_in (
 
   // instantiations
 
-  alt_cmos_in i_rx_data_iddr (
+  alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in),
     .dout ({rx_data_p, rx_data_n}));
diff --git a/library/common/altera/ad_cmos_out.v b/library/common/altera/ad_cmos_out.v
index 4f877f0bb..46896e197 100644
--- a/library/common/altera/ad_cmos_out.v
+++ b/library/common/altera/ad_cmos_out.v
@@ -94,7 +94,7 @@ module ad_cmos_out (
 
   // instantiations
 
-  alt_cmos_out i_tx_data_oddr (
+  alt_ddio_out i_tx_data_oddr (
     .ck (tx_clk),
     .din ({tx_data_p, tx_data_n}),
     .pad_out (tx_data_out));
diff --git a/library/common/altera/ad_lvds_clk.v b/library/common/altera/ad_lvds_clk.v
index 12937f03e..6b7301ea9 100644
--- a/library/common/altera/ad_lvds_clk.v
+++ b/library/common/altera/ad_lvds_clk.v
@@ -39,12 +39,18 @@
 
 module ad_lvds_clk (
 
+  rst,
+  locked,
+
   clk_in_p,
   clk_in_n,
   clk);
 
   parameter   DEVICE_TYPE       = 0;
 
+  input     rst;
+  output    locked;
+
   input     clk_in_p;
   input     clk_in_n;
   output    clk;
@@ -52,10 +58,10 @@ module ad_lvds_clk (
   // instantiations
 
   alt_clk i_clk (
-    .rst (1'b0),
+    .rst (rst),
     .refclk (clk_in_p),
     .outclk_0 (clk),
-    .locked ());
+    .locked (locked));
 
 endmodule
 
diff --git a/library/common/altera/ad_lvds_in.v b/library/common/altera/ad_lvds_in.v
index 1313e52f8..7422234bd 100644
--- a/library/common/altera/ad_lvds_in.v
+++ b/library/common/altera/ad_lvds_in.v
@@ -95,10 +95,9 @@ module ad_lvds_in (
 
   // instantiations
 
-  alt_lvds_in i_rx_data_iddr (
+  alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in_p),
-    .pad_in_b (rx_data_in_n),
     .dout ({rx_data_p, rx_data_n}));
 
 endmodule
diff --git a/library/common/altera/ad_lvds_out.v b/library/common/altera/ad_lvds_out.v
index 05e8a87bc..dc673ac80 100644
--- a/library/common/altera/ad_lvds_out.v
+++ b/library/common/altera/ad_lvds_out.v
@@ -96,11 +96,10 @@ module ad_lvds_out (
 
   // instantiations
 
-  alt_lvds_out i_tx_data_oddr (
+  alt_ddio_out i_tx_data_oddr (
     .ck (tx_clk),
     .din ({tx_data_p, tx_data_n}),
-    .pad_out (tx_data_out_p),
-    .pad_out_b (tx_data_out_n));
+    .pad_out (tx_data_out_p));
 
 endmodule
 

From 1aac44b0d97f0c72b408ada21a43fc546bc18119 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:38:10 -0400
Subject: [PATCH 176/972] library: ad_*clk- rst/locked

---
 library/axi_ad9265/axi_ad9265_if.v | 2 ++
 library/axi_ad9467/axi_ad9467_if.v | 2 ++
 library/axi_ad9643/axi_ad9643_if.v | 2 ++
 library/axi_ad9652/axi_ad9652_if.v | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/library/axi_ad9265/axi_ad9265_if.v b/library/axi_ad9265/axi_ad9265_if.v
index ad6d41025..4225fa9f8 100644
--- a/library/axi_ad9265/axi_ad9265_if.v
+++ b/library/axi_ad9265/axi_ad9265_if.v
@@ -175,6 +175,8 @@ module axi_ad9265_if (
   ad_lvds_clk #(
     .DEVICE_TYPE (DEVICE_TYPE))
   i_adc_clk (
+    .rst (1'b0),
+    .locked (),
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk));
diff --git a/library/axi_ad9467/axi_ad9467_if.v b/library/axi_ad9467/axi_ad9467_if.v
index d4379eb3c..0886dc693 100644
--- a/library/axi_ad9467/axi_ad9467_if.v
+++ b/library/axi_ad9467/axi_ad9467_if.v
@@ -209,6 +209,8 @@ module axi_ad9467_if (
   ad_lvds_clk #(
     .DEVICE_TYPE (DEVICE_TYPE))
   i_adc_clk (
+    .rst (1'b0),
+    .locked (),
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk));
diff --git a/library/axi_ad9643/axi_ad9643_if.v b/library/axi_ad9643/axi_ad9643_if.v
index fd6600489..b46678775 100644
--- a/library/axi_ad9643/axi_ad9643_if.v
+++ b/library/axi_ad9643/axi_ad9643_if.v
@@ -245,6 +245,8 @@ module axi_ad9643_if (
   ad_lvds_clk #(
     .DEVICE_TYPE (DEVICE_TYPE))
   i_adc_clk (
+    .rst (1'b0),
+    .locked (),
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk));
diff --git a/library/axi_ad9652/axi_ad9652_if.v b/library/axi_ad9652/axi_ad9652_if.v
index 86075ddd6..ad422c0d7 100644
--- a/library/axi_ad9652/axi_ad9652_if.v
+++ b/library/axi_ad9652/axi_ad9652_if.v
@@ -214,6 +214,8 @@ module axi_ad9652_if (
   ad_lvds_clk #(
     .DEVICE_TYPE (DEVICE_TYPE))
   i_adc_clk (
+    .rst (1'b0),
+    .locked (),
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk));

From 16a13b2023781aad5b4e3f3339d93f8fee216175 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:38:53 -0400
Subject: [PATCH 177/972] library/axi_ad9361: add rst/locked to clock

---
 library/axi_ad9361/axi_ad9361_cmos_if.v | 14 +++++++++++++-
 library/axi_ad9361/axi_ad9361_lvds_if.v | 14 +++++++++++++-
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_cmos_if.v b/library/axi_ad9361/axi_ad9361_cmos_if.v
index a3dcf6f59..0e4997cba 100644
--- a/library/axi_ad9361/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/axi_ad9361_cmos_if.v
@@ -84,6 +84,7 @@ module axi_ad9361_cmos_if (
 
   // delay interface
 
+  mmcm_rst,
   up_clk,
   up_enable,
   up_txnrx,
@@ -148,6 +149,7 @@ module axi_ad9361_cmos_if (
 
   // delay interface
 
+  input           mmcm_rst;
   input           up_clk;
   input           up_enable;
   input           up_txnrx;
@@ -209,6 +211,8 @@ module axi_ad9361_cmos_if (
   reg             txnrx_n_int = 'd0;
   reg             enable_p_int = 'd0;
   reg             txnrx_p_int = 'd0;
+  reg             locked_m1 = 'd0;
+  reg             locked = 'd0;
 
   // internal signals
 
@@ -219,6 +223,7 @@ module axi_ad9361_cmos_if (
   wire    [11:0]  rx_data_n_s;
   wire            rx_frame_p_s;
   wire            rx_frame_n_s;
+  wire            locked_s;
 
   genvar          l_inst;
 
@@ -293,7 +298,7 @@ module axi_ad9361_cmos_if (
     if (adc_valid_int == 1'b1) begin
       adc_data <= adc_data_int;
     end
-    adc_status <= adc_status_int;
+    adc_status <= adc_status_int & locked;
   end
 
   // transmit data path mux (reverse of what receive does above)
@@ -550,9 +555,16 @@ module axi_ad9361_cmos_if (
 
   // device clock interface (receive clock)
 
+  always @(posedge clk) begin
+    locked_m1 <= locked_s;
+    locked <= locked_m1;
+  end
+
   ad_cmos_clk #(
     .DEVICE_TYPE (DEVICE_TYPE))
   i_clk (
+    .rst (mmcm_rst),
+    .locked (locked_s),
     .clk_in (rx_clk_in),
     .clk (l_clk));
 
diff --git a/library/axi_ad9361/axi_ad9361_lvds_if.v b/library/axi_ad9361/axi_ad9361_lvds_if.v
index e9a11cf07..56eb8ad6b 100644
--- a/library/axi_ad9361/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/axi_ad9361_lvds_if.v
@@ -90,6 +90,7 @@ module axi_ad9361_lvds_if (
 
   // delay interface
 
+  mmcm_rst,
   up_clk,
   up_enable,
   up_txnrx,
@@ -160,6 +161,7 @@ module axi_ad9361_lvds_if (
 
   // delay interface
 
+  input           mmcm_rst;
   input           up_clk;
   input           up_enable;
   input           up_txnrx;
@@ -225,6 +227,8 @@ module axi_ad9361_lvds_if (
   reg             txnrx_n_int = 'd0;
   reg             enable_p_int = 'd0;
   reg             txnrx_p_int = 'd0;
+  reg             locked_m1 = 'd0;
+  reg             locked = 'd0;
 
   // internal signals
 
@@ -235,6 +239,7 @@ module axi_ad9361_lvds_if (
   wire    [ 5:0]  rx_data_n_s;
   wire            rx_frame_p_s;
   wire            rx_frame_n_s;
+  wire            locked_s;
 
   genvar          l_inst;
 
@@ -326,7 +331,7 @@ module axi_ad9361_lvds_if (
     if (adc_valid_int == 1'b1) begin
       adc_data <= adc_data_int;
     end
-    adc_status <= adc_status_int;
+    adc_status <= adc_status_int & locked;
   end
 
   // transmit data path mux (reverse of what receive does above)
@@ -605,9 +610,16 @@ module axi_ad9361_lvds_if (
 
   // device clock interface (receive clock)
 
+  always @(posedge clk) begin
+    locked_m1 <= locked_s;
+    locked <= locked_m1;
+  end
+
   ad_lvds_clk #(
     .DEVICE_TYPE (DEVICE_TYPE))
   i_clk (
+    .rst (mmcm_rst),
+    .locked (locked_s),
     .clk_in_p (rx_clk_in_p),
     .clk_in_n (rx_clk_in_n),
     .clk (l_clk));

From 3b5e44e37daf3820b13289a68b5040f2ad42b846 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:39:26 -0400
Subject: [PATCH 178/972] library/axi_ad9361: mmcm rst for plls

---
 library/axi_ad9361/axi_ad9361.v    | 16 ++++++----------
 library/axi_ad9361/axi_ad9361_rx.v | 10 +++++++++-
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index a242ab42e..e3808214c 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -159,11 +159,7 @@ module axi_ad9361 (
   up_dac_gpio_in,
   up_dac_gpio_out,
   up_adc_gpio_in,
-  up_adc_gpio_out,
-
-  // chipscope signals
-
-  tdd_dbg);
+  up_adc_gpio_out);
 
   // parameters
 
@@ -297,10 +293,6 @@ module axi_ad9361 (
   input   [31:0]  up_adc_gpio_in;
   output  [31:0]  up_adc_gpio_out;
 
-  // chipscope signals
-
-  output  [41:0]  tdd_dbg;
-
   // internal registers
 
   reg             up_wack = 'd0;
@@ -315,6 +307,7 @@ module axi_ad9361 (
 
   wire            up_clk;
   wire            up_rstn;
+  wire            mmcm_rst;
   wire            delay_rst;
 
   // internal signals
@@ -423,6 +416,7 @@ module axi_ad9361 (
     .tdd_enable (tdd_enable_s),
     .tdd_txnrx (tdd_txnrx_s),
     .tdd_mode (tdd_mode_s),
+    .mmcm_rst (mmcm_rst),
     .up_clk (up_clk),
     .up_enable (up_enable),
     .up_txnrx (up_txnrx),
@@ -480,6 +474,7 @@ module axi_ad9361 (
     .tdd_enable (tdd_enable_s),
     .tdd_txnrx (tdd_txnrx_s),
     .tdd_mode (tdd_mode_s),
+    .mmcm_rst (mmcm_rst),
     .up_clk (up_clk),
     .up_enable (up_enable),
     .up_txnrx (up_txnrx),
@@ -558,7 +553,7 @@ module axi_ad9361 (
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata_tdd_s),
     .up_rack (up_rack_tdd_s),
-    .tdd_dbg (tdd_dbg));
+    .tdd_dbg ());
 
   // receive
 
@@ -566,6 +561,7 @@ module axi_ad9361 (
     .ID (ID),
     .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
   i_rx (
+    .mmcm_rst (mmcm_rst),
     .adc_rst (rst),
     .adc_clk (clk),
     .adc_valid (adc_valid_s),
diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v
index 22a699616..271b2138b 100644
--- a/library/axi_ad9361/axi_ad9361_rx.v
+++ b/library/axi_ad9361/axi_ad9361_rx.v
@@ -40,6 +40,10 @@
 
 module axi_ad9361_rx (
 
+  // common
+
+  mmcm_rst,
+
   // adc interface
 
   adc_rst,
@@ -100,6 +104,10 @@ module axi_ad9361_rx (
   parameter   DATAPATH_DISABLE = 0;
   parameter   ID = 0;
 
+  // common
+
+  output          mmcm_rst;
+
   // adc interface
 
   output          adc_rst;
@@ -335,7 +343,7 @@ module axi_ad9361_rx (
   // common processor control
 
   up_adc_common #(.ID (ID)) i_up_adc_common (
-    .mmcm_rst (),
+    .mmcm_rst (mmcm_rst),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_r1_mode (adc_r1_mode),

From ef6c99ecab95e6a7644a06b82e03e9786beee803 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:39:52 -0400
Subject: [PATCH 179/972] library/axi_ad9361: hw component updates

---
 library/axi_ad9361/axi_ad9361_hw.tcl | 201 ++++++++++++++++-----------
 1 file changed, 118 insertions(+), 83 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index b1b4c1e3d..a3c73dc11 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -73,13 +73,34 @@ set_parameter_property DEVICE_TYPE TYPE INTEGER
 set_parameter_property DEVICE_TYPE UNITS None
 set_parameter_property DEVICE_TYPE HDL_PARAMETER true
 
+add_parameter CMOS_OR_LVDS_N INTEGER 0
+set_parameter_property CMOS_OR_LVDS_N DEFAULT_VALUE 0
+set_parameter_property CMOS_OR_LVDS_N DISPLAY_NAME CMOS_OR_LVDS_N
+set_parameter_property CMOS_OR_LVDS_N TYPE INTEGER
+set_parameter_property CMOS_OR_LVDS_N UNITS None
+set_parameter_property CMOS_OR_LVDS_N HDL_PARAMETER true
+
+add_parameter DAC_DATAPATH_DISABLE INTEGER 0
+set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
+set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
+set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
+set_parameter_property DAC_DATAPATH_DISABLE UNITS None
+set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
+
+add_parameter ADC_DATAPATH_DISABLE INTEGER 0
+set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0
+set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE
+set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
+set_parameter_property ADC_DATAPATH_DISABLE UNITS None
+set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
+
 add_parameter DEVICE_FAMILY STRING 
 set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
 set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
 set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
 set_parameter_property DEVICE_FAMILY ENABLED false
 
-# axi4 slave
+# axi4 slave interface
 
 add_interface s_axi_clock clock end
 add_interface_port s_axi_clock s_axi_aclk clk Input 1
@@ -111,120 +132,134 @@ add_interface_port s_axi s_axi_rresp rresp Output 2
 add_interface_port s_axi s_axi_rdata rdata Output 32
 add_interface_port s_axi s_axi_rready rready Input 1
 
-# device interface
+# master-slave interface
 
-add_interface device_clock clock end
-add_interface_port device_clock clk clk Input 1
+ad_alt_intf signal dac_sync_in input 1
+ad_alt_intf signal dac_sync_out output 1
+ad_alt_intf signal tdd_sync input 1
+ad_alt_intf signal tdd_sync_cntr output 1
 
-add_interface device_if conduit end
-set_interface_property device_if associatedClock device_clock
-add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1
-add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1
-add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1
-add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1
-add_interface_port device_if rx_data_in_p rx_data_in_p Input 6
-add_interface_port device_if rx_data_in_n rx_data_in_n Input 6
-add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1
-add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1
-add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1
-add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1
-add_interface_port device_if tx_data_out_p tx_data_out_p Output 6
-add_interface_port device_if tx_data_out_n tx_data_out_n Output 6
-
-ad_alt_intf signal  dac_sync_in     input   1   sync
-ad_alt_intf signal  dac_sync_out    output  1   sync
-
-ad_alt_intf clock   l_clk           output  1
-ad_alt_intf reset   rst             output  1   if_l_clk
+ad_alt_intf clock delay_clk input 1
+ad_alt_intf clock l_clk output 1
+ad_alt_intf clock clk input 1
 
+ad_alt_intf reset rst output 1 if_clk
 set_interface_property if_rst associatedResetSinks none
 
 add_interface fifo_ch_0_in conduit end
-add_interface_port fifo_ch_0_in  adc_enable_i0 enable   Output  1
-add_interface_port fifo_ch_0_in  adc_valid_i0  valid    Output  1
-add_interface_port fifo_ch_0_in  adc_data_i0   data     Output  16
+add_interface_port fifo_ch_0_in adc_enable_i0 enable Output 1
+add_interface_port fifo_ch_0_in adc_valid_i0 valid Output 1
+add_interface_port fifo_ch_0_in adc_data_i0 data Output 16
 
 add_interface fifo_ch_1_in conduit end
-add_interface_port fifo_ch_1_in  adc_enable_q0 enable   Output  1
-add_interface_port fifo_ch_1_in  adc_valid_q0  valid    Output  1
-add_interface_port fifo_ch_1_in  adc_data_q0   data     Output  16
+add_interface_port fifo_ch_1_in adc_enable_q0 enable Output 1
+add_interface_port fifo_ch_1_in adc_valid_q0 valid Output 1
+add_interface_port fifo_ch_1_in adc_data_q0 data Output 16
 
 add_interface fifo_ch_2_in conduit end
-add_interface_port fifo_ch_2_in  adc_enable_i1 enable   Output  1
-add_interface_port fifo_ch_2_in  adc_valid_i1  valid    Output  1
-add_interface_port fifo_ch_2_in  adc_data_i1   data     Output  16
+add_interface_port fifo_ch_2_in adc_enable_i1 enable Output 1
+add_interface_port fifo_ch_2_in adc_valid_i1 valid Output 1
+add_interface_port fifo_ch_2_in adc_data_i1 data Output 16
 
 add_interface fifo_ch_3_in conduit end
-add_interface_port fifo_ch_3_in  adc_enable_q1 enable   Output  1
-add_interface_port fifo_ch_3_in  adc_valid_q1  valid    Output  1
-add_interface_port fifo_ch_3_in  adc_data_q1   data     Output  16
+add_interface_port fifo_ch_3_in adc_enable_q1 enable Output 1
+add_interface_port fifo_ch_3_in adc_valid_q1 valid Output 1
+add_interface_port fifo_ch_3_in adc_data_q1 data Output 16
 
-ad_alt_intf signal  adc_dovf        input  1   ovf
-ad_alt_intf signal  adc_dunf        input  1   unf
+ad_alt_intf signal adc_dovf input 1 ovf
+ad_alt_intf signal adc_dunf input 1 unf
+ad_alt_intf signal adc_r1_mode output 1 r1_mode
 
 add_interface fifo_ch_0_out conduit end
-add_interface_port fifo_ch_0_out  dac_enable_i0 enable   Output  1
-add_interface_port fifo_ch_0_out  dac_valid_i0  valid    Output  1
-add_interface_port fifo_ch_0_out  dac_data_i0   data     Input   16
+add_interface_port fifo_ch_0_out dac_enable_i0 enable Output 1
+add_interface_port fifo_ch_0_out dac_valid_i0 valid Output 1
+add_interface_port fifo_ch_0_out dac_data_i0 data Input 16
 
 add_interface fifo_ch_1_out conduit end
-add_interface_port fifo_ch_1_out  dac_enable_q0 enable   Output  1
-add_interface_port fifo_ch_1_out  dac_valid_q0  valid    Output  1
-add_interface_port fifo_ch_1_out  dac_data_q0   data     Input   16
+add_interface_port fifo_ch_1_out dac_enable_q0 enable Output 1
+add_interface_port fifo_ch_1_out dac_valid_q0 valid Output 1
+add_interface_port fifo_ch_1_out dac_data_q0 data Input 16
 
 add_interface fifo_ch_2_out conduit end
-add_interface_port fifo_ch_2_out  dac_enable_i1 enable   Output  1
-add_interface_port fifo_ch_2_out  dac_valid_i1  valid    Output  1
-add_interface_port fifo_ch_2_out  dac_data_i1   data     Input   16
+add_interface_port fifo_ch_2_out dac_enable_i1 enable Output 1
+add_interface_port fifo_ch_2_out dac_valid_i1 valid Output 1
+add_interface_port fifo_ch_2_out dac_data_i1 data Input 16
 
 add_interface fifo_ch_3_out conduit end
-add_interface_port fifo_ch_3_out  dac_enable_q1 enable   Output  1
-add_interface_port fifo_ch_3_out  dac_valid_q1  valid    Output  1
-add_interface_port fifo_ch_3_out  dac_data_q1   data     Input   16
+add_interface_port fifo_ch_3_out dac_enable_q1 enable Output 1
+add_interface_port fifo_ch_3_out dac_valid_q1 valid Output 1
+add_interface_port fifo_ch_3_out dac_data_q1 data Input 16
 
-ad_alt_intf signal  dac_dovf       input   1 ovf
-ad_alt_intf signal  dac_dunf       input   1 unf
+ad_alt_intf signal dac_dovf input 1 ovf
+ad_alt_intf signal dac_dunf input 1 unf
+ad_alt_intf signal dac_r1_mode output 1 r1_mode
 
-add_interface delay_clock clock end
-add_interface_port delay_clock delay_clk clk Input 1
+ad_alt_intf signal up_enable input 1
+ad_alt_intf signal up_txnrx input 1
+ad_alt_intf signal up_dac_gpio_in input 32
+ad_alt_intf signal up_dac_gpio_out output 32
+ad_alt_intf signal up_adc_gpio_in input 32
+ad_alt_intf signal up_adc_gpio_out output 32
 
-add_hdl_instance alt_lvds_in altera_gpio
-set_instance_parameter_value alt_lvds_in {PIN_TYPE_GUI} {Input}
-set_instance_parameter_value alt_lvds_in {SIZE} {1}
-set_instance_parameter_value alt_lvds_in {gui_diff_buff} {1}
-set_instance_parameter_value alt_lvds_in {gui_pseudo_diff} {0}
-set_instance_parameter_value alt_lvds_in {gui_io_reg_mode} {DDIO}
+# sub-modules
 
-add_hdl_instance alt_lvds_out altera_gpio
-set_instance_parameter_value alt_lvds_out {PIN_TYPE_GUI} {Output}
-set_instance_parameter_value alt_lvds_out {SIZE} {1}
-set_instance_parameter_value alt_lvds_out {gui_diff_buff} {1}
-set_instance_parameter_value alt_lvds_out {gui_pseudo_diff} {0}
-set_instance_parameter_value alt_lvds_out {gui_io_reg_mode} {DDIO}
+add_hdl_instance alt_ddio_in altera_gpio
+set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
+set_instance_parameter_value alt_ddio_in {SIZE} {1}
+set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
+set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
 
-add_hdl_instance alt_cmos_in altera_gpio
-set_instance_parameter_value alt_cmos_in {PIN_TYPE_GUI} {Input}
-set_instance_parameter_value alt_cmos_in {SIZE} {1}
-set_instance_parameter_value alt_cmos_in {gui_diff_buff} {0}
-set_instance_parameter_value alt_cmos_in {gui_pseudo_diff} {0}
-set_instance_parameter_value alt_cmos_in {gui_io_reg_mode} {DDIO}
+add_hdl_instance alt_ddio_out altera_gpio
+set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
+set_instance_parameter_value alt_ddio_out {SIZE} {1}
+set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
+set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
 
-add_hdl_instance alt_cmos_out altera_gpio
-set_instance_parameter_value alt_cmos_out {PIN_TYPE_GUI} {Output}
-set_instance_parameter_value alt_cmos_out {SIZE} {1}
-set_instance_parameter_value alt_cmos_out {gui_diff_buff} {0}
-set_instance_parameter_value alt_cmos_out {gui_pseudo_diff} {0}
-set_instance_parameter_value alt_cmos_out {gui_io_reg_mode} {DDIO}
+# updates
 
 proc p_axi_ad9361 {} {
 
-  set ALTERA_DEVICE_TYPE [get_parameter_value DEVICE_TYPE]
-  set ALTERA_DEVICE_FAMILY [get_parameter_value DEVICE_FAMILY]
+  set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N]
+  set m_device_type [get_parameter_value DEVICE_TYPE]
+  set m_device_family [get_parameter_value DEVICE_FAMILY]
 
-  if {$ALTERA_DEVICE_TYPE == 1} {
+  add_interface device_if conduit end
+  set_interface_property device_if associatedClock none
+  set_interface_property device_if associatedReset none
+
+  if {$m_cmos_or_lvds_n == 1} {
+
+    add_interface_port device_if rx_clk_in rx_clk_in_p Input 1
+    add_interface_port device_if rx_frame_in rx_frame_in_p Input 1
+    add_interface_port device_if rx_data_in rx_data_in_p Input 12
+    add_interface_port device_if tx_clk_out tx_clk_out_p Output 1
+    add_interface_port device_if tx_frame_out tx_frame_out_p Output 1
+    add_interface_port device_if tx_data_out tx_data_out_p Output 12
   }
 
-  if {$ALTERA_DEVICE_TYPE == 0} {
+  if {$m_cmos_or_lvds_n == 0} {
+
+    add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1
+    add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1
+    add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1
+    add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1
+    add_interface_port device_if rx_data_in_p rx_data_in_p Input 6
+    add_interface_port device_if rx_data_in_n rx_data_in_n Input 6
+    add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1
+    add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1
+    add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1
+    add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1
+    add_interface_port device_if tx_data_out_p tx_data_out_p Output 6
+    add_interface_port device_if tx_data_out_n tx_data_out_n Output 6
+  }
+
+  add_interface_port device_if enable enable Output 1
+  add_interface_port device_if txnrx txnrx Output 1
+
+  if {$m_device_type == 1} {
+  }
+
+  if {$m_device_type == 0} {
 
     add_hdl_instance alt_clk altera_iopll
     set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
@@ -234,7 +269,7 @@ proc p_axi_ad9361 {} {
     set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
     set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
     set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
-    set_instance_parameter_value alt_clk {system_info_device_family} $ALTERA_DEVICE_FAMILY
+    set_instance_parameter_value alt_clk {system_info_device_family} $m_device_family
   }
 }
 

From bdfa383622d8db1a681b168425964ef854296424 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:40:09 -0400
Subject: [PATCH 180/972] library/axi_ad9361: tdd false paths

---
 library/axi_ad9361/axi_ad9361_constr.sdc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/library/axi_ad9361/axi_ad9361_constr.sdc b/library/axi_ad9361/axi_ad9361_constr.sdc
index 158259284..5c47199cc 100644
--- a/library/axi_ad9361/axi_ad9361_constr.sdc
+++ b/library/axi_ad9361/axi_ad9361_constr.sdc
@@ -1,4 +1,7 @@
 
 set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*]
 set_false_path -from [get_registers *i_dev_if|up_txnrx_int*]  -to [get_registers *i_dev_if|txnrx_up_m1*]
+set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle*]   -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_state_m1*]
+set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_toggle*]  -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle_m1*]
+set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_data*]    -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_data_cntrl*]
 

From 92dcce16740a82cba0b44650f180302d17623d48 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:40:55 -0400
Subject: [PATCH 181/972] a10soc: default ports

---
 .../common/a10soc/a10soc_system_assign.tcl    | 148 +++++++-----------
 1 file changed, 60 insertions(+), 88 deletions(-)

diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
index fe465eb13..01f67d323 100755
--- a/projects/common/a10soc/a10soc_system_assign.tcl
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -99,31 +99,31 @@ set_location_assignment PIN_E26   -to hps_ddr_rzq
 
 set_location_assignment PIN_F18   -to hps_eth_rxclk
 set_location_assignment PIN_G17   -to hps_eth_rxctl
-set_location_assignment PIN_G20   -to hps_eth_rxd0
-set_location_assignment PIN_G21   -to hps_eth_rxd1
-set_location_assignment PIN_F22   -to hps_eth_rxd2
-set_location_assignment PIN_G22   -to hps_eth_rxd3
+set_location_assignment PIN_G20   -to hps_eth_rxd[0]
+set_location_assignment PIN_G21   -to hps_eth_rxd[1]
+set_location_assignment PIN_F22   -to hps_eth_rxd[2]
+set_location_assignment PIN_G22   -to hps_eth_rxd[3]
 set_location_assignment PIN_H18   -to hps_eth_txclk
 set_location_assignment PIN_H19   -to hps_eth_txctl
-set_location_assignment PIN_E20   -to hps_eth_txd0
-set_location_assignment PIN_F20   -to hps_eth_txd1
-set_location_assignment PIN_F19   -to hps_eth_txd2
-set_location_assignment PIN_G19   -to hps_eth_txd3
+set_location_assignment PIN_E20   -to hps_eth_txd[0]
+set_location_assignment PIN_F20   -to hps_eth_txd[1]
+set_location_assignment PIN_F19   -to hps_eth_txd[2]
+set_location_assignment PIN_G19   -to hps_eth_txd[3]
 set_location_assignment PIN_K20   -to hps_eth_mdc
 set_location_assignment PIN_K21   -to hps_eth_mdio
 
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxclk
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxctl
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd0
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd1
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd2
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd3
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd[3]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txclk
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txctl
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd0
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd1
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd2
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd3
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd[3]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_mdc
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_mdio
 
@@ -133,42 +133,42 @@ set_instance_assignment -name OUTPUT_DELAY_CHAIN 8 -to hps_eth_txclk
 
 set_location_assignment PIN_K16   -to hps_sdio_clk
 set_location_assignment PIN_H16   -to hps_sdio_cmd
-set_location_assignment PIN_E16   -to hps_sdio_d0
-set_location_assignment PIN_G16   -to hps_sdio_d1
-set_location_assignment PIN_H17   -to hps_sdio_d2
-set_location_assignment PIN_F15   -to hps_sdio_d3
-set_location_assignment PIN_M19   -to hps_sdio_d4
-set_location_assignment PIN_E15   -to hps_sdio_d5
-set_location_assignment PIN_J16   -to hps_sdio_d6
-set_location_assignment PIN_L18   -to hps_sdio_d7
+set_location_assignment PIN_E16   -to hps_sdio_d[0]
+set_location_assignment PIN_G16   -to hps_sdio_d[1]
+set_location_assignment PIN_H17   -to hps_sdio_d[2]
+set_location_assignment PIN_F15   -to hps_sdio_d[3]
+set_location_assignment PIN_M19   -to hps_sdio_d[4]
+set_location_assignment PIN_E15   -to hps_sdio_d[5]
+set_location_assignment PIN_J16   -to hps_sdio_d[6]
+set_location_assignment PIN_L18   -to hps_sdio_d[7]
 
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_clk
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_cmd
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d0
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d1
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d2
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d3
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d4
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d5
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d6
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d7
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[7]
 
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_clk
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_cmd
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d2
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d3
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d4
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d5
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d6
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d7
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[7]
 set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_clk
 set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_cmd
-set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d0
-set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d1
-set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d2
-set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d3
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d[0]
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d[1]
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d[2]
+set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d[3]
 
 # hps-usb
 
@@ -176,27 +176,27 @@ set_location_assignment PIN_D18   -to hps_usb_clk
 set_location_assignment PIN_C19   -to hps_usb_dir
 set_location_assignment PIN_F17   -to hps_usb_nxt
 set_location_assignment PIN_E18   -to hps_usb_stp
-set_location_assignment PIN_D19   -to hps_usb_d0
-set_location_assignment PIN_E17   -to hps_usb_d1
-set_location_assignment PIN_C17   -to hps_usb_d2
-set_location_assignment PIN_C18   -to hps_usb_d3
-set_location_assignment PIN_D21   -to hps_usb_d4
-set_location_assignment PIN_D20   -to hps_usb_d5
-set_location_assignment PIN_E21   -to hps_usb_d6
-set_location_assignment PIN_E22   -to hps_usb_d7
+set_location_assignment PIN_D19   -to hps_usb_d[0]
+set_location_assignment PIN_E17   -to hps_usb_d[1]
+set_location_assignment PIN_C17   -to hps_usb_d[2]
+set_location_assignment PIN_C18   -to hps_usb_d[3]
+set_location_assignment PIN_D21   -to hps_usb_d[4]
+set_location_assignment PIN_D20   -to hps_usb_d[5]
+set_location_assignment PIN_E21   -to hps_usb_d[6]
+set_location_assignment PIN_E22   -to hps_usb_d[7]
 
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_clk
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_dir
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_nxt
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_stp
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d0
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d1
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d2
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d3
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d4
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d5
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d6
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d7
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[7]
 
 # hps-uart
 
@@ -214,20 +214,6 @@ set_location_assignment PIN_L20   -to hps_i2c_sda
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c_scl
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c_sda
 
-# hps-spi (max-v-u16)
-
-set_location_assignment PIN_H21   -to hps_spi_cs0_n
-set_location_assignment PIN_J21   -to hps_spi_cs1_n
-set_location_assignment PIN_K18   -to hps_spi_clk
-set_location_assignment PIN_L19   -to hps_spi_mosi
-set_location_assignment PIN_H22   -to hps_spi_miso
-
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_cs0_n
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_cs1_n
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_clk
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_mosi
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spi_miso
-
 # gpio (max-v-u21)
 
 set_location_assignment PIN_AR23  -to gpio_bd_o[0]  ; ## led[0]
@@ -268,20 +254,6 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[1]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[2]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[3]
 
-# hps-trace
-
-set_location_assignment PIN_P20   -to hps_trace_clk
-set_location_assignment PIN_K22   -to hps_trace_d0
-set_location_assignment PIN_L22   -to hps_trace_d1
-set_location_assignment PIN_M22   -to hps_trace_d2
-set_location_assignment PIN_M21   -to hps_trace_d3
-
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_clk
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_d0
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_d1
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_d2
-set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_d3
-
 # globals
 
 set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO

From f4e5965936d45f51e28c0f14436d0e9fb4f1c601 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:41:25 -0400
Subject: [PATCH 182/972] fmcomms2/a10soc: ip updates

---
 projects/fmcomms2/common/fmcomms2_bd.qsys | 66 ++++++++++-------------
 1 file changed, 27 insertions(+), 39 deletions(-)

diff --git a/projects/fmcomms2/common/fmcomms2_bd.qsys b/projects/fmcomms2/common/fmcomms2_bd.qsys
index 8656a32da..d7daaf622 100755
--- a/projects/fmcomms2/common/fmcomms2_bd.qsys
+++ b/projects/fmcomms2/common/fmcomms2_bd.qsys
@@ -9,19 +9,11 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element ad9361_clk_bridge
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
    element adc_pack
    {
       datum _sortIndex
       {
-         value = "4";
+         value = "3";
          type = "int";
       }
       datum sopceditor_expanded
@@ -90,7 +82,7 @@
    {
       datum _sortIndex
       {
-         value = "3";
+         value = "2";
          type = "int";
       }
       datum sopceditor_expanded
@@ -111,7 +103,7 @@
    {
       datum _sortIndex
       {
-         value = "5";
+         value = "4";
          type = "int";
       }
       datum sopceditor_expanded
@@ -132,7 +124,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "6";
          type = "int";
       }
       datum sopceditor_expanded
@@ -153,7 +145,7 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "5";
          type = "int";
       }
       datum sopceditor_expanded
@@ -200,25 +192,31 @@
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
-   name="axi_ad9361_device_clock"
-   internal="axi_ad9361.device_clock"
+   name="axi_ad9361_delay_clk"
+   internal="axi_ad9361.if_delay_clk"
    type="clock"
    dir="end" />
+ <interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
  <interface
    name="axi_ad9361_device_if"
    internal="axi_ad9361.device_if"
    type="conduit"
    dir="end" />
- <interface
-   name="axi_ad9361_l_clk"
-   internal="ad9361_clk_bridge.out_clk"
-   type="clock"
-   dir="start" />
  <interface
    name="axi_ad9361_s_axi"
    internal="axi_ad9361.s_axi"
    type="axi4lite"
    dir="end" />
+ <interface
+   name="axi_ad9361_up_enable"
+   internal="axi_ad9361.if_up_enable"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9361_up_txnrx"
+   internal="axi_ad9361.if_up_txnrx"
+   type="conduit"
+   dir="end" />
  <interface
    name="axi_dmac_adc_fifo_wr_clock"
    internal="axi_dmac_adc.fifo_wr_clock" />
@@ -259,20 +257,15 @@
    dir="end" />
  <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
  <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <module
-   name="ad9361_clk_bridge"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
  <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
   <parameter name="CHANNEL_DATA_WIDTH" value="16" />
   <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
  <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
+  <parameter name="ADC_DATAPATH_DISABLE" value="0" />
+  <parameter name="CMOS_OR_LVDS_N" value="0" />
+  <parameter name="DAC_DATAPATH_DISABLE" value="0" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
   <parameter name="DEVICE_TYPE" value="0" />
   <parameter name="ID" value="0" />
  </module>
@@ -331,6 +324,11 @@
    version="15.1"
    start="axi_ad9361.if_l_clk"
    end="adc_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="axi_ad9361.if_l_clk"
+   end="axi_ad9361.if_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -346,16 +344,6 @@
    version="15.1"
    start="axi_ad9361.if_l_clk"
    end="axi_dmac_adc.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="ad9361_clk_bridge.in_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9361.delay_clock" />
  <connection
    kind="clock"
    version="15.1"

From ddfaff2cf5c59c15f9562d0c6243644bb1df4cde Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 May 2016 13:42:01 -0400
Subject: [PATCH 183/972] fmcomms2/a10soc: compile version

---
 projects/fmcomms2/a10soc/system_bd.qsys     |  42 ++-
 projects/fmcomms2/a10soc/system_constr.sdc  |  38 +-
 projects/fmcomms2/a10soc/system_project.tcl | 115 ++++++
 projects/fmcomms2/a10soc/system_top.v       | 392 +++++++++-----------
 4 files changed, 326 insertions(+), 261 deletions(-)

diff --git a/projects/fmcomms2/a10soc/system_bd.qsys b/projects/fmcomms2/a10soc/system_bd.qsys
index 97b293a4e..72d7386ca 100755
--- a/projects/fmcomms2/a10soc/system_bd.qsys
+++ b/projects/fmcomms2/a10soc/system_bd.qsys
@@ -315,6 +315,11 @@
    internal="fmcomms2.axi_ad9361_device_if"
    type="conduit"
    dir="end" />
+ <interface
+   name="delay_clk"
+   internal="fmcomms2.axi_ad9361_delay_clk"
+   type="clock"
+   dir="end" />
  <interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
  <interface
    name="hps_ddr_oct"
@@ -346,27 +351,37 @@
    internal="sys_clk.clk_in_reset"
    type="reset"
    dir="end" />
+ <interface
+   name="up_enable"
+   internal="fmcomms2.axi_ad9361_up_enable"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="up_txnrx"
+   internal="fmcomms2.axi_ad9361_up_txnrx"
+   type="conduit"
+   dir="end" />
  <module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
   <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="4" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="2" />
   <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="4" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="2" />
   <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
   <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
-  <parameter name="AUTO_UNIQUE_ID" value="system_bd_a10soc" />
+  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
  </module>
  <module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_DOMAIN" value="2" />
-  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_RESET_DOMAIN" value="2" />
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
   <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
@@ -379,10 +394,10 @@
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
-  <parameter name="AUTO_UNIQUE_ID" value="system_bd_fmcomms2" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
+  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
  </module>
  <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
@@ -435,11 +450,6 @@
   <parameter name="baseAddress" value="0x00010000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection
-   kind="clock"
-   version="15.1"
-   start="fmcomms2.axi_ad9361_l_clk"
-   end="fmcomms2.axi_ad9361_device_clock" />
  <connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
  <connection
    kind="clock"
diff --git a/projects/fmcomms2/a10soc/system_constr.sdc b/projects/fmcomms2/a10soc/system_constr.sdc
index 7ec6b3f16..1f9b3d462 100644
--- a/projects/fmcomms2/a10soc/system_constr.sdc
+++ b/projects/fmcomms2/a10soc/system_constr.sdc
@@ -1,43 +1,7 @@
 
 create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
-create_clock -period "2.000 ns"   -name rx_ref_clk_500mhz   [get_ports {rx_ref_clk}]
-create_clock -period "2.000 ns"   -name tx_ref_clk_500mhz   [get_ports {tx_ref_clk}]
+create_clock -period  "4.000 ns"  -name rx_clk_250mhz       [get_ports {rx_clk_in}]
 
 derive_pll_clocks
 derive_clock_uncertainty
 
-set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
- 
-set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
-
-set_false_path -from [get_clocks {sys_clk_100mhz}]\
-  -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
-
-set_false_path -from [get_clocks {sys_clk_100mhz}]\
-  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
-
-set_false_path -from [get_clocks {sys_clk_100mhz}]\
-  -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]
-
-set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
-  -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {sys_clk_100mhz}]
-
-set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
-  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {sys_clk_100mhz}]
-
-set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]\
-  -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {sys_clk_100mhz}]
-
diff --git a/projects/fmcomms2/a10soc/system_project.tcl b/projects/fmcomms2/a10soc/system_project.tcl
index 561871428..83b8cdf94 100644
--- a/projects/fmcomms2/a10soc/system_project.tcl
+++ b/projects/fmcomms2/a10soc/system_project.tcl
@@ -11,5 +11,120 @@ set_global_assignment -name VERILOG_FILE system_top.v
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
 
+# data-path
+
+set_location_assignment PIN_G14   -to rx_clk_in             ; ## G6   FMC_LPC_LA00_CC_P
+set_location_assignment PIN_H14   -to "rx_clk_in(n)"        ; ## G7   FMC_LPC_LA00_CC_N
+set_location_assignment PIN_E12   -to rx_frame_in           ; ## D8   FMC_LPC_LA01_CC_P
+set_location_assignment PIN_E13   -to "rx_frame_in(n)"      ; ## D9   FMC_LPC_LA01_CC_N
+set_location_assignment PIN_C13   -to rx_data_in[0]         ; ## H7   FMC_LPC_LA02_P
+set_location_assignment PIN_D13   -to "rx_data_in[0](n)"    ; ## H8   FMC_LPC_LA02_N
+set_location_assignment PIN_C14   -to rx_data_in[1]         ; ## G9   FMC_LPC_LA03_P
+set_location_assignment PIN_D14   -to "rx_data_in[1](n)"    ; ## G10  FMC_LPC_LA03_N
+set_location_assignment PIN_H12   -to rx_data_in[2]         ; ## H10  FMC_LPC_LA04_P
+set_location_assignment PIN_H13   -to "rx_data_in[2](n)"    ; ## H11  FMC_LPC_LA04_N
+set_location_assignment PIN_F13   -to rx_data_in[3]         ; ## D11  FMC_LPC_LA05_P
+set_location_assignment PIN_F14   -to "rx_data_in[3](n)"    ; ## D12  FMC_LPC_LA05_N
+set_location_assignment PIN_A10   -to rx_data_in[4]         ; ## C10  FMC_LPC_LA06_P
+set_location_assignment PIN_B10   -to "rx_data_in[4](n)"    ; ## C11  FMC_LPC_LA06_N
+set_location_assignment PIN_A9    -to rx_data_in[5]         ; ## H13  FMC_LPC_LA07_P
+set_location_assignment PIN_B9    -to "rx_data_in[5](n)"    ; ## H14  FMC_LPC_LA07_N
+set_location_assignment PIN_B11   -to tx_clk_out            ; ## G12  FMC_LPC_LA08_P
+set_location_assignment PIN_B12   -to "tx_clk_out(n)"       ; ## G13  FMC_LPC_LA08_N
+set_location_assignment PIN_A12   -to tx_frame_out          ; ## D14  FMC_LPC_LA09_P
+set_location_assignment PIN_A13   -to "tx_frame_out(n)"     ; ## D15  FMC_LPC_LA09_N
+set_location_assignment PIN_C9    -to tx_data_out[0]        ; ## H16  FMC_LPC_LA11_P
+set_location_assignment PIN_D9    -to "tx_data_out[0](n)"   ; ## H17  FMC_LPC_LA11_N
+set_location_assignment PIN_M12   -to tx_data_out[1]        ; ## G15  FMC_LPC_LA12_P
+set_location_assignment PIN_N13   -to "tx_data_out[1](n)"   ; ## G16  FMC_LPC_LA12_N
+set_location_assignment PIN_J11   -to tx_data_out[2]        ; ## D17  FMC_LPC_LA13_P
+set_location_assignment PIN_K11   -to "tx_data_out[2](n)"   ; ## D18  FMC_LPC_LA13_N
+set_location_assignment PIN_A7    -to tx_data_out[3]        ; ## C14  FMC_LPC_LA10_P
+set_location_assignment PIN_A8    -to "tx_data_out[3](n)"   ; ## C15  FMC_LPC_LA10_N
+set_location_assignment PIN_J9    -to tx_data_out[4]        ; ## C18  FMC_LPC_LA14_P
+set_location_assignment PIN_J10   -to "tx_data_out[4](n)"   ; ## C19  FMC_LPC_LA14_N
+set_location_assignment PIN_D4    -to tx_data_out[5]        ; ## H19  FMC_LPC_LA15_P
+set_location_assignment PIN_D5    -to "tx_data_out[5](n)"   ; ## H20  FMC_LPC_LA15_N
+
+set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
+set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[1]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[2]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[3]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[4]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[5]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_clk_out
+set_instance_assignment -name IO_STANDARD LVDS -to tx_frame_out
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[0]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[1]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5]
+
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_clk_in
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_frame_in
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[0]
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[1]
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[2]
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[3]
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[4]
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[5]
+
+# ensm/tdd control
+
+set_location_assignment PIN_D6    -to enable                ; ## G18  FMC_LPC_LA16_P
+set_location_assignment PIN_E6    -to txnrx                 ; ## G19  FMC_LPC_LA16_N
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to enable
+set_instance_assignment -name IO_STANDARD "1.8 V" -to txnrx
+
+# control & status
+
+set_location_assignment PIN_C3    -to gpio_status[0]        ; ## G21  FMC_LPC_LA20_P
+set_location_assignment PIN_C4    -to gpio_status[1]        ; ## G22  FMC_LPC_LA20_N
+set_location_assignment PIN_C2    -to gpio_status[2]        ; ## H25  FMC_LPC_LA21_P
+set_location_assignment PIN_D3    -to gpio_status[3]        ; ## H26  FMC_LPC_LA21_N
+set_location_assignment PIN_F4    -to gpio_status[4]        ; ## G24  FMC_LPC_LA22_P
+set_location_assignment PIN_G4    -to gpio_status[5]        ; ## G25  FMC_LPC_LA22_N
+set_location_assignment PIN_C1    -to gpio_status[6]        ; ## D23  FMC_LPC_LA23_P
+set_location_assignment PIN_D1    -to gpio_status[7]        ; ## D24  FMC_LPC_LA23_N
+set_location_assignment PIN_E1    -to gpio_ctl[0]           ; ## H28  FMC_LPC_LA24_P
+set_location_assignment PIN_E2    -to gpio_ctl[1]           ; ## H29  FMC_LPC_LA24_N
+set_location_assignment PIN_E3    -to gpio_ctl[2]           ; ## G27  FMC_LPC_LA25_P
+set_location_assignment PIN_F3    -to gpio_ctl[3]           ; ## G28  FMC_LPC_LA25_N
+set_location_assignment PIN_G5    -to gpio_en_agc           ; ## H22  FMC_LPC_LA19_P
+set_location_assignment PIN_G6    -to gpio_sync             ; ## H23  FMC_LPC_LA19_N
+set_location_assignment PIN_L5    -to gpio_resetb           ; ## H31  FMC_LPC_LA28_P
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[0]    
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[1]    
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[2]    
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[3]    
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[4]    
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[5]    
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[6]    
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[7]    
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[0]       
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[1]       
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[2]       
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[3]       
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_en_agc       
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_sync         
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_resetb       
+
+# spi
+
+set_location_assignment PIN_F2    -to spi_csn               ; ## D26  FMC_LPC_LA26_P
+set_location_assignment PIN_G2    -to spi_clk               ; ## D27  FMC_LPC_LA26_N
+set_location_assignment PIN_G1    -to spi_mosi              ; ## C26  FMC_LPC_LA27_P
+set_location_assignment PIN_H2    -to spi_miso              ; ## C27  FMC_LPC_LA27_N
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
+
 execute_flow -compile
 
diff --git a/projects/fmcomms2/a10soc/system_top.v b/projects/fmcomms2/a10soc/system_top.v
index 7e3d0bfb1..e4211a457 100644
--- a/projects/fmcomms2/a10soc/system_top.v
+++ b/projects/fmcomms2/a10soc/system_top.v
@@ -41,246 +41,222 @@ module system_top (
 
   // clock and resets
 
-  sys_clk,
-  sys_resetn,
+  input             sys_clk,
+  input             sys_resetn,
 
-  // ddr3
+  // hps-ddr4 (32)
 
-  ddr3_clk_p,
-  ddr3_clk_n,
-  ddr3_a,
-  ddr3_ba,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_odt,
-  ddr3_reset_n,
-  ddr3_we_n,
-  ddr3_ras_n,
-  ddr3_cas_n,
-  ddr3_dqs_p,
-  ddr3_dqs_n,
-  ddr3_dq,
-  ddr3_dm,
-  ddr3_rzq,
-  ddr3_ref_clk,
+  input             hps_ddr_ref_clk,
+  output  [  0:0]   hps_ddr_clk_p,
+  output  [  0:0]   hps_ddr_clk_n,
+  output  [ 16:0]   hsp_ddr_a,
+  output  [  1:0]   hps_ddr_ba,
+  output  [  0:0]   hps_ddr_bg,
+  output  [  0:0]   hps_ddr_cke,
+  output  [  0:0]   hps_ddr_cs_n,
+  output  [  0:0]   hps_ddr_odt,
+  output  [  0:0]   hps_ddr_reset_n,
+  output  [  0:0]   hps_ddr_act_n,
+  output  [  0:0]   hps_ddr_par,
+  input   [  0:0]   hps_ddr_alert_n,
+  inout   [  3:0]   hps_ddr_dqs_p,
+  inout   [  3:0]   hps_ddr_dqs_n,
+  inout   [ 31:0]   hps_ddr_dq,
+  inout   [  3:0]   hps_ddr_dbi_n,
+  input             hps_ddr_rzq,
 
-  // ethernet
+  // hps-ethernet
 
-  eth_ref_clk,
-  eth_rxd,
-  eth_txd,
-  eth_mdc,
-  eth_mdio,
-  eth_resetn,
-  eth_intn,
+  input   [  0:0]   hps_eth_rxclk,
+  input   [  0:0]   hps_eth_rxctl,
+  input   [  3:0]   hps_eth_rxd,
+  output  [  0:0]   hps_eth_txclk,
+  output  [  0:0]   hps_eth_txctl,
+  output  [  3:0]   hps_eth_txd,
+  output  [  0:0]   hps_eth_mdc,
+  inout   [  0:0]   hps_eth_mdio,
 
-  // board gpio
+  // hps-sdio
 
-  gpio_bd_i,
-  gpio_bd_o,
+  output  [  0:0]   hps_sdio_clk,
+  inout   [  0:0]   hps_sdio_cmd,
+  inout   [  7:0]   hps_sdio_d,
 
-  // lane interface
+  // hps-usb
 
-  rx_ref_clk,
-  rx_sysref,
-  rx_sync,
-  rx_data,
-  tx_ref_clk,
-  tx_sysref,
-  tx_sync,
-  tx_data,
+  input   [  0:0]   hps_usb_clk,
+  input   [  0:0]   hps_usb_dir,
+  input   [  0:0]   hps_usb_nxt,
+  output  [  0:0]   hps_usb_stp,
+  inout   [  7:0]   hps_usb_d,
 
-  // gpio
+  // hps-uart
 
-  trig,
-  adc_fdb,
-  adc_fda,
-  dac_irq,
-  clkd_status,
-  adc_pd,
-  dac_txen,
-  dac_reset,
-  clkd_sync,
+  input   [  0:0]   hps_uart_rx,
+  output  [  0:0]   hps_uart_tx,
 
-  // spi
+  // hps-i2c (shared w fmc-a, fmc-b)
 
-  spi_csn_clk,
-  spi_csn_dac,
-  spi_csn_adc,
-  spi_clk,
-  spi_sdio,
-  spi_dir);
+  inout   [  0:0]   hps_i2c_sda,
+  inout   [  0:0]   hps_i2c_scl,
 
-  // clock and resets
+  // hps-gpio (max-v-u16)
 
-  input             sys_clk;
-  input             sys_resetn;
+  inout   [  3:0]   hps_gpio,
+          
+  // gpio (max-v-u21)
 
-  // ddr3
+  input   [  7:0]   gpio_bd_i,
+  output  [  3:0]   gpio_bd_o,
 
-  output            ddr3_clk_p;
-  output            ddr3_clk_n;
-  output  [ 14:0]   ddr3_a;
-  output  [  2:0]   ddr3_ba;
-  output            ddr3_cke;
-  output            ddr3_cs_n;
-  output            ddr3_odt;
-  output            ddr3_reset_n;
-  output            ddr3_we_n;
-  output            ddr3_ras_n;
-  output            ddr3_cas_n;
-  inout   [  7:0]   ddr3_dqs_p;
-  inout   [  7:0]   ddr3_dqs_n;
-  inout   [ 63:0]   ddr3_dq;
-  output  [  7:0]   ddr3_dm;
-  input             ddr3_rzq;
-  input             ddr3_ref_clk;
+  // ad9361-interface
 
-  // ethernet
+  input             rx_clk_in,
+  input             rx_frame_in,
+  input   [  5:0]   rx_data_in,
+  output            tx_clk_out,
+  output            tx_frame_out,
+  output  [  5:0]   tx_data_out,
+  output            enable,
+  output            txnrx,
 
-  input             eth_ref_clk;
-  input             eth_rxd;
-  output            eth_txd;
-  output            eth_mdc;
-  inout             eth_mdio;
-  output            eth_resetn;
-  input             eth_intn;
+  output            gpio_resetb,
+  output            gpio_sync,
+  output            gpio_en_agc,
+  output  [  3:0]   gpio_ctl,
+  input   [  7:0]   gpio_status,
 
-  // board gpio
-
-  input   [ 10:0]   gpio_bd_i;
-  output  [ 15:0]   gpio_bd_o;
-
-  // lane interface
-
-  input             rx_ref_clk;
-  input             rx_sysref;
-  output            rx_sync;
-  input   [  3:0]   rx_data;
-  input             tx_ref_clk;
-  input             tx_sysref;
-  input             tx_sync;
-  output  [  3:0]   tx_data;
-
-  // gpio
-
-  input             trig;
-  input             adc_fdb;
-  input             adc_fda;
-  input             dac_irq;
-  input   [  1:0]   clkd_status;
-  output            adc_pd;
-  output            dac_txen;
-  output            dac_reset;
-  output            clkd_sync;
-
-  // spi
-
-  output            spi_csn_clk;
-  output            spi_csn_dac;
-  output            spi_csn_adc;
-  output            spi_clk;
-  inout             spi_sdio;
-  output            spi_dir;
+  output            spi_csn,
+  output            spi_clk,
+  output            spi_mosi,
+  input             spi_miso);
 
   // internal signals
 
-  wire              eth_reset;
-  wire              eth_mdio_i;
-  wire              eth_mdio_o;
-  wire              eth_mdio_t;
-  wire    [ 63:0]   gpio_i;
-  wire    [ 63:0]   gpio_o;
-  wire              spi_miso_s;
-  wire              spi_mosi_s;
-  wire    [  7:0]   spi_csn_s;
+  wire    [ 31:0]   gpio_i;
+  wire    [ 31:0]   gpio_o;
 
-  // daq2
+  // gpio (ad9361)
 
-  assign spi_csn_adc = spi_csn_s[2];
-  assign spi_csn_dac = spi_csn_s[1];
-  assign spi_csn_clk = spi_csn_s[0];
+  assign gpio_i[31:24] = gpio_o[31:24];
+  assign gpio_i[23:16] = gpio_status;
 
-  daq2_spi i_daq2_spi (
-    .spi_csn (spi_csn_s[2:0]),
-    .spi_clk (spi_clk),
-    .spi_mosi (spi_mosi_s),
-    .spi_miso (spi_miso_s),
-    .spi_sdio (spi_sdio),
-    .spi_dir (spi_dir));
+  assign gpio_resetb = gpio_o[22];
+  assign gpio_sync = gpio_o[21];
+  assign gpio_en_agc = gpio_o[20];
+  assign gpio_ctl = gpio_o[19:16];
 
-  // gpio in & out are separate cores
+  // gpio (max-v-u21)
 
-  assign adc_pd = gpio_o[42];
-  assign dac_txen = gpio_o[41];
-  assign dac_reset = gpio_o[40];
-  assign clkd_sync = gpio_o[38];
+  assign gpio_i[15:8] = gpio_o[15:8];
+  assign gpio_i[ 7:0] = gpio_bd_i;
 
-  assign gpio_i[63:38] = gpio_o[63:38];
-  assign gpio_i[37:37] = trig;
-  assign gpio_i[36:36] = adc_fdb;
-  assign gpio_i[35:35] = adc_fda;
-  assign gpio_i[34:34] = dac_irq;
-  assign gpio_i[33:32] = clkd_status;
+  assign gpio_bd_o = gpio_o[3:0];
 
-  // board stuff
-
-  assign eth_resetn = ~eth_reset;
-  assign eth_mdio_i = eth_mdio;
-  assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
-
-  assign ddr3_a[14:12] = 3'd0;
-
-  assign gpio_i[31:27] = gpio_o[31:27];
-  assign gpio_i[26:16] = gpio_bd_i;
-  assign gpio_i[15: 0] = gpio_o[15:0];
-
-  assign gpio_bd_o = gpio_o[15:0];
+  // instantiations
 
   system_bd i_system_bd (
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
-    .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
-    .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc),
-    .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
-    .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
-    .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
-    .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
-    .a10gx_base_sys_ethernet_reset_reset (eth_reset),
-    .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
-    .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
-    .a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
-    .a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
-    .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
-    .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
-    .a10gx_base_sys_spi_MISO (spi_miso_s),
-    .a10gx_base_sys_spi_MOSI (spi_mosi_s),
-    .a10gx_base_sys_spi_SCLK (spi_clk),
-    .a10gx_base_sys_spi_SS_n (spi_csn_s),
-    .daq2_rx_data_rx_serial_data (rx_data),
-    .daq2_rx_ref_clk_clk (rx_ref_clk),
-    .daq2_rx_sync_rx_sync (rx_sync),
-    .daq2_rx_sysref_rx_ext_sysref_in (rx_sysref),
-    .daq2_tx_data_tx_serial_data (tx_data),
-    .daq2_tx_ref_clk_clk (tx_ref_clk),
-    .daq2_tx_sync_tx_sync (tx_sync),
-    .daq2_tx_sysref_tx_ext_sysref_in (tx_sysref),
+    .ad9361_if_rx_clk_in_p (rx_clk_in),
+    .ad9361_if_rx_clk_in_n (1'b0),
+    .ad9361_if_rx_frame_in_p (rx_frame_in),
+    .ad9361_if_rx_frame_in_n (1'b0),
+    .ad9361_if_rx_data_in_p (rx_data_in),
+    .ad9361_if_rx_data_in_n (6'd0),
+    .ad9361_if_tx_clk_out_p (tx_clk_out),
+    .ad9361_if_tx_clk_out_n (),
+    .ad9361_if_tx_frame_out_p (tx_frame_out),
+    .ad9361_if_tx_frame_out_n (),
+    .ad9361_if_tx_data_out_p (tx_data_out),
+    .ad9361_if_tx_data_out_n (),
+    .ad9361_if_enable (enable),
+    .ad9361_if_txnrx (txnrx),
+    .delay_clk_clk (1'b0),
+    .hps_ddr_mem_ck (hps_ddr_clk_p),
+    .hps_ddr_mem_ck_n (hps_ddr_clk_n),
+    .hps_ddr_mem_a (hsp_ddr_a),
+    .hps_ddr_mem_act_n (hps_ddr_act_n),
+    .hps_ddr_mem_ba (hps_ddr_ba),
+    .hps_ddr_mem_bg (hps_ddr_bg),
+    .hps_ddr_mem_cke (hps_ddr_cke),
+    .hps_ddr_mem_cs_n (hps_ddr_cs_n),
+    .hps_ddr_mem_odt (hps_ddr_odt),
+    .hps_ddr_mem_reset_n (hps_ddr_reset_n),
+    .hps_ddr_mem_par (hps_ddr_par),
+    .hps_ddr_mem_alert_n (hps_ddr_alert_n),
+    .hps_ddr_mem_dqs (hps_ddr_dqs_p),
+    .hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
+    .hps_ddr_mem_dq (hps_ddr_dq),
+    .hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
+    .hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
+    .hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
+    .hps_gpio_gp_in (gpio_i),
+    .hps_gpio_gp_out (gpio_o),
+    .hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
+    .hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
+    .hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
+    .hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
+    .hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
+    .hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
+    .hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
+    .hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
+    .hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
+    .hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
+    .hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
+    .hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
+    .hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
+    .hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
+    .hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
+    .hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
+    .hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
+    .hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
+    .hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
+    .hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
+    .hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
+    .hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
+    .hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
+    .hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
+    .hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
+    .hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
+    .hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
+    .hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
+    .hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
+    .hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
+    .hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
+    .hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
+    .hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
+    .hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
+    .hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
+    .hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
+    .hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
+    .hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
+    .hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
+    .hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
+    .hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
+    .hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
+    .hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
+    .hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
+    .hps_spi0_mosi_o (spi_mosi),
+    .hps_spi0_miso_i (spi_miso),
+    .hps_spi0_ss_in_n (1'b1),
+    .hps_spi0_mosi_oe (),
+    .hps_spi0_ss0_n_o (spi_csn),
+    .hps_spi0_ss1_n_o (),
+    .hps_spi0_ss2_n_o (),
+    .hps_spi0_ss3_n_o (),
+    .hps_spi0_sclk_clk (spi_clk),
+    .hps_spi1_mosi_o (),
+    .hps_spi1_miso_i (1'b0),
+    .hps_spi1_ss_in_n (1'b1),
+    .hps_spi1_mosi_oe (),
+    .hps_spi1_ss0_n_o (),
+    .hps_spi1_ss1_n_o (),
+    .hps_spi1_ss2_n_o (),
+    .hps_spi1_ss3_n_o (),
+    .hps_spi1_sclk_clk (),
     .sys_clk_clk (sys_clk),
-    .sys_reset_reset_n (sys_resetn));
+    .sys_reset_reset_n (sys_resetn),
+    .up_enable_up_enable (gpio_o[23]),
+    .up_txnrx_up_txnrx (gpio_o[24]));
 
 endmodule
 

From 4863a041325aba87f49eb5721c6b8a1a6b06df83 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 5 May 2016 09:40:25 +0300
Subject: [PATCH 184/972] axi_adc/dacfifo: Split the intergration script file

Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
---
 .../zc706/zc706_system_plddr3_adcfifo.tcl     | 81 +++++++++++++++++++
 ...r3.tcl => zc706_system_plddr3_dacfifo.tcl} | 81 +------------------
 projects/daq2/zc706/system_bd.tcl             |  4 +-
 projects/daq3/zc706/system_bd.tcl             |  4 +-
 projects/fmcadc2/zc706/system_bd.tcl          |  4 +-
 projects/fmcadc4/zc706/system_bd.tcl          |  4 +-
 projects/fmcomms7/zc706/system_bd.tcl         |  4 +-
 projects/usdrx1/zc706/system_bd.tcl           |  5 +-
 8 files changed, 95 insertions(+), 92 deletions(-)
 create mode 100644 projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 rename projects/common/zc706/{zc706_system_plddr3.tcl => zc706_system_plddr3_dacfifo.tcl} (52%)

diff --git a/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
new file mode 100644
index 000000000..1be9c1e41
--- /dev/null
+++ b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
@@ -0,0 +1,81 @@
+
+# pl ddr3 (use only when dma is not capable of keeping up).
+# generic fifo interface - existence is oblivious to software.
+
+proc p_plddr3_adcfifo {p_name m_name adc_data_width} {
+
+  global ad_hdl_dir
+
+  set p_instance [get_bd_cells $p_name]
+  set c_instance [current_bd_instance .]
+
+  current_bd_instance $p_instance
+
+  set m_instance [create_bd_cell -type hier $m_name]
+  current_bd_instance $m_instance
+
+  create_bd_pin -dir I -type rst sys_rst
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
+
+  create_bd_pin -dir I adc_rst
+  create_bd_pin -dir I -type clk adc_clk
+  create_bd_pin -dir I adc_wr
+  create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata
+  create_bd_pin -dir O adc_wovf
+
+  create_bd_pin -dir I -type clk dma_clk
+  create_bd_pin -dir O dma_wr
+  create_bd_pin -dir O -from 63 -to 0 dma_wdata
+  create_bd_pin -dir I dma_wready
+  create_bd_pin -dir I dma_xfer_req
+  create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
+
+  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
+  set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
+  file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
+  set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
+
+  set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
+  set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
+  set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
+
+  set axi_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_adcfifo:1.0 axi_adcfifo]
+  set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_adcfifo
+  set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $axi_adcfifo
+  set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_adcfifo
+  set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $axi_adcfifo
+  set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_adcfifo
+  set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_adcfifo
+  set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_adcfifo
+  set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_adcfifo
+  set_property -dict [list CONFIG.AXI_BYTE_WIDTH {64}] $axi_adcfifo
+
+  ad_connect  sys_rst axi_ddr_cntrl/sys_rst
+  ad_connect  sys_clk axi_ddr_cntrl/SYS_CLK
+  ad_connect  ddr3 axi_ddr_cntrl/DDR3
+  ad_connect  axi_ddr_cntrl/S_AXI axi_adcfifo/axi
+  ad_connect  adc_rst axi_adcfifo/adc_rst
+  ad_connect  adc_rst axi_rstgen/ext_reset_in
+  ad_connect  adc_clk axi_adcfifo/adc_clk
+  ad_connect  adc_wr axi_adcfifo/adc_wr
+  ad_connect  adc_wdata axi_adcfifo/adc_wdata
+  ad_connect  adc_wovf axi_adcfifo/adc_wovf
+  ad_connect  dma_clk axi_adcfifo/dma_clk
+  ad_connect  dma_wr axi_adcfifo/dma_wr
+  ad_connect  dma_wdata axi_adcfifo/dma_wdata
+  ad_connect  dma_wready axi_adcfifo/dma_wready
+  ad_connect  dma_xfer_req axi_adcfifo/dma_xfer_req
+  ad_connect  dma_xfer_status axi_adcfifo/dma_xfer_status
+  ad_connect  axi_clk axi_ddr_cntrl/ui_clk
+  ad_connect  axi_clk axi_adcfifo/axi_clk
+  ad_connect  axi_clk axi_rstgen/slowest_sync_clk
+  ad_connect  axi_resetn axi_rstgen/peripheral_aresetn
+  ad_connect  axi_resetn axi_adcfifo/axi_resetn
+  ad_connect  axi_resetn axi_ddr_cntrl/aresetn
+
+  ad_connect  axi_ddr_cntrl/device_temp_i GND
+
+  current_bd_instance $c_instance
+}
+
diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
similarity index 52%
rename from projects/common/zc706/zc706_system_plddr3.tcl
rename to projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index fc27c4b3f..7a181ea39 100644
--- a/projects/common/zc706/zc706_system_plddr3.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -2,84 +2,6 @@
 # pl ddr3 (use only when dma is not capable of keeping up).
 # generic fifo interface - existence is oblivious to software.
 
-proc p_plddr3_fifo {p_name m_name adc_data_width} {
-
-  global ad_hdl_dir
-
-  set p_instance [get_bd_cells $p_name]
-  set c_instance [current_bd_instance .]
-
-  current_bd_instance $p_instance
-
-  set m_instance [create_bd_cell -type hier $m_name]
-  current_bd_instance $m_instance
-
-  create_bd_pin -dir I -type rst sys_rst
-  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
-  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
-
-  create_bd_pin -dir I adc_rst
-  create_bd_pin -dir I -type clk adc_clk
-  create_bd_pin -dir I adc_wr
-  create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata
-  create_bd_pin -dir O adc_wovf
-
-  create_bd_pin -dir I -type clk dma_clk
-  create_bd_pin -dir O dma_wr
-  create_bd_pin -dir O -from 63 -to 0 dma_wdata
-  create_bd_pin -dir I dma_wready
-  create_bd_pin -dir I dma_xfer_req
-  create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
-
-  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
-  set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
-  file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
-  set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
-
-  set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
-  set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
-  set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
-
-  set axi_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_adcfifo:1.0 axi_adcfifo]
-  set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_adcfifo
-  set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $axi_adcfifo
-  set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_adcfifo
-  set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $axi_adcfifo
-  set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_adcfifo
-  set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_adcfifo
-  set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_adcfifo
-  set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_adcfifo
-  set_property -dict [list CONFIG.AXI_BYTE_WIDTH {64}] $axi_adcfifo
-
-  ad_connect  sys_rst axi_ddr_cntrl/sys_rst
-  ad_connect  sys_clk axi_ddr_cntrl/SYS_CLK
-  ad_connect  ddr3 axi_ddr_cntrl/DDR3
-  ad_connect  axi_ddr_cntrl/S_AXI axi_adcfifo/axi
-  ad_connect  adc_rst axi_adcfifo/adc_rst
-  ad_connect  adc_rst axi_rstgen/ext_reset_in
-  ad_connect  adc_clk axi_adcfifo/adc_clk
-  ad_connect  adc_wr axi_adcfifo/adc_wr
-  ad_connect  adc_wdata axi_adcfifo/adc_wdata
-  ad_connect  adc_wovf axi_adcfifo/adc_wovf
-  ad_connect  dma_clk axi_adcfifo/dma_clk
-  ad_connect  dma_wr axi_adcfifo/dma_wr
-  ad_connect  dma_wdata axi_adcfifo/dma_wdata
-  ad_connect  dma_wready axi_adcfifo/dma_wready
-  ad_connect  dma_xfer_req axi_adcfifo/dma_xfer_req
-  ad_connect  dma_xfer_status axi_adcfifo/dma_xfer_status
-  ad_connect  axi_clk axi_ddr_cntrl/ui_clk
-  ad_connect  axi_clk axi_adcfifo/axi_clk
-  ad_connect  axi_clk axi_rstgen/slowest_sync_clk
-  ad_connect  axi_resetn axi_rstgen/peripheral_aresetn
-  ad_connect  axi_resetn axi_adcfifo/axi_resetn
-  ad_connect  axi_resetn axi_ddr_cntrl/aresetn
-
-  ad_connect  axi_ddr_cntrl/device_temp_i GND
-
-  current_bd_instance $c_instance
-}
-
-
 proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
 
   global ad_hdl_dir
@@ -111,7 +33,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   create_bd_pin -dir I dma_xfer_req
   create_bd_pin -dir I dma_xfer_last
 
-  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
+  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
   set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
   file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
   set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
@@ -168,4 +90,3 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
 
   current_bd_instance $c_instance
 }
-
diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl
index 0d7b97711..44e72997e 100644
--- a/projects/daq2/zc706/system_bd.tcl
+++ b/projects/daq2/zc706/system_bd.tcl
@@ -1,10 +1,10 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
 
-p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
 
 create_bd_port -dir I -type rst sys_rst
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl
index 655c77173..b64eb4a15 100644
--- a/projects/daq3/zc706/system_bd.tcl
+++ b/projects/daq3/zc706/system_bd.tcl
@@ -1,9 +1,9 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
 
-p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
 p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
 
 create_bd_port -dir I -type rst sys_rst
diff --git a/projects/fmcadc2/zc706/system_bd.tcl b/projects/fmcadc2/zc706/system_bd.tcl
index 26f3c6a89..f7567d53a 100644
--- a/projects/fmcadc2/zc706/system_bd.tcl
+++ b/projects/fmcadc2/zc706/system_bd.tcl
@@ -1,8 +1,8 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 
-p_plddr3_fifo [current_bd_instance .] axi_ad9625_fifo 256
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256
 
 create_bd_port -dir I -type rst sys_rst
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl
index 06ae1973f..a20c17b24 100644
--- a/projects/fmcadc4/zc706/system_bd.tcl
+++ b/projects/fmcadc4/zc706/system_bd.tcl
@@ -1,8 +1,8 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 
-p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 256
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 256
 
 create_bd_port -dir I -type rst sys_rst
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
diff --git a/projects/fmcomms7/zc706/system_bd.tcl b/projects/fmcomms7/zc706/system_bd.tcl
index 3206d6a58..94dc97284 100644
--- a/projects/fmcomms7/zc706/system_bd.tcl
+++ b/projects/fmcomms7/zc706/system_bd.tcl
@@ -1,9 +1,9 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
 
-p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 256 10
 
 create_bd_port -dir I -type rst sys_rst
diff --git a/projects/usdrx1/zc706/system_bd.tcl b/projects/usdrx1/zc706/system_bd.tcl
index 0657c681c..239c0152f 100644
--- a/projects/usdrx1/zc706/system_bd.tcl
+++ b/projects/usdrx1/zc706/system_bd.tcl
@@ -1,8 +1,9 @@
 
+
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 
-p_plddr3_fifo [current_bd_instance .] usdrx1_fifo 512
+p_plddr3_adcfifo [current_bd_instance .] usdrx1_fifo 512
 
 create_bd_port -dir I -type rst sys_rst
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3

From 0d2dc2c62bda0109c8c84f7b2dad546660efcb18 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Thu, 5 May 2016 13:26:59 +0300
Subject: [PATCH 185/972] axi_hdmi_tx: Fixed data bus width

---
 library/axi_hdmi_tx/axi_hdmi_tx.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v
index 056eb2fb3..0c40fcb8f 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx.v
@@ -202,8 +202,8 @@ module axi_hdmi_tx (
   wire    [15:0]  hdmi_vs_width_s;
   wire    [15:0]  hdmi_ve_max_s;
   wire    [15:0]  hdmi_ve_min_s;
-  wire    [31:0]  hdmi_clip_max_s;
-  wire    [31:0]  hdmi_clip_min_s;
+  wire    [23:0]  hdmi_clip_max_s;
+  wire    [23:0]  hdmi_clip_min_s;
   wire            hdmi_fs_toggle_s;
   wire    [ 8:0]  hdmi_raddr_g_s;
   wire            hdmi_tpm_oos_s;

From 68d83def01f6f79be70ee123753d5c4cfdd76327 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Thu, 5 May 2016 13:32:25 +0300
Subject: [PATCH 186/972] axi_hdmi_tx_core: Fixed data path

---
 library/axi_hdmi_tx/axi_hdmi_tx_core.v | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
index fd1ccf12c..cc251c993 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
@@ -203,6 +203,10 @@ module axi_hdmi_tx_core (
   reg     [47:0]  hdmi_data_2d = 'd0;
   reg     [23:0]  hdmi_tpm_data = 'd0;
   reg             hdmi_tpm_oos = 'd0;
+  reg             hdmi_36_hsync = 'd0;
+  reg             hdmi_36_vsync = 'd0;
+  reg             hdmi_36_data_e = 'd0;
+  reg     [35:0]  hdmi_36_data = 'd0;
   reg             hdmi_hsync = 'd0;
   reg             hdmi_vsync = 'd0;
   reg             hdmi_hsync_data_e = 'd0;
@@ -543,15 +547,15 @@ module axi_hdmi_tx_core (
 
   // hdmi csc 16, 24 and 36 outputs
 
-  assign hdmi_36_hsync = hdmi_24_hsync;
-  assign hdmi_36_vsync = hdmi_24_vsync;
-  assign hdmi_36_data_e = hdmi_24_data_e;
-  assign hdmi_36_data[35:24] = {hdmi_24_data[23:16], hdmi_24_data[23:20]};
-  assign hdmi_36_data[23:12] = {hdmi_24_data[15: 8], hdmi_24_data[15:12]};
-  assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]};
-
   always @(posedge hdmi_clk) begin
 
+    hdmi_36_hsync = hdmi_clip_hs_d;
+    hdmi_36_vsync = hdmi_clip_vs_d;
+    hdmi_36_data_e = hdmi_clip_de_d;
+    hdmi_36_data[35:24] = {hdmi_clip_data[23:16], hdmi_clip_data[23:20]};
+    hdmi_36_data[23:12] = {hdmi_clip_data[15: 8], hdmi_clip_data[15:12]};
+    hdmi_36_data[11: 0] = {hdmi_clip_data[ 7: 0], hdmi_clip_data[ 7: 4]};
+
     hdmi_24_hsync <= hdmi_clip_hs_d;
     hdmi_24_vsync <= hdmi_clip_vs_d;
     hdmi_24_hsync_data_e <= hdmi_clip_hs_de_d;

From b36c722ec9f9f26249aff71c1e9e66b589780c8a Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Thu, 5 May 2016 13:41:46 +0300
Subject: [PATCH 187/972] up_hdmi_tx: Discard the standard default values

Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
---
 library/common/up_hdmi_tx.v | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v
index e1750e76b..691ce86b2 100644
--- a/library/common/up_hdmi_tx.v
+++ b/library/common/up_hdmi_tx.v
@@ -251,15 +251,6 @@ module up_hdmi_tx (
       end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
         up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0];
       end
-      if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
-        if ((up_wdata[1]== 1'b1) || (up_wdata[0] == 1'b1)) begin
-          up_clip_max <= 24'hfefefe;
-          up_clip_min <= 24'h010101;
-        end else begin
-          up_clip_max <= 24'hf0ebf0;
-          up_clip_min <= 24'h101010;
-        end
-      end
       if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin
         up_clip_max <= up_wdata[23:0];
       end

From b0538a03a21963ce12c5686452373c63b5147ee0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 5 May 2016 10:09:34 +0300
Subject: [PATCH 188/972] Make: Update

---
 library/axi_jesd_gt/Makefile     | 2 ++
 projects/arradio/c5soc/Makefile  | 8 +++++---
 projects/daq2/zc706/Makefile     | 6 +-----
 projects/daq3/zc706/Makefile     | 6 +-----
 projects/fmcadc2/zc706/Makefile  | 6 +-----
 projects/fmcadc4/zc706/Makefile  | 6 +-----
 projects/fmcomms7/zc706/Makefile | 6 +-----
 projects/usdrx1/zc706/Makefile   | 6 +-----
 8 files changed, 13 insertions(+), 33 deletions(-)

diff --git a/library/axi_jesd_gt/Makefile b/library/axi_jesd_gt/Makefile
index e8fdc5069..b8d0e78bd 100644
--- a/library/axi_jesd_gt/Makefile
+++ b/library/axi_jesd_gt/Makefile
@@ -19,6 +19,8 @@ M_DEPS += ../common/ad_jesd_align.v
 M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_gt_channel.v
 M_DEPS += ../common/up_gt.v
+M_DEPS += axi_jesd_gt_tx_constr.xdc
+M_DEPS += axi_jesd_gt_rx_constr.xdc
 M_DEPS += axi_jesd_gt_constr.xdc
 M_DEPS += axi_jesd_gt.v
 M_DEPS += ../interfaces/if_gt_qpll.xml
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 336822c5b..db86d7572 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -15,10 +15,9 @@ M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys
 M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_alt_lvds_rx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_alt_lvds_tx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_dev_if_alt.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
@@ -58,6 +57,9 @@ M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_tdd_control.v
 M_DEPS += ../../../library/common/altera/DSP48E1.v
 M_DEPS += ../../../library/common/altera/MULT_MACRO.v
+M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
+M_DEPS += ../../../library/common/altera/ad_cmos_in.v
+M_DEPS += ../../../library/common/altera/ad_cmos_out.v
 M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
 M_DEPS += ../../../library/common/altera/ad_lvds_in.v
 M_DEPS += ../../../library/common/altera/ad_lvds_out.v
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index 3bc213b4f..ec2fa7313 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -14,10 +14,9 @@ M_DEPS += ../common/daq2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
-M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
@@ -26,7 +25,6 @@ M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -67,7 +65,6 @@ clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -89,7 +86,6 @@ lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index cdf156482..a591c3306 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -14,10 +14,9 @@ M_DEPS += ../common/daq3_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
-M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
@@ -26,7 +25,6 @@ M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -68,7 +66,6 @@ clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -91,7 +88,6 @@ lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index d3305cc22..7a83de7f5 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -14,17 +14,15 @@ M_DEPS += ../common/fmcadc2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
-M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -60,7 +58,6 @@ clean-all:clean
 	make -C ../../../library/axi_ad9625 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -77,7 +74,6 @@ lib:
 	make -C ../../../library/axi_ad9625
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index b646b7ad8..b4f4379f4 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -14,17 +14,15 @@ M_DEPS += ../common/fmcadc4_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
-M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -63,7 +61,6 @@ clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -83,7 +80,6 @@ lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index f42098826..3f42f718c 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -14,10 +14,9 @@ M_DEPS += ../common/fmcomms7_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
-M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
@@ -26,7 +25,6 @@ M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -67,7 +65,6 @@ clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -89,7 +86,6 @@ lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index d653e20b8..1add6ecb0 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -14,16 +14,14 @@ M_DEPS += ../common/usdrx1_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl
 M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
-M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -59,7 +57,6 @@ clean-all:clean
 	make -C ../../../library/axi_ad9671 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -76,7 +73,6 @@ lib:
 	make -C ../../../library/axi_ad9671
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt

From 8d72b645ae6fac097909fb2966bc35334259aef2 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Mon, 9 May 2016 10:28:10 +0300
Subject: [PATCH 189/972] fmcomms2/common: Remove ila_tdd block

---
 projects/fmcomms2/common/fmcomms2_bd.tcl | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl
index b74ba6e76..c2afa50c9 100644
--- a/projects/fmcomms2/common/fmcomms2_bd.tcl
+++ b/projects/fmcomms2/common/fmcomms2_bd.tcl
@@ -186,15 +186,3 @@ ad_connect  util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3
 ad_connect  util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4
 ad_connect  sys_cpu_clk ila_adc/clk
 
-# ila (tdd)
-
-set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tdd]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd
-set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_tdd
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {42}] $ila_tdd
-
-ad_connect  axi_ad9361_clk          ila_tdd/clk
-ad_connect  axi_ad9361/tdd_dbg      ila_tdd/probe0
-

From 726ddb6e9337bbc7dc09eba1e1b7babbbc500bd0 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Mon, 9 May 2016 10:32:18 +0300
Subject: [PATCH 190/972] ad_lvds_clk: Fixed assignment mismatched

---
 library/common/ad_lvds_clk.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/common/ad_lvds_clk.v b/library/common/ad_lvds_clk.v
index 2bacd6d9c..a4c0ca153 100644
--- a/library/common/ad_lvds_clk.v
+++ b/library/common/ad_lvds_clk.v
@@ -65,7 +65,7 @@ module ad_lvds_clk (
 
   // defaults
 
-  assign locked <= 1'b1;
+  assign locked = 1'b1;
 
   // instantiations
 

From 9cd6e2da5129cf9a144784b2ac0496604a607070 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 9 May 2016 13:49:13 -0400
Subject: [PATCH 191/972] quartus-mess- altddio direct instantiation

---
 library/common/altera/ad_cmos_in.v  | 19 +++++++++++++++++++
 library/common/altera/ad_cmos_out.v | 21 +++++++++++++++++++++
 library/common/altera/ad_lvds_in.v  | 19 +++++++++++++++++++
 library/common/altera/ad_lvds_out.v | 21 +++++++++++++++++++++
 4 files changed, 80 insertions(+)

diff --git a/library/common/altera/ad_cmos_in.v b/library/common/altera/ad_cmos_in.v
index 85b791926..b424cc440 100644
--- a/library/common/altera/ad_cmos_in.v
+++ b/library/common/altera/ad_cmos_in.v
@@ -93,10 +93,29 @@ module ad_cmos_in (
 
   // instantiations
 
+  generate
+  if (DEVICE_TYPE == 0) begin
   alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in),
     .dout ({rx_data_p, rx_data_n}));
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == 1) begin
+  altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
+    .inclock (rx_clk),
+    .datain (rx_data_in),
+    .dataout_h (rx_data_p),
+    .dataout_l (rx_data_n),
+    .inclocken (1'b1),
+    .aclr (1'b0),
+    .aset (1'b0),
+    .sclr (1'b0),
+    .sset (1'b0));
+  end
+  endgenerate
 
 endmodule
 
diff --git a/library/common/altera/ad_cmos_out.v b/library/common/altera/ad_cmos_out.v
index 46896e197..c54d53d5d 100644
--- a/library/common/altera/ad_cmos_out.v
+++ b/library/common/altera/ad_cmos_out.v
@@ -94,10 +94,31 @@ module ad_cmos_out (
 
   // instantiations
 
+  generate
+  if (DEVICE_TYPE == 0) begin
   alt_ddio_out i_tx_data_oddr (
     .ck (tx_clk),
     .din ({tx_data_p, tx_data_n}),
     .pad_out (tx_data_out));
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == 1) begin
+  altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
+    .outclock (tx_clk),
+    .datain_h (tx_data_p),
+    .datain_l (tx_data_n),
+    .dataout (tx_data_out),
+    .outclocken (1'b1),
+    .oe_out (),
+    .oe (1'b1),
+    .aclr (1'b0),
+    .aset (1'b0),
+    .sclr (1'b0),
+    .sset (1'b0));
+  end
+  endgenerate
 
 endmodule
 
diff --git a/library/common/altera/ad_lvds_in.v b/library/common/altera/ad_lvds_in.v
index 7422234bd..08dd863f1 100644
--- a/library/common/altera/ad_lvds_in.v
+++ b/library/common/altera/ad_lvds_in.v
@@ -95,10 +95,29 @@ module ad_lvds_in (
 
   // instantiations
 
+  generate
+  if (DEVICE_TYPE == 0) begin
   alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in_p),
     .dout ({rx_data_p, rx_data_n}));
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == 1) begin
+  altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
+    .inclock (rx_clk),
+    .datain (rx_data_in_p),
+    .dataout_h (rx_data_p),
+    .dataout_l (rx_data_n),
+    .inclocken (1'b1),
+    .aclr (1'b0),
+    .aset (1'b0),
+    .sclr (1'b0),
+    .sset (1'b0));
+  end
+  endgenerate
 
 endmodule
 
diff --git a/library/common/altera/ad_lvds_out.v b/library/common/altera/ad_lvds_out.v
index dc673ac80..9f8bf8cec 100644
--- a/library/common/altera/ad_lvds_out.v
+++ b/library/common/altera/ad_lvds_out.v
@@ -96,10 +96,31 @@ module ad_lvds_out (
 
   // instantiations
 
+  generate
+  if (DEVICE_TYPE == 0) begin
   alt_ddio_out i_tx_data_oddr (
     .ck (tx_clk),
     .din ({tx_data_p, tx_data_n}),
     .pad_out (tx_data_out_p));
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == 1) begin
+  altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
+    .outclock (tx_clk),
+    .datain_h (tx_data_p),
+    .datain_l (tx_data_n),
+    .dataout (tx_data_out_p),
+    .outclocken (1'b1),
+    .oe_out (),
+    .oe (1'b1),
+    .aclr (1'b0),
+    .aset (1'b0),
+    .sclr (1'b0),
+    .sset (1'b0));
+  end
+  endgenerate
 
 endmodule
 

From 3871d3ce2b28a0198e178d5e70ea9b0a6f74634e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 9 May 2016 13:52:08 -0400
Subject: [PATCH 192/972] ad9361-c5/a10 - updates

---
 library/axi_ad9361/axi_ad9361_hw.tcl | 35 +++++++++++++++++-----------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index a3c73dc11..fe5b66393 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -201,20 +201,6 @@ ad_alt_intf signal up_dac_gpio_out output 32
 ad_alt_intf signal up_adc_gpio_in input 32
 ad_alt_intf signal up_adc_gpio_out output 32
 
-# sub-modules
-
-add_hdl_instance alt_ddio_in altera_gpio
-set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
-set_instance_parameter_value alt_ddio_in {SIZE} {1}
-set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
-set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
-
-add_hdl_instance alt_ddio_out altera_gpio
-set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
-set_instance_parameter_value alt_ddio_out {SIZE} {1}
-set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
-set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
-
 # updates
 
 proc p_axi_ad9361 {} {
@@ -257,10 +243,31 @@ proc p_axi_ad9361 {} {
   add_interface_port device_if txnrx txnrx Output 1
 
   if {$m_device_type == 1} {
+
+    add_hdl_instance alt_clk altera_pll
+    set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
+    set_instance_parameter_value alt_clk {gui_use_locked} {1}
+    set_instance_parameter_value alt_clk {gui_operation_mode} {source synchronous}
+    set_instance_parameter_value alt_clk {gui_number_of_clocks} {1}
+    set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
+    set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
+    set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
   }
 
   if {$m_device_type == 0} {
 
+    add_hdl_instance alt_ddio_in altera_gpio
+    set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
+    set_instance_parameter_value alt_ddio_in {SIZE} {1}
+    set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
+    set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
+
+    add_hdl_instance alt_ddio_out altera_gpio
+    set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
+    set_instance_parameter_value alt_ddio_out {SIZE} {1}
+    set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
+    set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
+
     add_hdl_instance alt_clk altera_iopll
     set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
     set_instance_parameter_value alt_clk {gui_use_locked} {1}

From 89b20f2a35b051f88c74d0721a44e796489be0fe Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 9 May 2016 13:53:15 -0400
Subject: [PATCH 193/972] c5soc- remove unused hps ports

---
 projects/common/c5soc/c5soc_system_assign.tcl | 213 +++++++++---------
 projects/common/c5soc/c5soc_system_bd.qsys    |  42 ++--
 2 files changed, 126 insertions(+), 129 deletions(-)

diff --git a/projects/common/c5soc/c5soc_system_assign.tcl b/projects/common/c5soc/c5soc_system_assign.tcl
index 9c25eda56..46d7f375b 100755
--- a/projects/common/c5soc/c5soc_system_assign.tcl
+++ b/projects/common/c5soc/c5soc_system_assign.tcl
@@ -14,95 +14,95 @@ set_instance_assignment -name IO_STANDARD "1.5 V" -to sys_clk
 set_location_assignment PIN_W20   -to vga_clk
 set_location_assignment PIN_AH3   -to vga_blank_n
 set_location_assignment PIN_AG2   -to vga_sync_n
-set_location_assignment PIN_AD12  -to vga_hs
-set_location_assignment PIN_AC12  -to vga_vs
-set_location_assignment PIN_AF29 -to vga_b[7]
-set_location_assignment PIN_AE28 -to vga_b[0]
-set_location_assignment PIN_Y23 -to vga_b[1]
-set_location_assignment PIN_Y24 -to vga_b[2]
-set_location_assignment PIN_AG28 -to vga_b[3]
-set_location_assignment PIN_AF28 -to vga_b[4]
-set_location_assignment PIN_V23 -to vga_b[5]
-set_location_assignment PIN_W24 -to vga_b[6]
-set_location_assignment PIN_Y21 -to vga_g[0]
-set_location_assignment PIN_AA25 -to vga_g[1]
-set_location_assignment PIN_AB26 -to vga_g[2]
-set_location_assignment PIN_AB22 -to vga_g[3]
-set_location_assignment PIN_AB23 -to vga_g[4]
-set_location_assignment PIN_AA24 -to vga_g[5]
-set_location_assignment PIN_AB25 -to vga_g[6]
-set_location_assignment PIN_AE27 -to vga_g[7]
-set_location_assignment PIN_AG5 -to vga_r[0]
-set_location_assignment PIN_AA12 -to vga_r[1]
-set_location_assignment PIN_AB12 -to vga_r[2]
-set_location_assignment PIN_AF6 -to vga_r[3]
-set_location_assignment PIN_AG6 -to vga_r[4]
-set_location_assignment PIN_AJ2 -to vga_r[5]
-set_location_assignment PIN_AH5 -to vga_r[6]
-set_location_assignment PIN_AJ1 -to vga_r[7]
+set_location_assignment PIN_AD12  -to vga_hsync
+set_location_assignment PIN_AC12  -to vga_vsync
+set_location_assignment PIN_AG5   -to vga_red[0]
+set_location_assignment PIN_AA12  -to vga_red[1]
+set_location_assignment PIN_AB12  -to vga_red[2]
+set_location_assignment PIN_AF6   -to vga_red[3]
+set_location_assignment PIN_AG6   -to vga_red[4]
+set_location_assignment PIN_AJ2   -to vga_red[5]
+set_location_assignment PIN_AH5   -to vga_red[6]
+set_location_assignment PIN_AJ1   -to vga_red[7]
+set_location_assignment PIN_Y21   -to vga_grn[0]
+set_location_assignment PIN_AA25  -to vga_grn[1]
+set_location_assignment PIN_AB26  -to vga_grn[2]
+set_location_assignment PIN_AB22  -to vga_grn[3]
+set_location_assignment PIN_AB23  -to vga_grn[4]
+set_location_assignment PIN_AA24  -to vga_grn[5]
+set_location_assignment PIN_AB25  -to vga_grn[6]
+set_location_assignment PIN_AE27  -to vga_grn[7]
+set_location_assignment PIN_AE28  -to vga_blu[0]
+set_location_assignment PIN_Y23   -to vga_blu[1]
+set_location_assignment PIN_Y24   -to vga_blu[2]
+set_location_assignment PIN_AG28  -to vga_blu[3]
+set_location_assignment PIN_AF28  -to vga_blu[4]
+set_location_assignment PIN_V23   -to vga_blu[5]
+set_location_assignment PIN_W24   -to vga_blu[6]
+set_location_assignment PIN_AF29  -to vga_blu[7]
+
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blank_n
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_sync_n
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hs
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vs
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hsync
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vsync
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[7]
 
 # led & switches
 
-set_location_assignment PIN_AD7  -to led[3]
-set_location_assignment PIN_AE11 -to led[2]
-set_location_assignment PIN_AD10 -to led[1]
-set_location_assignment PIN_AF10 -to led[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[0]
+set_location_assignment PIN_AD7  -to gpio_bd_o[3]
+set_location_assignment PIN_AE11 -to gpio_bd_o[2]
+set_location_assignment PIN_AD10 -to gpio_bd_o[1]
+set_location_assignment PIN_AF10 -to gpio_bd_o[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[0]
 
-set_location_assignment PIN_AD11 -to push_buttons[3]
-set_location_assignment PIN_AD9  -to push_buttons[2]
-set_location_assignment PIN_AE12 -to push_buttons[1]
-set_location_assignment PIN_AE9  -to push_buttons[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[0]
-
-set_location_assignment PIN_AC29 -to dip_switches[3]
-set_location_assignment PIN_AC28 -to dip_switches[2]
-set_location_assignment PIN_V25  -to dip_switches[1]
-set_location_assignment PIN_W25  -to dip_switches[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[0]
+set_location_assignment PIN_AD11 -to gpio_bd_i[0]
+set_location_assignment PIN_AD9  -to gpio_bd_i[1]
+set_location_assignment PIN_AE12 -to gpio_bd_i[2]
+set_location_assignment PIN_AE9  -to gpio_bd_i[3]
+set_location_assignment PIN_AC29 -to gpio_bd_i[4]
+set_location_assignment PIN_AC28 -to gpio_bd_i[5]
+set_location_assignment PIN_V25  -to gpio_bd_i[6]
+set_location_assignment PIN_W25  -to gpio_bd_i[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[7]
 
 # uart
 
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_tx
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_rx
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_tx
 
 # spim1 (lcd)
 
@@ -117,47 +117,47 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_stp
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_dir
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_nxt
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d3
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d4
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d5
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d6
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[7]
 
 # sdio
 
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_cmd
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d0
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d3
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[3]
 
 # qspi
 
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_ss0
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io0
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io3
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[3]
 
 # ethernet
 
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_ctl
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[3]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_ctl
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[3]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdc
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdio
 
@@ -320,7 +320,7 @@ set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_reset_n
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_oct_rzqin
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_rzq
 
 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
@@ -461,6 +461,13 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
 set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
+# set libraries
+
+set ad_lib_folders "../common/;../../common/c5soc/;../../../library/**/*"
+
+set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
+set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
+
 
 
 
diff --git a/projects/common/c5soc/c5soc_system_bd.qsys b/projects/common/c5soc/c5soc_system_bd.qsys
index dab5f0d2f..51cbefb5e 100644
--- a/projects/common/c5soc/c5soc_system_bd.qsys
+++ b/projects/common/c5soc/c5soc_system_bd.qsys
@@ -18,7 +18,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -39,7 +39,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -52,7 +52,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -73,7 +73,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -107,7 +107,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -128,7 +128,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -154,7 +154,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -183,7 +183,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -196,7 +196,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -209,7 +209,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -318,7 +318,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -331,7 +331,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -352,7 +352,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -365,7 +365,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -424,16 +424,6 @@
    internal="sys_hps.memory"
    type="conduit"
    dir="end" />
- <interface
-   name="sys_hps_spim0"
-   internal="sys_hps.spim0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_spim0_sclk_out"
-   internal="sys_hps.spim0_sclk_out"
-   type="clock"
-   dir="start" />
  <interface
    name="sys_intr"
    internal="sys_intr.receiver_irq"
@@ -938,8 +928,8 @@
   <parameter name="SKIP_MEM_INIT" value="true" />
   <parameter name="SOPC_COMPAT_RESET" value="false" />
   <parameter name="SPEED_GRADE" value="7" />
-  <parameter name="SPIM0_Mode" value="Full" />
-  <parameter name="SPIM0_PinMuxing" value="FPGA" />
+  <parameter name="SPIM0_Mode" value="N/A" />
+  <parameter name="SPIM0_PinMuxing" value="Unused" />
   <parameter name="SPIM1_Mode" value="Single Slave Select" />
   <parameter name="SPIM1_PinMuxing" value="HPS I/O Set 0" />
   <parameter name="SPIS0_Mode" value="N/A" />

From 0041bf69be009cf15d97243314a4cf75c85f90b1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 9 May 2016 13:53:49 -0400
Subject: [PATCH 194/972] c5soc- remove unused hps ports

---
 projects/arradio/c5soc/system_bd.qsys     |  83 ++--
 projects/arradio/c5soc/system_constr.sdc  |  55 +--
 projects/arradio/c5soc/system_project.tcl |  94 ++--
 projects/arradio/c5soc/system_top.v       | 547 ++++++++--------------
 projects/arradio/common/arradio_bd.qsys   |  72 ++-
 5 files changed, 327 insertions(+), 524 deletions(-)

diff --git a/projects/arradio/c5soc/system_bd.qsys b/projects/arradio/c5soc/system_bd.qsys
index ec86e336c..15acbb0a3 100644
--- a/projects/arradio/c5soc/system_bd.qsys
+++ b/projects/arradio/c5soc/system_bd.qsys
@@ -135,76 +135,81 @@
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
-   name="axi_ad9361_device_clock"
-   internal="arradio.axi_ad9361_device_clock"
+   name="axi_ad9361_delay_clk"
+   internal="arradio.axi_ad9361_delay_clk"
    type="clock"
    dir="end" />
+ <interface
+   name="axi_ad9361_device_clock"
+   internal="arradio.axi_ad9361_device_clock" />
  <interface
    name="axi_ad9361_device_if"
    internal="arradio.axi_ad9361_device_if"
    type="conduit"
    dir="end" />
+ <interface name="axi_ad9361_l_clk" internal="arradio.axi_ad9361_l_clk" />
  <interface
-   name="axi_ad9361_l_clk"
-   internal="arradio.axi_ad9361_l_clk"
-   type="clock"
-   dir="start" />
- <interface name="clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+   name="axi_ad9361_up_enable"
+   internal="arradio.axi_ad9361_up_enable"
+   type="conduit"
+   dir="end" />
  <interface
-   name="gpio_external_connection"
+   name="axi_ad9361_up_txnrx"
+   internal="arradio.axi_ad9361_up_txnrx"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="gpio"
    internal="arradio.gpio_external_connection"
    type="conduit"
    dir="end" />
- <interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
  <interface
-   name="spi_ad9361_external"
+   name="spi"
    internal="arradio.spi_ad9361_external"
    type="conduit"
    dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
  <interface
-   name="sys_gpio_external_connection"
+   name="sys_gpio"
    internal="c5soc.sys_gpio_external_connection"
    type="conduit"
    dir="end" />
  <interface
-   name="sys_hps_h2f_reset"
-   internal="c5soc.sys_hps_h2f_reset"
-   type="reset"
-   dir="start" />
- <interface
-   name="sys_hps_hps_io"
+   name="sys_hps_io"
    internal="c5soc.sys_hps_hps_io"
    type="conduit"
    dir="end" />
  <interface
-   name="sys_hps_memory"
+   name="sys_hps_mem"
    internal="c5soc.sys_hps_memory"
    type="conduit"
    dir="end" />
  <interface
-   name="sys_hps_spim0"
-   internal="c5soc.sys_hps_spim0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_spim0_sclk_out"
-   internal="c5soc.sys_hps_spim0_sclk_out"
-   type="clock"
+   name="sys_hps_reset"
+   internal="c5soc.sys_hps_h2f_reset"
+   type="reset"
    dir="start" />
+ <interface name="sys_hps_spim0" internal="c5soc.sys_hps_spim0" />
+ <interface name="sys_hps_spim0_sclk_out" internal="c5soc.sys_hps_spim0_sclk_out" />
  <interface
-   name="vga_clock_video_output_clocked_video"
-   internal="c5soc.vga_clock_video_output_clocked_video"
-   type="conduit"
+   name="sys_reset"
+   internal="sys_clk.clk_in_reset"
+   type="reset"
    dir="end" />
  <interface
-   name="vga_pixel_clock_bridge_out_clk"
+   name="vga_clk"
    internal="c5soc.vga_pixel_clock_bridge_out_clk"
    type="clock"
    dir="start" />
+ <interface
+   name="vga_if"
+   internal="c5soc.vga_clock_video_output_clocked_video"
+   type="conduit"
+   dir="end" />
  <module name="arradio" kind="arradio_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_DOMAIN" value="1" />
-  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
   <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
@@ -217,12 +222,12 @@
   <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="6" />
   <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="80000000" />
-  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
+  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
   <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_arradio</parameter>
  </module>
  <module name="c5soc" kind="c5soc_system_bd" version="1.0" enabled="1">
@@ -230,9 +235,9 @@
   <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
   <parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
diff --git a/projects/arradio/c5soc/system_constr.sdc b/projects/arradio/c5soc/system_constr.sdc
index 26a1241ec..d6dd5ca69 100644
--- a/projects/arradio/c5soc/system_constr.sdc
+++ b/projects/arradio/c5soc/system_constr.sdc
@@ -1,25 +1,14 @@
 
-create_clock -period "20.000 ns" -name clk_50m  [get_ports {sys_clk}]
-create_clock -period  "4.000 ns" -name clk_250m [get_ports {rx_clk_in}]
-create_clock -period "12.500 ns" -name clk_80m  [get_pins {i_system_bd|c5soc|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
+create_clock -period "20.000 ns" -name sys_clk  [get_ports {sys_clk}]
+create_clock -period "12.500 ns" -name dma_clk  [get_pins {*sys_hps*h2f_user0_clk}]
+
+create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}]
+create_clock -period 4.0 -name v_rx_clk
 
 derive_pll_clocks
 derive_clock_uncertainty
 
-set clk_125m [get_clocks {i_system_bd|arradio|axi_ad9361|i_dev_if|i_rx|i_altlvds_rx|auto_generated|pll_sclk~PLL_OUTPUT_COUNTER|divclk}]
-
-set clk_vga [get_clocks {i_system_bd|c5soc|vga_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
-
-set_false_path -from clk_50m     -to clk_80m
-set_false_path -from clk_50m     -to $clk_125m
-set_false_path -from clk_80m     -to clk_50m 
-set_false_path -from clk_80m     -to $clk_125m
-set_false_path -from $clk_125m   -to clk_50m 
-set_false_path -from $clk_125m   -to clk_80m 
-set_false_path -from clk_50m     -to $clk_vga
-set_false_path -from $clk_vga    -to clk_50m
-
-create_clock -period 4.0 -name v_rx_clk
+create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}]
 
 set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_frame_in}]
 set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[0]}]
@@ -36,23 +25,19 @@ set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[3]}]   -clo
 set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[4]}]   -clock_fall -add_delay
 set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[5]}]   -clock_fall -add_delay
 
-create_generated_clock -source [get_ports {rx_clk_in}] -name v_tx_clk [get_ports {tx_clk_out}] -phase 90
 
-set_false_path -from clk_250m    -to v_tx_clk
-set_false_path -from v_tx_clk    -to clk_250m
-
-set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_frame_out}]
-set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[0]}]
-set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[1]}]
-set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[2]}]
-set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[3]}]
-set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[4]}]
-set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[5]}]
-set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_frame_out}]    -clock_fall -add_delay
-set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[0]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[1]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[2]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[3]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[4]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[5]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_frame_out}]
+set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[0]}]
+set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[1]}]
+set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[2]}]
+set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[3]}]
+set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[4]}]
+set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[5]}]
+set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_frame_out}]    -clock_fall -add_delay
+set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[0]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[1]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[2]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[3]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[4]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[5]}]  -clock_fall -add_delay
 
diff --git a/projects/arradio/c5soc/system_project.tcl b/projects/arradio/c5soc/system_project.tcl
index a00f71e25..2fbce5857 100644
--- a/projects/arradio/c5soc/system_project.tcl
+++ b/projects/arradio/c5soc/system_project.tcl
@@ -5,16 +5,46 @@ source ../../scripts/adi_env.tcl
 project_new arradio_c5soc -overwrite
 
 source "../../common/c5soc/c5soc_system_assign.tcl"
-set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
-set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
-set_global_assignment -name QSYS_FILE system_bd.qsys
 
+set_global_assignment -name QSYS_FILE system_bd.qsys
 set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
 set_global_assignment -name VERILOG_FILE system_top.v
-
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
 
+set_location_assignment PIN_H15 -to rx_clk_in
+set_location_assignment PIN_G15 -to "rx_clk_in(n)"
+set_location_assignment PIN_F13 -to rx_frame_in
+set_location_assignment PIN_E13 -to "rx_frame_in(n)"
+set_location_assignment PIN_D11 -to rx_data_in[0]
+set_location_assignment PIN_D10 -to "rx_data_in[0](n)"
+set_location_assignment PIN_E12 -to rx_data_in[1]
+set_location_assignment PIN_D12 -to "rx_data_in[1](n)"
+set_location_assignment PIN_E9  -to rx_data_in[2]
+set_location_assignment PIN_D9  -to "rx_data_in[2](n)"
+set_location_assignment PIN_B6  -to rx_data_in[3]
+set_location_assignment PIN_B5  -to "rx_data_in[3](n)"
+set_location_assignment PIN_F11 -to rx_data_in[4]
+set_location_assignment PIN_E11 -to "rx_data_in[4](n)"
+set_location_assignment PIN_C13 -to rx_data_in[5]
+set_location_assignment PIN_B12 -to "rx_data_in[5](n)"
+set_location_assignment PIN_A11 -to tx_clk_out
+set_location_assignment PIN_A10 -to "tx_clk_out(n)"
+set_location_assignment PIN_E3  -to tx_frame_out
+set_location_assignment PIN_E2  -to "tx_frame_out(n)"
+set_location_assignment PIN_E1  -to tx_data_out[0]
+set_location_assignment PIN_D1  -to "tx_data_out[0](n)"
+set_location_assignment PIN_D2  -to tx_data_out[1]
+set_location_assignment PIN_C2  -to "tx_data_out[1](n)"
+set_location_assignment PIN_C3  -to tx_data_out[2]
+set_location_assignment PIN_B3  -to "tx_data_out[2](n)"
+set_location_assignment PIN_B2  -to tx_data_out[3]
+set_location_assignment PIN_B1  -to "tx_data_out[3](n)"
+set_location_assignment PIN_A4  -to tx_data_out[4]
+set_location_assignment PIN_A3  -to "tx_data_out[4](n)"
+set_location_assignment PIN_E4  -to tx_data_out[5]
+set_location_assignment PIN_D4  -to "tx_data_out[5](n)"
+
 set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
 set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
 set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
@@ -41,60 +71,28 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[3]
 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[4]
 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[5]
 
-set_location_assignment PIN_H15 -to rx_clk_in
-set_location_assignment PIN_G15 -to "rx_clk_in(n)"
-set_location_assignment PIN_F13 -to rx_frame_in
-set_location_assignment PIN_E13 -to "rx_frame_in(n)"
-set_location_assignment PIN_D11 -to rx_data_in[0]
-set_location_assignment PIN_D10 -to "rx_data_in[0](n)"
-set_location_assignment PIN_E12 -to rx_data_in[1]
-set_location_assignment PIN_D12 -to "rx_data_in[1](n)"
-set_location_assignment PIN_E9  -to rx_data_in[2]
-set_location_assignment PIN_D9  -to "rx_data_in[2](n)"
-set_location_assignment PIN_B6  -to rx_data_in[3]
-set_location_assignment PIN_B5  -to "rx_data_in[3](n)"
-set_location_assignment PIN_F11 -to rx_data_in[4]
-set_location_assignment PIN_E11 -to "rx_data_in[4](n)"
-set_location_assignment PIN_C13 -to rx_data_in[5]
-set_location_assignment PIN_B12 -to "rx_data_in[5](n)"
-
-set_location_assignment PIN_A11 -to tx_clk_out
-set_location_assignment PIN_A10 -to "tx_clk_out(n)"
-set_location_assignment PIN_E3  -to tx_frame_out
-set_location_assignment PIN_E2  -to "tx_frame_out(n)"
-set_location_assignment PIN_E1  -to tx_data_out[0]
-set_location_assignment PIN_D1  -to "tx_data_out[0](n)"
-set_location_assignment PIN_D2  -to tx_data_out[1]
-set_location_assignment PIN_C2  -to "tx_data_out[1](n)"
-set_location_assignment PIN_C3  -to tx_data_out[2]
-set_location_assignment PIN_B3  -to "tx_data_out[2](n)"
-set_location_assignment PIN_B2  -to tx_data_out[3]
-set_location_assignment PIN_B1  -to "tx_data_out[3](n)"
-set_location_assignment PIN_A4  -to tx_data_out[4]
-set_location_assignment PIN_A3  -to "tx_data_out[4](n)"
-set_location_assignment PIN_E4  -to tx_data_out[5]
-set_location_assignment PIN_D4  -to "tx_data_out[5](n)"
+set_location_assignment PIN_B11 -to enable
+set_location_assignment PIN_C12 -to txnrx
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enable
+set_instance_assignment -name IO_STANDARD "2.5 V" -to txnrx
 
+set_location_assignment PIN_C4  -to ad9361_resetb
+set_location_assignment PIN_C5  -to ad9361_en_agc
+set_location_assignment PIN_D5  -to ad9361_sync
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_resetb
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_en_agc
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_sync
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_enable
-set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_txnrx
 
+set_location_assignment PIN_A8  -to spi_csn
+set_location_assignment PIN_H12 -to spi_clk
+set_location_assignment PIN_H13 -to spi_mosi
+set_location_assignment PIN_G11 -to spi_miso
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_mosi
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_miso
 
-set_location_assignment PIN_C4  -to ad9361_resetb
-set_location_assignment PIN_C5  -to ad9361_en_agc
-set_location_assignment PIN_D5  -to ad9361_sync
-set_location_assignment PIN_B11 -to ad9361_enable
-set_location_assignment PIN_C12 -to ad9361_txnrx
-set_location_assignment PIN_A8  -to spi_csn
-set_location_assignment PIN_H12 -to spi_clk
-set_location_assignment PIN_H13 -to spi_mosi
-set_location_assignment PIN_G11 -to spi_miso
+set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity axi_ad9361
 
 execute_flow -compile
 
diff --git a/projects/arradio/c5soc/system_top.v b/projects/arradio/c5soc/system_top.v
index e3ee25a18..72475bbed 100644
--- a/projects/arradio/c5soc/system_top.v
+++ b/projects/arradio/c5soc/system_top.v
@@ -41,379 +41,139 @@ module system_top (
 
   // clock and resets
 
-  sys_clk,
+  input             sys_clk,
 
-  // hps
+  // hps-ddr
 
-  ddr3_a,
-  ddr3_ba,
-  ddr3_ck_p,
-  ddr3_ck_n,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_ras_n,
-  ddr3_cas_n,
-  ddr3_we_n,
-  ddr3_reset_n,
-  ddr3_dq,
-  ddr3_dqs_p,
-  ddr3_dqs_n,
-  ddr3_odt,
-  ddr3_dm,
-  ddr3_oct_rzqin,
-  eth1_tx_clk,
-  eth1_tx_ctl,
-  eth1_txd0,
-  eth1_txd1,
-  eth1_txd2,
-  eth1_txd3,
-  eth1_rx_clk,
-  eth1_rx_ctl,
-  eth1_rxd0,
-  eth1_rxd1,
-  eth1_rxd2,
-  eth1_rxd3,
-  eth1_mdc,
-  eth1_mdio,
-  qspi_ss0,
-  qspi_clk,
-  qspi_io0,
-  qspi_io1,
-  qspi_io2,
-  qspi_io3,
-  sdio_clk,
-  sdio_cmd,
-  sdio_d0,
-  sdio_d1,
-  sdio_d2,
-  sdio_d3,
-  usb1_clk,
-  usb1_stp,
-  usb1_dir,
-  usb1_nxt,
-  usb1_d0,
-  usb1_d1,
-  usb1_d2,
-  usb1_d3,
-  usb1_d4,
-  usb1_d5,
-  usb1_d6,
-  usb1_d7,
-  spim1_ss0,
-  spim1_clk,
-  spim1_mosi,
-  spim1_miso,
-  uart0_rx,
-  uart0_tx,
+  output  [ 14:0]   ddr3_a,
+  output  [  2:0]   ddr3_ba,
+  output            ddr3_reset_n,
+  output            ddr3_ck_p,
+  output            ddr3_ck_n,
+  output            ddr3_cke,
+  output            ddr3_cs_n,
+  output            ddr3_ras_n,
+  output            ddr3_cas_n,
+  output            ddr3_we_n,
+  inout   [ 31:0]   ddr3_dq,
+  inout   [  3:0]   ddr3_dqs_p,
+  inout   [  3:0]   ddr3_dqs_n,
+  output  [  3:0]   ddr3_dm,
+  output            ddr3_odt,
+  input             ddr3_rzq,
+
+  // hps-ethernet
+
+  output            eth1_tx_clk,
+  output            eth1_tx_ctl,
+  output  [  3:0]   eth1_tx_d,
+  input             eth1_rx_clk,
+  input             eth1_rx_ctl,
+  input   [  3:0]   eth1_rx_d,
+  output            eth1_mdc,
+  inout             eth1_mdio,
+
+  // hps-qspi
+
+  output            qspi_ss0,
+  output            qspi_clk,
+  inout   [  3:0]   qspi_io,
+
+  // hps-sdio
+
+  output            sdio_clk,
+  inout             sdio_cmd,
+  inout   [  3:0]   sdio_d,
+
+  // hps-usb
+
+  input             usb1_clk,
+  output            usb1_stp,
+  input             usb1_dir,
+  input             usb1_nxt,
+  inout   [  7:0]   usb1_d,
+
+  // hps-spim1-lcd
+
+  output            spim1_ss0,
+  output            spim1_clk,
+  output            spim1_mosi,
+  input             spim1_miso,
+
+  // hps-uart
+
+  input             uart0_rx,
+  output            uart0_tx,
 
   // board gpio
 
-  led,
-  push_buttons,
-  dip_switches,
+  output  [  3:0]   gpio_bd_o,
+  input   [  7:0]   gpio_bd_i,
 
   // display
 
-  vga_clk,
-  vga_blank_n,
-  vga_sync_n,
-  vga_hs,
-  vga_vs,
-  vga_r,
-  vga_g,
-  vga_b,
+  output            vga_clk,
+  output            vga_blank_n,
+  output            vga_sync_n,
+  output            vga_hsync,
+  output            vga_vsync,
+  output  [  7:0]   vga_red,
+  output  [  7:0]   vga_grn,
+  output  [  7:0]   vga_blu,
 
-  // data interface
+  // ad9361
 
-  rx_clk_in,
-  rx_frame_in,
-  rx_data_in,
-  tx_clk_out,
-  tx_frame_out,
-  tx_data_out,
+  input             rx_clk_in,
+  input             rx_frame_in,
+  input   [  5:0]   rx_data_in,
+  output            tx_clk_out,
+  output            tx_frame_out,
+  output  [  5:0]   tx_data_out,
+  output            enable,
+  output            txnrx,
 
   // gpio interface
 
-  ad9361_resetb,
-  ad9361_en_agc,
-  ad9361_sync,
-  ad9361_enable,
-  ad9361_txnrx,
-
-  // spi
-
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso);
-
-  // clock and resets
-
-  input             sys_clk;
-
-  // hps
-
-  output  [ 14:0]   ddr3_a;
-  output  [  2:0]   ddr3_ba;
-  output            ddr3_ck_p;
-  output            ddr3_ck_n;
-  output            ddr3_cke;
-  output            ddr3_cs_n;
-  output            ddr3_ras_n;
-  output            ddr3_cas_n;
-  output            ddr3_we_n;
-  output            ddr3_reset_n;
-  inout   [ 31:0]   ddr3_dq;
-  inout   [  3:0]   ddr3_dqs_p;
-  inout   [  3:0]   ddr3_dqs_n;
-  output            ddr3_odt;
-  output  [  3:0]   ddr3_dm;
-  input             ddr3_oct_rzqin;
-  output            eth1_tx_clk;
-  output            eth1_tx_ctl;
-  output            eth1_txd0;
-  output            eth1_txd1;
-  output            eth1_txd2;
-  output            eth1_txd3;
-  input             eth1_rx_clk;
-  input             eth1_rx_ctl;
-  input             eth1_rxd0;
-  input             eth1_rxd1;
-  input             eth1_rxd2;
-  input             eth1_rxd3;
-  output            eth1_mdc;
-  inout             eth1_mdio;
-  output            qspi_ss0;
-  output            qspi_clk;
-  inout             qspi_io0;
-  inout             qspi_io1;
-  inout             qspi_io2;
-  inout             qspi_io3;
-  output            sdio_clk;
-  inout             sdio_cmd;
-  inout             sdio_d0;
-  inout             sdio_d1;
-  inout             sdio_d2;
-  inout             sdio_d3;
-  input             usb1_clk;
-  output            usb1_stp;
-  input             usb1_dir;
-  input             usb1_nxt;
-  inout             usb1_d0;
-  inout             usb1_d1;
-  inout             usb1_d2;
-  inout             usb1_d3;
-  inout             usb1_d4;
-  inout             usb1_d5;
-  inout             usb1_d6;
-  inout             usb1_d7;
-  output            spim1_ss0;
-  output            spim1_clk;
-  output            spim1_mosi;
-  input             spim1_miso;
-  input             uart0_rx;
-  output            uart0_tx;
-
-  // board gpio
-
-  output  [  3:0]   led;
-  input   [  3:0]   push_buttons;
-  input   [  3:0]   dip_switches;
-
-  // display
-
-  output            vga_clk;
-  output            vga_blank_n;
-  output            vga_sync_n;
-  output            vga_hs;
-  output            vga_vs;
-  output  [  7:0]   vga_r;
-  output  [  7:0]   vga_g;
-  output  [  7:0]   vga_b;
-
-  // data interface
-
-  input             rx_clk_in;
-  input             rx_frame_in;
-  input   [  5:0]   rx_data_in;
-  output            tx_clk_out;
-  output            tx_frame_out;
-  output  [  5:0]   tx_data_out;
-
-  // gpio interface
-
-  output            ad9361_resetb;
-  output            ad9361_en_agc;
-  output            ad9361_sync;
-  output            ad9361_enable;
-  output            ad9361_txnrx;
+  output            ad9361_resetb,
+  output            ad9361_en_agc,
+  output            ad9361_sync,
 
   // spi interface
 
-  output            spi_csn;
-  output            spi_clk;
-  output            spi_mosi;
-  input             spi_miso;
-
-  // internal clocks and resets
-
-  wire    [ 31:0]   gpio_open;
-  wire              sys_resetn;
-  wire              clk;
+  output            spi_csn,
+  output            spi_clk,
+  output            spi_mosi,
+  input             spi_miso);
 
   // internal signals
 
-  wire              adc_enable_i0;
-  wire              adc_enable_q0;
-  wire              adc_enable_i1;
-  wire              adc_enable_q1;
-  wire              adc_valid_i0;
-  wire              adc_valid_q0;
-  wire              adc_valid_i1;
-  wire              adc_valid_q1;
-  wire              adc_dwr;
-  wire              adc_dsync;
-  wire    [ 15:0]   adc_chan_i0;
-  wire    [ 15:0]   adc_chan_q0;
-  wire    [ 15:0]   adc_chan_i1;
-  wire    [ 15:0]   adc_chan_q1;
-  wire    [ 63:0]   adc_ddata;
-  wire              adc_dovf;
-  wire              dac_enable_i0;
-  wire              dac_enable_q0;
-  wire              dac_enable_i1;
-  wire              dac_enable_q1;
-  wire              dac_valid_i0;
-  wire              dac_valid_q0;
-  wire              dac_valid_i1;
-  wire              dac_valid_q1;
-  wire    [ 15:0]   dac_data_i0;
-  wire    [ 15:0]   dac_data_q0;
-  wire    [ 15:0]   dac_data_i1;
-  wire    [ 15:0]   dac_data_q1;
-  wire    [ 63:0]   dac_ddata;
-  wire              dac_dunf;
-  wire              dac_rd_en;
-  wire              dac_fifo_valid;  
-  wire              vga_pixel_clock;
-  wire              vid_v_sync;
-  wire              vid_h_sync;
-  wire    [7:0]     vid_r,vid_g,vid_b;
+  wire              sys_resetn;
+  wire    [ 31:0]   sys_gpio_i;
+  wire    [ 31:0]   sys_gpio_o;
+  wire    [  4:0]   gpio;
 
   // defaults
+
+  assign gpio_bd_o = sys_gpio_o[3:0];
+
+  assign sys_gpio_i[31:8] = sys_gpio_o[31:8];
+  assign sys_gpio_i[ 7:0] = gpio_bd_i;
   
-  assign vga_clk = vga_pixel_clock;
   assign vga_blank_n = 1'b1;
   assign vga_sync_n = 1'b0;
-  assign vga_hs = vid_h_sync;
-  assign vga_vs = vid_v_sync;
-  assign {vga_b,vga_g,vga_r} =  {vid_b,vid_g,vid_r};
+
+  assign ad9361_resetb = gpio[4];
+  assign ad9361_en_agc = gpio[3];
+  assign ad9361_sync = gpio[2];
 
   // instantiations
 
-  sld_signaltap #(
-    .sld_advanced_trigger_entity ("basic,1,"),
-    .sld_data_bits (64),
-    .sld_data_bit_cntr_bits (7),
-    .sld_enable_advanced_trigger (0),
-    .sld_mem_address_bits (10),
-    .sld_node_crc_bits (32),
-    .sld_node_crc_hiword (13323),
-    .sld_node_crc_loword (24084),
-    .sld_node_info (1076736),
-    .sld_ram_block_type ("AUTO"),
-    .sld_sample_depth (1024),
-    .sld_storage_qualifier_gap_record (0),
-    .sld_storage_qualifier_mode ("OFF"),
-    .sld_trigger_bits (1),
-    .sld_trigger_in_enabled (0),
-    .sld_trigger_level (1),
-    .sld_trigger_level_pipeline (1))
-  i_ila_adc (
-    .acq_clk (clk),
-    .acq_data_in (adc_ddata),
-    .acq_trigger_in (adc_valid_i0));
-
   system_bd i_system_bd (
-    .clk_clk (sys_clk),
-    .reset_reset_n (sys_resetn),
-    .sys_hps_memory_mem_a (ddr3_a),
-    .sys_hps_memory_mem_ba (ddr3_ba),
-    .sys_hps_memory_mem_ck (ddr3_ck_p),
-    .sys_hps_memory_mem_ck_n (ddr3_ck_n),
-    .sys_hps_memory_mem_cke (ddr3_cke),
-    .sys_hps_memory_mem_cs_n (ddr3_cs_n),
-    .sys_hps_memory_mem_ras_n (ddr3_ras_n),
-    .sys_hps_memory_mem_cas_n (ddr3_cas_n),
-    .sys_hps_memory_mem_we_n (ddr3_we_n),
-    .sys_hps_memory_mem_reset_n (ddr3_reset_n),
-    .sys_hps_memory_mem_dq (ddr3_dq),
-    .sys_hps_memory_mem_dqs (ddr3_dqs_p),
-    .sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
-    .sys_hps_memory_mem_odt (ddr3_odt),
-    .sys_hps_memory_mem_dm (ddr3_dm),
-    .sys_hps_memory_oct_rzqin (ddr3_oct_rzqin),
-    .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
-    .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
-    .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
-    .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
-    .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
-    .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
-    .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
-    .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
-    .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
-    .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
-    .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
-    .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
-    .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
-    .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
-    .sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
-    .sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
-    .sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
-    .sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
-    .sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
-    .sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
-    .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
-    .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
-    .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
-    .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
-    .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
-    .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
-    .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
-    .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
-    .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
-    .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
-    .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
-    .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
-    .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
-    .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
-    .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
-    .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
-    .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
-    .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
-    .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
-    .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
-    .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
-    .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
-    .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
-    .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
-    .sys_gpio_external_connection_in_port ({16'd0, 4'd0, led, push_buttons, dip_switches}),
-    .sys_gpio_external_connection_out_port ({gpio_open[31:16], gpio_open[15:12], led, gpio_open[7:0]}),
-    .sys_hps_h2f_reset_reset_n (sys_resetn),
-    .sys_hps_spim0_txd (),
-    .sys_hps_spim0_rxd (),
-    .sys_hps_spim0_ss_in_n (1'b1),
-    .sys_hps_spim0_ssi_oe_n (),
-    .sys_hps_spim0_ss_0_n (),
-    .sys_hps_spim0_ss_1_n (),
-    .sys_hps_spim0_ss_2_n (),
-    .sys_hps_spim0_ss_3_n (),
-    .sys_hps_spim0_sclk_out_clk (),
-    .axi_ad9361_device_clock_clk (clk),
+    .axi_ad9361_delay_clk_clk (1'd0),
     .axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
-    .axi_ad9361_device_if_rx_clk_in_n (1'b0),
+    .axi_ad9361_device_if_rx_clk_in_n (1'd0),
     .axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
-    .axi_ad9361_device_if_rx_frame_in_n (1'b0),
+    .axi_ad9361_device_if_rx_frame_in_n (1'd0),
     .axi_ad9361_device_if_rx_data_in_p (rx_data_in),
     .axi_ad9361_device_if_rx_data_in_n (6'd0),
     .axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
@@ -422,23 +182,90 @@ module system_top (
     .axi_ad9361_device_if_tx_frame_out_n (),
     .axi_ad9361_device_if_tx_data_out_p (tx_data_out),
     .axi_ad9361_device_if_tx_data_out_n (),
-    .axi_ad9361_l_clk_clk (clk),
-    .spi_ad9361_external_MISO (spi_miso),
-    .spi_ad9361_external_MOSI (spi_mosi),
-    .spi_ad9361_external_SCLK (spi_clk),
-    .spi_ad9361_external_SS_n (spi_csn),
-    .vga_pixel_clock_bridge_out_clk_clk (vga_pixel_clock),
-    .vga_clock_video_output_clocked_video_vid_clk (vga_pixel_clock),
-    .vga_clock_video_output_clocked_video_vid_data ({vid_r,vid_g,vid_b}),
-    .vga_clock_video_output_clocked_video_underflow (),
-    .vga_clock_video_output_clocked_video_vid_datavalid (),
-    .vga_clock_video_output_clocked_video_vid_v_sync (vid_v_sync),
-    .vga_clock_video_output_clocked_video_vid_h_sync (vid_h_sync),
-    .vga_clock_video_output_clocked_video_vid_f (),
-    .vga_clock_video_output_clocked_video_vid_h (),
-    .vga_clock_video_output_clocked_video_vid_v (),
-    .gpio_external_connection_export ({ad9361_resetb, ad9361_en_agc, ad9361_sync, ad9361_enable, ad9361_txnrx})
-  );
+    .axi_ad9361_device_if_enable (enable),
+    .axi_ad9361_device_if_txnrx (txnrx),
+    .axi_ad9361_up_enable_up_enable (gpio[1]),
+    .axi_ad9361_up_txnrx_up_txnrx (gpio[0]),
+    .gpio_export (gpio),
+    .spi_MISO (spi_miso),
+    .spi_MOSI (spi_mosi),
+    .spi_SCLK (spi_clk),
+    .spi_SS_n (spi_csn),
+    .sys_clk_clk (sys_clk),
+    .sys_gpio_in_port (sys_gpio_i),
+    .sys_gpio_out_port (sys_gpio_o),
+    .sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
+    .sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
+    .sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
+    .sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
+    .sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
+    .sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
+    .sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
+    .sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
+    .sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
+    .sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
+    .sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
+    .sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
+    .sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
+    .sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
+    .sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]),
+    .sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]),
+    .sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]),
+    .sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]),
+    .sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
+    .sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
+    .sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
+    .sys_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
+    .sys_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
+    .sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
+    .sys_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
+    .sys_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
+    .sys_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
+    .sys_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
+    .sys_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
+    .sys_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
+    .sys_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
+    .sys_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
+    .sys_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
+    .sys_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
+    .sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
+    .sys_hps_io_hps_io_usb1_inst_STP (usb1_stp),
+    .sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
+    .sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
+    .sys_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
+    .sys_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
+    .sys_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
+    .sys_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
+    .sys_hps_io_hps_io_uart0_inst_RX (uart0_rx),
+    .sys_hps_io_hps_io_uart0_inst_TX (uart0_tx),
+    .sys_hps_mem_mem_a (ddr3_a),
+    .sys_hps_mem_mem_ba (ddr3_ba),
+    .sys_hps_mem_mem_ck (ddr3_ck_p),
+    .sys_hps_mem_mem_ck_n (ddr3_ck_n),
+    .sys_hps_mem_mem_cke (ddr3_cke),
+    .sys_hps_mem_mem_cs_n (ddr3_cs_n),
+    .sys_hps_mem_mem_ras_n (ddr3_ras_n),
+    .sys_hps_mem_mem_cas_n (ddr3_cas_n),
+    .sys_hps_mem_mem_we_n (ddr3_we_n),
+    .sys_hps_mem_mem_reset_n (ddr3_reset_n),
+    .sys_hps_mem_mem_dq (ddr3_dq),
+    .sys_hps_mem_mem_dqs (ddr3_dqs_p),
+    .sys_hps_mem_mem_dqs_n (ddr3_dqs_n),
+    .sys_hps_mem_mem_odt (ddr3_odt),
+    .sys_hps_mem_mem_dm (ddr3_dm),
+    .sys_hps_mem_oct_rzqin (ddr3_rzq),
+    .sys_hps_reset_reset_n (sys_resetn),
+    .sys_reset_reset_n (sys_resetn),
+    .vga_clk_clk (vga_clk),
+    .vga_if_vid_clk (vga_clk),
+    .vga_if_vid_data ({vga_red, vga_grn, vga_blu}),
+    .vga_if_underflow (),
+    .vga_if_vid_datavalid (),
+    .vga_if_vid_v_sync (vga_vsync),
+    .vga_if_vid_h_sync (vga_hsync),
+    .vga_if_vid_f (),
+    .vga_if_vid_h (),
+    .vga_if_vid_v ());
 
 endmodule
 
diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys
index ffbb1cae5..5d27c3c9e 100755
--- a/projects/arradio/common/arradio_bd.qsys
+++ b/projects/arradio/common/arradio_bd.qsys
@@ -9,19 +9,11 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element ad9361_clk_bridge
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
    element adc_pack
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "5";
          type = "int";
       }
       datum sopceditor_expanded
@@ -90,7 +82,7 @@
    {
       datum _sortIndex
       {
-         value = "5";
+         value = "4";
          type = "int";
       }
       datum sopceditor_expanded
@@ -111,7 +103,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "6";
          type = "int";
       }
       datum sopceditor_expanded
@@ -132,7 +124,7 @@
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "8";
          type = "int";
       }
       datum sopceditor_expanded
@@ -153,7 +145,7 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "7";
          type = "int";
       }
       datum sopceditor_expanded
@@ -166,7 +158,7 @@
    {
       datum _sortIndex
       {
-         value = "11";
+         value = "10";
          type = "int";
       }
    }
@@ -190,7 +182,7 @@
    {
       datum _sortIndex
       {
-         value = "10";
+         value = "9";
          type = "int";
       }
       datum sopceditor_expanded
@@ -245,25 +237,31 @@
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
-   name="axi_ad9361_device_clock"
-   internal="axi_ad9361.device_clock"
+   name="axi_ad9361_delay_clk"
+   internal="axi_ad9361.if_delay_clk"
    type="clock"
    dir="end" />
+ <interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
  <interface
    name="axi_ad9361_device_if"
    internal="axi_ad9361.device_if"
    type="conduit"
    dir="end" />
- <interface
-   name="axi_ad9361_l_clk"
-   internal="ad9361_clk_bridge.out_clk"
-   type="clock"
-   dir="start" />
  <interface
    name="axi_ad9361_s_axi"
    internal="axi_ad9361.s_axi"
    type="axi4lite"
    dir="end" />
+ <interface
+   name="axi_ad9361_up_enable"
+   internal="axi_ad9361.if_up_enable"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9361_up_txnrx"
+   internal="axi_ad9361.if_up_txnrx"
+   type="conduit"
+   dir="end" />
  <interface
    name="axi_dmac_adc_fifo_wr_clock"
    internal="axi_dmac_adc.fifo_wr_clock" />
@@ -327,21 +325,16 @@
    dir="end" />
  <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
  <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <module
-   name="ad9361_clk_bridge"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
  <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
   <parameter name="CHANNEL_DATA_WIDTH" value="16" />
   <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
  <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ADC_DATAPATH_DISABLE" value="0" />
+  <parameter name="CMOS_OR_LVDS_N" value="0" />
+  <parameter name="DAC_DATAPATH_DISABLE" value="0" />
+  <parameter name="DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="DEVICE_TYPE" value="1" />
   <parameter name="ID" value="0" />
  </module>
  <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
@@ -441,6 +434,11 @@
    version="15.1"
    start="axi_ad9361.if_l_clk"
    end="adc_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="axi_ad9361.if_l_clk"
+   end="axi_ad9361.if_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -456,22 +454,12 @@
    version="15.1"
    start="axi_ad9361.if_l_clk"
    end="axi_dmac_adc.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="ad9361_clk_bridge.in_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
    end="spi_ad9361.clk" />
  <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9361.delay_clock" />
  <connection
    kind="clock"
    version="15.1"

From e8fbdd0f5d275780943e97aff177123d3f9af78b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 3 May 2016 15:59:20 -0400
Subject: [PATCH 195/972] zcu102: zynq ultrascale

---
 projects/common/zcu102/zcu102_system_bd.tcl   | 214 ++++++++++++++++++
 .../common/zcu102/zcu102_system_constr.xdc    |  63 ++++++
 2 files changed, 277 insertions(+)
 create mode 100644 projects/common/zcu102/zcu102_system_bd.tcl
 create mode 100644 projects/common/zcu102/zcu102_system_constr.xdc

diff --git a/projects/common/zcu102/zcu102_system_bd.tcl b/projects/common/zcu102/zcu102_system_bd.tcl
new file mode 100644
index 000000000..49380211b
--- /dev/null
+++ b/projects/common/zcu102/zcu102_system_bd.tcl
@@ -0,0 +1,214 @@
+
+# create board design
+# default ports
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
+create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+
+create_bd_port -dir O spi0_csn_2_o
+create_bd_port -dir O spi0_csn_1_o
+create_bd_port -dir O spi0_csn_0_o
+create_bd_port -dir I spi0_csn_i
+create_bd_port -dir I spi0_clk_i
+create_bd_port -dir O spi0_clk_o
+create_bd_port -dir I spi0_sdo_i
+create_bd_port -dir O spi0_sdo_o
+create_bd_port -dir I spi0_sdi_i
+
+create_bd_port -dir O spi1_csn_2_o
+create_bd_port -dir O spi1_csn_1_o
+create_bd_port -dir O spi1_csn_0_o
+create_bd_port -dir I spi1_csn_i
+create_bd_port -dir I spi1_clk_i
+create_bd_port -dir O spi1_clk_o
+create_bd_port -dir I spi1_sdo_i
+create_bd_port -dir O spi1_sdo_o
+create_bd_port -dir I spi1_sdi_i
+
+create_bd_port -dir I -from 63 -to 0 gpio_i
+create_bd_port -dir O -from 63 -to 0 gpio_o
+create_bd_port -dir O -from 63 -to 0 gpio_t
+
+# hdmi interface
+
+create_bd_port -dir O hdmi_out_clk
+create_bd_port -dir O hdmi_hsync
+create_bd_port -dir O hdmi_vsync
+create_bd_port -dir O hdmi_data_e
+create_bd_port -dir O -from 23 -to 0 hdmi_data
+
+# spdif audio
+
+create_bd_port -dir O spdif
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_11
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+set_property -dict [list CONFIG.preset {ZC706}] $sys_ps7
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
+set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+# hdmi peripherals
+
+set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
+set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+
+set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
+set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
+set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
+set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
+
+# audio peripherals
+
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
+set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
+
+set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
+set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+
+# interface connections
+
+ad_connect  ddr sys_ps7/DDR
+ad_connect  gpio_i sys_ps7/GPIO_I
+ad_connect  gpio_o sys_ps7/GPIO_O
+ad_connect  gpio_t sys_ps7/GPIO_T
+ad_connect  fixed_io sys_ps7/FIXED_IO
+ad_connect  iic_main axi_iic_main/iic
+ad_connect  sys_200m_clk axi_hdmi_clkgen/clk
+
+# spi connections
+
+ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
+ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
+ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
+ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
+ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
+ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
+ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
+ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
+ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+
+ad_connect  spi1_csn_2_o sys_ps7/SPI1_SS2_O
+ad_connect  spi1_csn_1_o sys_ps7/SPI1_SS1_O
+ad_connect  spi1_csn_0_o sys_ps7/SPI1_SS_O
+ad_connect  spi1_csn_i sys_ps7/SPI1_SS_I
+ad_connect  spi1_clk_i sys_ps7/SPI1_SCLK_I
+ad_connect  spi1_clk_o sys_ps7/SPI1_SCLK_O
+ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
+ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
+ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
+
+# hdmi
+
+ad_connect  sys_cpu_clk axi_hdmi_core/vdma_clk
+ad_connect  sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
+ad_connect  axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
+ad_connect  axi_hdmi_core/hdmi_out_clk hdmi_out_clk
+ad_connect  axi_hdmi_core/hdmi_24_hsync hdmi_hsync
+ad_connect  axi_hdmi_core/hdmi_24_vsync hdmi_vsync
+ad_connect  axi_hdmi_core/hdmi_24_data_e hdmi_data_e
+ad_connect  axi_hdmi_core/hdmi_24_data hdmi_data
+ad_connect  axi_hdmi_core/vdma_valid axi_hdmi_dma/m_axis_mm2s_tvalid
+ad_connect  axi_hdmi_core/vdma_data axi_hdmi_dma/m_axis_mm2s_tdata
+ad_connect  axi_hdmi_core/vdma_ready axi_hdmi_dma/m_axis_mm2s_tready
+ad_connect  axi_hdmi_core/vdma_fs axi_hdmi_dma/mm2s_fsync
+ad_connect  axi_hdmi_core/vdma_fs axi_hdmi_core/vdma_fs_ret
+
+# spdif audio
+
+ad_connect  sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA0_ACLK
+ad_connect  sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
+ad_connect  sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
+ad_connect  sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
+ad_connect  sys_200m_clk sys_audio_clkgen/clk_in1
+ad_connect  sys_cpu_resetn sys_audio_clkgen/resetn
+ad_connect  sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
+ad_connect  spdif axi_spdif_tx_core/spdif_tx_o
+
+# interrupts
+
+ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
+ad_connect  sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
+ad_connect  sys_concat_intc/In13 ps_intr_13
+ad_connect  sys_concat_intc/In12 ps_intr_12
+ad_connect  sys_concat_intc/In11 ps_intr_11
+ad_connect  sys_concat_intc/In10 ps_intr_10
+ad_connect  sys_concat_intc/In9 ps_intr_09
+ad_connect  sys_concat_intc/In8 ps_intr_08
+ad_connect  sys_concat_intc/In7 ps_intr_07
+ad_connect  sys_concat_intc/In6 ps_intr_06
+ad_connect  sys_concat_intc/In5 ps_intr_05
+ad_connect  sys_concat_intc/In4 ps_intr_04
+ad_connect  sys_concat_intc/In3 ps_intr_03
+ad_connect  sys_concat_intc/In2 ps_intr_02
+ad_connect  sys_concat_intc/In1 ps_intr_01
+ad_connect  sys_concat_intc/In0 ps_intr_00
+
+# interconnects
+
+ad_cpu_interconnect 0x41600000 axi_iic_main
+ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
+ad_cpu_interconnect 0x43000000 axi_hdmi_dma
+ad_cpu_interconnect 0x70e00000 axi_hdmi_core
+ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
+ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
+ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
+
diff --git a/projects/common/zcu102/zcu102_system_constr.xdc b/projects/common/zcu102/zcu102_system_constr.xdc
new file mode 100644
index 000000000..e589dc33d
--- /dev/null
+++ b/projects/common/zcu102/zcu102_system_constr.xdc
@@ -0,0 +1,63 @@
+
+# constraints
+
+# hdmi
+
+set_property  -dict {PACKAGE_PIN  P28   IOSTANDARD LVCMOS25}           [get_ports hdmi_out_clk]
+set_property  -dict {PACKAGE_PIN  U21   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_vsync]
+set_property  -dict {PACKAGE_PIN  R22   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_hsync]
+set_property  -dict {PACKAGE_PIN  V24   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data_e]
+set_property  -dict {PACKAGE_PIN  U24   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[0]]
+set_property  -dict {PACKAGE_PIN  T22   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[1]]
+set_property  -dict {PACKAGE_PIN  R23   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[2]]
+set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[3]]
+set_property  -dict {PACKAGE_PIN  AE28  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[4]]
+set_property  -dict {PACKAGE_PIN  T23   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[5]]
+set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[6]]
+set_property  -dict {PACKAGE_PIN  T27   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[7]]
+set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[8]]
+set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[9]]
+set_property  -dict {PACKAGE_PIN  AA28  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[10]]
+set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[11]]
+set_property  -dict {PACKAGE_PIN  AE30  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[12]]
+set_property  -dict {PACKAGE_PIN  Y25   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[13]]
+set_property  -dict {PACKAGE_PIN  AA29  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[14]]
+set_property  -dict {PACKAGE_PIN  AD30  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[15]]
+set_property  -dict {PACKAGE_PIN  Y28   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[16]]
+set_property  -dict {PACKAGE_PIN  AF28  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[17]]
+set_property  -dict {PACKAGE_PIN  V22   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[18]]
+set_property  -dict {PACKAGE_PIN  AA27  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[19]]
+set_property  -dict {PACKAGE_PIN  U22   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[20]]
+set_property  -dict {PACKAGE_PIN  N28   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[21]]
+set_property  -dict {PACKAGE_PIN  V21   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[22]]
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[23]]
+
+# spdif
+
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD LVCMOS25} [get_ports spdif]
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  AJ14  IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  AJ18  IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]
+
+# gpio (switches, leds and such)
+
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]           ; ## GPIO_DIP_SW0
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]           ; ## GPIO_DIP_SW1
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]           ; ## GPIO_DIP_SW2
+set_property  -dict {PACKAGE_PIN  AJ13  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]           ; ## GPIO_DIP_SW3
+set_property  -dict {PACKAGE_PIN  AK25  IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]           ; ## GPIO_SW_LEFT
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]]           ; ## GPIO_SW_CENTER
+set_property  -dict {PACKAGE_PIN  R27   IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]           ; ## GPIO_SW_RIGHT
+
+set_property  -dict {PACKAGE_PIN  Y21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]           ; ## GPIO_LED_LEFT
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]]           ; ## GPIO_LED_CENTER
+set_property  -dict {PACKAGE_PIN  W21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]           ; ## GPIO_LED_RIGHT
+set_property  -dict {PACKAGE_PIN  A17   IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]]          ; ## GPIO_LED_0
+
+set_property  -dict {PACKAGE_PIN  H14   IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]]          ; ## XADC_GPIO_0
+set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]]          ; ## XADC_GPIO_1
+set_property  -dict {PACKAGE_PIN  J16   IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]]          ; ## XADC_GPIO_2
+set_property  -dict {PACKAGE_PIN  J14   IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]]          ; ## XADC_GPIO_3
+

From a6411dbd63c1e21226c809e3903fc889cb0a4ce5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 3 May 2016 16:02:40 -0400
Subject: [PATCH 196/972] zcu102- added

---
 projects/fmcomms2/zcu102/Makefile           |  83 +++++
 projects/fmcomms2/zcu102/system_bd.tcl      |   4 +
 projects/fmcomms2/zcu102/system_constr.xdc  |  76 +++++
 projects/fmcomms2/zcu102/system_project.tcl |  17 +
 projects/fmcomms2/zcu102/system_top.v       | 328 ++++++++++++++++++++
 5 files changed, 508 insertions(+)
 create mode 100644 projects/fmcomms2/zcu102/Makefile
 create mode 100755 projects/fmcomms2/zcu102/system_bd.tcl
 create mode 100644 projects/fmcomms2/zcu102/system_constr.xdc
 create mode 100755 projects/fmcomms2/zcu102/system_project.tcl
 create mode 100644 projects/fmcomms2/zcu102/system_top.v

diff --git a/projects/fmcomms2/zcu102/Makefile b/projects/fmcomms2/zcu102/Makefile
new file mode 100644
index 000000000..d3c52de44
--- /dev/null
+++ b/projects/fmcomms2/zcu102/Makefile
@@ -0,0 +1,83 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/fmcomms2_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zc706/zc706_system_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib fmcomms2_zc706.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+fmcomms2_zc706.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> fmcomms2_zc706_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/fmcomms2/zcu102/system_bd.tcl b/projects/fmcomms2/zcu102/system_bd.tcl
new file mode 100755
index 000000000..928d43c42
--- /dev/null
+++ b/projects/fmcomms2/zcu102/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
+source ../common/fmcomms2_bd.tcl
+
diff --git a/projects/fmcomms2/zcu102/system_constr.xdc b/projects/fmcomms2/zcu102/system_constr.xdc
new file mode 100644
index 000000000..2509dc955
--- /dev/null
+++ b/projects/fmcomms2/zcu102/system_constr.xdc
@@ -0,0 +1,76 @@
+
+# constraints
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p]        ; ## G6   FMC_LPC_LA00_CC_P
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n]        ; ## G7   FMC_LPC_LA00_CC_N
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p]      ; ## D8   FMC_LPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  AG15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n]      ; ## D9   FMC_LPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]    ; ## H7   FMC_LPC_LA02_P
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]    ; ## H8   FMC_LPC_LA02_N
+set_property  -dict {PACKAGE_PIN  AG12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]    ; ## G9   FMC_LPC_LA03_P
+set_property  -dict {PACKAGE_PIN  AH12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]    ; ## G10  FMC_LPC_LA03_N
+set_property  -dict {PACKAGE_PIN  AJ15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]    ; ## H10  FMC_LPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AK15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]    ; ## H11  FMC_LPC_LA04_N
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]    ; ## D11  FMC_LPC_LA05_P
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]    ; ## D12  FMC_LPC_LA05_N
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]    ; ## C10  FMC_LPC_LA06_P
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]    ; ## C11  FMC_LPC_LA06_N
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]    ; ## H13  FMC_LPC_LA07_P
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]    ; ## H14  FMC_LPC_LA07_N
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25} [get_ports tx_clk_out_p]                      ; ## G12  FMC_LPC_LA08_P
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVDS_25} [get_ports tx_clk_out_n]                      ; ## G13  FMC_LPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AH14  IOSTANDARD LVDS_25} [get_ports tx_frame_out_p]                    ; ## D14  FMC_LPC_LA09_P
+set_property  -dict {PACKAGE_PIN  AH13  IOSTANDARD LVDS_25} [get_ports tx_frame_out_n]                    ; ## D15  FMC_LPC_LA09_N
+set_property  -dict {PACKAGE_PIN  AJ16  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]]                  ; ## H16  FMC_LPC_LA11_P
+set_property  -dict {PACKAGE_PIN  AK16  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]]                  ; ## H17  FMC_LPC_LA11_N
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]]                  ; ## G15  FMC_LPC_LA12_P
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]]                  ; ## G16  FMC_LPC_LA12_N
+set_property  -dict {PACKAGE_PIN  AH17  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]]                  ; ## D17  FMC_LPC_LA13_P
+set_property  -dict {PACKAGE_PIN  AH16  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]]                  ; ## D18  FMC_LPC_LA13_N
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]]                  ; ## C14  FMC_LPC_LA10_P
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]]                  ; ## C15  FMC_LPC_LA10_N
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]]                  ; ## C18  FMC_LPC_LA14_P
+set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]]                  ; ## C19  FMC_LPC_LA14_N
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]]                  ; ## H19  FMC_LPC_LA15_P
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]]                  ; ## H20  FMC_LPC_LA15_N
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports enable]                           ; ## G18  FMC_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports txnrx]                            ; ## G19  FMC_LPC_LA16_N
+set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD LVCMOS25} [get_ports tdd_sync]                         ; ## PMOD1_5_LS
+
+set_property  -dict {PACKAGE_PIN  AG26  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                   ; ## G21  FMC_LPC_LA20_P
+set_property  -dict {PACKAGE_PIN  AG27  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                   ; ## G22  FMC_LPC_LA20_N
+set_property  -dict {PACKAGE_PIN  AH28  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                   ; ## H25  FMC_LPC_LA21_P
+set_property  -dict {PACKAGE_PIN  AH29  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                   ; ## H26  FMC_LPC_LA21_N
+set_property  -dict {PACKAGE_PIN  AK27  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                   ; ## G24  FMC_LPC_LA22_P
+set_property  -dict {PACKAGE_PIN  AK28  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                   ; ## G25  FMC_LPC_LA22_N
+set_property  -dict {PACKAGE_PIN  AJ26  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                   ; ## D23  FMC_LPC_LA23_P
+set_property  -dict {PACKAGE_PIN  AK26  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                   ; ## D24  FMC_LPC_LA23_N
+set_property  -dict {PACKAGE_PIN  AF30  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                      ; ## H28  FMC_LPC_LA24_P
+set_property  -dict {PACKAGE_PIN  AG30  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                      ; ## H29  FMC_LPC_LA24_N
+set_property  -dict {PACKAGE_PIN  AF29  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                      ; ## G27  FMC_LPC_LA25_P
+set_property  -dict {PACKAGE_PIN  AG29  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                      ; ## G28  FMC_LPC_LA25_N
+set_property  -dict {PACKAGE_PIN  AH26  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                      ; ## H22  FMC_LPC_LA19_P
+set_property  -dict {PACKAGE_PIN  AH27  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                        ; ## H23  FMC_LPC_LA19_N
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                      ; ## H31  FMC_LPC_LA28_P
+
+set_property  -dict {PACKAGE_PIN  AJ30  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]         ; ## D26  FMC_LPC_LA26_P
+set_property  -dict {PACKAGE_PIN  AK30  IOSTANDARD LVCMOS25} [get_ports spi_clk]                          ; ## D27  FMC_LPC_LA26_N
+set_property  -dict {PACKAGE_PIN  AJ28  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                         ; ## C26  FMC_LPC_LA27_P
+set_property  -dict {PACKAGE_PIN  AJ29  IOSTANDARD LVCMOS25} [get_ports spi_miso]                         ; ## C27  FMC_LPC_LA27_N
+
+# spi pmod J58
+
+set_property  -dict {PACKAGE_PIN  AJ21  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_udc_csn_tx]  ; ## PMOD1_0_LS
+set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_udc_csn_rx]  ; ## PMOD1_4_LS
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS25} [get_ports spi_udc_sclk]                     ; ## PMOD1_3_LS
+set_property  -dict {PACKAGE_PIN  AK21  IOSTANDARD LVCMOS25} [get_ports spi_udc_data]                     ; ## PMOD1_1_LS
+
+set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD LVCMOS25} [get_ports gpio_muxout_tx]                   ; ## PMOD1_2_LS
+set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD LVCMOS25} [get_ports gpio_muxout_rx]                   ; ## PMOD1_6_LS
+
+
+# clocks
+
+create_clock -name rx_clk       -period  4.00 [get_ports rx_clk_in_p]
+
diff --git a/projects/fmcomms2/zcu102/system_project.tcl b/projects/fmcomms2/zcu102/system_project.tcl
new file mode 100755
index 000000000..68b41d86f
--- /dev/null
+++ b/projects/fmcomms2/zcu102/system_project.tcl
@@ -0,0 +1,17 @@
+
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create fmcomms2_zc706
+adi_project_files fmcomms2_zc706 [list \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
+
+adi_project_run fmcomms2_zc706
+
+
diff --git a/projects/fmcomms2/zcu102/system_top.v b/projects/fmcomms2/zcu102/system_top.v
new file mode 100644
index 000000000..7f6b166b7
--- /dev/null
+++ b/projects/fmcomms2/zcu102/system_top.v
@@ -0,0 +1,328 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  gpio_bd,
+
+  hdmi_out_clk,
+  hdmi_vsync,
+  hdmi_hsync,
+  hdmi_data_e,
+  hdmi_data,
+
+  spdif,
+
+  iic_scl,
+  iic_sda,
+
+  rx_clk_in_p,
+  rx_clk_in_n,
+  rx_frame_in_p,
+  rx_frame_in_n,
+  rx_data_in_p,
+  rx_data_in_n,
+  tx_clk_out_p,
+  tx_clk_out_n,
+  tx_frame_out_p,
+  tx_frame_out_n,
+  tx_data_out_p,
+  tx_data_out_n,
+
+  enable,
+  txnrx,
+
+  tdd_sync,
+
+  gpio_muxout_tx,
+  gpio_muxout_rx,
+  gpio_resetb,
+  gpio_sync,
+  gpio_en_agc,
+  gpio_ctl,
+  gpio_status,
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  spi_udc_csn_tx,
+  spi_udc_csn_rx,
+  spi_udc_sclk,
+  spi_udc_data);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout   [14:0]  gpio_bd;
+
+  output          hdmi_out_clk;
+  output          hdmi_vsync;
+  output          hdmi_hsync;
+  output          hdmi_data_e;
+  output  [23:0]  hdmi_data;
+
+  output          spdif;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  input           rx_clk_in_p;
+  input           rx_clk_in_n;
+  input           rx_frame_in_p;
+  input           rx_frame_in_n;
+  input   [ 5:0]  rx_data_in_p;
+  input   [ 5:0]  rx_data_in_n;
+  output          tx_clk_out_p;
+  output          tx_clk_out_n;
+  output          tx_frame_out_p;
+  output          tx_frame_out_n;
+  output  [ 5:0]  tx_data_out_p;
+  output  [ 5:0]  tx_data_out_n;
+
+  output          enable;
+  output          txnrx;
+
+  inout           tdd_sync;
+
+  inout           gpio_muxout_tx;
+  inout           gpio_muxout_rx;
+  inout           gpio_resetb;
+  inout           gpio_sync;
+  inout           gpio_en_agc;
+  inout   [ 3:0]  gpio_ctl;
+  inout   [ 7:0]  gpio_status;
+
+  output          spi_csn;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  output          spi_udc_csn_tx;
+  output          spi_udc_csn_rx;
+  output          spi_udc_sclk;
+  output          spi_udc_data;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire            clk;
+  wire            dma_dac_dunf;
+  wire            core_dac_dunf;
+  wire    [63:0]  dma_dac_ddata;
+  wire    [63:0]  core_dac_ddata;
+  wire            dma_dac_en;
+  wire            core_dac_en;
+  wire            dma_dac_dvalid;
+  wire            core_dac_dvalid;
+  wire            dma_adc_ovf;
+  wire            core_adc_ovf;
+  wire    [63:0]  dma_adc_ddata;
+  wire    [63:0]  core_adc_ddata;
+  wire            dma_adc_dwr;
+  wire            core_adc_dwr;
+  wire            dma_adc_dsync;
+  wire            core_adc_dsync;
+  wire    [31:0]  adc_gpio_input;
+  wire    [31:0]  adc_gpio_output;
+  wire    [31:0]  dac_gpio_input;
+  wire    [31:0]  dac_gpio_output;
+  wire            tdd_sync_t;
+  wire            tdd_sync_o;
+  wire            tdd_sync_i;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
+    .dio_t ({gpio_t[50:49], gpio_t[46:32]}),
+    .dio_i ({gpio_o[50:49], gpio_o[46:32]}),
+    .dio_o ({gpio_i[50:49], gpio_i[46:32]}),
+    .dio_p ({ gpio_muxout_tx,     // 50:50
+              gpio_muxout_rx,     // 49:49
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
+    .dio_t (gpio_t[14:0]),
+    .dio_i (gpio_o[14:0]),
+    .dio_o (gpio_i[14:0]),
+    .dio_p (gpio_bd));
+
+  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
+    .dio_t (tdd_sync_t),
+    .dio_i (tdd_sync_o),
+    .dio_o (tdd_sync_i),
+    .dio_p (tdd_sync));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .spdif (spdif),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (spi_udc_sclk),
+    .spi1_csn_0_o (spi_udc_csn_tx),
+    .spi1_csn_1_o (spi_udc_csn_rx),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (spi_udc_data),
+    .spi1_sdo_o (spi_udc_data),
+    .tdd_sync_i (tdd_sync_i),
+    .tdd_sync_o (tdd_sync_o),
+    .tdd_sync_t (tdd_sync_t),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From e1350018da8afc6a4ae2ce016ec255df4ae4ccfc Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 10 May 2016 15:39:41 -0400
Subject: [PATCH 197/972] zcu102- updates

---
 projects/fmcomms2/zcu102/system_bd.tcl      |   2 +-
 projects/fmcomms2/zcu102/system_constr.xdc  | 118 ++++----
 projects/fmcomms2/zcu102/system_project.tcl |   8 +-
 projects/fmcomms2/zcu102/system_top.v       | 297 ++++----------------
 4 files changed, 114 insertions(+), 311 deletions(-)

diff --git a/projects/fmcomms2/zcu102/system_bd.tcl b/projects/fmcomms2/zcu102/system_bd.tcl
index 928d43c42..ffeb9f0ee 100755
--- a/projects/fmcomms2/zcu102/system_bd.tcl
+++ b/projects/fmcomms2/zcu102/system_bd.tcl
@@ -1,4 +1,4 @@
 
-source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
+source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
 source ../common/fmcomms2_bd.tcl
 
diff --git a/projects/fmcomms2/zcu102/system_constr.xdc b/projects/fmcomms2/zcu102/system_constr.xdc
index 2509dc955..921dc981b 100644
--- a/projects/fmcomms2/zcu102/system_constr.xdc
+++ b/projects/fmcomms2/zcu102/system_constr.xdc
@@ -2,73 +2,61 @@
 # constraints
 # ad9361
 
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p]        ; ## G6   FMC_LPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n]        ; ## G7   FMC_LPC_LA00_CC_N
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p]      ; ## D8   FMC_LPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN  AG15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n]      ; ## D9   FMC_LPC_LA01_CC_N
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]    ; ## H7   FMC_LPC_LA02_P
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]    ; ## H8   FMC_LPC_LA02_N
-set_property  -dict {PACKAGE_PIN  AG12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]    ; ## G9   FMC_LPC_LA03_P
-set_property  -dict {PACKAGE_PIN  AH12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]    ; ## G10  FMC_LPC_LA03_N
-set_property  -dict {PACKAGE_PIN  AJ15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]    ; ## H10  FMC_LPC_LA04_P
-set_property  -dict {PACKAGE_PIN  AK15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]    ; ## H11  FMC_LPC_LA04_N
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]    ; ## D11  FMC_LPC_LA05_P
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]    ; ## D12  FMC_LPC_LA05_N
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]    ; ## C10  FMC_LPC_LA06_P
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]    ; ## C11  FMC_LPC_LA06_N
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]    ; ## H13  FMC_LPC_LA07_P
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]    ; ## H14  FMC_LPC_LA07_N
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25} [get_ports tx_clk_out_p]                      ; ## G12  FMC_LPC_LA08_P
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVDS_25} [get_ports tx_clk_out_n]                      ; ## G13  FMC_LPC_LA08_N
-set_property  -dict {PACKAGE_PIN  AH14  IOSTANDARD LVDS_25} [get_ports tx_frame_out_p]                    ; ## D14  FMC_LPC_LA09_P
-set_property  -dict {PACKAGE_PIN  AH13  IOSTANDARD LVDS_25} [get_ports tx_frame_out_n]                    ; ## D15  FMC_LPC_LA09_N
-set_property  -dict {PACKAGE_PIN  AJ16  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]]                  ; ## H16  FMC_LPC_LA11_P
-set_property  -dict {PACKAGE_PIN  AK16  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]]                  ; ## H17  FMC_LPC_LA11_N
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]]                  ; ## G15  FMC_LPC_LA12_P
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]]                  ; ## G16  FMC_LPC_LA12_N
-set_property  -dict {PACKAGE_PIN  AH17  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]]                  ; ## D17  FMC_LPC_LA13_P
-set_property  -dict {PACKAGE_PIN  AH16  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]]                  ; ## D18  FMC_LPC_LA13_N
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]]                  ; ## C14  FMC_LPC_LA10_P
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]]                  ; ## C15  FMC_LPC_LA10_N
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]]                  ; ## C18  FMC_LPC_LA14_P
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]]                  ; ## C19  FMC_LPC_LA14_N
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]]                  ; ## H19  FMC_LPC_LA15_P
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]]                  ; ## H20  FMC_LPC_LA15_N
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports enable]                           ; ## G18  FMC_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports txnrx]                            ; ## G19  FMC_LPC_LA16_N
-set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD LVCMOS25} [get_ports tdd_sync]                         ; ## PMOD1_5_LS
+set_property  -dict {PACKAGE_PIN  Y4    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p]           ; ## G6   FMC_LPC_LA00_CC_P
+set_property  -dict {PACKAGE_PIN  Y3    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n]           ; ## G7   FMC_LPC_LA00_CC_N
+set_property  -dict {PACKAGE_PIN  W2    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p]         ; ## D8   FMC_LPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  W1    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n]         ; ## D9   FMC_LPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  V2    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]       ; ## H7   FMC_LPC_LA02_P
+set_property  -dict {PACKAGE_PIN  V1    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]       ; ## H8   FMC_LPC_LA02_N
+set_property  -dict {PACKAGE_PIN  Y2    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]       ; ## G9   FMC_LPC_LA03_P
+set_property  -dict {PACKAGE_PIN  Y1    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]       ; ## G10  FMC_LPC_LA03_N
+set_property  -dict {PACKAGE_PIN  AA2   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]       ; ## H10  FMC_LPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AA1   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]       ; ## H11  FMC_LPC_LA04_N
+set_property  -dict {PACKAGE_PIN  AB3   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]       ; ## D11  FMC_LPC_LA05_P
+set_property  -dict {PACKAGE_PIN  AC3   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]       ; ## D12  FMC_LPC_LA05_N
+set_property  -dict {PACKAGE_PIN  AC2   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]       ; ## C10  FMC_LPC_LA06_P
+set_property  -dict {PACKAGE_PIN  AC1   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]       ; ## C11  FMC_LPC_LA06_N
+set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]       ; ## H13  FMC_LPC_LA07_P
+set_property  -dict {PACKAGE_PIN  U4    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]       ; ## H14  FMC_LPC_LA07_N
+set_property  -dict {PACKAGE_PIN  V4    IOSTANDARD LVDS} [get_ports tx_clk_out_p]                         ; ## G12  FMC_LPC_LA08_P
+set_property  -dict {PACKAGE_PIN  V3    IOSTANDARD LVDS} [get_ports tx_clk_out_n]                         ; ## G13  FMC_LPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AB4   IOSTANDARD LVDS} [get_ports tx_frame_out_p]                       ; ## D14  FMC_LPC_LA09_P
+set_property  -dict {PACKAGE_PIN  AC4   IOSTANDARD LVDS} [get_ports tx_frame_out_n]                       ; ## D15  FMC_LPC_LA09_N
+set_property  -dict {PACKAGE_PIN  AB6   IOSTANDARD LVDS} [get_ports tx_data_out_p[0]]                     ; ## H16  FMC_LPC_LA11_P
+set_property  -dict {PACKAGE_PIN  AB5   IOSTANDARD LVDS} [get_ports tx_data_out_n[0]]                     ; ## H17  FMC_LPC_LA11_N
+set_property  -dict {PACKAGE_PIN  W7    IOSTANDARD LVDS} [get_ports tx_data_out_p[1]]                     ; ## G15  FMC_LPC_LA12_P
+set_property  -dict {PACKAGE_PIN  W6    IOSTANDARD LVDS} [get_ports tx_data_out_n[1]]                     ; ## G16  FMC_LPC_LA12_N
+set_property  -dict {PACKAGE_PIN  AB8   IOSTANDARD LVDS} [get_ports tx_data_out_p[2]]                     ; ## D17  FMC_LPC_LA13_P
+set_property  -dict {PACKAGE_PIN  AC8   IOSTANDARD LVDS} [get_ports tx_data_out_n[2]]                     ; ## D18  FMC_LPC_LA13_N
+set_property  -dict {PACKAGE_PIN  W5    IOSTANDARD LVDS} [get_ports tx_data_out_p[3]]                     ; ## C14  FMC_LPC_LA10_P
+set_property  -dict {PACKAGE_PIN  W4    IOSTANDARD LVDS} [get_ports tx_data_out_n[3]]                     ; ## C15  FMC_LPC_LA10_N
+set_property  -dict {PACKAGE_PIN  AC7   IOSTANDARD LVDS} [get_ports tx_data_out_p[4]]                     ; ## C18  FMC_LPC_LA14_P
+set_property  -dict {PACKAGE_PIN  AC6   IOSTANDARD LVDS} [get_ports tx_data_out_n[4]]                     ; ## C19  FMC_LPC_LA14_N
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD LVDS} [get_ports tx_data_out_p[5]]                     ; ## H19  FMC_LPC_LA15_P
+set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD LVDS} [get_ports tx_data_out_n[5]]                     ; ## H20  FMC_LPC_LA15_N
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD LVCMOS18} [get_ports enable]                           ; ## G18  FMC_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS18} [get_ports txnrx]                            ; ## G19  FMC_LPC_LA16_N
 
-set_property  -dict {PACKAGE_PIN  AG26  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                   ; ## G21  FMC_LPC_LA20_P
-set_property  -dict {PACKAGE_PIN  AG27  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                   ; ## G22  FMC_LPC_LA20_N
-set_property  -dict {PACKAGE_PIN  AH28  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                   ; ## H25  FMC_LPC_LA21_P
-set_property  -dict {PACKAGE_PIN  AH29  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                   ; ## H26  FMC_LPC_LA21_N
-set_property  -dict {PACKAGE_PIN  AK27  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                   ; ## G24  FMC_LPC_LA22_P
-set_property  -dict {PACKAGE_PIN  AK28  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                   ; ## G25  FMC_LPC_LA22_N
-set_property  -dict {PACKAGE_PIN  AJ26  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                   ; ## D23  FMC_LPC_LA23_P
-set_property  -dict {PACKAGE_PIN  AK26  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                   ; ## D24  FMC_LPC_LA23_N
-set_property  -dict {PACKAGE_PIN  AF30  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                      ; ## H28  FMC_LPC_LA24_P
-set_property  -dict {PACKAGE_PIN  AG30  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                      ; ## H29  FMC_LPC_LA24_N
-set_property  -dict {PACKAGE_PIN  AF29  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                      ; ## G27  FMC_LPC_LA25_P
-set_property  -dict {PACKAGE_PIN  AG29  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                      ; ## G28  FMC_LPC_LA25_N
-set_property  -dict {PACKAGE_PIN  AH26  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                      ; ## H22  FMC_LPC_LA19_P
-set_property  -dict {PACKAGE_PIN  AH27  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                        ; ## H23  FMC_LPC_LA19_N
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                      ; ## H31  FMC_LPC_LA28_P
-
-set_property  -dict {PACKAGE_PIN  AJ30  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]         ; ## D26  FMC_LPC_LA26_P
-set_property  -dict {PACKAGE_PIN  AK30  IOSTANDARD LVCMOS25} [get_ports spi_clk]                          ; ## D27  FMC_LPC_LA26_N
-set_property  -dict {PACKAGE_PIN  AJ28  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                         ; ## C26  FMC_LPC_LA27_P
-set_property  -dict {PACKAGE_PIN  AJ29  IOSTANDARD LVCMOS25} [get_ports spi_miso]                         ; ## C27  FMC_LPC_LA27_N
-
-# spi pmod J58
-
-set_property  -dict {PACKAGE_PIN  AJ21  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_udc_csn_tx]  ; ## PMOD1_0_LS
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_udc_csn_rx]  ; ## PMOD1_4_LS
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS25} [get_ports spi_udc_sclk]                     ; ## PMOD1_3_LS
-set_property  -dict {PACKAGE_PIN  AK21  IOSTANDARD LVCMOS25} [get_ports spi_udc_data]                     ; ## PMOD1_1_LS
-
-set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD LVCMOS25} [get_ports gpio_muxout_tx]                   ; ## PMOD1_2_LS
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD LVCMOS25} [get_ports gpio_muxout_rx]                   ; ## PMOD1_6_LS
+set_property  -dict {PACKAGE_PIN  N13   IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]                   ; ## G21  FMC_LPC_LA20_P
+set_property  -dict {PACKAGE_PIN  M13   IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]                   ; ## G22  FMC_LPC_LA20_N
+set_property  -dict {PACKAGE_PIN  P12   IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]                   ; ## H25  FMC_LPC_LA21_P
+set_property  -dict {PACKAGE_PIN  N12   IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]                   ; ## H26  FMC_LPC_LA21_N
+set_property  -dict {PACKAGE_PIN  M15   IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]                   ; ## G24  FMC_LPC_LA22_P
+set_property  -dict {PACKAGE_PIN  M14   IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]                   ; ## G25  FMC_LPC_LA22_N
+set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]                   ; ## D23  FMC_LPC_LA23_P
+set_property  -dict {PACKAGE_PIN  K16   IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]                   ; ## D24  FMC_LPC_LA23_N
+set_property  -dict {PACKAGE_PIN  L12   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]                      ; ## H28  FMC_LPC_LA24_P
+set_property  -dict {PACKAGE_PIN  K12   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]                      ; ## H29  FMC_LPC_LA24_N
+set_property  -dict {PACKAGE_PIN  M11   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]                      ; ## G27  FMC_LPC_LA25_P
+set_property  -dict {PACKAGE_PIN  L11   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]                      ; ## G28  FMC_LPC_LA25_N
+set_property  -dict {PACKAGE_PIN  L13   IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]                      ; ## H22  FMC_LPC_LA19_P
+set_property  -dict {PACKAGE_PIN  K13   IOSTANDARD LVCMOS18} [get_ports gpio_sync]                        ; ## H23  FMC_LPC_LA19_N
+set_property  -dict {PACKAGE_PIN  T7    IOSTANDARD LVCMOS18} [get_ports gpio_resetb]                      ; ## H31  FMC_LPC_LA28_P
 
+set_property  -dict {PACKAGE_PIN  N9    IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]         ; ## D26  FMC_LPC_LA26_P
+set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD LVCMOS18} [get_ports spi_clk]                          ; ## D27  FMC_LPC_LA26_N
+set_property  -dict {PACKAGE_PIN  M10   IOSTANDARD LVCMOS18} [get_ports spi_mosi]                         ; ## C26  FMC_LPC_LA27_P
+set_property  -dict {PACKAGE_PIN  L10   IOSTANDARD LVCMOS18} [get_ports spi_miso]                         ; ## C27  FMC_LPC_LA27_N
 
 # clocks
 
diff --git a/projects/fmcomms2/zcu102/system_project.tcl b/projects/fmcomms2/zcu102/system_project.tcl
index 68b41d86f..6997e3d28 100755
--- a/projects/fmcomms2/zcu102/system_project.tcl
+++ b/projects/fmcomms2/zcu102/system_project.tcl
@@ -5,13 +5,13 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create fmcomms2_zc706
-adi_project_files fmcomms2_zc706 [list \
+adi_project_create fmcomms2_zcu102
+adi_project_files fmcomms2_zcu102 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
 
-adi_project_run fmcomms2_zc706
+adi_project_run fmcomms2_zcu102
 
 
diff --git a/projects/fmcomms2/zcu102/system_top.v b/projects/fmcomms2/zcu102/system_top.v
index 7f6b166b7..4ae6455bb 100644
--- a/projects/fmcomms2/zcu102/system_top.v
+++ b/projects/fmcomms2/zcu102/system_top.v
@@ -39,239 +39,63 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  input   [12:0]  gpio_bd_i,
+  output  [ 7:0]  gpio_bd_o,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
 
-  gpio_bd,
+  output          enable,
+  output          txnrx,
 
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
+  output          gpio_resetb,
+  output          gpio_sync,
+  output          gpio_en_agc,
+  output  [ 3:0]  gpio_ctl,
+  input   [ 7:0]  gpio_status,
 
-  spdif,
-
-  iic_scl,
-  iic_sda,
-
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
-
-  enable,
-  txnrx,
-
-  tdd_sync,
-
-  gpio_muxout_tx,
-  gpio_muxout_rx,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
-
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
-
-  spi_udc_csn_tx,
-  spi_udc_csn_rx,
-  spi_udc_sclk,
-  spi_udc_data);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout   [14:0]  gpio_bd;
-
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [23:0]  hdmi_data;
-
-  output          spdif;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  output          enable;
-  output          txnrx;
-
-  inout           tdd_sync;
-
-  inout           gpio_muxout_tx;
-  inout           gpio_muxout_rx;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
-
-  output          spi_udc_csn_tx;
-  output          spi_udc_csn_rx;
-  output          spi_udc_sclk;
-  output          spi_udc_data;
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso);
 
   // internal signals
 
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire            clk;
-  wire            dma_dac_dunf;
-  wire            core_dac_dunf;
-  wire    [63:0]  dma_dac_ddata;
-  wire    [63:0]  core_dac_ddata;
-  wire            dma_dac_en;
-  wire            core_dac_en;
-  wire            dma_dac_dvalid;
-  wire            core_dac_dvalid;
-  wire            dma_adc_ovf;
-  wire            core_adc_ovf;
-  wire    [63:0]  dma_adc_ddata;
-  wire    [63:0]  core_adc_ddata;
-  wire            dma_adc_dwr;
-  wire            core_adc_dwr;
-  wire            dma_adc_dsync;
-  wire            core_adc_dsync;
-  wire    [31:0]  adc_gpio_input;
-  wire    [31:0]  adc_gpio_output;
-  wire    [31:0]  dac_gpio_input;
-  wire    [31:0]  dac_gpio_output;
-  wire            tdd_sync_t;
-  wire            tdd_sync_o;
-  wire            tdd_sync_i;
+  wire    [95:0]  gpio_i;
+  wire    [95:0]  gpio_o;
+  wire    [ 2:0]  spi0_csn;
+
+  // defaults
+
+  assign gpio_resetb = gpio_o[46:46];
+  assign gpio_sync = gpio_o[45:45];
+  assign gpio_en_agc = gpio_o[44:44];
+  assign gpio_ctl = gpio_o[43:40];
+  assign gpio_bd_o = gpio_o[20:13];
+
+  assign gpio_i[95:40] = gpio_o[95:40];
+  assign gpio_i[39:32] = gpio_status;
+  assign gpio_i[31:13] = gpio_o[31:13];
+  assign gpio_i[12: 0] = gpio_bd_i;
+
+  assign spi_csn = spi0_csn[0];
 
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
-    .dio_t ({gpio_t[50:49], gpio_t[46:32]}),
-    .dio_i ({gpio_o[50:49], gpio_o[46:32]}),
-    .dio_o ({gpio_i[50:49], gpio_i[46:32]}),
-    .dio_p ({ gpio_muxout_tx,     // 50:50
-              gpio_muxout_rx,     // 49:49
-              gpio_resetb,        // 46:46
-              gpio_sync,          // 45:45
-              gpio_en_agc,        // 44:44
-              gpio_ctl,           // 43:40
-              gpio_status}));     // 39:32
-
-  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
-    .dio_t (gpio_t[14:0]),
-    .dio_i (gpio_o[14:0]),
-    .dio_o (gpio_i[14:0]),
-    .dio_p (gpio_bd));
-
-  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
-    .dio_t (tdd_sync_t),
-    .dio_i (tdd_sync_o),
-    .dio_o (tdd_sync_i),
-    .dio_p (tdd_sync));
-
   system_wrapper i_system_wrapper (
-    .ddr_addr (ddr_addr),
-    .ddr_ba (ddr_ba),
-    .ddr_cas_n (ddr_cas_n),
-    .ddr_ck_n (ddr_ck_n),
-    .ddr_ck_p (ddr_ck_p),
-    .ddr_cke (ddr_cke),
-    .ddr_cs_n (ddr_cs_n),
-    .ddr_dm (ddr_dm),
-    .ddr_dq (ddr_dq),
-    .ddr_dqs_n (ddr_dqs_n),
-    .ddr_dqs_p (ddr_dqs_p),
-    .ddr_odt (ddr_odt),
-    .ddr_ras_n (ddr_ras_n),
-    .ddr_reset_n (ddr_reset_n),
-    .ddr_we_n (ddr_we_n),
     .enable (enable),
-    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
-    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
-    .fixed_io_mio (fixed_io_mio),
-    .fixed_io_ps_clk (fixed_io_ps_clk),
-    .fixed_io_ps_porb (fixed_io_ps_porb),
-    .fixed_io_ps_srstb (fixed_io_ps_srstb),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
-    .gpio_t (gpio_t),
-    .hdmi_data (hdmi_data),
-    .hdmi_data_e (hdmi_data_e),
-    .hdmi_hsync (hdmi_hsync),
-    .hdmi_out_clk (hdmi_out_clk),
-    .hdmi_vsync (hdmi_vsync),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
     .ps_intr_00 (1'b0),
     .ps_intr_01 (1'b0),
     .ps_intr_02 (1'b0),
@@ -284,34 +108,25 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
+    .ps_intr_14 (1'b0),
+    .ps_intr_15 (1'b0),
     .rx_clk_in_n (rx_clk_in_n),
     .rx_clk_in_p (rx_clk_in_p),
     .rx_data_in_n (rx_data_in_n),
     .rx_data_in_p (rx_data_in_p),
     .rx_frame_in_n (rx_frame_in_n),
     .rx_frame_in_p (rx_frame_in_p),
-    .spdif (spdif),
-    .spi0_clk_i (1'b0),
-    .spi0_clk_o (spi_clk),
-    .spi0_csn_0_o (spi_csn),
-    .spi0_csn_1_o (),
-    .spi0_csn_2_o (),
-    .spi0_csn_i (1'b1),
-    .spi0_sdi_i (spi_miso),
-    .spi0_sdo_i (1'b0),
-    .spi0_sdo_o (spi_mosi),
-    .spi1_clk_i (1'b0),
-    .spi1_clk_o (spi_udc_sclk),
-    .spi1_csn_0_o (spi_udc_csn_tx),
-    .spi1_csn_1_o (spi_udc_csn_rx),
-    .spi1_csn_2_o (),
-    .spi1_csn_i (1'b1),
-    .spi1_sdi_i (1'b0),
-    .spi1_sdo_i (spi_udc_data),
-    .spi1_sdo_o (spi_udc_data),
-    .tdd_sync_i (tdd_sync_i),
-    .tdd_sync_o (tdd_sync_o),
-    .tdd_sync_t (tdd_sync_t),
+    .spi0_csn (spi0_csn),
+    .spi0_miso (spi_miso),
+    .spi0_mosi (spi_mosi),
+    .spi0_sclk (spi_clk),
+    .spi1_csn (),
+    .spi1_miso (1'b0),
+    .spi1_mosi (),
+    .spi1_sclk (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
     .tx_clk_out_n (tx_clk_out_n),
     .tx_clk_out_p (tx_clk_out_p),
     .tx_data_out_n (tx_data_out_n),

From aadb220a3f94a9db1c503fd79a6be88bdabe4b7a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 10 May 2016 15:40:12 -0400
Subject: [PATCH 198/972] zcu102- updates

---
 library/scripts/adi_ip.tcl | 156 ++++++++++++++++---------------------
 1 file changed, 67 insertions(+), 89 deletions(-)

diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl
index f9d416a59..a765ca247 100644
--- a/library/scripts/adi_ip.tcl
+++ b/library/scripts/adi_ip.tcl
@@ -77,31 +77,7 @@ proc adi_ip_bd {ip_name ip_bd_files} {
 
 proc adi_ip_properties {ip_name} {
 
-  ipx::package_project -root_dir .
-
-  set_property vendor {analog.com} [ipx::current_core]
-  set_property library {user} [ipx::current_core]
-  set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
-  set_property vendor_display_name {Analog Devices} [ipx::current_core]
-  set_property company_url {www.analog.com} [ipx::current_core]
-
-  set_property supported_families \
-    {{kintexu}    {Pre-Production} \
-     {virtexu}    {Pre-Production} \
-     {virtex7}    {Production} \
-     {qvirtex7}   {Production} \
-     {kintex7}    {Production} \
-     {kintex7l}   {Production} \
-     {qkintex7}   {Production} \
-     {qkintex7l}  {Production} \
-     {artix7}     {Production} \
-     {artix7l}    {Production} \
-     {aartix7}    {Production} \
-     {qartix7}    {Production} \
-     {zynq}       {Production} \
-     {qzynq}      {Production} \
-     {azynq}      {Production}} \
-  [ipx::current_core]
+  adi_ip_properties_lite $ip_name
 
   ipx::remove_all_bus_interface [ipx::current_core]
   ipx::infer_bus_interface {\
@@ -139,10 +115,10 @@ proc adi_ip_properties {ip_name} {
     -of_objects [ipx::get_bus_interfaces s_axi_aclk \
     -of_objects [ipx::current_core]]]
 
-    ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
-    ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
-    ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
-    ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
+  ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
+  ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
+  ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
+  ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
 }
 
 proc adi_ip_properties_lite {ip_name} {
@@ -155,91 +131,93 @@ proc adi_ip_properties_lite {ip_name} {
   set_property vendor_display_name {Analog Devices} [ipx::current_core]
   set_property company_url {www.analog.com} [ipx::current_core]
 
-  set_property supported_families \
-    {{kintexu}    {Pre-Production} \
-     {virtexu}    {Pre-Production} \
-     {virtex7}    {Production} \
-     {qvirtex7}   {Production} \
-     {kintex7}    {Production} \
-     {kintex7l}   {Production} \
-     {qkintex7}   {Production} \
-     {qkintex7l}  {Production} \
-     {artix7}     {Production} \
-     {artix7l}    {Production} \
-     {aartix7}    {Production} \
-     {qartix7}    {Production} \
-     {zynq}       {Production} \
-     {qzynq}      {Production} \
-     {azynq}      {Production}} \
+  set_property supported_families {\
+    virtex7       Production
+    qvirtex7      Production
+    kintex7       Production
+    kintex7l      Production
+    qkintex7      Production
+    qkintex7l     Production
+    artix7        Production
+    artix7l       Production
+    aartix7       Production
+    qartix7       Production
+    zynq          Production
+    qzynq         Production
+    azynq         Production
+    virtexu       Production
+    kintexuplus   Production
+    zynquplus     Production
+    kintexu       Production}\
   [ipx::current_core]
 }
 
 proc adi_set_ports_dependency {port_prefix dependency} {
-	foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
-		set_property ENABLEMENT_DEPENDENCY $dependency $port
-	}
+  foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
+    set_property ENABLEMENT_DEPENDENCY $dependency $port
+  }
 }
 
 proc adi_set_bus_dependency {bus prefix dependency} {
-	set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
-	adi_set_ports_dependency $prefix $dependency
+  set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
+  adi_set_ports_dependency $prefix $dependency
 }
 
 proc adi_add_port_map {bus phys logic} {
-	set map [ipx::add_port_map $phys $bus]
-	set_property "PHYSICAL_NAME" $phys $map
-	set_property "LOGICAL_NAME" $logic $map
+  set map [ipx::add_port_map $phys $bus]
+  set_property "PHYSICAL_NAME" $phys $map
+  set_property "LOGICAL_NAME" $logic $map
 }
 
 proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
-	set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
+  set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
 
-	set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
-	set_property "BUS_TYPE_VLNV" $bus_type $bus
-	set_property "INTERFACE_MODE" $mode $bus
+  set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
+  set_property "BUS_TYPE_VLNV" $bus_type $bus
+  set_property "INTERFACE_MODE" $mode $bus
 
-	foreach port_map $port_maps {
-		adi_add_port_map $bus {*}$port_map
-	}
+  foreach port_map $port_maps {
+    adi_add_port_map $bus {*}$port_map
+  }
 }
 
 proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
-	set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
-	set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
-	set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
-	set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
-	set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
-	set_property display_name $clock_inf_name $clock_inf
-	set clock_map [ipx::add_port_map "CLK" $clock_inf]
-	set_property physical_name $clock_signal_name $clock_map
+  set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
+  set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
+  set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
+  set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
+  set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
+  set_property display_name $clock_inf_name $clock_inf
+  set clock_map [ipx::add_port_map "CLK" $clock_inf]
+  set_property physical_name $clock_signal_name $clock_map
 
-	set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
-	set_property value $bus_inf_name $assoc_busif
+  set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
+  set_property value $bus_inf_name $assoc_busif
 
-	if { $reset_signal_name != "" } {
-		set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
-		set_property value $reset_signal_name $assoc_reset
+  if { $reset_signal_name != "" } {
+    set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
+    set_property value $reset_signal_name $assoc_reset
 
-		set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
-		set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
-		set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
-		set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
-		set_property display_name $reset_inf_name $reset_inf
-		set_property interface_mode $reset_signal_mode $reset_inf
-		set reset_map [ipx::add_port_map "RST" $reset_inf]
-		set_property physical_name $reset_signal_name $reset_map
+    set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
+    set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
+    set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
+    set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
+    set_property display_name $reset_inf_name $reset_inf
+    set_property interface_mode $reset_signal_mode $reset_inf
+    set reset_map [ipx::add_port_map "RST" $reset_inf]
+    set_property physical_name $reset_signal_name $reset_map
 
-		set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
-		set_property value "ACTIVE_LOW" $reset_polarity
-	}
+    set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
+    set_property value "ACTIVE_LOW" $reset_polarity
+  }
 }
 
 proc adi_ip_add_core_dependencies {vlnvs} {
-	foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
-		foreach vlnv $vlnvs {
-			ipx::add_subcore $vlnv $file_group
-		}
-	}
+  foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
+    foreach vlnv $vlnvs {
+      ipx::add_subcore $vlnv $file_group
+    }
+  }
 }
 
 proc adi_if_define {name} {

From 16e3a0e56999ade8a8669066474b6e762aae23c8 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 10 May 2016 15:40:21 -0400
Subject: [PATCH 199/972] zcu102- updates

---
 projects/scripts/adi_board.tcl   | 131 +++++++++++++++++++++++++------
 projects/scripts/adi_project.tcl |   5 ++
 2 files changed, 112 insertions(+), 24 deletions(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index c5a5762d8..6454d2079 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -115,7 +115,7 @@ proc ad_mem_hp0_interconnect {p_clk p_name} {
 
   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
-  if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
+  if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
 }
 
 proc ad_mem_hp1_interconnect {p_clk p_name} {
@@ -124,7 +124,7 @@ proc ad_mem_hp1_interconnect {p_clk p_name} {
 
   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
-  if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
+  if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
 }
 
 proc ad_mem_hp2_interconnect {p_clk p_name} {
@@ -133,7 +133,7 @@ proc ad_mem_hp2_interconnect {p_clk p_name} {
 
   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
-  if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
+  if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
 }
 
 proc ad_mem_hp3_interconnect {p_clk p_name} {
@@ -142,7 +142,7 @@ proc ad_mem_hp3_interconnect {p_clk p_name} {
 
   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
-  if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
+  if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
 }
 
 ###################################################################################################
@@ -158,6 +158,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
   global sys_hp3_interconnect_index
   global sys_mem_interconnect_index
 
+  set p_name_int $p_name
   set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
 
   if {$p_sel eq "MEM"} {
@@ -169,8 +170,9 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
   }
 
-  if {$p_sel eq "HP0"} {
+  if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
     if {$sys_hp0_interconnect_index < 0} {
+      set p_name_int sys_ps7/S_AXI_HP0
       set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
       create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp0_interconnect
     }
@@ -179,8 +181,9 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
   }
 
-  if {$p_sel eq "HP1"} {
+  if {($p_sel eq "HP1") && ($sys_zynq == 1)} {
     if {$sys_hp1_interconnect_index < 0} {
+      set p_name_int sys_ps7/S_AXI_HP1
       set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
       create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp1_interconnect
     }
@@ -189,8 +192,9 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
   }
 
-  if {$p_sel eq "HP2"} {
+  if {($p_sel eq "HP2") && ($sys_zynq == 1)} {
     if {$sys_hp2_interconnect_index < 0} {
+      set p_name_int sys_ps7/S_AXI_HP2
       set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
       create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp2_interconnect
     }
@@ -199,8 +203,9 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
   }
 
-  if {$p_sel eq "HP3"} {
+  if {($p_sel eq "HP3") && ($sys_zynq == 1)} {
     if {$sys_hp3_interconnect_index < 0} {
+      set p_name_int sys_ps7/S_AXI_HP3
       set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
       create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp3_interconnect
     }
@@ -209,6 +214,50 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
   }
 
+  if {($p_sel eq "HP0") && ($sys_zynq == 2)} {
+    if {$sys_hp0_interconnect_index < 0} {
+      set p_name_int sys_ps8/S_AXI_HP0_FPD
+      set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
+      create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp0_interconnect
+    }
+    set m_interconnect_index $sys_hp0_interconnect_index
+    set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
+    set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP0_FPD/PLLPD_DDR_LOW]
+  }
+
+  if {($p_sel eq "HP1") && ($sys_zynq == 2)} {
+    if {$sys_hp1_interconnect_index < 0} {
+      set p_name_int sys_ps8/S_AXI_HP1_FPD
+      set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
+      create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp1_interconnect
+    }
+    set m_interconnect_index $sys_hp1_interconnect_index
+    set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
+    set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP1_FPD/HP0_DDR_LOW]
+  }
+
+  if {($p_sel eq "HP2") && ($sys_zynq == 2)} {
+    if {$sys_hp2_interconnect_index < 0} {
+      set p_name_int sys_ps8/S_AXI_HP2_FPD
+      set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
+      create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp2_interconnect
+    }
+    set m_interconnect_index $sys_hp2_interconnect_index
+    set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
+    set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP2_FPD/HP1_DDR_LOW]
+  }
+
+  if {($p_sel eq "HP3") && ($sys_zynq == 2)} {
+    if {$sys_hp3_interconnect_index < 0} {
+      set p_name_int sys_ps8/S_AXI_HP3_FPD
+      set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
+      create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp3_interconnect
+    }
+    set m_interconnect_index $sys_hp3_interconnect_index
+    set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
+    set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP3_FPD/HP2_DDR_LOW]
+  }
+
   set i_str "S$m_interconnect_index"
   if {$m_interconnect_index < 10} {
     set i_str "S0$m_interconnect_index"
@@ -216,8 +265,8 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
 
   set m_interconnect_index [expr $m_interconnect_index + 1]
 
-  set p_intf_name [lrange [split $p_name "/"] end end]
-  set p_cell_name [lrange [split $p_name "/"] 0 0]
+  set p_intf_name [lrange [split $p_name_int "/"] end end]
+  set p_cell_name [lrange [split $p_name_int "/"] 0 0]
   set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
     CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
     CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
@@ -233,7 +282,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     ad_connect $p_clk $m_interconnect_cell/ACLK
     ad_connect sys_cpu_resetn $m_interconnect_cell/M00_ARESETN
     ad_connect $p_clk $m_interconnect_cell/M00_ACLK
-    ad_connect $m_interconnect_cell/M00_AXI $p_name
+    ad_connect $m_interconnect_cell/M00_AXI $p_name_int
     if {$p_intf_clock ne ""} {
       ad_connect $p_clk $p_intf_clock
     }
@@ -241,7 +290,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
     ad_connect sys_cpu_resetn $m_interconnect_cell/${i_str}_ARESETN
     ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
-    ad_connect $m_interconnect_cell/${i_str}_AXI $p_name
+    ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
     if {$p_intf_clock ne ""} {
       ad_connect $p_clk $p_intf_clock
     }
@@ -274,6 +323,14 @@ proc ad_cpu_interconnect {p_address p_name} {
 
   if {$sys_cpu_interconnect_index == 0} {
     create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect
+    if {$sys_zynq == 2} {
+      ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
+      ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
+      ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
+      ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
+      ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
+      ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
+    }
     if {$sys_zynq == 1} {
       ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
@@ -281,7 +338,8 @@ proc ad_cpu_interconnect {p_address p_name} {
       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
       ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
-    } else {
+    }
+    if {$sys_zynq == 0} {
       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
@@ -290,9 +348,13 @@ proc ad_cpu_interconnect {p_address p_name} {
     }
   }
 
+  if {$sys_zynq == 2} {
+    set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
+  }
   if {$sys_zynq == 1} {
     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
-  } else {
+  }
+  if {$sys_zynq == 0} {
     set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
   }
 
@@ -336,7 +398,7 @@ proc ad_cpu_interconnect {p_address p_name} {
   set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
   set p_index 0
   foreach p_seg_name $p_seg {
-    if {$p_index == 0} {
+    if {($p_index == 0) && ($sys_zynq < 2)} {
       set p_seg_range [get_property range $p_seg_name]
       create_bd_addr_seg -range $p_seg_range \
         -offset $p_address $sys_addr_cntrl_space \
@@ -355,18 +417,39 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
 
   global sys_zynq
 
-  if {$sys_zynq == 1} {
-    set p_index [regsub -all {[^0-9]} $p_ps_index ""]
-  } else {
-    set p_index [regsub -all {[^0-9]} $p_mb_index ""]
+  if {$sys_zynq == 0} {set p_index_int $p_mb_index}
+  if {$sys_zynq >= 1} {set p_index_int $p_ps_index}
+
+  set p_index [regsub -all {[^0-9]} $p_index_int ""]
+  set m_index [expr ($p_index - 8)]
+
+  if {($sys_zynq == 2) && ($p_index <= 7)} {
+    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]] 
+    set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc_0/In$p_index]]
+
+    puts "delete_bd_objs $p_net $p_pin"
+    delete_bd_objs $p_net $p_pin
+    ad_connect sys_concat_intc_0/In$p_index $p_name
   }
 
-  set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]] 
-  set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc/In$p_index]]
+  if {($sys_zynq == 2) && ($p_index >= 8)} {
+    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]] 
+    set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc_1/In$m_index]]
 
-  puts "delete_bd_objs $p_net $p_pin"
-  delete_bd_objs $p_net $p_pin
-  ad_connect sys_concat_intc/In$p_index $p_name
+    puts "delete_bd_objs $p_net $p_pin"
+    delete_bd_objs $p_net $p_pin
+    ad_connect sys_concat_intc_1/In$m_index $p_name
+  }
+
+  if {$sys_zynq <= 1} {
+
+    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]] 
+    set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc/In$p_index]]
+
+    puts "delete_bd_objs $p_net $p_pin"
+    delete_bd_objs $p_net $p_pin
+    ad_connect sys_concat_intc/In$p_index $p_name
+  }
 }
 
 ###################################################################################################
diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index 335ed839b..91144dc7d 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -85,6 +85,11 @@ proc adi_project_create {project_name {mode 0}} {
     set p_board "not-applicable"
     set sys_zynq 1
   }
+  if [regexp "_zcu102$" $project_name] {
+    set p_device "xczu9eg-ffvb1156-1-i-EVAL"
+    set p_board "not-applicable"
+    set sys_zynq 2
+  }
 
   if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} {
     return -code error [format "ERROR: This project requires Vivado %s." $REQUIRED_VIVADO_VERSION]

From f3f5353944387030bc65881469d2efda51088073 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 10 May 2016 15:40:32 -0400
Subject: [PATCH 200/972] zcu102- updates

---
 projects/common/zcu102/zcu102_system_bd.tcl   | 519 ++++++++++++------
 .../common/zcu102/zcu102_system_constr.xdc    |  78 +--
 2 files changed, 375 insertions(+), 222 deletions(-)

diff --git a/projects/common/zcu102/zcu102_system_bd.tcl b/projects/common/zcu102/zcu102_system_bd.tcl
index 49380211b..07895c315 100644
--- a/projects/common/zcu102/zcu102_system_bd.tcl
+++ b/projects/common/zcu102/zcu102_system_bd.tcl
@@ -2,45 +2,18 @@
 # create board design
 # default ports
 
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
-create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+create_bd_port -dir O -from 2 -to 0 spi0_csn
+create_bd_port -dir O spi0_sclk
+create_bd_port -dir O spi0_mosi
+create_bd_port -dir I spi0_miso
 
-create_bd_port -dir O spi0_csn_2_o
-create_bd_port -dir O spi0_csn_1_o
-create_bd_port -dir O spi0_csn_0_o
-create_bd_port -dir I spi0_csn_i
-create_bd_port -dir I spi0_clk_i
-create_bd_port -dir O spi0_clk_o
-create_bd_port -dir I spi0_sdo_i
-create_bd_port -dir O spi0_sdo_o
-create_bd_port -dir I spi0_sdi_i
+create_bd_port -dir O -from 2 -to 0 spi1_csn
+create_bd_port -dir O spi1_sclk
+create_bd_port -dir O spi1_mosi
+create_bd_port -dir I spi1_miso
 
-create_bd_port -dir O spi1_csn_2_o
-create_bd_port -dir O spi1_csn_1_o
-create_bd_port -dir O spi1_csn_0_o
-create_bd_port -dir I spi1_csn_i
-create_bd_port -dir I spi1_clk_i
-create_bd_port -dir O spi1_clk_o
-create_bd_port -dir I spi1_sdo_i
-create_bd_port -dir O spi1_sdo_o
-create_bd_port -dir I spi1_sdi_i
-
-create_bd_port -dir I -from 63 -to 0 gpio_i
-create_bd_port -dir O -from 63 -to 0 gpio_o
-create_bd_port -dir O -from 63 -to 0 gpio_t
-
-# hdmi interface
-
-create_bd_port -dir O hdmi_out_clk
-create_bd_port -dir O hdmi_hsync
-create_bd_port -dir O hdmi_vsync
-create_bd_port -dir O hdmi_data_e
-create_bd_port -dir O -from 23 -to 0 hdmi_data
-
-# spdif audio
-
-create_bd_port -dir O spdif
+create_bd_port -dir I -from 95 -to 0 gpio_i
+create_bd_port -dir O -from 95 -to 0 gpio_o
 
 # interrupts
 
@@ -58,157 +31,373 @@ create_bd_port -dir I -type intr ps_intr_10
 create_bd_port -dir I -type intr ps_intr_11
 create_bd_port -dir I -type intr ps_intr_12
 create_bd_port -dir I -type intr ps_intr_13
+create_bd_port -dir I -type intr ps_intr_14
+create_bd_port -dir I -type intr ps_intr_15
 
-# instance: sys_ps7
+# instance: sys_ps8
 
-set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
-set_property -dict [list CONFIG.preset {ZC706}] $sys_ps7
-set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+set sys_ps8  [create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:1.0 sys_ps8]
 
-set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
-set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
+# defaults -- remove after board is supported in the tool
+set_property -dict [list\
+  CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+  CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+  CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+  CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+  CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+  CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+  CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
+  CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+  CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+  CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+  CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+  CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
+  CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
+  CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+  CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+  CONFIG.PSU__SD1__GRP_POW__ENABLE {1} \
+  CONFIG.PSU__SD1__GRP_POW__IO {MIO 43} \
+  CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
+  CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
+  CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+  CONFIG.PSU__SD1__SLOT_TYPE {SD} \
+  CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+  CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+  CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+  CONFIG.PSU__USE__M_AXI_GP2 {1} \
+  CONFIG.PSU__MAXIGP2__DATA_WIDTH {64} \
+  CONFIG.PSU__GT__LANE0_REF_SEL {Ref Clk0} \
+  CONFIG.PSU__GT__LANE1_REF_SEL {Ref Clk0} \
+  CONFIG.PSU__GT__LANE2_REF_SEL {Ref Clk2} \
+  CONFIG.PSU__GT__LANE3_REF_SEL {Ref Clk1} \
+  CONFIG.PSU__GT__REF_SEL0 {100} \
+  CONFIG.PSU__GT__REF_SEL1 {100} \
+  CONFIG.PSU__GT__REF_SEL2 {26} \
+  CONFIG.PSU__GT__REF_SEL3 {125} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
+  CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
+  CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
+  CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
+  CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
+  CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
+  CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
+  CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
+  CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
+  CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
+  CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \
+  CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
+  CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+  CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+  CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+  CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+  CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+  CONFIG.PSU__DDRC__VREF {1} \
+  CONFIG.PSU__DDRC__ECC {0} \
+  CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+  CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \
+  CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+  CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+  CONFIG.PSU__DDRC__FREQ_MHZ {1066.50} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+  CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+  CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+  CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \
+  CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+  CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+  CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+  CONFIG.PSU__DDRC__CL {15} \
+  CONFIG.PSU__DDRC__T_RCD {15} \
+  CONFIG.PSU__DDRC__T_RP {15} \
+  CONFIG.PSU__DDRC__CWL {14} \
+  CONFIG.PSU__DDRC__AL {0} \
+  CONFIG.PSU__DDRC__BL {8} \
+  CONFIG.PSU__DDRC__T_RC {46.5} \
+  CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+  CONFIG.PSU__DDRC__T_FAW {21.0} \
+  CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
+  CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+  CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {0} \
+  CONFIG.PSU__DDRC__RD_DBI_ENABLE {0} \
+  CONFIG.PSU__DDRC__WR_DBI_ENABLE {0} \
+  CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+  CONFIG.PSU__DDRC__DATA_MASK {1} \
+  CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+  CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+  CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+  CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+  CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+  CONFIG.PSU__DDRC__BRC_MAPPING {0} \
+  CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+  CONFIG.PSU__DDRC__FGRM {0} \
+  CONFIG.PSU__DDRC__LP_ASR {0} \
+  CONFIG.PSU__DDRC__UDIMM_INDICATOR {1} \
+  CONFIG.PSU__DDRC__RDIMM_INDICATOR {0} \
+  CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+  CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+  CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+  CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+  CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {66} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {57} \
+  CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.508} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {72} \
+  CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__SRCSEL {VPLL} \
+  CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DBG_FPD__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {39} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {17} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRF_APB__DPDMA__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__GDMA__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {4} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__ADMA__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__DBG_LPD__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__PCAP__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+] $sys_ps8
 
-set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
-set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+set_property CONFIG.PSU__USE__M_AXI_GP2 {1} $sys_ps8
+set_property CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} $sys_ps8
+set_property CONFIG.PSU__FPGA_PL0_ENABLE {1} $sys_ps8
+set_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} $sys_ps8
+set_property CONFIG.PSU__FPGA_PL1_ENABLE {1} $sys_ps8
+set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {200} $sys_ps8
+set_property CONFIG.PSU__USE__IRQ0 {1} $sys_ps8
+set_property CONFIG.PSU__USE__IRQ1 {1} $sys_ps8
+set_property CONFIG.PSU__GPIO0_EMIO__PERIPHERAL__ENABLE {1} $sys_ps8
+
+set_property -dict [list\
+  CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
+  CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \
+] $sys_ps8
 
 set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
 set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
 
-# hdmi peripherals
-
-set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
-set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
-
-set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
-set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
-set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
-set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
-
-# audio peripherals
-
-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
-set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
-set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
-set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
-set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
-
-set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
-set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
-set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
-
 # system reset/clock definitions
 
-ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
-ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_clk sys_ps8/pl_clk0
+ad_connect  sys_200m_clk sys_ps8/pl_clk1
 ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
 ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
 ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
-ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+ad_connect  sys_rstgen/ext_reset_in GND
 
-# interface connections
+# gpio
 
-ad_connect  ddr sys_ps7/DDR
-ad_connect  gpio_i sys_ps7/GPIO_I
-ad_connect  gpio_o sys_ps7/GPIO_O
-ad_connect  gpio_t sys_ps7/GPIO_T
-ad_connect  fixed_io sys_ps7/FIXED_IO
-ad_connect  iic_main axi_iic_main/iic
-ad_connect  sys_200m_clk axi_hdmi_clkgen/clk
+ad_connect  gpio_i sys_ps8/emio_gpio_i
+ad_connect  gpio_o sys_ps8/emio_gpio_o
 
-# spi connections
+# spi
 
-ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
-ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
-ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
-ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
-ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
-ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
-ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
-ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
-ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+ad_connect  sys_ps8/emio_spi0_ss_i_n VCC
+ad_connect  sys_ps8/emio_spi0_sclk_i sys_ps8/emio_spi0_sclk_o
+ad_connect  sys_ps8/emio_spi0_m_i sys_ps8/emio_spi0_m_o
 
-ad_connect  spi1_csn_2_o sys_ps7/SPI1_SS2_O
-ad_connect  spi1_csn_1_o sys_ps7/SPI1_SS1_O
-ad_connect  spi1_csn_0_o sys_ps7/SPI1_SS_O
-ad_connect  spi1_csn_i sys_ps7/SPI1_SS_I
-ad_connect  spi1_clk_i sys_ps7/SPI1_SCLK_I
-ad_connect  spi1_clk_o sys_ps7/SPI1_SCLK_O
-ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
-ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
-ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
+ad_connect  spi0_csn sys_ps8/emio_spi0_ss_o_n
+ad_connect  spi0_sclk sys_ps8/emio_spi0_sclk_o
+ad_connect  spi0_mosi sys_ps8/emio_spi0_m_o
+ad_connect  spi0_miso sys_ps8/emio_spi0_s_i
 
-# hdmi
+ad_connect  sys_ps8/emio_spi1_ss_i_n VCC
+ad_connect  sys_ps8/emio_spi1_sclk_i sys_ps8/emio_spi1_sclk_o
+ad_connect  sys_ps8/emio_spi1_m_i sys_ps8/emio_spi1_m_o
 
-ad_connect  sys_cpu_clk axi_hdmi_core/vdma_clk
-ad_connect  sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
-ad_connect  axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
-ad_connect  axi_hdmi_core/hdmi_out_clk hdmi_out_clk
-ad_connect  axi_hdmi_core/hdmi_24_hsync hdmi_hsync
-ad_connect  axi_hdmi_core/hdmi_24_vsync hdmi_vsync
-ad_connect  axi_hdmi_core/hdmi_24_data_e hdmi_data_e
-ad_connect  axi_hdmi_core/hdmi_24_data hdmi_data
-ad_connect  axi_hdmi_core/vdma_valid axi_hdmi_dma/m_axis_mm2s_tvalid
-ad_connect  axi_hdmi_core/vdma_data axi_hdmi_dma/m_axis_mm2s_tdata
-ad_connect  axi_hdmi_core/vdma_ready axi_hdmi_dma/m_axis_mm2s_tready
-ad_connect  axi_hdmi_core/vdma_fs axi_hdmi_dma/mm2s_fsync
-ad_connect  axi_hdmi_core/vdma_fs axi_hdmi_core/vdma_fs_ret
-
-# spdif audio
-
-ad_connect  sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
-ad_connect  sys_cpu_clk sys_ps7/DMA0_ACLK
-ad_connect  sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
-ad_connect  sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
-ad_connect  sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
-ad_connect  sys_200m_clk sys_audio_clkgen/clk_in1
-ad_connect  sys_cpu_resetn sys_audio_clkgen/resetn
-ad_connect  sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
-ad_connect  spdif axi_spdif_tx_core/spdif_tx_o
+ad_connect  spi1_csn sys_ps8/emio_spi1_ss_o_n
+ad_connect  spi1_sclk sys_ps8/emio_spi1_sclk_o
+ad_connect  spi1_mosi sys_ps8/emio_spi1_m_o
+ad_connect  spi1_miso sys_ps8/emio_spi1_s_i
 
 # interrupts
 
-ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
-ad_connect  sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
-ad_connect  sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
-ad_connect  sys_concat_intc/In13 ps_intr_13
-ad_connect  sys_concat_intc/In12 ps_intr_12
-ad_connect  sys_concat_intc/In11 ps_intr_11
-ad_connect  sys_concat_intc/In10 ps_intr_10
-ad_connect  sys_concat_intc/In9 ps_intr_09
-ad_connect  sys_concat_intc/In8 ps_intr_08
-ad_connect  sys_concat_intc/In7 ps_intr_07
-ad_connect  sys_concat_intc/In6 ps_intr_06
-ad_connect  sys_concat_intc/In5 ps_intr_05
-ad_connect  sys_concat_intc/In4 ps_intr_04
-ad_connect  sys_concat_intc/In3 ps_intr_03
-ad_connect  sys_concat_intc/In2 ps_intr_02
-ad_connect  sys_concat_intc/In1 ps_intr_01
-ad_connect  sys_concat_intc/In0 ps_intr_00
+set sys_concat_intc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0]
+set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc_0
 
-# interconnects
+set sys_concat_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1]
+set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc_1
 
-ad_cpu_interconnect 0x41600000 axi_iic_main
-ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
-ad_cpu_interconnect 0x43000000 axi_hdmi_dma
-ad_cpu_interconnect 0x70e00000 axi_hdmi_core
-ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
-ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
-ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
+ad_connect  sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
+ad_connect  sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
+
+ad_connect  sys_concat_intc_1/In7 ps_intr_15
+ad_connect  sys_concat_intc_1/In6 ps_intr_14
+ad_connect  sys_concat_intc_1/In5 ps_intr_13
+ad_connect  sys_concat_intc_1/In4 ps_intr_12
+ad_connect  sys_concat_intc_1/In3 ps_intr_11
+ad_connect  sys_concat_intc_1/In2 ps_intr_10
+ad_connect  sys_concat_intc_1/In1 ps_intr_09
+ad_connect  sys_concat_intc_1/In0 ps_intr_08
+ad_connect  sys_concat_intc_0/In7 ps_intr_07
+ad_connect  sys_concat_intc_0/In6 ps_intr_06
+ad_connect  sys_concat_intc_0/In5 ps_intr_05
+ad_connect  sys_concat_intc_0/In4 ps_intr_04
+ad_connect  sys_concat_intc_0/In3 ps_intr_03
+ad_connect  sys_concat_intc_0/In2 ps_intr_02
+ad_connect  sys_concat_intc_0/In1 ps_intr_01
+ad_connect  sys_concat_intc_0/In0 ps_intr_00
 
diff --git a/projects/common/zcu102/zcu102_system_constr.xdc b/projects/common/zcu102/zcu102_system_constr.xdc
index e589dc33d..19740608b 100644
--- a/projects/common/zcu102/zcu102_system_constr.xdc
+++ b/projects/common/zcu102/zcu102_system_constr.xdc
@@ -1,63 +1,27 @@
 
 # constraints
-
-# hdmi
-
-set_property  -dict {PACKAGE_PIN  P28   IOSTANDARD LVCMOS25}           [get_ports hdmi_out_clk]
-set_property  -dict {PACKAGE_PIN  U21   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_vsync]
-set_property  -dict {PACKAGE_PIN  R22   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_hsync]
-set_property  -dict {PACKAGE_PIN  V24   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data_e]
-set_property  -dict {PACKAGE_PIN  U24   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[0]]
-set_property  -dict {PACKAGE_PIN  T22   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[1]]
-set_property  -dict {PACKAGE_PIN  R23   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[2]]
-set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[3]]
-set_property  -dict {PACKAGE_PIN  AE28  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[4]]
-set_property  -dict {PACKAGE_PIN  T23   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[5]]
-set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[6]]
-set_property  -dict {PACKAGE_PIN  T27   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[7]]
-set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[8]]
-set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[9]]
-set_property  -dict {PACKAGE_PIN  AA28  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[10]]
-set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[11]]
-set_property  -dict {PACKAGE_PIN  AE30  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[12]]
-set_property  -dict {PACKAGE_PIN  Y25   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[13]]
-set_property  -dict {PACKAGE_PIN  AA29  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[14]]
-set_property  -dict {PACKAGE_PIN  AD30  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[15]]
-set_property  -dict {PACKAGE_PIN  Y28   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[16]]
-set_property  -dict {PACKAGE_PIN  AF28  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[17]]
-set_property  -dict {PACKAGE_PIN  V22   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[18]]
-set_property  -dict {PACKAGE_PIN  AA27  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[19]]
-set_property  -dict {PACKAGE_PIN  U22   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[20]]
-set_property  -dict {PACKAGE_PIN  N28   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[21]]
-set_property  -dict {PACKAGE_PIN  V21   IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[22]]
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS25  IOB TRUE} [get_ports hdmi_data[23]]
-
-# spdif
-
-set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD LVCMOS25} [get_ports spdif]
-
-# iic
-
-set_property  -dict {PACKAGE_PIN  AJ14  IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]
-set_property  -dict {PACKAGE_PIN  AJ18  IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]
-
 # gpio (switches, leds and such)
 
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]           ; ## GPIO_DIP_SW0
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]           ; ## GPIO_DIP_SW1
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]           ; ## GPIO_DIP_SW2
-set_property  -dict {PACKAGE_PIN  AJ13  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]           ; ## GPIO_DIP_SW3
-set_property  -dict {PACKAGE_PIN  AK25  IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]           ; ## GPIO_SW_LEFT
-set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]]           ; ## GPIO_SW_CENTER
-set_property  -dict {PACKAGE_PIN  R27   IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]           ; ## GPIO_SW_RIGHT
+set_property  -dict {PACKAGE_PIN  AN14  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[0]]           ; ## GPIO_DIP_SW0
+set_property  -dict {PACKAGE_PIN  AP14  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[1]]           ; ## GPIO_DIP_SW1
+set_property  -dict {PACKAGE_PIN  AM14  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[2]]           ; ## GPIO_DIP_SW2
+set_property  -dict {PACKAGE_PIN  AN13  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[3]]           ; ## GPIO_DIP_SW3
+set_property  -dict {PACKAGE_PIN  AN12  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[4]]           ; ## GPIO_DIP_SW4
+set_property  -dict {PACKAGE_PIN  AP12  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[5]]           ; ## GPIO_DIP_SW5
+set_property  -dict {PACKAGE_PIN  AL13  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[6]]           ; ## GPIO_DIP_SW6
+set_property  -dict {PACKAGE_PIN  AK13  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[7]]           ; ## GPIO_DIP_SW7
+set_property  -dict {PACKAGE_PIN  AE14  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[8]]           ; ## GPIO_SW_E
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[9]]           ; ## GPIO_SW_S
+set_property  -dict {PACKAGE_PIN  AG15  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[10]]          ; ## GPIO_SW_N
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[11]]          ; ## GPIO_SW_W
+set_property  -dict {PACKAGE_PIN  AG13  IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[12]]          ; ## GPIO_SW_C
 
-set_property  -dict {PACKAGE_PIN  Y21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]           ; ## GPIO_LED_LEFT
-set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]]           ; ## GPIO_LED_CENTER
-set_property  -dict {PACKAGE_PIN  W21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]           ; ## GPIO_LED_RIGHT
-set_property  -dict {PACKAGE_PIN  A17   IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]]          ; ## GPIO_LED_0
-
-set_property  -dict {PACKAGE_PIN  H14   IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]]          ; ## XADC_GPIO_0
-set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]]          ; ## XADC_GPIO_1
-set_property  -dict {PACKAGE_PIN  J16   IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]]          ; ## XADC_GPIO_2
-set_property  -dict {PACKAGE_PIN  J14   IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]]          ; ## XADC_GPIO_3
+set_property  -dict {PACKAGE_PIN  AG14  IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[0]]           ; ## GPIO_LED_0
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[1]]           ; ## GPIO_LED_1
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[2]]           ; ## GPIO_LED_2
+set_property  -dict {PACKAGE_PIN  AJ14  IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[3]]           ; ## GPIO_LED_3
+set_property  -dict {PACKAGE_PIN  AJ15  IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[4]]           ; ## GPIO_LED_4
+set_property  -dict {PACKAGE_PIN  AH13  IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[5]]           ; ## GPIO_LED_5
+set_property  -dict {PACKAGE_PIN  AH14  IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[6]]           ; ## GPIO_LED_6
+set_property  -dict {PACKAGE_PIN  AL12  IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[7]]           ; ## GPIO_LED_7
 

From 72151bb1a6b9f14baeab810ecefe94ddf8e30e2f Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 13 May 2016 18:44:41 +0300
Subject: [PATCH 201/972] a10gx: Updated base design to include MMU

---
 projects/common/a10gx/a10gx_system_bd.qsys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys
index 7bdd08068..9cb193b00 100644
--- a/projects/common/a10gx/a10gx_system_bd.qsys
+++ b/projects/common/a10gx/a10gx_system_bd.qsys
@@ -803,7 +803,7 @@
   <parameter name="mmu_TLBMissExcOffset" value="4096" />
   <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
   <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_enabled" value="true" />
   <parameter name="mmu_processIDNumBits" value="8" />
   <parameter name="mmu_ramBlockType" value="Automatic" />
   <parameter name="mmu_tlbNumWays" value="16" />

From 31671bf9d5238ca4c796addecb1aa0c1e07c26a0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 10:45:33 -0400
Subject: [PATCH 202/972] util_rfifo: constraints

---
 library/util_rfifo/util_rfifo_constr.sdc | 5 +++++
 library/util_rfifo/util_rfifo_constr.xdc | 9 +++++++++
 2 files changed, 14 insertions(+)
 create mode 100644 library/util_rfifo/util_rfifo_constr.sdc
 create mode 100644 library/util_rfifo/util_rfifo_constr.xdc

diff --git a/library/util_rfifo/util_rfifo_constr.sdc b/library/util_rfifo/util_rfifo_constr.sdc
new file mode 100644
index 000000000..121bac542
--- /dev/null
+++ b/library/util_rfifo/util_rfifo_constr.sdc
@@ -0,0 +1,5 @@
+
+set_false_path -from [get_registers *dout_enable*]  -to [get_registers *din_enable_m1*]
+set_false_path -from [get_registers *dout_req_t*]   -to [get_registers *din_req_t_m1*]
+set_false_path -from [get_registers *din_unf*]      -to [get_registers *dout_unf_m1*]
+
diff --git a/library/util_rfifo/util_rfifo_constr.xdc b/library/util_rfifo/util_rfifo_constr.xdc
new file mode 100644
index 000000000..cb8c395cf
--- /dev/null
+++ b/library/util_rfifo/util_rfifo_constr.xdc
@@ -0,0 +1,9 @@
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *din_enable_m*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *din_req_t_m*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_unf_m*}]
+
+set_false_path -from [get_cells -hier -filter {name =~ *dout_enable*  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_enable_m1*  && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *dout_req_t*   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_req_t_m1*   && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *din_unf*      && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_unf_m1*    && IS_SEQUENTIAL}]
+

From 82d43783f1adf323c67a8dddce9b1d3c5b2d2089 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 10:50:04 -0400
Subject: [PATCH 203/972] util_rfifo: altera ip

---
 library/util_rfifo/util_rfifo_hw.tcl | 212 +++++++++++++++++++++++++++
 1 file changed, 212 insertions(+)
 create mode 100755 library/util_rfifo/util_rfifo_hw.tcl

diff --git a/library/util_rfifo/util_rfifo_hw.tcl b/library/util_rfifo/util_rfifo_hw.tcl
new file mode 100755
index 000000000..4bd0df673
--- /dev/null
+++ b/library/util_rfifo/util_rfifo_hw.tcl
@@ -0,0 +1,212 @@
+
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+set_module_property NAME util_rfifo
+set_module_property DESCRIPTION "Utils Write FIFO"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME util_rfifo
+set_module_property ELABORATION_CALLBACK p_util_rfifo
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
+set_fileset_property quartus_synth TOP_LEVEL util_rfifo
+add_fileset_file ad_mem.v               VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
+add_fileset_file util_rfifo.v           VERILOG PATH util_rfifo.v TOP_LEVEL_FILE
+add_fileset_file util_rfifo_constr.sdc  SDC     PATH util_rfifo_constr.xdc
+
+# parameters
+
+add_parameter NUM_OF_CHANNELS INTEGER 0
+set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 4
+set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS
+set_parameter_property NUM_OF_CHANNELS TYPE INTEGER
+set_parameter_property NUM_OF_CHANNELS UNITS None
+set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
+
+add_parameter DIN_DATA_WIDTH INTEGER 0
+set_parameter_property DIN_DATA_WIDTH DEFAULT_VALUE 32
+set_parameter_property DIN_DATA_WIDTH DISPLAY_NAME DIN_DATA_WIDTH
+set_parameter_property DIN_DATA_WIDTH TYPE INTEGER
+set_parameter_property DIN_DATA_WIDTH UNITS None
+set_parameter_property DIN_DATA_WIDTH HDL_PARAMETER true
+
+add_parameter DOUT_DATA_WIDTH INTEGER 0
+set_parameter_property DOUT_DATA_WIDTH DEFAULT_VALUE 64
+set_parameter_property DOUT_DATA_WIDTH DISPLAY_NAME DOUT_DATA_WIDTH
+set_parameter_property DOUT_DATA_WIDTH TYPE INTEGER
+set_parameter_property DOUT_DATA_WIDTH UNITS None
+set_parameter_property DOUT_DATA_WIDTH HDL_PARAMETER true
+
+add_parameter DIN_ADDRESS_WIDTH INTEGER 0
+set_parameter_property DIN_ADDRESS_WIDTH DEFAULT_VALUE 8
+set_parameter_property DIN_ADDRESS_WIDTH DISPLAY_NAME DIN_ADDRESS_WIDTH
+set_parameter_property DIN_ADDRESS_WIDTH TYPE INTEGER
+set_parameter_property DIN_ADDRESS_WIDTH UNITS None
+set_parameter_property DIN_ADDRESS_WIDTH HDL_PARAMETER true
+
+# defaults
+
+ad_alt_intf clock   din_clk         input   1
+ad_alt_intf reset-n din_rstn        input   1 if_din_clk
+
+ad_alt_intf clock   dout_clk        input   1
+ad_alt_intf reset   dout_rst        input   1 if_dout_clk
+
+add_interface din_0 conduit end
+add_interface_port din_0  din_enable_0  enable   Output 1
+add_interface_port din_0  din_valid_0   valid    Output 1
+add_interface_port din_0  din_data_0    data     Input  DIN_DATA_WIDTH
+
+set_interface_property din_0 associatedClock if_din_clk
+set_interface_property din_0 associatedReset if_din_rstn
+
+add_interface dout_0 conduit end
+add_interface_port dout_0 dout_enable_0 enable   Input  1
+add_interface_port dout_0 dout_valid_0  valid    Input  1
+add_interface_port dout_0 dout_data_0   data     Output DOUT_DATA_WIDTH
+
+set_interface_property dout_0 associatedClock if_dout_clk
+set_interface_property dout_0 associatedReset if_dout_rst
+
+proc p_util_rfifo {} {
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 1} {
+
+    add_interface din_1 conduit end
+    add_interface_port din_1  din_enable_1  enable   Output 1
+    add_interface_port din_1  din_valid_1   valid    Output 1
+    add_interface_port din_1  din_data_1    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_1 associatedClock if_din_clk
+    set_interface_property din_1 associatedReset if_din_rstn
+
+    add_interface dout_1 conduit end
+    add_interface_port dout_1 dout_enable_1 enable   Input  1
+    add_interface_port dout_1 dout_valid_1  valid    Input  1
+    add_interface_port dout_1 dout_data_1   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_1 associatedClock if_dout_clk
+    set_interface_property dout_1 associatedReset if_dout_rst
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
+
+    add_interface din_2 conduit end
+    add_interface_port din_2  din_enable_2  enable   Output 1
+    add_interface_port din_2  din_valid_2   valid    Output 1
+    add_interface_port din_2  din_data_2    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_2 associatedClock if_din_clk
+    set_interface_property din_2 associatedReset if_din_rstn
+
+    add_interface dout_2 conduit end
+    add_interface_port dout_2 dout_enable_2 enable   Input  1
+    add_interface_port dout_2 dout_valid_2  valid    Input  1
+    add_interface_port dout_2 dout_data_2   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_2 associatedClock if_dout_clk
+    set_interface_property dout_2 associatedReset if_dout_rst
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
+
+    add_interface din_3 conduit end
+    add_interface_port din_3  din_enable_3  enable   Output 1
+    add_interface_port din_3  din_valid_3   valid    Output 1
+    add_interface_port din_3  din_data_3    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_3 associatedClock if_din_clk
+    set_interface_property din_3 associatedReset if_din_rstn
+
+    add_interface dout_3 conduit end
+    add_interface_port dout_3 dout_enable_3 enable   Input  1
+    add_interface_port dout_3 dout_valid_3  valid    Input  1
+    add_interface_port dout_3 dout_data_3   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_3 associatedClock if_dout_clk
+    set_interface_property dout_3 associatedReset if_dout_rst
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
+
+    add_interface din_4 conduit end
+    add_interface_port din_4  din_enable_4  enable   Output 1
+    add_interface_port din_4  din_valid_4   valid    Output 1
+    add_interface_port din_4  din_data_4    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_4 associatedClock if_din_clk
+    set_interface_property din_4 associatedReset if_din_rstn
+
+    add_interface dout_4 conduit end
+    add_interface_port dout_4 dout_enable_4 enable   Input  1
+    add_interface_port dout_4 dout_valid_4  valid    Input  1
+    add_interface_port dout_4 dout_data_4   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_4 associatedClock if_dout_clk
+    set_interface_property dout_4 associatedReset if_dout_rst
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
+
+    add_interface din_5 conduit end
+    add_interface_port din_5  din_enable_5  enable   Output 1
+    add_interface_port din_5  din_valid_5   valid    Output 1
+    add_interface_port din_5  din_data_5    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_5 associatedClock if_din_clk
+    set_interface_property din_5 associatedReset if_din_rstn
+
+    add_interface dout_5 conduit end
+    add_interface_port dout_5 dout_enable_5 enable   Input  1
+    add_interface_port dout_5 dout_valid_5  valid    Input  1
+    add_interface_port dout_5 dout_data_5   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_5 associatedClock if_dout_clk
+    set_interface_property dout_5 associatedReset if_dout_rst
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
+
+    add_interface din_6 conduit end
+    add_interface_port din_6  din_enable_6  enable   Output 1
+    add_interface_port din_6  din_valid_6   valid    Output 1
+    add_interface_port din_6  din_data_6    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_6 associatedClock if_din_clk
+    set_interface_property din_6 associatedReset if_din_rstn
+
+    add_interface dout_6 conduit end
+    add_interface_port dout_6 dout_enable_6 enable   Input  1
+    add_interface_port dout_6 dout_valid_6  valid    Input  1
+    add_interface_port dout_6 dout_data_6   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_6 associatedClock if_dout_clk
+    set_interface_property dout_6 associatedReset if_dout_rst
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
+
+    add_interface din_7 conduit end
+    add_interface_port din_7  din_enable_7  enable   Output 1
+    add_interface_port din_7  din_valid_7   valid    Output 1
+    add_interface_port din_7  din_data_7    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_7 associatedClock if_din_clk
+    set_interface_property din_7 associatedReset if_din_rstn
+
+    add_interface dout_7 conduit end
+    add_interface_port dout_7 dout_enable_7 enable   Input  1
+    add_interface_port dout_7 dout_valid_7  valid    Input  1
+    add_interface_port dout_7 dout_data_7   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_7 associatedClock if_dout_clk
+    set_interface_property dout_7 associatedReset if_dout_rst
+  }
+
+}
+

From 58a2a3259c26064c41b9e5a405f5c8dcf733ea35 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 10:57:02 -0400
Subject: [PATCH 204/972] util_rfifo: updates

---
 library/util_rfifo/util_rfifo.v      | 398 +++++++++++++++++++++------
 library/util_rfifo/util_rfifo_ip.tcl |  23 ++
 2 files changed, 333 insertions(+), 88 deletions(-)

diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v
index d7c7e9ffb..c724e3638 100644
--- a/library/util_rfifo/util_rfifo.v
+++ b/library/util_rfifo/util_rfifo.v
@@ -34,131 +34,353 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// allows conversions between the dac (or similar) interface to the dma (or similar).
-//    * asymmetric bus widths in the range allowed by the fifo
-//    * frequency -- dma can run slower at reduced channels
-//    * drop or add channels -- pre processing samples
-//    * interface axis -- allows axi-stream interface
-//
-// in all cases bandwidth requirements must be met (read <= write).
-//
-// axis-interface support
-//    * connect dma_rd as axis_ready, make sure data is present (use dma_rd as
-//        enable for the data pipe line). leave axis_valid open!
-//    * make sure read bandwidth <= write bandwidth (or interpolate samples)
-//
-// the fifo is external- connect all the fifo_* signals to a fifo generator IP.
-// configure the IP to match the buswidths & clocks.
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
 module util_rfifo (
 
-  // dac interface
+  // d-in interface
 
-  dac_clk,
-  dac_rd,
-  dac_rdata,
-  dac_runf,
+  din_rstn,
+  din_clk,
+  din_enable_0,
+  din_valid_0,
+  din_data_0,
+  din_enable_1,
+  din_valid_1,
+  din_data_1,
+  din_enable_2,
+  din_valid_2,
+  din_data_2,
+  din_enable_3,
+  din_valid_3,
+  din_data_3,
+  din_enable_4,
+  din_valid_4,
+  din_data_4,
+  din_enable_5,
+  din_valid_5,
+  din_data_5,
+  din_enable_6,
+  din_valid_6,
+  din_data_6,
+  din_enable_7,
+  din_valid_7,
+  din_data_7,
+  din_unf,
 
-  // dma interface
+  // d-out interface
 
-  dma_clk,
-  dma_rd,
-  dma_rdata,
-  dma_runf,
-
-  // fifo interface
-
-  fifo_rst,
-  fifo_rstn,
-  fifo_wr,
-  fifo_wdata,
-  fifo_wfull,
-  fifo_rd,
-  fifo_rdata,
-  fifo_rempty,
-  fifo_runf);
+  dout_rst,
+  dout_clk,
+  dout_enable_0,
+  dout_valid_0,
+  dout_data_0,
+  dout_enable_1,
+  dout_valid_1,
+  dout_data_1,
+  dout_enable_2,
+  dout_valid_2,
+  dout_data_2,
+  dout_enable_3,
+  dout_valid_3,
+  dout_data_3,
+  dout_enable_4,
+  dout_valid_4,
+  dout_data_4,
+  dout_enable_5,
+  dout_valid_5,
+  dout_data_5,
+  dout_enable_6,
+  dout_valid_6,
+  dout_data_6,
+  dout_enable_7,
+  dout_valid_7,
+  dout_data_7,
+  dout_unf);
 
   // parameters
 
-  parameter DAC_DATA_WIDTH = 32;
-  parameter DMA_DATA_WIDTH = 64;
+  parameter   NUM_OF_CHANNELS = 4;
+  parameter   DIN_DATA_WIDTH = 32;
+  parameter   DOUT_DATA_WIDTH = 64;
+  parameter   DIN_ADDRESS_WIDTH = 8;
 
-  // dac interface
+  localparam  M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
+  localparam  ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4;
+  localparam  DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;
+  localparam  T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;
+  localparam  T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;
 
-  input                           dac_clk;
-  input                           dac_rd;
-  output  [DAC_DATA_WIDTH-1:0]    dac_rdata;
-  output                          dac_runf;
+  // d-in interface
 
-  // dma interface
+  input                               din_rstn;
+  input                               din_clk;
+  output                              din_enable_0;
+  output                              din_valid_0;
+  input   [DIN_DATA_WIDTH-1:0]        din_data_0;
+  output                              din_enable_1;
+  output                              din_valid_1;
+  input   [DIN_DATA_WIDTH-1:0]        din_data_1;
+  output                              din_enable_2;
+  output                              din_valid_2;
+  input   [DIN_DATA_WIDTH-1:0]        din_data_2;
+  output                              din_enable_3;
+  output                              din_valid_3;
+  input   [DIN_DATA_WIDTH-1:0]        din_data_3;
+  output                              din_enable_4;
+  output                              din_valid_4;
+  input   [DIN_DATA_WIDTH-1:0]        din_data_4;
+  output                              din_enable_5;
+  output                              din_valid_5;
+  input   [DIN_DATA_WIDTH-1:0]        din_data_5;
+  output                              din_enable_6;
+  output                              din_valid_6;
+  input   [DIN_DATA_WIDTH-1:0]        din_data_6;
+  output                              din_enable_7;
+  output                              din_valid_7;
+  input   [DIN_DATA_WIDTH-1:0]        din_data_7;
+  input                               din_unf;
 
-  input                           dma_clk;
-  output                          dma_rd;
-  input   [DMA_DATA_WIDTH-1:0]    dma_rdata;
-  input                           dma_runf;
+  // dout interface
 
-  // fifo interface
-
-  output                          fifo_rst;
-  output                          fifo_rstn;
-  output                          fifo_wr;
-  output  [DMA_DATA_WIDTH-1:0]    fifo_wdata;
-  input                           fifo_wfull;
-  output                          fifo_rd;
-  input   [DAC_DATA_WIDTH-1:0]    fifo_rdata;
-  input                           fifo_rempty;
-  input                           fifo_runf;
+  input                               dout_rst;
+  input                               dout_clk;
+  input                               dout_enable_0;
+  input                               dout_valid_0;
+  output  [DOUT_DATA_WIDTH-1:0]       dout_data_0;
+  input                               dout_enable_1;
+  input                               dout_valid_1;
+  output  [DOUT_DATA_WIDTH-1:0]       dout_data_1;
+  input                               dout_enable_2;
+  input                               dout_valid_2;
+  output  [DOUT_DATA_WIDTH-1:0]       dout_data_2;
+  input                               dout_enable_3;
+  input                               dout_valid_3;
+  output  [DOUT_DATA_WIDTH-1:0]       dout_data_3;
+  input                               dout_enable_4;
+  input                               dout_valid_4;
+  output  [DOUT_DATA_WIDTH-1:0]       dout_data_4;
+  input                               dout_enable_5;
+  input                               dout_valid_5;
+  output  [DOUT_DATA_WIDTH-1:0]       dout_data_5;
+  input                               dout_enable_6;
+  input                               dout_valid_6;
+  output  [DOUT_DATA_WIDTH-1:0]       dout_data_6;
+  input                               dout_enable_7;
+  input                               dout_valid_7;
+  output  [DOUT_DATA_WIDTH-1:0]       dout_data_7;
+  output                              dout_unf;
 
   // internal registers
 
-  reg     [ 1:0]                  dac_runf_m = 'd0;
-  reg                             dac_runf = 'd0;
-  reg                             dma_rd = 'd0;
+  reg     [(DATA_WIDTH-1):0]          din_wdata = 'd0;
+  reg     [(ADDRESS_WIDTH-1):0]       din_waddr = 'd0;
+  reg                                 din_wr = 'd0;
+  reg     [ 6:0]                      din_req_cnt = 'd0;
+  reg     [ 7:0]                      din_enable_m1 = 'd0;
+  reg     [ 7:0]                      din_enable = 'd0;
+  reg                                 din_req_t_m1 = 'd0;
+  reg                                 din_req_t_m2 = 'd0;
+  reg                                 din_req_t_m3 = 'd0;
+  reg     [(T_DOUT_DATA_WIDTH+1):0]   dout_data = 'd0;
+  reg     [(DATA_WIDTH-1):0]          dout_rdata = 'd0;
+  reg     [ 7:0]                      dout_enable = 'd0;
+  reg                                 dout_req_t = 'd0;
+  reg     [(ADDRESS_WIDTH-1):0]       dout_raddr = 'd0;
+  reg                                 dout_unf_m1 = 'd0;
+  reg                                 dout_unf = 'd0;
 
-  // dac underflow
+  // internal signals
 
-  always @(posedge dac_clk) begin
-    dac_runf_m[0] <= dma_runf | fifo_runf;
-    dac_runf_m[1] <= dac_runf_m[0];
-    dac_runf <= dac_runf_m[1];
-  end
+  wire    [(T_DIN_DATA_WIDTH-1):0]    din_data_s;
+  wire                                din_req_s;
+  wire    [ 7:0]                      dout_enable_s;
+  wire    [ 7:0]                      dout_valid_s;
+  wire    [(T_DOUT_DATA_WIDTH+1):0]   dout_data_s;
+  wire    [(DATA_WIDTH-1):0]          dout_rdata_s;
 
-  // dma read
+  // variables
 
-  always @(posedge dma_clk) begin
-    dma_rd <= ~fifo_wfull;
-  end
+  genvar                              n;
 
-  // write
+  // enables & valids
 
-  assign fifo_wr = dma_rd;
+  assign din_enable_7 = din_enable[7];
+  assign din_enable_6 = din_enable[6];
+  assign din_enable_5 = din_enable[5];
+  assign din_enable_4 = din_enable[4];
+  assign din_enable_3 = din_enable[3];
+  assign din_enable_2 = din_enable[2];
+  assign din_enable_1 = din_enable[1];
+  assign din_enable_0 = din_enable[0];
+
+  assign din_valid_7 = din_req_cnt[6];
+  assign din_valid_6 = din_req_cnt[6];
+  assign din_valid_5 = din_req_cnt[6];
+  assign din_valid_4 = din_req_cnt[6];
+  assign din_valid_3 = din_req_cnt[6];
+  assign din_valid_2 = din_req_cnt[6];
+  assign din_valid_1 = din_req_cnt[6];
+  assign din_valid_0 = din_req_cnt[6];
+
+  assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4,
+                        din_data_3, din_data_2, din_data_1, din_data_0};
+
+  // dout_width >= din_width only
 
-  genvar s;
   generate
-  for (s = 0; s < DMA_DATA_WIDTH; s = s + 1) begin: g_wdata
-  assign fifo_wdata[s] = dma_rdata[(DMA_DATA_WIDTH-1)-s];
+  for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in
+  if (M_MEM_RATIO == 1) begin
+  always @(posedge din_clk) begin
+    if (din_req_cnt[6] == 1'b1) begin
+      din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
+        din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)];
+    end
+  end
+  end else begin
+  always @(posedge din_clk) begin
+    if (din_req_cnt[6] == 1'b1) begin
+      din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
+        {din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)],
+        din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]};
+    end
+  end
+  end
   end
   endgenerate
 
-  // read
+  always @(posedge din_clk or negedge din_rstn) begin
+    if (din_rstn == 1'b0) begin
+      din_waddr <= 'd0;
+      din_wr <= 1'd0;
+    end else begin
+      if (din_wr == 1'b1) begin
+        din_waddr <= din_waddr + 1'b1;
+      end
+      case (M_MEM_RATIO)
+        8: din_wr <= din_req_cnt[6] & din_req_cnt[2] & din_req_cnt[1] & din_req_cnt[0];
+        4: din_wr <= din_req_cnt[6] & din_req_cnt[1] & din_req_cnt[0];
+        2: din_wr <= din_req_cnt[6] & din_req_cnt[0];
+        default: din_wr <= din_req_cnt[6];
+      endcase
+    end
+  end
 
-  assign fifo_rd = ~fifo_rempty & dac_rd;
+  always @(posedge din_clk or negedge din_rstn) begin
+    if (din_rstn == 1'b0) begin
+      din_req_cnt <= 'd0;
+    end else begin
+      if (din_req_s == 1'b1) begin
+        case (M_MEM_RATIO)
+          8: din_req_cnt <= 7'h40;
+          4: din_req_cnt <= 7'h60;
+          2: din_req_cnt <= 7'h70;
+          default: din_req_cnt <= 7'h78;
+        endcase
+      end else if (din_req_cnt[6] == 1'b1) begin
+        din_req_cnt <= din_req_cnt + 1'b1;
+      end
+    end
+  end
+
+  assign din_req_s = din_req_t_m3 ^ din_req_t_m2;
+
+  always @(posedge din_clk or negedge din_rstn) begin
+    if (din_rstn == 1'b0) begin
+      din_enable_m1 <= 'd0;
+      din_enable <= 'd0;
+      din_req_t_m1 <= 'd0;
+      din_req_t_m2 <= 'd0;
+      din_req_t_m3 <= 'd0;
+    end else begin
+      din_enable_m1 <= dout_enable;
+      din_enable <= din_enable_m1;
+      din_req_t_m1 <= dout_req_t;
+      din_req_t_m2 <= din_req_t_m1;
+      din_req_t_m3 <= din_req_t_m2;
+    end
+  end
+
+  // read interface (bus expansion and/or clock conversion)
+
+  assign dout_enable_s =  { dout_enable_7, dout_enable_6, dout_enable_5, dout_enable_4,
+                            dout_enable_3, dout_enable_2, dout_enable_1, dout_enable_0};
+
+  assign dout_valid_s = { dout_valid_7, dout_valid_6, dout_valid_5, dout_valid_4,
+                          dout_valid_3, dout_valid_2, dout_valid_1, dout_valid_0};
 
-  genvar m;
   generate
-  for (m = 0; m < DAC_DATA_WIDTH; m = m + 1) begin: g_rdata
-  assign dac_rdata[m] = fifo_rdata[(DAC_DATA_WIDTH-1)-m];
+  if (NUM_OF_CHANNELS >= 8) begin
+  assign dout_data_s = dout_rdata;
+  end else begin
+  assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0;
+  assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata;
   end
   endgenerate
 
-  // reset & resetn
+  assign dout_data_7 = dout_data[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)];
+  assign dout_data_6 = dout_data[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)];
+  assign dout_data_5 = dout_data[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)];
+  assign dout_data_4 = dout_data[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)];
+  assign dout_data_3 = dout_data[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)];
+  assign dout_data_2 = dout_data[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)];
+  assign dout_data_1 = dout_data[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)];
+  assign dout_data_0 = dout_data[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)];
 
-  assign fifo_rst = 1'b0;
-  assign fifo_rstn = 1'b1;
+  generate
+  for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_out
+  always @(posedge dout_clk) begin
+    if (dout_rst == 1'b1) begin
+      dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= 'd0;
+    end else if (dout_valid_s[n] == 1'b1) begin
+      dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
+        dout_data_s[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)];
+    end
+  end
+  end
+  endgenerate
+
+  always @(posedge dout_clk) begin
+    dout_rdata <= dout_rdata_s;
+  end
+
+  always @(posedge dout_clk) begin
+    if (dout_rst == 1'b1) begin
+      dout_enable <= 'd0;
+      dout_req_t <= 'd0;
+      dout_raddr <= 'd0;
+    end else begin
+      dout_enable <= dout_enable_s;
+      if (dout_valid_s[0] == 1'b1) begin
+        if (dout_raddr[2:0] == 3'd0) begin
+          dout_req_t <= ~dout_req_t;
+        end
+        dout_raddr <= dout_raddr + 1'b1;
+      end
+    end
+  end
+
+  always @(posedge dout_clk) begin
+    if (dout_rst == 1'b1) begin
+      dout_unf_m1 <= 'd0;
+      dout_unf <= 'd0;
+    end else begin
+      dout_unf_m1 <= din_unf;
+      dout_unf <= dout_unf_m1;
+    end
+  end
+
+  // instantiations
+
+  ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem (
+    .clka (din_clk),
+    .wea (din_wr),
+    .addra (din_waddr),
+    .dina (din_wdata),
+    .clkb (dout_clk),
+    .addrb (dout_raddr),
+    .doutb (dout_rdata_s));
 
 endmodule
 
diff --git a/library/util_rfifo/util_rfifo_ip.tcl b/library/util_rfifo/util_rfifo_ip.tcl
index d18ca94d8..d8d2b8d7f 100644
--- a/library/util_rfifo/util_rfifo_ip.tcl
+++ b/library/util_rfifo/util_rfifo_ip.tcl
@@ -5,11 +5,34 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create util_rfifo
 adi_ip_files util_rfifo [list \
+  "$ad_hdl_dir/library/common/ad_mem.v" \
   "util_rfifo.v" ]
 
 adi_ip_properties_lite util_rfifo
 
+adi_ip_constraints util_rfifo [list \
+  "util_rfifo_constr.xdc" ]
+
 ipx::remove_all_bus_interface [ipx::current_core]
+set_property driver_value 0 [ipx::get_ports *dout_enable* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dout_valid* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *din_unf* -of_objects [ipx::current_core]]
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \
+  [ipx::get_ports *_1* -of_objects [ipx::current_core]] 
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \
+  [ipx::get_ports *_2* -of_objects [ipx::current_core]]
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \
+  [ipx::get_ports *_3* -of_objects [ipx::current_core]]
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \
+  [ipx::get_ports *_4* -of_objects [ipx::current_core]]
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \
+  [ipx::get_ports *_5* -of_objects [ipx::current_core]]
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \
+  [ipx::get_ports *_6* -of_objects [ipx::current_core]]
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
+  [ipx::get_ports *_7* -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]
 
 

From f515885fc4229a3ff6683b80c89fa3fed7b19d63 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:07:43 -0400
Subject: [PATCH 205/972] util_wfifo: altera ip

---
 library/util_wfifo/util_wfifo_constr.sdc |   5 +
 library/util_wfifo/util_wfifo_hw.tcl     | 212 +++++++++++++++++++++++
 2 files changed, 217 insertions(+)
 create mode 100644 library/util_wfifo/util_wfifo_constr.sdc
 create mode 100755 library/util_wfifo/util_wfifo_hw.tcl

diff --git a/library/util_wfifo/util_wfifo_constr.sdc b/library/util_wfifo/util_wfifo_constr.sdc
new file mode 100644
index 000000000..3e298bd37
--- /dev/null
+++ b/library/util_wfifo/util_wfifo_constr.sdc
@@ -0,0 +1,5 @@
+
+set_false_path -from [get_registers *din_enable*] -to [get_registers *dout_enable_m1*]
+set_false_path -from [get_registers *din_req_t*]  -to [get_registers *dout_req_t_m1*]
+set_false_path -from [get_registers *dout_ovf*]   -to [get_registers *din_ovf_m1*]
+
diff --git a/library/util_wfifo/util_wfifo_hw.tcl b/library/util_wfifo/util_wfifo_hw.tcl
new file mode 100755
index 000000000..8c7912dc4
--- /dev/null
+++ b/library/util_wfifo/util_wfifo_hw.tcl
@@ -0,0 +1,212 @@
+
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+set_module_property NAME util_wfifo
+set_module_property DESCRIPTION "Utils Write FIFO"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME util_wfifo
+set_module_property ELABORATION_CALLBACK p_util_wfifo
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
+set_fileset_property quartus_synth TOP_LEVEL util_wfifo
+add_fileset_file ad_mem.v               VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
+add_fileset_file util_wfifo.v           VERILOG PATH util_wfifo.v TOP_LEVEL_FILE
+add_fileset_file util_wfifo_constr.sdc  SDC     PATH util_wfifo_constr.xdc
+
+# parameters
+
+add_parameter NUM_OF_CHANNELS INTEGER 0
+set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 4
+set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS
+set_parameter_property NUM_OF_CHANNELS TYPE INTEGER
+set_parameter_property NUM_OF_CHANNELS UNITS None
+set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
+
+add_parameter DIN_DATA_WIDTH INTEGER 0
+set_parameter_property DIN_DATA_WIDTH DEFAULT_VALUE 32
+set_parameter_property DIN_DATA_WIDTH DISPLAY_NAME DIN_DATA_WIDTH
+set_parameter_property DIN_DATA_WIDTH TYPE INTEGER
+set_parameter_property DIN_DATA_WIDTH UNITS None
+set_parameter_property DIN_DATA_WIDTH HDL_PARAMETER true
+
+add_parameter DOUT_DATA_WIDTH INTEGER 0
+set_parameter_property DOUT_DATA_WIDTH DEFAULT_VALUE 64
+set_parameter_property DOUT_DATA_WIDTH DISPLAY_NAME DOUT_DATA_WIDTH
+set_parameter_property DOUT_DATA_WIDTH TYPE INTEGER
+set_parameter_property DOUT_DATA_WIDTH UNITS None
+set_parameter_property DOUT_DATA_WIDTH HDL_PARAMETER true
+
+add_parameter DIN_ADDRESS_WIDTH INTEGER 0
+set_parameter_property DIN_ADDRESS_WIDTH DEFAULT_VALUE 8
+set_parameter_property DIN_ADDRESS_WIDTH DISPLAY_NAME DIN_ADDRESS_WIDTH
+set_parameter_property DIN_ADDRESS_WIDTH TYPE INTEGER
+set_parameter_property DIN_ADDRESS_WIDTH UNITS None
+set_parameter_property DIN_ADDRESS_WIDTH HDL_PARAMETER true
+
+# defaults
+
+ad_alt_intf clock   din_clk         input   1
+ad_alt_intf reset   din_rst         input   1 if_din_clk
+
+ad_alt_intf clock   dout_clk        input   1
+ad_alt_intf reset-n dout_rstn       input   1 if_dout_clk
+
+add_interface din_0 conduit end
+add_interface_port din_0  din_enable_0  enable   Input  1
+add_interface_port din_0  din_valid_0   valid    Input  1
+add_interface_port din_0  din_data_0    data     Input  DIN_DATA_WIDTH
+
+set_interface_property din_0 associatedClock if_din_clk
+set_interface_property din_0 associatedReset if_din_rst
+
+add_interface dout_0 conduit end
+add_interface_port dout_0 dout_enable_0 enable   Output 1
+add_interface_port dout_0 dout_valid_0  valid    Output 1
+add_interface_port dout_0 dout_data_0   data     Output DOUT_DATA_WIDTH
+
+set_interface_property dout_0 associatedClock if_dout_clk
+set_interface_property dout_0 associatedReset if_dout_rstn
+
+proc p_util_wfifo {} {
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 1} {
+
+    add_interface din_1 conduit end
+    add_interface_port din_1  din_enable_1  enable   Input  1
+    add_interface_port din_1  din_valid_1   valid    Input  1
+    add_interface_port din_1  din_data_1    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_1 associatedClock if_din_clk
+    set_interface_property din_1 associatedReset if_din_rst
+
+    add_interface dout_1 conduit end
+    add_interface_port dout_1 dout_enable_1 enable   Output 1
+    add_interface_port dout_1 dout_valid_1  valid    Output 1
+    add_interface_port dout_1 dout_data_1   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_1 associatedClock if_dout_clk
+    set_interface_property dout_1 associatedReset if_dout_rstn
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
+
+    add_interface din_2 conduit end
+    add_interface_port din_2  din_enable_2  enable   Input  1
+    add_interface_port din_2  din_valid_2   valid    Input  1
+    add_interface_port din_2  din_data_2    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_2 associatedClock if_din_clk
+    set_interface_property din_2 associatedReset if_din_rst
+
+    add_interface dout_2 conduit end
+    add_interface_port dout_2 dout_enable_2 enable   Output 1
+    add_interface_port dout_2 dout_valid_2  valid    Output 1
+    add_interface_port dout_2 dout_data_2   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_2 associatedClock if_dout_clk
+    set_interface_property dout_2 associatedReset if_dout_rstn
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
+
+    add_interface din_3 conduit end
+    add_interface_port din_3  din_enable_3  enable   Input  1
+    add_interface_port din_3  din_valid_3   valid    Input  1
+    add_interface_port din_3  din_data_3    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_3 associatedClock if_din_clk
+    set_interface_property din_3 associatedReset if_din_rst
+
+    add_interface dout_3 conduit end
+    add_interface_port dout_3 dout_enable_3 enable   Output 1
+    add_interface_port dout_3 dout_valid_3  valid    Output 1
+    add_interface_port dout_3 dout_data_3   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_3 associatedClock if_dout_clk
+    set_interface_property dout_3 associatedReset if_dout_rstn
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
+
+    add_interface din_4 conduit end
+    add_interface_port din_4  din_enable_4  enable   Input  1
+    add_interface_port din_4  din_valid_4   valid    Input  1
+    add_interface_port din_4  din_data_4    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_4 associatedClock if_din_clk
+    set_interface_property din_4 associatedReset if_din_rst
+
+    add_interface dout_4 conduit end
+    add_interface_port dout_4 dout_enable_4 enable   Output 1
+    add_interface_port dout_4 dout_valid_4  valid    Output 1
+    add_interface_port dout_4 dout_data_4   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_4 associatedClock if_dout_clk
+    set_interface_property dout_4 associatedReset if_dout_rstn
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
+
+    add_interface din_5 conduit end
+    add_interface_port din_5  din_enable_5  enable   Input  1
+    add_interface_port din_5  din_valid_5   valid    Input  1
+    add_interface_port din_5  din_data_5    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_5 associatedClock if_din_clk
+    set_interface_property din_5 associatedReset if_din_rst
+
+    add_interface dout_5 conduit end
+    add_interface_port dout_5 dout_enable_5 enable   Output 1
+    add_interface_port dout_5 dout_valid_5  valid    Output 1
+    add_interface_port dout_5 dout_data_5   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_5 associatedClock if_dout_clk
+    set_interface_property dout_5 associatedReset if_dout_rstn
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
+
+    add_interface din_6 conduit end
+    add_interface_port din_6  din_enable_6  enable   Input  1
+    add_interface_port din_6  din_valid_6   valid    Input  1
+    add_interface_port din_6  din_data_6    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_6 associatedClock if_din_clk
+    set_interface_property din_6 associatedReset if_din_rst
+
+    add_interface dout_6 conduit end
+    add_interface_port dout_6 dout_enable_6 enable   Output 1
+    add_interface_port dout_6 dout_valid_6  valid    Output 1
+    add_interface_port dout_6 dout_data_6   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_6 associatedClock if_dout_clk
+    set_interface_property dout_6 associatedReset if_dout_rstn
+  }
+
+  if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
+
+    add_interface din_7 conduit end
+    add_interface_port din_7  din_enable_7  enable   Input  1
+    add_interface_port din_7  din_valid_7   valid    Input  1
+    add_interface_port din_7  din_data_7    data     Input  DIN_DATA_WIDTH
+
+    set_interface_property din_7 associatedClock if_din_clk
+    set_interface_property din_7 associatedReset if_din_rst
+
+    add_interface dout_7 conduit end
+    add_interface_port dout_7 dout_enable_7 enable   Output 1
+    add_interface_port dout_7 dout_valid_7  valid    Output 1
+    add_interface_port dout_7 dout_data_7   data     Output DOUT_DATA_WIDTH
+
+    set_interface_property dout_7 associatedClock if_dout_clk
+    set_interface_property dout_7 associatedReset if_dout_rstn
+  }
+
+}
+

From 4fbff45e27e685be2f5ff7f9e684aac5fce2bfec Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:12:56 -0400
Subject: [PATCH 206/972] util_wfifo- updates

---
 library/util_wfifo/util_wfifo.v          | 130 ++++++++++++-----------
 library/util_wfifo/util_wfifo_constr.xdc |  18 ++--
 2 files changed, 72 insertions(+), 76 deletions(-)

diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v
index c2a2a7da4..f073b3318 100644
--- a/library/util_wfifo/util_wfifo.v
+++ b/library/util_wfifo/util_wfifo.v
@@ -34,10 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// allows conversions of clock/buswidth for adc/dac channels
-// in all cases bandwidth requirements must be met (read >= write).
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -183,27 +179,26 @@ module util_wfifo (
   reg     [ 2:0]                      din_dcnt = 'd0;
   reg                                 din_wr = 'd0;
   reg     [(ADDRESS_WIDTH-1):0]       din_waddr = 'd0;
-  reg                                 din_waddr_rel_t = 'd0;
-  reg     [(ADDRESS_WIDTH-1):0]       din_waddr_rel = 'd0;
-  reg     [ 2:0]                      din_ovf_m = 'd0;
+  reg                                 din_req_t = 'd0;
+  reg                                 din_ovf_m1 = 'd0;
   reg                                 din_ovf = 'd0;
-  reg     [ 2:0]                      dout_waddr_rel_t_m = 'd0;
-  reg     [(ADDRESS_WIDTH-1):0]       dout_waddr_rel = 'd0;
-  reg                                 dout_ovf_int = 'd0;
-  reg     [ 7:0]                      dout_enable_m = 'd0;
-  reg     [ 7:0]                      dout_enable = 'd0;
-  reg                                 dout_rd = 'd0;
-  reg                                 dout_rd_d = 'd0;
-  reg     [(DATA_WIDTH-1):0]          dout_rdata_d = 'd0;
+  reg                                 dout_req_t_m1 = 'd0;
+  reg                                 dout_req_t_m2 = 'd0;
+  reg                                 dout_req_t_m3 = 'd0;
+  reg     [ 3:0]                      dout_req_cnt = 'd0;
   reg     [(ADDRESS_WIDTH-1):0]       dout_raddr = 'd0;
+  reg                                 dout_rd = 'd0;
+  reg                                 dout_valid = 'd0;
+  reg     [ 7:0]                      dout_enable_m1 = 'd0;
+  reg     [ 7:0]                      dout_enable = 'd0;
+  reg     [(DATA_WIDTH-1):0]          dout_rdata = 'd0;
 
   // internal signals
 
   wire    [ 7:0]                      din_enable_s;
   wire    [ 7:0]                      din_valid_s;
   wire    [(T_DIN_DATA_WIDTH-1):0]    din_data_s;
-  wire                                dout_waddr_rel_t_s;
-  wire                                dout_rd_s;
+  wire                                dout_req_t_s;
   wire    [(DATA_WIDTH-1):0]          dout_rdata_s;
   wire    [(T_DOUT_DATA_WIDTH+1):0]   dout_data_s;
 
@@ -220,6 +215,7 @@ module util_wfifo (
   assign din_data_s   = { din_data_7,   din_data_6,   din_data_5,   din_data_4,
                           din_data_3,   din_data_2,   din_data_1,   din_data_0};
 
+  // simple data transfer-- no ovf/unf handling- read-bw > write-bw
   // dout_width >= din_width only
 
   generate
@@ -248,10 +244,9 @@ module util_wfifo (
       din_enable <= 8'd0;
       din_dcnt <= 3'd0;
       din_wr <= 1'd0;
-      din_waddr <= 5'd0;
-      din_waddr_rel_t <= 1'd0;
-      din_waddr_rel <= 5'd0;
-      din_ovf_m <= 'd0;
+      din_waddr <= 'd0;
+      din_req_t <= 1'd0;
+      din_ovf_m1 <= 'd0;
       din_ovf <= 'd0;
     end else begin
       din_enable <= din_enable_s;
@@ -268,95 +263,102 @@ module util_wfifo (
         din_waddr <= din_waddr + 1'b1;
       end
       if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd0)) begin
-        din_waddr_rel_t <= ~din_waddr_rel_t;
-        din_waddr_rel <= din_waddr;
+        din_req_t <= ~din_req_t;
       end
-      din_ovf_m <= {din_ovf_m[1:0], dout_ovf_int};
-      din_ovf <= din_ovf_m[2];
+      din_ovf_m1 <= dout_ovf;
+      din_ovf <= din_ovf_m1;
     end
   end
 
   // read interface (bus expansion and/or clock conversion)
 
-  assign dout_waddr_rel_t_s = dout_waddr_rel_t_m[2] ^ dout_waddr_rel_t_m[1];
+  assign dout_req_t_s = dout_req_t_m3 ^ dout_req_t_m2;
 
   always @(posedge dout_clk or negedge dout_rstn) begin
     if (dout_rstn == 1'b0) begin
-      dout_waddr_rel_t_m <= 3'd0;
-      dout_waddr_rel <= 'd0;
-      dout_ovf_int <= 1'b1;
+      dout_req_t_m1 <= 'd0;
+      dout_req_t_m2 <= 'd0;
+      dout_req_t_m3 <= 'd0;
     end else begin
-      dout_waddr_rel_t_m <= {dout_waddr_rel_t_m[1:0], din_waddr_rel_t};
-      if (dout_waddr_rel_t_s == 1'b1) begin
-        dout_waddr_rel <= din_waddr_rel;
-        if (dout_raddr == dout_waddr_rel) begin
-          dout_ovf_int <= dout_ovf;
-        end else begin
-          dout_ovf_int <= 1'b1;
-        end
-      end
+      dout_req_t_m1 <= din_req_t;
+      dout_req_t_m2 <= dout_req_t_m1;
+      dout_req_t_m3 <= dout_req_t_m2;
     end
   end
 
-  assign dout_rd_s = (dout_raddr == dout_waddr_rel) ? 1'b0 : 1'b1;
-  assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0;
-  assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata_d;
+  always @(posedge dout_clk or negedge dout_rstn) begin
+    if (dout_rstn == 1'b0) begin
+      dout_req_cnt <= 'd0;
+      dout_raddr <= 'd0;
+      dout_rd <= 'd0;
+      dout_valid <= 'd0;
+    end else begin
+      if (dout_req_t_s == 1'b1) begin
+        dout_req_cnt <= 4'h8;
+      end else if (dout_req_cnt[3] == 1'b1) begin
+        dout_req_cnt <= dout_req_cnt + 1'b1;
+      end
+      if (dout_req_cnt[3] == 1'b1) begin
+        dout_raddr <= dout_raddr + 1'b1;
+      end
+      dout_rd <= dout_req_cnt[3];
+      dout_valid <= dout_rd;
+    end
+  end
 
   always @(posedge dout_clk or negedge dout_rstn) begin
     if (dout_rstn == 1'b0) begin
-      dout_enable_m <= 'd0;
+      dout_enable_m1 <= 'd0;
       dout_enable <= 'd0;
     end else begin
-      dout_enable_m <= din_enable;
-      dout_enable <= dout_enable_m;
+      dout_enable_m1 <= din_enable;
+      dout_enable <= dout_enable_m1;
     end
   end
 
   always @(posedge dout_clk) begin
-    dout_rdata_d <= dout_rdata_s;
-    if (dout_rstn == 1'b0) begin
-      dout_rd <= 'd0;
-      dout_rd_d <= 'd0;
-      dout_raddr <= 'd0;
-    end else begin
-      dout_rd <= dout_rd_s;
-      dout_rd_d <= dout_rd;
-      if (dout_rd_s == 1'b1) begin
-        dout_raddr <= dout_raddr + 1'b1;
-      end
-    end
+    dout_rdata <= dout_rdata_s;
   end
 
+  generate
+  if (NUM_OF_CHANNELS >= 8) begin
+  assign dout_data_s = dout_rdata;
+  end else begin
+  assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0;
+  assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata;
+  end
+  endgenerate
+
   assign dout_enable_7 = dout_enable[7];
-  assign dout_valid_7 = dout_rd_d;
+  assign dout_valid_7 = dout_valid;
   assign dout_data_7 = dout_data_s[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)];
 
   assign dout_enable_6 = dout_enable[6];
-  assign dout_valid_6 = dout_rd_d;
+  assign dout_valid_6 = dout_valid;
   assign dout_data_6 = dout_data_s[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)];
 
   assign dout_enable_5 = dout_enable[5];
-  assign dout_valid_5 = dout_rd_d;
+  assign dout_valid_5 = dout_valid;
   assign dout_data_5 = dout_data_s[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)];
 
   assign dout_enable_4 = dout_enable[4];
-  assign dout_valid_4 = dout_rd_d;
+  assign dout_valid_4 = dout_valid;
   assign dout_data_4 = dout_data_s[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)];
 
   assign dout_enable_3 = dout_enable[3];
-  assign dout_valid_3 = dout_rd_d;
+  assign dout_valid_3 = dout_valid;
   assign dout_data_3 = dout_data_s[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)];
 
   assign dout_enable_2 = dout_enable[2];
-  assign dout_valid_2 = dout_rd_d;
+  assign dout_valid_2 = dout_valid;
   assign dout_data_2 = dout_data_s[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)];
 
   assign dout_enable_1 = dout_enable[1];
-  assign dout_valid_1 = dout_rd_d;
+  assign dout_valid_1 = dout_valid;
   assign dout_data_1 = dout_data_s[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)];
 
   assign dout_enable_0 = dout_enable[0];
-  assign dout_valid_0 = dout_rd_d;
+  assign dout_valid_0 = dout_valid;
   assign dout_data_0 = dout_data_s[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)];
 
   // instantiations
diff --git a/library/util_wfifo/util_wfifo_constr.xdc b/library/util_wfifo/util_wfifo_constr.xdc
index 064dfaf99..e554dcff1 100644
--- a/library/util_wfifo/util_wfifo_constr.xdc
+++ b/library/util_wfifo/util_wfifo_constr.xdc
@@ -1,15 +1,9 @@
 
-set_property SHREG_EXTRACT NO [get_cells -hier *din_ovf_m*]
-set_property SHREG_EXTRACT NO [get_cells -hier *dout_waddr_rel_t_m*]
-set_property SHREG_EXTRACT NO [get_cells -hier *dout_enable_m*]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_enable_m*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_req_t_m*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *din_ovf_m*}]
 
-set_false_path -from [get_cells -hier *dout_ovf_int* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier *din_ovf_m* -filter {primitive_subgroup == flop}]
-set_false_path -from [get_cells -hier *din_waddr_rel_t* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier *dout_waddr_rel_t_m* -filter {primitive_subgroup == flop}]
-set_false_path -from [get_cells -hier *din_enable* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier *dout_enable_m* -filter {primitive_subgroup == flop}]
-
-set_max_delay -datapath_only -from [get_cells -hier *din_waddr_rel* -filter {primitive_subgroup == flop}] \
-	-to [get_cells -hier *dout_waddr_rel* -filter {primitive_subgroup == flop}]  8
+set_false_path -from [get_cells -hier -filter {name =~ *din_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_enable_m1* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *din_req_t*  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_req_t_m1*  && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *dout_ovf*   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_ovf_m1*     && IS_SEQUENTIAL}]
 

From cd7c9c99ed90e1c80e15d99e4cf9f28ad3884673 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:16:41 -0400
Subject: [PATCH 207/972] ad_*_clk: altera-pll not supported by qsys flow

---
 library/common/altera/ad_cmos_clk.v | 24 ++++++++++++++++++++++--
 library/common/altera/ad_lvds_clk.v | 20 ++++++++++++++++++++
 2 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/library/common/altera/ad_cmos_clk.v b/library/common/altera/ad_cmos_clk.v
index fcedeb324..735b8fb01 100644
--- a/library/common/altera/ad_cmos_clk.v
+++ b/library/common/altera/ad_cmos_clk.v
@@ -46,8 +46,6 @@ module ad_cmos_clk (
   clk);
 
   parameter   DEVICE_TYPE   = 0;
-  localparam  SERIES7       = 0;
-  localparam  VIRTEX6       = 1;
 
   input     rst;
   output    locked;
@@ -57,11 +55,33 @@ module ad_cmos_clk (
 
   // instantiations
 
+  generate
+  if (DEVICE_TYPE == 0) begin
   alt_clk i_clk (
     .rst (rst),
     .refclk (clk_in),
     .outclk_0 (clk),
     .locked (locked));
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == 1) begin
+  altera_pll #(
+    .reference_clock_frequency("250.0 MHz"),
+    .operation_mode("source synchronous"),
+    .number_of_clocks(1),
+    .output_clock_frequency0("0 MHz"),
+    .phase_shift0("0"))
+  i_clk (
+    .rst (rst),
+    .refclk (clk_in),
+    .outclk (clk),
+    .fboutclk (),
+    .fbclk (1'b0),
+    .locked (locked));
+  end
+  endgenerate
 
 endmodule
 
diff --git a/library/common/altera/ad_lvds_clk.v b/library/common/altera/ad_lvds_clk.v
index 6b7301ea9..983a94723 100644
--- a/library/common/altera/ad_lvds_clk.v
+++ b/library/common/altera/ad_lvds_clk.v
@@ -57,11 +57,31 @@ module ad_lvds_clk (
   
   // instantiations
 
+  generate
+  if (DEVICE_TYPE == 0) begin
   alt_clk i_clk (
     .rst (rst),
     .refclk (clk_in_p),
     .outclk_0 (clk),
     .locked (locked));
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == 1) begin
+  altera_pll #(
+    .reference_clock_frequency("250.0 MHz"),
+    .operation_mode("lvds"),
+    .number_of_clocks(1),
+    .output_clock_frequency0("250.0 MHz"),
+    .phase_shift0("0"))
+  i_clk (
+    .rst (rst),
+    .refclk (clk_in_p),
+    .outclk (clk),
+    .locked (locked));
+  end
+  endgenerate
 
 endmodule
 

From 6bc05fc844573c90c29cf61cc996544e1343db21 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:17:19 -0400
Subject: [PATCH 208/972] ad_*_in: register post-iob

---
 library/common/altera/ad_cmos_in.v | 21 ++++++++++++++++++---
 library/common/altera/ad_lvds_in.v | 21 ++++++++++++++++++---
 2 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/library/common/altera/ad_cmos_in.v b/library/common/altera/ad_cmos_in.v
index b424cc440..4860361ea 100644
--- a/library/common/altera/ad_cmos_in.v
+++ b/library/common/altera/ad_cmos_in.v
@@ -86,6 +86,16 @@ module ad_cmos_in (
   input               delay_rst;
   output              delay_locked;
 
+  // internal registers
+
+  reg                 rx_data_p = 'd0;
+  reg                 rx_data_n = 'd0;
+
+  // internal signals
+
+  wire                rx_data_p_s;
+  wire                rx_data_n_s;
+
   // defaults
 
   assign up_drdata = 5'd0;
@@ -98,7 +108,7 @@ module ad_cmos_in (
   alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in),
-    .dout ({rx_data_p, rx_data_n}));
+    .dout ({rx_data_p_s, rx_data_n_s}));
   end
   endgenerate
 
@@ -107,8 +117,8 @@ module ad_cmos_in (
   altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
     .inclock (rx_clk),
     .datain (rx_data_in),
-    .dataout_h (rx_data_p),
-    .dataout_l (rx_data_n),
+    .dataout_h (rx_data_p_s),
+    .dataout_l (rx_data_n_s),
     .inclocken (1'b1),
     .aclr (1'b0),
     .aset (1'b0),
@@ -117,6 +127,11 @@ module ad_cmos_in (
   end
   endgenerate
 
+  always @(posedge rx_clk) begin
+    rx_data_p <= rx_data_p_s;
+    rx_data_n <= rx_data_n_s;
+  end
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/common/altera/ad_lvds_in.v b/library/common/altera/ad_lvds_in.v
index 08dd863f1..91774bdf1 100644
--- a/library/common/altera/ad_lvds_in.v
+++ b/library/common/altera/ad_lvds_in.v
@@ -88,6 +88,16 @@ module ad_lvds_in (
   input               delay_rst;
   output              delay_locked;
 
+  // internal registers
+
+  reg                 rx_data_p = 'd0;
+  reg                 rx_data_n = 'd0;
+
+  // internal signals
+
+  wire                rx_data_p_s;
+  wire                rx_data_n_s;
+
   // defaults
 
   assign up_drdata = 5'd0;
@@ -100,7 +110,7 @@ module ad_lvds_in (
   alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in_p),
-    .dout ({rx_data_p, rx_data_n}));
+    .dout ({rx_data_p_s, rx_data_n_s}));
   end
   endgenerate
 
@@ -109,8 +119,8 @@ module ad_lvds_in (
   altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
     .inclock (rx_clk),
     .datain (rx_data_in_p),
-    .dataout_h (rx_data_p),
-    .dataout_l (rx_data_n),
+    .dataout_h (rx_data_p_s),
+    .dataout_l (rx_data_n_s),
     .inclocken (1'b1),
     .aclr (1'b0),
     .aset (1'b0),
@@ -119,6 +129,11 @@ module ad_lvds_in (
   end
   endgenerate
 
+  always @(posedge rx_clk) begin
+    rx_data_p <= rx_data_p_s;
+    rx_data_n <= rx_data_n_s;
+  end
+
 endmodule
 
 // ***************************************************************************

From e05204a86da29c8026ebef0f02bc0a172fe1f53f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:17:45 -0400
Subject: [PATCH 209/972] util_cpack: interface updates

---
 library/util_cpack/util_cpack_hw.tcl | 116 +++++++++++++++++----------
 1 file changed, 73 insertions(+), 43 deletions(-)

diff --git a/library/util_cpack/util_cpack_hw.tcl b/library/util_cpack/util_cpack_hw.tcl
index 889704d3c..5cabc02e8 100755
--- a/library/util_cpack/util_cpack_hw.tcl
+++ b/library/util_cpack/util_cpack_hw.tcl
@@ -39,67 +39,97 @@ set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
 # defaults
 
 ad_alt_intf clock   adc_clk         input   1
-ad_alt_intf reset   adc_rst         input   1                                   if_adc_clk
-ad_alt_intf signal  adc_valid       output  1                                   valid
-ad_alt_intf signal  adc_sync        output  1                                   sync
+ad_alt_intf reset   adc_rst         input   1  if_adc_clk
+
+ad_alt_intf signal  adc_valid       output  1  valid
+ad_alt_intf signal  adc_sync        output  1  sync
 ad_alt_intf signal  adc_data        output  NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH  data
 
-add_interface fifo_ch_0 conduit end
-#set_interface_property fifo_ch_0  associatedClock if_adc_clk
-add_interface_port fifo_ch_0  adc_enable_0  enable   Input  1
-add_interface_port fifo_ch_0  adc_valid_0   valid    Input  1
-add_interface_port fifo_ch_0  adc_data_0    data     Input  CHANNEL_DATA_WIDTH
+add_interface adc_ch_0 conduit end
+add_interface_port adc_ch_0  adc_enable_0  enable   Input  1
+add_interface_port adc_ch_0  adc_valid_0   valid    Input  1
+add_interface_port adc_ch_0  adc_data_0    data     Input  CHANNEL_DATA_WIDTH
+
+set_interface_property adc_ch_0  associatedClock if_adc_clk
+set_interface_property adc_ch_0  associatedReset if_adc_rst
 
 proc p_util_cpack {} {
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 1} {
-    add_interface fifo_ch_1 conduit end
-    #set_interface_property fifo_ch_1  associatedClock if_adc_clk
-    add_interface_port fifo_ch_1  adc_enable_1 enable   Input  1
-    add_interface_port fifo_ch_1  adc_valid_1  valid    Input  1
-    add_interface_port fifo_ch_1  adc_data_1   data     Input  CHANNEL_DATA_WIDTH
+
+    add_interface adc_ch_1 conduit end
+    add_interface_port adc_ch_1  adc_enable_1 enable   Input  1
+    add_interface_port adc_ch_1  adc_valid_1  valid    Input  1
+    add_interface_port adc_ch_1  adc_data_1   data     Input  CHANNEL_DATA_WIDTH
+
+    set_interface_property adc_ch_1  associatedClock if_adc_clk
+    set_interface_property adc_ch_1  associatedReset if_adc_rst
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
-    add_interface fifo_ch_2 conduit end
-    #set_interface_property fifo_ch_2  associatedClock if_adc_clk
-    add_interface_port fifo_ch_2  adc_enable_2 enable   Input  1
-    add_interface_port fifo_ch_2  adc_valid_2  valid    Input  1
-    add_interface_port fifo_ch_2  adc_data_2   data     Input  CHANNEL_DATA_WIDTH
+
+    add_interface adc_ch_2 conduit end
+    add_interface_port adc_ch_2  adc_enable_2 enable   Input  1
+    add_interface_port adc_ch_2  adc_valid_2  valid    Input  1
+    add_interface_port adc_ch_2  adc_data_2   data     Input  CHANNEL_DATA_WIDTH
+
+    set_interface_property adc_ch_2  associatedClock if_adc_clk
+    set_interface_property adc_ch_2  associatedReset if_adc_rst
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
-    add_interface fifo_ch_3 conduit end
-    #set_interface_property fifo_ch_3  associatedClock if_adc_clk
-    add_interface_port fifo_ch_3  adc_enable_3 enable   Input  1
-    add_interface_port fifo_ch_3  adc_valid_3  valid    Input  1
-    add_interface_port fifo_ch_3  adc_data_3   data     Input  CHANNEL_DATA_WIDTH
+
+    add_interface adc_ch_3 conduit end
+    add_interface_port adc_ch_3  adc_enable_3 enable   Input  1
+    add_interface_port adc_ch_3  adc_valid_3  valid    Input  1
+    add_interface_port adc_ch_3  adc_data_3   data     Input  CHANNEL_DATA_WIDTH
+
+    set_interface_property adc_ch_3  associatedClock if_adc_clk
+    set_interface_property adc_ch_3  associatedReset if_adc_rst
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
-    add_interface fifo_ch_4 conduit end
-    #set_interface_property fifo_ch_4  associatedClock if_adc_clk
-    add_interface_port fifo_ch_4  adc_enable_4 enable   Input  1
-    add_interface_port fifo_ch_4  adc_valid_4  valid    Input  1
-    add_interface_port fifo_ch_4  adc_data_4   data     Input  CHANNEL_DATA_WIDTH
+
+    add_interface adc_ch_4 conduit end
+    add_interface_port adc_ch_4  adc_enable_4 enable   Input  1
+    add_interface_port adc_ch_4  adc_valid_4  valid    Input  1
+    add_interface_port adc_ch_4  adc_data_4   data     Input  CHANNEL_DATA_WIDTH
+
+    set_interface_property adc_ch_4  associatedClock if_adc_clk
+    set_interface_property adc_ch_4  associatedReset if_adc_rst
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
-    add_interface fifo_ch_5 conduit end
-    #set_interface_property fifo_ch_5  associatedClock if_adc_clk
-    add_interface_port fifo_ch_5  adc_enable_5 enable   Input  1
-    add_interface_port fifo_ch_5  adc_valid_5  valid    Input  1
-    add_interface_port fifo_ch_5  adc_data_5   data     Input  CHANNEL_DATA_WIDTH
+
+    add_interface adc_ch_5 conduit end
+    add_interface_port adc_ch_5  adc_enable_5 enable   Input  1
+    add_interface_port adc_ch_5  adc_valid_5  valid    Input  1
+    add_interface_port adc_ch_5  adc_data_5   data     Input  CHANNEL_DATA_WIDTH
+
+    set_interface_property adc_ch_5  associatedClock if_adc_clk
+    set_interface_property adc_ch_5  associatedReset if_adc_rst
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
-    add_interface fifo_ch_6 conduit end
-    #set_interface_property fifo_ch_6  associatedClock if_adc_clk
-    add_interface_port fifo_ch_6  adc_enable_6 enable   Input  1
-    add_interface_port fifo_ch_6  adc_valid_6  valid    Input  1
-    add_interface_port fifo_ch_6  adc_data_6   data     Input  CHANNEL_DATA_WIDTH
+
+    add_interface adc_ch_6 conduit end
+    add_interface_port adc_ch_6  adc_enable_6 enable   Input  1
+    add_interface_port adc_ch_6  adc_valid_6  valid    Input  1
+    add_interface_port adc_ch_6  adc_data_6   data     Input  CHANNEL_DATA_WIDTH
+
+    set_interface_property adc_ch_6  associatedClock if_adc_clk
+    set_interface_property adc_ch_6  associatedReset if_adc_rst
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
-    add_interface fifo_ch_7 conduit end
-    #set_interface_property fifo_ch_7  associatedClock if_adc_clk
-    add_interface_port fifo_ch_7  adc_enable_7 enable   Input  1
-    add_interface_port fifo_ch_7  adc_valid_7  valid    Input  1
-    add_interface_port fifo_ch_7  adc_data_7   data     Input  CHANNEL_DATA_WIDTH
+
+    add_interface adc_ch_7 conduit end
+    add_interface_port adc_ch_7  adc_enable_7 enable   Input  1
+    add_interface_port adc_ch_7  adc_valid_7  valid    Input  1
+    add_interface_port adc_ch_7  adc_data_7   data     Input  CHANNEL_DATA_WIDTH
+
+    set_interface_property adc_ch_7  associatedClock if_adc_clk
+    set_interface_property adc_ch_7  associatedReset if_adc_rst
   }
 }
 

From 421c0519f476b80547df92008def29a5bf38cf56 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:18:15 -0400
Subject: [PATCH 210/972] util_rfifo- updates

---
 library/util_rfifo/util_rfifo.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v
index c724e3638..8cf395c9d 100644
--- a/library/util_rfifo/util_rfifo.v
+++ b/library/util_rfifo/util_rfifo.v
@@ -227,6 +227,7 @@ module util_rfifo (
   assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4,
                         din_data_3, din_data_2, din_data_1, din_data_0};
 
+  // simple data transfer-- no ovf/unf handling- read-bw > write-bw
   // dout_width >= din_width only
 
   generate

From 68329de73822f84019b686c7ff27111d2e281217 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:18:31 -0400
Subject: [PATCH 211/972] ad9361- interface updates

---
 library/axi_ad9361/axi_ad9361_hw.tcl | 100 +++++++++++++++------------
 1 file changed, 56 insertions(+), 44 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index fe5b66393..07a3ede20 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -146,49 +146,73 @@ ad_alt_intf clock clk input 1
 ad_alt_intf reset rst output 1 if_clk
 set_interface_property if_rst associatedResetSinks none
 
-add_interface fifo_ch_0_in conduit end
-add_interface_port fifo_ch_0_in adc_enable_i0 enable Output 1
-add_interface_port fifo_ch_0_in adc_valid_i0 valid Output 1
-add_interface_port fifo_ch_0_in adc_data_i0 data Output 16
+add_interface adc_ch_0 conduit end
+add_interface_port adc_ch_0 adc_enable_i0 enable Output 1
+add_interface_port adc_ch_0 adc_valid_i0 valid Output 1
+add_interface_port adc_ch_0 adc_data_i0 data Output 16
 
-add_interface fifo_ch_1_in conduit end
-add_interface_port fifo_ch_1_in adc_enable_q0 enable Output 1
-add_interface_port fifo_ch_1_in adc_valid_q0 valid Output 1
-add_interface_port fifo_ch_1_in adc_data_q0 data Output 16
+set_interface_property adc_ch_0 associatedClock if_clk
+set_interface_property adc_ch_0 associatedReset if_rst
 
-add_interface fifo_ch_2_in conduit end
-add_interface_port fifo_ch_2_in adc_enable_i1 enable Output 1
-add_interface_port fifo_ch_2_in adc_valid_i1 valid Output 1
-add_interface_port fifo_ch_2_in adc_data_i1 data Output 16
+add_interface adc_ch_1 conduit end
+add_interface_port adc_ch_1 adc_enable_q0 enable Output 1
+add_interface_port adc_ch_1 adc_valid_q0 valid Output 1
+add_interface_port adc_ch_1 adc_data_q0 data Output 16
 
-add_interface fifo_ch_3_in conduit end
-add_interface_port fifo_ch_3_in adc_enable_q1 enable Output 1
-add_interface_port fifo_ch_3_in adc_valid_q1 valid Output 1
-add_interface_port fifo_ch_3_in adc_data_q1 data Output 16
+set_interface_property adc_ch_1 associatedClock if_clk
+set_interface_property adc_ch_1 associatedReset if_rst
+
+add_interface adc_ch_2 conduit end
+add_interface_port adc_ch_2 adc_enable_i1 enable Output 1
+add_interface_port adc_ch_2 adc_valid_i1 valid Output 1
+add_interface_port adc_ch_2 adc_data_i1 data Output 16
+
+set_interface_property adc_ch_2 associatedClock if_clk
+set_interface_property adc_ch_2 associatedReset if_rst
+
+add_interface adc_ch_3 conduit end
+add_interface_port adc_ch_3 adc_enable_q1 enable Output 1
+add_interface_port adc_ch_3 adc_valid_q1 valid Output 1
+add_interface_port adc_ch_3 adc_data_q1 data Output 16
+
+set_interface_property adc_ch_3 associatedClock if_clk
+set_interface_property adc_ch_3 associatedReset if_rst
 
 ad_alt_intf signal adc_dovf input 1 ovf
 ad_alt_intf signal adc_dunf input 1 unf
 ad_alt_intf signal adc_r1_mode output 1 r1_mode
 
-add_interface fifo_ch_0_out conduit end
-add_interface_port fifo_ch_0_out dac_enable_i0 enable Output 1
-add_interface_port fifo_ch_0_out dac_valid_i0 valid Output 1
-add_interface_port fifo_ch_0_out dac_data_i0 data Input 16
+add_interface dac_ch_0 conduit end
+add_interface_port dac_ch_0 dac_enable_i0 enable Output 1
+add_interface_port dac_ch_0 dac_valid_i0 valid Output 1
+add_interface_port dac_ch_0 dac_data_i0 data Input 16
 
-add_interface fifo_ch_1_out conduit end
-add_interface_port fifo_ch_1_out dac_enable_q0 enable Output 1
-add_interface_port fifo_ch_1_out dac_valid_q0 valid Output 1
-add_interface_port fifo_ch_1_out dac_data_q0 data Input 16
+set_interface_property dac_ch_0 associatedClock if_clk
+set_interface_property dac_ch_0 associatedReset if_rst
 
-add_interface fifo_ch_2_out conduit end
-add_interface_port fifo_ch_2_out dac_enable_i1 enable Output 1
-add_interface_port fifo_ch_2_out dac_valid_i1 valid Output 1
-add_interface_port fifo_ch_2_out dac_data_i1 data Input 16
+add_interface dac_ch_1 conduit end
+add_interface_port dac_ch_1 dac_enable_q0 enable Output 1
+add_interface_port dac_ch_1 dac_valid_q0 valid Output 1
+add_interface_port dac_ch_1 dac_data_q0 data Input 16
 
-add_interface fifo_ch_3_out conduit end
-add_interface_port fifo_ch_3_out dac_enable_q1 enable Output 1
-add_interface_port fifo_ch_3_out dac_valid_q1 valid Output 1
-add_interface_port fifo_ch_3_out dac_data_q1 data Input 16
+set_interface_property dac_ch_1 associatedClock if_clk
+set_interface_property dac_ch_1 associatedReset if_rst
+
+add_interface dac_ch_2 conduit end
+add_interface_port dac_ch_2 dac_enable_i1 enable Output 1
+add_interface_port dac_ch_2 dac_valid_i1 valid Output 1
+add_interface_port dac_ch_2 dac_data_i1 data Input 16
+
+set_interface_property dac_ch_2 associatedClock if_clk
+set_interface_property dac_ch_2 associatedReset if_rst
+
+add_interface dac_ch_3 conduit end
+add_interface_port dac_ch_3 dac_enable_q1 enable Output 1
+add_interface_port dac_ch_3 dac_valid_q1 valid Output 1
+add_interface_port dac_ch_3 dac_data_q1 data Input 16
+
+set_interface_property dac_ch_3 associatedClock if_clk
+set_interface_property dac_ch_3 associatedReset if_rst
 
 ad_alt_intf signal dac_dovf input 1 ovf
 ad_alt_intf signal dac_dunf input 1 unf
@@ -242,18 +266,6 @@ proc p_axi_ad9361 {} {
   add_interface_port device_if enable enable Output 1
   add_interface_port device_if txnrx txnrx Output 1
 
-  if {$m_device_type == 1} {
-
-    add_hdl_instance alt_clk altera_pll
-    set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
-    set_instance_parameter_value alt_clk {gui_use_locked} {1}
-    set_instance_parameter_value alt_clk {gui_operation_mode} {source synchronous}
-    set_instance_parameter_value alt_clk {gui_number_of_clocks} {1}
-    set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
-    set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
-    set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
-  }
-
   if {$m_device_type == 0} {
 
     add_hdl_instance alt_ddio_in altera_gpio

From e345953bdd05b1ce7bb2c653054831d0c4df38df Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:19:30 -0400
Subject: [PATCH 212/972] arradio- updates

---
 projects/arradio/common/arradio_bd.qsys | 179 ++++++++++++++----------
 1 file changed, 104 insertions(+), 75 deletions(-)

diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys
index 5d27c3c9e..14f13bf65 100755
--- a/projects/arradio/common/arradio_bd.qsys
+++ b/projects/arradio/common/arradio_bd.qsys
@@ -9,17 +9,20 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element adc_pack
+   element arradio_bd
    {
-      datum _sortIndex
+      datum _originalDeviceFamily
       {
-         value = "5";
-         type = "int";
+         value = "Cyclone V";
+         type = "String";
       }
-      datum sopceditor_expanded
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
       {
-         value = "1";
-         type = "boolean";
+         value = "Cyclone V";
+         type = "String";
       }
    }
    element arradio_bd
@@ -99,11 +102,11 @@
          type = "String";
       }
    }
-   element axi_dmac_adc
+   element axi_adc_dma
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "7";
          type = "int";
       }
       datum sopceditor_expanded
@@ -112,7 +115,7 @@
          type = "boolean";
       }
    }
-   element axi_dmac_adc.s_axi
+   element axi_adc_dma.s_axi
    {
       datum baseAddress
       {
@@ -124,7 +127,7 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "9";
          type = "int";
       }
       datum sopceditor_expanded
@@ -145,7 +148,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "8";
          type = "int";
       }
       datum sopceditor_expanded
@@ -158,7 +161,7 @@
    {
       datum _sortIndex
       {
-         value = "10";
+         value = "11";
          type = "int";
       }
    }
@@ -182,7 +185,7 @@
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "10";
          type = "int";
       }
       datum sopceditor_expanded
@@ -215,6 +218,27 @@
          type = "int";
       }
    }
+   element util_adc_pack
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element util_adc_wfifo
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
@@ -264,21 +288,21 @@
    dir="end" />
  <interface
    name="axi_dmac_adc_fifo_wr_clock"
-   internal="axi_dmac_adc.fifo_wr_clock" />
- <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
+   internal="axi_adc_dma.fifo_wr_clock" />
+ <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_adc_dma.fifo_wr_if" />
  <interface
    name="axi_dmac_adc_intr"
-   internal="axi_dmac_adc.interrupt_sender"
+   internal="axi_adc_dma.interrupt_sender"
    type="interrupt"
    dir="end" />
  <interface
    name="axi_dmac_adc_m_dest_axi"
-   internal="axi_dmac_adc.m_dest_axi"
+   internal="axi_adc_dma.m_dest_axi"
    type="axi4"
    dir="start" />
  <interface
    name="axi_dmac_adc_s_axi"
-   internal="axi_dmac_adc.s_axi"
+   internal="axi_adc_dma.s_axi"
    type="axi4lite"
    dir="end" />
  <interface
@@ -325,10 +349,6 @@
    dir="end" />
  <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
  <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
  <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
   <parameter name="ADC_DATAPATH_DISABLE" value="0" />
   <parameter name="CMOS_OR_LVDS_N" value="0" />
@@ -337,7 +357,7 @@
   <parameter name="DEVICE_TYPE" value="1" />
   <parameter name="ID" value="0" />
  </module>
- <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
+ <module name="axi_adc_dma" kind="axi_dmac" version="1.0" enabled="1">
   <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
   <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
   <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
@@ -429,11 +449,16 @@
   <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="adc_pack.if_adc_clk" />
+ <module name="util_adc_pack" kind="util_cpack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <module name="util_adc_wfifo" kind="util_wfifo" version="1.0" enabled="1">
+  <parameter name="DIN_ADDRESS_WIDTH" value="8" />
+  <parameter name="DIN_DATA_WIDTH" value="16" />
+  <parameter name="DOUT_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
  <connection
    kind="clock"
    version="15.1"
@@ -448,12 +473,12 @@
    kind="clock"
    version="15.1"
    start="axi_ad9361.if_l_clk"
-   end="axi_dmac_dac.if_fifo_rd_clk" />
+   end="util_adc_wfifo.if_din_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="axi_ad9361.if_l_clk"
-   end="axi_dmac_adc.if_fifo_wr_clk" />
+   end="axi_dmac_dac.if_fifo_rd_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -464,7 +489,22 @@
    kind="clock"
    version="15.1"
    start="mem_clk.out_clk"
-   end="axi_dmac_adc.m_dest_axi_clock" />
+   end="util_adc_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="mem_clk.out_clk"
+   end="util_adc_wfifo.if_dout_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="mem_clk.out_clk"
+   end="axi_adc_dma.if_fifo_wr_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="mem_clk.out_clk"
+   end="axi_adc_dma.m_dest_axi_clock" />
  <connection
    kind="clock"
    version="15.1"
@@ -479,7 +519,7 @@
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="axi_dmac_adc.s_axi_clock" />
+   end="axi_adc_dma.s_axi_clock" />
  <connection
    kind="clock"
    version="15.1"
@@ -488,8 +528,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="dac_upack.fifo_ch_0"
-   end="axi_ad9361.fifo_ch_0_out">
+   start="axi_ad9361.adc_ch_0"
+   end="util_adc_wfifo.din_0">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -499,8 +539,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_ad9361.fifo_ch_0_in"
-   end="adc_pack.fifo_ch_0">
+   start="axi_ad9361.adc_ch_1"
+   end="util_adc_wfifo.din_1">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -510,8 +550,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_ad9361.fifo_ch_1_in"
-   end="adc_pack.fifo_ch_1">
+   start="util_adc_pack.adc_ch_1"
+   end="util_adc_wfifo.dout_1">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -521,8 +561,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_ad9361.fifo_ch_1_out"
-   end="dac_upack.fifo_ch_1">
+   start="axi_ad9361.adc_ch_2"
+   end="util_adc_wfifo.din_2">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -532,8 +572,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_ad9361.fifo_ch_2_in"
-   end="adc_pack.fifo_ch_2">
+   start="util_adc_pack.adc_ch_2"
+   end="util_adc_wfifo.dout_2">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -543,8 +583,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_ad9361.fifo_ch_2_out"
-   end="dac_upack.fifo_ch_2">
+   start="axi_ad9361.adc_ch_3"
+   end="util_adc_wfifo.din_3">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -554,8 +594,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_ad9361.fifo_ch_3_in"
-   end="adc_pack.fifo_ch_3">
+   start="util_adc_wfifo.dout_0"
+   end="util_adc_pack.adc_ch_0">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -565,8 +605,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_ad9361.fifo_ch_3_out"
-   end="dac_upack.fifo_ch_3">
+   start="util_adc_wfifo.dout_3"
+   end="util_adc_pack.adc_ch_3">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -576,8 +616,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="adc_pack.if_adc_data"
-   end="axi_dmac_adc.if_fifo_wr_din">
+   start="util_adc_pack.if_adc_data"
+   end="axi_adc_dma.if_fifo_wr_din">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -587,8 +627,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="adc_pack.if_adc_sync"
-   end="axi_dmac_adc.if_fifo_wr_sync">
+   start="util_adc_pack.if_adc_sync"
+   end="axi_adc_dma.if_fifo_wr_sync">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -598,8 +638,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="adc_pack.if_adc_valid"
-   end="axi_dmac_adc.if_fifo_wr_en">
+   start="util_adc_pack.if_adc_valid"
+   end="axi_adc_dma.if_fifo_wr_en">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -650,37 +690,26 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_adc.if_fifo_wr_overflow"
-   end="axi_ad9361.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
  <connection
    kind="reset"
    version="15.1"
    start="axi_ad9361.if_rst"
-   end="adc_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="adc_pack.if_adc_rst" />
+   end="util_adc_wfifo.if_din_rst" />
  <connection
    kind="reset"
    version="15.1"
    start="mem_rst.out_reset"
-   end="adc_pack.if_adc_rst" />
+   end="util_adc_pack.if_adc_rst" />
  <connection
    kind="reset"
    version="15.1"
    start="mem_rst.out_reset"
-   end="axi_dmac_adc.m_dest_axi_reset" />
+   end="util_adc_wfifo.if_dout_rstn" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="mem_rst.out_reset"
+   end="axi_adc_dma.m_dest_axi_reset" />
  <connection
    kind="reset"
    version="15.1"
@@ -705,7 +734,7 @@
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="axi_dmac_adc.s_axi_reset" />
+   end="axi_adc_dma.s_axi_reset" />
  <connection
    kind="reset"
    version="15.1"

From 42b0fabd4081b4323741d4d4d460f10d72ae04ba Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Tue, 17 May 2016 14:41:18 +0300
Subject: [PATCH 213/972] axi_hdmi_tx_core: Fixed data path

---
 library/axi_hdmi_tx/axi_hdmi_tx_core.v | 92 ++++++++++++--------------
 1 file changed, 44 insertions(+), 48 deletions(-)

diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
index cc251c993..ea7442861 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
@@ -225,21 +225,22 @@ module axi_hdmi_tx_core (
   reg             hdmi_24_vsync_data_e = 'd0;
   reg             hdmi_24_data_e = 'd0;
   reg     [23:0]  hdmi_24_data = 'd0;
-  reg             hdmi_24_hsync_ss = 'd0;
-  reg             hdmi_24_vsync_ss = 'd0;
-  reg             hdmi_24_hsync_data_e_ss = 'd0;
-  reg             hdmi_24_vsync_data_e_ss = 'd0;
-  reg             hdmi_24_data_e_ss = 'd0;
-  reg     [23:0]  hdmi_24_data_ss = 'd0;
   reg             hdmi_16_hsync = 'd0;
   reg             hdmi_16_vsync = 'd0;
   reg             hdmi_16_hsync_data_e = 'd0;
   reg             hdmi_16_vsync_data_e = 'd0;
+  reg             hdmi_16_hsync_d = 'd0;
+  reg             hdmi_16_vsync_d = 'd0;
+  reg             hdmi_16_hsync_data_e_d = 'd0;
+  reg             hdmi_16_vsync_data_e_d = 'd0;
+  reg             hdmi_16_data_e_d = 'd0;
+  reg     [15:0]  hdmi_16_data_d = 'd0;
   reg             hdmi_16_data_e = 'd0;
   reg     [15:0]  hdmi_16_data = 'd0;
   reg             hdmi_es_hs_de = 'd0;
   reg             hdmi_es_vs_de = 'd0;
   reg     [15:0]  hdmi_es_data = 'd0;
+  reg     [15:0]  hdmi_16_es_data = 'd0;
   reg     [23:0]  hdmi_clip_data = 'd0;
   reg             hdmi_clip_hs_de_d = 'd0;
   reg             hdmi_clip_vs_de_d = 'd0;
@@ -271,15 +272,9 @@ module axi_hdmi_tx_core (
   wire            hdmi_ss_vsync_data_e_s;
   wire            hdmi_ss_data_e_s;
   wire    [15:0]  hdmi_ss_data_s;
-  wire            hdmi_clip_hs_de_s;
-  wire            hdmi_clip_vs_de_s;
-  wire            hdmi_clip_de_s;
-  wire    [23:0]  hdmi_clip_data_s;
-  wire            hdmi_es_hs_de_s;
-  wire            hdmi_es_vs_de_s;
-  wire            hdmi_es_de_s;
   wire    [15:0]  hdmi_es_data_s;
 
+
   // binary to grey conversion
 
   function [8:0] b2g;
@@ -505,8 +500,6 @@ module axi_hdmi_tx_core (
 
   // hdmi clipping
 
-  assign hdmi_clip_data_s = hdmi_24_csc_data;
-
   always @(posedge hdmi_clk) begin
     hdmi_clip_hs_d <= hdmi_24_csc_hsync;
     hdmi_clip_vs_d <= hdmi_24_csc_vsync;
@@ -516,32 +509,32 @@ module axi_hdmi_tx_core (
 
     // Cr (red-diff) / red
 
-    if (hdmi_clip_data_s[23:16] > hdmi_clip_max[23:16]) begin
+    if (hdmi_24_csc_data[23:16] > hdmi_clip_max[23:16]) begin
       hdmi_clip_data[23:16] <= hdmi_clip_max[23:16];
-    end else if (hdmi_clip_data_s[23:16] < hdmi_clip_min[23:16]) begin
+    end else if (hdmi_24_csc_data[23:16] < hdmi_clip_min[23:16]) begin
       hdmi_clip_data[23:16] <= hdmi_clip_min[23:16];
     end else begin
-      hdmi_clip_data[23:16] <= hdmi_clip_data_s[23:16];
+      hdmi_clip_data[23:16] <= hdmi_24_csc_data[23:16];
     end
 
     // Y (luma) / green
 
-    if (hdmi_clip_data_s[15:8] > hdmi_clip_max[15:8]) begin
+    if (hdmi_24_csc_data[15:8] > hdmi_clip_max[15:8]) begin
       hdmi_clip_data[15:8] <= hdmi_clip_max[15:8];
-    end else if (hdmi_clip_data_s[15:8] < hdmi_clip_min[15:8]) begin
+    end else if (hdmi_24_csc_data[15:8] < hdmi_clip_min[15:8]) begin
       hdmi_clip_data[15:8] <= hdmi_clip_min[15:8];
     end else begin
-      hdmi_clip_data[15:8] <= hdmi_clip_data_s[15:8];
+      hdmi_clip_data[15:8] <= hdmi_24_csc_data[15:8];
     end
 
     // Cb (blue-diff) / blue
 
-    if (hdmi_clip_data_s[7:0] > hdmi_clip_max[7:0]) begin
+    if (hdmi_24_csc_data[7:0] > hdmi_clip_max[7:0]) begin
       hdmi_clip_data[7:0] <= hdmi_clip_max[7:0];
-    end else if (hdmi_clip_data_s[7:0] < hdmi_clip_min[7:0]) begin
+    end else if (hdmi_24_csc_data[7:0] < hdmi_clip_min[7:0]) begin
       hdmi_clip_data[7:0] <= hdmi_clip_min[7:0];
     end else begin
-      hdmi_clip_data[7:0] <= hdmi_clip_data_s[7:0];
+      hdmi_clip_data[7:0] <= hdmi_24_csc_data[7:0];
     end
   end
 
@@ -563,42 +556,45 @@ module axi_hdmi_tx_core (
     hdmi_24_data_e <= hdmi_clip_de_d;
     hdmi_24_data <= hdmi_clip_data;
 
+    hdmi_16_hsync <= hdmi_16_hsync_d;
+    hdmi_16_vsync <= hdmi_16_vsync_d;
+    hdmi_16_hsync_data_e <= hdmi_16_hsync_data_e_d;
+    hdmi_16_vsync_data_e <= hdmi_16_vsync_data_e_d;
+    hdmi_16_data_e <= hdmi_16_data_e_d;
+    hdmi_16_data <= hdmi_16_data_d;
+    hdmi_16_es_data <= hdmi_es_data_s;
+
     if (hdmi_ss_bypass == 1'b1) begin
-      hdmi_16_hsync <= hdmi_24_hsync;
-      hdmi_16_vsync <= hdmi_24_vsync;
-      hdmi_16_hsync_data_e <= hdmi_24_hsync_data_e;
-      hdmi_16_vsync_data_e <= hdmi_24_vsync_data_e;
-      hdmi_16_data_e <= hdmi_24_data_e;
-      hdmi_16_data <= hdmi_24_data[15:0]; // Ignore the upper 8 bit
+      hdmi_16_hsync_d <= hdmi_clip_hs_d;
+      hdmi_16_vsync_d <= hdmi_clip_vs_d;
+      hdmi_16_hsync_data_e_d <= hdmi_clip_hs_de_d;
+      hdmi_16_vsync_data_e_d <= hdmi_clip_vs_de_d;
+      hdmi_16_data_e_d <= hdmi_clip_de_d;
+      hdmi_16_data_d <= hdmi_clip_data[15:0]; // Ignore the upper 8 bit
     end else begin
-      hdmi_16_hsync <= hdmi_ss_hsync_s;
-      hdmi_16_vsync <= hdmi_ss_vsync_s;
-      hdmi_16_hsync_data_e <= hdmi_ss_hsync_data_e_s;
-      hdmi_16_vsync_data_e <= hdmi_ss_vsync_data_e_s;
-      hdmi_16_data_e <= hdmi_ss_data_e_s;
-      hdmi_16_data <= hdmi_ss_data_s;
+      hdmi_16_hsync_d <= hdmi_ss_hsync_s;
+      hdmi_16_vsync_d <= hdmi_ss_vsync_s;
+      hdmi_16_hsync_data_e_d <= hdmi_ss_hsync_data_e_s;
+      hdmi_16_vsync_data_e_d <= hdmi_ss_vsync_data_e_s;
+      hdmi_16_data_e_d <= hdmi_ss_data_e_s;
+      hdmi_16_data_d <= hdmi_ss_data_s;
     end
   end
 
   // hdmi embedded sync
 
-  assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e;
-  assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e;
-  assign hdmi_es_de_s = hdmi_16_data_e;
-  assign hdmi_es_data_s = hdmi_16_data;
-
   always @(posedge hdmi_clk) begin
-    hdmi_es_hs_de <= hdmi_es_hs_de_s;
-    hdmi_es_vs_de <= hdmi_es_vs_de_s;
-    if (hdmi_es_de_s == 1'b0) begin
+    hdmi_es_hs_de <= hdmi_16_hsync_d;
+    hdmi_es_vs_de <= hdmi_16_vsync_d;
+    if (hdmi_16_data_e_d == 1'b0) begin
       hdmi_es_data[15:8] <= 8'h80;
     end else begin
-      hdmi_es_data[15:8] <= hdmi_es_data_s[15:8];
+      hdmi_es_data[15:8] <= hdmi_16_data_d[15:8];
     end
-    if (hdmi_es_de_s == 1'b0) begin
+    if (hdmi_16_data_e_d == 1'b0) begin
       hdmi_es_data[7:0] <= 8'h80;
     end else begin
-      hdmi_es_data[7:0] <= hdmi_es_data_s[7:0];
+      hdmi_es_data[7:0] <= hdmi_16_data_d[7:0];
     end
   end
 
@@ -655,7 +651,7 @@ module axi_hdmi_tx_core (
     .hdmi_hs_de (hdmi_es_hs_de),
     .hdmi_vs_de (hdmi_es_vs_de),
     .hdmi_data_de (hdmi_es_data),
-    .hdmi_data (hdmi_16_es_data));
+    .hdmi_data (hdmi_es_data_s));
 
 endmodule
 

From bb4ed42a932c3e422f04074d67ee0222db0b9503 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 13:24:02 -0400
Subject: [PATCH 214/972] ad9361- add missing wires

---
 library/axi_ad9361/axi_ad9361.v | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index e3808214c..64da73b26 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -353,6 +353,10 @@ module axi_ad9361 (
   wire            tdd_enable_s;
   wire            tdd_txnrx_s;
   wire            tdd_mode_s;
+  wire            adc_valid_i0_s;
+  wire            adc_valid_q0_s;
+  wire            adc_valid_i1_s;
+  wire            adc_valid_q1_s;
   wire    [15:0]  adc_data_i0_s;
   wire    [15:0]  adc_data_q0_s;
   wire    [15:0]  adc_data_i1_s;

From d7f0bd1b7688fb76d9dd22e071430c2385ee420a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 13:24:51 -0400
Subject: [PATCH 215/972] ad9361- add reset sink

---
 library/axi_ad9361/axi_ad9361_hw.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 07a3ede20..a0a3b1eb9 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -144,7 +144,7 @@ ad_alt_intf clock l_clk output 1
 ad_alt_intf clock clk input 1
 
 ad_alt_intf reset rst output 1 if_clk
-set_interface_property if_rst associatedResetSinks none
+set_interface_property if_rst associatedResetSinks s_axi_reset
 
 add_interface adc_ch_0 conduit end
 add_interface_port adc_ch_0 adc_enable_i0 enable Output 1

From 285cbc722597060fb1e88a6dd98c1b58a26bfbb7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 13:27:41 -0400
Subject: [PATCH 216/972] xfifo- fix sdc/xdc names

---
 library/util_rfifo/util_rfifo_hw.tcl | 2 +-
 library/util_wfifo/util_wfifo_hw.tcl | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/util_rfifo/util_rfifo_hw.tcl b/library/util_rfifo/util_rfifo_hw.tcl
index 4bd0df673..f4399da94 100755
--- a/library/util_rfifo/util_rfifo_hw.tcl
+++ b/library/util_rfifo/util_rfifo_hw.tcl
@@ -17,7 +17,7 @@ add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL util_rfifo
 add_fileset_file ad_mem.v               VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
 add_fileset_file util_rfifo.v           VERILOG PATH util_rfifo.v TOP_LEVEL_FILE
-add_fileset_file util_rfifo_constr.sdc  SDC     PATH util_rfifo_constr.xdc
+add_fileset_file util_rfifo_constr.sdc  SDC     PATH util_rfifo_constr.sdc
 
 # parameters
 
diff --git a/library/util_wfifo/util_wfifo_hw.tcl b/library/util_wfifo/util_wfifo_hw.tcl
index 8c7912dc4..64b2621f5 100755
--- a/library/util_wfifo/util_wfifo_hw.tcl
+++ b/library/util_wfifo/util_wfifo_hw.tcl
@@ -17,7 +17,7 @@ add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL util_wfifo
 add_fileset_file ad_mem.v               VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
 add_fileset_file util_wfifo.v           VERILOG PATH util_wfifo.v TOP_LEVEL_FILE
-add_fileset_file util_wfifo_constr.sdc  SDC     PATH util_wfifo_constr.xdc
+add_fileset_file util_wfifo_constr.sdc  SDC     PATH util_wfifo_constr.sdc
 
 # parameters
 

From e15893444cfbb2e31c513712b6d9c0e5f7c8f3a8 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 13:28:24 -0400
Subject: [PATCH 217/972] upack- fix interface names

---
 library/util_upack/util_upack_hw.tcl | 119 +++++++++++++++------------
 1 file changed, 67 insertions(+), 52 deletions(-)

diff --git a/library/util_upack/util_upack_hw.tcl b/library/util_upack/util_upack_hw.tcl
index 0217d3734..c7444712d 100755
--- a/library/util_upack/util_upack_hw.tcl
+++ b/library/util_upack/util_upack_hw.tcl
@@ -39,76 +39,91 @@ set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
 # defaults
 
 ad_alt_intf clock   dac_clk         input   1
-ad_alt_intf signal  dma_xfer_in     input   1                                   xfer_req
-ad_alt_intf signal  dac_xfer_out    output  1                                   xfer_req
-ad_alt_intf signal  dac_valid       output  1                                   valid
-ad_alt_intf signal  dac_sync        output  1                                   sync
+
+ad_alt_intf signal  dma_xfer_in     input   1 xfer_req
+ad_alt_intf signal  dac_xfer_out    output  1 xfer_req
+
+ad_alt_intf signal  dac_valid       output  1 valid
+ad_alt_intf signal  dac_sync        output  1 sync
 ad_alt_intf signal  dac_data        input   NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH  data
 
-add_interface fifo_ch_0 conduit end
-#set_interface_property fifo_ch_0  associatedClock if_dac_clk
-add_interface_port fifo_ch_0  dac_enable_0  enable   Input  1
-add_interface_port fifo_ch_0  dac_valid_0   valid    Input  1
-#add_interface_port fifo_ch_0  upack_valid_0 valid_o  Output  1
-add_interface_port fifo_ch_0  dac_data_0    data     Output  CHANNEL_DATA_WIDTH
+add_interface dac_ch_0 conduit end
+add_interface_port dac_ch_0  dac_enable_0  enable   Input  1
+add_interface_port dac_ch_0  dac_valid_0   valid    Input  1
+add_interface_port dac_ch_0  dac_data_0    data     Output CHANNEL_DATA_WIDTH
+
+set_interface_property dac_ch_0  associatedClock if_dac_clk
 
 proc p_util_upack {} {
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 1} {
-    add_interface fifo_ch_1 conduit end
-    #set_interface_property fifo_ch_1  associatedClock if_dac_clk
-    add_interface_port fifo_ch_1  dac_enable_1  enable   Input  1
-    add_interface_port fifo_ch_1  dac_valid_1   valid    Input  1
-#    add_interface_port fifo_ch_1  upack_valid_1 valid_o  Output  1
-    add_interface_port fifo_ch_1  dac_data_1    data     Output  CHANNEL_DATA_WIDTH
+
+    add_interface dac_ch_1 conduit end
+    add_interface_port dac_ch_1  dac_enable_1  enable   Input  1
+    add_interface_port dac_ch_1  dac_valid_1   valid    Input  1
+    add_interface_port dac_ch_1  dac_data_1    data     Output CHANNEL_DATA_WIDTH
+
+    set_interface_property dac_ch_1  associatedClock if_dac_clk
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
-    add_interface fifo_ch_2 conduit end
-    #set_interface_property fifo_ch_2  associatedClock if_dac_clk
-    add_interface_port fifo_ch_2  dac_enable_2  enable   Input  1
-    add_interface_port fifo_ch_2  dac_valid_2   valid    Input  1
-#    add_interface_port fifo_ch_2  upack_valid_2 valid_o  Output  1
-    add_interface_port fifo_ch_2  dac_data_2    data     Output  CHANNEL_DATA_WIDTH
+
+    add_interface dac_ch_2 conduit end
+    add_interface_port dac_ch_2  dac_enable_2  enable   Input  1
+    add_interface_port dac_ch_2  dac_valid_2   valid    Input  1
+    add_interface_port dac_ch_2  dac_data_2    data     Output CHANNEL_DATA_WIDTH
+
+    set_interface_property dac_ch_2  associatedClock if_dac_clk
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
-    add_interface fifo_ch_3 conduit end
-    #set_interface_property fifo_ch_3  associatedClock if_dac_clk
-    add_interface_port fifo_ch_3  dac_enable_3  enable   Input  1
-    add_interface_port fifo_ch_3  dac_valid_3   valid    Input  1
-#    add_interface_port fifo_ch_3  upack_valid_3 valid_o  Output  1
-    add_interface_port fifo_ch_3  dac_data_3    data     Output  CHANNEL_DATA_WIDTH
+
+    add_interface dac_ch_3 conduit end
+    add_interface_port dac_ch_3  dac_enable_3  enable   Input  1
+    add_interface_port dac_ch_3  dac_valid_3   valid    Input  1
+    add_interface_port dac_ch_3  dac_data_3    data     Output CHANNEL_DATA_WIDTH
+
+    set_interface_property dac_ch_3  associatedClock if_dac_clk
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
-    add_interface fifo_ch_4 conduit end
-    #set_interface_property fifo_ch_4  associatedClock if_dac_clk
-    add_interface_port fifo_ch_4  dac_enable_4  enable   Input  1
-    add_interface_port fifo_ch_4  dac_valid_4   valid    Input  1
-#    add_interface_port fifo_ch_4  upack_valid_4 valid_o  Output  1
-    add_interface_port fifo_ch_4  dac_data_4    data     Output  CHANNEL_DATA_WIDTH
+
+    add_interface dac_ch_4 conduit end
+    add_interface_port dac_ch_4  dac_enable_4  enable   Input  1
+    add_interface_port dac_ch_4  dac_valid_4   valid    Input  1
+    add_interface_port dac_ch_4  dac_data_4    data     Output CHANNEL_DATA_WIDTH
+
+    set_interface_property dac_ch_4  associatedClock if_dac_clk
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
-    add_interface fifo_ch_5 conduit end
-    #set_interface_property fifo_ch_5  associatedClock if_dac_clk
-    add_interface_port fifo_ch_5  dac_enable_5  enable   Input  1
-    add_interface_port fifo_ch_5  dac_valid_5   valid    Input  1
-#    add_interface_port fifo_ch_5  upack_valid_5 valid_o  Output  1
-    add_interface_port fifo_ch_5  dac_data_5    data     Output  CHANNEL_DATA_WIDTH
+
+    add_interface dac_ch_5 conduit end
+    add_interface_port dac_ch_5  dac_enable_5  enable   Input  1
+    add_interface_port dac_ch_5  dac_valid_5   valid    Input  1
+    add_interface_port dac_ch_5  dac_data_5    data     Output CHANNEL_DATA_WIDTH
+
+    set_interface_property dac_ch_5  associatedClock if_dac_clk
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
-    add_interface fifo_ch_6 conduit end
-    #set_interface_property fifo_ch_6  associatedClock if_dac_clk
-    add_interface_port fifo_ch_6  dac_enable_6  enable   Input  1
-    add_interface_port fifo_ch_6  dac_valid_6   valid    Input  1
-#    add_interface_port fifo_ch_6  upack_valid_6 valid_o  Output  1
-    add_interface_port fifo_ch_6  dac_data_6    data     Output  CHANNEL_DATA_WIDTH
+
+    add_interface dac_ch_6 conduit end
+    add_interface_port dac_ch_6  dac_enable_6  enable   Input  1
+    add_interface_port dac_ch_6  dac_valid_6   valid    Input  1
+    add_interface_port dac_ch_6  dac_data_6    data     Output CHANNEL_DATA_WIDTH
+
+    set_interface_property dac_ch_6  associatedClock if_dac_clk
   }
+
   if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
-    add_interface fifo_ch_7 conduit end
-    #set_interface_property fifo_ch_7  associatedClock if_dac_clk
-    add_interface_port fifo_ch_7  dac_enable_7  enable   Input  1
-    add_interface_port fifo_ch_7  dac_valid_7   valid    Input  1
-#    add_interface_port fifo_ch_7  upack_valid_7 valid_o  Output  1
-    add_interface_port fifo_ch_7  dac_data_7    data     Output  CHANNEL_DATA_WIDTH
+
+    add_interface dac_ch_7 conduit end
+    add_interface_port dac_ch_7  dac_enable_7  enable   Input  1
+    add_interface_port dac_ch_7  dac_valid_7   valid    Input  1
+    add_interface_port dac_ch_7  dac_data_7    data     Output CHANNEL_DATA_WIDTH
+
+    set_interface_property dac_ch_7  associatedClock if_dac_clk
   }
 }
 

From a262eb7ab35e9efbf251ce66748d6c31b368d3b2 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 18 May 2016 13:21:30 -0400
Subject: [PATCH 218/972] ad9361- output-rst - associated-rst issue?

---
 library/axi_ad9361/axi_ad9361_hw.tcl | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index a0a3b1eb9..974e2e720 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -152,7 +152,7 @@ add_interface_port adc_ch_0 adc_valid_i0 valid Output 1
 add_interface_port adc_ch_0 adc_data_i0 data Output 16
 
 set_interface_property adc_ch_0 associatedClock if_clk
-set_interface_property adc_ch_0 associatedReset if_rst
+set_interface_property adc_ch_0 associatedReset none
 
 add_interface adc_ch_1 conduit end
 add_interface_port adc_ch_1 adc_enable_q0 enable Output 1
@@ -160,7 +160,7 @@ add_interface_port adc_ch_1 adc_valid_q0 valid Output 1
 add_interface_port adc_ch_1 adc_data_q0 data Output 16
 
 set_interface_property adc_ch_1 associatedClock if_clk
-set_interface_property adc_ch_1 associatedReset if_rst
+set_interface_property adc_ch_1 associatedReset none
 
 add_interface adc_ch_2 conduit end
 add_interface_port adc_ch_2 adc_enable_i1 enable Output 1
@@ -168,7 +168,7 @@ add_interface_port adc_ch_2 adc_valid_i1 valid Output 1
 add_interface_port adc_ch_2 adc_data_i1 data Output 16
 
 set_interface_property adc_ch_2 associatedClock if_clk
-set_interface_property adc_ch_2 associatedReset if_rst
+set_interface_property adc_ch_2 associatedReset none
 
 add_interface adc_ch_3 conduit end
 add_interface_port adc_ch_3 adc_enable_q1 enable Output 1
@@ -176,7 +176,7 @@ add_interface_port adc_ch_3 adc_valid_q1 valid Output 1
 add_interface_port adc_ch_3 adc_data_q1 data Output 16
 
 set_interface_property adc_ch_3 associatedClock if_clk
-set_interface_property adc_ch_3 associatedReset if_rst
+set_interface_property adc_ch_3 associatedReset none
 
 ad_alt_intf signal adc_dovf input 1 ovf
 ad_alt_intf signal adc_dunf input 1 unf
@@ -188,7 +188,7 @@ add_interface_port dac_ch_0 dac_valid_i0 valid Output 1
 add_interface_port dac_ch_0 dac_data_i0 data Input 16
 
 set_interface_property dac_ch_0 associatedClock if_clk
-set_interface_property dac_ch_0 associatedReset if_rst
+set_interface_property dac_ch_0 associatedReset none
 
 add_interface dac_ch_1 conduit end
 add_interface_port dac_ch_1 dac_enable_q0 enable Output 1
@@ -196,7 +196,7 @@ add_interface_port dac_ch_1 dac_valid_q0 valid Output 1
 add_interface_port dac_ch_1 dac_data_q0 data Input 16
 
 set_interface_property dac_ch_1 associatedClock if_clk
-set_interface_property dac_ch_1 associatedReset if_rst
+set_interface_property dac_ch_1 associatedReset none
 
 add_interface dac_ch_2 conduit end
 add_interface_port dac_ch_2 dac_enable_i1 enable Output 1
@@ -204,7 +204,7 @@ add_interface_port dac_ch_2 dac_valid_i1 valid Output 1
 add_interface_port dac_ch_2 dac_data_i1 data Input 16
 
 set_interface_property dac_ch_2 associatedClock if_clk
-set_interface_property dac_ch_2 associatedReset if_rst
+set_interface_property dac_ch_2 associatedReset none
 
 add_interface dac_ch_3 conduit end
 add_interface_port dac_ch_3 dac_enable_q1 enable Output 1
@@ -212,7 +212,7 @@ add_interface_port dac_ch_3 dac_valid_q1 valid Output 1
 add_interface_port dac_ch_3 dac_data_q1 data Input 16
 
 set_interface_property dac_ch_3 associatedClock if_clk
-set_interface_property dac_ch_3 associatedReset if_rst
+set_interface_property dac_ch_3 associatedReset none
 
 ad_alt_intf signal dac_dovf input 1 ovf
 ad_alt_intf signal dac_dunf input 1 unf
@@ -239,12 +239,12 @@ proc p_axi_ad9361 {} {
 
   if {$m_cmos_or_lvds_n == 1} {
 
-    add_interface_port device_if rx_clk_in rx_clk_in_p Input 1
-    add_interface_port device_if rx_frame_in rx_frame_in_p Input 1
-    add_interface_port device_if rx_data_in rx_data_in_p Input 12
-    add_interface_port device_if tx_clk_out tx_clk_out_p Output 1
-    add_interface_port device_if tx_frame_out tx_frame_out_p Output 1
-    add_interface_port device_if tx_data_out tx_data_out_p Output 12
+    add_interface_port device_if rx_clk_in rx_clk_in Input 1
+    add_interface_port device_if rx_frame_in rx_frame_in Input 1
+    add_interface_port device_if rx_data_in rx_data_in Input 12
+    add_interface_port device_if tx_clk_out tx_clk_out Output 1
+    add_interface_port device_if tx_frame_out tx_frame_out Output 1
+    add_interface_port device_if tx_data_out tx_data_out Output 12
   }
 
   if {$m_cmos_or_lvds_n == 0} {

From 7fdaee186c04899b861140e3348ce14131410502 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 18 May 2016 13:22:04 -0400
Subject: [PATCH 219/972] upack/cpack- qsys ip

---
 library/util_cpack/util_cpack_hw.tcl | 16 ++++++++--------
 library/util_upack/util_upack_hw.tcl |  1 +
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/library/util_cpack/util_cpack_hw.tcl b/library/util_cpack/util_cpack_hw.tcl
index 5cabc02e8..cb375a5b3 100755
--- a/library/util_cpack/util_cpack_hw.tcl
+++ b/library/util_cpack/util_cpack_hw.tcl
@@ -51,7 +51,7 @@ add_interface_port adc_ch_0  adc_valid_0   valid    Input  1
 add_interface_port adc_ch_0  adc_data_0    data     Input  CHANNEL_DATA_WIDTH
 
 set_interface_property adc_ch_0  associatedClock if_adc_clk
-set_interface_property adc_ch_0  associatedReset if_adc_rst
+set_interface_property adc_ch_0  associatedReset none
 
 proc p_util_cpack {} {
 
@@ -63,7 +63,7 @@ proc p_util_cpack {} {
     add_interface_port adc_ch_1  adc_data_1   data     Input  CHANNEL_DATA_WIDTH
 
     set_interface_property adc_ch_1  associatedClock if_adc_clk
-    set_interface_property adc_ch_1  associatedReset if_adc_rst
+    set_interface_property adc_ch_1  associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
@@ -74,7 +74,7 @@ proc p_util_cpack {} {
     add_interface_port adc_ch_2  adc_data_2   data     Input  CHANNEL_DATA_WIDTH
 
     set_interface_property adc_ch_2  associatedClock if_adc_clk
-    set_interface_property adc_ch_2  associatedReset if_adc_rst
+    set_interface_property adc_ch_2  associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
@@ -85,7 +85,7 @@ proc p_util_cpack {} {
     add_interface_port adc_ch_3  adc_data_3   data     Input  CHANNEL_DATA_WIDTH
 
     set_interface_property adc_ch_3  associatedClock if_adc_clk
-    set_interface_property adc_ch_3  associatedReset if_adc_rst
+    set_interface_property adc_ch_3  associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
@@ -96,7 +96,7 @@ proc p_util_cpack {} {
     add_interface_port adc_ch_4  adc_data_4   data     Input  CHANNEL_DATA_WIDTH
 
     set_interface_property adc_ch_4  associatedClock if_adc_clk
-    set_interface_property adc_ch_4  associatedReset if_adc_rst
+    set_interface_property adc_ch_4  associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
@@ -107,7 +107,7 @@ proc p_util_cpack {} {
     add_interface_port adc_ch_5  adc_data_5   data     Input  CHANNEL_DATA_WIDTH
 
     set_interface_property adc_ch_5  associatedClock if_adc_clk
-    set_interface_property adc_ch_5  associatedReset if_adc_rst
+    set_interface_property adc_ch_5  associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
@@ -118,7 +118,7 @@ proc p_util_cpack {} {
     add_interface_port adc_ch_6  adc_data_6   data     Input  CHANNEL_DATA_WIDTH
 
     set_interface_property adc_ch_6  associatedClock if_adc_clk
-    set_interface_property adc_ch_6  associatedReset if_adc_rst
+    set_interface_property adc_ch_6  associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
@@ -129,7 +129,7 @@ proc p_util_cpack {} {
     add_interface_port adc_ch_7  adc_data_7   data     Input  CHANNEL_DATA_WIDTH
 
     set_interface_property adc_ch_7  associatedClock if_adc_clk
-    set_interface_property adc_ch_7  associatedReset if_adc_rst
+    set_interface_property adc_ch_7  associatedReset none
   }
 }
 
diff --git a/library/util_upack/util_upack_hw.tcl b/library/util_upack/util_upack_hw.tcl
index c7444712d..7e4ecc1d0 100755
--- a/library/util_upack/util_upack_hw.tcl
+++ b/library/util_upack/util_upack_hw.tcl
@@ -53,6 +53,7 @@ add_interface_port dac_ch_0  dac_valid_0   valid    Input  1
 add_interface_port dac_ch_0  dac_data_0    data     Output CHANNEL_DATA_WIDTH
 
 set_interface_property dac_ch_0  associatedClock if_dac_clk
+set_interface_property dac_ch_0  associatedReset none
 
 proc p_util_upack {} {
 

From bf0b90229a4ba999301fb8b90700fd385c2a609c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 18 May 2016 13:22:38 -0400
Subject: [PATCH 220/972] rfifo/wfifo- qsys ip

---
 library/util_rfifo/util_rfifo.v          |  5 +++-
 library/util_rfifo/util_rfifo_constr.sdc |  2 +-
 library/util_rfifo/util_rfifo_hw.tcl     | 35 +++++++++++++-----------
 library/util_wfifo/util_wfifo.v          |  5 +++-
 library/util_wfifo/util_wfifo_constr.sdc |  2 +-
 library/util_wfifo/util_wfifo_hw.tcl     | 35 +++++++++++++-----------
 6 files changed, 48 insertions(+), 36 deletions(-)

diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v
index 8cf395c9d..67e295cba 100644
--- a/library/util_rfifo/util_rfifo.v
+++ b/library/util_rfifo/util_rfifo.v
@@ -183,6 +183,7 @@ module util_rfifo (
   reg                                 din_req_t_m1 = 'd0;
   reg                                 din_req_t_m2 = 'd0;
   reg                                 din_req_t_m3 = 'd0;
+  reg                                 din_unf_d = 'd0;
   reg     [(T_DOUT_DATA_WIDTH+1):0]   dout_data = 'd0;
   reg     [(DATA_WIDTH-1):0]          dout_rdata = 'd0;
   reg     [ 7:0]                      dout_enable = 'd0;
@@ -294,12 +295,14 @@ module util_rfifo (
       din_req_t_m1 <= 'd0;
       din_req_t_m2 <= 'd0;
       din_req_t_m3 <= 'd0;
+      din_unf_d <= 'd0;
     end else begin
       din_enable_m1 <= dout_enable;
       din_enable <= din_enable_m1;
       din_req_t_m1 <= dout_req_t;
       din_req_t_m2 <= din_req_t_m1;
       din_req_t_m3 <= din_req_t_m2;
+      din_unf_d <= din_unf;
     end
   end
 
@@ -367,7 +370,7 @@ module util_rfifo (
       dout_unf_m1 <= 'd0;
       dout_unf <= 'd0;
     end else begin
-      dout_unf_m1 <= din_unf;
+      dout_unf_m1 <= din_unf_d;
       dout_unf <= dout_unf_m1;
     end
   end
diff --git a/library/util_rfifo/util_rfifo_constr.sdc b/library/util_rfifo/util_rfifo_constr.sdc
index 121bac542..99764df65 100644
--- a/library/util_rfifo/util_rfifo_constr.sdc
+++ b/library/util_rfifo/util_rfifo_constr.sdc
@@ -1,5 +1,5 @@
 
 set_false_path -from [get_registers *dout_enable*]  -to [get_registers *din_enable_m1*]
 set_false_path -from [get_registers *dout_req_t*]   -to [get_registers *din_req_t_m1*]
-set_false_path -from [get_registers *din_unf*]      -to [get_registers *dout_unf_m1*]
+set_false_path -from [get_registers *din_unf_d*]    -to [get_registers *dout_unf_m1*]
 
diff --git a/library/util_rfifo/util_rfifo_hw.tcl b/library/util_rfifo/util_rfifo_hw.tcl
index f4399da94..064b8de18 100755
--- a/library/util_rfifo/util_rfifo_hw.tcl
+++ b/library/util_rfifo/util_rfifo_hw.tcl
@@ -63,7 +63,7 @@ add_interface_port din_0  din_valid_0   valid    Output 1
 add_interface_port din_0  din_data_0    data     Input  DIN_DATA_WIDTH
 
 set_interface_property din_0 associatedClock if_din_clk
-set_interface_property din_0 associatedReset if_din_rstn
+set_interface_property din_0 associatedReset none
 
 add_interface dout_0 conduit end
 add_interface_port dout_0 dout_enable_0 enable   Input  1
@@ -71,7 +71,10 @@ add_interface_port dout_0 dout_valid_0  valid    Input  1
 add_interface_port dout_0 dout_data_0   data     Output DOUT_DATA_WIDTH
 
 set_interface_property dout_0 associatedClock if_dout_clk
-set_interface_property dout_0 associatedReset if_dout_rst
+set_interface_property dout_0 associatedReset none
+
+ad_alt_intf signal din_unf input 1 unf
+ad_alt_intf signal dout_unf output 1 unf
 
 proc p_util_rfifo {} {
 
@@ -83,7 +86,7 @@ proc p_util_rfifo {} {
     add_interface_port din_1  din_data_1    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_1 associatedClock if_din_clk
-    set_interface_property din_1 associatedReset if_din_rstn
+    set_interface_property din_1 associatedReset none
 
     add_interface dout_1 conduit end
     add_interface_port dout_1 dout_enable_1 enable   Input  1
@@ -91,7 +94,7 @@ proc p_util_rfifo {} {
     add_interface_port dout_1 dout_data_1   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_1 associatedClock if_dout_clk
-    set_interface_property dout_1 associatedReset if_dout_rst
+    set_interface_property dout_1 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
@@ -102,7 +105,7 @@ proc p_util_rfifo {} {
     add_interface_port din_2  din_data_2    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_2 associatedClock if_din_clk
-    set_interface_property din_2 associatedReset if_din_rstn
+    set_interface_property din_2 associatedReset none
 
     add_interface dout_2 conduit end
     add_interface_port dout_2 dout_enable_2 enable   Input  1
@@ -110,7 +113,7 @@ proc p_util_rfifo {} {
     add_interface_port dout_2 dout_data_2   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_2 associatedClock if_dout_clk
-    set_interface_property dout_2 associatedReset if_dout_rst
+    set_interface_property dout_2 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
@@ -121,7 +124,7 @@ proc p_util_rfifo {} {
     add_interface_port din_3  din_data_3    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_3 associatedClock if_din_clk
-    set_interface_property din_3 associatedReset if_din_rstn
+    set_interface_property din_3 associatedReset none
 
     add_interface dout_3 conduit end
     add_interface_port dout_3 dout_enable_3 enable   Input  1
@@ -129,7 +132,7 @@ proc p_util_rfifo {} {
     add_interface_port dout_3 dout_data_3   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_3 associatedClock if_dout_clk
-    set_interface_property dout_3 associatedReset if_dout_rst
+    set_interface_property dout_3 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
@@ -140,7 +143,7 @@ proc p_util_rfifo {} {
     add_interface_port din_4  din_data_4    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_4 associatedClock if_din_clk
-    set_interface_property din_4 associatedReset if_din_rstn
+    set_interface_property din_4 associatedReset none
 
     add_interface dout_4 conduit end
     add_interface_port dout_4 dout_enable_4 enable   Input  1
@@ -148,7 +151,7 @@ proc p_util_rfifo {} {
     add_interface_port dout_4 dout_data_4   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_4 associatedClock if_dout_clk
-    set_interface_property dout_4 associatedReset if_dout_rst
+    set_interface_property dout_4 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
@@ -159,7 +162,7 @@ proc p_util_rfifo {} {
     add_interface_port din_5  din_data_5    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_5 associatedClock if_din_clk
-    set_interface_property din_5 associatedReset if_din_rstn
+    set_interface_property din_5 associatedReset none
 
     add_interface dout_5 conduit end
     add_interface_port dout_5 dout_enable_5 enable   Input  1
@@ -167,7 +170,7 @@ proc p_util_rfifo {} {
     add_interface_port dout_5 dout_data_5   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_5 associatedClock if_dout_clk
-    set_interface_property dout_5 associatedReset if_dout_rst
+    set_interface_property dout_5 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
@@ -178,7 +181,7 @@ proc p_util_rfifo {} {
     add_interface_port din_6  din_data_6    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_6 associatedClock if_din_clk
-    set_interface_property din_6 associatedReset if_din_rstn
+    set_interface_property din_6 associatedReset none
 
     add_interface dout_6 conduit end
     add_interface_port dout_6 dout_enable_6 enable   Input  1
@@ -186,7 +189,7 @@ proc p_util_rfifo {} {
     add_interface_port dout_6 dout_data_6   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_6 associatedClock if_dout_clk
-    set_interface_property dout_6 associatedReset if_dout_rst
+    set_interface_property dout_6 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
@@ -197,7 +200,7 @@ proc p_util_rfifo {} {
     add_interface_port din_7  din_data_7    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_7 associatedClock if_din_clk
-    set_interface_property din_7 associatedReset if_din_rstn
+    set_interface_property din_7 associatedReset none
 
     add_interface dout_7 conduit end
     add_interface_port dout_7 dout_enable_7 enable   Input  1
@@ -205,7 +208,7 @@ proc p_util_rfifo {} {
     add_interface_port dout_7 dout_data_7   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_7 associatedClock if_dout_clk
-    set_interface_property dout_7 associatedReset if_dout_rst
+    set_interface_property dout_7 associatedReset none
   }
 
 }
diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v
index f073b3318..7a446ed10 100644
--- a/library/util_wfifo/util_wfifo.v
+++ b/library/util_wfifo/util_wfifo.v
@@ -185,6 +185,7 @@ module util_wfifo (
   reg                                 dout_req_t_m1 = 'd0;
   reg                                 dout_req_t_m2 = 'd0;
   reg                                 dout_req_t_m3 = 'd0;
+  reg                                 dout_ovf_d = 'd0;
   reg     [ 3:0]                      dout_req_cnt = 'd0;
   reg     [(ADDRESS_WIDTH-1):0]       dout_raddr = 'd0;
   reg                                 dout_rd = 'd0;
@@ -265,7 +266,7 @@ module util_wfifo (
       if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd0)) begin
         din_req_t <= ~din_req_t;
       end
-      din_ovf_m1 <= dout_ovf;
+      din_ovf_m1 <= dout_ovf_d;
       din_ovf <= din_ovf_m1;
     end
   end
@@ -279,10 +280,12 @@ module util_wfifo (
       dout_req_t_m1 <= 'd0;
       dout_req_t_m2 <= 'd0;
       dout_req_t_m3 <= 'd0;
+      dout_ovf_d <= 'd0;
     end else begin
       dout_req_t_m1 <= din_req_t;
       dout_req_t_m2 <= dout_req_t_m1;
       dout_req_t_m3 <= dout_req_t_m2;
+      dout_ovf_d <= dout_ovf;
     end
   end
 
diff --git a/library/util_wfifo/util_wfifo_constr.sdc b/library/util_wfifo/util_wfifo_constr.sdc
index 3e298bd37..8d24422e1 100644
--- a/library/util_wfifo/util_wfifo_constr.sdc
+++ b/library/util_wfifo/util_wfifo_constr.sdc
@@ -1,5 +1,5 @@
 
 set_false_path -from [get_registers *din_enable*] -to [get_registers *dout_enable_m1*]
 set_false_path -from [get_registers *din_req_t*]  -to [get_registers *dout_req_t_m1*]
-set_false_path -from [get_registers *dout_ovf*]   -to [get_registers *din_ovf_m1*]
+set_false_path -from [get_registers *dout_ovf_d*] -to [get_registers *din_ovf_m1*]
 
diff --git a/library/util_wfifo/util_wfifo_hw.tcl b/library/util_wfifo/util_wfifo_hw.tcl
index 64b2621f5..c6468f132 100755
--- a/library/util_wfifo/util_wfifo_hw.tcl
+++ b/library/util_wfifo/util_wfifo_hw.tcl
@@ -63,7 +63,7 @@ add_interface_port din_0  din_valid_0   valid    Input  1
 add_interface_port din_0  din_data_0    data     Input  DIN_DATA_WIDTH
 
 set_interface_property din_0 associatedClock if_din_clk
-set_interface_property din_0 associatedReset if_din_rst
+set_interface_property din_0 associatedReset none
 
 add_interface dout_0 conduit end
 add_interface_port dout_0 dout_enable_0 enable   Output 1
@@ -71,7 +71,10 @@ add_interface_port dout_0 dout_valid_0  valid    Output 1
 add_interface_port dout_0 dout_data_0   data     Output DOUT_DATA_WIDTH
 
 set_interface_property dout_0 associatedClock if_dout_clk
-set_interface_property dout_0 associatedReset if_dout_rstn
+set_interface_property dout_0 associatedReset none
+
+ad_alt_intf signal din_ovf output 1 ovf
+ad_alt_intf signal dout_ovf input 1 ovf
 
 proc p_util_wfifo {} {
 
@@ -83,7 +86,7 @@ proc p_util_wfifo {} {
     add_interface_port din_1  din_data_1    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_1 associatedClock if_din_clk
-    set_interface_property din_1 associatedReset if_din_rst
+    set_interface_property din_1 associatedReset none
 
     add_interface dout_1 conduit end
     add_interface_port dout_1 dout_enable_1 enable   Output 1
@@ -91,7 +94,7 @@ proc p_util_wfifo {} {
     add_interface_port dout_1 dout_data_1   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_1 associatedClock if_dout_clk
-    set_interface_property dout_1 associatedReset if_dout_rstn
+    set_interface_property dout_1 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
@@ -102,7 +105,7 @@ proc p_util_wfifo {} {
     add_interface_port din_2  din_data_2    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_2 associatedClock if_din_clk
-    set_interface_property din_2 associatedReset if_din_rst
+    set_interface_property din_2 associatedReset none
 
     add_interface dout_2 conduit end
     add_interface_port dout_2 dout_enable_2 enable   Output 1
@@ -110,7 +113,7 @@ proc p_util_wfifo {} {
     add_interface_port dout_2 dout_data_2   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_2 associatedClock if_dout_clk
-    set_interface_property dout_2 associatedReset if_dout_rstn
+    set_interface_property dout_2 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
@@ -121,7 +124,7 @@ proc p_util_wfifo {} {
     add_interface_port din_3  din_data_3    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_3 associatedClock if_din_clk
-    set_interface_property din_3 associatedReset if_din_rst
+    set_interface_property din_3 associatedReset none
 
     add_interface dout_3 conduit end
     add_interface_port dout_3 dout_enable_3 enable   Output 1
@@ -129,7 +132,7 @@ proc p_util_wfifo {} {
     add_interface_port dout_3 dout_data_3   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_3 associatedClock if_dout_clk
-    set_interface_property dout_3 associatedReset if_dout_rstn
+    set_interface_property dout_3 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
@@ -140,7 +143,7 @@ proc p_util_wfifo {} {
     add_interface_port din_4  din_data_4    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_4 associatedClock if_din_clk
-    set_interface_property din_4 associatedReset if_din_rst
+    set_interface_property din_4 associatedReset none
 
     add_interface dout_4 conduit end
     add_interface_port dout_4 dout_enable_4 enable   Output 1
@@ -148,7 +151,7 @@ proc p_util_wfifo {} {
     add_interface_port dout_4 dout_data_4   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_4 associatedClock if_dout_clk
-    set_interface_property dout_4 associatedReset if_dout_rstn
+    set_interface_property dout_4 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
@@ -159,7 +162,7 @@ proc p_util_wfifo {} {
     add_interface_port din_5  din_data_5    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_5 associatedClock if_din_clk
-    set_interface_property din_5 associatedReset if_din_rst
+    set_interface_property din_5 associatedReset none
 
     add_interface dout_5 conduit end
     add_interface_port dout_5 dout_enable_5 enable   Output 1
@@ -167,7 +170,7 @@ proc p_util_wfifo {} {
     add_interface_port dout_5 dout_data_5   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_5 associatedClock if_dout_clk
-    set_interface_property dout_5 associatedReset if_dout_rstn
+    set_interface_property dout_5 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
@@ -178,7 +181,7 @@ proc p_util_wfifo {} {
     add_interface_port din_6  din_data_6    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_6 associatedClock if_din_clk
-    set_interface_property din_6 associatedReset if_din_rst
+    set_interface_property din_6 associatedReset none
 
     add_interface dout_6 conduit end
     add_interface_port dout_6 dout_enable_6 enable   Output 1
@@ -186,7 +189,7 @@ proc p_util_wfifo {} {
     add_interface_port dout_6 dout_data_6   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_6 associatedClock if_dout_clk
-    set_interface_property dout_6 associatedReset if_dout_rstn
+    set_interface_property dout_6 associatedReset none
   }
 
   if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
@@ -197,7 +200,7 @@ proc p_util_wfifo {} {
     add_interface_port din_7  din_data_7    data     Input  DIN_DATA_WIDTH
 
     set_interface_property din_7 associatedClock if_din_clk
-    set_interface_property din_7 associatedReset if_din_rst
+    set_interface_property din_7 associatedReset none
 
     add_interface dout_7 conduit end
     add_interface_port dout_7 dout_enable_7 enable   Output 1
@@ -205,7 +208,7 @@ proc p_util_wfifo {} {
     add_interface_port dout_7 dout_data_7   data     Output DOUT_DATA_WIDTH
 
     set_interface_property dout_7 associatedClock if_dout_clk
-    set_interface_property dout_7 associatedReset if_dout_rstn
+    set_interface_property dout_7 associatedReset none
   }
 
 }

From 50d018fc11d7466f307a8d2ae4e7d0ae90e00af3 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 18 May 2016 13:24:04 -0400
Subject: [PATCH 221/972] arradio- rfifo/wfifo added

---
 projects/arradio/c5soc/system_constr.sdc |  60 +++---
 projects/arradio/common/arradio_bd.qsys  | 259 ++++++++++++++++++-----
 2 files changed, 241 insertions(+), 78 deletions(-)

diff --git a/projects/arradio/c5soc/system_constr.sdc b/projects/arradio/c5soc/system_constr.sdc
index d6dd5ca69..2848a0de7 100644
--- a/projects/arradio/c5soc/system_constr.sdc
+++ b/projects/arradio/c5soc/system_constr.sdc
@@ -3,41 +3,41 @@ create_clock -period "20.000 ns" -name sys_clk  [get_ports {sys_clk}]
 create_clock -period "12.500 ns" -name dma_clk  [get_pins {*sys_hps*h2f_user0_clk}]
 
 create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}]
-create_clock -period 4.0 -name v_rx_clk
 
 derive_pll_clocks
 derive_clock_uncertainty
 
-create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}]
+#create_clock -period 4.0 -name v_rx_clk
+#create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}]
 
-set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_frame_in}]
-set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[0]}]
-set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[1]}]
-set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[2]}]
-set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[3]}]
-set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[4]}]
-set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[5]}]
-set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_frame_in}]     -clock_fall -add_delay
-set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[0]}]   -clock_fall -add_delay
-set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[1]}]   -clock_fall -add_delay
-set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[2]}]   -clock_fall -add_delay
-set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[3]}]   -clock_fall -add_delay
-set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[4]}]   -clock_fall -add_delay
-set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[5]}]   -clock_fall -add_delay
+#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_frame_in}]
+#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[0]}]
+#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[1]}]
+#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[2]}]
+#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[3]}]
+#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[4]}]
+#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[5]}]
+#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_frame_in}]     -clock_fall -add_delay
+#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[0]}]   -clock_fall -add_delay
+#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[1]}]   -clock_fall -add_delay
+#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[2]}]   -clock_fall -add_delay
+#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[3]}]   -clock_fall -add_delay
+#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[4]}]   -clock_fall -add_delay
+#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[5]}]   -clock_fall -add_delay
 
 
-set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_frame_out}]
-set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[0]}]
-set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[1]}]
-set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[2]}]
-set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[3]}]
-set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[4]}]
-set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[5]}]
-set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_frame_out}]    -clock_fall -add_delay
-set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[0]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[1]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[2]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[3]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[4]}]  -clock_fall -add_delay
-set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[5]}]  -clock_fall -add_delay
+#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_frame_out}]
+#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[0]}]
+#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[1]}]
+#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[2]}]
+#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[3]}]
+#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[4]}]
+#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[5]}]
+#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_frame_out}]    -clock_fall -add_delay
+#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[0]}]  -clock_fall -add_delay
+#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[1]}]  -clock_fall -add_delay
+#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[2]}]  -clock_fall -add_delay
+#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[3]}]  -clock_fall -add_delay
+#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[4]}]  -clock_fall -add_delay
+#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[5]}]  -clock_fall -add_delay
 
diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys
index 14f13bf65..dbd04f1ef 100755
--- a/projects/arradio/common/arradio_bd.qsys
+++ b/projects/arradio/common/arradio_bd.qsys
@@ -81,6 +81,14 @@
          type = "String";
       }
    }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
    element axi_ad9361
    {
       datum _sortIndex
@@ -106,7 +114,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "9";
          type = "int";
       }
       datum sopceditor_expanded
@@ -123,11 +131,11 @@
          type = "String";
       }
    }
-   element axi_dmac_dac
+   element axi_dac_dma
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "10";
          type = "int";
       }
       datum sopceditor_expanded
@@ -136,7 +144,7 @@
          type = "boolean";
       }
    }
-   element axi_dmac_dac.s_axi
+   element axi_dac_dma.s_axi
    {
       datum baseAddress
       {
@@ -144,24 +152,11 @@
          type = "String";
       }
    }
-   element dac_upack
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
    element gpio
    {
       datum _sortIndex
       {
-         value = "11";
+         value = "12";
          type = "int";
       }
    }
@@ -185,7 +180,7 @@
    {
       datum _sortIndex
       {
-         value = "10";
+         value = "11";
          type = "int";
       }
       datum sopceditor_expanded
@@ -222,7 +217,7 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "7";
          type = "int";
       }
       datum sopceditor_expanded
@@ -239,6 +234,27 @@
          type = "int";
       }
    }
+   element util_dac_rfifo
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element util_dac_upack
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
@@ -307,21 +323,21 @@
    dir="end" />
  <interface
    name="axi_dmac_dac_fifo_rd_clock"
-   internal="axi_dmac_dac.fifo_rd_clock" />
- <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
+   internal="axi_dac_dma.fifo_rd_clock" />
+ <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dac_dma.fifo_rd_if" />
  <interface
    name="axi_dmac_dac_intr"
-   internal="axi_dmac_dac.interrupt_sender"
+   internal="axi_dac_dma.interrupt_sender"
    type="interrupt"
    dir="end" />
  <interface
    name="axi_dmac_dac_m_src_axi"
-   internal="axi_dmac_dac.m_src_axi"
+   internal="axi_dac_dma.m_src_axi"
    type="axi4"
    dir="start" />
  <interface
    name="axi_dmac_dac_s_axi"
-   internal="axi_dmac_dac.s_axi"
+   internal="axi_dac_dma.s_axi"
    type="axi4lite"
    dir="end" />
  <interface
@@ -374,7 +390,7 @@
   <parameter name="ID" value="0" />
   <parameter name="SYNC_TRANSFER_START" value="1" />
  </module>
- <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
+ <module name="axi_dac_dma" kind="axi_dmac" version="1.0" enabled="1">
   <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
   <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
   <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
@@ -391,10 +407,6 @@
   <parameter name="ID" value="0" />
   <parameter name="SYNC_TRANSFER_START" value="0" />
  </module>
- <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
  <module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
   <parameter name="bitModifyingOutReg" value="false" />
@@ -454,21 +466,26 @@
   <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
  <module name="util_adc_wfifo" kind="util_wfifo" version="1.0" enabled="1">
-  <parameter name="DIN_ADDRESS_WIDTH" value="8" />
+  <parameter name="DIN_ADDRESS_WIDTH" value="5" />
   <parameter name="DIN_DATA_WIDTH" value="16" />
   <parameter name="DOUT_DATA_WIDTH" value="16" />
   <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
+ <module name="util_dac_rfifo" kind="util_rfifo" version="1.0" enabled="1">
+  <parameter name="DIN_ADDRESS_WIDTH" value="5" />
+  <parameter name="DIN_DATA_WIDTH" value="16" />
+  <parameter name="DOUT_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <module name="util_dac_upack" kind="util_upack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
  <connection
    kind="clock"
    version="15.1"
    start="axi_ad9361.if_l_clk"
    end="axi_ad9361.if_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="dac_upack.if_dac_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -478,7 +495,7 @@
    kind="clock"
    version="15.1"
    start="axi_ad9361.if_l_clk"
-   end="axi_dmac_dac.if_fifo_rd_clk" />
+   end="util_dac_rfifo.if_dout_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -490,11 +507,26 @@
    version="15.1"
    start="mem_clk.out_clk"
    end="util_adc_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="mem_clk.out_clk"
+   end="util_dac_upack.if_dac_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="mem_clk.out_clk"
+   end="util_dac_rfifo.if_din_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="mem_clk.out_clk"
    end="util_adc_wfifo.if_dout_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="mem_clk.out_clk"
+   end="axi_dac_dma.if_fifo_rd_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -509,7 +541,7 @@
    kind="clock"
    version="15.1"
    start="mem_clk.out_clk"
-   end="axi_dmac_dac.m_src_axi_clock" />
+   end="axi_dac_dma.m_src_axi_clock" />
  <connection
    kind="clock"
    version="15.1"
@@ -524,7 +556,7 @@
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="axi_dmac_dac.s_axi_clock" />
+   end="axi_dac_dma.s_axi_clock" />
  <connection
    kind="conduit"
    version="15.1"
@@ -591,6 +623,72 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="util_dac_upack.dac_ch_0"
+   end="util_dac_rfifo.din_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="util_dac_upack.dac_ch_1"
+   end="util_dac_rfifo.din_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.dac_ch_1"
+   end="util_dac_rfifo.dout_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="util_dac_upack.dac_ch_2"
+   end="util_dac_rfifo.din_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="util_dac_upack.dac_ch_3"
+   end="util_dac_rfifo.din_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9361.dac_ch_3"
+   end="util_dac_rfifo.dout_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.1"
@@ -602,6 +700,28 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="util_dac_rfifo.dout_0"
+   end="axi_ad9361.dac_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="util_dac_rfifo.dout_2"
+   end="axi_ad9361.dac_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.1"
@@ -649,8 +769,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="dac_upack.if_dac_data"
-   end="axi_dmac_dac.if_fifo_rd_dout">
+   start="util_dac_upack.if_dac_data"
+   end="axi_dac_dma.if_fifo_rd_dout">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -660,8 +780,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="dac_upack.if_dma_xfer_in"
-   end="axi_dmac_dac.if_fifo_rd_xfer_req">
+   start="util_adc_wfifo.if_din_ovf"
+   end="axi_ad9361.if_adc_dovf">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -671,8 +791,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_dmac_dac.if_fifo_rd_en"
-   end="dac_upack.if_dac_valid">
+   start="util_dac_upack.if_dma_xfer_in"
+   end="axi_dac_dma.if_fifo_rd_xfer_req">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -682,7 +802,7 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_dmac_dac.if_fifo_rd_underflow"
+   start="util_dac_rfifo.if_dout_unf"
    end="axi_ad9361.if_dac_dunf">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
@@ -690,16 +810,59 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_dac_dma.if_fifo_rd_en"
+   end="util_dac_upack.if_dac_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_dac_dma.if_fifo_rd_underflow"
+   end="util_dac_rfifo.if_din_unf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_adc_dma.if_fifo_wr_overflow"
+   end="util_adc_wfifo.if_dout_ovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="reset"
    version="15.1"
    start="axi_ad9361.if_rst"
    end="util_adc_wfifo.if_din_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="axi_ad9361.if_rst"
+   end="util_dac_rfifo.if_dout_rst" />
  <connection
    kind="reset"
    version="15.1"
    start="mem_rst.out_reset"
    end="util_adc_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="mem_rst.out_reset"
+   end="util_dac_rfifo.if_din_rstn" />
  <connection
    kind="reset"
    version="15.1"
@@ -714,7 +877,7 @@
    kind="reset"
    version="15.1"
    start="mem_rst.out_reset"
-   end="axi_dmac_dac.m_src_axi_reset" />
+   end="axi_dac_dma.m_src_axi_reset" />
  <connection
    kind="reset"
    version="15.1"
@@ -739,7 +902,7 @@
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="axi_dmac_dac.s_axi_reset" />
+   end="axi_dac_dma.s_axi_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
  <interconnectRequirement

From b5b05bb9d1aa2286512aac162ecd9b0d99c70527 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 20 May 2016 11:41:54 -0400
Subject: [PATCH 222/972] axi_ad9371: added

---
 library/axi_ad9371/axi_ad9371.v            | 401 +++++++++++++++++++++
 library/axi_ad9371/axi_ad9371_if.v         | 119 ++++++
 library/axi_ad9371/axi_ad9371_ip.tcl       |  43 +++
 library/axi_ad9371/axi_ad9371_rx.v         | 344 ++++++++++++++++++
 library/axi_ad9371/axi_ad9371_rx_channel.v | 256 +++++++++++++
 library/axi_ad9371/axi_ad9371_rx_os.v      | 261 ++++++++++++++
 library/axi_ad9371/axi_ad9371_tx.v         | 329 +++++++++++++++++
 library/axi_ad9371/axi_ad9371_tx_channel.v | 283 +++++++++++++++
 8 files changed, 2036 insertions(+)
 create mode 100644 library/axi_ad9371/axi_ad9371.v
 create mode 100644 library/axi_ad9371/axi_ad9371_if.v
 create mode 100755 library/axi_ad9371/axi_ad9371_ip.tcl
 create mode 100644 library/axi_ad9371/axi_ad9371_rx.v
 create mode 100644 library/axi_ad9371/axi_ad9371_rx_channel.v
 create mode 100644 library/axi_ad9371/axi_ad9371_rx_os.v
 create mode 100644 library/axi_ad9371/axi_ad9371_tx.v
 create mode 100644 library/axi_ad9371/axi_ad9371_tx_channel.v

diff --git a/library/axi_ad9371/axi_ad9371.v b/library/axi_ad9371/axi_ad9371.v
new file mode 100644
index 000000000..1adef14f0
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371.v
@@ -0,0 +1,401 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9371 (
+
+  // receive
+
+  adc_clk,
+  adc_rx_data,
+  adc_os_clk,
+  adc_rx_os_data,
+
+  // transmit
+
+  dac_clk,
+  dac_tx_data,
+
+  // master/slave
+
+  dac_sync_in,
+  dac_sync_out,
+
+  // dma interface
+
+  adc_enable_i0,
+  adc_valid_i0,
+  adc_data_i0,
+  adc_enable_q0,
+  adc_valid_q0,
+  adc_data_q0,
+  adc_enable_i1,
+  adc_valid_i1,
+  adc_data_i1,
+  adc_enable_q1,
+  adc_valid_q1,
+  adc_data_q1,
+  adc_dovf,
+  adc_dunf,
+
+  adc_os_enable_i0,
+  adc_os_valid_i0,
+  adc_os_data_i0,
+  adc_os_enable_q0,
+  adc_os_valid_q0,
+  adc_os_data_q0,
+  adc_os_dovf,
+  adc_os_dunf,
+
+  dac_enable_i0,
+  dac_valid_i0,
+  dac_data_i0,
+  dac_enable_q0,
+  dac_valid_q0,
+  dac_data_q0,
+  dac_enable_i1,
+  dac_valid_i1,
+  dac_data_i1,
+  dac_enable_q1,
+  dac_valid_q1,
+  dac_data_q1,
+  dac_dovf,
+  dac_dunf,
+
+  // axi interface
+
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awvalid,
+  s_axi_awaddr,
+  s_axi_awprot,
+  s_axi_awready,
+  s_axi_wvalid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wready,
+  s_axi_bvalid,
+  s_axi_bresp,
+  s_axi_bready,
+  s_axi_arvalid,
+  s_axi_araddr,
+  s_axi_arprot,
+  s_axi_arready,
+  s_axi_rvalid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rready);
+
+  // parameters
+
+  parameter   ID = 0;
+  parameter   DAC_DATAPATH_DISABLE = 0;
+  parameter   ADC_DATAPATH_DISABLE = 0;
+
+  // receive
+
+  input             adc_clk;
+  input   [ 63:0]   adc_rx_data;
+  input             adc_os_clk;
+  input   [ 63:0]   adc_rx_os_data;
+
+  // transmit
+
+  input             dac_clk;
+  output  [127:0]   dac_tx_data;
+
+  // master/slave
+
+  input             dac_sync_in;
+  output            dac_sync_out;
+
+  // dma interface
+
+  output            adc_enable_i0;
+  output            adc_valid_i0;
+  output  [ 15:0]   adc_data_i0;
+  output            adc_enable_q0;
+  output            adc_valid_q0;
+  output  [ 15:0]   adc_data_q0;
+  output            adc_enable_i1;
+  output            adc_valid_i1;
+  output  [ 15:0]   adc_data_i1;
+  output            adc_enable_q1;
+  output            adc_valid_q1;
+  output  [ 15:0]   adc_data_q1;
+  input             adc_dovf;
+  input             adc_dunf;
+
+  output            adc_os_enable_i0;
+  output            adc_os_valid_i0;
+  output  [ 31:0]   adc_os_data_i0;
+  output            adc_os_enable_q0;
+  output            adc_os_valid_q0;
+  output  [ 31:0]   adc_os_data_q0;
+  input             adc_os_dovf;
+  input             adc_os_dunf;
+
+  output            dac_enable_i0;
+  output            dac_valid_i0;
+  input   [ 31:0]   dac_data_i0;
+  output            dac_enable_q0;
+  output            dac_valid_q0;
+  input   [ 31:0]   dac_data_q0;
+  output            dac_enable_i1;
+  output            dac_valid_i1;
+  input   [ 31:0]   dac_data_i1;
+  output            dac_enable_q1;
+  output            dac_valid_q1;
+  input   [ 31:0]   dac_data_q1;
+  input             dac_dovf;
+  input             dac_dunf;
+
+  // axi interface
+
+  input             s_axi_aclk;
+  input             s_axi_aresetn;
+  input             s_axi_awvalid;
+  input   [ 31:0]   s_axi_awaddr;
+  input   [  2:0]   s_axi_awprot;
+  output            s_axi_awready;
+  input             s_axi_wvalid;
+  input   [ 31:0]   s_axi_wdata;
+  input   [  3:0]   s_axi_wstrb;
+  output            s_axi_wready;
+  output            s_axi_bvalid;
+  output  [  1:0]   s_axi_bresp;
+  input             s_axi_bready;
+  input             s_axi_arvalid;
+  input   [ 31:0]   s_axi_araddr;
+  input   [  2:0]   s_axi_arprot;
+  output            s_axi_arready;
+  output            s_axi_rvalid;
+  output  [ 31:0]   s_axi_rdata;
+  output  [  1:0]   s_axi_rresp;
+  input             s_axi_rready;
+
+  // internal registers
+
+  reg               up_wack = 'd0;
+  reg               up_rack = 'd0;
+  reg     [ 31:0]   up_rdata = 'd0;
+
+  // internal signals
+
+  wire              up_clk;
+  wire              up_rstn;
+  wire    [ 63:0]   adc_data_s;
+  wire              adc_os_valid_s;
+  wire    [ 63:0]   adc_os_data_s;
+  wire    [127:0]   dac_data_s;
+  wire              up_wreq_s;
+  wire    [ 13:0]   up_waddr_s;
+  wire    [ 31:0]   up_wdata_s;
+  wire    [  2:0]   up_wack_s;
+  wire              up_rreq_s;
+  wire    [ 13:0]   up_raddr_s;
+  wire    [ 31:0]   up_rdata_s[0:2];
+  wire    [  2:0]   up_rack_s;
+
+  // signal name changes
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_wack <= | up_wack_s;
+      up_rack <= | up_rack_s;
+      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
+    end
+  end
+
+  // device interface
+
+  axi_ad9371_if i_if (
+    .adc_clk (adc_clk),
+    .adc_rx_data (adc_rx_data),
+    .adc_os_clk (adc_os_clk),
+    .adc_rx_os_data (adc_rx_os_data),
+    .adc_data (adc_data_s),
+    .adc_os_valid (adc_os_valid_s),
+    .adc_os_data (adc_os_data_s),
+    .dac_clk (dac_clk),
+    .dac_tx_data (dac_tx_data),
+    .dac_data (dac_data_s));
+
+  // receive
+
+  axi_ad9371_rx #(
+    .ID (ID),
+    .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
+  i_rx (
+    .adc_rst (adc_rst),
+    .adc_clk (adc_clk),
+    .adc_data (adc_data_s),
+    .adc_enable_i0 (adc_enable_i0),
+    .adc_valid_i0 (adc_valid_i0),
+    .adc_data_i0 (adc_data_i0),
+    .adc_enable_q0 (adc_enable_q0),
+    .adc_valid_q0 (adc_valid_q0),
+    .adc_data_q0 (adc_data_q0),
+    .adc_enable_i1 (adc_enable_i1),
+    .adc_valid_i1 (adc_valid_i1),
+    .adc_data_i1 (adc_data_i1),
+    .adc_enable_q1 (adc_enable_q1),
+    .adc_valid_q1 (adc_valid_q1),
+    .adc_data_q1 (adc_data_q1),
+    .adc_dovf (adc_dovf),
+    .adc_dunf (adc_dunf),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  // receive (o/s)
+
+  axi_ad9371_rx_os #(
+    .ID (ID),
+    .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
+  i_rx_os (
+    .adc_os_rst (adc_os_rst),
+    .adc_os_clk (adc_os_clk),
+    .adc_os_valid (adc_os_valid_s),
+    .adc_os_data (adc_os_data_s),
+    .adc_os_enable_i0 (adc_os_enable_i0),
+    .adc_os_valid_i0 (adc_os_valid_i0),
+    .adc_os_data_i0 (adc_os_data_i0),
+    .adc_os_enable_q0 (adc_os_enable_q0),
+    .adc_os_valid_q0 (adc_os_valid_q0),
+    .adc_os_data_q0 (adc_os_data_q0),
+    .adc_os_dovf (adc_os_dovf),
+    .adc_os_dunf (adc_os_dunf),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[1]),
+    .up_rack (up_rack_s[1]));
+
+  // transmit
+
+  axi_ad9371_tx #(
+    .ID (ID),
+    .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
+  i_tx (
+    .dac_rst (dac_rst),
+    .dac_clk (dac_clk),
+    .dac_data (dac_data_s),
+    .dac_sync_in (dac_sync_in),
+    .dac_sync_out (dac_sync_out),
+    .dac_enable_i0 (dac_enable_i0),
+    .dac_valid_i0 (dac_valid_i0),
+    .dac_data_i0 (dac_data_i0),
+    .dac_enable_q0 (dac_enable_q0),
+    .dac_valid_q0 (dac_valid_q0),
+    .dac_data_q0 (dac_data_q0),
+    .dac_enable_i1 (dac_enable_i1),
+    .dac_valid_i1 (dac_valid_i1),
+    .dac_data_i1 (dac_data_i1),
+    .dac_enable_q1 (dac_enable_q1),
+    .dac_valid_q1 (dac_valid_q1),
+    .dac_data_q1 (dac_data_q1),
+    .dac_dovf(dac_dovf),
+    .dac_dunf(dac_dunf),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[2]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[2]),
+    .up_rack (up_rack_s[2]));
+
+  // axi interface
+
+  up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9371/axi_ad9371_if.v b/library/axi_ad9371/axi_ad9371_if.v
new file mode 100644
index 000000000..df834e204
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371_if.v
@@ -0,0 +1,119 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9371_if (
+
+  // receive
+
+  adc_clk,
+  adc_rx_data,
+  adc_os_clk,
+  adc_rx_os_data,
+
+  adc_data,
+  adc_os_valid,
+  adc_os_data,
+
+  // transmit
+
+  dac_clk,
+  dac_tx_data,
+
+  dac_data);
+
+  // receive
+
+  input             adc_clk;
+  input   [ 63:0]   adc_rx_data;
+  input             adc_os_clk;
+  input   [ 63:0]   adc_rx_os_data;
+
+  output  [ 63:0]   adc_data;
+  output            adc_os_valid;
+  output  [ 63:0]   adc_os_data;
+
+  // transmit
+
+  input             dac_clk;
+  output  [127:0]   dac_tx_data;
+
+  input   [127:0]   dac_data;
+
+  // delineating
+
+  assign adc_data[((8* 7)+7):(8* 7)] = adc_rx_data[((8* 6)+7):(8* 6)];
+  assign adc_data[((8* 6)+7):(8* 6)] = adc_rx_data[((8* 7)+7):(8* 7)];
+  assign adc_data[((8* 5)+7):(8* 5)] = adc_rx_data[((8* 4)+7):(8* 4)];
+  assign adc_data[((8* 4)+7):(8* 4)] = adc_rx_data[((8* 5)+7):(8* 5)];
+  assign adc_data[((8* 3)+7):(8* 3)] = adc_rx_data[((8* 2)+7):(8* 2)];
+  assign adc_data[((8* 2)+7):(8* 2)] = adc_rx_data[((8* 3)+7):(8* 3)];
+  assign adc_data[((8* 1)+7):(8* 1)] = adc_rx_data[((8* 0)+7):(8* 0)];
+  assign adc_data[((8* 0)+7):(8* 0)] = adc_rx_data[((8* 1)+7):(8* 1)];
+
+  assign adc_os_valid = 'd1;
+  assign adc_os_data[((8* 7)+7):(8* 7)] = adc_rx_os_data[((8* 6)+7):(8* 6)];
+  assign adc_os_data[((8* 6)+7):(8* 6)] = adc_rx_os_data[((8* 7)+7):(8* 7)];
+  assign adc_os_data[((8* 5)+7):(8* 5)] = adc_rx_os_data[((8* 4)+7):(8* 4)];
+  assign adc_os_data[((8* 4)+7):(8* 4)] = adc_rx_os_data[((8* 5)+7):(8* 5)];
+  assign adc_os_data[((8* 3)+7):(8* 3)] = adc_rx_os_data[((8* 2)+7):(8* 2)];
+  assign adc_os_data[((8* 2)+7):(8* 2)] = adc_rx_os_data[((8* 3)+7):(8* 3)];
+  assign adc_os_data[((8* 1)+7):(8* 1)] = adc_rx_os_data[((8* 0)+7):(8* 0)];
+  assign adc_os_data[((8* 0)+7):(8* 0)] = adc_rx_os_data[((8* 1)+7):(8* 1)];
+
+  assign dac_tx_data[((8*15)+7):(8*15)] = dac_data[((8*14)+7):(8*14)];
+  assign dac_tx_data[((8*14)+7):(8*14)] = dac_data[((8*15)+7):(8*15)];
+  assign dac_tx_data[((8*13)+7):(8*13)] = dac_data[((8*12)+7):(8*12)];
+  assign dac_tx_data[((8*12)+7):(8*12)] = dac_data[((8*13)+7):(8*13)];
+  assign dac_tx_data[((8*11)+7):(8*11)] = dac_data[((8*10)+7):(8*10)];
+  assign dac_tx_data[((8*10)+7):(8*10)] = dac_data[((8*11)+7):(8*11)];
+  assign dac_tx_data[((8* 9)+7):(8* 9)] = dac_data[((8* 8)+7):(8* 8)];
+  assign dac_tx_data[((8* 8)+7):(8* 8)] = dac_data[((8* 9)+7):(8* 9)];
+  assign dac_tx_data[((8* 7)+7):(8* 7)] = dac_data[((8* 6)+7):(8* 6)];
+  assign dac_tx_data[((8* 6)+7):(8* 6)] = dac_data[((8* 7)+7):(8* 7)];
+  assign dac_tx_data[((8* 5)+7):(8* 5)] = dac_data[((8* 4)+7):(8* 4)];
+  assign dac_tx_data[((8* 4)+7):(8* 4)] = dac_data[((8* 5)+7):(8* 5)];
+  assign dac_tx_data[((8* 3)+7):(8* 3)] = dac_data[((8* 2)+7):(8* 2)];
+  assign dac_tx_data[((8* 2)+7):(8* 2)] = dac_data[((8* 3)+7):(8* 3)];
+  assign dac_tx_data[((8* 1)+7):(8* 1)] = dac_data[((8* 0)+7):(8* 0)];
+  assign dac_tx_data[((8* 0)+7):(8* 0)] = dac_data[((8* 1)+7):(8* 1)];
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9371/axi_ad9371_ip.tcl b/library/axi_ad9371/axi_ad9371_ip.tcl
new file mode 100755
index 000000000..dc67d418e
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371_ip.tcl
@@ -0,0 +1,43 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_ad9371
+adi_ip_files axi_ad9371 [list \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/common/ad_dds_sine.v" \
+  "$ad_hdl_dir/library/common/ad_dds_1.v" \
+  "$ad_hdl_dir/library/common/ad_dds.v" \
+  "$ad_hdl_dir/library/common/ad_datafmt.v" \
+  "$ad_hdl_dir/library/common/ad_dcfilter.v" \
+  "$ad_hdl_dir/library/common/ad_iqcor.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_xfer_status.v" \
+  "$ad_hdl_dir/library/common/up_clock_mon.v" \
+  "$ad_hdl_dir/library/common/up_adc_common.v" \
+  "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/up_dac_common.v" \
+  "$ad_hdl_dir/library/common/up_dac_channel.v" \
+  "axi_ad9371_if.v" \
+  "axi_ad9371_rx_channel.v" \
+  "axi_ad9371_rx.v" \
+  "axi_ad9371_rx_os.v" \
+  "axi_ad9371_tx_channel.v" \
+  "axi_ad9371_tx.v" \
+  "axi_ad9371.v" ]
+
+adi_ip_properties axi_ad9371
+
+adi_ip_constraints axi_jesd_gt [list \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
+
+set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
+
+ipx::save_core [ipx::current_core]
+
diff --git a/library/axi_ad9371/axi_ad9371_rx.v b/library/axi_ad9371/axi_ad9371_rx.v
new file mode 100644
index 000000000..55c7ce5c9
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371_rx.v
@@ -0,0 +1,344 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9371_rx (
+
+  // adc interface
+
+  adc_rst,
+  adc_clk,
+  adc_data,
+
+  // dma interface
+
+  adc_enable_i0,
+  adc_valid_i0,
+  adc_data_i0,
+  adc_enable_q0,
+  adc_valid_q0,
+  adc_data_q0,
+  adc_enable_i1,
+  adc_valid_i1,
+  adc_data_i1,
+  adc_enable_q1,
+  adc_valid_q1,
+  adc_data_q1,
+  adc_dovf,
+  adc_dunf,
+
+  // processor interface
+
+  up_rstn,
+  up_clk,
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack);
+
+  // parameters
+
+  parameter   DATAPATH_DISABLE = 0;
+  parameter   ID = 0;
+
+  // adc interface
+
+  output            adc_rst;
+  input             adc_clk;
+  input   [ 63:0]   adc_data;
+
+  // dma interface
+
+  output            adc_enable_i0;
+  output            adc_valid_i0;
+  output  [ 15:0]   adc_data_i0;
+  output            adc_enable_q0;
+  output            adc_valid_q0;
+  output  [ 15:0]   adc_data_q0;
+  output            adc_enable_i1;
+  output            adc_valid_i1;
+  output  [ 15:0]   adc_data_i1;
+  output            adc_enable_q1;
+  output            adc_valid_q1;
+  output  [ 15:0]   adc_data_q1;
+  input             adc_dovf;
+  input             adc_dunf;
+
+  // processor interface
+
+  input             up_rstn;
+  input             up_clk;
+  input             up_wreq;
+  input   [ 13:0]   up_waddr;
+  input   [ 31:0]   up_wdata;
+  output            up_wack;
+  input             up_rreq;
+  input   [ 13:0]   up_raddr;
+  output  [ 31:0]   up_rdata;
+  output            up_rack;
+
+  // internal registers
+
+  reg               up_status_pn_err = 'd0;
+  reg               up_status_pn_oos = 'd0;
+  reg               up_status_or = 'd0;
+  reg               up_wack = 'd0;
+  reg               up_rack = 'd0;
+  reg     [ 31:0]   up_rdata = 'd0;
+
+  // internal signals
+
+  wire    [ 15:0]   adc_data_iq_i0_s;
+  wire    [ 15:0]   adc_data_iq_q0_s;
+  wire    [ 15:0]   adc_data_iq_i1_s;
+  wire    [ 15:0]   adc_data_iq_q1_s;
+  wire    [  3:0]   up_adc_pn_err_s;
+  wire    [  3:0]   up_adc_pn_oos_s;
+  wire    [  3:0]   up_adc_or_s;
+  wire    [  4:0]   up_wack_s;
+  wire    [  4:0]   up_rack_s;
+  wire    [ 31:0]   up_rdata_s[0:4];
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_status_pn_err <= 'd0;
+      up_status_pn_oos <= 'd0;
+      up_status_or <= 'd0;
+      up_wack <= 'd0;
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_status_pn_err <= | up_adc_pn_err_s;
+      up_status_pn_oos <= | up_adc_pn_oos_s;
+      up_status_or <= | up_adc_or_s;
+      up_wack <= | up_wack_s;
+      up_rack <= | up_rack_s;
+      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
+    end
+  end
+
+  // channel width is 32 bits
+
+  assign adc_valid_i0 = 1'b1;
+  assign adc_valid_q0 = 1'b1;
+  assign adc_valid_i1 = 1'b1;
+  assign adc_valid_q1 = 1'b1;
+
+  // channel 0 (i)
+
+  axi_ad9371_rx_channel #(
+    .Q_OR_I_N (0),
+    .COMMON_ID ('h01),
+    .CHANNEL_ID (0),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE),
+    .DATA_WIDTH (16))
+  i_rx_channel_0 (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_valid_in (1'b1),
+    .adc_data_in (adc_data[15:0]),
+    .adc_valid_out (),
+    .adc_data_out (adc_data_i0),
+    .adc_data_iq_in (adc_data_iq_q0_s),
+    .adc_data_iq_out (adc_data_iq_i0_s),
+    .adc_enable (adc_enable_i0),
+    .up_adc_pn_err (up_adc_pn_err_s[0]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[0]),
+    .up_adc_or (up_adc_or_s[0]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  // channel 1 (q)
+
+  axi_ad9371_rx_channel #(
+    .Q_OR_I_N (1),
+    .COMMON_ID ('h01),
+    .CHANNEL_ID (1),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE),
+    .DATA_WIDTH (16))
+  i_rx_channel_1 (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_valid_in (1'b1),
+    .adc_data_in (adc_data[31:16]),
+    .adc_valid_out (),
+    .adc_data_out (adc_data_q0),
+    .adc_data_iq_in (adc_data_iq_i0_s),
+    .adc_data_iq_out (adc_data_iq_q0_s),
+    .adc_enable (adc_enable_q0),
+    .up_adc_pn_err (up_adc_pn_err_s[1]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[1]),
+    .up_adc_or (up_adc_or_s[1]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[1]),
+    .up_rack (up_rack_s[1]));
+
+  // channel 2 (i)
+
+  axi_ad9371_rx_channel #(
+    .Q_OR_I_N (0),
+    .COMMON_ID ('h01),
+    .CHANNEL_ID (2),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE),
+    .DATA_WIDTH (16))
+  i_rx_channel_2 (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_valid_in (1'b1),
+    .adc_data_in (adc_data[47:32]),
+    .adc_valid_out (),
+    .adc_data_out (adc_data_i1),
+    .adc_data_iq_in (adc_data_iq_q1_s),
+    .adc_data_iq_out (adc_data_iq_i1_s),
+    .adc_enable (adc_enable_i1),
+    .up_adc_pn_err (up_adc_pn_err_s[2]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[2]),
+    .up_adc_or (up_adc_or_s[2]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[2]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[2]),
+    .up_rack (up_rack_s[2]));
+
+  // channel 3 (q)
+
+  axi_ad9371_rx_channel #(
+    .Q_OR_I_N (1),
+    .COMMON_ID ('h01),
+    .CHANNEL_ID (3),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE),
+    .DATA_WIDTH (16))
+  i_rx_channel_3 (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_valid_in (1'b1),
+    .adc_data_in (adc_data[63:48]),
+    .adc_valid_out (),
+    .adc_data_out (adc_data_q1),
+    .adc_data_iq_in (adc_data_iq_i1_s),
+    .adc_data_iq_out (adc_data_iq_q1_s),
+    .adc_enable (adc_enable_q1),
+    .up_adc_pn_err (up_adc_pn_err_s[3]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[3]),
+    .up_adc_or (up_adc_or_s[3]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[3]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[3]),
+    .up_rack (up_rack_s[3]));
+
+  // common processor control
+
+  up_adc_common #(
+    .ADC_COMMON_ID ('h00),
+    .ID (ID))
+  i_up_adc_common (
+    .mmcm_rst (),
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_r1_mode (),
+    .adc_ddr_edgesel (),
+    .adc_pin_mode (),
+    .adc_status (1'b1),
+    .adc_sync_status (1'd0),
+    .adc_status_ovf (adc_dovf),
+    .adc_status_unf (adc_dunf),
+    .adc_clk_ratio (32'd1),
+    .adc_start_code (),
+    .adc_sync (),
+    .up_status_pn_err (up_status_pn_err),
+    .up_status_pn_oos (up_status_pn_oos),
+    .up_status_or (up_status_or),
+    .up_drp_sel (),
+    .up_drp_wr (),
+    .up_drp_addr (),
+    .up_drp_wdata (),
+    .up_drp_rdata (16'd0),
+    .up_drp_ready (1'd0),
+    .up_drp_locked (1'd1),
+    .up_usr_chanmax (),
+    .adc_usr_chanmax (8'd3),
+    .up_adc_gpio_in (32'd0),
+    .up_adc_gpio_out (),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[4]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[4]),
+    .up_rack (up_rack_s[4]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_ad9371/axi_ad9371_rx_channel.v b/library/axi_ad9371/axi_ad9371_rx_channel.v
new file mode 100644
index 000000000..9c47e188b
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371_rx_channel.v
@@ -0,0 +1,256 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9371_rx_channel (
+
+  // adc interface
+
+  adc_clk,
+  adc_rst,
+  adc_valid_in,
+  adc_data_in,
+  adc_valid_out,
+  adc_data_out,
+  adc_data_iq_in,
+  adc_data_iq_out,
+  adc_enable,
+
+  // channel interface
+
+  up_adc_pn_err,
+  up_adc_pn_oos,
+  up_adc_or,
+
+  // processor interface
+
+  up_rstn,
+  up_clk,
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack);
+
+  // parameters
+
+  parameter   Q_OR_I_N = 0;
+  parameter   COMMON_ID = 0;
+  parameter   CHANNEL_ID = 0;
+  parameter   DATAPATH_DISABLE = 0;
+  parameter   DATA_WIDTH = 32;
+
+  localparam  NUM_OF_SAMPLES = DATA_WIDTH/16;
+
+  // adc interface
+
+  input                           adc_clk;
+  input                           adc_rst;
+  input                           adc_valid_in;
+  input   [(DATA_WIDTH-1):0]      adc_data_in;
+  output                          adc_valid_out;
+  output  [(DATA_WIDTH-1):0]      adc_data_out;
+  input   [(DATA_WIDTH-1):0]      adc_data_iq_in;
+  output  [(DATA_WIDTH-1):0]      adc_data_iq_out;
+  output                          adc_enable;
+
+  // channel interface
+
+  output                          up_adc_pn_err;
+  output                          up_adc_pn_oos;
+  output                          up_adc_or;
+
+  // processor interface
+
+  input                           up_rstn;
+  input                           up_clk;
+  input                           up_wreq;
+  input   [13:0]                  up_waddr;
+  input   [31:0]                  up_wdata;
+  output                          up_wack;
+  input                           up_rreq;
+  input   [13:0]                  up_raddr;
+  output  [31:0]                  up_rdata;
+  output                          up_rack;
+
+  // internal signals
+
+  wire    [(NUM_OF_SAMPLES-1):0]  adc_dfmt_valid_s;
+  wire    [(DATA_WIDTH-1):0]      adc_dfmt_data_s;
+  wire    [(NUM_OF_SAMPLES-1):0]  adc_dcfilter_valid_s;
+  wire    [(DATA_WIDTH-1):0]      adc_dcfilter_data_s;
+  wire    [(NUM_OF_SAMPLES-1):0]  adc_valid_out_s;
+  wire                            adc_pn_err_s;
+  wire                            adc_pn_oos_s;
+  wire                            adc_dfmt_se_s;
+  wire                            adc_dfmt_type_s;
+  wire                            adc_dfmt_enable_s;
+  wire                            adc_dcfilt_enb_s;
+  wire    [15:0]                  adc_dcfilt_offset_s;
+  wire    [15:0]                  adc_dcfilt_coeff_s;
+  wire                            adc_iqcor_enb_s;
+  wire    [15:0]                  adc_iqcor_coeff_1_s;
+  wire    [15:0]                  adc_iqcor_coeff_2_s;
+
+  // variables
+
+  genvar                          n;
+
+  // iq correction inputs
+
+  assign adc_pn_oos_s = 1'b1;
+  assign adc_pn_err_s = 1'b0;
+
+  generate
+  for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_datafmt
+  if (DATAPATH_DISABLE == 1) begin
+  assign adc_dfmt_valid_s[n] = adc_valid_in;
+  assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in[((16*n)+15):(16*n)];
+  end else begin
+  ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt (
+    .clk (adc_clk),
+    .valid (adc_valid_in),
+    .data (adc_data_in[((16*n)+15):(16*n)]),
+    .valid_out (adc_dfmt_valid_s[n]),
+    .data_out (adc_dfmt_data_s[((16*n)+15):(16*n)]),
+    .dfmt_enable (adc_dfmt_enable_s),
+    .dfmt_type (adc_dfmt_type_s),
+    .dfmt_se (adc_dfmt_se_s));
+  end
+  end
+  endgenerate
+
+  generate
+  for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_dcfilter
+  if (DATAPATH_DISABLE == 1) begin
+  assign adc_dcfilter_valid_s[n] = adc_dfmt_valid_s[n];
+  assign adc_dcfilter_data_s[((16*n)+15):(16*n)] = adc_dfmt_data_s[((16*n)+15):(16*n)];
+  end else begin
+  ad_dcfilter i_ad_dcfilter (
+    .clk (adc_clk),
+    .valid (adc_dfmt_valid_s[n]),
+    .data (adc_dfmt_data_s[((16*n)+15):(16*n)]),
+    .valid_out (adc_dcfilter_valid_s[n]),
+    .data_out (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
+    .dcfilt_enb (adc_dcfilt_enb_s),
+    .dcfilt_coeff (adc_dcfilt_coeff_s),
+    .dcfilt_offset (adc_dcfilt_offset_s));
+  end
+  end
+  endgenerate
+
+  assign adc_valid_out = adc_valid_out_s[0];
+  assign adc_data_iq_out = adc_dcfilter_data_s;
+
+  generate
+  for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_iqcor
+  if (DATAPATH_DISABLE == 1) begin
+  assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n];
+  assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)];
+  end else begin
+  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
+    .clk (adc_clk),
+    .valid (adc_dcfilter_valid_s[n]),
+    .data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
+    .data_iq (adc_data_iq_in[((16*n)+15):(16*n)]),
+    .valid_out (adc_valid_out_s[n]),
+    .data_out (adc_data_out[((16*n)+15):(16*n)]),
+    .iqcor_enable (adc_iqcor_enb_s),
+    .iqcor_coeff_1 (adc_iqcor_coeff_1_s),
+    .iqcor_coeff_2 (adc_iqcor_coeff_2_s));
+  end
+  end
+  endgenerate
+
+  up_adc_channel #(
+    .ADC_COMMON_ID (COMMON_ID),
+    .ADC_CHANNEL_ID (CHANNEL_ID))
+  i_up_adc_channel (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_enable (adc_enable),
+    .adc_iqcor_enb (adc_iqcor_enb_s),
+    .adc_dcfilt_enb (adc_dcfilt_enb_s),
+    .adc_dfmt_se (adc_dfmt_se_s),
+    .adc_dfmt_type (adc_dfmt_type_s),
+    .adc_dfmt_enable (adc_dfmt_enable_s),
+    .adc_dcfilt_offset (adc_dcfilt_offset_s),
+    .adc_dcfilt_coeff (adc_dcfilt_coeff_s),
+    .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
+    .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
+    .adc_pnseq_sel (),
+    .adc_data_sel (),
+    .adc_pn_err (adc_pn_err_s),
+    .adc_pn_oos (adc_pn_oos_s),
+    .adc_or (1'd0),
+    .up_adc_pn_err (up_adc_pn_err),
+    .up_adc_pn_oos (up_adc_pn_oos),
+    .up_adc_or (up_adc_or),
+    .up_usr_datatype_be (),
+    .up_usr_datatype_signed (),
+    .up_usr_datatype_shift (),
+    .up_usr_datatype_total_bits (),
+    .up_usr_datatype_bits (),
+    .up_usr_decimation_m (),
+    .up_usr_decimation_n (),
+    .adc_usr_datatype_be (1'b0),
+    .adc_usr_datatype_signed (1'b1),
+    .adc_usr_datatype_shift (8'd0),
+    .adc_usr_datatype_total_bits (8'd16),
+    .adc_usr_datatype_bits (8'd16),
+    .adc_usr_decimation_m (16'd1),
+    .adc_usr_decimation_n (16'd1),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_ad9371/axi_ad9371_rx_os.v b/library/axi_ad9371/axi_ad9371_rx_os.v
new file mode 100644
index 000000000..ec839738f
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371_rx_os.v
@@ -0,0 +1,261 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9371_rx_os (
+
+  // adc interface
+
+  adc_os_rst,
+  adc_os_clk,
+  adc_os_valid,
+  adc_os_data,
+
+  // dma interface
+
+  adc_os_enable_i0,
+  adc_os_valid_i0,
+  adc_os_data_i0,
+  adc_os_enable_q0,
+  adc_os_valid_q0,
+  adc_os_data_q0,
+  adc_os_dovf,
+  adc_os_dunf,
+
+  // processor interface
+
+  up_rstn,
+  up_clk,
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack);
+
+  // parameters
+
+  parameter   DATAPATH_DISABLE = 0;
+  parameter   ID = 0;
+
+  // adc interface
+
+  output            adc_os_rst;
+  input             adc_os_clk;
+  input             adc_os_valid;
+  input   [ 63:0]   adc_os_data;
+
+  // dma interface
+
+  output            adc_os_enable_i0;
+  output            adc_os_valid_i0;
+  output  [ 31:0]   adc_os_data_i0;
+  output            adc_os_enable_q0;
+  output            adc_os_valid_q0;
+  output  [ 31:0]   adc_os_data_q0;
+  input             adc_os_dovf;
+  input             adc_os_dunf;
+
+  // processor interface
+
+  input             up_rstn;
+  input             up_clk;
+  input             up_wreq;
+  input   [ 13:0]   up_waddr;
+  input   [ 31:0]   up_wdata;
+  output            up_wack;
+  input             up_rreq;
+  input   [ 13:0]   up_raddr;
+  output  [ 31:0]   up_rdata;
+  output            up_rack;
+
+  // internal registers
+
+  reg               up_status_pn_err = 'd0;
+  reg               up_status_pn_oos = 'd0;
+  reg               up_status_or = 'd0;
+  reg               up_wack = 'd0;
+  reg               up_rack = 'd0;
+  reg     [ 31:0]   up_rdata = 'd0;
+
+  // internal signals
+
+  wire    [ 31:0]   adc_os_data_iq_i0_s;
+  wire    [ 31:0]   adc_os_data_iq_q0_s;
+  wire    [  1:0]   up_adc_pn_err_s;
+  wire    [  1:0]   up_adc_pn_oos_s;
+  wire    [  1:0]   up_adc_or_s;
+  wire    [  2:0]   up_wack_s;
+  wire    [  2:0]   up_rack_s;
+  wire    [ 31:0]   up_rdata_s[0:2];
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_status_pn_err <= 'd0;
+      up_status_pn_oos <= 'd0;
+      up_status_or <= 'd0;
+      up_wack <= 'd0;
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_status_pn_err <= | up_adc_pn_err_s;
+      up_status_pn_oos <= | up_adc_pn_oos_s;
+      up_status_or <= | up_adc_or_s;
+      up_wack <= | up_wack_s;
+      up_rack <= | up_rack_s;
+      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
+    end
+  end
+
+  // channel o/s (i)
+
+  axi_ad9371_rx_channel #(
+    .Q_OR_I_N (0),
+    .COMMON_ID ('h21),
+    .CHANNEL_ID (0),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE),
+    .DATA_WIDTH (32))
+  i_rx_os_channel_0 (
+    .adc_clk (adc_os_clk),
+    .adc_rst (adc_os_rst),
+    .adc_valid_in (adc_os_valid),
+    .adc_data_in (adc_os_data[31:0]),
+    .adc_valid_out (adc_os_valid_i0),
+    .adc_data_out (adc_os_data_i0),
+    .adc_data_iq_in (adc_os_data_iq_q0_s),
+    .adc_data_iq_out (adc_os_data_iq_i0_s),
+    .adc_enable (adc_os_enable_i0),
+    .up_adc_pn_err (up_adc_pn_err_s[0]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[0]),
+    .up_adc_or (up_adc_or_s[0]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  // channel o/s (q)
+
+  axi_ad9371_rx_channel #(
+    .Q_OR_I_N (1),
+    .COMMON_ID ('h21),
+    .CHANNEL_ID (1),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE),
+    .DATA_WIDTH (32))
+  i_rx_os_channel_1 (
+    .adc_clk (adc_os_clk),
+    .adc_rst (adc_os_rst),
+    .adc_valid_in (adc_os_valid),
+    .adc_data_in (adc_os_data[63:32]),
+    .adc_valid_out (adc_os_valid_q0),
+    .adc_data_out (adc_os_data_q0),
+    .adc_data_iq_in (adc_os_data_iq_i0_s),
+    .adc_data_iq_out (adc_os_data_iq_q0_s),
+    .adc_enable (adc_os_enable_q0),
+    .up_adc_pn_err (up_adc_pn_err_s[1]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[1]),
+    .up_adc_or (up_adc_or_s[1]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[1]),
+    .up_rack (up_rack_s[1]));
+
+  // common processor control
+
+  up_adc_common #(
+    .ADC_COMMON_ID ('h20),
+    .ID (ID))
+  i_up_adc_common (
+    .mmcm_rst (),
+    .adc_clk (adc_os_clk),
+    .adc_rst (adc_os_rst),
+    .adc_r1_mode (),
+    .adc_ddr_edgesel (),
+    .adc_pin_mode (),
+    .adc_status (1'b1),
+    .adc_sync_status (1'd0),
+    .adc_status_ovf (adc_os_dovf),
+    .adc_status_unf (adc_os_dunf),
+    .adc_clk_ratio (32'd1),
+    .adc_start_code (),
+    .adc_sync (),
+    .up_status_pn_err (up_status_pn_err),
+    .up_status_pn_oos (up_status_pn_oos),
+    .up_status_or (up_status_or),
+    .up_drp_sel (),
+    .up_drp_wr (),
+    .up_drp_addr (),
+    .up_drp_wdata (),
+    .up_drp_rdata (16'd0),
+    .up_drp_ready (1'd0),
+    .up_drp_locked (1'd1),
+    .up_usr_chanmax (),
+    .adc_usr_chanmax (8'd3),
+    .up_adc_gpio_in (32'd0),
+    .up_adc_gpio_out (),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[2]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[2]),
+    .up_rack (up_rack_s[2]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v
new file mode 100644
index 000000000..4bd197b48
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371_tx.v
@@ -0,0 +1,329 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9371_tx (
+
+  // dac interface
+
+  dac_rst,
+  dac_clk,
+  dac_data,
+  
+  // master/slave
+
+  dac_sync_in,
+  dac_sync_out,
+
+  // dma interface
+
+  dac_enable_i0,
+  dac_valid_i0,
+  dac_data_i0,
+  dac_enable_q0,
+  dac_valid_q0,
+  dac_data_q0,
+  dac_enable_i1,
+  dac_valid_i1,
+  dac_data_i1,
+  dac_enable_q1,
+  dac_valid_q1,
+  dac_data_q1,
+  dac_dovf,
+  dac_dunf,
+
+  // processor interface
+
+  up_rstn,
+  up_clk,
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack);
+
+  // parameters
+
+  parameter   DATAPATH_DISABLE = 0;
+  parameter   ID = 0;
+
+  // dac interface
+
+  output            dac_rst;
+  input             dac_clk;
+  output  [127:0]   dac_data;
+  
+  // master/slave
+
+  input             dac_sync_in;
+  output            dac_sync_out;
+
+  // dma interface
+
+  output            dac_enable_i0;
+  output            dac_valid_i0;
+  input   [ 31:0]   dac_data_i0;
+  output            dac_enable_q0;
+  output            dac_valid_q0;
+  input   [ 31:0]   dac_data_q0;
+  output            dac_enable_i1;
+  output            dac_valid_i1;
+  input   [ 31:0]   dac_data_i1;
+  output            dac_enable_q1;
+  output            dac_valid_q1;
+  input   [ 31:0]   dac_data_q1;
+  input             dac_dovf;
+  input             dac_dunf;
+
+  // processor interface
+
+  input             up_rstn;
+  input             up_clk;
+  input             up_wreq;
+  input   [ 13:0]   up_waddr;
+  input   [ 31:0]   up_wdata;
+  output            up_wack;
+  input             up_rreq;
+  input   [ 13:0]   up_raddr;
+  output  [ 31:0]   up_rdata;
+  output            up_rack;
+
+  // internal registers
+
+  reg               dac_data_sync = 'd0;
+  reg               up_wack = 'd0;
+  reg               up_rack = 'd0;
+  reg     [ 31:0]   up_rdata = 'd0;
+
+  // internal signals
+
+  wire              dac_data_sync_s;
+  wire    [ 31:0]   dac_data_iq_i0_s;
+  wire    [ 31:0]   dac_data_iq_q0_s;
+  wire    [ 31:0]   dac_data_iq_i1_s;
+  wire    [ 31:0]   dac_data_iq_q1_s;
+  wire              dac_dds_format_s;
+  wire    [  4:0]   up_wack_s;
+  wire    [  4:0]   up_rack_s;
+  wire    [ 31:0]   up_rdata_s[0:4];
+
+  // master/slave
+
+  assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
+
+  always @(posedge dac_clk) begin
+    dac_data_sync <= dac_data_sync_s;
+  end
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_wack <= | up_wack_s;
+      up_rack <= | up_rack_s;
+      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
+        up_rdata_s[3] | up_rdata_s[4];
+    end
+  end
+
+  // dac channel
+
+  assign dac_valid_i0 = 1'b1;
+  
+  axi_ad9371_tx_channel #(
+    .CHANNEL_ID (0),
+    .Q_OR_I_N (0),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+  i_tx_channel_0 (
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_data_in (dac_data_i0),
+    .dac_data_out (dac_data[31:0]),
+    .dac_data_iq_in (dac_data_iq_q0_s),
+    .dac_data_iq_out (dac_data_iq_i0_s),
+    .dac_enable (dac_enable_i0),
+    .dac_data_sync (dac_data_sync),
+    .dac_dds_format (dac_dds_format_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  // dac channel
+  
+  assign dac_valid_q0 = 1'b1;
+
+  axi_ad9371_tx_channel #(
+    .CHANNEL_ID (1),
+    .Q_OR_I_N (1),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+  i_tx_channel_1 (
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_data_in (dac_data_q0),
+    .dac_data_out (dac_data[63:32]),
+    .dac_data_iq_in (dac_data_iq_i0_s),
+    .dac_data_iq_out (dac_data_iq_q0_s),
+    .dac_enable (dac_enable_q0),
+    .dac_data_sync (dac_data_sync),
+    .dac_dds_format (dac_dds_format_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[1]),
+    .up_rack (up_rack_s[1]));
+
+  // dac channel
+  
+  assign dac_valid_i1 = 1'b1;
+
+  axi_ad9371_tx_channel #(
+    .CHANNEL_ID (2),
+    .Q_OR_I_N (0),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+  i_tx_channel_2 (
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_data_in (dac_data_i1),
+    .dac_data_out (dac_data[95:64]),
+    .dac_data_iq_in (dac_data_iq_q1_s),
+    .dac_data_iq_out (dac_data_iq_i1_s),
+    .dac_enable (dac_enable_i1),
+    .dac_data_sync (dac_data_sync),
+    .dac_dds_format (dac_dds_format_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[2]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[2]),
+    .up_rack (up_rack_s[2]));
+
+  // dac channel
+  
+  assign dac_valid_q1 = 1'b1;
+
+  axi_ad9371_tx_channel #(
+    .CHANNEL_ID (3),
+    .Q_OR_I_N (1),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+  i_tx_channel_3 (
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_data_in (dac_data_q1),
+    .dac_data_out (dac_data[127:96]),
+    .dac_data_iq_in (dac_data_iq_i1_s),
+    .dac_data_iq_out (dac_data_iq_q1_s),
+    .dac_enable (dac_enable_q1),
+    .dac_data_sync (dac_data_sync),
+    .dac_dds_format (dac_dds_format_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[3]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[3]),
+    .up_rack (up_rack_s[3]));
+
+  // dac common processor interface
+
+  up_dac_common #(.ID (ID)) i_up_dac_common (
+    .mmcm_rst (),
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_sync (dac_sync_out),
+    .dac_frame (),
+    .dac_par_type (),
+    .dac_par_enb (),
+    .dac_r1_mode (),
+    .dac_datafmt (dac_dds_format_s),
+    .dac_datarate (),
+    .dac_status (1'b1),
+    .dac_status_ovf (dac_dovf),
+    .dac_status_unf (dac_dunf),
+    .dac_clk_ratio (32'd1),
+    .up_drp_sel (),
+    .up_drp_wr (),
+    .up_drp_addr (),
+    .up_drp_wdata (),
+    .up_drp_rdata (16'd0),
+    .up_drp_ready (1'd0),
+    .up_drp_locked (1'd1),
+    .up_usr_chanmax (),
+    .dac_usr_chanmax (8'd3),
+    .up_dac_gpio_in (32'd0),
+    .up_dac_gpio_out (),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[4]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[4]),
+    .up_rack (up_rack_s[4]));
+  
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9371/axi_ad9371_tx_channel.v b/library/axi_ad9371/axi_ad9371_tx_channel.v
new file mode 100644
index 000000000..6dc5f100d
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371_tx_channel.v
@@ -0,0 +1,283 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9371_tx_channel (
+
+  // dac interface
+
+  dac_clk,
+  dac_rst,
+  dac_data_in,
+  dac_data_out,
+  dac_data_iq_in,
+  dac_data_iq_out,
+
+  // processor interface
+
+  dac_enable,
+  dac_data_sync,
+  dac_dds_format,
+
+  // bus interface
+
+  up_rstn,
+  up_clk,
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack);
+
+  // parameters
+
+  parameter   CHANNEL_ID = 32'h0;
+  parameter   Q_OR_I_N = 0;
+  parameter   DATAPATH_DISABLE = 0;
+
+  // dac interface
+
+  input           dac_clk;
+  input           dac_rst;
+  input   [31:0]  dac_data_in;
+  output  [31:0]  dac_data_out;
+  input   [31:0]  dac_data_iq_in;
+  output  [31:0]  dac_data_iq_out;
+
+  // processor interface
+
+  output          dac_enable;
+  input           dac_data_sync;
+  input           dac_dds_format;
+
+  // bus interface
+
+  input           up_rstn;
+  input           up_clk;
+  input           up_wreq;
+  input   [13:0]  up_waddr;
+  input   [31:0]  up_wdata;
+  output          up_wack;
+  input           up_rreq;
+  input   [13:0]  up_raddr;
+  output  [31:0]  up_rdata;
+  output          up_rack;
+
+  // internal registers
+
+  reg             dac_enable = 'd0;
+  reg     [31:0]  dac_data_iq_out = 'd0;
+  reg     [31:0]  dac_pat_data = 'd0;
+  reg     [15:0]  dac_dds_phase_0_0 = 'd0;
+  reg     [15:0]  dac_dds_phase_0_1 = 'd0;
+  reg     [15:0]  dac_dds_phase_1_0 = 'd0;
+  reg     [15:0]  dac_dds_phase_1_1 = 'd0;
+  reg     [15:0]  dac_dds_incr_0 = 'd0;
+  reg     [15:0]  dac_dds_incr_1 = 'd0;
+  reg     [31:0]  dac_dds_data = 'd0;
+
+  // internal signals
+
+  wire    [15:0]  dac_dds_data_0_s;
+  wire    [15:0]  dac_dds_data_1_s;
+  wire    [15:0]  dac_dds_scale_1_s;
+  wire    [15:0]  dac_dds_init_1_s;
+  wire    [15:0]  dac_dds_incr_1_s;
+  wire    [15:0]  dac_dds_scale_2_s;
+  wire    [15:0]  dac_dds_init_2_s;
+  wire    [15:0]  dac_dds_incr_2_s;
+  wire    [15:0]  dac_pat_data_1_s;
+  wire    [15:0]  dac_pat_data_2_s;
+  wire    [ 3:0]  dac_data_sel_s;
+  wire            dac_iqcor_enb_s;
+  wire    [15:0]  dac_iqcor_coeff_1_s;
+  wire    [15:0]  dac_iqcor_coeff_2_s;
+
+  // dac iq correction
+
+  generate
+  if (DATAPATH_DISABLE == 1) begin
+
+  assign dac_data_out = dac_data_iq_out;
+
+  end else begin
+
+  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_1 (
+    .clk (dac_clk),
+    .valid (1'b1),
+    .data_in (dac_data_iq_out[31:16]),
+    .data_iq (dac_data_iq_in[31:16]),
+    .valid_out (),
+    .data_out (dac_data_out[31:16]),
+    .iqcor_enable (dac_iqcor_enb_s),
+    .iqcor_coeff_1 (dac_iqcor_coeff_1_s),
+    .iqcor_coeff_2 (dac_iqcor_coeff_2_s));
+
+  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_0 (
+    .clk (dac_clk),
+    .valid (1'b1),
+    .data_in (dac_data_iq_out[15:0]),
+    .data_iq (dac_data_iq_in[15:0]),
+    .valid_out (),
+    .data_out (dac_data_out[15:0]),
+    .iqcor_enable (dac_iqcor_enb_s),
+    .iqcor_coeff_1 (dac_iqcor_coeff_1_s),
+    .iqcor_coeff_2 (dac_iqcor_coeff_2_s));
+  end
+  endgenerate
+
+  // dac mux
+
+  always @(posedge dac_clk) begin
+    dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
+    case (dac_data_sel_s)
+      4'h3: dac_data_iq_out <= 32'd0;
+      4'h2: dac_data_iq_out <= dac_data_in;
+      4'h1: dac_data_iq_out <= dac_pat_data;
+      default: dac_data_iq_out <= dac_dds_data;
+    endcase
+  end
+
+  // pattern
+
+  always @(posedge dac_clk) begin
+    dac_pat_data <= {dac_pat_data_2_s, dac_pat_data_1_s};
+  end
+
+  // dds
+
+  always @(posedge dac_clk) begin
+    if (dac_data_sync == 1'b1) begin
+      dac_dds_phase_0_0 <= dac_dds_init_1_s;
+      dac_dds_phase_0_1 <= dac_dds_init_2_s;
+      dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
+      dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
+      dac_dds_incr_0 <= {dac_dds_incr_1_s[14:0], 1'd0};
+      dac_dds_incr_1 <= {dac_dds_incr_2_s[14:0], 1'd0};
+      dac_dds_data <= 32'd0;
+    end else begin
+      dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
+      dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
+      dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
+      dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
+      dac_dds_incr_0 <= dac_dds_incr_0;
+      dac_dds_incr_1 <= dac_dds_incr_1;
+      dac_dds_data <= {dac_dds_data_1_s, dac_dds_data_0_s};
+    end
+  end
+
+  // dds
+
+  generate
+  if (DATAPATH_DISABLE == 1) begin
+
+  assign dac_dds_data_0_s = 16'd0;
+  assign dac_dds_data_1_s = 16'd0;
+
+  end else begin
+
+  ad_dds i_dds_0 (
+    .clk (dac_clk),
+    .dds_format (dac_dds_format),
+    .dds_phase_0 (dac_dds_phase_0_0),
+    .dds_scale_0 (dac_dds_scale_1_s),
+    .dds_phase_1 (dac_dds_phase_0_1),
+    .dds_scale_1 (dac_dds_scale_2_s),
+    .dds_data (dac_dds_data_0_s));
+
+  ad_dds i_dds_1 (
+    .clk (dac_clk),
+    .dds_format (dac_dds_format),
+    .dds_phase_0 (dac_dds_phase_1_0),
+    .dds_scale_0 (dac_dds_scale_1_s),
+    .dds_phase_1 (dac_dds_phase_1_1),
+    .dds_scale_1 (dac_dds_scale_2_s),
+    .dds_data (dac_dds_data_1_s));
+
+  end
+  endgenerate
+
+  // single channel processor
+
+  up_dac_channel #(.DAC_CHANNEL_ID (CHANNEL_ID)) i_up_dac_channel (
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_dds_scale_1 (dac_dds_scale_1_s),
+    .dac_dds_init_1 (dac_dds_init_1_s),
+    .dac_dds_incr_1 (dac_dds_incr_1_s),
+    .dac_dds_scale_2 (dac_dds_scale_2_s),
+    .dac_dds_init_2 (dac_dds_init_2_s),
+    .dac_dds_incr_2 (dac_dds_incr_2_s),
+    .dac_pat_data_1 (dac_pat_data_1_s),
+    .dac_pat_data_2 (dac_pat_data_2_s),
+    .dac_data_sel (dac_data_sel_s),
+    .dac_iqcor_enb (dac_iqcor_enb_s),
+    .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
+    .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
+    .up_usr_datatype_be (),
+    .up_usr_datatype_signed (),
+    .up_usr_datatype_shift (),
+    .up_usr_datatype_total_bits (),
+    .up_usr_datatype_bits (),
+    .up_usr_interpolation_m (),
+    .up_usr_interpolation_n (),
+    .dac_usr_datatype_be (1'b0),
+    .dac_usr_datatype_signed (1'b1),
+    .dac_usr_datatype_shift (8'd0),
+    .dac_usr_datatype_total_bits (8'd16),
+    .dac_usr_datatype_bits (8'd16),
+    .dac_usr_interpolation_m (16'd1),
+    .dac_usr_interpolation_n (16'd1),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+  
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From f92e8509bb30537a116700c4ff5e0daf7f1dde1a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 20 May 2016 11:46:25 -0400
Subject: [PATCH 223/972] adrv9371x- added

---
 projects/adrv9371x/a10soc/Makefile           | 142 ++++++
 projects/adrv9371x/a10soc/system_bd.qsys     | 500 +++++++++++++++++++
 projects/adrv9371x/a10soc/system_constr.sdc  |   7 +
 projects/adrv9371x/a10soc/system_project.tcl | 137 +++++
 projects/adrv9371x/a10soc/system_top.v       | 264 ++++++++++
 projects/adrv9371x/common/adrv9371x_bd.tcl   | 433 ++++++++++++++++
 projects/adrv9371x/zc706/system_bd.tcl       |   5 +
 projects/adrv9371x/zc706/system_constr.xdc   |  80 +++
 projects/adrv9371x/zc706/system_project.tcl  |  20 +
 projects/adrv9371x/zc706/system_top.v        | 389 +++++++++++++++
 10 files changed, 1977 insertions(+)
 create mode 100644 projects/adrv9371x/a10soc/Makefile
 create mode 100755 projects/adrv9371x/a10soc/system_bd.qsys
 create mode 100644 projects/adrv9371x/a10soc/system_constr.sdc
 create mode 100644 projects/adrv9371x/a10soc/system_project.tcl
 create mode 100644 projects/adrv9371x/a10soc/system_top.v
 create mode 100644 projects/adrv9371x/common/adrv9371x_bd.tcl
 create mode 100644 projects/adrv9371x/zc706/system_bd.tcl
 create mode 100644 projects/adrv9371x/zc706/system_constr.xdc
 create mode 100644 projects/adrv9371x/zc706/system_project.tcl
 create mode 100644 projects/adrv9371x/zc706/system_top.v

diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
new file mode 100644
index 000000000..ed286a1c4
--- /dev/null
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -0,0 +1,142 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.sdc
+M_DEPS += system_bd.qsys
+M_DEPS += ../common/fmcomms2_bd.qsys
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
+M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_addsub.v
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dcfilter.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_iqcor.v
+M_DEPS += ../../../library/common/ad_mul.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_tdd_control.v
+M_DEPS += ../../../library/common/altera/DSP48E1.v
+M_DEPS += ../../../library/common/altera/MULT_MACRO.v
+M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
+M_DEPS += ../../../library/common/altera/ad_cmos_in.v
+M_DEPS += ../../../library/common/altera/ad_cmos_out.v
+M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
+M_DEPS += ../../../library/common/altera/ad_lvds_in.v
+M_DEPS += ../../../library/common/altera/ad_lvds_out.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_tdd_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+
+
+M_ALTERA := quartus_sh --64bit -t 
+
+
+M_FLIST += *.log
+M_FLIST += *_INFO.txt
+M_FLIST += *_dump.txt
+M_FLIST += db
+M_FLIST += *.asm.rpt
+M_FLIST += *.done
+M_FLIST += *.eda.rpt
+M_FLIST += *.fit.*
+M_FLIST += *.map.*
+M_FLIST += *.sta.*
+M_FLIST += *.qsf
+M_FLIST += *.qpf
+M_FLIST += *.qws
+M_FLIST += *.sof
+M_FLIST += *.cdf
+M_FLIST += *.sld
+M_FLIST += *.qdf
+M_FLIST += hc_output
+M_FLIST += system_bd
+M_FLIST += hps_isw_handoff
+M_FLIST += hps_sdram_*.csv
+M_FLIST += *ddr3_*.csv
+M_FLIST += incremental_db
+M_FLIST += reconfig_mif
+M_FLIST += *.sopcinfo
+M_FLIST +=  *.jdi
+M_FLIST += *.pin
+
+
+
+.PHONY: all clean clean-all
+all: fmcomms2_a10soc.sof
+
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+fmcomms2_a10soc.sof: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_ALTERA) system_project.tcl  >> fmcomms2_a10soc_quartus.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/projects/adrv9371x/a10soc/system_bd.qsys b/projects/adrv9371x/a10soc/system_bd.qsys
new file mode 100755
index 000000000..72d7386ca
--- /dev/null
+++ b/projects/adrv9371x/a10soc/system_bd.qsys
@@ -0,0 +1,500 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element a10soc
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element a10soc.hps_s1_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element fmcomms2
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element fmcomms2.axi_ad9361_s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element fmcomms2.axi_dmac_adc_s_axi
+   {
+      datum baseAddress
+      {
+         value = "81920";
+         type = "String";
+      }
+   }
+   element fmcomms2.axi_dmac_dac_s_axi
+   {
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="10AS066N3F40E2SGE2" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="fmcomms2_a10soc.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="ad9361_if"
+   internal="fmcomms2.axi_ad9361_device_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="delay_clk"
+   internal="fmcomms2.axi_ad9361_delay_clk"
+   type="clock"
+   dir="end" />
+ <interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
+ <interface
+   name="hps_ddr_oct"
+   internal="a10soc.hps_ddr_oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hps_ddr_ref_clk"
+   internal="a10soc.hps_ddr_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface name="hps_gpio" internal="a10soc.hps_gpio" type="conduit" dir="end" />
+ <interface name="hps_io" internal="a10soc.hps_io" type="conduit" dir="end" />
+ <interface name="hps_spi0" internal="a10soc.hps_spi0" type="conduit" dir="end" />
+ <interface
+   name="hps_spi0_sclk"
+   internal="a10soc.hps_spi0_sclk"
+   type="clock"
+   dir="start" />
+ <interface name="hps_spi1" internal="a10soc.hps_spi1" type="conduit" dir="end" />
+ <interface
+   name="hps_spi1_sclk"
+   internal="a10soc.hps_spi1_sclk"
+   type="clock"
+   dir="start" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="sys_reset"
+   internal="sys_clk.clk_in_reset"
+   type="reset"
+   dir="end" />
+ <interface
+   name="up_enable"
+   internal="fmcomms2.axi_ad9361_up_enable"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="up_txnrx"
+   internal="fmcomms2.axi_ad9361_up_txnrx"
+   type="conduit"
+   dir="end" />
+ <module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="2" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="2" />
+  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
+  <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
+  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
+ </module>
+ <module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 32" />
+  <parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 32" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
+  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
+ </module>
+ <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="fmcomms2.axi_dmac_adc_m_dest_axi"
+   end="a10soc.hps_s1_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="fmcomms2.axi_dmac_dac_m_src_axi"
+   end="a10soc.hps_s1_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="fmcomms2.axi_ad9361_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="fmcomms2.axi_dmac_adc_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00014000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="fmcomms2.axi_dmac_dac_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.clk"
+   end="fmcomms2.sys_clk" />
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10soc.hps_irq0"
+   end="fmcomms2.axi_dmac_adc_intr">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10soc.hps_irq0"
+   end="fmcomms2.axi_dmac_dac_intr">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10soc.hps_irq1"
+   end="fmcomms2.axi_dmac_adc_intr">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10soc.hps_irq1"
+   end="fmcomms2.axi_dmac_dac_intr">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_clk.clk_reset"
+   end="a10soc.sys_rst_in" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="a10soc.sys_rst"
+   end="fmcomms2.sys_rst" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+</system>
diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc
new file mode 100644
index 000000000..1f9b3d462
--- /dev/null
+++ b/projects/adrv9371x/a10soc/system_constr.sdc
@@ -0,0 +1,7 @@
+
+create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
+create_clock -period  "4.000 ns"  -name rx_clk_250mhz       [get_ports {rx_clk_in}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
diff --git a/projects/adrv9371x/a10soc/system_project.tcl b/projects/adrv9371x/a10soc/system_project.tcl
new file mode 100644
index 000000000..1dceee79f
--- /dev/null
+++ b/projects/adrv9371x/a10soc/system_project.tcl
@@ -0,0 +1,137 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new fmcomms2_a10soc -overwrite
+
+source "../../common/a10soc/a10soc_system_assign.tcl"
+
+set_global_assignment -name QSYS_FILE system_bd.qsys
+set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name SDC_FILE system_constr.sdc
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
+
+# ad9371
+
+set_location_assignment PIN_N29   -to ref_clk0              ; ## D04  FMC_HPC_GBTCLK0_M2C_P (NC)
+set_location_assignment PIN_N28   -to "ref_clk0(n)"         ; ## D05  FMC_HPC_GBTCLK0_M2C_N (NC)
+set_location_assignment PIN_R29   -to ref_clk1              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_location_assignment PIN_R28   -to "ref_clk1(n)"         ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_location_assignment PIN_R32   -to rx_data[0]            ; ## A02  FMC_HPC_DP1_M2C_P
+set_location_assignment PIN_R33   -to "rx_data[0](n)"       ; ## A03  FMC_HPC_DP1_M2C_N
+set_location_assignment PIN_P34   -to rx_data[1]            ; ## A06  FMC_HPC_DP2_M2C_P
+set_location_assignment PIN_P35   -to "rx_data[1](n)"       ; ## A07  FMC_HPC_DP2_M2C_N
+set_location_assignment PIN_T30   -to rx_data[2]            ; ## C06  FMC_HPC_DP0_M2C_P
+set_location_assignment PIN_T31   -to "rx_data[2](n)"       ; ## C07  FMC_HPC_DP0_M2C_N
+set_location_assignment PIN_P30   -to rx_data[3]            ; ## A10  FMC_HPC_DP3_M2C_P
+set_location_assignment PIN_P31   -to "rx_data[3](n)"       ; ## A11  FMC_HPC_DP3_M2C_N
+set_location_assignment PIN_M38   -to tx_data[0]            ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[3])
+set_location_assignment PIN_M39   -to "tx_data[0](n)"       ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[3])
+set_location_assignment PIN_L36   -to tx_data[1]            ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[0])
+set_location_assignment PIN_L37   -to "tx_data[1](n)"       ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[0])
+set_location_assignment PIN_N36   -to tx_data[2]            ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[1])
+set_location_assignment PIN_N37   -to "tx_data[2](n)"       ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[1])
+set_location_assignment PIN_K38   -to tx_data[3]            ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[2])
+set_location_assignment PIN_K39   -to "tx_data[3](n)"       ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[2])
+
+set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0
+set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
+
+set_location_assignment PIN_C14   -to rx_sync               ; ## G09  FMC_HPC_LA03_P
+set_location_assignment PIN_D14   -to rx_sync(n)            ; ## G10  FMC_HPC_LA03_N
+set_location_assignment PIN_E3    -to rx_os_sync            ; ## G27  FMC_HPC_LA25_P (Sniffer)
+set_location_assignment PIN_F3    -to rx_os_sync(n)         ; ## G28  FMC_HPC_LA25_N (Sniffer)
+set_location_assignment PIN_C13   -to tx_sync               ; ## H07  FMC_HPC_LA02_P
+set_location_assignment PIN_D13   -to tx_sync(n)            ; ## H08  FMC_HPC_LA02_N
+set_location_assignment PIN_P11   -to sysref                ; ## G36  FMC_HPC_LA33_P
+set_location_assignment PIN_R11   -to sysref(n)             ; ## G37  FMC_HPC_LA33_N
+
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync
+set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to sysref
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref
+
+set_location_assignment PIN_A12   -to spi_csn_ad9528        ; ## D15  FMC_HPC_LA09_N
+set_location_assignment PIN_A13   -to spi_csn_ad9371        ; ## D14  FMC_HPC_LA09_P
+set_location_assignment PIN_A9    -to spi_clk               ; ## H13  FMC_HPC_LA07_P
+set_location_assignment PIN_B9    -to spi_mosi              ; ## H14  FMC_HPC_LA07_N
+set_location_assignment PIN_B11   -to spi_miso              ; ## G12  FMC_HPC_LA08_P
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528        
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9371        
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk               
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi              
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso              
+
+set_location_assignment PIN_F2    -to ad9528_reset_b        ; ## D26  FMC_HPC_LA26_P
+set_location_assignment PIN_G2    -to ad9528_sysref_req     ; ## D27  FMC_HPC_LA26_N
+set_location_assignment PIN_J11   -to ad9371_tx1_enable     ; ## D17  FMC_HPC_LA13_P
+set_location_assignment PIN_J9    -to ad9371_tx2_enable     ; ## C18  FMC_HPC_LA14_P
+set_location_assignment PIN_K11   -to ad9371_rx1_enable     ; ## D18  FMC_HPC_LA13_N
+set_location_assignment PIN_J10   -to ad9371_rx2_enable     ; ## C19  FMC_HPC_LA14_N
+set_location_assignment PIN_F13   -to ad9371_test           ; ## D11  FMC_HPC_LA05_P (DNI/NC) 
+set_location_assignment PIN_H12   -to ad9371_reset_b        ; ## H10  FMC_HPC_LA04_P
+set_location_assignment PIN_H13   -to ad9371_gpint          ; ## H11  FMC_HPC_LA04_N
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b        
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req     
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx1_enable     
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx2_enable     
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx1_enable     
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx2_enable     
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_test           
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_reset_b        
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpint          
+
+set_location_assignment PIN_D4    -to ad9371_gpio_00        ; ## H19  FMC_HPC_LA15_P          
+set_location_assignment PIN_D5    -to ad9371_gpio_01        ; ## H20  FMC_HPC_LA15_N          
+set_location_assignment PIN_D6    -to ad9371_gpio_02        ; ## G18  FMC_HPC_LA16_P          
+set_location_assignment PIN_E6    -to ad9371_gpio_03        ; ## G19  FMC_HPC_LA16_N          
+set_location_assignment PIN_C2    -to ad9371_gpio_04        ; ## H25  FMC_HPC_LA21_P          
+set_location_assignment PIN_D3    -to ad9371_gpio_05        ; ## H26  FMC_HPC_LA21_N          
+set_location_assignment PIN_G7    -to ad9371_gpio_06        ; ## C22  FMC_HPC_LA18_CC_P       
+set_location_assignment PIN_H7    -to ad9371_gpio_07        ; ## C23  FMC_HPC_LA18_CC_N       
+set_location_assignment PIN_F4    -to ad9371_gpio_15        ; ## G24  FMC_HPC_LA22_P     (LVDS Pairs?)    
+set_location_assignment PIN_G4    -to ad9371_gpio_08        ; ## G25  FMC_HPC_LA22_N     (LVDS Pairs?)    
+set_location_assignment PIN_G5    -to ad9371_gpio_09        ; ## H22  FMC_HPC_LA19_P     (LVDS Pairs?)    
+set_location_assignment PIN_G6    -to ad9371_gpio_10        ; ## H23  FMC_HPC_LA19_N     (LVDS Pairs?)    
+set_location_assignment PIN_C3    -to ad9371_gpio_11        ; ## G21  FMC_HPC_LA20_P     (LVDS Pairs?)    
+set_location_assignment PIN_C4    -to ad9371_gpio_12        ; ## G22  FMC_HPC_LA20_N     (LVDS Pairs?)    
+set_location_assignment PIN_N9    -to ad9371_gpio_14        ; ## G30  FMC_HPC_LA29_P     (LVDS Pairs?)    
+set_location_assignment PIN_P10   -to ad9371_gpio_13        ; ## G31  FMC_HPC_LA29_N     (LVDS Pairs?)    
+set_location_assignment PIN_M12   -to ad9371_gpio_17        ; ## G15  FMC_HPC_LA12_P     (LVDS Pairs?)
+set_location_assignment PIN_N13   -to ad9371_gpio_16        ; ## G16  FMC_HPC_LA12_N     (LVDS Pairs?)
+set_location_assignment PIN_F14   -to ad9371_gpio_18        ; ## D12  FMC_HPC_LA05_N          
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_00
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_01
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_02
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_03
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_04
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_05
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_06
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_07
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_15
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_08
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_09
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_10
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_11
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_12
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_14
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_13
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_17
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_16
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_18
+
+execute_flow -compile
+
diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v
new file mode 100644
index 000000000..e4211a457
--- /dev/null
+++ b/projects/adrv9371x/a10soc/system_top.v
@@ -0,0 +1,264 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  input             sys_clk,
+  input             sys_resetn,
+
+  // hps-ddr4 (32)
+
+  input             hps_ddr_ref_clk,
+  output  [  0:0]   hps_ddr_clk_p,
+  output  [  0:0]   hps_ddr_clk_n,
+  output  [ 16:0]   hsp_ddr_a,
+  output  [  1:0]   hps_ddr_ba,
+  output  [  0:0]   hps_ddr_bg,
+  output  [  0:0]   hps_ddr_cke,
+  output  [  0:0]   hps_ddr_cs_n,
+  output  [  0:0]   hps_ddr_odt,
+  output  [  0:0]   hps_ddr_reset_n,
+  output  [  0:0]   hps_ddr_act_n,
+  output  [  0:0]   hps_ddr_par,
+  input   [  0:0]   hps_ddr_alert_n,
+  inout   [  3:0]   hps_ddr_dqs_p,
+  inout   [  3:0]   hps_ddr_dqs_n,
+  inout   [ 31:0]   hps_ddr_dq,
+  inout   [  3:0]   hps_ddr_dbi_n,
+  input             hps_ddr_rzq,
+
+  // hps-ethernet
+
+  input   [  0:0]   hps_eth_rxclk,
+  input   [  0:0]   hps_eth_rxctl,
+  input   [  3:0]   hps_eth_rxd,
+  output  [  0:0]   hps_eth_txclk,
+  output  [  0:0]   hps_eth_txctl,
+  output  [  3:0]   hps_eth_txd,
+  output  [  0:0]   hps_eth_mdc,
+  inout   [  0:0]   hps_eth_mdio,
+
+  // hps-sdio
+
+  output  [  0:0]   hps_sdio_clk,
+  inout   [  0:0]   hps_sdio_cmd,
+  inout   [  7:0]   hps_sdio_d,
+
+  // hps-usb
+
+  input   [  0:0]   hps_usb_clk,
+  input   [  0:0]   hps_usb_dir,
+  input   [  0:0]   hps_usb_nxt,
+  output  [  0:0]   hps_usb_stp,
+  inout   [  7:0]   hps_usb_d,
+
+  // hps-uart
+
+  input   [  0:0]   hps_uart_rx,
+  output  [  0:0]   hps_uart_tx,
+
+  // hps-i2c (shared w fmc-a, fmc-b)
+
+  inout   [  0:0]   hps_i2c_sda,
+  inout   [  0:0]   hps_i2c_scl,
+
+  // hps-gpio (max-v-u16)
+
+  inout   [  3:0]   hps_gpio,
+          
+  // gpio (max-v-u21)
+
+  input   [  7:0]   gpio_bd_i,
+  output  [  3:0]   gpio_bd_o,
+
+  // ad9361-interface
+
+  input             rx_clk_in,
+  input             rx_frame_in,
+  input   [  5:0]   rx_data_in,
+  output            tx_clk_out,
+  output            tx_frame_out,
+  output  [  5:0]   tx_data_out,
+  output            enable,
+  output            txnrx,
+
+  output            gpio_resetb,
+  output            gpio_sync,
+  output            gpio_en_agc,
+  output  [  3:0]   gpio_ctl,
+  input   [  7:0]   gpio_status,
+
+  output            spi_csn,
+  output            spi_clk,
+  output            spi_mosi,
+  input             spi_miso);
+
+  // internal signals
+
+  wire    [ 31:0]   gpio_i;
+  wire    [ 31:0]   gpio_o;
+
+  // gpio (ad9361)
+
+  assign gpio_i[31:24] = gpio_o[31:24];
+  assign gpio_i[23:16] = gpio_status;
+
+  assign gpio_resetb = gpio_o[22];
+  assign gpio_sync = gpio_o[21];
+  assign gpio_en_agc = gpio_o[20];
+  assign gpio_ctl = gpio_o[19:16];
+
+  // gpio (max-v-u21)
+
+  assign gpio_i[15:8] = gpio_o[15:8];
+  assign gpio_i[ 7:0] = gpio_bd_i;
+
+  assign gpio_bd_o = gpio_o[3:0];
+
+  // instantiations
+
+  system_bd i_system_bd (
+    .ad9361_if_rx_clk_in_p (rx_clk_in),
+    .ad9361_if_rx_clk_in_n (1'b0),
+    .ad9361_if_rx_frame_in_p (rx_frame_in),
+    .ad9361_if_rx_frame_in_n (1'b0),
+    .ad9361_if_rx_data_in_p (rx_data_in),
+    .ad9361_if_rx_data_in_n (6'd0),
+    .ad9361_if_tx_clk_out_p (tx_clk_out),
+    .ad9361_if_tx_clk_out_n (),
+    .ad9361_if_tx_frame_out_p (tx_frame_out),
+    .ad9361_if_tx_frame_out_n (),
+    .ad9361_if_tx_data_out_p (tx_data_out),
+    .ad9361_if_tx_data_out_n (),
+    .ad9361_if_enable (enable),
+    .ad9361_if_txnrx (txnrx),
+    .delay_clk_clk (1'b0),
+    .hps_ddr_mem_ck (hps_ddr_clk_p),
+    .hps_ddr_mem_ck_n (hps_ddr_clk_n),
+    .hps_ddr_mem_a (hsp_ddr_a),
+    .hps_ddr_mem_act_n (hps_ddr_act_n),
+    .hps_ddr_mem_ba (hps_ddr_ba),
+    .hps_ddr_mem_bg (hps_ddr_bg),
+    .hps_ddr_mem_cke (hps_ddr_cke),
+    .hps_ddr_mem_cs_n (hps_ddr_cs_n),
+    .hps_ddr_mem_odt (hps_ddr_odt),
+    .hps_ddr_mem_reset_n (hps_ddr_reset_n),
+    .hps_ddr_mem_par (hps_ddr_par),
+    .hps_ddr_mem_alert_n (hps_ddr_alert_n),
+    .hps_ddr_mem_dqs (hps_ddr_dqs_p),
+    .hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
+    .hps_ddr_mem_dq (hps_ddr_dq),
+    .hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
+    .hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
+    .hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
+    .hps_gpio_gp_in (gpio_i),
+    .hps_gpio_gp_out (gpio_o),
+    .hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
+    .hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
+    .hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
+    .hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
+    .hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
+    .hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
+    .hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
+    .hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
+    .hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
+    .hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
+    .hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
+    .hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
+    .hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
+    .hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
+    .hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
+    .hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
+    .hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
+    .hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
+    .hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
+    .hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
+    .hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
+    .hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
+    .hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
+    .hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
+    .hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
+    .hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
+    .hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
+    .hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
+    .hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
+    .hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
+    .hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
+    .hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
+    .hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
+    .hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
+    .hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
+    .hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
+    .hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
+    .hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
+    .hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
+    .hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
+    .hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
+    .hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
+    .hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
+    .hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
+    .hps_spi0_mosi_o (spi_mosi),
+    .hps_spi0_miso_i (spi_miso),
+    .hps_spi0_ss_in_n (1'b1),
+    .hps_spi0_mosi_oe (),
+    .hps_spi0_ss0_n_o (spi_csn),
+    .hps_spi0_ss1_n_o (),
+    .hps_spi0_ss2_n_o (),
+    .hps_spi0_ss3_n_o (),
+    .hps_spi0_sclk_clk (spi_clk),
+    .hps_spi1_mosi_o (),
+    .hps_spi1_miso_i (1'b0),
+    .hps_spi1_ss_in_n (1'b1),
+    .hps_spi1_mosi_oe (),
+    .hps_spi1_ss0_n_o (),
+    .hps_spi1_ss1_n_o (),
+    .hps_spi1_ss2_n_o (),
+    .hps_spi1_ss3_n_o (),
+    .hps_spi1_sclk_clk (),
+    .sys_clk_clk (sys_clk),
+    .sys_reset_reset_n (sys_resetn),
+    .up_enable_up_enable (gpio_o[23]),
+    .up_txnrx_up_txnrx (gpio_o[24]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
new file mode 100644
index 000000000..46c7f6920
--- /dev/null
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -0,0 +1,433 @@
+
+# ad9371
+
+create_bd_port -dir I rx_ref_clk
+create_bd_port -dir I rx_sysref
+create_bd_port -dir I -from 1 -to 0 rx_p
+create_bd_port -dir I -from 1 -to 0 rx_n
+create_bd_port -dir O rx_sync
+create_bd_port -dir I -from 1 -to 0 rx_os_p
+create_bd_port -dir I -from 1 -to 0 rx_os_n
+create_bd_port -dir O rx_os_sync
+
+create_bd_port -dir I tx_ref_clk
+create_bd_port -dir I tx_sysref
+create_bd_port -dir O -from 3 -to 0 tx_p
+create_bd_port -dir O -from 3 -to 0 tx_n
+create_bd_port -dir I tx_sync
+
+create_bd_port -dir I dac_fifo_bypass
+
+# dma clock
+
+set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150}] $sys_ps7
+
+set sys_dma_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_dma_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_dma_rstgen
+
+ad_connect  sys_dma_clk sys_ps7/FCLK_CLK2
+ad_connect  sys_dma_reset sys_dma_rstgen/peripheral_reset
+ad_connect  sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
+ad_connect  sys_dma_clk sys_dma_rstgen/slowest_sync_clk
+ad_connect  sys_dma_rstgen/ext_reset_in sys_ps7/FCLK_RESET2_N
+
+# dac peripherals
+
+set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_tx_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9371_tx_dma
+
+p_sys_dacfifo [current_bd_instance .] axi_ad9371_tx_fifo 128 17
+
+set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
+
+set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_tx_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9371_tx_jesd
+set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9371_tx_jesd
+
+# adc peripherals
+
+set axi_ad9371_rx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_rx_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_jesd
+set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_jesd
+
+set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_rx_os_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_os_jesd
+set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_os_jesd
+
+set axi_ad9371_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_dma
+
+set axi_ad9371_rx_os_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_os_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_os_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_os_dma
+
+set util_ad9371_rx_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_cpack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9371_rx_cpack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_rx_cpack
+
+set util_ad9371_rx_os_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_os_cpack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_rx_os_cpack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9371_rx_os_cpack
+
+# ad9371 gt & core
+
+set axi_ad9371_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9371:1.0 axi_ad9371_core]
+
+set axi_ad9371_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9371_gt]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9371_gt
+set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_ad9371_gt
+set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9371_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_0 {5}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_0 {5}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_0 {3}] $axi_ad9371_gt
+set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9371_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_1 {5}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {0}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_1 {5}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {0}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_1 {0}] $axi_ad9371_gt
+set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9371_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_2 {5}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_2 {5}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {0}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9371_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_3 {5}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {0}] $axi_ad9371_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_3 {5}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {0}] $axi_ad9371_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_ad9371_gt
+
+set util_ad9371_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9371_gt]
+set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_ad9371_gt
+set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9371_gt
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_ad9371_gt
+set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9371_gt
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad9371_gt
+set_property -dict [list CONFIG.TX_ENABLE {1}] $util_ad9371_gt
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_ad9371_gt
+
+set util_ad9371_os_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9371_os_gt]
+set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9371_os_gt
+set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9371_os_gt
+set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad9371_os_gt
+set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9371_os_gt
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad9371_os_gt
+set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9371_os_gt
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {2}] $util_ad9371_os_gt
+
+# ad9371 data path clocks
+
+set axi_tx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_tx_clkgen]
+set_property -dict [list CONFIG.ID {2}] $axi_tx_clkgen
+set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_tx_clkgen
+set_property -dict [list CONFIG.VCO_DIV {1}] $axi_tx_clkgen
+set_property -dict [list CONFIG.VCO_MUL {8}] $axi_tx_clkgen
+set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_tx_clkgen
+
+set axi_rx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_rx_clkgen]
+set_property -dict [list CONFIG.ID {2}] $axi_rx_clkgen
+set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_rx_clkgen
+set_property -dict [list CONFIG.VCO_DIV {1}] $axi_rx_clkgen
+set_property -dict [list CONFIG.VCO_MUL {8}] $axi_rx_clkgen
+set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_rx_clkgen
+
+set axi_rx_os_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_rx_os_clkgen]
+set_property -dict [list CONFIG.ID {2}] $axi_rx_os_clkgen
+set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_rx_os_clkgen
+set_property -dict [list CONFIG.VCO_DIV {1}] $axi_rx_os_clkgen
+set_property -dict [list CONFIG.VCO_MUL {8}] $axi_rx_os_clkgen
+set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_rx_os_clkgen
+
+# connections (gt)
+
+ad_connect  util_ad9371_gt/qpll_ref_clk rx_ref_clk
+ad_connect  util_ad9371_gt/cpll_ref_clk tx_ref_clk
+ad_connect  util_ad9371_os_gt/qpll_ref_clk rx_ref_clk
+ad_connect  util_ad9371_os_gt/cpll_ref_clk tx_ref_clk
+
+ad_connect  axi_ad9371_gt/gt_qpll_0 util_ad9371_gt/gt_qpll_0
+ad_connect  axi_ad9371_gt/gt_pll_0 util_ad9371_gt/gt_pll_0
+ad_connect  axi_ad9371_gt/gt_pll_1 util_ad9371_gt/gt_pll_1
+ad_connect  axi_ad9371_gt/gt_pll_2 util_ad9371_gt/gt_pll_2
+ad_connect  axi_ad9371_gt/gt_pll_3 util_ad9371_gt/gt_pll_3
+ad_connect  axi_ad9371_gt/gt_rx_0 util_ad9371_gt/gt_rx_0
+ad_connect  axi_ad9371_gt/gt_rx_1 util_ad9371_gt/gt_rx_1
+ad_connect  axi_ad9371_gt/gt_rx_ip_0 axi_ad9371_rx_jesd/gt0_rx
+ad_connect  axi_ad9371_gt/gt_rx_ip_1 axi_ad9371_rx_jesd/gt1_rx
+ad_connect  axi_ad9371_gt/rx_gt_comma_align_enb_0 axi_ad9371_rx_jesd/rxencommaalign_out
+ad_connect  axi_ad9371_gt/rx_gt_comma_align_enb_1 axi_ad9371_rx_jesd/rxencommaalign_out
+ad_connect  axi_ad9371_gt/gt_rx_2 util_ad9371_os_gt/gt_rx_0
+ad_connect  axi_ad9371_gt/gt_rx_3 util_ad9371_os_gt/gt_rx_1
+ad_connect  axi_ad9371_gt/gt_rx_ip_2 axi_ad9371_rx_os_jesd/gt0_rx
+ad_connect  axi_ad9371_gt/gt_rx_ip_3 axi_ad9371_rx_os_jesd/gt1_rx
+ad_connect  axi_ad9371_gt/rx_gt_comma_align_enb_2 axi_ad9371_rx_os_jesd/rxencommaalign_out
+ad_connect  axi_ad9371_gt/rx_gt_comma_align_enb_3 axi_ad9371_rx_os_jesd/rxencommaalign_out
+ad_connect  axi_ad9371_gt/gt_tx_0 util_ad9371_gt/gt_tx_0
+ad_connect  axi_ad9371_gt/gt_tx_1 util_ad9371_gt/gt_tx_1
+ad_connect  axi_ad9371_gt/gt_tx_2 util_ad9371_gt/gt_tx_2
+ad_connect  axi_ad9371_gt/gt_tx_3 util_ad9371_gt/gt_tx_3
+ad_connect  axi_ad9371_gt/gt_tx_ip_0 axi_ad9371_tx_jesd/gt0_tx
+ad_connect  axi_ad9371_gt/gt_tx_ip_1 axi_ad9371_tx_jesd/gt1_tx
+ad_connect  axi_ad9371_gt/gt_tx_ip_2 axi_ad9371_tx_jesd/gt2_tx
+ad_connect  axi_ad9371_gt/gt_tx_ip_3 axi_ad9371_tx_jesd/gt3_tx
+
+# connections (dac)
+
+ad_connect  util_ad9371_gt/tx_sysref tx_sysref
+ad_connect  util_ad9371_gt/tx_p tx_p
+ad_connect  util_ad9371_gt/tx_n tx_n
+ad_connect  util_ad9371_gt/tx_sync tx_sync
+ad_connect  util_ad9371_gt/tx_out_clk axi_tx_clkgen/clk
+ad_connect  axi_tx_clkgen/clk_0 util_ad9371_gt/tx_clk
+ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk
+ad_connect  util_ad9371_gt/tx_ip_rst axi_ad9371_tx_jesd/tx_reset
+ad_connect  util_ad9371_gt/tx_ip_rst_done axi_ad9371_tx_jesd/tx_reset_done
+ad_connect  util_ad9371_gt/tx_ip_sysref axi_ad9371_tx_jesd/tx_sysref
+ad_connect  util_ad9371_gt/tx_ip_sync axi_ad9371_tx_jesd/tx_sync
+ad_connect  util_ad9371_gt/tx_ip_data axi_ad9371_tx_jesd/tx_tdata
+ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_core/dac_clk
+ad_connect  util_ad9371_gt/tx_data axi_ad9371_core/dac_tx_data
+ad_connect  axi_tx_clkgen/clk_0 util_ad9371_tx_upack/dac_clk
+ad_connect  axi_ad9371_core/dac_valid_i0 util_ad9371_tx_upack/dac_valid_0
+ad_connect  axi_ad9371_core/dac_enable_i0 util_ad9371_tx_upack/dac_enable_0
+ad_connect  axi_ad9371_core/dac_data_i0 util_ad9371_tx_upack/dac_data_0
+ad_connect  axi_ad9371_core/dac_valid_q0 util_ad9371_tx_upack/dac_valid_1
+ad_connect  axi_ad9371_core/dac_enable_q0 util_ad9371_tx_upack/dac_enable_1
+ad_connect  axi_ad9371_core/dac_data_q0 util_ad9371_tx_upack/dac_data_1
+ad_connect  axi_ad9371_core/dac_valid_i1 util_ad9371_tx_upack/dac_valid_2
+ad_connect  axi_ad9371_core/dac_enable_i1 util_ad9371_tx_upack/dac_enable_2
+ad_connect  axi_ad9371_core/dac_data_i1 util_ad9371_tx_upack/dac_data_2
+ad_connect  axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
+ad_connect  axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
+ad_connect  axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
+ad_connect  util_ad9371_tx_upack/dma_xfer_in axi_ad9371_tx_fifo/dac_xfer_out
+ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_fifo/dac_clk
+ad_connect  util_ad9371_tx_upack/dac_valid axi_ad9371_tx_fifo/dac_valid
+ad_connect  util_ad9371_tx_upack/dac_data axi_ad9371_tx_fifo/dac_data
+ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_fifo/dma_clk
+ad_connect  util_ad9371_gt/tx_rst axi_ad9371_tx_fifo/dma_rst
+ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_dma/m_axis_aclk
+ad_connect  sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
+ad_connect  axi_ad9371_tx_fifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
+ad_connect  axi_ad9371_tx_fifo/dma_ready axi_ad9371_tx_dma/m_axis_ready
+ad_connect  axi_ad9371_tx_fifo/dma_data axi_ad9371_tx_dma/m_axis_data
+ad_connect  axi_ad9371_tx_fifo/dma_valid axi_ad9371_tx_dma/m_axis_valid
+ad_connect  axi_ad9371_tx_fifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
+
+# connections (adc)
+
+ad_connect  util_ad9371_gt/rx_sysref rx_sysref
+ad_connect  util_ad9371_gt/rx_p rx_p
+ad_connect  util_ad9371_gt/rx_n rx_n
+ad_connect  util_ad9371_gt/rx_sync rx_sync
+ad_connect  util_ad9371_os_gt/rx_p rx_os_p
+ad_connect  util_ad9371_os_gt/rx_n rx_os_n
+ad_connect  util_ad9371_os_gt/rx_sysref rx_sysref
+ad_connect  util_ad9371_os_gt/rx_sync rx_os_sync
+ad_connect  util_ad9371_gt/rx_out_clk axi_rx_clkgen/clk
+ad_connect  axi_rx_clkgen/clk_0 util_ad9371_gt/rx_clk
+ad_connect  axi_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk
+ad_connect  util_ad9371_gt/rx_ip_rst axi_ad9371_rx_jesd/rx_reset
+ad_connect  util_ad9371_gt/rx_ip_rst_done axi_ad9371_rx_jesd/rx_reset_done
+ad_connect  util_ad9371_gt/rx_ip_sysref axi_ad9371_rx_jesd/rx_sysref
+ad_connect  util_ad9371_gt/rx_ip_sync axi_ad9371_rx_jesd/rx_sync
+ad_connect  util_ad9371_gt/rx_ip_sof axi_ad9371_rx_jesd/rx_start_of_frame
+ad_connect  util_ad9371_gt/rx_ip_data axi_ad9371_rx_jesd/rx_tdata
+ad_connect  util_ad9371_os_gt/rx_out_clk axi_rx_os_clkgen/clk
+ad_connect  axi_rx_os_clkgen/clk_0 util_ad9371_os_gt/rx_clk
+ad_connect  axi_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk
+ad_connect  util_ad9371_os_gt/rx_ip_rst axi_ad9371_rx_os_jesd/rx_reset
+ad_connect  util_ad9371_os_gt/rx_ip_rst_done axi_ad9371_rx_os_jesd/rx_reset_done
+ad_connect  util_ad9371_os_gt/rx_ip_sysref axi_ad9371_rx_os_jesd/rx_sysref
+ad_connect  util_ad9371_os_gt/rx_ip_sync axi_ad9371_rx_os_jesd/rx_sync
+ad_connect  util_ad9371_os_gt/rx_ip_sof axi_ad9371_rx_jesd/rx_start_of_frame
+ad_connect  util_ad9371_os_gt/rx_ip_data axi_ad9371_rx_os_jesd/rx_tdata
+ad_connect  axi_rx_clkgen/clk_0 axi_ad9371_core/adc_clk
+ad_connect  util_ad9371_gt/rx_data axi_ad9371_core/adc_rx_data
+ad_connect  axi_rx_os_clkgen/clk_0 axi_ad9371_core/adc_os_clk
+ad_connect  util_ad9371_os_gt/rx_data axi_ad9371_core/adc_rx_os_data
+ad_connect  axi_rx_clkgen/clk_0 util_ad9371_rx_cpack/adc_clk
+ad_connect  util_ad9371_gt/rx_rst util_ad9371_rx_cpack/adc_rst
+ad_connect  axi_ad9371_core/adc_enable_i0 util_ad9371_rx_cpack/adc_enable_0
+ad_connect  axi_ad9371_core/adc_valid_i0 util_ad9371_rx_cpack/adc_valid_0
+ad_connect  axi_ad9371_core/adc_data_i0 util_ad9371_rx_cpack/adc_data_0
+ad_connect  axi_ad9371_core/adc_enable_q0 util_ad9371_rx_cpack/adc_enable_1
+ad_connect  axi_ad9371_core/adc_valid_q0 util_ad9371_rx_cpack/adc_valid_1
+ad_connect  axi_ad9371_core/adc_data_q0 util_ad9371_rx_cpack/adc_data_1
+ad_connect  axi_ad9371_core/adc_enable_i1 util_ad9371_rx_cpack/adc_enable_2
+ad_connect  axi_ad9371_core/adc_valid_i1 util_ad9371_rx_cpack/adc_valid_2
+ad_connect  axi_ad9371_core/adc_data_i1 util_ad9371_rx_cpack/adc_data_2
+ad_connect  axi_ad9371_core/adc_enable_q1 util_ad9371_rx_cpack/adc_enable_3
+ad_connect  axi_ad9371_core/adc_valid_q1 util_ad9371_rx_cpack/adc_valid_3
+ad_connect  axi_ad9371_core/adc_data_q1 util_ad9371_rx_cpack/adc_data_3
+ad_connect  axi_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk
+ad_connect  sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn
+ad_connect  util_ad9371_rx_cpack/adc_valid axi_ad9371_rx_dma/fifo_wr_en
+ad_connect  util_ad9371_rx_cpack/adc_sync axi_ad9371_rx_dma/fifo_wr_sync
+ad_connect  util_ad9371_rx_cpack/adc_data axi_ad9371_rx_dma/fifo_wr_din
+ad_connect  axi_ad9371_rx_dma/fifo_wr_overflow axi_ad9371_core/adc_dovf
+ad_connect  axi_rx_os_clkgen/clk_0 util_ad9371_rx_os_cpack/adc_clk
+ad_connect  util_ad9371_os_gt/rx_rst util_ad9371_rx_os_cpack/adc_rst
+ad_connect  axi_ad9371_core/adc_os_enable_i0 util_ad9371_rx_os_cpack/adc_enable_0
+ad_connect  axi_ad9371_core/adc_os_valid_i0 util_ad9371_rx_os_cpack/adc_valid_0
+ad_connect  axi_ad9371_core/adc_os_data_i0 util_ad9371_rx_os_cpack/adc_data_0
+ad_connect  axi_ad9371_core/adc_os_enable_q0 util_ad9371_rx_os_cpack/adc_enable_1
+ad_connect  axi_ad9371_core/adc_os_valid_q0 util_ad9371_rx_os_cpack/adc_valid_1
+ad_connect  axi_ad9371_core/adc_os_data_q0 util_ad9371_rx_os_cpack/adc_data_1
+ad_connect  axi_rx_os_clkgen/clk_0 axi_ad9371_rx_os_dma/fifo_wr_clk
+ad_connect  sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn
+ad_connect  util_ad9371_rx_os_cpack/adc_valid axi_ad9371_rx_os_dma/fifo_wr_en
+ad_connect  util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync
+ad_connect  util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din
+ad_connect  axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf
+ad_connect  axi_ad9371_tx_fifo/dac_fifo_bypass dac_fifo_bypass
+
+# interconnect (cpu)
+
+ad_cpu_interconnect 0x44A60000 axi_ad9371_gt
+ad_cpu_interconnect 0x44A00000 axi_ad9371_core
+ad_cpu_interconnect 0x43C00000 axi_tx_clkgen
+ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd
+ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma
+ad_cpu_interconnect 0x43C10000 axi_rx_clkgen
+ad_cpu_interconnect 0x43C20000 axi_rx_os_clkgen
+ad_cpu_interconnect 0x44A91000 axi_ad9371_rx_jesd
+ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd
+ad_cpu_interconnect 0x7c400000 axi_ad9371_rx_dma
+ad_cpu_interconnect 0x7c440000 axi_ad9371_rx_os_dma
+
+# gt uses hp0, and 100MHz clock for both DRP and AXI4
+
+ad_mem_hp0_interconnect sys_cpu_clk axi_ad9371_gt/m_axi
+
+# interconnect (mem/dac)
+
+ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_dma_clk axi_ad9371_tx_dma/m_src_axi
+ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_dma/m_dest_axi
+ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_os_dma/m_dest_axi
+
+ad_disconnect sys_cpu_resetn axi_hp1_interconnect/ARESETN
+ad_disconnect sys_cpu_resetn axi_hp1_interconnect/M00_ARESETN
+ad_disconnect sys_cpu_resetn axi_hp1_interconnect/S00_ARESETN
+ad_disconnect sys_cpu_resetn axi_hp2_interconnect/ARESETN
+ad_disconnect sys_cpu_resetn axi_hp2_interconnect/M00_ARESETN
+ad_disconnect sys_cpu_resetn axi_hp2_interconnect/S00_ARESETN
+ad_disconnect sys_cpu_resetn axi_hp2_interconnect/S01_ARESETN
+
+ad_connect  sys_dma_resetn axi_hp1_interconnect/ARESETN
+ad_connect  sys_dma_resetn axi_hp1_interconnect/M00_ARESETN
+ad_connect  sys_dma_resetn axi_hp1_interconnect/S00_ARESETN
+ad_connect  sys_dma_resetn axi_hp2_interconnect/ARESETN
+ad_connect  sys_dma_resetn axi_hp2_interconnect/M00_ARESETN
+ad_connect  sys_dma_resetn axi_hp2_interconnect/S00_ARESETN
+ad_connect  sys_dma_resetn axi_hp2_interconnect/S01_ARESETN
+
+# interrupts
+
+ad_cpu_interrupt ps-11 mb-11 axi_ad9371_rx_os_dma/irq
+ad_cpu_interrupt ps-12 mb-12 axi_ad9371_tx_dma/irq
+ad_cpu_interrupt ps-13 mb-13 axi_ad9371_rx_dma/irq
+
+# ila
+
+set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
+set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
+set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_adc
+set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
+set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
+set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
+set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
+set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}]  $ila_adc
+set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
+
+ad_connect  axi_rx_clkgen/clk_0                   ila_adc/clk
+ad_connect  axi_ad9371_core/adc_data_i0           ila_adc/probe0
+ad_connect  axi_ad9371_core/adc_data_q0           ila_adc/probe1
+ad_connect  axi_ad9371_core/adc_data_i1           ila_adc/probe2
+ad_connect  axi_ad9371_core/adc_data_q1           ila_adc/probe3
+
+set bsplit_os_adc_0 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 bsplit_os_adc_0]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_0
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $bsplit_os_adc_0
+
+set bsplit_os_adc_1 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 bsplit_os_adc_1]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_1
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $bsplit_os_adc_1
+
+set ila_os_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_os_adc]
+set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_os_adc
+set_property -dict [list CONFIG.C_NUM_OF_PROBES {6}] $ila_os_adc
+set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_os_adc
+set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_os_adc
+set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_os_adc
+set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_os_adc
+set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_os_adc
+set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_os_adc
+set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}]  $ila_os_adc
+set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_os_adc
+
+ad_connect  axi_ad9371_core/adc_os_data_i0        bsplit_os_adc_0/data
+ad_connect  axi_ad9371_core/adc_os_data_q0        bsplit_os_adc_1/data
+ad_connect  axi_rx_os_clkgen/clk_0                ila_os_adc/clk
+ad_connect  axi_ad9371_core/adc_os_valid_i0       ila_os_adc/probe0
+ad_connect  bsplit_os_adc_0/split_data_0          ila_os_adc/probe1
+ad_connect  bsplit_os_adc_0/split_data_1          ila_os_adc/probe2
+ad_connect  axi_ad9371_core/adc_os_valid_q0       ila_os_adc/probe3
+ad_connect  bsplit_os_adc_1/split_data_0          ila_os_adc/probe4
+ad_connect  bsplit_os_adc_1/split_data_1          ila_os_adc/probe5
+
diff --git a/projects/adrv9371x/zc706/system_bd.tcl b/projects/adrv9371x/zc706/system_bd.tcl
new file mode 100644
index 000000000..108741a54
--- /dev/null
+++ b/projects/adrv9371x/zc706/system_bd.tcl
@@ -0,0 +1,5 @@
+
+source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source ../common/adrv9371x_bd.tcl
+
diff --git a/projects/adrv9371x/zc706/system_constr.xdc b/projects/adrv9371x/zc706/system_constr.xdc
new file mode 100644
index 000000000..944b90df3
--- /dev/null
+++ b/projects/adrv9371x/zc706/system_constr.xdc
@@ -0,0 +1,80 @@
+
+# ad9371
+
+set_property  -dict {PACKAGE_PIN  AD10} [get_ports ref_clk0_p]                                        ; ## D04  FMC_HPC_GBTCLK0_M2C_P (NC)
+set_property  -dict {PACKAGE_PIN  AD9 } [get_ports ref_clk0_n]                                        ; ## D05  FMC_HPC_GBTCLK0_M2C_N (NC)
+set_property  -dict {PACKAGE_PIN  AA8 } [get_ports ref_clk1_p]                                        ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  AA7 } [get_ports ref_clk1_n]                                        ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[0]]                                      ; ## A02  FMC_HPC_DP1_M2C_P
+set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[0]]                                      ; ## A03  FMC_HPC_DP1_M2C_N
+set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[1]]                                      ; ## A06  FMC_HPC_DP2_M2C_P
+set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[1]]                                      ; ## A07  FMC_HPC_DP2_M2C_N
+set_property  -dict {PACKAGE_PIN  AH10} [get_ports rx_data_p[2]]                                      ; ## C06  FMC_HPC_DP0_M2C_P
+set_property  -dict {PACKAGE_PIN  AH9 } [get_ports rx_data_n[2]]                                      ; ## C07  FMC_HPC_DP0_M2C_N
+set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[3]]                                      ; ## A10  FMC_HPC_DP3_M2C_P
+set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[3]]                                      ; ## A11  FMC_HPC_DP3_M2C_N
+set_property  -dict {PACKAGE_PIN  AK6 } [get_ports tx_data_p[0]]                                      ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[3])
+set_property  -dict {PACKAGE_PIN  AK5 } [get_ports tx_data_n[0]]                                      ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[3])
+set_property  -dict {PACKAGE_PIN  AJ4 } [get_ports tx_data_p[1]]                                      ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[0])
+set_property  -dict {PACKAGE_PIN  AJ3 } [get_ports tx_data_n[1]]                                      ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[0])
+set_property  -dict {PACKAGE_PIN  AK10} [get_ports tx_data_p[2]]                                      ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[1])
+set_property  -dict {PACKAGE_PIN  AK9 } [get_ports tx_data_n[2]]                                      ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[1])
+set_property  -dict {PACKAGE_PIN  AK2 } [get_ports tx_data_p[3]]                                      ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[2])
+set_property  -dict {PACKAGE_PIN  AK1 } [get_ports tx_data_n[3]]                                      ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[2])
+set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## G09  FMC_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## G10  FMC_HPC_LA03_N
+set_property  -dict {PACKAGE_PIN  T29   IOSTANDARD LVDS_25} [get_ports rx_os_sync_p]                  ; ## G27  FMC_HPC_LA25_P (Sniffer)
+set_property  -dict {PACKAGE_PIN  U29   IOSTANDARD LVDS_25} [get_ports rx_os_sync_n]                  ; ## G28  FMC_HPC_LA25_N (Sniffer)
+set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p]      ; ## H07  FMC_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n]      ; ## H08  FMC_HPC_LA02_N
+set_property  -dict {PACKAGE_PIN  N26   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p]       ; ## G36  FMC_HPC_LA33_P
+set_property  -dict {PACKAGE_PIN  N27   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n]       ; ## G37  FMC_HPC_LA33_N
+
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528]               ; ## D15  FMC_HPC_LA09_N
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9371]               ; ## D14  FMC_HPC_LA09_P
+set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## H13  FMC_HPC_LA07_P
+set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                     ; ## H14  FMC_HPC_LA07_N
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports spi_miso]                     ; ## G12  FMC_HPC_LA08_P
+
+set_property  -dict {PACKAGE_PIN  R28   IOSTANDARD LVCMOS25} [get_ports ad9528_reset_b]               ; ## D26  FMC_HPC_LA26_P
+set_property  -dict {PACKAGE_PIN  T28   IOSTANDARD LVCMOS25} [get_ports ad9528_sysref_req]            ; ## D27  FMC_HPC_LA26_N
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports ad9371_tx1_enable]            ; ## D17  FMC_HPC_LA13_P
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD LVCMOS25} [get_ports ad9371_tx2_enable]            ; ## C18  FMC_HPC_LA14_P
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports ad9371_rx1_enable]            ; ## D18  FMC_HPC_LA13_N
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVCMOS25} [get_ports ad9371_rx2_enable]            ; ## C19  FMC_HPC_LA14_N
+set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVCMOS25} [get_ports ad9371_test]                  ; ## D11  FMC_HPC_LA05_P
+set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVCMOS25} [get_ports ad9371_reset_b]               ; ## H10  FMC_HPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVCMOS25} [get_ports ad9371_gpint]                 ; ## H11  FMC_HPC_LA04_N
+
+set_property  -dict {PACKAGE_PIN  Y22   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_00]               ; ## H19  FMC_HPC_LA15_P          
+set_property  -dict {PACKAGE_PIN  Y23   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_01]               ; ## H20  FMC_HPC_LA15_N          
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_02]               ; ## G18  FMC_HPC_LA16_P          
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_03]               ; ## G19  FMC_HPC_LA16_N          
+set_property  -dict {PACKAGE_PIN  W29   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_04]               ; ## H25  FMC_HPC_LA21_P          
+set_property  -dict {PACKAGE_PIN  W30   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_05]               ; ## H26  FMC_HPC_LA21_N          
+set_property  -dict {PACKAGE_PIN  W25   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_06]               ; ## C22  FMC_HPC_LA18_CC_P       
+set_property  -dict {PACKAGE_PIN  W26   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_07]               ; ## C23  FMC_HPC_LA18_CC_N       
+set_property  -dict {PACKAGE_PIN  V27   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_15]               ; ## G24  FMC_HPC_LA22_P     (LVDS Pairs?)    
+set_property  -dict {PACKAGE_PIN  W28   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_08]               ; ## G25  FMC_HPC_LA22_N     (LVDS Pairs?)    
+set_property  -dict {PACKAGE_PIN  T24   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_09]               ; ## H22  FMC_HPC_LA19_P     (LVDS Pairs?)    
+set_property  -dict {PACKAGE_PIN  T25   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_10]               ; ## H23  FMC_HPC_LA19_N     (LVDS Pairs?)    
+set_property  -dict {PACKAGE_PIN  U25   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_11]               ; ## G21  FMC_HPC_LA20_P     (LVDS Pairs?)    
+set_property  -dict {PACKAGE_PIN  V26   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_12]               ; ## G22  FMC_HPC_LA20_N     (LVDS Pairs?)    
+set_property  -dict {PACKAGE_PIN  R25   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_14]               ; ## G30  FMC_HPC_LA29_P     (LVDS Pairs?)    
+set_property  -dict {PACKAGE_PIN  R26   IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_13]               ; ## G31  FMC_HPC_LA29_N     (LVDS Pairs?)    
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_17]               ; ## G15  FMC_HPC_LA12_P     (LVDS Pairs?)
+set_property  -dict {PACKAGE_PIN  AF24  IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_16]               ; ## G16  FMC_HPC_LA12_N     (LVDS Pairs?)
+set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_18]               ; ## D12  FMC_HPC_LA05_N          
+
+# clocks
+
+create_clock -name tx_ref_clk   -period  6.25 [get_ports ref_clk0_p]
+create_clock -name rx_ref_clk   -period  6.25 [get_ports ref_clk1_p]
+create_clock -name tx_div_clk   -period  6.25 [get_pins i_system_wrapper/system_i/axi_ad9371_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  6.25 [get_pins i_system_wrapper/system_i/axi_ad9371_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+
+# sync is also sampled at the cpu clock by the ip.
+
+set_false_path -from [get_cells -hier -filter {name =~ *axi_ad9371_gt*tx_ip_sync*  && IS_SEQUENTIAL}] \
+  -to [get_cells -hier -filter {name =~ *axi_ad9371_tx_jesd*sync_tx_sync*data_sync* && IS_SEQUENTIAL}]
+
diff --git a/projects/adrv9371x/zc706/system_project.tcl b/projects/adrv9371x/zc706/system_project.tcl
new file mode 100644
index 000000000..7c4ff30c2
--- /dev/null
+++ b/projects/adrv9371x/zc706/system_project.tcl
@@ -0,0 +1,20 @@
+
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create adrv9371x_zc706
+adi_project_files adrv9371x_zc706 [list \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
+
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+
+adi_project_run adrv9371x_zc706
+
+
diff --git a/projects/adrv9371x/zc706/system_top.v b/projects/adrv9371x/zc706/system_top.v
new file mode 100644
index 000000000..a7d4ff1b8
--- /dev/null
+++ b/projects/adrv9371x/zc706/system_top.v
@@ -0,0 +1,389 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  gpio_bd,
+
+  hdmi_out_clk,
+  hdmi_vsync,
+  hdmi_hsync,
+  hdmi_data_e,
+  hdmi_data,
+
+  spdif,
+
+  iic_scl,
+  iic_sda,
+
+  ref_clk0_p,
+  ref_clk0_n,
+  ref_clk1_p,
+  ref_clk1_n,
+  rx_data_p,
+  rx_data_n,
+  tx_data_p,
+  tx_data_n,
+  rx_sync_p,
+  rx_sync_n,
+  rx_os_sync_p,
+  rx_os_sync_n,
+  tx_sync_p,
+  tx_sync_n,
+  sysref_p,
+  sysref_n,
+
+  spi_csn_ad9528,
+  spi_csn_ad9371,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  ad9528_reset_b,
+  ad9528_sysref_req,
+  ad9371_tx1_enable,
+  ad9371_tx2_enable,
+  ad9371_rx1_enable,
+  ad9371_rx2_enable,
+  ad9371_test,
+  ad9371_reset_b,
+  ad9371_gpint,
+
+  ad9371_gpio_00,
+  ad9371_gpio_01,
+  ad9371_gpio_02,
+  ad9371_gpio_03,
+  ad9371_gpio_04,
+  ad9371_gpio_05,
+  ad9371_gpio_06,
+  ad9371_gpio_07,
+  ad9371_gpio_15,
+  ad9371_gpio_08,
+  ad9371_gpio_09,
+  ad9371_gpio_10,
+  ad9371_gpio_11,
+  ad9371_gpio_12,
+  ad9371_gpio_14,
+  ad9371_gpio_13,
+  ad9371_gpio_17,
+  ad9371_gpio_16,
+  ad9371_gpio_18);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout   [14:0]  gpio_bd;
+
+  output          hdmi_out_clk;
+  output          hdmi_vsync;
+  output          hdmi_hsync;
+  output          hdmi_data_e;
+  output  [23:0]  hdmi_data;
+
+  output          spdif;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  input           ref_clk0_p;
+  input           ref_clk0_n;
+  input           ref_clk1_p;
+  input           ref_clk1_n;
+  input   [ 3:0]  rx_data_p;
+  input   [ 3:0]  rx_data_n;
+  output  [ 3:0]  tx_data_p;
+  output  [ 3:0]  tx_data_n;
+  output          rx_sync_p;
+  output          rx_sync_n;
+  output          rx_os_sync_p;
+  output          rx_os_sync_n;
+  input           tx_sync_p;
+  input           tx_sync_n;
+  input           sysref_p;
+  input           sysref_n;
+
+  output          spi_csn_ad9528;
+  output          spi_csn_ad9371;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  inout           ad9528_reset_b;
+  inout           ad9528_sysref_req;
+  inout           ad9371_tx1_enable;
+  inout           ad9371_tx2_enable;
+  inout           ad9371_rx1_enable;
+  inout           ad9371_rx2_enable;
+  inout           ad9371_test;
+  inout           ad9371_reset_b;
+  inout           ad9371_gpint;
+
+  inout           ad9371_gpio_00;
+  inout           ad9371_gpio_01;
+  inout           ad9371_gpio_02;
+  inout           ad9371_gpio_03;
+  inout           ad9371_gpio_04;
+  inout           ad9371_gpio_05;
+  inout           ad9371_gpio_06;
+  inout           ad9371_gpio_07;
+  inout           ad9371_gpio_15;
+  inout           ad9371_gpio_08;
+  inout           ad9371_gpio_09;
+  inout           ad9371_gpio_10;
+  inout           ad9371_gpio_11;
+  inout           ad9371_gpio_12;
+  inout           ad9371_gpio_14;
+  inout           ad9371_gpio_13;
+  inout           ad9371_gpio_17;
+  inout           ad9371_gpio_16;
+  inout           ad9371_gpio_18;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire            ref_clk0;
+  wire            ref_clk1;
+  wire            rx_sync;
+  wire            rx_os_sync;
+  wire            tx_sync;
+  wire            sysref;
+  wire            ad9371_dac_fifo_bypass_s;
+
+  // instantiations
+
+  IBUFDS_GTE2 i_ibufds_rx_ref_clk (
+    .CEB (1'd0),
+    .I (ref_clk0_p),
+    .IB (ref_clk0_n),
+    .O (ref_clk0),
+    .ODIV2 ());
+
+  IBUFDS_GTE2 i_ibufds_ref_clk1 (
+    .CEB (1'd0),
+    .I (ref_clk1_p),
+    .IB (ref_clk1_n),
+    .O (ref_clk1),
+    .ODIV2 ());
+
+  OBUFDS i_obufds_rx_sync (
+    .I (rx_sync),
+    .O (rx_sync_p),
+    .OB (rx_sync_n));
+
+  OBUFDS i_obufds_rx_os_sync (
+    .I (rx_os_sync),
+    .O (rx_os_sync_p),
+    .OB (rx_os_sync_n));
+
+  IBUFDS i_ibufds_tx_sync (
+    .I (tx_sync_p),
+    .IB (tx_sync_n),
+    .O (tx_sync));
+
+  IBUFDS i_ibufds_sysref (
+    .I (sysref_p),
+    .IB (sysref_n),
+    .O (sysref));
+
+  ad_iobuf #(.DATA_WIDTH(29)) i_iobuf (
+    .dio_t ({gpio_t[60:32]}),
+    .dio_i ({gpio_o[60:32]}),
+    .dio_o ({gpio_i[60:32]}),
+    .dio_p ({ ad9371_dac_fifo_bypass_s, // 60
+              ad9528_reset_b,       // 59
+              ad9528_sysref_req,    // 58
+              ad9371_tx1_enable,    // 57
+              ad9371_tx2_enable,    // 56
+              ad9371_rx1_enable,    // 55
+              ad9371_rx2_enable,    // 54
+              ad9371_test,          // 53
+              ad9371_reset_b,       // 52
+              ad9371_gpint,         // 51
+              ad9371_gpio_00,       // 50
+              ad9371_gpio_01,       // 49
+              ad9371_gpio_02,       // 48
+              ad9371_gpio_03,       // 47
+              ad9371_gpio_04,       // 46
+              ad9371_gpio_05,       // 45
+              ad9371_gpio_06,       // 44
+              ad9371_gpio_07,       // 43
+              ad9371_gpio_15,       // 42
+              ad9371_gpio_08,       // 41
+              ad9371_gpio_09,       // 40
+              ad9371_gpio_10,       // 39
+              ad9371_gpio_11,       // 38
+              ad9371_gpio_12,       // 37
+              ad9371_gpio_14,       // 36
+              ad9371_gpio_13,       // 35
+              ad9371_gpio_17,       // 34
+              ad9371_gpio_16,       // 33
+              ad9371_gpio_18}));    // 32
+
+  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
+    .dio_t (gpio_t[14:0]),
+    .dio_i (gpio_o[14:0]),
+    .dio_o (gpio_i[14:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .rx_n (rx_data_n[1:0]),
+    .rx_os_n (rx_data_n[3:2]),
+    .rx_os_p (rx_data_p[3:2]),
+    .rx_os_sync (rx_os_sync),
+    .rx_p (rx_data_p[1:0]),
+    .rx_ref_clk (ref_clk1),
+    .rx_sync (rx_sync),
+    .rx_sysref (sysref),
+    .spdif (spdif),
+    .spi0_clk_i (spi_clk),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn_ad9528),
+    .spi0_csn_1_o (spi_csn_ad9371),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (spi_mosi),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'd0),
+    .spi1_clk_o (1'd0),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'd0),
+    .spi1_sdo_i (1'd0),
+    .spi1_sdo_o (),
+    .tx_n (tx_data_n),
+    .tx_p (tx_data_p),
+    .tx_ref_clk (ref_clk1),
+    .tx_sync (tx_sync),
+    .tx_sysref (sysref),
+    .dac_fifo_bypass(ad9371_dac_fifo_bypass_s));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 09520709b0e6494571a553cab7cb4e8b1a47e44a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 20 May 2016 12:35:45 -0400
Subject: [PATCH 224/972] make updates

---
 library/Makefile                   |  2 +
 library/axi_ad9371/Makefile        | 65 +++++++++++++++++++++
 library/util_rfifo/Makefile        |  1 +
 projects/Makefile                  |  3 +
 projects/adrv9371x/Makefile        | 24 ++++++++
 projects/adrv9371x/a10soc/Makefile | 75 ------------------------
 projects/adrv9371x/zc706/Makefile  | 93 ++++++++++++++++++++++++++++++
 projects/arradio/c5soc/Makefile    |  5 ++
 projects/fmcomms2/Makefile         |  3 +
 projects/fmcomms2/zcu102/Makefile  | 19 ++----
 10 files changed, 201 insertions(+), 89 deletions(-)
 create mode 100644 library/axi_ad9371/Makefile
 create mode 100644 projects/adrv9371x/Makefile
 create mode 100644 projects/adrv9371x/zc706/Makefile

diff --git a/library/Makefile b/library/Makefile
index 983870d4f..9f733ebdc 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -18,6 +18,7 @@ clean:
 	make -C axi_ad9250 clean
 	make -C axi_ad9265 clean
 	make -C axi_ad9361 clean
+	make -C axi_ad9371 clean
 	make -C axi_ad9434 clean
 	make -C axi_ad9467 clean
 	make -C axi_ad9625 clean
@@ -86,6 +87,7 @@ lib:
 	-make -C axi_ad9250
 	-make -C axi_ad9265
 	-make -C axi_ad9361
+	-make -C axi_ad9371
 	-make -C axi_ad9434
 	-make -C axi_ad9467
 	-make -C axi_ad9625
diff --git a/library/axi_ad9371/Makefile b/library/axi_ad9371/Makefile
new file mode 100644
index 000000000..61d7ca6e1
--- /dev/null
+++ b/library/axi_ad9371/Makefile
@@ -0,0 +1,65 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := axi_ad9371_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_mul.v
+M_DEPS += ../common/ad_dds_sine.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_dcfilter.v
+M_DEPS += ../common/ad_iqcor.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_dac_common.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += axi_ad9371_if.v
+M_DEPS += axi_ad9371_rx_channel.v
+M_DEPS += axi_ad9371_rx.v
+M_DEPS += axi_ad9371_rx_os.v
+M_DEPS += axi_ad9371_tx_channel.v
+M_DEPS += axi_ad9371_tx.v
+M_DEPS += axi_ad9371.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_ad9371.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_ad9371.xpr: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_ad9371_ip.tcl  >> axi_ad9371_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/util_rfifo/Makefile b/library/util_rfifo/Makefile
index eab393fd5..b4c7de9fa 100644
--- a/library/util_rfifo/Makefile
+++ b/library/util_rfifo/Makefile
@@ -8,6 +8,7 @@
 M_DEPS := util_rfifo_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../common/ad_mem.v
 M_DEPS += util_rfifo.v
 
 M_VIVADO := vivado -mode batch -source
diff --git a/projects/Makefile b/projects/Makefile
index b326e0903..ee568616a 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -13,6 +13,7 @@ all:
 	-make -C ad9434_fmc all
 	-make -C ad9467_fmc all
 	-make -C ad9739a_fmc all
+	-make -C adrv9371x all
 	-make -C adv7511 all
 	-make -C arradio all
 	-make -C cftl_cip all
@@ -46,6 +47,7 @@ clean:
 	make -C ad9434_fmc clean
 	make -C ad9467_fmc clean
 	make -C ad9739a_fmc clean
+	make -C adrv9371x clean
 	make -C adv7511 clean
 	make -C arradio clean
 	make -C cftl_cip clean
@@ -79,6 +81,7 @@ clean-all:
 	make -C ad9434_fmc clean-all
 	make -C ad9467_fmc clean-all
 	make -C ad9739a_fmc clean-all
+	make -C adrv9371x clean-all
 	make -C adv7511 clean-all
 	make -C arradio clean-all
 	make -C cftl_cip clean-all
diff --git a/projects/adrv9371x/Makefile b/projects/adrv9371x/Makefile
new file mode 100644
index 000000000..feb85db28
--- /dev/null
+++ b/projects/adrv9371x/Makefile
@@ -0,0 +1,24 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+.PHONY: all clean clean-all 
+all:
+	-make -C a10soc all
+	-make -C zc706 all
+
+
+clean: 
+	make -C a10soc clean
+	make -C zc706 clean
+
+
+clean-all:
+	make -C a10soc clean-all
+	make -C zc706 clean-all
+
+####################################################################################
+####################################################################################
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index ed286a1c4..77133e4f4 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -9,84 +9,9 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += system_bd.qsys
-M_DEPS += ../common/fmcomms2_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
-M_DEPS += ../../../library/axi_dmac/2d_transfer.v
-M_DEPS += ../../../library/axi_dmac/address_generator.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
-M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
-M_DEPS += ../../../library/axi_dmac/data_mover.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
-M_DEPS += ../../../library/axi_dmac/inc_id.h
-M_DEPS += ../../../library/axi_dmac/request_arb.v
-M_DEPS += ../../../library/axi_dmac/request_generator.v
-M_DEPS += ../../../library/axi_dmac/resp.h
-M_DEPS += ../../../library/axi_dmac/response_generator.v
-M_DEPS += ../../../library/axi_dmac/response_handler.v
-M_DEPS += ../../../library/axi_dmac/splitter.v
-M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/common/ad_addsub.v
-M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_dcfilter.v
-M_DEPS += ../../../library/common/ad_dds.v
-M_DEPS += ../../../library/common/ad_dds_1.v
-M_DEPS += ../../../library/common/ad_dds_sine.v
-M_DEPS += ../../../library/common/ad_iqcor.v
-M_DEPS += ../../../library/common/ad_mul.v
-M_DEPS += ../../../library/common/ad_pnmon.v
-M_DEPS += ../../../library/common/ad_rst.v
-M_DEPS += ../../../library/common/ad_tdd_control.v
-M_DEPS += ../../../library/common/altera/DSP48E1.v
-M_DEPS += ../../../library/common/altera/MULT_MACRO.v
-M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
-M_DEPS += ../../../library/common/altera/ad_cmos_in.v
-M_DEPS += ../../../library/common/altera/ad_cmos_out.v
-M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
-M_DEPS += ../../../library/common/altera/ad_lvds_in.v
-M_DEPS += ../../../library/common/altera/ad_lvds_out.v
-M_DEPS += ../../../library/common/sync_bits.v
-M_DEPS += ../../../library/common/sync_gray.v
-M_DEPS += ../../../library/common/up_adc_channel.v
-M_DEPS += ../../../library/common/up_adc_common.v
-M_DEPS += ../../../library/common/up_axi.v
-M_DEPS += ../../../library/common/up_clock_mon.v
-M_DEPS += ../../../library/common/up_dac_channel.v
-M_DEPS += ../../../library/common/up_dac_common.v
-M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_tdd_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
-M_DEPS += ../../../library/util_axis_fifo/address_sync.v
-M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
-M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
-M_DEPS += ../../../library/util_cpack/util_cpack.v
-M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
-M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
-M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
-M_DEPS += ../../../library/util_upack/util_upack.v
-M_DEPS += ../../../library/util_upack/util_upack_dmx.v
-M_DEPS += ../../../library/util_upack/util_upack_dsf.v
-M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
new file mode 100644
index 000000000..751f13fe8
--- /dev/null
+++ b/projects/adrv9371x/zc706/Makefile
@@ -0,0 +1,93 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/adrv9371x_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zc706/zc706_system_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
+M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib adrv9371x_zc706.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9371 clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/util_bsplit clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_dacfifo clean
+	make -C ../../../library/util_jesd_gt clean
+	make -C ../../../library/util_upack clean
+
+
+adrv9371x_zc706.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> adrv9371x_zc706_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9371
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_adcfifo
+	make -C ../../../library/util_bsplit
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_dacfifo
+	make -C ../../../library/util_jesd_gt
+	make -C ../../../library/util_upack
+
+####################################################################################
+####################################################################################
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index db86d7572..d9de7293b 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -51,6 +51,7 @@ M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_iqcor.v
+M_DEPS += ../../../library/common/ad_mem.v
 M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
@@ -84,10 +85,14 @@ M_DEPS += ../../../library/util_cpack/util_cpack.v
 M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
 M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
 M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_rfifo/util_rfifo.v
+M_DEPS += ../../../library/util_rfifo/util_rfifo_hw.tcl
 M_DEPS += ../../../library/util_upack/util_upack.v
 M_DEPS += ../../../library/util_upack/util_upack_dmx.v
 M_DEPS += ../../../library/util_upack/util_upack_dsf.v
 M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+M_DEPS += ../../../library/util_wfifo/util_wfifo.v
+M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/fmcomms2/Makefile b/projects/fmcomms2/Makefile
index 7da011a70..297dc87af 100644
--- a/projects/fmcomms2/Makefile
+++ b/projects/fmcomms2/Makefile
@@ -14,6 +14,7 @@ all:
 	-make -C vc707 all
 	-make -C zc702 all
 	-make -C zc706 all
+	-make -C zcu102 all
 	-make -C zed all
 
 
@@ -25,6 +26,7 @@ clean:
 	make -C vc707 clean
 	make -C zc702 clean
 	make -C zc706 clean
+	make -C zcu102 clean
 	make -C zed clean
 
 
@@ -36,6 +38,7 @@ clean-all:
 	make -C vc707 clean-all
 	make -C zc702 clean-all
 	make -C zc706 clean-all
+	make -C zcu102 clean-all
 	make -C zed clean-all
 
 ####################################################################################
diff --git a/projects/fmcomms2/zcu102/Makefile b/projects/fmcomms2/zcu102/Makefile
index d3c52de44..3418eb35a 100644
--- a/projects/fmcomms2/zcu102/Makefile
+++ b/projects/fmcomms2/zcu102/Makefile
@@ -13,14 +13,11 @@ M_DEPS += ../common/fmcomms2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_constr.xdc
-M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
+M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
-M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
@@ -44,7 +41,7 @@ M_FLIST += .Xil
 
 
 .PHONY: all lib clean clean-all
-all: lib fmcomms2_zc706.sdk/system_top.hdf
+all: lib fmcomms2_zcu102.sdk/system_top.hdf
 
 
 clean: 
@@ -53,27 +50,21 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
-	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
 
 
-fmcomms2_zc706.sdk/system_top.hdf: $(M_DEPS)
+fmcomms2_zcu102.sdk/system_top.hdf: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms2_zc706_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> fmcomms2_zcu102_vivado.log 2>&1
 
 
 lib:
 	make -C ../../../library/axi_ad9361
-	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack

From f1a603a3b1f6b884bd4156b2dd2ed1cac7baf154 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 20 May 2016 15:16:36 -0400
Subject: [PATCH 225/972] ad9371- altera ip

---
 library/axi_ad9371/axi_ad9371_hw.tcl | 208 +++++++++++++++++++++++++++
 1 file changed, 208 insertions(+)
 create mode 100755 library/axi_ad9371/axi_ad9371_hw.tcl

diff --git a/library/axi_ad9371/axi_ad9371_hw.tcl b/library/axi_ad9371/axi_ad9371_hw.tcl
new file mode 100755
index 000000000..2fb63d294
--- /dev/null
+++ b/library/axi_ad9371/axi_ad9371_hw.tcl
@@ -0,0 +1,208 @@
+
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+set_module_property NAME axi_ad9371
+set_module_property DESCRIPTION "AXI AD9371 Interface"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME axi_ad9371
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL axi_ad9371
+add_fileset_file MULT_MACRO.v               VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
+add_fileset_file ad_rst.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
+add_fileset_file ad_mul.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
+add_fileset_file ad_dds_sine.v              VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
+add_fileset_file ad_dds_1.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
+add_fileset_file ad_dds.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
+add_fileset_file ad_datafmt.v               VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
+add_fileset_file ad_dcfilter.v              VERILOG PATH $ad_hdl_dir/library/common/ad_dcfilter.v
+add_fileset_file ad_iqcor.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
+add_fileset_file up_axi.v                   VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
+add_fileset_file up_xfer_cntrl.v            VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
+add_fileset_file up_xfer_status.v           VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
+add_fileset_file up_clock_mon.v             VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
+add_fileset_file up_adc_common.v            VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
+add_fileset_file up_adc_channel.v           VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
+add_fileset_file up_dac_common.v            VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
+add_fileset_file up_dac_channel.v           VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
+add_fileset_file axi_ad9371_if.v            VERILOG PATH axi_ad9371_if.v
+add_fileset_file axi_ad9371_rx_channel.v    VERILOG PATH axi_ad9371_rx_channel.v
+add_fileset_file axi_ad9371_rx.v            VERILOG PATH axi_ad9371_rx.v
+add_fileset_file axi_ad9371_rx_os.v         VERILOG PATH axi_ad9371_rx_os.v
+add_fileset_file axi_ad9371_tx_channel.v    VERILOG PATH axi_ad9371_tx_channel.v
+add_fileset_file axi_ad9371_tx.v            VERILOG PATH axi_ad9371_tx.v
+add_fileset_file axi_ad9371.v               VERILOG PATH axi_ad9371.v TOP_LEVEL_FILE
+add_fileset_file ad_axi_ip_constr.sdc       SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+
+# parameters
+
+add_parameter ID INTEGER 0
+set_parameter_property ID DEFAULT_VALUE 0
+set_parameter_property ID DISPLAY_NAME ID
+set_parameter_property ID TYPE INTEGER
+set_parameter_property ID UNITS None
+set_parameter_property ID HDL_PARAMETER true
+
+add_parameter DAC_DATAPATH_DISABLE INTEGER 0
+set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
+set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
+set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
+set_parameter_property DAC_DATAPATH_DISABLE UNITS None
+set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
+
+add_parameter ADC_DATAPATH_DISABLE INTEGER 0
+set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0
+set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE
+set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
+set_parameter_property ADC_DATAPATH_DISABLE UNITS None
+set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
+
+# axi4 slave
+
+add_interface s_axi_clock clock end
+add_interface_port s_axi_clock s_axi_aclk clk Input 1
+
+add_interface s_axi_reset reset end
+set_interface_property s_axi_reset associatedClock s_axi_clock
+add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
+
+add_interface s_axi axi4lite end
+set_interface_property s_axi associatedClock s_axi_clock
+set_interface_property s_axi associatedReset s_axi_reset
+add_interface_port s_axi s_axi_awvalid awvalid Input 1
+add_interface_port s_axi s_axi_awaddr awaddr Input 16
+add_interface_port s_axi s_axi_awprot awprot Input 3
+add_interface_port s_axi s_axi_awready awready Output 1
+add_interface_port s_axi s_axi_wvalid wvalid Input 1
+add_interface_port s_axi s_axi_wdata wdata Input 32
+add_interface_port s_axi s_axi_wstrb wstrb Input 4
+add_interface_port s_axi s_axi_wready wready Output 1
+add_interface_port s_axi s_axi_bvalid bvalid Output 1
+add_interface_port s_axi s_axi_bresp bresp Output 2
+add_interface_port s_axi s_axi_bready bready Input 1
+add_interface_port s_axi s_axi_arvalid arvalid Input 1
+add_interface_port s_axi s_axi_araddr araddr Input 16
+add_interface_port s_axi s_axi_arprot arprot Input 3
+add_interface_port s_axi s_axi_arready arready Output 1
+add_interface_port s_axi s_axi_rvalid rvalid Output 1
+add_interface_port s_axi s_axi_rresp rresp Output 2
+add_interface_port s_axi s_axi_rdata rdata Output 32
+add_interface_port s_axi s_axi_rready rready Input 1
+
+# transceiver interface
+
+ad_alt_intf clock   adc_clk         input   1
+ad_alt_intf signal  adc_rx_data     input   64  data
+
+ad_alt_intf clock   adc_os_clk      input   1
+ad_alt_intf signal  adc_rx_os_data  input   64  data
+
+ad_alt_intf clock   dac_clk         input   1
+ad_alt_intf signal  dac_tx_data     output  128 data
+
+# master/slave
+
+ad_alt_intf signal  dac_sync_in     input   1
+ad_alt_intf signal  dac_sync_out    output  1
+
+# adc-channel interface
+
+add_interface adc_ch_0 conduit end
+add_interface_port adc_ch_0  adc_enable_i0  enable   Output  1
+add_interface_port adc_ch_0  adc_valid_i0   valid    Output  1
+add_interface_port adc_ch_0  adc_data_i0    data     Output  16
+
+set_interface_property adc_ch_0 associatedClock if_adc_clk
+set_interface_property adc_ch_0 associatedReset none
+
+add_interface adc_ch_1 conduit end
+add_interface_port adc_ch_1  adc_enable_q0  enable   Output  1
+add_interface_port adc_ch_1  adc_valid_q0   valid    Output  1
+add_interface_port adc_ch_1  adc_data_q0    data     Output  16
+
+set_interface_property adc_ch_1 associatedClock if_adc_clk
+set_interface_property adc_ch_1 associatedReset none
+
+add_interface adc_ch_2 conduit end
+add_interface_port adc_ch_2  adc_enable_i1  enable   Output  1
+add_interface_port adc_ch_2  adc_valid_i1   valid    Output  1
+add_interface_port adc_ch_2  adc_data_i1    data     Output  16
+
+set_interface_property adc_ch_2 associatedClock if_adc_clk
+set_interface_property adc_ch_2 associatedReset none
+
+add_interface adc_ch_3 conduit end
+add_interface_port adc_ch_3  adc_enable_q1  enable   Output  1
+add_interface_port adc_ch_3  adc_valid_q1   valid    Output  1
+add_interface_port adc_ch_3  adc_data_q1    data     Output  16
+
+set_interface_property adc_ch_3 associatedClock if_adc_clk
+set_interface_property adc_ch_3 associatedReset none
+
+ad_alt_intf signal  adc_dovf      input   1 ovf
+ad_alt_intf signal  adc_dunf      input   1 unf
+
+# adc-os-channel interface
+
+add_interface adc_os_ch_0 conduit end
+add_interface_port adc_os_ch_0  adc_os_enable_i0  enable   Output  1
+add_interface_port adc_os_ch_0  adc_os_valid_i0   valid    Output  1
+add_interface_port adc_os_ch_0  adc_os_data_i0    data     Output  32
+
+set_interface_property adc_os_ch_0 associatedClock if_adc_os_clk
+set_interface_property adc_os_ch_0 associatedReset none
+
+add_interface adc_os_ch_1 conduit end
+add_interface_port adc_os_ch_1  adc_os_enable_q0  enable   Output  1
+add_interface_port adc_os_ch_1  adc_os_valid_q0   valid    Output  1
+add_interface_port adc_os_ch_1  adc_os_data_q0    data     Output  32
+
+set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk
+set_interface_property adc_os_ch_1 associatedReset none
+
+ad_alt_intf signal  adc_os_dovf      input   1 ovf
+ad_alt_intf signal  adc_os_dunf      input   1 unf
+
+# dac-channel interface
+
+add_interface dac_ch_0 conduit end
+add_interface_port dac_ch_0  dac_enable_i0  enable   Output  1
+add_interface_port dac_ch_0  dac_valid_i0   valid    Output  1
+add_interface_port dac_ch_0  dac_data_i0    data     Input   32
+
+set_interface_property dac_ch_0 associatedClock if_dac_clk
+set_interface_property dac_ch_0 associatedReset none
+
+add_interface dac_ch_1 conduit end
+add_interface_port dac_ch_1  dac_enable_q0  enable   Output  1
+add_interface_port dac_ch_1  dac_valid_q0   valid    Output  1
+add_interface_port dac_ch_1  dac_data_q0    data     Input   32
+
+set_interface_property dac_ch_1 associatedClock if_dac_clk
+set_interface_property dac_ch_1 associatedReset none
+
+add_interface dac_ch_2 conduit end
+add_interface_port dac_ch_2  dac_enable_i1  enable   Output  1
+add_interface_port dac_ch_2  dac_valid_i1   valid    Output  1
+add_interface_port dac_ch_2  dac_data_i1    data     Input   32
+
+set_interface_property dac_ch_2 associatedClock if_dac_clk
+set_interface_property dac_ch_2 associatedReset none
+
+add_interface dac_ch_3 conduit end
+add_interface_port dac_ch_3  dac_enable_q1  enable   Output  1
+add_interface_port dac_ch_3  dac_valid_q1   valid    Output  1
+add_interface_port dac_ch_3  dac_data_q1    data     Input   32
+
+set_interface_property dac_ch_3 associatedClock if_dac_clk
+set_interface_property dac_ch_3 associatedReset none
+
+ad_alt_intf signal  dac_dovf      input   1 ovf
+ad_alt_intf signal  dac_dunf      input   1 unf
+

From 3f00614bc71ce85c1adae06d41e91c581f998127 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 20 May 2016 16:13:36 -0400
Subject: [PATCH 226/972] axi_jesd_xcvr: rx/tx only select

---
 library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl | 82 ++++++++++++----------
 1 file changed, 44 insertions(+), 38 deletions(-)

diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl b/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
index 40ed2e55c..7415ce27a 100755
--- a/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+++ b/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
@@ -88,49 +88,55 @@ add_interface_port s_axi s_axi_rready rready Input 1
 
 ad_alt_intf reset   rst                 output  1 s_axi_clock s_axi_reset
 
-ad_alt_intf clock   rx_clk              input   1
-ad_alt_intf reset-n rx_rstn             output  1 if_rx_clk s_axi_reset
-ad_alt_intf signal  rx_ext_sysref_in    input   1
-ad_alt_intf signal  rx_ext_sysref_out   output  1
-ad_alt_intf signal  rx_sync             output  1
-ad_alt_intf signal  rx_sof              output  RX_NUM_OF_LANES
-ad_alt_intf signal  rx_data             output  RX_NUM_OF_LANES*32  data
-ad_alt_intf signal  rx_ready            input   RX_NUM_OF_LANES rx_ready
-ad_alt_intf signal  rx_ip_sysref        output  1 export
-ad_alt_intf signal  rx_ip_sync          input   1 export
-ad_alt_intf signal  rx_ip_sof           input   4 export
-
-add_interface if_rx_ip_avl avalon_streaming sink
-add_interface_port if_rx_ip_avl rx_ip_data  data  input RX_NUM_OF_LANES*32
-add_interface_port if_rx_ip_avl rx_ip_valid valid input 1
-add_interface_port if_rx_ip_avl rx_ip_ready ready output 1
-
-ad_alt_intf clock   tx_clk              input   1
-ad_alt_intf reset-n tx_rstn             output  1 if_tx_clk s_axi_reset
-ad_alt_intf signal  tx_ext_sysref_in    input   1
-ad_alt_intf signal  tx_ext_sysref_out   output  1
-ad_alt_intf signal  tx_sync             input   1
-ad_alt_intf signal  tx_data             input   TX_NUM_OF_LANES*32  data
-ad_alt_intf signal  tx_ready            input   TX_NUM_OF_LANES tx_ready
-ad_alt_intf signal  tx_ip_sysref        output  1 export
-ad_alt_intf signal  tx_ip_sync          output  1 export
-
-add_interface if_tx_ip_avl avalon_streaming source
-add_interface_port if_tx_ip_avl tx_ip_data  data  output TX_NUM_OF_LANES*32
-add_interface_port if_tx_ip_avl tx_ip_valid valid output 1
-add_interface_port if_tx_ip_avl tx_ip_ready ready input 1
-
 proc p_axi_jesd_xcvr {} {
 
   set p_num_of_rx_lanes [get_parameter_value "RX_NUM_OF_LANES"]
   set p_num_of_tx_lanes [get_parameter_value "TX_NUM_OF_LANES"]
 
-  set_interface_property if_rx_ip_avl associatedClock if_rx_clk
-  set_interface_property if_rx_ip_avl associatedReset if_rx_rstn
-  set_interface_property if_rx_ip_avl dataBitsPerSymbol [expr ($p_num_of_rx_lanes*32)]
+  if {$p_num_of_rx_lanes > 0} {
+
+    ad_alt_intf clock   rx_clk              input   1
+    ad_alt_intf reset-n rx_rstn             output  1 if_rx_clk s_axi_reset
+    ad_alt_intf signal  rx_ext_sysref_in    input   1
+    ad_alt_intf signal  rx_ext_sysref_out   output  1
+    ad_alt_intf signal  rx_sync             output  1
+    ad_alt_intf signal  rx_sof              output  $p_num_of_rx_lanes
+    ad_alt_intf signal  rx_data             output  $p_num_of_rx_lanes*32  data
+    ad_alt_intf signal  rx_ready            input   $p_num_of_rx_lanes rx_ready
+    ad_alt_intf signal  rx_ip_sysref        output  1 export
+    ad_alt_intf signal  rx_ip_sync          input   1 export
+    ad_alt_intf signal  rx_ip_sof           input   4 export
+ 
+    add_interface if_rx_ip_avl avalon_streaming sink
+    add_interface_port if_rx_ip_avl rx_ip_data  data  input $p_num_of_rx_lanes*32
+    add_interface_port if_rx_ip_avl rx_ip_valid valid input 1
+    add_interface_port if_rx_ip_avl rx_ip_ready ready output 1
+ 
+    set_interface_property if_rx_ip_avl associatedClock if_rx_clk
+    set_interface_property if_rx_ip_avl associatedReset if_rx_rstn
+    set_interface_property if_rx_ip_avl dataBitsPerSymbol [expr ($p_num_of_rx_lanes*32)]
+  }
   
-  set_interface_property if_tx_ip_avl associatedClock if_tx_clk
-  set_interface_property if_tx_ip_avl associatedReset if_tx_rstn
-  set_interface_property if_tx_ip_avl dataBitsPerSymbol [expr ($p_num_of_tx_lanes*32)]
+  if {$p_num_of_tx_lanes > 0} {
+
+    ad_alt_intf clock   tx_clk              input   1
+    ad_alt_intf reset-n tx_rstn             output  1 if_tx_clk s_axi_reset
+    ad_alt_intf signal  tx_ext_sysref_in    input   1
+    ad_alt_intf signal  tx_ext_sysref_out   output  1
+    ad_alt_intf signal  tx_sync             input   1
+    ad_alt_intf signal  tx_data             input   $p_num_of_tx_lanes*32  data
+    ad_alt_intf signal  tx_ready            input   $p_num_of_tx_lanes tx_ready
+    ad_alt_intf signal  tx_ip_sysref        output  1 export
+    ad_alt_intf signal  tx_ip_sync          output  1 export
+
+    add_interface if_tx_ip_avl avalon_streaming source
+    add_interface_port if_tx_ip_avl tx_ip_data  data  output $p_num_of_tx_lanes*32
+    add_interface_port if_tx_ip_avl tx_ip_valid valid output 1
+    add_interface_port if_tx_ip_avl tx_ip_ready ready input 1
+
+    set_interface_property if_tx_ip_avl associatedClock if_tx_clk
+    set_interface_property if_tx_ip_avl associatedReset if_tx_rstn
+    set_interface_property if_tx_ip_avl dataBitsPerSymbol [expr ($p_num_of_tx_lanes*32)]
+  }
 }
 

From 0d1c4d232eb6e8f644aeae0093167036ed4d1627 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 20 May 2016 16:14:57 -0400
Subject: [PATCH 227/972] a10soc- updates-1

---
 projects/adrv9371x/a10soc/system_bd.qsys     |    0
 projects/adrv9371x/a10soc/system_constr.sdc  |    3 +-
 projects/adrv9371x/a10soc/system_project.tcl |    2 +-
 projects/adrv9371x/common/adrv9371x_bd.qsys  | 1214 ++++++++++++++++++
 4 files changed, 1217 insertions(+), 2 deletions(-)
 mode change 100755 => 100644 projects/adrv9371x/a10soc/system_bd.qsys
 create mode 100755 projects/adrv9371x/common/adrv9371x_bd.qsys

diff --git a/projects/adrv9371x/a10soc/system_bd.qsys b/projects/adrv9371x/a10soc/system_bd.qsys
old mode 100755
new mode 100644
diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc
index 1f9b3d462..ddbb2743c 100644
--- a/projects/adrv9371x/a10soc/system_constr.sdc
+++ b/projects/adrv9371x/a10soc/system_constr.sdc
@@ -1,6 +1,7 @@
 
 create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
-create_clock -period  "4.000 ns"  -name rx_clk_250mhz       [get_ports {rx_clk_in}]
+create_clock -period  "8.139 ns"  -name ref_clk0_122mhz     [get_ports {ref_clk0}]
+create_clock -period  "8.139 ns"  -name ref_clk1_122mhz     [get_ports {ref_clk1}]
 
 derive_pll_clocks
 derive_clock_uncertainty
diff --git a/projects/adrv9371x/a10soc/system_project.tcl b/projects/adrv9371x/a10soc/system_project.tcl
index 1dceee79f..7dd47698b 100644
--- a/projects/adrv9371x/a10soc/system_project.tcl
+++ b/projects/adrv9371x/a10soc/system_project.tcl
@@ -2,7 +2,7 @@
 load_package flow
 
 source ../../scripts/adi_env.tcl
-project_new fmcomms2_a10soc -overwrite
+project_new adrv9371x_a10soc -overwrite
 
 source "../../common/a10soc/a10soc_system_assign.tcl"
 
diff --git a/projects/adrv9371x/common/adrv9371x_bd.qsys b/projects/adrv9371x/common/adrv9371x_bd.qsys
new file mode 100755
index 000000000..03dab1a9e
--- /dev/null
+++ b/projects/adrv9371x/common/adrv9371x_bd.qsys
@@ -0,0 +1,1214 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element adc_pack
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element avl_xcvr_os_rx
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element avl_xcvr_rx
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element avl_xcvr_tx
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element axi_ad9371
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element axi_dmac_adc
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_dmac_adc.s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element axi_dmac_dac
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_dmac_dac.s_axi
+   {
+      datum baseAddress
+      {
+         value = "16384";
+         type = "String";
+      }
+   }
+   element axi_jesd_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element dac_upack
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element rstcntrl_xcvr_tx
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_rst
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element xcvr_pll
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element xcvr_pll_reconfig
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element xcvr_ref_clk
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="10AS066N3F40E2SGE2" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="avl_xcvr_os_rx"
+   internal="avl_xcvr_os_rx.reconfig_avmm"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_xcvr_pll"
+   internal="xcvr_pll_reconfig.mgmt_avalon_slave"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_xcvr_rx"
+   internal="avl_xcvr_rx.reconfig_avmm"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_xcvr_tx"
+   internal="avl_xcvr_tx.jesd204_tx_avs"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="axi_dmac_adc_fifo_wr_clock"
+   internal="axi_dmac_adc.fifo_wr_clock" />
+ <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
+ <interface
+   name="axi_dmac_adc_intr"
+   internal="axi_dmac_adc.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_dmac_adc_m_dest_axi"
+   internal="axi_dmac_adc.m_dest_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_dmac_adc_s_axi"
+   internal="axi_dmac_adc.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_dmac_dac_fifo_rd_clock"
+   internal="axi_dmac_dac.fifo_rd_clock" />
+ <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
+ <interface
+   name="axi_dmac_dac_intr"
+   internal="axi_dmac_dac.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_dmac_dac_m_src_axi"
+   internal="axi_dmac_dac.m_src_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_dmac_dac_s_axi"
+   internal="axi_dmac_dac.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_jesd_xcvr"
+   internal="axi_jesd_xcvr.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="rx_sysref"
+   internal="avl_xcvr_rx.sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
+ <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
+ <interface
+   name="tx_sync"
+   internal="axi_jesd_xcvr.if_tx_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="tx_sysref"
+   internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="xcvr_ref_clk"
+   internal="xcvr_ref_clk.in_clk"
+   type="clock"
+   dir="end" />
+ <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <module
+   name="avl_xcvr_os_rx"
+   kind="altera_jesd204"
+   version="15.1"
+   enabled="1">
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="BID" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="CS" value="0" />
+  <parameter name="DATA_PATH" value="RX" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DID" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
+  <parameter name="GUI_CFG_F" value="4" />
+  <parameter name="GUI_EN_CFG_F" value="false" />
+  <parameter name="HD" value="0" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="K" value="16" />
+  <parameter name="L" value="2" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="M" value="2" />
+  <parameter name="N" value="16" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="REFCLK_FREQ" value="122.88" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="S" value="1" />
+  <parameter name="SCR" value="1" />
+  <parameter name="SUBCLASSV" value="1" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="bonded_mode" value="bonded" />
+  <parameter name="lane_rate" value="4915.2" />
+  <parameter name="part_trait_bd" value="NIGHTFURY4" />
+  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
+  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="rcfg_jtag_enable" value="false" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="set_capability_reg_enable" value="true" />
+  <parameter name="set_csr_soft_logic_enable" value="true" />
+  <parameter name="set_prbs_soft_logic_enable" value="false" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="wrapper_opt" value="base_phy" />
+ </module>
+ <module name="avl_xcvr_rx" kind="altera_jesd204" version="15.1" enabled="1">
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="BID" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="CS" value="0" />
+  <parameter name="DATA_PATH" value="RX" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DID" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
+  <parameter name="GUI_CFG_F" value="4" />
+  <parameter name="GUI_EN_CFG_F" value="false" />
+  <parameter name="HD" value="0" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="K" value="16" />
+  <parameter name="L" value="2" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="M" value="4" />
+  <parameter name="N" value="16" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="REFCLK_FREQ" value="122.88" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="S" value="1" />
+  <parameter name="SCR" value="1" />
+  <parameter name="SUBCLASSV" value="1" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="bonded_mode" value="bonded" />
+  <parameter name="lane_rate" value="4915.2" />
+  <parameter name="part_trait_bd" value="NIGHTFURY4" />
+  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
+  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="rcfg_jtag_enable" value="false" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="set_capability_reg_enable" value="true" />
+  <parameter name="set_csr_soft_logic_enable" value="false" />
+  <parameter name="set_prbs_soft_logic_enable" value="false" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="wrapper_opt" value="base_phy" />
+ </module>
+ <module name="avl_xcvr_tx" kind="altera_jesd204" version="15.1" enabled="1">
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="BID" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="CS" value="0" />
+  <parameter name="DATA_PATH" value="TX" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DID" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
+  <parameter name="GUI_CFG_F" value="4" />
+  <parameter name="GUI_EN_CFG_F" value="false" />
+  <parameter name="HD" value="0" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="K" value="32" />
+  <parameter name="L" value="4" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="M" value="4" />
+  <parameter name="N" value="16" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="REFCLK_FREQ" value="125.0" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="S" value="1" />
+  <parameter name="SCR" value="1" />
+  <parameter name="SUBCLASSV" value="1" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="bonded_mode" value="bonded" />
+  <parameter name="lane_rate" value="4915.2" />
+  <parameter name="part_trait_bd" value="NIGHTFURY4" />
+  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
+  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="rcfg_jtag_enable" value="false" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="set_capability_reg_enable" value="false" />
+  <parameter name="set_csr_soft_logic_enable" value="true" />
+  <parameter name="set_prbs_soft_logic_enable" value="false" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="wrapper_opt" value="base_phy" />
+ </module>
+ <module name="axi_ad9371" kind="axi_ad9371" version="1.0" enabled="1">
+  <parameter name="ADC_DATAPATH_DISABLE" value="0" />
+  <parameter name="DAC_DATAPATH_DISABLE" value="0" />
+  <parameter name="ID" value="0" />
+ </module>
+ <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="0" />
+  <parameter name="DMA_TYPE_SRC" value="2" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
+ </module>
+ <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="1" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="2" />
+  <parameter name="DMA_TYPE_SRC" value="0" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="0" />
+ </module>
+ <module name="axi_jesd_xcvr" kind="axi_jesd_xcvr" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="0" />
+  <parameter name="RX_NUM_OF_LANES" value="2" />
+  <parameter name="TX_NUM_OF_LANES" value="4" />
+ </module>
+ <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <module
+   name="rstcntrl_xcvr_tx"
+   kind="altera_xcvr_reset_control"
+   version="15.1"
+   enabled="1">
+  <parameter name="CHANNELS" value="4" />
+  <parameter name="PLLS" value="1" />
+  <parameter name="REDUCED_SIM_TIME" value="1" />
+  <parameter name="RX_ENABLE" value="0" />
+  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+  <parameter name="SYNCHRONIZE_RESET" value="1" />
+  <parameter name="SYS_CLK_IN_MHZ" value="100" />
+  <parameter name="TX_ENABLE" value="1" />
+  <parameter name="TX_PER_CHANNEL" value="0" />
+  <parameter name="TX_PLL_ENABLE" value="1" />
+  <parameter name="T_PLL_LOCK_HYST" value="0" />
+  <parameter name="T_PLL_POWERDOWN" value="1000" />
+  <parameter name="T_RX_ANALOGRESET" value="40" />
+  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_ANALOGRESET" value="0" />
+  <parameter name="T_TX_DIGITALRESET" value="20" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="gui_pll_cal_busy" value="0" />
+  <parameter name="gui_rx_auto_reset" value="0" />
+  <parameter name="gui_split_interfaces" value="0" />
+  <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="xcvr_pll" kind="altera_iopll" version="15.1" enabled="1">
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_duty_cycle0" value="50.0" />
+  <parameter name="gui_actual_duty_cycle1" value="50.0" />
+  <parameter name="gui_actual_duty_cycle10" value="50.0" />
+  <parameter name="gui_actual_duty_cycle11" value="50.0" />
+  <parameter name="gui_actual_duty_cycle12" value="50.0" />
+  <parameter name="gui_actual_duty_cycle13" value="50.0" />
+  <parameter name="gui_actual_duty_cycle14" value="50.0" />
+  <parameter name="gui_actual_duty_cycle15" value="50.0" />
+  <parameter name="gui_actual_duty_cycle16" value="50.0" />
+  <parameter name="gui_actual_duty_cycle17" value="50.0" />
+  <parameter name="gui_actual_duty_cycle2" value="50.0" />
+  <parameter name="gui_actual_duty_cycle3" value="50.0" />
+  <parameter name="gui_actual_duty_cycle4" value="50.0" />
+  <parameter name="gui_actual_duty_cycle5" value="50.0" />
+  <parameter name="gui_actual_duty_cycle6" value="50.0" />
+  <parameter name="gui_actual_duty_cycle7" value="50.0" />
+  <parameter name="gui_actual_duty_cycle8" value="50.0" />
+  <parameter name="gui_actual_duty_cycle9" value="50.0" />
+  <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_actual_phase_shift0" value="0.0" />
+  <parameter name="gui_actual_phase_shift1" value="0.0" />
+  <parameter name="gui_actual_phase_shift10" value="0.0" />
+  <parameter name="gui_actual_phase_shift11" value="0.0" />
+  <parameter name="gui_actual_phase_shift12" value="0.0" />
+  <parameter name="gui_actual_phase_shift13" value="0.0" />
+  <parameter name="gui_actual_phase_shift14" value="0.0" />
+  <parameter name="gui_actual_phase_shift15" value="0.0" />
+  <parameter name="gui_actual_phase_shift16" value="0.0" />
+  <parameter name="gui_actual_phase_shift17" value="0.0" />
+  <parameter name="gui_actual_phase_shift2" value="0.0" />
+  <parameter name="gui_actual_phase_shift3" value="0.0" />
+  <parameter name="gui_actual_phase_shift4" value="0.0" />
+  <parameter name="gui_actual_phase_shift5" value="0.0" />
+  <parameter name="gui_actual_phase_shift6" value="0.0" />
+  <parameter name="gui_actual_phase_shift7" value="0.0" />
+  <parameter name="gui_actual_phase_shift8" value="0.0" />
+  <parameter name="gui_actual_phase_shift9" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_clock_name_global0" value="false" />
+  <parameter name="gui_clock_name_global1" value="false" />
+  <parameter name="gui_clock_name_global10" value="false" />
+  <parameter name="gui_clock_name_global11" value="false" />
+  <parameter name="gui_clock_name_global12" value="false" />
+  <parameter name="gui_clock_name_global13" value="false" />
+  <parameter name="gui_clock_name_global14" value="false" />
+  <parameter name="gui_clock_name_global15" value="false" />
+  <parameter name="gui_clock_name_global16" value="false" />
+  <parameter name="gui_clock_name_global17" value="false" />
+  <parameter name="gui_clock_name_global2" value="false" />
+  <parameter name="gui_clock_name_global3" value="false" />
+  <parameter name="gui_clock_name_global4" value="false" />
+  <parameter name="gui_clock_name_global5" value="false" />
+  <parameter name="gui_clock_name_global6" value="false" />
+  <parameter name="gui_clock_name_global7" value="false" />
+  <parameter name="gui_clock_name_global8" value="false" />
+  <parameter name="gui_clock_name_global9" value="false" />
+  <parameter name="gui_clock_name_string0" value="tx_dac_clk" />
+  <parameter name="gui_clock_name_string1" value="rx_adc_clk" />
+  <parameter name="gui_clock_name_string10" value="outclk10" />
+  <parameter name="gui_clock_name_string11" value="outclk11" />
+  <parameter name="gui_clock_name_string12" value="outclk12" />
+  <parameter name="gui_clock_name_string13" value="outclk13" />
+  <parameter name="gui_clock_name_string14" value="outclk14" />
+  <parameter name="gui_clock_name_string15" value="outclk15" />
+  <parameter name="gui_clock_name_string16" value="outclk16" />
+  <parameter name="gui_clock_name_string17" value="outclk17" />
+  <parameter name="gui_clock_name_string2" value="rx_adc_os_clk" />
+  <parameter name="gui_clock_name_string3" value="outclk3" />
+  <parameter name="gui_clock_name_string4" value="outclk4" />
+  <parameter name="gui_clock_name_string5" value="outclk5" />
+  <parameter name="gui_clock_name_string6" value="outclk6" />
+  <parameter name="gui_clock_name_string7" value="outclk7" />
+  <parameter name="gui_clock_name_string8" value="outclk8" />
+  <parameter name="gui_clock_name_string9" value="outclk9" />
+  <parameter name="gui_device_speed_grade" value="1" />
+  <parameter name="gui_divide_factor_c0" value="6" />
+  <parameter name="gui_divide_factor_c1" value="6" />
+  <parameter name="gui_divide_factor_c10" value="6" />
+  <parameter name="gui_divide_factor_c11" value="6" />
+  <parameter name="gui_divide_factor_c12" value="6" />
+  <parameter name="gui_divide_factor_c13" value="6" />
+  <parameter name="gui_divide_factor_c14" value="6" />
+  <parameter name="gui_divide_factor_c15" value="6" />
+  <parameter name="gui_divide_factor_c16" value="6" />
+  <parameter name="gui_divide_factor_c17" value="6" />
+  <parameter name="gui_divide_factor_c2" value="6" />
+  <parameter name="gui_divide_factor_c3" value="6" />
+  <parameter name="gui_divide_factor_c4" value="6" />
+  <parameter name="gui_divide_factor_c5" value="6" />
+  <parameter name="gui_divide_factor_c6" value="6" />
+  <parameter name="gui_divide_factor_c7" value="6" />
+  <parameter name="gui_divide_factor_c8" value="6" />
+  <parameter name="gui_divide_factor_c9" value="6" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50.0" />
+  <parameter name="gui_duty_cycle1" value="50.0" />
+  <parameter name="gui_duty_cycle10" value="50.0" />
+  <parameter name="gui_duty_cycle11" value="50.0" />
+  <parameter name="gui_duty_cycle12" value="50.0" />
+  <parameter name="gui_duty_cycle13" value="50.0" />
+  <parameter name="gui_duty_cycle14" value="50.0" />
+  <parameter name="gui_duty_cycle15" value="50.0" />
+  <parameter name="gui_duty_cycle16" value="50.0" />
+  <parameter name="gui_duty_cycle17" value="50.0" />
+  <parameter name="gui_duty_cycle2" value="50.0" />
+  <parameter name="gui_duty_cycle3" value="50.0" />
+  <parameter name="gui_duty_cycle4" value="50.0" />
+  <parameter name="gui_duty_cycle5" value="50.0" />
+  <parameter name="gui_duty_cycle6" value="50.0" />
+  <parameter name="gui_duty_cycle7" value="50.0" />
+  <parameter name="gui_duty_cycle8" value="50.0" />
+  <parameter name="gui_duty_cycle9" value="50.0" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_extclkout_ports" value="false" />
+  <parameter name="gui_en_lvds_ports" value="Disabled" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="true" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_enable_output_counter_cascading" value="false" />
+  <parameter name="gui_extclkout_0_source" value="C0" />
+  <parameter name="gui_extclkout_1_source" value="C0" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_fix_vco_frequency" value="false" />
+  <parameter name="gui_fixed_vco_frequency" value="600.0" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="6" />
+  <parameter name="gui_number_of_clocks" value="3" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_output_clock_frequency0" value="122.88" />
+  <parameter name="gui_output_clock_frequency1" value="122.88" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="122.88" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0.0" />
+  <parameter name="gui_phase_shift1" value="0.0" />
+  <parameter name="gui_phase_shift10" value="0.0" />
+  <parameter name="gui_phase_shift11" value="0.0" />
+  <parameter name="gui_phase_shift12" value="0.0" />
+  <parameter name="gui_phase_shift13" value="0.0" />
+  <parameter name="gui_phase_shift14" value="0.0" />
+  <parameter name="gui_phase_shift15" value="0.0" />
+  <parameter name="gui_phase_shift16" value="0.0" />
+  <parameter name="gui_phase_shift17" value="0.0" />
+  <parameter name="gui_phase_shift2" value="0.0" />
+  <parameter name="gui_phase_shift3" value="0.0" />
+  <parameter name="gui_phase_shift4" value="0.0" />
+  <parameter name="gui_phase_shift5" value="0.0" />
+  <parameter name="gui_phase_shift6" value="0.0" />
+  <parameter name="gui_phase_shift7" value="0.0" />
+  <parameter name="gui_phase_shift8" value="0.0" />
+  <parameter name="gui_phase_shift9" value="0.0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="false" />
+  <parameter name="gui_pll_bandwidth_preset" value="Low" />
+  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="122.88" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_NDFB_modes" value="false" />
+  <parameter name="gui_use_locked" value="false" />
+  <parameter name="gui_vco_frequency" value="600.0" />
+  <parameter name="system_info_device_component" value="10AS066N3F40E2SGE2" />
+  <parameter name="system_info_device_family" value="Arria 10" />
+  <parameter name="system_info_device_speed_grade" value="2" />
+  <parameter name="system_part_trait_speed_grade" value="2" />
+ </module>
+ <module
+   name="xcvr_pll_reconfig"
+   kind="altera_pll_reconfig"
+   version="15.1"
+   enabled="1">
+  <parameter name="ENABLE_BYTEENABLE" value="false" />
+  <parameter name="ENABLE_MIF" value="false" />
+  <parameter name="MIF_FILE_NAME" value="" />
+  <parameter name="device_family" value="Arria 10" />
+ </module>
+ <module
+   name="xcvr_ref_clk"
+   kind="altera_clock_bridge"
+   version="15.1"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <connection
+   kind="avalon_streaming"
+   version="15.1"
+   start="axi_jesd_xcvr.if_tx_ip_avl"
+   end="avl_xcvr_tx.jesd204_tx_link" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="rstcntrl_xcvr_tx.clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="avl_xcvr_tx.jesd204_tx_avs_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_dmac_adc.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_dmac_dac.m_src_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_pll_reconfig.mgmt_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="avl_xcvr_os_rx.reconfig_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="avl_xcvr_rx.reconfig_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_ref_clk.out_clk"
+   end="xcvr_pll.refclk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_dmac_adc.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_dmac_dac.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_jesd_xcvr.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk0"
+   end="axi_jesd_xcvr.if_tx_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk0"
+   end="avl_xcvr_tx.txlink_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk1"
+   end="adc_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk1"
+   end="axi_jesd_xcvr.if_rx_clk" />
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="avl_xcvr_tx.dev_sync_n"
+   end="avl_xcvr_tx.mdev_sync_n">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_pack.if_adc_data"
+   end="axi_dmac_adc.if_fifo_wr_din">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_pack.if_adc_sync"
+   end="axi_dmac_adc.if_fifo_wr_sync">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_pack.if_adc_valid"
+   end="axi_dmac_adc.if_fifo_wr_en">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="dac_upack.if_dac_data"
+   end="axi_dmac_dac.if_fifo_rd_dout">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="dac_upack.if_dma_xfer_in"
+   end="axi_dmac_dac.if_fifo_rd_xfer_req">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_dmac_dac.if_fifo_rd_en"
+   end="dac_upack.if_dac_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_jesd_xcvr.if_tx_ip_sync"
+   end="avl_xcvr_tx.sync_n">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_jesd_xcvr.if_tx_ip_sysref"
+   end="avl_xcvr_tx.sysref">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_pll_reconfig.reconfig_from_pll"
+   end="xcvr_pll.reconfig_from_pll">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_pll_reconfig.reconfig_to_pll"
+   end="xcvr_pll.reconfig_to_pll">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="15.1"
+   start="axi_jesd_xcvr.if_rst"
+   end="rstcntrl_xcvr_tx.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="axi_jesd_xcvr.if_tx_rstn"
+   end="avl_xcvr_tx.txlink_rst_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="adc_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="avl_xcvr_tx.jesd204_tx_avs_rst_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_dmac_adc.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_dmac_dac.m_src_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_pll_reconfig.mgmt_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="avl_xcvr_os_rx.reconfig_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="avl_xcvr_rx.reconfig_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_pll.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_dmac_adc.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_dmac_dac.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_jesd_xcvr.s_axi_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+ <interconnectRequirement
+   for="mm_interconnect_0|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_2|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+</system>

From d254fa841b724fdc1f90baa8fc8f2c23dacee595 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 23 May 2016 10:55:07 -0400
Subject: [PATCH 228/972] library- altera updates

---
 library/axi_ad9144/axi_ad9144_hw.tcl     | 47 +++++++++++++++---------
 library/axi_ad9680/axi_ad9680_hw.tcl     | 26 ++++++++-----
 library/util_adcfifo/util_adcfifo_hw.tcl |  2 +-
 3 files changed, 46 insertions(+), 29 deletions(-)

diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl
index 2844d5a5d..eb28df04f 100755
--- a/library/axi_ad9144/axi_ad9144_hw.tcl
+++ b/library/axi_ad9144/axi_ad9144_hw.tcl
@@ -90,18 +90,24 @@ ad_alt_intf signal  tx_data       output  128*(QUAD_OR_DUAL_N+1) data
 
 ad_alt_intf clock   dac_clk       output  1
 
-add_interface fifo_ch_0_out conduit end
-add_interface_port fifo_ch_0_out  dac_enable_0  enable   Output  1
-add_interface_port fifo_ch_0_out  dac_valid_0   valid    Output  1
-add_interface_port fifo_ch_0_out  dac_data_0    data     Input   64
+add_interface dac_ch_0 conduit end
+add_interface_port dac_ch_0  dac_enable_0  enable   Output  1
+add_interface_port dac_ch_0  dac_valid_0   valid    Output  1
+add_interface_port dac_ch_0  dac_ddata_0   data     Input   64
 
-add_interface fifo_ch_1_out conduit end
-add_interface_port fifo_ch_1_out  dac_enable_1  enable   Output  1
-add_interface_port fifo_ch_1_out  dac_valid_1   valid    Output  1
-add_interface_port fifo_ch_1_out  dac_data_1    data     Input   64
+set_interface_property dac_ch_0 associatedClock if_tx_clk
+set_interface_property dac_ch_0 associatedReset none
 
-ad_alt_intf signal  dac_dovf      input   1
-ad_alt_intf signal  dac_dunf      input   1
+add_interface dac_ch_1 conduit end
+add_interface_port dac_ch_1  dac_enable_1  enable   Output  1
+add_interface_port dac_ch_1  dac_valid_1   valid    Output  1
+add_interface_port dac_ch_1  dac_ddata_1   data     Input   64
+
+set_interface_property dac_ch_1 associatedClock if_tx_clk
+set_interface_property dac_ch_1 associatedReset none
+
+ad_alt_intf signal  dac_dovf      input   1 ovf
+ad_alt_intf signal  dac_dunf      input   1 unf
 
 proc p_axi_ad9144 {} {
 
@@ -109,15 +115,20 @@ proc p_axi_ad9144 {} {
 
   if {[get_parameter_value QUAD_OR_DUAL_N] == 1} {
 
-    add_interface fifo_ch_2_out conduit end
-    add_interface_port fifo_ch_2_out  dac_enable_2  enable   Output  1
-    add_interface_port fifo_ch_2_out  dac_valid_2   valid    Output  1
-    add_interface_port fifo_ch_2_out  dac_data_2    data     Input   64
+    add_interface dac_ch_2 conduit end
+    add_interface_port dac_ch_2  dac_enable_2  enable   Output  1
+    add_interface_port dac_ch_2  dac_valid_2   valid    Output  1
+    add_interface_port dac_ch_2  dac_ddata_2   data     Input   64
 
-    add_interface fifo_ch_3_out conduit end
-    add_interface_port fifo_ch_3_out  dac_enable_3  enable   Output  1
-    add_interface_port fifo_ch_3_out  dac_valid_3   valid    Output  1
-    add_interface_port fifo_ch_3_out  dac_data_3    data     Input   64
+    set_interface_property dac_ch_2 associatedClock if_tx_clk
+    set_interface_property dac_ch_2 associatedReset none
 
+    add_interface dac_ch_3 conduit end
+    add_interface_port dac_ch_3  dac_enable_3  enable   Output  1
+    add_interface_port dac_ch_3  dac_valid_3   valid    Output  1
+    add_interface_port dac_ch_3  dac_ddata_3   data     Input   64
+
+    set_interface_property dac_ch_3 associatedClock if_tx_clk
+    set_interface_property dac_ch_3 associatedReset none
   }
 }
diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl
index 4a91fa68c..b103f2d9c 100755
--- a/library/axi_ad9680/axi_ad9680_hw.tcl
+++ b/library/axi_ad9680/axi_ad9680_hw.tcl
@@ -80,16 +80,22 @@ ad_alt_intf signal  rx_data       input   128 data
 
 ad_alt_intf clock   adc_clock     output  1
 
-add_interface fifo_ch_0 conduit end
-add_interface_port fifo_ch_0  adc_enable_0  enable   Output  1
-add_interface_port fifo_ch_0  adc_valid_0   valid    Output  1
-add_interface_port fifo_ch_0  adc_data_0    data     Output  64
+add_interface adc_ch_0 conduit end
+add_interface_port adc_ch_0  adc_enable_0  enable   Output  1
+add_interface_port adc_ch_0  adc_valid_0   valid    Output  1
+add_interface_port adc_ch_0  adc_data_0    data     Output  64
 
-add_interface fifo_ch_1 conduit end
-add_interface_port fifo_ch_1  adc_enable_1  enable   Output  1
-add_interface_port fifo_ch_1  adc_valid_1   valid    Output  1
-add_interface_port fifo_ch_1  adc_data_1    data     Output  64
+set_interface_property adc_ch_0 associatedClock if_rx_clk
+set_interface_property adc_ch_0 associatedReset none
 
-ad_alt_intf signal  adc_dovf      input   1
-ad_alt_intf signal  adc_dunf      input   1
+add_interface adc_ch_1 conduit end
+add_interface_port adc_ch_1  adc_enable_1  enable   Output  1
+add_interface_port adc_ch_1  adc_valid_1   valid    Output  1
+add_interface_port adc_ch_1  adc_data_1    data     Output  64
+
+set_interface_property adc_ch_1 associatedClock if_rx_clk
+set_interface_property adc_ch_1 associatedReset none
+
+ad_alt_intf signal  adc_dovf      input   1 ovf
+ad_alt_intf signal  adc_dunf      input   1 unf
 
diff --git a/library/util_adcfifo/util_adcfifo_hw.tcl b/library/util_adcfifo/util_adcfifo_hw.tcl
index 95cc93bcc..73784bf58 100755
--- a/library/util_adcfifo/util_adcfifo_hw.tcl
+++ b/library/util_adcfifo/util_adcfifo_hw.tcl
@@ -57,7 +57,7 @@ ad_alt_intf clock   adc_clk         input   1               adc_clk
 ad_alt_intf reset   adc_rst         input   1               if_adc_clk
 ad_alt_intf signal  adc_wr          input   1               valid
 ad_alt_intf signal  adc_wdata       input   ADC_DATA_WIDTH  data
-ad_alt_intf signal  adc_wovf        output  1               adc_dovf
+ad_alt_intf signal  adc_wovf        output  1               ovf
 
 ad_alt_intf clock   dma_clk           input   1                 clk
 ad_alt_intf signal  dma_wr            output  1                 valid

From 39d23032f18fdacfe2db06e5ad4a79b1807db2bf Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 23 May 2016 10:55:44 -0400
Subject: [PATCH 229/972] daq2- qsys updates

---
 projects/common/a10gx/a10gx_system_bd.qsys |  2 +-
 projects/daq2/common/daq2_bd.qsys          | 52 ++++++++++++++++++++--
 2 files changed, 49 insertions(+), 5 deletions(-)

diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys
index 9cb193b00..7bdd08068 100644
--- a/projects/common/a10gx/a10gx_system_bd.qsys
+++ b/projects/common/a10gx/a10gx_system_bd.qsys
@@ -803,7 +803,7 @@
   <parameter name="mmu_TLBMissExcOffset" value="4096" />
   <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
   <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="true" />
+  <parameter name="mmu_enabled" value="false" />
   <parameter name="mmu_processIDNumBits" value="8" />
   <parameter name="mmu_ramBlockType" value="Automatic" />
   <parameter name="mmu_tlbNumWays" value="16" />
diff --git a/projects/daq2/common/daq2_bd.qsys b/projects/daq2/common/daq2_bd.qsys
index d61b9f7ba..3bd3eaf0d 100755
--- a/projects/daq2/common/daq2_bd.qsys
+++ b/projects/daq2/common/daq2_bd.qsys
@@ -1880,6 +1880,28 @@
    version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="xcvr_core.txlink_clk" />
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9680_core.adc_ch_0"
+   end="util_cpack_0.adc_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9680_core.adc_ch_1"
+   end="util_cpack_0.adc_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.1"
@@ -1894,8 +1916,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_ad9680_core.fifo_ch_0"
-   end="util_cpack_0.fifo_ch_0">
+   start="axi_ad9144_core.dac_ch_0"
+   end="util_upack_0.dac_ch_0">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1905,8 +1927,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="util_cpack_0.fifo_ch_1"
-   end="axi_ad9680_core.fifo_ch_1">
+   start="axi_ad9144_core.dac_ch_1"
+   end="util_upack_0.dac_ch_1">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1935,6 +1957,17 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="ad9680_adcfifo.if_adc_wovf"
+   end="axi_ad9680_core.if_adc_dovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.1"
@@ -2001,6 +2034,17 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9144_dma.if_fifo_rd_underflow"
+   end="axi_ad9144_core.if_dac_dunf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.1"

From 05ac271aff9d1bf411974124681270a66ea20ba4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 24 May 2016 03:15:24 -0400
Subject: [PATCH 230/972] daq3/a10gx- qsys modifications

---
 library/axi_ad9152/axi_ad9152_hw.tcl | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl
index 27c96ffd0..e2642f384 100755
--- a/library/axi_ad9152/axi_ad9152_hw.tcl
+++ b/library/axi_ad9152/axi_ad9152_hw.tcl
@@ -82,15 +82,21 @@ ad_alt_intf signal  tx_data       output  128 data
 
 ad_alt_intf clock   dac_clk       output  1
 
-add_interface fifo_ch_0_out conduit end
-add_interface_port fifo_ch_0_out  dac_enable_0  enable   Output  1
-add_interface_port fifo_ch_0_out  dac_valid_0   valid    Output  1
-add_interface_port fifo_ch_0_out  dac_ddata_0   data     Input   64
+add_interface dac_ch_0 conduit end
+add_interface_port dac_ch_0  dac_enable_0  enable   Output  1
+add_interface_port dac_ch_0  dac_valid_0   valid    Output  1
+add_interface_port dac_ch_0  dac_ddata_0   data     Input   64
 
-add_interface fifo_ch_1_out conduit end
-add_interface_port fifo_ch_1_out  dac_enable_1  enable   Output  1
-add_interface_port fifo_ch_1_out  dac_valid_1   valid    Output  1
-add_interface_port fifo_ch_1_out  dac_ddata_1   data     Input   64
+set_interface_property dac_ch_0 associatedClock if_tx_clk
+set_interface_property dac_ch_0 associatedReset none
+
+add_interface dac_ch_1 conduit end
+add_interface_port dac_ch_1  dac_enable_1  enable   Output  1
+add_interface_port dac_ch_1  dac_valid_1   valid    Output  1
+add_interface_port dac_ch_1  dac_ddata_1   data     Input   64
+
+set_interface_property dac_ch_1 associatedClock if_tx_clk
+set_interface_property dac_ch_1 associatedReset none
 
 ad_alt_intf signal  dac_dovf      input   1 ovf
 ad_alt_intf signal  dac_dunf      input   1 unf

From 9c6e80fca291c7c230278c4f2e9f707c644dfcb3 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 24 May 2016 03:15:45 -0400
Subject: [PATCH 231/972] daq3/a10gx- qsys modifications

---
 projects/daq3/common/daq3_bd.qsys | 294 +++++++++++++++---------------
 1 file changed, 151 insertions(+), 143 deletions(-)

diff --git a/projects/daq3/common/daq3_bd.qsys b/projects/daq3/common/daq3_bd.qsys
index 8edbb937f..9e7961940 100755
--- a/projects/daq3/common/daq3_bd.qsys
+++ b/projects/daq3/common/daq3_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
    element ad9680_adcfifo
    {
       datum _sortIndex
@@ -729,7 +721,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45I2SGE2" />
+ <parameter name="device" value="10AX115S3F45E2SGE3" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -889,24 +881,24 @@
   <parameter name="RX_NUM_OF_LANES" value="4" />
   <parameter name="TX_NUM_OF_LANES" value="4" />
  </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="125000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
   <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
   <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
   <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
@@ -921,10 +913,10 @@
   <parameter name="CHANNEL_DATA_WIDTH" value="64" />
   <parameter name="NUM_OF_CHANNELS" value="2" />
  </module>
- <module name="xcvr_core" kind="altera_jesd204" version="15.0" enabled="1">
+ <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
   <parameter name="ADJCNT" value="0" />
   <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="BID" value="0" />
   <parameter name="CF" value="0" />
@@ -934,6 +926,13 @@
   <parameter name="DID" value="0" />
   <parameter name="DLB_TEST" value="0" />
   <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
   <parameter name="GUI_CFG_F" value="1" />
   <parameter name="GUI_EN_CFG_F" value="true" />
   <parameter name="HD" value="1" />
@@ -965,8 +964,8 @@
   <parameter name="bitrev_en" value="false" />
   <parameter name="bonded_mode" value="non_bonded" />
   <parameter name="lane_rate" value="10000.0" />
-  <parameter name="part_trait_bd" value="NIGHTFURY5ES2" />
-  <parameter name="part_trait_dp" value="10AX115S3F45I2SGE2" />
+  <parameter name="part_trait_bd" value="NIGHTFURY5" />
+  <parameter name="part_trait_dp" value="10AX115S3F45E2SGE3" />
   <parameter name="pll_reconfig_enable" value="false" />
   <parameter name="pll_type" value="CMU" />
   <parameter name="rcfg_jtag_enable" value="false" />
@@ -980,7 +979,7 @@
  <module
    name="xcvr_rst_cntrl"
    kind="altera_xcvr_reset_control"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="CHANNELS" value="4" />
   <parameter name="PLLS" value="1" />
@@ -997,6 +996,7 @@
   <parameter name="T_PLL_POWERDOWN" value="1000" />
   <parameter name="T_RX_ANALOGRESET" value="40" />
   <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_ANALOGRESET" value="0" />
   <parameter name="T_TX_DIGITALRESET" value="20" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="gui_pll_cal_busy" value="1" />
@@ -1004,7 +1004,7 @@
   <parameter name="gui_split_interfaces" value="0" />
   <parameter name="gui_tx_auto_reset" value="0" />
  </module>
- <module name="xcvr_rx_pll" kind="altera_iopll" version="15.0" enabled="1">
+ <module name="xcvr_rx_pll" kind="altera_iopll" version="15.1" enabled="1">
   <parameter name="gui_active_clk" value="false" />
   <parameter name="gui_actual_duty_cycle0" value="50.0" />
   <parameter name="gui_actual_duty_cycle1" value="50.0" />
@@ -1179,7 +1179,7 @@
   <parameter name="gui_en_adv_params" value="false" />
   <parameter name="gui_en_dps_ports" value="false" />
   <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_en_lvds_ports" value="Disabled" />
   <parameter name="gui_en_phout_ports" value="false" />
   <parameter name="gui_en_reconf" value="false" />
   <parameter name="gui_enable_cascade_in" value="false" />
@@ -1279,8 +1279,10 @@
   <parameter name="gui_reference_clock_frequency" value="500.0" />
   <parameter name="gui_switchover_delay" value="0" />
   <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_NDFB_modes" value="false" />
   <parameter name="gui_use_locked" value="false" />
-  <parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
+  <parameter name="gui_vco_frequency" value="600.0" />
+  <parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
   <parameter name="system_info_device_family" value="Arria 10" />
   <parameter name="system_info_device_speed_grade" value="2" />
   <parameter name="system_part_trait_speed_grade" value="2" />
@@ -1288,7 +1290,7 @@
  <module
    name="xcvr_rx_ref_clk"
    kind="altera_clock_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
@@ -1297,14 +1299,15 @@
  <module
    name="xcvr_tx_lane_pll"
    kind="altera_xcvr_atx_pll_a10"
-   version="15.0"
+   version="15.1"
    enabled="1">
-  <parameter name="base_device" value="NIGHTFURY5ES2" />
+  <parameter name="base_device" value="NIGHTFURY5" />
   <parameter name="bw_sel" value="medium" />
-  <parameter name="device" value="10AX115S3F45I2SGE2" />
+  <parameter name="device" value="10AX115S3F45E2SGE3" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="enable_16G_path" value="0" />
   <parameter name="enable_8G_path" value="1" />
+  <parameter name="enable_analog_resets" value="0" />
   <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
   <parameter name="enable_bonding_clks" value="1" />
   <parameter name="enable_cascade_out" value="0" />
@@ -1329,6 +1332,7 @@
   <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
   <parameter name="prot_mode" value="Basic" />
   <parameter name="rcfg_debug" value="0" />
+  <parameter name="rcfg_enable_avmm_busy_port" value="0" />
   <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
   <parameter name="rcfg_h_file_enable" value="0" />
   <parameter name="rcfg_jtag_enable" value="0" />
@@ -1338,6 +1342,7 @@
   <parameter name="rcfg_param_vals2" value="" />
   <parameter name="rcfg_profile_cnt" value="2" />
   <parameter name="rcfg_profile_select" value="1" />
+  <parameter name="rcfg_separate_avmm_busy" value="0" />
   <parameter name="rcfg_sv_file_enable" value="0" />
   <parameter name="rcfg_txt_file_enable" value="0" />
   <parameter name="refclk_cnt" value="1" />
@@ -1351,6 +1356,7 @@
   <parameter name="set_hip_cal_en" value="0" />
   <parameter name="set_k_counter" value="1" />
   <parameter name="set_l_cascade_counter" value="4" />
+  <parameter name="set_l_cascade_predivider" value="1" />
   <parameter name="set_l_counter" value="4" />
   <parameter name="set_m_counter" value="50" />
   <parameter name="set_manual_reference_clock_frequency" value="100.0" />
@@ -1361,7 +1367,7 @@
   <parameter name="support_mode" value="user_mode" />
   <parameter name="test_mode" value="0" />
  </module>
- <module name="xcvr_tx_pll" kind="altera_iopll" version="15.0" enabled="1">
+ <module name="xcvr_tx_pll" kind="altera_iopll" version="15.1" enabled="1">
   <parameter name="gui_active_clk" value="false" />
   <parameter name="gui_actual_duty_cycle0" value="50.0" />
   <parameter name="gui_actual_duty_cycle1" value="50.0" />
@@ -1536,7 +1542,7 @@
   <parameter name="gui_en_adv_params" value="false" />
   <parameter name="gui_en_dps_ports" value="false" />
   <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_en_lvds_ports" value="Disabled" />
   <parameter name="gui_en_phout_ports" value="false" />
   <parameter name="gui_en_reconf" value="false" />
   <parameter name="gui_enable_cascade_in" value="false" />
@@ -1636,8 +1642,10 @@
   <parameter name="gui_reference_clock_frequency" value="500.0" />
   <parameter name="gui_switchover_delay" value="0" />
   <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_NDFB_modes" value="false" />
   <parameter name="gui_use_locked" value="false" />
-  <parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
+  <parameter name="gui_vco_frequency" value="600.0" />
+  <parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
   <parameter name="system_info_device_family" value="Arria 10" />
   <parameter name="system_info_device_speed_grade" value="2" />
   <parameter name="system_part_trait_speed_grade" value="2" />
@@ -1645,7 +1653,7 @@
  <module
    name="xcvr_tx_ref_clk"
    kind="altera_clock_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
@@ -1653,149 +1661,171 @@
  </module>
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_ip_avl"
    end="xcvr_core.jesd204_tx_link" />
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.jesd204_rx_link"
    end="axi_jesd_xcvr.if_rx_ip_avl" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
+ <connection kind="clock" version="15.1" start="mem_clk.out_clk" end="mem_rst.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="xcvr_rst_cntrl.clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="ad9680_adcfifo.if_dma_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_ad9680_dma.if_s_axis_aclk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="xcvr_core.jesd204_rx_avs_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="xcvr_core.jesd204_tx_avs_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_ad9680_dma.m_dest_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_ad9152_dma.m_src_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_ref_clk.out_clk"
    end="xcvr_tx_lane_pll.pll_refclk0" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_ref_clk.out_clk"
    end="xcvr_tx_pll.refclk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_ref_clk.out_clk"
    end="xcvr_rx_pll.refclk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_ref_clk.out_clk"
    end="xcvr_core.rx_pll_ref_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9680_dma.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9680_core.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9152_core.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_jesd_xcvr.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9152_dma.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="util_cpack_0.if_adc_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="ad9680_adcfifo.if_adc_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="util_upack_0.if_dac_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="axi_ad9152_dma.if_fifo_rd_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="axi_ad9680_core.if_rx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="axi_jesd_xcvr.if_rx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="axi_ad9152_core.if_tx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="axi_jesd_xcvr.if_tx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="xcvr_core.rxlink_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="xcvr_core.txlink_clk" />
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
+   start="util_cpack_0.adc_ch_0"
+   end="axi_ad9680_core.adc_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="util_cpack_0.adc_ch_1"
+   end="axi_ad9680_core.adc_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
    start="xcvr_core.alldev_lane_aligned"
    end="xcvr_core.dev_lane_aligned">
   <parameter name="endPort" value="" />
@@ -1806,9 +1836,9 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
-   start="axi_ad9680_core.fifo_ch_0"
-   end="util_cpack_0.fifo_ch_0">
+   version="15.1"
+   start="util_upack_0.dac_ch_0"
+   end="axi_ad9152_core.dac_ch_0">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1817,9 +1847,9 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
-   start="axi_ad9152_core.fifo_ch_0_out"
-   end="util_upack_0.fifo_ch_0">
+   version="15.1"
+   start="axi_ad9152_core.dac_ch_1"
+   end="util_upack_0.dac_ch_1">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1828,29 +1858,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
-   start="util_cpack_0.fifo_ch_1"
-   end="axi_ad9680_core.fifo_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.0"
-   start="axi_ad9152_core.fifo_ch_1_out"
-   end="util_upack_0.fifo_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_0.if_adc_data"
    end="ad9680_adcfifo.if_adc_wdata">
   <parameter name="endPort" value="" />
@@ -1861,7 +1869,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_0.if_adc_valid"
    end="ad9680_adcfifo.if_adc_wr">
   <parameter name="endPort" value="" />
@@ -1872,7 +1880,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_adc_wovf"
    end="axi_ad9680_core.if_adc_dovf">
   <parameter name="endPort" value="" />
@@ -1883,7 +1891,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9152_core.if_dac_dunf"
    end="axi_ad9152_dma.if_fifo_rd_underflow">
   <parameter name="endPort" value="" />
@@ -1894,7 +1902,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_upack_0.if_dac_valid"
    end="axi_ad9152_dma.if_fifo_rd_en">
   <parameter name="endPort" value="" />
@@ -1905,7 +1913,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_dma_wdata"
    end="axi_ad9680_dma.if_s_axis_data">
   <parameter name="endPort" value="" />
@@ -1916,7 +1924,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_dma_wr"
    end="axi_ad9680_dma.if_s_axis_valid">
   <parameter name="endPort" value="" />
@@ -1927,7 +1935,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_dma_wready"
    end="axi_ad9680_dma.if_s_axis_ready">
   <parameter name="endPort" value="" />
@@ -1938,7 +1946,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_dma_xfer_req"
    end="axi_ad9680_dma.if_s_axis_xfer_req">
   <parameter name="endPort" value="" />
@@ -1949,7 +1957,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9152_dma.if_fifo_rd_dout"
    end="util_upack_0.if_dac_data">
   <parameter name="endPort" value="" />
@@ -1960,7 +1968,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9680_core.if_rx_data"
    end="axi_jesd_xcvr.if_rx_data">
   <parameter name="endPort" value="" />
@@ -1971,7 +1979,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ip_sof"
    end="xcvr_core.rx_sof">
   <parameter name="endPort" value="" />
@@ -1982,7 +1990,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ip_sync"
    end="xcvr_core.rx_dev_sync_n">
   <parameter name="endPort" value="" />
@@ -1993,7 +2001,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ip_sysref"
    end="xcvr_core.rx_sysref">
   <parameter name="endPort" value="" />
@@ -2004,7 +2012,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ready"
    end="xcvr_rst_cntrl.rx_ready">
   <parameter name="endPort" value="" />
@@ -2015,7 +2023,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_data"
    end="axi_ad9152_core.if_tx_data">
   <parameter name="endPort" value="" />
@@ -2026,7 +2034,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_ip_sysref"
    end="xcvr_core.tx_sysref">
   <parameter name="endPort" value="" />
@@ -2037,7 +2045,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_ready"
    end="xcvr_rst_cntrl.tx_ready">
   <parameter name="endPort" value="" />
@@ -2048,7 +2056,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.pll_cal_busy"
    end="xcvr_tx_lane_pll.pll_cal_busy">
   <parameter name="endPort" value="" />
@@ -2059,7 +2067,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.pll_locked"
    end="xcvr_rst_cntrl.pll_locked">
   <parameter name="endPort" value="" />
@@ -2070,7 +2078,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.pll_powerdown"
    end="xcvr_rst_cntrl.pll_powerdown">
   <parameter name="endPort" value="" />
@@ -2081,7 +2089,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.rx_analogreset"
    end="xcvr_core.rx_analogreset">
   <parameter name="endPort" value="" />
@@ -2092,7 +2100,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.rx_cal_busy"
    end="xcvr_rst_cntrl.rx_cal_busy">
   <parameter name="endPort" value="" />
@@ -2103,7 +2111,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.rx_digitalreset"
    end="xcvr_rst_cntrl.rx_digitalreset">
   <parameter name="endPort" value="" />
@@ -2114,7 +2122,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.rx_is_lockedtodata"
    end="xcvr_core.rx_islockedtodata">
   <parameter name="endPort" value="" />
@@ -2125,7 +2133,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.sync_n"
    end="axi_jesd_xcvr.if_tx_ip_sync">
   <parameter name="endPort" value="" />
@@ -2136,7 +2144,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.tx_analogreset"
    end="xcvr_core.tx_analogreset">
   <parameter name="endPort" value="" />
@@ -2147,7 +2155,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.tx_cal_busy"
    end="xcvr_core.tx_cal_busy">
   <parameter name="endPort" value="" />
@@ -2158,7 +2166,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.tx_dev_sync_n"
    end="xcvr_core.mdev_sync_n">
   <parameter name="endPort" value="" />
@@ -2169,7 +2177,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.tx_digitalreset"
    end="xcvr_core.tx_digitalreset">
   <parameter name="endPort" value="" />
@@ -2180,127 +2188,127 @@
  </connection>
  <connection
    kind="hssi_serial_clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.tx_serial_clk"
    end="xcvr_core.tx_serial_clk0_ch0" />
  <connection
    kind="hssi_serial_clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.tx_serial_clk"
    end="xcvr_core.tx_serial_clk0_ch1" />
  <connection
    kind="hssi_serial_clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.tx_serial_clk"
    end="xcvr_core.tx_serial_clk0_ch2" />
  <connection
    kind="hssi_serial_clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.tx_serial_clk"
    end="xcvr_core.tx_serial_clk0_ch3" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rst"
    end="xcvr_tx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rst"
    end="xcvr_rx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rst"
    end="xcvr_rst_cntrl.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_rstn"
    end="xcvr_core.rxlink_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_rstn"
    end="xcvr_core.txlink_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="util_cpack_0.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="util_cpack_0.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="ad9680_adcfifo.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="ad9680_adcfifo.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_core.jesd204_rx_avs_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_core.jesd204_tx_avs_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="axi_ad9680_dma.m_dest_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="axi_ad9152_dma.m_src_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_rst_cntrl.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_tx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_rx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_jesd_xcvr.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9152_core.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9680_core.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9680_dma.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9152_dma.s_axi_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

From f10c1e6e93c2091eef9fb7e3ec6a73c878c812ea Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Fri, 27 May 2016 14:04:40 +0300
Subject: [PATCH 232/972] axi_hdmi_tx: Remove hdmi_full_range register

---
 library/axi_hdmi_tx/axi_hdmi_tx.v      | 3 ---
 library/axi_hdmi_tx/axi_hdmi_tx_core.v | 2 --
 library/common/up_hdmi_tx.v            | 9 +--------
 3 files changed, 1 insertion(+), 13 deletions(-)

diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v
index 0c40fcb8f..b0b08b758 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx.v
@@ -187,7 +187,6 @@ module axi_hdmi_tx (
   wire    [13:0]  up_raddr_s;
   wire    [31:0]  up_rdata_s;
   wire            up_rack_s;
-  wire            hdmi_full_range_s;
   wire            hdmi_csc_bypass_s;
   wire            hdmi_ss_bypass_s;
   wire    [ 1:0]  hdmi_srcsel_s;
@@ -258,7 +257,6 @@ module axi_hdmi_tx (
   up_hdmi_tx i_up (
     .hdmi_clk (hdmi_clk),
     .hdmi_rst (hdmi_rst),
-    .hdmi_full_range (hdmi_full_range_s),
     .hdmi_csc_bypass (hdmi_csc_bypass_s),
     .hdmi_ss_bypass (hdmi_ss_bypass_s),
     .hdmi_srcsel (hdmi_srcsel_s),
@@ -346,7 +344,6 @@ module axi_hdmi_tx (
     .vdma_wdata (vdma_wdata_s),
     .vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
     .vdma_fs_waddr (vdma_fs_waddr_s),
-    .hdmi_full_range (hdmi_full_range_s),
     .hdmi_csc_bypass (hdmi_csc_bypass_s),
     .hdmi_ss_bypass (hdmi_ss_bypass_s),
     .hdmi_srcsel (hdmi_srcsel_s),
diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
index ea7442861..8ce7afebf 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
@@ -83,7 +83,6 @@ module axi_hdmi_tx_core (
 
   // processor interface
 
-  hdmi_full_range,
   hdmi_csc_bypass,
   hdmi_ss_bypass,
   hdmi_srcsel,
@@ -151,7 +150,6 @@ module axi_hdmi_tx_core (
 
   // processor interface
 
-  input           hdmi_full_range;
   input           hdmi_csc_bypass;
   input           hdmi_ss_bypass;
   input   [ 1:0]  hdmi_srcsel;
diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v
index 691ce86b2..491524f32 100644
--- a/library/common/up_hdmi_tx.v
+++ b/library/common/up_hdmi_tx.v
@@ -43,7 +43,6 @@ module up_hdmi_tx (
 
   hdmi_clk,
   hdmi_rst,
-  hdmi_full_range,
   hdmi_csc_bypass,
   hdmi_ss_bypass,
   hdmi_srcsel,
@@ -94,7 +93,6 @@ module up_hdmi_tx (
 
   input           hdmi_clk;
   output          hdmi_rst;
-  output          hdmi_full_range;
   output          hdmi_csc_bypass;
   output          hdmi_ss_bypass;
   output  [ 1:0]  hdmi_srcsel;
@@ -142,7 +140,6 @@ module up_hdmi_tx (
   reg             up_wack = 'd0;
   reg     [31:0]  up_scratch = 'd0;
   reg             up_resetn = 'd0;
-  reg             up_full_range = 'd0;
   reg             up_csc_bypass = 'd0;
   reg             up_ss_bypass = 'd0;
   reg     [ 1:0]  up_srcsel = 'd1;
@@ -190,7 +187,6 @@ module up_hdmi_tx (
       up_wack <= 'd0;
       up_scratch <= 'd0;
       up_resetn <= 'd0;
-      up_full_range <= 'd0;
       up_csc_bypass <= 'd0;
       up_ss_bypass <= 'd0;
       up_srcsel <= 'd1;
@@ -222,7 +218,6 @@ module up_hdmi_tx (
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
         up_ss_bypass <= up_wdata[2];
-        up_full_range <= up_wdata[1];
         up_csc_bypass <= up_wdata[0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h012)) begin
@@ -296,7 +291,7 @@ module up_hdmi_tx (
           12'h001: up_rdata <= ID;
           12'h002: up_rdata <= up_scratch;
           12'h010: up_rdata <= {31'd0, up_resetn};
-          12'h011: up_rdata <= {29'd0, up_ss_bypass, up_full_range, up_csc_bypass};
+          12'h011: up_rdata <= {29'd0, up_ss_bypass, 1'b0, up_csc_bypass};
           12'h012: up_rdata <= {30'd0, up_srcsel};
           12'h013: up_rdata <= {8'd0, up_const_rgb};
           12'h015: up_rdata <= up_hdmi_clk_count_s;
@@ -332,7 +327,6 @@ module up_hdmi_tx (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_ss_bypass,
-                      up_full_range,
                       up_csc_bypass,
                       up_srcsel,
                       up_const_rgb,
@@ -352,7 +346,6 @@ module up_hdmi_tx (
     .d_rst (hdmi_rst),
     .d_clk (hdmi_clk),
     .d_data_cntrl ({  hdmi_ss_bypass,
-                      hdmi_full_range,
                       hdmi_csc_bypass,
                       hdmi_srcsel,
                       hdmi_const_rgb,

From 578376c8fe13e1032df6b1bc354361c72f2f081a Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 17 May 2016 11:04:21 +0300
Subject: [PATCH 233/972] axi_dacfifo: Add bypass logic

---
 library/axi_dacfifo/axi_dacfifo.v                 | 15 +++++++++++++--
 .../common/zc706/zc706_system_plddr3_dacfifo.tcl  |  2 ++
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index c949dcb6c..a01dd53a1 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -60,6 +60,8 @@ module axi_dacfifo (
   dac_dovf,
   dac_xfer_out,
 
+  dac_fifo_bypass,
+
   // axi interface
 
   axi_clk,
@@ -139,6 +141,8 @@ module axi_dacfifo (
   output                              dac_dovf;
   output                              dac_xfer_out;
 
+  input                               dac_fifo_bypass;
+
   // axi interface
 
   input                               axi_clk;
@@ -209,6 +213,8 @@ module axi_dacfifo (
     dma_dacrst_m2 <= dma_dacrst_m1;
   end
   assign dma_rst_s = dma_dacrst_m2;
+  wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
+  wire                                dma_ready_s;
 
   // instantiations
 
@@ -223,7 +229,7 @@ module axi_dacfifo (
     .dma_clk (dma_clk),
     .dma_rst (dma_rst_s),
     .dma_data (dma_data),
-    .dma_ready (dma_ready),
+    .dma_ready (dma_ready_s),
     .dma_valid (dma_valid),
     .dma_xfer_req (dma_xfer_req),
     .dma_xfer_last (dma_xfer_last),
@@ -301,10 +307,15 @@ module axi_dacfifo (
     .axi_xfer_req (axi_xfer_req_s),
     .dac_clk (dac_clk),
     .dac_valid (dac_valid),
-    .dac_data (dac_data),
+    .dac_data (dac_data_s),
     .dac_xfer_out (dac_xfer_out),
     .dac_dunf (dac_dunf),
     .dac_dovf (dac_dovf));
 
+  // output logic
+
+  assign dac_data = (dac_fifo_bypass) ? dma_data : dac_data_s;
+  assign dma_ready = (dac_fifo_bypass) ? dac_valid : dma_ready_s;
+
 endmodule
 
diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index 7a181ea39..6e8e7aee4 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -25,6 +25,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   create_bd_pin -dir O dac_dunf
   create_bd_pin -dir O dac_dovf
   create_bd_pin -dir O dac_xfer_out
+  create_bd_pin -dir I dac_fifo_bypass
 
   create_bd_pin -dir I -type clk dma_clk
   create_bd_pin -dir I dma_rvalid
@@ -80,6 +81,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   ad_connect  dma_xfer_req axi_dacfifo/dma_xfer_req
   ad_connect  dma_xfer_last axi_dacfifo/dma_xfer_last
 
+  ad_connect  dac_fifo_bypass axi_dacfifo/dac_fifo_bypass
   ad_connect  dac_valid axi_dacfifo/dac_valid
   ad_connect  dac_data axi_dacfifo/dac_data
   ad_connect  dac_dunf axi_dacfifo/dac_dunf

From 81ade7f26c75ec34ecba4eda44aa8d3a0daf20d1 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 17 May 2016 11:30:41 +0300
Subject: [PATCH 234/972] axi_dacfifo: Fix resets

DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
---
 library/axi_dacfifo/axi_dacfifo.v             | 18 +++--------------
 library/axi_dacfifo/axi_dacfifo_dac.v         |  3 ++-
 library/axi_dacfifo/axi_dacfifo_wr.v          | 20 +++++++++++++++----
 .../zc706/zc706_system_plddr3_dacfifo.tcl     |  2 +-
 4 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index a01dd53a1..c62f224b5 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -53,7 +53,7 @@ module axi_dacfifo (
   // dac interface
 
   dac_clk,
-  dac_reset,
+  dac_rst,
   dac_valid,
   dac_data,
   dac_dunf,
@@ -134,7 +134,7 @@ module axi_dacfifo (
   // dac interface
 
   input                               dac_clk;
-  input                               dac_reset;
+  input                               dac_rst;
   input                               dac_valid;
   output  [(DAC_DATA_WIDTH-1):0]      dac_data;
   output                              dac_dunf;
@@ -190,10 +190,6 @@ module axi_dacfifo (
   input   [(AXI_DATA_WIDTH-1):0]      axi_rdata;
   output                              axi_rready;
 
-  // internal registers
-  reg                                 dma_dacrst_m1 = 1'b0;
-  reg                                 dma_dacrst_m2 = 1'b0;
-
   // internal signals
 
   wire    [(AXI_DATA_WIDTH-1):0]      axi_wr_data_s;
@@ -204,15 +200,7 @@ module axi_dacfifo (
   wire                                axi_rd_valid_s;
   wire    [31:0]                      axi_rd_lastaddr_s;
   wire                                axi_xfer_req_s;
-  wire                                dma_rst_s;
 
-  // DAC reset the DMA side too
-
-  always @(posedge dma_clk) begin
-    dma_dacrst_m1 <= dac_reset;
-    dma_dacrst_m2 <= dma_dacrst_m1;
-  end
-  assign dma_rst_s = dma_dacrst_m2;
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
   wire                                dma_ready_s;
 
@@ -227,7 +215,6 @@ module axi_dacfifo (
     .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
   ) i_wr (
     .dma_clk (dma_clk),
-    .dma_rst (dma_rst_s),
     .dma_data (dma_data),
     .dma_ready (dma_ready_s),
     .dma_valid (dma_valid),
@@ -306,6 +293,7 @@ module axi_dacfifo (
     .axi_dready (axi_rd_ready_s),
     .axi_xfer_req (axi_xfer_req_s),
     .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
     .dac_valid (dac_valid),
     .dac_data (dac_data_s),
     .dac_xfer_out (dac_xfer_out),
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 37f725a01..9c175aea2 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -48,6 +48,7 @@ module axi_dacfifo_dac (
   axi_xfer_req,
 
   dac_clk,
+  dac_rst,
   dac_valid,
   dac_data,
   dac_xfer_out,
@@ -81,6 +82,7 @@ module axi_dacfifo_dac (
   // dac read
 
   input                               dac_clk;
+  input                               dac_rst;
   input                               dac_valid;
   output  [(DAC_DATA_WIDTH-1):0]      dac_data;
   output                              dac_xfer_out;
@@ -100,7 +102,6 @@ module axi_dacfifo_dac (
   reg                                 axi_almost_empty  = 1'b0;
   reg                                 axi_dwovf = 1'b0;
 
-  reg                                 dac_rst = 'd0;
   reg                                 dac_rd = 'd0;
   reg                                 dac_rd_d = 'd0;
   reg     [(DAC_DATA_WIDTH-1):0]      dac_rdata_d = 'd0;
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index 7111200cf..073e56d1d 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -44,7 +44,6 @@ module axi_dacfifo_wr (
   // dma fifo interface
 
   dma_clk,
-  dma_rst,
   dma_data,
   dma_ready,
   dma_valid,
@@ -115,7 +114,6 @@ module axi_dacfifo_wr (
   // dma fifo interface
 
   input                                     dma_clk;
-  input                                     dma_rst;
   input   [(DMA_DATA_WIDTH-1):0]            dma_data;
   output                                    dma_ready;
   input                                     dma_valid;
@@ -165,6 +163,8 @@ module axi_dacfifo_wr (
   reg     [(AXI_MADDRESS_WIDTH-1):0]        dma_mem_raddr_m2 = 'd0;
   reg     [(AXI_MADDRESS_WIDTH-1):0]        dma_mem_raddr = 'd0;
   reg                                       dma_ready = 'd0;
+  reg                                       dma_rst_m1 = 1'b0;
+  reg                                       dma_rst_m2 = 1'b0;
 
   reg     [ 2:0]                            axi_xfer_req_m = 3'b0;
   reg     [ 2:0]                            axi_xfer_last_m = 3'b0;
@@ -188,10 +188,13 @@ module axi_dacfifo_wr (
   reg                                       axi_mem_last_d = 1'b0;
   reg     [ 3:0]                            axi_wvalid_cntr = 4'b0;
 
+
   // internal signal
 
   wire    [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_addr_diff_s;
   wire    [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_raddr_s;
+  wire                                      dma_rst_s;
+
   wire    [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr_s;
   wire                                      axi_req_s;
   wire    [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata_s;
@@ -234,10 +237,19 @@ module axi_dacfifo_wr (
     end
   endfunction
 
+
+  // syncronize the AXI interface reset
+
+  always @(posedge dma_clk) begin
+    dma_rst_m1 <= ~axi_resetn;
+    dma_rst_m2 <= dma_rst_m1;
+  end
+  assign dma_rst_s = dma_rst_m2;
+
   // write address generation for the asymetric memory
 
   always @(posedge dma_clk) begin
-    if (dma_rst == 1'b1) begin
+    if (dma_rst_s == 1'b1) begin
       dma_mem_waddr <= 8'h0;
       dma_mem_waddr_g <= 8'h0;
     end else begin
@@ -255,7 +267,7 @@ module axi_dacfifo_wr (
                                               {dma_mem_raddr, 3'b0};
 
   always @(posedge dma_clk) begin
-    if (dma_rst == 1'b1) begin
+    if (dma_rst_s == 1'b1) begin
       dma_mem_addr_diff <= 'b0;
       dma_mem_raddr_m1 <= 'b0;
       dma_mem_raddr_m2 <= 'b0;
diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index 6e8e7aee4..03b705ca1 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -67,7 +67,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   ad_connect  axi_resetn axi_rstgen/peripheral_aresetn
   ad_connect  axi_resetn axi_dacfifo/axi_resetn
   ad_connect  axi_resetn axi_ddr_cntrl/aresetn
-  ad_connect  dac_rst axi_dacfifo/dac_reset
+  ad_connect  dac_rst axi_dacfifo/dac_rst
   ad_connect  dac_rst axi_rstgen/ext_reset_in
 
   ## interfaces

From aca3038919ec0a388264edc982c7721b2f7df75f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 17 May 2016 17:04:12 +0300
Subject: [PATCH 235/972] axi_dacfifo: No overflow for DAC

---
 library/axi_dacfifo/axi_dacfifo.v                     |  5 +----
 library/axi_dacfifo/axi_dacfifo_dac.v                 | 11 +----------
 projects/common/zc706/zc706_system_plddr3_dacfifo.tcl |  2 --
 3 files changed, 2 insertions(+), 16 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index c62f224b5..3ba17de2d 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -57,7 +57,6 @@ module axi_dacfifo (
   dac_valid,
   dac_data,
   dac_dunf,
-  dac_dovf,
   dac_xfer_out,
 
   dac_fifo_bypass,
@@ -138,7 +137,6 @@ module axi_dacfifo (
   input                               dac_valid;
   output  [(DAC_DATA_WIDTH-1):0]      dac_data;
   output                              dac_dunf;
-  output                              dac_dovf;
   output                              dac_xfer_out;
 
   input                               dac_fifo_bypass;
@@ -297,8 +295,7 @@ module axi_dacfifo (
     .dac_valid (dac_valid),
     .dac_data (dac_data_s),
     .dac_xfer_out (dac_xfer_out),
-    .dac_dunf (dac_dunf),
-    .dac_dovf (dac_dovf));
+    .dac_dunf (dac_dunf));
 
   // output logic
 
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 9c175aea2..7216d9c72 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -52,9 +52,7 @@ module axi_dacfifo_dac (
   dac_valid,
   dac_data,
   dac_xfer_out,
-  dac_dunf,
-  dac_dovf
-
+  dac_dunf
 );
 
   // parameters
@@ -87,7 +85,6 @@ module axi_dacfifo_dac (
   output  [(DAC_DATA_WIDTH-1):0]      dac_data;
   output                              dac_xfer_out;
   output                              dac_dunf;
-  output                              dac_dovf;
 
   // internal registers
 
@@ -100,7 +97,6 @@ module axi_dacfifo_dac (
   reg                                 axi_almost_full = 1'b0;
   reg                                 axi_dwunf = 1'b0;
   reg                                 axi_almost_empty  = 1'b0;
-  reg                                 axi_dwovf = 1'b0;
 
   reg                                 dac_rd = 'd0;
   reg                                 dac_rd_d = 'd0;
@@ -109,7 +105,6 @@ module axi_dacfifo_dac (
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_raddr_g = 'd0;
 
   reg     [ 2:0]                      dac_dunf_m = 3'b0;
-  reg     [ 2:0]                      dac_dovf_m = 3'b0;
   reg     [ 2:0]                      dac_xfer_req_m = 3'b0;
 
   // internal signals
@@ -189,7 +184,6 @@ module axi_dacfifo_dac (
       axi_almost_full <= 1'b0;
       axi_dwunf <= 1'b0;
       axi_almost_empty <= 1'b0;
-      axi_dwovf <= 1'b0;
     end else begin
       axi_raddr_m <= g2b(dac_raddr_g);
       axi_raddr <= axi_raddr_m;
@@ -210,17 +204,14 @@ module axi_dacfifo_dac (
         axi_almost_empty <= 1'b0;
       end
       axi_dwunf <= (axi_addr_diff == 0) ? 1'b1 : 1'b0;
-      axi_dwovf <= (axi_addr_diff == {(DAC_ADDRESS_WIDTH){1'b1}}) ? 1'b1 : 1'b0;
     end
   end
 
   always @(posedge dac_clk) begin
     dac_dunf_m <= {dac_dunf_m[1:0], axi_dwunf};
-    dac_dovf_m <= {dac_dovf_m[1:0], axi_dwovf};
     dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
   end
 
-  assign dac_dovf = dac_dovf_m[2];
   assign dac_dunf = dac_dunf_m[2];
   assign dac_xfer_out = dac_xfer_req_m[2];
 
diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index 03b705ca1..a0f32bdd1 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -23,7 +23,6 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   create_bd_pin -dir I dac_valid
   create_bd_pin -dir O -from [expr ($dac_data_width-1)] -to 0 dac_data
   create_bd_pin -dir O dac_dunf
-  create_bd_pin -dir O dac_dovf
   create_bd_pin -dir O dac_xfer_out
   create_bd_pin -dir I dac_fifo_bypass
 
@@ -85,7 +84,6 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   ad_connect  dac_valid axi_dacfifo/dac_valid
   ad_connect  dac_data axi_dacfifo/dac_data
   ad_connect  dac_dunf axi_dacfifo/dac_dunf
-  ad_connect  dac_dovf axi_dacfifo/dac_dovf
   ad_connect  dac_xfer_out axi_dacfifo/dac_xfer_out
 
   ad_connect  axi_ddr_cntrl/device_temp_i GND

From 88e0cfec42e6bd9d7c601b918a7f1249c7878737 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 17 May 2016 17:07:18 +0300
Subject: [PATCH 236/972] axi_dacfifo: The AXI read and write have the same
 properties

AXI read and AXI write channel have the same SIZE and LENGTH.
---
 library/axi_dacfifo/axi_dacfifo.v     | 15 +++++++--------
 library/axi_dacfifo/axi_dacfifo_dac.v |  3 ++-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index 3ba17de2d..01f140e0a 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -113,10 +113,8 @@ module axi_dacfifo (
   parameter   DAC_DATA_WIDTH = 128;
   parameter   DMA_DATA_WIDTH = 64;
   parameter   AXI_DATA_WIDTH = 512;
-  parameter   AXI_RD_SIZE = 2;
-  parameter   AXI_RD_LENGTH = 32;
-  parameter   AXI_WR_SIZE = 2;
-  parameter   AXI_WR_LENGTH = 32;
+  parameter   AXI_SIZE = 2;
+  parameter   AXI_LENGTH = 15;
   parameter   AXI_ADDRESS = 32'h00000000;
   parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
   parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
@@ -207,8 +205,8 @@ module axi_dacfifo (
   axi_dacfifo_wr #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
     .DMA_DATA_WIDTH (DMA_DATA_WIDTH),
-    .AXI_SIZE (AXI_WR_SIZE),
-    .AXI_LENGTH (AXI_WR_LENGTH),
+    .AXI_SIZE (AXI_SIZE),
+    .AXI_LENGTH (AXI_LENGTH),
     .AXI_ADDRESS (AXI_ADDRESS),
     .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
   ) i_wr (
@@ -249,8 +247,8 @@ module axi_dacfifo (
 
   axi_dacfifo_rd #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
-    .AXI_SIZE (AXI_RD_SIZE),
-    .AXI_LENGTH (AXI_RD_LENGTH),
+    .AXI_SIZE (AXI_SIZE),
+    .AXI_LENGTH (AXI_LENGTH),
     .AXI_ADDRESS (AXI_ADDRESS)
   ) i_rd (
     .axi_rd_lastaddr (axi_rd_lastaddr_s),
@@ -283,6 +281,7 @@ module axi_dacfifo (
 
   axi_dacfifo_dac #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
+    .AXI_LENGTH(AXI_LENGTH),
     .DAC_DATA_WIDTH (DAC_DATA_WIDTH)
   ) i_dac (
     .axi_clk (axi_clk),
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 7216d9c72..44a47ea1f 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -58,7 +58,8 @@ module axi_dacfifo_dac (
   // parameters
 
   parameter   AXI_DATA_WIDTH = 512;
-  parameter   DAC_DATA_WIDTH =  64;
+  parameter   AXI_LENGTH = 15;
+  parameter   DAC_DATA_WIDTH = 64;
 
   localparam  MEM_RATIO = AXI_DATA_WIDTH/DAC_DATA_WIDTH;
   localparam  DAC_ADDRESS_WIDTH = 8;

From c8d4f956e7956c1af8e7924da4801110329c3452 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 17 May 2016 18:43:59 +0300
Subject: [PATCH 237/972] axi_dacfifo: Update the read back logic

Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
---
 library/axi_dacfifo/axi_dacfifo.v     |   3 +
 library/axi_dacfifo/axi_dacfifo_dac.v | 233 ++++++++++++++++----------
 library/axi_dacfifo/axi_dacfifo_rd.v  |   3 +-
 library/axi_dacfifo/axi_dacfifo_wr.v  |  20 ++-
 4 files changed, 170 insertions(+), 89 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index 01f140e0a..f6b3ccc96 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -196,6 +196,7 @@ module axi_dacfifo (
   wire                                axi_rd_valid_s;
   wire    [31:0]                      axi_rd_lastaddr_s;
   wire                                axi_xfer_req_s;
+  wire    [31:0]                      dma_last_addr_s;
 
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
   wire                                dma_ready_s;
@@ -217,6 +218,7 @@ module axi_dacfifo (
     .dma_xfer_req (dma_xfer_req),
     .dma_xfer_last (dma_xfer_last),
     .axi_last_raddr (axi_rd_lastaddr_s),
+    .dma_last_addr (dma_last_addr_s),
     .axi_xfer_out (axi_xfer_req_s),
     .axi_clk (axi_clk),
     .axi_resetn (axi_resetn),
@@ -289,6 +291,7 @@ module axi_dacfifo (
     .axi_ddata (axi_rd_data_s),
     .axi_dready (axi_rd_ready_s),
     .axi_xfer_req (axi_xfer_req_s),
+    .dma_last_addr (dma_last_addr_s),
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid),
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 44a47ea1f..3aeeb3d94 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -47,6 +47,8 @@ module axi_dacfifo_dac (
   axi_dready,
   axi_xfer_req,
 
+  dma_last_addr,
+
   dac_clk,
   dac_rst,
   dac_valid,
@@ -67,8 +69,13 @@ module axi_dacfifo_dac (
                                   (MEM_RATIO == 2) ? (DAC_ADDRESS_WIDTH - 1) :
                                   (MEM_RATIO == 4) ? (DAC_ADDRESS_WIDTH - 2) :
                                                      (DAC_ADDRESS_WIDTH - 3);
-  localparam  BUF_THRESHOLD_LO = 8'd32;
-  localparam  BUF_THRESHOLD_HI = 8'd240;
+
+  // BUF_THRESHOLD_LO will make sure that there are always at least two burst in the memmory
+  localparam  AXI_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1);
+  localparam  AXI_BUF_THRESHOLD_HI = {(AXI_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1);
+  localparam  DAC_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1) * MEM_RATIO;
+  localparam  DAC_BUF_THRESHOLD_HI = {(DAC_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1) * MEM_RATIO;
+  localparam  DAC_ARINCR = (AXI_LENGTH+1) * MEM_RATIO;
 
   // dma write
 
@@ -78,6 +85,8 @@ module axi_dacfifo_dac (
   output                              axi_dready;
   input                               axi_xfer_req;
 
+  input   [32:0]                      dma_last_addr;
+
   // dac read
 
   input                               dac_clk;
@@ -89,34 +98,44 @@ module axi_dacfifo_dac (
 
   // internal registers
 
-  reg     [(AXI_ADDRESS_WIDTH-1):0]   axi_waddr = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_waddr_g = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_raddr = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_raddr_m = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_addr_diff = 'd0;
+  reg     [(AXI_ADDRESS_WIDTH-1):0]   axi_mem_waddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_waddr_g = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr_m = 'd0;
+  reg     [(AXI_ADDRESS_WIDTH-1):0]   axi_mem_addr_diff = 'd0;
   reg                                 axi_dready = 'd0;
-  reg                                 axi_almost_full = 1'b0;
-  reg                                 axi_dwunf = 1'b0;
-  reg                                 axi_almost_empty  = 1'b0;
 
-  reg                                 dac_rd = 'd0;
-  reg                                 dac_rd_d = 'd0;
-  reg     [(DAC_DATA_WIDTH-1):0]      dac_rdata_d = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_raddr = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_raddr_g = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_raddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_raddr_next = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_raddr_g = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr_m = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_addr_diff = 'd0;
+  reg                                 dac_mem_init = 1'b0;
+  reg                                 dac_mem_init_d = 1'b0;
+  reg                                 dac_mem_enable = 1'b0;
 
-  reg     [ 2:0]                      dac_dunf_m = 3'b0;
   reg     [ 2:0]                      dac_xfer_req_m = 3'b0;
+  reg                                 dac_xfer_init = 1'b0;
+
+  reg     [31:0]                      dac_raddr_cnt = 32'b0;
+  reg     [31:0]                      dac_last_raddr = 32'b0;
+  reg     [31:0]                      dac_last_raddr_m = 32'b0;
+  reg                                 dac_almost_full = 1'b0;
+  reg                                 dac_almost_empty = 1'b0;
+  reg                                 dac_dunf = 1'b0;
 
   // internal signals
 
-  wire    [DAC_ADDRESS_WIDTH:0]       axi_addr_diff_s;
-  wire    [(DAC_ADDRESS_WIDTH-1):0]   axi_waddr_s;
-  wire                                dac_wready_s;
-  wire                                dac_rd_s;
-  wire    [(DAC_DATA_WIDTH-1):0]      dac_rdata_s;
+  wire    [AXI_ADDRESS_WIDTH:0]       axi_mem_addr_diff_s;
+  wire    [(AXI_ADDRESS_WIDTH-1):0]   axi_mem_raddr_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_waddr_s;
 
-  wire                                dac_valid_s;
+  wire    [DAC_ADDRESS_WIDTH:0]       dac_mem_addr_diff_s;
+  wire    [DAC_ADDRESS_WIDTH:0]       dac_mem_raddr_diff_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr_s;
+  wire                                dac_mem_valid_s;
+  wire                                dac_xfer_init_s;
 
   // binary to grey conversion
 
@@ -158,83 +177,136 @@ module axi_dacfifo_dac (
 
   always @(posedge axi_clk) begin
     if (axi_xfer_req == 1'b0) begin
-      axi_waddr <= 'd0;
-      axi_waddr_g <= 'd0;
+      axi_mem_waddr <= 'd0;
+      axi_mem_waddr_g <= 'd0;
     end else begin
       if (axi_dvalid == 1'b1) begin
-        axi_waddr <= axi_waddr + 1'b1;
+        axi_mem_waddr <= axi_mem_waddr + 1'b1;
       end
-      axi_waddr_g <= b2g(axi_waddr_s);
+      axi_mem_waddr_g <= b2g(axi_mem_waddr_s);
     end
   end
 
-  // underflow / overflow
+  // scale the axi_mem_* addresses
 
-  assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr;
-  assign axi_waddr_s = (MEM_RATIO == 1) ? axi_waddr :
-                       (MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
-                       (MEM_RATIO == 4) ? {axi_waddr, 2'd0} :
-                                          {axi_waddr, 3'd0};
+  assign axi_mem_raddr_s = (MEM_RATIO == 1) ? axi_mem_raddr :
+                           (MEM_RATIO == 2) ? axi_mem_raddr[(DAC_ADDRESS_WIDTH-1):1] :
+                           (MEM_RATIO == 4) ? axi_mem_raddr[(DAC_ADDRESS_WIDTH-1):2] :
+                                              axi_mem_raddr[(DAC_ADDRESS_WIDTH-1):3];
+  assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr :
+                           (MEM_RATIO == 2) ? {axi_mem_waddr, 1'b0} :
+                           (MEM_RATIO == 4) ? {axi_mem_waddr, 2'b0} :
+                                              {axi_mem_waddr, 3'b0};
+
+  // incomming data flow control
+
+  assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr} - axi_mem_raddr_s;
 
   always @(posedge axi_clk) begin
     if (axi_xfer_req == 1'b0) begin
-      axi_addr_diff <= 'd0;
-      axi_raddr <= 'd0;
-      axi_raddr_m <= 'd0;
+      axi_mem_addr_diff <= 'd0;
+      axi_mem_raddr <= 'd0;
+      axi_mem_raddr_m <= 'd0;
       axi_dready <= 'd0;
-      axi_almost_full <= 1'b0;
-      axi_dwunf <= 1'b0;
-      axi_almost_empty <= 1'b0;
     end else begin
-      axi_raddr_m <= g2b(dac_raddr_g);
-      axi_raddr <= axi_raddr_m;
-      axi_addr_diff <= axi_addr_diff_s[DAC_ADDRESS_WIDTH-1:0];
-      if (axi_addr_diff >= BUF_THRESHOLD_HI) begin
+      axi_mem_raddr_m <= g2b(dac_mem_raddr_g);
+      axi_mem_raddr <= axi_mem_raddr_m;
+      axi_mem_addr_diff <= axi_mem_addr_diff_s[AXI_ADDRESS_WIDTH-1:0];
+      if (axi_mem_addr_diff >= AXI_BUF_THRESHOLD_HI) begin
         axi_dready <= 1'b0;
-      end else if (axi_addr_diff <= BUF_THRESHOLD_LO) begin
+      end else if (axi_mem_addr_diff <= AXI_BUF_THRESHOLD_LO) begin
         axi_dready <= 1'b1;
       end
-      if (axi_addr_diff > BUF_THRESHOLD_HI) begin
-        axi_almost_full <= 1'b1;
-      end else begin
-        axi_almost_full <= 1'b0;
+    end
+  end
+
+  // CDC for xfer_req signal
+
+  always @(posedge dac_clk) begin
+    dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
+  end
+
+  assign dac_xfer_out = dac_xfer_req_m[2];
+  assign dac_xfer_init_s = ~dac_xfer_req_m[2] & dac_xfer_req_m[1];
+
+  // read interface
+
+  always @(posedge dac_clk) begin
+    if (dac_xfer_out == 1'b0) begin
+      dac_mem_init <= 1'b0;
+      dac_mem_init_d <= 1'b0;
+      dac_mem_enable <= 1'b0;
+    end else begin
+      if (dac_xfer_init == 1'b1) begin
+        dac_mem_init <= 1'b1;
       end
-      if (axi_addr_diff < BUF_THRESHOLD_LO) begin
-        axi_almost_empty <= 1'b1;
-      end else begin
-        axi_almost_empty <= 1'b0;
+      if ((dac_mem_init == 1'b1) && (dac_mem_addr_diff > DAC_BUF_THRESHOLD_LO)) begin
+        dac_mem_init <= 1'b0;
       end
-      axi_dwunf <= (axi_addr_diff == 0) ? 1'b1 : 1'b0;
+      dac_mem_init_d <= dac_mem_init;
+      // memory is ready when the initial fill up is done
+      dac_mem_enable <= (dac_mem_init_d & ~dac_mem_init) ? 1'b1 : dac_mem_enable;
+    end
+    dac_xfer_init <= dac_xfer_init_s;
+  end
+
+  always @(posedge dac_clk) begin
+    if (dac_xfer_out == 1'b0) begin
+      dac_mem_waddr <= 'b0;
+      dac_mem_waddr_m <= 'b0;
+    end else begin
+      dac_mem_waddr_m <= g2b(axi_mem_waddr_g);
+      dac_mem_waddr <= dac_mem_waddr_m;
+    end
+  end
+
+  assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr} - dac_mem_raddr;
+  assign dac_mem_raddr_diff_s = {1'b1, dac_mem_raddr_next} - dac_mem_raddr;
+  assign dac_mem_valid_s = (dac_mem_enable) ? dac_valid : 1'b0;
+
+  // CDC for the dma_last_addr
+
+  always @(posedge dac_clk) begin
+    if (dac_rst == 1'b1) begin
+      dac_last_raddr <= 32'b0;
+      dac_last_raddr_m <= 32'b0;
+    end else begin
+      dac_last_raddr_m <= dma_last_addr;
+      dac_last_raddr <= dac_last_raddr_m;
     end
   end
 
   always @(posedge dac_clk) begin
-    dac_dunf_m <= {dac_dunf_m[1:0], axi_dwunf};
-    dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
+    if (dac_xfer_out == 1'b0) begin
+      dac_mem_raddr <= 'd0;
+      dac_mem_raddr_next <= DAC_ARINCR;
+      dac_mem_raddr_g <= 'd0;
+      dac_mem_addr_diff <= 'd0;
+    end else begin
+      dac_mem_addr_diff <= dac_mem_addr_diff_s[DAC_ADDRESS_WIDTH-1:0];
+      if (dac_mem_valid_s == 1'b1) begin
+        dac_raddr_cnt <= (dac_raddr_cnt == dac_last_raddr) ? 32'b0 : dac_raddr_cnt + 1;
+        dac_mem_raddr <= (dac_raddr_cnt == dac_last_raddr) ? dac_mem_raddr_next : dac_mem_raddr + 1'b1;
+      end
+      dac_mem_raddr_next <= (dac_mem_raddr_diff_s[DAC_ADDRESS_WIDTH-1:0] <= 1) ? dac_mem_raddr_next + DAC_ARINCR : dac_mem_raddr_next;
+      dac_mem_raddr_g <= b2g(dac_mem_raddr);
+    end
   end
 
-  assign dac_dunf = dac_dunf_m[2];
-  assign dac_xfer_out = dac_xfer_req_m[2];
-
-  // read interface
-
-  assign dac_rd_s = dac_xfer_out & dac_valid;
+  // underflow generation, there is no overflow
 
   always @(posedge dac_clk) begin
-    if (dac_xfer_out == 1'b0) begin
-      dac_rd <= 'd0;
-      dac_rd_d <= 'd0;
-      dac_rdata_d <= 'd0;
-      dac_raddr <= 'd0;
-      dac_raddr_g <= 'd0;
+    if(dac_xfer_out == 1'b0) begin
+      dac_almost_full <= 1'b0;
+      dac_almost_empty <= 1'b0;
+      dac_dunf <= 1'b0;
     end else begin
-      dac_rd <= dac_rd_s;
-      dac_rd_d <= dac_rd;
-      dac_rdata_d <= dac_rdata_s;
-      if (dac_rd_s == 1'b1) begin
-        dac_raddr <= dac_raddr + 1'b1;
+      if (dac_mem_addr_diff < DAC_BUF_THRESHOLD_LO) begin
+        dac_almost_empty <= 1'b1;
+      end else begin
+        dac_almost_empty <= 1'b0;
       end
-      dac_raddr_g <= b2g(dac_raddr);
+      dac_dunf <= (dac_mem_addr_diff == 0) ? 1'b1 : 1'b0;
     end
   end
 
@@ -248,22 +320,11 @@ module axi_dacfifo_dac (
   i_mem_asym (
     .clka (axi_clk),
     .wea (axi_dvalid),
-    .addra (axi_waddr),
+    .addra (axi_mem_waddr),
     .dina (axi_ddata),
     .clkb (dac_clk),
-    .addrb (dac_raddr),
-    .doutb (dac_rdata_s));
-
-  ad_axis_inf_rx #(.DATA_WIDTH(DAC_DATA_WIDTH)) i_axis_inf (
-    .clk (dac_clk),
-    .rst (dac_rst),
-    .valid (dac_rd_d),
-    .last (1'd0),
-    .data (dac_rdata_d),
-    .inf_valid (dac_valid_s),
-    .inf_last (),
-    .inf_data (dac_data),
-    .inf_ready (dac_valid));
+    .addrb (dac_mem_raddr),
+    .doutb (dac_data));
 
 endmodule
 
diff --git a/library/axi_dacfifo/axi_dacfifo_rd.v b/library/axi_dacfifo/axi_dacfifo_rd.v
index b3ec1388f..f4f309fc7 100644
--- a/library/axi_dacfifo/axi_dacfifo_rd.v
+++ b/library/axi_dacfifo/axi_dacfifo_rd.v
@@ -186,6 +186,7 @@ module axi_dacfifo_rd (
     if (axi_resetn == 1'b0) begin
       axi_arvalid <= 'd0;
       axi_araddr <= 'd0;
+      axi_rd_addr_h <= 'd0;
     end else begin
       if (axi_arvalid == 1'b1) begin
         if (axi_arready == 1'b1) begin
@@ -202,7 +203,7 @@ module axi_dacfifo_rd (
       end else if ((axi_xfer_req == 1'b1) &&
                    (axi_arvalid == 1'b1) &&
                    (axi_arready == 1'b1)) begin
-        axi_araddr <= ((axi_araddr + AXI_AWINCR) >= axi_rd_addr_h) ? AXI_ADDRESS : axi_araddr + AXI_AWINCR;
+        axi_araddr <= (axi_araddr >= axi_rd_addr_h) ? AXI_ADDRESS : axi_araddr + AXI_AWINCR;
       end
     end
   end
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index 073e56d1d..71c4ccd95 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -56,6 +56,7 @@ module axi_dacfifo_wr (
   // syncronization for the read side
 
   axi_last_raddr,
+  dma_last_addr,
   axi_xfer_out,
 
   // axi write address, write data and write response channels
@@ -122,6 +123,7 @@ module axi_dacfifo_wr (
   input                                     dma_xfer_last;
 
   output  [31:0]                            axi_last_raddr;
+  output  [31:0]                            dma_last_addr;
   output                                    axi_xfer_out;
 
   // axi interface
@@ -165,6 +167,8 @@ module axi_dacfifo_wr (
   reg                                       dma_ready = 'd0;
   reg                                       dma_rst_m1 = 1'b0;
   reg                                       dma_rst_m2 = 1'b0;
+  reg     [31:0]                            dma_last_addr = 32'b0;
+  reg     [31:0]                            dma_addr_cnt = 32'b0;
 
   reg     [ 2:0]                            axi_xfer_req_m = 3'b0;
   reg     [ 2:0]                            axi_xfer_last_m = 3'b0;
@@ -248,6 +252,18 @@ module axi_dacfifo_wr (
 
   // write address generation for the asymetric memory
 
+  always @(posedge dma_clk) begin
+    if (dma_rst_s == 1'b1) begin
+      dma_addr_cnt <= 32'b0;
+      dma_last_addr <= 32'b0;
+    end else begin
+      if((dma_valid == 1'b1) && (dma_xfer_req == 1'b1)) begin
+        dma_addr_cnt <= (dma_xfer_last == 1'b1) ? 32'b0 : dma_addr_cnt + 1;
+        dma_last_addr <= (dma_xfer_last == 1'b1) ? dma_addr_cnt : dma_last_addr;
+      end
+    end
+  end
+
   always @(posedge dma_clk) begin
     if (dma_rst_s == 1'b1) begin
       dma_mem_waddr <= 8'h0;
@@ -371,8 +387,8 @@ module axi_dacfifo_wr (
       end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
         axi_awaddr <= axi_awaddr + AXI_AWINCR;
       end
-      if(axi_xfer_last_m[2] == 1) begin
-        axi_last_raddr <= axi_awaddr;
+      if ((axi_xfer_req_m[2] == 1) && (axi_xfer_last_m[2] == 1)) begin
+        axi_last_raddr <= axi_awaddr - AXI_AWINCR;
         axi_xfer_out <= 1'b1;
       end
     end

From d0b40afb45bd3a278be7af7aec2d9d964cda4756 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 17 May 2016 19:00:52 +0300
Subject: [PATCH 238/972] zc706/common: Fix PL_DDR3 fifo integration script

---
 projects/common/zc706/zc706_system_plddr3_dacfifo.tcl | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index a0f32bdd1..d7fceee87 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -46,10 +46,8 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   set_property -dict [list CONFIG.DAC_DATA_WIDTH $dac_data_width] $axi_dacfifo
   set_property -dict [list CONFIG.DMA_DATA_WIDTH $dma_data_width] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_dacfifo
-  set_property -dict [list CONFIG.AXI_WR_SIZE {6}] $axi_dacfifo
-  set_property -dict [list CONFIG.AXI_WR_LENGTH {3}] $axi_dacfifo
-  set_property -dict [list CONFIG.AXI_RD_SIZE {6}] $axi_dacfifo
-  set_property -dict [list CONFIG.AXI_RD_LENGTH {15}] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_dacfifo
+  set_property -dict [list CONFIG.AXI_LENGTH {15}] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo
 

From 3b6a36e3e2d343d9cccad78b42677cd43dcd43a7 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 17 May 2016 19:03:31 +0300
Subject: [PATCH 239/972] axi_dacfifo: Increase the ASYM_MEM depth in the DAC
 side

Increase the asymetric memory depth on the DAC side. Increase the
data width of the grey coder and decoder.
The controller fills up the CDC memory with three AXI burst, to prevent
underflow on the wrap arounds.
---
 library/axi_dacfifo/axi_dacfifo_dac.v | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 3aeeb3d94..3dd620f2a 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -64,7 +64,7 @@ module axi_dacfifo_dac (
   parameter   DAC_DATA_WIDTH = 64;
 
   localparam  MEM_RATIO = AXI_DATA_WIDTH/DAC_DATA_WIDTH;
-  localparam  DAC_ADDRESS_WIDTH = 8;
+  localparam  DAC_ADDRESS_WIDTH = 10;
   localparam  AXI_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
                                   (MEM_RATIO == 2) ? (DAC_ADDRESS_WIDTH - 1) :
                                   (MEM_RATIO == 4) ? (DAC_ADDRESS_WIDTH - 2) :
@@ -139,11 +139,13 @@ module axi_dacfifo_dac (
 
   // binary to grey conversion
 
-  function [7:0] b2g;
-    input [7:0] b;
-    reg   [7:0] g;
+  function [9:0] b2g;
+    input [9:0] b;
+    reg   [9:0] g;
     begin
-      g[7] = b[7];
+      g[9] = b[9];
+      g[8] = b[9] ^ b[8];
+      g[7] = b[8] ^ b[7];
       g[6] = b[7] ^ b[6];
       g[5] = b[6] ^ b[5];
       g[4] = b[5] ^ b[4];
@@ -157,11 +159,13 @@ module axi_dacfifo_dac (
 
   // grey to binary conversion
 
-  function [7:0] g2b;
-    input [7:0] g;
-    reg   [7:0] b;
+  function [9:0] g2b;
+    input [9:0] g;
+    reg   [9:0] b;
     begin
-      b[7] = g[7];
+      b[9] = g[9];
+      b[8] = b[9] ^ g[8];
+      b[7] = b[8] ^ g[7];
       b[6] = b[7] ^ g[6];
       b[5] = b[6] ^ g[5];
       b[4] = b[5] ^ g[4];

From 3859cba186b91d595ecc6d30b54997dcd2dd2c62 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 17 May 2016 10:05:52 +0300
Subject: [PATCH 240/972] adrv9371x/zc706: Add PL_DDR FIFO to the design

---
 projects/adrv9371x/common/adrv9371x_bd.tcl  | 30 +++++-----
 projects/adrv9371x/zc706/system_bd.tcl      | 19 +++++++
 projects/adrv9371x/zc706/system_project.tcl |  1 +
 projects/adrv9371x/zc706/system_top.v       | 63 ++++++++++++++++++++-
 4 files changed, 96 insertions(+), 17 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index 46c7f6920..28e864ca3 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -37,7 +37,6 @@ set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_tx_dma
-set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_tx_dma
@@ -46,8 +45,6 @@ set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9371_tx_dma
 
-p_sys_dacfifo [current_bd_instance .] axi_ad9371_tx_fifo 128 17
-
 set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack]
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
@@ -253,19 +250,21 @@ ad_connect  axi_ad9371_core/dac_data_i1 util_ad9371_tx_upack/dac_data_2
 ad_connect  axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
 ad_connect  axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
 ad_connect  axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
-ad_connect  util_ad9371_tx_upack/dma_xfer_in axi_ad9371_tx_fifo/dac_xfer_out
-ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_fifo/dac_clk
-ad_connect  util_ad9371_tx_upack/dac_valid axi_ad9371_tx_fifo/dac_valid
-ad_connect  util_ad9371_tx_upack/dac_data axi_ad9371_tx_fifo/dac_data
-ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_fifo/dma_clk
-ad_connect  util_ad9371_gt/tx_rst axi_ad9371_tx_fifo/dma_rst
+
 ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_dma/m_axis_aclk
 ad_connect  sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
-ad_connect  axi_ad9371_tx_fifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
-ad_connect  axi_ad9371_tx_fifo/dma_ready axi_ad9371_tx_dma/m_axis_ready
-ad_connect  axi_ad9371_tx_fifo/dma_data axi_ad9371_tx_dma/m_axis_data
-ad_connect  axi_ad9371_tx_fifo/dma_valid axi_ad9371_tx_dma/m_axis_valid
-ad_connect  axi_ad9371_tx_fifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
+ad_connect  util_ad9371_gt/tx_rst axi_ad9371_dacfifo/dac_rst
+ad_connect  util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out
+ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
+ad_connect  util_ad9371_tx_upack/dac_valid axi_ad9371_dacfifo/dac_valid
+ad_connect  util_ad9371_tx_upack/dac_data axi_ad9371_dacfifo/dac_data
+ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dma_clk
+
+ad_connect  axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
+ad_connect  axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready
+ad_connect  axi_ad9371_dacfifo/dma_rdata axi_ad9371_tx_dma/m_axis_data
+ad_connect  axi_ad9371_dacfifo/dma_rvalid axi_ad9371_tx_dma/m_axis_valid
+ad_connect  axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
 
 # connections (adc)
 
@@ -333,7 +332,8 @@ ad_connect  util_ad9371_rx_os_cpack/adc_valid axi_ad9371_rx_os_dma/fifo_wr_en
 ad_connect  util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync
 ad_connect  util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din
 ad_connect  axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf
-ad_connect  axi_ad9371_tx_fifo/dac_fifo_bypass dac_fifo_bypass
+
+#ad_connect  axi_ad9371_tx_fifo/dac_fifo_bypass dac_fifo_bypass
 
 # interconnect (cpu)
 
diff --git a/projects/adrv9371x/zc706/system_bd.tcl b/projects/adrv9371x/zc706/system_bd.tcl
index 108741a54..09f629479 100644
--- a/projects/adrv9371x/zc706/system_bd.tcl
+++ b/projects/adrv9371x/zc706/system_bd.tcl
@@ -1,5 +1,24 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+
+p_plddr3_dacfifo [current_bd_instance .] axi_ad9371_dacfifo 128 128
+
+create_bd_port -dir I -type rst sys_rst
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
+
+set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
+
+ad_connect  sys_rst axi_ad9371_dacfifo/sys_rst
+ad_connect  sys_clk axi_ad9371_dacfifo/sys_clk
+ad_connect  ddr3 axi_ad9371_dacfifo/ddr3
+
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
+  [get_bd_addr_spaces axi_ad9371_dacfifo/axi_dacfifo/axi] \
+  [get_bd_addr_segs axi_ad9371_dacfifo/axi_ddr_cntrl/memmap/memaddr] \
+  SEG_axi_ddr_cntrl_memaddr
+
 source ../common/adrv9371x_bd.tcl
 
diff --git a/projects/adrv9371x/zc706/system_project.tcl b/projects/adrv9371x/zc706/system_project.tcl
index 7c4ff30c2..3a9b054a9 100644
--- a/projects/adrv9371x/zc706/system_project.tcl
+++ b/projects/adrv9371x/zc706/system_project.tcl
@@ -10,6 +10,7 @@ adi_project_files adrv9371x_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
diff --git a/projects/adrv9371x/zc706/system_top.v b/projects/adrv9371x/zc706/system_top.v
index a7d4ff1b8..28522d8ff 100644
--- a/projects/adrv9371x/zc706/system_top.v
+++ b/projects/adrv9371x/zc706/system_top.v
@@ -126,7 +126,27 @@ module system_top (
   ad9371_gpio_13,
   ad9371_gpio_17,
   ad9371_gpio_16,
-  ad9371_gpio_18);
+  ad9371_gpio_18,
+
+  sys_rst,
+  sys_clk_p,
+  sys_clk_n,
+
+  ddr3_addr,
+  ddr3_ba,
+  ddr3_cas_n,
+  ddr3_ck_n,
+  ddr3_ck_p,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_dm,
+  ddr3_dq,
+  ddr3_dqs_n,
+  ddr3_dqs_p,
+  ddr3_odt,
+  ddr3_ras_n,
+  ddr3_reset_n,
+  ddr3_we_n);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -217,6 +237,27 @@ module system_top (
   inout           ad9371_gpio_16;
   inout           ad9371_gpio_18;
 
+  input           sys_rst;
+  input           sys_clk_p;
+  input           sys_clk_n;
+
+
+  output  [13:0]  ddr3_addr;
+  output  [ 2:0]  ddr3_ba;
+  output          ddr3_cas_n;
+  output  [ 0:0]  ddr3_ck_n;
+  output  [ 0:0]  ddr3_ck_p;
+  output  [ 0:0]  ddr3_cke;
+  output  [ 0:0]  ddr3_cs_n;
+  output  [ 7:0]  ddr3_dm;
+  inout   [63:0]  ddr3_dq;
+  inout   [ 7:0]  ddr3_dqs_n;
+  inout   [ 7:0]  ddr3_dqs_p;
+  output  [ 0:0]  ddr3_odt;
+  output          ddr3_ras_n;
+  output          ddr3_reset_n;
+  output          ddr3_we_n;
+
   // internal signals
 
   wire    [63:0]  gpio_i;
@@ -381,7 +422,25 @@ module system_top (
     .tx_ref_clk (ref_clk1),
     .tx_sync (tx_sync),
     .tx_sysref (sysref),
-    .dac_fifo_bypass(ad9371_dac_fifo_bypass_s));
+    .dac_fifo_bypass(ad9371_dac_fifo_bypass_s),
+    .sys_rst(sys_rst),
+    .sys_clk_clk_p (sys_clk_p),
+    .sys_clk_clk_n (sys_clk_n),
+    .ddr3_addr (ddr3_addr),
+    .ddr3_ba (ddr3_ba),
+    .ddr3_cas_n (ddr3_cas_n),
+    .ddr3_ck_n (ddr3_ck_n),
+    .ddr3_ck_p (ddr3_ck_p),
+    .ddr3_cke (ddr3_cke),
+    .ddr3_cs_n (ddr3_cs_n),
+    .ddr3_dm (ddr3_dm),
+    .ddr3_dq (ddr3_dq),
+    .ddr3_dqs_n (ddr3_dqs_n),
+    .ddr3_dqs_p (ddr3_dqs_p),
+    .ddr3_odt (ddr3_odt),
+    .ddr3_ras_n (ddr3_ras_n),
+    .ddr3_reset_n (ddr3_reset_n),
+    .ddr3_we_n (ddr3_we_n));
 
 endmodule
 

From b452a8e2d48c57083865b098c29b99f135c672d0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 20 May 2016 12:45:33 +0300
Subject: [PATCH 241/972] adrv9371x: Connect bypass and data underflow

---
 projects/adrv9371x/common/adrv9371x_bd.tcl | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index 28e864ca3..73fb466d1 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -266,6 +266,9 @@ ad_connect  axi_ad9371_dacfifo/dma_rdata axi_ad9371_tx_dma/m_axis_data
 ad_connect  axi_ad9371_dacfifo/dma_rvalid axi_ad9371_tx_dma/m_axis_valid
 ad_connect  axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
 
+ad_connect  dac_fifo_bypass axi_ad9371_dacfifo/dac_fifo_bypass
+ad_connect  axi_ad9371_dacfifo/dac_dunf axi_ad9371_core/dac_dunf
+
 # connections (adc)
 
 ad_connect  util_ad9371_gt/rx_sysref rx_sysref
@@ -333,8 +336,6 @@ ad_connect  util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync
 ad_connect  util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din
 ad_connect  axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf
 
-#ad_connect  axi_ad9371_tx_fifo/dac_fifo_bypass dac_fifo_bypass
-
 # interconnect (cpu)
 
 ad_cpu_interconnect 0x44A60000 axi_ad9371_gt

From 32d46389f20e3bb0b44e4df47ad1f1d8831cd457 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 19 May 2016 17:19:57 +0300
Subject: [PATCH 242/972] adrv9371x: Move GTs AXI interface to HP3

If the VDMA and the GTs AXI are connected to the same HP port, the
HDMI won't work on full resolution (1080p). Care should be taken, this can
affect the receive and observation paths (both are connected to HP2).
---
 projects/adrv9371x/common/adrv9371x_bd.tcl | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index 73fb466d1..3e9d91694 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -350,9 +350,10 @@ ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9371_rx_dma
 ad_cpu_interconnect 0x7c440000 axi_ad9371_rx_os_dma
 
-# gt uses hp0, and 100MHz clock for both DRP and AXI4
+# gt uses hp3, and 100MHz clock for both DRP and AXI4
 
-ad_mem_hp0_interconnect sys_cpu_clk axi_ad9371_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_gt/m_axi
 
 # interconnect (mem/dac)
 

From 8caa783f5ca03cdbeb4a5f7c0a8a2d71acbde532 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 24 May 2016 18:09:27 +0300
Subject: [PATCH 243/972] axi_dacfifo: Update the constraints

---
 library/axi_dacfifo/axi_dacfifo_constr.xdc | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo_constr.xdc b/library/axi_dacfifo/axi_dacfifo_constr.xdc
index 0343601bc..55262bad7 100644
--- a/library/axi_dacfifo/axi_dacfifo_constr.xdc
+++ b/library/axi_dacfifo/axi_dacfifo_constr.xdc
@@ -1,8 +1,14 @@
 
-set_property ASYNC_REG TRUE \
-  [get_cells -hier *dac_dovf_m_reg*] \
-  [get_cells -hier *dac_xfer_req_m_reg*] \
-  [get_cells -hier *dac_dunf_m_reg*]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *xfer_req_m*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *xfer_last_m*}]
+
+set_false_path -to [get_cells axi_xfer_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -to [get_cells *dma_rst_m1* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+
+set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
 
 set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
   -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]

From 183c67aca038708a5f6f01e142098c7472396326 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 26 May 2016 13:59:59 +0300
Subject: [PATCH 244/972] axi_dacfifo: Update the axi write controller

Do some refactoring and add a DMA beat counter.
---
 library/axi_dacfifo/axi_dacfifo_dac.v |   6 +-
 library/axi_dacfifo/axi_dacfifo_wr.v  | 372 ++++++++++++++++----------
 2 files changed, 243 insertions(+), 135 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 3dd620f2a..60c88ac62 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -227,7 +227,11 @@ module axi_dacfifo_dac (
   // CDC for xfer_req signal
 
   always @(posedge dac_clk) begin
-    dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
+    if (dac_rst == 1'b1) begin
+      dac_xfer_req_m <= 3'b0;
+    end else begin
+      dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
+    end
   end
 
   assign dac_xfer_out = dac_xfer_req_m[2];
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index 71c4ccd95..bec106942 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -93,24 +93,27 @@ module axi_dacfifo_wr (
 
   parameter       AXI_DATA_WIDTH = 512;
   parameter       DMA_DATA_WIDTH = 64;
-  parameter       AXI_SIZE = 2;
-  parameter       AXI_LENGTH = 15;
+  parameter       AXI_SIZE = 6;                     // axi_awsize format
+  parameter       AXI_LENGTH = 15;                  // axi_awlength format
   parameter       AXI_ADDRESS = 32'h00000000;
   parameter       AXI_ADDRESS_LIMIT = 32'h00000000;
+  parameter       DMA_MEM_ADDRESS_WIDTH = 8;
 
   // for the syncronization buffer
 
-  localparam      MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
-  localparam      DMA_MADDRESS_WIDTH = 8;
-  localparam      AXI_MADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MADDRESS_WIDTH :
-                                       (MEM_RATIO == 2) ? (DMA_MADDRESS_WIDTH - 1) :
-                                       (MEM_RATIO == 4) ? (DMA_MADDRESS_WIDTH - 2) :
-                                       (DMA_MADDRESS_WIDTH - 3);
+  localparam      MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;  // Max supported MEM_RATIO is 16
+  localparam      AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH :
+                                       (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) :
+                                       (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) :
+                                       (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) :
+                                                          (DMA_MEM_ADDRESS_WIDTH - 4);
 
   // for the AXI interface
 
   localparam      AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
+  localparam      DMA_BYTE_WIDTH = DMA_DATA_WIDTH/8;
   localparam      AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;
+  localparam      DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4;
 
   // dma fifo interface
 
@@ -156,30 +159,39 @@ module axi_dacfifo_wr (
 
   output                                    axi_werror;
 
-  // internal register
+  // registers
 
-  reg     [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_waddr = 'd0;
-  reg     [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_waddr_g = 'd0;
-  reg     [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_addr_diff = 'd0;
-  reg     [(AXI_MADDRESS_WIDTH-1):0]        dma_mem_raddr_m1 = 'd0;
-  reg     [(AXI_MADDRESS_WIDTH-1):0]        dma_mem_raddr_m2 = 'd0;
-  reg     [(AXI_MADDRESS_WIDTH-1):0]        dma_mem_raddr = 'd0;
+  reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     dma_mem_waddr = 'd0;
+  reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     dma_mem_waddr_g = 'd0;
+  reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     dma_mem_addr_diff = 'd0;
+  reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m1 = 'd0;
+  reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m2 = 'd0;
+  reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr = 'd0;
   reg                                       dma_ready = 'd0;
   reg                                       dma_rst_m1 = 1'b0;
   reg                                       dma_rst_m2 = 1'b0;
-  reg     [31:0]                            dma_last_addr = 32'b0;
+  reg     [ 2:0]                            dma_mem_last_read_toggle_m = 3'b0;
   reg     [31:0]                            dma_addr_cnt = 32'b0;
+  reg     [31:0]                            dma_last_addr = 32'b0;
+
 
   reg     [ 2:0]                            axi_xfer_req_m = 3'b0;
   reg     [ 2:0]                            axi_xfer_last_m = 3'b0;
-  reg     [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr_m1 = 'b0;
-  reg     [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr_m2 = 'b0;
-  reg     [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr = 'b0;
-  reg                                       axi_mem_ready = 'b0;
-  reg                                       axi_mem_ready_d = 'b0;
-  reg     [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata_d = 'b0;
-  reg     [(AXI_MADDRESS_WIDTH-1):0]        axi_mem_raddr = 'd0;
-  reg     [(AXI_MADDRESS_WIDTH-1):0]        axi_mem_raddr_g = 'd0;
+
+  reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr_m1 = 'b0;
+  reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr_m2 = 'b0;
+  reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr = 'b0;
+  reg                                       axi_mem_valid = 'b0;
+  reg                                       axi_mem_valid_d = 'b0;
+  reg                                       axi_mem_last = 1'b0;
+  reg                                       axi_mem_last_d = 1'b0;
+  reg     [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata = 'b0;
+  reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     axi_mem_raddr = 'd0;
+  reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     axi_mem_raddr_g = 'd0;
+  reg                                       axi_mem_read_en = 1'b0;
+  reg                                       axi_mem_read_en_d = 1'b0;
+  reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     axi_mem_addr_diff = 'b0;
+  reg                                       axi_mem_last_read_toggle = 1'b0;
 
   reg                                       axi_reset = 1'b0;
   reg                                       axi_xfer_out = 1'b0;
@@ -188,22 +200,27 @@ module axi_dacfifo_wr (
   reg     [31:0]                            axi_awaddr = 32'b0;
   reg                                       axi_xfer_init = 1'b0;
   reg                                       axi_werror = 1'b0;
-  reg                                       axi_mem_last = 1'b0;
-  reg                                       axi_mem_last_d = 1'b0;
-  reg     [ 3:0]                            axi_wvalid_cntr = 4'b0;
+  reg     [ 3:0]                            axi_wvalid_counter = 4'b0;
+  reg                                       axi_wr_active = 1'b0;
 
+  reg                                       axi_last_transaction = 1'b0;
+  reg                                       axi_last_transaction_d = 1'b0;
 
-  // internal signal
+  // internal signals
 
-  wire    [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_addr_diff_s;
-  wire    [(DMA_MADDRESS_WIDTH-1):0]        dma_mem_raddr_s;
+  wire    [(DMA_MEM_ADDRESS_WIDTH):0]       dma_mem_addr_diff_s;
+  wire    [(DMA_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_s;
+  wire                                      dma_mem_last_read_s;
   wire                                      dma_rst_s;
 
-  wire    [(DMA_MADDRESS_WIDTH-1):0]        axi_mem_waddr_s;
-  wire                                      axi_req_s;
+  wire    [(AXI_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr_s;
+  wire    [AXI_MEM_ADDRESS_WIDTH:0]         axi_mem_addr_diff_s;
   wire    [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata_s;
-  wire                                      axi_wready_s;
   wire                                      axi_mem_last_s;
+  wire                                      axi_mem_eot_s;
+
+  wire                                      axi_waddr_ready_s;
+  wire                                      axi_wready_s;
 
   // binary to grey conversion
 
@@ -241,8 +258,45 @@ module axi_dacfifo_wr (
     end
   endfunction
 
+  // Instantiations
 
-  // syncronize the AXI interface reset
+  // An asymmetric memory to transfer data from DMAC interface to AXI Memory Map
+  // interface
+
+  ad_mem_asym #(
+    .A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH),
+    .A_DATA_WIDTH (DMA_DATA_WIDTH),
+    .B_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH),
+    .B_DATA_WIDTH (AXI_DATA_WIDTH))
+  i_mem_asym (
+    .clka (dma_clk),
+    .wea (dma_valid),
+    .addra (dma_mem_waddr),
+    .dina (dma_data),
+    .clkb (axi_clk),
+    .addrb (axi_mem_raddr),
+    .doutb (axi_mem_rdata_s));
+
+  ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
+    .clk (axi_clk),
+    .rst (axi_reset),
+    .valid (axi_mem_valid_d),
+    .last (axi_mem_last_d),
+    .data (axi_mem_rdata),
+    .inf_valid (axi_wvalid),
+    .inf_last (axi_wlast),
+    .inf_data (axi_wdata),
+    .inf_ready (axi_wready));
+
+  // fifo needs a reset
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_reset <= 1'b1;
+    end else begin
+      axi_reset <= 1'b0;
+    end
+  end
 
   always @(posedge dma_clk) begin
     dma_rst_m1 <= ~axi_resetn;
@@ -250,7 +304,59 @@ module axi_dacfifo_wr (
   end
   assign dma_rst_s = dma_rst_m2;
 
-  // write address generation for the asymetric memory
+  // Write address generation for the asymmetric memory
+
+  // There is no underflow or overflow. All the data movements are controlled by
+  // this module.
+
+  assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
+  assign dma_mem_raddr_s = (MEM_RATIO == 1) ?  dma_mem_raddr :
+                           (MEM_RATIO == 2) ? {dma_mem_raddr, 1'b0} :
+                           (MEM_RATIO == 4) ? {dma_mem_raddr, 2'b0} :
+                           (MEM_RATIO == 8) ? {dma_mem_raddr, 3'b0} :
+                                              {dma_mem_raddr, 4'b0};
+  assign dma_mem_last_read_s = dma_mem_last_read_toggle_m[2] ^ dma_mem_last_read_toggle_m[1];
+
+  always @(posedge dma_clk) begin
+    if (dma_rst_s == 1'b1) begin
+      dma_mem_waddr <= 'h0;
+      dma_mem_waddr_g <= 8'h0;
+      dma_mem_last_read_toggle_m <= 3'b0;
+    end else begin
+      dma_mem_last_read_toggle_m = {dma_mem_last_read_toggle_m[1:0], axi_mem_last_read_toggle};
+      if ((dma_xfer_req == 1'b1) && (dma_valid == 1'b1)) begin
+        dma_mem_waddr <= dma_mem_waddr + 8'b1;
+      end
+      if (dma_mem_last_read_s == 1'b1) begin
+        dma_mem_waddr <= 'h0;
+      end
+      dma_mem_waddr_g <= b2g(dma_mem_waddr);
+    end
+  end
+
+  // The memory module request data until reaches the high threshold.
+
+  always @(posedge dma_clk) begin
+    if (dma_rst_s == 1'b1) begin
+      dma_mem_addr_diff <= 'b0;
+      dma_mem_raddr_m1 <= 'b0;
+      dma_mem_raddr_m2 <= 'b0;
+      dma_mem_raddr <= 'b0;
+    end else begin
+      dma_mem_raddr_m1 <= g2b(axi_mem_raddr_g);
+      dma_mem_raddr_m2 <= dma_mem_raddr_m1;
+      dma_mem_raddr <= dma_mem_raddr_m2;
+      dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
+      if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
+        dma_ready <= 1'b0;
+      end else begin
+        dma_ready <= 1'b1;
+      end
+    end
+  end
+
+  // An absolute address counter with DMA's granularity, this address will be
+  // used on read back
 
   always @(posedge dma_clk) begin
     if (dma_rst_s == 1'b1) begin
@@ -264,53 +370,21 @@ module axi_dacfifo_wr (
     end
   end
 
-  always @(posedge dma_clk) begin
-    if (dma_rst_s == 1'b1) begin
-      dma_mem_waddr <= 8'h0;
-      dma_mem_waddr_g <= 8'h0;
-    end else begin
-      if ((dma_ready == 1'b1) && (dma_valid == 1'b1)) begin
-        dma_mem_waddr <= dma_mem_waddr + 1;
-      end
-      dma_mem_waddr_g <= b2g(dma_mem_waddr);
-    end
-  end
+  // Read address generation for the asymmetric memory
 
-  assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
-  assign dma_mem_raddr_s = (MEM_RATIO == 1) ?  dma_mem_raddr :
-                           (MEM_RATIO == 2) ? {dma_mem_raddr, 1'b0} :
-                           (MEM_RATIO == 4) ? {dma_mem_raddr, 2'b0} :
-                                              {dma_mem_raddr, 3'b0};
+  // The asymmetric memory have to have enough data for at least one AXI burst,
+  // before the controller start an AXI write transaction.
 
-  always @(posedge dma_clk) begin
-    if (dma_rst_s == 1'b1) begin
-      dma_mem_addr_diff <= 'b0;
-      dma_mem_raddr_m1 <= 'b0;
-      dma_mem_raddr_m2 <= 'b0;
-      dma_mem_raddr <= 'b0;
-    end else begin
-      dma_mem_raddr_m1 <= g2b(axi_mem_raddr_g);
-      dma_mem_raddr_m2 <= dma_mem_raddr_m1;
-      dma_mem_raddr <= dma_mem_raddr_m2;
-      dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MADDRESS_WIDTH-1:0];
-      if (dma_mem_addr_diff >= 180) begin
-        dma_ready <= 1'b0;
-      end else begin
-        dma_ready <= 1'b1;
-      end
-    end
-  end
-
-  // read address generation for the asymetric memory
+  // CDC for the memory write address, xfer_req and xfer_last
 
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
       axi_xfer_req_m <= 3'b0;
       axi_xfer_last_m <= 3'b0;
+      axi_xfer_init <= 1'b0;
       axi_mem_waddr_m1 <= 'b0;
       axi_mem_waddr_m2 <= 'b0;
       axi_mem_waddr <= 'b0;
-      axi_xfer_init <= 1'b0;
     end else begin
       axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
       axi_xfer_last_m <= {axi_xfer_last_m[1:0], dma_xfer_last};
@@ -321,39 +395,105 @@ module axi_dacfifo_wr (
     end
   end
 
+  // check if the AXI write channel is ready
+
   assign axi_wready_s = ~axi_wvalid | axi_wready;
-  assign axi_mem_ready_s = (axi_mem_raddr == axi_mem_waddr_s) ? 1'b0 : axi_wready_s;
-  assign axi_req_s = (axi_mem_raddr[1:0] == 2'h0) ? axi_mem_ready_s : 1'b0;
-  assign axi_mem_last_s = (axi_wvalid_cntr == AXI_LENGTH) ? axi_mem_ready_s : 1'b0;
+
+  // check if there is enough data in the asymmetric memory
+
   assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr :
-                           (MEM_RATIO == 2) ? axi_mem_waddr[(DMA_MADDRESS_WIDTH-1):1] :
-                           (MEM_RATIO == 4) ? axi_mem_waddr[(DMA_MADDRESS_WIDTH-1):2] :
-                                              axi_mem_waddr[(DMA_MADDRESS_WIDTH-1):3];
+                           (MEM_RATIO == 2) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):1] :
+                           (MEM_RATIO == 4) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):2] :
+                           (MEM_RATIO == 8) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):3] :
+                                              axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):4];
+
+  assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr_s} - axi_mem_raddr;
 
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
-      axi_mem_ready <= 1'b0;
-      axi_mem_ready_d <= 1'b0;
-      axi_mem_rdata_d <= 'b0;
-      axi_mem_raddr <= 'b0;
-      axi_wvalid_cntr <= 4'b0;
+      axi_mem_read_en <= 1'b0;
+      axi_mem_read_en_d <= 1'b0;
+      axi_mem_addr_diff <= 'b0;
     end else begin
-      axi_mem_ready <= axi_mem_ready_s;
+      axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0];
+      // If there is a valid request and there is enough data in the memory or it's the end of the dma transaction
+      if ((axi_xfer_req_m[2] == 1'b1) && (axi_mem_read_en == 1'b0) && (axi_wr_active == 1'b0)) begin
+        if (((axi_mem_addr_diff > AXI_LENGTH) && (axi_last_transaction == 1'b0)) ||
+             (axi_last_transaction == 1'b1) && (axi_last_transaction_d == 1'b0)) begin
+          axi_mem_read_en <= 1'b1;
+        end
+      end else if (axi_mem_last_s == 1'b1) begin
+        axi_mem_read_en <= 1'b0;
+      end
+      axi_mem_read_en_d <= axi_mem_read_en;
+    end
+  end
+
+  always @(posedge axi_clk) begin
+    if(axi_resetn == 1'b0) begin
+      axi_wr_active = 1'b0;
+    end else begin
+      if (axi_mem_read_en == 1'b1) begin
+        axi_wr_active = 1'b1;
+      end
+      if ((axi_wlast == 1'b1) && (axi_wvalid == 1'b1)) begin
+        axi_wr_active = 1'b0;
+      end
+    end
+  end
+
+  // If there is enough data and the AXI interface is ready, we can start to read
+  // out data from the memory
+
+  assign axi_mem_valid_s =  axi_mem_read_en & axi_wready_s;
+  assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_valid_s : 1'b0;
+  assign axi_mem_eot_s = axi_last_transaction_d & ~axi_last_transaction;
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_mem_valid <= 1'b0;
+      axi_mem_valid_d <= 1'b0;
+      axi_mem_last <= 1'b0;
+      axi_mem_last_d <= 1'b0;
+      axi_mem_rdata <= 'b0;
+      axi_mem_raddr <= 'b0;
+      axi_wvalid_counter <= 4'b0;
+      axi_mem_last_read_toggle <= 1'b1;
+    end else begin
+      axi_mem_valid <= axi_mem_valid_s;
+      axi_mem_valid_d <= axi_mem_valid;
       axi_mem_last <= axi_mem_last_s;
       axi_mem_last_d <= axi_mem_last;
-      axi_mem_ready_d <= axi_mem_ready;
-      axi_mem_rdata_d <= axi_mem_rdata_s;
-      if (axi_mem_ready_s == 1'b1) begin
+      axi_mem_rdata <= axi_mem_rdata_s;
+      if (axi_mem_valid_s == 1'b1) begin
         axi_mem_raddr <= axi_mem_raddr + 1;
-        axi_wvalid_cntr <= (axi_wvalid_cntr == AXI_LENGTH) ? 4'b0 : axi_wvalid_cntr + 1;
+        axi_wvalid_counter <= (axi_wvalid_counter == axi_awlen) ? 4'b0 : axi_wvalid_counter + 1;
+      end
+      if (axi_mem_eot_s == 1'b1) begin
+        axi_mem_raddr <= 'b0;
+        axi_mem_last_read_toggle <= ~axi_mem_last_read_toggle;
       end
       axi_mem_raddr_g <= b2g(axi_mem_raddr);
     end
   end
 
-  // write address generation for AXI MEMORY MAP interface
 
-  // address channel
+
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_last_transaction <= 1'b0;
+      axi_last_transaction_d <= 1'b0;
+    end else begin
+      if (axi_xfer_last_m[2] == 1'b1) begin
+        axi_last_transaction <= 1'b1;
+      end else if (axi_wlast == 1'b1) begin
+        axi_last_transaction <= 1'b0;
+      end
+      axi_last_transaction_d <= axi_last_transaction;
+    end
+  end
+
+  // AXI Memory Map interface write address channel
 
   assign axi_awid = 4'b0000;
   assign axi_awburst = 2'b01;
@@ -365,6 +505,8 @@ module axi_dacfifo_wr (
   assign axi_awlen = AXI_LENGTH;
   assign axi_awsize = AXI_SIZE;
 
+  assign axi_waddr_ready_s = axi_mem_read_en & ~axi_mem_read_en_d;
+
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
       axi_awvalid <= 'd0;
@@ -377,24 +519,24 @@ module axi_dacfifo_wr (
           axi_awvalid <= 1'b0;
         end
       end else begin
-        if (axi_req_s == 1'b1) begin
+        if (axi_waddr_ready_s == 1'b1) begin
           axi_awvalid <= 1'b1;
         end
       end
       if (axi_xfer_init == 1'b1) begin
-        axi_awaddr <= (axi_xfer_out == 1'b1) ? AXI_ADDRESS : axi_last_raddr;
+        axi_awaddr <= (axi_xfer_out == 1'b1) ? AXI_ADDRESS : axi_last_addr;
         axi_xfer_out <= 1'b0;
       end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
-        axi_awaddr <= axi_awaddr + AXI_AWINCR;
+        axi_awaddr <= axi_awaddr +  AXI_AWINCR;
       end
-      if ((axi_xfer_req_m[2] == 1) && (axi_xfer_last_m[2] == 1)) begin
-        axi_last_raddr <= axi_awaddr - AXI_AWINCR;
+      if(axi_xfer_last_m[2] == 1'b1) begin
+        axi_last_raddr <= axi_awaddr;
         axi_xfer_out <= 1'b1;
       end
     end
   end
 
-  // write channel
+  // write data channel controls
 
   assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
   assign axi_wuser = 4'b0000;
@@ -411,42 +553,4 @@ module axi_dacfifo_wr (
     end
   end
 
-  // fifo needs a reset
-
-  always @(posedge axi_clk) begin
-    if (axi_resetn == 1'b0) begin
-      axi_reset <= 1'b1;
-    end else begin
-      axi_reset <= 1'b0;
-    end
-  end
-
-  // instantiations
-
-  ad_mem_asym #(
-    .A_ADDRESS_WIDTH (DMA_MADDRESS_WIDTH),
-    .A_DATA_WIDTH (DMA_DATA_WIDTH),
-    .B_ADDRESS_WIDTH (AXI_MADDRESS_WIDTH),
-    .B_DATA_WIDTH (AXI_DATA_WIDTH))
-  i_mem_asym (
-    .clka (dma_clk),
-    .wea (dma_valid),
-    .addra (dma_mem_waddr),
-    .dina (dma_data),
-    .clkb (axi_clk),
-    .addrb (axi_mem_raddr),
-    .doutb (axi_mem_rdata_s));
-
-  ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
-    .clk (axi_clk),
-    .rst (axi_reset),
-    .valid (axi_mem_ready_d),
-    .last (axi_mem_last_d),
-    .data (axi_mem_rdata_d),
-    .inf_valid (axi_wvalid),
-    .inf_last (axi_wlast),
-    .inf_data (axi_wdata),
-    .inf_ready (axi_wready));
-
 endmodule
-

From c724c027c4449b606357c9fc074dda8cbed06f87 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 26 May 2016 14:22:27 +0300
Subject: [PATCH 245/972] axi_dacfifo: Fix the synchronizers

---
 library/axi_dacfifo/axi_dacfifo_dac.v | 22 ++++++++++++++--------
 library/axi_dacfifo/axi_dacfifo_wr.v  | 10 +++++-----
 2 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 60c88ac62..750d0f0a5 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -101,7 +101,8 @@ module axi_dacfifo_dac (
   reg     [(AXI_ADDRESS_WIDTH-1):0]   axi_mem_waddr = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_waddr_g = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr_m = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr_m1 = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr_m2 = 'd0;
   reg     [(AXI_ADDRESS_WIDTH-1):0]   axi_mem_addr_diff = 'd0;
   reg                                 axi_dready = 'd0;
 
@@ -109,7 +110,8 @@ module axi_dacfifo_dac (
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_raddr_next = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_raddr_g = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr_m = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr_m1 = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr_m2 = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_addr_diff = 'd0;
   reg                                 dac_mem_init = 1'b0;
   reg                                 dac_mem_init_d = 1'b0;
@@ -210,11 +212,13 @@ module axi_dacfifo_dac (
     if (axi_xfer_req == 1'b0) begin
       axi_mem_addr_diff <= 'd0;
       axi_mem_raddr <= 'd0;
-      axi_mem_raddr_m <= 'd0;
+      axi_mem_raddr_m1 <= 'd0;
+      axi_mem_raddr_m2 <= 'd0;
       axi_dready <= 'd0;
     end else begin
-      axi_mem_raddr_m <= g2b(dac_mem_raddr_g);
-      axi_mem_raddr <= axi_mem_raddr_m;
+      axi_mem_raddr_m1 <= dac_mem_raddr_g;
+      axi_mem_raddr_m2 <= axi_mem_raddr_m1;
+      axi_mem_raddr <= g2b(axi_mem_raddr_m2);
       axi_mem_addr_diff <= axi_mem_addr_diff_s[AXI_ADDRESS_WIDTH-1:0];
       if (axi_mem_addr_diff >= AXI_BUF_THRESHOLD_HI) begin
         axi_dready <= 1'b0;
@@ -261,10 +265,12 @@ module axi_dacfifo_dac (
   always @(posedge dac_clk) begin
     if (dac_xfer_out == 1'b0) begin
       dac_mem_waddr <= 'b0;
-      dac_mem_waddr_m <= 'b0;
+      dac_mem_waddr_m1 <= 'b0;
+      dac_mem_waddr_m2 <= 'b0;
     end else begin
-      dac_mem_waddr_m <= g2b(axi_mem_waddr_g);
-      dac_mem_waddr <= dac_mem_waddr_m;
+      dac_mem_waddr_m1 <= axi_mem_waddr_g;
+      dac_mem_waddr_m2 <= dac_mem_waddr_m1;
+      dac_mem_waddr <= g2b(dac_mem_waddr_m2);
     end
   end
 
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index bec106942..84345e722 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -343,9 +343,9 @@ module axi_dacfifo_wr (
       dma_mem_raddr_m2 <= 'b0;
       dma_mem_raddr <= 'b0;
     end else begin
-      dma_mem_raddr_m1 <= g2b(axi_mem_raddr_g);
+      dma_mem_raddr_m1 <= axi_mem_raddr_g;
       dma_mem_raddr_m2 <= dma_mem_raddr_m1;
-      dma_mem_raddr <= dma_mem_raddr_m2;
+      dma_mem_raddr <= g2b(dma_mem_raddr_m2);
       dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
       if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
         dma_ready <= 1'b0;
@@ -388,10 +388,10 @@ module axi_dacfifo_wr (
     end else begin
       axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
       axi_xfer_last_m <= {axi_xfer_last_m[1:0], dma_xfer_last};
-      axi_mem_waddr_m1 <= g2b(dma_mem_waddr_g);
-      axi_mem_waddr_m2 <= axi_mem_waddr_m1;
-      axi_mem_waddr <= axi_mem_waddr_m2;
       axi_xfer_init = ~axi_xfer_req_m[2] & axi_xfer_req_m[1];
+      axi_mem_waddr_m1 <= dma_mem_waddr_g;
+      axi_mem_waddr_m2 <= axi_mem_waddr_m1;
+      axi_mem_waddr <= g2b(axi_mem_waddr_m2);
     end
   end
 

From e1495b89f981ab2c9f1fb0e42bf28943ae086529 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 26 May 2016 14:25:36 +0300
Subject: [PATCH 246/972] axi_dacfifo: Cosmetic changes

---
 library/axi_dacfifo/axi_dacfifo.v     |  6 +++---
 library/axi_dacfifo/axi_dacfifo_dac.v |  4 ++--
 library/axi_dacfifo/axi_dacfifo_rd.v  |  8 ++++----
 library/axi_dacfifo/axi_dacfifo_wr.v  | 10 +++++-----
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index f6b3ccc96..82e236db3 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -194,8 +194,8 @@ module axi_dacfifo (
   wire    [(AXI_DATA_WIDTH-1):0]      axi_rd_data_s;
   wire                                axi_rd_ready_s;
   wire                                axi_rd_valid_s;
-  wire    [31:0]                      axi_rd_lastaddr_s;
   wire                                axi_xfer_req_s;
+  wire    [31:0]                      axi_last_addr_s;
   wire    [31:0]                      dma_last_addr_s;
 
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
@@ -217,7 +217,7 @@ module axi_dacfifo (
     .dma_valid (dma_valid),
     .dma_xfer_req (dma_xfer_req),
     .dma_xfer_last (dma_xfer_last),
-    .axi_last_raddr (axi_rd_lastaddr_s),
+    .axi_last_addr (axi_last_addr_s),
     .dma_last_addr (dma_last_addr_s),
     .axi_xfer_out (axi_xfer_req_s),
     .axi_clk (axi_clk),
@@ -253,7 +253,7 @@ module axi_dacfifo (
     .AXI_LENGTH (AXI_LENGTH),
     .AXI_ADDRESS (AXI_ADDRESS)
   ) i_rd (
-    .axi_rd_lastaddr (axi_rd_lastaddr_s),
+    .axi_last_raddr (axi_last_addr_s),
     .axi_xfer_req (axi_xfer_req_s),
     .axi_clk (axi_clk),
     .axi_resetn (axi_resetn),
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 750d0f0a5..d077b81cc 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -85,7 +85,7 @@ module axi_dacfifo_dac (
   output                              axi_dready;
   input                               axi_xfer_req;
 
-  input   [32:0]                      dma_last_addr;
+  input   [31:0]                      dma_last_addr;
 
   // dac read
 
@@ -320,7 +320,7 @@ module axi_dacfifo_dac (
       end else begin
         dac_almost_empty <= 1'b0;
       end
-      dac_dunf <= (dac_mem_addr_diff == 0) ? 1'b1 : 1'b0;
+      dac_dunf <= (dac_mem_addr_diff == 1'b0) ? 1'b1 : 1'b0;
     end
   end
 
diff --git a/library/axi_dacfifo/axi_dacfifo_rd.v b/library/axi_dacfifo/axi_dacfifo_rd.v
index f4f309fc7..aef01ac36 100644
--- a/library/axi_dacfifo/axi_dacfifo_rd.v
+++ b/library/axi_dacfifo/axi_dacfifo_rd.v
@@ -44,7 +44,7 @@ module axi_dacfifo_rd (
  // xfer last for read/write synchronization
 
   axi_xfer_req,
-  axi_rd_lastaddr,
+  axi_last_raddr,
 
   // axi read address and read data channels
 
@@ -92,7 +92,7 @@ module axi_dacfifo_rd (
   // xfer last for read/write synchronization
 
   input                           axi_xfer_req;
-  input   [ 31:0]                 axi_rd_lastaddr;
+  input   [ 31:0]                 axi_last_raddr;
 
   // axi interface
 
@@ -199,7 +199,7 @@ module axi_dacfifo_rd (
       end
       if ((axi_xfer_req_init == 1'b1)) begin
         axi_araddr <= AXI_ADDRESS;
-        axi_rd_addr_h <= axi_rd_lastaddr;
+        axi_rd_addr_h <= axi_last_raddr;
       end else if ((axi_xfer_req == 1'b1) &&
                    (axi_arvalid == 1'b1) &&
                    (axi_arready == 1'b1)) begin
@@ -220,7 +220,7 @@ module axi_dacfifo_rd (
     end else begin
       axi_ddata <= axi_rdata;
       axi_dvalid <= axi_dvalid_s;
-      if (axi_xfer_req == 1) begin
+      if (axi_xfer_req == 1'b1) begin
         axi_rready <= axi_rvalid;
       end
     end
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index 84345e722..55618ac17 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -55,7 +55,7 @@ module axi_dacfifo_wr (
 
   // syncronization for the read side
 
-  axi_last_raddr,
+  axi_last_addr,
   dma_last_addr,
   axi_xfer_out,
 
@@ -125,7 +125,7 @@ module axi_dacfifo_wr (
   input                                     dma_xfer_req;
   input                                     dma_xfer_last;
 
-  output  [31:0]                            axi_last_raddr;
+  output  [31:0]                            axi_last_addr;
   output  [31:0]                            dma_last_addr;
   output                                    axi_xfer_out;
 
@@ -195,7 +195,7 @@ module axi_dacfifo_wr (
 
   reg                                       axi_reset = 1'b0;
   reg                                       axi_xfer_out = 1'b0;
-  reg     [31:0]                            axi_last_raddr = 'b0;
+  reg     [31:0]                            axi_last_addr = 'b0;
   reg                                       axi_awvalid = 1'b0;
   reg     [31:0]                            axi_awaddr = 32'b0;
   reg                                       axi_xfer_init = 1'b0;
@@ -511,7 +511,7 @@ module axi_dacfifo_wr (
     if (axi_resetn == 1'b0) begin
       axi_awvalid <= 'd0;
       axi_awaddr <= AXI_ADDRESS;
-      axi_last_raddr <= AXI_ADDRESS;
+      axi_last_addr <= AXI_ADDRESS;
       axi_xfer_out <= 1'b0;
     end else begin
       if (axi_awvalid == 1'b1) begin
@@ -530,7 +530,7 @@ module axi_dacfifo_wr (
         axi_awaddr <= axi_awaddr +  AXI_AWINCR;
       end
       if(axi_xfer_last_m[2] == 1'b1) begin
-        axi_last_raddr <= axi_awaddr;
+        axi_last_addr <= axi_awaddr;
         axi_xfer_out <= 1'b1;
       end
     end

From a6fbf6c20b075b938e63f884320ee9c428ba0a37 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 26 May 2016 14:29:31 +0300
Subject: [PATCH 247/972] adrv9371x: Update the Makefiles

---
 projects/adrv9371x/a10soc/Makefile | 70 ++++++++++++++++++++++++++++--
 projects/adrv9371x/zc706/Makefile  |  6 +++
 2 files changed, 73 insertions(+), 3 deletions(-)

diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 77133e4f4..5b4383f8d 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -9,9 +9,73 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += system_bd.qsys
+M_DEPS += ../common/adrv9371x_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_channel.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_os.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx_channel.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dcfilter.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_iqcor.v
+M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_mul.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/altera/MULT_MACRO.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_xcvr.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
@@ -48,7 +112,7 @@ M_FLIST += *.pin
 
 
 .PHONY: all clean clean-all
-all: fmcomms2_a10soc.sof
+all: adrv9371x_a10soc.sof
 
 
 
@@ -59,9 +123,9 @@ clean-all:
 	rm -rf $(M_FLIST)
 
 
-fmcomms2_a10soc.sof: $(M_DEPS)
+adrv9371x_a10soc.sof: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_ALTERA) system_project.tcl  >> fmcomms2_a10soc_quartus.log 2>&1
+	$(M_ALTERA) system_project.tcl  >> adrv9371x_a10soc_quartus.log 2>&1
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
index 751f13fe8..933be8e1c 100644
--- a/projects/adrv9371x/zc706/Makefile
+++ b/projects/adrv9371x/zc706/Makefile
@@ -13,12 +13,16 @@ M_DEPS += ../common/adrv9371x_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_dacfifo.tcl
+M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -58,6 +62,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9371 clean
 	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -78,6 +83,7 @@ adrv9371x_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9371
 	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt

From 1853c6921dfa382e7a366a7e859b91c45c79733c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 27 May 2016 14:01:20 +0300
Subject: [PATCH 248/972] adrv9371x/zc706: Fix typo in system_top

---
 projects/adrv9371x/zc706/system_top.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/adrv9371x/zc706/system_top.v b/projects/adrv9371x/zc706/system_top.v
index 28522d8ff..c4f1eb46d 100644
--- a/projects/adrv9371x/zc706/system_top.v
+++ b/projects/adrv9371x/zc706/system_top.v
@@ -409,7 +409,7 @@ module system_top (
     .spi0_sdo_i (spi_mosi),
     .spi0_sdo_o (spi_mosi),
     .spi1_clk_i (1'd0),
-    .spi1_clk_o (1'd0),
+    .spi1_clk_o (),
     .spi1_csn_0_o (),
     .spi1_csn_1_o (),
     .spi1_csn_2_o (),

From d10dd780949709dfbe22bceabd6ae92c9bf81cc7 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri, 27 May 2016 14:59:28 +0300
Subject: [PATCH 249/972] kcu105: Update common design to 2015.4

---
 projects/common/kcu105/kcu105_system_bd.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl
index 80fc8619d..3bbc41c3f 100644
--- a/projects/common/kcu105/kcu105_system_bd.tcl
+++ b/projects/common/kcu105/kcu105_system_bd.tcl
@@ -80,14 +80,14 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
 
 # instance: ddr (mig)
 
-set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig:7.1 axi_ddr_cntrl]
+set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl]
 source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
 
 set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen]
 
 # instance: default peripherals
 
-set axi_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 axi_ethernet_clkgen]
+set axi_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 axi_ethernet_clkgen]
 set_property -dict [list CONFIG.PRIM_IN_FREQ {625}] $axi_ethernet_clkgen
 set_property -dict [list CONFIG.PRIM_SOURCE {Differential_clock_capable_pin}] $axi_ethernet_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $axi_ethernet_clkgen

From d2fc64d1308519d2baa9268adeddc0efde0f0d48 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 27 May 2016 08:37:26 -0400
Subject: [PATCH 250/972] daq3/a10gx: updates

---
 projects/daq3/a10gx/system_bd.qsys    | 168 +++++++++++----
 projects/daq3/a10gx/system_constr.sdc |  27 +++
 projects/daq3/a10gx/system_top.v      |  12 +-
 projects/daq3/common/daq3_bd.qsys     | 292 +++++++++++++++++++-------
 4 files changed, 381 insertions(+), 118 deletions(-)

diff --git a/projects/daq3/a10gx/system_bd.qsys b/projects/daq3/a10gx/system_bd.qsys
index 94756fbd1..ec6989ffe 100755
--- a/projects/daq3/a10gx/system_bd.qsys
+++ b/projects/daq3/a10gx/system_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
    element a10gx_base
    {
       datum _sortIndex
@@ -58,7 +50,7 @@
    {
       datum baseAddress
       {
-         value = "212992";
+         value = "229376";
          type = "String";
       }
    }
@@ -74,7 +66,7 @@
    {
       datum baseAddress
       {
-         value = "196608";
+         value = "212992";
          type = "String";
       }
    }
@@ -86,6 +78,54 @@
          type = "String";
       }
    }
+   element daq3.xcvr_core_jesd204_rx_s_avl
+   {
+      datum baseAddress
+      {
+         value = "254976";
+         type = "String";
+      }
+   }
+   element daq3.xcvr_core_jesd204_tx_s_avl
+   {
+      datum baseAddress
+      {
+         value = "253952";
+         type = "String";
+      }
+   }
+   element daq3.xcvr_core_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "196608";
+         type = "String";
+      }
+   }
+   element daq3.xcvr_rx_pll_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "251904";
+         type = "String";
+      }
+   }
+   element daq3.xcvr_tx_lane_pll_s_avl
+   {
+      datum baseAddress
+      {
+         value = "245760";
+         type = "String";
+      }
+   }
+   element daq3.xcvr_tx_pll_reconfig_s_avl
+   {
+      datum baseAddress
+      {
+         value = "249856";
+         type = "String";
+      }
+   }
    element sys_clk
    {
       datum _sortIndex
@@ -321,7 +361,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45I2SGE2" />
+ <parameter name="device" value="10AX115S3F45E2SGE3" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -426,14 +466,14 @@
    type="reset"
    dir="end" />
  <module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq3_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq3_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq3_axi_ad9152_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq3_axi_ad9680_dma.s_axi' start='0x30000' end='0x34000' /><slave name='daq3_axi_ad9152_dma.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq3_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq3_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq3_axi_ad9152_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq3_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq3_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq3_axi_ad9152_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq3_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq3_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq3_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq3_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq3_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
   <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
   <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
@@ -445,15 +485,15 @@
   <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
  </module>
  <module name="daq3" kind="daq3_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 29" />
-  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 29" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
@@ -471,7 +511,7 @@
   <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
   <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq3" />
  </module>
- <module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
+ <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
   <parameter name="clockFrequencyKnown" value="true" />
   <parameter name="inputClockFrequency" value="0" />
@@ -479,7 +519,7 @@
  </module>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="daq3.axi_ad9152_dma_m_axi"
    end="a10gx_base.sys_mem_s_avl">
   <parameter name="arbitrationPriority" value="1" />
@@ -488,7 +528,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="daq3.axi_ad9680_dma_m_axi"
    end="a10gx_base.sys_mem_s_avl">
   <parameter name="arbitrationPriority" value="1" />
@@ -497,7 +537,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq3.axi_ad9152_core_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -506,16 +546,16 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq3.axi_ad9152_dma_s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00034000" />
+  <parameter name="baseAddress" value="0x00038000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq3.axi_ad9680_core_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -524,16 +564,16 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq3.axi_ad9680_dma_s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
+  <parameter name="baseAddress" value="0x00034000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq3.axi_jesd_xcvr_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -541,43 +581,97 @@
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.clk"
-   end="a10gx_base.sys_clk" />
- <connection kind="clock" version="15.0" start="sys_clk.clk" end="daq3.sys_clk" />
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq3.xcvr_core_jesd204_rx_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003e400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq3.xcvr_core_jesd204_tx_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003e000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq3.xcvr_core_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00030000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq3.xcvr_rx_pll_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003d800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq3.xcvr_tx_lane_pll_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003c000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq3.xcvr_tx_pll_reconfig_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0003d000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
+   start="sys_clk.clk"
+   end="a10gx_base.sys_clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.clk" end="daq3.sys_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
    start="a10gx_base.mem_clk"
    end="daq3.mem_clk" />
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_intr"
    end="daq3.axi_ad9152_dma_intr">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_intr"
    end="daq3.axi_ad9680_dma_intr">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk_reset"
    end="a10gx_base.sys_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk_reset"
    end="daq3.sys_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.mem_rst"
    end="daq3.mem_rst" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc
index 86ef79f85..409f353e1 100644
--- a/projects/daq3/a10gx/system_constr.sdc
+++ b/projects/daq3/a10gx/system_constr.sdc
@@ -14,3 +14,30 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
   i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
   i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
  
+set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]
+
+set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v
index 8524d6ead..c04de0cac 100644
--- a/projects/daq3/a10gx/system_top.v
+++ b/projects/daq3/a10gx/system_top.v
@@ -147,8 +147,8 @@ module system_top (
 
   // board gpio
 
-  inout   [ 10:0]   gpio_bd_i;
-  inout   [ 15:0]   gpio_bd_o;
+  input   [ 10:0]   gpio_bd_i;
+  output  [ 15:0]   gpio_bd_o;
 
   // lane interface
 
@@ -209,11 +209,11 @@ module system_top (
 
   // gpio in & out are separate cores
 
-  assign sysref = gpio_o[36];
-  assign adc_pd = gpio_o[35];
-  assign dac_txen = gpio_o[34];
+  assign sysref = gpio_o[43];
+  assign adc_pd = gpio_o[42];
+  assign dac_txen = gpio_o[41];
 
-  assign gpio_i[63:38] = 26'd0;
+  assign gpio_i[63:38] = gpio_o[63:38];
   assign gpio_i[37:37] = trig;
   assign gpio_i[36:36] = adc_fdb;
   assign gpio_i[35:35] = adc_fda;
diff --git a/projects/daq3/common/daq3_bd.qsys b/projects/daq3/common/daq3_bd.qsys
index 9e7961940..50888360b 100755
--- a/projects/daq3/common/daq3_bd.qsys
+++ b/projects/daq3/common/daq3_bd.qsys
@@ -13,7 +13,7 @@
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "11";
          type = "int";
       }
    }
@@ -21,7 +21,7 @@
    {
       datum _sortIndex
       {
-         value = "14";
+         value = "16";
          type = "int";
       }
    }
@@ -37,7 +37,7 @@
    {
       datum _sortIndex
       {
-         value = "12";
+         value = "14";
          type = "int";
       }
    }
@@ -53,7 +53,7 @@
    {
       datum _sortIndex
       {
-         value = "11";
+         value = "13";
          type = "int";
       }
    }
@@ -69,7 +69,7 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "10";
          type = "int";
       }
       datum sopceditor_expanded
@@ -90,7 +90,7 @@
    {
       datum _sortIndex
       {
-         value = "15";
+         value = "17";
          type = "int";
       }
    }
@@ -406,14 +406,6 @@
          type = "String";
       }
    }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
    element mem_clk
    {
       datum _sortIndex
@@ -650,7 +642,7 @@
    {
       datum _sortIndex
       {
-         value = "10";
+         value = "12";
          type = "int";
       }
    }
@@ -658,7 +650,7 @@
    {
       datum _sortIndex
       {
-         value = "13";
+         value = "15";
          type = "int";
       }
    }
@@ -666,7 +658,7 @@
    {
       datum _sortIndex
       {
-         value = "18";
+         value = "20";
          type = "int";
       }
    }
@@ -674,7 +666,7 @@
    {
       datum _sortIndex
       {
-         value = "16";
+         value = "18";
          type = "int";
       }
    }
@@ -682,7 +674,15 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "8";
+         type = "int";
+      }
+   }
+   element xcvr_rx_pll_reconfig
+   {
+      datum _sortIndex
+      {
+         value = "9";
          type = "int";
       }
    }
@@ -690,7 +690,7 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "7";
          type = "int";
       }
    }
@@ -698,7 +698,7 @@
    {
       datum _sortIndex
       {
-         value = "17";
+         value = "19";
          type = "int";
       }
    }
@@ -710,6 +710,14 @@
          type = "int";
       }
    }
+   element xcvr_tx_pll_reconfig
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
    element xcvr_tx_ref_clk
    {
       datum _sortIndex
@@ -829,6 +837,36 @@
    internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
    type="conduit"
    dir="end" />
+ <interface
+   name="xcvr_core_jesd204_rx_s_avl"
+   internal="xcvr_core.jesd204_rx_avs"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_core_jesd204_tx_s_avl"
+   internal="xcvr_core.jesd204_tx_avs"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_core_reconfig_s_avl"
+   internal="xcvr_core.reconfig_avmm"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_rx_pll_reconfig_s_avl"
+   internal="xcvr_rx_pll_reconfig.mgmt_avalon_slave"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_tx_lane_pll_s_avl"
+   internal="xcvr_tx_lane_pll.reconfig_avmm0"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="xcvr_tx_pll_reconfig_s_avl"
+   internal="xcvr_tx_pll_reconfig.mgmt_avalon_slave"
+   type="avalon"
+   dir="end" />
  <module name="ad9680_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
   <parameter name="ADC_DATA_WIDTH" value="128" />
   <parameter name="DMA_ADDRESS_WIDTH" value="16" />
@@ -966,12 +1004,12 @@
   <parameter name="lane_rate" value="10000.0" />
   <parameter name="part_trait_bd" value="NIGHTFURY5" />
   <parameter name="part_trait_dp" value="10AX115S3F45E2SGE3" />
-  <parameter name="pll_reconfig_enable" value="false" />
+  <parameter name="pll_reconfig_enable" value="true" />
   <parameter name="pll_type" value="CMU" />
   <parameter name="rcfg_jtag_enable" value="false" />
   <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="false" />
-  <parameter name="set_csr_soft_logic_enable" value="false" />
+  <parameter name="set_capability_reg_enable" value="true" />
+  <parameter name="set_csr_soft_logic_enable" value="true" />
   <parameter name="set_prbs_soft_logic_enable" value="false" />
   <parameter name="set_user_identifier" value="0" />
   <parameter name="wrapper_opt" value="base_phy" />
@@ -994,10 +1032,10 @@
   <parameter name="TX_PLL_ENABLE" value="1" />
   <parameter name="T_PLL_LOCK_HYST" value="0" />
   <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
+  <parameter name="T_RX_ANALOGRESET" value="70000" />
   <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_ANALOGRESET" value="0" />
-  <parameter name="T_TX_DIGITALRESET" value="20" />
+  <parameter name="T_TX_ANALOGRESET" value="70000" />
+  <parameter name="T_TX_DIGITALRESET" value="70000" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="gui_pll_cal_busy" value="1" />
   <parameter name="gui_rx_auto_reset" value="0" />
@@ -1181,7 +1219,7 @@
   <parameter name="gui_en_extclkout_ports" value="false" />
   <parameter name="gui_en_lvds_ports" value="Disabled" />
   <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_en_reconf" value="true" />
   <parameter name="gui_enable_cascade_in" value="false" />
   <parameter name="gui_enable_cascade_out" value="false" />
   <parameter name="gui_enable_mif_dps" value="false" />
@@ -1287,6 +1325,16 @@
   <parameter name="system_info_device_speed_grade" value="2" />
   <parameter name="system_part_trait_speed_grade" value="2" />
  </module>
+ <module
+   name="xcvr_rx_pll_reconfig"
+   kind="altera_pll_reconfig"
+   version="15.1"
+   enabled="1">
+  <parameter name="ENABLE_BYTEENABLE" value="false" />
+  <parameter name="ENABLE_MIF" value="false" />
+  <parameter name="MIF_FILE_NAME" value="" />
+  <parameter name="device_family" value="Arria 10" />
+ </module>
  <module
    name="xcvr_rx_ref_clk"
    kind="altera_clock_bridge"
@@ -1309,7 +1357,7 @@
   <parameter name="enable_8G_path" value="1" />
   <parameter name="enable_analog_resets" value="0" />
   <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
-  <parameter name="enable_bonding_clks" value="1" />
+  <parameter name="enable_bonding_clks" value="0" />
   <parameter name="enable_cascade_out" value="0" />
   <parameter name="enable_debug_ports_parameters" value="0" />
   <parameter name="enable_fb_comp_bonding" value="0" />
@@ -1322,7 +1370,7 @@
   <parameter name="enable_pcie_clk" value="0" />
   <parameter name="enable_pld_atx_cal_busy_port" value="1" />
   <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
-  <parameter name="enable_pll_reconfig" value="0" />
+  <parameter name="enable_pll_reconfig" value="1" />
   <parameter name="generate_add_hdl_instance_example" value="0" />
   <parameter name="generate_docs" value="1" />
   <parameter name="mcgb_aux_clkin_cnt" value="0" />
@@ -1342,7 +1390,7 @@
   <parameter name="rcfg_param_vals2" value="" />
   <parameter name="rcfg_profile_cnt" value="2" />
   <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_separate_avmm_busy" value="0" />
+  <parameter name="rcfg_separate_avmm_busy" value="1" />
   <parameter name="rcfg_sv_file_enable" value="0" />
   <parameter name="rcfg_txt_file_enable" value="0" />
   <parameter name="refclk_cnt" value="1" />
@@ -1350,16 +1398,16 @@
   <parameter name="select_manual_config" value="false" />
   <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
   <parameter name="set_auto_reference_clock_frequency" value="500.0" />
-  <parameter name="set_capability_reg_enable" value="0" />
-  <parameter name="set_csr_soft_logic_enable" value="0" />
-  <parameter name="set_fref_clock_frequency" value="100.0" />
+  <parameter name="set_capability_reg_enable" value="1" />
+  <parameter name="set_csr_soft_logic_enable" value="1" />
+  <parameter name="set_fref_clock_frequency" value="156.25" />
   <parameter name="set_hip_cal_en" value="0" />
-  <parameter name="set_k_counter" value="1" />
-  <parameter name="set_l_cascade_counter" value="4" />
+  <parameter name="set_k_counter" value="2000000000" />
+  <parameter name="set_l_cascade_counter" value="15" />
   <parameter name="set_l_cascade_predivider" value="1" />
-  <parameter name="set_l_counter" value="4" />
-  <parameter name="set_m_counter" value="50" />
-  <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+  <parameter name="set_l_counter" value="16" />
+  <parameter name="set_m_counter" value="24" />
+  <parameter name="set_manual_reference_clock_frequency" value="200.0" />
   <parameter name="set_output_clock_frequency" value="5000.0" />
   <parameter name="set_ref_clk_div" value="1" />
   <parameter name="set_user_identifier" value="0" />
@@ -1544,7 +1592,7 @@
   <parameter name="gui_en_extclkout_ports" value="false" />
   <parameter name="gui_en_lvds_ports" value="Disabled" />
   <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_en_reconf" value="true" />
   <parameter name="gui_enable_cascade_in" value="false" />
   <parameter name="gui_enable_cascade_out" value="false" />
   <parameter name="gui_enable_mif_dps" value="false" />
@@ -1650,6 +1698,16 @@
   <parameter name="system_info_device_speed_grade" value="2" />
   <parameter name="system_part_trait_speed_grade" value="2" />
  </module>
+ <module
+   name="xcvr_tx_pll_reconfig"
+   kind="altera_pll_reconfig"
+   version="15.1"
+   enabled="1">
+  <parameter name="ENABLE_BYTEENABLE" value="false" />
+  <parameter name="ENABLE_MIF" value="false" />
+  <parameter name="MIF_FILE_NAME" value="" />
+  <parameter name="device_family" value="Arria 10" />
+ </module>
  <module
    name="xcvr_tx_ref_clk"
    kind="altera_clock_bridge"
@@ -1706,11 +1764,31 @@
    version="15.1"
    start="mem_clk.out_clk"
    end="axi_ad9152_dma.m_src_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_tx_pll_reconfig.mgmt_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_rx_pll_reconfig.mgmt_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="xcvr_tx_ref_clk.out_clk"
    end="xcvr_tx_lane_pll.pll_refclk0" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_core.reconfig_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_tx_lane_pll.reconfig_clk0" />
  <connection
    kind="clock"
    version="15.1"
@@ -1804,8 +1882,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="util_cpack_0.adc_ch_0"
-   end="axi_ad9680_core.adc_ch_0">
+   start="axi_ad9680_core.adc_ch_0"
+   end="util_cpack_0.adc_ch_0">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1815,8 +1893,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="util_cpack_0.adc_ch_1"
-   end="axi_ad9680_core.adc_ch_1">
+   start="axi_ad9680_core.adc_ch_1"
+   end="util_cpack_0.adc_ch_1">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1837,8 +1915,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="util_upack_0.dac_ch_0"
-   end="axi_ad9152_core.dac_ch_0">
+   start="axi_ad9152_core.dac_ch_0"
+   end="util_upack_0.dac_ch_0">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1889,17 +1967,6 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9152_core.if_dac_dunf"
-   end="axi_ad9152_dma.if_fifo_rd_underflow">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
  <connection
    kind="conduit"
    version="15.1"
@@ -1966,6 +2033,17 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9152_dma.if_fifo_rd_underflow"
+   end="axi_ad9152_core.if_dac_dunf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.1"
@@ -2046,19 +2124,8 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="axi_jesd_xcvr.if_tx_ready"
-   end="xcvr_rst_cntrl.tx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.pll_cal_busy"
-   end="xcvr_tx_lane_pll.pll_cal_busy">
+   start="xcvr_tx_lane_pll.pll_cal_busy"
+   end="xcvr_rst_cntrl.pll_cal_busy">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -2079,8 +2146,52 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="xcvr_tx_lane_pll.pll_powerdown"
-   end="xcvr_rst_cntrl.pll_powerdown">
+   start="xcvr_rst_cntrl.pll_powerdown"
+   end="xcvr_tx_lane_pll.pll_powerdown">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_pll_reconfig.reconfig_from_pll"
+   end="xcvr_tx_pll.reconfig_from_pll">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_pll.reconfig_from_pll"
+   end="xcvr_rx_pll_reconfig.reconfig_from_pll">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_pll.reconfig_to_pll"
+   end="xcvr_tx_pll_reconfig.reconfig_to_pll">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_pll_reconfig.reconfig_to_pll"
+   end="xcvr_rx_pll.reconfig_to_pll">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -2178,8 +2289,19 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="xcvr_rst_cntrl.tx_digitalreset"
-   end="xcvr_core.tx_digitalreset">
+   start="xcvr_core.tx_digitalreset"
+   end="xcvr_rst_cntrl.tx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rst_cntrl.tx_ready"
+   end="axi_jesd_xcvr.if_tx_ready">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -2275,7 +2397,22 @@
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="xcvr_rst_cntrl.reset" />
+   end="xcvr_tx_pll_reconfig.mgmt_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_rx_pll_reconfig.mgmt_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_core.reconfig_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_tx_lane_pll.reconfig_reset0" />
  <connection
    kind="reset"
    version="15.1"
@@ -2286,6 +2423,11 @@
    version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_rx_pll.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_rst_cntrl.reset" />
  <connection
    kind="reset"
    version="15.1"

From af45acfcb91d70abb2cd1ff8a8f2501e04fecfb3 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 31 May 2016 14:20:43 -0400
Subject: [PATCH 251/972] ad9371- qsys updates

---
 projects/adrv9371x/common/adrv9371x_bd.qsys | 1676 +++++++++++++++----
 1 file changed, 1325 insertions(+), 351 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.qsys b/projects/adrv9371x/common/adrv9371x_bd.qsys
index 03dab1a9e..ffb2f1e60 100755
--- a/projects/adrv9371x/common/adrv9371x_bd.qsys
+++ b/projects/adrv9371x/common/adrv9371x_bd.qsys
@@ -9,11 +9,19 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
+   element adc_os_pack
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+   }
    element adc_pack
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "15";
          type = "int";
       }
       datum sopceditor_expanded
@@ -78,30 +86,6 @@
          type = "String";
       }
    }
-   element avl_xcvr_os_rx
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element avl_xcvr_rx
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element avl_xcvr_tx
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
    element axi_ad9371
    {
       datum _sortIndex
@@ -110,11 +94,11 @@
          type = "int";
       }
    }
-   element axi_dmac_adc
+   element axi_adc_dma
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "17";
          type = "int";
       }
       datum sopceditor_expanded
@@ -123,7 +107,7 @@
          type = "boolean";
       }
    }
-   element axi_dmac_adc.s_axi
+   element axi_adc_dma.s_axi
    {
       datum baseAddress
       {
@@ -131,11 +115,11 @@
          type = "String";
       }
    }
-   element axi_dmac_dac
+   element axi_dac_dma
    {
       datum _sortIndex
       {
-         value = "11";
+         value = "18";
          type = "int";
       }
       datum sopceditor_expanded
@@ -144,7 +128,7 @@
          type = "boolean";
       }
    }
-   element axi_dmac_dac.s_axi
+   element axi_dac_dma.s_axi
    {
       datum baseAddress
       {
@@ -160,11 +144,27 @@
          type = "int";
       }
    }
+   element axi_os_adc_dma
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element axi_os_jesd_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
    element dac_upack
    {
       datum _sortIndex
       {
-         value = "10";
+         value = "16";
          type = "int";
       }
       datum sopceditor_expanded
@@ -173,14 +173,6 @@
          type = "boolean";
       }
    }
-   element rstcntrl_xcvr_tx
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
    element sys_clk
    {
       datum _sortIndex
@@ -221,6 +213,62 @@
          type = "int";
       }
    }
+   element xcvr_rx_core
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element xcvr_rx_os_core
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element xcvr_rx_os_rst_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element xcvr_rx_rst_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element xcvr_tx_core
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element xcvr_tx_lane_pll
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element xcvr_tx_rst_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
@@ -243,8 +291,38 @@
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
-   name="avl_xcvr_os_rx"
-   internal="avl_xcvr_os_rx.reconfig_avmm"
+   name="avl_rx_jesd"
+   internal="xcvr_rx_core.jesd204_rx_avs"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_rx_os_jesd"
+   internal="xcvr_rx_os_core.jesd204_rx_avs"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_rx_os_xcvr"
+   internal="xcvr_rx_os_core.reconfig_avmm"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_rx_xcvr"
+   internal="xcvr_rx_core.reconfig_avmm"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_tx_jesd"
+   internal="xcvr_tx_core.jesd204_tx_avs"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_tx_lane_pll"
+   internal="xcvr_tx_lane_pll.reconfig_avmm0"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="avl_tx_xcvr"
+   internal="xcvr_tx_core.reconfig_avmm"
    type="avalon"
    dir="end" />
  <interface
@@ -253,65 +331,105 @@
    type="avalon"
    dir="end" />
  <interface
-   name="avl_xcvr_rx"
-   internal="avl_xcvr_rx.reconfig_avmm"
-   type="avalon"
+   name="axi_adc_dma_intr"
+   internal="axi_adc_dma.interrupt_sender"
+   type="interrupt"
    dir="end" />
  <interface
-   name="avl_xcvr_tx"
-   internal="avl_xcvr_tx.jesd204_tx_avs"
-   type="avalon"
+   name="axi_adc_dma_m"
+   internal="axi_adc_dma.m_dest_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_adc_dma_s"
+   internal="axi_adc_dma.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_adc_os_dma_intr"
+   internal="axi_os_adc_dma.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_adc_os_dma_m"
+   internal="axi_os_adc_dma.m_dest_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_adc_os_dma_s"
+   internal="axi_os_adc_dma.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_dac_dma_intr"
+   internal="axi_dac_dma.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_dac_dma_m"
+   internal="axi_dac_dma.m_src_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_dac_dma_s"
+   internal="axi_dac_dma.s_axi"
+   type="axi4lite"
    dir="end" />
  <interface
    name="axi_dmac_adc_fifo_wr_clock"
-   internal="axi_dmac_adc.fifo_wr_clock" />
- <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
- <interface
-   name="axi_dmac_adc_intr"
-   internal="axi_dmac_adc.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_adc_m_dest_axi"
-   internal="axi_dmac_adc.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_adc_s_axi"
-   internal="axi_dmac_adc.s_axi"
-   type="axi4lite"
-   dir="end" />
+   internal="axi_adc_dma.fifo_wr_clock" />
+ <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_adc_dma.fifo_wr_if" />
  <interface
    name="axi_dmac_dac_fifo_rd_clock"
-   internal="axi_dmac_dac.fifo_rd_clock" />
- <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
- <interface
-   name="axi_dmac_dac_intr"
-   internal="axi_dmac_dac.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_dac_m_src_axi"
-   internal="axi_dmac_dac.m_src_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_dac_s_axi"
-   internal="axi_dmac_dac.s_axi"
-   type="axi4lite"
-   dir="end" />
+   internal="axi_dac_dma.fifo_rd_clock" />
+ <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dac_dma.fifo_rd_if" />
  <interface
    name="axi_jesd_xcvr"
    internal="axi_jesd_xcvr.s_axi"
    type="axi4lite"
    dir="end" />
+ <interface
+   name="axi_os_jesd_xcvr"
+   internal="axi_os_jesd_xcvr.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="rx_data"
+   internal="xcvr_rx_core.rx_serial_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_os_data"
+   internal="xcvr_rx_os_core.rx_serial_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_os_sync"
+   internal="axi_os_jesd_xcvr.if_rx_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_os_sysref"
+   internal="axi_os_jesd_xcvr.if_rx_ext_sysref_in"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_sync"
+   internal="axi_jesd_xcvr.if_rx_sync"
+   type="conduit"
+   dir="end" />
  <interface
    name="rx_sysref"
-   internal="avl_xcvr_rx.sysref"
+   internal="axi_jesd_xcvr.if_rx_ext_sysref_in"
    type="conduit"
    dir="end" />
  <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
  <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
+ <interface
+   name="tx_data"
+   internal="xcvr_tx_core.tx_serial_data"
+   type="conduit"
+   dir="end" />
  <interface
    name="tx_sync"
    internal="axi_jesd_xcvr.if_tx_sync"
@@ -327,209 +445,20 @@
    internal="xcvr_ref_clk.in_clk"
    type="clock"
    dir="end" />
+ <module name="adc_os_pack" kind="util_cpack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
+  <parameter name="NUM_OF_CHANNELS" value="2" />
+ </module>
  <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
   <parameter name="CHANNEL_DATA_WIDTH" value="16" />
   <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
- <module
-   name="avl_xcvr_os_rx"
-   kind="altera_jesd204"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="4" />
-  <parameter name="GUI_EN_CFG_F" value="false" />
-  <parameter name="HD" value="0" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="16" />
-  <parameter name="L" value="2" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="2" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="122.88" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="bonded" />
-  <parameter name="lane_rate" value="4915.2" />
-  <parameter name="part_trait_bd" value="NIGHTFURY4" />
-  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="true" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="true" />
-  <parameter name="set_csr_soft_logic_enable" value="true" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module name="avl_xcvr_rx" kind="altera_jesd204" version="15.1" enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="4" />
-  <parameter name="GUI_EN_CFG_F" value="false" />
-  <parameter name="HD" value="0" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="16" />
-  <parameter name="L" value="2" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="4" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="122.88" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="bonded" />
-  <parameter name="lane_rate" value="4915.2" />
-  <parameter name="part_trait_bd" value="NIGHTFURY4" />
-  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="true" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="true" />
-  <parameter name="set_csr_soft_logic_enable" value="false" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module name="avl_xcvr_tx" kind="altera_jesd204" version="15.1" enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="TX" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="4" />
-  <parameter name="GUI_EN_CFG_F" value="false" />
-  <parameter name="HD" value="0" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="32" />
-  <parameter name="L" value="4" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="4" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="125.0" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="bonded" />
-  <parameter name="lane_rate" value="4915.2" />
-  <parameter name="part_trait_bd" value="NIGHTFURY4" />
-  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="true" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="false" />
-  <parameter name="set_csr_soft_logic_enable" value="true" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
  <module name="axi_ad9371" kind="axi_ad9371" version="1.0" enabled="1">
   <parameter name="ADC_DATAPATH_DISABLE" value="0" />
   <parameter name="DAC_DATAPATH_DISABLE" value="0" />
   <parameter name="ID" value="0" />
  </module>
- <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
+ <module name="axi_adc_dma" kind="axi_dmac" version="1.0" enabled="1">
   <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
   <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
   <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
@@ -546,7 +475,7 @@
   <parameter name="ID" value="0" />
   <parameter name="SYNC_TRANSFER_START" value="1" />
  </module>
- <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
+ <module name="axi_dac_dma" kind="axi_dmac" version="1.0" enabled="1">
   <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
   <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
   <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
@@ -554,8 +483,8 @@
   <parameter name="AXI_SLICE_SRC" value="0" />
   <parameter name="CYCLIC" value="1" />
   <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
   <parameter name="DMA_LENGTH_WIDTH" value="24" />
   <parameter name="DMA_TYPE_DEST" value="2" />
   <parameter name="DMA_TYPE_SRC" value="0" />
@@ -569,37 +498,36 @@
   <parameter name="RX_NUM_OF_LANES" value="2" />
   <parameter name="TX_NUM_OF_LANES" value="4" />
  </module>
- <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
+ <module name="axi_os_adc_dma" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="0" />
+  <parameter name="DMA_TYPE_SRC" value="2" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
  </module>
  <module
-   name="rstcntrl_xcvr_tx"
-   kind="altera_xcvr_reset_control"
-   version="15.1"
+   name="axi_os_jesd_xcvr"
+   kind="axi_jesd_xcvr"
+   version="1.0"
    enabled="1">
-  <parameter name="CHANNELS" value="4" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="0" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="100" />
-  <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_ANALOGRESET" value="0" />
-  <parameter name="T_TX_DIGITALRESET" value="20" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="0" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="0" />
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="1" />
+  <parameter name="RX_NUM_OF_LANES" value="2" />
+  <parameter name="TX_NUM_OF_LANES" value="0" />
+ </module>
+ <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
  <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
@@ -915,31 +843,414 @@
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
+ <module name="xcvr_rx_core" kind="altera_jesd204" version="15.1" enabled="1">
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="BID" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="CS" value="0" />
+  <parameter name="DATA_PATH" value="RX" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DID" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
+  <parameter name="GUI_CFG_F" value="4" />
+  <parameter name="GUI_EN_CFG_F" value="false" />
+  <parameter name="HD" value="0" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="K" value="32" />
+  <parameter name="L" value="2" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="M" value="4" />
+  <parameter name="N" value="16" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG2" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="REFCLK_FREQ" value="122.88" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="S" value="1" />
+  <parameter name="SCR" value="1" />
+  <parameter name="SUBCLASSV" value="1" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="bonded_mode" value="non_bonded" />
+  <parameter name="lane_rate" value="4915.2" />
+  <parameter name="part_trait_bd" value="NIGHTFURY4" />
+  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
+  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="rcfg_jtag_enable" value="false" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="set_capability_reg_enable" value="true" />
+  <parameter name="set_csr_soft_logic_enable" value="true" />
+  <parameter name="set_prbs_soft_logic_enable" value="false" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="wrapper_opt" value="base_phy" />
+ </module>
+ <module
+   name="xcvr_rx_os_core"
+   kind="altera_jesd204"
+   version="15.1"
+   enabled="1">
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="BID" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="CS" value="0" />
+  <parameter name="DATA_PATH" value="RX" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DID" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
+  <parameter name="GUI_CFG_F" value="4" />
+  <parameter name="GUI_EN_CFG_F" value="false" />
+  <parameter name="HD" value="0" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="K" value="16" />
+  <parameter name="L" value="2" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="M" value="2" />
+  <parameter name="N" value="16" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="REFCLK_FREQ" value="122.88" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="S" value="1" />
+  <parameter name="SCR" value="1" />
+  <parameter name="SUBCLASSV" value="1" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="bonded_mode" value="bonded" />
+  <parameter name="lane_rate" value="4915.2" />
+  <parameter name="part_trait_bd" value="NIGHTFURY4" />
+  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
+  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="rcfg_jtag_enable" value="false" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="set_capability_reg_enable" value="true" />
+  <parameter name="set_csr_soft_logic_enable" value="true" />
+  <parameter name="set_prbs_soft_logic_enable" value="false" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="wrapper_opt" value="base_phy" />
+ </module>
+ <module
+   name="xcvr_rx_os_rst_cntrl"
+   kind="altera_xcvr_reset_control"
+   version="15.1"
+   enabled="1">
+  <parameter name="CHANNELS" value="2" />
+  <parameter name="PLLS" value="1" />
+  <parameter name="REDUCED_SIM_TIME" value="1" />
+  <parameter name="RX_ENABLE" value="1" />
+  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+  <parameter name="SYNCHRONIZE_RESET" value="1" />
+  <parameter name="SYS_CLK_IN_MHZ" value="100" />
+  <parameter name="TX_ENABLE" value="0" />
+  <parameter name="TX_PER_CHANNEL" value="0" />
+  <parameter name="TX_PLL_ENABLE" value="0" />
+  <parameter name="T_PLL_LOCK_HYST" value="0" />
+  <parameter name="T_PLL_POWERDOWN" value="1000" />
+  <parameter name="T_RX_ANALOGRESET" value="70000" />
+  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_ANALOGRESET" value="70000" />
+  <parameter name="T_TX_DIGITALRESET" value="70000" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="gui_pll_cal_busy" value="1" />
+  <parameter name="gui_rx_auto_reset" value="0" />
+  <parameter name="gui_split_interfaces" value="0" />
+  <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <module
+   name="xcvr_rx_rst_cntrl"
+   kind="altera_xcvr_reset_control"
+   version="15.1"
+   enabled="1">
+  <parameter name="CHANNELS" value="2" />
+  <parameter name="PLLS" value="1" />
+  <parameter name="REDUCED_SIM_TIME" value="1" />
+  <parameter name="RX_ENABLE" value="1" />
+  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+  <parameter name="SYNCHRONIZE_RESET" value="1" />
+  <parameter name="SYS_CLK_IN_MHZ" value="100" />
+  <parameter name="TX_ENABLE" value="0" />
+  <parameter name="TX_PER_CHANNEL" value="0" />
+  <parameter name="TX_PLL_ENABLE" value="0" />
+  <parameter name="T_PLL_LOCK_HYST" value="0" />
+  <parameter name="T_PLL_POWERDOWN" value="1000" />
+  <parameter name="T_RX_ANALOGRESET" value="70000" />
+  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_ANALOGRESET" value="70000" />
+  <parameter name="T_TX_DIGITALRESET" value="70000" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="gui_pll_cal_busy" value="1" />
+  <parameter name="gui_rx_auto_reset" value="0" />
+  <parameter name="gui_split_interfaces" value="0" />
+  <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <module name="xcvr_tx_core" kind="altera_jesd204" version="15.1" enabled="1">
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="BID" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="CS" value="0" />
+  <parameter name="DATA_PATH" value="TX" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DID" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
+  <parameter name="GUI_CFG_F" value="4" />
+  <parameter name="GUI_EN_CFG_F" value="false" />
+  <parameter name="HD" value="0" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="K" value="32" />
+  <parameter name="L" value="4" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="M" value="4" />
+  <parameter name="N" value="16" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG2" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="REFCLK_FREQ" value="125.0" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="S" value="1" />
+  <parameter name="SCR" value="1" />
+  <parameter name="SUBCLASSV" value="1" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="bonded_mode" value="non_bonded" />
+  <parameter name="lane_rate" value="4915.2" />
+  <parameter name="part_trait_bd" value="NIGHTFURY4" />
+  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
+  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="rcfg_jtag_enable" value="false" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="set_capability_reg_enable" value="false" />
+  <parameter name="set_csr_soft_logic_enable" value="true" />
+  <parameter name="set_prbs_soft_logic_enable" value="false" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="wrapper_opt" value="base_phy" />
+ </module>
+ <module
+   name="xcvr_tx_lane_pll"
+   kind="altera_xcvr_atx_pll_a10"
+   version="15.1"
+   enabled="1">
+  <parameter name="base_device" value="NIGHTFURY4" />
+  <parameter name="bw_sel" value="medium" />
+  <parameter name="device" value="10AS066N3F40E2SGE2" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="enable_16G_path" value="0" />
+  <parameter name="enable_8G_path" value="1" />
+  <parameter name="enable_analog_resets" value="0" />
+  <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
+  <parameter name="enable_bonding_clks" value="0" />
+  <parameter name="enable_cascade_out" value="0" />
+  <parameter name="enable_debug_ports_parameters" value="0" />
+  <parameter name="enable_fb_comp_bonding" value="0" />
+  <parameter name="enable_fractional" value="0" />
+  <parameter name="enable_hfreq_clk" value="0" />
+  <parameter name="enable_hip_cal_done_port" value="0" />
+  <parameter name="enable_manual_configuration" value="1" />
+  <parameter name="enable_mcgb" value="0" />
+  <parameter name="enable_mcgb_pcie_clksw" value="0" />
+  <parameter name="enable_pcie_clk" value="0" />
+  <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+  <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+  <parameter name="enable_pll_reconfig" value="1" />
+  <parameter name="generate_add_hdl_instance_example" value="0" />
+  <parameter name="generate_docs" value="1" />
+  <parameter name="mcgb_aux_clkin_cnt" value="0" />
+  <parameter name="mcgb_div" value="1" />
+  <parameter name="message_level" value="error" />
+  <parameter name="pma_width" value="64" />
+  <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+  <parameter name="prot_mode" value="Basic" />
+  <parameter name="rcfg_debug" value="0" />
+  <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+  <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
+  <parameter name="rcfg_h_file_enable" value="0" />
+  <parameter name="rcfg_jtag_enable" value="0" />
+  <parameter name="rcfg_mif_file_enable" value="0" />
+  <parameter name="rcfg_multi_enable" value="0" />
+  <parameter name="rcfg_param_vals1" value="" />
+  <parameter name="rcfg_param_vals2" value="" />
+  <parameter name="rcfg_profile_cnt" value="2" />
+  <parameter name="rcfg_profile_select" value="1" />
+  <parameter name="rcfg_separate_avmm_busy" value="1" />
+  <parameter name="rcfg_sv_file_enable" value="0" />
+  <parameter name="rcfg_txt_file_enable" value="0" />
+  <parameter name="refclk_cnt" value="1" />
+  <parameter name="refclk_index" value="0" />
+  <parameter name="select_manual_config" value="false" />
+  <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
+  <parameter name="set_auto_reference_clock_frequency" value="122.88" />
+  <parameter name="set_capability_reg_enable" value="1" />
+  <parameter name="set_csr_soft_logic_enable" value="1" />
+  <parameter name="set_fref_clock_frequency" value="156.25" />
+  <parameter name="set_hip_cal_en" value="0" />
+  <parameter name="set_k_counter" value="2000000000" />
+  <parameter name="set_l_cascade_counter" value="15" />
+  <parameter name="set_l_cascade_predivider" value="1" />
+  <parameter name="set_l_counter" value="16" />
+  <parameter name="set_m_counter" value="24" />
+  <parameter name="set_manual_reference_clock_frequency" value="200.0" />
+  <parameter name="set_output_clock_frequency" value="2457.6" />
+  <parameter name="set_ref_clk_div" value="1" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="silicon_rev" value="false" />
+  <parameter name="support_mode" value="user_mode" />
+  <parameter name="test_mode" value="0" />
+ </module>
+ <module
+   name="xcvr_tx_rst_cntrl"
+   kind="altera_xcvr_reset_control"
+   version="15.1"
+   enabled="1">
+  <parameter name="CHANNELS" value="4" />
+  <parameter name="PLLS" value="1" />
+  <parameter name="REDUCED_SIM_TIME" value="1" />
+  <parameter name="RX_ENABLE" value="0" />
+  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+  <parameter name="SYNCHRONIZE_RESET" value="1" />
+  <parameter name="SYS_CLK_IN_MHZ" value="100" />
+  <parameter name="TX_ENABLE" value="1" />
+  <parameter name="TX_PER_CHANNEL" value="0" />
+  <parameter name="TX_PLL_ENABLE" value="1" />
+  <parameter name="T_PLL_LOCK_HYST" value="0" />
+  <parameter name="T_PLL_POWERDOWN" value="1000" />
+  <parameter name="T_RX_ANALOGRESET" value="40" />
+  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_ANALOGRESET" value="70000" />
+  <parameter name="T_TX_DIGITALRESET" value="70000" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="gui_pll_cal_busy" value="1" />
+  <parameter name="gui_rx_auto_reset" value="0" />
+  <parameter name="gui_split_interfaces" value="0" />
+  <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
  <connection
    kind="avalon_streaming"
    version="15.1"
    start="axi_jesd_xcvr.if_tx_ip_avl"
-   end="avl_xcvr_tx.jesd204_tx_link" />
+   end="xcvr_tx_core.jesd204_tx_link" />
+ <connection
+   kind="avalon_streaming"
+   version="15.1"
+   start="xcvr_rx_core.jesd204_rx_link"
+   end="axi_jesd_xcvr.if_rx_ip_avl" />
+ <connection
+   kind="avalon_streaming"
+   version="15.1"
+   start="xcvr_rx_os_core.jesd204_rx_link"
+   end="axi_os_jesd_xcvr.if_rx_ip_avl" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="rstcntrl_xcvr_tx.clock" />
+   end="xcvr_tx_rst_cntrl.clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="avl_xcvr_tx.jesd204_tx_avs_clk" />
+   end="xcvr_rx_rst_cntrl.clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="axi_dmac_adc.m_dest_axi_clock" />
+   end="xcvr_rx_os_rst_cntrl.clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="axi_dmac_dac.m_src_axi_clock" />
+   end="xcvr_rx_core.jesd204_rx_avs_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_rx_os_core.jesd204_rx_avs_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_tx_core.jesd204_tx_avs_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_adc_dma.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_os_adc_dma.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_dac_dma.m_src_axi_clock" />
  <connection
    kind="clock"
    version="15.1"
@@ -948,13 +1259,38 @@
  <connection
    kind="clock"
    version="15.1"
-   start="sys_clk.out_clk"
-   end="avl_xcvr_os_rx.reconfig_clk" />
+   start="xcvr_ref_clk.out_clk"
+   end="xcvr_rx_core.pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_ref_clk.out_clk"
+   end="xcvr_rx_os_core.pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_ref_clk.out_clk"
+   end="xcvr_tx_lane_pll.pll_refclk0" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="avl_xcvr_rx.reconfig_clk" />
+   end="xcvr_rx_os_core.reconfig_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_tx_core.reconfig_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_rx_core.reconfig_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_tx_lane_pll.reconfig_clk0" />
  <connection
    kind="clock"
    version="15.1"
@@ -964,17 +1300,47 @@
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="axi_dmac_adc.s_axi_clock" />
+   end="axi_adc_dma.s_axi_clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
-   end="axi_dmac_dac.s_axi_clock" />
+   end="axi_dac_dma.s_axi_clock" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.out_clk"
    end="axi_jesd_xcvr.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_os_jesd_xcvr.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_ad9371.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="axi_os_adc_dma.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk0"
+   end="axi_ad9371.if_dac_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk0"
+   end="dac_upack.if_dac_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk0"
+   end="axi_dac_dma.if_fifo_rd_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -984,22 +1350,205 @@
    kind="clock"
    version="15.1"
    start="xcvr_pll.outclk0"
-   end="avl_xcvr_tx.txlink_clk" />
+   end="xcvr_tx_core.txlink_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="xcvr_pll.outclk1"
    end="adc_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk1"
+   end="axi_ad9371.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk1"
+   end="axi_adc_dma.if_fifo_wr_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="xcvr_pll.outclk1"
    end="axi_jesd_xcvr.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk1"
+   end="xcvr_rx_core.rxlink_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk2"
+   end="adc_os_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk2"
+   end="axi_ad9371.if_adc_os_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk2"
+   end="axi_os_adc_dma.if_fifo_wr_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk2"
+   end="axi_os_jesd_xcvr.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="xcvr_pll.outclk2"
+   end="xcvr_rx_os_core.rxlink_clk" />
  <connection
    kind="conduit"
    version="15.1"
-   start="avl_xcvr_tx.dev_sync_n"
-   end="avl_xcvr_tx.mdev_sync_n">
+   start="adc_pack.adc_ch_0"
+   end="axi_ad9371.adc_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_os_pack.adc_ch_0"
+   end="axi_ad9371.adc_os_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9371.adc_ch_1"
+   end="adc_pack.adc_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_pack.adc_ch_2"
+   end="axi_ad9371.adc_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9371.adc_ch_3"
+   end="adc_pack.adc_ch_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9371.adc_os_ch_1"
+   end="adc_os_pack.adc_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_os_core.alldev_lane_aligned"
+   end="xcvr_rx_os_core.dev_lane_aligned">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="dac_upack.dac_ch_0"
+   end="axi_ad9371.dac_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9371.dac_ch_1"
+   end="dac_upack.dac_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="dac_upack.dac_ch_2"
+   end="axi_ad9371.dac_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9371.dac_ch_3"
+   end="dac_upack.dac_ch_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_core.dev_lane_aligned"
+   end="xcvr_rx_core.alldev_lane_aligned">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_core.dev_sync_n"
+   end="axi_jesd_xcvr.if_rx_ip_sync">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_core.dev_sync_n"
+   end="xcvr_tx_core.mdev_sync_n">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1010,7 +1559,40 @@
    kind="conduit"
    version="15.1"
    start="adc_pack.if_adc_data"
-   end="axi_dmac_adc.if_fifo_wr_din">
+   end="axi_adc_dma.if_fifo_wr_din">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_os_pack.if_adc_data"
+   end="axi_os_adc_dma.if_fifo_wr_din">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9371.if_adc_rx_data"
+   end="axi_jesd_xcvr.if_rx_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_ad9371.if_adc_rx_os_data"
+   end="axi_os_jesd_xcvr.if_rx_data">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1021,7 +1603,18 @@
    kind="conduit"
    version="15.1"
    start="adc_pack.if_adc_sync"
-   end="axi_dmac_adc.if_fifo_wr_sync">
+   end="axi_adc_dma.if_fifo_wr_sync">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="adc_os_pack.if_adc_sync"
+   end="axi_os_adc_dma.if_fifo_wr_sync">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1032,7 +1625,7 @@
    kind="conduit"
    version="15.1"
    start="adc_pack.if_adc_valid"
-   end="axi_dmac_adc.if_fifo_wr_en">
+   end="axi_adc_dma.if_fifo_wr_en">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1043,7 +1636,7 @@
    kind="conduit"
    version="15.1"
    start="dac_upack.if_dac_data"
-   end="axi_dmac_dac.if_fifo_rd_dout">
+   end="axi_dac_dma.if_fifo_rd_dout">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1053,18 +1646,7 @@
  <connection
    kind="conduit"
    version="15.1"
-   start="dac_upack.if_dma_xfer_in"
-   end="axi_dmac_dac.if_fifo_rd_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_dac.if_fifo_rd_en"
+   start="axi_dac_dma.if_fifo_rd_en"
    end="dac_upack.if_dac_valid">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
@@ -1072,11 +1654,110 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_dac_dma.if_fifo_rd_underflow"
+   end="axi_ad9371.if_dac_dunf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_os_adc_dma.if_fifo_wr_en"
+   end="adc_os_pack.if_adc_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_adc_dma.if_fifo_wr_overflow"
+   end="axi_ad9371.if_adc_dovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_os_adc_dma.if_fifo_wr_overflow"
+   end="axi_ad9371.if_adc_os_dovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_jesd_xcvr.if_rx_ip_sof"
+   end="xcvr_rx_core.sof">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_os_jesd_xcvr.if_rx_ip_sync"
+   end="xcvr_rx_os_core.dev_sync_n">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_jesd_xcvr.if_rx_ip_sysref"
+   end="xcvr_rx_core.sysref">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_jesd_xcvr.if_rx_ready"
+   end="xcvr_rx_rst_cntrl.rx_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="axi_jesd_xcvr.if_tx_data"
+   end="axi_ad9371.if_dac_tx_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.1"
    start="axi_jesd_xcvr.if_tx_ip_sync"
-   end="avl_xcvr_tx.sync_n">
+   end="xcvr_tx_core.sync_n">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1087,7 +1768,40 @@
    kind="conduit"
    version="15.1"
    start="axi_jesd_xcvr.if_tx_ip_sysref"
-   end="avl_xcvr_tx.sysref">
+   end="xcvr_tx_core.sysref">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_lane_pll.pll_cal_busy"
+   end="xcvr_tx_rst_cntrl.pll_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_lane_pll.pll_locked"
+   end="xcvr_tx_rst_cntrl.pll_locked">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_lane_pll.pll_powerdown"
+   end="xcvr_tx_rst_cntrl.pll_powerdown">
   <parameter name="endPort" value="" />
   <parameter name="endPortLSB" value="0" />
   <parameter name="startPort" value="" />
@@ -1116,36 +1830,256 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_core.rx_analogreset"
+   end="xcvr_rx_rst_cntrl.rx_analogreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_os_core.rx_analogreset"
+   end="xcvr_rx_os_rst_cntrl.rx_analogreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_rst_cntrl.rx_cal_busy"
+   end="xcvr_rx_core.rx_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_os_rst_cntrl.rx_cal_busy"
+   end="xcvr_rx_os_core.rx_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_rst_cntrl.rx_digitalreset"
+   end="xcvr_rx_core.rx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_os_rst_cntrl.rx_digitalreset"
+   end="xcvr_rx_os_core.rx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_core.rx_islockedtodata"
+   end="xcvr_rx_rst_cntrl.rx_is_lockedtodata">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_os_core.rx_islockedtodata"
+   end="xcvr_rx_os_rst_cntrl.rx_is_lockedtodata">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_os_rst_cntrl.rx_ready"
+   end="axi_os_jesd_xcvr.if_rx_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_os_core.sof"
+   end="axi_os_jesd_xcvr.if_rx_ip_sof">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_rx_os_core.sysref"
+   end="axi_os_jesd_xcvr.if_rx_ip_sysref">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_core.tx_analogreset"
+   end="xcvr_tx_rst_cntrl.tx_analogreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_core.tx_cal_busy"
+   end="xcvr_tx_rst_cntrl.tx_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_rst_cntrl.tx_digitalreset"
+   end="xcvr_tx_core.tx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="15.1"
+   start="xcvr_tx_rst_cntrl.tx_ready"
+   end="axi_jesd_xcvr.if_tx_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="hssi_serial_clock"
+   version="15.1"
+   start="xcvr_tx_lane_pll.tx_serial_clk"
+   end="xcvr_tx_core.tx_serial_clk0_ch0" />
+ <connection
+   kind="hssi_serial_clock"
+   version="15.1"
+   start="xcvr_tx_lane_pll.tx_serial_clk"
+   end="xcvr_tx_core.tx_serial_clk0_ch1" />
+ <connection
+   kind="hssi_serial_clock"
+   version="15.1"
+   start="xcvr_tx_lane_pll.tx_serial_clk"
+   end="xcvr_tx_core.tx_serial_clk0_ch2" />
+ <connection
+   kind="hssi_serial_clock"
+   version="15.1"
+   start="xcvr_tx_lane_pll.tx_serial_clk"
+   end="xcvr_tx_core.tx_serial_clk0_ch3" />
  <connection
    kind="reset"
    version="15.1"
    start="axi_jesd_xcvr.if_rst"
-   end="rstcntrl_xcvr_tx.reset" />
+   end="xcvr_tx_rst_cntrl.reset" />
  <connection
    kind="reset"
    version="15.1"
-   start="axi_jesd_xcvr.if_tx_rstn"
-   end="avl_xcvr_tx.txlink_rst_n" />
+   start="axi_os_jesd_xcvr.if_rst"
+   end="xcvr_rx_os_rst_cntrl.reset" />
  <connection
    kind="reset"
    version="15.1"
-   start="sys_rst.out_reset"
+   start="axi_jesd_xcvr.if_rx_rstn"
    end="adc_pack.if_adc_rst" />
  <connection
    kind="reset"
    version="15.1"
-   start="sys_rst.out_reset"
-   end="avl_xcvr_tx.jesd204_tx_avs_rst_n" />
+   start="axi_os_jesd_xcvr.if_rx_rstn"
+   end="adc_os_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="axi_jesd_xcvr.if_rx_rstn"
+   end="xcvr_rx_core.rxlink_rst_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="axi_os_jesd_xcvr.if_rx_rstn"
+   end="xcvr_rx_os_core.rxlink_rst_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="axi_jesd_xcvr.if_tx_rstn"
+   end="xcvr_tx_core.txlink_rst_n" />
  <connection
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="axi_dmac_adc.m_dest_axi_reset" />
+   end="xcvr_rx_core.jesd204_rx_avs_rst_n" />
  <connection
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="axi_dmac_dac.m_src_axi_reset" />
+   end="xcvr_rx_os_core.jesd204_rx_avs_rst_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_tx_core.jesd204_tx_avs_rst_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_adc_dma.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_os_adc_dma.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_dac_dma.m_src_axi_reset" />
  <connection
    kind="reset"
    version="15.1"
@@ -1155,12 +2089,22 @@
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="avl_xcvr_os_rx.reconfig_reset" />
+   end="xcvr_rx_os_core.reconfig_reset" />
  <connection
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="avl_xcvr_rx.reconfig_reset" />
+   end="xcvr_tx_core.reconfig_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_rx_core.reconfig_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_tx_lane_pll.reconfig_reset0" />
  <connection
    kind="reset"
    version="15.1"
@@ -1170,17 +2114,47 @@
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="axi_dmac_adc.s_axi_reset" />
+   end="xcvr_rx_rst_cntrl.reset" />
  <connection
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
-   end="axi_dmac_dac.s_axi_reset" />
+   end="xcvr_tx_rst_cntrl.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_rx_os_rst_cntrl.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_adc_dma.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_dac_dma.s_axi_reset" />
  <connection
    kind="reset"
    version="15.1"
    start="sys_rst.out_reset"
    end="axi_jesd_xcvr.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_os_jesd_xcvr.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_ad9371.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="axi_os_adc_dma.s_axi_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
  <interconnectRequirement

From 5b2a90ffff581553ff10a943aad956bc5256f17c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 31 May 2016 14:32:09 -0400
Subject: [PATCH 252/972] adrv9371- qsys

---
 projects/adrv9371x/a10soc/system_bd.qsys | 330 ++++++++++++++++++-----
 1 file changed, 269 insertions(+), 61 deletions(-)

diff --git a/projects/adrv9371x/a10soc/system_bd.qsys b/projects/adrv9371x/a10soc/system_bd.qsys
index 72d7386ca..bde72906e 100644
--- a/projects/adrv9371x/a10soc/system_bd.qsys
+++ b/projects/adrv9371x/a10soc/system_bd.qsys
@@ -25,7 +25,7 @@
          type = "String";
       }
    }
-   element fmcomms2
+   element adrv9371x
    {
       datum _sortIndex
       {
@@ -33,6 +33,110 @@
          type = "int";
       }
    }
+   element adrv9371x.avl_rx_jesd
+   {
+      datum baseAddress
+      {
+         value = "221184";
+         type = "String";
+      }
+   }
+   element adrv9371x.avl_rx_os_jesd
+   {
+      datum baseAddress
+      {
+         value = "220160";
+         type = "String";
+      }
+   }
+   element adrv9371x.avl_rx_os_xcvr
+   {
+      datum baseAddress
+      {
+         value = "204800";
+         type = "String";
+      }
+   }
+   element adrv9371x.avl_rx_xcvr
+   {
+      datum baseAddress
+      {
+         value = "196608";
+         type = "String";
+      }
+   }
+   element adrv9371x.avl_tx_jesd
+   {
+      datum baseAddress
+      {
+         value = "219136";
+         type = "String";
+      }
+   }
+   element adrv9371x.avl_tx_lane_pll
+   {
+      datum baseAddress
+      {
+         value = "212992";
+         type = "String";
+      }
+   }
+   element adrv9371x.avl_tx_xcvr
+   {
+      datum baseAddress
+      {
+         value = "180224";
+         type = "String";
+      }
+   }
+   element adrv9371x.avl_xcvr_pll
+   {
+      datum baseAddress
+      {
+         value = "217088";
+         type = "String";
+      }
+   }
+   element adrv9371x.axi_adc_dma_s
+   {
+      datum baseAddress
+      {
+         value = "163840";
+         type = "String";
+      }
+   }
+   element adrv9371x.axi_adc_os_dma_s
+   {
+      datum baseAddress
+      {
+         value = "147456";
+         type = "String";
+      }
+   }
+   element adrv9371x.axi_dac_dma_s
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element adrv9371x.axi_jesd_xcvr
+   {
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
+   element adrv9371x.axi_os_jesd_xcvr
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
    element fmcomms2.axi_ad9361_s_axi
    {
       datum baseAddress
@@ -303,23 +407,13 @@
  <parameter name="hideFromIPCatalog" value="false" />
  <parameter name="lockedInterfaceDefinition" value="" />
  <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="fmcomms2_a10soc.qpf" />
+ <parameter name="projectName">adrv9371x_a10soc.qpf</parameter>
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="0" />
  <parameter name="testBenchDutName" value="" />
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
- <interface
-   name="ad9361_if"
-   internal="fmcomms2.axi_ad9361_device_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="delay_clk"
-   internal="fmcomms2.axi_ad9361_delay_clk"
-   type="clock"
-   dir="end" />
  <interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
  <interface
    name="hps_ddr_oct"
@@ -345,20 +439,44 @@
    internal="a10soc.hps_spi1_sclk"
    type="clock"
    dir="start" />
+ <interface
+   name="ref_clk"
+   internal="adrv9371x.xcvr_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface name="rx_data" internal="adrv9371x.rx_data" type="conduit" dir="end" />
+ <interface
+   name="rx_os_data"
+   internal="adrv9371x.rx_os_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_os_sync"
+   internal="adrv9371x.rx_os_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_os_sysref"
+   internal="adrv9371x.rx_os_sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="rx_sync" internal="adrv9371x.rx_sync" type="conduit" dir="end" />
+ <interface
+   name="rx_sysref"
+   internal="adrv9371x.rx_sysref"
+   type="conduit"
+   dir="end" />
  <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
  <interface
    name="sys_reset"
    internal="sys_clk.clk_in_reset"
    type="reset"
    dir="end" />
+ <interface name="tx_data" internal="adrv9371x.tx_data" type="conduit" dir="end" />
+ <interface name="tx_sync" internal="adrv9371x.tx_sync" type="conduit" dir="end" />
  <interface
-   name="up_enable"
-   internal="fmcomms2.axi_ad9361_up_enable"
-   type="conduit"
-   dir="end" />
- <interface
-   name="up_txnrx"
-   internal="fmcomms2.axi_ad9361_up_txnrx"
+   name="tx_sysref"
+   internal="adrv9371x.tx_sysref"
    type="conduit"
    dir="end" />
  <module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
@@ -366,30 +484,25 @@
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="2" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="1" />
   <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="2" />
-  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
+  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="7" />
+  <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="0" />
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_core.reconfig_avmm' start='0x2C000' end='0x30000' /><slave name='adrv9371x_xcvr_rx_core.reconfig_avmm' start='0x30000' end='0x32000' /><slave name='adrv9371x_xcvr_rx_os_core.reconfig_avmm' start='0x32000' end='0x34000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
   <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
  </module>
- <module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 32" />
-  <parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 32" />
+ <module name="adrv9371x" kind="adrv9371x_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_AXI_ADC_DMA_M_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_ADC_DMA_M_ADDRESS_WIDTH" value="AddressWidth = 32" />
+  <parameter name="AUTO_AXI_ADC_OS_DMA_M_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_ADC_OS_DMA_M_ADDRESS_WIDTH" value="AddressWidth = 32" />
+  <parameter name="AUTO_AXI_DAC_DMA_M_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_DAC_DMA_M_ADDRESS_WIDTH" value="AddressWidth = 32" />
   <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
@@ -397,7 +510,10 @@
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
+  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_adrv9371x</parameter>
+  <parameter name="AUTO_XCVR_REF_CLK_CLOCK_DOMAIN" value="4" />
+  <parameter name="AUTO_XCVR_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_XCVR_REF_CLK_RESET_DOMAIN" value="4" />
  </module>
  <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
@@ -408,7 +524,7 @@
  <connection
    kind="avalon"
    version="15.1"
-   start="fmcomms2.axi_dmac_adc_m_dest_axi"
+   start="adrv9371x.axi_adc_dma_m"
    end="a10soc.hps_s1_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
@@ -417,7 +533,16 @@
  <connection
    kind="avalon"
    version="15.1"
-   start="fmcomms2.axi_dmac_dac_m_src_axi"
+   start="adrv9371x.axi_adc_os_dma_m"
+   end="a10soc.hps_s1_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="adrv9371x.axi_dac_dma_m"
    end="a10soc.hps_s1_axi">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
@@ -427,73 +552,156 @@
    kind="avalon"
    version="15.1"
    start="a10soc.sys_cpu_m_avl"
-   end="fmcomms2.axi_ad9361_s_axi">
+   end="adrv9371x.avl_rx_jesd">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="baseAddress" value="0x00036000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="15.1"
    start="a10soc.sys_cpu_m_avl"
-   end="fmcomms2.axi_dmac_adc_s_axi">
+   end="adrv9371x.avl_rx_os_jesd">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00014000" />
+  <parameter name="baseAddress" value="0x00035c00" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="15.1"
    start="a10soc.sys_cpu_m_avl"
-   end="fmcomms2.axi_dmac_dac_s_axi">
+   end="adrv9371x.avl_rx_os_xcvr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00032000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_rx_xcvr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00030000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_tx_jesd">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00035800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_tx_lane_pll">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00034000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_tx_xcvr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0002c000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_xcvr_pll">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00035000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.axi_adc_dma_s">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00028000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.axi_adc_os_dma_s">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00024000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.axi_dac_dma_s">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.axi_jesd_xcvr">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00010000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.axi_os_jesd_xcvr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
  <connection
    kind="clock"
    version="15.1"
    start="sys_clk.clk"
-   end="fmcomms2.sys_clk" />
+   end="adrv9371x.sys_clk" />
  <connection
    kind="interrupt"
    version="15.1"
    start="a10soc.hps_irq0"
-   end="fmcomms2.axi_dmac_adc_intr">
+   end="adrv9371x.axi_adc_dma_intr">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
    kind="interrupt"
    version="15.1"
    start="a10soc.hps_irq0"
-   end="fmcomms2.axi_dmac_dac_intr">
+   end="adrv9371x.axi_adc_os_dma_intr">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
    version="15.1"
-   start="a10soc.hps_irq1"
-   end="fmcomms2.axi_dmac_adc_intr">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq1"
-   end="fmcomms2.axi_dmac_dac_intr">
-  <parameter name="irqNumber" value="1" />
+   start="a10soc.hps_irq0"
+   end="adrv9371x.axi_dac_dma_intr">
+  <parameter name="irqNumber" value="2" />
  </connection>
  <connection
    kind="reset"
    version="15.1"
    start="sys_clk.clk_reset"
-   end="a10soc.sys_rst_in" />
+   end="adrv9371x.sys_rst" />
  <connection
    kind="reset"
    version="15.1"
-   start="a10soc.sys_rst"
-   end="fmcomms2.sys_rst" />
+   start="sys_clk.clk_reset"
+   end="a10soc.sys_rst_in" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />

From 54f398cc36487c9a0db8d4e05cd77b0e57226d52 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Jun 2016 13:45:19 -0400
Subject: [PATCH 253/972] ad9371-hw- add dsp slice

---
 library/axi_ad9371/axi_ad9371_hw.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_ad9371/axi_ad9371_hw.tcl b/library/axi_ad9371/axi_ad9371_hw.tcl
index 2fb63d294..24e732442 100755
--- a/library/axi_ad9371/axi_ad9371_hw.tcl
+++ b/library/axi_ad9371/axi_ad9371_hw.tcl
@@ -15,6 +15,7 @@ set_module_property DISPLAY_NAME axi_ad9371
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9371
 add_fileset_file MULT_MACRO.v               VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
+add_fileset_file DSP48E1.v                  VERILOG PATH $ad_hdl_dir/library/common/altera/DSP48E1.v
 add_fileset_file ad_rst.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_mul.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
 add_fileset_file ad_dds_sine.v              VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v

From a958ef27da21239b42d828b399b4654ce86e21ef Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Jun 2016 13:46:15 -0400
Subject: [PATCH 254/972] adrv9371- qsys updates

---
 projects/adrv9371x/a10soc/system_bd.qsys    | 53 +++++++++++----------
 projects/adrv9371x/common/adrv9371x_bd.qsys | 51 ++++++++++++++++++++
 2 files changed, 78 insertions(+), 26 deletions(-)

diff --git a/projects/adrv9371x/a10soc/system_bd.qsys b/projects/adrv9371x/a10soc/system_bd.qsys
index bde72906e..bbab402c3 100644
--- a/projects/adrv9371x/a10soc/system_bd.qsys
+++ b/projects/adrv9371x/a10soc/system_bd.qsys
@@ -33,6 +33,14 @@
          type = "int";
       }
    }
+   element adrv9371x.avl_ad9371_gpio
+   {
+      datum baseAddress
+      {
+         value = "222208";
+         type = "String";
+      }
+   }
    element adrv9371x.avl_rx_jesd
    {
       datum baseAddress
@@ -137,30 +145,6 @@
          type = "String";
       }
    }
-   element fmcomms2.axi_ad9361_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element fmcomms2.axi_dmac_adc_s_axi
-   {
-      datum baseAddress
-      {
-         value = "81920";
-         type = "String";
-      }
-   }
-   element fmcomms2.axi_dmac_dac_s_axi
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
    element sys_clk
    {
       datum _sortIndex
@@ -414,6 +398,7 @@
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
+ <interface name="gpio" internal="adrv9371x.ad9371_gpio" type="conduit" dir="end" />
  <interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
  <interface
    name="hps_ddr_oct"
@@ -487,12 +472,12 @@
   <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="1" />
   <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
   <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="7" />
+  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="15" />
   <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="0" />
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_core.reconfig_avmm' start='0x2C000' end='0x30000' /><slave name='adrv9371x_xcvr_rx_core.reconfig_avmm' start='0x30000' end='0x32000' /><slave name='adrv9371x_xcvr_rx_os_core.reconfig_avmm' start='0x32000' end='0x34000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_core.reconfig_avmm' start='0x2C000' end='0x30000' /><slave name='adrv9371x_xcvr_rx_core.reconfig_avmm' start='0x30000' end='0x32000' /><slave name='adrv9371x_xcvr_rx_os_core.reconfig_avmm' start='0x32000' end='0x34000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /></address-map>]]></parameter>
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
   <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
  </module>
@@ -548,6 +533,15 @@
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_ad9371_gpio">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00036400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="avalon"
    version="15.1"
@@ -671,6 +665,13 @@
    version="15.1"
    start="sys_clk.clk"
    end="adrv9371x.sys_clk" />
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10soc.hps_irq0"
+   end="adrv9371x.ad9371_gpio_irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
  <connection
    kind="interrupt"
    version="15.1"
diff --git a/projects/adrv9371x/common/adrv9371x_bd.qsys b/projects/adrv9371x/common/adrv9371x_bd.qsys
index ffb2f1e60..56f0877a7 100755
--- a/projects/adrv9371x/common/adrv9371x_bd.qsys
+++ b/projects/adrv9371x/common/adrv9371x_bd.qsys
@@ -9,6 +9,14 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
+   element ad9371_gpio
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
    element adc_os_pack
    {
       datum _sortIndex
@@ -290,6 +298,21 @@
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
+ <interface
+   name="ad9371_gpio"
+   internal="ad9371_gpio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ad9371_gpio_irq"
+   internal="ad9371_gpio.irq"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="avl_ad9371_gpio"
+   internal="ad9371_gpio.s1"
+   type="avalon"
+   dir="end" />
  <interface
    name="avl_rx_jesd"
    internal="xcvr_rx_core.jesd204_rx_avs"
@@ -445,6 +468,24 @@
    internal="xcvr_ref_clk.in_clk"
    type="clock"
    dir="end" />
+ <module
+   name="ad9371_gpio"
+   kind="altera_avalon_pio"
+   version="15.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="true" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Bidir" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="19" />
+ </module>
  <module name="adc_os_pack" kind="util_cpack" version="1.0" enabled="1">
   <parameter name="CHANNEL_DATA_WIDTH" value="32" />
   <parameter name="NUM_OF_CHANNELS" value="2" />
@@ -1206,6 +1247,11 @@
    version="15.1"
    start="xcvr_rx_os_core.jesd204_rx_link"
    end="axi_os_jesd_xcvr.if_rx_ip_avl" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="ad9371_gpio.clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -2125,6 +2171,11 @@
    version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_rx_os_rst_cntrl.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="ad9371_gpio.reset" />
  <connection
    kind="reset"
    version="15.1"

From 3832f2669ec2b2d8de2d9178d5db6e6524d19aef Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Jun 2016 13:47:10 -0400
Subject: [PATCH 255/972] axi_jesd_xcvr: support tx/rx disable

---
 library/axi_jesd_xcvr/axi_jesd_xcvr.v | 37 +++++++++++++++------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr.v b/library/axi_jesd_xcvr/axi_jesd_xcvr.v
index 149af54b9..ada3f5ef7 100644
--- a/library/axi_jesd_xcvr/axi_jesd_xcvr.v
+++ b/library/axi_jesd_xcvr/axi_jesd_xcvr.v
@@ -102,6 +102,9 @@ module axi_jesd_xcvr (
   parameter   TX_NUM_OF_LANES = 4;
   parameter   RX_NUM_OF_LANES = 4;
 
+  localparam  TX_LANECNT  = (TX_NUM_OF_LANES == 0) ? 1 : TX_NUM_OF_LANES;
+  localparam  RX_LANECNT  = (RX_NUM_OF_LANES == 0) ? 1 : RX_NUM_OF_LANES;
+
   output                                        rst;
 
   // receive interface
@@ -111,14 +114,14 @@ module axi_jesd_xcvr (
   input                                         rx_ext_sysref_in;
   output                                        rx_ext_sysref_out;
   output                                        rx_sync;
-  output  [((RX_NUM_OF_LANES* 1)-1):0]          rx_sof;
-  output  [((RX_NUM_OF_LANES*32)-1):0]          rx_data;
-  input   [((RX_NUM_OF_LANES* 1)-1):0]          rx_ready;
+  output  [((RX_LANECNT* 1)-1):0]               rx_sof;
+  output  [((RX_LANECNT*32)-1):0]               rx_data;
+  input   [((RX_LANECNT* 1)-1):0]               rx_ready;
   output                                        rx_ip_sysref;
   input                                         rx_ip_sync;
   input   [  3:0]                               rx_ip_sof;
   input                                         rx_ip_valid;
-  input   [((RX_NUM_OF_LANES*32)-1):0]          rx_ip_data;
+  input   [((RX_LANECNT*32)-1):0]               rx_ip_data;
   output                                        rx_ip_ready;
 
   // transmit interface
@@ -128,12 +131,12 @@ module axi_jesd_xcvr (
   input                                         tx_ext_sysref_in;
   output                                        tx_ext_sysref_out;
   input                                         tx_sync;
-  input   [((TX_NUM_OF_LANES*32)-1):0]          tx_data;
-  input   [((RX_NUM_OF_LANES* 1)-1):0]          tx_ready;
+  input   [((TX_LANECNT*32)-1):0]               tx_data;
+  input   [((TX_LANECNT* 1)-1):0]               tx_ready;
   output                                        tx_ip_sysref;
   output                                        tx_ip_sync;
   output                                        tx_ip_valid;
-  output  [((RX_NUM_OF_LANES*32)-1):0]          tx_ip_data;
+  output  [((TX_LANECNT*32)-1):0]               tx_ip_data;
   input                                         tx_ip_ready;
 
   // axi interface
@@ -166,7 +169,7 @@ module axi_jesd_xcvr (
   wire                                          up_clk;
   wire    [  7:0]                               status_s;
   wire    [  3:0]                               rx_ip_sof_s;
-  wire    [((RX_NUM_OF_LANES*32)-1):0]          rx_ip_data_s;
+  wire    [((RX_LANECNT*32)-1):0]               rx_ip_data_s;
   wire    [  7:0]                               rx_status_s;
   wire    [  7:0]                               tx_status_s;
   wire                                          up_wreq_s;
@@ -197,7 +200,7 @@ module axi_jesd_xcvr (
   assign rx_ip_sof_s[0] = rx_ip_sof[3];
 
   generate
-  for (n = 0; n < RX_NUM_OF_LANES; n = n + 1) begin: g_rx_swap
+  for (n = 0; n < RX_LANECNT; n = n + 1) begin: g_rx_swap
   assign rx_ip_data_s[((n*32) + 31):((n*32) + 24)] = rx_ip_data[((n*32) +  7):((n*32) +  0)];
   assign rx_ip_data_s[((n*32) + 23):((n*32) + 16)] = rx_ip_data[((n*32) + 15):((n*32) +  8)];
   assign rx_ip_data_s[((n*32) + 15):((n*32) +  8)] = rx_ip_data[((n*32) + 23):((n*32) + 16)];
@@ -206,16 +209,16 @@ module axi_jesd_xcvr (
   endgenerate
 
   generate
-  if (RX_NUM_OF_LANES < 8) begin
-  assign rx_status_s[7:RX_NUM_OF_LANES] = status_s[7:RX_NUM_OF_LANES];
-  assign rx_status_s[(RX_NUM_OF_LANES-1):0] = rx_ready;
+  if (RX_LANECNT < 8) begin
+  assign rx_status_s[7:RX_LANECNT] = status_s[7:RX_LANECNT];
+  assign rx_status_s[(RX_LANECNT-1):0] = rx_ready;
   end else begin
   assign rx_status_s = rx_ready[7:0];
   end
   endgenerate
 
   generate
-  for (n = 0; n < RX_NUM_OF_LANES; n = n + 1) begin: g_rx_align
+  for (n = 0; n < RX_LANECNT; n = n + 1) begin: g_rx_align
   ad_jesd_align i_jesd_align (
     .rx_clk (rx_clk),
     .rx_ip_sof (rx_ip_sof_s),
@@ -229,7 +232,7 @@ module axi_jesd_xcvr (
   assign tx_ip_sysref = tx_ext_sysref_out;
 
   generate
-  for (n = 0; n < TX_NUM_OF_LANES; n = n + 1) begin: g_tx_swap
+  for (n = 0; n < TX_LANECNT; n = n + 1) begin: g_tx_swap
   assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) +  7):((n*32) +  0)];
   assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) +  8)];
   assign tx_ip_data[((n*32) + 15):((n*32) +  8)] = tx_data[((n*32) + 23):((n*32) + 16)];
@@ -238,9 +241,9 @@ module axi_jesd_xcvr (
   endgenerate
 
   generate
-  if (TX_NUM_OF_LANES < 8) begin
-  assign tx_status_s[7:TX_NUM_OF_LANES] = status_s[7:TX_NUM_OF_LANES];
-  assign tx_status_s[(TX_NUM_OF_LANES-1):0] = tx_ready;
+  if (TX_LANECNT < 8) begin
+  assign tx_status_s[7:TX_LANECNT] = status_s[7:TX_LANECNT];
+  assign tx_status_s[(TX_LANECNT-1):0] = tx_ready;
   end else begin
   assign tx_status_s = tx_ready[7:0];
   end

From 46b464ed7235f497793ae29cc05f1bf2028049f4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Jun 2016 13:48:28 -0400
Subject: [PATCH 256/972] adrv9371/a10soc- qsys updates

---
 projects/adrv9371x/a10soc/system_project.tcl | 88 ++++++++++--------
 projects/adrv9371x/a10soc/system_top.v       | 94 +++++++++++---------
 2 files changed, 100 insertions(+), 82 deletions(-)

diff --git a/projects/adrv9371x/a10soc/system_project.tcl b/projects/adrv9371x/a10soc/system_project.tcl
index 7dd47698b..d095a5245 100644
--- a/projects/adrv9371x/a10soc/system_project.tcl
+++ b/projects/adrv9371x/a10soc/system_project.tcl
@@ -45,6 +45,16 @@ set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_d
 set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
 set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
 
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3]
+
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
+
 set_location_assignment PIN_C14   -to rx_sync               ; ## G09  FMC_HPC_LA03_P
 set_location_assignment PIN_D14   -to rx_sync(n)            ; ## G10  FMC_HPC_LA03_N
 set_location_assignment PIN_E3    -to rx_os_sync            ; ## G27  FMC_HPC_LA25_P (Sniffer)
@@ -93,45 +103,47 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_test
 set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_reset_b        
 set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpint          
 
-set_location_assignment PIN_D4    -to ad9371_gpio_00        ; ## H19  FMC_HPC_LA15_P          
-set_location_assignment PIN_D5    -to ad9371_gpio_01        ; ## H20  FMC_HPC_LA15_N          
-set_location_assignment PIN_D6    -to ad9371_gpio_02        ; ## G18  FMC_HPC_LA16_P          
-set_location_assignment PIN_E6    -to ad9371_gpio_03        ; ## G19  FMC_HPC_LA16_N          
-set_location_assignment PIN_C2    -to ad9371_gpio_04        ; ## H25  FMC_HPC_LA21_P          
-set_location_assignment PIN_D3    -to ad9371_gpio_05        ; ## H26  FMC_HPC_LA21_N          
-set_location_assignment PIN_G7    -to ad9371_gpio_06        ; ## C22  FMC_HPC_LA18_CC_P       
-set_location_assignment PIN_H7    -to ad9371_gpio_07        ; ## C23  FMC_HPC_LA18_CC_N       
-set_location_assignment PIN_F4    -to ad9371_gpio_15        ; ## G24  FMC_HPC_LA22_P     (LVDS Pairs?)    
-set_location_assignment PIN_G4    -to ad9371_gpio_08        ; ## G25  FMC_HPC_LA22_N     (LVDS Pairs?)    
-set_location_assignment PIN_G5    -to ad9371_gpio_09        ; ## H22  FMC_HPC_LA19_P     (LVDS Pairs?)    
-set_location_assignment PIN_G6    -to ad9371_gpio_10        ; ## H23  FMC_HPC_LA19_N     (LVDS Pairs?)    
-set_location_assignment PIN_C3    -to ad9371_gpio_11        ; ## G21  FMC_HPC_LA20_P     (LVDS Pairs?)    
-set_location_assignment PIN_C4    -to ad9371_gpio_12        ; ## G22  FMC_HPC_LA20_N     (LVDS Pairs?)    
-set_location_assignment PIN_N9    -to ad9371_gpio_14        ; ## G30  FMC_HPC_LA29_P     (LVDS Pairs?)    
-set_location_assignment PIN_P10   -to ad9371_gpio_13        ; ## G31  FMC_HPC_LA29_N     (LVDS Pairs?)    
-set_location_assignment PIN_M12   -to ad9371_gpio_17        ; ## G15  FMC_HPC_LA12_P     (LVDS Pairs?)
-set_location_assignment PIN_N13   -to ad9371_gpio_16        ; ## G16  FMC_HPC_LA12_N     (LVDS Pairs?)
-set_location_assignment PIN_F14   -to ad9371_gpio_18        ; ## D12  FMC_HPC_LA05_N          
+# single ended default
 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_00
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_01
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_02
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_03
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_04
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_05
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_06
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_07
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_15
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_08
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_09
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_10
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_11
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_12
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_14
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_13
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_17
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_16
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_18
+set_location_assignment PIN_D4    -to ad9371_gpio[0]        ; ## H19  FMC_HPC_LA15_P          
+set_location_assignment PIN_D5    -to ad9371_gpio[1]        ; ## H20  FMC_HPC_LA15_N          
+set_location_assignment PIN_D6    -to ad9371_gpio[2]        ; ## G18  FMC_HPC_LA16_P          
+set_location_assignment PIN_E6    -to ad9371_gpio[3]        ; ## G19  FMC_HPC_LA16_N          
+set_location_assignment PIN_C2    -to ad9371_gpio[4]        ; ## H25  FMC_HPC_LA21_P          
+set_location_assignment PIN_D3    -to ad9371_gpio[5]        ; ## H26  FMC_HPC_LA21_N          
+set_location_assignment PIN_G7    -to ad9371_gpio[6]        ; ## C22  FMC_HPC_LA18_CC_P       
+set_location_assignment PIN_H7    -to ad9371_gpio[7]        ; ## C23  FMC_HPC_LA18_CC_N       
+set_location_assignment PIN_G4    -to ad9371_gpio[8]        ; ## G25  FMC_HPC_LA22_N     (LVDS_1N)    
+set_location_assignment PIN_G5    -to ad9371_gpio[9]        ; ## H22  FMC_HPC_LA19_P     (LVDS_2P)    
+set_location_assignment PIN_G6    -to ad9371_gpio[10]       ; ## H23  FMC_HPC_LA19_N     (LVDS_2N)    
+set_location_assignment PIN_C3    -to ad9371_gpio[11]       ; ## G21  FMC_HPC_LA20_P     (LVDS_3P)    
+set_location_assignment PIN_C4    -to ad9371_gpio[12]       ; ## G22  FMC_HPC_LA20_N     (LVDS_3N)    
+set_location_assignment PIN_P10   -to ad9371_gpio[13]       ; ## G31  FMC_HPC_LA29_N     (LVDS_4N)    
+set_location_assignment PIN_N9    -to ad9371_gpio[14]       ; ## G30  FMC_HPC_LA29_P     (LVDS_4P)    
+set_location_assignment PIN_F4    -to ad9371_gpio[15]       ; ## G24  FMC_HPC_LA22_P     (LVDS_1P)    
+set_location_assignment PIN_N13   -to ad9371_gpio[16]       ; ## G16  FMC_HPC_LA12_N     (LVDS_5N)
+set_location_assignment PIN_M12   -to ad9371_gpio[17]       ; ## G15  FMC_HPC_LA12_P     (LVDS_5P)
+set_location_assignment PIN_F14   -to ad9371_gpio[18]       ; ## D12  FMC_HPC_LA05_N
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[11]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[12]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[13]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[14]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[15]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[16]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[17]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[18]
 
 execute_flow -compile
 
diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v
index e4211a457..6d2213529 100644
--- a/projects/adrv9371x/a10soc/system_top.v
+++ b/projects/adrv9371x/a10soc/system_top.v
@@ -109,24 +109,31 @@ module system_top (
   input   [  7:0]   gpio_bd_i,
   output  [  3:0]   gpio_bd_o,
 
-  // ad9361-interface
+  // ad9371-interface
 
-  input             rx_clk_in,
-  input             rx_frame_in,
-  input   [  5:0]   rx_data_in,
-  output            tx_clk_out,
-  output            tx_frame_out,
-  output  [  5:0]   tx_data_out,
-  output            enable,
-  output            txnrx,
+  input             ref_clk0,
+  input             ref_clk1,
+  input   [  3:0]   rx_data,
+  output  [  3:0]   tx_data,
+  output            rx_sync,
+  output            rx_os_sync,
+  input             tx_sync,
+  input             sysref,
 
-  output            gpio_resetb,
-  output            gpio_sync,
-  output            gpio_en_agc,
-  output  [  3:0]   gpio_ctl,
-  input   [  7:0]   gpio_status,
+  output            ad9528_reset_b,
+  output            ad9528_sysref_req,
+  output            ad9371_tx1_enable,
+  output            ad9371_tx2_enable,
+  output            ad9371_rx1_enable,
+  output            ad9371_rx2_enable,
+  output            ad9371_test,
+  output            ad9371_reset_b,
+  input             ad9371_gpint,
+                    
+  inout   [ 18:0]   ad9371_gpio,
 
-  output            spi_csn,
+  output            spi_csn_ad9528,
+  output            spi_csn_ad9371,
   output            spi_clk,
   output            spi_mosi,
   input             spi_miso);
@@ -136,16 +143,21 @@ module system_top (
   wire    [ 31:0]   gpio_i;
   wire    [ 31:0]   gpio_o;
 
-  // gpio (ad9361)
+  // gpio (ad9371)
 
-  assign gpio_i[31:24] = gpio_o[31:24];
-  assign gpio_i[23:16] = gpio_status;
-
-  assign gpio_resetb = gpio_o[22];
-  assign gpio_sync = gpio_o[21];
-  assign gpio_en_agc = gpio_o[20];
-  assign gpio_ctl = gpio_o[19:16];
+  assign ad9371_tx1_enable = gpio_o[23];
+  assign ad9371_tx2_enable = gpio_o[22];
+  assign ad9371_rx1_enable = gpio_o[21];
+  assign ad9371_rx2_enable = gpio_o[20];
+  assign ad9371_test = gpio_o[19];
+  assign ad9371_reset_b = gpio_o[18];
+  assign ad9528_sysref_req = gpio_o[17];
+  assign ad9528_reset_b = gpio_o[16];
 
+  assign gpio_i[31:25] = gpio_o[31:25];
+  assign gpio_i[24:24] = ad9371_gpint;
+  assign gpio_i[23:16] = gpio_o[23:16];
+  
   // gpio (max-v-u21)
 
   assign gpio_i[15:8] = gpio_o[15:8];
@@ -156,21 +168,7 @@ module system_top (
   // instantiations
 
   system_bd i_system_bd (
-    .ad9361_if_rx_clk_in_p (rx_clk_in),
-    .ad9361_if_rx_clk_in_n (1'b0),
-    .ad9361_if_rx_frame_in_p (rx_frame_in),
-    .ad9361_if_rx_frame_in_n (1'b0),
-    .ad9361_if_rx_data_in_p (rx_data_in),
-    .ad9361_if_rx_data_in_n (6'd0),
-    .ad9361_if_tx_clk_out_p (tx_clk_out),
-    .ad9361_if_tx_clk_out_n (),
-    .ad9361_if_tx_frame_out_p (tx_frame_out),
-    .ad9361_if_tx_frame_out_n (),
-    .ad9361_if_tx_data_out_p (tx_data_out),
-    .ad9361_if_tx_data_out_n (),
-    .ad9361_if_enable (enable),
-    .ad9361_if_txnrx (txnrx),
-    .delay_clk_clk (1'b0),
+    .gpio_export (ad9371_gpio),
     .hps_ddr_mem_ck (hps_ddr_clk_p),
     .hps_ddr_mem_ck_n (hps_ddr_clk_n),
     .hps_ddr_mem_a (hsp_ddr_a),
@@ -239,8 +237,8 @@ module system_top (
     .hps_spi0_miso_i (spi_miso),
     .hps_spi0_ss_in_n (1'b1),
     .hps_spi0_mosi_oe (),
-    .hps_spi0_ss0_n_o (spi_csn),
-    .hps_spi0_ss1_n_o (),
+    .hps_spi0_ss0_n_o (spi_csn_ad9528),
+    .hps_spi0_ss1_n_o (spi_csn_ad9371),
     .hps_spi0_ss2_n_o (),
     .hps_spi0_ss3_n_o (),
     .hps_spi0_sclk_clk (spi_clk),
@@ -253,10 +251,18 @@ module system_top (
     .hps_spi1_ss2_n_o (),
     .hps_spi1_ss3_n_o (),
     .hps_spi1_sclk_clk (),
-    .sys_clk_clk (sys_clk),
-    .sys_reset_reset_n (sys_resetn),
-    .up_enable_up_enable (gpio_o[23]),
-    .up_txnrx_up_txnrx (gpio_o[24]));
+    .ref_clk_clk (ref_clk1),
+		.rx_data_rx_serial_data (rx_data[1:0]),
+		.rx_os_data_rx_serial_data (rx_data[3:2]),
+		.rx_os_sync_rx_sync (rx_os_sync),
+		.rx_os_sysref_rx_ext_sysref_in (sysref),
+		.rx_sync_rx_sync (rx_sync),
+		.rx_sysref_rx_ext_sysref_in (sysref),
+		.sys_clk_clk (sys_clk),
+		.sys_reset_reset_n (sys_resetn),
+		.tx_data_tx_serial_data (tx_data),
+		.tx_sync_tx_sync (tx_sync),
+		.tx_sysref_tx_ext_sysref_in (sysref));
 
 endmodule
 

From c293c0463418282275c5474db2d28f68fbb188b5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Jun 2016 13:53:09 -0400
Subject: [PATCH 257/972] hdl make updates

---
 library/axi_ad6676/Makefile                         | 4 ++++
 library/axi_ad9122/Makefile                         | 4 ++++
 library/axi_ad9144/Makefile                         | 4 ++++
 library/axi_ad9152/Makefile                         | 4 ++++
 library/axi_ad9234/Makefile                         | 4 ++++
 library/axi_ad9250/Makefile                         | 4 ++++
 library/axi_ad9265/Makefile                         | 4 ++++
 library/axi_ad9361/Makefile                         | 4 ++++
 library/axi_ad9371/Makefile                         | 4 ++++
 library/axi_ad9434/Makefile                         | 4 ++++
 library/axi_ad9467/Makefile                         | 4 ++++
 library/axi_ad9625/Makefile                         | 4 ++++
 library/axi_ad9643/Makefile                         | 4 ++++
 library/axi_ad9652/Makefile                         | 4 ++++
 library/axi_ad9671/Makefile                         | 4 ++++
 library/axi_ad9680/Makefile                         | 4 ++++
 library/axi_ad9684/Makefile                         | 4 ++++
 library/axi_ad9739a/Makefile                        | 4 ++++
 library/axi_adcfifo/Makefile                        | 4 ++++
 library/axi_clkgen/Makefile                         | 4 ++++
 library/axi_dacfifo/Makefile                        | 4 ++++
 library/axi_dmac/Makefile                           | 4 ++++
 library/axi_generic_adc/Makefile                    | 4 ++++
 library/axi_gpreg/Makefile                          | 4 ++++
 library/axi_hdmi_rx/Makefile                        | 4 ++++
 library/axi_hdmi_tx/Makefile                        | 4 ++++
 library/axi_i2s_adi/Makefile                        | 4 ++++
 library/axi_jesd_gt/Makefile                        | 4 ++++
 library/axi_mc_controller/Makefile                  | 4 ++++
 library/axi_mc_current_monitor/Makefile             | 4 ++++
 library/axi_mc_speed/Makefile                       | 4 ++++
 library/axi_spdif_rx/Makefile                       | 4 ++++
 library/axi_spdif_tx/Makefile                       | 4 ++++
 library/axi_usb_fx3/Makefile                        | 4 ++++
 library/cn0363/cn0363_dma_sequencer/Makefile        | 4 ++++
 library/cn0363/cn0363_phase_data_sync/Makefile      | 4 ++++
 library/cordic_demod/Makefile                       | 4 ++++
 library/spi_engine/axi_spi_engine/Makefile          | 4 ++++
 library/spi_engine/spi_engine_execution/Makefile    | 4 ++++
 library/spi_engine/spi_engine_interconnect/Makefile | 4 ++++
 library/spi_engine/spi_engine_offload/Makefile      | 4 ++++
 library/util_adc_pack/Makefile                      | 4 ++++
 library/util_adcfifo/Makefile                       | 4 ++++
 library/util_axis_fifo/Makefile                     | 4 ++++
 library/util_axis_resize/Makefile                   | 4 ++++
 library/util_bsplit/Makefile                        | 4 ++++
 library/util_ccat/Makefile                          | 4 ++++
 library/util_cpack/Makefile                         | 4 ++++
 library/util_dac_unpack/Makefile                    | 4 ++++
 library/util_dacfifo/Makefile                       | 4 ++++
 library/util_gmii_to_rgmii/Makefile                 | 4 ++++
 library/util_gtlb/Makefile                          | 4 ++++
 library/util_i2c_mixer/Makefile                     | 4 ++++
 library/util_jesd_gt/Makefile                       | 4 ++++
 library/util_mfifo/Makefile                         | 4 ++++
 library/util_pmod_adc/Makefile                      | 4 ++++
 library/util_pmod_fmeter/Makefile                   | 4 ++++
 library/util_rfifo/Makefile                         | 4 ++++
 library/util_sigma_delta_spi/Makefile               | 4 ++++
 library/util_tdd_sync/Makefile                      | 4 ++++
 library/util_upack/Makefile                         | 4 ++++
 library/util_wfifo/Makefile                         | 4 ++++
 projects/adrv9371x/a10soc/Makefile                  | 1 +
 63 files changed, 249 insertions(+)

diff --git a/library/axi_ad6676/Makefile b/library/axi_ad6676/Makefile
index 126ec4e10..e9a652ca6 100644
--- a/library/axi_ad6676/Makefile
+++ b/library/axi_ad6676/Makefile
@@ -32,6 +32,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9122/Makefile b/library/axi_ad9122/Makefile
index c1ff2e4dd..aa9711858 100644
--- a/library/axi_ad9122/Makefile
+++ b/library/axi_ad9122/Makefile
@@ -38,6 +38,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9144/Makefile b/library/axi_ad9144/Makefile
index 795b50715..bbe2e084d 100644
--- a/library/axi_ad9144/Makefile
+++ b/library/axi_ad9144/Makefile
@@ -34,6 +34,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9152/Makefile b/library/axi_ad9152/Makefile
index 55aaa7c77..2d3974280 100644
--- a/library/axi_ad9152/Makefile
+++ b/library/axi_ad9152/Makefile
@@ -34,6 +34,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9234/Makefile b/library/axi_ad9234/Makefile
index d783795ac..9b4a4e670 100644
--- a/library/axi_ad9234/Makefile
+++ b/library/axi_ad9234/Makefile
@@ -31,6 +31,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9250/Makefile b/library/axi_ad9250/Makefile
index d99cf1872..35499b851 100644
--- a/library/axi_ad9250/Makefile
+++ b/library/axi_ad9250/Makefile
@@ -33,6 +33,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9265/Makefile b/library/axi_ad9265/Makefile
index ae440127f..d10188c50 100644
--- a/library/axi_ad9265/Makefile
+++ b/library/axi_ad9265/Makefile
@@ -37,6 +37,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile
index ab8ddbc6d..b0bf60371 100644
--- a/library/axi_ad9361/Makefile
+++ b/library/axi_ad9361/Makefile
@@ -57,6 +57,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9371/Makefile b/library/axi_ad9371/Makefile
index 61d7ca6e1..9d6965166 100644
--- a/library/axi_ad9371/Makefile
+++ b/library/axi_ad9371/Makefile
@@ -42,6 +42,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9434/Makefile b/library/axi_ad9434/Makefile
index f8841cd1f..9813805af 100644
--- a/library/axi_ad9434/Makefile
+++ b/library/axi_ad9434/Makefile
@@ -37,6 +37,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9467/Makefile b/library/axi_ad9467/Makefile
index 1bd3c4919..bd023d81f 100644
--- a/library/axi_ad9467/Makefile
+++ b/library/axi_ad9467/Makefile
@@ -36,6 +36,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9625/Makefile b/library/axi_ad9625/Makefile
index 23f0a474b..57fdc321a 100644
--- a/library/axi_ad9625/Makefile
+++ b/library/axi_ad9625/Makefile
@@ -34,6 +34,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9643/Makefile b/library/axi_ad9643/Makefile
index f556924d4..5b4c7ff34 100644
--- a/library/axi_ad9643/Makefile
+++ b/library/axi_ad9643/Makefile
@@ -39,6 +39,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9652/Makefile b/library/axi_ad9652/Makefile
index 67cd73faf..4f38ceedb 100644
--- a/library/axi_ad9652/Makefile
+++ b/library/axi_ad9652/Makefile
@@ -38,6 +38,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9671/Makefile b/library/axi_ad9671/Makefile
index 954b0313f..dd4590b3c 100644
--- a/library/axi_ad9671/Makefile
+++ b/library/axi_ad9671/Makefile
@@ -34,6 +34,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9680/Makefile b/library/axi_ad9680/Makefile
index 7eac51c70..ce1aec3b9 100644
--- a/library/axi_ad9680/Makefile
+++ b/library/axi_ad9680/Makefile
@@ -32,6 +32,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9684/Makefile b/library/axi_ad9684/Makefile
index 3fbb3114b..dfec1c9ab 100644
--- a/library/axi_ad9684/Makefile
+++ b/library/axi_ad9684/Makefile
@@ -37,6 +37,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_ad9739a/Makefile b/library/axi_ad9739a/Makefile
index 0068469d5..f55a287ab 100644
--- a/library/axi_ad9739a/Makefile
+++ b/library/axi_ad9739a/Makefile
@@ -36,6 +36,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_adcfifo/Makefile b/library/axi_adcfifo/Makefile
index 91db65830..629722ba8 100644
--- a/library/axi_adcfifo/Makefile
+++ b/library/axi_adcfifo/Makefile
@@ -28,6 +28,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_clkgen/Makefile b/library/axi_clkgen/Makefile
index 790233395..e403b516b 100644
--- a/library/axi_clkgen/Makefile
+++ b/library/axi_clkgen/Makefile
@@ -24,6 +24,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_dacfifo/Makefile b/library/axi_dacfifo/Makefile
index f84dfb477..f943c069d 100644
--- a/library/axi_dacfifo/Makefile
+++ b/library/axi_dacfifo/Makefile
@@ -25,6 +25,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile
index 7c9e6bc4a..2565a8954 100644
--- a/library/axi_dmac/Makefile
+++ b/library/axi_dmac/Makefile
@@ -40,6 +40,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_generic_adc/Makefile b/library/axi_generic_adc/Makefile
index ef3361cc4..bde2c8023 100644
--- a/library/axi_generic_adc/Makefile
+++ b/library/axi_generic_adc/Makefile
@@ -27,6 +27,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_gpreg/Makefile b/library/axi_gpreg/Makefile
index f8a659395..a83047d14 100644
--- a/library/axi_gpreg/Makefile
+++ b/library/axi_gpreg/Makefile
@@ -25,6 +25,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_hdmi_rx/Makefile b/library/axi_hdmi_rx/Makefile
index d08123f0f..ef6052d84 100644
--- a/library/axi_hdmi_rx/Makefile
+++ b/library/axi_hdmi_rx/Makefile
@@ -35,6 +35,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_hdmi_tx/Makefile b/library/axi_hdmi_tx/Makefile
index 39f79bd36..927014fa1 100644
--- a/library/axi_hdmi_tx/Makefile
+++ b/library/axi_hdmi_tx/Makefile
@@ -36,6 +36,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_i2s_adi/Makefile b/library/axi_i2s_adi/Makefile
index 04e05795e..774b543fa 100644
--- a/library/axi_i2s_adi/Makefile
+++ b/library/axi_i2s_adi/Makefile
@@ -30,6 +30,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_jesd_gt/Makefile b/library/axi_jesd_gt/Makefile
index b8d0e78bd..fd6220adc 100644
--- a/library/axi_jesd_gt/Makefile
+++ b/library/axi_jesd_gt/Makefile
@@ -43,6 +43,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_mc_controller/Makefile b/library/axi_mc_controller/Makefile
index d1e1e455a..a63f1aefc 100644
--- a/library/axi_mc_controller/Makefile
+++ b/library/axi_mc_controller/Makefile
@@ -32,6 +32,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_mc_current_monitor/Makefile b/library/axi_mc_current_monitor/Makefile
index 5df04372d..711f9cffb 100644
--- a/library/axi_mc_current_monitor/Makefile
+++ b/library/axi_mc_current_monitor/Makefile
@@ -30,6 +30,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_mc_speed/Makefile b/library/axi_mc_speed/Makefile
index 53fa8b598..f5b5fc941 100644
--- a/library/axi_mc_speed/Makefile
+++ b/library/axi_mc_speed/Makefile
@@ -31,6 +31,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_spdif_rx/Makefile b/library/axi_spdif_rx/Makefile
index d56a4b265..7b503cbd6 100644
--- a/library/axi_spdif_rx/Makefile
+++ b/library/axi_spdif_rx/Makefile
@@ -28,6 +28,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_spdif_tx/Makefile b/library/axi_spdif_tx/Makefile
index bf7a33117..d1415571a 100644
--- a/library/axi_spdif_tx/Makefile
+++ b/library/axi_spdif_tx/Makefile
@@ -26,6 +26,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/axi_usb_fx3/Makefile b/library/axi_usb_fx3/Makefile
index 54123fcfc..2e981685b 100644
--- a/library/axi_usb_fx3/Makefile
+++ b/library/axi_usb_fx3/Makefile
@@ -23,6 +23,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/cn0363/cn0363_dma_sequencer/Makefile b/library/cn0363/cn0363_dma_sequencer/Makefile
index 29972c388..c1f55b1dc 100644
--- a/library/cn0363/cn0363_dma_sequencer/Makefile
+++ b/library/cn0363/cn0363_dma_sequencer/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/cn0363/cn0363_phase_data_sync/Makefile b/library/cn0363/cn0363_phase_data_sync/Makefile
index 33cf98cdd..e9324860b 100644
--- a/library/cn0363/cn0363_phase_data_sync/Makefile
+++ b/library/cn0363/cn0363_phase_data_sync/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/cordic_demod/Makefile b/library/cordic_demod/Makefile
index 4b2891ff3..c0621be0e 100644
--- a/library/cordic_demod/Makefile
+++ b/library/cordic_demod/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/spi_engine/axi_spi_engine/Makefile b/library/spi_engine/axi_spi_engine/Makefile
index def1365cf..f915b7cf9 100644
--- a/library/spi_engine/axi_spi_engine/Makefile
+++ b/library/spi_engine/axi_spi_engine/Makefile
@@ -24,6 +24,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/spi_engine/spi_engine_execution/Makefile b/library/spi_engine/spi_engine_execution/Makefile
index f3af6ed7d..b85a13c81 100644
--- a/library/spi_engine/spi_engine_execution/Makefile
+++ b/library/spi_engine/spi_engine_execution/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/spi_engine/spi_engine_interconnect/Makefile b/library/spi_engine/spi_engine_interconnect/Makefile
index eb521ec54..518188939 100644
--- a/library/spi_engine/spi_engine_interconnect/Makefile
+++ b/library/spi_engine/spi_engine_interconnect/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/spi_engine/spi_engine_offload/Makefile b/library/spi_engine/spi_engine_offload/Makefile
index f48f54660..0b65a0563 100644
--- a/library/spi_engine/spi_engine_offload/Makefile
+++ b/library/spi_engine/spi_engine_offload/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_adc_pack/Makefile b/library/util_adc_pack/Makefile
index 6bb0658f2..b8c7b2cbf 100644
--- a/library/util_adc_pack/Makefile
+++ b/library/util_adc_pack/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_adcfifo/Makefile b/library/util_adcfifo/Makefile
index c1d4d0865..bbe345e35 100644
--- a/library/util_adcfifo/Makefile
+++ b/library/util_adcfifo/Makefile
@@ -22,6 +22,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_axis_fifo/Makefile b/library/util_axis_fifo/Makefile
index 70453feea..f7c2168d3 100644
--- a/library/util_axis_fifo/Makefile
+++ b/library/util_axis_fifo/Makefile
@@ -24,6 +24,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_axis_resize/Makefile b/library/util_axis_resize/Makefile
index d6748f31c..bcb142830 100644
--- a/library/util_axis_resize/Makefile
+++ b/library/util_axis_resize/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_bsplit/Makefile b/library/util_bsplit/Makefile
index f411a00e7..7c81a5222 100644
--- a/library/util_bsplit/Makefile
+++ b/library/util_bsplit/Makefile
@@ -20,6 +20,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_ccat/Makefile b/library/util_ccat/Makefile
index d4b2f97fb..79ad826ed 100644
--- a/library/util_ccat/Makefile
+++ b/library/util_ccat/Makefile
@@ -20,6 +20,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_cpack/Makefile b/library/util_cpack/Makefile
index 02c8b0cfc..2614cc2ff 100644
--- a/library/util_cpack/Makefile
+++ b/library/util_cpack/Makefile
@@ -22,6 +22,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_dac_unpack/Makefile b/library/util_dac_unpack/Makefile
index 87fe8fceb..0f55eca36 100644
--- a/library/util_dac_unpack/Makefile
+++ b/library/util_dac_unpack/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_dacfifo/Makefile b/library/util_dacfifo/Makefile
index 9c7ce6257..a246111ff 100644
--- a/library/util_dacfifo/Makefile
+++ b/library/util_dacfifo/Makefile
@@ -21,6 +21,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_gmii_to_rgmii/Makefile b/library/util_gmii_to_rgmii/Makefile
index 648819e48..506c4f458 100644
--- a/library/util_gmii_to_rgmii/Makefile
+++ b/library/util_gmii_to_rgmii/Makefile
@@ -21,6 +21,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_gtlb/Makefile b/library/util_gtlb/Makefile
index 8dc22b792..3b0bacb04 100644
--- a/library/util_gtlb/Makefile
+++ b/library/util_gtlb/Makefile
@@ -29,6 +29,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_i2c_mixer/Makefile b/library/util_i2c_mixer/Makefile
index 20e5a8f0c..ed7c3d74e 100644
--- a/library/util_i2c_mixer/Makefile
+++ b/library/util_i2c_mixer/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_jesd_gt/Makefile b/library/util_jesd_gt/Makefile
index c78666c37..3835ca21c 100644
--- a/library/util_jesd_gt/Makefile
+++ b/library/util_jesd_gt/Makefile
@@ -27,6 +27,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_mfifo/Makefile b/library/util_mfifo/Makefile
index 0f3e4869c..9dca6ebea 100644
--- a/library/util_mfifo/Makefile
+++ b/library/util_mfifo/Makefile
@@ -20,6 +20,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_pmod_adc/Makefile b/library/util_pmod_adc/Makefile
index b96f79884..52d72b1ea 100644
--- a/library/util_pmod_adc/Makefile
+++ b/library/util_pmod_adc/Makefile
@@ -20,6 +20,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_pmod_fmeter/Makefile b/library/util_pmod_fmeter/Makefile
index ec1445ae3..25b76d41a 100644
--- a/library/util_pmod_fmeter/Makefile
+++ b/library/util_pmod_fmeter/Makefile
@@ -24,6 +24,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_rfifo/Makefile b/library/util_rfifo/Makefile
index b4c7de9fa..7483f8983 100644
--- a/library/util_rfifo/Makefile
+++ b/library/util_rfifo/Makefile
@@ -20,6 +20,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_sigma_delta_spi/Makefile b/library/util_sigma_delta_spi/Makefile
index bb6af71ea..e7a5a4263 100644
--- a/library/util_sigma_delta_spi/Makefile
+++ b/library/util_sigma_delta_spi/Makefile
@@ -19,6 +19,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_tdd_sync/Makefile b/library/util_tdd_sync/Makefile
index 82391ca4c..27c793e79 100644
--- a/library/util_tdd_sync/Makefile
+++ b/library/util_tdd_sync/Makefile
@@ -20,6 +20,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_upack/Makefile b/library/util_upack/Makefile
index 49a0fcda7..48d0c3e8e 100644
--- a/library/util_upack/Makefile
+++ b/library/util_upack/Makefile
@@ -22,6 +22,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/library/util_wfifo/Makefile b/library/util_wfifo/Makefile
index 0d6a5b2a5..5e41155f0 100644
--- a/library/util_wfifo/Makefile
+++ b/library/util_wfifo/Makefile
@@ -20,6 +20,10 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 5b4383f8d..a58ec1db3 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -51,6 +51,7 @@ M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_jesd_align.v
 M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/altera/DSP48E1.v
 M_DEPS += ../../../library/common/altera/MULT_MACRO.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v

From eca4d4e2a6ef795e2fe8c8ecd423c4689673f50e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Jun 2016 13:54:45 -0400
Subject: [PATCH 258/972] imageon/zc706- board updates

---
 projects/imageon/common/imageon_bd.tcl | 99 ++++++++++++++------------
 1 file changed, 52 insertions(+), 47 deletions(-)

diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl
index 412705ab3..8de628c5b 100644
--- a/projects/imageon/common/imageon_bd.tcl
+++ b/projects/imageon/common/imageon_bd.tcl
@@ -1,33 +1,28 @@
 
-# define additional ports
-
-create_bd_port -dir I spdif_rx
-
 # adv7511 (reconfigure base design)
 
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_out_clk]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_vsync]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_hsync]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_data_e]]]
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_data]]]
+
+delete_bd_objs [get_bd_ports hdmi_out_clk]
+delete_bd_objs [get_bd_ports hdmi_vsync]
+delete_bd_objs [get_bd_ports hdmi_hsync]
+delete_bd_objs [get_bd_ports hdmi_data_e]
+delete_bd_objs [get_bd_ports hdmi_data]
+
 set_property CONFIG.EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core]
 
-create_bd_port -dir O -from 15 -to 0 hdmi_es_data
-ad_connect  hdmi_es_data axi_hdmi_core/hdmi_16_es_data
+create_bd_port -dir O hdmi_tx_clk
+create_bd_port -dir O -from 15 -to 0 hdmi_tx_data
+
+ad_connect  hdmi_tx_clk axi_hdmi_core/hdmi_out_clk
+ad_connect  hdmi_tx_data axi_hdmi_core/hdmi_16_es_data
 
 # adv7611
 
-create_bd_port -dir I hdmi_rx_clk
-create_bd_port -dir I -from 15 -to 0 hdmi_rx_data
-
-# iic interface
-
-set axi_iic_imageon [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_imageon]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_imageon
-set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_imageon
-
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_imageon
-ad_connect  iic_imageon axi_iic_imageon/iic
-ad_cpu_interconnect  0x43C40000  axi_iic_imageon
-ad_cpu_interrupt ps-11 mb-11 axi_iic_imageon/iic2intc_irpt
-
-# hdmi peripherals
-
 set axi_hdmi_rx_core  [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_rx:1.0 axi_hdmi_rx_core]
 
 set axi_hdmi_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_hdmi_rx_dma]
@@ -42,14 +37,39 @@ set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_hdmi_rx_dma
 
+create_bd_port -dir I hdmi_rx_clk
+create_bd_port -dir I -from 15 -to 0 hdmi_rx_data
+
 ad_connect  hdmi_rx_clk axi_hdmi_rx_core/hdmi_rx_clk
 ad_connect  hdmi_rx_data axi_hdmi_rx_core/hdmi_rx_data
-ad_connect  hdmi_clk axi_hdmi_rx_core/hdmi_clk
-ad_connect  hdmi_clk axi_hdmi_rx_dma/fifo_wr_clk
+
+ad_connect  hdmi_rx_clk axi_hdmi_rx_dma/fifo_wr_clk
 ad_connect  axi_hdmi_rx_core/hdmi_dma_sof axi_hdmi_rx_dma/fifo_wr_sync
 ad_connect  axi_hdmi_rx_core/hdmi_dma_de axi_hdmi_rx_dma/fifo_wr_en
 ad_connect  axi_hdmi_rx_core/hdmi_dma_data axi_hdmi_rx_dma/fifo_wr_din
 ad_connect  axi_hdmi_rx_core/hdmi_dma_ovf axi_hdmi_rx_dma/fifo_wr_overflow
+ad_connect  axi_hdmi_rx_core/hdmi_dma_unf GND
+ad_connect  sys_cpu_resetn axi_hdmi_rx_dma/m_dest_axi_aresetn
+
+ad_cpu_interconnect 0x43100000 axi_hdmi_rx_core
+ad_cpu_interconnect 0x43C20000 axi_hdmi_rx_dma
+
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk axi_hdmi_rx_dma/m_dest_axi
+
+ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq
+
+# spdif tx
+
+delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports spdif]]]
+delete_bd_objs [get_bd_ports spdif]
+
+create_bd_port -dir O spdif_tx
+ad_connect  spdif_tx axi_spdif_tx_core/spdif_tx_o
+
+# spdif rx
+
+create_bd_port -dir I spdif_rx
 
 set axi_spdif_rx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_rx:1.0 axi_spdif_rx_core]
 set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_rx_core
@@ -64,31 +84,16 @@ ad_connect  sys_ps7/DMA3_REQ axi_spdif_rx_core/DMA_REQ
 ad_connect  sys_ps7/DMA3_ACK axi_spdif_rx_core/DMA_ACK
 ad_connect  spdif_rx axi_spdif_rx_core/spdif_rx_i
 
-ad_cpu_interconnect 0x43100000 axi_hdmi_rx_core
-ad_cpu_interconnect 0x43C20000 axi_hdmi_rx_dma
 ad_cpu_interconnect 0x75C20000 axi_spdif_rx_core
 
-ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
-ad_mem_hp2_interconnect sys_cpu_clk axi_hdmi_rx_dma/m_dest_axi
-ad_connect sys_cpu_resetn axi_hdmi_rx_dma/m_dest_axi_aresetn
+# iic interface
 
-ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq
+set axi_iic_imageon [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_imageon]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_imageon
+set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_imageon
 
-# debug
-
-set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_fifo_dma_rx]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_fifo_dma_rx
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_fifo_dma_rx
-set_property -dict [list CONFIG.C_DATA_DEPTH {4096}] $ila_fifo_dma_rx
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_fifo_dma_rx
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_fifo_dma_rx
-set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_fifo_dma_rx
-set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_fifo_dma_rx
-
-ad_connect  hdmi_rx_clk ila_fifo_dma_rx/clk
-
-ad_connect  ila_fifo_dma_rx/probe0 axi_hdmi_rx_dma/fifo_wr_sync
-ad_connect  ila_fifo_dma_rx/probe1 axi_hdmi_rx_dma/fifo_wr_en
-ad_connect  ila_fifo_dma_rx/probe2 axi_hdmi_rx_dma/fifo_wr_din
-ad_connect  ila_fifo_dma_rx/probe3 axi_hdmi_rx_dma/fifo_wr_overflow
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_imageon
+ad_connect  iic_imageon axi_iic_imageon/iic
+ad_cpu_interconnect  0x43C40000  axi_iic_imageon
+ad_cpu_interrupt ps-11 mb-11 axi_iic_imageon/iic2intc_irpt
 

From bfeebc27911711069ba070664001b1778bd2d324 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Jun 2016 13:55:10 -0400
Subject: [PATCH 259/972] imageon/zc706- remove onboard hdmi

---
 projects/imageon/zc706/system_constr.xdc  | 28 +++++++++++
 projects/imageon/zc706/system_project.tcl |  6 +--
 projects/imageon/zc706/system_top.v       | 57 ++++-------------------
 3 files changed, 39 insertions(+), 52 deletions(-)

diff --git a/projects/imageon/zc706/system_constr.xdc b/projects/imageon/zc706/system_constr.xdc
index 8ad9c0346..919fc0dd9 100644
--- a/projects/imageon/zc706/system_constr.xdc
+++ b/projects/imageon/zc706/system_constr.xdc
@@ -51,3 +51,31 @@ set_property  -dict {PACKAGE_PIN   AG15   IOSTANDARD LVCMOS25}    [get_ports  hd
 # clock definition
 
 create_clock -period 6.66667  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
+
+# default constraints
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  AJ14  IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  AJ18  IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]
+
+# gpio (switches, leds and such)
+
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]           ; ## GPIO_DIP_SW0
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]           ; ## GPIO_DIP_SW1
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]           ; ## GPIO_DIP_SW2
+set_property  -dict {PACKAGE_PIN  AJ13  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]           ; ## GPIO_DIP_SW3
+set_property  -dict {PACKAGE_PIN  AK25  IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]           ; ## GPIO_SW_LEFT
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]]           ; ## GPIO_SW_CENTER
+set_property  -dict {PACKAGE_PIN  R27   IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]           ; ## GPIO_SW_RIGHT
+
+set_property  -dict {PACKAGE_PIN  Y21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]           ; ## GPIO_LED_LEFT
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]]           ; ## GPIO_LED_CENTER
+set_property  -dict {PACKAGE_PIN  W21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]           ; ## GPIO_LED_RIGHT
+set_property  -dict {PACKAGE_PIN  A17   IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]]          ; ## GPIO_LED_0
+
+set_property  -dict {PACKAGE_PIN  H14   IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]]          ; ## XADC_GPIO_0
+set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]]          ; ## XADC_GPIO_1
+set_property  -dict {PACKAGE_PIN  J16   IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]]          ; ## XADC_GPIO_2
+set_property  -dict {PACKAGE_PIN  J14   IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]]          ; ## XADC_GPIO_3
+
diff --git a/projects/imageon/zc706/system_project.tcl b/projects/imageon/zc706/system_project.tcl
index 18329559e..32c416aae 100644
--- a/projects/imageon/zc706/system_project.tcl
+++ b/projects/imageon/zc706/system_project.tcl
@@ -8,11 +8,7 @@ adi_project_create imageon_zc706
 adi_project_files imageon_zc706 [list \
   "system_top.v" \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+  "system_constr.xdc" ]
 
 adi_project_run imageon_zc706
 
diff --git a/projects/imageon/zc706/system_top.v b/projects/imageon/zc706/system_top.v
index f8a26049e..9cd1cd2f6 100644
--- a/projects/imageon/zc706/system_top.v
+++ b/projects/imageon/zc706/system_top.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -66,14 +64,6 @@ module system_top (
 
   gpio_bd,
 
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
-
-  spdif,
-
   iic_scl,
   iic_sda,
 
@@ -115,14 +105,6 @@ module system_top (
 
   inout   [14:0]  gpio_bd;
 
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [23:0]  hdmi_data;
-
-  output          spdif;
-
   inout           iic_scl;
   inout           iic_sda;
 
@@ -145,28 +127,13 @@ module system_top (
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
-  // base hdmi
-
-  assign hdmi_out_clk = 1'd0;
-  assign hdmi_vsync = 1'd0;
-  assign hdmi_hsync = 1'd0;
-  assign hdmi_data_e = 1'd0;
-  assign hdmi_data = 24'd0;
-  assign spdif = 1'd0;
-
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi_iic_rstn (
-    .dio_t (gpio_t[33]),
-    .dio_i (gpio_o[33]),
-    .dio_o (gpio_i[33]),
-    .dio_p (hdmi_iic_rstn));
-
-  ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi (
-    .dio_t (gpio_t[32]),
-    .dio_i (gpio_o[32]),
-    .dio_o (gpio_i[32]),
-    .dio_p (hdmi_rx_int));
+  ad_iobuf #(.DATA_WIDTH(2)) i_gpio (
+    .dio_t (gpio_t[33:32]),
+    .dio_i (gpio_o[33:32]),
+    .dio_o (gpio_i[33:32]),
+    .dio_p ({hdmi_iic_rstn, hdmi_rx_int}));
 
   ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd (
     .dio_t (gpio_t[14:0]),
@@ -199,14 +166,10 @@ module system_top (
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .hdmi_data (),
-    .hdmi_data_e (),
-    .hdmi_es_data (hdmi_tx_data),
-    .hdmi_hsync (),
-    .hdmi_out_clk (hdmi_tx_clk),
     .hdmi_rx_clk (hdmi_rx_clk),
     .hdmi_rx_data (hdmi_rx_data),
-    .hdmi_vsync (),
+    .hdmi_tx_clk (hdmi_tx_clk),
+    .hdmi_tx_data (hdmi_tx_data),
     .iic_imageon_scl_io (hdmi_iic_scl),
     .iic_imageon_sda_io (hdmi_iic_sda),
     .iic_main_scl_io (iic_scl),
@@ -223,14 +186,14 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_13 (1'b0),
-    .spdif (hdmi_tx_spdif),
     .spdif_rx (hdmi_rx_spdif),
+    .spdif_tx (hdmi_tx_spdif),
     .spi0_clk_i (1'b0),
     .spi0_clk_o (),
     .spi0_csn_0_o (),
     .spi0_csn_1_o (),
     .spi0_csn_2_o (),
-    .spi0_csn_i (1'b0),
+    .spi0_csn_i (1'b1),
     .spi0_sdi_i (1'b0),
     .spi0_sdo_i (1'b0),
     .spi0_sdo_o (),
@@ -239,7 +202,7 @@ module system_top (
     .spi1_csn_0_o (),
     .spi1_csn_1_o (),
     .spi1_csn_2_o (),
-    .spi1_csn_i (1'b0),
+    .spi1_csn_i (1'b1),
     .spi1_sdi_i (1'b0),
     .spi1_sdo_i (1'b0),
     .spi1_sdo_o ());

From ebdc7832a780ba082464b500198f24e55411cf5a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Jun 2016 14:00:30 -0400
Subject: [PATCH 260/972] hdl make updates

---
 projects/imageon/zc706/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile
index c4981bb84..bf8076634 100644
--- a/projects/imageon/zc706/Makefile
+++ b/projects/imageon/zc706/Makefile
@@ -13,7 +13,6 @@ M_DEPS += ../common/imageon_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr

From abe837e6083aa958edc8db0cd8e0e14705f191e4 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Thu, 2 Jun 2016 17:34:29 +0300
Subject: [PATCH 261/972] util_rfifo: Set an offset for the write addres

---
 library/util_rfifo/util_rfifo.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v
index 67e295cba..939ea820c 100644
--- a/library/util_rfifo/util_rfifo.v
+++ b/library/util_rfifo/util_rfifo.v
@@ -175,7 +175,7 @@ module util_rfifo (
   // internal registers
 
   reg     [(DATA_WIDTH-1):0]          din_wdata = 'd0;
-  reg     [(ADDRESS_WIDTH-1):0]       din_waddr = 'd0;
+  reg     [(ADDRESS_WIDTH-1):0]       din_waddr = 'hc;
   reg                                 din_wr = 'd0;
   reg     [ 6:0]                      din_req_cnt = 'd0;
   reg     [ 7:0]                      din_enable_m1 = 'd0;
@@ -254,7 +254,7 @@ module util_rfifo (
 
   always @(posedge din_clk or negedge din_rstn) begin
     if (din_rstn == 1'b0) begin
-      din_waddr <= 'd0;
+      din_waddr <= 'hc;
       din_wr <= 1'd0;
     end else begin
       if (din_wr == 1'b1) begin

From 3351ff607e55574f30c90942398fa17d83ddfd54 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 2 Jun 2016 16:22:40 -0400
Subject: [PATCH 262/972] adrv9371x- need to investigate merge with avalon

---
 projects/adrv9371x/a10soc/system_bd.qsys     | 53 +--------------
 projects/adrv9371x/a10soc/system_constr.sdc  | 32 +++++++++
 projects/adrv9371x/a10soc/system_project.tcl | 32 ++++-----
 projects/adrv9371x/common/adrv9371x_bd.qsys  | 70 ++++----------------
 4 files changed, 63 insertions(+), 124 deletions(-)

diff --git a/projects/adrv9371x/a10soc/system_bd.qsys b/projects/adrv9371x/a10soc/system_bd.qsys
index bbab402c3..5ead260a9 100644
--- a/projects/adrv9371x/a10soc/system_bd.qsys
+++ b/projects/adrv9371x/a10soc/system_bd.qsys
@@ -57,22 +57,6 @@
          type = "String";
       }
    }
-   element adrv9371x.avl_rx_os_xcvr
-   {
-      datum baseAddress
-      {
-         value = "204800";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_rx_xcvr
-   {
-      datum baseAddress
-      {
-         value = "196608";
-         type = "String";
-      }
-   }
    element adrv9371x.avl_tx_jesd
    {
       datum baseAddress
@@ -89,14 +73,6 @@
          type = "String";
       }
    }
-   element adrv9371x.avl_tx_xcvr
-   {
-      datum baseAddress
-      {
-         value = "180224";
-         type = "String";
-      }
-   }
    element adrv9371x.avl_xcvr_pll
    {
       datum baseAddress
@@ -477,7 +453,7 @@
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_core.reconfig_avmm' start='0x2C000' end='0x30000' /><slave name='adrv9371x_xcvr_rx_core.reconfig_avmm' start='0x30000' end='0x32000' /><slave name='adrv9371x_xcvr_rx_os_core.reconfig_avmm' start='0x32000' end='0x34000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /></address-map>]]></parameter>
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
   <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
  </module>
@@ -560,24 +536,6 @@
   <parameter name="baseAddress" value="0x00035c00" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_rx_os_xcvr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00032000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_rx_xcvr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="avalon"
    version="15.1"
@@ -596,15 +554,6 @@
   <parameter name="baseAddress" value="0x00034000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_tx_xcvr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0002c000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="avalon"
    version="15.1"
diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc
index ddbb2743c..ed6d0cc7e 100644
--- a/projects/adrv9371x/a10soc/system_constr.sdc
+++ b/projects/adrv9371x/a10soc/system_constr.sdc
@@ -6,3 +6,35 @@ create_clock -period  "8.139 ns"  -name ref_clk1_122mhz     [get_ports {ref_clk1
 derive_pll_clocks
 derive_clock_uncertainty
 
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_os_clk}]
+
+set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_clk}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_os_clk}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
diff --git a/projects/adrv9371x/a10soc/system_project.tcl b/projects/adrv9371x/a10soc/system_project.tcl
index d095a5245..49e6487e8 100644
--- a/projects/adrv9371x/a10soc/system_project.tcl
+++ b/projects/adrv9371x/a10soc/system_project.tcl
@@ -17,22 +17,22 @@ set_location_assignment PIN_N29   -to ref_clk0              ; ## D04  FMC_HPC_GB
 set_location_assignment PIN_N28   -to "ref_clk0(n)"         ; ## D05  FMC_HPC_GBTCLK0_M2C_N (NC)
 set_location_assignment PIN_R29   -to ref_clk1              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
 set_location_assignment PIN_R28   -to "ref_clk1(n)"         ; ## B21  FMC_HPC_GBTCLK1_M2C_N
-set_location_assignment PIN_R32   -to rx_data[0]            ; ## A02  FMC_HPC_DP1_M2C_P
-set_location_assignment PIN_R33   -to "rx_data[0](n)"       ; ## A03  FMC_HPC_DP1_M2C_N
-set_location_assignment PIN_P34   -to rx_data[1]            ; ## A06  FMC_HPC_DP2_M2C_P
-set_location_assignment PIN_P35   -to "rx_data[1](n)"       ; ## A07  FMC_HPC_DP2_M2C_N
-set_location_assignment PIN_T30   -to rx_data[2]            ; ## C06  FMC_HPC_DP0_M2C_P
-set_location_assignment PIN_T31   -to "rx_data[2](n)"       ; ## C07  FMC_HPC_DP0_M2C_N
-set_location_assignment PIN_P30   -to rx_data[3]            ; ## A10  FMC_HPC_DP3_M2C_P
-set_location_assignment PIN_P31   -to "rx_data[3](n)"       ; ## A11  FMC_HPC_DP3_M2C_N
-set_location_assignment PIN_M38   -to tx_data[0]            ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[3])
-set_location_assignment PIN_M39   -to "tx_data[0](n)"       ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[3])
-set_location_assignment PIN_L36   -to tx_data[1]            ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[0])
-set_location_assignment PIN_L37   -to "tx_data[1](n)"       ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[0])
-set_location_assignment PIN_N36   -to tx_data[2]            ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[1])
-set_location_assignment PIN_N37   -to "tx_data[2](n)"       ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[1])
-set_location_assignment PIN_K38   -to tx_data[3]            ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[2])
-set_location_assignment PIN_K39   -to "tx_data[3](n)"       ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[2])
+set_location_assignment PIN_R33   -to rx_data[0]            ; ## A02  FMC_HPC_DP1_M2C_P
+set_location_assignment PIN_R32   -to "rx_data[0](n)"       ; ## A03  FMC_HPC_DP1_M2C_N
+set_location_assignment PIN_P35   -to rx_data[1]            ; ## A06  FMC_HPC_DP2_M2C_P
+set_location_assignment PIN_P34   -to "rx_data[1](n)"       ; ## A07  FMC_HPC_DP2_M2C_N
+set_location_assignment PIN_T31   -to rx_data[2]            ; ## C06  FMC_HPC_DP0_M2C_P
+set_location_assignment PIN_T30   -to "rx_data[2](n)"       ; ## C07  FMC_HPC_DP0_M2C_N
+set_location_assignment PIN_P31   -to rx_data[3]            ; ## A10  FMC_HPC_DP3_M2C_P
+set_location_assignment PIN_P30   -to "rx_data[3](n)"       ; ## A11  FMC_HPC_DP3_M2C_N
+set_location_assignment PIN_M39   -to tx_data[0]            ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[3])
+set_location_assignment PIN_M38   -to "tx_data[0](n)"       ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[3])
+set_location_assignment PIN_L37   -to tx_data[1]            ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[0])
+set_location_assignment PIN_L36   -to "tx_data[1](n)"       ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[0])
+set_location_assignment PIN_N37   -to tx_data[2]            ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[1])
+set_location_assignment PIN_N36   -to "tx_data[2](n)"       ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[1])
+set_location_assignment PIN_K39   -to tx_data[3]            ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[2])
+set_location_assignment PIN_K38   -to "tx_data[3](n)"       ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[2])
 
 set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0
 set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1
diff --git a/projects/adrv9371x/common/adrv9371x_bd.qsys b/projects/adrv9371x/common/adrv9371x_bd.qsys
index 56f0877a7..8f1721be9 100755
--- a/projects/adrv9371x/common/adrv9371x_bd.qsys
+++ b/projects/adrv9371x/common/adrv9371x_bd.qsys
@@ -323,16 +323,8 @@
    internal="xcvr_rx_os_core.jesd204_rx_avs"
    type="avalon"
    dir="end" />
- <interface
-   name="avl_rx_os_xcvr"
-   internal="xcvr_rx_os_core.reconfig_avmm"
-   type="avalon"
-   dir="end" />
- <interface
-   name="avl_rx_xcvr"
-   internal="xcvr_rx_core.reconfig_avmm"
-   type="avalon"
-   dir="end" />
+ <interface name="avl_rx_os_xcvr" internal="xcvr_rx_os_core.reconfig_avmm" />
+ <interface name="avl_rx_xcvr" internal="xcvr_rx_core.reconfig_avmm" />
  <interface
    name="avl_tx_jesd"
    internal="xcvr_tx_core.jesd204_tx_avs"
@@ -343,11 +335,7 @@
    internal="xcvr_tx_lane_pll.reconfig_avmm0"
    type="avalon"
    dir="end" />
- <interface
-   name="avl_tx_xcvr"
-   internal="xcvr_tx_core.reconfig_avmm"
-   type="avalon"
-   dir="end" />
+ <interface name="avl_tx_xcvr" internal="xcvr_tx_core.reconfig_avmm" />
  <interface
    name="avl_xcvr_pll"
    internal="xcvr_pll_reconfig.mgmt_avalon_slave"
@@ -922,7 +910,7 @@
   <parameter name="N" value="16" />
   <parameter name="N_PRIME" value="16" />
   <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG2" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
   <parameter name="PHADJ" value="0" />
   <parameter name="REFCLK_FREQ" value="122.88" />
   <parameter name="RES1" value="0" />
@@ -937,12 +925,12 @@
   <parameter name="lane_rate" value="4915.2" />
   <parameter name="part_trait_bd" value="NIGHTFURY4" />
   <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_reconfig_enable" value="false" />
   <parameter name="pll_type" value="CMU" />
   <parameter name="rcfg_jtag_enable" value="false" />
   <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="true" />
-  <parameter name="set_csr_soft_logic_enable" value="true" />
+  <parameter name="set_capability_reg_enable" value="false" />
+  <parameter name="set_csr_soft_logic_enable" value="false" />
   <parameter name="set_prbs_soft_logic_enable" value="false" />
   <parameter name="set_user_identifier" value="0" />
   <parameter name="wrapper_opt" value="base_phy" />
@@ -1000,16 +988,16 @@
   <parameter name="TERMINATE_RECONFIG_EN" value="false" />
   <parameter name="TEST_COMPONENTS_EN" value="false" />
   <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="bonded" />
+  <parameter name="bonded_mode" value="non_bonded" />
   <parameter name="lane_rate" value="4915.2" />
   <parameter name="part_trait_bd" value="NIGHTFURY4" />
   <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_reconfig_enable" value="false" />
   <parameter name="pll_type" value="CMU" />
   <parameter name="rcfg_jtag_enable" value="false" />
   <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="true" />
-  <parameter name="set_csr_soft_logic_enable" value="true" />
+  <parameter name="set_capability_reg_enable" value="false" />
+  <parameter name="set_csr_soft_logic_enable" value="false" />
   <parameter name="set_prbs_soft_logic_enable" value="false" />
   <parameter name="set_user_identifier" value="0" />
   <parameter name="wrapper_opt" value="base_phy" />
@@ -1108,7 +1096,7 @@
   <parameter name="N" value="16" />
   <parameter name="N_PRIME" value="16" />
   <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG2" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
   <parameter name="PHADJ" value="0" />
   <parameter name="REFCLK_FREQ" value="125.0" />
   <parameter name="RES1" value="0" />
@@ -1123,12 +1111,12 @@
   <parameter name="lane_rate" value="4915.2" />
   <parameter name="part_trait_bd" value="NIGHTFURY4" />
   <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="true" />
+  <parameter name="pll_reconfig_enable" value="false" />
   <parameter name="pll_type" value="CMU" />
   <parameter name="rcfg_jtag_enable" value="false" />
   <parameter name="sdc_constraint" value="1.0" />
   <parameter name="set_capability_reg_enable" value="false" />
-  <parameter name="set_csr_soft_logic_enable" value="true" />
+  <parameter name="set_csr_soft_logic_enable" value="false" />
   <parameter name="set_prbs_soft_logic_enable" value="false" />
   <parameter name="set_user_identifier" value="0" />
   <parameter name="wrapper_opt" value="base_phy" />
@@ -1317,21 +1305,6 @@
    version="15.1"
    start="xcvr_ref_clk.out_clk"
    end="xcvr_tx_lane_pll.pll_refclk0" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_os_core.reconfig_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_tx_core.reconfig_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_core.reconfig_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -2131,21 +2104,6 @@
    version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_pll_reconfig.mgmt_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_os_core.reconfig_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_core.reconfig_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_core.reconfig_reset" />
  <connection
    kind="reset"
    version="15.1"

From 3516ec28b726008a9a30b30ea2ba1576b11c60a8 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 7 Jun 2016 12:24:08 -0400
Subject: [PATCH 263/972] daq2/a10gx- qsys updates

---
 projects/common/a10gx/a10gx_system_qsys.tcl | 330 ++++++++++++++++++++
 projects/daq2/a10gx/system_qsys.tcl         |   8 +
 projects/daq2/common/daq2_qsys.tcl          | 299 ++++++++++++++++++
 3 files changed, 637 insertions(+)
 create mode 100644 projects/common/a10gx/a10gx_system_qsys.tcl
 create mode 100644 projects/daq2/a10gx/system_qsys.tcl
 create mode 100644 projects/daq2/common/daq2_qsys.tcl

diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl
new file mode 100644
index 000000000..751fa002d
--- /dev/null
+++ b/projects/common/a10gx/a10gx_system_qsys.tcl
@@ -0,0 +1,330 @@
+
+package require -exact qsys 14.0
+
+set_module_property NAME {system_bd}
+set_project_property DEVICE_FAMILY {Arria 10}
+set_project_property DEVICE {10AX115S3F45E2SGE3}
+
+# clock-&-reset
+
+add_instance sys_clk clock_source 15.1
+add_interface sys_clk clock sink
+add_interface sys_rst reset sink
+set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
+set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
+
+# memory (int)
+
+add_instance sys_int_mem altera_avalon_onchip_memory2 15.1
+set_instance_parameter_value sys_int_mem {dataWidth} {32}
+set_instance_parameter_value sys_int_mem {dualPort} {0}
+set_instance_parameter_value sys_int_mem {initMemContent} {0}
+set_instance_parameter_value sys_int_mem {memorySize} {163840.0}
+
+add_connection sys_clk.clk sys_int_mem.clk1
+add_connection sys_clk.clk_reset sys_int_mem.reset1
+
+# memory (tlb)
+
+add_instance sys_tlb_mem altera_avalon_onchip_memory2 15.1
+set_instance_parameter_value sys_tlb_mem {dataWidth} {32}
+set_instance_parameter_value sys_tlb_mem {dualPort} {1}
+set_instance_parameter_value sys_tlb_mem {initMemContent} {1}
+set_instance_parameter_value sys_tlb_mem {memorySize} {163840.0}
+
+add_connection sys_clk.clk sys_tlb_mem.clk1
+add_connection sys_clk.clk_reset sys_tlb_mem.reset1
+add_connection sys_clk.clk sys_tlb_mem.clk2
+add_connection sys_clk.clk_reset sys_tlb_mem.reset2
+
+# memory (ddr)
+
+add_instance sys_ddr3_cntrl altera_emif 15.1
+set_instance_parameter_value sys_ddr3_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR3}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_MEM_CLK_FREQ_MHZ} {533.333}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_DEFAULT_REF_CLK_FREQ} {0}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_REF_CLK_FREQ_MHZ} {133.333}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_DEFAULT_IO} {0}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_15_C1}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_AC_MODE_ENUM} {CURRENT_ST_12}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_15_C1}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_CK_MODE_ENUM} {CURRENT_ST_12}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IO_STD_ENUM} {IO_STD_SSTL_15}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_15}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {IN_OCT_40_CAL}
+set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_LVDS}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_FORMAT_ENUM} {MEM_FORMAT_UDIMM}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_DQ_WIDTH} {64}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_ROW_ADDR_WIDTH} {12}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_COL_ADDR_WIDTH} {10}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_BANK_ADDR_WIDTH} {3}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_DM_EN} {1}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TCL} {13}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_WTCL} {9}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRCD_NS} {10.285}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {10.285}
+set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {4.0}
+set_instance_parameter_value sys_ddr3_cntrl {SHORT_QSYS_INTERFACE_NAMES} {1}
+
+add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset_n
+add_interface sys_ddr3_cntrl_mem conduit end
+add_interface sys_ddr3_cntrl_oct conduit end
+add_interface sys_ddr3_cntrl_pll_ref_clk clock sink
+
+set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.mem
+set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct
+set_interface_property sys_ddr3_cntrl_pll_ref_clk EXPORT_OF sys_ddr3_cntrl.pll_ref_clk
+
+# cpu
+
+add_instance sys_cpu altera_nios2_gen2 15.1
+set_instance_parameter_value sys_cpu {setting_support31bitdcachebypass} {0}
+set_instance_parameter_value sys_cpu {setting_activateTrace} {1}
+set_instance_parameter_value sys_cpu {mmu_autoAssignTlbPtrSz} {0}
+set_instance_parameter_value sys_cpu {mmu_TLBMissExcOffset} {4096}
+set_instance_parameter_value sys_cpu {resetSlave} {sys_ddr3_cntrl_arch.ctrl_amm_0}
+set_instance_parameter_value sys_cpu {mmu_TLBMissExcSlave} {sys_tlb_mem.s2}
+set_instance_parameter_value sys_cpu {exceptionSlave} {sys_ddr3_cntrl_arch.ctrl_amm_0}
+set_instance_parameter_value sys_cpu {breakSlave} {sys_cpu.jtag_debug_module}
+set_instance_parameter_value sys_cpu {mul_32_impl} {3}
+set_instance_parameter_value sys_cpu {shift_rot_impl} {0}
+set_instance_parameter_value sys_cpu {icache_size} {32768}
+set_instance_parameter_value sys_cpu {icache_numTCIM} {1}
+set_instance_parameter_value sys_cpu {dcache_size} {32768}
+set_instance_parameter_value sys_cpu {dcache_numTCDM} {1}
+set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
+set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
+set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
+
+add_connection sys_clk.clk sys_cpu.clk
+add_connection sys_clk.clk_reset sys_cpu.reset
+add_connection sys_cpu.debug_reset_request sys_cpu.reset
+
+add_connection sys_cpu.instruction_master sys_cpu.debug_mem_slave
+add_connection sys_cpu.data_master sys_cpu.debug_mem_slave
+add_connection sys_cpu.instruction_master sys_int_mem.s1
+add_connection sys_cpu.data_master sys_int_mem.s1
+add_connection sys_cpu.tightly_coupled_instruction_master_0 sys_tlb_mem.s2
+add_connection sys_cpu.tightly_coupled_data_master_0 sys_tlb_mem.s1
+add_connection sys_cpu.instruction_master sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.data_master sys_ddr3_cntrl.ctrl_amm_0
+
+# ethernet
+
+add_instance sys_ethernet altera_eth_tse 15.1
+set_instance_parameter_value sys_ethernet {core_variation} {MAC_PCS}
+set_instance_parameter_value sys_ethernet {ifGMII} {MII_GMII}
+set_instance_parameter_value sys_ethernet {transceiver_type} {LVDS_IO}
+set_instance_parameter_value sys_ethernet {enable_hd_logic} {0}
+set_instance_parameter_value sys_ethernet {useMDIO} {1}
+set_instance_parameter_value sys_ethernet {eg_addr} {12}
+set_instance_parameter_value sys_ethernet {ing_addr} {12}
+set_instance_parameter_value sys_ethernet {enable_sgmii} {1}
+
+add_instance sys_ethernet_dma_rx altera_msgdma 15.1
+set_instance_parameter_value sys_ethernet_dma_rx {MODE} {2}
+set_instance_parameter_value sys_ethernet_dma_rx {DATA_WIDTH} {64}
+set_instance_parameter_value sys_ethernet_dma_rx {DATA_FIFO_DEPTH} {256}
+set_instance_parameter_value sys_ethernet_dma_rx {DESCRIPTOR_FIFO_DEPTH} {512}
+set_instance_parameter_value sys_ethernet_dma_rx {RESPONSE_PORT} {0}
+set_instance_parameter_value sys_ethernet_dma_rx {MAX_BYTE} {2048}
+set_instance_parameter_value sys_ethernet_dma_rx {TRANSFER_TYPE} {Unaligned Accesses}
+set_instance_parameter_value sys_ethernet_dma_rx {BURST_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_rx {MAX_BURST_COUNT} {64}
+set_instance_parameter_value sys_ethernet_dma_rx {ENHANCED_FEATURES} {1}
+set_instance_parameter_value sys_ethernet_dma_rx {PACKET_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_rx {ERROR_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_rx {ERROR_WIDTH} {6}
+
+add_instance sys_ethernet_dma_tx altera_msgdma 15.1
+set_instance_parameter_value sys_ethernet_dma_tx {MODE} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {DATA_WIDTH} {64}
+set_instance_parameter_value sys_ethernet_dma_tx {DATA_FIFO_DEPTH} {256}
+set_instance_parameter_value sys_ethernet_dma_tx {DESCRIPTOR_FIFO_DEPTH} {512}
+set_instance_parameter_value sys_ethernet_dma_tx {MAX_BYTE} {2048}
+set_instance_parameter_value sys_ethernet_dma_tx {TRANSFER_TYPE} {Unaligned Accesses}
+set_instance_parameter_value sys_ethernet_dma_tx {BURST_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {MAX_BURST_COUNT} {64}
+set_instance_parameter_value sys_ethernet_dma_tx {ENHANCED_FEATURES} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {PACKET_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {ERROR_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {ERROR_WIDTH} {1}
+
+add_instance sys_ethernet_reset altera_reset_bridge 15.1
+set_instance_parameter_value sys_ethernet_reset {ACTIVE_LOW_RESET} {0}
+set_instance_parameter_value sys_ethernet_reset {NUM_RESET_OUTPUTS} {1}
+
+add_connection sys_clk.clk_reset sys_ethernet.reset_connection
+add_connection sys_clk.clk_reset sys_ethernet_dma_rx.reset_n
+add_connection sys_clk.clk_reset sys_ethernet_dma_tx.reset_n
+add_connection sys_clk.clk_reset sys_ethernet_reset.in_reset
+add_connection sys_clk.clk sys_ethernet.control_port_clock_connection
+add_connection sys_clk.clk sys_ethernet.receive_clock_connection
+add_connection sys_clk.clk sys_ethernet.transmit_clock_connection
+add_connection sys_clk.clk sys_ethernet_dma_rx.clock
+add_connection sys_clk.clk sys_ethernet_dma_tx.clock
+add_connection sys_clk.clk sys_ethernet_reset.clk
+add_connection sys_cpu.data_master sys_ethernet.control_port
+add_connection sys_cpu.data_master sys_ethernet_dma_rx.csr
+add_connection sys_cpu.data_master sys_ethernet_dma_rx.response
+add_connection sys_cpu.data_master sys_ethernet_dma_rx.descriptor_slave
+add_connection sys_cpu.data_master sys_ethernet_dma_tx.csr
+add_connection sys_cpu.data_master sys_ethernet_dma_tx.descriptor_slave
+add_connection sys_cpu.irq sys_ethernet_dma_rx.csr_irq
+add_connection sys_cpu.irq sys_ethernet_dma_tx.csr_irq
+add_connection sys_ethernet.receive sys_ethernet_dma_rx.st_sink
+add_connection sys_ethernet_dma_tx.st_source sys_ethernet.transmit
+add_connection sys_ethernet_dma_rx.mm_write sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_ethernet_dma_tx.mm_read sys_ddr3_cntrl.ctrl_amm_0
+add_interface sys_ethernet_reset reset source
+add_interface sys_ethernet_ref_clk clock sink
+add_interface sys_ethernet_mdio conduit end
+add_interface sys_ethernet_sgmii conduit end
+
+set_interface_property sys_ethernet_mdio EXPORT_OF sys_ethernet.mac_mdio_connection
+set_interface_property sys_ethernet_ref_clk EXPORT_OF sys_ethernet.pcs_ref_clk_clock_connection
+set_interface_property sys_ethernet_reset EXPORT_OF sys_ethernet_reset.out_reset
+set_interface_property sys_ethernet_sgmii EXPORT_OF sys_ethernet.serial_connection
+
+# sys-id
+
+add_instance sys_id altera_avalon_sysid_qsys 15.1
+set_instance_parameter_value sys_id {id} {182193580}
+
+add_connection sys_clk.clk_reset sys_id.reset
+add_connection sys_clk.clk sys_id.clk
+add_connection sys_cpu.data_master sys_id.control_slave
+
+# timer-1
+
+add_instance sys_timer_1 altera_avalon_timer 15.1
+set_instance_parameter_value sys_timer_1 {counterSize} {32}
+
+add_connection sys_clk.clk_reset sys_timer_1.reset
+add_connection sys_clk.clk sys_timer_1.clk
+add_connection sys_cpu.data_master sys_timer_1.s1
+add_connection sys_cpu.irq sys_timer_1.irq
+
+# timer-2
+
+add_instance sys_timer_2 altera_avalon_timer 15.1
+set_instance_parameter_value sys_timer_2 {counterSize} {32}
+
+add_connection sys_clk.clk_reset sys_timer_2.reset
+add_connection sys_clk.clk sys_timer_2.clk
+add_connection sys_cpu.data_master sys_timer_2.s1
+add_connection sys_cpu.irq sys_timer_2.irq
+
+# uart
+
+add_instance sys_uart altera_avalon_jtag_uart 15.1
+set_instance_parameter_value sys_uart {allowMultipleConnections} {0}
+
+add_connection sys_clk.clk_reset sys_uart.reset
+add_connection sys_clk.clk sys_uart.clk
+add_connection sys_cpu.data_master sys_uart.avalon_jtag_slave
+add_connection sys_cpu.irq sys_uart.irq
+
+# gpio-bd
+
+add_instance sys_gpio_bd altera_avalon_pio 15.1
+set_instance_parameter_value sys_gpio_bd {direction} {InOut}
+set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_bd {width} {32}
+
+add_connection sys_clk.clk_reset sys_gpio_bd.reset
+add_connection sys_clk.clk sys_gpio_bd.clk
+add_connection sys_cpu.data_master sys_gpio_bd.s1
+add_connection sys_cpu.irq sys_gpio_bd.irq
+add_interface sys_gpio_bd conduit end
+
+set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
+
+# gpio-in
+
+add_instance sys_gpio_in altera_avalon_pio 15.1
+set_instance_parameter_value sys_gpio_in {direction} {Input}
+set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_in {width} {32}
+
+add_connection sys_clk.clk_reset sys_gpio_in.reset
+add_connection sys_clk.clk sys_gpio_in.clk
+add_connection sys_cpu.data_master sys_gpio_in.s1
+add_connection sys_cpu.irq sys_gpio_in.irq
+add_interface sys_gpio_in conduit end
+
+set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
+
+# gpio-out
+
+add_instance sys_gpio_out altera_avalon_pio 15.1
+set_instance_parameter_value sys_gpio_out {direction} {Output}
+set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
+set_instance_parameter_value sys_gpio_out {width} {32}
+
+add_connection sys_clk.clk_reset sys_gpio_out.reset
+add_connection sys_clk.clk sys_gpio_out.clk
+add_connection sys_cpu.data_master sys_gpio_out.s1
+add_interface sys_gpio_out conduit end
+
+set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
+
+# spi
+
+add_instance sys_spi altera_avalon_spi 15.1
+set_instance_parameter_value sys_spi {clockPhase} {0}
+set_instance_parameter_value sys_spi {clockPolarity} {0}
+set_instance_parameter_value sys_spi {dataWidth} {8}
+set_instance_parameter_value sys_spi {masterSPI} {1}
+set_instance_parameter_value sys_spi {numberOfSlaves} {8}
+set_instance_parameter_value sys_spi {targetClockRate} {128000.0}
+
+add_connection sys_clk.clk_reset sys_spi.reset
+add_connection sys_clk.clk sys_spi.clk
+add_connection sys_cpu.data_master sys_spi.spi_control_port
+add_connection sys_cpu.irq sys_spi.irq
+add_interface sys_spi conduit end
+
+set_interface_property sys_spi EXPORT_OF sys_spi.external
+
+# addresses
+
+set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.ctrl_amm_0                baseAddress {0x00000000}
+set_connection_parameter_value sys_cpu.data_master/sys_int_mem.s1                           baseAddress {0x10140000}
+set_connection_parameter_value sys_cpu.data_master/sys_cpu.debug_mem_slave                  baseAddress {0x10180800}
+set_connection_parameter_value sys_cpu.data_master/sys_uart.avalon_jtag_slave               baseAddress {0x101814f0}
+set_connection_parameter_value sys_cpu.data_master/sys_ethernet.control_port                baseAddress {0x10181000}
+set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.csr                  baseAddress {0x101814a0}
+set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.response             baseAddress {0x101814e0}
+set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.descriptor_slave     baseAddress {0x10181440}
+set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_tx.csr                  baseAddress {0x10181480}
+set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_tx.descriptor_slave     baseAddress {0x10181460}
+set_connection_parameter_value sys_cpu.data_master/sys_spi.spi_control_port                 baseAddress {0x10181400}
+set_connection_parameter_value sys_cpu.data_master/sys_gpio_out.s1                          baseAddress {0x10181500}
+set_connection_parameter_value sys_cpu.data_master/sys_gpio_in.s1                           baseAddress {0x101814c0}
+set_connection_parameter_value sys_cpu.data_master/sys_gpio_bd.s1                           baseAddress {0x101814d0}
+set_connection_parameter_value sys_cpu.data_master/sys_timer_2.s1                           baseAddress {0x10181520}
+set_connection_parameter_value sys_cpu.data_master/sys_timer_1.s1                           baseAddress {0x10181420}
+set_connection_parameter_value sys_cpu.data_master/sys_id.control_slave                     baseAddress {0x101814e8}
+set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
+set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave           baseAddress {0x10180800}
+set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1                    baseAddress {0x10140000}
+set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2  baseAddress {0x10200000}
+set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1         baseAddress {0x10200000}
+set_connection_parameter_value sys_ethernet_dma_tx.mm_read/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
+set_connection_parameter_value sys_ethernet_dma_rx.mm_write/sys_ddr3_cntrl.ctrl_amm_0       baseAddress {0x00000000}
+
+set_connection_parameter_value sys_cpu.irq/sys_ethernet_dma_rx.csr_irq irqNumber  {0}
+set_connection_parameter_value sys_cpu.irq/sys_ethernet_dma_tx.csr_irq irqNumber  {1}
+set_connection_parameter_value sys_cpu.irq/sys_uart.irq irqNumber                 {2}
+set_connection_parameter_value sys_cpu.irq/sys_timer_2.irq irqNumber              {3}
+set_connection_parameter_value sys_cpu.irq/sys_timer_1.irq irqNumber              {4}
+set_connection_parameter_value sys_cpu.irq/sys_gpio_in.irq irqNumber              {5}
+set_connection_parameter_value sys_cpu.irq/sys_gpio_bd.irq irqNumber              {6}
+set_connection_parameter_value sys_cpu.irq/sys_spi.irq irqNumber                  {7}
+
+# interrupts
+
+
diff --git a/projects/daq2/a10gx/system_qsys.tcl b/projects/daq2/a10gx/system_qsys.tcl
new file mode 100644
index 000000000..50e56a642
--- /dev/null
+++ b/projects/daq2/a10gx/system_qsys.tcl
@@ -0,0 +1,8 @@
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
+source ../common/daq2_qsys.tcl
+
+save_system "system_bd.qsys"
+
diff --git a/projects/daq2/common/daq2_qsys.tcl b/projects/daq2/common/daq2_qsys.tcl
new file mode 100644
index 000000000..218a8b161
--- /dev/null
+++ b/projects/daq2/common/daq2_qsys.tcl
@@ -0,0 +1,299 @@
+
+# transmit-path (refclk)
+
+add_instance xcvr_tx_ref_clk altera_clock_bridge 15.1
+set_instance_parameter_value xcvr_tx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
+
+# transmit-path (pll-core)
+
+add_instance xcvr_tx_pll altera_iopll 15.1
+add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 15.1
+set_instance_parameter_value xcvr_tx_pll {gui_en_reconf} {1}
+set_instance_parameter_value xcvr_tx_pll {gui_reference_clock_frequency} {500.0}
+set_instance_parameter_value xcvr_tx_pll {gui_use_locked} {0}
+set_instance_parameter_value xcvr_tx_pll {gui_output_clock_frequency0} {250.0}
+
+# transmit-path (pll-atx)
+
+add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 15.1
+set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {5000.0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {500.0}
+
+# receive-path (refclk)
+
+add_instance xcvr_rx_ref_clk altera_clock_bridge 15.1
+set_instance_parameter_value xcvr_rx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
+
+# receive-path (pll-core)
+
+add_instance xcvr_rx_pll altera_iopll 15.1
+add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 15.1
+set_instance_parameter_value xcvr_rx_pll {gui_en_reconf} {1}
+set_instance_parameter_value xcvr_rx_pll {gui_reference_clock_frequency} {500.0}
+set_instance_parameter_value xcvr_rx_pll {gui_use_locked} {0}
+set_instance_parameter_value xcvr_rx_pll {gui_output_clock_frequency0} {250.0}
+
+# transceiver-control
+
+add_instance axi_jesd_xcvr axi_jesd_xcvr 1.0
+set_instance_parameter_value axi_jesd_xcvr {DEVICE_TYPE} {0}
+set_instance_parameter_value axi_jesd_xcvr {TX_NUM_OF_LANES} {4}
+set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {4}
+
+# transceiver-reset
+
+add_instance xcvr_rst_cntrl altera_xcvr_reset_control 15.1
+set_instance_parameter_value xcvr_rst_cntrl {CHANNELS} {4}
+set_instance_parameter_value xcvr_rst_cntrl {SYS_CLK_IN_MHZ} {100}
+set_instance_parameter_value xcvr_rst_cntrl {TX_PLL_ENABLE} {1}
+set_instance_parameter_value xcvr_rst_cntrl {T_PLL_POWERDOWN} {1000}
+set_instance_parameter_value xcvr_rst_cntrl {TX_ENABLE} {1}
+set_instance_parameter_value xcvr_rst_cntrl {T_TX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_rst_cntrl {T_TX_DIGITALRESET} {70000}
+set_instance_parameter_value xcvr_rst_cntrl {gui_pll_cal_busy} {1}
+set_instance_parameter_value xcvr_rst_cntrl {RX_ENABLE} {1}
+set_instance_parameter_value xcvr_rst_cntrl {T_RX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_rst_cntrl {T_RX_DIGITALRESET} {4000}
+
+# transceiver-core (+ jesd)
+
+add_instance xcvr_core altera_jesd204 15.1
+set_instance_parameter_value xcvr_core {wrapper_opt} {base_phy}
+set_instance_parameter_value xcvr_core {DATA_PATH} {RX_TX}
+set_instance_parameter_value xcvr_core {lane_rate} {10000.0}
+set_instance_parameter_value xcvr_core {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value xcvr_core {bonded_mode} {non_bonded}
+set_instance_parameter_value xcvr_core {REFCLK_FREQ} {500.0}
+set_instance_parameter_value xcvr_core {pll_reconfig_enable} {1}
+set_instance_parameter_value xcvr_core {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_core {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_core {L} {4}
+set_instance_parameter_value xcvr_core {M} {2}
+set_instance_parameter_value xcvr_core {GUI_EN_CFG_F} {1}
+set_instance_parameter_value xcvr_core {GUI_CFG_F} {1}
+set_instance_parameter_value xcvr_core {N} {16}
+set_instance_parameter_value xcvr_core {S} {1}
+set_instance_parameter_value xcvr_core {K} {32}
+set_instance_parameter_value xcvr_core {SCR} {1}
+set_instance_parameter_value xcvr_core {HD} {1}
+
+# transceiver + jesd interfaces
+
+add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_pll.refclk
+add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_lane_pll.pll_refclk0
+add_interface tx_ref_clk clock sink
+set_interface_property tx_ref_clk EXPORT_OF xcvr_tx_ref_clk.in_clk
+
+add_connection xcvr_rx_ref_clk.out_clk xcvr_rx_pll.refclk
+add_connection xcvr_rx_ref_clk.out_clk xcvr_core.rx_pll_ref_clk
+add_interface rx_ref_clk clock sink
+set_interface_property rx_ref_clk EXPORT_OF xcvr_rx_ref_clk.in_clk
+
+add_connection sys_clk.clk_reset xcvr_tx_pll.reset
+add_connection axi_jesd_xcvr.if_rst xcvr_tx_pll.reset
+add_connection xcvr_tx_pll.outclk0 xcvr_core.txlink_clk
+add_connection sys_clk.clk_reset xcvr_tx_pll_reconfig.mgmt_reset
+add_connection sys_clk.clk xcvr_tx_pll_reconfig.mgmt_clk
+add_connection sys_cpu.data_master xcvr_tx_pll_reconfig.mgmt_avalon_slave
+add_connection xcvr_tx_pll_reconfig.reconfig_from_pll xcvr_tx_pll.reconfig_from_pll
+add_connection xcvr_tx_pll.reconfig_to_pll xcvr_tx_pll_reconfig.reconfig_to_pll
+
+add_connection sys_clk.clk_reset xcvr_rx_pll.reset
+add_connection axi_jesd_xcvr.if_rst xcvr_rx_pll.reset
+add_connection xcvr_rx_pll.outclk0 xcvr_core.rxlink_clk
+add_connection sys_clk.clk_reset xcvr_rx_pll_reconfig.mgmt_reset
+add_connection sys_clk.clk xcvr_rx_pll_reconfig.mgmt_clk
+add_connection sys_cpu.data_master xcvr_rx_pll_reconfig.mgmt_avalon_slave
+add_connection xcvr_rx_pll.reconfig_from_pll xcvr_rx_pll_reconfig.reconfig_from_pll
+add_connection xcvr_rx_pll_reconfig.reconfig_to_pll xcvr_rx_pll.reconfig_to_pll
+
+add_connection xcvr_rst_cntrl.pll_powerdown xcvr_tx_lane_pll.pll_powerdown
+add_connection xcvr_tx_lane_pll.pll_cal_busy xcvr_rst_cntrl.pll_cal_busy
+add_connection xcvr_tx_lane_pll.pll_locked xcvr_rst_cntrl.pll_locked
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch0
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch1
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch2
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch3
+add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
+add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0
+add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
+
+add_connection sys_clk.clk_reset xcvr_rst_cntrl.reset
+add_connection sys_clk.clk xcvr_rst_cntrl.clock
+add_connection xcvr_rst_cntrl.tx_analogreset xcvr_core.tx_analogreset
+add_connection xcvr_rst_cntrl.tx_digitalreset xcvr_core.tx_digitalreset
+add_connection xcvr_rst_cntrl.tx_cal_busy xcvr_core.tx_cal_busy
+add_connection xcvr_rst_cntrl.rx_analogreset xcvr_core.rx_analogreset
+add_connection xcvr_rst_cntrl.rx_digitalreset xcvr_core.rx_digitalreset
+add_connection xcvr_rst_cntrl.rx_cal_busy xcvr_core.rx_cal_busy
+add_connection xcvr_rst_cntrl.rx_is_lockedtodata xcvr_core.rx_islockedtodata
+add_connection axi_jesd_xcvr.if_rst xcvr_rst_cntrl.reset
+add_connection xcvr_tx_pll.outclk0 axi_jesd_xcvr.if_tx_clk
+add_connection axi_jesd_xcvr.if_tx_rstn xcvr_core.txlink_rst_n
+add_connection axi_jesd_xcvr.if_tx_ready xcvr_rst_cntrl.tx_ready
+add_connection axi_jesd_xcvr.if_tx_ip_sysref xcvr_core.tx_sysref
+add_connection axi_jesd_xcvr.if_tx_ip_sync xcvr_core.sync_n
+add_connection axi_jesd_xcvr.if_tx_ip_avl xcvr_core.jesd204_tx_link
+add_connection xcvr_rx_pll.outclk0 axi_jesd_xcvr.if_rx_clk
+add_connection axi_jesd_xcvr.if_rx_rstn xcvr_core.rxlink_rst_n
+add_connection axi_jesd_xcvr.if_rx_ready xcvr_rst_cntrl.rx_ready
+add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_core.rx_sysref
+add_connection axi_jesd_xcvr.if_rx_ip_sync xcvr_core.rx_dev_sync_n
+add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_core.rx_sof
+add_connection xcvr_core.jesd204_rx_link axi_jesd_xcvr.if_rx_ip_avl
+add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
+add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
+add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
+add_interface tx_sysref conduit end
+add_interface tx_sync conduit end
+add_interface rx_sysref conduit end
+add_interface rx_sync conduit end
+set_interface_property tx_sysref EXPORT_OF axi_jesd_xcvr.if_tx_ext_sysref_in
+set_interface_property tx_sync EXPORT_OF axi_jesd_xcvr.if_tx_sync
+set_interface_property rx_sysref EXPORT_OF axi_jesd_xcvr.if_rx_ext_sysref_in
+set_interface_property rx_sync EXPORT_OF axi_jesd_xcvr.if_rx_sync
+
+add_connection sys_clk.clk_reset xcvr_core.reconfig_reset
+add_connection sys_clk.clk xcvr_core.reconfig_clk
+add_connection sys_clk.clk_reset xcvr_core.jesd204_tx_avs_rst_n
+add_connection sys_clk.clk xcvr_core.jesd204_tx_avs_clk
+add_connection sys_clk.clk_reset xcvr_core.jesd204_rx_avs_rst_n
+add_connection sys_clk.clk xcvr_core.jesd204_rx_avs_clk
+add_connection xcvr_core.alldev_lane_aligned xcvr_core.dev_lane_aligned
+add_connection xcvr_core.tx_dev_sync_n xcvr_core.mdev_sync_n
+add_connection sys_cpu.data_master xcvr_core.reconfig_avmm
+add_connection sys_cpu.data_master xcvr_core.jesd204_tx_avs
+add_connection sys_cpu.data_master xcvr_core.jesd204_rx_avs
+add_interface tx_data conduit end
+add_interface rx_data conduit end
+set_interface_property tx_data EXPORT_OF xcvr_core.tx_serial_data
+set_interface_property rx_data EXPORT_OF xcvr_core.rx_serial_data
+
+# ad9144
+
+add_instance axi_ad9144_core axi_ad9144 1.0
+set_instance_parameter_value axi_ad9144_core {QUAD_OR_DUAL_N} {0}
+
+add_connection xcvr_tx_pll.outclk0 axi_ad9144_core.if_tx_clk
+add_connection axi_jesd_xcvr.if_tx_data axi_ad9144_core.if_tx_data
+add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset
+add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9144_core.s_axi
+
+# ad9144-unpack
+
+add_instance util_ad9144_upack util_upack 1.0
+set_instance_parameter_value util_ad9144_upack {CHANNEL_DATA_WIDTH} {64}
+set_instance_parameter_value util_ad9144_upack {NUM_OF_CHANNELS} {2}
+
+add_connection xcvr_tx_pll.outclk0 util_ad9144_upack.if_dac_clk
+add_connection axi_ad9144_core.dac_ch_0 util_ad9144_upack.dac_ch_0
+add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1
+
+# ad9144-dma
+
+add_instance axi_ad9144_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9144_dma {DMA_DATA_WIDTH_SRC} {128}
+set_instance_parameter_value axi_ad9144_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9144_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_SRC} {0}
+
+add_connection xcvr_tx_pll.outclk0 axi_ad9144_dma.if_fifo_rd_clk
+add_connection util_ad9144_upack.if_dac_valid axi_ad9144_dma.if_fifo_rd_en
+add_connection util_ad9144_upack.if_dac_data axi_ad9144_dma.if_fifo_rd_dout
+add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf
+add_connection sys_clk.clk_reset axi_ad9144_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9144_dma.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9144_dma.s_axi
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9144_dma.m_src_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9144_dma.m_src_axi_clock
+add_connection axi_ad9144_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.irq axi_ad9144_dma.interrupt_sender
+
+# ad9680
+
+add_instance axi_ad9680_core axi_ad9680 1.0
+
+add_connection xcvr_rx_pll.outclk0 axi_ad9680_core.if_rx_clk
+add_connection axi_jesd_xcvr.if_rx_data axi_ad9680_core.if_rx_data
+add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
+add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9680_core.s_axi
+
+# ad9680-pack
+
+add_instance util_ad9680_cpack util_cpack 1.0
+set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64}
+set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
+
+add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
+add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst
+add_connection xcvr_rx_pll.outclk0 util_ad9680_cpack.if_adc_clk
+add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
+add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
+
+# ad9680-fifo
+
+add_instance ad9680_adcfifo util_adcfifo 1.0
+set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} {128}
+set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128}
+set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
+
+add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
+add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst
+add_connection xcvr_rx_pll.outclk0 ad9680_adcfifo.if_adc_clk
+add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
+add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
+add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk
+
+# ad9680-dma
+
+add_instance axi_ad9680_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} {128}
+set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0}
+set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
+
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk
+add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid
+add_connection ad9680_adcfifo.if_dma_wdata axi_ad9680_dma.if_s_axis_data
+add_connection ad9680_adcfifo.if_dma_wready axi_ad9680_dma.if_s_axis_ready
+add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
+add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
+add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9680_dma.s_axi
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
+add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
+
+# addresses
+
+set_connection_parameter_value sys_cpu.data_master/xcvr_rx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d800}
+set_connection_parameter_value sys_cpu.data_master/xcvr_tx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0        baseAddress {0x1003c000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi                   baseAddress {0x10034000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi                  baseAddress {0x10010000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9144_dma.s_axi                   baseAddress {0x10038000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9144_core.s_axi                  baseAddress {0x10020000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_core.reconfig_avmm                baseAddress {0x10030000}
+set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi                    baseAddress {0x10000000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_tx_avs               baseAddress {0x1003e000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_rx_avs               baseAddress {0x1003e400}
+set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
+set_connection_parameter_value axi_ad9144_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
+
+# interrupts
+
+set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}
+set_connection_parameter_value sys_cpu.irq/axi_ad9144_dma.interrupt_sender irqNumber {11}

From ae1dd1d58e4bdd31ee6c5a7829ba3585bfadaeb2 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 7 Jun 2016 12:25:56 -0400
Subject: [PATCH 264/972] daq2/a10gx- qsys updates

---
 projects/daq2/a10gx/system_constr.sdc  | 26 ++++----
 projects/daq2/a10gx/system_project.tcl |  4 +-
 projects/daq2/a10gx/system_top.v       | 84 +++++++++++++-------------
 3 files changed, 56 insertions(+), 58 deletions(-)

diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc
index 7ec6b3f16..a1450327d 100644
--- a/projects/daq2/a10gx/system_constr.sdc
+++ b/projects/daq2/a10gx/system_constr.sdc
@@ -7,37 +7,37 @@ derive_pll_clocks
 derive_clock_uncertainty
 
 set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
+  i_system_bd|sys_ddr3_cntrl_phy_clk_0 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_1 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_2 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}]
  
 set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
+  i_system_bd|sys_ddr3_cntrl_core_nios_clk}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]
 
-set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
diff --git a/projects/daq2/a10gx/system_project.tcl b/projects/daq2/a10gx/system_project.tcl
index 664f75637..6947398c3 100644
--- a/projects/daq2/a10gx/system_project.tcl
+++ b/projects/daq2/a10gx/system_project.tcl
@@ -5,13 +5,11 @@ source ../../scripts/adi_env.tcl
 project_new daq2_a10gx -overwrite
 
 source "../../common/a10gx/a10gx_system_assign.tcl"
-set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*"
-set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*"
-set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
 set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v
index 7e3d0bfb1..ccfaa6820 100644
--- a/projects/daq2/a10gx/system_top.v
+++ b/projects/daq2/a10gx/system_top.v
@@ -238,49 +238,49 @@ module system_top (
   assign gpio_bd_o = gpio_o[15:0];
 
   system_bd i_system_bd (
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
-    .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
-    .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc),
-    .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
-    .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
-    .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
-    .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
-    .a10gx_base_sys_ethernet_reset_reset (eth_reset),
-    .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
-    .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
-    .a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
-    .a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
-    .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
-    .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
-    .a10gx_base_sys_spi_MISO (spi_miso_s),
-    .a10gx_base_sys_spi_MOSI (spi_mosi_s),
-    .a10gx_base_sys_spi_SCLK (spi_clk),
-    .a10gx_base_sys_spi_SS_n (spi_csn_s),
-    .daq2_rx_data_rx_serial_data (rx_data),
-    .daq2_rx_ref_clk_clk (rx_ref_clk),
-    .daq2_rx_sync_rx_sync (rx_sync),
-    .daq2_rx_sysref_rx_ext_sysref_in (rx_sysref),
-    .daq2_tx_data_tx_serial_data (tx_data),
-    .daq2_tx_ref_clk_clk (tx_ref_clk),
-    .daq2_tx_sync_tx_sync (tx_sync),
-    .daq2_tx_sysref_tx_ext_sysref_in (tx_sysref),
+    .rx_data_rx_serial_data (rx_data),
+    .rx_ref_clk_clk (rx_ref_clk),
+    .rx_sync_rx_sync (rx_sync),
+    .rx_sysref_rx_ext_sysref_in (rx_sysref),
     .sys_clk_clk (sys_clk),
-    .sys_reset_reset_n (sys_resetn));
+    .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
+    .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
+    .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
+    .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
+    .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
+    .sys_ethernet_mdio_mdc (eth_mdc),
+    .sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .sys_ethernet_ref_clk_clk (eth_ref_clk),
+    .sys_ethernet_reset_reset (eth_reset),
+    .sys_ethernet_sgmii_rxp_0 (eth_rxd),
+    .sys_ethernet_sgmii_txp_0 (eth_txd),
+    .sys_gpio_bd_in_port (gpio_i[31:0]),
+    .sys_gpio_bd_out_port (gpio_o[31:0]),
+    .sys_gpio_in_export (gpio_i[63:32]),
+    .sys_gpio_out_export (gpio_o[63:32]),
+    .sys_rst_reset_n (sys_resetn),
+    .sys_spi_MISO (spi_miso_s),
+    .sys_spi_MOSI (spi_mosi_s),
+    .sys_spi_SCLK (spi_clk),
+    .sys_spi_SS_n (spi_csn_s),
+    .tx_data_tx_serial_data (tx_data),
+    .tx_ref_clk_clk (tx_ref_clk),
+    .tx_sync_tx_sync (tx_sync),
+    .tx_sysref_tx_ext_sysref_in (tx_sysref));
 
 endmodule
 

From d53b06849eeda8d2a8e5f1ddac11e2dcd1ec9948 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 7 Jun 2016 12:26:15 -0400
Subject: [PATCH 265/972] daq2/a10gx- qsys updates

---
 projects/common/a10gx/a10gx_system_assign.tcl | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl
index 145c90666..f1d6eeb6c 100755
--- a/projects/common/a10gx/a10gx_system_assign.tcl
+++ b/projects/common/a10gx/a10gx_system_assign.tcl
@@ -237,4 +237,15 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
 set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
+# library paths
+
+set ad_lib_folders "$ad_hdl_dir/library/**/*;$ad_phdl_dir/library/**/*"
+
+set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
+set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
+
+# generate qsys
+
+exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script --script=system_qsys.tcl
+ 
 

From 625052f46e5ba953291c74a46135cf3ac86d3563 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 7 Jun 2016 12:27:47 -0400
Subject: [PATCH 266/972] daq2/a10gx- qsys updates

---
 projects/common/a10gx/a10gx_system_bd.qsys | 2801 --------------------
 projects/daq2/a10gx/system_bd.qsys         |  680 -----
 projects/daq2/common/daq2_bd.qsys          | 2460 -----------------
 3 files changed, 5941 deletions(-)
 delete mode 100644 projects/common/a10gx/a10gx_system_bd.qsys
 delete mode 100755 projects/daq2/a10gx/system_bd.qsys
 delete mode 100755 projects/daq2/common/daq2_bd.qsys

diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys
deleted file mode 100644
index 7bdd08068..000000000
--- a/projects/common/a10gx/a10gx_system_bd.qsys
+++ /dev/null
@@ -1,2801 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element a10gx_system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element mem_clk
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element mem_rst
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_cpu
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_cpu.debug_mem_slave
-   {
-      datum baseAddress
-      {
-         value = "270010368";
-         type = "String";
-      }
-   }
-   element sys_cpu_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-   }
-   element sys_cpu_interconnect.s0
-   {
-      datum baseAddress
-      {
-         value = "268435456";
-         type = "String";
-      }
-   }
-   element sys_ddr3_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element sys_ethernet
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet.control_port
-   {
-      datum baseAddress
-      {
-         value = "270012416";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-   }
-   element sys_ethernet_dma_rx.csr
-   {
-      datum baseAddress
-      {
-         value = "270013600";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx.descriptor_slave
-   {
-      datum baseAddress
-      {
-         value = "270013504";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx.response
-   {
-      datum baseAddress
-      {
-         value = "270013664";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_tx
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element sys_ethernet_dma_tx.csr
-   {
-      datum baseAddress
-      {
-         value = "270013568";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_tx.descriptor_slave
-   {
-      datum baseAddress
-      {
-         value = "270013536";
-         type = "String";
-      }
-   }
-   element sys_ethernet_reset
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element sys_gpio_bd
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_gpio_bd.s1
-   {
-      datum baseAddress
-      {
-         value = "270013648";
-         type = "String";
-      }
-   }
-   element sys_gpio_in
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-   }
-   element sys_gpio_in.s1
-   {
-      datum baseAddress
-      {
-         value = "270013632";
-         type = "String";
-      }
-   }
-   element sys_gpio_out
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-   }
-   element sys_gpio_out.s1
-   {
-      datum baseAddress
-      {
-         value = "270013696";
-         type = "String";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_id.control_slave
-   {
-      datum baseAddress
-      {
-         value = "270013672";
-         type = "String";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_int_mem.s1
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "269746176";
-         type = "String";
-      }
-   }
-   element sys_irq
-   {
-      datum _sortIndex
-      {
-         value = "22";
-         type = "int";
-      }
-   }
-   element sys_mem_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "21";
-         type = "int";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element sys_spi
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_spi.spi_control_port
-   {
-      datum baseAddress
-      {
-         value = "270013440";
-         type = "String";
-      }
-   }
-   element sys_timer
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_timer.s1
-   {
-      datum baseAddress
-      {
-         value = "270013472";
-         type = "String";
-      }
-   }
-   element sys_timer_2nd
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element sys_timer_2nd.s1
-   {
-      datum baseAddress
-      {
-         value = "270013728";
-         type = "String";
-      }
-   }
-   element sys_tlb_mem
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element sys_tlb_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "270532608";
-         type = "String";
-      }
-   }
-   element sys_tlb_mem.s2
-   {
-      datum baseAddress
-      {
-         value = "270532608";
-         type = "String";
-      }
-   }
-   element sys_uart
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_uart.avalon_jtag_slave
-   {
-      datum baseAddress
-      {
-         value = "270013680";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45E2SGE3" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
- <interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface
-   name="sys_cpu_m_avl"
-   internal="sys_cpu_interconnect.m0"
-   type="avalon"
-   dir="start" />
- <interface
-   name="sys_ddr3_cntrl_mem"
-   internal="sys_ddr3_cntrl.mem"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ddr3_cntrl_mem_conduit_end"
-   internal="sys_ddr3_cntrl.mem_conduit_end" />
- <interface
-   name="sys_ddr3_cntrl_oct"
-   internal="sys_ddr3_cntrl.oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ddr3_cntrl_oct_conduit_end"
-   internal="sys_ddr3_cntrl.oct_conduit_end" />
- <interface
-   name="sys_ddr3_cntrl_pll_ref_clk"
-   internal="sys_ddr3_cntrl.pll_ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_ddr3_cntrl_ref_clk"
-   internal="sys_ddr3_cntrl.pll_ref_clk_clock_sink" />
- <interface
-   name="sys_ddr3_cntrl_status_conduit_end"
-   internal="sys_ddr3_cntrl.status_conduit_end" />
- <interface
-   name="sys_ethernet_mdio"
-   internal="sys_ethernet.mac_mdio_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_ref_clk"
-   internal="sys_ethernet.pcs_ref_clk_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_ethernet_reset"
-   internal="sys_ethernet_reset.out_reset"
-   type="reset"
-   dir="start" />
- <interface
-   name="sys_ethernet_rgmii"
-   internal="sys_ethernet.mac_rgmii_connection" />
- <interface
-   name="sys_ethernet_rx_clk"
-   internal="sys_ethernet.pcs_mac_rx_clock_connection" />
- <interface
-   name="sys_ethernet_sgmii"
-   internal="sys_ethernet.serial_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_status"
-   internal="sys_ethernet.mac_status_connection" />
- <interface
-   name="sys_ethernet_tx_clk"
-   internal="sys_ethernet.pcs_mac_tx_clock_connection" />
- <interface
-   name="sys_gpio_bd"
-   internal="sys_gpio_bd.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_in"
-   internal="sys_gpio_in.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_out"
-   internal="sys_gpio_out.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_intr"
-   internal="sys_irq.receiver_irq"
-   type="interrupt"
-   dir="start" />
- <interface
-   name="sys_mem_s_avl"
-   internal="sys_mem_interconnect.s0"
-   type="avalon"
-   dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="133333250" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="bht_ramBlockType" value="Automatic" />
-  <parameter name="breakOffset" value="32" />
-  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
-  <parameter name="cdx_enabled" value="false" />
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="cpuArchRev" value="1" />
-  <parameter name="cpuID" value="0" />
-  <parameter name="cpuReset" value="false" />
-  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
-  <parameter name="dataAddrWidth" value="29" />
-  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_cpu_interconnect.s0' start='0x10000000' end='0x10100000' type='altera_avalon_mm_bridge.s0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2nd.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
-  <parameter name="data_master_high_performance_paddr_base" value="0" />
-  <parameter name="data_master_high_performance_paddr_size" value="0" />
-  <parameter name="data_master_paddr_base" value="0" />
-  <parameter name="data_master_paddr_size" value="0" />
-  <parameter name="dcache_bursts" value="false" />
-  <parameter name="dcache_numTCDM" value="1" />
-  <parameter name="dcache_ramBlockType" value="Automatic" />
-  <parameter name="dcache_size" value="32768" />
-  <parameter name="dcache_tagramBlockType" value="Automatic" />
-  <parameter name="dcache_victim_buf_impl" value="ram" />
-  <parameter name="debug_OCIOnchipTrace" value="_128" />
-  <parameter name="debug_assignJtagInstanceID" value="false" />
-  <parameter name="debug_datatrigger" value="0" />
-  <parameter name="debug_debugReqSignals" value="false" />
-  <parameter name="debug_enabled" value="true" />
-  <parameter name="debug_hwbreakpoint" value="0" />
-  <parameter name="debug_jtagInstanceID" value="0" />
-  <parameter name="debug_traceStorage" value="onchip_trace" />
-  <parameter name="debug_traceType" value="none" />
-  <parameter name="debug_triggerArming" value="true" />
-  <parameter name="deviceFamilyName" value="Arria 10" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
-  <parameter name="dividerType" value="no_div" />
-  <parameter name="exceptionOffset" value="32" />
-  <parameter name="exceptionSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
-  <parameter name="faAddrWidth" value="1" />
-  <parameter name="faSlaveMapParam" value="" />
-  <parameter name="fa_cache_line" value="2" />
-  <parameter name="fa_cache_linesize" value="0" />
-  <parameter name="flash_instruction_master_paddr_base" value="0" />
-  <parameter name="flash_instruction_master_paddr_size" value="0" />
-  <parameter name="icache_burstType" value="None" />
-  <parameter name="icache_numTCIM" value="1" />
-  <parameter name="icache_ramBlockType" value="Automatic" />
-  <parameter name="icache_size" value="32768" />
-  <parameter name="icache_tagramBlockType" value="Automatic" />
-  <parameter name="impl" value="Fast" />
-  <parameter name="instAddrWidth" value="29" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
-  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
-  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
-  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
-  <parameter name="instruction_master_paddr_base" value="0" />
-  <parameter name="instruction_master_paddr_size" value="0" />
-  <parameter name="internalIrqMaskSystemInfo" value="65535" />
-  <parameter name="io_regionbase" value="0" />
-  <parameter name="io_regionsize" value="0" />
-  <parameter name="master_addr_map" value="false" />
-  <parameter name="mmu_TLBMissExcOffset" value="4096" />
-  <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
-  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="false" />
-  <parameter name="mmu_processIDNumBits" value="8" />
-  <parameter name="mmu_ramBlockType" value="Automatic" />
-  <parameter name="mmu_tlbNumWays" value="16" />
-  <parameter name="mmu_tlbPtrSz" value="7" />
-  <parameter name="mmu_udtlbNumEntries" value="6" />
-  <parameter name="mmu_uitlbNumEntries" value="4" />
-  <parameter name="mpu_enabled" value="false" />
-  <parameter name="mpu_minDataRegionSize" value="12" />
-  <parameter name="mpu_minInstRegionSize" value="12" />
-  <parameter name="mpu_numOfDataRegion" value="8" />
-  <parameter name="mpu_numOfInstRegion" value="8" />
-  <parameter name="mpu_useLimit" value="false" />
-  <parameter name="mpx_enabled" value="false" />
-  <parameter name="mul_32_impl" value="3" />
-  <parameter name="mul_64_impl" value="0" />
-  <parameter name="mul_shift_choice" value="0" />
-  <parameter name="ocimem_ramBlockType" value="Automatic" />
-  <parameter name="ocimem_ramInit" value="false" />
-  <parameter name="regfile_ramBlockType" value="Automatic" />
-  <parameter name="resetOffset" value="0" />
-  <parameter name="resetSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="setting_HBreakTest" value="false" />
-  <parameter name="setting_HDLSimCachesCleared" value="true" />
-  <parameter name="setting_activateMonitors" value="true" />
-  <parameter name="setting_activateTestEndChecker" value="false" />
-  <parameter name="setting_activateTrace" value="true" />
-  <parameter name="setting_allow_break_inst" value="false" />
-  <parameter name="setting_alwaysEncrypt" value="true" />
-  <parameter name="setting_asic_add_scan_mode_input" value="false" />
-  <parameter name="setting_asic_enabled" value="false" />
-  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
-  <parameter name="setting_asic_third_party_synthesis" value="false" />
-  <parameter name="setting_avalonDebugPortPresent" value="false" />
-  <parameter name="setting_bhtPtrSz" value="8" />
-  <parameter name="setting_bigEndian" value="false" />
-  <parameter name="setting_branchpredictiontype" value="Dynamic" />
-  <parameter name="setting_breakslaveoveride" value="false" />
-  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
-  <parameter name="setting_dc_ecc_present" value="false" />
-  <parameter name="setting_disable_tmr_inj" value="false" />
-  <parameter name="setting_disableocitrace" value="false" />
-  <parameter name="setting_dtcm_ecc_present" value="false" />
-  <parameter name="setting_ecc_present" value="false" />
-  <parameter name="setting_ecc_sim_test_ports" value="false" />
-  <parameter name="setting_exportHostDebugPort" value="false" />
-  <parameter name="setting_exportPCB" value="false" />
-  <parameter name="setting_export_large_RAMs" value="false" />
-  <parameter name="setting_exportdebuginfo" value="false" />
-  <parameter name="setting_exportvectors" value="false" />
-  <parameter name="setting_fast_register_read" value="false" />
-  <parameter name="setting_ic_ecc_present" value="true" />
-  <parameter name="setting_interruptControllerType" value="Internal" />
-  <parameter name="setting_itcm_ecc_present" value="false" />
-  <parameter name="setting_mmu_ecc_present" value="true" />
-  <parameter name="setting_oci_export_jtag_signals" value="false" />
-  <parameter name="setting_oci_version" value="1" />
-  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
-  <parameter name="setting_removeRAMinit" value="false" />
-  <parameter name="setting_rf_ecc_present" value="true" />
-  <parameter name="setting_shadowRegisterSets" value="0" />
-  <parameter name="setting_showInternalSettings" value="false" />
-  <parameter name="setting_showUnpublishedSettings" value="false" />
-  <parameter name="setting_support31bitdcachebypass" value="false" />
-  <parameter name="setting_usedesignware" value="false" />
-  <parameter name="shift_rot_impl" value="0" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
-  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
-  <parameter name="tmr_enabled" value="false" />
-  <parameter name="tracefilename" value="" />
-  <parameter name="userDefinedSettings" value="" />
- </module>
- <module
-   name="sys_cpu_interconnect"
-   kind="altera_avalon_mm_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="20" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DATA_WIDTH" value="32" />
-  <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="MAX_PENDING_RESPONSES" value="4" />
-  <parameter name="PIPELINE_COMMAND" value="1" />
-  <parameter name="PIPELINE_RESPONSE" value="1" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
-  <parameter name="USE_RESPONSE" value="0" />
- </module>
- <module name="sys_ddr3_cntrl" kind="altera_emif" version="15.1" enabled="1">
-  <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
-  <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
-  <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
-  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
-  <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
-  <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
-  <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
-  <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
-  <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="3.5" />
-  <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
-  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
-  <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
-  <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
-  <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
-  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
-  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
-  <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
-  <parameter name="CTRL_DDR3_ECC_EN" value="false" />
-  <parameter name="CTRL_DDR3_MMR_EN" value="false" />
-  <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
-  <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
-  <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
-  <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
-  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
-  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
-  <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
-  <parameter name="CTRL_DDR4_ECC_EN" value="false" />
-  <parameter name="CTRL_DDR4_MMR_EN" value="false" />
-  <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
-  <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
-  <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
-  <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
-  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
-  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
-  <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
-  <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
-  <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
-  <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
-  <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
-  <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
-  <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
-  <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
-  <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
-  <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
-  <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
-  <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
-  <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
-  <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
-  <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
-  <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
-  <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
-  <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
-  <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
-  <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
-  <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="false" />
-  <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
-  <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
-  <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
-  <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
-  <parameter name="DIAG_EXPORT_VJI" value="false" />
-  <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
-  <parameter name="DIAG_EXTRA_CONFIGS" value="" />
-  <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
-  <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
-  <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
-  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
-  <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
-  <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
-  <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
-  <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
-  <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
-  <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
-  <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
-  <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
-  <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
-  <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="DIAG_USE_RS232_UART" value="false" />
-  <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
-  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter
-     name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
-     value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="INTERNAL_TESTING_MODE" value="false" />
-  <parameter name="IS_ED_SLAVE" value="false" />
-  <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
-  <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
-  <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
-  <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
-  <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
-  <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
-  <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
-  <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
-  <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
-  <parameter name="MEM_DDR3_DLL_EN" value="true" />
-  <parameter name="MEM_DDR3_DM_EN" value="true" />
-  <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DDR3_DQ_WIDTH" value="64" />
-  <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
-  <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
-  <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="0x0" />
-  <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
-  <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
-  <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
-  <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0" />
-  <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="12" />
-  <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
-  <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
-  <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
-  <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
-  <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
-  <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
-  <parameter name="MEM_DDR3_TCL" value="13" />
-  <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
-  <parameter name="MEM_DDR3_TDH_PS" value="55" />
-  <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
-  <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
-  <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
-  <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
-  <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
-  <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
-  <parameter name="MEM_DDR3_TDS_PS" value="53" />
-  <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
-  <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
-  <parameter name="MEM_DDR3_TIH_PS" value="95" />
-  <parameter name="MEM_DDR3_TINIT_US" value="500" />
-  <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
-  <parameter name="MEM_DDR3_TIS_PS" value="60" />
-  <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
-  <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
-  <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
-  <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
-  <parameter name="MEM_DDR3_TRCD_NS" value="10.285" />
-  <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
-  <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
-  <parameter name="MEM_DDR3_TRP_NS" value="10.285" />
-  <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
-  <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
-  <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
-  <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
-  <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
-  <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
-  <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_DDR3_WTCL" value="9" />
-  <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
-  <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
-  <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
-  <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
-  <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
-  <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_AUTO</parameter>
-  <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
-  <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
-  <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
-  <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
-  <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
-  <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
-  <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
-  <parameter name="MEM_DDR4_CAL_MODE" value="0" />
-  <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
-  <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR4_CK_WIDTH" value="1" />
-  <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="true" />
-  <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
-  <parameter name="MEM_DDR4_DLL_EN" value="true" />
-  <parameter name="MEM_DDR4_DM_EN" value="true" />
-  <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
-  <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
-  <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
-  <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
-  <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
-  <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
-  <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG" value="0000000000000000" />
-  <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
-  <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
-  <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
-  <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
-  <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
-  <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
-  <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
-  <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR4_RDIMM_CONFIG">0000000000000000000000000000000F000000</parameter>
-  <parameter name="MEM_DDR4_READ_DBI" value="false" />
-  <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
-  <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
-  <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_DDR4_RTT_NOM_ENUM">DDR4_RTT_NOM_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR4_RTT_WR_ENUM" value="DDR4_RTT_WR_RZQ_1" />
-  <parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
-  <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,off" />
-  <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR4_R_ODT1_2X2" value="off,off" />
-  <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
-  <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
-  <parameter name="MEM_DDR4_TCCD_L_CYC" value="6" />
-  <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
-  <parameter name="MEM_DDR4_TCL" value="18" />
-  <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
-  <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
-  <parameter name="MEM_DDR4_TDQSCK_PS" value="165" />
-  <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
-  <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
-  <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
-  <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
-  <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
-  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
-  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
-  <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
-  <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
-  <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
-  <parameter name="MEM_DDR4_TIH_PS" value="95" />
-  <parameter name="MEM_DDR4_TINIT_US" value="500" />
-  <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
-  <parameter name="MEM_DDR4_TIS_PS" value="60" />
-  <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
-  <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
-  <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
-  <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
-  <parameter name="MEM_DDR4_TRAS_NS" value="32.0" />
-  <parameter name="MEM_DDR4_TRCD_NS" value="15.0" />
-  <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
-  <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
-  <parameter name="MEM_DDR4_TRP_NS" value="15.0" />
-  <parameter name="MEM_DDR4_TRRD_L_CYC" value="6" />
-  <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
-  <parameter name="MEM_DDR4_TWLH_PS" value="108.0" />
-  <parameter name="MEM_DDR4_TWLS_PS" value="108.0" />
-  <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
-  <parameter name="MEM_DDR4_TWTR_L_CYC" value="9" />
-  <parameter name="MEM_DDR4_TWTR_S_CYC" value="3" />
-  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
-  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="60.0" />
-  <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
-  <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
-  <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
-  <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
-  <parameter name="MEM_DDR4_WTCL" value="12" />
-  <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
-  <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
-  <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
-  <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
-  <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
-  <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
-  <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
-  <parameter name="MEM_LPDDR3_DM_EN" value="true" />
-  <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
-  <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
-  <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
-  <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
-  <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
-  <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
-  <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
-  <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
-  <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
-  <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
-  <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
-  <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
-  <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
-  <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
-  <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
-  <parameter name="MEM_LPDDR3_TDQSCK_PS" value="614" />
-  <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
-  <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
-  <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
-  <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
-  <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
-  <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
-  <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
-  <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
-  <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
-  <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
-  <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
-  <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
-  <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
-  <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
-  <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
-  <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
-  <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
-  <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
-  <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
-  <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
-  <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
-  <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
-  <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
-  <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
-  <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
-  <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
-  <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
-  <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
-  <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
-  <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
-  <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
-  <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
-  <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
-  <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
-  <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
-  <parameter name="MEM_QDR2_BL" value="4" />
-  <parameter name="MEM_QDR2_BWS_EN" value="true" />
-  <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
-  <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
-  <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
-  <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
-  <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
-  <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
-  <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
-  <parameter name="MEM_QDR2_THA_NS" value="0.18" />
-  <parameter name="MEM_QDR2_THD_NS" value="0.18" />
-  <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
-  <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
-  <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
-  <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
-  <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
-  <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
-  <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
-  <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
-  <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
-  <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
-  <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
-  <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
-  <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
-  <parameter name="MEM_QDR4_TAH_PS" value="125" />
-  <parameter name="MEM_QDR4_TAS_PS" value="125" />
-  <parameter name="MEM_QDR4_TCH_PS" value="150" />
-  <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
-  <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
-  <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
-  <parameter name="MEM_QDR4_TCS_PS" value="150" />
-  <parameter name="MEM_QDR4_TIH_PS" value="125" />
-  <parameter name="MEM_QDR4_TIS_PS" value="125" />
-  <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
-  <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
-  <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
-  <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
-  <parameter name="MEM_RLD2_BL" value="4" />
-  <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
-  <parameter name="MEM_RLD2_DM_EN" value="true" />
-  <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
-  <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
-  <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
-  <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
-  <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
-  <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
-  <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
-  <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
-  <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
-  <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
-  <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
-  <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
-  <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
-  <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
-  <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
-  <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
-  <parameter name="MEM_RLD3_BL" value="2" />
-  <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
-  <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD3_DM_EN" value="true" />
-  <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
-  <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
-  <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
-  <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
-  <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
-  <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
-  <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
-  <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
-  <parameter name="MEM_RLD3_TDH_PS" value="5" />
-  <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
-  <parameter name="MEM_RLD3_TDS_PS" value="-30" />
-  <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
-  <parameter name="MEM_RLD3_TIH_PS" value="65" />
-  <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
-  <parameter name="MEM_RLD3_TIS_PS" value="85" />
-  <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
-  <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
-  <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
-  <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
-  <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
-  <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
-  <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
-  <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
-  <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_DDR3_DEFAULT_IO" value="false" />
-  <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
-  <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
-  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="533.333" />
-  <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_15_C1" />
-  <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="CURRENT_ST_12" />
-  <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_15_C1" />
-  <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="CURRENT_ST_12" />
-  <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="IN_OCT_40_CAL" />
-  <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="IO_STD_SSTL_15" />
-  <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
-  <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_LVDS" />
-  <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
-  <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_15" />
-  <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
-  <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
-  <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
-  <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
-  <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
-  <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
-  <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
-  <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
-  <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
-  <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
-  <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
-  <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
-  <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
-  <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
-  <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
-  <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
-  <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
-  <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
-  <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
-  <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
-  <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
-  <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
-  <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
-  <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
-  <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR3" />
-  <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
-  <parameter name="SYS_INFO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
-  <parameter name="TRAIT_SUPPORTS_VID" value="0" />
- </module>
- <module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="core_variation" value="MAC_PCS" />
-  <parameter name="deviceFamilyName" value="Arria 10" />
-  <parameter name="eg_addr" value="12" />
-  <parameter name="ena_hash" value="false" />
-  <parameter name="enable_alt_reconfig" value="false" />
-  <parameter name="enable_ecc" value="false" />
-  <parameter name="enable_ena" value="32" />
-  <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_hd_logic" value="false" />
-  <parameter name="enable_mac_flow_ctrl" value="false" />
-  <parameter name="enable_mac_vlan" value="false" />
-  <parameter name="enable_magic_detect" value="true" />
-  <parameter name="enable_ptp_1step" value="false" />
-  <parameter name="enable_sgmii" value="true" />
-  <parameter name="enable_shift16" value="true" />
-  <parameter name="enable_sup_addr" value="false" />
-  <parameter name="enable_timestamping" value="false" />
-  <parameter name="enable_use_internal_fifo" value="true" />
-  <parameter name="export_pwrdn" value="false" />
-  <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ifGMII" value="MII_GMII" />
-  <parameter name="ing_addr" value="12" />
-  <parameter name="max_channels" value="1" />
-  <parameter name="mdio_clk_div" value="40" />
-  <parameter name="nf_phyip_rcfg_enable" value="false" />
-  <parameter name="phy_identifier" value="0" />
-  <parameter name="phyip_en_synce_support" value="false" />
-  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
-  <parameter name="phyip_pll_type" value="CMU" />
-  <parameter name="phyip_pma_bonding_mode" value="x1" />
-  <parameter name="starting_channel_number" value="0" />
-  <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="transceiver_type" value="LVDS_IO" />
-  <parameter name="tstamp_fp_width" value="4" />
-  <parameter name="useMDIO" value="true" />
-  <parameter name="use_mac_clken" value="false" />
-  <parameter name="use_misc_ports" value="true" />
- </module>
- <module
-   name="sys_ethernet_dma_rx"
-   kind="altera_msgdma"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="6" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="2" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="0" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_ethernet_dma_tx"
-   kind="altera_msgdma"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="1" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="1" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="2" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_ethernet_reset"
-   kind="altera_reset_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module
-   name="sys_gpio_bd"
-   kind="altera_avalon_pio"
-   version="15.1"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_in"
-   kind="altera_avalon_pio"
-   version="15.1"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_out"
-   kind="altera_avalon_pio"
-   version="15.1"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="id" value="182193580" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria 10" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="false" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="163840" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module name="sys_irq" kind="altera_irq_bridge" version="15.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
-  <parameter name="IRQ_N" value="0" />
-  <parameter name="IRQ_WIDTH" value="8" />
- </module>
- <module
-   name="sys_mem_interconnect"
-   kind="altera_avalon_mm_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="29" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DATA_WIDTH" value="512" />
-  <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="MAX_PENDING_RESPONSES" value="4" />
-  <parameter name="PIPELINE_COMMAND" value="1" />
-  <parameter name="PIPELINE_RESPONSE" value="1" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="28" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
-  <parameter name="USE_RESPONSE" value="0" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="15.1" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="0" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="100000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="8" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="128000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
- <module
-   name="sys_timer"
-   kind="altera_avalon_timer"
-   version="15.1"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_timer_2nd"
-   kind="altera_avalon_timer"
-   version="15.1"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_tlb_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tlb_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria 10" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="163840" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sys_uart"
-   kind="altera_avalon_jtag_uart"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowMultipleConnections" value="false" />
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="100000000" />
-  <parameter name="hubInstanceID" value="0" />
-  <parameter name="readBufferDepth" value="64" />
-  <parameter name="readIRQThreshold" value="8" />
-  <parameter name="simInputCharacterStream" value="" />
-  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
-  <parameter name="useRegistersForReadBuffer" value="false" />
-  <parameter name="useRegistersForWriteBuffer" value="false" />
-  <parameter name="useRelativePathForSimFile" value="false" />
-  <parameter name="writeBufferDepth" value="64" />
-  <parameter name="writeIRQThreshold" value="8" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_uart.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814f0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet.control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814e8" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814a0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181480" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10180800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181460" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181440" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.response">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814e0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_cpu_interconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10140000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_timer.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181420" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio_bd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814d0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio_in.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio_out.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181500" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_timer_2nd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181520" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_spi.spi_control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10180800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10140000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_mem_interconnect.m0"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_ethernet_dma_tx.mm_read"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_ethernet_dma_rx.mm_write"
-   end="sys_ddr3_cntrl.ctrl_amm_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.tightly_coupled_data_master_0"
-   end="sys_tlb_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.tightly_coupled_instruction_master_0"
-   end="sys_tlb_mem.s2">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="sys_ethernet.receive"
-   end="sys_ethernet_dma_rx.st_sink" />
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="sys_ethernet_dma_tx.st_source"
-   end="sys_ethernet.transmit" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_clk"
-   end="sys_mem_interconnect.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_clk"
-   end="mem_rst.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_clk"
-   end="mem_clk.in_clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_cpu.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_uart.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_timer.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_id.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_gpio_bd.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_spi.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_cpu_interconnect.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_irq.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet_reset.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_gpio_in.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_gpio_out.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_timer_2nd.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_tlb_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_tlb_mem.clk2" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet_dma_rx.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet_dma_tx.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet.control_port_clock_connection" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet.receive_clock_connection" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ethernet.transmit_clock_connection" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_rx.csr_irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_tx.csr_irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_uart.irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_timer.irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection kind="interrupt" version="15.1" start="sys_cpu.irq" end="sys_spi.irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_gpio_bd.irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_gpio_in.irq">
-  <parameter name="irqNumber" value="8" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_timer_2nd.irq">
-  <parameter name="irqNumber" value="15" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender0_irq">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender1_irq">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender2_irq">
-  <parameter name="irqNumber" value="9" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender3_irq">
-  <parameter name="irqNumber" value="10" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender4_irq">
-  <parameter name="irqNumber" value="11" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender5_irq">
-  <parameter name="irqNumber" value="12" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender6_irq">
-  <parameter name="irqNumber" value="13" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_irq.sender7_irq">
-  <parameter name="irqNumber" value="14" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_cpu.debug_reset_request"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_reset_n"
-   end="mem_rst.in_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_ddr3_cntrl.emif_usr_reset_n"
-   end="sys_mem_interconnect.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_irq.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ddr3_cntrl.global_reset_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet_reset.in_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_uart.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_timer.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio_bd.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_spi.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_cpu_interconnect.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio_in.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio_out.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_timer_2nd.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_int_mem.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_tlb_mem.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_tlb_mem.reset2" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet.reset_connection" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet_dma_rx.reset_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet_dma_tx.reset_n" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys
deleted file mode 100755
index fac722018..000000000
--- a/projects/daq2/a10gx/system_bd.qsys
+++ /dev/null
@@ -1,680 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element a10gx_base
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element a10gx_base.sys_mem_s_avl
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element daq2
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element daq2.axi_ad9144_core_s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element daq2.axi_ad9144_dma_s_axi
-   {
-      datum baseAddress
-      {
-         value = "229376";
-         type = "String";
-      }
-   }
-   element daq2.axi_ad9680_core_s_axi
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element daq2.axi_ad9680_dma_s_axi
-   {
-      datum baseAddress
-      {
-         value = "212992";
-         type = "String";
-      }
-   }
-   element daq2.axi_jesd_xcvr_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_core_jesd204_rx_s_avl
-   {
-      datum baseAddress
-      {
-         value = "254976";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_core_jesd204_tx_s_avl
-   {
-      datum baseAddress
-      {
-         value = "253952";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_core_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "196608";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_rx_pll_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "251904";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_tx_lane_pll_s_avl
-   {
-      datum baseAddress
-      {
-         value = "245760";
-         type = "String";
-      }
-   }
-   element daq2.xcvr_tx_pll_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "249856";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45E2SGE3" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="daq2_a10gx.qpf" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="a10gx_base_sys_ddr3_cntrl_mem"
-   internal="a10gx_base.sys_ddr3_cntrl_mem"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ddr3_cntrl_oct"
-   internal="a10gx_base.sys_ddr3_cntrl_oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ddr3_cntrl_pll_ref_clk"
-   internal="a10gx_base.sys_ddr3_cntrl_pll_ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ethernet_mdio"
-   internal="a10gx_base.sys_ethernet_mdio"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ethernet_ref_clk"
-   internal="a10gx_base.sys_ethernet_ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ethernet_reset"
-   internal="a10gx_base.sys_ethernet_reset"
-   type="reset"
-   dir="start" />
- <interface
-   name="a10gx_base_sys_ethernet_sgmii"
-   internal="a10gx_base.sys_ethernet_sgmii"
-   type="conduit"
-   dir="end" />
- <interface name="a10gx_base_sys_gpio" internal="a10gx_base.sys_gpio" />
- <interface
-   name="a10gx_base_sys_gpio_bd"
-   internal="a10gx_base.sys_gpio_bd"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_gpio_in"
-   internal="a10gx_base.sys_gpio_in"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_gpio_out"
-   internal="a10gx_base.sys_gpio_out"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_spi"
-   internal="a10gx_base.sys_spi"
-   type="conduit"
-   dir="end" />
- <interface name="daq2_rx_data" internal="daq2.rx_data" type="conduit" dir="end" />
- <interface
-   name="daq2_rx_ref_clk"
-   internal="daq2.rx_ref_clk"
-   type="clock"
-   dir="end" />
- <interface name="daq2_rx_sync" internal="daq2.rx_sync" type="conduit" dir="end" />
- <interface
-   name="daq2_rx_sysref"
-   internal="daq2.rx_sysref"
-   type="conduit"
-   dir="end" />
- <interface name="daq2_tx_data" internal="daq2.tx_data" type="conduit" dir="end" />
- <interface
-   name="daq2_tx_ref_clk"
-   internal="daq2.tx_ref_clk"
-   type="clock"
-   dir="end" />
- <interface name="daq2_tx_sync" internal="daq2.tx_sync" type="conduit" dir="end" />
- <interface
-   name="daq2_tx_sysref"
-   internal="daq2.tx_sysref"
-   type="conduit"
-   dir="end" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_reset"
-   internal="sys_clk.clk_in_reset"
-   type="reset"
-   dir="end" />
- <module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq2_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq2_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq2_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq2_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq2_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_RESET_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
- </module>
- <module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 29" />
-  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 29" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133333250" />
-  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_TX_REF_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_TX_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
- </module>
- <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="daq2.axi_ad9144_dma_m_axi"
-   end="a10gx_base.sys_mem_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="daq2.axi_ad9680_dma_m_axi"
-   end="a10gx_base.sys_mem_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9144_core_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9144_dma_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00038000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9680_core_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_ad9680_dma_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00034000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.axi_jesd_xcvr_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_core_jesd204_rx_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003e400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_core_jesd204_tx_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003e000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_core_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_rx_pll_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003d800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_tx_lane_pll_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003c000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq2.xcvr_tx_pll_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003d000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.clk"
-   end="a10gx_base.sys_clk" />
- <connection kind="clock" version="15.1" start="sys_clk.clk" end="daq2.sys_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="a10gx_base.mem_clk"
-   end="daq2.mem_clk" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10gx_base.sys_intr"
-   end="daq2.axi_ad9144_dma_intr">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10gx_base.sys_intr"
-   end="daq2.axi_ad9680_dma_intr">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="a10gx_base.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="daq2.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="a10gx_base.mem_rst"
-   end="daq2.mem_rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/daq2/common/daq2_bd.qsys b/projects/daq2/common/daq2_bd.qsys
deleted file mode 100755
index 3bd3eaf0d..000000000
--- a/projects/daq2/common/daq2_bd.qsys
+++ /dev/null
@@ -1,2460 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element ad9680_adcfifo
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element axi_ad9144_core
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-   }
-   element axi_ad9144_core.s_axi
-   {
-      datum baseAddress
-      {
-         value = "269025280";
-         type = "String";
-      }
-   }
-   element axi_ad9144_dma
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element axi_ad9144_dma.s_axi
-   {
-      datum baseAddress
-      {
-         value = "269156352";
-         type = "String";
-      }
-   }
-   element axi_ad9680_core
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element axi_ad9680_core.s_axi
-   {
-      datum baseAddress
-      {
-         value = "269090816";
-         type = "String";
-      }
-   }
-   element axi_ad9680_dma
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9680_dma.s_axi
-   {
-      datum baseAddress
-      {
-         value = "269172736";
-         type = "String";
-      }
-   }
-   element axi_jesd_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-   }
-   element axi_jesd_xcvr.s_axi
-   {
-      datum baseAddress
-      {
-         value = "268959744";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq2_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element mem_clk
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element mem_rst
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element util_cpack_0
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element util_upack_0
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-   }
-   element xcvr_core
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-   }
-   element xcvr_rst_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-   }
-   element xcvr_rx_pll
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element xcvr_rx_pll_reconfig
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element xcvr_rx_ref_clk
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element xcvr_tx_lane_pll
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-   }
-   element xcvr_tx_pll
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element xcvr_tx_pll_reconfig
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element xcvr_tx_ref_clk
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45E2SGE3" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="axi_ad9144_core_s_axi"
-   internal="axi_ad9144_core.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9144_dma_intr"
-   internal="axi_ad9144_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_ad9144_dma_m_axi"
-   internal="axi_ad9144_dma.m_src_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_ad9144_dma_s_axi"
-   internal="axi_ad9144_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9680_core_s_axi"
-   internal="axi_ad9680_core.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9680_dma_intr"
-   internal="axi_ad9680_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_ad9680_dma_m_axi"
-   internal="axi_ad9680_dma.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_ad9680_dma_s_axi"
-   internal="axi_ad9680_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_jesd_xcvr_s_axi"
-   internal="axi_jesd_xcvr.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
- <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="rx_data"
-   internal="xcvr_core.rx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ref_clk"
-   internal="xcvr_rx_ref_clk.in_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="rx_sync"
-   internal="axi_jesd_xcvr.if_rx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sysref"
-   internal="axi_jesd_xcvr.if_rx_ext_sysref_in"
-   type="conduit"
-   dir="end" />
- <interface name="stp_trigger" internal="axi_jesd_xcvr.if_stp_trigger" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="tx_data"
-   internal="xcvr_core.tx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="tx_ref_clk"
-   internal="xcvr_tx_ref_clk.in_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="tx_sync"
-   internal="axi_jesd_xcvr.if_tx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="tx_sysref"
-   internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
-   type="conduit"
-   dir="end" />
- <interface
-   name="xcvr_core_jesd204_rx_s_avl"
-   internal="xcvr_core.jesd204_rx_avs"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_core_jesd204_tx_s_avl"
-   internal="xcvr_core.jesd204_tx_avs"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_core_reconfig_s_avl"
-   internal="xcvr_core.reconfig_avmm"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_rx_pll_reconfig_s_avl"
-   internal="xcvr_rx_pll_reconfig.mgmt_avalon_slave"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_tx_lane_pll_s_avl"
-   internal="xcvr_tx_lane_pll.reconfig_avmm0"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_tx_pll_reconfig_s_avl"
-   internal="xcvr_tx_pll_reconfig.mgmt_avalon_slave"
-   type="avalon"
-   dir="end" />
- <module name="ad9680_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
-  <parameter name="ADC_DATA_WIDTH" value="128" />
-  <parameter name="DMA_ADDRESS_WIDTH" value="16" />
-  <parameter name="DMA_DATA_WIDTH" value="128" />
-  <parameter name="DMA_READY_ENABLE" value="1" />
- </module>
- <module name="axi_ad9144_core" kind="axi_ad9144" version="1.0" enabled="1">
-  <parameter name="ID" value="0" />
-  <parameter name="QUAD_OR_DUAL_N" value="0" />
- </module>
- <module name="axi_ad9144_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="1" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
-  <parameter name="DMA_LENGTH_WIDTH" value="14" />
-  <parameter name="DMA_TYPE_DEST" value="2" />
-  <parameter name="DMA_TYPE_SRC" value="0" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
- </module>
- <module name="axi_ad9680_core" kind="axi_ad9680" version="1.0" enabled="1">
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_ad9680_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="1" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_jesd_xcvr" kind="axi_jesd_xcvr" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
-  <parameter name="RX_NUM_OF_LANES" value="4" />
-  <parameter name="TX_NUM_OF_LANES" value="4" />
- </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="125000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="util_cpack_0" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="64" />
-  <parameter name="NUM_OF_CHANNELS" value="2" />
- </module>
- <module name="util_upack_0" kind="util_upack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="64" />
-  <parameter name="NUM_OF_CHANNELS" value="2" />
- </module>
- <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX_TX" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="1" />
-  <parameter name="GUI_EN_CFG_F" value="true" />
-  <parameter name="HD" value="1" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="32" />
-  <parameter name="L" value="4" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="2" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG2" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="500.0" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="non_bonded" />
-  <parameter name="lane_rate" value="10000.0" />
-  <parameter name="part_trait_bd" value="NIGHTFURY5" />
-  <parameter name="part_trait_dp" value="10AX115S3F45E2SGE3" />
-  <parameter name="pll_reconfig_enable" value="true" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="true" />
-  <parameter name="set_csr_soft_logic_enable" value="true" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module
-   name="xcvr_rst_cntrl"
-   kind="altera_xcvr_reset_control"
-   version="15.1"
-   enabled="1">
-  <parameter name="CHANNELS" value="4" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="100" />
-  <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="70000" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_ANALOGRESET" value="70000" />
-  <parameter name="T_TX_DIGITALRESET" value="70000" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="1" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="0" />
- </module>
- <module name="xcvr_rx_pll" kind="altera_iopll" version="15.1" enabled="1">
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_duty_cycle0" value="50.0" />
-  <parameter name="gui_actual_duty_cycle1" value="50.0" />
-  <parameter name="gui_actual_duty_cycle10" value="50.0" />
-  <parameter name="gui_actual_duty_cycle11" value="50.0" />
-  <parameter name="gui_actual_duty_cycle12" value="50.0" />
-  <parameter name="gui_actual_duty_cycle13" value="50.0" />
-  <parameter name="gui_actual_duty_cycle14" value="50.0" />
-  <parameter name="gui_actual_duty_cycle15" value="50.0" />
-  <parameter name="gui_actual_duty_cycle16" value="50.0" />
-  <parameter name="gui_actual_duty_cycle17" value="50.0" />
-  <parameter name="gui_actual_duty_cycle2" value="50.0" />
-  <parameter name="gui_actual_duty_cycle3" value="50.0" />
-  <parameter name="gui_actual_duty_cycle4" value="50.0" />
-  <parameter name="gui_actual_duty_cycle5" value="50.0" />
-  <parameter name="gui_actual_duty_cycle6" value="50.0" />
-  <parameter name="gui_actual_duty_cycle7" value="50.0" />
-  <parameter name="gui_actual_duty_cycle8" value="50.0" />
-  <parameter name="gui_actual_duty_cycle9" value="50.0" />
-  <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_actual_phase_shift0" value="0.0" />
-  <parameter name="gui_actual_phase_shift1" value="0.0" />
-  <parameter name="gui_actual_phase_shift10" value="0.0" />
-  <parameter name="gui_actual_phase_shift11" value="0.0" />
-  <parameter name="gui_actual_phase_shift12" value="0.0" />
-  <parameter name="gui_actual_phase_shift13" value="0.0" />
-  <parameter name="gui_actual_phase_shift14" value="0.0" />
-  <parameter name="gui_actual_phase_shift15" value="0.0" />
-  <parameter name="gui_actual_phase_shift16" value="0.0" />
-  <parameter name="gui_actual_phase_shift17" value="0.0" />
-  <parameter name="gui_actual_phase_shift2" value="0.0" />
-  <parameter name="gui_actual_phase_shift3" value="0.0" />
-  <parameter name="gui_actual_phase_shift4" value="0.0" />
-  <parameter name="gui_actual_phase_shift5" value="0.0" />
-  <parameter name="gui_actual_phase_shift6" value="0.0" />
-  <parameter name="gui_actual_phase_shift7" value="0.0" />
-  <parameter name="gui_actual_phase_shift8" value="0.0" />
-  <parameter name="gui_actual_phase_shift9" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_clock_name_global0" value="false" />
-  <parameter name="gui_clock_name_global1" value="false" />
-  <parameter name="gui_clock_name_global10" value="false" />
-  <parameter name="gui_clock_name_global11" value="false" />
-  <parameter name="gui_clock_name_global12" value="false" />
-  <parameter name="gui_clock_name_global13" value="false" />
-  <parameter name="gui_clock_name_global14" value="false" />
-  <parameter name="gui_clock_name_global15" value="false" />
-  <parameter name="gui_clock_name_global16" value="false" />
-  <parameter name="gui_clock_name_global17" value="false" />
-  <parameter name="gui_clock_name_global2" value="false" />
-  <parameter name="gui_clock_name_global3" value="false" />
-  <parameter name="gui_clock_name_global4" value="false" />
-  <parameter name="gui_clock_name_global5" value="false" />
-  <parameter name="gui_clock_name_global6" value="false" />
-  <parameter name="gui_clock_name_global7" value="false" />
-  <parameter name="gui_clock_name_global8" value="false" />
-  <parameter name="gui_clock_name_global9" value="false" />
-  <parameter name="gui_clock_name_string0" value="outclk0" />
-  <parameter name="gui_clock_name_string1" value="outclk1" />
-  <parameter name="gui_clock_name_string10" value="outclk10" />
-  <parameter name="gui_clock_name_string11" value="outclk11" />
-  <parameter name="gui_clock_name_string12" value="outclk12" />
-  <parameter name="gui_clock_name_string13" value="outclk13" />
-  <parameter name="gui_clock_name_string14" value="outclk14" />
-  <parameter name="gui_clock_name_string15" value="outclk15" />
-  <parameter name="gui_clock_name_string16" value="outclk16" />
-  <parameter name="gui_clock_name_string17" value="outclk17" />
-  <parameter name="gui_clock_name_string2" value="outclk2" />
-  <parameter name="gui_clock_name_string3" value="outclk3" />
-  <parameter name="gui_clock_name_string4" value="outclk4" />
-  <parameter name="gui_clock_name_string5" value="outclk5" />
-  <parameter name="gui_clock_name_string6" value="outclk6" />
-  <parameter name="gui_clock_name_string7" value="outclk7" />
-  <parameter name="gui_clock_name_string8" value="outclk8" />
-  <parameter name="gui_clock_name_string9" value="outclk9" />
-  <parameter name="gui_device_speed_grade" value="1" />
-  <parameter name="gui_divide_factor_c0" value="6" />
-  <parameter name="gui_divide_factor_c1" value="6" />
-  <parameter name="gui_divide_factor_c10" value="6" />
-  <parameter name="gui_divide_factor_c11" value="6" />
-  <parameter name="gui_divide_factor_c12" value="6" />
-  <parameter name="gui_divide_factor_c13" value="6" />
-  <parameter name="gui_divide_factor_c14" value="6" />
-  <parameter name="gui_divide_factor_c15" value="6" />
-  <parameter name="gui_divide_factor_c16" value="6" />
-  <parameter name="gui_divide_factor_c17" value="6" />
-  <parameter name="gui_divide_factor_c2" value="6" />
-  <parameter name="gui_divide_factor_c3" value="6" />
-  <parameter name="gui_divide_factor_c4" value="6" />
-  <parameter name="gui_divide_factor_c5" value="6" />
-  <parameter name="gui_divide_factor_c6" value="6" />
-  <parameter name="gui_divide_factor_c7" value="6" />
-  <parameter name="gui_divide_factor_c8" value="6" />
-  <parameter name="gui_divide_factor_c9" value="6" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50.0" />
-  <parameter name="gui_duty_cycle1" value="50.0" />
-  <parameter name="gui_duty_cycle10" value="50.0" />
-  <parameter name="gui_duty_cycle11" value="50.0" />
-  <parameter name="gui_duty_cycle12" value="50.0" />
-  <parameter name="gui_duty_cycle13" value="50.0" />
-  <parameter name="gui_duty_cycle14" value="50.0" />
-  <parameter name="gui_duty_cycle15" value="50.0" />
-  <parameter name="gui_duty_cycle16" value="50.0" />
-  <parameter name="gui_duty_cycle17" value="50.0" />
-  <parameter name="gui_duty_cycle2" value="50.0" />
-  <parameter name="gui_duty_cycle3" value="50.0" />
-  <parameter name="gui_duty_cycle4" value="50.0" />
-  <parameter name="gui_duty_cycle5" value="50.0" />
-  <parameter name="gui_duty_cycle6" value="50.0" />
-  <parameter name="gui_duty_cycle7" value="50.0" />
-  <parameter name="gui_duty_cycle8" value="50.0" />
-  <parameter name="gui_duty_cycle9" value="50.0" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="Disabled" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="true" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_enable_output_counter_cascading" value="false" />
-  <parameter name="gui_extclkout_0_source" value="C0" />
-  <parameter name="gui_extclkout_1_source" value="C0" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_fix_vco_frequency" value="false" />
-  <parameter name="gui_fixed_vco_frequency" value="600.0" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="6" />
-  <parameter name="gui_number_of_clocks" value="1" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="250.0" />
-  <parameter name="gui_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0.0" />
-  <parameter name="gui_phase_shift1" value="0.0" />
-  <parameter name="gui_phase_shift10" value="0.0" />
-  <parameter name="gui_phase_shift11" value="0.0" />
-  <parameter name="gui_phase_shift12" value="0.0" />
-  <parameter name="gui_phase_shift13" value="0.0" />
-  <parameter name="gui_phase_shift14" value="0.0" />
-  <parameter name="gui_phase_shift15" value="0.0" />
-  <parameter name="gui_phase_shift16" value="0.0" />
-  <parameter name="gui_phase_shift17" value="0.0" />
-  <parameter name="gui_phase_shift2" value="0.0" />
-  <parameter name="gui_phase_shift3" value="0.0" />
-  <parameter name="gui_phase_shift4" value="0.0" />
-  <parameter name="gui_phase_shift5" value="0.0" />
-  <parameter name="gui_phase_shift6" value="0.0" />
-  <parameter name="gui_phase_shift7" value="0.0" />
-  <parameter name="gui_phase_shift8" value="0.0" />
-  <parameter name="gui_phase_shift9" value="0.0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="false" />
-  <parameter name="gui_pll_bandwidth_preset" value="Low" />
-  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="500.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_NDFB_modes" value="false" />
-  <parameter name="gui_use_locked" value="false" />
-  <parameter name="gui_vco_frequency" value="600.0" />
-  <parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
-  <parameter name="system_info_device_family" value="Arria 10" />
-  <parameter name="system_info_device_speed_grade" value="2" />
-  <parameter name="system_part_trait_speed_grade" value="2" />
- </module>
- <module
-   name="xcvr_rx_pll_reconfig"
-   kind="altera_pll_reconfig"
-   version="15.1"
-   enabled="1">
-  <parameter name="ENABLE_BYTEENABLE" value="false" />
-  <parameter name="ENABLE_MIF" value="false" />
-  <parameter name="MIF_FILE_NAME" value="" />
-  <parameter name="device_family" value="Arria 10" />
- </module>
- <module
-   name="xcvr_rx_ref_clk"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module
-   name="xcvr_tx_lane_pll"
-   kind="altera_xcvr_atx_pll_a10"
-   version="15.1"
-   enabled="1">
-  <parameter name="base_device" value="NIGHTFURY5" />
-  <parameter name="bw_sel" value="medium" />
-  <parameter name="device" value="10AX115S3F45E2SGE3" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="enable_16G_path" value="0" />
-  <parameter name="enable_8G_path" value="1" />
-  <parameter name="enable_analog_resets" value="0" />
-  <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
-  <parameter name="enable_bonding_clks" value="0" />
-  <parameter name="enable_cascade_out" value="0" />
-  <parameter name="enable_debug_ports_parameters" value="0" />
-  <parameter name="enable_fb_comp_bonding" value="0" />
-  <parameter name="enable_fractional" value="0" />
-  <parameter name="enable_hfreq_clk" value="0" />
-  <parameter name="enable_hip_cal_done_port" value="0" />
-  <parameter name="enable_manual_configuration" value="1" />
-  <parameter name="enable_mcgb" value="0" />
-  <parameter name="enable_mcgb_pcie_clksw" value="0" />
-  <parameter name="enable_pcie_clk" value="0" />
-  <parameter name="enable_pld_atx_cal_busy_port" value="1" />
-  <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
-  <parameter name="enable_pll_reconfig" value="1" />
-  <parameter name="generate_add_hdl_instance_example" value="0" />
-  <parameter name="generate_docs" value="1" />
-  <parameter name="mcgb_aux_clkin_cnt" value="0" />
-  <parameter name="mcgb_div" value="1" />
-  <parameter name="message_level" value="error" />
-  <parameter name="pma_width" value="64" />
-  <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
-  <parameter name="prot_mode" value="Basic" />
-  <parameter name="rcfg_debug" value="0" />
-  <parameter name="rcfg_enable_avmm_busy_port" value="0" />
-  <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
-  <parameter name="rcfg_h_file_enable" value="0" />
-  <parameter name="rcfg_jtag_enable" value="0" />
-  <parameter name="rcfg_mif_file_enable" value="0" />
-  <parameter name="rcfg_multi_enable" value="0" />
-  <parameter name="rcfg_param_vals1" value="" />
-  <parameter name="rcfg_param_vals2" value="" />
-  <parameter name="rcfg_profile_cnt" value="2" />
-  <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_separate_avmm_busy" value="1" />
-  <parameter name="rcfg_sv_file_enable" value="0" />
-  <parameter name="rcfg_txt_file_enable" value="0" />
-  <parameter name="refclk_cnt" value="1" />
-  <parameter name="refclk_index" value="0" />
-  <parameter name="select_manual_config" value="false" />
-  <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
-  <parameter name="set_auto_reference_clock_frequency" value="500.0" />
-  <parameter name="set_capability_reg_enable" value="1" />
-  <parameter name="set_csr_soft_logic_enable" value="1" />
-  <parameter name="set_fref_clock_frequency" value="156.25" />
-  <parameter name="set_hip_cal_en" value="0" />
-  <parameter name="set_k_counter" value="2000000000" />
-  <parameter name="set_l_cascade_counter" value="15" />
-  <parameter name="set_l_cascade_predivider" value="1" />
-  <parameter name="set_l_counter" value="16" />
-  <parameter name="set_m_counter" value="24" />
-  <parameter name="set_manual_reference_clock_frequency" value="200.0" />
-  <parameter name="set_output_clock_frequency" value="5000.0" />
-  <parameter name="set_ref_clk_div" value="1" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="silicon_rev" value="false" />
-  <parameter name="support_mode" value="user_mode" />
-  <parameter name="test_mode" value="0" />
- </module>
- <module name="xcvr_tx_pll" kind="altera_iopll" version="15.1" enabled="1">
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_duty_cycle0" value="50.0" />
-  <parameter name="gui_actual_duty_cycle1" value="50.0" />
-  <parameter name="gui_actual_duty_cycle10" value="50.0" />
-  <parameter name="gui_actual_duty_cycle11" value="50.0" />
-  <parameter name="gui_actual_duty_cycle12" value="50.0" />
-  <parameter name="gui_actual_duty_cycle13" value="50.0" />
-  <parameter name="gui_actual_duty_cycle14" value="50.0" />
-  <parameter name="gui_actual_duty_cycle15" value="50.0" />
-  <parameter name="gui_actual_duty_cycle16" value="50.0" />
-  <parameter name="gui_actual_duty_cycle17" value="50.0" />
-  <parameter name="gui_actual_duty_cycle2" value="50.0" />
-  <parameter name="gui_actual_duty_cycle3" value="50.0" />
-  <parameter name="gui_actual_duty_cycle4" value="50.0" />
-  <parameter name="gui_actual_duty_cycle5" value="50.0" />
-  <parameter name="gui_actual_duty_cycle6" value="50.0" />
-  <parameter name="gui_actual_duty_cycle7" value="50.0" />
-  <parameter name="gui_actual_duty_cycle8" value="50.0" />
-  <parameter name="gui_actual_duty_cycle9" value="50.0" />
-  <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_actual_phase_shift0" value="0.0" />
-  <parameter name="gui_actual_phase_shift1" value="0.0" />
-  <parameter name="gui_actual_phase_shift10" value="0.0" />
-  <parameter name="gui_actual_phase_shift11" value="0.0" />
-  <parameter name="gui_actual_phase_shift12" value="0.0" />
-  <parameter name="gui_actual_phase_shift13" value="0.0" />
-  <parameter name="gui_actual_phase_shift14" value="0.0" />
-  <parameter name="gui_actual_phase_shift15" value="0.0" />
-  <parameter name="gui_actual_phase_shift16" value="0.0" />
-  <parameter name="gui_actual_phase_shift17" value="0.0" />
-  <parameter name="gui_actual_phase_shift2" value="0.0" />
-  <parameter name="gui_actual_phase_shift3" value="0.0" />
-  <parameter name="gui_actual_phase_shift4" value="0.0" />
-  <parameter name="gui_actual_phase_shift5" value="0.0" />
-  <parameter name="gui_actual_phase_shift6" value="0.0" />
-  <parameter name="gui_actual_phase_shift7" value="0.0" />
-  <parameter name="gui_actual_phase_shift8" value="0.0" />
-  <parameter name="gui_actual_phase_shift9" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_clock_name_global0" value="false" />
-  <parameter name="gui_clock_name_global1" value="false" />
-  <parameter name="gui_clock_name_global10" value="false" />
-  <parameter name="gui_clock_name_global11" value="false" />
-  <parameter name="gui_clock_name_global12" value="false" />
-  <parameter name="gui_clock_name_global13" value="false" />
-  <parameter name="gui_clock_name_global14" value="false" />
-  <parameter name="gui_clock_name_global15" value="false" />
-  <parameter name="gui_clock_name_global16" value="false" />
-  <parameter name="gui_clock_name_global17" value="false" />
-  <parameter name="gui_clock_name_global2" value="false" />
-  <parameter name="gui_clock_name_global3" value="false" />
-  <parameter name="gui_clock_name_global4" value="false" />
-  <parameter name="gui_clock_name_global5" value="false" />
-  <parameter name="gui_clock_name_global6" value="false" />
-  <parameter name="gui_clock_name_global7" value="false" />
-  <parameter name="gui_clock_name_global8" value="false" />
-  <parameter name="gui_clock_name_global9" value="false" />
-  <parameter name="gui_clock_name_string0" value="outclk0" />
-  <parameter name="gui_clock_name_string1" value="outclk1" />
-  <parameter name="gui_clock_name_string10" value="outclk10" />
-  <parameter name="gui_clock_name_string11" value="outclk11" />
-  <parameter name="gui_clock_name_string12" value="outclk12" />
-  <parameter name="gui_clock_name_string13" value="outclk13" />
-  <parameter name="gui_clock_name_string14" value="outclk14" />
-  <parameter name="gui_clock_name_string15" value="outclk15" />
-  <parameter name="gui_clock_name_string16" value="outclk16" />
-  <parameter name="gui_clock_name_string17" value="outclk17" />
-  <parameter name="gui_clock_name_string2" value="outclk2" />
-  <parameter name="gui_clock_name_string3" value="outclk3" />
-  <parameter name="gui_clock_name_string4" value="outclk4" />
-  <parameter name="gui_clock_name_string5" value="outclk5" />
-  <parameter name="gui_clock_name_string6" value="outclk6" />
-  <parameter name="gui_clock_name_string7" value="outclk7" />
-  <parameter name="gui_clock_name_string8" value="outclk8" />
-  <parameter name="gui_clock_name_string9" value="outclk9" />
-  <parameter name="gui_device_speed_grade" value="1" />
-  <parameter name="gui_divide_factor_c0" value="6" />
-  <parameter name="gui_divide_factor_c1" value="6" />
-  <parameter name="gui_divide_factor_c10" value="6" />
-  <parameter name="gui_divide_factor_c11" value="6" />
-  <parameter name="gui_divide_factor_c12" value="6" />
-  <parameter name="gui_divide_factor_c13" value="6" />
-  <parameter name="gui_divide_factor_c14" value="6" />
-  <parameter name="gui_divide_factor_c15" value="6" />
-  <parameter name="gui_divide_factor_c16" value="6" />
-  <parameter name="gui_divide_factor_c17" value="6" />
-  <parameter name="gui_divide_factor_c2" value="6" />
-  <parameter name="gui_divide_factor_c3" value="6" />
-  <parameter name="gui_divide_factor_c4" value="6" />
-  <parameter name="gui_divide_factor_c5" value="6" />
-  <parameter name="gui_divide_factor_c6" value="6" />
-  <parameter name="gui_divide_factor_c7" value="6" />
-  <parameter name="gui_divide_factor_c8" value="6" />
-  <parameter name="gui_divide_factor_c9" value="6" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50.0" />
-  <parameter name="gui_duty_cycle1" value="50.0" />
-  <parameter name="gui_duty_cycle10" value="50.0" />
-  <parameter name="gui_duty_cycle11" value="50.0" />
-  <parameter name="gui_duty_cycle12" value="50.0" />
-  <parameter name="gui_duty_cycle13" value="50.0" />
-  <parameter name="gui_duty_cycle14" value="50.0" />
-  <parameter name="gui_duty_cycle15" value="50.0" />
-  <parameter name="gui_duty_cycle16" value="50.0" />
-  <parameter name="gui_duty_cycle17" value="50.0" />
-  <parameter name="gui_duty_cycle2" value="50.0" />
-  <parameter name="gui_duty_cycle3" value="50.0" />
-  <parameter name="gui_duty_cycle4" value="50.0" />
-  <parameter name="gui_duty_cycle5" value="50.0" />
-  <parameter name="gui_duty_cycle6" value="50.0" />
-  <parameter name="gui_duty_cycle7" value="50.0" />
-  <parameter name="gui_duty_cycle8" value="50.0" />
-  <parameter name="gui_duty_cycle9" value="50.0" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="Disabled" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="true" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_enable_output_counter_cascading" value="false" />
-  <parameter name="gui_extclkout_0_source" value="C0" />
-  <parameter name="gui_extclkout_1_source" value="C0" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_fix_vco_frequency" value="false" />
-  <parameter name="gui_fixed_vco_frequency" value="600.0" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="6" />
-  <parameter name="gui_number_of_clocks" value="1" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="250.0" />
-  <parameter name="gui_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0.0" />
-  <parameter name="gui_phase_shift1" value="0.0" />
-  <parameter name="gui_phase_shift10" value="0.0" />
-  <parameter name="gui_phase_shift11" value="0.0" />
-  <parameter name="gui_phase_shift12" value="0.0" />
-  <parameter name="gui_phase_shift13" value="0.0" />
-  <parameter name="gui_phase_shift14" value="0.0" />
-  <parameter name="gui_phase_shift15" value="0.0" />
-  <parameter name="gui_phase_shift16" value="0.0" />
-  <parameter name="gui_phase_shift17" value="0.0" />
-  <parameter name="gui_phase_shift2" value="0.0" />
-  <parameter name="gui_phase_shift3" value="0.0" />
-  <parameter name="gui_phase_shift4" value="0.0" />
-  <parameter name="gui_phase_shift5" value="0.0" />
-  <parameter name="gui_phase_shift6" value="0.0" />
-  <parameter name="gui_phase_shift7" value="0.0" />
-  <parameter name="gui_phase_shift8" value="0.0" />
-  <parameter name="gui_phase_shift9" value="0.0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="false" />
-  <parameter name="gui_pll_bandwidth_preset" value="Low" />
-  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="500.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_NDFB_modes" value="false" />
-  <parameter name="gui_use_locked" value="false" />
-  <parameter name="gui_vco_frequency" value="600.0" />
-  <parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
-  <parameter name="system_info_device_family" value="Arria 10" />
-  <parameter name="system_info_device_speed_grade" value="2" />
-  <parameter name="system_part_trait_speed_grade" value="2" />
- </module>
- <module
-   name="xcvr_tx_pll_reconfig"
-   kind="altera_pll_reconfig"
-   version="15.1"
-   enabled="1">
-  <parameter name="ENABLE_BYTEENABLE" value="false" />
-  <parameter name="ENABLE_MIF" value="false" />
-  <parameter name="MIF_FILE_NAME" value="" />
-  <parameter name="device_family" value="Arria 10" />
- </module>
- <module
-   name="xcvr_tx_ref_clk"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_ip_avl"
-   end="xcvr_core.jesd204_tx_link" />
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="xcvr_core.jesd204_rx_link"
-   end="axi_jesd_xcvr.if_rx_ip_avl" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection kind="clock" version="15.1" start="mem_clk.out_clk" end="mem_rst.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rst_cntrl.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="ad9680_adcfifo.if_dma_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_ad9680_dma.if_s_axis_aclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_core.jesd204_rx_avs_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_core.jesd204_tx_avs_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_ad9680_dma.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_ad9144_dma.m_src_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_tx_pll_reconfig.mgmt_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_pll_reconfig.mgmt_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_ref_clk.out_clk"
-   end="xcvr_tx_lane_pll.pll_refclk0" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_core.reconfig_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_tx_lane_pll.reconfig_clk0" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_ref_clk.out_clk"
-   end="xcvr_tx_pll.refclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_ref_clk.out_clk"
-   end="xcvr_rx_pll.refclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_ref_clk.out_clk"
-   end="xcvr_core.rx_pll_ref_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9680_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9680_core.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9144_core.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_jesd_xcvr.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9144_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="util_cpack_0.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="ad9680_adcfifo.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="util_upack_0.if_dac_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="axi_ad9144_dma.if_fifo_rd_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_ad9680_core.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_jesd_xcvr.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="axi_ad9144_core.if_tx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="axi_jesd_xcvr.if_tx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="xcvr_core.rxlink_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="xcvr_core.txlink_clk" />
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9680_core.adc_ch_0"
-   end="util_cpack_0.adc_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9680_core.adc_ch_1"
-   end="util_cpack_0.adc_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.alldev_lane_aligned"
-   end="xcvr_core.dev_lane_aligned">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9144_core.dac_ch_0"
-   end="util_upack_0.dac_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9144_core.dac_ch_1"
-   end="util_upack_0.dac_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_cpack_0.if_adc_data"
-   end="ad9680_adcfifo.if_adc_wdata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_cpack_0.if_adc_valid"
-   end="ad9680_adcfifo.if_adc_wr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_adc_wovf"
-   end="axi_ad9680_core.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_upack_0.if_dac_valid"
-   end="axi_ad9144_dma.if_fifo_rd_en">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_dma_wdata"
-   end="axi_ad9680_dma.if_s_axis_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_dma_wr"
-   end="axi_ad9680_dma.if_s_axis_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_dma_wready"
-   end="axi_ad9680_dma.if_s_axis_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_dma_xfer_req"
-   end="axi_ad9680_dma.if_s_axis_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9144_dma.if_fifo_rd_dout"
-   end="util_upack_0.if_dac_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9144_dma.if_fifo_rd_underflow"
-   end="axi_ad9144_core.if_dac_dunf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9680_core.if_rx_data"
-   end="axi_jesd_xcvr.if_rx_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sof"
-   end="xcvr_core.rx_sof">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sync"
-   end="xcvr_core.rx_dev_sync_n">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sysref"
-   end="xcvr_core.rx_sysref">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ready"
-   end="xcvr_rst_cntrl.rx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_data"
-   end="axi_ad9144_core.if_tx_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_ip_sysref"
-   end="xcvr_core.tx_sysref">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_lane_pll.pll_cal_busy"
-   end="xcvr_rst_cntrl.pll_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_lane_pll.pll_locked"
-   end="xcvr_rst_cntrl.pll_locked">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.pll_powerdown"
-   end="xcvr_tx_lane_pll.pll_powerdown">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_pll_reconfig.reconfig_from_pll"
-   end="xcvr_tx_pll.reconfig_from_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_pll.reconfig_from_pll"
-   end="xcvr_rx_pll_reconfig.reconfig_from_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_pll.reconfig_to_pll"
-   end="xcvr_tx_pll_reconfig.reconfig_to_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_pll_reconfig.reconfig_to_pll"
-   end="xcvr_rx_pll.reconfig_to_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.rx_analogreset"
-   end="xcvr_core.rx_analogreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.rx_cal_busy"
-   end="xcvr_rst_cntrl.rx_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.rx_digitalreset"
-   end="xcvr_rst_cntrl.rx_digitalreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.rx_is_lockedtodata"
-   end="xcvr_core.rx_islockedtodata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.sync_n"
-   end="axi_jesd_xcvr.if_tx_ip_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.tx_analogreset"
-   end="xcvr_core.tx_analogreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.tx_cal_busy"
-   end="xcvr_core.tx_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.tx_dev_sync_n"
-   end="xcvr_core.mdev_sync_n">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.tx_digitalreset"
-   end="xcvr_rst_cntrl.tx_digitalreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.tx_ready"
-   end="axi_jesd_xcvr.if_tx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_core.tx_serial_clk0_ch0" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_core.tx_serial_clk0_ch1" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_core.tx_serial_clk0_ch2" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_core.tx_serial_clk0_ch3" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_tx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_rx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_rstn"
-   end="xcvr_core.rxlink_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_rstn"
-   end="xcvr_core.txlink_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="util_cpack_0.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="util_cpack_0.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="ad9680_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="ad9680_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_core.jesd204_rx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_core.jesd204_tx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="axi_ad9680_dma.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="axi_ad9144_dma.m_src_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_pll_reconfig.mgmt_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_pll_reconfig.mgmt_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_core.reconfig_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_lane_pll.reconfig_reset0" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_jesd_xcvr.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9144_core.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9680_core.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9680_dma.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9144_dma.s_axi_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>

From 468800bb38896a5045f1267d66666a5102e80a4e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 7 Jun 2016 14:06:42 -0400
Subject: [PATCH 267/972] daq2/a10gx- makefile update

---
 projects/daq2/a10gx/Makefile | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index 51c24bfef..38bbd6d29 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -8,11 +8,11 @@
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
-M_DEPS += system_bd.qsys
+M_DEPS += system_qsys.tcl
 M_DEPS += ../common/daq2_spi.v
-M_DEPS += ../common/daq2_bd.qsys
+M_DEPS += ../common/daq2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
+M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v

From 9d1ae436b1481a1a9a9289bd7788800606399c0c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 9 Jun 2016 09:34:06 +0300
Subject: [PATCH 268/972] common/util_pulse_gen: Rename the ad_tdd_sync module

---
 .../{ad_tdd_sync.v => util_pulse_gen.v}       | 46 +++++++++----------
 library/util_tdd_sync/Makefile                |  2 +-
 library/util_tdd_sync/util_tdd_sync.v         | 12 ++---
 library/util_tdd_sync/util_tdd_sync_ip.tcl    |  2 +-
 4 files changed, 30 insertions(+), 32 deletions(-)
 rename library/common/{ad_tdd_sync.v => util_pulse_gen.v} (70%)

diff --git a/library/common/ad_tdd_sync.v b/library/common/util_pulse_gen.v
similarity index 70%
rename from library/common/ad_tdd_sync.v
rename to library/common/util_pulse_gen.v
index 139768863..b9803ba18 100644
--- a/library/common/ad_tdd_sync.v
+++ b/library/common/util_pulse_gen.v
@@ -38,57 +38,55 @@
 // ***************************************************************************
 `timescale 1ns/1ps
 
-module ad_tdd_sync (
+module util_pulse_gen (
 
-  clk,                                           // system clock (100 Mhz)
+  clk,
   rstn,
 
-  sync                                           // re-synchronization signal
+  pulse
 );
 
-  localparam      PULSE_CNTR_WIDTH  = 7;
-  parameter       TDD_SYNC_PERIOD   = 100000000; // t_period * clk_freq - 1
+  parameter       PULSE_WIDTH = 7;
+  parameter       PULSE_PERIOD = 100000000; // t_period * clk_freq
 
   input           clk;
   input           rstn;
-  output          sync;
+  output          pulse;
 
   // internal registers
 
-  reg     [(PULSE_CNTR_WIDTH-1):0]  pulse_counter   =  {PULSE_CNTR_WIDTH{1'b1}};
-  reg     [31:0]                    sync_counter    = 32'h0;
-  reg                               sync_pulse      =  1'b0;
-  reg                               sync_period_eof =  1'b0;
+  reg     [(PULSE_WIDTH-1):0]  pulse_width_cnt = {PULSE_WIDTH{1'b1}};
+  reg     [31:0]               pulse_period_cnt = 32'h0;
+  reg                          pulse =  1'b0;
 
-  assign sync = sync_pulse;
+  wire                         end_of_period_s;
 
-  // a free running sync pulse generator
+  // a free running pulse generator
 
   always @(posedge clk) begin
     if (rstn == 1'b0) begin
-      sync_counter <= 32'h0;
-      sync_period_eof <= 1'b0;
+      pulse_period_cnt <= 32'h0;
     end else begin
-      sync_counter <= (sync_counter < TDD_SYNC_PERIOD) ? (sync_counter + 1) : 32'b0;
-      sync_period_eof <= (sync_counter == (TDD_SYNC_PERIOD - 1)) ? 1'b1 : 1'b0;
+      pulse_period_cnt <= (pulse_period_cnt < PULSE_PERIOD) ? (pulse_period_cnt + 1) : 32'b0;
     end
   end
 
+  assign  end_of_period_s = (pulse_period_cnt == (PULSE_PERIOD - 1)) ? 1'b1 : 1'b0;
+
   // generate pulse with a specified width
 
   always @(posedge clk) begin
     if (rstn == 1'b0) begin
-      pulse_counter <= 0;
-      sync_pulse <= 0;
+      pulse_width_cnt <= 0;
+      pulse <= 0;
     end else begin
-      pulse_counter <= (sync_pulse == 1'b1) ? pulse_counter + 1 : {PULSE_CNTR_WIDTH{1'h0}};
-      if(sync_period_eof == 1'b1) begin
-        sync_pulse <= 1'b1;
-      end else if(pulse_counter == {PULSE_CNTR_WIDTH{1'b1}}) begin
-        sync_pulse <= 1'b0;
+      pulse_width_cnt <= (pulse == 1'b1) ? pulse_width_cnt + 1 : {PULSE_WIDTH{1'h0}};
+      if(end_of_period_s == 1'b1) begin
+        pulse <= 1'b1;
+      end else if(pulse_width_cnt == {PULSE_WIDTH{1'b1}}) begin
+        pulse <= 1'b0;
       end
     end
   end
 
 endmodule
-
diff --git a/library/util_tdd_sync/Makefile b/library/util_tdd_sync/Makefile
index 27c793e79..91e542b08 100644
--- a/library/util_tdd_sync/Makefile
+++ b/library/util_tdd_sync/Makefile
@@ -8,7 +8,7 @@
 M_DEPS := util_tdd_sync_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_tdd_sync.v
+M_DEPS += ../common/util_pulse_gen.v
 M_DEPS += util_tdd_sync.v
 
 M_VIVADO := vivado -mode batch -source
diff --git a/library/util_tdd_sync/util_tdd_sync.v b/library/util_tdd_sync/util_tdd_sync.v
index 1fa21bd46..e75ce0687 100644
--- a/library/util_tdd_sync/util_tdd_sync.v
+++ b/library/util_tdd_sync/util_tdd_sync.v
@@ -63,10 +63,10 @@ module util_tdd_sync (
   input         sync_in;
   output        sync_out;
 
-  parameter TDD_SYNC_PERIOD     = 100000000;
+  parameter     TDD_SYNC_PERIOD = 100000000;
 
-  reg           sync_mode_d1  = 1'b0;
-  reg           sync_mode_d2  = 1'b0;
+  reg           sync_mode_d1 = 1'b0;
+  reg           sync_mode_d2 = 1'b0;
   reg           sync_out = 1'b0;
 
   wire          sync_internal;
@@ -74,13 +74,13 @@ module util_tdd_sync (
 
   // pulse generator
 
-  ad_tdd_sync #(
-    .TDD_SYNC_PERIOD(TDD_SYNC_PERIOD)
+  util_pulse_gen #(
+    .PULSE_PERIOD(TDD_SYNC_PERIOD)
   )
     i_tdd_sync (
     .clk (clk),
     .rstn (rstn),
-    .sync (sync_internal)
+    .pulse (sync_internal)
   );
 
   // synchronization logic
diff --git a/library/util_tdd_sync/util_tdd_sync_ip.tcl b/library/util_tdd_sync/util_tdd_sync_ip.tcl
index c1345792d..5881b95d5 100644
--- a/library/util_tdd_sync/util_tdd_sync_ip.tcl
+++ b/library/util_tdd_sync/util_tdd_sync_ip.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create util_tdd_sync
 adi_ip_files util_tdd_sync [list \
-  "$ad_hdl_dir/library/common/ad_tdd_sync.v" \
+  "$ad_hdl_dir/library/common/util_pulse_gen.v" \
   "util_tdd_sync.v"]
 
 adi_ip_properties_lite util_tdd_sync

From f84fafaaac4e7d6d49e30d3634b9f90bfb58908f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 10 Jun 2016 10:11:27 +0300
Subject: [PATCH 269/972] adrv9371x/zc706: Fix system top

The dac_fifo_bypass gpio is an internal gpio only. No need for IOBUF.
---
 projects/adrv9371x/zc706/system_top.v | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/projects/adrv9371x/zc706/system_top.v b/projects/adrv9371x/zc706/system_top.v
index c4f1eb46d..c5ee99b82 100644
--- a/projects/adrv9371x/zc706/system_top.v
+++ b/projects/adrv9371x/zc706/system_top.v
@@ -269,7 +269,6 @@ module system_top (
   wire            rx_os_sync;
   wire            tx_sync;
   wire            sysref;
-  wire            ad9371_dac_fifo_bypass_s;
 
   // instantiations
 
@@ -307,12 +306,11 @@ module system_top (
     .IB (sysref_n),
     .O (sysref));
 
-  ad_iobuf #(.DATA_WIDTH(29)) i_iobuf (
-    .dio_t ({gpio_t[60:32]}),
-    .dio_i ({gpio_o[60:32]}),
-    .dio_o ({gpio_i[60:32]}),
-    .dio_p ({ ad9371_dac_fifo_bypass_s, // 60
-              ad9528_reset_b,       // 59
+  ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
+    .dio_t ({gpio_t[59:32]}),
+    .dio_i ({gpio_o[59:32]}),
+    .dio_o ({gpio_i[59:32]}),
+    .dio_p ({ ad9528_reset_b,       // 59
               ad9528_sysref_req,    // 58
               ad9371_tx1_enable,    // 57
               ad9371_tx2_enable,    // 56
@@ -422,7 +420,7 @@ module system_top (
     .tx_ref_clk (ref_clk1),
     .tx_sync (tx_sync),
     .tx_sysref (sysref),
-    .dac_fifo_bypass(ad9371_dac_fifo_bypass_s),
+    .dac_fifo_bypass(gpio_o[60]),
     .sys_rst(sys_rst),
     .sys_clk_clk_p (sys_clk_p),
     .sys_clk_clk_n (sys_clk_n),

From 341b7badee9cb0d359e3fee9fe34de95097eced9 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 10 Jun 2016 14:46:32 +0300
Subject: [PATCH 270/972] library/scripts: Remove all autogenerated interface
 in adi_ip_properties_lite

There are a few IP, which is configured by using just the adi_ip_properties_lite
process, therefor the remove_all_bus_interface will be called in the end of that
process, to make sure that all the autogenerated interfaces are deleted during the
IP properties setup.
---
 library/scripts/adi_ip.tcl | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl
index a765ca247..4baa1c0d2 100644
--- a/library/scripts/adi_ip.tcl
+++ b/library/scripts/adi_ip.tcl
@@ -79,7 +79,6 @@ proc adi_ip_properties {ip_name} {
 
   adi_ip_properties_lite $ip_name
 
-  ipx::remove_all_bus_interface [ipx::current_core]
   ipx::infer_bus_interface {\
     s_axi_awvalid \
     s_axi_awaddr \
@@ -150,6 +149,9 @@ proc adi_ip_properties_lite {ip_name} {
     zynquplus     Production
     kintexu       Production}\
   [ipx::current_core]
+
+  ipx::remove_all_bus_interface [ipx::current_core]
+
 }
 
 proc adi_set_ports_dependency {port_prefix dependency} {

From 8f00760c13f3684983915dd79cae3774459b68aa Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 8 Jun 2016 11:54:46 -0400
Subject: [PATCH 271/972] fmcomms11- initial commit

---
 projects/fmcomms11/common/fmcomms11_bd.tcl  | 223 ++++++++++
 projects/fmcomms11/zc706/Makefile           | 100 +++++
 projects/fmcomms11/zc706/system_bd.tcl      |  25 ++
 projects/fmcomms11/zc706/system_constr.xdc  |  61 +++
 projects/fmcomms11/zc706/system_project.tcl |  22 +
 projects/fmcomms11/zc706/system_top.v       | 425 ++++++++++++++++++++
 6 files changed, 856 insertions(+)
 create mode 100644 projects/fmcomms11/common/fmcomms11_bd.tcl
 create mode 100644 projects/fmcomms11/zc706/Makefile
 create mode 100644 projects/fmcomms11/zc706/system_bd.tcl
 create mode 100644 projects/fmcomms11/zc706/system_constr.xdc
 create mode 100644 projects/fmcomms11/zc706/system_project.tcl
 create mode 100644 projects/fmcomms11/zc706/system_top.v

diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
new file mode 100644
index 000000000..d9c58fdd2
--- /dev/null
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -0,0 +1,223 @@
+
+# daq2
+
+create_bd_port -dir I rx_ref_clk
+create_bd_port -dir O rx_sync
+create_bd_port -dir I rx_sysref
+create_bd_port -dir I -from 3 -to 0 rx_data_p
+create_bd_port -dir I -from 3 -to 0 rx_data_n
+
+create_bd_port -dir I tx_ref_clk
+create_bd_port -dir I tx_sync
+create_bd_port -dir I tx_sysref
+create_bd_port -dir O -from 3 -to 0 tx_data_p
+create_bd_port -dir O -from 3 -to 0 tx_data_n
+
+# dac peripherals
+
+set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
+set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core
+
+set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
+set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
+
+set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma
+set_property -dict [list CONFIG.ID {1}] $axi_ad9144_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma
+set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9144_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
+
+set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack
+
+# adc peripherals
+
+set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
+
+set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
+set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
+
+set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
+set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
+
+set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
+
+# dac/adc common gt
+
+set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq2_gt
+set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq2_gt
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq2_gt
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq2_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq2_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq2_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq2_gt
+set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq2_gt
+
+set util_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq2_gt]
+set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq2_gt
+set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq2_gt
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq2_gt
+set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq2_gt
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq2_gt
+set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq2_gt
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_gt
+
+# connections (gt)
+
+ad_connect  util_daq2_gt/qpll_ref_clk rx_ref_clk
+ad_connect  util_daq2_gt/cpll_ref_clk tx_ref_clk
+
+ad_connect  axi_daq2_gt/gt_qpll_0 util_daq2_gt/gt_qpll_0
+ad_connect  axi_daq2_gt/gt_pll_0 util_daq2_gt/gt_pll_0
+ad_connect  axi_daq2_gt/gt_pll_1 util_daq2_gt/gt_pll_1
+ad_connect  axi_daq2_gt/gt_pll_2 util_daq2_gt/gt_pll_2
+ad_connect  axi_daq2_gt/gt_pll_3 util_daq2_gt/gt_pll_3
+ad_connect  axi_daq2_gt/gt_rx_0 util_daq2_gt/gt_rx_0
+ad_connect  axi_daq2_gt/gt_rx_1 util_daq2_gt/gt_rx_1
+ad_connect  axi_daq2_gt/gt_rx_2 util_daq2_gt/gt_rx_2
+ad_connect  axi_daq2_gt/gt_rx_3 util_daq2_gt/gt_rx_3
+ad_connect  axi_daq2_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
+ad_connect  axi_daq2_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
+ad_connect  axi_daq2_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
+ad_connect  axi_daq2_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
+ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
+ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
+ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
+ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
+ad_connect  axi_daq2_gt/gt_tx_0 util_daq2_gt/gt_tx_0
+ad_connect  axi_daq2_gt/gt_tx_1 util_daq2_gt/gt_tx_1
+ad_connect  axi_daq2_gt/gt_tx_2 util_daq2_gt/gt_tx_2
+ad_connect  axi_daq2_gt/gt_tx_3 util_daq2_gt/gt_tx_3
+ad_connect  axi_daq2_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx
+ad_connect  axi_daq2_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx
+ad_connect  axi_daq2_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx
+ad_connect  axi_daq2_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx
+
+# connections (dac)
+
+ad_connect  util_daq2_gt/tx_sysref tx_sysref
+ad_connect  util_daq2_gt/tx_p tx_data_p
+ad_connect  util_daq2_gt/tx_n tx_data_n
+ad_connect  util_daq2_gt/tx_sync tx_sync
+ad_connect  util_daq2_gt/tx_out_clk util_daq2_gt/tx_clk
+ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk
+ad_connect  util_daq2_gt/tx_ip_rst axi_ad9144_jesd/tx_reset
+ad_connect  util_daq2_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done
+ad_connect  util_daq2_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref
+ad_connect  util_daq2_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
+ad_connect  util_daq2_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
+ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_core/tx_clk
+ad_connect  util_daq2_gt/tx_data axi_ad9144_core/tx_data
+ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_upack/dac_clk
+ad_connect  axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
+ad_connect  axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
+ad_connect  axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
+ad_connect  axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1
+ad_connect  axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1
+ad_connect  axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1
+ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk
+ad_connect  axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
+ad_connect  axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
+ad_connect  axi_ad9144_upack/dma_xfer_in axi_ad9144_fifo/dac_xfer_out
+ad_connect  sys_cpu_clk axi_ad9144_fifo/dma_clk
+ad_connect  sys_cpu_reset axi_ad9144_fifo/dma_rst
+ad_connect  sys_cpu_clk axi_ad9144_dma/m_axis_aclk
+ad_connect  sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
+ad_connect  axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req
+ad_connect  axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready
+ad_connect  axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data
+ad_connect  axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid
+ad_connect  axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
+
+# connections (adc)
+
+ad_connect  util_daq2_gt/rx_sysref rx_sysref
+ad_connect  util_daq2_gt/rx_p rx_data_p
+ad_connect  util_daq2_gt/rx_n rx_data_n
+ad_connect  util_daq2_gt/rx_sync rx_sync
+ad_connect  util_daq2_gt/rx_out_clk util_daq2_gt/rx_clk
+ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
+ad_connect  util_daq2_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
+ad_connect  util_daq2_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
+ad_connect  util_daq2_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
+ad_connect  util_daq2_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
+ad_connect  util_daq2_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
+ad_connect  util_daq2_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
+ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_core/rx_clk
+ad_connect  util_daq2_gt/rx_data axi_ad9680_core/rx_data
+ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_cpack/adc_clk
+ad_connect  util_daq2_gt/rx_rst axi_ad9680_cpack/adc_rst
+ad_connect  axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
+ad_connect  axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
+ad_connect  axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
+ad_connect  axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
+ad_connect  axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
+ad_connect  axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
+ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_fifo/adc_clk
+ad_connect  util_daq2_gt/rx_rst axi_ad9680_fifo/adc_rst
+ad_connect  axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
+ad_connect  axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
+ad_connect  sys_cpu_clk axi_ad9680_fifo/dma_clk
+ad_connect  sys_cpu_clk axi_ad9680_dma/s_axis_aclk
+ad_connect  sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
+ad_connect  axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
+ad_connect  axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
+ad_connect  axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
+ad_connect  axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
+ad_connect  axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
+
+# interconnect (cpu)
+
+ad_cpu_interconnect 0x44A60000 axi_daq2_gt
+ad_cpu_interconnect 0x44A00000 axi_ad9144_core
+ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
+ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
+ad_cpu_interconnect 0x44A10000 axi_ad9680_core
+ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
+ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
+
+# gt uses hp3, and 100MHz clock for both DRP and AXI4
+
+ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
+ad_mem_hp3_interconnect sys_cpu_clk axi_daq2_gt/m_axi
+
+# interconnect (mem/dac)
+
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk axi_ad9144_dma/m_src_axi
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
+
+# interrupts
+
+ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
+ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
+
+ad_connect  axi_ad9144_core/dac_ddata_2 GND
+ad_connect  axi_ad9144_core/dac_ddata_3 GND
+
+
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
new file mode 100644
index 000000000..ec2fa7313
--- /dev/null
+++ b/projects/fmcomms11/zc706/Makefile
@@ -0,0 +1,100 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/daq2_spi.v
+M_DEPS += ../common/daq2_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl
+M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
+M_DEPS += ../../common/zc706/zc706_system_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
+M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
+M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all lib clean clean-all
+all: lib daq2_zc706.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9144 clean
+	make -C ../../../library/axi_ad9680 clean
+	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_dacfifo clean
+	make -C ../../../library/util_jesd_gt clean
+	make -C ../../../library/util_upack clean
+
+
+daq2_zc706.sdk/system_top.hdf: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> daq2_zc706_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9144
+	make -C ../../../library/axi_ad9680
+	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_adcfifo
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_dacfifo
+	make -C ../../../library/util_jesd_gt
+	make -C ../../../library/util_upack
+
+####################################################################################
+####################################################################################
diff --git a/projects/fmcomms11/zc706/system_bd.tcl b/projects/fmcomms11/zc706/system_bd.tcl
new file mode 100644
index 000000000..44e72997e
--- /dev/null
+++ b/projects/fmcomms11/zc706/system_bd.tcl
@@ -0,0 +1,25 @@
+
+source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+
+p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
+
+create_bd_port -dir I -type rst sys_rst
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
+
+set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
+
+ad_connect  sys_rst axi_ad9680_fifo/sys_rst
+ad_connect  sys_clk axi_ad9680_fifo/sys_clk
+ad_connect  ddr3 axi_ad9680_fifo/ddr3
+
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
+  [get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
+  [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
+  SEG_axi_ddr_cntrl_memaddr
+
+source ../common/daq2_bd.tcl
+
diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc
new file mode 100644
index 000000000..df68021e6
--- /dev/null
+++ b/projects/fmcomms11/zc706/system_constr.xdc
@@ -0,0 +1,61 @@
+
+# daq2
+
+set_property  -dict {PACKAGE_PIN  AA8 } [get_ports rx_ref_clk_p]                                      ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  AA7 } [get_ports rx_ref_clk_n]                                      ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[0]]                                      ; ## A10  FMC_HPC_DP3_M2C_P
+set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[0]]                                      ; ## A11  FMC_HPC_DP3_M2C_N
+set_property  -dict {PACKAGE_PIN  AH10} [get_ports rx_data_p[1]]                                      ; ## C06  FMC_HPC_DP0_M2C_P
+set_property  -dict {PACKAGE_PIN  AH9 } [get_ports rx_data_n[1]]                                      ; ## C07  FMC_HPC_DP0_M2C_N
+set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[2]]                                      ; ## A06  FMC_HPC_DP2_M2C_P
+set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[2]]                                      ; ## A07  FMC_HPC_DP2_M2C_N
+set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[3]]                                      ; ## A02  FMC_HPC_DP1_M2C_P
+set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[3]]                                      ; ## A03  FMC_HPC_DP1_M2C_N
+set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## D08  FMC_HPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## D09  FMC_HPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]    ; ## G09  FMC_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]    ; ## G10  FMC_HPC_LA03_N
+
+set_property  -dict {PACKAGE_PIN  AD10} [get_ports tx_ref_clk_p]                                      ; ## D04  FMC_HPC_GBTCLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  AD9 } [get_ports tx_ref_clk_n]                                      ; ## D05  FMC_HPC_GBTCLK0_M2C_N
+set_property  -dict {PACKAGE_PIN  AK2 } [get_ports tx_data_p[0]]                                      ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[0])
+set_property  -dict {PACKAGE_PIN  AK1 } [get_ports tx_data_n[0]]                                      ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[0])
+set_property  -dict {PACKAGE_PIN  AK10} [get_ports tx_data_p[1]]                                      ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[3])
+set_property  -dict {PACKAGE_PIN  AK9 } [get_ports tx_data_n[1]]                                      ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[3])
+set_property  -dict {PACKAGE_PIN  AJ4 } [get_ports tx_data_p[2]]                                      ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[1])
+set_property  -dict {PACKAGE_PIN  AJ3 } [get_ports tx_data_n[2]]                                      ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[1])
+set_property  -dict {PACKAGE_PIN  AK6 } [get_ports tx_data_p[3]]                                      ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
+set_property  -dict {PACKAGE_PIN  AK5 } [get_ports tx_data_n[3]]                                      ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
+set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p]      ; ## H07  FMC_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n]      ; ## H08  FMC_HPC_LA02_N
+set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p]    ; ## H10  FMC_HPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n]    ; ## H11  FMC_HPC_LA04_N
+
+set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVCMOS25} [get_ports spi_csn_clk]                  ; ## D11  FMC_HPC_LA05_P
+set_property  -dict {PACKAGE_PIN  AG24  IOSTANDARD LVCMOS25} [get_ports spi_csn_dac]                  ; ## C14  FMC_HPC_LA10_P
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports spi_csn_adc]                  ; ## D15  FMC_HPC_LA09_N
+set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## D12  FMC_HPC_LA05_N
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS25} [get_ports spi_sdio]                     ; ## D14  FMC_HPC_LA09_P
+set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVCMOS25} [get_ports spi_dir]                      ; ## G13  FMC_HPC_LA08_N
+
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports clkd_sync]                    ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  AG25  IOSTANDARD LVCMOS25} [get_ports dac_reset]                    ; ## C15  FMC_HPC_LA10_N
+set_property  -dict {PACKAGE_PIN  AF24  IOSTANDARD LVCMOS25} [get_ports dac_txen]                     ; ## G16  FMC_HPC_LA12_N
+set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports adc_pd]                       ; ## C10  FMC_HPC_LA06_P
+
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports clkd_status[0]]               ; ## D17  FMC_HPC_LA13_P
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports clkd_status[1]]               ; ## D18  FMC_HPC_LA13_N
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports dac_irq]                      ; ## G15  FMC_HPC_LA12_P
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports adc_fda]                      ; ## H16  FMC_HPC_LA11_P
+set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports adc_fdb]                      ; ## H17  FMC_HPC_LA11_N
+
+set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p]         ; ## H13  FMC_HPC_LA07_P
+set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n]         ; ## H14  FMC_HPC_LA07_N
+
+# clocks
+
+create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
+create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+
diff --git a/projects/fmcomms11/zc706/system_project.tcl b/projects/fmcomms11/zc706/system_project.tcl
new file mode 100644
index 000000000..8d6209938
--- /dev/null
+++ b/projects/fmcomms11/zc706/system_project.tcl
@@ -0,0 +1,22 @@
+
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create daq2_zc706
+adi_project_files daq2_zc706 [list \
+  "../common/daq2_spi.v" \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
+  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
+
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+
+adi_project_run daq2_zc706
+
+
diff --git a/projects/fmcomms11/zc706/system_top.v b/projects/fmcomms11/zc706/system_top.v
new file mode 100644
index 000000000..071300f3a
--- /dev/null
+++ b/projects/fmcomms11/zc706/system_top.v
@@ -0,0 +1,425 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  gpio_bd,
+
+  hdmi_out_clk,
+  hdmi_vsync,
+  hdmi_hsync,
+  hdmi_data_e,
+  hdmi_data,
+
+  spdif,
+
+  sys_rst,
+  sys_clk_p,
+  sys_clk_n,
+
+  ddr3_addr,
+  ddr3_ba,
+  ddr3_cas_n,
+  ddr3_ck_n,
+  ddr3_ck_p,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_dm,
+  ddr3_dq,
+  ddr3_dqs_n,
+  ddr3_dqs_p,
+  ddr3_odt,
+  ddr3_ras_n,
+  ddr3_reset_n,
+  ddr3_we_n,
+
+  iic_scl,
+  iic_sda,
+
+  rx_ref_clk_p,
+  rx_ref_clk_n,
+  rx_sysref_p,
+  rx_sysref_n,
+  rx_sync_p,
+  rx_sync_n,
+  rx_data_p,
+  rx_data_n,
+
+  tx_ref_clk_p,
+  tx_ref_clk_n,
+  tx_sysref_p,
+  tx_sysref_n,
+  tx_sync_p,
+  tx_sync_n,
+  tx_data_p,
+  tx_data_n,
+
+  trig_p,
+  trig_n,
+
+  adc_fdb,
+  adc_fda,
+  dac_irq,
+  clkd_status,
+
+  adc_pd,
+  dac_txen,
+  dac_reset,
+  clkd_sync,
+
+  spi_csn_clk,
+  spi_csn_dac,
+  spi_csn_adc,
+  spi_clk,
+  spi_sdio,
+  spi_dir);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout   [14:0]  gpio_bd;
+
+  output          hdmi_out_clk;
+  output          hdmi_vsync;
+  output          hdmi_hsync;
+  output          hdmi_data_e;
+  output  [23:0]  hdmi_data;
+
+  output          spdif;
+
+  input           sys_rst;
+  input           sys_clk_p;
+  input           sys_clk_n;
+
+  output  [13:0]  ddr3_addr;
+  output  [ 2:0]  ddr3_ba;
+  output          ddr3_cas_n;
+  output  [ 0:0]  ddr3_ck_n;
+  output  [ 0:0]  ddr3_ck_p;
+  output  [ 0:0]  ddr3_cke;
+  output  [ 0:0]  ddr3_cs_n;
+  output  [ 7:0]  ddr3_dm;
+  inout   [63:0]  ddr3_dq;
+  inout   [ 7:0]  ddr3_dqs_n;
+  inout   [ 7:0]  ddr3_dqs_p;
+  output  [ 0:0]  ddr3_odt;
+  output          ddr3_ras_n;
+  output          ddr3_reset_n;
+  output          ddr3_we_n;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  input           rx_ref_clk_p;
+  input           rx_ref_clk_n;
+  input           rx_sysref_p;
+  input           rx_sysref_n;
+  output          rx_sync_p;
+  output          rx_sync_n;
+  input   [ 3:0]  rx_data_p;
+  input   [ 3:0]  rx_data_n;
+
+  input           tx_ref_clk_p;
+  input           tx_ref_clk_n;
+  input           tx_sysref_p;
+  input           tx_sysref_n;
+  input           tx_sync_p;
+  input           tx_sync_n;
+  output  [ 3:0]  tx_data_p;
+  output  [ 3:0]  tx_data_n;
+
+  input           trig_p;
+  input           trig_n;
+
+  inout           adc_fdb;
+  inout           adc_fda;
+  inout           dac_irq;
+  inout   [ 1:0]  clkd_status;
+
+  inout           adc_pd;
+  inout           dac_txen;
+  inout           dac_reset;
+  inout           clkd_sync;
+
+  output          spi_csn_clk;
+  output          spi_csn_dac;
+  output          spi_csn_adc;
+  output          spi_clk;
+  inout           spi_sdio;
+  output          spi_dir;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire    [ 2:0]  spi0_csn;
+  wire            spi0_clk;
+  wire            spi0_mosi;
+  wire            spi0_miso;
+  wire    [ 2:0]  spi1_csn;
+  wire            spi1_clk;
+  wire            spi1_mosi;
+  wire            spi1_miso;
+  wire            trig;
+  wire            rx_ref_clk;
+  wire            rx_sysref;
+  wire            rx_sync;
+  wire            tx_ref_clk;
+  wire            tx_sysref;
+  wire            tx_sync;
+
+  // spi
+
+  assign spi_csn_adc = spi0_csn[2];
+  assign spi_csn_dac = spi0_csn[1];
+  assign spi_csn_clk = spi0_csn[0];
+
+  // instantiations
+
+  IBUFDS_GTE2 i_ibufds_rx_ref_clk (
+    .CEB (1'd0),
+    .I (rx_ref_clk_p),
+    .IB (rx_ref_clk_n),
+    .O (rx_ref_clk),
+    .ODIV2 ());
+
+  IBUFDS i_ibufds_rx_sysref (
+    .I (rx_sysref_p),
+    .IB (rx_sysref_n),
+    .O (rx_sysref));
+
+  OBUFDS i_obufds_rx_sync (
+    .I (rx_sync),
+    .O (rx_sync_p),
+    .OB (rx_sync_n));
+
+  IBUFDS_GTE2 i_ibufds_tx_ref_clk (
+    .CEB (1'd0),
+    .I (tx_ref_clk_p),
+    .IB (tx_ref_clk_n),
+    .O (tx_ref_clk),
+    .ODIV2 ());
+
+  IBUFDS i_ibufds_tx_sysref (
+    .I (tx_sysref_p),
+    .IB (tx_sysref_n),
+    .O (tx_sysref));
+
+  IBUFDS i_ibufds_tx_sync (
+    .I (tx_sync_p),
+    .IB (tx_sync_n),
+    .O (tx_sync));
+
+  daq2_spi i_spi (
+    .spi_csn (spi0_csn),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi0_mosi),
+    .spi_miso (spi0_miso),
+    .spi_sdio (spi_sdio),
+    .spi_dir (spi_dir));
+
+  IBUFDS i_ibufds_trig (
+    .I (trig_p),
+    .IB (trig_n),
+    .O (trig));
+
+  assign gpio_i[43] = trig;
+  assign spi_clk = spi0_clk;
+
+  ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
+    .dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
+    .dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
+    .dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
+    .dio_p ({ adc_pd,           // 42
+              dac_txen,         // 41
+              dac_reset,        // 40
+              clkd_sync,        // 38
+              adc_fdb,          // 36
+              adc_fda,          // 35
+              dac_irq,          // 34
+              clkd_status}));   // 32
+
+  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
+    .dio_t (gpio_t[14:0]),
+    .dio_i (gpio_o[14:0]),
+    .dio_o (gpio_i[14:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr3_addr (ddr3_addr),
+    .ddr3_ba (ddr3_ba),
+    .ddr3_cas_n (ddr3_cas_n),
+    .ddr3_ck_n (ddr3_ck_n),
+    .ddr3_ck_p (ddr3_ck_p),
+    .ddr3_cke (ddr3_cke),
+    .ddr3_cs_n (ddr3_cs_n),
+    .ddr3_dm (ddr3_dm),
+    .ddr3_dq (ddr3_dq),
+    .ddr3_dqs_n (ddr3_dqs_n),
+    .ddr3_dqs_p (ddr3_dqs_p),
+    .ddr3_odt (ddr3_odt),
+    .ddr3_ras_n (ddr3_ras_n),
+    .ddr3_reset_n (ddr3_reset_n),
+    .ddr3_we_n (ddr3_we_n),
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .rx_data_n (rx_data_n),
+    .rx_data_p (rx_data_p),
+    .rx_ref_clk (rx_ref_clk),
+    .rx_sync (rx_sync),
+    .rx_sysref (rx_sysref),
+    .spdif (spdif),
+    .spi0_clk_i (spi0_clk),
+    .spi0_clk_o (spi0_clk),
+    .spi0_csn_0_o (spi0_csn[0]),
+    .spi0_csn_1_o (spi0_csn[1]),
+    .spi0_csn_2_o (spi0_csn[2]),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi0_miso),
+    .spi0_sdo_i (spi0_mosi),
+    .spi0_sdo_o (spi0_mosi),
+    .spi1_clk_i (spi1_clk),
+    .spi1_clk_o (spi1_clk),
+    .spi1_csn_0_o (spi1_csn[0]),
+    .spi1_csn_1_o (spi1_csn[1]),
+    .spi1_csn_2_o (spi1_csn[2]),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b1),
+    .spi1_sdo_i (spi1_mosi),
+    .spi1_sdo_o (spi1_mosi),
+    .sys_clk_clk_n (sys_clk_n),
+    .sys_clk_clk_p (sys_clk_p),
+    .sys_rst (sys_rst),
+    .tx_data_n (tx_data_n),
+    .tx_data_p (tx_data_p),
+    .tx_ref_clk (tx_ref_clk),
+    .tx_sync (tx_sync),
+    .tx_sysref (tx_sysref));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From fdc1240cc89ad5bd89b631697a5854a8633f7b19 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 10 Jun 2016 10:19:45 -0400
Subject: [PATCH 272/972] fmcomms11- spi

---
 projects/fmcomms11/common/fmcomms11_spi.v | 109 ++++++++++++++++++++++
 1 file changed, 109 insertions(+)
 create mode 100644 projects/fmcomms11/common/fmcomms11_spi.v

diff --git a/projects/fmcomms11/common/fmcomms11_spi.v b/projects/fmcomms11/common/fmcomms11_spi.v
new file mode 100644
index 000000000..546948627
--- /dev/null
+++ b/projects/fmcomms11/common/fmcomms11_spi.v
@@ -0,0 +1,109 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module fmcomms11_spi (
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  spi_sdio,
+  spi_dir);
+
+  // 4 wire
+
+  input   [ 2:0]  spi_csn;
+  input           spi_clk;
+  input           spi_mosi;
+  output          spi_miso;
+
+  // 3 wire
+
+  inout           spi_sdio;
+  output          spi_dir;
+
+  // internal registers
+
+  reg     [ 5:0]  spi_count = 'd0;
+  reg             spi_rd_wr_n = 'd0;
+  reg             spi_enable = 'd0;
+
+  // internal signals
+
+  wire            spi_csn_s;
+  wire            spi_enable_s;
+
+  // check on rising edge and change on falling edge
+
+  assign spi_csn_s = & spi_csn;
+  assign spi_dir = ~spi_enable_s;
+  assign spi_enable_s = spi_enable & ~spi_csn_s;
+
+  always @(posedge spi_clk or posedge spi_csn_s) begin
+    if (spi_csn_s == 1'b1) begin
+      spi_count <= 6'd0;
+      spi_rd_wr_n <= 1'd0;
+    end else begin
+      spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
+      if (spi_count == 6'd0) begin
+        spi_rd_wr_n <= spi_mosi;
+      end
+    end
+  end
+
+  always @(negedge spi_clk or posedge spi_csn_s) begin
+    if (spi_csn_s == 1'b1) begin
+      spi_enable <= 1'b0;
+    end else begin
+      if (spi_count == 6'd16) begin
+        spi_enable <= spi_rd_wr_n;
+      end
+    end
+  end
+
+  // io butter
+
+  assign spi_miso = spi_sdio;
+  assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 509f031d58d9563e541be9ae43cb367483cac6f5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 10 Jun 2016 14:20:00 -0400
Subject: [PATCH 273/972] fmcomms11- updates

---
 projects/fmcomms11/common/fmcomms11_bd.tcl | 345 ++++++++++++---------
 projects/fmcomms11/common/fmcomms11_spi.v  |  45 ++-
 2 files changed, 227 insertions(+), 163 deletions(-)

diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index d9c58fdd2..a33f06c09 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -1,26 +1,25 @@
 
-# daq2
+# fmcomms11
+
+create_bd_port -dir I sysref
 
 create_bd_port -dir I rx_ref_clk
 create_bd_port -dir O rx_sync
-create_bd_port -dir I rx_sysref
-create_bd_port -dir I -from 3 -to 0 rx_data_p
-create_bd_port -dir I -from 3 -to 0 rx_data_n
+create_bd_port -dir I -from 7 -to 0 rx_data_p
+create_bd_port -dir I -from 7 -to 0 rx_data_n
 
 create_bd_port -dir I tx_ref_clk
 create_bd_port -dir I tx_sync
-create_bd_port -dir I tx_sysref
-create_bd_port -dir O -from 3 -to 0 tx_data_p
-create_bd_port -dir O -from 3 -to 0 tx_data_n
+create_bd_port -dir O -from 7 -to 0 tx_data_p
+create_bd_port -dir O -from 7 -to 0 tx_data_n
 
 # dac peripherals
 
 set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
-set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core
 
 set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
-set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
+set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd
 
 set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma
@@ -31,118 +30,176 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
-
-set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9144_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9144_dma
 
 # adc peripherals
 
-set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
+set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
 
-set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
-set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
-set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
+set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
+set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
 
-set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
-set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
-set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
-set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma
-set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma
-set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
-set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
-set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
-set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
-set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
-
-set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
+set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.ID {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 
 # dac/adc common gt
 
-set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq2_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq2_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq2_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq2_gt
+set axi_fmcomms11_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcomms11_gt]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_0 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_1 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_2 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_3 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_4 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_5 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_6 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_7 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcomms11_gt
 
-set util_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq2_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq2_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq2_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq2_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq2_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq2_gt
-set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq2_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_gt
+set util_fmcomms11_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcomms11_gt]
+set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $util_fmcomms11_gt
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcomms11_gt
+set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcomms11_gt
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_gt
+set_property -dict [list CONFIG.TX_ENABLE {1}] $util_fmcomms11_gt
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_gt
 
 # connections (gt)
 
-ad_connect  util_daq2_gt/qpll_ref_clk rx_ref_clk
-ad_connect  util_daq2_gt/cpll_ref_clk tx_ref_clk
+ad_connect  util_fmcomms11_gt/qpll_ref_clk rx_ref_clk
+ad_connect  util_fmcomms11_gt/cpll_ref_clk tx_ref_clk
 
-ad_connect  axi_daq2_gt/gt_qpll_0 util_daq2_gt/gt_qpll_0
-ad_connect  axi_daq2_gt/gt_pll_0 util_daq2_gt/gt_pll_0
-ad_connect  axi_daq2_gt/gt_pll_1 util_daq2_gt/gt_pll_1
-ad_connect  axi_daq2_gt/gt_pll_2 util_daq2_gt/gt_pll_2
-ad_connect  axi_daq2_gt/gt_pll_3 util_daq2_gt/gt_pll_3
-ad_connect  axi_daq2_gt/gt_rx_0 util_daq2_gt/gt_rx_0
-ad_connect  axi_daq2_gt/gt_rx_1 util_daq2_gt/gt_rx_1
-ad_connect  axi_daq2_gt/gt_rx_2 util_daq2_gt/gt_rx_2
-ad_connect  axi_daq2_gt/gt_rx_3 util_daq2_gt/gt_rx_3
-ad_connect  axi_daq2_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
-ad_connect  axi_daq2_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
-ad_connect  axi_daq2_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
-ad_connect  axi_daq2_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
-ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq2_gt/gt_tx_0 util_daq2_gt/gt_tx_0
-ad_connect  axi_daq2_gt/gt_tx_1 util_daq2_gt/gt_tx_1
-ad_connect  axi_daq2_gt/gt_tx_2 util_daq2_gt/gt_tx_2
-ad_connect  axi_daq2_gt/gt_tx_3 util_daq2_gt/gt_tx_3
-ad_connect  axi_daq2_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx
-ad_connect  axi_daq2_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx
-ad_connect  axi_daq2_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx
-ad_connect  axi_daq2_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx
+ad_connect  axi_fmcomms11_gt/gt_qpll_0 util_fmcomms11_gt/gt_qpll_0
+ad_connect  axi_fmcomms11_gt/gt_qpll_1 util_fmcomms11_gt/gt_qpll_1
+ad_connect  axi_fmcomms11_gt/gt_pll_0 util_fmcomms11_gt/gt_pll_0
+ad_connect  axi_fmcomms11_gt/gt_pll_1 util_fmcomms11_gt/gt_pll_1
+ad_connect  axi_fmcomms11_gt/gt_pll_2 util_fmcomms11_gt/gt_pll_2
+ad_connect  axi_fmcomms11_gt/gt_pll_3 util_fmcomms11_gt/gt_pll_3
+ad_connect  axi_fmcomms11_gt/gt_pll_4 util_fmcomms11_gt/gt_pll_4
+ad_connect  axi_fmcomms11_gt/gt_pll_5 util_fmcomms11_gt/gt_pll_5
+ad_connect  axi_fmcomms11_gt/gt_pll_6 util_fmcomms11_gt/gt_pll_6
+ad_connect  axi_fmcomms11_gt/gt_pll_7 util_fmcomms11_gt/gt_pll_7
+ad_connect  axi_fmcomms11_gt/gt_rx_0 util_fmcomms11_gt/gt_rx_0
+ad_connect  axi_fmcomms11_gt/gt_rx_1 util_fmcomms11_gt/gt_rx_1
+ad_connect  axi_fmcomms11_gt/gt_rx_2 util_fmcomms11_gt/gt_rx_2
+ad_connect  axi_fmcomms11_gt/gt_rx_3 util_fmcomms11_gt/gt_rx_3
+ad_connect  axi_fmcomms11_gt/gt_rx_4 util_fmcomms11_gt/gt_rx_4
+ad_connect  axi_fmcomms11_gt/gt_rx_5 util_fmcomms11_gt/gt_rx_5
+ad_connect  axi_fmcomms11_gt/gt_rx_6 util_fmcomms11_gt/gt_rx_6
+ad_connect  axi_fmcomms11_gt/gt_rx_7 util_fmcomms11_gt/gt_rx_7
+ad_connect  axi_fmcomms11_gt/gt_rx_ip_0 axi_ad9625_jesd/gt0_rx
+ad_connect  axi_fmcomms11_gt/gt_rx_ip_1 axi_ad9625_jesd/gt1_rx
+ad_connect  axi_fmcomms11_gt/gt_rx_ip_2 axi_ad9625_jesd/gt2_rx
+ad_connect  axi_fmcomms11_gt/gt_rx_ip_3 axi_ad9625_jesd/gt3_rx
+ad_connect  axi_fmcomms11_gt/gt_rx_ip_4 axi_ad9625_jesd/gt4_rx
+ad_connect  axi_fmcomms11_gt/gt_rx_ip_5 axi_ad9625_jesd/gt5_rx
+ad_connect  axi_fmcomms11_gt/gt_rx_ip_6 axi_ad9625_jesd/gt6_rx
+ad_connect  axi_fmcomms11_gt/gt_rx_ip_7 axi_ad9625_jesd/gt7_rx
+ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_0 axi_ad9625_jesd/rxencommaalign_out
+ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_1 axi_ad9625_jesd/rxencommaalign_out
+ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_2 axi_ad9625_jesd/rxencommaalign_out
+ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_3 axi_ad9625_jesd/rxencommaalign_out
+ad_connect  axi_fmcomms11_gt/gt_tx_0 util_fmcomms11_gt/gt_tx_0
+ad_connect  axi_fmcomms11_gt/gt_tx_1 util_fmcomms11_gt/gt_tx_1
+ad_connect  axi_fmcomms11_gt/gt_tx_2 util_fmcomms11_gt/gt_tx_2
+ad_connect  axi_fmcomms11_gt/gt_tx_3 util_fmcomms11_gt/gt_tx_3
+ad_connect  axi_fmcomms11_gt/gt_tx_4 util_fmcomms11_gt/gt_tx_4
+ad_connect  axi_fmcomms11_gt/gt_tx_5 util_fmcomms11_gt/gt_tx_5
+ad_connect  axi_fmcomms11_gt/gt_tx_6 util_fmcomms11_gt/gt_tx_6
+ad_connect  axi_fmcomms11_gt/gt_tx_7 util_fmcomms11_gt/gt_tx_7
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_4 axi_ad9144_jesd/gt4_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_5 axi_ad9144_jesd/gt5_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_6 axi_ad9144_jesd/gt6_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_7 axi_ad9144_jesd/gt7_tx
 
 # connections (dac)
 
-ad_connect  util_daq2_gt/tx_sysref tx_sysref
-ad_connect  util_daq2_gt/tx_p tx_data_p
-ad_connect  util_daq2_gt/tx_n tx_data_n
-ad_connect  util_daq2_gt/tx_sync tx_sync
-ad_connect  util_daq2_gt/tx_out_clk util_daq2_gt/tx_clk
-ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk
-ad_connect  util_daq2_gt/tx_ip_rst axi_ad9144_jesd/tx_reset
-ad_connect  util_daq2_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done
-ad_connect  util_daq2_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref
-ad_connect  util_daq2_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
-ad_connect  util_daq2_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
-ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_core/tx_clk
-ad_connect  util_daq2_gt/tx_data axi_ad9144_core/tx_data
-ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_upack/dac_clk
-ad_connect  axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
-ad_connect  axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
-ad_connect  axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
-ad_connect  axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1
-ad_connect  axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1
-ad_connect  axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1
-ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk
-ad_connect  axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
-ad_connect  axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
-ad_connect  axi_ad9144_upack/dma_xfer_in axi_ad9144_fifo/dac_xfer_out
+ad_connect  util_fmcomms11_gt/tx_sysref sysref
+ad_connect  util_fmcomms11_gt/tx_p tx_data_p
+ad_connect  util_fmcomms11_gt/tx_n tx_data_n
+ad_connect  util_fmcomms11_gt/tx_sync tx_sync
+ad_connect  util_fmcomms11_gt/tx_out_clk util_fmcomms11_gt/tx_clk
+ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk
+ad_connect  util_fmcomms11_gt/tx_ip_rst axi_ad9144_jesd/tx_reset
+ad_connect  util_fmcomms11_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done
+ad_connect  util_fmcomms11_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref
+ad_connect  util_fmcomms11_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
+ad_connect  util_fmcomms11_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
+ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9144_core/tx_clk
+ad_connect  util_fmcomms11_gt/tx_data axi_ad9144_core/tx_data
+ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9144_fifo/dac_clk
+ad_connect  axi_ad9144_core/dac_valid_0 axi_ad9144_fifo/dac_valid
+ad_connect  axi_ad9144_core/dac_ddata_0 axi_ad9144_fifo/dac_data
 ad_connect  sys_cpu_clk axi_ad9144_fifo/dma_clk
 ad_connect  sys_cpu_reset axi_ad9144_fifo/dma_rst
 ad_connect  sys_cpu_clk axi_ad9144_dma/m_axis_aclk
@@ -155,67 +212,61 @@ ad_connect  axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
 
 # connections (adc)
 
-ad_connect  util_daq2_gt/rx_sysref rx_sysref
-ad_connect  util_daq2_gt/rx_p rx_data_p
-ad_connect  util_daq2_gt/rx_n rx_data_n
-ad_connect  util_daq2_gt/rx_sync rx_sync
-ad_connect  util_daq2_gt/rx_out_clk util_daq2_gt/rx_clk
-ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
-ad_connect  util_daq2_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
-ad_connect  util_daq2_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
-ad_connect  util_daq2_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
-ad_connect  util_daq2_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
-ad_connect  util_daq2_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
-ad_connect  util_daq2_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
-ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_core/rx_clk
-ad_connect  util_daq2_gt/rx_data axi_ad9680_core/rx_data
-ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_cpack/adc_clk
-ad_connect  util_daq2_gt/rx_rst axi_ad9680_cpack/adc_rst
-ad_connect  axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
-ad_connect  axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
-ad_connect  axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
-ad_connect  axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
-ad_connect  axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
-ad_connect  axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
-ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_fifo/adc_clk
-ad_connect  util_daq2_gt/rx_rst axi_ad9680_fifo/adc_rst
-ad_connect  axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
-ad_connect  axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
-ad_connect  sys_cpu_clk axi_ad9680_fifo/dma_clk
-ad_connect  sys_cpu_clk axi_ad9680_dma/s_axis_aclk
-ad_connect  sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
-ad_connect  axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
-ad_connect  axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
-ad_connect  axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
-ad_connect  axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
-ad_connect  axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
+ad_connect  util_fmcomms11_gt/rx_sysref sysref
+ad_connect  util_fmcomms11_gt/rx_p rx_data_p
+ad_connect  util_fmcomms11_gt/rx_n rx_data_n
+ad_connect  util_fmcomms11_gt/rx_sync rx_sync
+ad_connect  util_fmcomms11_gt/rx_out_clk util_fmcomms11_gt/rx_clk
+ad_connect  util_fmcomms11_gt/rx_out_clk axi_ad9625_jesd/rx_core_clk
+ad_connect  util_fmcomms11_gt/rx_ip_rst axi_ad9625_jesd/rx_reset
+ad_connect  util_fmcomms11_gt/rx_ip_rst_done axi_ad9625_jesd/rx_reset_done
+ad_connect  util_fmcomms11_gt/rx_ip_sysref axi_ad9625_jesd/rx_sysref
+ad_connect  util_fmcomms11_gt/rx_ip_sync axi_ad9625_jesd/rx_sync
+ad_connect  util_fmcomms11_gt/rx_ip_sof axi_ad9625_jesd/rx_start_of_frame
+ad_connect  util_fmcomms11_gt/rx_ip_data axi_ad9625_jesd/rx_tdata
+ad_connect  util_fmcomms11_gt/rx_out_clk axi_ad9625_core/rx_clk
+ad_connect  util_fmcomms11_gt/rx_data axi_ad9625_core/rx_data
+ad_connect  axi_ad9625_core/adc_raddr_in GND
+ad_connect  axi_ad9625_core/adc_dunf GND
+ad_connect  util_fmcomms11_gt/rx_out_clk axi_ad9625_fifo/adc_clk
+ad_connect  util_fmcomms11_gt/rx_rst axi_ad9625_fifo/adc_rst
+ad_connect  axi_ad9625_core/adc_valid axi_ad9625_fifo/adc_wr
+ad_connect  axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
+ad_connect  sys_cpu_clk axi_ad9625_fifo/dma_clk
+ad_connect  sys_cpu_clk axi_ad9625_dma/s_axis_aclk
+ad_connect  sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
+ad_connect  axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
+ad_connect  axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
+ad_connect  axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
+ad_connect  axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
+ad_connect  axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_daq2_gt
+ad_cpu_interconnect 0x44A60000 axi_fmcomms11_gt
 ad_cpu_interconnect 0x44A00000 axi_ad9144_core
 ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
-ad_cpu_interconnect 0x44A10000 axi_ad9680_core
-ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
-ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
+ad_cpu_interconnect 0x44A10000 axi_ad9625_core
+ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd
+ad_cpu_interconnect 0x7c400000 axi_ad9625_dma
 
 # gt uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_daq2_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_fmcomms11_gt/m_axi
 
 # interconnect (mem/dac)
 
 ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
 ad_mem_hp1_interconnect sys_cpu_clk axi_ad9144_dma/m_src_axi
 ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
-ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
+ad_mem_hp2_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
 
 # interrupts
 
-ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
-ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
+ad_cpu_interrupt ps-12 mb-12 axi_ad9144_dma/irq
+ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
 
 ad_connect  axi_ad9144_core/dac_ddata_2 GND
 ad_connect  axi_ad9144_core/dac_ddata_3 GND
diff --git a/projects/fmcomms11/common/fmcomms11_spi.v b/projects/fmcomms11/common/fmcomms11_spi.v
index 546948627..0a154cfd5 100644
--- a/projects/fmcomms11/common/fmcomms11_spi.v
+++ b/projects/fmcomms11/common/fmcomms11_spi.v
@@ -39,25 +39,23 @@
 
 module fmcomms11_spi (
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
-
-  spi_sdio,
-  spi_dir);
-
   // 4 wire
 
-  input   [ 2:0]  spi_csn;
-  input           spi_clk;
-  input           spi_mosi;
-  output          spi_miso;
+  input   [ 2:0]  spi_csn,
+  input           spi_clk,
+  input           spi_mosi,
+  output          spi_miso,
 
   // 3 wire
 
-  inout           spi_sdio;
-  output          spi_dir;
+  output          spi_csn_ad9625,
+  output          spi_csn_ad9162,
+  output          spi_csn_ad9508,
+  output          spi_csn_adl5240,
+  output          spi_csn_adf4355,
+  output          spi_csn_hmc1119,
+  inout           spi_sdio,
+  output          spi_dir);
 
   // internal registers
 
@@ -67,12 +65,27 @@ module fmcomms11_spi (
 
   // internal signals
 
+  wire    [ 5:0]  spi_csn6_s;
   wire            spi_csn_s;
   wire            spi_enable_s;
 
   // check on rising edge and change on falling edge
 
-  assign spi_csn_s = & spi_csn;
+  assign spi_csn_ad9625 = spi_csn6_s[0];
+  assign spi_csn_ad9162 = spi_csn6_s[1];
+  assign spi_csn_ad9508 = spi_csn6_s[2];
+  assign spi_csn_adl5240 = spi_csn6_s[3];
+  assign spi_csn_adf4355 = spi_csn6_s[4];
+  assign spi_csn_hmc1119 = spi_csn6_s[5];
+
+  assign spi_csn6_s[0] = (spi_csn == 3'b001) ? 1'b0 : 1'b1;
+  assign spi_csn6_s[1] = (spi_csn == 3'b010) ? 1'b0 : 1'b1;
+  assign spi_csn6_s[2] = (spi_csn == 3'b011) ? 1'b0 : 1'b1;
+  assign spi_csn6_s[3] = (spi_csn == 3'b100) ? 1'b0 : 1'b1;
+  assign spi_csn6_s[4] = (spi_csn == 3'b101) ? 1'b0 : 1'b1;
+  assign spi_csn6_s[5] = (spi_csn == 3'b110) ? 1'b0 : 1'b1;
+
+  assign spi_csn_s = & spi_csn6_s;
   assign spi_dir = ~spi_enable_s;
   assign spi_enable_s = spi_enable & ~spi_csn_s;
 
@@ -98,7 +111,7 @@ module fmcomms11_spi (
     end
   end
 
-  // io butter
+  // io buffer
 
   assign spi_miso = spi_sdio;
   assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;

From 1746701d45e5f38221f7b3b3f23219abc80fbd5d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 10 Jun 2016 14:20:28 -0400
Subject: [PATCH 274/972] fmcomms11- updates

---
 projects/fmcomms11/zc706/system_bd.tcl      |  14 +-
 projects/fmcomms11/zc706/system_constr.xdc  | 113 ++++---
 projects/fmcomms11/zc706/system_project.tcl |  11 +-
 projects/fmcomms11/zc706/system_top.v       | 328 +++++++-------------
 4 files changed, 183 insertions(+), 283 deletions(-)

diff --git a/projects/fmcomms11/zc706/system_bd.tcl b/projects/fmcomms11/zc706/system_bd.tcl
index 44e72997e..887ffb2d0 100644
--- a/projects/fmcomms11/zc706/system_bd.tcl
+++ b/projects/fmcomms11/zc706/system_bd.tcl
@@ -4,7 +4,7 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
 
 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
-p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 128
 
 create_bd_port -dir I -type rst sys_rst
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
@@ -12,14 +12,14 @@ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sy
 
 set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
 
-ad_connect  sys_rst axi_ad9680_fifo/sys_rst
-ad_connect  sys_clk axi_ad9680_fifo/sys_clk
-ad_connect  ddr3 axi_ad9680_fifo/ddr3
+ad_connect  sys_rst axi_ad9625_fifo/sys_rst
+ad_connect  sys_clk axi_ad9625_fifo/sys_clk
+ad_connect  ddr3 axi_ad9625_fifo/ddr3
 
 create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
-  [get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
-  [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
+  [get_bd_addr_spaces axi_ad9625_fifo/axi_adcfifo/axi] \
+  [get_bd_addr_segs axi_ad9625_fifo/axi_ddr_cntrl/memmap/memaddr] \
   SEG_axi_ddr_cntrl_memaddr
 
-source ../common/daq2_bd.tcl
+source ../common/fmcomms11_bd.tcl
 
diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc
index df68021e6..8bc2535be 100644
--- a/projects/fmcomms11/zc706/system_constr.xdc
+++ b/projects/fmcomms11/zc706/system_constr.xdc
@@ -1,61 +1,72 @@
 
-# daq2
+# fmcomms11
 
-set_property  -dict {PACKAGE_PIN  AA8 } [get_ports rx_ref_clk_p]                                      ; ## B20  FMC_HPC_GBTCLK1_M2C_P
-set_property  -dict {PACKAGE_PIN  AA7 } [get_ports rx_ref_clk_n]                                      ; ## B21  FMC_HPC_GBTCLK1_M2C_N
-set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[0]]                                      ; ## A10  FMC_HPC_DP3_M2C_P
-set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[0]]                                      ; ## A11  FMC_HPC_DP3_M2C_N
-set_property  -dict {PACKAGE_PIN  AH10} [get_ports rx_data_p[1]]                                      ; ## C06  FMC_HPC_DP0_M2C_P
-set_property  -dict {PACKAGE_PIN  AH9 } [get_ports rx_data_n[1]]                                      ; ## C07  FMC_HPC_DP0_M2C_N
-set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[2]]                                      ; ## A06  FMC_HPC_DP2_M2C_P
-set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[2]]                                      ; ## A07  FMC_HPC_DP2_M2C_N
-set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[3]]                                      ; ## A02  FMC_HPC_DP1_M2C_P
-set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[3]]                                      ; ## A03  FMC_HPC_DP1_M2C_N
-set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## D08  FMC_HPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## D09  FMC_HPC_LA01_CC_N
-set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]    ; ## G09  FMC_HPC_LA03_P
-set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]    ; ## G10  FMC_HPC_LA03_N
+set_property  -dict {PACKAGE_PIN  AA8 } [get_ports rx_ref_clk_p]                                      ; ## B20  FMC_HPC_GBTCLK1_M2C_P   
+set_property  -dict {PACKAGE_PIN  AA7 } [get_ports rx_ref_clk_n]                                      ; ## B21  FMC_HPC_GBTCLK1_M2C_N   
+set_property  -dict {PACKAGE_PIN  AH10} [get_ports rx_data_p[0]]                                      ; ## C06  FMC_HPC_DP0_M2C_P       
+set_property  -dict {PACKAGE_PIN  AH9 } [get_ports rx_data_n[0]]                                      ; ## C07  FMC_HPC_DP0_M2C_N       
+set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[1]]                                      ; ## A02  FMC_HPC_DP1_M2C_P       
+set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[1]]                                      ; ## A03  FMC_HPC_DP1_M2C_N       
+set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[2]]                                      ; ## A06  FMC_HPC_DP2_M2C_P       
+set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[2]]                                      ; ## A07  FMC_HPC_DP2_M2C_N       
+set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[3]]                                      ; ## A10  FMC_HPC_DP3_M2C_P       
+set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[3]]                                      ; ## A11  FMC_HPC_DP3_M2C_N       
+set_property  -dict {PACKAGE_PIN  AD6 } [get_ports rx_data_p[4]]                                      ; ## B12  FMC_HPC_DP7_M2C_P       
+set_property  -dict {PACKAGE_PIN  AD5 } [get_ports rx_data_n[4]]                                      ; ## B13  FMC_HPC_DP7_M2C_N       
+set_property  -dict {PACKAGE_PIN  AH6 } [get_ports rx_data_p[5]]                                      ; ## A14  FMC_HPC_DP4_M2C_P       
+set_property  -dict {PACKAGE_PIN  AH5 } [get_ports rx_data_n[5]]                                      ; ## A15  FMC_HPC_DP4_M2C_N       
+set_property  -dict {PACKAGE_PIN  AF6 } [get_ports rx_data_p[6]]                                      ; ## B16  FMC_HPC_DP6_M2C_P       
+set_property  -dict {PACKAGE_PIN  AF5 } [get_ports rx_data_n[6]]                                      ; ## B17  FMC_HPC_DP6_M2C_N       
+set_property  -dict {PACKAGE_PIN  AG4 } [get_ports rx_data_p[7]]                                      ; ## A18  FMC_HPC_DP5_M2C_P       
+set_property  -dict {PACKAGE_PIN  AG3 } [get_ports rx_data_n[7]]                                      ; ## A19  FMC_HPC_DP5_M2C_N       
+set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## H07  FMC_HPC_LA02_P          
+set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## H08  FMC_HPC_LA02_N          
 
-set_property  -dict {PACKAGE_PIN  AD10} [get_ports tx_ref_clk_p]                                      ; ## D04  FMC_HPC_GBTCLK0_M2C_P
-set_property  -dict {PACKAGE_PIN  AD9 } [get_ports tx_ref_clk_n]                                      ; ## D05  FMC_HPC_GBTCLK0_M2C_N
-set_property  -dict {PACKAGE_PIN  AK2 } [get_ports tx_data_p[0]]                                      ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[0])
-set_property  -dict {PACKAGE_PIN  AK1 } [get_ports tx_data_n[0]]                                      ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[0])
-set_property  -dict {PACKAGE_PIN  AK10} [get_ports tx_data_p[1]]                                      ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[3])
-set_property  -dict {PACKAGE_PIN  AK9 } [get_ports tx_data_n[1]]                                      ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[3])
-set_property  -dict {PACKAGE_PIN  AJ4 } [get_ports tx_data_p[2]]                                      ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[1])
-set_property  -dict {PACKAGE_PIN  AJ3 } [get_ports tx_data_n[2]]                                      ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[1])
-set_property  -dict {PACKAGE_PIN  AK6 } [get_ports tx_data_p[3]]                                      ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
-set_property  -dict {PACKAGE_PIN  AK5 } [get_ports tx_data_n[3]]                                      ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
-set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p]      ; ## H07  FMC_HPC_LA02_P
-set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n]      ; ## H08  FMC_HPC_LA02_N
-set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p]    ; ## H10  FMC_HPC_LA04_P
-set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n]    ; ## H11  FMC_HPC_LA04_N
+set_property  -dict {PACKAGE_PIN  AD10} [get_ports tx_ref_clk_p]                                      ; ## D04  FMC_HPC_GBTCLK0_M2C_P   
+set_property  -dict {PACKAGE_PIN  AD9 } [get_ports tx_ref_clk_n]                                      ; ## D05  FMC_HPC_GBTCLK0_M2C_N   
+set_property  -dict {PACKAGE_PIN  AK10} [get_ports tx_data_p[0]]                                      ; ## C02  FMC_HPC_DP0_C2M_P       
+set_property  -dict {PACKAGE_PIN  AK9 } [get_ports tx_data_n[0]]                                      ; ## C03  FMC_HPC_DP0_C2M_N       
+set_property  -dict {PACKAGE_PIN  AK6 } [get_ports tx_data_p[1]]                                      ; ## A22  FMC_HPC_DP1_C2M_P       
+set_property  -dict {PACKAGE_PIN  AK5 } [get_ports tx_data_n[1]]                                      ; ## A23  FMC_HPC_DP1_C2M_N       
+set_property  -dict {PACKAGE_PIN  AJ4 } [get_ports tx_data_p[2]]                                      ; ## A26  FMC_HPC_DP2_C2M_P       
+set_property  -dict {PACKAGE_PIN  AJ3 } [get_ports tx_data_n[2]]                                      ; ## A27  FMC_HPC_DP2_C2M_N       
+set_property  -dict {PACKAGE_PIN  AK2 } [get_ports tx_data_p[3]]                                      ; ## A30  FMC_HPC_DP3_C2M_P       
+set_property  -dict {PACKAGE_PIN  AK1 } [get_ports tx_data_n[3]]                                      ; ## A31  FMC_HPC_DP3_C2M_N       
+set_property  -dict {PACKAGE_PIN  AD2 } [get_ports tx_data_p[4]]                                      ; ## B32  FMC_HPC_DP7_C2M_P       
+set_property  -dict {PACKAGE_PIN  AD1 } [get_ports tx_data_n[4]]                                      ; ## B33  FMC_HPC_DP7_C2M_N       
+set_property  -dict {PACKAGE_PIN  AH2 } [get_ports tx_data_p[5]]                                      ; ## A34  FMC_HPC_DP4_C2M_P       
+set_property  -dict {PACKAGE_PIN  AH1 } [get_ports tx_data_n[5]]                                      ; ## A35  FMC_HPC_DP4_C2M_N       
+set_property  -dict {PACKAGE_PIN  AE4 } [get_ports tx_data_p[6]]                                      ; ## B36  FMC_HPC_DP6_C2M_P       
+set_property  -dict {PACKAGE_PIN  AE3 } [get_ports tx_data_n[6]]                                      ; ## B37  FMC_HPC_DP6_C2M_N       
+set_property  -dict {PACKAGE_PIN  AF2 } [get_ports tx_data_p[7]]                                      ; ## A38  FMC_HPC_DP5_C2M_P       
+set_property  -dict {PACKAGE_PIN  AF1 } [get_ports tx_data_n[7]]                                      ; ## A39  FMC_HPC_DP5_C2M_N       
+set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p]      ; ## G09  FMC_HPC_LA03_P          
+set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n]      ; ## G10  FMC_HPC_LA03_N          
 
-set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVCMOS25} [get_ports spi_csn_clk]                  ; ## D11  FMC_HPC_LA05_P
-set_property  -dict {PACKAGE_PIN  AG24  IOSTANDARD LVCMOS25} [get_ports spi_csn_dac]                  ; ## C14  FMC_HPC_LA10_P
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports spi_csn_adc]                  ; ## D15  FMC_HPC_LA09_N
-set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## D12  FMC_HPC_LA05_N
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS25} [get_ports spi_sdio]                     ; ## D14  FMC_HPC_LA09_P
-set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVCMOS25} [get_ports spi_dir]                      ; ## G13  FMC_HPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_p]      ; ## G06  FMC_HPC_LA00_CC_P       
+set_property  -dict {PACKAGE_PIN  AG20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_n]      ; ## G07  FMC_HPC_LA00_CC_N       
+set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p]       ; ## H10  FMC_HPC_LA04_P          
+set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n]       ; ## H11  FMC_HPC_LA04_N          
 
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports clkd_sync]                    ; ## G12  FMC_HPC_LA08_P
-set_property  -dict {PACKAGE_PIN  AG25  IOSTANDARD LVCMOS25} [get_ports dac_reset]                    ; ## C15  FMC_HPC_LA10_N
-set_property  -dict {PACKAGE_PIN  AF24  IOSTANDARD LVCMOS25} [get_ports dac_txen]                     ; ## G16  FMC_HPC_LA12_N
-set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports adc_pd]                       ; ## C10  FMC_HPC_LA06_P
+set_property  -dict {PACKAGE_PIN  AH22  IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9625]               ; ## C11  FMC_HPC_LA06_N          
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9162]               ; ## G12  FMC_HPC_LA08_P          
+set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9508]               ; ## H14  FMC_HPC_LA07_N          
+set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports spi_csn_adl5240]              ; ## C10  FMC_HPC_LA06_P          
+set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports spi_csn_adf4355]              ; ## D12  FMC_HPC_LA05_N          
+set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVCMOS25} [get_ports spi_csn_hmc1119]              ; ## D11  FMC_HPC_LA05_P          
+set_property  -dict {PACKAGE_PIN  AG24  IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## C14  FMC_HPC_LA10_P          
+set_property  -dict {PACKAGE_PIN  AG25  IOSTANDARD LVCMOS25} [get_ports spi_sdio]                     ; ## C15  FMC_HPC_LA10_N          
+set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVCMOS25} [get_ports spi_dir]                      ; ## H13  FMC_HPC_LA07_P          
 
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports clkd_status[0]]               ; ## D17  FMC_HPC_LA13_P
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports clkd_status[1]]               ; ## D18  FMC_HPC_LA13_N
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports dac_irq]                      ; ## G15  FMC_HPC_LA12_P
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports adc_fda]                      ; ## H16  FMC_HPC_LA11_P
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports adc_fdb]                      ; ## H17  FMC_HPC_LA11_N
-
-set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p]         ; ## H13  FMC_HPC_LA07_P
-set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n]         ; ## H14  FMC_HPC_LA07_N
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS25} [get_ports adf4355_muxout]               ; ## D14  FMC_HPC_LA09_P             
+set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVCMOS25} [get_ports ad9162_txen]                  ; ## G13  FMC_HPC_LA08_N             
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports ad9625_irq]                   ; ## D15  FMC_HPC_LA09_N             
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports ad9162_irq]                   ; ## H16  FMC_HPC_LA11_P             
 
 # clocks
 
-create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
-create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_ref_clk   -period  1.60 [get_ports tx_ref_clk_p]
+create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
+create_clock -name tx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_fmcomms11_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_fmcomms11_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
 
diff --git a/projects/fmcomms11/zc706/system_project.tcl b/projects/fmcomms11/zc706/system_project.tcl
index 8d6209938..f9b1c39a7 100644
--- a/projects/fmcomms11/zc706/system_project.tcl
+++ b/projects/fmcomms11/zc706/system_project.tcl
@@ -5,18 +5,15 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create daq2_zc706
-adi_project_files daq2_zc706 [list \
-  "../common/daq2_spi.v" \
+adi_project_create fmcomms11_zc706
+adi_project_files fmcomms11_zc706 [list \
+  "../common/fmcomms11_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run daq2_zc706
+adi_project_run fmcomms11_zc706
 
 
diff --git a/projects/fmcomms11/zc706/system_top.v b/projects/fmcomms11/zc706/system_top.v
index 071300f3a..c124326ad 100644
--- a/projects/fmcomms11/zc706/system_top.v
+++ b/projects/fmcomms11/zc706/system_top.v
@@ -34,200 +34,100 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  gpio_bd,
+  inout   [14:0]  gpio_bd,
 
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
+  output          hdmi_out_clk,
+  output          hdmi_vsync,
+  output          hdmi_hsync,
+  output          hdmi_data_e,
+  output  [23:0]  hdmi_data,
 
-  spdif,
+  output          spdif,
 
-  sys_rst,
-  sys_clk_p,
-  sys_clk_n,
+  input           sys_rst,
+  input           sys_clk_p,
+  input           sys_clk_n,
 
-  ddr3_addr,
-  ddr3_ba,
-  ddr3_cas_n,
-  ddr3_ck_n,
-  ddr3_ck_p,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_dm,
-  ddr3_dq,
-  ddr3_dqs_n,
-  ddr3_dqs_p,
-  ddr3_odt,
-  ddr3_ras_n,
-  ddr3_reset_n,
-  ddr3_we_n,
+  output  [13:0]  ddr3_addr,
+  output  [ 2:0]  ddr3_ba,
+  output          ddr3_cas_n,
+  output  [ 0:0]  ddr3_ck_n,
+  output  [ 0:0]  ddr3_ck_p,
+  output  [ 0:0]  ddr3_cke,
+  output  [ 0:0]  ddr3_cs_n,
+  output  [ 7:0]  ddr3_dm,
+  inout   [63:0]  ddr3_dq,
+  inout   [ 7:0]  ddr3_dqs_n,
+  inout   [ 7:0]  ddr3_dqs_p,
+  output  [ 0:0]  ddr3_odt,
+  output          ddr3_ras_n,
+  output          ddr3_reset_n,
+  output          ddr3_we_n,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  rx_ref_clk_p,
-  rx_ref_clk_n,
-  rx_sysref_p,
-  rx_sysref_n,
-  rx_sync_p,
-  rx_sync_n,
-  rx_data_p,
-  rx_data_n,
+  input           rx_ref_clk_p,
+  input           rx_ref_clk_n,
+  output          rx_sync_p,
+  output          rx_sync_n,
+  input   [ 7:0]  rx_data_p,
+  input   [ 7:0]  rx_data_n,
 
-  tx_ref_clk_p,
-  tx_ref_clk_n,
-  tx_sysref_p,
-  tx_sysref_n,
-  tx_sync_p,
-  tx_sync_n,
-  tx_data_p,
-  tx_data_n,
+  input           tx_ref_clk_p,
+  input           tx_ref_clk_n,
+  input           tx_sync_p,
+  input           tx_sync_n,
+  output  [ 7:0]  tx_data_p,
+  output  [ 7:0]  tx_data_n,
 
-  trig_p,
-  trig_n,
+  input           sysref_p,
+  input           sysref_n,
+  input           usr_clk_p,
+  input           usr_clk_n,
 
-  adc_fdb,
-  adc_fda,
-  dac_irq,
-  clkd_status,
+  inout           adf4355_muxout,
+  inout           ad9162_txen,
+  inout           ad9625_irq,
+  inout           ad9162_irq,
 
-  adc_pd,
-  dac_txen,
-  dac_reset,
-  clkd_sync,
-
-  spi_csn_clk,
-  spi_csn_dac,
-  spi_csn_adc,
-  spi_clk,
-  spi_sdio,
-  spi_dir);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout   [14:0]  gpio_bd;
-
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [23:0]  hdmi_data;
-
-  output          spdif;
-
-  input           sys_rst;
-  input           sys_clk_p;
-  input           sys_clk_n;
-
-  output  [13:0]  ddr3_addr;
-  output  [ 2:0]  ddr3_ba;
-  output          ddr3_cas_n;
-  output  [ 0:0]  ddr3_ck_n;
-  output  [ 0:0]  ddr3_ck_p;
-  output  [ 0:0]  ddr3_cke;
-  output  [ 0:0]  ddr3_cs_n;
-  output  [ 7:0]  ddr3_dm;
-  inout   [63:0]  ddr3_dq;
-  inout   [ 7:0]  ddr3_dqs_n;
-  inout   [ 7:0]  ddr3_dqs_p;
-  output  [ 0:0]  ddr3_odt;
-  output          ddr3_ras_n;
-  output          ddr3_reset_n;
-  output          ddr3_we_n;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  input           rx_ref_clk_p;
-  input           rx_ref_clk_n;
-  input           rx_sysref_p;
-  input           rx_sysref_n;
-  output          rx_sync_p;
-  output          rx_sync_n;
-  input   [ 3:0]  rx_data_p;
-  input   [ 3:0]  rx_data_n;
-
-  input           tx_ref_clk_p;
-  input           tx_ref_clk_n;
-  input           tx_sysref_p;
-  input           tx_sysref_n;
-  input           tx_sync_p;
-  input           tx_sync_n;
-  output  [ 3:0]  tx_data_p;
-  output  [ 3:0]  tx_data_n;
-
-  input           trig_p;
-  input           trig_n;
-
-  inout           adc_fdb;
-  inout           adc_fda;
-  inout           dac_irq;
-  inout   [ 1:0]  clkd_status;
-
-  inout           adc_pd;
-  inout           dac_txen;
-  inout           dac_reset;
-  inout           clkd_sync;
-
-  output          spi_csn_clk;
-  output          spi_csn_dac;
-  output          spi_csn_adc;
-  output          spi_clk;
-  inout           spi_sdio;
-  output          spi_dir;
+  output          spi_csn_ad9625,
+  output          spi_csn_ad9162,
+  output          spi_csn_ad9508,
+  output          spi_csn_adl5240,
+  output          spi_csn_adf4355,
+  output          spi_csn_hmc1119,
+  output          spi_clk,
+  inout           spi_sdio,
+  output          spi_dir);
 
   // internal signals
 
@@ -242,19 +142,12 @@ module system_top (
   wire            spi1_clk;
   wire            spi1_mosi;
   wire            spi1_miso;
-  wire            trig;
   wire            rx_ref_clk;
-  wire            rx_sysref;
   wire            rx_sync;
   wire            tx_ref_clk;
-  wire            tx_sysref;
   wire            tx_sync;
-
-  // spi
-
-  assign spi_csn_adc = spi0_csn[2];
-  assign spi_csn_dac = spi0_csn[1];
-  assign spi_csn_clk = spi0_csn[0];
+  wire            sysref;
+  wire            usr_clk;
 
   // instantiations
 
@@ -265,11 +158,6 @@ module system_top (
     .O (rx_ref_clk),
     .ODIV2 ());
 
-  IBUFDS i_ibufds_rx_sysref (
-    .I (rx_sysref_p),
-    .IB (rx_sysref_n),
-    .O (rx_sysref));
-
   OBUFDS i_obufds_rx_sync (
     .I (rx_sync),
     .O (rx_sync_p),
@@ -282,44 +170,49 @@ module system_top (
     .O (tx_ref_clk),
     .ODIV2 ());
 
-  IBUFDS i_ibufds_tx_sysref (
-    .I (tx_sysref_p),
-    .IB (tx_sysref_n),
-    .O (tx_sysref));
-
   IBUFDS i_ibufds_tx_sync (
     .I (tx_sync_p),
     .IB (tx_sync_n),
     .O (tx_sync));
 
-  daq2_spi i_spi (
+  IBUFDS i_ibufds_sysref (
+    .I (sysref_p),
+    .IB (sysref_n),
+    .O (sysref));
+
+  IBUFDS i_ibufds_usr_clk (
+    .I (usr_clk_p),
+    .IB (usr_clk_n),
+    .O (usr_clk));
+
+  fmcomms11_spi i_spi (
     .spi_csn (spi0_csn),
     .spi_clk (spi_clk),
     .spi_mosi (spi0_mosi),
     .spi_miso (spi0_miso),
+    .spi_csn_ad9625 (spi_csn_ad9625),
+    .spi_csn_ad9162 (spi_csn_ad9162),
+    .spi_csn_ad9508 (spi_csn_ad9508),
+    .spi_csn_adl5240 (spi_csn_adl5240),
+    .spi_csn_adf4355 (spi_csn_adf4355),
+    .spi_csn_hmc1119 (spi_csn_hmc1119),
     .spi_sdio (spi_sdio),
     .spi_dir (spi_dir));
 
-  IBUFDS i_ibufds_trig (
-    .I (trig_p),
-    .IB (trig_n),
-    .O (trig));
-
-  assign gpio_i[43] = trig;
   assign spi_clk = spi0_clk;
 
-  ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
-    .dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
-    .dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
-    .dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
-    .dio_p ({ adc_pd,           // 42
-              dac_txen,         // 41
-              dac_reset,        // 40
-              clkd_sync,        // 38
-              adc_fdb,          // 36
-              adc_fda,          // 35
-              dac_irq,          // 34
-              clkd_status}));   // 32
+  assign gpio_i[63:36] = gpio_o[63:36];
+
+  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf (
+    .dio_t ({gpio_t[35:32]}),
+    .dio_i ({gpio_o[35:32]}),
+    .dio_o ({gpio_i[35:32]}),
+    .dio_p ({ adf4355_muxout,   // 35
+              ad9162_txen,      // 34
+              ad9625_irq,       // 33
+              ad9162_irq}));    // 32
+
+  assign gpio_i[31:15] = gpio_o[31:15];
 
   ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
     .dio_t (gpio_t[14:0]),
@@ -390,7 +283,6 @@ module system_top (
     .rx_data_p (rx_data_p),
     .rx_ref_clk (rx_ref_clk),
     .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),
@@ -413,11 +305,11 @@ module system_top (
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
+    .sysref (sysref),
     .tx_data_n (tx_data_n),
     .tx_data_p (tx_data_p),
     .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref));
+    .tx_sync (tx_sync));
 
 endmodule
 

From eaf4d4a19d89b78e86fa122d7c6a5ff3e23567d0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 10 Jun 2016 14:26:14 -0400
Subject: [PATCH 275/972] makefile updates

---
 projects/Makefile                   |  3 +++
 projects/adrv9371x/a10soc/Makefile  |  2 ++
 projects/arradio/c5soc/Makefile     |  2 ++
 projects/common/a5gte/Makefile      |  2 ++
 projects/daq2/a10gx/Makefile        |  4 +++-
 projects/daq3/a10gx/Makefile        |  3 ++-
 projects/fmcjesdadc1/a5gt/Makefile  |  2 ++
 projects/fmcjesdadc1/a5soc/Makefile |  2 ++
 projects/fmcomms1/Makefile          |  3 +++
 projects/fmcomms11/zc706/Makefile   | 22 ++++++++--------------
 projects/fmcomms2/a10soc/Makefile   |  2 ++
 projects/usdrx1/a5gt/Makefile       |  2 ++
 12 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/projects/Makefile b/projects/Makefile
index ee568616a..0a7d71849 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -28,6 +28,7 @@ all:
 	-make -C fmcadc5 all
 	-make -C fmcjesdadc1 all
 	-make -C fmcomms1 all
+	-make -C fmcomms11 all
 	-make -C fmcomms2 all
 	-make -C fmcomms5 all
 	-make -C fmcomms6 all
@@ -62,6 +63,7 @@ clean:
 	make -C fmcadc5 clean
 	make -C fmcjesdadc1 clean
 	make -C fmcomms1 clean
+	make -C fmcomms11 clean
 	make -C fmcomms2 clean
 	make -C fmcomms5 clean
 	make -C fmcomms6 clean
@@ -96,6 +98,7 @@ clean-all:
 	make -C fmcadc5 clean-all
 	make -C fmcjesdadc1 clean-all
 	make -C fmcomms1 clean-all
+	make -C fmcomms11 clean-all
 	make -C fmcomms2 clean-all
 	make -C fmcomms5 clean-all
 	make -C fmcomms6 clean-all
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index a58ec1db3..e3a6e61e3 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -109,6 +109,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index d9de7293b..3275b8b8b 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -125,6 +125,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 
diff --git a/projects/common/a5gte/Makefile b/projects/common/a5gte/Makefile
index 7b79c11f7..c15cb453a 100644
--- a/projects/common/a5gte/Makefile
+++ b/projects/common/a5gte/Makefile
@@ -41,6 +41,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index 38bbd6d29..cf18f1a8c 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -6,9 +6,9 @@
 ####################################################################################
 
 M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
-M_DEPS += system_qsys.tcl
 M_DEPS += ../common/daq2_spi.v
 M_DEPS += ../common/daq2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
@@ -116,6 +116,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index f5526e19e..9d7568db8 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -12,7 +12,6 @@ M_DEPS += system_bd.qsys
 M_DEPS += ../common/daq3_spi.v
 M_DEPS += ../common/daq3_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
@@ -115,6 +114,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 
diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index ef4b1eefb..7f0b6b3b3 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -98,6 +98,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index d40337cda..9399511e1 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -98,6 +98,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 
diff --git a/projects/fmcomms1/Makefile b/projects/fmcomms1/Makefile
index 82b83fb73..d79fd3853 100644
--- a/projects/fmcomms1/Makefile
+++ b/projects/fmcomms1/Makefile
@@ -13,6 +13,7 @@ all:
 	-make -C zc702 all
 	-make -C zc706 all
 	-make -C zed all
+	-make -C zc706 all
 
 
 clean: 
@@ -22,6 +23,7 @@ clean:
 	make -C zc702 clean
 	make -C zc706 clean
 	make -C zed clean
+	make -C zc706 clean
 
 
 clean-all:
@@ -31,6 +33,7 @@ clean-all:
 	make -C zc702 clean-all
 	make -C zc706 clean-all
 	make -C zed clean-all
+	make -C zc706 clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index ec2fa7313..c9331f515 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -9,8 +9,8 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
-M_DEPS += ../common/daq2_spi.v
-M_DEPS += ../common/daq2_bd.tcl
+M_DEPS += ../common/fmcomms11_spi.v
+M_DEPS += ../common/fmcomms11_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
@@ -22,7 +22,7 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
-M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
+M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -30,10 +30,8 @@ M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
-M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -53,7 +51,7 @@ M_FLIST += .Xil
 
 
 .PHONY: all lib clean clean-all
-all: lib daq2_zc706.sdk/system_top.hdf
+all: lib fmcomms11_zc706.sdk/system_top.hdf
 
 
 clean: 
@@ -62,7 +60,7 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
-	make -C ../../../library/axi_ad9680 clean
+	make -C ../../../library/axi_ad9625 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
@@ -70,20 +68,18 @@ clean-all:clean
 	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/util_adcfifo clean
-	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_jesd_gt clean
-	make -C ../../../library/util_upack clean
 
 
-daq2_zc706.sdk/system_top.hdf: $(M_DEPS)
+fmcomms11_zc706.sdk/system_top.hdf: $(M_DEPS)
 	rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> daq2_zc706_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> fmcomms11_zc706_vivado.log 2>&1
 
 
 lib:
 	make -C ../../../library/axi_ad9144
-	make -C ../../../library/axi_ad9680
+	make -C ../../../library/axi_ad9625
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
@@ -91,10 +87,8 @@ lib:
 	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/util_adcfifo
-	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_jesd_gt
-	make -C ../../../library/util_upack
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcomms2/a10soc/Makefile b/projects/fmcomms2/a10soc/Makefile
index ed286a1c4..5ad3076bd 100644
--- a/projects/fmcomms2/a10soc/Makefile
+++ b/projects/fmcomms2/a10soc/Makefile
@@ -119,6 +119,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index d461204bb..53d4949eb 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -44,6 +44,8 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
 
 
 

From 8f48a5520a35f542c0339c3bdab8d7c7acb1ff66 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 10 Jun 2016 14:26:46 -0400
Subject: [PATCH 276/972] makefile updates

---
 projects/fmcomms11/Makefile | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 projects/fmcomms11/Makefile

diff --git a/projects/fmcomms11/Makefile b/projects/fmcomms11/Makefile
new file mode 100644
index 000000000..5b866a1ac
--- /dev/null
+++ b/projects/fmcomms11/Makefile
@@ -0,0 +1,21 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+.PHONY: all clean clean-all 
+all:
+	-make -C zc706 all
+
+
+clean: 
+	make -C zc706 clean
+
+
+clean-all:
+	make -C zc706 clean-all
+
+####################################################################################
+####################################################################################

From 83dd7e91c4bff4e8ca0d14156ca790447e8ba4ef Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 9 Jun 2016 17:55:52 -0400
Subject: [PATCH 277/972] deleted pn23 and pn 31, data width yet to be modified

---
 library/axi_ad9144/axi_ad9144_channel.v | 439 ++++++++----------------
 1 file changed, 148 insertions(+), 291 deletions(-)

diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v
index d079f0707..37833974b 100644
--- a/library/axi_ad9144/axi_ad9144_channel.v
+++ b/library/axi_ad9144/axi_ad9144_channel.v
@@ -104,8 +104,8 @@ module axi_ad9144_channel (
   reg     [63:0]  dac_data = 'd0;
   reg     [63:0]  dac_pn7_data = 'd0;
   reg     [63:0]  dac_pn15_data = 'd0;
-  reg     [63:0]  dac_pn23_data = 'd0;
-  reg     [63:0]  dac_pn31_data = 'd0;
+ // reg     [63:0]  dac_pn23_data = 'd0;
+ // reg     [63:0]  dac_pn31_data = 'd0;
   reg     [15:0]  dac_dds_phase_0_0 = 'd0;
   reg     [15:0]  dac_dds_phase_0_1 = 'd0;
   reg     [15:0]  dac_dds_phase_1_0 = 'd0;
@@ -134,309 +134,162 @@ module axi_ad9144_channel (
   wire    [15:0]  dac_pat_data_2_s;
   wire    [ 3:0]  dac_data_sel_s;
 
-  // pn7 function
+   // PN7 function
 
   function [63:0] pn7;
-    input [63:0] din;
+    input [7:0] din;
     reg   [63:0] dout;
     begin
-      dout[63] = din[ 7] ^ din[ 6];
-      dout[62] = din[ 6] ^ din[ 5];
-      dout[61] = din[ 5] ^ din[ 4];
-      dout[60] = din[ 4] ^ din[ 3];
-      dout[59] = din[ 3] ^ din[ 2];
-      dout[58] = din[ 2] ^ din[ 1];
-      dout[57] = din[ 1] ^ din[ 0];
-      dout[56] = din[ 0] ^ din[ 7] ^ din[ 6];
-      dout[55] = din[ 7] ^ din[ 5];
-      dout[54] = din[ 6] ^ din[ 4];
-      dout[53] = din[ 5] ^ din[ 3];
-      dout[52] = din[ 4] ^ din[ 2];
-      dout[51] = din[ 3] ^ din[ 1];
-      dout[50] = din[ 2] ^ din[ 0];
-      dout[49] = din[ 1] ^ din[ 7] ^ din[ 6];
-      dout[48] = din[ 0] ^ din[ 6] ^ din[ 5];
-      dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
-      dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
-      dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
-      dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
-      dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
-      dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6];
-      dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5];
-      dout[40] = din[ 0] ^ din[ 7] ^ din[ 4];
-      dout[39] = din[ 7] ^ din[ 3];
-      dout[38] = din[ 6] ^ din[ 2];
-      dout[37] = din[ 5] ^ din[ 1];
-      dout[36] = din[ 4] ^ din[ 0];
-      dout[35] = din[ 3] ^ din[ 7] ^ din[ 6];
-      dout[34] = din[ 2] ^ din[ 6] ^ din[ 5];
-      dout[33] = din[ 1] ^ din[ 5] ^ din[ 4];
-      dout[32] = din[ 0] ^ din[ 4] ^ din[ 3];
-      dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2];
-      dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
-      dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
-      dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6];
-      dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5];
-      dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4];
-      dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3];
-      dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
-      dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
-      dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
-      dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6];
-      dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
-      dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4];
-      dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3];
-      dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
-      dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1];
-      dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
-      dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7];
-      dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2];
-      dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1];
-      dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0];
-      dout[10] = din[ 0] ^ din[ 1] ^ din[ 7];
-      dout[ 9] = din[ 7] ^ din[ 0];
-      dout[ 8] = din[ 7];
-      dout[ 7] = din[ 6];
-      dout[ 6] = din[ 5];
-      dout[ 5] = din[ 4];
-      dout[ 4] = din[ 3];
-      dout[ 3] = din[ 2];
-      dout[ 2] = din[ 1];
-      dout[ 1] = din[ 0];
-      dout[ 0] = din[ 7] ^ din[ 6];
+      dout[63] = din[ 6] ^ din[ 5];
+      dout[62] = din[ 5] ^ din[ 4];
+      dout[61] = din[ 4] ^ din[ 3];
+      dout[60] = din[ 3] ^ din[ 2];
+      dout[59] = din[ 2] ^ din[ 1];
+      dout[58] = din[ 1] ^ din[ 0];
+      dout[57] = din[ 0] ^ din[ 6] ^ din[ 5];
+      dout[56] = din[ 6] ^ din[ 4];
+      dout[55] = din[ 5] ^ din[ 3];
+      dout[54] = din[ 4] ^ din[ 2];
+      dout[53] = din[ 3] ^ din[ 1];
+      dout[52] = din[ 2] ^ din[ 0];
+      dout[51] = din[ 1] ^ din[ 6] ^ din[ 5];
+      dout[50] = din[ 0] ^ din[ 5] ^ din[ 4];
+      dout[49] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
+      dout[48] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
+      dout[47] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
+      dout[46] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
+      dout[45] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
+      dout[44] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
+      dout[43] = din[ 0] ^ din[ 6] ^ din[ 3];
+      dout[42] = din[ 6] ^ din[ 2];
+      dout[41] = din[ 5] ^ din[ 1];
+      dout[40] = din[ 4] ^ din[ 0];
+      dout[39] = din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[38] = din[ 2] ^ din[ 5] ^ din[ 4];
+      dout[37] = din[ 1] ^ din[ 4] ^ din[ 3];
+      dout[36] = din[ 0] ^ din[ 3] ^ din[ 2];
+      dout[35] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
+      dout[34] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
+      dout[33] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[32] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
+      dout[31] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
+      dout[30] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
+      dout[29] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
+      dout[28] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
+      dout[27] = din[ 1] ^ din[ 3] ^ din[ 6];
+      dout[26] = din[ 0] ^ din[ 5] ^ din[ 2];
+      dout[25] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
+      dout[24] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
+      dout[23] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[22] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
+      dout[21] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
+      dout[20] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
+      dout[19] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
+      dout[18] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
+      dout[17] = din[ 0] ^ din[ 2] ^ din[ 6];
+      dout[16] = din[ 6] ^ din[ 1];
+      dout[15] = din[ 5] ^ din[ 0];
+      dout[14] = din[ 4] ^ din[ 6] ^ din[ 5];
+      dout[13] = din[ 3] ^ din[ 5] ^ din[ 4];
+      dout[12] = din[ 2] ^ din[ 4] ^ din[ 3];
+      dout[11] = din[ 1] ^ din[ 3] ^ din[ 2];
+      dout[10] = din[ 0] ^ din[ 2] ^ din[ 1];
+      dout[ 9] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
+      dout[ 8] = din[ 0] ^ din[ 4] ^ din[ 6];
+      dout[ 7] = din[ 6] ^ din[ 3];
+      dout[ 6] = din[ 5] ^ din[ 2];
+      dout[ 5] = din[ 4] ^ din[ 1];
+      dout[ 4] = din[ 3] ^ din[ 0];
+      dout[ 3] = din[ 2] ^ din[ 6] ^ din[ 5];
+      dout[ 2] = din[ 1] ^ din[ 5] ^ din[ 4];
+      dout[ 1] = din[ 0] ^ din[ 4] ^ din[ 3];
+      dout[ 0] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
       pn7 = dout;
     end
   endfunction
 
-  // pn15 function
+  
+  // PN15 function
 
   function [63:0] pn15;
-    input [63:0] din;
+    input [15:0] din;
     reg   [63:0] dout;
     begin
-      dout[63] = din[15] ^ din[14];
-      dout[62] = din[14] ^ din[13];
-      dout[61] = din[13] ^ din[12];
-      dout[60] = din[12] ^ din[11];
-      dout[59] = din[11] ^ din[10];
-      dout[58] = din[10] ^ din[ 9];
-      dout[57] = din[ 9] ^ din[ 8];
-      dout[56] = din[ 8] ^ din[ 7];
-      dout[55] = din[ 7] ^ din[ 6];
-      dout[54] = din[ 6] ^ din[ 5];
-      dout[53] = din[ 5] ^ din[ 4];
-      dout[52] = din[ 4] ^ din[ 3];
-      dout[51] = din[ 3] ^ din[ 2];
-      dout[50] = din[ 2] ^ din[ 1];
-      dout[49] = din[ 1] ^ din[ 0];
-      dout[48] = din[ 0] ^ din[15] ^ din[14];
-      dout[47] = din[15] ^ din[13];
-      dout[46] = din[14] ^ din[12];
-      dout[45] = din[13] ^ din[11];
-      dout[44] = din[12] ^ din[10];
-      dout[43] = din[11] ^ din[ 9];
-      dout[42] = din[10] ^ din[ 8];
-      dout[41] = din[ 9] ^ din[ 7];
-      dout[40] = din[ 8] ^ din[ 6];
-      dout[39] = din[ 7] ^ din[ 5];
-      dout[38] = din[ 6] ^ din[ 4];
-      dout[37] = din[ 5] ^ din[ 3];
-      dout[36] = din[ 4] ^ din[ 2];
-      dout[35] = din[ 3] ^ din[ 1];
-      dout[34] = din[ 2] ^ din[ 0];
-      dout[33] = din[ 1] ^ din[15] ^ din[14];
-      dout[32] = din[ 0] ^ din[14] ^ din[13];
-      dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12];
-      dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11];
-      dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10];
-      dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
-      dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
-      dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
-      dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
-      dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
-      dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
-      dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
-      dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
-      dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
-      dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
-      dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14];
-      dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13];
-      dout[16] = din[ 0] ^ din[15] ^ din[12];
-      dout[15] = din[15] ^ din[11];
-      dout[14] = din[14] ^ din[10];
-      dout[13] = din[13] ^ din[ 9];
-      dout[12] = din[12] ^ din[ 8];
-      dout[11] = din[11] ^ din[ 7];
-      dout[10] = din[10] ^ din[ 6];
-      dout[ 9] = din[ 9] ^ din[ 5];
-      dout[ 8] = din[ 8] ^ din[ 4];
-      dout[ 7] = din[ 7] ^ din[ 3];
-      dout[ 6] = din[ 6] ^ din[ 2];
-      dout[ 5] = din[ 5] ^ din[ 1];
-      dout[ 4] = din[ 4] ^ din[ 0];
-      dout[ 3] = din[ 3] ^ din[15] ^ din[14];
-      dout[ 2] = din[ 2] ^ din[14] ^ din[13];
-      dout[ 1] = din[ 1] ^ din[13] ^ din[12];
-      dout[ 0] = din[ 0] ^ din[12] ^ din[11];
+      dout[63] = din[14] ^ din[13];
+      dout[62] = din[13] ^ din[12];
+      dout[61] = din[12] ^ din[11];
+      dout[60] = din[11] ^ din[10];
+      dout[59] = din[10] ^ din[ 9];
+      dout[58] = din[ 9] ^ din[ 8];
+      dout[57] = din[ 8] ^ din[ 7];
+      dout[56] = din[ 7] ^ din[ 6];
+      dout[55] = din[ 6] ^ din[ 5];
+      dout[54] = din[ 5] ^ din[ 4];
+      dout[53] = din[ 4] ^ din[ 3];
+      dout[52] = din[ 3] ^ din[ 2];
+      dout[51] = din[ 2] ^ din[ 1];
+      dout[50] = din[ 1] ^ din[ 0];
+      dout[49] = din[ 0] ^ din[14] ^ din[13];
+      dout[48] = din[14] ^ din[12];
+      dout[47] = din[13] ^ din[11];
+      dout[46] = din[12] ^ din[10];
+      dout[45] = din[11] ^ din[ 9];
+      dout[44] = din[10] ^ din[ 8];
+      dout[43] = din[ 9] ^ din[ 7];
+      dout[42] = din[ 8] ^ din[ 6];
+      dout[41] = din[ 7] ^ din[ 5];
+      dout[40] = din[ 6] ^ din[ 4];
+      dout[39] = din[ 5] ^ din[ 3];
+      dout[38] = din[ 4] ^ din[ 2];
+      dout[37] = din[ 3] ^ din[ 1];
+      dout[36] = din[ 2] ^ din[ 0];
+      dout[35] = din[ 1] ^ din[14] ^ din[13];
+      dout[34] = din[ 0] ^ din[13] ^ din[12];
+      dout[33] = din[14] ^ din[12] ^ din[13] ^ din[11];
+      dout[32] = din[13] ^ din[11] ^ din[12] ^ din[10];
+      dout[31] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
+      dout[30] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
+      dout[29] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
+      dout[28] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
+      dout[27] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
+      dout[26] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
+      dout[25] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
+      dout[24] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
+      dout[23] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
+      dout[22] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
+      dout[21] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
+      dout[20] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
+      dout[19] = din[ 0] ^ din[14] ^ din[11];
+      dout[18] = din[14] ^ din[10];
+      dout[17] = din[13] ^ din[ 9];
+      dout[16] = din[12] ^ din[ 8];
+      dout[15] = din[11] ^ din[ 7];
+      dout[14] = din[10] ^ din[ 6];
+      dout[13] = din[ 9] ^ din[ 5];
+      dout[12] = din[ 8] ^ din[ 4];
+      dout[11] = din[ 7] ^ din[ 3];
+      dout[10] = din[ 6] ^ din[ 2];
+      dout[ 9] = din[ 5] ^ din[ 1];
+      dout[ 8] = din[ 4] ^ din[ 0];
+      dout[ 7] = din[ 3] ^ din[14] ^ din[13];
+      dout[ 6] = din[ 2] ^ din[13] ^ din[12];
+      dout[ 5] = din[ 1] ^ din[12] ^ din[11];
+      dout[ 4] = din[ 0] ^ din[11] ^ din[10];
+      dout[ 3] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
+      dout[ 2] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
+      dout[ 1] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
+      dout[ 0] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
       pn15 = dout;
     end
   endfunction
 
-  // pn23 function
-
-  function [63:0] pn23;
-    input [63:0] din;
-    reg   [63:0] dout;
-    begin
-      dout[63] = din[23] ^ din[18];
-      dout[62] = din[22] ^ din[17];
-      dout[61] = din[21] ^ din[16];
-      dout[60] = din[20] ^ din[15];
-      dout[59] = din[19] ^ din[14];
-      dout[58] = din[18] ^ din[13];
-      dout[57] = din[17] ^ din[12];
-      dout[56] = din[16] ^ din[11];
-      dout[55] = din[15] ^ din[10];
-      dout[54] = din[14] ^ din[ 9];
-      dout[53] = din[13] ^ din[ 8];
-      dout[52] = din[12] ^ din[ 7];
-      dout[51] = din[11] ^ din[ 6];
-      dout[50] = din[10] ^ din[ 5];
-      dout[49] = din[ 9] ^ din[ 4];
-      dout[48] = din[ 8] ^ din[ 3];
-      dout[47] = din[ 7] ^ din[ 2];
-      dout[46] = din[ 6] ^ din[ 1];
-      dout[45] = din[ 5] ^ din[ 0];
-      dout[44] = din[ 4] ^ din[23] ^ din[18];
-      dout[43] = din[ 3] ^ din[22] ^ din[17];
-      dout[42] = din[ 2] ^ din[21] ^ din[16];
-      dout[41] = din[ 1] ^ din[20] ^ din[15];
-      dout[40] = din[ 0] ^ din[19] ^ din[14];
-      dout[39] = din[23] ^ din[13];
-      dout[38] = din[22] ^ din[12];
-      dout[37] = din[21] ^ din[11];
-      dout[36] = din[20] ^ din[10];
-      dout[35] = din[19] ^ din[ 9];
-      dout[34] = din[18] ^ din[ 8];
-      dout[33] = din[17] ^ din[ 7];
-      dout[32] = din[16] ^ din[ 6];
-      dout[31] = din[15] ^ din[ 5];
-      dout[30] = din[14] ^ din[ 4];
-      dout[29] = din[13] ^ din[ 3];
-      dout[28] = din[12] ^ din[ 2];
-      dout[27] = din[11] ^ din[ 1];
-      dout[26] = din[10] ^ din[ 0];
-      dout[25] = din[ 9] ^ din[23] ^ din[18];
-      dout[24] = din[ 8] ^ din[22] ^ din[17];
-      dout[23] = din[ 7] ^ din[21] ^ din[16];
-      dout[22] = din[ 6] ^ din[20] ^ din[15];
-      dout[21] = din[ 5] ^ din[19] ^ din[14];
-      dout[20] = din[ 4] ^ din[18] ^ din[13];
-      dout[19] = din[ 3] ^ din[17] ^ din[12];
-      dout[18] = din[ 2] ^ din[16] ^ din[11];
-      dout[17] = din[ 1] ^ din[15] ^ din[10];
-      dout[16] = din[ 0] ^ din[14] ^ din[ 9];
-      dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8];
-      dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
-      dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
-      dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
-      dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
-      dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
-      dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
-      dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
-      dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
-      dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18];
-      dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17];
-      dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16];
-      dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15];
-      dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14];
-      dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13];
-      dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12];
-      pn23 = dout;
-    end
-  endfunction
-
-  // pn31 function
-
-  function [63:0] pn31;
-    input [63:0] din;
-    reg   [63:0] dout;
-    begin
-      dout[63] = din[31] ^ din[28];
-      dout[62] = din[30] ^ din[27];
-      dout[61] = din[29] ^ din[26];
-      dout[60] = din[28] ^ din[25];
-      dout[59] = din[27] ^ din[24];
-      dout[58] = din[26] ^ din[23];
-      dout[57] = din[25] ^ din[22];
-      dout[56] = din[24] ^ din[21];
-      dout[55] = din[23] ^ din[20];
-      dout[54] = din[22] ^ din[19];
-      dout[53] = din[21] ^ din[18];
-      dout[52] = din[20] ^ din[17];
-      dout[51] = din[19] ^ din[16];
-      dout[50] = din[18] ^ din[15];
-      dout[49] = din[17] ^ din[14];
-      dout[48] = din[16] ^ din[13];
-      dout[47] = din[15] ^ din[12];
-      dout[46] = din[14] ^ din[11];
-      dout[45] = din[13] ^ din[10];
-      dout[44] = din[12] ^ din[ 9];
-      dout[43] = din[11] ^ din[ 8];
-      dout[42] = din[10] ^ din[ 7];
-      dout[41] = din[ 9] ^ din[ 6];
-      dout[40] = din[ 8] ^ din[ 5];
-      dout[39] = din[ 7] ^ din[ 4];
-      dout[38] = din[ 6] ^ din[ 3];
-      dout[37] = din[ 5] ^ din[ 2];
-      dout[36] = din[ 4] ^ din[ 1];
-      dout[35] = din[ 3] ^ din[ 0];
-      dout[34] = din[ 2] ^ din[31] ^ din[28];
-      dout[33] = din[ 1] ^ din[30] ^ din[27];
-      dout[32] = din[ 0] ^ din[29] ^ din[26];
-      dout[31] = din[31] ^ din[25];
-      dout[30] = din[30] ^ din[24];
-      dout[29] = din[29] ^ din[23];
-      dout[28] = din[28] ^ din[22];
-      dout[27] = din[27] ^ din[21];
-      dout[26] = din[26] ^ din[20];
-      dout[25] = din[25] ^ din[19];
-      dout[24] = din[24] ^ din[18];
-      dout[23] = din[23] ^ din[17];
-      dout[22] = din[22] ^ din[16];
-      dout[21] = din[21] ^ din[15];
-      dout[20] = din[20] ^ din[14];
-      dout[19] = din[19] ^ din[13];
-      dout[18] = din[18] ^ din[12];
-      dout[17] = din[17] ^ din[11];
-      dout[16] = din[16] ^ din[10];
-      dout[15] = din[15] ^ din[ 9];
-      dout[14] = din[14] ^ din[ 8];
-      dout[13] = din[13] ^ din[ 7];
-      dout[12] = din[12] ^ din[ 6];
-      dout[11] = din[11] ^ din[ 5];
-      dout[10] = din[10] ^ din[ 4];
-      dout[ 9] = din[ 9] ^ din[ 3];
-      dout[ 8] = din[ 8] ^ din[ 2];
-      dout[ 7] = din[ 7] ^ din[ 1];
-      dout[ 6] = din[ 6] ^ din[ 0];
-      dout[ 5] = din[ 5] ^ din[31] ^ din[28];
-      dout[ 4] = din[ 4] ^ din[30] ^ din[27];
-      dout[ 3] = din[ 3] ^ din[29] ^ din[26];
-      dout[ 2] = din[ 2] ^ din[28] ^ din[25];
-      dout[ 1] = din[ 1] ^ din[27] ^ din[24];
-      dout[ 0] = din[ 0] ^ din[26] ^ din[23];
-      pn31 = dout;
-    end
-  endfunction
-
-  // dac data select
+   // dac data select
 
   always @(posedge dac_clk) begin
     dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
     case (dac_data_sel_s)
-      4'h7: dac_data <= dac_pn31_data;
-      4'h6: dac_data <= dac_pn23_data;
+      //4'h7: dac_data <= dac_pn31_data;
+      //4'h6: dac_data <= dac_pn23_data;
       4'h5: dac_data <= dac_pn15_data;
       4'h4: dac_data <= dac_pn7_data;
       4'h3: dac_data <= 64'd0;
@@ -451,15 +304,15 @@ module axi_ad9144_channel (
 
   always @(posedge dac_clk) begin
     if (dac_data_sync == 1'b1) begin
-      dac_pn7_data <= {64{1'd1}};
-      dac_pn15_data <= {64{1'd1}};
-      dac_pn23_data <= {64{1'd1}};
-      dac_pn31_data <= {64{1'd1}};
+      dac_pn7_data <= {8{1'd1}};
+      dac_pn15_data <= {8{1'd1}};
+      //dac_pn23_data <= {64{1'd1}};
+      //dac_pn31_data <= {64{1'd1}};
     end else begin
       dac_pn7_data <= pn7(dac_pn7_data);
       dac_pn15_data <= pn15(dac_pn15_data);
-      dac_pn23_data <= pn23(dac_pn23_data);
-      dac_pn31_data <= pn31(dac_pn31_data);
+      //dac_pn23_data <= pn23(dac_pn23_data);
+      //dac_pn31_data <= pn31(dac_pn31_data);
     end
   end
 
@@ -600,3 +453,7 @@ endmodule
 
 // ***************************************************************************
 // ***************************************************************************
+
+
+
+  

From 27fd5f5bdcbb512e55094d38df2b38888f5ef174 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Mon, 13 Jun 2016 14:09:39 -0400
Subject: [PATCH 278/972] modified prbs7 and prbs15 gereration code

---
 library/axi_ad9144/axi_ad9144_channel.v | 293 ++++++++++++------------
 1 file changed, 147 insertions(+), 146 deletions(-)

diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v
index 37833974b..c6b41a101 100644
--- a/library/axi_ad9144/axi_ad9144_channel.v
+++ b/library/axi_ad9144/axi_ad9144_channel.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -104,8 +102,6 @@ module axi_ad9144_channel (
   reg     [63:0]  dac_data = 'd0;
   reg     [63:0]  dac_pn7_data = 'd0;
   reg     [63:0]  dac_pn15_data = 'd0;
- // reg     [63:0]  dac_pn23_data = 'd0;
- // reg     [63:0]  dac_pn31_data = 'd0;
   reg     [15:0]  dac_dds_phase_0_0 = 'd0;
   reg     [15:0]  dac_dds_phase_0_1 = 'd0;
   reg     [15:0]  dac_dds_phase_1_0 = 'd0;
@@ -133,6 +129,10 @@ module axi_ad9144_channel (
   wire    [15:0]  dac_pat_data_1_s;
   wire    [15:0]  dac_pat_data_2_s;
   wire    [ 3:0]  dac_data_sel_s;
+  wire    [63:0]  dac_pn7_data_i_s;
+  wire    [63:0]  dac_pn15_data_i_s;
+  wire    [63:0]  dac_pn7_data_s;
+  wire    [63:0]  dac_pn15_data_s;
 
    // PN7 function
 
@@ -140,74 +140,73 @@ module axi_ad9144_channel (
     input [7:0] din;
     reg   [63:0] dout;
     begin
-      dout[63] = din[ 6] ^ din[ 5];
-      dout[62] = din[ 5] ^ din[ 4];
-      dout[61] = din[ 4] ^ din[ 3];
-      dout[60] = din[ 3] ^ din[ 2];
-      dout[59] = din[ 2] ^ din[ 1];
-      dout[58] = din[ 1] ^ din[ 0];
-      dout[57] = din[ 0] ^ din[ 6] ^ din[ 5];
-      dout[56] = din[ 6] ^ din[ 4];
-      dout[55] = din[ 5] ^ din[ 3];
-      dout[54] = din[ 4] ^ din[ 2];
-      dout[53] = din[ 3] ^ din[ 1];
-      dout[52] = din[ 2] ^ din[ 0];
-      dout[51] = din[ 1] ^ din[ 6] ^ din[ 5];
-      dout[50] = din[ 0] ^ din[ 5] ^ din[ 4];
-      dout[49] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
-      dout[48] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
-      dout[47] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
-      dout[46] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
-      dout[45] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
-      dout[44] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
-      dout[43] = din[ 0] ^ din[ 6] ^ din[ 3];
-      dout[42] = din[ 6] ^ din[ 2];
-      dout[41] = din[ 5] ^ din[ 1];
-      dout[40] = din[ 4] ^ din[ 0];
-      dout[39] = din[ 3] ^ din[ 6] ^ din[ 5];
-      dout[38] = din[ 2] ^ din[ 5] ^ din[ 4];
-      dout[37] = din[ 1] ^ din[ 4] ^ din[ 3];
-      dout[36] = din[ 0] ^ din[ 3] ^ din[ 2];
-      dout[35] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
-      dout[34] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
-      dout[33] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
-      dout[32] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
-      dout[31] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
-      dout[30] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
-      dout[29] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
-      dout[28] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
-      dout[27] = din[ 1] ^ din[ 3] ^ din[ 6];
-      dout[26] = din[ 0] ^ din[ 5] ^ din[ 2];
-      dout[25] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
-      dout[24] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
-      dout[23] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
-      dout[22] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
-      dout[21] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
-      dout[20] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
-      dout[19] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
-      dout[18] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
-      dout[17] = din[ 0] ^ din[ 2] ^ din[ 6];
-      dout[16] = din[ 6] ^ din[ 1];
-      dout[15] = din[ 5] ^ din[ 0];
-      dout[14] = din[ 4] ^ din[ 6] ^ din[ 5];
-      dout[13] = din[ 3] ^ din[ 5] ^ din[ 4];
-      dout[12] = din[ 2] ^ din[ 4] ^ din[ 3];
-      dout[11] = din[ 1] ^ din[ 3] ^ din[ 2];
-      dout[10] = din[ 0] ^ din[ 2] ^ din[ 1];
-      dout[ 9] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
-      dout[ 8] = din[ 0] ^ din[ 4] ^ din[ 6];
-      dout[ 7] = din[ 6] ^ din[ 3];
-      dout[ 6] = din[ 5] ^ din[ 2];
-      dout[ 5] = din[ 4] ^ din[ 1];
-      dout[ 4] = din[ 3] ^ din[ 0];
-      dout[ 3] = din[ 2] ^ din[ 6] ^ din[ 5];
-      dout[ 2] = din[ 1] ^ din[ 5] ^ din[ 4];
-      dout[ 1] = din[ 0] ^ din[ 4] ^ din[ 3];
-      dout[ 0] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
+      dout[15] = din[ 6] ^ din[ 5];
+      dout[14] = din[ 5] ^ din[ 4];
+      dout[13] = din[ 4] ^ din[ 3];
+      dout[12] = din[ 3] ^ din[ 2];
+      dout[11] = din[ 2] ^ din[ 1];
+      dout[10] = din[ 1] ^ din[ 0];
+      dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5];
+      dout[ 8] = din[ 6] ^ din[ 4];
+      dout[ 7] = din[ 5] ^ din[ 3];
+      dout[ 6] = din[ 4] ^ din[ 2];
+      dout[ 5] = din[ 3] ^ din[ 1];
+      dout[ 4] = din[ 2] ^ din[ 0];
+      dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5];
+      dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4];
+      dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
+      dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
+      dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
+      dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
+      dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
+      dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
+      dout[27] = din[ 0] ^ din[ 6] ^ din[ 3];
+      dout[26] = din[ 6] ^ din[ 2];
+      dout[25] = din[ 5] ^ din[ 1];
+      dout[24] = din[ 4] ^ din[ 0];
+      dout[23] = din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[22] = din[ 2] ^ din[ 5] ^ din[ 4];
+      dout[21] = din[ 1] ^ din[ 4] ^ din[ 3];
+      dout[20] = din[ 0] ^ din[ 3] ^ din[ 2];
+      dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
+      dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
+      dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
+      dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
+      dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
+      dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
+      dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
+      dout[43] = din[ 1] ^ din[ 3] ^ din[ 6];
+      dout[42] = din[ 0] ^ din[ 5] ^ din[ 2];
+      dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
+      dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
+      dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
+      dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
+      dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
+      dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
+      dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
+      dout[33] = din[ 0] ^ din[ 2] ^ din[ 6];
+      dout[32] = din[ 6] ^ din[ 1];
+      dout[63] = din[ 5] ^ din[ 0];
+      dout[62] = din[ 4] ^ din[ 6] ^ din[ 5];
+      dout[61] = din[ 3] ^ din[ 5] ^ din[ 4];
+      dout[60] = din[ 2] ^ din[ 4] ^ din[ 3];
+      dout[59] = din[ 1] ^ din[ 3] ^ din[ 2];
+      dout[58] = din[ 0] ^ din[ 2] ^ din[ 1];
+      dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
+      dout[56] = din[ 0] ^ din[ 4] ^ din[ 6];
+      dout[55] = din[ 6] ^ din[ 3];
+      dout[54] = din[ 5] ^ din[ 2];
+      dout[53] = din[ 4] ^ din[ 1];
+      dout[52] = din[ 3] ^ din[ 0];
+      dout[51] = din[ 2] ^ din[ 6] ^ din[ 5];
+      dout[50] = din[ 1] ^ din[ 5] ^ din[ 4];
+      dout[49] = din[ 0] ^ din[ 4] ^ din[ 3];
+      dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
       pn7 = dout;
     end
   endfunction
-
   
   // PN15 function
 
@@ -215,83 +214,89 @@ module axi_ad9144_channel (
     input [15:0] din;
     reg   [63:0] dout;
     begin
-      dout[63] = din[14] ^ din[13];
-      dout[62] = din[13] ^ din[12];
-      dout[61] = din[12] ^ din[11];
-      dout[60] = din[11] ^ din[10];
-      dout[59] = din[10] ^ din[ 9];
-      dout[58] = din[ 9] ^ din[ 8];
-      dout[57] = din[ 8] ^ din[ 7];
-      dout[56] = din[ 7] ^ din[ 6];
-      dout[55] = din[ 6] ^ din[ 5];
-      dout[54] = din[ 5] ^ din[ 4];
-      dout[53] = din[ 4] ^ din[ 3];
-      dout[52] = din[ 3] ^ din[ 2];
-      dout[51] = din[ 2] ^ din[ 1];
-      dout[50] = din[ 1] ^ din[ 0];
-      dout[49] = din[ 0] ^ din[14] ^ din[13];
-      dout[48] = din[14] ^ din[12];
-      dout[47] = din[13] ^ din[11];
-      dout[46] = din[12] ^ din[10];
-      dout[45] = din[11] ^ din[ 9];
-      dout[44] = din[10] ^ din[ 8];
-      dout[43] = din[ 9] ^ din[ 7];
-      dout[42] = din[ 8] ^ din[ 6];
-      dout[41] = din[ 7] ^ din[ 5];
-      dout[40] = din[ 6] ^ din[ 4];
-      dout[39] = din[ 5] ^ din[ 3];
-      dout[38] = din[ 4] ^ din[ 2];
-      dout[37] = din[ 3] ^ din[ 1];
-      dout[36] = din[ 2] ^ din[ 0];
-      dout[35] = din[ 1] ^ din[14] ^ din[13];
-      dout[34] = din[ 0] ^ din[13] ^ din[12];
-      dout[33] = din[14] ^ din[12] ^ din[13] ^ din[11];
-      dout[32] = din[13] ^ din[11] ^ din[12] ^ din[10];
-      dout[31] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
-      dout[30] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
-      dout[29] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
-      dout[28] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
-      dout[27] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
-      dout[26] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
-      dout[25] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
-      dout[24] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
-      dout[23] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
-      dout[22] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
-      dout[21] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
-      dout[20] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
-      dout[19] = din[ 0] ^ din[14] ^ din[11];
-      dout[18] = din[14] ^ din[10];
-      dout[17] = din[13] ^ din[ 9];
-      dout[16] = din[12] ^ din[ 8];
-      dout[15] = din[11] ^ din[ 7];
-      dout[14] = din[10] ^ din[ 6];
-      dout[13] = din[ 9] ^ din[ 5];
-      dout[12] = din[ 8] ^ din[ 4];
-      dout[11] = din[ 7] ^ din[ 3];
-      dout[10] = din[ 6] ^ din[ 2];
-      dout[ 9] = din[ 5] ^ din[ 1];
-      dout[ 8] = din[ 4] ^ din[ 0];
-      dout[ 7] = din[ 3] ^ din[14] ^ din[13];
-      dout[ 6] = din[ 2] ^ din[13] ^ din[12];
-      dout[ 5] = din[ 1] ^ din[12] ^ din[11];
-      dout[ 4] = din[ 0] ^ din[11] ^ din[10];
-      dout[ 3] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
-      dout[ 2] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
-      dout[ 1] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
-      dout[ 0] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
+      dout[15] = din[14] ^ din[13];
+      dout[14] = din[13] ^ din[12];
+      dout[13] = din[12] ^ din[11];
+      dout[12] = din[11] ^ din[10];
+      dout[11] = din[10] ^ din[ 9];
+      dout[10] = din[ 9] ^ din[ 8];
+      dout[ 9] = din[ 8] ^ din[ 7];
+      dout[ 8] = din[ 7] ^ din[ 6];
+      dout[ 7] = din[ 6] ^ din[ 5];
+      dout[ 6] = din[ 5] ^ din[ 4];
+      dout[ 5] = din[ 4] ^ din[ 3];
+      dout[ 4] = din[ 3] ^ din[ 2];
+      dout[ 3] = din[ 2] ^ din[ 1];
+      dout[ 2] = din[ 1] ^ din[ 0];
+      dout[ 1] = din[ 0] ^ din[14] ^ din[13];
+      dout[ 0] = din[14] ^ din[12];
+      dout[31] = din[13] ^ din[11];
+      dout[30] = din[12] ^ din[10];
+      dout[29] = din[11] ^ din[ 9];
+      dout[28] = din[10] ^ din[ 8];
+      dout[27] = din[ 9] ^ din[ 7];
+      dout[26] = din[ 8] ^ din[ 6];
+      dout[25] = din[ 7] ^ din[ 5];
+      dout[24] = din[ 6] ^ din[ 4];
+      dout[23] = din[ 5] ^ din[ 3];
+      dout[22] = din[ 4] ^ din[ 2];
+      dout[21] = din[ 3] ^ din[ 1];
+      dout[20] = din[ 2] ^ din[ 0];
+      dout[19] = din[ 1] ^ din[14] ^ din[13];
+      dout[18] = din[ 0] ^ din[13] ^ din[12];
+      dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11];
+      dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10];
+      dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
+      dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
+      dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
+      dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
+      dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
+      dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
+      dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
+      dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
+      dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
+      dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
+      dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
+      dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
+      dout[35] = din[ 0] ^ din[14] ^ din[11];
+      dout[34] = din[14] ^ din[10];
+      dout[33] = din[13] ^ din[ 9];
+      dout[32] = din[12] ^ din[ 8];
+      dout[63] = din[11] ^ din[ 7];
+      dout[62] = din[10] ^ din[ 6];
+      dout[61] = din[ 9] ^ din[ 5];
+      dout[60] = din[ 8] ^ din[ 4];
+      dout[59] = din[ 7] ^ din[ 3];
+      dout[58] = din[ 6] ^ din[ 2];
+      dout[57] = din[ 5] ^ din[ 1];
+      dout[56] = din[ 4] ^ din[ 0];
+      dout[55] = din[ 3] ^ din[14] ^ din[13];
+      dout[54] = din[ 2] ^ din[13] ^ din[12];
+      dout[53] = din[ 1] ^ din[12] ^ din[11];
+      dout[52] = din[ 0] ^ din[11] ^ din[10];
+      dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
+      dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
+      dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
+      dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
       pn15 = dout;
     end
   endfunction
 
-   // dac data select
+  assign dac_pn7_data_i_s  = ~dac_pn7_data;
+  assign dac_pn15_data_i_s = ~dac_pn15_data;
+
+  assign dac_pn7_data_s    = dac_pn7_data;
+  assign dac_pn15_data_s   = dac_pn15_data;
+
+  // dac data select
 
   always @(posedge dac_clk) begin
     dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
     case (dac_data_sel_s)
-      //4'h7: dac_data <= dac_pn31_data;
-      //4'h6: dac_data <= dac_pn23_data;
-      4'h5: dac_data <= dac_pn15_data;
-      4'h4: dac_data <= dac_pn7_data;
+      4'h7: dac_data <= dac_pn15_data_s;
+      4'h6: dac_data <= dac_pn7_data_s;
+      4'h5: dac_data <= dac_pn15_data_i_s;
+      4'h4: dac_data <= dac_pn7_data_i_s;
       4'h3: dac_data <= 64'd0;
       4'h2: dac_data <= dma_data;
       4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
@@ -304,15 +309,11 @@ module axi_ad9144_channel (
 
   always @(posedge dac_clk) begin
     if (dac_data_sync == 1'b1) begin
-      dac_pn7_data <= {8{1'd1}};
-      dac_pn15_data <= {8{1'd1}};
-      //dac_pn23_data <= {64{1'd1}};
-      //dac_pn31_data <= {64{1'd1}};
+      dac_pn7_data <= {64{1'd1}};
+      dac_pn15_data <= {64{1'd1}};
     end else begin
-      dac_pn7_data <= pn7(dac_pn7_data);
-      dac_pn15_data <= pn15(dac_pn15_data);
-      //dac_pn23_data <= pn23(dac_pn23_data);
-      //dac_pn31_data <= pn31(dac_pn31_data);
+      dac_pn7_data <= pn7(dac_pn7_data[55:48]);
+      dac_pn15_data <= pn15(dac_pn15_data[63:48]);
     end
   end
 

From aee38e1cc90f108acbac358859ba39064fec4428 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Tue, 14 Jun 2016 14:27:03 +0300
Subject: [PATCH 279/972] up_hdmi_tx: Fixed data path width

---
 library/common/up_hdmi_tx.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v
index 491524f32..64099b9e3 100644
--- a/library/common/up_hdmi_tx.v
+++ b/library/common/up_hdmi_tx.v
@@ -323,7 +323,7 @@ module up_hdmi_tx (
 
   // hdmi control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(237)) i_xfer_cntrl (
+  up_xfer_cntrl #(.DATA_WIDTH(236)) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_ss_bypass,

From c19ed4c8ef150eda88b47e0bc1b68beea751aaf3 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Tue, 14 Jun 2016 14:30:28 +0300
Subject: [PATCH 280/972] axi_hdmi_tx_core: Fixed embedded sync synchronization
 signals

---
 library/axi_hdmi_tx/axi_hdmi_tx_core.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
index 8ce7afebf..6a3ff7bb9 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
@@ -582,8 +582,8 @@ module axi_hdmi_tx_core (
   // hdmi embedded sync
 
   always @(posedge hdmi_clk) begin
-    hdmi_es_hs_de <= hdmi_16_hsync_d;
-    hdmi_es_vs_de <= hdmi_16_vsync_d;
+    hdmi_es_hs_de <= hdmi_16_hsync_data_e_d;
+    hdmi_es_vs_de <= hdmi_16_vsync_data_e_d;
     if (hdmi_16_data_e_d == 1'b0) begin
       hdmi_es_data[15:8] <= 8'h80;
     end else begin

From dc45287b14435bf1d6d38d0db47b6a42b54f1e6a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 14 Jun 2016 12:18:56 -0400
Subject: [PATCH 281/972] util_adxcvr- added

---
 library/util_adxcvr/util_adxcvr_xch.v | 1357 +++++++++++++++++++++++++
 library/util_adxcvr/util_adxcvr_xcm.v |  291 ++++++
 2 files changed, 1648 insertions(+)
 create mode 100644 library/util_adxcvr/util_adxcvr_xch.v
 create mode 100644 library/util_adxcvr/util_adxcvr_xcm.v

diff --git a/library/util_adxcvr/util_adxcvr_xch.v b/library/util_adxcvr/util_adxcvr_xch.v
new file mode 100644
index 000000000..2734e04e4
--- /dev/null
+++ b/library/util_adxcvr/util_adxcvr_xch.v
@@ -0,0 +1,1357 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module util_adxcvr_xch (
+
+  // rst and clocks
+
+  input           ref_clk,
+  input           pll_rst,
+
+  input           qpll_clk,
+  input           qpll_ref_clk,
+  input           qpll_locked,
+
+  // receive
+
+  input           rx_p,
+  input           rx_n,
+
+  input           rx_rst,
+  input           rx_clk,
+  input           rx_lpm_dfe_n,
+  input   [ 2:0]  rx_rate,
+  input   [ 1:0]  rx_sys_clk_sel,
+  input   [ 2:0]  rx_out_clk_sel,
+  output          rx_out_clk,
+  output          rx_rst_done,
+  output          rx_pll_locked,
+  input           rx_user_ready,
+  output  [ 3:0]  rx_gt_charisk,
+  output  [ 3:0]  rx_gt_disperr,
+  output  [ 3:0]  rx_gt_notintable,
+  output  [31:0]  rx_gt_data,
+  input           rx_gt_calign,
+
+  // transmit
+
+  output          tx_p,
+  output          tx_n,
+
+  input           tx_rst,
+  input           tx_clk,
+  input   [ 2:0]  tx_rate,
+  input   [ 1:0]  tx_sys_clk_sel,
+  input   [ 2:0]  tx_out_clk_sel,
+  output          tx_out_clk,
+  output          tx_rst_done,
+  output          tx_pll_locked,
+  input           tx_user_ready,
+  input   [ 3:0]  tx_gt_charisk,
+  input   [31:0]  tx_gt_data,
+
+  // drp interface
+
+  input           up_rstn,
+  input           up_clk,
+  input   [ 7:0]  up_drp_sel,
+  input           up_drp_enb,
+  input   [11:0]  up_drp_addr,
+  input           up_drp_wr,
+  input   [15:0]  up_drp_wdata,
+  output  [15:0]  up_drp_rdata,
+  output          up_drp_ready);
+
+  // parameters
+
+  parameter   integer GTH_OR_GTX_N = 0;
+  parameter   integer CPLL_FBDIV = 2;
+  parameter   integer RX_OUT_DIV = 1;
+  parameter   integer RX_CLK25_DIV = 10;
+  parameter   integer RX_CLKBUF_ENABLE = 0;
+  parameter   integer TX_OUT_DIV = 1;
+  parameter   integer TX_CLK25_DIV = 10;
+  parameter   integer TX_CLKBUF_ENABLE = 0;
+  parameter   [31:0]  PMA_RSV = 32'h00018480;
+  parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff20400020;
+
+  // internal registers
+
+  reg             up_drp_enb_int = 'd0;
+  reg     [11:0]  up_drp_addr_int = 'd0;
+  reg             up_drp_wr_int = 'd0;
+  reg     [15:0]  up_drp_wdata_int = 'd0;
+  reg     [15:0]  up_drp_rdata_int = 'd0;
+  reg             up_drp_ready_int = 'd0;
+
+  // internal signals
+
+  wire    [ 3:0]  rx_charisk_open_s;
+  wire    [ 3:0]  rx_disperr_open_s;
+  wire    [ 3:0]  rx_notintable_open_s;
+  wire    [31:0]  rx_data_open_s;
+  wire    [ 1:0]  rx_sys_clk_sel_s;
+  wire    [ 1:0]  tx_sys_clk_sel_s;
+  wire    [ 1:0]  rx_pll_clk_sel_s;
+  wire    [ 1:0]  tx_pll_clk_sel_s;
+  wire            cpll_locked_s;
+  wire    [15:0]  up_drp_rdata_s;
+  wire            up_drp_ready_s;
+
+  // pll locked
+
+  assign rx_pll_locked = (rx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
+  assign tx_pll_locked = (tx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
+
+  // drp access
+
+  assign up_drp_rdata = up_drp_rdata_int;
+  assign up_drp_ready = up_drp_ready_int;
+
+  always @(posedge up_clk or negedge up_rstn) begin
+    if (up_rstn == 1'b0) begin
+        up_drp_enb_int <= 1'd0;
+        up_drp_addr_int <= 12'd0;
+        up_drp_wr_int <= 1'd0;
+        up_drp_wdata_int <= 15'd0;
+        up_drp_rdata_int <= 15'd0;
+        up_drp_ready_int <= 1'd0;
+    end else begin
+      if ((up_drp_sel == XCVR_ID) || (up_drp_sel == 8'hff)) begin
+        up_drp_enb_int <= up_drp_enb;
+        up_drp_addr_int <= up_drp_addr;
+        up_drp_wr_int <= up_drp_wr;
+        up_drp_wdata_int <= up_drp_wdata;
+        up_drp_rdata_int <= up_drp_rdata_s;
+        up_drp_ready_int <= up_drp_ready_s;
+      end else begin
+        up_drp_enb_int <= 1'd0;
+        up_drp_addr_int <= 12'd0;
+        up_drp_wr_int <= 1'd0;
+        up_drp_wdata_int <= 15'd0;
+        up_drp_rdata_int <= 15'd0;
+        up_drp_ready_int <= 1'd0;
+      end
+    end
+  end
+
+  // instantiations
+
+  generate
+  if (GTH_OR_GTX_N == 0) begin
+  assign rx_sys_clk_sel_s = rx_sys_clk_sel;
+  assign tx_sys_clk_sel_s = tx_sys_clk_sel;
+  assign rx_pll_clk_sel_s = 2'd0;
+  assign tx_pll_clk_sel_s = 2'd0;
+  end
+  endgenerate
+
+  generate
+  if (GTH_OR_GTX_N == 0) begin
+  GTXE2_CHANNEL #(
+    .SIM_RECEIVER_DETECT_PASS ("TRUE"),
+    .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), 
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_CPLLREFCLK_SEL (3'b001),
+    .SIM_VERSION ("3.0"),
+    .ALIGN_COMMA_DOUBLE ("FALSE"),
+    .ALIGN_COMMA_ENABLE (10'b1111111111),
+    .ALIGN_COMMA_WORD (1),
+    .ALIGN_MCOMMA_DET ("TRUE"),
+    .ALIGN_MCOMMA_VALUE (10'b1010000011),
+    .ALIGN_PCOMMA_DET ("TRUE"),
+    .ALIGN_PCOMMA_VALUE (10'b0101111100),
+    .SHOW_REALIGN_COMMA ("TRUE"),
+    .RXSLIDE_AUTO_WAIT (7),
+    .RXSLIDE_MODE ("OFF"),
+    .RX_SIG_VALID_DLY (10),
+    .RX_DISPERR_SEQ_MATCH ("TRUE"),
+    .DEC_MCOMMA_DETECT ("TRUE"),
+    .DEC_PCOMMA_DETECT ("TRUE"),
+    .DEC_VALID_COMMA_ONLY ("FALSE"),
+    .CBCC_DATA_SOURCE_SEL ("DECODED"),
+    .CLK_COR_SEQ_2_USE ("FALSE"),
+    .CLK_COR_KEEP_IDLE ("FALSE"),
+    .CLK_COR_MAX_LAT (35),
+    .CLK_COR_MIN_LAT (31),
+    .CLK_COR_PRECEDENCE ("TRUE"),
+    .CLK_COR_REPEAT_WAIT (0),
+    .CLK_COR_SEQ_LEN (1),
+    .CLK_COR_SEQ_1_ENABLE (4'b1111),
+    .CLK_COR_SEQ_1_1 (10'b0000000000),
+    .CLK_COR_SEQ_1_2 (10'b0000000000),
+    .CLK_COR_SEQ_1_3 (10'b0000000000),
+    .CLK_COR_SEQ_1_4 (10'b0000000000),
+    .CLK_CORRECT_USE ("FALSE"),
+    .CLK_COR_SEQ_2_ENABLE (4'b1111),
+    .CLK_COR_SEQ_2_1 (10'b0000000000),
+    .CLK_COR_SEQ_2_2 (10'b0000000000),
+    .CLK_COR_SEQ_2_3 (10'b0000000000),
+    .CLK_COR_SEQ_2_4 (10'b0000000000),
+    .CHAN_BOND_KEEP_ALIGN ("FALSE"),
+    .CHAN_BOND_MAX_SKEW (7),
+    .CHAN_BOND_SEQ_LEN (1),
+    .CHAN_BOND_SEQ_1_1 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_2 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_3 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_4 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_ENABLE (4'b1111),
+    .CHAN_BOND_SEQ_2_1 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_2 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_3 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_4 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_ENABLE (4'b1111),
+    .CHAN_BOND_SEQ_2_USE ("FALSE"),
+    .FTS_DESKEW_SEQ_ENABLE (4'b1111),
+    .FTS_LANE_DESKEW_CFG (4'b1111),
+    .FTS_LANE_DESKEW_EN ("FALSE"),
+    .ES_CONTROL (6'b000000),
+    .ES_ERRDET_EN ("TRUE"),
+    .ES_EYE_SCAN_EN ("TRUE"),
+    .ES_HORZ_OFFSET (12'h000),
+    .ES_PMA_CFG (10'b0000000000),
+    .ES_PRESCALE (5'b00000),
+    .ES_QUALIFIER (80'h00000000000000000000),
+    .ES_QUAL_MASK (80'h00000000000000000000),
+    .ES_SDATA_MASK (80'h00000000000000000000),
+    .ES_VERT_OFFSET (9'b000000000),
+    .RX_DATA_WIDTH (40),
+    .OUTREFCLK_SEL_INV (2'b11),
+    .PMA_RSV (PMA_RSV),
+    .PMA_RSV2 (16'h2070),
+    .PMA_RSV3 (2'b00),
+    .PMA_RSV4 (32'h00000000),
+    .RX_BIAS_CFG (12'b000000000100),
+    .DMONITOR_CFG (24'h000A00),
+    .RX_CM_SEL (2'b11),
+    .RX_CM_TRIM (3'b010),
+    .RX_DEBUG_CFG (12'b000000000000),
+    .RX_OS_CFG (13'b0000010000000),
+    .TERM_RCAL_CFG (5'b10000),
+    .TERM_RCAL_OVRD (1'b0),
+    .TST_RSV (32'h00000000),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .UCODEER_CLR (1'b0),
+    .PCS_PCIE_EN ("FALSE"),
+    .PCS_RSVD_ATTR (48'h000000000000),
+    .RXBUF_ADDR_MODE ("FULL"),
+    .RXBUF_EIDLE_HI_CNT (4'b1000),
+    .RXBUF_EIDLE_LO_CNT (4'b0000),
+    .RXBUF_EN ("TRUE"),
+    .RX_BUFFER_CFG (6'b000000),
+    .RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
+    .RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
+    .RXBUF_RESET_ON_EIDLE ("FALSE"),
+    .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
+    .RXBUFRESET_TIME (5'b00001),
+    .RXBUF_THRESH_OVFLW (61),
+    .RXBUF_THRESH_OVRD ("FALSE"),
+    .RXBUF_THRESH_UNDFLW (4),
+    .RXDLY_CFG (16'h001F),
+    .RXDLY_LCFG (9'h030),
+    .RXDLY_TAP_CFG (16'h0000),
+    .RXPH_CFG (24'h000000),
+    .RXPHDLY_CFG (24'h084020),
+    .RXPH_MONITOR_SEL (5'b00000),
+    .RX_XCLK_SEL ("RXREC"),
+    .RX_DDI_SEL (6'b000000),
+    .RX_DEFER_RESET_BUF_EN ("TRUE"),
+    .RXCDR_CFG (RX_CDR_CFG),
+    .RXCDR_FR_RESET_ON_EIDLE (1'b0),
+    .RXCDR_HOLD_DURING_EIDLE (1'b0),
+    .RXCDR_PH_RESET_ON_EIDLE (1'b0),
+    .RXCDR_LOCK_CFG (6'b010101),
+    .RXCDRFREQRESET_TIME (5'b00001),
+    .RXCDRPHRESET_TIME (5'b00001),
+    .RXISCANRESET_TIME (5'b00001),
+    .RXPCSRESET_TIME (5'b00001),
+    .RXPMARESET_TIME (5'b00011),
+    .RXOOB_CFG (7'b0000110),
+    .RXGEARBOX_EN ("FALSE"),
+    .GEARBOX_MODE (3'b000),
+    .RXPRBS_ERR_LOOPBACK (1'b0),
+    .PD_TRANS_TIME_FROM_P2 (12'h03c),
+    .PD_TRANS_TIME_NONE_P2 (8'h3c),
+    .PD_TRANS_TIME_TO_P2 (8'h64),
+    .SAS_MAX_COM (64),
+    .SAS_MIN_COM (36),
+    .SATA_BURST_SEQ_LEN (4'b1111),
+    .SATA_BURST_VAL (3'b100),
+    .SATA_EIDLE_VAL (3'b100),
+    .SATA_MAX_BURST (8),
+    .SATA_MAX_INIT (21),
+    .SATA_MAX_WAKE (7),
+    .SATA_MIN_BURST (4),
+    .SATA_MIN_INIT (12),
+    .SATA_MIN_WAKE (4),
+    .TRANS_TIME_RATE (8'h0E),
+    .TXBUF_EN ("TRUE"),
+    .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
+    .TXDLY_CFG (16'h001F),
+    .TXDLY_LCFG (9'h030),
+    .TXDLY_TAP_CFG (16'h0000),
+    .TXPH_CFG (16'h0780),
+    .TXPHDLY_CFG (24'h084020),
+    .TXPH_MONITOR_SEL (5'b00000),
+    .TX_XCLK_SEL ("TXOUT"),
+    .TX_DATA_WIDTH (40),
+    .TX_DEEMPH0 (5'b00000),
+    .TX_DEEMPH1 (5'b00000),
+    .TX_EIDLE_ASSERT_DELAY (3'b110),
+    .TX_EIDLE_DEASSERT_DELAY (3'b100),
+    .TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
+    .TX_MAINCURSOR_SEL (1'b0),
+    .TX_DRIVE_MODE ("DIRECT"),
+    .TX_MARGIN_FULL_0 (7'b1001110),
+    .TX_MARGIN_FULL_1 (7'b1001001),
+    .TX_MARGIN_FULL_2 (7'b1000101),
+    .TX_MARGIN_FULL_3 (7'b1000010),
+    .TX_MARGIN_FULL_4 (7'b1000000),
+    .TX_MARGIN_LOW_0 (7'b1000110),
+    .TX_MARGIN_LOW_1 (7'b1000100),
+    .TX_MARGIN_LOW_2 (7'b1000010),
+    .TX_MARGIN_LOW_3 (7'b1000000),
+    .TX_MARGIN_LOW_4 (7'b1000000),
+    .TXGEARBOX_EN ("FALSE"),
+    .TXPCSRESET_TIME (5'b00001),
+    .TXPMARESET_TIME (5'b00001),
+    .TX_RXDETECT_CFG (14'h1832),
+    .TX_RXDETECT_REF (3'b100),
+    .CPLL_CFG (24'hBC07DC),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .CPLL_FBDIV_45 (5),
+    .CPLL_INIT_CFG (24'h00001E),
+    .CPLL_LOCK_CFG (16'h01E8),
+    .CPLL_REFCLK_DIV (1),
+    .RXOUT_DIV (RX_OUT_DIV),
+    .TXOUT_DIV (TX_OUT_DIV),
+    .SATA_CPLL_CFG ("VCO_3000MHZ"),
+    .RXDFELPMRESET_TIME (7'b0001111),
+    .RXLPM_HF_CFG (14'b00000011110000),
+    .RXLPM_LF_CFG (14'b00000011110000),
+    .RX_DFE_GAIN_CFG (23'h020FEA),
+    .RX_DFE_H2_CFG (12'b000000000000),
+    .RX_DFE_H3_CFG (12'b000001000000),
+    .RX_DFE_H4_CFG (11'b00011110000),
+    .RX_DFE_H5_CFG (11'b00011100000),
+    .RX_DFE_KL_CFG (13'b0000011111110),
+    .RX_DFE_LPM_CFG (16'h0954),
+    .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
+    .RX_DFE_UT_CFG (17'b10001111000000000),
+    .RX_DFE_VP_CFG (17'b00011111100000011),
+    .RX_CLKMUX_PD (1'b1),
+    .TX_CLKMUX_PD (1'b1),
+    .RX_INT_DATAWIDTH (1),
+    .TX_INT_DATAWIDTH (1),
+    .TX_QPI_STATUS_EN (1'b0),
+    .RX_DFE_KL_CFG2 (32'h3010D90C),
+    .RX_DFE_XYD_CFG (13'b0001100010000),
+    .TX_PREDRIVER_MODE (1'b0))
+  i_gtxe2_channel (
+    .CPLLFBCLKLOST (),
+    .CPLLLOCK (cpll_locked_s),
+    .CPLLLOCKDETCLK (up_clk),
+    .CPLLLOCKEN (1'd1),
+    .CPLLPD (1'b0),
+    .CPLLREFCLKLOST (),
+    .CPLLREFCLKSEL (3'b001),
+    .CPLLRESET (pll_rst),
+    .GTRSVD (16'b0000000000000000),
+    .PCSRSVDIN (16'b0000000000000000),
+    .PCSRSVDIN2 (5'b00000),
+    .PMARSVDIN (5'b00000),
+    .PMARSVDIN2 (5'b00000),
+    .TSTIN (20'b11111111111111111111),
+    .TSTOUT (),
+    .CLKRSVD (4'b0000),
+    .GTGREFCLK (1'd0),
+    .GTNORTHREFCLK0 (1'd0),
+    .GTNORTHREFCLK1 (1'd0),
+    .GTREFCLK0 (ref_clk),
+    .GTREFCLK1 (1'd0),
+    .GTSOUTHREFCLK0 (1'd0),
+    .GTSOUTHREFCLK1 (1'd0),
+    .DRPADDR (up_drp_addr_int[8:0]),
+    .DRPCLK (up_clk),
+    .DRPDI (up_drp_wdata_int),
+    .DRPDO (up_drp_rdata_s),
+    .DRPEN (up_drp_enb_int),
+    .DRPRDY (up_drp_ready_s),
+    .DRPWE (up_drp_wr_int),
+    .GTREFCLKMONITOR (),
+    .QPLLCLK (qpll_clk),
+    .QPLLREFCLK (qpll_ref_clk),
+    .RXSYSCLKSEL (rx_sys_clk_sel_s),
+    .TXSYSCLKSEL (tx_sys_clk_sel_s),
+    .DMONITOROUT (),
+    .TX8B10BEN (1'd1),
+    .LOOPBACK (3'd0),
+    .PHYSTATUS (),
+    .RXRATE (rx_rate),
+    .RXVALID (),
+    .RXPD (2'b00),
+    .TXPD (2'b00),
+    .SETERRSTATUS (1'd0),
+    .EYESCANRESET (1'd0),
+    .RXUSERRDY (rx_user_ready),
+    .EYESCANDATAERROR (),
+    .EYESCANMODE (1'd0),
+    .EYESCANTRIGGER (1'd0),
+    .RXCDRFREQRESET (1'd0),
+    .RXCDRHOLD (1'd0),
+    .RXCDRLOCK (),
+    .RXCDROVRDEN (1'd0),
+    .RXCDRRESET (1'd0),
+    .RXCDRRESETRSV (1'd0),
+    .RXCLKCORCNT (),
+    .RX8B10BEN (1'd1),
+    .RXUSRCLK (rx_clk),
+    .RXUSRCLK2 (rx_clk),
+    .RXDATA ({rx_data_open_s, rx_gt_data}),
+    .RXPRBSERR (),
+    .RXPRBSSEL (3'd0),
+    .RXPRBSCNTRESET (1'd0),
+    .RXDFEXYDEN (1'd0),
+    .RXDFEXYDHOLD (1'd0),
+    .RXDFEXYDOVRDEN (1'd0),
+    .RXDISPERR ({rx_disperr_open_s, rx_gt_disperr}),
+    .RXNOTINTABLE ({rx_notintable_open_s, rx_gt_notintable}),
+    .GTXRXP (rx_p),
+    .GTXRXN (rx_n),
+    .RXBUFRESET (1'd0),
+    .RXBUFSTATUS (),
+    .RXDDIEN (1'd0),
+    .RXDLYBYPASS (1'd1),
+    .RXDLYEN (1'd0),
+    .RXDLYOVRDEN (1'd0),
+    .RXDLYSRESET (1'd0),
+    .RXDLYSRESETDONE (),
+    .RXPHALIGN (1'd0),
+    .RXPHALIGNDONE (),
+    .RXPHALIGNEN (1'd0),
+    .RXPHDLYPD (1'd0),
+    .RXPHDLYRESET (1'd0),
+    .RXPHMONITOR (),
+    .RXPHOVRDEN (1'd0),
+    .RXPHSLIPMONITOR (),
+    .RXSTATUS (),
+    .RXBYTEISALIGNED (),
+    .RXBYTEREALIGN (),
+    .RXCOMMADET (),
+    .RXCOMMADETEN (1'd1),
+    .RXMCOMMAALIGNEN (rx_gt_calign),
+    .RXPCOMMAALIGNEN (rx_gt_calign),
+    .RXCHANBONDSEQ (),
+    .RXCHBONDEN (1'd0),
+    .RXCHBONDLEVEL (3'd0),
+    .RXCHBONDMASTER (1'd1),
+    .RXCHBONDO (),
+    .RXCHBONDSLAVE (1'd0),
+    .RXCHANISALIGNED (),
+    .RXCHANREALIGN (),
+    .RXDFEAGCHOLD (1'd0),
+    .RXDFEAGCOVRDEN (1'd0),
+    .RXDFECM1EN (1'd0),
+    .RXDFELFHOLD (1'd0),
+    .RXDFELFOVRDEN (1'd1),
+    .RXDFELPMRESET (1'd0),
+    .RXDFETAP2HOLD (1'd0),
+    .RXDFETAP2OVRDEN (1'd0),
+    .RXDFETAP3HOLD (1'd0),
+    .RXDFETAP3OVRDEN (1'd0),
+    .RXDFETAP4HOLD (1'd0),
+    .RXDFETAP4OVRDEN (1'd0),
+    .RXDFETAP5HOLD (1'd0),
+    .RXDFETAP5OVRDEN (1'd0),
+    .RXDFEUTHOLD (1'd0),
+    .RXDFEUTOVRDEN (1'd0),
+    .RXDFEVPHOLD (1'd0),
+    .RXDFEVPOVRDEN (1'd0),
+    .RXDFEVSEN (1'd0),
+    .RXLPMLFKLOVRDEN (1'd0),
+    .RXMONITOROUT (),
+    .RXMONITORSEL (2'd0),
+    .RXOSHOLD (1'd0),
+    .RXOSOVRDEN (1'd0),
+    .RXLPMHFHOLD (1'd0),
+    .RXLPMHFOVRDEN (1'd0),
+    .RXLPMLFHOLD (1'd0),
+    .RXRATEDONE (),
+    .RXOUTCLK (rx_out_clk),
+    .RXOUTCLKFABRIC (),
+    .RXOUTCLKPCS (),
+    .RXOUTCLKSEL (rx_out_clk_sel),
+    .RXDATAVALID (),
+    .RXHEADER (),
+    .RXHEADERVALID (),
+    .RXSTARTOFSEQ (),
+    .RXGEARBOXSLIP (1'd0),
+    .GTRXRESET (rx_rst),
+    .RXOOBRESET (1'd0),
+    .RXPCSRESET (1'd0),
+    .RXPMARESET (1'd0),
+    .RXLPMEN (rx_lpm_dfe_n),
+    .RXCOMSASDET (),
+    .RXCOMWAKEDET (),
+    .RXCOMINITDET (),
+    .RXELECIDLE (),
+    .RXELECIDLEMODE (2'b10),
+    .RXPOLARITY (1'd0),
+    .RXSLIDE (1'd0),
+    .RXCHARISCOMMA (),
+    .RXCHARISK ({rx_charisk_open_s, rx_gt_charisk}),
+    .RXCHBONDI (5'd0),
+    .RXRESETDONE (rx_rst_done),
+    .RXQPIEN (1'd0),
+    .RXQPISENN (),
+    .RXQPISENP (),
+    .TXPHDLYTSTCLK (1'd0),
+    .TXPOSTCURSOR (5'd0),
+    .TXPOSTCURSORINV (1'd0),
+    .TXPRECURSOR (5'd0),
+    .TXPRECURSORINV (1'd0),
+    .TXQPIBIASEN (1'd0),
+    .TXQPISTRONGPDOWN (1'd0),
+    .TXQPIWEAKPUP (1'd0),
+    .CFGRESET (1'd0),
+    .GTTXRESET (tx_rst),
+    .PCSRSVDOUT (),
+    .TXUSERRDY (tx_user_ready),
+    .GTRESETSEL (1'd0),
+    .RESETOVRD (1'd0),
+    .TXCHARDISPMODE (8'd0),
+    .TXCHARDISPVAL (8'd0),
+    .TXUSRCLK (tx_clk),
+    .TXUSRCLK2 (tx_clk),
+    .TXELECIDLE (1'd0),
+    .TXMARGIN (3'd0),
+    .TXRATE (tx_rate),
+    .TXSWING (1'd0),
+    .TXPRBSFORCEERR (1'd0),
+    .TXDLYBYPASS (1'd1),
+    .TXDLYEN (1'd0),
+    .TXDLYHOLD (1'd0),
+    .TXDLYOVRDEN (1'd0),
+    .TXDLYSRESET (1'd0),
+    .TXDLYSRESETDONE (),
+    .TXDLYUPDOWN (1'd0),
+    .TXPHALIGN (1'd0),
+    .TXPHALIGNDONE (),
+    .TXPHALIGNEN (1'd0),
+    .TXPHDLYPD (1'd0),
+    .TXPHDLYRESET (1'd0),
+    .TXPHINIT (1'd0),
+    .TXPHINITDONE (),
+    .TXPHOVRDEN (1'd0),
+    .TXBUFSTATUS (),
+    .TXBUFDIFFCTRL (3'b100),
+    .TXDEEMPH (1'd0),
+    .TXDIFFCTRL (4'b1000),
+    .TXDIFFPD (1'd0),
+    .TXINHIBIT (1'd0),
+    .TXMAINCURSOR (7'b0000000),
+    .TXPISOPD (1'd0),
+    .TXDATA ({32'd0, tx_gt_data}),
+    .GTXTXP (tx_p),
+    .GTXTXN (tx_n),
+    .TXOUTCLK (tx_out_clk),
+    .TXOUTCLKFABRIC (),
+    .TXOUTCLKPCS (),
+    .TXOUTCLKSEL (tx_out_clk_sel),
+    .TXRATEDONE (),
+    .TXCHARISK ({4'd0, tx_gt_charisk}),
+    .TXGEARBOXREADY (),
+    .TXHEADER (3'd0),
+    .TXSEQUENCE (7'd0),
+    .TXSTARTSEQ (1'd0),
+    .TXPCSRESET (1'd0),
+    .TXPMARESET (1'd0),
+    .TXRESETDONE (tx_rst_done),
+    .TXCOMFINISH (),
+    .TXCOMINIT (1'd0),
+    .TXCOMSAS (1'd0),
+    .TXCOMWAKE (1'd0),
+    .TXPDELECIDLEMODE (1'd0),
+    .TXPOLARITY (1'd0),
+    .TXDETECTRX (1'd0),
+    .TX8B10BBYPASS (8'd0),
+    .TXPRBSSEL (3'd0),
+    .TXQPISENP (),
+    .TXQPISENN ());
+  end
+  endgenerate
+
+  generate
+  if (GTH_OR_GTX_N == 1) begin
+  assign rx_sys_clk_sel_s = (rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
+  assign tx_sys_clk_sel_s = (tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
+  assign rx_pll_clk_sel_s = rx_sys_clk_sel;
+  assign tx_pll_clk_sel_s = tx_sys_clk_sel;
+  end
+  endgenerate
+
+  generate
+  if (GTH_OR_GTX_N == 1) begin
+  GTHE3_CHANNEL #(
+    .ACJTAG_DEBUG_MODE (1'b0),
+    .ACJTAG_MODE (1'b0),
+    .ACJTAG_RESET (1'b0),
+    .ADAPT_CFG0 (16'b1111100000000000),
+    .ADAPT_CFG1 (16'b0000000000000000),
+    .ALIGN_COMMA_DOUBLE ("FALSE"),
+    .ALIGN_COMMA_ENABLE (10'b1111111111),
+    .ALIGN_COMMA_WORD (1),
+    .ALIGN_MCOMMA_DET ("TRUE"),
+    .ALIGN_MCOMMA_VALUE (10'b1010000011),
+    .ALIGN_PCOMMA_DET ("TRUE"),
+    .ALIGN_PCOMMA_VALUE (10'b0101111100),
+    .A_RXOSCALRESET (1'b0),
+    .A_RXPROGDIVRESET (1'b0),
+    .A_TXPROGDIVRESET (1'b0),
+    .CBCC_DATA_SOURCE_SEL ("DECODED"),
+    .CDR_SWAP_MODE_EN (1'b0),
+    .CHAN_BOND_KEEP_ALIGN ("FALSE"),
+    .CHAN_BOND_MAX_SKEW (1),
+    .CHAN_BOND_SEQ_1_1 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_2 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_3 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_4 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_ENABLE (4'b1111),
+    .CHAN_BOND_SEQ_2_1 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_2 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_3 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_4 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_ENABLE (4'b1111),
+    .CHAN_BOND_SEQ_2_USE ("FALSE"),
+    .CHAN_BOND_SEQ_LEN (1),
+    .CLK_CORRECT_USE ("FALSE"),
+    .CLK_COR_KEEP_IDLE ("FALSE"),
+    .CLK_COR_MAX_LAT (12),
+    .CLK_COR_MIN_LAT (8),
+    .CLK_COR_PRECEDENCE ("TRUE"),
+    .CLK_COR_REPEAT_WAIT (0),
+    .CLK_COR_SEQ_1_1 (10'b0100000000),
+    .CLK_COR_SEQ_1_2 (10'b0100000000),
+    .CLK_COR_SEQ_1_3 (10'b0100000000),
+    .CLK_COR_SEQ_1_4 (10'b0100000000),
+    .CLK_COR_SEQ_1_ENABLE (4'b1111),
+    .CLK_COR_SEQ_2_1 (10'b0100000000),
+    .CLK_COR_SEQ_2_2 (10'b0100000000),
+    .CLK_COR_SEQ_2_3 (10'b0100000000),
+    .CLK_COR_SEQ_2_4 (10'b0100000000),
+    .CLK_COR_SEQ_2_ENABLE (4'b1111),
+    .CLK_COR_SEQ_2_USE ("FALSE"),
+    .CLK_COR_SEQ_LEN (1),
+    .CPLL_CFG0 (16'b0110011111111010),
+    .CPLL_CFG1 (16'b1010010010010100),
+    .CPLL_CFG2 (16'b1111000000000111),
+    .CPLL_CFG3 (6'b000000),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .CPLL_FBDIV_45 (5),
+    .CPLL_INIT_CFG0 (16'b0000000000011110),
+    .CPLL_INIT_CFG1 (8'b00000000),
+    .CPLL_LOCK_CFG (16'b0000000111101000),
+    .CPLL_REFCLK_DIV (1),
+    .DDI_CTRL (2'b00),
+    .DDI_REALIGN_WAIT (15),
+    .DEC_MCOMMA_DETECT ("TRUE"),
+    .DEC_PCOMMA_DETECT ("TRUE"),
+    .DEC_VALID_COMMA_ONLY ("FALSE"),
+    .DFE_D_X_REL_POS (1'b0),
+    .DFE_VCM_COMP_EN (1'b0),
+    .DMONITOR_CFG0 (10'b0000000000),
+    .DMONITOR_CFG1 (8'b00000000),
+    .ES_CLK_PHASE_SEL (1'b0),
+    .ES_CONTROL (6'b000000),
+    .ES_ERRDET_EN ("TRUE"),
+    .ES_EYE_SCAN_EN ("TRUE"),
+    .ES_HORZ_OFFSET (12'b000000000000),
+    .ES_PMA_CFG (10'b0000000000),
+    .ES_PRESCALE (5'b00000),
+    .ES_QUALIFIER0 (16'b0000000000000000),
+    .ES_QUALIFIER1 (16'b0000000000000000),
+    .ES_QUALIFIER2 (16'b0000000000000000),
+    .ES_QUALIFIER3 (16'b0000000000000000),
+    .ES_QUALIFIER4 (16'b0000000000000000),
+    .ES_QUAL_MASK0 (16'b0000000000000000),
+    .ES_QUAL_MASK1 (16'b0000000000000000),
+    .ES_QUAL_MASK2 (16'b0000000000000000),
+    .ES_QUAL_MASK3 (16'b0000000000000000),
+    .ES_QUAL_MASK4 (16'b0000000000000000),
+    .ES_SDATA_MASK0 (16'b0000000000000000),
+    .ES_SDATA_MASK1 (16'b0000000000000000),
+    .ES_SDATA_MASK2 (16'b0000000000000000),
+    .ES_SDATA_MASK3 (16'b0000000000000000),
+    .ES_SDATA_MASK4 (16'b0000000000000000),
+    .EVODD_PHI_CFG (11'b00000000000),
+    .EYE_SCAN_SWAP_EN (1'b0),
+    .FTS_DESKEW_SEQ_ENABLE (4'b1111),
+    .FTS_LANE_DESKEW_CFG (4'b1111),
+    .FTS_LANE_DESKEW_EN ("FALSE"),
+    .GEARBOX_MODE (5'b00000),
+    .GM_BIAS_SELECT (1'b0),
+    .LOCAL_MASTER (1'b1),
+    .OOBDIVCTL (2'b00),
+    .OOB_PWRUP (1'b0),
+    .PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
+    .PCI3_PIPE_RX_ELECIDLE (1'b0),
+    .PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
+    .PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
+    .PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
+    .PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
+    .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
+    .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
+    .PCI3_RX_FIFO_DISABLE (1'b0),
+    .PCIE_BUFG_DIV_CTRL (16'b0011010100001001),
+    .PCIE_RXPCS_CFG_GEN3 (16'b0000001010100100),
+    .PCIE_RXPMA_CFG (16'b0000000000001010),
+    .PCIE_TXPCS_CFG_GEN3 (16'b0010010010100000),
+    .PCIE_TXPMA_CFG (16'b0000000000001010),
+    .PCS_PCIE_EN ("FALSE"),
+    .PCS_RSVD0 (16'b0000000000000000),
+    .PCS_RSVD1 (3'b000),
+    .PD_TRANS_TIME_FROM_P2 (12'b000000111100),
+    .PD_TRANS_TIME_NONE_P2 (8'b00011001),
+    .PD_TRANS_TIME_TO_P2 (8'b01100100),
+    .PLL_SEL_MODE_GEN12 (2'b11),
+    .PLL_SEL_MODE_GEN3 (2'b11),
+    .PMA_RSV1 (16'b0001000000000000),
+    .PROCESS_PAR (3'b010),
+    .RATE_SW_USE_DRP (1'b0),
+    .RESET_POWERSAVE_DISABLE (1'b0),
+    .RXBUFRESET_TIME (5'b00011),
+    .RXBUF_ADDR_MODE ("FAST"),
+    .RXBUF_EIDLE_HI_CNT (4'b1000),
+    .RXBUF_EIDLE_LO_CNT (4'b0000),
+    .RXBUF_EN ("TRUE"),
+    .RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
+    .RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
+    .RXBUF_RESET_ON_EIDLE ("FALSE"),
+    .RXBUF_RESET_ON_RATE_CHANGE ("FALSE"),
+    .RXBUF_THRESH_OVFLW (57),
+    .RXBUF_THRESH_OVRD ("TRUE"),
+    .RXBUF_THRESH_UNDFLW (3),
+    .RXCDRFREQRESET_TIME (5'b00001),
+    .RXCDRPHRESET_TIME (5'b00001),
+    .RXCDR_CFG0 (16'b0000000000000000),
+    .RXCDR_CFG0_GEN3 (16'b0000000000000000),
+    .RXCDR_CFG1 (16'b0000000000000000),
+    .RXCDR_CFG1_GEN3 (16'b0000000000000000),
+    .RXCDR_CFG2 (16'b0000011101100110),
+    .RXCDR_CFG2_GEN3 (16'b0000011101100110),
+    .RXCDR_CFG3 (16'b0000000000000000),
+    .RXCDR_CFG3_GEN3 (16'b0000000000000000),
+    .RXCDR_CFG4 (16'b0000000000000000),
+    .RXCDR_CFG4_GEN3 (16'b0000000000000000),
+    .RXCDR_CFG5 (16'b0000000000000000),
+    .RXCDR_CFG5_GEN3 (16'b0000000000000000),
+    .RXCDR_FR_RESET_ON_EIDLE (1'b0),
+    .RXCDR_HOLD_DURING_EIDLE (1'b0),
+    .RXCDR_LOCK_CFG0 (16'b0100010010000000),
+    .RXCDR_LOCK_CFG1 (16'b0101111111111111),
+    .RXCDR_LOCK_CFG2 (16'b0111011111000011),
+    .RXCDR_PH_RESET_ON_EIDLE (1'b0),
+    .RXCFOK_CFG0 (16'b0100000000000000),
+    .RXCFOK_CFG1 (16'b0000000001100101),
+    .RXCFOK_CFG2 (16'b0000000000101110),
+    .RXDFELPMRESET_TIME (7'b0001111),
+    .RXDFELPM_KL_CFG0 (16'b0000000000000000),
+    .RXDFELPM_KL_CFG1 (16'b0000000000000010),
+    .RXDFELPM_KL_CFG2 (16'b0000000000000000),
+    .RXDFE_CFG0 (16'b0000101000000000),
+    .RXDFE_CFG1 (16'b0000000000000000),
+    .RXDFE_GC_CFG0 (16'b0000000000000000),
+    .RXDFE_GC_CFG1 (16'b0111100001100000),
+    .RXDFE_GC_CFG2 (16'b0000000000000000),
+    .RXDFE_H2_CFG0 (16'b0000000000000000),
+    .RXDFE_H2_CFG1 (16'b0000000000000000),
+    .RXDFE_H3_CFG0 (16'b0100000000000000),
+    .RXDFE_H3_CFG1 (16'b0000000000000000),
+    .RXDFE_H4_CFG0 (16'b0010000000000000),
+    .RXDFE_H4_CFG1 (16'b0000000000000011),
+    .RXDFE_H5_CFG0 (16'b0010000000000000),
+    .RXDFE_H5_CFG1 (16'b0000000000000011),
+    .RXDFE_H6_CFG0 (16'b0010000000000000),
+    .RXDFE_H6_CFG1 (16'b0000000000000000),
+    .RXDFE_H7_CFG0 (16'b0010000000000000),
+    .RXDFE_H7_CFG1 (16'b0000000000000000),
+    .RXDFE_H8_CFG0 (16'b0010000000000000),
+    .RXDFE_H8_CFG1 (16'b0000000000000000),
+    .RXDFE_H9_CFG0 (16'b0010000000000000),
+    .RXDFE_H9_CFG1 (16'b0000000000000000),
+    .RXDFE_HA_CFG0 (16'b0010000000000000),
+    .RXDFE_HA_CFG1 (16'b0000000000000000),
+    .RXDFE_HB_CFG0 (16'b0010000000000000),
+    .RXDFE_HB_CFG1 (16'b0000000000000000),
+    .RXDFE_HC_CFG0 (16'b0000000000000000),
+    .RXDFE_HC_CFG1 (16'b0000000000000000),
+    .RXDFE_HD_CFG0 (16'b0000000000000000),
+    .RXDFE_HD_CFG1 (16'b0000000000000000),
+    .RXDFE_HE_CFG0 (16'b0000000000000000),
+    .RXDFE_HE_CFG1 (16'b0000000000000000),
+    .RXDFE_HF_CFG0 (16'b0000000000000000),
+    .RXDFE_HF_CFG1 (16'b0000000000000000),
+    .RXDFE_OS_CFG0 (16'b1000000000000000),
+    .RXDFE_OS_CFG1 (16'b0000000000000000),
+    .RXDFE_UT_CFG0 (16'b1000000000000000),
+    .RXDFE_UT_CFG1 (16'b0000000000000011),
+    .RXDFE_VP_CFG0 (16'b1010101000000000),
+    .RXDFE_VP_CFG1 (16'b0000000000110011),
+    .RXDLY_CFG (16'b0000000000011111),
+    .RXDLY_LCFG (16'b0000000000110000),
+    .RXELECIDLE_CFG ("Sigcfg_4"),
+    .RXGBOX_FIFO_INIT_RD_ADDR (4),
+    .RXGEARBOX_EN ("FALSE"),
+    .RXISCANRESET_TIME (5'b00001),
+    .RXLPM_CFG (16'b0000000000000000),
+    .RXLPM_GC_CFG (16'b0000000000000000),
+    .RXLPM_KH_CFG0 (16'b0000000000000000),
+    .RXLPM_KH_CFG1 (16'b0000000000000010),
+    .RXLPM_OS_CFG0 (16'b1000000000000000),
+    .RXLPM_OS_CFG1 (16'b0000000000000010),
+    .RXOOB_CFG (9'b000000110),
+    .RXOOB_CLK_CFG ("PMA"),
+    .RXOSCALRESET_TIME (5'b00011),
+    .RXOUT_DIV (RX_OUT_DIV),
+    .RXPCSRESET_TIME (5'b00011),
+    .RXPHBEACON_CFG (16'b0000000000000000),
+    .RXPHDLY_CFG (16'b0010000000100000),
+    .RXPHSAMP_CFG (16'b0010000100000000),
+    .RXPHSLIP_CFG (16'b0110011000100010),
+    .RXPH_MONITOR_SEL (5'b00000),
+    .RXPI_CFG0 (2'b00),
+    .RXPI_CFG1 (2'b00),
+    .RXPI_CFG2 (2'b00),
+    .RXPI_CFG3 (2'b00),
+    .RXPI_CFG4 (1'b0),
+    .RXPI_CFG5 (1'b1),
+    .RXPI_CFG6 (3'b000),
+    .RXPI_LPM (1'b0),
+    .RXPI_VREFSEL (1'b0),
+    .RXPMACLK_SEL ("DATA"),
+    .RXPMARESET_TIME (5'b00011),
+    .RXPRBS_ERR_LOOPBACK (1'b0),
+    .RXPRBS_LINKACQ_CNT (15),
+    .RXSLIDE_AUTO_WAIT (7),
+    .RXSLIDE_MODE ("OFF"),
+    .RXSYNC_MULTILANE (1'b1),
+    .RXSYNC_OVRD (1'b0),
+    .RXSYNC_SKIP_DA (1'b0),
+    .RX_AFE_CM_EN (1'b0),
+    .RX_BIAS_CFG0 (16'b0000101010110100),
+    .RX_BUFFER_CFG (6'b000000),
+    .RX_CAPFF_SARC_ENB (1'b0),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKMUX_EN (1'b1),
+    .RX_CLK_SLIP_OVRD (5'b00000),
+    .RX_CM_BUF_CFG (4'b1010),
+    .RX_CM_BUF_PD (1'b0),
+    .RX_CM_SEL (2'b11),
+    .RX_CM_TRIM (4'b1010),
+    .RX_CTLE3_LPF (8'b00000001),
+    .RX_DATA_WIDTH (40),
+    .RX_DDI_SEL (6'b000000),
+    .RX_DEFER_RESET_BUF_EN ("TRUE"),
+    .RX_DFELPM_CFG0 (4'b0110),
+    .RX_DFELPM_CFG1 (1'b1),
+    .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
+    .RX_DFE_AGC_CFG0 (2'b10),
+    .RX_DFE_AGC_CFG1 (3'b100),
+    .RX_DFE_KL_LPM_KH_CFG0 (2'b01),
+    .RX_DFE_KL_LPM_KH_CFG1 (3'b100),
+    .RX_DFE_KL_LPM_KL_CFG0 (2'b01),
+    .RX_DFE_KL_LPM_KL_CFG1 (3'b100),
+    .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
+    .RX_DISPERR_SEQ_MATCH ("TRUE"),
+    .RX_DIVRESET_TIME (5'b00001),
+    .RX_EN_HI_LR (1'b1),
+    .RX_EYESCAN_VS_CODE (7'b0000000),
+    .RX_EYESCAN_VS_NEG_DIR (1'b0),
+    .RX_EYESCAN_VS_RANGE (2'b00),
+    .RX_EYESCAN_VS_UT_SIGN (1'b0),
+    .RX_FABINT_USRCLK_FLOP (1'b0),
+    .RX_INT_DATAWIDTH (1),
+    .RX_PMA_POWER_SAVE (1'b0),
+    .RX_PROGDIV_CFG (20.0),
+    .RX_SAMPLE_PERIOD (3'b101),
+    .RX_SIG_VALID_DLY (11),
+    .RX_SUM_DFETAPREP_EN (1'b0),
+    .RX_SUM_IREF_TUNE (4'b0000),
+    .RX_SUM_RES_CTRL (2'b00),
+    .RX_SUM_VCMTUNE (4'b0000),
+    .RX_SUM_VCM_OVWR (1'b0),
+    .RX_SUM_VREF_TUNE (3'b000),
+    .RX_TUNE_AFE_OS (2'b10),
+    .RX_WIDEMODE_CDR (1'b1),
+    .RX_XCLK_SEL ("RXDES"),
+    .SAS_MAX_COM (64),
+    .SAS_MIN_COM (36),
+    .SATA_BURST_SEQ_LEN (4'b1111),
+    .SATA_BURST_VAL (3'b100),
+    .SATA_CPLL_CFG ("VCO_3000MHZ"),
+    .SATA_EIDLE_VAL (3'b100),
+    .SATA_MAX_BURST (8),
+    .SATA_MAX_INIT (21),
+    .SATA_MAX_WAKE (7),
+    .SATA_MIN_BURST (4),
+    .SATA_MIN_INIT (12),
+    .SATA_MIN_WAKE (4),
+    .SHOW_REALIGN_COMMA ("TRUE"),
+    .SIM_RECEIVER_DETECT_PASS ("TRUE"),
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_TX_EIDLE_DRIVE_LEVEL (1'b0),
+    .SIM_VERSION (2),
+    .TAPDLY_SET_TX (2'b00),
+    .TEMPERATUR_PAR (4'b0010),
+    .TERM_RCAL_CFG (15'b100001000010000),
+    .TERM_RCAL_OVRD (3'b000),
+    .TRANS_TIME_RATE (8'b00001110),
+    .TST_RSV0 (8'b00000000),
+    .TST_RSV1 (8'b00000000),
+    .TXBUF_EN ("TRUE"),
+    .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
+    .TXDLY_CFG (16'b0000000000001001),
+    .TXDLY_LCFG (16'b0000000001010000),
+    .TXDRVBIAS_N (4'b1010),
+    .TXDRVBIAS_P (4'b1010),
+    .TXFIFO_ADDR_CFG ("LOW"),
+    .TXGBOX_FIFO_INIT_RD_ADDR (4),
+    .TXGEARBOX_EN ("FALSE"),
+    .TXOUT_DIV (TX_OUT_DIV),
+    .TXPCSRESET_TIME (5'b00011),
+    .TXPHDLY_CFG0 (16'b0010000000100000),
+    .TXPHDLY_CFG1 (16'b0000000011010101),
+    .TXPH_CFG (16'b0000100110000000),
+    .TXPH_MONITOR_SEL (5'b00000),
+    .TXPI_CFG0 (2'b00),
+    .TXPI_CFG1 (2'b00),
+    .TXPI_CFG2 (2'b00),
+    .TXPI_CFG3 (1'b0),
+    .TXPI_CFG4 (1'b1),
+    .TXPI_CFG5 (3'b000),
+    .TXPI_GRAY_SEL (1'b0),
+    .TXPI_INVSTROBE_SEL (1'b0),
+    .TXPI_LPM (1'b0),
+    .TXPI_PPMCLK_SEL ("TXUSRCLK2"),
+    .TXPI_PPM_CFG (8'b00000000),
+    .TXPI_SYNFREQ_PPM (3'b000),
+    .TXPI_VREFSEL (1'b0),
+    .TXPMARESET_TIME (5'b00011),
+    .TXSYNC_MULTILANE (1'b1),
+    .TXSYNC_OVRD (1'b0),
+    .TXSYNC_SKIP_DA (1'b0),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKMUX_EN (1'b1),
+    .TX_DATA_WIDTH (40),
+    .TX_DCD_CFG (6'b000010),
+    .TX_DCD_EN (1'b0),
+    .TX_DEEMPH0 (6'b000000),
+    .TX_DEEMPH1 (6'b000000),
+    .TX_DIVRESET_TIME (5'b00001),
+    .TX_DRIVE_MODE ("DIRECT"),
+    .TX_EIDLE_ASSERT_DELAY (3'b100),
+    .TX_EIDLE_DEASSERT_DELAY (3'b011),
+    .TX_EML_PHI_TUNE (1'b0),
+    .TX_FABINT_USRCLK_FLOP (1'b0),
+    .TX_IDLE_DATA_ZERO (1'b0),
+    .TX_INT_DATAWIDTH (1),
+    .TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
+    .TX_MAINCURSOR_SEL (1'b0),
+    .TX_MARGIN_FULL_0 (7'b1001111),
+    .TX_MARGIN_FULL_1 (7'b1001110),
+    .TX_MARGIN_FULL_2 (7'b1001100),
+    .TX_MARGIN_FULL_3 (7'b1001010),
+    .TX_MARGIN_FULL_4 (7'b1001000),
+    .TX_MARGIN_LOW_0 (7'b1000110),
+    .TX_MARGIN_LOW_1 (7'b1000101),
+    .TX_MARGIN_LOW_2 (7'b1000011),
+    .TX_MARGIN_LOW_3 (7'b1000010),
+    .TX_MARGIN_LOW_4 (7'b1000000),
+    .TX_MODE_SEL (3'b000),
+    .TX_PMADATA_OPT (1'b0),
+    .TX_PMA_POWER_SAVE (1'b0),
+    .TX_PROGCLK_SEL ("PREPI"),
+    .TX_PROGDIV_CFG (20.0),
+    .TX_QPI_STATUS_EN (1'b0),
+    .TX_RXDETECT_CFG (14'b00000000110010),
+    .TX_RXDETECT_REF (3'b100),
+    .TX_SAMPLE_PERIOD (3'b101),
+    .TX_SARC_LPBK_ENB (1'b0),                   
+    .TX_XCLK_SEL ("TXOUT"),                     
+    .USE_PCS_CLK_PHASE_SEL (1'b0),              
+    .WB_MODE (2'b00))                                                                        
+  i_gthe3_channel (                                                            
+    .CFGRESET (1'd0),
+    .CLKRSVD0 (1'd0),
+    .CLKRSVD1 (1'd0),
+    .CPLLLOCKDETCLK (up_clk),
+    .CPLLLOCKEN (1'd1),
+    .CPLLPD (1'b0),
+    .CPLLREFCLKSEL (3'b001),
+    .CPLLRESET (pll_rst),
+    .DMONFIFORESET (1'd0),
+    .DMONITORCLK (1'd0),
+    .DRPADDR (up_drp_addr_int[8:0]),
+    .DRPCLK (up_clk),
+    .DRPDI (up_drp_wdata_int),
+    .DRPEN (up_drp_enb_int),
+    .DRPWE (up_drp_wr_int),
+    .EVODDPHICALDONE (1'd0),
+    .EVODDPHICALSTART (1'd0),
+    .EVODDPHIDRDEN (1'd0),
+    .EVODDPHIDWREN (1'd0),
+    .EVODDPHIXRDEN (1'd0),
+    .EVODDPHIXWREN (1'd0),
+    .EYESCANMODE (1'd0),
+    .EYESCANRESET (1'd0),
+    .EYESCANTRIGGER (1'd0),
+    .GTGREFCLK (1'd0),
+    .GTHRXN (rx_n),
+    .GTHRXP (rx_p),
+    .GTNORTHREFCLK0 (1'd0),
+    .GTNORTHREFCLK1 (1'd0),
+    .GTREFCLK0 (ref_clk),
+    .GTREFCLK1 (1'd0),
+    .GTRESETSEL (1'd0),
+    .GTRSVD (15'd0),
+    .GTRXRESET (rx_rst),
+    .GTSOUTHREFCLK0 (1'd0),
+    .GTSOUTHREFCLK1 (1'd0),
+    .GTTXRESET (tx_rst),
+    .LOOPBACK (3'd0),
+    .LPBKRXTXSEREN (1'd0),
+    .LPBKTXRXSEREN (1'd0),
+    .PCIEEQRXEQADAPTDONE (1'd0),
+    .PCIERSTIDLE (1'd0),
+    .PCIERSTTXSYNCSTART (1'd0),
+    .PCIEUSERRATEDONE (1'd0),
+    .PCSRSVDIN (16'd0),
+    .PCSRSVDIN2 (5'd0),
+    .PMARSVDIN (5'd0),
+    .QPLL0CLK (qpll_clk),
+    .QPLL0REFCLK (qpll_ref_clk),
+    .QPLL1CLK (1'd0),
+    .QPLL1REFCLK (1'd0),
+    .RESETOVRD (1'd0),
+    .RSTCLKENTX (1'd0),
+    .RXBUFRESET (1'd0),
+    .RXCDRFREQRESET (1'd0),
+    .RXCDRHOLD (1'd0),
+    .RXCDROVRDEN (1'd0),
+    .RXCDRRESET (1'd0),
+    .RXCDRRESETRSV (1'd0),
+    .RXCHBONDEN (1'd0),
+    .RXCHBONDI (5'd0),
+    .RXCHBONDLEVEL (2'd0),
+    .RXCHBONDMASTER (1'd0),
+    .RXCHBONDSLAVE (1'd0),
+    .RXCOMMADETEN (1'd1),
+    .RXDFEAGCCTRL (2'b01),
+    .RXDFEAGCHOLD (1'd0),
+    .RXDFEAGCOVRDEN (1'd0),
+    .RXDFELFHOLD (1'd0),
+    .RXDFELFOVRDEN (1'd0),
+    .RXDFELPMRESET (1'd0),
+    .RXDFETAP10HOLD (1'd0),
+    .RXDFETAP10OVRDEN (1'd0),
+    .RXDFETAP11HOLD (1'd0),
+    .RXDFETAP11OVRDEN (1'd0),
+    .RXDFETAP12HOLD (1'd0),
+    .RXDFETAP12OVRDEN (1'd0),
+    .RXDFETAP13HOLD (1'd0),
+    .RXDFETAP13OVRDEN (1'd0),
+    .RXDFETAP14HOLD (1'd0),
+    .RXDFETAP14OVRDEN (1'd0),
+    .RXDFETAP15HOLD (1'd0),
+    .RXDFETAP15OVRDEN (1'd0),
+    .RXDFETAP2HOLD (1'd0),
+    .RXDFETAP2OVRDEN (1'd0),
+    .RXDFETAP3HOLD (1'd0),
+    .RXDFETAP3OVRDEN (1'd0),
+    .RXDFETAP4HOLD (1'd0),
+    .RXDFETAP4OVRDEN (1'd0),
+    .RXDFETAP5HOLD (1'd0),
+    .RXDFETAP5OVRDEN (1'd0),
+    .RXDFETAP6HOLD (1'd0),
+    .RXDFETAP6OVRDEN (1'd0),
+    .RXDFETAP7HOLD (1'd0),
+    .RXDFETAP7OVRDEN (1'd0),
+    .RXDFETAP8HOLD (1'd0),
+    .RXDFETAP8OVRDEN (1'd0),
+    .RXDFETAP9HOLD (1'd0),
+    .RXDFETAP9OVRDEN (1'd0),
+    .RXDFEUTHOLD (1'd0),
+    .RXDFEUTOVRDEN (1'd0),
+    .RXDFEVPHOLD (1'd0),
+    .RXDFEVPOVRDEN (1'd0),
+    .RXDFEVSEN (1'd0),
+    .RXDFEXYDEN (1'd1),
+    .RXDLYBYPASS (1'd1),
+    .RXDLYEN (1'd0),
+    .RXDLYOVRDEN (1'd0),
+    .RXDLYSRESET (1'd0),
+    .RXELECIDLEMODE (2'b11),
+    .RXGEARBOXSLIP (1'd0),
+    .RXLATCLK (1'd0),
+    .RXLPMEN (rx_lpm_dfe_n),
+    .RXLPMGCHOLD (1'd0),
+    .RXLPMGCOVRDEN (1'd0),
+    .RXLPMHFHOLD (1'd0),
+    .RXLPMHFOVRDEN (1'd0),
+    .RXLPMLFHOLD (1'd0),
+    .RXLPMLFKLOVRDEN (1'd0),
+    .RXLPMOSHOLD (1'd0),
+    .RXLPMOSOVRDEN (1'd0),
+    .RXMCOMMAALIGNEN (rx_gt_calign),
+    .RXMONITORSEL (2'd0),
+    .RXOOBRESET (1'd0),
+    .RXOSCALRESET (1'd0),
+    .RXOSHOLD (1'd0),
+    .RXOSINTCFG (4'b1101),
+    .RXOSINTEN (1'd1),
+    .RXOSINTHOLD (1'd0),
+    .RXOSINTOVRDEN (1'd0),
+    .RXOSINTSTROBE (1'd0),
+    .RXOSINTTESTOVRDEN (1'd0),
+    .RXOSOVRDEN (1'd0),
+    .RXOUTCLKSEL (rx_out_clk_sel),
+    .RXPCOMMAALIGNEN (rx_gt_calign),
+    .RXPCSRESET (1'd0),
+    .RXPD (2'd0),
+    .RXPHALIGN (1'd0),
+    .RXPHALIGNEN (1'd0),
+    .RXPHDLYPD (1'd1),
+    .RXPHDLYRESET (1'd0),
+    .RXPHOVRDEN (1'd0),
+    .RXPLLCLKSEL (rx_pll_clk_sel_s),
+    .RXPMARESET (1'd0),
+    .RXPOLARITY (1'd0),
+    .RXPRBSCNTRESET (1'd0),
+    .RXPRBSSEL (4'd0),
+    .RXPROGDIVRESET (1'd0),
+    .RXQPIEN (1'd0),
+    .RXRATE (rx_rate),
+    .RXRATEMODE (1'd0),
+    .RXSLIDE (1'd0),
+    .RXSLIPOUTCLK (1'd0),
+    .RXSLIPPMA (1'd0),
+    .RXSYNCALLIN (1'd0),
+    .RXSYNCIN (1'd0),
+    .RXSYNCMODE (1'd0),
+    .RXSYSCLKSEL (rx_sys_clk_sel_s),
+    .RXUSERRDY (rx_user_ready),
+    .RXUSRCLK (rx_clk),
+    .RXUSRCLK2 (rx_clk),
+    .RX8B10BEN (1'd1),
+    .SIGVALIDCLK (1'd0),
+    .TSTIN (20'd0),
+    .TXBUFDIFFCTRL (3'd0),
+    .TXCOMINIT (1'd0),
+    .TXCOMSAS (1'd0),
+    .TXCOMWAKE (1'd0),
+    .TXCTRL0 (16'd0),
+    .TXCTRL1 (16'd0),
+    .TXCTRL2 ({4'd0, tx_gt_charisk}),
+    .TXDATA ({32'd0, tx_gt_data}),
+    .TXDATAEXTENDRSVD (8'd0),
+    .TXDEEMPH (1'd0),
+    .TXDETECTRX (1'd0),
+    .TXDIFFCTRL (4'b1100),
+    .TXDIFFPD (1'd0),
+    .TXDLYBYPASS (1'd1),
+    .TXDLYEN (1'd0),
+    .TXDLYHOLD (1'd0),
+    .TXDLYOVRDEN (1'd0),
+    .TXDLYSRESET (1'd0),
+    .TXDLYUPDOWN (1'd0),
+    .TXELECIDLE (1'd0),
+    .TXHEADER (6'd0),
+    .TXINHIBIT (1'd0),
+    .TXLATCLK (1'd0),
+    .TXMAINCURSOR (7'b1000000),
+    .TXMARGIN (3'd0),
+    .TXOUTCLKSEL (tx_out_clk_sel),
+    .TXPCSRESET (1'd0),
+    .TXPD (2'd0),
+    .TXPDELECIDLEMODE (1'd0),
+    .TXPHALIGN (1'd0),
+    .TXPHALIGNEN (1'd0),
+    .TXPHDLYPD (1'd1),
+    .TXPHDLYRESET (1'd0),
+    .TXPHDLYTSTCLK (1'd0),
+    .TXPHINIT (1'd0),
+    .TXPHOVRDEN (1'd0),
+    .TXPIPPMEN (1'd0),
+    .TXPIPPMOVRDEN (1'd0),
+    .TXPIPPMPD (1'd0),
+    .TXPIPPMSEL (1'd0),
+    .TXPIPPMSTEPSIZE (5'd0),
+    .TXPISOPD (1'd0),
+    .TXPLLCLKSEL (tx_pll_clk_sel_s),
+    .TXPMARESET (1'd0),
+    .TXPOLARITY (1'd0),
+    .TXPOSTCURSOR (5'd0),
+    .TXPOSTCURSORINV (1'd0),
+    .TXPRBSFORCEERR (1'd0),
+    .TXPRBSSEL (4'd0),
+    .TXPRECURSOR (5'd0),
+    .TXPRECURSORINV (1'd0),
+    .TXPROGDIVRESET (tx_rst),
+    .TXQPIBIASEN (1'd0),
+    .TXQPISTRONGPDOWN (1'd0),
+    .TXQPIWEAKPUP (1'd0),
+    .TXRATE (tx_rate),
+    .TXRATEMODE (1'd0),
+    .TXSEQUENCE (7'd0),
+    .TXSWING (1'd0),
+    .TXSYNCALLIN (1'd0),
+    .TXSYNCIN (1'd0),
+    .TXSYNCMODE (1'd0),
+    .TXSYSCLKSEL (tx_sys_clk_sel_s),
+    .TXUSERRDY (tx_user_ready),
+    .TXUSRCLK (tx_clk),
+    .TXUSRCLK2 (tx_clk),
+    .TX8B10BBYPASS (8'd0),
+    .TX8B10BEN (1'd1),
+    .BUFGTCE (),
+    .BUFGTCEMASK (),
+    .BUFGTDIV (),
+    .BUFGTRESET (),
+    .BUFGTRSTMASK (),
+    .CPLLFBCLKLOST (),
+    .CPLLLOCK (cpll_locked_s),
+    .CPLLREFCLKLOST (),
+    .DMONITOROUT (),
+    .DRPDO (up_drp_rdata_s),
+    .DRPRDY (up_drp_ready_s),
+    .EYESCANDATAERROR (),
+    .GTHTXN (tx_n),
+    .GTHTXP (tx_p),
+    .GTPOWERGOOD (),
+    .GTREFCLKMONITOR (),
+    .PCIERATEGEN3 (),
+    .PCIERATEIDLE (),
+    .PCIERATEQPLLPD (),
+    .PCIERATEQPLLRESET (),
+    .PCIESYNCTXSYNCDONE (),
+    .PCIEUSERGEN3RDY (),
+    .PCIEUSERPHYSTATUSRST (),
+    .PCIEUSERRATESTART (),
+    .PCSRSVDOUT (),
+    .PHYSTATUS (),
+    .PINRSRVDAS (),
+    .RESETEXCEPTION (),
+    .RXBUFSTATUS (),
+    .RXBYTEISALIGNED (),
+    .RXBYTEREALIGN (),
+    .RXCDRLOCK (),
+    .RXCDRPHDONE (),
+    .RXCHANBONDSEQ (),
+    .RXCHANISALIGNED (),
+    .RXCHANREALIGN (),
+    .RXCHBONDO (),
+    .RXCLKCORCNT (),
+    .RXCOMINITDET (),
+    .RXCOMMADET (),
+    .RXCOMSASDET (),
+    .RXCOMWAKEDET (),
+    .RXCTRL0 ({rx_charisk_open_s, rx_gt_charisk}),
+    .RXCTRL1 ({rx_disperr_open_s, rx_gt_disperr}),
+    .RXCTRL2 (),
+    .RXCTRL3 ({rx_notintable_open_s, rx_gt_notintable}),
+    .RXDATA ({rx_data_open_s, rx_gt_data}),
+    .RXDATAEXTENDRSVD (),
+    .RXDATAVALID (),
+    .RXDLYSRESETDONE (),
+    .RXELECIDLE (),
+    .RXHEADER (),
+    .RXHEADERVALID (),
+    .RXMONITOROUT (),
+    .RXOSINTDONE (),
+    .RXOSINTSTARTED (),
+    .RXOSINTSTROBEDONE (),
+    .RXOSINTSTROBESTARTED (),
+    .RXOUTCLK (rx_out_clk),
+    .RXOUTCLKFABRIC (),
+    .RXOUTCLKPCS (),
+    .RXPHALIGNDONE (),
+    .RXPHALIGNERR (),
+    .RXPMARESETDONE (),
+    .RXPRBSERR (),
+    .RXPRBSLOCKED (),
+    .RXPRGDIVRESETDONE (),
+    .RXQPISENN (),
+    .RXQPISENP (),
+    .RXRATEDONE (),
+    .RXRECCLKOUT (),
+    .RXRESETDONE (rx_rst_done),
+    .RXSLIDERDY (),
+    .RXSLIPDONE (),
+    .RXSLIPOUTCLKRDY (),
+    .RXSLIPPMARDY (),
+    .RXSTARTOFSEQ (),
+    .RXSTATUS (),
+    .RXSYNCDONE (),
+    .RXSYNCOUT (),
+    .RXVALID (),
+    .TXBUFSTATUS (),
+    .TXCOMFINISH (),
+    .TXDLYSRESETDONE (),
+    .TXOUTCLK (tx_out_clk),
+    .TXOUTCLKFABRIC (),
+    .TXOUTCLKPCS (),
+    .TXPHALIGNDONE (),
+    .TXPHINITDONE (),
+    .TXPMARESETDONE (),
+    .TXPRGDIVRESETDONE (),
+    .TXQPISENN (),
+    .TXQPISENP (),
+    .TXRATEDONE (),
+    .TXRESETDONE (tx_rst_done),
+    .TXSYNCDONE (),
+    .TXSYNCOUT ());
+  end
+  endgenerate
+
+endmodule     
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/util_adxcvr/util_adxcvr_xcm.v b/library/util_adxcvr/util_adxcvr_xcm.v
new file mode 100644
index 000000000..6ec6b35df
--- /dev/null
+++ b/library/util_adxcvr/util_adxcvr_xcm.v
@@ -0,0 +1,291 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module util_adxcvr_xcm (
+
+  // reset and clocks
+
+  input           ref_clk,
+  input           pll_rst,
+  output          qpll_clk,
+  output          qpll_ref_clk,
+  output          qpll_locked,
+
+  // drp interface
+
+  input           up_clk,
+  input           up_drp_sel,
+  input   [11:0]  up_drp_addr,
+  input           up_drp_wr,
+  input   [15:0]  up_drp_wdata,
+  output  [15:0]  up_drp_rdata,
+  output          up_drp_ready);
+
+  // parameters
+
+  parameter   integer GTH_OR_GTX_N = 0;
+  parameter   integer QPLL_ENABLE = 1;
+  parameter   integer QPLL_REFCLK_DIV = 2;
+  parameter   integer QPLL_FBDIV_RATIO = 1;
+  parameter   [26:0]  QPLL_CFG = 27'h06801C1;
+  parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000;
+
+  // instantiations
+
+  generate
+  if (QPLL_ENABLE == 0) begin
+  assign qpll_clk = 1'd0;
+  assign qpll_ref_clk = 1'd0;
+  assign qpll_locked = 1'd0;
+  assign up_drp_rdata = 16'd0;
+  assign up_drp_ready = 1'd0;
+  end
+  endgenerate
+
+  generate
+  if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 0)) begin
+  GTXE2_COMMON #(
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_QPLLREFCLK_SEL (3'b001),
+    .SIM_VERSION ("3.0"),
+    .BIAS_CFG (64'h0000040000001000),
+    .COMMON_CFG (32'h00000000),
+    .QPLL_CFG (QPLL_CFG),
+    .QPLL_CLKOUT_CFG (4'b0000),
+    .QPLL_COARSE_FREQ_OVRD (6'b010000),
+    .QPLL_COARSE_FREQ_OVRD_EN (1'b0),
+    .QPLL_CP (10'b0000011111),
+    .QPLL_CP_MONITOR_EN (1'b0),
+    .QPLL_DMONITOR_SEL (1'b0),
+    .QPLL_FBDIV (QPLL_FBDIV),
+    .QPLL_FBDIV_MONITOR_EN (1'b0),
+    .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
+    .QPLL_INIT_CFG (24'h000006),
+    .QPLL_LOCK_CFG (16'h21E8),
+    .QPLL_LPF (4'b1111),
+    .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
+  i_gtxe2_common (
+    .DRPCLK (up_clk),
+    .DRPEN (up_drp_sel),
+    .DRPADDR (up_drp_addr[7:0]),
+    .DRPWE (up_drp_wr),
+    .DRPDI (up_drp_wdata),
+    .DRPDO (up_drp_rdata),
+    .DRPRDY (up_drp_ready),
+    .GTGREFCLK (1'd0),
+    .GTNORTHREFCLK0 (1'd0),
+    .GTNORTHREFCLK1 (1'd0),
+    .GTREFCLK0 (ref_clk),
+    .GTREFCLK1 (1'd0),
+    .GTSOUTHREFCLK0 (1'd0),
+    .GTSOUTHREFCLK1 (1'd0),
+    .QPLLDMONITOR (),
+    .QPLLOUTCLK (qpll_clk),
+    .QPLLOUTREFCLK (qpll_ref_clk),
+    .REFCLKOUTMONITOR (),
+    .QPLLFBCLKLOST (),
+    .QPLLLOCK (qpll_locked),
+    .QPLLLOCKDETCLK (up_clk),
+    .QPLLLOCKEN (1'd1),
+    .QPLLOUTRESET (1'd0),
+    .QPLLPD (1'd0),
+    .QPLLREFCLKLOST (),
+    .QPLLREFCLKSEL (3'b001),
+    .QPLLRESET (pll_rst),
+    .QPLLRSVD1 (16'b0000000000000000),
+    .QPLLRSVD2 (5'b11111),
+    .BGBYPASSB (1'd1),
+    .BGMONITORENB (1'd1),
+    .BGPDB (1'd1),
+    .BGRCALOVRD (5'b00000),
+    .PMARSVD (8'b00000000),
+    .RCALENB (1'd1));
+  end
+  endgenerate
+
+  generate
+  if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 1)) begin
+  GTHE3_COMMON #(
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_VERSION (2),
+    .SARC_EN (1'b1),
+    .SARC_SEL (1'b0),
+    .SDM0_DATA_PIN_SEL (1'b0),
+    .SDM0_WIDTH_PIN_SEL (1'b0),
+    .SDM1_DATA_PIN_SEL (1'b0),
+    .SDM1_WIDTH_PIN_SEL (1'b0),
+    .BIAS_CFG0 (16'b0000000000000000),
+    .BIAS_CFG1 (16'b0000000000000000),
+    .BIAS_CFG2 (16'b0000000000000000),
+    .BIAS_CFG3 (16'b0000000001000000),
+    .BIAS_CFG4 (16'b0000000000000000),
+    .COMMON_CFG0 (16'b0000000000000000),
+    .COMMON_CFG1 (16'b0000000000000000),
+    .POR_CFG (16'b0000000000000100),
+    .QPLL0_CFG0 (16'b0011000000011100),
+    .QPLL0_CFG1 (16'b0000000000011000),
+    .QPLL0_CFG1_G3 (16'b0000000000011000),
+    .QPLL0_CFG2 (16'b0000000001001000),
+    .QPLL0_CFG2_G3 (16'b0000000001001000),
+    .QPLL0_CFG3 (16'b0000000100100000),
+    .QPLL0_CFG4 (16'b0000000000001001),
+    .QPLL0_INIT_CFG0 (16'b0000000000000000),
+    .QPLL0_LOCK_CFG (16'b0010010111101000),
+    .QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
+    .QPLL0_SDM_CFG0 (16'b0000000000000000),
+    .QPLL0_SDM_CFG1 (16'b0000000000000000),
+    .QPLL0_SDM_CFG2 (16'b0000000000000000),
+    .QPLL1_CFG0 (16'b0011000000011100),
+    .QPLL1_CFG1 (16'b0000000000011000),
+    .QPLL1_CFG1_G3 (16'b0000000000011000),
+    .QPLL1_CFG2 (16'b0000000001000000),
+    .QPLL1_CFG2_G3 (16'b0000000001000000),
+    .QPLL1_CFG3 (16'b0000000100100000),
+    .QPLL1_CFG4 (16'b0000000000001001),
+    .QPLL1_INIT_CFG0 (16'b0000000000000000),
+    .QPLL1_LOCK_CFG (16'b0010010111101000),
+    .QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
+    .QPLL1_SDM_CFG0 (16'b0000000000000000),
+    .QPLL1_SDM_CFG1 (16'b0000000000000000),
+    .QPLL1_SDM_CFG2 (16'b0000000000000000),
+    .RSVD_ATTR0 (16'b0000000000000000),
+    .RSVD_ATTR1 (16'b0000000000000000),
+    .RSVD_ATTR2 (16'b0000000000000000),
+    .RSVD_ATTR3 (16'b0000000000000000),
+    .SDM0DATA1_0 (16'b0000000000000000),
+    .SDM0INITSEED0_0 (16'b0000000000000000),
+    .SDM1DATA1_0 (16'b0000000000000000),
+    .SDM1INITSEED0_0 (16'b0000000000000000),
+    .RXRECCLKOUT0_SEL (2'b00),
+    .RXRECCLKOUT1_SEL (2'b00),
+    .QPLL0_INIT_CFG1 (8'b00000000),
+    .QPLL1_INIT_CFG1 (8'b00000000),
+    .SDM0DATA1_1 (9'b000000000),
+    .SDM0INITSEED0_1 (9'b000000000),
+    .SDM1DATA1_1 (9'b000000000),
+    .SDM1INITSEED0_1 (9'b000000000),
+    .BIAS_CFG_RSVD (10'b0000000000),
+    .QPLL0_CP (10'b0000011111),
+    .QPLL0_CP_G3 (10'b1111111111),
+    .QPLL0_LPF (10'b1111111111),
+    .QPLL0_LPF_G3 (10'b0000010101),
+    .QPLL1_CP (10'b0000011111),
+    .QPLL1_CP_G3 (10'b1111111111),
+    .QPLL1_LPF (10'b1111111111),
+    .QPLL1_LPF_G3 (10'b0000010101),
+    .QPLL0_FBDIV (QPLL_FBDIV),
+    .QPLL0_FBDIV_G3 (80),
+    .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
+    .QPLL1_FBDIV (QPLL_FBDIV),
+    .QPLL1_FBDIV_G3 (80),
+    .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV))
+  i_gthe3_common (
+    .BGBYPASSB (1'd1),
+    .BGMONITORENB (1'd1),
+    .BGPDB (1'd1),
+    .BGRCALOVRD (5'b11111),
+    .BGRCALOVRDENB (1'd1),
+    .DRPADDR (up_drp_addr[8:0]),
+    .DRPCLK (up_clk),
+    .DRPDI (up_drp_wdata),
+    .DRPEN (up_drp_sel),
+    .DRPWE (up_drp_wr),
+    .GTGREFCLK0 (1'd0),
+    .GTGREFCLK1 (1'd0),
+    .GTNORTHREFCLK00 (1'd0),
+    .GTNORTHREFCLK01 (1'd0),
+    .GTNORTHREFCLK10 (1'd0),
+    .GTNORTHREFCLK11 (1'd0),
+    .GTREFCLK00 (ref_clk),
+    .GTREFCLK01 (1'd0),
+    .GTREFCLK10 (1'd0),
+    .GTREFCLK11 (1'd0),
+    .GTSOUTHREFCLK00 (1'd0),
+    .GTSOUTHREFCLK01 (1'd0),
+    .GTSOUTHREFCLK10 (1'd0),
+    .GTSOUTHREFCLK11 (1'd0),
+    .PMARSVD0 (8'd0),
+    .PMARSVD1 (8'd0),
+    .QPLLRSVD1 (8'd0),
+    .QPLLRSVD2 (5'd0),
+    .QPLLRSVD3 (5'd0),
+    .QPLLRSVD4 (8'd0),
+    .QPLL0CLKRSVD0 (1'd0),
+    .QPLL0CLKRSVD1 (1'd0),
+    .QPLL0LOCKDETCLK (up_clk),
+    .QPLL0LOCKEN (1'd1),
+    .QPLL0PD (1'd0),
+    .QPLL0REFCLKSEL (3'b001),
+    .QPLL0RESET (pll_rst),
+    .QPLL1CLKRSVD0 (1'd0),
+    .QPLL1CLKRSVD1 (1'd0),
+    .QPLL1LOCKDETCLK (1'd0),
+    .QPLL1LOCKEN (1'd0),
+    .QPLL1PD (1'd1),
+    .QPLL1REFCLKSEL (3'b001),
+    .QPLL1RESET (1'd1),
+    .RCALENB (1'd1),
+    .DRPDO (up_drp_rdata),
+    .DRPRDY (up_drp_ready),
+    .PMARSVDOUT0 (),
+    .PMARSVDOUT1 (),
+    .QPLLDMONITOR0 (),
+    .QPLLDMONITOR1 (),
+    .QPLL0FBCLKLOST (),
+    .QPLL0LOCK (qpll_locked),
+    .QPLL0OUTCLK (qpll_clk),
+    .QPLL0OUTREFCLK (qpll_ref_clk),
+    .QPLL0REFCLKLOST (),
+    .QPLL1FBCLKLOST (),
+    .QPLL1LOCK (),
+    .QPLL1OUTCLK (),
+    .QPLL1OUTREFCLK (),
+    .QPLL1REFCLKLOST (),
+    .REFCLKOUTMONITOR0 (),
+    .REFCLKOUTMONITOR1 (),
+    .RXRECCLK0_SEL (),
+    .RXRECCLK1_SEL ());
+  end
+  endgenerate
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+

From 5d437083cc4ef2422cd97fe39a873dcf22cde6a0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 14 Jun 2016 12:19:35 -0400
Subject: [PATCH 282/972] ad9361/altera- a10+ only

---
 library/axi_ad9361/axi_ad9361_hw.tcl | 49 ++++++++++++++++------------
 1 file changed, 28 insertions(+), 21 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 974e2e720..7a9ce8eaa 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -225,6 +225,28 @@ ad_alt_intf signal up_dac_gpio_out output 32
 ad_alt_intf signal up_adc_gpio_in input 32
 ad_alt_intf signal up_adc_gpio_out output 32
 
+add_hdl_instance alt_ddio_in altera_gpio
+set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
+set_instance_parameter_value alt_ddio_in {SIZE} {1}
+set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
+set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
+
+add_hdl_instance alt_ddio_out altera_gpio
+set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
+set_instance_parameter_value alt_ddio_out {SIZE} {1}
+set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
+set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
+
+add_hdl_instance alt_clk altera_iopll
+set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
+set_instance_parameter_value alt_clk {gui_use_locked} {1}
+set_instance_parameter_value alt_clk {gui_operation_mode} {source synchronous}
+set_instance_parameter_value alt_clk {gui_number_of_clocks} {1}
+set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
+set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
+set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
+set_instance_parameter_value alt_clk {system_info_device_family} $m_device_family
+
 # updates
 
 proc p_axi_ad9361 {} {
@@ -266,29 +288,14 @@ proc p_axi_ad9361 {} {
   add_interface_port device_if enable enable Output 1
   add_interface_port device_if txnrx txnrx Output 1
 
+  if {$m_device_type == 1} {
+
+    ## add_hdl_instance do not work here (pending altera support)
+  }
+
   if {$m_device_type == 0} {
 
-    add_hdl_instance alt_ddio_in altera_gpio
-    set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
-    set_instance_parameter_value alt_ddio_in {SIZE} {1}
-    set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
-    set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
-
-    add_hdl_instance alt_ddio_out altera_gpio
-    set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
-    set_instance_parameter_value alt_ddio_out {SIZE} {1}
-    set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
-    set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
-
-    add_hdl_instance alt_clk altera_iopll
-    set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
-    set_instance_parameter_value alt_clk {gui_use_locked} {1}
-    set_instance_parameter_value alt_clk {gui_operation_mode} {source synchronous}
-    set_instance_parameter_value alt_clk {gui_number_of_clocks} {1}
-    set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
-    set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
-    set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
-    set_instance_parameter_value alt_clk {system_info_device_family} $m_device_family
+    ## add_hdl_instance do not work here (pending altera support)
   }
 }
 

From 7485d27d374e8daa52005f899b69cb0799101cbd Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 14 Jun 2016 12:28:13 -0400
Subject: [PATCH 283/972] ad9361/altera- device-family variable

---
 library/axi_ad9361/axi_ad9361_hw.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 7a9ce8eaa..fec710019 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -245,7 +245,7 @@ set_instance_parameter_value alt_clk {gui_number_of_clocks} {1}
 set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
 set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
 set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
-set_instance_parameter_value alt_clk {system_info_device_family} $m_device_family
+set_instance_parameter_value alt_clk {system_info_device_family} DEVICE_FAMILY
 
 # updates
 

From 67c948e8211a96a0bed2b7c8d5642d18963fc7eb Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 14 Jun 2016 12:29:36 -0400
Subject: [PATCH 284/972] fmcomms2/a10soc-- bad board design

---
 projects/fmcomms2/a10soc/Makefile           | 144 ------
 projects/fmcomms2/a10soc/system_bd.qsys     | 500 --------------------
 projects/fmcomms2/a10soc/system_constr.sdc  |   7 -
 projects/fmcomms2/a10soc/system_project.tcl | 130 -----
 projects/fmcomms2/a10soc/system_top.v       | 264 -----------
 5 files changed, 1045 deletions(-)
 delete mode 100644 projects/fmcomms2/a10soc/Makefile
 delete mode 100755 projects/fmcomms2/a10soc/system_bd.qsys
 delete mode 100644 projects/fmcomms2/a10soc/system_constr.sdc
 delete mode 100644 projects/fmcomms2/a10soc/system_project.tcl
 delete mode 100644 projects/fmcomms2/a10soc/system_top.v

diff --git a/projects/fmcomms2/a10soc/Makefile b/projects/fmcomms2/a10soc/Makefile
deleted file mode 100644
index 5ad3076bd..000000000
--- a/projects/fmcomms2/a10soc/Makefile
+++ /dev/null
@@ -1,144 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.sdc
-M_DEPS += system_bd.qsys
-M_DEPS += ../common/fmcomms2_bd.qsys
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
-M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
-M_DEPS += ../../../library/axi_dmac/2d_transfer.v
-M_DEPS += ../../../library/axi_dmac/address_generator.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
-M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
-M_DEPS += ../../../library/axi_dmac/data_mover.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
-M_DEPS += ../../../library/axi_dmac/inc_id.h
-M_DEPS += ../../../library/axi_dmac/request_arb.v
-M_DEPS += ../../../library/axi_dmac/request_generator.v
-M_DEPS += ../../../library/axi_dmac/resp.h
-M_DEPS += ../../../library/axi_dmac/response_generator.v
-M_DEPS += ../../../library/axi_dmac/response_handler.v
-M_DEPS += ../../../library/axi_dmac/splitter.v
-M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/common/ad_addsub.v
-M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_dcfilter.v
-M_DEPS += ../../../library/common/ad_dds.v
-M_DEPS += ../../../library/common/ad_dds_1.v
-M_DEPS += ../../../library/common/ad_dds_sine.v
-M_DEPS += ../../../library/common/ad_iqcor.v
-M_DEPS += ../../../library/common/ad_mul.v
-M_DEPS += ../../../library/common/ad_pnmon.v
-M_DEPS += ../../../library/common/ad_rst.v
-M_DEPS += ../../../library/common/ad_tdd_control.v
-M_DEPS += ../../../library/common/altera/DSP48E1.v
-M_DEPS += ../../../library/common/altera/MULT_MACRO.v
-M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
-M_DEPS += ../../../library/common/altera/ad_cmos_in.v
-M_DEPS += ../../../library/common/altera/ad_cmos_out.v
-M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
-M_DEPS += ../../../library/common/altera/ad_lvds_in.v
-M_DEPS += ../../../library/common/altera/ad_lvds_out.v
-M_DEPS += ../../../library/common/sync_bits.v
-M_DEPS += ../../../library/common/sync_gray.v
-M_DEPS += ../../../library/common/up_adc_channel.v
-M_DEPS += ../../../library/common/up_adc_common.v
-M_DEPS += ../../../library/common/up_axi.v
-M_DEPS += ../../../library/common/up_clock_mon.v
-M_DEPS += ../../../library/common/up_dac_channel.v
-M_DEPS += ../../../library/common/up_dac_common.v
-M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_tdd_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
-M_DEPS += ../../../library/util_axis_fifo/address_sync.v
-M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
-M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
-M_DEPS += ../../../library/util_cpack/util_cpack.v
-M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
-M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
-M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
-M_DEPS += ../../../library/util_upack/util_upack.v
-M_DEPS += ../../../library/util_upack/util_upack_dmx.v
-M_DEPS += ../../../library/util_upack/util_upack_dsf.v
-M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
-
-
-M_ALTERA := quartus_sh --64bit -t 
-
-
-M_FLIST += *.log
-M_FLIST += *_INFO.txt
-M_FLIST += *_dump.txt
-M_FLIST += db
-M_FLIST += *.asm.rpt
-M_FLIST += *.done
-M_FLIST += *.eda.rpt
-M_FLIST += *.fit.*
-M_FLIST += *.map.*
-M_FLIST += *.sta.*
-M_FLIST += *.qsf
-M_FLIST += *.qpf
-M_FLIST += *.qws
-M_FLIST += *.sof
-M_FLIST += *.cdf
-M_FLIST += *.sld
-M_FLIST += *.qdf
-M_FLIST += hc_output
-M_FLIST += system_bd
-M_FLIST += hps_isw_handoff
-M_FLIST += hps_sdram_*.csv
-M_FLIST += *ddr3_*.csv
-M_FLIST += incremental_db
-M_FLIST += reconfig_mif
-M_FLIST += *.sopcinfo
-M_FLIST +=  *.jdi
-M_FLIST += *.pin
-M_FLIST += *_summary.csv
-M_FLIST += *.dpf
-
-
-
-.PHONY: all clean clean-all
-all: fmcomms2_a10soc.sof
-
-
-
-clean:clean-all
-
-
-clean-all:
-	rm -rf $(M_FLIST)
-
-
-fmcomms2_a10soc.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
-	$(M_ALTERA) system_project.tcl  >> fmcomms2_a10soc_quartus.log 2>&1
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms2/a10soc/system_bd.qsys b/projects/fmcomms2/a10soc/system_bd.qsys
deleted file mode 100755
index 72d7386ca..000000000
--- a/projects/fmcomms2/a10soc/system_bd.qsys
+++ /dev/null
@@ -1,500 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element a10soc
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element a10soc.hps_s1_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element fmcomms2
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element fmcomms2.axi_ad9361_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element fmcomms2.axi_dmac_adc_s_axi
-   {
-      datum baseAddress
-      {
-         value = "81920";
-         type = "String";
-      }
-   }
-   element fmcomms2.axi_dmac_dac_s_axi
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40E2SGE2" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="fmcomms2_a10soc.qpf" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="ad9361_if"
-   internal="fmcomms2.axi_ad9361_device_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="delay_clk"
-   internal="fmcomms2.axi_ad9361_delay_clk"
-   type="clock"
-   dir="end" />
- <interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
- <interface
-   name="hps_ddr_oct"
-   internal="a10soc.hps_ddr_oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_ddr_ref_clk"
-   internal="a10soc.hps_ddr_ref_clk"
-   type="clock"
-   dir="end" />
- <interface name="hps_gpio" internal="a10soc.hps_gpio" type="conduit" dir="end" />
- <interface name="hps_io" internal="a10soc.hps_io" type="conduit" dir="end" />
- <interface name="hps_spi0" internal="a10soc.hps_spi0" type="conduit" dir="end" />
- <interface
-   name="hps_spi0_sclk"
-   internal="a10soc.hps_spi0_sclk"
-   type="clock"
-   dir="start" />
- <interface name="hps_spi1" internal="a10soc.hps_spi1" type="conduit" dir="end" />
- <interface
-   name="hps_spi1_sclk"
-   internal="a10soc.hps_spi1_sclk"
-   type="clock"
-   dir="start" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_reset"
-   internal="sys_clk.clk_in_reset"
-   type="reset"
-   dir="end" />
- <interface
-   name="up_enable"
-   internal="fmcomms2.axi_ad9361_up_enable"
-   type="conduit"
-   dir="end" />
- <interface
-   name="up_txnrx"
-   internal="fmcomms2.axi_ad9361_up_txnrx"
-   type="conduit"
-   dir="end" />
- <module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="2" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="2" />
-  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
-  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
- </module>
- <module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 32" />
-  <parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 32" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
- </module>
- <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fmcomms2.axi_dmac_adc_m_dest_axi"
-   end="a10soc.hps_s1_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fmcomms2.axi_dmac_dac_m_src_axi"
-   end="a10soc.hps_s1_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="fmcomms2.axi_ad9361_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="fmcomms2.axi_dmac_adc_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00014000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="fmcomms2.axi_dmac_dac_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.clk"
-   end="fmcomms2.sys_clk" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq0"
-   end="fmcomms2.axi_dmac_adc_intr">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq0"
-   end="fmcomms2.axi_dmac_dac_intr">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq1"
-   end="fmcomms2.axi_dmac_adc_intr">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq1"
-   end="fmcomms2.axi_dmac_dac_intr">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="a10soc.sys_rst_in" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="a10soc.sys_rst"
-   end="fmcomms2.sys_rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/fmcomms2/a10soc/system_constr.sdc b/projects/fmcomms2/a10soc/system_constr.sdc
deleted file mode 100644
index 1f9b3d462..000000000
--- a/projects/fmcomms2/a10soc/system_constr.sdc
+++ /dev/null
@@ -1,7 +0,0 @@
-
-create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
-create_clock -period  "4.000 ns"  -name rx_clk_250mhz       [get_ports {rx_clk_in}]
-
-derive_pll_clocks
-derive_clock_uncertainty
-
diff --git a/projects/fmcomms2/a10soc/system_project.tcl b/projects/fmcomms2/a10soc/system_project.tcl
deleted file mode 100644
index 83b8cdf94..000000000
--- a/projects/fmcomms2/a10soc/system_project.tcl
+++ /dev/null
@@ -1,130 +0,0 @@
-
-load_package flow
-
-source ../../scripts/adi_env.tcl
-project_new fmcomms2_a10soc -overwrite
-
-source "../../common/a10soc/a10soc_system_assign.tcl"
-
-set_global_assignment -name QSYS_FILE system_bd.qsys
-set_global_assignment -name VERILOG_FILE system_top.v
-set_global_assignment -name SDC_FILE system_constr.sdc
-set_global_assignment -name TOP_LEVEL_ENTITY system_top
-
-# data-path
-
-set_location_assignment PIN_G14   -to rx_clk_in             ; ## G6   FMC_LPC_LA00_CC_P
-set_location_assignment PIN_H14   -to "rx_clk_in(n)"        ; ## G7   FMC_LPC_LA00_CC_N
-set_location_assignment PIN_E12   -to rx_frame_in           ; ## D8   FMC_LPC_LA01_CC_P
-set_location_assignment PIN_E13   -to "rx_frame_in(n)"      ; ## D9   FMC_LPC_LA01_CC_N
-set_location_assignment PIN_C13   -to rx_data_in[0]         ; ## H7   FMC_LPC_LA02_P
-set_location_assignment PIN_D13   -to "rx_data_in[0](n)"    ; ## H8   FMC_LPC_LA02_N
-set_location_assignment PIN_C14   -to rx_data_in[1]         ; ## G9   FMC_LPC_LA03_P
-set_location_assignment PIN_D14   -to "rx_data_in[1](n)"    ; ## G10  FMC_LPC_LA03_N
-set_location_assignment PIN_H12   -to rx_data_in[2]         ; ## H10  FMC_LPC_LA04_P
-set_location_assignment PIN_H13   -to "rx_data_in[2](n)"    ; ## H11  FMC_LPC_LA04_N
-set_location_assignment PIN_F13   -to rx_data_in[3]         ; ## D11  FMC_LPC_LA05_P
-set_location_assignment PIN_F14   -to "rx_data_in[3](n)"    ; ## D12  FMC_LPC_LA05_N
-set_location_assignment PIN_A10   -to rx_data_in[4]         ; ## C10  FMC_LPC_LA06_P
-set_location_assignment PIN_B10   -to "rx_data_in[4](n)"    ; ## C11  FMC_LPC_LA06_N
-set_location_assignment PIN_A9    -to rx_data_in[5]         ; ## H13  FMC_LPC_LA07_P
-set_location_assignment PIN_B9    -to "rx_data_in[5](n)"    ; ## H14  FMC_LPC_LA07_N
-set_location_assignment PIN_B11   -to tx_clk_out            ; ## G12  FMC_LPC_LA08_P
-set_location_assignment PIN_B12   -to "tx_clk_out(n)"       ; ## G13  FMC_LPC_LA08_N
-set_location_assignment PIN_A12   -to tx_frame_out          ; ## D14  FMC_LPC_LA09_P
-set_location_assignment PIN_A13   -to "tx_frame_out(n)"     ; ## D15  FMC_LPC_LA09_N
-set_location_assignment PIN_C9    -to tx_data_out[0]        ; ## H16  FMC_LPC_LA11_P
-set_location_assignment PIN_D9    -to "tx_data_out[0](n)"   ; ## H17  FMC_LPC_LA11_N
-set_location_assignment PIN_M12   -to tx_data_out[1]        ; ## G15  FMC_LPC_LA12_P
-set_location_assignment PIN_N13   -to "tx_data_out[1](n)"   ; ## G16  FMC_LPC_LA12_N
-set_location_assignment PIN_J11   -to tx_data_out[2]        ; ## D17  FMC_LPC_LA13_P
-set_location_assignment PIN_K11   -to "tx_data_out[2](n)"   ; ## D18  FMC_LPC_LA13_N
-set_location_assignment PIN_A7    -to tx_data_out[3]        ; ## C14  FMC_LPC_LA10_P
-set_location_assignment PIN_A8    -to "tx_data_out[3](n)"   ; ## C15  FMC_LPC_LA10_N
-set_location_assignment PIN_J9    -to tx_data_out[4]        ; ## C18  FMC_LPC_LA14_P
-set_location_assignment PIN_J10   -to "tx_data_out[4](n)"   ; ## C19  FMC_LPC_LA14_N
-set_location_assignment PIN_D4    -to tx_data_out[5]        ; ## H19  FMC_LPC_LA15_P
-set_location_assignment PIN_D5    -to "tx_data_out[5](n)"   ; ## H20  FMC_LPC_LA15_N
-
-set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
-set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
-set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
-set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[1]
-set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[2]
-set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[3]
-set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[4]
-set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[5]
-set_instance_assignment -name IO_STANDARD LVDS -to tx_clk_out
-set_instance_assignment -name IO_STANDARD LVDS -to tx_frame_out
-set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[0]
-set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[1]
-set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2]
-set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3]
-set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4]
-set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5]
-
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_clk_in
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_frame_in
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[0]
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[1]
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[2]
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[3]
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[4]
-set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[5]
-
-# ensm/tdd control
-
-set_location_assignment PIN_D6    -to enable                ; ## G18  FMC_LPC_LA16_P
-set_location_assignment PIN_E6    -to txnrx                 ; ## G19  FMC_LPC_LA16_N
-
-set_instance_assignment -name IO_STANDARD "1.8 V" -to enable
-set_instance_assignment -name IO_STANDARD "1.8 V" -to txnrx
-
-# control & status
-
-set_location_assignment PIN_C3    -to gpio_status[0]        ; ## G21  FMC_LPC_LA20_P
-set_location_assignment PIN_C4    -to gpio_status[1]        ; ## G22  FMC_LPC_LA20_N
-set_location_assignment PIN_C2    -to gpio_status[2]        ; ## H25  FMC_LPC_LA21_P
-set_location_assignment PIN_D3    -to gpio_status[3]        ; ## H26  FMC_LPC_LA21_N
-set_location_assignment PIN_F4    -to gpio_status[4]        ; ## G24  FMC_LPC_LA22_P
-set_location_assignment PIN_G4    -to gpio_status[5]        ; ## G25  FMC_LPC_LA22_N
-set_location_assignment PIN_C1    -to gpio_status[6]        ; ## D23  FMC_LPC_LA23_P
-set_location_assignment PIN_D1    -to gpio_status[7]        ; ## D24  FMC_LPC_LA23_N
-set_location_assignment PIN_E1    -to gpio_ctl[0]           ; ## H28  FMC_LPC_LA24_P
-set_location_assignment PIN_E2    -to gpio_ctl[1]           ; ## H29  FMC_LPC_LA24_N
-set_location_assignment PIN_E3    -to gpio_ctl[2]           ; ## G27  FMC_LPC_LA25_P
-set_location_assignment PIN_F3    -to gpio_ctl[3]           ; ## G28  FMC_LPC_LA25_N
-set_location_assignment PIN_G5    -to gpio_en_agc           ; ## H22  FMC_LPC_LA19_P
-set_location_assignment PIN_G6    -to gpio_sync             ; ## H23  FMC_LPC_LA19_N
-set_location_assignment PIN_L5    -to gpio_resetb           ; ## H31  FMC_LPC_LA28_P
-
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[0]    
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[1]    
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[2]    
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[3]    
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[4]    
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[5]    
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[6]    
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[7]    
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[0]       
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[1]       
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[2]       
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[3]       
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_en_agc       
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_sync         
-set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_resetb       
-
-# spi
-
-set_location_assignment PIN_F2    -to spi_csn               ; ## D26  FMC_LPC_LA26_P
-set_location_assignment PIN_G2    -to spi_clk               ; ## D27  FMC_LPC_LA26_N
-set_location_assignment PIN_G1    -to spi_mosi              ; ## C26  FMC_LPC_LA27_P
-set_location_assignment PIN_H2    -to spi_miso              ; ## C27  FMC_LPC_LA27_N
-
-set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn
-set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
-set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
-set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
-
-execute_flow -compile
-
diff --git a/projects/fmcomms2/a10soc/system_top.v b/projects/fmcomms2/a10soc/system_top.v
deleted file mode 100644
index e4211a457..000000000
--- a/projects/fmcomms2/a10soc/system_top.v
+++ /dev/null
@@ -1,264 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module system_top (
-
-  // clock and resets
-
-  input             sys_clk,
-  input             sys_resetn,
-
-  // hps-ddr4 (32)
-
-  input             hps_ddr_ref_clk,
-  output  [  0:0]   hps_ddr_clk_p,
-  output  [  0:0]   hps_ddr_clk_n,
-  output  [ 16:0]   hsp_ddr_a,
-  output  [  1:0]   hps_ddr_ba,
-  output  [  0:0]   hps_ddr_bg,
-  output  [  0:0]   hps_ddr_cke,
-  output  [  0:0]   hps_ddr_cs_n,
-  output  [  0:0]   hps_ddr_odt,
-  output  [  0:0]   hps_ddr_reset_n,
-  output  [  0:0]   hps_ddr_act_n,
-  output  [  0:0]   hps_ddr_par,
-  input   [  0:0]   hps_ddr_alert_n,
-  inout   [  3:0]   hps_ddr_dqs_p,
-  inout   [  3:0]   hps_ddr_dqs_n,
-  inout   [ 31:0]   hps_ddr_dq,
-  inout   [  3:0]   hps_ddr_dbi_n,
-  input             hps_ddr_rzq,
-
-  // hps-ethernet
-
-  input   [  0:0]   hps_eth_rxclk,
-  input   [  0:0]   hps_eth_rxctl,
-  input   [  3:0]   hps_eth_rxd,
-  output  [  0:0]   hps_eth_txclk,
-  output  [  0:0]   hps_eth_txctl,
-  output  [  3:0]   hps_eth_txd,
-  output  [  0:0]   hps_eth_mdc,
-  inout   [  0:0]   hps_eth_mdio,
-
-  // hps-sdio
-
-  output  [  0:0]   hps_sdio_clk,
-  inout   [  0:0]   hps_sdio_cmd,
-  inout   [  7:0]   hps_sdio_d,
-
-  // hps-usb
-
-  input   [  0:0]   hps_usb_clk,
-  input   [  0:0]   hps_usb_dir,
-  input   [  0:0]   hps_usb_nxt,
-  output  [  0:0]   hps_usb_stp,
-  inout   [  7:0]   hps_usb_d,
-
-  // hps-uart
-
-  input   [  0:0]   hps_uart_rx,
-  output  [  0:0]   hps_uart_tx,
-
-  // hps-i2c (shared w fmc-a, fmc-b)
-
-  inout   [  0:0]   hps_i2c_sda,
-  inout   [  0:0]   hps_i2c_scl,
-
-  // hps-gpio (max-v-u16)
-
-  inout   [  3:0]   hps_gpio,
-          
-  // gpio (max-v-u21)
-
-  input   [  7:0]   gpio_bd_i,
-  output  [  3:0]   gpio_bd_o,
-
-  // ad9361-interface
-
-  input             rx_clk_in,
-  input             rx_frame_in,
-  input   [  5:0]   rx_data_in,
-  output            tx_clk_out,
-  output            tx_frame_out,
-  output  [  5:0]   tx_data_out,
-  output            enable,
-  output            txnrx,
-
-  output            gpio_resetb,
-  output            gpio_sync,
-  output            gpio_en_agc,
-  output  [  3:0]   gpio_ctl,
-  input   [  7:0]   gpio_status,
-
-  output            spi_csn,
-  output            spi_clk,
-  output            spi_mosi,
-  input             spi_miso);
-
-  // internal signals
-
-  wire    [ 31:0]   gpio_i;
-  wire    [ 31:0]   gpio_o;
-
-  // gpio (ad9361)
-
-  assign gpio_i[31:24] = gpio_o[31:24];
-  assign gpio_i[23:16] = gpio_status;
-
-  assign gpio_resetb = gpio_o[22];
-  assign gpio_sync = gpio_o[21];
-  assign gpio_en_agc = gpio_o[20];
-  assign gpio_ctl = gpio_o[19:16];
-
-  // gpio (max-v-u21)
-
-  assign gpio_i[15:8] = gpio_o[15:8];
-  assign gpio_i[ 7:0] = gpio_bd_i;
-
-  assign gpio_bd_o = gpio_o[3:0];
-
-  // instantiations
-
-  system_bd i_system_bd (
-    .ad9361_if_rx_clk_in_p (rx_clk_in),
-    .ad9361_if_rx_clk_in_n (1'b0),
-    .ad9361_if_rx_frame_in_p (rx_frame_in),
-    .ad9361_if_rx_frame_in_n (1'b0),
-    .ad9361_if_rx_data_in_p (rx_data_in),
-    .ad9361_if_rx_data_in_n (6'd0),
-    .ad9361_if_tx_clk_out_p (tx_clk_out),
-    .ad9361_if_tx_clk_out_n (),
-    .ad9361_if_tx_frame_out_p (tx_frame_out),
-    .ad9361_if_tx_frame_out_n (),
-    .ad9361_if_tx_data_out_p (tx_data_out),
-    .ad9361_if_tx_data_out_n (),
-    .ad9361_if_enable (enable),
-    .ad9361_if_txnrx (txnrx),
-    .delay_clk_clk (1'b0),
-    .hps_ddr_mem_ck (hps_ddr_clk_p),
-    .hps_ddr_mem_ck_n (hps_ddr_clk_n),
-    .hps_ddr_mem_a (hsp_ddr_a),
-    .hps_ddr_mem_act_n (hps_ddr_act_n),
-    .hps_ddr_mem_ba (hps_ddr_ba),
-    .hps_ddr_mem_bg (hps_ddr_bg),
-    .hps_ddr_mem_cke (hps_ddr_cke),
-    .hps_ddr_mem_cs_n (hps_ddr_cs_n),
-    .hps_ddr_mem_odt (hps_ddr_odt),
-    .hps_ddr_mem_reset_n (hps_ddr_reset_n),
-    .hps_ddr_mem_par (hps_ddr_par),
-    .hps_ddr_mem_alert_n (hps_ddr_alert_n),
-    .hps_ddr_mem_dqs (hps_ddr_dqs_p),
-    .hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
-    .hps_ddr_mem_dq (hps_ddr_dq),
-    .hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
-    .hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
-    .hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
-    .hps_gpio_gp_in (gpio_i),
-    .hps_gpio_gp_out (gpio_o),
-    .hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
-    .hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
-    .hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
-    .hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
-    .hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
-    .hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
-    .hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
-    .hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
-    .hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
-    .hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
-    .hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
-    .hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
-    .hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
-    .hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
-    .hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
-    .hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
-    .hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
-    .hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
-    .hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
-    .hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
-    .hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
-    .hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
-    .hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
-    .hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
-    .hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
-    .hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
-    .hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
-    .hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
-    .hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
-    .hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
-    .hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
-    .hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
-    .hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
-    .hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
-    .hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
-    .hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
-    .hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
-    .hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
-    .hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
-    .hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
-    .hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
-    .hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
-    .hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
-    .hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
-    .hps_spi0_mosi_o (spi_mosi),
-    .hps_spi0_miso_i (spi_miso),
-    .hps_spi0_ss_in_n (1'b1),
-    .hps_spi0_mosi_oe (),
-    .hps_spi0_ss0_n_o (spi_csn),
-    .hps_spi0_ss1_n_o (),
-    .hps_spi0_ss2_n_o (),
-    .hps_spi0_ss3_n_o (),
-    .hps_spi0_sclk_clk (spi_clk),
-    .hps_spi1_mosi_o (),
-    .hps_spi1_miso_i (1'b0),
-    .hps_spi1_ss_in_n (1'b1),
-    .hps_spi1_mosi_oe (),
-    .hps_spi1_ss0_n_o (),
-    .hps_spi1_ss1_n_o (),
-    .hps_spi1_ss2_n_o (),
-    .hps_spi1_ss3_n_o (),
-    .hps_spi1_sclk_clk (),
-    .sys_clk_clk (sys_clk),
-    .sys_reset_reset_n (sys_resetn),
-    .up_enable_up_enable (gpio_o[23]),
-    .up_txnrx_up_txnrx (gpio_o[24]));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From 10090a296e84fbf0a7092f8593089ddc44e16d77 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 15 Jun 2016 12:18:27 +0300
Subject: [PATCH 285/972] library/axi_dacfifo: Cosmetic changes

Rename a few registers and improve consistency.
---
 library/axi_dacfifo/axi_dacfifo_wr.v | 45 +++++++++++-----------------
 1 file changed, 17 insertions(+), 28 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index 55618ac17..8a0fb9cd2 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -167,7 +167,7 @@ module axi_dacfifo_wr (
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m1 = 'd0;
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m2 = 'd0;
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr = 'd0;
-  reg                                       dma_ready = 'd0;
+  reg                                       dma_ready = 1'b0;
   reg                                       dma_rst_m1 = 1'b0;
   reg                                       dma_rst_m2 = 1'b0;
   reg     [ 2:0]                            dma_mem_last_read_toggle_m = 3'b0;
@@ -181,8 +181,8 @@ module axi_dacfifo_wr (
   reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr_m1 = 'b0;
   reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr_m2 = 'b0;
   reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr = 'b0;
-  reg                                       axi_mem_valid = 'b0;
-  reg                                       axi_mem_valid_d = 'b0;
+  reg                                       axi_mem_rvalid = 1'b0;
+  reg                                       axi_mem_rvalid_d = 1'b0;
   reg                                       axi_mem_last = 1'b0;
   reg                                       axi_mem_last_d = 1'b0;
   reg     [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata = 'b0;
@@ -201,7 +201,6 @@ module axi_dacfifo_wr (
   reg                                       axi_xfer_init = 1'b0;
   reg                                       axi_werror = 1'b0;
   reg     [ 3:0]                            axi_wvalid_counter = 4'b0;
-  reg                                       axi_wr_active = 1'b0;
 
   reg                                       axi_last_transaction = 1'b0;
   reg                                       axi_last_transaction_d = 1'b0;
@@ -211,11 +210,13 @@ module axi_dacfifo_wr (
   wire    [(DMA_MEM_ADDRESS_WIDTH):0]       dma_mem_addr_diff_s;
   wire    [(DMA_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_s;
   wire                                      dma_mem_last_read_s;
+  wire                                      dma_mem_wea_s;
   wire                                      dma_rst_s;
 
   wire    [(AXI_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr_s;
   wire    [AXI_MEM_ADDRESS_WIDTH:0]         axi_mem_addr_diff_s;
   wire    [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata_s;
+  wire                                      axi_mem_rvalid_s;
   wire                                      axi_mem_last_s;
   wire                                      axi_mem_eot_s;
 
@@ -270,7 +271,7 @@ module axi_dacfifo_wr (
     .B_DATA_WIDTH (AXI_DATA_WIDTH))
   i_mem_asym (
     .clka (dma_clk),
-    .wea (dma_valid),
+    .wea (dma_mem_wea_s),
     .addra (dma_mem_waddr),
     .dina (dma_data),
     .clkb (axi_clk),
@@ -280,7 +281,7 @@ module axi_dacfifo_wr (
   ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
     .clk (axi_clk),
     .rst (axi_reset),
-    .valid (axi_mem_valid_d),
+    .valid (axi_mem_rvalid_d),
     .last (axi_mem_last_d),
     .data (axi_mem_rdata),
     .inf_valid (axi_wvalid),
@@ -316,15 +317,16 @@ module axi_dacfifo_wr (
                            (MEM_RATIO == 8) ? {dma_mem_raddr, 3'b0} :
                                               {dma_mem_raddr, 4'b0};
   assign dma_mem_last_read_s = dma_mem_last_read_toggle_m[2] ^ dma_mem_last_read_toggle_m[1];
+  assign dma_mem_wea_s = dma_xfer_req & dma_valid;
 
   always @(posedge dma_clk) begin
     if (dma_rst_s == 1'b1) begin
       dma_mem_waddr <= 'h0;
-      dma_mem_waddr_g <= 8'h0;
+      dma_mem_waddr_g <= 'h0;
       dma_mem_last_read_toggle_m <= 3'b0;
     end else begin
       dma_mem_last_read_toggle_m = {dma_mem_last_read_toggle_m[1:0], axi_mem_last_read_toggle};
-      if ((dma_xfer_req == 1'b1) && (dma_valid == 1'b1)) begin
+      if (dma_mem_wea_s == 1'b1) begin
         dma_mem_waddr <= dma_mem_waddr + 8'b1;
       end
       if (dma_mem_last_read_s == 1'b1) begin
@@ -429,30 +431,17 @@ module axi_dacfifo_wr (
     end
   end
 
-  always @(posedge axi_clk) begin
-    if(axi_resetn == 1'b0) begin
-      axi_wr_active = 1'b0;
-    end else begin
-      if (axi_mem_read_en == 1'b1) begin
-        axi_wr_active = 1'b1;
-      end
-      if ((axi_wlast == 1'b1) && (axi_wvalid == 1'b1)) begin
-        axi_wr_active = 1'b0;
-      end
-    end
-  end
-
   // If there is enough data and the AXI interface is ready, we can start to read
   // out data from the memory
 
-  assign axi_mem_valid_s =  axi_mem_read_en & axi_wready_s;
-  assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_valid_s : 1'b0;
   assign axi_mem_eot_s = axi_last_transaction_d & ~axi_last_transaction;
+  assign axi_mem_rvalid_s =  axi_mem_read_en & axi_wready_s;
+  assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_rvalid_s : 1'b0;
 
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
-      axi_mem_valid <= 1'b0;
-      axi_mem_valid_d <= 1'b0;
+      axi_mem_rvalid <= 1'b0;
+      axi_mem_rvalid_d <= 1'b0;
       axi_mem_last <= 1'b0;
       axi_mem_last_d <= 1'b0;
       axi_mem_rdata <= 'b0;
@@ -460,12 +449,12 @@ module axi_dacfifo_wr (
       axi_wvalid_counter <= 4'b0;
       axi_mem_last_read_toggle <= 1'b1;
     end else begin
-      axi_mem_valid <= axi_mem_valid_s;
-      axi_mem_valid_d <= axi_mem_valid;
+      axi_mem_rvalid <= axi_mem_rvalid_s;
+      axi_mem_rvalid_d <= axi_mem_rvalid;
       axi_mem_last <= axi_mem_last_s;
       axi_mem_last_d <= axi_mem_last;
       axi_mem_rdata <= axi_mem_rdata_s;
-      if (axi_mem_valid_s == 1'b1) begin
+      if (axi_mem_rvalid_s == 1'b1) begin
         axi_mem_raddr <= axi_mem_raddr + 1;
         axi_wvalid_counter <= (axi_wvalid_counter == axi_awlen) ? 4'b0 : axi_wvalid_counter + 1;
       end

From d5ce137c554a631993f4daaf4d4ca5ba9d210adf Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 15 Jun 2016 12:23:38 +0300
Subject: [PATCH 286/972] library/axi_dacfifo: Fix reset for a few registers

---
 library/axi_dacfifo/axi_dacfifo_wr.v | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index 8a0fb9cd2..b8b33dc3d 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -344,6 +344,7 @@ module axi_dacfifo_wr (
       dma_mem_raddr_m1 <= 'b0;
       dma_mem_raddr_m2 <= 'b0;
       dma_mem_raddr <= 'b0;
+      dma_ready <= 1'b0;
     end else begin
       dma_mem_raddr_m1 <= axi_mem_raddr_g;
       dma_mem_raddr_m2 <= dma_mem_raddr_m1;
@@ -448,6 +449,7 @@ module axi_dacfifo_wr (
       axi_mem_raddr <= 'b0;
       axi_wvalid_counter <= 4'b0;
       axi_mem_last_read_toggle <= 1'b1;
+      axi_mem_raddr_g <= 8'b0;
     end else begin
       axi_mem_rvalid <= axi_mem_rvalid_s;
       axi_mem_rvalid_d <= axi_mem_rvalid;

From 7c762f63a879c8a2a1f85e86b8161f2c95286c6c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 15 Jun 2016 13:41:33 +0300
Subject: [PATCH 287/972] library/axi_dacfifo: Fix the control logic of the
 write side

Fix the control logic for the AXI write transactions.
---
 library/axi_dacfifo/axi_dacfifo_wr.v | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index b8b33dc3d..893a70506 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -375,9 +375,6 @@ module axi_dacfifo_wr (
 
   // Read address generation for the asymmetric memory
 
-  // The asymmetric memory have to have enough data for at least one AXI burst,
-  // before the controller start an AXI write transaction.
-
   // CDC for the memory write address, xfer_req and xfer_last
 
   always @(posedge axi_clk) begin
@@ -412,6 +409,9 @@ module axi_dacfifo_wr (
 
   assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr_s} - axi_mem_raddr;
 
+  // The asymmetric memory have to have enough data for at least one AXI burst,
+  // before the controller start an AXI write transaction.
+
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
       axi_mem_read_en <= 1'b0;
@@ -419,9 +419,8 @@ module axi_dacfifo_wr (
       axi_mem_addr_diff <= 'b0;
     end else begin
       axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0];
-      // If there is a valid request and there is enough data in the memory or it's the end of the dma transaction
-      if ((axi_xfer_req_m[2] == 1'b1) && (axi_mem_read_en == 1'b0) && (axi_wr_active == 1'b0)) begin
-        if (((axi_mem_addr_diff > AXI_LENGTH) && (axi_last_transaction == 1'b0)) ||
+      if (axi_mem_read_en == 1'b0) begin
+        if (((axi_xfer_req_m[2] == 1'b1) && (axi_mem_addr_diff > AXI_LENGTH) && (axi_last_transaction_d == 1'b0)) ||
              (axi_last_transaction == 1'b1) && (axi_last_transaction_d == 1'b0)) begin
           axi_mem_read_en <= 1'b1;
         end
@@ -435,9 +434,9 @@ module axi_dacfifo_wr (
   // If there is enough data and the AXI interface is ready, we can start to read
   // out data from the memory
 
-  assign axi_mem_eot_s = axi_last_transaction_d & ~axi_last_transaction;
   assign axi_mem_rvalid_s =  axi_mem_read_en & axi_wready_s;
   assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_rvalid_s : 1'b0;
+  assign axi_mem_eot_s = axi_wlast & axi_last_transaction;
 
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
@@ -468,14 +467,12 @@ module axi_dacfifo_wr (
     end
   end
 
-
-
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
       axi_last_transaction <= 1'b0;
       axi_last_transaction_d <= 1'b0;
     end else begin
-      if (axi_xfer_last_m[2] == 1'b1) begin
+      if ((axi_xfer_req_m[2] == 1'b1) && (axi_xfer_last_m[2] == 1'b1)) begin
         axi_last_transaction <= 1'b1;
       end else if (axi_wlast == 1'b1) begin
         axi_last_transaction <= 1'b0;

From 80ce7aeb66a71234596b87dc1af483160ae14461 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 16 Jun 2016 16:40:57 -0400
Subject: [PATCH 288/972] util_adxcvr- updates

---
 library/util_adxcvr/util_adxcvr.v | 2444 +++++++++++++++++++++++++++++
 1 file changed, 2444 insertions(+)
 create mode 100644 library/util_adxcvr/util_adxcvr.v

diff --git a/library/util_adxcvr/util_adxcvr.v b/library/util_adxcvr/util_adxcvr.v
new file mode 100644
index 000000000..c7aa11320
--- /dev/null
+++ b/library/util_adxcvr/util_adxcvr.v
@@ -0,0 +1,2444 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module util_adxcvr (
+
+  input           up_rstn,
+  input           up_clk,
+
+  input           qpll_ref_clk_00,
+  input           cpll_ref_clk_00,
+
+  input           rx_00_p,
+  input           rx_00_n,
+  output          rx_out_clk_00,
+  input           rx_clk_00,
+  output  [ 3:0]  rx_charisk_00,
+  output  [ 3:0]  rx_disperr_00,
+  output  [ 3:0]  rx_notintable_00,
+  output  [31:0]  rx_data_00,
+  input           rx_calign_00,
+
+  output          tx_00_p,
+  output          tx_00_n,
+  output          tx_out_clk_00,
+  input           tx_clk_00,
+  input   [ 3:0]  tx_charisk_00,
+  input   [31:0]  tx_data_00,
+
+  input   [ 7:0]  up_cm_sel_00,
+  input           up_cm_enb_00,
+  input   [11:0]  up_cm_addr_00,
+  input           up_cm_wr_00,
+  input   [15:0]  up_cm_wdata_00,
+  output  [15:0]  up_cm_rdata_00,
+  output          up_cm_ready_00,
+  input   [ 7:0]  up_es_sel_00,
+  input           up_es_enb_00,
+  input   [11:0]  up_es_addr_00,
+  input           up_es_wr_00,
+  input   [15:0]  up_es_wdata_00,
+  output  [15:0]  up_es_rdata_00,
+  output          up_es_ready_00,
+  input           up_rx_pll_rst_00,
+  output          up_rx_pll_locked_00,
+  input           up_rx_rst_00,
+  input           up_rx_user_ready_00,
+  output          up_rx_rst_done_00,
+  input           up_rx_lpm_dfe_n_00,
+  input   [ 2:0]  up_rx_rate_00,
+  input   [ 1:0]  up_rx_sys_clk_sel_00,
+  input   [ 2:0]  up_rx_out_clk_sel_00,
+  input   [ 7:0]  up_rx_sel_00,
+  input           up_rx_enb_00,
+  input   [11:0]  up_rx_addr_00,
+  input           up_rx_wr_00,
+  input   [15:0]  up_rx_wdata_00,
+  output  [15:0]  up_rx_rdata_00,
+  output          up_rx_ready_00,
+  input           up_tx_pll_rst_00,
+  output          up_tx_pll_locked_00,
+  input           up_tx_rst_00,
+  input           up_tx_user_ready_00,
+  output          up_tx_rst_done_00,
+  input           up_tx_lpm_dfe_n_00,
+  input   [ 2:0]  up_tx_rate_00,
+  input   [ 1:0]  up_tx_sys_clk_sel_00,
+  input   [ 2:0]  up_tx_out_clk_sel_00,
+  input   [ 7:0]  up_tx_sel_00,
+  input           up_tx_enb_00,
+  input   [11:0]  up_tx_addr_00,
+  input           up_tx_wr_00,
+  input   [15:0]  up_tx_wdata_00,
+  output  [15:0]  up_tx_rdata_00,
+  output          up_tx_ready_00,
+
+  input           cpll_ref_clk_01,
+
+  input           rx_01_p,
+  input           rx_01_n,
+  output          rx_out_clk_01,
+  input           rx_clk_01,
+  output  [ 3:0]  rx_charisk_01,
+  output  [ 3:0]  rx_disperr_01,
+  output  [ 3:0]  rx_notintable_01,
+  output  [31:0]  rx_data_01,
+  input           rx_calign_01,
+
+  output          tx_01_p,
+  output          tx_01_n,
+  output          tx_out_clk_01,
+  input           tx_clk_01,
+  input   [ 3:0]  tx_charisk_01,
+  input   [31:0]  tx_data_01,
+
+  input   [ 7:0]  up_es_sel_01,
+  input           up_es_enb_01,
+  input   [11:0]  up_es_addr_01,
+  input           up_es_wr_01,
+  input   [15:0]  up_es_wdata_01,
+  output  [15:0]  up_es_rdata_01,
+  output          up_es_ready_01,
+  input           up_rx_pll_rst_01,
+  output          up_rx_pll_locked_01,
+  input           up_rx_rst_01,
+  input           up_rx_user_ready_01,
+  output          up_rx_rst_done_01,
+  input           up_rx_lpm_dfe_n_01,
+  input   [ 2:0]  up_rx_rate_01,
+  input   [ 1:0]  up_rx_sys_clk_sel_01,
+  input   [ 2:0]  up_rx_out_clk_sel_01,
+  input   [ 7:0]  up_rx_sel_01,
+  input           up_rx_enb_01,
+  input   [11:0]  up_rx_addr_01,
+  input           up_rx_wr_01,
+  input   [15:0]  up_rx_wdata_01,
+  output  [15:0]  up_rx_rdata_01,
+  output          up_rx_ready_01,
+  input           up_tx_pll_rst_01,
+  output          up_tx_pll_locked_01,
+  input           up_tx_rst_01,
+  input           up_tx_user_ready_01,
+  output          up_tx_rst_done_01,
+  input           up_tx_lpm_dfe_n_01,
+  input   [ 2:0]  up_tx_rate_01,
+  input   [ 1:0]  up_tx_sys_clk_sel_01,
+  input   [ 2:0]  up_tx_out_clk_sel_01,
+  input   [ 7:0]  up_tx_sel_01,
+  input           up_tx_enb_01,
+  input   [11:0]  up_tx_addr_01,
+  input           up_tx_wr_01,
+  input   [15:0]  up_tx_wdata_01,
+  output  [15:0]  up_tx_rdata_01,
+  output          up_tx_ready_01,
+
+  input           cpll_ref_clk_02,
+
+  input           rx_02_p,
+  input           rx_02_n,
+  output          rx_out_clk_02,
+  input           rx_clk_02,
+  output  [ 3:0]  rx_charisk_02,
+  output  [ 3:0]  rx_disperr_02,
+  output  [ 3:0]  rx_notintable_02,
+  output  [31:0]  rx_data_02,
+  input           rx_calign_02,
+
+  output          tx_02_p,
+  output          tx_02_n,
+  output          tx_out_clk_02,
+  input           tx_clk_02,
+  input   [ 3:0]  tx_charisk_02,
+  input   [31:0]  tx_data_02,
+
+  input   [ 7:0]  up_es_sel_02,
+  input           up_es_enb_02,
+  input   [11:0]  up_es_addr_02,
+  input           up_es_wr_02,
+  input   [15:0]  up_es_wdata_02,
+  output  [15:0]  up_es_rdata_02,
+  output          up_es_ready_02,
+  input           up_rx_pll_rst_02,
+  output          up_rx_pll_locked_02,
+  input           up_rx_rst_02,
+  input           up_rx_user_ready_02,
+  output          up_rx_rst_done_02,
+  input           up_rx_lpm_dfe_n_02,
+  input   [ 2:0]  up_rx_rate_02,
+  input   [ 1:0]  up_rx_sys_clk_sel_02,
+  input   [ 2:0]  up_rx_out_clk_sel_02,
+  input   [ 7:0]  up_rx_sel_02,
+  input           up_rx_enb_02,
+  input   [11:0]  up_rx_addr_02,
+  input           up_rx_wr_02,
+  input   [15:0]  up_rx_wdata_02,
+  output  [15:0]  up_rx_rdata_02,
+  output          up_rx_ready_02,
+  input           up_tx_pll_rst_02,
+  output          up_tx_pll_locked_02,
+  input           up_tx_rst_02,
+  input           up_tx_user_ready_02,
+  output          up_tx_rst_done_02,
+  input           up_tx_lpm_dfe_n_02,
+  input   [ 2:0]  up_tx_rate_02,
+  input   [ 1:0]  up_tx_sys_clk_sel_02,
+  input   [ 2:0]  up_tx_out_clk_sel_02,
+  input   [ 7:0]  up_tx_sel_02,
+  input           up_tx_enb_02,
+  input   [11:0]  up_tx_addr_02,
+  input           up_tx_wr_02,
+  input   [15:0]  up_tx_wdata_02,
+  output  [15:0]  up_tx_rdata_02,
+  output          up_tx_ready_02,
+
+  input           cpll_ref_clk_03,
+
+  input           rx_03_p,
+  input           rx_03_n,
+  output          rx_out_clk_03,
+  input           rx_clk_03,
+  output  [ 3:0]  rx_charisk_03,
+  output  [ 3:0]  rx_disperr_03,
+  output  [ 3:0]  rx_notintable_03,
+  output  [31:0]  rx_data_03,
+  input           rx_calign_03,
+
+  output          tx_03_p,
+  output          tx_03_n,
+  output          tx_out_clk_03,
+  input           tx_clk_03,
+  input   [ 3:0]  tx_charisk_03,
+  input   [31:0]  tx_data_03,
+
+  input   [ 7:0]  up_es_sel_03,
+  input           up_es_enb_03,
+  input   [11:0]  up_es_addr_03,
+  input           up_es_wr_03,
+  input   [15:0]  up_es_wdata_03,
+  output  [15:0]  up_es_rdata_03,
+  output          up_es_ready_03,
+  input           up_rx_pll_rst_03,
+  output          up_rx_pll_locked_03,
+  input           up_rx_rst_03,
+  input           up_rx_user_ready_03,
+  output          up_rx_rst_done_03,
+  input           up_rx_lpm_dfe_n_03,
+  input   [ 2:0]  up_rx_rate_03,
+  input   [ 1:0]  up_rx_sys_clk_sel_03,
+  input   [ 2:0]  up_rx_out_clk_sel_03,
+  input   [ 7:0]  up_rx_sel_03,
+  input           up_rx_enb_03,
+  input   [11:0]  up_rx_addr_03,
+  input           up_rx_wr_03,
+  input   [15:0]  up_rx_wdata_03,
+  output  [15:0]  up_rx_rdata_03,
+  output          up_rx_ready_03,
+  input           up_tx_pll_rst_03,
+  output          up_tx_pll_locked_03,
+  input           up_tx_rst_03,
+  input           up_tx_user_ready_03,
+  output          up_tx_rst_done_03,
+  input           up_tx_lpm_dfe_n_03,
+  input   [ 2:0]  up_tx_rate_03,
+  input   [ 1:0]  up_tx_sys_clk_sel_03,
+  input   [ 2:0]  up_tx_out_clk_sel_03,
+  input   [ 7:0]  up_tx_sel_03,
+  input           up_tx_enb_03,
+  input   [11:0]  up_tx_addr_03,
+  input           up_tx_wr_03,
+  input   [15:0]  up_tx_wdata_03,
+  output  [15:0]  up_tx_rdata_03,
+  output          up_tx_ready_03,
+
+  input           qpll_ref_clk_04,
+  input           cpll_ref_clk_04,
+
+  input           rx_04_p,
+  input           rx_04_n,
+  output          rx_out_clk_04,
+  input           rx_clk_04,
+  output  [ 3:0]  rx_charisk_04,
+  output  [ 3:0]  rx_disperr_04,
+  output  [ 3:0]  rx_notintable_04,
+  output  [31:0]  rx_data_04,
+  input           rx_calign_04,
+
+  output          tx_04_p,
+  output          tx_04_n,
+  output          tx_out_clk_04,
+  input           tx_clk_04,
+  input   [ 3:0]  tx_charisk_04,
+  input   [31:0]  tx_data_04,
+
+  input   [ 7:0]  up_cm_sel_04,
+  input           up_cm_enb_04,
+  input   [11:0]  up_cm_addr_04,
+  input           up_cm_wr_04,
+  input   [15:0]  up_cm_wdata_04,
+  output  [15:0]  up_cm_rdata_04,
+  output          up_cm_ready_04,
+  input   [ 7:0]  up_es_sel_04,
+  input           up_es_enb_04,
+  input   [11:0]  up_es_addr_04,
+  input           up_es_wr_04,
+  input   [15:0]  up_es_wdata_04,
+  output  [15:0]  up_es_rdata_04,
+  output          up_es_ready_04,
+  input           up_rx_pll_rst_04,
+  output          up_rx_pll_locked_04,
+  input           up_rx_rst_04,
+  input           up_rx_user_ready_04,
+  output          up_rx_rst_done_04,
+  input           up_rx_lpm_dfe_n_04,
+  input   [ 2:0]  up_rx_rate_04,
+  input   [ 1:0]  up_rx_sys_clk_sel_04,
+  input   [ 2:0]  up_rx_out_clk_sel_04,
+  input   [ 7:0]  up_rx_sel_04,
+  input           up_rx_enb_04,
+  input   [11:0]  up_rx_addr_04,
+  input           up_rx_wr_04,
+  input   [15:0]  up_rx_wdata_04,
+  output  [15:0]  up_rx_rdata_04,
+  output          up_rx_ready_04,
+  input           up_tx_pll_rst_04,
+  output          up_tx_pll_locked_04,
+  input           up_tx_rst_04,
+  input           up_tx_user_ready_04,
+  output          up_tx_rst_done_04,
+  input           up_tx_lpm_dfe_n_04,
+  input   [ 2:0]  up_tx_rate_04,
+  input   [ 1:0]  up_tx_sys_clk_sel_04,
+  input   [ 2:0]  up_tx_out_clk_sel_04,
+  input   [ 7:0]  up_tx_sel_04,
+  input           up_tx_enb_04,
+  input   [11:0]  up_tx_addr_04,
+  input           up_tx_wr_04,
+  input   [15:0]  up_tx_wdata_04,
+  output  [15:0]  up_tx_rdata_04,
+  output          up_tx_ready_04,
+
+  input           cpll_ref_clk_05,
+
+  input           rx_05_p,
+  input           rx_05_n,
+  output          rx_out_clk_05,
+  input           rx_clk_05,
+  output  [ 3:0]  rx_charisk_05,
+  output  [ 3:0]  rx_disperr_05,
+  output  [ 3:0]  rx_notintable_05,
+  output  [31:0]  rx_data_05,
+  input           rx_calign_05,
+
+  output          tx_05_p,
+  output          tx_05_n,
+  output          tx_out_clk_05,
+  input           tx_clk_05,
+  input   [ 3:0]  tx_charisk_05,
+  input   [31:0]  tx_data_05,
+
+  input   [ 7:0]  up_es_sel_05,
+  input           up_es_enb_05,
+  input   [11:0]  up_es_addr_05,
+  input           up_es_wr_05,
+  input   [15:0]  up_es_wdata_05,
+  output  [15:0]  up_es_rdata_05,
+  output          up_es_ready_05,
+  input           up_rx_pll_rst_05,
+  output          up_rx_pll_locked_05,
+  input           up_rx_rst_05,
+  input           up_rx_user_ready_05,
+  output          up_rx_rst_done_05,
+  input           up_rx_lpm_dfe_n_05,
+  input   [ 2:0]  up_rx_rate_05,
+  input   [ 1:0]  up_rx_sys_clk_sel_05,
+  input   [ 2:0]  up_rx_out_clk_sel_05,
+  input   [ 7:0]  up_rx_sel_05,
+  input           up_rx_enb_05,
+  input   [11:0]  up_rx_addr_05,
+  input           up_rx_wr_05,
+  input   [15:0]  up_rx_wdata_05,
+  output  [15:0]  up_rx_rdata_05,
+  output          up_rx_ready_05,
+  input           up_tx_pll_rst_05,
+  output          up_tx_pll_locked_05,
+  input           up_tx_rst_05,
+  input           up_tx_user_ready_05,
+  output          up_tx_rst_done_05,
+  input           up_tx_lpm_dfe_n_05,
+  input   [ 2:0]  up_tx_rate_05,
+  input   [ 1:0]  up_tx_sys_clk_sel_05,
+  input   [ 2:0]  up_tx_out_clk_sel_05,
+  input   [ 7:0]  up_tx_sel_05,
+  input           up_tx_enb_05,
+  input   [11:0]  up_tx_addr_05,
+  input           up_tx_wr_05,
+  input   [15:0]  up_tx_wdata_05,
+  output  [15:0]  up_tx_rdata_05,
+  output          up_tx_ready_05,
+
+  input           cpll_ref_clk_06,
+
+  input           rx_06_p,
+  input           rx_06_n,
+  output          rx_out_clk_06,
+  input           rx_clk_06,
+  output  [ 3:0]  rx_charisk_06,
+  output  [ 3:0]  rx_disperr_06,
+  output  [ 3:0]  rx_notintable_06,
+  output  [31:0]  rx_data_06,
+  input           rx_calign_06,
+
+  output          tx_06_p,
+  output          tx_06_n,
+  output          tx_out_clk_06,
+  input           tx_clk_06,
+  input   [ 3:0]  tx_charisk_06,
+  input   [31:0]  tx_data_06,
+
+  input   [ 7:0]  up_es_sel_06,
+  input           up_es_enb_06,
+  input   [11:0]  up_es_addr_06,
+  input           up_es_wr_06,
+  input   [15:0]  up_es_wdata_06,
+  output  [15:0]  up_es_rdata_06,
+  output          up_es_ready_06,
+  input           up_rx_pll_rst_06,
+  output          up_rx_pll_locked_06,
+  input           up_rx_rst_06,
+  input           up_rx_user_ready_06,
+  output          up_rx_rst_done_06,
+  input           up_rx_lpm_dfe_n_06,
+  input   [ 2:0]  up_rx_rate_06,
+  input   [ 1:0]  up_rx_sys_clk_sel_06,
+  input   [ 2:0]  up_rx_out_clk_sel_06,
+  input   [ 7:0]  up_rx_sel_06,
+  input           up_rx_enb_06,
+  input   [11:0]  up_rx_addr_06,
+  input           up_rx_wr_06,
+  input   [15:0]  up_rx_wdata_06,
+  output  [15:0]  up_rx_rdata_06,
+  output          up_rx_ready_06,
+  input           up_tx_pll_rst_06,
+  output          up_tx_pll_locked_06,
+  input           up_tx_rst_06,
+  input           up_tx_user_ready_06,
+  output          up_tx_rst_done_06,
+  input           up_tx_lpm_dfe_n_06,
+  input   [ 2:0]  up_tx_rate_06,
+  input   [ 1:0]  up_tx_sys_clk_sel_06,
+  input   [ 2:0]  up_tx_out_clk_sel_06,
+  input   [ 7:0]  up_tx_sel_06,
+  input           up_tx_enb_06,
+  input   [11:0]  up_tx_addr_06,
+  input           up_tx_wr_06,
+  input   [15:0]  up_tx_wdata_06,
+  output  [15:0]  up_tx_rdata_06,
+  output          up_tx_ready_06,
+
+  input           cpll_ref_clk_07,
+
+  input           rx_07_p,
+  input           rx_07_n,
+  output          rx_out_clk_07,
+  input           rx_clk_07,
+  output  [ 3:0]  rx_charisk_07,
+  output  [ 3:0]  rx_disperr_07,
+  output  [ 3:0]  rx_notintable_07,
+  output  [31:0]  rx_data_07,
+  input           rx_calign_07,
+
+  output          tx_07_p,
+  output          tx_07_n,
+  output          tx_out_clk_07,
+  input           tx_clk_07,
+  input   [ 3:0]  tx_charisk_07,
+  input   [31:0]  tx_data_07,
+
+  input   [ 7:0]  up_es_sel_07,
+  input           up_es_enb_07,
+  input   [11:0]  up_es_addr_07,
+  input           up_es_wr_07,
+  input   [15:0]  up_es_wdata_07,
+  output  [15:0]  up_es_rdata_07,
+  output          up_es_ready_07,
+  input           up_rx_pll_rst_07,
+  output          up_rx_pll_locked_07,
+  input           up_rx_rst_07,
+  input           up_rx_user_ready_07,
+  output          up_rx_rst_done_07,
+  input           up_rx_lpm_dfe_n_07,
+  input   [ 2:0]  up_rx_rate_07,
+  input   [ 1:0]  up_rx_sys_clk_sel_07,
+  input   [ 2:0]  up_rx_out_clk_sel_07,
+  input   [ 7:0]  up_rx_sel_07,
+  input           up_rx_enb_07,
+  input   [11:0]  up_rx_addr_07,
+  input           up_rx_wr_07,
+  input   [15:0]  up_rx_wdata_07,
+  output  [15:0]  up_rx_rdata_07,
+  output          up_rx_ready_07,
+  input           up_tx_pll_rst_07,
+  output          up_tx_pll_locked_07,
+  input           up_tx_rst_07,
+  input           up_tx_user_ready_07,
+  output          up_tx_rst_done_07,
+  input           up_tx_lpm_dfe_n_07,
+  input   [ 2:0]  up_tx_rate_07,
+  input   [ 1:0]  up_tx_sys_clk_sel_07,
+  input   [ 2:0]  up_tx_out_clk_sel_07,
+  input   [ 7:0]  up_tx_sel_07,
+  input           up_tx_enb_07,
+  input   [11:0]  up_tx_addr_07,
+  input           up_tx_wr_07,
+  input   [15:0]  up_tx_wdata_07,
+  output  [15:0]  up_tx_rdata_07,
+  output          up_tx_ready_07,
+
+  input           qpll_ref_clk_08,
+  input           cpll_ref_clk_08,
+
+  input           rx_08_p,
+  input           rx_08_n,
+  output          rx_out_clk_08,
+  input           rx_clk_08,
+  output  [ 3:0]  rx_charisk_08,
+  output  [ 3:0]  rx_disperr_08,
+  output  [ 3:0]  rx_notintable_08,
+  output  [31:0]  rx_data_08,
+  input           rx_calign_08,
+
+  output          tx_08_p,
+  output          tx_08_n,
+  output          tx_out_clk_08,
+  input           tx_clk_08,
+  input   [ 3:0]  tx_charisk_08,
+  input   [31:0]  tx_data_08,
+
+  input   [ 7:0]  up_cm_sel_08,
+  input           up_cm_enb_08,
+  input   [11:0]  up_cm_addr_08,
+  input           up_cm_wr_08,
+  input   [15:0]  up_cm_wdata_08,
+  output  [15:0]  up_cm_rdata_08,
+  output          up_cm_ready_08,
+  input   [ 7:0]  up_es_sel_08,
+  input           up_es_enb_08,
+  input   [11:0]  up_es_addr_08,
+  input           up_es_wr_08,
+  input   [15:0]  up_es_wdata_08,
+  output  [15:0]  up_es_rdata_08,
+  output          up_es_ready_08,
+  input           up_rx_pll_rst_08,
+  output          up_rx_pll_locked_08,
+  input           up_rx_rst_08,
+  input           up_rx_user_ready_08,
+  output          up_rx_rst_done_08,
+  input           up_rx_lpm_dfe_n_08,
+  input   [ 2:0]  up_rx_rate_08,
+  input   [ 1:0]  up_rx_sys_clk_sel_08,
+  input   [ 2:0]  up_rx_out_clk_sel_08,
+  input   [ 7:0]  up_rx_sel_08,
+  input           up_rx_enb_08,
+  input   [11:0]  up_rx_addr_08,
+  input           up_rx_wr_08,
+  input   [15:0]  up_rx_wdata_08,
+  output  [15:0]  up_rx_rdata_08,
+  output          up_rx_ready_08,
+  input           up_tx_pll_rst_08,
+  output          up_tx_pll_locked_08,
+  input           up_tx_rst_08,
+  input           up_tx_user_ready_08,
+  output          up_tx_rst_done_08,
+  input           up_tx_lpm_dfe_n_08,
+  input   [ 2:0]  up_tx_rate_08,
+  input   [ 1:0]  up_tx_sys_clk_sel_08,
+  input   [ 2:0]  up_tx_out_clk_sel_08,
+  input   [ 7:0]  up_tx_sel_08,
+  input           up_tx_enb_08,
+  input   [11:0]  up_tx_addr_08,
+  input           up_tx_wr_08,
+  input   [15:0]  up_tx_wdata_08,
+  output  [15:0]  up_tx_rdata_08,
+  output          up_tx_ready_08,
+
+  input           cpll_ref_clk_09,
+
+  input           rx_09_p,
+  input           rx_09_n,
+  output          rx_out_clk_09,
+  input           rx_clk_09,
+  output  [ 3:0]  rx_charisk_09,
+  output  [ 3:0]  rx_disperr_09,
+  output  [ 3:0]  rx_notintable_09,
+  output  [31:0]  rx_data_09,
+  input           rx_calign_09,
+
+  output          tx_09_p,
+  output          tx_09_n,
+  output          tx_out_clk_09,
+  input           tx_clk_09,
+  input   [ 3:0]  tx_charisk_09,
+  input   [31:0]  tx_data_09,
+
+  input   [ 7:0]  up_es_sel_09,
+  input           up_es_enb_09,
+  input   [11:0]  up_es_addr_09,
+  input           up_es_wr_09,
+  input   [15:0]  up_es_wdata_09,
+  output  [15:0]  up_es_rdata_09,
+  output          up_es_ready_09,
+  input           up_rx_pll_rst_09,
+  output          up_rx_pll_locked_09,
+  input           up_rx_rst_09,
+  input           up_rx_user_ready_09,
+  output          up_rx_rst_done_09,
+  input           up_rx_lpm_dfe_n_09,
+  input   [ 2:0]  up_rx_rate_09,
+  input   [ 1:0]  up_rx_sys_clk_sel_09,
+  input   [ 2:0]  up_rx_out_clk_sel_09,
+  input   [ 7:0]  up_rx_sel_09,
+  input           up_rx_enb_09,
+  input   [11:0]  up_rx_addr_09,
+  input           up_rx_wr_09,
+  input   [15:0]  up_rx_wdata_09,
+  output  [15:0]  up_rx_rdata_09,
+  output          up_rx_ready_09,
+  input           up_tx_pll_rst_09,
+  output          up_tx_pll_locked_09,
+  input           up_tx_rst_09,
+  input           up_tx_user_ready_09,
+  output          up_tx_rst_done_09,
+  input           up_tx_lpm_dfe_n_09,
+  input   [ 2:0]  up_tx_rate_09,
+  input   [ 1:0]  up_tx_sys_clk_sel_09,
+  input   [ 2:0]  up_tx_out_clk_sel_09,
+  input   [ 7:0]  up_tx_sel_09,
+  input           up_tx_enb_09,
+  input   [11:0]  up_tx_addr_09,
+  input           up_tx_wr_09,
+  input   [15:0]  up_tx_wdata_09,
+  output  [15:0]  up_tx_rdata_09,
+  output          up_tx_ready_09,
+
+  input           cpll_ref_clk_10,
+
+  input           rx_10_p,
+  input           rx_10_n,
+  output          rx_out_clk_10,
+  input           rx_clk_10,
+  output  [ 3:0]  rx_charisk_10,
+  output  [ 3:0]  rx_disperr_10,
+  output  [ 3:0]  rx_notintable_10,
+  output  [31:0]  rx_data_10,
+  input           rx_calign_10,
+
+  output          tx_10_p,
+  output          tx_10_n,
+  output          tx_out_clk_10,
+  input           tx_clk_10,
+  input   [ 3:0]  tx_charisk_10,
+  input   [31:0]  tx_data_10,
+
+  input   [ 7:0]  up_es_sel_10,
+  input           up_es_enb_10,
+  input   [11:0]  up_es_addr_10,
+  input           up_es_wr_10,
+  input   [15:0]  up_es_wdata_10,
+  output  [15:0]  up_es_rdata_10,
+  output          up_es_ready_10,
+  input           up_rx_pll_rst_10,
+  output          up_rx_pll_locked_10,
+  input           up_rx_rst_10,
+  input           up_rx_user_ready_10,
+  output          up_rx_rst_done_10,
+  input           up_rx_lpm_dfe_n_10,
+  input   [ 2:0]  up_rx_rate_10,
+  input   [ 1:0]  up_rx_sys_clk_sel_10,
+  input   [ 2:0]  up_rx_out_clk_sel_10,
+  input   [ 7:0]  up_rx_sel_10,
+  input           up_rx_enb_10,
+  input   [11:0]  up_rx_addr_10,
+  input           up_rx_wr_10,
+  input   [15:0]  up_rx_wdata_10,
+  output  [15:0]  up_rx_rdata_10,
+  output          up_rx_ready_10,
+  input           up_tx_pll_rst_10,
+  output          up_tx_pll_locked_10,
+  input           up_tx_rst_10,
+  input           up_tx_user_ready_10,
+  output          up_tx_rst_done_10,
+  input           up_tx_lpm_dfe_n_10,
+  input   [ 2:0]  up_tx_rate_10,
+  input   [ 1:0]  up_tx_sys_clk_sel_10,
+  input   [ 2:0]  up_tx_out_clk_sel_10,
+  input   [ 7:0]  up_tx_sel_10,
+  input           up_tx_enb_10,
+  input   [11:0]  up_tx_addr_10,
+  input           up_tx_wr_10,
+  input   [15:0]  up_tx_wdata_10,
+  output  [15:0]  up_tx_rdata_10,
+  output          up_tx_ready_10,
+
+  input           cpll_ref_clk_11,
+
+  input           rx_11_p,
+  input           rx_11_n,
+  output          rx_out_clk_11,
+  input           rx_clk_11,
+  output  [ 3:0]  rx_charisk_11,
+  output  [ 3:0]  rx_disperr_11,
+  output  [ 3:0]  rx_notintable_11,
+  output  [31:0]  rx_data_11,
+  input           rx_calign_11,
+
+  output          tx_11_p,
+  output          tx_11_n,
+  output          tx_out_clk_11,
+  input           tx_clk_11,
+  input   [ 3:0]  tx_charisk_11,
+  input   [31:0]  tx_data_11,
+
+  input   [ 7:0]  up_es_sel_11,
+  input           up_es_enb_11,
+  input   [11:0]  up_es_addr_11,
+  input           up_es_wr_11,
+  input   [15:0]  up_es_wdata_11,
+  output  [15:0]  up_es_rdata_11,
+  output          up_es_ready_11,
+  input           up_rx_pll_rst_11,
+  output          up_rx_pll_locked_11,
+  input           up_rx_rst_11,
+  input           up_rx_user_ready_11,
+  output          up_rx_rst_done_11,
+  input           up_rx_lpm_dfe_n_11,
+  input   [ 2:0]  up_rx_rate_11,
+  input   [ 1:0]  up_rx_sys_clk_sel_11,
+  input   [ 2:0]  up_rx_out_clk_sel_11,
+  input   [ 7:0]  up_rx_sel_11,
+  input           up_rx_enb_11,
+  input   [11:0]  up_rx_addr_11,
+  input           up_rx_wr_11,
+  input   [15:0]  up_rx_wdata_11,
+  output  [15:0]  up_rx_rdata_11,
+  output          up_rx_ready_11,
+  input           up_tx_pll_rst_11,
+  output          up_tx_pll_locked_11,
+  input           up_tx_rst_11,
+  input           up_tx_user_ready_11,
+  output          up_tx_rst_done_11,
+  input           up_tx_lpm_dfe_n_11,
+  input   [ 2:0]  up_tx_rate_11,
+  input   [ 1:0]  up_tx_sys_clk_sel_11,
+  input   [ 2:0]  up_tx_out_clk_sel_11,
+  input   [ 7:0]  up_tx_sel_11,
+  input           up_tx_enb_11,
+  input   [11:0]  up_tx_addr_11,
+  input           up_tx_wr_11,
+  input   [15:0]  up_tx_wdata_11,
+  output  [15:0]  up_tx_rdata_11,
+  output          up_tx_ready_11,
+
+  input           qpll_ref_clk_12,
+  input           cpll_ref_clk_12,
+
+  input           rx_12_p,
+  input           rx_12_n,
+  output          rx_out_clk_12,
+  input           rx_clk_12,
+  output  [ 3:0]  rx_charisk_12,
+  output  [ 3:0]  rx_disperr_12,
+  output  [ 3:0]  rx_notintable_12,
+  output  [31:0]  rx_data_12,
+  input           rx_calign_12,
+
+  output          tx_12_p,
+  output          tx_12_n,
+  output          tx_out_clk_12,
+  input           tx_clk_12,
+  input   [ 3:0]  tx_charisk_12,
+  input   [31:0]  tx_data_12,
+
+  input   [ 7:0]  up_cm_sel_12,
+  input           up_cm_enb_12,
+  input   [11:0]  up_cm_addr_12,
+  input           up_cm_wr_12,
+  input   [15:0]  up_cm_wdata_12,
+  output  [15:0]  up_cm_rdata_12,
+  output          up_cm_ready_12,
+  input   [ 7:0]  up_es_sel_12,
+  input           up_es_enb_12,
+  input   [11:0]  up_es_addr_12,
+  input           up_es_wr_12,
+  input   [15:0]  up_es_wdata_12,
+  output  [15:0]  up_es_rdata_12,
+  output          up_es_ready_12,
+  input           up_rx_pll_rst_12,
+  output          up_rx_pll_locked_12,
+  input           up_rx_rst_12,
+  input           up_rx_user_ready_12,
+  output          up_rx_rst_done_12,
+  input           up_rx_lpm_dfe_n_12,
+  input   [ 2:0]  up_rx_rate_12,
+  input   [ 1:0]  up_rx_sys_clk_sel_12,
+  input   [ 2:0]  up_rx_out_clk_sel_12,
+  input   [ 7:0]  up_rx_sel_12,
+  input           up_rx_enb_12,
+  input   [11:0]  up_rx_addr_12,
+  input           up_rx_wr_12,
+  input   [15:0]  up_rx_wdata_12,
+  output  [15:0]  up_rx_rdata_12,
+  output          up_rx_ready_12,
+  input           up_tx_pll_rst_12,
+  output          up_tx_pll_locked_12,
+  input           up_tx_rst_12,
+  input           up_tx_user_ready_12,
+  output          up_tx_rst_done_12,
+  input           up_tx_lpm_dfe_n_12,
+  input   [ 2:0]  up_tx_rate_12,
+  input   [ 1:0]  up_tx_sys_clk_sel_12,
+  input   [ 2:0]  up_tx_out_clk_sel_12,
+  input   [ 7:0]  up_tx_sel_12,
+  input           up_tx_enb_12,
+  input   [11:0]  up_tx_addr_12,
+  input           up_tx_wr_12,
+  input   [15:0]  up_tx_wdata_12,
+  output  [15:0]  up_tx_rdata_12,
+  output          up_tx_ready_12,
+
+  input           cpll_ref_clk_13,
+
+  input           rx_13_p,
+  input           rx_13_n,
+  output          rx_out_clk_13,
+  input           rx_clk_13,
+  output  [ 3:0]  rx_charisk_13,
+  output  [ 3:0]  rx_disperr_13,
+  output  [ 3:0]  rx_notintable_13,
+  output  [31:0]  rx_data_13,
+  input           rx_calign_13,
+
+  output          tx_13_p,
+  output          tx_13_n,
+  output          tx_out_clk_13,
+  input           tx_clk_13,
+  input   [ 3:0]  tx_charisk_13,
+  input   [31:0]  tx_data_13,
+
+  input   [ 7:0]  up_es_sel_13,
+  input           up_es_enb_13,
+  input   [11:0]  up_es_addr_13,
+  input           up_es_wr_13,
+  input   [15:0]  up_es_wdata_13,
+  output  [15:0]  up_es_rdata_13,
+  output          up_es_ready_13,
+  input           up_rx_pll_rst_13,
+  output          up_rx_pll_locked_13,
+  input           up_rx_rst_13,
+  input           up_rx_user_ready_13,
+  output          up_rx_rst_done_13,
+  input           up_rx_lpm_dfe_n_13,
+  input   [ 2:0]  up_rx_rate_13,
+  input   [ 1:0]  up_rx_sys_clk_sel_13,
+  input   [ 2:0]  up_rx_out_clk_sel_13,
+  input   [ 7:0]  up_rx_sel_13,
+  input           up_rx_enb_13,
+  input   [11:0]  up_rx_addr_13,
+  input           up_rx_wr_13,
+  input   [15:0]  up_rx_wdata_13,
+  output  [15:0]  up_rx_rdata_13,
+  output          up_rx_ready_13,
+  input           up_tx_pll_rst_13,
+  output          up_tx_pll_locked_13,
+  input           up_tx_rst_13,
+  input           up_tx_user_ready_13,
+  output          up_tx_rst_done_13,
+  input           up_tx_lpm_dfe_n_13,
+  input   [ 2:0]  up_tx_rate_13,
+  input   [ 1:0]  up_tx_sys_clk_sel_13,
+  input   [ 2:0]  up_tx_out_clk_sel_13,
+  input   [ 7:0]  up_tx_sel_13,
+  input           up_tx_enb_13,
+  input   [11:0]  up_tx_addr_13,
+  input           up_tx_wr_13,
+  input   [15:0]  up_tx_wdata_13,
+  output  [15:0]  up_tx_rdata_13,
+  output          up_tx_ready_13,
+
+  input           cpll_ref_clk_14,
+
+  input           rx_14_p,
+  input           rx_14_n,
+  output          rx_out_clk_14,
+  input           rx_clk_14,
+  output  [ 3:0]  rx_charisk_14,
+  output  [ 3:0]  rx_disperr_14,
+  output  [ 3:0]  rx_notintable_14,
+  output  [31:0]  rx_data_14,
+  input           rx_calign_14,
+
+  output          tx_14_p,
+  output          tx_14_n,
+  output          tx_out_clk_14,
+  input           tx_clk_14,
+  input   [ 3:0]  tx_charisk_14,
+  input   [31:0]  tx_data_14,
+
+  input   [ 7:0]  up_es_sel_14,
+  input           up_es_enb_14,
+  input   [11:0]  up_es_addr_14,
+  input           up_es_wr_14,
+  input   [15:0]  up_es_wdata_14,
+  output  [15:0]  up_es_rdata_14,
+  output          up_es_ready_14,
+  input           up_rx_pll_rst_14,
+  output          up_rx_pll_locked_14,
+  input           up_rx_rst_14,
+  input           up_rx_user_ready_14,
+  output          up_rx_rst_done_14,
+  input           up_rx_lpm_dfe_n_14,
+  input   [ 2:0]  up_rx_rate_14,
+  input   [ 1:0]  up_rx_sys_clk_sel_14,
+  input   [ 2:0]  up_rx_out_clk_sel_14,
+  input   [ 7:0]  up_rx_sel_14,
+  input           up_rx_enb_14,
+  input   [11:0]  up_rx_addr_14,
+  input           up_rx_wr_14,
+  input   [15:0]  up_rx_wdata_14,
+  output  [15:0]  up_rx_rdata_14,
+  output          up_rx_ready_14,
+  input           up_tx_pll_rst_14,
+  output          up_tx_pll_locked_14,
+  input           up_tx_rst_14,
+  input           up_tx_user_ready_14,
+  output          up_tx_rst_done_14,
+  input           up_tx_lpm_dfe_n_14,
+  input   [ 2:0]  up_tx_rate_14,
+  input   [ 1:0]  up_tx_sys_clk_sel_14,
+  input   [ 2:0]  up_tx_out_clk_sel_14,
+  input   [ 7:0]  up_tx_sel_14,
+  input           up_tx_enb_14,
+  input   [11:0]  up_tx_addr_14,
+  input           up_tx_wr_14,
+  input   [15:0]  up_tx_wdata_14,
+  output  [15:0]  up_tx_rdata_14,
+  output          up_tx_ready_14,
+
+  input           cpll_ref_clk_15,
+
+  input           rx_15_p,
+  input           rx_15_n,
+  output          rx_out_clk_15,
+  input           rx_clk_15,
+  output  [ 3:0]  rx_charisk_15,
+  output  [ 3:0]  rx_disperr_15,
+  output  [ 3:0]  rx_notintable_15,
+  output  [31:0]  rx_data_15,
+  input           rx_calign_15,
+
+  output          tx_15_p,
+  output          tx_15_n,
+  output          tx_out_clk_15,
+  input           tx_clk_15,
+  input   [ 3:0]  tx_charisk_15,
+  input   [31:0]  tx_data_15,
+
+  input   [ 7:0]  up_es_sel_15,
+  input           up_es_enb_15,
+  input   [11:0]  up_es_addr_15,
+  input           up_es_wr_15,
+  input   [15:0]  up_es_wdata_15,
+  output  [15:0]  up_es_rdata_15,
+  output          up_es_ready_15,
+  input           up_rx_pll_rst_15,
+  output          up_rx_pll_locked_15,
+  input           up_rx_rst_15,
+  input           up_rx_user_ready_15,
+  output          up_rx_rst_done_15,
+  input           up_rx_lpm_dfe_n_15,
+  input   [ 2:0]  up_rx_rate_15,
+  input   [ 1:0]  up_rx_sys_clk_sel_15,
+  input   [ 2:0]  up_rx_out_clk_sel_15,
+  input   [ 7:0]  up_rx_sel_15,
+  input           up_rx_enb_15,
+  input   [11:0]  up_rx_addr_15,
+  input           up_rx_wr_15,
+  input   [15:0]  up_rx_wdata_15,
+  output  [15:0]  up_rx_rdata_15,
+  output          up_rx_ready_15,
+  input           up_tx_pll_rst_15,
+  output          up_tx_pll_locked_15,
+  input           up_tx_rst_15,
+  input           up_tx_user_ready_15,
+  output          up_tx_rst_done_15,
+  input           up_tx_lpm_dfe_n_15,
+  input   [ 2:0]  up_tx_rate_15,
+  input   [ 1:0]  up_tx_sys_clk_sel_15,
+  input   [ 2:0]  up_tx_out_clk_sel_15,
+  input   [ 7:0]  up_tx_sel_15,
+  input           up_tx_enb_15,
+  input   [11:0]  up_tx_addr_15,
+  input           up_tx_wr_15,
+  input   [15:0]  up_tx_wdata_15,
+  output  [15:0]  up_tx_rdata_15,
+  output          up_tx_ready_15);
+
+  // parameters
+
+  parameter   integer XCVR_ID = 0;
+  parameter   integer GTH_OR_GTX_N = 0;
+  parameter   integer CPLL_TX_OR_RX_N = 0;
+  parameter   integer CPLL_FBDIV = 2;
+  parameter   integer QPLL_REFCLK_DIV = 2;
+  parameter   integer QPLL_FBDIV_RATIO = 1;
+  parameter   integer RX_OUT_DIV = 1;
+  parameter   integer RX_CLK25_DIV = 10;
+  parameter   integer RX_CLKBUF_ENABLE = 0;
+  parameter   integer TX_OUT_DIV = 1;
+  parameter   integer TX_CLK25_DIV = 10;
+  parameter   integer TX_CLKBUF_ENABLE = 0;
+  parameter   [31:0]  PMA_RSV = 32'h00018480;
+  parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff20400020;
+  parameter   [26:0]  QPLL_CFG = 27'h06801C1;
+  parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000;
+
+  // internal signals
+
+  wire            qpll2ch_clk_00;
+  wire            qpll2ch_ref_clk_00;
+  wire            qpll2ch_locked_00;
+  wire            up_qpll_rst_00;
+  wire            qpll2ch_clk_04;
+  wire            qpll2ch_ref_clk_04;
+  wire            qpll2ch_locked_04;
+  wire            up_qpll_rst_04;
+  wire            qpll2ch_clk_08;
+  wire            qpll2ch_ref_clk_08;
+  wire            qpll2ch_locked_08;
+  wire            up_qpll_rst_08;
+  wire            qpll2ch_clk_12;
+  wire            qpll2ch_ref_clk_12;
+  wire            qpll2ch_locked_12;
+  wire            up_qpll_rst_12;
+
+  // quad controls
+
+  assign up_qpll_rst_00 = (CPLL_TX_OR_RX_N == 0) ? up_tx_00.pll_rst : up_rx_00.pll_rst;
+  assign up_qpll_rst_04 = (CPLL_TX_OR_RX_N == 0) ? up_tx_04.pll_rst : up_rx_04.pll_rst;
+  assign up_qpll_rst_08 = (CPLL_TX_OR_RX_N == 0) ? up_tx_08.pll_rst : up_rx_08.pll_rst;
+  assign up_qpll_rst_12 = (CPLL_TX_OR_RX_N == 0) ? up_tx_12.pll_rst : up_rx_12.pll_rst;
+
+  // instantiations
+
+  generate
+  if (NUM_OF_LANES >= 1) begin
+  util_adxcvr_xcm #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
+    .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
+    .QPLL_CFG (QPLL_CFG),
+    .QPLL_FBDIV (QPLL_FBDIV))
+  i_xcm_00 (
+    .qpll_ref_clk (qpll_ref_clk_00),
+    .qpll2ch_clk (qpll2ch_clk_00),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
+    .qpll2ch_locked (qpll2ch_locked_00),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_qpll_rst (up_qpll_rst_00),
+    .up_cm_sel (up_cm_sel_00),
+    .up_cm_enb (up_cm_enb_00),
+    .up_cm_addr (up_cm_addr_00),
+    .up_cm_wr (up_cm_wr_00),
+    .up_cm_wdata (up_cm_wdata_00),
+    .up_cm_rdata (up_cm_rdata_00),
+    .up_cm_ready (up_cm_ready_00));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 1) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_00 (
+    .qpll2ch_clk (qpll2ch_clk_00),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
+    .qpll2ch_locked (qpll2ch_locked_00),
+    .cpll_ref_clk (cpll_ref_clk_00),
+    .rx_p (rx_00_p),
+    .rx_n (rx_00_n),
+    .rx_out_clk (rx_out_clk_00),
+    .rx_clk (rx_clk_00),
+    .rx_charisk (rx_charisk_00),
+    .rx_disperr (rx_disperr_00),
+    .rx_notintable (rx_notintable_00),
+    .rx_data (rx_data_00),
+    .rx_calign (rx_calign_00),
+    .tx_p (tx_00_p),
+    .tx_n (tx_00_n),
+    .tx_out_clk (tx_out_clk_00),
+    .tx_clk (tx_clk_00),
+    .tx_charisk (tx_charisk_00),
+    .tx_data (tx_data_00),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_00),
+    .up_es_enb (up_es_enb_00),
+    .up_es_addr (up_es_addr_00),
+    .up_es_wr (up_es_wr_00),
+    .up_es_wdata (up_es_wdata_00),
+    .up_es_rdata (up_es_rdata_00),
+    .up_es_ready (up_es_ready_00),
+    .up_rx_pll_rst (up_rx_pll_rst_00),
+    .up_rx_pll_locked (up_rx_pll_locked_00),
+    .up_rx_rst (up_rx_rst_00),
+    .up_rx_user_ready (up_rx_user_ready_00),
+    .up_rx_rst_done (up_rx_rst_done_00),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_00),
+    .up_rx_rate (up_rx_rate_00),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_00),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_00),
+    .up_rx_sel (up_rx_sel_00),
+    .up_rx_enb (up_rx_enb_00),
+    .up_rx_addr (up_rx_addr_00),
+    .up_rx_wr (up_rx_wr_00),
+    .up_rx_wdata (up_rx_wdata_00),
+    .up_rx_rdata (up_rx_rdata_00),
+    .up_rx_ready (up_rx_ready_00),
+    .up_tx_pll_rst (up_tx_pll_rst_00),
+    .up_tx_pll_locked (up_tx_pll_locked_00),
+    .up_tx_rst (up_tx_rst_00),
+    .up_tx_user_ready (up_tx_user_ready_00),
+    .up_tx_rst_done (up_tx_rst_done_00),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_00),
+    .up_tx_rate (up_tx_rate_00),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_00),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_00),
+    .up_tx_sel (up_tx_sel_00),
+    .up_tx_enb (up_tx_enb_00),
+    .up_tx_addr (up_tx_addr_00),
+    .up_tx_wr (up_tx_wr_00),
+    .up_tx_wdata (up_tx_wdata_00),
+    .up_tx_rdata (up_tx_rdata_00),
+    .up_tx_ready (up_tx_ready_00));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 2) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_01 (
+    .qpll2ch_clk (qpll2ch_clk_00),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
+    .qpll2ch_locked (qpll2ch_locked_00),
+    .cpll_ref_clk (cpll_ref_clk_01),
+    .rx_p (rx_01_p),
+    .rx_n (rx_01_n),
+    .rx_out_clk (rx_out_clk_01),
+    .rx_clk (rx_clk_01),
+    .rx_charisk (rx_charisk_01),
+    .rx_disperr (rx_disperr_01),
+    .rx_notintable (rx_notintable_01),
+    .rx_data (rx_data_01),
+    .rx_calign (rx_calign_01),
+    .tx_p (tx_01_p),
+    .tx_n (tx_01_n),
+    .tx_out_clk (tx_out_clk_01),
+    .tx_clk (tx_clk_01),
+    .tx_charisk (tx_charisk_01),
+    .tx_data (tx_data_01),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_01),
+    .up_es_enb (up_es_enb_01),
+    .up_es_addr (up_es_addr_01),
+    .up_es_wr (up_es_wr_01),
+    .up_es_wdata (up_es_wdata_01),
+    .up_es_rdata (up_es_rdata_01),
+    .up_es_ready (up_es_ready_01),
+    .up_rx_pll_rst (up_rx_pll_rst_01),
+    .up_rx_pll_locked (up_rx_pll_locked_01),
+    .up_rx_rst (up_rx_rst_01),
+    .up_rx_user_ready (up_rx_user_ready_01),
+    .up_rx_rst_done (up_rx_rst_done_01),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_01),
+    .up_rx_rate (up_rx_rate_01),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_01),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_01),
+    .up_rx_sel (up_rx_sel_01),
+    .up_rx_enb (up_rx_enb_01),
+    .up_rx_addr (up_rx_addr_01),
+    .up_rx_wr (up_rx_wr_01),
+    .up_rx_wdata (up_rx_wdata_01),
+    .up_rx_rdata (up_rx_rdata_01),
+    .up_rx_ready (up_rx_ready_01),
+    .up_tx_pll_rst (up_tx_pll_rst_01),
+    .up_tx_pll_locked (up_tx_pll_locked_01),
+    .up_tx_rst (up_tx_rst_01),
+    .up_tx_user_ready (up_tx_user_ready_01),
+    .up_tx_rst_done (up_tx_rst_done_01),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_01),
+    .up_tx_rate (up_tx_rate_01),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_01),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_01),
+    .up_tx_sel (up_tx_sel_01),
+    .up_tx_enb (up_tx_enb_01),
+    .up_tx_addr (up_tx_addr_01),
+    .up_tx_wr (up_tx_wr_01),
+    .up_tx_wdata (up_tx_wdata_01),
+    .up_tx_rdata (up_tx_rdata_01),
+    .up_tx_ready (up_tx_ready_01));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 3) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_02 (
+    .qpll2ch_clk (qpll2ch_clk_00),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
+    .qpll2ch_locked (qpll2ch_locked_00),
+    .cpll_ref_clk (cpll_ref_clk_02),
+    .rx_p (rx_02_p),
+    .rx_n (rx_02_n),
+    .rx_out_clk (rx_out_clk_02),
+    .rx_clk (rx_clk_02),
+    .rx_charisk (rx_charisk_02),
+    .rx_disperr (rx_disperr_02),
+    .rx_notintable (rx_notintable_02),
+    .rx_data (rx_data_02),
+    .rx_calign (rx_calign_02),
+    .tx_p (tx_02_p),
+    .tx_n (tx_02_n),
+    .tx_out_clk (tx_out_clk_02),
+    .tx_clk (tx_clk_02),
+    .tx_charisk (tx_charisk_02),
+    .tx_data (tx_data_02),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_02),
+    .up_es_enb (up_es_enb_02),
+    .up_es_addr (up_es_addr_02),
+    .up_es_wr (up_es_wr_02),
+    .up_es_wdata (up_es_wdata_02),
+    .up_es_rdata (up_es_rdata_02),
+    .up_es_ready (up_es_ready_02),
+    .up_rx_pll_rst (up_rx_pll_rst_02),
+    .up_rx_pll_locked (up_rx_pll_locked_02),
+    .up_rx_rst (up_rx_rst_02),
+    .up_rx_user_ready (up_rx_user_ready_02),
+    .up_rx_rst_done (up_rx_rst_done_02),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_02),
+    .up_rx_rate (up_rx_rate_02),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_02),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_02),
+    .up_rx_sel (up_rx_sel_02),
+    .up_rx_enb (up_rx_enb_02),
+    .up_rx_addr (up_rx_addr_02),
+    .up_rx_wr (up_rx_wr_02),
+    .up_rx_wdata (up_rx_wdata_02),
+    .up_rx_rdata (up_rx_rdata_02),
+    .up_rx_ready (up_rx_ready_02),
+    .up_tx_pll_rst (up_tx_pll_rst_02),
+    .up_tx_pll_locked (up_tx_pll_locked_02),
+    .up_tx_rst (up_tx_rst_02),
+    .up_tx_user_ready (up_tx_user_ready_02),
+    .up_tx_rst_done (up_tx_rst_done_02),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_02),
+    .up_tx_rate (up_tx_rate_02),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_02),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_02),
+    .up_tx_sel (up_tx_sel_02),
+    .up_tx_enb (up_tx_enb_02),
+    .up_tx_addr (up_tx_addr_02),
+    .up_tx_wr (up_tx_wr_02),
+    .up_tx_wdata (up_tx_wdata_02),
+    .up_tx_rdata (up_tx_rdata_02),
+    .up_tx_ready (up_tx_ready_02));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 4) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_03 (
+    .qpll2ch_clk (qpll2ch_clk_00),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
+    .qpll2ch_locked (qpll2ch_locked_00),
+    .cpll_ref_clk (cpll_ref_clk_03),
+    .rx_p (rx_03_p),
+    .rx_n (rx_03_n),
+    .rx_out_clk (rx_out_clk_03),
+    .rx_clk (rx_clk_03),
+    .rx_charisk (rx_charisk_03),
+    .rx_disperr (rx_disperr_03),
+    .rx_notintable (rx_notintable_03),
+    .rx_data (rx_data_03),
+    .rx_calign (rx_calign_03),
+    .tx_p (tx_03_p),
+    .tx_n (tx_03_n),
+    .tx_out_clk (tx_out_clk_03),
+    .tx_clk (tx_clk_03),
+    .tx_charisk (tx_charisk_03),
+    .tx_data (tx_data_03),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_03),
+    .up_es_enb (up_es_enb_03),
+    .up_es_addr (up_es_addr_03),
+    .up_es_wr (up_es_wr_03),
+    .up_es_wdata (up_es_wdata_03),
+    .up_es_rdata (up_es_rdata_03),
+    .up_es_ready (up_es_ready_03),
+    .up_rx_pll_rst (up_rx_pll_rst_03),
+    .up_rx_pll_locked (up_rx_pll_locked_03),
+    .up_rx_rst (up_rx_rst_03),
+    .up_rx_user_ready (up_rx_user_ready_03),
+    .up_rx_rst_done (up_rx_rst_done_03),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_03),
+    .up_rx_rate (up_rx_rate_03),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_03),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_03),
+    .up_rx_sel (up_rx_sel_03),
+    .up_rx_enb (up_rx_enb_03),
+    .up_rx_addr (up_rx_addr_03),
+    .up_rx_wr (up_rx_wr_03),
+    .up_rx_wdata (up_rx_wdata_03),
+    .up_rx_rdata (up_rx_rdata_03),
+    .up_rx_ready (up_rx_ready_03),
+    .up_tx_pll_rst (up_tx_pll_rst_03),
+    .up_tx_pll_locked (up_tx_pll_locked_03),
+    .up_tx_rst (up_tx_rst_03),
+    .up_tx_user_ready (up_tx_user_ready_03),
+    .up_tx_rst_done (up_tx_rst_done_03),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_03),
+    .up_tx_rate (up_tx_rate_03),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_03),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_03),
+    .up_tx_sel (up_tx_sel_03),
+    .up_tx_enb (up_tx_enb_03),
+    .up_tx_addr (up_tx_addr_03),
+    .up_tx_wr (up_tx_wr_03),
+    .up_tx_wdata (up_tx_wdata_03),
+    .up_tx_rdata (up_tx_rdata_03),
+    .up_tx_ready (up_tx_ready_03));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 5) begin
+  util_adxcvr_xcm #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
+    .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
+    .QPLL_CFG (QPLL_CFG),
+    .QPLL_FBDIV (QPLL_FBDIV))
+  i_xcm_04 (
+    .qpll_ref_clk (qpll_ref_clk_04),
+    .qpll2ch_clk (qpll2ch_clk_04),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
+    .qpll2ch_locked (qpll2ch_locked_04),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_qpll_rst (up_qpll_rst_04),
+    .up_cm_sel (up_cm_sel_04),
+    .up_cm_enb (up_cm_enb_04),
+    .up_cm_addr (up_cm_addr_04),
+    .up_cm_wr (up_cm_wr_04),
+    .up_cm_wdata (up_cm_wdata_04),
+    .up_cm_rdata (up_cm_rdata_04),
+    .up_cm_ready (up_cm_ready_04));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 5) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_04 (
+    .qpll2ch_clk (qpll2ch_clk_04),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
+    .qpll2ch_locked (qpll2ch_locked_04),
+    .cpll_ref_clk (cpll_ref_clk_04),
+    .rx_p (rx_04_p),
+    .rx_n (rx_04_n),
+    .rx_out_clk (rx_out_clk_04),
+    .rx_clk (rx_clk_04),
+    .rx_charisk (rx_charisk_04),
+    .rx_disperr (rx_disperr_04),
+    .rx_notintable (rx_notintable_04),
+    .rx_data (rx_data_04),
+    .rx_calign (rx_calign_04),
+    .tx_p (tx_04_p),
+    .tx_n (tx_04_n),
+    .tx_out_clk (tx_out_clk_04),
+    .tx_clk (tx_clk_04),
+    .tx_charisk (tx_charisk_04),
+    .tx_data (tx_data_04),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_04),
+    .up_es_enb (up_es_enb_04),
+    .up_es_addr (up_es_addr_04),
+    .up_es_wr (up_es_wr_04),
+    .up_es_wdata (up_es_wdata_04),
+    .up_es_rdata (up_es_rdata_04),
+    .up_es_ready (up_es_ready_04),
+    .up_rx_pll_rst (up_rx_pll_rst_04),
+    .up_rx_pll_locked (up_rx_pll_locked_04),
+    .up_rx_rst (up_rx_rst_04),
+    .up_rx_user_ready (up_rx_user_ready_04),
+    .up_rx_rst_done (up_rx_rst_done_04),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_04),
+    .up_rx_rate (up_rx_rate_04),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_04),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_04),
+    .up_rx_sel (up_rx_sel_04),
+    .up_rx_enb (up_rx_enb_04),
+    .up_rx_addr (up_rx_addr_04),
+    .up_rx_wr (up_rx_wr_04),
+    .up_rx_wdata (up_rx_wdata_04),
+    .up_rx_rdata (up_rx_rdata_04),
+    .up_rx_ready (up_rx_ready_04),
+    .up_tx_pll_rst (up_tx_pll_rst_04),
+    .up_tx_pll_locked (up_tx_pll_locked_04),
+    .up_tx_rst (up_tx_rst_04),
+    .up_tx_user_ready (up_tx_user_ready_04),
+    .up_tx_rst_done (up_tx_rst_done_04),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_04),
+    .up_tx_rate (up_tx_rate_04),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_04),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_04),
+    .up_tx_sel (up_tx_sel_04),
+    .up_tx_enb (up_tx_enb_04),
+    .up_tx_addr (up_tx_addr_04),
+    .up_tx_wr (up_tx_wr_04),
+    .up_tx_wdata (up_tx_wdata_04),
+    .up_tx_rdata (up_tx_rdata_04),
+    .up_tx_ready (up_tx_ready_04));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 6) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_05 (
+    .qpll2ch_clk (qpll2ch_clk_04),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
+    .qpll2ch_locked (qpll2ch_locked_04),
+    .cpll_ref_clk (cpll_ref_clk_05),
+    .rx_p (rx_05_p),
+    .rx_n (rx_05_n),
+    .rx_out_clk (rx_out_clk_05),
+    .rx_clk (rx_clk_05),
+    .rx_charisk (rx_charisk_05),
+    .rx_disperr (rx_disperr_05),
+    .rx_notintable (rx_notintable_05),
+    .rx_data (rx_data_05),
+    .rx_calign (rx_calign_05),
+    .tx_p (tx_05_p),
+    .tx_n (tx_05_n),
+    .tx_out_clk (tx_out_clk_05),
+    .tx_clk (tx_clk_05),
+    .tx_charisk (tx_charisk_05),
+    .tx_data (tx_data_05),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_05),
+    .up_es_enb (up_es_enb_05),
+    .up_es_addr (up_es_addr_05),
+    .up_es_wr (up_es_wr_05),
+    .up_es_wdata (up_es_wdata_05),
+    .up_es_rdata (up_es_rdata_05),
+    .up_es_ready (up_es_ready_05),
+    .up_rx_pll_rst (up_rx_pll_rst_05),
+    .up_rx_pll_locked (up_rx_pll_locked_05),
+    .up_rx_rst (up_rx_rst_05),
+    .up_rx_user_ready (up_rx_user_ready_05),
+    .up_rx_rst_done (up_rx_rst_done_05),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_05),
+    .up_rx_rate (up_rx_rate_05),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_05),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_05),
+    .up_rx_sel (up_rx_sel_05),
+    .up_rx_enb (up_rx_enb_05),
+    .up_rx_addr (up_rx_addr_05),
+    .up_rx_wr (up_rx_wr_05),
+    .up_rx_wdata (up_rx_wdata_05),
+    .up_rx_rdata (up_rx_rdata_05),
+    .up_rx_ready (up_rx_ready_05),
+    .up_tx_pll_rst (up_tx_pll_rst_05),
+    .up_tx_pll_locked (up_tx_pll_locked_05),
+    .up_tx_rst (up_tx_rst_05),
+    .up_tx_user_ready (up_tx_user_ready_05),
+    .up_tx_rst_done (up_tx_rst_done_05),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_05),
+    .up_tx_rate (up_tx_rate_05),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_05),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_05),
+    .up_tx_sel (up_tx_sel_05),
+    .up_tx_enb (up_tx_enb_05),
+    .up_tx_addr (up_tx_addr_05),
+    .up_tx_wr (up_tx_wr_05),
+    .up_tx_wdata (up_tx_wdata_05),
+    .up_tx_rdata (up_tx_rdata_05),
+    .up_tx_ready (up_tx_ready_05));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 7) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_06 (
+    .qpll2ch_clk (qpll2ch_clk_04),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
+    .qpll2ch_locked (qpll2ch_locked_04),
+    .cpll_ref_clk (cpll_ref_clk_06),
+    .rx_p (rx_06_p),
+    .rx_n (rx_06_n),
+    .rx_out_clk (rx_out_clk_06),
+    .rx_clk (rx_clk_06),
+    .rx_charisk (rx_charisk_06),
+    .rx_disperr (rx_disperr_06),
+    .rx_notintable (rx_notintable_06),
+    .rx_data (rx_data_06),
+    .rx_calign (rx_calign_06),
+    .tx_p (tx_06_p),
+    .tx_n (tx_06_n),
+    .tx_out_clk (tx_out_clk_06),
+    .tx_clk (tx_clk_06),
+    .tx_charisk (tx_charisk_06),
+    .tx_data (tx_data_06),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_06),
+    .up_es_enb (up_es_enb_06),
+    .up_es_addr (up_es_addr_06),
+    .up_es_wr (up_es_wr_06),
+    .up_es_wdata (up_es_wdata_06),
+    .up_es_rdata (up_es_rdata_06),
+    .up_es_ready (up_es_ready_06),
+    .up_rx_pll_rst (up_rx_pll_rst_06),
+    .up_rx_pll_locked (up_rx_pll_locked_06),
+    .up_rx_rst (up_rx_rst_06),
+    .up_rx_user_ready (up_rx_user_ready_06),
+    .up_rx_rst_done (up_rx_rst_done_06),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_06),
+    .up_rx_rate (up_rx_rate_06),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_06),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_06),
+    .up_rx_sel (up_rx_sel_06),
+    .up_rx_enb (up_rx_enb_06),
+    .up_rx_addr (up_rx_addr_06),
+    .up_rx_wr (up_rx_wr_06),
+    .up_rx_wdata (up_rx_wdata_06),
+    .up_rx_rdata (up_rx_rdata_06),
+    .up_rx_ready (up_rx_ready_06),
+    .up_tx_pll_rst (up_tx_pll_rst_06),
+    .up_tx_pll_locked (up_tx_pll_locked_06),
+    .up_tx_rst (up_tx_rst_06),
+    .up_tx_user_ready (up_tx_user_ready_06),
+    .up_tx_rst_done (up_tx_rst_done_06),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_06),
+    .up_tx_rate (up_tx_rate_06),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_06),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_06),
+    .up_tx_sel (up_tx_sel_06),
+    .up_tx_enb (up_tx_enb_06),
+    .up_tx_addr (up_tx_addr_06),
+    .up_tx_wr (up_tx_wr_06),
+    .up_tx_wdata (up_tx_wdata_06),
+    .up_tx_rdata (up_tx_rdata_06),
+    .up_tx_ready (up_tx_ready_06));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 8) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_07 (
+    .qpll2ch_clk (qpll2ch_clk_04),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
+    .qpll2ch_locked (qpll2ch_locked_04),
+    .cpll_ref_clk (cpll_ref_clk_07),
+    .rx_p (rx_07_p),
+    .rx_n (rx_07_n),
+    .rx_out_clk (rx_out_clk_07),
+    .rx_clk (rx_clk_07),
+    .rx_charisk (rx_charisk_07),
+    .rx_disperr (rx_disperr_07),
+    .rx_notintable (rx_notintable_07),
+    .rx_data (rx_data_07),
+    .rx_calign (rx_calign_07),
+    .tx_p (tx_07_p),
+    .tx_n (tx_07_n),
+    .tx_out_clk (tx_out_clk_07),
+    .tx_clk (tx_clk_07),
+    .tx_charisk (tx_charisk_07),
+    .tx_data (tx_data_07),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_07),
+    .up_es_enb (up_es_enb_07),
+    .up_es_addr (up_es_addr_07),
+    .up_es_wr (up_es_wr_07),
+    .up_es_wdata (up_es_wdata_07),
+    .up_es_rdata (up_es_rdata_07),
+    .up_es_ready (up_es_ready_07),
+    .up_rx_pll_rst (up_rx_pll_rst_07),
+    .up_rx_pll_locked (up_rx_pll_locked_07),
+    .up_rx_rst (up_rx_rst_07),
+    .up_rx_user_ready (up_rx_user_ready_07),
+    .up_rx_rst_done (up_rx_rst_done_07),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_07),
+    .up_rx_rate (up_rx_rate_07),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_07),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_07),
+    .up_rx_sel (up_rx_sel_07),
+    .up_rx_enb (up_rx_enb_07),
+    .up_rx_addr (up_rx_addr_07),
+    .up_rx_wr (up_rx_wr_07),
+    .up_rx_wdata (up_rx_wdata_07),
+    .up_rx_rdata (up_rx_rdata_07),
+    .up_rx_ready (up_rx_ready_07),
+    .up_tx_pll_rst (up_tx_pll_rst_07),
+    .up_tx_pll_locked (up_tx_pll_locked_07),
+    .up_tx_rst (up_tx_rst_07),
+    .up_tx_user_ready (up_tx_user_ready_07),
+    .up_tx_rst_done (up_tx_rst_done_07),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_07),
+    .up_tx_rate (up_tx_rate_07),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_07),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_07),
+    .up_tx_sel (up_tx_sel_07),
+    .up_tx_enb (up_tx_enb_07),
+    .up_tx_addr (up_tx_addr_07),
+    .up_tx_wr (up_tx_wr_07),
+    .up_tx_wdata (up_tx_wdata_07),
+    .up_tx_rdata (up_tx_rdata_07),
+    .up_tx_ready (up_tx_ready_07));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 9) begin
+  util_adxcvr_xcm #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
+    .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
+    .QPLL_CFG (QPLL_CFG),
+    .QPLL_FBDIV (QPLL_FBDIV))
+  i_xcm_08 (
+    .qpll_ref_clk (qpll_ref_clk_08),
+    .qpll2ch_clk (qpll2ch_clk_08),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
+    .qpll2ch_locked (qpll2ch_locked_08),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_qpll_rst (up_qpll_rst_08),
+    .up_cm_sel (up_cm_sel_08),
+    .up_cm_enb (up_cm_enb_08),
+    .up_cm_addr (up_cm_addr_08),
+    .up_cm_wr (up_cm_wr_08),
+    .up_cm_wdata (up_cm_wdata_08),
+    .up_cm_rdata (up_cm_rdata_08),
+    .up_cm_ready (up_cm_ready_08));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 9) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_08 (
+    .qpll2ch_clk (qpll2ch_clk_08),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
+    .qpll2ch_locked (qpll2ch_locked_08),
+    .cpll_ref_clk (cpll_ref_clk_08),
+    .rx_p (rx_08_p),
+    .rx_n (rx_08_n),
+    .rx_out_clk (rx_out_clk_08),
+    .rx_clk (rx_clk_08),
+    .rx_charisk (rx_charisk_08),
+    .rx_disperr (rx_disperr_08),
+    .rx_notintable (rx_notintable_08),
+    .rx_data (rx_data_08),
+    .rx_calign (rx_calign_08),
+    .tx_p (tx_08_p),
+    .tx_n (tx_08_n),
+    .tx_out_clk (tx_out_clk_08),
+    .tx_clk (tx_clk_08),
+    .tx_charisk (tx_charisk_08),
+    .tx_data (tx_data_08),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_08),
+    .up_es_enb (up_es_enb_08),
+    .up_es_addr (up_es_addr_08),
+    .up_es_wr (up_es_wr_08),
+    .up_es_wdata (up_es_wdata_08),
+    .up_es_rdata (up_es_rdata_08),
+    .up_es_ready (up_es_ready_08),
+    .up_rx_pll_rst (up_rx_pll_rst_08),
+    .up_rx_pll_locked (up_rx_pll_locked_08),
+    .up_rx_rst (up_rx_rst_08),
+    .up_rx_user_ready (up_rx_user_ready_08),
+    .up_rx_rst_done (up_rx_rst_done_08),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_08),
+    .up_rx_rate (up_rx_rate_08),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_08),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_08),
+    .up_rx_sel (up_rx_sel_08),
+    .up_rx_enb (up_rx_enb_08),
+    .up_rx_addr (up_rx_addr_08),
+    .up_rx_wr (up_rx_wr_08),
+    .up_rx_wdata (up_rx_wdata_08),
+    .up_rx_rdata (up_rx_rdata_08),
+    .up_rx_ready (up_rx_ready_08),
+    .up_tx_pll_rst (up_tx_pll_rst_08),
+    .up_tx_pll_locked (up_tx_pll_locked_08),
+    .up_tx_rst (up_tx_rst_08),
+    .up_tx_user_ready (up_tx_user_ready_08),
+    .up_tx_rst_done (up_tx_rst_done_08),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_08),
+    .up_tx_rate (up_tx_rate_08),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_08),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_08),
+    .up_tx_sel (up_tx_sel_08),
+    .up_tx_enb (up_tx_enb_08),
+    .up_tx_addr (up_tx_addr_08),
+    .up_tx_wr (up_tx_wr_08),
+    .up_tx_wdata (up_tx_wdata_08),
+    .up_tx_rdata (up_tx_rdata_08),
+    .up_tx_ready (up_tx_ready_08));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 10) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_09 (
+    .qpll2ch_clk (qpll2ch_clk_08),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
+    .qpll2ch_locked (qpll2ch_locked_08),
+    .cpll_ref_clk (cpll_ref_clk_09),
+    .rx_p (rx_09_p),
+    .rx_n (rx_09_n),
+    .rx_out_clk (rx_out_clk_09),
+    .rx_clk (rx_clk_09),
+    .rx_charisk (rx_charisk_09),
+    .rx_disperr (rx_disperr_09),
+    .rx_notintable (rx_notintable_09),
+    .rx_data (rx_data_09),
+    .rx_calign (rx_calign_09),
+    .tx_p (tx_09_p),
+    .tx_n (tx_09_n),
+    .tx_out_clk (tx_out_clk_09),
+    .tx_clk (tx_clk_09),
+    .tx_charisk (tx_charisk_09),
+    .tx_data (tx_data_09),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_09),
+    .up_es_enb (up_es_enb_09),
+    .up_es_addr (up_es_addr_09),
+    .up_es_wr (up_es_wr_09),
+    .up_es_wdata (up_es_wdata_09),
+    .up_es_rdata (up_es_rdata_09),
+    .up_es_ready (up_es_ready_09),
+    .up_rx_pll_rst (up_rx_pll_rst_09),
+    .up_rx_pll_locked (up_rx_pll_locked_09),
+    .up_rx_rst (up_rx_rst_09),
+    .up_rx_user_ready (up_rx_user_ready_09),
+    .up_rx_rst_done (up_rx_rst_done_09),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_09),
+    .up_rx_rate (up_rx_rate_09),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_09),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_09),
+    .up_rx_sel (up_rx_sel_09),
+    .up_rx_enb (up_rx_enb_09),
+    .up_rx_addr (up_rx_addr_09),
+    .up_rx_wr (up_rx_wr_09),
+    .up_rx_wdata (up_rx_wdata_09),
+    .up_rx_rdata (up_rx_rdata_09),
+    .up_rx_ready (up_rx_ready_09),
+    .up_tx_pll_rst (up_tx_pll_rst_09),
+    .up_tx_pll_locked (up_tx_pll_locked_09),
+    .up_tx_rst (up_tx_rst_09),
+    .up_tx_user_ready (up_tx_user_ready_09),
+    .up_tx_rst_done (up_tx_rst_done_09),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_09),
+    .up_tx_rate (up_tx_rate_09),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_09),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_09),
+    .up_tx_sel (up_tx_sel_09),
+    .up_tx_enb (up_tx_enb_09),
+    .up_tx_addr (up_tx_addr_09),
+    .up_tx_wr (up_tx_wr_09),
+    .up_tx_wdata (up_tx_wdata_09),
+    .up_tx_rdata (up_tx_rdata_09),
+    .up_tx_ready (up_tx_ready_09));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 11) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_10 (
+    .qpll2ch_clk (qpll2ch_clk_08),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
+    .qpll2ch_locked (qpll2ch_locked_08),
+    .cpll_ref_clk (cpll_ref_clk_10),
+    .rx_p (rx_10_p),
+    .rx_n (rx_10_n),
+    .rx_out_clk (rx_out_clk_10),
+    .rx_clk (rx_clk_10),
+    .rx_charisk (rx_charisk_10),
+    .rx_disperr (rx_disperr_10),
+    .rx_notintable (rx_notintable_10),
+    .rx_data (rx_data_10),
+    .rx_calign (rx_calign_10),
+    .tx_p (tx_10_p),
+    .tx_n (tx_10_n),
+    .tx_out_clk (tx_out_clk_10),
+    .tx_clk (tx_clk_10),
+    .tx_charisk (tx_charisk_10),
+    .tx_data (tx_data_10),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_10),
+    .up_es_enb (up_es_enb_10),
+    .up_es_addr (up_es_addr_10),
+    .up_es_wr (up_es_wr_10),
+    .up_es_wdata (up_es_wdata_10),
+    .up_es_rdata (up_es_rdata_10),
+    .up_es_ready (up_es_ready_10),
+    .up_rx_pll_rst (up_rx_pll_rst_10),
+    .up_rx_pll_locked (up_rx_pll_locked_10),
+    .up_rx_rst (up_rx_rst_10),
+    .up_rx_user_ready (up_rx_user_ready_10),
+    .up_rx_rst_done (up_rx_rst_done_10),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_10),
+    .up_rx_rate (up_rx_rate_10),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_10),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_10),
+    .up_rx_sel (up_rx_sel_10),
+    .up_rx_enb (up_rx_enb_10),
+    .up_rx_addr (up_rx_addr_10),
+    .up_rx_wr (up_rx_wr_10),
+    .up_rx_wdata (up_rx_wdata_10),
+    .up_rx_rdata (up_rx_rdata_10),
+    .up_rx_ready (up_rx_ready_10),
+    .up_tx_pll_rst (up_tx_pll_rst_10),
+    .up_tx_pll_locked (up_tx_pll_locked_10),
+    .up_tx_rst (up_tx_rst_10),
+    .up_tx_user_ready (up_tx_user_ready_10),
+    .up_tx_rst_done (up_tx_rst_done_10),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_10),
+    .up_tx_rate (up_tx_rate_10),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_10),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_10),
+    .up_tx_sel (up_tx_sel_10),
+    .up_tx_enb (up_tx_enb_10),
+    .up_tx_addr (up_tx_addr_10),
+    .up_tx_wr (up_tx_wr_10),
+    .up_tx_wdata (up_tx_wdata_10),
+    .up_tx_rdata (up_tx_rdata_10),
+    .up_tx_ready (up_tx_ready_10));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 12) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_11 (
+    .qpll2ch_clk (qpll2ch_clk_08),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
+    .qpll2ch_locked (qpll2ch_locked_08),
+    .cpll_ref_clk (cpll_ref_clk_11),
+    .rx_p (rx_11_p),
+    .rx_n (rx_11_n),
+    .rx_out_clk (rx_out_clk_11),
+    .rx_clk (rx_clk_11),
+    .rx_charisk (rx_charisk_11),
+    .rx_disperr (rx_disperr_11),
+    .rx_notintable (rx_notintable_11),
+    .rx_data (rx_data_11),
+    .rx_calign (rx_calign_11),
+    .tx_p (tx_11_p),
+    .tx_n (tx_11_n),
+    .tx_out_clk (tx_out_clk_11),
+    .tx_clk (tx_clk_11),
+    .tx_charisk (tx_charisk_11),
+    .tx_data (tx_data_11),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_11),
+    .up_es_enb (up_es_enb_11),
+    .up_es_addr (up_es_addr_11),
+    .up_es_wr (up_es_wr_11),
+    .up_es_wdata (up_es_wdata_11),
+    .up_es_rdata (up_es_rdata_11),
+    .up_es_ready (up_es_ready_11),
+    .up_rx_pll_rst (up_rx_pll_rst_11),
+    .up_rx_pll_locked (up_rx_pll_locked_11),
+    .up_rx_rst (up_rx_rst_11),
+    .up_rx_user_ready (up_rx_user_ready_11),
+    .up_rx_rst_done (up_rx_rst_done_11),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_11),
+    .up_rx_rate (up_rx_rate_11),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_11),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_11),
+    .up_rx_sel (up_rx_sel_11),
+    .up_rx_enb (up_rx_enb_11),
+    .up_rx_addr (up_rx_addr_11),
+    .up_rx_wr (up_rx_wr_11),
+    .up_rx_wdata (up_rx_wdata_11),
+    .up_rx_rdata (up_rx_rdata_11),
+    .up_rx_ready (up_rx_ready_11),
+    .up_tx_pll_rst (up_tx_pll_rst_11),
+    .up_tx_pll_locked (up_tx_pll_locked_11),
+    .up_tx_rst (up_tx_rst_11),
+    .up_tx_user_ready (up_tx_user_ready_11),
+    .up_tx_rst_done (up_tx_rst_done_11),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_11),
+    .up_tx_rate (up_tx_rate_11),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_11),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_11),
+    .up_tx_sel (up_tx_sel_11),
+    .up_tx_enb (up_tx_enb_11),
+    .up_tx_addr (up_tx_addr_11),
+    .up_tx_wr (up_tx_wr_11),
+    .up_tx_wdata (up_tx_wdata_11),
+    .up_tx_rdata (up_tx_rdata_11),
+    .up_tx_ready (up_tx_ready_11));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 13) begin
+  util_adxcvr_xcm #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
+    .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
+    .QPLL_CFG (QPLL_CFG),
+    .QPLL_FBDIV (QPLL_FBDIV))
+  i_xcm_12 (
+    .qpll_ref_clk (qpll_ref_clk_12),
+    .qpll2ch_clk (qpll2ch_clk_12),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
+    .qpll2ch_locked (qpll2ch_locked_12),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_qpll_rst (up_qpll_rst_12),
+    .up_cm_sel (up_cm_sel_12),
+    .up_cm_enb (up_cm_enb_12),
+    .up_cm_addr (up_cm_addr_12),
+    .up_cm_wr (up_cm_wr_12),
+    .up_cm_wdata (up_cm_wdata_12),
+    .up_cm_rdata (up_cm_rdata_12),
+    .up_cm_ready (up_cm_ready_12));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 13) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_12 (
+    .qpll2ch_clk (qpll2ch_clk_12),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
+    .qpll2ch_locked (qpll2ch_locked_12),
+    .cpll_ref_clk (cpll_ref_clk_12),
+    .rx_p (rx_12_p),
+    .rx_n (rx_12_n),
+    .rx_out_clk (rx_out_clk_12),
+    .rx_clk (rx_clk_12),
+    .rx_charisk (rx_charisk_12),
+    .rx_disperr (rx_disperr_12),
+    .rx_notintable (rx_notintable_12),
+    .rx_data (rx_data_12),
+    .rx_calign (rx_calign_12),
+    .tx_p (tx_12_p),
+    .tx_n (tx_12_n),
+    .tx_out_clk (tx_out_clk_12),
+    .tx_clk (tx_clk_12),
+    .tx_charisk (tx_charisk_12),
+    .tx_data (tx_data_12),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_12),
+    .up_es_enb (up_es_enb_12),
+    .up_es_addr (up_es_addr_12),
+    .up_es_wr (up_es_wr_12),
+    .up_es_wdata (up_es_wdata_12),
+    .up_es_rdata (up_es_rdata_12),
+    .up_es_ready (up_es_ready_12),
+    .up_rx_pll_rst (up_rx_pll_rst_12),
+    .up_rx_pll_locked (up_rx_pll_locked_12),
+    .up_rx_rst (up_rx_rst_12),
+    .up_rx_user_ready (up_rx_user_ready_12),
+    .up_rx_rst_done (up_rx_rst_done_12),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_12),
+    .up_rx_rate (up_rx_rate_12),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_12),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_12),
+    .up_rx_sel (up_rx_sel_12),
+    .up_rx_enb (up_rx_enb_12),
+    .up_rx_addr (up_rx_addr_12),
+    .up_rx_wr (up_rx_wr_12),
+    .up_rx_wdata (up_rx_wdata_12),
+    .up_rx_rdata (up_rx_rdata_12),
+    .up_rx_ready (up_rx_ready_12),
+    .up_tx_pll_rst (up_tx_pll_rst_12),
+    .up_tx_pll_locked (up_tx_pll_locked_12),
+    .up_tx_rst (up_tx_rst_12),
+    .up_tx_user_ready (up_tx_user_ready_12),
+    .up_tx_rst_done (up_tx_rst_done_12),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_12),
+    .up_tx_rate (up_tx_rate_12),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_12),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_12),
+    .up_tx_sel (up_tx_sel_12),
+    .up_tx_enb (up_tx_enb_12),
+    .up_tx_addr (up_tx_addr_12),
+    .up_tx_wr (up_tx_wr_12),
+    .up_tx_wdata (up_tx_wdata_12),
+    .up_tx_rdata (up_tx_rdata_12),
+    .up_tx_ready (up_tx_ready_12));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 14) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_13 (
+    .qpll2ch_clk (qpll2ch_clk_12),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
+    .qpll2ch_locked (qpll2ch_locked_12),
+    .cpll_ref_clk (cpll_ref_clk_13),
+    .rx_p (rx_13_p),
+    .rx_n (rx_13_n),
+    .rx_out_clk (rx_out_clk_13),
+    .rx_clk (rx_clk_13),
+    .rx_charisk (rx_charisk_13),
+    .rx_disperr (rx_disperr_13),
+    .rx_notintable (rx_notintable_13),
+    .rx_data (rx_data_13),
+    .rx_calign (rx_calign_13),
+    .tx_p (tx_13_p),
+    .tx_n (tx_13_n),
+    .tx_out_clk (tx_out_clk_13),
+    .tx_clk (tx_clk_13),
+    .tx_charisk (tx_charisk_13),
+    .tx_data (tx_data_13),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_13),
+    .up_es_enb (up_es_enb_13),
+    .up_es_addr (up_es_addr_13),
+    .up_es_wr (up_es_wr_13),
+    .up_es_wdata (up_es_wdata_13),
+    .up_es_rdata (up_es_rdata_13),
+    .up_es_ready (up_es_ready_13),
+    .up_rx_pll_rst (up_rx_pll_rst_13),
+    .up_rx_pll_locked (up_rx_pll_locked_13),
+    .up_rx_rst (up_rx_rst_13),
+    .up_rx_user_ready (up_rx_user_ready_13),
+    .up_rx_rst_done (up_rx_rst_done_13),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_13),
+    .up_rx_rate (up_rx_rate_13),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_13),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_13),
+    .up_rx_sel (up_rx_sel_13),
+    .up_rx_enb (up_rx_enb_13),
+    .up_rx_addr (up_rx_addr_13),
+    .up_rx_wr (up_rx_wr_13),
+    .up_rx_wdata (up_rx_wdata_13),
+    .up_rx_rdata (up_rx_rdata_13),
+    .up_rx_ready (up_rx_ready_13),
+    .up_tx_pll_rst (up_tx_pll_rst_13),
+    .up_tx_pll_locked (up_tx_pll_locked_13),
+    .up_tx_rst (up_tx_rst_13),
+    .up_tx_user_ready (up_tx_user_ready_13),
+    .up_tx_rst_done (up_tx_rst_done_13),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_13),
+    .up_tx_rate (up_tx_rate_13),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_13),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_13),
+    .up_tx_sel (up_tx_sel_13),
+    .up_tx_enb (up_tx_enb_13),
+    .up_tx_addr (up_tx_addr_13),
+    .up_tx_wr (up_tx_wr_13),
+    .up_tx_wdata (up_tx_wdata_13),
+    .up_tx_rdata (up_tx_rdata_13),
+    .up_tx_ready (up_tx_ready_13));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 15) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_14 (
+    .qpll2ch_clk (qpll2ch_clk_12),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
+    .qpll2ch_locked (qpll2ch_locked_12),
+    .cpll_ref_clk (cpll_ref_clk_14),
+    .rx_p (rx_14_p),
+    .rx_n (rx_14_n),
+    .rx_out_clk (rx_out_clk_14),
+    .rx_clk (rx_clk_14),
+    .rx_charisk (rx_charisk_14),
+    .rx_disperr (rx_disperr_14),
+    .rx_notintable (rx_notintable_14),
+    .rx_data (rx_data_14),
+    .rx_calign (rx_calign_14),
+    .tx_p (tx_14_p),
+    .tx_n (tx_14_n),
+    .tx_out_clk (tx_out_clk_14),
+    .tx_clk (tx_clk_14),
+    .tx_charisk (tx_charisk_14),
+    .tx_data (tx_data_14),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_14),
+    .up_es_enb (up_es_enb_14),
+    .up_es_addr (up_es_addr_14),
+    .up_es_wr (up_es_wr_14),
+    .up_es_wdata (up_es_wdata_14),
+    .up_es_rdata (up_es_rdata_14),
+    .up_es_ready (up_es_ready_14),
+    .up_rx_pll_rst (up_rx_pll_rst_14),
+    .up_rx_pll_locked (up_rx_pll_locked_14),
+    .up_rx_rst (up_rx_rst_14),
+    .up_rx_user_ready (up_rx_user_ready_14),
+    .up_rx_rst_done (up_rx_rst_done_14),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_14),
+    .up_rx_rate (up_rx_rate_14),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_14),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_14),
+    .up_rx_sel (up_rx_sel_14),
+    .up_rx_enb (up_rx_enb_14),
+    .up_rx_addr (up_rx_addr_14),
+    .up_rx_wr (up_rx_wr_14),
+    .up_rx_wdata (up_rx_wdata_14),
+    .up_rx_rdata (up_rx_rdata_14),
+    .up_rx_ready (up_rx_ready_14),
+    .up_tx_pll_rst (up_tx_pll_rst_14),
+    .up_tx_pll_locked (up_tx_pll_locked_14),
+    .up_tx_rst (up_tx_rst_14),
+    .up_tx_user_ready (up_tx_user_ready_14),
+    .up_tx_rst_done (up_tx_rst_done_14),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_14),
+    .up_tx_rate (up_tx_rate_14),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_14),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_14),
+    .up_tx_sel (up_tx_sel_14),
+    .up_tx_enb (up_tx_enb_14),
+    .up_tx_addr (up_tx_addr_14),
+    .up_tx_wr (up_tx_wr_14),
+    .up_tx_wdata (up_tx_wdata_14),
+    .up_tx_rdata (up_tx_rdata_14),
+    .up_tx_ready (up_tx_ready_14));
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES >= 16) begin
+  util_adxcvr_xch #(
+    .XCVR_ID (n),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
+    .TX_OUT_DIV (TX_OUT_DIV),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
+    .PMA_RSV (PMA_RSV),
+    .RX_CDR_CFG (RX_CDR_CFG))
+  i_xch_15 (
+    .qpll2ch_clk (qpll2ch_clk_12),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
+    .qpll2ch_locked (qpll2ch_locked_12),
+    .cpll_ref_clk (cpll_ref_clk_15),
+    .rx_p (rx_15_p),
+    .rx_n (rx_15_n),
+    .rx_out_clk (rx_out_clk_15),
+    .rx_clk (rx_clk_15),
+    .rx_charisk (rx_charisk_15),
+    .rx_disperr (rx_disperr_15),
+    .rx_notintable (rx_notintable_15),
+    .rx_data (rx_data_15),
+    .rx_calign (rx_calign_15),
+    .tx_p (tx_15_p),
+    .tx_n (tx_15_n),
+    .tx_out_clk (tx_out_clk_15),
+    .tx_clk (tx_clk_15),
+    .tx_charisk (tx_charisk_15),
+    .tx_data (tx_data_15),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (up_es_sel_15),
+    .up_es_enb (up_es_enb_15),
+    .up_es_addr (up_es_addr_15),
+    .up_es_wr (up_es_wr_15),
+    .up_es_wdata (up_es_wdata_15),
+    .up_es_rdata (up_es_rdata_15),
+    .up_es_ready (up_es_ready_15),
+    .up_rx_pll_rst (up_rx_pll_rst_15),
+    .up_rx_pll_locked (up_rx_pll_locked_15),
+    .up_rx_rst (up_rx_rst_15),
+    .up_rx_user_ready (up_rx_user_ready_15),
+    .up_rx_rst_done (up_rx_rst_done_15),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_15),
+    .up_rx_rate (up_rx_rate_15),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_15),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_15),
+    .up_rx_sel (up_rx_sel_15),
+    .up_rx_enb (up_rx_enb_15),
+    .up_rx_addr (up_rx_addr_15),
+    .up_rx_wr (up_rx_wr_15),
+    .up_rx_wdata (up_rx_wdata_15),
+    .up_rx_rdata (up_rx_rdata_15),
+    .up_rx_ready (up_rx_ready_15),
+    .up_tx_pll_rst (up_tx_pll_rst_15),
+    .up_tx_pll_locked (up_tx_pll_locked_15),
+    .up_tx_rst (up_tx_rst_15),
+    .up_tx_user_ready (up_tx_user_ready_15),
+    .up_tx_rst_done (up_tx_rst_done_15),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_15),
+    .up_tx_rate (up_tx_rate_15),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_15),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_15),
+    .up_tx_sel (up_tx_sel_15),
+    .up_tx_enb (up_tx_enb_15),
+    .up_tx_addr (up_tx_addr_15),
+    .up_tx_wr (up_tx_wr_15),
+    .up_tx_wdata (up_tx_wdata_15),
+    .up_tx_rdata (up_tx_rdata_15),
+    .up_tx_ready (up_tx_ready_15));
+  end
+  endgenerate
+
+endmodule     
+
+// ***************************************************************************
+// ***************************************************************************
+

From 87cf13b0efc9af982c2e2f33ea1ff0243ab47914 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 16 Jun 2016 16:41:43 -0400
Subject: [PATCH 289/972] util_adxcvr- system verilog interfaces

---
 library/util_adxcvr/util_adxcvr_ip.tcl | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 library/util_adxcvr/util_adxcvr_ip.tcl

diff --git a/library/util_adxcvr/util_adxcvr_ip.tcl b/library/util_adxcvr/util_adxcvr_ip.tcl
new file mode 100644
index 000000000..03b1b119f
--- /dev/null
+++ b/library/util_adxcvr/util_adxcvr_ip.tcl
@@ -0,0 +1,16 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create util_adxcvr
+adi_ip_files util_adxcvr [list \
+  "util_adxcvr_intf.svh" \
+  "util_adxcvr_xcm.sv" \
+  "util_adxcvr_xch.sv" \
+  "util_adxcvr.sv" ]
+
+adi_ip_properties_lite util_adxcvr
+
+ipx::save_core [ipx::current_core]
+

From 36fbf4fc42c5c2c30a6f87d28ba8d9a630f9b320 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 17 Jun 2016 11:59:42 -0400
Subject: [PATCH 290/972] util_adxcvr: shared xcvr cores

---
 library/util_adxcvr/util_adxcvr.v      | 2839 +++++++++++++-----------
 library/util_adxcvr/util_adxcvr_ip.tcl |  609 ++++-
 library/util_adxcvr/util_adxcvr_xch.v  |  366 +--
 library/util_adxcvr/util_adxcvr_xcm.v  |  132 +-
 4 files changed, 2506 insertions(+), 1440 deletions(-)

diff --git a/library/util_adxcvr/util_adxcvr.v b/library/util_adxcvr/util_adxcvr.v
index c7aa11320..5be095b9b 100644
--- a/library/util_adxcvr/util_adxcvr.v
+++ b/library/util_adxcvr/util_adxcvr.v
@@ -34,6 +34,7 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
+// AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY!
 
 `timescale 1ns/1ps
 
@@ -42,619 +43,619 @@ module util_adxcvr (
   input           up_rstn,
   input           up_clk,
 
-  input           qpll_ref_clk_00,
-  input           cpll_ref_clk_00,
+  input           qpll_ref_clk_0,
+  input           cpll_ref_clk_0,
 
-  input           rx_00_p,
-  input           rx_00_n,
-  output          rx_out_clk_00,
-  input           rx_clk_00,
-  output  [ 3:0]  rx_charisk_00,
-  output  [ 3:0]  rx_disperr_00,
-  output  [ 3:0]  rx_notintable_00,
-  output  [31:0]  rx_data_00,
-  input           rx_calign_00,
+  input           rx_0_p,
+  input           rx_0_n,
+  output          rx_out_clk_0,
+  input           rx_clk_0,
+  output  [ 3:0]  rx_charisk_0,
+  output  [ 3:0]  rx_disperr_0,
+  output  [ 3:0]  rx_notintable_0,
+  output  [31:0]  rx_data_0,
+  input           rx_calign_0,
 
-  output          tx_00_p,
-  output          tx_00_n,
-  output          tx_out_clk_00,
-  input           tx_clk_00,
-  input   [ 3:0]  tx_charisk_00,
-  input   [31:0]  tx_data_00,
+  output          tx_0_p,
+  output          tx_0_n,
+  output          tx_out_clk_0,
+  input           tx_clk_0,
+  input   [ 3:0]  tx_charisk_0,
+  input   [31:0]  tx_data_0,
 
-  input   [ 7:0]  up_cm_sel_00,
-  input           up_cm_enb_00,
-  input   [11:0]  up_cm_addr_00,
-  input           up_cm_wr_00,
-  input   [15:0]  up_cm_wdata_00,
-  output  [15:0]  up_cm_rdata_00,
-  output          up_cm_ready_00,
-  input   [ 7:0]  up_es_sel_00,
-  input           up_es_enb_00,
-  input   [11:0]  up_es_addr_00,
-  input           up_es_wr_00,
-  input   [15:0]  up_es_wdata_00,
-  output  [15:0]  up_es_rdata_00,
-  output          up_es_ready_00,
-  input           up_rx_pll_rst_00,
-  output          up_rx_pll_locked_00,
-  input           up_rx_rst_00,
-  input           up_rx_user_ready_00,
-  output          up_rx_rst_done_00,
-  input           up_rx_lpm_dfe_n_00,
-  input   [ 2:0]  up_rx_rate_00,
-  input   [ 1:0]  up_rx_sys_clk_sel_00,
-  input   [ 2:0]  up_rx_out_clk_sel_00,
-  input   [ 7:0]  up_rx_sel_00,
-  input           up_rx_enb_00,
-  input   [11:0]  up_rx_addr_00,
-  input           up_rx_wr_00,
-  input   [15:0]  up_rx_wdata_00,
-  output  [15:0]  up_rx_rdata_00,
-  output          up_rx_ready_00,
-  input           up_tx_pll_rst_00,
-  output          up_tx_pll_locked_00,
-  input           up_tx_rst_00,
-  input           up_tx_user_ready_00,
-  output          up_tx_rst_done_00,
-  input           up_tx_lpm_dfe_n_00,
-  input   [ 2:0]  up_tx_rate_00,
-  input   [ 1:0]  up_tx_sys_clk_sel_00,
-  input   [ 2:0]  up_tx_out_clk_sel_00,
-  input   [ 7:0]  up_tx_sel_00,
-  input           up_tx_enb_00,
-  input   [11:0]  up_tx_addr_00,
-  input           up_tx_wr_00,
-  input   [15:0]  up_tx_wdata_00,
-  output  [15:0]  up_tx_rdata_00,
-  output          up_tx_ready_00,
+  input   [ 7:0]  up_cm_sel_0,
+  input           up_cm_enb_0,
+  input   [11:0]  up_cm_addr_0,
+  input           up_cm_wr_0,
+  input   [15:0]  up_cm_wdata_0,
+  output  [15:0]  up_cm_rdata_0,
+  output          up_cm_ready_0,
+  input   [ 7:0]  up_es_sel_0,
+  input           up_es_enb_0,
+  input   [11:0]  up_es_addr_0,
+  input           up_es_wr_0,
+  input   [15:0]  up_es_wdata_0,
+  output  [15:0]  up_es_rdata_0,
+  output          up_es_ready_0,
+  input           up_rx_pll_rst_0,
+  output          up_rx_pll_locked_0,
+  input           up_rx_rst_0,
+  input           up_rx_user_ready_0,
+  output          up_rx_rst_done_0,
+  input           up_rx_lpm_dfe_n_0,
+  input   [ 2:0]  up_rx_rate_0,
+  input   [ 1:0]  up_rx_sys_clk_sel_0,
+  input   [ 2:0]  up_rx_out_clk_sel_0,
+  input   [ 7:0]  up_rx_sel_0,
+  input           up_rx_enb_0,
+  input   [11:0]  up_rx_addr_0,
+  input           up_rx_wr_0,
+  input   [15:0]  up_rx_wdata_0,
+  output  [15:0]  up_rx_rdata_0,
+  output          up_rx_ready_0,
+  input           up_tx_pll_rst_0,
+  output          up_tx_pll_locked_0,
+  input           up_tx_rst_0,
+  input           up_tx_user_ready_0,
+  output          up_tx_rst_done_0,
+  input           up_tx_lpm_dfe_n_0,
+  input   [ 2:0]  up_tx_rate_0,
+  input   [ 1:0]  up_tx_sys_clk_sel_0,
+  input   [ 2:0]  up_tx_out_clk_sel_0,
+  input   [ 7:0]  up_tx_sel_0,
+  input           up_tx_enb_0,
+  input   [11:0]  up_tx_addr_0,
+  input           up_tx_wr_0,
+  input   [15:0]  up_tx_wdata_0,
+  output  [15:0]  up_tx_rdata_0,
+  output          up_tx_ready_0,
 
-  input           cpll_ref_clk_01,
+  input           cpll_ref_clk_1,
 
-  input           rx_01_p,
-  input           rx_01_n,
-  output          rx_out_clk_01,
-  input           rx_clk_01,
-  output  [ 3:0]  rx_charisk_01,
-  output  [ 3:0]  rx_disperr_01,
-  output  [ 3:0]  rx_notintable_01,
-  output  [31:0]  rx_data_01,
-  input           rx_calign_01,
+  input           rx_1_p,
+  input           rx_1_n,
+  output          rx_out_clk_1,
+  input           rx_clk_1,
+  output  [ 3:0]  rx_charisk_1,
+  output  [ 3:0]  rx_disperr_1,
+  output  [ 3:0]  rx_notintable_1,
+  output  [31:0]  rx_data_1,
+  input           rx_calign_1,
 
-  output          tx_01_p,
-  output          tx_01_n,
-  output          tx_out_clk_01,
-  input           tx_clk_01,
-  input   [ 3:0]  tx_charisk_01,
-  input   [31:0]  tx_data_01,
+  output          tx_1_p,
+  output          tx_1_n,
+  output          tx_out_clk_1,
+  input           tx_clk_1,
+  input   [ 3:0]  tx_charisk_1,
+  input   [31:0]  tx_data_1,
 
-  input   [ 7:0]  up_es_sel_01,
-  input           up_es_enb_01,
-  input   [11:0]  up_es_addr_01,
-  input           up_es_wr_01,
-  input   [15:0]  up_es_wdata_01,
-  output  [15:0]  up_es_rdata_01,
-  output          up_es_ready_01,
-  input           up_rx_pll_rst_01,
-  output          up_rx_pll_locked_01,
-  input           up_rx_rst_01,
-  input           up_rx_user_ready_01,
-  output          up_rx_rst_done_01,
-  input           up_rx_lpm_dfe_n_01,
-  input   [ 2:0]  up_rx_rate_01,
-  input   [ 1:0]  up_rx_sys_clk_sel_01,
-  input   [ 2:0]  up_rx_out_clk_sel_01,
-  input   [ 7:0]  up_rx_sel_01,
-  input           up_rx_enb_01,
-  input   [11:0]  up_rx_addr_01,
-  input           up_rx_wr_01,
-  input   [15:0]  up_rx_wdata_01,
-  output  [15:0]  up_rx_rdata_01,
-  output          up_rx_ready_01,
-  input           up_tx_pll_rst_01,
-  output          up_tx_pll_locked_01,
-  input           up_tx_rst_01,
-  input           up_tx_user_ready_01,
-  output          up_tx_rst_done_01,
-  input           up_tx_lpm_dfe_n_01,
-  input   [ 2:0]  up_tx_rate_01,
-  input   [ 1:0]  up_tx_sys_clk_sel_01,
-  input   [ 2:0]  up_tx_out_clk_sel_01,
-  input   [ 7:0]  up_tx_sel_01,
-  input           up_tx_enb_01,
-  input   [11:0]  up_tx_addr_01,
-  input           up_tx_wr_01,
-  input   [15:0]  up_tx_wdata_01,
-  output  [15:0]  up_tx_rdata_01,
-  output          up_tx_ready_01,
+  input   [ 7:0]  up_es_sel_1,
+  input           up_es_enb_1,
+  input   [11:0]  up_es_addr_1,
+  input           up_es_wr_1,
+  input   [15:0]  up_es_wdata_1,
+  output  [15:0]  up_es_rdata_1,
+  output          up_es_ready_1,
+  input           up_rx_pll_rst_1,
+  output          up_rx_pll_locked_1,
+  input           up_rx_rst_1,
+  input           up_rx_user_ready_1,
+  output          up_rx_rst_done_1,
+  input           up_rx_lpm_dfe_n_1,
+  input   [ 2:0]  up_rx_rate_1,
+  input   [ 1:0]  up_rx_sys_clk_sel_1,
+  input   [ 2:0]  up_rx_out_clk_sel_1,
+  input   [ 7:0]  up_rx_sel_1,
+  input           up_rx_enb_1,
+  input   [11:0]  up_rx_addr_1,
+  input           up_rx_wr_1,
+  input   [15:0]  up_rx_wdata_1,
+  output  [15:0]  up_rx_rdata_1,
+  output          up_rx_ready_1,
+  input           up_tx_pll_rst_1,
+  output          up_tx_pll_locked_1,
+  input           up_tx_rst_1,
+  input           up_tx_user_ready_1,
+  output          up_tx_rst_done_1,
+  input           up_tx_lpm_dfe_n_1,
+  input   [ 2:0]  up_tx_rate_1,
+  input   [ 1:0]  up_tx_sys_clk_sel_1,
+  input   [ 2:0]  up_tx_out_clk_sel_1,
+  input   [ 7:0]  up_tx_sel_1,
+  input           up_tx_enb_1,
+  input   [11:0]  up_tx_addr_1,
+  input           up_tx_wr_1,
+  input   [15:0]  up_tx_wdata_1,
+  output  [15:0]  up_tx_rdata_1,
+  output          up_tx_ready_1,
 
-  input           cpll_ref_clk_02,
+  input           cpll_ref_clk_2,
 
-  input           rx_02_p,
-  input           rx_02_n,
-  output          rx_out_clk_02,
-  input           rx_clk_02,
-  output  [ 3:0]  rx_charisk_02,
-  output  [ 3:0]  rx_disperr_02,
-  output  [ 3:0]  rx_notintable_02,
-  output  [31:0]  rx_data_02,
-  input           rx_calign_02,
+  input           rx_2_p,
+  input           rx_2_n,
+  output          rx_out_clk_2,
+  input           rx_clk_2,
+  output  [ 3:0]  rx_charisk_2,
+  output  [ 3:0]  rx_disperr_2,
+  output  [ 3:0]  rx_notintable_2,
+  output  [31:0]  rx_data_2,
+  input           rx_calign_2,
 
-  output          tx_02_p,
-  output          tx_02_n,
-  output          tx_out_clk_02,
-  input           tx_clk_02,
-  input   [ 3:0]  tx_charisk_02,
-  input   [31:0]  tx_data_02,
+  output          tx_2_p,
+  output          tx_2_n,
+  output          tx_out_clk_2,
+  input           tx_clk_2,
+  input   [ 3:0]  tx_charisk_2,
+  input   [31:0]  tx_data_2,
 
-  input   [ 7:0]  up_es_sel_02,
-  input           up_es_enb_02,
-  input   [11:0]  up_es_addr_02,
-  input           up_es_wr_02,
-  input   [15:0]  up_es_wdata_02,
-  output  [15:0]  up_es_rdata_02,
-  output          up_es_ready_02,
-  input           up_rx_pll_rst_02,
-  output          up_rx_pll_locked_02,
-  input           up_rx_rst_02,
-  input           up_rx_user_ready_02,
-  output          up_rx_rst_done_02,
-  input           up_rx_lpm_dfe_n_02,
-  input   [ 2:0]  up_rx_rate_02,
-  input   [ 1:0]  up_rx_sys_clk_sel_02,
-  input   [ 2:0]  up_rx_out_clk_sel_02,
-  input   [ 7:0]  up_rx_sel_02,
-  input           up_rx_enb_02,
-  input   [11:0]  up_rx_addr_02,
-  input           up_rx_wr_02,
-  input   [15:0]  up_rx_wdata_02,
-  output  [15:0]  up_rx_rdata_02,
-  output          up_rx_ready_02,
-  input           up_tx_pll_rst_02,
-  output          up_tx_pll_locked_02,
-  input           up_tx_rst_02,
-  input           up_tx_user_ready_02,
-  output          up_tx_rst_done_02,
-  input           up_tx_lpm_dfe_n_02,
-  input   [ 2:0]  up_tx_rate_02,
-  input   [ 1:0]  up_tx_sys_clk_sel_02,
-  input   [ 2:0]  up_tx_out_clk_sel_02,
-  input   [ 7:0]  up_tx_sel_02,
-  input           up_tx_enb_02,
-  input   [11:0]  up_tx_addr_02,
-  input           up_tx_wr_02,
-  input   [15:0]  up_tx_wdata_02,
-  output  [15:0]  up_tx_rdata_02,
-  output          up_tx_ready_02,
+  input   [ 7:0]  up_es_sel_2,
+  input           up_es_enb_2,
+  input   [11:0]  up_es_addr_2,
+  input           up_es_wr_2,
+  input   [15:0]  up_es_wdata_2,
+  output  [15:0]  up_es_rdata_2,
+  output          up_es_ready_2,
+  input           up_rx_pll_rst_2,
+  output          up_rx_pll_locked_2,
+  input           up_rx_rst_2,
+  input           up_rx_user_ready_2,
+  output          up_rx_rst_done_2,
+  input           up_rx_lpm_dfe_n_2,
+  input   [ 2:0]  up_rx_rate_2,
+  input   [ 1:0]  up_rx_sys_clk_sel_2,
+  input   [ 2:0]  up_rx_out_clk_sel_2,
+  input   [ 7:0]  up_rx_sel_2,
+  input           up_rx_enb_2,
+  input   [11:0]  up_rx_addr_2,
+  input           up_rx_wr_2,
+  input   [15:0]  up_rx_wdata_2,
+  output  [15:0]  up_rx_rdata_2,
+  output          up_rx_ready_2,
+  input           up_tx_pll_rst_2,
+  output          up_tx_pll_locked_2,
+  input           up_tx_rst_2,
+  input           up_tx_user_ready_2,
+  output          up_tx_rst_done_2,
+  input           up_tx_lpm_dfe_n_2,
+  input   [ 2:0]  up_tx_rate_2,
+  input   [ 1:0]  up_tx_sys_clk_sel_2,
+  input   [ 2:0]  up_tx_out_clk_sel_2,
+  input   [ 7:0]  up_tx_sel_2,
+  input           up_tx_enb_2,
+  input   [11:0]  up_tx_addr_2,
+  input           up_tx_wr_2,
+  input   [15:0]  up_tx_wdata_2,
+  output  [15:0]  up_tx_rdata_2,
+  output          up_tx_ready_2,
 
-  input           cpll_ref_clk_03,
+  input           cpll_ref_clk_3,
 
-  input           rx_03_p,
-  input           rx_03_n,
-  output          rx_out_clk_03,
-  input           rx_clk_03,
-  output  [ 3:0]  rx_charisk_03,
-  output  [ 3:0]  rx_disperr_03,
-  output  [ 3:0]  rx_notintable_03,
-  output  [31:0]  rx_data_03,
-  input           rx_calign_03,
+  input           rx_3_p,
+  input           rx_3_n,
+  output          rx_out_clk_3,
+  input           rx_clk_3,
+  output  [ 3:0]  rx_charisk_3,
+  output  [ 3:0]  rx_disperr_3,
+  output  [ 3:0]  rx_notintable_3,
+  output  [31:0]  rx_data_3,
+  input           rx_calign_3,
 
-  output          tx_03_p,
-  output          tx_03_n,
-  output          tx_out_clk_03,
-  input           tx_clk_03,
-  input   [ 3:0]  tx_charisk_03,
-  input   [31:0]  tx_data_03,
+  output          tx_3_p,
+  output          tx_3_n,
+  output          tx_out_clk_3,
+  input           tx_clk_3,
+  input   [ 3:0]  tx_charisk_3,
+  input   [31:0]  tx_data_3,
 
-  input   [ 7:0]  up_es_sel_03,
-  input           up_es_enb_03,
-  input   [11:0]  up_es_addr_03,
-  input           up_es_wr_03,
-  input   [15:0]  up_es_wdata_03,
-  output  [15:0]  up_es_rdata_03,
-  output          up_es_ready_03,
-  input           up_rx_pll_rst_03,
-  output          up_rx_pll_locked_03,
-  input           up_rx_rst_03,
-  input           up_rx_user_ready_03,
-  output          up_rx_rst_done_03,
-  input           up_rx_lpm_dfe_n_03,
-  input   [ 2:0]  up_rx_rate_03,
-  input   [ 1:0]  up_rx_sys_clk_sel_03,
-  input   [ 2:0]  up_rx_out_clk_sel_03,
-  input   [ 7:0]  up_rx_sel_03,
-  input           up_rx_enb_03,
-  input   [11:0]  up_rx_addr_03,
-  input           up_rx_wr_03,
-  input   [15:0]  up_rx_wdata_03,
-  output  [15:0]  up_rx_rdata_03,
-  output          up_rx_ready_03,
-  input           up_tx_pll_rst_03,
-  output          up_tx_pll_locked_03,
-  input           up_tx_rst_03,
-  input           up_tx_user_ready_03,
-  output          up_tx_rst_done_03,
-  input           up_tx_lpm_dfe_n_03,
-  input   [ 2:0]  up_tx_rate_03,
-  input   [ 1:0]  up_tx_sys_clk_sel_03,
-  input   [ 2:0]  up_tx_out_clk_sel_03,
-  input   [ 7:0]  up_tx_sel_03,
-  input           up_tx_enb_03,
-  input   [11:0]  up_tx_addr_03,
-  input           up_tx_wr_03,
-  input   [15:0]  up_tx_wdata_03,
-  output  [15:0]  up_tx_rdata_03,
-  output          up_tx_ready_03,
+  input   [ 7:0]  up_es_sel_3,
+  input           up_es_enb_3,
+  input   [11:0]  up_es_addr_3,
+  input           up_es_wr_3,
+  input   [15:0]  up_es_wdata_3,
+  output  [15:0]  up_es_rdata_3,
+  output          up_es_ready_3,
+  input           up_rx_pll_rst_3,
+  output          up_rx_pll_locked_3,
+  input           up_rx_rst_3,
+  input           up_rx_user_ready_3,
+  output          up_rx_rst_done_3,
+  input           up_rx_lpm_dfe_n_3,
+  input   [ 2:0]  up_rx_rate_3,
+  input   [ 1:0]  up_rx_sys_clk_sel_3,
+  input   [ 2:0]  up_rx_out_clk_sel_3,
+  input   [ 7:0]  up_rx_sel_3,
+  input           up_rx_enb_3,
+  input   [11:0]  up_rx_addr_3,
+  input           up_rx_wr_3,
+  input   [15:0]  up_rx_wdata_3,
+  output  [15:0]  up_rx_rdata_3,
+  output          up_rx_ready_3,
+  input           up_tx_pll_rst_3,
+  output          up_tx_pll_locked_3,
+  input           up_tx_rst_3,
+  input           up_tx_user_ready_3,
+  output          up_tx_rst_done_3,
+  input           up_tx_lpm_dfe_n_3,
+  input   [ 2:0]  up_tx_rate_3,
+  input   [ 1:0]  up_tx_sys_clk_sel_3,
+  input   [ 2:0]  up_tx_out_clk_sel_3,
+  input   [ 7:0]  up_tx_sel_3,
+  input           up_tx_enb_3,
+  input   [11:0]  up_tx_addr_3,
+  input           up_tx_wr_3,
+  input   [15:0]  up_tx_wdata_3,
+  output  [15:0]  up_tx_rdata_3,
+  output          up_tx_ready_3,
 
-  input           qpll_ref_clk_04,
-  input           cpll_ref_clk_04,
+  input           qpll_ref_clk_4,
+  input           cpll_ref_clk_4,
 
-  input           rx_04_p,
-  input           rx_04_n,
-  output          rx_out_clk_04,
-  input           rx_clk_04,
-  output  [ 3:0]  rx_charisk_04,
-  output  [ 3:0]  rx_disperr_04,
-  output  [ 3:0]  rx_notintable_04,
-  output  [31:0]  rx_data_04,
-  input           rx_calign_04,
+  input           rx_4_p,
+  input           rx_4_n,
+  output          rx_out_clk_4,
+  input           rx_clk_4,
+  output  [ 3:0]  rx_charisk_4,
+  output  [ 3:0]  rx_disperr_4,
+  output  [ 3:0]  rx_notintable_4,
+  output  [31:0]  rx_data_4,
+  input           rx_calign_4,
 
-  output          tx_04_p,
-  output          tx_04_n,
-  output          tx_out_clk_04,
-  input           tx_clk_04,
-  input   [ 3:0]  tx_charisk_04,
-  input   [31:0]  tx_data_04,
+  output          tx_4_p,
+  output          tx_4_n,
+  output          tx_out_clk_4,
+  input           tx_clk_4,
+  input   [ 3:0]  tx_charisk_4,
+  input   [31:0]  tx_data_4,
 
-  input   [ 7:0]  up_cm_sel_04,
-  input           up_cm_enb_04,
-  input   [11:0]  up_cm_addr_04,
-  input           up_cm_wr_04,
-  input   [15:0]  up_cm_wdata_04,
-  output  [15:0]  up_cm_rdata_04,
-  output          up_cm_ready_04,
-  input   [ 7:0]  up_es_sel_04,
-  input           up_es_enb_04,
-  input   [11:0]  up_es_addr_04,
-  input           up_es_wr_04,
-  input   [15:0]  up_es_wdata_04,
-  output  [15:0]  up_es_rdata_04,
-  output          up_es_ready_04,
-  input           up_rx_pll_rst_04,
-  output          up_rx_pll_locked_04,
-  input           up_rx_rst_04,
-  input           up_rx_user_ready_04,
-  output          up_rx_rst_done_04,
-  input           up_rx_lpm_dfe_n_04,
-  input   [ 2:0]  up_rx_rate_04,
-  input   [ 1:0]  up_rx_sys_clk_sel_04,
-  input   [ 2:0]  up_rx_out_clk_sel_04,
-  input   [ 7:0]  up_rx_sel_04,
-  input           up_rx_enb_04,
-  input   [11:0]  up_rx_addr_04,
-  input           up_rx_wr_04,
-  input   [15:0]  up_rx_wdata_04,
-  output  [15:0]  up_rx_rdata_04,
-  output          up_rx_ready_04,
-  input           up_tx_pll_rst_04,
-  output          up_tx_pll_locked_04,
-  input           up_tx_rst_04,
-  input           up_tx_user_ready_04,
-  output          up_tx_rst_done_04,
-  input           up_tx_lpm_dfe_n_04,
-  input   [ 2:0]  up_tx_rate_04,
-  input   [ 1:0]  up_tx_sys_clk_sel_04,
-  input   [ 2:0]  up_tx_out_clk_sel_04,
-  input   [ 7:0]  up_tx_sel_04,
-  input           up_tx_enb_04,
-  input   [11:0]  up_tx_addr_04,
-  input           up_tx_wr_04,
-  input   [15:0]  up_tx_wdata_04,
-  output  [15:0]  up_tx_rdata_04,
-  output          up_tx_ready_04,
+  input   [ 7:0]  up_cm_sel_4,
+  input           up_cm_enb_4,
+  input   [11:0]  up_cm_addr_4,
+  input           up_cm_wr_4,
+  input   [15:0]  up_cm_wdata_4,
+  output  [15:0]  up_cm_rdata_4,
+  output          up_cm_ready_4,
+  input   [ 7:0]  up_es_sel_4,
+  input           up_es_enb_4,
+  input   [11:0]  up_es_addr_4,
+  input           up_es_wr_4,
+  input   [15:0]  up_es_wdata_4,
+  output  [15:0]  up_es_rdata_4,
+  output          up_es_ready_4,
+  input           up_rx_pll_rst_4,
+  output          up_rx_pll_locked_4,
+  input           up_rx_rst_4,
+  input           up_rx_user_ready_4,
+  output          up_rx_rst_done_4,
+  input           up_rx_lpm_dfe_n_4,
+  input   [ 2:0]  up_rx_rate_4,
+  input   [ 1:0]  up_rx_sys_clk_sel_4,
+  input   [ 2:0]  up_rx_out_clk_sel_4,
+  input   [ 7:0]  up_rx_sel_4,
+  input           up_rx_enb_4,
+  input   [11:0]  up_rx_addr_4,
+  input           up_rx_wr_4,
+  input   [15:0]  up_rx_wdata_4,
+  output  [15:0]  up_rx_rdata_4,
+  output          up_rx_ready_4,
+  input           up_tx_pll_rst_4,
+  output          up_tx_pll_locked_4,
+  input           up_tx_rst_4,
+  input           up_tx_user_ready_4,
+  output          up_tx_rst_done_4,
+  input           up_tx_lpm_dfe_n_4,
+  input   [ 2:0]  up_tx_rate_4,
+  input   [ 1:0]  up_tx_sys_clk_sel_4,
+  input   [ 2:0]  up_tx_out_clk_sel_4,
+  input   [ 7:0]  up_tx_sel_4,
+  input           up_tx_enb_4,
+  input   [11:0]  up_tx_addr_4,
+  input           up_tx_wr_4,
+  input   [15:0]  up_tx_wdata_4,
+  output  [15:0]  up_tx_rdata_4,
+  output          up_tx_ready_4,
 
-  input           cpll_ref_clk_05,
+  input           cpll_ref_clk_5,
 
-  input           rx_05_p,
-  input           rx_05_n,
-  output          rx_out_clk_05,
-  input           rx_clk_05,
-  output  [ 3:0]  rx_charisk_05,
-  output  [ 3:0]  rx_disperr_05,
-  output  [ 3:0]  rx_notintable_05,
-  output  [31:0]  rx_data_05,
-  input           rx_calign_05,
+  input           rx_5_p,
+  input           rx_5_n,
+  output          rx_out_clk_5,
+  input           rx_clk_5,
+  output  [ 3:0]  rx_charisk_5,
+  output  [ 3:0]  rx_disperr_5,
+  output  [ 3:0]  rx_notintable_5,
+  output  [31:0]  rx_data_5,
+  input           rx_calign_5,
 
-  output          tx_05_p,
-  output          tx_05_n,
-  output          tx_out_clk_05,
-  input           tx_clk_05,
-  input   [ 3:0]  tx_charisk_05,
-  input   [31:0]  tx_data_05,
+  output          tx_5_p,
+  output          tx_5_n,
+  output          tx_out_clk_5,
+  input           tx_clk_5,
+  input   [ 3:0]  tx_charisk_5,
+  input   [31:0]  tx_data_5,
 
-  input   [ 7:0]  up_es_sel_05,
-  input           up_es_enb_05,
-  input   [11:0]  up_es_addr_05,
-  input           up_es_wr_05,
-  input   [15:0]  up_es_wdata_05,
-  output  [15:0]  up_es_rdata_05,
-  output          up_es_ready_05,
-  input           up_rx_pll_rst_05,
-  output          up_rx_pll_locked_05,
-  input           up_rx_rst_05,
-  input           up_rx_user_ready_05,
-  output          up_rx_rst_done_05,
-  input           up_rx_lpm_dfe_n_05,
-  input   [ 2:0]  up_rx_rate_05,
-  input   [ 1:0]  up_rx_sys_clk_sel_05,
-  input   [ 2:0]  up_rx_out_clk_sel_05,
-  input   [ 7:0]  up_rx_sel_05,
-  input           up_rx_enb_05,
-  input   [11:0]  up_rx_addr_05,
-  input           up_rx_wr_05,
-  input   [15:0]  up_rx_wdata_05,
-  output  [15:0]  up_rx_rdata_05,
-  output          up_rx_ready_05,
-  input           up_tx_pll_rst_05,
-  output          up_tx_pll_locked_05,
-  input           up_tx_rst_05,
-  input           up_tx_user_ready_05,
-  output          up_tx_rst_done_05,
-  input           up_tx_lpm_dfe_n_05,
-  input   [ 2:0]  up_tx_rate_05,
-  input   [ 1:0]  up_tx_sys_clk_sel_05,
-  input   [ 2:0]  up_tx_out_clk_sel_05,
-  input   [ 7:0]  up_tx_sel_05,
-  input           up_tx_enb_05,
-  input   [11:0]  up_tx_addr_05,
-  input           up_tx_wr_05,
-  input   [15:0]  up_tx_wdata_05,
-  output  [15:0]  up_tx_rdata_05,
-  output          up_tx_ready_05,
+  input   [ 7:0]  up_es_sel_5,
+  input           up_es_enb_5,
+  input   [11:0]  up_es_addr_5,
+  input           up_es_wr_5,
+  input   [15:0]  up_es_wdata_5,
+  output  [15:0]  up_es_rdata_5,
+  output          up_es_ready_5,
+  input           up_rx_pll_rst_5,
+  output          up_rx_pll_locked_5,
+  input           up_rx_rst_5,
+  input           up_rx_user_ready_5,
+  output          up_rx_rst_done_5,
+  input           up_rx_lpm_dfe_n_5,
+  input   [ 2:0]  up_rx_rate_5,
+  input   [ 1:0]  up_rx_sys_clk_sel_5,
+  input   [ 2:0]  up_rx_out_clk_sel_5,
+  input   [ 7:0]  up_rx_sel_5,
+  input           up_rx_enb_5,
+  input   [11:0]  up_rx_addr_5,
+  input           up_rx_wr_5,
+  input   [15:0]  up_rx_wdata_5,
+  output  [15:0]  up_rx_rdata_5,
+  output          up_rx_ready_5,
+  input           up_tx_pll_rst_5,
+  output          up_tx_pll_locked_5,
+  input           up_tx_rst_5,
+  input           up_tx_user_ready_5,
+  output          up_tx_rst_done_5,
+  input           up_tx_lpm_dfe_n_5,
+  input   [ 2:0]  up_tx_rate_5,
+  input   [ 1:0]  up_tx_sys_clk_sel_5,
+  input   [ 2:0]  up_tx_out_clk_sel_5,
+  input   [ 7:0]  up_tx_sel_5,
+  input           up_tx_enb_5,
+  input   [11:0]  up_tx_addr_5,
+  input           up_tx_wr_5,
+  input   [15:0]  up_tx_wdata_5,
+  output  [15:0]  up_tx_rdata_5,
+  output          up_tx_ready_5,
 
-  input           cpll_ref_clk_06,
+  input           cpll_ref_clk_6,
 
-  input           rx_06_p,
-  input           rx_06_n,
-  output          rx_out_clk_06,
-  input           rx_clk_06,
-  output  [ 3:0]  rx_charisk_06,
-  output  [ 3:0]  rx_disperr_06,
-  output  [ 3:0]  rx_notintable_06,
-  output  [31:0]  rx_data_06,
-  input           rx_calign_06,
+  input           rx_6_p,
+  input           rx_6_n,
+  output          rx_out_clk_6,
+  input           rx_clk_6,
+  output  [ 3:0]  rx_charisk_6,
+  output  [ 3:0]  rx_disperr_6,
+  output  [ 3:0]  rx_notintable_6,
+  output  [31:0]  rx_data_6,
+  input           rx_calign_6,
 
-  output          tx_06_p,
-  output          tx_06_n,
-  output          tx_out_clk_06,
-  input           tx_clk_06,
-  input   [ 3:0]  tx_charisk_06,
-  input   [31:0]  tx_data_06,
+  output          tx_6_p,
+  output          tx_6_n,
+  output          tx_out_clk_6,
+  input           tx_clk_6,
+  input   [ 3:0]  tx_charisk_6,
+  input   [31:0]  tx_data_6,
 
-  input   [ 7:0]  up_es_sel_06,
-  input           up_es_enb_06,
-  input   [11:0]  up_es_addr_06,
-  input           up_es_wr_06,
-  input   [15:0]  up_es_wdata_06,
-  output  [15:0]  up_es_rdata_06,
-  output          up_es_ready_06,
-  input           up_rx_pll_rst_06,
-  output          up_rx_pll_locked_06,
-  input           up_rx_rst_06,
-  input           up_rx_user_ready_06,
-  output          up_rx_rst_done_06,
-  input           up_rx_lpm_dfe_n_06,
-  input   [ 2:0]  up_rx_rate_06,
-  input   [ 1:0]  up_rx_sys_clk_sel_06,
-  input   [ 2:0]  up_rx_out_clk_sel_06,
-  input   [ 7:0]  up_rx_sel_06,
-  input           up_rx_enb_06,
-  input   [11:0]  up_rx_addr_06,
-  input           up_rx_wr_06,
-  input   [15:0]  up_rx_wdata_06,
-  output  [15:0]  up_rx_rdata_06,
-  output          up_rx_ready_06,
-  input           up_tx_pll_rst_06,
-  output          up_tx_pll_locked_06,
-  input           up_tx_rst_06,
-  input           up_tx_user_ready_06,
-  output          up_tx_rst_done_06,
-  input           up_tx_lpm_dfe_n_06,
-  input   [ 2:0]  up_tx_rate_06,
-  input   [ 1:0]  up_tx_sys_clk_sel_06,
-  input   [ 2:0]  up_tx_out_clk_sel_06,
-  input   [ 7:0]  up_tx_sel_06,
-  input           up_tx_enb_06,
-  input   [11:0]  up_tx_addr_06,
-  input           up_tx_wr_06,
-  input   [15:0]  up_tx_wdata_06,
-  output  [15:0]  up_tx_rdata_06,
-  output          up_tx_ready_06,
+  input   [ 7:0]  up_es_sel_6,
+  input           up_es_enb_6,
+  input   [11:0]  up_es_addr_6,
+  input           up_es_wr_6,
+  input   [15:0]  up_es_wdata_6,
+  output  [15:0]  up_es_rdata_6,
+  output          up_es_ready_6,
+  input           up_rx_pll_rst_6,
+  output          up_rx_pll_locked_6,
+  input           up_rx_rst_6,
+  input           up_rx_user_ready_6,
+  output          up_rx_rst_done_6,
+  input           up_rx_lpm_dfe_n_6,
+  input   [ 2:0]  up_rx_rate_6,
+  input   [ 1:0]  up_rx_sys_clk_sel_6,
+  input   [ 2:0]  up_rx_out_clk_sel_6,
+  input   [ 7:0]  up_rx_sel_6,
+  input           up_rx_enb_6,
+  input   [11:0]  up_rx_addr_6,
+  input           up_rx_wr_6,
+  input   [15:0]  up_rx_wdata_6,
+  output  [15:0]  up_rx_rdata_6,
+  output          up_rx_ready_6,
+  input           up_tx_pll_rst_6,
+  output          up_tx_pll_locked_6,
+  input           up_tx_rst_6,
+  input           up_tx_user_ready_6,
+  output          up_tx_rst_done_6,
+  input           up_tx_lpm_dfe_n_6,
+  input   [ 2:0]  up_tx_rate_6,
+  input   [ 1:0]  up_tx_sys_clk_sel_6,
+  input   [ 2:0]  up_tx_out_clk_sel_6,
+  input   [ 7:0]  up_tx_sel_6,
+  input           up_tx_enb_6,
+  input   [11:0]  up_tx_addr_6,
+  input           up_tx_wr_6,
+  input   [15:0]  up_tx_wdata_6,
+  output  [15:0]  up_tx_rdata_6,
+  output          up_tx_ready_6,
 
-  input           cpll_ref_clk_07,
+  input           cpll_ref_clk_7,
 
-  input           rx_07_p,
-  input           rx_07_n,
-  output          rx_out_clk_07,
-  input           rx_clk_07,
-  output  [ 3:0]  rx_charisk_07,
-  output  [ 3:0]  rx_disperr_07,
-  output  [ 3:0]  rx_notintable_07,
-  output  [31:0]  rx_data_07,
-  input           rx_calign_07,
+  input           rx_7_p,
+  input           rx_7_n,
+  output          rx_out_clk_7,
+  input           rx_clk_7,
+  output  [ 3:0]  rx_charisk_7,
+  output  [ 3:0]  rx_disperr_7,
+  output  [ 3:0]  rx_notintable_7,
+  output  [31:0]  rx_data_7,
+  input           rx_calign_7,
 
-  output          tx_07_p,
-  output          tx_07_n,
-  output          tx_out_clk_07,
-  input           tx_clk_07,
-  input   [ 3:0]  tx_charisk_07,
-  input   [31:0]  tx_data_07,
+  output          tx_7_p,
+  output          tx_7_n,
+  output          tx_out_clk_7,
+  input           tx_clk_7,
+  input   [ 3:0]  tx_charisk_7,
+  input   [31:0]  tx_data_7,
 
-  input   [ 7:0]  up_es_sel_07,
-  input           up_es_enb_07,
-  input   [11:0]  up_es_addr_07,
-  input           up_es_wr_07,
-  input   [15:0]  up_es_wdata_07,
-  output  [15:0]  up_es_rdata_07,
-  output          up_es_ready_07,
-  input           up_rx_pll_rst_07,
-  output          up_rx_pll_locked_07,
-  input           up_rx_rst_07,
-  input           up_rx_user_ready_07,
-  output          up_rx_rst_done_07,
-  input           up_rx_lpm_dfe_n_07,
-  input   [ 2:0]  up_rx_rate_07,
-  input   [ 1:0]  up_rx_sys_clk_sel_07,
-  input   [ 2:0]  up_rx_out_clk_sel_07,
-  input   [ 7:0]  up_rx_sel_07,
-  input           up_rx_enb_07,
-  input   [11:0]  up_rx_addr_07,
-  input           up_rx_wr_07,
-  input   [15:0]  up_rx_wdata_07,
-  output  [15:0]  up_rx_rdata_07,
-  output          up_rx_ready_07,
-  input           up_tx_pll_rst_07,
-  output          up_tx_pll_locked_07,
-  input           up_tx_rst_07,
-  input           up_tx_user_ready_07,
-  output          up_tx_rst_done_07,
-  input           up_tx_lpm_dfe_n_07,
-  input   [ 2:0]  up_tx_rate_07,
-  input   [ 1:0]  up_tx_sys_clk_sel_07,
-  input   [ 2:0]  up_tx_out_clk_sel_07,
-  input   [ 7:0]  up_tx_sel_07,
-  input           up_tx_enb_07,
-  input   [11:0]  up_tx_addr_07,
-  input           up_tx_wr_07,
-  input   [15:0]  up_tx_wdata_07,
-  output  [15:0]  up_tx_rdata_07,
-  output          up_tx_ready_07,
+  input   [ 7:0]  up_es_sel_7,
+  input           up_es_enb_7,
+  input   [11:0]  up_es_addr_7,
+  input           up_es_wr_7,
+  input   [15:0]  up_es_wdata_7,
+  output  [15:0]  up_es_rdata_7,
+  output          up_es_ready_7,
+  input           up_rx_pll_rst_7,
+  output          up_rx_pll_locked_7,
+  input           up_rx_rst_7,
+  input           up_rx_user_ready_7,
+  output          up_rx_rst_done_7,
+  input           up_rx_lpm_dfe_n_7,
+  input   [ 2:0]  up_rx_rate_7,
+  input   [ 1:0]  up_rx_sys_clk_sel_7,
+  input   [ 2:0]  up_rx_out_clk_sel_7,
+  input   [ 7:0]  up_rx_sel_7,
+  input           up_rx_enb_7,
+  input   [11:0]  up_rx_addr_7,
+  input           up_rx_wr_7,
+  input   [15:0]  up_rx_wdata_7,
+  output  [15:0]  up_rx_rdata_7,
+  output          up_rx_ready_7,
+  input           up_tx_pll_rst_7,
+  output          up_tx_pll_locked_7,
+  input           up_tx_rst_7,
+  input           up_tx_user_ready_7,
+  output          up_tx_rst_done_7,
+  input           up_tx_lpm_dfe_n_7,
+  input   [ 2:0]  up_tx_rate_7,
+  input   [ 1:0]  up_tx_sys_clk_sel_7,
+  input   [ 2:0]  up_tx_out_clk_sel_7,
+  input   [ 7:0]  up_tx_sel_7,
+  input           up_tx_enb_7,
+  input   [11:0]  up_tx_addr_7,
+  input           up_tx_wr_7,
+  input   [15:0]  up_tx_wdata_7,
+  output  [15:0]  up_tx_rdata_7,
+  output          up_tx_ready_7,
 
-  input           qpll_ref_clk_08,
-  input           cpll_ref_clk_08,
+  input           qpll_ref_clk_8,
+  input           cpll_ref_clk_8,
 
-  input           rx_08_p,
-  input           rx_08_n,
-  output          rx_out_clk_08,
-  input           rx_clk_08,
-  output  [ 3:0]  rx_charisk_08,
-  output  [ 3:0]  rx_disperr_08,
-  output  [ 3:0]  rx_notintable_08,
-  output  [31:0]  rx_data_08,
-  input           rx_calign_08,
+  input           rx_8_p,
+  input           rx_8_n,
+  output          rx_out_clk_8,
+  input           rx_clk_8,
+  output  [ 3:0]  rx_charisk_8,
+  output  [ 3:0]  rx_disperr_8,
+  output  [ 3:0]  rx_notintable_8,
+  output  [31:0]  rx_data_8,
+  input           rx_calign_8,
 
-  output          tx_08_p,
-  output          tx_08_n,
-  output          tx_out_clk_08,
-  input           tx_clk_08,
-  input   [ 3:0]  tx_charisk_08,
-  input   [31:0]  tx_data_08,
+  output          tx_8_p,
+  output          tx_8_n,
+  output          tx_out_clk_8,
+  input           tx_clk_8,
+  input   [ 3:0]  tx_charisk_8,
+  input   [31:0]  tx_data_8,
 
-  input   [ 7:0]  up_cm_sel_08,
-  input           up_cm_enb_08,
-  input   [11:0]  up_cm_addr_08,
-  input           up_cm_wr_08,
-  input   [15:0]  up_cm_wdata_08,
-  output  [15:0]  up_cm_rdata_08,
-  output          up_cm_ready_08,
-  input   [ 7:0]  up_es_sel_08,
-  input           up_es_enb_08,
-  input   [11:0]  up_es_addr_08,
-  input           up_es_wr_08,
-  input   [15:0]  up_es_wdata_08,
-  output  [15:0]  up_es_rdata_08,
-  output          up_es_ready_08,
-  input           up_rx_pll_rst_08,
-  output          up_rx_pll_locked_08,
-  input           up_rx_rst_08,
-  input           up_rx_user_ready_08,
-  output          up_rx_rst_done_08,
-  input           up_rx_lpm_dfe_n_08,
-  input   [ 2:0]  up_rx_rate_08,
-  input   [ 1:0]  up_rx_sys_clk_sel_08,
-  input   [ 2:0]  up_rx_out_clk_sel_08,
-  input   [ 7:0]  up_rx_sel_08,
-  input           up_rx_enb_08,
-  input   [11:0]  up_rx_addr_08,
-  input           up_rx_wr_08,
-  input   [15:0]  up_rx_wdata_08,
-  output  [15:0]  up_rx_rdata_08,
-  output          up_rx_ready_08,
-  input           up_tx_pll_rst_08,
-  output          up_tx_pll_locked_08,
-  input           up_tx_rst_08,
-  input           up_tx_user_ready_08,
-  output          up_tx_rst_done_08,
-  input           up_tx_lpm_dfe_n_08,
-  input   [ 2:0]  up_tx_rate_08,
-  input   [ 1:0]  up_tx_sys_clk_sel_08,
-  input   [ 2:0]  up_tx_out_clk_sel_08,
-  input   [ 7:0]  up_tx_sel_08,
-  input           up_tx_enb_08,
-  input   [11:0]  up_tx_addr_08,
-  input           up_tx_wr_08,
-  input   [15:0]  up_tx_wdata_08,
-  output  [15:0]  up_tx_rdata_08,
-  output          up_tx_ready_08,
+  input   [ 7:0]  up_cm_sel_8,
+  input           up_cm_enb_8,
+  input   [11:0]  up_cm_addr_8,
+  input           up_cm_wr_8,
+  input   [15:0]  up_cm_wdata_8,
+  output  [15:0]  up_cm_rdata_8,
+  output          up_cm_ready_8,
+  input   [ 7:0]  up_es_sel_8,
+  input           up_es_enb_8,
+  input   [11:0]  up_es_addr_8,
+  input           up_es_wr_8,
+  input   [15:0]  up_es_wdata_8,
+  output  [15:0]  up_es_rdata_8,
+  output          up_es_ready_8,
+  input           up_rx_pll_rst_8,
+  output          up_rx_pll_locked_8,
+  input           up_rx_rst_8,
+  input           up_rx_user_ready_8,
+  output          up_rx_rst_done_8,
+  input           up_rx_lpm_dfe_n_8,
+  input   [ 2:0]  up_rx_rate_8,
+  input   [ 1:0]  up_rx_sys_clk_sel_8,
+  input   [ 2:0]  up_rx_out_clk_sel_8,
+  input   [ 7:0]  up_rx_sel_8,
+  input           up_rx_enb_8,
+  input   [11:0]  up_rx_addr_8,
+  input           up_rx_wr_8,
+  input   [15:0]  up_rx_wdata_8,
+  output  [15:0]  up_rx_rdata_8,
+  output          up_rx_ready_8,
+  input           up_tx_pll_rst_8,
+  output          up_tx_pll_locked_8,
+  input           up_tx_rst_8,
+  input           up_tx_user_ready_8,
+  output          up_tx_rst_done_8,
+  input           up_tx_lpm_dfe_n_8,
+  input   [ 2:0]  up_tx_rate_8,
+  input   [ 1:0]  up_tx_sys_clk_sel_8,
+  input   [ 2:0]  up_tx_out_clk_sel_8,
+  input   [ 7:0]  up_tx_sel_8,
+  input           up_tx_enb_8,
+  input   [11:0]  up_tx_addr_8,
+  input           up_tx_wr_8,
+  input   [15:0]  up_tx_wdata_8,
+  output  [15:0]  up_tx_rdata_8,
+  output          up_tx_ready_8,
 
-  input           cpll_ref_clk_09,
+  input           cpll_ref_clk_9,
 
-  input           rx_09_p,
-  input           rx_09_n,
-  output          rx_out_clk_09,
-  input           rx_clk_09,
-  output  [ 3:0]  rx_charisk_09,
-  output  [ 3:0]  rx_disperr_09,
-  output  [ 3:0]  rx_notintable_09,
-  output  [31:0]  rx_data_09,
-  input           rx_calign_09,
+  input           rx_9_p,
+  input           rx_9_n,
+  output          rx_out_clk_9,
+  input           rx_clk_9,
+  output  [ 3:0]  rx_charisk_9,
+  output  [ 3:0]  rx_disperr_9,
+  output  [ 3:0]  rx_notintable_9,
+  output  [31:0]  rx_data_9,
+  input           rx_calign_9,
 
-  output          tx_09_p,
-  output          tx_09_n,
-  output          tx_out_clk_09,
-  input           tx_clk_09,
-  input   [ 3:0]  tx_charisk_09,
-  input   [31:0]  tx_data_09,
+  output          tx_9_p,
+  output          tx_9_n,
+  output          tx_out_clk_9,
+  input           tx_clk_9,
+  input   [ 3:0]  tx_charisk_9,
+  input   [31:0]  tx_data_9,
 
-  input   [ 7:0]  up_es_sel_09,
-  input           up_es_enb_09,
-  input   [11:0]  up_es_addr_09,
-  input           up_es_wr_09,
-  input   [15:0]  up_es_wdata_09,
-  output  [15:0]  up_es_rdata_09,
-  output          up_es_ready_09,
-  input           up_rx_pll_rst_09,
-  output          up_rx_pll_locked_09,
-  input           up_rx_rst_09,
-  input           up_rx_user_ready_09,
-  output          up_rx_rst_done_09,
-  input           up_rx_lpm_dfe_n_09,
-  input   [ 2:0]  up_rx_rate_09,
-  input   [ 1:0]  up_rx_sys_clk_sel_09,
-  input   [ 2:0]  up_rx_out_clk_sel_09,
-  input   [ 7:0]  up_rx_sel_09,
-  input           up_rx_enb_09,
-  input   [11:0]  up_rx_addr_09,
-  input           up_rx_wr_09,
-  input   [15:0]  up_rx_wdata_09,
-  output  [15:0]  up_rx_rdata_09,
-  output          up_rx_ready_09,
-  input           up_tx_pll_rst_09,
-  output          up_tx_pll_locked_09,
-  input           up_tx_rst_09,
-  input           up_tx_user_ready_09,
-  output          up_tx_rst_done_09,
-  input           up_tx_lpm_dfe_n_09,
-  input   [ 2:0]  up_tx_rate_09,
-  input   [ 1:0]  up_tx_sys_clk_sel_09,
-  input   [ 2:0]  up_tx_out_clk_sel_09,
-  input   [ 7:0]  up_tx_sel_09,
-  input           up_tx_enb_09,
-  input   [11:0]  up_tx_addr_09,
-  input           up_tx_wr_09,
-  input   [15:0]  up_tx_wdata_09,
-  output  [15:0]  up_tx_rdata_09,
-  output          up_tx_ready_09,
+  input   [ 7:0]  up_es_sel_9,
+  input           up_es_enb_9,
+  input   [11:0]  up_es_addr_9,
+  input           up_es_wr_9,
+  input   [15:0]  up_es_wdata_9,
+  output  [15:0]  up_es_rdata_9,
+  output          up_es_ready_9,
+  input           up_rx_pll_rst_9,
+  output          up_rx_pll_locked_9,
+  input           up_rx_rst_9,
+  input           up_rx_user_ready_9,
+  output          up_rx_rst_done_9,
+  input           up_rx_lpm_dfe_n_9,
+  input   [ 2:0]  up_rx_rate_9,
+  input   [ 1:0]  up_rx_sys_clk_sel_9,
+  input   [ 2:0]  up_rx_out_clk_sel_9,
+  input   [ 7:0]  up_rx_sel_9,
+  input           up_rx_enb_9,
+  input   [11:0]  up_rx_addr_9,
+  input           up_rx_wr_9,
+  input   [15:0]  up_rx_wdata_9,
+  output  [15:0]  up_rx_rdata_9,
+  output          up_rx_ready_9,
+  input           up_tx_pll_rst_9,
+  output          up_tx_pll_locked_9,
+  input           up_tx_rst_9,
+  input           up_tx_user_ready_9,
+  output          up_tx_rst_done_9,
+  input           up_tx_lpm_dfe_n_9,
+  input   [ 2:0]  up_tx_rate_9,
+  input   [ 1:0]  up_tx_sys_clk_sel_9,
+  input   [ 2:0]  up_tx_out_clk_sel_9,
+  input   [ 7:0]  up_tx_sel_9,
+  input           up_tx_enb_9,
+  input   [11:0]  up_tx_addr_9,
+  input           up_tx_wr_9,
+  input   [15:0]  up_tx_wdata_9,
+  output  [15:0]  up_tx_rdata_9,
+  output          up_tx_ready_9,
 
   input           cpll_ref_clk_10,
 
@@ -1020,7 +1021,8 @@ module util_adxcvr (
 
   // parameters
 
-  parameter   integer XCVR_ID = 0;
+  parameter   integer RX_NUM_OF_LANES = 8;
+  parameter   integer TX_NUM_OF_LANES = 8;
   parameter   integer GTH_OR_GTX_N = 0;
   parameter   integer CPLL_TX_OR_RX_N = 0;
   parameter   integer CPLL_FBDIV = 2;
@@ -1037,20 +1039,23 @@ module util_adxcvr (
   parameter   [26:0]  QPLL_CFG = 27'h06801C1;
   parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000;
 
+  localparam  integer NUM_OF_LANES = (TX_NUM_OF_LANES > RX_NUM_OF_LANES) ?
+    TX_NUM_OF_LANES : RX_NUM_OF_LANES;
+
   // internal signals
 
-  wire            qpll2ch_clk_00;
-  wire            qpll2ch_ref_clk_00;
-  wire            qpll2ch_locked_00;
-  wire            up_qpll_rst_00;
-  wire            qpll2ch_clk_04;
-  wire            qpll2ch_ref_clk_04;
-  wire            qpll2ch_locked_04;
-  wire            up_qpll_rst_04;
-  wire            qpll2ch_clk_08;
-  wire            qpll2ch_ref_clk_08;
-  wire            qpll2ch_locked_08;
-  wire            up_qpll_rst_08;
+  wire            qpll2ch_clk_0;
+  wire            qpll2ch_ref_clk_0;
+  wire            qpll2ch_locked_0;
+  wire            up_qpll_rst_0;
+  wire            qpll2ch_clk_4;
+  wire            qpll2ch_ref_clk_4;
+  wire            qpll2ch_locked_4;
+  wire            up_qpll_rst_4;
+  wire            qpll2ch_clk_8;
+  wire            qpll2ch_ref_clk_8;
+  wire            qpll2ch_locked_8;
+  wire            up_qpll_rst_8;
   wire            qpll2ch_clk_12;
   wire            qpll2ch_ref_clk_12;
   wire            qpll2ch_locked_12;
@@ -1058,44 +1063,50 @@ module util_adxcvr (
 
   // quad controls
 
-  assign up_qpll_rst_00 = (CPLL_TX_OR_RX_N == 0) ? up_tx_00.pll_rst : up_rx_00.pll_rst;
-  assign up_qpll_rst_04 = (CPLL_TX_OR_RX_N == 0) ? up_tx_04.pll_rst : up_rx_04.pll_rst;
-  assign up_qpll_rst_08 = (CPLL_TX_OR_RX_N == 0) ? up_tx_08.pll_rst : up_rx_08.pll_rst;
-  assign up_qpll_rst_12 = (CPLL_TX_OR_RX_N == 0) ? up_tx_12.pll_rst : up_rx_12.pll_rst;
+  assign up_qpll_rst_0 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_0 : up_rx_pll_rst_0;
+  assign up_qpll_rst_4 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_4 : up_rx_pll_rst_4;
+  assign up_qpll_rst_8 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_8 : up_rx_pll_rst_8;
+  assign up_qpll_rst_12 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_12 : up_rx_pll_rst_12;
 
   // instantiations
 
   generate
   if (NUM_OF_LANES >= 1) begin
   util_adxcvr_xcm #(
-    .XCVR_ID (n),
+    .XCVR_ID (0),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
     .QPLL_CFG (QPLL_CFG),
     .QPLL_FBDIV (QPLL_FBDIV))
-  i_xcm_00 (
-    .qpll_ref_clk (qpll_ref_clk_00),
-    .qpll2ch_clk (qpll2ch_clk_00),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
-    .qpll2ch_locked (qpll2ch_locked_00),
+  i_xcm_0 (
+    .qpll_ref_clk (qpll_ref_clk_0),
+    .qpll2ch_clk (qpll2ch_clk_0),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
+    .qpll2ch_locked (qpll2ch_locked_0),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_qpll_rst (up_qpll_rst_00),
-    .up_cm_sel (up_cm_sel_00),
-    .up_cm_enb (up_cm_enb_00),
-    .up_cm_addr (up_cm_addr_00),
-    .up_cm_wr (up_cm_wr_00),
-    .up_cm_wdata (up_cm_wdata_00),
-    .up_cm_rdata (up_cm_rdata_00),
-    .up_cm_ready (up_cm_ready_00));
+    .up_qpll_rst (up_qpll_rst_0),
+    .up_cm_sel (up_cm_sel_0),
+    .up_cm_enb (up_cm_enb_0),
+    .up_cm_addr (up_cm_addr_0),
+    .up_cm_wr (up_cm_wr_0),
+    .up_cm_wdata (up_cm_wdata_0),
+    .up_cm_rdata (up_cm_rdata_0),
+    .up_cm_ready (up_cm_ready_0));
+  end else begin
+  assign qpll2ch_clk_0 = 1'd0;
+  assign qpll2ch_ref_clk_0 = 1'd0;
+  assign qpll2ch_locked_0 = 1'd0;
+  assign up_cm_rdata_0 = 16'd0;
+  assign up_cm_ready_0 = 1'd0;
   end
   endgenerate
 
   generate
   if (NUM_OF_LANES >= 1) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (0),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1107,74 +1118,94 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_00 (
-    .qpll2ch_clk (qpll2ch_clk_00),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
-    .qpll2ch_locked (qpll2ch_locked_00),
-    .cpll_ref_clk (cpll_ref_clk_00),
-    .rx_p (rx_00_p),
-    .rx_n (rx_00_n),
-    .rx_out_clk (rx_out_clk_00),
-    .rx_clk (rx_clk_00),
-    .rx_charisk (rx_charisk_00),
-    .rx_disperr (rx_disperr_00),
-    .rx_notintable (rx_notintable_00),
-    .rx_data (rx_data_00),
-    .rx_calign (rx_calign_00),
-    .tx_p (tx_00_p),
-    .tx_n (tx_00_n),
-    .tx_out_clk (tx_out_clk_00),
-    .tx_clk (tx_clk_00),
-    .tx_charisk (tx_charisk_00),
-    .tx_data (tx_data_00),
+  i_xch_0 (
+    .qpll2ch_clk (qpll2ch_clk_0),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
+    .qpll2ch_locked (qpll2ch_locked_0),
+    .cpll_ref_clk (cpll_ref_clk_0),
+    .rx_p (rx_0_p),
+    .rx_n (rx_0_n),
+    .rx_out_clk (rx_out_clk_0),
+    .rx_clk (rx_clk_0),
+    .rx_charisk (rx_charisk_0),
+    .rx_disperr (rx_disperr_0),
+    .rx_notintable (rx_notintable_0),
+    .rx_data (rx_data_0),
+    .rx_calign (rx_calign_0),
+    .tx_p (tx_0_p),
+    .tx_n (tx_0_n),
+    .tx_out_clk (tx_out_clk_0),
+    .tx_clk (tx_clk_0),
+    .tx_charisk (tx_charisk_0),
+    .tx_data (tx_data_0),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_00),
-    .up_es_enb (up_es_enb_00),
-    .up_es_addr (up_es_addr_00),
-    .up_es_wr (up_es_wr_00),
-    .up_es_wdata (up_es_wdata_00),
-    .up_es_rdata (up_es_rdata_00),
-    .up_es_ready (up_es_ready_00),
-    .up_rx_pll_rst (up_rx_pll_rst_00),
-    .up_rx_pll_locked (up_rx_pll_locked_00),
-    .up_rx_rst (up_rx_rst_00),
-    .up_rx_user_ready (up_rx_user_ready_00),
-    .up_rx_rst_done (up_rx_rst_done_00),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_00),
-    .up_rx_rate (up_rx_rate_00),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_00),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_00),
-    .up_rx_sel (up_rx_sel_00),
-    .up_rx_enb (up_rx_enb_00),
-    .up_rx_addr (up_rx_addr_00),
-    .up_rx_wr (up_rx_wr_00),
-    .up_rx_wdata (up_rx_wdata_00),
-    .up_rx_rdata (up_rx_rdata_00),
-    .up_rx_ready (up_rx_ready_00),
-    .up_tx_pll_rst (up_tx_pll_rst_00),
-    .up_tx_pll_locked (up_tx_pll_locked_00),
-    .up_tx_rst (up_tx_rst_00),
-    .up_tx_user_ready (up_tx_user_ready_00),
-    .up_tx_rst_done (up_tx_rst_done_00),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_00),
-    .up_tx_rate (up_tx_rate_00),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_00),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_00),
-    .up_tx_sel (up_tx_sel_00),
-    .up_tx_enb (up_tx_enb_00),
-    .up_tx_addr (up_tx_addr_00),
-    .up_tx_wr (up_tx_wr_00),
-    .up_tx_wdata (up_tx_wdata_00),
-    .up_tx_rdata (up_tx_rdata_00),
-    .up_tx_ready (up_tx_ready_00));
+    .up_es_sel (up_es_sel_0),
+    .up_es_enb (up_es_enb_0),
+    .up_es_addr (up_es_addr_0),
+    .up_es_wr (up_es_wr_0),
+    .up_es_wdata (up_es_wdata_0),
+    .up_es_rdata (up_es_rdata_0),
+    .up_es_ready (up_es_ready_0),
+    .up_rx_pll_rst (up_rx_pll_rst_0),
+    .up_rx_pll_locked (up_rx_pll_locked_0),
+    .up_rx_rst (up_rx_rst_0),
+    .up_rx_user_ready (up_rx_user_ready_0),
+    .up_rx_rst_done (up_rx_rst_done_0),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_0),
+    .up_rx_rate (up_rx_rate_0),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_0),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_0),
+    .up_rx_sel (up_rx_sel_0),
+    .up_rx_enb (up_rx_enb_0),
+    .up_rx_addr (up_rx_addr_0),
+    .up_rx_wr (up_rx_wr_0),
+    .up_rx_wdata (up_rx_wdata_0),
+    .up_rx_rdata (up_rx_rdata_0),
+    .up_rx_ready (up_rx_ready_0),
+    .up_tx_pll_rst (up_tx_pll_rst_0),
+    .up_tx_pll_locked (up_tx_pll_locked_0),
+    .up_tx_rst (up_tx_rst_0),
+    .up_tx_user_ready (up_tx_user_ready_0),
+    .up_tx_rst_done (up_tx_rst_done_0),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_0),
+    .up_tx_rate (up_tx_rate_0),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_0),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_0),
+    .up_tx_sel (up_tx_sel_0),
+    .up_tx_enb (up_tx_enb_0),
+    .up_tx_addr (up_tx_addr_0),
+    .up_tx_wr (up_tx_wr_0),
+    .up_tx_wdata (up_tx_wdata_0),
+    .up_tx_rdata (up_tx_rdata_0),
+    .up_tx_ready (up_tx_ready_0));
+  end else begin
+  assign rx_out_clk_0 = 1'd0;
+  assign rx_charisk_0 = 4'd0;
+  assign rx_disperr_0 = 4'd0;
+  assign rx_notintable_0 = 4'd0;
+  assign rx_data_0 = 32'd0;
+  assign tx_0_p = 1'd0;
+  assign tx_0_n = 1'd0;
+  assign tx_out_clk_0 = 1'd0;
+  assign up_es_rdata_0 = 16'd0;
+  assign up_es_ready_0 = 1'd0;
+  assign up_rx_pll_locked_0 = 1'd0;
+  assign up_rx_rst_done_0 = 1'd0;
+  assign up_rx_rdata_0 = 16'd0;
+  assign up_rx_ready_0 = 1'd0;
+  assign up_tx_pll_locked_0 = 1'd0;
+  assign up_tx_rst_done_0 = 1'd0;
+  assign up_tx_rdata_0 = 16'd0;
+  assign up_tx_ready_0 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 2) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (1),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1186,74 +1217,94 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_01 (
-    .qpll2ch_clk (qpll2ch_clk_00),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
-    .qpll2ch_locked (qpll2ch_locked_00),
-    .cpll_ref_clk (cpll_ref_clk_01),
-    .rx_p (rx_01_p),
-    .rx_n (rx_01_n),
-    .rx_out_clk (rx_out_clk_01),
-    .rx_clk (rx_clk_01),
-    .rx_charisk (rx_charisk_01),
-    .rx_disperr (rx_disperr_01),
-    .rx_notintable (rx_notintable_01),
-    .rx_data (rx_data_01),
-    .rx_calign (rx_calign_01),
-    .tx_p (tx_01_p),
-    .tx_n (tx_01_n),
-    .tx_out_clk (tx_out_clk_01),
-    .tx_clk (tx_clk_01),
-    .tx_charisk (tx_charisk_01),
-    .tx_data (tx_data_01),
+  i_xch_1 (
+    .qpll2ch_clk (qpll2ch_clk_0),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
+    .qpll2ch_locked (qpll2ch_locked_0),
+    .cpll_ref_clk (cpll_ref_clk_1),
+    .rx_p (rx_1_p),
+    .rx_n (rx_1_n),
+    .rx_out_clk (rx_out_clk_1),
+    .rx_clk (rx_clk_1),
+    .rx_charisk (rx_charisk_1),
+    .rx_disperr (rx_disperr_1),
+    .rx_notintable (rx_notintable_1),
+    .rx_data (rx_data_1),
+    .rx_calign (rx_calign_1),
+    .tx_p (tx_1_p),
+    .tx_n (tx_1_n),
+    .tx_out_clk (tx_out_clk_1),
+    .tx_clk (tx_clk_1),
+    .tx_charisk (tx_charisk_1),
+    .tx_data (tx_data_1),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_01),
-    .up_es_enb (up_es_enb_01),
-    .up_es_addr (up_es_addr_01),
-    .up_es_wr (up_es_wr_01),
-    .up_es_wdata (up_es_wdata_01),
-    .up_es_rdata (up_es_rdata_01),
-    .up_es_ready (up_es_ready_01),
-    .up_rx_pll_rst (up_rx_pll_rst_01),
-    .up_rx_pll_locked (up_rx_pll_locked_01),
-    .up_rx_rst (up_rx_rst_01),
-    .up_rx_user_ready (up_rx_user_ready_01),
-    .up_rx_rst_done (up_rx_rst_done_01),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_01),
-    .up_rx_rate (up_rx_rate_01),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_01),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_01),
-    .up_rx_sel (up_rx_sel_01),
-    .up_rx_enb (up_rx_enb_01),
-    .up_rx_addr (up_rx_addr_01),
-    .up_rx_wr (up_rx_wr_01),
-    .up_rx_wdata (up_rx_wdata_01),
-    .up_rx_rdata (up_rx_rdata_01),
-    .up_rx_ready (up_rx_ready_01),
-    .up_tx_pll_rst (up_tx_pll_rst_01),
-    .up_tx_pll_locked (up_tx_pll_locked_01),
-    .up_tx_rst (up_tx_rst_01),
-    .up_tx_user_ready (up_tx_user_ready_01),
-    .up_tx_rst_done (up_tx_rst_done_01),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_01),
-    .up_tx_rate (up_tx_rate_01),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_01),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_01),
-    .up_tx_sel (up_tx_sel_01),
-    .up_tx_enb (up_tx_enb_01),
-    .up_tx_addr (up_tx_addr_01),
-    .up_tx_wr (up_tx_wr_01),
-    .up_tx_wdata (up_tx_wdata_01),
-    .up_tx_rdata (up_tx_rdata_01),
-    .up_tx_ready (up_tx_ready_01));
+    .up_es_sel (up_es_sel_1),
+    .up_es_enb (up_es_enb_1),
+    .up_es_addr (up_es_addr_1),
+    .up_es_wr (up_es_wr_1),
+    .up_es_wdata (up_es_wdata_1),
+    .up_es_rdata (up_es_rdata_1),
+    .up_es_ready (up_es_ready_1),
+    .up_rx_pll_rst (up_rx_pll_rst_1),
+    .up_rx_pll_locked (up_rx_pll_locked_1),
+    .up_rx_rst (up_rx_rst_1),
+    .up_rx_user_ready (up_rx_user_ready_1),
+    .up_rx_rst_done (up_rx_rst_done_1),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_1),
+    .up_rx_rate (up_rx_rate_1),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_1),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_1),
+    .up_rx_sel (up_rx_sel_1),
+    .up_rx_enb (up_rx_enb_1),
+    .up_rx_addr (up_rx_addr_1),
+    .up_rx_wr (up_rx_wr_1),
+    .up_rx_wdata (up_rx_wdata_1),
+    .up_rx_rdata (up_rx_rdata_1),
+    .up_rx_ready (up_rx_ready_1),
+    .up_tx_pll_rst (up_tx_pll_rst_1),
+    .up_tx_pll_locked (up_tx_pll_locked_1),
+    .up_tx_rst (up_tx_rst_1),
+    .up_tx_user_ready (up_tx_user_ready_1),
+    .up_tx_rst_done (up_tx_rst_done_1),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_1),
+    .up_tx_rate (up_tx_rate_1),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_1),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_1),
+    .up_tx_sel (up_tx_sel_1),
+    .up_tx_enb (up_tx_enb_1),
+    .up_tx_addr (up_tx_addr_1),
+    .up_tx_wr (up_tx_wr_1),
+    .up_tx_wdata (up_tx_wdata_1),
+    .up_tx_rdata (up_tx_rdata_1),
+    .up_tx_ready (up_tx_ready_1));
+  end else begin
+  assign rx_out_clk_1 = 1'd0;
+  assign rx_charisk_1 = 4'd0;
+  assign rx_disperr_1 = 4'd0;
+  assign rx_notintable_1 = 4'd0;
+  assign rx_data_1 = 32'd0;
+  assign tx_1_p = 1'd0;
+  assign tx_1_n = 1'd0;
+  assign tx_out_clk_1 = 1'd0;
+  assign up_es_rdata_1 = 16'd0;
+  assign up_es_ready_1 = 1'd0;
+  assign up_rx_pll_locked_1 = 1'd0;
+  assign up_rx_rst_done_1 = 1'd0;
+  assign up_rx_rdata_1 = 16'd0;
+  assign up_rx_ready_1 = 1'd0;
+  assign up_tx_pll_locked_1 = 1'd0;
+  assign up_tx_rst_done_1 = 1'd0;
+  assign up_tx_rdata_1 = 16'd0;
+  assign up_tx_ready_1 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 3) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (2),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1265,74 +1316,94 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_02 (
-    .qpll2ch_clk (qpll2ch_clk_00),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
-    .qpll2ch_locked (qpll2ch_locked_00),
-    .cpll_ref_clk (cpll_ref_clk_02),
-    .rx_p (rx_02_p),
-    .rx_n (rx_02_n),
-    .rx_out_clk (rx_out_clk_02),
-    .rx_clk (rx_clk_02),
-    .rx_charisk (rx_charisk_02),
-    .rx_disperr (rx_disperr_02),
-    .rx_notintable (rx_notintable_02),
-    .rx_data (rx_data_02),
-    .rx_calign (rx_calign_02),
-    .tx_p (tx_02_p),
-    .tx_n (tx_02_n),
-    .tx_out_clk (tx_out_clk_02),
-    .tx_clk (tx_clk_02),
-    .tx_charisk (tx_charisk_02),
-    .tx_data (tx_data_02),
+  i_xch_2 (
+    .qpll2ch_clk (qpll2ch_clk_0),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
+    .qpll2ch_locked (qpll2ch_locked_0),
+    .cpll_ref_clk (cpll_ref_clk_2),
+    .rx_p (rx_2_p),
+    .rx_n (rx_2_n),
+    .rx_out_clk (rx_out_clk_2),
+    .rx_clk (rx_clk_2),
+    .rx_charisk (rx_charisk_2),
+    .rx_disperr (rx_disperr_2),
+    .rx_notintable (rx_notintable_2),
+    .rx_data (rx_data_2),
+    .rx_calign (rx_calign_2),
+    .tx_p (tx_2_p),
+    .tx_n (tx_2_n),
+    .tx_out_clk (tx_out_clk_2),
+    .tx_clk (tx_clk_2),
+    .tx_charisk (tx_charisk_2),
+    .tx_data (tx_data_2),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_02),
-    .up_es_enb (up_es_enb_02),
-    .up_es_addr (up_es_addr_02),
-    .up_es_wr (up_es_wr_02),
-    .up_es_wdata (up_es_wdata_02),
-    .up_es_rdata (up_es_rdata_02),
-    .up_es_ready (up_es_ready_02),
-    .up_rx_pll_rst (up_rx_pll_rst_02),
-    .up_rx_pll_locked (up_rx_pll_locked_02),
-    .up_rx_rst (up_rx_rst_02),
-    .up_rx_user_ready (up_rx_user_ready_02),
-    .up_rx_rst_done (up_rx_rst_done_02),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_02),
-    .up_rx_rate (up_rx_rate_02),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_02),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_02),
-    .up_rx_sel (up_rx_sel_02),
-    .up_rx_enb (up_rx_enb_02),
-    .up_rx_addr (up_rx_addr_02),
-    .up_rx_wr (up_rx_wr_02),
-    .up_rx_wdata (up_rx_wdata_02),
-    .up_rx_rdata (up_rx_rdata_02),
-    .up_rx_ready (up_rx_ready_02),
-    .up_tx_pll_rst (up_tx_pll_rst_02),
-    .up_tx_pll_locked (up_tx_pll_locked_02),
-    .up_tx_rst (up_tx_rst_02),
-    .up_tx_user_ready (up_tx_user_ready_02),
-    .up_tx_rst_done (up_tx_rst_done_02),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_02),
-    .up_tx_rate (up_tx_rate_02),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_02),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_02),
-    .up_tx_sel (up_tx_sel_02),
-    .up_tx_enb (up_tx_enb_02),
-    .up_tx_addr (up_tx_addr_02),
-    .up_tx_wr (up_tx_wr_02),
-    .up_tx_wdata (up_tx_wdata_02),
-    .up_tx_rdata (up_tx_rdata_02),
-    .up_tx_ready (up_tx_ready_02));
+    .up_es_sel (up_es_sel_2),
+    .up_es_enb (up_es_enb_2),
+    .up_es_addr (up_es_addr_2),
+    .up_es_wr (up_es_wr_2),
+    .up_es_wdata (up_es_wdata_2),
+    .up_es_rdata (up_es_rdata_2),
+    .up_es_ready (up_es_ready_2),
+    .up_rx_pll_rst (up_rx_pll_rst_2),
+    .up_rx_pll_locked (up_rx_pll_locked_2),
+    .up_rx_rst (up_rx_rst_2),
+    .up_rx_user_ready (up_rx_user_ready_2),
+    .up_rx_rst_done (up_rx_rst_done_2),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_2),
+    .up_rx_rate (up_rx_rate_2),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_2),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_2),
+    .up_rx_sel (up_rx_sel_2),
+    .up_rx_enb (up_rx_enb_2),
+    .up_rx_addr (up_rx_addr_2),
+    .up_rx_wr (up_rx_wr_2),
+    .up_rx_wdata (up_rx_wdata_2),
+    .up_rx_rdata (up_rx_rdata_2),
+    .up_rx_ready (up_rx_ready_2),
+    .up_tx_pll_rst (up_tx_pll_rst_2),
+    .up_tx_pll_locked (up_tx_pll_locked_2),
+    .up_tx_rst (up_tx_rst_2),
+    .up_tx_user_ready (up_tx_user_ready_2),
+    .up_tx_rst_done (up_tx_rst_done_2),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_2),
+    .up_tx_rate (up_tx_rate_2),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_2),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_2),
+    .up_tx_sel (up_tx_sel_2),
+    .up_tx_enb (up_tx_enb_2),
+    .up_tx_addr (up_tx_addr_2),
+    .up_tx_wr (up_tx_wr_2),
+    .up_tx_wdata (up_tx_wdata_2),
+    .up_tx_rdata (up_tx_rdata_2),
+    .up_tx_ready (up_tx_ready_2));
+  end else begin
+  assign rx_out_clk_2 = 1'd0;
+  assign rx_charisk_2 = 4'd0;
+  assign rx_disperr_2 = 4'd0;
+  assign rx_notintable_2 = 4'd0;
+  assign rx_data_2 = 32'd0;
+  assign tx_2_p = 1'd0;
+  assign tx_2_n = 1'd0;
+  assign tx_out_clk_2 = 1'd0;
+  assign up_es_rdata_2 = 16'd0;
+  assign up_es_ready_2 = 1'd0;
+  assign up_rx_pll_locked_2 = 1'd0;
+  assign up_rx_rst_done_2 = 1'd0;
+  assign up_rx_rdata_2 = 16'd0;
+  assign up_rx_ready_2 = 1'd0;
+  assign up_tx_pll_locked_2 = 1'd0;
+  assign up_tx_rst_done_2 = 1'd0;
+  assign up_tx_rdata_2 = 16'd0;
+  assign up_tx_ready_2 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 4) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (3),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1344,101 +1415,126 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_03 (
-    .qpll2ch_clk (qpll2ch_clk_00),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_00),
-    .qpll2ch_locked (qpll2ch_locked_00),
-    .cpll_ref_clk (cpll_ref_clk_03),
-    .rx_p (rx_03_p),
-    .rx_n (rx_03_n),
-    .rx_out_clk (rx_out_clk_03),
-    .rx_clk (rx_clk_03),
-    .rx_charisk (rx_charisk_03),
-    .rx_disperr (rx_disperr_03),
-    .rx_notintable (rx_notintable_03),
-    .rx_data (rx_data_03),
-    .rx_calign (rx_calign_03),
-    .tx_p (tx_03_p),
-    .tx_n (tx_03_n),
-    .tx_out_clk (tx_out_clk_03),
-    .tx_clk (tx_clk_03),
-    .tx_charisk (tx_charisk_03),
-    .tx_data (tx_data_03),
+  i_xch_3 (
+    .qpll2ch_clk (qpll2ch_clk_0),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
+    .qpll2ch_locked (qpll2ch_locked_0),
+    .cpll_ref_clk (cpll_ref_clk_3),
+    .rx_p (rx_3_p),
+    .rx_n (rx_3_n),
+    .rx_out_clk (rx_out_clk_3),
+    .rx_clk (rx_clk_3),
+    .rx_charisk (rx_charisk_3),
+    .rx_disperr (rx_disperr_3),
+    .rx_notintable (rx_notintable_3),
+    .rx_data (rx_data_3),
+    .rx_calign (rx_calign_3),
+    .tx_p (tx_3_p),
+    .tx_n (tx_3_n),
+    .tx_out_clk (tx_out_clk_3),
+    .tx_clk (tx_clk_3),
+    .tx_charisk (tx_charisk_3),
+    .tx_data (tx_data_3),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_03),
-    .up_es_enb (up_es_enb_03),
-    .up_es_addr (up_es_addr_03),
-    .up_es_wr (up_es_wr_03),
-    .up_es_wdata (up_es_wdata_03),
-    .up_es_rdata (up_es_rdata_03),
-    .up_es_ready (up_es_ready_03),
-    .up_rx_pll_rst (up_rx_pll_rst_03),
-    .up_rx_pll_locked (up_rx_pll_locked_03),
-    .up_rx_rst (up_rx_rst_03),
-    .up_rx_user_ready (up_rx_user_ready_03),
-    .up_rx_rst_done (up_rx_rst_done_03),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_03),
-    .up_rx_rate (up_rx_rate_03),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_03),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_03),
-    .up_rx_sel (up_rx_sel_03),
-    .up_rx_enb (up_rx_enb_03),
-    .up_rx_addr (up_rx_addr_03),
-    .up_rx_wr (up_rx_wr_03),
-    .up_rx_wdata (up_rx_wdata_03),
-    .up_rx_rdata (up_rx_rdata_03),
-    .up_rx_ready (up_rx_ready_03),
-    .up_tx_pll_rst (up_tx_pll_rst_03),
-    .up_tx_pll_locked (up_tx_pll_locked_03),
-    .up_tx_rst (up_tx_rst_03),
-    .up_tx_user_ready (up_tx_user_ready_03),
-    .up_tx_rst_done (up_tx_rst_done_03),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_03),
-    .up_tx_rate (up_tx_rate_03),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_03),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_03),
-    .up_tx_sel (up_tx_sel_03),
-    .up_tx_enb (up_tx_enb_03),
-    .up_tx_addr (up_tx_addr_03),
-    .up_tx_wr (up_tx_wr_03),
-    .up_tx_wdata (up_tx_wdata_03),
-    .up_tx_rdata (up_tx_rdata_03),
-    .up_tx_ready (up_tx_ready_03));
+    .up_es_sel (up_es_sel_3),
+    .up_es_enb (up_es_enb_3),
+    .up_es_addr (up_es_addr_3),
+    .up_es_wr (up_es_wr_3),
+    .up_es_wdata (up_es_wdata_3),
+    .up_es_rdata (up_es_rdata_3),
+    .up_es_ready (up_es_ready_3),
+    .up_rx_pll_rst (up_rx_pll_rst_3),
+    .up_rx_pll_locked (up_rx_pll_locked_3),
+    .up_rx_rst (up_rx_rst_3),
+    .up_rx_user_ready (up_rx_user_ready_3),
+    .up_rx_rst_done (up_rx_rst_done_3),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_3),
+    .up_rx_rate (up_rx_rate_3),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_3),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_3),
+    .up_rx_sel (up_rx_sel_3),
+    .up_rx_enb (up_rx_enb_3),
+    .up_rx_addr (up_rx_addr_3),
+    .up_rx_wr (up_rx_wr_3),
+    .up_rx_wdata (up_rx_wdata_3),
+    .up_rx_rdata (up_rx_rdata_3),
+    .up_rx_ready (up_rx_ready_3),
+    .up_tx_pll_rst (up_tx_pll_rst_3),
+    .up_tx_pll_locked (up_tx_pll_locked_3),
+    .up_tx_rst (up_tx_rst_3),
+    .up_tx_user_ready (up_tx_user_ready_3),
+    .up_tx_rst_done (up_tx_rst_done_3),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_3),
+    .up_tx_rate (up_tx_rate_3),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_3),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_3),
+    .up_tx_sel (up_tx_sel_3),
+    .up_tx_enb (up_tx_enb_3),
+    .up_tx_addr (up_tx_addr_3),
+    .up_tx_wr (up_tx_wr_3),
+    .up_tx_wdata (up_tx_wdata_3),
+    .up_tx_rdata (up_tx_rdata_3),
+    .up_tx_ready (up_tx_ready_3));
+  end else begin
+  assign rx_out_clk_3 = 1'd0;
+  assign rx_charisk_3 = 4'd0;
+  assign rx_disperr_3 = 4'd0;
+  assign rx_notintable_3 = 4'd0;
+  assign rx_data_3 = 32'd0;
+  assign tx_3_p = 1'd0;
+  assign tx_3_n = 1'd0;
+  assign tx_out_clk_3 = 1'd0;
+  assign up_es_rdata_3 = 16'd0;
+  assign up_es_ready_3 = 1'd0;
+  assign up_rx_pll_locked_3 = 1'd0;
+  assign up_rx_rst_done_3 = 1'd0;
+  assign up_rx_rdata_3 = 16'd0;
+  assign up_rx_ready_3 = 1'd0;
+  assign up_tx_pll_locked_3 = 1'd0;
+  assign up_tx_rst_done_3 = 1'd0;
+  assign up_tx_rdata_3 = 16'd0;
+  assign up_tx_ready_3 = 1'd0;
   end
   endgenerate
 
   generate
   if (NUM_OF_LANES >= 5) begin
   util_adxcvr_xcm #(
-    .XCVR_ID (n),
+    .XCVR_ID (4),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
     .QPLL_CFG (QPLL_CFG),
     .QPLL_FBDIV (QPLL_FBDIV))
-  i_xcm_04 (
-    .qpll_ref_clk (qpll_ref_clk_04),
-    .qpll2ch_clk (qpll2ch_clk_04),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
-    .qpll2ch_locked (qpll2ch_locked_04),
+  i_xcm_4 (
+    .qpll_ref_clk (qpll_ref_clk_4),
+    .qpll2ch_clk (qpll2ch_clk_4),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
+    .qpll2ch_locked (qpll2ch_locked_4),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_qpll_rst (up_qpll_rst_04),
-    .up_cm_sel (up_cm_sel_04),
-    .up_cm_enb (up_cm_enb_04),
-    .up_cm_addr (up_cm_addr_04),
-    .up_cm_wr (up_cm_wr_04),
-    .up_cm_wdata (up_cm_wdata_04),
-    .up_cm_rdata (up_cm_rdata_04),
-    .up_cm_ready (up_cm_ready_04));
+    .up_qpll_rst (up_qpll_rst_4),
+    .up_cm_sel (up_cm_sel_4),
+    .up_cm_enb (up_cm_enb_4),
+    .up_cm_addr (up_cm_addr_4),
+    .up_cm_wr (up_cm_wr_4),
+    .up_cm_wdata (up_cm_wdata_4),
+    .up_cm_rdata (up_cm_rdata_4),
+    .up_cm_ready (up_cm_ready_4));
+  end else begin
+  assign qpll2ch_clk_4 = 1'd0;
+  assign qpll2ch_ref_clk_4 = 1'd0;
+  assign qpll2ch_locked_4 = 1'd0;
+  assign up_cm_rdata_4 = 16'd0;
+  assign up_cm_ready_4 = 1'd0;
   end
   endgenerate
 
   generate
   if (NUM_OF_LANES >= 5) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (4),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1450,74 +1546,94 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_04 (
-    .qpll2ch_clk (qpll2ch_clk_04),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
-    .qpll2ch_locked (qpll2ch_locked_04),
-    .cpll_ref_clk (cpll_ref_clk_04),
-    .rx_p (rx_04_p),
-    .rx_n (rx_04_n),
-    .rx_out_clk (rx_out_clk_04),
-    .rx_clk (rx_clk_04),
-    .rx_charisk (rx_charisk_04),
-    .rx_disperr (rx_disperr_04),
-    .rx_notintable (rx_notintable_04),
-    .rx_data (rx_data_04),
-    .rx_calign (rx_calign_04),
-    .tx_p (tx_04_p),
-    .tx_n (tx_04_n),
-    .tx_out_clk (tx_out_clk_04),
-    .tx_clk (tx_clk_04),
-    .tx_charisk (tx_charisk_04),
-    .tx_data (tx_data_04),
+  i_xch_4 (
+    .qpll2ch_clk (qpll2ch_clk_4),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
+    .qpll2ch_locked (qpll2ch_locked_4),
+    .cpll_ref_clk (cpll_ref_clk_4),
+    .rx_p (rx_4_p),
+    .rx_n (rx_4_n),
+    .rx_out_clk (rx_out_clk_4),
+    .rx_clk (rx_clk_4),
+    .rx_charisk (rx_charisk_4),
+    .rx_disperr (rx_disperr_4),
+    .rx_notintable (rx_notintable_4),
+    .rx_data (rx_data_4),
+    .rx_calign (rx_calign_4),
+    .tx_p (tx_4_p),
+    .tx_n (tx_4_n),
+    .tx_out_clk (tx_out_clk_4),
+    .tx_clk (tx_clk_4),
+    .tx_charisk (tx_charisk_4),
+    .tx_data (tx_data_4),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_04),
-    .up_es_enb (up_es_enb_04),
-    .up_es_addr (up_es_addr_04),
-    .up_es_wr (up_es_wr_04),
-    .up_es_wdata (up_es_wdata_04),
-    .up_es_rdata (up_es_rdata_04),
-    .up_es_ready (up_es_ready_04),
-    .up_rx_pll_rst (up_rx_pll_rst_04),
-    .up_rx_pll_locked (up_rx_pll_locked_04),
-    .up_rx_rst (up_rx_rst_04),
-    .up_rx_user_ready (up_rx_user_ready_04),
-    .up_rx_rst_done (up_rx_rst_done_04),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_04),
-    .up_rx_rate (up_rx_rate_04),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_04),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_04),
-    .up_rx_sel (up_rx_sel_04),
-    .up_rx_enb (up_rx_enb_04),
-    .up_rx_addr (up_rx_addr_04),
-    .up_rx_wr (up_rx_wr_04),
-    .up_rx_wdata (up_rx_wdata_04),
-    .up_rx_rdata (up_rx_rdata_04),
-    .up_rx_ready (up_rx_ready_04),
-    .up_tx_pll_rst (up_tx_pll_rst_04),
-    .up_tx_pll_locked (up_tx_pll_locked_04),
-    .up_tx_rst (up_tx_rst_04),
-    .up_tx_user_ready (up_tx_user_ready_04),
-    .up_tx_rst_done (up_tx_rst_done_04),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_04),
-    .up_tx_rate (up_tx_rate_04),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_04),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_04),
-    .up_tx_sel (up_tx_sel_04),
-    .up_tx_enb (up_tx_enb_04),
-    .up_tx_addr (up_tx_addr_04),
-    .up_tx_wr (up_tx_wr_04),
-    .up_tx_wdata (up_tx_wdata_04),
-    .up_tx_rdata (up_tx_rdata_04),
-    .up_tx_ready (up_tx_ready_04));
+    .up_es_sel (up_es_sel_4),
+    .up_es_enb (up_es_enb_4),
+    .up_es_addr (up_es_addr_4),
+    .up_es_wr (up_es_wr_4),
+    .up_es_wdata (up_es_wdata_4),
+    .up_es_rdata (up_es_rdata_4),
+    .up_es_ready (up_es_ready_4),
+    .up_rx_pll_rst (up_rx_pll_rst_4),
+    .up_rx_pll_locked (up_rx_pll_locked_4),
+    .up_rx_rst (up_rx_rst_4),
+    .up_rx_user_ready (up_rx_user_ready_4),
+    .up_rx_rst_done (up_rx_rst_done_4),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_4),
+    .up_rx_rate (up_rx_rate_4),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_4),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_4),
+    .up_rx_sel (up_rx_sel_4),
+    .up_rx_enb (up_rx_enb_4),
+    .up_rx_addr (up_rx_addr_4),
+    .up_rx_wr (up_rx_wr_4),
+    .up_rx_wdata (up_rx_wdata_4),
+    .up_rx_rdata (up_rx_rdata_4),
+    .up_rx_ready (up_rx_ready_4),
+    .up_tx_pll_rst (up_tx_pll_rst_4),
+    .up_tx_pll_locked (up_tx_pll_locked_4),
+    .up_tx_rst (up_tx_rst_4),
+    .up_tx_user_ready (up_tx_user_ready_4),
+    .up_tx_rst_done (up_tx_rst_done_4),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_4),
+    .up_tx_rate (up_tx_rate_4),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_4),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_4),
+    .up_tx_sel (up_tx_sel_4),
+    .up_tx_enb (up_tx_enb_4),
+    .up_tx_addr (up_tx_addr_4),
+    .up_tx_wr (up_tx_wr_4),
+    .up_tx_wdata (up_tx_wdata_4),
+    .up_tx_rdata (up_tx_rdata_4),
+    .up_tx_ready (up_tx_ready_4));
+  end else begin
+  assign rx_out_clk_4 = 1'd0;
+  assign rx_charisk_4 = 4'd0;
+  assign rx_disperr_4 = 4'd0;
+  assign rx_notintable_4 = 4'd0;
+  assign rx_data_4 = 32'd0;
+  assign tx_4_p = 1'd0;
+  assign tx_4_n = 1'd0;
+  assign tx_out_clk_4 = 1'd0;
+  assign up_es_rdata_4 = 16'd0;
+  assign up_es_ready_4 = 1'd0;
+  assign up_rx_pll_locked_4 = 1'd0;
+  assign up_rx_rst_done_4 = 1'd0;
+  assign up_rx_rdata_4 = 16'd0;
+  assign up_rx_ready_4 = 1'd0;
+  assign up_tx_pll_locked_4 = 1'd0;
+  assign up_tx_rst_done_4 = 1'd0;
+  assign up_tx_rdata_4 = 16'd0;
+  assign up_tx_ready_4 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 6) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (5),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1529,74 +1645,94 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_05 (
-    .qpll2ch_clk (qpll2ch_clk_04),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
-    .qpll2ch_locked (qpll2ch_locked_04),
-    .cpll_ref_clk (cpll_ref_clk_05),
-    .rx_p (rx_05_p),
-    .rx_n (rx_05_n),
-    .rx_out_clk (rx_out_clk_05),
-    .rx_clk (rx_clk_05),
-    .rx_charisk (rx_charisk_05),
-    .rx_disperr (rx_disperr_05),
-    .rx_notintable (rx_notintable_05),
-    .rx_data (rx_data_05),
-    .rx_calign (rx_calign_05),
-    .tx_p (tx_05_p),
-    .tx_n (tx_05_n),
-    .tx_out_clk (tx_out_clk_05),
-    .tx_clk (tx_clk_05),
-    .tx_charisk (tx_charisk_05),
-    .tx_data (tx_data_05),
+  i_xch_5 (
+    .qpll2ch_clk (qpll2ch_clk_4),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
+    .qpll2ch_locked (qpll2ch_locked_4),
+    .cpll_ref_clk (cpll_ref_clk_5),
+    .rx_p (rx_5_p),
+    .rx_n (rx_5_n),
+    .rx_out_clk (rx_out_clk_5),
+    .rx_clk (rx_clk_5),
+    .rx_charisk (rx_charisk_5),
+    .rx_disperr (rx_disperr_5),
+    .rx_notintable (rx_notintable_5),
+    .rx_data (rx_data_5),
+    .rx_calign (rx_calign_5),
+    .tx_p (tx_5_p),
+    .tx_n (tx_5_n),
+    .tx_out_clk (tx_out_clk_5),
+    .tx_clk (tx_clk_5),
+    .tx_charisk (tx_charisk_5),
+    .tx_data (tx_data_5),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_05),
-    .up_es_enb (up_es_enb_05),
-    .up_es_addr (up_es_addr_05),
-    .up_es_wr (up_es_wr_05),
-    .up_es_wdata (up_es_wdata_05),
-    .up_es_rdata (up_es_rdata_05),
-    .up_es_ready (up_es_ready_05),
-    .up_rx_pll_rst (up_rx_pll_rst_05),
-    .up_rx_pll_locked (up_rx_pll_locked_05),
-    .up_rx_rst (up_rx_rst_05),
-    .up_rx_user_ready (up_rx_user_ready_05),
-    .up_rx_rst_done (up_rx_rst_done_05),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_05),
-    .up_rx_rate (up_rx_rate_05),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_05),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_05),
-    .up_rx_sel (up_rx_sel_05),
-    .up_rx_enb (up_rx_enb_05),
-    .up_rx_addr (up_rx_addr_05),
-    .up_rx_wr (up_rx_wr_05),
-    .up_rx_wdata (up_rx_wdata_05),
-    .up_rx_rdata (up_rx_rdata_05),
-    .up_rx_ready (up_rx_ready_05),
-    .up_tx_pll_rst (up_tx_pll_rst_05),
-    .up_tx_pll_locked (up_tx_pll_locked_05),
-    .up_tx_rst (up_tx_rst_05),
-    .up_tx_user_ready (up_tx_user_ready_05),
-    .up_tx_rst_done (up_tx_rst_done_05),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_05),
-    .up_tx_rate (up_tx_rate_05),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_05),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_05),
-    .up_tx_sel (up_tx_sel_05),
-    .up_tx_enb (up_tx_enb_05),
-    .up_tx_addr (up_tx_addr_05),
-    .up_tx_wr (up_tx_wr_05),
-    .up_tx_wdata (up_tx_wdata_05),
-    .up_tx_rdata (up_tx_rdata_05),
-    .up_tx_ready (up_tx_ready_05));
+    .up_es_sel (up_es_sel_5),
+    .up_es_enb (up_es_enb_5),
+    .up_es_addr (up_es_addr_5),
+    .up_es_wr (up_es_wr_5),
+    .up_es_wdata (up_es_wdata_5),
+    .up_es_rdata (up_es_rdata_5),
+    .up_es_ready (up_es_ready_5),
+    .up_rx_pll_rst (up_rx_pll_rst_5),
+    .up_rx_pll_locked (up_rx_pll_locked_5),
+    .up_rx_rst (up_rx_rst_5),
+    .up_rx_user_ready (up_rx_user_ready_5),
+    .up_rx_rst_done (up_rx_rst_done_5),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_5),
+    .up_rx_rate (up_rx_rate_5),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_5),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_5),
+    .up_rx_sel (up_rx_sel_5),
+    .up_rx_enb (up_rx_enb_5),
+    .up_rx_addr (up_rx_addr_5),
+    .up_rx_wr (up_rx_wr_5),
+    .up_rx_wdata (up_rx_wdata_5),
+    .up_rx_rdata (up_rx_rdata_5),
+    .up_rx_ready (up_rx_ready_5),
+    .up_tx_pll_rst (up_tx_pll_rst_5),
+    .up_tx_pll_locked (up_tx_pll_locked_5),
+    .up_tx_rst (up_tx_rst_5),
+    .up_tx_user_ready (up_tx_user_ready_5),
+    .up_tx_rst_done (up_tx_rst_done_5),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_5),
+    .up_tx_rate (up_tx_rate_5),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_5),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_5),
+    .up_tx_sel (up_tx_sel_5),
+    .up_tx_enb (up_tx_enb_5),
+    .up_tx_addr (up_tx_addr_5),
+    .up_tx_wr (up_tx_wr_5),
+    .up_tx_wdata (up_tx_wdata_5),
+    .up_tx_rdata (up_tx_rdata_5),
+    .up_tx_ready (up_tx_ready_5));
+  end else begin
+  assign rx_out_clk_5 = 1'd0;
+  assign rx_charisk_5 = 4'd0;
+  assign rx_disperr_5 = 4'd0;
+  assign rx_notintable_5 = 4'd0;
+  assign rx_data_5 = 32'd0;
+  assign tx_5_p = 1'd0;
+  assign tx_5_n = 1'd0;
+  assign tx_out_clk_5 = 1'd0;
+  assign up_es_rdata_5 = 16'd0;
+  assign up_es_ready_5 = 1'd0;
+  assign up_rx_pll_locked_5 = 1'd0;
+  assign up_rx_rst_done_5 = 1'd0;
+  assign up_rx_rdata_5 = 16'd0;
+  assign up_rx_ready_5 = 1'd0;
+  assign up_tx_pll_locked_5 = 1'd0;
+  assign up_tx_rst_done_5 = 1'd0;
+  assign up_tx_rdata_5 = 16'd0;
+  assign up_tx_ready_5 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 7) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (6),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1608,74 +1744,94 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_06 (
-    .qpll2ch_clk (qpll2ch_clk_04),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
-    .qpll2ch_locked (qpll2ch_locked_04),
-    .cpll_ref_clk (cpll_ref_clk_06),
-    .rx_p (rx_06_p),
-    .rx_n (rx_06_n),
-    .rx_out_clk (rx_out_clk_06),
-    .rx_clk (rx_clk_06),
-    .rx_charisk (rx_charisk_06),
-    .rx_disperr (rx_disperr_06),
-    .rx_notintable (rx_notintable_06),
-    .rx_data (rx_data_06),
-    .rx_calign (rx_calign_06),
-    .tx_p (tx_06_p),
-    .tx_n (tx_06_n),
-    .tx_out_clk (tx_out_clk_06),
-    .tx_clk (tx_clk_06),
-    .tx_charisk (tx_charisk_06),
-    .tx_data (tx_data_06),
+  i_xch_6 (
+    .qpll2ch_clk (qpll2ch_clk_4),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
+    .qpll2ch_locked (qpll2ch_locked_4),
+    .cpll_ref_clk (cpll_ref_clk_6),
+    .rx_p (rx_6_p),
+    .rx_n (rx_6_n),
+    .rx_out_clk (rx_out_clk_6),
+    .rx_clk (rx_clk_6),
+    .rx_charisk (rx_charisk_6),
+    .rx_disperr (rx_disperr_6),
+    .rx_notintable (rx_notintable_6),
+    .rx_data (rx_data_6),
+    .rx_calign (rx_calign_6),
+    .tx_p (tx_6_p),
+    .tx_n (tx_6_n),
+    .tx_out_clk (tx_out_clk_6),
+    .tx_clk (tx_clk_6),
+    .tx_charisk (tx_charisk_6),
+    .tx_data (tx_data_6),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_06),
-    .up_es_enb (up_es_enb_06),
-    .up_es_addr (up_es_addr_06),
-    .up_es_wr (up_es_wr_06),
-    .up_es_wdata (up_es_wdata_06),
-    .up_es_rdata (up_es_rdata_06),
-    .up_es_ready (up_es_ready_06),
-    .up_rx_pll_rst (up_rx_pll_rst_06),
-    .up_rx_pll_locked (up_rx_pll_locked_06),
-    .up_rx_rst (up_rx_rst_06),
-    .up_rx_user_ready (up_rx_user_ready_06),
-    .up_rx_rst_done (up_rx_rst_done_06),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_06),
-    .up_rx_rate (up_rx_rate_06),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_06),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_06),
-    .up_rx_sel (up_rx_sel_06),
-    .up_rx_enb (up_rx_enb_06),
-    .up_rx_addr (up_rx_addr_06),
-    .up_rx_wr (up_rx_wr_06),
-    .up_rx_wdata (up_rx_wdata_06),
-    .up_rx_rdata (up_rx_rdata_06),
-    .up_rx_ready (up_rx_ready_06),
-    .up_tx_pll_rst (up_tx_pll_rst_06),
-    .up_tx_pll_locked (up_tx_pll_locked_06),
-    .up_tx_rst (up_tx_rst_06),
-    .up_tx_user_ready (up_tx_user_ready_06),
-    .up_tx_rst_done (up_tx_rst_done_06),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_06),
-    .up_tx_rate (up_tx_rate_06),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_06),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_06),
-    .up_tx_sel (up_tx_sel_06),
-    .up_tx_enb (up_tx_enb_06),
-    .up_tx_addr (up_tx_addr_06),
-    .up_tx_wr (up_tx_wr_06),
-    .up_tx_wdata (up_tx_wdata_06),
-    .up_tx_rdata (up_tx_rdata_06),
-    .up_tx_ready (up_tx_ready_06));
+    .up_es_sel (up_es_sel_6),
+    .up_es_enb (up_es_enb_6),
+    .up_es_addr (up_es_addr_6),
+    .up_es_wr (up_es_wr_6),
+    .up_es_wdata (up_es_wdata_6),
+    .up_es_rdata (up_es_rdata_6),
+    .up_es_ready (up_es_ready_6),
+    .up_rx_pll_rst (up_rx_pll_rst_6),
+    .up_rx_pll_locked (up_rx_pll_locked_6),
+    .up_rx_rst (up_rx_rst_6),
+    .up_rx_user_ready (up_rx_user_ready_6),
+    .up_rx_rst_done (up_rx_rst_done_6),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_6),
+    .up_rx_rate (up_rx_rate_6),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_6),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_6),
+    .up_rx_sel (up_rx_sel_6),
+    .up_rx_enb (up_rx_enb_6),
+    .up_rx_addr (up_rx_addr_6),
+    .up_rx_wr (up_rx_wr_6),
+    .up_rx_wdata (up_rx_wdata_6),
+    .up_rx_rdata (up_rx_rdata_6),
+    .up_rx_ready (up_rx_ready_6),
+    .up_tx_pll_rst (up_tx_pll_rst_6),
+    .up_tx_pll_locked (up_tx_pll_locked_6),
+    .up_tx_rst (up_tx_rst_6),
+    .up_tx_user_ready (up_tx_user_ready_6),
+    .up_tx_rst_done (up_tx_rst_done_6),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_6),
+    .up_tx_rate (up_tx_rate_6),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_6),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_6),
+    .up_tx_sel (up_tx_sel_6),
+    .up_tx_enb (up_tx_enb_6),
+    .up_tx_addr (up_tx_addr_6),
+    .up_tx_wr (up_tx_wr_6),
+    .up_tx_wdata (up_tx_wdata_6),
+    .up_tx_rdata (up_tx_rdata_6),
+    .up_tx_ready (up_tx_ready_6));
+  end else begin
+  assign rx_out_clk_6 = 1'd0;
+  assign rx_charisk_6 = 4'd0;
+  assign rx_disperr_6 = 4'd0;
+  assign rx_notintable_6 = 4'd0;
+  assign rx_data_6 = 32'd0;
+  assign tx_6_p = 1'd0;
+  assign tx_6_n = 1'd0;
+  assign tx_out_clk_6 = 1'd0;
+  assign up_es_rdata_6 = 16'd0;
+  assign up_es_ready_6 = 1'd0;
+  assign up_rx_pll_locked_6 = 1'd0;
+  assign up_rx_rst_done_6 = 1'd0;
+  assign up_rx_rdata_6 = 16'd0;
+  assign up_rx_ready_6 = 1'd0;
+  assign up_tx_pll_locked_6 = 1'd0;
+  assign up_tx_rst_done_6 = 1'd0;
+  assign up_tx_rdata_6 = 16'd0;
+  assign up_tx_ready_6 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 8) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (7),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1687,101 +1843,126 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_07 (
-    .qpll2ch_clk (qpll2ch_clk_04),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_04),
-    .qpll2ch_locked (qpll2ch_locked_04),
-    .cpll_ref_clk (cpll_ref_clk_07),
-    .rx_p (rx_07_p),
-    .rx_n (rx_07_n),
-    .rx_out_clk (rx_out_clk_07),
-    .rx_clk (rx_clk_07),
-    .rx_charisk (rx_charisk_07),
-    .rx_disperr (rx_disperr_07),
-    .rx_notintable (rx_notintable_07),
-    .rx_data (rx_data_07),
-    .rx_calign (rx_calign_07),
-    .tx_p (tx_07_p),
-    .tx_n (tx_07_n),
-    .tx_out_clk (tx_out_clk_07),
-    .tx_clk (tx_clk_07),
-    .tx_charisk (tx_charisk_07),
-    .tx_data (tx_data_07),
+  i_xch_7 (
+    .qpll2ch_clk (qpll2ch_clk_4),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
+    .qpll2ch_locked (qpll2ch_locked_4),
+    .cpll_ref_clk (cpll_ref_clk_7),
+    .rx_p (rx_7_p),
+    .rx_n (rx_7_n),
+    .rx_out_clk (rx_out_clk_7),
+    .rx_clk (rx_clk_7),
+    .rx_charisk (rx_charisk_7),
+    .rx_disperr (rx_disperr_7),
+    .rx_notintable (rx_notintable_7),
+    .rx_data (rx_data_7),
+    .rx_calign (rx_calign_7),
+    .tx_p (tx_7_p),
+    .tx_n (tx_7_n),
+    .tx_out_clk (tx_out_clk_7),
+    .tx_clk (tx_clk_7),
+    .tx_charisk (tx_charisk_7),
+    .tx_data (tx_data_7),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_07),
-    .up_es_enb (up_es_enb_07),
-    .up_es_addr (up_es_addr_07),
-    .up_es_wr (up_es_wr_07),
-    .up_es_wdata (up_es_wdata_07),
-    .up_es_rdata (up_es_rdata_07),
-    .up_es_ready (up_es_ready_07),
-    .up_rx_pll_rst (up_rx_pll_rst_07),
-    .up_rx_pll_locked (up_rx_pll_locked_07),
-    .up_rx_rst (up_rx_rst_07),
-    .up_rx_user_ready (up_rx_user_ready_07),
-    .up_rx_rst_done (up_rx_rst_done_07),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_07),
-    .up_rx_rate (up_rx_rate_07),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_07),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_07),
-    .up_rx_sel (up_rx_sel_07),
-    .up_rx_enb (up_rx_enb_07),
-    .up_rx_addr (up_rx_addr_07),
-    .up_rx_wr (up_rx_wr_07),
-    .up_rx_wdata (up_rx_wdata_07),
-    .up_rx_rdata (up_rx_rdata_07),
-    .up_rx_ready (up_rx_ready_07),
-    .up_tx_pll_rst (up_tx_pll_rst_07),
-    .up_tx_pll_locked (up_tx_pll_locked_07),
-    .up_tx_rst (up_tx_rst_07),
-    .up_tx_user_ready (up_tx_user_ready_07),
-    .up_tx_rst_done (up_tx_rst_done_07),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_07),
-    .up_tx_rate (up_tx_rate_07),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_07),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_07),
-    .up_tx_sel (up_tx_sel_07),
-    .up_tx_enb (up_tx_enb_07),
-    .up_tx_addr (up_tx_addr_07),
-    .up_tx_wr (up_tx_wr_07),
-    .up_tx_wdata (up_tx_wdata_07),
-    .up_tx_rdata (up_tx_rdata_07),
-    .up_tx_ready (up_tx_ready_07));
+    .up_es_sel (up_es_sel_7),
+    .up_es_enb (up_es_enb_7),
+    .up_es_addr (up_es_addr_7),
+    .up_es_wr (up_es_wr_7),
+    .up_es_wdata (up_es_wdata_7),
+    .up_es_rdata (up_es_rdata_7),
+    .up_es_ready (up_es_ready_7),
+    .up_rx_pll_rst (up_rx_pll_rst_7),
+    .up_rx_pll_locked (up_rx_pll_locked_7),
+    .up_rx_rst (up_rx_rst_7),
+    .up_rx_user_ready (up_rx_user_ready_7),
+    .up_rx_rst_done (up_rx_rst_done_7),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_7),
+    .up_rx_rate (up_rx_rate_7),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_7),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_7),
+    .up_rx_sel (up_rx_sel_7),
+    .up_rx_enb (up_rx_enb_7),
+    .up_rx_addr (up_rx_addr_7),
+    .up_rx_wr (up_rx_wr_7),
+    .up_rx_wdata (up_rx_wdata_7),
+    .up_rx_rdata (up_rx_rdata_7),
+    .up_rx_ready (up_rx_ready_7),
+    .up_tx_pll_rst (up_tx_pll_rst_7),
+    .up_tx_pll_locked (up_tx_pll_locked_7),
+    .up_tx_rst (up_tx_rst_7),
+    .up_tx_user_ready (up_tx_user_ready_7),
+    .up_tx_rst_done (up_tx_rst_done_7),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_7),
+    .up_tx_rate (up_tx_rate_7),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_7),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_7),
+    .up_tx_sel (up_tx_sel_7),
+    .up_tx_enb (up_tx_enb_7),
+    .up_tx_addr (up_tx_addr_7),
+    .up_tx_wr (up_tx_wr_7),
+    .up_tx_wdata (up_tx_wdata_7),
+    .up_tx_rdata (up_tx_rdata_7),
+    .up_tx_ready (up_tx_ready_7));
+  end else begin
+  assign rx_out_clk_7 = 1'd0;
+  assign rx_charisk_7 = 4'd0;
+  assign rx_disperr_7 = 4'd0;
+  assign rx_notintable_7 = 4'd0;
+  assign rx_data_7 = 32'd0;
+  assign tx_7_p = 1'd0;
+  assign tx_7_n = 1'd0;
+  assign tx_out_clk_7 = 1'd0;
+  assign up_es_rdata_7 = 16'd0;
+  assign up_es_ready_7 = 1'd0;
+  assign up_rx_pll_locked_7 = 1'd0;
+  assign up_rx_rst_done_7 = 1'd0;
+  assign up_rx_rdata_7 = 16'd0;
+  assign up_rx_ready_7 = 1'd0;
+  assign up_tx_pll_locked_7 = 1'd0;
+  assign up_tx_rst_done_7 = 1'd0;
+  assign up_tx_rdata_7 = 16'd0;
+  assign up_tx_ready_7 = 1'd0;
   end
   endgenerate
 
   generate
   if (NUM_OF_LANES >= 9) begin
   util_adxcvr_xcm #(
-    .XCVR_ID (n),
+    .XCVR_ID (8),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
     .QPLL_CFG (QPLL_CFG),
     .QPLL_FBDIV (QPLL_FBDIV))
-  i_xcm_08 (
-    .qpll_ref_clk (qpll_ref_clk_08),
-    .qpll2ch_clk (qpll2ch_clk_08),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
-    .qpll2ch_locked (qpll2ch_locked_08),
+  i_xcm_8 (
+    .qpll_ref_clk (qpll_ref_clk_8),
+    .qpll2ch_clk (qpll2ch_clk_8),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
+    .qpll2ch_locked (qpll2ch_locked_8),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_qpll_rst (up_qpll_rst_08),
-    .up_cm_sel (up_cm_sel_08),
-    .up_cm_enb (up_cm_enb_08),
-    .up_cm_addr (up_cm_addr_08),
-    .up_cm_wr (up_cm_wr_08),
-    .up_cm_wdata (up_cm_wdata_08),
-    .up_cm_rdata (up_cm_rdata_08),
-    .up_cm_ready (up_cm_ready_08));
+    .up_qpll_rst (up_qpll_rst_8),
+    .up_cm_sel (up_cm_sel_8),
+    .up_cm_enb (up_cm_enb_8),
+    .up_cm_addr (up_cm_addr_8),
+    .up_cm_wr (up_cm_wr_8),
+    .up_cm_wdata (up_cm_wdata_8),
+    .up_cm_rdata (up_cm_rdata_8),
+    .up_cm_ready (up_cm_ready_8));
+  end else begin
+  assign qpll2ch_clk_8 = 1'd0;
+  assign qpll2ch_ref_clk_8 = 1'd0;
+  assign qpll2ch_locked_8 = 1'd0;
+  assign up_cm_rdata_8 = 16'd0;
+  assign up_cm_ready_8 = 1'd0;
   end
   endgenerate
 
   generate
   if (NUM_OF_LANES >= 9) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (8),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1793,74 +1974,94 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_08 (
-    .qpll2ch_clk (qpll2ch_clk_08),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
-    .qpll2ch_locked (qpll2ch_locked_08),
-    .cpll_ref_clk (cpll_ref_clk_08),
-    .rx_p (rx_08_p),
-    .rx_n (rx_08_n),
-    .rx_out_clk (rx_out_clk_08),
-    .rx_clk (rx_clk_08),
-    .rx_charisk (rx_charisk_08),
-    .rx_disperr (rx_disperr_08),
-    .rx_notintable (rx_notintable_08),
-    .rx_data (rx_data_08),
-    .rx_calign (rx_calign_08),
-    .tx_p (tx_08_p),
-    .tx_n (tx_08_n),
-    .tx_out_clk (tx_out_clk_08),
-    .tx_clk (tx_clk_08),
-    .tx_charisk (tx_charisk_08),
-    .tx_data (tx_data_08),
+  i_xch_8 (
+    .qpll2ch_clk (qpll2ch_clk_8),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
+    .qpll2ch_locked (qpll2ch_locked_8),
+    .cpll_ref_clk (cpll_ref_clk_8),
+    .rx_p (rx_8_p),
+    .rx_n (rx_8_n),
+    .rx_out_clk (rx_out_clk_8),
+    .rx_clk (rx_clk_8),
+    .rx_charisk (rx_charisk_8),
+    .rx_disperr (rx_disperr_8),
+    .rx_notintable (rx_notintable_8),
+    .rx_data (rx_data_8),
+    .rx_calign (rx_calign_8),
+    .tx_p (tx_8_p),
+    .tx_n (tx_8_n),
+    .tx_out_clk (tx_out_clk_8),
+    .tx_clk (tx_clk_8),
+    .tx_charisk (tx_charisk_8),
+    .tx_data (tx_data_8),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_08),
-    .up_es_enb (up_es_enb_08),
-    .up_es_addr (up_es_addr_08),
-    .up_es_wr (up_es_wr_08),
-    .up_es_wdata (up_es_wdata_08),
-    .up_es_rdata (up_es_rdata_08),
-    .up_es_ready (up_es_ready_08),
-    .up_rx_pll_rst (up_rx_pll_rst_08),
-    .up_rx_pll_locked (up_rx_pll_locked_08),
-    .up_rx_rst (up_rx_rst_08),
-    .up_rx_user_ready (up_rx_user_ready_08),
-    .up_rx_rst_done (up_rx_rst_done_08),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_08),
-    .up_rx_rate (up_rx_rate_08),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_08),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_08),
-    .up_rx_sel (up_rx_sel_08),
-    .up_rx_enb (up_rx_enb_08),
-    .up_rx_addr (up_rx_addr_08),
-    .up_rx_wr (up_rx_wr_08),
-    .up_rx_wdata (up_rx_wdata_08),
-    .up_rx_rdata (up_rx_rdata_08),
-    .up_rx_ready (up_rx_ready_08),
-    .up_tx_pll_rst (up_tx_pll_rst_08),
-    .up_tx_pll_locked (up_tx_pll_locked_08),
-    .up_tx_rst (up_tx_rst_08),
-    .up_tx_user_ready (up_tx_user_ready_08),
-    .up_tx_rst_done (up_tx_rst_done_08),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_08),
-    .up_tx_rate (up_tx_rate_08),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_08),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_08),
-    .up_tx_sel (up_tx_sel_08),
-    .up_tx_enb (up_tx_enb_08),
-    .up_tx_addr (up_tx_addr_08),
-    .up_tx_wr (up_tx_wr_08),
-    .up_tx_wdata (up_tx_wdata_08),
-    .up_tx_rdata (up_tx_rdata_08),
-    .up_tx_ready (up_tx_ready_08));
+    .up_es_sel (up_es_sel_8),
+    .up_es_enb (up_es_enb_8),
+    .up_es_addr (up_es_addr_8),
+    .up_es_wr (up_es_wr_8),
+    .up_es_wdata (up_es_wdata_8),
+    .up_es_rdata (up_es_rdata_8),
+    .up_es_ready (up_es_ready_8),
+    .up_rx_pll_rst (up_rx_pll_rst_8),
+    .up_rx_pll_locked (up_rx_pll_locked_8),
+    .up_rx_rst (up_rx_rst_8),
+    .up_rx_user_ready (up_rx_user_ready_8),
+    .up_rx_rst_done (up_rx_rst_done_8),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_8),
+    .up_rx_rate (up_rx_rate_8),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_8),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_8),
+    .up_rx_sel (up_rx_sel_8),
+    .up_rx_enb (up_rx_enb_8),
+    .up_rx_addr (up_rx_addr_8),
+    .up_rx_wr (up_rx_wr_8),
+    .up_rx_wdata (up_rx_wdata_8),
+    .up_rx_rdata (up_rx_rdata_8),
+    .up_rx_ready (up_rx_ready_8),
+    .up_tx_pll_rst (up_tx_pll_rst_8),
+    .up_tx_pll_locked (up_tx_pll_locked_8),
+    .up_tx_rst (up_tx_rst_8),
+    .up_tx_user_ready (up_tx_user_ready_8),
+    .up_tx_rst_done (up_tx_rst_done_8),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_8),
+    .up_tx_rate (up_tx_rate_8),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_8),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_8),
+    .up_tx_sel (up_tx_sel_8),
+    .up_tx_enb (up_tx_enb_8),
+    .up_tx_addr (up_tx_addr_8),
+    .up_tx_wr (up_tx_wr_8),
+    .up_tx_wdata (up_tx_wdata_8),
+    .up_tx_rdata (up_tx_rdata_8),
+    .up_tx_ready (up_tx_ready_8));
+  end else begin
+  assign rx_out_clk_8 = 1'd0;
+  assign rx_charisk_8 = 4'd0;
+  assign rx_disperr_8 = 4'd0;
+  assign rx_notintable_8 = 4'd0;
+  assign rx_data_8 = 32'd0;
+  assign tx_8_p = 1'd0;
+  assign tx_8_n = 1'd0;
+  assign tx_out_clk_8 = 1'd0;
+  assign up_es_rdata_8 = 16'd0;
+  assign up_es_ready_8 = 1'd0;
+  assign up_rx_pll_locked_8 = 1'd0;
+  assign up_rx_rst_done_8 = 1'd0;
+  assign up_rx_rdata_8 = 16'd0;
+  assign up_rx_ready_8 = 1'd0;
+  assign up_tx_pll_locked_8 = 1'd0;
+  assign up_tx_rst_done_8 = 1'd0;
+  assign up_tx_rdata_8 = 16'd0;
+  assign up_tx_ready_8 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 10) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (9),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1872,74 +2073,94 @@ module util_adxcvr (
     .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
-  i_xch_09 (
-    .qpll2ch_clk (qpll2ch_clk_08),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
-    .qpll2ch_locked (qpll2ch_locked_08),
-    .cpll_ref_clk (cpll_ref_clk_09),
-    .rx_p (rx_09_p),
-    .rx_n (rx_09_n),
-    .rx_out_clk (rx_out_clk_09),
-    .rx_clk (rx_clk_09),
-    .rx_charisk (rx_charisk_09),
-    .rx_disperr (rx_disperr_09),
-    .rx_notintable (rx_notintable_09),
-    .rx_data (rx_data_09),
-    .rx_calign (rx_calign_09),
-    .tx_p (tx_09_p),
-    .tx_n (tx_09_n),
-    .tx_out_clk (tx_out_clk_09),
-    .tx_clk (tx_clk_09),
-    .tx_charisk (tx_charisk_09),
-    .tx_data (tx_data_09),
+  i_xch_9 (
+    .qpll2ch_clk (qpll2ch_clk_8),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
+    .qpll2ch_locked (qpll2ch_locked_8),
+    .cpll_ref_clk (cpll_ref_clk_9),
+    .rx_p (rx_9_p),
+    .rx_n (rx_9_n),
+    .rx_out_clk (rx_out_clk_9),
+    .rx_clk (rx_clk_9),
+    .rx_charisk (rx_charisk_9),
+    .rx_disperr (rx_disperr_9),
+    .rx_notintable (rx_notintable_9),
+    .rx_data (rx_data_9),
+    .rx_calign (rx_calign_9),
+    .tx_p (tx_9_p),
+    .tx_n (tx_9_n),
+    .tx_out_clk (tx_out_clk_9),
+    .tx_clk (tx_clk_9),
+    .tx_charisk (tx_charisk_9),
+    .tx_data (tx_data_9),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_es_sel (up_es_sel_09),
-    .up_es_enb (up_es_enb_09),
-    .up_es_addr (up_es_addr_09),
-    .up_es_wr (up_es_wr_09),
-    .up_es_wdata (up_es_wdata_09),
-    .up_es_rdata (up_es_rdata_09),
-    .up_es_ready (up_es_ready_09),
-    .up_rx_pll_rst (up_rx_pll_rst_09),
-    .up_rx_pll_locked (up_rx_pll_locked_09),
-    .up_rx_rst (up_rx_rst_09),
-    .up_rx_user_ready (up_rx_user_ready_09),
-    .up_rx_rst_done (up_rx_rst_done_09),
-    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_09),
-    .up_rx_rate (up_rx_rate_09),
-    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_09),
-    .up_rx_out_clk_sel (up_rx_out_clk_sel_09),
-    .up_rx_sel (up_rx_sel_09),
-    .up_rx_enb (up_rx_enb_09),
-    .up_rx_addr (up_rx_addr_09),
-    .up_rx_wr (up_rx_wr_09),
-    .up_rx_wdata (up_rx_wdata_09),
-    .up_rx_rdata (up_rx_rdata_09),
-    .up_rx_ready (up_rx_ready_09),
-    .up_tx_pll_rst (up_tx_pll_rst_09),
-    .up_tx_pll_locked (up_tx_pll_locked_09),
-    .up_tx_rst (up_tx_rst_09),
-    .up_tx_user_ready (up_tx_user_ready_09),
-    .up_tx_rst_done (up_tx_rst_done_09),
-    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_09),
-    .up_tx_rate (up_tx_rate_09),
-    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_09),
-    .up_tx_out_clk_sel (up_tx_out_clk_sel_09),
-    .up_tx_sel (up_tx_sel_09),
-    .up_tx_enb (up_tx_enb_09),
-    .up_tx_addr (up_tx_addr_09),
-    .up_tx_wr (up_tx_wr_09),
-    .up_tx_wdata (up_tx_wdata_09),
-    .up_tx_rdata (up_tx_rdata_09),
-    .up_tx_ready (up_tx_ready_09));
+    .up_es_sel (up_es_sel_9),
+    .up_es_enb (up_es_enb_9),
+    .up_es_addr (up_es_addr_9),
+    .up_es_wr (up_es_wr_9),
+    .up_es_wdata (up_es_wdata_9),
+    .up_es_rdata (up_es_rdata_9),
+    .up_es_ready (up_es_ready_9),
+    .up_rx_pll_rst (up_rx_pll_rst_9),
+    .up_rx_pll_locked (up_rx_pll_locked_9),
+    .up_rx_rst (up_rx_rst_9),
+    .up_rx_user_ready (up_rx_user_ready_9),
+    .up_rx_rst_done (up_rx_rst_done_9),
+    .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_9),
+    .up_rx_rate (up_rx_rate_9),
+    .up_rx_sys_clk_sel (up_rx_sys_clk_sel_9),
+    .up_rx_out_clk_sel (up_rx_out_clk_sel_9),
+    .up_rx_sel (up_rx_sel_9),
+    .up_rx_enb (up_rx_enb_9),
+    .up_rx_addr (up_rx_addr_9),
+    .up_rx_wr (up_rx_wr_9),
+    .up_rx_wdata (up_rx_wdata_9),
+    .up_rx_rdata (up_rx_rdata_9),
+    .up_rx_ready (up_rx_ready_9),
+    .up_tx_pll_rst (up_tx_pll_rst_9),
+    .up_tx_pll_locked (up_tx_pll_locked_9),
+    .up_tx_rst (up_tx_rst_9),
+    .up_tx_user_ready (up_tx_user_ready_9),
+    .up_tx_rst_done (up_tx_rst_done_9),
+    .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_9),
+    .up_tx_rate (up_tx_rate_9),
+    .up_tx_sys_clk_sel (up_tx_sys_clk_sel_9),
+    .up_tx_out_clk_sel (up_tx_out_clk_sel_9),
+    .up_tx_sel (up_tx_sel_9),
+    .up_tx_enb (up_tx_enb_9),
+    .up_tx_addr (up_tx_addr_9),
+    .up_tx_wr (up_tx_wr_9),
+    .up_tx_wdata (up_tx_wdata_9),
+    .up_tx_rdata (up_tx_rdata_9),
+    .up_tx_ready (up_tx_ready_9));
+  end else begin
+  assign rx_out_clk_9 = 1'd0;
+  assign rx_charisk_9 = 4'd0;
+  assign rx_disperr_9 = 4'd0;
+  assign rx_notintable_9 = 4'd0;
+  assign rx_data_9 = 32'd0;
+  assign tx_9_p = 1'd0;
+  assign tx_9_n = 1'd0;
+  assign tx_out_clk_9 = 1'd0;
+  assign up_es_rdata_9 = 16'd0;
+  assign up_es_ready_9 = 1'd0;
+  assign up_rx_pll_locked_9 = 1'd0;
+  assign up_rx_rst_done_9 = 1'd0;
+  assign up_rx_rdata_9 = 16'd0;
+  assign up_rx_ready_9 = 1'd0;
+  assign up_tx_pll_locked_9 = 1'd0;
+  assign up_tx_rst_done_9 = 1'd0;
+  assign up_tx_rdata_9 = 16'd0;
+  assign up_tx_ready_9 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 11) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (10),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -1952,9 +2173,9 @@ module util_adxcvr (
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_10 (
-    .qpll2ch_clk (qpll2ch_clk_08),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
-    .qpll2ch_locked (qpll2ch_locked_08),
+    .qpll2ch_clk (qpll2ch_clk_8),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
+    .qpll2ch_locked (qpll2ch_locked_8),
     .cpll_ref_clk (cpll_ref_clk_10),
     .rx_p (rx_10_p),
     .rx_n (rx_10_n),
@@ -2012,13 +2233,33 @@ module util_adxcvr (
     .up_tx_wdata (up_tx_wdata_10),
     .up_tx_rdata (up_tx_rdata_10),
     .up_tx_ready (up_tx_ready_10));
+  end else begin
+  assign rx_out_clk_10 = 1'd0;
+  assign rx_charisk_10 = 4'd0;
+  assign rx_disperr_10 = 4'd0;
+  assign rx_notintable_10 = 4'd0;
+  assign rx_data_10 = 32'd0;
+  assign tx_10_p = 1'd0;
+  assign tx_10_n = 1'd0;
+  assign tx_out_clk_10 = 1'd0;
+  assign up_es_rdata_10 = 16'd0;
+  assign up_es_ready_10 = 1'd0;
+  assign up_rx_pll_locked_10 = 1'd0;
+  assign up_rx_rst_done_10 = 1'd0;
+  assign up_rx_rdata_10 = 16'd0;
+  assign up_rx_ready_10 = 1'd0;
+  assign up_tx_pll_locked_10 = 1'd0;
+  assign up_tx_rst_done_10 = 1'd0;
+  assign up_tx_rdata_10 = 16'd0;
+  assign up_tx_ready_10 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 12) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (11),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -2031,9 +2272,9 @@ module util_adxcvr (
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_11 (
-    .qpll2ch_clk (qpll2ch_clk_08),
-    .qpll2ch_ref_clk (qpll2ch_ref_clk_08),
-    .qpll2ch_locked (qpll2ch_locked_08),
+    .qpll2ch_clk (qpll2ch_clk_8),
+    .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
+    .qpll2ch_locked (qpll2ch_locked_8),
     .cpll_ref_clk (cpll_ref_clk_11),
     .rx_p (rx_11_p),
     .rx_n (rx_11_n),
@@ -2091,13 +2332,32 @@ module util_adxcvr (
     .up_tx_wdata (up_tx_wdata_11),
     .up_tx_rdata (up_tx_rdata_11),
     .up_tx_ready (up_tx_ready_11));
+  end else begin
+  assign rx_out_clk_11 = 1'd0;
+  assign rx_charisk_11 = 4'd0;
+  assign rx_disperr_11 = 4'd0;
+  assign rx_notintable_11 = 4'd0;
+  assign rx_data_11 = 32'd0;
+  assign tx_11_p = 1'd0;
+  assign tx_11_n = 1'd0;
+  assign tx_out_clk_11 = 1'd0;
+  assign up_es_rdata_11 = 16'd0;
+  assign up_es_ready_11 = 1'd0;
+  assign up_rx_pll_locked_11 = 1'd0;
+  assign up_rx_rst_done_11 = 1'd0;
+  assign up_rx_rdata_11 = 16'd0;
+  assign up_rx_ready_11 = 1'd0;
+  assign up_tx_pll_locked_11 = 1'd0;
+  assign up_tx_rst_done_11 = 1'd0;
+  assign up_tx_rdata_11 = 16'd0;
+  assign up_tx_ready_11 = 1'd0;
   end
   endgenerate
 
   generate
   if (NUM_OF_LANES >= 13) begin
   util_adxcvr_xcm #(
-    .XCVR_ID (n),
+    .XCVR_ID (12),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
@@ -2118,13 +2378,19 @@ module util_adxcvr (
     .up_cm_wdata (up_cm_wdata_12),
     .up_cm_rdata (up_cm_rdata_12),
     .up_cm_ready (up_cm_ready_12));
+  end else begin
+  assign qpll2ch_clk_12 = 1'd0;
+  assign qpll2ch_ref_clk_12 = 1'd0;
+  assign qpll2ch_locked_12 = 1'd0;
+  assign up_cm_rdata_12 = 16'd0;
+  assign up_cm_ready_12 = 1'd0;
   end
   endgenerate
 
   generate
   if (NUM_OF_LANES >= 13) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (12),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -2197,13 +2463,33 @@ module util_adxcvr (
     .up_tx_wdata (up_tx_wdata_12),
     .up_tx_rdata (up_tx_rdata_12),
     .up_tx_ready (up_tx_ready_12));
+  end else begin
+  assign rx_out_clk_12 = 1'd0;
+  assign rx_charisk_12 = 4'd0;
+  assign rx_disperr_12 = 4'd0;
+  assign rx_notintable_12 = 4'd0;
+  assign rx_data_12 = 32'd0;
+  assign tx_12_p = 1'd0;
+  assign tx_12_n = 1'd0;
+  assign tx_out_clk_12 = 1'd0;
+  assign up_es_rdata_12 = 16'd0;
+  assign up_es_ready_12 = 1'd0;
+  assign up_rx_pll_locked_12 = 1'd0;
+  assign up_rx_rst_done_12 = 1'd0;
+  assign up_rx_rdata_12 = 16'd0;
+  assign up_rx_ready_12 = 1'd0;
+  assign up_tx_pll_locked_12 = 1'd0;
+  assign up_tx_rst_done_12 = 1'd0;
+  assign up_tx_rdata_12 = 16'd0;
+  assign up_tx_ready_12 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 14) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (13),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -2276,13 +2562,33 @@ module util_adxcvr (
     .up_tx_wdata (up_tx_wdata_13),
     .up_tx_rdata (up_tx_rdata_13),
     .up_tx_ready (up_tx_ready_13));
+  end else begin
+  assign rx_out_clk_13 = 1'd0;
+  assign rx_charisk_13 = 4'd0;
+  assign rx_disperr_13 = 4'd0;
+  assign rx_notintable_13 = 4'd0;
+  assign rx_data_13 = 32'd0;
+  assign tx_13_p = 1'd0;
+  assign tx_13_n = 1'd0;
+  assign tx_out_clk_13 = 1'd0;
+  assign up_es_rdata_13 = 16'd0;
+  assign up_es_ready_13 = 1'd0;
+  assign up_rx_pll_locked_13 = 1'd0;
+  assign up_rx_rst_done_13 = 1'd0;
+  assign up_rx_rdata_13 = 16'd0;
+  assign up_rx_ready_13 = 1'd0;
+  assign up_tx_pll_locked_13 = 1'd0;
+  assign up_tx_rst_done_13 = 1'd0;
+  assign up_tx_rdata_13 = 16'd0;
+  assign up_tx_ready_13 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 15) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (14),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -2355,13 +2661,33 @@ module util_adxcvr (
     .up_tx_wdata (up_tx_wdata_14),
     .up_tx_rdata (up_tx_rdata_14),
     .up_tx_ready (up_tx_ready_14));
+  end else begin
+  assign rx_out_clk_14 = 1'd0;
+  assign rx_charisk_14 = 4'd0;
+  assign rx_disperr_14 = 4'd0;
+  assign rx_notintable_14 = 4'd0;
+  assign rx_data_14 = 32'd0;
+  assign tx_14_p = 1'd0;
+  assign tx_14_n = 1'd0;
+  assign tx_out_clk_14 = 1'd0;
+  assign up_es_rdata_14 = 16'd0;
+  assign up_es_ready_14 = 1'd0;
+  assign up_rx_pll_locked_14 = 1'd0;
+  assign up_rx_rst_done_14 = 1'd0;
+  assign up_rx_rdata_14 = 16'd0;
+  assign up_rx_ready_14 = 1'd0;
+  assign up_tx_pll_locked_14 = 1'd0;
+  assign up_tx_rst_done_14 = 1'd0;
+  assign up_tx_rdata_14 = 16'd0;
+  assign up_tx_ready_14 = 1'd0;
   end
   endgenerate
 
+
   generate
   if (NUM_OF_LANES >= 16) begin
   util_adxcvr_xch #(
-    .XCVR_ID (n),
+    .XCVR_ID (15),
     .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
@@ -2434,10 +2760,29 @@ module util_adxcvr (
     .up_tx_wdata (up_tx_wdata_15),
     .up_tx_rdata (up_tx_rdata_15),
     .up_tx_ready (up_tx_ready_15));
+  end else begin
+  assign rx_out_clk_15 = 1'd0;
+  assign rx_charisk_15 = 4'd0;
+  assign rx_disperr_15 = 4'd0;
+  assign rx_notintable_15 = 4'd0;
+  assign rx_data_15 = 32'd0;
+  assign tx_15_p = 1'd0;
+  assign tx_15_n = 1'd0;
+  assign tx_out_clk_15 = 1'd0;
+  assign up_es_rdata_15 = 16'd0;
+  assign up_es_ready_15 = 1'd0;
+  assign up_rx_pll_locked_15 = 1'd0;
+  assign up_rx_rst_done_15 = 1'd0;
+  assign up_rx_rdata_15 = 16'd0;
+  assign up_rx_ready_15 = 1'd0;
+  assign up_tx_pll_locked_15 = 1'd0;
+  assign up_tx_rst_done_15 = 1'd0;
+  assign up_tx_rdata_15 = 16'd0;
+  assign up_tx_ready_15 = 1'd0;
   end
   endgenerate
 
-endmodule     
+endmodule
 
 // ***************************************************************************
 // ***************************************************************************
diff --git a/library/util_adxcvr/util_adxcvr_ip.tcl b/library/util_adxcvr/util_adxcvr_ip.tcl
index 03b1b119f..0162c5f78 100644
--- a/library/util_adxcvr/util_adxcvr_ip.tcl
+++ b/library/util_adxcvr/util_adxcvr_ip.tcl
@@ -1,16 +1,615 @@
-# ip
+## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY!
 
 source ../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create util_adxcvr
 adi_ip_files util_adxcvr [list \
-  "util_adxcvr_intf.svh" \
-  "util_adxcvr_xcm.sv" \
-  "util_adxcvr_xch.sv" \
-  "util_adxcvr.sv" ]
+  "util_adxcvr_xcm.v" \
+  "util_adxcvr_xch.v" \
+  "util_adxcvr.v" ]
 
 adi_ip_properties_lite util_adxcvr
 
+ipx::remove_all_bus_interface [ipx::current_core]
+
+set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
+
+for {set n 0} {$n < 16} {incr n} {
+
+  if {($n%4) == 0} {
+  adi_if_infer_bus ADI:user:if_xcvr_cm slave up_cm_${n} [list \
+    "sel                 up_cm_sel_${n}         "\
+    "enb                 up_cm_enb_${n}         "\
+    "addr                up_cm_addr_${n}        "\
+    "wr                  up_cm_wr_${n}          "\
+    "wdata               up_cm_wdata_${n}       "\
+    "rdata               up_cm_rdata_${n}       "\
+    "ready               up_cm_ready_${n}       "]
+  }
+
+  adi_if_infer_bus ADI:user:if_xcvr_cm slave up_es_${n} [list \
+    "sel                 up_es_sel_${n}         "\
+    "enb                 up_es_enb_${n}         "\
+    "addr                up_es_addr_${n}        "\
+    "wr                  up_es_wr_${n}          "\
+    "wdata               up_es_wdata_${n}       "\
+    "rdata               up_es_rdata_${n}       "\
+    "ready               up_es_ready_${n}       "]
+
+  adi_if_infer_bus ADI:user:if_xcvr_ch slave up_rx_${n} [list \
+    "pll_rst             up_rx_pll_rst_${n}     "\
+    "pll_locked          up_rx_pll_locked_${n}  "\
+    "rst                 up_rx_rst_${n}         "\
+    "user_ready          up_rx_user_ready_${n}  "\
+    "rst_done            up_rx_rst_done_${n}    "\
+    "lpm_dfe_n           up_rx_lpm_dfe_n_${n}   "\
+    "rate                up_rx_rate_${n}        "\
+    "sys_clk_sel         up_rx_sys_clk_sel_${n} "\
+    "out_clk_sel         up_rx_out_clk_sel_${n} "\
+    "sel                 up_rx_sel_${n}         "\
+    "enb                 up_rx_enb_${n}         "\
+    "addr                up_rx_addr_${n}        "\
+    "wr                  up_rx_wr_${n}          "\
+    "wdata               up_rx_wdata_${n}       "\
+    "rdata               up_rx_rdata_${n}       "\
+    "ready               up_rx_ready_${n}       "]
+
+  adi_if_infer_bus ADI:user:if_xcvr_ch slave up_tx_${n} [list \
+    "pll_rst             up_tx_pll_rst_${n}     "\
+    "pll_locked          up_tx_pll_locked_${n}  "\
+    "rst                 up_tx_rst_${n}         "\
+    "user_ready          up_tx_user_ready_${n}  "\
+    "rst_done            up_tx_rst_done_${n}    "\
+    "lpm_dfe_n           up_tx_lpm_dfe_n_${n}   "\
+    "rate                up_tx_rate_${n}        "\
+    "sys_clk_sel         up_tx_sys_clk_sel_${n} "\
+    "out_clk_sel         up_tx_out_clk_sel_${n} "\
+    "sel                 up_tx_sel_${n}         "\
+    "enb                 up_tx_enb_${n}         "\
+    "addr                up_tx_addr_${n}        "\
+    "wr                  up_tx_wr_${n}          "\
+    "wdata               up_tx_wdata_${n}       "\
+    "rdata               up_tx_rdata_${n}       "\
+    "ready               up_tx_ready_${n}       "]
+
+  ipx::add_bus_interface rx_${n} [ipx::current_core]
+  set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \
+    [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
+  set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \
+    [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
+  set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
+  ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
+  set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \
+    [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
+  ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
+  set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \
+    [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
+  ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
+  set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \
+    [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
+  ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
+  set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \
+    [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
+
+  ipx::add_bus_interface tx_${n} [ipx::current_core]
+  set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \
+    [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
+  set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \
+    [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
+  set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
+  ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
+  set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \
+    [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
+  ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
+  set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \
+    [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
+
+}
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
+  [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
+  [ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
+  [ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
+  [ipx::get_ports rx_*0* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
+  [ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
+  [ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
+  [ipx::get_ports tx_*0* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0))} \
+  [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0))} \
+  [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0))} \
+  [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
+  [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
+  [ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
+  [ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
+  [ipx::get_ports rx_*1* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
+  [ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
+  [ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
+  [ipx::get_ports tx_*1* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1))} \
+  [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
+  [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
+  [ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
+  [ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
+  [ipx::get_ports rx_*2* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
+  [ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
+  [ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
+  [ipx::get_ports tx_*2* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2))} \
+  [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
+  [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
+  [ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
+  [ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
+  [ipx::get_ports rx_*3* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
+  [ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
+  [ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
+  [ipx::get_ports tx_*3* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3))} \
+  [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
+  [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
+  [ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
+  [ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
+  [ipx::get_ports rx_*4* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
+  [ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
+  [ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
+  [ipx::get_ports tx_*4* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4))} \
+  [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4))} \
+  [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4))} \
+  [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
+  [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
+  [ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
+  [ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
+  [ipx::get_ports rx_*5* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
+  [ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
+  [ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
+  [ipx::get_ports tx_*5* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5))} \
+  [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
+  [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
+  [ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
+  [ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
+  [ipx::get_ports rx_*6* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
+  [ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
+  [ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
+  [ipx::get_ports tx_*6* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6))} \
+  [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
+  [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
+  [ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
+  [ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
+  [ipx::get_ports rx_*7* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
+  [ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
+  [ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
+  [ipx::get_ports tx_*7* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7))} \
+  [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
+  [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
+  [ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
+  [ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
+  [ipx::get_ports rx_*8* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
+  [ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
+  [ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
+  [ipx::get_ports tx_*8* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8))} \
+  [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8))} \
+  [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8))} \
+  [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
+  [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
+  [ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
+  [ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
+  [ipx::get_ports rx_*9* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
+  [ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
+  [ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
+  [ipx::get_ports tx_*9* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9))} \
+  [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
+  [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
+  [ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
+  [ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
+  [ipx::get_ports rx_*10* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
+  [ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
+  [ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
+  [ipx::get_ports tx_*10* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10))} \
+  [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
+  [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
+  [ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
+  [ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
+  [ipx::get_ports rx_*11* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
+  [ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
+  [ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
+  [ipx::get_ports tx_*11* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11))} \
+  [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
+  [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
+  [ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
+  [ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
+  [ipx::get_ports rx_*12* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
+  [ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
+  [ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
+  [ipx::get_ports tx_*12* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12))} \
+  [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12))} \
+  [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12))} \
+  [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
+  [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
+  [ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
+  [ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
+  [ipx::get_ports rx_*13* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
+  [ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
+  [ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
+  [ipx::get_ports tx_*13* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13))} \
+  [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
+  [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
+  [ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
+  [ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
+  [ipx::get_ports rx_*14* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
+  [ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
+  [ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
+  [ipx::get_ports tx_*14* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14))} \
+  [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
+  [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
+  [ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
+  [ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
+  [ipx::get_ports rx_*15* -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
+  [ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
+  [ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
+  [ipx::get_ports tx_*15* -of_objects [ipx::current_core]] 
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15)) or \
+  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15))} \
+  [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/util_adxcvr/util_adxcvr_xch.v b/library/util_adxcvr/util_adxcvr_xch.v
index 2734e04e4..0b19f9d6a 100644
--- a/library/util_adxcvr/util_adxcvr_xch.v
+++ b/library/util_adxcvr/util_adxcvr_xch.v
@@ -39,68 +39,85 @@
 
 module util_adxcvr_xch (
 
-  // rst and clocks
+  // pll interface
 
-  input           ref_clk,
-  input           pll_rst,
-
-  input           qpll_clk,
-  input           qpll_ref_clk,
-  input           qpll_locked,
+  input           qpll2ch_clk,
+  input           qpll2ch_ref_clk,
+  input           qpll2ch_locked,
+  input           cpll_ref_clk,
 
   // receive
 
   input           rx_p,
   input           rx_n,
 
-  input           rx_rst,
-  input           rx_clk,
-  input           rx_lpm_dfe_n,
-  input   [ 2:0]  rx_rate,
-  input   [ 1:0]  rx_sys_clk_sel,
-  input   [ 2:0]  rx_out_clk_sel,
   output          rx_out_clk,
-  output          rx_rst_done,
-  output          rx_pll_locked,
-  input           rx_user_ready,
-  output  [ 3:0]  rx_gt_charisk,
-  output  [ 3:0]  rx_gt_disperr,
-  output  [ 3:0]  rx_gt_notintable,
-  output  [31:0]  rx_gt_data,
-  input           rx_gt_calign,
+  input           rx_clk,
+  output  [ 3:0]  rx_charisk,
+  output  [ 3:0]  rx_disperr,
+  output  [ 3:0]  rx_notintable,
+  output  [31:0]  rx_data,
+  input           rx_calign,
 
   // transmit
 
   output          tx_p,
   output          tx_n,
 
-  input           tx_rst,
-  input           tx_clk,
-  input   [ 2:0]  tx_rate,
-  input   [ 1:0]  tx_sys_clk_sel,
-  input   [ 2:0]  tx_out_clk_sel,
   output          tx_out_clk,
-  output          tx_rst_done,
-  output          tx_pll_locked,
-  input           tx_user_ready,
-  input   [ 3:0]  tx_gt_charisk,
-  input   [31:0]  tx_gt_data,
+  input           tx_clk,
+  input   [ 3:0]  tx_charisk,
+  input   [31:0]  tx_data,
 
-  // drp interface
+  // up interface
 
   input           up_rstn,
   input           up_clk,
-  input   [ 7:0]  up_drp_sel,
-  input           up_drp_enb,
-  input   [11:0]  up_drp_addr,
-  input           up_drp_wr,
-  input   [15:0]  up_drp_wdata,
-  output  [15:0]  up_drp_rdata,
-  output          up_drp_ready);
+  input   [ 7:0]  up_es_sel,
+  input           up_es_enb,
+  input   [11:0]  up_es_addr,
+  input           up_es_wr,
+  input   [15:0]  up_es_wdata,
+  output  [15:0]  up_es_rdata,
+  output          up_es_ready,
+  input           up_rx_pll_rst,
+  output          up_rx_pll_locked,
+  input           up_rx_rst,
+  input           up_rx_user_ready,
+  output          up_rx_rst_done,
+  input           up_rx_lpm_dfe_n,
+  input   [ 2:0]  up_rx_rate,
+  input   [ 1:0]  up_rx_sys_clk_sel,
+  input   [ 2:0]  up_rx_out_clk_sel,
+  input   [ 7:0]  up_rx_sel,
+  input           up_rx_enb,
+  input   [11:0]  up_rx_addr,
+  input           up_rx_wr,
+  input   [15:0]  up_rx_wdata,
+  output  [15:0]  up_rx_rdata,
+  output          up_rx_ready,
+  input           up_tx_pll_rst,
+  output          up_tx_pll_locked,
+  input           up_tx_rst,
+  input           up_tx_user_ready,
+  output          up_tx_rst_done,
+  input           up_tx_lpm_dfe_n,
+  input   [ 2:0]  up_tx_rate,
+  input   [ 1:0]  up_tx_sys_clk_sel,
+  input   [ 2:0]  up_tx_out_clk_sel,
+  input   [ 7:0]  up_tx_sel,
+  input           up_tx_enb,
+  input   [11:0]  up_tx_addr,
+  input           up_tx_wr,
+  input   [15:0]  up_tx_wdata,
+  output  [15:0]  up_tx_rdata,
+  output          up_tx_ready);
 
   // parameters
 
+  parameter   integer XCVR_ID = 0;
   parameter   integer GTH_OR_GTX_N = 0;
+  parameter   integer CPLL_TX_OR_RX_N = 0;
   parameter   integer CPLL_FBDIV = 2;
   parameter   integer RX_OUT_DIV = 1;
   parameter   integer RX_CLK25_DIV = 10;
@@ -113,60 +130,127 @@ module util_adxcvr_xch (
 
   // internal registers
 
-  reg             up_drp_enb_int = 'd0;
-  reg     [11:0]  up_drp_addr_int = 'd0;
-  reg             up_drp_wr_int = 'd0;
-  reg     [15:0]  up_drp_wdata_int = 'd0;
-  reg     [15:0]  up_drp_rdata_int = 'd0;
-  reg             up_drp_ready_int = 'd0;
+  reg     [15:0]  up_es_rdata_int = 'd0;
+  reg             up_es_ready_int = 'd0;
+  reg     [15:0]  up_rx_rdata_int = 'd0;
+  reg             up_rx_ready_int = 'd0;
+  reg     [15:0]  up_tx_rdata_int = 'd0;
+  reg             up_tx_ready_int = 'd0;
+  reg     [ 2:0]  up_sel_int = 'd0;
+  reg             up_enb_int = 'd0;
+  reg     [11:0]  up_addr_int = 'd0;
+  reg             up_wr_int = 'd0;
+  reg     [15:0]  up_wdata_int = 'd0;
 
   // internal signals
 
-  wire    [ 3:0]  rx_charisk_open_s;
-  wire    [ 3:0]  rx_disperr_open_s;
-  wire    [ 3:0]  rx_notintable_open_s;
-  wire    [31:0]  rx_data_open_s;
+  wire            up_cpll_rst;
+  wire            up_es_enb_s;
+  wire            up_rx_enb_s;
+  wire            up_tx_enb_s;
+  wire    [15:0]  up_rdata_s;
+  wire            up_ready_s;
   wire    [ 1:0]  rx_sys_clk_sel_s;
   wire    [ 1:0]  tx_sys_clk_sel_s;
   wire    [ 1:0]  rx_pll_clk_sel_s;
   wire    [ 1:0]  tx_pll_clk_sel_s;
+  wire    [ 3:0]  rx_charisk_open_s;
+  wire    [ 3:0]  rx_disperr_open_s;
+  wire    [ 3:0]  rx_notintable_open_s;
+  wire    [31:0]  rx_data_open_s;
   wire            cpll_locked_s;
-  wire    [15:0]  up_drp_rdata_s;
-  wire            up_drp_ready_s;
 
-  // pll locked
+  // pll
 
-  assign rx_pll_locked = (rx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
-  assign tx_pll_locked = (tx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
+  assign up_cpll_rst = (CPLL_TX_OR_RX_N == 1) ? up_tx_pll_rst : up_rx_pll_rst;
+  assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s;
+  assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s;
 
   // drp access
 
-  assign up_drp_rdata = up_drp_rdata_int;
-  assign up_drp_ready = up_drp_ready_int;
+  assign up_es_rdata = up_es_rdata_int;
+  assign up_es_ready = up_es_ready_int;
+  assign up_rx_rdata = up_rx_rdata_int;
+  assign up_rx_ready = up_rx_ready_int;
+  assign up_tx_rdata = up_tx_rdata_int;
+  assign up_tx_ready = up_tx_ready_int;
 
-  always @(posedge up_clk or negedge up_rstn) begin
+  assign up_es_enb_s = ((up_es_sel == XCVR_ID) ||
+    (up_es_sel == 8'hff)) ? up_es_enb : 1'b0;
+
+  assign up_rx_enb_s = ((up_rx_sel == XCVR_ID) ||
+    (up_rx_sel == 8'hff)) ? up_rx_enb : 1'b0;
+
+  assign up_tx_enb_s = ((up_tx_sel == XCVR_ID) ||
+    (up_tx_sel == 8'hff)) ? up_tx_enb : 1'b0;
+
+  always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
-        up_drp_enb_int <= 1'd0;
-        up_drp_addr_int <= 12'd0;
-        up_drp_wr_int <= 1'd0;
-        up_drp_wdata_int <= 15'd0;
-        up_drp_rdata_int <= 15'd0;
-        up_drp_ready_int <= 1'd0;
+      up_es_rdata_int <= 15'd0;
+      up_es_ready_int <= 1'd0;
+      up_rx_rdata_int <= 15'd0;
+      up_rx_ready_int <= 1'd0;
+      up_tx_rdata_int <= 15'd0;
+      up_tx_ready_int <= 1'd0;
+      up_sel_int <= 3'd0;
+      up_enb_int <= 1'd0;
+      up_addr_int <= 12'd0;
+      up_wr_int <= 1'd0;
+      up_wdata_int <= 15'd0;
     end else begin
-      if ((up_drp_sel == XCVR_ID) || (up_drp_sel == 8'hff)) begin
-        up_drp_enb_int <= up_drp_enb;
-        up_drp_addr_int <= up_drp_addr;
-        up_drp_wr_int <= up_drp_wr;
-        up_drp_wdata_int <= up_drp_wdata;
-        up_drp_rdata_int <= up_drp_rdata_s;
-        up_drp_ready_int <= up_drp_ready_s;
+      if (up_sel_int == 3'b100) begin
+        up_es_rdata_int <= up_rdata_s;
+        up_es_ready_int <= up_ready_s;
       end else begin
-        up_drp_enb_int <= 1'd0;
-        up_drp_addr_int <= 12'd0;
-        up_drp_wr_int <= 1'd0;
-        up_drp_wdata_int <= 15'd0;
-        up_drp_rdata_int <= 15'd0;
-        up_drp_ready_int <= 1'd0;
+        up_es_rdata_int <= 15'd0;
+        up_es_ready_int <= 1'd0;
+      end
+      if (up_sel_int == 3'b101) begin
+        up_rx_rdata_int <= up_rdata_s;
+        up_rx_ready_int <= up_ready_s;
+      end else begin
+        up_rx_rdata_int <= 15'd0;
+        up_rx_ready_int <= 1'd0;
+      end
+      if (up_sel_int == 3'b110) begin
+        up_tx_rdata_int <= up_rdata_s;
+        up_tx_ready_int <= up_ready_s;
+      end else begin
+        up_tx_rdata_int <= 15'd0;
+        up_tx_ready_int <= 1'd0;
+      end
+      if (up_sel_int[2] == 1'b1) begin
+        if (up_ready_s == 1'b1) begin
+          up_sel_int <= 3'b000;
+        end
+        up_enb_int <= 1'b0;
+        up_addr_int <= 12'd0;
+        up_wr_int <= 1'd0;
+        up_wdata_int <= 15'd0;
+      end else if (up_es_enb_s == 1'b1) begin
+        up_sel_int <= 3'b100;
+        up_enb_int <= 1'b1;
+        up_addr_int <= up_es_addr;
+        up_wr_int <= up_es_wr;
+        up_wdata_int <= up_es_wdata;
+      end else if (up_rx_enb_s == 1'b1) begin
+        up_sel_int <= 3'b101;
+        up_enb_int <= 1'b1;
+        up_addr_int <= up_rx_addr;
+        up_wr_int <= up_rx_wr;
+        up_wdata_int <= up_rx_wdata;
+      end else if (up_tx_enb_s == 1'b1) begin
+        up_sel_int <= 3'b110;
+        up_enb_int <= 1'b1;
+        up_addr_int <= up_tx_addr;
+        up_wr_int <= up_tx_wr;
+        up_wdata_int <= up_tx_wdata;
+      end else begin
+        up_sel_int <= 3'b000;
+        up_enb_int <= 1'b0;
+        up_addr_int <= 12'd0;
+        up_wr_int <= 1'd0;
+        up_wdata_int <= 15'd0;
       end
     end
   end
@@ -175,8 +259,8 @@ module util_adxcvr_xch (
 
   generate
   if (GTH_OR_GTX_N == 0) begin
-  assign rx_sys_clk_sel_s = rx_sys_clk_sel;
-  assign tx_sys_clk_sel_s = tx_sys_clk_sel;
+  assign rx_sys_clk_sel_s = up_rx_sys_clk_sel;
+  assign tx_sys_clk_sel_s = up_tx_sys_clk_sel;
   assign rx_pll_clk_sel_s = 2'd0;
   assign tx_pll_clk_sel_s = 2'd0;
   end
@@ -392,7 +476,7 @@ module util_adxcvr_xch (
     .CPLLPD (1'b0),
     .CPLLREFCLKLOST (),
     .CPLLREFCLKSEL (3'b001),
-    .CPLLRESET (pll_rst),
+    .CPLLRESET (up_cpll_rst),
     .GTRSVD (16'b0000000000000000),
     .PCSRSVDIN (16'b0000000000000000),
     .PCSRSVDIN2 (5'b00000),
@@ -404,33 +488,33 @@ module util_adxcvr_xch (
     .GTGREFCLK (1'd0),
     .GTNORTHREFCLK0 (1'd0),
     .GTNORTHREFCLK1 (1'd0),
-    .GTREFCLK0 (ref_clk),
+    .GTREFCLK0 (cpll_ref_clk),
     .GTREFCLK1 (1'd0),
     .GTSOUTHREFCLK0 (1'd0),
     .GTSOUTHREFCLK1 (1'd0),
-    .DRPADDR (up_drp_addr_int[8:0]),
+    .DRPADDR (up_addr_int[8:0]),
     .DRPCLK (up_clk),
-    .DRPDI (up_drp_wdata_int),
-    .DRPDO (up_drp_rdata_s),
-    .DRPEN (up_drp_enb_int),
-    .DRPRDY (up_drp_ready_s),
-    .DRPWE (up_drp_wr_int),
+    .DRPDI (up_wdata_int),
+    .DRPDO (up_rdata_s),
+    .DRPEN (up_enb_int),
+    .DRPRDY (up_ready_s),
+    .DRPWE (up_wr_int),
     .GTREFCLKMONITOR (),
-    .QPLLCLK (qpll_clk),
-    .QPLLREFCLK (qpll_ref_clk),
+    .QPLLCLK (qpll2ch_clk),
+    .QPLLREFCLK (qpll2ch_ref_clk),
     .RXSYSCLKSEL (rx_sys_clk_sel_s),
     .TXSYSCLKSEL (tx_sys_clk_sel_s),
     .DMONITOROUT (),
     .TX8B10BEN (1'd1),
     .LOOPBACK (3'd0),
     .PHYSTATUS (),
-    .RXRATE (rx_rate),
+    .RXRATE (up_rx_rate),
     .RXVALID (),
     .RXPD (2'b00),
     .TXPD (2'b00),
     .SETERRSTATUS (1'd0),
     .EYESCANRESET (1'd0),
-    .RXUSERRDY (rx_user_ready),
+    .RXUSERRDY (up_rx_user_ready),
     .EYESCANDATAERROR (),
     .EYESCANMODE (1'd0),
     .EYESCANTRIGGER (1'd0),
@@ -444,15 +528,15 @@ module util_adxcvr_xch (
     .RX8B10BEN (1'd1),
     .RXUSRCLK (rx_clk),
     .RXUSRCLK2 (rx_clk),
-    .RXDATA ({rx_data_open_s, rx_gt_data}),
+    .RXDATA ({rx_data_open_s, rx_data}),
     .RXPRBSERR (),
     .RXPRBSSEL (3'd0),
     .RXPRBSCNTRESET (1'd0),
     .RXDFEXYDEN (1'd0),
     .RXDFEXYDHOLD (1'd0),
     .RXDFEXYDOVRDEN (1'd0),
-    .RXDISPERR ({rx_disperr_open_s, rx_gt_disperr}),
-    .RXNOTINTABLE ({rx_notintable_open_s, rx_gt_notintable}),
+    .RXDISPERR ({rx_disperr_open_s, rx_disperr}),
+    .RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
     .GTXRXP (rx_p),
     .GTXRXN (rx_n),
     .RXBUFRESET (1'd0),
@@ -476,8 +560,8 @@ module util_adxcvr_xch (
     .RXBYTEREALIGN (),
     .RXCOMMADET (),
     .RXCOMMADETEN (1'd1),
-    .RXMCOMMAALIGNEN (rx_gt_calign),
-    .RXPCOMMAALIGNEN (rx_gt_calign),
+    .RXMCOMMAALIGNEN (rx_calign),
+    .RXPCOMMAALIGNEN (rx_calign),
     .RXCHANBONDSEQ (),
     .RXCHBONDEN (1'd0),
     .RXCHBONDLEVEL (3'd0),
@@ -517,17 +601,17 @@ module util_adxcvr_xch (
     .RXOUTCLK (rx_out_clk),
     .RXOUTCLKFABRIC (),
     .RXOUTCLKPCS (),
-    .RXOUTCLKSEL (rx_out_clk_sel),
+    .RXOUTCLKSEL (up_rx_out_clk_sel),
     .RXDATAVALID (),
     .RXHEADER (),
     .RXHEADERVALID (),
     .RXSTARTOFSEQ (),
     .RXGEARBOXSLIP (1'd0),
-    .GTRXRESET (rx_rst),
+    .GTRXRESET (up_rx_rst),
     .RXOOBRESET (1'd0),
     .RXPCSRESET (1'd0),
     .RXPMARESET (1'd0),
-    .RXLPMEN (rx_lpm_dfe_n),
+    .RXLPMEN (up_rx_lpm_dfe_n),
     .RXCOMSASDET (),
     .RXCOMWAKEDET (),
     .RXCOMINITDET (),
@@ -536,9 +620,9 @@ module util_adxcvr_xch (
     .RXPOLARITY (1'd0),
     .RXSLIDE (1'd0),
     .RXCHARISCOMMA (),
-    .RXCHARISK ({rx_charisk_open_s, rx_gt_charisk}),
+    .RXCHARISK ({rx_charisk_open_s, rx_charisk}),
     .RXCHBONDI (5'd0),
-    .RXRESETDONE (rx_rst_done),
+    .RXRESETDONE (up_rx_rst_done),
     .RXQPIEN (1'd0),
     .RXQPISENN (),
     .RXQPISENP (),
@@ -551,9 +635,9 @@ module util_adxcvr_xch (
     .TXQPISTRONGPDOWN (1'd0),
     .TXQPIWEAKPUP (1'd0),
     .CFGRESET (1'd0),
-    .GTTXRESET (tx_rst),
+    .GTTXRESET (up_tx_rst),
     .PCSRSVDOUT (),
-    .TXUSERRDY (tx_user_ready),
+    .TXUSERRDY (up_tx_user_ready),
     .GTRESETSEL (1'd0),
     .RESETOVRD (1'd0),
     .TXCHARDISPMODE (8'd0),
@@ -562,7 +646,7 @@ module util_adxcvr_xch (
     .TXUSRCLK2 (tx_clk),
     .TXELECIDLE (1'd0),
     .TXMARGIN (3'd0),
-    .TXRATE (tx_rate),
+    .TXRATE (up_tx_rate),
     .TXSWING (1'd0),
     .TXPRBSFORCEERR (1'd0),
     .TXDLYBYPASS (1'd1),
@@ -588,22 +672,22 @@ module util_adxcvr_xch (
     .TXINHIBIT (1'd0),
     .TXMAINCURSOR (7'b0000000),
     .TXPISOPD (1'd0),
-    .TXDATA ({32'd0, tx_gt_data}),
+    .TXDATA ({32'd0, tx_data}),
     .GTXTXP (tx_p),
     .GTXTXN (tx_n),
     .TXOUTCLK (tx_out_clk),
     .TXOUTCLKFABRIC (),
     .TXOUTCLKPCS (),
-    .TXOUTCLKSEL (tx_out_clk_sel),
+    .TXOUTCLKSEL (up_tx_out_clk_sel),
     .TXRATEDONE (),
-    .TXCHARISK ({4'd0, tx_gt_charisk}),
+    .TXCHARISK ({4'd0, tx_charisk}),
     .TXGEARBOXREADY (),
     .TXHEADER (3'd0),
     .TXSEQUENCE (7'd0),
     .TXSTARTSEQ (1'd0),
     .TXPCSRESET (1'd0),
     .TXPMARESET (1'd0),
-    .TXRESETDONE (tx_rst_done),
+    .TXRESETDONE (up_tx_rst_done),
     .TXCOMFINISH (),
     .TXCOMINIT (1'd0),
     .TXCOMSAS (1'd0),
@@ -620,10 +704,10 @@ module util_adxcvr_xch (
 
   generate
   if (GTH_OR_GTX_N == 1) begin
-  assign rx_sys_clk_sel_s = (rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
-  assign tx_sys_clk_sel_s = (tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
-  assign rx_pll_clk_sel_s = rx_sys_clk_sel;
-  assign tx_pll_clk_sel_s = tx_sys_clk_sel;
+  assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
+  assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
+  assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
+  assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
   end
   endgenerate
 
@@ -1025,14 +1109,14 @@ module util_adxcvr_xch (
     .CPLLLOCKEN (1'd1),
     .CPLLPD (1'b0),
     .CPLLREFCLKSEL (3'b001),
-    .CPLLRESET (pll_rst),
+    .CPLLRESET (up_cpll_rst),
     .DMONFIFORESET (1'd0),
     .DMONITORCLK (1'd0),
-    .DRPADDR (up_drp_addr_int[8:0]),
+    .DRPADDR (up_addr_int[8:0]),
     .DRPCLK (up_clk),
-    .DRPDI (up_drp_wdata_int),
-    .DRPEN (up_drp_enb_int),
-    .DRPWE (up_drp_wr_int),
+    .DRPDI (up_wdata_int),
+    .DRPEN (up_enb_int),
+    .DRPWE (up_wr_int),
     .EVODDPHICALDONE (1'd0),
     .EVODDPHICALSTART (1'd0),
     .EVODDPHIDRDEN (1'd0),
@@ -1047,14 +1131,14 @@ module util_adxcvr_xch (
     .GTHRXP (rx_p),
     .GTNORTHREFCLK0 (1'd0),
     .GTNORTHREFCLK1 (1'd0),
-    .GTREFCLK0 (ref_clk),
+    .GTREFCLK0 (cpll_ref_clk),
     .GTREFCLK1 (1'd0),
     .GTRESETSEL (1'd0),
     .GTRSVD (15'd0),
-    .GTRXRESET (rx_rst),
+    .GTRXRESET (up_rx_rst),
     .GTSOUTHREFCLK0 (1'd0),
     .GTSOUTHREFCLK1 (1'd0),
-    .GTTXRESET (tx_rst),
+    .GTTXRESET (up_tx_rst),
     .LOOPBACK (3'd0),
     .LPBKRXTXSEREN (1'd0),
     .LPBKTXRXSEREN (1'd0),
@@ -1065,8 +1149,8 @@ module util_adxcvr_xch (
     .PCSRSVDIN (16'd0),
     .PCSRSVDIN2 (5'd0),
     .PMARSVDIN (5'd0),
-    .QPLL0CLK (qpll_clk),
-    .QPLL0REFCLK (qpll_ref_clk),
+    .QPLL0CLK (qpll2ch_clk),
+    .QPLL0REFCLK (qpll2ch_ref_clk),
     .QPLL1CLK (1'd0),
     .QPLL1REFCLK (1'd0),
     .RESETOVRD (1'd0),
@@ -1130,7 +1214,7 @@ module util_adxcvr_xch (
     .RXELECIDLEMODE (2'b11),
     .RXGEARBOXSLIP (1'd0),
     .RXLATCLK (1'd0),
-    .RXLPMEN (rx_lpm_dfe_n),
+    .RXLPMEN (up_rx_lpm_dfe_n),
     .RXLPMGCHOLD (1'd0),
     .RXLPMGCOVRDEN (1'd0),
     .RXLPMHFHOLD (1'd0),
@@ -1139,7 +1223,7 @@ module util_adxcvr_xch (
     .RXLPMLFKLOVRDEN (1'd0),
     .RXLPMOSHOLD (1'd0),
     .RXLPMOSOVRDEN (1'd0),
-    .RXMCOMMAALIGNEN (rx_gt_calign),
+    .RXMCOMMAALIGNEN (rx_calign),
     .RXMONITORSEL (2'd0),
     .RXOOBRESET (1'd0),
     .RXOSCALRESET (1'd0),
@@ -1151,8 +1235,8 @@ module util_adxcvr_xch (
     .RXOSINTSTROBE (1'd0),
     .RXOSINTTESTOVRDEN (1'd0),
     .RXOSOVRDEN (1'd0),
-    .RXOUTCLKSEL (rx_out_clk_sel),
-    .RXPCOMMAALIGNEN (rx_gt_calign),
+    .RXOUTCLKSEL (up_rx_out_clk_sel),
+    .RXPCOMMAALIGNEN (rx_calign),
     .RXPCSRESET (1'd0),
     .RXPD (2'd0),
     .RXPHALIGN (1'd0),
@@ -1167,7 +1251,7 @@ module util_adxcvr_xch (
     .RXPRBSSEL (4'd0),
     .RXPROGDIVRESET (1'd0),
     .RXQPIEN (1'd0),
-    .RXRATE (rx_rate),
+    .RXRATE (up_rx_rate),
     .RXRATEMODE (1'd0),
     .RXSLIDE (1'd0),
     .RXSLIPOUTCLK (1'd0),
@@ -1176,7 +1260,7 @@ module util_adxcvr_xch (
     .RXSYNCIN (1'd0),
     .RXSYNCMODE (1'd0),
     .RXSYSCLKSEL (rx_sys_clk_sel_s),
-    .RXUSERRDY (rx_user_ready),
+    .RXUSERRDY (up_rx_user_ready),
     .RXUSRCLK (rx_clk),
     .RXUSRCLK2 (rx_clk),
     .RX8B10BEN (1'd1),
@@ -1188,8 +1272,8 @@ module util_adxcvr_xch (
     .TXCOMWAKE (1'd0),
     .TXCTRL0 (16'd0),
     .TXCTRL1 (16'd0),
-    .TXCTRL2 ({4'd0, tx_gt_charisk}),
-    .TXDATA ({32'd0, tx_gt_data}),
+    .TXCTRL2 ({4'd0, tx_charisk}),
+    .TXDATA ({32'd0, tx_data}),
     .TXDATAEXTENDRSVD (8'd0),
     .TXDEEMPH (1'd0),
     .TXDETECTRX (1'd0),
@@ -1207,7 +1291,7 @@ module util_adxcvr_xch (
     .TXLATCLK (1'd0),
     .TXMAINCURSOR (7'b1000000),
     .TXMARGIN (3'd0),
-    .TXOUTCLKSEL (tx_out_clk_sel),
+    .TXOUTCLKSEL (up_tx_out_clk_sel),
     .TXPCSRESET (1'd0),
     .TXPD (2'd0),
     .TXPDELECIDLEMODE (1'd0),
@@ -1233,11 +1317,11 @@ module util_adxcvr_xch (
     .TXPRBSSEL (4'd0),
     .TXPRECURSOR (5'd0),
     .TXPRECURSORINV (1'd0),
-    .TXPROGDIVRESET (tx_rst),
+    .TXPROGDIVRESET (up_tx_rst),
     .TXQPIBIASEN (1'd0),
     .TXQPISTRONGPDOWN (1'd0),
     .TXQPIWEAKPUP (1'd0),
-    .TXRATE (tx_rate),
+    .TXRATE (up_tx_rate),
     .TXRATEMODE (1'd0),
     .TXSEQUENCE (7'd0),
     .TXSWING (1'd0),
@@ -1245,7 +1329,7 @@ module util_adxcvr_xch (
     .TXSYNCIN (1'd0),
     .TXSYNCMODE (1'd0),
     .TXSYSCLKSEL (tx_sys_clk_sel_s),
-    .TXUSERRDY (tx_user_ready),
+    .TXUSERRDY (up_tx_user_ready),
     .TXUSRCLK (tx_clk),
     .TXUSRCLK2 (tx_clk),
     .TX8B10BBYPASS (8'd0),
@@ -1259,8 +1343,8 @@ module util_adxcvr_xch (
     .CPLLLOCK (cpll_locked_s),
     .CPLLREFCLKLOST (),
     .DMONITOROUT (),
-    .DRPDO (up_drp_rdata_s),
-    .DRPRDY (up_drp_ready_s),
+    .DRPDO (up_rdata_s),
+    .DRPRDY (up_ready_s),
     .EYESCANDATAERROR (),
     .GTHTXN (tx_n),
     .GTHTXP (tx_p),
@@ -1292,11 +1376,11 @@ module util_adxcvr_xch (
     .RXCOMMADET (),
     .RXCOMSASDET (),
     .RXCOMWAKEDET (),
-    .RXCTRL0 ({rx_charisk_open_s, rx_gt_charisk}),
-    .RXCTRL1 ({rx_disperr_open_s, rx_gt_disperr}),
+    .RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
+    .RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
     .RXCTRL2 (),
-    .RXCTRL3 ({rx_notintable_open_s, rx_gt_notintable}),
-    .RXDATA ({rx_data_open_s, rx_gt_data}),
+    .RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
+    .RXDATA ({rx_data_open_s, rx_data}),
     .RXDATAEXTENDRSVD (),
     .RXDATAVALID (),
     .RXDLYSRESETDONE (),
@@ -1321,7 +1405,7 @@ module util_adxcvr_xch (
     .RXQPISENP (),
     .RXRATEDONE (),
     .RXRECCLKOUT (),
-    .RXRESETDONE (rx_rst_done),
+    .RXRESETDONE (up_rx_rst_done),
     .RXSLIDERDY (),
     .RXSLIPDONE (),
     .RXSLIPOUTCLKRDY (),
@@ -1344,7 +1428,7 @@ module util_adxcvr_xch (
     .TXQPISENN (),
     .TXQPISENP (),
     .TXRATEDONE (),
-    .TXRESETDONE (tx_rst_done),
+    .TXRESETDONE (up_tx_rst_done),
     .TXSYNCDONE (),
     .TXSYNCOUT ());
   end
diff --git a/library/util_adxcvr/util_adxcvr_xcm.v b/library/util_adxcvr/util_adxcvr_xcm.v
index 6ec6b35df..ba3c88785 100644
--- a/library/util_adxcvr/util_adxcvr_xcm.v
+++ b/library/util_adxcvr/util_adxcvr_xcm.v
@@ -41,45 +41,83 @@ module util_adxcvr_xcm (
 
   // reset and clocks
 
-  input           ref_clk,
-  input           pll_rst,
-  output          qpll_clk,
-  output          qpll_ref_clk,
-  output          qpll_locked,
-
+  input           qpll_ref_clk,
+  output          qpll2ch_clk,
+  output          qpll2ch_ref_clk,
+  output          qpll2ch_locked,
+  
   // drp interface
 
+  input           up_rstn,
   input           up_clk,
-  input           up_drp_sel,
-  input   [11:0]  up_drp_addr,
-  input           up_drp_wr,
-  input   [15:0]  up_drp_wdata,
-  output  [15:0]  up_drp_rdata,
-  output          up_drp_ready);
+  input           up_qpll_rst,
+  input   [ 7:0]  up_cm_sel,
+  input           up_cm_enb,
+  input   [11:0]  up_cm_addr,
+  input           up_cm_wr,
+  input   [15:0]  up_cm_wdata,
+  output  [15:0]  up_cm_rdata,
+  output          up_cm_ready);
 
   // parameters
 
+  parameter   integer XCVR_ID = 0;
   parameter   integer GTH_OR_GTX_N = 0;
-  parameter   integer QPLL_ENABLE = 1;
   parameter   integer QPLL_REFCLK_DIV = 2;
   parameter   integer QPLL_FBDIV_RATIO = 1;
   parameter   [26:0]  QPLL_CFG = 27'h06801C1;
   parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000;
 
+  // internal registers
+
+  reg             up_enb_int = 'd0;
+  reg     [11:0]  up_addr_int = 'd0;
+  reg             up_wr_int = 'd0;
+  reg     [15:0]  up_wdata_int = 'd0;
+  reg     [15:0]  up_rdata_int = 'd0;
+  reg             up_ready_int = 'd0;
+
+  // internal signals
+
+  wire    [15:0]  up_rdata_s;
+  wire            up_ready_s;
+
+  // drp access
+
+  assign up_cm_rdata = up_rdata_int;
+  assign up_cm_ready = up_ready_int;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_enb_int <= 1'd0;
+      up_addr_int <= 12'd0;
+      up_wr_int <= 1'd0;
+      up_wdata_int <= 16'd0;
+      up_rdata_int <= 16'd0;
+      up_ready_int <= 1'd0;
+    end else begin
+      if ((up_cm_sel == XCVR_ID) || (up_cm_sel == 8'hff)) begin
+        up_enb_int <= up_cm_enb;
+        up_addr_int <= up_cm_addr;
+        up_wr_int <= up_cm_wr;
+        up_wdata_int <= up_cm_wdata;
+        up_rdata_int <= up_rdata_s;
+        up_ready_int <= up_ready_s;
+      end else begin
+        up_enb_int <= 1'd0;
+        up_addr_int <= 12'd0;
+        up_wr_int <= 1'd0;
+        up_wdata_int <= 16'd0;
+        up_rdata_int <= 16'd0;
+        up_ready_int <= 1'd0;
+      end
+    end
+  end
+
   // instantiations
 
   generate
-  if (QPLL_ENABLE == 0) begin
-  assign qpll_clk = 1'd0;
-  assign qpll_ref_clk = 1'd0;
-  assign qpll_locked = 1'd0;
-  assign up_drp_rdata = 16'd0;
-  assign up_drp_ready = 1'd0;
-  end
-  endgenerate
-
-  generate
-  if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 0)) begin
+  if (GTH_OR_GTX_N == 0) begin
   GTXE2_COMMON #(
     .SIM_RESET_SPEEDUP ("TRUE"),
     .SIM_QPLLREFCLK_SEL (3'b001),
@@ -102,32 +140,32 @@ module util_adxcvr_xcm (
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
   i_gtxe2_common (
     .DRPCLK (up_clk),
-    .DRPEN (up_drp_sel),
-    .DRPADDR (up_drp_addr[7:0]),
-    .DRPWE (up_drp_wr),
-    .DRPDI (up_drp_wdata),
-    .DRPDO (up_drp_rdata),
-    .DRPRDY (up_drp_ready),
+    .DRPEN (up_enb_int),
+    .DRPADDR (up_addr_int[7:0]),
+    .DRPWE (up_wr_int),
+    .DRPDI (up_wdata_int),
+    .DRPDO (up_rdata_s),
+    .DRPRDY (up_ready_s),
     .GTGREFCLK (1'd0),
     .GTNORTHREFCLK0 (1'd0),
     .GTNORTHREFCLK1 (1'd0),
-    .GTREFCLK0 (ref_clk),
+    .GTREFCLK0 (qpll_ref_clk),
     .GTREFCLK1 (1'd0),
     .GTSOUTHREFCLK0 (1'd0),
     .GTSOUTHREFCLK1 (1'd0),
     .QPLLDMONITOR (),
-    .QPLLOUTCLK (qpll_clk),
-    .QPLLOUTREFCLK (qpll_ref_clk),
+    .QPLLOUTCLK (qpll2ch_clk),
+    .QPLLOUTREFCLK (qpll2ch_ref_clk),
     .REFCLKOUTMONITOR (),
     .QPLLFBCLKLOST (),
-    .QPLLLOCK (qpll_locked),
+    .QPLLLOCK (qpll2ch_locked),
     .QPLLLOCKDETCLK (up_clk),
     .QPLLLOCKEN (1'd1),
     .QPLLOUTRESET (1'd0),
     .QPLLPD (1'd0),
     .QPLLREFCLKLOST (),
     .QPLLREFCLKSEL (3'b001),
-    .QPLLRESET (pll_rst),
+    .QPLLRESET (up_qpll_rst),
     .QPLLRSVD1 (16'b0000000000000000),
     .QPLLRSVD2 (5'b11111),
     .BGBYPASSB (1'd1),
@@ -140,7 +178,7 @@ module util_adxcvr_xcm (
   endgenerate
 
   generate
-  if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 1)) begin
+  if (GTH_OR_GTX_N == 1) begin
   GTHE3_COMMON #(
     .SIM_RESET_SPEEDUP ("TRUE"),
     .SIM_VERSION (2),
@@ -221,18 +259,18 @@ module util_adxcvr_xcm (
     .BGPDB (1'd1),
     .BGRCALOVRD (5'b11111),
     .BGRCALOVRDENB (1'd1),
-    .DRPADDR (up_drp_addr[8:0]),
+    .DRPADDR (up_addr_int[8:0]),
     .DRPCLK (up_clk),
-    .DRPDI (up_drp_wdata),
-    .DRPEN (up_drp_sel),
-    .DRPWE (up_drp_wr),
+    .DRPDI (up_wdata_int),
+    .DRPEN (up_enb_int),
+    .DRPWE (up_wr_int),
     .GTGREFCLK0 (1'd0),
     .GTGREFCLK1 (1'd0),
     .GTNORTHREFCLK00 (1'd0),
     .GTNORTHREFCLK01 (1'd0),
     .GTNORTHREFCLK10 (1'd0),
     .GTNORTHREFCLK11 (1'd0),
-    .GTREFCLK00 (ref_clk),
+    .GTREFCLK00 (qpll_ref_clk),
     .GTREFCLK01 (1'd0),
     .GTREFCLK10 (1'd0),
     .GTREFCLK11 (1'd0),
@@ -252,7 +290,7 @@ module util_adxcvr_xcm (
     .QPLL0LOCKEN (1'd1),
     .QPLL0PD (1'd0),
     .QPLL0REFCLKSEL (3'b001),
-    .QPLL0RESET (pll_rst),
+    .QPLL0RESET (up_qpll_rst),
     .QPLL1CLKRSVD0 (1'd0),
     .QPLL1CLKRSVD1 (1'd0),
     .QPLL1LOCKDETCLK (1'd0),
@@ -261,16 +299,16 @@ module util_adxcvr_xcm (
     .QPLL1REFCLKSEL (3'b001),
     .QPLL1RESET (1'd1),
     .RCALENB (1'd1),
-    .DRPDO (up_drp_rdata),
-    .DRPRDY (up_drp_ready),
+    .DRPDO (up_rdata_s),
+    .DRPRDY (up_ready_s),
     .PMARSVDOUT0 (),
     .PMARSVDOUT1 (),
     .QPLLDMONITOR0 (),
     .QPLLDMONITOR1 (),
     .QPLL0FBCLKLOST (),
-    .QPLL0LOCK (qpll_locked),
-    .QPLL0OUTCLK (qpll_clk),
-    .QPLL0OUTREFCLK (qpll_ref_clk),
+    .QPLL0LOCK (qpll2ch_locked),
+    .QPLL0OUTCLK (qpll2ch_clk),
+    .QPLL0OUTREFCLK (qpll2ch_ref_clk),
     .QPLL0REFCLKLOST (),
     .QPLL1FBCLKLOST (),
     .QPLL1LOCK (),

From def47dd53672f568ff17723f99e799f9aaca4965 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 17 Jun 2016 12:00:15 -0400
Subject: [PATCH 291/972] interfaces: added xcvr interfaces

---
 library/interfaces/interfaces_ip.tcl | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/library/interfaces/interfaces_ip.tcl b/library/interfaces/interfaces_ip.tcl
index 6b3c4dc15..4e98d5682 100644
--- a/library/interfaces/interfaces_ip.tcl
+++ b/library/interfaces/interfaces_ip.tcl
@@ -3,6 +3,33 @@
 source ../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
+adi_if_define if_xcvr_cm
+adi_if_ports output    8  sel
+adi_if_ports output    1  enb
+adi_if_ports output   12  addr
+adi_if_ports output    1  wr  
+adi_if_ports output   16  wdata
+adi_if_ports input    16  rdata
+adi_if_ports input     1  ready
+
+adi_if_define if_xcvr_ch
+adi_if_ports output    1  pll_rst
+adi_if_ports input     1  pll_locked
+adi_if_ports output    1  rst
+adi_if_ports output    1  user_ready
+adi_if_ports input     1  rst_done
+adi_if_ports output    1  lpm_dfe_n
+adi_if_ports output    3  rate
+adi_if_ports output    2  sys_clk_sel
+adi_if_ports output    3  out_clk_sel
+adi_if_ports output    8  sel
+adi_if_ports output    1  enb
+adi_if_ports output   12  addr
+adi_if_ports output    1  wr
+adi_if_ports output   16  wdata
+adi_if_ports input    16  rdata
+adi_if_ports input     1  ready
+
 adi_if_define if_gt_qpll
 adi_if_ports output    1  qpll_rst            reset
 adi_if_ports output    1  qpll_ref_clk        clock

From cdf01a492edcc074abdb73da5cd876618bad5d51 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 22 Jun 2016 12:24:54 +0300
Subject: [PATCH 292/972] library/axi_dacfifo: Update the bypass logic

The bypass logic is located between the AXI read controller and the
DAC CDC fifo. When the bypass is enabled the DMAC destination interface
must be clocked with the PL_DDR controller's ui_clk. This way it can easily
switch between the AXI read's stream and DMAC's stream interface.
---
 library/axi_dacfifo/axi_dacfifo.v          | 46 ++++++++++++++++++----
 library/axi_dacfifo/axi_dacfifo_constr.xdc |  5 +++
 library/axi_dacfifo/axi_dacfifo_ip.tcl     |  5 ++-
 3 files changed, 47 insertions(+), 9 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index 82e236db3..e1af682ce 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -118,6 +118,7 @@ module axi_dacfifo (
   parameter   AXI_ADDRESS = 32'h00000000;
   parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
   parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
+  parameter   BYPASS_EN = 1;
 
   // dma interface
 
@@ -195,13 +196,18 @@ module axi_dacfifo (
   wire                                axi_rd_ready_s;
   wire                                axi_rd_valid_s;
   wire                                axi_xfer_req_s;
+  wire    [(AXI_DATA_WIDTH-1):0]      dac_rd_data_s;
+  wire                                dac_rd_ready_s;
+  wire                                dac_rd_valid_s;
   wire    [31:0]                      axi_last_addr_s;
   wire    [31:0]                      dma_last_addr_s;
 
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
   wire                                dma_ready_s;
 
-  // instantiations
+  wire                                dma_valid_bp_s;
+  wire    [(AXI_DATA_WIDTH-1):0]      dma_data_bp_s;
+  wire                                dma_ready_bp_s;
 
   axi_dacfifo_wr #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@@ -287,22 +293,48 @@ module axi_dacfifo (
     .DAC_DATA_WIDTH (DAC_DATA_WIDTH)
   ) i_dac (
     .axi_clk (axi_clk),
-    .axi_dvalid (axi_rd_valid_s),
-    .axi_ddata (axi_rd_data_s),
+    .axi_dvalid (dac_rd_valid_s),
+    .axi_ddata (dac_rd_data_s),
     .axi_dready (axi_rd_ready_s),
     .axi_xfer_req (axi_xfer_req_s),
     .dma_last_addr (dma_last_addr_s),
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid),
-    .dac_data (dac_data_s),
+    .dac_data (dac_data),
     .dac_xfer_out (dac_xfer_out),
     .dac_dunf (dac_dunf));
 
-  // output logic
+  // bypass logic
 
-  assign dac_data = (dac_fifo_bypass) ? dma_data : dac_data_s;
-  assign dma_ready = (dac_fifo_bypass) ? dac_valid : dma_ready_s;
+  generate if (BYPASS_EN == 1) begin
+
+    util_axis_resize #(
+      .MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
+      .SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
+    ) i_util_axis_resize (
+      .clk (axi_clk),
+      .resetn (axi_resetn),
+      .s_valid (dma_valid),
+      .s_ready (dma_ready_bp_s),
+      .s_data (dma_data),
+      .m_valid (dma_valid_bp_s),
+      .m_ready (axi_rd_ready_s),
+      .m_data (dma_data_bp_s)
+    );
+
+    assign  dac_rd_valid_s = (dac_fifo_bypass) ? dma_valid_bp_s : axi_rd_valid_s;
+    assign  dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
+    assign  dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
+
+  end else begin
+
+    assign  dac_rd_valid_s = axi_rd_valid_s;
+    assign  dac_rd_data_s = axi_rd_data_s;
+    assign  dma_ready = dma_ready_s;
+
+  end
+  endgenerate
 
 endmodule
 
diff --git a/library/axi_dacfifo/axi_dacfifo_constr.xdc b/library/axi_dacfifo/axi_dacfifo_constr.xdc
index 55262bad7..8942ef3d9 100644
--- a/library/axi_dacfifo/axi_dacfifo_constr.xdc
+++ b/library/axi_dacfifo/axi_dacfifo_constr.xdc
@@ -15,3 +15,8 @@ set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP
 set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
   -to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
 
+set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+
diff --git a/library/axi_dacfifo/axi_dacfifo_ip.tcl b/library/axi_dacfifo/axi_dacfifo_ip.tcl
index 905139739..77c5b2acc 100644
--- a/library/axi_dacfifo/axi_dacfifo_ip.tcl
+++ b/library/axi_dacfifo/axi_dacfifo_ip.tcl
@@ -8,11 +8,12 @@ adi_ip_create axi_dacfifo
 adi_ip_files axi_dacfifo [list \
   "$ad_hdl_dir/library/common/ad_mem_asym.v" \
   "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
+  "$ad_hdl_dir/library/util_axis_resize/util_axis_resize.v" \
+  "axi_dacfifo_constr.xdc" \
   "axi_dacfifo_dac.v" \
   "axi_dacfifo_wr.v" \
   "axi_dacfifo_rd.v" \
-  "axi_dacfifo.v" \
-  "axi_dacfifo_constr.xdc" ]
+  "axi_dacfifo.v"]
 
 adi_ip_properties_lite axi_dacfifo
 adi_ip_constraints axi_dacfifo [list \

From 2e80dec51391763cec08804d8fbc938ae08f162c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 22 Jun 2016 12:33:47 +0300
Subject: [PATCH 293/972] adrv9371x/zc706: Update project with the new
 axi_dacfifo

---
 projects/adrv9371x/common/adrv9371x_bd.tcl            | 7 ++++---
 projects/common/zc706/zc706_system_plddr3_dacfifo.tcl | 6 +++++-
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index 3e9d91694..90b36d9e6 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -36,7 +36,7 @@ ad_connect  sys_dma_rstgen/ext_reset_in sys_ps7/FCLK_RESET2_N
 set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_tx_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma
-set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_tx_dma
+set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_tx_dma
@@ -251,14 +251,15 @@ ad_connect  axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
 ad_connect  axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
 ad_connect  axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
 
-ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_dma/m_axis_aclk
+ad_connect  pl_ddr_clk axi_ad9371_dacfifo/ddr_clk
+ad_connect  pl_ddr_clk axi_ad9371_tx_dma/m_axis_aclk
+ad_connect  pl_ddr_clk axi_ad9371_dacfifo/dma_clk
 ad_connect  sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
 ad_connect  util_ad9371_gt/tx_rst axi_ad9371_dacfifo/dac_rst
 ad_connect  util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out
 ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
 ad_connect  util_ad9371_tx_upack/dac_valid axi_ad9371_dacfifo/dac_valid
 ad_connect  util_ad9371_tx_upack/dac_data axi_ad9371_dacfifo/dac_data
-ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dma_clk
 
 ad_connect  axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
 ad_connect  axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready
diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index d7fceee87..2c2281846 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -33,6 +33,8 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   create_bd_pin -dir I dma_xfer_req
   create_bd_pin -dir I dma_xfer_last
 
+  create_bd_pin -dir O ddr_clk
+
   set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
   set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
   file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
@@ -50,6 +52,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   set_property -dict [list CONFIG.AXI_LENGTH {15}] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo
+  set_property -dict [list CONFIG.BYPASS_EN {1}] $axi_dacfifo
 
   ## clock and reset
 
@@ -58,8 +61,9 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   ad_connect  axi_clk axi_ddr_cntrl/ui_clk
   ad_connect  axi_clk axi_dacfifo/axi_clk
   ad_connect  axi_clk axi_rstgen/slowest_sync_clk
-  ad_connect  dac_clk axi_dacfifo/dac_clk
   ad_connect  dma_clk axi_dacfifo/dma_clk
+  ad_connect  ddr_clk axi_ddr_cntrl/ui_clk
+  ad_connect  dac_clk axi_dacfifo/dac_clk
 
   ad_connect  axi_resetn axi_rstgen/peripheral_aresetn
   ad_connect  axi_resetn axi_dacfifo/axi_resetn

From e6494b9a745ae4900e71e1dfc0e136c8265506d0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 29 Jun 2016 14:11:02 +0300
Subject: [PATCH 294/972] axi_ad7616: Change the DMA interface type to Write
 FIFO

---
 library/axi_ad7616/axi_ad7616.v              | 179 ++++++++++---------
 library/axi_ad7616/axi_ad7616_ip.tcl         |   7 +-
 library/axi_ad7616/axi_ad7616_maxis2wrfifo.v | 107 +++++++++++
 library/axi_ad7616/axi_ad7616_pif.v          |  59 +++---
 projects/ad7616_sdz/common/ad7616_bd.tcl     |  10 +-
 5 files changed, 237 insertions(+), 125 deletions(-)
 create mode 100644 library/axi_ad7616/axi_ad7616_maxis2wrfifo.v

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 3d82ae8cc..3f0a18df5 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -82,12 +82,11 @@ module axi_ad7616 (
   s_axi_rdata,
   s_axi_rready,
 
-  // AXI-Stream Master
+  // Write FIFO interface
 
-  m_axis_tdata,
-  m_axis_tvalid,
-  m_axis_tready,
-  m_axis_xfer_req,
+  adc_valid,
+  adc_data,
+  adc_sync,
 
   irq
 );
@@ -96,11 +95,9 @@ module axi_ad7616 (
 
   parameter       ID = 0;
   parameter       IF_TYPE = 1;
-  parameter       M_AXIS_READY_ENABLE = 0;
 
   // local parameters
 
-  localparam      DATA_WIDTH = 8;
   localparam      NUM_OF_SDI = 2;
   localparam      SERIAL = 0;
   localparam      PARALLEL = 1;
@@ -109,50 +106,53 @@ module axi_ad7616 (
 
   // IO definitions
 
-  output          sclk;
-  output          cs_n;
-  output          sdo;
-  input           sdi_0;
-  input           sdi_1;
+  output                            sclk;
+  output                            cs_n;
+  output                            sdo;
+  input                             sdi_0;
+  input                             sdi_1;
 
-  output  [15:0]  db_o;
-  input   [15:0]  db_i;
-  output          db_t;
-  output          rd_n;
-  output          wr_n;
+  output  [15:0]                    db_o;
+  input   [15:0]                    db_i;
+  output                            db_t;
+  output                            rd_n;
+  output                            wr_n;
 
-  output          cnvst;
-  input           busy;
+  output                            cnvst;
+  input                             busy;
 
-  input           s_axi_aclk;
-  input           s_axi_aresetn;
-  input           s_axi_awvalid;
-  input   [31:0]  s_axi_awaddr;
-  output          s_axi_awready;
-  input           s_axi_wvalid;
-  input   [31:0]  s_axi_wdata;
-  input   [ 3:0]  s_axi_wstrb;
-  output          s_axi_wready;
-  output          s_axi_bvalid;
-  output  [ 1:0]  s_axi_bresp;
-  input           s_axi_bready;
-  input           s_axi_arvalid;
-  input   [31:0]  s_axi_araddr;
-  output          s_axi_arready;
-  output          s_axi_rvalid;
-  output  [ 1:0]  s_axi_rresp;
-  output  [31:0]  s_axi_rdata;
-  input           s_axi_rready;
+  input                             s_axi_aclk;
+  input                             s_axi_aresetn;
+  input                             s_axi_awvalid;
+  input   [31:0]                    s_axi_awaddr;
+  output                            s_axi_awready;
+  input                             s_axi_wvalid;
+  input   [31:0]                    s_axi_wdata;
+  input   [ 3:0]                    s_axi_wstrb;
+  output                            s_axi_wready;
+  output                            s_axi_bvalid;
+  output  [ 1:0]                    s_axi_bresp;
+  input                             s_axi_bready;
+  input                             s_axi_arvalid;
+  input   [31:0]                    s_axi_araddr;
+  output                            s_axi_arready;
+  output                            s_axi_rvalid;
+  output  [ 1:0]                    s_axi_rresp;
+  output  [31:0]                    s_axi_rdata;
+  input                             s_axi_rready;
 
-  output  [(NUM_OF_SDI * DATA_WIDTH-1):0]  m_axis_tdata;
-  input           m_axis_tready;
-  output          m_axis_tvalid;
-  input           m_axis_xfer_req;
+  output                            adc_valid;
+  output  [15:0]                    adc_data;
+  output                            adc_sync;
 
-  output          irq;
+  output                            irq;
 
   // internal registers
 
+  reg                               up_wack = 1'b0;
+  reg                               up_rack = 1'b0;
+  reg     [31:0]                    up_rdata = 32'b0;
+
   // internal signals
 
   wire                              up_clk;
@@ -180,12 +180,10 @@ module axi_ad7616 (
   wire                              rd_valid_s;
 
   wire                              m_axis_ready_s;
-
-  // internal registers
-
-  reg                               up_wack = 1'b0;
-  reg                               up_rack = 1'b0;
-  reg     [31:0]                    up_rdata = 32'b0;
+  wire                              m_axis_valid_s;
+  wire    [15:0]                    m_axis_data_s;
+  wire                              m_axis_xfer_req_s;
+  wire    [15:0]                    adc_data_s;
 
   // defaults
 
@@ -207,8 +205,6 @@ module axi_ad7616 (
     end
   end
 
-  assign m_axis_ready_s = (M_AXIS_READY_ENABLE) ? m_axis_tready : 1'b1;
-
   generate if (IF_TYPE == SERIAL) begin
 
     // ground all parallel interface signals
@@ -225,10 +221,10 @@ module axi_ad7616 (
     wire  [15:0]                            s0_cmd_data_s;
     wire                                    s0_sdo_data_ready_s;
     wire                                    s0_sdo_data_valid_s;
-    wire  [(DATA_WIDTH-1):0]                s0_sdo_data_s;
+    wire  [ 7:0]                            s0_sdo_data_s;
     wire                                    s0_sdi_data_ready_s;
     wire                                    s0_sdi_data_valid_s;
-    wire  [(NUM_OF_SDI * DATA_WIDTH-1):0]   s0_sdi_data_s;
+    wire  [15:0]                            s0_sdi_data_s;
     wire                                    s0_sync_ready_s;
     wire                                    s0_sync_valid_s;
     wire  [ 7:0]                            s0_sync_s;
@@ -237,10 +233,10 @@ module axi_ad7616 (
     wire  [15:0]                            s1_cmd_data_s;
     wire                                    s1_sdo_data_ready_s;
     wire                                    s1_sdo_data_valid_s;
-    wire  [(DATA_WIDTH-1):0]                s1_sdo_data_s;
+    wire  [ 7:0]                            s1_sdo_data_s;
     wire                                    s1_sdi_data_ready_s;
     wire                                    s1_sdi_data_valid_s;
-    wire  [(NUM_OF_SDI * DATA_WIDTH-1):0]   s1_sdi_data_s;
+    wire  [15:0]                            s1_sdi_data_s;
     wire                                    s1_sync_ready_s;
     wire                                    s1_sync_valid_s;
     wire  [ 7:0]                            s1_sync_s;
@@ -249,28 +245,28 @@ module axi_ad7616 (
     wire  [15:0]                            m_cmd_data_s;
     wire                                    m_sdo_data_ready_s;
     wire                                    m_sdo_data_valid_s;
-    wire  [(DATA_WIDTH-1):0]                m_sdo_data_s;
+    wire  [7:0]                             m_sdo_data_s;
     wire                                    m_sdi_data_ready_s;
     wire                                    m_sdi_data_valid_s;
-    wire  [(NUM_OF_SDI * DATA_WIDTH-1):0]   m_sdi_data_s;
+    wire  [15:0]                            m_sdi_data_s;
     wire                                    m_sync_ready_s;
     wire                                    m_sync_valid_s;
     wire  [ 7:0]                            m_sync_s;
     wire                                    offload0_cmd_wr_en_s;
     wire  [15:0]                            offload0_cmd_wr_data_s;
     wire                                    offload0_sdo_wr_en_s;
-    wire  [(DATA_WIDTH-1):0]                offload0_sdo_wr_data_s;
+    wire  [ 7:0]                            offload0_sdo_wr_data_s;
     wire                                    offload0_mem_reset_s;
     wire                                    offload0_enable_s;
     wire                                    offload0_enabled_s;
 
     axi_spi_engine #(
-      .DATA_WIDTH (DATA_WIDTH),
+      .DATA_WIDTH (8),
       .NUM_OF_SDI (NUM_OF_SDI),
       .NUM_OFFLOAD(1),
       .MM_IF_TYPE(1),
       .UP_ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
-    ) i_axi_spi_engine(
+    ) i_axi_spi_engine (
       .up_clk (up_clk),
       .up_rstn (up_rstn),
       .up_wreq (up_wreq_s),
@@ -305,9 +301,9 @@ module axi_ad7616 (
       .offload0_enabled(offload0_enabled_s));
 
     spi_engine_offload #(
-      .DATA_WIDTH (DATA_WIDTH),
+      .DATA_WIDTH (8),
       .NUM_OF_SDI (NUM_OF_SDI)
-    ) i_spi_engine_offload(
+    ) i_spi_engine_offload (
       .ctrl_clk (up_clk),
       .ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
       .ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
@@ -331,12 +327,12 @@ module axi_ad7616 (
       .sync_valid (s1_sync_valid_s),
       .sync_ready (s1_sync_ready_s),
       .sync_data (s1_sync_s),
-      .offload_sdi_valid (m_axis_tvalid),
+      .offload_sdi_valid (m_axis_valid_s),
       .offload_sdi_ready (m_axis_ready_s),
-      .offload_sdi_data (m_axis_tdata));
+      .offload_sdi_data (m_axis_data_s));
 
     spi_engine_interconnect #(
-      .DATA_WIDTH (DATA_WIDTH),
+      .DATA_WIDTH (8),
       .NUM_OF_SDI (NUM_OF_SDI)
     ) i_spi_engine_interconnect (
       .clk (up_clk),
@@ -379,7 +375,7 @@ module axi_ad7616 (
       .s1_sync (s1_sync_s));
 
     spi_engine_execution #(
-      .DATA_WIDTH (DATA_WIDTH),
+      .DATA_WIDTH (8),
       .NUM_OF_SDI (NUM_OF_SDI)
     ) i_spi_engine_execution (
       .clk (up_clk),
@@ -407,8 +403,21 @@ module axi_ad7616 (
       .cs (cs_n),
       .three_wire ());
 
-  end
+    axi_ad7616_maxis2wrfifo #(
+      .DATA_WIDTH(16)
+    ) i_maxis2wrfifo (
+      .clk(up_clk),
+      .rstn(up_rstn),
+      .sync_in(trigger_s),
+      .m_axis_data(m_axis_data_s),
+      .m_axis_ready(m_axis_ready_s),
+      .m_axis_valid(m_axis_valid_s),
+      .fifo_wr_en(adc_valid),
+      .fifo_wr_data(adc_data_s),
+      .fifo_wr_sync(adc_sync)
+    );
 
+  end
   endgenerate
 
   generate if (IF_TYPE == PARALLEL) begin
@@ -422,23 +431,23 @@ module axi_ad7616 (
     assign up_rdata_if_s = 1'h0;
 
     axi_ad7616_pif i_ad7616_parallel_interface (
-      .cs_n(cs_n),
-      .db_o(db_o),
-      .db_i(db_i),
-      .db_t(db_t),
-      .rd_n(rd_n),
-      .wr_n(wr_n),
-      .m_axis_tdata(m_axis_tdata),
-      .m_axis_tvalid(m_axis_tvalid),
-      .m_axis_xfer_req(m_axis_xfer_req),
-      .end_of_conv(trigger_s),
-      .clk(up_clk),
-      .rstn(up_rstn),
-      .rd_req(rd_req_s),
-      .wr_req(wr_req_s),
-      .wr_data(wr_data_s),
-      .rd_data(rd_data_s),
-      .rd_valid(rd_valid_s)
+      .cs_n (cs_n),
+      .db_o (db_o),
+      .db_i (db_i),
+      .db_t (db_t),
+      .rd_n (rd_n),
+      .wr_n (wr_n),
+      .adc_data (adc_data_s),
+      .adc_valid (adc_valid),
+      .adc_sync (adc_sync),
+      .end_of_conv (trigger_s),
+      .clk (up_clk),
+      .rstn (up_rstn),
+      .rd_req (rd_req_s),
+      .wr_req (wr_req_s),
+      .wr_data (wr_data_s),
+      .rd_data (rd_data_s),
+      .rd_valid (rd_valid_s)
     );
 
   end
@@ -467,6 +476,8 @@ module axi_ad7616 (
     .up_rdata (up_rdata_cntrl_s),
     .up_rack (up_rack_cntrl_s));
 
+  assign adc_data = adc_data_s;
+
   // up bus interface
 
   up_axi #(
diff --git a/library/axi_ad7616/axi_ad7616_ip.tcl b/library/axi_ad7616/axi_ad7616_ip.tcl
index a9cf3a196..328ac97e5 100644
--- a/library/axi_ad7616/axi_ad7616_ip.tcl
+++ b/library/axi_ad7616/axi_ad7616_ip.tcl
@@ -5,11 +5,12 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create axi_ad7616
 adi_ip_files axi_ad7616 [list \
-    "axi_ad7616.v" \
+    "$ad_hdl_dir/library/common/ad_edge_detect.v" \
+    "$ad_hdl_dir/library/common/up_axi.v" \
     "axi_ad7616_control.v" \
     "axi_ad7616_pif.v" \
-    "$ad_hdl_dir/library/common/ad_edge_detect.v" \
-    "$ad_hdl_dir/library/common/up_axi.v"]
+    "axi_ad7616_maxis2wrfifo.v" \
+    "axi_ad7616.v" ]
 
 adi_ip_properties axi_ad7616
 
diff --git a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
new file mode 100644
index 000000000..03448feed
--- /dev/null
+++ b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
@@ -0,0 +1,107 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2013(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad7616_maxis2wrfifo (
+
+  clk,
+  rstn,
+  sync_in,
+
+  // m_axis interface
+
+  m_axis_data,
+  m_axis_ready,
+  m_axis_valid,
+  m_axis_xfer_req,
+
+  // write fifo interface
+
+  fifo_wr_en,
+  fifo_wr_data,
+  fifo_wr_sync,
+  fifo_wr_xfer_req
+
+);
+
+  parameter   DATA_WIDTH = 16;
+
+  input                     clk;
+  input                     rstn;
+  input                     sync_in;
+
+  input  [DATA_WIDTH-1:0]   m_axis_data;
+  output                    m_axis_ready;
+  input                     m_axis_valid;
+  output                    m_axis_xfer_req;
+
+  output                    fifo_wr_en;
+  output [DATA_WIDTH-1:0]   fifo_wr_data;
+  output                    fifo_wr_sync;
+  input                     fifo_wr_xfer_req;
+
+  reg                       m_axis_ready = 1'b0;
+  reg                       m_axis_xfer_req = 1'b0;
+  reg                       fifo_wr_en = 1'b0;
+  reg    [DATA_WIDTH-1:0]   fifo_wr_data = 'b0;
+  reg                       fifo_wr_sync = 1'b0;
+
+  always @(posedge clk) begin
+    if (rstn == 1'b0) begin
+      m_axis_ready <= 1'b0;
+      m_axis_xfer_req <= 1'b0;
+      fifo_wr_data <= 'b0;
+      fifo_wr_en <= 1'b0;
+      fifo_wr_sync <= 1'b0;
+    end else begin
+      m_axis_ready <= 1'b1;
+      m_axis_xfer_req <= fifo_wr_xfer_req;
+      fifo_wr_data <= m_axis_data;
+      fifo_wr_en <= m_axis_valid;
+      if (sync_in == 1'b1) begin
+        fifo_wr_sync <= 1'b1;
+      end else if ((m_axis_valid == 1'b1) &&
+                   (fifo_wr_sync == 1'b1)) begin
+        fifo_wr_sync <= 1'b0;
+      end
+    end
+  end
+
+endmodule
diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v
index a983406ce..962cf67bf 100644
--- a/library/axi_ad7616/axi_ad7616_pif.v
+++ b/library/axi_ad7616/axi_ad7616_pif.v
@@ -50,11 +50,11 @@ module axi_ad7616_pif (
   rd_n,
   wr_n,
 
-  // axi stream master
+  // FIFO interface
 
-  m_axis_tdata,
-  m_axis_tvalid,
-  m_axis_xfer_req,
+  adc_data,
+  adc_valid,
+  adc_sync,
 
   // end of convertion
 
@@ -92,9 +92,9 @@ module axi_ad7616_pif (
   output  [15:0]                  rd_data;
   output                          rd_valid;
 
-  output  [31:0]                  m_axis_tdata;
-  output                          m_axis_tvalid;
-  input                           m_axis_xfer_req;
+  output  [15:0]                  adc_data;
+  output                          adc_valid;
+  output                          adc_sync;
 
   // state registers
 
@@ -118,15 +118,15 @@ module axi_ad7616_pif (
 
   reg                             xfer_req_d = 1'h0;
 
-  reg     [15:0]                  data_out_a = 16'h0;
-  reg     [15:0]                  data_out_b = 16'h0;
-  reg                             rd_db_valid_div2 = 1'h0;
+  reg                             adc_sync = 1'h0;
   reg                             rd_valid = 1'h0;
+  reg                             rd_valid_d = 1'h0;
+  reg     [15:0]                  rd_data = 16'h0;
 
   // internal wires
 
-  wire                            start_transfer;
-  wire                            rd_db_valid;
+  wire                            start_transfer_s;
+  wire                            rd_valid_s;
 
   // FSM state register
 
@@ -140,7 +140,7 @@ module axi_ad7616_pif (
 
   // counters to control the RD_N and WR_N lines
 
-  assign start_transfer = end_of_conv | rd_req | wr_req;
+  assign start_transfer_s = end_of_conv | rd_req | wr_req;
 
   always @(posedge clk) begin
     if (rstn == 1'b0) begin
@@ -167,7 +167,7 @@ module axi_ad7616_pif (
   always @(*) begin
     case (transfer_state)
       IDLE : begin
-        transfer_state_next <= (start_transfer == 1'b1) ? CS_LOW : IDLE;
+        transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE;
       end
       CS_LOW : begin
         transfer_state_next <= CNTRL0_LOW;
@@ -196,28 +196,21 @@ module axi_ad7616_pif (
 
   // data valid for the register access and m_axis interface
 
-  assign rd_db_valid = ((transfer_state == CS_HIGH) &&
+  assign rd_valid_s = (((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH)) &&
                        ((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0;
 
-  always @(posedge clk) begin
-    if (cs_n) begin
-      rd_db_valid_div2 <= 1'h0;
-    end else begin
-      rd_db_valid_div2 <= (rd_db_valid) ? ~rd_db_valid_div2 : rd_db_valid_div2;
-    end
-  end
-
   // FSM output logic
 
   assign db_o = wr_data;
 
   always @(posedge clk) begin
-    data_out_a <= (transfer_state == CNTRL0_HIGH) ? db_i : data_out_a;
-    data_out_b <= (transfer_state == CNTRL1_HIGH) ? db_i : data_out_b;
-    rd_valid <= rd_db_valid;
+    rd_data <= (rd_valid_s & ~rd_valid_d) ? db_i : rd_data;
+    rd_valid_d <= rd_valid_s;
+    rd_valid <= rd_valid_s & ~rd_valid_d;
   end
 
-  assign rd_data = data_out_a;
+  assign adc_valid = rd_valid;
+  assign adc_data = rd_data;
 
   assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
   assign db_t = ~wr_req_d;
@@ -225,17 +218,15 @@ module axi_ad7616_pif (
                   (transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1;
   assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1;
 
-  // Master AXI stream output logic with additional xfer_req signal
-  // The first valid data is ALWAYS the first sample of a convertion
+  // sync will be asserted at the first valid data right after the convertion start
 
-  always @(negedge clk) begin
+  always @(posedge clk) begin
     if (end_of_conv == 1'b1) begin
-      xfer_req_d <= m_axis_xfer_req;
+      adc_sync <= 1'b1;
+    end else if (rd_valid == 1'b1) begin
+      adc_sync <= 1'b0;
     end
   end
 
-  assign m_axis_tdata = {data_out_b, data_out_a};
-  assign m_axis_tvalid = xfer_req_d & rd_valid & rd_db_valid_div2;
-
 endmodule
 
diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index 858459e44..71537e87b 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -26,7 +26,7 @@ set axi_ad7616 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad7616:1.0 axi
 set_property -dict [list CONFIG.IF_TYPE $ad7616_if] $axi_ad7616
 
 set axi_ad7616_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad7616_dma]
-set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad7616_dma
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad7616_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad7616_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad7616_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad7616_dma
@@ -59,9 +59,11 @@ if {$ad7616_if == 0} {
 
 }
 
-ad_connect  sys_cpu_clk axi_ad7616_dma/s_axis_aclk
-ad_connect  axi_ad7616/m_axis axi_ad7616_dma/s_axis
-ad_connect  axi_ad7616/m_axis_xfer_req axi_ad7616_dma/s_axis_xfer_req
+ad_connect  sys_cpu_clk axi_ad7616_dma/s_axi_aclk
+ad_connect  sys_cpu_clk axi_ad7616_dma/fifo_wr_clk
+ad_connect  axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en
+ad_connect  axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din
+ad_connect  axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync
 
 # interconnect
 

From 18e28b01fd62c1a5a84aa819c33f84280cbf5b09 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 29 Jun 2016 14:17:28 +0300
Subject: [PATCH 295/972] axi_ad7616: Add burst counter to the parallel
 interface

With this counter the parallel logic supports the burst sequencer.
---
 library/axi_ad7616/axi_ad7616.v         |  4 +++-
 library/axi_ad7616/axi_ad7616_control.v | 18 +++++++++++++-----
 library/axi_ad7616/axi_ad7616_pif.v     | 16 +++++++++++++++-
 3 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 3f0a18df5..a1ee5fa93 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -178,7 +178,7 @@ module axi_ad7616 (
   wire    [15:0]                    wr_data_s;
   wire    [15:0]                    rd_data_s;
   wire                              rd_valid_s;
-
+  wire    [ 4:0]                    burst_length_s;
   wire                              m_axis_ready_s;
   wire                              m_axis_valid_s;
   wire    [15:0]                    m_axis_data_s;
@@ -441,6 +441,7 @@ module axi_ad7616 (
       .adc_valid (adc_valid),
       .adc_sync (adc_sync),
       .end_of_conv (trigger_s),
+      .burst_length(burst_length_s),
       .clk (up_clk),
       .rstn (up_rstn),
       .rd_req (rd_req_s),
@@ -459,6 +460,7 @@ module axi_ad7616 (
   ) i_ad7616_control (
     .cnvst (cnvst),
     .busy (busy),
+    .up_burst_length (burst_length_s),
     .up_read_data (rd_data_s),
     .up_read_valid (rd_valid_s),
     .up_write_data (wr_data_s),
diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index 22198be1f..bc40f101d 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -52,6 +52,7 @@ module axi_ad7616_control (
   up_read_req,
   up_write_req,
 
+  up_burst_length,
   end_of_conv,
 
   // bus interface
@@ -82,6 +83,7 @@ module axi_ad7616_control (
   input           busy;
 
   output          end_of_conv;
+  output  [ 4:0]  up_burst_length;
 
   input   [15:0]  up_read_data;
   input           up_read_valid;
@@ -111,6 +113,7 @@ module axi_ad7616_control (
   reg             up_rack = 1'b0;
   reg     [31:0]  up_rdata = 32'b0;
   reg     [31:0]  up_conv_rate = 32'b0;
+  reg     [ 4:0]  up_burst_length = 5'h0;
   reg     [15:0]  up_write_data = 16'h0;
 
   reg     [31:0]  cnvst_counter = 32'b0;
@@ -146,6 +149,7 @@ module axi_ad7616_control (
       up_resetn <= 1'b0;
       up_cnvst_en <= 1'b0;
       up_conv_rate <= 32'b0;
+      up_burst_length <= 5'h0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@@ -158,18 +162,21 @@ module axi_ad7616_control (
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
         up_conv_rate <= up_wdata;
       end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
+        up_burst_length <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
         up_write_data <= up_wdata;
       end
     end
   end
 
-  assign up_write_req = (up_waddr[7:0] == 8'h13) ? up_wreq_s : 1'h0;
+  assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0;
 
   // processor read interface
 
-  assign up_rack_s = (up_raddr[7:0] == 8'h12) ? up_read_valid_s : up_rreq_s;
-  assign up_read_req = (up_raddr[7:0] == 8'h12) ? up_rreq_s : 1'b0;
+  assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
+  assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0;
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
@@ -185,7 +192,8 @@ module axi_ad7616_control (
           8'h03 : up_rdata = IF_TYPE;
           8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
           8'h11 : up_rdata = up_conv_rate;
-          8'h12 : up_rdata = up_read_data_s;
+          8'h12 : up_rdata = {27'b0, up_burst_length};
+          8'h13 : up_rdata = up_read_data_s;
         endcase
       end
     end
diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v
index 962cf67bf..491222f30 100644
--- a/library/axi_ad7616/axi_ad7616_pif.v
+++ b/library/axi_ad7616/axi_ad7616_pif.v
@@ -59,6 +59,7 @@ module axi_ad7616_pif (
   // end of convertion
 
   end_of_conv,
+  burst_length,
 
   // register access
 
@@ -83,6 +84,7 @@ module axi_ad7616_pif (
   output                          wr_n;
 
   input                           end_of_conv;
+  input   [ 4:0]                  burst_length;
 
   input                           clk;
   input                           rstn;
@@ -111,6 +113,7 @@ module axi_ad7616_pif (
   reg     [ 2:0]                  transfer_state = 3'h0;
   reg     [ 2:0]                  transfer_state_next = 3'h0;
   reg     [ 1:0]                  width_counter = 2'h0;
+  reg     [ 4:0]                  burst_counter = 5'h0;
 
   reg                             wr_req_d = 1'h0;
   reg                             rd_req_d = 1'h0;
@@ -154,6 +157,17 @@ module axi_ad7616_pif (
     end
   end
 
+  always @(posedge clk) begin
+    if (rstn == 1'b0) begin
+      burst_counter <= 2'h0;
+    end else begin
+      if (transfer_state == CS_HIGH)
+        burst_counter <= burst_counter + 1;
+      else if (transfer_state == IDLE)
+        burst_counter <= 5'h0;
+    end
+  end
+
   always @(negedge clk) begin
     if (transfer_state == IDLE) begin
       wr_req_d <= wr_req;
@@ -186,7 +200,7 @@ module axi_ad7616_pif (
         transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
       end
       CS_HIGH : begin
-        transfer_state_next <= IDLE;
+        transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW;
       end
       default : begin
         transfer_state_next <= IDLE;

From 8d558b253800cd20601e72c55c2040f9b09be4bf Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 29 Jun 2016 14:49:16 +0300
Subject: [PATCH 296/972] make: Update Make files

---
 library/axi_ad7616/Makefile        | 27 +++++++++++++++------------
 library/axi_dacfifo/Makefile       |  3 ++-
 projects/ad7616_sdz/zc706/Makefile |  2 ++
 projects/ad7616_sdz/zed/Makefile   |  2 ++
 4 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile
index 0e1c103ae..5b9dfea8c 100644
--- a/library/axi_ad7616/Makefile
+++ b/library/axi_ad7616/Makefile
@@ -8,15 +8,16 @@
 M_DEPS := axi_ad7616_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += axi_ad7616.v
-M_DEPS += axi_ad7616_control.v
-M_DEPS += axi_ad7616_pif.v
 M_DEPS += ../common/ad_edge_detect.v
 M_DEPS += ../common/up_axi.v
-M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
-M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
-M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
-M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
+M_DEPS += axi_ad7616_control.v
+M_DEPS += axi_ad7616_pif.v
+M_DEPS += axi_ad7616_maxis2wrfifo.v
+M_DEPS += axi_ad7616.v
+M_DEPS += ../spi_engine_execution/spi_engine_execution.xpr
+M_DEPS += ../axi_spi_engine/axi_spi_engine.xpr
+M_DEPS += ../spi_engine_offload/spi_engine_offload.xpr
+M_DEPS += ../spi_engine_interconnect/spi_engine_interconnect.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -27,9 +28,11 @@ M_FLIST += *.log
 M_FLIST += component.xml
 M_FLIST += *.jou
 M_FLIST +=  xgui
-M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
 M_FLIST += *.hw
 M_FLIST += *.sim
+M_FLIST += .Xil
 
 
 
@@ -49,9 +52,9 @@ axi_ad7616.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_ad7616_ip.tcl  >> axi_ad7616_ip.log 2>&1
 
 dep:
-	make -C ../spi_engine/spi_engine_execution
-	make -C ../spi_engine/axi_spi_engine
-	make -C ../spi_engine/spi_engine_offload
-	make -C ../spi_engine/spi_engine_interconnect
+	make -C ../spi_engine_execution
+	make -C ../axi_spi_engine
+	make -C ../spi_engine_offload
+	make -C ../spi_engine_interconnect
 ####################################################################################
 ####################################################################################
diff --git a/library/axi_dacfifo/Makefile b/library/axi_dacfifo/Makefile
index f943c069d..bac4b509e 100644
--- a/library/axi_dacfifo/Makefile
+++ b/library/axi_dacfifo/Makefile
@@ -10,11 +10,12 @@ M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_mem_asym.v
 M_DEPS += ../common/ad_axis_inf_rx.v
+M_DEPS += ../util_axis_resize/util_axis_resize.v
+M_DEPS += axi_dacfifo_constr.xdc
 M_DEPS += axi_dacfifo_dac.v
 M_DEPS += axi_dacfifo_wr.v
 M_DEPS += axi_dacfifo_rd.v
 M_DEPS += axi_dacfifo.v
-M_DEPS += axi_dacfifo_constr.xdc
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile
index fa9f0c96a..539ba381d 100644
--- a/projects/ad7616_sdz/zc706/Makefile
+++ b/projects/ad7616_sdz/zc706/Makefile
@@ -37,6 +37,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 
diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile
index 2923b2ef6..635cb90be 100644
--- a/projects/ad7616_sdz/zed/Makefile
+++ b/projects/ad7616_sdz/zed/Makefile
@@ -39,6 +39,8 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
 
 

From c6c3622816a9e62c43fb59c8ec150d744bcb4568 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 30 Jun 2016 10:59:29 +0300
Subject: [PATCH 297/972] a10gx: Updated common design adding explicit clock
 frequency and synchronous reset deassertion

---
 projects/common/a10gx/a10gx_system_qsys.tcl | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl
index 751fa002d..b94d2a15e 100644
--- a/projects/common/a10gx/a10gx_system_qsys.tcl
+++ b/projects/common/a10gx/a10gx_system_qsys.tcl
@@ -12,6 +12,9 @@ add_interface sys_clk clock sink
 add_interface sys_rst reset sink
 set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
 set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
+set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
+set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
 
 # memory (int)
 
@@ -97,6 +100,7 @@ set_instance_parameter_value sys_cpu {dcache_numTCDM} {1}
 set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
 set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
 set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
+#set_instance_parameter_value sys_cpu {mmu_enabled} {1}
 
 add_connection sys_clk.clk sys_cpu.clk
 add_connection sys_clk.clk_reset sys_cpu.reset

From d931b2ee64079b7d666baed5bbbf34cf76616978 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Wed, 29 Jun 2016 15:05:44 -0400
Subject: [PATCH 298/972] ad9162 core verilog files

---
 library/axi_ad9162/axi_ad9162.v         | 260 ++++++++++
 library/axi_ad9162/axi_ad9162_channel.v | 630 ++++++++++++++++++++++++
 library/axi_ad9162/axi_ad9162_core.v    | 234 +++++++++
 library/axi_ad9162/axi_ad9162_if.v      | 145 ++++++
 library/axi_ad9162/axi_ad9162_ip.tcl    |  35 ++
 5 files changed, 1304 insertions(+)
 create mode 100644 library/axi_ad9162/axi_ad9162.v
 create mode 100644 library/axi_ad9162/axi_ad9162_channel.v
 create mode 100644 library/axi_ad9162/axi_ad9162_core.v
 create mode 100644 library/axi_ad9162/axi_ad9162_if.v
 create mode 100644 library/axi_ad9162/axi_ad9162_ip.tcl

diff --git a/library/axi_ad9162/axi_ad9162.v b/library/axi_ad9162/axi_ad9162.v
new file mode 100644
index 000000000..0590af546
--- /dev/null
+++ b/library/axi_ad9162/axi_ad9162.v
@@ -0,0 +1,260 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns / 1ps
+
+module axi_ad9162(
+
+    // jesd interface
+    // tx_clk is (line-rate/40)
+    
+    tx_clk,
+    tx_data,
+    
+    // dma interface
+    
+    dac_clk,
+    dac_valid_0,
+    dac_enable_0,
+    dac_ddata_0,
+    dac_dovf,
+    dac_dunf,
+    
+    // axi interface
+    
+    s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awvalid,
+    s_axi_awaddr,
+    s_axi_awprot,
+    s_axi_awready,
+    s_axi_wvalid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wready,
+    s_axi_bvalid,
+    s_axi_bresp,
+    s_axi_bready,
+    s_axi_arvalid,
+    s_axi_araddr,
+    s_axi_arprot,
+    s_axi_arready,
+    s_axi_rvalid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rready);
+    
+    // parameters
+    
+    parameter   ID = 0;
+    parameter   DAC_DATAPATH_DISABLE = 0;
+    
+    // jesd interface
+    // tx_clk is (line-rate/40)
+    
+    input                                     tx_clk;
+    output  [255:0]                           tx_data;
+    
+    // dma interface
+    
+    output                                    dac_clk;
+    output                                    dac_valid_0;
+    output                                    dac_enable_0;
+    input   [255:0]                           dac_ddata_0;
+    input                                     dac_dovf;
+    input                                     dac_dunf;
+    
+    // axi interface
+    
+    input                                     s_axi_aclk;
+    input                                     s_axi_aresetn;
+    input                                     s_axi_awvalid;
+    input   [ 31:0]                           s_axi_awaddr;
+    input   [  2:0]                           s_axi_awprot;
+    output                                    s_axi_awready;
+    input                                     s_axi_wvalid;
+    input   [ 31:0]                           s_axi_wdata;
+    input   [  3:0]                           s_axi_wstrb;
+    output                                    s_axi_wready;
+    output                                    s_axi_bvalid;
+    output  [  1:0]                           s_axi_bresp;
+    input                                     s_axi_bready;
+    input                                     s_axi_arvalid;
+    input   [ 31:0]                           s_axi_araddr;
+    input   [  2:0]                           s_axi_arprot;
+    output                                    s_axi_arready;
+    output                                    s_axi_rvalid;
+    output  [ 31:0]                           s_axi_rdata;
+    output  [  1:0]                           s_axi_rresp;
+    input                                     s_axi_rready;
+    
+    // internal clocks and resets
+    
+    wire                                      dac_rst;
+    wire                                      up_clk;
+    wire                                      up_rstn;
+    
+    // internal signals
+    
+    wire    [255:0]                           tx_data_s;
+    wire    [ 15:0]                           dac_data_0_0_s;
+    wire    [ 15:0]                           dac_data_0_1_s;
+    wire    [ 15:0]                           dac_data_0_2_s;
+    wire    [ 15:0]                           dac_data_0_3_s;
+    wire    [ 15:0]                           dac_data_0_4_s;
+    wire    [ 15:0]                           dac_data_0_5_s;
+    wire    [ 15:0]                           dac_data_0_6_s;
+    wire    [ 15:0]                           dac_data_0_7_s;
+    wire    [ 15:0]                           dac_data_0_8_s;
+    wire    [ 15:0]                           dac_data_0_9_s;
+    wire    [ 15:0]                           dac_data_0_10_s;
+    wire    [ 15:0]                           dac_data_0_11_s;
+    wire    [ 15:0]                           dac_data_0_12_s;
+    wire    [ 15:0]                           dac_data_0_13_s;
+    wire    [ 15:0]                           dac_data_0_14_s;
+    wire    [ 15:0]                           dac_data_0_15_s;
+    wire                                      up_wreq_s;
+    wire    [ 13:0]                           up_waddr_s;
+    wire    [ 31:0]                           up_wdata_s;
+    wire                                      up_wack_s;
+    wire                                      up_rreq_s;
+    wire    [ 13:0]                           up_raddr_s;
+    wire    [ 31:0]                           up_rdata_s;
+    wire                                      up_rack_s;
+    
+    // signal name changes
+    
+    assign up_clk = s_axi_aclk;
+    assign up_rstn = s_axi_aresetn;
+    assign tx_data = tx_data_s;
+    
+    // device interface
+    
+    axi_ad9162_if i_if (
+      .tx_clk (tx_clk),
+      .tx_data (tx_data_s),
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_data_0_0 (dac_data_0_0_s),
+      .dac_data_0_1 (dac_data_0_1_s),
+      .dac_data_0_2 (dac_data_0_2_s),
+      .dac_data_0_3 (dac_data_0_3_s),
+      .dac_data_0_4 (dac_data_0_4_s),
+      .dac_data_0_5 (dac_data_0_5_s),
+      .dac_data_0_6 (dac_data_0_6_s),
+      .dac_data_0_7 (dac_data_0_7_s),
+      .dac_data_0_8 (dac_data_0_8_s),
+      .dac_data_0_9 (dac_data_0_9_s),
+      .dac_data_0_10 (dac_data_0_10_s),
+      .dac_data_0_11 (dac_data_0_11_s),
+      .dac_data_0_12 (dac_data_0_12_s),
+      .dac_data_0_13 (dac_data_0_13_s),
+      .dac_data_0_14 (dac_data_0_14_s),
+      .dac_data_0_15 (dac_data_0_15_s));
+    
+    // core
+    
+    axi_ad9162_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_data_0_0 (dac_data_0_0_s),
+      .dac_data_0_1 (dac_data_0_1_s),
+      .dac_data_0_2 (dac_data_0_2_s),
+      .dac_data_0_3 (dac_data_0_3_s),
+      .dac_data_0_4 (dac_data_0_4_s),
+      .dac_data_0_5 (dac_data_0_5_s),
+      .dac_data_0_6 (dac_data_0_6_s),
+      .dac_data_0_7 (dac_data_0_7_s),
+      .dac_data_0_8 (dac_data_0_8_s),
+      .dac_data_0_9 (dac_data_0_9_s),
+      .dac_data_0_10 (dac_data_0_10_s),
+      .dac_data_0_11 (dac_data_0_11_s),
+      .dac_data_0_12 (dac_data_0_12_s),
+      .dac_data_0_13 (dac_data_0_13_s),
+      .dac_data_0_14 (dac_data_0_14_s),
+      .dac_data_0_15 (dac_data_0_15_s),
+      .dac_valid_0 (dac_valid_0),
+      .dac_enable_0 (dac_enable_0),
+      .dac_ddata_0 (dac_ddata_0),
+      .dac_dovf (dac_dovf),
+      .dac_dunf (dac_dunf),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq_s),
+      .up_waddr (up_waddr_s),
+      .up_wdata (up_wdata_s),
+      .up_wack (up_wack_s),
+      .up_rreq (up_rreq_s),
+      .up_raddr (up_raddr_s),
+      .up_rdata (up_rdata_s),
+      .up_rack (up_rack_s));
+    
+    // up bus interface
+    
+    up_axi i_up_axi (
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_axi_awvalid (s_axi_awvalid),
+      .up_axi_awaddr (s_axi_awaddr),
+      .up_axi_awready (s_axi_awready),
+      .up_axi_wvalid (s_axi_wvalid),
+      .up_axi_wdata (s_axi_wdata),
+      .up_axi_wstrb (s_axi_wstrb),
+      .up_axi_wready (s_axi_wready),
+      .up_axi_bvalid (s_axi_bvalid),
+      .up_axi_bresp (s_axi_bresp),
+      .up_axi_bready (s_axi_bready),
+      .up_axi_arvalid (s_axi_arvalid),
+      .up_axi_araddr (s_axi_araddr),
+      .up_axi_arready (s_axi_arready),
+      .up_axi_rvalid (s_axi_rvalid),
+      .up_axi_rresp (s_axi_rresp),
+      .up_axi_rdata (s_axi_rdata),
+      .up_axi_rready (s_axi_rready),
+      .up_wreq (up_wreq_s),
+      .up_waddr (up_waddr_s),
+      .up_wdata (up_wdata_s),
+      .up_wack (up_wack_s),
+      .up_rreq (up_rreq_s),
+      .up_raddr (up_raddr_s),
+      .up_rdata (up_rdata_s),
+      .up_rack (up_rack_s));
+
+endmodule
+
diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v
new file mode 100644
index 000000000..238107a43
--- /dev/null
+++ b/library/axi_ad9162/axi_ad9162_channel.v
@@ -0,0 +1,630 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns / 1ps
+
+module axi_ad9162_channel(
+
+    // dac interface
+    
+    dac_clk,
+    dac_rst,
+    dac_enable,
+    dac_data,
+    dma_data,
+    
+    // processor interface
+    
+    dac_data_sync,
+    dac_dds_format,
+    
+    // bus interface
+    
+    up_rstn,
+    up_clk,
+    up_wreq,
+    up_waddr,
+    up_wdata,
+    up_wack,
+    up_rreq,
+    up_raddr,
+    up_rdata,
+    up_rack);
+    
+    // parameters
+    
+    parameter CHANNEL_ID = 32'h0;
+    parameter DATAPATH_DISABLE = 0;
+    
+    // dac interface
+    
+    input           dac_clk;
+    input           dac_rst;
+    output          dac_enable;
+    output  [255:0]  dac_data;
+    input   [255:0]  dma_data;
+    
+    // processor interface
+    
+    input           dac_data_sync;
+    input           dac_dds_format;
+    
+    // bus interface
+    
+    input           up_rstn;
+    input           up_clk;
+    input           up_wreq;
+    input   [13:0]  up_waddr;
+    input   [31:0]  up_wdata;
+    output          up_wack;
+    input           up_rreq;
+    input   [13:0]  up_raddr;
+    output  [31:0]  up_rdata;
+    output          up_rack;
+    
+    // internal registers
+    
+    reg              dac_enable = 'd0;
+    reg     [255:0]  dac_data = 'd0;
+    reg     [15: 0]  dac_dds_phase_0_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_0_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_1_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_1_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_2_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_2_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_3_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_3_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_4_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_4_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_5_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_5_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_6_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_6_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_7_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_7_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_8_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_8_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_9_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_9_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_10_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_10_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_11_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_11_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_12_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_12_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_13_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_13_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_14_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_14_1 = 'd0;
+    reg     [15: 0]  dac_dds_phase_15_0 = 'd0;
+    reg     [15: 0]  dac_dds_phase_15_1 = 'd0;
+    reg     [15: 0]  dac_dds_incr_0 = 'd0;
+    reg     [15: 0]  dac_dds_incr_1 = 'd0;
+    reg     [255:0]  dac_dds_data = 'd0;
+    reg     [255:0]  dac_pn7_data = 'd0;
+    reg     [255:0]  dac_pn15_data = 'd0;
+    
+    // internal signals
+    
+    wire    [15: 0]  dac_dds_data_0_s;
+    wire    [15: 0]  dac_dds_data_1_s;
+    wire    [15: 0]  dac_dds_data_2_s;
+    wire    [15: 0]  dac_dds_data_3_s;
+    wire    [15: 0]  dac_dds_data_4_s;
+    wire    [15: 0]  dac_dds_data_5_s;
+    wire    [15: 0]  dac_dds_data_6_s;
+    wire    [15: 0]  dac_dds_data_7_s;
+    wire    [15: 0]  dac_dds_data_8_s;
+    wire    [15: 0]  dac_dds_data_9_s;
+    wire    [15: 0]  dac_dds_data_10_s;
+    wire    [15: 0]  dac_dds_data_11_s;
+    wire    [15: 0]  dac_dds_data_12_s;
+    wire    [15: 0]  dac_dds_data_13_s;
+    wire    [15: 0]  dac_dds_data_14_s;
+    wire    [15: 0]  dac_dds_data_15_s;
+    wire    [15: 0]  dac_dds_scale_1_s;
+    wire    [15: 0]  dac_dds_init_1_s;
+    wire    [15: 0]  dac_dds_incr_1_s;
+    wire    [15: 0]  dac_dds_scale_2_s;
+    wire    [15: 0]  dac_dds_init_2_s;
+    wire    [15: 0]  dac_dds_incr_2_s;
+    wire    [15: 0]  dac_pat_data_1_s;
+    wire    [15: 0]  dac_pat_data_2_s;
+    wire    [ 3: 0]  dac_data_sel_s;
+    wire    [255:0] dac_pn7_data_i_s;
+    wire    [255:0] dac_pn15_data_i_s;
+    wire    [255:0] dac_pn7_data_s;
+    wire    [255:0] dac_pn15_data_s;
+    
+     
+    // PN7 function
+    
+    function [255:0] pn7;
+         input [7:0] din;
+         reg   [255:0] dout;
+         reg   [15:0] dout16;
+         reg   [7:0] din_reg;
+         integer i;
+         integer j;
+         begin
+         din_reg = din;
+           for ( j=0 ; j<16 ; j=j+1)begin
+             for ( i=0 ; i<16 ; i= i+1)begin
+                 din_reg = {din_reg,din_reg[6]^din_reg[5]};
+                 dout16[15-i] = din_reg[0];
+              end
+              dout = {dout16,dout[255:16]};
+           end         
+           pn7 = dout;
+         end
+    endfunction
+    
+    // PN15 function
+    
+    function [255:0] pn15;
+         input [15:0] din;
+         reg   [255:0] dout;
+         reg   [15:0] dout16;
+         reg   [15:0] din_reg;
+         integer i;
+         integer j;
+         begin
+         din_reg = din;
+           for (j=0 ; j<16 ; j=j+1)begin
+             for (i=0 ; i<16 ; i= i+1)begin
+                 din_reg = {din_reg,din_reg[14]^din_reg[13]};
+                 dout16[15-i] = din_reg[0];
+              end
+              dout = {dout16,dout[255:16]};
+           end         
+           pn15 = dout;
+         end
+    endfunction
+    
+    assign dac_pn7_data_i_s  = ~dac_pn7_data;
+    assign dac_pn15_data_i_s = ~dac_pn15_data;
+    
+    assign dac_pn7_data_s    = dac_pn7_data;
+    assign dac_pn15_data_s   = dac_pn15_data;
+    
+     
+    // dac data select
+    
+    always @(posedge dac_clk) begin
+      dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
+      case (dac_data_sel_s)
+        4'h7: dac_data <= dac_pn15_data_s;
+        4'h6: dac_data <= dac_pn7_data_s;
+        4'h5: dac_data <= dac_pn15_data_i_s;
+        4'h4: dac_data <= dac_pn7_data_i_s;
+        4'h3: dac_data <= 256'd0;
+        4'h2: dac_data <= dma_data;
+        4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
+                            dac_pat_data_2_s, dac_pat_data_1_s,
+                            dac_pat_data_2_s, dac_pat_data_1_s,
+                            dac_pat_data_2_s, dac_pat_data_1_s,
+                            dac_pat_data_2_s, dac_pat_data_1_s,
+                            dac_pat_data_2_s, dac_pat_data_1_s,
+                            dac_pat_data_2_s, dac_pat_data_1_s,
+                            dac_pat_data_2_s, dac_pat_data_1_s};
+        default: dac_data <= dac_dds_data;
+      endcase
+    end
+    
+    // pn registers
+    
+    always @(posedge dac_clk) begin
+      if (dac_data_sync == 1'b1) begin
+        dac_pn7_data <= {255{1'd1}};
+        dac_pn15_data <= {255{1'd1}};
+      end else begin
+        dac_pn7_data <= pn7(dac_pn7_data[247:240]);
+        dac_pn15_data <= pn15(dac_pn15_data[255:240]);
+      end
+    end
+    
+    // dds
+    
+    always @(posedge dac_clk) begin
+      if (dac_data_sync == 1'b1) begin
+        dac_dds_phase_0_0 <= dac_dds_init_1_s;
+        dac_dds_phase_0_1 <= dac_dds_init_2_s;
+        dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
+        dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
+        dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
+        dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
+        dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
+        dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
+        dac_dds_phase_4_0 <= dac_dds_phase_3_0 + dac_dds_incr_1_s;
+        dac_dds_phase_4_1 <= dac_dds_phase_3_1 + dac_dds_incr_2_s;
+        dac_dds_phase_5_0 <= dac_dds_phase_4_0 + dac_dds_incr_1_s;
+        dac_dds_phase_5_1 <= dac_dds_phase_4_1 + dac_dds_incr_2_s;
+        dac_dds_phase_6_0 <= dac_dds_phase_5_0 + dac_dds_incr_1_s;
+        dac_dds_phase_6_1 <= dac_dds_phase_5_1 + dac_dds_incr_2_s;
+        dac_dds_phase_7_0 <= dac_dds_phase_6_0 + dac_dds_incr_1_s;
+        dac_dds_phase_7_1 <= dac_dds_phase_6_1 + dac_dds_incr_2_s;
+        dac_dds_phase_8_0 <= dac_dds_phase_7_0 + dac_dds_incr_1_s;
+        dac_dds_phase_8_1 <= dac_dds_phase_7_1 + dac_dds_incr_2_s;
+        dac_dds_phase_9_0 <= dac_dds_phase_8_0 + dac_dds_incr_1_s;
+        dac_dds_phase_9_1 <= dac_dds_phase_8_1 + dac_dds_incr_2_s;
+        dac_dds_phase_10_0 <= dac_dds_phase_9_0 + dac_dds_incr_1_s;
+        dac_dds_phase_10_1 <= dac_dds_phase_9_1 + dac_dds_incr_2_s;
+        dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
+        dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
+        dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
+        dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
+        dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
+        dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
+        dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
+        dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
+        dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
+        dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
+        dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
+        dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
+        dac_dds_data <= 256'd0;
+      end else begin
+        dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
+        dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
+        dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
+        dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
+        dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
+        dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
+        dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
+        dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
+        dac_dds_phase_4_0 <= dac_dds_phase_4_0 + dac_dds_incr_1_s;
+        dac_dds_phase_4_1 <= dac_dds_phase_4_1 + dac_dds_incr_2_s;
+        dac_dds_phase_5_0 <= dac_dds_phase_5_0 + dac_dds_incr_1_s;
+        dac_dds_phase_5_1 <= dac_dds_phase_5_1 + dac_dds_incr_2_s;
+        dac_dds_phase_6_0 <= dac_dds_phase_6_0 + dac_dds_incr_1_s;
+        dac_dds_phase_6_1 <= dac_dds_phase_6_1 + dac_dds_incr_2_s;
+        dac_dds_phase_7_0 <= dac_dds_phase_7_0 + dac_dds_incr_1_s;
+        dac_dds_phase_7_1 <= dac_dds_phase_7_1 + dac_dds_incr_2_s;
+        dac_dds_phase_8_0 <= dac_dds_phase_8_0 + dac_dds_incr_1_s;
+        dac_dds_phase_8_1 <= dac_dds_phase_8_1 + dac_dds_incr_2_s;
+        dac_dds_phase_9_0 <= dac_dds_phase_9_0 + dac_dds_incr_1_s;
+        dac_dds_phase_9_1 <= dac_dds_phase_9_1 + dac_dds_incr_2_s;
+        dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
+        dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
+        dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
+        dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
+        dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
+        dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
+        dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
+        dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
+        dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
+        dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
+        dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_1_s;
+        dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_2_s;
+        dac_dds_incr_0 <= dac_dds_incr_0;
+        dac_dds_incr_1 <= dac_dds_incr_1;
+        dac_dds_data <= { dac_dds_data_15_s, dac_dds_data_14_s,
+                          dac_dds_data_13_s, dac_dds_data_12_s,
+                          dac_dds_data_11_s, dac_dds_data_10_s,
+                          dac_dds_data_9_s, dac_dds_data_8_s,
+                          dac_dds_data_7_s, dac_dds_data_6_s,
+                          dac_dds_data_5_s, dac_dds_data_4_s,
+                          dac_dds_data_3_s, dac_dds_data_2_s,
+                          dac_dds_data_1_s, dac_dds_data_0_s};
+      end
+    end
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_0_s = 16'd0;
+    end else begin
+    ad_dds i_dds_0 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_0_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_0_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_0_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_1_s = 16'd0;
+    end else begin
+    ad_dds i_dds_1 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_1_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_1_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_1_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_2_s = 16'd0;
+    end else begin
+    ad_dds i_dds_2 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_2_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_2_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_2_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_3_s = 16'd0;
+    end else begin
+    ad_dds i_dds_3 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_3_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_3_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_3_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_4_s = 16'd0;
+    end else begin
+    ad_dds i_dds_4 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_4_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_4_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_4_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_5_s = 16'd0;
+    end else begin
+    ad_dds i_dds_5 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_5_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_5_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_5_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_6_s = 16'd0;
+    end else begin
+    ad_dds i_dds_6 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_6_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_6_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_6_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_7_s = 16'd0;
+    end else begin
+    ad_dds i_dds_7 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_7_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_7_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_7_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_8_s = 16'd0;
+    end else begin
+    ad_dds i_dds_8 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_8_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_8_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_8_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_9_s = 16'd0;
+    end else begin
+    ad_dds i_dds_9 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_9_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_9_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_9_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_10_s = 16'd0;
+    end else begin
+    ad_dds i_dds_10 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_10_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_10_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_10_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_11_s = 16'd0;
+    end else begin
+    ad_dds i_dds_11 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_11_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_11_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_11_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_12_s = 16'd0;
+    end else begin
+    ad_dds i_dds_12 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_12_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_12_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_12_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_13_s = 16'd0;
+    end else begin
+    ad_dds i_dds_13 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_13_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_13_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_13_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_14_s = 16'd0;
+    end else begin
+    ad_dds i_dds_14 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_14_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_14_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_14_s));
+    end
+    endgenerate
+    
+    generate
+    if (DATAPATH_DISABLE == 1) begin
+    assign dac_dds_data_15_s = 16'd0;
+    end else begin
+    ad_dds i_dds_15 (
+      .clk (dac_clk),
+      .dds_format (dac_dds_format),
+      .dds_phase_0 (dac_dds_phase_15_0),
+      .dds_scale_0 (dac_dds_scale_1_s),
+      .dds_phase_1 (dac_dds_phase_15_1),
+      .dds_scale_1 (dac_dds_scale_2_s),
+      .dds_data (dac_dds_data_15_s));
+    end
+    endgenerate
+    
+    // single channel processor
+    
+    up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_dds_scale_1 (dac_dds_scale_1_s),
+      .dac_dds_init_1 (dac_dds_init_1_s),
+      .dac_dds_incr_1 (dac_dds_incr_1_s),
+      .dac_dds_scale_2 (dac_dds_scale_2_s),
+      .dac_dds_init_2 (dac_dds_init_2_s),
+      .dac_dds_incr_2 (dac_dds_incr_2_s),
+      .dac_pat_data_1 (dac_pat_data_1_s),
+      .dac_pat_data_2 (dac_pat_data_2_s),
+      .dac_data_sel (dac_data_sel_s),
+      .dac_iqcor_enb (),
+      .dac_iqcor_coeff_1 (),
+      .dac_iqcor_coeff_2 (),
+      .up_usr_datatype_be (),
+      .up_usr_datatype_signed (),
+      .up_usr_datatype_shift (),
+      .up_usr_datatype_total_bits (),
+      .up_usr_datatype_bits (),
+      .up_usr_interpolation_m (),
+      .up_usr_interpolation_n (),
+      .dac_usr_datatype_be (1'b0),
+      .dac_usr_datatype_signed (1'b1),
+      .dac_usr_datatype_shift (8'd0),
+      .dac_usr_datatype_total_bits (8'd16),
+      .dac_usr_datatype_bits (8'd16),
+      .dac_usr_interpolation_m (16'd1),
+      .dac_usr_interpolation_n (16'd1),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata),
+      .up_rack (up_rack));
+
+endmodule
+
diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v
new file mode 100644
index 000000000..87f9620d2
--- /dev/null
+++ b/library/axi_ad9162/axi_ad9162_core.v
@@ -0,0 +1,234 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns / 1ps
+
+module axi_ad9162_core(
+
+    // dac interface
+    
+    dac_clk,
+    dac_rst,
+    dac_data_0_0,
+    dac_data_0_1,
+    dac_data_0_2,
+    dac_data_0_3,
+    dac_data_0_4,
+    dac_data_0_5,
+    dac_data_0_6,
+    dac_data_0_7,
+    dac_data_0_8,
+    dac_data_0_9,
+    dac_data_0_10,
+    dac_data_0_11,
+    dac_data_0_12,
+    dac_data_0_13,
+    dac_data_0_14,
+    dac_data_0_15,
+    
+    // dma interface
+    
+    dac_valid_0,
+    dac_enable_0,
+    dac_ddata_0,
+    dac_dovf,
+    dac_dunf,
+    
+    // processor interface
+    
+    up_rstn,
+    up_clk,
+    up_wreq,
+    up_waddr,
+    up_wdata,
+    up_wack,
+    up_rreq,
+    up_raddr,
+    up_rdata,
+    up_rack);
+    
+    // parameters
+    
+    parameter   ID = 0;
+    parameter   DATAPATH_DISABLE = 0;
+    
+    // dac interface
+    
+    input            dac_clk;
+    output           dac_rst;
+    output  [ 15:0]  dac_data_0_0;
+    output  [ 15:0]  dac_data_0_1;
+    output  [ 15:0]  dac_data_0_2;
+    output  [ 15:0]  dac_data_0_3;
+    output  [ 15:0]  dac_data_0_4;
+    output  [ 15:0]  dac_data_0_5;
+    output  [ 15:0]  dac_data_0_6;
+    output  [ 15:0]  dac_data_0_7;
+    output  [ 15:0]  dac_data_0_8;
+    output  [ 15:0]  dac_data_0_9;
+    output  [ 15:0]  dac_data_0_10;
+    output  [ 15:0]  dac_data_0_11;
+    output  [ 15:0]  dac_data_0_12;
+    output  [ 15:0]  dac_data_0_13;
+    output  [ 15:0]  dac_data_0_14;
+    output  [ 15:0]  dac_data_0_15;
+    
+    // dma interface
+    
+    output           dac_valid_0;
+    output           dac_enable_0;
+    input   [255:0]  dac_ddata_0;
+    input            dac_dovf;
+    input            dac_dunf;
+    
+    
+    // processor interface
+    
+    input            up_rstn;
+    input            up_clk;
+    input            up_wreq;
+    input   [ 13:0]  up_waddr;
+    input   [ 31:0]  up_wdata;
+    output           up_wack;
+    input            up_rreq;
+    input   [ 13:0]  up_raddr;
+    output  [ 31:0]  up_rdata;
+    output           up_rack;
+    
+    // internal registers
+    
+    reg     [ 31:0]  up_rdata = 'd0;
+    reg              up_rack = 'd0;
+    reg              up_wack = 'd0;
+    
+    // internal signals
+    
+    wire             dac_sync_s;
+    wire             dac_datafmt_s;
+    wire    [ 31:0]  up_rdata_0_s;
+    wire             up_rack_0_s;
+    wire             up_wack_0_s;
+    wire    [ 31:0]  up_rdata_s;
+    wire             up_rack_s;
+    wire             up_wack_s;
+    
+    // dac valid
+    
+    assign dac_valid_0 = 1'b1;
+    
+    // processor read interface
+    
+    always @(negedge up_rstn or posedge up_clk) begin
+      if (up_rstn == 0) begin
+        up_rdata <= 'd0;
+        up_rack <= 'd0;
+        up_wack <= 'd0;
+      end else begin
+        up_rdata <= up_rdata_s | up_rdata_0_s;
+        up_rack <= up_rack_s | up_rack_0_s;
+        up_wack <= up_wack_s | up_wack_0_s;
+      end
+    end
+    
+    // dac channel
+    
+    axi_ad9162_channel #(.CHANNEL_ID(0), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 (
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_enable (dac_enable_0),
+      .dac_data ({dac_data_0_15, dac_data_0_14, dac_data_0_13, dac_data_0_12,
+                  dac_data_0_11, dac_data_0_10, dac_data_0_9, dac_data_0_8,
+                  dac_data_0_7, dac_data_0_6, dac_data_0_5, dac_data_0_4,
+                  dac_data_0_3, dac_data_0_2, dac_data_0_1, dac_data_0_0}),
+      .dma_data (dac_ddata_0),
+      .dac_data_sync (dac_sync_s),
+      .dac_dds_format (dac_datafmt_s),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_0_s),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_0_s),
+      .up_rack (up_rack_0_s));
+    
+    
+    // dac common processor interface
+    
+    up_dac_common #(.ID(ID)) i_up_dac_common (
+      .mmcm_rst (),
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_sync (dac_sync_s),
+      .dac_frame (),
+      .dac_par_type (),
+      .dac_par_enb (),
+      .dac_r1_mode (),
+      .dac_datafmt (dac_datafmt_s),
+      .dac_datarate (),
+      .dac_status (1'b1),
+      .dac_status_ovf (dac_dovf),
+      .dac_status_unf (dac_dunf),
+      .dac_clk_ratio (32'd16),
+      .up_drp_sel (),
+      .up_drp_wr (),
+      .up_drp_addr (),
+      .up_drp_wdata (),
+      .up_drp_rdata (16'd0),
+      .up_drp_ready (1'd0),
+      .up_drp_locked (1'd1),
+      .up_usr_chanmax (),
+      .dac_usr_chanmax (8'd0),
+      .up_dac_gpio_in (32'd0),
+      .up_dac_gpio_out (),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s),
+      .up_rack (up_rack_s));
+
+endmodule
+
diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v
new file mode 100644
index 000000000..9727a82f2
--- /dev/null
+++ b/library/axi_ad9162/axi_ad9162_if.v
@@ -0,0 +1,145 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns / 1ps
+
+module axi_ad9162_if(
+
+    // jesd interface
+    // tx_clk is (line-rate/40)
+    
+    tx_clk,
+    tx_data,
+    
+    // dac interface
+    
+    dac_clk,
+    dac_rst,
+    dac_data_0_0,
+    dac_data_0_1,
+    dac_data_0_2,
+    dac_data_0_3,
+    dac_data_0_4,
+    dac_data_0_5,
+    dac_data_0_6,
+    dac_data_0_7,
+    dac_data_0_8,
+    dac_data_0_9,
+    dac_data_0_10,
+    dac_data_0_11,
+    dac_data_0_12,
+    dac_data_0_13,
+    dac_data_0_14,
+    dac_data_0_15);
+    
+    // jesd interface
+    // tx_clk is (line-rate/40)
+    
+    input           tx_clk;
+    output [255:0]  tx_data;
+    
+    // dac interface
+    
+    output          dac_clk;
+    input           dac_rst;
+    input   [15:0]  dac_data_0_0;
+    input   [15:0]  dac_data_0_1;
+    input   [15:0]  dac_data_0_2;
+    input   [15:0]  dac_data_0_3;
+    input   [15:0]  dac_data_0_4;
+    input   [15:0]  dac_data_0_5;
+    input   [15:0]  dac_data_0_6;
+    input   [15:0]  dac_data_0_7;
+    input   [15:0]  dac_data_0_8;
+    input   [15:0]  dac_data_0_9;
+    input   [15:0]  dac_data_0_10;
+    input   [15:0]  dac_data_0_11;
+    input   [15:0]  dac_data_0_12;
+    input   [15:0]  dac_data_0_13;
+    input   [15:0]  dac_data_0_14;
+    input   [15:0]  dac_data_0_15;
+    
+    // internal registers
+    
+    reg    [255:0]  tx_data = 'd0;
+    
+    // reorder data for the jesd links
+    
+    assign dac_clk = tx_clk;
+    
+    always @(posedge dac_clk) begin
+      if (dac_rst == 1'b1) begin
+        tx_data <= 256'd0;
+      end else begin
+        tx_data[255:248] <= dac_data_0_15 [ 7: 0];
+        tx_data[247:240] <= dac_data_0_11 [ 7: 0];
+        tx_data[239:232] <= dac_data_0_7  [ 7: 0];
+        tx_data[231:224] <= dac_data_0_3  [ 7: 0];
+        tx_data[223:216] <= dac_data_0_15 [15: 8];
+        tx_data[215:208] <= dac_data_0_11 [15: 8];
+        tx_data[207:200] <= dac_data_0_7  [15: 8];
+        tx_data[199:192] <= dac_data_0_3  [15: 8];
+        tx_data[191:184] <= dac_data_0_14 [ 7: 0];
+        tx_data[183:176] <= dac_data_0_10 [ 7: 0];
+        tx_data[175:168] <= dac_data_0_6  [ 7: 0];
+        tx_data[167:160] <= dac_data_0_2  [ 7: 0];
+        tx_data[159:152] <= dac_data_0_14 [15: 8];
+        tx_data[151:144] <= dac_data_0_10 [15: 8];
+        tx_data[143:136] <= dac_data_0_6  [15: 8];
+        tx_data[135:128] <= dac_data_0_2  [15: 8];
+        tx_data[127:120] <= dac_data_0_13 [ 7: 0];
+        tx_data[119:112] <= dac_data_0_9  [ 7: 0];
+        tx_data[111:104] <= dac_data_0_5  [ 7: 0];
+        tx_data[103: 96] <= dac_data_0_1  [ 7: 0];
+        tx_data[ 95: 88] <= dac_data_0_13 [15: 8];
+        tx_data[ 87: 80] <= dac_data_0_9  [15: 8];
+        tx_data[ 79: 72] <= dac_data_0_5  [15: 8];
+        tx_data[ 71: 64] <= dac_data_0_1  [15: 8];
+        tx_data[ 63: 56] <= dac_data_0_12 [ 7: 0];
+        tx_data[ 55: 48] <= dac_data_0_8  [ 7: 0];
+        tx_data[ 47: 40] <= dac_data_0_4  [ 7: 0];
+        tx_data[ 39: 32] <= dac_data_0_0  [ 7: 0];
+        tx_data[ 31: 24] <= dac_data_0_12 [15: 8];
+        tx_data[ 23: 16] <= dac_data_0_8  [15: 8];
+        tx_data[ 15:  8] <= dac_data_0_4  [15: 8];
+        tx_data[  7:  0] <= dac_data_0_0  [15: 8];
+      end
+    end
+    
+endmodule
diff --git a/library/axi_ad9162/axi_ad9162_ip.tcl b/library/axi_ad9162/axi_ad9162_ip.tcl
new file mode 100644
index 000000000..7c30478c1
--- /dev/null
+++ b/library/axi_ad9162/axi_ad9162_ip.tcl
@@ -0,0 +1,35 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_ad9162
+adi_ip_files axi_ad9162 [list \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/common/ad_dds_sine.v" \
+  "$ad_hdl_dir/library/common/ad_dds_1.v" \
+  "$ad_hdl_dir/library/common/ad_dds.v" \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_xfer_status.v" \
+  "$ad_hdl_dir/library/common/up_clock_mon.v" \
+  "$ad_hdl_dir/library/common/up_dac_common.v" \
+  "$ad_hdl_dir/library/common/up_dac_channel.v" \
+  "axi_ad9162_channel.v" \
+  "axi_ad9162_core.v" \
+  "axi_ad9162_if.v" \
+  "axi_ad9162.v" ]
+
+adi_ip_properties axi_ad9162
+
+adi_ip_constraints axi_ad9162 [list \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
+
+set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
+
+ipx::save_core [ipx::current_core]
+
+

From ad491ec04a953d3cc448b09e607ffc8e9a52c854 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 30 Jun 2016 13:26:16 -0400
Subject: [PATCH 299/972] updated tcl files after inclusion of ad9162 core

---
 projects/fmcomms11/common/fmcomms11_bd.tcl | 101 ++++++++++-----------
 projects/fmcomms11/zc706/system_bd.tcl     |   4 +-
 2 files changed, 50 insertions(+), 55 deletions(-)

diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index a33f06c09..a69687798 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -15,23 +15,23 @@ create_bd_port -dir O -from 7 -to 0 tx_data_n
 
 # dac peripherals
 
-set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
+set axi_ad9162_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9162:1.0 axi_ad9162_core]
 
-set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd]
-set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
-set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd
+set axi_ad9162_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9162_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9162_jesd
+set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9162_jesd
 
-set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
-set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma
-set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma
-set_property -dict [list CONFIG.ID {1}] $axi_ad9144_dma
-set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma
-set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma
-set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
-set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9144_dma
-set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9144_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9144_dma
+set axi_ad9162_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9162_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9162_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9162_dma
+set_property -dict [list CONFIG.ID {1}] $axi_ad9162_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9162_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9162_dma
+set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9162_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9162_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9162_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9162_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9162_dma
 
 # adc peripherals
 
@@ -173,14 +173,14 @@ ad_connect  axi_fmcomms11_gt/gt_tx_4 util_fmcomms11_gt/gt_tx_4
 ad_connect  axi_fmcomms11_gt/gt_tx_5 util_fmcomms11_gt/gt_tx_5
 ad_connect  axi_fmcomms11_gt/gt_tx_6 util_fmcomms11_gt/gt_tx_6
 ad_connect  axi_fmcomms11_gt/gt_tx_7 util_fmcomms11_gt/gt_tx_7
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_4 axi_ad9144_jesd/gt4_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_5 axi_ad9144_jesd/gt5_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_6 axi_ad9144_jesd/gt6_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_7 axi_ad9144_jesd/gt7_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_0 axi_ad9162_jesd/gt0_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_1 axi_ad9162_jesd/gt1_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_2 axi_ad9162_jesd/gt2_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_3 axi_ad9162_jesd/gt3_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_4 axi_ad9162_jesd/gt4_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_5 axi_ad9162_jesd/gt5_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_6 axi_ad9162_jesd/gt6_tx
+ad_connect  axi_fmcomms11_gt/gt_tx_ip_7 axi_ad9162_jesd/gt7_tx
 
 # connections (dac)
 
@@ -189,26 +189,26 @@ ad_connect  util_fmcomms11_gt/tx_p tx_data_p
 ad_connect  util_fmcomms11_gt/tx_n tx_data_n
 ad_connect  util_fmcomms11_gt/tx_sync tx_sync
 ad_connect  util_fmcomms11_gt/tx_out_clk util_fmcomms11_gt/tx_clk
-ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk
-ad_connect  util_fmcomms11_gt/tx_ip_rst axi_ad9144_jesd/tx_reset
-ad_connect  util_fmcomms11_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done
-ad_connect  util_fmcomms11_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref
-ad_connect  util_fmcomms11_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
-ad_connect  util_fmcomms11_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
-ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9144_core/tx_clk
-ad_connect  util_fmcomms11_gt/tx_data axi_ad9144_core/tx_data
-ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9144_fifo/dac_clk
-ad_connect  axi_ad9144_core/dac_valid_0 axi_ad9144_fifo/dac_valid
-ad_connect  axi_ad9144_core/dac_ddata_0 axi_ad9144_fifo/dac_data
-ad_connect  sys_cpu_clk axi_ad9144_fifo/dma_clk
-ad_connect  sys_cpu_reset axi_ad9144_fifo/dma_rst
-ad_connect  sys_cpu_clk axi_ad9144_dma/m_axis_aclk
-ad_connect  sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
-ad_connect  axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req
-ad_connect  axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready
-ad_connect  axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data
-ad_connect  axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid
-ad_connect  axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
+ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9162_jesd/tx_core_clk
+ad_connect  util_fmcomms11_gt/tx_ip_rst axi_ad9162_jesd/tx_reset
+ad_connect  util_fmcomms11_gt/tx_ip_rst_done axi_ad9162_jesd/tx_reset_done
+ad_connect  util_fmcomms11_gt/tx_ip_sysref axi_ad9162_jesd/tx_sysref
+ad_connect  util_fmcomms11_gt/tx_ip_sync axi_ad9162_jesd/tx_sync
+ad_connect  util_fmcomms11_gt/tx_ip_data axi_ad9162_jesd/tx_tdata
+ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9162_core/tx_clk
+ad_connect  util_fmcomms11_gt/tx_data axi_ad9162_core/tx_data
+ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9162_fifo/dac_clk
+ad_connect  axi_ad9162_core/dac_valid_0 axi_ad9162_fifo/dac_valid
+ad_connect  axi_ad9162_core/dac_ddata_0 axi_ad9162_fifo/dac_data
+ad_connect  sys_cpu_clk axi_ad9162_fifo/dma_clk
+ad_connect  sys_cpu_reset axi_ad9162_fifo/dma_rst
+ad_connect  sys_cpu_clk axi_ad9162_dma/m_axis_aclk
+ad_connect  sys_cpu_resetn axi_ad9162_dma/m_src_axi_aresetn
+ad_connect  axi_ad9162_fifo/dma_xfer_req axi_ad9162_dma/m_axis_xfer_req
+ad_connect  axi_ad9162_fifo/dma_ready axi_ad9162_dma/m_axis_ready
+ad_connect  axi_ad9162_fifo/dma_data axi_ad9162_dma/m_axis_data
+ad_connect  axi_ad9162_fifo/dma_valid axi_ad9162_dma/m_axis_valid
+ad_connect  axi_ad9162_fifo/dma_xfer_last axi_ad9162_dma/m_axis_last
 
 # connections (adc)
 
@@ -244,9 +244,9 @@ ad_connect  axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
 # interconnect (cpu)
 
 ad_cpu_interconnect 0x44A60000 axi_fmcomms11_gt
-ad_cpu_interconnect 0x44A00000 axi_ad9144_core
-ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
-ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
+ad_cpu_interconnect 0x44A00000 axi_ad9162_core
+ad_cpu_interconnect 0x44A90000 axi_ad9162_jesd
+ad_cpu_interconnect 0x7c420000 axi_ad9162_dma
 ad_cpu_interconnect 0x44A10000 axi_ad9625_core
 ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9625_dma
@@ -259,16 +259,11 @@ ad_mem_hp3_interconnect sys_cpu_clk axi_fmcomms11_gt/m_axi
 # interconnect (mem/dac)
 
 ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
-ad_mem_hp1_interconnect sys_cpu_clk axi_ad9144_dma/m_src_axi
+ad_mem_hp1_interconnect sys_cpu_clk axi_ad9162_dma/m_src_axi
 ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
 ad_mem_hp2_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
 
 # interrupts
 
-ad_cpu_interrupt ps-12 mb-12 axi_ad9144_dma/irq
+ad_cpu_interrupt ps-12 mb-12 axi_ad9162_dma/irq
 ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
-
-ad_connect  axi_ad9144_core/dac_ddata_2 GND
-ad_connect  axi_ad9144_core/dac_ddata_3 GND
-
-
diff --git a/projects/fmcomms11/zc706/system_bd.tcl b/projects/fmcomms11/zc706/system_bd.tcl
index 887ffb2d0..619e17fcb 100644
--- a/projects/fmcomms11/zc706/system_bd.tcl
+++ b/projects/fmcomms11/zc706/system_bd.tcl
@@ -3,8 +3,8 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
 source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
 
-p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
-p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 128
+p_sys_dacfifo [current_bd_instance .] axi_ad9162_fifo 256 10
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256
 
 create_bd_port -dir I -type rst sys_rst
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3

From 69a68a99e02b7d8218852f8d48ab0b13cf39d50d Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Fri, 1 Jul 2016 14:11:49 +0300
Subject: [PATCH 300/972] imageon/zed - remove onboard hdmi and update design

---
 projects/imageon/zed/Makefile           |  1 -
 projects/imageon/zed/system_constr.xdc  | 61 +++++++++++++++++++++++++
 projects/imageon/zed/system_project.tcl |  6 +--
 projects/imageon/zed/system_top.v       | 54 +++++-----------------
 4 files changed, 73 insertions(+), 49 deletions(-)

diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile
index 1148228ee..bf3a40c13 100644
--- a/projects/imageon/zed/Makefile
+++ b/projects/imageon/zed/Makefile
@@ -13,7 +13,6 @@ M_DEPS += ../common/imageon_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/imageon/zed/system_constr.xdc b/projects/imageon/zed/system_constr.xdc
index 124112969..d94f1220b 100644
--- a/projects/imageon/zed/system_constr.xdc
+++ b/projects/imageon/zed/system_constr.xdc
@@ -2,6 +2,7 @@
 # fmc hdmi rx (adv7611)
 
 set_property  -dict {PACKAGE_PIN  D18     IOSTANDARD LVCMOS25}                 [get_ports  hdmi_rx_clk]          ; ## G2   FMC_LPC_CLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  A19     IOSTANDARD LVCMOS25}                 [get_ports  hdmi_rx_spdif]        ; ## H29  FMC_LPC_LA24_N
 set_property  -dict {PACKAGE_PIN  A17     IOSTANDARD LVCMOS25     IOB TRUE}    [get_ports  hdmi_rx_data[0]]      ; ## H32  FMC_LPC_LA28_N
 set_property  -dict {PACKAGE_PIN  A16     IOSTANDARD LVCMOS25     IOB TRUE}    [get_ports  hdmi_rx_data[1]]      ; ## H31  FMC_LPC_LA28_P
 set_property  -dict {PACKAGE_PIN  C18     IOSTANDARD LVCMOS25     IOB TRUE}    [get_ports  hdmi_rx_data[2]]      ; ## G31  FMC_LPC_LA29_N
@@ -51,3 +52,63 @@ set_property  -dict {PACKAGE_PIN   N20    IOSTANDARD LVCMOS25}    [get_ports  hd
 
 create_clock -period 6.66667  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
 
+# i2s
+
+set_property  -dict {PACKAGE_PIN  AB2   IOSTANDARD LVCMOS33} [get_ports i2s_mclk]
+set_property  -dict {PACKAGE_PIN  AA6   IOSTANDARD LVCMOS33} [get_ports i2s_bclk]
+set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD LVCMOS33} [get_ports i2s_lrclk]
+set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD LVCMOS33} [get_ports i2s_sdata_out]
+set_property  -dict {PACKAGE_PIN  AA7   IOSTANDARD LVCMOS33} [get_ports i2s_sdata_in]
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  R7    IOSTANDARD LVCMOS33} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD LVCMOS33} [get_ports iic_sda]
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[1]]
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[1]]
+set_property  -dict {PACKAGE_PIN  AB4   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[0]]
+set_property  -dict {PACKAGE_PIN  AB5   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[0]]
+
+# otg
+
+set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD LVCMOS25} [get_ports otg_vbusoc]
+
+# gpio (switches, leds and such)
+
+set_property  -dict {PACKAGE_PIN  P16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]       ; ## BTNC
+set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]       ; ## BTND
+set_property  -dict {PACKAGE_PIN  N15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]       ; ## BTNL
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]       ; ## BTNR
+set_property  -dict {PACKAGE_PIN  T18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]       ; ## BTNU
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]]       ; ## OLED-DC
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]]       ; ## OLED-RES
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVCMOS33} [get_ports gpio_bd[7]]       ; ## OLED-SCLK
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS33} [get_ports gpio_bd[8]]       ; ## OLED-SDIN
+set_property  -dict {PACKAGE_PIN  U11   IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]]       ; ## OLED-VBAT
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]]      ; ## OLED-VDD
+
+set_property  -dict {PACKAGE_PIN  F22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]      ; ## SW0
+set_property  -dict {PACKAGE_PIN  G22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]]      ; ## SW1
+set_property  -dict {PACKAGE_PIN  H22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]]      ; ## SW2
+set_property  -dict {PACKAGE_PIN  F21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]]      ; ## SW3
+set_property  -dict {PACKAGE_PIN  H19   IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]]      ; ## SW4
+set_property  -dict {PACKAGE_PIN  H18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]]      ; ## SW5
+set_property  -dict {PACKAGE_PIN  H17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]]      ; ## SW6
+set_property  -dict {PACKAGE_PIN  M15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]]      ; ## SW7
+
+set_property  -dict {PACKAGE_PIN  T22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[19]]      ; ## LD0
+set_property  -dict {PACKAGE_PIN  T21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[20]]      ; ## LD1
+set_property  -dict {PACKAGE_PIN  U22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[21]]      ; ## LD2
+set_property  -dict {PACKAGE_PIN  U21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[22]]      ; ## LD3
+set_property  -dict {PACKAGE_PIN  V22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[23]]      ; ## LD4
+set_property  -dict {PACKAGE_PIN  W22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[24]]      ; ## LD5
+set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD LVCMOS33} [get_ports gpio_bd[25]]      ; ## LD6
+set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD LVCMOS33} [get_ports gpio_bd[26]]      ; ## LD7
+
+set_property  -dict {PACKAGE_PIN  H15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[27]]      ; ## XADC-GIO0
+set_property  -dict {PACKAGE_PIN  R15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[28]]      ; ## XADC-GIO1
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[29]]      ; ## XADC-GIO2
+set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[30]]      ; ## XADC-GIO3
+
+set_property  -dict {PACKAGE_PIN  G17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[31]]      ; ## OTG-RESETN
+
diff --git a/projects/imageon/zed/system_project.tcl b/projects/imageon/zed/system_project.tcl
index b33d46487..a8cb06bc1 100644
--- a/projects/imageon/zed/system_project.tcl
+++ b/projects/imageon/zed/system_project.tcl
@@ -8,11 +8,7 @@ adi_project_create imageon_zed
 adi_project_files imageon_zed [list \
   "system_top.v" \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zed/zed_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+  "system_constr.xdc"]
 
 adi_project_run imageon_zed
 
diff --git a/projects/imageon/zed/system_top.v b/projects/imageon/zed/system_top.v
index 80b6e87b0..41c79230c 100644
--- a/projects/imageon/zed/system_top.v
+++ b/projects/imageon/zed/system_top.v
@@ -66,20 +66,12 @@ module system_top (
 
   gpio_bd,
 
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
-
   i2s_mclk,
   i2s_bclk,
   i2s_lrclk,
   i2s_sdata_out,
   i2s_sdata_in,
 
-  spdif,
-
   iic_scl,
   iic_sda,
   iic_mux_scl,
@@ -88,6 +80,7 @@ module system_top (
   hdmi_rx_clk,
   hdmi_rx_data,
   hdmi_rx_int,
+  hdmi_rx_spdif,
 
   hdmi_tx_clk,
   hdmi_tx_data,
@@ -124,14 +117,6 @@ module system_top (
 
   inout   [31:0]  gpio_bd;
 
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [15:0]  hdmi_data;
-
-  output          spdif;
-
   output          i2s_mclk;
   output          i2s_bclk;
   output          i2s_lrclk;
@@ -147,6 +132,7 @@ module system_top (
   input           hdmi_rx_clk;
   input   [15:0]  hdmi_rx_data;
   inout           hdmi_rx_int;
+  input           hdmi_rx_spdif;
 
   output          hdmi_tx_clk;
   output  [15:0]  hdmi_tx_data;
@@ -170,28 +156,13 @@ module system_top (
   wire    [ 1:0]  iic_mux_sda_o_s;
   wire            iic_mux_sda_t_s;
 
-  // base hdmi
-
-  assign hdmi_out_clk = 1'd0;
-  assign hdmi_vsync = 1'd0;
-  assign hdmi_hsync = 1'd0;
-  assign hdmi_data_e = 1'd0;
-  assign hdmi_data = 24'd0;
-  assign spdif = 1'd0;
-
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi_iic_rstn (
-    .dio_t (gpio_t[33]),
-    .dio_i (gpio_o[33]),
-    .dio_o (gpio_i[33]),
-    .dio_p (hdmi_iic_rstn));
-
-  ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi (
-    .dio_t (gpio_t[32]),
-    .dio_i (gpio_o[32]),
-    .dio_o (gpio_i[32]),
-    .dio_p (hdmi_rx_int));
+  ad_iobuf #(.DATA_WIDTH(2)) i_gpio (
+    .dio_t (gpio_t[33:32]),
+    .dio_i (gpio_o[33:32]),
+    .dio_o (gpio_i[33:32]),
+    .dio_p ({hdmi_iic_rstn, hdmi_rx_int}));
 
   ad_iobuf #(
     .DATA_WIDTH(32)
@@ -242,14 +213,10 @@ module system_top (
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .hdmi_data (),
-    .hdmi_data_e (),
-    .hdmi_es_data (hdmi_tx_data),
-    .hdmi_hsync (),
-    .hdmi_out_clk (hdmi_tx_clk),
     .hdmi_rx_clk (hdmi_rx_clk),
     .hdmi_rx_data (hdmi_rx_data),
-    .hdmi_vsync (),
+    .hdmi_tx_clk (hdmi_tx_clk),
+    .hdmi_tx_data (hdmi_tx_data),
     .iic_imageon_scl_io (hdmi_iic_scl),
     .iic_imageon_sda_io (hdmi_iic_sda),
     .i2s_bclk (i2s_bclk),
@@ -278,7 +245,8 @@ module system_top (
     .ps_intr_10 (1'b0),
     .ps_intr_13 (1'b0),
     .otg_vbusoc (otg_vbusoc),
-    .spdif (hdmi_tx_spdif),
+    .spdif_rx (hdmi_rx_spdif),
+    .spdif_tx (hdmi_tx_spdif),
     .spi0_clk_i (1'b0),
     .spi0_clk_o (),
     .spi0_csn_0_o (),

From 427cc84bb27b35001457734ea13b9489b5aa1def Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 1 Jul 2016 11:12:00 +0300
Subject: [PATCH 301/972] axi_ad7616: Rename the physical interface signals to
 rx_*

No functional modification.
---
 library/axi_ad7616/axi_ad7616.v           | 91 +++++++++++------------
 projects/ad7616_sdz/common/ad7616_bd.tcl  | 54 +++++++-------
 projects/ad7616_sdz/zc706/system_top_pi.v | 16 ++--
 projects/ad7616_sdz/zc706/system_top_si.v | 14 ++--
 projects/ad7616_sdz/zed/system_top_pi.v   | 16 ++--
 projects/ad7616_sdz/zed/system_top_si.v   | 14 ++--
 6 files changed, 101 insertions(+), 104 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index a1ee5fa93..97da48a65 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -43,22 +43,22 @@ module axi_ad7616 (
 
   // physical data interface
 
-  sclk,
-  cs_n,
-  sdo,
-  sdi_0,
-  sdi_1,
+  rx_sclk,
+  rx_cs_n,
+  rx_sdo,
+  rx_sdi_0,
+  rx_sdi_1,
 
-  db_o,
-  db_i,
-  db_t,
-  rd_n,
-  wr_n,
+  rx_db_o,
+  rx_db_i,
+  rx_db_t,
+  rx_rd_n,
+  rx_wr_n,
 
   // physical control interface
 
-  cnvst,
-  busy,
+  rx_cnvst,
+  rx_busy,
 
   // AXI Slave Memory Map
 
@@ -106,20 +106,20 @@ module axi_ad7616 (
 
   // IO definitions
 
-  output                            sclk;
-  output                            cs_n;
-  output                            sdo;
-  input                             sdi_0;
-  input                             sdi_1;
+  output                            rx_sclk;
+  output                            rx_cs_n;
+  output                            rx_sdo;
+  input                             rx_sdi_0;
+  input                             rx_sdi_1;
 
-  output  [15:0]                    db_o;
-  input   [15:0]                    db_i;
-  output                            db_t;
-  output                            rd_n;
-  output                            wr_n;
+  output  [15:0]                    rx_db_o;
+  input   [15:0]                    rx_db_i;
+  output                            rx_db_t;
+  output                            rx_rd_n;
+  output                            rx_wr_n;
 
-  output                            cnvst;
-  input                             busy;
+  output                            rx_cnvst;
+  input                             rx_busy;
 
   input                             s_axi_aclk;
   input                             s_axi_aresetn;
@@ -183,7 +183,6 @@ module axi_ad7616 (
   wire                              m_axis_valid_s;
   wire    [15:0]                    m_axis_data_s;
   wire                              m_axis_xfer_req_s;
-  wire    [15:0]                    adc_data_s;
 
   // defaults
 
@@ -209,9 +208,9 @@ module axi_ad7616 (
 
     // ground all parallel interface signals
 
-    assign db_o = 16'b0;
-    assign rd_n = 1'b0;
-    assign wr_n = 1'b0;
+    assign rx_db_o = 16'b0;
+    assign rx_rd_n = 1'b0;
+    assign rx_wr_n = 1'b0;
 
     // SPI Framework instances and logic
 
@@ -393,14 +392,14 @@ module axi_ad7616 (
       .sync_ready (m_sync_ready_s),
       .sync_valid (m_sync_valid_s),
       .sync (m_sync_s),
-      .sclk (sclk),
-      .sdo (sdo),
+      .sclk (rx_sclk),
+      .sdo (rx_sdo),
       .sdo_t (),
-      .sdi (sdi_0),
-      .sdi_1 (sdi_1),
+      .sdi (rx_sdi_0),
+      .sdi_1 (rx_sdi_1),
       .sdi_2 (1'b0),
       .sdi_3 (1'b0),
-      .cs (cs_n),
+      .cs (rx_cs_n),
       .three_wire ());
 
     axi_ad7616_maxis2wrfifo #(
@@ -413,7 +412,7 @@ module axi_ad7616 (
       .m_axis_ready(m_axis_ready_s),
       .m_axis_valid(m_axis_valid_s),
       .fifo_wr_en(adc_valid),
-      .fifo_wr_data(adc_data_s),
+      .fifo_wr_data(adc_data),
       .fifo_wr_sync(adc_sync)
     );
 
@@ -422,8 +421,8 @@ module axi_ad7616 (
 
   generate if (IF_TYPE == PARALLEL) begin
 
-    assign sclk = 1'h0;
-    assign sdo = 1'h0;
+    assign rx_sclk = 1'h0;
+    assign rx_sdo = 1'h0;
     assign irq = 1'h0;
 
     assign up_wack_if_s = 1'h0;
@@ -431,13 +430,13 @@ module axi_ad7616 (
     assign up_rdata_if_s = 1'h0;
 
     axi_ad7616_pif i_ad7616_parallel_interface (
-      .cs_n (cs_n),
-      .db_o (db_o),
-      .db_i (db_i),
-      .db_t (db_t),
-      .rd_n (rd_n),
-      .wr_n (wr_n),
-      .adc_data (adc_data_s),
+      .cs_n (rx_cs_n),
+      .db_o (rx_db_o),
+      .db_i (rx_db_i),
+      .db_t (rx_db_t),
+      .rd_n (rx_rd_n),
+      .wr_n (rx_wr_n),
+      .adc_data (adc_data),
       .adc_valid (adc_valid),
       .adc_sync (adc_sync),
       .end_of_conv (trigger_s),
@@ -458,8 +457,8 @@ module axi_ad7616 (
     .ID(ID),
     .IF_TYPE(IF_TYPE)
   ) i_ad7616_control (
-    .cnvst (cnvst),
-    .busy (busy),
+    .cnvst (rx_cnvst),
+    .busy (rx_busy),
     .up_burst_length (burst_length_s),
     .up_read_data (rd_data_s),
     .up_read_valid (rd_valid_s),
@@ -478,8 +477,6 @@ module axi_ad7616 (
     .up_rdata (up_rdata_cntrl_s),
     .up_rack (up_rack_cntrl_s));
 
-  assign adc_data = adc_data_s;
-
   // up bus interface
 
   up_axi #(
diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index 71537e87b..e61e1da78 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -3,22 +3,22 @@ global ad7616_if
 
 # data interfaces
 
-create_bd_port -dir O sclk
-create_bd_port -dir O sdo
-create_bd_port -dir I sdi_0
-create_bd_port -dir I sdi_1
+create_bd_port -dir O rx_sclk
+create_bd_port -dir O rx_sdo
+create_bd_port -dir I rx_sdi_0
+create_bd_port -dir I rx_sdi_1
 
-create_bd_port -dir O -from 15 -to 0 db_o
-create_bd_port -dir I -from 15 -to 0 db_i
-create_bd_port -dir O db_t
-create_bd_port -dir O rd_n
-create_bd_port -dir O wr_n
+create_bd_port -dir O -from 15 -to 0 rx_db_o
+create_bd_port -dir I -from 15 -to 0 rx_db_i
+create_bd_port -dir O rx_db_t
+create_bd_port -dir O rx_rd_n
+create_bd_port -dir O rx_wr_n
 
 # control lines
 
-create_bd_port -dir O cnvst
-create_bd_port -dir O cs_n
-create_bd_port -dir I busy
+create_bd_port -dir O rx_cnvst
+create_bd_port -dir O rx_cs_n
+create_bd_port -dir I rx_busy
 
 # instantiation
 
@@ -36,26 +36,26 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad7616_dma
 # interface connections
 if {$ad7616_if == 0} {
 
-  ad_connect  sclk axi_ad7616/sclk
-  ad_connect  sdo axi_ad7616/sdo
-  ad_connect  sdi_0 axi_ad7616/sdi_0
-  ad_connect  sdi_1 axi_ad7616/sdi_1
-  ad_connect  cs_n axi_ad7616/cs_n
+  ad_connect  rx_sclk axi_ad7616/rx_sclk
+  ad_connect  rx_sdo axi_ad7616/rx_sdo
+  ad_connect  rx_sdi_0 axi_ad7616/rx_sdi_0
+  ad_connect  rx_sdi_1 axi_ad7616/rx_sdi_1
+  ad_connect  rx_cs_n axi_ad7616/rx_cs_n
 
-  ad_connect  cnvst axi_ad7616/cnvst
-  ad_connect  busy axi_ad7616/busy
+  ad_connect  rx_cnvst axi_ad7616/rx_cnvst
+  ad_connect  rx_busy axi_ad7616/rx_busy
 
 } else {
 
-  ad_connect  db_o axi_ad7616/db_o
-  ad_connect  db_i axi_ad7616/db_i
-  ad_connect  db_t axi_ad7616/db_t
-  ad_connect  rd_n axi_ad7616/rd_n
-  ad_connect  wr_n axi_ad7616/wr_n
+  ad_connect  rx_db_o axi_ad7616/rx_db_o
+  ad_connect  rx_db_i axi_ad7616/rx_db_i
+  ad_connect  rx_db_t axi_ad7616/rx_db_t
+  ad_connect  rx_rd_n axi_ad7616/rx_rd_n
+  ad_connect  rx_wr_n axi_ad7616/rx_wr_n
 
-  ad_connect  cs_n axi_ad7616/cs_n
-  ad_connect  cnvst axi_ad7616/cnvst
-  ad_connect  busy axi_ad7616/busy
+  ad_connect  rx_cs_n axi_ad7616/rx_cs_n
+  ad_connect  rx_cnvst axi_ad7616/rx_cnvst
+  ad_connect  rx_busy axi_ad7616/rx_busy
 
 }
 
diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v
index 3a1800ef5..3abb0fbef 100644
--- a/projects/ad7616_sdz/zc706/system_top_pi.v
+++ b/projects/ad7616_sdz/zc706/system_top_pi.v
@@ -223,14 +223,14 @@ module system_top (
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
     .spdif (spdif),
-    .cnvst (adc_convst),
-    .cs_n (adc_cs_n),
-    .busy (adc_busy),
-    .db_o (adc_db_o),
-    .db_i (adc_db_i),
-    .db_t (adc_db_t),
-    .rd_n (adc_rd_n),
-    .wr_n (adc_wr_n)
+    .rx_cnvst (adc_convst),
+    .rx_cs_n (adc_cs_n),
+    .rx_busy (adc_busy),
+    .rx_db_o (adc_db_o),
+    .rx_db_i (adc_db_i),
+    .rx_db_t (adc_db_t),
+    .rx_rd_n (adc_rd_n),
+    .rx_wr_n (adc_wr_n)
   );
 
 endmodule
diff --git a/projects/ad7616_sdz/zc706/system_top_si.v b/projects/ad7616_sdz/zc706/system_top_si.v
index a16b522d8..fef99aef4 100644
--- a/projects/ad7616_sdz/zc706/system_top_si.v
+++ b/projects/ad7616_sdz/zc706/system_top_si.v
@@ -218,13 +218,13 @@ module system_top (
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
     .spdif (spdif),
-    .sclk (spi_sclk),
-    .sdo (spi_sdo),
-    .sdi_0 (spi_sdi_0),
-    .sdi_1 (spi_sdi_1),
-    .cnvst (adc_convst),
-    .cs_n (spi_cs_n),
-    .busy (adc_busy));
+    .rx_sclk (spi_sclk),
+    .rx_sdo (spi_sdo),
+    .rx_sdi_0 (spi_sdi_0),
+    .rx_sdi_1 (spi_sdi_1),
+    .rx_cnvst (adc_convst),
+    .rx_cs_n (spi_cs_n),
+    .rx_busy (adc_busy));
 
 endmodule
 
diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v
index f085ca86c..0a21783d3 100644
--- a/projects/ad7616_sdz/zed/system_top_pi.v
+++ b/projects/ad7616_sdz/zed/system_top_pi.v
@@ -277,14 +277,14 @@ module system_top (
     .ps_intr_10 (1'b0),
     .otg_vbusoc (otg_vbusoc),
     .spdif (spdif),
-    .cnvst (adc_convst),
-    .cs_n (adc_cs_n),
-    .busy (adc_busy),
-    .db_o (adc_db_o),
-    .db_i (adc_db_i),
-    .db_t (adc_db_t),
-    .rd_n (adc_rd_n),
-    .wr_n (adc_wr_n)
+    .rx_cnvst (adc_convst),
+    .rx_cs_n (adc_cs_n),
+    .rx_busy (adc_busy),
+    .rx_db_o (adc_db_o),
+    .rx_db_i (adc_db_i),
+    .rx_db_t (adc_db_t),
+    .rx_rd_n (adc_rd_n),
+    .rx_wr_n (adc_wr_n)
   );
 
 endmodule
diff --git a/projects/ad7616_sdz/zed/system_top_si.v b/projects/ad7616_sdz/zed/system_top_si.v
index 25406e7ae..312baad48 100644
--- a/projects/ad7616_sdz/zed/system_top_si.v
+++ b/projects/ad7616_sdz/zed/system_top_si.v
@@ -272,13 +272,13 @@ module system_top (
     .ps_intr_10 (1'b0),
     .otg_vbusoc (otg_vbusoc),
     .spdif (spdif),
-    .cnvst (adc_convst),
-    .sclk (spi_sclk),
-    .sdo (spi_sdo),
-    .sdi_0 (spi_sdi_0),
-    .sdi_1 (spi_sdi_1),
-    .cs_n (spi_cs_n),
-    .busy (adc_busy)
+    .rx_cnvst (adc_convst),
+    .rx_sclk (spi_sclk),
+    .rx_sdo (spi_sdo),
+    .rx_sdi_0 (spi_sdi_0),
+    .rx_sdi_1 (spi_sdi_1),
+    .rx_cs_n (spi_cs_n),
+    .rx_busy (adc_busy)
   );
 
 endmodule

From 48762519b5913a81d361c818b00a9f547d17cb0d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 6 Jul 2016 15:02:00 -0400
Subject: [PATCH 302/972] make updates

---
 library/Makefile                  |  4 ++
 library/axi_ad9162/Makefile       | 61 +++++++++++++++++++++++++++++++
 library/interfaces/Makefile       | 18 ++++++++-
 library/util_adxcvr/Makefile      | 54 +++++++++++++++++++++++++++
 projects/Makefile                 |  6 +--
 projects/fmcomms11/zc706/Makefile |  6 +--
 projects/fmcomms2/Makefile        |  3 --
 7 files changed, 142 insertions(+), 10 deletions(-)
 create mode 100644 library/axi_ad9162/Makefile
 create mode 100644 library/util_adxcvr/Makefile

diff --git a/library/Makefile b/library/Makefile
index 6c9c46f35..80ad4558c 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -15,6 +15,7 @@ clean:
 	make -C axi_ad9122 clean
 	make -C axi_ad9144 clean
 	make -C axi_ad9152 clean
+	make -C axi_ad9162 clean
 	make -C axi_ad9234 clean
 	make -C axi_ad9250 clean
 	make -C axi_ad9265 clean
@@ -55,6 +56,7 @@ clean:
 	make -C spi_engine/spi_engine_offload clean
 	make -C util_adc_pack clean
 	make -C util_adcfifo clean
+	make -C util_adxcvr clean
 	make -C util_axis_fifo clean
 	make -C util_axis_resize clean
 	make -C util_bsplit clean
@@ -85,6 +87,7 @@ lib:
 	-make -C axi_ad9122
 	-make -C axi_ad9144
 	-make -C axi_ad9152
+	-make -C axi_ad9162
 	-make -C axi_ad9234
 	-make -C axi_ad9250
 	-make -C axi_ad9265
@@ -125,6 +128,7 @@ lib:
 	-make -C spi_engine/spi_engine_offload
 	-make -C util_adc_pack
 	-make -C util_adcfifo
+	-make -C util_adxcvr
 	-make -C util_axis_fifo
 	-make -C util_axis_resize
 	-make -C util_bsplit
diff --git a/library/axi_ad9162/Makefile b/library/axi_ad9162/Makefile
new file mode 100644
index 000000000..cb4a9469b
--- /dev/null
+++ b/library/axi_ad9162/Makefile
@@ -0,0 +1,61 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := axi_ad9162_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../common/ad_mul.v
+M_DEPS += ../common/ad_dds_sine.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_common.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += axi_ad9162_channel.v
+M_DEPS += axi_ad9162_core.v
+M_DEPS += axi_ad9162_if.v
+M_DEPS += axi_ad9162.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_ad9162.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_ad9162.xpr: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_ad9162_ip.tcl  >> axi_ad9162_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/interfaces/Makefile b/library/interfaces/Makefile
index 996cec8d9..e7165b29f 100644
--- a/library/interfaces/Makefile
+++ b/library/interfaces/Makefile
@@ -13,6 +13,10 @@ M_VIVADO := vivado -mode batch -source
 
 M_FLIST := *.log
 M_FLIST += *.jou
+M_FLIST += if_xcvr_cm.xml
+M_FLIST += if_xcvr_cm_rtl.xml
+M_FLIST += if_xcvr_ch.xml
+M_FLIST += if_xcvr_ch_rtl.xml
 M_FLIST += if_gt_qpll.xml
 M_FLIST += if_gt_qpll_rtl.xml
 M_FLIST += if_gt_pll.xml
@@ -26,13 +30,25 @@ M_FLIST += if_gt_rx_ksig_rtl.xml
 
 
 .PHONY: all clean clean-all
-all: if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml 
+all: if_xcvr_cm.xml if_xcvr_cm_rtl.xml if_xcvr_ch.xml if_xcvr_ch_rtl.xml if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml 
 
 clean:clean-all
 
 clean-all:
 	rm -rf $(M_FLIST)
 
+if_xcvr_cm.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_xcvr_cm_rtl.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_xcvr_ch.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+if_xcvr_ch_rtl.xml:
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
 if_gt_qpll.xml:
 	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
 
diff --git a/library/util_adxcvr/Makefile b/library/util_adxcvr/Makefile
new file mode 100644
index 000000000..9c322fe6b
--- /dev/null
+++ b/library/util_adxcvr/Makefile
@@ -0,0 +1,54 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := util_adxcvr_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += util_adxcvr_xcm.v
+M_DEPS += util_adxcvr_xch.v
+M_DEPS += util_adxcvr.v
+M_DEPS += ../interfaces/if_xcvr_cm.xml
+M_DEPS += ../interfaces/if_xcvr_cm_rtl.xml
+M_DEPS += ../interfaces/if_xcvr_ch.xml
+M_DEPS += ../interfaces/if_xcvr_ch_rtl.xml
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all dep clean clean-all
+all: dep util_adxcvr.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+util_adxcvr.xpr: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) util_adxcvr_ip.tcl  >> util_adxcvr_ip.log 2>&1
+
+dep:
+	make -C ../interfaces
+####################################################################################
+####################################################################################
diff --git a/projects/Makefile b/projects/Makefile
index 148d20ef3..5a24b647e 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -8,8 +8,8 @@
 .PHONY: all clean clean_all
 all:
 	-make -C ad6676evb all
-	-make -C ad7768evb all
 	-make -C ad7616_sdz all
+	-make -C ad7768evb all
 	-make -C ad9265_fmc all
 	-make -C ad9434_fmc all
 	-make -C ad9467_fmc all
@@ -44,8 +44,8 @@ all:
 
 clean:
 	make -C ad6676evb clean
-	make -C ad7768evb clean
 	make -C ad7616_sdz clean
+	make -C ad7768evb clean
 	make -C ad9265_fmc clean
 	make -C ad9434_fmc clean
 	make -C ad9467_fmc clean
@@ -80,8 +80,8 @@ clean:
 
 clean-all:
 	make -C ad6676evb clean-all
-	make -C ad7768evb clean-all
 	make -C ad7616_sdz clean-all
+	make -C ad7768evb clean-all
 	make -C ad9265_fmc clean-all
 	make -C ad9434_fmc clean-all
 	make -C ad9467_fmc clean-all
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index c9331f515..72b3b1c6b 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -21,7 +21,7 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
+M_DEPS += ../../../library/axi_ad9162/axi_ad9162.xpr
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
@@ -59,7 +59,7 @@ clean:
 
 
 clean-all:clean
-	make -C ../../../library/axi_ad9144 clean
+	make -C ../../../library/axi_ad9162 clean
 	make -C ../../../library/axi_ad9625 clean
 	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
@@ -78,7 +78,7 @@ fmcomms11_zc706.sdk/system_top.hdf: $(M_DEPS)
 
 
 lib:
-	make -C ../../../library/axi_ad9144
+	make -C ../../../library/axi_ad9162
 	make -C ../../../library/axi_ad9625
 	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
diff --git a/projects/fmcomms2/Makefile b/projects/fmcomms2/Makefile
index 297dc87af..895391c8a 100644
--- a/projects/fmcomms2/Makefile
+++ b/projects/fmcomms2/Makefile
@@ -7,7 +7,6 @@
 
 .PHONY: all clean clean-all 
 all:
-	-make -C a10soc all
 	-make -C ac701 all
 	-make -C kc705 all
 	-make -C mitx045 all
@@ -19,7 +18,6 @@ all:
 
 
 clean: 
-	make -C a10soc clean
 	make -C ac701 clean
 	make -C kc705 clean
 	make -C mitx045 clean
@@ -31,7 +29,6 @@ clean:
 
 
 clean-all:
-	make -C a10soc clean-all
 	make -C ac701 clean-all
 	make -C kc705 clean-all
 	make -C mitx045 clean-all

From 9169e20b5ea6b673a9d65146e7d405a731c49d2f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 6 Jul 2016 09:16:18 +0300
Subject: [PATCH 303/972] daq1: Fix the data width on the DMAC interfaces

+ HP ports maximum width is 64 bits
+ DMAC's default width is 64, no need for redefinition
---
 projects/daq1/common/daq1_bd.tcl | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl
index 74b8ad4f9..350d0b17e 100644
--- a/projects/daq1/common/daq1_bd.tcl
+++ b/projects/daq1/common/daq1_bd.tcl
@@ -34,7 +34,6 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9122_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9122_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma
 set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9122_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma
 
 set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122]
@@ -55,8 +54,6 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9684_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9684_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9684_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9684_dma
 
 set util_cpack_ad9684 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9684]
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_cpack_ad9684

From 7be017baa3237b6cc78f3b693ee366058332a808 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 6 Jul 2016 09:20:57 +0300
Subject: [PATCH 304/972] daq1: Add AXI PLDDR FIFO to the receive path

The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
---
 projects/daq1/common/daq1_bd.tcl       | 20 ++++++---
 projects/daq1/zc706/Makefile           |  6 +++
 projects/daq1/zc706/system_bd.tcl      | 19 ++++++++
 projects/daq1/zc706/system_project.tcl |  8 +++-
 projects/daq1/zc706/system_top.v       | 61 +++++++++++++++++++++++++-
 5 files changed, 105 insertions(+), 9 deletions(-)

diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl
index 350d0b17e..8af27fc59 100644
--- a/projects/daq1/common/daq1_bd.tcl
+++ b/projects/daq1/common/daq1_bd.tcl
@@ -46,13 +46,14 @@ set axi_ad9684_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9684:1.
 set_property -dict [list CONFIG.OR_STATUS {0}] $axi_ad9684_core
 
 set axi_ad9684_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9684_dma]
-set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9684_dma
+set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9684_dma
 set_property -dict [list CONFIG.ID {1}] $axi_ad9684_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9684_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9684_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9684_dma
+set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9684_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9684_dma
 
 set util_cpack_ad9684 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9684]
@@ -90,7 +91,7 @@ ad_connect  util_upack_ad9122/dac_sync axi_ad9122_core/dac_sync_in
 
 ad_connect  adc_clk axi_ad9684_core/adc_clk
 ad_connect  sys_200m_clk axi_ad9684_core/delay_clk
-ad_connect  adc_clk axi_ad9684_dma/fifo_wr_clk
+ad_connect  sys_cpu_clk axi_ad9684_dma/s_axis_aclk
 ad_connect  adc_clk util_cpack_ad9684/adc_clk
 
 ad_connect  adc_clk_in_p axi_ad9684_core/adc_clk_in_p
@@ -107,11 +108,18 @@ ad_connect  axi_ad9684_core/adc_data_0 util_cpack_ad9684/adc_data_0
 ad_connect  axi_ad9684_core/adc_enable_1 util_cpack_ad9684/adc_enable_1
 ad_connect  axi_ad9684_core/adc_valid_1 util_cpack_ad9684/adc_valid_1
 ad_connect  axi_ad9684_core/adc_data_1 util_cpack_ad9684/adc_data_1
-ad_connect  axi_ad9684_core/adc_dovf axi_ad9684_dma/fifo_wr_overflow
+ad_connect  axi_ad9684_core/adc_dovf axi_ad9684_fifo/adc_wovf
+
+ad_connect  adc_clk axi_ad9684_fifo/adc_clk
+ad_connect  sys_cpu_clk axi_ad9684_fifo/dma_clk
+ad_connect  axi_ad9684_core/adc_rst axi_ad9684_fifo/adc_rst
+ad_connect  util_cpack_ad9684/adc_valid axi_ad9684_fifo/adc_wr
+ad_connect  util_cpack_ad9684/adc_data axi_ad9684_fifo/adc_wdata
+ad_connect  axi_ad9684_fifo/dma_wr axi_ad9684_dma/s_axis_valid
+ad_connect  axi_ad9684_fifo/dma_wdata axi_ad9684_dma/s_axis_data
+ad_connect  axi_ad9684_fifo/dma_wready axi_ad9684_dma/s_axis_ready
+ad_connect  axi_ad9684_fifo/dma_xfer_req axi_ad9684_dma/s_axis_xfer_req
 
-ad_connect  util_cpack_ad9684/adc_valid axi_ad9684_dma/fifo_wr_en
-ad_connect  util_cpack_ad9684/adc_data axi_ad9684_dma/fifo_wr_din
-ad_connect  util_cpack_ad9684/adc_sync axi_ad9684_dma/fifo_wr_sync
 
 # memory interconnect
 
diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile
index f0387db04..f17d14899 100644
--- a/projects/daq1/zc706/Makefile
+++ b/projects/daq1/zc706/Makefile
@@ -14,11 +14,15 @@ M_DEPS += ../common/daq1_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl
+M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684.xpr
+M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -54,6 +58,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9122 clean
 	make -C ../../../library/axi_ad9684 clean
+	make -C ../../../library/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
@@ -70,6 +75,7 @@ daq1_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9122
 	make -C ../../../library/axi_ad9684
+	make -C ../../../library/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
diff --git a/projects/daq1/zc706/system_bd.tcl b/projects/daq1/zc706/system_bd.tcl
index 138650de3..5fa45b20a 100644
--- a/projects/daq1/zc706/system_bd.tcl
+++ b/projects/daq1/zc706/system_bd.tcl
@@ -1,4 +1,23 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
+
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9684_fifo 64
+
+create_bd_port -dir I -type rst sys_rst
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
+
+set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
+
+ad_connect  sys_rst axi_ad9684_fifo/sys_rst
+ad_connect  sys_clk axi_ad9684_fifo/sys_clk
+ad_connect  ddr3 axi_ad9684_fifo/ddr3
+
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
+  [get_bd_addr_spaces axi_ad9684_fifo/axi_adcfifo/axi] \
+  [get_bd_addr_segs axi_ad9684_fifo/axi_ddr_cntrl/memmap/memaddr] \
+  SEG_axi_ddr_cntrl_memaddr
+
 source ../common/daq1_bd.tcl
 
diff --git a/projects/daq1/zc706/system_project.tcl b/projects/daq1/zc706/system_project.tcl
index 5fb216408..b468be7db 100644
--- a/projects/daq1/zc706/system_project.tcl
+++ b/projects/daq1/zc706/system_project.tcl
@@ -7,9 +7,13 @@ adi_project_create daq1_zc706
 adi_project_files daq1_zc706 [list \
   "../common/daq1_spi.v" \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
+  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
+  "system_top.v" ]
+
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run daq1_zc706
 
diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v
index 109232e4a..2741a9b73 100644
--- a/projects/daq1/zc706/system_top.v
+++ b/projects/daq1/zc706/system_top.v
@@ -92,7 +92,28 @@ module system_top (
   spi_clk,
   spi_csn,
   spi_sdio,
-  spi_int);
+  spi_int,
+
+  sys_rst,
+  sys_clk_p,
+  sys_clk_n,
+
+  ddr3_addr,
+  ddr3_ba,
+  ddr3_cas_n,
+  ddr3_ck_n,
+  ddr3_ck_p,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_dm,
+  ddr3_dq,
+  ddr3_dqs_n,
+  ddr3_dqs_p,
+  ddr3_odt,
+  ddr3_ras_n,
+  ddr3_reset_n,
+  ddr3_we_n
+);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -149,6 +170,26 @@ module system_top (
   inout           spi_sdio;
   input           spi_int;
 
+  input           sys_rst;
+  input           sys_clk_p;
+  input           sys_clk_n;
+
+  output  [13:0]  ddr3_addr;
+  output  [ 2:0]  ddr3_ba;
+  output          ddr3_cas_n;
+  output  [ 0:0]  ddr3_ck_n;
+  output  [ 0:0]  ddr3_ck_p;
+  output  [ 0:0]  ddr3_cke;
+  output  [ 0:0]  ddr3_cs_n;
+  output  [ 7:0]  ddr3_dm;
+  inout   [63:0]  ddr3_dq;
+  inout   [ 7:0]  ddr3_dqs_n;
+  inout   [ 7:0]  ddr3_dqs_p;
+  output  [ 0:0]  ddr3_odt;
+  output          ddr3_ras_n;
+  output          ddr3_reset_n;
+  output          ddr3_we_n;
+
   // internal signals
 
   wire    [63:0]  gpio_i;
@@ -173,6 +214,24 @@ module system_top (
     .spi_sdio (spi_sdio));
 
   system_wrapper i_system_wrapper (
+    .sys_clk_clk_n (sys_clk_n),
+    .sys_clk_clk_p (sys_clk_p),
+    .sys_rst (sys_rst),
+    .ddr3_addr (ddr3_addr),
+    .ddr3_ba (ddr3_ba),
+    .ddr3_cas_n (ddr3_cas_n),
+    .ddr3_ck_n (ddr3_ck_n),
+    .ddr3_ck_p (ddr3_ck_p),
+    .ddr3_cke (ddr3_cke),
+    .ddr3_cs_n (ddr3_cs_n),
+    .ddr3_dm (ddr3_dm),
+    .ddr3_dq (ddr3_dq),
+    .ddr3_dqs_n (ddr3_dqs_n),
+    .ddr3_dqs_p (ddr3_dqs_p),
+    .ddr3_odt (ddr3_odt),
+    .ddr3_ras_n (ddr3_ras_n),
+    .ddr3_reset_n (ddr3_reset_n),
+    .ddr3_we_n (ddr3_we_n),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_clk_in_p (adc_clk_in_p),
     .adc_data_in_n (adc_data_in_n),

From 92c580a84dd76aea8f503201bb1a111df4612825 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 8 Jul 2016 12:00:37 +0300
Subject: [PATCH 305/972] daq3: A10GX, updated project to the TCL flow

---
 projects/daq3/a10gx/Makefile           |    5 +-
 projects/daq3/a10gx/system_bd.qsys     |  680 -------
 projects/daq3/a10gx/system_constr.sdc  |   26 +-
 projects/daq3/a10gx/system_project.tcl |    4 +-
 projects/daq3/a10gx/system_qsys.tcl    |    8 +
 projects/daq3/a10gx/system_top.v       |   84 +-
 projects/daq3/common/daq3_bd.qsys      | 2459 ------------------------
 projects/daq3/common/daq3_qsys.tcl     |  301 +++
 8 files changed, 368 insertions(+), 3199 deletions(-)
 delete mode 100755 projects/daq3/a10gx/system_bd.qsys
 create mode 100644 projects/daq3/a10gx/system_qsys.tcl
 delete mode 100755 projects/daq3/common/daq3_bd.qsys
 create mode 100644 projects/daq3/common/daq3_qsys.tcl

diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index 9d7568db8..a15ed07fd 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -6,12 +6,13 @@
 ####################################################################################
 
 M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
-M_DEPS += system_bd.qsys
 M_DEPS += ../common/daq3_spi.v
-M_DEPS += ../common/daq3_bd.qsys
+M_DEPS += ../common/daq3_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
diff --git a/projects/daq3/a10gx/system_bd.qsys b/projects/daq3/a10gx/system_bd.qsys
deleted file mode 100755
index ec6989ffe..000000000
--- a/projects/daq3/a10gx/system_bd.qsys
+++ /dev/null
@@ -1,680 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element a10gx_base
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element a10gx_base.sys_mem_s_avl
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element daq3
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element daq3.axi_ad9152_core_s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element daq3.axi_ad9152_dma_s_axi
-   {
-      datum baseAddress
-      {
-         value = "229376";
-         type = "String";
-      }
-   }
-   element daq3.axi_ad9680_core_s_axi
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element daq3.axi_ad9680_dma_s_axi
-   {
-      datum baseAddress
-      {
-         value = "212992";
-         type = "String";
-      }
-   }
-   element daq3.axi_jesd_xcvr_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element daq3.xcvr_core_jesd204_rx_s_avl
-   {
-      datum baseAddress
-      {
-         value = "254976";
-         type = "String";
-      }
-   }
-   element daq3.xcvr_core_jesd204_tx_s_avl
-   {
-      datum baseAddress
-      {
-         value = "253952";
-         type = "String";
-      }
-   }
-   element daq3.xcvr_core_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "196608";
-         type = "String";
-      }
-   }
-   element daq3.xcvr_rx_pll_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "251904";
-         type = "String";
-      }
-   }
-   element daq3.xcvr_tx_lane_pll_s_avl
-   {
-      datum baseAddress
-      {
-         value = "245760";
-         type = "String";
-      }
-   }
-   element daq3.xcvr_tx_pll_reconfig_s_avl
-   {
-      datum baseAddress
-      {
-         value = "249856";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45E2SGE3" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="daq3_a10gx.qpf" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="a10gx_base_sys_ddr3_cntrl_mem"
-   internal="a10gx_base.sys_ddr3_cntrl_mem"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ddr3_cntrl_oct"
-   internal="a10gx_base.sys_ddr3_cntrl_oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ddr3_cntrl_pll_ref_clk"
-   internal="a10gx_base.sys_ddr3_cntrl_pll_ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ethernet_mdio"
-   internal="a10gx_base.sys_ethernet_mdio"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ethernet_ref_clk"
-   internal="a10gx_base.sys_ethernet_ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_ethernet_reset"
-   internal="a10gx_base.sys_ethernet_reset"
-   type="reset"
-   dir="start" />
- <interface
-   name="a10gx_base_sys_ethernet_sgmii"
-   internal="a10gx_base.sys_ethernet_sgmii"
-   type="conduit"
-   dir="end" />
- <interface name="a10gx_base_sys_gpio" internal="a10gx_base.sys_gpio" />
- <interface
-   name="a10gx_base_sys_gpio_bd"
-   internal="a10gx_base.sys_gpio_bd"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_gpio_in"
-   internal="a10gx_base.sys_gpio_in"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_gpio_out"
-   internal="a10gx_base.sys_gpio_out"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a10gx_base_sys_spi"
-   internal="a10gx_base.sys_spi"
-   type="conduit"
-   dir="end" />
- <interface name="daq3_rx_data" internal="daq3.rx_data" type="conduit" dir="end" />
- <interface
-   name="daq3_rx_ref_clk"
-   internal="daq3.rx_ref_clk"
-   type="clock"
-   dir="end" />
- <interface name="daq3_rx_sync" internal="daq3.rx_sync" type="conduit" dir="end" />
- <interface
-   name="daq3_rx_sysref"
-   internal="daq3.rx_sysref"
-   type="conduit"
-   dir="end" />
- <interface name="daq3_tx_data" internal="daq3.tx_data" type="conduit" dir="end" />
- <interface
-   name="daq3_tx_ref_clk"
-   internal="daq3.tx_ref_clk"
-   type="clock"
-   dir="end" />
- <interface name="daq3_tx_sync" internal="daq3.tx_sync" type="conduit" dir="end" />
- <interface
-   name="daq3_tx_sysref"
-   internal="daq3.tx_sysref"
-   type="conduit"
-   dir="end" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_reset"
-   internal="sys_clk.clk_in_reset"
-   type="reset"
-   dir="end" />
- <module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq3_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq3_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq3_axi_ad9152_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq3_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq3_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq3_axi_ad9152_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq3_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq3_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq3_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq3_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq3_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_RESET_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
- </module>
- <module name="daq3" kind="daq3_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 29" />
-  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 29" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133333250" />
-  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_TX_REF_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_TX_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq3" />
- </module>
- <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="daq3.axi_ad9152_dma_m_axi"
-   end="a10gx_base.sys_mem_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="daq3.axi_ad9680_dma_m_axi"
-   end="a10gx_base.sys_mem_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.axi_ad9152_core_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.axi_ad9152_dma_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00038000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.axi_ad9680_core_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.axi_ad9680_dma_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00034000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.axi_jesd_xcvr_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.xcvr_core_jesd204_rx_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003e400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.xcvr_core_jesd204_tx_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003e000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.xcvr_core_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.xcvr_rx_pll_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003d800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.xcvr_tx_lane_pll_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003c000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10gx_base.sys_cpu_m_avl"
-   end="daq3.xcvr_tx_pll_reconfig_s_avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0003d000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.clk"
-   end="a10gx_base.sys_clk" />
- <connection kind="clock" version="15.1" start="sys_clk.clk" end="daq3.sys_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="a10gx_base.mem_clk"
-   end="daq3.mem_clk" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10gx_base.sys_intr"
-   end="daq3.axi_ad9152_dma_intr">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10gx_base.sys_intr"
-   end="daq3.axi_ad9680_dma_intr">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="a10gx_base.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="daq3.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="a10gx_base.mem_rst"
-   end="daq3.mem_rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc
index 409f353e1..a1450327d 100644
--- a/projects/daq3/a10gx/system_constr.sdc
+++ b/projects/daq3/a10gx/system_constr.sdc
@@ -7,37 +7,37 @@ derive_pll_clocks
 derive_clock_uncertainty
 
 set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
+  i_system_bd|sys_ddr3_cntrl_phy_clk_0 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_1 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_2 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}]
  
 set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
-  i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
+  i_system_bd|sys_ddr3_cntrl_core_nios_clk}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]
 
-set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl
index a28b59e65..e2541bda9 100644
--- a/projects/daq3/a10gx/system_project.tcl
+++ b/projects/daq3/a10gx/system_project.tcl
@@ -5,12 +5,10 @@ source ../../scripts/adi_env.tcl
 project_new daq3_a10gx -overwrite
 
 source "../../common/a10gx/a10gx_system_assign.tcl"
-set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*"
-set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*"
-set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name VERILOG_FILE ../common/daq3_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
diff --git a/projects/daq3/a10gx/system_qsys.tcl b/projects/daq3/a10gx/system_qsys.tcl
new file mode 100644
index 000000000..b6503f47a
--- /dev/null
+++ b/projects/daq3/a10gx/system_qsys.tcl
@@ -0,0 +1,8 @@
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
+source ../common/daq3_qsys.tcl
+
+save_system "system_bd.qsys"
+
diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v
index c04de0cac..5cf8b702a 100644
--- a/projects/daq3/a10gx/system_top.v
+++ b/projects/daq3/a10gx/system_top.v
@@ -235,49 +235,49 @@ module system_top (
   assign gpio_bd_o = gpio_o[15:0];
 
   system_bd i_system_bd (
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
-    .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
-    .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
-    .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
-    .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc),
-    .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
-    .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
-    .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
-    .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
-    .a10gx_base_sys_ethernet_reset_reset (eth_reset),
-    .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
-    .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
-    .a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
-    .a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
-    .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
-    .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
-    .a10gx_base_sys_spi_MISO (spi_miso_s),
-    .a10gx_base_sys_spi_MOSI (spi_mosi_s),
-    .a10gx_base_sys_spi_SCLK (spi_clk),
-    .a10gx_base_sys_spi_SS_n (spi_csn_s),
-    .daq3_rx_data_rx_serial_data (rx_data),
-    .daq3_rx_ref_clk_clk (rx_ref_clk),
-    .daq3_rx_sync_rx_sync (rx_sync),
-    .daq3_rx_sysref_rx_ext_sysref_in (rx_sysref),
-    .daq3_tx_data_tx_serial_data (tx_data),
-    .daq3_tx_ref_clk_clk (tx_ref_clk),
-    .daq3_tx_sync_tx_sync (tx_sync),
-    .daq3_tx_sysref_tx_ext_sysref_in (tx_sysref),
+    .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
+    .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
+    .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
+    .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
+    .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
+    .sys_ethernet_mdio_mdc (eth_mdc),
+    .sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .sys_ethernet_ref_clk_clk (eth_ref_clk),
+    .sys_ethernet_reset_reset (eth_reset),
+    .sys_ethernet_sgmii_rxp_0 (eth_rxd),
+    .sys_ethernet_sgmii_txp_0 (eth_txd),
+    .sys_gpio_in_export (gpio_i[63:32]),
+    .sys_gpio_out_export (gpio_o[63:32]),
+    .sys_gpio_bd_in_port (gpio_i[31:0]),
+    .sys_gpio_bd_out_port (gpio_o[31:0]),
+    .sys_spi_MISO (spi_miso_s),
+    .sys_spi_MOSI (spi_mosi_s),
+    .sys_spi_SCLK (spi_clk),
+    .sys_spi_SS_n (spi_csn_s),
+    .rx_data_rx_serial_data (rx_data),
+    .rx_ref_clk_clk (rx_ref_clk),
+    .rx_sync_rx_sync (rx_sync),
+    .rx_sysref_rx_ext_sysref_in (rx_sysref),
+    .tx_data_tx_serial_data (tx_data),
+    .tx_ref_clk_clk (tx_ref_clk),
+    .tx_sync_tx_sync (tx_sync),
+    .tx_sysref_tx_ext_sysref_in (tx_sysref),
     .sys_clk_clk (sys_clk),
-    .sys_reset_reset_n (sys_resetn));
+    .sys_rst_reset_n (sys_resetn));
 
 endmodule
 
diff --git a/projects/daq3/common/daq3_bd.qsys b/projects/daq3/common/daq3_bd.qsys
deleted file mode 100755
index 50888360b..000000000
--- a/projects/daq3/common/daq3_bd.qsys
+++ /dev/null
@@ -1,2459 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element ad9680_adcfifo
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element axi_ad9152_core
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-   }
-   element axi_ad9152_core.s_axi
-   {
-      datum baseAddress
-      {
-         value = "269025280";
-         type = "String";
-      }
-   }
-   element axi_ad9152_dma
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element axi_ad9152_dma.s_axi
-   {
-      datum baseAddress
-      {
-         value = "269156352";
-         type = "String";
-      }
-   }
-   element axi_ad9680_core
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element axi_ad9680_core.s_axi
-   {
-      datum baseAddress
-      {
-         value = "269090816";
-         type = "String";
-      }
-   }
-   element axi_ad9680_dma
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9680_dma.s_axi
-   {
-      datum baseAddress
-      {
-         value = "269172736";
-         type = "String";
-      }
-   }
-   element axi_jesd_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-   }
-   element axi_jesd_xcvr.s_axi
-   {
-      datum baseAddress
-      {
-         value = "268959744";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element daq3_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element mem_clk
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element mem_rst
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element util_cpack_0
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element util_upack_0
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-   }
-   element xcvr_core
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-   }
-   element xcvr_rst_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-   }
-   element xcvr_rx_pll
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element xcvr_rx_pll_reconfig
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element xcvr_rx_ref_clk
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element xcvr_tx_lane_pll
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-   }
-   element xcvr_tx_pll
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element xcvr_tx_pll_reconfig
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element xcvr_tx_ref_clk
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AX115S3F45E2SGE3" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="axi_ad9152_core_s_axi"
-   internal="axi_ad9152_core.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9152_dma_intr"
-   internal="axi_ad9152_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_ad9152_dma_m_axi"
-   internal="axi_ad9152_dma.m_src_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_ad9152_dma_s_axi"
-   internal="axi_ad9152_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9680_core_s_axi"
-   internal="axi_ad9680_core.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9680_dma_intr"
-   internal="axi_ad9680_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_ad9680_dma_m_axi"
-   internal="axi_ad9680_dma.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_ad9680_dma_s_axi"
-   internal="axi_ad9680_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_jesd_xcvr_s_axi"
-   internal="axi_jesd_xcvr.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
- <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="rx_data"
-   internal="xcvr_core.rx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ref_clk"
-   internal="xcvr_rx_ref_clk.in_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="rx_sync"
-   internal="axi_jesd_xcvr.if_rx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sysref"
-   internal="axi_jesd_xcvr.if_rx_ext_sysref_in"
-   type="conduit"
-   dir="end" />
- <interface name="stp_trigger" internal="axi_jesd_xcvr.if_stp_trigger" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="tx_data"
-   internal="xcvr_core.tx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="tx_ref_clk"
-   internal="xcvr_tx_ref_clk.in_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="tx_sync"
-   internal="axi_jesd_xcvr.if_tx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="tx_sysref"
-   internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
-   type="conduit"
-   dir="end" />
- <interface
-   name="xcvr_core_jesd204_rx_s_avl"
-   internal="xcvr_core.jesd204_rx_avs"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_core_jesd204_tx_s_avl"
-   internal="xcvr_core.jesd204_tx_avs"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_core_reconfig_s_avl"
-   internal="xcvr_core.reconfig_avmm"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_rx_pll_reconfig_s_avl"
-   internal="xcvr_rx_pll_reconfig.mgmt_avalon_slave"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_tx_lane_pll_s_avl"
-   internal="xcvr_tx_lane_pll.reconfig_avmm0"
-   type="avalon"
-   dir="end" />
- <interface
-   name="xcvr_tx_pll_reconfig_s_avl"
-   internal="xcvr_tx_pll_reconfig.mgmt_avalon_slave"
-   type="avalon"
-   dir="end" />
- <module name="ad9680_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
-  <parameter name="ADC_DATA_WIDTH" value="128" />
-  <parameter name="DMA_ADDRESS_WIDTH" value="16" />
-  <parameter name="DMA_DATA_WIDTH" value="128" />
-  <parameter name="DMA_READY_ENABLE" value="1" />
- </module>
- <module name="axi_ad9152_core" kind="axi_ad9152" version="1.0" enabled="1">
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_ad9152_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="1" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
-  <parameter name="DMA_LENGTH_WIDTH" value="14" />
-  <parameter name="DMA_TYPE_DEST" value="2" />
-  <parameter name="DMA_TYPE_SRC" value="0" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
- </module>
- <module name="axi_ad9680_core" kind="axi_ad9680" version="1.0" enabled="1">
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_ad9680_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="1" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_jesd_xcvr" kind="axi_jesd_xcvr" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
-  <parameter name="RX_NUM_OF_LANES" value="4" />
-  <parameter name="TX_NUM_OF_LANES" value="4" />
- </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="125000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="util_cpack_0" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="64" />
-  <parameter name="NUM_OF_CHANNELS" value="2" />
- </module>
- <module name="util_upack_0" kind="util_upack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="64" />
-  <parameter name="NUM_OF_CHANNELS" value="2" />
- </module>
- <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX_TX" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="1" />
-  <parameter name="GUI_EN_CFG_F" value="true" />
-  <parameter name="HD" value="1" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="32" />
-  <parameter name="L" value="4" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="2" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG2" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="500.0" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="non_bonded" />
-  <parameter name="lane_rate" value="10000.0" />
-  <parameter name="part_trait_bd" value="NIGHTFURY5" />
-  <parameter name="part_trait_dp" value="10AX115S3F45E2SGE3" />
-  <parameter name="pll_reconfig_enable" value="true" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="true" />
-  <parameter name="set_csr_soft_logic_enable" value="true" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module
-   name="xcvr_rst_cntrl"
-   kind="altera_xcvr_reset_control"
-   version="15.1"
-   enabled="1">
-  <parameter name="CHANNELS" value="4" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="100" />
-  <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="70000" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_ANALOGRESET" value="70000" />
-  <parameter name="T_TX_DIGITALRESET" value="70000" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="1" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="0" />
- </module>
- <module name="xcvr_rx_pll" kind="altera_iopll" version="15.1" enabled="1">
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_duty_cycle0" value="50.0" />
-  <parameter name="gui_actual_duty_cycle1" value="50.0" />
-  <parameter name="gui_actual_duty_cycle10" value="50.0" />
-  <parameter name="gui_actual_duty_cycle11" value="50.0" />
-  <parameter name="gui_actual_duty_cycle12" value="50.0" />
-  <parameter name="gui_actual_duty_cycle13" value="50.0" />
-  <parameter name="gui_actual_duty_cycle14" value="50.0" />
-  <parameter name="gui_actual_duty_cycle15" value="50.0" />
-  <parameter name="gui_actual_duty_cycle16" value="50.0" />
-  <parameter name="gui_actual_duty_cycle17" value="50.0" />
-  <parameter name="gui_actual_duty_cycle2" value="50.0" />
-  <parameter name="gui_actual_duty_cycle3" value="50.0" />
-  <parameter name="gui_actual_duty_cycle4" value="50.0" />
-  <parameter name="gui_actual_duty_cycle5" value="50.0" />
-  <parameter name="gui_actual_duty_cycle6" value="50.0" />
-  <parameter name="gui_actual_duty_cycle7" value="50.0" />
-  <parameter name="gui_actual_duty_cycle8" value="50.0" />
-  <parameter name="gui_actual_duty_cycle9" value="50.0" />
-  <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_actual_phase_shift0" value="0.0" />
-  <parameter name="gui_actual_phase_shift1" value="0.0" />
-  <parameter name="gui_actual_phase_shift10" value="0.0" />
-  <parameter name="gui_actual_phase_shift11" value="0.0" />
-  <parameter name="gui_actual_phase_shift12" value="0.0" />
-  <parameter name="gui_actual_phase_shift13" value="0.0" />
-  <parameter name="gui_actual_phase_shift14" value="0.0" />
-  <parameter name="gui_actual_phase_shift15" value="0.0" />
-  <parameter name="gui_actual_phase_shift16" value="0.0" />
-  <parameter name="gui_actual_phase_shift17" value="0.0" />
-  <parameter name="gui_actual_phase_shift2" value="0.0" />
-  <parameter name="gui_actual_phase_shift3" value="0.0" />
-  <parameter name="gui_actual_phase_shift4" value="0.0" />
-  <parameter name="gui_actual_phase_shift5" value="0.0" />
-  <parameter name="gui_actual_phase_shift6" value="0.0" />
-  <parameter name="gui_actual_phase_shift7" value="0.0" />
-  <parameter name="gui_actual_phase_shift8" value="0.0" />
-  <parameter name="gui_actual_phase_shift9" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_clock_name_global0" value="false" />
-  <parameter name="gui_clock_name_global1" value="false" />
-  <parameter name="gui_clock_name_global10" value="false" />
-  <parameter name="gui_clock_name_global11" value="false" />
-  <parameter name="gui_clock_name_global12" value="false" />
-  <parameter name="gui_clock_name_global13" value="false" />
-  <parameter name="gui_clock_name_global14" value="false" />
-  <parameter name="gui_clock_name_global15" value="false" />
-  <parameter name="gui_clock_name_global16" value="false" />
-  <parameter name="gui_clock_name_global17" value="false" />
-  <parameter name="gui_clock_name_global2" value="false" />
-  <parameter name="gui_clock_name_global3" value="false" />
-  <parameter name="gui_clock_name_global4" value="false" />
-  <parameter name="gui_clock_name_global5" value="false" />
-  <parameter name="gui_clock_name_global6" value="false" />
-  <parameter name="gui_clock_name_global7" value="false" />
-  <parameter name="gui_clock_name_global8" value="false" />
-  <parameter name="gui_clock_name_global9" value="false" />
-  <parameter name="gui_clock_name_string0" value="outclk0" />
-  <parameter name="gui_clock_name_string1" value="outclk1" />
-  <parameter name="gui_clock_name_string10" value="outclk10" />
-  <parameter name="gui_clock_name_string11" value="outclk11" />
-  <parameter name="gui_clock_name_string12" value="outclk12" />
-  <parameter name="gui_clock_name_string13" value="outclk13" />
-  <parameter name="gui_clock_name_string14" value="outclk14" />
-  <parameter name="gui_clock_name_string15" value="outclk15" />
-  <parameter name="gui_clock_name_string16" value="outclk16" />
-  <parameter name="gui_clock_name_string17" value="outclk17" />
-  <parameter name="gui_clock_name_string2" value="outclk2" />
-  <parameter name="gui_clock_name_string3" value="outclk3" />
-  <parameter name="gui_clock_name_string4" value="outclk4" />
-  <parameter name="gui_clock_name_string5" value="outclk5" />
-  <parameter name="gui_clock_name_string6" value="outclk6" />
-  <parameter name="gui_clock_name_string7" value="outclk7" />
-  <parameter name="gui_clock_name_string8" value="outclk8" />
-  <parameter name="gui_clock_name_string9" value="outclk9" />
-  <parameter name="gui_device_speed_grade" value="1" />
-  <parameter name="gui_divide_factor_c0" value="6" />
-  <parameter name="gui_divide_factor_c1" value="6" />
-  <parameter name="gui_divide_factor_c10" value="6" />
-  <parameter name="gui_divide_factor_c11" value="6" />
-  <parameter name="gui_divide_factor_c12" value="6" />
-  <parameter name="gui_divide_factor_c13" value="6" />
-  <parameter name="gui_divide_factor_c14" value="6" />
-  <parameter name="gui_divide_factor_c15" value="6" />
-  <parameter name="gui_divide_factor_c16" value="6" />
-  <parameter name="gui_divide_factor_c17" value="6" />
-  <parameter name="gui_divide_factor_c2" value="6" />
-  <parameter name="gui_divide_factor_c3" value="6" />
-  <parameter name="gui_divide_factor_c4" value="6" />
-  <parameter name="gui_divide_factor_c5" value="6" />
-  <parameter name="gui_divide_factor_c6" value="6" />
-  <parameter name="gui_divide_factor_c7" value="6" />
-  <parameter name="gui_divide_factor_c8" value="6" />
-  <parameter name="gui_divide_factor_c9" value="6" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50.0" />
-  <parameter name="gui_duty_cycle1" value="50.0" />
-  <parameter name="gui_duty_cycle10" value="50.0" />
-  <parameter name="gui_duty_cycle11" value="50.0" />
-  <parameter name="gui_duty_cycle12" value="50.0" />
-  <parameter name="gui_duty_cycle13" value="50.0" />
-  <parameter name="gui_duty_cycle14" value="50.0" />
-  <parameter name="gui_duty_cycle15" value="50.0" />
-  <parameter name="gui_duty_cycle16" value="50.0" />
-  <parameter name="gui_duty_cycle17" value="50.0" />
-  <parameter name="gui_duty_cycle2" value="50.0" />
-  <parameter name="gui_duty_cycle3" value="50.0" />
-  <parameter name="gui_duty_cycle4" value="50.0" />
-  <parameter name="gui_duty_cycle5" value="50.0" />
-  <parameter name="gui_duty_cycle6" value="50.0" />
-  <parameter name="gui_duty_cycle7" value="50.0" />
-  <parameter name="gui_duty_cycle8" value="50.0" />
-  <parameter name="gui_duty_cycle9" value="50.0" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="Disabled" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="true" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_enable_output_counter_cascading" value="false" />
-  <parameter name="gui_extclkout_0_source" value="C0" />
-  <parameter name="gui_extclkout_1_source" value="C0" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_fix_vco_frequency" value="false" />
-  <parameter name="gui_fixed_vco_frequency" value="600.0" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="6" />
-  <parameter name="gui_number_of_clocks" value="1" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="250.0" />
-  <parameter name="gui_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0.0" />
-  <parameter name="gui_phase_shift1" value="0.0" />
-  <parameter name="gui_phase_shift10" value="0.0" />
-  <parameter name="gui_phase_shift11" value="0.0" />
-  <parameter name="gui_phase_shift12" value="0.0" />
-  <parameter name="gui_phase_shift13" value="0.0" />
-  <parameter name="gui_phase_shift14" value="0.0" />
-  <parameter name="gui_phase_shift15" value="0.0" />
-  <parameter name="gui_phase_shift16" value="0.0" />
-  <parameter name="gui_phase_shift17" value="0.0" />
-  <parameter name="gui_phase_shift2" value="0.0" />
-  <parameter name="gui_phase_shift3" value="0.0" />
-  <parameter name="gui_phase_shift4" value="0.0" />
-  <parameter name="gui_phase_shift5" value="0.0" />
-  <parameter name="gui_phase_shift6" value="0.0" />
-  <parameter name="gui_phase_shift7" value="0.0" />
-  <parameter name="gui_phase_shift8" value="0.0" />
-  <parameter name="gui_phase_shift9" value="0.0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="false" />
-  <parameter name="gui_pll_bandwidth_preset" value="Low" />
-  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="500.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_NDFB_modes" value="false" />
-  <parameter name="gui_use_locked" value="false" />
-  <parameter name="gui_vco_frequency" value="600.0" />
-  <parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
-  <parameter name="system_info_device_family" value="Arria 10" />
-  <parameter name="system_info_device_speed_grade" value="2" />
-  <parameter name="system_part_trait_speed_grade" value="2" />
- </module>
- <module
-   name="xcvr_rx_pll_reconfig"
-   kind="altera_pll_reconfig"
-   version="15.1"
-   enabled="1">
-  <parameter name="ENABLE_BYTEENABLE" value="false" />
-  <parameter name="ENABLE_MIF" value="false" />
-  <parameter name="MIF_FILE_NAME" value="" />
-  <parameter name="device_family" value="Arria 10" />
- </module>
- <module
-   name="xcvr_rx_ref_clk"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module
-   name="xcvr_tx_lane_pll"
-   kind="altera_xcvr_atx_pll_a10"
-   version="15.1"
-   enabled="1">
-  <parameter name="base_device" value="NIGHTFURY5" />
-  <parameter name="bw_sel" value="medium" />
-  <parameter name="device" value="10AX115S3F45E2SGE3" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="enable_16G_path" value="0" />
-  <parameter name="enable_8G_path" value="1" />
-  <parameter name="enable_analog_resets" value="0" />
-  <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
-  <parameter name="enable_bonding_clks" value="0" />
-  <parameter name="enable_cascade_out" value="0" />
-  <parameter name="enable_debug_ports_parameters" value="0" />
-  <parameter name="enable_fb_comp_bonding" value="0" />
-  <parameter name="enable_fractional" value="0" />
-  <parameter name="enable_hfreq_clk" value="0" />
-  <parameter name="enable_hip_cal_done_port" value="0" />
-  <parameter name="enable_manual_configuration" value="1" />
-  <parameter name="enable_mcgb" value="0" />
-  <parameter name="enable_mcgb_pcie_clksw" value="0" />
-  <parameter name="enable_pcie_clk" value="0" />
-  <parameter name="enable_pld_atx_cal_busy_port" value="1" />
-  <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
-  <parameter name="enable_pll_reconfig" value="1" />
-  <parameter name="generate_add_hdl_instance_example" value="0" />
-  <parameter name="generate_docs" value="1" />
-  <parameter name="mcgb_aux_clkin_cnt" value="0" />
-  <parameter name="mcgb_div" value="1" />
-  <parameter name="message_level" value="error" />
-  <parameter name="pma_width" value="64" />
-  <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
-  <parameter name="prot_mode" value="Basic" />
-  <parameter name="rcfg_debug" value="0" />
-  <parameter name="rcfg_enable_avmm_busy_port" value="0" />
-  <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
-  <parameter name="rcfg_h_file_enable" value="0" />
-  <parameter name="rcfg_jtag_enable" value="0" />
-  <parameter name="rcfg_mif_file_enable" value="0" />
-  <parameter name="rcfg_multi_enable" value="0" />
-  <parameter name="rcfg_param_vals1" value="" />
-  <parameter name="rcfg_param_vals2" value="" />
-  <parameter name="rcfg_profile_cnt" value="2" />
-  <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_separate_avmm_busy" value="1" />
-  <parameter name="rcfg_sv_file_enable" value="0" />
-  <parameter name="rcfg_txt_file_enable" value="0" />
-  <parameter name="refclk_cnt" value="1" />
-  <parameter name="refclk_index" value="0" />
-  <parameter name="select_manual_config" value="false" />
-  <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
-  <parameter name="set_auto_reference_clock_frequency" value="500.0" />
-  <parameter name="set_capability_reg_enable" value="1" />
-  <parameter name="set_csr_soft_logic_enable" value="1" />
-  <parameter name="set_fref_clock_frequency" value="156.25" />
-  <parameter name="set_hip_cal_en" value="0" />
-  <parameter name="set_k_counter" value="2000000000" />
-  <parameter name="set_l_cascade_counter" value="15" />
-  <parameter name="set_l_cascade_predivider" value="1" />
-  <parameter name="set_l_counter" value="16" />
-  <parameter name="set_m_counter" value="24" />
-  <parameter name="set_manual_reference_clock_frequency" value="200.0" />
-  <parameter name="set_output_clock_frequency" value="5000.0" />
-  <parameter name="set_ref_clk_div" value="1" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="silicon_rev" value="false" />
-  <parameter name="support_mode" value="user_mode" />
-  <parameter name="test_mode" value="0" />
- </module>
- <module name="xcvr_tx_pll" kind="altera_iopll" version="15.1" enabled="1">
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_duty_cycle0" value="50.0" />
-  <parameter name="gui_actual_duty_cycle1" value="50.0" />
-  <parameter name="gui_actual_duty_cycle10" value="50.0" />
-  <parameter name="gui_actual_duty_cycle11" value="50.0" />
-  <parameter name="gui_actual_duty_cycle12" value="50.0" />
-  <parameter name="gui_actual_duty_cycle13" value="50.0" />
-  <parameter name="gui_actual_duty_cycle14" value="50.0" />
-  <parameter name="gui_actual_duty_cycle15" value="50.0" />
-  <parameter name="gui_actual_duty_cycle16" value="50.0" />
-  <parameter name="gui_actual_duty_cycle17" value="50.0" />
-  <parameter name="gui_actual_duty_cycle2" value="50.0" />
-  <parameter name="gui_actual_duty_cycle3" value="50.0" />
-  <parameter name="gui_actual_duty_cycle4" value="50.0" />
-  <parameter name="gui_actual_duty_cycle5" value="50.0" />
-  <parameter name="gui_actual_duty_cycle6" value="50.0" />
-  <parameter name="gui_actual_duty_cycle7" value="50.0" />
-  <parameter name="gui_actual_duty_cycle8" value="50.0" />
-  <parameter name="gui_actual_duty_cycle9" value="50.0" />
-  <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_actual_phase_shift0" value="0.0" />
-  <parameter name="gui_actual_phase_shift1" value="0.0" />
-  <parameter name="gui_actual_phase_shift10" value="0.0" />
-  <parameter name="gui_actual_phase_shift11" value="0.0" />
-  <parameter name="gui_actual_phase_shift12" value="0.0" />
-  <parameter name="gui_actual_phase_shift13" value="0.0" />
-  <parameter name="gui_actual_phase_shift14" value="0.0" />
-  <parameter name="gui_actual_phase_shift15" value="0.0" />
-  <parameter name="gui_actual_phase_shift16" value="0.0" />
-  <parameter name="gui_actual_phase_shift17" value="0.0" />
-  <parameter name="gui_actual_phase_shift2" value="0.0" />
-  <parameter name="gui_actual_phase_shift3" value="0.0" />
-  <parameter name="gui_actual_phase_shift4" value="0.0" />
-  <parameter name="gui_actual_phase_shift5" value="0.0" />
-  <parameter name="gui_actual_phase_shift6" value="0.0" />
-  <parameter name="gui_actual_phase_shift7" value="0.0" />
-  <parameter name="gui_actual_phase_shift8" value="0.0" />
-  <parameter name="gui_actual_phase_shift9" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_clock_name_global0" value="false" />
-  <parameter name="gui_clock_name_global1" value="false" />
-  <parameter name="gui_clock_name_global10" value="false" />
-  <parameter name="gui_clock_name_global11" value="false" />
-  <parameter name="gui_clock_name_global12" value="false" />
-  <parameter name="gui_clock_name_global13" value="false" />
-  <parameter name="gui_clock_name_global14" value="false" />
-  <parameter name="gui_clock_name_global15" value="false" />
-  <parameter name="gui_clock_name_global16" value="false" />
-  <parameter name="gui_clock_name_global17" value="false" />
-  <parameter name="gui_clock_name_global2" value="false" />
-  <parameter name="gui_clock_name_global3" value="false" />
-  <parameter name="gui_clock_name_global4" value="false" />
-  <parameter name="gui_clock_name_global5" value="false" />
-  <parameter name="gui_clock_name_global6" value="false" />
-  <parameter name="gui_clock_name_global7" value="false" />
-  <parameter name="gui_clock_name_global8" value="false" />
-  <parameter name="gui_clock_name_global9" value="false" />
-  <parameter name="gui_clock_name_string0" value="outclk0" />
-  <parameter name="gui_clock_name_string1" value="outclk1" />
-  <parameter name="gui_clock_name_string10" value="outclk10" />
-  <parameter name="gui_clock_name_string11" value="outclk11" />
-  <parameter name="gui_clock_name_string12" value="outclk12" />
-  <parameter name="gui_clock_name_string13" value="outclk13" />
-  <parameter name="gui_clock_name_string14" value="outclk14" />
-  <parameter name="gui_clock_name_string15" value="outclk15" />
-  <parameter name="gui_clock_name_string16" value="outclk16" />
-  <parameter name="gui_clock_name_string17" value="outclk17" />
-  <parameter name="gui_clock_name_string2" value="outclk2" />
-  <parameter name="gui_clock_name_string3" value="outclk3" />
-  <parameter name="gui_clock_name_string4" value="outclk4" />
-  <parameter name="gui_clock_name_string5" value="outclk5" />
-  <parameter name="gui_clock_name_string6" value="outclk6" />
-  <parameter name="gui_clock_name_string7" value="outclk7" />
-  <parameter name="gui_clock_name_string8" value="outclk8" />
-  <parameter name="gui_clock_name_string9" value="outclk9" />
-  <parameter name="gui_device_speed_grade" value="1" />
-  <parameter name="gui_divide_factor_c0" value="6" />
-  <parameter name="gui_divide_factor_c1" value="6" />
-  <parameter name="gui_divide_factor_c10" value="6" />
-  <parameter name="gui_divide_factor_c11" value="6" />
-  <parameter name="gui_divide_factor_c12" value="6" />
-  <parameter name="gui_divide_factor_c13" value="6" />
-  <parameter name="gui_divide_factor_c14" value="6" />
-  <parameter name="gui_divide_factor_c15" value="6" />
-  <parameter name="gui_divide_factor_c16" value="6" />
-  <parameter name="gui_divide_factor_c17" value="6" />
-  <parameter name="gui_divide_factor_c2" value="6" />
-  <parameter name="gui_divide_factor_c3" value="6" />
-  <parameter name="gui_divide_factor_c4" value="6" />
-  <parameter name="gui_divide_factor_c5" value="6" />
-  <parameter name="gui_divide_factor_c6" value="6" />
-  <parameter name="gui_divide_factor_c7" value="6" />
-  <parameter name="gui_divide_factor_c8" value="6" />
-  <parameter name="gui_divide_factor_c9" value="6" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50.0" />
-  <parameter name="gui_duty_cycle1" value="50.0" />
-  <parameter name="gui_duty_cycle10" value="50.0" />
-  <parameter name="gui_duty_cycle11" value="50.0" />
-  <parameter name="gui_duty_cycle12" value="50.0" />
-  <parameter name="gui_duty_cycle13" value="50.0" />
-  <parameter name="gui_duty_cycle14" value="50.0" />
-  <parameter name="gui_duty_cycle15" value="50.0" />
-  <parameter name="gui_duty_cycle16" value="50.0" />
-  <parameter name="gui_duty_cycle17" value="50.0" />
-  <parameter name="gui_duty_cycle2" value="50.0" />
-  <parameter name="gui_duty_cycle3" value="50.0" />
-  <parameter name="gui_duty_cycle4" value="50.0" />
-  <parameter name="gui_duty_cycle5" value="50.0" />
-  <parameter name="gui_duty_cycle6" value="50.0" />
-  <parameter name="gui_duty_cycle7" value="50.0" />
-  <parameter name="gui_duty_cycle8" value="50.0" />
-  <parameter name="gui_duty_cycle9" value="50.0" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="Disabled" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="true" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_enable_output_counter_cascading" value="false" />
-  <parameter name="gui_extclkout_0_source" value="C0" />
-  <parameter name="gui_extclkout_1_source" value="C0" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_fix_vco_frequency" value="false" />
-  <parameter name="gui_fixed_vco_frequency" value="600.0" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="6" />
-  <parameter name="gui_number_of_clocks" value="1" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="250.0" />
-  <parameter name="gui_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0.0" />
-  <parameter name="gui_phase_shift1" value="0.0" />
-  <parameter name="gui_phase_shift10" value="0.0" />
-  <parameter name="gui_phase_shift11" value="0.0" />
-  <parameter name="gui_phase_shift12" value="0.0" />
-  <parameter name="gui_phase_shift13" value="0.0" />
-  <parameter name="gui_phase_shift14" value="0.0" />
-  <parameter name="gui_phase_shift15" value="0.0" />
-  <parameter name="gui_phase_shift16" value="0.0" />
-  <parameter name="gui_phase_shift17" value="0.0" />
-  <parameter name="gui_phase_shift2" value="0.0" />
-  <parameter name="gui_phase_shift3" value="0.0" />
-  <parameter name="gui_phase_shift4" value="0.0" />
-  <parameter name="gui_phase_shift5" value="0.0" />
-  <parameter name="gui_phase_shift6" value="0.0" />
-  <parameter name="gui_phase_shift7" value="0.0" />
-  <parameter name="gui_phase_shift8" value="0.0" />
-  <parameter name="gui_phase_shift9" value="0.0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="false" />
-  <parameter name="gui_pll_bandwidth_preset" value="Low" />
-  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="500.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_NDFB_modes" value="false" />
-  <parameter name="gui_use_locked" value="false" />
-  <parameter name="gui_vco_frequency" value="600.0" />
-  <parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
-  <parameter name="system_info_device_family" value="Arria 10" />
-  <parameter name="system_info_device_speed_grade" value="2" />
-  <parameter name="system_part_trait_speed_grade" value="2" />
- </module>
- <module
-   name="xcvr_tx_pll_reconfig"
-   kind="altera_pll_reconfig"
-   version="15.1"
-   enabled="1">
-  <parameter name="ENABLE_BYTEENABLE" value="false" />
-  <parameter name="ENABLE_MIF" value="false" />
-  <parameter name="MIF_FILE_NAME" value="" />
-  <parameter name="device_family" value="Arria 10" />
- </module>
- <module
-   name="xcvr_tx_ref_clk"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_ip_avl"
-   end="xcvr_core.jesd204_tx_link" />
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="xcvr_core.jesd204_rx_link"
-   end="axi_jesd_xcvr.if_rx_ip_avl" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection kind="clock" version="15.1" start="mem_clk.out_clk" end="mem_rst.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rst_cntrl.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="ad9680_adcfifo.if_dma_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_ad9680_dma.if_s_axis_aclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_core.jesd204_rx_avs_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_core.jesd204_tx_avs_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_ad9680_dma.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_ad9152_dma.m_src_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_tx_pll_reconfig.mgmt_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_pll_reconfig.mgmt_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_ref_clk.out_clk"
-   end="xcvr_tx_lane_pll.pll_refclk0" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_core.reconfig_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_tx_lane_pll.reconfig_clk0" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_ref_clk.out_clk"
-   end="xcvr_tx_pll.refclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_ref_clk.out_clk"
-   end="xcvr_rx_pll.refclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_ref_clk.out_clk"
-   end="xcvr_core.rx_pll_ref_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9680_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9680_core.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9152_core.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_jesd_xcvr.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9152_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="util_cpack_0.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="ad9680_adcfifo.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="util_upack_0.if_dac_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="axi_ad9152_dma.if_fifo_rd_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_ad9680_core.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_jesd_xcvr.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="axi_ad9152_core.if_tx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="axi_jesd_xcvr.if_tx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="xcvr_core.rxlink_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_tx_pll.outclk0"
-   end="xcvr_core.txlink_clk" />
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9680_core.adc_ch_0"
-   end="util_cpack_0.adc_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9680_core.adc_ch_1"
-   end="util_cpack_0.adc_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.alldev_lane_aligned"
-   end="xcvr_core.dev_lane_aligned">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9152_core.dac_ch_0"
-   end="util_upack_0.dac_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9152_core.dac_ch_1"
-   end="util_upack_0.dac_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_cpack_0.if_adc_data"
-   end="ad9680_adcfifo.if_adc_wdata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_cpack_0.if_adc_valid"
-   end="ad9680_adcfifo.if_adc_wr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_adc_wovf"
-   end="axi_ad9680_core.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_upack_0.if_dac_valid"
-   end="axi_ad9152_dma.if_fifo_rd_en">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_dma_wdata"
-   end="axi_ad9680_dma.if_s_axis_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_dma_wr"
-   end="axi_ad9680_dma.if_s_axis_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_dma_wready"
-   end="axi_ad9680_dma.if_s_axis_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="ad9680_adcfifo.if_dma_xfer_req"
-   end="axi_ad9680_dma.if_s_axis_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9152_dma.if_fifo_rd_dout"
-   end="util_upack_0.if_dac_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9152_dma.if_fifo_rd_underflow"
-   end="axi_ad9152_core.if_dac_dunf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9680_core.if_rx_data"
-   end="axi_jesd_xcvr.if_rx_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sof"
-   end="xcvr_core.rx_sof">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sync"
-   end="xcvr_core.rx_dev_sync_n">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sysref"
-   end="xcvr_core.rx_sysref">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ready"
-   end="xcvr_rst_cntrl.rx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_data"
-   end="axi_ad9152_core.if_tx_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_ip_sysref"
-   end="xcvr_core.tx_sysref">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_lane_pll.pll_cal_busy"
-   end="xcvr_rst_cntrl.pll_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_lane_pll.pll_locked"
-   end="xcvr_rst_cntrl.pll_locked">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.pll_powerdown"
-   end="xcvr_tx_lane_pll.pll_powerdown">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_pll_reconfig.reconfig_from_pll"
-   end="xcvr_tx_pll.reconfig_from_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_pll.reconfig_from_pll"
-   end="xcvr_rx_pll_reconfig.reconfig_from_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_pll.reconfig_to_pll"
-   end="xcvr_tx_pll_reconfig.reconfig_to_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_pll_reconfig.reconfig_to_pll"
-   end="xcvr_rx_pll.reconfig_to_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.rx_analogreset"
-   end="xcvr_core.rx_analogreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.rx_cal_busy"
-   end="xcvr_rst_cntrl.rx_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.rx_digitalreset"
-   end="xcvr_rst_cntrl.rx_digitalreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.rx_is_lockedtodata"
-   end="xcvr_core.rx_islockedtodata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.sync_n"
-   end="axi_jesd_xcvr.if_tx_ip_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.tx_analogreset"
-   end="xcvr_core.tx_analogreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.tx_cal_busy"
-   end="xcvr_core.tx_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.tx_dev_sync_n"
-   end="xcvr_core.mdev_sync_n">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.tx_digitalreset"
-   end="xcvr_rst_cntrl.tx_digitalreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.tx_ready"
-   end="axi_jesd_xcvr.if_tx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_core.tx_serial_clk0_ch0" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_core.tx_serial_clk0_ch1" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_core.tx_serial_clk0_ch2" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_core.tx_serial_clk0_ch3" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_tx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_rx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_rstn"
-   end="xcvr_core.rxlink_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_rstn"
-   end="xcvr_core.txlink_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="util_cpack_0.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="util_cpack_0.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="ad9680_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="ad9680_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_core.jesd204_rx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_core.jesd204_tx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="axi_ad9680_dma.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="axi_ad9152_dma.m_src_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_pll_reconfig.mgmt_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_pll_reconfig.mgmt_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_core.reconfig_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_lane_pll.reconfig_reset0" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_jesd_xcvr.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9152_core.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9680_core.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9680_dma.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9152_dma.s_axi_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl
new file mode 100644
index 000000000..831f46503
--- /dev/null
+++ b/projects/daq3/common/daq3_qsys.tcl
@@ -0,0 +1,301 @@
+
+# transmit-path (refclk)
+
+add_instance xcvr_tx_ref_clk altera_clock_bridge 15.1
+set_instance_parameter_value xcvr_tx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
+
+# transmit-path (pll-core)
+
+add_instance xcvr_tx_pll altera_iopll 15.1
+add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 15.1
+set_instance_parameter_value xcvr_tx_pll {gui_en_reconf} {1}
+set_instance_parameter_value xcvr_tx_pll {gui_reference_clock_frequency} {500.0}
+set_instance_parameter_value xcvr_tx_pll {gui_use_locked} {0}
+set_instance_parameter_value xcvr_tx_pll {gui_output_clock_frequency0} {250.0}
+
+# transmit-path (pll-atx)
+
+add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 15.1
+set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {5000.0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {500.0}
+
+# receive-path (refclk)
+
+add_instance xcvr_rx_ref_clk altera_clock_bridge 15.1
+set_instance_parameter_value xcvr_rx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
+
+# receive-path (pll-core)
+
+add_instance xcvr_rx_pll altera_iopll 15.1
+add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 15.1
+set_instance_parameter_value xcvr_rx_pll {gui_en_reconf} {1}
+set_instance_parameter_value xcvr_rx_pll {gui_reference_clock_frequency} {500.0}
+set_instance_parameter_value xcvr_rx_pll {gui_use_locked} {0}
+set_instance_parameter_value xcvr_rx_pll {gui_output_clock_frequency0} {250.0}
+
+# transceiver-control
+
+add_instance axi_jesd_xcvr axi_jesd_xcvr 1.0
+set_instance_parameter_value axi_jesd_xcvr {DEVICE_TYPE} {0}
+set_instance_parameter_value axi_jesd_xcvr {TX_NUM_OF_LANES} {4}
+set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {4}
+
+# transceiver-reset
+
+add_instance xcvr_rst_cntrl altera_xcvr_reset_control 15.1
+set_instance_parameter_value xcvr_rst_cntrl {CHANNELS} {4}
+set_instance_parameter_value xcvr_rst_cntrl {SYS_CLK_IN_MHZ} {100}
+set_instance_parameter_value xcvr_rst_cntrl {TX_PLL_ENABLE} {1}
+set_instance_parameter_value xcvr_rst_cntrl {T_PLL_POWERDOWN} {1000}
+set_instance_parameter_value xcvr_rst_cntrl {TX_ENABLE} {1}
+set_instance_parameter_value xcvr_rst_cntrl {T_TX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_rst_cntrl {T_TX_DIGITALRESET} {70000}
+set_instance_parameter_value xcvr_rst_cntrl {gui_pll_cal_busy} {1}
+set_instance_parameter_value xcvr_rst_cntrl {RX_ENABLE} {1}
+set_instance_parameter_value xcvr_rst_cntrl {T_RX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_rst_cntrl {T_RX_DIGITALRESET} {4000}
+
+# transceiver-core (+ jesd)
+
+add_instance xcvr_core altera_jesd204 15.1
+set_instance_parameter_value xcvr_core {wrapper_opt} {base_phy}
+set_instance_parameter_value xcvr_core {DATA_PATH} {RX_TX}
+set_instance_parameter_value xcvr_core {lane_rate} {10000.0}
+set_instance_parameter_value xcvr_core {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value xcvr_core {bonded_mode} {non_bonded}
+set_instance_parameter_value xcvr_core {REFCLK_FREQ} {500.0}
+set_instance_parameter_value xcvr_core {pll_reconfig_enable} {1}
+set_instance_parameter_value xcvr_core {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_core {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_core {L} {4}
+set_instance_parameter_value xcvr_core {M} {2}
+set_instance_parameter_value xcvr_core {GUI_EN_CFG_F} {1}
+set_instance_parameter_value xcvr_core {GUI_CFG_F} {1}
+set_instance_parameter_value xcvr_core {N} {16}
+set_instance_parameter_value xcvr_core {S} {1}
+set_instance_parameter_value xcvr_core {K} {32}
+set_instance_parameter_value xcvr_core {SCR} {1}
+set_instance_parameter_value xcvr_core {HD} {1}
+
+# transceiver + jesd interfaces
+
+add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_pll.refclk
+add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_lane_pll.pll_refclk0
+add_interface tx_ref_clk clock sink
+set_interface_property tx_ref_clk EXPORT_OF xcvr_tx_ref_clk.in_clk
+
+add_connection xcvr_rx_ref_clk.out_clk xcvr_rx_pll.refclk
+add_connection xcvr_rx_ref_clk.out_clk xcvr_core.rx_pll_ref_clk
+add_interface rx_ref_clk clock sink
+set_interface_property rx_ref_clk EXPORT_OF xcvr_rx_ref_clk.in_clk
+
+add_connection sys_clk.clk_reset xcvr_tx_pll.reset
+add_connection axi_jesd_xcvr.if_rst xcvr_tx_pll.reset
+add_connection xcvr_tx_pll.outclk0 xcvr_core.txlink_clk
+add_connection sys_clk.clk_reset xcvr_tx_pll_reconfig.mgmt_reset
+add_connection sys_clk.clk xcvr_tx_pll_reconfig.mgmt_clk
+add_connection sys_cpu.data_master xcvr_tx_pll_reconfig.mgmt_avalon_slave
+add_connection xcvr_tx_pll_reconfig.reconfig_from_pll xcvr_tx_pll.reconfig_from_pll
+add_connection xcvr_tx_pll.reconfig_to_pll xcvr_tx_pll_reconfig.reconfig_to_pll
+
+add_connection sys_clk.clk_reset xcvr_rx_pll.reset
+add_connection axi_jesd_xcvr.if_rst xcvr_rx_pll.reset
+add_connection xcvr_rx_pll.outclk0 xcvr_core.rxlink_clk
+add_connection sys_clk.clk_reset xcvr_rx_pll_reconfig.mgmt_reset
+add_connection sys_clk.clk xcvr_rx_pll_reconfig.mgmt_clk
+add_connection sys_cpu.data_master xcvr_rx_pll_reconfig.mgmt_avalon_slave
+add_connection xcvr_rx_pll.reconfig_from_pll xcvr_rx_pll_reconfig.reconfig_from_pll
+add_connection xcvr_rx_pll_reconfig.reconfig_to_pll xcvr_rx_pll.reconfig_to_pll
+
+add_connection xcvr_rst_cntrl.pll_powerdown xcvr_tx_lane_pll.pll_powerdown
+add_connection xcvr_tx_lane_pll.pll_cal_busy xcvr_rst_cntrl.pll_cal_busy
+add_connection xcvr_tx_lane_pll.pll_locked xcvr_rst_cntrl.pll_locked
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch0
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch1
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch2
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch3
+add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
+add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0
+add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
+
+add_connection sys_clk.clk_reset xcvr_rst_cntrl.reset
+add_connection sys_clk.clk xcvr_rst_cntrl.clock
+add_connection xcvr_rst_cntrl.tx_analogreset xcvr_core.tx_analogreset
+add_connection xcvr_rst_cntrl.tx_digitalreset xcvr_core.tx_digitalreset
+add_connection xcvr_rst_cntrl.tx_cal_busy xcvr_core.tx_cal_busy
+add_connection xcvr_rst_cntrl.rx_analogreset xcvr_core.rx_analogreset
+add_connection xcvr_rst_cntrl.rx_digitalreset xcvr_core.rx_digitalreset
+add_connection xcvr_rst_cntrl.rx_cal_busy xcvr_core.rx_cal_busy
+add_connection xcvr_rst_cntrl.rx_is_lockedtodata xcvr_core.rx_islockedtodata
+add_connection axi_jesd_xcvr.if_rst xcvr_rst_cntrl.reset
+add_connection xcvr_tx_pll.outclk0 axi_jesd_xcvr.if_tx_clk
+add_connection axi_jesd_xcvr.if_tx_rstn xcvr_core.txlink_rst_n
+add_connection axi_jesd_xcvr.if_tx_ready xcvr_rst_cntrl.tx_ready
+add_connection axi_jesd_xcvr.if_tx_ip_sysref xcvr_core.tx_sysref
+add_connection axi_jesd_xcvr.if_tx_ip_sync xcvr_core.sync_n
+add_connection axi_jesd_xcvr.if_tx_ip_avl xcvr_core.jesd204_tx_link
+add_connection xcvr_rx_pll.outclk0 axi_jesd_xcvr.if_rx_clk
+add_connection axi_jesd_xcvr.if_rx_rstn xcvr_core.rxlink_rst_n
+add_connection axi_jesd_xcvr.if_rx_ready xcvr_rst_cntrl.rx_ready
+add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_core.rx_sysref
+add_connection axi_jesd_xcvr.if_rx_ip_sync xcvr_core.rx_dev_sync_n
+add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_core.rx_sof
+add_connection xcvr_core.jesd204_rx_link axi_jesd_xcvr.if_rx_ip_avl
+add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
+add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
+add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
+add_interface tx_sysref conduit end
+add_interface tx_sync conduit end
+add_interface rx_sysref conduit end
+add_interface rx_sync conduit end
+set_interface_property tx_sysref EXPORT_OF axi_jesd_xcvr.if_tx_ext_sysref_in
+set_interface_property tx_sync EXPORT_OF axi_jesd_xcvr.if_tx_sync
+set_interface_property rx_sysref EXPORT_OF axi_jesd_xcvr.if_rx_ext_sysref_in
+set_interface_property rx_sync EXPORT_OF axi_jesd_xcvr.if_rx_sync
+
+add_connection sys_clk.clk_reset xcvr_core.reconfig_reset
+add_connection sys_clk.clk xcvr_core.reconfig_clk
+add_connection sys_clk.clk_reset xcvr_core.jesd204_tx_avs_rst_n
+add_connection sys_clk.clk xcvr_core.jesd204_tx_avs_clk
+add_connection sys_clk.clk_reset xcvr_core.jesd204_rx_avs_rst_n
+add_connection sys_clk.clk xcvr_core.jesd204_rx_avs_clk
+add_connection xcvr_core.alldev_lane_aligned xcvr_core.dev_lane_aligned
+add_connection xcvr_core.tx_dev_sync_n xcvr_core.mdev_sync_n
+add_connection sys_cpu.data_master xcvr_core.reconfig_avmm
+add_connection sys_cpu.data_master xcvr_core.jesd204_tx_avs
+add_connection sys_cpu.data_master xcvr_core.jesd204_rx_avs
+add_interface tx_data conduit end
+add_interface rx_data conduit end
+set_interface_property tx_data EXPORT_OF xcvr_core.tx_serial_data
+set_interface_property rx_data EXPORT_OF xcvr_core.rx_serial_data
+
+# ad9152
+
+add_instance axi_ad9152_core axi_ad9152 1.0
+#set_instance_parameter_value axi_ad9152_core {QUAD_OR_DUAL_N} {0}
+
+add_connection xcvr_tx_pll.outclk0 axi_ad9152_core.if_tx_clk
+add_connection axi_jesd_xcvr.if_tx_data axi_ad9152_core.if_tx_data
+add_connection sys_clk.clk_reset axi_ad9152_core.s_axi_reset
+add_connection sys_clk.clk axi_ad9152_core.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9152_core.s_axi
+
+# ad9152-unpack
+
+add_instance util_ad9152_upack util_upack 1.0
+set_instance_parameter_value util_ad9152_upack {CHANNEL_DATA_WIDTH} {64}
+set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} {2}
+
+add_connection xcvr_tx_pll.outclk0 util_ad9152_upack.if_dac_clk
+add_connection axi_ad9152_core.dac_ch_0 util_ad9152_upack.dac_ch_0
+add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1
+
+# ad9152-dma
+
+add_instance axi_ad9152_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_SRC} {128}
+set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0}
+
+add_connection xcvr_tx_pll.outclk0 axi_ad9152_dma.if_fifo_rd_clk
+add_connection util_ad9152_upack.if_dac_valid axi_ad9152_dma.if_fifo_rd_en
+add_connection util_ad9152_upack.if_dac_data axi_ad9152_dma.if_fifo_rd_dout
+add_connection axi_ad9152_dma.if_fifo_rd_underflow axi_ad9152_core.if_dac_dunf
+add_connection sys_clk.clk_reset axi_ad9152_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9152_dma.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9152_dma.s_axi
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9152_dma.m_src_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9152_dma.m_src_axi_clock
+add_connection axi_ad9152_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.irq axi_ad9152_dma.interrupt_sender
+
+# ad9680
+
+add_instance axi_ad9680_core axi_ad9680 1.0
+
+add_connection xcvr_rx_pll.outclk0 axi_ad9680_core.if_rx_clk
+add_connection axi_jesd_xcvr.if_rx_data axi_ad9680_core.if_rx_data
+add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
+add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9680_core.s_axi
+
+# ad9680-pack
+
+add_instance util_ad9680_cpack util_cpack 1.0
+set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64}
+set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
+
+add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
+add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst
+add_connection xcvr_rx_pll.outclk0 util_ad9680_cpack.if_adc_clk
+add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
+add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
+
+# ad9680-fifo
+
+add_instance ad9680_adcfifo util_adcfifo 1.0
+set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} {128}
+set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128}
+set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
+
+add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
+add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst
+add_connection xcvr_rx_pll.outclk0 ad9680_adcfifo.if_adc_clk
+add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
+add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
+add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk
+
+# ad9680-dma
+
+add_instance axi_ad9680_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} {128}
+set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0}
+set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
+set_instance_parameter_value axi_ad9680_dma {FIFO_SIZE} {8}
+
+
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk
+add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid
+add_connection ad9680_adcfifo.if_dma_wdata axi_ad9680_dma.if_s_axis_data
+add_connection ad9680_adcfifo.if_dma_wready axi_ad9680_dma.if_s_axis_ready
+add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
+add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
+add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9680_dma.s_axi
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
+add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
+
+# addresses
+
+set_connection_parameter_value sys_cpu.data_master/xcvr_rx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d800}
+set_connection_parameter_value sys_cpu.data_master/xcvr_tx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0        baseAddress {0x1003c000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi                   baseAddress {0x10034000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi                  baseAddress {0x10010000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9152_dma.s_axi                   baseAddress {0x10038000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9152_core.s_axi                  baseAddress {0x10020000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_core.reconfig_avmm                baseAddress {0x10030000}
+set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi                    baseAddress {0x10000000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_tx_avs               baseAddress {0x1003e000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_rx_avs               baseAddress {0x1003e400}
+set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
+set_connection_parameter_value axi_ad9152_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
+
+# interrupts
+
+set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}
+set_connection_parameter_value sys_cpu.irq/axi_ad9152_dma.interrupt_sender irqNumber {11}

From 20ac95b1ece567df16a32ed2a8d1495f0338d1de Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 8 Jul 2016 13:56:08 -0400
Subject: [PATCH 306/972] adxcvr- initial commit

---
 library/axi_adxcvr/axi_adxcvr.v         | 1748 +++++++++++++++++++++++
 library/axi_adxcvr/axi_adxcvr_es.v      |  567 ++++++++
 library/axi_adxcvr/axi_adxcvr_ip.tcl    |  268 ++++
 library/axi_adxcvr/axi_adxcvr_mdrp.v    |  135 ++
 library/axi_adxcvr/axi_adxcvr_mstatus.v |   76 +
 library/axi_adxcvr/axi_adxcvr_up.v      |  483 +++++++
 6 files changed, 3277 insertions(+)
 create mode 100644 library/axi_adxcvr/axi_adxcvr.v
 create mode 100644 library/axi_adxcvr/axi_adxcvr_es.v
 create mode 100644 library/axi_adxcvr/axi_adxcvr_ip.tcl
 create mode 100644 library/axi_adxcvr/axi_adxcvr_mdrp.v
 create mode 100644 library/axi_adxcvr/axi_adxcvr_mstatus.v
 create mode 100644 library/axi_adxcvr/axi_adxcvr_up.v

diff --git a/library/axi_adxcvr/axi_adxcvr.v b/library/axi_adxcvr/axi_adxcvr.v
new file mode 100644
index 000000000..33e1074fc
--- /dev/null
+++ b/library/axi_adxcvr/axi_adxcvr.v
@@ -0,0 +1,1748 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY!
+
+`timescale 1ns/1ps
+
+module axi_adxcvr (
+
+  output  [ 7:0]  up_cm_sel_0,
+  output          up_cm_enb_0,
+  output  [11:0]  up_cm_addr_0,
+  output          up_cm_wr_0,
+  output  [15:0]  up_cm_wdata_0,
+  input   [15:0]  up_cm_rdata_0,
+  input           up_cm_ready_0,
+
+  output  [ 7:0]  up_es_sel_0,
+  output          up_es_enb_0,
+  output  [11:0]  up_es_addr_0,
+  output          up_es_wr_0,
+  output  [15:0]  up_es_wdata_0,
+  input   [15:0]  up_es_rdata_0,
+  input           up_es_ready_0,
+
+  output          up_ch_pll_rst_0,
+  input           up_ch_pll_locked_0,
+  output          up_ch_rst_0,
+  output          up_ch_user_ready_0,
+  input           up_ch_rst_done_0,
+  output          up_ch_lpm_dfe_n_0,
+  output  [ 2:0]  up_ch_rate_0,
+  output  [ 1:0]  up_ch_sys_clk_sel_0,
+  output  [ 2:0]  up_ch_out_clk_sel_0,
+  output  [ 7:0]  up_ch_sel_0,
+  output          up_ch_enb_0,
+  output  [11:0]  up_ch_addr_0,
+  output          up_ch_wr_0,
+  output  [15:0]  up_ch_wdata_0,
+  input   [15:0]  up_ch_rdata_0,
+  input           up_ch_ready_0,
+
+  output  [ 7:0]  up_es_sel_1,
+  output          up_es_enb_1,
+  output  [11:0]  up_es_addr_1,
+  output          up_es_wr_1,
+  output  [15:0]  up_es_wdata_1,
+  input   [15:0]  up_es_rdata_1,
+  input           up_es_ready_1,
+
+  output          up_ch_pll_rst_1,
+  input           up_ch_pll_locked_1,
+  output          up_ch_rst_1,
+  output          up_ch_user_ready_1,
+  input           up_ch_rst_done_1,
+  output          up_ch_lpm_dfe_n_1,
+  output  [ 2:0]  up_ch_rate_1,
+  output  [ 1:0]  up_ch_sys_clk_sel_1,
+  output  [ 2:0]  up_ch_out_clk_sel_1,
+  output  [ 7:0]  up_ch_sel_1,
+  output          up_ch_enb_1,
+  output  [11:0]  up_ch_addr_1,
+  output          up_ch_wr_1,
+  output  [15:0]  up_ch_wdata_1,
+  input   [15:0]  up_ch_rdata_1,
+  input           up_ch_ready_1,
+
+  output  [ 7:0]  up_es_sel_2,
+  output          up_es_enb_2,
+  output  [11:0]  up_es_addr_2,
+  output          up_es_wr_2,
+  output  [15:0]  up_es_wdata_2,
+  input   [15:0]  up_es_rdata_2,
+  input           up_es_ready_2,
+
+  output          up_ch_pll_rst_2,
+  input           up_ch_pll_locked_2,
+  output          up_ch_rst_2,
+  output          up_ch_user_ready_2,
+  input           up_ch_rst_done_2,
+  output          up_ch_lpm_dfe_n_2,
+  output  [ 2:0]  up_ch_rate_2,
+  output  [ 1:0]  up_ch_sys_clk_sel_2,
+  output  [ 2:0]  up_ch_out_clk_sel_2,
+  output  [ 7:0]  up_ch_sel_2,
+  output          up_ch_enb_2,
+  output  [11:0]  up_ch_addr_2,
+  output          up_ch_wr_2,
+  output  [15:0]  up_ch_wdata_2,
+  input   [15:0]  up_ch_rdata_2,
+  input           up_ch_ready_2,
+
+  output  [ 7:0]  up_es_sel_3,
+  output          up_es_enb_3,
+  output  [11:0]  up_es_addr_3,
+  output          up_es_wr_3,
+  output  [15:0]  up_es_wdata_3,
+  input   [15:0]  up_es_rdata_3,
+  input           up_es_ready_3,
+
+  output          up_ch_pll_rst_3,
+  input           up_ch_pll_locked_3,
+  output          up_ch_rst_3,
+  output          up_ch_user_ready_3,
+  input           up_ch_rst_done_3,
+  output          up_ch_lpm_dfe_n_3,
+  output  [ 2:0]  up_ch_rate_3,
+  output  [ 1:0]  up_ch_sys_clk_sel_3,
+  output  [ 2:0]  up_ch_out_clk_sel_3,
+  output  [ 7:0]  up_ch_sel_3,
+  output          up_ch_enb_3,
+  output  [11:0]  up_ch_addr_3,
+  output          up_ch_wr_3,
+  output  [15:0]  up_ch_wdata_3,
+  input   [15:0]  up_ch_rdata_3,
+  input           up_ch_ready_3,
+
+  output  [ 7:0]  up_cm_sel_4,
+  output          up_cm_enb_4,
+  output  [11:0]  up_cm_addr_4,
+  output          up_cm_wr_4,
+  output  [15:0]  up_cm_wdata_4,
+  input   [15:0]  up_cm_rdata_4,
+  input           up_cm_ready_4,
+
+  output  [ 7:0]  up_es_sel_4,
+  output          up_es_enb_4,
+  output  [11:0]  up_es_addr_4,
+  output          up_es_wr_4,
+  output  [15:0]  up_es_wdata_4,
+  input   [15:0]  up_es_rdata_4,
+  input           up_es_ready_4,
+
+  output          up_ch_pll_rst_4,
+  input           up_ch_pll_locked_4,
+  output          up_ch_rst_4,
+  output          up_ch_user_ready_4,
+  input           up_ch_rst_done_4,
+  output          up_ch_lpm_dfe_n_4,
+  output  [ 2:0]  up_ch_rate_4,
+  output  [ 1:0]  up_ch_sys_clk_sel_4,
+  output  [ 2:0]  up_ch_out_clk_sel_4,
+  output  [ 7:0]  up_ch_sel_4,
+  output          up_ch_enb_4,
+  output  [11:0]  up_ch_addr_4,
+  output          up_ch_wr_4,
+  output  [15:0]  up_ch_wdata_4,
+  input   [15:0]  up_ch_rdata_4,
+  input           up_ch_ready_4,
+
+  output  [ 7:0]  up_es_sel_5,
+  output          up_es_enb_5,
+  output  [11:0]  up_es_addr_5,
+  output          up_es_wr_5,
+  output  [15:0]  up_es_wdata_5,
+  input   [15:0]  up_es_rdata_5,
+  input           up_es_ready_5,
+
+  output          up_ch_pll_rst_5,
+  input           up_ch_pll_locked_5,
+  output          up_ch_rst_5,
+  output          up_ch_user_ready_5,
+  input           up_ch_rst_done_5,
+  output          up_ch_lpm_dfe_n_5,
+  output  [ 2:0]  up_ch_rate_5,
+  output  [ 1:0]  up_ch_sys_clk_sel_5,
+  output  [ 2:0]  up_ch_out_clk_sel_5,
+  output  [ 7:0]  up_ch_sel_5,
+  output          up_ch_enb_5,
+  output  [11:0]  up_ch_addr_5,
+  output          up_ch_wr_5,
+  output  [15:0]  up_ch_wdata_5,
+  input   [15:0]  up_ch_rdata_5,
+  input           up_ch_ready_5,
+
+  output  [ 7:0]  up_es_sel_6,
+  output          up_es_enb_6,
+  output  [11:0]  up_es_addr_6,
+  output          up_es_wr_6,
+  output  [15:0]  up_es_wdata_6,
+  input   [15:0]  up_es_rdata_6,
+  input           up_es_ready_6,
+
+  output          up_ch_pll_rst_6,
+  input           up_ch_pll_locked_6,
+  output          up_ch_rst_6,
+  output          up_ch_user_ready_6,
+  input           up_ch_rst_done_6,
+  output          up_ch_lpm_dfe_n_6,
+  output  [ 2:0]  up_ch_rate_6,
+  output  [ 1:0]  up_ch_sys_clk_sel_6,
+  output  [ 2:0]  up_ch_out_clk_sel_6,
+  output  [ 7:0]  up_ch_sel_6,
+  output          up_ch_enb_6,
+  output  [11:0]  up_ch_addr_6,
+  output          up_ch_wr_6,
+  output  [15:0]  up_ch_wdata_6,
+  input   [15:0]  up_ch_rdata_6,
+  input           up_ch_ready_6,
+
+  output  [ 7:0]  up_es_sel_7,
+  output          up_es_enb_7,
+  output  [11:0]  up_es_addr_7,
+  output          up_es_wr_7,
+  output  [15:0]  up_es_wdata_7,
+  input   [15:0]  up_es_rdata_7,
+  input           up_es_ready_7,
+
+  output          up_ch_pll_rst_7,
+  input           up_ch_pll_locked_7,
+  output          up_ch_rst_7,
+  output          up_ch_user_ready_7,
+  input           up_ch_rst_done_7,
+  output          up_ch_lpm_dfe_n_7,
+  output  [ 2:0]  up_ch_rate_7,
+  output  [ 1:0]  up_ch_sys_clk_sel_7,
+  output  [ 2:0]  up_ch_out_clk_sel_7,
+  output  [ 7:0]  up_ch_sel_7,
+  output          up_ch_enb_7,
+  output  [11:0]  up_ch_addr_7,
+  output          up_ch_wr_7,
+  output  [15:0]  up_ch_wdata_7,
+  input   [15:0]  up_ch_rdata_7,
+  input           up_ch_ready_7,
+
+  output  [ 7:0]  up_cm_sel_8,
+  output          up_cm_enb_8,
+  output  [11:0]  up_cm_addr_8,
+  output          up_cm_wr_8,
+  output  [15:0]  up_cm_wdata_8,
+  input   [15:0]  up_cm_rdata_8,
+  input           up_cm_ready_8,
+
+  output  [ 7:0]  up_es_sel_8,
+  output          up_es_enb_8,
+  output  [11:0]  up_es_addr_8,
+  output          up_es_wr_8,
+  output  [15:0]  up_es_wdata_8,
+  input   [15:0]  up_es_rdata_8,
+  input           up_es_ready_8,
+
+  output          up_ch_pll_rst_8,
+  input           up_ch_pll_locked_8,
+  output          up_ch_rst_8,
+  output          up_ch_user_ready_8,
+  input           up_ch_rst_done_8,
+  output          up_ch_lpm_dfe_n_8,
+  output  [ 2:0]  up_ch_rate_8,
+  output  [ 1:0]  up_ch_sys_clk_sel_8,
+  output  [ 2:0]  up_ch_out_clk_sel_8,
+  output  [ 7:0]  up_ch_sel_8,
+  output          up_ch_enb_8,
+  output  [11:0]  up_ch_addr_8,
+  output          up_ch_wr_8,
+  output  [15:0]  up_ch_wdata_8,
+  input   [15:0]  up_ch_rdata_8,
+  input           up_ch_ready_8,
+
+  output  [ 7:0]  up_es_sel_9,
+  output          up_es_enb_9,
+  output  [11:0]  up_es_addr_9,
+  output          up_es_wr_9,
+  output  [15:0]  up_es_wdata_9,
+  input   [15:0]  up_es_rdata_9,
+  input           up_es_ready_9,
+
+  output          up_ch_pll_rst_9,
+  input           up_ch_pll_locked_9,
+  output          up_ch_rst_9,
+  output          up_ch_user_ready_9,
+  input           up_ch_rst_done_9,
+  output          up_ch_lpm_dfe_n_9,
+  output  [ 2:0]  up_ch_rate_9,
+  output  [ 1:0]  up_ch_sys_clk_sel_9,
+  output  [ 2:0]  up_ch_out_clk_sel_9,
+  output  [ 7:0]  up_ch_sel_9,
+  output          up_ch_enb_9,
+  output  [11:0]  up_ch_addr_9,
+  output          up_ch_wr_9,
+  output  [15:0]  up_ch_wdata_9,
+  input   [15:0]  up_ch_rdata_9,
+  input           up_ch_ready_9,
+
+  output  [ 7:0]  up_es_sel_10,
+  output          up_es_enb_10,
+  output  [11:0]  up_es_addr_10,
+  output          up_es_wr_10,
+  output  [15:0]  up_es_wdata_10,
+  input   [15:0]  up_es_rdata_10,
+  input           up_es_ready_10,
+
+  output          up_ch_pll_rst_10,
+  input           up_ch_pll_locked_10,
+  output          up_ch_rst_10,
+  output          up_ch_user_ready_10,
+  input           up_ch_rst_done_10,
+  output          up_ch_lpm_dfe_n_10,
+  output  [ 2:0]  up_ch_rate_10,
+  output  [ 1:0]  up_ch_sys_clk_sel_10,
+  output  [ 2:0]  up_ch_out_clk_sel_10,
+  output  [ 7:0]  up_ch_sel_10,
+  output          up_ch_enb_10,
+  output  [11:0]  up_ch_addr_10,
+  output          up_ch_wr_10,
+  output  [15:0]  up_ch_wdata_10,
+  input   [15:0]  up_ch_rdata_10,
+  input           up_ch_ready_10,
+
+  output  [ 7:0]  up_es_sel_11,
+  output          up_es_enb_11,
+  output  [11:0]  up_es_addr_11,
+  output          up_es_wr_11,
+  output  [15:0]  up_es_wdata_11,
+  input   [15:0]  up_es_rdata_11,
+  input           up_es_ready_11,
+
+  output          up_ch_pll_rst_11,
+  input           up_ch_pll_locked_11,
+  output          up_ch_rst_11,
+  output          up_ch_user_ready_11,
+  input           up_ch_rst_done_11,
+  output          up_ch_lpm_dfe_n_11,
+  output  [ 2:0]  up_ch_rate_11,
+  output  [ 1:0]  up_ch_sys_clk_sel_11,
+  output  [ 2:0]  up_ch_out_clk_sel_11,
+  output  [ 7:0]  up_ch_sel_11,
+  output          up_ch_enb_11,
+  output  [11:0]  up_ch_addr_11,
+  output          up_ch_wr_11,
+  output  [15:0]  up_ch_wdata_11,
+  input   [15:0]  up_ch_rdata_11,
+  input           up_ch_ready_11,
+
+  output  [ 7:0]  up_cm_sel_12,
+  output          up_cm_enb_12,
+  output  [11:0]  up_cm_addr_12,
+  output          up_cm_wr_12,
+  output  [15:0]  up_cm_wdata_12,
+  input   [15:0]  up_cm_rdata_12,
+  input           up_cm_ready_12,
+
+  output  [ 7:0]  up_es_sel_12,
+  output          up_es_enb_12,
+  output  [11:0]  up_es_addr_12,
+  output          up_es_wr_12,
+  output  [15:0]  up_es_wdata_12,
+  input   [15:0]  up_es_rdata_12,
+  input           up_es_ready_12,
+
+  output          up_ch_pll_rst_12,
+  input           up_ch_pll_locked_12,
+  output          up_ch_rst_12,
+  output          up_ch_user_ready_12,
+  input           up_ch_rst_done_12,
+  output          up_ch_lpm_dfe_n_12,
+  output  [ 2:0]  up_ch_rate_12,
+  output  [ 1:0]  up_ch_sys_clk_sel_12,
+  output  [ 2:0]  up_ch_out_clk_sel_12,
+  output  [ 7:0]  up_ch_sel_12,
+  output          up_ch_enb_12,
+  output  [11:0]  up_ch_addr_12,
+  output          up_ch_wr_12,
+  output  [15:0]  up_ch_wdata_12,
+  input   [15:0]  up_ch_rdata_12,
+  input           up_ch_ready_12,
+
+  output  [ 7:0]  up_es_sel_13,
+  output          up_es_enb_13,
+  output  [11:0]  up_es_addr_13,
+  output          up_es_wr_13,
+  output  [15:0]  up_es_wdata_13,
+  input   [15:0]  up_es_rdata_13,
+  input           up_es_ready_13,
+
+  output          up_ch_pll_rst_13,
+  input           up_ch_pll_locked_13,
+  output          up_ch_rst_13,
+  output          up_ch_user_ready_13,
+  input           up_ch_rst_done_13,
+  output          up_ch_lpm_dfe_n_13,
+  output  [ 2:0]  up_ch_rate_13,
+  output  [ 1:0]  up_ch_sys_clk_sel_13,
+  output  [ 2:0]  up_ch_out_clk_sel_13,
+  output  [ 7:0]  up_ch_sel_13,
+  output          up_ch_enb_13,
+  output  [11:0]  up_ch_addr_13,
+  output          up_ch_wr_13,
+  output  [15:0]  up_ch_wdata_13,
+  input   [15:0]  up_ch_rdata_13,
+  input           up_ch_ready_13,
+
+  output  [ 7:0]  up_es_sel_14,
+  output          up_es_enb_14,
+  output  [11:0]  up_es_addr_14,
+  output          up_es_wr_14,
+  output  [15:0]  up_es_wdata_14,
+  input   [15:0]  up_es_rdata_14,
+  input           up_es_ready_14,
+
+  output          up_ch_pll_rst_14,
+  input           up_ch_pll_locked_14,
+  output          up_ch_rst_14,
+  output          up_ch_user_ready_14,
+  input           up_ch_rst_done_14,
+  output          up_ch_lpm_dfe_n_14,
+  output  [ 2:0]  up_ch_rate_14,
+  output  [ 1:0]  up_ch_sys_clk_sel_14,
+  output  [ 2:0]  up_ch_out_clk_sel_14,
+  output  [ 7:0]  up_ch_sel_14,
+  output          up_ch_enb_14,
+  output  [11:0]  up_ch_addr_14,
+  output          up_ch_wr_14,
+  output  [15:0]  up_ch_wdata_14,
+  input   [15:0]  up_ch_rdata_14,
+  input           up_ch_ready_14,
+
+  output  [ 7:0]  up_es_sel_15,
+  output          up_es_enb_15,
+  output  [11:0]  up_es_addr_15,
+  output          up_es_wr_15,
+  output  [15:0]  up_es_wdata_15,
+  input   [15:0]  up_es_rdata_15,
+  input           up_es_ready_15,
+
+  output          up_ch_pll_rst_15,
+  input           up_ch_pll_locked_15,
+  output          up_ch_rst_15,
+  output          up_ch_user_ready_15,
+  input           up_ch_rst_done_15,
+  output          up_ch_lpm_dfe_n_15,
+  output  [ 2:0]  up_ch_rate_15,
+  output  [ 1:0]  up_ch_sys_clk_sel_15,
+  output  [ 2:0]  up_ch_out_clk_sel_15,
+  output  [ 7:0]  up_ch_sel_15,
+  output          up_ch_enb_15,
+  output  [11:0]  up_ch_addr_15,
+  output          up_ch_wr_15,
+  output  [15:0]  up_ch_wdata_15,
+  input   [15:0]  up_ch_rdata_15,
+  input           up_ch_ready_15,
+
+  input           axi_clk,
+  input           axi_aresetn,
+
+  input           s_axi_awvalid,
+  input   [31:0]  s_axi_awaddr,
+  input   [ 2:0]  s_axi_awprot,
+  output          s_axi_awready,
+  input           s_axi_wvalid,
+  input   [31:0]  s_axi_wdata,
+  input   [ 3:0]  s_axi_wstrb,
+  output          s_axi_wready,
+  output          s_axi_bvalid,
+  output  [ 1:0]  s_axi_bresp,
+  input           s_axi_bready,
+  input           s_axi_arvalid,
+  input   [31:0]  s_axi_araddr,
+  input   [ 2:0]  s_axi_arprot,
+  output          s_axi_arready,
+  output          s_axi_rvalid,
+  output  [ 1:0]  s_axi_rresp,
+  output  [31:0]  s_axi_rdata,
+  input           s_axi_rready,
+
+  output          m_axi_awvalid,
+  output  [31:0]  m_axi_awaddr,
+  output  [ 2:0]  m_axi_awprot,
+  input           m_axi_awready,
+  output          m_axi_wvalid,
+  output  [31:0]  m_axi_wdata,
+  output  [ 3:0]  m_axi_wstrb,
+  input           m_axi_wready,
+  input           m_axi_bvalid,
+  input   [ 1:0]  m_axi_bresp,
+  output          m_axi_bready,
+  output          m_axi_arvalid,
+  output  [31:0]  m_axi_araddr,
+  output  [ 2:0]  m_axi_arprot,
+  input           m_axi_arready,
+  input           m_axi_rvalid,
+  input   [31:0]  m_axi_rdata,
+  input   [ 1:0]  m_axi_rresp,
+  output          m_axi_rready);
+
+  // parameters
+
+  parameter   integer ID = 0;
+  parameter   integer NUM_OF_LANES = 8;
+  parameter   integer GTH_OR_GTX_N = 0;
+  parameter   integer TX_OR_RX_N = 0;
+  parameter   integer QPLL_ENABLE = 1;
+
+  // internal signals
+
+  wire    [ 7:0]  up_cm_sel;
+  wire            up_cm_enb;
+  wire    [11:0]  up_cm_addr;
+  wire            up_cm_wr;
+  wire    [15:0]  up_cm_wdata;
+  wire    [15:0]  up_cm_rdata_0_s;
+  wire            up_cm_ready_0_s;
+  wire    [15:0]  up_cm_rdata_4_s;
+  wire            up_cm_ready_4_s;
+  wire    [15:0]  up_cm_rdata_8_s;
+  wire            up_cm_ready_8_s;
+  wire    [15:0]  up_cm_rdata_12_s;
+  wire            up_cm_ready_12_s;
+  wire    [ 7:0]  up_es_sel;
+  wire            up_es_enb;
+  wire    [11:0]  up_es_addr;
+  wire            up_es_wr;
+  wire    [15:0]  up_es_wdata;
+  wire    [15:0]  up_es_rdata_0_s;
+  wire            up_es_ready_0_s;
+  wire    [15:0]  up_es_rdata_1_s;
+  wire            up_es_ready_1_s;
+  wire    [15:0]  up_es_rdata_2_s;
+  wire            up_es_ready_2_s;
+  wire    [15:0]  up_es_rdata_3_s;
+  wire            up_es_ready_3_s;
+  wire    [15:0]  up_es_rdata_4_s;
+  wire            up_es_ready_4_s;
+  wire    [15:0]  up_es_rdata_5_s;
+  wire            up_es_ready_5_s;
+  wire    [15:0]  up_es_rdata_6_s;
+  wire            up_es_ready_6_s;
+  wire    [15:0]  up_es_rdata_7_s;
+  wire            up_es_ready_7_s;
+  wire    [15:0]  up_es_rdata_8_s;
+  wire            up_es_ready_8_s;
+  wire    [15:0]  up_es_rdata_9_s;
+  wire            up_es_ready_9_s;
+  wire    [15:0]  up_es_rdata_10_s;
+  wire            up_es_ready_10_s;
+  wire    [15:0]  up_es_rdata_11_s;
+  wire            up_es_ready_11_s;
+  wire    [15:0]  up_es_rdata_12_s;
+  wire            up_es_ready_12_s;
+  wire    [15:0]  up_es_rdata_13_s;
+  wire            up_es_ready_13_s;
+  wire    [15:0]  up_es_rdata_14_s;
+  wire            up_es_ready_14_s;
+  wire    [15:0]  up_es_rdata_15_s;
+  wire            up_es_ready_15_s;
+  wire            up_ch_pll_rst;
+  wire            up_ch_rst;
+  wire            up_ch_user_ready;
+  wire            up_ch_lpm_dfe_n;
+  wire    [ 2:0]  up_ch_rate;
+  wire    [ 1:0]  up_ch_sys_clk_sel;
+  wire    [ 2:0]  up_ch_out_clk_sel;
+  wire            up_ch_pll_locked_0_s;
+  wire            up_ch_rst_done_0_s;
+  wire            up_ch_pll_locked_1_s;
+  wire            up_ch_rst_done_1_s;
+  wire            up_ch_pll_locked_2_s;
+  wire            up_ch_rst_done_2_s;
+  wire            up_ch_pll_locked_3_s;
+  wire            up_ch_rst_done_3_s;
+  wire            up_ch_pll_locked_4_s;
+  wire            up_ch_rst_done_4_s;
+  wire            up_ch_pll_locked_5_s;
+  wire            up_ch_rst_done_5_s;
+  wire            up_ch_pll_locked_6_s;
+  wire            up_ch_rst_done_6_s;
+  wire            up_ch_pll_locked_7_s;
+  wire            up_ch_rst_done_7_s;
+  wire            up_ch_pll_locked_8_s;
+  wire            up_ch_rst_done_8_s;
+  wire            up_ch_pll_locked_9_s;
+  wire            up_ch_rst_done_9_s;
+  wire            up_ch_pll_locked_10_s;
+  wire            up_ch_rst_done_10_s;
+  wire            up_ch_pll_locked_11_s;
+  wire            up_ch_rst_done_11_s;
+  wire            up_ch_pll_locked_12_s;
+  wire            up_ch_rst_done_12_s;
+  wire            up_ch_pll_locked_13_s;
+  wire            up_ch_rst_done_13_s;
+  wire            up_ch_pll_locked_14_s;
+  wire            up_ch_rst_done_14_s;
+  wire            up_ch_pll_locked_15_s;
+  wire            up_ch_rst_done_15_s;
+  wire    [ 7:0]  up_ch_sel;
+  wire            up_ch_enb;
+  wire    [11:0]  up_ch_addr;
+  wire            up_ch_wr;
+  wire    [15:0]  up_ch_wdata;
+  wire    [15:0]  up_ch_rdata_0_s;
+  wire            up_ch_ready_0_s;
+  wire    [15:0]  up_ch_rdata_1_s;
+  wire            up_ch_ready_1_s;
+  wire    [15:0]  up_ch_rdata_2_s;
+  wire            up_ch_ready_2_s;
+  wire    [15:0]  up_ch_rdata_3_s;
+  wire            up_ch_ready_3_s;
+  wire    [15:0]  up_ch_rdata_4_s;
+  wire            up_ch_ready_4_s;
+  wire    [15:0]  up_ch_rdata_5_s;
+  wire            up_ch_ready_5_s;
+  wire    [15:0]  up_ch_rdata_6_s;
+  wire            up_ch_ready_6_s;
+  wire    [15:0]  up_ch_rdata_7_s;
+  wire            up_ch_ready_7_s;
+  wire    [15:0]  up_ch_rdata_8_s;
+  wire            up_ch_ready_8_s;
+  wire    [15:0]  up_ch_rdata_9_s;
+  wire            up_ch_ready_9_s;
+  wire    [15:0]  up_ch_rdata_10_s;
+  wire            up_ch_ready_10_s;
+  wire    [15:0]  up_ch_rdata_11_s;
+  wire            up_ch_ready_11_s;
+  wire    [15:0]  up_ch_rdata_12_s;
+  wire            up_ch_ready_12_s;
+  wire    [15:0]  up_ch_rdata_13_s;
+  wire            up_ch_ready_13_s;
+  wire    [15:0]  up_ch_rdata_14_s;
+  wire            up_ch_ready_14_s;
+  wire    [15:0]  up_ch_rdata_15_s;
+  wire            up_ch_ready_15_s;
+  wire            up_es_req;
+  wire            up_es_ack;
+  wire    [ 4:0]  up_es_pscale;
+  wire    [ 1:0]  up_es_vrange;
+  wire    [ 7:0]  up_es_vstep;
+  wire    [ 7:0]  up_es_vmax;
+  wire    [ 7:0]  up_es_vmin;
+  wire    [11:0]  up_es_hmax;
+  wire    [11:0]  up_es_hmin;
+  wire    [11:0]  up_es_hstep;
+  wire    [31:0]  up_es_saddr;
+  wire            up_es_status;
+  wire            up_rstn;
+  wire            up_clk;
+  wire            up_wreq;
+  wire    [ 9:0]  up_waddr;
+  wire    [31:0]  up_wdata;
+  wire            up_wack;
+  wire            up_rreq;
+  wire    [ 9:0]  up_raddr;
+  wire    [31:0]  up_rdata;
+  wire            up_rack;
+
+  // channel broadcast
+
+  assign up_rstn = axi_aresetn;
+  assign up_clk = axi_clk;
+
+  assign up_cm_sel_0 = up_cm_sel;
+  assign up_cm_enb_0 = up_cm_enb;
+  assign up_cm_addr_0 = up_cm_addr;
+  assign up_cm_wr_0 = up_cm_wr;
+  assign up_cm_wdata_0 = up_cm_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(0)) i_mdrp_cm_0 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_cm_sel),
+    .up_enb (up_cm_enb),
+    .up_rdata_in (16'd0),
+    .up_ready_in (1'd0),
+    .up_rdata (up_cm_rdata_0),
+    .up_ready (up_cm_ready_0),
+    .up_rdata_out (up_cm_rdata_0_s),
+    .up_ready_out (up_cm_ready_0_s));
+
+  assign up_es_sel_0 = up_es_sel;
+  assign up_es_enb_0 = up_es_enb;
+  assign up_es_addr_0 = up_es_addr;
+  assign up_es_wr_0 = up_es_wr;
+  assign up_es_wdata_0 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(0)) i_mdrp_es_0 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (16'd0),
+    .up_ready_in (1'd0),
+    .up_rdata (up_es_rdata_0),
+    .up_ready (up_es_ready_0),
+    .up_rdata_out (up_es_rdata_0_s),
+    .up_ready_out (up_es_ready_0_s));
+
+  assign up_ch_pll_rst_0 = up_ch_pll_rst;
+  assign up_ch_rst_0 = up_ch_rst;
+  assign up_ch_user_ready_0 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_0 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_0 = up_ch_rate;
+  assign up_ch_sys_clk_sel_0 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_0 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_0 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (1'd1),
+    .up_rst_done_in (1'd1),
+    .up_pll_locked (up_ch_pll_locked_0),
+    .up_rst_done (up_ch_rst_done_0),
+    .up_pll_locked_out (up_ch_pll_locked_0_s),
+    .up_rst_done_out (up_ch_rst_done_0_s));
+
+  assign up_ch_sel_0 = up_ch_sel;
+  assign up_ch_enb_0 = up_ch_enb;
+  assign up_ch_addr_0 = up_ch_addr;
+  assign up_ch_wr_0 = up_ch_wr;
+  assign up_ch_wdata_0 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(0)) i_mdrp_ch_0 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (16'd0),
+    .up_ready_in (1'd0),
+    .up_rdata (up_ch_rdata_0),
+    .up_ready (up_ch_ready_0),
+    .up_rdata_out (up_ch_rdata_0_s),
+    .up_ready_out (up_ch_ready_0_s));
+
+  assign up_es_sel_1 = up_es_sel;
+  assign up_es_enb_1 = up_es_enb;
+  assign up_es_addr_1 = up_es_addr;
+  assign up_es_wr_1 = up_es_wr;
+  assign up_es_wdata_1 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(1)) i_mdrp_es_1 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_0_s),
+    .up_ready_in (up_es_ready_0_s),
+    .up_rdata (up_es_rdata_1),
+    .up_ready (up_es_ready_1),
+    .up_rdata_out (up_es_rdata_1_s),
+    .up_ready_out (up_es_ready_1_s));
+
+  assign up_ch_pll_rst_1 = up_ch_pll_rst;
+  assign up_ch_rst_1 = up_ch_rst;
+  assign up_ch_user_ready_1 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_1 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_1 = up_ch_rate;
+  assign up_ch_sys_clk_sel_1 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_1 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_1 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_0_s),
+    .up_rst_done_in (up_ch_rst_done_0_s),
+    .up_pll_locked (up_ch_pll_locked_1),
+    .up_rst_done (up_ch_rst_done_1),
+    .up_pll_locked_out (up_ch_pll_locked_1_s),
+    .up_rst_done_out (up_ch_rst_done_1_s));
+
+  assign up_ch_sel_1 = up_ch_sel;
+  assign up_ch_enb_1 = up_ch_enb;
+  assign up_ch_addr_1 = up_ch_addr;
+  assign up_ch_wr_1 = up_ch_wr;
+  assign up_ch_wdata_1 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(1)) i_mdrp_ch_1 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_0_s),
+    .up_ready_in (up_ch_ready_0_s),
+    .up_rdata (up_ch_rdata_1),
+    .up_ready (up_ch_ready_1),
+    .up_rdata_out (up_ch_rdata_1_s),
+    .up_ready_out (up_ch_ready_1_s));
+
+  assign up_es_sel_2 = up_es_sel;
+  assign up_es_enb_2 = up_es_enb;
+  assign up_es_addr_2 = up_es_addr;
+  assign up_es_wr_2 = up_es_wr;
+  assign up_es_wdata_2 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(2)) i_mdrp_es_2 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_1_s),
+    .up_ready_in (up_es_ready_1_s),
+    .up_rdata (up_es_rdata_2),
+    .up_ready (up_es_ready_2),
+    .up_rdata_out (up_es_rdata_2_s),
+    .up_ready_out (up_es_ready_2_s));
+
+  assign up_ch_pll_rst_2 = up_ch_pll_rst;
+  assign up_ch_rst_2 = up_ch_rst;
+  assign up_ch_user_ready_2 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_2 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_2 = up_ch_rate;
+  assign up_ch_sys_clk_sel_2 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_2 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_2 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_1_s),
+    .up_rst_done_in (up_ch_rst_done_1_s),
+    .up_pll_locked (up_ch_pll_locked_2),
+    .up_rst_done (up_ch_rst_done_2),
+    .up_pll_locked_out (up_ch_pll_locked_2_s),
+    .up_rst_done_out (up_ch_rst_done_2_s));
+
+  assign up_ch_sel_2 = up_ch_sel;
+  assign up_ch_enb_2 = up_ch_enb;
+  assign up_ch_addr_2 = up_ch_addr;
+  assign up_ch_wr_2 = up_ch_wr;
+  assign up_ch_wdata_2 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(2)) i_mdrp_ch_2 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_1_s),
+    .up_ready_in (up_ch_ready_1_s),
+    .up_rdata (up_ch_rdata_2),
+    .up_ready (up_ch_ready_2),
+    .up_rdata_out (up_ch_rdata_2_s),
+    .up_ready_out (up_ch_ready_2_s));
+
+  assign up_es_sel_3 = up_es_sel;
+  assign up_es_enb_3 = up_es_enb;
+  assign up_es_addr_3 = up_es_addr;
+  assign up_es_wr_3 = up_es_wr;
+  assign up_es_wdata_3 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(3)) i_mdrp_es_3 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_2_s),
+    .up_ready_in (up_es_ready_2_s),
+    .up_rdata (up_es_rdata_3),
+    .up_ready (up_es_ready_3),
+    .up_rdata_out (up_es_rdata_3_s),
+    .up_ready_out (up_es_ready_3_s));
+
+  assign up_ch_pll_rst_3 = up_ch_pll_rst;
+  assign up_ch_rst_3 = up_ch_rst;
+  assign up_ch_user_ready_3 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_3 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_3 = up_ch_rate;
+  assign up_ch_sys_clk_sel_3 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_3 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_3 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_2_s),
+    .up_rst_done_in (up_ch_rst_done_2_s),
+    .up_pll_locked (up_ch_pll_locked_3),
+    .up_rst_done (up_ch_rst_done_3),
+    .up_pll_locked_out (up_ch_pll_locked_3_s),
+    .up_rst_done_out (up_ch_rst_done_3_s));
+
+  assign up_ch_sel_3 = up_ch_sel;
+  assign up_ch_enb_3 = up_ch_enb;
+  assign up_ch_addr_3 = up_ch_addr;
+  assign up_ch_wr_3 = up_ch_wr;
+  assign up_ch_wdata_3 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(3)) i_mdrp_ch_3 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_2_s),
+    .up_ready_in (up_ch_ready_2_s),
+    .up_rdata (up_ch_rdata_3),
+    .up_ready (up_ch_ready_3),
+    .up_rdata_out (up_ch_rdata_3_s),
+    .up_ready_out (up_ch_ready_3_s));
+
+  assign up_cm_sel_4 = up_cm_sel;
+  assign up_cm_enb_4 = up_cm_enb;
+  assign up_cm_addr_4 = up_cm_addr;
+  assign up_cm_wr_4 = up_cm_wr;
+  assign up_cm_wdata_4 = up_cm_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(4)) i_mdrp_cm_4 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_cm_sel),
+    .up_enb (up_cm_enb),
+    .up_rdata_in (up_cm_rdata_0_s),
+    .up_ready_in (up_cm_ready_0_s),
+    .up_rdata (up_cm_rdata_4),
+    .up_ready (up_cm_ready_4),
+    .up_rdata_out (up_cm_rdata_4_s),
+    .up_ready_out (up_cm_ready_4_s));
+
+  assign up_es_sel_4 = up_es_sel;
+  assign up_es_enb_4 = up_es_enb;
+  assign up_es_addr_4 = up_es_addr;
+  assign up_es_wr_4 = up_es_wr;
+  assign up_es_wdata_4 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(4)) i_mdrp_es_4 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_3_s),
+    .up_ready_in (up_es_ready_3_s),
+    .up_rdata (up_es_rdata_4),
+    .up_ready (up_es_ready_4),
+    .up_rdata_out (up_es_rdata_4_s),
+    .up_ready_out (up_es_ready_4_s));
+
+  assign up_ch_pll_rst_4 = up_ch_pll_rst;
+  assign up_ch_rst_4 = up_ch_rst;
+  assign up_ch_user_ready_4 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_4 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_4 = up_ch_rate;
+  assign up_ch_sys_clk_sel_4 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_4 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_4 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_3_s),
+    .up_rst_done_in (up_ch_rst_done_3_s),
+    .up_pll_locked (up_ch_pll_locked_4),
+    .up_rst_done (up_ch_rst_done_4),
+    .up_pll_locked_out (up_ch_pll_locked_4_s),
+    .up_rst_done_out (up_ch_rst_done_4_s));
+
+  assign up_ch_sel_4 = up_ch_sel;
+  assign up_ch_enb_4 = up_ch_enb;
+  assign up_ch_addr_4 = up_ch_addr;
+  assign up_ch_wr_4 = up_ch_wr;
+  assign up_ch_wdata_4 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(4)) i_mdrp_ch_4 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_3_s),
+    .up_ready_in (up_ch_ready_3_s),
+    .up_rdata (up_ch_rdata_4),
+    .up_ready (up_ch_ready_4),
+    .up_rdata_out (up_ch_rdata_4_s),
+    .up_ready_out (up_ch_ready_4_s));
+
+  assign up_es_sel_5 = up_es_sel;
+  assign up_es_enb_5 = up_es_enb;
+  assign up_es_addr_5 = up_es_addr;
+  assign up_es_wr_5 = up_es_wr;
+  assign up_es_wdata_5 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(5)) i_mdrp_es_5 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_4_s),
+    .up_ready_in (up_es_ready_4_s),
+    .up_rdata (up_es_rdata_5),
+    .up_ready (up_es_ready_5),
+    .up_rdata_out (up_es_rdata_5_s),
+    .up_ready_out (up_es_ready_5_s));
+
+  assign up_ch_pll_rst_5 = up_ch_pll_rst;
+  assign up_ch_rst_5 = up_ch_rst;
+  assign up_ch_user_ready_5 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_5 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_5 = up_ch_rate;
+  assign up_ch_sys_clk_sel_5 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_5 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_5 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_4_s),
+    .up_rst_done_in (up_ch_rst_done_4_s),
+    .up_pll_locked (up_ch_pll_locked_5),
+    .up_rst_done (up_ch_rst_done_5),
+    .up_pll_locked_out (up_ch_pll_locked_5_s),
+    .up_rst_done_out (up_ch_rst_done_5_s));
+
+  assign up_ch_sel_5 = up_ch_sel;
+  assign up_ch_enb_5 = up_ch_enb;
+  assign up_ch_addr_5 = up_ch_addr;
+  assign up_ch_wr_5 = up_ch_wr;
+  assign up_ch_wdata_5 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(5)) i_mdrp_ch_5 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_4_s),
+    .up_ready_in (up_ch_ready_4_s),
+    .up_rdata (up_ch_rdata_5),
+    .up_ready (up_ch_ready_5),
+    .up_rdata_out (up_ch_rdata_5_s),
+    .up_ready_out (up_ch_ready_5_s));
+
+  assign up_es_sel_6 = up_es_sel;
+  assign up_es_enb_6 = up_es_enb;
+  assign up_es_addr_6 = up_es_addr;
+  assign up_es_wr_6 = up_es_wr;
+  assign up_es_wdata_6 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(6)) i_mdrp_es_6 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_5_s),
+    .up_ready_in (up_es_ready_5_s),
+    .up_rdata (up_es_rdata_6),
+    .up_ready (up_es_ready_6),
+    .up_rdata_out (up_es_rdata_6_s),
+    .up_ready_out (up_es_ready_6_s));
+
+  assign up_ch_pll_rst_6 = up_ch_pll_rst;
+  assign up_ch_rst_6 = up_ch_rst;
+  assign up_ch_user_ready_6 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_6 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_6 = up_ch_rate;
+  assign up_ch_sys_clk_sel_6 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_6 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_6 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_5_s),
+    .up_rst_done_in (up_ch_rst_done_5_s),
+    .up_pll_locked (up_ch_pll_locked_6),
+    .up_rst_done (up_ch_rst_done_6),
+    .up_pll_locked_out (up_ch_pll_locked_6_s),
+    .up_rst_done_out (up_ch_rst_done_6_s));
+
+  assign up_ch_sel_6 = up_ch_sel;
+  assign up_ch_enb_6 = up_ch_enb;
+  assign up_ch_addr_6 = up_ch_addr;
+  assign up_ch_wr_6 = up_ch_wr;
+  assign up_ch_wdata_6 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(6)) i_mdrp_ch_6 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_5_s),
+    .up_ready_in (up_ch_ready_5_s),
+    .up_rdata (up_ch_rdata_6),
+    .up_ready (up_ch_ready_6),
+    .up_rdata_out (up_ch_rdata_6_s),
+    .up_ready_out (up_ch_ready_6_s));
+
+  assign up_es_sel_7 = up_es_sel;
+  assign up_es_enb_7 = up_es_enb;
+  assign up_es_addr_7 = up_es_addr;
+  assign up_es_wr_7 = up_es_wr;
+  assign up_es_wdata_7 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(7)) i_mdrp_es_7 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_6_s),
+    .up_ready_in (up_es_ready_6_s),
+    .up_rdata (up_es_rdata_7),
+    .up_ready (up_es_ready_7),
+    .up_rdata_out (up_es_rdata_7_s),
+    .up_ready_out (up_es_ready_7_s));
+
+  assign up_ch_pll_rst_7 = up_ch_pll_rst;
+  assign up_ch_rst_7 = up_ch_rst;
+  assign up_ch_user_ready_7 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_7 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_7 = up_ch_rate;
+  assign up_ch_sys_clk_sel_7 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_7 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_7 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_6_s),
+    .up_rst_done_in (up_ch_rst_done_6_s),
+    .up_pll_locked (up_ch_pll_locked_7),
+    .up_rst_done (up_ch_rst_done_7),
+    .up_pll_locked_out (up_ch_pll_locked_7_s),
+    .up_rst_done_out (up_ch_rst_done_7_s));
+
+  assign up_ch_sel_7 = up_ch_sel;
+  assign up_ch_enb_7 = up_ch_enb;
+  assign up_ch_addr_7 = up_ch_addr;
+  assign up_ch_wr_7 = up_ch_wr;
+  assign up_ch_wdata_7 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(7)) i_mdrp_ch_7 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_6_s),
+    .up_ready_in (up_ch_ready_6_s),
+    .up_rdata (up_ch_rdata_7),
+    .up_ready (up_ch_ready_7),
+    .up_rdata_out (up_ch_rdata_7_s),
+    .up_ready_out (up_ch_ready_7_s));
+
+  assign up_cm_sel_8 = up_cm_sel;
+  assign up_cm_enb_8 = up_cm_enb;
+  assign up_cm_addr_8 = up_cm_addr;
+  assign up_cm_wr_8 = up_cm_wr;
+  assign up_cm_wdata_8 = up_cm_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(8)) i_mdrp_cm_8 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_cm_sel),
+    .up_enb (up_cm_enb),
+    .up_rdata_in (up_cm_rdata_4_s),
+    .up_ready_in (up_cm_ready_4_s),
+    .up_rdata (up_cm_rdata_8),
+    .up_ready (up_cm_ready_8),
+    .up_rdata_out (up_cm_rdata_8_s),
+    .up_ready_out (up_cm_ready_8_s));
+
+  assign up_es_sel_8 = up_es_sel;
+  assign up_es_enb_8 = up_es_enb;
+  assign up_es_addr_8 = up_es_addr;
+  assign up_es_wr_8 = up_es_wr;
+  assign up_es_wdata_8 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(8)) i_mdrp_es_8 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_7_s),
+    .up_ready_in (up_es_ready_7_s),
+    .up_rdata (up_es_rdata_8),
+    .up_ready (up_es_ready_8),
+    .up_rdata_out (up_es_rdata_8_s),
+    .up_ready_out (up_es_ready_8_s));
+
+  assign up_ch_pll_rst_8 = up_ch_pll_rst;
+  assign up_ch_rst_8 = up_ch_rst;
+  assign up_ch_user_ready_8 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_8 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_8 = up_ch_rate;
+  assign up_ch_sys_clk_sel_8 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_8 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_8 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_7_s),
+    .up_rst_done_in (up_ch_rst_done_7_s),
+    .up_pll_locked (up_ch_pll_locked_8),
+    .up_rst_done (up_ch_rst_done_8),
+    .up_pll_locked_out (up_ch_pll_locked_8_s),
+    .up_rst_done_out (up_ch_rst_done_8_s));
+
+  assign up_ch_sel_8 = up_ch_sel;
+  assign up_ch_enb_8 = up_ch_enb;
+  assign up_ch_addr_8 = up_ch_addr;
+  assign up_ch_wr_8 = up_ch_wr;
+  assign up_ch_wdata_8 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(8)) i_mdrp_ch_8 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_7_s),
+    .up_ready_in (up_ch_ready_7_s),
+    .up_rdata (up_ch_rdata_8),
+    .up_ready (up_ch_ready_8),
+    .up_rdata_out (up_ch_rdata_8_s),
+    .up_ready_out (up_ch_ready_8_s));
+
+  assign up_es_sel_9 = up_es_sel;
+  assign up_es_enb_9 = up_es_enb;
+  assign up_es_addr_9 = up_es_addr;
+  assign up_es_wr_9 = up_es_wr;
+  assign up_es_wdata_9 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(9)) i_mdrp_es_9 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_8_s),
+    .up_ready_in (up_es_ready_8_s),
+    .up_rdata (up_es_rdata_9),
+    .up_ready (up_es_ready_9),
+    .up_rdata_out (up_es_rdata_9_s),
+    .up_ready_out (up_es_ready_9_s));
+
+  assign up_ch_pll_rst_9 = up_ch_pll_rst;
+  assign up_ch_rst_9 = up_ch_rst;
+  assign up_ch_user_ready_9 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_9 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_9 = up_ch_rate;
+  assign up_ch_sys_clk_sel_9 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_9 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_9 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_8_s),
+    .up_rst_done_in (up_ch_rst_done_8_s),
+    .up_pll_locked (up_ch_pll_locked_9),
+    .up_rst_done (up_ch_rst_done_9),
+    .up_pll_locked_out (up_ch_pll_locked_9_s),
+    .up_rst_done_out (up_ch_rst_done_9_s));
+
+  assign up_ch_sel_9 = up_ch_sel;
+  assign up_ch_enb_9 = up_ch_enb;
+  assign up_ch_addr_9 = up_ch_addr;
+  assign up_ch_wr_9 = up_ch_wr;
+  assign up_ch_wdata_9 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(9)) i_mdrp_ch_9 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_8_s),
+    .up_ready_in (up_ch_ready_8_s),
+    .up_rdata (up_ch_rdata_9),
+    .up_ready (up_ch_ready_9),
+    .up_rdata_out (up_ch_rdata_9_s),
+    .up_ready_out (up_ch_ready_9_s));
+
+  assign up_es_sel_10 = up_es_sel;
+  assign up_es_enb_10 = up_es_enb;
+  assign up_es_addr_10 = up_es_addr;
+  assign up_es_wr_10 = up_es_wr;
+  assign up_es_wdata_10 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(10)) i_mdrp_es_10 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_9_s),
+    .up_ready_in (up_es_ready_9_s),
+    .up_rdata (up_es_rdata_10),
+    .up_ready (up_es_ready_10),
+    .up_rdata_out (up_es_rdata_10_s),
+    .up_ready_out (up_es_ready_10_s));
+
+  assign up_ch_pll_rst_10 = up_ch_pll_rst;
+  assign up_ch_rst_10 = up_ch_rst;
+  assign up_ch_user_ready_10 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_10 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_10 = up_ch_rate;
+  assign up_ch_sys_clk_sel_10 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_10 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_10 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_9_s),
+    .up_rst_done_in (up_ch_rst_done_9_s),
+    .up_pll_locked (up_ch_pll_locked_10),
+    .up_rst_done (up_ch_rst_done_10),
+    .up_pll_locked_out (up_ch_pll_locked_10_s),
+    .up_rst_done_out (up_ch_rst_done_10_s));
+
+  assign up_ch_sel_10 = up_ch_sel;
+  assign up_ch_enb_10 = up_ch_enb;
+  assign up_ch_addr_10 = up_ch_addr;
+  assign up_ch_wr_10 = up_ch_wr;
+  assign up_ch_wdata_10 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(10)) i_mdrp_ch_10 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_9_s),
+    .up_ready_in (up_ch_ready_9_s),
+    .up_rdata (up_ch_rdata_10),
+    .up_ready (up_ch_ready_10),
+    .up_rdata_out (up_ch_rdata_10_s),
+    .up_ready_out (up_ch_ready_10_s));
+
+  assign up_es_sel_11 = up_es_sel;
+  assign up_es_enb_11 = up_es_enb;
+  assign up_es_addr_11 = up_es_addr;
+  assign up_es_wr_11 = up_es_wr;
+  assign up_es_wdata_11 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(11)) i_mdrp_es_11 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_10_s),
+    .up_ready_in (up_es_ready_10_s),
+    .up_rdata (up_es_rdata_11),
+    .up_ready (up_es_ready_11),
+    .up_rdata_out (up_es_rdata_11_s),
+    .up_ready_out (up_es_ready_11_s));
+
+  assign up_ch_pll_rst_11 = up_ch_pll_rst;
+  assign up_ch_rst_11 = up_ch_rst;
+  assign up_ch_user_ready_11 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_11 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_11 = up_ch_rate;
+  assign up_ch_sys_clk_sel_11 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_11 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_11 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_10_s),
+    .up_rst_done_in (up_ch_rst_done_10_s),
+    .up_pll_locked (up_ch_pll_locked_11),
+    .up_rst_done (up_ch_rst_done_11),
+    .up_pll_locked_out (up_ch_pll_locked_11_s),
+    .up_rst_done_out (up_ch_rst_done_11_s));
+
+  assign up_ch_sel_11 = up_ch_sel;
+  assign up_ch_enb_11 = up_ch_enb;
+  assign up_ch_addr_11 = up_ch_addr;
+  assign up_ch_wr_11 = up_ch_wr;
+  assign up_ch_wdata_11 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(11)) i_mdrp_ch_11 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_10_s),
+    .up_ready_in (up_ch_ready_10_s),
+    .up_rdata (up_ch_rdata_11),
+    .up_ready (up_ch_ready_11),
+    .up_rdata_out (up_ch_rdata_11_s),
+    .up_ready_out (up_ch_ready_11_s));
+
+  assign up_cm_sel_12 = up_cm_sel;
+  assign up_cm_enb_12 = up_cm_enb;
+  assign up_cm_addr_12 = up_cm_addr;
+  assign up_cm_wr_12 = up_cm_wr;
+  assign up_cm_wdata_12 = up_cm_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(12)) i_mdrp_cm_12 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_cm_sel),
+    .up_enb (up_cm_enb),
+    .up_rdata_in (up_cm_rdata_8_s),
+    .up_ready_in (up_cm_ready_8_s),
+    .up_rdata (up_cm_rdata_12),
+    .up_ready (up_cm_ready_12),
+    .up_rdata_out (up_cm_rdata_12_s),
+    .up_ready_out (up_cm_ready_12_s));
+
+  assign up_es_sel_12 = up_es_sel;
+  assign up_es_enb_12 = up_es_enb;
+  assign up_es_addr_12 = up_es_addr;
+  assign up_es_wr_12 = up_es_wr;
+  assign up_es_wdata_12 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(12)) i_mdrp_es_12 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_11_s),
+    .up_ready_in (up_es_ready_11_s),
+    .up_rdata (up_es_rdata_12),
+    .up_ready (up_es_ready_12),
+    .up_rdata_out (up_es_rdata_12_s),
+    .up_ready_out (up_es_ready_12_s));
+
+  assign up_ch_pll_rst_12 = up_ch_pll_rst;
+  assign up_ch_rst_12 = up_ch_rst;
+  assign up_ch_user_ready_12 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_12 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_12 = up_ch_rate;
+  assign up_ch_sys_clk_sel_12 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_12 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_12 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_11_s),
+    .up_rst_done_in (up_ch_rst_done_11_s),
+    .up_pll_locked (up_ch_pll_locked_12),
+    .up_rst_done (up_ch_rst_done_12),
+    .up_pll_locked_out (up_ch_pll_locked_12_s),
+    .up_rst_done_out (up_ch_rst_done_12_s));
+
+  assign up_ch_sel_12 = up_ch_sel;
+  assign up_ch_enb_12 = up_ch_enb;
+  assign up_ch_addr_12 = up_ch_addr;
+  assign up_ch_wr_12 = up_ch_wr;
+  assign up_ch_wdata_12 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(12)) i_mdrp_ch_12 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_11_s),
+    .up_ready_in (up_ch_ready_11_s),
+    .up_rdata (up_ch_rdata_12),
+    .up_ready (up_ch_ready_12),
+    .up_rdata_out (up_ch_rdata_12_s),
+    .up_ready_out (up_ch_ready_12_s));
+
+  assign up_es_sel_13 = up_es_sel;
+  assign up_es_enb_13 = up_es_enb;
+  assign up_es_addr_13 = up_es_addr;
+  assign up_es_wr_13 = up_es_wr;
+  assign up_es_wdata_13 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(13)) i_mdrp_es_13 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_12_s),
+    .up_ready_in (up_es_ready_12_s),
+    .up_rdata (up_es_rdata_13),
+    .up_ready (up_es_ready_13),
+    .up_rdata_out (up_es_rdata_13_s),
+    .up_ready_out (up_es_ready_13_s));
+
+  assign up_ch_pll_rst_13 = up_ch_pll_rst;
+  assign up_ch_rst_13 = up_ch_rst;
+  assign up_ch_user_ready_13 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_13 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_13 = up_ch_rate;
+  assign up_ch_sys_clk_sel_13 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_13 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_13 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_12_s),
+    .up_rst_done_in (up_ch_rst_done_12_s),
+    .up_pll_locked (up_ch_pll_locked_13),
+    .up_rst_done (up_ch_rst_done_13),
+    .up_pll_locked_out (up_ch_pll_locked_13_s),
+    .up_rst_done_out (up_ch_rst_done_13_s));
+
+  assign up_ch_sel_13 = up_ch_sel;
+  assign up_ch_enb_13 = up_ch_enb;
+  assign up_ch_addr_13 = up_ch_addr;
+  assign up_ch_wr_13 = up_ch_wr;
+  assign up_ch_wdata_13 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(13)) i_mdrp_ch_13 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_12_s),
+    .up_ready_in (up_ch_ready_12_s),
+    .up_rdata (up_ch_rdata_13),
+    .up_ready (up_ch_ready_13),
+    .up_rdata_out (up_ch_rdata_13_s),
+    .up_ready_out (up_ch_ready_13_s));
+
+  assign up_es_sel_14 = up_es_sel;
+  assign up_es_enb_14 = up_es_enb;
+  assign up_es_addr_14 = up_es_addr;
+  assign up_es_wr_14 = up_es_wr;
+  assign up_es_wdata_14 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(14)) i_mdrp_es_14 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_13_s),
+    .up_ready_in (up_es_ready_13_s),
+    .up_rdata (up_es_rdata_14),
+    .up_ready (up_es_ready_14),
+    .up_rdata_out (up_es_rdata_14_s),
+    .up_ready_out (up_es_ready_14_s));
+
+  assign up_ch_pll_rst_14 = up_ch_pll_rst;
+  assign up_ch_rst_14 = up_ch_rst;
+  assign up_ch_user_ready_14 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_14 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_14 = up_ch_rate;
+  assign up_ch_sys_clk_sel_14 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_14 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_14 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_13_s),
+    .up_rst_done_in (up_ch_rst_done_13_s),
+    .up_pll_locked (up_ch_pll_locked_14),
+    .up_rst_done (up_ch_rst_done_14),
+    .up_pll_locked_out (up_ch_pll_locked_14_s),
+    .up_rst_done_out (up_ch_rst_done_14_s));
+
+  assign up_ch_sel_14 = up_ch_sel;
+  assign up_ch_enb_14 = up_ch_enb;
+  assign up_ch_addr_14 = up_ch_addr;
+  assign up_ch_wr_14 = up_ch_wr;
+  assign up_ch_wdata_14 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(14)) i_mdrp_ch_14 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_13_s),
+    .up_ready_in (up_ch_ready_13_s),
+    .up_rdata (up_ch_rdata_14),
+    .up_ready (up_ch_ready_14),
+    .up_rdata_out (up_ch_rdata_14_s),
+    .up_ready_out (up_ch_ready_14_s));
+
+  assign up_es_sel_15 = up_es_sel;
+  assign up_es_enb_15 = up_es_enb;
+  assign up_es_addr_15 = up_es_addr;
+  assign up_es_wr_15 = up_es_wr;
+  assign up_es_wdata_15 = up_es_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(15)) i_mdrp_es_15 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_es_sel),
+    .up_enb (up_es_enb),
+    .up_rdata_in (up_es_rdata_14_s),
+    .up_ready_in (up_es_ready_14_s),
+    .up_rdata (up_es_rdata_15),
+    .up_ready (up_es_ready_15),
+    .up_rdata_out (up_es_rdata_15_s),
+    .up_ready_out (up_es_ready_15_s));
+
+  assign up_ch_pll_rst_15 = up_ch_pll_rst;
+  assign up_ch_rst_15 = up_ch_rst;
+  assign up_ch_user_ready_15 = up_ch_user_ready;
+  assign up_ch_lpm_dfe_n_15 = up_ch_lpm_dfe_n;
+  assign up_ch_rate_15 = up_ch_rate;
+  assign up_ch_sys_clk_sel_15 = up_ch_sys_clk_sel;
+  assign up_ch_out_clk_sel_15 = up_ch_out_clk_sel;
+
+  axi_adxcvr_mstatus i_mstatus_ch_15 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_pll_locked_in (up_ch_pll_locked_14_s),
+    .up_rst_done_in (up_ch_rst_done_14_s),
+    .up_pll_locked (up_ch_pll_locked_15),
+    .up_rst_done (up_ch_rst_done_15),
+    .up_pll_locked_out (up_ch_pll_locked_15_s),
+    .up_rst_done_out (up_ch_rst_done_15_s));
+
+  assign up_ch_sel_15 = up_ch_sel;
+  assign up_ch_enb_15 = up_ch_enb;
+  assign up_ch_addr_15 = up_ch_addr;
+  assign up_ch_wr_15 = up_ch_wr;
+  assign up_ch_wdata_15 = up_ch_wdata;
+
+  axi_adxcvr_mdrp #(.XCVR_ID(15)) i_mdrp_ch_15 (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_sel (up_ch_sel),
+    .up_enb (up_ch_enb),
+    .up_rdata_in (up_ch_rdata_14_s),
+    .up_ready_in (up_ch_ready_14_s),
+    .up_rdata (up_ch_rdata_15),
+    .up_ready (up_ch_ready_15),
+    .up_rdata_out (up_ch_rdata_15_s),
+    .up_ready_out (up_ch_ready_15_s));
+
+  axi_adxcvr_es #(
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .TX_OR_RX_N (TX_OR_RX_N))
+  i_es (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_enb (up_es_enb),
+    .up_es_addr (up_es_addr),
+    .up_es_wr (up_es_wr),
+    .up_es_wdata (up_es_wdata),
+    .up_es_rdata (up_es_rdata_15_s),
+    .up_es_ready (up_es_ready_15_s),
+    .up_ch_lpm_dfe_n (up_ch_lpm_dfe_n),
+    .up_es_req (up_es_req),
+    .up_es_ack (up_es_ack),
+    .up_es_pscale (up_es_pscale),
+    .up_es_vrange (up_es_vrange),
+    .up_es_vstep (up_es_vstep),
+    .up_es_vmax (up_es_vmax),
+    .up_es_vmin (up_es_vmin),
+    .up_es_hmax (up_es_hmax),
+    .up_es_hmin (up_es_hmin),
+    .up_es_hstep (up_es_hstep),
+    .up_es_saddr (up_es_saddr),
+    .up_es_status (up_es_status),
+    .up_axi_awvalid (m_axi_awvalid),
+    .up_axi_awaddr (m_axi_awaddr),
+    .up_axi_awprot (m_axi_awprot),
+    .up_axi_awready (m_axi_awready),
+    .up_axi_wvalid (m_axi_wvalid),
+    .up_axi_wdata (m_axi_wdata),
+    .up_axi_wstrb (m_axi_wstrb),
+    .up_axi_wready (m_axi_wready),
+    .up_axi_bvalid (m_axi_bvalid),
+    .up_axi_bresp (m_axi_bresp),
+    .up_axi_bready (m_axi_bready),
+    .up_axi_arvalid (m_axi_arvalid),
+    .up_axi_araddr (m_axi_araddr),
+    .up_axi_arprot (m_axi_arprot),
+    .up_axi_arready (m_axi_arready),
+    .up_axi_rvalid (m_axi_rvalid),
+    .up_axi_rdata (m_axi_rdata),
+    .up_axi_rresp (m_axi_rresp),
+    .up_axi_rready (m_axi_rready));
+
+  axi_adxcvr_up #(
+    .ID (ID),
+    .TX_OR_RX_N (TX_OR_RX_N),
+    .QPLL_ENABLE (QPLL_ENABLE))
+  i_up (
+    .up_cm_sel (up_cm_sel),
+    .up_cm_enb (up_cm_enb),
+    .up_cm_addr (up_cm_addr),
+    .up_cm_wr (up_cm_wr),
+    .up_cm_wdata (up_cm_wdata),
+    .up_cm_rdata (up_cm_rdata_12_s),
+    .up_cm_ready (up_cm_ready_12_s),
+    .up_ch_pll_rst (up_ch_pll_rst),
+    .up_ch_pll_locked (up_ch_pll_locked_15_s),
+    .up_ch_rst (up_ch_rst),
+    .up_ch_user_ready (up_ch_user_ready),
+    .up_ch_rst_done (up_ch_rst_done_15_s),
+    .up_ch_lpm_dfe_n (up_ch_lpm_dfe_n),
+    .up_ch_rate (up_ch_rate),
+    .up_ch_sys_clk_sel (up_ch_sys_clk_sel),
+    .up_ch_out_clk_sel (up_ch_out_clk_sel),
+    .up_ch_sel (up_ch_sel),
+    .up_ch_enb (up_ch_enb),
+    .up_ch_addr (up_ch_addr),
+    .up_ch_wr (up_ch_wr),
+    .up_ch_wdata (up_ch_wdata),
+    .up_ch_rdata (up_ch_rdata_15_s),
+    .up_ch_ready (up_ch_ready_15_s),
+    .up_es_sel (up_es_sel),
+    .up_es_req (up_es_req),
+    .up_es_ack (up_es_ack),
+    .up_es_pscale (up_es_pscale),
+    .up_es_vrange (up_es_vrange),
+    .up_es_vstep (up_es_vstep),
+    .up_es_vmax (up_es_vmax),
+    .up_es_vmin (up_es_vmin),
+    .up_es_hmax (up_es_hmax),
+    .up_es_hmin (up_es_hmin),
+    .up_es_hstep (up_es_hstep),
+    .up_es_saddr (up_es_saddr),
+    .up_es_status (up_es_status),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+  up_axi #(.ADDRESS_WIDTH (10)) i_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_adxcvr/axi_adxcvr_es.v b/library/axi_adxcvr/axi_adxcvr_es.v
new file mode 100644
index 000000000..eaff6065e
--- /dev/null
+++ b/library/axi_adxcvr/axi_adxcvr_es.v
@@ -0,0 +1,567 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_adxcvr_es (
+
+  // up interface
+
+  input           up_rstn,
+  input           up_clk,
+  output          up_es_enb,
+  output  [11:0]  up_es_addr,
+  output          up_es_wr,
+  output  [15:0]  up_es_wdata,
+  input   [15:0]  up_es_rdata,
+  input           up_es_ready,
+  input           up_ch_lpm_dfe_n,
+  input           up_es_req,
+  output          up_es_ack,
+  input   [ 4:0]  up_es_pscale,
+  input   [ 1:0]  up_es_vrange,
+  input   [ 7:0]  up_es_vstep,
+  input   [ 7:0]  up_es_vmax,
+  input   [ 7:0]  up_es_vmin,
+  input   [11:0]  up_es_hmax,
+  input   [11:0]  up_es_hmin,
+  input   [11:0]  up_es_hstep,
+  input   [31:0]  up_es_saddr,
+  output          up_es_status,
+
+  // axi interface
+
+  output          up_axi_awvalid,
+  output  [31:0]  up_axi_awaddr,
+  output  [ 2:0]  up_axi_awprot,
+  input           up_axi_awready,
+  output          up_axi_wvalid,
+  output  [31:0]  up_axi_wdata,
+  output  [ 3:0]  up_axi_wstrb,
+  input           up_axi_wready,
+  input           up_axi_bvalid,
+  input   [ 1:0]  up_axi_bresp,
+  output          up_axi_bready,
+  output          up_axi_arvalid,
+  output  [31:0]  up_axi_araddr,
+  output  [ 2:0]  up_axi_arprot,
+  input           up_axi_arready,
+  input           up_axi_rvalid,
+  input   [31:0]  up_axi_rdata,
+  input   [ 1:0]  up_axi_rresp,
+  output          up_axi_rready);
+
+  // parameters
+
+  parameter   integer GTH_OR_GTX_N = 0;
+  parameter   integer TX_OR_RX_N = 0;
+
+  // addresses
+
+  localparam  [11:0]  ES_DRP_CTRL_ADDR    = (GTH_OR_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d 
+  localparam  [11:0]  ES_DRP_HOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c 
+  localparam  [11:0]  ES_DRP_VOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b 
+  localparam  [11:0]  ES_DRP_STATUS_ADDR  = (GTH_OR_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153 
+  localparam  [11:0]  ES_DRP_SCNT_ADDR    = (GTH_OR_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152 
+  localparam  [11:0]  ES_DRP_ECNT_ADDR    = (GTH_OR_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151 
+
+  // fsm-states
+
+  localparam  [ 4:0]  ES_FSM_IDLE             = 6'h00;
+  localparam  [ 4:0]  ES_FSM_HOFFSET_READ     = 6'h01;
+  localparam  [ 4:0]  ES_FSM_HOFFSET_RRDY     = 6'h02;
+  localparam  [ 4:0]  ES_FSM_HOFFSET_WRITE    = 6'h03;
+  localparam  [ 4:0]  ES_FSM_HOFFSET_WRDY     = 6'h04;
+  localparam  [ 4:0]  ES_FSM_VOFFSET_READ     = 6'h05;
+  localparam  [ 4:0]  ES_FSM_VOFFSET_RRDY     = 6'h06;
+  localparam  [ 4:0]  ES_FSM_VOFFSET_WRITE    = 6'h07;
+  localparam  [ 4:0]  ES_FSM_VOFFSET_WRDY     = 6'h08;
+  localparam  [ 4:0]  ES_FSM_CTRL_READ        = 6'h09;
+  localparam  [ 4:0]  ES_FSM_CTRL_RRDY        = 6'h0a;
+  localparam  [ 4:0]  ES_FSM_START_WRITE      = 6'h0b;
+  localparam  [ 4:0]  ES_FSM_START_WRDY       = 6'h0c;
+  localparam  [ 4:0]  ES_FSM_STATUS_READ      = 6'h0d;
+  localparam  [ 4:0]  ES_FSM_STATUS_RRDY      = 6'h0e;
+  localparam  [ 4:0]  ES_FSM_STOP_WRITE       = 6'h0f;
+  localparam  [ 4:0]  ES_FSM_STOP_WRDY        = 6'h10;
+  localparam  [ 4:0]  ES_FSM_SCNT_READ        = 6'h11;
+  localparam  [ 4:0]  ES_FSM_SCNT_RRDY        = 6'h12;
+  localparam  [ 4:0]  ES_FSM_ECNT_READ        = 6'h13;
+  localparam  [ 4:0]  ES_FSM_ECNT_RRDY        = 6'h14;
+  localparam  [ 4:0]  ES_FSM_AXI_WRITE        = 6'h15;
+  localparam  [ 4:0]  ES_FSM_AXI_READY        = 6'h16;
+  localparam  [ 4:0]  ES_FSM_UPDATE           = 6'h17;
+
+  // internal registers
+
+  reg             up_awvalid = 'd0;
+  reg     [31:0]  up_awaddr = 'd0;
+  reg             up_wvalid = 'd0;
+  reg     [31:0]  up_wdata = 'd0;
+  reg             up_status = 'd0;
+  reg             up_ut = 'd0;
+  reg     [31:0]  up_daddr = 'd0;
+  reg     [11:0]  up_hindex = 'd0;
+  reg     [ 7:0]  up_vindex = 'd0;
+  reg     [15:0]  up_hdata = 'd0;
+  reg     [15:0]  up_vdata = 'd0;
+  reg     [15:0]  up_cdata = 'd0;
+  reg     [15:0]  up_sdata = 'd0;
+  reg     [15:0]  up_edata = 'd0;
+  reg             up_req_d = 'd0;
+  reg             up_ack = 'd0;
+  reg     [ 4:0]  up_fsm = 'd0;
+  reg             up_enb = 'd0;
+  reg     [11:0]  up_addr = 'd0;
+  reg             up_wr = 'd0;
+  reg     [15:0]  up_data = 'd0;
+
+  // internal signals
+
+  wire            up_heos_s;
+  wire            up_eos_s;
+  wire            up_ut_s;
+  wire    [ 7:0]  up_vindex_m_s;
+  wire    [ 7:0]  up_vindex_n_s;
+  wire    [ 7:0]  up_vindex_s;
+  wire            up_start_s;
+
+  // axi interface
+
+  generate
+  if (TX_OR_RX_N == 1) begin
+  assign up_axi_awvalid = 1'b0;
+  assign up_axi_awaddr = 32'd0;
+  assign up_axi_awprot = 3'd0;
+  assign up_axi_wvalid = 1'b0;
+  assign up_axi_wdata = 32'd0;
+  assign up_axi_wstrb = 4'hf;
+  assign up_axi_bready = 1'b1;
+  assign up_axi_arvalid = 1'b0;
+  assign up_axi_araddr = 32'd0;
+  assign up_axi_arprot = 3'd0;
+  assign up_axi_rready = 1'b1;
+  end else begin
+  assign up_axi_awvalid = up_awvalid;
+  assign up_axi_awaddr = up_awaddr;
+  assign up_axi_awprot = 3'd0;
+  assign up_axi_wvalid = up_wvalid;
+  assign up_axi_wdata = up_wdata;
+  assign up_axi_wstrb = 4'hf;
+  assign up_axi_bready = 1'b1;
+  assign up_axi_arvalid = 1'b0;
+  assign up_axi_araddr = 32'd0;
+  assign up_axi_arprot = 3'd0;
+  assign up_axi_rready = 1'b1;
+  end
+  endgenerate
+
+  // reconfig interface
+
+  generate
+  if (TX_OR_RX_N == 1) begin
+  assign up_es_ack = 1'b1;
+  assign up_es_enb = 1'b0;
+  assign up_es_addr = 12'd0;
+  assign up_es_wr = 1'd0;
+  assign up_es_wdata = 16'd0;
+  assign up_es_status = 1'd0;
+  end else begin
+  assign up_es_ack = up_ack;
+  assign up_es_enb = up_enb;
+  assign up_es_addr = up_addr;
+  assign up_es_wr = up_wr;
+  assign up_es_wdata = up_data;
+  assign up_es_status = up_status;
+  end
+  endgenerate
+
+  // axi write
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_awvalid <= 'b0;
+      up_awaddr <= 'd0;
+      up_wvalid <= 'b0;
+      up_wdata <= 'd0;
+      up_status <= 'd0;
+    end else begin
+      if ((up_awvalid == 1'b1) && (up_axi_awready == 1'b1)) begin
+        up_awvalid <= 1'b0;
+        up_awaddr <= 32'd0;
+      end else if (up_fsm == ES_FSM_AXI_WRITE) begin
+        up_awvalid <= 1'b1;
+        up_awaddr <= up_daddr;
+      end
+      if ((up_wvalid == 1'b1) && (up_axi_wready == 1'b1)) begin
+        up_wvalid <= 1'b0;
+        up_wdata <= 32'd0;
+      end else if (up_fsm == ES_FSM_AXI_WRITE) begin
+        up_wvalid <= 1'b1;
+        up_wdata <= {up_sdata, up_edata};
+      end
+      if (up_axi_bvalid == 1'b1) begin
+        up_status <= | up_axi_bresp;
+      end
+    end
+  end
+
+  // prescale, horizontal and vertical offsets
+
+  assign up_heos_s = (up_hindex == up_es_hmax) ? up_ut : 1'b0;
+  assign up_eos_s = (up_vindex == up_es_vmax) ? up_heos_s : 1'b0;
+
+  assign up_ut_s = up_ut & ~up_ch_lpm_dfe_n;
+  assign up_vindex_m_s = ~up_vindex + 1'b1;
+  assign up_vindex_n_s = {1'b1, up_vindex_m_s[6:0]};
+  assign up_vindex_s = (up_vindex[7] == 1'b1) ? up_vindex_n_s : up_vindex;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_ut <= 'd0;
+      up_daddr <= 'd0;
+      up_hindex <= 'd0;
+      up_vindex <= 'd0;
+    end else begin
+      if (up_fsm == ES_FSM_IDLE) begin
+        up_ut <= up_ch_lpm_dfe_n;
+        up_daddr <= up_es_saddr;
+        up_hindex <= up_es_hmin;
+        up_vindex <= up_es_vmin;
+      end else if (up_fsm == ES_FSM_UPDATE) begin
+        up_ut <= ~up_ut | up_ch_lpm_dfe_n;
+        up_daddr <= up_daddr + 3'd4;
+        if (up_heos_s == 1'b1) begin
+          up_hindex <= up_es_hmin;
+        end else if (up_ut == 1'b1) begin
+          up_hindex <= up_hindex + up_es_hstep;
+        end
+        if (up_heos_s == 1'b1) begin
+          up_vindex <= up_vindex + up_es_vstep;
+        end
+      end
+    end
+  end
+
+  // read-modify-write
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_hdata <= 'd0;
+      up_vdata <= 'd0;
+      up_cdata <= 'd0;
+      up_sdata <= 'd0;
+      up_edata <= 'd0;
+    end else begin
+      if ((up_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_ready == 1'b1)) begin
+        up_hdata <= up_es_rdata;
+      end
+      if ((up_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_ready == 1'b1)) begin
+        up_vdata <= up_es_rdata;
+      end
+      if ((up_fsm == ES_FSM_CTRL_RRDY) && (up_es_ready == 1'b1)) begin
+        up_cdata <= up_es_rdata;
+      end
+      if ((up_fsm == ES_FSM_SCNT_RRDY) && (up_es_ready == 1'b1)) begin
+        up_sdata <= up_es_rdata;
+      end
+      if ((up_fsm == ES_FSM_ECNT_RRDY) && (up_es_ready == 1'b1)) begin
+        up_edata <= up_es_rdata;
+      end
+    end
+  end
+
+  // request, start and ack
+
+  assign up_start_s = up_es_req & ~up_req_d;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_req_d <= 1'b0;
+      up_ack <= 1'b0;
+    end else begin
+      up_req_d <= up_es_req;
+      if (up_fsm == ES_FSM_UPDATE) begin 
+        up_ack <= up_eos_s | ~up_es_req;
+      end else begin
+        up_ack <= 1'b0;
+      end
+    end
+  end
+
+  // es-fsm
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_fsm <= ES_FSM_IDLE;
+    end else begin
+      case (up_fsm)
+        ES_FSM_IDLE: begin 
+          if (up_start_s == 1'b1) begin
+            up_fsm <= ES_FSM_HOFFSET_READ;
+          end else begin
+            up_fsm <= ES_FSM_IDLE;
+          end
+        end
+        ES_FSM_HOFFSET_READ: begin 
+          up_fsm <= ES_FSM_HOFFSET_RRDY;
+        end
+        ES_FSM_HOFFSET_RRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_HOFFSET_WRITE;
+          end else begin
+            up_fsm <= ES_FSM_HOFFSET_RRDY;
+          end
+        end
+        ES_FSM_HOFFSET_WRITE: begin 
+          up_fsm <= ES_FSM_HOFFSET_WRDY;
+        end
+        ES_FSM_HOFFSET_WRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_VOFFSET_READ;
+          end else begin
+            up_fsm <= ES_FSM_HOFFSET_WRDY;
+          end
+        end
+        ES_FSM_VOFFSET_READ: begin 
+          up_fsm <= ES_FSM_VOFFSET_RRDY;
+        end
+        ES_FSM_VOFFSET_RRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_VOFFSET_WRITE;
+          end else begin
+            up_fsm <= ES_FSM_VOFFSET_RRDY;
+          end
+        end
+        ES_FSM_VOFFSET_WRITE: begin 
+          up_fsm <= ES_FSM_VOFFSET_WRDY;
+        end
+        ES_FSM_VOFFSET_WRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_CTRL_READ;
+          end else begin
+            up_fsm <= ES_FSM_VOFFSET_WRDY;
+          end
+        end
+        ES_FSM_CTRL_READ: begin 
+          up_fsm <= ES_FSM_CTRL_RRDY;
+        end
+        ES_FSM_CTRL_RRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_START_WRITE;
+          end else begin
+            up_fsm <= ES_FSM_CTRL_RRDY;
+          end
+        end
+        ES_FSM_START_WRITE: begin 
+          up_fsm <= ES_FSM_START_WRDY;
+        end
+        ES_FSM_START_WRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_STATUS_READ;
+          end else begin
+            up_fsm <= ES_FSM_START_WRDY;
+          end
+        end
+        ES_FSM_STATUS_READ: begin 
+          up_fsm <= ES_FSM_STATUS_RRDY;
+        end
+        ES_FSM_STATUS_RRDY: begin 
+          if (up_es_ready == 1'b0) begin
+            up_fsm <= ES_FSM_STATUS_RRDY;
+          end else if (up_es_rdata[3:0] == 4'b0101) begin
+            up_fsm <= ES_FSM_STOP_WRITE;
+          end else begin
+            up_fsm <= ES_FSM_STATUS_READ;
+          end
+        end
+        ES_FSM_STOP_WRITE: begin 
+          up_fsm <= ES_FSM_STOP_WRDY;
+        end
+        ES_FSM_STOP_WRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_SCNT_READ;
+          end else begin
+            up_fsm <= ES_FSM_STOP_WRDY;
+          end
+        end
+        ES_FSM_SCNT_READ: begin 
+          up_fsm <= ES_FSM_SCNT_RRDY;
+        end
+        ES_FSM_SCNT_RRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_ECNT_READ;
+          end else begin
+            up_fsm <= ES_FSM_SCNT_RRDY;
+          end
+        end
+        ES_FSM_ECNT_READ: begin 
+          up_fsm <= ES_FSM_ECNT_RRDY;
+        end
+        ES_FSM_ECNT_RRDY: begin 
+          if (up_es_ready == 1'b1) begin
+            up_fsm <= ES_FSM_AXI_WRITE;
+          end else begin
+            up_fsm <= ES_FSM_ECNT_RRDY;
+          end
+        end
+        ES_FSM_AXI_WRITE: begin 
+          up_fsm <= ES_FSM_AXI_READY;
+        end
+        ES_FSM_AXI_READY: begin 
+          if (up_axi_bvalid == 1'b1) begin
+            up_fsm <= ES_FSM_UPDATE;
+          end else begin
+            up_fsm <= ES_FSM_AXI_READY;
+          end
+        end
+        ES_FSM_UPDATE: begin 
+          if ((up_eos_s == 1'b1) || (up_es_req == 1'b0)) begin
+            up_fsm <= ES_FSM_IDLE;
+          end else if (up_ut == 1'b1) begin
+            up_fsm <= ES_FSM_HOFFSET_READ;
+          end else begin
+            up_fsm <= ES_FSM_VOFFSET_READ;
+          end
+        end
+        default: begin
+          up_fsm <= ES_FSM_IDLE;
+        end
+      endcase
+    end
+  end
+
+  // channel access
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_enb <= 'd0;
+      up_addr <= 'd0;
+      up_wr <= 'd0;
+      up_data <= 'd0;
+    end else begin
+      case (up_fsm)
+        ES_FSM_HOFFSET_READ: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_HOFFSET_ADDR;
+          up_wr <= 1'b0;
+          up_data <= 16'h0000;
+        end
+        ES_FSM_HOFFSET_WRITE: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_HOFFSET_ADDR;
+          up_wr <= 1'b1;
+          if (GTH_OR_GTX_N == 1) begin
+          up_data <= {up_hindex, up_hdata[3:0]};
+          end else begin
+          up_data <= {up_hdata[15:12], up_hindex};
+          end
+        end
+        ES_FSM_VOFFSET_READ: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_VOFFSET_ADDR;
+          up_wr <= 1'b0;
+          up_data <= 16'h0000;
+        end
+        ES_FSM_VOFFSET_WRITE: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_VOFFSET_ADDR;
+          up_wr <= 1'b1;
+          if (GTH_OR_GTX_N == 1) begin
+          up_data <= {up_vdata[15:11], up_vindex_s[7], up_ut_s, up_vindex_s[6:0], up_es_vrange};
+          end else begin
+          up_data <= {up_es_pscale, up_vdata[10:9], up_ut_s, up_vindex_s};
+          end
+        end
+        ES_FSM_CTRL_READ: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_CTRL_ADDR;
+          up_wr <= 1'b0;
+          up_data <= 16'h0000;
+        end
+        ES_FSM_START_WRITE: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_CTRL_ADDR;
+          up_wr <= 1'b1;
+          if (GTH_OR_GTX_N == 1) begin
+          up_data <= {6'd1, 2'b11, up_cdata[7:5], up_es_pscale};
+          end else begin
+          up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd1};
+          end
+        end
+        ES_FSM_STATUS_READ: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_STATUS_ADDR;
+          up_wr <= 1'b0;
+          up_data <= 16'h0000;
+        end
+        ES_FSM_STOP_WRITE: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_CTRL_ADDR;
+          up_wr <= 1'b1;
+          if (GTH_OR_GTX_N == 1) begin
+          up_data <= {6'd0, 2'b11, up_cdata[7:5], up_es_pscale};
+          end else begin
+          up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd0};
+          end
+        end
+        ES_FSM_SCNT_READ: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_SCNT_ADDR;
+          up_wr <= 1'b0;
+          up_data <= 16'h0000;
+        end
+        ES_FSM_ECNT_READ: begin
+          up_enb <= 1'b1;
+          up_addr <= ES_DRP_ECNT_ADDR;
+          up_wr <= 1'b0;
+          up_data <= 16'h0000;
+        end
+        default: begin
+          up_enb <= 1'b0;
+          up_addr <= 9'h000;
+          up_wr <= 1'b0;
+          up_data <= 16'h0000;
+        end
+      endcase
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_adxcvr/axi_adxcvr_ip.tcl b/library/axi_adxcvr/axi_adxcvr_ip.tcl
new file mode 100644
index 000000000..fbfb42ef2
--- /dev/null
+++ b/library/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -0,0 +1,268 @@
+## AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY!
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_adxcvr
+adi_ip_files axi_adxcvr [list \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "axi_adxcvr_es.v" \
+  "axi_adxcvr_up.v" \
+  "axi_adxcvr_mdrp.v" \
+  "axi_adxcvr_mstatus.v" \
+  "axi_adxcvr.v" ]
+
+adi_ip_properties_lite axi_adxcvr
+
+ipx::remove_all_bus_interface [ipx::current_core]
+
+set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
+
+ipx::infer_bus_interface {\
+  s_axi_awvalid \
+  s_axi_awaddr \
+  s_axi_awprot \
+  s_axi_awready \
+  s_axi_wvalid \
+  s_axi_wdata \
+  s_axi_wstrb \
+  s_axi_wready \
+  s_axi_bvalid \
+  s_axi_bresp \
+  s_axi_bready \
+  s_axi_arvalid \
+  s_axi_araddr \
+  s_axi_arprot \
+  s_axi_arready \
+  s_axi_rvalid \
+  s_axi_rdata \
+  s_axi_rresp \
+  s_axi_rready} \
+xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface {\
+  m_axi_awvalid \
+  m_axi_awaddr \
+  m_axi_awprot \
+  m_axi_awready \
+  m_axi_wvalid \
+  m_axi_wdata \
+  m_axi_wstrb \
+  m_axi_wready \
+  m_axi_bvalid \
+  m_axi_bresp \
+  m_axi_bready \
+  m_axi_arvalid \
+  m_axi_araddr \
+  m_axi_arprot \
+  m_axi_arready \
+  m_axi_rvalid \
+  m_axi_rdata \
+  m_axi_rresp \
+  m_axi_rready} \
+xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
+  -of_objects [ipx::current_core]]
+set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
+  -of_objects [ipx::get_bus_interfaces axi_clk \
+  -of_objects [ipx::current_core]]]
+ipx::add_memory_map {s_axi} [ipx::current_core]
+set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
+ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
+set_property range {4096} [ipx::get_address_blocks axi_lite \
+  -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
+for {set n 0} {$n < 16} {incr n} {
+
+  if {($n%4) == 0} {
+  adi_if_infer_bus ADI:user:if_xcvr_cm master up_cm_${n} [list \
+    "sel                 up_cm_sel_${n}         "\
+    "enb                 up_cm_enb_${n}         "\
+    "addr                up_cm_addr_${n}        "\
+    "wr                  up_cm_wr_${n}          "\
+    "wdata               up_cm_wdata_${n}       "\
+    "rdata               up_cm_rdata_${n}       "\
+    "ready               up_cm_ready_${n}       "]
+  }
+
+  adi_if_infer_bus ADI:user:if_xcvr_cm master up_es_${n} [list \
+    "sel                 up_es_sel_${n}         "\
+    "enb                 up_es_enb_${n}         "\
+    "addr                up_es_addr_${n}        "\
+    "wr                  up_es_wr_${n}          "\
+    "wdata               up_es_wdata_${n}       "\
+    "rdata               up_es_rdata_${n}       "\
+    "ready               up_es_ready_${n}       "]
+
+  adi_if_infer_bus ADI:user:if_xcvr_ch master up_ch_${n} [list \
+    "pll_rst             up_ch_pll_rst_${n}     "\
+    "pll_locked          up_ch_pll_locked_${n}  "\
+    "rst                 up_ch_rst_${n}         "\
+    "user_ready          up_ch_user_ready_${n}  "\
+    "rst_done            up_ch_rst_done_${n}    "\
+    "lpm_dfe_n           up_ch_lpm_dfe_n_${n}   "\
+    "rate                up_ch_rate_${n}        "\
+    "sys_clk_sel         up_ch_sys_clk_sel_${n} "\
+    "out_clk_sel         up_ch_out_clk_sel_${n} "\
+    "sel                 up_ch_sel_${n}         "\
+    "enb                 up_ch_enb_${n}         "\
+    "addr                up_ch_addr_${n}        "\
+    "wr                  up_ch_wr_${n}          "\
+    "wdata               up_ch_wdata_${n}       "\
+    "rdata               up_ch_rdata_${n}       "\
+    "ready               up_ch_ready_${n}       "]
+
+}
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
+  [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
+  [ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
+  [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \
+  [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
+  [ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \
+  [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
+  [ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \
+  [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
+  [ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
+  [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
+  [ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
+  [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \
+  [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
+  [ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \
+  [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
+  [ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \
+  [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
+  [ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
+  [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \
+  [ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
+  [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \
+  [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \
+  [ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \
+  [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \
+  [ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \
+  [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \
+  [ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
+  [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \
+  [ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
+  [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \
+  [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \
+  [ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \
+  [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \
+  [ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency \
+  {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
+  (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \
+  [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \
+  [ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]]
+
+ipx::save_core [ipx::current_core]
+
diff --git a/library/axi_adxcvr/axi_adxcvr_mdrp.v b/library/axi_adxcvr/axi_adxcvr_mdrp.v
new file mode 100644
index 000000000..25cb7b0a1
--- /dev/null
+++ b/library/axi_adxcvr/axi_adxcvr_mdrp.v
@@ -0,0 +1,135 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module axi_adxcvr_mdrp (
+
+  input           up_rstn,
+  input           up_clk,
+
+  input   [ 7:0]  up_sel,
+  input           up_enb,
+  input   [15:0]  up_rdata_in,
+  input           up_ready_in,
+  input   [15:0]  up_rdata,
+  input           up_ready,
+  output  [15:0]  up_rdata_out,
+  output          up_ready_out);
+
+  // parameters
+
+  parameter   integer XCVR_ID = 0;
+
+  // internal registers
+
+  reg             up_ready_d = 'd0;
+  reg     [15:0]  up_rdata_int = 'd0;
+  reg             up_ready_int = 'd0;
+  reg     [15:0]  up_rdata_m_in = 'd0;
+  reg             up_ready_m_in = 'd0;
+  reg     [15:0]  up_rdata_m = 'd0;
+  reg             up_ready_m = 'd0;
+
+  // internal signals
+
+  wire            up_ready_s;
+  wire    [15:0]  up_rdata_m_s;
+  wire            up_ready_m_s;
+
+  // disable if not selected
+
+  assign up_rdata_out = up_rdata_int;
+  assign up_ready_out = up_ready_int;
+
+  assign up_ready_s = up_ready_m & up_ready_m_in;
+  assign up_rdata_m_s = up_rdata_m | up_rdata_m_in;
+  assign up_ready_m_s = up_ready_s & ~up_ready_d;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_ready_d <= 1'd0;
+      up_rdata_int <= 16'd0;
+      up_ready_int <= 1'b0;
+    end else begin
+      up_ready_d <= up_ready_s;
+      case (up_sel)
+        8'hff: begin
+          up_rdata_int <= up_rdata_m_s;
+          up_ready_int <= up_ready_m_s;
+        end
+        XCVR_ID: begin
+          up_rdata_int <= up_rdata;
+          up_ready_int <= up_ready;
+        end
+        default: begin
+          up_rdata_int <= up_rdata_in;
+          up_ready_int <= up_ready_int;
+        end
+      endcase
+    end
+  end
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_rdata_m_in <= 16'd0;
+      up_ready_m_in <= 1'b0;
+      up_rdata_m <= 16'd0;
+      up_ready_m <= 1'b0;
+    end else begin
+      if (up_ready_in == 1'b1) begin
+        up_rdata_m_in <= up_rdata_in;
+        up_ready_m_in <= 1'b1;
+      end else if (up_enb == 1'b1) begin
+        up_rdata_m_in <= 16'd0;
+        up_ready_m_in <= 1'b0;
+      end
+      if (up_ready == 1'b1) begin
+        up_rdata_m <= up_rdata;
+        up_ready_m <= 1'b1;
+      end else if (up_enb == 1'b1) begin
+        up_rdata_m <= 16'd0;
+        up_ready_m <= 1'b0;
+      end
+    end
+  end
+
+endmodule     
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_adxcvr/axi_adxcvr_mstatus.v b/library/axi_adxcvr/axi_adxcvr_mstatus.v
new file mode 100644
index 000000000..52079d0e8
--- /dev/null
+++ b/library/axi_adxcvr/axi_adxcvr_mstatus.v
@@ -0,0 +1,76 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module axi_adxcvr_mstatus (
+
+  input           up_rstn,
+  input           up_clk,
+
+  input           up_pll_locked_in,
+  input           up_rst_done_in,
+  input           up_pll_locked,
+  input           up_rst_done,
+  output          up_pll_locked_out,
+  output          up_rst_done_out);
+
+  // internal registers
+
+  reg             up_pll_locked_int = 'd0;
+  reg             up_rst_done_int = 'd0;
+
+  // daisy-chain the signals
+
+  assign up_pll_locked_out = up_pll_locked_int;
+  assign up_rst_done_out = up_rst_done_int;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_pll_locked_int <= 1'd0;
+      up_rst_done_int <= 1'd0;
+    end else begin
+      up_pll_locked_int <= up_pll_locked_in & up_pll_locked;
+      up_rst_done_int <= up_rst_done_in & up_rst_done;
+    end
+  end
+
+endmodule     
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_adxcvr/axi_adxcvr_up.v b/library/axi_adxcvr/axi_adxcvr_up.v
new file mode 100644
index 000000000..94551a00e
--- /dev/null
+++ b/library/axi_adxcvr/axi_adxcvr_up.v
@@ -0,0 +1,483 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_adxcvr_up (
+
+  // common
+
+  output  [ 7:0]  up_cm_sel,
+  output          up_cm_enb,
+  output  [11:0]  up_cm_addr,
+  output          up_cm_wr,
+  output  [15:0]  up_cm_wdata,
+  input   [15:0]  up_cm_rdata,
+  input           up_cm_ready,
+
+  // channel
+
+  output          up_ch_pll_rst,
+  input           up_ch_pll_locked,
+  output          up_ch_rst,
+  output          up_ch_user_ready,
+  input           up_ch_rst_done,
+  output          up_ch_lpm_dfe_n,
+  output  [ 2:0]  up_ch_rate,
+  output  [ 1:0]  up_ch_sys_clk_sel,
+  output  [ 2:0]  up_ch_out_clk_sel,
+  output  [ 7:0]  up_ch_sel,
+  output          up_ch_enb,
+  output  [11:0]  up_ch_addr,
+  output          up_ch_wr,
+  output  [15:0]  up_ch_wdata,
+  input   [15:0]  up_ch_rdata,
+  input           up_ch_ready,
+
+  // eye-scan
+
+  output  [ 7:0]  up_es_sel,
+  output          up_es_req,
+  input           up_es_ack,
+  output  [ 4:0]  up_es_pscale,
+  output  [ 1:0]  up_es_vrange,
+  output  [ 7:0]  up_es_vstep,
+  output  [ 7:0]  up_es_vmax,
+  output  [ 7:0]  up_es_vmin,
+  output  [11:0]  up_es_hmax,
+  output  [11:0]  up_es_hmin,
+  output  [11:0]  up_es_hstep,
+  output  [31:0]  up_es_saddr,
+  input           up_es_status,
+
+  // bus interface
+
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [ 9:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [ 9:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
+
+  // parameters
+
+  localparam  [31:0]  VERSION = 32'h00100161;
+  parameter   integer ID = 0;
+  parameter   integer TX_OR_RX_N = 0;
+  parameter   integer QPLL_ENABLE = 1;
+
+  // internal registers
+
+  reg             up_wreq_d = 'd0;
+  reg     [31:0]  up_scratch = 'd0;
+  reg             up_resetn = 'd0;
+  reg     [ 3:0]  up_pll_rst_cnt = 'd0;
+  reg     [ 3:0]  up_rst_cnt = 'd0;
+  reg     [ 6:0]  up_user_ready_cnt = 'd0;
+  reg             up_status = 'd0;
+  reg             up_lpm_dfe_n = 'd0;
+  reg     [ 2:0]  up_rate = 'd0;
+  reg     [ 1:0]  up_sys_clk_sel = 'd0;
+  reg     [ 2:0]  up_out_clk_sel = 'd0;
+  reg     [ 7:0]  up_icm_sel = 'd0;
+  reg             up_icm_enb = 'd0;
+  reg             up_icm_wr = 'd0;
+  reg     [11:0]  up_icm_addr = 'd0;
+  reg     [15:0]  up_icm_wdata = 'd0;
+  reg     [15:0]  up_icm_rdata = 'd0;
+  reg             up_icm_busy = 'd0;
+  reg     [ 7:0]  up_ich_sel = 'd0;
+  reg             up_ich_enb = 'd0;
+  reg             up_ich_wr = 'd0;
+  reg     [11:0]  up_ich_addr = 'd0;
+  reg     [15:0]  up_ich_wdata = 'd0;
+  reg     [15:0]  up_ich_rdata = 'd0;
+  reg             up_ich_busy = 'd0;
+  reg     [ 7:0]  up_ies_sel = 'd0;
+  reg             up_ies_req = 'd0;
+  reg     [ 4:0]  up_ies_prescale = 'd0;
+  reg     [ 1:0]  up_ies_voffset_range = 'd0;
+  reg     [ 7:0]  up_ies_voffset_step = 'd0;
+  reg     [ 7:0]  up_ies_voffset_max = 'd0;
+  reg     [ 7:0]  up_ies_voffset_min = 'd0;
+  reg     [11:0]  up_ies_hoffset_max = 'd0;
+  reg     [11:0]  up_ies_hoffset_min = 'd0;
+  reg     [11:0]  up_ies_hoffset_step = 'd0;
+  reg     [31:0]  up_ies_start_addr = 'd0;
+  reg             up_ies_status = 'd0;
+  reg             up_rreq_d = 'd0;
+  reg     [31:0]  up_rdata_d = 'd0;
+
+  // defaults
+
+  assign up_wack = up_wreq_d;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wreq_d <= 'd0;
+      up_scratch <= 'd0;
+    end else begin
+      up_wreq_d <= up_wreq;
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin
+        up_scratch <= up_wdata;
+      end
+    end
+  end
+
+  // reset-controller
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_resetn <= 'd0;
+    end else begin
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin
+        up_resetn <= up_wdata[0];
+      end
+    end
+  end
+
+  assign up_ch_pll_rst = up_pll_rst_cnt[3];
+  assign up_ch_rst = up_rst_cnt[3];
+  assign up_ch_user_ready = up_user_ready_cnt[6];
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_pll_rst_cnt <= 4'h8;
+      up_rst_cnt <= 4'h8;
+      up_user_ready_cnt <= 7'h00;
+      up_status <= 1'b0;
+    end else begin
+      if (up_resetn == 1'b0) begin
+        up_pll_rst_cnt <= 4'h8;
+      end else if (up_pll_rst_cnt[3] == 1'b1) begin
+        up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1;
+      end
+      if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) ||
+        (up_ch_pll_locked == 1'b0)) begin
+        up_rst_cnt <= 4'h8;
+      end else if (up_rst_cnt[3] == 1'b1) begin
+        up_rst_cnt <= up_rst_cnt + 1'b1;
+      end
+      if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin
+        up_user_ready_cnt <= 7'h00;
+      end else if (up_user_ready_cnt[6] == 1'b0) begin
+        up_user_ready_cnt <= up_user_ready_cnt + 1'b1;
+      end
+      if (up_resetn == 1'b0) begin
+        up_status <= 1'b0;
+      end else if (up_ch_rst_done == 1'b1) begin
+        up_status <= 1'b1;
+      end
+    end
+  end
+
+  // control signals
+
+  assign up_ch_lpm_dfe_n = up_lpm_dfe_n;
+  assign up_ch_rate = up_rate;
+  assign up_ch_sys_clk_sel = up_sys_clk_sel;
+  assign up_ch_out_clk_sel = up_out_clk_sel;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_lpm_dfe_n <= 'd0;
+      up_rate <= 'd0;
+      up_sys_clk_sel <= 'd0;
+      up_out_clk_sel <= 'd0;
+    end else begin
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin
+        up_lpm_dfe_n <= up_wdata[12];
+        up_rate <= up_wdata[10:8];
+        up_sys_clk_sel <= up_wdata[5:4];
+        up_out_clk_sel <= up_wdata[2:0];
+      end
+    end
+  end
+
+  // common access
+
+  assign up_cm_sel = up_icm_sel;
+  assign up_cm_enb = up_icm_enb;
+  assign up_cm_wr = up_icm_wr;
+  assign up_cm_addr = up_icm_addr;
+  assign up_cm_wdata = up_icm_wdata;
+
+  generate
+  if (QPLL_ENABLE == 0) begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_icm_sel <= 'd0;
+      up_icm_enb <= 'd0;
+      up_icm_wr <= 'd0;
+      up_icm_addr <= 'd0;
+      up_icm_wdata <= 'd0;
+      up_icm_rdata <= 'd0;
+      up_icm_busy <= 'd0;
+    end else begin
+      up_icm_sel <= 'd0;
+      up_icm_enb <= 'd0;
+      up_icm_wr <= 'd0;
+      up_icm_addr <= 'd0;
+      up_icm_wdata <= 'd0;
+      up_icm_rdata <= 'd0;
+      up_icm_busy <= 'd0;
+    end
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_icm_sel <= 'd0;
+      up_icm_enb <= 'd0;
+      up_icm_wr <= 'd0;
+      up_icm_addr <= 'd0;
+      up_icm_wdata <= 'd0;
+      up_icm_rdata <= 'd0;
+      up_icm_busy <= 'd0;
+    end else begin
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h010)) begin
+        up_icm_sel <= up_wdata[7:0];
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
+        up_icm_enb <= 1'b1;
+      end else begin
+        up_icm_enb <= 1'b0;
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
+        up_icm_wr <= up_wdata[28];
+        up_icm_addr <= up_wdata[27:16];
+        up_icm_wdata <= up_wdata[15:0];
+      end
+      if (up_cm_ready == 1'b1) begin
+        up_icm_rdata <= up_cm_rdata;
+        up_icm_busy <= 1'b0;
+      end else if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
+        up_icm_rdata <= 16'd0;
+        up_icm_busy <= 1'b1;
+      end
+    end
+  end
+  end
+  endgenerate
+
+  // channel access
+
+  assign up_ch_sel = up_ich_sel;
+  assign up_ch_enb = up_ich_enb;
+  assign up_ch_wr = up_ich_wr;
+  assign up_ch_addr = up_ich_addr;
+  assign up_ch_wdata = up_ich_wdata;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_ich_sel <= 'd0;
+      up_ich_enb <= 'd0;
+      up_ich_wr <= 'd0;
+      up_ich_addr <= 'd0;
+      up_ich_wdata <= 'd0;
+      up_ich_rdata <= 'd0;
+      up_ich_busy <= 'd0;
+    end else begin
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h018)) begin
+        up_ich_sel <= up_wdata[7:0];
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
+        up_ich_enb <= 1'b1;
+      end else begin
+        up_ich_enb <= 1'b0;
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
+        up_ich_wr <= up_wdata[28];
+        up_ich_addr <= up_wdata[27:16];
+        up_ich_wdata <= up_wdata[15:0];
+      end
+      if (up_ch_ready == 1'b1) begin
+        up_ich_rdata <= up_ch_rdata;
+        up_ich_busy <= 1'b0;
+      end else if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
+        up_ich_rdata <= 16'd0;
+        up_ich_busy <= 1'b1;
+      end
+    end
+  end
+
+  // eye-scan
+
+  assign up_es_sel = up_ies_sel;
+  assign up_es_req = up_ies_req;
+  assign up_es_pscale = up_ies_prescale;
+  assign up_es_vrange = up_ies_voffset_range;
+  assign up_es_vstep = up_ies_voffset_step;
+  assign up_es_vmax = up_ies_voffset_max;
+  assign up_es_vmin = up_ies_voffset_min;
+  assign up_es_hmax = up_ies_hoffset_max;
+  assign up_es_hmin = up_ies_hoffset_min;
+  assign up_es_hstep = up_ies_hoffset_step;
+  assign up_es_saddr = up_ies_start_addr;
+
+  generate
+  if (TX_OR_RX_N == 1) begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_ies_sel <= 'd0;
+      up_ies_req <= 'd0;
+      up_ies_prescale <= 'd0;
+      up_ies_voffset_range <= 'd0;
+      up_ies_voffset_step <= 'd0;
+      up_ies_voffset_max <= 'd0;
+      up_ies_voffset_min <= 'd0;
+      up_ies_hoffset_max <= 'd0;
+      up_ies_hoffset_min <= 'd0;
+      up_ies_hoffset_step <= 'd0;
+      up_ies_start_addr <= 'd0;
+      up_ies_status <= 'd0;
+    end else begin
+      up_ies_sel <= 'd0;
+      up_ies_req <= 'd0;
+      up_ies_prescale <= 'd0;
+      up_ies_voffset_range <= 'd0;
+      up_ies_voffset_step <= 'd0;
+      up_ies_voffset_max <= 'd0;
+      up_ies_voffset_min <= 'd0;
+      up_ies_hoffset_max <= 'd0;
+      up_ies_hoffset_min <= 'd0;
+      up_ies_hoffset_step <= 'd0;
+      up_ies_start_addr <= 'd0;
+      up_ies_status <= 'd0;
+    end
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_ies_sel <= 'd0;
+      up_ies_req <= 'd0;
+      up_ies_prescale <= 'd0;
+      up_ies_voffset_range <= 'd0;
+      up_ies_voffset_step <= 'd0;
+      up_ies_voffset_max <= 'd0;
+      up_ies_voffset_min <= 'd0;
+      up_ies_hoffset_max <= 'd0;
+      up_ies_hoffset_min <= 'd0;
+      up_ies_hoffset_step <= 'd0;
+      up_ies_start_addr <= 'd0;
+      up_ies_status <= 'd0;
+    end else begin
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h020)) begin
+        up_ies_sel <= up_wdata[7:0];
+      end
+      if (up_es_ack == 1'b1) begin
+        up_ies_req <= 1'b0;
+      end else if ((up_wreq == 1'b1) && (up_waddr == 10'h028)) begin
+        up_ies_req <= up_wdata[0];
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h029)) begin
+        up_ies_prescale <= up_wdata[4:0];
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h02a)) begin
+        up_ies_voffset_range <= up_wdata[25:24];
+        up_ies_voffset_step <= up_wdata[23:16];
+        up_ies_voffset_max <= up_wdata[15:8];
+        up_ies_voffset_min <= up_wdata[7:0];
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h02b)) begin
+        up_ies_hoffset_max <= up_wdata[27:16];
+        up_ies_hoffset_min <= up_wdata[11:0];
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h02c)) begin
+        up_ies_hoffset_step <= up_wdata[11:0];
+      end
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h02d)) begin
+        up_ies_start_addr <= up_wdata;
+      end
+      if (up_es_status == 1'b1) begin
+        up_ies_status <= 1'b1;
+      end else if ((up_wreq == 1'b1) && (up_waddr == 10'h02e)) begin
+        up_ies_status <= up_ies_status & ~up_wdata[0];
+      end
+    end
+  end
+  end
+  endgenerate
+
+  // read interface
+
+  assign up_rack = up_rreq_d;
+  assign up_rdata = up_rdata_d;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rreq_d <= 'd0;
+      up_rdata_d <= 'd0;
+    end else begin
+      up_rreq_d <= up_rreq;
+      if (up_rreq == 1'b1) begin
+        case (up_raddr)
+          10'h000: up_rdata_d <= VERSION;
+          10'h001: up_rdata_d <= ID;
+          10'h002: up_rdata_d <= up_scratch;
+          10'h004: up_rdata_d <= {31'd0, up_resetn};
+          10'h005: up_rdata_d <= {31'd0, up_status};
+          10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel};
+          10'h010: up_rdata_d <= {24'd0, up_icm_sel};
+          10'h011: up_rdata_d <= {3'd0, up_icm_wr, up_icm_addr, up_icm_wdata};
+          10'h012: up_rdata_d <= {15'd0, up_icm_busy, up_icm_rdata};
+          10'h018: up_rdata_d <= {24'd0, up_ich_sel};
+          10'h019: up_rdata_d <= {3'd0, up_ich_wr, up_ich_addr, up_ich_wdata};
+          10'h01a: up_rdata_d <= {15'd0, up_ich_busy, up_ich_rdata};
+          10'h020: up_rdata_d <= {24'd0, up_ies_sel};
+          10'h028: up_rdata_d <= {31'd0, up_ies_req};
+          10'h029: up_rdata_d <= {27'd0, up_ies_prescale};
+          10'h02a: up_rdata_d <= {6'd0, up_ies_voffset_range, up_ies_voffset_step, up_ies_voffset_max, up_ies_voffset_min};
+          10'h02b: up_rdata_d <= {4'd0, up_ies_hoffset_max, 4'd0, up_ies_hoffset_min};
+          10'h02c: up_rdata_d <= {20'd0, up_ies_hoffset_step};
+          10'h02d: up_rdata_d <= up_ies_start_addr;
+          10'h02e: up_rdata_d <= {31'd0, up_es_status};
+          default: up_rdata_d <= 32'd0;
+        endcase
+      end else begin
+        up_rdata_d <= 32'd0;
+      end
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 7a03d44e4e45a525d9eafe0d8b8375c034efc23c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 8 Jul 2016 13:56:46 -0400
Subject: [PATCH 307/972] adxcvr- clock buffers are removed

---
 library/util_adxcvr/util_adxcvr.v     | 34 ---------------------------
 library/util_adxcvr/util_adxcvr_xch.v |  2 --
 2 files changed, 36 deletions(-)

diff --git a/library/util_adxcvr/util_adxcvr.v b/library/util_adxcvr/util_adxcvr.v
index 5be095b9b..9f14027eb 100644
--- a/library/util_adxcvr/util_adxcvr.v
+++ b/library/util_adxcvr/util_adxcvr.v
@@ -1030,10 +1030,8 @@ module util_adxcvr (
   parameter   integer QPLL_FBDIV_RATIO = 1;
   parameter   integer RX_OUT_DIV = 1;
   parameter   integer RX_CLK25_DIV = 10;
-  parameter   integer RX_CLKBUF_ENABLE = 0;
   parameter   integer TX_OUT_DIV = 1;
   parameter   integer TX_CLK25_DIV = 10;
-  parameter   integer TX_CLKBUF_ENABLE = 0;
   parameter   [31:0]  PMA_RSV = 32'h00018480;
   parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff20400020;
   parameter   [26:0]  QPLL_CFG = 27'h06801C1;
@@ -1112,10 +1110,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_0 (
@@ -1211,10 +1207,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_1 (
@@ -1310,10 +1304,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_2 (
@@ -1409,10 +1401,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_3 (
@@ -1540,10 +1530,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_4 (
@@ -1639,10 +1627,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_5 (
@@ -1738,10 +1724,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_6 (
@@ -1837,10 +1821,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_7 (
@@ -1968,10 +1950,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_8 (
@@ -2067,10 +2047,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_9 (
@@ -2166,10 +2144,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_10 (
@@ -2265,10 +2241,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_11 (
@@ -2396,10 +2370,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_12 (
@@ -2495,10 +2467,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_13 (
@@ -2594,10 +2564,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_14 (
@@ -2693,10 +2661,8 @@ module util_adxcvr (
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
     .PMA_RSV (PMA_RSV),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_15 (
diff --git a/library/util_adxcvr/util_adxcvr_xch.v b/library/util_adxcvr/util_adxcvr_xch.v
index 0b19f9d6a..a4b303aa9 100644
--- a/library/util_adxcvr/util_adxcvr_xch.v
+++ b/library/util_adxcvr/util_adxcvr_xch.v
@@ -121,10 +121,8 @@ module util_adxcvr_xch (
   parameter   integer CPLL_FBDIV = 2;
   parameter   integer RX_OUT_DIV = 1;
   parameter   integer RX_CLK25_DIV = 10;
-  parameter   integer RX_CLKBUF_ENABLE = 0;
   parameter   integer TX_OUT_DIV = 1;
   parameter   integer TX_CLK25_DIV = 10;
-  parameter   integer TX_CLKBUF_ENABLE = 0;
   parameter   [31:0]  PMA_RSV = 32'h00018480;
   parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff20400020;
 

From 832efdc99c889b0af40354e868a50605b89cbffc Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 8 Jul 2016 13:58:56 -0400
Subject: [PATCH 308/972] hdlmake updates

---
 library/Makefile            |  2 ++
 library/axi_adxcvr/Makefile | 57 +++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100644 library/axi_adxcvr/Makefile

diff --git a/library/Makefile b/library/Makefile
index 80ad4558c..560659162 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -31,6 +31,7 @@ clean:
 	make -C axi_ad9684 clean
 	make -C axi_ad9739a clean
 	make -C axi_adcfifo clean
+	make -C axi_adxcvr clean
 	make -C axi_clkgen clean
 	make -C axi_dacfifo clean
 	make -C axi_dmac clean
@@ -103,6 +104,7 @@ lib:
 	-make -C axi_ad9684
 	-make -C axi_ad9739a
 	-make -C axi_adcfifo
+	-make -C axi_adxcvr
 	-make -C axi_clkgen
 	-make -C axi_dacfifo
 	-make -C axi_dmac
diff --git a/library/axi_adxcvr/Makefile b/library/axi_adxcvr/Makefile
new file mode 100644
index 000000000..3d4ab3ed4
--- /dev/null
+++ b/library/axi_adxcvr/Makefile
@@ -0,0 +1,57 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := axi_adxcvr_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../common/up_axi.v
+M_DEPS += axi_adxcvr_es.v
+M_DEPS += axi_adxcvr_up.v
+M_DEPS += axi_adxcvr_mdrp.v
+M_DEPS += axi_adxcvr_mstatus.v
+M_DEPS += axi_adxcvr.v
+M_DEPS += ../interfaces/if_xcvr_cm.xml
+M_DEPS += ../interfaces/if_xcvr_cm_rtl.xml
+M_DEPS += ../interfaces/if_xcvr_ch.xml
+M_DEPS += ../interfaces/if_xcvr_ch_rtl.xml
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all dep clean clean-all
+all: dep axi_adxcvr.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_adxcvr.xpr: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_adxcvr_ip.tcl  >> axi_adxcvr_ip.log 2>&1
+
+dep:
+	make -C ../interfaces
+####################################################################################
+####################################################################################

From 4f0d7bd6eb9d774fb717de72f94dc6844b5faa3b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 11 Jul 2016 09:59:31 -0400
Subject: [PATCH 309/972] util_wfifo: read after write is complete

---
 library/util_wfifo/util_wfifo.v          | 32 ++++++++++++++++--------
 library/util_wfifo/util_wfifo_constr.sdc |  1 +
 library/util_wfifo/util_wfifo_constr.xdc |  1 +
 3 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v
index 7a446ed10..ffcdefee6 100644
--- a/library/util_wfifo/util_wfifo.v
+++ b/library/util_wfifo/util_wfifo.v
@@ -180,15 +180,18 @@ module util_wfifo (
   reg                                 din_wr = 'd0;
   reg     [(ADDRESS_WIDTH-1):0]       din_waddr = 'd0;
   reg                                 din_req_t = 'd0;
+  reg     [(ADDRESS_WIDTH-4):0]       din_rinit = 'd0;
   reg                                 din_ovf_m1 = 'd0;
   reg                                 din_ovf = 'd0;
   reg                                 dout_req_t_m1 = 'd0;
   reg                                 dout_req_t_m2 = 'd0;
   reg                                 dout_req_t_m3 = 'd0;
+  reg                                 dout_req_t = 'd0;
+  reg     [(ADDRESS_WIDTH-4):0]       dout_rinit = 'd0;
   reg                                 dout_ovf_d = 'd0;
   reg     [ 3:0]                      dout_req_cnt = 'd0;
   reg     [(ADDRESS_WIDTH-1):0]       dout_raddr = 'd0;
-  reg                                 dout_rd = 'd0;
+  reg                                 dout_rd_d = 'd0;
   reg                                 dout_valid = 'd0;
   reg     [ 7:0]                      dout_enable_m1 = 'd0;
   reg     [ 7:0]                      dout_enable = 'd0;
@@ -216,8 +219,8 @@ module util_wfifo (
   assign din_data_s   = { din_data_7,   din_data_6,   din_data_5,   din_data_4,
                           din_data_3,   din_data_2,   din_data_1,   din_data_0};
 
-  // simple data transfer-- no ovf/unf handling- read-bw > write-bw
-  // dout_width >= din_width only
+  // simple data transfer-- no ovf/unf handling- read-bw > write-bw (equal will NOT work)
+  // dout_width >= din_width only-
 
   generate
   for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in
@@ -247,6 +250,7 @@ module util_wfifo (
       din_wr <= 1'd0;
       din_waddr <= 'd0;
       din_req_t <= 1'd0;
+      din_rinit <= 'd0;
       din_ovf_m1 <= 'd0;
       din_ovf <= 'd0;
     end else begin
@@ -263,8 +267,9 @@ module util_wfifo (
       if (din_wr == 1'b1) begin
         din_waddr <= din_waddr + 1'b1;
       end
-      if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd0)) begin
+      if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd7)) begin
         din_req_t <= ~din_req_t;
+        din_rinit <= din_waddr[(ADDRESS_WIDTH-1):3];
       end
       din_ovf_m1 <= dout_ovf_d;
       din_ovf <= din_ovf_m1;
@@ -280,11 +285,17 @@ module util_wfifo (
       dout_req_t_m1 <= 'd0;
       dout_req_t_m2 <= 'd0;
       dout_req_t_m3 <= 'd0;
+      dout_req_t <= 'd0;
+      dout_rinit <= 'd0;
       dout_ovf_d <= 'd0;
     end else begin
       dout_req_t_m1 <= din_req_t;
       dout_req_t_m2 <= dout_req_t_m1;
       dout_req_t_m3 <= dout_req_t_m2;
+      dout_req_t <= dout_req_t_s;
+      if (dout_req_t_s == 1'b1) begin
+        dout_rinit <= din_rinit;
+      end
       dout_ovf_d <= dout_ovf;
     end
   end
@@ -292,20 +303,19 @@ module util_wfifo (
   always @(posedge dout_clk or negedge dout_rstn) begin
     if (dout_rstn == 1'b0) begin
       dout_req_cnt <= 'd0;
-      dout_raddr <= 'd0;
-      dout_rd <= 'd0;
+      dout_raddr <= 'd8;
+      dout_rd_d <= 'd0;
       dout_valid <= 'd0;
     end else begin
-      if (dout_req_t_s == 1'b1) begin
+      if (dout_req_t == 1'b1) begin
         dout_req_cnt <= 4'h8;
+        dout_raddr <= {dout_rinit, 3'd0};
       end else if (dout_req_cnt[3] == 1'b1) begin
         dout_req_cnt <= dout_req_cnt + 1'b1;
-      end
-      if (dout_req_cnt[3] == 1'b1) begin
         dout_raddr <= dout_raddr + 1'b1;
       end
-      dout_rd <= dout_req_cnt[3];
-      dout_valid <= dout_rd;
+      dout_rd_d <= dout_req_cnt[3];
+      dout_valid <= dout_rd_d;
     end
   end
 
diff --git a/library/util_wfifo/util_wfifo_constr.sdc b/library/util_wfifo/util_wfifo_constr.sdc
index 8d24422e1..b3226e083 100644
--- a/library/util_wfifo/util_wfifo_constr.sdc
+++ b/library/util_wfifo/util_wfifo_constr.sdc
@@ -1,5 +1,6 @@
 
 set_false_path -from [get_registers *din_enable*] -to [get_registers *dout_enable_m1*]
 set_false_path -from [get_registers *din_req_t*]  -to [get_registers *dout_req_t_m1*]
+set_false_path -from [get_registers *din_rinit*]  -to [get_registers *dout_rinit*]
 set_false_path -from [get_registers *dout_ovf_d*] -to [get_registers *din_ovf_m1*]
 
diff --git a/library/util_wfifo/util_wfifo_constr.xdc b/library/util_wfifo/util_wfifo_constr.xdc
index e554dcff1..dc52b3271 100644
--- a/library/util_wfifo/util_wfifo_constr.xdc
+++ b/library/util_wfifo/util_wfifo_constr.xdc
@@ -5,5 +5,6 @@ set_property shreg_extract no [get_cells -hier -filter {name =~ *din_ovf_m*}]
 
 set_false_path -from [get_cells -hier -filter {name =~ *din_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_enable_m1* && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {name =~ *din_req_t*  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_req_t_m1*  && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *din_rinit*  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_rinit*     && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {name =~ *dout_ovf*   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_ovf_m1*     && IS_SEQUENTIAL}]
 

From e9fe752b7acd1fa485abb5a80f5fd5c31c2ef324 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Mon, 11 Jul 2016 18:34:21 +0300
Subject: [PATCH 310/972] fmcomms2_qsys.tcl: Add fmcomms2 block design script
 for Altera

---
 projects/fmcomms2/common/fmcomms2_bd.qsys  | 613 ---------------------
 projects/fmcomms2/common/fmcomms2_qsys.tcl | 135 +++++
 2 files changed, 135 insertions(+), 613 deletions(-)
 delete mode 100755 projects/fmcomms2/common/fmcomms2_bd.qsys
 create mode 100644 projects/fmcomms2/common/fmcomms2_qsys.tcl

diff --git a/projects/fmcomms2/common/fmcomms2_bd.qsys b/projects/fmcomms2/common/fmcomms2_bd.qsys
deleted file mode 100755
index d7daaf622..000000000
--- a/projects/fmcomms2/common/fmcomms2_bd.qsys
+++ /dev/null
@@ -1,613 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element adc_pack
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element axi_ad9361
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9361.s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element axi_dmac_adc
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dmac_adc.s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element axi_dmac_dac
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dmac_dac.s_axi
-   {
-      datum baseAddress
-      {
-         value = "16384";
-         type = "String";
-      }
-   }
-   element dac_upack
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40E2SGE2" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="axi_ad9361_delay_clk"
-   internal="axi_ad9361.if_delay_clk"
-   type="clock"
-   dir="end" />
- <interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
- <interface
-   name="axi_ad9361_device_if"
-   internal="axi_ad9361.device_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9361_s_axi"
-   internal="axi_ad9361.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9361_up_enable"
-   internal="axi_ad9361.if_up_enable"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9361_up_txnrx"
-   internal="axi_ad9361.if_up_txnrx"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_dmac_adc_fifo_wr_clock"
-   internal="axi_dmac_adc.fifo_wr_clock" />
- <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
- <interface
-   name="axi_dmac_adc_intr"
-   internal="axi_dmac_adc.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_adc_m_dest_axi"
-   internal="axi_dmac_adc.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_adc_s_axi"
-   internal="axi_dmac_adc.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_dmac_dac_fifo_rd_clock"
-   internal="axi_dmac_dac.fifo_rd_clock" />
- <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
- <interface
-   name="axi_dmac_dac_intr"
-   internal="axi_dmac_dac.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_dac_m_src_axi"
-   internal="axi_dmac_dac.m_src_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_dac_s_axi"
-   internal="axi_dmac_dac.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
-  <parameter name="ADC_DATAPATH_DISABLE" value="0" />
-  <parameter name="CMOS_OR_LVDS_N" value="0" />
-  <parameter name="DAC_DATAPATH_DISABLE" value="0" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="1" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="2" />
-  <parameter name="DMA_TYPE_SRC" value="0" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
- </module>
- <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="adc_pack.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="axi_ad9361.if_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="dac_upack.if_dac_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="axi_dmac_dac.if_fifo_rd_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="axi_dmac_adc.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_adc.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_dac.m_src_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9361.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_adc.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_dac.s_axi_clock" />
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.fifo_ch_0"
-   end="axi_ad9361.fifo_ch_0_out">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_0_in"
-   end="adc_pack.fifo_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_1_in"
-   end="adc_pack.fifo_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_1_out"
-   end="dac_upack.fifo_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_2_in"
-   end="adc_pack.fifo_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_2_out"
-   end="dac_upack.fifo_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_3_in"
-   end="adc_pack.fifo_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.fifo_ch_3_out"
-   end="dac_upack.fifo_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_data"
-   end="axi_dmac_adc.if_fifo_wr_din">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_sync"
-   end="axi_dmac_adc.if_fifo_wr_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_valid"
-   end="axi_dmac_adc.if_fifo_wr_en">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.if_dac_data"
-   end="axi_dmac_dac.if_fifo_rd_dout">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.if_dma_xfer_in"
-   end="axi_dmac_dac.if_fifo_rd_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_dac.if_fifo_rd_en"
-   end="dac_upack.if_dac_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_dac.if_fifo_rd_underflow"
-   end="axi_ad9361.if_dac_dunf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_adc.if_fifo_wr_overflow"
-   end="axi_ad9361.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_ad9361.if_rst"
-   end="adc_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="adc_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_adc.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_dac.m_src_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9361.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_adc.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_dac.s_axi_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
- <interconnectRequirement
-   for="mm_interconnect_0|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_2|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
-</system>
diff --git a/projects/fmcomms2/common/fmcomms2_qsys.tcl b/projects/fmcomms2/common/fmcomms2_qsys.tcl
new file mode 100644
index 000000000..2196c97b0
--- /dev/null
+++ b/projects/fmcomms2/common/fmcomms2_qsys.tcl
@@ -0,0 +1,135 @@
+
+# fmcomms2
+
+# ad9361 core
+
+add_instance axi_ad9361 axi_ad9361 1.0
+set_instance_parameter_value axi_ad9361 {ID} {0}
+
+add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
+add_connection sys_clk.clk axi_ad9361.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9361.s_axi
+add_connection  axi_ad9361.if_l_clk axi_ad9361.if_clk
+
+# ad9361-unpack (dac)
+
+add_instance util_ad9361_dac_upack util_upack 1.0
+set_instance_parameter_value util_ad9361_dac_upack {CHANNEL_DATA_WIDTH} {16}
+set_instance_parameter_value util_ad9361_dac_upack {NUM_OF_CHANNELS} {4}
+
+add_connection  axi_ad9361.if_l_clk util_ad9361_dac_upack.if_dac_clk
+
+# ad9361-dma (dac)
+
+add_instance axi_ad9361_dac_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9361_dac_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_ad9361_dac_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9361_dac_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_ad9361_dac_dma {DMA_TYPE_SRC} {0}
+set_instance_parameter_value axi_ad9361_dac_dma {CYCLIC} {1}
+set_instance_parameter_value axi_ad9361_dac_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_ad9361_dac_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9361_dac_dma {AXI_SLICE_DEST} {1}
+
+add_connection sys_clk.clk_reset axi_ad9361_dac_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9361_dac_dma.s_axi_clock
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9361_dac_dma.m_src_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9361_dac_dma.m_src_axi_clock
+add_connection axi_ad9361_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.irq axi_ad9361_dac_dma.interrupt_sender
+
+# dac path connections
+
+add_connection  sys_cpu.data_master axi_ad9361_dac_dma.s_axi
+add_connection  util_ad9361_dac_upack.if_dac_valid axi_ad9361_dac_dma.if_fifo_rd_en
+add_connection  util_ad9361_dac_upack.if_dac_data axi_ad9361_dac_dma.if_fifo_rd_dout
+add_connection  axi_ad9361_dac_dma.if_fifo_rd_underflow axi_ad9361.if_dac_dunf
+add_connection  util_ad9361_dac_upack.dac_ch_0 axi_ad9361.dac_ch_0
+add_connection  util_ad9361_dac_upack.dac_ch_1 axi_ad9361.dac_ch_1
+add_connection  util_ad9361_dac_upack.dac_ch_2 axi_ad9361.dac_ch_2
+add_connection  util_ad9361_dac_upack.dac_ch_3 axi_ad9361.dac_ch_3
+add_connection  axi_ad9361.if_l_clk axi_ad9361_dac_dma.if_fifo_rd_clk
+
+# ad9361-adc-fifo
+
+add_instance util_ad9361_adc_fifo util_wfifo 1.0
+set_instance_parameter_value util_ad9361_adc_fifo {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value util_ad9361_adc_fifo {DIN_ADDRESS_WIDTH} {4}
+set_instance_parameter_value util_ad9361_adc_fifo {DIN_DATA_WIDTH} {16}
+set_instance_parameter_value util_ad9361_adc_fifo {DOUT_DATA_WIDTH} {16}
+
+add_connection  axi_ad9361.if_l_clk util_ad9361_adc_fifo.if_din_clk
+add_connection  axi_ad9361.if_rst util_ad9361_adc_fifo.if_din_rst
+add_connection  sys_clk.clk_reset util_ad9361_adc_fifo.if_dout_rstn
+add_connection  sys_clk.clk util_ad9361_adc_fifo.if_dout_clk
+
+# ad9361-pack (adc)
+
+add_instance util_ad9361_adc_cpack util_cpack 1.0
+set_instance_parameter_value util_ad9361_adc_cpack {CHANNEL_DATA_WIDTH} {16}
+set_instance_parameter_value util_ad9361_adc_cpack {NUM_OF_CHANNELS} {4}
+
+add_connection  sys_clk.clk util_ad9361_adc_cpack.if_adc_clk
+add_connection  sys_clk.clk_reset util_ad9361_adc_cpack.if_adc_rst
+
+# ad9361-dma (adc)
+
+add_instance axi_ad9361_adc_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9361_adc_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_ad9361_adc_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9361_adc_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9361_adc_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_ad9361_adc_dma {CYCLIC} {0}
+set_instance_parameter_value axi_ad9361_adc_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9361_adc_dma {DMA_TYPE_SRC} {2}
+
+add_connection sys_clk.clk_reset axi_ad9361_adc_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9361_adc_dma.s_axi_clock
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9361_adc_dma.m_dest_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9361_adc_dma.m_dest_axi_clock
+add_connection sys_clk.clk axi_ad9361_adc_dma.if_fifo_wr_clk
+add_connection sys_cpu.irq axi_ad9361_adc_dma.interrupt_sender
+add_connection axi_ad9361_adc_dma.if_fifo_wr_overflow util_ad9361_adc_fifo.if_dout_ovf
+add_connection axi_ad9361_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+
+# adc path connections
+
+add_connection  axi_ad9361.adc_ch_0 util_ad9361_adc_fifo.din_0
+add_connection  axi_ad9361.adc_ch_1 util_ad9361_adc_fifo.din_1
+add_connection  axi_ad9361.adc_ch_2 util_ad9361_adc_fifo.din_2
+add_connection  axi_ad9361.adc_ch_3 util_ad9361_adc_fifo.din_3
+add_connection  util_ad9361_adc_fifo.if_din_ovf axi_ad9361.if_adc_dovf
+add_connection  util_ad9361_adc_fifo.dout_0 util_ad9361_adc_cpack.adc_ch_0
+add_connection  util_ad9361_adc_fifo.dout_1 util_ad9361_adc_cpack.adc_ch_1
+add_connection  util_ad9361_adc_fifo.dout_2 util_ad9361_adc_cpack.adc_ch_2
+add_connection  util_ad9361_adc_fifo.dout_3 util_ad9361_adc_cpack.adc_ch_3
+add_connection  util_ad9361_adc_cpack.if_adc_valid axi_ad9361_adc_dma.if_fifo_wr_en
+add_connection  util_ad9361_adc_cpack.if_adc_sync axi_ad9361_adc_dma.if_fifo_wr_sync
+add_connection  util_ad9361_adc_cpack.if_adc_data axi_ad9361_adc_dma.if_fifo_wr_din
+add_connection sys_cpu.data_master axi_ad9361_adc_dma.s_axi
+add_interface up_enable conduit end
+add_interface up_txnrx conduit end
+add_interface delay_clk conduit end
+
+# setting interface propriety
+
+set_interface_property  axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
+set_interface_property  up_enable EXPORT_OF axi_ad9361.if_up_enable
+set_interface_property  up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
+set_interface_property  delay_clk EXPORT_OF axi_ad9361.if_delay_clk
+
+# addresses
+
+set_connection_parameter_value sys_cpu.data_master/axi_ad9361.s_axi                       baseAddress {0x10000000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9361_dac_dma.s_axi               baseAddress {0x10034000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9361_adc_dma.s_axi               baseAddress {0x10010000}
+
+set_connection_parameter_value axi_ad9361_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0    baseAddress {0x00000000}
+set_connection_parameter_value axi_ad9361_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0     baseAddress {0x00000000}
+
+
+# interrupts
+
+set_connection_parameter_value sys_cpu.irq/axi_ad9361_adc_dma.interrupt_sender irqNumber {10}
+set_connection_parameter_value sys_cpu.irq/axi_ad9361_dac_dma.interrupt_sender irqNumber {11}
+

From 283bf9ad75b126989593390e6f9a35e4fb0e5ff1 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Mon, 11 Jul 2016 18:37:18 +0300
Subject: [PATCH 311/972] fmcomms2_a10GX: Add fmcomms2 on a10gx

---
 projects/fmcomms2/a10gx/Makefile           | 150 +++++++++++++
 projects/fmcomms2/a10gx/system_constr.sdc  |  17 ++
 projects/fmcomms2/a10gx/system_project.tcl | 117 ++++++++++
 projects/fmcomms2/a10gx/system_qsys.tcl    |   7 +
 projects/fmcomms2/a10gx/system_top.v       | 250 +++++++++++++++++++++
 5 files changed, 541 insertions(+)
 create mode 100644 projects/fmcomms2/a10gx/Makefile
 create mode 100644 projects/fmcomms2/a10gx/system_constr.sdc
 create mode 100644 projects/fmcomms2/a10gx/system_project.tcl
 create mode 100644 projects/fmcomms2/a10gx/system_qsys.tcl
 create mode 100644 projects/fmcomms2/a10gx/system_top.v

diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
new file mode 100644
index 000000000..e72b8c54f
--- /dev/null
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -0,0 +1,150 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.sdc
+M_DEPS += ../common/fmcomms2_qsys.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_addsub.v
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dcfilter.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_iqcor.v
+M_DEPS += ../../../library/common/ad_mem.v
+M_DEPS += ../../../library/common/ad_mul.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_tdd_control.v
+M_DEPS += ../../../library/common/altera/DSP48E1.v
+M_DEPS += ../../../library/common/altera/MULT_MACRO.v
+M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
+M_DEPS += ../../../library/common/altera/ad_cmos_in.v
+M_DEPS += ../../../library/common/altera/ad_cmos_out.v
+M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
+M_DEPS += ../../../library/common/altera/ad_lvds_in.v
+M_DEPS += ../../../library/common/altera/ad_lvds_out.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_tdd_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/common/util_pulse_gen.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.v
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync_hw.tcl
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+M_DEPS += ../../../library/util_wfifo/util_wfifo.v
+M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl
+
+
+M_ALTERA := quartus_sh --64bit -t
+
+
+M_FLIST += *.log
+M_FLIST += *_INFO.txt
+M_FLIST += *_dump.txt
+M_FLIST += db
+M_FLIST += *.asm.rpt
+M_FLIST += *.done
+M_FLIST += *.eda.rpt
+M_FLIST += *.fit.*
+M_FLIST += *.map.*
+M_FLIST += *.sta.*
+M_FLIST += *.qsf
+M_FLIST += *.qpf
+M_FLIST += *.qws
+M_FLIST += *.sof
+M_FLIST += *.cdf
+M_FLIST += *.sld
+M_FLIST += *.qdf
+M_FLIST += hc_output
+M_FLIST += system_bd
+M_FLIST += hps_isw_handoff
+M_FLIST += hps_sdram_*.csv
+M_FLIST += *ddr3_*.csv
+M_FLIST += incremental_db
+M_FLIST += reconfig_mif
+M_FLIST += *.sopcinfo
+M_FLIST +=  *.jdi
+M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
+
+
+
+.PHONY: all clean clean-all
+all: fmcomms2_a10gx.sof
+
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+fmcomms2_a10gx.sof: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_ALTERA) system_project.tcl  >> fmcomms2_a10gx_quartus.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/projects/fmcomms2/a10gx/system_constr.sdc b/projects/fmcomms2/a10gx/system_constr.sdc
new file mode 100644
index 000000000..6274154c7
--- /dev/null
+++ b/projects/fmcomms2/a10gx/system_constr.sdc
@@ -0,0 +1,17 @@
+
+create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
+create_clock -period "4.000 ns"   -name rx_clk_250mhz       [get_ports {rx_clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
+  i_system_bd|sys_ddr3_cntrl_phy_clk_0 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_1 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_2 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \
+  i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
+  i_system_bd|sys_ddr3_cntrl_core_nios_clk}]
diff --git a/projects/fmcomms2/a10gx/system_project.tcl b/projects/fmcomms2/a10gx/system_project.tcl
new file mode 100644
index 000000000..903b406b3
--- /dev/null
+++ b/projects/fmcomms2/a10gx/system_project.tcl
@@ -0,0 +1,117 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new fmcomms2_a10gx -overwrite
+
+source "../../common/a10gx/a10gx_system_assign.tcl"
+
+set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name QSYS_FILE system_bd.qsys
+
+set_global_assignment -name SDC_FILE system_constr.sdc
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
+
+# lane interface
+
+set_location_assignment PIN_AV15 -to rx_clk_in             ; ## G6   FMC_LPC_LA00_CC_P
+set_location_assignment PIN_AU15 -to "rx_clk_in(n)"        ; ## G7   FMC_LPC_LA00_CC_N
+set_location_assignment PIN_AT10 -to rx_frame_in           ; ## D8   FMC_LPC_LA01_CC_P
+set_location_assignment PIN_AR11 -to "rx_frame_in(n)"      ; ## D9   FMC_LPC_LA01_CC_N
+set_location_assignment PIN_AR22 -to rx_data_in[0]         ; ## H7   FMC_LPC_LA02_P
+set_location_assignment PIN_AT22 -to "rx_data_in[0](n)"    ; ## H8   FMC_LPC_LA02_N
+set_location_assignment PIN_AR20 -to rx_data_in[1]         ; ## G9   FMC_LPC_LA03_P
+set_location_assignment PIN_AR19 -to "rx_data_in[1](n)"    ; ## G10  FMC_LPC_LA03_N
+set_location_assignment PIN_AN20 -to rx_data_in[2]         ; ## H10  FMC_LPC_LA04_P
+set_location_assignment PIN_AP19 -to "rx_data_in[2](n)"    ; ## H11  FMC_LPC_LA04_N
+set_location_assignment PIN_AV11 -to rx_data_in[3]         ; ## D11  FMC_LPC_LA05_P
+set_location_assignment PIN_AW11 -to "rx_data_in[3](n)"    ; ## D12  FMC_LPC_LA05_N
+set_location_assignment PIN_AV14 -to rx_data_in[4]         ; ## C10  FMC_LPC_LA06_P
+set_location_assignment PIN_AW14 -to "rx_data_in[4](n)"    ; ## C11  FMC_LPC_LA06_N
+set_location_assignment PIN_AT17 -to rx_data_in[5]         ; ## H13  FMC_LPC_LA07_P
+set_location_assignment PIN_AU17 -to "rx_data_in[5](n)"    ; ## H14  FMC_LPC_LA07_N
+set_location_assignment PIN_AP18 -to tx_clk_out            ; ## G12  FMC_LPC_LA08_P
+set_location_assignment PIN_AN19 -to "tx_clk_out(n)"       ; ## G13  FMC_LPC_LA08_N
+set_location_assignment PIN_AW13 -to tx_frame_out          ; ## D14  FMC_LPC_LA09_P
+set_location_assignment PIN_AV13 -to "tx_frame_out(n)"     ; ## D15  FMC_LPC_LA09_N
+set_location_assignment PIN_AT14 -to tx_data_out[0]        ; ## H16  FMC_LPC_LA11_P
+set_location_assignment PIN_AR14 -to "tx_data_out[0](n)"   ; ## H17  FMC_LPC_LA11_N
+set_location_assignment PIN_AR16 -to tx_data_out[1]        ; ## G15  FMC_LPC_LA12_P
+set_location_assignment PIN_AP16 -to "tx_data_out[1](n)"   ; ## G16  FMC_LPC_LA12_N
+set_location_assignment PIN_AR17 -to tx_data_out[2]        ; ## D17  FMC_LPC_LA13_P
+set_location_assignment PIN_AP17 -to "tx_data_out[2](n)"   ; ## D18  FMC_LPC_LA13_N
+set_location_assignment PIN_AR15 -to tx_data_out[3]        ; ## C14  FMC_LPC_LA10_P
+set_location_assignment PIN_AT15 -to "tx_data_out[3](n)"   ; ## C15  FMC_LPC_LA10_N
+set_location_assignment PIN_AW18 -to tx_data_out[4]        ; ## C18  FMC_LPC_LA14_P
+set_location_assignment PIN_AV18 -to "tx_data_out[4](n)"   ; ## C19  FMC_LPC_LA14_N
+set_location_assignment PIN_AR9  -to tx_data_out[5]        ; ## H19  FMC_LPC_LA15_P
+set_location_assignment PIN_AT9  -to "tx_data_out[5](n)"   ; ## H20  FMC_LPC_LA15_N
+set_location_assignment PIN_AT13 -to enable]               ; ## G18  FMC_LPC_LA16_P
+set_location_assignment PIN_AU13 -to txnrx]                ; ## G19  FMC_LPC_LA16_N
+
+set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
+set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[1]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[2]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[3]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[4]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[5]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_clk_out
+set_instance_assignment -name IO_STANDARD LVDS -to tx_frame_out
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[0]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[1]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5]
+set_instance_assignment -name IO_STANDARD LVDS -to enable
+set_instance_assignment -name IO_STANDARD LVDS -to txnrx
+
+# gpio
+
+set_location_assignment PIN_AU8   -to gpio_status[0]                   ; ## G21  FMC_LPC_LA20_P
+set_location_assignment PIN_AT8   -to gpio_status[1]                   ; ## G22  FMC_LPC_LA20_N
+set_location_assignment PIN_AY10  -to gpio_status[2]                   ; ## H25  FMC_LPC_LA21_P
+set_location_assignment PIN_AY11  -to gpio_status[3]                   ; ## H26  FMC_LPC_LA21_N
+set_location_assignment PIN_AW12  -to gpio_status[4]                   ; ## G24  FMC_LPC_LA22_P
+set_location_assignment PIN_AY12  -to gpio_status[5]                   ; ## G25  FMC_LPC_LA22_N
+set_location_assignment PIN_AU18  -to gpio_status[6]                   ; ## D23  FMC_LPC_LA23_P
+set_location_assignment PIN_AT18  -to gpio_status[7]                   ; ## D24  FMC_LPC_LA23_N
+set_location_assignment PIN_BB15  -to gpio_ctl[0]                      ; ## H28  FMC_LPC_LA24_P
+set_location_assignment PIN_BC15  -to gpio_ctl[1]                      ; ## H29  FMC_LPC_LA24_N
+set_location_assignment PIN_AY15  -to gpio_ctl[2]                      ; ## G27  FMC_LPC_LA25_P
+set_location_assignment PIN_AY14  -to gpio_ctl[3]                      ; ## G28  FMC_LPC_LA25_N
+set_location_assignment PIN_AU11  -to gpio_en_agc                      ; ## H22  FMC_LPC_LA19_P
+set_location_assignment PIN_AU12  -to gpio_sync                        ; ## H23  FMC_LPC_LA19_N
+set_location_assignment PIN_AY16  -to gpio_resetb                      ; ## H31  FMC_LPC_LA28_P
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_en_agc
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_sync
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_resetb
+
+# spi
+
+set_location_assignment PIN_AT19  -to spi_csn                          ; ## D26  FMC_LPC_LA26_P
+set_location_assignment PIN_AT20  -to spi_clk                          ; ## D27  FMC_LPC_LA26_N
+set_location_assignment PIN_AP21  -to spi_mosi                         ; ## C26  FMC_LPC_LA27_P
+set_location_assignment PIN_AR21  -to spi_miso                         ; ## C27  FMC_LPC_LA27_N
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
+
+execute_flow -compile
diff --git a/projects/fmcomms2/a10gx/system_qsys.tcl b/projects/fmcomms2/a10gx/system_qsys.tcl
new file mode 100644
index 000000000..07a5e1a90
--- /dev/null
+++ b/projects/fmcomms2/a10gx/system_qsys.tcl
@@ -0,0 +1,7 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
+source ../common/fmcomms2_qsys.tcl
+
+save_system "system_bd.qsys"
+
diff --git a/projects/fmcomms2/a10gx/system_top.v b/projects/fmcomms2/a10gx/system_top.v
new file mode 100644
index 000000000..b326ff43a
--- /dev/null
+++ b/projects/fmcomms2/a10gx/system_top.v
@@ -0,0 +1,250 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  sys_clk,
+  sys_resetn,
+
+  // ddr3
+
+  ddr3_clk_p,
+  ddr3_clk_n,
+  ddr3_a,
+  ddr3_ba,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_odt,
+  ddr3_reset_n,
+  ddr3_we_n,
+  ddr3_ras_n,
+  ddr3_cas_n,
+  ddr3_dqs_p,
+  ddr3_dqs_n,
+  ddr3_dq,
+  ddr3_dm,
+  ddr3_rzq,
+  ddr3_ref_clk,
+
+  // ethernet
+
+  eth_ref_clk,
+  eth_rxd,
+  eth_txd,
+  eth_mdc,
+  eth_mdio,
+  eth_resetn,
+  eth_intn,
+
+  // board gpio
+
+  gpio_bd_i,
+  gpio_bd_o,
+
+  // ad9361-interface
+
+  rx_clk_in,
+  rx_frame_in,
+  rx_data_in,
+  tx_clk_out,
+  tx_frame_out,
+  tx_data_out,
+
+  enable,
+  txnrx,
+
+  gpio_resetb,
+  gpio_sync,
+  gpio_en_agc,
+  gpio_ctl,
+  gpio_status,
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso);
+
+
+ // clock and resets
+
+  input             sys_clk;
+  input             sys_resetn;
+
+  // ddr3
+
+  output            ddr3_clk_p;
+  output            ddr3_clk_n;
+  output  [ 14:0]   ddr3_a;
+  output  [  2:0]   ddr3_ba;
+  output            ddr3_cke;
+  output            ddr3_cs_n;
+  output            ddr3_odt;
+  output            ddr3_reset_n;
+  output            ddr3_we_n;
+  output            ddr3_ras_n;
+  output            ddr3_cas_n;
+  inout   [  7:0]   ddr3_dqs_p;
+  inout   [  7:0]   ddr3_dqs_n;
+  inout   [ 63:0]   ddr3_dq;
+  output  [  7:0]   ddr3_dm;
+  input             ddr3_rzq;
+  input             ddr3_ref_clk;
+
+  // ethernet
+
+  input             eth_ref_clk;
+  input             eth_rxd;
+  output            eth_txd;
+  output            eth_mdc;
+  inout             eth_mdio;
+  output            eth_resetn;
+  input             eth_intn;
+
+  // board gpio
+
+  input   [ 10:0]   gpio_bd_i;
+  output  [ 15:0]   gpio_bd_o;
+
+  // ad9361-interface
+
+  input             rx_clk_in;
+  input             rx_frame_in;
+  input   [  5:0]   rx_data_in;
+  output            tx_clk_out;
+  output            tx_frame_out;
+  output  [  5:0]   tx_data_out;
+  output            enable;
+  output            txnrx;
+
+  output            gpio_resetb;
+  output            gpio_sync;
+  output            gpio_en_agc;
+  output  [  3:0]   gpio_ctl;
+  input   [  7:0]   gpio_status;
+
+  output            spi_csn;
+  output            spi_clk;
+  output            spi_mosi;
+  input             spi_miso;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // conections
+
+  assign gpio_resetb    = gpio_o[46];
+  assign gpio_sync      = gpio_o[45];
+  assign gpio_en_agc    = gpio_o[44];
+  assign gpio_ctl       = gpio_o[43:40];
+  assign gpio_i[39:32]  = gpio_status;
+
+  assign gpio_bd_o      = gpio_o[15:0];
+
+  assign gpio_i[31:27]  = gpio_o[31:27];
+  assign gpio_i[15: 0]  = gpio_o[15:0];
+  assign gpio_i[26:16]  = gpio_bd_i;
+
+  // instantiations
+
+ system_bd i_system_bd (
+    .sys_clk_clk (sys_clk),
+    .sys_rst_reset_n (sys_resetn),
+
+    .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
+    .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
+    .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
+    .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
+    .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
+
+    .sys_ethernet_mdio_mdc (eth_mdc),
+    .sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .sys_ethernet_ref_clk_clk (eth_ref_clk),
+    .sys_ethernet_reset_reset (eth_reset),
+    .sys_ethernet_sgmii_rxp_0 (eth_rxd),
+    .sys_ethernet_sgmii_txp_0 (eth_txd),
+
+    .sys_gpio_bd_in_port (gpio_i[31:0]),
+    .sys_gpio_bd_out_port (gpio_o[31:0]),
+    .sys_gpio_in_export (gpio_i[63:32]),
+    .sys_gpio_out_export (gpio_o[63:32]),
+
+    .axi_ad9361_device_if_enable (enable),
+    .axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
+    .axi_ad9361_device_if_rx_clk_in_n (1'b0),
+    .axi_ad9361_device_if_rx_data_in_p (rx_data_in),
+    .axi_ad9361_device_if_rx_data_in_n (6'd0),
+    .axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
+    .axi_ad9361_device_if_rx_frame_in_n (1'b0),
+    .axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
+    .axi_ad9361_device_if_tx_clk_out_n (1'b0),
+    .axi_ad9361_device_if_tx_data_out_p (tx_data_out),
+    .axi_ad9361_device_if_tx_data_out_n (6'd0),
+    .axi_ad9361_device_if_tx_frame_out_p (tx_frame_out),
+    .axi_ad9361_device_if_tx_frame_out_n (1'b0),
+    .axi_ad9361_device_if_txnrx (txnrx),
+
+    .delay_clk_clk (1'b0),
+
+    .up_enable_up_enable (gpio_o[47]),
+    .up_txnrx_up_txnrx (gpio_o[48]));
+
+endmodule
+
+
+// ***************************************************************************
+// ***************************************************************************

From 12abe2b6b903c8384f0115737ef457f60d10bc87 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <Andrei.Grozav@analog.com>
Date: Tue, 12 Jul 2016 09:39:24 +0300
Subject: [PATCH 312/972] fmcomms2: Makefile update

---
 projects/fmcomms2/Makefile       | 3 +++
 projects/fmcomms2/a10gx/Makefile | 3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/fmcomms2/Makefile b/projects/fmcomms2/Makefile
index 895391c8a..a56d97d9b 100644
--- a/projects/fmcomms2/Makefile
+++ b/projects/fmcomms2/Makefile
@@ -7,6 +7,7 @@
 
 .PHONY: all clean clean-all 
 all:
+	-make -C a10gx all
 	-make -C ac701 all
 	-make -C kc705 all
 	-make -C mitx045 all
@@ -18,6 +19,7 @@ all:
 
 
 clean: 
+	make -C a10gx clean
 	make -C ac701 clean
 	make -C kc705 clean
 	make -C mitx045 clean
@@ -29,6 +31,7 @@ clean:
 
 
 clean-all:
+	make -C a10gx clean-all
 	make -C ac701 clean-all
 	make -C kc705 clean-all
 	make -C mitx045 clean-all
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index e72b8c54f..8d08ed786 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -75,7 +75,6 @@ M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_tdd_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/common/util_pulse_gen.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
@@ -85,8 +84,6 @@ M_DEPS += ../../../library/util_cpack/util_cpack.v
 M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
 M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
 M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
-M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.v
-M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync_hw.tcl
 M_DEPS += ../../../library/util_upack/util_upack.v
 M_DEPS += ../../../library/util_upack/util_upack_dmx.v
 M_DEPS += ../../../library/util_upack/util_upack_dsf.v

From 1df942b752878cb90e4fc01744b1c4010dd5b28a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 12 Jul 2016 10:24:02 -0400
Subject: [PATCH 313/972] rfifo- buffer 1 seg before read

---
 library/util_rfifo/util_rfifo.v          | 42 ++++++++++++++++--------
 library/util_rfifo/util_rfifo_constr.sdc |  1 +
 library/util_rfifo/util_rfifo_constr.xdc |  1 +
 3 files changed, 31 insertions(+), 13 deletions(-)

diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v
index 939ea820c..e0b35a19b 100644
--- a/library/util_rfifo/util_rfifo.v
+++ b/library/util_rfifo/util_rfifo.v
@@ -107,7 +107,7 @@ module util_rfifo (
   parameter   DIN_ADDRESS_WIDTH = 8;
 
   localparam  M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
-  localparam  ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4;
+  localparam  ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 5) ? DIN_ADDRESS_WIDTH : 5;
   localparam  DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;
   localparam  T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;
   localparam  T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;
@@ -177,17 +177,21 @@ module util_rfifo (
   reg     [(DATA_WIDTH-1):0]          din_wdata = 'd0;
   reg     [(ADDRESS_WIDTH-1):0]       din_waddr = 'hc;
   reg                                 din_wr = 'd0;
+  reg                                 din_valid = 'd0;
   reg     [ 6:0]                      din_req_cnt = 'd0;
   reg     [ 7:0]                      din_enable_m1 = 'd0;
   reg     [ 7:0]                      din_enable = 'd0;
   reg                                 din_req_t_m1 = 'd0;
   reg                                 din_req_t_m2 = 'd0;
   reg                                 din_req_t_m3 = 'd0;
+  reg                                 din_req = 'd0;
+  reg     [(ADDRESS_WIDTH-4):0]       din_rinit = 'd0;
   reg                                 din_unf_d = 'd0;
   reg     [(T_DOUT_DATA_WIDTH+1):0]   dout_data = 'd0;
   reg     [(DATA_WIDTH-1):0]          dout_rdata = 'd0;
   reg     [ 7:0]                      dout_enable = 'd0;
   reg                                 dout_req_t = 'd0;
+  reg     [(ADDRESS_WIDTH-4):0]       dout_rinit = 'd0;
   reg     [(ADDRESS_WIDTH-1):0]       dout_raddr = 'd0;
   reg                                 dout_unf_m1 = 'd0;
   reg                                 dout_unf = 'd0;
@@ -216,14 +220,14 @@ module util_rfifo (
   assign din_enable_1 = din_enable[1];
   assign din_enable_0 = din_enable[0];
 
-  assign din_valid_7 = din_req_cnt[6];
-  assign din_valid_6 = din_req_cnt[6];
-  assign din_valid_5 = din_req_cnt[6];
-  assign din_valid_4 = din_req_cnt[6];
-  assign din_valid_3 = din_req_cnt[6];
-  assign din_valid_2 = din_req_cnt[6];
-  assign din_valid_1 = din_req_cnt[6];
-  assign din_valid_0 = din_req_cnt[6];
+  assign din_valid_7 = din_valid;
+  assign din_valid_6 = din_valid;
+  assign din_valid_5 = din_valid;
+  assign din_valid_4 = din_valid;
+  assign din_valid_3 = din_valid;
+  assign din_valid_2 = din_valid;
+  assign din_valid_1 = din_valid;
+  assign din_valid_0 = din_valid;
 
   assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4,
                         din_data_3, din_data_2, din_data_1, din_data_0};
@@ -235,14 +239,14 @@ module util_rfifo (
   for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in
   if (M_MEM_RATIO == 1) begin
   always @(posedge din_clk) begin
-    if (din_req_cnt[6] == 1'b1) begin
+    if (din_valid == 1'b1) begin
       din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
         din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)];
     end
   end
   end else begin
   always @(posedge din_clk) begin
-    if (din_req_cnt[6] == 1'b1) begin
+    if (din_valid == 1'b1) begin
       din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
         {din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)],
         din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]};
@@ -257,7 +261,9 @@ module util_rfifo (
       din_waddr <= 'hc;
       din_wr <= 1'd0;
     end else begin
-      if (din_wr == 1'b1) begin
+      if (din_req == 1'b1) begin
+        din_waddr <= {din_rinit, 3'd0};
+      end else if (din_wr == 1'b1) begin
         din_waddr <= din_waddr + 1'b1;
       end
       case (M_MEM_RATIO)
@@ -271,8 +277,10 @@ module util_rfifo (
 
   always @(posedge din_clk or negedge din_rstn) begin
     if (din_rstn == 1'b0) begin
+      din_valid <= 'd0;
       din_req_cnt <= 'd0;
     end else begin
+      din_valid <= din_req_cnt[6];
       if (din_req_s == 1'b1) begin
         case (M_MEM_RATIO)
           8: din_req_cnt <= 7'h40;
@@ -295,6 +303,8 @@ module util_rfifo (
       din_req_t_m1 <= 'd0;
       din_req_t_m2 <= 'd0;
       din_req_t_m3 <= 'd0;
+      din_req <= 'd0;
+      din_rinit <= 'd0;
       din_unf_d <= 'd0;
     end else begin
       din_enable_m1 <= dout_enable;
@@ -302,6 +312,10 @@ module util_rfifo (
       din_req_t_m1 <= dout_req_t;
       din_req_t_m2 <= din_req_t_m1;
       din_req_t_m3 <= din_req_t_m2;
+      din_req <= din_req_s;
+      if (din_req_s == 1'b1) begin
+        din_rinit <= dout_rinit;
+      end
       din_unf_d <= din_unf;
     end
   end
@@ -353,12 +367,14 @@ module util_rfifo (
     if (dout_rst == 1'b1) begin
       dout_enable <= 'd0;
       dout_req_t <= 'd0;
+      dout_rinit <= 'd0;
       dout_raddr <= 'd0;
     end else begin
       dout_enable <= dout_enable_s;
       if (dout_valid_s[0] == 1'b1) begin
-        if (dout_raddr[2:0] == 3'd0) begin
+        if (dout_raddr[2:0] == 3'd7) begin
           dout_req_t <= ~dout_req_t;
+          dout_rinit <= dout_raddr[(ADDRESS_WIDTH-1):3] + 2'd2;
         end
         dout_raddr <= dout_raddr + 1'b1;
       end
diff --git a/library/util_rfifo/util_rfifo_constr.sdc b/library/util_rfifo/util_rfifo_constr.sdc
index 99764df65..22c99c8cf 100644
--- a/library/util_rfifo/util_rfifo_constr.sdc
+++ b/library/util_rfifo/util_rfifo_constr.sdc
@@ -1,5 +1,6 @@
 
 set_false_path -from [get_registers *dout_enable*]  -to [get_registers *din_enable_m1*]
 set_false_path -from [get_registers *dout_req_t*]   -to [get_registers *din_req_t_m1*]
+set_false_path -from [get_registers *dout_rinit*]   -to [get_registers *din_rinit*]
 set_false_path -from [get_registers *din_unf_d*]    -to [get_registers *dout_unf_m1*]
 
diff --git a/library/util_rfifo/util_rfifo_constr.xdc b/library/util_rfifo/util_rfifo_constr.xdc
index cb8c395cf..dc0d606ed 100644
--- a/library/util_rfifo/util_rfifo_constr.xdc
+++ b/library/util_rfifo/util_rfifo_constr.xdc
@@ -5,5 +5,6 @@ set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_unf_m*}]
 
 set_false_path -from [get_cells -hier -filter {name =~ *dout_enable*  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_enable_m1*  && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {name =~ *dout_req_t*   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_req_t_m1*   && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *dout_rinit*   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_rinit*      && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {name =~ *din_unf*      && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_unf_m1*    && IS_SEQUENTIAL}]
 

From 62c7114d77e76a2f10da6b9c1efa3dac63378d08 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Wed, 13 Jul 2016 18:46:34 +0200
Subject: [PATCH 314/972] Enable bitstream compression for Xilinx projects

Enabling bitstream compression reduces the size of the generated bitstream.

This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.

On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.

The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.

When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.

Initial tests show a reduction of a round 50% in size for most ADI
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/common/xilinx/compression_system_constr.xdc | 1 +
 projects/scripts/adi_project.tcl                     | 6 ++++++
 2 files changed, 7 insertions(+)
 create mode 100644 projects/common/xilinx/compression_system_constr.xdc

diff --git a/projects/common/xilinx/compression_system_constr.xdc b/projects/common/xilinx/compression_system_constr.xdc
new file mode 100644
index 000000000..94ea80e52
--- /dev/null
+++ b/projects/common/xilinx/compression_system_constr.xdc
@@ -0,0 +1 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index 91144dc7d..d18d626b8 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -141,6 +141,12 @@ proc adi_project_create {project_name {mode 0}} {
   } else {
     write_hwdef -file "$project_name.data/$project_name.hwdef"
   }
+
+  if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] || ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
+    add_files -norecurse -fileset sources_1 \
+		"$ad_hdl_dir/projects/common/xilinx/compression_system_constr.xdc"
+  }
+
 }
 
 proc adi_project_files {project_name project_files} {

From 44d9f98e12d1dffbb881979ce4ae2aa729d32918 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Wed, 13 Jul 2016 18:46:34 +0200
Subject: [PATCH 315/972] adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION
 detection logic

Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/scripts/adi_project.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index d18d626b8..d715725eb 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -142,7 +142,7 @@ proc adi_project_create {project_name {mode 0}} {
     write_hwdef -file "$project_name.data/$project_name.hwdef"
   }
 
-  if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] || ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
+  if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
     add_files -norecurse -fileset sources_1 \
 		"$ad_hdl_dir/projects/common/xilinx/compression_system_constr.xdc"
   }

From d6243f3d013ee08ddf329a26607f91244c853972 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Mon, 18 Jul 2016 08:59:56 -0400
Subject: [PATCH 316/972] update in fmcomms11 tcl and clock constrains

---
 projects/fmcomms11/common/fmcomms11_bd.tcl | 185 +++++++++++++++++----
 projects/fmcomms11/zc706/system_constr.xdc |   4 +-
 2 files changed, 154 insertions(+), 35 deletions(-)

diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index a69687798..44ae5d456 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -60,66 +60,74 @@ set axi_fmcomms11_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:
 set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL1_REFCLK_DIV {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL0_CFG {0x06801C1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL1_CFG {0x06801C1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL0_FBDIV_RATIO {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL1_FBDIV_RATIO {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL0_FBDIV {"0010000000"}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL1_FBDIV {"0010000000"}] $axi_fmcomms11_gt   
+set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_0 {7}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_0 {7}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff10400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_1 {7}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_1 {7}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff10400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_2 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_2 {7}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_2 {7}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff10400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_3 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_3 {7}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_3 {7}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff10400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_4 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_4 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_4 {7}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_4 {7}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff10400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_5 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_5 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_5 {7}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_5 {7}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff10400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_6 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_6 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_6 {7}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_6 {7}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff10400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.CPLL_FBDIV_7 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_7 {25}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CLK25_DIV_7 {7}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.TX_CLK25_DIV_7 {7}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff10400020}] $axi_fmcomms11_gt
 
 set util_fmcomms11_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcomms11_gt]
 set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_fmcomms11_gt
@@ -132,7 +140,7 @@ set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_gt
 
 # connections (gt)
 
-ad_connect  util_fmcomms11_gt/qpll_ref_clk rx_ref_clk
+ad_connect  util_fmcomms11_gt/qpll_ref_clk tx_ref_clk
 ad_connect  util_fmcomms11_gt/cpll_ref_clk tx_ref_clk
 
 ad_connect  axi_fmcomms11_gt/gt_qpll_0 util_fmcomms11_gt/gt_qpll_0
@@ -267,3 +275,114 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
 
 ad_cpu_interrupt ps-12 mb-12 axi_ad9162_dma/irq
 ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
+
+# unused
+
+ad_connect  axi_ad9162_fifo/dac_fifo_bypass GND
+
+# ila
+
+create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ad9625_ila
+set_property CONFIG.C_MONITOR_TYPE {Native} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_NUM_OF_PROBES {33} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE0_WIDTH  {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE1_WIDTH  {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE2_WIDTH  {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE3_WIDTH  {32} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE4_WIDTH  {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE5_WIDTH  {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE6_WIDTH  {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE7_WIDTH  {32} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE8_WIDTH  {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE9_WIDTH  {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE10_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE11_WIDTH {32} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE12_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE13_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE14_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE15_WIDTH {32} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE16_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE17_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE18_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE19_WIDTH {32} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE20_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE21_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE22_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE23_WIDTH {32} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE24_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE25_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE26_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE27_WIDTH {32} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE28_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE29_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE30_WIDTH {4}  [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE31_WIDTH {32} [get_bd_cells ad9625_ila]
+set_property CONFIG.C_PROBE32_WIDTH {1}  [get_bd_cells ad9625_ila]
+
+ad_connect  axi_ad9625_jesd/gt0_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_0   
+ad_connect  axi_ad9625_jesd/gt0_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_0   
+ad_connect  axi_ad9625_jesd/gt0_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_0
+ad_connect  axi_ad9625_jesd/gt0_rxdata       axi_fmcomms11_gt/rx_gt_data_0      
+ad_connect  axi_ad9625_jesd/gt1_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_1   
+ad_connect  axi_ad9625_jesd/gt1_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_1   
+ad_connect  axi_ad9625_jesd/gt1_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_1
+ad_connect  axi_ad9625_jesd/gt1_rxdata       axi_fmcomms11_gt/rx_gt_data_1      
+ad_connect  axi_ad9625_jesd/gt2_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_2   
+ad_connect  axi_ad9625_jesd/gt2_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_2   
+ad_connect  axi_ad9625_jesd/gt2_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_2
+ad_connect  axi_ad9625_jesd/gt2_rxdata       axi_fmcomms11_gt/rx_gt_data_2      
+ad_connect  axi_ad9625_jesd/gt3_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_3   
+ad_connect  axi_ad9625_jesd/gt3_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_3   
+ad_connect  axi_ad9625_jesd/gt3_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_3
+ad_connect  axi_ad9625_jesd/gt3_rxdata       axi_fmcomms11_gt/rx_gt_data_3      
+ad_connect  axi_ad9625_jesd/gt4_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_4   
+ad_connect  axi_ad9625_jesd/gt4_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_4   
+ad_connect  axi_ad9625_jesd/gt4_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_4
+ad_connect  axi_ad9625_jesd/gt4_rxdata       axi_fmcomms11_gt/rx_gt_data_4      
+ad_connect  axi_ad9625_jesd/gt5_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_5   
+ad_connect  axi_ad9625_jesd/gt5_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_5   
+ad_connect  axi_ad9625_jesd/gt5_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_5
+ad_connect  axi_ad9625_jesd/gt5_rxdata       axi_fmcomms11_gt/rx_gt_data_5      
+ad_connect  axi_ad9625_jesd/gt6_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_6   
+ad_connect  axi_ad9625_jesd/gt6_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_6   
+ad_connect  axi_ad9625_jesd/gt6_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_6
+ad_connect  axi_ad9625_jesd/gt6_rxdata       axi_fmcomms11_gt/rx_gt_data_6      
+ad_connect  axi_ad9625_jesd/gt7_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_7   
+ad_connect  axi_ad9625_jesd/gt7_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_7   
+ad_connect  axi_ad9625_jesd/gt7_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_7
+ad_connect  axi_ad9625_jesd/gt7_rxdata       axi_fmcomms11_gt/rx_gt_data_7      
+
+ad_connect  axi_fmcomms11_gt/rx_gt_charisk_0    ad9625_ila/probe0
+ad_connect  axi_fmcomms11_gt/rx_gt_disperr_0    ad9625_ila/probe1
+ad_connect  axi_fmcomms11_gt/rx_gt_notintable_0 ad9625_ila/probe2
+ad_connect  axi_fmcomms11_gt/rx_gt_data_0       ad9625_ila/probe3
+ad_connect  axi_fmcomms11_gt/rx_gt_charisk_1    ad9625_ila/probe4
+ad_connect  axi_fmcomms11_gt/rx_gt_disperr_1    ad9625_ila/probe5
+ad_connect  axi_fmcomms11_gt/rx_gt_notintable_1 ad9625_ila/probe6
+ad_connect  axi_fmcomms11_gt/rx_gt_data_1       ad9625_ila/probe7
+ad_connect  axi_fmcomms11_gt/rx_gt_charisk_2    ad9625_ila/probe8
+ad_connect  axi_fmcomms11_gt/rx_gt_disperr_2    ad9625_ila/probe9
+ad_connect  axi_fmcomms11_gt/rx_gt_notintable_2 ad9625_ila/probe10
+ad_connect  axi_fmcomms11_gt/rx_gt_data_2       ad9625_ila/probe11
+ad_connect  axi_fmcomms11_gt/rx_gt_charisk_3    ad9625_ila/probe12
+ad_connect  axi_fmcomms11_gt/rx_gt_disperr_3    ad9625_ila/probe13
+ad_connect  axi_fmcomms11_gt/rx_gt_notintable_3 ad9625_ila/probe14
+ad_connect  axi_fmcomms11_gt/rx_gt_data_3       ad9625_ila/probe15
+ad_connect  axi_fmcomms11_gt/rx_gt_charisk_4    ad9625_ila/probe16
+ad_connect  axi_fmcomms11_gt/rx_gt_disperr_4    ad9625_ila/probe17
+ad_connect  axi_fmcomms11_gt/rx_gt_notintable_4 ad9625_ila/probe18
+ad_connect  axi_fmcomms11_gt/rx_gt_data_4       ad9625_ila/probe19
+ad_connect  axi_fmcomms11_gt/rx_gt_charisk_5    ad9625_ila/probe20
+ad_connect  axi_fmcomms11_gt/rx_gt_disperr_5    ad9625_ila/probe21
+ad_connect  axi_fmcomms11_gt/rx_gt_notintable_5 ad9625_ila/probe22
+ad_connect  axi_fmcomms11_gt/rx_gt_data_5       ad9625_ila/probe23
+ad_connect  axi_fmcomms11_gt/rx_gt_charisk_6    ad9625_ila/probe24
+ad_connect  axi_fmcomms11_gt/rx_gt_disperr_6    ad9625_ila/probe25
+ad_connect  axi_fmcomms11_gt/rx_gt_notintable_6 ad9625_ila/probe26
+ad_connect  axi_fmcomms11_gt/rx_gt_data_6       ad9625_ila/probe27
+ad_connect  axi_fmcomms11_gt/rx_gt_charisk_7    ad9625_ila/probe28
+ad_connect  axi_fmcomms11_gt/rx_gt_disperr_7    ad9625_ila/probe29
+ad_connect  axi_fmcomms11_gt/rx_gt_notintable_7 ad9625_ila/probe30
+ad_connect  axi_fmcomms11_gt/rx_gt_data_7       ad9625_ila/probe31
+ad_connect  axi_ad9625_jesd/rx_sync             ad9625_ila/probe32
+ad_connect  util_fmcomms11_gt/rx_out_clk        ad9625_ila/clk
diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc
index 8bc2535be..4f0d4369d 100644
--- a/projects/fmcomms11/zc706/system_constr.xdc
+++ b/projects/fmcomms11/zc706/system_constr.xdc
@@ -65,8 +65,8 @@ set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports ad9162_i
 
 # clocks
 
-create_clock -name tx_ref_clk   -period  1.60 [get_ports tx_ref_clk_p]
-create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
+create_clock -name tx_ref_clk   -period  6.40 [get_ports tx_ref_clk_p]
+create_clock -name rx_ref_clk   -period  6.40 [get_ports rx_ref_clk_p]
 create_clock -name tx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_fmcomms11_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
 create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_fmcomms11_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
 

From 74f45cff240d8d75e71ac852868d66ce63637fe9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 19 Jul 2016 16:21:13 -0400
Subject: [PATCH 317/972] axi-ad9625: fix clock ratio to match sampling clock

---
 library/axi_ad9625/axi_ad9625.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v
index 9f7be37ba..18ef759f6 100644
--- a/library/axi_ad9625/axi_ad9625.v
+++ b/library/axi_ad9625/axi_ad9625.v
@@ -227,7 +227,7 @@ module axi_ad9625 (
     .adc_sync_status (1'd0),
     .adc_status_ovf (adc_dovf),
     .adc_status_unf (adc_dunf),
-    .adc_clk_ratio (32'd1),
+    .adc_clk_ratio (32'd16),
     .adc_start_code (),
     .adc_sync (),
     .up_status_pn_err (up_adc_pn_err_s),

From c75289be214d1ae21cca2e20d8d110798717235c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 19 Jul 2016 16:21:49 -0400
Subject: [PATCH 318/972] fmcomms11- use qpll tx-12g5, cpll rx-6g25

---
 projects/fmcomms11/common/fmcomms11_bd.tcl | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index 44ae5d456..2a753b8f2 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -62,16 +62,16 @@ set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.QPLL1_REFCLK_DIV {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL0_CFG {0x06801C1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL1_CFG {0x06801C1}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL0_CFG {0x0680181}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL1_CFG {0x0680181}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.QPLL0_FBDIV_RATIO {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.QPLL1_FBDIV_RATIO {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL0_FBDIV {"0010000000"}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL1_FBDIV {"0010000000"}] $axi_fmcomms11_gt   
+set_property -dict [list CONFIG.QPLL0_FBDIV {"0100100000"}] $axi_fmcomms11_gt
+set_property -dict [list CONFIG.QPLL1_FBDIV {"0100100000"}] $axi_fmcomms11_gt   
 set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_fmcomms11_gt
 set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_fmcomms11_gt
@@ -173,6 +173,10 @@ ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_0 axi_ad9625_jesd/rxencommaal
 ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_1 axi_ad9625_jesd/rxencommaalign_out
 ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_2 axi_ad9625_jesd/rxencommaalign_out
 ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_3 axi_ad9625_jesd/rxencommaalign_out
+ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_4 axi_ad9625_jesd/rxencommaalign_out
+ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_5 axi_ad9625_jesd/rxencommaalign_out
+ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_6 axi_ad9625_jesd/rxencommaalign_out
+ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_7 axi_ad9625_jesd/rxencommaalign_out
 ad_connect  axi_fmcomms11_gt/gt_tx_0 util_fmcomms11_gt/gt_tx_0
 ad_connect  axi_fmcomms11_gt/gt_tx_1 util_fmcomms11_gt/gt_tx_1
 ad_connect  axi_fmcomms11_gt/gt_tx_2 util_fmcomms11_gt/gt_tx_2

From b48401175ae4e12af8d65ed3ef525ee39817b3c1 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 10:59:58 +0300
Subject: [PATCH 319/972] axi_dacfifo: Optimize the AXI write logic

---
 library/axi_dacfifo/axi_dacfifo_wr.v | 75 +++++++++++++++-------------
 1 file changed, 40 insertions(+), 35 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index 893a70506..c3170b6e9 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -174,9 +174,8 @@ module axi_dacfifo_wr (
   reg     [31:0]                            dma_addr_cnt = 32'b0;
   reg     [31:0]                            dma_last_addr = 32'b0;
 
-
-  reg     [ 2:0]                            axi_xfer_req_m = 3'b0;
-  reg     [ 2:0]                            axi_xfer_last_m = 3'b0;
+  reg     [ 4:0]                            axi_xfer_req_m = 3'b0;
+  reg     [ 4:0]                            axi_xfer_last_m = 3'b0;
 
   reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr_m1 = 'b0;
   reg     [(DMA_MEM_ADDRESS_WIDTH-1):0]     axi_mem_waddr_m2 = 'b0;
@@ -190,6 +189,7 @@ module axi_dacfifo_wr (
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     axi_mem_raddr_g = 'd0;
   reg                                       axi_mem_read_en = 1'b0;
   reg                                       axi_mem_read_en_d = 1'b0;
+  reg                                       axi_mem_read_en_delay = 1'b0;
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     axi_mem_addr_diff = 'b0;
   reg                                       axi_mem_last_read_toggle = 1'b0;
 
@@ -202,8 +202,8 @@ module axi_dacfifo_wr (
   reg                                       axi_werror = 1'b0;
   reg     [ 3:0]                            axi_wvalid_counter = 4'b0;
 
-  reg                                       axi_last_transaction = 1'b0;
-  reg                                       axi_last_transaction_d = 1'b0;
+  reg                                       axi_endof_transaction = 1'b0;
+  reg                                       axi_endof_transaction_d = 1'b0;
 
   // internal signals
 
@@ -218,7 +218,6 @@ module axi_dacfifo_wr (
   wire    [(AXI_DATA_WIDTH-1):0]            axi_mem_rdata_s;
   wire                                      axi_mem_rvalid_s;
   wire                                      axi_mem_last_s;
-  wire                                      axi_mem_eot_s;
 
   wire                                      axi_waddr_ready_s;
   wire                                      axi_wready_s;
@@ -379,15 +378,15 @@ module axi_dacfifo_wr (
 
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
-      axi_xfer_req_m <= 3'b0;
-      axi_xfer_last_m <= 3'b0;
+      axi_xfer_req_m <= 4'b0;
+      axi_xfer_last_m <= 5'b0;
       axi_xfer_init <= 1'b0;
       axi_mem_waddr_m1 <= 'b0;
       axi_mem_waddr_m2 <= 'b0;
       axi_mem_waddr <= 'b0;
     end else begin
-      axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
-      axi_xfer_last_m <= {axi_xfer_last_m[1:0], dma_xfer_last};
+      axi_xfer_req_m <= {axi_xfer_req_m[3:0], dma_xfer_req};
+      axi_xfer_last_m <= {axi_xfer_last_m[3:0], dma_xfer_last};
       axi_xfer_init = ~axi_xfer_req_m[2] & axi_xfer_req_m[1];
       axi_mem_waddr_m1 <= dma_mem_waddr_g;
       axi_mem_waddr_m2 <= axi_mem_waddr_m1;
@@ -409,6 +408,22 @@ module axi_dacfifo_wr (
 
   assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr_s} - axi_mem_raddr;
 
+  always @(posedge axi_clk) begin
+    if (axi_resetn == 1'b0) begin
+      axi_endof_transaction <= 1'b0;
+      axi_endof_transaction_d <= 1'b0;
+      axi_mem_addr_diff <= 'b0;
+    end else begin
+     axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0];
+     axi_endof_transaction_d <= axi_endof_transaction;
+     if ((axi_xfer_req_m[4] == 1'b1) && (axi_xfer_last_m[4] == 1'b1) && (axi_xfer_last_m[3] == 1'b0)) begin
+        axi_endof_transaction <= 1'b1;
+      end else if((axi_endof_transaction == 1'b1) && (axi_wlast == 1'b1) && ((axi_mem_addr_diff == 0) || (axi_mem_addr_diff > AXI_LENGTH))) begin
+        axi_endof_transaction <= 1'b0;
+      end
+    end
+  end
+
   // The asymmetric memory have to have enough data for at least one AXI burst,
   // before the controller start an AXI write transaction.
 
@@ -416,27 +431,29 @@ module axi_dacfifo_wr (
     if (axi_resetn == 1'b0) begin
       axi_mem_read_en <= 1'b0;
       axi_mem_read_en_d <= 1'b0;
+      axi_mem_read_en_delay <= 1'b0;
       axi_mem_addr_diff <= 'b0;
     end else begin
       axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0];
-      if (axi_mem_read_en == 1'b0) begin
-        if (((axi_xfer_req_m[2] == 1'b1) && (axi_mem_addr_diff > AXI_LENGTH) && (axi_last_transaction_d == 1'b0)) ||
-             (axi_last_transaction == 1'b1) && (axi_last_transaction_d == 1'b0)) begin
+      if ((axi_mem_read_en == 1'b0) && (axi_mem_read_en_delay == 1'b0)) begin
+        if (((axi_xfer_req_m[2] == 1'b1) && (axi_mem_addr_diff > AXI_LENGTH)) ||
+            ((axi_endof_transaction == 1'b1) && (axi_mem_addr_diff > AXI_LENGTH)) ||
+            ((axi_endof_transaction == 1'b1) && (axi_mem_addr_diff > 0))) begin
           axi_mem_read_en <= 1'b1;
         end
       end else if (axi_mem_last_s == 1'b1) begin
         axi_mem_read_en <= 1'b0;
+        axi_mem_read_en_delay <= 1;
+      end
+      if (axi_wlast == 1'b1) begin
+        axi_mem_read_en_delay <= 0;
       end
       axi_mem_read_en_d <= axi_mem_read_en;
     end
   end
 
-  // If there is enough data and the AXI interface is ready, we can start to read
-  // out data from the memory
-
   assign axi_mem_rvalid_s =  axi_mem_read_en & axi_wready_s;
   assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_rvalid_s : 1'b0;
-  assign axi_mem_eot_s = axi_wlast & axi_last_transaction;
 
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
@@ -457,9 +474,9 @@ module axi_dacfifo_wr (
       axi_mem_rdata <= axi_mem_rdata_s;
       if (axi_mem_rvalid_s == 1'b1) begin
         axi_mem_raddr <= axi_mem_raddr + 1;
-        axi_wvalid_counter <= (axi_wvalid_counter == axi_awlen) ? 4'b0 : axi_wvalid_counter + 1;
+        axi_wvalid_counter <= ((axi_wvalid_counter == axi_awlen) || (axi_xfer_init == 1'b1)) ? 4'b0 : axi_wvalid_counter + 1;
       end
-      if (axi_mem_eot_s == 1'b1) begin
+      if ((axi_endof_transaction == 1'b0) && (axi_endof_transaction_d == 1'b1)) begin
         axi_mem_raddr <= 'b0;
         axi_mem_last_read_toggle <= ~axi_mem_last_read_toggle;
       end
@@ -467,20 +484,6 @@ module axi_dacfifo_wr (
     end
   end
 
-  always @(posedge axi_clk) begin
-    if (axi_resetn == 1'b0) begin
-      axi_last_transaction <= 1'b0;
-      axi_last_transaction_d <= 1'b0;
-    end else begin
-      if ((axi_xfer_req_m[2] == 1'b1) && (axi_xfer_last_m[2] == 1'b1)) begin
-        axi_last_transaction <= 1'b1;
-      end else if (axi_wlast == 1'b1) begin
-        axi_last_transaction <= 1'b0;
-      end
-      axi_last_transaction_d <= axi_last_transaction;
-    end
-  end
-
   // AXI Memory Map interface write address channel
 
   assign axi_awid = 4'b0000;
@@ -517,10 +520,12 @@ module axi_dacfifo_wr (
       end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
         axi_awaddr <= axi_awaddr +  AXI_AWINCR;
       end
-      if(axi_xfer_last_m[2] == 1'b1) begin
-        axi_last_addr <= axi_awaddr;
+      if (axi_xfer_last_m[2] == 1'b1) begin
         axi_xfer_out <= 1'b1;
       end
+      if ((axi_awvalid == 1'b1) && (axi_endof_transaction == 1'b1)) begin
+        axi_last_addr <= axi_awaddr;
+      end
     end
   end
 

From e46990e508ba7e3befa2b7f32f341987b2b1e7b0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 11:13:04 +0300
Subject: [PATCH 320/972] axi_dacfifo: Cosmetic changes

Rename a few registers and fix indentation.
---
 library/axi_dacfifo/axi_dacfifo.v     |  2 --
 library/axi_dacfifo/axi_dacfifo_dac.v |  1 +
 library/axi_dacfifo/axi_dacfifo_rd.v  | 46 +++++++++++++--------------
 library/axi_dacfifo/axi_dacfifo_wr.v  | 12 +++----
 4 files changed, 30 insertions(+), 31 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index e1af682ce..1b5b55bfa 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -201,10 +201,8 @@ module axi_dacfifo (
   wire                                dac_rd_valid_s;
   wire    [31:0]                      axi_last_addr_s;
   wire    [31:0]                      dma_last_addr_s;
-
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
   wire                                dma_ready_s;
-
   wire                                dma_valid_bp_s;
   wire    [(AXI_DATA_WIDTH-1):0]      dma_data_bp_s;
   wire                                dma_ready_bp_s;
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index d077b81cc..7c21f2bd1 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -71,6 +71,7 @@ module axi_dacfifo_dac (
                                                      (DAC_ADDRESS_WIDTH - 3);
 
   // BUF_THRESHOLD_LO will make sure that there are always at least two burst in the memmory
+
   localparam  AXI_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1);
   localparam  AXI_BUF_THRESHOLD_HI = {(AXI_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1);
   localparam  DAC_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1) * MEM_RATIO;
diff --git a/library/axi_dacfifo/axi_dacfifo_rd.v b/library/axi_dacfifo/axi_dacfifo_rd.v
index aef01ac36..263e2d845 100644
--- a/library/axi_dacfifo/axi_dacfifo_rd.v
+++ b/library/axi_dacfifo/axi_dacfifo_rd.v
@@ -92,28 +92,28 @@ module axi_dacfifo_rd (
   // xfer last for read/write synchronization
 
   input                           axi_xfer_req;
-  input   [ 31:0]                 axi_last_raddr;
+  input   [31:0]                 axi_last_raddr;
 
   // axi interface
 
   input                           axi_clk;
   input                           axi_resetn;
   output                          axi_arvalid;
-  output  [  3:0]                 axi_arid;
-  output  [  1:0]                 axi_arburst;
+  output  [ 3:0]                  axi_arid;
+  output  [ 1:0]                  axi_arburst;
   output                          axi_arlock;
-  output  [  3:0]                 axi_arcache;
-  output  [  2:0]                 axi_arprot;
-  output  [  3:0]                 axi_arqos;
-  output  [  3:0]                 axi_aruser;
-  output  [  7:0]                 axi_arlen;
-  output  [  2:0]                 axi_arsize;
-  output  [ 31:0]                 axi_araddr;
+  output  [ 3:0]                  axi_arcache;
+  output  [ 2:0]                  axi_arprot;
+  output  [ 3:0]                  axi_arqos;
+  output  [ 3:0]                  axi_aruser;
+  output  [ 7:0]                  axi_arlen;
+  output  [ 2:0]                  axi_arsize;
+  output  [31:0]                  axi_araddr;
   input                           axi_arready;
   input                           axi_rvalid;
-  input   [  3:0]                 axi_rid;
-  input   [  3:0]                 axi_ruser;
-  input   [  1:0]                 axi_rresp;
+  input   [ 3:0]                  axi_rid;
+  input   [ 3:0]                  axi_ruser;
+  input   [ 1:0]                  axi_rresp;
   input                           axi_rlast;
   input   [(AXI_DATA_WIDTH-1):0]  axi_rdata;
   output                          axi_rready;
@@ -131,8 +131,8 @@ module axi_dacfifo_rd (
   // internal registers
 
   reg     [ 31:0]                 axi_rd_addr_h = 32'b0;
-  reg                             axi_rd = 1'b0;
-  reg                             axi_rd_active = 1'b0;
+  reg                             axi_rnext = 1'b0;
+  reg                             axi_ractive = 1'b0;
   reg                             axi_arvalid = 1'b0;
   reg     [ 31:0]                 axi_araddr = 32'b0;
   reg     [(AXI_DATA_WIDTH-1):0]  axi_ddata = 'b0;
@@ -151,18 +151,18 @@ module axi_dacfifo_rd (
 
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
-      axi_rd <= 1'b0;
-      axi_rd_active <= 1'b0;
+      axi_rnext <= 1'b0;
+      axi_ractive <= 1'b0;
       axi_xfer_req_m <= 2'b0;
     end else begin
-      if (axi_rd_active == 1'b1) begin
-        axi_rd <= 1'b0;
+      if (axi_ractive == 1'b1) begin
+        axi_rnext <= 1'b0;
         if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
-          axi_rd_active <= 1'b0;
+          axi_ractive <= 1'b0;
         end
       end else if ((axi_ready_s == 1'b1)) begin
-        axi_rd <= axi_xfer_req;
-        axi_rd_active <= axi_xfer_req;
+        axi_rnext <= axi_xfer_req;
+        axi_ractive <= axi_xfer_req;
       end
     axi_xfer_req_m <= {axi_xfer_req_m[0], axi_xfer_req};
     end
@@ -193,7 +193,7 @@ module axi_dacfifo_rd (
           axi_arvalid <= 1'b0;
         end
       end else begin
-        if (axi_rd == 1'b1) begin
+        if (axi_rnext == 1'b1) begin
           axi_arvalid <= 1'b1;
         end
       end
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index c3170b6e9..43a71c1b6 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -102,11 +102,11 @@ module axi_dacfifo_wr (
   // for the syncronization buffer
 
   localparam      MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;  // Max supported MEM_RATIO is 16
-  localparam      AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH :
-                                       (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) :
-                                       (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) :
-                                       (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) :
-                                                          (DMA_MEM_ADDRESS_WIDTH - 4);
+  localparam      AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ?  DMA_MEM_ADDRESS_WIDTH :
+                                          (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) :
+                                          (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) :
+                                          (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) :
+                                                             (DMA_MEM_ADDRESS_WIDTH - 4);
 
   // for the AXI interface
 
@@ -195,7 +195,7 @@ module axi_dacfifo_wr (
 
   reg                                       axi_reset = 1'b0;
   reg                                       axi_xfer_out = 1'b0;
-  reg     [31:0]                            axi_last_addr = 'b0;
+  reg     [31:0]                            axi_last_addr = 32'b0;
   reg                                       axi_awvalid = 1'b0;
   reg     [31:0]                            axi_awaddr = 32'b0;
   reg                                       axi_xfer_init = 1'b0;

From b9a5bb3549b62f40438a75a5ff0770e11e340642 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 11:27:06 +0300
Subject: [PATCH 321/972] axi_dacfifo: Optimize the AXI read logic

Save the valid AXI beats number of the last AXI transaction, and the valid
DMA beats number of the last AXI beat, so the read back logic can use this
data and prevent to feel up the CDC memory with invalid samples. Also in
this way the end of the read back cycle get a more robust control: no more
duplicated samples at the end of the buffer.
---
 library/axi_dacfifo/axi_dacfifo.v     | 16 +++--
 library/axi_dacfifo/axi_dacfifo_dac.v | 93 ++++++++++++++++++---------
 library/axi_dacfifo/axi_dacfifo_rd.v  | 43 +++++++++----
 library/axi_dacfifo/axi_dacfifo_wr.v  | 63 +++++++++++-------
 4 files changed, 145 insertions(+), 70 deletions(-)

diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index 1b5b55bfa..496360775 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -200,7 +200,9 @@ module axi_dacfifo (
   wire                                dac_rd_ready_s;
   wire                                dac_rd_valid_s;
   wire    [31:0]                      axi_last_addr_s;
-  wire    [31:0]                      dma_last_addr_s;
+  wire    [ 3:0]                      axi_last_beats_s;
+  wire                                axi_dlast_s;
+  wire    [ 3:0]                      dma_last_beats_s;
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
   wire                                dma_ready_s;
   wire                                dma_valid_bp_s;
@@ -221,8 +223,9 @@ module axi_dacfifo (
     .dma_valid (dma_valid),
     .dma_xfer_req (dma_xfer_req),
     .dma_xfer_last (dma_xfer_last),
+    .dma_last_beats (dma_last_beats_s),
     .axi_last_addr (axi_last_addr_s),
-    .dma_last_addr (dma_last_addr_s),
+    .axi_last_beats (axi_last_beats_s),
     .axi_xfer_out (axi_xfer_req_s),
     .axi_clk (axi_clk),
     .axi_resetn (axi_resetn),
@@ -257,8 +260,9 @@ module axi_dacfifo (
     .AXI_LENGTH (AXI_LENGTH),
     .AXI_ADDRESS (AXI_ADDRESS)
   ) i_rd (
-    .axi_last_raddr (axi_last_addr_s),
     .axi_xfer_req (axi_xfer_req_s),
+    .axi_last_raddr (axi_last_addr_s),
+    .axi_last_beats (axi_last_beats_s),
     .axi_clk (axi_clk),
     .axi_resetn (axi_resetn),
     .axi_arvalid (axi_arvalid),
@@ -283,7 +287,8 @@ module axi_dacfifo (
     .axi_rerror (axi_rerror),
     .axi_dvalid (axi_rd_valid_s),
     .axi_ddata (axi_rd_data_s),
-    .axi_dready (axi_rd_ready_s));
+    .axi_dready (axi_rd_ready_s),
+    .axi_dlast (axi_dlast_s));
 
   axi_dacfifo_dac #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@@ -294,8 +299,9 @@ module axi_dacfifo (
     .axi_dvalid (dac_rd_valid_s),
     .axi_ddata (dac_rd_data_s),
     .axi_dready (axi_rd_ready_s),
+    .axi_dlast (axi_dlast_s),
     .axi_xfer_req (axi_xfer_req_s),
-    .dma_last_addr (dma_last_addr_s),
+    .dma_last_beats (dma_last_beats_s),
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid),
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v
index 7c21f2bd1..2ef272ab3 100644
--- a/library/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/axi_dacfifo/axi_dacfifo_dac.v
@@ -45,9 +45,10 @@ module axi_dacfifo_dac (
   axi_dvalid,
   axi_ddata,
   axi_dready,
+  axi_dlast,
   axi_xfer_req,
 
-  dma_last_addr,
+  dma_last_beats,
 
   dac_clk,
   dac_rst,
@@ -84,9 +85,10 @@ module axi_dacfifo_dac (
   input                               axi_dvalid;
   input   [(AXI_DATA_WIDTH-1):0]      axi_ddata;
   output                              axi_dready;
+  input                               axi_dlast;
   input                               axi_xfer_req;
 
-  input   [31:0]                      dma_last_addr;
+  input   [ 3:0]                      dma_last_beats;
 
   // dac read
 
@@ -100,7 +102,9 @@ module axi_dacfifo_dac (
   // internal registers
 
   reg     [(AXI_ADDRESS_WIDTH-1):0]   axi_mem_waddr = 'd0;
+  reg     [(AXI_ADDRESS_WIDTH-1):0]   axi_mem_laddr = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_waddr_g = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_laddr_g = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr_m1 = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_raddr_m2 = 'd0;
@@ -108,11 +112,13 @@ module axi_dacfifo_dac (
   reg                                 axi_dready = 'd0;
 
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_raddr = 'd0;
-  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_raddr_next = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_raddr_g = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr_m1 = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr_m2 = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_laddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_laddr_m1 = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_laddr_m2 = 'd0;
   reg     [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_addr_diff = 'd0;
   reg                                 dac_mem_init = 1'b0;
   reg                                 dac_mem_init_d = 1'b0;
@@ -121,24 +127,26 @@ module axi_dacfifo_dac (
   reg     [ 2:0]                      dac_xfer_req_m = 3'b0;
   reg                                 dac_xfer_init = 1'b0;
 
-  reg     [31:0]                      dac_raddr_cnt = 32'b0;
-  reg     [31:0]                      dac_last_raddr = 32'b0;
-  reg     [31:0]                      dac_last_raddr_m = 32'b0;
-  reg                                 dac_almost_full = 1'b0;
-  reg                                 dac_almost_empty = 1'b0;
+  reg     [ 3:0]                      dac_last_beats = 4'b0;
+  reg     [ 3:0]                      dac_last_beats_m = 4'b0;
   reg                                 dac_dunf = 1'b0;
+  reg     [ 3:0]                      dac_beat_cnt = 4'b0;
+  reg                                 dac_dlast = 1'b0;
+  reg                                 dac_dlast_m1 = 1'b0;
+  reg                                 dac_dlast_m2 = 1'b0;
+  reg                                 dac_dlast_inmem = 1'b0;
 
   // internal signals
 
   wire    [AXI_ADDRESS_WIDTH:0]       axi_mem_addr_diff_s;
   wire    [(AXI_ADDRESS_WIDTH-1):0]   axi_mem_raddr_s;
   wire    [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_waddr_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_laddr_s;
 
   wire    [DAC_ADDRESS_WIDTH:0]       dac_mem_addr_diff_s;
-  wire    [DAC_ADDRESS_WIDTH:0]       dac_mem_raddr_diff_s;
-  wire    [(DAC_ADDRESS_WIDTH-1):0]   dac_mem_waddr_s;
   wire                                dac_mem_valid_s;
   wire                                dac_xfer_init_s;
+  wire                                dac_last_axi_beats_s;
 
   // binary to grey conversion
 
@@ -186,11 +194,14 @@ module axi_dacfifo_dac (
     if (axi_xfer_req == 1'b0) begin
       axi_mem_waddr <= 'd0;
       axi_mem_waddr_g <= 'd0;
+      axi_mem_laddr <= {AXI_ADDRESS_WIDTH{1'b1}};
     end else begin
       if (axi_dvalid == 1'b1) begin
         axi_mem_waddr <= axi_mem_waddr + 1'b1;
+        axi_mem_laddr <= (axi_dlast == 1'b1) ? axi_mem_waddr : axi_mem_laddr;
       end
       axi_mem_waddr_g <= b2g(axi_mem_waddr_s);
+      axi_mem_laddr_g <= b2g(axi_mem_laddr_s);
     end
   end
 
@@ -204,6 +215,10 @@ module axi_dacfifo_dac (
                            (MEM_RATIO == 2) ? {axi_mem_waddr, 1'b0} :
                            (MEM_RATIO == 4) ? {axi_mem_waddr, 2'b0} :
                                               {axi_mem_waddr, 3'b0};
+   assign axi_mem_laddr_s = (MEM_RATIO == 1) ? axi_mem_laddr :
+                            (MEM_RATIO == 2) ? {axi_mem_laddr, 1'b0} :
+                            (MEM_RATIO == 4) ? {axi_mem_laddr, 2'b0} :
+                                               {axi_mem_laddr, 3'b0};
 
   // incomming data flow control
 
@@ -268,42 +283,63 @@ module axi_dacfifo_dac (
       dac_mem_waddr <= 'b0;
       dac_mem_waddr_m1 <= 'b0;
       dac_mem_waddr_m2 <= 'b0;
+      dac_mem_laddr <= 'b0;
+      dac_mem_laddr_m1 <= 'b0;
+      dac_mem_laddr_m2 <= 'b0;
+      dac_dlast <= 1'b0;
+      dac_dlast_m1 <= 1'b0;
+      dac_dlast_m2 <= 1'b0;
     end else begin
       dac_mem_waddr_m1 <= axi_mem_waddr_g;
       dac_mem_waddr_m2 <= dac_mem_waddr_m1;
       dac_mem_waddr <= g2b(dac_mem_waddr_m2);
+      dac_mem_laddr_m1 <= axi_mem_laddr_g;
+      dac_mem_laddr_m2 <= dac_mem_laddr_m1;
+      dac_mem_laddr <= g2b(dac_mem_laddr_m2);
+      dac_dlast_m1 <= axi_dlast;
+      dac_dlast_m2 <= dac_dlast_m1;
+      dac_dlast <= dac_dlast_m2;
     end
   end
 
   assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr} - dac_mem_raddr;
-  assign dac_mem_raddr_diff_s = {1'b1, dac_mem_raddr_next} - dac_mem_raddr;
   assign dac_mem_valid_s = (dac_mem_enable) ? dac_valid : 1'b0;
 
-  // CDC for the dma_last_addr
+  // CDC for the dma_last_beats
 
   always @(posedge dac_clk) begin
     if (dac_rst == 1'b1) begin
-      dac_last_raddr <= 32'b0;
-      dac_last_raddr_m <= 32'b0;
+      dac_last_beats <= 32'b0;
+      dac_last_beats_m <= 32'b0;
     end else begin
-      dac_last_raddr_m <= dma_last_addr;
-      dac_last_raddr <= dac_last_raddr_m;
+      dac_last_beats_m <= dma_last_beats;
+      dac_last_beats <= dac_last_beats_m;
     end
   end
 
+  // If the MEM_RATIO is grater than one, it can happen that not all the DAC beats from
+  // an AXI beat are valid. In this case the invalid data is dropped.
+  // The axi_dlast indicates the last AXI beat. The valid number of DAC beats on the last AXI beat
+  // commes from the AXI write module. (axi_dacfifo_wr.v)
+
+  assign dac_last_axi_beats_s = ((dac_dlast_inmem == 1'b1) && (dac_mem_raddr >= dac_mem_laddr) && (dac_mem_raddr < dac_mem_laddr + MEM_RATIO)) ? 1'b1 : 1'b0;
+
   always @(posedge dac_clk) begin
     if (dac_xfer_out == 1'b0) begin
       dac_mem_raddr <= 'd0;
-      dac_mem_raddr_next <= DAC_ARINCR;
-      dac_mem_raddr_g <= 'd0;
-      dac_mem_addr_diff <= 'd0;
+      dac_beat_cnt <= 'd0;
+      dac_dlast_inmem <= 1'b0;
     end else begin
-      dac_mem_addr_diff <= dac_mem_addr_diff_s[DAC_ADDRESS_WIDTH-1:0];
-      if (dac_mem_valid_s == 1'b1) begin
-        dac_raddr_cnt <= (dac_raddr_cnt == dac_last_raddr) ? 32'b0 : dac_raddr_cnt + 1;
-        dac_mem_raddr <= (dac_raddr_cnt == dac_last_raddr) ? dac_mem_raddr_next : dac_mem_raddr + 1'b1;
+      if (dac_dlast == 1'b1) begin
+        dac_dlast_inmem <= 1'b1;
+      end else if (dac_mem_raddr == dac_mem_laddr + MEM_RATIO) begin
+        dac_dlast_inmem <= 1'b0;
+      end
+      if (dac_mem_valid_s == 1'b1) begin
+        dac_beat_cnt <= ((dac_beat_cnt >= MEM_RATIO-1) ||
+                         ((dac_last_beats > 1'b1) && (dac_last_axi_beats_s > 1'b0) && (dac_beat_cnt == dac_last_beats-1))) ? 0 : dac_beat_cnt + 1;
+        dac_mem_raddr <= ((dac_last_axi_beats_s) && (dac_beat_cnt == dac_last_beats-1)) ? (dac_mem_laddr + MEM_RATIO) : dac_mem_raddr + 1'b1;
       end
-      dac_mem_raddr_next <= (dac_mem_raddr_diff_s[DAC_ADDRESS_WIDTH-1:0] <= 1) ? dac_mem_raddr_next + DAC_ARINCR : dac_mem_raddr_next;
       dac_mem_raddr_g <= b2g(dac_mem_raddr);
     end
   end
@@ -312,15 +348,10 @@ module axi_dacfifo_dac (
 
   always @(posedge dac_clk) begin
     if(dac_xfer_out == 1'b0) begin
-      dac_almost_full <= 1'b0;
-      dac_almost_empty <= 1'b0;
+      dac_mem_addr_diff <= 'b0;
       dac_dunf <= 1'b0;
     end else begin
-      if (dac_mem_addr_diff < DAC_BUF_THRESHOLD_LO) begin
-        dac_almost_empty <= 1'b1;
-      end else begin
-        dac_almost_empty <= 1'b0;
-      end
+      dac_mem_addr_diff <= dac_mem_addr_diff_s[DAC_ADDRESS_WIDTH-1:0];
       dac_dunf <= (dac_mem_addr_diff == 1'b0) ? 1'b1 : 1'b0;
     end
   end
diff --git a/library/axi_dacfifo/axi_dacfifo_rd.v b/library/axi_dacfifo/axi_dacfifo_rd.v
index 263e2d845..3e93a6ee6 100644
--- a/library/axi_dacfifo/axi_dacfifo_rd.v
+++ b/library/axi_dacfifo/axi_dacfifo_rd.v
@@ -45,6 +45,7 @@ module axi_dacfifo_rd (
 
   axi_xfer_req,
   axi_last_raddr,
+  axi_last_beats,
 
   // axi read address and read data channels
 
@@ -78,7 +79,8 @@ module axi_dacfifo_rd (
 
   axi_dvalid,
   axi_ddata,
-  axi_dready);
+  axi_dready,
+  axi_dlast);
 
   // parameters
 
@@ -93,6 +95,7 @@ module axi_dacfifo_rd (
 
   input                           axi_xfer_req;
   input   [31:0]                 axi_last_raddr;
+  input   [ 3:0]                 axi_last_beats;
 
   // axi interface
 
@@ -127,25 +130,30 @@ module axi_dacfifo_rd (
   output                          axi_dvalid;
   output  [(AXI_DATA_WIDTH-1):0]  axi_ddata;
   input                           axi_dready;
+  output                          axi_dlast;
 
   // internal registers
 
-  reg     [ 31:0]                 axi_rd_addr_h = 32'b0;
   reg                             axi_rnext = 1'b0;
   reg                             axi_ractive = 1'b0;
   reg                             axi_arvalid = 1'b0;
   reg     [ 31:0]                 axi_araddr = 32'b0;
+  reg     [ 31:0]                 axi_araddr_prev = 32'b0;
   reg     [(AXI_DATA_WIDTH-1):0]  axi_ddata = 'b0;
   reg                             axi_dvalid = 1'b0;
+  reg                             axi_dlast = 1'b0;
   reg                             axi_rready = 1'b0;
   reg                             axi_rerror = 1'b0;
   reg     [ 1:0]                  axi_xfer_req_m = 2'b0;
+  reg     [ 4:0]                  axi_last_beats_cntr = 16'b0;
 
   // internal signals
 
   wire                            axi_ready_s;
   wire                            axi_xfer_req_init;
   wire                            axi_dvalid_s;
+  wire                            axi_dlast_s;
+  wire    [ 4:0]                  axi_last_beats_s;
 
   assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
 
@@ -170,6 +178,16 @@ module axi_dacfifo_rd (
 
   assign axi_xfer_req_init = axi_xfer_req_m[0] & ~axi_xfer_req_m[1];
 
+  always @(posedge axi_clk) begin
+    if ((axi_resetn == 1'b0) || (axi_xfer_req == 1'b0)) begin
+      axi_last_beats_cntr <= 0;
+    end else begin
+      if ((axi_rready == 1'b1) && (axi_rvalid == 1'b1)) begin
+        axi_last_beats_cntr <= (axi_rlast == 1'b1) ? 0 : axi_last_beats_cntr +  1;
+      end
+    end
+  end
+
   // address channel
 
   assign axi_arid = 4'b0000;
@@ -185,8 +203,8 @@ module axi_dacfifo_rd (
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
       axi_arvalid <= 'd0;
-      axi_araddr <= 'd0;
-      axi_rd_addr_h <= 'd0;
+      axi_araddr <= AXI_ADDRESS;
+      axi_araddr_prev <= AXI_ADDRESS;
     end else begin
       if (axi_arvalid == 1'b1) begin
         if (axi_arready == 1'b1) begin
@@ -197,20 +215,20 @@ module axi_dacfifo_rd (
           axi_arvalid <= 1'b1;
         end
       end
-      if ((axi_xfer_req_init == 1'b1)) begin
-        axi_araddr <= AXI_ADDRESS;
-        axi_rd_addr_h <= axi_last_raddr;
-      end else if ((axi_xfer_req == 1'b1) &&
-                   (axi_arvalid == 1'b1) &&
-                   (axi_arready == 1'b1)) begin
-        axi_araddr <= (axi_araddr >= axi_rd_addr_h) ? AXI_ADDRESS : axi_araddr + AXI_AWINCR;
+      if ((axi_xfer_req == 1'b1) &&
+          (axi_arvalid == 1'b1) &&
+          (axi_arready == 1'b1)) begin
+        axi_araddr <= (axi_araddr >= axi_last_raddr) ? AXI_ADDRESS : axi_araddr + AXI_AWINCR;
+        axi_araddr_prev <= axi_araddr;
       end
     end
   end
 
   // read data channel
 
-  assign axi_dvalid_s = axi_rvalid & axi_rready;
+  assign axi_last_beats_s = {1'b0, axi_last_beats} - 1;
+  assign axi_dvalid_s = ((axi_last_beats_cntr > axi_last_beats_s) && (axi_araddr_prev == axi_last_raddr)) ? 0 : axi_rvalid & axi_rready;
+  assign axi_dlast_s = (axi_araddr_prev == axi_last_raddr) ? 1 : 0;
 
   always @(posedge axi_clk) begin
     if (axi_resetn == 1'b0) begin
@@ -220,6 +238,7 @@ module axi_dacfifo_rd (
     end else begin
       axi_ddata <= axi_rdata;
       axi_dvalid <= axi_dvalid_s;
+      axi_dlast <= axi_dlast_s;
       if (axi_xfer_req == 1'b1) begin
         axi_rready <= axi_rvalid;
       end
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v
index 43a71c1b6..e3e4ddb7d 100644
--- a/library/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/axi_dacfifo/axi_dacfifo_wr.v
@@ -52,11 +52,12 @@ module axi_dacfifo_wr (
 
   dma_xfer_req,
   dma_xfer_last,
+  dma_last_beats,
 
   // syncronization for the read side
 
   axi_last_addr,
-  dma_last_addr,
+  axi_last_beats,
   axi_xfer_out,
 
   // axi write address, write data and write response channels
@@ -124,9 +125,10 @@ module axi_dacfifo_wr (
 
   input                                     dma_xfer_req;
   input                                     dma_xfer_last;
+  output  [ 3:0]                            dma_last_beats;
 
   output  [31:0]                            axi_last_addr;
-  output  [31:0]                            dma_last_addr;
+  output  [ 3:0]                            axi_last_beats;
   output                                    axi_xfer_out;
 
   // axi interface
@@ -171,8 +173,8 @@ module axi_dacfifo_wr (
   reg                                       dma_rst_m1 = 1'b0;
   reg                                       dma_rst_m2 = 1'b0;
   reg     [ 2:0]                            dma_mem_last_read_toggle_m = 3'b0;
-  reg     [31:0]                            dma_addr_cnt = 32'b0;
-  reg     [31:0]                            dma_last_addr = 32'b0;
+  reg                                       dma_xfer_req_d = 1'b0;
+  reg     [ 3:0]                            dma_last_beats = 4'b0;
 
   reg     [ 4:0]                            axi_xfer_req_m = 3'b0;
   reg     [ 4:0]                            axi_xfer_last_m = 3'b0;
@@ -196,6 +198,7 @@ module axi_dacfifo_wr (
   reg                                       axi_reset = 1'b0;
   reg                                       axi_xfer_out = 1'b0;
   reg     [31:0]                            axi_last_addr = 32'b0;
+  reg     [ 3:0]                            axi_last_beats = 15'b0;
   reg                                       axi_awvalid = 1'b0;
   reg     [31:0]                            axi_awaddr = 32'b0;
   reg                                       axi_xfer_init = 1'b0;
@@ -210,6 +213,7 @@ module axi_dacfifo_wr (
   wire    [(DMA_MEM_ADDRESS_WIDTH):0]       dma_mem_addr_diff_s;
   wire    [(DMA_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_s;
   wire                                      dma_mem_last_read_s;
+  wire                                      dma_xfer_init;
   wire                                      dma_mem_wea_s;
   wire                                      dma_rst_s;
 
@@ -304,10 +308,21 @@ module axi_dacfifo_wr (
   end
   assign dma_rst_s = dma_rst_m2;
 
-  // Write address generation for the asymmetric memory
+  // DMA beat counter
 
-  // There is no underflow or overflow. All the data movements are controlled by
-  // this module.
+  assign dma_xfer_init = dma_xfer_req & ~dma_xfer_req_d;
+  always @(posedge dma_clk) begin
+    dma_xfer_req_d <= dma_xfer_req;
+    if ((dma_rst_s == 1'b1) || (dma_xfer_init == 1'b1)) begin
+      dma_last_beats <= 4'b0;
+    end else begin
+      if ((dma_ready == 1'b1) && (dma_valid == 1'b1)) begin
+        dma_last_beats <= (dma_last_beats < MEM_RATIO-1) ? dma_last_beats + 1 : 0;
+      end
+    end
+  end
+
+  // Write address generation for the asymmetric memory
 
   assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
   assign dma_mem_raddr_s = (MEM_RATIO == 1) ?  dma_mem_raddr :
@@ -327,6 +342,11 @@ module axi_dacfifo_wr (
       dma_mem_last_read_toggle_m = {dma_mem_last_read_toggle_m[1:0], axi_mem_last_read_toggle};
       if (dma_mem_wea_s == 1'b1) begin
         dma_mem_waddr <= dma_mem_waddr + 8'b1;
+        if (dma_xfer_last == 1'b1) begin
+          if (dma_last_beats != (MEM_RATIO - 1)) begin
+            dma_mem_waddr <= dma_mem_waddr + (MEM_RATIO - dma_last_beats);
+          end
+        end
       end
       if (dma_mem_last_read_s == 1'b1) begin
         dma_mem_waddr <= 'h0;
@@ -357,21 +377,6 @@ module axi_dacfifo_wr (
     end
   end
 
-  // An absolute address counter with DMA's granularity, this address will be
-  // used on read back
-
-  always @(posedge dma_clk) begin
-    if (dma_rst_s == 1'b1) begin
-      dma_addr_cnt <= 32'b0;
-      dma_last_addr <= 32'b0;
-    end else begin
-      if((dma_valid == 1'b1) && (dma_xfer_req == 1'b1)) begin
-        dma_addr_cnt <= (dma_xfer_last == 1'b1) ? 32'b0 : dma_addr_cnt + 1;
-        dma_last_addr <= (dma_xfer_last == 1'b1) ? dma_addr_cnt : dma_last_addr;
-      end
-    end
-  end
-
   // Read address generation for the asymmetric memory
 
   // CDC for the memory write address, xfer_req and xfer_last
@@ -546,4 +551,18 @@ module axi_dacfifo_wr (
     end
   end
 
+  // AXI beat counter
+
+  always @(posedge axi_clk) begin
+    if(axi_resetn == 1'b0) begin
+      axi_last_beats <= 4'b0;
+    end else begin
+      if ((axi_endof_transaction == 1'b1) && (axi_awready == 1'b1) && (axi_awvalid == 1'b1)) begin
+        axi_last_beats <= axi_mem_addr_diff;
+      end else begin
+        axi_last_beats <= axi_last_beats;
+      end
+    end
+  end
+
 endmodule

From 74c220d79eeb9585bd24c471c471b8130878939d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 13:15:44 +0300
Subject: [PATCH 322/972] make: Update Make files

---
 library/axi_ad7616/Makefile                | 16 ++++++++--------
 library/axi_dmac/Makefile                  |  4 ++--
 library/spi_engine/axi_spi_engine/Makefile |  2 +-
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile
index 5b9dfea8c..e0736d1a8 100644
--- a/library/axi_ad7616/Makefile
+++ b/library/axi_ad7616/Makefile
@@ -14,10 +14,10 @@ M_DEPS += axi_ad7616_control.v
 M_DEPS += axi_ad7616_pif.v
 M_DEPS += axi_ad7616_maxis2wrfifo.v
 M_DEPS += axi_ad7616.v
-M_DEPS += ../spi_engine_execution/spi_engine_execution.xpr
-M_DEPS += ../axi_spi_engine/axi_spi_engine.xpr
-M_DEPS += ../spi_engine_offload/spi_engine_offload.xpr
-M_DEPS += ../spi_engine_interconnect/spi_engine_interconnect.xpr
+M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
+M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
+M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
+M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -52,9 +52,9 @@ axi_ad7616.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_ad7616_ip.tcl  >> axi_ad7616_ip.log 2>&1
 
 dep:
-	make -C ../spi_engine_execution
-	make -C ../axi_spi_engine
-	make -C ../spi_engine_offload
-	make -C ../spi_engine_interconnect
+	make -C ../spi_engine/spi_engine_execution/
+	make -C ../spi_engine/axi_spi_engine/
+	make -C ../spi_engine/spi_engine_offload/
+	make -C ../spi_engine/spi_engine_interconnect/
 ####################################################################################
 ####################################################################################
diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile
index 2565a8954..909ea7a81 100644
--- a/library/axi_dmac/Makefile
+++ b/library/axi_dmac/Makefile
@@ -64,7 +64,7 @@ axi_dmac.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_dmac_ip.tcl  >> axi_dmac_ip.log 2>&1
 
 dep:
-	make -C ../util_axis_resize
-	make -C ../util_axis_fifo
+	make -C ../util_axis_resize/
+	make -C ../util_axis_fifo/
 ####################################################################################
 ####################################################################################
diff --git a/library/spi_engine/axi_spi_engine/Makefile b/library/spi_engine/axi_spi_engine/Makefile
index f915b7cf9..fe1a9dc4a 100644
--- a/library/spi_engine/axi_spi_engine/Makefile
+++ b/library/spi_engine/axi_spi_engine/Makefile
@@ -48,6 +48,6 @@ axi_spi_engine.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_spi_engine_ip.tcl  >> axi_spi_engine_ip.log 2>&1
 
 dep:
-	make -C ../../util_axis_fifo
+	make -C ../../util_axis_fifo/
 ####################################################################################
 ####################################################################################

From 634924246ad85bbe19c7424be1939720e465a2f1 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 13:18:18 +0300
Subject: [PATCH 323/972] axi_jesd_xcvr: Delete Makefile

This core is an Altera core only, no need for Makefile.
---
 library/axi_jesd_xcvr/Makefile | 53 ----------------------------------
 1 file changed, 53 deletions(-)
 delete mode 100644 library/axi_jesd_xcvr/Makefile

diff --git a/library/axi_jesd_xcvr/Makefile b/library/axi_jesd_xcvr/Makefile
deleted file mode 100644
index 3cd8bf682..000000000
--- a/library/axi_jesd_xcvr/Makefile
+++ /dev/null
@@ -1,53 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS := axi_jesd_gt_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_gt_common_1.v
-M_DEPS += ../common/ad_gt_channel_1.v
-M_DEPS += ../common/ad_gt_es.v
-M_DEPS += ../common/ad_jesd_align.v
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/up_xfer_cntrl.v
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_drp_cntrl.v
-M_DEPS += ../common/up_gt.v
-M_DEPS += axi_jesd_gt.v
-M_DEPS += axi_jesd_gt_constr.xdc
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += component.xml
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += .Xil
-
-
-
-.PHONY: all clean clean-all
-all: axi_jesd_gt.xpr
-
-
-clean:clean-all
-
-
-clean-all:
-	rm -rf $(M_FLIST)
-
-
-axi_jesd_gt.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
-	$(M_VIVADO) axi_jesd_gt_ip.tcl  >> axi_jesd_gt_ip.log 2>&1
-
-####################################################################################
-####################################################################################

From 8902a31ca6eaff7f701093beabc4a5bba8ea6bef Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 13:24:36 +0300
Subject: [PATCH 324/972] util_dac_unpack: Delete unused IP core

---
 library/util_dac_unpack/Makefile              |  46 ----
 library/util_dac_unpack/util_dac_unpack.v     | 236 ------------------
 .../util_dac_unpack/util_dac_unpack_hw.tcl    |  81 ------
 .../util_dac_unpack/util_dac_unpack_ip.tcl    |  46 ----
 4 files changed, 409 deletions(-)
 delete mode 100644 library/util_dac_unpack/Makefile
 delete mode 100644 library/util_dac_unpack/util_dac_unpack.v
 delete mode 100644 library/util_dac_unpack/util_dac_unpack_hw.tcl
 delete mode 100644 library/util_dac_unpack/util_dac_unpack_ip.tcl

diff --git a/library/util_dac_unpack/Makefile b/library/util_dac_unpack/Makefile
deleted file mode 100644
index 0f55eca36..000000000
--- a/library/util_dac_unpack/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS := util_dac_unpack_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += util_dac_unpack.v
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += component.xml
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.ip_user_files
-M_FLIST += *.srcs
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-
-
-
-.PHONY: all clean clean-all
-all: util_dac_unpack.xpr
-
-
-clean:clean-all
-
-
-clean-all:
-	rm -rf $(M_FLIST)
-
-
-util_dac_unpack.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
-	$(M_VIVADO) util_dac_unpack_ip.tcl  >> util_dac_unpack_ip.log 2>&1
-
-####################################################################################
-####################################################################################
diff --git a/library/util_dac_unpack/util_dac_unpack.v b/library/util_dac_unpack/util_dac_unpack.v
deleted file mode 100644
index bf2edbf3d..000000000
--- a/library/util_dac_unpack/util_dac_unpack.v
+++ /dev/null
@@ -1,236 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2014(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module util_dac_unpack (
-
-  clk,
-
-  dac_enable_00,
-  dac_valid_00,
-  dac_data_00,
-
-  dac_enable_01,
-  dac_valid_01,
-  dac_data_01,
-
-  dac_enable_02,
-  dac_valid_02,
-  dac_data_02,
-
-  dac_enable_03,
-  dac_valid_03,
-  dac_data_03,
-
-  dac_enable_04,
-  dac_valid_04,
-  dac_data_04,
-
-  dac_enable_05,
-  dac_valid_05,
-  dac_data_05,
-
-  dac_enable_06,
-  dac_valid_06,
-  dac_data_06,
-
-  dac_enable_07,
-  dac_valid_07,
-  dac_data_07,
-
-  fifo_valid,
-  dma_rd,
-  dma_data);
-
-  parameter NUM_OF_CHANNELS = 8; // valid values are 4 and 8
-  parameter DATA_WIDTH = 16;
-
-  input                   clk;
-
-  input                    dac_enable_00;
-  input                    dac_valid_00;
-  output  [DATA_WIDTH-1:0] dac_data_00;
-
-  input                    dac_enable_01;
-  input                    dac_valid_01;
-  output  [DATA_WIDTH-1:0] dac_data_01;
-
-  input                    dac_enable_02;
-  input                    dac_valid_02;
-  output  [DATA_WIDTH-1:0] dac_data_02;
-
-  input                    dac_enable_03;
-  input                    dac_valid_03;
-  output  [DATA_WIDTH-1:0] dac_data_03;
-
-  input                    dac_enable_04;
-  input                    dac_valid_04;
-  output  [DATA_WIDTH-1:0] dac_data_04;
-
-  input                    dac_enable_05;
-  input                    dac_valid_05;
-  output  [DATA_WIDTH-1:0] dac_data_05;
-
-  input                    dac_enable_06;
-  input                    dac_valid_06;
-  output  [DATA_WIDTH-1:0] dac_data_06;
-
-  input                    dac_enable_07;
-  input                    dac_valid_07;
-  output  [DATA_WIDTH-1:0] dac_data_07;
-
-  input                             fifo_valid;
-  output                            dma_rd;
-  input   [NUM_OF_CHANNELS*DATA_WIDTH-1:0] dma_data;
-
-
-  localparam DMA_DATA_WIDTH = NUM_OF_CHANNELS*DATA_WIDTH;
-
-  wire [NUM_OF_CHANNELS-1:0]            dac_enable;
-  wire [NUM_OF_CHANNELS-1:0]            dac_valid;
-
-  wire [DATA_WIDTH-1:0]          data_array[0:NUM_OF_CHANNELS-1];
-
-  wire [$clog2(NUM_OF_CHANNELS)-1:0]    offset [0:NUM_OF_CHANNELS-1];
-  wire                           dac_chan_valid;
-
-  reg [DATA_WIDTH*NUM_OF_CHANNELS-1:0]  dac_data = 'h00;
-  reg [DMA_DATA_WIDTH-1:0]            buffer = 'h00;
-  reg                            dma_rd = 1'b0;
-  reg [$clog2(NUM_OF_CHANNELS)-1:0]     rd_counter = 'h00;
-  reg [$clog2(NUM_OF_CHANNELS)-1:0]     req_counter = 'h00;
-  reg [NUM_OF_CHANNELS-1:0]             dac_enable_d1 = 'h00;
-
-  assign dac_enable[0] = dac_enable_00;
-  assign dac_enable[1] = dac_enable_01;
-  assign dac_enable[2] = dac_enable_02;
-  assign dac_enable[3] = dac_enable_03;
-  assign dac_valid[0] = dac_valid_00;
-  assign dac_valid[1] = dac_valid_01;
-  assign dac_valid[2] = dac_valid_02;
-  assign dac_valid[3] = dac_valid_03;
-  assign dac_data_00 = dac_data[DATA_WIDTH*1-1:DATA_WIDTH*0];
-  assign dac_data_01 = dac_data[DATA_WIDTH*2-1:DATA_WIDTH*1];
-  assign dac_data_02 = dac_data[DATA_WIDTH*3-1:DATA_WIDTH*2];
-  assign dac_data_03 = dac_data[DATA_WIDTH*4-1:DATA_WIDTH*3];
-
-  generate
-    if (NUM_OF_CHANNELS >= 8) begin
-      assign dac_enable[4] = dac_enable_04;
-      assign dac_enable[5] = dac_enable_05;
-      assign dac_enable[6] = dac_enable_06;
-      assign dac_enable[7] = dac_enable_07;
-      assign dac_valid[4] = dac_valid_04;
-      assign dac_valid[5] = dac_valid_05;
-      assign dac_valid[6] = dac_valid_06;
-      assign dac_valid[7] = dac_valid_07;
-      assign dac_data_04 = dac_data[DATA_WIDTH*5-1:DATA_WIDTH*4];
-      assign dac_data_05 = dac_data[DATA_WIDTH*6-1:DATA_WIDTH*5];
-      assign dac_data_06 = dac_data[DATA_WIDTH*7-1:DATA_WIDTH*6];
-      assign dac_data_07 = dac_data[DATA_WIDTH*8-1:DATA_WIDTH*7];
-    end else begin
-      assign dac_data_04 = 'h0;
-      assign dac_data_05 = 'h0;
-      assign dac_data_06 = 'h0;
-      assign dac_data_07 = 'h0;
-    end
-  endgenerate
-
-  function integer enable_reduce;
-    input n;
-    integer n;
-    integer i;
-    begin
-      enable_reduce = 0;
-      for (i = 0; i < n; i = i + 1)
-        enable_reduce = enable_reduce + dac_enable[i];
-    end
-  endfunction
-
-  assign dac_chan_valid = |dac_valid;
-
-  always @(posedge clk) begin
-    if (fifo_valid == 1'b1) begin
-      buffer <= dma_data;
-      rd_counter <= 'h0;
-    end else if (dac_chan_valid == 1'b1) begin
-      rd_counter <= rd_counter + enable_reduce(NUM_OF_CHANNELS);
-    end
-  end
-
-  always @(posedge clk) begin
-     dma_rd <= 1'b0;
-     if (dac_enable != dac_enable_d1) begin
-       req_counter <= 'h00;
-     end else if (dac_chan_valid == 1'b1) begin
-       req_counter <= req_counter + enable_reduce(NUM_OF_CHANNELS);
-       if (req_counter == 'h00) begin
-         dma_rd <= 1'b1;
-       end
-     end
-     dac_enable_d1 <= dac_enable;
-  end
-
-  generate
-    genvar i;
-    for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin : gen_data_array
-      assign data_array[i] = buffer[DATA_WIDTH+i*DATA_WIDTH-1:i*DATA_WIDTH];
-    end
-  endgenerate
-
-  generate
-    genvar j;
-    for (j = 0; j < NUM_OF_CHANNELS; j = j + 1) begin : gen_dac_data
-      assign offset[j] = rd_counter + enable_reduce(j);
-      always @(posedge clk) begin
-        if (dac_chan_valid) begin
-          if (dac_enable[j])
-            dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= data_array[offset[j]];
-          else
-            dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= 'h0000;
-        end
-      end
-    end
-  endgenerate
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/util_dac_unpack/util_dac_unpack_hw.tcl b/library/util_dac_unpack/util_dac_unpack_hw.tcl
deleted file mode 100644
index 549860d43..000000000
--- a/library/util_dac_unpack/util_dac_unpack_hw.tcl
+++ /dev/null
@@ -1,81 +0,0 @@
-
-package require -exact qsys 13.0
-source ../scripts/adi_env.tcl
-
-set_module_property NAME util_dac_unpack
-set_module_property DESCRIPTION "Util DAC data unpacker"
-set_module_property VERSION 1.0
-set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME util_dac_unpack
-set_module_property ELABORATION_CALLBACK util_dac_unpack_elaborate
-
-# files
-
-add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
-set_fileset_property quartus_synth TOP_LEVEL util_dac_unpack
-add_fileset_file util_dac_unpack.v   VERILOG PATH util_dac_unpack.v
-
-add_parameter NUM_OF_CHANNELS INTEGER 0
-set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8
-set_parameter_property NUM_OF_CHANNELS ALLOWED_RANGES {4 8}
-set_parameter_property NUM_OF_CHANNELS DESCRIPTION "Valid values are 4 and 8"
-set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS
-set_parameter_property NUM_OF_CHANNELS TYPE INTEGER
-set_parameter_property NUM_OF_CHANNELS UNITS None
-set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
-
-add_parameter DATA_WIDTH INTEGER 0
-set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
-set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
-set_parameter_property DATA_WIDTH TYPE INTEGER
-set_parameter_property DATA_WIDTH UNITS None
-set_parameter_property DATA_WIDTH HDL_PARAMETER true
-
-add_interface data_clock clock end
-add_interface_port data_clock clk clk Input 1
-
-proc util_dac_unpack_elaborate {} {
-  set DW [ get_parameter_value DATA_WIDTH ]
-  set CHAN [ get_parameter_value NUM_OF_CHANNELS ]
-
-  add_interface channels_data conduit end
-  set_interface_property channels_data associatedClock data_clock
-  add_interface_port channels_data dac_enable_00 dac_enable_00 Input 1
-  add_interface_port channels_data dac_valid_00 dac_valid_00 Input 1
-  add_interface_port channels_data dac_data_00 dac_data_00 Output DATA_WIDTH
-
-  add_interface_port channels_data dac_enable_01 dac_enable_01 Input 1
-  add_interface_port channels_data dac_valid_01  dac_valid_01 Input 1
-  add_interface_port channels_data dac_data_01   dac_data_01 Output DATA_WIDTH
-
-  add_interface_port channels_data dac_enable_02 dac_enable_02 Input 1
-  add_interface_port channels_data dac_valid_02 dac_valid_02 Input 1
-  add_interface_port channels_data dac_data_02 dac_data_02 Output DATA_WIDTH
-
-  add_interface_port channels_data dac_enable_03 dac_enable_03 Input 1
-  add_interface_port channels_data dac_valid_03 dac_valid_03 Input 1
-  add_interface_port channels_data dac_data_03 dac_data_03 Output DATA_WIDTH
-
-  if {$CHAN == 8} {
-    add_interface_port channels_data dac_enable_04 dac_enable_04 Input 1
-    add_interface_port channels_data dac_valid_04 dac_valid_04 Input 1
-    add_interface_port channels_data dac_data_04 dac_data_04 Output DATA_WIDTH
-
-    add_interface_port channels_data dac_enable_05 dac_enable_05 Input 1
-    add_interface_port channels_data dac_valid_05 dac_valid_05 Input 1
-    add_interface_port channels_data dac_data_05 dac_data_05 Output DATA_WIDTH
-
-    add_interface_port channels_data dac_enable_06 dac_enable_06 Input 1
-    add_interface_port channels_data dac_valid_06 dac_valid_06 Input 1
-    add_interface_port channels_data dac_data_06 dac_data_06 Output DATA_WIDTH
-
-    add_interface_port channels_data dac_enable_07 dac_enable_07 Input 1
-    add_interface_port channels_data dac_valid_07 dac_valid_07 Input 1
-    add_interface_port channels_data dac_data_07 dac_data_07 Output DATA_WIDTH
-  }
-
-  add_interface_port channels_data fifo_valid fifo_valid Input 1
-  add_interface_port channels_data dma_rd dma_rd Output 1
-  add_interface_port channels_data dma_data dma_data Input [expr {$DW * $CHAN}]
-}
-
diff --git a/library/util_dac_unpack/util_dac_unpack_ip.tcl b/library/util_dac_unpack/util_dac_unpack_ip.tcl
deleted file mode 100644
index d5ada0d9b..000000000
--- a/library/util_dac_unpack/util_dac_unpack_ip.tcl
+++ /dev/null
@@ -1,46 +0,0 @@
-# ip
-
-source ../scripts/adi_env.tcl
-source $ad_hdl_dir/library/scripts/adi_ip.tcl
-
-adi_ip_create util_dac_unpack
-adi_ip_files util_dac_unpack [list \
-  "util_dac_unpack.v" ]
-
-adi_ip_properties_lite util_dac_unpack
-
-ipx::remove_bus_interface {s} [ipx::current_core]
-ipx::remove_bus_interface {m} [ipx::current_core]
-ipx::remove_bus_interface {fifo} [ipx::current_core]
-ipx::remove_bus_interface {signal_clock} [ipx::current_core]
-
-ipx::remove_memory_map {m} [ipx::current_core]
-ipx::remove_address_space {s} [ipx::current_core]
-ipx::remove_address_space {fifo} [ipx::current_core]
-
-for {set i 0} {$i < 8} {incr i} {
-	foreach port {"dac_enable" "dac_valid" "dac_data"} {
-		set name [format "%s_%.2d" $port $i]
-		set_property ENABLEMENT_DEPENDENCY \
-		"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i)" \
-		[ipx::get_ports $name]
-	}
-	foreach port {"dac_enable" "dac_valid"} {
-		set name [format "%s_%.2d" $port $i]
-		set_property DRIVER_VALUE "0" [ipx::get_ports $name]
-	}
-}
-
-adi_add_bus "fifo_rd" "master" \
-	"analog.com:interface:fifo_rd_rtl:1.0" \
-	"analog.com:interface:fifo_rd:1.0" \
-	{ \
-		{"dma_rd" "EN"} \
-		{"dma_data" "DATA"} \
-		{"fifo_valid" "VALID"} \
-	}
-adi_add_bus_clock "clk" "fifo_rd"
-
-ipx::save_core [ipx::current_core]
-
-

From 46b00aea2dd93cd7aa42887af917efebb7f2dd8f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 13:25:40 +0300
Subject: [PATCH 325/972] util_adc_pack: Delete unused IP core

---
 library/util_adc_pack/Makefile             |  46 --
 library/util_adc_pack/util_adc_pack.v      | 536 ---------------------
 library/util_adc_pack/util_adc_pack_hw.tcl |  87 ----
 library/util_adc_pack/util_adc_pack_ip.tcl |  42 --
 4 files changed, 711 deletions(-)
 delete mode 100644 library/util_adc_pack/Makefile
 delete mode 100644 library/util_adc_pack/util_adc_pack.v
 delete mode 100644 library/util_adc_pack/util_adc_pack_hw.tcl
 delete mode 100644 library/util_adc_pack/util_adc_pack_ip.tcl

diff --git a/library/util_adc_pack/Makefile b/library/util_adc_pack/Makefile
deleted file mode 100644
index b8c7b2cbf..000000000
--- a/library/util_adc_pack/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS := util_adc_pack_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += util_adc_pack.v
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += component.xml
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.ip_user_files
-M_FLIST += *.srcs
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-
-
-
-.PHONY: all clean clean-all
-all: util_adc_pack.xpr
-
-
-clean:clean-all
-
-
-clean-all:
-	rm -rf $(M_FLIST)
-
-
-util_adc_pack.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
-	$(M_VIVADO) util_adc_pack_ip.tcl  >> util_adc_pack_ip.log 2>&1
-
-####################################################################################
-####################################################################################
diff --git a/library/util_adc_pack/util_adc_pack.v b/library/util_adc_pack/util_adc_pack.v
deleted file mode 100644
index 6a7dae0ab..000000000
--- a/library/util_adc_pack/util_adc_pack.v
+++ /dev/null
@@ -1,536 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2014(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module util_adc_pack (
-
-  clk,
-
-  chan_enable_0,
-  chan_valid_0,
-  chan_data_0,
-
-  chan_enable_1,
-  chan_valid_1,
-  chan_data_1,
-
-  chan_enable_2,
-  chan_valid_2,
-  chan_data_2,
-
-  chan_enable_3,
-  chan_valid_3,
-  chan_data_3,
-
-  chan_enable_4,
-  chan_valid_4,
-  chan_data_4,
-
-  chan_enable_5,
-  chan_valid_5,
-  chan_data_5,
-
-  chan_enable_6,
-  chan_valid_6,
-  chan_data_6,
-
-  chan_enable_7,
-  chan_valid_7,
-  chan_data_7,
-
-  ddata,
-  dvalid,
-  dsync
-
-  );
-
-  parameter NUM_OF_CHANNELS = 8; // valid values are 4 and 8
-  parameter DATA_WIDTH = 16; // valid values are 16 and 32
-  // common clock
-
-  input           clk;
-
-  input                       chan_enable_0;
-  input                       chan_valid_0;
-  input   [(DATA_WIDTH-1):0]  chan_data_0;
-
-  input                       chan_enable_1;
-  input                       chan_valid_1;
-  input   [(DATA_WIDTH-1):0]  chan_data_1;
-
-  input                       chan_enable_2;
-  input                       chan_valid_2;
-  input   [(DATA_WIDTH-1):0]  chan_data_2;
-
-  input                       chan_enable_3;
-  input                       chan_valid_3;
-  input   [(DATA_WIDTH-1):0]  chan_data_3;
-
-  input                       chan_enable_4;
-  input                       chan_valid_4;
-  input   [(DATA_WIDTH-1):0]  chan_data_4;
-
-  input                       chan_enable_5;
-  input                       chan_valid_5;
-  input   [(DATA_WIDTH-1):0]  chan_data_5;
-
-  input                       chan_enable_6;
-  input                       chan_valid_6;
-  input   [(DATA_WIDTH-1):0]  chan_data_6;
-
-  input                       chan_valid_7;
-  input                       chan_enable_7;
-  input   [(DATA_WIDTH-1):0]  chan_data_7;
-
-  output  [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] ddata;
-  output                              dvalid;
-  output                              dsync;
-
-  reg  [(DATA_WIDTH*NUM_OF_CHANNELS-1):0]    packed_data = 0;
-  reg  [(DATA_WIDTH*NUM_OF_CHANNELS-1):0]    temp_data_0 = 0;
-  reg  [(DATA_WIDTH*NUM_OF_CHANNELS-1):0]    temp_data_1 = 0;
-
-  reg  [3:0]      enable_cnt;
-  reg  [2:0]      enable_cnt_0;
-  reg  [2:0]      enable_cnt_1;
-
-
-  reg  [7:0]      path_enabled = 0;
-  reg  [7:0]      path_enabled_d1 = 0;
-  reg  [6:0]      counter_0 = 0;
-  reg  [7:0]      en1 = 0;
-  reg  [7:0]      en2 = 0;
-  reg  [7:0]      en4 = 0;
-  reg             dvalid = 0;
-
-  reg  [(DATA_WIDTH*NUM_OF_CHANNELS-1):0]  ddata = 0;
-  reg  [(DATA_WIDTH-1):0]           chan_data_0_r;
-  reg  [(DATA_WIDTH-1):0]           chan_data_1_r;
-  reg  [(DATA_WIDTH-1):0]           chan_data_2_r;
-  reg  [(DATA_WIDTH-1):0]           chan_data_3_r;
-  reg  [(DATA_WIDTH-1):0]           chan_data_4_r;
-  reg  [(DATA_WIDTH-1):0]           chan_data_5_r;
-  reg  [(DATA_WIDTH-1):0]           chan_data_6_r;
-  reg  [(DATA_WIDTH-1):0]           chan_data_7_r;
-
-  wire            chan_valid;
-
-  assign dsync        = dvalid;
-  assign chan_valid   = chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ;
-
-  always @(posedge clk)
-  begin
-    enable_cnt   = enable_cnt_0 + enable_cnt_1;
-    enable_cnt_0 = chan_enable_0 + chan_enable_1 + chan_enable_2 + chan_enable_3;
-    if (NUM_OF_CHANNELS == 8)
-    begin
-      enable_cnt_1 = chan_enable_4 + chan_enable_5 + chan_enable_6 + chan_enable_7;
-    end
-    else
-    begin
-      enable_cnt_1 = 0;
-    end
-  end
-
-  always @(posedge clk)
-  begin
-    if(chan_valid == 1'b1)
-    begin
-      chan_data_0_r <= chan_data_0;
-      chan_data_1_r <= chan_data_1;
-      chan_data_2_r <= chan_data_2;
-      chan_data_3_r <= chan_data_3;
-      chan_data_4_r <= chan_data_4;
-      chan_data_5_r <= chan_data_5;
-      chan_data_6_r <= chan_data_6;
-      chan_data_7_r <= chan_data_7;
-    end
-  end
-
-  always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3 )
-  begin
-    casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
-      4'bxxx1: temp_data_0[(DATA_WIDTH-1):0] = chan_data_0_r;
-      4'bxx10: temp_data_0[(DATA_WIDTH-1):0] = chan_data_1_r;
-      4'bx100: temp_data_0[(DATA_WIDTH-1):0] = chan_data_2_r;
-      4'b1000: temp_data_0[(DATA_WIDTH-1):0] = chan_data_3_r;
-      default: temp_data_0 [(DATA_WIDTH-1):0] = 0;
-    endcase
-
-    casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
-      4'bxx11: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_1_r;
-      4'bx110: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r;
-      4'bx101: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r;
-      4'b1001: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
-      4'b1010: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
-      4'b1100: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
-      default: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = 0;
-    endcase
-
-    casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
-      4'bx111: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_2_r;
-      4'b1011: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
-      4'b1101: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
-      4'b1110: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
-      default: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0;
-    endcase
-
-    case ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
-      4'b1111: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_3_r;
-      default: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
-    endcase
-  end
-
-  always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7)
-  begin
-    casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
-      4'bxxx1: temp_data_1[(DATA_WIDTH-1):0] = chan_data_4_r;
-      4'bxx10: temp_data_1[(DATA_WIDTH-1):0] = chan_data_5_r;
-      4'bx100: temp_data_1[(DATA_WIDTH-1):0] = chan_data_6_r;
-      4'b1000: temp_data_1[(DATA_WIDTH-1):0] = chan_data_7_r;
-      default: temp_data_1[(DATA_WIDTH-1):0] = 0;
-    endcase
-
-    casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
-      4'bxx11: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_5_r;
-      4'bx110: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r;
-      4'bx101: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r;
-      4'b1001: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
-      4'b1010: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
-      4'b1100: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
-      default: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = 0;
-    endcase
-
-    casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
-      4'bx111: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_6_r;
-      4'b1011: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
-      4'b1101: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
-      4'b1110: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
-      default: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0;
-    endcase
-
-    case ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
-      4'b1111: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_7_r;
-      default: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
-    endcase
-  end
-
-  always @(enable_cnt)
-  begin
-    case(enable_cnt)
-     4'h1: path_enabled = 8'h01;
-     4'h2: path_enabled = 8'h02;
-     4'h4: path_enabled = 8'h08;
-     4'h8: path_enabled = 8'h80;
-     default: path_enabled = 8'h0;
-    endcase
-  end
-
-  always @(temp_data_0, temp_data_1, enable_cnt_0)
-  begin
-    packed_data = temp_data_0 | temp_data_1 << (enable_cnt_0 * DATA_WIDTH);
-  end
-
-  always @(counter_0, path_enabled)
-  begin
-    case (counter_0)
-      0:
-      begin
-        en1 = path_enabled[0];
-        en2 = {2{path_enabled[1]}};
-        en4 = {4{path_enabled[3]}};
-      end
-      1:
-      begin
-        en1 = path_enabled[0]       << 1;
-        en2 = {2{path_enabled[1]}}  << 0;
-        en4 = {4{path_enabled[3]}}  << 0;
-      end
-      2:
-      begin
-        en1 = path_enabled[0]       << 2;
-        en2 = {2{path_enabled[1]}}  << 2;
-        en4 = {4{path_enabled[3]}}  << 0;
-      end
-      3:
-      begin
-        en1 = path_enabled[0]       << 3;
-        en2 = {2{path_enabled[1]}}  << 2;
-        en4 = {4{path_enabled[3]}}  << 0;
-      end
-      4:
-      begin
-        if (NUM_OF_CHANNELS == 8)
-        begin
-          en1 = path_enabled[0]       << 4;
-          en2 = {2{path_enabled[1]}}  << 4;
-          en4 = {4{path_enabled[3]}}  << 4;
-        end
-        else
-        begin
-          en1 = path_enabled[0];
-          en2 = {2{path_enabled[1]}};
-          en4 = {4{path_enabled[3]}};
-        end
-      end
-      5:
-      begin
-        en1 = path_enabled[0]       << 5;
-        en2 = {2{path_enabled[1]}}  << 4;
-        en4 = {4{path_enabled[3]}}  << 4;
-      end
-      6:
-      begin
-        en1 = path_enabled[0]       << 6;
-        en2 = {2{path_enabled[1]}}  << 6;
-        en4 = {4{path_enabled[3]}}  << 4;
-      end
-      7:
-      begin
-        en1 = path_enabled[0]       << 7;
-        en2 = {2{path_enabled[1]}}  << 6;
-        en4 = {4{path_enabled[3]}}  << 4;
-      end
-      8:
-      begin
-        en1 = path_enabled[0]       << 0;
-        en2 = {2{path_enabled[1]}}  << 0;
-        en4 = {4{path_enabled[3]}}  << 0;
-      end
-      default:
-      begin
-        en1 = 8'h0;
-        en2 = 8'h0;
-        en4 = 8'h0;
-      end
-    endcase
-  end
-
-  always @(posedge clk)
-  begin
-    path_enabled_d1 <= path_enabled;
-    if (path_enabled == 8'h0 || path_enabled_d1 != path_enabled )
-    begin
-      counter_0 <= 7'h0;
-    end
-    else
-    begin
-      if( chan_valid == 1'b1)
-      begin
-        if (counter_0 > (NUM_OF_CHANNELS - 1) )
-        begin
-          counter_0 <= counter_0 - NUM_OF_CHANNELS + enable_cnt;
-        end
-        else
-        begin
-          counter_0 <= counter_0 + enable_cnt;
-        end
-        if ((counter_0 == (NUM_OF_CHANNELS - enable_cnt)) || (path_enabled == (8'h1 << (NUM_OF_CHANNELS - 1)) ))
-        begin
-          dvalid  <= 1'b1;
-        end
-        else
-        begin
-          dvalid  <= 1'b0;
-        end
-      end
-      else
-      begin
-        dvalid      <= 1'b0;
-      end
-    end
-  end
-
-  generate
-  // 8 NUM_OF_CHANNELS
-  if ( NUM_OF_CHANNELS == 8 )
-  begin
-    // FIRST FOUR NUM_OF_CHANNELS
-    always @(posedge clk)
-    begin
-      // ddata 0
-      if ((en1[0] | en2[0] | en4[0] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1)
-      begin
-        ddata[(DATA_WIDTH-1):0]     <=  packed_data[(DATA_WIDTH-1):0];
-      end
-
-      // ddata 1
-      if( en1[1] == 1'b1)
-      begin
-        ddata[2*DATA_WIDTH-1:DATA_WIDTH]    <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if ( (en2[1] | en4[1] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1)
-      begin
-        ddata[2*DATA_WIDTH-1:DATA_WIDTH]    <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
-      end
-
-      // ddata 2
-      if ((en1[2] | en2[2]) == 1'b1)
-      begin
-        ddata[3*DATA_WIDTH-1:2*DATA_WIDTH]    <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if ((en4[2] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1)
-      begin
-        ddata[3*DATA_WIDTH-1:2*DATA_WIDTH]    <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
-      end
-
-      // ddata 3
-      if (en1[3] == 1'b1)
-      begin
-        ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if (en2[3] == 1'b1)
-      begin
-        ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
-      end
-      if ((en4[3] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1)
-      begin
-        ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
-      end
-
-      // ddata 4
-      if ((en1[4] | en2[4] | en4[4]) == 1'b1)
-      begin
-        ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1)
-      begin
-        ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[5*DATA_WIDTH-1:4*DATA_WIDTH];
-      end
-
-      // ddata 5
-      if (en1[5] == 1'b1)
-      begin
-        ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if ((en2[5] | en4[5]) == 1'b1)
-      begin
-        ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
-      end
-      if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1)
-      begin
-        ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[6*DATA_WIDTH-1:5*DATA_WIDTH];
-      end
-
-      // ddata 6
-      if ((en1[6] | en2[6]) == 1'b1)
-      begin
-        ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if (en4[6] == 1'b1)
-      begin
-        ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
-      end
-      if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1)
-      begin
-        ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[7*DATA_WIDTH-1:6*DATA_WIDTH];
-      end
-
-      // ddata 7
-      if (en1[7] == 1'b1)
-      begin
-        ddata[8*DATA_WIDTH-1:7*DATA_WIDTH]  <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if (en2[7] == 1'b1)
-      begin
-        ddata[8*DATA_WIDTH-1:7*DATA_WIDTH]  <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
-      end
-      if (en4[7] == 1'b1)
-      begin
-        ddata[8*DATA_WIDTH-1:7*DATA_WIDTH]  <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
-      end
-      if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1)
-      begin
-        ddata[8*DATA_WIDTH-1:7*DATA_WIDTH]  <= packed_data[8*DATA_WIDTH-1:7*DATA_WIDTH];
-      end
-    end
-  end
-  else
-  begin
-    always @(posedge clk)
-    begin
-      // ddata 0
-      if ((en1[0] | en2[0] | path_enabled[3] ) == 1'b1)
-      begin
-        ddata[(DATA_WIDTH-1):0]     <=  packed_data[(DATA_WIDTH-1):0];
-      end
-
-      // ddata 1
-      if( en1[1] == 1'b1)
-      begin
-        ddata[2*DATA_WIDTH-1:DATA_WIDTH]    <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if ( (en2[1] | | path_enabled[3] )== 1'b1)
-      begin
-        ddata[2*DATA_WIDTH-1:DATA_WIDTH]    <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
-      end
-
-      // ddata 2
-      if ((en1[2] | en2[2]) == 1'b1)
-      begin
-        ddata[3*DATA_WIDTH-1:2*DATA_WIDTH]    <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if (( path_enabled[3]) == 1'b1)
-      begin
-        ddata[3*DATA_WIDTH-1:2*DATA_WIDTH]    <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
-      end
-
-      // ddata 3
-      if (en1[3] == 1'b1)
-      begin
-        ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
-      end
-      if (en2[3] == 1'b1)
-      begin
-        ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
-      end
-      if (path_enabled[3] == 1'b1)
-      begin
-        ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
-      end
-
-    end
-  end
-  endgenerate
-
-  endmodule
-
-  // ***************************************************************************
-  // ***************************************************************************
diff --git a/library/util_adc_pack/util_adc_pack_hw.tcl b/library/util_adc_pack/util_adc_pack_hw.tcl
deleted file mode 100644
index 30c58480a..000000000
--- a/library/util_adc_pack/util_adc_pack_hw.tcl
+++ /dev/null
@@ -1,87 +0,0 @@
-
-package require -exact qsys 13.0
-source ../scripts/adi_env.tcl
-
-set_module_property NAME util_adc_pack
-set_module_property DESCRIPTION "Util ADC data packager"
-set_module_property VERSION 1.0
-set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME util_adc_pack
-set_module_property ELABORATION_CALLBACK util_adc_pack_elaborate
-
-# files
-
-add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
-set_fileset_property quartus_synth TOP_LEVEL util_adc_pack
-add_fileset_file util_adc_pack.v   VERILOG PATH util_adc_pack.v
-
-# parameters
-
-add_parameter NUM_OF_CHANNELS INTEGER 0
-set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8
-set_parameter_property NUM_OF_CHANNELS ALLOWED_RANGES {4 8}
-set_parameter_property NUM_OF_CHANNELS DESCRIPTION "Valid values are 4 and 8"
-set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS
-set_parameter_property NUM_OF_CHANNELS TYPE INTEGER
-set_parameter_property NUM_OF_CHANNELS UNITS None
-set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
-
-add_parameter DATA_WIDTH INTEGER 0
-set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
-set_parameter_property DATA_WIDTH ALLOWED_RANGES {16 32}
-set_parameter_property DATA_WIDTH DESCRIPTION "Valid values are 16 and 32"
-set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
-set_parameter_property DATA_WIDTH TYPE INTEGER
-set_parameter_property DATA_WIDTH UNITS None
-set_parameter_property DATA_WIDTH HDL_PARAMETER true
-
-add_interface data_clock clock end
-add_interface_port data_clock clk clk Input 1
-
-add_interface channels_data conduit end
-set_interface_property channels_data associatedClock data_clock
-add_interface_port channels_data chan_enable_0 chan_enable_0 Input 1
-add_interface_port channels_data chan_valid_0 chan_valid_0 Input 1
-add_interface_port channels_data chan_data_0 chan_data_0 Input DATA_WIDTH
-
-add_interface_port channels_data chan_enable_1 chan_enable_1 Input 1
-add_interface_port channels_data chan_valid_1 chan_valid_1 Input 1
-add_interface_port channels_data chan_data_1 chan_data_1 Input DATA_WIDTH
-
-add_interface_port channels_data chan_enable_2 chan_enable_2 Input 1
-add_interface_port channels_data chan_valid_2 chan_valid_2 Input 1
-add_interface_port channels_data chan_data_2 chan_data_2 Input DATA_WIDTH
-
-add_interface_port channels_data chan_enable_3 chan_enable_3 Input 1
-add_interface_port channels_data chan_valid_3 chan_valid_3 Input 1
-add_interface_port channels_data chan_data_3 chan_data_3 Input DATA_WIDTH
-
-proc util_adc_pack_elaborate {} {
-
-  set DW [ get_parameter_value DATA_WIDTH ]
-  set CHAN [ get_parameter_value NUM_OF_CHANNELS ]
-  add_interface_port channels_data dvalid dvalid Output 1
-  add_interface_port channels_data dsync dsync Output 1
-  add_interface_port channels_data ddata ddata Output [expr {$DW * $CHAN}]
-
-  if {[get_parameter_value NUM_OF_CHANNELS] == 8} {
-
-    add_interface_port channels_data chan_enable_4 chan_enable_4 Input 1
-    add_interface_port channels_data chan_valid_4 chan_valid_4 Input 1
-    add_interface_port channels_data chan_data_4 chan_data_4 Input DATA_WIDTH
-
-    add_interface_port channels_data chan_enable_5 chan_enable_5 Input 1
-    add_interface_port channels_data chan_valid_5 chan_valid_5 Input 1
-    add_interface_port channels_data chan_data_5 chan_data_5 Input DATA_WIDTH
-
-    add_interface_port channels_data chan_enable_6 chan_enable_6 Input 1
-    add_interface_port channels_data chan_valid_6 chan_valid_6 Input 1
-    add_interface_port channels_data chan_data_6 chan_data_6 Input DATA_WIDTH
-
-    add_interface_port channels_data chan_enable_7 chan_enable_7 Input 1
-    add_interface_port channels_data chan_valid_7 chan_valid_7 Input 1
-    add_interface_port channels_data chan_data_7 chan_data_7 Input DATA_WIDTH
-}
-
-}
-
diff --git a/library/util_adc_pack/util_adc_pack_ip.tcl b/library/util_adc_pack/util_adc_pack_ip.tcl
deleted file mode 100644
index e2f31f206..000000000
--- a/library/util_adc_pack/util_adc_pack_ip.tcl
+++ /dev/null
@@ -1,42 +0,0 @@
-# ip
-
-source ../scripts/adi_env.tcl
-source $ad_hdl_dir/library/scripts/adi_ip.tcl
-
-adi_ip_create util_adc_pack
-adi_ip_files util_adc_pack [list \
-  "util_adc_pack.v" ]
-
-adi_ip_properties_lite util_adc_pack
-
-ipx::remove_bus_interface {s} [ipx::current_core]
-ipx::remove_bus_interface {m} [ipx::current_core]
-ipx::remove_bus_interface {fifo} [ipx::current_core]
-ipx::remove_bus_interface {signal_clock} [ipx::current_core]
-
-ipx::remove_memory_map {m} [ipx::current_core]
-ipx::remove_address_space {s} [ipx::current_core]
-ipx::remove_address_space {fifo} [ipx::current_core]
-
-for {set i 0} {$i < 8} {incr i} {
-	foreach port {"chan_enable" "chan_valid" "chan_data"} {
-		set name [format "%s_%d" $port $i]
-		set_property ENABLEMENT_DEPENDENCY \
-		"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i)" \
-		[ipx::get_ports $name]
-		set_property DRIVER_VALUE "0" [ipx::get_ports $name]
-	}
-}
-
-adi_add_bus "fifo_wr" "master" \
-	"analog.com:interface:fifo_wr_rtl:1.0" \
-	"analog.com:interface:fifo_wr:1.0" \
-	{ \
-		{"dvalid" "EN"} \
-		{"ddata" "DATA"} \
-		{"dsync" "SYNC"} \
-	}
-
-adi_add_bus_clock "clk" "fifo_wr"
-
-ipx::save_core [ipx::current_core]

From df43ca9332cc30222ab0b01e2410c76138db846e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 13:27:32 +0300
Subject: [PATCH 326/972] ad_axis_dma_*: Delete unused modules

---
 library/common/ad_axis_dma_rx.v | 330 --------------------------------
 library/common/ad_axis_dma_tx.v | 281 ---------------------------
 2 files changed, 611 deletions(-)
 delete mode 100644 library/common/ad_axis_dma_rx.v
 delete mode 100644 library/common/ad_axis_dma_tx.v

diff --git a/library/common/ad_axis_dma_rx.v b/library/common/ad_axis_dma_rx.v
deleted file mode 100644
index 08c40b4e2..000000000
--- a/library/common/ad_axis_dma_rx.v
+++ /dev/null
@@ -1,330 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module ad_axis_dma_rx (
-
-  // dma interface
-
-  dma_clk,
-  dma_rst,
-  dma_valid,
-  dma_last,
-  dma_data,
-  dma_ready,
-  dma_ovf,
-  dma_unf,
-  dma_status,
-  dma_bw,
-
-  // data interface
-
-  adc_clk,
-  adc_rst,
-  adc_valid,
-  adc_data,
-
-  // processor interface
-
-  dma_start,
-  dma_stream,
-  dma_count);
-
-  // parameters
-
-  parameter       DATA_WIDTH = 64;
-  localparam      DW = DATA_WIDTH - 1;
-  localparam      BUF_THRESHOLD_LO = 6'd3;
-  localparam      BUF_THRESHOLD_HI = 6'd60;
-  localparam      DATA_WIDTH_IN_BYTES = DATA_WIDTH/8;
-
-  // dma interface
-
-  input           dma_clk;
-  input           dma_rst;
-  output          dma_valid;
-  output          dma_last;
-  output  [DW:0]  dma_data;
-  input           dma_ready;
-  output          dma_ovf;
-  output          dma_unf;
-  output          dma_status;
-  output  [31:0]  dma_bw;
-
-  // data interface
-
-  input           adc_clk;
-  input           adc_rst;
-  input           adc_valid;
-  input   [DW:0]  adc_data;
-
-  // processor interface
-
-  input           dma_start;
-  input           dma_stream;
-  input   [31:0]  dma_count;
-
-  // internal registers
-
-  reg             dma_valid_int = 'd0;
-  reg             dma_last_int = 'd0;
-  reg     [DW:0]  dma_data_int = 'd0;
-  reg             dma_capture_enable = 'd0;
-  reg     [31:0]  dma_capture_count = 'd0;
-  reg             dma_rd = 'd0;
-  reg     [ 5:0]  dma_raddr = 'd0;
-  reg             dma_release_toggle_m1 = 'd0;
-  reg             dma_release_toggle_m2 = 'd0;
-  reg             dma_release_toggle_m3 = 'd0;
-  reg     [ 5:0]  dma_release_waddr = 'd0;
-  reg     [ 5:0]  dma_waddr_m1 = 'd0;
-  reg     [ 5:0]  dma_waddr_m2 = 'd0;
-  reg     [ 5:0]  dma_waddr = 'd0;
-  reg     [ 5:0]  dma_addr_diff = 'd0;
-  reg             dma_almost_full = 'd0;
-  reg             dma_almost_empty = 'd0;
-  reg             dma_ovf = 'd0;
-  reg             dma_unf = 'd0;
-  reg             dma_resync = 'd0;
-  reg             adc_wr = 'd0;
-  reg     [ 5:0]  adc_waddr = 'd0;
-  reg     [ 5:0]  adc_waddr_g = 'd0;
-  reg     [ 3:0]  adc_release_count = 'd0;
-  reg     [DW:0]  adc_wdata = 'd0;
-  reg             adc_release_toggle = 'd0;
-  reg     [ 5:0]  adc_release_waddr = 'd0;
-  reg             adc_resync_m1 = 'd0;
-  reg             adc_resync_m2 = 'd0;
-  reg             adc_resync = 'd0;
-
-  // internal signals
-
-  wire            dma_rd_valid_s;
-  wire            dma_last_s;
-  wire            dma_ready_s;
-  wire            dma_rd_s;
-  wire            dma_release_s;
-  wire    [ 6:0]  dma_addr_diff_s;
-  wire            dma_ovf_s;
-  wire            dma_unf_s;
-  wire    [DW:0]  dma_rdata_s;
-
-  // binary to grey conversion
-
-  function [5:0] b2g;
-    input [5:0] b;
-    reg   [5:0] g;
-    begin
-      g[5] = b[5];
-      g[4] = b[5] ^ b[4];
-      g[3] = b[4] ^ b[3];
-      g[2] = b[3] ^ b[2];
-      g[1] = b[2] ^ b[1];
-      g[0] = b[1] ^ b[0];
-      b2g = g;
-    end
-  endfunction
-
-  // grey to binary conversion
-
-  function [5:0] g2b;
-    input [5:0] g;
-    reg   [5:0] b;
-    begin
-      b[5] = g[5];
-      b[4] = b[5] ^ g[4];
-      b[3] = b[4] ^ g[3];
-      b[2] = b[3] ^ g[2];
-      b[1] = b[2] ^ g[1];
-      b[0] = b[1] ^ g[0];
-      g2b = b;
-    end
-  endfunction
-
-  // dma read- user interface
-
-  assign dma_bw = DATA_WIDTH_IN_BYTES;
-  assign dma_status = dma_capture_enable;
-
-  always @(posedge dma_clk) begin
-    dma_valid_int <= dma_rd_valid_s;
-    dma_last_int <= dma_last_s;
-    dma_data_int <= dma_rdata_s;
-  end
-
-  // dma read- capture control signals
-
-  assign dma_rd_valid_s = dma_capture_enable & dma_rd;
-  assign dma_last_s = (dma_capture_count == dma_count) ? dma_rd_valid_s : 1'b0;
-
-  always @(posedge dma_clk) begin
-    if ((dma_stream == 1'b0) && (dma_last_s == 1'b1)) begin
-      dma_capture_enable <= 1'b0;
-    end else if (dma_start == 1'b1) begin
-      dma_capture_enable <= 1'b1;
-    end
-    if ((dma_capture_enable == 1'b0) || (dma_last_s == 1'b1)) begin
-      dma_capture_count <= dma_bw;
-    end else if (dma_rd == 1'b1) begin
-      dma_capture_count <= dma_capture_count + dma_bw;
-    end
-  end
-
-  // dma read- read data always and pass it to the external memory
-
-  assign dma_ready_s = (~dma_capture_enable) | dma_ready;
-  assign dma_rd_s = (dma_release_waddr == dma_raddr) ? 1'b0 : dma_ready_s;
-
-  always @(posedge dma_clk) begin
-    dma_rd <= dma_rd_s;
-    if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
-      dma_raddr <= 6'd0;
-    end else if (dma_rd_s == 1'b1) begin
-      dma_raddr <= dma_raddr + 1'b1;
-    end
-  end
-
-  // dma read- get bursts of adc data from the other side
-
-  assign dma_release_s = dma_release_toggle_m3 ^ dma_release_toggle_m2;
-
-  always @(posedge dma_clk) begin
-    if (dma_rst == 1'b1) begin
-      dma_release_toggle_m1 <= 'd0;
-      dma_release_toggle_m2 <= 'd0;
-      dma_release_toggle_m3 <= 'd0;
-    end else begin
-      dma_release_toggle_m1 <= adc_release_toggle;
-      dma_release_toggle_m2 <= dma_release_toggle_m1;
-      dma_release_toggle_m3 <= dma_release_toggle_m2;
-    end
-    if (dma_resync == 1'b1) begin
-      dma_release_waddr <= 6'd0;
-    end else if (dma_release_s == 1'b1) begin
-      dma_release_waddr <= adc_release_waddr;
-    end
-  end
-
-  // dma read- get free running write address for ovf/unf checking
-
-  assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
-  assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
-  assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
-
-  always @(posedge dma_clk) begin
-    if (dma_rst == 1'b1) begin
-      dma_waddr_m1 <= 'd0;
-      dma_waddr_m2 <= 'd0;
-    end else begin
-      dma_waddr_m1 <= adc_waddr_g;
-      dma_waddr_m2 <= dma_waddr_m1;
-    end
-    dma_waddr <= g2b(dma_waddr_m2);
-    dma_addr_diff <= dma_addr_diff_s[5:0];
-    if (dma_addr_diff > BUF_THRESHOLD_HI) begin
-      dma_almost_full <= 1'b1;
-    end else begin
-      dma_almost_full <= 1'b0;
-    end
-    if (dma_addr_diff < BUF_THRESHOLD_LO) begin
-      dma_almost_empty <= 1'b1;
-    end else begin
-      dma_almost_empty <= 1'b0;
-    end
-    dma_ovf <= dma_ovf_s;
-    dma_unf <= dma_unf_s;
-    dma_resync <= dma_ovf | dma_unf;
-  end
-
-  // adc write- used here to simply transfer data to the dma side
-  // address is released with a free running counter
-
-  always @(posedge adc_clk) begin
-    adc_wr <= adc_valid;
-    if ((adc_resync == 1'b1) || (adc_rst == 1'b1)) begin
-      adc_waddr <= 6'd0;
-    end else if (adc_wr == 1'b1) begin
-      adc_waddr <= adc_waddr + 1'b1;
-    end
-    adc_waddr_g <= b2g(adc_waddr);
-    adc_wdata <= adc_data;
-    adc_release_count <= adc_release_count + 1'b1;
-    if (adc_release_count == 4'hf) begin
-      adc_release_toggle <= ~adc_release_toggle;
-      adc_release_waddr <= adc_waddr;
-    end
-    if (adc_rst == 1'b1) begin
-      adc_resync_m1 <= 'd0;
-      adc_resync_m2 <= 'd0;
-    end else begin
-      adc_resync_m1 <= dma_resync;
-      adc_resync_m2 <= adc_resync_m1;
-    end
-    adc_resync <= adc_resync_m2;
-  end
-
-  // interface handler for ready
-
-  ad_axis_inf_rx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_inf (
-    .clk (dma_clk),
-    .rst (dma_rst),
-    .valid (dma_valid_int),
-    .last (dma_last_int),
-    .data (dma_data_int),
-    .inf_valid (dma_valid),
-    .inf_last (dma_last),
-    .inf_data (dma_data),
-    .inf_ready (dma_ready));
-
-  // buffer (mainly for clock domain transfer)
-
-  ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem (
-    .clka (adc_clk),
-    .wea (adc_wr),
-    .addra (adc_waddr),
-    .dina (adc_wdata),
-    .clkb (dma_clk),
-    .addrb (dma_raddr),
-    .doutb (dma_rdata_s));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_axis_dma_tx.v b/library/common/ad_axis_dma_tx.v
deleted file mode 100644
index d14f32c48..000000000
--- a/library/common/ad_axis_dma_tx.v
+++ /dev/null
@@ -1,281 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// dac vdma read
-
-module ad_axis_dma_tx (
-
-  // vdma interface
-
-  dma_clk,
-  dma_rst,
-  dma_fs,
-  dma_valid,
-  dma_data,
-  dma_ready,
-  dma_ovf,
-  dma_unf,
-
-  // dac interface 
-
-  dac_clk,
-  dac_rst,
-  dac_rd,
-  dac_valid,
-  dac_data,
-
-  // processor interface
-
-  dma_frmcnt);
-
-  // parameters
-
-  parameter       DATA_WIDTH = 64;
-  localparam      DW = DATA_WIDTH - 1;
-  localparam      BUF_THRESHOLD_LO = 6'd3;
-  localparam      BUF_THRESHOLD_HI = 6'd60;
-  localparam      RDY_THRESHOLD_LO = 6'd40;
-  localparam      RDY_THRESHOLD_HI = 6'd50;
-
-  // vdma interface
-
-  input           dma_clk;
-  input           dma_rst;
-  output          dma_fs;
-  input           dma_valid;
-  input   [DW:0]  dma_data;
-  output          dma_ready;
-  output          dma_ovf;
-  output          dma_unf;
-
-  // dac interface
-
-  input           dac_clk;
-  input           dac_rst;
-  input           dac_rd;
-  output          dac_valid;
-  output  [DW:0]  dac_data;
-
-  // processor interface
-
-  input   [31:0]  dma_frmcnt;
-
-  // internal registers
-
-  reg             dac_start_m1 = 'd0;
-  reg             dac_start = 'd0;
-  reg             dac_resync_m1 = 'd0;
-  reg             dac_resync = 'd0;
-  reg     [ 5:0]  dac_raddr = 'd0;
-  reg     [ 5:0]  dac_raddr_g = 'd0;
-  reg             dac_rd_d = 'd0;
-  reg             dac_rd_2d = 'd0;
-  reg             dac_valid = 'd0;
-  reg     [DW:0]  dac_data = 'd0;
-  reg     [31:0]  dma_clkcnt = 'd0;
-  reg             dma_fs = 'd0;
-  reg     [ 5:0]  dma_raddr_g_m1 = 'd0;
-  reg     [ 5:0]  dma_raddr_g_m2 = 'd0;
-  reg     [ 5:0]  dma_raddr = 'd0;
-  reg     [ 5:0]  dma_addr_diff = 'd0;
-  reg             dma_ready = 'd0;
-  reg             dma_almost_full = 'd0;
-  reg             dma_almost_empty = 'd0;
-  reg             dma_ovf = 'd0;
-  reg             dma_unf = 'd0;
-  reg             dma_resync = 'd0;
-  reg             dma_start = 'd0;
-  reg             dma_wr = 'd0;
-  reg     [ 5:0]  dma_waddr = 'd0;
-  reg     [DW:0]  dma_wdata = 'd0;
-
-  // internal signals
-
-  wire            dma_wr_s;
-  wire    [ 6:0]  dma_addr_diff_s;
-  wire            dma_ovf_s;
-  wire            dma_unf_s;
-  wire    [DW:0]  dac_rdata_s;
-
-  // binary to grey coversion
-
-  function [7:0] b2g;
-    input [7:0] b;
-    reg   [7:0] g;
-    begin
-      g[7] = b[7];
-      g[6] = b[7] ^ b[6];
-      g[5] = b[6] ^ b[5];
-      g[4] = b[5] ^ b[4];
-      g[3] = b[4] ^ b[3];
-      g[2] = b[3] ^ b[2];
-      g[1] = b[2] ^ b[1];
-      g[0] = b[1] ^ b[0];
-      b2g = g;
-    end
-  endfunction
-
-  // grey to binary conversion
-
-  function [7:0] g2b;
-    input [7:0] g;
-    reg   [7:0] b;
-    begin
-      b[7] = g[7];
-      b[6] = b[7] ^ g[6];
-      b[5] = b[6] ^ g[5];
-      b[4] = b[5] ^ g[4];
-      b[3] = b[4] ^ g[3];
-      b[2] = b[3] ^ g[2];
-      b[1] = b[2] ^ g[1];
-      b[0] = b[1] ^ g[0];
-      g2b = b;
-    end
-  endfunction
-
-  // dac read interface
-
-  always @(posedge dac_clk) begin
-    if (dac_rst == 1'b1) begin
-      dac_start_m1 <= 'd0;
-      dac_start <= 'd0;
-      dac_resync_m1 <= 'd0;
-      dac_resync <= 'd0;
-    end else begin
-      dac_start_m1 <= dma_start;
-      dac_start <= dac_start_m1;
-      dac_resync_m1 <= dma_resync;
-      dac_resync <= dac_resync_m1;
-    end
-    if ((dac_start == 1'b0) || (dac_resync == 1'b1) || (dac_rst == 1'b1)) begin
-      dac_raddr <= 6'd0;
-    end else if (dac_rd == 1'b1) begin
-      dac_raddr <= dac_raddr + 1'b1;
-    end
-    dac_raddr_g <= b2g(dac_raddr);
-    dac_rd_d <= dac_rd;
-    dac_rd_2d <= dac_rd_d;
-    dac_valid <= dac_rd_2d;
-    dac_data <= dac_rdata_s;
-  end
-    
-  // generate fsync
-
-  always @(posedge dma_clk) begin
-    if ((dma_resync == 1'b1) || (dma_rst == 1'b1) || (dma_clkcnt >= dma_frmcnt)) begin
-      dma_clkcnt <= 16'd0;
-    end else begin
-      dma_clkcnt <= dma_clkcnt + 1'b1;
-    end
-    if (dma_clkcnt == 32'd1) begin
-      dma_fs <= 1'b1;
-    end else begin
-      dma_fs <= 1'b0;
-    end
-  end
-
-  // overflow or underflow status
-
-  assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
-  assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
-  assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
-
-  always @(posedge dma_clk) begin
-    if (dma_rst == 1'b1) begin
-      dma_raddr_g_m1 <= 'd0;
-      dma_raddr_g_m2 <= 'd0;
-    end else begin
-      dma_raddr_g_m1 <= dac_raddr_g;
-      dma_raddr_g_m2 <= dma_raddr_g_m1;
-    end
-    dma_raddr <= g2b(dma_raddr_g_m2);
-    dma_addr_diff <= dma_addr_diff_s[5:0];
-    if (dma_addr_diff >= RDY_THRESHOLD_HI) begin
-      dma_ready <= 1'b0;
-    end else if (dma_addr_diff <= RDY_THRESHOLD_LO) begin
-      dma_ready <= 1'b1;
-    end
-    if (dma_addr_diff > BUF_THRESHOLD_HI) begin
-      dma_almost_full <= 1'b1;
-    end else begin
-      dma_almost_full <= 1'b0;
-    end
-    if (dma_addr_diff < BUF_THRESHOLD_LO) begin
-      dma_almost_empty <= 1'b1;
-    end else begin
-      dma_almost_empty <= 1'b0;
-    end
-    dma_ovf <= dma_ovf_s;
-    dma_unf <= dma_unf_s;
-    dma_resync <= dma_ovf | dma_unf;
-  end
-
-  // vdma write
-
-  assign dma_wr_s = dma_valid & dma_ready;
-
-  always @(posedge dma_clk) begin
-    if (dma_rst == 1'b1) begin
-      dma_start <= 1'b0;
-    end else if (dma_wr_s == 1'b1) begin
-      dma_start <= 1'b1;
-    end
-    dma_wr <= dma_wr_s;
-    if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
-      dma_waddr <= 6'd0;
-    end else if (dma_wr == 1'b1) begin
-      dma_waddr <= dma_waddr + 1'b1;
-    end
-    dma_wdata <= dma_data;
-  end
-
-  // memory
-
-  ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem (
-    .clka (dma_clk),
-    .wea (dma_wr),
-    .addra (dma_waddr),
-    .dina (dma_wdata),
-    .clkb (dac_clk),
-    .addrb (dac_raddr),
-    .doutb (dac_rdata_s));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From af9915b0603df0b2140997f4c80da683a322b282 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 13:29:01 +0300
Subject: [PATCH 327/972] up_axis_dma_*: Delete unused modules

---
 library/common/up_axis_dma_rx.v | 249 --------------------------------
 library/common/up_axis_dma_tx.v | 213 ---------------------------
 2 files changed, 462 deletions(-)
 delete mode 100644 library/common/up_axis_dma_rx.v
 delete mode 100644 library/common/up_axis_dma_tx.v

diff --git a/library/common/up_axis_dma_rx.v b/library/common/up_axis_dma_rx.v
deleted file mode 100644
index 71494cf80..000000000
--- a/library/common/up_axis_dma_rx.v
+++ /dev/null
@@ -1,249 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module up_axis_dma_rx (
-
-  // adc interface
-
-  adc_clk,
-  adc_rst,
-
-  // dma interface
-
-  dma_clk,
-  dma_rst,
-  dma_start,
-  dma_stream,
-  dma_count,
-  dma_ovf,
-  dma_unf,
-  dma_status,
-  dma_bw,
-
-  // bus interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
-
-  // parameters
-
-  localparam  PCORE_VERSION = 32'h00050063;
-  parameter   ID = 0;
-
-  // adc interface
-
-  input           adc_clk;
-  output          adc_rst;
-
-  // dma interface
-
-  input           dma_clk;
-  output          dma_rst;
-  output          dma_start;
-  output          dma_stream;
-  output  [31:0]  dma_count;
-  input           dma_ovf;
-  input           dma_unf;
-  input           dma_status;
-  input   [31:0]  dma_bw;
-
-  // bus interface
-
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
-
-  // internal registers
-
-  reg             up_preset = 'd0;
-  reg             up_wack = 'd0;
-  reg     [31:0]  up_scratch = 'd0;
-  reg             up_resetn = 'd0;
-  reg             up_dma_stream = 'd0;
-  reg             up_dma_start = 'd0;
-  reg     [31:0]  up_dma_count = 'd0;
-  reg             up_dma_ovf = 'd0;
-  reg             up_dma_unf = 'd0;
-  reg             up_rack = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
-  reg             dma_start_d = 'd0;
-  reg             dma_start_2d = 'd0;
-  reg             dma_start = 'd0;
-
-  // internal signals
-
-  wire            up_wreq_s;
-  wire            up_rreq_s;
-  wire            up_dma_ovf_s;
-  wire            up_dma_unf_s;
-  wire            up_dma_status_s;
-
-  // decode block select
-
-  assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
-  assign up_rreq_s = (up_waddr[13:8] == 6'h00) ? up_rreq : 1'b0;
-
-  // processor write interface
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_preset <= 1'd1;
-      up_wack <= 'd0;
-      up_scratch <= 'd0;
-      up_resetn <= 'd0;
-      up_dma_stream <= 'd0;
-      up_dma_start <= 'd0;
-      up_dma_count <= 'd0;
-      up_dma_ovf <= 'd0;
-      up_dma_unf <= 'd0;
-    end else begin
-      up_preset <= 1'd0;
-      up_wack <= up_wreq_s;
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
-        up_scratch <= up_wdata;
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
-        up_resetn <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
-        up_dma_stream <= up_wdata[1];
-        up_dma_start <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
-        up_dma_count <= up_wdata;
-      end
-      if (up_dma_ovf_s == 1'b1) begin
-        up_dma_ovf <= 1'b1;
-      end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
-        up_dma_ovf <= up_dma_ovf & ~up_wdata[2];
-      end
-      if (up_dma_unf_s == 1'b1) begin
-        up_dma_unf <= 1'b1;
-      end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
-        up_dma_unf <= up_dma_unf & ~up_wdata[1];
-      end
-    end
-  end
-
-  // processor read interface
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
-    end else begin
-      up_rack <= up_rreq_s;
-      if (up_rreq_s == 1'b1) begin
-        case (up_raddr[7:0])
-          8'h00: up_rdata <= PCORE_VERSION;
-          8'h01: up_rdata <= ID;
-          8'h02: up_rdata <= up_scratch;
-          8'h10: up_rdata <= {31'd0, up_resetn};
-          8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start};
-          8'h21: up_rdata <= up_dma_count;
-          8'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status_s};
-          8'h23: up_rdata <= dma_bw;
-          default: up_rdata <= 0;
-        endcase
-      end else begin
-        up_rdata <= 32'd0;
-      end
-    end
-  end
-
-  // resets
-
-  ad_rst i_adc_rst_reg (.preset(up_preset), .clk(adc_clk), .rst(adc_rst));
-  ad_rst i_dma_rst_reg (.preset(up_preset), .clk(dma_clk), .rst(dma_rst));
-
-  // dma control & status
-
-  up_xfer_cntrl #(.DATA_WIDTH(34)) i_dma_xfer_cntrl (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_data_cntrl ({ up_dma_start,
-                      up_dma_stream,
-                      up_dma_count}),
-    .d_rst (dma_rst),
-    .d_clk (dma_clk),
-    .d_data_cntrl ({  dma_start_s,
-                      dma_stream,
-                      dma_count}));
-
-  up_xfer_status #(.DATA_WIDTH(3)) i_dma_xfer_status (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_data_status ({up_dma_ovf_s,
-                      up_dma_unf_s,
-                      up_dma_status_s}),
-    .d_rst (dma_rst),
-    .d_clk (dma_clk),
-    .d_data_status ({ dma_ovf,
-                      dma_unf,
-                      dma_status}));
-
-  // start needs to be a pulse
-
-  always @(posedge dma_clk) begin
-    dma_start_d <= dma_start_s;
-    dma_start_2d <= dma_start_d;
-    dma_start <= dma_start_d & ~dma_start_2d;
-  end
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_axis_dma_tx.v b/library/common/up_axis_dma_tx.v
deleted file mode 100644
index 454ed9f37..000000000
--- a/library/common/up_axis_dma_tx.v
+++ /dev/null
@@ -1,213 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module up_axis_dma_tx (
-
-  // dac interface
-
-  dac_clk,
-  dac_rst,
-
-  // dma interface
-
-  dma_clk,
-  dma_rst,
-  dma_frmcnt,
-  dma_ovf,
-  dma_unf,
-
-  // bus interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
-
-  // parameters
-
-  localparam  PCORE_VERSION = 32'h00050062;
-  parameter   ID = 0;
-
-  // dac interface
-
-  input           dac_clk;
-  output          dac_rst;
-
-  // dma interface
-
-  input           dma_clk;
-  output          dma_rst;
-  output  [31:0]  dma_frmcnt;
-  input           dma_ovf;
-  input           dma_unf;
-
-  // bus interface
-
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
-
-  // internal registers
-
-  reg             up_preset = 'd0;
-  reg             up_wack = 'd0;
-  reg     [31:0]  up_scratch = 'd0;
-  reg             up_resetn = 'd0;
-  reg     [31:0]  up_dma_frmcnt = 'd0;
-  reg             up_dma_ovf = 'd0;
-  reg             up_dma_unf = 'd0;
-  reg             up_rack = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
-
-  // internal signals
-
-  wire            up_wreq_s;
-  wire            up_rreq_s;
-  wire            up_dma_ovf_s;
-  wire            up_dma_unf_s;
-
-  // decode block select
-
-  assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0;
-  assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0;
-
-  // processor write interface
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_preset <= 1'd1;
-      up_wack <= 'd0;
-      up_scratch <= 'd0;
-      up_resetn <= 'd0;
-      up_dma_frmcnt <= 'd0;
-      up_dma_ovf <= 'd0;
-      up_dma_unf <= 'd0;
-    end else begin
-      up_preset <= 1'd0;
-      up_wack <= up_wreq_s;
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
-        up_scratch <= up_wdata;
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
-        up_resetn <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
-        up_dma_frmcnt <= up_wdata;
-      end
-      if (up_dma_ovf_s == 1'b1) begin
-        up_dma_ovf <= 1'b1;
-      end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
-        up_dma_ovf <= up_dma_ovf & ~up_wdata[1];
-      end
-      if (up_dma_unf_s == 1'b1) begin
-        up_dma_unf <= 1'b1;
-      end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
-        up_dma_unf <= up_dma_unf & ~up_wdata[0];
-      end
-    end
-  end
-
-  // processor read interface
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
-    end else begin
-      up_rack <= up_rreq_s;
-      if (up_rreq_s == 1'b1) begin
-        case (up_raddr[7:0])
-          8'h00: up_rdata <= PCORE_VERSION;
-          8'h01: up_rdata <= ID;
-          8'h02: up_rdata <= up_scratch;
-          8'h10: up_rdata <= {31'd0, up_resetn};
-          8'h21: up_rdata <= up_dma_frmcnt;
-          8'h22: up_rdata <= {30'd0, up_dma_ovf, up_dma_unf};
-          default: up_rdata <= 0;
-        endcase
-      end else begin
-        up_rdata <= 32'd0;
-      end
-    end
-  end
-
-  // resets
-
-  ad_rst i_dac_rst_reg (.preset(up_preset), .clk(dac_clk), .rst(dac_rst));
-  ad_rst i_dma_rst_reg (.preset(up_preset), .clk(dma_clk), .rst(dma_rst));
-
-  // dma control & status
-
-  up_xfer_cntrl #(.DATA_WIDTH(32)) i_dma_xfer_cntrl (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_data_cntrl (  up_dma_frmcnt),
-    .d_rst (dma_rst),
-    .d_clk (dma_clk),
-    .d_data_cntrl (   dma_frmcnt));
-
-  up_xfer_status #(.DATA_WIDTH(2)) i_dma_xfer_status (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_data_status ({up_dma_ovf_s,
-                      up_dma_unf_s}),
-    .d_rst (dma_rst),
-    .d_clk (dma_clk),
-    .d_data_status ({ dma_ovf,
-                      dma_unf}));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From 2dd6bb0cb82e782eeb9b783de626b552d10d101c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 13:29:45 +0300
Subject: [PATCH 328/972] up_drp_cntrl: Delete unused module

---
 library/common/up_drp_cntrl.v | 194 ----------------------------------
 1 file changed, 194 deletions(-)
 delete mode 100644 library/common/up_drp_cntrl.v

diff --git a/library/common/up_drp_cntrl.v b/library/common/up_drp_cntrl.v
deleted file mode 100644
index c9bce27a8..000000000
--- a/library/common/up_drp_cntrl.v
+++ /dev/null
@@ -1,194 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module up_drp_cntrl (
-
-  // drp interface
-
-  drp_clk,
-  drp_rst,
-  drp_sel,
-  drp_wr,
-  drp_addr,
-  drp_wdata,
-  drp_rdata,
-  drp_ready,
-  drp_locked,
-
-  // processor interface
-
-  up_rstn,
-  up_clk,
-  up_drp_sel_t,
-  up_drp_rwn,
-  up_drp_addr,
-  up_drp_wdata,
-  up_drp_rdata,
-  up_drp_status,
-  up_drp_locked);
-
-  // drp interface
-
-  input           drp_clk;
-  input           drp_rst;
-  output          drp_sel;
-  output          drp_wr;
-  output  [11:0]  drp_addr;
-  output  [15:0]  drp_wdata;
-  input   [15:0]  drp_rdata;
-  input           drp_ready;
-  input           drp_locked;
-
-  // processor interface
-
-  input           up_rstn;
-  input           up_clk;
-  input           up_drp_sel_t;
-  input           up_drp_rwn;
-  input   [11:0]  up_drp_addr;
-  input   [15:0]  up_drp_wdata;
-  output  [15:0]  up_drp_rdata;
-  output          up_drp_status;
-  output          up_drp_locked;
-
-  // internal registers
-
-  reg             drp_sel_t_m1 = 'd0;
-  reg             drp_sel_t_m2 = 'd0;
-  reg             drp_sel_t_m3 = 'd0;
-  reg             drp_sel = 'd0;
-  reg             drp_wr = 'd0;
-  reg     [11:0]  drp_addr = 'd0;
-  reg     [15:0]  drp_wdata = 'd0;
-  reg             drp_ready_int = 'd0;
-  reg     [15:0]  drp_rdata_int = 'd0;
-  reg             drp_ack_t = 'd0;
-  reg             up_drp_locked_m1 = 'd0;
-  reg             up_drp_locked = 'd0;
-  reg             up_drp_ack_t_m1 = 'd0;
-  reg             up_drp_ack_t_m2 = 'd0;
-  reg             up_drp_ack_t_m3 = 'd0;
-  reg             up_drp_sel_t_d = 'd0;
-  reg             up_drp_status = 'd0;
-  reg     [15:0]  up_drp_rdata = 'd0;
-
-  // internal signals
-
-  wire            drp_sel_t_s;
-  wire            up_drp_ack_t_s;
-  wire            up_drp_sel_t_s;
-
-  // drp control and status
-
-  assign drp_sel_t_s = drp_sel_t_m2 ^ drp_sel_t_m3;
-
-  always @(posedge drp_clk) begin
-    if (drp_rst == 1'b1) begin
-      drp_sel_t_m1 <= 'd0;
-      drp_sel_t_m2 <= 'd0;
-      drp_sel_t_m3 <= 'd0;
-    end else begin
-      drp_sel_t_m1 <= up_drp_sel_t;
-      drp_sel_t_m2 <= drp_sel_t_m1;
-      drp_sel_t_m3 <= drp_sel_t_m2;
-    end
-  end
-
-  always @(posedge drp_clk) begin
-    if (drp_sel_t_s == 1'b1) begin
-      drp_sel <= 1'b1;
-      drp_wr <= ~up_drp_rwn;
-      drp_addr <= up_drp_addr;
-      drp_wdata <= up_drp_wdata;
-    end else begin
-      drp_sel <= 1'b0;
-      drp_wr <= 1'b0;
-      drp_addr <= 12'd0;
-      drp_wdata <= 16'd0;
-    end
-  end
-
-  always @(posedge drp_clk) begin
-    drp_ready_int <= drp_ready;
-    if ((drp_ready_int == 1'b0) && (drp_ready == 1'b1)) begin
-      drp_rdata_int <= drp_rdata;
-      drp_ack_t <= ~drp_ack_t;
-    end
-  end
-
-
-  // drp status transfer
-
-  assign up_drp_ack_t_s = up_drp_ack_t_m3 ^ up_drp_ack_t_m2;
-  assign up_drp_sel_t_s = up_drp_sel_t ^ up_drp_sel_t_d;
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 1'b0) begin
-      up_drp_locked_m1 <= 'd0;
-      up_drp_locked <= 'd0;
-      up_drp_ack_t_m1 <= 'd0;
-      up_drp_ack_t_m2 <= 'd0;
-      up_drp_ack_t_m3 <= 'd0;
-      up_drp_sel_t_d <= 'd0;
-      up_drp_status <= 'd0;
-      up_drp_rdata <= 'd0;
-    end else begin
-      up_drp_locked_m1 <= drp_locked;
-      up_drp_locked <= up_drp_locked_m1;
-      up_drp_ack_t_m1 <= drp_ack_t;
-      up_drp_ack_t_m2 <= up_drp_ack_t_m1;
-      up_drp_ack_t_m3 <= up_drp_ack_t_m2;
-      up_drp_sel_t_d <= up_drp_sel_t;
-      if (up_drp_ack_t_s == 1'b1) begin
-        up_drp_status <= 1'b0;
-      end else if (up_drp_sel_t_s == 1'b1) begin
-        up_drp_status <= 1'b1;
-      end
-      if (up_drp_ack_t_s == 1'b1) begin
-        up_drp_rdata <= drp_rdata_int;
-      end
-    end
-  end
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From 040f72d17221e1dd2b17c375b50488acc66bc1be Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 20 Jul 2016 13:30:28 +0300
Subject: [PATCH 329/972] ad_mul_u16: Delete unused module

---
 library/common/ad_mul_u16.v | 110 ------------------------------------
 1 file changed, 110 deletions(-)
 delete mode 100644 library/common/ad_mul_u16.v

diff --git a/library/common/ad_mul_u16.v b/library/common/ad_mul_u16.v
deleted file mode 100644
index eb4978dfb..000000000
--- a/library/common/ad_mul_u16.v
+++ /dev/null
@@ -1,110 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// both inputs are considered unsigned 16 bits-
-// ddata is delay matched generic data
-
-`timescale 1ps/1ps
-
-module ad_mul_u16 (
-
-  // data_p = data_a * data_b;
-
-  clk,
-  data_a,
-  data_b,
-  data_p,
-
-  // delay interface
-
-  ddata_in,
-  ddata_out);
-
-  // delayed data bus width
-
-  parameter   DELAY_DATA_WIDTH = 16;
-  localparam  DW = DELAY_DATA_WIDTH - 1;
-
-  // data_p = data_a * data_b;
-
-  input           clk;
-  input   [15:0]  data_a;
-  input   [15:0]  data_b;
-  output  [31:0]  data_p;
-
-  // delay interface
-
-  input   [DW:0]  ddata_in;
-  output  [DW:0]  ddata_out;
-
-  // internal registers
-
-  reg     [DW:0]  p1_ddata = 'd0;
-  reg     [DW:0]  p2_ddata = 'd0;
-  reg     [DW:0]  ddata_out = 'd0;
-
-  // internal signals
-
-  wire    [33:0]  data_p_s;
-
-  // a/b reg, m-reg, p-reg delay match
-
-  always @(posedge clk) begin
-    p1_ddata <= ddata_in;
-    p2_ddata <= p1_ddata;
-    ddata_out <= p2_ddata;
-  end
-
-  assign data_p = data_p_s[31:0];
-
-  MULT_MACRO #(
-    .LATENCY (3),
-    .A_DATA_WIDTH (17),
-    .B_DATA_WIDTH (17))
-  i_mult_macro (
-    .CE (1'b1),
-    .RST (1'b0),
-    .CLK (clk),
-    .A ({1'b0, data_a}),
-    .B ({1'b0, data_b}),
-    .P (data_p_s));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From 3a1ecb7463f5af10d15566c0448cb918a2b64902 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 21 Jul 2016 11:56:39 -0400
Subject: [PATCH 330/972] ad9162- support iq mode

---
 library/axi_ad9162/axi_ad9162.v         | 156 +++-----
 library/axi_ad9162/axi_ad9162_channel.v | 475 ++++++++++++------------
 library/axi_ad9162/axi_ad9162_core.v    | 119 +++---
 library/axi_ad9162/axi_ad9162_if.v      | 129 +++----
 4 files changed, 395 insertions(+), 484 deletions(-)

diff --git a/library/axi_ad9162/axi_ad9162.v b/library/axi_ad9162/axi_ad9162.v
index 0590af546..6fff5f0c7 100644
--- a/library/axi_ad9162/axi_ad9162.v
+++ b/library/axi_ad9162/axi_ad9162.v
@@ -34,12 +34,10 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns / 1ps
 
-module axi_ad9162(
+module axi_ad9162 (
 
     // jesd interface
     // tx_clk is (line-rate/40)
@@ -50,9 +48,9 @@ module axi_ad9162(
     // dma interface
     
     dac_clk,
-    dac_valid_0,
-    dac_enable_0,
-    dac_ddata_0,
+    dac_valid,
+    dac_enable,
+    dac_ddata,
     dac_dovf,
     dac_dunf,
     
@@ -88,75 +86,60 @@ module axi_ad9162(
     // jesd interface
     // tx_clk is (line-rate/40)
     
-    input                                     tx_clk;
-    output  [255:0]                           tx_data;
+    input             tx_clk;
+    output  [255:0]   tx_data;
     
     // dma interface
     
-    output                                    dac_clk;
-    output                                    dac_valid_0;
-    output                                    dac_enable_0;
-    input   [255:0]                           dac_ddata_0;
-    input                                     dac_dovf;
-    input                                     dac_dunf;
+    output            dac_clk;
+    output            dac_valid;
+    output            dac_enable;
+    input   [255:0]   dac_ddata;
+    input             dac_dovf;
+    input             dac_dunf;
     
     // axi interface
     
-    input                                     s_axi_aclk;
-    input                                     s_axi_aresetn;
-    input                                     s_axi_awvalid;
-    input   [ 31:0]                           s_axi_awaddr;
-    input   [  2:0]                           s_axi_awprot;
-    output                                    s_axi_awready;
-    input                                     s_axi_wvalid;
-    input   [ 31:0]                           s_axi_wdata;
-    input   [  3:0]                           s_axi_wstrb;
-    output                                    s_axi_wready;
-    output                                    s_axi_bvalid;
-    output  [  1:0]                           s_axi_bresp;
-    input                                     s_axi_bready;
-    input                                     s_axi_arvalid;
-    input   [ 31:0]                           s_axi_araddr;
-    input   [  2:0]                           s_axi_arprot;
-    output                                    s_axi_arready;
-    output                                    s_axi_rvalid;
-    output  [ 31:0]                           s_axi_rdata;
-    output  [  1:0]                           s_axi_rresp;
-    input                                     s_axi_rready;
+    input             s_axi_aclk;
+    input             s_axi_aresetn;
+    input             s_axi_awvalid;
+    input   [ 31:0]   s_axi_awaddr;
+    input   [  2:0]   s_axi_awprot;
+    output            s_axi_awready;
+    input             s_axi_wvalid;
+    input   [ 31:0]   s_axi_wdata;
+    input   [  3:0]   s_axi_wstrb;
+    output            s_axi_wready;
+    output            s_axi_bvalid;
+    output  [  1:0]   s_axi_bresp;
+    input             s_axi_bready;
+    input             s_axi_arvalid;
+    input   [ 31:0]   s_axi_araddr;
+    input   [  2:0]   s_axi_arprot;
+    output            s_axi_arready;
+    output            s_axi_rvalid;
+    output  [ 31:0]   s_axi_rdata;
+    output  [  1:0]   s_axi_rresp;
+    input             s_axi_rready;
     
     // internal clocks and resets
     
-    wire                                      dac_rst;
-    wire                                      up_clk;
-    wire                                      up_rstn;
+    wire              dac_rst;
+    wire              up_clk;
+    wire              up_rstn;
     
     // internal signals
     
-    wire    [255:0]                           tx_data_s;
-    wire    [ 15:0]                           dac_data_0_0_s;
-    wire    [ 15:0]                           dac_data_0_1_s;
-    wire    [ 15:0]                           dac_data_0_2_s;
-    wire    [ 15:0]                           dac_data_0_3_s;
-    wire    [ 15:0]                           dac_data_0_4_s;
-    wire    [ 15:0]                           dac_data_0_5_s;
-    wire    [ 15:0]                           dac_data_0_6_s;
-    wire    [ 15:0]                           dac_data_0_7_s;
-    wire    [ 15:0]                           dac_data_0_8_s;
-    wire    [ 15:0]                           dac_data_0_9_s;
-    wire    [ 15:0]                           dac_data_0_10_s;
-    wire    [ 15:0]                           dac_data_0_11_s;
-    wire    [ 15:0]                           dac_data_0_12_s;
-    wire    [ 15:0]                           dac_data_0_13_s;
-    wire    [ 15:0]                           dac_data_0_14_s;
-    wire    [ 15:0]                           dac_data_0_15_s;
-    wire                                      up_wreq_s;
-    wire    [ 13:0]                           up_waddr_s;
-    wire    [ 31:0]                           up_wdata_s;
-    wire                                      up_wack_s;
-    wire                                      up_rreq_s;
-    wire    [ 13:0]                           up_raddr_s;
-    wire    [ 31:0]                           up_rdata_s;
-    wire                                      up_rack_s;
+    wire    [255:0]   tx_data_s;
+    wire    [255:0]   dac_data_s;
+    wire              up_wreq_s;
+    wire    [ 13:0]   up_waddr_s;
+    wire    [ 31:0]   up_wdata_s;
+    wire              up_wack_s;
+    wire              up_rreq_s;
+    wire    [ 13:0]   up_raddr_s;
+    wire    [ 31:0]   up_rdata_s;
+    wire              up_rack_s;
     
     // signal name changes
     
@@ -171,47 +154,20 @@ module axi_ad9162(
       .tx_data (tx_data_s),
       .dac_clk (dac_clk),
       .dac_rst (dac_rst),
-      .dac_data_0_0 (dac_data_0_0_s),
-      .dac_data_0_1 (dac_data_0_1_s),
-      .dac_data_0_2 (dac_data_0_2_s),
-      .dac_data_0_3 (dac_data_0_3_s),
-      .dac_data_0_4 (dac_data_0_4_s),
-      .dac_data_0_5 (dac_data_0_5_s),
-      .dac_data_0_6 (dac_data_0_6_s),
-      .dac_data_0_7 (dac_data_0_7_s),
-      .dac_data_0_8 (dac_data_0_8_s),
-      .dac_data_0_9 (dac_data_0_9_s),
-      .dac_data_0_10 (dac_data_0_10_s),
-      .dac_data_0_11 (dac_data_0_11_s),
-      .dac_data_0_12 (dac_data_0_12_s),
-      .dac_data_0_13 (dac_data_0_13_s),
-      .dac_data_0_14 (dac_data_0_14_s),
-      .dac_data_0_15 (dac_data_0_15_s));
+      .dac_data (dac_data_s));
     
     // core
     
-    axi_ad9162_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
+    axi_ad9162_core #(
+      .ID (ID),
+      .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
+    i_core (
       .dac_clk (dac_clk),
       .dac_rst (dac_rst),
-      .dac_data_0_0 (dac_data_0_0_s),
-      .dac_data_0_1 (dac_data_0_1_s),
-      .dac_data_0_2 (dac_data_0_2_s),
-      .dac_data_0_3 (dac_data_0_3_s),
-      .dac_data_0_4 (dac_data_0_4_s),
-      .dac_data_0_5 (dac_data_0_5_s),
-      .dac_data_0_6 (dac_data_0_6_s),
-      .dac_data_0_7 (dac_data_0_7_s),
-      .dac_data_0_8 (dac_data_0_8_s),
-      .dac_data_0_9 (dac_data_0_9_s),
-      .dac_data_0_10 (dac_data_0_10_s),
-      .dac_data_0_11 (dac_data_0_11_s),
-      .dac_data_0_12 (dac_data_0_12_s),
-      .dac_data_0_13 (dac_data_0_13_s),
-      .dac_data_0_14 (dac_data_0_14_s),
-      .dac_data_0_15 (dac_data_0_15_s),
-      .dac_valid_0 (dac_valid_0),
-      .dac_enable_0 (dac_enable_0),
-      .dac_ddata_0 (dac_ddata_0),
+      .dac_data (dac_data_s),
+      .dac_valid (dac_valid),
+      .dac_enable (dac_enable),
+      .dac_ddata (dac_ddata),
       .dac_dovf (dac_dovf),
       .dac_dunf (dac_dunf),
       .up_rstn (up_rstn),
@@ -258,3 +214,5 @@ module axi_ad9162(
 
 endmodule
 
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v
index 238107a43..249510144 100644
--- a/library/axi_ad9162/axi_ad9162_channel.v
+++ b/library/axi_ad9162/axi_ad9162_channel.v
@@ -34,12 +34,10 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns / 1ps
 
-module axi_ad9162_channel(
+module axi_ad9162_channel (
 
     // dac interface
     
@@ -74,105 +72,93 @@ module axi_ad9162_channel(
     
     // dac interface
     
-    input           dac_clk;
-    input           dac_rst;
-    output          dac_enable;
-    output  [255:0]  dac_data;
-    input   [255:0]  dma_data;
+    input             dac_clk;
+    input             dac_rst;
+    output            dac_enable;
+    output  [255:0]   dac_data;
+    input   [255:0]   dma_data;
     
     // processor interface
     
-    input           dac_data_sync;
-    input           dac_dds_format;
+    input             dac_data_sync;
+    input             dac_dds_format;
     
     // bus interface
     
-    input           up_rstn;
-    input           up_clk;
-    input           up_wreq;
-    input   [13:0]  up_waddr;
-    input   [31:0]  up_wdata;
-    output          up_wack;
-    input           up_rreq;
-    input   [13:0]  up_raddr;
-    output  [31:0]  up_rdata;
-    output          up_rack;
+    input             up_rstn;
+    input             up_clk;
+    input             up_wreq;
+    input   [ 13:0]   up_waddr;
+    input   [ 31:0]   up_wdata;
+    output            up_wack;
+    input             up_rreq;
+    input   [ 13:0]   up_raddr;
+    output  [ 31:0]   up_rdata;
+    output            up_rack;
     
     // internal registers
     
-    reg              dac_enable = 'd0;
-    reg     [255:0]  dac_data = 'd0;
-    reg     [15: 0]  dac_dds_phase_0_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_0_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_1_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_1_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_2_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_2_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_3_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_3_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_4_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_4_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_5_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_5_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_6_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_6_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_7_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_7_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_8_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_8_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_9_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_9_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_10_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_10_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_11_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_11_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_12_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_12_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_13_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_13_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_14_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_14_1 = 'd0;
-    reg     [15: 0]  dac_dds_phase_15_0 = 'd0;
-    reg     [15: 0]  dac_dds_phase_15_1 = 'd0;
-    reg     [15: 0]  dac_dds_incr_0 = 'd0;
-    reg     [15: 0]  dac_dds_incr_1 = 'd0;
-    reg     [255:0]  dac_dds_data = 'd0;
-    reg     [255:0]  dac_pn7_data = 'd0;
-    reg     [255:0]  dac_pn15_data = 'd0;
+    reg               dac_enable = 'd0;
+    reg     [255:0]   dac_data = 'd0;
+    reg     [255:0]   dac_pn7_data = 'd0;
+    reg     [255:0]   dac_pn15_data = 'd0;
+    reg     [ 15:0]   dac_dds_phase_00_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_00_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_01_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_01_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_02_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_02_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_03_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_03_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_04_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_04_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_05_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_05_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_06_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_06_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_07_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_07_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_08_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_08_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_09_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_09_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_10_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_10_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_11_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_11_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_12_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_12_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_13_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_13_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_14_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_14_1 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_15_0 = 'd0;
+    reg     [ 15:0]   dac_dds_phase_15_1 = 'd0;
+    reg     [ 15:0]   dac_dds_incr_0 = 'd0;
+    reg     [ 15:0]   dac_dds_incr_1 = 'd0;
+    reg     [255:0]   dac_dds_data = 'd0;
     
     // internal signals
     
-    wire    [15: 0]  dac_dds_data_0_s;
-    wire    [15: 0]  dac_dds_data_1_s;
-    wire    [15: 0]  dac_dds_data_2_s;
-    wire    [15: 0]  dac_dds_data_3_s;
-    wire    [15: 0]  dac_dds_data_4_s;
-    wire    [15: 0]  dac_dds_data_5_s;
-    wire    [15: 0]  dac_dds_data_6_s;
-    wire    [15: 0]  dac_dds_data_7_s;
-    wire    [15: 0]  dac_dds_data_8_s;
-    wire    [15: 0]  dac_dds_data_9_s;
-    wire    [15: 0]  dac_dds_data_10_s;
-    wire    [15: 0]  dac_dds_data_11_s;
-    wire    [15: 0]  dac_dds_data_12_s;
-    wire    [15: 0]  dac_dds_data_13_s;
-    wire    [15: 0]  dac_dds_data_14_s;
-    wire    [15: 0]  dac_dds_data_15_s;
-    wire    [15: 0]  dac_dds_scale_1_s;
-    wire    [15: 0]  dac_dds_init_1_s;
-    wire    [15: 0]  dac_dds_incr_1_s;
-    wire    [15: 0]  dac_dds_scale_2_s;
-    wire    [15: 0]  dac_dds_init_2_s;
-    wire    [15: 0]  dac_dds_incr_2_s;
-    wire    [15: 0]  dac_pat_data_1_s;
-    wire    [15: 0]  dac_pat_data_2_s;
-    wire    [ 3: 0]  dac_data_sel_s;
-    wire    [255:0] dac_pn7_data_i_s;
-    wire    [255:0] dac_pn15_data_i_s;
-    wire    [255:0] dac_pn7_data_s;
-    wire    [255:0] dac_pn15_data_s;
+    wire    [ 15:0]   dac_dds_scale_1_s;
+    wire    [ 15:0]   dac_dds_init_1_s;
+    wire    [ 15:0]   dac_dds_incr_1_s;
+    wire    [ 15:0]   dac_dds_scale_2_s;
+    wire    [ 15:0]   dac_dds_init_2_s;
+    wire    [ 15:0]   dac_dds_incr_2_s;
+    wire    [ 15:0]   dac_pat_data_1_s;
+    wire    [ 15:0]   dac_pat_data_2_s;
+    wire    [  3:0]   dac_data_sel_s;
+    wire              dac_iq_mode_s;
+    wire    [255:0]   dac_pn7_data_i_s;
+    wire    [255:0]   dac_pn15_data_i_s;
+    wire    [255:0]   dac_pn7_data_s;
+    wire    [255:0]   dac_pn15_data_s;
+    wire    [255:0]   dac_pat_data_s;
+    wire    [255:0]   dac_dds_data_s;
     
-     
+    genvar n;
+
     // PN7 function
     
     function [255:0] pn7;
@@ -217,13 +203,19 @@ module axi_ad9162_channel(
          end
     endfunction
     
-    assign dac_pn7_data_i_s  = ~dac_pn7_data;
+    assign dac_pn7_data_i_s = ~dac_pn7_data;
     assign dac_pn15_data_i_s = ~dac_pn15_data;
     
-    assign dac_pn7_data_s    = dac_pn7_data;
-    assign dac_pn15_data_s   = dac_pn15_data;
+    assign dac_pn7_data_s = dac_pn7_data;
+    assign dac_pn15_data_s = dac_pn15_data;
+
+    generate
+    for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data
+    assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s;
+    assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s;
+    end
+    endgenerate
     
-     
     // dac data select
     
     always @(posedge dac_clk) begin
@@ -235,14 +227,7 @@ module axi_ad9162_channel(
         4'h4: dac_data <= dac_pn7_data_i_s;
         4'h3: dac_data <= 256'd0;
         4'h2: dac_data <= dma_data;
-        4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
-                            dac_pat_data_2_s, dac_pat_data_1_s,
-                            dac_pat_data_2_s, dac_pat_data_1_s,
-                            dac_pat_data_2_s, dac_pat_data_1_s,
-                            dac_pat_data_2_s, dac_pat_data_1_s,
-                            dac_pat_data_2_s, dac_pat_data_1_s,
-                            dac_pat_data_2_s, dac_pat_data_1_s,
-                            dac_pat_data_2_s, dac_pat_data_1_s};
+        4'h1: dac_data <= dac_pat_data_s;
         default: dac_data <= dac_dds_data;
       endcase
     end
@@ -262,29 +247,101 @@ module axi_ad9162_channel(
     // dds
     
     always @(posedge dac_clk) begin
-      if (dac_data_sync == 1'b1) begin
-        dac_dds_phase_0_0 <= dac_dds_init_1_s;
-        dac_dds_phase_0_1 <= dac_dds_init_2_s;
-        dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
-        dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
-        dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
-        dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
-        dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
-        dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
-        dac_dds_phase_4_0 <= dac_dds_phase_3_0 + dac_dds_incr_1_s;
-        dac_dds_phase_4_1 <= dac_dds_phase_3_1 + dac_dds_incr_2_s;
-        dac_dds_phase_5_0 <= dac_dds_phase_4_0 + dac_dds_incr_1_s;
-        dac_dds_phase_5_1 <= dac_dds_phase_4_1 + dac_dds_incr_2_s;
-        dac_dds_phase_6_0 <= dac_dds_phase_5_0 + dac_dds_incr_1_s;
-        dac_dds_phase_6_1 <= dac_dds_phase_5_1 + dac_dds_incr_2_s;
-        dac_dds_phase_7_0 <= dac_dds_phase_6_0 + dac_dds_incr_1_s;
-        dac_dds_phase_7_1 <= dac_dds_phase_6_1 + dac_dds_incr_2_s;
-        dac_dds_phase_8_0 <= dac_dds_phase_7_0 + dac_dds_incr_1_s;
-        dac_dds_phase_8_1 <= dac_dds_phase_7_1 + dac_dds_incr_2_s;
-        dac_dds_phase_9_0 <= dac_dds_phase_8_0 + dac_dds_incr_1_s;
-        dac_dds_phase_9_1 <= dac_dds_phase_8_1 + dac_dds_incr_2_s;
-        dac_dds_phase_10_0 <= dac_dds_phase_9_0 + dac_dds_incr_1_s;
-        dac_dds_phase_10_1 <= dac_dds_phase_9_1 + dac_dds_incr_2_s;
+      if (dac_data_sync == 1'b0) begin
+        dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
+        dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1;
+        dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0;
+        dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1;
+        dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0;
+        dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1;
+        dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0;
+        dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1;
+        dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0;
+        dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1;
+        dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0;
+        dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1;
+        dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0;
+        dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1;
+        dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0;
+        dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1;
+        dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0;
+        dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1;
+        dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0;
+        dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1;
+        dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0;
+        dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1;
+        dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0;
+        dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1;
+        dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0;
+        dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1;
+        dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0;
+        dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1;
+        dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0;
+        dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1;
+        dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0;
+        dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1;
+        dac_dds_incr_0 <= dac_dds_incr_0;
+        dac_dds_incr_1 <= dac_dds_incr_1;
+        dac_dds_data <= dac_dds_data_s;
+      end else if (dac_iq_mode_s == 1'b1) begin
+        dac_dds_phase_00_0 <= dac_dds_init_1_s;
+        dac_dds_phase_00_1 <= dac_dds_init_2_s;
+        dac_dds_phase_01_0 <= dac_dds_phase_00_0 + 16'h4000;
+        dac_dds_phase_01_1 <= dac_dds_phase_00_1 + 16'h4000;
+        dac_dds_phase_02_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
+        dac_dds_phase_02_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
+        dac_dds_phase_03_0 <= dac_dds_phase_02_0 + 16'h4000;
+        dac_dds_phase_03_1 <= dac_dds_phase_02_1 + 16'h4000;
+        dac_dds_phase_04_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
+        dac_dds_phase_04_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
+        dac_dds_phase_05_0 <= dac_dds_phase_04_0 + 16'h4000;
+        dac_dds_phase_05_1 <= dac_dds_phase_04_1 + 16'h4000;
+        dac_dds_phase_06_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
+        dac_dds_phase_06_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
+        dac_dds_phase_07_0 <= dac_dds_phase_06_0 + 16'h4000;
+        dac_dds_phase_07_1 <= dac_dds_phase_06_1 + 16'h4000;
+        dac_dds_phase_08_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
+        dac_dds_phase_08_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
+        dac_dds_phase_09_0 <= dac_dds_phase_08_0 + 16'h4000;
+        dac_dds_phase_09_1 <= dac_dds_phase_08_1 + 16'h4000;
+        dac_dds_phase_10_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
+        dac_dds_phase_10_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
+        dac_dds_phase_11_0 <= dac_dds_phase_10_0 + 16'h4000;
+        dac_dds_phase_11_1 <= dac_dds_phase_10_1 + 16'h4000;
+        dac_dds_phase_12_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
+        dac_dds_phase_12_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
+        dac_dds_phase_13_0 <= dac_dds_phase_12_0 + 16'h4000;
+        dac_dds_phase_13_1 <= dac_dds_phase_12_1 + 16'h4000;
+        dac_dds_phase_14_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
+        dac_dds_phase_14_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
+        dac_dds_phase_15_0 <= dac_dds_phase_14_0 + 16'h4000;
+        dac_dds_phase_15_1 <= dac_dds_phase_14_1 + 16'h4000;
+        dac_dds_incr_0 <= {dac_dds_incr_1_s[12:0], 3'd0};
+        dac_dds_incr_1 <= {dac_dds_incr_2_s[12:0], 3'd0};
+        dac_dds_data <= 256'd0;
+      end else begin
+        dac_dds_phase_00_0 <= dac_dds_init_1_s;
+        dac_dds_phase_00_1 <= dac_dds_init_2_s;
+        dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
+        dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
+        dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s;
+        dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s;
+        dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
+        dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
+        dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s;
+        dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s;
+        dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
+        dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
+        dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s;
+        dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s;
+        dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
+        dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
+        dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s;
+        dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s;
+        dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
+        dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
+        dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s;
+        dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s;
         dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
         dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
         dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
@@ -298,205 +355,162 @@ module axi_ad9162_channel(
         dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
         dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
         dac_dds_data <= 256'd0;
-      end else begin
-        dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
-        dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
-        dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
-        dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
-        dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
-        dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
-        dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
-        dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
-        dac_dds_phase_4_0 <= dac_dds_phase_4_0 + dac_dds_incr_1_s;
-        dac_dds_phase_4_1 <= dac_dds_phase_4_1 + dac_dds_incr_2_s;
-        dac_dds_phase_5_0 <= dac_dds_phase_5_0 + dac_dds_incr_1_s;
-        dac_dds_phase_5_1 <= dac_dds_phase_5_1 + dac_dds_incr_2_s;
-        dac_dds_phase_6_0 <= dac_dds_phase_6_0 + dac_dds_incr_1_s;
-        dac_dds_phase_6_1 <= dac_dds_phase_6_1 + dac_dds_incr_2_s;
-        dac_dds_phase_7_0 <= dac_dds_phase_7_0 + dac_dds_incr_1_s;
-        dac_dds_phase_7_1 <= dac_dds_phase_7_1 + dac_dds_incr_2_s;
-        dac_dds_phase_8_0 <= dac_dds_phase_8_0 + dac_dds_incr_1_s;
-        dac_dds_phase_8_1 <= dac_dds_phase_8_1 + dac_dds_incr_2_s;
-        dac_dds_phase_9_0 <= dac_dds_phase_9_0 + dac_dds_incr_1_s;
-        dac_dds_phase_9_1 <= dac_dds_phase_9_1 + dac_dds_incr_2_s;
-        dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
-        dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
-        dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
-        dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
-        dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
-        dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
-        dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
-        dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
-        dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
-        dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
-        dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_1_s;
-        dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_2_s;
-        dac_dds_incr_0 <= dac_dds_incr_0;
-        dac_dds_incr_1 <= dac_dds_incr_1;
-        dac_dds_data <= { dac_dds_data_15_s, dac_dds_data_14_s,
-                          dac_dds_data_13_s, dac_dds_data_12_s,
-                          dac_dds_data_11_s, dac_dds_data_10_s,
-                          dac_dds_data_9_s, dac_dds_data_8_s,
-                          dac_dds_data_7_s, dac_dds_data_6_s,
-                          dac_dds_data_5_s, dac_dds_data_4_s,
-                          dac_dds_data_3_s, dac_dds_data_2_s,
-                          dac_dds_data_1_s, dac_dds_data_0_s};
       end
     end
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_0_s = 16'd0;
+    assign dac_dds_data_s[15:0] = 16'd0;
     end else begin
-    ad_dds i_dds_0 (
+    ad_dds i_dds_00 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_0_0),
+      .dds_phase_0 (dac_dds_phase_00_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_0_1),
+      .dds_phase_1 (dac_dds_phase_00_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_0_s));
+      .dds_data (dac_dds_data_s[15:0]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_1_s = 16'd0;
+    assign dac_dds_data_s[31:16] = 16'd0;
     end else begin
-    ad_dds i_dds_1 (
+    ad_dds i_dds_01 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_1_0),
+      .dds_phase_0 (dac_dds_phase_01_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_1_1),
+      .dds_phase_1 (dac_dds_phase_01_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_1_s));
+      .dds_data (dac_dds_data_s[31:16]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_2_s = 16'd0;
+    assign dac_dds_data_s[47:32] = 16'd0;
     end else begin
-    ad_dds i_dds_2 (
+    ad_dds i_dds_02 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_2_0),
+      .dds_phase_0 (dac_dds_phase_02_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_2_1),
+      .dds_phase_1 (dac_dds_phase_02_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_2_s));
+      .dds_data (dac_dds_data_s[47:32]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_3_s = 16'd0;
+    assign dac_dds_data_s[63:48] = 16'd0;
     end else begin
-    ad_dds i_dds_3 (
+    ad_dds i_dds_03 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_3_0),
+      .dds_phase_0 (dac_dds_phase_03_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_3_1),
+      .dds_phase_1 (dac_dds_phase_03_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_3_s));
+      .dds_data (dac_dds_data_s[63:48]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_4_s = 16'd0;
+    assign dac_dds_data_s[79:64] = 16'd0;
     end else begin
-    ad_dds i_dds_4 (
+    ad_dds i_dds_04 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_4_0),
+      .dds_phase_0 (dac_dds_phase_04_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_4_1),
+      .dds_phase_1 (dac_dds_phase_04_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_4_s));
+      .dds_data (dac_dds_data_s[79:64]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_5_s = 16'd0;
+    assign dac_dds_data_s[95:80] = 16'd0;
     end else begin
-    ad_dds i_dds_5 (
+    ad_dds i_dds_05 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_5_0),
+      .dds_phase_0 (dac_dds_phase_05_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_5_1),
+      .dds_phase_1 (dac_dds_phase_05_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_5_s));
+      .dds_data (dac_dds_data_s[95:80]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_6_s = 16'd0;
+    assign dac_dds_data_s[111:96] = 16'd0;
     end else begin
-    ad_dds i_dds_6 (
+    ad_dds i_dds_06 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_6_0),
+      .dds_phase_0 (dac_dds_phase_06_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_6_1),
+      .dds_phase_1 (dac_dds_phase_06_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_6_s));
+      .dds_data (dac_dds_data_s[111:96]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_7_s = 16'd0;
+    assign dac_dds_data_s[127:112] = 16'd0;
     end else begin
-    ad_dds i_dds_7 (
+    ad_dds i_dds_07 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_7_0),
+      .dds_phase_0 (dac_dds_phase_07_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_7_1),
+      .dds_phase_1 (dac_dds_phase_07_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_7_s));
+      .dds_data (dac_dds_data_s[127:112]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_8_s = 16'd0;
+    assign dac_dds_data_s[143:128] = 16'd0;
     end else begin
-    ad_dds i_dds_8 (
+    ad_dds i_dds_08 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_8_0),
+      .dds_phase_0 (dac_dds_phase_08_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_8_1),
+      .dds_phase_1 (dac_dds_phase_08_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_8_s));
+      .dds_data (dac_dds_data_s[143:128]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_9_s = 16'd0;
+    assign dac_dds_data_s[159:144] = 16'd0;
     end else begin
-    ad_dds i_dds_9 (
+    ad_dds i_dds_09 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
-      .dds_phase_0 (dac_dds_phase_9_0),
+      .dds_phase_0 (dac_dds_phase_09_0),
       .dds_scale_0 (dac_dds_scale_1_s),
-      .dds_phase_1 (dac_dds_phase_9_1),
+      .dds_phase_1 (dac_dds_phase_09_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_9_s));
+      .dds_data (dac_dds_data_s[159:144]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_10_s = 16'd0;
+    assign dac_dds_data_s[175:160] = 16'd0;
     end else begin
     ad_dds i_dds_10 (
       .clk (dac_clk),
@@ -505,13 +519,13 @@ module axi_ad9162_channel(
       .dds_scale_0 (dac_dds_scale_1_s),
       .dds_phase_1 (dac_dds_phase_10_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_10_s));
+      .dds_data (dac_dds_data_s[175:160]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_11_s = 16'd0;
+    assign dac_dds_data_s[191:176] = 16'd0;
     end else begin
     ad_dds i_dds_11 (
       .clk (dac_clk),
@@ -520,13 +534,13 @@ module axi_ad9162_channel(
       .dds_scale_0 (dac_dds_scale_1_s),
       .dds_phase_1 (dac_dds_phase_11_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_11_s));
+      .dds_data (dac_dds_data_s[191:176]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_12_s = 16'd0;
+    assign dac_dds_data_s[207:192] = 16'd0;
     end else begin
     ad_dds i_dds_12 (
       .clk (dac_clk),
@@ -535,13 +549,13 @@ module axi_ad9162_channel(
       .dds_scale_0 (dac_dds_scale_1_s),
       .dds_phase_1 (dac_dds_phase_12_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_12_s));
+      .dds_data (dac_dds_data_s[207:192]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_13_s = 16'd0;
+    assign dac_dds_data_s[223:208] = 16'd0;
     end else begin
     ad_dds i_dds_13 (
       .clk (dac_clk),
@@ -550,13 +564,13 @@ module axi_ad9162_channel(
       .dds_scale_0 (dac_dds_scale_1_s),
       .dds_phase_1 (dac_dds_phase_13_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_13_s));
+      .dds_data (dac_dds_data_s[223:208]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_14_s = 16'd0;
+    assign dac_dds_data_s[239:224] = 16'd0;
     end else begin
     ad_dds i_dds_14 (
       .clk (dac_clk),
@@ -565,13 +579,13 @@ module axi_ad9162_channel(
       .dds_scale_0 (dac_dds_scale_1_s),
       .dds_phase_1 (dac_dds_phase_14_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_14_s));
+      .dds_data (dac_dds_data_s[239:224]));
     end
     endgenerate
     
     generate
     if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_15_s = 16'd0;
+    assign dac_dds_data_s[255:240] = 16'd0;
     end else begin
     ad_dds i_dds_15 (
       .clk (dac_clk),
@@ -580,7 +594,7 @@ module axi_ad9162_channel(
       .dds_scale_0 (dac_dds_scale_1_s),
       .dds_phase_1 (dac_dds_phase_15_1),
       .dds_scale_1 (dac_dds_scale_2_s),
-      .dds_data (dac_dds_data_15_s));
+      .dds_data (dac_dds_data_s[255:240]));
     end
     endgenerate
     
@@ -598,6 +612,7 @@ module axi_ad9162_channel(
       .dac_pat_data_1 (dac_pat_data_1_s),
       .dac_pat_data_2 (dac_pat_data_2_s),
       .dac_data_sel (dac_data_sel_s),
+      .dac_iq_mode (dac_iq_mode_s),
       .dac_iqcor_enb (),
       .dac_iqcor_coeff_1 (),
       .dac_iqcor_coeff_2 (),
@@ -628,3 +643,5 @@ module axi_ad9162_channel(
 
 endmodule
 
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v
index 87f9620d2..eea944f67 100644
--- a/library/axi_ad9162/axi_ad9162_core.v
+++ b/library/axi_ad9162/axi_ad9162_core.v
@@ -34,39 +34,22 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns / 1ps
 
-module axi_ad9162_core(
+module axi_ad9162_core (
 
     // dac interface
     
     dac_clk,
     dac_rst,
-    dac_data_0_0,
-    dac_data_0_1,
-    dac_data_0_2,
-    dac_data_0_3,
-    dac_data_0_4,
-    dac_data_0_5,
-    dac_data_0_6,
-    dac_data_0_7,
-    dac_data_0_8,
-    dac_data_0_9,
-    dac_data_0_10,
-    dac_data_0_11,
-    dac_data_0_12,
-    dac_data_0_13,
-    dac_data_0_14,
-    dac_data_0_15,
+    dac_data,
     
     // dma interface
     
-    dac_valid_0,
-    dac_enable_0,
-    dac_ddata_0,
+    dac_valid,
+    dac_enable,
+    dac_ddata,
     dac_dovf,
     dac_dunf,
     
@@ -90,67 +73,52 @@ module axi_ad9162_core(
     
     // dac interface
     
-    input            dac_clk;
-    output           dac_rst;
-    output  [ 15:0]  dac_data_0_0;
-    output  [ 15:0]  dac_data_0_1;
-    output  [ 15:0]  dac_data_0_2;
-    output  [ 15:0]  dac_data_0_3;
-    output  [ 15:0]  dac_data_0_4;
-    output  [ 15:0]  dac_data_0_5;
-    output  [ 15:0]  dac_data_0_6;
-    output  [ 15:0]  dac_data_0_7;
-    output  [ 15:0]  dac_data_0_8;
-    output  [ 15:0]  dac_data_0_9;
-    output  [ 15:0]  dac_data_0_10;
-    output  [ 15:0]  dac_data_0_11;
-    output  [ 15:0]  dac_data_0_12;
-    output  [ 15:0]  dac_data_0_13;
-    output  [ 15:0]  dac_data_0_14;
-    output  [ 15:0]  dac_data_0_15;
+    input             dac_clk;
+    output            dac_rst;
+    output  [255:0]   dac_data;
     
     // dma interface
     
-    output           dac_valid_0;
-    output           dac_enable_0;
-    input   [255:0]  dac_ddata_0;
-    input            dac_dovf;
-    input            dac_dunf;
+    output            dac_valid;
+    output            dac_enable;
+    input   [255:0]   dac_ddata;
+    input             dac_dovf;
+    input             dac_dunf;
     
     
     // processor interface
     
-    input            up_rstn;
-    input            up_clk;
-    input            up_wreq;
-    input   [ 13:0]  up_waddr;
-    input   [ 31:0]  up_wdata;
-    output           up_wack;
-    input            up_rreq;
-    input   [ 13:0]  up_raddr;
-    output  [ 31:0]  up_rdata;
-    output           up_rack;
+    input             up_rstn;
+    input             up_clk;
+    input             up_wreq;
+    input   [ 13:0]   up_waddr;
+    input   [ 31:0]   up_wdata;
+    output            up_wack;
+    input             up_rreq;
+    input   [ 13:0]   up_raddr;
+    output  [ 31:0]   up_rdata;
+    output            up_rack;
     
     // internal registers
     
-    reg     [ 31:0]  up_rdata = 'd0;
-    reg              up_rack = 'd0;
-    reg              up_wack = 'd0;
+    reg     [ 31:0]   up_rdata = 'd0;
+    reg               up_rack = 'd0;
+    reg               up_wack = 'd0;
     
     // internal signals
     
-    wire             dac_sync_s;
-    wire             dac_datafmt_s;
-    wire    [ 31:0]  up_rdata_0_s;
-    wire             up_rack_0_s;
-    wire             up_wack_0_s;
-    wire    [ 31:0]  up_rdata_s;
-    wire             up_rack_s;
-    wire             up_wack_s;
+    wire              dac_sync_s;
+    wire              dac_datafmt_s;
+    wire    [ 31:0]   up_rdata_0_s;
+    wire              up_rack_0_s;
+    wire              up_wack_0_s;
+    wire    [ 31:0]   up_rdata_s;
+    wire              up_rack_s;
+    wire              up_wack_s;
     
     // dac valid
     
-    assign dac_valid_0 = 1'b1;
+    assign dac_valid = 1'b1;
     
     // processor read interface
     
@@ -168,15 +136,15 @@ module axi_ad9162_core(
     
     // dac channel
     
-    axi_ad9162_channel #(.CHANNEL_ID(0), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 (
+    axi_ad9162_channel #(
+      .CHANNEL_ID (0),
+      .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    i_channel_0 (
       .dac_clk (dac_clk),
       .dac_rst (dac_rst),
-      .dac_enable (dac_enable_0),
-      .dac_data ({dac_data_0_15, dac_data_0_14, dac_data_0_13, dac_data_0_12,
-                  dac_data_0_11, dac_data_0_10, dac_data_0_9, dac_data_0_8,
-                  dac_data_0_7, dac_data_0_6, dac_data_0_5, dac_data_0_4,
-                  dac_data_0_3, dac_data_0_2, dac_data_0_1, dac_data_0_0}),
-      .dma_data (dac_ddata_0),
+      .dac_enable (dac_enable),
+      .dac_data (dac_data),
+      .dma_data (dac_ddata),
       .dac_data_sync (dac_sync_s),
       .dac_dds_format (dac_datafmt_s),
       .up_rstn (up_rstn),
@@ -190,7 +158,6 @@ module axi_ad9162_core(
       .up_rdata (up_rdata_0_s),
       .up_rack (up_rack_0_s));
     
-    
     // dac common processor interface
     
     up_dac_common #(.ID(ID)) i_up_dac_common (
@@ -232,3 +199,5 @@ module axi_ad9162_core(
 
 endmodule
 
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v
index 9727a82f2..c1d9cb2a3 100644
--- a/library/axi_ad9162/axi_ad9162_if.v
+++ b/library/axi_ad9162/axi_ad9162_if.v
@@ -34,12 +34,10 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns / 1ps
 
-module axi_ad9162_if(
+module axi_ad9162_if (
 
     // jesd interface
     // tx_clk is (line-rate/40)
@@ -51,95 +49,64 @@ module axi_ad9162_if(
     
     dac_clk,
     dac_rst,
-    dac_data_0_0,
-    dac_data_0_1,
-    dac_data_0_2,
-    dac_data_0_3,
-    dac_data_0_4,
-    dac_data_0_5,
-    dac_data_0_6,
-    dac_data_0_7,
-    dac_data_0_8,
-    dac_data_0_9,
-    dac_data_0_10,
-    dac_data_0_11,
-    dac_data_0_12,
-    dac_data_0_13,
-    dac_data_0_14,
-    dac_data_0_15);
+    dac_data);
     
     // jesd interface
     // tx_clk is (line-rate/40)
     
-    input           tx_clk;
-    output [255:0]  tx_data;
+    input             tx_clk;
+    output  [255:0]   tx_data;
     
     // dac interface
     
-    output          dac_clk;
-    input           dac_rst;
-    input   [15:0]  dac_data_0_0;
-    input   [15:0]  dac_data_0_1;
-    input   [15:0]  dac_data_0_2;
-    input   [15:0]  dac_data_0_3;
-    input   [15:0]  dac_data_0_4;
-    input   [15:0]  dac_data_0_5;
-    input   [15:0]  dac_data_0_6;
-    input   [15:0]  dac_data_0_7;
-    input   [15:0]  dac_data_0_8;
-    input   [15:0]  dac_data_0_9;
-    input   [15:0]  dac_data_0_10;
-    input   [15:0]  dac_data_0_11;
-    input   [15:0]  dac_data_0_12;
-    input   [15:0]  dac_data_0_13;
-    input   [15:0]  dac_data_0_14;
-    input   [15:0]  dac_data_0_15;
-    
+    output            dac_clk;
+    input             dac_rst;
+    input   [255:0]   dac_data;
+
     // internal registers
-    
-    reg    [255:0]  tx_data = 'd0;
+
+    reg     [255:0]   tx_data = 'd0;
     
     // reorder data for the jesd links
     
     assign dac_clk = tx_clk;
-    
-    always @(posedge dac_clk) begin
-      if (dac_rst == 1'b1) begin
-        tx_data <= 256'd0;
-      end else begin
-        tx_data[255:248] <= dac_data_0_15 [ 7: 0];
-        tx_data[247:240] <= dac_data_0_11 [ 7: 0];
-        tx_data[239:232] <= dac_data_0_7  [ 7: 0];
-        tx_data[231:224] <= dac_data_0_3  [ 7: 0];
-        tx_data[223:216] <= dac_data_0_15 [15: 8];
-        tx_data[215:208] <= dac_data_0_11 [15: 8];
-        tx_data[207:200] <= dac_data_0_7  [15: 8];
-        tx_data[199:192] <= dac_data_0_3  [15: 8];
-        tx_data[191:184] <= dac_data_0_14 [ 7: 0];
-        tx_data[183:176] <= dac_data_0_10 [ 7: 0];
-        tx_data[175:168] <= dac_data_0_6  [ 7: 0];
-        tx_data[167:160] <= dac_data_0_2  [ 7: 0];
-        tx_data[159:152] <= dac_data_0_14 [15: 8];
-        tx_data[151:144] <= dac_data_0_10 [15: 8];
-        tx_data[143:136] <= dac_data_0_6  [15: 8];
-        tx_data[135:128] <= dac_data_0_2  [15: 8];
-        tx_data[127:120] <= dac_data_0_13 [ 7: 0];
-        tx_data[119:112] <= dac_data_0_9  [ 7: 0];
-        tx_data[111:104] <= dac_data_0_5  [ 7: 0];
-        tx_data[103: 96] <= dac_data_0_1  [ 7: 0];
-        tx_data[ 95: 88] <= dac_data_0_13 [15: 8];
-        tx_data[ 87: 80] <= dac_data_0_9  [15: 8];
-        tx_data[ 79: 72] <= dac_data_0_5  [15: 8];
-        tx_data[ 71: 64] <= dac_data_0_1  [15: 8];
-        tx_data[ 63: 56] <= dac_data_0_12 [ 7: 0];
-        tx_data[ 55: 48] <= dac_data_0_8  [ 7: 0];
-        tx_data[ 47: 40] <= dac_data_0_4  [ 7: 0];
-        tx_data[ 39: 32] <= dac_data_0_0  [ 7: 0];
-        tx_data[ 31: 24] <= dac_data_0_12 [15: 8];
-        tx_data[ 23: 16] <= dac_data_0_8  [15: 8];
-        tx_data[ 15:  8] <= dac_data_0_4  [15: 8];
-        tx_data[  7:  0] <= dac_data_0_0  [15: 8];
-      end
+
+    always @(posedge tx_clk) begin
+      tx_data[255:248] <= dac_data[247:240];
+      tx_data[247:240] <= dac_data[183:176];
+      tx_data[239:232] <= dac_data[119:112];
+      tx_data[231:224] <= dac_data[ 55: 48];
+      tx_data[223:216] <= dac_data[255:248];
+      tx_data[215:208] <= dac_data[191:184];
+      tx_data[207:200] <= dac_data[127:120];
+      tx_data[199:192] <= dac_data[ 63: 56];
+      tx_data[191:184] <= dac_data[215:208];
+      tx_data[183:176] <= dac_data[151:144];
+      tx_data[175:168] <= dac_data[ 87: 80];
+      tx_data[167:160] <= dac_data[ 23: 16];
+      tx_data[159:152] <= dac_data[223:216];
+      tx_data[151:144] <= dac_data[159:152];
+      tx_data[143:136] <= dac_data[ 95: 88];
+      tx_data[135:128] <= dac_data[ 31: 24];
+      tx_data[127:120] <= dac_data[231:224];
+      tx_data[119:112] <= dac_data[167:160];
+      tx_data[111:104] <= dac_data[103: 96];
+      tx_data[103: 96] <= dac_data[ 39: 32];
+      tx_data[ 95: 88] <= dac_data[239:232];
+      tx_data[ 87: 80] <= dac_data[175:168];
+      tx_data[ 79: 72] <= dac_data[111:104];
+      tx_data[ 71: 64] <= dac_data[ 47: 40];
+      tx_data[ 63: 56] <= dac_data[199:192];
+      tx_data[ 55: 48] <= dac_data[135:128];
+      tx_data[ 47: 40] <= dac_data[ 71: 64];
+      tx_data[ 39: 32] <= dac_data[  7:  0];
+      tx_data[ 31: 24] <= dac_data[207:200];
+      tx_data[ 23: 16] <= dac_data[143:136];
+      tx_data[ 15:  8] <= dac_data[ 79: 72];
+      tx_data[  7:  0] <= dac_data[ 15:  8];
     end
-    
+   
 endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From ced36f6159cf5774af358edef7e3680722ee2a78 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 21 Jul 2016 11:57:03 -0400
Subject: [PATCH 331/972] up-dac- support iq mode

---
 library/common/up_dac_channel.v | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v
index e42f2fc08..7cb96f3e7 100644
--- a/library/common/up_dac_channel.v
+++ b/library/common/up_dac_channel.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -54,6 +52,7 @@ module up_dac_channel (
   dac_pat_data_1,
   dac_pat_data_2,
   dac_data_sel,
+  dac_iq_mode,
   dac_iqcor_enb,
   dac_iqcor_coeff_1,
   dac_iqcor_coeff_2,
@@ -106,6 +105,7 @@ module up_dac_channel (
   output  [15:0]  dac_pat_data_1;
   output  [15:0]  dac_pat_data_2;
   output  [ 3:0]  dac_data_sel;
+  output          dac_iq_mode;
   output          dac_iqcor_enb;
   output  [15:0]  dac_iqcor_coeff_1;
   output  [15:0]  dac_iqcor_coeff_2;
@@ -164,6 +164,7 @@ module up_dac_channel (
   reg     [ 7:0]  up_usr_datatype_bits = 'd0;
   reg     [15:0]  up_usr_interpolation_m = 'd0;
   reg     [15:0]  up_usr_interpolation_n = 'd0;
+  reg             up_dac_iq_mode = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
   reg     [15:0]  up_dac_dds_scale_tc_1 = 'd0;
@@ -223,6 +224,7 @@ module up_dac_channel (
       up_usr_datatype_bits <= 'd0;
       up_usr_interpolation_m <= 'd0;
       up_usr_interpolation_n <= 'd0;
+      up_dac_iq_mode <= 'd0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
@@ -266,6 +268,9 @@ module up_dac_channel (
         up_usr_interpolation_m <= up_wdata[31:16];
         up_usr_interpolation_n <= up_wdata[15:0];
       end
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin
+        up_dac_iq_mode <= up_wdata[0];
+      end
     end
   end
 
@@ -291,6 +296,7 @@ module up_dac_channel (
                               dac_usr_datatype_shift, dac_usr_datatype_total_bits,
                               dac_usr_datatype_bits};
           4'h9: up_rdata <= {dac_usr_interpolation_m, dac_usr_interpolation_n};
+          4'ha: up_rdata <= {31'd0, up_dac_iq_mode};
           default: up_rdata <= 0;
         endcase
       end else begin
@@ -331,10 +337,11 @@ module up_dac_channel (
 
   // dac control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(165)) i_xfer_cntrl (
+  up_xfer_cntrl #(.DATA_WIDTH(166)) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_data_cntrl ({ up_dac_iqcor_enb,
+    .up_data_cntrl ({ up_dac_iq_mode,
+                      up_dac_iqcor_enb,
                       up_dac_iqcor_coeff_tc_1,
                       up_dac_iqcor_coeff_tc_2,
                       up_dac_dds_scale_tc_1,
@@ -349,7 +356,8 @@ module up_dac_channel (
     .up_xfer_done (),
     .d_rst (dac_rst),
     .d_clk (dac_clk),
-    .d_data_cntrl ({  dac_iqcor_enb,
+    .d_data_cntrl ({  dac_iq_mode,
+                      dac_iqcor_enb,
                       dac_iqcor_coeff_1,
                       dac_iqcor_coeff_2,
                       dac_dds_scale_1,

From 4532e5c0cb10f9bc767ca16c67ff70bfaa848c8b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 21 Jul 2016 11:57:40 -0400
Subject: [PATCH 332/972] fmcomms11- support iq mode

---
 projects/fmcomms11/common/fmcomms11_bd.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index 2a753b8f2..59c36419a 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -210,8 +210,8 @@ ad_connect  util_fmcomms11_gt/tx_ip_data axi_ad9162_jesd/tx_tdata
 ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9162_core/tx_clk
 ad_connect  util_fmcomms11_gt/tx_data axi_ad9162_core/tx_data
 ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9162_fifo/dac_clk
-ad_connect  axi_ad9162_core/dac_valid_0 axi_ad9162_fifo/dac_valid
-ad_connect  axi_ad9162_core/dac_ddata_0 axi_ad9162_fifo/dac_data
+ad_connect  axi_ad9162_core/dac_valid axi_ad9162_fifo/dac_valid
+ad_connect  axi_ad9162_core/dac_ddata axi_ad9162_fifo/dac_data
 ad_connect  sys_cpu_clk axi_ad9162_fifo/dma_clk
 ad_connect  sys_cpu_reset axi_ad9162_fifo/dma_rst
 ad_connect  sys_cpu_clk axi_ad9162_dma/m_axis_aclk

From c797a579f1c989da35a5c32cae2381c49eb4ae84 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 13 Jul 2016 15:23:02 -0400
Subject: [PATCH 333/972] util_adxcvr- rstdone on usrclk2

---
 library/util_adxcvr/util_adxcvr_constr.xdc | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 library/util_adxcvr/util_adxcvr_constr.xdc

diff --git a/library/util_adxcvr/util_adxcvr_constr.xdc b/library/util_adxcvr/util_adxcvr_constr.xdc
new file mode 100644
index 000000000..20b13df10
--- /dev/null
+++ b/library/util_adxcvr/util_adxcvr_constr.xdc
@@ -0,0 +1,7 @@
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
+
+set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
+

From 1f25d7f637321abb361dfff3ddd1c0d3e7c7fca1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 15 Jul 2016 10:15:17 -0400
Subject: [PATCH 334/972] axi_adxcvr- self-disable based on num of lanes

---
 library/axi_adxcvr/axi_adxcvr_mdrp.v    | 72 +++++++++++++++++--------
 library/axi_adxcvr/axi_adxcvr_mstatus.v | 17 +++++-
 2 files changed, 64 insertions(+), 25 deletions(-)

diff --git a/library/axi_adxcvr/axi_adxcvr_mdrp.v b/library/axi_adxcvr/axi_adxcvr_mdrp.v
index 25cb7b0a1..4ec6d2db0 100644
--- a/library/axi_adxcvr/axi_adxcvr_mdrp.v
+++ b/library/axi_adxcvr/axi_adxcvr_mdrp.v
@@ -54,43 +54,38 @@ module axi_adxcvr_mdrp (
   // parameters
 
   parameter   integer XCVR_ID = 0;
+  parameter   integer NUM_OF_LANES = 8;
 
   // internal registers
 
-  reg             up_ready_d = 'd0;
   reg     [15:0]  up_rdata_int = 'd0;
   reg             up_ready_int = 'd0;
-  reg     [15:0]  up_rdata_m_in = 'd0;
-  reg             up_ready_m_in = 'd0;
+  reg             up_ready_mi = 'd0;
+  reg     [15:0]  up_rdata_i = 'd0;
+  reg             up_ready_i = 'd0;
   reg     [15:0]  up_rdata_m = 'd0;
   reg             up_ready_m = 'd0;
 
   // internal signals
 
   wire            up_ready_s;
-  wire    [15:0]  up_rdata_m_s;
-  wire            up_ready_m_s;
+  wire    [15:0]  up_rdata_mi_s;
+  wire            up_ready_mi_s;
 
   // disable if not selected
 
   assign up_rdata_out = up_rdata_int;
   assign up_ready_out = up_ready_int;
 
-  assign up_ready_s = up_ready_m & up_ready_m_in;
-  assign up_rdata_m_s = up_rdata_m | up_rdata_m_in;
-  assign up_ready_m_s = up_ready_s & ~up_ready_d;
-
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
-      up_ready_d <= 1'd0;
       up_rdata_int <= 16'd0;
       up_ready_int <= 1'b0;
     end else begin
-      up_ready_d <= up_ready_s;
       case (up_sel)
         8'hff: begin
-          up_rdata_int <= up_rdata_m_s;
-          up_ready_int <= up_ready_m_s;
+          up_rdata_int <= up_rdata_mi_s;
+          up_ready_int <= up_ready_mi_s & ~up_ready_mi;
         end
         XCVR_ID: begin
           up_rdata_int <= up_rdata;
@@ -98,7 +93,7 @@ module axi_adxcvr_mdrp (
         end
         default: begin
           up_rdata_int <= up_rdata_in;
-          up_ready_int <= up_ready_int;
+          up_ready_int <= up_ready_in;
         end
       endcase
     end
@@ -106,18 +101,37 @@ module axi_adxcvr_mdrp (
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
-      up_rdata_m_in <= 16'd0;
-      up_ready_m_in <= 1'b0;
+      up_ready_mi <= 1'b0;
+    end else begin
+      up_ready_mi <= up_ready_mi_s;
+    end
+  end
+
+  assign up_rdata_mi_s = up_rdata_m | up_rdata_i;
+  assign up_ready_mi_s = up_ready_m & up_ready_i;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_rdata_i <= 16'd0;
+      up_ready_i <= 1'b0;
+    end else begin
+      if (up_ready_in == 1'b1) begin
+        up_rdata_i <= up_rdata_in;
+        up_ready_i <= 1'b1;
+      end else if (up_enb == 1'b1) begin
+        up_rdata_i <= 16'd0;
+        up_ready_i <= 1'b0;
+      end
+    end
+  end
+
+  generate
+  if (XCVR_ID < NUM_OF_LANES) begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
       up_rdata_m <= 16'd0;
       up_ready_m <= 1'b0;
     end else begin
-      if (up_ready_in == 1'b1) begin
-        up_rdata_m_in <= up_rdata_in;
-        up_ready_m_in <= 1'b1;
-      end else if (up_enb == 1'b1) begin
-        up_rdata_m_in <= 16'd0;
-        up_ready_m_in <= 1'b0;
-      end
       if (up_ready == 1'b1) begin
         up_rdata_m <= up_rdata;
         up_ready_m <= 1'b1;
@@ -127,6 +141,18 @@ module axi_adxcvr_mdrp (
       end
     end
   end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_rdata_m <= 16'd0;
+      up_ready_m <= 1'b0;
+    end else begin
+      up_rdata_m <= 16'd0;
+      up_ready_m <= 1'b1;
+    end
+  end
+  end
+  endgenerate
 
 endmodule     
 
diff --git a/library/axi_adxcvr/axi_adxcvr_mstatus.v b/library/axi_adxcvr/axi_adxcvr_mstatus.v
index 52079d0e8..2319886da 100644
--- a/library/axi_adxcvr/axi_adxcvr_mstatus.v
+++ b/library/axi_adxcvr/axi_adxcvr_mstatus.v
@@ -49,23 +49,36 @@ module axi_adxcvr_mstatus (
   output          up_pll_locked_out,
   output          up_rst_done_out);
 
+  // parameters
+
+  parameter   integer XCVR_ID = 0;
+  parameter   integer NUM_OF_LANES = 8;
+
   // internal registers
 
   reg             up_pll_locked_int = 'd0;
   reg             up_rst_done_int = 'd0;
 
+  // internal signals
+
+  wire            up_pll_locked_s;
+  wire            up_rst_done_s;
+
   // daisy-chain the signals
 
   assign up_pll_locked_out = up_pll_locked_int;
   assign up_rst_done_out = up_rst_done_int;
 
+  assign up_pll_locked_s = (XCVR_ID < NUM_OF_LANES) ? up_pll_locked : 1'b1;
+  assign up_rst_done_s = (XCVR_ID < NUM_OF_LANES) ? up_rst_done : 1'b1;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
       up_pll_locked_int <= 1'd0;
       up_rst_done_int <= 1'd0;
     end else begin
-      up_pll_locked_int <= up_pll_locked_in & up_pll_locked;
-      up_rst_done_int <= up_rst_done_in & up_rst_done;
+      up_pll_locked_int <= up_pll_locked_in & up_pll_locked_s;
+      up_rst_done_int <= up_rst_done_in & up_rst_done_s;
     end
   end
 

From 8e04e70791f8a65bde59183257ee3b0b57834a60 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 15 Jul 2016 10:15:56 -0400
Subject: [PATCH 335/972] axi_adxcvr- status output for jesd ip

---
 library/axi_adxcvr/axi_adxcvr.v      | 262 +++++++++++++++++++++------
 library/axi_adxcvr/axi_adxcvr_ip.tcl |   4 +
 library/axi_adxcvr/axi_adxcvr_up.v   |  16 +-
 3 files changed, 225 insertions(+), 57 deletions(-)

diff --git a/library/axi_adxcvr/axi_adxcvr.v b/library/axi_adxcvr/axi_adxcvr.v
index 33e1074fc..909ac93f3 100644
--- a/library/axi_adxcvr/axi_adxcvr.v
+++ b/library/axi_adxcvr/axi_adxcvr.v
@@ -474,6 +474,7 @@ module axi_adxcvr (
 
   input           axi_clk,
   input           axi_aresetn,
+  output          up_status,
 
   input           s_axi_awvalid,
   input   [31:0]  s_axi_awaddr,
@@ -685,7 +686,10 @@ module axi_adxcvr (
   assign up_cm_wr_0 = up_cm_wr;
   assign up_cm_wdata_0 = up_cm_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(0)) i_mdrp_cm_0 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (0),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_cm_0 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_cm_sel),
@@ -703,7 +707,10 @@ module axi_adxcvr (
   assign up_es_wr_0 = up_es_wr;
   assign up_es_wdata_0 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(0)) i_mdrp_es_0 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (0),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_0 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -723,7 +730,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_0 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_0 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_0 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (0),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_0 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (1'd1),
@@ -739,7 +749,10 @@ module axi_adxcvr (
   assign up_ch_wr_0 = up_ch_wr;
   assign up_ch_wdata_0 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(0)) i_mdrp_ch_0 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (0),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_0 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -757,7 +770,10 @@ module axi_adxcvr (
   assign up_es_wr_1 = up_es_wr;
   assign up_es_wdata_1 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(1)) i_mdrp_es_1 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (1),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_1 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -777,7 +793,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_1 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_1 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_1 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (1),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_1 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_0_s),
@@ -793,7 +812,10 @@ module axi_adxcvr (
   assign up_ch_wr_1 = up_ch_wr;
   assign up_ch_wdata_1 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(1)) i_mdrp_ch_1 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (1),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_1 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -811,7 +833,10 @@ module axi_adxcvr (
   assign up_es_wr_2 = up_es_wr;
   assign up_es_wdata_2 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(2)) i_mdrp_es_2 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (2),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_2 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -831,7 +856,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_2 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_2 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_2 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (2),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_2 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_1_s),
@@ -847,7 +875,10 @@ module axi_adxcvr (
   assign up_ch_wr_2 = up_ch_wr;
   assign up_ch_wdata_2 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(2)) i_mdrp_ch_2 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (2),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_2 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -865,7 +896,10 @@ module axi_adxcvr (
   assign up_es_wr_3 = up_es_wr;
   assign up_es_wdata_3 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(3)) i_mdrp_es_3 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (3),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_3 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -885,7 +919,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_3 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_3 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_3 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (3),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_3 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_2_s),
@@ -901,7 +938,10 @@ module axi_adxcvr (
   assign up_ch_wr_3 = up_ch_wr;
   assign up_ch_wdata_3 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(3)) i_mdrp_ch_3 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (3),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_3 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -919,7 +959,10 @@ module axi_adxcvr (
   assign up_cm_wr_4 = up_cm_wr;
   assign up_cm_wdata_4 = up_cm_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(4)) i_mdrp_cm_4 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (4),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_cm_4 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_cm_sel),
@@ -937,7 +980,10 @@ module axi_adxcvr (
   assign up_es_wr_4 = up_es_wr;
   assign up_es_wdata_4 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(4)) i_mdrp_es_4 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (4),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_4 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -957,7 +1003,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_4 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_4 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_4 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (4),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_4 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_3_s),
@@ -973,7 +1022,10 @@ module axi_adxcvr (
   assign up_ch_wr_4 = up_ch_wr;
   assign up_ch_wdata_4 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(4)) i_mdrp_ch_4 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (4),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_4 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -991,7 +1043,10 @@ module axi_adxcvr (
   assign up_es_wr_5 = up_es_wr;
   assign up_es_wdata_5 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(5)) i_mdrp_es_5 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (5),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_5 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1011,7 +1066,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_5 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_5 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_5 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (5),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_5 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_4_s),
@@ -1027,7 +1085,10 @@ module axi_adxcvr (
   assign up_ch_wr_5 = up_ch_wr;
   assign up_ch_wdata_5 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(5)) i_mdrp_ch_5 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (5),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_5 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1045,7 +1106,10 @@ module axi_adxcvr (
   assign up_es_wr_6 = up_es_wr;
   assign up_es_wdata_6 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(6)) i_mdrp_es_6 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (6),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_6 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1065,7 +1129,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_6 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_6 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_6 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (6),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_6 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_5_s),
@@ -1081,7 +1148,10 @@ module axi_adxcvr (
   assign up_ch_wr_6 = up_ch_wr;
   assign up_ch_wdata_6 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(6)) i_mdrp_ch_6 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (6),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_6 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1099,7 +1169,10 @@ module axi_adxcvr (
   assign up_es_wr_7 = up_es_wr;
   assign up_es_wdata_7 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(7)) i_mdrp_es_7 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (7),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_7 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1119,7 +1192,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_7 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_7 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_7 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (7),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_7 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_6_s),
@@ -1135,7 +1211,10 @@ module axi_adxcvr (
   assign up_ch_wr_7 = up_ch_wr;
   assign up_ch_wdata_7 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(7)) i_mdrp_ch_7 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (7),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_7 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1153,7 +1232,10 @@ module axi_adxcvr (
   assign up_cm_wr_8 = up_cm_wr;
   assign up_cm_wdata_8 = up_cm_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(8)) i_mdrp_cm_8 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (8),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_cm_8 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_cm_sel),
@@ -1171,7 +1253,10 @@ module axi_adxcvr (
   assign up_es_wr_8 = up_es_wr;
   assign up_es_wdata_8 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(8)) i_mdrp_es_8 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (8),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_8 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1191,7 +1276,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_8 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_8 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_8 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (8),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_8 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_7_s),
@@ -1207,7 +1295,10 @@ module axi_adxcvr (
   assign up_ch_wr_8 = up_ch_wr;
   assign up_ch_wdata_8 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(8)) i_mdrp_ch_8 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (8),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_8 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1225,7 +1316,10 @@ module axi_adxcvr (
   assign up_es_wr_9 = up_es_wr;
   assign up_es_wdata_9 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(9)) i_mdrp_es_9 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (9),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_9 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1245,7 +1339,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_9 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_9 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_9 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (9),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_9 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_8_s),
@@ -1261,7 +1358,10 @@ module axi_adxcvr (
   assign up_ch_wr_9 = up_ch_wr;
   assign up_ch_wdata_9 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(9)) i_mdrp_ch_9 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (9),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_9 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1279,7 +1379,10 @@ module axi_adxcvr (
   assign up_es_wr_10 = up_es_wr;
   assign up_es_wdata_10 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(10)) i_mdrp_es_10 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (10),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_10 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1299,7 +1402,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_10 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_10 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_10 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (10),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_10 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_9_s),
@@ -1315,7 +1421,10 @@ module axi_adxcvr (
   assign up_ch_wr_10 = up_ch_wr;
   assign up_ch_wdata_10 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(10)) i_mdrp_ch_10 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (10),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_10 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1333,7 +1442,10 @@ module axi_adxcvr (
   assign up_es_wr_11 = up_es_wr;
   assign up_es_wdata_11 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(11)) i_mdrp_es_11 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (11),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_11 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1353,7 +1465,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_11 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_11 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_11 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (11),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_11 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_10_s),
@@ -1369,7 +1484,10 @@ module axi_adxcvr (
   assign up_ch_wr_11 = up_ch_wr;
   assign up_ch_wdata_11 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(11)) i_mdrp_ch_11 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (11),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_11 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1387,7 +1505,10 @@ module axi_adxcvr (
   assign up_cm_wr_12 = up_cm_wr;
   assign up_cm_wdata_12 = up_cm_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(12)) i_mdrp_cm_12 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (12),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_cm_12 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_cm_sel),
@@ -1405,7 +1526,10 @@ module axi_adxcvr (
   assign up_es_wr_12 = up_es_wr;
   assign up_es_wdata_12 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(12)) i_mdrp_es_12 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (12),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_12 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1425,7 +1549,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_12 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_12 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_12 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (12),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_12 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_11_s),
@@ -1441,7 +1568,10 @@ module axi_adxcvr (
   assign up_ch_wr_12 = up_ch_wr;
   assign up_ch_wdata_12 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(12)) i_mdrp_ch_12 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (12),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_12 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1459,7 +1589,10 @@ module axi_adxcvr (
   assign up_es_wr_13 = up_es_wr;
   assign up_es_wdata_13 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(13)) i_mdrp_es_13 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (13),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_13 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1479,7 +1612,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_13 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_13 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_13 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (13),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_13 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_12_s),
@@ -1495,7 +1631,10 @@ module axi_adxcvr (
   assign up_ch_wr_13 = up_ch_wr;
   assign up_ch_wdata_13 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(13)) i_mdrp_ch_13 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (13),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_13 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1513,7 +1652,10 @@ module axi_adxcvr (
   assign up_es_wr_14 = up_es_wr;
   assign up_es_wdata_14 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(14)) i_mdrp_es_14 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (14),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_14 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1533,7 +1675,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_14 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_14 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_14 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (14),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_14 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_13_s),
@@ -1549,7 +1694,10 @@ module axi_adxcvr (
   assign up_ch_wr_14 = up_ch_wr;
   assign up_ch_wdata_14 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(14)) i_mdrp_ch_14 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (14),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_14 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1567,7 +1715,10 @@ module axi_adxcvr (
   assign up_es_wr_15 = up_es_wr;
   assign up_es_wdata_15 = up_es_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(15)) i_mdrp_es_15 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (15),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_es_15 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1587,7 +1738,10 @@ module axi_adxcvr (
   assign up_ch_sys_clk_sel_15 = up_ch_sys_clk_sel;
   assign up_ch_out_clk_sel_15 = up_ch_out_clk_sel;
 
-  axi_adxcvr_mstatus i_mstatus_ch_15 (
+  axi_adxcvr_mstatus #(
+    .XCVR_ID (15),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mstatus_ch_15 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_14_s),
@@ -1603,7 +1757,10 @@ module axi_adxcvr (
   assign up_ch_wr_15 = up_ch_wr;
   assign up_ch_wdata_15 = up_ch_wdata;
 
-  axi_adxcvr_mdrp #(.XCVR_ID(15)) i_mdrp_ch_15 (
+  axi_adxcvr_mdrp #(
+    .XCVR_ID (15),
+    .NUM_OF_LANES (NUM_OF_LANES))
+  i_mdrp_ch_15 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1701,6 +1858,7 @@ module axi_adxcvr (
     .up_es_hstep (up_es_hstep),
     .up_es_saddr (up_es_saddr),
     .up_es_status (up_es_status),
+    .up_status (up_status),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq),
diff --git a/library/axi_adxcvr/axi_adxcvr_ip.tcl b/library/axi_adxcvr/axi_adxcvr_ip.tcl
index fbfb42ef2..b4dc7583b 100644
--- a/library/axi_adxcvr/axi_adxcvr_ip.tcl
+++ b/library/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -116,6 +116,10 @@ for {set n 0} {$n < 16} {incr n} {
 
 }
 
+set_property enablement_dependency \
+  {spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \
+  [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
+
 set_property enablement_dependency \
   {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
   (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
diff --git a/library/axi_adxcvr/axi_adxcvr_up.v b/library/axi_adxcvr/axi_adxcvr_up.v
index 94551a00e..afff578c5 100644
--- a/library/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/axi_adxcvr/axi_adxcvr_up.v
@@ -84,6 +84,10 @@ module axi_adxcvr_up (
   output  [31:0]  up_es_saddr,
   input           up_es_status,
 
+  // status
+
+  output          up_status,
+
   // bus interface
 
   input           up_rstn,
@@ -112,7 +116,7 @@ module axi_adxcvr_up (
   reg     [ 3:0]  up_pll_rst_cnt = 'd0;
   reg     [ 3:0]  up_rst_cnt = 'd0;
   reg     [ 6:0]  up_user_ready_cnt = 'd0;
-  reg             up_status = 'd0;
+  reg             up_status_int = 'd0;
   reg             up_lpm_dfe_n = 'd0;
   reg     [ 2:0]  up_rate = 'd0;
   reg     [ 1:0]  up_sys_clk_sel = 'd0;
@@ -177,13 +181,14 @@ module axi_adxcvr_up (
   assign up_ch_pll_rst = up_pll_rst_cnt[3];
   assign up_ch_rst = up_rst_cnt[3];
   assign up_ch_user_ready = up_user_ready_cnt[6];
+  assign up_status = up_status_int;
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_pll_rst_cnt <= 4'h8;
       up_rst_cnt <= 4'h8;
       up_user_ready_cnt <= 7'h00;
-      up_status <= 1'b0;
+      up_status_int <= 1'b0;
     end else begin
       if (up_resetn == 1'b0) begin
         up_pll_rst_cnt <= 4'h8;
@@ -202,9 +207,9 @@ module axi_adxcvr_up (
         up_user_ready_cnt <= up_user_ready_cnt + 1'b1;
       end
       if (up_resetn == 1'b0) begin
-        up_status <= 1'b0;
+        up_status_int <= 1'b0;
       end else if (up_ch_rst_done == 1'b1) begin
-        up_status <= 1'b1;
+        up_status_int <= 1'b1;
       end
     end
   end
@@ -453,7 +458,8 @@ module axi_adxcvr_up (
           10'h001: up_rdata_d <= ID;
           10'h002: up_rdata_d <= up_scratch;
           10'h004: up_rdata_d <= {31'd0, up_resetn};
-          10'h005: up_rdata_d <= {31'd0, up_status};
+          10'h005: up_rdata_d <= {31'd0, up_status_int};
+          10'h006: up_rdata_d <= {17'd0, up_user_ready_cnt, up_rst_cnt, up_pll_rst_cnt};
           10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel};
           10'h010: up_rdata_d <= {24'd0, up_icm_sel};
           10'h011: up_rdata_d <= {3'd0, up_icm_wr, up_icm_addr, up_icm_wdata};

From 1435c5f7f7aef5527ad1c12f61ef566dd58ab53b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 15 Jul 2016 10:18:34 -0400
Subject: [PATCH 336/972] util_adxcvr- add clock buffers, rst-done, rate on
 usrclk

---
 library/util_adxcvr/util_adxcvr_xch.v | 66 ++++++++++++++++++++++-----
 1 file changed, 54 insertions(+), 12 deletions(-)

diff --git a/library/util_adxcvr/util_adxcvr_xch.v b/library/util_adxcvr/util_adxcvr_xch.v
index a4b303aa9..f183f7da2 100644
--- a/library/util_adxcvr/util_adxcvr_xch.v
+++ b/library/util_adxcvr/util_adxcvr_xch.v
@@ -139,6 +139,14 @@ module util_adxcvr_xch (
   reg     [11:0]  up_addr_int = 'd0;
   reg             up_wr_int = 'd0;
   reg     [15:0]  up_wdata_int = 'd0;
+  reg             up_rx_rst_done_m1 = 'd0;
+  reg             up_rx_rst_done_m2 = 'd0;
+  reg             up_tx_rst_done_m1 = 'd0;
+  reg             up_tx_rst_done_m2 = 'd0;
+  reg     [ 2:0]  rx_rate_m1 = 'd0;
+  reg     [ 2:0]  rx_rate_m2 = 'd0;
+  reg     [ 2:0]  tx_rate_m1 = 'd0;
+  reg     [ 2:0]  tx_rate_m2 = 'd0;
 
   // internal signals
 
@@ -149,7 +157,11 @@ module util_adxcvr_xch (
   wire    [15:0]  up_rdata_s;
   wire            up_ready_s;
   wire    [ 1:0]  rx_sys_clk_sel_s;
+  wire            rx_out_clk_s;
+  wire            rx_rst_done_s;
   wire    [ 1:0]  tx_sys_clk_sel_s;
+  wire            tx_out_clk_s;
+  wire            tx_rst_done_s;
   wire    [ 1:0]  rx_pll_clk_sel_s;
   wire    [ 1:0]  tx_pll_clk_sel_s;
   wire    [ 3:0]  rx_charisk_open_s;
@@ -253,8 +265,38 @@ module util_adxcvr_xch (
     end
   end
 
+  assign up_rx_rst_done = up_rx_rst_done_m2;
+  assign up_tx_rst_done = up_tx_rst_done_m2;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_rx_rst_done_m1 <= 'd0;
+      up_rx_rst_done_m2 <= 'd0;
+      up_tx_rst_done_m1 <= 'd0;
+      up_tx_rst_done_m2 <= 'd0;
+    end else begin
+      up_rx_rst_done_m1 <= rx_rst_done_s;
+      up_rx_rst_done_m2 <= up_rx_rst_done_m1;
+      up_tx_rst_done_m1 <= tx_rst_done_s;
+      up_tx_rst_done_m2 <= up_tx_rst_done_m1;
+    end
+  end
+
+  always @(posedge rx_clk) begin
+    rx_rate_m1 <= up_rx_rate;
+    rx_rate_m2 <= rx_rate_m1;
+  end
+
+  always @(posedge tx_clk) begin
+    tx_rate_m1 <= up_tx_rate;
+    tx_rate_m2 <= tx_rate_m1;
+  end
+
   // instantiations
 
+  BUFG i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk));
+  BUFG i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk));
+
   generate
   if (GTH_OR_GTX_N == 0) begin
   assign rx_sys_clk_sel_s = up_rx_sys_clk_sel;
@@ -506,7 +548,7 @@ module util_adxcvr_xch (
     .TX8B10BEN (1'd1),
     .LOOPBACK (3'd0),
     .PHYSTATUS (),
-    .RXRATE (up_rx_rate),
+    .RXRATE (rx_rate_m2),
     .RXVALID (),
     .RXPD (2'b00),
     .TXPD (2'b00),
@@ -596,7 +638,7 @@ module util_adxcvr_xch (
     .RXLPMHFOVRDEN (1'd0),
     .RXLPMLFHOLD (1'd0),
     .RXRATEDONE (),
-    .RXOUTCLK (rx_out_clk),
+    .RXOUTCLK (rx_out_clk_s),
     .RXOUTCLKFABRIC (),
     .RXOUTCLKPCS (),
     .RXOUTCLKSEL (up_rx_out_clk_sel),
@@ -620,7 +662,7 @@ module util_adxcvr_xch (
     .RXCHARISCOMMA (),
     .RXCHARISK ({rx_charisk_open_s, rx_charisk}),
     .RXCHBONDI (5'd0),
-    .RXRESETDONE (up_rx_rst_done),
+    .RXRESETDONE (rx_rst_done_s),
     .RXQPIEN (1'd0),
     .RXQPISENN (),
     .RXQPISENP (),
@@ -644,7 +686,7 @@ module util_adxcvr_xch (
     .TXUSRCLK2 (tx_clk),
     .TXELECIDLE (1'd0),
     .TXMARGIN (3'd0),
-    .TXRATE (up_tx_rate),
+    .TXRATE (tx_rate_m2),
     .TXSWING (1'd0),
     .TXPRBSFORCEERR (1'd0),
     .TXDLYBYPASS (1'd1),
@@ -673,7 +715,7 @@ module util_adxcvr_xch (
     .TXDATA ({32'd0, tx_data}),
     .GTXTXP (tx_p),
     .GTXTXN (tx_n),
-    .TXOUTCLK (tx_out_clk),
+    .TXOUTCLK (tx_out_clk_s),
     .TXOUTCLKFABRIC (),
     .TXOUTCLKPCS (),
     .TXOUTCLKSEL (up_tx_out_clk_sel),
@@ -685,7 +727,7 @@ module util_adxcvr_xch (
     .TXSTARTSEQ (1'd0),
     .TXPCSRESET (1'd0),
     .TXPMARESET (1'd0),
-    .TXRESETDONE (up_tx_rst_done),
+    .TXRESETDONE (tx_rst_done_s),
     .TXCOMFINISH (),
     .TXCOMINIT (1'd0),
     .TXCOMSAS (1'd0),
@@ -1249,7 +1291,7 @@ module util_adxcvr_xch (
     .RXPRBSSEL (4'd0),
     .RXPROGDIVRESET (1'd0),
     .RXQPIEN (1'd0),
-    .RXRATE (up_rx_rate),
+    .RXRATE (rx_rate_m2),
     .RXRATEMODE (1'd0),
     .RXSLIDE (1'd0),
     .RXSLIPOUTCLK (1'd0),
@@ -1319,7 +1361,7 @@ module util_adxcvr_xch (
     .TXQPIBIASEN (1'd0),
     .TXQPISTRONGPDOWN (1'd0),
     .TXQPIWEAKPUP (1'd0),
-    .TXRATE (up_tx_rate),
+    .TXRATE (tx_rate_m2),
     .TXRATEMODE (1'd0),
     .TXSEQUENCE (7'd0),
     .TXSWING (1'd0),
@@ -1390,7 +1432,7 @@ module util_adxcvr_xch (
     .RXOSINTSTARTED (),
     .RXOSINTSTROBEDONE (),
     .RXOSINTSTROBESTARTED (),
-    .RXOUTCLK (rx_out_clk),
+    .RXOUTCLK (rx_out_clk_s),
     .RXOUTCLKFABRIC (),
     .RXOUTCLKPCS (),
     .RXPHALIGNDONE (),
@@ -1403,7 +1445,7 @@ module util_adxcvr_xch (
     .RXQPISENP (),
     .RXRATEDONE (),
     .RXRECCLKOUT (),
-    .RXRESETDONE (up_rx_rst_done),
+    .RXRESETDONE (rx_rst_done_s),
     .RXSLIDERDY (),
     .RXSLIPDONE (),
     .RXSLIPOUTCLKRDY (),
@@ -1416,7 +1458,7 @@ module util_adxcvr_xch (
     .TXBUFSTATUS (),
     .TXCOMFINISH (),
     .TXDLYSRESETDONE (),
-    .TXOUTCLK (tx_out_clk),
+    .TXOUTCLK (tx_out_clk_s),
     .TXOUTCLKFABRIC (),
     .TXOUTCLKPCS (),
     .TXPHALIGNDONE (),
@@ -1426,7 +1468,7 @@ module util_adxcvr_xch (
     .TXQPISENN (),
     .TXQPISENP (),
     .TXRATEDONE (),
-    .TXRESETDONE (up_tx_rst_done),
+    .TXRESETDONE (tx_rst_done_s),
     .TXSYNCDONE (),
     .TXSYNCOUT ());
   end

From 75864f0ce58a28b692b42f5dd9dd310557d209f7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 15 Jul 2016 10:19:48 -0400
Subject: [PATCH 337/972] util_adxcvr- add constraints file

---
 library/util_adxcvr/util_adxcvr.v          | 12 ++++++------
 library/util_adxcvr/util_adxcvr_constr.xdc |  4 ++++
 library/util_adxcvr/util_adxcvr_ip.tcl     |  2 ++
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/library/util_adxcvr/util_adxcvr.v b/library/util_adxcvr/util_adxcvr.v
index 9f14027eb..c876c4647 100644
--- a/library/util_adxcvr/util_adxcvr.v
+++ b/library/util_adxcvr/util_adxcvr.v
@@ -1026,15 +1026,15 @@ module util_adxcvr (
   parameter   integer GTH_OR_GTX_N = 0;
   parameter   integer CPLL_TX_OR_RX_N = 0;
   parameter   integer CPLL_FBDIV = 2;
-  parameter   integer QPLL_REFCLK_DIV = 2;
+  parameter   integer QPLL_REFCLK_DIV = 1;
   parameter   integer QPLL_FBDIV_RATIO = 1;
   parameter   integer RX_OUT_DIV = 1;
-  parameter   integer RX_CLK25_DIV = 10;
+  parameter   integer RX_CLK25_DIV = 20;
   parameter   integer TX_OUT_DIV = 1;
-  parameter   integer TX_CLK25_DIV = 10;
-  parameter   [31:0]  PMA_RSV = 32'h00018480;
-  parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff20400020;
-  parameter   [26:0]  QPLL_CFG = 27'h06801C1;
+  parameter   integer TX_CLK25_DIV = 20;
+  parameter   [31:0]  PMA_RSV = 32'h001e7080;
+  parameter   [72:0]  RX_CDR_CFG = 72'h0b000023ff10400020;
+  parameter   [26:0]  QPLL_CFG = 27'h0680181;
   parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000;
 
   localparam  integer NUM_OF_LANES = (TX_NUM_OF_LANES > RX_NUM_OF_LANES) ?
diff --git a/library/util_adxcvr/util_adxcvr_constr.xdc b/library/util_adxcvr/util_adxcvr_constr.xdc
index 20b13df10..92336c93a 100644
--- a/library/util_adxcvr/util_adxcvr_constr.xdc
+++ b/library/util_adxcvr/util_adxcvr_constr.xdc
@@ -1,7 +1,11 @@
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
 set_property shreg_extract no [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_rate*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_rate*}]
 
 set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
 set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}]
 
diff --git a/library/util_adxcvr/util_adxcvr_ip.tcl b/library/util_adxcvr/util_adxcvr_ip.tcl
index 0162c5f78..d73da5444 100644
--- a/library/util_adxcvr/util_adxcvr_ip.tcl
+++ b/library/util_adxcvr/util_adxcvr_ip.tcl
@@ -5,11 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create util_adxcvr
 adi_ip_files util_adxcvr [list \
+  "util_adxcvr_constr.xdc" \
   "util_adxcvr_xcm.v" \
   "util_adxcvr_xch.v" \
   "util_adxcvr.v" ]
 
 adi_ip_properties_lite util_adxcvr
+adi_ip_constraints util_adxcvr "util_adxcvr_constr.xdc"
 
 ipx::remove_all_bus_interface [ipx::current_core]
 

From db6d5f509f92e9610ccf626dbfa00cb259606005 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 15 Jul 2016 18:31:15 -0400
Subject: [PATCH 338/972] library/common- xcvr interface logic

---
 library/common/ad_xcvr_rx_if.v | 127 +++++++++++++++++++++++++++++++++
 1 file changed, 127 insertions(+)
 create mode 100644 library/common/ad_xcvr_rx_if.v

diff --git a/library/common/ad_xcvr_rx_if.v b/library/common/ad_xcvr_rx_if.v
new file mode 100644
index 000000000..a53052706
--- /dev/null
+++ b/library/common/ad_xcvr_rx_if.v
@@ -0,0 +1,127 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_xcvr_rx_if (
+
+  // jesd interface
+
+  rx_clk,
+  rx_ip_sof,
+  rx_ip_data,
+  rx_sof,
+  rx_data);
+
+  // parameter
+
+  parameter DEVICE_TYPE = 0;
+
+  // jesd interface
+
+  input           rx_clk;
+  input   [ 3:0]  rx_ip_sof;
+  input   [31:0]  rx_ip_data;
+
+  // aligned data
+
+  output          rx_sof;
+  output  [31:0]  rx_data;
+
+  // internal registers
+
+  reg     [31:0]  rx_ip_data_d = 'd0;
+  reg     [ 3:0]  rx_ip_sof_hold = 'd0;
+  reg             rx_sof = 'd0;
+  reg             rx_ip_sof_d = 'd0;
+  reg     [31:0]  rx_data = 'd0;
+
+  // internal signals
+
+  wire    [ 3:0]  rx_ip_sof_s;
+  wire    [31:0]  rx_ip_data_s;
+
+  // altera/xilinx
+
+  generate
+  if (DEVICE_TYPE == 1) begin
+  assign rx_ip_sof_s[3] = rx_ip_sof[0];
+  assign rx_ip_sof_s[2] = rx_ip_sof[1];
+  assign rx_ip_sof_s[1] = rx_ip_sof[2];
+  assign rx_ip_sof_s[0] = rx_ip_sof[3];
+  assign rx_ip_data_s[31:24] = rx_ip_data[ 7: 0];
+  assign rx_ip_data_s[23:16] = rx_ip_data[15: 8];
+  assign rx_ip_data_s[15: 8] = rx_ip_data[23:16];
+  assign rx_ip_data_s[ 7: 0] = rx_ip_data[31:24];
+  end else begin
+  assign rx_ip_sof_s[3] = rx_ip_sof[3];
+  assign rx_ip_sof_s[2] = rx_ip_sof[2];
+  assign rx_ip_sof_s[1] = rx_ip_sof[1];
+  assign rx_ip_sof_s[0] = rx_ip_sof[0];
+  assign rx_ip_data_s[31:24] = rx_ip_data[31:24];
+  assign rx_ip_data_s[23:16] = rx_ip_data[23:16];
+  assign rx_ip_data_s[15: 8] = rx_ip_data[15: 8];
+  assign rx_ip_data_s[ 7: 0] = rx_ip_data[ 7: 0];
+  end
+  endgenerate
+
+  // dword may contain more than one frame per clock
+
+  always @(posedge rx_clk) begin
+    rx_ip_data_d <= rx_ip_data_s;
+    rx_ip_sof_d <= rx_ip_sof_s;
+    if (rx_ip_sof_s != 4'h0) begin
+      rx_ip_sof_hold <= rx_ip_sof_s;
+    end
+    rx_sof <= |rx_ip_sof_d;
+    if (rx_ip_sof_hold[0] == 1'b1) begin
+      rx_data <= rx_ip_data_s;
+    end else if (rx_ip_sof_hold[1] == 1'b1) begin
+      rx_data <= {rx_ip_data_s[ 7:0], rx_ip_data_d[31: 8]};
+    end else if (rx_ip_sof_hold[2] == 1'b1) begin
+      rx_data <= {rx_ip_data_s[15:0], rx_ip_data_d[31:16]};
+    end else if (rx_ip_sof_hold[3] == 1'b1) begin
+      rx_data <= {rx_ip_data_s[23:0], rx_ip_data_d[31:24]};
+    end else begin
+      rx_data <= 32'd0;
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 5c91e41da84a98bb58a39a545b74106ec648201c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 21 Jul 2016 16:07:18 -0400
Subject: [PATCH 339/972] ad9680- sof + sample delineation

---
 library/axi_ad9680/axi_ad9680.v      |  5 +++-
 library/axi_ad9680/axi_ad9680_if.v   | 41 ++++++++++++++++++++--------
 library/axi_ad9680/axi_ad9680_ip.tcl |  1 +
 3 files changed, 35 insertions(+), 12 deletions(-)

diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v
index a32e442cb..321384f95 100644
--- a/library/axi_ad9680/axi_ad9680.v
+++ b/library/axi_ad9680/axi_ad9680.v
@@ -43,6 +43,7 @@ module axi_ad9680 (
   // rx_clk is (line-rate/40)
 
   rx_clk,
+  rx_sof,
   rx_data,
 
   // dma interface
@@ -89,6 +90,7 @@ module axi_ad9680 (
   // rx_clk is (line-rate/40)
 
   input           rx_clk;
+  input  [  3:0]  rx_sof;
   input  [127:0]  rx_data;
 
   // dma interface
@@ -193,8 +195,9 @@ module axi_ad9680 (
 
   // main (device interface)
 
-  axi_ad9680_if i_if (
+  axi_ad9680_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
     .rx_clk (rx_clk),
+    .rx_sof (rx_sof),
     .rx_data (rx_data),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
diff --git a/library/axi_ad9680/axi_ad9680_if.v b/library/axi_ad9680/axi_ad9680_if.v
index d7309858d..14c71068e 100644
--- a/library/axi_ad9680/axi_ad9680_if.v
+++ b/library/axi_ad9680/axi_ad9680_if.v
@@ -34,9 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// This is the LVDS/DDR interface
 
 `timescale 1ns/100ps
 
@@ -46,6 +43,7 @@ module axi_ad9680_if (
   // rx_clk is (line-rate/40)
 
   rx_clk,
+  rx_sof,
   rx_data,
 
   // adc data output
@@ -58,10 +56,15 @@ module axi_ad9680_if (
   adc_or_b,
   adc_status);
 
+  // parameters
+
+  parameter DEVICE_TYPE = 0;
+
   // jesd interface 
   // rx_clk is (line-rate/40)
 
   input           rx_clk;
+  input  [  3:0]  rx_sof;
   input  [127:0]  rx_data;
 
   // adc data output
@@ -88,6 +91,7 @@ module axi_ad9680_if (
   wire    [15:0]  adc_data_b_s2_s;
   wire    [15:0]  adc_data_b_s1_s;
   wire    [15:0]  adc_data_b_s0_s;
+  wire   [127:0]  rx_data_s;
 
   // adc clock is the reference clock
 
@@ -105,15 +109,15 @@ module axi_ad9680_if (
 
   // data multiplex
 
-  assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]};
-  assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]};
-  assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15:  8], rx_data[ 47: 42]};
-  assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[  7:  0], rx_data[ 39: 34]};
+  assign adc_data_a_s3_s = {rx_data_s[ 57: 56], rx_data_s[ 31: 24], rx_data_s[ 63: 58]};
+  assign adc_data_a_s2_s = {rx_data_s[ 49: 48], rx_data_s[ 23: 16], rx_data_s[ 55: 50]};
+  assign adc_data_a_s1_s = {rx_data_s[ 41: 40], rx_data_s[ 15:  8], rx_data_s[ 47: 42]};
+  assign adc_data_a_s0_s = {rx_data_s[ 33: 32], rx_data_s[  7:  0], rx_data_s[ 39: 34]};
 
-  assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]};
-  assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]};
-  assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]};
-  assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]};
+  assign adc_data_b_s3_s = {rx_data_s[121:120], rx_data_s[ 95: 88], rx_data_s[127:122]};
+  assign adc_data_b_s2_s = {rx_data_s[113:112], rx_data_s[ 87: 80], rx_data_s[119:114]};
+  assign adc_data_b_s1_s = {rx_data_s[105:104], rx_data_s[ 79: 72], rx_data_s[111:106]};
+  assign adc_data_b_s0_s = {rx_data_s[ 97: 96], rx_data_s[ 71: 64], rx_data_s[103: 98]};
 
   // status
 
@@ -125,6 +129,21 @@ module axi_ad9680_if (
     end
   end
 
+  // frame-alignment
+
+  genvar n;
+
+  generate
+  for (n = 0; n < 4; n = n + 1) begin: g_xcvr_if
+  ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
+    .rx_clk (rx_clk),
+    .rx_ip_sof (rx_sof),
+    .rx_ip_data (rx_data[((n*32)+31):(n*32)]),
+    .rx_sof (),
+    .rx_data (rx_data_s[((n*32)+31):(n*32)]));
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/axi_ad9680/axi_ad9680_ip.tcl b/library/axi_ad9680/axi_ad9680_ip.tcl
index 7a045961e..1f68f2a88 100644
--- a/library/axi_ad9680/axi_ad9680_ip.tcl
+++ b/library/axi_ad9680/axi_ad9680_ip.tcl
@@ -14,6 +14,7 @@ adi_ip_files axi_ad9680 [list \
   "$ad_hdl_dir/library/common/up_clock_mon.v" \
   "$ad_hdl_dir/library/common/up_adc_common.v" \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
   "axi_ad9680_pnmon.v" \
   "axi_ad9680_channel.v" \
   "axi_ad9680_if.v" \

From 6df5ba1a7a06e984c13c88526931a750f5d32578 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 21 Jul 2016 16:08:53 -0400
Subject: [PATCH 340/972] daq2- adxcvr version

---
 projects/daq2/common/daq2_bd.tcl      | 210 +++++++++++++++-----------
 projects/daq2/zc706/system_constr.xdc |   4 +-
 projects/daq2/zc706/system_top.v      |  22 ++-
 3 files changed, 137 insertions(+), 99 deletions(-)

diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index d9c58fdd2..b6e0c9c50 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -4,17 +4,36 @@
 create_bd_port -dir I rx_ref_clk
 create_bd_port -dir O rx_sync
 create_bd_port -dir I rx_sysref
-create_bd_port -dir I -from 3 -to 0 rx_data_p
-create_bd_port -dir I -from 3 -to 0 rx_data_n
+create_bd_port -dir I rx_data_0_p
+create_bd_port -dir I rx_data_0_n
+create_bd_port -dir I rx_data_1_p
+create_bd_port -dir I rx_data_1_n
+create_bd_port -dir I rx_data_2_p
+create_bd_port -dir I rx_data_2_n
+create_bd_port -dir I rx_data_3_p
+create_bd_port -dir I rx_data_3_n
 
 create_bd_port -dir I tx_ref_clk
 create_bd_port -dir I tx_sync
 create_bd_port -dir I tx_sysref
-create_bd_port -dir O -from 3 -to 0 tx_data_p
-create_bd_port -dir O -from 3 -to 0 tx_data_n
+create_bd_port -dir O tx_data_0_p
+create_bd_port -dir O tx_data_0_n
+create_bd_port -dir O tx_data_1_p
+create_bd_port -dir O tx_data_1_n
+create_bd_port -dir O tx_data_2_p
+create_bd_port -dir O tx_data_2_n
+create_bd_port -dir O tx_data_3_p
+create_bd_port -dir O tx_data_3_n
 
 # dac peripherals
 
+set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9144_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9144_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9144_xcvr
+
+set sys_ad9144_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9144_rstgen]
+
 set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
 set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core
 
@@ -40,6 +59,13 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack
 
 # adc peripherals
 
+set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
+
+set sys_ad9680_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9680_rstgen]
+
 set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
 
 set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
@@ -63,83 +89,47 @@ set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
 
-# dac/adc common gt
+# shared transceiver core
 
-set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq2_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq2_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq2_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq2_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq2_gt
+set util_daq2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq2_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq2_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_xcvr
 
-set util_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq2_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq2_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq2_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq2_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq2_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq2_gt
-set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq2_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_gt
-
-# connections (gt)
-
-ad_connect  util_daq2_gt/qpll_ref_clk rx_ref_clk
-ad_connect  util_daq2_gt/cpll_ref_clk tx_ref_clk
-
-ad_connect  axi_daq2_gt/gt_qpll_0 util_daq2_gt/gt_qpll_0
-ad_connect  axi_daq2_gt/gt_pll_0 util_daq2_gt/gt_pll_0
-ad_connect  axi_daq2_gt/gt_pll_1 util_daq2_gt/gt_pll_1
-ad_connect  axi_daq2_gt/gt_pll_2 util_daq2_gt/gt_pll_2
-ad_connect  axi_daq2_gt/gt_pll_3 util_daq2_gt/gt_pll_3
-ad_connect  axi_daq2_gt/gt_rx_0 util_daq2_gt/gt_rx_0
-ad_connect  axi_daq2_gt/gt_rx_1 util_daq2_gt/gt_rx_1
-ad_connect  axi_daq2_gt/gt_rx_2 util_daq2_gt/gt_rx_2
-ad_connect  axi_daq2_gt/gt_rx_3 util_daq2_gt/gt_rx_3
-ad_connect  axi_daq2_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
-ad_connect  axi_daq2_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
-ad_connect  axi_daq2_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
-ad_connect  axi_daq2_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
-ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq2_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq2_gt/gt_tx_0 util_daq2_gt/gt_tx_0
-ad_connect  axi_daq2_gt/gt_tx_1 util_daq2_gt/gt_tx_1
-ad_connect  axi_daq2_gt/gt_tx_2 util_daq2_gt/gt_tx_2
-ad_connect  axi_daq2_gt/gt_tx_3 util_daq2_gt/gt_tx_3
-ad_connect  axi_daq2_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx
-ad_connect  axi_daq2_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx
-ad_connect  axi_daq2_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx
-ad_connect  axi_daq2_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx
+ad_connect  sys_cpu_resetn util_daq2_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_daq2_xcvr/up_clk
 
 # connections (dac)
 
-ad_connect  util_daq2_gt/tx_sysref tx_sysref
-ad_connect  util_daq2_gt/tx_p tx_data_p
-ad_connect  util_daq2_gt/tx_n tx_data_n
-ad_connect  util_daq2_gt/tx_sync tx_sync
-ad_connect  util_daq2_gt/tx_out_clk util_daq2_gt/tx_clk
-ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk
-ad_connect  util_daq2_gt/tx_ip_rst axi_ad9144_jesd/tx_reset
-ad_connect  util_daq2_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done
-ad_connect  util_daq2_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref
-ad_connect  util_daq2_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
-ad_connect  util_daq2_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
-ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_core/tx_clk
-ad_connect  util_daq2_gt/tx_data axi_ad9144_core/tx_data
-ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_upack/dac_clk
+ad_connect  axi_ad9144_xcvr/up_cm_0 util_daq2_xcvr/up_cm_0
+ad_connect  axi_ad9144_xcvr/up_ch_0 util_daq2_xcvr/up_tx_0
+ad_connect  axi_ad9144_xcvr/up_ch_1 util_daq2_xcvr/up_tx_1
+ad_connect  axi_ad9144_xcvr/up_ch_2 util_daq2_xcvr/up_tx_2
+ad_connect  axi_ad9144_xcvr/up_ch_3 util_daq2_xcvr/up_tx_3
+ad_connect  axi_ad9144_jesd/gt0_tx util_daq2_xcvr/tx_0
+ad_connect  axi_ad9144_jesd/gt3_tx util_daq2_xcvr/tx_1
+ad_connect  axi_ad9144_jesd/gt1_tx util_daq2_xcvr/tx_2
+ad_connect  axi_ad9144_jesd/gt2_tx util_daq2_xcvr/tx_3
+ad_connect  util_daq2_xcvr/tx_out_clk_0 util_daq2_xcvr/tx_clk_0
+ad_connect  util_daq2_xcvr/tx_out_clk_0 util_daq2_xcvr/tx_clk_1
+ad_connect  util_daq2_xcvr/tx_out_clk_0 util_daq2_xcvr/tx_clk_2
+ad_connect  util_daq2_xcvr/tx_out_clk_0 util_daq2_xcvr/tx_clk_3
+ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_jesd/tx_core_clk
+ad_connect  util_daq2_xcvr/tx_out_clk_0 sys_ad9144_rstgen/slowest_sync_clk
+ad_connect  sys_cpu_resetn sys_ad9144_rstgen/ext_reset_in
+ad_connect  tx_sysref axi_ad9144_jesd/tx_sysref
+ad_connect  tx_sync axi_ad9144_jesd/tx_sync
+ad_connect  sys_ad9144_rstgen/peripheral_reset axi_ad9144_jesd/tx_reset
+ad_connect  axi_ad9144_xcvr/up_status axi_ad9144_jesd/tx_reset_done
+ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
+ad_connect  axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data
+ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk
 ad_connect  axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
 ad_connect  axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
 ad_connect  axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
 ad_connect  axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1
 ad_connect  axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1
 ad_connect  axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1
-ad_connect  util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk
+ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk
 ad_connect  axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
 ad_connect  axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
 ad_connect  axi_ad9144_upack/dma_xfer_in axi_ad9144_fifo/dac_xfer_out
@@ -152,33 +142,61 @@ ad_connect  axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready
 ad_connect  axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data
 ad_connect  axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid
 ad_connect  axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
+ad_connect  util_daq2_xcvr/cpll_ref_clk_0 tx_ref_clk
+ad_connect  util_daq2_xcvr/cpll_ref_clk_1 tx_ref_clk
+ad_connect  util_daq2_xcvr/cpll_ref_clk_2 tx_ref_clk
+ad_connect  util_daq2_xcvr/cpll_ref_clk_3 tx_ref_clk
+ad_connect  util_daq2_xcvr/tx_0_p tx_data_0_p
+ad_connect  util_daq2_xcvr/tx_0_n tx_data_0_n
+ad_connect  util_daq2_xcvr/tx_1_p tx_data_1_p
+ad_connect  util_daq2_xcvr/tx_1_n tx_data_1_n
+ad_connect  util_daq2_xcvr/tx_2_p tx_data_2_p
+ad_connect  util_daq2_xcvr/tx_2_n tx_data_2_n
+ad_connect  util_daq2_xcvr/tx_3_p tx_data_3_p
+ad_connect  util_daq2_xcvr/tx_3_n tx_data_3_n
 
 # connections (adc)
 
-ad_connect  util_daq2_gt/rx_sysref rx_sysref
-ad_connect  util_daq2_gt/rx_p rx_data_p
-ad_connect  util_daq2_gt/rx_n rx_data_n
-ad_connect  util_daq2_gt/rx_sync rx_sync
-ad_connect  util_daq2_gt/rx_out_clk util_daq2_gt/rx_clk
-ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
-ad_connect  util_daq2_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
-ad_connect  util_daq2_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
-ad_connect  util_daq2_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
-ad_connect  util_daq2_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
-ad_connect  util_daq2_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
-ad_connect  util_daq2_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
-ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_core/rx_clk
-ad_connect  util_daq2_gt/rx_data axi_ad9680_core/rx_data
-ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_cpack/adc_clk
-ad_connect  util_daq2_gt/rx_rst axi_ad9680_cpack/adc_rst
+ad_connect  axi_ad9680_xcvr/up_es_0 util_daq2_xcvr/up_es_0
+ad_connect  axi_ad9680_xcvr/up_es_1 util_daq2_xcvr/up_es_1
+ad_connect  axi_ad9680_xcvr/up_es_2 util_daq2_xcvr/up_es_2
+ad_connect  axi_ad9680_xcvr/up_es_3 util_daq2_xcvr/up_es_3
+ad_connect  axi_ad9680_xcvr/up_ch_0 util_daq2_xcvr/up_rx_0
+ad_connect  axi_ad9680_xcvr/up_ch_1 util_daq2_xcvr/up_rx_1
+ad_connect  axi_ad9680_xcvr/up_ch_2 util_daq2_xcvr/up_rx_2
+ad_connect  axi_ad9680_xcvr/up_ch_3 util_daq2_xcvr/up_rx_3
+ad_connect  axi_ad9680_jesd/gt0_rx util_daq2_xcvr/rx_0
+ad_connect  axi_ad9680_jesd/gt1_rx util_daq2_xcvr/rx_1
+ad_connect  axi_ad9680_jesd/gt2_rx util_daq2_xcvr/rx_2
+ad_connect  axi_ad9680_jesd/gt3_rx util_daq2_xcvr/rx_3
+ad_connect  axi_ad9680_jesd/rxencommaalign_out util_daq2_xcvr/rx_calign_0
+ad_connect  axi_ad9680_jesd/rxencommaalign_out util_daq2_xcvr/rx_calign_1
+ad_connect  axi_ad9680_jesd/rxencommaalign_out util_daq2_xcvr/rx_calign_2
+ad_connect  axi_ad9680_jesd/rxencommaalign_out util_daq2_xcvr/rx_calign_3
+ad_connect  util_daq2_xcvr/rx_out_clk_0 util_daq2_xcvr/rx_clk_0
+ad_connect  util_daq2_xcvr/rx_out_clk_0 util_daq2_xcvr/rx_clk_1
+ad_connect  util_daq2_xcvr/rx_out_clk_0 util_daq2_xcvr/rx_clk_2
+ad_connect  util_daq2_xcvr/rx_out_clk_0 util_daq2_xcvr/rx_clk_3
+ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_jesd/rx_core_clk
+ad_connect  util_daq2_xcvr/tx_out_clk_0 sys_ad9680_rstgen/slowest_sync_clk
+ad_connect  sys_cpu_resetn sys_ad9680_rstgen/ext_reset_in
+ad_connect  rx_sysref axi_ad9680_jesd/rx_sysref
+ad_connect  rx_sync axi_ad9680_jesd/rx_sync
+ad_connect  sys_ad9680_rstgen/peripheral_reset axi_ad9680_jesd/rx_reset
+ad_connect  axi_ad9680_xcvr/up_status axi_ad9680_jesd/rx_reset_done
+ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
+ad_connect  axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
+ad_connect  axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
+ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
+ad_connect  sys_ad9680_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
 ad_connect  axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
 ad_connect  axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
 ad_connect  axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
 ad_connect  axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
 ad_connect  axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
 ad_connect  axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
-ad_connect  util_daq2_gt/rx_out_clk axi_ad9680_fifo/adc_clk
-ad_connect  util_daq2_gt/rx_rst axi_ad9680_fifo/adc_rst
+ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
+ad_connect  sys_ad9680_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
 ad_connect  axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
 ad_connect  axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
 ad_connect  sys_cpu_clk axi_ad9680_fifo/dma_clk
@@ -189,13 +207,23 @@ ad_connect  axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
 ad_connect  axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
 ad_connect  axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
 ad_connect  axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
+ad_connect  util_daq2_xcvr/qpll_ref_clk_0 rx_ref_clk
+ad_connect  util_daq2_xcvr/rx_0_p rx_data_0_p
+ad_connect  util_daq2_xcvr/rx_0_n rx_data_0_n
+ad_connect  util_daq2_xcvr/rx_1_p rx_data_1_p
+ad_connect  util_daq2_xcvr/rx_1_n rx_data_1_n
+ad_connect  util_daq2_xcvr/rx_2_p rx_data_2_p
+ad_connect  util_daq2_xcvr/rx_2_n rx_data_2_n
+ad_connect  util_daq2_xcvr/rx_3_p rx_data_3_p
+ad_connect  util_daq2_xcvr/rx_3_n rx_data_3_n
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_daq2_gt
+ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
 ad_cpu_interconnect 0x44A00000 axi_ad9144_core
 ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
+ad_cpu_interconnect 0x44A70000 axi_ad9680_xcvr
 ad_cpu_interconnect 0x44A10000 axi_ad9680_core
 ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
@@ -203,7 +231,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
 # gt uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_daq2_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
 
 # interconnect (mem/dac)
 
@@ -219,5 +247,5 @@ ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
 
 ad_connect  axi_ad9144_core/dac_ddata_2 GND
 ad_connect  axi_ad9144_core/dac_ddata_3 GND
-
+ad_connect  axi_ad9144_fifo/dac_fifo_bypass GND
 
diff --git a/projects/daq2/zc706/system_constr.xdc b/projects/daq2/zc706/system_constr.xdc
index df68021e6..fd3ddf448 100644
--- a/projects/daq2/zc706/system_constr.xdc
+++ b/projects/daq2/zc706/system_constr.xdc
@@ -56,6 +56,6 @@ set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v
index 071300f3a..5a7d3d58a 100644
--- a/projects/daq2/zc706/system_top.v
+++ b/projects/daq2/zc706/system_top.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -386,8 +384,14 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
     .rx_ref_clk (rx_ref_clk),
     .rx_sync (rx_sync),
     .rx_sysref (rx_sysref),
@@ -413,8 +417,14 @@ module system_top (
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
     .tx_ref_clk (tx_ref_clk),
     .tx_sync (tx_sync),
     .tx_sysref (tx_sysref));

From 39a5534e00e4d0c4333a188af67ef458e4f6130e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 21 Jul 2016 16:10:38 -0400
Subject: [PATCH 341/972] hdlmake- updates

---
 library/Makefile                 |  4 ----
 library/axi_ad9680/Makefile      |  1 +
 library/util_adxcvr/Makefile     |  1 +
 projects/daq2/kc705/Makefile     | 12 ++++++------
 projects/daq2/kcu105/Makefile    | 12 ++++++------
 projects/daq2/vc707/Makefile     | 12 ++++++------
 projects/daq2/zc706/Makefile     | 12 ++++++------
 projects/fmcomms2/a10gx/Makefile |  2 +-
 8 files changed, 27 insertions(+), 29 deletions(-)

diff --git a/library/Makefile b/library/Makefile
index 560659162..1b40b5171 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -55,7 +55,6 @@ clean:
 	make -C spi_engine/spi_engine_execution clean
 	make -C spi_engine/spi_engine_interconnect clean
 	make -C spi_engine/spi_engine_offload clean
-	make -C util_adc_pack clean
 	make -C util_adcfifo clean
 	make -C util_adxcvr clean
 	make -C util_axis_fifo clean
@@ -63,7 +62,6 @@ clean:
 	make -C util_bsplit clean
 	make -C util_ccat clean
 	make -C util_cpack clean
-	make -C util_dac_unpack clean
 	make -C util_dacfifo clean
 	make -C util_gmii_to_rgmii clean
 	make -C util_gtlb clean
@@ -128,7 +126,6 @@ lib:
 	-make -C spi_engine/spi_engine_execution
 	-make -C spi_engine/spi_engine_interconnect
 	-make -C spi_engine/spi_engine_offload
-	-make -C util_adc_pack
 	-make -C util_adcfifo
 	-make -C util_adxcvr
 	-make -C util_axis_fifo
@@ -136,7 +133,6 @@ lib:
 	-make -C util_bsplit
 	-make -C util_ccat
 	-make -C util_cpack
-	-make -C util_dac_unpack
 	-make -C util_dacfifo
 	-make -C util_gmii_to_rgmii
 	-make -C util_gtlb
diff --git a/library/axi_ad9680/Makefile b/library/axi_ad9680/Makefile
index ce1aec3b9..65f8ad28a 100644
--- a/library/axi_ad9680/Makefile
+++ b/library/axi_ad9680/Makefile
@@ -17,6 +17,7 @@ M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
 M_DEPS += axi_ad9680_pnmon.v
 M_DEPS += axi_ad9680_channel.v
 M_DEPS += axi_ad9680_if.v
diff --git a/library/util_adxcvr/Makefile b/library/util_adxcvr/Makefile
index 9c322fe6b..c5bd23c76 100644
--- a/library/util_adxcvr/Makefile
+++ b/library/util_adxcvr/Makefile
@@ -8,6 +8,7 @@
 M_DEPS := util_adxcvr_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += util_adxcvr_constr.xdc
 M_DEPS += util_adxcvr_xcm.v
 M_DEPS += util_adxcvr_xch.v
 M_DEPS += util_adxcvr.v
diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile
index f5349f760..20b625f64 100644
--- a/projects/daq2/kc705/Makefile
+++ b/projects/daq2/kc705/Makefile
@@ -21,12 +21,12 @@ M_DEPS += ../../common/kc705/kc705_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
+M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -57,12 +57,12 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
+	make -C ../../../library/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_upack clean
 
 
@@ -74,12 +74,12 @@ daq2_kc705.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
+	make -C ../../../library/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_adcfifo
+	make -C ../../../library/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_upack
 
 ####################################################################################
diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile
index 82e1efb04..05a450015 100644
--- a/projects/daq2/kcu105/Makefile
+++ b/projects/daq2/kcu105/Makefile
@@ -21,12 +21,12 @@ M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
+M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -57,12 +57,12 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
+	make -C ../../../library/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_upack clean
 
 
@@ -74,12 +74,12 @@ daq2_kcu105.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
+	make -C ../../../library/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_adcfifo
+	make -C ../../../library/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_upack
 
 ####################################################################################
diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile
index 879592ecc..f766f1ade 100644
--- a/projects/daq2/vc707/Makefile
+++ b/projects/daq2/vc707/Makefile
@@ -21,12 +21,12 @@ M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
+M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -57,12 +57,12 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
+	make -C ../../../library/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_upack clean
 
 
@@ -74,12 +74,12 @@ daq2_vc707.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
+	make -C ../../../library/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_adcfifo
+	make -C ../../../library/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_upack
 
 ####################################################################################
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index ec2fa7313..7f8f0fd68 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -24,15 +24,15 @@ M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -64,15 +64,15 @@ clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_upack clean
 
 
@@ -85,15 +85,15 @@ lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/util_adcfifo
+	make -C ../../../library/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_upack
 
 ####################################################################################
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 8d08ed786..df6dcfd61 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -92,7 +92,7 @@ M_DEPS += ../../../library/util_wfifo/util_wfifo.v
 M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl
 
 
-M_ALTERA := quartus_sh --64bit -t
+M_ALTERA := quartus_sh --64bit -t 
 
 
 M_FLIST += *.log

From 6ebb32a1943fa61eaf0bc07b035433eb7e7c2d73 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Fri, 22 Jul 2016 12:54:27 -0400
Subject: [PATCH 342/972] library axi-slave missing protection signal added

---
 library/axi_ad6676/axi_ad6676.v                           | 7 ++++++-
 library/axi_ad7616/axi_ad7616.v                           | 5 +++++
 library/axi_ad9122/axi_ad9122.v                           | 7 ++++++-
 library/axi_ad9234/axi_ad9234.v                           | 7 ++++++-
 library/axi_ad9265/axi_ad9265.v                           | 7 ++++++-
 library/axi_ad9434/axi_ad9434.v                           | 7 ++++++-
 library/axi_ad9467/axi_ad9467.v                           | 5 +++++
 library/axi_ad9625/axi_ad9625.v                           | 7 ++++++-
 library/axi_ad9643/axi_ad9643.v                           | 7 ++++++-
 library/axi_ad9652/axi_ad9652.v                           | 7 ++++++-
 library/axi_ad9684/axi_ad9684.v                           | 5 +++++
 library/axi_ad9739a/axi_ad9739a.v                         | 7 ++++++-
 library/axi_clkgen/axi_clkgen.v                           | 8 +++++++-
 library/axi_generic_adc/axi_generic_adc.v                 | 5 ++++-
 library/axi_gpreg/axi_gpreg.v                             | 5 ++++-
 library/axi_hdmi_rx/axi_hdmi_rx.v                         | 7 ++++++-
 library/axi_i2s_adi/axi_i2s_adi.vhd                       | 5 ++++-
 library/axi_jesd_gt/axi_jesd_gt.v                         | 2 ++
 library/axi_mc_controller/axi_mc_controller.v             | 5 ++++-
 library/axi_mc_current_monitor/axi_mc_current_monitor.v   | 5 ++++-
 library/axi_mc_speed/axi_mc_speed.v                       | 5 ++++-
 library/axi_spdif_rx/axi_spdif_rx.vhd                     | 3 +++
 library/axi_spdif_tx/axi_spdif_tx.vhd                     | 2 ++
 library/axi_usb_fx3/axi_usb_fx3.v                         | 4 ++++
 .../cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl      | 2 +-
 library/util_pmod_fmeter/util_pmod_fmeter.v               | 7 ++++++-
 26 files changed, 124 insertions(+), 19 deletions(-)

diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v
index a55b8039d..7131e97fa 100755
--- a/library/axi_ad6676/axi_ad6676.v
+++ b/library/axi_ad6676/axi_ad6676.v
@@ -80,7 +80,9 @@ module axi_ad6676 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   parameter ID = 0;
   parameter DEVICE_TYPE = 0;
@@ -126,6 +128,9 @@ module axi_ad6676 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 
diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 97da48a65..8027d41c5 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -66,6 +66,7 @@ module axi_ad7616 (
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -76,6 +77,7 @@ module axi_ad7616 (
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rresp,
@@ -140,6 +142,9 @@ module axi_ad7616 (
   output  [ 1:0]                    s_axi_rresp;
   output  [31:0]                    s_axi_rdata;
   input                             s_axi_rready;
+  input   [ 2:0]                    s_axi_awprot;
+  input   [ 2:0]                    s_axi_arprot;
+
 
   output                            adc_valid;
   output  [15:0]                    adc_data;
diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v
index 9239c0575..69eb7d9f5 100644
--- a/library/axi_ad9122/axi_ad9122.v
+++ b/library/axi_ad9122/axi_ad9122.v
@@ -87,7 +87,9 @@ module axi_ad9122 (
   s_axi_rvalid,
   s_axi_rdata,
   s_axi_rresp,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -152,6 +154,9 @@ module axi_ad9122 (
   output  [31:0]  s_axi_rdata;
   output  [ 1:0]  s_axi_rresp;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal clocks and resets
 
diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v
index 202909deb..53680519b 100644
--- a/library/axi_ad9234/axi_ad9234.v
+++ b/library/axi_ad9234/axi_ad9234.v
@@ -79,7 +79,9 @@ module axi_ad9234 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   parameter ID = 0;
   parameter DEVICE_TYPE = 0;
@@ -124,6 +126,9 @@ module axi_ad9234 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 
diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v
index 0e00ddbaa..1afb8111a 100644
--- a/library/axi_ad9265/axi_ad9265.v
+++ b/library/axi_ad9265/axi_ad9265.v
@@ -84,7 +84,9 @@ module axi_ad9265 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -137,6 +139,9 @@ module axi_ad9265 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 
diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v
index 2a226e5e9..b8e9d96db 100644
--- a/library/axi_ad9434/axi_ad9434.v
+++ b/library/axi_ad9434/axi_ad9434.v
@@ -79,7 +79,9 @@ module axi_ad9434 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
 
   // parameters
@@ -128,6 +130,9 @@ module axi_ad9434 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal clocks & resets
   wire            adc_rst;
diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v
index 63b1d4cbc..3d549a15c 100644
--- a/library/axi_ad9467/axi_ad9467.v
+++ b/library/axi_ad9467/axi_ad9467.v
@@ -69,6 +69,7 @@ module axi_ad9467(
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -79,6 +80,7 @@ module axi_ad9467(
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rresp,
@@ -134,6 +136,9 @@ module axi_ad9467(
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 
diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v
index 18ef759f6..8fd860fc3 100644
--- a/library/axi_ad9625/axi_ad9625.v
+++ b/library/axi_ad9625/axi_ad9625.v
@@ -80,7 +80,9 @@ module axi_ad9625 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   parameter ID = 0;
   parameter DEVICE_TYPE = 0;
@@ -126,6 +128,9 @@ module axi_ad9625 (
   output  [  1:0] s_axi_rresp;
   output  [ 31:0] s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 
diff --git a/library/axi_ad9643/axi_ad9643.v b/library/axi_ad9643/axi_ad9643.v
index 58aba5e54..312036814 100644
--- a/library/axi_ad9643/axi_ad9643.v
+++ b/library/axi_ad9643/axi_ad9643.v
@@ -87,7 +87,9 @@ module axi_ad9643 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -145,6 +147,9 @@ module axi_ad9643 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 
diff --git a/library/axi_ad9652/axi_ad9652.v b/library/axi_ad9652/axi_ad9652.v
index 750c3c32a..f706e1494 100644
--- a/library/axi_ad9652/axi_ad9652.v
+++ b/library/axi_ad9652/axi_ad9652.v
@@ -87,7 +87,9 @@ module axi_ad9652 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -145,6 +147,9 @@ module axi_ad9652 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 
diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v
index be1072b71..010bcf5fd 100644
--- a/library/axi_ad9684/axi_ad9684.v
+++ b/library/axi_ad9684/axi_ad9684.v
@@ -74,6 +74,7 @@ module axi_ad9684 (
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -84,6 +85,7 @@ module axi_ad9684 (
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rresp,
@@ -139,6 +141,9 @@ module axi_ad9684 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 
diff --git a/library/axi_ad9739a/axi_ad9739a.v b/library/axi_ad9739a/axi_ad9739a.v
index e357648a5..c7e2beead 100644
--- a/library/axi_ad9739a/axi_ad9739a.v
+++ b/library/axi_ad9739a/axi_ad9739a.v
@@ -81,7 +81,9 @@ module axi_ad9739a (
   s_axi_rvalid,
   s_axi_rdata,
   s_axi_rresp,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -133,6 +135,9 @@ module axi_ad9739a (
   output  [ 31:0]   s_axi_rdata;
   output  [  1:0]   s_axi_rresp;
   input             s_axi_rready;
+  input   [ 2:0]    s_axi_awprot;
+  input   [ 2:0]    s_axi_arprot;
+
 
   // internal clocks and resets
 
diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v
index 8d18ee7c7..2a5586983 100644
--- a/library/axi_clkgen/axi_clkgen.v
+++ b/library/axi_clkgen/axi_clkgen.v
@@ -65,7 +65,9 @@ module axi_clkgen (
   s_axi_rvalid,
   s_axi_rdata,
   s_axi_rresp,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -110,6 +112,10 @@ module axi_clkgen (
   output  [31:0]  s_axi_rdata;
   output  [ 1:0]  s_axi_rresp;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
+
 
   // reset and clocks
 
diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v
index 7e747eb04..c466ec2eb 100644
--- a/library/axi_generic_adc/axi_generic_adc.v
+++ b/library/axi_generic_adc/axi_generic_adc.v
@@ -21,7 +21,10 @@ module axi_generic_adc (
 	output		s_axi_rvalid,
 	output	[ 1:0]	s_axi_rresp,
 	output	[31:0]	s_axi_rdata,
-	input		s_axi_rready
+	input		s_axi_rready,
+  input   [ 2:0]  s_axi_awprot,
+  input   [ 2:0]  s_axi_arprot
+
 );
 
 parameter NUM_OF_CHANNELS = 2;
diff --git a/library/axi_gpreg/axi_gpreg.v b/library/axi_gpreg/axi_gpreg.v
index 8b5d5852e..30a8471a3 100644
--- a/library/axi_gpreg/axi_gpreg.v
+++ b/library/axi_gpreg/axi_gpreg.v
@@ -111,7 +111,10 @@ module axi_gpreg #(
   output            s_axi_rvalid,
   output  [ 31:0]   s_axi_rdata,
   output  [  1:0]   s_axi_rresp,
-  input             s_axi_rready);
+  input             s_axi_rready,
+  input   [ 2:0]    s_axi_awprot,
+  input   [ 2:0]    s_axi_arprot);
+
 
   // version
 
diff --git a/library/axi_hdmi_rx/axi_hdmi_rx.v b/library/axi_hdmi_rx/axi_hdmi_rx.v
index afc20774e..3b6523f82 100644
--- a/library/axi_hdmi_rx/axi_hdmi_rx.v
+++ b/library/axi_hdmi_rx/axi_hdmi_rx.v
@@ -73,7 +73,9 @@ module axi_hdmi_rx  (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -114,6 +116,9 @@ module axi_hdmi_rx  (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal signals
 
diff --git a/library/axi_i2s_adi/axi_i2s_adi.vhd b/library/axi_i2s_adi/axi_i2s_adi.vhd
index 265cea358..90703fc3c 100644
--- a/library/axi_i2s_adi/axi_i2s_adi.vhd
+++ b/library/axi_i2s_adi/axi_i2s_adi.vhd
@@ -101,7 +101,10 @@ entity axi_i2s_adi is
 		S_AXI_WREADY		: out std_logic;
 		S_AXI_BRESP		: out std_logic_vector(1 downto 0);
 		S_AXI_BVALID		: out std_logic;
-		S_AXI_AWREADY		: out std_logic
+		S_AXI_AWREADY		: out std_logic;
+    S_AXI_AWPROT  : in  std_logic_vector(2 downto 0);
+    S_AXI_ARPROT  : in  std_logic_vector(2 downto 0)
+
 	);
 end entity axi_i2s_adi;
 
diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v
index 0612f9e6b..bb9030060 100644
--- a/library/axi_jesd_gt/axi_jesd_gt.v
+++ b/library/axi_jesd_gt/axi_jesd_gt.v
@@ -690,6 +690,8 @@ module axi_jesd_gt #(
   output  [ 31:0]                             s_axi_rdata,
   output  [  1:0]                             s_axi_rresp,
   input                                       s_axi_rready,
+  input   [ 2:0]                              s_axi_awprot,
+  input   [ 2:0]                              s_axi_arprot,
 
   // master interface
 
diff --git a/library/axi_mc_controller/axi_mc_controller.v b/library/axi_mc_controller/axi_mc_controller.v
index e802feef8..2f7d79688 100644
--- a/library/axi_mc_controller/axi_mc_controller.v
+++ b/library/axi_mc_controller/axi_mc_controller.v
@@ -84,7 +84,10 @@ module axi_mc_controller
   output          s_axi_rvalid,
   output  [1:0]   s_axi_rresp,
   output  [31:0]  s_axi_rdata,
-  input           s_axi_rready
+  input           s_axi_rready,
+  input   [ 2:0]  s_axi_awprot,
+  input   [ 2:0]  s_axi_arprot
+
 );
 
 //------------------------------------------------------------------------------
diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor.v b/library/axi_mc_current_monitor/axi_mc_current_monitor.v
index 71585d809..bc735f0d5 100644
--- a/library/axi_mc_current_monitor/axi_mc_current_monitor.v
+++ b/library/axi_mc_current_monitor/axi_mc_current_monitor.v
@@ -77,7 +77,10 @@ module axi_mc_current_monitor (
     output          s_axi_rvalid,
     output  [1:0]   s_axi_rresp,
     output  [31:0]  s_axi_rdata,
-    input           s_axi_rready
+    input           s_axi_rready,
+    input   [ 2:0]  s_axi_awprot,
+    input   [ 2:0]  s_axi_arprot
+  
 );
 
 //------------------------------------------------------------------------------
diff --git a/library/axi_mc_speed/axi_mc_speed.v b/library/axi_mc_speed/axi_mc_speed.v
index eae590835..4bd6cb0b9 100644
--- a/library/axi_mc_speed/axi_mc_speed.v
+++ b/library/axi_mc_speed/axi_mc_speed.v
@@ -68,7 +68,10 @@ module axi_mc_speed
     output          s_axi_rvalid,
     output  [ 1:0]  s_axi_rresp,
     output  [31:0]  s_axi_rdata,
-    input           s_axi_rready);
+    input           s_axi_rready,
+    input   [ 2:0]  s_axi_awprot,
+    input   [ 2:0]  s_axi_arprot
+);
 
 //------------------------------------------------------------------------------
 //----------- Registers Declarations -------------------------------------------
diff --git a/library/axi_spdif_rx/axi_spdif_rx.vhd b/library/axi_spdif_rx/axi_spdif_rx.vhd
index 881f02470..5738ab596 100644
--- a/library/axi_spdif_rx/axi_spdif_rx.vhd
+++ b/library/axi_spdif_rx/axi_spdif_rx.vhd
@@ -84,6 +84,9 @@ entity axi_spdif_rx is
     S_AXI_BRESP         : out std_logic_vector(1 downto 0);
     S_AXI_BVALID        : out std_logic;
     S_AXI_AWREADY       : out std_logic;
+    S_AXI_AWPROT        : in  std_logic_vector(2 downto 0);
+    S_AXI_ARPROT        : in  std_logic_vector(2 downto 0);
+
 
     --AXI STREAM interface
     M_AXIS_ACLK         : in  std_logic;
diff --git a/library/axi_spdif_tx/axi_spdif_tx.vhd b/library/axi_spdif_tx/axi_spdif_tx.vhd
index 2a0d1d2d5..eedf3ca9e 100644
--- a/library/axi_spdif_tx/axi_spdif_tx.vhd
+++ b/library/axi_spdif_tx/axi_spdif_tx.vhd
@@ -63,12 +63,14 @@ entity axi_spdif_tx is
 		S_AXI_ACLK	: in  std_logic;
 		S_AXI_ARESETN	: in  std_logic;
 		S_AXI_AWADDR	: in  std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
+    S_AXI_AWPROT  : in  std_logic_vector(2 downto 0);
 		S_AXI_AWVALID	: in  std_logic;
 		S_AXI_WDATA	: in  std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
 		S_AXI_WSTRB	: in  std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
 		S_AXI_WVALID	: in  std_logic;
 		S_AXI_BREADY	: in  std_logic;
 		S_AXI_ARADDR	: in  std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
+    S_AXI_ARPROT  : in  std_logic_vector(2 downto 0);
 		S_AXI_ARVALID	: in  std_logic;
 		S_AXI_RREADY	: in  std_logic;
 		S_AXI_ARREADY	: out std_logic;
diff --git a/library/axi_usb_fx3/axi_usb_fx3.v b/library/axi_usb_fx3/axi_usb_fx3.v
index 65cfbb2a1..d409b42b4 100644
--- a/library/axi_usb_fx3/axi_usb_fx3.v
+++ b/library/axi_usb_fx3/axi_usb_fx3.v
@@ -91,6 +91,7 @@ module axi_usb_fx3 (
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -101,6 +102,7 @@ module axi_usb_fx3 (
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rresp,
@@ -157,6 +159,7 @@ module axi_usb_fx3 (
   input           s_axi_aresetn;
   input           s_axi_awvalid;
   input   [31:0]  s_axi_awaddr;
+  input   [ 2:0]  s_axi_awprot;
   output          s_axi_awready;
   input           s_axi_wvalid;
   input   [31:0]  s_axi_wdata;
@@ -167,6 +170,7 @@ module axi_usb_fx3 (
   input           s_axi_bready;
   input           s_axi_arvalid;
   input   [31:0]  s_axi_araddr;
+  input   [ 2:0]  s_axi_arprot;
   output          s_axi_arready;
   output          s_axi_rvalid;
   output  [ 1:0]  s_axi_rresp;
diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl
index 77d41a487..4556af8ea 100644
--- a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl
+++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl
@@ -67,6 +67,6 @@ adi_add_bus "dma_wr" "master" \
 	}
 
 
-adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "resetn:processing_resetn"
+adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "processing_resetn"
 
 ipx::save_core [ipx::current_core]
diff --git a/library/util_pmod_fmeter/util_pmod_fmeter.v b/library/util_pmod_fmeter/util_pmod_fmeter.v
index da5dc5819..8cae03366 100644
--- a/library/util_pmod_fmeter/util_pmod_fmeter.v
+++ b/library/util_pmod_fmeter/util_pmod_fmeter.v
@@ -62,7 +62,9 @@ module util_pmod_fmeter (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -94,6 +96,9 @@ module util_pmod_fmeter (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal signals
 

From 08f4ba24d51d8bfac891a34efad9b8fc1d4e6c78 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 28 Jul 2016 15:21:38 +0300
Subject: [PATCH 343/972] usb_fx3: Switch PS7 UART to UARTLITE to communicate
 with the FX3 board

---
 projects/usb_fx3/common/usb_fx3_bd.tcl | 9 +++++++--
 projects/usb_fx3/zc706/system_top.v    | 1 -
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl
index 19d31f2c4..a497bbd2c 100644
--- a/projects/usb_fx3/common/usb_fx3_bd.tcl
+++ b/projects/usb_fx3/common/usb_fx3_bd.tcl
@@ -17,6 +17,9 @@ create_bd_port -dir O epswitch_n
 
 set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7
 
+set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
+set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
+
 set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3]
 
 set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma]
@@ -28,8 +31,8 @@ set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
 ad_connect axi_usb_fx3_dma/S_AXIS_S2MM axi_usb_fx3/m_axis
 ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
 
-ad_connect /sys_ps7/UART0_RX usb_fx3_uart_tx
-ad_connect /sys_ps7/UART0_TX usb_fx3_uart_rx
+ad_connect axi_uart/rx usb_fx3_uart_tx
+ad_connect axi_uart/tx usb_fx3_uart_rx
 
 ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk
 ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn
@@ -50,9 +53,11 @@ ad_connect axi_usb_fx3/epswitch_n epswitch_n
 ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
 ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
 ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut
+ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt
 
 ad_cpu_interconnect 0x50000000 axi_usb_fx3
 ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma
+ad_cpu_interconnect 0x40600000 axi_uart
 ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
 ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG
 ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S
diff --git a/projects/usb_fx3/zc706/system_top.v b/projects/usb_fx3/zc706/system_top.v
index 4b9eb12b7..8a212e3ca 100644
--- a/projects/usb_fx3/zc706/system_top.v
+++ b/projects/usb_fx3/zc706/system_top.v
@@ -226,7 +226,6 @@ module system_top (
     .ps_intr_07 (1'b0),
     .ps_intr_08 (1'b0),
     .ps_intr_09 (1'b0),
-    .ps_intr_10 (1'b0),
     .spdif (spdif));
 
 endmodule

From 8a2734b43e73e2da86f47be3a2c960d6cf5c3c2f Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:35:48 -0400
Subject: [PATCH 344/972] up_dac_common- typo- unf register reset

---
 library/common/up_dac_common.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index 1b6013585..c2b144394 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -223,7 +223,7 @@ module up_dac_common (
       up_drp_wdata <= 'd0;
       up_drp_rdata_hold <= 'd0;
       up_status_ovf <= 'd0;
-      up_status_ovf <= 'd0;
+      up_status_unf <= 'd0;
       up_usr_chanmax <= 'd0;
       up_dac_gpio_out <= 'd0;
     end else begin

From c316f0dfea2a1ae345914cfc221c85faaa7d6ed3 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:36:28 -0400
Subject: [PATCH 345/972] ad9144- synthesis warnings fix

---
 library/axi_ad9144/axi_ad9144_channel.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v
index c6b41a101..2559eb86d 100644
--- a/library/axi_ad9144/axi_ad9144_channel.v
+++ b/library/axi_ad9144/axi_ad9144_channel.v
@@ -422,6 +422,7 @@ module axi_ad9144_channel (
     .dac_pat_data_1 (dac_pat_data_1_s),
     .dac_pat_data_2 (dac_pat_data_2_s),
     .dac_data_sel (dac_data_sel_s),
+    .dac_iq_mode (),
     .dac_iqcor_enb (),
     .dac_iqcor_coeff_1 (),
     .dac_iqcor_coeff_2 (),

From 3384d384d3cb825ea6d94e9955d7dba9790e91a9 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:37:38 -0400
Subject: [PATCH 346/972] hdl-vivado-2016.2- infer bus interfaces separately

---
 library/scripts/adi_ip.tcl | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl
index 4baa1c0d2..9987a4780 100644
--- a/library/scripts/adi_ip.tcl
+++ b/library/scripts/adi_ip.tcl
@@ -2,7 +2,7 @@
 # check tool version
 
 if {![info exists REQUIRED_VIVADO_VERSION]} {
-  set REQUIRED_VIVADO_VERSION "2015.4.2"
+  set REQUIRED_VIVADO_VERSION "2016.2"
 }
 
 if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
@@ -26,6 +26,11 @@ proc adi_ip_create {ip_name} {
 
   create_project $ip_name . -force
 
+  set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
+  set_msg_config -id {IP_Flow 19-2999} -new_severity INFO 
+  set_msg_config -id {IP_Flow 19-1654} -new_severity INFO 
+  set_msg_config -id {IP_Flow 19-459} -new_severity INFO 
+
   set lib_dirs $ad_hdl_dir/library
   if {$ad_hdl_dir ne $ad_phdl_dir} {
     lappend lib_dirs $ad_phdl_dir/library
@@ -113,6 +118,9 @@ proc adi_ip_properties {ip_name} {
   set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
     -of_objects [ipx::get_bus_interfaces s_axi_aclk \
     -of_objects [ipx::current_core]]]
+}
+
+proc adi_ip_infer_interfaces {ip_name} {
 
   ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
   ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
@@ -122,11 +130,11 @@ proc adi_ip_properties {ip_name} {
 
 proc adi_ip_properties_lite {ip_name} {
 
-  ipx::package_project -root_dir .
+  ipx::package_project -root_dir . \
+    -vendor {analog.com} \
+    -library {user} \
+    -taxonomy {{/AXI_Infrastructure}} 
 
-  set_property vendor {analog.com} [ipx::current_core]
-  set_property library {user} [ipx::current_core]
-  set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
   set_property vendor_display_name {Analog Devices} [ipx::current_core]
   set_property company_url {www.analog.com} [ipx::current_core]
 
@@ -151,7 +159,6 @@ proc adi_ip_properties_lite {ip_name} {
   [ipx::current_core]
 
   ipx::remove_all_bus_interface [ipx::current_core]
-
 }
 
 proc adi_set_ports_dependency {port_prefix dependency} {

From 3b2bde2fa1a546d44bd0ac8944b4df7a08837183 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:38:39 -0400
Subject: [PATCH 347/972] hdl-vivado-2016.2- min. addr-space requirement

---
 projects/scripts/adi_board.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 6454d2079..f3a8f0cd3 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -400,6 +400,9 @@ proc ad_cpu_interconnect {p_address p_name} {
   foreach p_seg_name $p_seg {
     if {($p_index == 0) && ($sys_zynq < 2)} {
       set p_seg_range [get_property range $p_seg_name]
+      if {$p_seg_range < 0x1000} {
+        set p_seg_range 0x1000
+      }
       create_bd_addr_seg -range $p_seg_range \
         -offset $p_address $sys_addr_cntrl_space \
         $p_seg_name "SEG_data_${p_name}"

From 6ffe59728b6e4312d1160e7ac47e3c655f3f8d57 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:39:07 -0400
Subject: [PATCH 348/972] hdl-vivado-2016.2- update

---
 projects/scripts/adi_project.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index d715725eb..77101fc33 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -7,7 +7,7 @@ variable p_prcfg_list
 variable p_prcfg_status
 
 if {![info exists REQUIRED_VIVADO_VERSION]} {
-  set REQUIRED_VIVADO_VERSION "2015.4.2"
+  set REQUIRED_VIVADO_VERSION "2016.2"
 }
 
 if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {

From 52b544bb665972b76651473a6a85076e77e765e0 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:41:13 -0400
Subject: [PATCH 349/972] hdl-vivado-2016.2- auto infer bus interfaces

---
 library/axi_dmac/axi_dmac_ip.tcl         | 1 +
 library/axi_i2s_adi/axi_i2s_adi_ip.tcl   | 1 +
 library/axi_spdif_rx/axi_spdif_rx_ip.tcl | 1 +
 library/axi_spdif_tx/axi_spdif_tx_ip.tcl | 1 +
 4 files changed, 4 insertions(+)

diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl
index d6a6668d0..293a6b7a8 100644
--- a/library/axi_dmac/axi_dmac_ip.tcl
+++ b/library/axi_dmac/axi_dmac_ip.tcl
@@ -27,6 +27,7 @@ adi_ip_files axi_dmac [list \
   "bd/bd.tcl" ]
 
 adi_ip_properties axi_dmac
+adi_ip_infer_interfaces axi_dmac
 adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl"
 adi_ip_bd axi_dmac "bd/bd.tcl"
 
diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
index d30ec0834..a64232731 100644
--- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
+++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
@@ -20,6 +20,7 @@ adi_ip_files axi_i2s_adi [list \
 ]
 
 adi_ip_properties axi_i2s_adi
+adi_ip_infer_interfaces axi_i2s_adi
 adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late
 
 adi_add_bus "DMA_ACK_RX" "slave" \
diff --git a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl
index 9b22be7d6..ad44ef4ef 100644
--- a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl
+++ b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl
@@ -17,6 +17,7 @@ adi_ip_files axi_spdif_rx [list \
   "axi_spdif_rx_constr.xdc"]
 
 adi_ip_properties axi_spdif_rx
+adi_ip_infer_interfaces axi_spdif_rx
 adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc
 
 adi_add_bus "DMA_ACK" "slave" \
diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl
index fdc4c38c3..eece3075d 100644
--- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl
+++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl
@@ -15,6 +15,7 @@ adi_ip_files axi_spdif_tx [list \
   "axi_spdif_tx_constr.xdc" ]
 
 adi_ip_properties axi_spdif_tx
+adi_ip_infer_interfaces axi_spdif_tx
 adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc
 
 adi_add_bus "DMA_ACK" "slave" \

From d5d61ff51898a609084d726397db15bb517c845b Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:42:30 -0400
Subject: [PATCH 350/972] hdl-vivado-2016.2- productivity decimated again!

---
 library/util_bsplit/util_bsplit_ip.tcl | 14 +++++++-------
 library/util_ccat/util_ccat_ip.tcl     | 14 +++++++-------
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/library/util_bsplit/util_bsplit_ip.tcl b/library/util_bsplit/util_bsplit_ip.tcl
index 5791f5948..64440b9f8 100644
--- a/library/util_bsplit/util_bsplit_ip.tcl
+++ b/library/util_bsplit/util_bsplit_ip.tcl
@@ -13,31 +13,31 @@ adi_ip_constraints util_bsplit [list \
   "util_bsplit_constr.xdc" ]
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \
-  [ipx::get_port split_data_1 [ipx::current_core]] \
+  [ipx::get_ports *_1* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \
-  [ipx::get_port split_data_2 [ipx::current_core]] \
+  [ipx::get_ports *_2* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \
-  [ipx::get_port split_data_3 [ipx::current_core]] \
+  [ipx::get_ports *_3* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \
-  [ipx::get_port split_data_4 [ipx::current_core]] \
+  [ipx::get_ports *_4* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \
-  [ipx::get_port split_data_5 [ipx::current_core]] \
+  [ipx::get_ports *_5* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \
-  [ipx::get_port split_data_6 [ipx::current_core]] \
+  [ipx::get_ports *_6* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \
-  [ipx::get_port split_data_7 [ipx::current_core]] \
+  [ipx::get_ports *_7* -of_objects [ipx::current_core]] \
 
 
 ipx::save_core [ipx::current_core]
diff --git a/library/util_ccat/util_ccat_ip.tcl b/library/util_ccat/util_ccat_ip.tcl
index eb326e84c..3d5843e76 100644
--- a/library/util_ccat/util_ccat_ip.tcl
+++ b/library/util_ccat/util_ccat_ip.tcl
@@ -13,31 +13,31 @@ adi_ip_constraints util_ccat [list \
   "util_ccat_constr.xdc" ]
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \
-  [ipx::get_port data_1 [ipx::current_core]] \
+  [ipx::get_ports *_1* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \
-  [ipx::get_port data_2 [ipx::current_core]] \
+  [ipx::get_ports *_2* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \
-  [ipx::get_port data_3 [ipx::current_core]] \
+  [ipx::get_ports *_3* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \
-  [ipx::get_port data_4 [ipx::current_core]] \
+  [ipx::get_ports *_4* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \
-  [ipx::get_port data_5 [ipx::current_core]] \
+  [ipx::get_ports *_5* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \
-  [ipx::get_port data_6 [ipx::current_core]] \
+  [ipx::get_ports *_6* -of_objects [ipx::current_core]] \
 
 
 set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \
-  [ipx::get_port data_7 [ipx::current_core]] \
+  [ipx::get_ports *_7* -of_objects [ipx::current_core]] \
 
 
 ipx::save_core [ipx::current_core]

From 39ff059ef641dfbc1cf3e362d005421d391588c1 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:42:53 -0400
Subject: [PATCH 351/972] hdl-vivado-2016.2- productivity decimated again!

---
 library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl
index be06aa5d8..12ad32b92 100644
--- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl
+++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl
@@ -15,7 +15,7 @@ adi_ip_constraints util_gmii_to_rgmii [list \
   "util_gmii_to_rgmii_constr.xdc" ]
 
 ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core]
-set_property name {gmii} [ipx::get_bus_interface gmii_1 [ipx::current_core]]
+set_property name {gmii} [ipx::get_bus_interfaces gmii_1 -of_objects [ipx::current_core]]
 ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \

From 9952a94efbc2dd778f78228158c21a7461fcfebc Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Thu, 28 Jul 2016 13:44:41 -0400
Subject: [PATCH 352/972] hdl-vivado-2016.2- ip version updates

---
 projects/common/zc706/zc706_system_bd.tcl             | 2 +-
 projects/common/zc706/zc706_system_mig.prj            | 3 ++-
 projects/common/zc706/zc706_system_plddr3_adcfifo.tcl | 2 +-
 projects/daq2/common/daq2_bd.tcl                      | 4 ++--
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl
index 49380211b..0a1776c7c 100644
--- a/projects/common/zc706/zc706_system_bd.tcl
+++ b/projects/common/zc706/zc706_system_bd.tcl
@@ -103,7 +103,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
 
 # audio peripherals
 
-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
 set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
 set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
diff --git a/projects/common/zc706/zc706_system_mig.prj b/projects/common/zc706/zc706_system_mig.prj
index 5823f5a31..e56ffb640 100644
--- a/projects/common/zc706/zc706_system_mig.prj
+++ b/projects/common/zc706/zc706_system_mig.prj
@@ -9,7 +9,7 @@
     <LowPower_En>ON</LowPower_En>
     <XADC_En>Disabled</XADC_En>
     <TargetFPGA>xc7z045-ffg900/-2</TargetFPGA>
-    <Version>2.1</Version>
+    <Version>4.0</Version>
     <SystemClock>Differential</SystemClock>
     <ReferenceClock>Use System Clock</ReferenceClock>
     <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
@@ -24,6 +24,7 @@
         <PHYRatio>4:1</PHYRatio>
         <InputClkFreq>200</InputClkFreq>
         <UIExtraClocks>1</UIExtraClocks>
+        <MMCM_VCO>800</MMCM_VCO>
         <MMCMClkOut0> 1.000</MMCMClkOut0>
         <MMCMClkOut1>1</MMCMClkOut1>
         <MMCMClkOut2>1</MMCMClkOut2>
diff --git a/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
index 1be9c1e41..d71ee94f6 100644
--- a/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
@@ -31,7 +31,7 @@ proc p_plddr3_adcfifo {p_name m_name adc_data_width} {
   create_bd_pin -dir I dma_xfer_req
   create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
 
-  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
+  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl]
   set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
   file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
   set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index b6e0c9c50..b266cb135 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -37,7 +37,7 @@ set sys_ad9144_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_rese
 set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
 set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core
 
-set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd]
+set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
 
@@ -68,7 +68,7 @@ set sys_ad9680_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_rese
 
 set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
 
-set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
+set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
 

From 71dad14e0e2abea5ff64cc6fde4a7f7f4fb3b762 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Fri, 29 Jul 2016 09:37:17 -0400
Subject: [PATCH 353/972] axi_adcfifo- disable auto infer mess-up

---
 library/axi_adcfifo/axi_adcfifo_ip.tcl | 61 +++++++++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/library/axi_adcfifo/axi_adcfifo_ip.tcl b/library/axi_adcfifo/axi_adcfifo_ip.tcl
index 3b3fecd9c..7343caa24 100644
--- a/library/axi_adcfifo/axi_adcfifo_ip.tcl
+++ b/library/axi_adcfifo/axi_adcfifo_ip.tcl
@@ -20,7 +20,66 @@ adi_ip_properties_lite axi_adcfifo
 adi_ip_constraints axi_adcfifo [list \
   "axi_adcfifo_constr.xdc" ]
 
-ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]
+ipx::infer_bus_interface {\
+  axi_awvalid \
+  axi_awid \
+  axi_awburst \
+  axi_awlock \
+  axi_awcache \
+  axi_awprot \
+  axi_awqos \
+  axi_awuser \
+  axi_awlen \
+  axi_awsize \
+  axi_awaddr \
+  axi_awready \
+  axi_wvalid \
+  axi_wdata \
+  axi_wstrb \
+  axi_wlast \
+  axi_wuser \
+  axi_wready \
+  axi_bvalid \
+  axi_bid \
+  axi_bresp \
+  axi_buser \
+  axi_bready \
+  axi_arvalid \
+  axi_arid \
+  axi_arburst \
+  axi_arlock \
+  axi_arcache \
+  axi_arprot \
+  axi_arqos \
+  axi_aruser \
+  axi_arlen \
+  axi_arsize \
+  axi_araddr \
+  axi_arready \
+  axi_rvalid \
+  axi_rid \
+  axi_ruser \
+  axi_rresp \
+  axi_rlast \
+  axi_rdata \
+  axi_rready} \
+xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
+  -of_objects [ipx::current_core]]
+set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
+  -of_objects [ipx::get_bus_interfaces axi_clk \
+  -of_objects [ipx::current_core]]]
+
+ipx::add_address_space axi [ipx::current_core]
+set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
+  -of_objects [ipx::current_core]]
+set_property range 4294967296 [ipx::get_address_spaces axi \
+  -of_objects [ipx::current_core]]
+set_property width 512 [ipx::get_address_spaces axi \
+  -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]
 

From 4aa506de8dc5b6c6fcb23702d7fe1fa2d2bdbfbc Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Fri, 29 Jul 2016 09:38:08 -0400
Subject: [PATCH 354/972] adxcvr- added a space?

---
 library/axi_adxcvr/axi_adxcvr_ip.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_adxcvr/axi_adxcvr_ip.tcl b/library/axi_adxcvr/axi_adxcvr_ip.tcl
index b4dc7583b..914b06a0c 100644
--- a/library/axi_adxcvr/axi_adxcvr_ip.tcl
+++ b/library/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -74,6 +74,7 @@ set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_obj
 ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
 set_property range {4096} [ipx::get_address_blocks axi_lite \
   -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
+
 for {set n 0} {$n < 16} {incr n} {
 
   if {($n%4) == 0} {

From 7988d2c7a29b8dbf06be214ab7bcd9a504d02ae6 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 29 Jul 2016 12:32:19 -0400
Subject: [PATCH 355/972] adi_ip: remove duplicated errored auto address maps &
 interfaces

---
 library/scripts/adi_ip.tcl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl
index 9987a4780..c11f2a03e 100644
--- a/library/scripts/adi_ip.tcl
+++ b/library/scripts/adi_ip.tcl
@@ -158,7 +158,8 @@ proc adi_ip_properties_lite {ip_name} {
     kintexu       Production}\
   [ipx::current_core]
 
-  ipx::remove_all_bus_interface [ipx::current_core]
+  ipx::remove_all_bus_interface -quiet [ipx::current_core]
+  ipx::remove_all_address_block -quiet [ipx::get_memory_maps * -of_objects [ipx::current_core]]
 }
 
 proc adi_set_ports_dependency {port_prefix dependency} {

From 58b220ba816389ee17d0259074dbcee70b60b34b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 28 Jul 2016 13:29:09 +0300
Subject: [PATCH 356/972] ad_tdd_control: Add an on/off switch to the receive
 datapath

For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
---
 library/axi_ad9361/axi_ad9361_tdd.v | 27 +++++++---
 library/common/ad_tdd_control.v     | 81 +++++++++++++++++++++++++++--
 library/common/up_tdd_cntrl.v       | 58 ++++++++++++++++++---
 3 files changed, 146 insertions(+), 20 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index d32984860..8a5fb9144 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -192,6 +192,8 @@ module axi_ad9361_tdd (
   wire    [23:0]    tdd_vco_tx_off_1_s;
   wire    [23:0]    tdd_rx_on_1_s;
   wire    [23:0]    tdd_rx_off_1_s;
+  wire    [23:0]    tdd_rx_dp_on_1_s;
+  wire    [23:0]    tdd_rx_dp_off_1_s;
   wire    [23:0]    tdd_tx_on_1_s;
   wire    [23:0]    tdd_tx_off_1_s;
   wire    [23:0]    tdd_tx_dp_on_1_s;
@@ -202,6 +204,8 @@ module axi_ad9361_tdd (
   wire    [23:0]    tdd_vco_tx_off_2_s;
   wire    [23:0]    tdd_rx_on_2_s;
   wire    [23:0]    tdd_rx_off_2_s;
+  wire    [23:0]    tdd_rx_dp_on_2_s;
+  wire    [23:0]    tdd_rx_dp_off_2_s;
   wire    [23:0]    tdd_tx_on_2_s;
   wire    [23:0]    tdd_tx_off_2_s;
   wire    [23:0]    tdd_tx_dp_on_2_s;
@@ -209,6 +213,7 @@ module axi_ad9361_tdd (
 
   wire    [23:0]    tdd_counter_status;
 
+  wire              tdd_rx_dp_en_s;
   wire              tdd_tx_dp_en_s;
 
   assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_sync, tdd_tx_dp_en_s,
@@ -237,10 +242,10 @@ module axi_ad9361_tdd (
 
   always @(posedge clk) begin
     if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
-      tdd_rx_valid_i0 <= rx_valid_i0 & tdd_rx_rf_en;
-      tdd_rx_valid_q0 <= rx_valid_q0 & tdd_rx_rf_en;
-      tdd_rx_valid_i1 <= rx_valid_i1 & tdd_rx_rf_en;
-      tdd_rx_valid_q1 <= rx_valid_q1 & tdd_rx_rf_en;
+      tdd_rx_valid_i0 <= rx_valid_i0 & tdd_rx_dp_en_s;
+      tdd_rx_valid_q0 <= rx_valid_q0 & tdd_rx_dp_en_s;
+      tdd_rx_valid_i1 <= rx_valid_i1 & tdd_rx_dp_en_s;
+      tdd_rx_valid_q1 <= rx_valid_q1 & tdd_rx_dp_en_s;
     end else begin
       tdd_rx_valid_i0 <= rx_valid_i0;
       tdd_rx_valid_q0 <= rx_valid_q0;
@@ -249,7 +254,6 @@ module axi_ad9361_tdd (
     end
   end
 
-
   // instantiations
 
   up_tdd_cntrl i_up_tdd_cntrl(
@@ -271,6 +275,8 @@ module axi_ad9361_tdd (
     .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
     .tdd_rx_on_1(tdd_rx_on_1_s),
     .tdd_rx_off_1(tdd_rx_off_1_s),
+    .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
+    .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
     .tdd_tx_on_1(tdd_tx_on_1_s),
     .tdd_tx_off_1(tdd_tx_off_1_s),
     .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
@@ -281,6 +287,8 @@ module axi_ad9361_tdd (
     .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
     .tdd_rx_on_2(tdd_rx_on_2_s),
     .tdd_rx_off_2(tdd_rx_off_2_s),
+    .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
+    .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
     .tdd_tx_on_2(tdd_tx_on_2_s),
     .tdd_tx_off_2(tdd_tx_off_2_s),
     .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
@@ -301,8 +309,8 @@ module axi_ad9361_tdd (
   // for the axi_ad9361 core
 
   ad_tdd_control #(
-    .TX_DATA_PATH_DELAY(14),
-    .CONTROL_PATH_DELAY(3))
+    .TX_DATA_PATH_DELAY(),
+    .CONTROL_PATH_DELAY())
   i_tdd_control(
     .clk(clk),
     .rst(rst),
@@ -320,6 +328,8 @@ module axi_ad9361_tdd (
     .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
     .tdd_rx_on_1(tdd_rx_on_1_s),
     .tdd_rx_off_1(tdd_rx_off_1_s),
+    .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
+    .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
     .tdd_tx_on_1(tdd_tx_on_1_s),
     .tdd_tx_off_1(tdd_tx_off_1_s),
     .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
@@ -330,10 +340,13 @@ module axi_ad9361_tdd (
     .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
     .tdd_rx_on_2(tdd_rx_on_2_s),
     .tdd_rx_off_2(tdd_rx_off_2_s),
+    .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
+    .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
     .tdd_tx_on_2(tdd_tx_on_2_s),
     .tdd_tx_off_2(tdd_tx_off_2_s),
     .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
     .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
+    .tdd_rx_dp_en(tdd_rx_dp_en_s),
     .tdd_tx_dp_en(tdd_tx_dp_en_s),
     .tdd_rx_vco_en(tdd_rx_vco_en),
     .tdd_tx_vco_en(tdd_tx_vco_en),
diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v
index af9b6b61e..151a3edeb 100644
--- a/library/common/ad_tdd_control.v
+++ b/library/common/ad_tdd_control.v
@@ -61,6 +61,8 @@ module ad_tdd_control(
   tdd_vco_tx_off_1,
   tdd_rx_on_1,
   tdd_rx_off_1,
+  tdd_rx_dp_on_1,
+  tdd_rx_dp_off_1,
   tdd_tx_on_1,
   tdd_tx_off_1,
   tdd_tx_dp_on_1,
@@ -71,6 +73,8 @@ module ad_tdd_control(
   tdd_vco_tx_off_2,
   tdd_rx_on_2,
   tdd_rx_off_2,
+  tdd_rx_dp_on_2,
+  tdd_rx_dp_off_2,
   tdd_tx_on_2,
   tdd_tx_off_2,
   tdd_tx_dp_on_2,
@@ -80,6 +84,7 @@ module ad_tdd_control(
   // TDD control signals
 
   tdd_tx_dp_en,
+  tdd_rx_dp_en,
   tdd_rx_vco_en,
   tdd_tx_vco_en,
   tdd_rx_rf_en,
@@ -113,6 +118,8 @@ module ad_tdd_control(
   input  [23:0]   tdd_vco_tx_off_1;
   input  [23:0]   tdd_rx_on_1;
   input  [23:0]   tdd_rx_off_1;
+  input  [23:0]   tdd_rx_dp_on_1;
+  input  [23:0]   tdd_rx_dp_off_1;
   input  [23:0]   tdd_tx_on_1;
   input  [23:0]   tdd_tx_off_1;
   input  [23:0]   tdd_tx_dp_on_1;
@@ -123,6 +130,8 @@ module ad_tdd_control(
   input  [23:0]   tdd_vco_tx_off_2;
   input  [23:0]   tdd_rx_on_2;
   input  [23:0]   tdd_rx_off_2;
+  input  [23:0]   tdd_rx_dp_on_2;
+  input  [23:0]   tdd_rx_dp_off_2;
   input  [23:0]   tdd_tx_on_2;
   input  [23:0]   tdd_tx_off_2;
   input  [23:0]   tdd_tx_dp_on_2;
@@ -130,17 +139,19 @@ module ad_tdd_control(
 
   input           tdd_sync;
 
-  output          tdd_tx_dp_en;       // initiate vco tx2rx switch
-  output          tdd_rx_vco_en;      // initiate vco rx2tx switch
-  output          tdd_tx_vco_en;      // power up RF Rx
-  output          tdd_rx_rf_en;       // power up RF Tx
-  output          tdd_tx_rf_en;       // enable Tx datapath
+  output          tdd_rx_vco_en;      // initiate vco tx2rx switch
+  output          tdd_tx_vco_en;      // initiate vco rx2tx switch
+  output          tdd_rx_rf_en;       // power up RF Rx
+  output          tdd_tx_rf_en;       // power up RF Tx
+  output          tdd_tx_dp_en;       // enable Tx datapath
+  output          tdd_rx_dp_en;       // enable Rx datapath
 
   output [23:0]   tdd_counter_status;
 
   // tdd control related
 
   reg             tdd_tx_dp_en = 1'b0;
+  reg             tdd_rx_dp_en = 1'b0;
   reg             tdd_rx_vco_en = 1'b0;
   reg             tdd_tx_vco_en = 1'b0;
   reg             tdd_rx_rf_en = 1'b0;
@@ -160,6 +171,8 @@ module ad_tdd_control(
   reg             counter_at_tdd_vco_tx_off_1 = 1'b0;
   reg             counter_at_tdd_rx_on_1 = 1'b0;
   reg             counter_at_tdd_rx_off_1 = 1'b0;
+  reg             counter_at_tdd_rx_dp_on_1 = 1'b0;
+  reg             counter_at_tdd_rx_dp_off_1 = 1'b0;
   reg             counter_at_tdd_tx_on_1 = 1'b0;
   reg             counter_at_tdd_tx_off_1 = 1'b0;
   reg             counter_at_tdd_tx_dp_on_1 = 1'b0;
@@ -170,6 +183,8 @@ module ad_tdd_control(
   reg             counter_at_tdd_vco_tx_off_2 = 1'b0;
   reg             counter_at_tdd_rx_on_2 = 1'b0;
   reg             counter_at_tdd_rx_off_2 = 1'b0;
+  reg             counter_at_tdd_rx_dp_on_2 = 1'b0;
+  reg             counter_at_tdd_rx_dp_off_2 = 1'b0;
   reg             counter_at_tdd_tx_on_2 = 1'b0;
   reg             counter_at_tdd_tx_off_2 = 1'b0;
   reg             counter_at_tdd_tx_dp_on_2 = 1'b0;
@@ -499,6 +514,48 @@ module ad_tdd_control(
     end
   end
 
+  // start/stop rx data path
+  always @(posedge clk) begin
+    if(rst == 1'b1) begin
+      counter_at_tdd_rx_dp_on_1 <= 1'b0;
+    end else if(tdd_counter == tdd_rx_dp_on_1) begin
+      counter_at_tdd_rx_dp_on_1 <= 1'b1;
+    end else begin
+      counter_at_tdd_rx_dp_on_1 <= 1'b0;
+    end
+  end
+
+  always @(posedge clk) begin
+    if(rst == 1'b1) begin
+      counter_at_tdd_rx_dp_on_2 <= 1'b0;
+    end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_on_2)) begin
+      counter_at_tdd_rx_dp_on_2 <= 1'b1;
+    end else begin
+      counter_at_tdd_rx_dp_on_2 <= 1'b0;
+    end
+  end
+
+  always @(posedge clk) begin
+    if(rst == 1'b1) begin
+      counter_at_tdd_rx_dp_off_1 <= 1'b0;
+    end else if(tdd_counter == tdd_rx_dp_off_1) begin
+      counter_at_tdd_rx_dp_off_1 <= 1'b1;
+    end else begin
+      counter_at_tdd_rx_dp_off_1 <= 1'b0;
+    end
+  end
+
+  always @(posedge clk) begin
+    if(rst == 1'b1) begin
+      counter_at_tdd_rx_dp_off_2 <= 1'b0;
+    end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_off_2)) begin
+      counter_at_tdd_rx_dp_off_2 <= 1'b1;
+    end else begin
+      counter_at_tdd_rx_dp_off_2 <= 1'b0;
+    end
+  end
+
+
   // control-path delay compensation
 
   ad_addsub #(
@@ -817,5 +874,19 @@ module ad_tdd_control(
     end
   end
 
+  always @(posedge clk) begin
+    if(rst == 1'b1) begin
+      tdd_rx_dp_en <= 1'b0;
+    end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_dp_off_1 == 1'b1) || (counter_at_tdd_rx_dp_off_2 == 1'b1)) begin
+      tdd_rx_dp_en <= 1'b0;
+    end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin
+      tdd_rx_dp_en <= 1'b1;
+    end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
+      tdd_rx_dp_en <= tdd_rx_only;
+    end else begin
+      tdd_rx_dp_en <= tdd_rx_dp_en;
+    end
+  end
+
 endmodule
 
diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v
index c77da4ff4..9ef59b490 100644
--- a/library/common/up_tdd_cntrl.v
+++ b/library/common/up_tdd_cntrl.v
@@ -61,6 +61,8 @@ module up_tdd_cntrl (
   tdd_vco_tx_off_1,
   tdd_rx_on_1,
   tdd_rx_off_1,
+  tdd_rx_dp_on_1,
+  tdd_rx_dp_off_1,
   tdd_tx_on_1,
   tdd_tx_off_1,
   tdd_tx_dp_on_1,
@@ -71,6 +73,8 @@ module up_tdd_cntrl (
   tdd_vco_tx_off_2,
   tdd_rx_on_2,
   tdd_rx_off_2,
+  tdd_rx_dp_on_2,
+  tdd_rx_dp_off_2,
   tdd_tx_on_2,
   tdd_tx_off_2,
   tdd_tx_dp_on_2,
@@ -115,6 +119,8 @@ module up_tdd_cntrl (
   output  [23:0]  tdd_vco_tx_off_1;
   output  [23:0]  tdd_rx_on_1;
   output  [23:0]  tdd_rx_off_1;
+  output  [23:0]  tdd_rx_dp_on_1;
+  output  [23:0]  tdd_rx_dp_off_1;
   output  [23:0]  tdd_tx_on_1;
   output  [23:0]  tdd_tx_off_1;
   output  [23:0]  tdd_tx_dp_on_1;
@@ -125,6 +131,8 @@ module up_tdd_cntrl (
   output  [23:0]  tdd_vco_tx_off_2;
   output  [23:0]  tdd_rx_on_2;
   output  [23:0]  tdd_rx_off_2;
+  output  [23:0]  tdd_rx_dp_on_2;
+  output  [23:0]  tdd_rx_dp_off_2;
   output  [23:0]  tdd_tx_on_2;
   output  [23:0]  tdd_tx_off_2;
   output  [23:0]  tdd_tx_dp_on_2;
@@ -170,6 +178,8 @@ module up_tdd_cntrl (
   reg     [23:0]  up_tdd_vco_tx_off_1 = 24'h0;
   reg     [23:0]  up_tdd_rx_on_1 = 24'h0;
   reg     [23:0]  up_tdd_rx_off_1 = 24'h0;
+  reg     [23:0]  up_tdd_rx_dp_on_1 = 24'h0;
+  reg     [23:0]  up_tdd_rx_dp_off_1 = 24'h0;
   reg     [23:0]  up_tdd_tx_on_1 = 24'h0;
   reg     [23:0]  up_tdd_tx_off_1 = 24'h0;
   reg     [23:0]  up_tdd_tx_dp_on_1 = 24'h0;
@@ -180,6 +190,8 @@ module up_tdd_cntrl (
   reg     [23:0]  up_tdd_vco_tx_off_2 = 24'h0;
   reg     [23:0]  up_tdd_rx_on_2 = 24'h0;
   reg     [23:0]  up_tdd_rx_off_2 = 24'h0;
+  reg     [23:0]  up_tdd_rx_dp_on_2 = 24'h0;
+  reg     [23:0]  up_tdd_rx_dp_off_2 = 24'h0;
   reg     [23:0]  up_tdd_tx_on_2 = 24'h0;
   reg     [23:0]  up_tdd_tx_off_2 = 24'h0;
   reg     [23:0]  up_tdd_tx_dp_on_2 = 24'h0;
@@ -219,18 +231,24 @@ module up_tdd_cntrl (
       up_tdd_vco_tx_off_1 <= 24'h0;
       up_tdd_rx_on_1 <= 24'h0;
       up_tdd_rx_off_1 <= 24'h0;
+      up_tdd_rx_dp_on_1 <= 24'h0;
+      up_tdd_rx_dp_off_1 <= 24'h0;
       up_tdd_tx_on_1 <= 24'h0;
       up_tdd_tx_off_1 <= 24'h0;
       up_tdd_tx_dp_on_1 <= 24'h0;
+      up_tdd_tx_dp_off_1 <= 24'h0;
       up_tdd_vco_rx_on_2 <= 24'h0;
       up_tdd_vco_rx_off_2 <= 24'h0;
       up_tdd_vco_tx_on_2 <= 24'h0;
       up_tdd_vco_tx_off_2 <= 24'h0;
       up_tdd_rx_on_2 <= 24'h0;
       up_tdd_rx_off_2 <= 24'h0;
+      up_tdd_rx_dp_on_2 <= 24'h0;
+      up_tdd_rx_dp_off_2 <= 24'h0;
       up_tdd_tx_on_2 <= 24'h0;
       up_tdd_tx_off_2 <= 24'h0;
       up_tdd_tx_dp_on_2 <= 24'h0;
+      up_tdd_tx_dp_off_2 <= 24'h0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@@ -281,9 +299,15 @@ module up_tdd_cntrl (
         up_tdd_tx_off_1 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
-        up_tdd_tx_dp_on_1 <= up_wdata[23:0];
+        up_tdd_rx_dp_on_1 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
+        up_tdd_rx_dp_off_1 <= up_wdata[23:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin
+        up_tdd_tx_dp_on_1 <= up_wdata[23:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin
         up_tdd_tx_dp_off_1 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
@@ -308,14 +332,20 @@ module up_tdd_cntrl (
         up_tdd_tx_on_2 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
-        up_tdd_tx_off_2 <= up_wdata[23:0];
+        up_tdd_rx_off_2 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
-        up_tdd_tx_dp_on_2 <= up_wdata[23:0];
+        up_tdd_rx_dp_on_2 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
         up_tdd_tx_dp_off_2 <= up_wdata[23:0];
       end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin
+        up_tdd_tx_dp_on_2 <= up_wdata[23:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3b)) begin
+        up_tdd_tx_dp_off_2 <= up_wdata[23:0];
+      end
     end
   end
 
@@ -351,8 +381,10 @@ module up_tdd_cntrl (
           8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1};
           8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1};
           8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1};
-          8'h28: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
-          8'h29: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
+          8'h28: up_rdata <= { 8'h0, up_tdd_rx_dp_on_1};
+          8'h29: up_rdata <= { 8'h0, up_tdd_rx_dp_off_1};
+          8'h2a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
+          8'h2b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
           8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2};
           8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2};
           8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2};
@@ -361,8 +393,10 @@ module up_tdd_cntrl (
           8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2};
           8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2};
           8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2};
-          8'h38: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
-          8'h39: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
+          8'h38: up_rdata <= { 8'h0, up_tdd_rx_dp_on_2};
+          8'h39: up_rdata <= { 8'h0, up_tdd_rx_dp_off_2};
+          8'h3a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
+          8'h3b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
           default: up_rdata <= 32'h0;
         endcase
       end
@@ -396,7 +430,7 @@ module up_tdd_cntrl (
                    tdd_terminal_type
     }));
 
-  up_xfer_cntrl #(.DATA_WIDTH(528)) i_xfer_tdd_counter_values (
+  up_xfer_cntrl #(.DATA_WIDTH(624)) i_xfer_tdd_counter_values (
     .up_rstn(up_rstn),
     .up_clk(up_clk),
     .up_data_cntrl({up_tdd_counter_init,
@@ -409,6 +443,8 @@ module up_tdd_cntrl (
                     up_tdd_rx_off_1,
                     up_tdd_tx_on_1,
                     up_tdd_tx_off_1,
+                    up_tdd_rx_dp_on_1,
+                    up_tdd_rx_dp_off_1,
                     up_tdd_tx_dp_on_1,
                     up_tdd_tx_dp_off_1,
                     up_tdd_vco_rx_on_2,
@@ -419,6 +455,8 @@ module up_tdd_cntrl (
                     up_tdd_rx_off_2,
                     up_tdd_tx_on_2,
                     up_tdd_tx_off_2,
+                    up_tdd_rx_dp_on_2,
+                    up_tdd_rx_dp_off_2,
                     up_tdd_tx_dp_on_2,
                     up_tdd_tx_dp_off_2
     }),
@@ -435,6 +473,8 @@ module up_tdd_cntrl (
                    tdd_rx_off_1,
                    tdd_tx_on_1,
                    tdd_tx_off_1,
+                   tdd_rx_dp_on_1,
+                   tdd_rx_dp_off_1,
                    tdd_tx_dp_on_1,
                    tdd_tx_dp_off_1,
                    tdd_vco_rx_on_2,
@@ -445,6 +485,8 @@ module up_tdd_cntrl (
                    tdd_rx_off_2,
                    tdd_tx_on_2,
                    tdd_tx_off_2,
+                   tdd_rx_dp_on_2,
+                   tdd_rx_dp_off_2,
                    tdd_tx_dp_on_2,
                    tdd_tx_dp_off_2
     }));

From b99117e68658eeefffb01260513e70331c77f9a1 Mon Sep 17 00:00:00 2001
From: Matthew Fornero <matt.fornero@mathworks.com>
Date: Tue, 19 Jul 2016 09:41:33 -0700
Subject: [PATCH 357/972] up_axi: Same cycle BVALID/READY fails on Altera

The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22b5faf232a73e52fd9578ae89a66c4b
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
---
 library/common/up_axi.v | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/library/common/up_axi.v b/library/common/up_axi.v
index 681a49f94..2d5e3e503 100644
--- a/library/common/up_axi.v
+++ b/library/common/up_axi.v
@@ -129,6 +129,7 @@ module up_axi (
   reg     [31:0]  up_wdata = 'd0;
   reg     [ 2:0]  up_wcount = 'd0;
   reg             up_wack_int = 'd0;
+  reg             up_wack_int_d = 'd0;
   reg             up_axi_arready = 'd0;
   reg             up_axi_rvalid = 'd0;
   reg     [31:0]  up_axi_rdata = 'd0;
@@ -163,7 +164,7 @@ module up_axi (
       end
       if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
         up_axi_bvalid <= 1'b0;
-      end else if (up_wack_int == 1'b1) begin
+      end else if (up_wack_int_d == 1'b1) begin
         up_axi_bvalid <= 1'b1;
       end
     end
@@ -198,12 +199,14 @@ module up_axi (
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_wack_int <= 'd0;
+      up_wack_int_d <= 'd0;
     end else begin
       if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin
         up_wack_int <= 1'b1;
       end else if (up_wsel == 1'b1) begin
         up_wack_int <= up_wack;
       end
+      up_wack_int_d <= up_wack_int;
     end
   end
 

From fbe3d75eb043cbf3d49a8aecc65979a91b1bf85d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 1 Aug 2016 13:46:46 +0300
Subject: [PATCH 358/972] cosmetics: Delete trailing whitespace characters

---
 library/axi_jesd_gt/axi_jesd_gt_ip.tcl | 56 +++++++++++++-------------
 projects/pzsdr/common/ccfmc_bd.tcl     |  4 +-
 2 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
index e85b0ba1a..dd035f77f 100644
--- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
+++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
@@ -115,65 +115,65 @@ for {set n 0} {$n < 8} {incr n} {
 }
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL0_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_qpll_0 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_qpll_0 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL1_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_qpll_1 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_qpll_1 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
-  [ipx::get_bus_interfaces gt_pll_0 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_pll_0 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
-  [ipx::get_bus_interfaces gt_pll_1 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_pll_1 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
-  [ipx::get_bus_interfaces gt_pll_2 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_pll_2 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
-  [ipx::get_bus_interfaces gt_pll_3 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_pll_3 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
-  [ipx::get_bus_interfaces gt_pll_4 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_pll_4 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
-  [ipx::get_bus_interfaces gt_pll_5 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_pll_5 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
-  [ipx::get_bus_interfaces gt_pll_6 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_pll_6 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
-  [ipx::get_bus_interfaces gt_pll_7 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_pll_7 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
-  [ipx::get_bus_interfaces gt_rx_*0 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_rx_*0 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
-  [ipx::get_bus_interfaces gt_rx_*1 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_rx_*1 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
-  [ipx::get_bus_interfaces gt_rx_*2 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_rx_*2 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
-  [ipx::get_bus_interfaces gt_rx_*3 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_rx_*3 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
-  [ipx::get_bus_interfaces gt_rx_*4 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_rx_*4 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
-  [ipx::get_bus_interfaces gt_rx_*5 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_rx_*5 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
-  [ipx::get_bus_interfaces gt_rx_*6 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_rx_*6 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
-  [ipx::get_bus_interfaces gt_rx_*7 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_rx_*7 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
-  [ipx::get_bus_interfaces gt_tx_*0 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_tx_*0 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
-  [ipx::get_bus_interfaces gt_tx_*1 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_tx_*1 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
-  [ipx::get_bus_interfaces gt_tx_*2 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_tx_*2 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
-  [ipx::get_bus_interfaces gt_tx_*3 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_tx_*3 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
-  [ipx::get_bus_interfaces gt_tx_*4 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_tx_*4 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
-  [ipx::get_bus_interfaces gt_tx_*5 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_tx_*5 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
-  [ipx::get_bus_interfaces gt_tx_*6 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_tx_*6 -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
-  [ipx::get_bus_interfaces gt_tx_*7 -of_objects [ipx::current_core]] 
+  [ipx::get_bus_interfaces gt_tx_*7 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
-  [ipx::get_ports *rx_*0* -of_objects [ipx::current_core]] 
+  [ipx::get_ports *rx_*0* -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
-  [ipx::get_ports *rx_*1* -of_objects [ipx::current_core]] 
+  [ipx::get_ports *rx_*1* -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
   [ipx::get_ports *rx_*2* -of_objects [ipx::current_core]]
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr/common/ccfmc_bd.tcl
index df1e8573a..7296b5451 100644
--- a/projects/pzsdr/common/ccfmc_bd.tcl
+++ b/projects/pzsdr/common/ccfmc_bd.tcl
@@ -221,13 +221,13 @@ ad_connect  axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0
 ad_connect  axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0
 ad_connect  axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0
 ad_connect  axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0 
+ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0
 ad_connect  axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0
 ad_connect  axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0
 ad_connect  axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0
 ad_connect  axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
 ad_connect  axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0 
+ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0
 
 # un-used io (regular)
 

From af4c43b6e18bfd0ab6ef3555469683fd1e7fb29f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 1 Aug 2016 13:49:12 +0300
Subject: [PATCH 359/972] hdl-vivado-2016.2: Update fmcomms2 and pzsdr base
 design

---
 projects/fmcomms2/common/fmcomms2_bd.tcl | 2 +-
 projects/pzsdr/common/ccfmc_bd.tcl       | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl
index c2afa50c9..2dbf3d04e 100644
--- a/projects/fmcomms2/common/fmcomms2_bd.tcl
+++ b/projects/fmcomms2/common/fmcomms2_bd.tcl
@@ -168,7 +168,7 @@ ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
 
 # ila (adc)
 
-set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
+set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
 set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr/common/ccfmc_bd.tcl
index 7296b5451..dfeff9174 100644
--- a/projects/pzsdr/common/ccfmc_bd.tcl
+++ b/projects/pzsdr/common/ccfmc_bd.tcl
@@ -59,7 +59,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
 
 # audio peripherals
 
-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
 set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
 set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen

From a0ae79139543ef07a2d8d0e56ba013e73927dbd5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 1 Aug 2016 13:53:18 +0300
Subject: [PATCH 360/972] hdl-vivado-2016.2: Update axi_jesd_gt

Infer AXI bus interfaces separately.
---
 library/axi_jesd_gt/axi_jesd_gt_ip.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
index dd035f77f..5697a05f0 100644
--- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
+++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
@@ -22,6 +22,7 @@ adi_ip_files axi_jesd_gt [list \
   "axi_jesd_gt.v" ]
 
 adi_ip_properties axi_jesd_gt
+adi_ip_infer_interfaces axi_jesd_gt
 
 adi_ip_constraints axi_jesd_gt [list \
   "axi_jesd_gt_tx_constr.xdc" \

From 7ca8e10004e67f37dbc6b51ff40227dd666e4b8f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 1 Aug 2016 14:24:48 +0300
Subject: [PATCH 361/972] make: Update Make files

---
 projects/ad6676evb/vc707/Makefile   | 1 +
 projects/ad6676evb/zc706/Makefile   | 1 +
 projects/ad7616_sdz/zc706/Makefile  | 1 +
 projects/ad7616_sdz/zed/Makefile    | 1 +
 projects/ad7768evb/zed/Makefile     | 1 +
 projects/ad9265_fmc/zc706/Makefile  | 1 +
 projects/ad9434_fmc/zc706/Makefile  | 1 +
 projects/ad9467_fmc/kc705/Makefile  | 1 +
 projects/ad9467_fmc/zed/Makefile    | 1 +
 projects/ad9739a_fmc/zc706/Makefile | 1 +
 projects/adrv9371x/zc706/Makefile   | 1 +
 projects/adv7511/ac701/Makefile     | 1 +
 projects/adv7511/kc705/Makefile     | 1 +
 projects/adv7511/kcu105/Makefile    | 1 +
 projects/adv7511/mitx045/Makefile   | 1 +
 projects/adv7511/vc707/Makefile     | 1 +
 projects/adv7511/zc702/Makefile     | 1 +
 projects/adv7511/zc706/Makefile     | 1 +
 projects/adv7511/zed/Makefile       | 1 +
 projects/cftl_cip/zed/Makefile      | 1 +
 projects/cftl_std/zed/Makefile      | 1 +
 projects/cn0363/microzed/Makefile   | 1 +
 projects/cn0363/zed/Makefile        | 1 +
 projects/daq1/zc706/Makefile        | 1 +
 projects/daq2/kc705/Makefile        | 1 +
 projects/daq2/kcu105/Makefile       | 1 +
 projects/daq2/vc707/Makefile        | 1 +
 projects/daq2/zc706/Makefile        | 1 +
 projects/daq3/kcu105/Makefile       | 1 +
 projects/daq3/zc706/Makefile        | 1 +
 projects/fmcadc2/vc707/Makefile     | 1 +
 projects/fmcadc2/zc706/Makefile     | 1 +
 projects/fmcadc4/zc706/Makefile     | 1 +
 projects/fmcadc5/vc707/Makefile     | 1 +
 projects/fmcjesdadc1/kc705/Makefile | 1 +
 projects/fmcjesdadc1/vc707/Makefile | 1 +
 projects/fmcjesdadc1/zc706/Makefile | 1 +
 projects/fmcomms1/ac701/Makefile    | 1 +
 projects/fmcomms1/kc705/Makefile    | 1 +
 projects/fmcomms1/vc707/Makefile    | 1 +
 projects/fmcomms1/zc702/Makefile    | 1 +
 projects/fmcomms1/zc706/Makefile    | 1 +
 projects/fmcomms1/zed/Makefile      | 1 +
 projects/fmcomms11/zc706/Makefile   | 1 +
 projects/fmcomms2/ac701/Makefile    | 1 +
 projects/fmcomms2/kc705/Makefile    | 1 +
 projects/fmcomms2/mitx045/Makefile  | 1 +
 projects/fmcomms2/vc707/Makefile    | 1 +
 projects/fmcomms2/zc702/Makefile    | 1 +
 projects/fmcomms2/zc706/Makefile    | 1 +
 projects/fmcomms2/zcu102/Makefile   | 1 +
 projects/fmcomms2/zed/Makefile      | 1 +
 projects/fmcomms5/zc702/Makefile    | 1 +
 projects/fmcomms5/zc706/Makefile    | 1 +
 projects/fmcomms6/zc706/Makefile    | 1 +
 projects/fmcomms7/zc706/Makefile    | 1 +
 projects/imageon/zc706/Makefile     | 1 +
 projects/imageon/zed/Makefile       | 1 +
 projects/motcon2_fmc/zed/Makefile   | 1 +
 projects/pzsdr/ccbrk/Makefile       | 1 +
 projects/pzsdr/ccbrk_cmos/Makefile  | 1 +
 projects/pzsdr/ccfmc/Makefile       | 1 +
 projects/pzsdr/ccpci/Makefile       | 1 +
 projects/pzsdr1/ccbrk/Makefile      | 1 +
 projects/pzsdr1/ccbrk_cmos/Makefile | 1 +
 projects/usb_fx3/zc706/Makefile     | 1 +
 projects/usdrx1/zc706/Makefile      | 1 +
 67 files changed, 67 insertions(+)

diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile
index 5e0c9487c..641c1f02f 100644
--- a/projects/ad6676evb/vc707/Makefile
+++ b/projects/ad6676evb/vc707/Makefile
@@ -37,6 +37,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile
index b11811429..3ba298f82 100644
--- a/projects/ad6676evb/zc706/Makefile
+++ b/projects/ad6676evb/zc706/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile
index 539ba381d..ed84e3087 100644
--- a/projects/ad7616_sdz/zc706/Makefile
+++ b/projects/ad7616_sdz/zc706/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile
index 635cb90be..d95085855 100644
--- a/projects/ad7616_sdz/zed/Makefile
+++ b/projects/ad7616_sdz/zed/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad7768evb/zed/Makefile b/projects/ad7768evb/zed/Makefile
index b14ce41b3..c9ad07e82 100644
--- a/projects/ad7768evb/zed/Makefile
+++ b/projects/ad7768evb/zed/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9265_fmc/zc706/Makefile b/projects/ad9265_fmc/zc706/Makefile
index 9ad95e317..8787a78d6 100644
--- a/projects/ad9265_fmc/zc706/Makefile
+++ b/projects/ad9265_fmc/zc706/Makefile
@@ -37,6 +37,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9434_fmc/zc706/Makefile b/projects/ad9434_fmc/zc706/Makefile
index 70d247f5c..6db32568b 100644
--- a/projects/ad9434_fmc/zc706/Makefile
+++ b/projects/ad9434_fmc/zc706/Makefile
@@ -37,6 +37,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9467_fmc/kc705/Makefile b/projects/ad9467_fmc/kc705/Makefile
index 887838189..51930e6f2 100644
--- a/projects/ad9467_fmc/kc705/Makefile
+++ b/projects/ad9467_fmc/kc705/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9467_fmc/zed/Makefile b/projects/ad9467_fmc/zed/Makefile
index 0eee2b11c..c8e8554ff 100644
--- a/projects/ad9467_fmc/zed/Makefile
+++ b/projects/ad9467_fmc/zed/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9739a_fmc/zc706/Makefile b/projects/ad9739a_fmc/zc706/Makefile
index 481327975..7b0a212b9 100644
--- a/projects/ad9739a_fmc/zc706/Makefile
+++ b/projects/ad9739a_fmc/zc706/Makefile
@@ -36,6 +36,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
index 933be8e1c..7f5e028d2 100644
--- a/projects/adrv9371x/zc706/Makefile
+++ b/projects/adrv9371x/zc706/Makefile
@@ -48,6 +48,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile
index 0dfca3289..e0ab84e33 100644
--- a/projects/adv7511/ac701/Makefile
+++ b/projects/adv7511/ac701/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/kc705/Makefile b/projects/adv7511/kc705/Makefile
index 69dea3d47..0926f5973 100644
--- a/projects/adv7511/kc705/Makefile
+++ b/projects/adv7511/kc705/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile
index 9a09b9f4f..4b1000907 100644
--- a/projects/adv7511/kcu105/Makefile
+++ b/projects/adv7511/kcu105/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile
index 80c65e379..33d21bb6c 100644
--- a/projects/adv7511/mitx045/Makefile
+++ b/projects/adv7511/mitx045/Makefile
@@ -34,6 +34,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/vc707/Makefile b/projects/adv7511/vc707/Makefile
index b347dcd33..bed52b1dc 100644
--- a/projects/adv7511/vc707/Makefile
+++ b/projects/adv7511/vc707/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/zc702/Makefile b/projects/adv7511/zc702/Makefile
index 876158ecd..4d69884e1 100644
--- a/projects/adv7511/zc702/Makefile
+++ b/projects/adv7511/zc702/Makefile
@@ -32,6 +32,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/zc706/Makefile b/projects/adv7511/zc706/Makefile
index d00baa5e9..d9f86a2fa 100644
--- a/projects/adv7511/zc706/Makefile
+++ b/projects/adv7511/zc706/Makefile
@@ -32,6 +32,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/zed/Makefile b/projects/adv7511/zed/Makefile
index 26d233c0b..9962f024d 100644
--- a/projects/adv7511/zed/Makefile
+++ b/projects/adv7511/zed/Makefile
@@ -34,6 +34,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/cftl_cip/zed/Makefile b/projects/cftl_cip/zed/Makefile
index 687b6a0e0..48955f00a 100644
--- a/projects/cftl_cip/zed/Makefile
+++ b/projects/cftl_cip/zed/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/cftl_std/zed/Makefile b/projects/cftl_std/zed/Makefile
index 55923a3eb..5c3581bb5 100644
--- a/projects/cftl_std/zed/Makefile
+++ b/projects/cftl_std/zed/Makefile
@@ -36,6 +36,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile
index 81bbb9aff..63fc458db 100644
--- a/projects/cn0363/microzed/Makefile
+++ b/projects/cn0363/microzed/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile
index e5a811c0c..7e2ba850f 100644
--- a/projects/cn0363/zed/Makefile
+++ b/projects/cn0363/zed/Makefile
@@ -47,6 +47,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile
index f17d14899..15f689ed4 100644
--- a/projects/daq1/zc706/Makefile
+++ b/projects/daq1/zc706/Makefile
@@ -44,6 +44,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile
index 20b625f64..4da1284aa 100644
--- a/projects/daq2/kc705/Makefile
+++ b/projects/daq2/kc705/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile
index 05a450015..9276c41c7 100644
--- a/projects/daq2/kcu105/Makefile
+++ b/projects/daq2/kcu105/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile
index f766f1ade..8839fb7e6 100644
--- a/projects/daq2/vc707/Makefile
+++ b/projects/daq2/vc707/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index 7f8f0fd68..5f0d8a8c1 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -49,6 +49,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
index 256432946..098251b46 100644
--- a/projects/daq3/kcu105/Makefile
+++ b/projects/daq3/kcu105/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index a591c3306..f6fd315d0 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -50,6 +50,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index 3ae995270..bfd4ee312 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 7a83de7f5..c660319a3 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index b4f4379f4..4275abf7f 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -46,6 +46,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile
index 38905f714..c85922cb7 100644
--- a/projects/fmcadc5/vc707/Makefile
+++ b/projects/fmcadc5/vc707/Makefile
@@ -44,6 +44,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile
index 7050c879e..6cf8067b6 100644
--- a/projects/fmcjesdadc1/kc705/Makefile
+++ b/projects/fmcjesdadc1/kc705/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile
index 379caa28b..5fb268b22 100644
--- a/projects/fmcjesdadc1/vc707/Makefile
+++ b/projects/fmcjesdadc1/vc707/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile
index e3c623304..3a1c30df6 100644
--- a/projects/fmcjesdadc1/zc706/Makefile
+++ b/projects/fmcjesdadc1/zc706/Makefile
@@ -41,6 +41,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms1/ac701/Makefile
index 9c8a6771c..822102ea1 100644
--- a/projects/fmcomms1/ac701/Makefile
+++ b/projects/fmcomms1/ac701/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/kc705/Makefile b/projects/fmcomms1/kc705/Makefile
index 5d00e2573..6c60d5cba 100644
--- a/projects/fmcomms1/kc705/Makefile
+++ b/projects/fmcomms1/kc705/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/vc707/Makefile b/projects/fmcomms1/vc707/Makefile
index 8b7b14948..927e087a1 100644
--- a/projects/fmcomms1/vc707/Makefile
+++ b/projects/fmcomms1/vc707/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/zc702/Makefile b/projects/fmcomms1/zc702/Makefile
index c5faab08a..002c0e9f3 100644
--- a/projects/fmcomms1/zc702/Makefile
+++ b/projects/fmcomms1/zc702/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/zc706/Makefile b/projects/fmcomms1/zc706/Makefile
index 5170046cd..429f7e554 100644
--- a/projects/fmcomms1/zc706/Makefile
+++ b/projects/fmcomms1/zc706/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/zed/Makefile b/projects/fmcomms1/zed/Makefile
index 79e54721f..5310104ab 100644
--- a/projects/fmcomms1/zed/Makefile
+++ b/projects/fmcomms1/zed/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index 72b3b1c6b..5918ebca1 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -47,6 +47,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile
index 03282725e..be2f72cd4 100644
--- a/projects/fmcomms2/ac701/Makefile
+++ b/projects/fmcomms2/ac701/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile
index ab24ca35e..05ac0f8f9 100644
--- a/projects/fmcomms2/kc705/Makefile
+++ b/projects/fmcomms2/kc705/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile
index ca53855ce..1a0cb9a32 100644
--- a/projects/fmcomms2/mitx045/Makefile
+++ b/projects/fmcomms2/mitx045/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile
index 46327e71d..0e916389d 100644
--- a/projects/fmcomms2/vc707/Makefile
+++ b/projects/fmcomms2/vc707/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile
index 439cfe22c..23ebf1452 100644
--- a/projects/fmcomms2/zc702/Makefile
+++ b/projects/fmcomms2/zc702/Makefile
@@ -41,6 +41,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile
index d3c52de44..6124ac8a5 100644
--- a/projects/fmcomms2/zc706/Makefile
+++ b/projects/fmcomms2/zc706/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/zcu102/Makefile b/projects/fmcomms2/zcu102/Makefile
index 3418eb35a..12b25ef34 100644
--- a/projects/fmcomms2/zcu102/Makefile
+++ b/projects/fmcomms2/zcu102/Makefile
@@ -37,6 +37,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile
index 9fd8dcfc5..36c8f0f50 100644
--- a/projects/fmcomms2/zed/Makefile
+++ b/projects/fmcomms2/zed/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile
index bba74f74a..9a85c25db 100644
--- a/projects/fmcomms5/zc702/Makefile
+++ b/projects/fmcomms5/zc702/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile
index 5aee574f5..b383576b9 100644
--- a/projects/fmcomms5/zc706/Makefile
+++ b/projects/fmcomms5/zc706/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms6/zc706/Makefile b/projects/fmcomms6/zc706/Makefile
index 3846e87f0..b50f31185 100644
--- a/projects/fmcomms6/zc706/Makefile
+++ b/projects/fmcomms6/zc706/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index 3f42f718c..076394047 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -49,6 +49,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile
index bf8076634..cb5df8367 100644
--- a/projects/imageon/zc706/Makefile
+++ b/projects/imageon/zc706/Makefile
@@ -36,6 +36,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile
index bf3a40c13..a32aa12af 100644
--- a/projects/imageon/zed/Makefile
+++ b/projects/imageon/zed/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/motcon2_fmc/zed/Makefile b/projects/motcon2_fmc/zed/Makefile
index e214e56d0..dd9e940bf 100644
--- a/projects/motcon2_fmc/zed/Makefile
+++ b/projects/motcon2_fmc/zed/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile
index c9b8d0aa0..2df8fff21 100644
--- a/projects/pzsdr/ccbrk/Makefile
+++ b/projects/pzsdr/ccbrk/Makefile
@@ -44,6 +44,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
index bc6539695..1db280a0e 100644
--- a/projects/pzsdr/ccbrk_cmos/Makefile
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -44,6 +44,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile
index 643a619e6..5fe413176 100644
--- a/projects/pzsdr/ccfmc/Makefile
+++ b/projects/pzsdr/ccfmc/Makefile
@@ -48,6 +48,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci/Makefile
index 08fce8aaf..e621f6bf4 100644
--- a/projects/pzsdr/ccpci/Makefile
+++ b/projects/pzsdr/ccpci/Makefile
@@ -41,6 +41,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
index 8c9589b67..407e25fb5 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr1/ccbrk_cmos/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile
index 033e96bfd..4497779d9 100644
--- a/projects/pzsdr1/ccbrk_cmos/Makefile
+++ b/projects/pzsdr1/ccbrk_cmos/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile
index eb786cf55..916c1b8ce 100644
--- a/projects/usb_fx3/zc706/Makefile
+++ b/projects/usb_fx3/zc706/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index 1add6ecb0..ee90181bc 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 

From aece3f55559591e712a9082a2649bf5370ad3723 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 1 Aug 2016 15:05:30 +0300
Subject: [PATCH 362/972] axi_ad9680: Update IP core

- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
---
 library/axi_ad9680/axi_ad9680.v      |  6 ++++++
 library/axi_ad9680/axi_ad9680_hw.tcl | 17 ++++++++++++++++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v
index 321384f95..66e54937b 100644
--- a/library/axi_ad9680/axi_ad9680.v
+++ b/library/axi_ad9680/axi_ad9680.v
@@ -45,6 +45,8 @@ module axi_ad9680 (
   rx_clk,
   rx_sof,
   rx_data,
+  rx_valid,
+  rx_ready,
 
   // dma interface
 
@@ -93,6 +95,9 @@ module axi_ad9680 (
   input  [  3:0]  rx_sof;
   input  [127:0]  rx_data;
 
+  input           rx_valid;
+  output          rx_ready;
+
   // dma interface
 
   output          adc_clk;
@@ -172,6 +177,7 @@ module axi_ad9680 (
 
   assign adc_valid_0 = 1'b1;
   assign adc_valid_1 = 1'b1;
+  assign rx_ready = 1'b1;
 
   // processor read interface
 
diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl
index b103f2d9c..eb90f4386 100755
--- a/library/axi_ad9680/axi_ad9680_hw.tcl
+++ b/library/axi_ad9680/axi_ad9680_hw.tcl
@@ -24,6 +24,7 @@ add_fileset_file up_clock_mon.v       VERILOG PATH $ad_hdl_dir/library/common/up
 add_fileset_file up_delay_cntrl.v     VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
 add_fileset_file up_adc_common.v      VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
 add_fileset_file up_adc_channel.v     VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
+add_fileset_file ad_xcvr_rx_if.v      VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
 add_fileset_file axi_ad9680_pnmon.v   VERILOG PATH axi_ad9680_pnmon.v
 add_fileset_file axi_ad9680_channel.v VERILOG PATH axi_ad9680_channel.v
 add_fileset_file axi_ad9680_if.v      VERILOG PATH axi_ad9680_if.v
@@ -39,6 +40,13 @@ set_parameter_property ID TYPE INTEGER
 set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
+add_parameter DEVICE_TYPE INTEGER 0
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
 # axi4 slave
 
 add_interface s_axi_clock clock end
@@ -74,7 +82,14 @@ add_interface_port s_axi s_axi_rready rready Input 1
 # transceiver interface
 
 ad_alt_intf clock   rx_clk        input   1
-ad_alt_intf signal  rx_data       input   128 data
+ad_alt_intf signal  rx_sof        input   4 export
+
+add_interface if_rx_ip_avl avalon_streaming sink
+add_interface_port if_rx_ip_avl rx_data  data  input 128
+add_interface_port if_rx_ip_avl rx_valid valid input 1
+add_interface_port if_rx_ip_avl rx_ready ready output 1
+set_interface_property if_rx_ip_avl associatedClock if_rx_clk
+set_interface_property if_rx_ip_avl dataBitsPerSymbol 128
 
 # dma interface
 

From 52ae3ddd6ca996a9a316bc4ff11617b31c113630 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 1 Aug 2016 15:08:12 +0300
Subject: [PATCH 363/972] a10gx: Updated common files to 16.0

---
 projects/common/a10gx/a10gx_system_qsys.tcl | 36 ++++++++++-----------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl
index b94d2a15e..c559306fb 100644
--- a/projects/common/a10gx/a10gx_system_qsys.tcl
+++ b/projects/common/a10gx/a10gx_system_qsys.tcl
@@ -7,7 +7,7 @@ set_project_property DEVICE {10AX115S3F45E2SGE3}
 
 # clock-&-reset
 
-add_instance sys_clk clock_source 15.1
+add_instance sys_clk clock_source 16.0
 add_interface sys_clk clock sink
 add_interface sys_rst reset sink
 set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
@@ -18,7 +18,7 @@ set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
 
 # memory (int)
 
-add_instance sys_int_mem altera_avalon_onchip_memory2 15.1
+add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
 set_instance_parameter_value sys_int_mem {dataWidth} {32}
 set_instance_parameter_value sys_int_mem {dualPort} {0}
 set_instance_parameter_value sys_int_mem {initMemContent} {0}
@@ -29,7 +29,7 @@ add_connection sys_clk.clk_reset sys_int_mem.reset1
 
 # memory (tlb)
 
-add_instance sys_tlb_mem altera_avalon_onchip_memory2 15.1
+add_instance sys_tlb_mem altera_avalon_onchip_memory2 16.0
 set_instance_parameter_value sys_tlb_mem {dataWidth} {32}
 set_instance_parameter_value sys_tlb_mem {dualPort} {1}
 set_instance_parameter_value sys_tlb_mem {initMemContent} {1}
@@ -42,7 +42,7 @@ add_connection sys_clk.clk_reset sys_tlb_mem.reset2
 
 # memory (ddr)
 
-add_instance sys_ddr3_cntrl altera_emif 15.1
+add_instance sys_ddr3_cntrl altera_emif 16.0
 set_instance_parameter_value sys_ddr3_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR3}
 set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
 set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_MEM_CLK_FREQ_MHZ} {533.333}
@@ -82,7 +82,7 @@ set_interface_property sys_ddr3_cntrl_pll_ref_clk EXPORT_OF sys_ddr3_cntrl.pll_r
 
 # cpu
 
-add_instance sys_cpu altera_nios2_gen2 15.1
+add_instance sys_cpu altera_nios2_gen2 16.0
 set_instance_parameter_value sys_cpu {setting_support31bitdcachebypass} {0}
 set_instance_parameter_value sys_cpu {setting_activateTrace} {1}
 set_instance_parameter_value sys_cpu {mmu_autoAssignTlbPtrSz} {0}
@@ -100,7 +100,7 @@ set_instance_parameter_value sys_cpu {dcache_numTCDM} {1}
 set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
 set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
 set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
-#set_instance_parameter_value sys_cpu {mmu_enabled} {1}
+set_instance_parameter_value sys_cpu {mmu_enabled} {1}
 
 add_connection sys_clk.clk sys_cpu.clk
 add_connection sys_clk.clk_reset sys_cpu.reset
@@ -117,7 +117,7 @@ add_connection sys_cpu.data_master sys_ddr3_cntrl.ctrl_amm_0
 
 # ethernet
 
-add_instance sys_ethernet altera_eth_tse 15.1
+add_instance sys_ethernet altera_eth_tse 16.0
 set_instance_parameter_value sys_ethernet {core_variation} {MAC_PCS}
 set_instance_parameter_value sys_ethernet {ifGMII} {MII_GMII}
 set_instance_parameter_value sys_ethernet {transceiver_type} {LVDS_IO}
@@ -127,7 +127,7 @@ set_instance_parameter_value sys_ethernet {eg_addr} {12}
 set_instance_parameter_value sys_ethernet {ing_addr} {12}
 set_instance_parameter_value sys_ethernet {enable_sgmii} {1}
 
-add_instance sys_ethernet_dma_rx altera_msgdma 15.1
+add_instance sys_ethernet_dma_rx altera_msgdma 16.0
 set_instance_parameter_value sys_ethernet_dma_rx {MODE} {2}
 set_instance_parameter_value sys_ethernet_dma_rx {DATA_WIDTH} {64}
 set_instance_parameter_value sys_ethernet_dma_rx {DATA_FIFO_DEPTH} {256}
@@ -142,7 +142,7 @@ set_instance_parameter_value sys_ethernet_dma_rx {PACKET_ENABLE} {1}
 set_instance_parameter_value sys_ethernet_dma_rx {ERROR_ENABLE} {1}
 set_instance_parameter_value sys_ethernet_dma_rx {ERROR_WIDTH} {6}
 
-add_instance sys_ethernet_dma_tx altera_msgdma 15.1
+add_instance sys_ethernet_dma_tx altera_msgdma 16.0
 set_instance_parameter_value sys_ethernet_dma_tx {MODE} {1}
 set_instance_parameter_value sys_ethernet_dma_tx {DATA_WIDTH} {64}
 set_instance_parameter_value sys_ethernet_dma_tx {DATA_FIFO_DEPTH} {256}
@@ -156,7 +156,7 @@ set_instance_parameter_value sys_ethernet_dma_tx {PACKET_ENABLE} {1}
 set_instance_parameter_value sys_ethernet_dma_tx {ERROR_ENABLE} {1}
 set_instance_parameter_value sys_ethernet_dma_tx {ERROR_WIDTH} {1}
 
-add_instance sys_ethernet_reset altera_reset_bridge 15.1
+add_instance sys_ethernet_reset altera_reset_bridge 16.0
 set_instance_parameter_value sys_ethernet_reset {ACTIVE_LOW_RESET} {0}
 set_instance_parameter_value sys_ethernet_reset {NUM_RESET_OUTPUTS} {1}
 
@@ -194,7 +194,7 @@ set_interface_property sys_ethernet_sgmii EXPORT_OF sys_ethernet.serial_connecti
 
 # sys-id
 
-add_instance sys_id altera_avalon_sysid_qsys 15.1
+add_instance sys_id altera_avalon_sysid_qsys 16.0
 set_instance_parameter_value sys_id {id} {182193580}
 
 add_connection sys_clk.clk_reset sys_id.reset
@@ -203,7 +203,7 @@ add_connection sys_cpu.data_master sys_id.control_slave
 
 # timer-1
 
-add_instance sys_timer_1 altera_avalon_timer 15.1
+add_instance sys_timer_1 altera_avalon_timer 16.0
 set_instance_parameter_value sys_timer_1 {counterSize} {32}
 
 add_connection sys_clk.clk_reset sys_timer_1.reset
@@ -213,7 +213,7 @@ add_connection sys_cpu.irq sys_timer_1.irq
 
 # timer-2
 
-add_instance sys_timer_2 altera_avalon_timer 15.1
+add_instance sys_timer_2 altera_avalon_timer 16.0
 set_instance_parameter_value sys_timer_2 {counterSize} {32}
 
 add_connection sys_clk.clk_reset sys_timer_2.reset
@@ -223,7 +223,7 @@ add_connection sys_cpu.irq sys_timer_2.irq
 
 # uart
 
-add_instance sys_uart altera_avalon_jtag_uart 15.1
+add_instance sys_uart altera_avalon_jtag_uart 16.0
 set_instance_parameter_value sys_uart {allowMultipleConnections} {0}
 
 add_connection sys_clk.clk_reset sys_uart.reset
@@ -233,7 +233,7 @@ add_connection sys_cpu.irq sys_uart.irq
 
 # gpio-bd
 
-add_instance sys_gpio_bd altera_avalon_pio 15.1
+add_instance sys_gpio_bd altera_avalon_pio 16.0
 set_instance_parameter_value sys_gpio_bd {direction} {InOut}
 set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
 set_instance_parameter_value sys_gpio_bd {width} {32}
@@ -248,7 +248,7 @@ set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
 
 # gpio-in
 
-add_instance sys_gpio_in altera_avalon_pio 15.1
+add_instance sys_gpio_in altera_avalon_pio 16.0
 set_instance_parameter_value sys_gpio_in {direction} {Input}
 set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
 set_instance_parameter_value sys_gpio_in {width} {32}
@@ -263,7 +263,7 @@ set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
 
 # gpio-out
 
-add_instance sys_gpio_out altera_avalon_pio 15.1
+add_instance sys_gpio_out altera_avalon_pio 16.0
 set_instance_parameter_value sys_gpio_out {direction} {Output}
 set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
 set_instance_parameter_value sys_gpio_out {width} {32}
@@ -277,7 +277,7 @@ set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
 
 # spi
 
-add_instance sys_spi altera_avalon_spi 15.1
+add_instance sys_spi altera_avalon_spi 16.0
 set_instance_parameter_value sys_spi {clockPhase} {0}
 set_instance_parameter_value sys_spi {clockPolarity} {0}
 set_instance_parameter_value sys_spi {dataWidth} {8}

From 9a563de8ff546243b2bbd6b3d453a92a8b74e4ef Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 1 Aug 2016 15:09:53 +0300
Subject: [PATCH 364/972] daq2: A10GX updated project to Quartus 16.0

- connected directly axi_ad9680 to xcvr_core, skipping axi_jesd_xcvr
---
 projects/daq2/common/daq2_qsys.tcl | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/projects/daq2/common/daq2_qsys.tcl b/projects/daq2/common/daq2_qsys.tcl
index 218a8b161..0244be256 100644
--- a/projects/daq2/common/daq2_qsys.tcl
+++ b/projects/daq2/common/daq2_qsys.tcl
@@ -1,13 +1,13 @@
 
 # transmit-path (refclk)
 
-add_instance xcvr_tx_ref_clk altera_clock_bridge 15.1
+add_instance xcvr_tx_ref_clk altera_clock_bridge 16.0
 set_instance_parameter_value xcvr_tx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
 
 # transmit-path (pll-core)
 
-add_instance xcvr_tx_pll altera_iopll 15.1
-add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 15.1
+add_instance xcvr_tx_pll altera_iopll 16.0
+add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 16.0
 set_instance_parameter_value xcvr_tx_pll {gui_en_reconf} {1}
 set_instance_parameter_value xcvr_tx_pll {gui_reference_clock_frequency} {500.0}
 set_instance_parameter_value xcvr_tx_pll {gui_use_locked} {0}
@@ -15,7 +15,7 @@ set_instance_parameter_value xcvr_tx_pll {gui_output_clock_frequency0} {250.0}
 
 # transmit-path (pll-atx)
 
-add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 15.1
+add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 16.0
 set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
 set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
 set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
@@ -25,13 +25,13 @@ set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequenc
 
 # receive-path (refclk)
 
-add_instance xcvr_rx_ref_clk altera_clock_bridge 15.1
+add_instance xcvr_rx_ref_clk altera_clock_bridge 16.0
 set_instance_parameter_value xcvr_rx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
 
 # receive-path (pll-core)
 
-add_instance xcvr_rx_pll altera_iopll 15.1
-add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 15.1
+add_instance xcvr_rx_pll altera_iopll 16.0
+add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 16.0
 set_instance_parameter_value xcvr_rx_pll {gui_en_reconf} {1}
 set_instance_parameter_value xcvr_rx_pll {gui_reference_clock_frequency} {500.0}
 set_instance_parameter_value xcvr_rx_pll {gui_use_locked} {0}
@@ -46,7 +46,7 @@ set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {4}
 
 # transceiver-reset
 
-add_instance xcvr_rst_cntrl altera_xcvr_reset_control 15.1
+add_instance xcvr_rst_cntrl altera_xcvr_reset_control 16.0
 set_instance_parameter_value xcvr_rst_cntrl {CHANNELS} {4}
 set_instance_parameter_value xcvr_rst_cntrl {SYS_CLK_IN_MHZ} {100}
 set_instance_parameter_value xcvr_rst_cntrl {TX_PLL_ENABLE} {1}
@@ -61,7 +61,7 @@ set_instance_parameter_value xcvr_rst_cntrl {T_RX_DIGITALRESET} {4000}
 
 # transceiver-core (+ jesd)
 
-add_instance xcvr_core altera_jesd204 15.1
+add_instance xcvr_core altera_jesd204 16.0
 set_instance_parameter_value xcvr_core {wrapper_opt} {base_phy}
 set_instance_parameter_value xcvr_core {DATA_PATH} {RX_TX}
 set_instance_parameter_value xcvr_core {lane_rate} {10000.0}
@@ -143,8 +143,6 @@ add_connection axi_jesd_xcvr.if_rx_rstn xcvr_core.rxlink_rst_n
 add_connection axi_jesd_xcvr.if_rx_ready xcvr_rst_cntrl.rx_ready
 add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_core.rx_sysref
 add_connection axi_jesd_xcvr.if_rx_ip_sync xcvr_core.rx_dev_sync_n
-add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_core.rx_sof
-add_connection xcvr_core.jesd204_rx_link axi_jesd_xcvr.if_rx_ip_avl
 add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
 add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
 add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
@@ -220,11 +218,13 @@ add_connection sys_cpu.irq axi_ad9144_dma.interrupt_sender
 add_instance axi_ad9680_core axi_ad9680 1.0
 
 add_connection xcvr_rx_pll.outclk0 axi_ad9680_core.if_rx_clk
-add_connection axi_jesd_xcvr.if_rx_data axi_ad9680_core.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
 add_connection sys_cpu.data_master axi_ad9680_core.s_axi
 
+add_connection xcvr_core.jesd204_rx_link axi_ad9680_core.if_rx_ip_avl
+add_connection xcvr_core.rx_sof axi_ad9680_core.if_rx_sof
+
 # ad9680-pack
 
 add_instance util_ad9680_cpack util_cpack 1.0
@@ -277,6 +277,7 @@ add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
 add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
 add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
 
+
 # addresses
 
 set_connection_parameter_value sys_cpu.data_master/xcvr_rx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d800}

From 999eccc13441e601793f4ba4a80de99ffe79e0f9 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 1 Aug 2016 16:19:43 +0300
Subject: [PATCH 365/972] daq3: Update A10GX project to Quartus 16.0

---
 projects/daq3/common/daq3_qsys.tcl | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl
index 831f46503..e428a6a5c 100644
--- a/projects/daq3/common/daq3_qsys.tcl
+++ b/projects/daq3/common/daq3_qsys.tcl
@@ -1,13 +1,13 @@
 
 # transmit-path (refclk)
 
-add_instance xcvr_tx_ref_clk altera_clock_bridge 15.1
+add_instance xcvr_tx_ref_clk altera_clock_bridge 16.0
 set_instance_parameter_value xcvr_tx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
 
 # transmit-path (pll-core)
 
-add_instance xcvr_tx_pll altera_iopll 15.1
-add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 15.1
+add_instance xcvr_tx_pll altera_iopll 16.0
+add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 16.0
 set_instance_parameter_value xcvr_tx_pll {gui_en_reconf} {1}
 set_instance_parameter_value xcvr_tx_pll {gui_reference_clock_frequency} {500.0}
 set_instance_parameter_value xcvr_tx_pll {gui_use_locked} {0}
@@ -15,7 +15,7 @@ set_instance_parameter_value xcvr_tx_pll {gui_output_clock_frequency0} {250.0}
 
 # transmit-path (pll-atx)
 
-add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 15.1
+add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 16.0
 set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
 set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
 set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
@@ -25,13 +25,13 @@ set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequenc
 
 # receive-path (refclk)
 
-add_instance xcvr_rx_ref_clk altera_clock_bridge 15.1
+add_instance xcvr_rx_ref_clk altera_clock_bridge 16.0
 set_instance_parameter_value xcvr_rx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
 
 # receive-path (pll-core)
 
-add_instance xcvr_rx_pll altera_iopll 15.1
-add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 15.1
+add_instance xcvr_rx_pll altera_iopll 16.0
+add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 16.0
 set_instance_parameter_value xcvr_rx_pll {gui_en_reconf} {1}
 set_instance_parameter_value xcvr_rx_pll {gui_reference_clock_frequency} {500.0}
 set_instance_parameter_value xcvr_rx_pll {gui_use_locked} {0}
@@ -46,7 +46,7 @@ set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {4}
 
 # transceiver-reset
 
-add_instance xcvr_rst_cntrl altera_xcvr_reset_control 15.1
+add_instance xcvr_rst_cntrl altera_xcvr_reset_control 16.0
 set_instance_parameter_value xcvr_rst_cntrl {CHANNELS} {4}
 set_instance_parameter_value xcvr_rst_cntrl {SYS_CLK_IN_MHZ} {100}
 set_instance_parameter_value xcvr_rst_cntrl {TX_PLL_ENABLE} {1}
@@ -61,7 +61,7 @@ set_instance_parameter_value xcvr_rst_cntrl {T_RX_DIGITALRESET} {4000}
 
 # transceiver-core (+ jesd)
 
-add_instance xcvr_core altera_jesd204 15.1
+add_instance xcvr_core altera_jesd204 16.0
 set_instance_parameter_value xcvr_core {wrapper_opt} {base_phy}
 set_instance_parameter_value xcvr_core {DATA_PATH} {RX_TX}
 set_instance_parameter_value xcvr_core {lane_rate} {10000.0}
@@ -143,8 +143,6 @@ add_connection axi_jesd_xcvr.if_rx_rstn xcvr_core.rxlink_rst_n
 add_connection axi_jesd_xcvr.if_rx_ready xcvr_rst_cntrl.rx_ready
 add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_core.rx_sysref
 add_connection axi_jesd_xcvr.if_rx_ip_sync xcvr_core.rx_dev_sync_n
-add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_core.rx_sof
-add_connection xcvr_core.jesd204_rx_link axi_jesd_xcvr.if_rx_ip_avl
 add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
 add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
 add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
@@ -220,11 +218,13 @@ add_connection sys_cpu.irq axi_ad9152_dma.interrupt_sender
 add_instance axi_ad9680_core axi_ad9680 1.0
 
 add_connection xcvr_rx_pll.outclk0 axi_ad9680_core.if_rx_clk
-add_connection axi_jesd_xcvr.if_rx_data axi_ad9680_core.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
 add_connection sys_cpu.data_master axi_ad9680_core.s_axi
 
+add_connection xcvr_core.jesd204_rx_link axi_ad9680_core.if_rx_ip_avl
+add_connection xcvr_core.rx_sof axi_ad9680_core.if_rx_sof
+
 # ad9680-pack
 
 add_instance util_ad9680_cpack util_cpack 1.0

From cba53774caf4f56139d2522ac091d331cab6d507 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 6 Nov 2015 15:17:55 +0100
Subject: [PATCH 366/972] axi_dmac: Don't add CDC constraints when all clocks
 are synchronous

When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_dmac/axi_dmac_constr.ttcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl
index 43befdab1..2ca055ecf 100644
--- a/library/axi_dmac/axi_dmac_constr.ttcl
+++ b/library/axi_dmac/axi_dmac_constr.ttcl
@@ -11,10 +11,12 @@ set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
 set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
 set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
 
+<: if {$async_req_src || $async_src_dest || $async_dest_req} { :>
 set_property ASYNC_REG TRUE \
 	[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
 	[get_cells -quiet -hier *cdc_sync_stage2_reg*]
 
+<: } :>
 <: if {$async_req_src} { :>
 set_max_delay -quiet -datapath_only \
 	-from $req_clk \

From ed9e92621cd0d288559ad42a3c675bcdcaedae36 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 4 Aug 2016 10:50:31 -0400
Subject: [PATCH 367/972] daq2- spi+xcvr address conflict

---
 projects/daq2/common/daq2_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index b266cb135..ae51b664d 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -223,7 +223,7 @@ ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
 ad_cpu_interconnect 0x44A00000 axi_ad9144_core
 ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
-ad_cpu_interconnect 0x44A70000 axi_ad9680_xcvr
+ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
 ad_cpu_interconnect 0x44A10000 axi_ad9680_core
 ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9680_dma

From 2b7c976be5c13e1493aab1dede8b1318b341d433 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 4 Aug 2016 13:26:10 -0400
Subject: [PATCH 368/972] xcvr- altera/xilinx split

---
 library/altera/Makefile                       | 151 ++++++++++++++++++
 library/xilinx/Makefile                       | 151 ++++++++++++++++++
 library/{ => xilinx}/axi_adxcvr/Makefile      |   0
 library/{ => xilinx}/axi_adxcvr/axi_adxcvr.v  |   0
 .../{ => xilinx}/axi_adxcvr/axi_adxcvr_es.v   |   0
 .../{ => xilinx}/axi_adxcvr/axi_adxcvr_ip.tcl |   2 +-
 .../{ => xilinx}/axi_adxcvr/axi_adxcvr_mdrp.v |   0
 .../axi_adxcvr/axi_adxcvr_mstatus.v           |   0
 .../{ => xilinx}/axi_adxcvr/axi_adxcvr_up.v   |   0
 library/{ => xilinx}/util_adxcvr/Makefile     |   0
 .../{ => xilinx}/util_adxcvr/util_adxcvr.v    |   0
 .../util_adxcvr/util_adxcvr_constr.xdc        |   0
 .../util_adxcvr/util_adxcvr_ip.tcl            |   0
 .../util_adxcvr/util_adxcvr_xch.v             |   0
 .../util_adxcvr/util_adxcvr_xcm.v             |   0
 15 files changed, 303 insertions(+), 1 deletion(-)
 create mode 100644 library/altera/Makefile
 create mode 100644 library/xilinx/Makefile
 rename library/{ => xilinx}/axi_adxcvr/Makefile (100%)
 rename library/{ => xilinx}/axi_adxcvr/axi_adxcvr.v (100%)
 rename library/{ => xilinx}/axi_adxcvr/axi_adxcvr_es.v (100%)
 rename library/{ => xilinx}/axi_adxcvr/axi_adxcvr_ip.tcl (99%)
 rename library/{ => xilinx}/axi_adxcvr/axi_adxcvr_mdrp.v (100%)
 rename library/{ => xilinx}/axi_adxcvr/axi_adxcvr_mstatus.v (100%)
 rename library/{ => xilinx}/axi_adxcvr/axi_adxcvr_up.v (100%)
 rename library/{ => xilinx}/util_adxcvr/Makefile (100%)
 rename library/{ => xilinx}/util_adxcvr/util_adxcvr.v (100%)
 rename library/{ => xilinx}/util_adxcvr/util_adxcvr_constr.xdc (100%)
 rename library/{ => xilinx}/util_adxcvr/util_adxcvr_ip.tcl (100%)
 rename library/{ => xilinx}/util_adxcvr/util_adxcvr_xch.v (100%)
 rename library/{ => xilinx}/util_adxcvr/util_adxcvr_xcm.v (100%)

diff --git a/library/altera/Makefile b/library/altera/Makefile
new file mode 100644
index 000000000..1b40b5171
--- /dev/null
+++ b/library/altera/Makefile
@@ -0,0 +1,151 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+.PHONY: all lib clean clean-all
+all: lib
+
+
+clean:
+	make -C axi_ad6676 clean
+	make -C axi_ad7616 clean
+	make -C axi_ad9122 clean
+	make -C axi_ad9144 clean
+	make -C axi_ad9152 clean
+	make -C axi_ad9162 clean
+	make -C axi_ad9234 clean
+	make -C axi_ad9250 clean
+	make -C axi_ad9265 clean
+	make -C axi_ad9361 clean
+	make -C axi_ad9371 clean
+	make -C axi_ad9434 clean
+	make -C axi_ad9467 clean
+	make -C axi_ad9625 clean
+	make -C axi_ad9643 clean
+	make -C axi_ad9652 clean
+	make -C axi_ad9671 clean
+	make -C axi_ad9680 clean
+	make -C axi_ad9684 clean
+	make -C axi_ad9739a clean
+	make -C axi_adcfifo clean
+	make -C axi_adxcvr clean
+	make -C axi_clkgen clean
+	make -C axi_dacfifo clean
+	make -C axi_dmac clean
+	make -C axi_generic_adc clean
+	make -C axi_gpreg clean
+	make -C axi_hdmi_rx clean
+	make -C axi_hdmi_tx clean
+	make -C axi_i2s_adi clean
+	make -C axi_jesd_gt clean
+	make -C axi_mc_controller clean
+	make -C axi_mc_current_monitor clean
+	make -C axi_mc_speed clean
+	make -C axi_spdif_rx clean
+	make -C axi_spdif_tx clean
+	make -C axi_usb_fx3 clean
+	make -C cn0363/cn0363_dma_sequencer clean
+	make -C cn0363/cn0363_phase_data_sync clean
+	make -C cordic_demod clean
+	make -C interfaces clean
+	make -C spi_engine/axi_spi_engine clean
+	make -C spi_engine/spi_engine_execution clean
+	make -C spi_engine/spi_engine_interconnect clean
+	make -C spi_engine/spi_engine_offload clean
+	make -C util_adcfifo clean
+	make -C util_adxcvr clean
+	make -C util_axis_fifo clean
+	make -C util_axis_resize clean
+	make -C util_bsplit clean
+	make -C util_ccat clean
+	make -C util_cpack clean
+	make -C util_dacfifo clean
+	make -C util_gmii_to_rgmii clean
+	make -C util_gtlb clean
+	make -C util_i2c_mixer clean
+	make -C util_jesd_gt clean
+	make -C util_mfifo clean
+	make -C util_pmod_adc clean
+	make -C util_pmod_fmeter clean
+	make -C util_rfifo clean
+	make -C util_sigma_delta_spi clean
+	make -C util_tdd_sync clean
+	make -C util_upack clean
+	make -C util_wfifo clean
+
+
+clean-all:clean
+
+
+lib:
+	-make -C axi_ad6676
+	-make -C axi_ad7616
+	-make -C axi_ad9122
+	-make -C axi_ad9144
+	-make -C axi_ad9152
+	-make -C axi_ad9162
+	-make -C axi_ad9234
+	-make -C axi_ad9250
+	-make -C axi_ad9265
+	-make -C axi_ad9361
+	-make -C axi_ad9371
+	-make -C axi_ad9434
+	-make -C axi_ad9467
+	-make -C axi_ad9625
+	-make -C axi_ad9643
+	-make -C axi_ad9652
+	-make -C axi_ad9671
+	-make -C axi_ad9680
+	-make -C axi_ad9684
+	-make -C axi_ad9739a
+	-make -C axi_adcfifo
+	-make -C axi_adxcvr
+	-make -C axi_clkgen
+	-make -C axi_dacfifo
+	-make -C axi_dmac
+	-make -C axi_generic_adc
+	-make -C axi_gpreg
+	-make -C axi_hdmi_rx
+	-make -C axi_hdmi_tx
+	-make -C axi_i2s_adi
+	-make -C axi_jesd_gt
+	-make -C axi_mc_controller
+	-make -C axi_mc_current_monitor
+	-make -C axi_mc_speed
+	-make -C axi_spdif_rx
+	-make -C axi_spdif_tx
+	-make -C axi_usb_fx3
+	-make -C cn0363/cn0363_dma_sequencer
+	-make -C cn0363/cn0363_phase_data_sync
+	-make -C cordic_demod
+	-make -C interfaces
+	-make -C spi_engine/axi_spi_engine
+	-make -C spi_engine/spi_engine_execution
+	-make -C spi_engine/spi_engine_interconnect
+	-make -C spi_engine/spi_engine_offload
+	-make -C util_adcfifo
+	-make -C util_adxcvr
+	-make -C util_axis_fifo
+	-make -C util_axis_resize
+	-make -C util_bsplit
+	-make -C util_ccat
+	-make -C util_cpack
+	-make -C util_dacfifo
+	-make -C util_gmii_to_rgmii
+	-make -C util_gtlb
+	-make -C util_i2c_mixer
+	-make -C util_jesd_gt
+	-make -C util_mfifo
+	-make -C util_pmod_adc
+	-make -C util_pmod_fmeter
+	-make -C util_rfifo
+	-make -C util_sigma_delta_spi
+	-make -C util_tdd_sync
+	-make -C util_upack
+	-make -C util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/library/xilinx/Makefile b/library/xilinx/Makefile
new file mode 100644
index 000000000..1b40b5171
--- /dev/null
+++ b/library/xilinx/Makefile
@@ -0,0 +1,151 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+.PHONY: all lib clean clean-all
+all: lib
+
+
+clean:
+	make -C axi_ad6676 clean
+	make -C axi_ad7616 clean
+	make -C axi_ad9122 clean
+	make -C axi_ad9144 clean
+	make -C axi_ad9152 clean
+	make -C axi_ad9162 clean
+	make -C axi_ad9234 clean
+	make -C axi_ad9250 clean
+	make -C axi_ad9265 clean
+	make -C axi_ad9361 clean
+	make -C axi_ad9371 clean
+	make -C axi_ad9434 clean
+	make -C axi_ad9467 clean
+	make -C axi_ad9625 clean
+	make -C axi_ad9643 clean
+	make -C axi_ad9652 clean
+	make -C axi_ad9671 clean
+	make -C axi_ad9680 clean
+	make -C axi_ad9684 clean
+	make -C axi_ad9739a clean
+	make -C axi_adcfifo clean
+	make -C axi_adxcvr clean
+	make -C axi_clkgen clean
+	make -C axi_dacfifo clean
+	make -C axi_dmac clean
+	make -C axi_generic_adc clean
+	make -C axi_gpreg clean
+	make -C axi_hdmi_rx clean
+	make -C axi_hdmi_tx clean
+	make -C axi_i2s_adi clean
+	make -C axi_jesd_gt clean
+	make -C axi_mc_controller clean
+	make -C axi_mc_current_monitor clean
+	make -C axi_mc_speed clean
+	make -C axi_spdif_rx clean
+	make -C axi_spdif_tx clean
+	make -C axi_usb_fx3 clean
+	make -C cn0363/cn0363_dma_sequencer clean
+	make -C cn0363/cn0363_phase_data_sync clean
+	make -C cordic_demod clean
+	make -C interfaces clean
+	make -C spi_engine/axi_spi_engine clean
+	make -C spi_engine/spi_engine_execution clean
+	make -C spi_engine/spi_engine_interconnect clean
+	make -C spi_engine/spi_engine_offload clean
+	make -C util_adcfifo clean
+	make -C util_adxcvr clean
+	make -C util_axis_fifo clean
+	make -C util_axis_resize clean
+	make -C util_bsplit clean
+	make -C util_ccat clean
+	make -C util_cpack clean
+	make -C util_dacfifo clean
+	make -C util_gmii_to_rgmii clean
+	make -C util_gtlb clean
+	make -C util_i2c_mixer clean
+	make -C util_jesd_gt clean
+	make -C util_mfifo clean
+	make -C util_pmod_adc clean
+	make -C util_pmod_fmeter clean
+	make -C util_rfifo clean
+	make -C util_sigma_delta_spi clean
+	make -C util_tdd_sync clean
+	make -C util_upack clean
+	make -C util_wfifo clean
+
+
+clean-all:clean
+
+
+lib:
+	-make -C axi_ad6676
+	-make -C axi_ad7616
+	-make -C axi_ad9122
+	-make -C axi_ad9144
+	-make -C axi_ad9152
+	-make -C axi_ad9162
+	-make -C axi_ad9234
+	-make -C axi_ad9250
+	-make -C axi_ad9265
+	-make -C axi_ad9361
+	-make -C axi_ad9371
+	-make -C axi_ad9434
+	-make -C axi_ad9467
+	-make -C axi_ad9625
+	-make -C axi_ad9643
+	-make -C axi_ad9652
+	-make -C axi_ad9671
+	-make -C axi_ad9680
+	-make -C axi_ad9684
+	-make -C axi_ad9739a
+	-make -C axi_adcfifo
+	-make -C axi_adxcvr
+	-make -C axi_clkgen
+	-make -C axi_dacfifo
+	-make -C axi_dmac
+	-make -C axi_generic_adc
+	-make -C axi_gpreg
+	-make -C axi_hdmi_rx
+	-make -C axi_hdmi_tx
+	-make -C axi_i2s_adi
+	-make -C axi_jesd_gt
+	-make -C axi_mc_controller
+	-make -C axi_mc_current_monitor
+	-make -C axi_mc_speed
+	-make -C axi_spdif_rx
+	-make -C axi_spdif_tx
+	-make -C axi_usb_fx3
+	-make -C cn0363/cn0363_dma_sequencer
+	-make -C cn0363/cn0363_phase_data_sync
+	-make -C cordic_demod
+	-make -C interfaces
+	-make -C spi_engine/axi_spi_engine
+	-make -C spi_engine/spi_engine_execution
+	-make -C spi_engine/spi_engine_interconnect
+	-make -C spi_engine/spi_engine_offload
+	-make -C util_adcfifo
+	-make -C util_adxcvr
+	-make -C util_axis_fifo
+	-make -C util_axis_resize
+	-make -C util_bsplit
+	-make -C util_ccat
+	-make -C util_cpack
+	-make -C util_dacfifo
+	-make -C util_gmii_to_rgmii
+	-make -C util_gtlb
+	-make -C util_i2c_mixer
+	-make -C util_jesd_gt
+	-make -C util_mfifo
+	-make -C util_pmod_adc
+	-make -C util_pmod_fmeter
+	-make -C util_rfifo
+	-make -C util_sigma_delta_spi
+	-make -C util_tdd_sync
+	-make -C util_upack
+	-make -C util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/library/axi_adxcvr/Makefile b/library/xilinx/axi_adxcvr/Makefile
similarity index 100%
rename from library/axi_adxcvr/Makefile
rename to library/xilinx/axi_adxcvr/Makefile
diff --git a/library/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v
similarity index 100%
rename from library/axi_adxcvr/axi_adxcvr.v
rename to library/xilinx/axi_adxcvr/axi_adxcvr.v
diff --git a/library/axi_adxcvr/axi_adxcvr_es.v b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v
similarity index 100%
rename from library/axi_adxcvr/axi_adxcvr_es.v
rename to library/xilinx/axi_adxcvr/axi_adxcvr_es.v
diff --git a/library/axi_adxcvr/axi_adxcvr_ip.tcl b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
similarity index 99%
rename from library/axi_adxcvr/axi_adxcvr_ip.tcl
rename to library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
index 914b06a0c..8808bde9f 100644
--- a/library/axi_adxcvr/axi_adxcvr_ip.tcl
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -1,6 +1,6 @@
 ## AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY!
 
-source ../scripts/adi_env.tcl
+source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create axi_adxcvr
diff --git a/library/axi_adxcvr/axi_adxcvr_mdrp.v b/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
similarity index 100%
rename from library/axi_adxcvr/axi_adxcvr_mdrp.v
rename to library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
diff --git a/library/axi_adxcvr/axi_adxcvr_mstatus.v b/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
similarity index 100%
rename from library/axi_adxcvr/axi_adxcvr_mstatus.v
rename to library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
diff --git a/library/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
similarity index 100%
rename from library/axi_adxcvr/axi_adxcvr_up.v
rename to library/xilinx/axi_adxcvr/axi_adxcvr_up.v
diff --git a/library/util_adxcvr/Makefile b/library/xilinx/util_adxcvr/Makefile
similarity index 100%
rename from library/util_adxcvr/Makefile
rename to library/xilinx/util_adxcvr/Makefile
diff --git a/library/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v
similarity index 100%
rename from library/util_adxcvr/util_adxcvr.v
rename to library/xilinx/util_adxcvr/util_adxcvr.v
diff --git a/library/util_adxcvr/util_adxcvr_constr.xdc b/library/xilinx/util_adxcvr/util_adxcvr_constr.xdc
similarity index 100%
rename from library/util_adxcvr/util_adxcvr_constr.xdc
rename to library/xilinx/util_adxcvr/util_adxcvr_constr.xdc
diff --git a/library/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
similarity index 100%
rename from library/util_adxcvr/util_adxcvr_ip.tcl
rename to library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
diff --git a/library/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
similarity index 100%
rename from library/util_adxcvr/util_adxcvr_xch.v
rename to library/xilinx/util_adxcvr/util_adxcvr_xch.v
diff --git a/library/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
similarity index 100%
rename from library/util_adxcvr/util_adxcvr_xcm.v
rename to library/xilinx/util_adxcvr/util_adxcvr_xcm.v

From e42b4ea37897afc20a83e19dbab1e0c8c66a958a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 4 Aug 2016 13:28:25 -0400
Subject: [PATCH 369/972] hdlmake- updates

---
 library/Makefile                              |  8 ++++----
 library/axi_ad7616/Makefile                   | 16 ++++++++--------
 library/axi_dmac/Makefile                     |  4 ++--
 library/spi_engine/axi_spi_engine/Makefile    |  2 +-
 library/xilinx/axi_adxcvr/Makefile            |  6 +++---
 library/xilinx/util_adxcvr/Makefile           |  4 ++--
 library/xilinx/util_adxcvr/util_adxcvr_ip.tcl |  2 +-
 projects/ad6676evb/vc707/Makefile             |  1 -
 projects/ad6676evb/zc706/Makefile             |  1 -
 projects/ad7616_sdz/zc706/Makefile            |  1 -
 projects/ad7616_sdz/zed/Makefile              |  1 -
 projects/ad7768evb/zed/Makefile               |  1 -
 projects/ad9265_fmc/zc706/Makefile            |  1 -
 projects/ad9434_fmc/zc706/Makefile            |  1 -
 projects/ad9467_fmc/kc705/Makefile            |  1 -
 projects/ad9467_fmc/zed/Makefile              |  1 -
 projects/ad9739a_fmc/zc706/Makefile           |  1 -
 projects/adrv9371x/zc706/Makefile             |  1 -
 projects/adv7511/ac701/Makefile               |  1 -
 projects/adv7511/kc705/Makefile               |  1 -
 projects/adv7511/kcu105/Makefile              |  1 -
 projects/adv7511/mitx045/Makefile             |  1 -
 projects/adv7511/vc707/Makefile               |  1 -
 projects/adv7511/zc702/Makefile               |  1 -
 projects/adv7511/zc706/Makefile               |  1 -
 projects/adv7511/zed/Makefile                 |  1 -
 projects/cftl_cip/zed/Makefile                |  1 -
 projects/cftl_std/zed/Makefile                |  1 -
 projects/cn0363/microzed/Makefile             |  1 -
 projects/cn0363/zed/Makefile                  |  1 -
 projects/daq1/zc706/Makefile                  |  1 -
 projects/daq2/a10gx/Makefile                  |  1 +
 projects/daq2/kc705/Makefile                  | 13 ++++++-------
 projects/daq2/kcu105/Makefile                 | 13 ++++++-------
 projects/daq2/vc707/Makefile                  | 13 ++++++-------
 projects/daq2/zc706/Makefile                  | 13 ++++++-------
 projects/daq3/a10gx/Makefile                  |  1 +
 projects/daq3/kcu105/Makefile                 |  1 -
 projects/daq3/zc706/Makefile                  |  1 -
 projects/fmcadc2/vc707/Makefile               |  1 -
 projects/fmcadc2/zc706/Makefile               |  1 -
 projects/fmcadc4/zc706/Makefile               |  1 -
 projects/fmcadc5/vc707/Makefile               |  1 -
 projects/fmcjesdadc1/kc705/Makefile           |  1 -
 projects/fmcjesdadc1/vc707/Makefile           |  1 -
 projects/fmcjesdadc1/zc706/Makefile           |  1 -
 projects/fmcomms1/ac701/Makefile              |  1 -
 projects/fmcomms1/kc705/Makefile              |  1 -
 projects/fmcomms1/vc707/Makefile              |  1 -
 projects/fmcomms1/zc702/Makefile              |  1 -
 projects/fmcomms1/zc706/Makefile              |  1 -
 projects/fmcomms1/zed/Makefile                |  1 -
 projects/fmcomms11/zc706/Makefile             |  1 -
 projects/fmcomms2/ac701/Makefile              |  1 -
 projects/fmcomms2/kc705/Makefile              |  1 -
 projects/fmcomms2/mitx045/Makefile            |  1 -
 projects/fmcomms2/vc707/Makefile              |  1 -
 projects/fmcomms2/zc702/Makefile              |  1 -
 projects/fmcomms2/zc706/Makefile              |  1 -
 projects/fmcomms2/zcu102/Makefile             |  1 -
 projects/fmcomms2/zed/Makefile                |  1 -
 projects/fmcomms5/zc702/Makefile              |  1 -
 projects/fmcomms5/zc706/Makefile              |  1 -
 projects/fmcomms6/zc706/Makefile              |  1 -
 projects/fmcomms7/zc706/Makefile              |  1 -
 projects/imageon/zc706/Makefile               |  1 -
 projects/imageon/zed/Makefile                 |  1 -
 projects/motcon2_fmc/zed/Makefile             |  1 -
 projects/pzsdr/ccbrk/Makefile                 |  1 -
 projects/pzsdr/ccbrk_cmos/Makefile            |  1 -
 projects/pzsdr/ccfmc/Makefile                 |  1 -
 projects/pzsdr/ccpci/Makefile                 |  1 -
 projects/pzsdr1/ccbrk/Makefile                |  1 -
 projects/pzsdr1/ccbrk_cmos/Makefile           |  1 -
 projects/usb_fx3/zc706/Makefile               |  1 -
 projects/usdrx1/zc706/Makefile                |  1 -
 76 files changed, 47 insertions(+), 112 deletions(-)

diff --git a/library/Makefile b/library/Makefile
index 1b40b5171..58ebfc6c1 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -31,7 +31,6 @@ clean:
 	make -C axi_ad9684 clean
 	make -C axi_ad9739a clean
 	make -C axi_adcfifo clean
-	make -C axi_adxcvr clean
 	make -C axi_clkgen clean
 	make -C axi_dacfifo clean
 	make -C axi_dmac clean
@@ -56,7 +55,6 @@ clean:
 	make -C spi_engine/spi_engine_interconnect clean
 	make -C spi_engine/spi_engine_offload clean
 	make -C util_adcfifo clean
-	make -C util_adxcvr clean
 	make -C util_axis_fifo clean
 	make -C util_axis_resize clean
 	make -C util_bsplit clean
@@ -75,6 +73,8 @@ clean:
 	make -C util_tdd_sync clean
 	make -C util_upack clean
 	make -C util_wfifo clean
+	make -C xilinx/axi_adxcvr clean
+	make -C xilinx/util_adxcvr clean
 
 
 clean-all:clean
@@ -102,7 +102,6 @@ lib:
 	-make -C axi_ad9684
 	-make -C axi_ad9739a
 	-make -C axi_adcfifo
-	-make -C axi_adxcvr
 	-make -C axi_clkgen
 	-make -C axi_dacfifo
 	-make -C axi_dmac
@@ -127,7 +126,6 @@ lib:
 	-make -C spi_engine/spi_engine_interconnect
 	-make -C spi_engine/spi_engine_offload
 	-make -C util_adcfifo
-	-make -C util_adxcvr
 	-make -C util_axis_fifo
 	-make -C util_axis_resize
 	-make -C util_bsplit
@@ -146,6 +144,8 @@ lib:
 	-make -C util_tdd_sync
 	-make -C util_upack
 	-make -C util_wfifo
+	-make -C xilinx/axi_adxcvr
+	-make -C xilinx/util_adxcvr
 
 ####################################################################################
 ####################################################################################
diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile
index e0736d1a8..5b9dfea8c 100644
--- a/library/axi_ad7616/Makefile
+++ b/library/axi_ad7616/Makefile
@@ -14,10 +14,10 @@ M_DEPS += axi_ad7616_control.v
 M_DEPS += axi_ad7616_pif.v
 M_DEPS += axi_ad7616_maxis2wrfifo.v
 M_DEPS += axi_ad7616.v
-M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
-M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
-M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
-M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
+M_DEPS += ../spi_engine_execution/spi_engine_execution.xpr
+M_DEPS += ../axi_spi_engine/axi_spi_engine.xpr
+M_DEPS += ../spi_engine_offload/spi_engine_offload.xpr
+M_DEPS += ../spi_engine_interconnect/spi_engine_interconnect.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -52,9 +52,9 @@ axi_ad7616.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_ad7616_ip.tcl  >> axi_ad7616_ip.log 2>&1
 
 dep:
-	make -C ../spi_engine/spi_engine_execution/
-	make -C ../spi_engine/axi_spi_engine/
-	make -C ../spi_engine/spi_engine_offload/
-	make -C ../spi_engine/spi_engine_interconnect/
+	make -C ../spi_engine_execution
+	make -C ../axi_spi_engine
+	make -C ../spi_engine_offload
+	make -C ../spi_engine_interconnect
 ####################################################################################
 ####################################################################################
diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile
index 909ea7a81..2565a8954 100644
--- a/library/axi_dmac/Makefile
+++ b/library/axi_dmac/Makefile
@@ -64,7 +64,7 @@ axi_dmac.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_dmac_ip.tcl  >> axi_dmac_ip.log 2>&1
 
 dep:
-	make -C ../util_axis_resize/
-	make -C ../util_axis_fifo/
+	make -C ../util_axis_resize
+	make -C ../util_axis_fifo
 ####################################################################################
 ####################################################################################
diff --git a/library/spi_engine/axi_spi_engine/Makefile b/library/spi_engine/axi_spi_engine/Makefile
index fe1a9dc4a..f915b7cf9 100644
--- a/library/spi_engine/axi_spi_engine/Makefile
+++ b/library/spi_engine/axi_spi_engine/Makefile
@@ -48,6 +48,6 @@ axi_spi_engine.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_spi_engine_ip.tcl  >> axi_spi_engine_ip.log 2>&1
 
 dep:
-	make -C ../../util_axis_fifo/
+	make -C ../../util_axis_fifo
 ####################################################################################
 ####################################################################################
diff --git a/library/xilinx/axi_adxcvr/Makefile b/library/xilinx/axi_adxcvr/Makefile
index 3d4ab3ed4..89ddeba33 100644
--- a/library/xilinx/axi_adxcvr/Makefile
+++ b/library/xilinx/axi_adxcvr/Makefile
@@ -6,9 +6,9 @@
 ####################################################################################
 
 M_DEPS := axi_adxcvr_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/up_axi.v
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip.tcl
+M_DEPS += ../../common/up_axi.v
 M_DEPS += axi_adxcvr_es.v
 M_DEPS += axi_adxcvr_up.v
 M_DEPS += axi_adxcvr_mdrp.v
diff --git a/library/xilinx/util_adxcvr/Makefile b/library/xilinx/util_adxcvr/Makefile
index c5bd23c76..41bb4d5ee 100644
--- a/library/xilinx/util_adxcvr/Makefile
+++ b/library/xilinx/util_adxcvr/Makefile
@@ -6,8 +6,8 @@
 ####################################################################################
 
 M_DEPS := util_adxcvr_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip.tcl
 M_DEPS += util_adxcvr_constr.xdc
 M_DEPS += util_adxcvr_xcm.v
 M_DEPS += util_adxcvr_xch.v
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
index d73da5444..06a4ff7ed 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
+++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
@@ -1,6 +1,6 @@
 ## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY!
 
-source ../scripts/adi_env.tcl
+source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create util_adxcvr
diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile
index 641c1f02f..5e0c9487c 100644
--- a/projects/ad6676evb/vc707/Makefile
+++ b/projects/ad6676evb/vc707/Makefile
@@ -37,7 +37,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile
index 3ba298f82..b11811429 100644
--- a/projects/ad6676evb/zc706/Makefile
+++ b/projects/ad6676evb/zc706/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile
index ed84e3087..539ba381d 100644
--- a/projects/ad7616_sdz/zc706/Makefile
+++ b/projects/ad7616_sdz/zc706/Makefile
@@ -40,7 +40,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile
index d95085855..635cb90be 100644
--- a/projects/ad7616_sdz/zed/Makefile
+++ b/projects/ad7616_sdz/zed/Makefile
@@ -42,7 +42,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad7768evb/zed/Makefile b/projects/ad7768evb/zed/Makefile
index c9ad07e82..b14ce41b3 100644
--- a/projects/ad7768evb/zed/Makefile
+++ b/projects/ad7768evb/zed/Makefile
@@ -38,7 +38,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9265_fmc/zc706/Makefile b/projects/ad9265_fmc/zc706/Makefile
index 8787a78d6..9ad95e317 100644
--- a/projects/ad9265_fmc/zc706/Makefile
+++ b/projects/ad9265_fmc/zc706/Makefile
@@ -37,7 +37,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9434_fmc/zc706/Makefile b/projects/ad9434_fmc/zc706/Makefile
index 6db32568b..70d247f5c 100644
--- a/projects/ad9434_fmc/zc706/Makefile
+++ b/projects/ad9434_fmc/zc706/Makefile
@@ -37,7 +37,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9467_fmc/kc705/Makefile b/projects/ad9467_fmc/kc705/Makefile
index 51930e6f2..887838189 100644
--- a/projects/ad9467_fmc/kc705/Makefile
+++ b/projects/ad9467_fmc/kc705/Makefile
@@ -35,7 +35,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9467_fmc/zed/Makefile b/projects/ad9467_fmc/zed/Makefile
index c8e8554ff..0eee2b11c 100644
--- a/projects/ad9467_fmc/zed/Makefile
+++ b/projects/ad9467_fmc/zed/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/ad9739a_fmc/zc706/Makefile b/projects/ad9739a_fmc/zc706/Makefile
index 7b0a212b9..481327975 100644
--- a/projects/ad9739a_fmc/zc706/Makefile
+++ b/projects/ad9739a_fmc/zc706/Makefile
@@ -36,7 +36,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
index 7f5e028d2..933be8e1c 100644
--- a/projects/adrv9371x/zc706/Makefile
+++ b/projects/adrv9371x/zc706/Makefile
@@ -48,7 +48,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile
index e0ab84e33..0dfca3289 100644
--- a/projects/adv7511/ac701/Makefile
+++ b/projects/adv7511/ac701/Makefile
@@ -35,7 +35,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/kc705/Makefile b/projects/adv7511/kc705/Makefile
index 0926f5973..69dea3d47 100644
--- a/projects/adv7511/kc705/Makefile
+++ b/projects/adv7511/kc705/Makefile
@@ -35,7 +35,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile
index 4b1000907..9a09b9f4f 100644
--- a/projects/adv7511/kcu105/Makefile
+++ b/projects/adv7511/kcu105/Makefile
@@ -35,7 +35,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile
index 33d21bb6c..80c65e379 100644
--- a/projects/adv7511/mitx045/Makefile
+++ b/projects/adv7511/mitx045/Makefile
@@ -34,7 +34,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/vc707/Makefile b/projects/adv7511/vc707/Makefile
index bed52b1dc..b347dcd33 100644
--- a/projects/adv7511/vc707/Makefile
+++ b/projects/adv7511/vc707/Makefile
@@ -35,7 +35,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/zc702/Makefile b/projects/adv7511/zc702/Makefile
index 4d69884e1..876158ecd 100644
--- a/projects/adv7511/zc702/Makefile
+++ b/projects/adv7511/zc702/Makefile
@@ -32,7 +32,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/zc706/Makefile b/projects/adv7511/zc706/Makefile
index d9f86a2fa..d00baa5e9 100644
--- a/projects/adv7511/zc706/Makefile
+++ b/projects/adv7511/zc706/Makefile
@@ -32,7 +32,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/adv7511/zed/Makefile b/projects/adv7511/zed/Makefile
index 9962f024d..26d233c0b 100644
--- a/projects/adv7511/zed/Makefile
+++ b/projects/adv7511/zed/Makefile
@@ -34,7 +34,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/cftl_cip/zed/Makefile b/projects/cftl_cip/zed/Makefile
index 48955f00a..687b6a0e0 100644
--- a/projects/cftl_cip/zed/Makefile
+++ b/projects/cftl_cip/zed/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/cftl_std/zed/Makefile b/projects/cftl_std/zed/Makefile
index 5c3581bb5..55923a3eb 100644
--- a/projects/cftl_std/zed/Makefile
+++ b/projects/cftl_std/zed/Makefile
@@ -36,7 +36,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile
index 63fc458db..81bbb9aff 100644
--- a/projects/cn0363/microzed/Makefile
+++ b/projects/cn0363/microzed/Makefile
@@ -43,7 +43,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile
index 7e2ba850f..e5a811c0c 100644
--- a/projects/cn0363/zed/Makefile
+++ b/projects/cn0363/zed/Makefile
@@ -47,7 +47,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile
index 15f689ed4..f17d14899 100644
--- a/projects/daq1/zc706/Makefile
+++ b/projects/daq1/zc706/Makefile
@@ -44,7 +44,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index cf18f1a8c..a7ea3bfcc 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -54,6 +54,7 @@ M_DEPS += ../../../library/common/ad_jesd_align.v
 M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
 M_DEPS += ../../../library/common/altera/MULT_MACRO.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile
index 4da1284aa..728e1bcbf 100644
--- a/projects/daq2/kc705/Makefile
+++ b/projects/daq2/kc705/Makefile
@@ -21,10 +21,10 @@ M_DEPS += ../../common/kc705/kc705_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
-M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
-M_DEPS += ../../../library/util_adxcvr/util_adxcvr.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
@@ -43,7 +43,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
@@ -58,10 +57,10 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
-	make -C ../../../library/axi_adxcvr clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/util_adcfifo clean
-	make -C ../../../library/util_adxcvr clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_upack clean
@@ -75,10 +74,10 @@ daq2_kc705.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
-	make -C ../../../library/axi_adxcvr
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/util_adcfifo
-	make -C ../../../library/util_adxcvr
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_upack
diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile
index 9276c41c7..7ceb9267d 100644
--- a/projects/daq2/kcu105/Makefile
+++ b/projects/daq2/kcu105/Makefile
@@ -21,10 +21,10 @@ M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
-M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
-M_DEPS += ../../../library/util_adxcvr/util_adxcvr.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
@@ -43,7 +43,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
@@ -58,10 +57,10 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
-	make -C ../../../library/axi_adxcvr clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/util_adcfifo clean
-	make -C ../../../library/util_adxcvr clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_upack clean
@@ -75,10 +74,10 @@ daq2_kcu105.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
-	make -C ../../../library/axi_adxcvr
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/util_adcfifo
-	make -C ../../../library/util_adxcvr
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_upack
diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile
index 8839fb7e6..ca4997397 100644
--- a/projects/daq2/vc707/Makefile
+++ b/projects/daq2/vc707/Makefile
@@ -21,10 +21,10 @@ M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
-M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
-M_DEPS += ../../../library/util_adxcvr/util_adxcvr.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
@@ -43,7 +43,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
@@ -58,10 +57,10 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
-	make -C ../../../library/axi_adxcvr clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/util_adcfifo clean
-	make -C ../../../library/util_adxcvr clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_upack clean
@@ -75,10 +74,10 @@ daq2_vc707.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
-	make -C ../../../library/axi_adxcvr
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/util_adcfifo
-	make -C ../../../library/util_adxcvr
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_upack
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index 5f0d8a8c1..ee79c64bc 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -24,13 +24,13 @@ M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
-M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
-M_DEPS += ../../../library/util_adxcvr/util_adxcvr.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
@@ -49,7 +49,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
@@ -65,13 +64,13 @@ clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/axi_adcfifo clean
-	make -C ../../../library/axi_adxcvr clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/util_adcfifo clean
-	make -C ../../../library/util_adxcvr clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_upack clean
@@ -86,13 +85,13 @@ lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/axi_adcfifo
-	make -C ../../../library/axi_adxcvr
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/util_adcfifo
-	make -C ../../../library/util_adxcvr
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_upack
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index a15ed07fd..bf93b791b 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -53,6 +53,7 @@ M_DEPS += ../../../library/common/ad_jesd_align.v
 M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
 M_DEPS += ../../../library/common/altera/MULT_MACRO.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
index 098251b46..256432946 100644
--- a/projects/daq3/kcu105/Makefile
+++ b/projects/daq3/kcu105/Makefile
@@ -43,7 +43,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index f6fd315d0..a591c3306 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -50,7 +50,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index bfd4ee312..3ae995270 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -40,7 +40,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index c660319a3..7a83de7f5 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -43,7 +43,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index 4275abf7f..b4f4379f4 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -46,7 +46,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile
index c85922cb7..38905f714 100644
--- a/projects/fmcadc5/vc707/Makefile
+++ b/projects/fmcadc5/vc707/Makefile
@@ -44,7 +44,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile
index 6cf8067b6..7050c879e 100644
--- a/projects/fmcjesdadc1/kc705/Makefile
+++ b/projects/fmcjesdadc1/kc705/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile
index 5fb268b22..379caa28b 100644
--- a/projects/fmcjesdadc1/vc707/Makefile
+++ b/projects/fmcjesdadc1/vc707/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile
index 3a1c30df6..e3c623304 100644
--- a/projects/fmcjesdadc1/zc706/Makefile
+++ b/projects/fmcjesdadc1/zc706/Makefile
@@ -41,7 +41,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms1/ac701/Makefile
index 822102ea1..9c8a6771c 100644
--- a/projects/fmcomms1/ac701/Makefile
+++ b/projects/fmcomms1/ac701/Makefile
@@ -38,7 +38,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/kc705/Makefile b/projects/fmcomms1/kc705/Makefile
index 6c60d5cba..5d00e2573 100644
--- a/projects/fmcomms1/kc705/Makefile
+++ b/projects/fmcomms1/kc705/Makefile
@@ -38,7 +38,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/vc707/Makefile b/projects/fmcomms1/vc707/Makefile
index 927e087a1..8b7b14948 100644
--- a/projects/fmcomms1/vc707/Makefile
+++ b/projects/fmcomms1/vc707/Makefile
@@ -38,7 +38,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/zc702/Makefile b/projects/fmcomms1/zc702/Makefile
index 002c0e9f3..c5faab08a 100644
--- a/projects/fmcomms1/zc702/Makefile
+++ b/projects/fmcomms1/zc702/Makefile
@@ -40,7 +40,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/zc706/Makefile b/projects/fmcomms1/zc706/Makefile
index 429f7e554..5170046cd 100644
--- a/projects/fmcomms1/zc706/Makefile
+++ b/projects/fmcomms1/zc706/Makefile
@@ -40,7 +40,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms1/zed/Makefile b/projects/fmcomms1/zed/Makefile
index 5310104ab..79e54721f 100644
--- a/projects/fmcomms1/zed/Makefile
+++ b/projects/fmcomms1/zed/Makefile
@@ -42,7 +42,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index 5918ebca1..72b3b1c6b 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -47,7 +47,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile
index be2f72cd4..03282725e 100644
--- a/projects/fmcomms2/ac701/Makefile
+++ b/projects/fmcomms2/ac701/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile
index 05ac0f8f9..ab24ca35e 100644
--- a/projects/fmcomms2/kc705/Makefile
+++ b/projects/fmcomms2/kc705/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile
index 1a0cb9a32..ca53855ce 100644
--- a/projects/fmcomms2/mitx045/Makefile
+++ b/projects/fmcomms2/mitx045/Makefile
@@ -43,7 +43,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile
index 0e916389d..46327e71d 100644
--- a/projects/fmcomms2/vc707/Makefile
+++ b/projects/fmcomms2/vc707/Makefile
@@ -38,7 +38,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile
index 23ebf1452..439cfe22c 100644
--- a/projects/fmcomms2/zc702/Makefile
+++ b/projects/fmcomms2/zc702/Makefile
@@ -41,7 +41,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile
index 6124ac8a5..d3c52de44 100644
--- a/projects/fmcomms2/zc706/Makefile
+++ b/projects/fmcomms2/zc706/Makefile
@@ -40,7 +40,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/zcu102/Makefile b/projects/fmcomms2/zcu102/Makefile
index 12b25ef34..3418eb35a 100644
--- a/projects/fmcomms2/zcu102/Makefile
+++ b/projects/fmcomms2/zcu102/Makefile
@@ -37,7 +37,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile
index 36c8f0f50..9fd8dcfc5 100644
--- a/projects/fmcomms2/zed/Makefile
+++ b/projects/fmcomms2/zed/Makefile
@@ -43,7 +43,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile
index 9a85c25db..bba74f74a 100644
--- a/projects/fmcomms5/zc702/Makefile
+++ b/projects/fmcomms5/zc702/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile
index b383576b9..5aee574f5 100644
--- a/projects/fmcomms5/zc706/Makefile
+++ b/projects/fmcomms5/zc706/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms6/zc706/Makefile b/projects/fmcomms6/zc706/Makefile
index b50f31185..3846e87f0 100644
--- a/projects/fmcomms6/zc706/Makefile
+++ b/projects/fmcomms6/zc706/Makefile
@@ -39,7 +39,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index 076394047..3f42f718c 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -49,7 +49,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile
index cb5df8367..bf8076634 100644
--- a/projects/imageon/zc706/Makefile
+++ b/projects/imageon/zc706/Makefile
@@ -36,7 +36,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile
index a32aa12af..bf3a40c13 100644
--- a/projects/imageon/zed/Makefile
+++ b/projects/imageon/zed/Makefile
@@ -38,7 +38,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/motcon2_fmc/zed/Makefile b/projects/motcon2_fmc/zed/Makefile
index dd9e940bf..e214e56d0 100644
--- a/projects/motcon2_fmc/zed/Makefile
+++ b/projects/motcon2_fmc/zed/Makefile
@@ -42,7 +42,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile
index 2df8fff21..c9b8d0aa0 100644
--- a/projects/pzsdr/ccbrk/Makefile
+++ b/projects/pzsdr/ccbrk/Makefile
@@ -44,7 +44,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
index 1db280a0e..bc6539695 100644
--- a/projects/pzsdr/ccbrk_cmos/Makefile
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -44,7 +44,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile
index 5fe413176..643a619e6 100644
--- a/projects/pzsdr/ccfmc/Makefile
+++ b/projects/pzsdr/ccfmc/Makefile
@@ -48,7 +48,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci/Makefile
index e621f6bf4..08fce8aaf 100644
--- a/projects/pzsdr/ccpci/Makefile
+++ b/projects/pzsdr/ccpci/Makefile
@@ -41,7 +41,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
index 407e25fb5..8c9589b67 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -42,7 +42,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/pzsdr1/ccbrk_cmos/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile
index 4497779d9..033e96bfd 100644
--- a/projects/pzsdr1/ccbrk_cmos/Makefile
+++ b/projects/pzsdr1/ccbrk_cmos/Makefile
@@ -42,7 +42,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile
index 916c1b8ce..eb786cf55 100644
--- a/projects/usb_fx3/zc706/Makefile
+++ b/projects/usb_fx3/zc706/Makefile
@@ -35,7 +35,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index ee90181bc..1add6ecb0 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -42,7 +42,6 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
-M_FLIST += *.ip_user_files
 
 
 

From cb23ba8bb7070377fe658a423aaae5d6f0e66a4f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 4 Aug 2016 14:17:04 -0400
Subject: [PATCH 370/972] make- script needs update

---
 library/xilinx/axi_adxcvr/Makefile  | 10 +++++-----
 library/xilinx/util_adxcvr/Makefile | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/library/xilinx/axi_adxcvr/Makefile b/library/xilinx/axi_adxcvr/Makefile
index 89ddeba33..71ac0eda3 100644
--- a/library/xilinx/axi_adxcvr/Makefile
+++ b/library/xilinx/axi_adxcvr/Makefile
@@ -14,10 +14,10 @@ M_DEPS += axi_adxcvr_up.v
 M_DEPS += axi_adxcvr_mdrp.v
 M_DEPS += axi_adxcvr_mstatus.v
 M_DEPS += axi_adxcvr.v
-M_DEPS += ../interfaces/if_xcvr_cm.xml
-M_DEPS += ../interfaces/if_xcvr_cm_rtl.xml
-M_DEPS += ../interfaces/if_xcvr_ch.xml
-M_DEPS += ../interfaces/if_xcvr_ch_rtl.xml
+M_DEPS += ../../interfaces/if_xcvr_cm.xml
+M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
+M_DEPS += ../../interfaces/if_xcvr_ch.xml
+M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
@@ -52,6 +52,6 @@ axi_adxcvr.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_adxcvr_ip.tcl  >> axi_adxcvr_ip.log 2>&1
 
 dep:
-	make -C ../interfaces
+	make -C ../../interfaces
 ####################################################################################
 ####################################################################################
diff --git a/library/xilinx/util_adxcvr/Makefile b/library/xilinx/util_adxcvr/Makefile
index 41bb4d5ee..bd135b94f 100644
--- a/library/xilinx/util_adxcvr/Makefile
+++ b/library/xilinx/util_adxcvr/Makefile
@@ -12,10 +12,10 @@ M_DEPS += util_adxcvr_constr.xdc
 M_DEPS += util_adxcvr_xcm.v
 M_DEPS += util_adxcvr_xch.v
 M_DEPS += util_adxcvr.v
-M_DEPS += ../interfaces/if_xcvr_cm.xml
-M_DEPS += ../interfaces/if_xcvr_cm_rtl.xml
-M_DEPS += ../interfaces/if_xcvr_ch.xml
-M_DEPS += ../interfaces/if_xcvr_ch_rtl.xml
+M_DEPS += ../../interfaces/if_xcvr_cm.xml
+M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
+M_DEPS += ../../interfaces/if_xcvr_ch.xml
+M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
@@ -50,6 +50,6 @@ util_adxcvr.xpr: $(M_DEPS)
 	$(M_VIVADO) util_adxcvr_ip.tcl  >> util_adxcvr_ip.log 2>&1
 
 dep:
-	make -C ../interfaces
+	make -C ../../interfaces
 ####################################################################################
 ####################################################################################

From d60bce654c15b93505e34f13c3aaf1025f73834b Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 5 Aug 2016 15:16:04 +0300
Subject: [PATCH 371/972] Makefiles: Updated Makefiles so they run correctly
 with gnuwin32 tools

---
 library/axi_ad6676/Makefile                    |  2 +-
 library/axi_ad7616/Makefile                    | 18 +++++++++---------
 library/axi_ad9122/Makefile                    |  2 +-
 library/axi_ad9144/Makefile                    |  2 +-
 library/axi_ad9152/Makefile                    |  2 +-
 library/axi_ad9162/Makefile                    |  2 +-
 library/axi_ad9234/Makefile                    |  2 +-
 library/axi_ad9250/Makefile                    |  2 +-
 library/axi_ad9265/Makefile                    |  2 +-
 library/axi_ad9361/Makefile                    |  2 +-
 library/axi_ad9371/Makefile                    |  2 +-
 library/axi_ad9434/Makefile                    |  2 +-
 library/axi_ad9467/Makefile                    |  2 +-
 library/axi_ad9625/Makefile                    |  2 +-
 library/axi_ad9643/Makefile                    |  2 +-
 library/axi_ad9652/Makefile                    |  2 +-
 library/axi_ad9671/Makefile                    |  2 +-
 library/axi_ad9680/Makefile                    |  2 +-
 library/axi_ad9684/Makefile                    |  2 +-
 library/axi_ad9739a/Makefile                   |  2 +-
 library/axi_adcfifo/Makefile                   |  2 +-
 library/axi_clkgen/Makefile                    |  2 +-
 library/axi_dacfifo/Makefile                   |  2 +-
 library/axi_dmac/Makefile                      |  6 +++---
 library/axi_generic_adc/Makefile               |  2 +-
 library/axi_gpreg/Makefile                     |  2 +-
 library/axi_hdmi_rx/Makefile                   |  2 +-
 library/axi_hdmi_tx/Makefile                   |  2 +-
 library/axi_i2s_adi/Makefile                   |  2 +-
 library/axi_jesd_gt/Makefile                   |  2 +-
 library/axi_mc_controller/Makefile             |  2 +-
 library/axi_mc_current_monitor/Makefile        |  2 +-
 library/axi_mc_speed/Makefile                  |  2 +-
 library/axi_spdif_rx/Makefile                  |  2 +-
 library/axi_spdif_tx/Makefile                  |  2 +-
 library/axi_usb_fx3/Makefile                   |  2 +-
 library/cn0363/cn0363_dma_sequencer/Makefile   |  2 +-
 library/cn0363/cn0363_phase_data_sync/Makefile |  2 +-
 library/cordic_demod/Makefile                  |  2 +-
 library/spi_engine/axi_spi_engine/Makefile     |  4 ++--
 .../spi_engine/spi_engine_execution/Makefile   |  2 +-
 .../spi_engine_interconnect/Makefile           |  2 +-
 library/spi_engine/spi_engine_offload/Makefile |  2 +-
 library/util_adcfifo/Makefile                  |  2 +-
 library/util_axis_fifo/Makefile                |  2 +-
 library/util_axis_resize/Makefile              |  2 +-
 library/util_bsplit/Makefile                   |  2 +-
 library/util_ccat/Makefile                     |  2 +-
 library/util_cpack/Makefile                    |  2 +-
 library/util_dacfifo/Makefile                  |  2 +-
 library/util_gmii_to_rgmii/Makefile            |  2 +-
 library/util_gtlb/Makefile                     |  2 +-
 library/util_i2c_mixer/Makefile                |  2 +-
 library/util_jesd_gt/Makefile                  |  2 +-
 library/util_mfifo/Makefile                    |  2 +-
 library/util_pmod_adc/Makefile                 |  2 +-
 library/util_pmod_fmeter/Makefile              |  2 +-
 library/util_rfifo/Makefile                    |  2 +-
 library/util_sigma_delta_spi/Makefile          |  2 +-
 library/util_tdd_sync/Makefile                 |  2 +-
 library/util_upack/Makefile                    |  2 +-
 library/util_wfifo/Makefile                    |  2 +-
 library/xilinx/axi_adxcvr/Makefile             |  2 +-
 library/xilinx/util_adxcvr/Makefile            |  2 +-
 projects/ad6676evb/vc707/Makefile              |  3 ++-
 projects/ad6676evb/zc706/Makefile              |  3 ++-
 projects/ad7616_sdz/zc706/Makefile             |  3 ++-
 projects/ad7616_sdz/zed/Makefile               |  3 ++-
 projects/ad7768evb/zed/Makefile                |  3 ++-
 projects/ad9265_fmc/zc706/Makefile             |  3 ++-
 projects/ad9434_fmc/zc706/Makefile             |  3 ++-
 projects/ad9467_fmc/kc705/Makefile             |  3 ++-
 projects/ad9467_fmc/zed/Makefile               |  3 ++-
 projects/ad9739a_fmc/zc706/Makefile            |  3 ++-
 projects/adrv9371x/a10soc/Makefile             |  2 +-
 projects/adrv9371x/zc706/Makefile              |  3 ++-
 projects/adv7511/ac701/Makefile                |  3 ++-
 projects/adv7511/kc705/Makefile                |  3 ++-
 projects/adv7511/kcu105/Makefile               |  3 ++-
 projects/adv7511/mitx045/Makefile              |  3 ++-
 projects/adv7511/vc707/Makefile                |  3 ++-
 projects/adv7511/zc702/Makefile                |  3 ++-
 projects/adv7511/zc706/Makefile                |  3 ++-
 projects/adv7511/zed/Makefile                  |  3 ++-
 projects/arradio/c5soc/Makefile                |  2 +-
 projects/cftl_cip/zed/Makefile                 |  3 ++-
 projects/cftl_std/zed/Makefile                 |  3 ++-
 projects/cn0363/microzed/Makefile              |  3 ++-
 projects/cn0363/zed/Makefile                   |  3 ++-
 projects/common/a5gte/Makefile                 |  2 +-
 projects/daq1/zc706/Makefile                   |  3 ++-
 projects/daq2/a10gx/Makefile                   |  2 +-
 projects/daq2/kc705/Makefile                   |  3 ++-
 projects/daq2/kcu105/Makefile                  |  3 ++-
 projects/daq2/vc707/Makefile                   |  3 ++-
 projects/daq2/zc706/Makefile                   |  3 ++-
 projects/daq3/a10gx/Makefile                   |  2 +-
 projects/daq3/kcu105/Makefile                  |  3 ++-
 projects/daq3/zc706/Makefile                   |  3 ++-
 projects/fmcadc2/vc707/Makefile                |  3 ++-
 projects/fmcadc2/zc706/Makefile                |  3 ++-
 projects/fmcadc4/zc706/Makefile                |  3 ++-
 projects/fmcadc5/vc707/Makefile                |  3 ++-
 projects/fmcjesdadc1/a5gt/Makefile             |  2 +-
 projects/fmcjesdadc1/a5soc/Makefile            |  2 +-
 projects/fmcjesdadc1/kc705/Makefile            |  3 ++-
 projects/fmcjesdadc1/vc707/Makefile            |  3 ++-
 projects/fmcjesdadc1/zc706/Makefile            |  3 ++-
 projects/fmcomms1/ac701/Makefile               |  3 ++-
 projects/fmcomms1/kc705/Makefile               |  3 ++-
 projects/fmcomms1/vc707/Makefile               |  3 ++-
 projects/fmcomms1/zc702/Makefile               |  3 ++-
 projects/fmcomms1/zc706/Makefile               |  3 ++-
 projects/fmcomms1/zed/Makefile                 |  3 ++-
 projects/fmcomms11/zc706/Makefile              |  3 ++-
 projects/fmcomms2/a10gx/Makefile               |  2 +-
 projects/fmcomms2/ac701/Makefile               |  3 ++-
 projects/fmcomms2/kc705/Makefile               |  3 ++-
 projects/fmcomms2/mitx045/Makefile             |  3 ++-
 projects/fmcomms2/vc707/Makefile               |  3 ++-
 projects/fmcomms2/zc702/Makefile               |  3 ++-
 projects/fmcomms2/zc706/Makefile               |  3 ++-
 projects/fmcomms2/zcu102/Makefile              |  3 ++-
 projects/fmcomms2/zed/Makefile                 |  3 ++-
 projects/fmcomms5/zc702/Makefile               |  3 ++-
 projects/fmcomms5/zc706/Makefile               |  3 ++-
 projects/fmcomms6/zc706/Makefile               |  3 ++-
 projects/fmcomms7/zc706/Makefile               |  3 ++-
 projects/imageon/zc706/Makefile                |  3 ++-
 projects/imageon/zed/Makefile                  |  3 ++-
 projects/motcon2_fmc/zed/Makefile              |  3 ++-
 projects/pzsdr/ccbrk/Makefile                  |  3 ++-
 projects/pzsdr/ccbrk_cmos/Makefile             |  3 ++-
 projects/pzsdr/ccfmc/Makefile                  |  3 ++-
 projects/pzsdr/ccpci/Makefile                  |  3 ++-
 projects/pzsdr1/ccbrk/Makefile                 |  3 ++-
 projects/pzsdr1/ccbrk_cmos/Makefile            |  3 ++-
 projects/usb_fx3/zc706/Makefile                |  3 ++-
 projects/usdrx1/a5gt/Makefile                  |  2 +-
 projects/usdrx1/zc706/Makefile                 |  3 ++-
 140 files changed, 218 insertions(+), 151 deletions(-)

diff --git a/library/axi_ad6676/Makefile b/library/axi_ad6676/Makefile
index e9a652ca6..07bef5ad4 100644
--- a/library/axi_ad6676/Makefile
+++ b/library/axi_ad6676/Makefile
@@ -52,7 +52,7 @@ clean-all:
 
 
 axi_ad6676.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad6676_ip.tcl  >> axi_ad6676_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile
index 5b9dfea8c..4c1cd4690 100644
--- a/library/axi_ad7616/Makefile
+++ b/library/axi_ad7616/Makefile
@@ -14,10 +14,10 @@ M_DEPS += axi_ad7616_control.v
 M_DEPS += axi_ad7616_pif.v
 M_DEPS += axi_ad7616_maxis2wrfifo.v
 M_DEPS += axi_ad7616.v
-M_DEPS += ../spi_engine_execution/spi_engine_execution.xpr
-M_DEPS += ../axi_spi_engine/axi_spi_engine.xpr
-M_DEPS += ../spi_engine_offload/spi_engine_offload.xpr
-M_DEPS += ../spi_engine_interconnect/spi_engine_interconnect.xpr
+M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
+M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
+M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
+M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -48,13 +48,13 @@ clean-all:
 
 
 axi_ad7616.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad7616_ip.tcl  >> axi_ad7616_ip.log 2>&1
 
 dep:
-	make -C ../spi_engine_execution
-	make -C ../axi_spi_engine
-	make -C ../spi_engine_offload
-	make -C ../spi_engine_interconnect
+	make -C ../spi_engine/spi_engine_execution/
+	make -C ../spi_engine/axi_spi_engine/
+	make -C ../spi_engine/spi_engine_offload/
+	make -C ../spi_engine/spi_engine_interconnect/
 ####################################################################################
 ####################################################################################
diff --git a/library/axi_ad9122/Makefile b/library/axi_ad9122/Makefile
index aa9711858..cf6dc7c0b 100644
--- a/library/axi_ad9122/Makefile
+++ b/library/axi_ad9122/Makefile
@@ -58,7 +58,7 @@ clean-all:
 
 
 axi_ad9122.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9122_ip.tcl  >> axi_ad9122_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9144/Makefile b/library/axi_ad9144/Makefile
index bbe2e084d..1a62aaee0 100644
--- a/library/axi_ad9144/Makefile
+++ b/library/axi_ad9144/Makefile
@@ -54,7 +54,7 @@ clean-all:
 
 
 axi_ad9144.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9144_ip.tcl  >> axi_ad9144_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9152/Makefile b/library/axi_ad9152/Makefile
index 2d3974280..70ef37ad3 100644
--- a/library/axi_ad9152/Makefile
+++ b/library/axi_ad9152/Makefile
@@ -54,7 +54,7 @@ clean-all:
 
 
 axi_ad9152.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9152_ip.tcl  >> axi_ad9152_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9162/Makefile b/library/axi_ad9162/Makefile
index cb4a9469b..73919d834 100644
--- a/library/axi_ad9162/Makefile
+++ b/library/axi_ad9162/Makefile
@@ -54,7 +54,7 @@ clean-all:
 
 
 axi_ad9162.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9162_ip.tcl  >> axi_ad9162_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9234/Makefile b/library/axi_ad9234/Makefile
index 9b4a4e670..b034edda7 100644
--- a/library/axi_ad9234/Makefile
+++ b/library/axi_ad9234/Makefile
@@ -51,7 +51,7 @@ clean-all:
 
 
 axi_ad9234.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9234_ip.tcl  >> axi_ad9234_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9250/Makefile b/library/axi_ad9250/Makefile
index 35499b851..02c8ac556 100644
--- a/library/axi_ad9250/Makefile
+++ b/library/axi_ad9250/Makefile
@@ -53,7 +53,7 @@ clean-all:
 
 
 axi_ad9250.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9250_ip.tcl  >> axi_ad9250_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9265/Makefile b/library/axi_ad9265/Makefile
index d10188c50..6f6e07c31 100644
--- a/library/axi_ad9265/Makefile
+++ b/library/axi_ad9265/Makefile
@@ -57,7 +57,7 @@ clean-all:
 
 
 axi_ad9265.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9265_ip.tcl  >> axi_ad9265_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile
index b0bf60371..05640fc36 100644
--- a/library/axi_ad9361/Makefile
+++ b/library/axi_ad9361/Makefile
@@ -77,7 +77,7 @@ clean-all:
 
 
 axi_ad9361.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9361_ip.tcl  >> axi_ad9361_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9371/Makefile b/library/axi_ad9371/Makefile
index 9d6965166..bad4b3154 100644
--- a/library/axi_ad9371/Makefile
+++ b/library/axi_ad9371/Makefile
@@ -62,7 +62,7 @@ clean-all:
 
 
 axi_ad9371.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9371_ip.tcl  >> axi_ad9371_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9434/Makefile b/library/axi_ad9434/Makefile
index 9813805af..e9d7ef4de 100644
--- a/library/axi_ad9434/Makefile
+++ b/library/axi_ad9434/Makefile
@@ -57,7 +57,7 @@ clean-all:
 
 
 axi_ad9434.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9434_ip.tcl  >> axi_ad9434_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9467/Makefile b/library/axi_ad9467/Makefile
index bd023d81f..940dc400f 100644
--- a/library/axi_ad9467/Makefile
+++ b/library/axi_ad9467/Makefile
@@ -56,7 +56,7 @@ clean-all:
 
 
 axi_ad9467.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9467_ip.tcl  >> axi_ad9467_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9625/Makefile b/library/axi_ad9625/Makefile
index 57fdc321a..cae11d228 100644
--- a/library/axi_ad9625/Makefile
+++ b/library/axi_ad9625/Makefile
@@ -54,7 +54,7 @@ clean-all:
 
 
 axi_ad9625.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9625_ip.tcl  >> axi_ad9625_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9643/Makefile b/library/axi_ad9643/Makefile
index 5b4c7ff34..44ca7a684 100644
--- a/library/axi_ad9643/Makefile
+++ b/library/axi_ad9643/Makefile
@@ -59,7 +59,7 @@ clean-all:
 
 
 axi_ad9643.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9643_ip.tcl  >> axi_ad9643_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9652/Makefile b/library/axi_ad9652/Makefile
index 4f38ceedb..478c0f50e 100644
--- a/library/axi_ad9652/Makefile
+++ b/library/axi_ad9652/Makefile
@@ -58,7 +58,7 @@ clean-all:
 
 
 axi_ad9652.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9652_ip.tcl  >> axi_ad9652_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9671/Makefile b/library/axi_ad9671/Makefile
index dd4590b3c..48dc964a2 100644
--- a/library/axi_ad9671/Makefile
+++ b/library/axi_ad9671/Makefile
@@ -54,7 +54,7 @@ clean-all:
 
 
 axi_ad9671.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9671_ip.tcl  >> axi_ad9671_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9680/Makefile b/library/axi_ad9680/Makefile
index 65f8ad28a..a27151775 100644
--- a/library/axi_ad9680/Makefile
+++ b/library/axi_ad9680/Makefile
@@ -53,7 +53,7 @@ clean-all:
 
 
 axi_ad9680.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9680_ip.tcl  >> axi_ad9680_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9684/Makefile b/library/axi_ad9684/Makefile
index dfec1c9ab..3f25f512f 100644
--- a/library/axi_ad9684/Makefile
+++ b/library/axi_ad9684/Makefile
@@ -57,7 +57,7 @@ clean-all:
 
 
 axi_ad9684.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9684_ip.tcl  >> axi_ad9684_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_ad9739a/Makefile b/library/axi_ad9739a/Makefile
index f55a287ab..43e235827 100644
--- a/library/axi_ad9739a/Makefile
+++ b/library/axi_ad9739a/Makefile
@@ -56,7 +56,7 @@ clean-all:
 
 
 axi_ad9739a.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_ad9739a_ip.tcl  >> axi_ad9739a_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_adcfifo/Makefile b/library/axi_adcfifo/Makefile
index 629722ba8..ce104a3bc 100644
--- a/library/axi_adcfifo/Makefile
+++ b/library/axi_adcfifo/Makefile
@@ -48,7 +48,7 @@ clean-all:
 
 
 axi_adcfifo.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_adcfifo_ip.tcl  >> axi_adcfifo_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_clkgen/Makefile b/library/axi_clkgen/Makefile
index e403b516b..0a1f03758 100644
--- a/library/axi_clkgen/Makefile
+++ b/library/axi_clkgen/Makefile
@@ -44,7 +44,7 @@ clean-all:
 
 
 axi_clkgen.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_clkgen_ip.tcl  >> axi_clkgen_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_dacfifo/Makefile b/library/axi_dacfifo/Makefile
index bac4b509e..0734805a6 100644
--- a/library/axi_dacfifo/Makefile
+++ b/library/axi_dacfifo/Makefile
@@ -46,7 +46,7 @@ clean-all:
 
 
 axi_dacfifo.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_dacfifo_ip.tcl  >> axi_dacfifo_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile
index 2565a8954..df36863dd 100644
--- a/library/axi_dmac/Makefile
+++ b/library/axi_dmac/Makefile
@@ -60,11 +60,11 @@ clean-all:
 
 
 axi_dmac.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_dmac_ip.tcl  >> axi_dmac_ip.log 2>&1
 
 dep:
-	make -C ../util_axis_resize
-	make -C ../util_axis_fifo
+	make -C ../util_axis_resize/
+	make -C ../util_axis_fifo/
 ####################################################################################
 ####################################################################################
diff --git a/library/axi_generic_adc/Makefile b/library/axi_generic_adc/Makefile
index bde2c8023..0b493a6f9 100644
--- a/library/axi_generic_adc/Makefile
+++ b/library/axi_generic_adc/Makefile
@@ -47,7 +47,7 @@ clean-all:
 
 
 axi_generic_adc.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_generic_adc_ip.tcl  >> axi_generic_adc_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_gpreg/Makefile b/library/axi_gpreg/Makefile
index a83047d14..a7d7a1d06 100644
--- a/library/axi_gpreg/Makefile
+++ b/library/axi_gpreg/Makefile
@@ -45,7 +45,7 @@ clean-all:
 
 
 axi_gpreg.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_gpreg_ip.tcl  >> axi_gpreg_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_hdmi_rx/Makefile b/library/axi_hdmi_rx/Makefile
index ef6052d84..d2df089de 100644
--- a/library/axi_hdmi_rx/Makefile
+++ b/library/axi_hdmi_rx/Makefile
@@ -55,7 +55,7 @@ clean-all:
 
 
 axi_hdmi_rx.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_hdmi_rx_ip.tcl  >> axi_hdmi_rx_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_hdmi_tx/Makefile b/library/axi_hdmi_tx/Makefile
index 927014fa1..05ae19233 100644
--- a/library/axi_hdmi_tx/Makefile
+++ b/library/axi_hdmi_tx/Makefile
@@ -56,7 +56,7 @@ clean-all:
 
 
 axi_hdmi_tx.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_hdmi_tx_ip.tcl  >> axi_hdmi_tx_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_i2s_adi/Makefile b/library/axi_i2s_adi/Makefile
index 774b543fa..afe04c7fd 100644
--- a/library/axi_i2s_adi/Makefile
+++ b/library/axi_i2s_adi/Makefile
@@ -50,7 +50,7 @@ clean-all:
 
 
 axi_i2s_adi.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_i2s_adi_ip.tcl  >> axi_i2s_adi_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_jesd_gt/Makefile b/library/axi_jesd_gt/Makefile
index fd6220adc..4c3764e55 100644
--- a/library/axi_jesd_gt/Makefile
+++ b/library/axi_jesd_gt/Makefile
@@ -63,7 +63,7 @@ clean-all:
 
 
 axi_jesd_gt.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_jesd_gt_ip.tcl  >> axi_jesd_gt_ip.log 2>&1
 
 dep:
diff --git a/library/axi_mc_controller/Makefile b/library/axi_mc_controller/Makefile
index a63f1aefc..b024ae86c 100644
--- a/library/axi_mc_controller/Makefile
+++ b/library/axi_mc_controller/Makefile
@@ -52,7 +52,7 @@ clean-all:
 
 
 axi_mc_controller.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_mc_controller_ip.tcl  >> axi_mc_controller_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_mc_current_monitor/Makefile b/library/axi_mc_current_monitor/Makefile
index 711f9cffb..90aad4d97 100644
--- a/library/axi_mc_current_monitor/Makefile
+++ b/library/axi_mc_current_monitor/Makefile
@@ -50,7 +50,7 @@ clean-all:
 
 
 axi_mc_current_monitor.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_mc_current_monitor_ip.tcl  >> axi_mc_current_monitor_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_mc_speed/Makefile b/library/axi_mc_speed/Makefile
index f5b5fc941..8b0d8bf69 100644
--- a/library/axi_mc_speed/Makefile
+++ b/library/axi_mc_speed/Makefile
@@ -51,7 +51,7 @@ clean-all:
 
 
 axi_mc_speed.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_mc_speed_ip.tcl  >> axi_mc_speed_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_spdif_rx/Makefile b/library/axi_spdif_rx/Makefile
index 7b503cbd6..4f0a507df 100644
--- a/library/axi_spdif_rx/Makefile
+++ b/library/axi_spdif_rx/Makefile
@@ -48,7 +48,7 @@ clean-all:
 
 
 axi_spdif_rx.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_spdif_rx_ip.tcl  >> axi_spdif_rx_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_spdif_tx/Makefile b/library/axi_spdif_tx/Makefile
index d1415571a..8796f7dbd 100644
--- a/library/axi_spdif_tx/Makefile
+++ b/library/axi_spdif_tx/Makefile
@@ -46,7 +46,7 @@ clean-all:
 
 
 axi_spdif_tx.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_spdif_tx_ip.tcl  >> axi_spdif_tx_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/axi_usb_fx3/Makefile b/library/axi_usb_fx3/Makefile
index 2e981685b..762062712 100644
--- a/library/axi_usb_fx3/Makefile
+++ b/library/axi_usb_fx3/Makefile
@@ -43,7 +43,7 @@ clean-all:
 
 
 axi_usb_fx3.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_usb_fx3_ip.tcl  >> axi_usb_fx3_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/cn0363/cn0363_dma_sequencer/Makefile b/library/cn0363/cn0363_dma_sequencer/Makefile
index c1f55b1dc..8121ee0cc 100644
--- a/library/cn0363/cn0363_dma_sequencer/Makefile
+++ b/library/cn0363/cn0363_dma_sequencer/Makefile
@@ -39,7 +39,7 @@ clean-all:
 
 
 cn0363_dma_sequencer.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) cn0363_dma_sequencer_ip.tcl  >> cn0363_dma_sequencer_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/cn0363/cn0363_phase_data_sync/Makefile b/library/cn0363/cn0363_phase_data_sync/Makefile
index e9324860b..b6be55c46 100644
--- a/library/cn0363/cn0363_phase_data_sync/Makefile
+++ b/library/cn0363/cn0363_phase_data_sync/Makefile
@@ -39,7 +39,7 @@ clean-all:
 
 
 cn0363_phase_data_sync.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) cn0363_phase_data_sync_ip.tcl  >> cn0363_phase_data_sync_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/cordic_demod/Makefile b/library/cordic_demod/Makefile
index c0621be0e..91c755fa3 100644
--- a/library/cordic_demod/Makefile
+++ b/library/cordic_demod/Makefile
@@ -39,7 +39,7 @@ clean-all:
 
 
 cordic_demod.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) cordic_demod_ip.tcl  >> cordic_demod_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/spi_engine/axi_spi_engine/Makefile b/library/spi_engine/axi_spi_engine/Makefile
index f915b7cf9..74fe28da6 100644
--- a/library/spi_engine/axi_spi_engine/Makefile
+++ b/library/spi_engine/axi_spi_engine/Makefile
@@ -44,10 +44,10 @@ clean-all:
 
 
 axi_spi_engine.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_spi_engine_ip.tcl  >> axi_spi_engine_ip.log 2>&1
 
 dep:
-	make -C ../../util_axis_fifo
+	make -C ../../util_axis_fifo/
 ####################################################################################
 ####################################################################################
diff --git a/library/spi_engine/spi_engine_execution/Makefile b/library/spi_engine/spi_engine_execution/Makefile
index b85a13c81..9e717a20a 100644
--- a/library/spi_engine/spi_engine_execution/Makefile
+++ b/library/spi_engine/spi_engine_execution/Makefile
@@ -39,7 +39,7 @@ clean-all:
 
 
 spi_engine_execution.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) spi_engine_execution_ip.tcl  >> spi_engine_execution_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/spi_engine/spi_engine_interconnect/Makefile b/library/spi_engine/spi_engine_interconnect/Makefile
index 518188939..36d30eb7f 100644
--- a/library/spi_engine/spi_engine_interconnect/Makefile
+++ b/library/spi_engine/spi_engine_interconnect/Makefile
@@ -39,7 +39,7 @@ clean-all:
 
 
 spi_engine_interconnect.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) spi_engine_interconnect_ip.tcl  >> spi_engine_interconnect_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/spi_engine/spi_engine_offload/Makefile b/library/spi_engine/spi_engine_offload/Makefile
index 2a323646c..ebd78e156 100644
--- a/library/spi_engine/spi_engine_offload/Makefile
+++ b/library/spi_engine/spi_engine_offload/Makefile
@@ -40,7 +40,7 @@ clean-all:
 
 
 spi_engine_offload.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) spi_engine_offload_ip.tcl  >> spi_engine_offload_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_adcfifo/Makefile b/library/util_adcfifo/Makefile
index bbe345e35..24af6734e 100644
--- a/library/util_adcfifo/Makefile
+++ b/library/util_adcfifo/Makefile
@@ -42,7 +42,7 @@ clean-all:
 
 
 util_adcfifo.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_adcfifo_ip.tcl  >> util_adcfifo_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_axis_fifo/Makefile b/library/util_axis_fifo/Makefile
index f7c2168d3..6a0b72943 100644
--- a/library/util_axis_fifo/Makefile
+++ b/library/util_axis_fifo/Makefile
@@ -44,7 +44,7 @@ clean-all:
 
 
 util_axis_fifo.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_axis_fifo_ip.tcl  >> util_axis_fifo_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_axis_resize/Makefile b/library/util_axis_resize/Makefile
index bcb142830..9166b81b7 100644
--- a/library/util_axis_resize/Makefile
+++ b/library/util_axis_resize/Makefile
@@ -39,7 +39,7 @@ clean-all:
 
 
 util_axis_resize.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_axis_resize_ip.tcl  >> util_axis_resize_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_bsplit/Makefile b/library/util_bsplit/Makefile
index 7c81a5222..7ac60dd55 100644
--- a/library/util_bsplit/Makefile
+++ b/library/util_bsplit/Makefile
@@ -40,7 +40,7 @@ clean-all:
 
 
 util_bsplit.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_bsplit_ip.tcl  >> util_bsplit_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_ccat/Makefile b/library/util_ccat/Makefile
index 79ad826ed..65b7325cf 100644
--- a/library/util_ccat/Makefile
+++ b/library/util_ccat/Makefile
@@ -40,7 +40,7 @@ clean-all:
 
 
 util_ccat.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_ccat_ip.tcl  >> util_ccat_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_cpack/Makefile b/library/util_cpack/Makefile
index 2614cc2ff..f18473b98 100644
--- a/library/util_cpack/Makefile
+++ b/library/util_cpack/Makefile
@@ -42,7 +42,7 @@ clean-all:
 
 
 util_cpack.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_cpack_ip.tcl  >> util_cpack_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_dacfifo/Makefile b/library/util_dacfifo/Makefile
index a246111ff..9998c7c8c 100644
--- a/library/util_dacfifo/Makefile
+++ b/library/util_dacfifo/Makefile
@@ -41,7 +41,7 @@ clean-all:
 
 
 util_dacfifo.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_dacfifo_ip.tcl  >> util_dacfifo_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_gmii_to_rgmii/Makefile b/library/util_gmii_to_rgmii/Makefile
index 506c4f458..e162e3fa6 100644
--- a/library/util_gmii_to_rgmii/Makefile
+++ b/library/util_gmii_to_rgmii/Makefile
@@ -41,7 +41,7 @@ clean-all:
 
 
 util_gmii_to_rgmii.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_gmii_to_rgmii_ip.tcl  >> util_gmii_to_rgmii_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_gtlb/Makefile b/library/util_gtlb/Makefile
index 3b0bacb04..469e65bc1 100644
--- a/library/util_gtlb/Makefile
+++ b/library/util_gtlb/Makefile
@@ -49,7 +49,7 @@ clean-all:
 
 
 util_gtlb.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_gtlb_ip.tcl  >> util_gtlb_ip.log 2>&1
 
 dep:
diff --git a/library/util_i2c_mixer/Makefile b/library/util_i2c_mixer/Makefile
index ed7c3d74e..77651ba2e 100644
--- a/library/util_i2c_mixer/Makefile
+++ b/library/util_i2c_mixer/Makefile
@@ -39,7 +39,7 @@ clean-all:
 
 
 util_i2c_mixer.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_i2c_mixer_ip.tcl  >> util_i2c_mixer_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_jesd_gt/Makefile b/library/util_jesd_gt/Makefile
index 3835ca21c..07cb76d1d 100644
--- a/library/util_jesd_gt/Makefile
+++ b/library/util_jesd_gt/Makefile
@@ -47,7 +47,7 @@ clean-all:
 
 
 util_jesd_gt.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_jesd_gt_ip.tcl  >> util_jesd_gt_ip.log 2>&1
 
 dep:
diff --git a/library/util_mfifo/Makefile b/library/util_mfifo/Makefile
index 9dca6ebea..ced8923e6 100644
--- a/library/util_mfifo/Makefile
+++ b/library/util_mfifo/Makefile
@@ -40,7 +40,7 @@ clean-all:
 
 
 util_mfifo.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_mfifo_ip.tcl  >> util_mfifo_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_pmod_adc/Makefile b/library/util_pmod_adc/Makefile
index 52d72b1ea..b5650220f 100644
--- a/library/util_pmod_adc/Makefile
+++ b/library/util_pmod_adc/Makefile
@@ -40,7 +40,7 @@ clean-all:
 
 
 util_pmod_adc.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_pmod_adc_ip.tcl  >> util_pmod_adc_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_pmod_fmeter/Makefile b/library/util_pmod_fmeter/Makefile
index 25b76d41a..eabeba078 100644
--- a/library/util_pmod_fmeter/Makefile
+++ b/library/util_pmod_fmeter/Makefile
@@ -44,7 +44,7 @@ clean-all:
 
 
 util_pmod_fmeter.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_pmod_fmeter_ip.tcl  >> util_pmod_fmeter_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_rfifo/Makefile b/library/util_rfifo/Makefile
index 7483f8983..1ed8ab239 100644
--- a/library/util_rfifo/Makefile
+++ b/library/util_rfifo/Makefile
@@ -40,7 +40,7 @@ clean-all:
 
 
 util_rfifo.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_rfifo_ip.tcl  >> util_rfifo_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_sigma_delta_spi/Makefile b/library/util_sigma_delta_spi/Makefile
index e7a5a4263..2b29bbf71 100644
--- a/library/util_sigma_delta_spi/Makefile
+++ b/library/util_sigma_delta_spi/Makefile
@@ -39,7 +39,7 @@ clean-all:
 
 
 util_sigma_delta_spi.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_sigma_delta_spi_ip.tcl  >> util_sigma_delta_spi_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_tdd_sync/Makefile b/library/util_tdd_sync/Makefile
index 91e542b08..211ee2a99 100644
--- a/library/util_tdd_sync/Makefile
+++ b/library/util_tdd_sync/Makefile
@@ -40,7 +40,7 @@ clean-all:
 
 
 util_tdd_sync.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_tdd_sync_ip.tcl  >> util_tdd_sync_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_upack/Makefile b/library/util_upack/Makefile
index 48d0c3e8e..5a294b007 100644
--- a/library/util_upack/Makefile
+++ b/library/util_upack/Makefile
@@ -42,7 +42,7 @@ clean-all:
 
 
 util_upack.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_upack_ip.tcl  >> util_upack_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/util_wfifo/Makefile b/library/util_wfifo/Makefile
index 5e41155f0..3ba185305 100644
--- a/library/util_wfifo/Makefile
+++ b/library/util_wfifo/Makefile
@@ -40,7 +40,7 @@ clean-all:
 
 
 util_wfifo.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_wfifo_ip.tcl  >> util_wfifo_ip.log 2>&1
 
 ####################################################################################
diff --git a/library/xilinx/axi_adxcvr/Makefile b/library/xilinx/axi_adxcvr/Makefile
index 71ac0eda3..34d8a9662 100644
--- a/library/xilinx/axi_adxcvr/Makefile
+++ b/library/xilinx/axi_adxcvr/Makefile
@@ -48,7 +48,7 @@ clean-all:
 
 
 axi_adxcvr.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_adxcvr_ip.tcl  >> axi_adxcvr_ip.log 2>&1
 
 dep:
diff --git a/library/xilinx/util_adxcvr/Makefile b/library/xilinx/util_adxcvr/Makefile
index bd135b94f..22062b7b4 100644
--- a/library/xilinx/util_adxcvr/Makefile
+++ b/library/xilinx/util_adxcvr/Makefile
@@ -46,7 +46,7 @@ clean-all:
 
 
 util_adxcvr.xpr: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_adxcvr_ip.tcl  >> util_adxcvr_ip.log 2>&1
 
 dep:
diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile
index 5e0c9487c..616d1df47 100644
--- a/projects/ad6676evb/vc707/Makefile
+++ b/projects/ad6676evb/vc707/Makefile
@@ -37,6 +37,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -57,7 +58,7 @@ clean-all:clean
 
 
 ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad6676evb_vc707_vivado.log 2>&1
 
 
diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile
index b11811429..2320d034e 100644
--- a/projects/ad6676evb/zc706/Makefile
+++ b/projects/ad6676evb/zc706/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -62,7 +63,7 @@ clean-all:clean
 
 
 ad6676evb_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad6676evb_zc706_vivado.log 2>&1
 
 
diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile
index 539ba381d..8494dd0dd 100644
--- a/projects/ad7616_sdz/zc706/Makefile
+++ b/projects/ad7616_sdz/zc706/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -60,7 +61,7 @@ clean-all:clean
 
 
 ad7616_sdz_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad7616_sdz_zc706_vivado.log 2>&1
 
 
diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile
index 635cb90be..5bd037042 100644
--- a/projects/ad7616_sdz/zed/Makefile
+++ b/projects/ad7616_sdz/zed/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -64,7 +65,7 @@ clean-all:clean
 
 
 ad7616_sdz_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad7616_sdz_zed_vivado.log 2>&1
 
 
diff --git a/projects/ad7768evb/zed/Makefile b/projects/ad7768evb/zed/Makefile
index b14ce41b3..f84f18dfb 100644
--- a/projects/ad7768evb/zed/Makefile
+++ b/projects/ad7768evb/zed/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -59,7 +60,7 @@ clean-all:clean
 
 
 ad7768evb_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad7768evb_zed_vivado.log 2>&1
 
 
diff --git a/projects/ad9265_fmc/zc706/Makefile b/projects/ad9265_fmc/zc706/Makefile
index 9ad95e317..a6e129bf2 100644
--- a/projects/ad9265_fmc/zc706/Makefile
+++ b/projects/ad9265_fmc/zc706/Makefile
@@ -37,6 +37,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -57,7 +58,7 @@ clean-all:clean
 
 
 ad9265_fmc_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad9265_fmc_zc706_vivado.log 2>&1
 
 
diff --git a/projects/ad9434_fmc/zc706/Makefile b/projects/ad9434_fmc/zc706/Makefile
index 70d247f5c..134da3761 100644
--- a/projects/ad9434_fmc/zc706/Makefile
+++ b/projects/ad9434_fmc/zc706/Makefile
@@ -37,6 +37,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -57,7 +58,7 @@ clean-all:clean
 
 
 ad9434_fmc_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad9434_fmc_zc706_vivado.log 2>&1
 
 
diff --git a/projects/ad9467_fmc/kc705/Makefile b/projects/ad9467_fmc/kc705/Makefile
index 887838189..3d35cdf62 100644
--- a/projects/ad9467_fmc/kc705/Makefile
+++ b/projects/ad9467_fmc/kc705/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -52,7 +53,7 @@ clean-all:clean
 
 
 ad9467_fmc_kc705.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad9467_fmc_kc705_vivado.log 2>&1
 
 
diff --git a/projects/ad9467_fmc/zed/Makefile b/projects/ad9467_fmc/zed/Makefile
index 0eee2b11c..b7166bd48 100644
--- a/projects/ad9467_fmc/zed/Makefile
+++ b/projects/ad9467_fmc/zed/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -61,7 +62,7 @@ clean-all:clean
 
 
 ad9467_fmc_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad9467_fmc_zed_vivado.log 2>&1
 
 
diff --git a/projects/ad9739a_fmc/zc706/Makefile b/projects/ad9739a_fmc/zc706/Makefile
index 481327975..22fabd30a 100644
--- a/projects/ad9739a_fmc/zc706/Makefile
+++ b/projects/ad9739a_fmc/zc706/Makefile
@@ -36,6 +36,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -56,7 +57,7 @@ clean-all:clean
 
 
 ad9739a_fmc_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ad9739a_fmc_zc706_vivado.log 2>&1
 
 
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index e3a6e61e3..652c17457 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -127,7 +127,7 @@ clean-all:
 
 
 adrv9371x_a10soc.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> adrv9371x_a10soc_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
index 933be8e1c..75c8ccb71 100644
--- a/projects/adrv9371x/zc706/Makefile
+++ b/projects/adrv9371x/zc706/Makefile
@@ -48,6 +48,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -76,7 +77,7 @@ clean-all:clean
 
 
 adrv9371x_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adrv9371x_zc706_vivado.log 2>&1
 
 
diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile
index 0dfca3289..3e7747eed 100644
--- a/projects/adv7511/ac701/Makefile
+++ b/projects/adv7511/ac701/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -53,7 +54,7 @@ clean-all:clean
 
 
 adv7511_ac701.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adv7511_ac701_vivado.log 2>&1
 
 
diff --git a/projects/adv7511/kc705/Makefile b/projects/adv7511/kc705/Makefile
index 69dea3d47..9f1e38602 100644
--- a/projects/adv7511/kc705/Makefile
+++ b/projects/adv7511/kc705/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -53,7 +54,7 @@ clean-all:clean
 
 
 adv7511_kc705.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adv7511_kc705_vivado.log 2>&1
 
 
diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile
index 9a09b9f4f..a8f1a08fe 100644
--- a/projects/adv7511/kcu105/Makefile
+++ b/projects/adv7511/kcu105/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -53,7 +54,7 @@ clean-all:clean
 
 
 adv7511_kcu105.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adv7511_kcu105_vivado.log 2>&1
 
 
diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile
index 80c65e379..1701121f8 100644
--- a/projects/adv7511/mitx045/Makefile
+++ b/projects/adv7511/mitx045/Makefile
@@ -34,6 +34,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -53,7 +54,7 @@ clean-all:clean
 
 
 adv7511_mitx045.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adv7511_mitx045_vivado.log 2>&1
 
 
diff --git a/projects/adv7511/vc707/Makefile b/projects/adv7511/vc707/Makefile
index b347dcd33..f809d5bd5 100644
--- a/projects/adv7511/vc707/Makefile
+++ b/projects/adv7511/vc707/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -53,7 +54,7 @@ clean-all:clean
 
 
 adv7511_vc707.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adv7511_vc707_vivado.log 2>&1
 
 
diff --git a/projects/adv7511/zc702/Makefile b/projects/adv7511/zc702/Makefile
index 876158ecd..961410265 100644
--- a/projects/adv7511/zc702/Makefile
+++ b/projects/adv7511/zc702/Makefile
@@ -32,6 +32,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -50,7 +51,7 @@ clean-all:clean
 
 
 adv7511_zc702.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adv7511_zc702_vivado.log 2>&1
 
 
diff --git a/projects/adv7511/zc706/Makefile b/projects/adv7511/zc706/Makefile
index d00baa5e9..1ff02713a 100644
--- a/projects/adv7511/zc706/Makefile
+++ b/projects/adv7511/zc706/Makefile
@@ -32,6 +32,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -50,7 +51,7 @@ clean-all:clean
 
 
 adv7511_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adv7511_zc706_vivado.log 2>&1
 
 
diff --git a/projects/adv7511/zed/Makefile b/projects/adv7511/zed/Makefile
index 26d233c0b..e263f326a 100644
--- a/projects/adv7511/zed/Makefile
+++ b/projects/adv7511/zed/Makefile
@@ -34,6 +34,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -54,7 +55,7 @@ clean-all:clean
 
 
 adv7511_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> adv7511_zed_vivado.log 2>&1
 
 
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 3275b8b8b..ea68e588a 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -143,7 +143,7 @@ clean-all:
 
 
 arradio_c5soc.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> arradio_c5soc_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/cftl_cip/zed/Makefile b/projects/cftl_cip/zed/Makefile
index 687b6a0e0..686ba8caf 100644
--- a/projects/cftl_cip/zed/Makefile
+++ b/projects/cftl_cip/zed/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -62,7 +63,7 @@ clean-all:clean
 
 
 cftl_custom_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> cftl_custom_zed_vivado.log 2>&1
 
 
diff --git a/projects/cftl_std/zed/Makefile b/projects/cftl_std/zed/Makefile
index 55923a3eb..fd12ba5b0 100644
--- a/projects/cftl_std/zed/Makefile
+++ b/projects/cftl_std/zed/Makefile
@@ -36,6 +36,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -56,7 +57,7 @@ clean-all:clean
 
 
 cftl_std_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> cftl_std_zed_vivado.log 2>&1
 
 
diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile
index 81bbb9aff..fd152e0c1 100644
--- a/projects/cn0363/microzed/Makefile
+++ b/projects/cn0363/microzed/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -69,7 +70,7 @@ clean-all:clean
 
 
 cn0363_microzed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> cn0363_microzed_vivado.log 2>&1
 
 
diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile
index e5a811c0c..da541a22e 100644
--- a/projects/cn0363/zed/Makefile
+++ b/projects/cn0363/zed/Makefile
@@ -47,6 +47,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -78,7 +79,7 @@ clean-all:clean
 
 
 cn0363_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> cn0363_zed_vivado.log 2>&1
 
 
diff --git a/projects/common/a5gte/Makefile b/projects/common/a5gte/Makefile
index c15cb453a..b0e931ef0 100644
--- a/projects/common/a5gte/Makefile
+++ b/projects/common/a5gte/Makefile
@@ -59,7 +59,7 @@ clean-all:
 
 
 a5gte.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> a5gte_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile
index f17d14899..01ea63b33 100644
--- a/projects/daq1/zc706/Makefile
+++ b/projects/daq1/zc706/Makefile
@@ -44,6 +44,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -68,7 +69,7 @@ clean-all:clean
 
 
 daq1_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> daq1_zc706_vivado.log 2>&1
 
 
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index a7ea3bfcc..70076698f 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -135,7 +135,7 @@ clean-all:
 
 
 daq2_a10gx.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> daq2_a10gx_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile
index 728e1bcbf..f5d9acfd7 100644
--- a/projects/daq2/kc705/Makefile
+++ b/projects/daq2/kc705/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -67,7 +68,7 @@ clean-all:clean
 
 
 daq2_kc705.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> daq2_kc705_vivado.log 2>&1
 
 
diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile
index 7ceb9267d..247fbb27e 100644
--- a/projects/daq2/kcu105/Makefile
+++ b/projects/daq2/kcu105/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -67,7 +68,7 @@ clean-all:clean
 
 
 daq2_kcu105.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> daq2_kcu105_vivado.log 2>&1
 
 
diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile
index ca4997397..9b070ccc0 100644
--- a/projects/daq2/vc707/Makefile
+++ b/projects/daq2/vc707/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -67,7 +68,7 @@ clean-all:clean
 
 
 daq2_vc707.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> daq2_vc707_vivado.log 2>&1
 
 
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index ee79c64bc..380f4ea33 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -49,6 +49,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -77,7 +78,7 @@ clean-all:clean
 
 
 daq2_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> daq2_zc706_vivado.log 2>&1
 
 
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index bf93b791b..92492ad75 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -134,7 +134,7 @@ clean-all:
 
 
 daq3_a10gx.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> daq3_a10gx_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
index 256432946..568d3f2bc 100644
--- a/projects/daq3/kcu105/Makefile
+++ b/projects/daq3/kcu105/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -67,7 +68,7 @@ clean-all:clean
 
 
 daq3_kcu105.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> daq3_kcu105_vivado.log 2>&1
 
 
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index a591c3306..60655c5ef 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -50,6 +50,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -79,7 +80,7 @@ clean-all:clean
 
 
 daq3_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> daq3_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index 3ae995270..1215e2339 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -61,7 +62,7 @@ clean-all:clean
 
 
 fmcadc2_vc707.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcadc2_vc707_vivado.log 2>&1
 
 
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 7a83de7f5..f207d5a77 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -66,7 +67,7 @@ clean-all:clean
 
 
 fmcadc2_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcadc2_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index b4f4379f4..6086e7713 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -46,6 +46,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -72,7 +73,7 @@ clean-all:clean
 
 
 fmcadc4_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcadc4_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile
index 38905f714..421ca7519 100644
--- a/projects/fmcadc5/vc707/Makefile
+++ b/projects/fmcadc5/vc707/Makefile
@@ -44,6 +44,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -67,7 +68,7 @@ clean-all:clean
 
 
 fmcadc5_vc707.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcadc5_vc707_vivado.log 2>&1
 
 
diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index 7f0b6b3b3..ea00e8e03 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -116,7 +116,7 @@ clean-all:
 
 
 fmcjesdadc1_a5gt.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> fmcjesdadc1_a5gt_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 9399511e1..3a6dc113c 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -116,7 +116,7 @@ clean-all:
 
 
 fmcjesdadc1_a5soc.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> fmcjesdadc1_a5soc_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile
index 7050c879e..84e0f1d60 100644
--- a/projects/fmcjesdadc1/kc705/Makefile
+++ b/projects/fmcjesdadc1/kc705/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -60,7 +61,7 @@ clean-all:clean
 
 
 fmcjesdadc1_kc705.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcjesdadc1_kc705_vivado.log 2>&1
 
 
diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile
index 379caa28b..74b65b5ae 100644
--- a/projects/fmcjesdadc1/vc707/Makefile
+++ b/projects/fmcjesdadc1/vc707/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -60,7 +61,7 @@ clean-all:clean
 
 
 fmcjesdadc1_vc707.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcjesdadc1_vc707_vivado.log 2>&1
 
 
diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile
index e3c623304..030f961f0 100644
--- a/projects/fmcjesdadc1/zc706/Makefile
+++ b/projects/fmcjesdadc1/zc706/Makefile
@@ -41,6 +41,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -65,7 +66,7 @@ clean-all:clean
 
 
 fmcjesdadc1_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcjesdadc1_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms1/ac701/Makefile
index 9c8a6771c..052111b9d 100644
--- a/projects/fmcomms1/ac701/Makefile
+++ b/projects/fmcomms1/ac701/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -59,7 +60,7 @@ clean-all:clean
 
 
 fmcomms1_ac701.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms1_ac701_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms1/kc705/Makefile b/projects/fmcomms1/kc705/Makefile
index 5d00e2573..995135825 100644
--- a/projects/fmcomms1/kc705/Makefile
+++ b/projects/fmcomms1/kc705/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -59,7 +60,7 @@ clean-all:clean
 
 
 fmcomms1_kc705.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms1_kc705_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms1/vc707/Makefile b/projects/fmcomms1/vc707/Makefile
index 8b7b14948..f86716289 100644
--- a/projects/fmcomms1/vc707/Makefile
+++ b/projects/fmcomms1/vc707/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -59,7 +60,7 @@ clean-all:clean
 
 
 fmcomms1_vc707.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms1_vc707_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms1/zc702/Makefile b/projects/fmcomms1/zc702/Makefile
index c5faab08a..a1bfa3a34 100644
--- a/projects/fmcomms1/zc702/Makefile
+++ b/projects/fmcomms1/zc702/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -64,7 +65,7 @@ clean-all:clean
 
 
 fmcomms1_zc702.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms1_zc702_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms1/zc706/Makefile b/projects/fmcomms1/zc706/Makefile
index 5170046cd..2fed37f66 100644
--- a/projects/fmcomms1/zc706/Makefile
+++ b/projects/fmcomms1/zc706/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -64,7 +65,7 @@ clean-all:clean
 
 
 fmcomms1_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms1_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms1/zed/Makefile b/projects/fmcomms1/zed/Makefile
index 79e54721f..a5233c373 100644
--- a/projects/fmcomms1/zed/Makefile
+++ b/projects/fmcomms1/zed/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -68,7 +69,7 @@ clean-all:clean
 
 
 fmcomms1_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms1_zed_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index 72b3b1c6b..b747e7202 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -47,6 +47,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -73,7 +74,7 @@ clean-all:clean
 
 
 fmcomms11_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms11_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index df6dcfd61..2ee4d6487 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -140,7 +140,7 @@ clean-all:
 
 
 fmcomms2_a10gx.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> fmcomms2_a10gx_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile
index 03282725e..66954d699 100644
--- a/projects/fmcomms2/ac701/Makefile
+++ b/projects/fmcomms2/ac701/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -60,7 +61,7 @@ clean-all:clean
 
 
 fmcomms2_ac701.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms2_ac701_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile
index ab24ca35e..d7db6fb18 100644
--- a/projects/fmcomms2/kc705/Makefile
+++ b/projects/fmcomms2/kc705/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -60,7 +61,7 @@ clean-all:clean
 
 
 fmcomms2_kc705.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms2_kc705_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile
index ca53855ce..34c32cfeb 100644
--- a/projects/fmcomms2/mitx045/Makefile
+++ b/projects/fmcomms2/mitx045/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -68,7 +69,7 @@ clean-all:clean
 
 
 fmcomms2_mitx045.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms2_mitx045_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile
index 46327e71d..1089a7b28 100644
--- a/projects/fmcomms2/vc707/Makefile
+++ b/projects/fmcomms2/vc707/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -59,7 +60,7 @@ clean-all:clean
 
 
 fmcomms2_vc707.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms2_vc707_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile
index 439cfe22c..f5064b9e0 100644
--- a/projects/fmcomms2/zc702/Makefile
+++ b/projects/fmcomms2/zc702/Makefile
@@ -41,6 +41,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -65,7 +66,7 @@ clean-all:clean
 
 
 fmcomms2_zc702.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms2_zc702_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile
index d3c52de44..99f47d740 100644
--- a/projects/fmcomms2/zc706/Makefile
+++ b/projects/fmcomms2/zc706/Makefile
@@ -40,6 +40,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -64,7 +65,7 @@ clean-all:clean
 
 
 fmcomms2_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms2_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms2/zcu102/Makefile b/projects/fmcomms2/zcu102/Makefile
index 3418eb35a..ec72c72ec 100644
--- a/projects/fmcomms2/zcu102/Makefile
+++ b/projects/fmcomms2/zcu102/Makefile
@@ -37,6 +37,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -58,7 +59,7 @@ clean-all:clean
 
 
 fmcomms2_zcu102.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms2_zcu102_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile
index 9fd8dcfc5..ee553a9ac 100644
--- a/projects/fmcomms2/zed/Makefile
+++ b/projects/fmcomms2/zed/Makefile
@@ -43,6 +43,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -69,7 +70,7 @@ clean-all:clean
 
 
 fmcomms2_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms2_zed_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile
index bba74f74a..98e7a633e 100644
--- a/projects/fmcomms5/zc702/Makefile
+++ b/projects/fmcomms5/zc702/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -62,7 +63,7 @@ clean-all:clean
 
 
 fmcomms5_zc702.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms5_zc702_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile
index 5aee574f5..2645c832b 100644
--- a/projects/fmcomms5/zc706/Makefile
+++ b/projects/fmcomms5/zc706/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -62,7 +63,7 @@ clean-all:clean
 
 
 fmcomms5_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms5_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms6/zc706/Makefile b/projects/fmcomms6/zc706/Makefile
index 3846e87f0..b1292bc9f 100644
--- a/projects/fmcomms6/zc706/Makefile
+++ b/projects/fmcomms6/zc706/Makefile
@@ -39,6 +39,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -61,7 +62,7 @@ clean-all:clean
 
 
 fmcomms6_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms6_zc706_vivado.log 2>&1
 
 
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index 3f42f718c..c0df5c1da 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -49,6 +49,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -77,7 +78,7 @@ clean-all:clean
 
 
 fmcomms7_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> fmcomms7_zc706_vivado.log 2>&1
 
 
diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile
index bf8076634..da98488cb 100644
--- a/projects/imageon/zc706/Makefile
+++ b/projects/imageon/zc706/Makefile
@@ -36,6 +36,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -57,7 +58,7 @@ clean-all:clean
 
 
 imageon_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> imageon_zc706_vivado.log 2>&1
 
 
diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile
index bf3a40c13..f7011b01a 100644
--- a/projects/imageon/zed/Makefile
+++ b/projects/imageon/zed/Makefile
@@ -38,6 +38,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -61,7 +62,7 @@ clean-all:clean
 
 
 imageon_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> imageon_zed_vivado.log 2>&1
 
 
diff --git a/projects/motcon2_fmc/zed/Makefile b/projects/motcon2_fmc/zed/Makefile
index e214e56d0..d4d26249b 100644
--- a/projects/motcon2_fmc/zed/Makefile
+++ b/projects/motcon2_fmc/zed/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -68,7 +69,7 @@ clean-all:clean
 
 
 motcon2_fmc_zed.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> motcon2_fmc_zed_vivado.log 2>&1
 
 
diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile
index c9b8d0aa0..38dd273a7 100644
--- a/projects/pzsdr/ccbrk/Makefile
+++ b/projects/pzsdr/ccbrk/Makefile
@@ -44,6 +44,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -68,7 +69,7 @@ clean-all:clean
 
 
 ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1
 
 
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
index bc6539695..ca329962d 100644
--- a/projects/pzsdr/ccbrk_cmos/Makefile
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -44,6 +44,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -68,7 +69,7 @@ clean-all:clean
 
 
 ccbrk_cmos_pzsdr.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ccbrk_cmos_pzsdr_vivado.log 2>&1
 
 
diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile
index 643a619e6..c11c3c679 100644
--- a/projects/pzsdr/ccfmc/Makefile
+++ b/projects/pzsdr/ccfmc/Makefile
@@ -48,6 +48,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -76,7 +77,7 @@ clean-all:clean
 
 
 ccfmc_pzsdr.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ccfmc_pzsdr_vivado.log 2>&1
 
 
diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci/Makefile
index 08fce8aaf..e726fe70f 100644
--- a/projects/pzsdr/ccpci/Makefile
+++ b/projects/pzsdr/ccpci/Makefile
@@ -41,6 +41,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -62,7 +63,7 @@ clean-all:clean
 
 
 ccpci_pzsdr.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ccpci_pzsdr_vivado.log 2>&1
 
 
diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
index 8c9589b67..dc5a34c56 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -64,7 +65,7 @@ clean-all:clean
 
 
 ccbrk_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr1_vivado.log 2>&1
 
 
diff --git a/projects/pzsdr1/ccbrk_cmos/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile
index 033e96bfd..faa2e256a 100644
--- a/projects/pzsdr1/ccbrk_cmos/Makefile
+++ b/projects/pzsdr1/ccbrk_cmos/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -64,7 +65,7 @@ clean-all:clean
 
 
 ccbrk_cmos_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> ccbrk_cmos_pzsdr1_vivado.log 2>&1
 
 
diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile
index eb786cf55..84b91e988 100644
--- a/projects/usb_fx3/zc706/Makefile
+++ b/projects/usb_fx3/zc706/Makefile
@@ -35,6 +35,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -54,7 +55,7 @@ clean-all:clean
 
 
 usb_fx3_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> usb_fx3_zc706_vivado.log 2>&1
 
 
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index 53d4949eb..301866b75 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -62,7 +62,7 @@ clean-all:
 
 
 usdrx1_a5gt.sof: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> usdrx1_a5gt_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index 1add6ecb0..cb594bbe8 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -42,6 +42,7 @@ M_FLIST += *.sdk
 M_FLIST += *.hw
 M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
@@ -65,7 +66,7 @@ clean-all:clean
 
 
 usdrx1_zc706.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
+	-rm -rf $(M_FLIST)
 	$(M_VIVADO) system_project.tcl >> usdrx1_zc706_vivado.log 2>&1
 
 

From 5faf4c4976b179444c139260e32acb0b9acf8998 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 5 Aug 2016 16:27:52 +0300
Subject: [PATCH 372/972] cleanup: Don't need Makefiles specific to
 xilinx/altera libraries. Top Makefile covers them

---
 library/altera/Makefile | 151 ----------------------------------------
 library/xilinx/Makefile | 151 ----------------------------------------
 2 files changed, 302 deletions(-)
 delete mode 100644 library/altera/Makefile
 delete mode 100644 library/xilinx/Makefile

diff --git a/library/altera/Makefile b/library/altera/Makefile
deleted file mode 100644
index 1b40b5171..000000000
--- a/library/altera/Makefile
+++ /dev/null
@@ -1,151 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-.PHONY: all lib clean clean-all
-all: lib
-
-
-clean:
-	make -C axi_ad6676 clean
-	make -C axi_ad7616 clean
-	make -C axi_ad9122 clean
-	make -C axi_ad9144 clean
-	make -C axi_ad9152 clean
-	make -C axi_ad9162 clean
-	make -C axi_ad9234 clean
-	make -C axi_ad9250 clean
-	make -C axi_ad9265 clean
-	make -C axi_ad9361 clean
-	make -C axi_ad9371 clean
-	make -C axi_ad9434 clean
-	make -C axi_ad9467 clean
-	make -C axi_ad9625 clean
-	make -C axi_ad9643 clean
-	make -C axi_ad9652 clean
-	make -C axi_ad9671 clean
-	make -C axi_ad9680 clean
-	make -C axi_ad9684 clean
-	make -C axi_ad9739a clean
-	make -C axi_adcfifo clean
-	make -C axi_adxcvr clean
-	make -C axi_clkgen clean
-	make -C axi_dacfifo clean
-	make -C axi_dmac clean
-	make -C axi_generic_adc clean
-	make -C axi_gpreg clean
-	make -C axi_hdmi_rx clean
-	make -C axi_hdmi_tx clean
-	make -C axi_i2s_adi clean
-	make -C axi_jesd_gt clean
-	make -C axi_mc_controller clean
-	make -C axi_mc_current_monitor clean
-	make -C axi_mc_speed clean
-	make -C axi_spdif_rx clean
-	make -C axi_spdif_tx clean
-	make -C axi_usb_fx3 clean
-	make -C cn0363/cn0363_dma_sequencer clean
-	make -C cn0363/cn0363_phase_data_sync clean
-	make -C cordic_demod clean
-	make -C interfaces clean
-	make -C spi_engine/axi_spi_engine clean
-	make -C spi_engine/spi_engine_execution clean
-	make -C spi_engine/spi_engine_interconnect clean
-	make -C spi_engine/spi_engine_offload clean
-	make -C util_adcfifo clean
-	make -C util_adxcvr clean
-	make -C util_axis_fifo clean
-	make -C util_axis_resize clean
-	make -C util_bsplit clean
-	make -C util_ccat clean
-	make -C util_cpack clean
-	make -C util_dacfifo clean
-	make -C util_gmii_to_rgmii clean
-	make -C util_gtlb clean
-	make -C util_i2c_mixer clean
-	make -C util_jesd_gt clean
-	make -C util_mfifo clean
-	make -C util_pmod_adc clean
-	make -C util_pmod_fmeter clean
-	make -C util_rfifo clean
-	make -C util_sigma_delta_spi clean
-	make -C util_tdd_sync clean
-	make -C util_upack clean
-	make -C util_wfifo clean
-
-
-clean-all:clean
-
-
-lib:
-	-make -C axi_ad6676
-	-make -C axi_ad7616
-	-make -C axi_ad9122
-	-make -C axi_ad9144
-	-make -C axi_ad9152
-	-make -C axi_ad9162
-	-make -C axi_ad9234
-	-make -C axi_ad9250
-	-make -C axi_ad9265
-	-make -C axi_ad9361
-	-make -C axi_ad9371
-	-make -C axi_ad9434
-	-make -C axi_ad9467
-	-make -C axi_ad9625
-	-make -C axi_ad9643
-	-make -C axi_ad9652
-	-make -C axi_ad9671
-	-make -C axi_ad9680
-	-make -C axi_ad9684
-	-make -C axi_ad9739a
-	-make -C axi_adcfifo
-	-make -C axi_adxcvr
-	-make -C axi_clkgen
-	-make -C axi_dacfifo
-	-make -C axi_dmac
-	-make -C axi_generic_adc
-	-make -C axi_gpreg
-	-make -C axi_hdmi_rx
-	-make -C axi_hdmi_tx
-	-make -C axi_i2s_adi
-	-make -C axi_jesd_gt
-	-make -C axi_mc_controller
-	-make -C axi_mc_current_monitor
-	-make -C axi_mc_speed
-	-make -C axi_spdif_rx
-	-make -C axi_spdif_tx
-	-make -C axi_usb_fx3
-	-make -C cn0363/cn0363_dma_sequencer
-	-make -C cn0363/cn0363_phase_data_sync
-	-make -C cordic_demod
-	-make -C interfaces
-	-make -C spi_engine/axi_spi_engine
-	-make -C spi_engine/spi_engine_execution
-	-make -C spi_engine/spi_engine_interconnect
-	-make -C spi_engine/spi_engine_offload
-	-make -C util_adcfifo
-	-make -C util_adxcvr
-	-make -C util_axis_fifo
-	-make -C util_axis_resize
-	-make -C util_bsplit
-	-make -C util_ccat
-	-make -C util_cpack
-	-make -C util_dacfifo
-	-make -C util_gmii_to_rgmii
-	-make -C util_gtlb
-	-make -C util_i2c_mixer
-	-make -C util_jesd_gt
-	-make -C util_mfifo
-	-make -C util_pmod_adc
-	-make -C util_pmod_fmeter
-	-make -C util_rfifo
-	-make -C util_sigma_delta_spi
-	-make -C util_tdd_sync
-	-make -C util_upack
-	-make -C util_wfifo
-
-####################################################################################
-####################################################################################
diff --git a/library/xilinx/Makefile b/library/xilinx/Makefile
deleted file mode 100644
index 1b40b5171..000000000
--- a/library/xilinx/Makefile
+++ /dev/null
@@ -1,151 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-.PHONY: all lib clean clean-all
-all: lib
-
-
-clean:
-	make -C axi_ad6676 clean
-	make -C axi_ad7616 clean
-	make -C axi_ad9122 clean
-	make -C axi_ad9144 clean
-	make -C axi_ad9152 clean
-	make -C axi_ad9162 clean
-	make -C axi_ad9234 clean
-	make -C axi_ad9250 clean
-	make -C axi_ad9265 clean
-	make -C axi_ad9361 clean
-	make -C axi_ad9371 clean
-	make -C axi_ad9434 clean
-	make -C axi_ad9467 clean
-	make -C axi_ad9625 clean
-	make -C axi_ad9643 clean
-	make -C axi_ad9652 clean
-	make -C axi_ad9671 clean
-	make -C axi_ad9680 clean
-	make -C axi_ad9684 clean
-	make -C axi_ad9739a clean
-	make -C axi_adcfifo clean
-	make -C axi_adxcvr clean
-	make -C axi_clkgen clean
-	make -C axi_dacfifo clean
-	make -C axi_dmac clean
-	make -C axi_generic_adc clean
-	make -C axi_gpreg clean
-	make -C axi_hdmi_rx clean
-	make -C axi_hdmi_tx clean
-	make -C axi_i2s_adi clean
-	make -C axi_jesd_gt clean
-	make -C axi_mc_controller clean
-	make -C axi_mc_current_monitor clean
-	make -C axi_mc_speed clean
-	make -C axi_spdif_rx clean
-	make -C axi_spdif_tx clean
-	make -C axi_usb_fx3 clean
-	make -C cn0363/cn0363_dma_sequencer clean
-	make -C cn0363/cn0363_phase_data_sync clean
-	make -C cordic_demod clean
-	make -C interfaces clean
-	make -C spi_engine/axi_spi_engine clean
-	make -C spi_engine/spi_engine_execution clean
-	make -C spi_engine/spi_engine_interconnect clean
-	make -C spi_engine/spi_engine_offload clean
-	make -C util_adcfifo clean
-	make -C util_adxcvr clean
-	make -C util_axis_fifo clean
-	make -C util_axis_resize clean
-	make -C util_bsplit clean
-	make -C util_ccat clean
-	make -C util_cpack clean
-	make -C util_dacfifo clean
-	make -C util_gmii_to_rgmii clean
-	make -C util_gtlb clean
-	make -C util_i2c_mixer clean
-	make -C util_jesd_gt clean
-	make -C util_mfifo clean
-	make -C util_pmod_adc clean
-	make -C util_pmod_fmeter clean
-	make -C util_rfifo clean
-	make -C util_sigma_delta_spi clean
-	make -C util_tdd_sync clean
-	make -C util_upack clean
-	make -C util_wfifo clean
-
-
-clean-all:clean
-
-
-lib:
-	-make -C axi_ad6676
-	-make -C axi_ad7616
-	-make -C axi_ad9122
-	-make -C axi_ad9144
-	-make -C axi_ad9152
-	-make -C axi_ad9162
-	-make -C axi_ad9234
-	-make -C axi_ad9250
-	-make -C axi_ad9265
-	-make -C axi_ad9361
-	-make -C axi_ad9371
-	-make -C axi_ad9434
-	-make -C axi_ad9467
-	-make -C axi_ad9625
-	-make -C axi_ad9643
-	-make -C axi_ad9652
-	-make -C axi_ad9671
-	-make -C axi_ad9680
-	-make -C axi_ad9684
-	-make -C axi_ad9739a
-	-make -C axi_adcfifo
-	-make -C axi_adxcvr
-	-make -C axi_clkgen
-	-make -C axi_dacfifo
-	-make -C axi_dmac
-	-make -C axi_generic_adc
-	-make -C axi_gpreg
-	-make -C axi_hdmi_rx
-	-make -C axi_hdmi_tx
-	-make -C axi_i2s_adi
-	-make -C axi_jesd_gt
-	-make -C axi_mc_controller
-	-make -C axi_mc_current_monitor
-	-make -C axi_mc_speed
-	-make -C axi_spdif_rx
-	-make -C axi_spdif_tx
-	-make -C axi_usb_fx3
-	-make -C cn0363/cn0363_dma_sequencer
-	-make -C cn0363/cn0363_phase_data_sync
-	-make -C cordic_demod
-	-make -C interfaces
-	-make -C spi_engine/axi_spi_engine
-	-make -C spi_engine/spi_engine_execution
-	-make -C spi_engine/spi_engine_interconnect
-	-make -C spi_engine/spi_engine_offload
-	-make -C util_adcfifo
-	-make -C util_adxcvr
-	-make -C util_axis_fifo
-	-make -C util_axis_resize
-	-make -C util_bsplit
-	-make -C util_ccat
-	-make -C util_cpack
-	-make -C util_dacfifo
-	-make -C util_gmii_to_rgmii
-	-make -C util_gtlb
-	-make -C util_i2c_mixer
-	-make -C util_jesd_gt
-	-make -C util_mfifo
-	-make -C util_pmod_adc
-	-make -C util_pmod_fmeter
-	-make -C util_rfifo
-	-make -C util_sigma_delta_spi
-	-make -C util_tdd_sync
-	-make -C util_upack
-	-make -C util_wfifo
-
-####################################################################################
-####################################################################################

From 3cff0fa7dca57b6c3ce1cd42a857ef6fe912ff67 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Thu, 14 Jul 2016 10:33:01 +0200
Subject: [PATCH 373/972] pzsdr: ccpci: Use PL SPI and GPIO peripherals

To be able to access the GPIO pins and the SPI port through the PCIe bridge
we need to use the PL SPI and GPIO controllers rather than the PS
controllers. Adjust the sytem_top.v accordingly so that the PL peripherals
are connected to the external pins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/pzsdr/ccpci/system_top.v | 32 +++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/projects/pzsdr/ccpci/system_top.v b/projects/pzsdr/ccpci/system_top.v
index 84eaa8f7d..835a89372 100644
--- a/projects/pzsdr/ccpci/system_top.v
+++ b/projects/pzsdr/ccpci/system_top.v
@@ -178,9 +178,12 @@ module system_top (
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
+  wire    [63:0]  gpio_ps_i;
+
   // assignments
 
   assign pcie_waken = 1'bz;
+  assign gpio_ps_i[63:0] = 'h00;
 
   // instantiations
 
@@ -231,9 +234,9 @@ module system_top (
     .fixed_io_ps_clk (fixed_io_ps_clk),
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gpio_i (gpio_i),
-    .gpio_o (gpio_o),
-    .gpio_t (gpio_t),
+    .gpio_i (gpio_ps_i),
+    .gpio_o (),
+    .gpio_t (),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
@@ -263,14 +266,14 @@ module system_top (
     .rx_frame_in_n (rx_frame_in_n),
     .rx_frame_in_p (rx_frame_in_p),
     .spi0_clk_i (1'b0),
-    .spi0_clk_o (spi_clk),
-    .spi0_csn_0_o (spi_csn),
+    .spi0_clk_o (),
+    .spi0_csn_0_o (),
     .spi0_csn_1_o (),
     .spi0_csn_2_o (),
     .spi0_csn_i (1'b1),
-    .spi0_sdi_i (spi_miso),
+    .spi0_sdi_i (1'b0),
     .spi0_sdo_i (1'b0),
-    .spi0_sdo_o (spi_mosi),
+    .spi0_sdo_o (),
     .spi1_clk_i (1'b0),
     .spi1_clk_o (),
     .spi1_csn_0_o (),
@@ -291,7 +294,20 @@ module system_top (
     .tx_frame_out_p (tx_frame_out_p),
     .txnrx (txnrx),
     .up_enable (gpio_o[47]),
-    .up_txnrx (gpio_o[48]));
+    .up_txnrx (gpio_o[48]),
+    .pl_spi_clk_o(spi_clk),
+    .pl_spi_clk_i(spi_clk),
+    .pl_spi_sdo_o(spi_mosi),
+    .pl_spi_sdo_i(spi_mosi),
+    .pl_spi_sdi_i(spi_miso),
+    .pl_spi_csn_o(spi_csn),
+    .pl_spi_csn_i(spi_csn),
+    .pl_gpio0_o(gpio_o[31:0]),
+    .pl_gpio0_t(gpio_t[31:0]),
+    .pl_gpio0_i(gpio_i[31:0]),
+    .pl_gpio1_o(gpio_o[63:32]),
+    .pl_gpio1_t(gpio_t[63:32]),
+    .pl_gpio1_i(gpio_i[63:32]));
 
 endmodule
 

From 418217dd109530896a70fcf14f8603b37e6886c6 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Thu, 14 Jul 2016 17:09:20 +0200
Subject: [PATCH 374/972] pzsdr: Remove LED and button signals from PCIe
 carrier

Only the FMC carrier and the breakout board do have push buttons and LEDs.
They are not present on the PCIe carrier. So move the constraints to a
separate file that can be included by the projects that need them and
remove all LED and button related signals from the PCIe project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/common/pzsdr/pzsdr_bd_system_constr.xdc | 16 ++++++++++++++++
 projects/common/pzsdr/pzsdr_system_constr.xdc    | 16 ----------------
 projects/pzsdr/ccbrk/system_project.tcl          |  2 ++
 projects/pzsdr/ccbrk_cmos/system_project.tcl     |  1 +
 projects/pzsdr/ccfmc/system_project.tcl          |  2 ++
 projects/pzsdr/ccpci/system_top.v                | 10 ----------
 6 files changed, 21 insertions(+), 26 deletions(-)
 create mode 100644 projects/common/pzsdr/pzsdr_bd_system_constr.xdc

diff --git a/projects/common/pzsdr/pzsdr_bd_system_constr.xdc b/projects/common/pzsdr/pzsdr_bd_system_constr.xdc
new file mode 100644
index 000000000..1b84e3763
--- /dev/null
+++ b/projects/common/pzsdr/pzsdr_bd_system_constr.xdc
@@ -0,0 +1,16 @@
+
+# gpio
+
+set_property  -dict {PACKAGE_PIN  J3   IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L12N_T1_MRCC_33
+set_property  -dict {PACKAGE_PIN  D8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L8N_T1_34
+set_property  -dict {PACKAGE_PIN  F9   IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9P_T1_DQS_34
+set_property  -dict {PACKAGE_PIN  E8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]                        ; ## (pb)  IO_L9N_T1_DQS_34
+set_property  -dict {PACKAGE_PIN  A8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]]                        ; ## (led) IO_L17N_T2_34
+set_property  -dict {PACKAGE_PIN  W14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]]                        ; ## (led) IO_0_12
+set_property  -dict {PACKAGE_PIN  W17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]                        ; ## (led) IO_25_12
+set_property  -dict {PACKAGE_PIN  Y16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]                        ; ## (led) IO_L23P_T3_12
+set_property  -dict {PACKAGE_PIN  Y15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]]                        ; ## (dip) IO_L23N_T3_12
+set_property  -dict {PACKAGE_PIN  W16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]                        ; ## (dip) IO_L24P_T3_12
+set_property  -dict {PACKAGE_PIN  W15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]]                       ; ## (dip) IO_L24N_T3_12
+set_property  -dict {PACKAGE_PIN  V19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]                       ; ## (dip) IO_0_13
+
diff --git a/projects/common/pzsdr/pzsdr_system_constr.xdc b/projects/common/pzsdr/pzsdr_system_constr.xdc
index 05e510ba8..0c941c9bf 100644
--- a/projects/common/pzsdr/pzsdr_system_constr.xdc
+++ b/projects/common/pzsdr/pzsdr_system_constr.xdc
@@ -33,19 +33,3 @@ set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports clk_out]
 
 set_property  -dict {PACKAGE_PIN  AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L5P_T0_13             
 set_property  -dict {PACKAGE_PIN  AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L5N_T0_13             
-
-# gpio
-
-set_property  -dict {PACKAGE_PIN  J3   IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L12N_T1_MRCC_33       
-set_property  -dict {PACKAGE_PIN  D8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L8N_T1_34             
-set_property  -dict {PACKAGE_PIN  F9   IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9P_T1_DQS_34         
-set_property  -dict {PACKAGE_PIN  E8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]                        ; ## (pb)  IO_L9N_T1_DQS_34         
-set_property  -dict {PACKAGE_PIN  A8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]]                        ; ## (led) IO_L17N_T2_34            
-set_property  -dict {PACKAGE_PIN  W14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]]                        ; ## (led) IO_0_12                  
-set_property  -dict {PACKAGE_PIN  W17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]                        ; ## (led) IO_25_12                 
-set_property  -dict {PACKAGE_PIN  Y16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]                        ; ## (led) IO_L23P_T3_12            
-set_property  -dict {PACKAGE_PIN  Y15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]]                        ; ## (dip) IO_L23N_T3_12            
-set_property  -dict {PACKAGE_PIN  W16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]                        ; ## (dip) IO_L24P_T3_12            
-set_property  -dict {PACKAGE_PIN  W15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]]                       ; ## (dip) IO_L24N_T3_12            
-set_property  -dict {PACKAGE_PIN  V19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]                       ; ## (dip) IO_0_13                  
-
diff --git a/projects/pzsdr/ccbrk/system_project.tcl b/projects/pzsdr/ccbrk/system_project.tcl
index bcfeb1f4a..72cf71fed 100644
--- a/projects/pzsdr/ccbrk/system_project.tcl
+++ b/projects/pzsdr/ccbrk/system_project.tcl
@@ -11,9 +11,11 @@ adi_project_files ccbrk_pzsdr [list \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run ccbrk_pzsdr
diff --git a/projects/pzsdr/ccbrk_cmos/system_project.tcl b/projects/pzsdr/ccbrk_cmos/system_project.tcl
index 2912aaa6b..f32906815 100644
--- a/projects/pzsdr/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr/ccbrk_cmos/system_project.tcl
@@ -11,6 +11,7 @@ adi_project_files ccbrk_cmos_pzsdr [list \
   "../ccbrk/system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc" ]
 
 adi_project_run ccbrk_cmos_pzsdr
diff --git a/projects/pzsdr/ccfmc/system_project.tcl b/projects/pzsdr/ccfmc/system_project.tcl
index 5b6abc180..7c1d7075e 100644
--- a/projects/pzsdr/ccfmc/system_project.tcl
+++ b/projects/pzsdr/ccfmc/system_project.tcl
@@ -11,9 +11,11 @@ adi_project_files ccfmc_pzsdr [list \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 
 adi_project_run ccfmc_pzsdr
diff --git a/projects/pzsdr/ccpci/system_top.v b/projects/pzsdr/ccpci/system_top.v
index 835a89372..d72ac9b6e 100644
--- a/projects/pzsdr/ccpci/system_top.v
+++ b/projects/pzsdr/ccpci/system_top.v
@@ -65,8 +65,6 @@ module system_top (
   iic_scl,
   iic_sda,
 
-  gpio_bd,
-
   rx_clk_in_p,
   rx_clk_in_n,
   rx_frame_in_p,
@@ -131,8 +129,6 @@ module system_top (
   inout           iic_scl;
   inout           iic_sda;
 
-  inout   [11:0]  gpio_bd;
-
   input           rx_clk_in_p;
   input           rx_clk_in_n;
   input           rx_frame_in_p;
@@ -205,12 +201,6 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
-    .dio_t (gpio_t[11:0]),
-    .dio_i (gpio_o[11:0]),
-    .dio_o (gpio_i[11:0]),
-    .dio_p (gpio_bd));
-
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),

From 91782989adb210f672886312904819e95471dee2 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Thu, 14 Jul 2016 17:20:04 +0200
Subject: [PATCH 375/972] pzsdr: ccpci: Set IO standard to LVCMOS33 for banks
 12 and 13

The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/pzsdr/ccpci/system_constr.xdc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/projects/pzsdr/ccpci/system_constr.xdc b/projects/pzsdr/ccpci/system_constr.xdc
index 338bd4d3a..291fcd2d1 100644
--- a/projects/pzsdr/ccpci/system_constr.xdc
+++ b/projects/pzsdr/ccpci/system_constr.xdc
@@ -19,8 +19,12 @@ set_property  -dict {PACKAGE_PIN  AF4}  [get_ports pcie_data_tx_p[2]]
 set_property  -dict {PACKAGE_PIN  AF3}  [get_ports pcie_data_tx_n[2]]                                   ; ## MGTXTXN1_111
 set_property  -dict {PACKAGE_PIN  AF8}  [get_ports pcie_data_tx_p[3]]                                   ; ## MGTXTXP0_111
 set_property  -dict {PACKAGE_PIN  AF7}  [get_ports pcie_data_tx_n[3]]                                   ; ## MGTXTXN0_111
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports pcie_rstn]                      ; ## IO_L19P_T3_13      
-set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS25} [get_ports pcie_waken]                     ; ## IO_L20N_T3_13      
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS33} [get_ports pcie_rstn]                      ; ## IO_L19P_T3_13
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS33} [get_ports pcie_waken]                     ; ## IO_L20N_T3_13
+
+# Default constraints have LVCMOS25, overwite it
+set_property  -dict {IOSTANDARD LVCMOS33} [get_ports iic_scl]                                           ; ## IO_L5P_T0_13
+set_property  -dict {IOSTANDARD LVCMOS33} [get_ports iic_sda]                                           ; ## IO_L5N_T0_13
 
 set_property PULLUP true [get_ports pcie_rstn]
 set_property LOC IBUFDS_GTE2_X0Y5 [get_cells i_ibufds_pcie_ref_clk]

From 8f61e11a707b72c5d4c8ae523a1edddf98c67232 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Thu, 14 Jul 2016 17:20:09 +0200
Subject: [PATCH 376/972] pzsdr: ccpci: Add PCIe reset monitor

For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.

Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/pzsdr/ccpci/system_constr.xdc |  1 +
 projects/pzsdr/ccpci/system_top.v      | 35 ++++++++++++++++++++++++--
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/projects/pzsdr/ccpci/system_constr.xdc b/projects/pzsdr/ccpci/system_constr.xdc
index 291fcd2d1..149a2c1de 100644
--- a/projects/pzsdr/ccpci/system_constr.xdc
+++ b/projects/pzsdr/ccpci/system_constr.xdc
@@ -21,6 +21,7 @@ set_property  -dict {PACKAGE_PIN  AF8}  [get_ports pcie_data_tx_p[3]]
 set_property  -dict {PACKAGE_PIN  AF7}  [get_ports pcie_data_tx_n[3]]                                   ; ## MGTXTXN0_111
 set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS33} [get_ports pcie_rstn]                      ; ## IO_L19P_T3_13
 set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS33} [get_ports pcie_waken]                     ; ## IO_L20N_T3_13
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS33} [get_ports pcie_rstn_good]                 ; ## IO_L22N_T3_12
 
 # Default constraints have LVCMOS25, overwite it
 set_property  -dict {IOSTANDARD LVCMOS33} [get_ports iic_scl]                                           ; ## IO_L5P_T0_13
diff --git a/projects/pzsdr/ccpci/system_top.v b/projects/pzsdr/ccpci/system_top.v
index d72ac9b6e..a8bcc2e3b 100644
--- a/projects/pzsdr/ccpci/system_top.v
+++ b/projects/pzsdr/ccpci/system_top.v
@@ -101,7 +101,9 @@ module system_top (
   pcie_data_rx_p,
   pcie_data_rx_n,
   pcie_data_tx_p,
-  pcie_data_tx_n);
+  pcie_data_tx_n,
+
+  pcie_rstn_good);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -167,8 +169,14 @@ module system_top (
   output  [ 3:0]  pcie_data_tx_p;
   output  [ 3:0]  pcie_data_tx_n;
 
+  output          pcie_rstn_good;
+
   // internal signals
 
+  reg [3:0]       pcie_rstn_cnt0 = 'h00;
+  reg [3:0]       pcie_rstn_cnt1 = 'h00;
+  reg             pcie_rstn_good = 1'b0;
+
   wire            pcie_ref_clk;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
@@ -179,7 +187,30 @@ module system_top (
   // assignments
 
   assign pcie_waken = 1'bz;
-  assign gpio_ps_i[63:0] = 'h00;
+  assign gpio_ps_i[0] = pcie_rstn_good;
+  assign gpio_ps_i[63:1] = 'h00;
+
+  // PCIe reset monitor
+
+  always @(posedge pcie_ref_clk) begin
+    // If we see a stable low level followed by a stable high level we assume we
+    // got a good PCIe reset
+    if (pcie_rstn_cnt0 != 'hf) begin
+      if (pcie_rstn == 1'b0) begin
+        pcie_rstn_cnt0 <= pcie_rstn_cnt0 + 1'b1;
+      end else begin
+        pcie_rstn_cnt0 <= 'h00;
+      end
+    end else if (pcie_rstn_cnt1 != 'hf) begin
+      if (pcie_rstn == 1'b1) begin
+        pcie_rstn_cnt1 <= pcie_rstn_cnt1 + 1'b1;
+      end else begin
+        pcie_rstn_cnt1 <= 'h00;
+      end
+    end else begin
+      pcie_rstn_good <= 1'b1;
+    end
+  end
 
   // instantiations
 

From b806fa3b423ac02aad4064e518fb44d975a55744 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 5 Aug 2016 16:49:17 +0300
Subject: [PATCH 377/972] lib_refactoring: Move all the Xilinx common modules
 to library/xilinx/common

---
 library/{ => xilinx}/common/ad_iobuf.v      | 0
 library/{ => xilinx}/common/ad_lvds_clk.v   | 0
 library/{ => xilinx}/common/ad_lvds_in.v    | 0
 library/{ => xilinx}/common/ad_lvds_out.v   | 0
 library/{ => xilinx}/common/ad_mmcm_drp.v   | 0
 library/{ => xilinx}/common/ad_mul.v        | 0
 library/{ => xilinx}/common/ad_serdes_clk.v | 0
 library/{ => xilinx}/common/ad_serdes_in.v  | 0
 library/{ => xilinx}/common/ad_serdes_out.v | 0
 9 files changed, 0 insertions(+), 0 deletions(-)
 rename library/{ => xilinx}/common/ad_iobuf.v (100%)
 rename library/{ => xilinx}/common/ad_lvds_clk.v (100%)
 rename library/{ => xilinx}/common/ad_lvds_in.v (100%)
 rename library/{ => xilinx}/common/ad_lvds_out.v (100%)
 rename library/{ => xilinx}/common/ad_mmcm_drp.v (100%)
 rename library/{ => xilinx}/common/ad_mul.v (100%)
 rename library/{ => xilinx}/common/ad_serdes_clk.v (100%)
 rename library/{ => xilinx}/common/ad_serdes_in.v (100%)
 rename library/{ => xilinx}/common/ad_serdes_out.v (100%)

diff --git a/library/common/ad_iobuf.v b/library/xilinx/common/ad_iobuf.v
similarity index 100%
rename from library/common/ad_iobuf.v
rename to library/xilinx/common/ad_iobuf.v
diff --git a/library/common/ad_lvds_clk.v b/library/xilinx/common/ad_lvds_clk.v
similarity index 100%
rename from library/common/ad_lvds_clk.v
rename to library/xilinx/common/ad_lvds_clk.v
diff --git a/library/common/ad_lvds_in.v b/library/xilinx/common/ad_lvds_in.v
similarity index 100%
rename from library/common/ad_lvds_in.v
rename to library/xilinx/common/ad_lvds_in.v
diff --git a/library/common/ad_lvds_out.v b/library/xilinx/common/ad_lvds_out.v
similarity index 100%
rename from library/common/ad_lvds_out.v
rename to library/xilinx/common/ad_lvds_out.v
diff --git a/library/common/ad_mmcm_drp.v b/library/xilinx/common/ad_mmcm_drp.v
similarity index 100%
rename from library/common/ad_mmcm_drp.v
rename to library/xilinx/common/ad_mmcm_drp.v
diff --git a/library/common/ad_mul.v b/library/xilinx/common/ad_mul.v
similarity index 100%
rename from library/common/ad_mul.v
rename to library/xilinx/common/ad_mul.v
diff --git a/library/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v
similarity index 100%
rename from library/common/ad_serdes_clk.v
rename to library/xilinx/common/ad_serdes_clk.v
diff --git a/library/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v
similarity index 100%
rename from library/common/ad_serdes_in.v
rename to library/xilinx/common/ad_serdes_in.v
diff --git a/library/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v
similarity index 100%
rename from library/common/ad_serdes_out.v
rename to library/xilinx/common/ad_serdes_out.v

From f78455789518f2ceb7d71cd10875f0f55d7d2553 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 5 Aug 2016 17:19:30 +0300
Subject: [PATCH 378/972] lib_refactoring: IOBUF is a Xilinx macro, no need to
 use with Altera

---
 projects/arradio/c5soc/system_project.tcl     | 1 -
 projects/daq2/a10gx/system_project.tcl        | 1 -
 projects/fmcjesdadc1/a5gt/system_project.tcl  | 1 -
 projects/fmcjesdadc1/a5soc/system_project.tcl | 1 -
 4 files changed, 4 deletions(-)

diff --git a/projects/arradio/c5soc/system_project.tcl b/projects/arradio/c5soc/system_project.tcl
index 2fbce5857..70c4b16bd 100644
--- a/projects/arradio/c5soc/system_project.tcl
+++ b/projects/arradio/c5soc/system_project.tcl
@@ -7,7 +7,6 @@ project_new arradio_c5soc -overwrite
 source "../../common/c5soc/c5soc_system_assign.tcl"
 
 set_global_assignment -name QSYS_FILE system_bd.qsys
-set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
 set_global_assignment -name VERILOG_FILE system_top.v
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
diff --git a/projects/daq2/a10gx/system_project.tcl b/projects/daq2/a10gx/system_project.tcl
index 6947398c3..55dcff77f 100644
--- a/projects/daq2/a10gx/system_project.tcl
+++ b/projects/daq2/a10gx/system_project.tcl
@@ -6,7 +6,6 @@ project_new daq2_a10gx -overwrite
 
 source "../../common/a10gx/a10gx_system_assign.tcl"
 
-set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
 set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
 set_global_assignment -name QSYS_FILE system_bd.qsys
diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl
index d554fce31..f186b6135 100755
--- a/projects/fmcjesdadc1/a5gt/system_project.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_project.tcl
@@ -9,7 +9,6 @@ set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../
 set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
 set_global_assignment -name QSYS_FILE system_bd.qsys
 
-set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
 set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
 
diff --git a/projects/fmcjesdadc1/a5soc/system_project.tcl b/projects/fmcjesdadc1/a5soc/system_project.tcl
index a94a42fa0..27d33b6d2 100755
--- a/projects/fmcjesdadc1/a5soc/system_project.tcl
+++ b/projects/fmcjesdadc1/a5soc/system_project.tcl
@@ -9,7 +9,6 @@ set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a5soc;../..
 set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a5soc/;../../../library/**/*"
 set_global_assignment -name QSYS_FILE system_bd.qsys
 
-set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
 set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
 

From cb9af99c5dcebcf563cde50213243a82392c7873 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 5 Aug 2016 17:48:21 +0300
Subject: [PATCH 379/972] lib_refactoring: Add ad_mul.v for Altera

---
 library/altera/common/ad_mul.v | 105 +++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 library/altera/common/ad_mul.v

diff --git a/library/altera/common/ad_mul.v b/library/altera/common/ad_mul.v
new file mode 100644
index 000000000..896f9f185
--- /dev/null
+++ b/library/altera/common/ad_mul.v
@@ -0,0 +1,105 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ps/1ps
+
+module ad_mul (
+
+  // data_p = data_a * data_b;
+
+  clk,
+  data_a,
+  data_b,
+  data_p,
+
+  // delay interface
+
+  ddata_in,
+  ddata_out);
+
+  // delayed data bus width
+
+  parameter   DELAY_DATA_WIDTH = 16;
+
+  // data_p = data_a * data_b;
+
+  input                               clk;
+  input   [16:0]                      data_a;
+  input   [16:0]                      data_b;
+  output  [33:0]                      data_p;
+
+  // delay interface
+
+  input   [(DELAY_DATA_WIDTH-1):0]    ddata_in;
+  output  [(DELAY_DATA_WIDTH-1):0]    ddata_out;
+
+  // internal registers
+
+  reg     [(DELAY_DATA_WIDTH-1):0]    p1_ddata = 'd0;
+  reg     [(DELAY_DATA_WIDTH-1):0]    p2_ddata = 'd0;
+  reg     [(DELAY_DATA_WIDTH-1):0]    ddata_out = 'd0;
+
+  // a/b reg, m-reg, p-reg delay match
+
+  always @(posedge clk) begin
+    p1_ddata <= ddata_in;
+    p2_ddata <= p1_ddata;
+    ddata_out <= p2_ddata;
+  end
+
+  lpm_mult #(
+    .lpm_type ("lpm_mult"),
+    .lpm_widtha (17),
+    .lpm_widthb (17),
+    .lpm_widthp (34),
+    .lpm_representation ("SIGNED"),
+    .lpm_pipeline (3))
+  i_lpm_mult (
+    .clken (1'b1),
+    .aclr (1'b0),
+    .sum (1'b0),
+    .clock (clk),
+    .dataa (data_a),
+    .datab (data_b),
+    .result (data_p));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 90ac7b7ac9781325a1c32cf7178d0a31b2032ac0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 5 Aug 2016 17:53:27 +0300
Subject: [PATCH 380/972] lib_refactoring: Move all Altera module to
 library/altera/common

Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
---
 .../altera => altera/common}/ad_cmos_clk.v    |   0
 .../altera => altera/common}/ad_cmos_in.v     |   0
 .../altera => altera/common}/ad_cmos_out.v    |   0
 .../altera => altera/common}/ad_lvds_clk.v    |   0
 .../altera => altera/common}/ad_lvds_in.v     |   0
 .../altera => altera/common}/ad_lvds_out.v    |   0
 library/common/altera/DSP48E1.v               | 186 ------------------
 library/common/altera/MULT_MACRO.v            |  83 --------
 8 files changed, 269 deletions(-)
 rename library/{common/altera => altera/common}/ad_cmos_clk.v (100%)
 rename library/{common/altera => altera/common}/ad_cmos_in.v (100%)
 rename library/{common/altera => altera/common}/ad_cmos_out.v (100%)
 rename library/{common/altera => altera/common}/ad_lvds_clk.v (100%)
 rename library/{common/altera => altera/common}/ad_lvds_in.v (100%)
 rename library/{common/altera => altera/common}/ad_lvds_out.v (100%)
 delete mode 100644 library/common/altera/DSP48E1.v
 delete mode 100644 library/common/altera/MULT_MACRO.v

diff --git a/library/common/altera/ad_cmos_clk.v b/library/altera/common/ad_cmos_clk.v
similarity index 100%
rename from library/common/altera/ad_cmos_clk.v
rename to library/altera/common/ad_cmos_clk.v
diff --git a/library/common/altera/ad_cmos_in.v b/library/altera/common/ad_cmos_in.v
similarity index 100%
rename from library/common/altera/ad_cmos_in.v
rename to library/altera/common/ad_cmos_in.v
diff --git a/library/common/altera/ad_cmos_out.v b/library/altera/common/ad_cmos_out.v
similarity index 100%
rename from library/common/altera/ad_cmos_out.v
rename to library/altera/common/ad_cmos_out.v
diff --git a/library/common/altera/ad_lvds_clk.v b/library/altera/common/ad_lvds_clk.v
similarity index 100%
rename from library/common/altera/ad_lvds_clk.v
rename to library/altera/common/ad_lvds_clk.v
diff --git a/library/common/altera/ad_lvds_in.v b/library/altera/common/ad_lvds_in.v
similarity index 100%
rename from library/common/altera/ad_lvds_in.v
rename to library/altera/common/ad_lvds_in.v
diff --git a/library/common/altera/ad_lvds_out.v b/library/altera/common/ad_lvds_out.v
similarity index 100%
rename from library/common/altera/ad_lvds_out.v
rename to library/altera/common/ad_lvds_out.v
diff --git a/library/common/altera/DSP48E1.v b/library/common/altera/DSP48E1.v
deleted file mode 100644
index cdf993f86..000000000
--- a/library/common/altera/DSP48E1.v
+++ /dev/null
@@ -1,186 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
-
-`timescale 1ps/1ps
-
-module DSP48E1 (
-
-  ACOUT,
-  BCOUT,
-  CARRYCASCOUT,
-  CARRYOUT,
-  MULTSIGNOUT,
-  OVERFLOW,
-  P,
-  PATTERNBDETECT,
-  PATTERNDETECT,
-  PCOUT,
-  UNDERFLOW,
-  A,
-  ACIN,
-  ALUMODE,
-  B,
-  BCIN,
-  C,
-  CARRYCASCIN,
-  CARRYIN,
-  CARRYINSEL,
-  CEA1,
-  CEA2,
-  CEAD,
-  CEALUMODE,
-  CEB1,
-  CEB2,
-  CEC,
-  CECARRYIN,
-  CECTRL,
-  CED,
-  CEINMODE,
-  CEM,
-  CEP,
-  CLK,
-  D,
-  INMODE,
-  MULTSIGNIN,
-  OPMODE,
-  PCIN,
-  RSTA,
-  RSTALLCARRYIN,
-  RSTALUMODE,
-  RSTB,
-  RSTC,
-  RSTCTRL,
-  RSTD,
-  RSTINMODE,
-  RSTM,
-  RSTP);
-
-  parameter ACASCREG = 1;
-  parameter ADREG = 1;
-  parameter ALUMODEREG = 1;
-  parameter AREG = 1;
-  parameter AUTORESET_PATDET = "NO_RESET";
-  parameter A_INPUT = "DIRECT";
-  parameter BCASCREG = 1;
-  parameter BREG = 1;
-  parameter B_INPUT = "DIRECT";
-  parameter CARRYINREG = 1;
-  parameter CARRYINSELREG = 1;
-  parameter CREG = 1;
-  parameter DREG = 1;
-  parameter INMODEREG = 1;
-  parameter MASK = 'h3fffffffffff;
-  parameter MREG = 1;
-  parameter OPMODEREG = 1;
-  parameter PATTERN = 0;
-  parameter PREG = 1;
-  parameter SEL_MASK = "MASK";
-  parameter SEL_PATTERN = "PATTERN";
-  parameter USE_DPORT = 0;
-  parameter USE_MULT = "MULTIPLY";
-  parameter USE_PATTERN_DETECT = "NO_PATDET";
-  parameter USE_SIMD = "ONE48";
-
-  output  [29:0]  ACOUT;
-  output  [17:0]  BCOUT;
-  output          CARRYCASCOUT;
-  output  [ 3:0]  CARRYOUT;
-  output          MULTSIGNOUT;
-  output          OVERFLOW;
-  output  [47:0]  P;
-  output          PATTERNBDETECT;
-  output          PATTERNDETECT;
-  output  [47:0]  PCOUT;
-  output          UNDERFLOW;
-  input   [29:0]  A;
-  input   [29:0]  ACIN;
-  input   [ 3:0]  ALUMODE;
-  input   [17:0]  B;
-  input   [17:0]  BCIN;
-  input   [47:0]  C;
-  input           CARRYCASCIN;
-  input           CARRYIN;
-  input   [ 2:0]  CARRYINSEL;
-  input           CEA1;
-  input           CEA2;
-  input           CEAD;
-  input           CEALUMODE;
-  input           CEB1;
-  input           CEB2;
-  input           CEC;
-  input           CECARRYIN;
-  input           CECTRL;
-  input           CED;
-  input           CEINMODE;
-  input           CEM;
-  input           CEP;
-  input           CLK;
-  input   [24:0]  D;
-  input   [ 4:0]  INMODE;
-  input           MULTSIGNIN;
-  input   [ 6:0]  OPMODE;
-  input   [47:0]  PCIN;
-  input           RSTA;
-  input           RSTALLCARRYIN;
-  input           RSTALUMODE;
-  input           RSTB;
-  input           RSTC;
-  input           RSTCTRL;
-  input           RSTD;
-  input           RSTINMODE;
-  input           RSTM;
-  input           RSTP;
-
-  assign  ACOUT = 30'd0;
-  assign  BCOUT = 18'd0;
-  assign  CARRYCASCOUT = 1'd0;
-  assign  CARRYOUT = 4'd0;
-  assign  MULTSIGNOUT = 1'd0;
-  assign  OVERFLOW = 1'd0;
-  assign  P = 48'd0;
-  assign  PATTERNBDETECT = 1'd0;
-  assign  PATTERNDETECT = 1'd0;
-  assign  PCOUT = 48'd0;
-  assign  UNDERFLOW = 1'd0;
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/altera/MULT_MACRO.v b/library/common/altera/MULT_MACRO.v
deleted file mode 100644
index 54e6207ec..000000000
--- a/library/common/altera/MULT_MACRO.v
+++ /dev/null
@@ -1,83 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2014(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// replacing Xilinx's macro with Altera's LPM
-
-`timescale 1ps/1ps
-
-module MULT_MACRO (
-
-  CE,
-  RST,
-  CLK,
-  A,
-  B,
-  P);
-
-  parameter   LATENCY = 3;
-  parameter   WIDTH_A = 16;
-  parameter   WIDTH_B = 16;
-
-  localparam  WIDTH_P = WIDTH_A + WIDTH_B;
-
-  input                   CE;
-  input                   RST;
-  input                   CLK;
-
-  input   [WIDTH_A-1:0]   A;
-  input   [WIDTH_B-1:0]   B;
-  output  [WIDTH_P-1:0]   P;
-
-  lpm_mult #(
-    .lpm_type ("lpm_mult"),
-    .lpm_widtha (WIDTH_A),
-    .lpm_widthb (WIDTH_B),
-    .lpm_widthp (WIDTH_P),
-    .lpm_representation ("SIGNED"),
-    .lpm_pipeline (3))
-  i_lpm_mult (
-    .clken (CE),
-    .aclr (RST),
-    .sum (1'b0),
-    .clock (CLK),
-    .dataa (A),
-    .datab (B),
-    .result (P));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From df3690271320782e271a950aecd6cddad66481a1 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 5 Aug 2016 18:00:34 +0300
Subject: [PATCH 381/972] lib_refactoring: Fix path of the IO macros

---
 library/axi_ad9122/axi_ad9122_ip.tcl          |  8 ++++----
 library/axi_ad9144/axi_ad9144_hw.tcl          |  3 +--
 library/axi_ad9144/axi_ad9144_ip.tcl          |  2 +-
 library/axi_ad9152/axi_ad9152_hw.tcl          |  3 +--
 library/axi_ad9152/axi_ad9152_ip.tcl          |  2 +-
 library/axi_ad9162/axi_ad9162_ip.tcl          |  2 +-
 library/axi_ad9265/axi_ad9265_ip.tcl          |  4 ++--
 library/axi_ad9361/axi_ad9361_hw.tcl          | 18 ++++++++----------
 library/axi_ad9361/axi_ad9361_ip.tcl          |  8 ++++----
 library/axi_ad9371/axi_ad9371_hw.tcl          |  4 +---
 library/axi_ad9371/axi_ad9371_ip.tcl          |  2 +-
 library/axi_ad9434/axi_ad9434_ip.tcl          |  6 +++---
 library/axi_ad9467/axi_ad9467_ip.tcl          |  4 ++--
 library/axi_ad9643/axi_ad9643_ip.tcl          |  6 +++---
 library/axi_ad9652/axi_ad9652_ip.tcl          |  6 +++---
 library/axi_ad9684/axi_ad9684_ip.tcl          |  6 +++---
 library/axi_ad9739a/axi_ad9739a_ip.tcl        |  4 ++--
 library/axi_clkgen/axi_clkgen_ip.tcl          |  2 +-
 library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl        |  1 -
 projects/ad6676evb/vc707/system_project.tcl   |  2 +-
 projects/ad6676evb/zc706/system_project.tcl   |  2 +-
 projects/ad7616_sdz/zc706/system_project.tcl  |  4 ++--
 projects/ad7616_sdz/zed/system_project.tcl    |  4 ++--
 projects/ad7768evb/zed/system_project.tcl     |  2 +-
 projects/ad9265_fmc/zc706/system_project.tcl  |  2 +-
 projects/ad9434_fmc/zc706/system_project.tcl  |  2 +-
 projects/ad9467_fmc/kc705/system_project.tcl  |  2 +-
 projects/ad9467_fmc/zed/system_project.tcl    |  2 +-
 projects/ad9739a_fmc/zc706/system_project.tcl |  2 +-
 projects/adrv9371x/zc706/system_project.tcl   |  2 +-
 projects/adv7511/ac701/system_project.tcl     |  2 +-
 projects/adv7511/kc705/system_project.tcl     |  2 +-
 projects/adv7511/kcu105/system_project.tcl    |  2 +-
 projects/adv7511/mitx045/system_project.tcl   |  2 +-
 projects/adv7511/vc707/system_project.tcl     |  2 +-
 projects/adv7511/zc702/system_project.tcl     |  2 +-
 projects/adv7511/zc706/system_project.tcl     |  2 +-
 projects/adv7511/zed/system_project.tcl       |  2 +-
 projects/cftl_cip/zed/system_project.tcl      |  2 +-
 projects/cftl_std/zed/system_project.tcl      |  2 +-
 projects/cn0363/microzed/system_project.tcl   |  2 +-
 projects/cn0363/zed/system_project.tcl        |  2 +-
 projects/daq1/zc706/system_project.tcl        |  2 +-
 projects/daq2/kc705/system_project.tcl        |  2 +-
 projects/daq2/kcu105/system_project.tcl       |  2 +-
 projects/daq2/vc707/system_project.tcl        |  2 +-
 projects/daq2/zc706/system_project.tcl        |  2 +-
 projects/daq3/kcu105/system_project.tcl       |  2 +-
 projects/daq3/zc706/system_project.tcl        |  2 +-
 projects/fmcadc2/vc707/system_project.tcl     |  2 +-
 projects/fmcadc2/zc706/system_project.tcl     |  2 +-
 projects/fmcadc4/zc706/system_project.tcl     |  2 +-
 projects/fmcadc5/vc707/system_project.tcl     |  4 ++--
 projects/fmcjesdadc1/kc705/system_project.tcl |  2 +-
 projects/fmcjesdadc1/vc707/system_project.tcl |  2 +-
 projects/fmcjesdadc1/zc706/system_project.tcl |  2 +-
 projects/fmcomms1/ac701/system_project.tcl    |  2 +-
 projects/fmcomms1/kc705/system_project.tcl    |  2 +-
 projects/fmcomms1/vc707/system_project.tcl    |  2 +-
 projects/fmcomms1/zc702/system_project.tcl    |  2 +-
 projects/fmcomms1/zc706/system_project.tcl    |  2 +-
 projects/fmcomms1/zed/system_project.tcl      |  2 +-
 projects/fmcomms11/zc706/system_project.tcl   |  2 +-
 projects/fmcomms2/ac701/system_project.tcl    |  2 +-
 projects/fmcomms2/kc705/system_project.tcl    |  2 +-
 projects/fmcomms2/mitx045/system_project.tcl  |  2 +-
 projects/fmcomms2/vc707/system_project.tcl    |  2 +-
 projects/fmcomms2/zc702/system_project.tcl    |  2 +-
 projects/fmcomms2/zc706/system_project.tcl    |  2 +-
 projects/fmcomms2/zc706pr/system_project.tcl  |  2 +-
 projects/fmcomms2/zcu102/system_project.tcl   |  2 +-
 projects/fmcomms2/zed/system_project.tcl      |  2 +-
 projects/fmcomms5/zc702/system_project.tcl    |  2 +-
 projects/fmcomms5/zc706/system_project.tcl    |  2 +-
 projects/fmcomms6/zc706/system_project.tcl    |  2 +-
 projects/fmcomms7/zc706/system_project.tcl    |  2 +-
 projects/imageon/zc706/system_project.tcl     |  2 +-
 projects/imageon/zed/system_project.tcl       |  2 +-
 projects/motcon2_fmc/zed/system_project.tcl   |  2 +-
 projects/pzsdr/ccbrk/system_project.tcl       |  2 +-
 projects/pzsdr/ccbrk_cmos/system_project.tcl  |  2 +-
 projects/pzsdr/ccfmc/system_project.tcl       |  2 +-
 projects/pzsdr/ccpci/system_project.tcl       |  2 +-
 projects/pzsdr1/ccbrk/system_project.tcl      |  2 +-
 projects/pzsdr1/ccbrk_cmos/system_project.tcl |  2 +-
 projects/usb_fx3/zc706/system_project.tcl     |  2 +-
 86 files changed, 112 insertions(+), 119 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122_ip.tcl b/library/axi_ad9122/axi_ad9122_ip.tcl
index badf2c985..577439622 100644
--- a/library/axi_ad9122/axi_ad9122_ip.tcl
+++ b/library/axi_ad9122/axi_ad9122_ip.tcl
@@ -5,14 +5,14 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create axi_ad9122
 adi_ip_files axi_ad9122 [list \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
   "$ad_hdl_dir/library/common/ad_dds_1.v" \
   "$ad_hdl_dir/library/common/ad_dds.v" \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
-  "$ad_hdl_dir/library/common/ad_serdes_out.v" \
-  "$ad_hdl_dir/library/common/ad_serdes_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
   "$ad_hdl_dir/library/common/up_axi.v" \
   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
   "$ad_hdl_dir/library/common/up_xfer_status.v" \
diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl
index eb28df04f..1bd871a6e 100755
--- a/library/axi_ad9144/axi_ad9144_hw.tcl
+++ b/library/axi_ad9144/axi_ad9144_hw.tcl
@@ -15,8 +15,7 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9144
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9144
-add_fileset_file MULT_MACRO.v         VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
-add_fileset_file ad_mul.v             VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
+add_fileset_file ad_mul.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
 add_fileset_file ad_dds_sine.v        VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
 add_fileset_file ad_dds_1.v           VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
 add_fileset_file ad_dds.v             VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
diff --git a/library/axi_ad9144/axi_ad9144_ip.tcl b/library/axi_ad9144/axi_ad9144_ip.tcl
index dac97de77..13f868e4d 100644
--- a/library/axi_ad9144/axi_ad9144_ip.tcl
+++ b/library/axi_ad9144/axi_ad9144_ip.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_ad9144
 adi_ip_files axi_ad9144 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
   "$ad_hdl_dir/library/common/ad_dds_1.v" \
   "$ad_hdl_dir/library/common/ad_dds.v" \
diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl
index e2642f384..c9e0af707 100755
--- a/library/axi_ad9152/axi_ad9152_hw.tcl
+++ b/library/axi_ad9152/axi_ad9152_hw.tcl
@@ -14,8 +14,7 @@ set_module_property DISPLAY_NAME axi_ad9152
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9152
-add_fileset_file MULT_MACRO.v         VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
-add_fileset_file ad_mul.v             VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
+add_fileset_file ad_mul.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
 add_fileset_file ad_dds_sine.v        VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
 add_fileset_file ad_dds_1.v           VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
 add_fileset_file ad_dds.v             VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
diff --git a/library/axi_ad9152/axi_ad9152_ip.tcl b/library/axi_ad9152/axi_ad9152_ip.tcl
index 5f67222e0..055b8becb 100644
--- a/library/axi_ad9152/axi_ad9152_ip.tcl
+++ b/library/axi_ad9152/axi_ad9152_ip.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_ad9152
 adi_ip_files axi_ad9152 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
   "$ad_hdl_dir/library/common/ad_dds_1.v" \
   "$ad_hdl_dir/library/common/ad_dds.v" \
diff --git a/library/axi_ad9162/axi_ad9162_ip.tcl b/library/axi_ad9162/axi_ad9162_ip.tcl
index 7c30478c1..07312eb24 100644
--- a/library/axi_ad9162/axi_ad9162_ip.tcl
+++ b/library/axi_ad9162/axi_ad9162_ip.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_ad9162
 adi_ip_files axi_ad9162 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
   "$ad_hdl_dir/library/common/ad_dds_1.v" \
   "$ad_hdl_dir/library/common/ad_dds.v" \
diff --git a/library/axi_ad9265/axi_ad9265_ip.tcl b/library/axi_ad9265/axi_ad9265_ip.tcl
index b35aeebbd..2310f642a 100644
--- a/library/axi_ad9265/axi_ad9265_ip.tcl
+++ b/library/axi_ad9265/axi_ad9265_ip.tcl
@@ -6,8 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_ad9265
 adi_ip_files axi_ad9265 [list \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_clk.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
   "$ad_hdl_dir/library/common/ad_datafmt.v" \
   "$ad_hdl_dir/library/common/ad_dcfilter.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index fec710019..77b3d4cd4 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -15,16 +15,14 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9361
 
 add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
-add_fileset_file MULT_MACRO.v             VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
-add_fileset_file DSP48E1.v                VERILOG PATH $ad_hdl_dir/library/common/altera/DSP48E1.v
 add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file ad_lvds_clk.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_clk.v
-add_fileset_file ad_lvds_in.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_in.v
-add_fileset_file ad_lvds_out.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_out.v
-add_fileset_file ad_cmos_clk.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_cmos_clk.v
-add_fileset_file ad_cmos_in.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_cmos_in.v
-add_fileset_file ad_cmos_out.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_cmos_out.v
-add_fileset_file ad_mul.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
+add_fileset_file ad_lvds_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_clk.v
+add_fileset_file ad_lvds_in.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_in.v
+add_fileset_file ad_lvds_out.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_out.v
+add_fileset_file ad_cmos_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_clk.v
+add_fileset_file ad_cmos_in.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_in.v
+add_fileset_file ad_cmos_out.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_out.v
+add_fileset_file ad_mul.v                 VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
 add_fileset_file ad_pnmon.v               VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
 add_fileset_file ad_dds_sine.v            VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
 add_fileset_file ad_dds_1.v               VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
@@ -94,7 +92,7 @@ set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
 set_parameter_property ADC_DATAPATH_DISABLE UNITS None
 set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
 
-add_parameter DEVICE_FAMILY STRING 
+add_parameter DEVICE_FAMILY STRING
 set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
 set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
 set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl
index 470b780d3..1e8b1a2be 100755
--- a/library/axi_ad9361/axi_ad9361_ip.tcl
+++ b/library/axi_ad9361/axi_ad9361_ip.tcl
@@ -7,13 +7,13 @@ adi_ip_create axi_ad9361
 adi_ip_files axi_ad9361 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_clk.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_in.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
   "$ad_hdl_dir/library/common/ad_cmos_clk.v" \
   "$ad_hdl_dir/library/common/ad_cmos_in.v" \
   "$ad_hdl_dir/library/common/ad_cmos_out.v" \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
   "$ad_hdl_dir/library/common/ad_dds_1.v" \
diff --git a/library/axi_ad9371/axi_ad9371_hw.tcl b/library/axi_ad9371/axi_ad9371_hw.tcl
index 24e732442..569c5ac79 100755
--- a/library/axi_ad9371/axi_ad9371_hw.tcl
+++ b/library/axi_ad9371/axi_ad9371_hw.tcl
@@ -14,10 +14,8 @@ set_module_property DISPLAY_NAME axi_ad9371
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9371
-add_fileset_file MULT_MACRO.v               VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
-add_fileset_file DSP48E1.v                  VERILOG PATH $ad_hdl_dir/library/common/altera/DSP48E1.v
 add_fileset_file ad_rst.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file ad_mul.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
+add_fileset_file ad_mul.v                   VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
 add_fileset_file ad_dds_sine.v              VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
 add_fileset_file ad_dds_1.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
 add_fileset_file ad_dds.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
diff --git a/library/axi_ad9371/axi_ad9371_ip.tcl b/library/axi_ad9371/axi_ad9371_ip.tcl
index dc67d418e..7f5e2afe6 100755
--- a/library/axi_ad9371/axi_ad9371_ip.tcl
+++ b/library/axi_ad9371/axi_ad9371_ip.tcl
@@ -7,7 +7,7 @@ adi_ip_create axi_ad9371
 adi_ip_files axi_ad9371 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
   "$ad_hdl_dir/library/common/ad_dds_1.v" \
   "$ad_hdl_dir/library/common/ad_dds.v" \
diff --git a/library/axi_ad9434/axi_ad9434_ip.tcl b/library/axi_ad9434/axi_ad9434_ip.tcl
index d13a1bbd6..7e9f4cb4f 100644
--- a/library/axi_ad9434/axi_ad9434_ip.tcl
+++ b/library/axi_ad9434/axi_ad9434_ip.tcl
@@ -5,9 +5,9 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create axi_ad9434
 adi_ip_files axi_ad9434 [list \
-  "$ad_hdl_dir/library/common/ad_serdes_clk.v" \
-  "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
-  "$ad_hdl_dir/library/common/ad_serdes_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \
   "$ad_hdl_dir/library/common/ad_datafmt.v" \
   "$ad_hdl_dir/library/common/ad_rst.v" \
   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
diff --git a/library/axi_ad9467/axi_ad9467_ip.tcl b/library/axi_ad9467/axi_ad9467_ip.tcl
index 127effe37..1c61b680e 100644
--- a/library/axi_ad9467/axi_ad9467_ip.tcl
+++ b/library/axi_ad9467/axi_ad9467_ip.tcl
@@ -6,8 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_ad9467
 adi_ip_files axi_ad9467 [list \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_clk.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
   "$ad_hdl_dir/library/common/ad_datafmt.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/up_xfer_status.v" \
diff --git a/library/axi_ad9643/axi_ad9643_ip.tcl b/library/axi_ad9643/axi_ad9643_ip.tcl
index 51781ca0c..cbb5e2a9d 100644
--- a/library/axi_ad9643/axi_ad9643_ip.tcl
+++ b/library/axi_ad9643/axi_ad9643_ip.tcl
@@ -6,9 +6,9 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_ad9643
 adi_ip_files axi_ad9643 [list \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_clk.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/ad_datafmt.v" \
   "$ad_hdl_dir/library/common/ad_dcfilter.v" \
diff --git a/library/axi_ad9652/axi_ad9652_ip.tcl b/library/axi_ad9652/axi_ad9652_ip.tcl
index 5033b8b03..99bb266b9 100644
--- a/library/axi_ad9652/axi_ad9652_ip.tcl
+++ b/library/axi_ad9652/axi_ad9652_ip.tcl
@@ -6,9 +6,9 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_ad9652
 adi_ip_files axi_ad9652 [list \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_clk.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/ad_dcfilter.v" \
   "$ad_hdl_dir/library/common/ad_iqcor.v" \
diff --git a/library/axi_ad9684/axi_ad9684_ip.tcl b/library/axi_ad9684/axi_ad9684_ip.tcl
index 828ce234b..3ad31474e 100644
--- a/library/axi_ad9684/axi_ad9684_ip.tcl
+++ b/library/axi_ad9684/axi_ad9684_ip.tcl
@@ -7,9 +7,9 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_ad9684
 adi_ip_files axi_ad9684 [list \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_serdes_in.v" \
-  "$ad_hdl_dir/library/common/ad_serdes_clk.v" \
-  "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
   "$ad_hdl_dir/library/common/ad_datafmt.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/up_xfer_status.v" \
diff --git a/library/axi_ad9739a/axi_ad9739a_ip.tcl b/library/axi_ad9739a/axi_ad9739a_ip.tcl
index 49134339c..3c152248d 100644
--- a/library/axi_ad9739a/axi_ad9739a_ip.tcl
+++ b/library/axi_ad9739a/axi_ad9739a_ip.tcl
@@ -5,12 +5,12 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create axi_ad9739a
 adi_ip_files axi_ad9739a [list \
-  "$ad_hdl_dir/library/common/ad_mul.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
   "$ad_hdl_dir/library/common/ad_dds_1.v" \
   "$ad_hdl_dir/library/common/ad_dds.v" \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_serdes_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \
   "$ad_hdl_dir/library/common/up_axi.v" \
   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
   "$ad_hdl_dir/library/common/up_xfer_status.v" \
diff --git a/library/axi_clkgen/axi_clkgen_ip.tcl b/library/axi_clkgen/axi_clkgen_ip.tcl
index 0a472245e..4f041d954 100644
--- a/library/axi_clkgen/axi_clkgen_ip.tcl
+++ b/library/axi_clkgen/axi_clkgen_ip.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create axi_clkgen
 adi_ip_files axi_clkgen [list \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
   "$ad_hdl_dir/library/common/up_axi.v" \
   "$ad_hdl_dir/library/common/up_clkgen.v" \
   "axi_clkgen_constr.xdc" \
diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
index 8492d8cc1..9ee79219e 100755
--- a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
@@ -14,7 +14,6 @@ set_module_property DISPLAY_NAME axi_hdmi_tx
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_hdmi_tx
-add_fileset_file MULT_MACRO.v             VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
 add_fileset_file ad_mem.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
 add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_csc_1_mul.v           VERILOG PATH $ad_hdl_dir/library/common/ad_csc_1_mul.v
diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl
index 5439f1a91..5c7821c5b 100644
--- a/projects/ad6676evb/vc707/system_project.tcl
+++ b/projects/ad6676evb/vc707/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ad6676evb_vc707
 adi_project_files ad6676evb_vc707 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
diff --git a/projects/ad6676evb/zc706/system_project.tcl b/projects/ad6676evb/zc706/system_project.tcl
index b505e455c..debd98e9f 100644
--- a/projects/ad6676evb/zc706/system_project.tcl
+++ b/projects/ad6676evb/zc706/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ad6676evb_zc706
 adi_project_files ad6676evb_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl
index d36937e08..7d5ea14c0 100644
--- a/projects/ad7616_sdz/zc706/system_project.tcl
+++ b/projects/ad7616_sdz/zc706/system_project.tcl
@@ -23,7 +23,7 @@ adi_project_create ad7616_sdz_zc706
 if { $ad7616_if == 0 } {
 
   adi_project_files ad7616_sdz_zc706 [list \
-    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
     "system_top_si.v" \
     "serial_if_constr.xdc" \
     "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
@@ -31,7 +31,7 @@ if { $ad7616_if == 0 } {
 } elseif { $ad7616_if == 1 } {
 
   adi_project_files ad7616_sdz_zc706 [list \
-    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
     "system_top_pi.v" \
     "parallel_if_constr.xdc" \
     "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
diff --git a/projects/ad7616_sdz/zed/system_project.tcl b/projects/ad7616_sdz/zed/system_project.tcl
index f46ea4c76..e74dc8376 100644
--- a/projects/ad7616_sdz/zed/system_project.tcl
+++ b/projects/ad7616_sdz/zed/system_project.tcl
@@ -23,7 +23,7 @@ adi_project_create ad7616_sdz_zed
 if { $ad7616_if == 0 } {
 
   adi_project_files ad7616_sdz_zed [list \
-    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
     "system_top_si.v" \
     "serial_if_constr.xdc" \
     "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
@@ -31,7 +31,7 @@ if { $ad7616_if == 0 } {
 } elseif { $ad7616_if == 1 } {
 
   adi_project_files ad7616_sdz_zed [list \
-    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
     "system_top_pi.v" \
     "parallel_if_constr.xdc" \
     "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
diff --git a/projects/ad7768evb/zed/system_project.tcl b/projects/ad7768evb/zed/system_project.tcl
index 76d299860..3373673c1 100644
--- a/projects/ad7768evb/zed/system_project.tcl
+++ b/projects/ad7768evb/zed/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_files ad7768evb_zed [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" ]
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ]
 
 adi_project_run ad7768evb_zed
 
diff --git a/projects/ad9265_fmc/zc706/system_project.tcl b/projects/ad9265_fmc/zc706/system_project.tcl
index 17e5cab4e..92bce7ecf 100644
--- a/projects/ad9265_fmc/zc706/system_project.tcl
+++ b/projects/ad9265_fmc/zc706/system_project.tcl
@@ -8,7 +8,7 @@ adi_project_files ad9265_fmc_zc706 [list \
   "../common/ad9265_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
 
 adi_project_run ad9265_fmc_zc706
diff --git a/projects/ad9434_fmc/zc706/system_project.tcl b/projects/ad9434_fmc/zc706/system_project.tcl
index 090308c24..8014a0f5e 100644
--- a/projects/ad9434_fmc/zc706/system_project.tcl
+++ b/projects/ad9434_fmc/zc706/system_project.tcl
@@ -8,7 +8,7 @@ adi_project_files ad9434_fmc_zc706 [list \
   "../common/ad9434_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
 
 adi_project_run ad9434_fmc_zc706
diff --git a/projects/ad9467_fmc/kc705/system_project.tcl b/projects/ad9467_fmc/kc705/system_project.tcl
index 8e0368385..23c50fa2c 100644
--- a/projects/ad9467_fmc/kc705/system_project.tcl
+++ b/projects/ad9467_fmc/kc705/system_project.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create ad9467_fmc_kc705
 adi_project_files ad9467_fmc_kc705 [list \
   "../common/ad9467_spi.v" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc"]
diff --git a/projects/ad9467_fmc/zed/system_project.tcl b/projects/ad9467_fmc/zed/system_project.tcl
index 6e503e355..dfd7ca2ee 100644
--- a/projects/ad9467_fmc/zed/system_project.tcl
+++ b/projects/ad9467_fmc/zed/system_project.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create ad9467_fmc_zed
 adi_project_files ad9467_fmc_zed [list \
   "../common/ad9467_spi.v" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
diff --git a/projects/ad9739a_fmc/zc706/system_project.tcl b/projects/ad9739a_fmc/zc706/system_project.tcl
index f42d59f2c..4a681d17e 100644
--- a/projects/ad9739a_fmc/zc706/system_project.tcl
+++ b/projects/ad9739a_fmc/zc706/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ad9739a_fmc_zc706
 adi_project_files ad9739a_fmc_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
diff --git a/projects/adrv9371x/zc706/system_project.tcl b/projects/adrv9371x/zc706/system_project.tcl
index 3a9b054a9..183270edb 100644
--- a/projects/adrv9371x/zc706/system_project.tcl
+++ b/projects/adrv9371x/zc706/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create adrv9371x_zc706
 adi_project_files adrv9371x_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/adv7511/ac701/system_project.tcl b/projects/adv7511/ac701/system_project.tcl
index 0e7089508..053a42176 100644
--- a/projects/adv7511/ac701/system_project.tcl
+++ b/projects/adv7511/ac701/system_project.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create adv7511_ac701
 adi_project_files adv7511_ac701 [list \
   "system_top.v" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" \
   "$ad_hdl_dir/projects/adv7511/ac701/system_constr.xdc"]
 
diff --git a/projects/adv7511/kc705/system_project.tcl b/projects/adv7511/kc705/system_project.tcl
index 848ad356a..134972a38 100755
--- a/projects/adv7511/kc705/system_project.tcl
+++ b/projects/adv7511/kc705/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create adv7511_kc705
 adi_project_files adv7511_kc705 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
 adi_project_run adv7511_kc705
diff --git a/projects/adv7511/kcu105/system_project.tcl b/projects/adv7511/kcu105/system_project.tcl
index b66326b79..46799e383 100644
--- a/projects/adv7511/kcu105/system_project.tcl
+++ b/projects/adv7511/kcu105/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create adv7511_kcu105
 adi_project_files adv7511_kcu105 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
diff --git a/projects/adv7511/mitx045/system_project.tcl b/projects/adv7511/mitx045/system_project.tcl
index c6c812573..cb94ecb7d 100755
--- a/projects/adv7511/mitx045/system_project.tcl
+++ b/projects/adv7511/mitx045/system_project.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create adv7511_mitx045
 adi_project_files adv7511_mitx045 [list \
   "system_top.v" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc"]
 
 adi_project_run adv7511_mitx045
diff --git a/projects/adv7511/vc707/system_project.tcl b/projects/adv7511/vc707/system_project.tcl
index 90ce54fda..f1564ded2 100644
--- a/projects/adv7511/vc707/system_project.tcl
+++ b/projects/adv7511/vc707/system_project.tcl
@@ -5,7 +5,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project_create adv7511_vc707
 adi_project_files adv7511_vc707 [list \
-                  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+                  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
                   "system_top.v" \
                   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \
                   "$ad_hdl_dir/projects/adv7511/vc707/system_constr.xdc"]
diff --git a/projects/adv7511/zc702/system_project.tcl b/projects/adv7511/zc702/system_project.tcl
index 1f20c8ff0..01a7677c5 100644
--- a/projects/adv7511/zc702/system_project.tcl
+++ b/projects/adv7511/zc702/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create adv7511_zc702
 adi_project_files adv7511_zc702 [list \
   "system_top.v" \
   "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" ]
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ]
 
 adi_project_run adv7511_zc702
 
diff --git a/projects/adv7511/zc706/system_project.tcl b/projects/adv7511/zc706/system_project.tcl
index ffcd1819f..66167473f 100644
--- a/projects/adv7511/zc706/system_project.tcl
+++ b/projects/adv7511/zc706/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create adv7511_zc706
 adi_project_files adv7511_zc706 [list \
   "system_top.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v"]
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
 adi_project_run adv7511_zc706
 
diff --git a/projects/adv7511/zed/system_project.tcl b/projects/adv7511/zed/system_project.tcl
index a18cd7bf5..fc46b54e4 100644
--- a/projects/adv7511/zed/system_project.tcl
+++ b/projects/adv7511/zed/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create adv7511_zed
 adi_project_files adv7511_zed [list \
   "system_top.v" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v"]
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
 adi_project_run adv7511_zed
 
diff --git a/projects/cftl_cip/zed/system_project.tcl b/projects/cftl_cip/zed/system_project.tcl
index 7fd75f90c..7f66bf329 100644
--- a/projects/cftl_cip/zed/system_project.tcl
+++ b/projects/cftl_cip/zed/system_project.tcl
@@ -16,7 +16,7 @@ adi_project_files cftl_custom_zed [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v"]
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
 adi_project_run cftl_custom_zed
 
diff --git a/projects/cftl_std/zed/system_project.tcl b/projects/cftl_std/zed/system_project.tcl
index 8967736a9..f33858eef 100644
--- a/projects/cftl_std/zed/system_project.tcl
+++ b/projects/cftl_std/zed/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create cftl_std_zed
 adi_project_files cftl_std_zed [list \
   "system_top.v" \
   "system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
 
 adi_project_run cftl_std_zed
diff --git a/projects/cn0363/microzed/system_project.tcl b/projects/cn0363/microzed/system_project.tcl
index a66ba45b8..e56e42a4d 100644
--- a/projects/cn0363/microzed/system_project.tcl
+++ b/projects/cn0363/microzed/system_project.tcl
@@ -7,6 +7,6 @@ adi_project_files cn0363_microzed [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/microzed/microzed_system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v"]
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
 adi_project_run cn0363_microzed
diff --git a/projects/cn0363/zed/system_project.tcl b/projects/cn0363/zed/system_project.tcl
index 9aff54995..10baae44f 100644
--- a/projects/cn0363/zed/system_project.tcl
+++ b/projects/cn0363/zed/system_project.tcl
@@ -7,6 +7,6 @@ adi_project_files cn0363_zed [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v"]
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
 adi_project_run cn0363_zed
diff --git a/projects/daq1/zc706/system_project.tcl b/projects/daq1/zc706/system_project.tcl
index b468be7db..f38fb7b99 100644
--- a/projects/daq1/zc706/system_project.tcl
+++ b/projects/daq1/zc706/system_project.tcl
@@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create daq1_zc706
 adi_project_files daq1_zc706 [list \
   "../common/daq1_spi.v" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
diff --git a/projects/daq2/kc705/system_project.tcl b/projects/daq2/kc705/system_project.tcl
index 41d22923e..4e352bf38 100644
--- a/projects/daq2/kc705/system_project.tcl
+++ b/projects/daq2/kc705/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files daq2_kc705 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc]
diff --git a/projects/daq2/kcu105/system_project.tcl b/projects/daq2/kcu105/system_project.tcl
index 5d2541fd6..45db50cd7 100644
--- a/projects/daq2/kcu105/system_project.tcl
+++ b/projects/daq2/kcu105/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files daq2_kcu105 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
diff --git a/projects/daq2/vc707/system_project.tcl b/projects/daq2/vc707/system_project.tcl
index cff763141..d37dabbd3 100644
--- a/projects/daq2/vc707/system_project.tcl
+++ b/projects/daq2/vc707/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files daq2_vc707 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
diff --git a/projects/daq2/zc706/system_project.tcl b/projects/daq2/zc706/system_project.tcl
index 8d6209938..ba06bf649 100644
--- a/projects/daq2/zc706/system_project.tcl
+++ b/projects/daq2/zc706/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files daq2_zc706 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/daq3/kcu105/system_project.tcl b/projects/daq3/kcu105/system_project.tcl
index 1d0b428b7..db5948939 100644
--- a/projects/daq3/kcu105/system_project.tcl
+++ b/projects/daq3/kcu105/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files daq3_kcu105 [list \
   "../common/daq3_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
diff --git a/projects/daq3/zc706/system_project.tcl b/projects/daq3/zc706/system_project.tcl
index 1d91ac442..cd6094f43 100644
--- a/projects/daq3/zc706/system_project.tcl
+++ b/projects/daq3/zc706/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files daq3_zc706 [list \
   "../common/daq3_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/fmcadc2/vc707/system_project.tcl b/projects/fmcadc2/vc707/system_project.tcl
index cdbb502bc..b19774007 100644
--- a/projects/fmcadc2/vc707/system_project.tcl
+++ b/projects/fmcadc2/vc707/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files fmcadc2_vc707 [list \
   "../common/fmcadc2_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
diff --git a/projects/fmcadc2/zc706/system_project.tcl b/projects/fmcadc2/zc706/system_project.tcl
index 406afe7d3..af5a50cb7 100644
--- a/projects/fmcadc2/zc706/system_project.tcl
+++ b/projects/fmcadc2/zc706/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files fmcadc2_zc706 [list \
   "../common/fmcadc2_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/fmcadc4/zc706/system_project.tcl b/projects/fmcadc4/zc706/system_project.tcl
index d14bc56c9..787434877 100644
--- a/projects/fmcadc4/zc706/system_project.tcl
+++ b/projects/fmcadc4/zc706/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files fmcadc4_zc706 [list \
   "../common/fmcadc4_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/fmcadc5/vc707/system_project.tcl b/projects/fmcadc5/vc707/system_project.tcl
index 8611d77cf..f9297c0ed 100644
--- a/projects/fmcadc5/vc707/system_project.tcl
+++ b/projects/fmcadc5/vc707/system_project.tcl
@@ -11,8 +11,8 @@ adi_project_files fmcadc5_vc707 [list \
   "../common/fmcadc5_psync.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/library/common/ad_lvds_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
diff --git a/projects/fmcjesdadc1/kc705/system_project.tcl b/projects/fmcjesdadc1/kc705/system_project.tcl
index f5c371353..3b094ef0e 100644
--- a/projects/fmcjesdadc1/kc705/system_project.tcl
+++ b/projects/fmcjesdadc1/kc705/system_project.tcl
@@ -8,7 +8,7 @@ adi_project_files fmcjesdadc1_kc705 [list \
   "../common/fmcjesdadc1_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
diff --git a/projects/fmcjesdadc1/vc707/system_project.tcl b/projects/fmcjesdadc1/vc707/system_project.tcl
index 07b5f24af..64689dc0e 100644
--- a/projects/fmcjesdadc1/vc707/system_project.tcl
+++ b/projects/fmcjesdadc1/vc707/system_project.tcl
@@ -5,7 +5,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project_create fmcjesdadc1_vc707
 adi_project_files fmcjesdadc1_vc707 [list \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "../common/fmcjesdadc1_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
diff --git a/projects/fmcjesdadc1/zc706/system_project.tcl b/projects/fmcjesdadc1/zc706/system_project.tcl
index 28443abc5..8d06f1806 100644
--- a/projects/fmcjesdadc1/zc706/system_project.tcl
+++ b/projects/fmcjesdadc1/zc706/system_project.tcl
@@ -7,7 +7,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project_create fmcjesdadc1_zc706
 adi_project_files fmcjesdadc1_zc706 [list \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "../common/fmcjesdadc1_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
diff --git a/projects/fmcomms1/ac701/system_project.tcl b/projects/fmcomms1/ac701/system_project.tcl
index 6ee52d1ad..c41bf1b5d 100644
--- a/projects/fmcomms1/ac701/system_project.tcl
+++ b/projects/fmcomms1/ac701/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms1_ac701
 adi_project_files fmcomms1_ac701 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc]
diff --git a/projects/fmcomms1/kc705/system_project.tcl b/projects/fmcomms1/kc705/system_project.tcl
index 1c30388e3..34362a542 100644
--- a/projects/fmcomms1/kc705/system_project.tcl
+++ b/projects/fmcomms1/kc705/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms1_kc705
 adi_project_files fmcomms1_kc705 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc]
diff --git a/projects/fmcomms1/vc707/system_project.tcl b/projects/fmcomms1/vc707/system_project.tcl
index bebf0029a..4ab9b41b3 100644
--- a/projects/fmcomms1/vc707/system_project.tcl
+++ b/projects/fmcomms1/vc707/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms1_vc707
 adi_project_files fmcomms1_vc707 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
diff --git a/projects/fmcomms1/zc702/system_project.tcl b/projects/fmcomms1/zc702/system_project.tcl
index 2f78a58d1..fc13dc6d2 100644
--- a/projects/fmcomms1/zc702/system_project.tcl
+++ b/projects/fmcomms1/zc702/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms1_zc702
 adi_project_files fmcomms1_zc702 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc]
diff --git a/projects/fmcomms1/zc706/system_project.tcl b/projects/fmcomms1/zc706/system_project.tcl
index fcfd9048d..f104736d4 100644
--- a/projects/fmcomms1/zc706/system_project.tcl
+++ b/projects/fmcomms1/zc706/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms1_zc706
 adi_project_files fmcomms1_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
diff --git a/projects/fmcomms1/zed/system_project.tcl b/projects/fmcomms1/zed/system_project.tcl
index 5bf10f8dc..1e5eb5bd0 100644
--- a/projects/fmcomms1/zed/system_project.tcl
+++ b/projects/fmcomms1/zed/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms1_zed
 adi_project_files fmcomms1_zed [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zed/zed_system_constr.xdc]
diff --git a/projects/fmcomms11/zc706/system_project.tcl b/projects/fmcomms11/zc706/system_project.tcl
index f9b1c39a7..d0c5093df 100644
--- a/projects/fmcomms11/zc706/system_project.tcl
+++ b/projects/fmcomms11/zc706/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files fmcomms11_zc706 [list \
   "../common/fmcomms11_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/fmcomms2/ac701/system_project.tcl b/projects/fmcomms2/ac701/system_project.tcl
index b7a5bf4cd..9338fd190 100644
--- a/projects/fmcomms2/ac701/system_project.tcl
+++ b/projects/fmcomms2/ac701/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms2_ac701
 adi_project_files fmcomms2_ac701 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
 
 adi_project_run fmcomms2_ac701
diff --git a/projects/fmcomms2/kc705/system_project.tcl b/projects/fmcomms2/kc705/system_project.tcl
index aef268c03..aaf3ee949 100644
--- a/projects/fmcomms2/kc705/system_project.tcl
+++ b/projects/fmcomms2/kc705/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms2_kc705
 adi_project_files fmcomms2_kc705 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
 adi_project_run fmcomms2_kc705
diff --git a/projects/fmcomms2/mitx045/system_project.tcl b/projects/fmcomms2/mitx045/system_project.tcl
index 405d74069..4a6eeeb60 100755
--- a/projects/fmcomms2/mitx045/system_project.tcl
+++ b/projects/fmcomms2/mitx045/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms2_mitx045
 adi_project_files fmcomms2_mitx045 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc" ]
 
 adi_project_run fmcomms2_mitx045
diff --git a/projects/fmcomms2/vc707/system_project.tcl b/projects/fmcomms2/vc707/system_project.tcl
index 1176ef25b..40d68552c 100644
--- a/projects/fmcomms2/vc707/system_project.tcl
+++ b/projects/fmcomms2/vc707/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create fmcomms2_vc707
 adi_project_files fmcomms2_vc707 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
diff --git a/projects/fmcomms2/zc702/system_project.tcl b/projects/fmcomms2/zc702/system_project.tcl
index 485686110..6bf5f0282 100644
--- a/projects/fmcomms2/zc702/system_project.tcl
+++ b/projects/fmcomms2/zc702/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms2_zc702
 adi_project_files fmcomms2_zc702 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
 
 adi_project_run fmcomms2_zc702
diff --git a/projects/fmcomms2/zc706/system_project.tcl b/projects/fmcomms2/zc706/system_project.tcl
index 68b41d86f..09b56d4c5 100755
--- a/projects/fmcomms2/zc706/system_project.tcl
+++ b/projects/fmcomms2/zc706/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create fmcomms2_zc706
 adi_project_files fmcomms2_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 adi_project_run fmcomms2_zc706
diff --git a/projects/fmcomms2/zc706pr/system_project.tcl b/projects/fmcomms2/zc706pr/system_project.tcl
index 89e9c90c5..2202cb71e 100755
--- a/projects/fmcomms2/zc706pr/system_project.tcl
+++ b/projects/fmcomms2/zc706pr/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create fmcomms2_zc706 1
 adi_project_synth fmcomms2_zc706 "" \
   [list "system_top.v" \
   "../common/prcfg_bb.v" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v"] \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] \
   [list "../zc706/system_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
 
diff --git a/projects/fmcomms2/zcu102/system_project.tcl b/projects/fmcomms2/zcu102/system_project.tcl
index 6997e3d28..b11579292 100755
--- a/projects/fmcomms2/zcu102/system_project.tcl
+++ b/projects/fmcomms2/zcu102/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create fmcomms2_zcu102
 adi_project_files fmcomms2_zcu102 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
 
 adi_project_run fmcomms2_zcu102
diff --git a/projects/fmcomms2/zed/system_project.tcl b/projects/fmcomms2/zed/system_project.tcl
index 330fca68a..a5e387142 100644
--- a/projects/fmcomms2/zed/system_project.tcl
+++ b/projects/fmcomms2/zed/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms2_zed
 adi_project_files fmcomms2_zed [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
 
 adi_project_run fmcomms2_zed
diff --git a/projects/fmcomms5/zc702/system_project.tcl b/projects/fmcomms5/zc702/system_project.tcl
index f56d13e91..6f65a412b 100644
--- a/projects/fmcomms5/zc702/system_project.tcl
+++ b/projects/fmcomms5/zc702/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create fmcomms5_zc702
 adi_project_files fmcomms5_zc702 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
 
 adi_project_run fmcomms5_zc702
diff --git a/projects/fmcomms5/zc706/system_project.tcl b/projects/fmcomms5/zc706/system_project.tcl
index a791c0266..169ab7abb 100644
--- a/projects/fmcomms5/zc706/system_project.tcl
+++ b/projects/fmcomms5/zc706/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create fmcomms5_zc706
 adi_project_files fmcomms5_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 adi_project_run fmcomms5_zc706
diff --git a/projects/fmcomms6/zc706/system_project.tcl b/projects/fmcomms6/zc706/system_project.tcl
index 6be65ff55..0ebcebd0d 100644
--- a/projects/fmcomms6/zc706/system_project.tcl
+++ b/projects/fmcomms6/zc706/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files fmcomms6_zc706 [list \
   "../common/fmcomms6_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
diff --git a/projects/fmcomms7/zc706/system_project.tcl b/projects/fmcomms7/zc706/system_project.tcl
index 06c3ab354..35fd66fb5 100644
--- a/projects/fmcomms7/zc706/system_project.tcl
+++ b/projects/fmcomms7/zc706/system_project.tcl
@@ -10,7 +10,7 @@ adi_project_files fmcomms7_zc706 [list \
   "../common/fmcomms7_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/imageon/zc706/system_project.tcl b/projects/imageon/zc706/system_project.tcl
index 32c416aae..6f00db4d7 100644
--- a/projects/imageon/zc706/system_project.tcl
+++ b/projects/imageon/zc706/system_project.tcl
@@ -7,7 +7,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create imageon_zc706
 adi_project_files imageon_zc706 [list \
   "system_top.v" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "system_constr.xdc" ]
 
 adi_project_run imageon_zc706
diff --git a/projects/imageon/zed/system_project.tcl b/projects/imageon/zed/system_project.tcl
index a8cb06bc1..52944cc17 100644
--- a/projects/imageon/zed/system_project.tcl
+++ b/projects/imageon/zed/system_project.tcl
@@ -7,7 +7,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create imageon_zed
 adi_project_files imageon_zed [list \
   "system_top.v" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "system_constr.xdc"]
 
 adi_project_run imageon_zed
diff --git a/projects/motcon2_fmc/zed/system_project.tcl b/projects/motcon2_fmc/zed/system_project.tcl
index 65d0b6233..7772b1862 100755
--- a/projects/motcon2_fmc/zed/system_project.tcl
+++ b/projects/motcon2_fmc/zed/system_project.tcl
@@ -7,7 +7,7 @@ adi_project_create motcon2_fmc_zed
 adi_project_files motcon2_fmc_zed [list \
   "system_top.v" \
   "system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
diff --git a/projects/pzsdr/ccbrk/system_project.tcl b/projects/pzsdr/ccbrk/system_project.tcl
index 72cf71fed..1aabab6f4 100644
--- a/projects/pzsdr/ccbrk/system_project.tcl
+++ b/projects/pzsdr/ccbrk/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ccbrk_pzsdr
 adi_project_files ccbrk_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
diff --git a/projects/pzsdr/ccbrk_cmos/system_project.tcl b/projects/pzsdr/ccbrk_cmos/system_project.tcl
index f32906815..fc22d310b 100644
--- a/projects/pzsdr/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr/ccbrk_cmos/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ccbrk_cmos_pzsdr
 adi_project_files ccbrk_cmos_pzsdr [list \
   "system_top.v" \
   "../ccbrk/system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc" ]
diff --git a/projects/pzsdr/ccfmc/system_project.tcl b/projects/pzsdr/ccfmc/system_project.tcl
index 7c1d7075e..5550de22b 100644
--- a/projects/pzsdr/ccfmc/system_project.tcl
+++ b/projects/pzsdr/ccfmc/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ccfmc_pzsdr
 adi_project_files ccfmc_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
diff --git a/projects/pzsdr/ccpci/system_project.tcl b/projects/pzsdr/ccpci/system_project.tcl
index 10d4a8281..8c9076c3a 100644
--- a/projects/pzsdr/ccpci/system_project.tcl
+++ b/projects/pzsdr/ccpci/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ccpci_pzsdr
 adi_project_files ccpci_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
diff --git a/projects/pzsdr1/ccbrk/system_project.tcl b/projects/pzsdr1/ccbrk/system_project.tcl
index 304860343..046012886 100644
--- a/projects/pzsdr1/ccbrk/system_project.tcl
+++ b/projects/pzsdr1/ccbrk/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ccbrk_pzsdr1
 adi_project_files ccbrk_pzsdr1 [list \
   "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
 
diff --git a/projects/pzsdr1/ccbrk_cmos/system_project.tcl b/projects/pzsdr1/ccbrk_cmos/system_project.tcl
index e251c533c..45d3a4c8d 100644
--- a/projects/pzsdr1/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr1/ccbrk_cmos/system_project.tcl
@@ -9,7 +9,7 @@ adi_project_create ccbrk_cmos_pzsdr1
 adi_project_files ccbrk_cmos_pzsdr1 [list \
   "system_top.v" \
   "../ccbrk/system_constr.xdc"\
-  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc" ]
 
diff --git a/projects/usb_fx3/zc706/system_project.tcl b/projects/usb_fx3/zc706/system_project.tcl
index 8bfc00965..01174c14f 100644
--- a/projects/usb_fx3/zc706/system_project.tcl
+++ b/projects/usb_fx3/zc706/system_project.tcl
@@ -8,7 +8,7 @@ adi_project_files usb_fx3_zc706 [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
-  "$ad_hdl_dir/library/common/ad_iobuf.v"]
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
 adi_project_run usb_fx3_zc706
 

From 1d33d7d7ee4f2f8241239d8241c6979461fe466a Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 8 Aug 2016 13:26:34 +0300
Subject: [PATCH 382/972] lib_refactoring: Move the CMOS interface modules to
 ~/library/xilinx/common

---
 library/{ => xilinx}/common/ad_cmos_clk.v | 0
 library/{ => xilinx}/common/ad_cmos_in.v  | 0
 library/{ => xilinx}/common/ad_cmos_out.v | 0
 3 files changed, 0 insertions(+), 0 deletions(-)
 rename library/{ => xilinx}/common/ad_cmos_clk.v (100%)
 rename library/{ => xilinx}/common/ad_cmos_in.v (100%)
 rename library/{ => xilinx}/common/ad_cmos_out.v (100%)

diff --git a/library/common/ad_cmos_clk.v b/library/xilinx/common/ad_cmos_clk.v
similarity index 100%
rename from library/common/ad_cmos_clk.v
rename to library/xilinx/common/ad_cmos_clk.v
diff --git a/library/common/ad_cmos_in.v b/library/xilinx/common/ad_cmos_in.v
similarity index 100%
rename from library/common/ad_cmos_in.v
rename to library/xilinx/common/ad_cmos_in.v
diff --git a/library/common/ad_cmos_out.v b/library/xilinx/common/ad_cmos_out.v
similarity index 100%
rename from library/common/ad_cmos_out.v
rename to library/xilinx/common/ad_cmos_out.v

From aad8c265bc5efec148c91ce02a9cd76c6c24bc60 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 8 Aug 2016 13:46:34 +0300
Subject: [PATCH 383/972] lib_refactoring: Fix path for CMOS sources

---
 library/axi_ad9361/axi_ad9361_ip.tcl | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl
index 1e8b1a2be..f18ba9d09 100755
--- a/library/axi_ad9361/axi_ad9361_ip.tcl
+++ b/library/axi_ad9361/axi_ad9361_ip.tcl
@@ -10,9 +10,9 @@ adi_ip_files axi_ad9361 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
-  "$ad_hdl_dir/library/common/ad_cmos_clk.v" \
-  "$ad_hdl_dir/library/common/ad_cmos_in.v" \
-  "$ad_hdl_dir/library/common/ad_cmos_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_cmos_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_cmos_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_cmos_out.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \

From 0cd608a7e236528f763a4f3e2c63145d86989c25 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 8 Aug 2016 13:47:16 +0300
Subject: [PATCH 384/972] lib_refactoring: Update Make files

---
 library/axi_ad9122/Makefile         |  8 ++++----
 library/axi_ad9144/Makefile         |  2 +-
 library/axi_ad9152/Makefile         |  2 +-
 library/axi_ad9162/Makefile         |  2 +-
 library/axi_ad9265/Makefile         |  4 ++--
 library/axi_ad9361/Makefile         | 14 +++++++-------
 library/axi_ad9371/Makefile         |  2 +-
 library/axi_ad9434/Makefile         |  6 +++---
 library/axi_ad9467/Makefile         |  4 ++--
 library/axi_ad9643/Makefile         |  6 +++---
 library/axi_ad9652/Makefile         |  6 +++---
 library/axi_ad9684/Makefile         |  6 +++---
 library/axi_ad9739a/Makefile        |  4 ++--
 library/axi_clkgen/Makefile         |  2 +-
 projects/ad6676evb/vc707/Makefile   |  2 +-
 projects/ad6676evb/zc706/Makefile   |  2 +-
 projects/ad7616_sdz/zc706/Makefile  |  4 ++--
 projects/ad7616_sdz/zed/Makefile    |  4 ++--
 projects/ad7768evb/zed/Makefile     |  2 +-
 projects/ad9265_fmc/zc706/Makefile  |  2 +-
 projects/ad9434_fmc/zc706/Makefile  |  2 +-
 projects/ad9467_fmc/kc705/Makefile  |  2 +-
 projects/ad9467_fmc/zed/Makefile    |  2 +-
 projects/ad9739a_fmc/zc706/Makefile |  2 +-
 projects/adrv9371x/a10soc/Makefile  |  4 +---
 projects/adrv9371x/zc706/Makefile   |  2 +-
 projects/adv7511/ac701/Makefile     |  2 +-
 projects/adv7511/kc705/Makefile     |  2 +-
 projects/adv7511/kcu105/Makefile    |  2 +-
 projects/adv7511/mitx045/Makefile   |  2 +-
 projects/adv7511/vc707/Makefile     |  2 +-
 projects/adv7511/zc702/Makefile     |  2 +-
 projects/adv7511/zc706/Makefile     |  2 +-
 projects/adv7511/zed/Makefile       |  2 +-
 projects/arradio/c5soc/Makefile     | 17 +++++++----------
 projects/cftl_cip/zed/Makefile      |  2 +-
 projects/cftl_std/zed/Makefile      |  2 +-
 projects/cn0363/microzed/Makefile   |  2 +-
 projects/cn0363/zed/Makefile        |  2 +-
 projects/daq1/zc706/Makefile        |  2 +-
 projects/daq2/a10gx/Makefile        |  4 +---
 projects/daq2/kc705/Makefile        |  2 +-
 projects/daq2/kcu105/Makefile       |  2 +-
 projects/daq2/vc707/Makefile        |  2 +-
 projects/daq2/zc706/Makefile        |  2 +-
 projects/daq3/a10gx/Makefile        |  3 +--
 projects/daq3/kcu105/Makefile       |  2 +-
 projects/daq3/zc706/Makefile        |  2 +-
 projects/fmcadc2/vc707/Makefile     |  2 +-
 projects/fmcadc2/zc706/Makefile     |  2 +-
 projects/fmcadc4/zc706/Makefile     |  2 +-
 projects/fmcadc5/vc707/Makefile     |  4 ++--
 projects/fmcjesdadc1/a5gt/Makefile  |  1 -
 projects/fmcjesdadc1/a5soc/Makefile |  1 -
 projects/fmcjesdadc1/kc705/Makefile |  2 +-
 projects/fmcjesdadc1/vc707/Makefile |  2 +-
 projects/fmcjesdadc1/zc706/Makefile |  2 +-
 projects/fmcomms1/ac701/Makefile    |  2 +-
 projects/fmcomms1/kc705/Makefile    |  2 +-
 projects/fmcomms1/vc707/Makefile    |  2 +-
 projects/fmcomms1/zc702/Makefile    |  2 +-
 projects/fmcomms1/zc706/Makefile    |  2 +-
 projects/fmcomms1/zed/Makefile      |  2 +-
 projects/fmcomms11/zc706/Makefile   |  2 +-
 projects/fmcomms2/a10gx/Makefile    | 16 +++++++---------
 projects/fmcomms2/ac701/Makefile    |  2 +-
 projects/fmcomms2/kc705/Makefile    |  2 +-
 projects/fmcomms2/mitx045/Makefile  |  2 +-
 projects/fmcomms2/vc707/Makefile    |  2 +-
 projects/fmcomms2/zc702/Makefile    |  2 +-
 projects/fmcomms2/zc706/Makefile    |  2 +-
 projects/fmcomms2/zcu102/Makefile   |  2 +-
 projects/fmcomms2/zed/Makefile      |  2 +-
 projects/fmcomms5/zc702/Makefile    |  2 +-
 projects/fmcomms5/zc706/Makefile    |  2 +-
 projects/fmcomms6/zc706/Makefile    |  2 +-
 projects/fmcomms7/zc706/Makefile    |  2 +-
 projects/imageon/zc706/Makefile     |  2 +-
 projects/imageon/zed/Makefile       |  2 +-
 projects/motcon2_fmc/zed/Makefile   |  2 +-
 projects/pzsdr/ccbrk/Makefile       |  3 ++-
 projects/pzsdr/ccbrk_cmos/Makefile  |  3 ++-
 projects/pzsdr/ccfmc/Makefile       |  3 ++-
 projects/pzsdr/ccpci/Makefile       |  2 +-
 projects/pzsdr1/ccbrk/Makefile      |  2 +-
 projects/pzsdr1/ccbrk_cmos/Makefile |  2 +-
 projects/usb_fx3/zc706/Makefile     |  2 +-
 87 files changed, 123 insertions(+), 132 deletions(-)

diff --git a/library/axi_ad9122/Makefile b/library/axi_ad9122/Makefile
index cf6dc7c0b..d4ede90f8 100644
--- a/library/axi_ad9122/Makefile
+++ b/library/axi_ad9122/Makefile
@@ -8,14 +8,14 @@
 M_DEPS := axi_ad9122_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_mmcm_drp.v
-M_DEPS += ../common/ad_serdes_out.v
-M_DEPS += ../common/ad_serdes_clk.v
+M_DEPS += ../xilinx/common/ad_mmcm_drp.v
+M_DEPS += ../xilinx/common/ad_serdes_out.v
+M_DEPS += ../xilinx/common/ad_serdes_clk.v
 M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
diff --git a/library/axi_ad9144/Makefile b/library/axi_ad9144/Makefile
index 1a62aaee0..79c695e2c 100644
--- a/library/axi_ad9144/Makefile
+++ b/library/axi_ad9144/Makefile
@@ -9,7 +9,7 @@ M_DEPS := axi_ad9144_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
diff --git a/library/axi_ad9152/Makefile b/library/axi_ad9152/Makefile
index 70ef37ad3..ae659d94a 100644
--- a/library/axi_ad9152/Makefile
+++ b/library/axi_ad9152/Makefile
@@ -9,7 +9,7 @@ M_DEPS := axi_ad9152_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
diff --git a/library/axi_ad9162/Makefile b/library/axi_ad9162/Makefile
index 73919d834..ac071973d 100644
--- a/library/axi_ad9162/Makefile
+++ b/library/axi_ad9162/Makefile
@@ -9,7 +9,7 @@ M_DEPS := axi_ad9162_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
diff --git a/library/axi_ad9265/Makefile b/library/axi_ad9265/Makefile
index 6f6e07c31..bbff12cb5 100644
--- a/library/axi_ad9265/Makefile
+++ b/library/axi_ad9265/Makefile
@@ -9,8 +9,8 @@ M_DEPS := axi_ad9265_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_lvds_clk.v
-M_DEPS += ../common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_dcfilter.v
 M_DEPS += ../common/ad_pnmon.v
diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile
index 05640fc36..7752839e6 100644
--- a/library/axi_ad9361/Makefile
+++ b/library/axi_ad9361/Makefile
@@ -10,13 +10,13 @@ M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_lvds_clk.v
-M_DEPS += ../common/ad_lvds_in.v
-M_DEPS += ../common/ad_lvds_out.v
-M_DEPS += ../common/ad_cmos_clk.v
-M_DEPS += ../common/ad_cmos_in.v
-M_DEPS += ../common/ad_cmos_out.v
-M_DEPS += ../common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_lvds_out.v
+M_DEPS += ../xilinx/common/ad_cmos_clk.v
+M_DEPS += ../xilinx/common/ad_cmos_in.v
+M_DEPS += ../xilinx/common/ad_cmos_out.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += ../common/ad_pnmon.v
 M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_dds_1.v
diff --git a/library/axi_ad9371/Makefile b/library/axi_ad9371/Makefile
index bad4b3154..3dd9fb20c 100644
--- a/library/axi_ad9371/Makefile
+++ b/library/axi_ad9371/Makefile
@@ -10,7 +10,7 @@ M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
diff --git a/library/axi_ad9434/Makefile b/library/axi_ad9434/Makefile
index e9d7ef4de..b924b1398 100644
--- a/library/axi_ad9434/Makefile
+++ b/library/axi_ad9434/Makefile
@@ -8,9 +8,9 @@
 M_DEPS := axi_ad9434_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_serdes_clk.v
-M_DEPS += ../common/ad_mmcm_drp.v
-M_DEPS += ../common/ad_serdes_in.v
+M_DEPS += ../xilinx/common/ad_serdes_clk.v
+M_DEPS += ../xilinx/common/ad_mmcm_drp.v
+M_DEPS += ../xilinx/common/ad_serdes_in.v
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_rst.v
 M_DEPS += ../common/up_xfer_cntrl.v
diff --git a/library/axi_ad9467/Makefile b/library/axi_ad9467/Makefile
index 940dc400f..649976a9e 100644
--- a/library/axi_ad9467/Makefile
+++ b/library/axi_ad9467/Makefile
@@ -9,8 +9,8 @@ M_DEPS := axi_ad9467_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_lvds_clk.v
-M_DEPS += ../common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_pnmon.v
 M_DEPS += ../common/up_xfer_status.v
diff --git a/library/axi_ad9643/Makefile b/library/axi_ad9643/Makefile
index 44ca7a684..834b235cc 100644
--- a/library/axi_ad9643/Makefile
+++ b/library/axi_ad9643/Makefile
@@ -9,9 +9,9 @@ M_DEPS := axi_ad9643_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_mul.v
-M_DEPS += ../common/ad_lvds_clk.v
-M_DEPS += ../common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
 M_DEPS += ../common/ad_pnmon.v
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_dcfilter.v
diff --git a/library/axi_ad9652/Makefile b/library/axi_ad9652/Makefile
index 478c0f50e..6a12efda9 100644
--- a/library/axi_ad9652/Makefile
+++ b/library/axi_ad9652/Makefile
@@ -9,9 +9,9 @@ M_DEPS := axi_ad9652_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_mul.v
-M_DEPS += ../common/ad_lvds_clk.v
-M_DEPS += ../common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
 M_DEPS += ../common/ad_pnmon.v
 M_DEPS += ../common/ad_dcfilter.v
 M_DEPS += ../common/ad_iqcor.v
diff --git a/library/axi_ad9684/Makefile b/library/axi_ad9684/Makefile
index 3f25f512f..4754a0f74 100644
--- a/library/axi_ad9684/Makefile
+++ b/library/axi_ad9684/Makefile
@@ -9,9 +9,9 @@ M_DEPS := axi_ad9684_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_serdes_in.v
-M_DEPS += ../common/ad_serdes_clk.v
-M_DEPS += ../common/ad_mmcm_drp.v
+M_DEPS += ../xilinx/common/ad_serdes_in.v
+M_DEPS += ../xilinx/common/ad_serdes_clk.v
+M_DEPS += ../xilinx/common/ad_mmcm_drp.v
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_pnmon.v
 M_DEPS += ../common/up_xfer_status.v
diff --git a/library/axi_ad9739a/Makefile b/library/axi_ad9739a/Makefile
index 43e235827..0728a461e 100644
--- a/library/axi_ad9739a/Makefile
+++ b/library/axi_ad9739a/Makefile
@@ -8,12 +8,12 @@
 M_DEPS := axi_ad9739a_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_serdes_out.v
+M_DEPS += ../xilinx/common/ad_serdes_out.v
 M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
diff --git a/library/axi_clkgen/Makefile b/library/axi_clkgen/Makefile
index 0a1f03758..2936da44b 100644
--- a/library/axi_clkgen/Makefile
+++ b/library/axi_clkgen/Makefile
@@ -9,7 +9,7 @@ M_DEPS := axi_clkgen_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_mmcm_drp.v
+M_DEPS += ../xilinx/common/ad_mmcm_drp.v
 M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_clkgen.v
 M_DEPS += axi_clkgen_constr.xdc
diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile
index 616d1df47..f37c1c0ef 100644
--- a/projects/ad6676evb/vc707/Makefile
+++ b/projects/ad6676evb/vc707/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile
index 2320d034e..149104d87 100644
--- a/projects/ad6676evb/zc706/Makefile
+++ b/projects/ad6676evb/zc706/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile
index 8494dd0dd..29e53e7d3 100644
--- a/projects/ad7616_sdz/zc706/Makefile
+++ b/projects/ad7616_sdz/zc706/Makefile
@@ -18,8 +18,8 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile
index 5bd037042..4b61c5ee4 100644
--- a/projects/ad7616_sdz/zed/Makefile
+++ b/projects/ad7616_sdz/zed/Makefile
@@ -18,8 +18,8 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/ad7768evb/zed/Makefile b/projects/ad7768evb/zed/Makefile
index f84f18dfb..c15c5a91f 100644
--- a/projects/ad7768evb/zed/Makefile
+++ b/projects/ad7768evb/zed/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
diff --git a/projects/ad9265_fmc/zc706/Makefile b/projects/ad9265_fmc/zc706/Makefile
index a6e129bf2..e51b8b86c 100644
--- a/projects/ad9265_fmc/zc706/Makefile
+++ b/projects/ad9265_fmc/zc706/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9265/axi_ad9265.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/ad9434_fmc/zc706/Makefile b/projects/ad9434_fmc/zc706/Makefile
index 134da3761..e47d747f9 100644
--- a/projects/ad9434_fmc/zc706/Makefile
+++ b/projects/ad9434_fmc/zc706/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9434/axi_ad9434.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/ad9467_fmc/kc705/Makefile b/projects/ad9467_fmc/kc705/Makefile
index 3d35cdf62..1287d339f 100644
--- a/projects/ad9467_fmc/kc705/Makefile
+++ b/projects/ad9467_fmc/kc705/Makefile
@@ -17,7 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/kc705/kc705_system_mig.prj
 M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9467/axi_ad9467.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 
diff --git a/projects/ad9467_fmc/zed/Makefile b/projects/ad9467_fmc/zed/Makefile
index b7166bd48..e986af978 100644
--- a/projects/ad9467_fmc/zed/Makefile
+++ b/projects/ad9467_fmc/zed/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9467/axi_ad9467.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/ad9739a_fmc/zc706/Makefile b/projects/ad9739a_fmc/zc706/Makefile
index 22fabd30a..c7ff8e8ac 100644
--- a/projects/ad9739a_fmc/zc706/Makefile
+++ b/projects/ad9739a_fmc/zc706/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9739a/axi_ad9739a.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 652c17457..2870fb421 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -13,6 +13,7 @@ M_DEPS += ../common/adrv9371x_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
+M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v
@@ -49,10 +50,7 @@ M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_jesd_align.v
-M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_rst.v
-M_DEPS += ../../../library/common/altera/DSP48E1.v
-M_DEPS += ../../../library/common/altera/MULT_MACRO.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
 M_DEPS += ../../../library/common/up_adc_channel.v
diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
index 75c8ccb71..f02d31df9 100644
--- a/projects/adrv9371x/zc706/Makefile
+++ b/projects/adrv9371x/zc706/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile
index 3e7747eed..a6c78b927 100644
--- a/projects/adv7511/ac701/Makefile
+++ b/projects/adv7511/ac701/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../common/ac701/ac701_system_constr.xdc
 M_DEPS += ../../common/ac701/ac701_system_bd.tcl
 M_DEPS += ../../adv7511/common/adv7511_bd.tcl
 M_DEPS += ../../adv7511/ac701/system_constr.xdc
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
diff --git a/projects/adv7511/kc705/Makefile b/projects/adv7511/kc705/Makefile
index 9f1e38602..0700ae64e 100644
--- a/projects/adv7511/kc705/Makefile
+++ b/projects/adv7511/kc705/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../common/kc705/kc705_system_mig.prj
 M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
 M_DEPS += ../../adv7511/common/adv7511_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile
index a8f1a08fe..7d0d0e89f 100644
--- a/projects/adv7511/kcu105/Makefile
+++ b/projects/adv7511/kcu105/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile
index 1701121f8..20e6df52c 100644
--- a/projects/adv7511/mitx045/Makefile
+++ b/projects/adv7511/mitx045/Makefile
@@ -14,7 +14,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/mitx045/mitx045_system_ps7.tcl
 M_DEPS += ../../common/mitx045/mitx045_system_constr.xdc
 M_DEPS += ../../common/mitx045/mitx045_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
diff --git a/projects/adv7511/vc707/Makefile b/projects/adv7511/vc707/Makefile
index f809d5bd5..01f33d999 100644
--- a/projects/adv7511/vc707/Makefile
+++ b/projects/adv7511/vc707/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../adv7511/vc707/system_constr.xdc
 M_DEPS += ../../adv7511/common/adv7511_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
diff --git a/projects/adv7511/zc702/Makefile b/projects/adv7511/zc702/Makefile
index 961410265..71f192a50 100644
--- a/projects/adv7511/zc702/Makefile
+++ b/projects/adv7511/zc702/Makefile
@@ -13,7 +13,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc702/zc702_system_constr.xdc
 M_DEPS += ../../common/zc702/zc702_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
diff --git a/projects/adv7511/zc706/Makefile b/projects/adv7511/zc706/Makefile
index 1ff02713a..65085d55b 100644
--- a/projects/adv7511/zc706/Makefile
+++ b/projects/adv7511/zc706/Makefile
@@ -13,7 +13,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
diff --git a/projects/adv7511/zed/Makefile b/projects/adv7511/zed/Makefile
index e263f326a..d5f12056a 100644
--- a/projects/adv7511/zed/Makefile
+++ b/projects/adv7511/zed/Makefile
@@ -13,7 +13,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index ea68e588a..2b74027c2 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -13,7 +13,13 @@ M_DEPS += ../common/arradio_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys
 M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
+M_DEPS += ../../../library/altera/common/ad_cmos_in.v
+M_DEPS += ../../../library/altera/common/ad_cmos_out.v
+M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
+M_DEPS += ../../../library/altera/common/ad_lvds_in.v
+M_DEPS += ../../../library/altera/common/ad_lvds_out.v
+M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
@@ -52,18 +58,9 @@ M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_mem.v
-M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_tdd_control.v
-M_DEPS += ../../../library/common/altera/DSP48E1.v
-M_DEPS += ../../../library/common/altera/MULT_MACRO.v
-M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
-M_DEPS += ../../../library/common/altera/ad_cmos_in.v
-M_DEPS += ../../../library/common/altera/ad_cmos_out.v
-M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
-M_DEPS += ../../../library/common/altera/ad_lvds_in.v
-M_DEPS += ../../../library/common/altera/ad_lvds_out.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
 M_DEPS += ../../../library/common/up_adc_channel.v
diff --git a/projects/cftl_cip/zed/Makefile b/projects/cftl_cip/zed/Makefile
index 686ba8caf..fbd23dc41 100644
--- a/projects/cftl_cip/zed/Makefile
+++ b/projects/cftl_cip/zed/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
diff --git a/projects/cftl_std/zed/Makefile b/projects/cftl_std/zed/Makefile
index fd12ba5b0..7b2f85d78 100644
--- a/projects/cftl_std/zed/Makefile
+++ b/projects/cftl_std/zed/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile
index fd152e0c1..246d22806 100644
--- a/projects/cn0363/microzed/Makefile
+++ b/projects/cn0363/microzed/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/microzed/microzed_system_ps7.tcl
 M_DEPS += ../../common/microzed/microzed_system_constr.xdc
 M_DEPS += ../../common/microzed/microzed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_generic_adc/axi_generic_adc.xpr
 M_DEPS += ../../../library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile
index da541a22e..53871a020 100644
--- a/projects/cn0363/zed/Makefile
+++ b/projects/cn0363/zed/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_generic_adc/axi_generic_adc.xpr
diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile
index 01ea63b33..26a7a7ca0 100644
--- a/projects/daq1/zc706/Makefile
+++ b/projects/daq1/zc706/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index 70076698f..59baf6452 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -14,7 +14,7 @@ M_DEPS += ../common/daq2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
@@ -51,11 +51,9 @@ M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_jesd_align.v
-M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
-M_DEPS += ../../../library/common/altera/MULT_MACRO.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
 M_DEPS += ../../../library/common/up_adc_channel.v
diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile
index f5d9acfd7..81a783ac9 100644
--- a/projects/daq2/kc705/Makefile
+++ b/projects/daq2/kc705/Makefile
@@ -18,7 +18,7 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../common/kc705/kc705_system_mig.prj
 M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile
index 247fbb27e..a1ec352fc 100644
--- a/projects/daq2/kcu105/Makefile
+++ b/projects/daq2/kcu105/Makefile
@@ -18,7 +18,7 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile
index 9b070ccc0..04212c867 100644
--- a/projects/daq2/vc707/Makefile
+++ b/projects/daq2/vc707/Makefile
@@ -18,7 +18,7 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index 380f4ea33..52f51a53b 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -20,7 +20,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index 92492ad75..bb4b08976 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -14,6 +14,7 @@ M_DEPS += ../common/daq3_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_core.v
@@ -50,11 +51,9 @@ M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_jesd_align.v
-M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
-M_DEPS += ../../../library/common/altera/MULT_MACRO.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
 M_DEPS += ../../../library/common/up_adc_channel.v
diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
index 568d3f2bc..dc9fe218a 100644
--- a/projects/daq3/kcu105/Makefile
+++ b/projects/daq3/kcu105/Makefile
@@ -18,7 +18,7 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index 60655c5ef..78c21f40c 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -20,7 +20,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index 1215e2339..14e82f504 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -18,7 +18,7 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index f207d5a77..74b389f1e 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index 6086e7713..fbcd95760 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile
index 421ca7519..3ab6280e9 100644
--- a/projects/fmcadc5/vc707/Makefile
+++ b/projects/fmcadc5/vc707/Makefile
@@ -19,8 +19,8 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
-M_DEPS += ../../../library/common/ad_lvds_out.v
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index ea00e8e03..6a52e19bd 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -14,7 +14,6 @@ M_DEPS += ../common/fmcjesdadc1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 3a6dc113c..27db0a706 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -14,7 +14,6 @@ M_DEPS += ../common/fmcjesdadc1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5soc/a5soc_system_bd.qsys
 M_DEPS += ../../common/a5soc/a5soc_system_assign.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile
index 84e0f1d60..f2d344498 100644
--- a/projects/fmcjesdadc1/kc705/Makefile
+++ b/projects/fmcjesdadc1/kc705/Makefile
@@ -17,7 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/kc705/kc705_system_mig.prj
 M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile
index 74b65b5ae..9d3448e72 100644
--- a/projects/fmcjesdadc1/vc707/Makefile
+++ b/projects/fmcjesdadc1/vc707/Makefile
@@ -17,7 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile
index 030f961f0..f9fe02005 100644
--- a/projects/fmcjesdadc1/zc706/Makefile
+++ b/projects/fmcjesdadc1/zc706/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms1/ac701/Makefile
index 052111b9d..b75bf5e4d 100644
--- a/projects/fmcomms1/ac701/Makefile
+++ b/projects/fmcomms1/ac701/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/ac701/ac701_system_mig.prj
 M_DEPS += ../../common/ac701/ac701_system_constr.xdc
 M_DEPS += ../../common/ac701/ac701_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms1/kc705/Makefile b/projects/fmcomms1/kc705/Makefile
index 995135825..aa1633c2a 100644
--- a/projects/fmcomms1/kc705/Makefile
+++ b/projects/fmcomms1/kc705/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/kc705/kc705_system_mig.prj
 M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms1/vc707/Makefile b/projects/fmcomms1/vc707/Makefile
index f86716289..b1648171d 100644
--- a/projects/fmcomms1/vc707/Makefile
+++ b/projects/fmcomms1/vc707/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms1/zc702/Makefile b/projects/fmcomms1/zc702/Makefile
index a1bfa3a34..e6e0c6fa5 100644
--- a/projects/fmcomms1/zc702/Makefile
+++ b/projects/fmcomms1/zc702/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc702/zc702_system_constr.xdc
 M_DEPS += ../../common/zc702/zc702_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/fmcomms1/zc706/Makefile b/projects/fmcomms1/zc706/Makefile
index 2fed37f66..c0e2e5068 100644
--- a/projects/fmcomms1/zc706/Makefile
+++ b/projects/fmcomms1/zc706/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/fmcomms1/zed/Makefile b/projects/fmcomms1/zed/Makefile
index a5233c373..6d3fd1ac3 100644
--- a/projects/fmcomms1/zed/Makefile
+++ b/projects/fmcomms1/zed/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index b747e7202..de49805e9 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -20,7 +20,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9162/axi_ad9162.xpr
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 2ee4d6487..4c1ed9ca0 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -13,6 +13,13 @@ M_DEPS += ../common/fmcomms2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
+M_DEPS += ../../../library/altera/common/ad_cmos_in.v
+M_DEPS += ../../../library/altera/common/ad_cmos_out.v
+M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
+M_DEPS += ../../../library/altera/common/ad_lvds_in.v
+M_DEPS += ../../../library/altera/common/ad_lvds_out.v
+M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
@@ -51,18 +58,9 @@ M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_mem.v
-M_DEPS += ../../../library/common/ad_mul.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_tdd_control.v
-M_DEPS += ../../../library/common/altera/DSP48E1.v
-M_DEPS += ../../../library/common/altera/MULT_MACRO.v
-M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
-M_DEPS += ../../../library/common/altera/ad_cmos_in.v
-M_DEPS += ../../../library/common/altera/ad_cmos_out.v
-M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
-M_DEPS += ../../../library/common/altera/ad_lvds_in.v
-M_DEPS += ../../../library/common/altera/ad_lvds_out.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
 M_DEPS += ../../../library/common/up_adc_channel.v
diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile
index 66954d699..ce1b2c52f 100644
--- a/projects/fmcomms2/ac701/Makefile
+++ b/projects/fmcomms2/ac701/Makefile
@@ -17,7 +17,7 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/ac701/ac701_system_mig.prj
 M_DEPS += ../../common/ac701/ac701_system_constr.xdc
 M_DEPS += ../../common/ac701/ac701_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile
index d7db6fb18..d3f85e133 100644
--- a/projects/fmcomms2/kc705/Makefile
+++ b/projects/fmcomms2/kc705/Makefile
@@ -17,7 +17,7 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/kc705/kc705_system_mig.prj
 M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile
index 34c32cfeb..83e16785d 100644
--- a/projects/fmcomms2/mitx045/Makefile
+++ b/projects/fmcomms2/mitx045/Makefile
@@ -17,7 +17,7 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl
 M_DEPS += ../../common/mitx045/mitx045_system_ps7.tcl
 M_DEPS += ../../common/mitx045/mitx045_system_constr.xdc
 M_DEPS += ../../common/mitx045/mitx045_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile
index 1089a7b28..2bba9ecfc 100644
--- a/projects/fmcomms2/vc707/Makefile
+++ b/projects/fmcomms2/vc707/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile
index f5064b9e0..bb60b6d34 100644
--- a/projects/fmcomms2/zc702/Makefile
+++ b/projects/fmcomms2/zc702/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc702/zc702_system_constr.xdc
 M_DEPS += ../../common/zc702/zc702_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile
index 99f47d740..5a761936c 100644
--- a/projects/fmcomms2/zc706/Makefile
+++ b/projects/fmcomms2/zc706/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms2/zcu102/Makefile b/projects/fmcomms2/zcu102/Makefile
index ec72c72ec..96db5feba 100644
--- a/projects/fmcomms2/zcu102/Makefile
+++ b/projects/fmcomms2/zcu102/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
 M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile
index ee553a9ac..15b95124a 100644
--- a/projects/fmcomms2/zed/Makefile
+++ b/projects/fmcomms2/zed/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile
index 98e7a633e..00c7e089a 100644
--- a/projects/fmcomms5/zc702/Makefile
+++ b/projects/fmcomms5/zc702/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc702/zc702_system_constr.xdc
 M_DEPS += ../../common/zc702/zc702_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile
index 2645c832b..069f26c0d 100644
--- a/projects/fmcomms5/zc706/Makefile
+++ b/projects/fmcomms5/zc706/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms6/zc706/Makefile b/projects/fmcomms6/zc706/Makefile
index b1292bc9f..e84934f94 100644
--- a/projects/fmcomms6/zc706/Makefile
+++ b/projects/fmcomms6/zc706/Makefile
@@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9652/axi_ad9652.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index c0df5c1da..3ddbc0915 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -20,7 +20,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile
index da98488cb..a01d63ffa 100644
--- a/projects/imageon/zc706/Makefile
+++ b/projects/imageon/zc706/Makefile
@@ -14,7 +14,7 @@ M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_rx/axi_hdmi_rx.xpr
diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile
index f7011b01a..29e292c86 100644
--- a/projects/imageon/zed/Makefile
+++ b/projects/imageon/zed/Makefile
@@ -14,7 +14,7 @@ M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_rx/axi_hdmi_rx.xpr
diff --git a/projects/motcon2_fmc/zed/Makefile b/projects/motcon2_fmc/zed/Makefile
index d4d26249b..c4177d1a4 100644
--- a/projects/motcon2_fmc/zed/Makefile
+++ b/projects/motcon2_fmc/zed/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile
index 38dd273a7..41615cbcf 100644
--- a/projects/pzsdr/ccbrk/Makefile
+++ b/projects/pzsdr/ccbrk/Makefile
@@ -19,7 +19,8 @@ M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
index ca329962d..bfb0de681 100644
--- a/projects/pzsdr/ccbrk_cmos/Makefile
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -19,7 +19,8 @@ M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_cmos_system_constr.xdc
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile
index c11c3c679..3d51c29c6 100644
--- a/projects/pzsdr/ccfmc/Makefile
+++ b/projects/pzsdr/ccfmc/Makefile
@@ -19,7 +19,8 @@ M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci/Makefile
index e726fe70f..d0b9f415c 100644
--- a/projects/pzsdr/ccpci/Makefile
+++ b/projects/pzsdr/ccpci/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
 M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile
index dc5a34c56..20dd931d1 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
 M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
 M_DEPS += ../../common/pzsdr1/pzsdr1_lvds_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
diff --git a/projects/pzsdr1/ccbrk_cmos/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile
index faa2e256a..d8b08f86f 100644
--- a/projects/pzsdr1/ccbrk_cmos/Makefile
+++ b/projects/pzsdr1/ccbrk_cmos/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
 M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
 M_DEPS += ../../common/pzsdr1/pzsdr1_cmos_system_constr.xdc
 M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile
index 84b91e988..16c02f1aa 100644
--- a/projects/usb_fx3/zc706/Makefile
+++ b/projects/usb_fx3/zc706/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr

From e9ac4a5a0e06e390320e6f91581a89280cfa00ca Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 8 Aug 2016 16:39:25 +0300
Subject: [PATCH 385/972] util_rfifo: Patch up the description of Altera IP

---
 library/util_rfifo/util_rfifo_hw.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/util_rfifo/util_rfifo_hw.tcl b/library/util_rfifo/util_rfifo_hw.tcl
index 064b8de18..e64e2b3e7 100755
--- a/library/util_rfifo/util_rfifo_hw.tcl
+++ b/library/util_rfifo/util_rfifo_hw.tcl
@@ -5,7 +5,7 @@ source ../scripts/adi_env.tcl
 source ../scripts/adi_ip_alt.tcl
 
 set_module_property NAME util_rfifo
-set_module_property DESCRIPTION "Utils Write FIFO"
+set_module_property DESCRIPTION "Utils Read FIFO"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
 set_module_property DISPLAY_NAME util_rfifo

From ccf1c56b332685b7fb72845da263f61f00b8755b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 8 Aug 2016 16:39:56 +0300
Subject: [PATCH 386/972] util_upack: Patch up the description of Altera IP

---
 library/util_upack/util_upack_hw.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/util_upack/util_upack_hw.tcl b/library/util_upack/util_upack_hw.tcl
index 7e4ecc1d0..43039d60e 100755
--- a/library/util_upack/util_upack_hw.tcl
+++ b/library/util_upack/util_upack_hw.tcl
@@ -6,7 +6,7 @@ source ../scripts/adi_ip_alt.tcl
 
 
 set_module_property NAME util_upack
-set_module_property DESCRIPTION "Channel Pack Utility"
+set_module_property DESCRIPTION "Channel Unpack Utility"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
 set_module_property DISPLAY_NAME util_upack

From c6f4def93df9b2e3c351a322b3700187c70083b5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 8 Aug 2016 11:54:39 -0400
Subject: [PATCH 387/972] altera- make mmu a make switch

---
 projects/common/a10gx/a10gx_system_assign.tcl | 18 ++++++++++++++++--
 projects/common/a10gx/a10gx_system_qsys.tcl   |  4 ++--
 projects/daq2/a10gx/Makefile                  |  6 ++++++
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl
index f1d6eeb6c..92a45c027 100755
--- a/projects/common/a10gx/a10gx_system_assign.tcl
+++ b/projects/common/a10gx/a10gx_system_assign.tcl
@@ -245,7 +245,21 @@ set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
 set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
 
 # generate qsys
+# move this to a project script
+
+set mmu_enabled 1
+if [info exists ::env(ALT_NIOS_MMU_ENABLED)] {
+  set mmu_enabled $::env(ALT_NIOS_MMU_ENABLED)
+}
+
+if {$mmu_enabled == 0} {
+  set cmd_str "set mmu_enabled 0"
+  exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
+    --cmd=$cmd_str --script=system_qsys.tcl
+} else {
+  set cmd_str "set mmu_enabled 1"
+  exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
+    --cmd=$cmd_str --script=system_qsys.tcl
+}
 
-exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script --script=system_qsys.tcl
- 
 
diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl
index c559306fb..440e1bb68 100644
--- a/projects/common/a10gx/a10gx_system_qsys.tcl
+++ b/projects/common/a10gx/a10gx_system_qsys.tcl
@@ -1,5 +1,5 @@
 
-package require -exact qsys 14.0
+package require qsys
 
 set_module_property NAME {system_bd}
 set_project_property DEVICE_FAMILY {Arria 10}
@@ -100,7 +100,7 @@ set_instance_parameter_value sys_cpu {dcache_numTCDM} {1}
 set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
 set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
 set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
-set_instance_parameter_value sys_cpu {mmu_enabled} {1}
+set_instance_parameter_value sys_cpu {mmu_enabled} $mmu_enabled
 
 add_connection sys_clk.clk sys_cpu.clk
 add_connection sys_clk.clk_reset sys_cpu.reset
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index 59baf6452..96cd875de 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_top.v
 M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl

From 452d4706d3b95eb08c7b54d5431145c6204d3484 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 22 Jul 2016 17:50:18 +0300
Subject: [PATCH 388/972] kcu105: Update base project to 2015.4.2

- change part to revision 1.1 of the board
---
 projects/common/kcu105/kcu105_system_bd.tcl   |  46 ++----
 .../common/kcu105/kcu105_system_constr.xdc    | 132 ------------------
 projects/scripts/adi_project.tcl              |   2 +-
 3 files changed, 15 insertions(+), 165 deletions(-)

diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl
index 3bbc41c3f..82791a84f 100644
--- a/projects/common/kcu105/kcu105_system_bd.tcl
+++ b/projects/common/kcu105/kcu105_system_bd.tcl
@@ -80,32 +80,24 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
 
 # instance: ddr (mig)
 
-set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl]
-source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
+set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl ]
+set_property -dict [list CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_300}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl
 
 set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen]
 
 # instance: default peripherals
 
-set axi_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 axi_ethernet_clkgen]
-set_property -dict [list CONFIG.PRIM_IN_FREQ {625}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.PRIM_SOURCE {Differential_clock_capable_pin}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.CLKOUT2_USED {true}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {312}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.CLKOUT3_USED {true}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {625}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.CLKOUT4_USED {false}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.USE_LOCKED {true}] $axi_ethernet_clkgen
-set_property -dict [list CONFIG.USE_RESET {false}] $axi_ethernet_clkgen
-
-set axi_ethernet_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ethernet_rstgen]
-set axi_ethernet_idelayctrl [create_bd_cell -type ip -vlnv xilinx.com:ip:util_idelay_ctrl:1.0 axi_ethernet_idelayctrl]
-
 set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet]
-set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet
-set_property -dict [list CONFIG.ENABLE_LVDS {true}] $axi_ethernet
-set_property -dict [list CONFIG.SupportLevel {0}] $axi_ethernet
+set_property -dict [list CONFIG.SupportLevel {1}] $axi_ethernet
+set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethernet
+set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet
+set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet
+set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet
+set_property -dict [list CONFIG.lvdsclkrate {625}] $axi_ethernet
 set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
 set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
 set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet
@@ -210,13 +202,12 @@ ad_connect  c0_ddr4 axi_ddr_cntrl/C0_DDR4
 ad_connect  sys_clk axi_ddr_cntrl/C0_SYS_CLK
 
 ad_connect  axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in
-ad_connect  axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ethernet_rstgen/ext_reset_in
 ad_connect  axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in
 ad_connect  sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk
 
 # defaults (ethernet)
 
-ad_connect  phy_clk axi_ethernet_clkgen/CLK_IN1_D
+ad_connect  phy_clk axi_ethernet/lvds_clk
 ad_connect  mdio axi_ethernet/mdio
 ad_connect  sgmii axi_ethernet/sgmii
 ad_connect  axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S
@@ -224,20 +215,11 @@ ad_connect  axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL
 ad_connect  axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM
 ad_connect  axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS
 ad_connect  phy_sd axi_ethernet/signal_detect
-ad_connect  sys_cpu_resetn phy_rst_n
-ad_connect  axi_ethernet_clkgen/clk_out1 axi_ethernet/clk125m
-ad_connect  axi_ethernet_clkgen/clk_out1 axi_ethernet_rstgen/slowest_sync_clk
-ad_connect  axi_ethernet_clkgen/clk_out2 axi_ethernet/clk312
-ad_connect  axi_ethernet_clkgen/clk_out3 axi_ethernet/clk625
-ad_connect  axi_ethernet_clkgen/locked axi_ethernet/mmcm_locked
-ad_connect  axi_ethernet_rstgen/peripheral_reset axi_ethernet/rst_125
+ad_connect  phy_rst_n axi_ethernet/phy_rst_n
 ad_connect  axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n
 ad_connect  axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n
 ad_connect  axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n
 ad_connect  axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n
-ad_connect  axi_ethernet_idelayctrl/rdy axi_ethernet/idelay_rdy_in
-ad_connect  axi_ethernet_idelayctrl/rst axi_ethernet_rstgen/peripheral_reset
-ad_connect  axi_ethernet_idelayctrl/ref_clk axi_ethernet_clkgen/clk_out3
 
 # defaults (misc)
 
diff --git a/projects/common/kcu105/kcu105_system_constr.xdc b/projects/common/kcu105/kcu105_system_constr.xdc
index fb6306582..353122bca 100644
--- a/projects/common/kcu105/kcu105_system_constr.xdc
+++ b/projects/common/kcu105/kcu105_system_constr.xdc
@@ -3,21 +3,6 @@
 
 set_property -dict  {PACKAGE_PIN  AN8   IOSTANDARD  LVCMOS18} [get_ports sys_rst] 
 
-# clocks
-
-set_property -dict  {PACKAGE_PIN  P26   IOSTANDARD  LVDS_25} [get_ports phy_clk_p] 
-set_property -dict  {PACKAGE_PIN  N26   IOSTANDARD  LVDS_25} [get_ports phy_clk_n] 
-
-# ethernet
-
-set_property -dict  {PACKAGE_PIN  L25   IOSTANDARD  LVCMOS18}       [get_ports mdio_mdc] 
-set_property -dict  {PACKAGE_PIN  H26   IOSTANDARD  LVCMOS18}       [get_ports mdio_mdio] 
-set_property -dict  {PACKAGE_PIN  J23   IOSTANDARD  LVCMOS18}       [get_ports phy_rst_n] 
-set_property -dict  {PACKAGE_PIN  N24   IOSTANDARD  DIFF_HSTL_I_18} [get_ports phy_tx_p] 
-set_property -dict  {PACKAGE_PIN  M24   IOSTANDARD  DIFF_HSTL_I_18} [get_ports phy_tx_n] 
-set_property -dict  {PACKAGE_PIN  P24   IOSTANDARD  DIFF_HSTL_I_18} [get_ports phy_rx_p] 
-set_property -dict  {PACKAGE_PIN  P25   IOSTANDARD  DIFF_HSTL_I_18} [get_ports phy_rx_n] 
-
 # uart
 
 set_property -dict  {PACKAGE_PIN  K26   IOSTANDARD  LVCMOS18} [get_ports uart_sout]
@@ -56,125 +41,8 @@ set_property -dict  {PACKAGE_PIN  J25   IOSTANDARD  LVCMOS18} [get_ports iic_sda
 
 set_property -dict  {PACKAGE_PIN  AK17} [get_ports sys_clk_p]
 set_property -dict  {PACKAGE_PIN  AK16} [get_ports sys_clk_n]
-set_property -dict  {PACKAGE_PIN  AH14} [get_ports ddr4_act_n]
-set_property -dict  {PACKAGE_PIN  AE17} [get_ports ddr4_addr[0]]
-set_property -dict  {PACKAGE_PIN  AH17} [get_ports ddr4_addr[1]]
-set_property -dict  {PACKAGE_PIN  AE18} [get_ports ddr4_addr[2]]
-set_property -dict  {PACKAGE_PIN  AJ15} [get_ports ddr4_addr[3]]
-set_property -dict  {PACKAGE_PIN  AG16} [get_ports ddr4_addr[4]]
-set_property -dict  {PACKAGE_PIN  AL17} [get_ports ddr4_addr[5]]
-set_property -dict  {PACKAGE_PIN  AK18} [get_ports ddr4_addr[6]]
-set_property -dict  {PACKAGE_PIN  AG17} [get_ports ddr4_addr[7]]
-set_property -dict  {PACKAGE_PIN  AF18} [get_ports ddr4_addr[8]]
-set_property -dict  {PACKAGE_PIN  AH19} [get_ports ddr4_addr[9]]
-set_property -dict  {PACKAGE_PIN  AF15} [get_ports ddr4_addr[10]]
-set_property -dict  {PACKAGE_PIN  AD19} [get_ports ddr4_addr[11]]
-set_property -dict  {PACKAGE_PIN  AJ14} [get_ports ddr4_addr[12]]
-set_property -dict  {PACKAGE_PIN  AG19} [get_ports ddr4_addr[13]]
-set_property -dict  {PACKAGE_PIN  AD16} [get_ports ddr4_addr[14]]
-set_property -dict  {PACKAGE_PIN  AG14} [get_ports ddr4_addr[15]]
-set_property -dict  {PACKAGE_PIN  AF14} [get_ports ddr4_addr[16]]
-set_property -dict  {PACKAGE_PIN  AF17} [get_ports ddr4_ba[0]]
-set_property -dict  {PACKAGE_PIN  AL15} [get_ports ddr4_ba[1]]
-set_property -dict  {PACKAGE_PIN  AG15} [get_ports ddr4_bg[0]]
-set_property -dict  {PACKAGE_PIN  AE16} [get_ports ddr4_ck_p]
-set_property -dict  {PACKAGE_PIN  AE15} [get_ports ddr4_ck_n]
-set_property -dict  {PACKAGE_PIN  AD15} [get_ports ddr4_cke[0]]
-set_property -dict  {PACKAGE_PIN  AL19} [get_ports ddr4_cs_n[0]]
-set_property -dict  {PACKAGE_PIN  AD21} [get_ports ddr4_dm_n[0]]
-set_property -dict  {PACKAGE_PIN  AE25} [get_ports ddr4_dm_n[1]]
-set_property -dict  {PACKAGE_PIN  AJ21} [get_ports ddr4_dm_n[2]]
-set_property -dict  {PACKAGE_PIN  AM21} [get_ports ddr4_dm_n[3]]
-set_property -dict  {PACKAGE_PIN  AH26} [get_ports ddr4_dm_n[4]]
-set_property -dict  {PACKAGE_PIN  AN26} [get_ports ddr4_dm_n[5]]
-set_property -dict  {PACKAGE_PIN  AJ29} [get_ports ddr4_dm_n[6]]
-set_property -dict  {PACKAGE_PIN  AL32} [get_ports ddr4_dm_n[7]]
-set_property -dict  {PACKAGE_PIN  AE23} [get_ports ddr4_dq[0]]
-set_property -dict  {PACKAGE_PIN  AG20} [get_ports ddr4_dq[1]]
-set_property -dict  {PACKAGE_PIN  AF22} [get_ports ddr4_dq[2]]
-set_property -dict  {PACKAGE_PIN  AF20} [get_ports ddr4_dq[3]]
-set_property -dict  {PACKAGE_PIN  AE22} [get_ports ddr4_dq[4]]
-set_property -dict  {PACKAGE_PIN  AD20} [get_ports ddr4_dq[5]]
-set_property -dict  {PACKAGE_PIN  AG22} [get_ports ddr4_dq[6]]
-set_property -dict  {PACKAGE_PIN  AE20} [get_ports ddr4_dq[7]]
-set_property -dict  {PACKAGE_PIN  AJ24} [get_ports ddr4_dq[8]]
-set_property -dict  {PACKAGE_PIN  AG24} [get_ports ddr4_dq[9]]
-set_property -dict  {PACKAGE_PIN  AJ23} [get_ports ddr4_dq[10]]
-set_property -dict  {PACKAGE_PIN  AF23} [get_ports ddr4_dq[11]]
-set_property -dict  {PACKAGE_PIN  AH23} [get_ports ddr4_dq[12]]
-set_property -dict  {PACKAGE_PIN  AF24} [get_ports ddr4_dq[13]]
-set_property -dict  {PACKAGE_PIN  AH22} [get_ports ddr4_dq[14]]
-set_property -dict  {PACKAGE_PIN  AG25} [get_ports ddr4_dq[15]]
-set_property -dict  {PACKAGE_PIN  AL22} [get_ports ddr4_dq[16]]
-set_property -dict  {PACKAGE_PIN  AL25} [get_ports ddr4_dq[17]]
-set_property -dict  {PACKAGE_PIN  AM20} [get_ports ddr4_dq[18]]
-set_property -dict  {PACKAGE_PIN  AK23} [get_ports ddr4_dq[19]]
-set_property -dict  {PACKAGE_PIN  AK22} [get_ports ddr4_dq[20]]
-set_property -dict  {PACKAGE_PIN  AL24} [get_ports ddr4_dq[21]]
-set_property -dict  {PACKAGE_PIN  AL20} [get_ports ddr4_dq[22]]
-set_property -dict  {PACKAGE_PIN  AL23} [get_ports ddr4_dq[23]]
-set_property -dict  {PACKAGE_PIN  AM24} [get_ports ddr4_dq[24]]
-set_property -dict  {PACKAGE_PIN  AN23} [get_ports ddr4_dq[25]]
-set_property -dict  {PACKAGE_PIN  AN24} [get_ports ddr4_dq[26]]
-set_property -dict  {PACKAGE_PIN  AP23} [get_ports ddr4_dq[27]]
-set_property -dict  {PACKAGE_PIN  AP25} [get_ports ddr4_dq[28]]
-set_property -dict  {PACKAGE_PIN  AN22} [get_ports ddr4_dq[29]]
-set_property -dict  {PACKAGE_PIN  AP24} [get_ports ddr4_dq[30]]
-set_property -dict  {PACKAGE_PIN  AM22} [get_ports ddr4_dq[31]]
-set_property -dict  {PACKAGE_PIN  AH28} [get_ports ddr4_dq[32]]
-set_property -dict  {PACKAGE_PIN  AK26} [get_ports ddr4_dq[33]]
-set_property -dict  {PACKAGE_PIN  AK28} [get_ports ddr4_dq[34]]
-set_property -dict  {PACKAGE_PIN  AM27} [get_ports ddr4_dq[35]]
-set_property -dict  {PACKAGE_PIN  AJ28} [get_ports ddr4_dq[36]]
-set_property -dict  {PACKAGE_PIN  AH27} [get_ports ddr4_dq[37]]
-set_property -dict  {PACKAGE_PIN  AK27} [get_ports ddr4_dq[38]]
-set_property -dict  {PACKAGE_PIN  AM26} [get_ports ddr4_dq[39]]
-set_property -dict  {PACKAGE_PIN  AL30} [get_ports ddr4_dq[40]]
-set_property -dict  {PACKAGE_PIN  AP29} [get_ports ddr4_dq[41]]
-set_property -dict  {PACKAGE_PIN  AM30} [get_ports ddr4_dq[42]]
-set_property -dict  {PACKAGE_PIN  AN28} [get_ports ddr4_dq[43]]
-set_property -dict  {PACKAGE_PIN  AL29} [get_ports ddr4_dq[44]]
-set_property -dict  {PACKAGE_PIN  AP28} [get_ports ddr4_dq[45]]
-set_property -dict  {PACKAGE_PIN  AM29} [get_ports ddr4_dq[46]]
-set_property -dict  {PACKAGE_PIN  AN27} [get_ports ddr4_dq[47]]
-set_property -dict  {PACKAGE_PIN  AH31} [get_ports ddr4_dq[48]]
-set_property -dict  {PACKAGE_PIN  AH32} [get_ports ddr4_dq[49]]
-set_property -dict  {PACKAGE_PIN  AJ34} [get_ports ddr4_dq[50]]
-set_property -dict  {PACKAGE_PIN  AK31} [get_ports ddr4_dq[51]]
-set_property -dict  {PACKAGE_PIN  AJ31} [get_ports ddr4_dq[52]]
-set_property -dict  {PACKAGE_PIN  AJ30} [get_ports ddr4_dq[53]]
-set_property -dict  {PACKAGE_PIN  AH34} [get_ports ddr4_dq[54]]
-set_property -dict  {PACKAGE_PIN  AK32} [get_ports ddr4_dq[55]]
-set_property -dict  {PACKAGE_PIN  AN33} [get_ports ddr4_dq[56]]
-set_property -dict  {PACKAGE_PIN  AP33} [get_ports ddr4_dq[57]]
-set_property -dict  {PACKAGE_PIN  AM34} [get_ports ddr4_dq[58]]
-set_property -dict  {PACKAGE_PIN  AP31} [get_ports ddr4_dq[59]]
-set_property -dict  {PACKAGE_PIN  AM32} [get_ports ddr4_dq[60]]
-set_property -dict  {PACKAGE_PIN  AN31} [get_ports ddr4_dq[61]]
-set_property -dict  {PACKAGE_PIN  AL34} [get_ports ddr4_dq[62]]
-set_property -dict  {PACKAGE_PIN  AN32} [get_ports ddr4_dq[63]]
-set_property -dict  {PACKAGE_PIN  AG21} [get_ports ddr4_dqs_p[0]]
-set_property -dict  {PACKAGE_PIN  AH24} [get_ports ddr4_dqs_p[1]]
-set_property -dict  {PACKAGE_PIN  AJ20} [get_ports ddr4_dqs_p[2]]
-set_property -dict  {PACKAGE_PIN  AP20} [get_ports ddr4_dqs_p[3]]
-set_property -dict  {PACKAGE_PIN  AL27} [get_ports ddr4_dqs_p[4]]
-set_property -dict  {PACKAGE_PIN  AN29} [get_ports ddr4_dqs_p[5]]
-set_property -dict  {PACKAGE_PIN  AH33} [get_ports ddr4_dqs_p[6]]
-set_property -dict  {PACKAGE_PIN  AN34} [get_ports ddr4_dqs_p[7]]
-set_property -dict  {PACKAGE_PIN  AH21} [get_ports ddr4_dqs_n[0]]
-set_property -dict  {PACKAGE_PIN  AJ25} [get_ports ddr4_dqs_n[1]]
-set_property -dict  {PACKAGE_PIN  AK20} [get_ports ddr4_dqs_n[2]]
-set_property -dict  {PACKAGE_PIN  AP21} [get_ports ddr4_dqs_n[3]]
-set_property -dict  {PACKAGE_PIN  AL28} [get_ports ddr4_dqs_n[4]]
-set_property -dict  {PACKAGE_PIN  AP30} [get_ports ddr4_dqs_n[5]]
-set_property -dict  {PACKAGE_PIN  AJ33} [get_ports ddr4_dqs_n[6]]
-set_property -dict  {PACKAGE_PIN  AP34} [get_ports ddr4_dqs_n[7]]
-set_property -dict  {PACKAGE_PIN  AJ18} [get_ports ddr4_odt[0]]
-set_property -dict  {PACKAGE_PIN  AL18} [get_ports ddr4_reset_n]
 
 set_property -dict  {INTERNAL_VREF {0.84}}  [get_iobanks 44]
 set_property -dict  {INTERNAL_VREF {0.84}}  [get_iobanks 45]
 set_property -dict  {INTERNAL_VREF {0.84}}  [get_iobanks 46]
 
-set_false_path -to [get_pins -hier -filter {name =~ *axi_ethernet_idelayctrl*/RST}]
-
diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index 77101fc33..cce18d679 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -47,7 +47,7 @@ proc adi_project_create {project_name {mode 0}} {
   }
   if [regexp "_kcu105$" $project_name] {
     set p_device "xcku040-ffva1156-2-e"
-    set p_board "xilinx.com:kcu105:part0:1.0"
+    set p_board "xilinx.com:kcu105:part0:1.1"
     set sys_zynq 0
   }
   if [regexp "_zed$" $project_name] {

From 285059aed03f466d1abebb35e7b0814b4ed3e3f7 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 8 Aug 2016 17:53:32 +0300
Subject: [PATCH 389/972] kcu105: Don't use phy reset automation, as it's not
 supported for KCU105

---
 projects/common/kcu105/kcu105_system_bd.tcl     | 3 +--
 projects/common/kcu105/kcu105_system_constr.xdc | 7 +++++++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl
index 82791a84f..873e206a3 100644
--- a/projects/common/kcu105/kcu105_system_bd.tcl
+++ b/projects/common/kcu105/kcu105_system_bd.tcl
@@ -95,7 +95,6 @@ set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 a
 set_property -dict [list CONFIG.SupportLevel {1}] $axi_ethernet
 set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethernet
 set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet
-set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet
 set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet
 set_property -dict [list CONFIG.lvdsclkrate {625}] $axi_ethernet
 set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
@@ -215,7 +214,7 @@ ad_connect  axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL
 ad_connect  axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM
 ad_connect  axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS
 ad_connect  phy_sd axi_ethernet/signal_detect
-ad_connect  phy_rst_n axi_ethernet/phy_rst_n
+ad_connect  sys_cpu_resetn phy_rst_n
 ad_connect  axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n
 ad_connect  axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n
 ad_connect  axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n
diff --git a/projects/common/kcu105/kcu105_system_constr.xdc b/projects/common/kcu105/kcu105_system_constr.xdc
index 353122bca..1688c660e 100644
--- a/projects/common/kcu105/kcu105_system_constr.xdc
+++ b/projects/common/kcu105/kcu105_system_constr.xdc
@@ -8,6 +8,10 @@ set_property -dict  {PACKAGE_PIN  AN8   IOSTANDARD  LVCMOS18} [get_ports sys_rst
 set_property -dict  {PACKAGE_PIN  K26   IOSTANDARD  LVCMOS18} [get_ports uart_sout]
 set_property -dict  {PACKAGE_PIN  G25   IOSTANDARD  LVCMOS18} [get_ports uart_sin] 
 
+# ethernet  (phy_rst_n automation cannot be used with axi_ethernet 7.0) 
+
+set_property -dict  {PACKAGE_PIN  J23   IOSTANDARD  LVCMOS18}  [get_ports phy_rst_n]
+
 # fan 
 
 set_property -dict  {PACKAGE_PIN  AJ9   IOSTANDARD  LVCMOS18} [get_ports fan_pwm] 
@@ -46,3 +50,6 @@ set_property -dict  {INTERNAL_VREF {0.84}}  [get_iobanks 44]
 set_property -dict  {INTERNAL_VREF {0.84}}  [get_iobanks 45]
 set_property -dict  {INTERNAL_VREF {0.84}}  [get_iobanks 46]
 
+create_clock -name phy_clk      -period  1.60 [get_ports phy_clk_p]
+
+set_false_path -to [get_pins -hier -filter {name =~ *ethernet*idelayctrl*/RST}]

From b8f4e1c0aa73210fbc93b21f7b543a3b7dbf1db7 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Wed, 10 Aug 2016 14:50:31 -0400
Subject: [PATCH 390/972] updated 9680 hdl files(to resolve a critical warning)

---
 library/axi_ad9680/axi_ad9680.v      | 5 ++---
 library/axi_ad9680/axi_ad9680_ip.tcl | 1 +
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v
index 66e54937b..a7b50c7c5 100644
--- a/library/axi_ad9680/axi_ad9680.v
+++ b/library/axi_ad9680/axi_ad9680.v
@@ -44,8 +44,8 @@ module axi_ad9680 (
 
   rx_clk,
   rx_sof,
-  rx_data,
   rx_valid,
+  rx_data,
   rx_ready,
 
   // dma interface
@@ -93,9 +93,8 @@ module axi_ad9680 (
 
   input           rx_clk;
   input  [  3:0]  rx_sof;
-  input  [127:0]  rx_data;
-
   input           rx_valid;
+  input  [127:0]  rx_data;
   output          rx_ready;
 
   // dma interface
diff --git a/library/axi_ad9680/axi_ad9680_ip.tcl b/library/axi_ad9680/axi_ad9680_ip.tcl
index 1f68f2a88..29891e34d 100644
--- a/library/axi_ad9680/axi_ad9680_ip.tcl
+++ b/library/axi_ad9680/axi_ad9680_ip.tcl
@@ -26,6 +26,7 @@ adi_ip_properties axi_ad9680
 adi_ip_constraints axi_ad9680 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
 
+set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 

From 829e4155ca74ac2ba4ae7ecb3840cfebd81a8d67 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Wed, 10 Aug 2016 14:59:38 -0400
Subject: [PATCH 391/972] modified transceiver configuration files

---
 library/xilinx/axi_adxcvr/axi_adxcvr.v      | 6 +++---
 library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v
index 909ac93f3..8153141d0 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v
@@ -695,7 +695,7 @@ module axi_adxcvr (
     .up_sel (up_cm_sel),
     .up_enb (up_cm_enb),
     .up_rdata_in (16'd0),
-    .up_ready_in (1'd0),
+    .up_ready_in (1'd1),
     .up_rdata (up_cm_rdata_0),
     .up_ready (up_cm_ready_0),
     .up_rdata_out (up_cm_rdata_0_s),
@@ -716,7 +716,7 @@ module axi_adxcvr (
     .up_sel (up_es_sel),
     .up_enb (up_es_enb),
     .up_rdata_in (16'd0),
-    .up_ready_in (1'd0),
+    .up_ready_in (1'd1),
     .up_rdata (up_es_rdata_0),
     .up_ready (up_es_ready_0),
     .up_rdata_out (up_es_rdata_0_s),
@@ -758,7 +758,7 @@ module axi_adxcvr (
     .up_sel (up_ch_sel),
     .up_enb (up_ch_enb),
     .up_rdata_in (16'd0),
-    .up_ready_in (1'd0),
+    .up_ready_in (1'd1),
     .up_rdata (up_ch_rdata_0),
     .up_ready (up_ch_ready_0),
     .up_rdata_out (up_ch_rdata_0_s),
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
index 8808bde9f..7d73ae17b 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -64,11 +64,13 @@ xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
 
 ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 ipx::infer_bus_interface axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
   -of_objects [ipx::current_core]]
 set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
   -of_objects [ipx::get_bus_interfaces axi_clk \
   -of_objects [ipx::current_core]]]
+
 ipx::add_memory_map {s_axi} [ipx::current_core]
 set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
 ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]

From bb9cb86f346ffdc4f8987c1b399007506f733afe Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 11 Aug 2016 09:58:36 -0400
Subject: [PATCH 392/972] adc/dac- fifo constraints

---
 library/util_adcfifo/util_adcfifo_constr.xdc |  8 +++++---
 library/util_dacfifo/util_dacfifo.v          | 12 ++++++------
 library/util_dacfifo/util_dacfifo_constr.xdc |  9 +++++++--
 3 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/library/util_adcfifo/util_adcfifo_constr.xdc b/library/util_adcfifo/util_adcfifo_constr.xdc
index d0f3cfbaa..2e7ab2b1c 100644
--- a/library/util_adcfifo/util_adcfifo_constr.xdc
+++ b/library/util_adcfifo/util_adcfifo_constr.xdc
@@ -1,6 +1,8 @@
 
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dma_clk]]
-
+set_property shreg_extract no [get_cells -hier -filter {name =~ *adc_xfer_req_m*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *dma_waddr_rel_t*}]
 
+set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_t_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_t_m_reg[0]* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_reg* && IS_SEQUENTIAL}]   -to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
 
diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v
index e73eb0091..16e183acb 100644
--- a/library/util_dacfifo/util_dacfifo.v
+++ b/library/util_dacfifo/util_dacfifo.v
@@ -91,8 +91,8 @@ module util_dacfifo (
 
   reg     [(ADDRESS_WIDTH-1):0]       dma_waddr = 'b0;
   reg     [(ADDRESS_WIDTH-1):0]       dma_lastaddr = 'b0;
-  reg     [(ADDRESS_WIDTH-1):0]       dma_lastaddr_d = 'b0;
-  reg     [(ADDRESS_WIDTH-1):0]       dma_lastaddr_2d = 'b0;
+  reg     [(ADDRESS_WIDTH-1):0]       dac_lastaddr_d = 'b0;
+  reg     [(ADDRESS_WIDTH-1):0]       dac_lastaddr_2d = 'b0;
   reg                                 dma_xfer_req_ff = 1'b0;
   reg                                 dma_ready_d = 1'b0;
 
@@ -140,8 +140,8 @@ module util_dacfifo (
   // sync lastaddr to dac clock domain
 
   always @(posedge dac_clk) begin
-    dma_lastaddr_d <= dma_lastaddr;
-    dma_lastaddr_2d <= dma_lastaddr_d;
+    dac_lastaddr_d <= dma_lastaddr;
+    dac_lastaddr_2d <= dac_lastaddr_d;
     dac_xfer_out_m <= {dac_xfer_out_m[1:0], dma_xfer_out};
   end
 
@@ -151,10 +151,10 @@ module util_dacfifo (
 
   always @(posedge dac_clk) begin
     if(dac_valid == 1'b1) begin
-      if (dma_lastaddr_2d == 'h0) begin
+      if (dac_lastaddr_2d == 'h0) begin
         dac_raddr <= dac_raddr + 1;
       end else begin
-        dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
+        dac_raddr <= (dac_raddr < dac_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
       end
     end
   end
diff --git a/library/util_dacfifo/util_dacfifo_constr.xdc b/library/util_dacfifo/util_dacfifo_constr.xdc
index c8c0111d1..670b91327 100644
--- a/library/util_dacfifo/util_dacfifo_constr.xdc
+++ b/library/util_dacfifo/util_dacfifo_constr.xdc
@@ -1,2 +1,7 @@
-set_false_path -from [get_cells *dma_lastaddr_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-  -to [get_cells *dma_lastaddr_d_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_lastaddr_d*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_xfer_out_m*}]
+
+set_false_path -from [get_cells -hier -filter {name =~ *dma_lastaddr_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_lastaddr_d_reg* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m_reg[0]* && IS_SEQUENTIAL}]
+

From 3427965cd29891fad884d7eb89c3b66df29da26a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 11 Aug 2016 09:59:15 -0400
Subject: [PATCH 393/972] adxcvr- add u-gth bufg

---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index f183f7da2..34250b24f 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -294,8 +294,19 @@ module util_adxcvr_xch (
 
   // instantiations
 
+  generate
+  if (GTH_OR_GTX_N == 0) begin
   BUFG i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk));
   BUFG i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk));
+  end
+  endgenerate
+
+  generate
+  if (GTH_OR_GTX_N == 1) begin
+  BUFG_GT i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk));
+  BUFG_GT i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk));
+  end
+  endgenerate
 
   generate
   if (GTH_OR_GTX_N == 0) begin

From 16ad0f4379ffdf82dedf15cec1931cbf38313482 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 11 Aug 2016 09:59:38 -0400
Subject: [PATCH 394/972] kcu105- 2016.2 update

---
 projects/common/kcu105/kcu105_system_bd.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl
index 873e206a3..48a69d2b8 100644
--- a/projects/common/kcu105/kcu105_system_bd.tcl
+++ b/projects/common/kcu105/kcu105_system_bd.tcl
@@ -51,7 +51,7 @@ set_property -dict [list CONFIG.FREQ_HZ {625000000}] [get_bd_intf_ports phy_clk]
 
 # instance: microblaze - processor
 
-set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb]
+set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb]
 set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb
 set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
 
@@ -80,7 +80,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
 
 # instance: ddr (mig)
 
-set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl ]
+set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.0 axi_ddr_cntrl ]
 set_property -dict [list CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_300}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_ddr_cntrl

From 5d93e542ed251be727abf2340aecf73beb211d40 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 11 Aug 2016 10:00:26 -0400
Subject: [PATCH 395/972] daq2-kcu105: 2016.2 updates

---
 projects/daq2/kcu105/system_bd.tcl      |  6 +++---
 projects/daq2/kcu105/system_constr.xdc  | 15 +++++++++------
 projects/daq2/kcu105/system_project.tcl |  5 -----
 projects/daq2/kcu105/system_top.v       | 22 ++++++++++++++++------
 4 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl
index 644363e8d..d47f2bd68 100644
--- a/projects/daq2/kcu105/system_bd.tcl
+++ b/projects/daq2/kcu105/system_bd.tcl
@@ -7,8 +7,8 @@ p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
 
 source ../common/daq2_bd.tcl
 
-set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $axi_daq2_gt
-set_property -dict [list CONFIG.QPLL0_FBDIV {20}] $axi_daq2_gt
-set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_daq2_gt
+set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $util_daq2_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq2_xcvr
+set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq2_xcvr
 
 
diff --git a/projects/daq2/kcu105/system_constr.xdc b/projects/daq2/kcu105/system_constr.xdc
index 44a8f125c..ac806dd2d 100644
--- a/projects/daq2/kcu105/system_constr.xdc
+++ b/projects/daq2/kcu105/system_constr.xdc
@@ -40,8 +40,8 @@ set_property  -dict {PACKAGE_PIN  E8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [g
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
 
 # gt pin assignments below are for reference only and are ignored by the tool!
 
@@ -62,8 +62,11 @@ create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_
 ##  set_property  -dict {PACKAGE_PIN  D6} [get_ports tx_data_p[3]] ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
 ##  set_property  -dict {PACKAGE_PIN  D5} [get_ports tx_data_n[3]] ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
 
-set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[1].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[2].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[3].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_1/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9144_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9680_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
diff --git a/projects/daq2/kcu105/system_project.tcl b/projects/daq2/kcu105/system_project.tcl
index 45db50cd7..ad3fad935 100644
--- a/projects/daq2/kcu105/system_project.tcl
+++ b/projects/daq2/kcu105/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
@@ -13,9 +11,6 @@ adi_project_files daq2_kcu105 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
 adi_project_run daq2_kcu105
 
 
diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v
index fbf439919..4af3f1aa8 100644
--- a/projects/daq2/kcu105/system_top.v
+++ b/projects/daq2/kcu105/system_top.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -326,8 +324,14 @@ module system_top (
     .phy_clk_clk_p (phy_clk_p),
     .phy_rst_n (phy_rst_n),
     .phy_sd (1'b1),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
     .rx_ref_clk (rx_ref_clk),
     .rx_sync (rx_sync),
     .rx_sysref (rx_sysref),
@@ -345,8 +349,14 @@ module system_top (
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
     .tx_ref_clk (tx_ref_clk),
     .tx_sync (tx_sync),
     .tx_sysref (tx_sysref),

From 0b0aa8e6c0b4259f99dca17caea47a9d7b9fd9a6 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 11 Aug 2016 17:46:54 +0300
Subject: [PATCH 396/972] Makefile: Add MMU option to altera makefiles

---
 projects/adrv9371x/a10soc/Makefile  | 6 ++++++
 projects/arradio/c5soc/Makefile     | 6 ++++++
 projects/common/a5gte/Makefile      | 6 ++++++
 projects/daq3/a10gx/Makefile        | 6 ++++++
 projects/fmcjesdadc1/a5gt/Makefile  | 6 ++++++
 projects/fmcjesdadc1/a5soc/Makefile | 6 ++++++
 projects/fmcomms2/a10gx/Makefile    | 6 ++++++
 projects/usdrx1/a5gt/Makefile       | 6 ++++++
 8 files changed, 48 insertions(+)

diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 2870fb421..ffb050c77 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 2b74027c2..0c42d4a71 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
diff --git a/projects/common/a5gte/Makefile b/projects/common/a5gte/Makefile
index b0e931ef0..d782facbf 100644
--- a/projects/common/a5gte/Makefile
+++ b/projects/common/a5gte/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index bb4b08976..190c0bc8c 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_top.v
 M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index 6a52e19bd..9f80abb77 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 27db0a706..99701e708 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 4c1ed9ca0..62b1ca6e1 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_top.v
 M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index 301866b75..8850eed3e 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -5,6 +5,12 @@
 ####################################################################################
 ####################################################################################
 
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
 M_DEPS += system_project.tcl
 M_DEPS += ../common/usdrx1_spi.v
 M_DEPS += ../../scripts/adi_env.tcl

From 39c1c83d002cdee7dd506a6633172db5166f84a4 Mon Sep 17 00:00:00 2001
From: Dragos Bogdan <dragos.bogdan@analog.com>
Date: Fri, 12 Aug 2016 10:07:11 +0300
Subject: [PATCH 397/972] adrv9371x/a10soc: Fix spi_csn assignment

---
 projects/adrv9371x/a10soc/system_project.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/adrv9371x/a10soc/system_project.tcl b/projects/adrv9371x/a10soc/system_project.tcl
index 49e6487e8..21612194e 100644
--- a/projects/adrv9371x/a10soc/system_project.tcl
+++ b/projects/adrv9371x/a10soc/system_project.tcl
@@ -71,8 +71,8 @@ set_instance_assignment -name IO_STANDARD LVDS -to sysref
 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref
 
-set_location_assignment PIN_A12   -to spi_csn_ad9528        ; ## D15  FMC_HPC_LA09_N
-set_location_assignment PIN_A13   -to spi_csn_ad9371        ; ## D14  FMC_HPC_LA09_P
+set_location_assignment PIN_A13   -to spi_csn_ad9528        ; ## D15  FMC_HPC_LA09_N
+set_location_assignment PIN_A12   -to spi_csn_ad9371        ; ## D14  FMC_HPC_LA09_P
 set_location_assignment PIN_A9    -to spi_clk               ; ## H13  FMC_HPC_LA07_P
 set_location_assignment PIN_B9    -to spi_mosi              ; ## H14  FMC_HPC_LA07_N
 set_location_assignment PIN_B11   -to spi_miso              ; ## G12  FMC_HPC_LA08_P

From e754f0a46a94a7ce9d139fbb0140ecb1094e4ee9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Sun, 14 Aug 2016 11:21:19 -0400
Subject: [PATCH 398/972] up_axi- writes dropped by delayed w-responses

---
 library/common/up_axi.v | 88 +++++++++++++++++------------------------
 1 file changed, 36 insertions(+), 52 deletions(-)

diff --git a/library/common/up_axi.v b/library/common/up_axi.v
index 2d5e3e503..db62e659a 100644
--- a/library/common/up_axi.v
+++ b/library/common/up_axi.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -123,24 +121,27 @@ module up_axi (
   reg             up_axi_awready = 'd0;
   reg             up_axi_wready = 'd0;
   reg             up_axi_bvalid = 'd0;
+  reg             up_wack_d = 'd0;
   reg             up_wsel = 'd0;
   reg             up_wreq = 'd0;
   reg     [AW:0]  up_waddr = 'd0;
   reg     [31:0]  up_wdata = 'd0;
-  reg     [ 2:0]  up_wcount = 'd0;
-  reg             up_wack_int = 'd0;
-  reg             up_wack_int_d = 'd0;
+  reg     [ 4:0]  up_wcount = 'd0;
   reg             up_axi_arready = 'd0;
   reg             up_axi_rvalid = 'd0;
   reg     [31:0]  up_axi_rdata = 'd0;
+  reg             up_rack_d = 'd0;
+  reg     [31:0]  up_rdata_d = 'd0;
   reg             up_rsel = 'd0;
   reg             up_rreq = 'd0;
   reg     [AW:0]  up_raddr = 'd0;
   reg     [ 4:0]  up_rcount = 'd0;
-  reg             up_rack_int = 'd0;
-  reg     [31:0]  up_rdata_int = 'd0;
-  reg             up_rack_int_d = 'd0;
-  reg     [31:0]  up_rdata_int_d = 'd0;
+
+  // internal signals
+
+  wire            up_wack_s;
+  wire            up_rack_s;
+  wire    [31:0]  up_rdata_s;
 
   // write channel interface
 
@@ -154,30 +155,34 @@ module up_axi (
     end else begin
       if (up_axi_awready == 1'b1) begin
         up_axi_awready <= 1'b0;
-      end else if (up_wack_int == 1'b1) begin
+      end else if (up_wack_s == 1'b1) begin
         up_axi_awready <= 1'b1;
       end
       if (up_axi_wready == 1'b1) begin
         up_axi_wready <= 1'b0;
-      end else if (up_wack_int == 1'b1) begin
+      end else if (up_wack_s == 1'b1) begin
         up_axi_wready <= 1'b1;
       end
       if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
         up_axi_bvalid <= 1'b0;
-      end else if (up_wack_int_d == 1'b1) begin
+      end else if (up_wack_d == 1'b1) begin
         up_axi_bvalid <= 1'b1;
       end
     end
   end
 
+  assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
+      up_wack_d <= 'd0;
       up_wsel <= 'd0;
       up_wreq <= 'd0;
       up_waddr <= 'd0;
       up_wdata <= 'd0;
       up_wcount <= 'd0;
     end else begin
+      up_wack_d <= up_wack_s;
       if (up_wsel == 1'b1) begin
         if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
           up_wsel <= 1'b0;
@@ -185,28 +190,19 @@ module up_axi (
         up_wreq <= 1'b0;
         up_waddr <= up_waddr;
         up_wdata <= up_wdata;
-        up_wcount <= up_wcount + 1'b1;
       end else begin
         up_wsel <= up_axi_awvalid & up_axi_wvalid;
         up_wreq <= up_axi_awvalid & up_axi_wvalid;
         up_waddr <= up_axi_awaddr[AW+2:2];
         up_wdata <= up_axi_wdata;
-        up_wcount <= 3'd0;
       end
-    end
-  end
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_wack_int <= 'd0;
-      up_wack_int_d <= 'd0;
-    end else begin
-      if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin
-        up_wack_int <= 1'b1;
-      end else if (up_wsel == 1'b1) begin
-        up_wack_int <= up_wack;
+      if (up_wack_s == 1'b1) begin
+        up_wcount <= 5'h00;
+      end else if (up_wcount[4] == 1'b1) begin
+        up_wcount <= up_wcount + 1'b1;
+      end else if (up_wreq == 1'b1) begin
+        up_wcount <= 5'h10;
       end
-      up_wack_int_d <= up_wack_int;
     end
   end
 
@@ -222,26 +218,33 @@ module up_axi (
     end else begin
       if (up_axi_arready == 1'b1) begin
         up_axi_arready <= 1'b0;
-      end else if (up_rack_int == 1'b1) begin
+      end else if (up_rack_s == 1'b1) begin
         up_axi_arready <= 1'b1;
       end
       if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
         up_axi_rvalid <= 1'b0;
         up_axi_rdata <= 32'd0;
-      end else if (up_rack_int_d == 1'b1) begin
+      end else if (up_rack_d == 1'b1) begin
         up_axi_rvalid <= 1'b1;
-        up_axi_rdata <= up_rdata_int_d;
+        up_axi_rdata <= up_rdata_d;
       end
     end
   end
 
+  assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
+  assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
+      up_rack_d <= 'd0;
+      up_rdata_d <= 'd0;
       up_rsel <= 'd0;
       up_rreq <= 'd0;
       up_raddr <= 'd0;
       up_rcount <= 'd0;
     end else begin
+      up_rack_d <= up_rack_s;
+      up_rdata_d <= up_rdata_s;
       if (up_rsel == 1'b1) begin
         if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
           up_rsel <= 1'b0;
@@ -253,35 +256,16 @@ module up_axi (
         up_rreq <= up_axi_arvalid;
         up_raddr <= up_axi_araddr[AW+2:2];
       end
-      if (up_rack_int == 1'b1) begin
-        up_rcount <= 5'd0;
+      if (up_rack_s == 1'b1) begin
+        up_rcount <= 5'h00;
       end else if (up_rcount[4] == 1'b1) begin
         up_rcount <= up_rcount + 1'b1;
       end else if (up_rreq == 1'b1) begin
-        up_rcount <= 5'd16;
+        up_rcount <= 5'h10;
       end
     end
   end
 
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_rack_int <= 'd0;
-      up_rdata_int <= 'd0;
-      up_rack_int_d <= 'd0;
-      up_rdata_int_d <= 'd0;
-    end else begin
-      if ((up_rcount == 5'h1f) && (up_rack == 1'b0)) begin
-        up_rack_int <= 1'b1;
-        up_rdata_int <= {2{16'hdead}};
-      end else begin
-        up_rack_int <= up_rack;
-        up_rdata_int <= up_rdata;
-      end
-      up_rack_int_d <= up_rack_int;
-      up_rdata_int_d <= up_rdata_int;
-    end
-  end
-
 endmodule
 
 // ***************************************************************************

From 4658686ae1d59e864a6e9dc32b845ddc30a76823 Mon Sep 17 00:00:00 2001
From: dbogdan <dragos.bogdan@analog.com>
Date: Tue, 16 Aug 2016 11:56:25 +0300
Subject: [PATCH 399/972] adrv9371x/a10soc: Misc changes for being able to run
 Linux

---
 projects/adrv9371x/a10soc/system_bd.qsys     |  67 +++++++++++-
 projects/adrv9371x/a10soc/system_top.v       |  40 ++++----
 projects/adrv9371x/common/adrv9371x_bd.qsys  | 101 +++++++++++++++++++
 projects/common/a10soc/a10soc_system_bd.qsys |   8 +-
 4 files changed, 190 insertions(+), 26 deletions(-)

diff --git a/projects/adrv9371x/a10soc/system_bd.qsys b/projects/adrv9371x/a10soc/system_bd.qsys
index 5ead260a9..a900e1ab1 100644
--- a/projects/adrv9371x/a10soc/system_bd.qsys
+++ b/projects/adrv9371x/a10soc/system_bd.qsys
@@ -41,6 +41,22 @@
          type = "String";
       }
    }
+   element adrv9371x.avl_gpio_i
+   {
+      datum baseAddress
+      {
+         value = "222464";
+         type = "String";
+      }
+   }
+   element adrv9371x.avl_gpio_o
+   {
+      datum baseAddress
+      {
+         value = "222720";
+         type = "String";
+      }
+   }
    element adrv9371x.avl_rx_jesd
    {
       datum baseAddress
@@ -57,6 +73,14 @@
          type = "String";
       }
    }
+   element adrv9371x.avl_spi
+   {
+      datum baseAddress
+      {
+         value = "222976";
+         type = "String";
+      }
+   }
    element adrv9371x.avl_tx_jesd
    {
       datum baseAddress
@@ -375,6 +399,8 @@
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface name="gpio" internal="adrv9371x.ad9371_gpio" type="conduit" dir="end" />
+ <interface name="gpio_i" internal="adrv9371x.gpio_i" type="conduit" dir="end" />
+ <interface name="gpio_o" internal="adrv9371x.gpio_o" type="conduit" dir="end" />
  <interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
  <interface
    name="hps_ddr_oct"
@@ -386,7 +412,7 @@
    internal="a10soc.hps_ddr_ref_clk"
    type="clock"
    dir="end" />
- <interface name="hps_gpio" internal="a10soc.hps_gpio" type="conduit" dir="end" />
+ <interface name="hps_gpio" internal="a10soc.hps_gpio" />
  <interface name="hps_io" internal="a10soc.hps_io" type="conduit" dir="end" />
  <interface name="hps_spi0" internal="a10soc.hps_spi0" type="conduit" dir="end" />
  <interface
@@ -427,6 +453,7 @@
    internal="adrv9371x.rx_sysref"
    type="conduit"
    dir="end" />
+ <interface name="spi" internal="adrv9371x.spi" type="conduit" dir="end" />
  <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
  <interface
    name="sys_reset"
@@ -448,12 +475,12 @@
   <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="1" />
   <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
   <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="15" />
+  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="31" />
   <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="0" />
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /><slave name='adrv9371x_gpio_i.s1' start='0x36500' end='0x36510' /><slave name='adrv9371x_gpio_o.s1' start='0x36600' end='0x36620' /><slave name='adrv9371x_spi.spi_control_port' start='0x36700' end='0x36720' /></address-map>]]></parameter>
   <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
   <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
  </module>
@@ -518,6 +545,24 @@
   <parameter name="baseAddress" value="0x00036400" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_gpio_i">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00036500" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_gpio_o">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00036600" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="avalon"
    version="15.1"
@@ -536,6 +581,15 @@
   <parameter name="baseAddress" value="0x00035c00" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_spi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00036700" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="avalon"
    version="15.1"
@@ -642,6 +696,13 @@
    end="adrv9371x.axi_dac_dma_intr">
   <parameter name="irqNumber" value="2" />
  </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="a10soc.hps_irq0"
+   end="adrv9371x.spi_irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
  <connection
    kind="reset"
    version="15.1"
diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v
index 6d2213529..4e34c4d56 100644
--- a/projects/adrv9371x/a10soc/system_top.v
+++ b/projects/adrv9371x/a10soc/system_top.v
@@ -187,8 +187,6 @@ module system_top (
     .hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
     .hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
     .hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
-    .hps_gpio_gp_in (gpio_i),
-    .hps_gpio_gp_out (gpio_o),
     .hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
     .hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
     .hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
@@ -233,15 +231,15 @@ module system_top (
     .hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
     .hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
     .hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
-    .hps_spi0_mosi_o (spi_mosi),
-    .hps_spi0_miso_i (spi_miso),
+    .hps_spi0_mosi_o (),
+    .hps_spi0_miso_i (),
     .hps_spi0_ss_in_n (1'b1),
     .hps_spi0_mosi_oe (),
-    .hps_spi0_ss0_n_o (spi_csn_ad9528),
-    .hps_spi0_ss1_n_o (spi_csn_ad9371),
+    .hps_spi0_ss0_n_o (),
+    .hps_spi0_ss1_n_o (),
     .hps_spi0_ss2_n_o (),
     .hps_spi0_ss3_n_o (),
-    .hps_spi0_sclk_clk (spi_clk),
+    .hps_spi0_sclk_clk (),
     .hps_spi1_mosi_o (),
     .hps_spi1_miso_i (1'b0),
     .hps_spi1_ss_in_n (1'b1),
@@ -252,17 +250,23 @@ module system_top (
     .hps_spi1_ss3_n_o (),
     .hps_spi1_sclk_clk (),
     .ref_clk_clk (ref_clk1),
-		.rx_data_rx_serial_data (rx_data[1:0]),
-		.rx_os_data_rx_serial_data (rx_data[3:2]),
-		.rx_os_sync_rx_sync (rx_os_sync),
-		.rx_os_sysref_rx_ext_sysref_in (sysref),
-		.rx_sync_rx_sync (rx_sync),
-		.rx_sysref_rx_ext_sysref_in (sysref),
-		.sys_clk_clk (sys_clk),
-		.sys_reset_reset_n (sys_resetn),
-		.tx_data_tx_serial_data (tx_data),
-		.tx_sync_tx_sync (tx_sync),
-		.tx_sysref_tx_ext_sysref_in (sysref));
+    .rx_data_rx_serial_data (rx_data[1:0]),
+    .rx_os_data_rx_serial_data (rx_data[3:2]),
+    .rx_os_sync_rx_sync (rx_os_sync),
+    .rx_os_sysref_rx_ext_sysref_in (sysref),
+    .rx_sync_rx_sync (rx_sync),
+    .rx_sysref_rx_ext_sysref_in (sysref),
+    .sys_clk_clk (sys_clk),
+    .sys_reset_reset_n (sys_resetn),
+    .tx_data_tx_serial_data (tx_data),
+    .tx_sync_tx_sync (tx_sync),
+    .tx_sysref_tx_ext_sysref_in (sysref),
+    .gpio_i_export (gpio_i),
+    .gpio_o_export (gpio_o),
+    .spi_MISO (spi_miso),
+    .spi_MOSI (spi_mosi),
+    .spi_SCLK (spi_clk),
+    .spi_SS_n ({spi_csn_ad9528, spi_csn_ad9371}));
 
 endmodule
 
diff --git a/projects/adrv9371x/common/adrv9371x_bd.qsys b/projects/adrv9371x/common/adrv9371x_bd.qsys
index 8f1721be9..babd6c137 100755
--- a/projects/adrv9371x/common/adrv9371x_bd.qsys
+++ b/projects/adrv9371x/common/adrv9371x_bd.qsys
@@ -181,6 +181,30 @@
          type = "boolean";
       }
    }
+   element gpio_i
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element gpio_o
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element spi
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
    element sys_clk
    {
       datum _sortIndex
@@ -313,6 +337,8 @@
    internal="ad9371_gpio.s1"
    type="avalon"
    dir="end" />
+ <interface name="avl_gpio_i" internal="gpio_i.s1" type="avalon" dir="end" />
+ <interface name="avl_gpio_o" internal="gpio_o.s1" type="avalon" dir="end" />
  <interface
    name="avl_rx_jesd"
    internal="xcvr_rx_core.jesd204_rx_avs"
@@ -325,6 +351,11 @@
    dir="end" />
  <interface name="avl_rx_os_xcvr" internal="xcvr_rx_os_core.reconfig_avmm" />
  <interface name="avl_rx_xcvr" internal="xcvr_rx_core.reconfig_avmm" />
+ <interface
+   name="avl_spi"
+   internal="spi.spi_control_port"
+   type="avalon"
+   dir="end" />
  <interface
    name="avl_tx_jesd"
    internal="xcvr_tx_core.jesd204_tx_avs"
@@ -404,6 +435,16 @@
    internal="axi_os_jesd_xcvr.s_axi"
    type="axi4lite"
    dir="end" />
+ <interface
+   name="gpio_i"
+   internal="gpio_i.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="gpio_o"
+   internal="gpio_o.external_connection"
+   type="conduit"
+   dir="end" />
  <interface
    name="rx_data"
    internal="xcvr_rx_core.rx_serial_data"
@@ -434,6 +475,8 @@
    internal="axi_jesd_xcvr.if_rx_ext_sysref_in"
    type="conduit"
    dir="end" />
+ <interface name="spi" internal="spi.external" type="conduit" dir="end" />
+ <interface name="spi_irq" internal="spi.irq" type="interrupt" dir="end" />
  <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
  <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
  <interface
@@ -558,6 +601,50 @@
   <parameter name="CHANNEL_DATA_WIDTH" value="32" />
   <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
+ <module name="gpio_i" kind="altera_avalon_pio" version="15.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module name="gpio_o" kind="altera_avalon_pio" version="15.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="true" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module name="spi" kind="altera_avalon_spi" version="15.1" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="1" />
+  <parameter name="clockPolarity" value="1" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="50000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="2" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="5000000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
  <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
@@ -1240,6 +1327,9 @@
    version="15.1"
    start="sys_clk.out_clk"
    end="ad9371_gpio.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio_o.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio_i.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="spi.clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -2134,6 +2224,17 @@
    version="15.1"
    start="sys_rst.out_reset"
    end="ad9371_gpio.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="gpio_o.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="gpio_i.reset" />
+ <connection kind="reset" version="15.1" start="sys_rst.out_reset" end="spi.reset" />
  <connection
    kind="reset"
    version="15.1"
diff --git a/projects/common/a10soc/a10soc_system_bd.qsys b/projects/common/a10soc/a10soc_system_bd.qsys
index e999e15d9..75a5ae281 100644
--- a/projects/common/a10soc/a10soc_system_bd.qsys
+++ b/projects/common/a10soc/a10soc_system_bd.qsys
@@ -311,9 +311,7 @@
    dir="end" />
  <interface
    name="hps_gpio"
-   internal="arria10_hps_0.h2f_gp"
-   type="conduit"
-   dir="end" />
+   internal="arria10_hps_0.h2f_gp" />
  <interface
    name="hps_io"
    internal="arria10_hps_0.hps_io"
@@ -470,7 +468,7 @@
   <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
   <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
   <parameter name="GPIO_REF_CLK" value="4" />
-  <parameter name="GP_Enable" value="true" />
+  <parameter name="GP_Enable" value="false" />
   <parameter name="H2F_AXI_CLOCK_FREQ" value="100" />
   <parameter name="H2F_COLD_RST_Enable" value="false" />
   <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
@@ -1556,7 +1554,7 @@
   <parameter name="PIPELINE_RESPONSE" value="1" />
   <parameter name="SYMBOL_WIDTH" value="8" />
   <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
   <parameter name="USE_RESPONSE" value="0" />
  </module>
  <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">

From 5c27ccd1fa4d4044da484f9f590645021f02fb37 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 16 Aug 2016 15:34:10 +0300
Subject: [PATCH 400/972] adrv9371x: Added common qsys tcl

---
 projects/adrv9371x/common/adrv9371x_qsys.tcl | 713 +++++++++++++++++++
 1 file changed, 713 insertions(+)
 create mode 100644 projects/adrv9371x/common/adrv9371x_qsys.tcl

diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
new file mode 100644
index 000000000..ddbd00121
--- /dev/null
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -0,0 +1,713 @@
+
+add_instance xcvr_ref_clk altera_clock_bridge 16.0
+set_instance_parameter_value xcvr_ref_clk {EXPLICIT_CLOCK_RATE} {0.0}
+set_instance_parameter_value xcvr_ref_clk {NUM_CLOCK_OUTPUTS} {1}
+
+add_instance xcvr_pll altera_iopll 16.0
+set_instance_parameter_value xcvr_pll {gui_device_speed_grade} {1}
+set_instance_parameter_value xcvr_pll {gui_en_reconf} {1}
+set_instance_parameter_value xcvr_pll {gui_en_dps_ports} {0}
+set_instance_parameter_value xcvr_pll {gui_pll_mode} {Integer-N PLL}
+set_instance_parameter_value xcvr_pll {gui_reference_clock_frequency} {122.88}
+set_instance_parameter_value xcvr_pll {gui_fractional_cout} {32}
+set_instance_parameter_value xcvr_pll {gui_dsm_out_sel} {1st_order}
+set_instance_parameter_value xcvr_pll {gui_use_locked} {0}
+set_instance_parameter_value xcvr_pll {gui_en_adv_params} {0}
+set_instance_parameter_value xcvr_pll {gui_pll_bandwidth_preset} {Low}
+set_instance_parameter_value xcvr_pll {gui_lock_setting} {Low Lock Time}
+set_instance_parameter_value xcvr_pll {gui_pll_auto_reset} {0}
+set_instance_parameter_value xcvr_pll {gui_en_lvds_ports} {Disabled}
+set_instance_parameter_value xcvr_pll {gui_operation_mode} {direct}
+set_instance_parameter_value xcvr_pll {gui_feedback_clock} {Global Clock}
+set_instance_parameter_value xcvr_pll {gui_clock_to_compensate} {0}
+set_instance_parameter_value xcvr_pll {gui_use_NDFB_modes} {0}
+set_instance_parameter_value xcvr_pll {gui_refclk_switch} {0}
+set_instance_parameter_value xcvr_pll {gui_refclk1_frequency} {100.0}
+set_instance_parameter_value xcvr_pll {gui_en_phout_ports} {0}
+set_instance_parameter_value xcvr_pll {gui_phout_division} {1}
+set_instance_parameter_value xcvr_pll {gui_en_extclkout_ports} {0}
+set_instance_parameter_value xcvr_pll {gui_number_of_clocks} {3}
+set_instance_parameter_value xcvr_pll {gui_multiply_factor} {6}
+set_instance_parameter_value xcvr_pll {gui_divide_factor_n} {1}
+set_instance_parameter_value xcvr_pll {gui_frac_multiply_factor} {1.0}
+set_instance_parameter_value xcvr_pll {gui_fix_vco_frequency} {0}
+set_instance_parameter_value xcvr_pll {gui_fixed_vco_frequency} {600.0}
+set_instance_parameter_value xcvr_pll {gui_vco_frequency} {600.0}
+set_instance_parameter_value xcvr_pll {gui_enable_output_counter_cascading} {0}
+set_instance_parameter_value xcvr_pll {gui_mif_gen_options} {Generate New MIF File}
+set_instance_parameter_value xcvr_pll {gui_new_mif_file_path} {~/pll.mif}
+set_instance_parameter_value xcvr_pll {gui_existing_mif_file_path} {~/pll.mif}
+set_instance_parameter_value xcvr_pll {gui_mif_config_name} {unnamed}
+set_instance_parameter_value xcvr_pll {gui_active_clk} {0}
+set_instance_parameter_value xcvr_pll {gui_clk_bad} {0}
+set_instance_parameter_value xcvr_pll {gui_switchover_mode} {Automatic Switchover}
+set_instance_parameter_value xcvr_pll {gui_switchover_delay} {0}
+set_instance_parameter_value xcvr_pll {gui_enable_cascade_out} {0}
+set_instance_parameter_value xcvr_pll {gui_cascade_outclk_index} {0}
+set_instance_parameter_value xcvr_pll {gui_enable_cascade_in} {0}
+set_instance_parameter_value xcvr_pll {gui_pll_cascading_mode} {adjpllin}
+set_instance_parameter_value xcvr_pll {gui_enable_mif_dps} {0}
+set_instance_parameter_value xcvr_pll {gui_dps_cntr} {C0}
+set_instance_parameter_value xcvr_pll {gui_dps_num} {1}
+set_instance_parameter_value xcvr_pll {gui_dps_dir} {Positive}
+set_instance_parameter_value xcvr_pll {gui_extclkout_0_source} {C0}
+set_instance_parameter_value xcvr_pll {gui_extclkout_1_source} {C0}
+set_instance_parameter_value xcvr_pll {gui_clock_name_global} {0}
+set_instance_parameter_value xcvr_pll {gui_clock_name_string0} {tx_dac_clk}
+set_instance_parameter_value xcvr_pll {gui_clock_name_string1} {rx_adc_clk}
+set_instance_parameter_value xcvr_pll {gui_clock_name_string2} {rx_adc_os_clk}
+set_instance_parameter_value xcvr_pll {gui_divide_factor_c0} {6}
+set_instance_parameter_value xcvr_pll {gui_divide_factor_c1} {6}
+set_instance_parameter_value xcvr_pll {gui_divide_factor_c2} {6}
+set_instance_parameter_value xcvr_pll {gui_cascade_counter0} {0}
+set_instance_parameter_value xcvr_pll {gui_cascade_counter1} {0}
+set_instance_parameter_value xcvr_pll {gui_cascade_counter2} {0}
+set_instance_parameter_value xcvr_pll {gui_output_clock_frequency0} {122.88}
+set_instance_parameter_value xcvr_pll {gui_output_clock_frequency1} {122.88}
+set_instance_parameter_value xcvr_pll {gui_output_clock_frequency2} {122.88}
+set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency0} {100.0}
+set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency1} {100.0}
+set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency2} {100.0}
+set_instance_parameter_value xcvr_pll {gui_ps_units0} {ps}
+set_instance_parameter_value xcvr_pll {gui_ps_units1} {ps}
+set_instance_parameter_value xcvr_pll {gui_ps_units2} {ps}
+set_instance_parameter_value xcvr_pll {gui_phase_shift0} {0.0}
+set_instance_parameter_value xcvr_pll {gui_phase_shift1} {0.0}
+set_instance_parameter_value xcvr_pll {gui_phase_shift2} {0.0}
+set_instance_parameter_value xcvr_pll {gui_phase_shift_deg0} {0.0}
+set_instance_parameter_value xcvr_pll {gui_phase_shift_deg1} {0.0}
+set_instance_parameter_value xcvr_pll {gui_phase_shift_deg2} {0.0}
+set_instance_parameter_value xcvr_pll {gui_actual_phase_shift0} {0.0}
+set_instance_parameter_value xcvr_pll {gui_actual_phase_shift1} {0.0}
+set_instance_parameter_value xcvr_pll {gui_actual_phase_shift2} {0.0}
+set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg0} {0.0}
+set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg1} {0.0}
+set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg2} {0.0}
+set_instance_parameter_value xcvr_pll {gui_duty_cycle0} {50.0}
+set_instance_parameter_value xcvr_pll {gui_duty_cycle1} {50.0}
+set_instance_parameter_value xcvr_pll {gui_duty_cycle2} {50.0}
+set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle0} {50.0}
+set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle1} {50.0}
+set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle2} {50.0}
+
+add_instance xcvr_pll_reconfig altera_pll_reconfig 16.0
+set_instance_parameter_value xcvr_pll_reconfig {ENABLE_MIF} {0}
+set_instance_parameter_value xcvr_pll_reconfig {MIF_FILE_NAME} {}
+set_instance_parameter_value xcvr_pll_reconfig {ENABLE_BYTEENABLE} {0}
+
+add_instance xcvr_tx_rst_cntrl altera_xcvr_reset_control 16.0
+set_instance_parameter_value xcvr_tx_rst_cntrl {CHANNELS} {4}
+set_instance_parameter_value xcvr_tx_rst_cntrl {PLLS} {1}
+set_instance_parameter_value xcvr_tx_rst_cntrl {SYS_CLK_IN_MHZ} {100}
+set_instance_parameter_value xcvr_tx_rst_cntrl {SYNCHRONIZE_RESET} {1}
+set_instance_parameter_value xcvr_tx_rst_cntrl {REDUCED_SIM_TIME} {1}
+set_instance_parameter_value xcvr_tx_rst_cntrl {gui_split_interfaces} {0}
+set_instance_parameter_value xcvr_tx_rst_cntrl {TX_PLL_ENABLE} {1}
+set_instance_parameter_value xcvr_tx_rst_cntrl {T_PLL_POWERDOWN} {1000}
+set_instance_parameter_value xcvr_tx_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0}
+set_instance_parameter_value xcvr_tx_rst_cntrl {TX_ENABLE} {1}
+set_instance_parameter_value xcvr_tx_rst_cntrl {TX_PER_CHANNEL} {0}
+set_instance_parameter_value xcvr_tx_rst_cntrl {gui_tx_auto_reset} {0}
+set_instance_parameter_value xcvr_tx_rst_cntrl {T_TX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_tx_rst_cntrl {T_TX_DIGITALRESET} {70000}
+set_instance_parameter_value xcvr_tx_rst_cntrl {T_PLL_LOCK_HYST} {0}
+set_instance_parameter_value xcvr_tx_rst_cntrl {gui_pll_cal_busy} {1}
+set_instance_parameter_value xcvr_tx_rst_cntrl {RX_ENABLE} {0}
+set_instance_parameter_value xcvr_tx_rst_cntrl {RX_PER_CHANNEL} {0}
+set_instance_parameter_value xcvr_tx_rst_cntrl {gui_rx_auto_reset} {0}
+set_instance_parameter_value xcvr_tx_rst_cntrl {T_RX_ANALOGRESET} {40}
+set_instance_parameter_value xcvr_tx_rst_cntrl {T_RX_DIGITALRESET} {4000}
+
+add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 16.0
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_debug} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_jtag_enable} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_enable_avmm_busy_port} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_user_identifier} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_file_prefix} {altera_xcvr_atx_pll_a10}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_sv_file_enable} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_h_file_enable} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_txt_file_enable} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_mif_file_enable} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_multi_enable} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_profile_cnt} {2}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_profile_select} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_param_vals1} {}
+set_instance_parameter_value xcvr_tx_lane_pll {rcfg_param_vals2} {}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_manual_configuration} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {generate_docs} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {generate_add_hdl_instance_example} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {test_mode} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_pld_atx_cal_busy_port} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_debug_ports_parameters} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {support_mode} {user_mode}
+set_instance_parameter_value xcvr_tx_lane_pll {message_level} {error}
+set_instance_parameter_value xcvr_tx_lane_pll {prot_mode} {Basic}
+set_instance_parameter_value xcvr_tx_lane_pll {bw_sel} {medium}
+set_instance_parameter_value xcvr_tx_lane_pll {refclk_cnt} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {refclk_index} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {silicon_rev} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {primary_pll_buffer} {GX clock output buffer}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_8G_path} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_16G_path} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_pcie_clk} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_cascade_out} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_atx_to_fpll_cascade_out} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_hip_cal_done_port} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_hip_cal_en} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {2457.6}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_fractional} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {122.88}
+set_instance_parameter_value xcvr_tx_lane_pll {set_manual_reference_clock_frequency} {200.0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_fref_clock_frequency} {156.25}
+set_instance_parameter_value xcvr_tx_lane_pll {select_manual_config} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_m_counter} {24}
+set_instance_parameter_value xcvr_tx_lane_pll {set_ref_clk_div} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_l_counter} {16}
+set_instance_parameter_value xcvr_tx_lane_pll {set_l_cascade_counter} {15}
+set_instance_parameter_value xcvr_tx_lane_pll {set_l_cascade_predivider} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {set_k_counter} {2000000000.0}
+set_instance_parameter_value xcvr_tx_lane_pll {set_altera_xcvr_atx_pll_a10_calibration_en} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_analog_resets} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_mcgb} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {mcgb_div} {1}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_hfreq_clk} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_mcgb_pcie_clksw} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {mcgb_aux_clkin_cnt} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_bonding_clks} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_fb_comp_bonding} {0}
+set_instance_parameter_value xcvr_tx_lane_pll {pma_width} {64}
+set_instance_parameter_value xcvr_tx_lane_pll {enable_pld_mcgb_cal_busy_port} {0}
+
+add_instance xcvr_tx_core altera_jesd204 16.0
+set_instance_parameter_value xcvr_tx_core {wrapper_opt} {base_phy}
+set_instance_parameter_value xcvr_tx_core {sdc_constraint} {1.0}
+set_instance_parameter_value xcvr_tx_core {DATA_PATH} {TX}
+set_instance_parameter_value xcvr_tx_core {SUBCLASSV} {1}
+set_instance_parameter_value xcvr_tx_core {lane_rate} {4915.2}
+set_instance_parameter_value xcvr_tx_core {PCS_CONFIG} {JESD_PCS_CFG1}
+set_instance_parameter_value xcvr_tx_core {pll_type} {CMU}
+set_instance_parameter_value xcvr_tx_core {bonded_mode} {non_bonded}
+set_instance_parameter_value xcvr_tx_core {REFCLK_FREQ} {125.0}
+set_instance_parameter_value xcvr_tx_core {bitrev_en} {0}
+set_instance_parameter_value xcvr_tx_core {pll_reconfig_enable} {0}
+set_instance_parameter_value xcvr_tx_core {rcfg_jtag_enable} {0}
+set_instance_parameter_value xcvr_tx_core {set_capability_reg_enable} {0}
+set_instance_parameter_value xcvr_tx_core {set_user_identifier} {0}
+set_instance_parameter_value xcvr_tx_core {set_csr_soft_logic_enable} {0}
+set_instance_parameter_value xcvr_tx_core {set_prbs_soft_logic_enable} {0}
+set_instance_parameter_value xcvr_tx_core {L} {4}
+set_instance_parameter_value xcvr_tx_core {M} {4}
+set_instance_parameter_value xcvr_tx_core {GUI_EN_CFG_F} {0}
+set_instance_parameter_value xcvr_tx_core {GUI_CFG_F} {4}
+set_instance_parameter_value xcvr_tx_core {N} {16}
+set_instance_parameter_value xcvr_tx_core {N_PRIME} {16}
+set_instance_parameter_value xcvr_tx_core {S} {1}
+set_instance_parameter_value xcvr_tx_core {K} {32}
+set_instance_parameter_value xcvr_tx_core {SCR} {1}
+set_instance_parameter_value xcvr_tx_core {CS} {0}
+set_instance_parameter_value xcvr_tx_core {CF} {0}
+set_instance_parameter_value xcvr_tx_core {HD} {0}
+set_instance_parameter_value xcvr_tx_core {ECC_EN} {0}
+set_instance_parameter_value xcvr_tx_core {DLB_TEST} {0}
+set_instance_parameter_value xcvr_tx_core {PHADJ} {0}
+set_instance_parameter_value xcvr_tx_core {ADJCNT} {0}
+set_instance_parameter_value xcvr_tx_core {ADJDIR} {0}
+set_instance_parameter_value xcvr_tx_core {OPTIMIZE} {0}
+set_instance_parameter_value xcvr_tx_core {DID} {0}
+set_instance_parameter_value xcvr_tx_core {BID} {0}
+set_instance_parameter_value xcvr_tx_core {LID0} {0}
+set_instance_parameter_value xcvr_tx_core {LID1} {1}
+set_instance_parameter_value xcvr_tx_core {LID2} {2}
+set_instance_parameter_value xcvr_tx_core {LID3} {3}
+set_instance_parameter_value xcvr_tx_core {LID4} {4}
+set_instance_parameter_value xcvr_tx_core {LID5} {5}
+set_instance_parameter_value xcvr_tx_core {LID6} {6}
+set_instance_parameter_value xcvr_tx_core {LID7} {7}
+set_instance_parameter_value xcvr_tx_core {JESDV} {1}
+set_instance_parameter_value xcvr_tx_core {RES1} {0}
+set_instance_parameter_value xcvr_tx_core {RES2} {0}
+set_instance_parameter_value xcvr_tx_core {TEST_COMPONENTS_EN} {0}
+set_instance_parameter_value xcvr_tx_core {TERMINATE_RECONFIG_EN} {0}
+set_instance_parameter_value xcvr_tx_core {ED_GENERIC_5SERIES} {No}
+set_instance_parameter_value xcvr_tx_core {ED_GENERIC_A10} {No}
+set_instance_parameter_value xcvr_tx_core {ED_FILESET_SIM} {0}
+set_instance_parameter_value xcvr_tx_core {ED_FILESET_SYNTH} {0}
+set_instance_parameter_value xcvr_tx_core {ED_HDL_FORMAT_SIM} {VERILOG}
+set_instance_parameter_value xcvr_tx_core {ED_HDL_FORMAT_SYNTH} {VERILOG}
+set_instance_parameter_value xcvr_tx_core {ED_DEV_KIT} {NONE}
+
+add_instance axi_jesd_xcvr axi_jesd_xcvr 1.0
+set_instance_parameter_value axi_jesd_xcvr {ID} {0}
+set_instance_parameter_value axi_jesd_xcvr {DEVICE_TYPE} {0}
+set_instance_parameter_value axi_jesd_xcvr {TX_NUM_OF_LANES} {4}
+set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {2}
+
+add_instance xcvr_rx_rst_cntrl altera_xcvr_reset_control 16.0
+set_instance_parameter_value xcvr_rx_rst_cntrl {CHANNELS} {2}
+set_instance_parameter_value xcvr_rx_rst_cntrl {PLLS} {1}
+set_instance_parameter_value xcvr_rx_rst_cntrl {SYS_CLK_IN_MHZ} {100}
+set_instance_parameter_value xcvr_rx_rst_cntrl {SYNCHRONIZE_RESET} {1}
+set_instance_parameter_value xcvr_rx_rst_cntrl {REDUCED_SIM_TIME} {1}
+set_instance_parameter_value xcvr_rx_rst_cntrl {gui_split_interfaces} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {TX_PLL_ENABLE} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {T_PLL_POWERDOWN} {1000}
+set_instance_parameter_value xcvr_rx_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {TX_ENABLE} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {TX_PER_CHANNEL} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {gui_tx_auto_reset} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {T_TX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_rx_rst_cntrl {T_TX_DIGITALRESET} {70000}
+set_instance_parameter_value xcvr_rx_rst_cntrl {T_PLL_LOCK_HYST} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {gui_pll_cal_busy} {1}
+set_instance_parameter_value xcvr_rx_rst_cntrl {RX_ENABLE} {1}
+set_instance_parameter_value xcvr_rx_rst_cntrl {RX_PER_CHANNEL} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {gui_rx_auto_reset} {0}
+set_instance_parameter_value xcvr_rx_rst_cntrl {T_RX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_rx_rst_cntrl {T_RX_DIGITALRESET} {4000}
+
+add_instance xcvr_rx_core altera_jesd204 16.0
+set_instance_parameter_value xcvr_rx_core {wrapper_opt} {base_phy}
+set_instance_parameter_value xcvr_rx_core {sdc_constraint} {1.0}
+set_instance_parameter_value xcvr_rx_core {DATA_PATH} {RX}
+set_instance_parameter_value xcvr_rx_core {SUBCLASSV} {1}
+set_instance_parameter_value xcvr_rx_core {lane_rate} {4915.2}
+set_instance_parameter_value xcvr_rx_core {PCS_CONFIG} {JESD_PCS_CFG1}
+set_instance_parameter_value xcvr_rx_core {pll_type} {CMU}
+set_instance_parameter_value xcvr_rx_core {bonded_mode} {non_bonded}
+set_instance_parameter_value xcvr_rx_core {REFCLK_FREQ} {122.88}
+set_instance_parameter_value xcvr_rx_core {bitrev_en} {0}
+set_instance_parameter_value xcvr_rx_core {pll_reconfig_enable} {1}
+set_instance_parameter_value xcvr_rx_core {rcfg_jtag_enable} {0}
+set_instance_parameter_value xcvr_rx_core {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_rx_core {set_user_identifier} {0}
+set_instance_parameter_value xcvr_rx_core {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_rx_core {set_prbs_soft_logic_enable} {0}
+set_instance_parameter_value xcvr_rx_core {L} {2}
+set_instance_parameter_value xcvr_rx_core {M} {4}
+set_instance_parameter_value xcvr_rx_core {GUI_EN_CFG_F} {0}
+set_instance_parameter_value xcvr_rx_core {GUI_CFG_F} {4}
+set_instance_parameter_value xcvr_rx_core {N} {16}
+set_instance_parameter_value xcvr_rx_core {N_PRIME} {16}
+set_instance_parameter_value xcvr_rx_core {S} {1}
+set_instance_parameter_value xcvr_rx_core {K} {32}
+set_instance_parameter_value xcvr_rx_core {SCR} {1}
+set_instance_parameter_value xcvr_rx_core {CS} {0}
+set_instance_parameter_value xcvr_rx_core {CF} {0}
+set_instance_parameter_value xcvr_rx_core {HD} {0}
+set_instance_parameter_value xcvr_rx_core {ECC_EN} {0}
+set_instance_parameter_value xcvr_rx_core {DLB_TEST} {0}
+set_instance_parameter_value xcvr_rx_core {PHADJ} {0}
+set_instance_parameter_value xcvr_rx_core {ADJCNT} {0}
+set_instance_parameter_value xcvr_rx_core {ADJDIR} {0}
+set_instance_parameter_value xcvr_rx_core {OPTIMIZE} {0}
+set_instance_parameter_value xcvr_rx_core {DID} {0}
+set_instance_parameter_value xcvr_rx_core {BID} {0}
+set_instance_parameter_value xcvr_rx_core {LID0} {0}
+set_instance_parameter_value xcvr_rx_core {LID1} {1}
+set_instance_parameter_value xcvr_rx_core {LID2} {2}
+set_instance_parameter_value xcvr_rx_core {LID3} {3}
+set_instance_parameter_value xcvr_rx_core {LID4} {4}
+set_instance_parameter_value xcvr_rx_core {LID5} {5}
+set_instance_parameter_value xcvr_rx_core {LID6} {6}
+set_instance_parameter_value xcvr_rx_core {LID7} {7}
+set_instance_parameter_value xcvr_rx_core {JESDV} {1}
+set_instance_parameter_value xcvr_rx_core {RES1} {0}
+set_instance_parameter_value xcvr_rx_core {RES2} {0}
+set_instance_parameter_value xcvr_rx_core {TEST_COMPONENTS_EN} {0}
+set_instance_parameter_value xcvr_rx_core {TERMINATE_RECONFIG_EN} {0}
+set_instance_parameter_value xcvr_rx_core {ED_GENERIC_5SERIES} {No}
+set_instance_parameter_value xcvr_rx_core {ED_GENERIC_A10} {No}
+set_instance_parameter_value xcvr_rx_core {ED_FILESET_SIM} {0}
+set_instance_parameter_value xcvr_rx_core {ED_FILESET_SYNTH} {0}
+set_instance_parameter_value xcvr_rx_core {ED_HDL_FORMAT_SIM} {VERILOG}
+set_instance_parameter_value xcvr_rx_core {ED_HDL_FORMAT_SYNTH} {VERILOG}
+set_instance_parameter_value xcvr_rx_core {ED_DEV_KIT} {NONE}
+
+add_instance axi_os_jesd_xcvr axi_jesd_xcvr 1.0
+set_instance_parameter_value axi_os_jesd_xcvr {ID} {1}
+set_instance_parameter_value axi_os_jesd_xcvr {DEVICE_TYPE} {0}
+set_instance_parameter_value axi_os_jesd_xcvr {TX_NUM_OF_LANES} {0}
+set_instance_parameter_value axi_os_jesd_xcvr {RX_NUM_OF_LANES} {2}
+
+add_instance xcvr_rx_os_rst_cntrl altera_xcvr_reset_control 16.0
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {CHANNELS} {2}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {PLLS} {1}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYS_CLK_IN_MHZ} {100}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYNCHRONIZE_RESET} {1}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {REDUCED_SIM_TIME} {1}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_split_interfaces} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_PLL_ENABLE} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_PLL_POWERDOWN} {1000}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_ENABLE} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_PER_CHANNEL} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_tx_auto_reset} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_TX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_TX_DIGITALRESET} {70000}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_PLL_LOCK_HYST} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_pll_cal_busy} {1}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {RX_ENABLE} {1}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {RX_PER_CHANNEL} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_rx_auto_reset} {0}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_RX_ANALOGRESET} {70000}
+set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_RX_DIGITALRESET} {4000}
+
+add_instance xcvr_rx_os_core altera_jesd204 16.0
+set_instance_parameter_value xcvr_rx_os_core {wrapper_opt} {base_phy}
+set_instance_parameter_value xcvr_rx_os_core {sdc_constraint} {1.0}
+set_instance_parameter_value xcvr_rx_os_core {DATA_PATH} {RX}
+set_instance_parameter_value xcvr_rx_os_core {SUBCLASSV} {1}
+set_instance_parameter_value xcvr_rx_os_core {lane_rate} {4915.2}
+set_instance_parameter_value xcvr_rx_os_core {PCS_CONFIG} {JESD_PCS_CFG1}
+set_instance_parameter_value xcvr_rx_os_core {pll_type} {CMU}
+set_instance_parameter_value xcvr_rx_os_core {bonded_mode} {non_bonded}
+set_instance_parameter_value xcvr_rx_os_core {REFCLK_FREQ} {122.88}
+set_instance_parameter_value xcvr_rx_os_core {bitrev_en} {0}
+set_instance_parameter_value xcvr_rx_os_core {pll_reconfig_enable} {1}
+set_instance_parameter_value xcvr_rx_os_core {rcfg_jtag_enable} {0}
+set_instance_parameter_value xcvr_rx_os_core {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_rx_os_core {set_user_identifier} {0}
+set_instance_parameter_value xcvr_rx_os_core {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_rx_os_core {set_prbs_soft_logic_enable} {0}
+set_instance_parameter_value xcvr_rx_os_core {L} {2}
+set_instance_parameter_value xcvr_rx_os_core {M} {2}
+set_instance_parameter_value xcvr_rx_os_core {GUI_EN_CFG_F} {0}
+set_instance_parameter_value xcvr_rx_os_core {GUI_CFG_F} {4}
+set_instance_parameter_value xcvr_rx_os_core {N} {16}
+set_instance_parameter_value xcvr_rx_os_core {N_PRIME} {16}
+set_instance_parameter_value xcvr_rx_os_core {S} {1}
+set_instance_parameter_value xcvr_rx_os_core {K} {16}
+set_instance_parameter_value xcvr_rx_os_core {SCR} {1}
+set_instance_parameter_value xcvr_rx_os_core {CS} {0}
+set_instance_parameter_value xcvr_rx_os_core {CF} {0}
+set_instance_parameter_value xcvr_rx_os_core {HD} {0}
+set_instance_parameter_value xcvr_rx_os_core {ECC_EN} {0}
+set_instance_parameter_value xcvr_rx_os_core {DLB_TEST} {0}
+set_instance_parameter_value xcvr_rx_os_core {PHADJ} {0}
+set_instance_parameter_value xcvr_rx_os_core {ADJCNT} {0}
+set_instance_parameter_value xcvr_rx_os_core {ADJDIR} {0}
+set_instance_parameter_value xcvr_rx_os_core {OPTIMIZE} {0}
+set_instance_parameter_value xcvr_rx_os_core {DID} {0}
+set_instance_parameter_value xcvr_rx_os_core {BID} {0}
+set_instance_parameter_value xcvr_rx_os_core {LID0} {0}
+set_instance_parameter_value xcvr_rx_os_core {LID1} {1}
+set_instance_parameter_value xcvr_rx_os_core {LID2} {2}
+set_instance_parameter_value xcvr_rx_os_core {LID3} {3}
+set_instance_parameter_value xcvr_rx_os_core {LID4} {4}
+set_instance_parameter_value xcvr_rx_os_core {LID5} {5}
+set_instance_parameter_value xcvr_rx_os_core {LID6} {6}
+set_instance_parameter_value xcvr_rx_os_core {LID7} {7}
+set_instance_parameter_value xcvr_rx_os_core {JESDV} {1}
+set_instance_parameter_value xcvr_rx_os_core {RES1} {0}
+set_instance_parameter_value xcvr_rx_os_core {RES2} {0}
+set_instance_parameter_value xcvr_rx_os_core {TEST_COMPONENTS_EN} {0}
+set_instance_parameter_value xcvr_rx_os_core {TERMINATE_RECONFIG_EN} {0}
+set_instance_parameter_value xcvr_rx_os_core {ED_GENERIC_5SERIES} {No}
+set_instance_parameter_value xcvr_rx_os_core {ED_GENERIC_A10} {No}
+set_instance_parameter_value xcvr_rx_os_core {ED_FILESET_SIM} {0}
+set_instance_parameter_value xcvr_rx_os_core {ED_FILESET_SYNTH} {0}
+set_instance_parameter_value xcvr_rx_os_core {ED_HDL_FORMAT_SIM} {VERILOG}
+set_instance_parameter_value xcvr_rx_os_core {ED_HDL_FORMAT_SYNTH} {VERILOG}
+set_instance_parameter_value xcvr_rx_os_core {ED_DEV_KIT} {NONE}
+
+add_instance axi_ad9371 axi_ad9371 1.0
+set_instance_parameter_value axi_ad9371 {ID} {0}
+set_instance_parameter_value axi_ad9371 {DAC_DATAPATH_DISABLE} {0}
+set_instance_parameter_value axi_ad9371 {ADC_DATAPATH_DISABLE} {0}
+
+add_instance adc_pack util_cpack 1.0
+set_instance_parameter_value adc_pack {CHANNEL_DATA_WIDTH} {16}
+set_instance_parameter_value adc_pack {NUM_OF_CHANNELS} {4}
+
+add_instance dac_upack util_upack 1.0
+set_instance_parameter_value dac_upack {CHANNEL_DATA_WIDTH} {32}
+set_instance_parameter_value dac_upack {NUM_OF_CHANNELS} {4}
+
+add_instance adc_os_pack util_cpack 1.0
+set_instance_parameter_value adc_os_pack {CHANNEL_DATA_WIDTH} {32}
+set_instance_parameter_value adc_os_pack {NUM_OF_CHANNELS} {2}
+
+add_instance axi_adc_dma axi_dmac 1.0
+set_instance_parameter_value axi_adc_dma {ID} {0}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
+set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
+set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
+
+add_instance axi_os_adc_dma axi_dmac 1.0
+set_instance_parameter_value axi_os_adc_dma {ID} {0}
+set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_os_adc_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_os_adc_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_os_adc_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_os_adc_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_os_adc_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_os_adc_dma {CYCLIC} {0}
+set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_SRC} {2}
+set_instance_parameter_value axi_os_adc_dma {FIFO_SIZE} {4}
+
+add_instance axi_dac_dma axi_dmac 1.0
+set_instance_parameter_value axi_dac_dma {ID} {0}
+set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {128}
+set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
+set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
+set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
+
+add_instance ad9371_gpio altera_avalon_pio 16.0
+set_instance_parameter_value ad9371_gpio {bitClearingEdgeCapReg} {0}
+set_instance_parameter_value ad9371_gpio {bitModifyingOutReg} {1}
+set_instance_parameter_value ad9371_gpio {captureEdge} {0}
+set_instance_parameter_value ad9371_gpio {direction} {Bidir}
+set_instance_parameter_value ad9371_gpio {edgeType} {RISING}
+set_instance_parameter_value ad9371_gpio {generateIRQ} {0}
+set_instance_parameter_value ad9371_gpio {irqType} {LEVEL}
+set_instance_parameter_value ad9371_gpio {resetValue} {0.0}
+set_instance_parameter_value ad9371_gpio {simDoTestBenchWiring} {0}
+set_instance_parameter_value ad9371_gpio {simDrivenValue} {0.0}
+set_instance_parameter_value ad9371_gpio {width} {19}
+
+# connections
+
+add_connection axi_jesd_xcvr.if_tx_ip_avl xcvr_tx_core.jesd204_tx_link
+
+add_connection xcvr_rx_core.jesd204_rx_link axi_jesd_xcvr.if_rx_ip_avl
+
+add_connection xcvr_rx_os_core.jesd204_rx_link axi_os_jesd_xcvr.if_rx_ip_avl
+
+add_connection sys_clk.clk xcvr_tx_rst_cntrl.clock
+add_connection sys_clk.clk xcvr_rx_rst_cntrl.clock
+add_connection sys_clk.clk xcvr_rx_os_rst_cntrl.clock
+add_connection sys_clk.clk xcvr_rx_core.jesd204_rx_avs_clk
+add_connection sys_clk.clk xcvr_rx_os_core.jesd204_rx_avs_clk
+add_connection sys_clk.clk xcvr_tx_core.jesd204_tx_avs_clk
+add_connection sys_clk.clk axi_adc_dma.m_dest_axi_clock
+add_connection sys_clk.clk axi_os_adc_dma.m_dest_axi_clock
+add_connection sys_clk.clk axi_dac_dma.m_src_axi_clock
+add_connection sys_clk.clk xcvr_pll_reconfig.mgmt_clk
+add_connection sys_clk.clk xcvr_rx_core.reconfig_clk
+add_connection sys_clk.clk xcvr_rx_os_core.reconfig_clk
+add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0
+add_connection sys_clk.clk axi_adc_dma.s_axi_clock
+add_connection sys_clk.clk axi_dac_dma.s_axi_clock
+add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
+add_connection sys_clk.clk axi_os_jesd_xcvr.s_axi_clock
+add_connection sys_clk.clk axi_ad9371.s_axi_clock
+add_connection sys_clk.clk axi_os_adc_dma.s_axi_clock
+add_connection sys_clk.clk ad9371_gpio.clk
+
+add_connection sys_clk.clk_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n
+add_connection sys_clk.clk_reset xcvr_tx_core.jesd204_tx_avs_rst_n
+add_connection sys_clk.clk_reset axi_adc_dma.m_dest_axi_reset
+add_connection sys_clk.clk_reset axi_os_adc_dma.m_dest_axi_reset
+add_connection sys_clk.clk_reset axi_dac_dma.m_src_axi_reset
+add_connection sys_clk.clk_reset xcvr_pll_reconfig.mgmt_reset
+add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
+add_connection sys_clk.clk_reset xcvr_pll.reset
+add_connection sys_clk.clk_reset xcvr_rx_rst_cntrl.reset
+add_connection sys_clk.clk_reset xcvr_tx_rst_cntrl.reset
+add_connection sys_clk.clk_reset xcvr_rx_os_rst_cntrl.reset
+add_connection sys_clk.clk_reset xcvr_rx_core.reconfig_reset
+add_connection sys_clk.clk_reset xcvr_rx_os_core.reconfig_reset
+add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
+add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
+add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
+add_connection sys_clk.clk_reset axi_os_jesd_xcvr.s_axi_reset
+add_connection sys_clk.clk_reset axi_ad9371.s_axi_reset
+add_connection sys_clk.clk_reset axi_os_adc_dma.s_axi_reset
+add_connection sys_clk.clk_reset ad9371_gpio.reset
+
+add_connection xcvr_pll.outclk0 axi_ad9371.if_dac_clk
+add_connection xcvr_pll.outclk0 dac_upack.if_dac_clk
+add_connection xcvr_pll.outclk0 axi_dac_dma.if_fifo_rd_clk
+add_connection xcvr_pll.outclk0 axi_jesd_xcvr.if_tx_clk
+add_connection xcvr_pll.outclk0 xcvr_tx_core.txlink_clk
+add_connection xcvr_pll.outclk1 adc_pack.if_adc_clk
+add_connection xcvr_pll.outclk1 axi_ad9371.if_adc_clk
+add_connection xcvr_pll.outclk1 axi_adc_dma.if_fifo_wr_clk
+add_connection xcvr_pll.outclk1 axi_jesd_xcvr.if_rx_clk
+add_connection xcvr_pll.outclk1 xcvr_rx_core.rxlink_clk
+add_connection xcvr_pll.outclk2 adc_os_pack.if_adc_clk
+add_connection xcvr_pll.outclk2 axi_ad9371.if_adc_os_clk
+add_connection xcvr_pll.outclk2 axi_os_adc_dma.if_fifo_wr_clk
+add_connection xcvr_pll.outclk2 axi_os_jesd_xcvr.if_rx_clk
+add_connection xcvr_pll.outclk2 xcvr_rx_os_core.rxlink_clk
+
+add_connection adc_pack.adc_ch_0 axi_ad9371.adc_ch_0
+add_connection axi_ad9371.adc_ch_1 adc_pack.adc_ch_1
+add_connection adc_pack.adc_ch_2 axi_ad9371.adc_ch_2
+add_connection axi_ad9371.adc_ch_3 adc_pack.adc_ch_3
+
+add_connection adc_os_pack.adc_ch_0 axi_ad9371.adc_os_ch_0
+add_connection axi_ad9371.adc_os_ch_1 adc_os_pack.adc_ch_1
+
+add_connection xcvr_rx_os_core.alldev_lane_aligned xcvr_rx_os_core.dev_lane_aligned
+
+add_connection dac_upack.dac_ch_0 axi_ad9371.dac_ch_0
+add_connection axi_ad9371.dac_ch_1 dac_upack.dac_ch_1
+add_connection dac_upack.dac_ch_2 axi_ad9371.dac_ch_2
+add_connection axi_ad9371.dac_ch_3 dac_upack.dac_ch_3
+
+add_connection xcvr_rx_core.dev_lane_aligned xcvr_rx_core.alldev_lane_aligned
+add_connection xcvr_rx_core.dev_sync_n axi_jesd_xcvr.if_rx_ip_sync
+add_connection xcvr_tx_core.dev_sync_n xcvr_tx_core.mdev_sync_n
+add_connection adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
+add_connection adc_os_pack.if_adc_data axi_os_adc_dma.if_fifo_wr_din
+add_connection axi_ad9371.if_adc_rx_data axi_jesd_xcvr.if_rx_data
+add_connection axi_ad9371.if_adc_rx_os_data axi_os_jesd_xcvr.if_rx_data
+add_connection adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
+add_connection adc_os_pack.if_adc_sync axi_os_adc_dma.if_fifo_wr_sync
+add_connection adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
+add_connection dac_upack.if_dac_data axi_dac_dma.if_fifo_rd_dout
+add_connection axi_dac_dma.if_fifo_rd_en dac_upack.if_dac_valid
+add_connection axi_dac_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf
+add_connection axi_os_adc_dma.if_fifo_wr_en adc_os_pack.if_adc_valid
+add_connection axi_adc_dma.if_fifo_wr_overflow axi_ad9371.if_adc_dovf
+add_connection axi_os_adc_dma.if_fifo_wr_overflow axi_ad9371.if_adc_os_dovf
+add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_rx_core.sof
+add_connection axi_os_jesd_xcvr.if_rx_ip_sync xcvr_rx_os_core.dev_sync_n
+add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_rx_core.sysref
+add_connection axi_jesd_xcvr.if_rx_ready xcvr_rx_rst_cntrl.rx_ready
+add_connection axi_jesd_xcvr.if_tx_data axi_ad9371.if_dac_tx_data
+add_connection axi_jesd_xcvr.if_tx_ip_sync xcvr_tx_core.sync_n
+add_connection axi_jesd_xcvr.if_tx_ip_sysref xcvr_tx_core.sysref
+add_connection xcvr_tx_lane_pll.pll_cal_busy xcvr_tx_rst_cntrl.pll_cal_busy
+add_connection xcvr_tx_lane_pll.pll_locked xcvr_tx_rst_cntrl.pll_locked
+add_connection xcvr_tx_lane_pll.pll_powerdown xcvr_tx_rst_cntrl.pll_powerdown
+add_connection xcvr_pll_reconfig.reconfig_from_pll xcvr_pll.reconfig_from_pll
+add_connection xcvr_pll_reconfig.reconfig_to_pll xcvr_pll.reconfig_to_pll
+add_connection xcvr_rx_core.rx_analogreset xcvr_rx_rst_cntrl.rx_analogreset
+add_connection xcvr_rx_os_core.rx_analogreset xcvr_rx_os_rst_cntrl.rx_analogreset
+add_connection xcvr_rx_rst_cntrl.rx_cal_busy xcvr_rx_core.rx_cal_busy
+add_connection xcvr_rx_os_rst_cntrl.rx_cal_busy xcvr_rx_os_core.rx_cal_busy
+add_connection xcvr_rx_rst_cntrl.rx_digitalreset xcvr_rx_core.rx_digitalreset
+add_connection xcvr_rx_os_rst_cntrl.rx_digitalreset xcvr_rx_os_core.rx_digitalreset
+add_connection xcvr_rx_core.rx_islockedtodata xcvr_rx_rst_cntrl.rx_is_lockedtodata
+add_connection xcvr_rx_os_core.rx_islockedtodata xcvr_rx_os_rst_cntrl.rx_is_lockedtodata
+add_connection xcvr_rx_os_rst_cntrl.rx_ready axi_os_jesd_xcvr.if_rx_ready
+add_connection xcvr_rx_os_core.sof axi_os_jesd_xcvr.if_rx_ip_sof
+add_connection xcvr_rx_os_core.sysref axi_os_jesd_xcvr.if_rx_ip_sysref
+add_connection xcvr_tx_core.tx_analogreset xcvr_tx_rst_cntrl.tx_analogreset
+add_connection xcvr_tx_core.tx_cal_busy xcvr_tx_rst_cntrl.tx_cal_busy
+add_connection xcvr_tx_rst_cntrl.tx_digitalreset xcvr_tx_core.tx_digitalreset
+add_connection xcvr_tx_rst_cntrl.tx_ready axi_jesd_xcvr.if_tx_ready
+
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch0
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch1
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch2
+add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch3
+add_connection axi_jesd_xcvr.if_rst xcvr_tx_rst_cntrl.reset
+add_connection axi_os_jesd_xcvr.if_rst xcvr_rx_os_rst_cntrl.reset
+add_connection axi_jesd_xcvr.if_rx_rstn adc_pack.if_adc_rst
+add_connection axi_os_jesd_xcvr.if_rx_rstn adc_os_pack.if_adc_rst
+add_connection axi_jesd_xcvr.if_rx_rstn xcvr_rx_core.rxlink_rst_n
+add_connection axi_os_jesd_xcvr.if_rx_rstn xcvr_rx_os_core.rxlink_rst_n
+add_connection axi_jesd_xcvr.if_tx_rstn xcvr_tx_core.txlink_rst_n
+
+add_connection sys_clk.clk_reset xcvr_rx_core.jesd204_rx_avs_rst_n
+
+add_interface rx_data conduit end
+set_interface_property rx_data EXPORT_OF xcvr_rx_core.rx_serial_data
+add_interface rx_os_data conduit end
+set_interface_property rx_os_data EXPORT_OF xcvr_rx_os_core.rx_serial_data
+add_interface rx_os_sync conduit end
+set_interface_property rx_os_sync EXPORT_OF axi_os_jesd_xcvr.if_rx_sync
+add_interface rx_os_sysref conduit end
+set_interface_property rx_os_sysref EXPORT_OF axi_os_jesd_xcvr.if_rx_ext_sysref_in
+add_interface rx_sync conduit end
+set_interface_property rx_sync EXPORT_OF axi_jesd_xcvr.if_rx_sync
+add_interface rx_sysref conduit end
+set_interface_property rx_sysref EXPORT_OF axi_jesd_xcvr.if_rx_ext_sysref_in
+add_interface tx_data conduit end
+set_interface_property tx_data EXPORT_OF xcvr_tx_core.tx_serial_data
+add_interface tx_sync conduit end
+set_interface_property tx_sync EXPORT_OF axi_jesd_xcvr.if_tx_sync
+add_interface tx_sysref conduit end
+set_interface_property tx_sysref EXPORT_OF axi_jesd_xcvr.if_tx_ext_sysref_in
+
+add_interface xcvr_ref_clk clock sink
+set_interface_property xcvr_ref_clk EXPORT_OF xcvr_ref_clk.in_clk
+
+add_connection xcvr_ref_clk.out_clk xcvr_pll.refclk
+add_connection xcvr_ref_clk.out_clk xcvr_rx_core.pll_ref_clk
+add_connection xcvr_ref_clk.out_clk xcvr_rx_os_core.pll_ref_clk
+add_connection xcvr_ref_clk.out_clk xcvr_tx_lane_pll.pll_refclk0
+
+add_interface ad9371_gpio conduit end
+set_interface_property ad9371_gpio EXPORT_OF ad9371_gpio.external_connection
+
+# addresses
+
+add_connection sys_cpu.data_master xcvr_pll_reconfig.mgmt_avalon_slave
+add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
+add_connection sys_cpu.data_master axi_adc_dma.s_axi
+add_connection sys_cpu.data_master axi_dac_dma.s_axi
+add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
+add_connection sys_cpu.data_master axi_os_jesd_xcvr.s_axi
+add_connection sys_cpu.data_master axi_ad9371.s_axi
+add_connection sys_cpu.data_master axi_os_adc_dma.s_axi
+add_connection sys_cpu.data_master xcvr_rx_core.reconfig_avmm
+add_connection sys_cpu.data_master xcvr_rx_core.jesd204_rx_avs
+add_connection sys_cpu.data_master xcvr_rx_os_core.reconfig_avmm
+add_connection sys_cpu.data_master xcvr_rx_os_core.jesd204_rx_avs
+add_connection sys_cpu.data_master ad9371_gpio.s1
+
+add_connection axi_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection axi_os_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection axi_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
+
+set_connection_parameter_value sys_cpu.data_master/xcvr_pll_reconfig.mgmt_avalon_slave  baseAddress {0x1003d800}
+set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0      baseAddress {0x1003c000}
+set_connection_parameter_value sys_cpu.data_master/axi_adc_dma.s_axi                    baseAddress {0x10034000}
+set_connection_parameter_value sys_cpu.data_master/axi_dac_dma.s_axi                    baseAddress {0x10010000}
+set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi                  baseAddress {0x10040000}
+set_connection_parameter_value sys_cpu.data_master/axi_os_jesd_xcvr.s_axi               baseAddress {0x10020000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9371.s_axi                     baseAddress {0x10000000}
+set_connection_parameter_value sys_cpu.data_master/axi_os_adc_dma.s_axi                 baseAddress {0x10500000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.reconfig_avmm           baseAddress {0x10030000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.jesd204_rx_avs          baseAddress {0x1003e400}
+set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.reconfig_avmm        baseAddress {0x10130000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.jesd204_rx_avs       baseAddress {0x1013e400}
+set_connection_parameter_value sys_cpu.data_master/ad9371_gpio.s1                       baseAddress {0x10060000}
+
+set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
+set_connection_parameter_value axi_os_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0      baseAddress {0x00000000}
+set_connection_parameter_value axi_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0          baseAddress {0x00000000}
+
+# interrupts
+
+add_connection sys_cpu.irq axi_adc_dma.interrupt_sender
+add_connection sys_cpu.irq axi_dac_dma.interrupt_sender
+add_connection sys_cpu.irq axi_os_adc_dma.interrupt_sender
+set_connection_parameter_value sys_cpu.irq/axi_adc_dma.interrupt_sender irqNumber {10}
+set_connection_parameter_value sys_cpu.irq/axi_dac_dma.interrupt_sender irqNumber {11}
+set_connection_parameter_value sys_cpu.irq/axi_os_adc_dma.interrupt_sender irqNumber {12}
+

From eb55f600fbdcb83d7ac3a0b98e9f9b163b6e55de Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 16 Aug 2016 15:50:46 +0300
Subject: [PATCH 401/972] adrv9371x: Initial commit

-need to fix dc filter module for AD9371 / altera
---
 projects/adrv9371x/Makefile                 |   3 +
 projects/adrv9371x/a10gx/Makefile           | 138 ++++++++++
 projects/adrv9371x/a10gx/system_constr.sdc  |  41 +++
 projects/adrv9371x/a10gx/system_project.tcl | 152 +++++++++++
 projects/adrv9371x/a10gx/system_qsys.tcl    |   8 +
 projects/adrv9371x/a10gx/system_top.v       | 275 ++++++++++++++++++++
 6 files changed, 617 insertions(+)
 create mode 100644 projects/adrv9371x/a10gx/Makefile
 create mode 100644 projects/adrv9371x/a10gx/system_constr.sdc
 create mode 100644 projects/adrv9371x/a10gx/system_project.tcl
 create mode 100644 projects/adrv9371x/a10gx/system_qsys.tcl
 create mode 100644 projects/adrv9371x/a10gx/system_top.v

diff --git a/projects/adrv9371x/Makefile b/projects/adrv9371x/Makefile
index feb85db28..4947b6146 100644
--- a/projects/adrv9371x/Makefile
+++ b/projects/adrv9371x/Makefile
@@ -7,16 +7,19 @@
 
 .PHONY: all clean clean-all 
 all:
+	-make -C a10gx all
 	-make -C a10soc all
 	-make -C zc706 all
 
 
 clean: 
+	make -C a10gx clean
 	make -C a10soc clean
 	make -C zc706 clean
 
 
 clean-all:
+	make -C a10gx clean-all
 	make -C a10soc clean-all
 	make -C zc706 clean-all
 
diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile
new file mode 100644
index 000000000..80479025b
--- /dev/null
+++ b/projects/adrv9371x/a10gx/Makefile
@@ -0,0 +1,138 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
+M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.sdc
+M_DEPS += ../common/adrv9371x_qsys.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_channel.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_os.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx.v
+M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx_channel.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/altera/common/ad_dcfilter.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_iqcor.v
+M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_xcvr.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+
+
+M_ALTERA := quartus_sh --64bit -t 
+
+
+M_FLIST += *.log
+M_FLIST += *_INFO.txt
+M_FLIST += *_dump.txt
+M_FLIST += db
+M_FLIST += *.asm.rpt
+M_FLIST += *.done
+M_FLIST += *.eda.rpt
+M_FLIST += *.fit.*
+M_FLIST += *.map.*
+M_FLIST += *.sta.*
+M_FLIST += *.qsf
+M_FLIST += *.qpf
+M_FLIST += *.qws
+M_FLIST += *.sof
+M_FLIST += *.cdf
+M_FLIST += *.sld
+M_FLIST += *.qdf
+M_FLIST += hc_output
+M_FLIST += system_bd
+M_FLIST += hps_isw_handoff
+M_FLIST += hps_sdram_*.csv
+M_FLIST += *ddr3_*.csv
+M_FLIST += incremental_db
+M_FLIST += reconfig_mif
+M_FLIST += *.sopcinfo
+M_FLIST +=  *.jdi
+M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
+
+
+
+.PHONY: all clean clean-all
+all: adrv9371x_a10gx.sof
+
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+adrv9371x_a10gx.sof: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_ALTERA) system_project.tcl  >> adrv9371x_a10gx_quartus.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/projects/adrv9371x/a10gx/system_constr.sdc b/projects/adrv9371x/a10gx/system_constr.sdc
new file mode 100644
index 000000000..1241a1b8f
--- /dev/null
+++ b/projects/adrv9371x/a10gx/system_constr.sdc
@@ -0,0 +1,41 @@
+
+create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
+create_clock -period  "8.139 ns"  -name ref_clk0_122mhz     [get_ports {ref_clk0}]
+create_clock -period  "8.139 ns"  -name ref_clk1_122mhz     [get_ports {ref_clk1}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
+
+set_false_path -from [get_clocks {sys_clk_100mhz}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
+
+set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
+  -through [get_nets *altera_jesd204_tx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
+  -through [get_nets *altera_jesd204_tx_ctl_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {sys_clk_100mhz}]
+
+
diff --git a/projects/adrv9371x/a10gx/system_project.tcl b/projects/adrv9371x/a10gx/system_project.tcl
new file mode 100644
index 000000000..884886fbd
--- /dev/null
+++ b/projects/adrv9371x/a10gx/system_project.tcl
@@ -0,0 +1,152 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new adrv9371x_a10gx -overwrite
+
+source "../../common/a10gx/a10gx_system_assign.tcl"
+
+set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name QSYS_FILE system_bd.qsys
+
+set_global_assignment -name SDC_FILE system_constr.sdc
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
+
+# lane interface
+
+set_location_assignment PIN_AL8   -to ref_clk0            ; ## D04  FMCA_GBTCLK0_M2C_P
+set_location_assignment PIN_AL7   -to "ref_clk0(n)"       ; ## D05  FMCA_GBTCLK0_M2C_N
+set_location_assignment PIN_AJ8   -to ref_clk1            ; ## B20  FMCA_GBTCLK1_M2C_P
+set_location_assignment PIN_AJ7   -to "ref_clk1(n)"       ; ## B21  FMCA_GBTCLK1_M2C_N
+set_location_assignment PIN_BA7   -to rx_data[0]          ; ## A02  FMCA_DP1_M2C_P
+set_location_assignment PIN_BA8   -to "rx_data[0](n)"     ; ## A03  FMCA_DP1_M2C_N
+set_location_assignment PIN_AY5   -to rx_data[1]          ; ## A06  FMCA_DP2_M2C_P
+set_location_assignment PIN_AY6   -to "rx_data[1](n)"     ; ## A07  FMCA_DP2_M2C_N
+set_location_assignment PIN_AW7   -to rx_data[2]          ; ## C06  FMCA_DP0_M2C_P
+set_location_assignment PIN_AW8   -to "rx_data[2](n)"     ; ## C07  FMCA_DP0_M2C_N
+set_location_assignment PIN_AV5   -to rx_data[3]          ; ## A10  FMCA_DP3_M2C_P
+set_location_assignment PIN_AV6   -to "rx_data[3](n)"     ; ## A11  FMCA_DP3_M2C_N
+set_location_assignment PIN_BD5   -to tx_data[0]          ; ## A22  FMCA_DP1_C2M_P (tx_data_p[0])
+set_location_assignment PIN_BD6   -to "tx_data[0](n)"     ; ## A23  FMCA_DP1_C2M_N (tx_data_n[0])
+set_location_assignment PIN_BB5   -to tx_data[1]          ; ## A26  FMCA_DP2_C2M_P (tx_data_p[1])
+set_location_assignment PIN_BB6   -to "tx_data[1](n)"     ; ## A27  FMCA_DP2_C2M_N (tx_data_n[1])
+set_location_assignment PIN_BC7   -to tx_data[2]          ; ## C02  FMCA_DP0_C2M_P (tx_data_p[2])
+set_location_assignment PIN_BC8   -to "tx_data[2](n)"     ; ## C03  FMCA_DP0_C2M_N (tx_data_n[2])
+set_location_assignment PIN_BC3   -to tx_data[3]          ; ## A30  FMCA_DP3_C2M_P (tx_data_p[3])
+set_location_assignment PIN_BC4   -to "tx_data[3](n)"     ; ## A31  FMCA_DP3_C2M_N (tx_data_n[3])
+
+
+set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0
+set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
+
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3]
+
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
+
+
+set_location_assignment PIN_AR20  -to rx_sync               ; ## G09  FMCA_HPC_LA03_P
+set_location_assignment PIN_AR19  -to rx_sync(n)            ; ## G10  FMCA_HPC_LA03_N
+set_location_assignment PIN_AY15  -to rx_os_sync            ; ## G27  FMCA_HPC_LA25_P (Sniffer)
+set_location_assignment PIN_AY14  -to rx_os_sync(n)         ; ## G28  FMCA_HPC_LA25_N (Sniffer)
+set_location_assignment PIN_AR22  -to tx_sync               ; ## H07  FMCA_HPC_LA02_P
+set_location_assignment PIN_AT22  -to tx_sync(n)            ; ## H08  FMCA_HPC_LA02_N
+set_location_assignment PIN_AY17  -to sysref                ; ## G36  FMCA_HPC_LA33_P
+set_location_assignment PIN_AW17  -to sysref(n)             ; ## G37  FMCA_HPC_LA33_N
+
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync
+set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to sysref
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref
+
+set_location_assignment PIN_AW13  -to spi_csn_ad9371        ; ## D14  FMCA_HPC_LA09_P
+set_location_assignment PIN_AV13  -to spi_csn_ad9528        ; ## D15  FMCA_HPC_LA09_N
+set_location_assignment PIN_AT17  -to spi_clk               ; ## H13  FMCA_HPC_LA07_P
+set_location_assignment PIN_AU17  -to spi_mosi              ; ## H14  FMCA_HPC_LA07_N
+set_location_assignment PIN_AP18  -to spi_miso              ; ## G12  FMCA_HPC_LA08_P
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9371
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
+set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
+
+set_location_assignment PIN_AT19  -to ad9528_reset_b        ; ## D26  FMCA_HPC_LA26_P
+set_location_assignment PIN_AT20  -to ad9528_sysref_req     ; ## D27  FMCA_HPC_LA26_N
+set_location_assignment PIN_AR17  -to ad9371_tx1_enable     ; ## D17  FMCA_HPC_LA13_P
+set_location_assignment PIN_AW18  -to ad9371_tx2_enable     ; ## C18  FMCA_HPC_LA14_P
+set_location_assignment PIN_AP17  -to ad9371_rx1_enable     ; ## D18  FMCA_HPC_LA13_N
+set_location_assignment PIN_AV18  -to ad9371_rx2_enable     ; ## C19  FMCA_HPC_LA14_N
+set_location_assignment PIN_AV11  -to ad9371_test           ; ## D11  FMCA_HPC_LA05_P (DNI/NC)
+set_location_assignment PIN_AN20  -to ad9371_reset_b        ; ## H10  FMCA_HPC_LA04_P
+set_location_assignment PIN_AP19  -to ad9371_gpint          ; ## H11  FMCA_HPC_LA04_N
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx1_enable
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx2_enable
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx1_enable
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx2_enable
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_test
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_reset_b
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpint
+
+# single ended default
+
+set_location_assignment PIN_AR9   -to ad9371_gpio[0]        ; ## H19  FMCA_HPC_LA15_P
+set_location_assignment PIN_AT9   -to ad9371_gpio[1]        ; ## H20  FMCA_HPC_LA15_N
+set_location_assignment PIN_AT13  -to ad9371_gpio[2]        ; ## G18  FMCA_HPC_LA16_P
+set_location_assignment PIN_AU13  -to ad9371_gpio[3]        ; ## G19  FMCA_HPC_LA16_N
+set_location_assignment PIN_AY10  -to ad9371_gpio[4]        ; ## H25  FMCA_HPC_LA21_P
+set_location_assignment PIN_AY11  -to ad9371_gpio[5]        ; ## H26  FMCA_HPC_LA21_N
+set_location_assignment PIN_AU21  -to ad9371_gpio[6]        ; ## C22  FMCA_HPC_LA18_CC_P
+set_location_assignment PIN_AV21  -to ad9371_gpio[7]        ; ## C23  FMCA_HPC_LA18_CC_N
+set_location_assignment PIN_AY12  -to ad9371_gpio[8]        ; ## G25  FMCA_HPC_LA22_N     (LVDS_1N)
+set_location_assignment PIN_AU11  -to ad9371_gpio[9]        ; ## H22  FMCA_HPC_LA19_P     (LVDS_2P)
+set_location_assignment PIN_AU12  -to ad9371_gpio[10]       ; ## H23  FMCA_HPC_LA19_N     (LVDS_2N)
+set_location_assignment PIN_AU8   -to ad9371_gpio[11]       ; ## G21  FMCA_HPC_LA20_P     (LVDS_3P)
+set_location_assignment PIN_AT8   -to ad9371_gpio[12]       ; ## G22  FMCA_HPC_LA20_N     (LVDS_3N)
+set_location_assignment PIN_BA14  -to ad9371_gpio[13]       ; ## G31  FMCA_HPC_LA29_N     (LVDS_4N)
+set_location_assignment PIN_BA15  -to ad9371_gpio[14]       ; ## G30  FMCA_HPC_LA29_P     (LVDS_4P)
+set_location_assignment PIN_AW12  -to ad9371_gpio[15]       ; ## G24  FMCA_HPC_LA22_P     (LVDS_1P)
+set_location_assignment PIN_AP16  -to ad9371_gpio[16]       ; ## G16  FMCA_HPC_LA12_N     (LVDS_5N)
+set_location_assignment PIN_AR16  -to ad9371_gpio[17]       ; ## G15  FMCA_HPC_LA12_P     (LVDS_5P)
+set_location_assignment PIN_AW11  -to ad9371_gpio[18]       ; ## D12  FMCA_HPC_LA05_N
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[11]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[12]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[13]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[14]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[15]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[16]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[17]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[18]
+
+execute_flow -compile
+
diff --git a/projects/adrv9371x/a10gx/system_qsys.tcl b/projects/adrv9371x/a10gx/system_qsys.tcl
new file mode 100644
index 000000000..0af153b03
--- /dev/null
+++ b/projects/adrv9371x/a10gx/system_qsys.tcl
@@ -0,0 +1,8 @@
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
+source ../common/adrv9371x_qsys.tcl
+
+save_system "system_bd.qsys"
+
diff --git a/projects/adrv9371x/a10gx/system_top.v b/projects/adrv9371x/a10gx/system_top.v
new file mode 100644
index 000000000..d07c82e2b
--- /dev/null
+++ b/projects/adrv9371x/a10gx/system_top.v
@@ -0,0 +1,275 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  sys_clk,
+  sys_resetn,
+
+  // ddr3
+
+  ddr3_clk_p,
+  ddr3_clk_n,
+  ddr3_a,
+  ddr3_ba,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_odt,
+  ddr3_reset_n,
+  ddr3_we_n,
+  ddr3_ras_n,
+  ddr3_cas_n,
+  ddr3_dqs_p,
+  ddr3_dqs_n,
+  ddr3_dq,
+  ddr3_dm,
+  ddr3_rzq,
+  ddr3_ref_clk,
+
+  // ethernet
+
+  eth_ref_clk,
+  eth_rxd,
+  eth_txd,
+  eth_mdc,
+  eth_mdio,
+  eth_resetn,
+  eth_intn,
+
+  // board gpio
+
+  gpio_bd_i,
+  gpio_bd_o,
+
+  // lane interface
+
+  ref_clk0,
+  ref_clk1,
+  rx_data,
+  tx_data,
+  rx_sync,
+  rx_os_sync,
+  tx_sync,
+  sysref,
+
+  ad9528_reset_b,
+  ad9528_sysref_req,
+  ad9371_tx1_enable,
+  ad9371_tx2_enable,
+  ad9371_rx1_enable,
+  ad9371_rx2_enable,
+  ad9371_test,
+  ad9371_reset_b,
+  ad9371_gpint,
+  ad9371_gpio,
+
+  spi_csn_ad9528,
+  spi_csn_ad9371,
+  spi_clk,
+  spi_mosi,
+  spi_miso);
+
+  // clock and resets
+
+  input             sys_clk;
+  input             sys_resetn;
+
+  // ddr3
+
+  output            ddr3_clk_p;
+  output            ddr3_clk_n;
+  output  [ 14:0]   ddr3_a;
+  output  [  2:0]   ddr3_ba;
+  output            ddr3_cke;
+  output            ddr3_cs_n;
+  output            ddr3_odt;
+  output            ddr3_reset_n;
+  output            ddr3_we_n;
+  output            ddr3_ras_n;
+  output            ddr3_cas_n;
+  inout   [  7:0]   ddr3_dqs_p;
+  inout   [  7:0]   ddr3_dqs_n;
+  inout   [ 63:0]   ddr3_dq;
+  output  [  7:0]   ddr3_dm;
+  input             ddr3_rzq;
+  input             ddr3_ref_clk;
+
+  // ethernet
+
+  input             eth_ref_clk;
+  input             eth_rxd;
+  output            eth_txd;
+  output            eth_mdc;
+  inout             eth_mdio;
+  output            eth_resetn;
+  input             eth_intn;
+
+  // board gpio
+
+  input   [ 10:0]   gpio_bd_i;
+  output  [ 15:0]   gpio_bd_o;
+
+  // lane interface
+
+  input             ref_clk0;
+  input             ref_clk1;
+  input   [  3:0]   rx_data;
+  output  [  3:0]   tx_data;
+  output            rx_sync;
+  output            rx_os_sync;
+  input             tx_sync;
+  input             sysref;
+
+  output            ad9528_reset_b;
+  output            ad9528_sysref_req;
+  output            ad9371_tx1_enable;
+  output            ad9371_tx2_enable;
+  output            ad9371_rx1_enable;
+  output            ad9371_rx2_enable;
+  output            ad9371_test;
+  output            ad9371_reset_b;
+  input             ad9371_gpint;
+
+  inout   [ 18:0]   ad9371_gpio;
+
+  output            spi_csn_ad9528;
+  output            spi_csn_ad9371;
+  output            spi_clk;
+  output            spi_mosi;
+  input             spi_miso;
+
+  // internal signals
+
+  wire              eth_reset;
+  wire              eth_mdio_i;
+  wire              eth_mdio_o;
+  wire              eth_mdio_t;
+  wire    [ 63:0]   gpio_i;
+  wire    [ 63:0]   gpio_o;
+  wire              spi_miso_s;
+  wire              spi_mosi_s;
+  wire    [  7:0]   spi_csn_s;
+
+  assign spi_csn_ad9528 = spi_csn_s[0];
+  assign spi_csn_ad9371 = spi_csn_s[1];
+
+  // gpio (ad9371)
+
+  assign ad9371_tx1_enable = gpio_o[55];
+  assign ad9371_tx2_enable = gpio_o[54];
+  assign ad9371_rx1_enable = gpio_o[53];
+  assign ad9371_rx2_enable = gpio_o[52];
+  assign ad9371_test = gpio_o[51];
+  assign ad9371_reset_b = gpio_o[50];
+  assign ad9528_sysref_req = gpio_o[49];
+  assign ad9528_reset_b = gpio_o[48];
+
+  assign gpio_i[63:57] = gpio_o[63:57];
+  assign gpio_i[56:56] = ad9371_gpint;
+  assign gpio_i[55:32] = gpio_o[55:32];
+
+  // board stuff
+
+  assign eth_resetn = ~eth_reset;
+  assign eth_mdio_i = eth_mdio;
+  assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
+
+  assign ddr3_a[14:12] = 3'd0;
+
+  assign gpio_i[31:27] = gpio_o[31:27];
+  assign gpio_i[26:16] = gpio_bd_i;
+  assign gpio_i[15: 0] = gpio_o[15:0];
+
+  assign gpio_bd_o = gpio_o[15:0];
+
+  system_bd i_system_bd (
+    .sys_clk_clk (sys_clk),
+    .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
+    .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
+    .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
+    .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
+    .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
+    .sys_ethernet_mdio_mdc (eth_mdc),
+    .sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .sys_ethernet_ref_clk_clk (eth_ref_clk),
+    .sys_ethernet_reset_reset (eth_reset),
+    .sys_ethernet_sgmii_rxp_0 (eth_rxd),
+    .sys_ethernet_sgmii_txp_0 (eth_txd),
+    .sys_gpio_bd_in_port (gpio_i[31:0]),
+    .sys_gpio_bd_out_port (gpio_o[31:0]),
+    .sys_gpio_in_export (gpio_i[63:32]),
+    .sys_gpio_out_export (gpio_o[63:32]),
+    .sys_rst_reset_n (sys_resetn),
+    .sys_spi_MISO (spi_miso_s),
+    .sys_spi_MOSI (spi_mosi_s),
+    .sys_spi_SCLK (spi_clk),
+    .sys_spi_SS_n (spi_csn_s),
+    .ad9371_gpio_export(ad9371_gpio),
+    .xcvr_ref_clk_clk(ref_clk1),
+    .rx_data_rx_serial_data (rx_data[1:0]),
+    .rx_os_data_rx_serial_data (rx_data[3:2]),
+    .rx_os_sync_rx_sync (rx_os_sync),
+    .rx_os_sysref_rx_ext_sysref_in (sysref),
+    .rx_sync_rx_sync (rx_sync),
+    .rx_sysref_rx_ext_sysref_in (sysref),
+    .tx_data_tx_serial_data (tx_data),
+    .tx_sync_tx_sync (tx_sync),
+    .tx_sysref_tx_ext_sysref_in (sysref)
+  );
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 6a8ca8107aac11db7db2fdbd7fa8bd11ee79ad39 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 16 Aug 2016 17:37:16 +0300
Subject: [PATCH 402/972] common: Added common ad_dcfilter stub for altera.

---
 library/altera/common/ad_dcfilter.v  | 99 ++++++++++++++++++++++++++++
 library/axi_ad9361/axi_ad9361_hw.tcl |  2 +-
 library/axi_ad9371/axi_ad9371_hw.tcl |  2 +-
 3 files changed, 101 insertions(+), 2 deletions(-)
 create mode 100755 library/altera/common/ad_dcfilter.v

diff --git a/library/altera/common/ad_dcfilter.v b/library/altera/common/ad_dcfilter.v
new file mode 100755
index 000000000..8aac6dfc4
--- /dev/null
+++ b/library/altera/common/ad_dcfilter.v
@@ -0,0 +1,99 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
+// NOT IMPLEMENTED
+
+`timescale 1ps/1ps
+
+module ad_dcfilter (
+
+  // data interface
+
+  clk,
+  valid,
+  data,
+  valid_out,
+  data_out,
+
+  // control interface
+
+  dcfilt_enb,
+  dcfilt_coeff,
+  dcfilt_offset);
+
+  // data interface
+
+  input           clk;
+  input           valid;
+  input   [15:0]  data;
+  output          valid_out;
+  output  [15:0]  data_out;
+
+  // control interface
+
+  input           dcfilt_enb;
+  input   [15:0]  dcfilt_coeff;
+  input   [15:0]  dcfilt_offset;
+
+  // internal registers
+
+  reg             valid_d = 'd0;
+  reg     [15:0]  data_d = 'd0;
+  reg             valid_2d = 'd0;
+  reg     [15:0]  data_2d = 'd0;
+  reg             valid_out = 'd0;
+  reg     [15:0]  data_out = 'd0;
+
+  // internal signals
+
+  wire    [47:0]  dc_offset_s;
+
+  always @(posedge clk) begin
+    valid_d <= valid;
+    if (valid == 1'b1) begin
+      data_d <= data + dcfilt_offset;
+    end
+    valid_2d <= valid_d;
+    data_2d  <= data_d;
+    valid_out <= valid_2d;
+    data_out  <= data_2d;
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 77b3d4cd4..6f4d84346 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -28,7 +28,7 @@ add_fileset_file ad_dds_sine.v            VERILOG PATH $ad_hdl_dir/library/commo
 add_fileset_file ad_dds_1.v               VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
 add_fileset_file ad_dds.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
 add_fileset_file ad_datafmt.v             VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
-add_fileset_file ad_dcfilter.v            VERILOG PATH $ad_hdl_dir/library/common/ad_dcfilter.v
+add_fileset_file ad_dcfilter.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
 add_fileset_file ad_iqcor.v               VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
 add_fileset_file ad_addsub.v              VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v
 add_fileset_file ad_tdd_control.v         VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v
diff --git a/library/axi_ad9371/axi_ad9371_hw.tcl b/library/axi_ad9371/axi_ad9371_hw.tcl
index 569c5ac79..a99138f28 100755
--- a/library/axi_ad9371/axi_ad9371_hw.tcl
+++ b/library/axi_ad9371/axi_ad9371_hw.tcl
@@ -20,7 +20,7 @@ add_fileset_file ad_dds_sine.v              VERILOG PATH $ad_hdl_dir/library/com
 add_fileset_file ad_dds_1.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
 add_fileset_file ad_dds.v                   VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
 add_fileset_file ad_datafmt.v               VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
-add_fileset_file ad_dcfilter.v              VERILOG PATH $ad_hdl_dir/library/common/ad_dcfilter.v
+add_fileset_file ad_dcfilter.v              VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
 add_fileset_file ad_iqcor.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
 add_fileset_file up_axi.v                   VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
 add_fileset_file up_xfer_cntrl.v            VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v

From 8464816c8283f90af23aff578d11fed610205f57 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 16 Aug 2016 12:05:56 -0400
Subject: [PATCH 403/972] dmafifo-split to adc/dac

---
 projects/common/xilinx/sys_adcfifo.tcl        | 50 +++++++++++++++++++
 .../{sys_dmafifo.tcl => sys_dacfifo.tcl}      | 47 +----------------
 2 files changed, 51 insertions(+), 46 deletions(-)
 create mode 100644 projects/common/xilinx/sys_adcfifo.tcl
 rename projects/common/xilinx/{sys_dmafifo.tcl => sys_dacfifo.tcl} (51%)

diff --git a/projects/common/xilinx/sys_adcfifo.tcl b/projects/common/xilinx/sys_adcfifo.tcl
new file mode 100644
index 000000000..2c07f900f
--- /dev/null
+++ b/projects/common/xilinx/sys_adcfifo.tcl
@@ -0,0 +1,50 @@
+
+# sys bram (use only when dma is not capable of keeping up).
+# generic fifo interface - existence is oblivious to software.
+
+proc p_sys_adcfifo {p_name m_name adc_data_width dma_addr_width} {
+
+  global ad_hdl_dir
+
+  set p_instance [get_bd_cells $p_name]
+  set c_instance [current_bd_instance .]
+
+  current_bd_instance $p_instance
+
+  set m_instance [create_bd_cell -type hier $m_name]
+  current_bd_instance $m_instance
+
+  create_bd_pin -dir I adc_rst
+  create_bd_pin -dir I -type clk adc_clk
+  create_bd_pin -dir I adc_wr
+  create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata
+  create_bd_pin -dir O adc_wovf
+
+  create_bd_pin -dir I -type clk dma_clk
+  create_bd_pin -dir O dma_wr
+  create_bd_pin -dir O -from 63 -to 0 dma_wdata
+  create_bd_pin -dir I dma_wready
+  create_bd_pin -dir I dma_xfer_req
+  create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
+
+  set util_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:util_adcfifo:1.0 util_adcfifo]
+  set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $util_adcfifo
+  set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $util_adcfifo
+  set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $util_adcfifo
+  set_property -dict [list CONFIG.DMA_ADDRESS_WIDTH $dma_addr_width] $util_adcfifo
+
+  ad_connect  adc_rst util_adcfifo/adc_rst
+  ad_connect  adc_clk util_adcfifo/adc_clk
+  ad_connect  adc_wr util_adcfifo/adc_wr
+  ad_connect  adc_wdata util_adcfifo/adc_wdata
+  ad_connect  adc_wovf util_adcfifo/adc_wovf
+  ad_connect  dma_clk util_adcfifo/dma_clk
+  ad_connect  dma_wr util_adcfifo/dma_wr
+  ad_connect  dma_wdata util_adcfifo/dma_wdata
+  ad_connect  dma_wready util_adcfifo/dma_wready
+  ad_connect  dma_xfer_req util_adcfifo/dma_xfer_req
+  ad_connect  dma_xfer_status util_adcfifo/dma_xfer_status
+
+  current_bd_instance $c_instance
+}
+
diff --git a/projects/common/xilinx/sys_dmafifo.tcl b/projects/common/xilinx/sys_dacfifo.tcl
similarity index 51%
rename from projects/common/xilinx/sys_dmafifo.tcl
rename to projects/common/xilinx/sys_dacfifo.tcl
index f6876fd9b..e4ae5132b 100644
--- a/projects/common/xilinx/sys_dmafifo.tcl
+++ b/projects/common/xilinx/sys_dacfifo.tcl
@@ -2,52 +2,6 @@
 # sys bram (use only when dma is not capable of keeping up).
 # generic fifo interface - existence is oblivious to software.
 
-proc p_sys_dmafifo {p_name m_name adc_data_width dma_addr_width} {
-
-  global ad_hdl_dir
-
-  set p_instance [get_bd_cells $p_name]
-  set c_instance [current_bd_instance .]
-
-  current_bd_instance $p_instance
-
-  set m_instance [create_bd_cell -type hier $m_name]
-  current_bd_instance $m_instance
-
-  create_bd_pin -dir I adc_rst
-  create_bd_pin -dir I -type clk adc_clk
-  create_bd_pin -dir I adc_wr
-  create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata
-  create_bd_pin -dir O adc_wovf
-
-  create_bd_pin -dir I -type clk dma_clk
-  create_bd_pin -dir O dma_wr
-  create_bd_pin -dir O -from 63 -to 0 dma_wdata
-  create_bd_pin -dir I dma_wready
-  create_bd_pin -dir I dma_xfer_req
-  create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
-
-  set util_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:util_adcfifo:1.0 util_adcfifo]
-  set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $util_adcfifo
-  set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $util_adcfifo
-  set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $util_adcfifo
-  set_property -dict [list CONFIG.DMA_ADDRESS_WIDTH $dma_addr_width] $util_adcfifo
-
-  ad_connect  adc_rst util_adcfifo/adc_rst
-  ad_connect  adc_clk util_adcfifo/adc_clk
-  ad_connect  adc_wr util_adcfifo/adc_wr
-  ad_connect  adc_wdata util_adcfifo/adc_wdata
-  ad_connect  adc_wovf util_adcfifo/adc_wovf
-  ad_connect  dma_clk util_adcfifo/dma_clk
-  ad_connect  dma_wr util_adcfifo/dma_wr
-  ad_connect  dma_wdata util_adcfifo/dma_wdata
-  ad_connect  dma_wready util_adcfifo/dma_wready
-  ad_connect  dma_xfer_req util_adcfifo/dma_xfer_req
-  ad_connect  dma_xfer_status util_adcfifo/dma_xfer_status
-
-  current_bd_instance $c_instance
-}
-
 proc p_sys_dacfifo {p_name m_name data_width addr_width} {
 
   global ad_hdl_dir
@@ -93,3 +47,4 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
 
   current_bd_instance $c_instance
 }
+

From 8311098384428e89d5f7631a8a04b78ee73d1559 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 16 Aug 2016 12:47:19 -0400
Subject: [PATCH 404/972] daq2/kc705- adxcvr changes

---
 projects/daq2/kc705/system_bd.tcl     |  5 +++--
 projects/daq2/kc705/system_constr.xdc |  5 +++--
 projects/daq2/kc705/system_top.v      | 22 ++++++++++++++++------
 3 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/projects/daq2/kc705/system_bd.tcl b/projects/daq2/kc705/system_bd.tcl
index a48f1b952..74324936a 100644
--- a/projects/daq2/kc705/system_bd.tcl
+++ b/projects/daq2/kc705/system_bd.tcl
@@ -1,8 +1,9 @@
 
 source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
-p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
+p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
 
 source ../common/daq2_bd.tcl
diff --git a/projects/daq2/kc705/system_constr.xdc b/projects/daq2/kc705/system_constr.xdc
index c64d6aff5..841eaf030 100644
--- a/projects/daq2/kc705/system_constr.xdc
+++ b/projects/daq2/kc705/system_constr.xdc
@@ -56,5 +56,6 @@ set_property  -dict {PACKAGE_PIN  D28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_po
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
diff --git a/projects/daq2/kc705/system_top.v b/projects/daq2/kc705/system_top.v
index b7595882b..66a8137a2 100644
--- a/projects/daq2/kc705/system_top.v
+++ b/projects/daq2/kc705/system_top.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -374,8 +372,14 @@ module system_top (
     .mii_tx_clk (mii_tx_clk),
     .mii_tx_en (mii_tx_en),
     .mii_txd (mii_txd),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
     .rx_ref_clk (rx_ref_clk),
     .rx_sync (rx_sync),
     .rx_sysref (rx_sysref),
@@ -389,8 +393,14 @@ module system_top (
     .sys_clk_n (sys_clk_n),
     .sys_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
     .tx_ref_clk (tx_ref_clk),
     .tx_sync (tx_sync),
     .tx_sysref (tx_sysref),

From 0694a5015d091e81feacce6a401d0ee90c35bb9d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 16 Aug 2016 12:47:51 -0400
Subject: [PATCH 405/972] kc705- 2016.2 version

---
 projects/common/kc705/kc705_system_bd.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl
index f762c2b5d..8b58d1320 100644
--- a/projects/common/kc705/kc705_system_bd.tcl
+++ b/projects/common/kc705/kc705_system_bd.tcl
@@ -53,7 +53,7 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst]
 
 # instance: microblaze - processor
 
-set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb]
+set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb]
 set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb
 set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
 
@@ -82,7 +82,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
 
 # instance: ddr (mig)
 
-set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
+set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl]
 set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
 file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/"
 set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl

From ce1fed1ce6a2053dfab12eaae2d0f3a69733e7cc Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 16 Aug 2016 12:54:29 -0400
Subject: [PATCH 406/972] dmafifo- adc/dac split

---
 projects/adrv9371x/zc706/Makefile      | 7 -------
 projects/adrv9371x/zc706/system_bd.tcl | 1 -
 projects/adv7511/kcu105/Makefile       | 1 -
 projects/daq2/kc705/Makefile           | 3 ++-
 projects/daq2/kcu105/Makefile          | 4 ++--
 projects/daq2/kcu105/system_bd.tcl     | 5 +++--
 projects/daq2/vc707/Makefile           | 3 ++-
 projects/daq2/vc707/system_bd.tcl      | 5 +++--
 projects/daq2/zc706/Makefile           | 5 +----
 projects/daq2/zc706/system_bd.tcl      | 2 +-
 projects/daq3/kcu105/Makefile          | 4 ++--
 projects/daq3/kcu105/system_bd.tcl     | 5 +++--
 projects/daq3/zc706/Makefile           | 5 +----
 projects/daq3/zc706/system_bd.tcl      | 2 +-
 projects/fmcadc2/vc707/Makefile        | 5 +----
 projects/fmcadc2/vc707/system_bd.tcl   | 4 ++--
 projects/fmcadc5/common/fmcadc5_bd.tcl | 2 +-
 projects/fmcadc5/vc707/Makefile        | 5 +----
 projects/fmcadc5/vc707/system_bd.tcl   | 2 +-
 projects/fmcomms11/zc706/Makefile      | 5 +----
 projects/fmcomms11/zc706/system_bd.tcl | 2 +-
 projects/fmcomms7/zc706/Makefile       | 5 +----
 projects/fmcomms7/zc706/system_bd.tcl  | 2 +-
 23 files changed, 31 insertions(+), 53 deletions(-)

diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
index f02d31df9..e47ee3670 100644
--- a/projects/adrv9371x/zc706/Makefile
+++ b/projects/adrv9371x/zc706/Makefile
@@ -18,7 +18,6 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
@@ -27,10 +26,8 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
 M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
@@ -68,10 +65,8 @@ clean-all:clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_adcfifo clean
 	make -C ../../../library/util_bsplit clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_upack clean
 
@@ -89,10 +84,8 @@ lib:
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_adcfifo
 	make -C ../../../library/util_bsplit
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_upack
 
diff --git a/projects/adrv9371x/zc706/system_bd.tcl b/projects/adrv9371x/zc706/system_bd.tcl
index 09f629479..92ff569bc 100644
--- a/projects/adrv9371x/zc706/system_bd.tcl
+++ b/projects/adrv9371x/zc706/system_bd.tcl
@@ -1,6 +1,5 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
 source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
 
 p_plddr3_dacfifo [current_bd_instance .] axi_ad9371_dacfifo 128 128
diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile
index 7d0d0e89f..edaf81d6a 100644
--- a/projects/adv7511/kcu105/Makefile
+++ b/projects/adv7511/kcu105/Makefile
@@ -13,7 +13,6 @@ M_DEPS += ../common/adv7511_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile
index 81a783ac9..87955d895 100644
--- a/projects/daq2/kc705/Makefile
+++ b/projects/daq2/kc705/Makefile
@@ -14,7 +14,8 @@ M_DEPS += ../common/daq2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
+M_DEPS += ../../common/xilinx/sys_adcfifo.tcl
 M_DEPS += ../../common/kc705/kc705_system_mig.prj
 M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile
index a1ec352fc..30c090bd7 100644
--- a/projects/daq2/kcu105/Makefile
+++ b/projects/daq2/kcu105/Makefile
@@ -14,8 +14,8 @@ M_DEPS += ../common/daq2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
-M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
+M_DEPS += ../../common/xilinx/sys_adcfifo.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl
index d47f2bd68..7b40605ee 100644
--- a/projects/daq2/kcu105/system_bd.tcl
+++ b/projects/daq2/kcu105/system_bd.tcl
@@ -1,8 +1,9 @@
 
 source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
-p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
+p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
 
 source ../common/daq2_bd.tcl
diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile
index 04212c867..d134fec7a 100644
--- a/projects/daq2/vc707/Makefile
+++ b/projects/daq2/vc707/Makefile
@@ -14,7 +14,8 @@ M_DEPS += ../common/daq2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
+M_DEPS += ../../common/xilinx/sys_adcfifo.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
diff --git a/projects/daq2/vc707/system_bd.tcl b/projects/daq2/vc707/system_bd.tcl
index 8c4a257c2..9863621d0 100644
--- a/projects/daq2/vc707/system_bd.tcl
+++ b/projects/daq2/vc707/system_bd.tcl
@@ -1,8 +1,9 @@
 
 source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
-p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
+p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
 
 source ../common/daq2_bd.tcl
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index 52f51a53b..b079f8b90 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
@@ -29,7 +29,6 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
 M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
@@ -70,7 +69,6 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_adcfifo clean
 	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
@@ -91,7 +89,6 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_adcfifo
 	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl
index 44e72997e..f958ed1b2 100644
--- a/projects/daq2/zc706/system_bd.tcl
+++ b/projects/daq2/zc706/system_bd.tcl
@@ -1,7 +1,7 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
 source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
 p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
index dc9fe218a..892a5ed02 100644
--- a/projects/daq3/kcu105/Makefile
+++ b/projects/daq3/kcu105/Makefile
@@ -14,8 +14,8 @@ M_DEPS += ../common/daq3_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
-M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
+M_DEPS += ../../common/xilinx/sys_adcfifo.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
diff --git a/projects/daq3/kcu105/system_bd.tcl b/projects/daq3/kcu105/system_bd.tcl
index 6852ec9ae..694fbc6f9 100644
--- a/projects/daq3/kcu105/system_bd.tcl
+++ b/projects/daq3/kcu105/system_bd.tcl
@@ -1,8 +1,9 @@
 
 source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
-p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
+p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
 p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
 
 source ../common/daq3_bd.tcl
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index 78c21f40c..0de7f04db 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
@@ -29,7 +29,6 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
@@ -71,7 +70,6 @@ clean-all:clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_adcfifo clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_jesd_gt clean
@@ -93,7 +91,6 @@ lib:
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_adcfifo
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_jesd_gt
diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl
index b64eb4a15..fb9baa0b0 100644
--- a/projects/daq3/zc706/system_bd.tcl
+++ b/projects/daq3/zc706/system_bd.tcl
@@ -1,7 +1,7 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
 source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
 p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
 p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index 14e82f504..6b8d54583 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -14,7 +14,7 @@ M_DEPS += ../common/fmcadc2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/xilinx/sys_adcfifo.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
@@ -23,7 +23,6 @@ M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
-M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -57,7 +56,6 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_adcfifo clean
-	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_jesd_gt clean
 
 
@@ -71,7 +69,6 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_adcfifo
-	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
diff --git a/projects/fmcadc2/vc707/system_bd.tcl b/projects/fmcadc2/vc707/system_bd.tcl
index 437a6f4f6..b9644f373 100644
--- a/projects/fmcadc2/vc707/system_bd.tcl
+++ b/projects/fmcadc2/vc707/system_bd.tcl
@@ -1,8 +1,8 @@
 
 source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
 
-p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 18
+p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 18
 
 source ../common/fmcadc2_bd.tcl
 
diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl
index 4b3d0c793..210a862da 100644
--- a/projects/fmcadc5/common/fmcadc5_bd.tcl
+++ b/projects/fmcadc5/common/fmcadc5_bd.tcl
@@ -39,7 +39,7 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 
-p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 512 18
+p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 512 18
 
 # adc common gt
 
diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile
index 3ab6280e9..fe14cf4c2 100644
--- a/projects/fmcadc5/vc707/Makefile
+++ b/projects/fmcadc5/vc707/Makefile
@@ -15,7 +15,7 @@ M_DEPS += ../common/fmcadc5_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/xilinx/sys_adcfifo.tcl
 M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
@@ -26,7 +26,6 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr
 
@@ -62,7 +61,6 @@ clean-all:clean
 	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_adcfifo clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_mfifo clean
 
@@ -78,7 +76,6 @@ lib:
 	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_adcfifo
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_mfifo
 
diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl
index 6ca32626b..7bc7f1a11 100644
--- a/projects/fmcadc5/vc707/system_bd.tcl
+++ b/projects/fmcadc5/vc707/system_bd.tcl
@@ -1,6 +1,6 @@
 
 source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
 source ../common/fmcadc5_bd.tcl
 
 # ila 
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index de49805e9..befa85363 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9162/axi_ad9162.xpr
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
@@ -29,7 +29,6 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
@@ -68,7 +67,6 @@ clean-all:clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_adcfifo clean
 	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_jesd_gt clean
 
@@ -87,7 +85,6 @@ lib:
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_adcfifo
 	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_jesd_gt
 
diff --git a/projects/fmcomms11/zc706/system_bd.tcl b/projects/fmcomms11/zc706/system_bd.tcl
index 619e17fcb..e85adf8c4 100644
--- a/projects/fmcomms11/zc706/system_bd.tcl
+++ b/projects/fmcomms11/zc706/system_bd.tcl
@@ -1,7 +1,7 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
 source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
 p_sys_dacfifo [current_bd_instance .] axi_ad9162_fifo 256 10
 p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index 3ddbc0915..f3fba2e0a 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -19,7 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
@@ -29,7 +29,6 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
@@ -70,7 +69,6 @@ clean-all:clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_adcfifo clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
 	make -C ../../../library/util_jesd_gt clean
@@ -91,7 +89,6 @@ lib:
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_adcfifo
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
 	make -C ../../../library/util_jesd_gt
diff --git a/projects/fmcomms7/zc706/system_bd.tcl b/projects/fmcomms7/zc706/system_bd.tcl
index 94dc97284..dc501e7f8 100644
--- a/projects/fmcomms7/zc706/system_bd.tcl
+++ b/projects/fmcomms7/zc706/system_bd.tcl
@@ -1,7 +1,7 @@
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
 source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
-source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
 p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 256 10

From 0b6fbf2208fbc5bf07fcf79bf27df72f7bc6d4bf Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 17 Aug 2016 10:34:06 -0400
Subject: [PATCH 407/972] daq2/vc707- 2016.2 updates

---
 projects/daq2/vc707/system_constr.xdc  |  4 ++--
 projects/daq2/vc707/system_project.tcl |  5 -----
 projects/daq2/vc707/system_top.v       | 20 ++++++++++++++++----
 3 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/projects/daq2/vc707/system_constr.xdc b/projects/daq2/vc707/system_constr.xdc
index 3b7af5d89..c667046e4 100644
--- a/projects/daq2/vc707/system_constr.xdc
+++ b/projects/daq2/vc707/system_constr.xdc
@@ -56,6 +56,6 @@ set_property  -dict {PACKAGE_PIN  G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
diff --git a/projects/daq2/vc707/system_project.tcl b/projects/daq2/vc707/system_project.tcl
index d37dabbd3..1009755ba 100644
--- a/projects/daq2/vc707/system_project.tcl
+++ b/projects/daq2/vc707/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
@@ -13,9 +11,6 @@ adi_project_files daq2_vc707 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
 adi_project_run daq2_vc707
 
 
diff --git a/projects/daq2/vc707/system_top.v b/projects/daq2/vc707/system_top.v
index 79de46271..1239a57e6 100644
--- a/projects/daq2/vc707/system_top.v
+++ b/projects/daq2/vc707/system_top.v
@@ -354,8 +354,14 @@ module system_top (
     .mgt_clk_clk_p (mgt_clk_p),
     .phy_rstn (phy_rstn),
     .phy_sd (1'b1),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
     .rx_ref_clk (rx_ref_clk),
     .rx_sync (rx_sync),
     .rx_sysref (rx_sysref),
@@ -373,8 +379,14 @@ module system_top (
     .sys_clk_n (sys_clk_n),
     .sys_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
     .tx_ref_clk (tx_ref_clk),
     .tx_sync (tx_sync),
     .tx_sysref (tx_sysref),

From 73413366bc11ebfd3571ac99399dd65b4e1f5e59 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 17 Aug 2016 10:36:00 -0400
Subject: [PATCH 408/972] daq2/all - warnings fix

---
 projects/common/kc705/kc705_system_bd.tcl | 4 ++++
 projects/daq2/kc705/system_project.tcl    | 5 -----
 projects/daq2/zc706/system_project.tcl    | 5 -----
 3 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl
index 8b58d1320..3067eca3a 100644
--- a/projects/common/kc705/kc705_system_bd.tcl
+++ b/projects/common/kc705/kc705_system_bd.tcl
@@ -262,3 +262,7 @@ create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruc
   [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr
 
 set_property range 0x2000000 [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_linear_flash}]
+
+ad_connect axi_ddr_cntrl/device_temp_i GND
+
+
diff --git a/projects/daq2/kc705/system_project.tcl b/projects/daq2/kc705/system_project.tcl
index 4e352bf38..607b24ec1 100644
--- a/projects/daq2/kc705/system_project.tcl
+++ b/projects/daq2/kc705/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
@@ -13,9 +11,6 @@ adi_project_files daq2_kc705 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
 adi_project_run daq2_kc705
 
 
diff --git a/projects/daq2/zc706/system_project.tcl b/projects/daq2/zc706/system_project.tcl
index ba06bf649..b9723d97e 100644
--- a/projects/daq2/zc706/system_project.tcl
+++ b/projects/daq2/zc706/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
@@ -14,9 +12,6 @@ adi_project_files daq2_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
 adi_project_run daq2_zc706
 
 

From 5d0e08d92e41eb7e2cc8062364b17513c62ce290 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 17 Aug 2016 10:36:19 -0400
Subject: [PATCH 409/972] common/vc707- 2016.2 version

---
 projects/common/vc707/vc707_system_bd.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl
index 37c94841f..113d45541 100644
--- a/projects/common/vc707/vc707_system_bd.tcl
+++ b/projects/common/vc707/vc707_system_bd.tcl
@@ -49,7 +49,7 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst]
 
 # instance: microblaze - processor
 
-set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb]
+set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb]
 set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb
 set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
 
@@ -78,7 +78,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
 
 # instance: ddr (mig)
 
-set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
+set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl]
 set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
 file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/"
 set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl

From 03c83b59bf735e54a1547e1401217698c2cace24 Mon Sep 17 00:00:00 2001
From: dbogdan <dragos.bogdan@analog.com>
Date: Wed, 17 Aug 2016 19:03:53 +0300
Subject: [PATCH 410/972] adrv9371x/a10soc: Export axi_ad9371_s and
 xcvr_reconfig_avmm

---
 projects/adrv9371x/a10soc/system_bd.qsys    | 38 +++++++++++++++++++--
 projects/adrv9371x/common/adrv9371x_bd.qsys | 25 ++++++++++++--
 2 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/projects/adrv9371x/a10soc/system_bd.qsys b/projects/adrv9371x/a10soc/system_bd.qsys
index a900e1ab1..beb1b1e66 100644
--- a/projects/adrv9371x/a10soc/system_bd.qsys
+++ b/projects/adrv9371x/a10soc/system_bd.qsys
@@ -73,6 +73,14 @@
          type = "String";
       }
    }
+   element adrv9371x.avl_rx_xcvr_reconfig_avmm
+   {
+      datum baseAddress
+      {
+         value = "229376";
+         type = "String";
+      }
+   }
    element adrv9371x.avl_spi
    {
       datum baseAddress
@@ -105,6 +113,14 @@
          type = "String";
       }
    }
+   element adrv9371x.axi_ad9371_s
+   {
+      datum baseAddress
+      {
+         value = "262144";
+         type = "String";
+      }
+   }
    element adrv9371x.axi_adc_dma_s
    {
       datum baseAddress
@@ -480,8 +496,8 @@
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /><slave name='adrv9371x_gpio_i.s1' start='0x36500' end='0x36510' /><slave name='adrv9371x_gpio_o.s1' start='0x36600' end='0x36620' /><slave name='adrv9371x_spi.spi_control_port' start='0x36700' end='0x36720' /></address-map>]]></parameter>
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /><slave name='adrv9371x_gpio_i.s1' start='0x36500' end='0x36510' /><slave name='adrv9371x_gpio_o.s1' start='0x36600' end='0x36620' /><slave name='adrv9371x_spi.spi_control_port' start='0x36700' end='0x36720' /><slave name='adrv9371x_xcvr_rx_core.reconfig_avmm' start='0x38000' end='0x3A000' /><slave name='adrv9371x_axi_ad9371.s_axi' start='0x40000' end='0x50000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 19" />
   <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
  </module>
  <module name="adrv9371x" kind="adrv9371x_bd" version="1.0" enabled="1">
@@ -581,6 +597,15 @@
   <parameter name="baseAddress" value="0x00035c00" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.avl_rx_xcvr_reconfig_avmm">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00038000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="avalon"
    version="15.1"
@@ -617,6 +642,15 @@
   <parameter name="baseAddress" value="0x00035000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="a10soc.sys_cpu_m_avl"
+   end="adrv9371x.axi_ad9371_s">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00040000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="avalon"
    version="15.1"
diff --git a/projects/adrv9371x/common/adrv9371x_bd.qsys b/projects/adrv9371x/common/adrv9371x_bd.qsys
index babd6c137..da9538a80 100755
--- a/projects/adrv9371x/common/adrv9371x_bd.qsys
+++ b/projects/adrv9371x/common/adrv9371x_bd.qsys
@@ -350,7 +350,11 @@
    type="avalon"
    dir="end" />
  <interface name="avl_rx_os_xcvr" internal="xcvr_rx_os_core.reconfig_avmm" />
- <interface name="avl_rx_xcvr" internal="xcvr_rx_core.reconfig_avmm" />
+ <interface
+   name="avl_rx_xcvr_reconfig_avmm"
+   internal="xcvr_rx_core.reconfig_avmm"
+   type="avalon"
+   dir="end" />
  <interface
    name="avl_spi"
    internal="spi.spi_control_port"
@@ -372,6 +376,11 @@
    internal="xcvr_pll_reconfig.mgmt_avalon_slave"
    type="avalon"
    dir="end" />
+ <interface
+   name="axi_ad9371_s"
+   internal="axi_ad9371.s_axi"
+   type="axi4lite"
+   dir="end" />
  <interface
    name="axi_adc_dma_intr"
    internal="axi_adc_dma.interrupt_sender"
@@ -1012,11 +1021,11 @@
   <parameter name="lane_rate" value="4915.2" />
   <parameter name="part_trait_bd" value="NIGHTFURY4" />
   <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="false" />
+  <parameter name="pll_reconfig_enable" value="true" />
   <parameter name="pll_type" value="CMU" />
   <parameter name="rcfg_jtag_enable" value="false" />
   <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="false" />
+  <parameter name="set_capability_reg_enable" value="true" />
   <parameter name="set_csr_soft_logic_enable" value="false" />
   <parameter name="set_prbs_soft_logic_enable" value="false" />
   <parameter name="set_user_identifier" value="0" />
@@ -1395,6 +1404,11 @@
    version="15.1"
    start="xcvr_ref_clk.out_clk"
    end="xcvr_tx_lane_pll.pll_refclk0" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="xcvr_rx_core.reconfig_clk" />
  <connection
    kind="clock"
    version="15.1"
@@ -2194,6 +2208,11 @@
    version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_pll_reconfig.mgmt_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="xcvr_rx_core.reconfig_reset" />
  <connection
    kind="reset"
    version="15.1"

From 10b9a0e52f53a5acf9f10656ca1b99f056b3c621 Mon Sep 17 00:00:00 2001
From: Shrutika Redkar <Shrutika.Redkar@analog.com>
Date: Wed, 17 Aug 2016 15:51:37 -0400
Subject: [PATCH 411/972] upadated xcvr ips

---
 library/xilinx/axi_adxcvr/axi_adxcvr_up.v | 61 +++++++++--------------
 library/xilinx/util_adxcvr/util_adxcvr.v  |  2 +-
 2 files changed, 24 insertions(+), 39 deletions(-)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
index afff578c5..88f050115 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
@@ -124,15 +124,13 @@ module axi_adxcvr_up (
   reg     [ 7:0]  up_icm_sel = 'd0;
   reg             up_icm_enb = 'd0;
   reg             up_icm_wr = 'd0;
-  reg     [11:0]  up_icm_addr = 'd0;
-  reg     [15:0]  up_icm_wdata = 'd0;
+  reg     [28:0]  up_icm_data = 'd0;
   reg     [15:0]  up_icm_rdata = 'd0;
   reg             up_icm_busy = 'd0;
   reg     [ 7:0]  up_ich_sel = 'd0;
   reg             up_ich_enb = 'd0;
   reg             up_ich_wr = 'd0;
-  reg     [11:0]  up_ich_addr = 'd0;
-  reg     [15:0]  up_ich_wdata = 'd0;
+  reg     [28:0]  up_ich_data = 'd0;
   reg     [15:0]  up_ich_rdata = 'd0;
   reg             up_ich_busy = 'd0;
   reg     [ 7:0]  up_ies_sel = 'd0;
@@ -242,29 +240,18 @@ module axi_adxcvr_up (
   assign up_cm_sel = up_icm_sel;
   assign up_cm_enb = up_icm_enb;
   assign up_cm_wr = up_icm_wr;
-  assign up_cm_addr = up_icm_addr;
-  assign up_cm_wdata = up_icm_wdata;
+  assign up_cm_addr = up_icm_data[27:16];
+  assign up_cm_wdata = up_icm_data[15:0];
 
   generate
   if (QPLL_ENABLE == 0) begin
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_icm_sel <= 'd0;
-      up_icm_enb <= 'd0;
-      up_icm_wr <= 'd0;
-      up_icm_addr <= 'd0;
-      up_icm_wdata <= 'd0;
-      up_icm_rdata <= 'd0;
-      up_icm_busy <= 'd0;
-    end else begin
-      up_icm_sel <= 'd0;
-      up_icm_enb <= 'd0;
-      up_icm_wr <= 'd0;
-      up_icm_addr <= 'd0;
-      up_icm_wdata <= 'd0;
-      up_icm_rdata <= 'd0;
-      up_icm_busy <= 'd0;
-    end
+  always @(posedge up_clk) begin
+    up_icm_sel <= 'd0;
+    up_icm_enb <= 'd0;
+    up_icm_wr <= 'd0;
+    up_icm_data <= 'd0;
+    up_icm_rdata <= 'd0;
+    up_icm_busy <= 'd0;
   end
   end else begin
   always @(negedge up_rstn or posedge up_clk) begin
@@ -272,8 +259,7 @@ module axi_adxcvr_up (
       up_icm_sel <= 'd0;
       up_icm_enb <= 'd0;
       up_icm_wr <= 'd0;
-      up_icm_addr <= 'd0;
-      up_icm_wdata <= 'd0;
+      up_icm_data <= 'd0;
       up_icm_rdata <= 'd0;
       up_icm_busy <= 'd0;
     end else begin
@@ -282,13 +268,13 @@ module axi_adxcvr_up (
       end
       if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
         up_icm_enb <= 1'b1;
+        up_icm_wr <= up_wdata[28];
       end else begin
         up_icm_enb <= 1'b0;
+        up_icm_wr <= 1'b0;
       end
       if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
-        up_icm_wr <= up_wdata[28];
-        up_icm_addr <= up_wdata[27:16];
-        up_icm_wdata <= up_wdata[15:0];
+        up_icm_data <= up_wdata[28:0];
       end
       if (up_cm_ready == 1'b1) begin
         up_icm_rdata <= up_cm_rdata;
@@ -307,16 +293,15 @@ module axi_adxcvr_up (
   assign up_ch_sel = up_ich_sel;
   assign up_ch_enb = up_ich_enb;
   assign up_ch_wr = up_ich_wr;
-  assign up_ch_addr = up_ich_addr;
-  assign up_ch_wdata = up_ich_wdata;
+  assign up_ch_addr = up_ich_data[27:16];
+  assign up_ch_wdata = up_ich_data[15:0];
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_ich_sel <= 'd0;
       up_ich_enb <= 'd0;
       up_ich_wr <= 'd0;
-      up_ich_addr <= 'd0;
-      up_ich_wdata <= 'd0;
+      up_ich_data <= 'd0;
       up_ich_rdata <= 'd0;
       up_ich_busy <= 'd0;
     end else begin
@@ -325,13 +310,13 @@ module axi_adxcvr_up (
       end
       if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
         up_ich_enb <= 1'b1;
+        up_ich_wr <= up_wdata[28];
       end else begin
         up_ich_enb <= 1'b0;
+        up_ich_wr <= 1'b0;
       end
       if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
-        up_ich_wr <= up_wdata[28];
-        up_ich_addr <= up_wdata[27:16];
-        up_ich_wdata <= up_wdata[15:0];
+        up_ich_data <= up_wdata[28:0];
       end
       if (up_ch_ready == 1'b1) begin
         up_ich_rdata <= up_ch_rdata;
@@ -462,10 +447,10 @@ module axi_adxcvr_up (
           10'h006: up_rdata_d <= {17'd0, up_user_ready_cnt, up_rst_cnt, up_pll_rst_cnt};
           10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel};
           10'h010: up_rdata_d <= {24'd0, up_icm_sel};
-          10'h011: up_rdata_d <= {3'd0, up_icm_wr, up_icm_addr, up_icm_wdata};
+          10'h011: up_rdata_d <= {3'd0, up_icm_data};
           10'h012: up_rdata_d <= {15'd0, up_icm_busy, up_icm_rdata};
           10'h018: up_rdata_d <= {24'd0, up_ich_sel};
-          10'h019: up_rdata_d <= {3'd0, up_ich_wr, up_ich_addr, up_ich_wdata};
+          10'h019: up_rdata_d <= {3'd0, up_ich_data};
           10'h01a: up_rdata_d <= {15'd0, up_ich_busy, up_ich_rdata};
           10'h020: up_rdata_d <= {24'd0, up_ies_sel};
           10'h028: up_rdata_d <= {31'd0, up_ies_req};
diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v
index c876c4647..03ea527f7 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr.v
@@ -1033,7 +1033,7 @@ module util_adxcvr (
   parameter   integer TX_OUT_DIV = 1;
   parameter   integer TX_CLK25_DIV = 20;
   parameter   [31:0]  PMA_RSV = 32'h001e7080;
-  parameter   [72:0]  RX_CDR_CFG = 72'h0b000023ff10400020;
+  parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff10400020;
   parameter   [26:0]  QPLL_CFG = 27'h0680181;
   parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000;
 

From 41203d07e918518b19cb08a9e8c8dc2def0c766c Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 18 Aug 2016 17:42:27 +0300
Subject: [PATCH 412/972] adrv9371x: A10GX, update SPI connection

---
 projects/adrv9371x/a10gx/system_top.v        | 10 ++++------
 projects/adrv9371x/common/adrv9371x_qsys.tcl |  8 ++++++++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/projects/adrv9371x/a10gx/system_top.v b/projects/adrv9371x/a10gx/system_top.v
index d07c82e2b..5f916cf00 100644
--- a/projects/adrv9371x/a10gx/system_top.v
+++ b/projects/adrv9371x/a10gx/system_top.v
@@ -184,12 +184,10 @@ module system_top (
   wire              eth_mdio_t;
   wire    [ 63:0]   gpio_i;
   wire    [ 63:0]   gpio_o;
-  wire              spi_miso_s;
-  wire              spi_mosi_s;
   wire    [  7:0]   spi_csn_s;
 
-  assign spi_csn_ad9528 = spi_csn_s[0];
-  assign spi_csn_ad9371 = spi_csn_s[1];
+  assign spi_csn_ad9371 = spi_csn_s[0];
+  assign spi_csn_ad9528 = spi_csn_s[1];
 
   // gpio (ad9371)
 
@@ -252,8 +250,8 @@ module system_top (
     .sys_gpio_in_export (gpio_i[63:32]),
     .sys_gpio_out_export (gpio_o[63:32]),
     .sys_rst_reset_n (sys_resetn),
-    .sys_spi_MISO (spi_miso_s),
-    .sys_spi_MOSI (spi_mosi_s),
+    .sys_spi_MISO (spi_miso),
+    .sys_spi_MOSI (spi_mosi),
     .sys_spi_SCLK (spi_clk),
     .sys_spi_SS_n (spi_csn_s),
     .ad9371_gpio_export(ad9371_gpio),
diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index ddbd00121..457b62b7a 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -1,3 +1,11 @@
+#overwrite default settings
+
+set_instance_parameter_value sys_spi {clockPhase} {1}
+set_instance_parameter_value sys_spi {clockPolarity} {1}
+set_instance_parameter_value sys_spi {targetClockRate} {5000000.0}
+
+
+# Add adrv9371x
 
 add_instance xcvr_ref_clk altera_clock_bridge 16.0
 set_instance_parameter_value xcvr_ref_clk {EXPLICIT_CLOCK_RATE} {0.0}

From 6ef9555909411acacc8e50dbcc9b2a1604494a79 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 19 Aug 2016 13:45:40 -0400
Subject: [PATCH 413/972] sdrstk- added

---
 projects/sdrstk/Makefile           |  89 ++++++++
 projects/sdrstk/system_bd.tcl      |   4 +
 projects/sdrstk/system_constr.xdc  | 258 ++++++++++++++++++++++
 projects/sdrstk/system_project.tcl |  23 ++
 projects/sdrstk/system_top.v       | 331 +++++++++++++++++++++++++++++
 5 files changed, 705 insertions(+)
 create mode 100644 projects/sdrstk/Makefile
 create mode 100644 projects/sdrstk/system_bd.tcl
 create mode 100644 projects/sdrstk/system_constr.xdc
 create mode 100644 projects/sdrstk/system_project.tcl
 create mode 100644 projects/sdrstk/system_top.v

diff --git a/projects/sdrstk/Makefile b/projects/sdrstk/Makefile
new file mode 100644
index 000000000..41615cbcf
--- /dev/null
+++ b/projects/sdrstk/Makefile
@@ -0,0 +1,89 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
+M_DEPS += ../../common/xilinx/sys_wfifo.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
+M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
+M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib ccbrk_pzsdr.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_gtlb clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_gpreg
+	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_gtlb
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/sdrstk/system_bd.tcl b/projects/sdrstk/system_bd.tcl
new file mode 100644
index 000000000..4907eef1b
--- /dev/null
+++ b/projects/sdrstk/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/ccbrk_bd.tcl
+
diff --git a/projects/sdrstk/system_constr.xdc b/projects/sdrstk/system_constr.xdc
new file mode 100644
index 000000000..05083fdc9
--- /dev/null
+++ b/projects/sdrstk/system_constr.xdc
@@ -0,0 +1,258 @@
+
+## constraints
+## loopback
+## p4
+
+set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33              
+set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33              
+set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33              
+set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33              
+set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33              
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33          
+set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33              
+set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33          
+set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33              
+set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33              
+set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33         
+set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33              
+set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33              
+set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33              
+set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33              
+set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33              
+set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33             
+set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33          
+set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33             
+set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33          
+set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33        
+set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33        
+
+## p5
+
+set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33             
+set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33             
+set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33             
+set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33             
+set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33             
+set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33             
+set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33        
+set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33             
+set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33             
+set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33         
+set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33             
+set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33         
+set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33             
+set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33             
+set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33             
+set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33             
+set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34              
+set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34             
+set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33        
+set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33             
+set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33        
+set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33             
+set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33        
+set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33         
+set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33        
+set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33         
+
+## p6
+
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34              
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34              
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34              
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34              
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34              
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34   
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34              
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34          
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34              
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34              
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34         
+set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34              
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34              
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34              
+set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34        
+set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34        
+set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34        
+set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34        
+
+## p7
+
+set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34        
+set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34        
+set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34        
+set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34        
+set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34             
+set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34         
+set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34             
+set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34         
+set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34             
+set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34             
+set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34             
+set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34        
+set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34             
+set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34             
+set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33               
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34             
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34             
+set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33              
+
+## p13
+
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12             
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12         
+set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12             
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12         
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12        
+set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12        
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12             
+set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12          
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12             
+set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12          
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12              
+set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12              
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12              
+set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12              
+set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12              
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12              
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12         
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12              
+set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12              
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12          
+set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12              
+set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12          
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12              
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12              
+set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12              
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12              
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12             
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12             
+set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12             
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12             
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12             
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12             
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12             
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12        
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12             
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12         
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12             
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12         
+
+## p2
+
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13                  
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13              
+set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13              
+set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13              
+set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13              
+set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13              
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13              
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13          
+set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13              
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13          
+set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13              
+set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13              
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13              
+set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13              
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13             
+set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13          
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13             
+set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13          
+set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13        
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13        
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13             
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13         
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13             
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13         
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13             
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13             
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13             
+set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13             
+set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13             
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13             
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13             
+set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13        
+set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13             
+set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13         
+set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13             
+set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13         
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13             
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13             
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13             
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13             
+
+## vcc
+
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13         
+
+## on board
+
+set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111           
+set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111           
+set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111              
+set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111              
+set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111              
+set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111              
+set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111              
+set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111              
+set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111              
+set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111              
+set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111              
+set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111              
+set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111              
+set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111              
+set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111              
+set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111              
+set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111              
+set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111              
+
+## clocks
+
+create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+
+## MIO loopbacks (fixed-io)
+## the following are connected to AD9361 GPIO
+
+##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
+##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
+##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
+##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
+
+## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
+
+##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
+
+## the following are mio-to-pl loopback
+
+##  JX4.97    E26   PS_MIO00_500_JX4    <==>  JX1.76    K3    IO_L11N_T1_SRCC_33        
+##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
+##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
+##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
+
+set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33        
+set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34             
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34              
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34             
+
diff --git a/projects/sdrstk/system_project.tcl b/projects/sdrstk/system_project.tcl
new file mode 100644
index 000000000..1aabab6f4
--- /dev/null
+++ b/projects/sdrstk/system_project.tcl
@@ -0,0 +1,23 @@
+
+
+
+source ../../scripts/adi_env.tcl 
+source $ad_hdl_dir/projects/scripts/adi_project.tcl 
+source $ad_hdl_dir/projects/scripts/adi_board.tcl 
+
+adi_project_create ccbrk_pzsdr
+adi_project_files ccbrk_pzsdr [list \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
+
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+
+adi_project_run ccbrk_pzsdr
+
+
diff --git a/projects/sdrstk/system_top.v b/projects/sdrstk/system_top.v
new file mode 100644
index 000000000..585b2022d
--- /dev/null
+++ b/projects/sdrstk/system_top.v
@@ -0,0 +1,331 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  iic_scl,
+  iic_sda,
+
+  gpio_bd,
+
+  rx_clk_in_p,
+  rx_clk_in_n,
+  rx_frame_in_p,
+  rx_frame_in_n,
+  rx_data_in_p,
+  rx_data_in_n,
+  tx_clk_out_p,
+  tx_clk_out_n,
+  tx_frame_out_p,
+  tx_frame_out_n,
+  tx_data_out_p,
+  tx_data_out_n,
+
+  enable,
+  txnrx,
+  clk_out,
+
+  gpio_clksel,
+  gpio_resetb,
+  gpio_sync,
+  gpio_en_agc,
+  gpio_ctl,
+  gpio_status,
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  gp_out,
+  gp_in,
+  gp_in_mio,
+  gp_in_1,
+
+  gt_ref_clk_p,
+  gt_ref_clk_n,
+  gt_tx_p,
+  gt_tx_n,
+  gt_rx_p,
+  gt_rx_n);
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  inout   [11:0]  gpio_bd;
+
+  input           rx_clk_in_p;
+  input           rx_clk_in_n;
+  input           rx_frame_in_p;
+  input           rx_frame_in_n;
+  input   [ 5:0]  rx_data_in_p;
+  input   [ 5:0]  rx_data_in_n;
+  output          tx_clk_out_p;
+  output          tx_clk_out_n;
+  output          tx_frame_out_p;
+  output          tx_frame_out_n;
+  output  [ 5:0]  tx_data_out_p;
+  output  [ 5:0]  tx_data_out_n;
+
+  output          enable;
+  output          txnrx;
+  input           clk_out;
+
+  inout           gpio_clksel;
+  inout           gpio_resetb;
+  inout           gpio_sync;
+  inout           gpio_en_agc;
+  inout   [ 3:0]  gpio_ctl;
+  inout   [ 7:0]  gpio_status;
+
+  output          spi_csn;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  output  [87:0]  gp_out;
+  input   [87:0]  gp_in;
+  input   [ 3:0]  gp_in_mio;
+  input           gp_in_1;
+
+  input           gt_ref_clk_p;
+  input           gt_ref_clk_n;
+  output  [ 3:0]  gt_tx_p;
+  output  [ 3:0]  gt_tx_n;
+  input   [ 3:0]  gt_rx_p;
+  input   [ 3:0]  gt_rx_n;
+
+  // internal signals
+
+  wire            gt_ref_clk;
+  wire    [95:0]  gp_out_s;
+  wire    [95:0]  gp_in_s;
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+
+  assign gp_out[87:43] = gp_out_s[87:43];
+  assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
+  assign gp_out[41: 0] = gp_out_s[41: 0];
+
+  assign gp_in_s[95:93] = 3'd0;
+  assign gp_in_s[92:92] = gp_in_1;
+  assign gp_in_s[91:88] = gp_in_mio;
+  assign gp_in_s[87: 0] = gp_in;
+
+  // instantiations
+
+  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
+    .CEB (1'd0),
+    .I (gt_ref_clk_p),
+    .IB (gt_ref_clk_n),
+    .O (gt_ref_clk),
+    .ODIV2 ());
+
+  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
+    .dio_t ({gpio_t[51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[51], gpio_i[46:32]}),
+    .dio_p ({ gpio_clksel,        // 51:51
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
+    .dio_t (gpio_t[11:0]),
+    .dio_i (gpio_o[11:0]),
+    .dio_o (gpio_i[11:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gp_in_0 (gp_in_s[31:0]),
+    .gp_in_1 (gp_in_s[63:32]),
+    .gp_in_2 (gp_in_s[95:64]),
+    .gp_out_0 (gp_out_s[31:0]),
+    .gp_out_1 (gp_out_s[63:32]),
+    .gp_out_2 (gp_out_s[95:64]),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .gt_ref_clk (gt_ref_clk),
+    .gt_rx_0_n (gt_rx_n[0]),
+    .gt_rx_0_p (gt_rx_p[0]),
+    .gt_rx_1_n (gt_rx_n[1]),
+    .gt_rx_1_p (gt_rx_p[1]),
+    .gt_rx_2_n (gt_rx_n[2]),
+    .gt_rx_2_p (gt_rx_p[2]),
+    .gt_rx_3_n (gt_rx_n[3]),
+    .gt_rx_3_p (gt_rx_p[3]),
+    .gt_tx_0_n (gt_tx_n[0]),
+    .gt_tx_0_p (gt_tx_p[0]),
+    .gt_tx_1_n (gt_tx_n[1]),
+    .gt_tx_1_p (gt_tx_p[1]),
+    .gt_tx_2_n (gt_tx_n[2]),
+    .gt_tx_2_p (gt_tx_p[2]),
+    .gt_tx_3_n (gt_tx_n[3]),
+    .gt_tx_3_p (gt_tx_p[3]),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .otg_vbusoc (1'b0),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 67bf8f8e78a15bff9b7b6e296bf906a1c8bdcbd9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 19 Aug 2016 15:56:07 -0400
Subject: [PATCH 414/972] scripts- fix path and device defaults and override

---
 projects/scripts/adi_env.tcl     | 5 +++--
 projects/scripts/adi_project.tcl | 8 ++++----
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/projects/scripts/adi_env.tcl b/projects/scripts/adi_env.tcl
index e5e15c4ee..1e6ef3183 100644
--- a/projects/scripts/adi_env.tcl
+++ b/projects/scripts/adi_env.tcl
@@ -1,8 +1,9 @@
 
 # environment related stuff
 
-set ad_hdl_dir  "../../.."
-set ad_phdl_dir "../../.."
+set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
+set ad_phdl_dir $ad_hdl_dir
+
 
 if [info exists ::env(ADI_HDL_DIR)] {
   set ad_hdl_dir $::env(ADI_HDL_DIR)
diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index cce18d679..4aba77ace 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -16,6 +16,10 @@ if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
   set IGNORE_VERSION_CHECK 0
 }
 
+set p_board "not-applicable"
+set p_device "none"
+set sys_zynq 1
+
 proc adi_project_create {project_name {mode 0}} {
 
   global ad_hdl_dir
@@ -26,10 +30,6 @@ proc adi_project_create {project_name {mode 0}} {
   global REQUIRED_VIVADO_VERSION
   global IGNORE_VERSION_CHECK
 
-  set p_device "none"
-  set p_board "none"
-  set sys_zynq 0
-
   if [regexp "_ac701$" $project_name] {
     set p_device "xc7a200tfbg676-2"
     set p_board "xilinx.com:ac701:part0:1.0"

From 85825177127fc0ec2ce2c6cdf74f8456901e5315 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 19 Aug 2016 15:56:48 -0400
Subject: [PATCH 415/972] sdrstk- updates

---
 projects/sdrstk/system_bd.tcl      | 269 +++++++++++++++++++++++++-
 projects/sdrstk/system_constr.xdc  | 301 ++++++-----------------------
 projects/sdrstk/system_project.tcl |  26 +--
 projects/sdrstk/system_top.v       | 283 ++++++---------------------
 4 files changed, 393 insertions(+), 486 deletions(-)

diff --git a/projects/sdrstk/system_bd.tcl b/projects/sdrstk/system_bd.tcl
index 4907eef1b..6e482a32c 100644
--- a/projects/sdrstk/system_bd.tcl
+++ b/projects/sdrstk/system_bd.tcl
@@ -1,4 +1,269 @@
+# create board design
+# default ports
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
+create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+
+create_bd_port -dir O spi0_csn_2_o
+create_bd_port -dir O spi0_csn_1_o
+create_bd_port -dir O spi0_csn_0_o
+create_bd_port -dir I spi0_csn_i
+create_bd_port -dir I spi0_clk_i
+create_bd_port -dir O spi0_clk_o
+create_bd_port -dir I spi0_sdo_i
+create_bd_port -dir O spi0_sdo_o
+create_bd_port -dir I spi0_sdi_i
+
+create_bd_port -dir I -from 16 -to 0 gpio_i
+create_bd_port -dir O -from 16 -to 0 gpio_o
+create_bd_port -dir O -from 16 -to 0 gpio_t
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_11
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+create_bd_port -dir I -type intr ps_intr_14
+create_bd_port -dir I -type intr ps_intr_15
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+
+# ps7 settings
+
+set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+
+# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
+
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.066}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.029}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.017}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.038}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.301}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.330}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.314}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.333}] $sys_ps7
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+
+# interface connections
+
+ad_connect  ddr sys_ps7/DDR
+ad_connect  gpio_i sys_ps7/GPIO_I
+ad_connect  gpio_o sys_ps7/GPIO_O
+ad_connect  gpio_t sys_ps7/GPIO_T
+ad_connect  fixed_io sys_ps7/FIXED_IO
+
+# spi connections
+
+ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
+ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
+ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
+ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
+ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
+ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
+ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
+ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
+ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+
+# interrupts
+
+ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15 ps_intr_15
+ad_connect  sys_concat_intc/In14 ps_intr_14
+ad_connect  sys_concat_intc/In13 ps_intr_13
+ad_connect  sys_concat_intc/In12 ps_intr_12
+ad_connect  sys_concat_intc/In11 ps_intr_11
+ad_connect  sys_concat_intc/In10 ps_intr_10
+ad_connect  sys_concat_intc/In9 ps_intr_09
+ad_connect  sys_concat_intc/In8 ps_intr_08
+ad_connect  sys_concat_intc/In7 ps_intr_07
+ad_connect  sys_concat_intc/In6 ps_intr_06
+ad_connect  sys_concat_intc/In5 ps_intr_05
+ad_connect  sys_concat_intc/In4 ps_intr_04
+ad_connect  sys_concat_intc/In3 ps_intr_03
+ad_connect  sys_concat_intc/In2 ps_intr_02
+ad_connect  sys_concat_intc/In1 ps_intr_01
+ad_connect  sys_concat_intc/In0 ps_intr_00
+
+# iic
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+
+ad_connect  iic_main axi_iic_main/iic
+ad_cpu_interconnect 0x41600000 axi_iic_main
+ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt
+
+# ad9361
+
+create_bd_port -dir I rx_clk_in
+create_bd_port -dir I rx_frame_in
+create_bd_port -dir I -from 11 -to 0 rx_data_in
+
+create_bd_port -dir O tx_clk_out
+create_bd_port -dir O tx_frame_out
+create_bd_port -dir O -from 11 -to 0 tx_data_out
+
+create_bd_port -dir O enable
+create_bd_port -dir O txnrx
+create_bd_port -dir I up_enable
+create_bd_port -dir I up_txnrx
+
+# ad9361 core(s)
+
+set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
+set_property -dict [list CONFIG.ID {0}] $axi_ad9361
+set_property -dict [list CONFIG.CMOS_OR_LVDS_N {1}] $axi_ad9361
+
+set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {32}] $axi_ad9361_dac_dma
+
+set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_dac_upack
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack
+
+set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}]  $axi_ad9361_adc_dma
+
+set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_adc_pack
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack
+
+# connections
+
+ad_connect  rx_clk_in axi_ad9361/rx_clk_in
+ad_connect  rx_frame_in axi_ad9361/rx_frame_in
+ad_connect  rx_data_in axi_ad9361/rx_data_in
+ad_connect  tx_clk_out axi_ad9361/tx_clk_out
+ad_connect  tx_frame_out axi_ad9361/tx_frame_out
+ad_connect  tx_data_out axi_ad9361/tx_data_out
+ad_connect  enable axi_ad9361/enable
+ad_connect  txnrx axi_ad9361/txnrx
+ad_connect  up_enable axi_ad9361/up_enable
+ad_connect  up_txnrx axi_ad9361/up_txnrx
+
+ad_connect  axi_ad9361/tdd_sync GND
+ad_connect  sys_200m_clk axi_ad9361/delay_clk
+ad_connect  axi_ad9361/l_clk axi_ad9361/clk
+
+ad_connect  axi_ad9361/l_clk util_ad9361_adc_pack/adc_clk
+ad_connect  axi_ad9361/rst util_ad9361_adc_pack/adc_rst
+ad_connect  axi_ad9361/adc_enable_i0 util_ad9361_adc_pack/adc_enable_0
+ad_connect  axi_ad9361/adc_valid_i0 util_ad9361_adc_pack/adc_valid_0
+ad_connect  axi_ad9361/adc_data_i0 util_ad9361_adc_pack/adc_data_0
+ad_connect  axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1
+ad_connect  axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1
+ad_connect  axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1
+ad_connect  axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
+ad_connect  util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
+ad_connect  util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
+ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf
+ad_connect  axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk
+ad_connect  axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0
+ad_connect  axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0
+ad_connect  util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
+ad_connect  axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1
+ad_connect  axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1
+ad_connect  util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
+ad_connect  axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk
+ad_connect  util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
+ad_connect  axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data
+ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
+ad_connect  axi_ad9361/dac_data_i1 GND
+ad_connect  axi_ad9361/dac_data_q1 GND
+
+# interconnects
+
+ad_cpu_interconnect 0x79020000 axi_ad9361
+ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
+ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
+ad_connect  sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
+ad_connect  sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
+
+# interrupts
+
+ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
+ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
 
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
-source ../common/ccbrk_bd.tcl
 
diff --git a/projects/sdrstk/system_constr.xdc b/projects/sdrstk/system_constr.xdc
index 05083fdc9..bb185337e 100644
--- a/projects/sdrstk/system_constr.xdc
+++ b/projects/sdrstk/system_constr.xdc
@@ -1,258 +1,67 @@
+# constraints
+# ad9361
 
-## constraints
-## loopback
-## p4
+set_property  -dict {PACKAGE_PIN  L12  IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
+set_property  -dict {PACKAGE_PIN  N13  IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
+set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
+set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
+set_property  -dict {PACKAGE_PIN  H11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
+set_property  -dict {PACKAGE_PIN  J11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
 
-set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33              
-set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33              
-set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33              
-set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33              
-set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33              
-set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33          
-set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33              
-set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33          
-set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33              
-set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33              
-set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33         
-set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33              
-set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33              
-set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33              
-set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33              
-set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33              
-set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33             
-set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33          
-set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33             
-set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33          
-set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33        
-set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33        
+set_property  -dict {PACKAGE_PIN  P10  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
+set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
+set_property  -dict {PACKAGE_PIN  R13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
+set_property  -dict {PACKAGE_PIN  R15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
+set_property  -dict {PACKAGE_PIN  P11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
+set_property  -dict {PACKAGE_PIN  R11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
+set_property  -dict {PACKAGE_PIN  R12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
+set_property  -dict {PACKAGE_PIN  P14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
+set_property  -dict {PACKAGE_PIN  P13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
+set_property  -dict {PACKAGE_PIN  N9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
+set_property  -dict {PACKAGE_PIN  M9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
+set_property  -dict {PACKAGE_PIN  R8   IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
+set_property  -dict {PACKAGE_PIN  R7   IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
 
-## p5
+set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
+set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
+set_property  -dict {PACKAGE_PIN  N11  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]
+set_property  -dict {PACKAGE_PIN  N12  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]
+set_property  -dict {PACKAGE_PIN  M10  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]
+set_property  -dict {PACKAGE_PIN  M11  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]
+set_property  -dict {PACKAGE_PIN  N7   IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]
+set_property  -dict {PACKAGE_PIN  N8   IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]
 
-set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33             
-set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33             
-set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33             
-set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33             
-set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33             
-set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33             
-set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33        
-set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33             
-set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33             
-set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33         
-set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33             
-set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33         
-set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33             
-set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33             
-set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33             
-set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33             
-set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34              
-set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34             
-set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33        
-set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33             
-set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33        
-set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33             
-set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33        
-set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33         
-set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33        
-set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33         
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]
+set_property  -dict {PACKAGE_PIN  F14  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]
 
-## p6
+set_property  -dict {PACKAGE_PIN  L13  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]
+set_property  -dict {PACKAGE_PIN  P9   IOSTANDARD LVCMOS18} [get_ports gpio_resetb]
 
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34              
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34              
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34              
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34              
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34              
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34   
-set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34              
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34          
-set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34              
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34              
-set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34         
-set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34              
-set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34              
-set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34              
-set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34        
-set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34        
-set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34        
-set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34        
+set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports enable]
+set_property  -dict {PACKAGE_PIN  K11  IOSTANDARD LVCMOS18} [get_ports txnrx]
 
-## p7
+set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  N14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]
 
-set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34        
-set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34        
-set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34        
-set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34        
-set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34             
-set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34         
-set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34             
-set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34         
-set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34             
-set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34             
-set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34             
-set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34        
-set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34             
-set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34             
-set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33               
-set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34             
-set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34             
-set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33              
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports spi_clk]
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports spi_mosi]
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports spi_miso]
 
-## p13
+set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports gpio_bd]
+set_property  -dict {PACKAGE_PIN  P8   IOSTANDARD LVCMOS18} [get_ports clk_out]
 
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12             
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12         
-set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12             
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12         
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12             
-set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12          
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12             
-set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12          
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12              
-set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12              
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12              
-set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12              
-set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12              
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12              
-set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12         
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12              
-set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12              
-set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12          
-set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12              
-set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12          
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12              
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12              
-set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12              
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12              
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12             
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12             
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12             
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12             
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12             
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12             
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12             
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12        
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12             
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12         
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12             
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12         
+create_clock -name rx_clk -period  16 [get_ports rx_clk_in]
 
-## p2
-
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13                  
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13              
-set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13              
-set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13              
-set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13              
-set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13              
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13              
-set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13          
-set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13              
-set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13          
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13              
-set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13              
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13              
-set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13              
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13             
-set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13          
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13             
-set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13          
-set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13             
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13         
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13             
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13         
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13             
-set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13             
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13             
-set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13             
-set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13             
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13             
-set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13             
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13        
-set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13             
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13         
-set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13             
-set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13         
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13             
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13             
-set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13             
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13             
-
-## vcc
-
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13         
-
-## on board
-
-set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111           
-set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111           
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111              
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111              
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111              
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111              
-set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111              
-set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111              
-set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111              
-set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111              
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111              
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111              
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111              
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111              
-set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111              
-set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111              
-set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111              
-set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111              
-
-## clocks
-
-create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-
-## MIO loopbacks (fixed-io)
-## the following are connected to AD9361 GPIO
-
-##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
-##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
-##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
-##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
-
-## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
-
-##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
-
-## the following are mio-to-pl loopback
-
-##  JX4.97    E26   PS_MIO00_500_JX4    <==>  JX1.76    K3    IO_L11N_T1_SRCC_33        
-##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
-##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
-##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
-
-set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33        
-set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34             
-set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34              
-set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34             
 
diff --git a/projects/sdrstk/system_project.tcl b/projects/sdrstk/system_project.tcl
index 1aabab6f4..cad77b1fe 100644
--- a/projects/sdrstk/system_project.tcl
+++ b/projects/sdrstk/system_project.tcl
@@ -1,23 +1,15 @@
 
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
+set p_device "xc7z010clg225-1"
+adi_project_create sdrstk
 
-source ../../scripts/adi_env.tcl 
-source $ad_hdl_dir/projects/scripts/adi_project.tcl 
-source $ad_hdl_dir/projects/scripts/adi_board.tcl 
-
-adi_project_create ccbrk_pzsdr
-adi_project_files ccbrk_pzsdr [list \
+adi_project_files sdrstk [list \
   "system_top.v" \
-  "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run ccbrk_pzsdr
+  "system_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
+adi_project_run sdrstk
 
diff --git a/projects/sdrstk/system_top.v b/projects/sdrstk/system_top.v
index 585b2022d..c74269645 100644
--- a/projects/sdrstk/system_top.v
+++ b/projects/sdrstk/system_top.v
@@ -39,189 +39,72 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 1:0]  ddr_dm,
+  inout   [15:0]  ddr_dq,
+  inout   [ 1:0]  ddr_dqs_n,
+  inout   [ 1:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [31:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  gpio_bd,
+  inout           gpio_bd,
 
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
+  input           rx_clk_in,
+  input           rx_frame_in,
+  input   [11:0]  rx_data_in,
+  output          tx_clk_out,
+  output          tx_frame_out,
+  output  [11:0]  tx_data_out,
 
-  enable,
-  txnrx,
-  clk_out,
+  output          enable,
+  output          txnrx,
+  input           clk_out,
 
-  gpio_clksel,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
+  inout           gpio_resetb,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
-
-  gp_out,
-  gp_in,
-  gp_in_mio,
-  gp_in_1,
-
-  gt_ref_clk_p,
-  gt_ref_clk_n,
-  gt_tx_p,
-  gt_tx_n,
-  gt_rx_p,
-  gt_rx_n);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  inout   [11:0]  gpio_bd;
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  output          enable;
-  output          txnrx;
-  input           clk_out;
-
-  inout           gpio_clksel;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
-
-  output  [87:0]  gp_out;
-  input   [87:0]  gp_in;
-  input   [ 3:0]  gp_in_mio;
-  input           gp_in_1;
-
-  input           gt_ref_clk_p;
-  input           gt_ref_clk_n;
-  output  [ 3:0]  gt_tx_p;
-  output  [ 3:0]  gt_tx_n;
-  input   [ 3:0]  gt_rx_p;
-  input   [ 3:0]  gt_rx_n;
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso);
 
   // internal signals
 
-  wire            gt_ref_clk;
-  wire    [95:0]  gp_out_s;
-  wire    [95:0]  gp_in_s;
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-
-  // assignments
-
-  assign gp_out[87:43] = gp_out_s[87:43];
-  assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
-  assign gp_out[41: 0] = gp_out_s[41: 0];
-
-  assign gp_in_s[95:93] = 3'd0;
-  assign gp_in_s[92:92] = gp_in_1;
-  assign gp_in_s[91:88] = gp_in_mio;
-  assign gp_in_s[87: 0] = gp_in;
+  wire    [16:0]  gpio_i;
+  wire    [16:0]  gpio_o;
+  wire    [16:0]  gpio_t;
 
   // instantiations
 
-  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
-    .CEB (1'd0),
-    .I (gt_ref_clk_p),
-    .IB (gt_ref_clk_n),
-    .O (gt_ref_clk),
-    .ODIV2 ());
-
-  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
-    .dio_t ({gpio_t[51], gpio_t[46:32]}),
-    .dio_i ({gpio_o[51], gpio_o[46:32]}),
-    .dio_o ({gpio_i[51], gpio_i[46:32]}),
-    .dio_p ({ gpio_clksel,        // 51:51
-              gpio_resetb,        // 46:46
-              gpio_sync,          // 45:45
-              gpio_en_agc,        // 44:44
-              gpio_ctl,           // 43:40
-              gpio_status}));     // 39:32
-
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
-    .dio_t (gpio_t[11:0]),
-    .dio_i (gpio_o[11:0]),
-    .dio_o (gpio_i[11:0]),
-    .dio_p (gpio_bd));
+  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
+    .dio_t (gpio_t[14:0]),
+    .dio_i (gpio_o[14:0]),
+    .dio_o (gpio_i[14:0]),
+    .dio_p ({ gpio_bd,            // 14:14
+              gpio_resetb,        // 13:13
+              gpio_en_agc,        // 12:12
+              gpio_ctl,           // 11: 8
+              gpio_status}));     //  7: 0
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
@@ -246,35 +129,11 @@ module system_top (
     .fixed_io_ps_clk (fixed_io_ps_clk),
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gp_in_0 (gp_in_s[31:0]),
-    .gp_in_1 (gp_in_s[63:32]),
-    .gp_in_2 (gp_in_s[95:64]),
-    .gp_out_0 (gp_out_s[31:0]),
-    .gp_out_1 (gp_out_s[63:32]),
-    .gp_out_2 (gp_out_s[95:64]),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .gt_ref_clk (gt_ref_clk),
-    .gt_rx_0_n (gt_rx_n[0]),
-    .gt_rx_0_p (gt_rx_p[0]),
-    .gt_rx_1_n (gt_rx_n[1]),
-    .gt_rx_1_p (gt_rx_p[1]),
-    .gt_rx_2_n (gt_rx_n[2]),
-    .gt_rx_2_p (gt_rx_p[2]),
-    .gt_rx_3_n (gt_rx_n[3]),
-    .gt_rx_3_p (gt_rx_p[3]),
-    .gt_tx_0_n (gt_tx_n[0]),
-    .gt_tx_0_p (gt_tx_p[0]),
-    .gt_tx_1_n (gt_tx_n[1]),
-    .gt_tx_1_p (gt_tx_p[1]),
-    .gt_tx_2_n (gt_tx_n[2]),
-    .gt_tx_2_p (gt_tx_p[2]),
-    .gt_tx_3_n (gt_tx_n[3]),
-    .gt_tx_3_p (gt_tx_p[3]),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
-    .otg_vbusoc (1'b0),
     .ps_intr_00 (1'b0),
     .ps_intr_01 (1'b0),
     .ps_intr_02 (1'b0),
@@ -287,13 +146,10 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
-    .ps_intr_15 (1'b0),
-    .rx_clk_in_n (rx_clk_in_n),
-    .rx_clk_in_p (rx_clk_in_p),
-    .rx_data_in_n (rx_data_in_n),
-    .rx_data_in_p (rx_data_in_p),
-    .rx_frame_in_n (rx_frame_in_n),
-    .rx_frame_in_p (rx_frame_in_p),
+    .ps_intr_14 (1'b0),
+    .rx_clk_in (rx_clk_in),
+    .rx_data_in (rx_data_in),
+    .rx_frame_in (rx_frame_in),
     .spi0_clk_i (1'b0),
     .spi0_clk_o (spi_clk),
     .spi0_csn_0_o (spi_csn),
@@ -303,27 +159,12 @@ module system_top (
     .spi0_sdi_i (spi_miso),
     .spi0_sdo_i (1'b0),
     .spi0_sdo_o (spi_mosi),
-    .spi1_clk_i (1'b0),
-    .spi1_clk_o (),
-    .spi1_csn_0_o (),
-    .spi1_csn_1_o (),
-    .spi1_csn_2_o (),
-    .spi1_csn_i (1'b1),
-    .spi1_sdi_i (1'b0),
-    .spi1_sdo_i (1'b0),
-    .spi1_sdo_o (),
-    .tdd_sync_i (1'b0),
-    .tdd_sync_o (),
-    .tdd_sync_t (),
-    .tx_clk_out_n (tx_clk_out_n),
-    .tx_clk_out_p (tx_clk_out_p),
-    .tx_data_out_n (tx_data_out_n),
-    .tx_data_out_p (tx_data_out_p),
-    .tx_frame_out_n (tx_frame_out_n),
-    .tx_frame_out_p (tx_frame_out_p),
+    .tx_clk_out (tx_clk_out),
+    .tx_data_out (tx_data_out),
+    .tx_frame_out (tx_frame_out),
     .txnrx (txnrx),
-    .up_enable (gpio_o[47]),
-    .up_txnrx (gpio_o[48]));
+    .up_enable (gpio_o[15]),
+    .up_txnrx (gpio_o[16]));
 
 endmodule
 

From 5c35012f54ccd575f7c6fc64afdc7e5975055ffa Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 19 Aug 2016 15:59:13 -0400
Subject: [PATCH 416/972] sdrstk- updates

---
 projects/sdrstk/system_project.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/sdrstk/system_project.tcl b/projects/sdrstk/system_project.tcl
index cad77b1fe..3e639ce8e 100644
--- a/projects/sdrstk/system_project.tcl
+++ b/projects/sdrstk/system_project.tcl
@@ -13,3 +13,4 @@ adi_project_files sdrstk [list \
 
 adi_project_run sdrstk
 
+

From f697490de6ae3ee1aa4dfed6c9005226bd192a5a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 19 Aug 2016 15:59:41 -0400
Subject: [PATCH 417/972] hdlmake- updates

---
 projects/Makefile                  |  3 ++
 projects/adrv9371x/a10gx/Makefile  |  2 +-
 projects/adrv9371x/a10soc/Makefile |  2 +-
 projects/arradio/c5soc/Makefile    |  2 +-
 projects/fmcomms2/a10gx/Makefile   |  2 +-
 projects/sdrstk/Makefile           | 61 ++++++++++--------------------
 6 files changed, 26 insertions(+), 46 deletions(-)

diff --git a/projects/Makefile b/projects/Makefile
index 5a24b647e..47e5dee81 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -38,6 +38,7 @@ all:
 	-make -C motcon2_fmc all
 	-make -C pzsdr all
 	-make -C pzsdr1 all
+	-make -C sdrstk all
 	-make -C usb_fx3 all
 	-make -C usdrx1 all
 
@@ -74,6 +75,7 @@ clean:
 	make -C motcon2_fmc clean
 	make -C pzsdr clean
 	make -C pzsdr1 clean
+	make -C sdrstk clean
 	make -C usb_fx3 clean
 	make -C usdrx1 clean
 
@@ -110,6 +112,7 @@ clean-all:
 	make -C motcon2_fmc clean-all
 	make -C pzsdr clean-all
 	make -C pzsdr1 clean-all
+	make -C sdrstk clean-all
 	make -C usb_fx3 clean-all
 	make -C usdrx1 clean-all
 
diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile
index 80479025b..d35c8155c 100644
--- a/projects/adrv9371x/a10gx/Makefile
+++ b/projects/adrv9371x/a10gx/Makefile
@@ -19,6 +19,7 @@ M_DEPS += ../common/adrv9371x_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
@@ -50,7 +51,6 @@ M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
 M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
 M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
 M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index ffb050c77..84ef2b10b 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -19,6 +19,7 @@ M_DEPS += ../common/adrv9371x_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
+M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
@@ -50,7 +51,6 @@ M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
 M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
 M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
 M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_dcfilter.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 0c42d4a71..165776141 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -22,6 +22,7 @@ M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
 M_DEPS += ../../../library/altera/common/ad_cmos_in.v
 M_DEPS += ../../../library/altera/common/ad_cmos_out.v
+M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
 M_DEPS += ../../../library/altera/common/ad_lvds_in.v
 M_DEPS += ../../../library/altera/common/ad_lvds_out.v
@@ -58,7 +59,6 @@ M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
 M_DEPS += ../../../library/common/ad_addsub.v
 M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_dcfilter.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 62b1ca6e1..9ce6cb4a7 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -22,6 +22,7 @@ M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
 M_DEPS += ../../../library/altera/common/ad_cmos_in.v
 M_DEPS += ../../../library/altera/common/ad_cmos_out.v
+M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
 M_DEPS += ../../../library/altera/common/ad_lvds_in.v
 M_DEPS += ../../../library/altera/common/ad_lvds_out.v
@@ -58,7 +59,6 @@ M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
 M_DEPS += ../../../library/common/ad_addsub.v
 M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_dcfilter.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
diff --git a/projects/sdrstk/Makefile b/projects/sdrstk/Makefile
index 41615cbcf..b554b4b1f 100644
--- a/projects/sdrstk/Makefile
+++ b/projects/sdrstk/Makefile
@@ -9,27 +9,14 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
-M_DEPS += ../common/ccbrk_bd.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
-M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
-M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
-M_DEPS += ../../../library/util_upack/util_upack.xpr
-M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+M_DEPS += ../scripts/adi_project.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_board.tcl
+M_DEPS += ../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -50,7 +37,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_pzsdr.sdk/system_top.hdf
+all: lib sdrstk.sdk/system_top.hdf
 
 
 clean: 
@@ -58,32 +45,22 @@ clean:
 
 
 clean-all:clean
-	make -C ../../../library/axi_ad9361 clean
-	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_gpreg clean
-	make -C ../../../library/axi_jesd_gt clean
-	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_gtlb clean
-	make -C ../../../library/util_tdd_sync clean
-	make -C ../../../library/util_upack clean
-	make -C ../../../library/util_wfifo clean
+	make -C ../../library/axi_ad9361 clean
+	make -C ../../library/axi_dmac clean
+	make -C ../../library/util_cpack clean
+	make -C ../../library/util_upack clean
 
 
-ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+sdrstk.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> sdrstk_vivado.log 2>&1
 
 
 lib:
-	make -C ../../../library/axi_ad9361
-	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_gpreg
-	make -C ../../../library/axi_jesd_gt
-	make -C ../../../library/util_cpack
-	make -C ../../../library/util_gtlb
-	make -C ../../../library/util_tdd_sync
-	make -C ../../../library/util_upack
-	make -C ../../../library/util_wfifo
+	make -C ../../library/axi_ad9361
+	make -C ../../library/axi_dmac
+	make -C ../../library/util_cpack
+	make -C ../../library/util_upack
 
 ####################################################################################
 ####################################################################################

From c6b065c349943b397bc1d692da98c6be367c54b4 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 22 Aug 2016 16:48:52 +0300
Subject: [PATCH 418/972] zc706: Updated DDR3 dacfifo

---
 projects/common/zc706/zc706_system_plddr3_dacfifo.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index 2c2281846..c59030039 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -35,7 +35,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
 
   create_bd_pin -dir O ddr_clk
 
-  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
+  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl]
   set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
   file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
   set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl

From f1b834ab256f5e8a09c276e767467ba551e8b41b Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 22 Aug 2016 16:56:02 +0300
Subject: [PATCH 419/972] scripts: Update script so that all interconnects are
 optimized for performance

---
 projects/scripts/adi_board.tcl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index f3a8f0cd3..225c03332 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -297,7 +297,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     assign_bd_address $m_addr_seg
   }
 
-  if {$m_interconnect_index == 3} {
+  if {$m_interconnect_index > 0} {
     set_property CONFIG.STRATEGY {2} $m_interconnect_cell
   }
 
@@ -306,6 +306,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
   if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
   if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
   if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
+
 }
 
 ###################################################################################################

From 270f8a6bbea5df61460300bc44ed4c13bf7236bc Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 22 Aug 2016 16:58:21 +0300
Subject: [PATCH 420/972] adrv9371x: Updated project common

---
 projects/adrv9371x/common/adrv9371x_bd.tcl | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index 90b36d9e6..ea73cb727 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -49,23 +49,24 @@ set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upa
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
 
-set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_tx_jesd]
+set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_tx_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9371_tx_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9371_tx_jesd
 
 # adc peripherals
 
-set axi_ad9371_rx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_rx_jesd]
+set axi_ad9371_rx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_jesd
 set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_jesd
 
-set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_rx_os_jesd]
+set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_os_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_os_jesd
 set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_os_jesd
 
 set axi_ad9371_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_dma
@@ -388,7 +389,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_ad9371_rx_dma/irq
 
 # ila
 
-set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
+set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
 set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_adc
 set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
@@ -412,7 +413,7 @@ set bsplit_os_adc_1 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_1
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $bsplit_os_adc_1
 
-set ila_os_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_os_adc]
+set ila_os_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_os_adc]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_os_adc
 set_property -dict [list CONFIG.C_NUM_OF_PROBES {6}] $ila_os_adc
 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_os_adc

From 320f87d63bb7764b8a25147a82094e13e272efb5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 22 Aug 2016 16:52:15 -0400
Subject: [PATCH 421/972] sdrstk- fix spi/port connections

---
 projects/sdrstk/system_bd.tcl     | 12 +++----
 projects/sdrstk/system_constr.xdc | 52 +++++++++++++++----------------
 2 files changed, 30 insertions(+), 34 deletions(-)

diff --git a/projects/sdrstk/system_bd.tcl b/projects/sdrstk/system_bd.tcl
index 6e482a32c..5ca44c4a5 100644
--- a/projects/sdrstk/system_bd.tcl
+++ b/projects/sdrstk/system_bd.tcl
@@ -82,14 +82,10 @@ set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.066}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.029}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.017}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.038}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.301}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.330}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.314}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.333}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7
 
 set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
 set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
diff --git a/projects/sdrstk/system_constr.xdc b/projects/sdrstk/system_constr.xdc
index bb185337e..678037305 100644
--- a/projects/sdrstk/system_constr.xdc
+++ b/projects/sdrstk/system_constr.xdc
@@ -3,33 +3,33 @@
 
 set_property  -dict {PACKAGE_PIN  L12  IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
 set_property  -dict {PACKAGE_PIN  N13  IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
-set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
-set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
-set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
-set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
-set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
-set_property  -dict {PACKAGE_PIN  H11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
-set_property  -dict {PACKAGE_PIN  J11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
+set_property  -dict {PACKAGE_PIN  R13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
+set_property  -dict {PACKAGE_PIN  R15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
+set_property  -dict {PACKAGE_PIN  P11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
+set_property  -dict {PACKAGE_PIN  R11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
+set_property  -dict {PACKAGE_PIN  R12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
+set_property  -dict {PACKAGE_PIN  P14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
+set_property  -dict {PACKAGE_PIN  P13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
+set_property  -dict {PACKAGE_PIN  N9   IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
+set_property  -dict {PACKAGE_PIN  M9   IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
+set_property  -dict {PACKAGE_PIN  R8   IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
+set_property  -dict {PACKAGE_PIN  R7   IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
 
 set_property  -dict {PACKAGE_PIN  P10  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
 set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
-set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
-set_property  -dict {PACKAGE_PIN  R13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
-set_property  -dict {PACKAGE_PIN  R15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
-set_property  -dict {PACKAGE_PIN  P11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
-set_property  -dict {PACKAGE_PIN  R11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
-set_property  -dict {PACKAGE_PIN  R12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
-set_property  -dict {PACKAGE_PIN  P14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
-set_property  -dict {PACKAGE_PIN  P13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
-set_property  -dict {PACKAGE_PIN  N9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
-set_property  -dict {PACKAGE_PIN  M9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
-set_property  -dict {PACKAGE_PIN  R8   IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
-set_property  -dict {PACKAGE_PIN  R7   IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
+set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
+set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
+set_property  -dict {PACKAGE_PIN  H11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
+set_property  -dict {PACKAGE_PIN  J11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
 
 set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
 set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
@@ -56,8 +56,8 @@ set_property  -dict {PACKAGE_PIN  N14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get
 
 set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]
 set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports spi_clk]
-set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports spi_mosi]
-set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports spi_miso]
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports spi_mosi]
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports spi_miso]
 
 set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports gpio_bd]
 set_property  -dict {PACKAGE_PIN  P8   IOSTANDARD LVCMOS18} [get_ports clk_out]

From 215edb11c6a67a17c175b4f91e088a0b44dc7907 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 23 Aug 2016 18:25:48 +0300
Subject: [PATCH 422/972] adrv9371: A10GX, updated design

- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
---
 projects/adrv9371x/common/adrv9371x_qsys.tcl | 60 +++++++++++---------
 1 file changed, 33 insertions(+), 27 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index 457b62b7a..48515bb86 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -201,11 +201,11 @@ set_instance_parameter_value xcvr_tx_core {pll_type} {CMU}
 set_instance_parameter_value xcvr_tx_core {bonded_mode} {non_bonded}
 set_instance_parameter_value xcvr_tx_core {REFCLK_FREQ} {125.0}
 set_instance_parameter_value xcvr_tx_core {bitrev_en} {0}
-set_instance_parameter_value xcvr_tx_core {pll_reconfig_enable} {0}
+set_instance_parameter_value xcvr_tx_core {pll_reconfig_enable} {1}
 set_instance_parameter_value xcvr_tx_core {rcfg_jtag_enable} {0}
-set_instance_parameter_value xcvr_tx_core {set_capability_reg_enable} {0}
+set_instance_parameter_value xcvr_tx_core {set_capability_reg_enable} {1}
 set_instance_parameter_value xcvr_tx_core {set_user_identifier} {0}
-set_instance_parameter_value xcvr_tx_core {set_csr_soft_logic_enable} {0}
+set_instance_parameter_value xcvr_tx_core {set_csr_soft_logic_enable} {1}
 set_instance_parameter_value xcvr_tx_core {set_prbs_soft_logic_enable} {0}
 set_instance_parameter_value xcvr_tx_core {L} {4}
 set_instance_parameter_value xcvr_tx_core {M} {4}
@@ -288,11 +288,11 @@ set_instance_parameter_value xcvr_rx_core {pll_type} {CMU}
 set_instance_parameter_value xcvr_rx_core {bonded_mode} {non_bonded}
 set_instance_parameter_value xcvr_rx_core {REFCLK_FREQ} {122.88}
 set_instance_parameter_value xcvr_rx_core {bitrev_en} {0}
-set_instance_parameter_value xcvr_rx_core {pll_reconfig_enable} {1}
+set_instance_parameter_value xcvr_rx_core {pll_reconfig_enable} {0}
 set_instance_parameter_value xcvr_rx_core {rcfg_jtag_enable} {0}
-set_instance_parameter_value xcvr_rx_core {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_rx_core {set_capability_reg_enable} {0}
 set_instance_parameter_value xcvr_rx_core {set_user_identifier} {0}
-set_instance_parameter_value xcvr_rx_core {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_rx_core {set_csr_soft_logic_enable} {0}
 set_instance_parameter_value xcvr_rx_core {set_prbs_soft_logic_enable} {0}
 set_instance_parameter_value xcvr_rx_core {L} {2}
 set_instance_parameter_value xcvr_rx_core {M} {4}
@@ -375,11 +375,11 @@ set_instance_parameter_value xcvr_rx_os_core {pll_type} {CMU}
 set_instance_parameter_value xcvr_rx_os_core {bonded_mode} {non_bonded}
 set_instance_parameter_value xcvr_rx_os_core {REFCLK_FREQ} {122.88}
 set_instance_parameter_value xcvr_rx_os_core {bitrev_en} {0}
-set_instance_parameter_value xcvr_rx_os_core {pll_reconfig_enable} {1}
+set_instance_parameter_value xcvr_rx_os_core {pll_reconfig_enable} {0}
 set_instance_parameter_value xcvr_rx_os_core {rcfg_jtag_enable} {0}
-set_instance_parameter_value xcvr_rx_os_core {set_capability_reg_enable} {1}
+set_instance_parameter_value xcvr_rx_os_core {set_capability_reg_enable} {0}
 set_instance_parameter_value xcvr_rx_os_core {set_user_identifier} {0}
-set_instance_parameter_value xcvr_rx_os_core {set_csr_soft_logic_enable} {1}
+set_instance_parameter_value xcvr_rx_os_core {set_csr_soft_logic_enable} {0}
 set_instance_parameter_value xcvr_rx_os_core {set_prbs_soft_logic_enable} {0}
 set_instance_parameter_value xcvr_rx_os_core {L} {2}
 set_instance_parameter_value xcvr_rx_os_core {M} {2}
@@ -442,7 +442,7 @@ set_instance_parameter_value adc_os_pack {NUM_OF_CHANNELS} {2}
 add_instance axi_adc_dma axi_dmac 1.0
 set_instance_parameter_value axi_adc_dma {ID} {0}
 set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {256}
 set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
 set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
 set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
@@ -454,12 +454,12 @@ set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
 set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
 set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
 set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
-set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
+set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {16}
 
 add_instance axi_os_adc_dma axi_dmac 1.0
 set_instance_parameter_value axi_os_adc_dma {ID} {0}
 set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {256}
 set_instance_parameter_value axi_os_adc_dma {DMA_LENGTH_WIDTH} {24}
 set_instance_parameter_value axi_os_adc_dma {DMA_2D_TRANSFER} {0}
 set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_REQ_SRC} {1}
@@ -471,11 +471,11 @@ set_instance_parameter_value axi_os_adc_dma {SYNC_TRANSFER_START} {1}
 set_instance_parameter_value axi_os_adc_dma {CYCLIC} {0}
 set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_DEST} {0}
 set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_SRC} {2}
-set_instance_parameter_value axi_os_adc_dma {FIFO_SIZE} {4}
+set_instance_parameter_value axi_os_adc_dma {FIFO_SIZE} {16}
 
 add_instance axi_dac_dma axi_dmac 1.0
 set_instance_parameter_value axi_dac_dma {ID} {0}
-set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {128}
+set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {256}
 set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {128}
 set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
 set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
@@ -488,7 +488,7 @@ set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
 set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
 set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
 set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
-set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
+set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {16}
 
 add_instance ad9371_gpio altera_avalon_pio 16.0
 set_instance_parameter_value ad9371_gpio {bitClearingEdgeCapReg} {0}
@@ -517,12 +517,13 @@ add_connection sys_clk.clk xcvr_rx_os_rst_cntrl.clock
 add_connection sys_clk.clk xcvr_rx_core.jesd204_rx_avs_clk
 add_connection sys_clk.clk xcvr_rx_os_core.jesd204_rx_avs_clk
 add_connection sys_clk.clk xcvr_tx_core.jesd204_tx_avs_clk
-add_connection sys_clk.clk axi_adc_dma.m_dest_axi_clock
-add_connection sys_clk.clk axi_os_adc_dma.m_dest_axi_clock
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_adc_dma.m_dest_axi_clock
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_os_adc_dma.m_dest_axi_clock
 add_connection sys_clk.clk axi_dac_dma.m_src_axi_clock
 add_connection sys_clk.clk xcvr_pll_reconfig.mgmt_clk
-add_connection sys_clk.clk xcvr_rx_core.reconfig_clk
-add_connection sys_clk.clk xcvr_rx_os_core.reconfig_clk
+#add_connection sys_clk.clk xcvr_rx_core.reconfig_clk
+#add_connection sys_clk.clk xcvr_rx_os_core.reconfig_clk
+add_connection sys_clk.clk xcvr_tx_core.reconfig_clk
 add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0
 add_connection sys_clk.clk axi_adc_dma.s_axi_clock
 add_connection sys_clk.clk axi_dac_dma.s_axi_clock
@@ -534,8 +535,8 @@ add_connection sys_clk.clk ad9371_gpio.clk
 
 add_connection sys_clk.clk_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n
 add_connection sys_clk.clk_reset xcvr_tx_core.jesd204_tx_avs_rst_n
-add_connection sys_clk.clk_reset axi_adc_dma.m_dest_axi_reset
-add_connection sys_clk.clk_reset axi_os_adc_dma.m_dest_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_adc_dma.m_dest_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_os_adc_dma.m_dest_axi_reset
 add_connection sys_clk.clk_reset axi_dac_dma.m_src_axi_reset
 add_connection sys_clk.clk_reset xcvr_pll_reconfig.mgmt_reset
 add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
@@ -543,8 +544,9 @@ add_connection sys_clk.clk_reset xcvr_pll.reset
 add_connection sys_clk.clk_reset xcvr_rx_rst_cntrl.reset
 add_connection sys_clk.clk_reset xcvr_tx_rst_cntrl.reset
 add_connection sys_clk.clk_reset xcvr_rx_os_rst_cntrl.reset
-add_connection sys_clk.clk_reset xcvr_rx_core.reconfig_reset
-add_connection sys_clk.clk_reset xcvr_rx_os_core.reconfig_reset
+#add_connection sys_clk.clk_reset xcvr_rx_core.reconfig_reset
+#add_connection sys_clk.clk_reset xcvr_rx_os_core.reconfig_reset
+add_connection sys_clk.clk_reset xcvr_tx_core.reconfig_reset
 add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
 add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
 add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
@@ -682,10 +684,12 @@ add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
 add_connection sys_cpu.data_master axi_os_jesd_xcvr.s_axi
 add_connection sys_cpu.data_master axi_ad9371.s_axi
 add_connection sys_cpu.data_master axi_os_adc_dma.s_axi
-add_connection sys_cpu.data_master xcvr_rx_core.reconfig_avmm
+#add_connection sys_cpu.data_master xcvr_rx_core.reconfig_avmm
 add_connection sys_cpu.data_master xcvr_rx_core.jesd204_rx_avs
-add_connection sys_cpu.data_master xcvr_rx_os_core.reconfig_avmm
+#add_connection sys_cpu.data_master xcvr_rx_os_core.reconfig_avmm
 add_connection sys_cpu.data_master xcvr_rx_os_core.jesd204_rx_avs
+add_connection sys_cpu.data_master xcvr_tx_core.reconfig_avmm
+add_connection sys_cpu.data_master xcvr_tx_core.jesd204_tx_avs
 add_connection sys_cpu.data_master ad9371_gpio.s1
 
 add_connection axi_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
@@ -700,10 +704,12 @@ set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi
 set_connection_parameter_value sys_cpu.data_master/axi_os_jesd_xcvr.s_axi               baseAddress {0x10020000}
 set_connection_parameter_value sys_cpu.data_master/axi_ad9371.s_axi                     baseAddress {0x10000000}
 set_connection_parameter_value sys_cpu.data_master/axi_os_adc_dma.s_axi                 baseAddress {0x10500000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.reconfig_avmm           baseAddress {0x10030000}
+#set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.reconfig_avmm           baseAddress {0x10030000}
 set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.jesd204_rx_avs          baseAddress {0x1003e400}
-set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.reconfig_avmm        baseAddress {0x10130000}
+#set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.reconfig_avmm        baseAddress {0x10130000}
 set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.jesd204_rx_avs       baseAddress {0x1013e400}
+set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.reconfig_avmm           baseAddress {0x10050000}
+set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.jesd204_tx_avs          baseAddress {0x1005e400}
 set_connection_parameter_value sys_cpu.data_master/ad9371_gpio.s1                       baseAddress {0x10060000}
 
 set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}

From 3c6cfdc7b56ea79fc9de956fcca81c432d31195c Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 24 Aug 2016 18:06:14 +0300
Subject: [PATCH 423/972] adrv9371x: A10GX, switched TX lanes

---
 projects/adrv9371x/a10gx/system_top.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/adrv9371x/a10gx/system_top.v b/projects/adrv9371x/a10gx/system_top.v
index 5f916cf00..abf241fc9 100644
--- a/projects/adrv9371x/a10gx/system_top.v
+++ b/projects/adrv9371x/a10gx/system_top.v
@@ -262,7 +262,7 @@ module system_top (
     .rx_os_sysref_rx_ext_sysref_in (sysref),
     .rx_sync_rx_sync (rx_sync),
     .rx_sysref_rx_ext_sysref_in (sysref),
-    .tx_data_tx_serial_data (tx_data),
+    .tx_data_tx_serial_data ({tx_data[0],tx_data[3],tx_data[2],tx_data[1]}),
     .tx_sync_tx_sync (tx_sync),
     .tx_sysref_tx_ext_sysref_in (sysref)
   );

From 264bde77adcd05bdea41d3f134102bed7b3e53bb Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 24 Aug 2016 12:06:59 -0400
Subject: [PATCH 424/972] sdrstk- SWAP==1 option

---
 projects/sdrstk/system_constr.xdc | 50 +++++++++++++++----------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/projects/sdrstk/system_constr.xdc b/projects/sdrstk/system_constr.xdc
index 678037305..c87ebe980 100644
--- a/projects/sdrstk/system_constr.xdc
+++ b/projects/sdrstk/system_constr.xdc
@@ -1,35 +1,35 @@
 # constraints
-# ad9361
+# ad9361 (SWAP == 0x1)
 
 set_property  -dict {PACKAGE_PIN  L12  IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
 set_property  -dict {PACKAGE_PIN  N13  IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
-set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
-set_property  -dict {PACKAGE_PIN  R13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
-set_property  -dict {PACKAGE_PIN  R15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
-set_property  -dict {PACKAGE_PIN  P11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
-set_property  -dict {PACKAGE_PIN  R11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
-set_property  -dict {PACKAGE_PIN  R12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
-set_property  -dict {PACKAGE_PIN  P14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
-set_property  -dict {PACKAGE_PIN  P13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
-set_property  -dict {PACKAGE_PIN  N9   IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
-set_property  -dict {PACKAGE_PIN  M9   IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
-set_property  -dict {PACKAGE_PIN  R8   IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
-set_property  -dict {PACKAGE_PIN  R7   IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
+set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
+set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
+set_property  -dict {PACKAGE_PIN  H11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
+set_property  -dict {PACKAGE_PIN  J11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
 
 set_property  -dict {PACKAGE_PIN  P10  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
 set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
-set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
-set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
-set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
-set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
-set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
-set_property  -dict {PACKAGE_PIN  H11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
-set_property  -dict {PACKAGE_PIN  J11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
+set_property  -dict {PACKAGE_PIN  R13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
+set_property  -dict {PACKAGE_PIN  R15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
+set_property  -dict {PACKAGE_PIN  P11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
+set_property  -dict {PACKAGE_PIN  R11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
+set_property  -dict {PACKAGE_PIN  R12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
+set_property  -dict {PACKAGE_PIN  P14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
+set_property  -dict {PACKAGE_PIN  P13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
+set_property  -dict {PACKAGE_PIN  N9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
+set_property  -dict {PACKAGE_PIN  M9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
+set_property  -dict {PACKAGE_PIN  R8   IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
+set_property  -dict {PACKAGE_PIN  R7   IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
 
 set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
 set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]

From 9dfcfe61469636649eb6e07300b0d01bb55ea402 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 26 Aug 2016 09:49:04 +0300
Subject: [PATCH 425/972] version_upgrade: adv7511 common script to 2016.2

Xilinx IP Clock Wizard updated to version 5.3
---
 projects/adv7511/common/adv7511_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/adv7511/common/adv7511_bd.tcl b/projects/adv7511/common/adv7511_bd.tcl
index 51b9c2ab3..d33aadccf 100755
--- a/projects/adv7511/common/adv7511_bd.tcl
+++ b/projects/adv7511/common/adv7511_bd.tcl
@@ -31,7 +31,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
 
 # audio peripherals
 
-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
 set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
 

From 6ab137a0e93fd60000b4ca4cd70624f174487c23 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 26 Aug 2016 10:07:08 +0300
Subject: [PATCH 426/972] projects/scripts: Cosmetics

---
 projects/scripts/adi_board.tcl | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 225c03332..7f83177bb 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -428,7 +428,7 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
   set m_index [expr ($p_index - 8)]
 
   if {($sys_zynq == 2) && ($p_index <= 7)} {
-    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]] 
+    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
     set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc_0/In$p_index]]
 
     puts "delete_bd_objs $p_net $p_pin"
@@ -437,7 +437,7 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
   }
 
   if {($sys_zynq == 2) && ($p_index >= 8)} {
-    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]] 
+    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]]
     set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc_1/In$m_index]]
 
     puts "delete_bd_objs $p_net $p_pin"
@@ -447,7 +447,7 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
 
   if {$sys_zynq <= 1} {
 
-    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]] 
+    set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
     set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc/In$p_index]]
 
     puts "delete_bd_objs $p_net $p_pin"

From cd0c981b505eeb590971c8f8336d2ed0fffef0dd Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 26 Aug 2016 10:08:00 +0300
Subject: [PATCH 427/972] projects/scripts: Fix to prevent a warning

In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
---
 projects/scripts/adi_board.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 7f83177bb..175db0a7b 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -297,7 +297,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     assign_bd_address $m_addr_seg
   }
 
-  if {$m_interconnect_index > 0} {
+  if {$m_interconnect_index > 1} {
     set_property CONFIG.STRATEGY {2} $m_interconnect_cell
   }
 

From 5cc2ab37a50593b040453ccc6ebaefa5a478c19d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 26 Aug 2016 10:20:04 +0300
Subject: [PATCH 428/972] version_upgrade: Common ZC702 get an upgrade to
 2016.2

Xilinx IP Clock Wizard updated to version 5.3
---
 projects/common/zc702/zc702_system_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl
index bbcf32a50..f2d2bb3f2 100644
--- a/projects/common/zc702/zc702_system_bd.tcl
+++ b/projects/common/zc702/zc702_system_bd.tcl
@@ -100,7 +100,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
 
 # audio peripherals
 
-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
 set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
 set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen

From d18f6aa81655ca20cfd9b9d61a4708ec5b9a6fdf Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 26 Aug 2016 14:46:48 +0300
Subject: [PATCH 429/972] adrv9371x: A10GX, added adcfifo

- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
---
 projects/adrv9371x/common/adrv9371x_qsys.tcl | 78 +++++++++++++-------
 1 file changed, 53 insertions(+), 25 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index 48515bb86..c13a800b2 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -1,14 +1,13 @@
-#overwrite default settings
+# overwrite default settings
 
 set_instance_parameter_value sys_spi {clockPhase} {1}
 set_instance_parameter_value sys_spi {clockPolarity} {1}
 set_instance_parameter_value sys_spi {targetClockRate} {5000000.0}
 
-
 # Add adrv9371x
 
 add_instance xcvr_ref_clk altera_clock_bridge 16.0
-set_instance_parameter_value xcvr_ref_clk {EXPLICIT_CLOCK_RATE} {0.0}
+set_instance_parameter_value xcvr_ref_clk {EXPLICIT_CLOCK_RATE} {122880000.0}
 set_instance_parameter_value xcvr_ref_clk {NUM_CLOCK_OUTPUTS} {1}
 
 add_instance xcvr_pll altera_iopll 16.0
@@ -439,6 +438,18 @@ add_instance adc_os_pack util_cpack 1.0
 set_instance_parameter_value adc_os_pack {CHANNEL_DATA_WIDTH} {32}
 set_instance_parameter_value adc_os_pack {NUM_OF_CHANNELS} {2}
 
+add_instance rx_adcfifo util_adcfifo 1.0
+set_instance_parameter_value rx_adcfifo {ADC_DATA_WIDTH} {64}
+set_instance_parameter_value rx_adcfifo {DMA_DATA_WIDTH} {64}
+set_instance_parameter_value rx_adcfifo {DMA_READY_ENABLE} {1}
+set_instance_parameter_value rx_adcfifo {DMA_ADDRESS_WIDTH} {16}
+
+add_instance rx_os_adcfifo util_adcfifo 1.0
+set_instance_parameter_value rx_os_adcfifo {ADC_DATA_WIDTH} {64}
+set_instance_parameter_value rx_os_adcfifo {DMA_DATA_WIDTH} {64}
+set_instance_parameter_value rx_os_adcfifo {DMA_READY_ENABLE} {1}
+set_instance_parameter_value rx_os_adcfifo {DMA_ADDRESS_WIDTH} {16}
+
 add_instance axi_adc_dma axi_dmac 1.0
 set_instance_parameter_value axi_adc_dma {ID} {0}
 set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
@@ -450,10 +461,10 @@ set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
 set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
 set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
 set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {0}
 set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
 set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
+set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {1}
 set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {16}
 
 add_instance axi_os_adc_dma axi_dmac 1.0
@@ -467,10 +478,10 @@ set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_SRC_DEST} {1}
 set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_DEST_REQ} {1}
 set_instance_parameter_value axi_os_adc_dma {AXI_SLICE_DEST} {0}
 set_instance_parameter_value axi_os_adc_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_os_adc_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_os_adc_dma {SYNC_TRANSFER_START} {0}
 set_instance_parameter_value axi_os_adc_dma {CYCLIC} {0}
 set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_SRC} {2}
+set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_SRC} {1}
 set_instance_parameter_value axi_os_adc_dma {FIFO_SIZE} {16}
 
 add_instance axi_dac_dma axi_dmac 1.0
@@ -519,7 +530,7 @@ add_connection sys_clk.clk xcvr_rx_os_core.jesd204_rx_avs_clk
 add_connection sys_clk.clk xcvr_tx_core.jesd204_tx_avs_clk
 add_connection sys_ddr3_cntrl.emif_usr_clk axi_adc_dma.m_dest_axi_clock
 add_connection sys_ddr3_cntrl.emif_usr_clk axi_os_adc_dma.m_dest_axi_clock
-add_connection sys_clk.clk axi_dac_dma.m_src_axi_clock
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_dac_dma.m_src_axi_clock
 add_connection sys_clk.clk xcvr_pll_reconfig.mgmt_clk
 #add_connection sys_clk.clk xcvr_rx_core.reconfig_clk
 #add_connection sys_clk.clk xcvr_rx_os_core.reconfig_clk
@@ -533,11 +544,12 @@ add_connection sys_clk.clk axi_ad9371.s_axi_clock
 add_connection sys_clk.clk axi_os_adc_dma.s_axi_clock
 add_connection sys_clk.clk ad9371_gpio.clk
 
+
 add_connection sys_clk.clk_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n
 add_connection sys_clk.clk_reset xcvr_tx_core.jesd204_tx_avs_rst_n
 add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_adc_dma.m_dest_axi_reset
 add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_os_adc_dma.m_dest_axi_reset
-add_connection sys_clk.clk_reset axi_dac_dma.m_src_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_dac_dma.m_src_axi_reset
 add_connection sys_clk.clk_reset xcvr_pll_reconfig.mgmt_reset
 add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
 add_connection sys_clk.clk_reset xcvr_pll.reset
@@ -554,6 +566,8 @@ add_connection sys_clk.clk_reset axi_os_jesd_xcvr.s_axi_reset
 add_connection sys_clk.clk_reset axi_ad9371.s_axi_reset
 add_connection sys_clk.clk_reset axi_os_adc_dma.s_axi_reset
 add_connection sys_clk.clk_reset ad9371_gpio.reset
+add_connection sys_clk.clk_reset rx_adcfifo.if_adc_rst
+add_connection sys_clk.clk_reset rx_os_adcfifo.if_adc_rst
 
 add_connection xcvr_pll.outclk0 axi_ad9371.if_dac_clk
 add_connection xcvr_pll.outclk0 dac_upack.if_dac_clk
@@ -562,46 +576,60 @@ add_connection xcvr_pll.outclk0 axi_jesd_xcvr.if_tx_clk
 add_connection xcvr_pll.outclk0 xcvr_tx_core.txlink_clk
 add_connection xcvr_pll.outclk1 adc_pack.if_adc_clk
 add_connection xcvr_pll.outclk1 axi_ad9371.if_adc_clk
-add_connection xcvr_pll.outclk1 axi_adc_dma.if_fifo_wr_clk
 add_connection xcvr_pll.outclk1 axi_jesd_xcvr.if_rx_clk
 add_connection xcvr_pll.outclk1 xcvr_rx_core.rxlink_clk
+add_connection xcvr_pll.outclk1 rx_adcfifo.if_adc_clk
+add_connection xcvr_pll.outclk1 rx_adcfifo.if_dma_clk
+add_connection xcvr_pll.outclk1 axi_adc_dma.if_s_axis_aclk
 add_connection xcvr_pll.outclk2 adc_os_pack.if_adc_clk
 add_connection xcvr_pll.outclk2 axi_ad9371.if_adc_os_clk
-add_connection xcvr_pll.outclk2 axi_os_adc_dma.if_fifo_wr_clk
 add_connection xcvr_pll.outclk2 axi_os_jesd_xcvr.if_rx_clk
 add_connection xcvr_pll.outclk2 xcvr_rx_os_core.rxlink_clk
+add_connection xcvr_pll.outclk2 rx_os_adcfifo.if_adc_clk
+add_connection xcvr_pll.outclk2 rx_os_adcfifo.if_dma_clk
+add_connection xcvr_pll.outclk2 axi_os_adc_dma.if_s_axis_aclk
 
 add_connection adc_pack.adc_ch_0 axi_ad9371.adc_ch_0
-add_connection axi_ad9371.adc_ch_1 adc_pack.adc_ch_1
+add_connection adc_pack.adc_ch_1 axi_ad9371.adc_ch_1
 add_connection adc_pack.adc_ch_2 axi_ad9371.adc_ch_2
-add_connection axi_ad9371.adc_ch_3 adc_pack.adc_ch_3
+add_connection adc_pack.adc_ch_3 axi_ad9371.adc_ch_3
+
+add_connection adc_pack.if_adc_valid rx_adcfifo.if_adc_wr
+add_connection adc_pack.if_adc_data rx_adcfifo.if_adc_wdata
+
+add_connection rx_adcfifo.if_dma_wr axi_adc_dma.if_s_axis_valid
+add_connection rx_adcfifo.if_dma_wdata axi_adc_dma.if_s_axis_data
+add_connection rx_adcfifo.if_dma_wready axi_adc_dma.if_s_axis_ready
+add_connection rx_adcfifo.if_dma_xfer_req axi_adc_dma.if_s_axis_xfer_req
+add_connection rx_adcfifo.if_adc_wovf axi_ad9371.if_adc_dovf
 
 add_connection adc_os_pack.adc_ch_0 axi_ad9371.adc_os_ch_0
-add_connection axi_ad9371.adc_os_ch_1 adc_os_pack.adc_ch_1
+add_connection adc_os_pack.adc_ch_1 axi_ad9371.adc_os_ch_1
 
-add_connection xcvr_rx_os_core.alldev_lane_aligned xcvr_rx_os_core.dev_lane_aligned
+add_connection adc_os_pack.if_adc_valid rx_os_adcfifo.if_adc_wr
+add_connection adc_os_pack.if_adc_data rx_os_adcfifo.if_adc_wdata
+
+add_connection rx_os_adcfifo.if_dma_wr axi_os_adc_dma.if_s_axis_valid
+add_connection rx_os_adcfifo.if_dma_wdata axi_os_adc_dma.if_s_axis_data
+add_connection rx_os_adcfifo.if_dma_wready axi_os_adc_dma.if_s_axis_ready
+add_connection rx_os_adcfifo.if_dma_xfer_req axi_os_adc_dma.if_s_axis_xfer_req
+add_connection rx_os_adcfifo.if_adc_wovf axi_ad9371.if_adc_dovf
 
 add_connection dac_upack.dac_ch_0 axi_ad9371.dac_ch_0
-add_connection axi_ad9371.dac_ch_1 dac_upack.dac_ch_1
+add_connection dac_upack.dac_ch_1 axi_ad9371.dac_ch_1
 add_connection dac_upack.dac_ch_2 axi_ad9371.dac_ch_2
-add_connection axi_ad9371.dac_ch_3 dac_upack.dac_ch_3
+add_connection dac_upack.dac_ch_3 axi_ad9371.dac_ch_3
 
+add_connection xcvr_rx_os_core.alldev_lane_aligned xcvr_rx_os_core.dev_lane_aligned
 add_connection xcvr_rx_core.dev_lane_aligned xcvr_rx_core.alldev_lane_aligned
 add_connection xcvr_rx_core.dev_sync_n axi_jesd_xcvr.if_rx_ip_sync
 add_connection xcvr_tx_core.dev_sync_n xcvr_tx_core.mdev_sync_n
-add_connection adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
-add_connection adc_os_pack.if_adc_data axi_os_adc_dma.if_fifo_wr_din
+
 add_connection axi_ad9371.if_adc_rx_data axi_jesd_xcvr.if_rx_data
 add_connection axi_ad9371.if_adc_rx_os_data axi_os_jesd_xcvr.if_rx_data
-add_connection adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
-add_connection adc_os_pack.if_adc_sync axi_os_adc_dma.if_fifo_wr_sync
-add_connection adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
 add_connection dac_upack.if_dac_data axi_dac_dma.if_fifo_rd_dout
 add_connection axi_dac_dma.if_fifo_rd_en dac_upack.if_dac_valid
 add_connection axi_dac_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf
-add_connection axi_os_adc_dma.if_fifo_wr_en adc_os_pack.if_adc_valid
-add_connection axi_adc_dma.if_fifo_wr_overflow axi_ad9371.if_adc_dovf
-add_connection axi_os_adc_dma.if_fifo_wr_overflow axi_ad9371.if_adc_os_dovf
 add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_rx_core.sof
 add_connection axi_os_jesd_xcvr.if_rx_ip_sync xcvr_rx_os_core.dev_sync_n
 add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_rx_core.sysref

From 271029768c243fe0216aa07859aa1ba3b9c9a3ab Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 26 Aug 2016 10:28:00 -0400
Subject: [PATCH 430/972] pzsdr/cmos - swap==1

---
 .../common/pzsdr/pzsdr_cmos_system_constr.xdc | 48 +++++++++----------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
index 05bed7714..3a1144c80 100644
--- a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
+++ b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
@@ -4,33 +4,33 @@
 
 set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports rx_clk_in]       ; ## IO_L12P_T1_MRCC_35
 set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18} [get_ports rx_frame_in]     ; ## IO_L7P_T1_AD2P_35
-set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]   ; ## IO_L13N_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]   ; ## IO_L13P_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]   ; ## IO_L14N_T2_AD4N_SRCC_35
-set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]   ; ## IO_L14P_T2_AD4P_SRCC_35
-set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]   ; ## IO_L15N_T2_DQS_AD12N_35
-set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]   ; ## IO_L15P_T2_DQS_AD12P_35
-set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]   ; ## IO_L16N_T2_35
-set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]   ; ## IO_L16P_T2_35
-set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]   ; ## IO_L17N_T2_AD5N_35
-set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]   ; ## IO_L17P_T2_AD5P_35
-set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]  ; ## IO_L18N_T2_AD13N_35
-set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]  ; ## IO_L18P_T2_AD13P_35
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]   ; ## IO_L1N_T0_AD0N_35    
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]   ; ## IO_L1P_T0_AD0P_35    
+set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]   ; ## IO_L2N_T0_AD8N_35    
+set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]   ; ## IO_L2P_T0_AD8P_35    
+set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]   ; ## IO_L3N_T0_DQS_AD1N_35
+set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]   ; ## IO_L3P_T0_DQS_AD1P_35
+set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]   ; ## IO_L4N_T0_35         
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]   ; ## IO_L4P_T0_35         
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]   ; ## IO_L5N_T0_AD9N_35    
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]   ; ## IO_L5P_T0_AD9P_35    
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]  ; ## IO_L6N_T0_VREF_35    
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]  ; ## IO_L6P_T0_35         
 
 set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]      ; ## IO_L8P_T1_AD10P_35
 set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]    ; ## IO_L9P_T1_DQS_AD3P_35
-set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]  ; ## IO_L1N_T0_AD0N_35    
-set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]  ; ## IO_L1P_T0_AD0P_35    
-set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]  ; ## IO_L2N_T0_AD8N_35    
-set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]  ; ## IO_L2P_T0_AD8P_35    
-set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]  ; ## IO_L3N_T0_DQS_AD1N_35
-set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]  ; ## IO_L3P_T0_DQS_AD1P_35
-set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]  ; ## IO_L4N_T0_35         
-set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]  ; ## IO_L4P_T0_35         
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]  ; ## IO_L5N_T0_AD9N_35    
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]  ; ## IO_L5P_T0_AD9P_35    
-set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L6N_T0_VREF_35    
-set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L6P_T0_35         
+set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]  ; ## IO_L13N_T2_MRCC_35     
+set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]  ; ## IO_L13P_T2_MRCC_35     
+set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]  ; ## IO_L14N_T2_AD4N_SRCC_35
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]  ; ## IO_L14P_T2_AD4P_SRCC_35
+set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]  ; ## IO_L15N_T2_DQS_AD12N_35
+set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]  ; ## IO_L15P_T2_DQS_AD12P_35
+set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]  ; ## IO_L16N_T2_35          
+set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]  ; ## IO_L16P_T2_35          
+set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]  ; ## IO_L17N_T2_AD5N_35     
+set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]  ; ## IO_L17P_T2_AD5P_35     
+set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L18N_T2_AD13N_35    
+set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L18P_T2_AD13P_35    
 
 set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]]       ; ## IO_L8N_T1_AD10N_35
 set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]]       ; ## IO_L9N_T1_DQS_AD3N_35

From 74bc498a6d388a2dd14576c35d91a0031582bc3a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 26 Aug 2016 10:29:08 -0400
Subject: [PATCH 431/972] library/common- added dac clock select

---
 library/common/up_dac_common.v | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index c2b144394..82e5d1f45 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -49,6 +49,7 @@ module up_dac_common (
   dac_rst,
   dac_sync,
   dac_frame,
+  dac_clksel,
   dac_par_type,
   dac_par_enb,
   dac_r1_mode,
@@ -105,6 +106,7 @@ module up_dac_common (
   output          dac_rst;
   output          dac_sync;
   output          dac_frame;
+  output          dac_clksel;
   output          dac_par_type;
   output          dac_par_enb;
   output          dac_r1_mode;
@@ -160,6 +162,7 @@ module up_dac_common (
   reg             up_dac_datafmt = 'd0;
   reg     [ 7:0]  up_dac_datarate = 'd0;
   reg             up_dac_frame = 'd0;
+  reg             up_dac_clksel = 'd0;
   reg             up_drp_sel = 'd0;
   reg             up_drp_wr = 'd0;
   reg             up_drp_status = 'd0;
@@ -215,6 +218,7 @@ module up_dac_common (
       up_dac_datafmt <= 'd0;
       up_dac_datarate <= 'd0;
       up_dac_frame <= 'd0;
+      up_dac_clksel <= 'd0;
       up_drp_sel <= 'd0;
       up_drp_wr <= 'd0;
       up_drp_status <= 'd0;
@@ -260,6 +264,9 @@ module up_dac_common (
       end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
         up_dac_frame <= up_wdata[0];
       end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
+        up_dac_clksel <= up_wdata[0];
+      end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_sel <= 1'b1;
         up_drp_wr <= ~up_wdata[28];
@@ -321,6 +328,7 @@ module up_dac_common (
           8'h15: up_rdata <= up_dac_clk_count_s;
           8'h16: up_rdata <= dac_clk_ratio;
           8'h17: up_rdata <= {31'd0, up_status_s};
+          8'h18: up_rdata <= {31'd0, up_dac_clksel};
           8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
           8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
           8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};
@@ -342,10 +350,11 @@ module up_dac_common (
 
   // dac control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(14)) i_xfer_cntrl (
+  up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_dac_sync,
+                      up_dac_clksel,
                       up_dac_frame,
                       up_dac_par_type,
                       up_dac_par_enb,
@@ -356,6 +365,7 @@ module up_dac_common (
     .d_rst (dac_rst),
     .d_clk (dac_clk),
     .d_data_cntrl ({  dac_sync_s,
+                      dac_clksel,
                       dac_frame_s,
                       dac_par_type,
                       dac_par_enb,

From 9799599eee9975766a9f1232e9f6aa70b6aa1ddd Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 26 Aug 2016 10:30:46 -0400
Subject: [PATCH 432/972] library/ad9361- add dac clk sel

---
 library/axi_ad9361/axi_ad9361.v         | 12 ++++++++----
 library/axi_ad9361/axi_ad9361_cmos_if.v | 13 +++++++++++--
 library/axi_ad9361/axi_ad9361_lvds_if.v | 13 +++++++++++--
 library/axi_ad9361/axi_ad9361_tx.v      |  3 +++
 4 files changed, 33 insertions(+), 8 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 64da73b26..957ee9598 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -312,10 +312,11 @@ module axi_ad9361 (
 
   // internal signals
 
-  wire            adc_ddr_edgesel;
+  wire            adc_ddr_edgesel_s;
   wire            adc_valid_s;
   wire    [47:0]  adc_data_s;
   wire            adc_status_s;
+  wire            dac_clksel_s;
   wire            dac_valid_s;
   wire            g_dac_valid_s;
   wire    [47:0]  dac_data_s;
@@ -413,9 +414,10 @@ module axi_ad9361 (
     .adc_data (adc_data_s),
     .adc_status (adc_status_s),
     .adc_r1_mode (adc_r1_mode),
-    .adc_ddr_edgesel (adc_ddr_edgesel),
+    .adc_ddr_edgesel (adc_ddr_edgesel_s),
     .dac_valid (g_dac_valid_s),
     .dac_data (dac_data_s),
+    .dac_clksel (dac_clksel_s),
     .dac_r1_mode (dac_r1_mode),
     .tdd_enable (tdd_enable_s),
     .tdd_txnrx (tdd_txnrx_s),
@@ -471,9 +473,10 @@ module axi_ad9361 (
     .adc_data (adc_data_s),
     .adc_status (adc_status_s),
     .adc_r1_mode (adc_r1_mode),
-    .adc_ddr_edgesel (adc_ddr_edgesel),
+    .adc_ddr_edgesel (adc_ddr_edgesel_s),
     .dac_valid (g_dac_valid_s),
     .dac_data (dac_data_s),
+    .dac_clksel (dac_clksel_s),
     .dac_r1_mode (dac_r1_mode),
     .tdd_enable (tdd_enable_s),
     .tdd_txnrx (tdd_txnrx_s),
@@ -572,7 +575,7 @@ module axi_ad9361 (
     .adc_data (adc_data_s),
     .adc_status (adc_status_s),
     .adc_r1_mode (adc_r1_mode),
-    .adc_ddr_edgesel (adc_ddr_edgesel),
+    .adc_ddr_edgesel (adc_ddr_edgesel_s),
     .dac_data (dac_data_s),
     .up_dld (up_adc_dld_s),
     .up_dwdata (up_adc_dwdata_s),
@@ -616,6 +619,7 @@ module axi_ad9361 (
     .dac_clk (clk),
     .dac_valid (dac_valid_s),
     .dac_data (dac_data_s),
+    .dac_clksel (dac_clksel_s),
     .dac_r1_mode (dac_r1_mode),
     .adc_data (adc_data_s),
     .up_dld (up_dac_dld_s),
diff --git a/library/axi_ad9361/axi_ad9361_cmos_if.v b/library/axi_ad9361/axi_ad9361_cmos_if.v
index 0e4997cba..e54935390 100644
--- a/library/axi_ad9361/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/axi_ad9361_cmos_if.v
@@ -74,6 +74,7 @@ module axi_ad9361_cmos_if (
 
   dac_valid,
   dac_data,
+  dac_clksel,
   dac_r1_mode,
 
   // tdd interface
@@ -139,6 +140,7 @@ module axi_ad9361_cmos_if (
 
   input           dac_valid;
   input   [47:0]  dac_data;
+  input           dac_clksel;
   input           dac_r1_mode;
 
   // tdd interface
@@ -211,6 +213,8 @@ module axi_ad9361_cmos_if (
   reg             txnrx_n_int = 'd0;
   reg             enable_p_int = 'd0;
   reg             txnrx_p_int = 'd0;
+  reg             dac_clkdata_p = 'd0;
+  reg             dac_clkdata_n = 'd0;
   reg             locked_m1 = 'd0;
   reg             locked = 'd0;
 
@@ -400,6 +404,11 @@ module axi_ad9361_cmos_if (
     txnrx_p_int <= txnrx_n_int;
   end
 
+  always @(posedge l_clk) begin
+    dac_clkdata_p <= dac_clksel;
+    dac_clkdata_n <= ~dac_clksel;
+  end
+
   // receive data interface, ibuf -> idelay -> iddr
 
   generate
@@ -500,8 +509,8 @@ module axi_ad9361_cmos_if (
     .IODELAY_GROUP (IO_DELAY_GROUP))
   i_tx_clk (
     .tx_clk (l_clk),
-    .tx_data_p (1'b1),
-    .tx_data_n (1'b0),
+    .tx_data_p (dac_clkdata_p),
+    .tx_data_n (dac_clkdata_n),
     .tx_data_out (tx_clk_out),
     .up_clk (up_clk),
     .up_dld (up_dac_dld[13]),
diff --git a/library/axi_ad9361/axi_ad9361_lvds_if.v b/library/axi_ad9361/axi_ad9361_lvds_if.v
index 56eb8ad6b..cd74b05f0 100644
--- a/library/axi_ad9361/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/axi_ad9361_lvds_if.v
@@ -80,6 +80,7 @@ module axi_ad9361_lvds_if (
 
   dac_valid,
   dac_data,
+  dac_clksel,
   dac_r1_mode,
 
   // tdd interface
@@ -151,6 +152,7 @@ module axi_ad9361_lvds_if (
 
   input           dac_valid;
   input   [47:0]  dac_data;
+  input           dac_clksel;
   input           dac_r1_mode;
 
   // tdd interface
@@ -227,6 +229,8 @@ module axi_ad9361_lvds_if (
   reg             txnrx_n_int = 'd0;
   reg             enable_p_int = 'd0;
   reg             txnrx_p_int = 'd0;
+  reg             dac_clkdata_p = 'd0;
+  reg             dac_clkdata_n = 'd0;
   reg             locked_m1 = 'd0;
   reg             locked = 'd0;
 
@@ -452,6 +456,11 @@ module axi_ad9361_lvds_if (
     txnrx_p_int <= txnrx_n_int;
   end
 
+  always @(posedge l_clk) begin
+    dac_clkdata_p <= dac_clksel;
+    dac_clkdata_n <= ~dac_clksel;
+  end
+
   // receive data interface, ibuf -> idelay -> iddr
 
   generate
@@ -554,8 +563,8 @@ module axi_ad9361_lvds_if (
     .IODELAY_GROUP (IO_DELAY_GROUP))
   i_tx_clk (
     .tx_clk (l_clk),
-    .tx_data_p (1'b0),
-    .tx_data_n (1'b1),
+    .tx_data_p (dac_clkdata_p),
+    .tx_data_n (dac_clkdata_n),
     .tx_data_out_p (tx_clk_out_p),
     .tx_data_out_n (tx_clk_out_n),
     .up_clk (up_clk),
diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v
index 2b788d476..c9c3d9e3a 100644
--- a/library/axi_ad9361/axi_ad9361_tx.v
+++ b/library/axi_ad9361/axi_ad9361_tx.v
@@ -44,6 +44,7 @@ module axi_ad9361_tx (
   dac_clk,
   dac_valid,
   dac_data,
+  dac_clksel,
   dac_r1_mode,
   adc_data,
   
@@ -106,6 +107,7 @@ module axi_ad9361_tx (
   input           dac_clk;
   output          dac_valid;
   output  [47:0]  dac_data;
+  output          dac_clksel;
   output          dac_r1_mode;
   input   [47:0]  adc_data;
   
@@ -354,6 +356,7 @@ module axi_ad9361_tx (
     .dac_rst (dac_rst),
     .dac_sync (dac_sync_out),
     .dac_frame (),
+    .dac_clksel (dac_clksel),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (dac_r1_mode),

From 2e59f377e1b474c11b4a07ead68d19b76732822e Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Mon, 29 Aug 2016 09:50:46 +0300
Subject: [PATCH 433/972] version_upgrade: Update ac701, mitx045 and zed common
 design to Vivado 2016.2

---
 projects/common/ac701/ac701_system_bd.tcl     | 6 +++---
 projects/common/mitx045/mitx045_system_bd.tcl | 2 +-
 projects/common/zed/zed_system_bd.tcl         | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl
index 2ee349106..b35bdcdbd 100644
--- a/projects/common/ac701/ac701_system_bd.tcl
+++ b/projects/common/ac701/ac701_system_bd.tcl
@@ -47,7 +47,7 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst]
 
 # instance: microblaze - processor
 
-set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb]
+set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb]
 set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb
 set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
 
@@ -76,14 +76,14 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
 
 # instance: ddr (mig)
 
-set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
+set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl]
 set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
 file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/"
 set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl
 
 # instance: default peripherals
 
-set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_ethernet_clkgen]
+set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_ethernet_clkgen]
 set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen
 
diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl
index c114e8302..63c19e1fd 100644
--- a/projects/common/mitx045/mitx045_system_bd.tcl
+++ b/projects/common/mitx045/mitx045_system_bd.tcl
@@ -111,7 +111,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
 
 # audio peripherals
 
-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
 set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
 set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl
index 57e47c751..25c512ff2 100644
--- a/projects/common/zed/zed_system_bd.tcl
+++ b/projects/common/zed/zed_system_bd.tcl
@@ -125,7 +125,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
 
 # audio peripherals
 
-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
 set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
 set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen

From a6e6b3f96e4fed4f55dcc559ea76d41ada0d789e Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Mon, 29 Aug 2016 15:59:15 +0300
Subject: [PATCH 434/972] version_upgrade: Update fmcomms1 common design to
 Vivado 2016.2

---
 projects/fmcomms1/common/fmcomms1_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl
index 826ecaaf8..2e3eef67a 100644
--- a/projects/fmcomms1/common/fmcomms1_bd.tcl
+++ b/projects/fmcomms1/common/fmcomms1_bd.tcl
@@ -68,7 +68,7 @@
 
   # reference clock
 
-  set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 refclk_clkgen]
+  set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 refclk_clkgen]
   set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen
   set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen
   set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen

From b7ea2efa877be20cf2bf7329aa9918f9896cb864 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 29 Aug 2016 15:18:48 -0400
Subject: [PATCH 435/972] altera- xcvr cores

---
 library/altera/avl_adxcfg/avl_adxcfg.v      | 643 ++++++++++++++++++++
 library/altera/avl_adxcfg/avl_adxcfg_hw.tcl |  77 +++
 library/altera/avl_adxcvr/avl_adxcvr_hw.tcl | 299 +++++++++
 library/altera/axi_adxcvr/axi_adxcvr.v      | 148 +++++
 library/altera/axi_adxcvr/axi_adxcvr_hw.tcl |  77 +++
 library/altera/axi_adxcvr/axi_adxcvr_up.v   | 158 +++++
 6 files changed, 1402 insertions(+)
 create mode 100644 library/altera/avl_adxcfg/avl_adxcfg.v
 create mode 100644 library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
 create mode 100755 library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
 create mode 100644 library/altera/axi_adxcvr/axi_adxcvr.v
 create mode 100644 library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
 create mode 100644 library/altera/axi_adxcvr/axi_adxcvr_up.v

diff --git a/library/altera/avl_adxcfg/avl_adxcfg.v b/library/altera/avl_adxcfg/avl_adxcfg.v
new file mode 100644
index 000000000..3f7c9dfce
--- /dev/null
+++ b/library/altera/avl_adxcfg/avl_adxcfg.v
@@ -0,0 +1,643 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module avl_adxcfg (
+
+  // reconfig sharing
+
+  input           rcfg_clk,
+  input           rcfg_reset_n,
+
+  input           rcfg_in_read_0,
+  input           rcfg_in_write_0,
+  input   [11:0]  rcfg_in_address_0,
+  input   [31:0]  rcfg_in_writedata_0,
+  output  [31:0]  rcfg_in_readata_0,
+  output          rcfg_in_waitrequest_0,
+
+  output          rcfg_out_read_0,
+  output          rcfg_out_write_0,
+  output  [11:0]  rcfg_out_address_0,
+  output  [31:0]  rcfg_out_writedata_0,
+  input   [31:0]  rcfg_out_readata_0,
+  input           rcfg_out_waitrequest_0,
+
+  input           rcfg_in_read_1,
+  input           rcfg_in_write_1,
+  input   [11:0]  rcfg_in_address_1,
+  input   [31:0]  rcfg_in_writedata_1,
+  output  [31:0]  rcfg_in_readata_1,
+  output          rcfg_in_waitrequest_1,
+
+  output          rcfg_out_read_1,
+  output          rcfg_out_write_1,
+  output  [11:0]  rcfg_out_address_1,
+  output  [31:0]  rcfg_out_writedata_1,
+  input   [31:0]  rcfg_out_readata_1,
+  input           rcfg_out_waitrequest_1,
+
+  input           rcfg_in_read_2,
+  input           rcfg_in_write_2,
+  input   [11:0]  rcfg_in_address_2,
+  input   [31:0]  rcfg_in_writedata_2,
+  output  [31:0]  rcfg_in_readata_2,
+  output          rcfg_in_waitrequest_2,
+
+  output          rcfg_out_read_2,
+  output          rcfg_out_write_2,
+  output  [11:0]  rcfg_out_address_2,
+  output  [31:0]  rcfg_out_writedata_2,
+  input   [31:0]  rcfg_out_readata_2,
+  input           rcfg_out_waitrequest_2,
+
+  input           rcfg_in_read_3,
+  input           rcfg_in_write_3,
+  input   [11:0]  rcfg_in_address_3,
+  input   [31:0]  rcfg_in_writedata_3,
+  output  [31:0]  rcfg_in_readata_3,
+  output          rcfg_in_waitrequest_3,
+
+  output          rcfg_out_read_3,
+  output          rcfg_out_write_3,
+  output  [11:0]  rcfg_out_address_3,
+  output  [31:0]  rcfg_out_writedata_3,
+  input   [31:0]  rcfg_out_readata_3,
+  input           rcfg_out_waitrequest_3,
+
+  input           rcfg_in_read_4,
+  input           rcfg_in_write_4,
+  input   [11:0]  rcfg_in_address_4,
+  input   [31:0]  rcfg_in_writedata_4,
+  output  [31:0]  rcfg_in_readata_4,
+  output          rcfg_in_waitrequest_4,
+
+  output          rcfg_out_read_4,
+  output          rcfg_out_write_4,
+  output  [11:0]  rcfg_out_address_4,
+  output  [31:0]  rcfg_out_writedata_4,
+  input   [31:0]  rcfg_out_readata_4,
+  input           rcfg_out_waitrequest_4,
+
+  input           rcfg_in_read_5,
+  input           rcfg_in_write_5,
+  input   [11:0]  rcfg_in_address_5,
+  input   [31:0]  rcfg_in_writedata_5,
+  output  [31:0]  rcfg_in_readata_5,
+  output          rcfg_in_waitrequest_5,
+
+  output          rcfg_out_read_5,
+  output          rcfg_out_write_5,
+  output  [11:0]  rcfg_out_address_5,
+  output  [31:0]  rcfg_out_writedata_5,
+  input   [31:0]  rcfg_out_readata_5,
+  input           rcfg_out_waitrequest_5,
+
+  input           rcfg_in_read_6,
+  input           rcfg_in_write_6,
+  input   [11:0]  rcfg_in_address_6,
+  input   [31:0]  rcfg_in_writedata_6,
+  output  [31:0]  rcfg_in_readata_6,
+  output          rcfg_in_waitrequest_6,
+
+  output          rcfg_out_read_6,
+  output          rcfg_out_write_6,
+  output  [11:0]  rcfg_out_address_6,
+  output  [31:0]  rcfg_out_writedata_6,
+  input   [31:0]  rcfg_out_readata_6,
+  input           rcfg_out_waitrequest_6,
+
+  input           rcfg_in_read_7,
+  input           rcfg_in_write_7,
+  input   [11:0]  rcfg_in_address_7,
+  input   [31:0]  rcfg_in_writedata_7,
+  output  [31:0]  rcfg_in_readata_7,
+  output          rcfg_in_waitrequest_7,
+
+  output          rcfg_out_read_7,
+  output          rcfg_out_write_7,
+  output  [11:0]  rcfg_out_address_7,
+  output  [31:0]  rcfg_out_writedata_7,
+  input   [31:0]  rcfg_out_readata_7,
+  input           rcfg_out_waitrequest_7);
+
+  // internal registers
+
+  reg     [11:0]  rcfg_out_address = 'd0;
+  reg     [31:0]  rcfg_out_writedata = 'd0;
+  reg             rcfg_out_iread_0 = 'd0;
+  reg             rcfg_out_iwrite_0 = 'd0;
+  reg     [31:0]  rcfg_in_ireadata_0 = 'd0;
+  reg             rcfg_in_iwaitrequest_0 = 'd0;
+  reg             rcfg_out_iread_1 = 'd0;
+  reg             rcfg_out_iwrite_1 = 'd0;
+  reg     [31:0]  rcfg_in_ireadata_1 = 'd0;
+  reg             rcfg_in_iwaitrequest_1 = 'd0;
+  reg             rcfg_out_iread_2 = 'd0;
+  reg             rcfg_out_iwrite_2 = 'd0;
+  reg     [31:0]  rcfg_in_ireadata_2 = 'd0;
+  reg             rcfg_in_iwaitrequest_2 = 'd0;
+  reg             rcfg_out_iread_3 = 'd0;
+  reg             rcfg_out_iwrite_3 = 'd0;
+  reg     [31:0]  rcfg_in_ireadata_3 = 'd0;
+  reg             rcfg_in_iwaitrequest_3 = 'd0;
+  reg             rcfg_out_iread_4 = 'd0;
+  reg             rcfg_out_iwrite_4 = 'd0;
+  reg     [31:0]  rcfg_in_ireadata_4 = 'd0;
+  reg             rcfg_in_iwaitrequest_4 = 'd0;
+  reg             rcfg_out_iread_5 = 'd0;
+  reg             rcfg_out_iwrite_5 = 'd0;
+  reg     [31:0]  rcfg_in_ireadata_5 = 'd0;
+  reg             rcfg_in_iwaitrequest_5 = 'd0;
+  reg             rcfg_out_iread_6 = 'd0;
+  reg             rcfg_out_iwrite_6 = 'd0;
+  reg     [31:0]  rcfg_in_ireadata_6 = 'd0;
+  reg             rcfg_in_iwaitrequest_6 = 'd0;
+  reg             rcfg_out_iread_7 = 'd0;
+  reg             rcfg_out_iwrite_7 = 'd0;
+  reg     [31:0]  rcfg_in_ireadata_7 = 'd0;
+  reg             rcfg_in_iwaitrequest_7 = 'd0;
+  reg     [ 3:0]  rcfg_select = 'd0;
+
+  // internal signals
+
+  wire            recfg_in_req_0_s;
+  wire            recfg_in_req_1_s;
+  wire            recfg_in_req_2_s;
+  wire            recfg_in_req_3_s;
+  wire            recfg_in_req_4_s;
+  wire            recfg_in_req_5_s;
+  wire            recfg_in_req_6_s;
+  wire            recfg_in_req_7_s;
+
+  // xcvr sharing requires same bus with ONLY different write/read signals
+
+  assign rcfg_out_address_0 <= rcfg_out_address;
+  assign rcfg_out_writedata_0 <= rcfg_out_writedata;
+  assign rcfg_out_address_1 <= rcfg_out_address;
+  assign rcfg_out_writedata_1 <= rcfg_out_writedata;
+  assign rcfg_out_address_2 <= rcfg_out_address;
+  assign rcfg_out_writedata_2 <= rcfg_out_writedata;
+  assign rcfg_out_address_3 <= rcfg_out_address;
+  assign rcfg_out_writedata_3 <= rcfg_out_writedata;
+  assign rcfg_out_address_4 <= rcfg_out_address;
+  assign rcfg_out_writedata_4 <= rcfg_out_writedata;
+  assign rcfg_out_address_5 <= rcfg_out_address;
+  assign rcfg_out_writedata_5 <= rcfg_out_writedata;
+  assign rcfg_out_address_6 <= rcfg_out_address;
+  assign rcfg_out_writedata_6 <= rcfg_out_writedata;
+  assign rcfg_out_address_7 <= rcfg_out_address;
+  assign rcfg_out_writedata_7 <= rcfg_out_writedata;
+
+  always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
+    if (rcfg_reset_n == 0) begin
+      rcfg_out_address <= 12'd0;
+      rcfg_out_writedata <= 32'd0;
+    end else begin
+      case (rcfg_select)
+        4'h8: begin
+          rcfg_out_address <= rcfg_in_address_0;
+          rcfg_out_writedata <= rcfg_in_writedata_0;
+        end
+        4'h9: begin
+          rcfg_out_address <= rcfg_in_address_1;
+          rcfg_out_writedata <= rcfg_in_writedata_1;
+        end
+        4'ha: begin
+          rcfg_out_address <= rcfg_in_address_2;
+          rcfg_out_writedata <= rcfg_in_writedata_2;
+        end
+        4'hb: begin
+          rcfg_out_address <= rcfg_in_address_3;
+          rcfg_out_writedata <= rcfg_in_writedata_3;
+        end
+        4'hc: begin
+          rcfg_out_address <= rcfg_in_address_4;
+          rcfg_out_writedata <= rcfg_in_writedata_4;
+        end
+        4'hd: begin
+          rcfg_out_address <= rcfg_in_address_5;
+          rcfg_out_writedata <= rcfg_in_writedata_5;
+        end
+        4'he: begin
+          rcfg_out_address <= rcfg_in_address_6;
+          rcfg_out_writedata <= rcfg_in_writedata_6;
+        end
+        4'hf: begin
+          rcfg_out_address <= rcfg_in_address_7;
+          rcfg_out_writedata <= rcfg_in_writedata_7;
+        end
+        default: begin
+          rcfg_out_address <= 12'd0;
+          rcfg_out_writedata <= 32'd0;
+        end
+      endcase
+    end
+  end
+
+  assign rcfg_out_read_0 = rcfg_out_iread_0;
+  assign rcfg_out_write_0 = rcfg_out_iwrite_0;
+  assign rcfg_in_readata_0 = rcfg_in_ireadata_0;
+  assign rcfg_in_waitrequest_0 = rcfg_in_iwaitrequest_0;
+  assign rcfg_out_read_1 = rcfg_out_iread_1;
+  assign rcfg_out_write_1 = rcfg_out_iwrite_1;
+  assign rcfg_in_readata_1 = rcfg_in_ireadata_1;
+  assign rcfg_in_waitrequest_1 = rcfg_in_iwaitrequest_1;
+  assign rcfg_out_read_2 = rcfg_out_iread_2;
+  assign rcfg_out_write_2 = rcfg_out_iwrite_2;
+  assign rcfg_in_readata_2 = rcfg_in_ireadata_2;
+  assign rcfg_in_waitrequest_2 = rcfg_in_iwaitrequest_2;
+  assign rcfg_out_read_3 = rcfg_out_iread_3;
+  assign rcfg_out_write_3 = rcfg_out_iwrite_3;
+  assign rcfg_in_readata_3 = rcfg_in_ireadata_3;
+  assign rcfg_in_waitrequest_3 = rcfg_in_iwaitrequest_3;
+  assign rcfg_out_read_4 = rcfg_out_iread_4;
+  assign rcfg_out_write_4 = rcfg_out_iwrite_4;
+  assign rcfg_in_readata_4 = rcfg_in_ireadata_4;
+  assign rcfg_in_waitrequest_4 = rcfg_in_iwaitrequest_4;
+  assign rcfg_out_read_5 = rcfg_out_iread_5;
+  assign rcfg_out_write_5 = rcfg_out_iwrite_5;
+  assign rcfg_in_readata_5 = rcfg_in_ireadata_5;
+  assign rcfg_in_waitrequest_5 = rcfg_in_iwaitrequest_5;
+  assign rcfg_out_read_6 = rcfg_out_iread_6;
+  assign rcfg_out_write_6 = rcfg_out_iwrite_6;
+  assign rcfg_in_readata_6 = rcfg_in_ireadata_6;
+  assign rcfg_in_waitrequest_6 = rcfg_in_iwaitrequest_6;
+  assign rcfg_out_read_7 = rcfg_out_iread_7;
+  assign rcfg_out_write_7 = rcfg_out_iwrite_7;
+  assign rcfg_in_readata_7 = rcfg_in_ireadata_7;
+  assign rcfg_in_waitrequest_7 = rcfg_in_iwaitrequest_7;
+
+  always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
+    if (rcfg_reset_n == 0) begin
+      rcfg_out_iread_0 <= 1'd0;
+      rcfg_out_iwrite_0 <= 1'd0;
+      rcfg_in_ireaddata_0 <= 32'd0;
+      rcfg_in_iwaitrequest_0 <= 1'd1;
+      rcfg_out_iread_1 <= 1'd0;
+      rcfg_out_iwrite_1 <= 1'd0;
+      rcfg_in_ireaddata_1 <= 32'd0;
+      rcfg_in_iwaitrequest_1 <= 1'd1;
+      rcfg_out_iread_2 <= 1'd0;
+      rcfg_out_iwrite_2 <= 1'd0;
+      rcfg_in_ireaddata_2 <= 32'd0;
+      rcfg_in_iwaitrequest_2 <= 1'd1;
+      rcfg_out_iread_3 <= 1'd0;
+      rcfg_out_iwrite_3 <= 1'd0;
+      rcfg_in_ireaddata_3 <= 32'd0;
+      rcfg_in_iwaitrequest_3 <= 1'd1;
+      rcfg_out_iread_4 <= 1'd0;
+      rcfg_out_iwrite_4 <= 1'd0;
+      rcfg_in_ireaddata_4 <= 32'd0;
+      rcfg_in_iwaitrequest_4 <= 1'd1;
+      rcfg_out_iread_5 <= 1'd0;
+      rcfg_out_iwrite_5 <= 1'd0;
+      rcfg_in_ireaddata_5 <= 32'd0;
+      rcfg_in_iwaitrequest_5 <= 1'd1;
+      rcfg_out_iread_6 <= 1'd0;
+      rcfg_out_iwrite_6 <= 1'd0;
+      rcfg_in_ireaddata_6 <= 32'd0;
+      rcfg_in_iwaitrequest_6 <= 1'd1;
+      rcfg_out_iread_7 <= 1'd0;
+      rcfg_out_iwrite_7 <= 1'd0;
+      rcfg_in_ireaddata_7 <= 32'd0;
+      rcfg_in_iwaitrequest_7 <= 1'd1;
+    end else begin
+      if (rcfg_select == 4'h8) begin
+        rcfg_out_iread_0 <= rcfg_in_read_0;
+        rcfg_out_iwrite_0 <= rcfg_in_write_0;
+        rcfg_in_ireaddata_0 <= rcfg_out_readdata_0;
+        rcfg_in_iwaitrequest_0 <= rcfg_out_waitrequest_0 | ~rcfg_in_req_0_s;
+      end else begin
+        rcfg_out_iread_0 <= 1'd0;
+        rcfg_out_iwrite_0 <= 1'd0;
+        rcfg_in_ireaddata_0 <= 32'd0;
+        rcfg_in_iwaitrequest_0 <= 1'd1;
+      end
+      if (rcfg_select == 4'h9) begin
+        rcfg_out_iread_1 <= rcfg_in_read_1;
+        rcfg_out_iwrite_1 <= rcfg_in_write_1;
+        rcfg_in_ireaddata_1 <= rcfg_out_readdata_1;
+        rcfg_in_iwaitrequest_1 <= rcfg_out_waitrequest_1 | ~rcfg_in_req_1_s;
+      end else begin
+        rcfg_out_iread_1 <= 1'd0;
+        rcfg_out_iwrite_1 <= 1'd0;
+        rcfg_in_ireaddata_1 <= 32'd0;
+        rcfg_in_iwaitrequest_1 <= 1'd1;
+      end
+      if (rcfg_select == 4'ha) begin
+        rcfg_out_iread_2 <= rcfg_in_read_2;
+        rcfg_out_iwrite_2 <= rcfg_in_write_2;
+        rcfg_in_ireaddata_2 <= rcfg_out_readdata_2;
+        rcfg_in_iwaitrequest_2 <= rcfg_out_waitrequest_2 | ~rcfg_in_req_2_s;
+      end else begin
+        rcfg_out_iread_2 <= 1'd0;
+        rcfg_out_iwrite_2 <= 1'd0;
+        rcfg_in_ireaddata_2 <= 32'd0;
+        rcfg_in_iwaitrequest_2 <= 1'd1;
+      end
+      if (rcfg_select == 4'hb) begin
+        rcfg_out_iread_3 <= rcfg_in_read_3;
+        rcfg_out_iwrite_3 <= rcfg_in_write_3;
+        rcfg_in_ireaddata_3 <= rcfg_out_readdata_3;
+        rcfg_in_iwaitrequest_3 <= rcfg_out_waitrequest_3 | ~rcfg_in_req_3_s;
+      end else begin
+        rcfg_out_iread_3 <= 1'd0;
+        rcfg_out_iwrite_3 <= 1'd0;
+        rcfg_in_ireaddata_3 <= 32'd0;
+        rcfg_in_iwaitrequest_3 <= 1'd1;
+      end
+      if (rcfg_select == 4'hc) begin
+        rcfg_out_iread_4 <= rcfg_in_read_4;
+        rcfg_out_iwrite_4 <= rcfg_in_write_4;
+        rcfg_in_ireaddata_4 <= rcfg_out_readdata_4;
+        rcfg_in_iwaitrequest_4 <= rcfg_out_waitrequest_4 | ~rcfg_in_req_4_s;
+      end else begin
+        rcfg_out_iread_4 <= 1'd0;
+        rcfg_out_iwrite_4 <= 1'd0;
+        rcfg_in_ireaddata_4 <= 32'd0;
+        rcfg_in_iwaitrequest_4 <= 1'd1;
+      end
+      if (rcfg_select == 4'hd) begin
+        rcfg_out_iread_5 <= rcfg_in_read_5;
+        rcfg_out_iwrite_5 <= rcfg_in_write_5;
+        rcfg_in_ireaddata_5 <= rcfg_out_readdata_5;
+        rcfg_in_iwaitrequest_5 <= rcfg_out_waitrequest_5 | ~rcfg_in_req_5_s;
+      end else begin
+        rcfg_out_iread_5 <= 1'd0;
+        rcfg_out_iwrite_5 <= 1'd0;
+        rcfg_in_ireaddata_5 <= 32'd0;
+        rcfg_in_iwaitrequest_5 <= 1'd1;
+      end
+      if (rcfg_select == 4'he) begin
+        rcfg_out_iread_6 <= rcfg_in_read_6;
+        rcfg_out_iwrite_6 <= rcfg_in_write_6;
+        rcfg_in_ireaddata_6 <= rcfg_out_readdata_6;
+        rcfg_in_iwaitrequest_6 <= rcfg_out_waitrequest_6 | ~rcfg_in_req_6_s;
+      end else begin
+        rcfg_out_iread_6 <= 1'd0;
+        rcfg_out_iwrite_6 <= 1'd0;
+        rcfg_in_ireaddata_6 <= 32'd0;
+        rcfg_in_iwaitrequest_6 <= 1'd1;
+      end
+      if (rcfg_select == 4'hf) begin
+        rcfg_out_iread_7 <= rcfg_in_read_7;
+        rcfg_out_iwrite_7 <= rcfg_in_write_7;
+        rcfg_in_ireaddata_7 <= rcfg_out_readdata_7;
+        rcfg_in_iwaitrequest_7 <= rcfg_out_waitrequest_7 | ~rcfg_in_req_7_s;
+      end else begin
+        rcfg_out_iread_7 <= 1'd0;
+        rcfg_out_iwrite_7 <= 1'd0;
+        rcfg_in_ireaddata_7 <= 32'd0;
+        rcfg_in_iwaitrequest_7 <= 1'd1;
+      end
+    end
+  end
+
+  assign rcfg_in_req_0_s = rcfg_in_read_0 | rcfg_in_write_0;
+  assign rcfg_in_req_1_s = rcfg_in_read_1 | rcfg_in_write_1;
+  assign rcfg_in_req_2_s = rcfg_in_read_2 | rcfg_in_write_2;
+  assign rcfg_in_req_3_s = rcfg_in_read_3 | rcfg_in_write_3;
+  assign rcfg_in_req_4_s = rcfg_in_read_4 | rcfg_in_write_4;
+  assign rcfg_in_req_5_s = rcfg_in_read_5 | rcfg_in_write_5;
+  assign rcfg_in_req_6_s = rcfg_in_read_6 | rcfg_in_write_6;
+  assign rcfg_in_req_7_s = rcfg_in_read_7 | rcfg_in_write_7;
+
+  always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
+    if (rcfg_reset_n == 0) begin
+      rcfg_select <= 4'h0;
+    end else begin
+      case (rcfg_select)
+        4'h8: begin
+          if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+        4'h9: begin
+          if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+        4'ha: begin
+          if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+        4'hb: begin
+          if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+        4'hc: begin
+          if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+        4'hd: begin
+          if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+        4'he: begin
+          if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+        4'hf: begin
+          if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+        default: begin
+          if (rcfg_in_req_0_s == 1'b1) begin
+            rcfg_select <= 4'h8;
+          end else if (rcfg_in_req_1_s == 1'b1) begin
+            rcfg_select <= 4'h9;
+          end else if (rcfg_in_req_2_s == 1'b1) begin
+            rcfg_select <= 4'ha;
+          end else if (rcfg_in_req_3_s == 1'b1) begin
+            rcfg_select <= 4'hb;
+          end else if (rcfg_in_req_4_s == 1'b1) begin
+            rcfg_select <= 4'hc;
+          end else if (rcfg_in_req_5_s == 1'b1) begin
+            rcfg_select <= 4'hd;
+          end else if (rcfg_in_req_6_s == 1'b1) begin
+            rcfg_select <= 4'he;
+          end else if (rcfg_in_req_7_s == 1'b1) begin
+            rcfg_select <= 4'hf;
+          end else begin
+            rcfg_select <= 4'h0;
+          end
+        end
+      endcase
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl b/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
new file mode 100644
index 000000000..99c8e97f9
--- /dev/null
+++ b/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
@@ -0,0 +1,77 @@
+
+package require -exact qsys 14.0
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
+
+set_module_property NAME axi_adxcvr
+set_module_property DESCRIPTION "AXI ADXCVR Interface"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME axi_adxcvr
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
+set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr
+add_fileset_file up_axi.v                 VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
+add_fileset_file axi_adxcvr_up.v          VERILOG PATH axi_adxcvr_up.v
+add_fileset_file axi_adxcvr.v             VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE
+
+# parameters
+
+add_parameter ID INTEGER 0
+set_parameter_property ID DISPLAY_NAME ID
+set_parameter_property ID TYPE INTEGER
+set_parameter_property ID UNITS None
+set_parameter_property ID HDL_PARAMETER true
+
+add_parameter TX_OR_RX_N INTEGER 0
+set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
+# axi4 slave interface
+
+add_interface s_axi_clock clock end
+add_interface_port s_axi_clock s_axi_aclk clk Input 1
+
+add_interface s_axi_reset reset end
+set_interface_property s_axi_reset associatedClock s_axi_clock
+add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
+
+add_interface s_axi axi4lite end
+set_interface_property s_axi associatedClock s_axi_clock
+set_interface_property s_axi associatedReset s_axi_reset
+add_interface_port s_axi s_axi_awvalid awvalid Input 1
+add_interface_port s_axi s_axi_awaddr awaddr Input 16
+add_interface_port s_axi s_axi_awprot awprot Input 3
+add_interface_port s_axi s_axi_awready awready Output 1
+add_interface_port s_axi s_axi_wvalid wvalid Input 1
+add_interface_port s_axi s_axi_wdata wdata Input 32
+add_interface_port s_axi s_axi_wstrb wstrb Input 4
+add_interface_port s_axi s_axi_wready wready Output 1
+add_interface_port s_axi s_axi_bvalid bvalid Output 1
+add_interface_port s_axi s_axi_bresp bresp Output 2
+add_interface_port s_axi s_axi_bready bready Input 1
+add_interface_port s_axi s_axi_arvalid arvalid Input 1
+add_interface_port s_axi s_axi_araddr araddr Input 16
+add_interface_port s_axi s_axi_arprot arprot Input 3
+add_interface_port s_axi s_axi_arready arready Output 1
+add_interface_port s_axi s_axi_rvalid rvalid Output 1
+add_interface_port s_axi s_axi_rresp rresp Output 2
+add_interface_port s_axi s_axi_rdata rdata Output 32
+add_interface_port s_axi s_axi_rready rready Input 1
+
+# xcvr interface
+
+add_interface if_xcvr conduit end
+add_interface_port if_xcvr up_rst             up_rst            Output   1
+add_interface_port if_xcvr up_ref_pll_locked  up_ref_pll_locked Input    1
+add_interface_port if_xcvr up_pll_locked      up_pll_locked     Input    1
+add_interface_port if_xcvr up_ready           up_ready          Input    1
+
+set_interface_property if_xcvr associatedClock s_axi_clock
+
+
diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
new file mode 100755
index 000000000..fd0da3439
--- /dev/null
+++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
@@ -0,0 +1,299 @@
+
+package require -exact qsys 14.0
+
+set_module_property NAME avl_adxcvr
+set_module_property DESCRIPTION "Avalon Transceiver"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME avl_adxcvr
+set_module_property COMPOSITION_CALLBACK p_avl_adxcvr
+
+# parameters
+
+add_parameter DEVICE_FAMILY STRING 
+set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
+set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
+set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
+set_parameter_property DEVICE_FAMILY ENABLED false
+
+add_parameter TX_OR_RX_N INTEGER 0
+set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
+set_parameter_property TX_OR_RX_N TYPE INTEGER
+set_parameter_property TX_OR_RX_N UNITS None
+set_parameter_property TX_OR_RX_N HDL_PARAMETER false
+
+add_parameter ID INTEGER 0
+set_parameter_property ID DISPLAY_NAME ID
+set_parameter_property ID TYPE INTEGER
+set_parameter_property ID UNITS None
+set_parameter_property ID HDL_PARAMETER false
+
+add_parameter PCS_CONFIG STRING "JESD_PCS_CFG2"
+set_parameter_property PCS_CONFIG DISPLAY_NAME PCS_CONFIG
+set_parameter_property PCS_CONFIG TYPE STRING
+set_parameter_property PCS_CONFIG UNITS None
+set_parameter_property PCS_CONFIG HDL_PARAMETER false
+
+add_parameter LANE_RATE FLOAT 10000
+set_parameter_property LANE_RATE DISPLAY_NAME LANE_RATE
+set_parameter_property LANE_RATE TYPE FLOAT
+set_parameter_property LANE_RATE UNITS None
+set_parameter_property LANE_RATE DISPLAY_UNITS "Mbps"
+set_parameter_property LANE_RATE HDL_PARAMETER false
+
+add_parameter PLLCLK_FREQUENCY FLOAT 5000.0
+set_parameter_property PLLCLK_FREQUENCY DISPLAY_NAME PLLCLK_FREQUENCY
+set_parameter_property PLLCLK_FREQUENCY TYPE FLOAT
+set_parameter_property PLLCLK_FREQUENCY UNITS Megahertz
+set_parameter_property PLLCLK_FREQUENCY HDL_PARAMETER false
+
+add_parameter REFCLK_FREQUENCY FLOAT 500.0
+set_parameter_property REFCLK_FREQUENCY DISPLAY_NAME REFCLK_FREQUENCY
+set_parameter_property REFCLK_FREQUENCY TYPE FLOAT
+set_parameter_property REFCLK_FREQUENCY UNITS Megahertz
+set_parameter_property REFCLK_FREQUENCY HDL_PARAMETER false
+
+add_parameter CORECLK_FREQUENCY FLOAT 250.0
+set_parameter_property CORECLK_FREQUENCY DISPLAY_NAME CORECLK_FREQUENCY
+set_parameter_property CORECLK_FREQUENCY TYPE FLOAT
+set_parameter_property CORECLK_FREQUENCY UNITS Megahertz
+set_parameter_property CORECLK_FREQUENCY HDL_PARAMETER false
+
+add_parameter NUM_OF_LANES INTEGER 4
+set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
+set_parameter_property NUM_OF_LANES TYPE INTEGER
+set_parameter_property NUM_OF_LANES UNITS None
+set_parameter_property NUM_OF_LANES HDL_PARAMETER false
+
+add_parameter NUM_OF_CONVS INTEGER 2
+set_parameter_property NUM_OF_CONVS DISPLAY_NAME NUM_OF_CONVS
+set_parameter_property NUM_OF_CONVS TYPE INTEGER
+set_parameter_property NUM_OF_CONVS UNITS None
+set_parameter_property NUM_OF_CONVS HDL_PARAMETER false
+
+add_parameter FRM_BCNT INTEGER 1
+set_parameter_property FRM_BCNT DISPLAY_NAME FRM_BCNT
+set_parameter_property FRM_BCNT TYPE INTEGER
+set_parameter_property FRM_BCNT UNITS None
+set_parameter_property FRM_BCNT HDL_PARAMETER false
+
+add_parameter FRM_SCNT INTEGER 1
+set_parameter_property FRM_SCNT DISPLAY_NAME FRM_SCNT
+set_parameter_property FRM_SCNT TYPE INTEGER
+set_parameter_property FRM_SCNT UNITS None
+set_parameter_property FRM_SCNT HDL_PARAMETER false
+
+add_parameter MF_FCNT INTEGER 32
+set_parameter_property MF_FCNT DISPLAY_NAME MF_FCNT
+set_parameter_property MF_FCNT TYPE INTEGER
+set_parameter_property MF_FCNT UNITS None
+set_parameter_property MF_FCNT HDL_PARAMETER false
+
+add_parameter HD INTEGER 1
+set_parameter_property HD DISPLAY_NAME HD
+set_parameter_property HD TYPE INTEGER
+set_parameter_property HD UNITS None
+set_parameter_property HD HDL_PARAMETER false
+
+proc p_avl_adxcvr {} {
+
+  set m_id [get_parameter_value "ID"]
+  set m_lane_rate [get_parameter_value "LANE_RATE"]
+  set m_pcs_config [get_parameter_value "PCS_CONFIG"]
+  set m_tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
+  set m_num_of_lanes [get_parameter_value "NUM_OF_LANES"]
+  set m_device_family [get_parameter_value "DEVICE_FAMILY"]
+  set m_pllclk_frequency [get_parameter_value "PLLCLK_FREQUENCY"]
+  set m_refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
+  set m_coreclk_frequency [get_parameter_value "CORECLK_FREQUENCY"]
+  set m_num_of_convs [get_parameter_value "NUM_OF_CONVS"]
+  set m_frm_bcnt [get_parameter_value "FRM_BCNT"]
+  set m_frm_scnt [get_parameter_value "FRM_SCNT"]
+  set m_mf_fcnt [get_parameter_value "MF_FCNT"]
+  set m_hd [get_parameter_value "HD"]
+
+  add_instance alt_sys_clk clock_source 16.0
+  set_instance_parameter_value alt_sys_clk {clockFrequency} {100000000.0}
+  add_interface sys_clk clock sink
+  set_interface_property sys_clk EXPORT_OF alt_sys_clk.clk_in
+  add_interface sys_resetn reset sink
+  set_interface_property sys_resetn EXPORT_OF alt_sys_clk.clk_in_reset
+
+  add_instance alt_ref_clk altera_clock_bridge 16.0
+  set_instance_parameter_value alt_ref_clk {EXPLICIT_CLOCK_RATE} $m_refclk_frequency
+  add_interface ref_clk clock sink
+  set_interface_property ref_clk EXPORT_OF alt_ref_clk.in_clk
+
+  add_instance alt_ref_pll altera_iopll 16.0
+  set_instance_parameter_value alt_ref_pll {gui_en_reconf} {1}
+  set_instance_parameter_value alt_ref_pll {gui_reference_clock_frequency} $m_refclk_frequency
+  set_instance_parameter_value alt_ref_pll {gui_use_locked} {1}
+  set_instance_parameter_value alt_ref_pll {gui_output_clock_frequency0} $m_coreclk_frequency
+  add_connection alt_ref_clk.out_clk alt_ref_pll.refclk
+  add_connection alt_sys_clk.clk_reset alt_ref_pll.reset
+  add_interface ref_pll_locked conduit end
+  set_interface_property ref_pll_locked EXPORT_OF alt_ref_pll.locked
+
+  add_instance alt_ref_pll_reconfig altera_pll_reconfig 16.0
+  add_connection alt_sys_clk.clk_reset alt_ref_pll_reconfig.mgmt_reset
+  add_connection alt_sys_clk.clk alt_ref_pll_reconfig.mgmt_clk
+  add_connection alt_ref_pll_reconfig.reconfig_to_pll alt_ref_pll.reconfig_to_pll
+  add_connection alt_ref_pll.reconfig_from_pll alt_ref_pll_reconfig.reconfig_from_pll
+  add_interface ref_pll_reconfig avalon slave
+  set_interface_property ref_pll_reconfig EXPORT_OF alt_ref_pll_reconfig.mgmt_avalon_slave
+
+  add_instance alt_core_clk altera_clock_bridge 16.0
+  set_instance_parameter_value alt_core_clk {EXPLICIT_CLOCK_RATE} $m_coreclk_frequency
+  add_connection alt_ref_pll.outclk0 alt_core_clk.in_clk
+  add_interface core_clk clock source
+  set_interface_property core_clk EXPORT_OF alt_core_clk.out_clk
+
+  if {$m_tx_or_rx_n == 1} {
+
+    add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0
+    set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes
+    set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} {100}
+    set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {1}
+    set_instance_parameter_value alt_rst_cntrol {T_PLL_POWERDOWN} {1000}
+    set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {1}
+    set_instance_parameter_value alt_rst_cntrol {T_TX_ANALOGRESET} {70000}
+    set_instance_parameter_value alt_rst_cntrol {T_TX_DIGITALRESET} {70000}
+    set_instance_parameter_value alt_rst_cntrol {gui_pll_cal_busy} {1}
+    set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {0}
+    add_connection alt_sys_clk.clk alt_rst_cntrol.clock
+    add_interface rst reset sink
+    set_interface_property rst EXPORT_OF alt_rst_cntrol.reset
+    add_interface ready conduit end
+    set_interface_property ready EXPORT_OF alt_rst_cntrol.tx_ready
+
+    add_instance alt_lane_pll altera_xcvr_atx_pll_a10 16.0
+    set_instance_parameter_value alt_lane_pll {enable_pll_reconfig} {1}
+    set_instance_parameter_value alt_lane_pll {rcfg_separate_avmm_busy} {1}
+    set_instance_parameter_value alt_lane_pll {set_capability_reg_enable} {1}
+    set_instance_parameter_value alt_lane_pll {set_user_identifier} $m_id
+    set_instance_parameter_value alt_lane_pll {set_csr_soft_logic_enable} {1}
+    set_instance_parameter_value alt_lane_pll {set_output_clock_frequency} $m_pllclk_frequency
+    set_instance_parameter_value alt_lane_pll {set_auto_reference_clock_frequency} $m_refclk_frequency
+    add_connection alt_rst_cntrol.pll_powerdown alt_lane_pll.pll_powerdown
+    add_connection alt_lane_pll.pll_locked alt_rst_cntrol.pll_locked
+    add_connection alt_lane_pll.pll_cal_busy alt_rst_cntrol.pll_cal_busy
+    add_connection alt_ref_clk.out_clk alt_lane_pll.pll_refclk0
+    add_connection alt_sys_clk.clk alt_lane_pll.reconfig_clk0
+    add_connection alt_sys_clk.clk_reset alt_lane_pll.reconfig_reset0
+    add_interface lane_pll_reconfig avalon slave
+    set_interface_property lane_pll_reconfig EXPORT_OF alt_lane_pll.reconfig_avmm0
+
+    add_instance alt_xcvr altera_jesd204 16.0
+    set_instance_parameter_value alt_xcvr {wrapper_opt} {base_phy}
+    set_instance_parameter_value alt_xcvr {DATA_PATH} {TX}
+    set_instance_parameter_value alt_xcvr {lane_rate} $m_lane_rate
+    set_instance_parameter_value alt_xcvr {PCS_CONFIG} $m_pcs_config
+    set_instance_parameter_value alt_xcvr {bonded_mode} {non_bonded}
+    set_instance_parameter_value alt_xcvr {pll_reconfig_enable} {1}
+    set_instance_parameter_value alt_xcvr {set_capability_reg_enable} {1}
+    set_instance_parameter_value alt_xcvr {set_user_identifier} $m_id
+    set_instance_parameter_value alt_xcvr {set_csr_soft_logic_enable} {1}
+    set_instance_parameter_value alt_xcvr {L} $m_num_of_lanes
+    set_instance_parameter_value alt_xcvr {M} $m_num_of_convs
+    set_instance_parameter_value alt_xcvr {GUI_EN_CFG_F} {1}
+    set_instance_parameter_value alt_xcvr {GUI_CFG_F} $m_frm_bcnt
+    set_instance_parameter_value alt_xcvr {N} {16}
+    set_instance_parameter_value alt_xcvr {N_PRIME} {16}
+    set_instance_parameter_value alt_xcvr {S} $m_frm_scnt
+    set_instance_parameter_value alt_xcvr {K} $m_mf_fcnt
+    set_instance_parameter_value alt_xcvr {SCR} {1}
+    set_instance_parameter_value alt_xcvr {HD} $m_hd
+    add_connection alt_rst_cntrol.tx_digitalreset alt_xcvr.tx_digitalreset
+    add_connection alt_rst_cntrol.tx_analogreset alt_xcvr.tx_analogreset
+    add_connection alt_xcvr.tx_cal_busy alt_rst_cntrol.tx_cal_busy
+    add_connection alt_xcvr.dev_sync_n alt_xcvr.mdev_sync_n
+    add_connection alt_sys_clk.clk alt_xcvr.reconfig_clk
+    add_connection alt_sys_clk.clk_reset alt_xcvr.reconfig_reset
+    add_interface phy_reconfig avalon slave
+    set_interface_property phy_reconfig EXPORT_OF alt_xcvr.reconfig_avmm
+    add_connection alt_sys_clk.clk alt_xcvr.jesd204_tx_avs_clk
+    add_connection alt_sys_clk.clk_reset alt_xcvr.jesd204_tx_avs_rst_n
+    add_interface ip_reconfig avalon slave
+    set_interface_property ip_reconfig EXPORT_OF alt_xcvr.jesd204_tx_avs
+    add_connection alt_ref_pll.outclk0 alt_xcvr.txlink_clk
+    add_connection alt_sys_clk.clk_reset alt_xcvr.txlink_rst_n
+    add_interface ip_data avalon_streaming sink
+    set_interface_property ip_data EXPORT_OF alt_xcvr.jesd204_tx_link
+    add_interface sysref conduit end
+    set_interface_property sysref EXPORT_OF alt_xcvr.sysref
+    add_interface sync conduit end
+    set_interface_property sync EXPORT_OF alt_xcvr.sync_n
+    add_interface tx_data conduit end
+    set_interface_property tx_data EXPORT_OF alt_xcvr.tx_serial_data
+    add_interface pll_locked conduit end
+    set_interface_property pll_locked EXPORT_OF alt_xcvr.pll_locked
+    for {set n 0} {$n < $m_num_of_lanes} {incr n} {
+      add_connection alt_lane_pll.tx_serial_clk alt_xcvr.tx_serial_clk0_ch${n}
+    }
+  }
+
+  if {$m_tx_or_rx_n == 0} {
+
+    add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0
+    set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes
+    set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} {100}
+    set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {0}
+    set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {0}
+    set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {1}
+    set_instance_parameter_value alt_rst_cntrol {T_RX_ANALOGRESET} {70000}
+    set_instance_parameter_value alt_rst_cntrol {T_RX_DIGITALRESET} {4000}
+    add_connection alt_sys_clk.clk alt_rst_cntrol.clock
+    add_interface rst reset sink
+    set_interface_property rst EXPORT_OF alt_rst_cntrol.reset
+    add_interface ready conduit end
+    set_interface_property ready EXPORT_OF alt_rst_cntrol.rx_ready
+
+    add_instance alt_xcvr altera_jesd204 16.0
+    set_instance_parameter_value alt_xcvr {wrapper_opt} {base_phy}
+    set_instance_parameter_value alt_xcvr {DATA_PATH} {RX}
+    set_instance_parameter_value alt_xcvr {lane_rate} $m_lane_rate
+    set_instance_parameter_value alt_xcvr {PCS_CONFIG} $m_pcs_config
+    set_instance_parameter_value alt_xcvr {REFCLK_FREQ} $m_refclk_frequency
+    set_instance_parameter_value alt_xcvr {pll_reconfig_enable} {1}
+    set_instance_parameter_value alt_xcvr {set_capability_reg_enable} {1}
+    set_instance_parameter_value alt_xcvr {set_user_identifier} $m_id
+    set_instance_parameter_value alt_xcvr {set_csr_soft_logic_enable} {1}
+    set_instance_parameter_value alt_xcvr {L} $m_num_of_lanes
+    set_instance_parameter_value alt_xcvr {M} $m_num_of_convs
+    set_instance_parameter_value alt_xcvr {GUI_EN_CFG_F} {1}
+    set_instance_parameter_value alt_xcvr {GUI_CFG_F} $m_frm_bcnt
+    set_instance_parameter_value alt_xcvr {N} {16}
+    set_instance_parameter_value alt_xcvr {N_PRIME} {16}
+    set_instance_parameter_value alt_xcvr {S} $m_frm_scnt
+    set_instance_parameter_value alt_xcvr {K} $m_mf_fcnt
+    set_instance_parameter_value alt_xcvr {SCR} {1}
+    set_instance_parameter_value alt_xcvr {HD} $m_hd
+    add_connection alt_rst_cntrol.rx_digitalreset alt_xcvr.rx_digitalreset
+    add_connection alt_rst_cntrol.rx_analogreset alt_xcvr.rx_analogreset
+    add_connection alt_xcvr.rx_cal_busy alt_rst_cntrol.rx_cal_busy
+    add_connection alt_xcvr.rx_islockedtodata alt_rst_cntrol.rx_is_lockedtodata
+    add_connection alt_xcvr.dev_lane_aligned alt_xcvr.alldev_lane_aligned
+    add_connection alt_sys_clk.clk alt_xcvr.reconfig_clk
+    add_connection alt_sys_clk.clk_reset alt_xcvr.reconfig_reset
+    add_interface phy_reconfig avalon slave
+    set_interface_property phy_reconfig EXPORT_OF alt_xcvr.reconfig_avmm
+    add_connection alt_sys_clk.clk alt_xcvr.jesd204_rx_avs_clk
+    add_connection alt_sys_clk.clk_reset alt_xcvr.jesd204_rx_avs_rst_n
+    add_interface ip_reconfig avalon slave
+    set_interface_property ip_reconfig EXPORT_OF alt_xcvr.jesd204_rx_avs
+    add_connection alt_ref_clk.out_clk alt_xcvr.pll_ref_clk
+    add_connection alt_ref_pll.outclk0 alt_xcvr.rxlink_clk
+    add_connection alt_sys_clk.clk_reset alt_xcvr.rxlink_rst_n
+    add_interface ip_data avalon_streaming source
+    set_interface_property ip_data EXPORT_OF alt_xcvr.jesd204_rx_link
+    add_interface sysref conduit end
+    set_interface_property sysref EXPORT_OF alt_xcvr.sysref
+    add_interface sync conduit end
+    set_interface_property sync EXPORT_OF alt_xcvr.dev_sync_n
+    add_interface ip_sof conduit end
+    set_interface_property ip_sof EXPORT_OF alt_xcvr.sof
+    add_interface rx_data conduit end
+    set_interface_property rx_data EXPORT_OF alt_xcvr.rx_serial_data
+  }
+}
+
diff --git a/library/altera/axi_adxcvr/axi_adxcvr.v b/library/altera/axi_adxcvr/axi_adxcvr.v
new file mode 100644
index 000000000..79e33ba8d
--- /dev/null
+++ b/library/altera/axi_adxcvr/axi_adxcvr.v
@@ -0,0 +1,148 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module axi_adxcvr (
+
+  // xcvr, lane-pll and ref-pll are shared
+
+  output          up_rst,
+  input           up_ref_pll_locked,
+  input           up_pll_locked,
+  input           up_ready,
+
+  input           s_axi_clk,
+  input           s_axi_aresetn,
+  input           s_axi_awvalid,
+  input   [31:0]  s_axi_awaddr,
+  input   [ 2:0]  s_axi_awprot,
+  output          s_axi_awready,
+  input           s_axi_wvalid,
+  input   [31:0]  s_axi_wdata,
+  input   [ 3:0]  s_axi_wstrb,
+  output          s_axi_wready,
+  output          s_axi_bvalid,
+  output  [ 1:0]  s_axi_bresp,
+  input           s_axi_bready,
+  input           s_axi_arvalid,
+  input   [31:0]  s_axi_araddr,
+  input   [ 2:0]  s_axi_arprot,
+  output          s_axi_arready,
+  output          s_axi_rvalid,
+  output  [ 1:0]  s_axi_rresp,
+  output  [31:0]  s_axi_rdata,
+  input           s_axi_rready);
+
+  // parameters
+
+  parameter   integer ID = 0;
+  parameter   integer TX_OR_RX_N = 0;
+
+  // internal signals
+
+  wire            up_rstn;
+  wire            up_clk;
+  wire            up_wreq;
+  wire    [ 9:0]  up_waddr;
+  wire    [31:0]  up_wdata;
+  wire            up_wack;
+  wire            up_rreq;
+  wire    [ 9:0]  up_raddr;
+  wire    [31:0]  up_rdata;
+  wire            up_rack;
+
+  // clk & rst
+
+  assign up_rstn = axi_aresetn;
+  assign up_clk = axi_clk;
+
+  // instantiations
+
+  axi_adxcvr_up #(
+    .ID (ID),
+    .TX_OR_RX_N (TX_OR_RX_N))
+  i_up (
+    .up_rst (up_rst),
+    .up_ref_pll_locked (up_ref_pll_locked),
+    .up_pll_locked (up_pll_locked),
+    .up_ready (up_ready),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+  up_axi #(.ADDRESS_WIDTH (10)) i_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
new file mode 100644
index 000000000..99c8e97f9
--- /dev/null
+++ b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
@@ -0,0 +1,77 @@
+
+package require -exact qsys 14.0
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
+
+set_module_property NAME axi_adxcvr
+set_module_property DESCRIPTION "AXI ADXCVR Interface"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME axi_adxcvr
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
+set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr
+add_fileset_file up_axi.v                 VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
+add_fileset_file axi_adxcvr_up.v          VERILOG PATH axi_adxcvr_up.v
+add_fileset_file axi_adxcvr.v             VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE
+
+# parameters
+
+add_parameter ID INTEGER 0
+set_parameter_property ID DISPLAY_NAME ID
+set_parameter_property ID TYPE INTEGER
+set_parameter_property ID UNITS None
+set_parameter_property ID HDL_PARAMETER true
+
+add_parameter TX_OR_RX_N INTEGER 0
+set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
+# axi4 slave interface
+
+add_interface s_axi_clock clock end
+add_interface_port s_axi_clock s_axi_aclk clk Input 1
+
+add_interface s_axi_reset reset end
+set_interface_property s_axi_reset associatedClock s_axi_clock
+add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
+
+add_interface s_axi axi4lite end
+set_interface_property s_axi associatedClock s_axi_clock
+set_interface_property s_axi associatedReset s_axi_reset
+add_interface_port s_axi s_axi_awvalid awvalid Input 1
+add_interface_port s_axi s_axi_awaddr awaddr Input 16
+add_interface_port s_axi s_axi_awprot awprot Input 3
+add_interface_port s_axi s_axi_awready awready Output 1
+add_interface_port s_axi s_axi_wvalid wvalid Input 1
+add_interface_port s_axi s_axi_wdata wdata Input 32
+add_interface_port s_axi s_axi_wstrb wstrb Input 4
+add_interface_port s_axi s_axi_wready wready Output 1
+add_interface_port s_axi s_axi_bvalid bvalid Output 1
+add_interface_port s_axi s_axi_bresp bresp Output 2
+add_interface_port s_axi s_axi_bready bready Input 1
+add_interface_port s_axi s_axi_arvalid arvalid Input 1
+add_interface_port s_axi s_axi_araddr araddr Input 16
+add_interface_port s_axi s_axi_arprot arprot Input 3
+add_interface_port s_axi s_axi_arready arready Output 1
+add_interface_port s_axi s_axi_rvalid rvalid Output 1
+add_interface_port s_axi s_axi_rresp rresp Output 2
+add_interface_port s_axi s_axi_rdata rdata Output 32
+add_interface_port s_axi s_axi_rready rready Input 1
+
+# xcvr interface
+
+add_interface if_xcvr conduit end
+add_interface_port if_xcvr up_rst             up_rst            Output   1
+add_interface_port if_xcvr up_ref_pll_locked  up_ref_pll_locked Input    1
+add_interface_port if_xcvr up_pll_locked      up_pll_locked     Input    1
+add_interface_port if_xcvr up_ready           up_ready          Input    1
+
+set_interface_property if_xcvr associatedClock s_axi_clock
+
+
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v
new file mode 100644
index 000000000..78dd84489
--- /dev/null
+++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v
@@ -0,0 +1,158 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_adxcvr_up (
+
+  // xcvr, lane-pll and ref-pll are shared
+
+  output          up_rst,
+  input           up_ref_pll_locked,
+  input           up_pll_locked,
+  input           up_ready,
+
+  // bus interface
+
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [ 9:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [ 9:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
+
+  // parameters
+
+  localparam  [31:0]  VERSION = 32'h00100161;
+  parameter   integer ID = 0;
+  parameter   integer TX_OR_RX_N = 0;
+
+  // internal registers
+
+  reg             up_wreq_d = 'd0;
+  reg     [31:0]  up_scratch = 'd0;
+  reg             up_resetn = 'd0;
+  reg     [ 3:0]  up_rst_cnt = 'd0;
+  reg             up_status_int = 'd0;
+  reg             up_rreq_d = 'd0;
+  reg     [31:0]  up_rdata_d = 'd0;
+
+  // defaults
+
+  assign up_wack = up_wreq_d;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wreq_d <= 'd0;
+      up_scratch <= 'd0;
+    end else begin
+      up_wreq_d <= up_wreq;
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin
+        up_scratch <= up_wdata;
+      end
+    end
+  end
+
+  // reset-controller
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_resetn <= 'd0;
+    end else begin
+      if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin
+        up_resetn <= up_wdata[0];
+      end
+    end
+  end
+
+  assign up_rst = up_rst_cnt[3];
+  assign up_status = up_status_int;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rst_cnt <= 4'h8;
+      up_status_int <= 1'b0;
+    end else begin
+      if (up_resetn == 1'b0) begin
+        up_rst_cnt <= 4'h8;
+      end else if (up_rst_cnt[3] == 1'b1) begin
+        up_rst_cnt <= up_rst_cnt + 1'b1;
+      end
+      if (up_resetn == 1'b0) begin
+        up_status_int <= 1'b0;
+      end else if ((up_pll_locked == 1'b1) && (up_ready == 1'b1) &&
+        (up_ref_pll_locked == 1'b1)) begin
+        up_status_int <= 1'b1;
+      end
+    end
+  end
+
+  // read interface
+
+  assign up_rack = up_rreq_d;
+  assign up_rdata = up_rdata_d;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rreq_d <= 'd0;
+      up_rdata_d <= 'd0;
+    end else begin
+      up_rreq_d <= up_rreq;
+      if (up_rreq == 1'b1) begin
+        case (up_raddr)
+          10'h000: up_rdata_d <= VERSION;
+          10'h001: up_rdata_d <= ID;
+          10'h002: up_rdata_d <= up_scratch;
+          10'h004: up_rdata_d <= {31'd0, up_resetn};
+          10'h005: up_rdata_d <= {31'd0, up_status_int};
+          10'h006: up_rdata_d <= {29'd0, up_pll_locked, up_ref_pll_locked, up_ready};
+          default: up_rdata_d <= 32'd0;
+        endcase
+      end else begin
+        up_rdata_d <= 32'd0;
+      end
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 4248b9373a28b68a9324e69dd94c8219437476fe Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 30 Aug 2016 16:08:07 +0300
Subject: [PATCH 436/972] ad6676evb: Update to Vivado 2016.2

---
 projects/ad6676evb/common/ad6676evb_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl
index 11d73bd7f..7424ec3eb 100644
--- a/projects/ad6676evb/common/ad6676evb_bd.tcl
+++ b/projects/ad6676evb/common/ad6676evb_bd.tcl
@@ -11,7 +11,7 @@ create_bd_port -dir I -from 1 -to 0 rx_data_n
 
 set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
 
-set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad6676_jesd]
+set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad6676_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd
 set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd
 

From 6f0d1248614a78fe6ba0f1e9d48cecd444d2f99e Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 30 Aug 2016 16:09:28 +0300
Subject: [PATCH 437/972] fmcadc5: Update to Vivado 2016.2

---
 projects/fmcadc5/common/fmcadc5_bd.tcl | 4 ++--
 projects/fmcadc5/vc707/system_bd.tcl   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl
index 210a862da..3ddb1360e 100644
--- a/projects/fmcadc5/common/fmcadc5_bd.tcl
+++ b/projects/fmcadc5/common/fmcadc5_bd.tcl
@@ -19,10 +19,10 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
 set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
 set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
 
-set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_0_jesd]
+set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_0_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
-set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_1_jesd]
+set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_1_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
 
diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl
index 7bc7f1a11..1a8b7ed36 100644
--- a/projects/fmcadc5/vc707/system_bd.tcl
+++ b/projects/fmcadc5/vc707/system_bd.tcl
@@ -10,7 +10,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc
 set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc
 set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc
 
-set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
+set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
 set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc

From 2015bcedaa66aa8c7ee664d7f3adbe7e0b9544aa Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 30 Aug 2016 16:42:58 +0300
Subject: [PATCH 438/972] fmcadc2: Update common design to Vivado 2016.2

---
 projects/fmcadc2/common/fmcadc2_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl
index 7d684044d..516509a07 100644
--- a/projects/fmcadc2/common/fmcadc2_bd.tcl
+++ b/projects/fmcadc2/common/fmcadc2_bd.tcl
@@ -11,7 +11,7 @@ create_bd_port -dir I -from 7 -to 0 rx_data_n
 
 set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
 
-set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd]
+set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
 

From 1eccf5af078cb24ee45f8e7c49b1b98d94137741 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 30 Aug 2016 16:46:15 +0300
Subject: [PATCH 439/972] fmcomms7: Update common design to Vivado 2016.2

---
 projects/fmcomms7/common/fmcomms7_bd.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl
index 59e3cce66..d5af8eb08 100644
--- a/projects/fmcomms7/common/fmcomms7_bd.tcl
+++ b/projects/fmcomms7/common/fmcomms7_bd.tcl
@@ -26,7 +26,7 @@ create_bd_port -dir I spi2_sdi_i
 set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
 set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core
 
-set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd]
+set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd
 
@@ -50,7 +50,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack
 
 set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
 
-set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
+set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
 

From 8192e755e1add0a156d03baa5dcbcd9dc10ef4c0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 30 Aug 2016 11:47:55 -0400
Subject: [PATCH 440/972] altera- defaults

---
 projects/common/altera/sys_gen.tcl | 35 ++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 projects/common/altera/sys_gen.tcl

diff --git a/projects/common/altera/sys_gen.tcl b/projects/common/altera/sys_gen.tcl
new file mode 100644
index 000000000..25eaa37ad
--- /dev/null
+++ b/projects/common/altera/sys_gen.tcl
@@ -0,0 +1,35 @@
+
+# globals
+
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+
+# library paths
+
+set ad_lib_folders "$ad_hdl_dir/library/**/*;$ad_phdl_dir/library/**/*"
+
+set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
+set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
+
+# qsys-script is a crippled tool, so work around is generate a run-time one
+
+set mmu_enabled 1
+if [info exists ::env(ALT_NIOS_MMU_ENABLED)] {
+  set mmu_enabled $::env(ALT_NIOS_MMU_ENABLED)
+}
+
+set QFILE [open "system_qsys_script.tcl" "w"]
+puts $QFILE "set mmu_enabled $mmu_enabled"
+puts $QFILE "set ad_hdl_dir $ad_hdl_dir"
+puts $QFILE "set ad_phdl_dir $ad_phdl_dir"
+puts $QFILE "source system_qsys.tcl"
+close $QFILE
+
+exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
+  --script=system_qsys_script.tcl
+

From 917da79da1d80d4f77437d62084f417a756c5690 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 30 Aug 2016 11:49:12 -0400
Subject: [PATCH 441/972] altera- source defaults for qsys-script

---
 projects/common/a10gx/a10gx_system_assign.tcl | 36 ++-----------------
 1 file changed, 2 insertions(+), 34 deletions(-)

diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl
index 92a45c027..e31c7cf93 100755
--- a/projects/common/a10gx/a10gx_system_assign.tcl
+++ b/projects/common/a10gx/a10gx_system_assign.tcl
@@ -227,39 +227,7 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10]
 
-# globals
-
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
-set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
-
-# library paths
-
-set ad_lib_folders "$ad_hdl_dir/library/**/*;$ad_phdl_dir/library/**/*"
-
-set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
-set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
-
-# generate qsys
-# move this to a project script
-
-set mmu_enabled 1
-if [info exists ::env(ALT_NIOS_MMU_ENABLED)] {
-  set mmu_enabled $::env(ALT_NIOS_MMU_ENABLED)
-}
-
-if {$mmu_enabled == 0} {
-  set cmd_str "set mmu_enabled 0"
-  exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
-    --cmd=$cmd_str --script=system_qsys.tcl
-} else {
-  set cmd_str "set mmu_enabled 1"
-  exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
-    --cmd=$cmd_str --script=system_qsys.tcl
-}
+# source defaults
 
+source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
 

From 2f9ac4a342d2f98e6617b3923316ba14c48f8681 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 30 Aug 2016 11:50:13 -0400
Subject: [PATCH 442/972] altera- qsys-script does not support most tcl
 commands

---
 projects/daq2/a10gx/system_qsys.tcl | 2 --
 1 file changed, 2 deletions(-)

diff --git a/projects/daq2/a10gx/system_qsys.tcl b/projects/daq2/a10gx/system_qsys.tcl
index 50e56a642..2216c761a 100644
--- a/projects/daq2/a10gx/system_qsys.tcl
+++ b/projects/daq2/a10gx/system_qsys.tcl
@@ -1,6 +1,4 @@
 
-
-source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/daq2_qsys.tcl
 

From dc21384002833cdaa3abad0cfb7d6d2cb6a43ecf Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 1 Sep 2016 09:06:30 +0300
Subject: [PATCH 443/972] pzsdr: Update ccpci base design

---
 projects/pzsdr/common/ccpci_bd.tcl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/projects/pzsdr/common/ccpci_bd.tcl b/projects/pzsdr/common/ccpci_bd.tcl
index 6662565ec..c0157b824 100644
--- a/projects/pzsdr/common/ccpci_bd.tcl
+++ b/projects/pzsdr/common/ccpci_bd.tcl
@@ -49,7 +49,7 @@ ad_connect  pl_gpio1_t axi_gpio/gpio2_io_t
 
 # pci-express
 
-set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.7 axi_pcie_x4]
+set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.8 axi_pcie_x4]
 set_property -dict [list CONFIG.NO_OF_LANES {X4}] $axi_pcie_x4
 set_property -dict [list CONFIG.MAX_LINK_SPEED {5.0_GT/s}] $axi_pcie_x4
 set_property -dict [list CONFIG.VENDOR_ID {0x11D4}] $axi_pcie_x4
@@ -155,6 +155,7 @@ delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_t
 set axi_pcie_s_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_pcie_s_interconnect]
 set_property -dict [list CONFIG.NUM_SI {2}] $axi_pcie_s_interconnect
 set_property -dict [list CONFIG.NUM_MI {1}] $axi_pcie_s_interconnect
+set_property -dict [list CONFIG.STRATEGY {2} ] $axi_pcie_s_interconnect
 
 ad_connect  pcie_axi_clk axi_pcie_s_interconnect/ACLK
 ad_connect  pcie_axi_clk axi_pcie_s_interconnect/M00_ACLK

From 93fa5aeec37a95f830b2707682b343674c12de21 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Thu, 1 Sep 2016 16:11:39 +0300
Subject: [PATCH 444/972] fmcadc2/vc707: Add adf4355 access, update design to
 Vivado 2016.2

---
 projects/fmcadc2/vc707/system_constr.xdc | 62 ++++++++++++------------
 projects/fmcadc2/vc707/system_top.v      | 46 +++++++++---------
 2 files changed, 55 insertions(+), 53 deletions(-)

diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc
index 03009a936..47c95609b 100644
--- a/projects/fmcadc2/vc707/system_constr.xdc
+++ b/projects/fmcadc2/vc707/system_constr.xdc
@@ -1,39 +1,39 @@
 
 # ad9625
 
-set_property  -dict {PACKAGE_PIN  A10 } [get_ports rx_ref_clk_p]                                 ; ## D04  FMC1_HPC_GBTCLK0_M2C_P
-set_property  -dict {PACKAGE_PIN  A9  } [get_ports rx_ref_clk_n]                                 ; ## D05  FMC1_HPC_GBTCLK0_M2C_N
-set_property  -dict {PACKAGE_PIN  D8  } [get_ports rx_data_p[0]]                                 ; ## C06  FMC1_HPC_DP0_M2C_P
-set_property  -dict {PACKAGE_PIN  D7  } [get_ports rx_data_n[0]]                                 ; ## C07  FMC1_HPC_DP0_M2C_N
-set_property  -dict {PACKAGE_PIN  C6  } [get_ports rx_data_p[1]]                                 ; ## A02  FMC1_HPC_DP1_M2C_P
-set_property  -dict {PACKAGE_PIN  C5  } [get_ports rx_data_n[1]]                                 ; ## A03  FMC1_HPC_DP1_M2C_N
-set_property  -dict {PACKAGE_PIN  B8  } [get_ports rx_data_p[2]]                                 ; ## A06  FMC1_HPC_DP2_M2C_P
-set_property  -dict {PACKAGE_PIN  B7  } [get_ports rx_data_n[2]]                                 ; ## A07  FMC1_HPC_DP2_M2C_N
-set_property  -dict {PACKAGE_PIN  A6  } [get_ports rx_data_p[3]]                                 ; ## A10  FMC1_HPC_DP3_M2C_P
-set_property  -dict {PACKAGE_PIN  A5  } [get_ports rx_data_n[3]]                                 ; ## A11  FMC1_HPC_DP3_M2C_N
-set_property  -dict {PACKAGE_PIN  E6  } [get_ports rx_data_p[4]]                                 ; ## B12  FMC1_HPC_DP7_M2C_P
-set_property  -dict {PACKAGE_PIN  E5  } [get_ports rx_data_n[4]]                                 ; ## B13  FMC1_HPC_DP7_M2C_N
-set_property  -dict {PACKAGE_PIN  H8  } [get_ports rx_data_p[5]]                                 ; ## A14  FMC1_HPC_DP4_M2C_P
-set_property  -dict {PACKAGE_PIN  H7  } [get_ports rx_data_n[5]]                                 ; ## A15  FMC1_HPC_DP4_M2C_N
-set_property  -dict {PACKAGE_PIN  F8  } [get_ports rx_data_p[6]]                                 ; ## B16  FMC1_HPC_DP6_M2C_P
-set_property  -dict {PACKAGE_PIN  F7  } [get_ports rx_data_n[6]]                                 ; ## B17  FMC1_HPC_DP6_M2C_N
-set_property  -dict {PACKAGE_PIN  G6  } [get_ports rx_data_p[7]]                                 ; ## A18  FMC1_HPC_DP5_M2C_P
-set_property  -dict {PACKAGE_PIN  G5  } [get_ports rx_data_n[7]]                                 ; ## A19  FMC1_HPC_DP5_M2C_N
-set_property  -dict {PACKAGE_PIN  H40   IOSTANDARD LVDS} [get_ports rx_sync_p]                   ; ## H10  FMC1_HPC_LA04_P
-set_property  -dict {PACKAGE_PIN  H41   IOSTANDARD LVDS} [get_ports rx_sync_n]                   ; ## H11  FMC1_HPC_LA04_N
-set_property  -dict {PACKAGE_PIN  M41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p]  ; ## D11  FMC1_HPC_LA05_P
-set_property  -dict {PACKAGE_PIN  L41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n]  ; ## D12  FMC1_HPC_LA05_N
+set_property  -dict {PACKAGE_PIN  A10 } [get_ports rx_ref_clk_p]                                        ; ## D04  FMC1_HPC_GBTCLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  A9  } [get_ports rx_ref_clk_n]                                        ; ## D05  FMC1_HPC_GBTCLK0_M2C_N
+set_property  -dict {PACKAGE_PIN  D8  } [get_ports rx_data_p[0]]                                        ; ## C06  FMC1_HPC_DP0_M2C_P
+set_property  -dict {PACKAGE_PIN  D7  } [get_ports rx_data_n[0]]                                        ; ## C07  FMC1_HPC_DP0_M2C_N
+set_property  -dict {PACKAGE_PIN  C6  } [get_ports rx_data_p[1]]                                        ; ## A02  FMC1_HPC_DP1_M2C_P
+set_property  -dict {PACKAGE_PIN  C5  } [get_ports rx_data_n[1]]                                        ; ## A03  FMC1_HPC_DP1_M2C_N
+set_property  -dict {PACKAGE_PIN  B8  } [get_ports rx_data_p[2]]                                        ; ## A06  FMC1_HPC_DP2_M2C_P
+set_property  -dict {PACKAGE_PIN  B7  } [get_ports rx_data_n[2]]                                        ; ## A07  FMC1_HPC_DP2_M2C_N
+set_property  -dict {PACKAGE_PIN  A6  } [get_ports rx_data_p[3]]                                        ; ## A10  FMC1_HPC_DP3_M2C_P
+set_property  -dict {PACKAGE_PIN  A5  } [get_ports rx_data_n[3]]                                        ; ## A11  FMC1_HPC_DP3_M2C_N
+set_property  -dict {PACKAGE_PIN  E6  } [get_ports rx_data_p[4]]                                        ; ## B12  FMC1_HPC_DP7_M2C_P
+set_property  -dict {PACKAGE_PIN  E5  } [get_ports rx_data_n[4]]                                        ; ## B13  FMC1_HPC_DP7_M2C_N
+set_property  -dict {PACKAGE_PIN  H8  } [get_ports rx_data_p[5]]                                        ; ## A14  FMC1_HPC_DP4_M2C_P
+set_property  -dict {PACKAGE_PIN  H7  } [get_ports rx_data_n[5]]                                        ; ## A15  FMC1_HPC_DP4_M2C_N
+set_property  -dict {PACKAGE_PIN  F8  } [get_ports rx_data_p[6]]                                        ; ## B16  FMC1_HPC_DP6_M2C_P
+set_property  -dict {PACKAGE_PIN  F7  } [get_ports rx_data_n[6]]                                        ; ## B17  FMC1_HPC_DP6_M2C_N
+set_property  -dict {PACKAGE_PIN  G6  } [get_ports rx_data_p[7]]                                        ; ## A18  FMC1_HPC_DP5_M2C_P
+set_property  -dict {PACKAGE_PIN  G5  } [get_ports rx_data_n[7]]                                        ; ## A19  FMC1_HPC_DP5_M2C_N
+set_property  -dict {PACKAGE_PIN  H40   IOSTANDARD LVDS} [get_ports rx_sync_p]                          ; ## H10  FMC1_HPC_LA04_P
+set_property  -dict {PACKAGE_PIN  H41   IOSTANDARD LVDS} [get_ports rx_sync_n]                          ; ## H11  FMC1_HPC_LA04_N
+set_property  -dict {PACKAGE_PIN  M41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p]         ; ## D11  FMC1_HPC_LA05_P
+set_property  -dict {PACKAGE_PIN  L41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n]         ; ## D12  FMC1_HPC_LA05_N
 
-set_property  -dict {PACKAGE_PIN  N41  IOSTANDARD LVCMOS18} [get_ports spi_adc_csn]              ; ## H08  FMC1_HPC_LA02_N
-set_property  -dict {PACKAGE_PIN  J40  IOSTANDARD LVCMOS18} [get_ports spi_adc_clk]              ; ## D08  FMC1_HPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN  J41  IOSTANDARD LVCMOS18} [get_ports spi_adc_sdio]             ; ## D09  FMC1_HPC_LA01_CC_N
-set_property  -dict {PACKAGE_PIN  P41  IOSTANDARD LVCMOS18} [get_ports spi_ext_csn_0]            ; ## H07  FMC1_HPC_LA02_P
-set_property  -dict {PACKAGE_PIN  K42  IOSTANDARD LVCMOS18} [get_ports spi_ext_csn_1]            ; ## C10  FMC1_HPC_LA06_P
-set_property  -dict {PACKAGE_PIN  K39  IOSTANDARD LVCMOS18} [get_ports spi_ext_clk]              ; ## G06  FMC1_HPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN  K40  IOSTANDARD LVCMOS18} [get_ports spi_ext_sdio]             ; ## G07  FMC1_HPC_LA00_CC_N
+set_property  -dict {PACKAGE_PIN  N41  IOSTANDARD LVCMOS18} [get_ports spi_adc_csn]                     ; ## H08  FMC1_HPC_LA02_N
+set_property  -dict {PACKAGE_PIN  J40  IOSTANDARD LVCMOS18} [get_ports spi_adc_clk]                     ; ## D08  FMC1_HPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  J41  IOSTANDARD LVCMOS18} [get_ports spi_adc_sdio]                    ; ## D09  FMC1_HPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  P41  IOSTANDARD LVCMOS18} [get_ports spi_adf4355_data_or_csn_0]       ; ## H07  FMC1_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  K42  IOSTANDARD LVCMOS18} [get_ports spi_adf4355_clk_or_csn_1]        ; ## C10  FMC1_HPC_LA06_P
+set_property  -dict {PACKAGE_PIN  K39  IOSTANDARD LVCMOS18} [get_ports spi_adf4355_le_or_clk]           ; ## G06  FMC1_HPC_LA00_CC_P
+set_property  -dict {PACKAGE_PIN  K40  IOSTANDARD LVCMOS18} [get_ports spi_adf4355_ce_or_sdio]          ; ## G07  FMC1_HPC_LA00_CC_N
 
-set_property  -dict {PACKAGE_PIN  M42  IOSTANDARD LVCMOS18} [get_ports adc_irq]                  ; ## G09  FMC1_HPC_LA03_P
-set_property  -dict {PACKAGE_PIN  L42  IOSTANDARD LVCMOS18} [get_ports adc_fd]                   ; ## G10  FMC1_HPC_LA03_N
+set_property  -dict {PACKAGE_PIN  M42  IOSTANDARD LVCMOS18} [get_ports adc_irq]                         ; ## G09  FMC1_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  L42  IOSTANDARD LVCMOS18} [get_ports adc_fd]                          ; ## G10  FMC1_HPC_LA03_N
 
 # clocks
 
diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v
index 1ce119e2a..b87f6073e 100644
--- a/projects/fmcadc2/vc707/system_top.v
+++ b/projects/fmcadc2/vc707/system_top.v
@@ -104,10 +104,11 @@ module system_top (
   spi_adc_csn,
   spi_adc_clk,
   spi_adc_sdio,
-  spi_ext_csn_0,
-  spi_ext_csn_1,
-  spi_ext_clk,
-  spi_ext_sdio);
+
+  spi_adf4355_data_or_csn_0,
+  spi_adf4355_clk_or_csn_1,
+  spi_adf4355_le_or_clk,
+  spi_adf4355_ce_or_sdio);
 
   input             sys_rst;
   input             sys_clk_p;
@@ -174,10 +175,11 @@ module system_top (
   output            spi_adc_csn;
   output            spi_adc_clk;
   inout             spi_adc_sdio;
-  output            spi_ext_csn_0;
-  output            spi_ext_csn_1;
-  output            spi_ext_clk;
-  inout             spi_ext_sdio;
+
+  output            spi_adf4355_data_or_csn_0;
+  output            spi_adf4355_clk_or_csn_1;
+  output            spi_adf4355_le_or_clk;
+  inout             spi_adf4355_ce_or_sdio;
 
   // internal signals
 
@@ -191,14 +193,6 @@ module system_top (
   wire              rx_sysref;
   wire              rx_sync;
 
-  // spi
-
-  assign spi_adc_csn = spi_csn[0];
-  assign spi_adc_clk = spi_clk;
-  assign spi_ext_csn_0 = spi_csn[1];
-  assign spi_ext_csn_1 = spi_csn[2];
-  assign spi_ext_clk = spi_clk;
-
   // default logic
 
   assign fan_pwm = 1'b1;
@@ -223,22 +217,30 @@ module system_top (
     .O (rx_sync_p),
     .OB (rx_sync_n));
 
+    // spi
+
+    assign gpio_i[37:36] = gpio_o[37:36];
+
   fmcadc2_spi i_fmcadc2_spi (
-    .spi_adc_csn (spi_adc_csn),
-    .spi_ext_csn_0 (spi_ext_csn_0),
-    .spi_ext_csn_1 (spi_ext_csn_1),
+    .spi_adf4355 (gpio_o[36]),
+    .spi_adf4355_ce (gpio_o[37]),
     .spi_clk (spi_clk),
+    .spi_csn (spi_csn),
     .spi_mosi (spi_mosi),
     .spi_miso (spi_miso),
+    .spi_adc_csn (spi_adc_csn),
+    .spi_adc_clk (spi_adc_clk),
     .spi_adc_sdio (spi_adc_sdio),
-    .spi_ext_sdio (spi_ext_sdio));
+    .spi_adf4355_data_or_csn_0 (spi_adf4355_data_or_csn_0),
+    .spi_adf4355_clk_or_csn_1 (spi_adf4355_clk_or_csn_1),
+    .spi_adf4355_le_or_clk (spi_adf4355_le_or_clk),
+    .spi_adf4355_ce_or_sdio (spi_adf4355_ce_or_sdio));
 
   ad_iobuf #(.DATA_WIDTH(2)) i_iobuf (
     .dio_t (gpio_t[33:32]),
     .dio_i (gpio_o[33:32]),
     .dio_o (gpio_i[33:32]),
-    .dio_p ({ adc_irq,    // 33
-              adc_fd}));  // 32
+    .dio_p ({adc_irq, adc_fd}));
 
   ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
     .dio_t (gpio_t[20:0]),

From 230f1526c04133635a7595f15c54e6a66ca232dc Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 1 Sep 2016 10:02:14 -0400
Subject: [PATCH 445/972] avl_adxcfg- compile fixes

---
 library/altera/avl_adxcfg/avl_adxcfg.v      | 112 ++++++++++----------
 library/altera/avl_adxcfg/avl_adxcfg_hw.tcl | 105 +++++++++---------
 2 files changed, 106 insertions(+), 111 deletions(-)

diff --git a/library/altera/avl_adxcfg/avl_adxcfg.v b/library/altera/avl_adxcfg/avl_adxcfg.v
index 3f7c9dfce..081baca43 100644
--- a/library/altera/avl_adxcfg/avl_adxcfg.v
+++ b/library/altera/avl_adxcfg/avl_adxcfg.v
@@ -48,112 +48,112 @@ module avl_adxcfg (
   input           rcfg_in_write_0,
   input   [11:0]  rcfg_in_address_0,
   input   [31:0]  rcfg_in_writedata_0,
-  output  [31:0]  rcfg_in_readata_0,
+  output  [31:0]  rcfg_in_readdata_0,
   output          rcfg_in_waitrequest_0,
 
   output          rcfg_out_read_0,
   output          rcfg_out_write_0,
   output  [11:0]  rcfg_out_address_0,
   output  [31:0]  rcfg_out_writedata_0,
-  input   [31:0]  rcfg_out_readata_0,
+  input   [31:0]  rcfg_out_readdata_0,
   input           rcfg_out_waitrequest_0,
 
   input           rcfg_in_read_1,
   input           rcfg_in_write_1,
   input   [11:0]  rcfg_in_address_1,
   input   [31:0]  rcfg_in_writedata_1,
-  output  [31:0]  rcfg_in_readata_1,
+  output  [31:0]  rcfg_in_readdata_1,
   output          rcfg_in_waitrequest_1,
 
   output          rcfg_out_read_1,
   output          rcfg_out_write_1,
   output  [11:0]  rcfg_out_address_1,
   output  [31:0]  rcfg_out_writedata_1,
-  input   [31:0]  rcfg_out_readata_1,
+  input   [31:0]  rcfg_out_readdata_1,
   input           rcfg_out_waitrequest_1,
 
   input           rcfg_in_read_2,
   input           rcfg_in_write_2,
   input   [11:0]  rcfg_in_address_2,
   input   [31:0]  rcfg_in_writedata_2,
-  output  [31:0]  rcfg_in_readata_2,
+  output  [31:0]  rcfg_in_readdata_2,
   output          rcfg_in_waitrequest_2,
 
   output          rcfg_out_read_2,
   output          rcfg_out_write_2,
   output  [11:0]  rcfg_out_address_2,
   output  [31:0]  rcfg_out_writedata_2,
-  input   [31:0]  rcfg_out_readata_2,
+  input   [31:0]  rcfg_out_readdata_2,
   input           rcfg_out_waitrequest_2,
 
   input           rcfg_in_read_3,
   input           rcfg_in_write_3,
   input   [11:0]  rcfg_in_address_3,
   input   [31:0]  rcfg_in_writedata_3,
-  output  [31:0]  rcfg_in_readata_3,
+  output  [31:0]  rcfg_in_readdata_3,
   output          rcfg_in_waitrequest_3,
 
   output          rcfg_out_read_3,
   output          rcfg_out_write_3,
   output  [11:0]  rcfg_out_address_3,
   output  [31:0]  rcfg_out_writedata_3,
-  input   [31:0]  rcfg_out_readata_3,
+  input   [31:0]  rcfg_out_readdata_3,
   input           rcfg_out_waitrequest_3,
 
   input           rcfg_in_read_4,
   input           rcfg_in_write_4,
   input   [11:0]  rcfg_in_address_4,
   input   [31:0]  rcfg_in_writedata_4,
-  output  [31:0]  rcfg_in_readata_4,
+  output  [31:0]  rcfg_in_readdata_4,
   output          rcfg_in_waitrequest_4,
 
   output          rcfg_out_read_4,
   output          rcfg_out_write_4,
   output  [11:0]  rcfg_out_address_4,
   output  [31:0]  rcfg_out_writedata_4,
-  input   [31:0]  rcfg_out_readata_4,
+  input   [31:0]  rcfg_out_readdata_4,
   input           rcfg_out_waitrequest_4,
 
   input           rcfg_in_read_5,
   input           rcfg_in_write_5,
   input   [11:0]  rcfg_in_address_5,
   input   [31:0]  rcfg_in_writedata_5,
-  output  [31:0]  rcfg_in_readata_5,
+  output  [31:0]  rcfg_in_readdata_5,
   output          rcfg_in_waitrequest_5,
 
   output          rcfg_out_read_5,
   output          rcfg_out_write_5,
   output  [11:0]  rcfg_out_address_5,
   output  [31:0]  rcfg_out_writedata_5,
-  input   [31:0]  rcfg_out_readata_5,
+  input   [31:0]  rcfg_out_readdata_5,
   input           rcfg_out_waitrequest_5,
 
   input           rcfg_in_read_6,
   input           rcfg_in_write_6,
   input   [11:0]  rcfg_in_address_6,
   input   [31:0]  rcfg_in_writedata_6,
-  output  [31:0]  rcfg_in_readata_6,
+  output  [31:0]  rcfg_in_readdata_6,
   output          rcfg_in_waitrequest_6,
 
   output          rcfg_out_read_6,
   output          rcfg_out_write_6,
   output  [11:0]  rcfg_out_address_6,
   output  [31:0]  rcfg_out_writedata_6,
-  input   [31:0]  rcfg_out_readata_6,
+  input   [31:0]  rcfg_out_readdata_6,
   input           rcfg_out_waitrequest_6,
 
   input           rcfg_in_read_7,
   input           rcfg_in_write_7,
   input   [11:0]  rcfg_in_address_7,
   input   [31:0]  rcfg_in_writedata_7,
-  output  [31:0]  rcfg_in_readata_7,
+  output  [31:0]  rcfg_in_readdata_7,
   output          rcfg_in_waitrequest_7,
 
   output          rcfg_out_read_7,
   output          rcfg_out_write_7,
   output  [11:0]  rcfg_out_address_7,
   output  [31:0]  rcfg_out_writedata_7,
-  input   [31:0]  rcfg_out_readata_7,
+  input   [31:0]  rcfg_out_readdata_7,
   input           rcfg_out_waitrequest_7);
 
   // internal registers
@@ -162,67 +162,67 @@ module avl_adxcfg (
   reg     [31:0]  rcfg_out_writedata = 'd0;
   reg             rcfg_out_iread_0 = 'd0;
   reg             rcfg_out_iwrite_0 = 'd0;
-  reg     [31:0]  rcfg_in_ireadata_0 = 'd0;
+  reg     [31:0]  rcfg_in_ireaddata_0 = 'd0;
   reg             rcfg_in_iwaitrequest_0 = 'd0;
   reg             rcfg_out_iread_1 = 'd0;
   reg             rcfg_out_iwrite_1 = 'd0;
-  reg     [31:0]  rcfg_in_ireadata_1 = 'd0;
+  reg     [31:0]  rcfg_in_ireaddata_1 = 'd0;
   reg             rcfg_in_iwaitrequest_1 = 'd0;
   reg             rcfg_out_iread_2 = 'd0;
   reg             rcfg_out_iwrite_2 = 'd0;
-  reg     [31:0]  rcfg_in_ireadata_2 = 'd0;
+  reg     [31:0]  rcfg_in_ireaddata_2 = 'd0;
   reg             rcfg_in_iwaitrequest_2 = 'd0;
   reg             rcfg_out_iread_3 = 'd0;
   reg             rcfg_out_iwrite_3 = 'd0;
-  reg     [31:0]  rcfg_in_ireadata_3 = 'd0;
+  reg     [31:0]  rcfg_in_ireaddata_3 = 'd0;
   reg             rcfg_in_iwaitrequest_3 = 'd0;
   reg             rcfg_out_iread_4 = 'd0;
   reg             rcfg_out_iwrite_4 = 'd0;
-  reg     [31:0]  rcfg_in_ireadata_4 = 'd0;
+  reg     [31:0]  rcfg_in_ireaddata_4 = 'd0;
   reg             rcfg_in_iwaitrequest_4 = 'd0;
   reg             rcfg_out_iread_5 = 'd0;
   reg             rcfg_out_iwrite_5 = 'd0;
-  reg     [31:0]  rcfg_in_ireadata_5 = 'd0;
+  reg     [31:0]  rcfg_in_ireaddata_5 = 'd0;
   reg             rcfg_in_iwaitrequest_5 = 'd0;
   reg             rcfg_out_iread_6 = 'd0;
   reg             rcfg_out_iwrite_6 = 'd0;
-  reg     [31:0]  rcfg_in_ireadata_6 = 'd0;
+  reg     [31:0]  rcfg_in_ireaddata_6 = 'd0;
   reg             rcfg_in_iwaitrequest_6 = 'd0;
   reg             rcfg_out_iread_7 = 'd0;
   reg             rcfg_out_iwrite_7 = 'd0;
-  reg     [31:0]  rcfg_in_ireadata_7 = 'd0;
+  reg     [31:0]  rcfg_in_ireaddata_7 = 'd0;
   reg             rcfg_in_iwaitrequest_7 = 'd0;
   reg     [ 3:0]  rcfg_select = 'd0;
 
   // internal signals
 
-  wire            recfg_in_req_0_s;
-  wire            recfg_in_req_1_s;
-  wire            recfg_in_req_2_s;
-  wire            recfg_in_req_3_s;
-  wire            recfg_in_req_4_s;
-  wire            recfg_in_req_5_s;
-  wire            recfg_in_req_6_s;
-  wire            recfg_in_req_7_s;
+  wire            rcfg_in_req_0_s;
+  wire            rcfg_in_req_1_s;
+  wire            rcfg_in_req_2_s;
+  wire            rcfg_in_req_3_s;
+  wire            rcfg_in_req_4_s;
+  wire            rcfg_in_req_5_s;
+  wire            rcfg_in_req_6_s;
+  wire            rcfg_in_req_7_s;
 
   // xcvr sharing requires same bus with ONLY different write/read signals
 
-  assign rcfg_out_address_0 <= rcfg_out_address;
-  assign rcfg_out_writedata_0 <= rcfg_out_writedata;
-  assign rcfg_out_address_1 <= rcfg_out_address;
-  assign rcfg_out_writedata_1 <= rcfg_out_writedata;
-  assign rcfg_out_address_2 <= rcfg_out_address;
-  assign rcfg_out_writedata_2 <= rcfg_out_writedata;
-  assign rcfg_out_address_3 <= rcfg_out_address;
-  assign rcfg_out_writedata_3 <= rcfg_out_writedata;
-  assign rcfg_out_address_4 <= rcfg_out_address;
-  assign rcfg_out_writedata_4 <= rcfg_out_writedata;
-  assign rcfg_out_address_5 <= rcfg_out_address;
-  assign rcfg_out_writedata_5 <= rcfg_out_writedata;
-  assign rcfg_out_address_6 <= rcfg_out_address;
-  assign rcfg_out_writedata_6 <= rcfg_out_writedata;
-  assign rcfg_out_address_7 <= rcfg_out_address;
-  assign rcfg_out_writedata_7 <= rcfg_out_writedata;
+  assign rcfg_out_address_0 = rcfg_out_address;
+  assign rcfg_out_writedata_0 = rcfg_out_writedata;
+  assign rcfg_out_address_1 = rcfg_out_address;
+  assign rcfg_out_writedata_1 = rcfg_out_writedata;
+  assign rcfg_out_address_2 = rcfg_out_address;
+  assign rcfg_out_writedata_2 = rcfg_out_writedata;
+  assign rcfg_out_address_3 = rcfg_out_address;
+  assign rcfg_out_writedata_3 = rcfg_out_writedata;
+  assign rcfg_out_address_4 = rcfg_out_address;
+  assign rcfg_out_writedata_4 = rcfg_out_writedata;
+  assign rcfg_out_address_5 = rcfg_out_address;
+  assign rcfg_out_writedata_5 = rcfg_out_writedata;
+  assign rcfg_out_address_6 = rcfg_out_address;
+  assign rcfg_out_writedata_6 = rcfg_out_writedata;
+  assign rcfg_out_address_7 = rcfg_out_address;
+  assign rcfg_out_writedata_7 = rcfg_out_writedata;
 
   always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
     if (rcfg_reset_n == 0) begin
@@ -272,35 +272,35 @@ module avl_adxcfg (
 
   assign rcfg_out_read_0 = rcfg_out_iread_0;
   assign rcfg_out_write_0 = rcfg_out_iwrite_0;
-  assign rcfg_in_readata_0 = rcfg_in_ireadata_0;
+  assign rcfg_in_readdata_0 = rcfg_in_ireaddata_0;
   assign rcfg_in_waitrequest_0 = rcfg_in_iwaitrequest_0;
   assign rcfg_out_read_1 = rcfg_out_iread_1;
   assign rcfg_out_write_1 = rcfg_out_iwrite_1;
-  assign rcfg_in_readata_1 = rcfg_in_ireadata_1;
+  assign rcfg_in_readdata_1 = rcfg_in_ireaddata_1;
   assign rcfg_in_waitrequest_1 = rcfg_in_iwaitrequest_1;
   assign rcfg_out_read_2 = rcfg_out_iread_2;
   assign rcfg_out_write_2 = rcfg_out_iwrite_2;
-  assign rcfg_in_readata_2 = rcfg_in_ireadata_2;
+  assign rcfg_in_readdata_2 = rcfg_in_ireaddata_2;
   assign rcfg_in_waitrequest_2 = rcfg_in_iwaitrequest_2;
   assign rcfg_out_read_3 = rcfg_out_iread_3;
   assign rcfg_out_write_3 = rcfg_out_iwrite_3;
-  assign rcfg_in_readata_3 = rcfg_in_ireadata_3;
+  assign rcfg_in_readdata_3 = rcfg_in_ireaddata_3;
   assign rcfg_in_waitrequest_3 = rcfg_in_iwaitrequest_3;
   assign rcfg_out_read_4 = rcfg_out_iread_4;
   assign rcfg_out_write_4 = rcfg_out_iwrite_4;
-  assign rcfg_in_readata_4 = rcfg_in_ireadata_4;
+  assign rcfg_in_readdata_4 = rcfg_in_ireaddata_4;
   assign rcfg_in_waitrequest_4 = rcfg_in_iwaitrequest_4;
   assign rcfg_out_read_5 = rcfg_out_iread_5;
   assign rcfg_out_write_5 = rcfg_out_iwrite_5;
-  assign rcfg_in_readata_5 = rcfg_in_ireadata_5;
+  assign rcfg_in_readdata_5 = rcfg_in_ireaddata_5;
   assign rcfg_in_waitrequest_5 = rcfg_in_iwaitrequest_5;
   assign rcfg_out_read_6 = rcfg_out_iread_6;
   assign rcfg_out_write_6 = rcfg_out_iwrite_6;
-  assign rcfg_in_readata_6 = rcfg_in_ireadata_6;
+  assign rcfg_in_readdata_6 = rcfg_in_ireaddata_6;
   assign rcfg_in_waitrequest_6 = rcfg_in_iwaitrequest_6;
   assign rcfg_out_read_7 = rcfg_out_iread_7;
   assign rcfg_out_write_7 = rcfg_out_iwrite_7;
-  assign rcfg_in_readata_7 = rcfg_in_ireadata_7;
+  assign rcfg_in_readdata_7 = rcfg_in_ireaddata_7;
   assign rcfg_in_waitrequest_7 = rcfg_in_iwaitrequest_7;
 
   always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
diff --git a/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl b/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
index 99c8e97f9..9cc4ce9e0 100644
--- a/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
+++ b/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
@@ -1,77 +1,72 @@
 
 package require -exact qsys 14.0
 
-source ../../scripts/adi_env.tcl
-source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
-
-set_module_property NAME axi_adxcvr
-set_module_property DESCRIPTION "AXI ADXCVR Interface"
+set_module_property NAME avl_adxcfg
+set_module_property DESCRIPTION "Avalon ADXCFG Core"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME axi_adxcvr
+set_module_property DISPLAY_NAME avl_adxcfg
+set_module_property ELABORATION_CALLBACK p_avl_adxcfg
 
 # files
 
 add_fileset quartus_synth QUARTUS_SYNTH "" ""
-set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr
-add_fileset_file up_axi.v                 VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
-add_fileset_file axi_adxcvr_up.v          VERILOG PATH axi_adxcvr_up.v
-add_fileset_file axi_adxcvr.v             VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE
+set_fileset_property quartus_synth TOP_LEVEL avl_adxcfg
+add_fileset_file avl_adxcfg.v VERILOG PATH avl_adxcfg.v TOP_LEVEL_FILE
 
 # parameters
 
-add_parameter ID INTEGER 0
-set_parameter_property ID DISPLAY_NAME ID
-set_parameter_property ID TYPE INTEGER
-set_parameter_property ID UNITS None
-set_parameter_property ID HDL_PARAMETER true
+add_parameter NUM_OF_CORES INTEGER 0
+set_parameter_property NUM_OF_CORES DISPLAY_NAME NUM_OF_CORES
+set_parameter_property NUM_OF_CORES TYPE INTEGER
+set_parameter_property NUM_OF_CORES UNITS None
+set_parameter_property NUM_OF_CORES HDL_PARAMETER false
 
-add_parameter TX_OR_RX_N INTEGER 0
-set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N
-set_parameter_property DEVICE_TYPE TYPE INTEGER
-set_parameter_property DEVICE_TYPE UNITS None
-set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+# reconfiguration interfaces
 
-# axi4 slave interface
+add_interface rcfg_clk  clock sink
+add_interface_port rcfg_clk rcfg_clk clk Input 1
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
+add_interface rcfg_reset_n reset end
+set_interface_property rcfg_reset_n associatedClock rcfg_clk
+add_interface_port rcfg_reset_n rcfg_reset_n reset_n Input 1
 
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
+proc p_avl_adxcfg {} {
 
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+  set m_num_of_cores [get_parameter_value NUM_OF_CORES]
 
-# xcvr interface
+  if {$m_num_of_cores > 8} {
+    set m_num_of_cores 8
+  }
 
-add_interface if_xcvr conduit end
-add_interface_port if_xcvr up_rst             up_rst            Output   1
-add_interface_port if_xcvr up_ref_pll_locked  up_ref_pll_locked Input    1
-add_interface_port if_xcvr up_pll_locked      up_pll_locked     Input    1
-add_interface_port if_xcvr up_ready           up_ready          Input    1
+  for {set n 0} {$n < $m_num_of_cores} {incr n} {
 
-set_interface_property if_xcvr associatedClock s_axi_clock
+    add_interface rcfg_s${n} avalon slave
+    add_interface rcfg_m${n} avalon master
+
+    add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
+    add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
+    add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 12
+    add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
+    add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
+    add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
+    add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
+    add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
+    add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 12
+    add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
+    add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
+    add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
+
+    set_interface_property rcfg_s${n} associatedClock rcfg_clk
+    set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
+    set_interface_property rcfg_s${n} addressUnits WORDS
+    set_interface_property rcfg_s${n} burstCountUnits WORDS
+    set_interface_property rcfg_s${n} explicitAddressSpan 0
+    set_interface_property rcfg_m${n} associatedClock rcfg_clk
+    set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
+    set_interface_property rcfg_m${n} addressUnits WORDS
+    set_interface_property rcfg_m${n} burstCountUnits WORDS
+  }
+}
 
 

From 5544e3cf10810de8ffc1a179aaddc331a8922c2d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 1 Sep 2016 10:05:16 -0400
Subject: [PATCH 446/972] axi_adxcvr- compile fixes

---
 library/altera/axi_adxcvr/axi_adxcvr.v      | 74 ++++++++++-----------
 library/altera/axi_adxcvr/axi_adxcvr_hw.tcl | 44 +++++++++---
 library/altera/axi_adxcvr/axi_adxcvr_up.v   | 56 +++++++++-------
 3 files changed, 102 insertions(+), 72 deletions(-)

diff --git a/library/altera/axi_adxcvr/axi_adxcvr.v b/library/altera/axi_adxcvr/axi_adxcvr.v
index 79e33ba8d..1c81de268 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr.v
@@ -41,50 +41,50 @@ module axi_adxcvr (
 
   // xcvr, lane-pll and ref-pll are shared
 
-  output          up_rst,
-  input           up_ref_pll_locked,
-  input           up_pll_locked,
-  input           up_ready,
+  output                        up_rst,
+  input                         up_ref_pll_locked,
+  input   [(NUM_OF_LANES-1):0]  up_ready,
 
-  input           s_axi_clk,
-  input           s_axi_aresetn,
-  input           s_axi_awvalid,
-  input   [31:0]  s_axi_awaddr,
-  input   [ 2:0]  s_axi_awprot,
-  output          s_axi_awready,
-  input           s_axi_wvalid,
-  input   [31:0]  s_axi_wdata,
-  input   [ 3:0]  s_axi_wstrb,
-  output          s_axi_wready,
-  output          s_axi_bvalid,
-  output  [ 1:0]  s_axi_bresp,
-  input           s_axi_bready,
-  input           s_axi_arvalid,
-  input   [31:0]  s_axi_araddr,
-  input   [ 2:0]  s_axi_arprot,
-  output          s_axi_arready,
-  output          s_axi_rvalid,
-  output  [ 1:0]  s_axi_rresp,
-  output  [31:0]  s_axi_rdata,
-  input           s_axi_rready);
+  input                         s_axi_clk,
+  input                         s_axi_aresetn,
+  input                         s_axi_awvalid,
+  input   [31:0]                s_axi_awaddr,
+  input   [ 2:0]                s_axi_awprot,
+  output                        s_axi_awready,
+  input                         s_axi_wvalid,
+  input   [31:0]                s_axi_wdata,
+  input   [ 3:0]                s_axi_wstrb,
+  output                        s_axi_wready,
+  output                        s_axi_bvalid,
+  output  [ 1:0]                s_axi_bresp,
+  input                         s_axi_bready,
+  input                         s_axi_arvalid,
+  input   [31:0]                s_axi_araddr,
+  input   [ 2:0]                s_axi_arprot,
+  output                        s_axi_arready,
+  output                        s_axi_rvalid,
+  output  [ 1:0]                s_axi_rresp,
+  output  [31:0]                s_axi_rdata,
+  input                         s_axi_rready);
 
   // parameters
 
   parameter   integer ID = 0;
   parameter   integer TX_OR_RX_N = 0;
+  parameter   integer NUM_OF_LANES = 4;
 
   // internal signals
 
-  wire            up_rstn;
-  wire            up_clk;
-  wire            up_wreq;
-  wire    [ 9:0]  up_waddr;
-  wire    [31:0]  up_wdata;
-  wire            up_wack;
-  wire            up_rreq;
-  wire    [ 9:0]  up_raddr;
-  wire    [31:0]  up_rdata;
-  wire            up_rack;
+  wire                          up_rstn;
+  wire                          up_clk;
+  wire                          up_wreq;
+  wire    [ 9:0]                up_waddr;
+  wire    [31:0]                up_wdata;
+  wire                          up_wack;
+  wire                          up_rreq;
+  wire    [ 9:0]                up_raddr;
+  wire    [31:0]                up_rdata;
+  wire                          up_rack;
 
   // clk & rst
 
@@ -95,11 +95,11 @@ module axi_adxcvr (
 
   axi_adxcvr_up #(
     .ID (ID),
-    .TX_OR_RX_N (TX_OR_RX_N))
+    .TX_OR_RX_N (TX_OR_RX_N),
+    .NUM_OF_LANES (NUM_OF_LANES))
   i_up (
     .up_rst (up_rst),
     .up_ref_pll_locked (up_ref_pll_locked),
-    .up_pll_locked (up_pll_locked),
     .up_ready (up_ready),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
index 99c8e97f9..d59eb48b8 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+++ b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
@@ -5,10 +5,11 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
 
 set_module_property NAME axi_adxcvr
-set_module_property DESCRIPTION "AXI ADXCVR Interface"
+set_module_property DESCRIPTION "AXI ADXCVR Core"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
 set_module_property DISPLAY_NAME axi_adxcvr
+set_module_property ELABORATION_CALLBACK p_axi_adxcvr
 
 # files
 
@@ -27,10 +28,16 @@ set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
 add_parameter TX_OR_RX_N INTEGER 0
-set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N
-set_parameter_property DEVICE_TYPE TYPE INTEGER
-set_parameter_property DEVICE_TYPE UNITS None
-set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
+set_parameter_property TX_OR_RX_N TYPE INTEGER
+set_parameter_property TX_OR_RX_N UNITS None
+set_parameter_property TX_OR_RX_N HDL_PARAMETER true
+
+add_parameter NUM_OF_LANES INTEGER 4
+set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
+set_parameter_property NUM_OF_LANES TYPE INTEGER
+set_parameter_property NUM_OF_LANES UNITS None
+set_parameter_property NUM_OF_LANES HDL_PARAMETER true
 
 # axi4 slave interface
 
@@ -66,12 +73,27 @@ add_interface_port s_axi s_axi_rready rready Input 1
 
 # xcvr interface
 
-add_interface if_xcvr conduit end
-add_interface_port if_xcvr up_rst             up_rst            Output   1
-add_interface_port if_xcvr up_ref_pll_locked  up_ref_pll_locked Input    1
-add_interface_port if_xcvr up_pll_locked      up_pll_locked     Input    1
-add_interface_port if_xcvr up_ready           up_ready          Input    1
+ad_alt_intf reset up_rst output 1 s_axi_clock
+set_interface_property if_up_rst associatedResetSinks s_axi_reset
 
-set_interface_property if_xcvr associatedClock s_axi_clock
+add_interface ref_pll_locked conduit end
+add_interface_port ref_pll_locked up_ref_pll_locked export Input 1
 
+# name changes
+
+proc p_axi_adxcvr {} {
+
+  set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
+  set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
+
+  if {$m_tx_or_rx_n == 1} {
+    add_interface ready conduit end
+    add_interface_port ready up_ready tx_ready input $m_num_of_lanes
+  }
+
+  if {$m_tx_or_rx_n == 0} {
+    add_interface ready conduit end
+    add_interface_port ready up_ready rx_ready input $m_num_of_lanes
+  }
+}
 
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v
index 78dd84489..ca5fb1bb6 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v
@@ -41,39 +41,44 @@ module axi_adxcvr_up (
 
   // xcvr, lane-pll and ref-pll are shared
 
-  output          up_rst,
-  input           up_ref_pll_locked,
-  input           up_pll_locked,
-  input           up_ready,
+  output                        up_rst,
+  input                         up_ref_pll_locked,
+  input   [(NUM_OF_LANES-1):0]  up_ready,
 
   // bus interface
 
-  input           up_rstn,
-  input           up_clk,
-  input           up_wreq,
-  input   [ 9:0]  up_waddr,
-  input   [31:0]  up_wdata,
-  output          up_wack,
-  input           up_rreq,
-  input   [ 9:0]  up_raddr,
-  output  [31:0]  up_rdata,
-  output          up_rack);
+  input                         up_rstn,
+  input                         up_clk,
+  input                         up_wreq,
+  input   [ 9:0]                up_waddr,
+  input   [31:0]                up_wdata,
+  output                        up_wack,
+  input                         up_rreq,
+  input   [ 9:0]                up_raddr,
+  output  [31:0]                up_rdata,
+  output                        up_rack);
 
   // parameters
 
   localparam  [31:0]  VERSION = 32'h00100161;
   parameter   integer ID = 0;
   parameter   integer TX_OR_RX_N = 0;
+  parameter   integer NUM_OF_LANES = 4;
 
   // internal registers
 
-  reg             up_wreq_d = 'd0;
-  reg     [31:0]  up_scratch = 'd0;
-  reg             up_resetn = 'd0;
-  reg     [ 3:0]  up_rst_cnt = 'd0;
-  reg             up_status_int = 'd0;
-  reg             up_rreq_d = 'd0;
-  reg     [31:0]  up_rdata_d = 'd0;
+  reg                           up_wreq_d = 'd0;
+  reg     [31:0]                up_scratch = 'd0;
+  reg                           up_resetn = 'd0;
+  reg     [ 3:0]                up_rst_cnt = 'd0;
+  reg                           up_status_int = 'd0;
+  reg                           up_rreq_d = 'd0;
+  reg     [31:0]                up_rdata_d = 'd0;
+
+  // internal signals
+
+  wire                          up_ready_s;
+  wire    [31:0]                up_status_32_s;
 
   // defaults
 
@@ -105,6 +110,10 @@ module axi_adxcvr_up (
 
   assign up_rst = up_rst_cnt[3];
   assign up_status = up_status_int;
+  assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
+  assign up_status_32_s[31:(NUM_OF_LANES+1)] <= 'd0;
+  assign up_status_32_s[NUM_OF_LANES] <= up_ref_pll_locked;
+  assign up_status_32_s[(NUM_OF_LANES-1):0] <= up_ready;
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
@@ -118,8 +127,7 @@ module axi_adxcvr_up (
       end
       if (up_resetn == 1'b0) begin
         up_status_int <= 1'b0;
-      end else if ((up_pll_locked == 1'b1) && (up_ready == 1'b1) &&
-        (up_ref_pll_locked == 1'b1)) begin
+      end else if (up_ready_s == 1'b1) begin
         up_status_int <= 1'b1;
       end
     end
@@ -143,7 +151,7 @@ module axi_adxcvr_up (
           10'h002: up_rdata_d <= up_scratch;
           10'h004: up_rdata_d <= {31'd0, up_resetn};
           10'h005: up_rdata_d <= {31'd0, up_status_int};
-          10'h006: up_rdata_d <= {29'd0, up_pll_locked, up_ref_pll_locked, up_ready};
+          10'h006: up_rdata_d <= up_status_32_s;
           default: up_rdata_d <= 32'd0;
         endcase
       end else begin

From 4ae084ee32f4810705201d9c31fa7dcc65cdceb7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 1 Sep 2016 10:05:49 -0400
Subject: [PATCH 447/972] avl_adxcvr- compile fixes

---
 library/altera/avl_adxcvr/avl_adxcvr_hw.tcl | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
index fd0da3439..d72209030 100755
--- a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
@@ -2,7 +2,7 @@
 package require -exact qsys 14.0
 
 set_module_property NAME avl_adxcvr
-set_module_property DESCRIPTION "Avalon Transceiver"
+set_module_property DESCRIPTION "Avalon ADXCVR Core"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
 set_module_property DISPLAY_NAME avl_adxcvr
@@ -120,7 +120,7 @@ proc p_avl_adxcvr {} {
   set_interface_property sys_resetn EXPORT_OF alt_sys_clk.clk_in_reset
 
   add_instance alt_ref_clk altera_clock_bridge 16.0
-  set_instance_parameter_value alt_ref_clk {EXPLICIT_CLOCK_RATE} $m_refclk_frequency
+  set_instance_parameter_value alt_ref_clk {EXPLICIT_CLOCK_RATE} [expr $m_refclk_frequency*1000000]
   add_interface ref_clk clock sink
   set_interface_property ref_clk EXPORT_OF alt_ref_clk.in_clk
 
@@ -225,8 +225,6 @@ proc p_avl_adxcvr {} {
     set_interface_property sync EXPORT_OF alt_xcvr.sync_n
     add_interface tx_data conduit end
     set_interface_property tx_data EXPORT_OF alt_xcvr.tx_serial_data
-    add_interface pll_locked conduit end
-    set_interface_property pll_locked EXPORT_OF alt_xcvr.pll_locked
     for {set n 0} {$n < $m_num_of_lanes} {incr n} {
       add_connection alt_lane_pll.tx_serial_clk alt_xcvr.tx_serial_clk0_ch${n}
     }

From bbcf2a3ec3ed943144b828fcde3f3d8dcecad528 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Thu, 1 Sep 2016 16:48:37 +0300
Subject: [PATCH 448/972] axi_ad9434/axi_ad9434_constr: Change constraint file
 to resolve critical warning

---
 library/axi_ad9434/axi_ad9434_constr.xdc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/axi_ad9434/axi_ad9434_constr.xdc b/library/axi_ad9434/axi_ad9434_constr.xdc
index 3d94bab25..eb8b7d9e3 100644
--- a/library/axi_ad9434/axi_ad9434_constr.xdc
+++ b/library/axi_ad9434/axi_ad9434_constr.xdc
@@ -1,2 +1,2 @@
-set_false_path  -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}]
-                -to   [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]
+set_false_path  -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to \
+[get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]

From b837883b98e52d2e4ad61a648a86d7ce6f130793 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Thu, 1 Sep 2016 17:02:03 +0300
Subject: [PATCH 449/972] pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed
 voltage level selection

---
 .../pzsdr1/pzsdr1_cmos_system_constr.xdc      | 62 +++++++++----------
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
index 3f2dddbad..8ee340902 100644
--- a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
+++ b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
@@ -2,40 +2,40 @@
 # constraints
 # ad9361
 
-set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVCMOS18} [get_ports rx_clk_in]                         ; ## IO_L12P_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVCMOS18} [get_ports rx_frame_in]                       ; ## IO_L7P_T1_AD2P_35        
-set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]                     ; ## IO_L13N_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]                     ; ## IO_L13P_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]                     ; ## IO_L14N_T2_AD4N_SRCC_35  
-set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]                     ; ## IO_L14P_T2_AD4P_SRCC_35  
-set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]                     ; ## IO_L15N_T2_DQS_AD12N_35  
-set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]                     ; ## IO_L15P_T2_DQS_AD12P_35  
-set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]                     ; ## IO_L16N_T2_35            
-set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]                     ; ## IO_L16P_T2_35            
-set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]                     ; ## IO_L17N_T2_AD5N_35       
-set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]                     ; ## IO_L17P_T2_AD5P_35       
-set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]                    ; ## IO_L18N_T2_AD13N_35      
-set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]                    ; ## IO_L18P_T2_AD13P_35      
+set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVCMOS25} [get_ports rx_clk_in]                         ; ## IO_L12P_T1_MRCC_35
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVCMOS25} [get_ports rx_frame_in]                       ; ## IO_L7P_T1_AD2P_35
+set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVCMOS25} [get_ports rx_data_in[0]]                     ; ## IO_L13N_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS25} [get_ports rx_data_in[1]]                     ; ## IO_L13P_T2_MRCC_35
+set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[2]]                     ; ## IO_L14N_T2_AD4N_SRCC_35
+set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[3]]                     ; ## IO_L14P_T2_AD4P_SRCC_35
+set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[4]]                     ; ## IO_L15N_T2_DQS_AD12N_35
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVCMOS25} [get_ports rx_data_in[5]]                     ; ## IO_L15P_T2_DQS_AD12P_35
+set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[6]]                     ; ## IO_L16N_T2_35
+set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVCMOS25} [get_ports rx_data_in[7]]                     ; ## IO_L16P_T2_35
+set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[8]]                     ; ## IO_L17N_T2_AD5N_35
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[9]]                     ; ## IO_L17P_T2_AD5P_35
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[10]]                    ; ## IO_L18N_T2_AD13N_35
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVCMOS25} [get_ports rx_data_in[11]]                    ; ## IO_L18P_T2_AD13P_35
 
-set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]                        ; ## IO_L8P_T1_AD10P_35       
-set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]                      ; ## IO_L9P_T1_DQS_AD3P_35    
-set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]                    ; ## IO_L1N_T0_AD0N_35        
-set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]                    ; ## IO_L1P_T0_AD0P_35        
-set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]                    ; ## IO_L2N_T0_AD8N_35        
-set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]                    ; ## IO_L2P_T0_AD8P_35        
-set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]                    ; ## IO_L3N_T0_DQS_AD1N_35    
-set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]                    ; ## IO_L3P_T0_DQS_AD1P_35    
-set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]                    ; ## IO_L4N_T0_35             
-set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]                    ; ## IO_L4P_T0_35             
-set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]                    ; ## IO_L5N_T0_AD9N_35        
-set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]                    ; ## IO_L5P_T0_AD9P_35        
-set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]                   ; ## IO_L6N_T0_VREF_35        
-set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]                   ; ## IO_L6P_T0_35             
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVCMOS25} [get_ports tx_clk_out]                        ; ## IO_L8P_T1_AD10P_35
+set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVCMOS25} [get_ports tx_frame_out]                      ; ## IO_L9P_T1_DQS_AD3P_35
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[0]]                    ; ## IO_L1N_T0_AD0N_35
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[1]]                    ; ## IO_L1P_T0_AD0P_35
+set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[2]]                    ; ## IO_L2N_T0_AD8N_35
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[3]]                    ; ## IO_L2P_T0_AD8P_35
+set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVCMOS25} [get_ports tx_data_out[4]]                    ; ## IO_L3N_T0_DQS_AD1N_35
+set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVCMOS25} [get_ports tx_data_out[5]]                    ; ## IO_L3P_T0_DQS_AD1P_35
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[6]]                    ; ## IO_L4N_T0_35
+set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[7]]                    ; ## IO_L4P_T0_35
+set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[8]]                    ; ## IO_L5N_T0_AD9N_35
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVCMOS25} [get_ports tx_data_out[9]]                    ; ## IO_L5P_T0_AD9P_35
+set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVCMOS25} [get_ports tx_data_out[10]]                   ; ## IO_L6N_T0_VREF_35
+set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVCMOS25} [get_ports tx_data_out[11]]                   ; ## IO_L6P_T0_35
 
-set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]]                         ; ## IO_L8N_T1_AD10N_35       
-set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]]                         ; ## IO_L9N_T1_DQS_AD3N_35    
+set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVCMOS25} [get_ports tx_gnd[0]]                         ; ## IO_L8N_T1_AD10N_35
+set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVCMOS25} [get_ports tx_gnd[1]]                         ; ## IO_L9N_T1_DQS_AD3N_35
 # clocks
 
-create_clock -name rx_clk       -period  8 [get_ports rx_clk_in_p]
+create_clock -name rx_clk       -period  8 [get_ports rx_clk_in]
 create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
 

From b8c34791d5cfdee481b0263c089a6d2ee21e739b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 5 Sep 2016 11:16:29 +0300
Subject: [PATCH 450/972] version_upgrade: fmcjesdadc1 updated to 2016.2

Xilinx IP core JESD204 is updated to version 7.0
---
 projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
index 098001461..a6cc87cb7 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
@@ -12,7 +12,7 @@ create_bd_port -dir I -from 3 -to 0 rx_data_n
 set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
 set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
 
-set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd]
+set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9250_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd
 

From bae63ae5b1358552e53ec0e24eb5d310de9c7bab Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Sep 2016 11:39:47 +0300
Subject: [PATCH 451/972] version_upgrade: Update the DAQ3 project to 2016.2

---
 projects/daq3/common/daq3_bd.tcl  | 4 ++--
 projects/daq3/zc706/system_bd.tcl | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl
index 2eb48bf37..d8d7dc6be 100644
--- a/projects/daq3/common/daq3_bd.tcl
+++ b/projects/daq3/common/daq3_bd.tcl
@@ -17,7 +17,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n
 
 set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
 
-set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9152_jesd]
+set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9152_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd
 
@@ -41,7 +41,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack
 
 set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
 
-set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
+set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
 
diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl
index fb9baa0b0..8b2be9f57 100644
--- a/projects/daq3/zc706/system_bd.tcl
+++ b/projects/daq3/zc706/system_bd.tcl
@@ -23,14 +23,14 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
 
 source ../common/daq3_bd.tcl
 
-# ila 
+# ila
 
 set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc]
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc
 set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
 set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
 
-set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
+set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
 set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc

From 0d095f5da9da330dcea9435c2bfa3c13ae9cd9fa Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 8 Sep 2016 11:29:14 +0300
Subject: [PATCH 452/972] a10gx: Added system_type variable in common design

---
 projects/common/a10gx/a10gx_system_qsys.tcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl
index 440e1bb68..b19a8d54e 100644
--- a/projects/common/a10gx/a10gx_system_qsys.tcl
+++ b/projects/common/a10gx/a10gx_system_qsys.tcl
@@ -5,6 +5,8 @@ set_module_property NAME {system_bd}
 set_project_property DEVICE_FAMILY {Arria 10}
 set_project_property DEVICE {10AX115S3F45E2SGE3}
 
+set system_type nios
+
 # clock-&-reset
 
 add_instance sys_clk clock_source 16.0

From 40c9fc92c1887ac633f5c13ae64699baa7b62b39 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 8 Sep 2016 11:31:06 +0300
Subject: [PATCH 453/972] a10soc: Switched to tcl flow

---
 .../common/a10soc/a10soc_system_assign.tcl    |   19 +-
 projects/common/a10soc/a10soc_system_bd.qsys  | 1647 -----------------
 projects/common/a10soc/a10soc_system_qsys.tcl | 1284 +++++++++++++
 3 files changed, 1302 insertions(+), 1648 deletions(-)
 delete mode 100644 projects/common/a10soc/a10soc_system_bd.qsys
 create mode 100755 projects/common/a10soc/a10soc_system_qsys.tcl

diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
index 01f67d323..f39acc047 100755
--- a/projects/common/a10soc/a10soc_system_assign.tcl
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -266,8 +266,25 @@ set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
 # set libraries
 
-set ad_lib_folders "../common/;../../common/a10soc/;../../../library/**/*"
+set ad_lib_folders "$ad_hdl_dir/library/**/*;$ad_phdl_dir/library/**/*"
 
 set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
 set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
 
+# generate qsys
+# move this to a project script
+
+set mmu_enabled 1
+if [info exists ::env(ALT_NIOS_MMU_ENABLED)] {
+  set mmu_enabled $::env(ALT_NIOS_MMU_ENABLED)
+}
+
+if {$mmu_enabled == 0} {
+  set cmd_str "set mmu_enabled 0"
+  exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
+    --cmd=$cmd_str --script=system_qsys.tcl
+} else {
+  set cmd_str "set mmu_enabled 1"
+  exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
+    --cmd=$cmd_str --script=system_qsys.tcl
+}
diff --git a/projects/common/a10soc/a10soc_system_bd.qsys b/projects/common/a10soc/a10soc_system_bd.qsys
deleted file mode 100644
index 75a5ae281..000000000
--- a/projects/common/a10soc/a10soc_system_bd.qsys
+++ /dev/null
@@ -1,1647 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element a10gx_system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element arria10_hps_0
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-   element emif_a10_hps_0
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_cpu_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element sys_cpu_interconnect.s0
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element sys_rst_in
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40I2SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="hps_ddr"
-   internal="emif_a10_hps_0.mem_conduit_end"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_ddr_oct"
-   internal="emif_a10_hps_0.oct_conduit_end"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_ddr_ref_clk"
-   internal="emif_a10_hps_0.pll_ref_clk_clock_sink"
-   type="clock"
-   dir="end" />
- <interface
-   name="hps_gpio"
-   internal="arria10_hps_0.h2f_gp" />
- <interface
-   name="hps_io"
-   internal="arria10_hps_0.hps_io"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_irq0"
-   internal="arria10_hps_0.f2h_irq0"
-   type="interrupt"
-   dir="start" />
- <interface
-   name="hps_irq1"
-   internal="arria10_hps_0.f2h_irq1"
-   type="interrupt"
-   dir="start" />
- <interface name="hps_s0_axi" internal="arria10_hps_0.f2sdram0_data" />
- <interface
-   name="hps_s1_axi"
-   internal="arria10_hps_0.f2sdram1_data"
-   type="axi"
-   dir="end" />
- <interface name="hps_s2_axi" internal="arria10_hps_0.f2sdram2_data" />
- <interface
-   name="hps_spi0"
-   internal="arria10_hps_0.spim0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_spi0_sclk"
-   internal="arria10_hps_0.spim0_sclk_out"
-   type="clock"
-   dir="start" />
- <interface
-   name="hps_spi1"
-   internal="arria10_hps_0.spim1"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_spi1_sclk"
-   internal="arria10_hps_0.spim1_sclk_out"
-   type="clock"
-   dir="start" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface
-   name="sys_cpu_m_avl"
-   internal="sys_cpu_interconnect.m0"
-   type="avalon"
-   dir="start" />
- <interface name="sys_rst" internal="sys_rst.out_reset" type="reset" dir="start" />
- <interface
-   name="sys_rst_in"
-   internal="sys_rst_in.in_reset"
-   type="reset"
-   dir="end" />
- <module
-   name="arria10_hps_0"
-   kind="altera_arria10_hps"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BOOT_FROM_FPGA_Enable" value="false" />
-  <parameter name="BSEL" value="1" />
-  <parameter name="BSEL_EN" value="false" />
-  <parameter name="CLK_EMACA_SOURCE" value="1" />
-  <parameter name="CLK_EMACB_SOURCE" value="1" />
-  <parameter name="CLK_EMAC_PTP_SOURCE" value="1" />
-  <parameter name="CLK_GPIO_SOURCE" value="1" />
-  <parameter name="CLK_HMC_PLL_SOURCE" value="0" />
-  <parameter name="CLK_MAIN_PLL_SOURCE2" value="0" />
-  <parameter name="CLK_MPU_CNT" value="0" />
-  <parameter name="CLK_MPU_SOURCE" value="0" />
-  <parameter name="CLK_NOC_CNT" value="0" />
-  <parameter name="CLK_NOC_SOURCE" value="0" />
-  <parameter name="CLK_PERI_PLL_SOURCE2" value="0" />
-  <parameter name="CLK_S2F_USER0_SOURCE" value="0" />
-  <parameter name="CLK_S2F_USER1_SOURCE" value="0" />
-  <parameter name="CLK_SDMMC_SOURCE" value="1" />
-  <parameter name="CM_Mode" value="N/A" />
-  <parameter name="CM_PinMuxing" value="Unused" />
-  <parameter name="CTI_Enable" value="false" />
-  <parameter name="CUSTOM_MPU_CLK" value="800" />
-  <parameter name="DEBUG_APB_Enable" value="false" />
-  <parameter name="DISABLE_PERI_PLL" value="false" />
-  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
-  <parameter name="EMAC0_CLK" value="250" />
-  <parameter name="EMAC0_Mode" value="RGMII_with_MDIO" />
-  <parameter name="EMAC0_PTP" value="false" />
-  <parameter name="EMAC0_PinMuxing" value="IO" />
-  <parameter name="EMAC0_SWITCH_Enable" value="false" />
-  <parameter name="EMAC1_CLK" value="250" />
-  <parameter name="EMAC1_Mode" value="N/A" />
-  <parameter name="EMAC1_PTP" value="false" />
-  <parameter name="EMAC1_PinMuxing" value="Unused" />
-  <parameter name="EMAC1_SWITCH_Enable" value="false" />
-  <parameter name="EMAC2_CLK" value="250" />
-  <parameter name="EMAC2_Mode" value="N/A" />
-  <parameter name="EMAC2_PTP" value="false" />
-  <parameter name="EMAC2_PinMuxing" value="Unused" />
-  <parameter name="EMAC2_SWITCH_Enable" value="false" />
-  <parameter name="EMAC_PTP_REF_CLK" value="100" />
-  <parameter name="EMIF_CONDUIT_Enable" value="true" />
-  <parameter name="F2H_AXI_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_COLD_RST_Enable" value="true" />
-  <parameter name="F2H_DBG_RST_Enable" value="false" />
-  <parameter name="F2H_FREE_CLK_Enable" value="false" />
-  <parameter name="F2H_FREE_CLK_FREQ" value="200" />
-  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_WARM_RST_Enable" value="false" />
-  <parameter name="F2SDRAM0_ENABLED" value="false" />
-  <parameter name="F2SDRAM1_ENABLED" value="true" />
-  <parameter name="F2SDRAM2_ENABLED" value="false" />
-  <parameter name="F2SDRAM_ADDRESS_WIDTH" value="32" />
-  <parameter name="F2SDRAM_PORT_CONFIG" value="5" />
-  <parameter name="F2SDRAM_READY_LATENCY" value="false" />
-  <parameter name="F2SINTERRUPT_Enable" value="true" />
-  <parameter name="F2S_Width" value="0" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_TX_CLK_IN" value="100" />
-  <parameter
-     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
-     value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC0_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC1_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC2_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDMMC_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="2.5" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="2.5" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK" value="2.5" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
-  <parameter name="GPIO_REF_CLK" value="4" />
-  <parameter name="GP_Enable" value="false" />
-  <parameter name="H2F_AXI_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_COLD_RST_Enable" value="false" />
-  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="100000000" />
-  <parameter name="H2F_PENDING_RST_Enable" value="false" />
-  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
-  <parameter name="H2F_USER0_CLK_Enable" value="false" />
-  <parameter name="H2F_USER0_CLK_FREQ" value="400" />
-  <parameter name="H2F_USER1_CLK_Enable" value="false" />
-  <parameter name="H2F_USER1_CLK_FREQ" value="400" />
-  <parameter name="HMC_PLL_REF_CLK" value="800" />
-  <parameter name="HPS_DIV_GPIO_FREQ" value="125" />
-  <parameter name="HPS_IO_Enable">SDMMC:D0,SDMMC:CMD,SDMMC:CCLK,SDMMC:D1,SDMMC:D2,SDMMC:D3,NONE,NONE,SDMMC:D4,SDMMC:D5,SDMMC:D6,SDMMC:D7,UART1:TX,UART1:RX,USB0:CLK,USB0:STP,USB0:DIR,USB0:DATA0,USB0:DATA1,USB0:NXT,USB0:DATA2,USB0:DATA3,USB0:DATA4,USB0:DATA5,USB0:DATA6,USB0:DATA7,EMAC0:TX_CLK,EMAC0:TX_CTL,EMAC0:RX_CLK,EMAC0:RX_CTL,EMAC0:TXD0,EMAC0:TXD1,EMAC0:RXD0,EMAC0:RXD1,EMAC0:TXD2,EMAC0:TXD3,EMAC0:RXD2,EMAC0:RXD3,NONE,NONE,NONE,NONE,NONE,GPIO,NONE,NONE,NONE,NONE,MDIO0:MDIO,MDIO0:MDC,I2C1:SDA,I2C1:SCL,GPIO,NONE,GPIO,GPIO,NONE,NONE,NONE,NONE,NONE,NONE</parameter>
-  <parameter name="I2C0_Mode" value="N/A" />
-  <parameter name="I2C0_PinMuxing" value="Unused" />
-  <parameter name="I2C1_Mode" value="default" />
-  <parameter name="I2C1_PinMuxing" value="IO" />
-  <parameter name="I2CEMAC0_Mode" value="N/A" />
-  <parameter name="I2CEMAC0_PinMuxing" value="Unused" />
-  <parameter name="I2CEMAC1_Mode" value="N/A" />
-  <parameter name="I2CEMAC1_PinMuxing" value="Unused" />
-  <parameter name="I2CEMAC2_Mode" value="N/A" />
-  <parameter name="I2CEMAC2_PinMuxing" value="Unused" />
-  <parameter name="INTERNAL_OSCILLATOR_ENABLE" value="60" />
-  <parameter name="JTAG_Enable" value="false" />
-  <parameter name="L3_MAIN_FREE_CLK" value="400" />
-  <parameter name="L4_SYS_FREE_CLK" value="1" />
-  <parameter name="LWH2F_Enable" value="1" />
-  <parameter name="MPU_CLK_VCCL" value="0" />
-  <parameter name="MPU_EVENTS_Enable" value="false" />
-  <parameter name="NAND_Mode" value="N/A" />
-  <parameter name="NAND_PinMuxing" value="Unused" />
-  <parameter name="NOCDIV_CS_ATCLK" value="0" />
-  <parameter name="NOCDIV_CS_PDBGCLK" value="1" />
-  <parameter name="NOCDIV_CS_TRACECLK" value="0" />
-  <parameter name="NOCDIV_L4MAINCLK" value="0" />
-  <parameter name="NOCDIV_L4MPCLK" value="1" />
-  <parameter name="NOCDIV_L4SPCLK" value="2" />
-  <parameter name="OVERIDE_PERI_PLL" value="false" />
-  <parameter name="PERI_PLL_MANUAL_VCO_FREQ" value="2000" />
-  <parameter name="PLL_CLK0" value="Unused" />
-  <parameter name="PLL_CLK1" value="Unused" />
-  <parameter name="PLL_CLK2" value="Unused" />
-  <parameter name="PLL_CLK3" value="Unused" />
-  <parameter name="PLL_CLK4" value="Unused" />
-  <parameter name="QSPI_Mode" value="N/A" />
-  <parameter name="QSPI_PinMuxing" value="Unused" />
-  <parameter name="RUN_INTERNAL_BUILD_CHECKS" value="0" />
-  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_EMAC0_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_EMAC1_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_EMAC2_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_HMC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2C0_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2C1_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CEMAC0_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CEMAC1_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CEMAC2_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPIM0_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPIM1_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPIS0_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPIS1_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SYSTEMMANAGER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SYSTIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_UART0_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_UART1_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_USB0_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_USB1_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
-  <parameter name="S2F_Width" value="0" />
-  <parameter name="SDMMC_Mode" value="8-bit" />
-  <parameter name="SDMMC_PinMuxing" value="IO" />
-  <parameter name="SDMMC_REF_CLK" value="200" />
-  <parameter name="SECURITY_MODULE_Enable" value="false" />
-  <parameter name="SPIM0_Mode">Single_slave_selects</parameter>
-  <parameter name="SPIM0_PinMuxing" value="FPGA" />
-  <parameter name="SPIM1_Mode">Single_slave_selects</parameter>
-  <parameter name="SPIM1_PinMuxing" value="FPGA" />
-  <parameter name="SPIS0_Mode" value="N/A" />
-  <parameter name="SPIS0_PinMuxing" value="Unused" />
-  <parameter name="SPIS1_Mode" value="N/A" />
-  <parameter name="SPIS1_PinMuxing" value="Unused" />
-  <parameter name="STM_Enable" value="false" />
-  <parameter name="TESTIOCTRL_DEBUGCLKSEL" value="16" />
-  <parameter name="TESTIOCTRL_MAINCLKSEL" value="8" />
-  <parameter name="TESTIOCTRL_PERICLKSEL" value="8" />
-  <parameter name="TEST_Enable" value="false" />
-  <parameter name="TRACE_Mode" value="N/A" />
-  <parameter name="TRACE_PinMuxing" value="Unused" />
-  <parameter name="UART0_Mode" value="N/A" />
-  <parameter name="UART0_PinMuxing" value="Unused" />
-  <parameter name="UART1_Mode" value="No_flow_control" />
-  <parameter name="UART1_PinMuxing" value="IO" />
-  <parameter name="USB0_Mode" value="default" />
-  <parameter name="USB0_PinMuxing" value="IO" />
-  <parameter name="USB1_Mode" value="N/A" />
-  <parameter name="USB1_PinMuxing" value="Unused" />
-  <parameter name="USE_DEFAULT_MPU_CLK" value="false" />
-  <parameter name="device_name" value="10AS066N3F40I2SGES" />
-  <parameter name="eosc1_clk_mhz" value="25.0" />
-  <parameter name="quartus_ini_hps_ip_boot_from_fpga_ready" value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_a10_advanced_options" value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_emac_switch" value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_jtag" value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_sdmmc_clk_in" value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
-  <parameter name="quartus_ini_hps_ip_override_sdmmc_4bit" value="false" />
- </module>
- <module
-   name="emif_a10_hps_0"
-   kind="altera_emif_a10_hps"
-   version="15.1"
-   enabled="1">
-  <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
-  <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="5.0" />
-  <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
-  <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
-  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
-  <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="8.0" />
-  <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
-  <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
-  <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
-  <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
-  <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="5.0" />
-  <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="2.5" />
-  <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
-  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
-  <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="7.0" />
-  <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
-  <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
-  <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
-  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
-  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
-  <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
-  <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
-  <parameter name="CTRL_DDR3_ECC_EN" value="false" />
-  <parameter name="CTRL_DDR3_MMR_EN" value="false" />
-  <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
-  <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
-  <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
-  <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
-  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
-  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
-  <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
-  <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
-  <parameter name="CTRL_DDR4_ECC_EN" value="false" />
-  <parameter name="CTRL_DDR4_MMR_EN" value="false" />
-  <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
-  <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
-  <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
-  <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
-  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
-  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
-  <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
-  <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
-  <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
-  <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
-  <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
-  <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
-  <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
-  <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
-  <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
-  <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
-  <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
-  <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
-  <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
-  <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
-  <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
-  <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
-  <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
-  <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
-  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
-  <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
-  <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
-  <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
-  <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
-  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
-  <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="true" />
-  <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="false" />
-  <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
-  <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
-  <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
-  <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
-  <parameter name="DIAG_EXPORT_VJI" value="false" />
-  <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
-  <parameter name="DIAG_EXTRA_CONFIGS" value="" />
-  <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
-  <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
-  <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
-  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
-  <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
-  <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="false" />
-  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
-  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
-  <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="false" />
-  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
-  <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
-  <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
-  <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="false" />
-  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
-  <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
-  <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
-  <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
-  <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
-  <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
-  <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
-  <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
-  <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
-  <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
-  <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="DIAG_USE_RS232_UART" value="false" />
-  <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
-  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter
-     name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
-     value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
-  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
-  <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
-  <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
-  <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
-  <parameter name="INTERNAL_TESTING_MODE" value="false" />
-  <parameter name="IS_ED_SLAVE" value="false" />
-  <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
-  <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
-  <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
-  <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
-  <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
-  <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
-  <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
-  <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
-  <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
-  <parameter name="MEM_DDR3_DLL_EN" value="true" />
-  <parameter name="MEM_DDR3_DM_EN" value="true" />
-  <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DDR3_DQ_WIDTH" value="32" />
-  <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
-  <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
-  <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="000000000000000000" />
-  <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
-  <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
-  <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
-  <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
-  <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
-  <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
-  <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
-  <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
-  <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
-  <parameter name="MEM_DDR3_TCL" value="14" />
-  <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
-  <parameter name="MEM_DDR3_TDH_PS" value="55" />
-  <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
-  <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
-  <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
-  <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
-  <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
-  <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
-  <parameter name="MEM_DDR3_TDS_PS" value="53" />
-  <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
-  <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
-  <parameter name="MEM_DDR3_TIH_PS" value="95" />
-  <parameter name="MEM_DDR3_TINIT_US" value="500" />
-  <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
-  <parameter name="MEM_DDR3_TIS_PS" value="60" />
-  <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
-  <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
-  <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
-  <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
-  <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
-  <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
-  <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
-  <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
-  <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
-  <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
-  <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
-  <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
-  <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
-  <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
-  <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_DDR3_WTCL" value="10" />
-  <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
-  <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
-  <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
-  <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
-  <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
-  <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="3" />
-  <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
-  <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
-  <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
-  <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
-  <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
-  <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="1" />
-  <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
-  <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
-  <parameter name="MEM_DDR4_CAL_MODE" value="0" />
-  <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
-  <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR4_CK_WIDTH" value="1" />
-  <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="true" />
-  <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
-  <parameter name="MEM_DDR4_DLL_EN" value="true" />
-  <parameter name="MEM_DDR4_DM_EN" value="true" />
-  <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DDR4_DQ_WIDTH" value="32" />
-  <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
-  <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
-  <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
-  <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
-  <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
-  <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG" value="0000000000000000" />
-  <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
-  <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
-  <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
-  <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
-  <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
-  <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
-  <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
-  <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR4_RDIMM_CONFIG">00000000000000000000000000000000000000</parameter>
-  <parameter name="MEM_DDR4_READ_DBI" value="true" />
-  <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
-  <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
-  <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_6" />
-  <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
-  <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,off" />
-  <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR4_R_ODT1_2X2" value="off,off" />
-  <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
-  <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2666" />
-  <parameter name="MEM_DDR4_TCCD_L_CYC" value="6" />
-  <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
-  <parameter name="MEM_DDR4_TCL" value="20" />
-  <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
-  <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
-  <parameter name="MEM_DDR4_TDQSCK_PS" value="165" />
-  <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
-  <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
-  <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
-  <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
-  <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
-  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
-  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
-  <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
-  <parameter name="MEM_DDR4_TFAW_NS" value="30.0" />
-  <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
-  <parameter name="MEM_DDR4_TIH_PS" value="95" />
-  <parameter name="MEM_DDR4_TINIT_US" value="500" />
-  <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
-  <parameter name="MEM_DDR4_TIS_PS" value="60" />
-  <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
-  <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
-  <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
-  <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
-  <parameter name="MEM_DDR4_TRAS_NS" value="32.0" />
-  <parameter name="MEM_DDR4_TRCD_NS" value="14.25" />
-  <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
-  <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
-  <parameter name="MEM_DDR4_TRP_NS" value="14.25" />
-  <parameter name="MEM_DDR4_TRRD_L_CYC" value="8" />
-  <parameter name="MEM_DDR4_TRRD_S_CYC" value="7" />
-  <parameter name="MEM_DDR4_TWLH_PS" value="108.0" />
-  <parameter name="MEM_DDR4_TWLS_PS" value="108.0" />
-  <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
-  <parameter name="MEM_DDR4_TWTR_L_CYC" value="10" />
-  <parameter name="MEM_DDR4_TWTR_S_CYC" value="4" />
-  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
-  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="56.0" />
-  <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
-  <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
-  <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
-  <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
-  <parameter name="MEM_DDR4_WTCL" value="18" />
-  <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
-  <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
-  <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
-  <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
-  <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
-  <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
-  <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
-  <parameter name="MEM_LPDDR3_DM_EN" value="true" />
-  <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
-  <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
-  <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
-  <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
-  <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
-  <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
-  <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
-  <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
-  <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
-  <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
-  <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
-  <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
-  <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
-  <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
-  <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
-  <parameter name="MEM_LPDDR3_TDQSCK_PS" value="614" />
-  <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
-  <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
-  <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
-  <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
-  <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
-  <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
-  <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
-  <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
-  <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
-  <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
-  <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
-  <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
-  <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
-  <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
-  <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
-  <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
-  <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
-  <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
-  <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
-  <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
-  <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
-  <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
-  <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
-  <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
-  <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
-  <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
-  <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
-  <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
-  <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
-  <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
-  <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
-  <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
-  <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
-  <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
-  <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
-  <parameter name="MEM_QDR2_BL" value="4" />
-  <parameter name="MEM_QDR2_BWS_EN" value="true" />
-  <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
-  <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
-  <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
-  <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
-  <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
-  <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
-  <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
-  <parameter name="MEM_QDR2_THA_NS" value="0.18" />
-  <parameter name="MEM_QDR2_THD_NS" value="0.18" />
-  <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
-  <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
-  <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
-  <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
-  <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
-  <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
-  <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
-  <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
-  <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
-  <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
-  <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
-  <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
-  <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
-  <parameter name="MEM_QDR4_TAH_PS" value="125" />
-  <parameter name="MEM_QDR4_TAS_PS" value="125" />
-  <parameter name="MEM_QDR4_TCH_PS" value="150" />
-  <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
-  <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
-  <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
-  <parameter name="MEM_QDR4_TCS_PS" value="150" />
-  <parameter name="MEM_QDR4_TIH_PS" value="125" />
-  <parameter name="MEM_QDR4_TIS_PS" value="125" />
-  <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
-  <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
-  <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
-  <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
-  <parameter name="MEM_RLD2_BL" value="4" />
-  <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
-  <parameter name="MEM_RLD2_DM_EN" value="true" />
-  <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
-  <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
-  <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
-  <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
-  <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
-  <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
-  <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
-  <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
-  <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
-  <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
-  <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
-  <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
-  <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
-  <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
-  <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
-  <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
-  <parameter name="MEM_RLD3_BL" value="2" />
-  <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
-  <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD3_DM_EN" value="true" />
-  <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
-  <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
-  <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
-  <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
-  <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
-  <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
-  <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
-  <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
-  <parameter name="MEM_RLD3_TDH_PS" value="5" />
-  <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
-  <parameter name="MEM_RLD3_TDS_PS" value="-30" />
-  <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
-  <parameter name="MEM_RLD3_TIH_PS" value="65" />
-  <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
-  <parameter name="MEM_RLD3_TIS_PS" value="85" />
-  <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
-  <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
-  <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
-  <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
-  <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
-  <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
-  <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
-  <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
-  <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
-  <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
-  <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
-  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
-  <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
-  <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
-  <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_DDR4_DEFAULT_IO" value="false" />
-  <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
-  <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
-  <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
-  <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
-  <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="OUT_OCT_40_CAL" />
-  <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
-  <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
-  <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_60_CAL" />
-  <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
-  <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
-  <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_CMOS_12" />
-  <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="133.333" />
-  <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_12" />
-  <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
-  <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
-  <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
-  <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
-  <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
-  <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
-  <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
-  <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
-  <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
-  <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
-  <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
-  <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
-  <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
-  <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
-  <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
-  <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
-  <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
-  <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
-  <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
-  <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
-  <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
-  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
-  <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
-  <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
-  <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
-  <parameter name="SYS_INFO_DEVICE" value="10AS066N3F40I2SGES" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_emif_a10_hps_0</parameter>
-  <parameter name="TRAIT_SUPPORTS_VID" value="0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module
-   name="sys_cpu_interconnect"
-   kind="altera_avalon_mm_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="32" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DATA_WIDTH" value="32" />
-  <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="MAX_PENDING_RESPONSES" value="4" />
-  <parameter name="PIPELINE_COMMAND" value="1" />
-  <parameter name="PIPELINE_RESPONSE" value="1" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
-  <parameter name="USE_RESPONSE" value="0" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module
-   name="sys_rst_in"
-   kind="altera_reset_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="arria10_hps_0.h2f_lw_axi_master"
-   end="sys_cpu_interconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_rst_in.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_cpu_interconnect.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="arria10_hps_0.f2sdram1_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="arria10_hps_0.h2f_lw_axi_clock" />
- <connection
-   kind="conduit"
-   version="15.1"
-   start="emif_a10_hps_0.hps_emif_conduit_end"
-   end="arria10_hps_0.emif">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="arria10_hps_0.h2f_reset"
-   end="sys_rst.in_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst_in.out_reset"
-   end="arria10_hps_0.f2h_cold_reset_req" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst_in.out_reset"
-   end="emif_a10_hps_0.global_reset_reset_sink" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst_in.out_reset"
-   end="sys_rst.in_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst_in.out_reset"
-   end="sys_cpu_interconnect.reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl
new file mode 100755
index 000000000..837a92860
--- /dev/null
+++ b/projects/common/a10soc/a10soc_system_qsys.tcl
@@ -0,0 +1,1284 @@
+package require qsys
+
+set_module_property NAME {system_bd}
+set_project_property DEVICE_FAMILY {Arria 10}
+set_project_property DEVICE {10AS066N3F40E2SGE2}
+
+set system_type a10soc
+
+add_instance sys_clk clock_source 16.0
+add_interface sys_rst reset sink
+set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
+set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
+set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
+set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
+
+# HPS
+add_instance arria10_hps_0 altera_arria10_hps 16.0
+set_instance_parameter_value arria10_hps_0 {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {GP_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {DEBUG_APB_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {STM_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {CTI_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {JTAG_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {TEST_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {BOOT_FROM_FPGA_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {BSEL_EN} {0}
+set_instance_parameter_value arria10_hps_0 {BSEL} {1}
+set_instance_parameter_value arria10_hps_0 {F2S_Width} {0}
+set_instance_parameter_value arria10_hps_0 {S2F_Width} {0}
+set_instance_parameter_value arria10_hps_0 {LWH2F_Enable} {1}
+set_instance_parameter_value arria10_hps_0 {RUN_INTERNAL_BUILD_CHECKS} {0}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {6}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {1}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {0}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM2_ENABLED} {0}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM_READY_LATENCY} {0}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM2_DELAY} {4}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM_ADDRESS_WIDTH} {32}
+set_instance_parameter_value arria10_hps_0 {DMA_Enable} {No No No No No No No No}
+set_instance_parameter_value arria10_hps_0 {SECURITY_MODULE_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {EMAC0_SWITCH_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {EMAC1_SWITCH_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {EMAC2_SWITCH_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {F2SINTERRUPT_Enable} {1}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_CTI_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_DMA_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC0_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC1_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC2_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_GPIO_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_HMC_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC0_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC1_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC2_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2C0_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2C1_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_L4TIMER_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_NAND_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_QSPI_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SYSTIMER_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SDMMC_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIM0_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIM1_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIS0_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIS1_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SYSTEMMANAGER_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_UART0_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_UART1_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_USB0_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_USB1_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_WATCHDOG_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {eosc1_clk_mhz} {25.0}
+set_instance_parameter_value arria10_hps_0 {INTERNAL_OSCILLATOR_ENABLE} {60}
+set_instance_parameter_value arria10_hps_0 {F2H_FREE_CLK_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {F2H_FREE_CLK_FREQ} {200}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK} {2.5}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK} {2.5}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK} {2.5}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {MPU_CLK_VCCL} {0}
+set_instance_parameter_value arria10_hps_0 {USE_DEFAULT_MPU_CLK} {0}
+set_instance_parameter_value arria10_hps_0 {CUSTOM_MPU_CLK} {800}
+set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {1}
+set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {150}
+set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_FREQ} {400}
+set_instance_parameter_value arria10_hps_0 {HMC_PLL_REF_CLK} {800}
+set_instance_parameter_value arria10_hps_0 {EMAC_PTP_REF_CLK} {100}
+set_instance_parameter_value arria10_hps_0 {SDMMC_REF_CLK} {200}
+set_instance_parameter_value arria10_hps_0 {GPIO_REF_CLK} {4}
+set_instance_parameter_value arria10_hps_0 {L3_MAIN_FREE_CLK} {400}
+set_instance_parameter_value arria10_hps_0 {L4_SYS_FREE_CLK} {1}
+set_instance_parameter_value arria10_hps_0 {NOCDIV_L4MAINCLK} {0}
+set_instance_parameter_value arria10_hps_0 {NOCDIV_L4MPCLK} {1}
+set_instance_parameter_value arria10_hps_0 {NOCDIV_L4SPCLK} {2}
+set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_ATCLK} {0}
+set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_PDBGCLK} {1}
+set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_TRACECLK} {0}
+set_instance_parameter_value arria10_hps_0 {HPS_DIV_GPIO_FREQ} {125}
+set_instance_parameter_value arria10_hps_0 {EMAC0_CLK} {250}
+set_instance_parameter_value arria10_hps_0 {EMAC1_CLK} {250}
+set_instance_parameter_value arria10_hps_0 {EMAC2_CLK} {250}
+set_instance_parameter_value arria10_hps_0 {DISABLE_PERI_PLL} {0}
+set_instance_parameter_value arria10_hps_0 {OVERIDE_PERI_PLL} {0}
+set_instance_parameter_value arria10_hps_0 {PERI_PLL_MANUAL_VCO_FREQ} {2000}
+set_instance_parameter_value arria10_hps_0 {CLK_MAIN_PLL_SOURCE2} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_PERI_PLL_SOURCE2} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_MPU_SOURCE} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_MPU_CNT} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_NOC_SOURCE} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_NOC_CNT} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_S2F_USER0_SOURCE} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_S2F_USER1_SOURCE} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_HMC_PLL_SOURCE} {0}
+set_instance_parameter_value arria10_hps_0 {CLK_EMAC_PTP_SOURCE} {1}
+set_instance_parameter_value arria10_hps_0 {CLK_GPIO_SOURCE} {1}
+set_instance_parameter_value arria10_hps_0 {CLK_SDMMC_SOURCE} {1}
+set_instance_parameter_value arria10_hps_0 {CLK_EMACA_SOURCE} {1}
+set_instance_parameter_value arria10_hps_0 {CLK_EMACB_SOURCE} {1}
+set_instance_parameter_value arria10_hps_0 {H2F_PENDING_RST_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {H2F_COLD_RST_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {F2H_DBG_RST_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {F2H_WARM_RST_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {F2H_COLD_RST_Enable} {1}
+set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_MAINCLKSEL} {8}
+set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_PERICLKSEL} {8}
+set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_DEBUGCLKSEL} {16}
+set_instance_parameter_value arria10_hps_0 {EMIF_CONDUIT_Enable} {1}
+set_instance_parameter_value arria10_hps_0 {EMIF_BYPASS_CHECK} {0}
+set_instance_parameter_value arria10_hps_0 {EMAC0_PTP} {0}
+set_instance_parameter_value arria10_hps_0 {EMAC1_PTP} {0}
+set_instance_parameter_value arria10_hps_0 {EMAC2_PTP} {0}
+set_instance_parameter_value arria10_hps_0 {EMAC0_PinMuxing} {IO}
+set_instance_parameter_value arria10_hps_0 {EMAC0_Mode} {RGMII_with_MDIO}
+set_instance_parameter_value arria10_hps_0 {EMAC1_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {EMAC1_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {EMAC2_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {EMAC2_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {NAND_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {NAND_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {QSPI_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {QSPI_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {SDMMC_PinMuxing} {IO}
+set_instance_parameter_value arria10_hps_0 {SDMMC_Mode} {8-bit}
+set_instance_parameter_value arria10_hps_0 {USB0_PinMuxing} {IO}
+set_instance_parameter_value arria10_hps_0 {USB0_Mode} {default}
+set_instance_parameter_value arria10_hps_0 {USB1_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {USB1_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {SPIM0_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {SPIM0_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {SPIM1_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {SPIM1_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {SPIS0_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {SPIS0_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {SPIS1_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {SPIS1_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {UART0_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {UART0_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {UART1_PinMuxing} {IO}
+set_instance_parameter_value arria10_hps_0 {UART1_Mode} {No_flow_control}
+set_instance_parameter_value arria10_hps_0 {I2C0_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {I2C0_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {I2C1_PinMuxing} {IO}
+set_instance_parameter_value arria10_hps_0 {I2C1_Mode} {default}
+set_instance_parameter_value arria10_hps_0 {I2CEMAC0_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {I2CEMAC0_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {I2CEMAC1_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {I2CEMAC1_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {I2CEMAC2_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {I2CEMAC2_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {TRACE_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {TRACE_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {CM_PinMuxing} {Unused}
+set_instance_parameter_value arria10_hps_0 {CM_Mode} {N/A}
+set_instance_parameter_value arria10_hps_0 {PLL_CLK0} {Unused}
+set_instance_parameter_value arria10_hps_0 {PLL_CLK1} {Unused}
+set_instance_parameter_value arria10_hps_0 {PLL_CLK2} {Unused}
+set_instance_parameter_value arria10_hps_0 {PLL_CLK3} {Unused}
+set_instance_parameter_value arria10_hps_0 {PLL_CLK4} {Unused}
+set_instance_parameter_value arria10_hps_0 {HPS_IO_Enable} {SDMMC:D0 SDMMC:CMD SDMMC:CCLK SDMMC:D1 SDMMC:D2 SDMMC:D3 NONE NONE SDMMC:D4 SDMMC:D5 SDMMC:D6 SDMMC:D7 UART1:TX UART1:RX USB0:CLK USB0:STP USB0:DIR USB0:DATA0 USB0:DATA1 USB0:NXT USB0:DATA2 USB0:DATA3 USB0:DATA4 USB0:DATA5 USB0:DATA6 USB0:DATA7 EMAC0:TX_CLK EMAC0:TX_CTL EMAC0:RX_CLK EMAC0:RX_CTL EMAC0:TXD0 EMAC0:TXD1 EMAC0:RXD0 EMAC0:RXD1 EMAC0:TXD2 EMAC0:TXD3 EMAC0:RXD2 EMAC0:RXD3 NONE NONE NONE NONE NONE GPIO NONE NONE NONE NONE MDIO0:MDIO MDIO0:MDC I2C1:SDA I2C1:SCL GPIO NONE GPIO GPIO NONE NONE NONE NONE NONE NONE}
+
+add_instance emif_a10_hps_0 altera_emif_a10_hps 16.0
+set_instance_parameter_value emif_a10_hps_0 {PROTOCOL_ENUM} {PROTOCOL_DDR4}
+set_instance_parameter_value emif_a10_hps_0 {IS_ED_SLAVE} {0}
+set_instance_parameter_value emif_a10_hps_0 {INTERNAL_TESTING_MODE} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_ADD_EXTRA_CLKS} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_USER_NUM_OF_EXTRA_CLKS} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5} {100.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5} {100.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6} {100.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6} {100.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7} {100.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7} {100.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8} {100.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8} {100.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8} {0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PING_PONG_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_MEM_CLK_FREQ_MHZ} {1066.667}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_DEFAULT_REF_CLK_FREQ} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_REF_CLK_FREQ_MHZ} {133.333}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_REF_CLK_JITTER_PS} {10.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_RATE_ENUM} {RATE_HALF}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_IO_VOLTAGE} {1.5}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_DEFAULT_IO} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_HPS_ENABLE_EARLY_RELEASE} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ADDR0} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ADDR1} {8}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ENABLE_NON_DES} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_OUT_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_RZQ_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PING_PONG_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_REF_CLK_JITTER_PS} {10.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_RATE_ENUM} {RATE_HALF}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_IO_VOLTAGE} {1.2}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_DEFAULT_IO} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_STARTING_VREFIN} {70.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_HPS_ENABLE_EARLY_RELEASE} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_12}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_MODE_ENUM} {OUT_OCT_40_CAL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_12}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_MODE_ENUM} {OUT_OCT_40_CAL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_CMOS_12}
+set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PING_PONG_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_MEM_CLK_FREQ_MHZ} {633.333}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_DEFAULT_REF_CLK_FREQ} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_REF_CLK_FREQ_MHZ} {-1.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_REF_CLK_JITTER_PS} {10.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_RATE_ENUM} {RATE_HALF}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_IO_VOLTAGE} {1.5}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_DEFAULT_IO} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_HPS_ENABLE_EARLY_RELEASE} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_OUT_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_IN_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_RZQ_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PING_PONG_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_MEM_CLK_FREQ_MHZ} {1066.667}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_DEFAULT_REF_CLK_FREQ} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_REF_CLK_FREQ_MHZ} {-1.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_REF_CLK_JITTER_PS} {10.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_RATE_ENUM} {RATE_QUARTER}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_IO_VOLTAGE} {1.2}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_DEFAULT_IO} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_STARTING_VREFIN} {70.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_HPS_ENABLE_EARLY_RELEASE} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_OUT_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_IN_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_RZQ_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PING_PONG_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_MEM_CLK_FREQ_MHZ} {533.333}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_DEFAULT_REF_CLK_FREQ} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_REF_CLK_FREQ_MHZ} {-1.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_REF_CLK_JITTER_PS} {10.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_RATE_ENUM} {RATE_HALF}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_IO_VOLTAGE} {1.8}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_DEFAULT_IO} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_HPS_ENABLE_EARLY_RELEASE} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_OUT_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_IN_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_RZQ_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_CONFIG_ENUM} {CONFIG_PHY_ONLY}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PING_PONG_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_MEM_CLK_FREQ_MHZ} {1066.667}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_DEFAULT_REF_CLK_FREQ} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_REF_CLK_FREQ_MHZ} {-1.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_REF_CLK_JITTER_PS} {10.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_RATE_ENUM} {RATE_QUARTER}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_IO_VOLTAGE} {1.2}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_DEFAULT_IO} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_HPS_ENABLE_EARLY_RELEASE} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_OUT_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_IN_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_RZQ_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PING_PONG_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_MEM_CLK_FREQ_MHZ} {800.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_DEFAULT_REF_CLK_FREQ} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ} {-1.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_REF_CLK_JITTER_PS} {10.0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_RATE_ENUM} {RATE_HALF}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_IO_VOLTAGE} {1.2}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_DEFAULT_IO} {1}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE} {0}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_IN_MODE_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_RZQ_IO_STD_ENUM} {unset}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_FORMAT_ENUM} {MEM_FORMAT_UDIMM}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DQ_WIDTH} {32}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DQ_PER_DQS} {8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DISCRETE_CS_WIDTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_NUM_OF_DIMMS} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RANKS_PER_DIMM} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_CKE_PER_DIMM} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_CK_WIDTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ROW_ADDR_WIDTH} {15}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_COL_ADDR_WIDTH} {10}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BANK_ADDR_WIDTH} {3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DM_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_MIRROR_ADDRESSING_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_HIDE_ADV_MR_SETTINGS} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RDIMM_CONFIG} {0000000000000000}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_LRDIMM_EXTENDED_CONFIG} {000000000000000000}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ALERT_N_PLACEMENT_ENUM} {DDR3_ALERT_N_PLACEMENT_AC_LANES}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ALERT_N_DQS_GROUP} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BL_ENUM} {DDR3_BL_BL8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BT_ENUM} {DDR3_BT_SEQUENTIAL}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ASR_ENUM} {DDR3_ASR_MANUAL}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_SRT_ENUM} {DDR3_SRT_NORMAL}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_PD_ENUM} {DDR3_PD_OFF}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DRV_STR_ENUM} {DDR3_DRV_STR_RZQ_7}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DLL_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RTT_NOM_ENUM} {DDR3_RTT_NOM_ODT_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RTT_WR_ENUM} {DDR3_RTT_WR_RZQ_4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_WTCL} {10}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ATCL_ENUM} {DDR3_ATCL_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TCL} {14}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_USE_DEFAULT_ODT} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_1X1} {Rank\ 0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_1X1} {off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_1X1} {Rank\ 0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_1X1} {on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_2X2} {Rank\ 0 Rank\ 1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_2X2} {off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_2X2} {off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_2X2} {Rank\ 0 Rank\ 1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_2X2} {on off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_2X2} {off on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_4X2} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_4X2} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_4X2} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_4X2} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_4X4} {off off off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_4X4} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT2_4X4} {off off off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT3_4X4} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_4X4} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_4X4} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT2_4X4} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT3_4X4} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_SPEEDBIN_ENUM} {DDR3_SPEEDBIN_2133}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIS_PS} {60}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIS_AC_MV} {135}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIH_PS} {95}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIH_DC_MV} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDS_PS} {53}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDS_AC_MV} {135}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDH_PS} {55}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDH_DC_MV} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSQ_PS} {75}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TQH_CYC} {0.38}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSCK_PS} {180}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSS_CYC} {0.27}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TQSH_CYC} {0.4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDSH_CYC} {0.18}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWLS_PS} {125.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWLH_PS} {125.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDSS_CYC} {0.18}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TINIT_US} {500}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TMRD_CK_CYC} {4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRAS_NS} {33.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRCD_NS} {13.09}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRP_NS} {13.09}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TREFI_US} {7.8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRFC_NS} {160.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWR_NS} {15.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWTR_CYC} {8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TFAW_NS} {25.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRRD_CYC} {6}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRTP_CYC} {8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_FORMAT_ENUM} {MEM_FORMAT_UDIMM}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DQ_WIDTH} {32}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DQ_PER_DQS} {8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DISCRETE_CS_WIDTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_NUM_OF_DIMMS} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RANKS_PER_DIMM} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CKE_PER_DIMM} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CK_WIDTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ROW_ADDR_WIDTH} {15}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_COL_ADDR_WIDTH} {10}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BANK_ADDR_WIDTH} {2}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BANK_GROUP_WIDTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CHIP_ID_WIDTH} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DM_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_PAR_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_PLACEMENT_ENUM} {DDR4_ALERT_N_PLACEMENT_DATA_LANES}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_DQS_GROUP} {3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_AC_LANE} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_AC_PIN} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MIRROR_ADDRESSING_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_HIDE_ADV_MR_SETTINGS} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BL_ENUM} {DDR4_BL_BL8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BT_ENUM} {DDR4_BT_SEQUENTIAL}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCL} {20}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_NOM_ENUM} {DDR4_RTT_NOM_RZQ_6}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DLL_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ATCL_ENUM} {DDR4_ATCL_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DRV_STR_ENUM} {DDR4_DRV_STR_RZQ_7}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ASR_ENUM} {DDR4_ASR_MANUAL_NORMAL}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_WR_ENUM} {DDR4_RTT_WR_ODT_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WTCL} {18}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_CRC} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_GEARDOWN} {DDR4_GEARDOWN_HR}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_PER_DRAM_ADDR} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_SENSOR_READOUT} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_FINE_GRANULARITY_REFRESH} {DDR4_FINE_REFRESH_FIXED_1X}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MPR_READ_FORMAT} {DDR4_MPR_READ_FORMAT_SERIAL}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MAX_POWERDOWN} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE} {DDR4_TEMP_CONTROLLED_RFSH_NORMAL}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_INTERNAL_VREFDQ_MONITOR} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CAL_MODE} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SELF_RFSH_ABORT} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_PREAMBLE_TRAINING} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_PREAMBLE} {2}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_PREAMBLE} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_AC_PARITY_LATENCY} {DDR4_AC_PARITY_LATENCY_DISABLE}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ODT_IN_POWERDOWN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_PARK} {DDR4_RTT_PARK_ODT_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_AC_PERSISTENT_ERROR} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_DBI} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_DBI} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DEFAULT_VREFOUT} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USER_VREFDQ_TRAINING_VALUE} {56.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USER_VREFDQ_TRAINING_RANGE} {DDR4_VREFDQ_TRAINING_RANGE_1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CA_IBT_ENUM} {DDR4_RCD_CA_IBT_100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CS_IBT_ENUM} {DDR4_RCD_CS_IBT_100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CKE_IBT_ENUM} {DDR4_RCD_CKE_IBT_100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_ODT_IBT_ENUM} {DDR4_RCD_ODT_IBT_100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_NOM_ENUM} {DDR4_DB_RTT_NOM_ODT_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_WR_ENUM} {DDR4_DB_RTT_WR_RZQ_3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_PARK_ENUM} {DDR4_DB_RTT_PARK_ODT_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_DQ_DRV_ENUM} {DDR4_DB_DRV_STR_RZQ_7}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_137_RCD_CA_DRV} {101}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_138_RCD_CK_DRV} {5}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_140_DRAM_VREFDQ_R0} {29}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_141_DRAM_VREFDQ_R1} {29}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_142_DRAM_VREFDQ_R2} {29}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_143_DRAM_VREFDQ_R3} {29}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_144_DB_VREFDQ} {37}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_145_DB_MDQ_DRV} {21}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_148_DRAM_DRV} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM} {20}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_152_DRAM_RTT_PARK} {39}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_135_RCD_REV} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_139_DB_REV} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_ODT_LESS_BS} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM} {240}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USE_DEFAULT_ODT} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_1X1} {Rank\ 0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_1X1} {off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_1X1} {Rank\ 0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_1X1} {on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_2X2} {Rank\ 0 Rank\ 1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_2X2} {off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_2X2} {off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_2X2} {Rank\ 0 Rank\ 1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_2X2} {on off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_2X2} {off on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_4X2} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_4X2} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_4X2} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_4X2} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_4X4} {off off off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_4X4} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT2_4X4} {off off off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT3_4X4} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_4X4} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_4X4} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT2_4X4} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT3_4X4} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIS_PS} {60}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIS_AC_MV} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIH_PS} {95}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIH_DC_MV} {75}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDIVW_TOTAL_UI} {0.2}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_VDIVW_TOTAL} {136}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSQ_UI} {0.16}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQH_UI} {0.76}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDVWP_UI} {0.72}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSCK_PS} {165}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSS_CYC} {0.27}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQSH_CYC} {0.38}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDSH_CYC} {0.18}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDSS_CYC} {0.18}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWLS_PS} {108.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWLH_PS} {108.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TINIT_US} {500}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TMRD_CK_CYC} {8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRAS_NS} {32.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRCD_NS} {14.25}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRP_NS} {14.25}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TREFI_US} {7.8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRFC_NS} {260.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWR_NS} {15.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWTR_L_CYC} {10}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWTR_S_CYC} {4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TFAW_NS} {30.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRRD_L_CYC} {8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRRD_S_CYC} {7}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCCD_L_CYC} {6}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCCD_S_CYC} {4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDIVW_DJ_CYC} {0.1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSQ_PS} {66}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQH_CYC} {0.38}
+set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_VREFDQ_VALUE} {1D}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_WIDTH_EXPANDED} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_DATA_PER_DEVICE} {36}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_ADDR_WIDTH} {19}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_BWS_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_BL} {4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_SPEEDBIN_ENUM} {QDR2_SPEEDBIN_633}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TRL_CYC} {2.5}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TSA_NS} {0.23}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_THA_NS} {0.18}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TSD_NS} {0.23}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_THD_NS} {0.18}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQD_NS} {0.09}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQDOH_NS} {-0.09}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_INTERNAL_JITTER_NS} {0.08}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQH_NS} {0.71}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCCQO_NS} {0.45}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_WIDTH_EXPANDED} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DQ_PER_PORT_PER_DEVICE} {36}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_ADDR_WIDTH} {21}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_CK_ODT_MODE_ENUM} {QDR4_ODT_25_PCT}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_AC_ODT_MODE_ENUM} {QDR4_ODT_25_PCT}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DATA_ODT_MODE_ENUM} {QDR4_ODT_25_PCT}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM} {QDR4_OUTPUT_DRIVE_25_PCT}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM} {QDR4_OUTPUT_DRIVE_25_PCT}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DATA_INV_ENA} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_ADDR_INV_ENA} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_SPEEDBIN_ENUM} {QDR4_SPEEDBIN_2133}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TISH_PS} {150}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TQKQ_MAX_PS} {75}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TQH_CYC} {0.4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKDK_MAX_PS} {150}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKDK_MIN_PS} {-150}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKQK_MAX_PS} {225}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TASH_PS} {170}
+set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCSH_PS} {170}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_WIDTH_EXPANDED} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DQ_PER_DEVICE} {9}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_ADDR_WIDTH} {21}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_BANK_ADDR_WIDTH} {3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DM_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_BL} {4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_CONFIG_ENUM} {RLD2_CONFIG_TRC_8_TRL_8_TWL_9}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DRIVE_IMPEDENCE_ENUM} {RLD2_DRIVE_IMPEDENCE_INTERNAL_50}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_ODT_MODE_ENUM} {RLD2_ODT_ON}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_SPEEDBIN_ENUM} {RLD2_SPEEDBIN_18}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_REFRESH_INTERVAL_US} {0.24}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKH_CYC} {0.45}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKH_HCYC} {0.9}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TAS_NS} {0.3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TAH_NS} {0.3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TDS_NS} {0.17}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TDH_NS} {0.17}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKQ_MAX_NS} {0.12}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKQ_MIN_NS} {-0.12}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKDK_MAX_NS} {0.3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKDK_MIN_NS} {-0.3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKQK_MAX_NS} {0.2}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_WIDTH_EXPANDED} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DEPTH_EXPANDED} {0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DQ_PER_DEVICE} {36}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_ADDR_WIDTH} {20}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_BANK_ADDR_WIDTH} {4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DM_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_BL} {2}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DATA_LATENCY_MODE_ENUM} {RLD3_DL_RL16_WL17}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_T_RC_MODE_ENUM} {RLD3_TRC_9}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM} {RLD3_OUTPUT_DRIVE_40}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_ODT_MODE_ENUM} {RLD3_ODT_40}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_AREF_PROTOCOL_ENUM} {RLD3_AREF_BAC}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_WRITE_PROTOCOL_ENUM} {RLD3_WRITE_1BANK}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_SPEEDBIN_ENUM} {RLD3_SPEEDBIN_093E}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDS_PS} {-30}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDS_AC_MV} {150}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDH_PS} {5}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDH_DC_MV} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TQKQ_MAX_PS} {75}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TQH_CYC} {0.38}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKDK_MAX_CYC} {0.27}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKDK_MIN_CYC} {-0.27}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKQK_MAX_PS} {135}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIS_PS} {85}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIS_AC_MV} {150}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIH_PS} {65}
+set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIH_DC_MV} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DQ_WIDTH} {32}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DISCRETE_CS_WIDTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_CK_WIDTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DM_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_ROW_ADDR_WIDTH} {15}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_COL_ADDR_WIDTH} {10}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_BANK_ADDR_WIDTH} {3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_BL} {LPDDR3_BL_BL8}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DATA_LATENCY} {LPDDR3_DL_RL12_WL6}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_NWR} {LPDDR3_NWR_NWR10}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DRV_STR} {LPDDR3_DRV_STR_40D_40U}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DQODT} {LPDDR3_DQODT_DISABLE}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_PDODT} {LPDDR3_PDODT_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_USE_DEFAULT_ODT} {1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_1X1} {Rank\ 0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_1X1} {off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_1X1} {Rank\ 0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_1X1} {on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_2X2} {Rank\ 0 Rank\ 1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_2X2} {off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT1_2X2} {off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_2X2} {Rank\ 0 Rank\ 1}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_2X2} {on off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT1_2X2} {off on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_4X4} {off off on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT1_4X4} {off off off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT2_4X4} {on on off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT3_4X4} {off off off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_4X4} {on on on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT1_4X4} {off off off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT2_4X4} {on on on on}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT3_4X4} {off off off off}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_SPEEDBIN_ENUM} {LPDDR3_SPEEDBIN_1600}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIS_PS} {75}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIS_AC_MV} {150}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIH_PS} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIH_DC_MV} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDS_PS} {75}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDS_AC_MV} {150}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDH_PS} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDH_DC_MV} {100}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSQ_PS} {135}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TQH_CYC} {0.38}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSCKDL} {614}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSS_CYC} {1.25}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TQSH_CYC} {0.38}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDSH_CYC} {0.2}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWLS_PS} {175.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWLH_PS} {175.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDSS_CYC} {0.2}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TINIT_US} {500}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TMRR_CK_CYC} {4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TMRW_CK_CYC} {10}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRAS_NS} {42.5}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRCD_NS} {18.75}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRP_NS} {18.75}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TREFI_US} {3.9}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRFC_NS} {210.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWR_NS} {15.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWTR_CYC} {4}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TFAW_NS} {50.0}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRRD_CYC} {2}
+set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRTP_CYC} {4}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USE_DEFAULT_SLEW_RATES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USE_DEFAULT_ISI_VALUES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_CK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_AC_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RCLK_SLEW_RATE} {5.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WCLK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RDATA_SLEW_RATE} {2.5}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WDATA_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_AC_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED} {0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_DQS_TO_CK_SKEW_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS} {0.05}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_SKEW_BETWEEN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_AC_TO_CK_SKEW_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_MAX_CK_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_MAX_DQS_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USE_DEFAULT_SLEW_RATES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USE_DEFAULT_ISI_VALUES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_CK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_AC_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RCLK_SLEW_RATE} {8.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WCLK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RDATA_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WDATA_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_AC_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED} {0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_DQS_TO_CK_SKEW_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS} {0.05}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_SKEW_BETWEEN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_AC_TO_CK_SKEW_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_MAX_CK_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_MAX_DQS_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USE_DEFAULT_SLEW_RATES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USE_DEFAULT_ISI_VALUES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_K_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_AC_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RCLK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RDATA_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WDATA_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_AC_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED} {0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED} {0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_D_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_AC_TO_K_SKEW_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_MAX_K_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USE_DEFAULT_SLEW_RATES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USE_DEFAULT_ISI_VALUES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_CK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_AC_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RCLK_SLEW_RATE} {5.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WCLK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RDATA_SLEW_RATE} {2.5}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WDATA_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_AC_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED} {0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_DK_TO_CK_SKEW_NS} {-0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS} {0.05}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_SKEW_BETWEEN_DK_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_AC_TO_CK_SKEW_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_MAX_CK_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_MAX_DK_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USE_DEFAULT_SLEW_RATES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USE_DEFAULT_ISI_VALUES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_CK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_AC_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RCLK_SLEW_RATE} {7.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WCLK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RDATA_SLEW_RATE} {3.5}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WDATA_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_AC_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED} {0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_DK_TO_CK_SKEW_NS} {-0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS} {0.05}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_SKEW_BETWEEN_DK_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_AC_TO_CK_SKEW_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_MAX_CK_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_MAX_DK_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_CK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_AC_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RCLK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WCLK_SLEW_RATE} {4.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RDATA_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WDATA_SLEW_RATE} {2.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_AC_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WCLK_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WDATA_ISI_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED} {0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED} {1}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_DQS_TO_CK_SKEW_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS} {0.05}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS} {0.02}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_AC_TO_CK_SKEW_NS} {0.0}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_MAX_CK_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_MAX_DQS_DELAY_NS} {0.6}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_SELF_REFRESH_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_POWER_DOWN_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_POWER_DOWN_CYCS} {32}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_USER_REFRESH_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_USER_PRIORITY_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_PRECHARGE_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ADDR_ORDER_ENUM} {DDR3_CTRL_ADDR_ORDER_CS_R_B_C}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ECC_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ECC_AUTO_CORRECTION_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_REORDER_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_STARVE_LIMIT} {10}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_MMR_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_SELF_REFRESH_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_POWER_DOWN_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_POWER_DOWN_CYCS} {32}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_USER_REFRESH_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_USER_PRIORITY_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_PRECHARGE_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ADDR_ORDER_ENUM} {DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ECC_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ECC_AUTO_CORRECTION_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_REORDER_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_STARVE_LIMIT} {10}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_MMR_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_MAX_BURST_COUNT} {4}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_MAX_BURST_COUNT} {4}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD2_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD3_ADDR_ORDER_ENUM} {RLD3_CTRL_ADDR_ORDER_CS_R_B_C}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_SELF_REFRESH_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_POWER_DOWN_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS} {32}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_USER_REFRESH_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_USER_PRIORITY_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_PRECHARGE_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_ADDR_ORDER_ENUM} {LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_REORDER_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_STARVE_LIMIT} {10}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_MMR_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_SIM_REGTEST_MODE} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_TIMING_REGTEST_MODE} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_SYNTH_FOR_SIM} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_FAST_SIM_OVERRIDE} {FAST_SIM_OVERRIDE_DEFAULT}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_VERBOSE_IOAUX} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_ECLIPSE_DEBUG} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_EXPORT_VJI} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_JTAG_UART} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_JTAG_UART_HEX} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_HPS_EMIF_DEBUG} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_SOFT_NIOS_MODE} {SOFT_NIOS_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_SOFT_NIOS_CLOCK_FREQUENCY} {100}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_USE_RS232_UART} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RS232_UART_BAUDRATE} {57600}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_EX_DESIGN_ADD_TEST_EMIFS} {}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_EX_DESIGN_SEPARATE_RESETS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_EXPOSE_DFT_SIGNALS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_EXTRA_CONFIGS} {}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_USE_BOARD_DELAY_MODEL} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_BOARD_DELAY_CONFIG_STR} {}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_TG_AVL_2_NUM_CFG_INTERFACES} {0}
+set_instance_parameter_value emif_a10_hps_0 {SHORT_QSYS_INTERFACE_NAMES} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_ISSP_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_INTERFACE_ID} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_USE_TG_AVL_2} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_ABSTRACT_PHY} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_DEFAULT_PATTERN} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_USER_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_REPEAT_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_STRESS_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_TG_DATA_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_TG_BE_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_SEPARATE_READ_WRITE_ITFS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CA_LEVEL_EN} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ADDR0} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ADDR1} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ENABLE_NON_DES} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_FULL_CAL_ON_RESET} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_ISSP_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_INTERFACE_ID} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_USE_TG_AVL_2} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_ABSTRACT_PHY} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_DEFAULT_PATTERN} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_USER_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_REPEAT_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_STRESS_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_TG_DATA_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_TG_BE_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SEPARATE_READ_WRITE_ITFS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_CA_LEVEL} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_CA_DESKEW} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_VREF_CAL} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ADDR0} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ADDR1} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ENABLE_NON_DES} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_FULL_CAL_ON_RESET} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_ISSP_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_INTERFACE_ID} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_USE_TG_AVL_2} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_ABSTRACT_PHY} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_DEFAULT_PATTERN} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_USER_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_REPEAT_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_STRESS_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_TG_DATA_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_TG_BE_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_SEPARATE_READ_WRITE_ITFS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_ISSP_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_INTERFACE_ID} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_USE_TG_AVL_2} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_ABSTRACT_PHY} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_DEFAULT_PATTERN} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_USER_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_REPEAT_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_STRESS_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_TG_DATA_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_TG_BE_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SEPARATE_READ_WRITE_ITFS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SKIP_VREF_CAL} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_ISSP_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_INTERFACE_ID} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_USE_TG_AVL_2} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_ABSTRACT_PHY} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_DEFAULT_PATTERN} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_USER_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_REPEAT_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_STRESS_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_TG_DATA_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_TG_BE_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_SEPARATE_READ_WRITE_ITFS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_ISSP_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_INTERFACE_ID} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_USE_TG_AVL_2} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_ABSTRACT_PHY} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_DEFAULT_PATTERN} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_USER_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_REPEAT_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_STRESS_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_TG_DATA_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_TG_BE_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_SEPARATE_READ_WRITE_ITFS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_ISSP_EN} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_INTERFACE_ID} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_USE_TG_AVL_2} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_ABSTRACT_PHY} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_USER_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_REPEAT_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_STRESS_STAGE} {1}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_TG_BE_PATTERN_LENGTH} {8}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SKIP_CA_LEVEL} {0}
+set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SKIP_CA_DESKEW} {0}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_GEN_SIM} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_GEN_SYNTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_HDL_FORMAT} {HDL_FORMAT_VERILOG}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_PREV_PRESET} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_GEN_SIM} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_GEN_SYNTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_HDL_FORMAT} {HDL_FORMAT_VERILOG}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_PREV_PRESET} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_GEN_SIM} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_GEN_SYNTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_HDL_FORMAT} {HDL_FORMAT_VERILOG}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_PREV_PRESET} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_GEN_SIM} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_GEN_SYNTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_HDL_FORMAT} {HDL_FORMAT_VERILOG}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_PREV_PRESET} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_GEN_SIM} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_GEN_SYNTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_HDL_FORMAT} {HDL_FORMAT_VERILOG}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_PREV_PRESET} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_GEN_SIM} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_GEN_SYNTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_HDL_FORMAT} {HDL_FORMAT_VERILOG}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_PREV_PRESET} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_GEN_SIM} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_GEN_SYNTH} {1}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_HDL_FORMAT} {HDL_FORMAT_VERILOG}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
+set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_PREV_PRESET} {TARGET_DEV_KIT_NONE}
+
+add_instance sys_spi altera_avalon_spi 16.0
+set_instance_parameter_value sys_spi {clockPhase} {1}
+set_instance_parameter_value sys_spi {clockPolarity} {1}
+set_instance_parameter_value sys_spi {dataWidth} {8}
+set_instance_parameter_value sys_spi {disableAvalonFlowControl} {0}
+set_instance_parameter_value sys_spi {insertDelayBetweenSlaveSelectAndSClk} {0}
+set_instance_parameter_value sys_spi {insertSync} {0}
+set_instance_parameter_value sys_spi {lsbOrderedFirst} {0}
+set_instance_parameter_value sys_spi {masterSPI} {1}
+set_instance_parameter_value sys_spi {numberOfSlaves} {2}
+set_instance_parameter_value sys_spi {syncRegDepth} {2}
+set_instance_parameter_value sys_spi {targetClockRate} {5000000.0}
+set_instance_parameter_value sys_spi {targetSlaveSelectToSClkDelay} {0.0}
+
+add_instance gpio_i altera_avalon_pio 16.0
+set_instance_parameter_value gpio_i {bitClearingEdgeCapReg} {0}
+set_instance_parameter_value gpio_i {bitModifyingOutReg} {0}
+set_instance_parameter_value gpio_i {captureEdge} {0}
+set_instance_parameter_value gpio_i {direction} {Input}
+set_instance_parameter_value gpio_i {edgeType} {RISING}
+set_instance_parameter_value gpio_i {generateIRQ} {0}
+set_instance_parameter_value gpio_i {irqType} {LEVEL}
+set_instance_parameter_value gpio_i {resetValue} {0.0}
+set_instance_parameter_value gpio_i {simDoTestBenchWiring} {0}
+set_instance_parameter_value gpio_i {simDrivenValue} {0.0}
+set_instance_parameter_value gpio_i {width} {32}
+
+add_instance gpio_o altera_avalon_pio 16.0
+set_instance_parameter_value gpio_o {bitClearingEdgeCapReg} {0}
+set_instance_parameter_value gpio_o {bitModifyingOutReg} {1}
+set_instance_parameter_value gpio_o {captureEdge} {0}
+set_instance_parameter_value gpio_o {direction} {Output}
+set_instance_parameter_value gpio_o {edgeType} {RISING}
+set_instance_parameter_value gpio_o {generateIRQ} {0}
+set_instance_parameter_value gpio_o {irqType} {LEVEL}
+set_instance_parameter_value gpio_o {resetValue} {0.0}
+set_instance_parameter_value gpio_o {simDoTestBenchWiring} {0}
+set_instance_parameter_value gpio_o {simDrivenValue} {0.0}
+set_instance_parameter_value gpio_o {width} {32}
+
+# connections and connection parameters
+add_connection sys_clk.clk arria10_hps_0.h2f_lw_axi_clock clock
+add_connection sys_clk.clk sys_spi.clk clock
+add_connection sys_clk.clk gpio_i.clk clock
+add_connection sys_clk.clk gpio_o.clk clock
+
+add_connection arria10_hps_0.h2f_user0_clock arria10_hps_0.f2sdram0_clock clock
+
+add_connection emif_a10_hps_0.hps_emif_conduit_end arria10_hps_0.emif conduit
+
+add_connection sys_clk.clk_reset arria10_hps_0.f2h_cold_reset_req reset
+add_connection sys_clk.clk_reset emif_a10_hps_0.global_reset_reset_sink reset
+add_connection sys_clk.clk_reset sys_spi.reset reset
+add_connection sys_clk.clk_reset gpio_i.reset reset
+add_connection sys_clk.clk_reset gpio_o.reset reset
+
+# exported interfaces
+add_interface hps_ddr conduit end
+set_interface_property hps_ddr EXPORT_OF emif_a10_hps_0.mem_conduit_end
+add_interface hps_ddr_oct conduit end
+set_interface_property hps_ddr_oct EXPORT_OF emif_a10_hps_0.oct_conduit_end
+add_interface hps_ddr_ref_clk clock sink
+set_interface_property hps_ddr_ref_clk EXPORT_OF emif_a10_hps_0.pll_ref_clk_clock_sink
+
+add_interface hps_io conduit end
+set_interface_property hps_io EXPORT_OF arria10_hps_0.hps_io
+add_interface hps_s1_axi altera_axi slave
+
+set_interface_property sys_spi EXPORT_OF sys_spi.external
+set_interface_property gpio_o EXPORT_OF gpio_o.external_connection
+set_interface_property gpio_i EXPORT_OF gpio_i.external_connection
+
+# interrupts
+add_connection arria10_hps_0.f2h_irq0 sys_spi.irq
+set_connection_parameter_value arria10_hps_0.f2h_irq0/sys_spi.irq irqNumber {1}
+
+# cpu connections
+add_connection arria10_hps_0.h2f_lw_axi_master sys_spi.spi_control_port
+add_connection arria10_hps_0.h2f_lw_axi_master gpio_i.s1
+add_connection arria10_hps_0.h2f_lw_axi_master gpio_o.s1
+
+set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/sys_spi.spi_control_port baseAddress {0x00000000}
+set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/gpio_i.s1 baseAddress {0x00000020}
+set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/gpio_o.s1 baseAddress {0x00000040}
+

From 521c41ce32ddde603521bd1b9fab977b9a4e7d02 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 8 Sep 2016 11:44:45 +0300
Subject: [PATCH 454/972] adrv9371x: Updated a10soc project. Common design
 differentiates between nios and a10soc carrier

---
 projects/adrv9371x/a10soc/Makefile           |   10 +-
 projects/adrv9371x/a10soc/system_bd.qsys     |  753 ------
 projects/adrv9371x/a10soc/system_constr.sdc  |   16 +-
 projects/adrv9371x/a10soc/system_qsys.tcl    |    8 +
 projects/adrv9371x/a10soc/system_top.v       |   34 +-
 projects/adrv9371x/common/adrv9371x_bd.qsys  | 2317 ------------------
 projects/adrv9371x/common/adrv9371x_qsys.tcl |  169 +-
 7 files changed, 151 insertions(+), 3156 deletions(-)
 delete mode 100644 projects/adrv9371x/a10soc/system_bd.qsys
 create mode 100644 projects/adrv9371x/a10soc/system_qsys.tcl
 delete mode 100755 projects/adrv9371x/common/adrv9371x_bd.qsys

diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 84ef2b10b..74abe24c5 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -12,12 +12,12 @@ endif
 export ALT_NIOS_MMU_ENABLED := $(MMU)
 
 M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
-M_DEPS += system_bd.qsys
-M_DEPS += ../common/adrv9371x_bd.qsys
+M_DEPS += ../common/adrv9371x_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
+M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
@@ -68,6 +68,10 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
diff --git a/projects/adrv9371x/a10soc/system_bd.qsys b/projects/adrv9371x/a10soc/system_bd.qsys
deleted file mode 100644
index beb1b1e66..000000000
--- a/projects/adrv9371x/a10soc/system_bd.qsys
+++ /dev/null
@@ -1,753 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element a10soc
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element a10soc.hps_s1_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element adrv9371x
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element adrv9371x.avl_ad9371_gpio
-   {
-      datum baseAddress
-      {
-         value = "222208";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_gpio_i
-   {
-      datum baseAddress
-      {
-         value = "222464";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_gpio_o
-   {
-      datum baseAddress
-      {
-         value = "222720";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_rx_jesd
-   {
-      datum baseAddress
-      {
-         value = "221184";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_rx_os_jesd
-   {
-      datum baseAddress
-      {
-         value = "220160";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_rx_xcvr_reconfig_avmm
-   {
-      datum baseAddress
-      {
-         value = "229376";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_spi
-   {
-      datum baseAddress
-      {
-         value = "222976";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_tx_jesd
-   {
-      datum baseAddress
-      {
-         value = "219136";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_tx_lane_pll
-   {
-      datum baseAddress
-      {
-         value = "212992";
-         type = "String";
-      }
-   }
-   element adrv9371x.avl_xcvr_pll
-   {
-      datum baseAddress
-      {
-         value = "217088";
-         type = "String";
-      }
-   }
-   element adrv9371x.axi_ad9371_s
-   {
-      datum baseAddress
-      {
-         value = "262144";
-         type = "String";
-      }
-   }
-   element adrv9371x.axi_adc_dma_s
-   {
-      datum baseAddress
-      {
-         value = "163840";
-         type = "String";
-      }
-   }
-   element adrv9371x.axi_adc_os_dma_s
-   {
-      datum baseAddress
-      {
-         value = "147456";
-         type = "String";
-      }
-   }
-   element adrv9371x.axi_dac_dma_s
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element adrv9371x.axi_jesd_xcvr
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element adrv9371x.axi_os_jesd_xcvr
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40E2SGE2" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName">adrv9371x_a10soc.qpf</parameter>
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="gpio" internal="adrv9371x.ad9371_gpio" type="conduit" dir="end" />
- <interface name="gpio_i" internal="adrv9371x.gpio_i" type="conduit" dir="end" />
- <interface name="gpio_o" internal="adrv9371x.gpio_o" type="conduit" dir="end" />
- <interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
- <interface
-   name="hps_ddr_oct"
-   internal="a10soc.hps_ddr_oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_ddr_ref_clk"
-   internal="a10soc.hps_ddr_ref_clk"
-   type="clock"
-   dir="end" />
- <interface name="hps_gpio" internal="a10soc.hps_gpio" />
- <interface name="hps_io" internal="a10soc.hps_io" type="conduit" dir="end" />
- <interface name="hps_spi0" internal="a10soc.hps_spi0" type="conduit" dir="end" />
- <interface
-   name="hps_spi0_sclk"
-   internal="a10soc.hps_spi0_sclk"
-   type="clock"
-   dir="start" />
- <interface name="hps_spi1" internal="a10soc.hps_spi1" type="conduit" dir="end" />
- <interface
-   name="hps_spi1_sclk"
-   internal="a10soc.hps_spi1_sclk"
-   type="clock"
-   dir="start" />
- <interface
-   name="ref_clk"
-   internal="adrv9371x.xcvr_ref_clk"
-   type="clock"
-   dir="end" />
- <interface name="rx_data" internal="adrv9371x.rx_data" type="conduit" dir="end" />
- <interface
-   name="rx_os_data"
-   internal="adrv9371x.rx_os_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_os_sync"
-   internal="adrv9371x.rx_os_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_os_sysref"
-   internal="adrv9371x.rx_os_sysref"
-   type="conduit"
-   dir="end" />
- <interface name="rx_sync" internal="adrv9371x.rx_sync" type="conduit" dir="end" />
- <interface
-   name="rx_sysref"
-   internal="adrv9371x.rx_sysref"
-   type="conduit"
-   dir="end" />
- <interface name="spi" internal="adrv9371x.spi" type="conduit" dir="end" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_reset"
-   internal="sys_clk.clk_in_reset"
-   type="reset"
-   dir="end" />
- <interface name="tx_data" internal="adrv9371x.tx_data" type="conduit" dir="end" />
- <interface name="tx_sync" internal="adrv9371x.tx_sync" type="conduit" dir="end" />
- <interface
-   name="tx_sysref"
-   internal="adrv9371x.tx_sysref"
-   type="conduit"
-   dir="end" />
- <module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="1" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="31" />
-  <parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='adrv9371x_axi_os_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='adrv9371x_axi_jesd_xcvr.s_axi' start='0x10000' end='0x20000' /><slave name='adrv9371x_axi_dac_dma.s_axi' start='0x20000' end='0x24000' /><slave name='adrv9371x_axi_os_adc_dma.s_axi' start='0x24000' end='0x28000' /><slave name='adrv9371x_axi_adc_dma.s_axi' start='0x28000' end='0x2C000' /><slave name='adrv9371x_xcvr_tx_lane_pll.reconfig_avmm0' start='0x34000' end='0x35000' /><slave name='adrv9371x_xcvr_pll_reconfig.mgmt_avalon_slave' start='0x35000' end='0x35800' /><slave name='adrv9371x_xcvr_tx_core.jesd204_tx_avs' start='0x35800' end='0x35C00' /><slave name='adrv9371x_xcvr_rx_os_core.jesd204_rx_avs' start='0x35C00' end='0x36000' /><slave name='adrv9371x_xcvr_rx_core.jesd204_rx_avs' start='0x36000' end='0x36400' /><slave name='adrv9371x_ad9371_gpio.s1' start='0x36400' end='0x36420' /><slave name='adrv9371x_gpio_i.s1' start='0x36500' end='0x36510' /><slave name='adrv9371x_gpio_o.s1' start='0x36600' end='0x36620' /><slave name='adrv9371x_spi.spi_control_port' start='0x36700' end='0x36720' /><slave name='adrv9371x_xcvr_rx_core.reconfig_avmm' start='0x38000' end='0x3A000' /><slave name='adrv9371x_axi_ad9371.s_axi' start='0x40000' end='0x50000' /></address-map>]]></parameter>
-  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 19" />
-  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
- </module>
- <module name="adrv9371x" kind="adrv9371x_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_ADC_DMA_M_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_ADC_DMA_M_ADDRESS_WIDTH" value="AddressWidth = 32" />
-  <parameter name="AUTO_AXI_ADC_OS_DMA_M_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_ADC_OS_DMA_M_ADDRESS_WIDTH" value="AddressWidth = 32" />
-  <parameter name="AUTO_AXI_DAC_DMA_M_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_DAC_DMA_M_ADDRESS_WIDTH" value="AddressWidth = 32" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_adrv9371x</parameter>
-  <parameter name="AUTO_XCVR_REF_CLK_CLOCK_DOMAIN" value="4" />
-  <parameter name="AUTO_XCVR_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_XCVR_REF_CLK_RESET_DOMAIN" value="4" />
- </module>
- <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="adrv9371x.axi_adc_dma_m"
-   end="a10soc.hps_s1_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="adrv9371x.axi_adc_os_dma_m"
-   end="a10soc.hps_s1_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="adrv9371x.axi_dac_dma_m"
-   end="a10soc.hps_s1_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_ad9371_gpio">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00036400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_gpio_i">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00036500" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_gpio_o">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00036600" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_rx_jesd">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00036000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_rx_os_jesd">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00035c00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_rx_xcvr_reconfig_avmm">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00038000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_spi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00036700" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_tx_jesd">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00035800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_tx_lane_pll">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00034000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.avl_xcvr_pll">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00035000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.axi_ad9371_s">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00040000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.axi_adc_dma_s">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00028000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.axi_adc_os_dma_s">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00024000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.axi_dac_dma_s">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.axi_jesd_xcvr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a10soc.sys_cpu_m_avl"
-   end="adrv9371x.axi_os_jesd_xcvr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.clk"
-   end="adrv9371x.sys_clk" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq0"
-   end="adrv9371x.ad9371_gpio_irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq0"
-   end="adrv9371x.axi_adc_dma_intr">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq0"
-   end="adrv9371x.axi_adc_os_dma_intr">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq0"
-   end="adrv9371x.axi_dac_dma_intr">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a10soc.hps_irq0"
-   end="adrv9371x.spi_irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="adrv9371x.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="a10soc.sys_rst_in" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc
index ed6d0cc7e..adfd88a83 100644
--- a/projects/adrv9371x/a10soc/system_constr.sdc
+++ b/projects/adrv9371x/a10soc/system_constr.sdc
@@ -8,33 +8,33 @@ derive_clock_uncertainty
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]
+  -to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]
+  -to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_clk}]
+  -to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_os_clk}]
+  -to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
 
-set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_clk}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_os_clk}]\
+set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
diff --git a/projects/adrv9371x/a10soc/system_qsys.tcl b/projects/adrv9371x/a10soc/system_qsys.tcl
new file mode 100644
index 000000000..b34fcb1a6
--- /dev/null
+++ b/projects/adrv9371x/a10soc/system_qsys.tcl
@@ -0,0 +1,8 @@
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
+source ../common/adrv9371x_qsys.tcl
+
+save_system "system_bd.qsys"
+
diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v
index 4e34c4d56..1a350c207 100644
--- a/projects/adrv9371x/a10soc/system_top.v
+++ b/projects/adrv9371x/a10soc/system_top.v
@@ -168,7 +168,7 @@ module system_top (
   // instantiations
 
   system_bd i_system_bd (
-    .gpio_export (ad9371_gpio),
+    .ad9371_gpio_export (ad9371_gpio),
     .hps_ddr_mem_ck (hps_ddr_clk_p),
     .hps_ddr_mem_ck_n (hps_ddr_clk_n),
     .hps_ddr_mem_a (hsp_ddr_a),
@@ -231,25 +231,7 @@ module system_top (
     .hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
     .hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
     .hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
-    .hps_spi0_mosi_o (),
-    .hps_spi0_miso_i (),
-    .hps_spi0_ss_in_n (1'b1),
-    .hps_spi0_mosi_oe (),
-    .hps_spi0_ss0_n_o (),
-    .hps_spi0_ss1_n_o (),
-    .hps_spi0_ss2_n_o (),
-    .hps_spi0_ss3_n_o (),
-    .hps_spi0_sclk_clk (),
-    .hps_spi1_mosi_o (),
-    .hps_spi1_miso_i (1'b0),
-    .hps_spi1_ss_in_n (1'b1),
-    .hps_spi1_mosi_oe (),
-    .hps_spi1_ss0_n_o (),
-    .hps_spi1_ss1_n_o (),
-    .hps_spi1_ss2_n_o (),
-    .hps_spi1_ss3_n_o (),
-    .hps_spi1_sclk_clk (),
-    .ref_clk_clk (ref_clk1),
+    .xcvr_ref_clk_clk (ref_clk1),
     .rx_data_rx_serial_data (rx_data[1:0]),
     .rx_os_data_rx_serial_data (rx_data[3:2]),
     .rx_os_sync_rx_sync (rx_os_sync),
@@ -257,16 +239,16 @@ module system_top (
     .rx_sync_rx_sync (rx_sync),
     .rx_sysref_rx_ext_sysref_in (sysref),
     .sys_clk_clk (sys_clk),
-    .sys_reset_reset_n (sys_resetn),
-    .tx_data_tx_serial_data (tx_data),
+    .sys_rst_reset_n (sys_resetn),
+    .tx_data_tx_serial_data ({tx_data[0],tx_data[3],tx_data[2],tx_data[1]}),
     .tx_sync_tx_sync (tx_sync),
     .tx_sysref_tx_ext_sysref_in (sysref),
     .gpio_i_export (gpio_i),
     .gpio_o_export (gpio_o),
-    .spi_MISO (spi_miso),
-    .spi_MOSI (spi_mosi),
-    .spi_SCLK (spi_clk),
-    .spi_SS_n ({spi_csn_ad9528, spi_csn_ad9371}));
+    .sys_spi_MISO (spi_miso),
+    .sys_spi_MOSI (spi_mosi),
+    .sys_spi_SCLK (spi_clk),
+    .sys_spi_SS_n ({spi_csn_ad9528, spi_csn_ad9371}));
 
 endmodule
 
diff --git a/projects/adrv9371x/common/adrv9371x_bd.qsys b/projects/adrv9371x/common/adrv9371x_bd.qsys
deleted file mode 100755
index da9538a80..000000000
--- a/projects/adrv9371x/common/adrv9371x_bd.qsys
+++ /dev/null
@@ -1,2317 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element ad9371_gpio
-   {
-      datum _sortIndex
-      {
-         value = "21";
-         type = "int";
-      }
-   }
-   element adc_os_pack
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-   }
-   element adc_pack
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element axi_ad9371
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element axi_adc_dma
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_adc_dma.s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element axi_dac_dma
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dac_dma.s_axi
-   {
-      datum baseAddress
-      {
-         value = "16384";
-         type = "String";
-      }
-   }
-   element axi_jesd_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element axi_os_adc_dma
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-   }
-   element axi_os_jesd_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element dac_upack
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element gpio_i
-   {
-      datum _sortIndex
-      {
-         value = "23";
-         type = "int";
-      }
-   }
-   element gpio_o
-   {
-      datum _sortIndex
-      {
-         value = "22";
-         type = "int";
-      }
-   }
-   element spi
-   {
-      datum _sortIndex
-      {
-         value = "24";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element xcvr_pll
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element xcvr_pll_reconfig
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-   element xcvr_ref_clk
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element xcvr_rx_core
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-   }
-   element xcvr_rx_os_core
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element xcvr_rx_os_rst_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element xcvr_rx_rst_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element xcvr_tx_core
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element xcvr_tx_lane_pll
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element xcvr_tx_rst_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="10AS066N3F40E2SGE2" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="ad9371_gpio"
-   internal="ad9371_gpio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ad9371_gpio_irq"
-   internal="ad9371_gpio.irq"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="avl_ad9371_gpio"
-   internal="ad9371_gpio.s1"
-   type="avalon"
-   dir="end" />
- <interface name="avl_gpio_i" internal="gpio_i.s1" type="avalon" dir="end" />
- <interface name="avl_gpio_o" internal="gpio_o.s1" type="avalon" dir="end" />
- <interface
-   name="avl_rx_jesd"
-   internal="xcvr_rx_core.jesd204_rx_avs"
-   type="avalon"
-   dir="end" />
- <interface
-   name="avl_rx_os_jesd"
-   internal="xcvr_rx_os_core.jesd204_rx_avs"
-   type="avalon"
-   dir="end" />
- <interface name="avl_rx_os_xcvr" internal="xcvr_rx_os_core.reconfig_avmm" />
- <interface
-   name="avl_rx_xcvr_reconfig_avmm"
-   internal="xcvr_rx_core.reconfig_avmm"
-   type="avalon"
-   dir="end" />
- <interface
-   name="avl_spi"
-   internal="spi.spi_control_port"
-   type="avalon"
-   dir="end" />
- <interface
-   name="avl_tx_jesd"
-   internal="xcvr_tx_core.jesd204_tx_avs"
-   type="avalon"
-   dir="end" />
- <interface
-   name="avl_tx_lane_pll"
-   internal="xcvr_tx_lane_pll.reconfig_avmm0"
-   type="avalon"
-   dir="end" />
- <interface name="avl_tx_xcvr" internal="xcvr_tx_core.reconfig_avmm" />
- <interface
-   name="avl_xcvr_pll"
-   internal="xcvr_pll_reconfig.mgmt_avalon_slave"
-   type="avalon"
-   dir="end" />
- <interface
-   name="axi_ad9371_s"
-   internal="axi_ad9371.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_adc_dma_intr"
-   internal="axi_adc_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_adc_dma_m"
-   internal="axi_adc_dma.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_adc_dma_s"
-   internal="axi_adc_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_adc_os_dma_intr"
-   internal="axi_os_adc_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_adc_os_dma_m"
-   internal="axi_os_adc_dma.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_adc_os_dma_s"
-   internal="axi_os_adc_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_dac_dma_intr"
-   internal="axi_dac_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dac_dma_m"
-   internal="axi_dac_dma.m_src_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dac_dma_s"
-   internal="axi_dac_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_dmac_adc_fifo_wr_clock"
-   internal="axi_adc_dma.fifo_wr_clock" />
- <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_adc_dma.fifo_wr_if" />
- <interface
-   name="axi_dmac_dac_fifo_rd_clock"
-   internal="axi_dac_dma.fifo_rd_clock" />
- <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dac_dma.fifo_rd_if" />
- <interface
-   name="axi_jesd_xcvr"
-   internal="axi_jesd_xcvr.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_os_jesd_xcvr"
-   internal="axi_os_jesd_xcvr.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="gpio_i"
-   internal="gpio_i.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="gpio_o"
-   internal="gpio_o.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data"
-   internal="xcvr_rx_core.rx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_os_data"
-   internal="xcvr_rx_os_core.rx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_os_sync"
-   internal="axi_os_jesd_xcvr.if_rx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_os_sysref"
-   internal="axi_os_jesd_xcvr.if_rx_ext_sysref_in"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sync"
-   internal="axi_jesd_xcvr.if_rx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sysref"
-   internal="axi_jesd_xcvr.if_rx_ext_sysref_in"
-   type="conduit"
-   dir="end" />
- <interface name="spi" internal="spi.external" type="conduit" dir="end" />
- <interface name="spi_irq" internal="spi.irq" type="interrupt" dir="end" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="tx_data"
-   internal="xcvr_tx_core.tx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="tx_sync"
-   internal="axi_jesd_xcvr.if_tx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="tx_sysref"
-   internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
-   type="conduit"
-   dir="end" />
- <interface
-   name="xcvr_ref_clk"
-   internal="xcvr_ref_clk.in_clk"
-   type="clock"
-   dir="end" />
- <module
-   name="ad9371_gpio"
-   kind="altera_avalon_pio"
-   version="15.1"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="true" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="50000000" />
-  <parameter name="direction" value="Bidir" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="19" />
- </module>
- <module name="adc_os_pack" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
-  <parameter name="NUM_OF_CHANNELS" value="2" />
- </module>
- <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="axi_ad9371" kind="axi_ad9371" version="1.0" enabled="1">
-  <parameter name="ADC_DATAPATH_DISABLE" value="0" />
-  <parameter name="DAC_DATAPATH_DISABLE" value="0" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_adc_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_dac_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="1" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="2" />
-  <parameter name="DMA_TYPE_SRC" value="0" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
- </module>
- <module name="axi_jesd_xcvr" kind="axi_jesd_xcvr" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
-  <parameter name="RX_NUM_OF_LANES" value="2" />
-  <parameter name="TX_NUM_OF_LANES" value="4" />
- </module>
- <module name="axi_os_adc_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module
-   name="axi_os_jesd_xcvr"
-   kind="axi_jesd_xcvr"
-   version="1.0"
-   enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="1" />
-  <parameter name="RX_NUM_OF_LANES" value="2" />
-  <parameter name="TX_NUM_OF_LANES" value="0" />
- </module>
- <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="gpio_i" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="50000000" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module name="gpio_o" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="true" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="50000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module name="spi" kind="altera_avalon_spi" version="15.1" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="1" />
-  <parameter name="clockPolarity" value="1" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="50000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="2" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="5000000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="xcvr_pll" kind="altera_iopll" version="15.1" enabled="1">
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_duty_cycle0" value="50.0" />
-  <parameter name="gui_actual_duty_cycle1" value="50.0" />
-  <parameter name="gui_actual_duty_cycle10" value="50.0" />
-  <parameter name="gui_actual_duty_cycle11" value="50.0" />
-  <parameter name="gui_actual_duty_cycle12" value="50.0" />
-  <parameter name="gui_actual_duty_cycle13" value="50.0" />
-  <parameter name="gui_actual_duty_cycle14" value="50.0" />
-  <parameter name="gui_actual_duty_cycle15" value="50.0" />
-  <parameter name="gui_actual_duty_cycle16" value="50.0" />
-  <parameter name="gui_actual_duty_cycle17" value="50.0" />
-  <parameter name="gui_actual_duty_cycle2" value="50.0" />
-  <parameter name="gui_actual_duty_cycle3" value="50.0" />
-  <parameter name="gui_actual_duty_cycle4" value="50.0" />
-  <parameter name="gui_actual_duty_cycle5" value="50.0" />
-  <parameter name="gui_actual_duty_cycle6" value="50.0" />
-  <parameter name="gui_actual_duty_cycle7" value="50.0" />
-  <parameter name="gui_actual_duty_cycle8" value="50.0" />
-  <parameter name="gui_actual_duty_cycle9" value="50.0" />
-  <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_actual_phase_shift0" value="0.0" />
-  <parameter name="gui_actual_phase_shift1" value="0.0" />
-  <parameter name="gui_actual_phase_shift10" value="0.0" />
-  <parameter name="gui_actual_phase_shift11" value="0.0" />
-  <parameter name="gui_actual_phase_shift12" value="0.0" />
-  <parameter name="gui_actual_phase_shift13" value="0.0" />
-  <parameter name="gui_actual_phase_shift14" value="0.0" />
-  <parameter name="gui_actual_phase_shift15" value="0.0" />
-  <parameter name="gui_actual_phase_shift16" value="0.0" />
-  <parameter name="gui_actual_phase_shift17" value="0.0" />
-  <parameter name="gui_actual_phase_shift2" value="0.0" />
-  <parameter name="gui_actual_phase_shift3" value="0.0" />
-  <parameter name="gui_actual_phase_shift4" value="0.0" />
-  <parameter name="gui_actual_phase_shift5" value="0.0" />
-  <parameter name="gui_actual_phase_shift6" value="0.0" />
-  <parameter name="gui_actual_phase_shift7" value="0.0" />
-  <parameter name="gui_actual_phase_shift8" value="0.0" />
-  <parameter name="gui_actual_phase_shift9" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_clock_name_global0" value="false" />
-  <parameter name="gui_clock_name_global1" value="false" />
-  <parameter name="gui_clock_name_global10" value="false" />
-  <parameter name="gui_clock_name_global11" value="false" />
-  <parameter name="gui_clock_name_global12" value="false" />
-  <parameter name="gui_clock_name_global13" value="false" />
-  <parameter name="gui_clock_name_global14" value="false" />
-  <parameter name="gui_clock_name_global15" value="false" />
-  <parameter name="gui_clock_name_global16" value="false" />
-  <parameter name="gui_clock_name_global17" value="false" />
-  <parameter name="gui_clock_name_global2" value="false" />
-  <parameter name="gui_clock_name_global3" value="false" />
-  <parameter name="gui_clock_name_global4" value="false" />
-  <parameter name="gui_clock_name_global5" value="false" />
-  <parameter name="gui_clock_name_global6" value="false" />
-  <parameter name="gui_clock_name_global7" value="false" />
-  <parameter name="gui_clock_name_global8" value="false" />
-  <parameter name="gui_clock_name_global9" value="false" />
-  <parameter name="gui_clock_name_string0" value="tx_dac_clk" />
-  <parameter name="gui_clock_name_string1" value="rx_adc_clk" />
-  <parameter name="gui_clock_name_string10" value="outclk10" />
-  <parameter name="gui_clock_name_string11" value="outclk11" />
-  <parameter name="gui_clock_name_string12" value="outclk12" />
-  <parameter name="gui_clock_name_string13" value="outclk13" />
-  <parameter name="gui_clock_name_string14" value="outclk14" />
-  <parameter name="gui_clock_name_string15" value="outclk15" />
-  <parameter name="gui_clock_name_string16" value="outclk16" />
-  <parameter name="gui_clock_name_string17" value="outclk17" />
-  <parameter name="gui_clock_name_string2" value="rx_adc_os_clk" />
-  <parameter name="gui_clock_name_string3" value="outclk3" />
-  <parameter name="gui_clock_name_string4" value="outclk4" />
-  <parameter name="gui_clock_name_string5" value="outclk5" />
-  <parameter name="gui_clock_name_string6" value="outclk6" />
-  <parameter name="gui_clock_name_string7" value="outclk7" />
-  <parameter name="gui_clock_name_string8" value="outclk8" />
-  <parameter name="gui_clock_name_string9" value="outclk9" />
-  <parameter name="gui_device_speed_grade" value="1" />
-  <parameter name="gui_divide_factor_c0" value="6" />
-  <parameter name="gui_divide_factor_c1" value="6" />
-  <parameter name="gui_divide_factor_c10" value="6" />
-  <parameter name="gui_divide_factor_c11" value="6" />
-  <parameter name="gui_divide_factor_c12" value="6" />
-  <parameter name="gui_divide_factor_c13" value="6" />
-  <parameter name="gui_divide_factor_c14" value="6" />
-  <parameter name="gui_divide_factor_c15" value="6" />
-  <parameter name="gui_divide_factor_c16" value="6" />
-  <parameter name="gui_divide_factor_c17" value="6" />
-  <parameter name="gui_divide_factor_c2" value="6" />
-  <parameter name="gui_divide_factor_c3" value="6" />
-  <parameter name="gui_divide_factor_c4" value="6" />
-  <parameter name="gui_divide_factor_c5" value="6" />
-  <parameter name="gui_divide_factor_c6" value="6" />
-  <parameter name="gui_divide_factor_c7" value="6" />
-  <parameter name="gui_divide_factor_c8" value="6" />
-  <parameter name="gui_divide_factor_c9" value="6" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50.0" />
-  <parameter name="gui_duty_cycle1" value="50.0" />
-  <parameter name="gui_duty_cycle10" value="50.0" />
-  <parameter name="gui_duty_cycle11" value="50.0" />
-  <parameter name="gui_duty_cycle12" value="50.0" />
-  <parameter name="gui_duty_cycle13" value="50.0" />
-  <parameter name="gui_duty_cycle14" value="50.0" />
-  <parameter name="gui_duty_cycle15" value="50.0" />
-  <parameter name="gui_duty_cycle16" value="50.0" />
-  <parameter name="gui_duty_cycle17" value="50.0" />
-  <parameter name="gui_duty_cycle2" value="50.0" />
-  <parameter name="gui_duty_cycle3" value="50.0" />
-  <parameter name="gui_duty_cycle4" value="50.0" />
-  <parameter name="gui_duty_cycle5" value="50.0" />
-  <parameter name="gui_duty_cycle6" value="50.0" />
-  <parameter name="gui_duty_cycle7" value="50.0" />
-  <parameter name="gui_duty_cycle8" value="50.0" />
-  <parameter name="gui_duty_cycle9" value="50.0" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="Disabled" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="true" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_enable_output_counter_cascading" value="false" />
-  <parameter name="gui_extclkout_0_source" value="C0" />
-  <parameter name="gui_extclkout_1_source" value="C0" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_fix_vco_frequency" value="false" />
-  <parameter name="gui_fixed_vco_frequency" value="600.0" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="6" />
-  <parameter name="gui_number_of_clocks" value="3" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="122.88" />
-  <parameter name="gui_output_clock_frequency1" value="122.88" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="122.88" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0.0" />
-  <parameter name="gui_phase_shift1" value="0.0" />
-  <parameter name="gui_phase_shift10" value="0.0" />
-  <parameter name="gui_phase_shift11" value="0.0" />
-  <parameter name="gui_phase_shift12" value="0.0" />
-  <parameter name="gui_phase_shift13" value="0.0" />
-  <parameter name="gui_phase_shift14" value="0.0" />
-  <parameter name="gui_phase_shift15" value="0.0" />
-  <parameter name="gui_phase_shift16" value="0.0" />
-  <parameter name="gui_phase_shift17" value="0.0" />
-  <parameter name="gui_phase_shift2" value="0.0" />
-  <parameter name="gui_phase_shift3" value="0.0" />
-  <parameter name="gui_phase_shift4" value="0.0" />
-  <parameter name="gui_phase_shift5" value="0.0" />
-  <parameter name="gui_phase_shift6" value="0.0" />
-  <parameter name="gui_phase_shift7" value="0.0" />
-  <parameter name="gui_phase_shift8" value="0.0" />
-  <parameter name="gui_phase_shift9" value="0.0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="false" />
-  <parameter name="gui_pll_bandwidth_preset" value="Low" />
-  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="122.88" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_NDFB_modes" value="false" />
-  <parameter name="gui_use_locked" value="false" />
-  <parameter name="gui_vco_frequency" value="600.0" />
-  <parameter name="system_info_device_component" value="10AS066N3F40E2SGE2" />
-  <parameter name="system_info_device_family" value="Arria 10" />
-  <parameter name="system_info_device_speed_grade" value="2" />
-  <parameter name="system_part_trait_speed_grade" value="2" />
- </module>
- <module
-   name="xcvr_pll_reconfig"
-   kind="altera_pll_reconfig"
-   version="15.1"
-   enabled="1">
-  <parameter name="ENABLE_BYTEENABLE" value="false" />
-  <parameter name="ENABLE_MIF" value="false" />
-  <parameter name="MIF_FILE_NAME" value="" />
-  <parameter name="device_family" value="Arria 10" />
- </module>
- <module
-   name="xcvr_ref_clk"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="xcvr_rx_core" kind="altera_jesd204" version="15.1" enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="4" />
-  <parameter name="GUI_EN_CFG_F" value="false" />
-  <parameter name="HD" value="0" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="32" />
-  <parameter name="L" value="2" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="4" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="122.88" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="non_bonded" />
-  <parameter name="lane_rate" value="4915.2" />
-  <parameter name="part_trait_bd" value="NIGHTFURY4" />
-  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="true" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="true" />
-  <parameter name="set_csr_soft_logic_enable" value="false" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module
-   name="xcvr_rx_os_core"
-   kind="altera_jesd204"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="4" />
-  <parameter name="GUI_EN_CFG_F" value="false" />
-  <parameter name="HD" value="0" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="16" />
-  <parameter name="L" value="2" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="2" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="122.88" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="non_bonded" />
-  <parameter name="lane_rate" value="4915.2" />
-  <parameter name="part_trait_bd" value="NIGHTFURY4" />
-  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="false" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="false" />
-  <parameter name="set_csr_soft_logic_enable" value="false" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module
-   name="xcvr_rx_os_rst_cntrl"
-   kind="altera_xcvr_reset_control"
-   version="15.1"
-   enabled="1">
-  <parameter name="CHANNELS" value="2" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="100" />
-  <parameter name="TX_ENABLE" value="0" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="0" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="70000" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_ANALOGRESET" value="70000" />
-  <parameter name="T_TX_DIGITALRESET" value="70000" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="1" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="0" />
- </module>
- <module
-   name="xcvr_rx_rst_cntrl"
-   kind="altera_xcvr_reset_control"
-   version="15.1"
-   enabled="1">
-  <parameter name="CHANNELS" value="2" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="100" />
-  <parameter name="TX_ENABLE" value="0" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="0" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="70000" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_ANALOGRESET" value="70000" />
-  <parameter name="T_TX_DIGITALRESET" value="70000" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="1" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="0" />
- </module>
- <module name="xcvr_tx_core" kind="altera_jesd204" version="15.1" enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="TX" />
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="4" />
-  <parameter name="GUI_EN_CFG_F" value="false" />
-  <parameter name="HD" value="0" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="32" />
-  <parameter name="L" value="4" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="4" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="125.0" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="non_bonded" />
-  <parameter name="lane_rate" value="4915.2" />
-  <parameter name="part_trait_bd" value="NIGHTFURY4" />
-  <parameter name="part_trait_dp" value="10AS066N3F40E2SGE2" />
-  <parameter name="pll_reconfig_enable" value="false" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="false" />
-  <parameter name="set_csr_soft_logic_enable" value="false" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module
-   name="xcvr_tx_lane_pll"
-   kind="altera_xcvr_atx_pll_a10"
-   version="15.1"
-   enabled="1">
-  <parameter name="base_device" value="NIGHTFURY4" />
-  <parameter name="bw_sel" value="medium" />
-  <parameter name="device" value="10AS066N3F40E2SGE2" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="enable_16G_path" value="0" />
-  <parameter name="enable_8G_path" value="1" />
-  <parameter name="enable_analog_resets" value="0" />
-  <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
-  <parameter name="enable_bonding_clks" value="0" />
-  <parameter name="enable_cascade_out" value="0" />
-  <parameter name="enable_debug_ports_parameters" value="0" />
-  <parameter name="enable_fb_comp_bonding" value="0" />
-  <parameter name="enable_fractional" value="0" />
-  <parameter name="enable_hfreq_clk" value="0" />
-  <parameter name="enable_hip_cal_done_port" value="0" />
-  <parameter name="enable_manual_configuration" value="1" />
-  <parameter name="enable_mcgb" value="0" />
-  <parameter name="enable_mcgb_pcie_clksw" value="0" />
-  <parameter name="enable_pcie_clk" value="0" />
-  <parameter name="enable_pld_atx_cal_busy_port" value="1" />
-  <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
-  <parameter name="enable_pll_reconfig" value="1" />
-  <parameter name="generate_add_hdl_instance_example" value="0" />
-  <parameter name="generate_docs" value="1" />
-  <parameter name="mcgb_aux_clkin_cnt" value="0" />
-  <parameter name="mcgb_div" value="1" />
-  <parameter name="message_level" value="error" />
-  <parameter name="pma_width" value="64" />
-  <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
-  <parameter name="prot_mode" value="Basic" />
-  <parameter name="rcfg_debug" value="0" />
-  <parameter name="rcfg_enable_avmm_busy_port" value="0" />
-  <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
-  <parameter name="rcfg_h_file_enable" value="0" />
-  <parameter name="rcfg_jtag_enable" value="0" />
-  <parameter name="rcfg_mif_file_enable" value="0" />
-  <parameter name="rcfg_multi_enable" value="0" />
-  <parameter name="rcfg_param_vals1" value="" />
-  <parameter name="rcfg_param_vals2" value="" />
-  <parameter name="rcfg_profile_cnt" value="2" />
-  <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_separate_avmm_busy" value="1" />
-  <parameter name="rcfg_sv_file_enable" value="0" />
-  <parameter name="rcfg_txt_file_enable" value="0" />
-  <parameter name="refclk_cnt" value="1" />
-  <parameter name="refclk_index" value="0" />
-  <parameter name="select_manual_config" value="false" />
-  <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
-  <parameter name="set_auto_reference_clock_frequency" value="122.88" />
-  <parameter name="set_capability_reg_enable" value="1" />
-  <parameter name="set_csr_soft_logic_enable" value="1" />
-  <parameter name="set_fref_clock_frequency" value="156.25" />
-  <parameter name="set_hip_cal_en" value="0" />
-  <parameter name="set_k_counter" value="2000000000" />
-  <parameter name="set_l_cascade_counter" value="15" />
-  <parameter name="set_l_cascade_predivider" value="1" />
-  <parameter name="set_l_counter" value="16" />
-  <parameter name="set_m_counter" value="24" />
-  <parameter name="set_manual_reference_clock_frequency" value="200.0" />
-  <parameter name="set_output_clock_frequency" value="2457.6" />
-  <parameter name="set_ref_clk_div" value="1" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="silicon_rev" value="false" />
-  <parameter name="support_mode" value="user_mode" />
-  <parameter name="test_mode" value="0" />
- </module>
- <module
-   name="xcvr_tx_rst_cntrl"
-   kind="altera_xcvr_reset_control"
-   version="15.1"
-   enabled="1">
-  <parameter name="CHANNELS" value="4" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="0" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="100" />
-  <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_ANALOGRESET" value="70000" />
-  <parameter name="T_TX_DIGITALRESET" value="70000" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="1" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="0" />
- </module>
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_ip_avl"
-   end="xcvr_tx_core.jesd204_tx_link" />
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="xcvr_rx_core.jesd204_rx_link"
-   end="axi_jesd_xcvr.if_rx_ip_avl" />
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="xcvr_rx_os_core.jesd204_rx_link"
-   end="axi_os_jesd_xcvr.if_rx_ip_avl" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="ad9371_gpio.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio_o.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio_i.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="spi.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_tx_rst_cntrl.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_rst_cntrl.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_os_rst_cntrl.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_core.jesd204_rx_avs_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_os_core.jesd204_rx_avs_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_tx_core.jesd204_tx_avs_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_adc_dma.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_os_adc_dma.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dac_dma.m_src_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_pll_reconfig.mgmt_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_ref_clk.out_clk"
-   end="xcvr_rx_core.pll_ref_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_ref_clk.out_clk"
-   end="xcvr_rx_os_core.pll_ref_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_ref_clk.out_clk"
-   end="xcvr_tx_lane_pll.pll_refclk0" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rx_core.reconfig_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_tx_lane_pll.reconfig_clk0" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_ref_clk.out_clk"
-   end="xcvr_pll.refclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_adc_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dac_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_jesd_xcvr.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_os_jesd_xcvr.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9371.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_os_adc_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk0"
-   end="axi_ad9371.if_dac_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk0"
-   end="dac_upack.if_dac_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk0"
-   end="axi_dac_dma.if_fifo_rd_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk0"
-   end="axi_jesd_xcvr.if_tx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk0"
-   end="xcvr_tx_core.txlink_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk1"
-   end="adc_pack.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk1"
-   end="axi_ad9371.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk1"
-   end="axi_adc_dma.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk1"
-   end="axi_jesd_xcvr.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk1"
-   end="xcvr_rx_core.rxlink_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk2"
-   end="adc_os_pack.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk2"
-   end="axi_ad9371.if_adc_os_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk2"
-   end="axi_os_adc_dma.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk2"
-   end="axi_os_jesd_xcvr.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_pll.outclk2"
-   end="xcvr_rx_os_core.rxlink_clk" />
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.adc_ch_0"
-   end="axi_ad9371.adc_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_os_pack.adc_ch_0"
-   end="axi_ad9371.adc_os_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9371.adc_ch_1"
-   end="adc_pack.adc_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.adc_ch_2"
-   end="axi_ad9371.adc_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9371.adc_ch_3"
-   end="adc_pack.adc_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9371.adc_os_ch_1"
-   end="adc_os_pack.adc_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_os_core.alldev_lane_aligned"
-   end="xcvr_rx_os_core.dev_lane_aligned">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.dac_ch_0"
-   end="axi_ad9371.dac_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9371.dac_ch_1"
-   end="dac_upack.dac_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.dac_ch_2"
-   end="axi_ad9371.dac_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9371.dac_ch_3"
-   end="dac_upack.dac_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_core.dev_lane_aligned"
-   end="xcvr_rx_core.alldev_lane_aligned">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_core.dev_sync_n"
-   end="axi_jesd_xcvr.if_rx_ip_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_core.dev_sync_n"
-   end="xcvr_tx_core.mdev_sync_n">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_data"
-   end="axi_adc_dma.if_fifo_wr_din">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_os_pack.if_adc_data"
-   end="axi_os_adc_dma.if_fifo_wr_din">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9371.if_adc_rx_data"
-   end="axi_jesd_xcvr.if_rx_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9371.if_adc_rx_os_data"
-   end="axi_os_jesd_xcvr.if_rx_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_sync"
-   end="axi_adc_dma.if_fifo_wr_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_os_pack.if_adc_sync"
-   end="axi_os_adc_dma.if_fifo_wr_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="adc_pack.if_adc_valid"
-   end="axi_adc_dma.if_fifo_wr_en">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="dac_upack.if_dac_data"
-   end="axi_dac_dma.if_fifo_rd_dout">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dac_dma.if_fifo_rd_en"
-   end="dac_upack.if_dac_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dac_dma.if_fifo_rd_underflow"
-   end="axi_ad9371.if_dac_dunf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_os_adc_dma.if_fifo_wr_en"
-   end="adc_os_pack.if_adc_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_adc_dma.if_fifo_wr_overflow"
-   end="axi_ad9371.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_os_adc_dma.if_fifo_wr_overflow"
-   end="axi_ad9371.if_adc_os_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sof"
-   end="xcvr_rx_core.sof">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_os_jesd_xcvr.if_rx_ip_sync"
-   end="xcvr_rx_os_core.dev_sync_n">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sysref"
-   end="xcvr_rx_core.sysref">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ready"
-   end="xcvr_rx_rst_cntrl.rx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_data"
-   end="axi_ad9371.if_dac_tx_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_ip_sync"
-   end="xcvr_tx_core.sync_n">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_ip_sysref"
-   end="xcvr_tx_core.sysref">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_lane_pll.pll_cal_busy"
-   end="xcvr_tx_rst_cntrl.pll_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_lane_pll.pll_locked"
-   end="xcvr_tx_rst_cntrl.pll_locked">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_lane_pll.pll_powerdown"
-   end="xcvr_tx_rst_cntrl.pll_powerdown">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_pll_reconfig.reconfig_from_pll"
-   end="xcvr_pll.reconfig_from_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_pll_reconfig.reconfig_to_pll"
-   end="xcvr_pll.reconfig_to_pll">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_core.rx_analogreset"
-   end="xcvr_rx_rst_cntrl.rx_analogreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_os_core.rx_analogreset"
-   end="xcvr_rx_os_rst_cntrl.rx_analogreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_rst_cntrl.rx_cal_busy"
-   end="xcvr_rx_core.rx_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_os_rst_cntrl.rx_cal_busy"
-   end="xcvr_rx_os_core.rx_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_rst_cntrl.rx_digitalreset"
-   end="xcvr_rx_core.rx_digitalreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_os_rst_cntrl.rx_digitalreset"
-   end="xcvr_rx_os_core.rx_digitalreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_core.rx_islockedtodata"
-   end="xcvr_rx_rst_cntrl.rx_is_lockedtodata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_os_core.rx_islockedtodata"
-   end="xcvr_rx_os_rst_cntrl.rx_is_lockedtodata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_os_rst_cntrl.rx_ready"
-   end="axi_os_jesd_xcvr.if_rx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_os_core.sof"
-   end="axi_os_jesd_xcvr.if_rx_ip_sof">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rx_os_core.sysref"
-   end="axi_os_jesd_xcvr.if_rx_ip_sysref">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_core.tx_analogreset"
-   end="xcvr_tx_rst_cntrl.tx_analogreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_core.tx_cal_busy"
-   end="xcvr_tx_rst_cntrl.tx_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_rst_cntrl.tx_digitalreset"
-   end="xcvr_tx_core.tx_digitalreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_tx_rst_cntrl.tx_ready"
-   end="axi_jesd_xcvr.if_tx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_tx_core.tx_serial_clk0_ch0" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_tx_core.tx_serial_clk0_ch1" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_tx_core.tx_serial_clk0_ch2" />
- <connection
-   kind="hssi_serial_clock"
-   version="15.1"
-   start="xcvr_tx_lane_pll.tx_serial_clk"
-   end="xcvr_tx_core.tx_serial_clk0_ch3" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_tx_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_os_jesd_xcvr.if_rst"
-   end="xcvr_rx_os_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_rstn"
-   end="adc_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_os_jesd_xcvr.if_rx_rstn"
-   end="adc_os_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_rstn"
-   end="xcvr_rx_core.rxlink_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_os_jesd_xcvr.if_rx_rstn"
-   end="xcvr_rx_os_core.rxlink_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_tx_rstn"
-   end="xcvr_tx_core.txlink_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_core.jesd204_rx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_os_core.jesd204_rx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_core.jesd204_tx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_adc_dma.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_os_adc_dma.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dac_dma.m_src_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_pll_reconfig.mgmt_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_core.reconfig_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_lane_pll.reconfig_reset0" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_tx_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_rx_os_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="ad9371_gpio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="gpio_o.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="gpio_i.reset" />
- <connection kind="reset" version="15.1" start="sys_rst.out_reset" end="spi.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_adc_dma.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dac_dma.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_jesd_xcvr.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_os_jesd_xcvr.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9371.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_os_adc_dma.s_axi_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
- <interconnectRequirement
-   for="mm_interconnect_0|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_2|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
-</system>
diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index c13a800b2..dd237be5e 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -528,9 +528,6 @@ add_connection sys_clk.clk xcvr_rx_os_rst_cntrl.clock
 add_connection sys_clk.clk xcvr_rx_core.jesd204_rx_avs_clk
 add_connection sys_clk.clk xcvr_rx_os_core.jesd204_rx_avs_clk
 add_connection sys_clk.clk xcvr_tx_core.jesd204_tx_avs_clk
-add_connection sys_ddr3_cntrl.emif_usr_clk axi_adc_dma.m_dest_axi_clock
-add_connection sys_ddr3_cntrl.emif_usr_clk axi_os_adc_dma.m_dest_axi_clock
-add_connection sys_ddr3_cntrl.emif_usr_clk axi_dac_dma.m_src_axi_clock
 add_connection sys_clk.clk xcvr_pll_reconfig.mgmt_clk
 #add_connection sys_clk.clk xcvr_rx_core.reconfig_clk
 #add_connection sys_clk.clk xcvr_rx_os_core.reconfig_clk
@@ -544,12 +541,8 @@ add_connection sys_clk.clk axi_ad9371.s_axi_clock
 add_connection sys_clk.clk axi_os_adc_dma.s_axi_clock
 add_connection sys_clk.clk ad9371_gpio.clk
 
-
 add_connection sys_clk.clk_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n
 add_connection sys_clk.clk_reset xcvr_tx_core.jesd204_tx_avs_rst_n
-add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_adc_dma.m_dest_axi_reset
-add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_os_adc_dma.m_dest_axi_reset
-add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_dac_dma.m_src_axi_reset
 add_connection sys_clk.clk_reset xcvr_pll_reconfig.mgmt_reset
 add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
 add_connection sys_clk.clk_reset xcvr_pll.reset
@@ -589,6 +582,26 @@ add_connection xcvr_pll.outclk2 rx_os_adcfifo.if_adc_clk
 add_connection xcvr_pll.outclk2 rx_os_adcfifo.if_dma_clk
 add_connection xcvr_pll.outclk2 axi_os_adc_dma.if_s_axis_aclk
 
+# NIOS
+if { $system_type=="nios" } {
+  add_connection sys_ddr3_cntrl.emif_usr_clk axi_adc_dma.m_dest_axi_clock
+  add_connection sys_ddr3_cntrl.emif_usr_clk axi_os_adc_dma.m_dest_axi_clock
+  add_connection sys_ddr3_cntrl.emif_usr_clk axi_dac_dma.m_src_axi_clock
+  add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_adc_dma.m_dest_axi_reset
+  add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_os_adc_dma.m_dest_axi_reset
+  add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_dac_dma.m_src_axi_reset
+}
+
+# SOC
+if { $system_type=="a10soc" } {
+  add_connection arria10_hps_0.h2f_user0_clock axi_adc_dma.m_dest_axi_clock
+  add_connection arria10_hps_0.h2f_user0_clock axi_os_adc_dma.m_dest_axi_clock
+  add_connection arria10_hps_0.h2f_user0_clock axi_dac_dma.m_src_axi_clock
+  add_connection sys_clk.clk_reset axi_adc_dma.m_dest_axi_reset
+  add_connection sys_clk.clk_reset axi_os_adc_dma.m_dest_axi_reset
+  add_connection sys_clk.clk_reset axi_dac_dma.m_src_axi_reset
+}
+
 add_connection adc_pack.adc_ch_0 axi_ad9371.adc_ch_0
 add_connection adc_pack.adc_ch_1 axi_ad9371.adc_ch_1
 add_connection adc_pack.adc_ch_2 axi_ad9371.adc_ch_2
@@ -704,52 +717,110 @@ set_interface_property ad9371_gpio EXPORT_OF ad9371_gpio.external_connection
 
 # addresses
 
-add_connection sys_cpu.data_master xcvr_pll_reconfig.mgmt_avalon_slave
-add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
-add_connection sys_cpu.data_master axi_adc_dma.s_axi
-add_connection sys_cpu.data_master axi_dac_dma.s_axi
-add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
-add_connection sys_cpu.data_master axi_os_jesd_xcvr.s_axi
-add_connection sys_cpu.data_master axi_ad9371.s_axi
-add_connection sys_cpu.data_master axi_os_adc_dma.s_axi
-#add_connection sys_cpu.data_master xcvr_rx_core.reconfig_avmm
-add_connection sys_cpu.data_master xcvr_rx_core.jesd204_rx_avs
-#add_connection sys_cpu.data_master xcvr_rx_os_core.reconfig_avmm
-add_connection sys_cpu.data_master xcvr_rx_os_core.jesd204_rx_avs
-add_connection sys_cpu.data_master xcvr_tx_core.reconfig_avmm
-add_connection sys_cpu.data_master xcvr_tx_core.jesd204_tx_avs
-add_connection sys_cpu.data_master ad9371_gpio.s1
+# NIOS
+if { $system_type=="nios" } {
+  add_connection sys_cpu.data_master xcvr_pll_reconfig.mgmt_avalon_slave
+  add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
+  add_connection sys_cpu.data_master axi_adc_dma.s_axi
+  add_connection sys_cpu.data_master axi_dac_dma.s_axi
+  add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
+  add_connection sys_cpu.data_master axi_os_jesd_xcvr.s_axi
+  add_connection sys_cpu.data_master axi_ad9371.s_axi
+  add_connection sys_cpu.data_master axi_os_adc_dma.s_axi
+  #add_connection sys_cpu.data_master xcvr_rx_core.reconfig_avmm
+  add_connection sys_cpu.data_master xcvr_rx_core.jesd204_rx_avs
+  #add_connection sys_cpu.data_master xcvr_rx_os_core.reconfig_avmm
+  add_connection sys_cpu.data_master xcvr_rx_os_core.jesd204_rx_avs
+  add_connection sys_cpu.data_master xcvr_tx_core.reconfig_avmm
+  add_connection sys_cpu.data_master xcvr_tx_core.jesd204_tx_avs
+  add_connection sys_cpu.data_master ad9371_gpio.s1
 
-add_connection axi_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
-add_connection axi_os_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
-add_connection axi_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
+  add_connection axi_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+  add_connection axi_os_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+  add_connection axi_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
 
-set_connection_parameter_value sys_cpu.data_master/xcvr_pll_reconfig.mgmt_avalon_slave  baseAddress {0x1003d800}
-set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0      baseAddress {0x1003c000}
-set_connection_parameter_value sys_cpu.data_master/axi_adc_dma.s_axi                    baseAddress {0x10034000}
-set_connection_parameter_value sys_cpu.data_master/axi_dac_dma.s_axi                    baseAddress {0x10010000}
-set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi                  baseAddress {0x10040000}
-set_connection_parameter_value sys_cpu.data_master/axi_os_jesd_xcvr.s_axi               baseAddress {0x10020000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9371.s_axi                     baseAddress {0x10000000}
-set_connection_parameter_value sys_cpu.data_master/axi_os_adc_dma.s_axi                 baseAddress {0x10500000}
-#set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.reconfig_avmm           baseAddress {0x10030000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.jesd204_rx_avs          baseAddress {0x1003e400}
-#set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.reconfig_avmm        baseAddress {0x10130000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.jesd204_rx_avs       baseAddress {0x1013e400}
-set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.reconfig_avmm           baseAddress {0x10050000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.jesd204_tx_avs          baseAddress {0x1005e400}
-set_connection_parameter_value sys_cpu.data_master/ad9371_gpio.s1                       baseAddress {0x10060000}
+  set_connection_parameter_value sys_cpu.data_master/xcvr_pll_reconfig.mgmt_avalon_slave  baseAddress {0x1003d800}
+  set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0      baseAddress {0x1003c000}
+  set_connection_parameter_value sys_cpu.data_master/axi_adc_dma.s_axi                    baseAddress {0x10034000}
+  set_connection_parameter_value sys_cpu.data_master/axi_dac_dma.s_axi                    baseAddress {0x10010000}
+  set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi                  baseAddress {0x10040000}
+  set_connection_parameter_value sys_cpu.data_master/axi_os_jesd_xcvr.s_axi               baseAddress {0x10020000}
+  set_connection_parameter_value sys_cpu.data_master/axi_ad9371.s_axi                     baseAddress {0x10000000}
+  set_connection_parameter_value sys_cpu.data_master/axi_os_adc_dma.s_axi                 baseAddress {0x10500000}
+  #set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.reconfig_avmm           baseAddress {0x10030000}
+  set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.jesd204_rx_avs          baseAddress {0x1003e400}
+  #set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.reconfig_avmm        baseAddress {0x10130000}
+  set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.jesd204_rx_avs       baseAddress {0x1013e400}
+  set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.reconfig_avmm           baseAddress {0x10050000}
+  set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.jesd204_tx_avs          baseAddress {0x1005e400}
+  set_connection_parameter_value sys_cpu.data_master/ad9371_gpio.s1                       baseAddress {0x10060000}
 
-set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
-set_connection_parameter_value axi_os_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0      baseAddress {0x00000000}
-set_connection_parameter_value axi_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0          baseAddress {0x00000000}
+  set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
+  set_connection_parameter_value axi_os_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0      baseAddress {0x00000000}
+  set_connection_parameter_value axi_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0          baseAddress {0x00000000}
+}
+
+# SOC
+if { $system_type=="a10soc" } {
+  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_pll_reconfig.mgmt_avalon_slave
+  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_lane_pll.reconfig_avmm0
+  add_connection arria10_hps_0.h2f_lw_axi_master axi_adc_dma.s_axi
+  add_connection arria10_hps_0.h2f_lw_axi_master axi_dac_dma.s_axi
+  add_connection arria10_hps_0.h2f_lw_axi_master axi_jesd_xcvr.s_axi
+  add_connection arria10_hps_0.h2f_lw_axi_master axi_os_jesd_xcvr.s_axi
+  add_connection arria10_hps_0.h2f_lw_axi_master axi_ad9371.s_axi
+  add_connection arria10_hps_0.h2f_lw_axi_master axi_os_adc_dma.s_axi
+  #add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_core.reconfig_avmm
+  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_core.jesd204_rx_avs
+  #add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_os_core.reconfig_avmm
+  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_os_core.jesd204_rx_avs
+  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.reconfig_avmm
+  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.jesd204_tx_avs
+  add_connection arria10_hps_0.h2f_lw_axi_master ad9371_gpio.s1
+
+  add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data
+  add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data
+  add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram0_data
+
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/ad9371_gpio.s1 baseAddress {0x00001000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_pll_reconfig.mgmt_avalon_slave baseAddress {0x00010000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_lane_pll.reconfig_avmm0 baseAddress {0x00011000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_jesd_xcvr.s_axi baseAddress {0x00020000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_rx_core.jesd204_rx_avs baseAddress {0x00030000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_jesd_xcvr.s_axi baseAddress {0x00040000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_rx_os_core.jesd204_rx_avs baseAddress {0x00050000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_core.jesd204_tx_avs baseAddress {0x00060000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_core.reconfig_avmm baseAddress {0x00064000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_ad9371.s_axi baseAddress {0x00070000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_dac_dma.s_axi baseAddress {0x00080000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_adc_dma.s_axi baseAddress {0x0090000}
+  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_adc_dma.s_axi baseAddress {0x000a0000}
+
+  set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
+  set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
+  set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
+}
 
 # interrupts
 
-add_connection sys_cpu.irq axi_adc_dma.interrupt_sender
-add_connection sys_cpu.irq axi_dac_dma.interrupt_sender
-add_connection sys_cpu.irq axi_os_adc_dma.interrupt_sender
-set_connection_parameter_value sys_cpu.irq/axi_adc_dma.interrupt_sender irqNumber {10}
-set_connection_parameter_value sys_cpu.irq/axi_dac_dma.interrupt_sender irqNumber {11}
-set_connection_parameter_value sys_cpu.irq/axi_os_adc_dma.interrupt_sender irqNumber {12}
+# NIOS
+if { $system_type=="nios" } {
+  add_connection sys_cpu.irq axi_adc_dma.interrupt_sender
+  add_connection sys_cpu.irq axi_dac_dma.interrupt_sender
+  add_connection sys_cpu.irq axi_os_adc_dma.interrupt_sender
 
+  set_connection_parameter_value sys_cpu.irq/axi_adc_dma.interrupt_sender irqNumber {10}
+  set_connection_parameter_value sys_cpu.irq/axi_dac_dma.interrupt_sender irqNumber {11}
+  set_connection_parameter_value sys_cpu.irq/axi_os_adc_dma.interrupt_sender irqNumber {12}
+}
+
+# SOC
+if { $system_type=="a10soc" } {
+  add_connection arria10_hps_0.f2h_irq0 axi_adc_dma.interrupt_sender
+  add_connection arria10_hps_0.f2h_irq0 axi_dac_dma.interrupt_sender
+  add_connection arria10_hps_0.f2h_irq0 axi_os_adc_dma.interrupt_sender
+
+  set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_adc_dma.interrupt_sender irqNumber {10}
+  set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_dac_dma.interrupt_sender irqNumber {11}
+  set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_os_adc_dma.interrupt_sender irqNumber {12}
+}

From be41a8bcaae7fe58c824f0b819686baff010fb0d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 1 Sep 2016 16:50:32 +0300
Subject: [PATCH 455/972] axi_ad9361: Delete debug ports of the tdd module

---
 library/axi_ad9361/axi_ad9361.v     |  3 +--
 library/axi_ad9361/axi_ad9361_tdd.v | 10 +---------
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 957ee9598..53a4c2f13 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -559,8 +559,7 @@ module axi_ad9361 (
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata_tdd_s),
-    .up_rack (up_rack_tdd_s),
-    .tdd_dbg ());
+    .up_rack (up_rack_tdd_s));
 
   // receive
 
diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index 8a5fb9144..84b17d2a9 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -98,10 +98,7 @@ module axi_ad9361_tdd (
   up_rreq,
   up_raddr,
   up_rdata,
-  up_rack,
-
-  tdd_dbg
-);
+  up_rack);
 
   input             clk;
   input             rst;
@@ -158,8 +155,6 @@ module axi_ad9361_tdd (
   output  [31:0]    up_rdata;
   output            up_rack;
 
-  output  [41:0]    tdd_dbg;
-
   reg               tdd_slave_synced = 1'b0;
 
   reg               tdd_tx_valid    = 1'b0;
@@ -216,9 +211,6 @@ module axi_ad9361_tdd (
   wire              tdd_rx_dp_en_s;
   wire              tdd_tx_dp_en_s;
 
-  assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_sync, tdd_tx_dp_en_s,
-                    tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
-
   assign  tdd_enabled = tdd_enable_s;
   assign  tdd_sync_cntr = ~(tdd_enable_s & tdd_terminal_type_s);
 

From e42206e5105da5cff2b3ab09e8c9fdde271e3939 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 8 Sep 2016 18:09:45 +0300
Subject: [PATCH 456/972] axi_ad9361: Add a TDD enable/disable parameter

---
 library/axi_ad9361/axi_ad9361.v | 175 +++++++++++++++++++-------------
 1 file changed, 106 insertions(+), 69 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 53a4c2f13..6e5c85292 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -170,6 +170,7 @@ module axi_ad9361 (
   parameter   IO_DELAY_GROUP = "dev_if_delay_group";
   parameter   DAC_DATAPATH_DISABLE = 0;
   parameter   ADC_DATAPATH_DISABLE = 0;
+  parameter   TDD_CONTROL_EN = 0;
 
   // physical interface (receive-lvds)
 
@@ -298,10 +299,10 @@ module axi_ad9361 (
   reg             up_wack = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
-  reg     [15:0]  adc_data_i0 = 16'b0;
-  reg     [15:0]  adc_data_q0 = 16'b0;
-  reg     [15:0]  adc_data_i1 = 16'b0;
-  reg     [15:0]  adc_data_q1 = 16'b0;
+  reg     [15:0]  adc_data_i0_b = 16'b0;
+  reg     [15:0]  adc_data_q0_b = 16'b0;
+  reg     [15:0]  adc_data_i1_b = 16'b0;
+  reg     [15:0]  adc_data_q1_b = 16'b0;
 
   // internal clocks and resets
 
@@ -346,11 +347,6 @@ module axi_ad9361 (
   wire            up_rack_tdd_s;
   wire    [31:0]  up_rdata_tdd_s;
   wire            tdd_tx_dp_en_s;
-  wire            tdd_rx_vco_en_s;
-  wire            tdd_tx_vco_en_s;
-  wire            tdd_rx_rf_en_s;
-  wire            tdd_tx_rf_en_s;
-  wire    [ 7:0]  tdd_status_s;
   wire            tdd_enable_s;
   wire            tdd_txnrx_s;
   wire            tdd_mode_s;
@@ -497,69 +493,110 @@ module axi_ad9361 (
   end
   endgenerate
 
-  // TDD interface
+  generate
+  if (TDD_CONTROL_EN) begin
 
-  // additional flop to keep control and data synced
+    wire            tdd_rx_vco_en_s;
+    wire            tdd_tx_vco_en_s;
+    wire            tdd_rx_rf_en_s;
+    wire            tdd_tx_rf_en_s;
+    wire    [ 7:0]  tdd_status_s;
+
+    // additional flop to keep control and data synced
+
+    assign adc_data_i0 = adc_data_i0_b;
+    assign adc_data_q0 = adc_data_q0_b;
+    assign adc_data_i1 = adc_data_i1_b;
+    assign adc_data_q1 = adc_data_q1_b;
+
+    always @(posedge clk) begin
+      adc_data_i0_b <= adc_data_i0_s;
+      adc_data_q0_b <= adc_data_q0_s;
+      adc_data_i1_b <= adc_data_i1_s;
+      adc_data_q1_b <= adc_data_q1_s;
+    end
+
+    axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
+      .clk (clk),
+      .rst (rst),
+      .tdd_rx_vco_en (tdd_rx_vco_en_s),
+      .tdd_tx_vco_en (tdd_tx_vco_en_s),
+      .tdd_rx_rf_en (tdd_rx_rf_en_s),
+      .tdd_tx_rf_en (tdd_tx_rf_en_s),
+      .ad9361_txnrx (tdd_txnrx_s),
+      .ad9361_enable (tdd_enable_s),
+      .ad9361_tdd_status (tdd_status_s));
+
+    // TDD control
+
+    axi_ad9361_tdd i_tdd (
+      .clk (clk),
+      .rst (rst),
+      .tdd_rx_vco_en (tdd_rx_vco_en_s),
+      .tdd_tx_vco_en (tdd_tx_vco_en_s),
+      .tdd_rx_rf_en (tdd_rx_rf_en_s),
+      .tdd_tx_rf_en (tdd_tx_rf_en_s),
+      .tdd_enabled (tdd_mode_s),
+      .tdd_status (tdd_status_s),
+      .tdd_sync (tdd_sync),
+      .tdd_sync_cntr (tdd_sync_cntr),
+      .tx_valid (dac_valid_s),
+      .tx_valid_i0 (dac_valid_i0_s),
+      .tx_valid_q0 (dac_valid_q0_s),
+      .tx_valid_i1 (dac_valid_i1_s),
+      .tx_valid_q1 (dac_valid_q1_s),
+      .tdd_tx_valid (g_dac_valid_s),
+      .tdd_tx_valid_i0 (dac_valid_i0),
+      .tdd_tx_valid_q0 (dac_valid_q0),
+      .tdd_tx_valid_i1 (dac_valid_i1),
+      .tdd_tx_valid_q1 (dac_valid_q1),
+      .rx_valid_i0 (adc_valid_i0_s),
+      .rx_valid_q0 (adc_valid_q0_s),
+      .rx_valid_i1 (adc_valid_i1_s),
+      .rx_valid_q1 (adc_valid_q1_s),
+      .tdd_rx_valid_i0 (adc_valid_i0),
+      .tdd_rx_valid_q0 (adc_valid_q0),
+      .tdd_rx_valid_i1 (adc_valid_i1),
+      .tdd_rx_valid_q1 (adc_valid_q1),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq_s),
+      .up_waddr (up_waddr_s),
+      .up_wdata (up_wdata_s),
+      .up_wack (up_wack_tdd_s),
+      .up_rreq (up_rreq_s),
+      .up_raddr (up_raddr_s),
+      .up_rdata (up_rdata_tdd_s),
+      .up_rack (up_rack_tdd_s));
+
+  end else begin
+
+    // TDD control bypass
+
+    assign tdd_mode_s     = 1'b0;
+    assign tdd_status_s   = 8'b0;
+    assign tdd_enable_s   = 1'b0;
+    assign tdd_txnrx_s    = 1'b0;
+    assign adc_data_i0    = adc_data_i0_s;
+    assign adc_data_q0    = adc_data_q0_s;
+    assign adc_data_i1    = adc_data_i1_s;
+    assign adc_data_q1    = adc_data_q1_s;
+    assign tdd_sync_cntr  = 1'b0;
+    assign g_dac_valid_s  = dac_valid_s;
+    assign dac_valid_i0   = dac_valid_i0_s;
+    assign dac_valid_q0   = dac_valid_q0_s;
+    assign dac_valid_i1   = dac_valid_i1_s;
+    assign dac_valid_q1   = dac_valid_q1_s;
+    assign adc_valid_i0   = adc_valid_i0_s;
+    assign adc_valid_q0   = adc_valid_q0_s;
+    assign adc_valid_i1   = adc_valid_i1_s;
+    assign adc_valid_q1   = adc_valid_q1_s;
+    assign up_wack_tdd_s  = 1'b0;
+    assign up_rack_tdd_s  = 1'b0;
+    assign up_rdata_tdd_s = 32'b0;
 
-  always @(posedge clk) begin
-    adc_data_i0 <= adc_data_i0_s;
-    adc_data_q0 <= adc_data_q0_s;
-    adc_data_i1 <= adc_data_i1_s;
-    adc_data_q1 <= adc_data_q1_s;
   end
-
-  axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
-    .clk (clk),
-    .rst (rst),
-    .tdd_rx_vco_en (tdd_rx_vco_en_s),
-    .tdd_tx_vco_en (tdd_tx_vco_en_s),
-    .tdd_rx_rf_en (tdd_rx_rf_en_s),
-    .tdd_tx_rf_en (tdd_tx_rf_en_s),
-    .ad9361_txnrx (tdd_txnrx_s),
-    .ad9361_enable (tdd_enable_s),
-    .ad9361_tdd_status (tdd_status_s));
-
-  // TDD control
-
-  axi_ad9361_tdd i_tdd (
-    .clk (clk),
-    .rst (rst),
-    .tdd_rx_vco_en (tdd_rx_vco_en_s),
-    .tdd_tx_vco_en (tdd_tx_vco_en_s),
-    .tdd_rx_rf_en (tdd_rx_rf_en_s),
-    .tdd_tx_rf_en (tdd_tx_rf_en_s),
-    .tdd_enabled (tdd_mode_s),
-    .tdd_status (tdd_status_s),
-    .tdd_sync (tdd_sync),
-    .tdd_sync_cntr (tdd_sync_cntr),
-    .tx_valid (dac_valid_s),
-    .tx_valid_i0 (dac_valid_i0_s),
-    .tx_valid_q0 (dac_valid_q0_s),
-    .tx_valid_i1 (dac_valid_i1_s),
-    .tx_valid_q1 (dac_valid_q1_s),
-    .tdd_tx_valid (g_dac_valid_s),
-    .tdd_tx_valid_i0 (dac_valid_i0),
-    .tdd_tx_valid_q0 (dac_valid_q0),
-    .tdd_tx_valid_i1 (dac_valid_i1),
-    .tdd_tx_valid_q1 (dac_valid_q1),
-    .rx_valid_i0 (adc_valid_i0_s),
-    .rx_valid_q0 (adc_valid_q0_s),
-    .rx_valid_i1 (adc_valid_i1_s),
-    .rx_valid_q1 (adc_valid_q1_s),
-    .tdd_rx_valid_i0 (adc_valid_i0),
-    .tdd_rx_valid_q0 (adc_valid_q0),
-    .tdd_rx_valid_i1 (adc_valid_i1),
-    .tdd_rx_valid_q1 (adc_valid_q1),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq_s),
-    .up_waddr (up_waddr_s),
-    .up_wdata (up_wdata_s),
-    .up_wack (up_wack_tdd_s),
-    .up_rreq (up_rreq_s),
-    .up_raddr (up_raddr_s),
-    .up_rdata (up_rdata_tdd_s),
-    .up_rack (up_rack_tdd_s));
+  endgenerate
 
   // receive
 

From a183e51a12824df6b92a861639e226ef622cf549 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 9 Sep 2016 16:34:11 +0300
Subject: [PATCH 457/972] axi_ad9361: Add parameter R1_MODE_EN

R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
---
 library/axi_ad9361/axi_ad9361.v    |  7 +++++--
 library/axi_ad9361/axi_ad9361_rx.v |  7 +++++++
 library/axi_ad9361/axi_ad9361_tx.v | 31 ++++++++++++++++++------------
 3 files changed, 31 insertions(+), 14 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 6e5c85292..32e768afb 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -171,6 +171,7 @@ module axi_ad9361 (
   parameter   DAC_DATAPATH_DISABLE = 0;
   parameter   ADC_DATAPATH_DISABLE = 0;
   parameter   TDD_CONTROL_EN = 0;
+  parameter   R1_MODE_EN = 0;
 
   // physical interface (receive-lvds)
 
@@ -602,7 +603,8 @@ module axi_ad9361 (
 
   axi_ad9361_rx #(
     .ID (ID),
-    .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
+    .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE),
+    .R1_MODE_EN (R1_MODE_EN))
   i_rx (
     .mmcm_rst (mmcm_rst),
     .adc_rst (rst),
@@ -650,7 +652,8 @@ module axi_ad9361 (
 
   axi_ad9361_tx #(
     .ID (ID),
-    .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
+    .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE),
+    .R1_MODE_EN (R1_MODE_EN))
   i_tx (
     .dac_clk (clk),
     .dac_valid (dac_valid_s),
diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v
index 271b2138b..db4044d1a 100644
--- a/library/axi_ad9361/axi_ad9361_rx.v
+++ b/library/axi_ad9361/axi_ad9361_rx.v
@@ -103,6 +103,7 @@ module axi_ad9361_rx (
 
   parameter   DATAPATH_DISABLE = 0;
   parameter   ID = 0;
+  parameter   R1_MODE_EN = 0;
 
   // common
 
@@ -274,6 +275,9 @@ module axi_ad9361_rx (
     .up_rdata (up_rdata_s[1]),
     .up_rack (up_rack_s[1]));
 
+  generate
+  if (R1_MODE_EN == 0) begin
+
   // channel 2 (i)
 
   axi_ad9361_rx_channel #(
@@ -340,6 +344,9 @@ module axi_ad9361_rx (
     .up_rdata (up_rdata_s[3]),
     .up_rack (up_rack_s[3]));
 
+  end
+  endgenerate
+
   // common processor control
 
   up_adc_common #(.ID (ID)) i_up_adc_common (
diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v
index c9c3d9e3a..42ac81421 100644
--- a/library/axi_ad9361/axi_ad9361_tx.v
+++ b/library/axi_ad9361/axi_ad9361_tx.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -47,7 +47,7 @@ module axi_ad9361_tx (
   dac_clksel,
   dac_r1_mode,
   adc_data,
-  
+
   // delay interface
 
   up_dld,
@@ -101,6 +101,7 @@ module axi_ad9361_tx (
 
   parameter   DATAPATH_DISABLE = 0;
   parameter   ID = 0;
+  parameter   R1_MODE_EN = 0;
 
   // dac interface
 
@@ -110,7 +111,7 @@ module axi_ad9361_tx (
   output          dac_clksel;
   output          dac_r1_mode;
   input   [47:0]  adc_data;
-  
+
   // delay interface
 
   output  [15:0]  up_dld;
@@ -233,7 +234,7 @@ module axi_ad9361_tx (
   end
 
   // dac channel
-  
+
   axi_ad9361_tx_channel #(
     .CHANNEL_ID (0),
     .Q_OR_I_N (0),
@@ -262,7 +263,7 @@ module axi_ad9361_tx (
     .up_rack (up_rack_s[0]));
 
   // dac channel
-  
+
   axi_ad9361_tx_channel #(
     .CHANNEL_ID (1),
     .Q_OR_I_N (1),
@@ -290,8 +291,11 @@ module axi_ad9361_tx (
     .up_rdata (up_rdata_s[1]),
     .up_rack (up_rack_s[1]));
 
+  generate
+  if (R1_MODE_EN == 0) begin
+
   // dac channel
-  
+
   axi_ad9361_tx_channel #(
     .CHANNEL_ID (2),
     .Q_OR_I_N (0),
@@ -320,7 +324,7 @@ module axi_ad9361_tx (
     .up_rack (up_rack_s[2]));
 
   // dac channel
-  
+
   axi_ad9361_tx_channel #(
     .CHANNEL_ID (3),
     .Q_OR_I_N (1),
@@ -348,6 +352,9 @@ module axi_ad9361_tx (
     .up_rdata (up_rdata_s[3]),
     .up_rack (up_rack_s[3]));
 
+  end
+  endgenerate
+
   // dac common processor interface
 
   up_dac_common #(.ID (ID)) i_up_dac_common (
@@ -387,7 +394,7 @@ module axi_ad9361_tx (
     .up_raddr (up_raddr),
     .up_rdata (up_rdata_s[4]),
     .up_rack (up_rack_s[4]));
-  
+
   // dac delay control
 
   up_delay_cntrl #(.DATA_WIDTH(16), .BASE_ADDRESS(6'h12)) i_delay_cntrl (

From f4be0524b4f717f4163d710f3a434a7ef4ef8892 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 9 Sep 2016 18:04:41 +0300
Subject: [PATCH 458/972] altera/common: Add SERDES related modules

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 229 ++++++++++++++++++++
 library/altera/common/ad_serdes_clk.v       | 139 ++++++++++++
 library/altera/common/ad_serdes_in.v        | 142 ++++++++++++
 library/altera/common/ad_serdes_out.v       | 130 +++++++++++
 4 files changed, 640 insertions(+)
 create mode 100644 library/altera/alt_serdes/alt_serdes_hw.tcl
 create mode 100644 library/altera/common/ad_serdes_clk.v
 create mode 100644 library/altera/common/ad_serdes_in.v
 create mode 100644 library/altera/common/ad_serdes_out.v

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
new file mode 100644
index 000000000..e97b6281f
--- /dev/null
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -0,0 +1,229 @@
+
+package require -exact qsys 13.0
+source ../../scripts/adi_env.tcl
+source ../../scripts/adi_ip_alt.tcl
+
+set_module_property NAME util_serdes_clk
+set_module_property DESCRIPTION "A simple Altera IOPLL macro instance"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME util_serdes_clk
+set_module_property ELABORATION_CALLBACK p_util_serdes_clk
+
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
+set_fileset_property quartus_synth TOP_LEVEL ad_serdes_clk
+add_fileset_file  ad_serdes_clk.v  VERILOG PATH  $ad_hdl_dir/library/altera/common/ad_serdes_clk.v TOP_LEVEL_FILE
+
+add_parameter DEVICE_FAMILY STRING
+set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
+set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
+set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
+set_parameter_property DEVICE_FAMILY ENABLED false
+
+add_parameter MODE STRING 0
+set_parameter_property MODE DEFAULT_VALUE "TX"
+set_parameter_property MODE DISPLAY_NAME MODE
+set_parameter_property MODE TYPE STRING
+set_parameter_property MODE UNITS None
+set_parameter_property MODE HDL_PARAMETER true
+
+add_hdl_instance alt_clk altera_iopll
+set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {500.0}
+set_instance_parameter_value alt_clk {gui_use_locked} {1}
+set_instance_parameter_value alt_clk {gui_operation_mode} {lvds}
+set_instance_parameter_value alt_clk {gui_en_lvds_ports} {true}
+set_instance_parameter_value alt_clk {gui_number_of_clocks} {4}
+set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {1200.0}
+set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
+set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {180.0}
+set_instance_parameter_value alt_clk {gui_duty_cycle0} {50.0}
+set_instance_parameter_value alt_clk {gui_output_clock_frequency1} {150.0}
+set_instance_parameter_value alt_clk {gui_ps_units1} {degrees}
+set_instance_parameter_value alt_clk {gui_phase_shift_deg1} {315.0}
+set_instance_parameter_value alt_clk {gui_duty_cycle1} {12.5}
+set_instance_parameter_value alt_clk {gui_output_clock_frequency2} {150.0}
+set_instance_parameter_value alt_clk {gui_ps_units2} {degrees}
+set_instance_parameter_value alt_clk {gui_phase_shift_deg2} {22.5}
+set_instance_parameter_value alt_clk {gui_duty_cycle2} {50.0}
+set_instance_parameter_value alt_clk {gui_output_clock_frequency3} {600.0}
+set_instance_parameter_value alt_clk {gui_ps_units3} {degrees}
+set_instance_parameter_value alt_clk {gui_phase_shift_deg3} {90}
+set_instance_parameter_value alt_clk {gui_duty_cycle3} {50.0}
+set_instance_parameter_value alt_clk {system_info_device_family} DEVICE_FAMILY
+set_instance_parameter_value alt_clk {gui_en_reconf} {true}
+
+# input clock and reset
+
+ad_alt_intf clock clk Output 1
+ad_alt_intf clock div_clk Output 1
+ad_alt_intf clock loaden Output 1
+
+add_interface serdes_clk clock end
+add_interface_port serdes_clk clk_in_p clk Input 1
+
+add_interface serdes_rst reset end
+set_interface_property serdes_rst associatedClock serdes_clk
+add_interface_port serdes_rst mmcm_rst reset Input 1
+
+# updates
+
+proc p_util_serdes_clk {} {
+
+  set serdes_clk_mode [get_parameter_value MODE]
+
+  if {$serdes_clk_mode eq "TX"} {
+    set_instance_parameter_value alt_clk {gui_en_phout_ports} {false}
+  } elseif {$serdes_clk_mode eq "RX"} {
+    set_instance_parameter_value alt_clk {gui_en_phout_ports} {true}
+    ad_alt_intf signal phase   Output 8
+  } else {
+    set_instance_parameter_value alt_clk {gui_en_phout_ports} {false}
+  }
+
+}
+
+
+package require -exact qsys 13.0
+source ../../scripts/adi_env.tcl
+source ../../scripts/adi_ip_alt.tcl
+
+set_module_property NAME util_serdes_in
+set_module_property DESCRIPTION "A simple Altera LVDS Serdes macro instance in rx mode"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME util_serdes_in
+
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
+set_fileset_property quartus_synth TOP_LEVEL ad_serdes_in
+add_fileset_file  ad_serdes_in.v  VERILOG PATH  $ad_hdl_dir/library/altera/common/ad_serdes_in.v TOP_LEVEL_FILE
+
+add_parameter DEVICE_FAMILY STRING
+set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
+set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
+set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
+set_parameter_property DEVICE_FAMILY ENABLED false
+
+add_parameter DATA_WIDTH STRING
+set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
+set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
+set_parameter_property DATA_WIDTH TYPE INTEGER
+set_parameter_property DATA_WIDTH UNITS None
+set_parameter_property DATA_WIDTH HDL_PARAMETER true
+
+add_hdl_instance alt_serdes_in altera_lvds
+set_instance_parameter_value alt_serdes_in {DATA_RATE} {600.0}
+set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo}
+set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
+set_instance_parameter_value alt_serdes_in {J_FACTOR} {8}
+set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} {100}
+set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
+set_instance_parameter_value alt_serdes_in {TX_EXPORT_CORECLOCK} {false}
+set_instance_parameter_value alt_serdes_in {TX_USE_OUTCLOCK} {false}
+set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
+set_instance_parameter_value alt_serdes_in {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
+
+# input clock and reset
+
+add_interface fast_clk clock end
+add_interface_port fast_clk clk clk Input 1
+set_interface_property fast_clk associatedReset serdes_rst
+
+add_interface serdes_rst reset end
+add_interface_port serdes_rst rst reset Input 1
+set_interface_property serdes_rst associatedClock fast_clk
+
+add_interface div_clk clock end
+add_interface_port div_clk div_clk clk Input 1
+set_interface_property div_clk associatedReset none
+
+add_interface loaden clock end
+add_interface_port loaden loaden clk Input 1
+set_interface_property loaden associatedReset none
+
+add_interface parallel_data   conduit end
+add_interface_port parallel_data  data_s0 data0 output DATA_WIDTH
+add_interface_port parallel_data  data_s1 data1 output DATA_WIDTH
+add_interface_port parallel_data  data_s2 data2 output DATA_WIDTH
+add_interface_port parallel_data  data_s3 data3 output DATA_WIDTH
+add_interface_port parallel_data  data_s4 data4 output DATA_WIDTH
+add_interface_port parallel_data  data_s5 data5 output DATA_WIDTH
+add_interface_port parallel_data  data_s6 data6 output DATA_WIDTH
+add_interface_port parallel_data  data_s7 data7 output DATA_WIDTH
+
+set_interface_property parallel_data associatedClock div_clk
+set_interface_property parallel_data associatedReset none
+
+add_interface serial_data   conduit end
+add_interface_port serial_data  data_out_p data_p output 1
+add_interface_port serial_data  data_out_n data_n output 1
+
+package require -exact qsys 13.0
+source ../../scripts/adi_env.tcl
+source ../../scripts/adi_ip_alt.tcl
+
+set_module_property NAME util_serdes_out
+set_module_property DESCRIPTION "A simple Altera LVDS Serdes macro instance in tx mode"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME util_serdes_out
+
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
+set_fileset_property quartus_synth TOP_LEVEL ad_serdes_out
+add_fileset_file  ad_serdes_out.v  VERILOG PATH  $ad_hdl_dir/library/altera/common/ad_serdes_out.v TOP_LEVEL_FILE
+
+add_parameter DEVICE_FAMILY STRING
+set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
+set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
+set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
+set_parameter_property DEVICE_FAMILY ENABLED false
+
+add_parameter DATA_WIDTH STRING
+set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
+set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
+set_parameter_property DATA_WIDTH TYPE INTEGER
+set_parameter_property DATA_WIDTH UNITS None
+set_parameter_property DATA_WIDTH HDL_PARAMETER true
+
+add_parameter DEVICE_TYPE STRING
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
+add_hdl_instance alt_serdes_out altera_lvds
+set_instance_parameter_value alt_serdes_out {DATA_RATE} {600.0}
+set_instance_parameter_value alt_serdes_out {MODE} {TX}
+set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
+set_instance_parameter_value alt_serdes_out {J_FACTOR} {8}
+set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} {100}
+set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
+set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
+set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
+set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
+set_instance_parameter_value alt_serdes_out {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
+
+# input clock and reset
+
+ad_alt_intf clock clk Input 1
+ad_alt_intf clock div_clk Input 1
+ad_alt_intf clock loaden Input 1
+ad_alt_intf reset rst Input 1
+
+add_interface parallel_data   conduit end
+add_interface_port parallel_data  data_s0 data0 input DATA_WIDTH
+add_interface_port parallel_data  data_s1 data1 input DATA_WIDTH
+add_interface_port parallel_data  data_s2 data2 input DATA_WIDTH
+add_interface_port parallel_data  data_s3 data3 input DATA_WIDTH
+add_interface_port parallel_data  data_s4 data4 input DATA_WIDTH
+add_interface_port parallel_data  data_s5 data5 input DATA_WIDTH
+add_interface_port parallel_data  data_s6 data6 input DATA_WIDTH
+add_interface_port parallel_data  data_s7 data7 input DATA_WIDTH
+
+set_interface_property parallel_data associatedClock div_clk
+set_interface_property parallel_data associatedReset none
+
+add_interface serial_data   conduit end
+add_interface_port serial_data  data_out_p data_p output 1
+add_interface_port serial_data  data_out_n data_n output 1
+
diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
new file mode 100644
index 000000000..ffcacec85
--- /dev/null
+++ b/library/altera/common/ad_serdes_clk.v
@@ -0,0 +1,139 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// serial data output interface: serdes(x8)
+
+`timescale 1ps/1ps
+
+module ad_serdes_clk (
+
+  // clock and divided clock
+
+  mmcm_rst,
+  clk_in_p,
+  clk_in_n,
+
+  clk,
+  div_clk,
+  out_clk,
+  loaden,
+  phase,
+
+  // drp interface
+
+  up_clk,
+  up_rstn,
+  up_drp_sel,
+  up_drp_wr,
+  up_drp_addr,
+  up_drp_wdata,
+  up_drp_rdata,
+  up_drp_ready,
+  up_drp_locked);
+
+  // parameters
+
+  parameter       MODE = "TX";
+
+  // clock and divided clock
+
+  input           mmcm_rst;
+  input           clk_in_p;
+  input           clk_in_n;
+
+  output          clk;
+  output          div_clk;
+  output          out_clk;
+  output          loaden;
+  output  [ 7:0]  phase;
+
+  // drp interface
+
+  input           up_clk;
+  input           up_rstn;
+  input           up_drp_sel;
+  input           up_drp_wr;
+  input   [11:0]  up_drp_addr;
+  input   [15:0]  up_drp_wdata;
+  output  [15:0]  up_drp_rdata;
+  output          up_drp_ready;
+  output          up_drp_locked;
+
+  wire            locked;
+
+  // ground the unused outputs
+
+  assign up_drp_rdata = 15'b0;
+  assign up_drp_ready = 1'b0;
+  assign up_drp_locked = locked;
+
+  generate if (MODE == "TX") begin
+
+    assign phase = 8'h0;
+
+    alt_clk i_alt_clk (
+      .locked (locked),         // locked.export
+      .outclk_0 (clk),          // outclk0.clk
+      .outclk_1 (loaden),       // outclk1.clk
+      .outclk_2 (div_clk),      // outclk2.clk
+      .outclk_3 (out_clk),      // outclk3.clk
+      .reconfig_from_pll (),    // reconfig_from_pll.reconfig_from_pll
+      .reconfig_to_pll (),      // reconfig_to_pll.reconfig_to_pll
+      .refclk (clk_in_p),       // refclk.clk
+      .rst (mmcm_rst)           // reset.reset
+    );
+
+    // TODO: Add Altera PLL Reconfig IP
+
+  end else begin
+
+  alt_clk i_alt_clk (
+    .locked (locked),         // locked.export
+    .outclk_0 (clk),          // outclk0.clk
+    .outclk_1 (loaden),       // outclk1.clk
+    .outclk_2 (div_clk),      // outclk2.clk
+    .outclk_3 (out_clk),      // outclk3.clk
+    .reconfig_from_pll (),    // reconfig_from_pll.reconfig_from_pll
+    .reconfig_to_pll (),      // reconfig_to_pll.reconfig_to_pll
+    .phout (phase),
+    .refclk (clk_in_p),       // refclk.clk
+    .rst (mmcm_rst)           // reset.reset
+  );
+
+  end
+  endgenerate
+
+endmodule
diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
new file mode 100644
index 000000000..57e9da911
--- /dev/null
+++ b/library/altera/common/ad_serdes_in.v
@@ -0,0 +1,142 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+`timescale 1ps/1ps
+
+module ad_serdes_in (
+
+  // reset and clocks
+
+  rst,
+  clk,
+  div_clk,
+  loaden,
+  clk_phase,
+
+  // data interface
+
+  data_s0,
+  data_s1,
+  data_s2,
+  data_s3,
+  data_s4,
+  data_s5,
+  data_s6,
+  data_s7,
+  data_in_p,
+  data_in_n,
+
+  // delay-data interface
+
+  up_clk,
+  up_dld,
+  up_dwdata,
+  up_drdata,
+
+  // delay-control interface
+
+  delay_clk,
+  delay_rst,
+  delay_locked);
+
+  // parameters
+
+  parameter       DEVICE_TYPE  = 0;
+
+  // reset and clocks
+
+  input           rst;
+  input           clk;
+  input           div_clk;
+  input           loaden;
+  input           clk_phase;
+
+  // data interface
+
+  output          data_s0;
+  output          data_s1;
+  output          data_s2;
+  output          data_s3;
+  output          data_s4;
+  output          data_s5;
+  output          data_s6;
+  output          data_s7;
+  input           data_in_p;
+  input           data_in_n;
+
+  // delay-data interface
+
+  input           up_clk;
+  input           up_dld;
+  input    [ 4:0] up_dwdata;
+  output   [ 4:0] up_drdata;
+
+  // delay-control interface
+
+  input           delay_clk;
+  input           delay_rst;
+  output          delay_locked;
+
+  // internal signals
+
+  wire     [ 7:0] data_out_s;
+
+  assign data_s0 = data_out_s[0];
+  assign data_s1 = data_out_s[1];
+  assign data_s2 = data_out_s[2];
+  assign data_s2 = data_out_s[2];
+  assign data_s3 = data_out_s[3];
+  assign data_s4 = data_out_s[4];
+  assign data_s5 = data_out_s[5];
+  assign data_s6 = data_out_s[6];
+  assign data_s7 = data_out_s[7];
+
+  altera_lvds_in i_altera_lvds_in (
+    .ext_coreclock (div_clk),       //  ext_coreclock.export
+    .ext_fclk (clk),                //  ext_fclk.export
+    .ext_loaden (loaden),           //  ext_loaden.export
+    .ext_pll_locked (),             //  ext_pll_locked.export
+    .ext_vcoph (clk_phase),         //  ext_vcoph.export
+    .rx_dpa_locked (delay_locked),  //  rx_dpa_locked.export
+    .rx_in (data_in_p),             //  rx_in.export
+    .rx_out (data_out_s)            //  rx_out.export
+  );
+
+endmodule
+
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
new file mode 100644
index 000000000..e89c8ea05
--- /dev/null
+++ b/library/altera/common/ad_serdes_out.v
@@ -0,0 +1,130 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// serial data output interface: serdes(x8)
+
+`timescale 1ps/1ps
+
+module ad_serdes_out (
+
+  // reset and clocks
+
+  rst,
+  clk,
+  div_clk,
+  loaden,
+
+  // data interface
+
+  data_s0,
+  data_s1,
+  data_s2,
+  data_s3,
+  data_s4,
+  data_s5,
+  data_s6,
+  data_s7,
+  data_out_p,
+  data_out_n);
+
+  // parameters
+
+  parameter   DEVICE_TYPE = 0;
+  parameter   DATA_WIDTH = 16;
+
+  localparam  DW = DATA_WIDTH - 1;
+
+  // reset and clocks
+
+  input           rst;
+  input           clk;
+  input           div_clk;
+  input           loaden;
+
+  // data interface
+
+  input   [DW:0]  data_s0;
+  input   [DW:0]  data_s1;
+  input   [DW:0]  data_s2;
+  input   [DW:0]  data_s3;
+  input   [DW:0]  data_s4;
+  input   [DW:0]  data_s5;
+  input   [DW:0]  data_s6;
+  input   [DW:0]  data_s7;
+  output  [DW:0]  data_out_p;
+  output  [DW:0]  data_out_n;
+
+  // internal signals
+
+  wire    [DW:0]  data_out_s;
+  wire    [ 7:0]  data_in_s[DW:0];
+
+  // instantiations
+
+  assign data_out_p = data_out_s;
+  assign data_out_n = 0;   // differential pair will be defined by the Pin Planner
+
+  genvar l_inst;
+  generate
+  for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data
+
+    assign data_in_s[l_inst] = {data_s7[l_inst],
+                                data_s6[l_inst],
+                                data_s5[l_inst],
+                                data_s4[l_inst],
+                                data_s3[l_inst],
+                                data_s2[l_inst],
+                                data_s1[l_inst],
+                                data_s0[l_inst]};
+
+    alt_serdes_out i_alt_serdes_out (
+      .ext_coreclock (div_clk),         // ext_coreclock.export
+      .ext_fclk (clk),                  // ext_fclk.export
+      .ext_loaden (loaden),             // ext_loaden.export
+      .tx_in (data_in_s[l_inst]),       // tx_in.export
+      .tx_out (data_out_s[l_inst])      // tx_out.export
+    );
+
+  end
+  endgenerate
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+

From 9e0c39a71bc804b3de6b38d3a25fe9e01dc02673 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 10:30:28 -0400
Subject: [PATCH 459/972] alt_serdes_clk- changes

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 319 +++++++-------------
 library/altera/common/ad_serdes_clk.v       | 178 ++++++-----
 2 files changed, 207 insertions(+), 290 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index e97b6281f..cdc6b8f37 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -1,229 +1,130 @@
 
-package require -exact qsys 13.0
-source ../../scripts/adi_env.tcl
-source ../../scripts/adi_ip_alt.tcl
+package require -exact qsys 14.0
 
-set_module_property NAME util_serdes_clk
-set_module_property DESCRIPTION "A simple Altera IOPLL macro instance"
+set_module_property NAME alt_serdes
+set_module_property DESCRIPTION "Altera SERDES"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME util_serdes_clk
-set_module_property ELABORATION_CALLBACK p_util_serdes_clk
+set_module_property DISPLAY_NAME alt_serdes
+set_module_property COMPOSITION_CALLBACK p_alt_serdes
 
-add_fileset quartus_synth QUARTUS_SYNTH "" ""
-set_fileset_property quartus_synth TOP_LEVEL ad_serdes_clk
-add_fileset_file  ad_serdes_clk.v  VERILOG PATH  $ad_hdl_dir/library/altera/common/ad_serdes_clk.v TOP_LEVEL_FILE
+# parameters
 
-add_parameter DEVICE_FAMILY STRING
-set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
-set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
-set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
-set_parameter_property DEVICE_FAMILY ENABLED false
-
-add_parameter MODE STRING 0
-set_parameter_property MODE DEFAULT_VALUE "TX"
+add_parameter MODE STRING "CLK"
 set_parameter_property MODE DISPLAY_NAME MODE
 set_parameter_property MODE TYPE STRING
 set_parameter_property MODE UNITS None
-set_parameter_property MODE HDL_PARAMETER true
+set_parameter_property MODE HDL_PARAMETER false
+set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"}
 
-add_hdl_instance alt_clk altera_iopll
-set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {500.0}
-set_instance_parameter_value alt_clk {gui_use_locked} {1}
-set_instance_parameter_value alt_clk {gui_operation_mode} {lvds}
-set_instance_parameter_value alt_clk {gui_en_lvds_ports} {true}
-set_instance_parameter_value alt_clk {gui_number_of_clocks} {4}
-set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {1200.0}
-set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
-set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {180.0}
-set_instance_parameter_value alt_clk {gui_duty_cycle0} {50.0}
-set_instance_parameter_value alt_clk {gui_output_clock_frequency1} {150.0}
-set_instance_parameter_value alt_clk {gui_ps_units1} {degrees}
-set_instance_parameter_value alt_clk {gui_phase_shift_deg1} {315.0}
-set_instance_parameter_value alt_clk {gui_duty_cycle1} {12.5}
-set_instance_parameter_value alt_clk {gui_output_clock_frequency2} {150.0}
-set_instance_parameter_value alt_clk {gui_ps_units2} {degrees}
-set_instance_parameter_value alt_clk {gui_phase_shift_deg2} {22.5}
-set_instance_parameter_value alt_clk {gui_duty_cycle2} {50.0}
-set_instance_parameter_value alt_clk {gui_output_clock_frequency3} {600.0}
-set_instance_parameter_value alt_clk {gui_ps_units3} {degrees}
-set_instance_parameter_value alt_clk {gui_phase_shift_deg3} {90}
-set_instance_parameter_value alt_clk {gui_duty_cycle3} {50.0}
-set_instance_parameter_value alt_clk {system_info_device_family} DEVICE_FAMILY
-set_instance_parameter_value alt_clk {gui_en_reconf} {true}
+add_parameter DDR_OR_SDR_N INTEGER 1
+set_parameter_property DDR_OR_SDR_N DISPLAY_NAME DDR_OR_SDR_N
+set_parameter_property DDR_OR_SDR_N TYPE INTEGER
+set_parameter_property DDR_OR_SDR_N UNITS None
+set_parameter_property DDR_OR_SDR_N HDL_PARAMETER false
+set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1}
 
-# input clock and reset
+add_parameter SERDES_FACTOR INTEGER 8
+set_parameter_property SERDES_FACTOR DISPLAY_NAME SERDES_FACTOR
+set_parameter_property SERDES_FACTOR TYPE INTEGER
+set_parameter_property SERDES_FACTOR UNITS None
+set_parameter_property SERDES_FACTOR HDL_PARAMETER false
+set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
 
-ad_alt_intf clock clk Output 1
-ad_alt_intf clock div_clk Output 1
-ad_alt_intf clock loaden Output 1
+add_parameter CLKIN_FREQUENCY FLOAT 500.0
+set_parameter_property CLKIN_FREQUENCY DISPLAY_NAME CLKIN_FREQUENCY
+set_parameter_property CLKIN_FREQUENCY TYPE FLOAT
+set_parameter_property CLKIN_FREQUENCY UNITS None
+set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
+set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
 
-add_interface serdes_clk clock end
-add_interface_port serdes_clk clk_in_p clk Input 1
+proc p_alt_serdes {} {
 
-add_interface serdes_rst reset end
-set_interface_property serdes_rst associatedClock serdes_clk
-add_interface_port serdes_rst mmcm_rst reset Input 1
+  set m_mode [get_parameter_value "MODE"]
+  set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
+  set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
+  set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
 
-# updates
-
-proc p_util_serdes_clk {} {
-
-  set serdes_clk_mode [get_parameter_value MODE]
-
-  if {$serdes_clk_mode eq "TX"} {
-    set_instance_parameter_value alt_clk {gui_en_phout_ports} {false}
-  } elseif {$serdes_clk_mode eq "RX"} {
-    set_instance_parameter_value alt_clk {gui_en_phout_ports} {true}
-    ad_alt_intf signal phase   Output 8
-  } else {
-    set_instance_parameter_value alt_clk {gui_en_phout_ports} {false}
+  set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
+  set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
+  set m_ls_phase 315.0
+  if {$m_serdes_factor == 4} {
+    set m_ls_phase 270.0
   }
 
+  if {$m_mode == "CLK"} {
+
+    add_instance alt_serdes_pll altera_iopll
+    set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
+    set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
+    set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
+    set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
+    set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
+    set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ls_phase
+    set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} {12.5}
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
+    add_interface rst reset sink
+    set_interface_property rst EXPORT_OF alt_serdes_pll.reset
+    add_interface ref_clk clock sink
+    set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
+    add_interface locked conduit end
+    set_interface_property locked EXPORT_OF alt_serdes_pll.locked
+    add_interface hs_phase conduit end
+    set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
+    add_interface hs_clk conduit end
+    set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
+    add_interface loaden conduit end
+    set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
+    add_interface ls_clk clock source
+    set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
+
+    add_instance alt_serdes_pll_reconfig altera_pll_reconfig
+    add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
+    add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
+    add_interface drp_clk clock sink
+    set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
+    add_interface drp_rstn reset sink
+    set_interface_property drp_rstn EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
+    add_interface pll_reconfig avalon slave
+    set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
+  }
+
+  if {$m_mode == "IN"} {
+
+    add_hdl_instance alt_serdes_in altera_lvds
+    set_instance_parameter_value alt_serdes_in {DATA_RATE} {600.0}
+    set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo}
+    set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
+    set_instance_parameter_value alt_serdes_in {J_FACTOR} {8}
+    set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} {100}
+    set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
+    set_instance_parameter_value alt_serdes_in {TX_EXPORT_CORECLOCK} {false}
+    set_instance_parameter_value alt_serdes_in {TX_USE_OUTCLOCK} {false}
+    set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
+    set_instance_parameter_value alt_serdes_in {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
+  }
+
+  if {$m_mode == "OUT"} {
+
+    add_hdl_instance alt_serdes_out altera_lvds
+    set_instance_parameter_value alt_serdes_out {DATA_RATE} {600.0}
+    set_instance_parameter_value alt_serdes_out {MODE} {TX}
+    set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
+    set_instance_parameter_value alt_serdes_out {J_FACTOR} {8}
+    set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} {100}
+    set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
+    set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
+    set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
+    set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
+    set_instance_parameter_value alt_serdes_out {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
+  }
 }
 
 
-package require -exact qsys 13.0
-source ../../scripts/adi_env.tcl
-source ../../scripts/adi_ip_alt.tcl
-
-set_module_property NAME util_serdes_in
-set_module_property DESCRIPTION "A simple Altera LVDS Serdes macro instance in rx mode"
-set_module_property VERSION 1.0
-set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME util_serdes_in
-
-add_fileset quartus_synth QUARTUS_SYNTH "" ""
-set_fileset_property quartus_synth TOP_LEVEL ad_serdes_in
-add_fileset_file  ad_serdes_in.v  VERILOG PATH  $ad_hdl_dir/library/altera/common/ad_serdes_in.v TOP_LEVEL_FILE
-
-add_parameter DEVICE_FAMILY STRING
-set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
-set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
-set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
-set_parameter_property DEVICE_FAMILY ENABLED false
-
-add_parameter DATA_WIDTH STRING
-set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
-set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
-set_parameter_property DATA_WIDTH TYPE INTEGER
-set_parameter_property DATA_WIDTH UNITS None
-set_parameter_property DATA_WIDTH HDL_PARAMETER true
-
-add_hdl_instance alt_serdes_in altera_lvds
-set_instance_parameter_value alt_serdes_in {DATA_RATE} {600.0}
-set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo}
-set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
-set_instance_parameter_value alt_serdes_in {J_FACTOR} {8}
-set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} {100}
-set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
-set_instance_parameter_value alt_serdes_in {TX_EXPORT_CORECLOCK} {false}
-set_instance_parameter_value alt_serdes_in {TX_USE_OUTCLOCK} {false}
-set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
-set_instance_parameter_value alt_serdes_in {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
-
-# input clock and reset
-
-add_interface fast_clk clock end
-add_interface_port fast_clk clk clk Input 1
-set_interface_property fast_clk associatedReset serdes_rst
-
-add_interface serdes_rst reset end
-add_interface_port serdes_rst rst reset Input 1
-set_interface_property serdes_rst associatedClock fast_clk
-
-add_interface div_clk clock end
-add_interface_port div_clk div_clk clk Input 1
-set_interface_property div_clk associatedReset none
-
-add_interface loaden clock end
-add_interface_port loaden loaden clk Input 1
-set_interface_property loaden associatedReset none
-
-add_interface parallel_data   conduit end
-add_interface_port parallel_data  data_s0 data0 output DATA_WIDTH
-add_interface_port parallel_data  data_s1 data1 output DATA_WIDTH
-add_interface_port parallel_data  data_s2 data2 output DATA_WIDTH
-add_interface_port parallel_data  data_s3 data3 output DATA_WIDTH
-add_interface_port parallel_data  data_s4 data4 output DATA_WIDTH
-add_interface_port parallel_data  data_s5 data5 output DATA_WIDTH
-add_interface_port parallel_data  data_s6 data6 output DATA_WIDTH
-add_interface_port parallel_data  data_s7 data7 output DATA_WIDTH
-
-set_interface_property parallel_data associatedClock div_clk
-set_interface_property parallel_data associatedReset none
-
-add_interface serial_data   conduit end
-add_interface_port serial_data  data_out_p data_p output 1
-add_interface_port serial_data  data_out_n data_n output 1
-
-package require -exact qsys 13.0
-source ../../scripts/adi_env.tcl
-source ../../scripts/adi_ip_alt.tcl
-
-set_module_property NAME util_serdes_out
-set_module_property DESCRIPTION "A simple Altera LVDS Serdes macro instance in tx mode"
-set_module_property VERSION 1.0
-set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME util_serdes_out
-
-add_fileset quartus_synth QUARTUS_SYNTH "" ""
-set_fileset_property quartus_synth TOP_LEVEL ad_serdes_out
-add_fileset_file  ad_serdes_out.v  VERILOG PATH  $ad_hdl_dir/library/altera/common/ad_serdes_out.v TOP_LEVEL_FILE
-
-add_parameter DEVICE_FAMILY STRING
-set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
-set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
-set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
-set_parameter_property DEVICE_FAMILY ENABLED false
-
-add_parameter DATA_WIDTH STRING
-set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
-set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
-set_parameter_property DATA_WIDTH TYPE INTEGER
-set_parameter_property DATA_WIDTH UNITS None
-set_parameter_property DATA_WIDTH HDL_PARAMETER true
-
-add_parameter DEVICE_TYPE STRING
-set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
-set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
-set_parameter_property DEVICE_TYPE TYPE INTEGER
-set_parameter_property DEVICE_TYPE UNITS None
-set_parameter_property DEVICE_TYPE HDL_PARAMETER true
-
-add_hdl_instance alt_serdes_out altera_lvds
-set_instance_parameter_value alt_serdes_out {DATA_RATE} {600.0}
-set_instance_parameter_value alt_serdes_out {MODE} {TX}
-set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
-set_instance_parameter_value alt_serdes_out {J_FACTOR} {8}
-set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} {100}
-set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
-set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
-set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
-set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
-set_instance_parameter_value alt_serdes_out {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
-
-# input clock and reset
-
-ad_alt_intf clock clk Input 1
-ad_alt_intf clock div_clk Input 1
-ad_alt_intf clock loaden Input 1
-ad_alt_intf reset rst Input 1
-
-add_interface parallel_data   conduit end
-add_interface_port parallel_data  data_s0 data0 input DATA_WIDTH
-add_interface_port parallel_data  data_s1 data1 input DATA_WIDTH
-add_interface_port parallel_data  data_s2 data2 input DATA_WIDTH
-add_interface_port parallel_data  data_s3 data3 input DATA_WIDTH
-add_interface_port parallel_data  data_s4 data4 input DATA_WIDTH
-add_interface_port parallel_data  data_s5 data5 input DATA_WIDTH
-add_interface_port parallel_data  data_s6 data6 input DATA_WIDTH
-add_interface_port parallel_data  data_s7 data7 input DATA_WIDTH
-
-set_interface_property parallel_data associatedClock div_clk
-set_interface_property parallel_data associatedReset none
-
-add_interface serial_data   conduit end
-add_interface_port serial_data  data_out_p data_p output 1
-add_interface_port serial_data  data_out_n data_n output 1
-
diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
index ffcacec85..b417627d7 100644
--- a/library/altera/common/ad_serdes_clk.v
+++ b/library/altera/common/ad_serdes_clk.v
@@ -42,98 +42,114 @@ module ad_serdes_clk (
 
   // clock and divided clock
 
-  mmcm_rst,
-  clk_in_p,
-  clk_in_n,
+  input           rst,
+  input           clk_in_p,
+  input           clk_in_n,
 
-  clk,
-  div_clk,
-  out_clk,
-  loaden,
-  phase,
+  output          clk,
+  output          div_clk,
+  output          out_clk,
+  output          loaden,
+  output  [ 7:0]  phase,
 
   // drp interface
 
-  up_clk,
-  up_rstn,
-  up_drp_sel,
-  up_drp_wr,
-  up_drp_addr,
-  up_drp_wdata,
-  up_drp_rdata,
-  up_drp_ready,
-  up_drp_locked);
+  input           up_clk,
+  input           up_rstn,
+  input           up_drp_sel,
+  input           up_drp_wr,
+  input   [11:0]  up_drp_addr,
+  input   [31:0]  up_drp_wdata,
+  output  [31:0]  up_drp_rdata,
+  output          up_drp_ready,
+  output          up_drp_locked);
 
-  // parameters
+  // internal registers
 
-  parameter       MODE = "TX";
+  reg             up_drp_sel_int = 'd0;
+  reg             up_drp_rd_int = 'd0;
+  reg             up_drp_wr_int = 'd0;
+  reg     [ 8:0]  up_drp_addr_int = 'd0;
+  reg     [31:0]  up_drp_wdata_int = 'd0;
+  reg     [31:0]  up_drp_rdata_int = 'd0;
+  reg             up_drp_ready_int = 'd0;
+  reg             up_drp_locked_int_m = 'd0;
+  reg             up_drp_locked_int = 'd0;
 
-  // clock and divided clock
+  // internal signals
 
-  input           mmcm_rst;
-  input           clk_in_p;
-  input           clk_in_n;
+  wire    [31:0]  up_drp_rdata_int_s,
+  wire            up_drp_busy_int_s;
+  wire            up_drp_locked_int_s;
 
-  output          clk;
-  output          div_clk;
-  output          out_clk;
-  output          loaden;
-  output  [ 7:0]  phase;
+  // defaults
 
-  // drp interface
-
-  input           up_clk;
-  input           up_rstn;
-  input           up_drp_sel;
-  input           up_drp_wr;
-  input   [11:0]  up_drp_addr;
-  input   [15:0]  up_drp_wdata;
-  output  [15:0]  up_drp_rdata;
-  output          up_drp_ready;
-  output          up_drp_locked;
-
-  wire            locked;
-
-  // ground the unused outputs
-
-  assign up_drp_rdata = 15'b0;
-  assign up_drp_ready = 1'b0;
-  assign up_drp_locked = locked;
-
-  generate if (MODE == "TX") begin
-
-    assign phase = 8'h0;
-
-    alt_clk i_alt_clk (
-      .locked (locked),         // locked.export
-      .outclk_0 (clk),          // outclk0.clk
-      .outclk_1 (loaden),       // outclk1.clk
-      .outclk_2 (div_clk),      // outclk2.clk
-      .outclk_3 (out_clk),      // outclk3.clk
-      .reconfig_from_pll (),    // reconfig_from_pll.reconfig_from_pll
-      .reconfig_to_pll (),      // reconfig_to_pll.reconfig_to_pll
-      .refclk (clk_in_p),       // refclk.clk
-      .rst (mmcm_rst)           // reset.reset
-    );
-
-    // TODO: Add Altera PLL Reconfig IP
-
-  end else begin
-
-  alt_clk i_alt_clk (
-    .locked (locked),         // locked.export
-    .outclk_0 (clk),          // outclk0.clk
-    .outclk_1 (loaden),       // outclk1.clk
-    .outclk_2 (div_clk),      // outclk2.clk
-    .outclk_3 (out_clk),      // outclk3.clk
-    .reconfig_from_pll (),    // reconfig_from_pll.reconfig_from_pll
-    .reconfig_to_pll (),      // reconfig_to_pll.reconfig_to_pll
-    .phout (phase),
-    .refclk (clk_in_p),       // refclk.clk
-    .rst (mmcm_rst)           // reset.reset
-  );
+  assign out_clk = div_clk;
 
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_drp_sel_int <= 1'b0;
+      up_drp_rd_int <= 1'b0;
+      up_drp_wr_int <= 1'b0;
+      up_drp_addr_int <= 9'd0;
+      up_drp_wdata_int <= 32'd0;
+      up_drp_rdata_int <= 32'd0;
+      up_drp_ready_int <= 1'b0;
+      up_drp_locked_int_m <= 1'd0;
+      up_drp_locked_int <= 1'd0;
+    end else begin
+      if (up_drp_sel_int == 1'b1) begin
+        if (up_drp_busy_int_s == 1'b0) begin
+          up_drp_sel_int <= 1'b0;
+          up_drp_rd_int <= 1'b0;
+          up_drp_wr_int <= 1'b0;
+          up_drp_addr_int <= 9'd0;
+          up_drp_wdata_int <= 32'd0;
+          up_drp_rdata_int <= up_drp_rdata_int_s;
+          up_drp_ready_int <= 1'b1;
+        end
+      end else if (up_drp_sel == 1'b1) begin
+        up_drp_sel_int <= 1'b1;
+        up_drp_rd_int <= ~up_drp_wr;
+        up_drp_wr_int <= up_drp_wr;
+        up_drp_addr_int <= up_drp_addr[8:0];
+        up_drp_wdata_int <= up_drp_wdata;
+        up_drp_rdata_int <= 32'd0;
+        up_drp_ready_int <= 1'b0;
+      end else begin
+        up_drp_sel_int <= 1'b0;
+        up_drp_rd_int <= 1'b0;
+        up_drp_wr_int <= 1'b0;
+        up_drp_addr_int <= 9'd0;
+        up_drp_wdata_int <= 32'd0;
+        up_drp_rdata_int <= 32'd0;
+        up_drp_ready_int <= 1'b0;
+      end
+      up_drp_locked_int_m <= up_drp_locked_int_s;
+      up_drp_locked_int <= up_drp_locked_int_m;
+    end
   end
-  endgenerate
 
+  // instantiations (ip- hw.tcl must generate this core)
+
+  alt_serdes_clk_core i_core (
+    .rst_reset (rst),
+    .ref_clk_clk (clk_in_p),
+    .locked_export (up_drp_locked_int_s),
+    .hs_phase_phout (phase),
+    .hs_clk_lvds_clk (clk),
+    .loaden_loaden (loaden),
+    .ls_clk_clk (div_clk),
+    .drp_clk_clk (up_clk),
+    .drp_rstn_reset (up_rstn),
+    .pll_reconfig_waitrequest (up_drp_busy_int_s),
+    .pll_reconfig_read (up_drp_rd_int),
+    .pll_reconfig_write (up_drp_wr_int),
+    .pll_reconfig_readdata (up_drp_rdata_int_s),
+    .pll_reconfig_address (up_drp_addr_int),
+    .pll_reconfig_writedata (up_drp_wdata_int));
+  
 endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 2a34f9baa8a20320a36468d36ff0a8e323b99e9f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 11:45:23 -0400
Subject: [PATCH 460/972] alt-serdes, in & out

---
 library/altera/alt_serdes/alt_serdes_hw.tcl |  49 +++++---
 library/altera/common/ad_serdes_in.v        | 123 +++++++-------------
 library/altera/common/ad_serdes_out.v       |  96 ++++++---------
 3 files changed, 111 insertions(+), 157 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index cdc6b8f37..a9ec823ec 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -99,31 +99,52 @@ proc p_alt_serdes {} {
   if {$m_mode == "IN"} {
 
     add_hdl_instance alt_serdes_in altera_lvds
-    set_instance_parameter_value alt_serdes_in {DATA_RATE} {600.0}
     set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo}
     set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
-    set_instance_parameter_value alt_serdes_in {J_FACTOR} {8}
-    set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} {100}
-    set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
-    set_instance_parameter_value alt_serdes_in {TX_EXPORT_CORECLOCK} {false}
-    set_instance_parameter_value alt_serdes_in {TX_USE_OUTCLOCK} {false}
+    set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate
+    set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor
     set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
-    set_instance_parameter_value alt_serdes_in {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
+    set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency
+    set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
+    add_interface data_in conduit end
+    set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in
+    add_interface clk clock sink
+    set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk
+    add_interface loaden conduit end
+    set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden
+    add_interface div_clk clock sink
+    set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock
+    add_interface hs_phase conduit end
+    set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph
+    add_interface locked conduit end
+    set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked
+    add_interface data_s conduit end
+    set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out
+    add_interface delay_locked conduit end
+    set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked
   }
 
   if {$m_mode == "OUT"} {
 
     add_hdl_instance alt_serdes_out altera_lvds
-    set_instance_parameter_value alt_serdes_out {DATA_RATE} {600.0}
     set_instance_parameter_value alt_serdes_out {MODE} {TX}
     set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
-    set_instance_parameter_value alt_serdes_out {J_FACTOR} {8}
-    set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} {100}
-    set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
-    set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
-    set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
+    set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate
+    set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor
     set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
-    set_instance_parameter_value alt_serdes_out {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
+    set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
+    set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
+    set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
+    add_interface data_out conduit end
+    set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out
+    add_interface clk clock sink
+    set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk
+    add_interface loaden conduit end
+    set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden
+    add_interface div_clk clock sink
+    set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock
+    add_interface data_s conduit end
+    set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
   }
 }
 
diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 57e9da911..9b99895a8 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -35,108 +35,69 @@
 // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
+
 `timescale 1ps/1ps
 
 module ad_serdes_in (
 
   // reset and clocks
 
-  rst,
-  clk,
-  div_clk,
-  loaden,
-  clk_phase,
+  input           rst,
+  input           clk,
+  input           div_clk,
+  input           loaden,
+  input           hs_phase,
 
   // data interface
 
-  data_s0,
-  data_s1,
-  data_s2,
-  data_s3,
-  data_s4,
-  data_s5,
-  data_s6,
-  data_s7,
-  data_in_p,
-  data_in_n,
+  output          data_s0,
+  output          data_s1,
+  output          data_s2,
+  output          data_s3,
+  output          data_s4,
+  output          data_s5,
+  output          data_s6,
+  output          data_s7,
+  input           data_in_p,
+  input           data_in_n,
 
   // delay-data interface
 
-  up_clk,
-  up_dld,
-  up_dwdata,
-  up_drdata,
+  input           up_clk,
+  input           up_dld,
+  input    [ 4:0] up_dwdata,
+  output   [ 4:0] up_drdata,
 
   // delay-control interface
 
-  delay_clk,
-  delay_rst,
-  delay_locked);
+  input           delay_clk,
+  input           delay_rst,
+  output          delay_locked);
 
   // parameters
 
   parameter       DEVICE_TYPE  = 0;
 
-  // reset and clocks
+  // instantiations
 
-  input           rst;
-  input           clk;
-  input           div_clk;
-  input           loaden;
-  input           clk_phase;
-
-  // data interface
-
-  output          data_s0;
-  output          data_s1;
-  output          data_s2;
-  output          data_s3;
-  output          data_s4;
-  output          data_s5;
-  output          data_s6;
-  output          data_s7;
-  input           data_in_p;
-  input           data_in_n;
-
-  // delay-data interface
-
-  input           up_clk;
-  input           up_dld;
-  input    [ 4:0] up_dwdata;
-  output   [ 4:0] up_drdata;
-
-  // delay-control interface
-
-  input           delay_clk;
-  input           delay_rst;
-  output          delay_locked;
-
-  // internal signals
-
-  wire     [ 7:0] data_out_s;
-
-  assign data_s0 = data_out_s[0];
-  assign data_s1 = data_out_s[1];
-  assign data_s2 = data_out_s[2];
-  assign data_s2 = data_out_s[2];
-  assign data_s3 = data_out_s[3];
-  assign data_s4 = data_out_s[4];
-  assign data_s5 = data_out_s[5];
-  assign data_s6 = data_out_s[6];
-  assign data_s7 = data_out_s[7];
-
-  altera_lvds_in i_altera_lvds_in (
-    .ext_coreclock (div_clk),       //  ext_coreclock.export
-    .ext_fclk (clk),                //  ext_fclk.export
-    .ext_loaden (loaden),           //  ext_loaden.export
-    .ext_pll_locked (),             //  ext_pll_locked.export
-    .ext_vcoph (clk_phase),         //  ext_vcoph.export
-    .rx_dpa_locked (delay_locked),  //  rx_dpa_locked.export
-    .rx_in (data_in_p),             //  rx_in.export
-    .rx_out (data_out_s)            //  rx_out.export
-  );
+  alt_serdes_in_core i_core (
+    .data_in (data_in_p),
+    .clk (clk),
+    .loaden (loaden),
+    .div_clk (div_clk),
+    .hs_phase (hs_phase),
+    .locked (locked),
+    .data_s ({data_s7,
+              data_s6,
+              data_s5,
+              data_s4,
+              data_s3,
+              data_s2,
+              data_s1,
+              data_s0}),
+    .delay_locked (delay_locked));
 
 endmodule
 
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index e89c8ea05..45ccc4036 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 // serial data output interface: serdes(x8)
 
 `timescale 1ps/1ps
@@ -44,82 +42,56 @@ module ad_serdes_out (
 
   // reset and clocks
 
-  rst,
-  clk,
-  div_clk,
-  loaden,
+  input                       rst,
+  input                       clk,
+  input                       div_clk,
+  input                       loaden,
 
   // data interface
 
-  data_s0,
-  data_s1,
-  data_s2,
-  data_s3,
-  data_s4,
-  data_s5,
-  data_s6,
-  data_s7,
-  data_out_p,
-  data_out_n);
+  input   [(DATA_WIDTH-1):0]  data_s0,
+  input   [(DATA_WIDTH-1):0]  data_s1,
+  input   [(DATA_WIDTH-1):0]  data_s2,
+  input   [(DATA_WIDTH-1):0]  data_s3,
+  input   [(DATA_WIDTH-1):0]  data_s4,
+  input   [(DATA_WIDTH-1):0]  data_s5,
+  input   [(DATA_WIDTH-1):0]  data_s6,
+  input   [(DATA_WIDTH-1):0]  data_s7,
+  output  [(DATA_WIDTH-1):0]  data_out_p,
+  output  [(DATA_WIDTH-1):0]  data_out_n);
 
   // parameters
 
   parameter   DEVICE_TYPE = 0;
   parameter   DATA_WIDTH = 16;
 
-  localparam  DW = DATA_WIDTH - 1;
-
-  // reset and clocks
-
-  input           rst;
-  input           clk;
-  input           div_clk;
-  input           loaden;
-
-  // data interface
-
-  input   [DW:0]  data_s0;
-  input   [DW:0]  data_s1;
-  input   [DW:0]  data_s2;
-  input   [DW:0]  data_s3;
-  input   [DW:0]  data_s4;
-  input   [DW:0]  data_s5;
-  input   [DW:0]  data_s6;
-  input   [DW:0]  data_s7;
-  output  [DW:0]  data_out_p;
-  output  [DW:0]  data_out_n;
-
   // internal signals
 
-  wire    [DW:0]  data_out_s;
-  wire    [ 7:0]  data_in_s[DW:0];
+  wire    [(DATA_WIDTH-1):0]  data_out_s;
+  wire    [ 7:0]              data_in_s[(DATA_WIDTH-1):0];
+
+  // defaults
+
+  assign data_out_n = 'd0;
 
   // instantiations
 
-  assign data_out_p = data_out_s;
-  assign data_out_n = 0;   // differential pair will be defined by the Pin Planner
-
   genvar l_inst;
   generate
-  for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data
-
-    assign data_in_s[l_inst] = {data_s7[l_inst],
-                                data_s6[l_inst],
-                                data_s5[l_inst],
-                                data_s4[l_inst],
-                                data_s3[l_inst],
-                                data_s2[l_inst],
-                                data_s1[l_inst],
-                                data_s0[l_inst]};
-
-    alt_serdes_out i_alt_serdes_out (
-      .ext_coreclock (div_clk),         // ext_coreclock.export
-      .ext_fclk (clk),                  // ext_fclk.export
-      .ext_loaden (loaden),             // ext_loaden.export
-      .tx_in (data_in_s[l_inst]),       // tx_in.export
-      .tx_out (data_out_s[l_inst])      // tx_out.export
-    );
-
+  for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
+  alt_serdes_out_core i_core (
+    .data_out (data_out_p[l_inst]),
+    .clk (clk),
+    .loaden (loaden),
+    .div_clk (div_clk),
+    .data_s ({data_s7[l_inst],
+      data_s6[l_inst],
+      data_s5[l_inst],
+      data_s4[l_inst],
+      data_s3[l_inst],
+      data_s2[l_inst],
+      data_s1[l_inst],
+      data_s0[l_inst]}));
   end
   endgenerate
 

From 5a309d8863aa64bdab2463d9c4243872a1965801 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 8 Sep 2016 13:06:58 -0400
Subject: [PATCH 461/972] avl_adxphy- split

---
 library/altera/avl_adxphy/avl_adxphy.v      | 884 ++++++++++++++++++++
 library/altera/avl_adxphy/avl_adxphy_hw.tcl | 114 +++
 2 files changed, 998 insertions(+)
 create mode 100644 library/altera/avl_adxphy/avl_adxphy.v
 create mode 100644 library/altera/avl_adxphy/avl_adxphy_hw.tcl

diff --git a/library/altera/avl_adxphy/avl_adxphy.v b/library/altera/avl_adxphy/avl_adxphy.v
new file mode 100644
index 000000000..eefcd0173
--- /dev/null
+++ b/library/altera/avl_adxphy/avl_adxphy.v
@@ -0,0 +1,884 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// AUTO GENERATED BY avl_adxphy.pl, DO NOT MODIFY!
+
+`timescale 1ns/1ps
+
+module avl_adxphy (
+
+  // rx-ip interface
+
+  output  [((NUM_OF_LANES* 1)-1):0]   rx_ip_locked,
+  output  [((NUM_OF_LANES* 1)-1):0]   rx_ip_cal_busy,
+  output  [((NUM_OF_LANES* 1)-1):0]   rx_ip_valid,
+  output  [((NUM_OF_LANES*32)-1):0]   rx_ip_data,
+  output  [((NUM_OF_LANES* 4)-1):0]   rx_ip_disperr,
+  output  [((NUM_OF_LANES* 4)-1):0]   rx_ip_deterr,
+  output  [((NUM_OF_LANES* 4)-1):0]   rx_ip_kchar,
+  output  [((NUM_OF_LANES* 1)-1):0]   rx_ip_full,
+  output  [((NUM_OF_LANES* 1)-1):0]   rx_ip_empty,
+  input   [((NUM_OF_LANES* 1)-1):0]   rx_ip_align_en,
+  input   [((NUM_OF_LANES* 1)-1):0]   rx_ip_lane_polarity,
+  input   [((NUM_OF_LANES* 1)-1):0]   rx_ip_lane_powerdown,
+  input                               rx_ip_bit_reversal,
+  input                               rx_ip_byte_reversal,
+
+  // rx-phy interface(s)
+
+  input                               rx_phy_locked_0,
+  input                               rx_phy_cal_busy_0,
+  input                               rx_phy_valid_0,
+  input   [31:0]                      rx_phy_data_0,
+  input   [ 3:0]                      rx_phy_disperr_0,
+  input   [ 3:0]                      rx_phy_deterr_0,
+  input   [ 3:0]                      rx_phy_kchar_0,
+  input                               rx_phy_full_0,
+  input                               rx_phy_empty_0,
+  output                              rx_phy_align_en_0,
+  output                              rx_phy_lane_polarity_0,
+  output                              rx_phy_lane_powerdown_0,
+  output                              rx_phy_bit_reversal_0,
+  output                              rx_phy_byte_reversal_0,
+
+  input                               rx_phy_locked_1,
+  input                               rx_phy_cal_busy_1,
+  input                               rx_phy_valid_1,
+  input   [31:0]                      rx_phy_data_1,
+  input   [ 3:0]                      rx_phy_disperr_1,
+  input   [ 3:0]                      rx_phy_deterr_1,
+  input   [ 3:0]                      rx_phy_kchar_1,
+  input                               rx_phy_full_1,
+  input                               rx_phy_empty_1,
+  output                              rx_phy_align_en_1,
+  output                              rx_phy_lane_polarity_1,
+  output                              rx_phy_lane_powerdown_1,
+  output                              rx_phy_bit_reversal_1,
+  output                              rx_phy_byte_reversal_1,
+
+  input                               rx_phy_locked_2,
+  input                               rx_phy_cal_busy_2,
+  input                               rx_phy_valid_2,
+  input   [31:0]                      rx_phy_data_2,
+  input   [ 3:0]                      rx_phy_disperr_2,
+  input   [ 3:0]                      rx_phy_deterr_2,
+  input   [ 3:0]                      rx_phy_kchar_2,
+  input                               rx_phy_full_2,
+  input                               rx_phy_empty_2,
+  output                              rx_phy_align_en_2,
+  output                              rx_phy_lane_polarity_2,
+  output                              rx_phy_lane_powerdown_2,
+  output                              rx_phy_bit_reversal_2,
+  output                              rx_phy_byte_reversal_2,
+
+  input                               rx_phy_locked_3,
+  input                               rx_phy_cal_busy_3,
+  input                               rx_phy_valid_3,
+  input   [31:0]                      rx_phy_data_3,
+  input   [ 3:0]                      rx_phy_disperr_3,
+  input   [ 3:0]                      rx_phy_deterr_3,
+  input   [ 3:0]                      rx_phy_kchar_3,
+  input                               rx_phy_full_3,
+  input                               rx_phy_empty_3,
+  output                              rx_phy_align_en_3,
+  output                              rx_phy_lane_polarity_3,
+  output                              rx_phy_lane_powerdown_3,
+  output                              rx_phy_bit_reversal_3,
+  output                              rx_phy_byte_reversal_3,
+
+  input                               rx_phy_locked_4,
+  input                               rx_phy_cal_busy_4,
+  input                               rx_phy_valid_4,
+  input   [31:0]                      rx_phy_data_4,
+  input   [ 3:0]                      rx_phy_disperr_4,
+  input   [ 3:0]                      rx_phy_deterr_4,
+  input   [ 3:0]                      rx_phy_kchar_4,
+  input                               rx_phy_full_4,
+  input                               rx_phy_empty_4,
+  output                              rx_phy_align_en_4,
+  output                              rx_phy_lane_polarity_4,
+  output                              rx_phy_lane_powerdown_4,
+  output                              rx_phy_bit_reversal_4,
+  output                              rx_phy_byte_reversal_4,
+
+  input                               rx_phy_locked_5,
+  input                               rx_phy_cal_busy_5,
+  input                               rx_phy_valid_5,
+  input   [31:0]                      rx_phy_data_5,
+  input   [ 3:0]                      rx_phy_disperr_5,
+  input   [ 3:0]                      rx_phy_deterr_5,
+  input   [ 3:0]                      rx_phy_kchar_5,
+  input                               rx_phy_full_5,
+  input                               rx_phy_empty_5,
+  output                              rx_phy_align_en_5,
+  output                              rx_phy_lane_polarity_5,
+  output                              rx_phy_lane_powerdown_5,
+  output                              rx_phy_bit_reversal_5,
+  output                              rx_phy_byte_reversal_5,
+
+  input                               rx_phy_locked_6,
+  input                               rx_phy_cal_busy_6,
+  input                               rx_phy_valid_6,
+  input   [31:0]                      rx_phy_data_6,
+  input   [ 3:0]                      rx_phy_disperr_6,
+  input   [ 3:0]                      rx_phy_deterr_6,
+  input   [ 3:0]                      rx_phy_kchar_6,
+  input                               rx_phy_full_6,
+  input                               rx_phy_empty_6,
+  output                              rx_phy_align_en_6,
+  output                              rx_phy_lane_polarity_6,
+  output                              rx_phy_lane_powerdown_6,
+  output                              rx_phy_bit_reversal_6,
+  output                              rx_phy_byte_reversal_6,
+
+  input                               rx_phy_locked_7,
+  input                               rx_phy_cal_busy_7,
+  input                               rx_phy_valid_7,
+  input   [31:0]                      rx_phy_data_7,
+  input   [ 3:0]                      rx_phy_disperr_7,
+  input   [ 3:0]                      rx_phy_deterr_7,
+  input   [ 3:0]                      rx_phy_kchar_7,
+  input                               rx_phy_full_7,
+  input                               rx_phy_empty_7,
+  output                              rx_phy_align_en_7,
+  output                              rx_phy_lane_polarity_7,
+  output                              rx_phy_lane_powerdown_7,
+  output                              rx_phy_bit_reversal_7,
+  output                              rx_phy_byte_reversal_7,
+
+  // rx-core interface
+
+  output  [((NUM_OF_LANES* 1)-1):0]   rx_core_locked,
+  output  [((NUM_OF_LANES* 1)-1):0]   rx_core_cal_busy,
+
+  // tx-ip interface
+
+  output  [((NUM_OF_LANES* 1)-1):0]   tx_ip_cal_busy,
+  output  [((NUM_OF_LANES* 1)-1):0]   tx_ip_full,
+  output  [((NUM_OF_LANES* 1)-1):0]   tx_ip_empty,
+  input   [((NUM_OF_LANES*32)-1):0]   tx_ip_data,
+  input   [((NUM_OF_LANES* 4)-1):0]   tx_ip_kchar,
+  input   [((NUM_OF_LANES* 1)-1):0]   tx_ip_elecidle,
+  input   [((NUM_OF_LANES* 1)-1):0]   tx_ip_lane_polarity,
+  input   [((NUM_OF_LANES* 1)-1):0]   tx_ip_lane_powerdown,
+  input                               tx_ip_bit_reversal,
+  input                               tx_ip_byte_reversal,
+
+  // tx-mux interface
+
+  input   [ 2:0]                      tx_ip_s_0,
+  output  [38:0]                      tx_ip_d_0,
+  output  [ 2:0]                      tx_phy_s_0,
+  input   [38:0]                      tx_phy_d_0,
+
+  input   [ 2:0]                      tx_ip_s_1,
+  output  [38:0]                      tx_ip_d_1,
+  output  [ 2:0]                      tx_phy_s_1,
+  input   [38:0]                      tx_phy_d_1,
+
+  input   [ 2:0]                      tx_ip_s_2,
+  output  [38:0]                      tx_ip_d_2,
+  output  [ 2:0]                      tx_phy_s_2,
+  input   [38:0]                      tx_phy_d_2,
+
+  input   [ 2:0]                      tx_ip_s_3,
+  output  [38:0]                      tx_ip_d_3,
+  output  [ 2:0]                      tx_phy_s_3,
+  input   [38:0]                      tx_phy_d_3,
+
+  input   [ 2:0]                      tx_ip_s_4,
+  output  [38:0]                      tx_ip_d_4,
+  output  [ 2:0]                      tx_phy_s_4,
+  input   [38:0]                      tx_phy_d_4,
+
+  input   [ 2:0]                      tx_ip_s_5,
+  output  [38:0]                      tx_ip_d_5,
+  output  [ 2:0]                      tx_phy_s_5,
+  input   [38:0]                      tx_phy_d_5,
+
+  input   [ 2:0]                      tx_ip_s_6,
+  output  [38:0]                      tx_ip_d_6,
+  output  [ 2:0]                      tx_phy_s_6,
+  input   [38:0]                      tx_phy_d_6,
+
+  input   [ 2:0]                      tx_ip_s_7,
+  output  [38:0]                      tx_ip_d_7,
+  output  [ 2:0]                      tx_phy_s_7,
+  input   [38:0]                      tx_phy_d_7,
+
+  // tx-phy interface
+
+  input                               tx_phy_cal_busy_0,
+  input                               tx_phy_full_0,
+  input                               tx_phy_empty_0,
+  output  [31:0]                      tx_phy_data_0,
+  output  [ 3:0]                      tx_phy_kchar_0,
+  output                              tx_phy_elecidle_0,
+  output                              tx_phy_lane_polarity_0,
+  output                              tx_phy_lane_powerdown_0,
+  output                              tx_phy_bit_reversal_0,
+  output                              tx_phy_byte_reversal_0,
+
+  input                               tx_phy_cal_busy_1,
+  input                               tx_phy_full_1,
+  input                               tx_phy_empty_1,
+  output  [31:0]                      tx_phy_data_1,
+  output  [ 3:0]                      tx_phy_kchar_1,
+  output                              tx_phy_elecidle_1,
+  output                              tx_phy_lane_polarity_1,
+  output                              tx_phy_lane_powerdown_1,
+  output                              tx_phy_bit_reversal_1,
+  output                              tx_phy_byte_reversal_1,
+
+  input                               tx_phy_cal_busy_2,
+  input                               tx_phy_full_2,
+  input                               tx_phy_empty_2,
+  output  [31:0]                      tx_phy_data_2,
+  output  [ 3:0]                      tx_phy_kchar_2,
+  output                              tx_phy_elecidle_2,
+  output                              tx_phy_lane_polarity_2,
+  output                              tx_phy_lane_powerdown_2,
+  output                              tx_phy_bit_reversal_2,
+  output                              tx_phy_byte_reversal_2,
+
+  input                               tx_phy_cal_busy_3,
+  input                               tx_phy_full_3,
+  input                               tx_phy_empty_3,
+  output  [31:0]                      tx_phy_data_3,
+  output  [ 3:0]                      tx_phy_kchar_3,
+  output                              tx_phy_elecidle_3,
+  output                              tx_phy_lane_polarity_3,
+  output                              tx_phy_lane_powerdown_3,
+  output                              tx_phy_bit_reversal_3,
+  output                              tx_phy_byte_reversal_3,
+
+  input                               tx_phy_cal_busy_4,
+  input                               tx_phy_full_4,
+  input                               tx_phy_empty_4,
+  output  [31:0]                      tx_phy_data_4,
+  output  [ 3:0]                      tx_phy_kchar_4,
+  output                              tx_phy_elecidle_4,
+  output                              tx_phy_lane_polarity_4,
+  output                              tx_phy_lane_powerdown_4,
+  output                              tx_phy_bit_reversal_4,
+  output                              tx_phy_byte_reversal_4,
+
+  input                               tx_phy_cal_busy_5,
+  input                               tx_phy_full_5,
+  input                               tx_phy_empty_5,
+  output  [31:0]                      tx_phy_data_5,
+  output  [ 3:0]                      tx_phy_kchar_5,
+  output                              tx_phy_elecidle_5,
+  output                              tx_phy_lane_polarity_5,
+  output                              tx_phy_lane_powerdown_5,
+  output                              tx_phy_bit_reversal_5,
+  output                              tx_phy_byte_reversal_5,
+
+  input                               tx_phy_cal_busy_6,
+  input                               tx_phy_full_6,
+  input                               tx_phy_empty_6,
+  output  [31:0]                      tx_phy_data_6,
+  output  [ 3:0]                      tx_phy_kchar_6,
+  output                              tx_phy_elecidle_6,
+  output                              tx_phy_lane_polarity_6,
+  output                              tx_phy_lane_powerdown_6,
+  output                              tx_phy_bit_reversal_6,
+  output                              tx_phy_byte_reversal_6,
+
+  input                               tx_phy_cal_busy_7,
+  input                               tx_phy_full_7,
+  input                               tx_phy_empty_7,
+  output  [31:0]                      tx_phy_data_7,
+  output  [ 3:0]                      tx_phy_kchar_7,
+  output                              tx_phy_elecidle_7,
+  output                              tx_phy_lane_polarity_7,
+  output                              tx_phy_lane_powerdown_7,
+  output                              tx_phy_bit_reversal_7,
+  output                              tx_phy_byte_reversal_7,
+
+  // tx-core interface
+
+  output  [((NUM_OF_LANES* 1)-1):0]   tx_core_cal_busy);
+
+  // parameters
+
+  parameter   integer NUM_OF_LANES = 4;
+
+  // rx assignments
+
+  generate
+  if (NUM_OF_LANES > 0) begin
+  assign rx_core_locked[0] = rx_phy_locked_0;
+  assign rx_core_cal_busy[0] = rx_phy_cal_busy_0;
+  assign rx_ip_locked[0] = rx_phy_locked_0;
+  assign rx_ip_cal_busy[0] = rx_phy_cal_busy_0;
+  assign rx_ip_valid[0] = rx_phy_valid_0;
+  assign rx_ip_data[((32*1)-1):(32*0)] = rx_phy_data_0;
+  assign rx_ip_disperr[((32*1)-1):(32*0)] = rx_phy_disperr_0;
+  assign rx_ip_deterr[((32*1)-1):(32*0)] = rx_phy_deterr_0;
+  assign rx_ip_kchar[((32*1)-1):(32*0)] = rx_phy_kchar_0;
+  assign rx_ip_full[0] = rx_phy_full_0;
+  assign rx_ip_empty[0] = rx_phy_empty_0;
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 0) begin
+  assign rx_phy_align_en_0 = rx_ip_align_en[0];
+  assign rx_phy_lane_polarity_0 = rx_ip_lane_polarity[0];
+  assign rx_phy_lane_powerdown_0 = rx_ip_lane_powerdown[0];
+  end else begin
+  assign rx_phy_align_en_0 = 1'd0;
+  assign rx_phy_lane_polarity_0 = 1'd0;
+  assign rx_phy_lane_powerdown_0 = 1'd0;
+  end
+  endgenerate
+
+  assign rx_phy_bit_reversal_0 = rx_ip_bit_reversal;
+  assign rx_phy_byte_reversal_0 = rx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 1) begin
+  assign rx_core_locked[1] = rx_phy_locked_1;
+  assign rx_core_cal_busy[1] = rx_phy_cal_busy_1;
+  assign rx_ip_locked[1] = rx_phy_locked_1;
+  assign rx_ip_cal_busy[1] = rx_phy_cal_busy_1;
+  assign rx_ip_valid[1] = rx_phy_valid_1;
+  assign rx_ip_data[((32*2)-1):(32*1)] = rx_phy_data_1;
+  assign rx_ip_disperr[((32*2)-1):(32*1)] = rx_phy_disperr_1;
+  assign rx_ip_deterr[((32*2)-1):(32*1)] = rx_phy_deterr_1;
+  assign rx_ip_kchar[((32*2)-1):(32*1)] = rx_phy_kchar_1;
+  assign rx_ip_full[1] = rx_phy_full_1;
+  assign rx_ip_empty[1] = rx_phy_empty_1;
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 1) begin
+  assign rx_phy_align_en_1 = rx_ip_align_en[1];
+  assign rx_phy_lane_polarity_1 = rx_ip_lane_polarity[1];
+  assign rx_phy_lane_powerdown_1 = rx_ip_lane_powerdown[1];
+  end else begin
+  assign rx_phy_align_en_1 = 1'd0;
+  assign rx_phy_lane_polarity_1 = 1'd0;
+  assign rx_phy_lane_powerdown_1 = 1'd0;
+  end
+  endgenerate
+
+  assign rx_phy_bit_reversal_1 = rx_ip_bit_reversal;
+  assign rx_phy_byte_reversal_1 = rx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 2) begin
+  assign rx_core_locked[2] = rx_phy_locked_2;
+  assign rx_core_cal_busy[2] = rx_phy_cal_busy_2;
+  assign rx_ip_locked[2] = rx_phy_locked_2;
+  assign rx_ip_cal_busy[2] = rx_phy_cal_busy_2;
+  assign rx_ip_valid[2] = rx_phy_valid_2;
+  assign rx_ip_data[((32*3)-1):(32*2)] = rx_phy_data_2;
+  assign rx_ip_disperr[((32*3)-1):(32*2)] = rx_phy_disperr_2;
+  assign rx_ip_deterr[((32*3)-1):(32*2)] = rx_phy_deterr_2;
+  assign rx_ip_kchar[((32*3)-1):(32*2)] = rx_phy_kchar_2;
+  assign rx_ip_full[2] = rx_phy_full_2;
+  assign rx_ip_empty[2] = rx_phy_empty_2;
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 2) begin
+  assign rx_phy_align_en_2 = rx_ip_align_en[2];
+  assign rx_phy_lane_polarity_2 = rx_ip_lane_polarity[2];
+  assign rx_phy_lane_powerdown_2 = rx_ip_lane_powerdown[2];
+  end else begin
+  assign rx_phy_align_en_2 = 1'd0;
+  assign rx_phy_lane_polarity_2 = 1'd0;
+  assign rx_phy_lane_powerdown_2 = 1'd0;
+  end
+  endgenerate
+
+  assign rx_phy_bit_reversal_2 = rx_ip_bit_reversal;
+  assign rx_phy_byte_reversal_2 = rx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 3) begin
+  assign rx_core_locked[3] = rx_phy_locked_3;
+  assign rx_core_cal_busy[3] = rx_phy_cal_busy_3;
+  assign rx_ip_locked[3] = rx_phy_locked_3;
+  assign rx_ip_cal_busy[3] = rx_phy_cal_busy_3;
+  assign rx_ip_valid[3] = rx_phy_valid_3;
+  assign rx_ip_data[((32*4)-1):(32*3)] = rx_phy_data_3;
+  assign rx_ip_disperr[((32*4)-1):(32*3)] = rx_phy_disperr_3;
+  assign rx_ip_deterr[((32*4)-1):(32*3)] = rx_phy_deterr_3;
+  assign rx_ip_kchar[((32*4)-1):(32*3)] = rx_phy_kchar_3;
+  assign rx_ip_full[3] = rx_phy_full_3;
+  assign rx_ip_empty[3] = rx_phy_empty_3;
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 3) begin
+  assign rx_phy_align_en_3 = rx_ip_align_en[3];
+  assign rx_phy_lane_polarity_3 = rx_ip_lane_polarity[3];
+  assign rx_phy_lane_powerdown_3 = rx_ip_lane_powerdown[3];
+  end else begin
+  assign rx_phy_align_en_3 = 1'd0;
+  assign rx_phy_lane_polarity_3 = 1'd0;
+  assign rx_phy_lane_powerdown_3 = 1'd0;
+  end
+  endgenerate
+
+  assign rx_phy_bit_reversal_3 = rx_ip_bit_reversal;
+  assign rx_phy_byte_reversal_3 = rx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 4) begin
+  assign rx_core_locked[4] = rx_phy_locked_4;
+  assign rx_core_cal_busy[4] = rx_phy_cal_busy_4;
+  assign rx_ip_locked[4] = rx_phy_locked_4;
+  assign rx_ip_cal_busy[4] = rx_phy_cal_busy_4;
+  assign rx_ip_valid[4] = rx_phy_valid_4;
+  assign rx_ip_data[((32*5)-1):(32*4)] = rx_phy_data_4;
+  assign rx_ip_disperr[((32*5)-1):(32*4)] = rx_phy_disperr_4;
+  assign rx_ip_deterr[((32*5)-1):(32*4)] = rx_phy_deterr_4;
+  assign rx_ip_kchar[((32*5)-1):(32*4)] = rx_phy_kchar_4;
+  assign rx_ip_full[4] = rx_phy_full_4;
+  assign rx_ip_empty[4] = rx_phy_empty_4;
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 4) begin
+  assign rx_phy_align_en_4 = rx_ip_align_en[4];
+  assign rx_phy_lane_polarity_4 = rx_ip_lane_polarity[4];
+  assign rx_phy_lane_powerdown_4 = rx_ip_lane_powerdown[4];
+  end else begin
+  assign rx_phy_align_en_4 = 1'd0;
+  assign rx_phy_lane_polarity_4 = 1'd0;
+  assign rx_phy_lane_powerdown_4 = 1'd0;
+  end
+  endgenerate
+
+  assign rx_phy_bit_reversal_4 = rx_ip_bit_reversal;
+  assign rx_phy_byte_reversal_4 = rx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 5) begin
+  assign rx_core_locked[5] = rx_phy_locked_5;
+  assign rx_core_cal_busy[5] = rx_phy_cal_busy_5;
+  assign rx_ip_locked[5] = rx_phy_locked_5;
+  assign rx_ip_cal_busy[5] = rx_phy_cal_busy_5;
+  assign rx_ip_valid[5] = rx_phy_valid_5;
+  assign rx_ip_data[((32*6)-1):(32*5)] = rx_phy_data_5;
+  assign rx_ip_disperr[((32*6)-1):(32*5)] = rx_phy_disperr_5;
+  assign rx_ip_deterr[((32*6)-1):(32*5)] = rx_phy_deterr_5;
+  assign rx_ip_kchar[((32*6)-1):(32*5)] = rx_phy_kchar_5;
+  assign rx_ip_full[5] = rx_phy_full_5;
+  assign rx_ip_empty[5] = rx_phy_empty_5;
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 5) begin
+  assign rx_phy_align_en_5 = rx_ip_align_en[5];
+  assign rx_phy_lane_polarity_5 = rx_ip_lane_polarity[5];
+  assign rx_phy_lane_powerdown_5 = rx_ip_lane_powerdown[5];
+  end else begin
+  assign rx_phy_align_en_5 = 1'd0;
+  assign rx_phy_lane_polarity_5 = 1'd0;
+  assign rx_phy_lane_powerdown_5 = 1'd0;
+  end
+  endgenerate
+
+  assign rx_phy_bit_reversal_5 = rx_ip_bit_reversal;
+  assign rx_phy_byte_reversal_5 = rx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 6) begin
+  assign rx_core_locked[6] = rx_phy_locked_6;
+  assign rx_core_cal_busy[6] = rx_phy_cal_busy_6;
+  assign rx_ip_locked[6] = rx_phy_locked_6;
+  assign rx_ip_cal_busy[6] = rx_phy_cal_busy_6;
+  assign rx_ip_valid[6] = rx_phy_valid_6;
+  assign rx_ip_data[((32*7)-1):(32*6)] = rx_phy_data_6;
+  assign rx_ip_disperr[((32*7)-1):(32*6)] = rx_phy_disperr_6;
+  assign rx_ip_deterr[((32*7)-1):(32*6)] = rx_phy_deterr_6;
+  assign rx_ip_kchar[((32*7)-1):(32*6)] = rx_phy_kchar_6;
+  assign rx_ip_full[6] = rx_phy_full_6;
+  assign rx_ip_empty[6] = rx_phy_empty_6;
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 6) begin
+  assign rx_phy_align_en_6 = rx_ip_align_en[6];
+  assign rx_phy_lane_polarity_6 = rx_ip_lane_polarity[6];
+  assign rx_phy_lane_powerdown_6 = rx_ip_lane_powerdown[6];
+  end else begin
+  assign rx_phy_align_en_6 = 1'd0;
+  assign rx_phy_lane_polarity_6 = 1'd0;
+  assign rx_phy_lane_powerdown_6 = 1'd0;
+  end
+  endgenerate
+
+  assign rx_phy_bit_reversal_6 = rx_ip_bit_reversal;
+  assign rx_phy_byte_reversal_6 = rx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 7) begin
+  assign rx_core_locked[7] = rx_phy_locked_7;
+  assign rx_core_cal_busy[7] = rx_phy_cal_busy_7;
+  assign rx_ip_locked[7] = rx_phy_locked_7;
+  assign rx_ip_cal_busy[7] = rx_phy_cal_busy_7;
+  assign rx_ip_valid[7] = rx_phy_valid_7;
+  assign rx_ip_data[((32*8)-1):(32*7)] = rx_phy_data_7;
+  assign rx_ip_disperr[((32*8)-1):(32*7)] = rx_phy_disperr_7;
+  assign rx_ip_deterr[((32*8)-1):(32*7)] = rx_phy_deterr_7;
+  assign rx_ip_kchar[((32*8)-1):(32*7)] = rx_phy_kchar_7;
+  assign rx_ip_full[7] = rx_phy_full_7;
+  assign rx_ip_empty[7] = rx_phy_empty_7;
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 7) begin
+  assign rx_phy_align_en_7 = rx_ip_align_en[7];
+  assign rx_phy_lane_polarity_7 = rx_ip_lane_polarity[7];
+  assign rx_phy_lane_powerdown_7 = rx_ip_lane_powerdown[7];
+  end else begin
+  assign rx_phy_align_en_7 = 1'd0;
+  assign rx_phy_lane_polarity_7 = 1'd0;
+  assign rx_phy_lane_powerdown_7 = 1'd0;
+  end
+  endgenerate
+
+  assign rx_phy_bit_reversal_7 = rx_ip_bit_reversal;
+  assign rx_phy_byte_reversal_7 = rx_ip_byte_reversal;
+
+  // tx assignments
+
+  generate
+  if (NUM_OF_LANES > 0) begin
+  assign tx_core_cal_busy[0] = tx_ip_s_0[0];
+  assign tx_ip_cal_busy[0] = tx_ip_s_0[0];
+  assign tx_ip_full[0] = tx_ip_s_0[1];
+  assign tx_ip_empty[0] = tx_ip_s_0[2];
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 0) begin
+  assign tx_ip_d_0[31: 0] = tx_ip_data[((32*1)-1):(32*0)];
+  assign tx_ip_d_0[35:32] = tx_ip_kchar[((4*1)-1):(4*0)];
+  assign tx_ip_d_0[36:36] = tx_ip_elecidle[0];
+  assign tx_ip_d_0[37:37] = tx_ip_lane_polarity[0];
+  assign tx_ip_d_0[38:38] = tx_ip_lane_powerdown[0];
+  end else begin
+  assign tx_ip_d_0[31: 0] = 32'd0;
+  assign tx_ip_d_0[35:32] = 4'd0;
+  assign tx_ip_d_0[36:36] = 1'd0;
+  assign tx_ip_d_0[37:37] = 1'd0;
+  assign tx_ip_d_0[38:38] = 1'd0;
+  end
+  endgenerate
+
+  assign tx_phy_s_0[0] = tx_phy_cal_busy_0;
+  assign tx_phy_s_0[1] = tx_phy_full_0;
+  assign tx_phy_s_0[2] = tx_phy_empty_0;
+  assign tx_phy_data_0 = tx_phy_d_0[31:0];
+  assign tx_phy_kchar_0 = tx_phy_d_0[35:32];
+  assign tx_phy_elecidle_0 = tx_phy_d_0[36];
+  assign tx_phy_lane_polarity_0 = tx_phy_d_0[37];
+  assign tx_phy_lane_powerdown_0 = tx_phy_d_0[38];
+  assign tx_phy_bit_reversal_0 = tx_ip_bit_reversal;
+  assign tx_phy_byte_reversal_0 = tx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 1) begin
+  assign tx_core_cal_busy[1] = tx_ip_s_1[0];
+  assign tx_ip_cal_busy[1] = tx_ip_s_1[0];
+  assign tx_ip_full[1] = tx_ip_s_1[1];
+  assign tx_ip_empty[1] = tx_ip_s_1[2];
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 1) begin
+  assign tx_ip_d_1[31: 0] = tx_ip_data[((32*2)-1):(32*1)];
+  assign tx_ip_d_1[35:32] = tx_ip_kchar[((4*2)-1):(4*1)];
+  assign tx_ip_d_1[36:36] = tx_ip_elecidle[1];
+  assign tx_ip_d_1[37:37] = tx_ip_lane_polarity[1];
+  assign tx_ip_d_1[38:38] = tx_ip_lane_powerdown[1];
+  end else begin
+  assign tx_ip_d_1[31: 0] = 32'd0;
+  assign tx_ip_d_1[35:32] = 4'd0;
+  assign tx_ip_d_1[36:36] = 1'd0;
+  assign tx_ip_d_1[37:37] = 1'd0;
+  assign tx_ip_d_1[38:38] = 1'd0;
+  end
+  endgenerate
+
+  assign tx_phy_s_1[0] = tx_phy_cal_busy_1;
+  assign tx_phy_s_1[1] = tx_phy_full_1;
+  assign tx_phy_s_1[2] = tx_phy_empty_1;
+  assign tx_phy_data_1 = tx_phy_d_1[31:0];
+  assign tx_phy_kchar_1 = tx_phy_d_1[35:32];
+  assign tx_phy_elecidle_1 = tx_phy_d_1[36];
+  assign tx_phy_lane_polarity_1 = tx_phy_d_1[37];
+  assign tx_phy_lane_powerdown_1 = tx_phy_d_1[38];
+  assign tx_phy_bit_reversal_1 = tx_ip_bit_reversal;
+  assign tx_phy_byte_reversal_1 = tx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 2) begin
+  assign tx_core_cal_busy[2] = tx_ip_s_2[0];
+  assign tx_ip_cal_busy[2] = tx_ip_s_2[0];
+  assign tx_ip_full[2] = tx_ip_s_2[1];
+  assign tx_ip_empty[2] = tx_ip_s_2[2];
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 2) begin
+  assign tx_ip_d_2[31: 0] = tx_ip_data[((32*3)-1):(32*2)];
+  assign tx_ip_d_2[35:32] = tx_ip_kchar[((4*3)-1):(4*2)];
+  assign tx_ip_d_2[36:36] = tx_ip_elecidle[2];
+  assign tx_ip_d_2[37:37] = tx_ip_lane_polarity[2];
+  assign tx_ip_d_2[38:38] = tx_ip_lane_powerdown[2];
+  end else begin
+  assign tx_ip_d_2[31: 0] = 32'd0;
+  assign tx_ip_d_2[35:32] = 4'd0;
+  assign tx_ip_d_2[36:36] = 1'd0;
+  assign tx_ip_d_2[37:37] = 1'd0;
+  assign tx_ip_d_2[38:38] = 1'd0;
+  end
+  endgenerate
+
+  assign tx_phy_s_2[0] = tx_phy_cal_busy_2;
+  assign tx_phy_s_2[1] = tx_phy_full_2;
+  assign tx_phy_s_2[2] = tx_phy_empty_2;
+  assign tx_phy_data_2 = tx_phy_d_2[31:0];
+  assign tx_phy_kchar_2 = tx_phy_d_2[35:32];
+  assign tx_phy_elecidle_2 = tx_phy_d_2[36];
+  assign tx_phy_lane_polarity_2 = tx_phy_d_2[37];
+  assign tx_phy_lane_powerdown_2 = tx_phy_d_2[38];
+  assign tx_phy_bit_reversal_2 = tx_ip_bit_reversal;
+  assign tx_phy_byte_reversal_2 = tx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 3) begin
+  assign tx_core_cal_busy[3] = tx_ip_s_3[0];
+  assign tx_ip_cal_busy[3] = tx_ip_s_3[0];
+  assign tx_ip_full[3] = tx_ip_s_3[1];
+  assign tx_ip_empty[3] = tx_ip_s_3[2];
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 3) begin
+  assign tx_ip_d_3[31: 0] = tx_ip_data[((32*4)-1):(32*3)];
+  assign tx_ip_d_3[35:32] = tx_ip_kchar[((4*4)-1):(4*3)];
+  assign tx_ip_d_3[36:36] = tx_ip_elecidle[3];
+  assign tx_ip_d_3[37:37] = tx_ip_lane_polarity[3];
+  assign tx_ip_d_3[38:38] = tx_ip_lane_powerdown[3];
+  end else begin
+  assign tx_ip_d_3[31: 0] = 32'd0;
+  assign tx_ip_d_3[35:32] = 4'd0;
+  assign tx_ip_d_3[36:36] = 1'd0;
+  assign tx_ip_d_3[37:37] = 1'd0;
+  assign tx_ip_d_3[38:38] = 1'd0;
+  end
+  endgenerate
+
+  assign tx_phy_s_3[0] = tx_phy_cal_busy_3;
+  assign tx_phy_s_3[1] = tx_phy_full_3;
+  assign tx_phy_s_3[2] = tx_phy_empty_3;
+  assign tx_phy_data_3 = tx_phy_d_3[31:0];
+  assign tx_phy_kchar_3 = tx_phy_d_3[35:32];
+  assign tx_phy_elecidle_3 = tx_phy_d_3[36];
+  assign tx_phy_lane_polarity_3 = tx_phy_d_3[37];
+  assign tx_phy_lane_powerdown_3 = tx_phy_d_3[38];
+  assign tx_phy_bit_reversal_3 = tx_ip_bit_reversal;
+  assign tx_phy_byte_reversal_3 = tx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 4) begin
+  assign tx_core_cal_busy[4] = tx_ip_s_4[0];
+  assign tx_ip_cal_busy[4] = tx_ip_s_4[0];
+  assign tx_ip_full[4] = tx_ip_s_4[1];
+  assign tx_ip_empty[4] = tx_ip_s_4[2];
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 4) begin
+  assign tx_ip_d_4[31: 0] = tx_ip_data[((32*5)-1):(32*4)];
+  assign tx_ip_d_4[35:32] = tx_ip_kchar[((4*5)-1):(4*4)];
+  assign tx_ip_d_4[36:36] = tx_ip_elecidle[4];
+  assign tx_ip_d_4[37:37] = tx_ip_lane_polarity[4];
+  assign tx_ip_d_4[38:38] = tx_ip_lane_powerdown[4];
+  end else begin
+  assign tx_ip_d_4[31: 0] = 32'd0;
+  assign tx_ip_d_4[35:32] = 4'd0;
+  assign tx_ip_d_4[36:36] = 1'd0;
+  assign tx_ip_d_4[37:37] = 1'd0;
+  assign tx_ip_d_4[38:38] = 1'd0;
+  end
+  endgenerate
+
+  assign tx_phy_s_4[0] = tx_phy_cal_busy_4;
+  assign tx_phy_s_4[1] = tx_phy_full_4;
+  assign tx_phy_s_4[2] = tx_phy_empty_4;
+  assign tx_phy_data_4 = tx_phy_d_4[31:0];
+  assign tx_phy_kchar_4 = tx_phy_d_4[35:32];
+  assign tx_phy_elecidle_4 = tx_phy_d_4[36];
+  assign tx_phy_lane_polarity_4 = tx_phy_d_4[37];
+  assign tx_phy_lane_powerdown_4 = tx_phy_d_4[38];
+  assign tx_phy_bit_reversal_4 = tx_ip_bit_reversal;
+  assign tx_phy_byte_reversal_4 = tx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 5) begin
+  assign tx_core_cal_busy[5] = tx_ip_s_5[0];
+  assign tx_ip_cal_busy[5] = tx_ip_s_5[0];
+  assign tx_ip_full[5] = tx_ip_s_5[1];
+  assign tx_ip_empty[5] = tx_ip_s_5[2];
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 5) begin
+  assign tx_ip_d_5[31: 0] = tx_ip_data[((32*6)-1):(32*5)];
+  assign tx_ip_d_5[35:32] = tx_ip_kchar[((4*6)-1):(4*5)];
+  assign tx_ip_d_5[36:36] = tx_ip_elecidle[5];
+  assign tx_ip_d_5[37:37] = tx_ip_lane_polarity[5];
+  assign tx_ip_d_5[38:38] = tx_ip_lane_powerdown[5];
+  end else begin
+  assign tx_ip_d_5[31: 0] = 32'd0;
+  assign tx_ip_d_5[35:32] = 4'd0;
+  assign tx_ip_d_5[36:36] = 1'd0;
+  assign tx_ip_d_5[37:37] = 1'd0;
+  assign tx_ip_d_5[38:38] = 1'd0;
+  end
+  endgenerate
+
+  assign tx_phy_s_5[0] = tx_phy_cal_busy_5;
+  assign tx_phy_s_5[1] = tx_phy_full_5;
+  assign tx_phy_s_5[2] = tx_phy_empty_5;
+  assign tx_phy_data_5 = tx_phy_d_5[31:0];
+  assign tx_phy_kchar_5 = tx_phy_d_5[35:32];
+  assign tx_phy_elecidle_5 = tx_phy_d_5[36];
+  assign tx_phy_lane_polarity_5 = tx_phy_d_5[37];
+  assign tx_phy_lane_powerdown_5 = tx_phy_d_5[38];
+  assign tx_phy_bit_reversal_5 = tx_ip_bit_reversal;
+  assign tx_phy_byte_reversal_5 = tx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 6) begin
+  assign tx_core_cal_busy[6] = tx_ip_s_6[0];
+  assign tx_ip_cal_busy[6] = tx_ip_s_6[0];
+  assign tx_ip_full[6] = tx_ip_s_6[1];
+  assign tx_ip_empty[6] = tx_ip_s_6[2];
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 6) begin
+  assign tx_ip_d_6[31: 0] = tx_ip_data[((32*7)-1):(32*6)];
+  assign tx_ip_d_6[35:32] = tx_ip_kchar[((4*7)-1):(4*6)];
+  assign tx_ip_d_6[36:36] = tx_ip_elecidle[6];
+  assign tx_ip_d_6[37:37] = tx_ip_lane_polarity[6];
+  assign tx_ip_d_6[38:38] = tx_ip_lane_powerdown[6];
+  end else begin
+  assign tx_ip_d_6[31: 0] = 32'd0;
+  assign tx_ip_d_6[35:32] = 4'd0;
+  assign tx_ip_d_6[36:36] = 1'd0;
+  assign tx_ip_d_6[37:37] = 1'd0;
+  assign tx_ip_d_6[38:38] = 1'd0;
+  end
+  endgenerate
+
+  assign tx_phy_s_6[0] = tx_phy_cal_busy_6;
+  assign tx_phy_s_6[1] = tx_phy_full_6;
+  assign tx_phy_s_6[2] = tx_phy_empty_6;
+  assign tx_phy_data_6 = tx_phy_d_6[31:0];
+  assign tx_phy_kchar_6 = tx_phy_d_6[35:32];
+  assign tx_phy_elecidle_6 = tx_phy_d_6[36];
+  assign tx_phy_lane_polarity_6 = tx_phy_d_6[37];
+  assign tx_phy_lane_powerdown_6 = tx_phy_d_6[38];
+  assign tx_phy_bit_reversal_6 = tx_ip_bit_reversal;
+  assign tx_phy_byte_reversal_6 = tx_ip_byte_reversal;
+
+  generate
+  if (NUM_OF_LANES > 7) begin
+  assign tx_core_cal_busy[7] = tx_ip_s_7[0];
+  assign tx_ip_cal_busy[7] = tx_ip_s_7[0];
+  assign tx_ip_full[7] = tx_ip_s_7[1];
+  assign tx_ip_empty[7] = tx_ip_s_7[2];
+  end
+  endgenerate
+
+  generate
+  if (NUM_OF_LANES > 7) begin
+  assign tx_ip_d_7[31: 0] = tx_ip_data[((32*8)-1):(32*7)];
+  assign tx_ip_d_7[35:32] = tx_ip_kchar[((4*8)-1):(4*7)];
+  assign tx_ip_d_7[36:36] = tx_ip_elecidle[7];
+  assign tx_ip_d_7[37:37] = tx_ip_lane_polarity[7];
+  assign tx_ip_d_7[38:38] = tx_ip_lane_powerdown[7];
+  end else begin
+  assign tx_ip_d_7[31: 0] = 32'd0;
+  assign tx_ip_d_7[35:32] = 4'd0;
+  assign tx_ip_d_7[36:36] = 1'd0;
+  assign tx_ip_d_7[37:37] = 1'd0;
+  assign tx_ip_d_7[38:38] = 1'd0;
+  end
+  endgenerate
+
+  assign tx_phy_s_7[0] = tx_phy_cal_busy_7;
+  assign tx_phy_s_7[1] = tx_phy_full_7;
+  assign tx_phy_s_7[2] = tx_phy_empty_7;
+  assign tx_phy_data_7 = tx_phy_d_7[31:0];
+  assign tx_phy_kchar_7 = tx_phy_d_7[35:32];
+  assign tx_phy_elecidle_7 = tx_phy_d_7[36];
+  assign tx_phy_lane_polarity_7 = tx_phy_d_7[37];
+  assign tx_phy_lane_powerdown_7 = tx_phy_d_7[38];
+  assign tx_phy_bit_reversal_7 = tx_ip_bit_reversal;
+  assign tx_phy_byte_reversal_7 = tx_ip_byte_reversal;
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/altera/avl_adxphy/avl_adxphy_hw.tcl b/library/altera/avl_adxphy/avl_adxphy_hw.tcl
new file mode 100644
index 000000000..104b8d526
--- /dev/null
+++ b/library/altera/avl_adxphy/avl_adxphy_hw.tcl
@@ -0,0 +1,114 @@
+
+package require -exact qsys 14.0
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
+
+set_module_property NAME avl_adxphy
+set_module_property DESCRIPTION "Avalon ADXPHY Core"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME avl_adxphy
+set_module_property ELABORATION_CALLBACK p_avl_adxphy
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" ""
+set_fileset_property quartus_synth TOP_LEVEL avl_adxphy
+add_fileset_file avl_adxphy.v VERILOG PATH avl_adxphy.v TOP_LEVEL_FILE
+
+# parameters
+
+add_parameter TX_OR_RX_N INTEGER 0
+set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
+set_parameter_property TX_OR_RX_N TYPE INTEGER
+set_parameter_property TX_OR_RX_N UNITS None
+set_parameter_property TX_OR_RX_N HDL_PARAMETER false
+
+add_parameter NUM_OF_LANES INTEGER 4
+set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
+set_parameter_property NUM_OF_LANES TYPE INTEGER
+set_parameter_property NUM_OF_LANES UNITS None
+set_parameter_property NUM_OF_LANES HDL_PARAMETER true
+
+proc p_avl_adxphy {} {
+
+  set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
+  set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
+
+  if {$m_tx_or_rx_n == 1} {
+
+    ad_conduit tx_core_cal_busy tx_cal_busy tx_core_cal_busy output $m_num_of_lanes
+
+    ad_conduit tx_ip_cal_busy tx_cal_busy tx_ip_cal_busy output $m_num_of_lanes
+    ad_conduit tx_ip_pcfifo_full export tx_ip_full output $m_num_of_lanes
+    ad_conduit tx_ip_pcfifo_empty export tx_ip_empty output $m_num_of_lanes
+    ad_conduit tx_ip_pcs_data export tx_ip_data input 32*$m_num_of_lanes
+    ad_conduit tx_ip_pcs_kchar_data export tx_ip_kchar input 4*$m_num_of_lanes
+    ad_conduit tx_ip_elecidle export tx_ip_elecidle input $m_num_of_lanes
+    ad_conduit tx_ip_csr_lane_polarity export tx_ip_lane_polarity input $m_num_of_lanes
+    ad_conduit tx_ip_csr_lane_powerdown export tx_ip_lane_powerdown input $m_num_of_lanes
+    ad_conduit tx_ip_csr_bit_reversal export rx_tp_bit_reversal input 1
+    ad_conduit tx_ip_csr_byte_reversal export rx_tp_byte_reversal input 1
+
+    for {set n 0} {$n < $m_num_of_lanes} {incr n} {
+
+      ad_conduit tx_ip_s_${n} export tx_ip_s_${n} input 3
+      ad_conduit tx_ip_d_${n} export tx_ip_d_${n} output 39
+      ad_conduit tx_phy_s_${n} export tx_phy_s_${n} output 3
+      ad_conduit tx_phy_d_${n} export tx_phy_d_${n} input 39
+
+      ad_conduit tx_phy${n}_cal_busy tx_cal_busy tx_phy_cal_busy_${n} input 1
+      ad_conduit tx_phy${n}_pcfifo_full export tx_phy_full_${n} input 1
+      ad_conduit tx_phy${n}_pcfifo_empty export tx_phy_empty_${n} input 1
+      ad_conduit tx_phy${n}_pcs_data export tx_phy_data_${n} output 32
+      ad_conduit tx_phy${n}_pcs_kchar_data export tx_phy_kchar_${n} output 4
+      ad_conduit tx_phy${n}_elecidle export tx_phy_elecidle_${n} output 1
+      ad_conduit tx_phy${n}_csr_lane_polarity export tx_phy_lane_polarity_${n} output 1
+      ad_conduit tx_phy${n}_csr_lane_powerdown export tx_phy_lane_powerdown_${n} output 1
+      ad_conduit tx_phy${n}_csr_bit_reversal export tx_phy_bit_reversal_${n} output 1
+      ad_conduit tx_phy${n}_csr_byte_reversal export tx_phy_byte_reversal_${n} output 1
+    }
+  }
+
+  if {$m_tx_or_rx_n == 0} {
+
+    ad_conduit rx_core_is_lockedtodata rx_is_lockedtodata rx_core_locked output $m_num_of_lanes
+    ad_conduit rx_core_cal_busy rx_cal_busy rx_core_cal_busy output $m_num_of_lanes
+
+    ad_conduit rx_ip_is_lockedtodata rx_is_lockedtodata rx_ip_locked output $m_num_of_lanes
+    ad_conduit rx_ip_cal_busy rx_cal_busy rx_ip_cal_busy output $m_num_of_lanes
+    ad_conduit rx_ip_pcs_data_valid export rx_ip_valid output $m_num_of_lanes
+    ad_conduit rx_ip_pcs_data export rx_ip_data output 32*$m_num_of_lanes
+    ad_conduit rx_ip_pcs_disperr export rx_ip_disperr output 4*$m_num_of_lanes
+    ad_conduit rx_ip_pcs_errdetect export rx_ip_deterr output 4*$m_num_of_lanes
+    ad_conduit rx_ip_pcs_kchar_data export rx_ip_kchar output 4*$m_num_of_lanes
+    ad_conduit rx_ip_pcfifo_full export rx_ip_full output $m_num_of_lanes
+    ad_conduit rx_ip_pcfifo_empty export rx_ip_empty output $m_num_of_lanes
+    ad_conduit rx_ip_patternalign_en export rx_ip_align_en input $m_num_of_lanes
+    ad_conduit rx_ip_csr_lane_polarity export rx_ip_lane_polarity input $m_num_of_lanes
+    ad_conduit rx_ip_csr_lane_powerdown export rx_ip_lane_powerdown input $m_num_of_lanes
+    ad_conduit rx_ip_csr_bit_reversal export rx_ip_bit_reversal input 1
+    ad_conduit rx_ip_csr_byte_reversal export rx_ip_byte_reversal input 1
+
+    for {set n 0} {$n < $m_num_of_lanes} {incr n} {
+
+      ad_conduit rx_phy${n}_is_lockedtodata rx_is_lockedtodata rx_phy_locked_${n} input 1
+      ad_conduit rx_phy${n}_cal_busy rx_cal_busy rx_phy_cal_busy_${n} input 1
+      ad_conduit rx_phy${n}_pcs_data_valid export rx_phy_valid_${n} input 1
+      ad_conduit rx_phy${n}_pcs_data export rx_phy_data_${n} input 32
+      ad_conduit rx_phy${n}_pcs_disperr export rx_phy_disperr_${n} input 4
+      ad_conduit rx_phy${n}_pcs_errdetect export rx_phy_deterr_${n} input 4
+      ad_conduit rx_phy${n}_pcs_kchar_data export rx_phy_kchar_${n} input 4
+      ad_conduit rx_phy${n}_pcfifo_full export rx_phy_full_${n} input 1
+      ad_conduit rx_phy${n}_pcfifo_empty export rx_phy_empty_${n} input 1
+      ad_conduit rx_phy${n}_patternalign_en export rx_phy_align_en_${n} output 1
+      ad_conduit rx_phy${n}_csr_lane_polarity export rx_phy_lane_polarity_${n} output 1
+      ad_conduit rx_phy${n}_csr_lane_powerdown export rx_phy_lane_powerdown_${n} output 1
+      ad_conduit rx_phy${n}_csr_bit_reversal export rx_phy_bit_reversal_${n} output 1
+      ad_conduit rx_phy${n}_csr_byte_reversal export rx_phy_byte_reversal_${n} output 1
+    }
+  }
+}
+
+

From 9159e31244ee8e525dd399b33cecb27f37a6b3fe Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 8 Sep 2016 13:08:41 -0400
Subject: [PATCH 462/972] axi_adxcvr- compile fixes

---
 library/altera/axi_adxcvr/axi_adxcvr.v    | 6 +++---
 library/altera/axi_adxcvr/axi_adxcvr_up.v | 7 +++----
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/library/altera/axi_adxcvr/axi_adxcvr.v b/library/altera/axi_adxcvr/axi_adxcvr.v
index 1c81de268..d5f38db9b 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr.v
@@ -45,7 +45,7 @@ module axi_adxcvr (
   input                         up_ref_pll_locked,
   input   [(NUM_OF_LANES-1):0]  up_ready,
 
-  input                         s_axi_clk,
+  input                         s_axi_aclk,
   input                         s_axi_aresetn,
   input                         s_axi_awvalid,
   input   [31:0]                s_axi_awaddr,
@@ -88,8 +88,8 @@ module axi_adxcvr (
 
   // clk & rst
 
-  assign up_rstn = axi_aresetn;
-  assign up_clk = axi_clk;
+  assign up_rstn = s_axi_aresetn;
+  assign up_clk = s_axi_aclk;
 
   // instantiations
 
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v
index ca5fb1bb6..e9f9dbe9c 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v
@@ -109,11 +109,10 @@ module axi_adxcvr_up (
   end
 
   assign up_rst = up_rst_cnt[3];
-  assign up_status = up_status_int;
   assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
-  assign up_status_32_s[31:(NUM_OF_LANES+1)] <= 'd0;
-  assign up_status_32_s[NUM_OF_LANES] <= up_ref_pll_locked;
-  assign up_status_32_s[(NUM_OF_LANES-1):0] <= up_ready;
+  assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
+  assign up_status_32_s[NUM_OF_LANES] = up_ref_pll_locked;
+  assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready;
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin

From d30ffdb7e973f95ec8641d8e0fc1706bc9588bd0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:45:03 -0400
Subject: [PATCH 463/972] avl_adxcfg- ip/phy split

---
 library/altera/avl_adxcfg/avl_adxcfg.v      | 639 +++-----------------
 library/altera/avl_adxcfg/avl_adxcfg_hw.tcl |  67 +-
 2 files changed, 106 insertions(+), 600 deletions(-)

diff --git a/library/altera/avl_adxcfg/avl_adxcfg.v b/library/altera/avl_adxcfg/avl_adxcfg.v
index 081baca43..510b077cb 100644
--- a/library/altera/avl_adxcfg/avl_adxcfg.v
+++ b/library/altera/avl_adxcfg/avl_adxcfg.v
@@ -46,593 +46,116 @@ module avl_adxcfg (
 
   input           rcfg_in_read_0,
   input           rcfg_in_write_0,
-  input   [11:0]  rcfg_in_address_0,
+  input   [ 9:0]  rcfg_in_address_0,
   input   [31:0]  rcfg_in_writedata_0,
   output  [31:0]  rcfg_in_readdata_0,
   output          rcfg_in_waitrequest_0,
 
-  output          rcfg_out_read_0,
-  output          rcfg_out_write_0,
-  output  [11:0]  rcfg_out_address_0,
-  output  [31:0]  rcfg_out_writedata_0,
-  input   [31:0]  rcfg_out_readdata_0,
-  input           rcfg_out_waitrequest_0,
-
   input           rcfg_in_read_1,
   input           rcfg_in_write_1,
-  input   [11:0]  rcfg_in_address_1,
+  input   [ 9:0]  rcfg_in_address_1,
   input   [31:0]  rcfg_in_writedata_1,
   output  [31:0]  rcfg_in_readdata_1,
   output          rcfg_in_waitrequest_1,
 
+  output          rcfg_out_read_0,
+  output          rcfg_out_write_0,
+  output  [ 9:0]  rcfg_out_address_0,
+  output  [31:0]  rcfg_out_writedata_0,
+  input   [31:0]  rcfg_out_readdata_0,
+  input           rcfg_out_waitrequest_0,
+
   output          rcfg_out_read_1,
   output          rcfg_out_write_1,
-  output  [11:0]  rcfg_out_address_1,
+  output  [ 9:0]  rcfg_out_address_1,
   output  [31:0]  rcfg_out_writedata_1,
   input   [31:0]  rcfg_out_readdata_1,
-  input           rcfg_out_waitrequest_1,
-
-  input           rcfg_in_read_2,
-  input           rcfg_in_write_2,
-  input   [11:0]  rcfg_in_address_2,
-  input   [31:0]  rcfg_in_writedata_2,
-  output  [31:0]  rcfg_in_readdata_2,
-  output          rcfg_in_waitrequest_2,
-
-  output          rcfg_out_read_2,
-  output          rcfg_out_write_2,
-  output  [11:0]  rcfg_out_address_2,
-  output  [31:0]  rcfg_out_writedata_2,
-  input   [31:0]  rcfg_out_readdata_2,
-  input           rcfg_out_waitrequest_2,
-
-  input           rcfg_in_read_3,
-  input           rcfg_in_write_3,
-  input   [11:0]  rcfg_in_address_3,
-  input   [31:0]  rcfg_in_writedata_3,
-  output  [31:0]  rcfg_in_readdata_3,
-  output          rcfg_in_waitrequest_3,
-
-  output          rcfg_out_read_3,
-  output          rcfg_out_write_3,
-  output  [11:0]  rcfg_out_address_3,
-  output  [31:0]  rcfg_out_writedata_3,
-  input   [31:0]  rcfg_out_readdata_3,
-  input           rcfg_out_waitrequest_3,
-
-  input           rcfg_in_read_4,
-  input           rcfg_in_write_4,
-  input   [11:0]  rcfg_in_address_4,
-  input   [31:0]  rcfg_in_writedata_4,
-  output  [31:0]  rcfg_in_readdata_4,
-  output          rcfg_in_waitrequest_4,
-
-  output          rcfg_out_read_4,
-  output          rcfg_out_write_4,
-  output  [11:0]  rcfg_out_address_4,
-  output  [31:0]  rcfg_out_writedata_4,
-  input   [31:0]  rcfg_out_readdata_4,
-  input           rcfg_out_waitrequest_4,
-
-  input           rcfg_in_read_5,
-  input           rcfg_in_write_5,
-  input   [11:0]  rcfg_in_address_5,
-  input   [31:0]  rcfg_in_writedata_5,
-  output  [31:0]  rcfg_in_readdata_5,
-  output          rcfg_in_waitrequest_5,
-
-  output          rcfg_out_read_5,
-  output          rcfg_out_write_5,
-  output  [11:0]  rcfg_out_address_5,
-  output  [31:0]  rcfg_out_writedata_5,
-  input   [31:0]  rcfg_out_readdata_5,
-  input           rcfg_out_waitrequest_5,
-
-  input           rcfg_in_read_6,
-  input           rcfg_in_write_6,
-  input   [11:0]  rcfg_in_address_6,
-  input   [31:0]  rcfg_in_writedata_6,
-  output  [31:0]  rcfg_in_readdata_6,
-  output          rcfg_in_waitrequest_6,
-
-  output          rcfg_out_read_6,
-  output          rcfg_out_write_6,
-  output  [11:0]  rcfg_out_address_6,
-  output  [31:0]  rcfg_out_writedata_6,
-  input   [31:0]  rcfg_out_readdata_6,
-  input           rcfg_out_waitrequest_6,
-
-  input           rcfg_in_read_7,
-  input           rcfg_in_write_7,
-  input   [11:0]  rcfg_in_address_7,
-  input   [31:0]  rcfg_in_writedata_7,
-  output  [31:0]  rcfg_in_readdata_7,
-  output          rcfg_in_waitrequest_7,
-
-  output          rcfg_out_read_7,
-  output          rcfg_out_write_7,
-  output  [11:0]  rcfg_out_address_7,
-  output  [31:0]  rcfg_out_writedata_7,
-  input   [31:0]  rcfg_out_readdata_7,
-  input           rcfg_out_waitrequest_7);
+  input           rcfg_out_waitrequest_1);
 
   // internal registers
 
-  reg     [11:0]  rcfg_out_address = 'd0;
-  reg     [31:0]  rcfg_out_writedata = 'd0;
-  reg             rcfg_out_iread_0 = 'd0;
-  reg             rcfg_out_iwrite_0 = 'd0;
-  reg     [31:0]  rcfg_in_ireaddata_0 = 'd0;
-  reg             rcfg_in_iwaitrequest_0 = 'd0;
-  reg             rcfg_out_iread_1 = 'd0;
-  reg             rcfg_out_iwrite_1 = 'd0;
-  reg     [31:0]  rcfg_in_ireaddata_1 = 'd0;
-  reg             rcfg_in_iwaitrequest_1 = 'd0;
-  reg             rcfg_out_iread_2 = 'd0;
-  reg             rcfg_out_iwrite_2 = 'd0;
-  reg     [31:0]  rcfg_in_ireaddata_2 = 'd0;
-  reg             rcfg_in_iwaitrequest_2 = 'd0;
-  reg             rcfg_out_iread_3 = 'd0;
-  reg             rcfg_out_iwrite_3 = 'd0;
-  reg     [31:0]  rcfg_in_ireaddata_3 = 'd0;
-  reg             rcfg_in_iwaitrequest_3 = 'd0;
-  reg             rcfg_out_iread_4 = 'd0;
-  reg             rcfg_out_iwrite_4 = 'd0;
-  reg     [31:0]  rcfg_in_ireaddata_4 = 'd0;
-  reg             rcfg_in_iwaitrequest_4 = 'd0;
-  reg             rcfg_out_iread_5 = 'd0;
-  reg             rcfg_out_iwrite_5 = 'd0;
-  reg     [31:0]  rcfg_in_ireaddata_5 = 'd0;
-  reg             rcfg_in_iwaitrequest_5 = 'd0;
-  reg             rcfg_out_iread_6 = 'd0;
-  reg             rcfg_out_iwrite_6 = 'd0;
-  reg     [31:0]  rcfg_in_ireaddata_6 = 'd0;
-  reg             rcfg_in_iwaitrequest_6 = 'd0;
-  reg             rcfg_out_iread_7 = 'd0;
-  reg             rcfg_out_iwrite_7 = 'd0;
-  reg     [31:0]  rcfg_in_ireaddata_7 = 'd0;
-  reg             rcfg_in_iwaitrequest_7 = 'd0;
-  reg     [ 3:0]  rcfg_select = 'd0;
+  reg     [ 1:0]  rcfg_select = 'd0;
+  reg             rcfg_read_int = 'd0;
+  reg             rcfg_write_int = 'd0;
+  reg     [ 9:0]  rcfg_address_int = 'd0;
+  reg     [31:0]  rcfg_writedata_int = 'd0;
+  reg     [31:0]  rcfg_readdata_int = 'd0;
+  reg             rcfg_waitrequest_int_0 = 'd0;
+  reg             rcfg_waitrequest_int_1 = 'd0;
 
   // internal signals
 
-  wire            rcfg_in_req_0_s;
-  wire            rcfg_in_req_1_s;
-  wire            rcfg_in_req_2_s;
-  wire            rcfg_in_req_3_s;
-  wire            rcfg_in_req_4_s;
-  wire            rcfg_in_req_5_s;
-  wire            rcfg_in_req_6_s;
-  wire            rcfg_in_req_7_s;
+  wire    [31:0]  rcfg_readdata_s;
+  wire            rcfg_waitrequest_s;
 
-  // xcvr sharing requires same bus with ONLY different write/read signals
+  // xcvr sharing requires same bus (sw must make sure they are mutually exclusive access).
 
-  assign rcfg_out_address_0 = rcfg_out_address;
-  assign rcfg_out_writedata_0 = rcfg_out_writedata;
-  assign rcfg_out_address_1 = rcfg_out_address;
-  assign rcfg_out_writedata_1 = rcfg_out_writedata;
-  assign rcfg_out_address_2 = rcfg_out_address;
-  assign rcfg_out_writedata_2 = rcfg_out_writedata;
-  assign rcfg_out_address_3 = rcfg_out_address;
-  assign rcfg_out_writedata_3 = rcfg_out_writedata;
-  assign rcfg_out_address_4 = rcfg_out_address;
-  assign rcfg_out_writedata_4 = rcfg_out_writedata;
-  assign rcfg_out_address_5 = rcfg_out_address;
-  assign rcfg_out_writedata_5 = rcfg_out_writedata;
-  assign rcfg_out_address_6 = rcfg_out_address;
-  assign rcfg_out_writedata_6 = rcfg_out_writedata;
-  assign rcfg_out_address_7 = rcfg_out_address;
-  assign rcfg_out_writedata_7 = rcfg_out_writedata;
+  assign rcfg_out_read_0 = rcfg_read_int;
+  assign rcfg_out_write_0 = rcfg_write_int;
+  assign rcfg_out_address_0 = rcfg_address_int;
+  assign rcfg_out_writedata_0 = rcfg_writedata_int;
+  assign rcfg_out_read_1 = rcfg_read_int;
+  assign rcfg_out_write_1 = rcfg_write_int;
+  assign rcfg_out_address_1 = rcfg_address_int;
+  assign rcfg_out_writedata_1 = rcfg_writedata_int;
+  assign rcfg_in_readdata_0 = rcfg_readdata_int;
+  assign rcfg_in_readdata_1 = rcfg_readdata_int;
+  assign rcfg_in_waitrequest_0 = rcfg_waitrequest_int_0;
+  assign rcfg_in_waitrequest_1 = rcfg_waitrequest_int_1;
+
+  assign rcfg_readdata_s = rcfg_out_readdata_1 & rcfg_out_readdata_0;
+  assign rcfg_waitrequest_s = rcfg_out_waitrequest_1 & rcfg_out_waitrequest_0;
 
   always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
     if (rcfg_reset_n == 0) begin
-      rcfg_out_address <= 12'd0;
-      rcfg_out_writedata <= 32'd0;
+      rcfg_select <= 2'd0;
+      rcfg_read_int <= 1'd0;
+      rcfg_write_int <= 1'd0;
+      rcfg_address_int <= 10'd0;
+      rcfg_writedata_int <= 32'd0;
+      rcfg_readdata_int = 32'd0;
+      rcfg_waitrequest_int_0 <= 1'b1;
+      rcfg_waitrequest_int_1 <= 1'b1;
     end else begin
-      case (rcfg_select)
-        4'h8: begin
-          rcfg_out_address <= rcfg_in_address_0;
-          rcfg_out_writedata <= rcfg_in_writedata_0;
+      if (rcfg_select[1] == 1'b1) begin
+        if (rcfg_waitrequest_s == 1'b0) begin
+          rcfg_select <= 2'd0;
+          rcfg_read_int <= 1'b0;
+          rcfg_write_int <= 1'b0;
+          rcfg_address_int <= 10'd0;
+          rcfg_writedata_int <= 32'd0;
         end
-        4'h9: begin
-          rcfg_out_address <= rcfg_in_address_1;
-          rcfg_out_writedata <= rcfg_in_writedata_1;
-        end
-        4'ha: begin
-          rcfg_out_address <= rcfg_in_address_2;
-          rcfg_out_writedata <= rcfg_in_writedata_2;
-        end
-        4'hb: begin
-          rcfg_out_address <= rcfg_in_address_3;
-          rcfg_out_writedata <= rcfg_in_writedata_3;
-        end
-        4'hc: begin
-          rcfg_out_address <= rcfg_in_address_4;
-          rcfg_out_writedata <= rcfg_in_writedata_4;
-        end
-        4'hd: begin
-          rcfg_out_address <= rcfg_in_address_5;
-          rcfg_out_writedata <= rcfg_in_writedata_5;
-        end
-        4'he: begin
-          rcfg_out_address <= rcfg_in_address_6;
-          rcfg_out_writedata <= rcfg_in_writedata_6;
-        end
-        4'hf: begin
-          rcfg_out_address <= rcfg_in_address_7;
-          rcfg_out_writedata <= rcfg_in_writedata_7;
-        end
-        default: begin
-          rcfg_out_address <= 12'd0;
-          rcfg_out_writedata <= 32'd0;
-        end
-      endcase
-    end
-  end
-
-  assign rcfg_out_read_0 = rcfg_out_iread_0;
-  assign rcfg_out_write_0 = rcfg_out_iwrite_0;
-  assign rcfg_in_readdata_0 = rcfg_in_ireaddata_0;
-  assign rcfg_in_waitrequest_0 = rcfg_in_iwaitrequest_0;
-  assign rcfg_out_read_1 = rcfg_out_iread_1;
-  assign rcfg_out_write_1 = rcfg_out_iwrite_1;
-  assign rcfg_in_readdata_1 = rcfg_in_ireaddata_1;
-  assign rcfg_in_waitrequest_1 = rcfg_in_iwaitrequest_1;
-  assign rcfg_out_read_2 = rcfg_out_iread_2;
-  assign rcfg_out_write_2 = rcfg_out_iwrite_2;
-  assign rcfg_in_readdata_2 = rcfg_in_ireaddata_2;
-  assign rcfg_in_waitrequest_2 = rcfg_in_iwaitrequest_2;
-  assign rcfg_out_read_3 = rcfg_out_iread_3;
-  assign rcfg_out_write_3 = rcfg_out_iwrite_3;
-  assign rcfg_in_readdata_3 = rcfg_in_ireaddata_3;
-  assign rcfg_in_waitrequest_3 = rcfg_in_iwaitrequest_3;
-  assign rcfg_out_read_4 = rcfg_out_iread_4;
-  assign rcfg_out_write_4 = rcfg_out_iwrite_4;
-  assign rcfg_in_readdata_4 = rcfg_in_ireaddata_4;
-  assign rcfg_in_waitrequest_4 = rcfg_in_iwaitrequest_4;
-  assign rcfg_out_read_5 = rcfg_out_iread_5;
-  assign rcfg_out_write_5 = rcfg_out_iwrite_5;
-  assign rcfg_in_readdata_5 = rcfg_in_ireaddata_5;
-  assign rcfg_in_waitrequest_5 = rcfg_in_iwaitrequest_5;
-  assign rcfg_out_read_6 = rcfg_out_iread_6;
-  assign rcfg_out_write_6 = rcfg_out_iwrite_6;
-  assign rcfg_in_readdata_6 = rcfg_in_ireaddata_6;
-  assign rcfg_in_waitrequest_6 = rcfg_in_iwaitrequest_6;
-  assign rcfg_out_read_7 = rcfg_out_iread_7;
-  assign rcfg_out_write_7 = rcfg_out_iwrite_7;
-  assign rcfg_in_readdata_7 = rcfg_in_ireaddata_7;
-  assign rcfg_in_waitrequest_7 = rcfg_in_iwaitrequest_7;
-
-  always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
-    if (rcfg_reset_n == 0) begin
-      rcfg_out_iread_0 <= 1'd0;
-      rcfg_out_iwrite_0 <= 1'd0;
-      rcfg_in_ireaddata_0 <= 32'd0;
-      rcfg_in_iwaitrequest_0 <= 1'd1;
-      rcfg_out_iread_1 <= 1'd0;
-      rcfg_out_iwrite_1 <= 1'd0;
-      rcfg_in_ireaddata_1 <= 32'd0;
-      rcfg_in_iwaitrequest_1 <= 1'd1;
-      rcfg_out_iread_2 <= 1'd0;
-      rcfg_out_iwrite_2 <= 1'd0;
-      rcfg_in_ireaddata_2 <= 32'd0;
-      rcfg_in_iwaitrequest_2 <= 1'd1;
-      rcfg_out_iread_3 <= 1'd0;
-      rcfg_out_iwrite_3 <= 1'd0;
-      rcfg_in_ireaddata_3 <= 32'd0;
-      rcfg_in_iwaitrequest_3 <= 1'd1;
-      rcfg_out_iread_4 <= 1'd0;
-      rcfg_out_iwrite_4 <= 1'd0;
-      rcfg_in_ireaddata_4 <= 32'd0;
-      rcfg_in_iwaitrequest_4 <= 1'd1;
-      rcfg_out_iread_5 <= 1'd0;
-      rcfg_out_iwrite_5 <= 1'd0;
-      rcfg_in_ireaddata_5 <= 32'd0;
-      rcfg_in_iwaitrequest_5 <= 1'd1;
-      rcfg_out_iread_6 <= 1'd0;
-      rcfg_out_iwrite_6 <= 1'd0;
-      rcfg_in_ireaddata_6 <= 32'd0;
-      rcfg_in_iwaitrequest_6 <= 1'd1;
-      rcfg_out_iread_7 <= 1'd0;
-      rcfg_out_iwrite_7 <= 1'd0;
-      rcfg_in_ireaddata_7 <= 32'd0;
-      rcfg_in_iwaitrequest_7 <= 1'd1;
-    end else begin
-      if (rcfg_select == 4'h8) begin
-        rcfg_out_iread_0 <= rcfg_in_read_0;
-        rcfg_out_iwrite_0 <= rcfg_in_write_0;
-        rcfg_in_ireaddata_0 <= rcfg_out_readdata_0;
-        rcfg_in_iwaitrequest_0 <= rcfg_out_waitrequest_0 | ~rcfg_in_req_0_s;
+        rcfg_readdata_int = rcfg_readdata_s;
+        rcfg_waitrequest_int_0 <= rcfg_waitrequest_s | rcfg_select[0];
+        rcfg_waitrequest_int_1 <= rcfg_waitrequest_s | ~rcfg_select[0];
+      end else if ((rcfg_in_read_0 == 1'b1) || (rcfg_in_write_0 == 1'b1)) begin
+        rcfg_select <= 2'b10;
+        rcfg_read_int <= rcfg_in_read_0;
+        rcfg_write_int <= rcfg_in_write_0;
+        rcfg_address_int <= rcfg_in_address_0;
+        rcfg_writedata_int <= rcfg_in_writedata_0;
+        rcfg_readdata_int = 32'd0;
+        rcfg_waitrequest_int_0 <= 1'b1;
+        rcfg_waitrequest_int_1 <= 1'b1;
+      end else if ((rcfg_in_read_1 == 1'b1) || (rcfg_in_write_1 == 1'b1)) begin
+        rcfg_select <= 2'b11;
+        rcfg_read_int <= rcfg_in_read_1;
+        rcfg_write_int <= rcfg_in_write_1;
+        rcfg_address_int <= rcfg_in_address_1;
+        rcfg_writedata_int <= rcfg_in_writedata_1;
+        rcfg_readdata_int = 32'd0;
+        rcfg_waitrequest_int_0 <= 1'b1;
+        rcfg_waitrequest_int_1 <= 1'b1;
       end else begin
-        rcfg_out_iread_0 <= 1'd0;
-        rcfg_out_iwrite_0 <= 1'd0;
-        rcfg_in_ireaddata_0 <= 32'd0;
-        rcfg_in_iwaitrequest_0 <= 1'd1;
+        rcfg_select <= 2'd0;
+        rcfg_read_int <= 1'd0;
+        rcfg_write_int <= 1'd0;
+        rcfg_address_int <= 10'd0;
+        rcfg_writedata_int <= 32'd0;
+        rcfg_readdata_int = 32'd0;
+        rcfg_waitrequest_int_0 <= 1'b1;
+        rcfg_waitrequest_int_1 <= 1'b1;
       end
-      if (rcfg_select == 4'h9) begin
-        rcfg_out_iread_1 <= rcfg_in_read_1;
-        rcfg_out_iwrite_1 <= rcfg_in_write_1;
-        rcfg_in_ireaddata_1 <= rcfg_out_readdata_1;
-        rcfg_in_iwaitrequest_1 <= rcfg_out_waitrequest_1 | ~rcfg_in_req_1_s;
-      end else begin
-        rcfg_out_iread_1 <= 1'd0;
-        rcfg_out_iwrite_1 <= 1'd0;
-        rcfg_in_ireaddata_1 <= 32'd0;
-        rcfg_in_iwaitrequest_1 <= 1'd1;
-      end
-      if (rcfg_select == 4'ha) begin
-        rcfg_out_iread_2 <= rcfg_in_read_2;
-        rcfg_out_iwrite_2 <= rcfg_in_write_2;
-        rcfg_in_ireaddata_2 <= rcfg_out_readdata_2;
-        rcfg_in_iwaitrequest_2 <= rcfg_out_waitrequest_2 | ~rcfg_in_req_2_s;
-      end else begin
-        rcfg_out_iread_2 <= 1'd0;
-        rcfg_out_iwrite_2 <= 1'd0;
-        rcfg_in_ireaddata_2 <= 32'd0;
-        rcfg_in_iwaitrequest_2 <= 1'd1;
-      end
-      if (rcfg_select == 4'hb) begin
-        rcfg_out_iread_3 <= rcfg_in_read_3;
-        rcfg_out_iwrite_3 <= rcfg_in_write_3;
-        rcfg_in_ireaddata_3 <= rcfg_out_readdata_3;
-        rcfg_in_iwaitrequest_3 <= rcfg_out_waitrequest_3 | ~rcfg_in_req_3_s;
-      end else begin
-        rcfg_out_iread_3 <= 1'd0;
-        rcfg_out_iwrite_3 <= 1'd0;
-        rcfg_in_ireaddata_3 <= 32'd0;
-        rcfg_in_iwaitrequest_3 <= 1'd1;
-      end
-      if (rcfg_select == 4'hc) begin
-        rcfg_out_iread_4 <= rcfg_in_read_4;
-        rcfg_out_iwrite_4 <= rcfg_in_write_4;
-        rcfg_in_ireaddata_4 <= rcfg_out_readdata_4;
-        rcfg_in_iwaitrequest_4 <= rcfg_out_waitrequest_4 | ~rcfg_in_req_4_s;
-      end else begin
-        rcfg_out_iread_4 <= 1'd0;
-        rcfg_out_iwrite_4 <= 1'd0;
-        rcfg_in_ireaddata_4 <= 32'd0;
-        rcfg_in_iwaitrequest_4 <= 1'd1;
-      end
-      if (rcfg_select == 4'hd) begin
-        rcfg_out_iread_5 <= rcfg_in_read_5;
-        rcfg_out_iwrite_5 <= rcfg_in_write_5;
-        rcfg_in_ireaddata_5 <= rcfg_out_readdata_5;
-        rcfg_in_iwaitrequest_5 <= rcfg_out_waitrequest_5 | ~rcfg_in_req_5_s;
-      end else begin
-        rcfg_out_iread_5 <= 1'd0;
-        rcfg_out_iwrite_5 <= 1'd0;
-        rcfg_in_ireaddata_5 <= 32'd0;
-        rcfg_in_iwaitrequest_5 <= 1'd1;
-      end
-      if (rcfg_select == 4'he) begin
-        rcfg_out_iread_6 <= rcfg_in_read_6;
-        rcfg_out_iwrite_6 <= rcfg_in_write_6;
-        rcfg_in_ireaddata_6 <= rcfg_out_readdata_6;
-        rcfg_in_iwaitrequest_6 <= rcfg_out_waitrequest_6 | ~rcfg_in_req_6_s;
-      end else begin
-        rcfg_out_iread_6 <= 1'd0;
-        rcfg_out_iwrite_6 <= 1'd0;
-        rcfg_in_ireaddata_6 <= 32'd0;
-        rcfg_in_iwaitrequest_6 <= 1'd1;
-      end
-      if (rcfg_select == 4'hf) begin
-        rcfg_out_iread_7 <= rcfg_in_read_7;
-        rcfg_out_iwrite_7 <= rcfg_in_write_7;
-        rcfg_in_ireaddata_7 <= rcfg_out_readdata_7;
-        rcfg_in_iwaitrequest_7 <= rcfg_out_waitrequest_7 | ~rcfg_in_req_7_s;
-      end else begin
-        rcfg_out_iread_7 <= 1'd0;
-        rcfg_out_iwrite_7 <= 1'd0;
-        rcfg_in_ireaddata_7 <= 32'd0;
-        rcfg_in_iwaitrequest_7 <= 1'd1;
-      end
-    end
-  end
-
-  assign rcfg_in_req_0_s = rcfg_in_read_0 | rcfg_in_write_0;
-  assign rcfg_in_req_1_s = rcfg_in_read_1 | rcfg_in_write_1;
-  assign rcfg_in_req_2_s = rcfg_in_read_2 | rcfg_in_write_2;
-  assign rcfg_in_req_3_s = rcfg_in_read_3 | rcfg_in_write_3;
-  assign rcfg_in_req_4_s = rcfg_in_read_4 | rcfg_in_write_4;
-  assign rcfg_in_req_5_s = rcfg_in_read_5 | rcfg_in_write_5;
-  assign rcfg_in_req_6_s = rcfg_in_read_6 | rcfg_in_write_6;
-  assign rcfg_in_req_7_s = rcfg_in_read_7 | rcfg_in_write_7;
-
-  always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
-    if (rcfg_reset_n == 0) begin
-      rcfg_select <= 4'h0;
-    end else begin
-      case (rcfg_select)
-        4'h8: begin
-          if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-        4'h9: begin
-          if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-        4'ha: begin
-          if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-        4'hb: begin
-          if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-        4'hc: begin
-          if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-        4'hd: begin
-          if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-        4'he: begin
-          if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-        4'hf: begin
-          if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-        default: begin
-          if (rcfg_in_req_0_s == 1'b1) begin
-            rcfg_select <= 4'h8;
-          end else if (rcfg_in_req_1_s == 1'b1) begin
-            rcfg_select <= 4'h9;
-          end else if (rcfg_in_req_2_s == 1'b1) begin
-            rcfg_select <= 4'ha;
-          end else if (rcfg_in_req_3_s == 1'b1) begin
-            rcfg_select <= 4'hb;
-          end else if (rcfg_in_req_4_s == 1'b1) begin
-            rcfg_select <= 4'hc;
-          end else if (rcfg_in_req_5_s == 1'b1) begin
-            rcfg_select <= 4'hd;
-          end else if (rcfg_in_req_6_s == 1'b1) begin
-            rcfg_select <= 4'he;
-          end else if (rcfg_in_req_7_s == 1'b1) begin
-            rcfg_select <= 4'hf;
-          end else begin
-            rcfg_select <= 4'h0;
-          end
-        end
-      endcase
     end
   end
 
diff --git a/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl b/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
index 9cc4ce9e0..6577b976f 100644
--- a/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
+++ b/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
@@ -6,7 +6,6 @@ set_module_property DESCRIPTION "Avalon ADXCFG Core"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
 set_module_property DISPLAY_NAME avl_adxcfg
-set_module_property ELABORATION_CALLBACK p_avl_adxcfg
 
 # files
 
@@ -14,14 +13,6 @@ add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL avl_adxcfg
 add_fileset_file avl_adxcfg.v VERILOG PATH avl_adxcfg.v TOP_LEVEL_FILE
 
-# parameters
-
-add_parameter NUM_OF_CORES INTEGER 0
-set_parameter_property NUM_OF_CORES DISPLAY_NAME NUM_OF_CORES
-set_parameter_property NUM_OF_CORES TYPE INTEGER
-set_parameter_property NUM_OF_CORES UNITS None
-set_parameter_property NUM_OF_CORES HDL_PARAMETER false
-
 # reconfiguration interfaces
 
 add_interface rcfg_clk  clock sink
@@ -31,42 +22,34 @@ add_interface rcfg_reset_n reset end
 set_interface_property rcfg_reset_n associatedClock rcfg_clk
 add_interface_port rcfg_reset_n rcfg_reset_n reset_n Input 1
 
-proc p_avl_adxcfg {} {
+for {set n 0} {$n < 2} {incr n} {
 
-  set m_num_of_cores [get_parameter_value NUM_OF_CORES]
+  add_interface rcfg_s${n} avalon slave
+  add_interface rcfg_m${n} avalon master
 
-  if {$m_num_of_cores > 8} {
-    set m_num_of_cores 8
-  }
+  add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
+  add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
+  add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 10
+  add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
+  add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
+  add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
+  add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
+  add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
+  add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 10
+  add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
+  add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
+  add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
 
-  for {set n 0} {$n < $m_num_of_cores} {incr n} {
-
-    add_interface rcfg_s${n} avalon slave
-    add_interface rcfg_m${n} avalon master
-
-    add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
-    add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
-    add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 12
-    add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
-    add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
-    add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
-    add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
-    add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
-    add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 12
-    add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
-    add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
-    add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
-
-    set_interface_property rcfg_s${n} associatedClock rcfg_clk
-    set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
-    set_interface_property rcfg_s${n} addressUnits WORDS
-    set_interface_property rcfg_s${n} burstCountUnits WORDS
-    set_interface_property rcfg_s${n} explicitAddressSpan 0
-    set_interface_property rcfg_m${n} associatedClock rcfg_clk
-    set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
-    set_interface_property rcfg_m${n} addressUnits WORDS
-    set_interface_property rcfg_m${n} burstCountUnits WORDS
-  }
+  set_interface_property rcfg_s${n} associatedClock rcfg_clk
+  set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
+  set_interface_property rcfg_s${n} addressUnits WORDS
+  set_interface_property rcfg_s${n} burstCountUnits WORDS
+  set_interface_property rcfg_s${n} explicitAddressSpan 0
+  set_interface_property rcfg_m${n} associatedClock rcfg_clk
+  set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
+  set_interface_property rcfg_m${n} addressUnits WORDS
+  set_interface_property rcfg_m${n} burstCountUnits WORDS
 }
 
 
+

From 8718b7f4771c8ae166d5c0282b9fb1c8fbecef1f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:46:19 -0400
Subject: [PATCH 464/972] avl_adxphy- ip/phy split

---
 library/altera/avl_adxphy/avl_adxphy.v      | 196 +++++++++++++++++---
 library/altera/avl_adxphy/avl_adxphy_hw.tcl |  12 +-
 2 files changed, 182 insertions(+), 26 deletions(-)

diff --git a/library/altera/avl_adxphy/avl_adxphy.v b/library/altera/avl_adxphy/avl_adxphy.v
index eefcd0173..36428fa2d 100644
--- a/library/altera/avl_adxphy/avl_adxphy.v
+++ b/library/altera/avl_adxphy/avl_adxphy.v
@@ -73,6 +73,8 @@ module avl_adxphy (
   output                              rx_phy_lane_powerdown_0,
   output                              rx_phy_bit_reversal_0,
   output                              rx_phy_byte_reversal_0,
+  output                              rx_phy_analogreset_0,
+  output                              rx_phy_digitalreset_0,
 
   input                               rx_phy_locked_1,
   input                               rx_phy_cal_busy_1,
@@ -88,6 +90,8 @@ module avl_adxphy (
   output                              rx_phy_lane_powerdown_1,
   output                              rx_phy_bit_reversal_1,
   output                              rx_phy_byte_reversal_1,
+  output                              rx_phy_analogreset_1,
+  output                              rx_phy_digitalreset_1,
 
   input                               rx_phy_locked_2,
   input                               rx_phy_cal_busy_2,
@@ -103,6 +107,8 @@ module avl_adxphy (
   output                              rx_phy_lane_powerdown_2,
   output                              rx_phy_bit_reversal_2,
   output                              rx_phy_byte_reversal_2,
+  output                              rx_phy_analogreset_2,
+  output                              rx_phy_digitalreset_2,
 
   input                               rx_phy_locked_3,
   input                               rx_phy_cal_busy_3,
@@ -118,6 +124,8 @@ module avl_adxphy (
   output                              rx_phy_lane_powerdown_3,
   output                              rx_phy_bit_reversal_3,
   output                              rx_phy_byte_reversal_3,
+  output                              rx_phy_analogreset_3,
+  output                              rx_phy_digitalreset_3,
 
   input                               rx_phy_locked_4,
   input                               rx_phy_cal_busy_4,
@@ -133,6 +141,8 @@ module avl_adxphy (
   output                              rx_phy_lane_powerdown_4,
   output                              rx_phy_bit_reversal_4,
   output                              rx_phy_byte_reversal_4,
+  output                              rx_phy_analogreset_4,
+  output                              rx_phy_digitalreset_4,
 
   input                               rx_phy_locked_5,
   input                               rx_phy_cal_busy_5,
@@ -148,6 +158,8 @@ module avl_adxphy (
   output                              rx_phy_lane_powerdown_5,
   output                              rx_phy_bit_reversal_5,
   output                              rx_phy_byte_reversal_5,
+  output                              rx_phy_analogreset_5,
+  output                              rx_phy_digitalreset_5,
 
   input                               rx_phy_locked_6,
   input                               rx_phy_cal_busy_6,
@@ -163,6 +175,8 @@ module avl_adxphy (
   output                              rx_phy_lane_powerdown_6,
   output                              rx_phy_bit_reversal_6,
   output                              rx_phy_byte_reversal_6,
+  output                              rx_phy_analogreset_6,
+  output                              rx_phy_digitalreset_6,
 
   input                               rx_phy_locked_7,
   input                               rx_phy_cal_busy_7,
@@ -178,9 +192,13 @@ module avl_adxphy (
   output                              rx_phy_lane_powerdown_7,
   output                              rx_phy_bit_reversal_7,
   output                              rx_phy_byte_reversal_7,
+  output                              rx_phy_analogreset_7,
+  output                              rx_phy_digitalreset_7,
 
   // rx-core interface
 
+  input   [((NUM_OF_LANES* 1)-1):0]   rx_core_analogreset,
+  input   [((NUM_OF_LANES* 1)-1):0]   rx_core_digitalreset,
   output  [((NUM_OF_LANES* 1)-1):0]   rx_core_locked,
   output  [((NUM_OF_LANES* 1)-1):0]   rx_core_cal_busy,
 
@@ -251,6 +269,8 @@ module avl_adxphy (
   output                              tx_phy_lane_powerdown_0,
   output                              tx_phy_bit_reversal_0,
   output                              tx_phy_byte_reversal_0,
+  output                              tx_phy_analogreset_0,
+  output                              tx_phy_digitalreset_0,
 
   input                               tx_phy_cal_busy_1,
   input                               tx_phy_full_1,
@@ -262,6 +282,8 @@ module avl_adxphy (
   output                              tx_phy_lane_powerdown_1,
   output                              tx_phy_bit_reversal_1,
   output                              tx_phy_byte_reversal_1,
+  output                              tx_phy_analogreset_1,
+  output                              tx_phy_digitalreset_1,
 
   input                               tx_phy_cal_busy_2,
   input                               tx_phy_full_2,
@@ -273,6 +295,8 @@ module avl_adxphy (
   output                              tx_phy_lane_powerdown_2,
   output                              tx_phy_bit_reversal_2,
   output                              tx_phy_byte_reversal_2,
+  output                              tx_phy_analogreset_2,
+  output                              tx_phy_digitalreset_2,
 
   input                               tx_phy_cal_busy_3,
   input                               tx_phy_full_3,
@@ -284,6 +308,8 @@ module avl_adxphy (
   output                              tx_phy_lane_powerdown_3,
   output                              tx_phy_bit_reversal_3,
   output                              tx_phy_byte_reversal_3,
+  output                              tx_phy_analogreset_3,
+  output                              tx_phy_digitalreset_3,
 
   input                               tx_phy_cal_busy_4,
   input                               tx_phy_full_4,
@@ -295,6 +321,8 @@ module avl_adxphy (
   output                              tx_phy_lane_powerdown_4,
   output                              tx_phy_bit_reversal_4,
   output                              tx_phy_byte_reversal_4,
+  output                              tx_phy_analogreset_4,
+  output                              tx_phy_digitalreset_4,
 
   input                               tx_phy_cal_busy_5,
   input                               tx_phy_full_5,
@@ -306,6 +334,8 @@ module avl_adxphy (
   output                              tx_phy_lane_powerdown_5,
   output                              tx_phy_bit_reversal_5,
   output                              tx_phy_byte_reversal_5,
+  output                              tx_phy_analogreset_5,
+  output                              tx_phy_digitalreset_5,
 
   input                               tx_phy_cal_busy_6,
   input                               tx_phy_full_6,
@@ -317,6 +347,8 @@ module avl_adxphy (
   output                              tx_phy_lane_powerdown_6,
   output                              tx_phy_bit_reversal_6,
   output                              tx_phy_byte_reversal_6,
+  output                              tx_phy_analogreset_6,
+  output                              tx_phy_digitalreset_6,
 
   input                               tx_phy_cal_busy_7,
   input                               tx_phy_full_7,
@@ -328,9 +360,13 @@ module avl_adxphy (
   output                              tx_phy_lane_powerdown_7,
   output                              tx_phy_bit_reversal_7,
   output                              tx_phy_byte_reversal_7,
+  output                              tx_phy_analogreset_7,
+  output                              tx_phy_digitalreset_7,
 
   // tx-core interface
 
+  input   [((NUM_OF_LANES* 1)-1):0]   tx_core_analogreset,
+  input   [((NUM_OF_LANES* 1)-1):0]   tx_core_digitalreset,
   output  [((NUM_OF_LANES* 1)-1):0]   tx_core_cal_busy);
 
   // parameters
@@ -347,9 +383,9 @@ module avl_adxphy (
   assign rx_ip_cal_busy[0] = rx_phy_cal_busy_0;
   assign rx_ip_valid[0] = rx_phy_valid_0;
   assign rx_ip_data[((32*1)-1):(32*0)] = rx_phy_data_0;
-  assign rx_ip_disperr[((32*1)-1):(32*0)] = rx_phy_disperr_0;
-  assign rx_ip_deterr[((32*1)-1):(32*0)] = rx_phy_deterr_0;
-  assign rx_ip_kchar[((32*1)-1):(32*0)] = rx_phy_kchar_0;
+  assign rx_ip_disperr[((4*1)-1):(4*0)] = rx_phy_disperr_0;
+  assign rx_ip_deterr[((4*1)-1):(4*0)] = rx_phy_deterr_0;
+  assign rx_ip_kchar[((4*1)-1):(4*0)] = rx_phy_kchar_0;
   assign rx_ip_full[0] = rx_phy_full_0;
   assign rx_ip_empty[0] = rx_phy_empty_0;
   end
@@ -360,10 +396,14 @@ module avl_adxphy (
   assign rx_phy_align_en_0 = rx_ip_align_en[0];
   assign rx_phy_lane_polarity_0 = rx_ip_lane_polarity[0];
   assign rx_phy_lane_powerdown_0 = rx_ip_lane_powerdown[0];
+  assign rx_phy_analogreset_0 = rx_core_analogreset[0];
+  assign rx_phy_digitalreset_0 = rx_core_digitalreset[0];
   end else begin
   assign rx_phy_align_en_0 = 1'd0;
   assign rx_phy_lane_polarity_0 = 1'd0;
   assign rx_phy_lane_powerdown_0 = 1'd0;
+  assign rx_phy_analogreset_0 = 1'd1;
+  assign rx_phy_digitalreset_0 = 1'd1;
   end
   endgenerate
 
@@ -378,9 +418,9 @@ module avl_adxphy (
   assign rx_ip_cal_busy[1] = rx_phy_cal_busy_1;
   assign rx_ip_valid[1] = rx_phy_valid_1;
   assign rx_ip_data[((32*2)-1):(32*1)] = rx_phy_data_1;
-  assign rx_ip_disperr[((32*2)-1):(32*1)] = rx_phy_disperr_1;
-  assign rx_ip_deterr[((32*2)-1):(32*1)] = rx_phy_deterr_1;
-  assign rx_ip_kchar[((32*2)-1):(32*1)] = rx_phy_kchar_1;
+  assign rx_ip_disperr[((4*2)-1):(4*1)] = rx_phy_disperr_1;
+  assign rx_ip_deterr[((4*2)-1):(4*1)] = rx_phy_deterr_1;
+  assign rx_ip_kchar[((4*2)-1):(4*1)] = rx_phy_kchar_1;
   assign rx_ip_full[1] = rx_phy_full_1;
   assign rx_ip_empty[1] = rx_phy_empty_1;
   end
@@ -391,10 +431,14 @@ module avl_adxphy (
   assign rx_phy_align_en_1 = rx_ip_align_en[1];
   assign rx_phy_lane_polarity_1 = rx_ip_lane_polarity[1];
   assign rx_phy_lane_powerdown_1 = rx_ip_lane_powerdown[1];
+  assign rx_phy_analogreset_1 = rx_core_analogreset[1];
+  assign rx_phy_digitalreset_1 = rx_core_digitalreset[1];
   end else begin
   assign rx_phy_align_en_1 = 1'd0;
   assign rx_phy_lane_polarity_1 = 1'd0;
   assign rx_phy_lane_powerdown_1 = 1'd0;
+  assign rx_phy_analogreset_1 = 1'd1;
+  assign rx_phy_digitalreset_1 = 1'd1;
   end
   endgenerate
 
@@ -409,9 +453,9 @@ module avl_adxphy (
   assign rx_ip_cal_busy[2] = rx_phy_cal_busy_2;
   assign rx_ip_valid[2] = rx_phy_valid_2;
   assign rx_ip_data[((32*3)-1):(32*2)] = rx_phy_data_2;
-  assign rx_ip_disperr[((32*3)-1):(32*2)] = rx_phy_disperr_2;
-  assign rx_ip_deterr[((32*3)-1):(32*2)] = rx_phy_deterr_2;
-  assign rx_ip_kchar[((32*3)-1):(32*2)] = rx_phy_kchar_2;
+  assign rx_ip_disperr[((4*3)-1):(4*2)] = rx_phy_disperr_2;
+  assign rx_ip_deterr[((4*3)-1):(4*2)] = rx_phy_deterr_2;
+  assign rx_ip_kchar[((4*3)-1):(4*2)] = rx_phy_kchar_2;
   assign rx_ip_full[2] = rx_phy_full_2;
   assign rx_ip_empty[2] = rx_phy_empty_2;
   end
@@ -422,10 +466,14 @@ module avl_adxphy (
   assign rx_phy_align_en_2 = rx_ip_align_en[2];
   assign rx_phy_lane_polarity_2 = rx_ip_lane_polarity[2];
   assign rx_phy_lane_powerdown_2 = rx_ip_lane_powerdown[2];
+  assign rx_phy_analogreset_2 = rx_core_analogreset[2];
+  assign rx_phy_digitalreset_2 = rx_core_digitalreset[2];
   end else begin
   assign rx_phy_align_en_2 = 1'd0;
   assign rx_phy_lane_polarity_2 = 1'd0;
   assign rx_phy_lane_powerdown_2 = 1'd0;
+  assign rx_phy_analogreset_2 = 1'd1;
+  assign rx_phy_digitalreset_2 = 1'd1;
   end
   endgenerate
 
@@ -440,9 +488,9 @@ module avl_adxphy (
   assign rx_ip_cal_busy[3] = rx_phy_cal_busy_3;
   assign rx_ip_valid[3] = rx_phy_valid_3;
   assign rx_ip_data[((32*4)-1):(32*3)] = rx_phy_data_3;
-  assign rx_ip_disperr[((32*4)-1):(32*3)] = rx_phy_disperr_3;
-  assign rx_ip_deterr[((32*4)-1):(32*3)] = rx_phy_deterr_3;
-  assign rx_ip_kchar[((32*4)-1):(32*3)] = rx_phy_kchar_3;
+  assign rx_ip_disperr[((4*4)-1):(4*3)] = rx_phy_disperr_3;
+  assign rx_ip_deterr[((4*4)-1):(4*3)] = rx_phy_deterr_3;
+  assign rx_ip_kchar[((4*4)-1):(4*3)] = rx_phy_kchar_3;
   assign rx_ip_full[3] = rx_phy_full_3;
   assign rx_ip_empty[3] = rx_phy_empty_3;
   end
@@ -453,10 +501,14 @@ module avl_adxphy (
   assign rx_phy_align_en_3 = rx_ip_align_en[3];
   assign rx_phy_lane_polarity_3 = rx_ip_lane_polarity[3];
   assign rx_phy_lane_powerdown_3 = rx_ip_lane_powerdown[3];
+  assign rx_phy_analogreset_3 = rx_core_analogreset[3];
+  assign rx_phy_digitalreset_3 = rx_core_digitalreset[3];
   end else begin
   assign rx_phy_align_en_3 = 1'd0;
   assign rx_phy_lane_polarity_3 = 1'd0;
   assign rx_phy_lane_powerdown_3 = 1'd0;
+  assign rx_phy_analogreset_3 = 1'd1;
+  assign rx_phy_digitalreset_3 = 1'd1;
   end
   endgenerate
 
@@ -471,9 +523,9 @@ module avl_adxphy (
   assign rx_ip_cal_busy[4] = rx_phy_cal_busy_4;
   assign rx_ip_valid[4] = rx_phy_valid_4;
   assign rx_ip_data[((32*5)-1):(32*4)] = rx_phy_data_4;
-  assign rx_ip_disperr[((32*5)-1):(32*4)] = rx_phy_disperr_4;
-  assign rx_ip_deterr[((32*5)-1):(32*4)] = rx_phy_deterr_4;
-  assign rx_ip_kchar[((32*5)-1):(32*4)] = rx_phy_kchar_4;
+  assign rx_ip_disperr[((4*5)-1):(4*4)] = rx_phy_disperr_4;
+  assign rx_ip_deterr[((4*5)-1):(4*4)] = rx_phy_deterr_4;
+  assign rx_ip_kchar[((4*5)-1):(4*4)] = rx_phy_kchar_4;
   assign rx_ip_full[4] = rx_phy_full_4;
   assign rx_ip_empty[4] = rx_phy_empty_4;
   end
@@ -484,10 +536,14 @@ module avl_adxphy (
   assign rx_phy_align_en_4 = rx_ip_align_en[4];
   assign rx_phy_lane_polarity_4 = rx_ip_lane_polarity[4];
   assign rx_phy_lane_powerdown_4 = rx_ip_lane_powerdown[4];
+  assign rx_phy_analogreset_4 = rx_core_analogreset[4];
+  assign rx_phy_digitalreset_4 = rx_core_digitalreset[4];
   end else begin
   assign rx_phy_align_en_4 = 1'd0;
   assign rx_phy_lane_polarity_4 = 1'd0;
   assign rx_phy_lane_powerdown_4 = 1'd0;
+  assign rx_phy_analogreset_4 = 1'd1;
+  assign rx_phy_digitalreset_4 = 1'd1;
   end
   endgenerate
 
@@ -502,9 +558,9 @@ module avl_adxphy (
   assign rx_ip_cal_busy[5] = rx_phy_cal_busy_5;
   assign rx_ip_valid[5] = rx_phy_valid_5;
   assign rx_ip_data[((32*6)-1):(32*5)] = rx_phy_data_5;
-  assign rx_ip_disperr[((32*6)-1):(32*5)] = rx_phy_disperr_5;
-  assign rx_ip_deterr[((32*6)-1):(32*5)] = rx_phy_deterr_5;
-  assign rx_ip_kchar[((32*6)-1):(32*5)] = rx_phy_kchar_5;
+  assign rx_ip_disperr[((4*6)-1):(4*5)] = rx_phy_disperr_5;
+  assign rx_ip_deterr[((4*6)-1):(4*5)] = rx_phy_deterr_5;
+  assign rx_ip_kchar[((4*6)-1):(4*5)] = rx_phy_kchar_5;
   assign rx_ip_full[5] = rx_phy_full_5;
   assign rx_ip_empty[5] = rx_phy_empty_5;
   end
@@ -515,10 +571,14 @@ module avl_adxphy (
   assign rx_phy_align_en_5 = rx_ip_align_en[5];
   assign rx_phy_lane_polarity_5 = rx_ip_lane_polarity[5];
   assign rx_phy_lane_powerdown_5 = rx_ip_lane_powerdown[5];
+  assign rx_phy_analogreset_5 = rx_core_analogreset[5];
+  assign rx_phy_digitalreset_5 = rx_core_digitalreset[5];
   end else begin
   assign rx_phy_align_en_5 = 1'd0;
   assign rx_phy_lane_polarity_5 = 1'd0;
   assign rx_phy_lane_powerdown_5 = 1'd0;
+  assign rx_phy_analogreset_5 = 1'd1;
+  assign rx_phy_digitalreset_5 = 1'd1;
   end
   endgenerate
 
@@ -533,9 +593,9 @@ module avl_adxphy (
   assign rx_ip_cal_busy[6] = rx_phy_cal_busy_6;
   assign rx_ip_valid[6] = rx_phy_valid_6;
   assign rx_ip_data[((32*7)-1):(32*6)] = rx_phy_data_6;
-  assign rx_ip_disperr[((32*7)-1):(32*6)] = rx_phy_disperr_6;
-  assign rx_ip_deterr[((32*7)-1):(32*6)] = rx_phy_deterr_6;
-  assign rx_ip_kchar[((32*7)-1):(32*6)] = rx_phy_kchar_6;
+  assign rx_ip_disperr[((4*7)-1):(4*6)] = rx_phy_disperr_6;
+  assign rx_ip_deterr[((4*7)-1):(4*6)] = rx_phy_deterr_6;
+  assign rx_ip_kchar[((4*7)-1):(4*6)] = rx_phy_kchar_6;
   assign rx_ip_full[6] = rx_phy_full_6;
   assign rx_ip_empty[6] = rx_phy_empty_6;
   end
@@ -546,10 +606,14 @@ module avl_adxphy (
   assign rx_phy_align_en_6 = rx_ip_align_en[6];
   assign rx_phy_lane_polarity_6 = rx_ip_lane_polarity[6];
   assign rx_phy_lane_powerdown_6 = rx_ip_lane_powerdown[6];
+  assign rx_phy_analogreset_6 = rx_core_analogreset[6];
+  assign rx_phy_digitalreset_6 = rx_core_digitalreset[6];
   end else begin
   assign rx_phy_align_en_6 = 1'd0;
   assign rx_phy_lane_polarity_6 = 1'd0;
   assign rx_phy_lane_powerdown_6 = 1'd0;
+  assign rx_phy_analogreset_6 = 1'd1;
+  assign rx_phy_digitalreset_6 = 1'd1;
   end
   endgenerate
 
@@ -564,9 +628,9 @@ module avl_adxphy (
   assign rx_ip_cal_busy[7] = rx_phy_cal_busy_7;
   assign rx_ip_valid[7] = rx_phy_valid_7;
   assign rx_ip_data[((32*8)-1):(32*7)] = rx_phy_data_7;
-  assign rx_ip_disperr[((32*8)-1):(32*7)] = rx_phy_disperr_7;
-  assign rx_ip_deterr[((32*8)-1):(32*7)] = rx_phy_deterr_7;
-  assign rx_ip_kchar[((32*8)-1):(32*7)] = rx_phy_kchar_7;
+  assign rx_ip_disperr[((4*8)-1):(4*7)] = rx_phy_disperr_7;
+  assign rx_ip_deterr[((4*8)-1):(4*7)] = rx_phy_deterr_7;
+  assign rx_ip_kchar[((4*8)-1):(4*7)] = rx_phy_kchar_7;
   assign rx_ip_full[7] = rx_phy_full_7;
   assign rx_ip_empty[7] = rx_phy_empty_7;
   end
@@ -577,10 +641,14 @@ module avl_adxphy (
   assign rx_phy_align_en_7 = rx_ip_align_en[7];
   assign rx_phy_lane_polarity_7 = rx_ip_lane_polarity[7];
   assign rx_phy_lane_powerdown_7 = rx_ip_lane_powerdown[7];
+  assign rx_phy_analogreset_7 = rx_core_analogreset[7];
+  assign rx_phy_digitalreset_7 = rx_core_digitalreset[7];
   end else begin
   assign rx_phy_align_en_7 = 1'd0;
   assign rx_phy_lane_polarity_7 = 1'd0;
   assign rx_phy_lane_powerdown_7 = 1'd0;
+  assign rx_phy_analogreset_7 = 1'd1;
+  assign rx_phy_digitalreset_7 = 1'd1;
   end
   endgenerate
 
@@ -614,6 +682,16 @@ module avl_adxphy (
   end
   endgenerate
 
+  generate
+  if (NUM_OF_LANES > 0) begin
+  assign tx_phy_analogreset_0 = tx_core_analogreset[0];
+  assign tx_phy_digitalreset_0 = tx_core_digitalreset[0];
+  end else begin
+  assign tx_phy_analogreset_0 = 1'd1;
+  assign tx_phy_digitalreset_0 = 1'd1;
+  end
+  endgenerate
+
   assign tx_phy_s_0[0] = tx_phy_cal_busy_0;
   assign tx_phy_s_0[1] = tx_phy_full_0;
   assign tx_phy_s_0[2] = tx_phy_empty_0;
@@ -650,6 +728,16 @@ module avl_adxphy (
   end
   endgenerate
 
+  generate
+  if (NUM_OF_LANES > 1) begin
+  assign tx_phy_analogreset_1 = tx_core_analogreset[1];
+  assign tx_phy_digitalreset_1 = tx_core_digitalreset[1];
+  end else begin
+  assign tx_phy_analogreset_1 = 1'd1;
+  assign tx_phy_digitalreset_1 = 1'd1;
+  end
+  endgenerate
+
   assign tx_phy_s_1[0] = tx_phy_cal_busy_1;
   assign tx_phy_s_1[1] = tx_phy_full_1;
   assign tx_phy_s_1[2] = tx_phy_empty_1;
@@ -686,6 +774,16 @@ module avl_adxphy (
   end
   endgenerate
 
+  generate
+  if (NUM_OF_LANES > 2) begin
+  assign tx_phy_analogreset_2 = tx_core_analogreset[2];
+  assign tx_phy_digitalreset_2 = tx_core_digitalreset[2];
+  end else begin
+  assign tx_phy_analogreset_2 = 1'd1;
+  assign tx_phy_digitalreset_2 = 1'd1;
+  end
+  endgenerate
+
   assign tx_phy_s_2[0] = tx_phy_cal_busy_2;
   assign tx_phy_s_2[1] = tx_phy_full_2;
   assign tx_phy_s_2[2] = tx_phy_empty_2;
@@ -722,6 +820,16 @@ module avl_adxphy (
   end
   endgenerate
 
+  generate
+  if (NUM_OF_LANES > 3) begin
+  assign tx_phy_analogreset_3 = tx_core_analogreset[3];
+  assign tx_phy_digitalreset_3 = tx_core_digitalreset[3];
+  end else begin
+  assign tx_phy_analogreset_3 = 1'd1;
+  assign tx_phy_digitalreset_3 = 1'd1;
+  end
+  endgenerate
+
   assign tx_phy_s_3[0] = tx_phy_cal_busy_3;
   assign tx_phy_s_3[1] = tx_phy_full_3;
   assign tx_phy_s_3[2] = tx_phy_empty_3;
@@ -758,6 +866,16 @@ module avl_adxphy (
   end
   endgenerate
 
+  generate
+  if (NUM_OF_LANES > 4) begin
+  assign tx_phy_analogreset_4 = tx_core_analogreset[4];
+  assign tx_phy_digitalreset_4 = tx_core_digitalreset[4];
+  end else begin
+  assign tx_phy_analogreset_4 = 1'd1;
+  assign tx_phy_digitalreset_4 = 1'd1;
+  end
+  endgenerate
+
   assign tx_phy_s_4[0] = tx_phy_cal_busy_4;
   assign tx_phy_s_4[1] = tx_phy_full_4;
   assign tx_phy_s_4[2] = tx_phy_empty_4;
@@ -794,6 +912,16 @@ module avl_adxphy (
   end
   endgenerate
 
+  generate
+  if (NUM_OF_LANES > 5) begin
+  assign tx_phy_analogreset_5 = tx_core_analogreset[5];
+  assign tx_phy_digitalreset_5 = tx_core_digitalreset[5];
+  end else begin
+  assign tx_phy_analogreset_5 = 1'd1;
+  assign tx_phy_digitalreset_5 = 1'd1;
+  end
+  endgenerate
+
   assign tx_phy_s_5[0] = tx_phy_cal_busy_5;
   assign tx_phy_s_5[1] = tx_phy_full_5;
   assign tx_phy_s_5[2] = tx_phy_empty_5;
@@ -830,6 +958,16 @@ module avl_adxphy (
   end
   endgenerate
 
+  generate
+  if (NUM_OF_LANES > 6) begin
+  assign tx_phy_analogreset_6 = tx_core_analogreset[6];
+  assign tx_phy_digitalreset_6 = tx_core_digitalreset[6];
+  end else begin
+  assign tx_phy_analogreset_6 = 1'd1;
+  assign tx_phy_digitalreset_6 = 1'd1;
+  end
+  endgenerate
+
   assign tx_phy_s_6[0] = tx_phy_cal_busy_6;
   assign tx_phy_s_6[1] = tx_phy_full_6;
   assign tx_phy_s_6[2] = tx_phy_empty_6;
@@ -866,6 +1004,16 @@ module avl_adxphy (
   end
   endgenerate
 
+  generate
+  if (NUM_OF_LANES > 7) begin
+  assign tx_phy_analogreset_7 = tx_core_analogreset[7];
+  assign tx_phy_digitalreset_7 = tx_core_digitalreset[7];
+  end else begin
+  assign tx_phy_analogreset_7 = 1'd1;
+  assign tx_phy_digitalreset_7 = 1'd1;
+  end
+  endgenerate
+
   assign tx_phy_s_7[0] = tx_phy_cal_busy_7;
   assign tx_phy_s_7[1] = tx_phy_full_7;
   assign tx_phy_s_7[2] = tx_phy_empty_7;
diff --git a/library/altera/avl_adxphy/avl_adxphy_hw.tcl b/library/altera/avl_adxphy/avl_adxphy_hw.tcl
index 104b8d526..46fae17d4 100644
--- a/library/altera/avl_adxphy/avl_adxphy_hw.tcl
+++ b/library/altera/avl_adxphy/avl_adxphy_hw.tcl
@@ -38,6 +38,8 @@ proc p_avl_adxphy {} {
 
   if {$m_tx_or_rx_n == 1} {
 
+    ad_conduit tx_core_analogreset tx_analogreset tx_core_analogreset input $m_num_of_lanes
+    ad_conduit tx_core_digitalreset tx_digitalreset tx_core_digitalreset input $m_num_of_lanes
     ad_conduit tx_core_cal_busy tx_cal_busy tx_core_cal_busy output $m_num_of_lanes
 
     ad_conduit tx_ip_cal_busy tx_cal_busy tx_ip_cal_busy output $m_num_of_lanes
@@ -48,8 +50,8 @@ proc p_avl_adxphy {} {
     ad_conduit tx_ip_elecidle export tx_ip_elecidle input $m_num_of_lanes
     ad_conduit tx_ip_csr_lane_polarity export tx_ip_lane_polarity input $m_num_of_lanes
     ad_conduit tx_ip_csr_lane_powerdown export tx_ip_lane_powerdown input $m_num_of_lanes
-    ad_conduit tx_ip_csr_bit_reversal export rx_tp_bit_reversal input 1
-    ad_conduit tx_ip_csr_byte_reversal export rx_tp_byte_reversal input 1
+    ad_conduit tx_ip_csr_bit_reversal export rx_ip_bit_reversal input 1
+    ad_conduit tx_ip_csr_byte_reversal export rx_ip_byte_reversal input 1
 
     for {set n 0} {$n < $m_num_of_lanes} {incr n} {
 
@@ -68,11 +70,15 @@ proc p_avl_adxphy {} {
       ad_conduit tx_phy${n}_csr_lane_powerdown export tx_phy_lane_powerdown_${n} output 1
       ad_conduit tx_phy${n}_csr_bit_reversal export tx_phy_bit_reversal_${n} output 1
       ad_conduit tx_phy${n}_csr_byte_reversal export tx_phy_byte_reversal_${n} output 1
+      ad_conduit tx_phy${n}_analogreset tx_analogreset tx_phy_analogreset_${n} output 1
+      ad_conduit tx_phy${n}_digitalreset tx_digitalreset tx_phy_digitalreset_${n} output 1
     }
   }
 
   if {$m_tx_or_rx_n == 0} {
 
+    ad_conduit rx_core_analogreset rx_analogreset rx_core_analogreset input $m_num_of_lanes
+    ad_conduit rx_core_digitalreset rx_digitalreset rx_core_digitalreset input $m_num_of_lanes
     ad_conduit rx_core_is_lockedtodata rx_is_lockedtodata rx_core_locked output $m_num_of_lanes
     ad_conduit rx_core_cal_busy rx_cal_busy rx_core_cal_busy output $m_num_of_lanes
 
@@ -107,6 +113,8 @@ proc p_avl_adxphy {} {
       ad_conduit rx_phy${n}_csr_lane_powerdown export rx_phy_lane_powerdown_${n} output 1
       ad_conduit rx_phy${n}_csr_bit_reversal export rx_phy_bit_reversal_${n} output 1
       ad_conduit rx_phy${n}_csr_byte_reversal export rx_phy_byte_reversal_${n} output 1
+      ad_conduit rx_phy${n}_analogreset rx_analogreset rx_phy_analogreset_${n} output 1
+      ad_conduit rx_phy${n}_digitalreset rx_digitalreset rx_phy_digitalreset_${n} output 1
     }
   }
 }

From 21545ee83ff0b391637e0e7efd713a983cf74420 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:47:12 -0400
Subject: [PATCH 465/972] avl_adxcvr- ip/phy split

---
 library/altera/avl_adxcvr/avl_adxcvr_hw.tcl | 293 +++++++++++++-------
 1 file changed, 191 insertions(+), 102 deletions(-)

diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
index d72209030..0a480a619 100755
--- a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
@@ -124,27 +124,27 @@ proc p_avl_adxcvr {} {
   add_interface ref_clk clock sink
   set_interface_property ref_clk EXPORT_OF alt_ref_clk.in_clk
 
-  add_instance alt_ref_pll altera_iopll 16.0
-  set_instance_parameter_value alt_ref_pll {gui_en_reconf} {1}
-  set_instance_parameter_value alt_ref_pll {gui_reference_clock_frequency} $m_refclk_frequency
-  set_instance_parameter_value alt_ref_pll {gui_use_locked} {1}
-  set_instance_parameter_value alt_ref_pll {gui_output_clock_frequency0} $m_coreclk_frequency
-  add_connection alt_ref_clk.out_clk alt_ref_pll.refclk
-  add_connection alt_sys_clk.clk_reset alt_ref_pll.reset
-  add_interface ref_pll_locked conduit end
-  set_interface_property ref_pll_locked EXPORT_OF alt_ref_pll.locked
+  add_instance alt_core_pll altera_iopll 16.0
+  set_instance_parameter_value alt_core_pll {gui_en_reconf} {1}
+  set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency
+  set_instance_parameter_value alt_core_pll {gui_use_locked} {1}
+  set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency
+  add_connection alt_ref_clk.out_clk alt_core_pll.refclk
+  add_connection alt_sys_clk.clk_reset alt_core_pll.reset
+  add_interface core_pll_locked conduit end
+  set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked
 
-  add_instance alt_ref_pll_reconfig altera_pll_reconfig 16.0
-  add_connection alt_sys_clk.clk_reset alt_ref_pll_reconfig.mgmt_reset
-  add_connection alt_sys_clk.clk alt_ref_pll_reconfig.mgmt_clk
-  add_connection alt_ref_pll_reconfig.reconfig_to_pll alt_ref_pll.reconfig_to_pll
-  add_connection alt_ref_pll.reconfig_from_pll alt_ref_pll_reconfig.reconfig_from_pll
-  add_interface ref_pll_reconfig avalon slave
-  set_interface_property ref_pll_reconfig EXPORT_OF alt_ref_pll_reconfig.mgmt_avalon_slave
+  add_instance alt_core_pll_reconfig altera_pll_reconfig 16.0
+  add_connection alt_sys_clk.clk_reset alt_core_pll_reconfig.mgmt_reset
+  add_connection alt_sys_clk.clk alt_core_pll_reconfig.mgmt_clk
+  add_connection alt_core_pll_reconfig.reconfig_to_pll alt_core_pll.reconfig_to_pll
+  add_connection alt_core_pll.reconfig_from_pll alt_core_pll_reconfig.reconfig_from_pll
+  add_interface core_pll_reconfig avalon slave
+  set_interface_property core_pll_reconfig EXPORT_OF alt_core_pll_reconfig.mgmt_avalon_slave
 
   add_instance alt_core_clk altera_clock_bridge 16.0
   set_instance_parameter_value alt_core_clk {EXPLICIT_CLOCK_RATE} $m_coreclk_frequency
-  add_connection alt_ref_pll.outclk0 alt_core_clk.in_clk
+  add_connection alt_core_pll.outclk0 alt_core_clk.in_clk
   add_interface core_clk clock source
   set_interface_property core_clk EXPORT_OF alt_core_clk.out_clk
 
@@ -183,50 +183,94 @@ proc p_avl_adxcvr {} {
     add_interface lane_pll_reconfig avalon slave
     set_interface_property lane_pll_reconfig EXPORT_OF alt_lane_pll.reconfig_avmm0
 
-    add_instance alt_xcvr altera_jesd204 16.0
-    set_instance_parameter_value alt_xcvr {wrapper_opt} {base_phy}
-    set_instance_parameter_value alt_xcvr {DATA_PATH} {TX}
-    set_instance_parameter_value alt_xcvr {lane_rate} $m_lane_rate
-    set_instance_parameter_value alt_xcvr {PCS_CONFIG} $m_pcs_config
-    set_instance_parameter_value alt_xcvr {bonded_mode} {non_bonded}
-    set_instance_parameter_value alt_xcvr {pll_reconfig_enable} {1}
-    set_instance_parameter_value alt_xcvr {set_capability_reg_enable} {1}
-    set_instance_parameter_value alt_xcvr {set_user_identifier} $m_id
-    set_instance_parameter_value alt_xcvr {set_csr_soft_logic_enable} {1}
-    set_instance_parameter_value alt_xcvr {L} $m_num_of_lanes
-    set_instance_parameter_value alt_xcvr {M} $m_num_of_convs
-    set_instance_parameter_value alt_xcvr {GUI_EN_CFG_F} {1}
-    set_instance_parameter_value alt_xcvr {GUI_CFG_F} $m_frm_bcnt
-    set_instance_parameter_value alt_xcvr {N} {16}
-    set_instance_parameter_value alt_xcvr {N_PRIME} {16}
-    set_instance_parameter_value alt_xcvr {S} $m_frm_scnt
-    set_instance_parameter_value alt_xcvr {K} $m_mf_fcnt
-    set_instance_parameter_value alt_xcvr {SCR} {1}
-    set_instance_parameter_value alt_xcvr {HD} $m_hd
-    add_connection alt_rst_cntrol.tx_digitalreset alt_xcvr.tx_digitalreset
-    add_connection alt_rst_cntrol.tx_analogreset alt_xcvr.tx_analogreset
-    add_connection alt_xcvr.tx_cal_busy alt_rst_cntrol.tx_cal_busy
-    add_connection alt_xcvr.dev_sync_n alt_xcvr.mdev_sync_n
-    add_connection alt_sys_clk.clk alt_xcvr.reconfig_clk
-    add_connection alt_sys_clk.clk_reset alt_xcvr.reconfig_reset
-    add_interface phy_reconfig avalon slave
-    set_interface_property phy_reconfig EXPORT_OF alt_xcvr.reconfig_avmm
-    add_connection alt_sys_clk.clk alt_xcvr.jesd204_tx_avs_clk
-    add_connection alt_sys_clk.clk_reset alt_xcvr.jesd204_tx_avs_rst_n
-    add_interface ip_reconfig avalon slave
-    set_interface_property ip_reconfig EXPORT_OF alt_xcvr.jesd204_tx_avs
-    add_connection alt_ref_pll.outclk0 alt_xcvr.txlink_clk
-    add_connection alt_sys_clk.clk_reset alt_xcvr.txlink_rst_n
+    add_instance alt_ip altera_jesd204 16.0
+    set_instance_parameter_value alt_ip {wrapper_opt} {base}
+    set_instance_parameter_value alt_ip {DATA_PATH} {TX}
+    set_instance_parameter_value alt_ip {lane_rate} $m_lane_rate
+    set_instance_parameter_value alt_ip {L} $m_num_of_lanes
+    set_instance_parameter_value alt_ip {M} $m_num_of_convs
+    set_instance_parameter_value alt_ip {GUI_EN_CFG_F} {1}
+    set_instance_parameter_value alt_ip {GUI_CFG_F} $m_frm_bcnt
+    set_instance_parameter_value alt_ip {N} {16}
+    set_instance_parameter_value alt_ip {N_PRIME} {16}
+    set_instance_parameter_value alt_ip {S} $m_frm_scnt
+    set_instance_parameter_value alt_ip {K} $m_mf_fcnt
+    set_instance_parameter_value alt_ip {SCR} {1}
+    set_instance_parameter_value alt_ip {HD} $m_hd
+    add_connection alt_core_pll.outclk0 alt_ip.txlink_clk
+    add_connection alt_sys_clk.clk_reset alt_ip.txlink_rst_n
     add_interface ip_data avalon_streaming sink
-    set_interface_property ip_data EXPORT_OF alt_xcvr.jesd204_tx_link
+    set_interface_property ip_data EXPORT_OF alt_ip.jesd204_tx_link
+    add_connection alt_sys_clk.clk alt_ip.jesd204_tx_avs_clk
+    add_connection alt_sys_clk.clk_reset alt_ip.jesd204_tx_avs_rst_n
+    add_interface ip_reconfig avalon slave
+    set_interface_property ip_reconfig EXPORT_OF alt_ip.jesd204_tx_avs
     add_interface sysref conduit end
-    set_interface_property sysref EXPORT_OF alt_xcvr.sysref
+    set_interface_property sysref EXPORT_OF alt_ip.sysref
     add_interface sync conduit end
-    set_interface_property sync EXPORT_OF alt_xcvr.sync_n
-    add_interface tx_data conduit end
-    set_interface_property tx_data EXPORT_OF alt_xcvr.tx_serial_data
+    set_interface_property sync EXPORT_OF alt_ip.sync_n
+    add_connection alt_ip.dev_sync_n alt_ip.mdev_sync_n
+
+    add_instance alt_xphy avl_adxphy 1.0
+    set_instance_parameter_value alt_xphy {TX_OR_RX_N} {1}
+    set_instance_parameter_value alt_xphy {NUM_OF_LANES} $m_num_of_lanes
+    add_connection alt_rst_cntrol.tx_analogreset alt_xphy.tx_core_analogreset
+    add_connection alt_rst_cntrol.tx_digitalreset alt_xphy.tx_core_digitalreset
+    add_connection alt_xphy.tx_core_cal_busy alt_rst_cntrol.tx_cal_busy
+    add_connection alt_xphy.tx_ip_cal_busy alt_ip.tx_cal_busy
+    add_connection alt_xphy.tx_ip_pcfifo_full alt_ip.phy_csr_tx_pcfifo_full
+    add_connection alt_xphy.tx_ip_pcfifo_empty alt_ip.phy_csr_tx_pcfifo_empty
+    add_connection alt_ip.jesd204_tx_pcs_data alt_xphy.tx_ip_pcs_data
+    add_connection alt_ip.jesd204_tx_pcs_kchar_data alt_xphy.tx_ip_pcs_kchar_data
+    add_connection alt_ip.phy_tx_elecidle alt_xphy.tx_ip_elecidle
+    add_connection alt_ip.csr_lane_polarity alt_xphy.tx_ip_csr_lane_polarity
+    add_connection alt_ip.csr_lane_powerdown alt_xphy.tx_ip_csr_lane_powerdown
+    add_connection alt_ip.csr_bit_reversal alt_xphy.tx_ip_csr_bit_reversal
+    add_connection alt_ip.csr_byte_reversal alt_xphy.tx_ip_csr_byte_reversal
+
     for {set n 0} {$n < $m_num_of_lanes} {incr n} {
-      add_connection alt_lane_pll.tx_serial_clk alt_xcvr.tx_serial_clk0_ch${n}
+
+      add_interface tx_ip_s_${n} conduit end
+      set_interface_property tx_ip_s_${n} EXPORT_OF alt_xphy.tx_ip_s_${n}
+      add_interface tx_ip_d_${n} conduit end
+      set_interface_property tx_ip_d_${n} EXPORT_OF alt_xphy.tx_ip_d_${n}
+      add_interface tx_phy_s_${n} conduit end
+      set_interface_property tx_phy_s_${n} EXPORT_OF alt_xphy.tx_phy_s_${n}
+      add_interface tx_phy_d_${n} conduit end
+      set_interface_property tx_phy_d_${n} EXPORT_OF alt_xphy.tx_phy_d_${n}
+
+      add_instance alt_phy_${n} altera_jesd204 16.0
+      set_instance_parameter_value alt_phy_${n} {wrapper_opt} {phy}
+      set_instance_parameter_value alt_phy_${n} {DATA_PATH} {TX}
+      set_instance_parameter_value alt_phy_${n} {lane_rate} $m_lane_rate
+      set_instance_parameter_value alt_phy_${n} {PCS_CONFIG} $m_pcs_config
+      set_instance_parameter_value alt_phy_${n} {bonded_mode} {non_bonded}
+      set_instance_parameter_value alt_phy_${n} {pll_reconfig_enable} {1}
+      set_instance_parameter_value alt_phy_${n} {set_capability_reg_enable} {1}
+      set_instance_parameter_value alt_phy_${n} {set_user_identifier} $m_id
+      set_instance_parameter_value alt_phy_${n} {set_csr_soft_logic_enable} {1}
+      set_instance_parameter_value alt_phy_${n} {L} 1
+      add_connection alt_core_pll.outclk0 alt_phy_${n}.txlink_clk
+      add_connection alt_sys_clk.clk_reset alt_phy_${n}.txlink_rst_n
+      add_interface tx_data_${n} conduit end
+      set_interface_property tx_data_${n} EXPORT_OF alt_phy_${n}.tx_serial_data
+      add_connection alt_xphy.tx_phy${n}_analogreset alt_phy_${n}.tx_analogreset
+      add_connection alt_xphy.tx_phy${n}_digitalreset alt_phy_${n}.tx_digitalreset
+      add_connection alt_lane_pll.tx_serial_clk alt_phy_${n}.tx_serial_clk0
+      add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk
+      add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset
+      add_interface phy_reconfig_${n} avalon slave
+      set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm
+      add_connection alt_phy_${n}.tx_cal_busy alt_xphy.tx_phy${n}_cal_busy
+      add_connection alt_phy_${n}.phy_csr_tx_pcfifo_full alt_xphy.tx_phy${n}_pcfifo_full
+      add_connection alt_phy_${n}.phy_csr_tx_pcfifo_empty alt_xphy.tx_phy${n}_pcfifo_empty
+      add_connection alt_xphy.tx_phy${n}_pcs_data alt_phy_${n}.jesd204_tx_pcs_data
+      add_connection alt_xphy.tx_phy${n}_pcs_kchar_data alt_phy_${n}.jesd204_tx_pcs_kchar_data
+      add_connection alt_xphy.tx_phy${n}_elecidle alt_phy_${n}.phy_tx_elecidle
+      add_connection alt_xphy.tx_phy${n}_csr_lane_polarity alt_phy_${n}.csr_lane_polarity
+      add_connection alt_xphy.tx_phy${n}_csr_lane_powerdown alt_phy_${n}.csr_lane_powerdown
+      add_connection alt_xphy.tx_phy${n}_csr_bit_reversal alt_phy_${n}.csr_bit_reversal
+      add_connection alt_xphy.tx_phy${n}_csr_byte_reversal alt_phy_${n}.csr_byte_reversal
     }
   }
 
@@ -246,52 +290,97 @@ proc p_avl_adxcvr {} {
     add_interface ready conduit end
     set_interface_property ready EXPORT_OF alt_rst_cntrol.rx_ready
 
-    add_instance alt_xcvr altera_jesd204 16.0
-    set_instance_parameter_value alt_xcvr {wrapper_opt} {base_phy}
-    set_instance_parameter_value alt_xcvr {DATA_PATH} {RX}
-    set_instance_parameter_value alt_xcvr {lane_rate} $m_lane_rate
-    set_instance_parameter_value alt_xcvr {PCS_CONFIG} $m_pcs_config
-    set_instance_parameter_value alt_xcvr {REFCLK_FREQ} $m_refclk_frequency
-    set_instance_parameter_value alt_xcvr {pll_reconfig_enable} {1}
-    set_instance_parameter_value alt_xcvr {set_capability_reg_enable} {1}
-    set_instance_parameter_value alt_xcvr {set_user_identifier} $m_id
-    set_instance_parameter_value alt_xcvr {set_csr_soft_logic_enable} {1}
-    set_instance_parameter_value alt_xcvr {L} $m_num_of_lanes
-    set_instance_parameter_value alt_xcvr {M} $m_num_of_convs
-    set_instance_parameter_value alt_xcvr {GUI_EN_CFG_F} {1}
-    set_instance_parameter_value alt_xcvr {GUI_CFG_F} $m_frm_bcnt
-    set_instance_parameter_value alt_xcvr {N} {16}
-    set_instance_parameter_value alt_xcvr {N_PRIME} {16}
-    set_instance_parameter_value alt_xcvr {S} $m_frm_scnt
-    set_instance_parameter_value alt_xcvr {K} $m_mf_fcnt
-    set_instance_parameter_value alt_xcvr {SCR} {1}
-    set_instance_parameter_value alt_xcvr {HD} $m_hd
-    add_connection alt_rst_cntrol.rx_digitalreset alt_xcvr.rx_digitalreset
-    add_connection alt_rst_cntrol.rx_analogreset alt_xcvr.rx_analogreset
-    add_connection alt_xcvr.rx_cal_busy alt_rst_cntrol.rx_cal_busy
-    add_connection alt_xcvr.rx_islockedtodata alt_rst_cntrol.rx_is_lockedtodata
-    add_connection alt_xcvr.dev_lane_aligned alt_xcvr.alldev_lane_aligned
-    add_connection alt_sys_clk.clk alt_xcvr.reconfig_clk
-    add_connection alt_sys_clk.clk_reset alt_xcvr.reconfig_reset
-    add_interface phy_reconfig avalon slave
-    set_interface_property phy_reconfig EXPORT_OF alt_xcvr.reconfig_avmm
-    add_connection alt_sys_clk.clk alt_xcvr.jesd204_rx_avs_clk
-    add_connection alt_sys_clk.clk_reset alt_xcvr.jesd204_rx_avs_rst_n
-    add_interface ip_reconfig avalon slave
-    set_interface_property ip_reconfig EXPORT_OF alt_xcvr.jesd204_rx_avs
-    add_connection alt_ref_clk.out_clk alt_xcvr.pll_ref_clk
-    add_connection alt_ref_pll.outclk0 alt_xcvr.rxlink_clk
-    add_connection alt_sys_clk.clk_reset alt_xcvr.rxlink_rst_n
-    add_interface ip_data avalon_streaming source
-    set_interface_property ip_data EXPORT_OF alt_xcvr.jesd204_rx_link
-    add_interface sysref conduit end
-    set_interface_property sysref EXPORT_OF alt_xcvr.sysref
-    add_interface sync conduit end
-    set_interface_property sync EXPORT_OF alt_xcvr.dev_sync_n
+    add_instance alt_ip altera_jesd204 16.0
+    set_instance_parameter_value alt_ip {wrapper_opt} {base}
+    set_instance_parameter_value alt_ip {DATA_PATH} {RX}
+    set_instance_parameter_value alt_ip {lane_rate} $m_lane_rate
+    set_instance_parameter_value alt_ip {L} $m_num_of_lanes
+    set_instance_parameter_value alt_ip {M} $m_num_of_convs
+    set_instance_parameter_value alt_ip {GUI_EN_CFG_F} {1}
+    set_instance_parameter_value alt_ip {GUI_CFG_F} $m_frm_bcnt
+    set_instance_parameter_value alt_ip {N} {16}
+    set_instance_parameter_value alt_ip {N_PRIME} {16}
+    set_instance_parameter_value alt_ip {S} $m_frm_scnt
+    set_instance_parameter_value alt_ip {K} $m_mf_fcnt
+    set_instance_parameter_value alt_ip {SCR} {1}
+    set_instance_parameter_value alt_ip {HD} $m_hd
+    add_connection alt_core_pll.outclk0 alt_ip.rxlink_clk
+    add_connection alt_sys_clk.clk_reset alt_ip.rxlink_rst_n
     add_interface ip_sof conduit end
-    set_interface_property ip_sof EXPORT_OF alt_xcvr.sof
-    add_interface rx_data conduit end
-    set_interface_property rx_data EXPORT_OF alt_xcvr.rx_serial_data
+    set_interface_property ip_sof EXPORT_OF alt_ip.sof
+    add_interface ip_data avalon_streaming source
+    set_interface_property ip_data EXPORT_OF alt_ip.jesd204_rx_link
+    add_connection alt_sys_clk.clk alt_ip.jesd204_rx_avs_clk
+    add_connection alt_sys_clk.clk_reset alt_ip.jesd204_rx_avs_rst_n
+    add_interface ip_reconfig avalon slave
+    set_interface_property ip_reconfig EXPORT_OF alt_ip.jesd204_rx_avs
+    add_interface sysref conduit end
+    set_interface_property sysref EXPORT_OF alt_ip.sysref
+    add_interface sync conduit end
+    set_interface_property sync EXPORT_OF alt_ip.dev_sync_n
+    add_connection alt_ip.dev_lane_aligned alt_ip.alldev_lane_aligned
+
+    add_instance alt_xphy avl_adxphy 1.0
+    set_instance_parameter_value alt_xphy {TX_OR_RX_N} {0}
+    set_instance_parameter_value alt_xphy {NUM_OF_LANES} $m_num_of_lanes
+    add_connection alt_rst_cntrol.rx_analogreset alt_xphy.rx_core_analogreset
+    add_connection alt_rst_cntrol.rx_digitalreset alt_xphy.rx_core_digitalreset
+    add_connection alt_xphy.rx_core_is_lockedtodata alt_rst_cntrol.rx_is_lockedtodata
+    add_connection alt_xphy.rx_core_cal_busy alt_rst_cntrol.rx_cal_busy
+    add_connection alt_xphy.rx_ip_is_lockedtodata alt_ip.rx_islockedtodata
+    add_connection alt_xphy.rx_ip_cal_busy alt_ip.rx_cal_busy
+    add_connection alt_xphy.rx_ip_pcs_data_valid alt_ip.jesd204_rx_pcs_data_valid
+    add_connection alt_xphy.rx_ip_pcs_data alt_ip.jesd204_rx_pcs_data
+    add_connection alt_xphy.rx_ip_pcs_disperr alt_ip.jesd204_rx_pcs_disperr
+    add_connection alt_xphy.rx_ip_pcs_errdetect alt_ip.jesd204_rx_pcs_errdetect
+    add_connection alt_xphy.rx_ip_pcs_kchar_data alt_ip.jesd204_rx_pcs_kchar_data
+    add_connection alt_xphy.rx_ip_pcfifo_full alt_ip.phy_csr_rx_pcfifo_full
+    add_connection alt_xphy.rx_ip_pcfifo_empty alt_ip.phy_csr_rx_pcfifo_empty
+    add_connection alt_xphy.rx_ip_patternalign_en alt_ip.patternalign_en
+    add_connection alt_xphy.rx_ip_csr_lane_polarity alt_ip.csr_lane_polarity
+    add_connection alt_xphy.rx_ip_csr_lane_powerdown alt_ip.csr_lane_powerdown
+    add_connection alt_xphy.rx_ip_csr_bit_reversal alt_ip.csr_bit_reversal
+    add_connection alt_xphy.rx_ip_csr_byte_reversal alt_ip.csr_byte_reversal
+
+    for {set n 0} {$n < $m_num_of_lanes} {incr n} {
+
+      add_instance alt_phy_${n} altera_jesd204 16.0
+      set_instance_parameter_value alt_phy_${n} {wrapper_opt} {phy}
+      set_instance_parameter_value alt_phy_${n} {DATA_PATH} {RX}
+      set_instance_parameter_value alt_phy_${n} {lane_rate} $m_lane_rate
+      set_instance_parameter_value alt_phy_${n} {PCS_CONFIG} $m_pcs_config
+      set_instance_parameter_value alt_phy_${n} {REFCLK_FREQ} $m_refclk_frequency
+      set_instance_parameter_value alt_phy_${n} {pll_reconfig_enable} {1}
+      set_instance_parameter_value alt_phy_${n} {set_capability_reg_enable} {1}
+      set_instance_parameter_value alt_phy_${n} {set_user_identifier} $m_id
+      set_instance_parameter_value alt_phy_${n} {set_csr_soft_logic_enable} {1}
+      set_instance_parameter_value alt_phy_${n} {L} 1
+      add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk
+      add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset
+      add_interface phy_reconfig_${n} avalon slave
+      set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm
+      add_connection alt_ref_clk.out_clk alt_phy_${n}.pll_ref_clk
+      add_connection alt_core_pll.outclk0 alt_phy_${n}.rxlink_clk
+      add_connection alt_sys_clk.clk_reset alt_phy_${n}.rxlink_rst_n
+      add_interface rx_data_${n} conduit end
+      set_interface_property rx_data_${n} EXPORT_OF alt_phy_${n}.rx_serial_data
+      add_connection alt_xphy.rx_phy${n}_analogreset alt_phy_${n}.rx_analogreset
+      add_connection alt_xphy.rx_phy${n}_digitalreset alt_phy_${n}.rx_digitalreset
+      add_connection alt_phy_${n}.rx_islockedtodata alt_xphy.rx_phy${n}_is_lockedtodata
+      add_connection alt_phy_${n}.rx_cal_busy alt_xphy.rx_phy${n}_cal_busy
+      add_connection alt_phy_${n}.jesd204_rx_pcs_data_valid alt_xphy.rx_phy${n}_pcs_data_valid
+      add_connection alt_phy_${n}.jesd204_rx_pcs_data alt_xphy.rx_phy${n}_pcs_data
+      add_connection alt_phy_${n}.jesd204_rx_pcs_disperr alt_xphy.rx_phy${n}_pcs_disperr
+      add_connection alt_phy_${n}.jesd204_rx_pcs_errdetect alt_xphy.rx_phy${n}_pcs_errdetect
+      add_connection alt_phy_${n}.jesd204_rx_pcs_kchar_data alt_xphy.rx_phy${n}_pcs_kchar_data
+      add_connection alt_phy_${n}.phy_csr_rx_pcfifo_full alt_xphy.rx_phy${n}_pcfifo_full
+      add_connection alt_phy_${n}.phy_csr_rx_pcfifo_empty alt_xphy.rx_phy${n}_pcfifo_empty
+      add_connection alt_xphy.rx_phy${n}_patternalign_en alt_phy_${n}.patternalign_en
+      add_connection alt_xphy.rx_phy${n}_csr_lane_polarity alt_phy_${n}.csr_lane_polarity
+      add_connection alt_xphy.rx_phy${n}_csr_lane_powerdown alt_phy_${n}.csr_lane_powerdown
+      add_connection alt_xphy.rx_phy${n}_csr_bit_reversal alt_phy_${n}.csr_bit_reversal
+      add_connection alt_xphy.rx_phy${n}_csr_byte_reversal alt_phy_${n}.csr_byte_reversal
+    }
   }
 }
 

From 73ebf1225c7cede685ec0b29b118663cb504f455 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:48:11 -0400
Subject: [PATCH 466/972] axi_adxcvr- ip/phy split

---
 library/altera/axi_adxcvr/axi_adxcvr.v      | 4 ++--
 library/altera/axi_adxcvr/axi_adxcvr_hw.tcl | 4 ++--
 library/altera/axi_adxcvr/axi_adxcvr_up.v   | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/library/altera/axi_adxcvr/axi_adxcvr.v b/library/altera/axi_adxcvr/axi_adxcvr.v
index d5f38db9b..ff28d082b 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr.v
@@ -42,7 +42,7 @@ module axi_adxcvr (
   // xcvr, lane-pll and ref-pll are shared
 
   output                        up_rst,
-  input                         up_ref_pll_locked,
+  input                         up_pll_locked,
   input   [(NUM_OF_LANES-1):0]  up_ready,
 
   input                         s_axi_aclk,
@@ -99,7 +99,7 @@ module axi_adxcvr (
     .NUM_OF_LANES (NUM_OF_LANES))
   i_up (
     .up_rst (up_rst),
-    .up_ref_pll_locked (up_ref_pll_locked),
+    .up_pll_locked (up_pll_locked),
     .up_ready (up_ready),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
index d59eb48b8..cdb1834a1 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+++ b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
@@ -76,8 +76,8 @@ add_interface_port s_axi s_axi_rready rready Input 1
 ad_alt_intf reset up_rst output 1 s_axi_clock
 set_interface_property if_up_rst associatedResetSinks s_axi_reset
 
-add_interface ref_pll_locked conduit end
-add_interface_port ref_pll_locked up_ref_pll_locked export Input 1
+add_interface core_pll_locked conduit end
+add_interface_port core_pll_locked up_pll_locked export Input 1
 
 # name changes
 
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v
index e9f9dbe9c..88418242f 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v
@@ -42,7 +42,7 @@ module axi_adxcvr_up (
   // xcvr, lane-pll and ref-pll are shared
 
   output                        up_rst,
-  input                         up_ref_pll_locked,
+  input                         up_pll_locked,
   input   [(NUM_OF_LANES-1):0]  up_ready,
 
   // bus interface
@@ -111,7 +111,7 @@ module axi_adxcvr_up (
   assign up_rst = up_rst_cnt[3];
   assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
   assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
-  assign up_status_32_s[NUM_OF_LANES] = up_ref_pll_locked;
+  assign up_status_32_s[NUM_OF_LANES] = up_pll_locked;
   assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready;
 
   always @(negedge up_rstn or posedge up_clk) begin

From c6998dd396b136b775d63ccd68a0318dc42cbd16 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:49:11 -0400
Subject: [PATCH 467/972] scripts- altera conduit

---
 library/scripts/adi_ip_alt.tcl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl
index 3967f0a08..664b1d5d1 100644
--- a/library/scripts/adi_ip_alt.tcl
+++ b/library/scripts/adi_ip_alt.tcl
@@ -64,3 +64,9 @@ proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
   }
 }
 
+proc ad_conduit {if_name if_port port dir width} {
+
+  add_interface $if_name conduit end
+  add_interface_port $if_name $port $if_port $dir $width
+}
+

From 5df30ac6b0f0e0f270163e5014a7af5a3de00638 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:50:54 -0400
Subject: [PATCH 468/972] daq2/a10gx- xcvr sharing

---
 projects/daq2/a10gx/system_constr.sdc  | 12 ++++++------
 projects/daq2/a10gx/system_project.tcl | 10 ++++++++++
 projects/daq2/a10gx/system_top.v       | 18 ++++++++++++------
 3 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc
index a1450327d..dbb02427a 100644
--- a/projects/daq2/a10gx/system_constr.sdc
+++ b/projects/daq2/a10gx/system_constr.sdc
@@ -19,25 +19,25 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
diff --git a/projects/daq2/a10gx/system_project.tcl b/projects/daq2/a10gx/system_project.tcl
index 55dcff77f..824055fdd 100644
--- a/projects/daq2/a10gx/system_project.tcl
+++ b/projects/daq2/a10gx/system_project.tcl
@@ -60,6 +60,16 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
 set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
 
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3]
+
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
+
 # gpio
 
 set_location_assignment PIN_AT17  -to trig                  ; ## H13  FMCA_LA07_P
diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v
index ccfaa6820..5b8b15688 100644
--- a/projects/daq2/a10gx/system_top.v
+++ b/projects/daq2/a10gx/system_top.v
@@ -238,10 +238,13 @@ module system_top (
   assign gpio_bd_o = gpio_o[15:0];
 
   system_bd i_system_bd (
-    .rx_data_rx_serial_data (rx_data),
+    .rx_data_0_rx_serial_data (rx_data[0]),
+    .rx_data_1_rx_serial_data (rx_data[1]),
+    .rx_data_2_rx_serial_data (rx_data[2]),
+    .rx_data_3_rx_serial_data (rx_data[3]),
     .rx_ref_clk_clk (rx_ref_clk),
-    .rx_sync_rx_sync (rx_sync),
-    .rx_sysref_rx_ext_sysref_in (rx_sysref),
+    .rx_sync_export (rx_sync),
+    .rx_sysref_export (rx_sysref),
     .sys_clk_clk (sys_clk),
     .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
     .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
@@ -277,10 +280,13 @@ module system_top (
     .sys_spi_MOSI (spi_mosi_s),
     .sys_spi_SCLK (spi_clk),
     .sys_spi_SS_n (spi_csn_s),
-    .tx_data_tx_serial_data (tx_data),
+    .tx_data_0_tx_serial_data (tx_data[0]),
+    .tx_data_1_tx_serial_data (tx_data[1]),
+    .tx_data_2_tx_serial_data (tx_data[2]),
+    .tx_data_3_tx_serial_data (tx_data[3]),
     .tx_ref_clk_clk (tx_ref_clk),
-    .tx_sync_tx_sync (tx_sync),
-    .tx_sysref_tx_ext_sysref_in (tx_sysref));
+    .tx_sync_export (tx_sync),
+    .tx_sysref_export (tx_sysref));
 
 endmodule
 

From 236a938425461a5a5051d94f32a57702ce822aa6 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:51:37 -0400
Subject: [PATCH 469/972] daq2/a10gx- qsys updates

---
 projects/daq2/common/daq2_qsys.tcl | 355 ++++++++++++++---------------
 1 file changed, 166 insertions(+), 189 deletions(-)

diff --git a/projects/daq2/common/daq2_qsys.tcl b/projects/daq2/common/daq2_qsys.tcl
index 0244be256..d831ead53 100644
--- a/projects/daq2/common/daq2_qsys.tcl
+++ b/projects/daq2/common/daq2_qsys.tcl
@@ -1,183 +1,70 @@
 
-# transmit-path (refclk)
+# ad9144-xcvr
 
-add_instance xcvr_tx_ref_clk altera_clock_bridge 16.0
-set_instance_parameter_value xcvr_tx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
+add_instance avl_ad9144_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_ad9144_xcvr {ID} {0}
+set_instance_parameter_value avl_ad9144_xcvr {TX_OR_RX_N} {1}
+set_instance_parameter_value avl_ad9144_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value avl_ad9144_xcvr {LANE_RATE} {10000.0}
+set_instance_parameter_value avl_ad9144_xcvr {PLLCLK_FREQUENCY} {5000.0}
+set_instance_parameter_value avl_ad9144_xcvr {REFCLK_FREQUENCY} {500.0}
+set_instance_parameter_value avl_ad9144_xcvr {CORECLK_FREQUENCY} {250.0}
+set_instance_parameter_value avl_ad9144_xcvr {NUM_OF_LANES} {4}
+set_instance_parameter_value avl_ad9144_xcvr {NUM_OF_CONVS} {2}
+set_instance_parameter_value avl_ad9144_xcvr {FRM_BCNT} {1}
+set_instance_parameter_value avl_ad9144_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_ad9144_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_ad9144_xcvr {HD} {1}
 
-# transmit-path (pll-core)
-
-add_instance xcvr_tx_pll altera_iopll 16.0
-add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 16.0
-set_instance_parameter_value xcvr_tx_pll {gui_en_reconf} {1}
-set_instance_parameter_value xcvr_tx_pll {gui_reference_clock_frequency} {500.0}
-set_instance_parameter_value xcvr_tx_pll {gui_use_locked} {0}
-set_instance_parameter_value xcvr_tx_pll {gui_output_clock_frequency0} {250.0}
-
-# transmit-path (pll-atx)
-
-add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 16.0
-set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_csr_soft_logic_enable} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {5000.0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {500.0}
-
-# receive-path (refclk)
-
-add_instance xcvr_rx_ref_clk altera_clock_bridge 16.0
-set_instance_parameter_value xcvr_rx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
-
-# receive-path (pll-core)
-
-add_instance xcvr_rx_pll altera_iopll 16.0
-add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 16.0
-set_instance_parameter_value xcvr_rx_pll {gui_en_reconf} {1}
-set_instance_parameter_value xcvr_rx_pll {gui_reference_clock_frequency} {500.0}
-set_instance_parameter_value xcvr_rx_pll {gui_use_locked} {0}
-set_instance_parameter_value xcvr_rx_pll {gui_output_clock_frequency0} {250.0}
-
-# transceiver-control
-
-add_instance axi_jesd_xcvr axi_jesd_xcvr 1.0
-set_instance_parameter_value axi_jesd_xcvr {DEVICE_TYPE} {0}
-set_instance_parameter_value axi_jesd_xcvr {TX_NUM_OF_LANES} {4}
-set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {4}
-
-# transceiver-reset
-
-add_instance xcvr_rst_cntrl altera_xcvr_reset_control 16.0
-set_instance_parameter_value xcvr_rst_cntrl {CHANNELS} {4}
-set_instance_parameter_value xcvr_rst_cntrl {SYS_CLK_IN_MHZ} {100}
-set_instance_parameter_value xcvr_rst_cntrl {TX_PLL_ENABLE} {1}
-set_instance_parameter_value xcvr_rst_cntrl {T_PLL_POWERDOWN} {1000}
-set_instance_parameter_value xcvr_rst_cntrl {TX_ENABLE} {1}
-set_instance_parameter_value xcvr_rst_cntrl {T_TX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_rst_cntrl {T_TX_DIGITALRESET} {70000}
-set_instance_parameter_value xcvr_rst_cntrl {gui_pll_cal_busy} {1}
-set_instance_parameter_value xcvr_rst_cntrl {RX_ENABLE} {1}
-set_instance_parameter_value xcvr_rst_cntrl {T_RX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_rst_cntrl {T_RX_DIGITALRESET} {4000}
-
-# transceiver-core (+ jesd)
-
-add_instance xcvr_core altera_jesd204 16.0
-set_instance_parameter_value xcvr_core {wrapper_opt} {base_phy}
-set_instance_parameter_value xcvr_core {DATA_PATH} {RX_TX}
-set_instance_parameter_value xcvr_core {lane_rate} {10000.0}
-set_instance_parameter_value xcvr_core {PCS_CONFIG} {JESD_PCS_CFG2}
-set_instance_parameter_value xcvr_core {bonded_mode} {non_bonded}
-set_instance_parameter_value xcvr_core {REFCLK_FREQ} {500.0}
-set_instance_parameter_value xcvr_core {pll_reconfig_enable} {1}
-set_instance_parameter_value xcvr_core {set_capability_reg_enable} {1}
-set_instance_parameter_value xcvr_core {set_csr_soft_logic_enable} {1}
-set_instance_parameter_value xcvr_core {L} {4}
-set_instance_parameter_value xcvr_core {M} {2}
-set_instance_parameter_value xcvr_core {GUI_EN_CFG_F} {1}
-set_instance_parameter_value xcvr_core {GUI_CFG_F} {1}
-set_instance_parameter_value xcvr_core {N} {16}
-set_instance_parameter_value xcvr_core {S} {1}
-set_instance_parameter_value xcvr_core {K} {32}
-set_instance_parameter_value xcvr_core {SCR} {1}
-set_instance_parameter_value xcvr_core {HD} {1}
-
-# transceiver + jesd interfaces
-
-add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_pll.refclk
-add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_lane_pll.pll_refclk0
+add_connection sys_clk.clk avl_ad9144_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_ad9144_xcvr.sys_resetn
 add_interface tx_ref_clk clock sink
-set_interface_property tx_ref_clk EXPORT_OF xcvr_tx_ref_clk.in_clk
-
-add_connection xcvr_rx_ref_clk.out_clk xcvr_rx_pll.refclk
-add_connection xcvr_rx_ref_clk.out_clk xcvr_core.rx_pll_ref_clk
-add_interface rx_ref_clk clock sink
-set_interface_property rx_ref_clk EXPORT_OF xcvr_rx_ref_clk.in_clk
-
-add_connection sys_clk.clk_reset xcvr_tx_pll.reset
-add_connection axi_jesd_xcvr.if_rst xcvr_tx_pll.reset
-add_connection xcvr_tx_pll.outclk0 xcvr_core.txlink_clk
-add_connection sys_clk.clk_reset xcvr_tx_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk xcvr_tx_pll_reconfig.mgmt_clk
-add_connection sys_cpu.data_master xcvr_tx_pll_reconfig.mgmt_avalon_slave
-add_connection xcvr_tx_pll_reconfig.reconfig_from_pll xcvr_tx_pll.reconfig_from_pll
-add_connection xcvr_tx_pll.reconfig_to_pll xcvr_tx_pll_reconfig.reconfig_to_pll
-
-add_connection sys_clk.clk_reset xcvr_rx_pll.reset
-add_connection axi_jesd_xcvr.if_rst xcvr_rx_pll.reset
-add_connection xcvr_rx_pll.outclk0 xcvr_core.rxlink_clk
-add_connection sys_clk.clk_reset xcvr_rx_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk xcvr_rx_pll_reconfig.mgmt_clk
-add_connection sys_cpu.data_master xcvr_rx_pll_reconfig.mgmt_avalon_slave
-add_connection xcvr_rx_pll.reconfig_from_pll xcvr_rx_pll_reconfig.reconfig_from_pll
-add_connection xcvr_rx_pll_reconfig.reconfig_to_pll xcvr_rx_pll.reconfig_to_pll
-
-add_connection xcvr_rst_cntrl.pll_powerdown xcvr_tx_lane_pll.pll_powerdown
-add_connection xcvr_tx_lane_pll.pll_cal_busy xcvr_rst_cntrl.pll_cal_busy
-add_connection xcvr_tx_lane_pll.pll_locked xcvr_rst_cntrl.pll_locked
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch0
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch1
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch2
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch3
-add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
-add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0
-add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
-
-add_connection sys_clk.clk_reset xcvr_rst_cntrl.reset
-add_connection sys_clk.clk xcvr_rst_cntrl.clock
-add_connection xcvr_rst_cntrl.tx_analogreset xcvr_core.tx_analogreset
-add_connection xcvr_rst_cntrl.tx_digitalreset xcvr_core.tx_digitalreset
-add_connection xcvr_rst_cntrl.tx_cal_busy xcvr_core.tx_cal_busy
-add_connection xcvr_rst_cntrl.rx_analogreset xcvr_core.rx_analogreset
-add_connection xcvr_rst_cntrl.rx_digitalreset xcvr_core.rx_digitalreset
-add_connection xcvr_rst_cntrl.rx_cal_busy xcvr_core.rx_cal_busy
-add_connection xcvr_rst_cntrl.rx_is_lockedtodata xcvr_core.rx_islockedtodata
-add_connection axi_jesd_xcvr.if_rst xcvr_rst_cntrl.reset
-add_connection xcvr_tx_pll.outclk0 axi_jesd_xcvr.if_tx_clk
-add_connection axi_jesd_xcvr.if_tx_rstn xcvr_core.txlink_rst_n
-add_connection axi_jesd_xcvr.if_tx_ready xcvr_rst_cntrl.tx_ready
-add_connection axi_jesd_xcvr.if_tx_ip_sysref xcvr_core.tx_sysref
-add_connection axi_jesd_xcvr.if_tx_ip_sync xcvr_core.sync_n
-add_connection axi_jesd_xcvr.if_tx_ip_avl xcvr_core.jesd204_tx_link
-add_connection xcvr_rx_pll.outclk0 axi_jesd_xcvr.if_rx_clk
-add_connection axi_jesd_xcvr.if_rx_rstn xcvr_core.rxlink_rst_n
-add_connection axi_jesd_xcvr.if_rx_ready xcvr_rst_cntrl.rx_ready
-add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_core.rx_sysref
-add_connection axi_jesd_xcvr.if_rx_ip_sync xcvr_core.rx_dev_sync_n
-add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
-add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
-add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
+set_interface_property tx_ref_clk EXPORT_OF avl_ad9144_xcvr.ref_clk
+add_interface tx_data_0 conduit end
+set_interface_property tx_data_0 EXPORT_OF avl_ad9144_xcvr.tx_data_0
+add_interface tx_data_1 conduit end
+set_interface_property tx_data_1 EXPORT_OF avl_ad9144_xcvr.tx_data_1
+add_interface tx_data_2 conduit end
+set_interface_property tx_data_2 EXPORT_OF avl_ad9144_xcvr.tx_data_2
+add_interface tx_data_3 conduit end
+set_interface_property tx_data_3 EXPORT_OF avl_ad9144_xcvr.tx_data_3
 add_interface tx_sysref conduit end
+set_interface_property tx_sysref EXPORT_OF avl_ad9144_xcvr.sysref
 add_interface tx_sync conduit end
-add_interface rx_sysref conduit end
-add_interface rx_sync conduit end
-set_interface_property tx_sysref EXPORT_OF axi_jesd_xcvr.if_tx_ext_sysref_in
-set_interface_property tx_sync EXPORT_OF axi_jesd_xcvr.if_tx_sync
-set_interface_property rx_sysref EXPORT_OF axi_jesd_xcvr.if_rx_ext_sysref_in
-set_interface_property rx_sync EXPORT_OF axi_jesd_xcvr.if_rx_sync
+set_interface_property tx_sync EXPORT_OF avl_ad9144_xcvr.sync
+add_connection avl_ad9144_xcvr.tx_phy_s_0 avl_ad9144_xcvr.tx_ip_s_0
+add_connection avl_ad9144_xcvr.tx_phy_s_1 avl_ad9144_xcvr.tx_ip_s_3
+add_connection avl_ad9144_xcvr.tx_phy_s_2 avl_ad9144_xcvr.tx_ip_s_1
+add_connection avl_ad9144_xcvr.tx_phy_s_3 avl_ad9144_xcvr.tx_ip_s_2
+add_connection avl_ad9144_xcvr.tx_ip_d_0 avl_ad9144_xcvr.tx_phy_d_0
+add_connection avl_ad9144_xcvr.tx_ip_d_3 avl_ad9144_xcvr.tx_phy_d_1
+add_connection avl_ad9144_xcvr.tx_ip_d_1 avl_ad9144_xcvr.tx_phy_d_2
+add_connection avl_ad9144_xcvr.tx_ip_d_2 avl_ad9144_xcvr.tx_phy_d_3
+add_connection sys_cpu.data_master avl_ad9144_xcvr.core_pll_reconfig
+add_connection sys_cpu.data_master avl_ad9144_xcvr.lane_pll_reconfig
+add_connection sys_cpu.data_master avl_ad9144_xcvr.ip_reconfig
 
-add_connection sys_clk.clk_reset xcvr_core.reconfig_reset
-add_connection sys_clk.clk xcvr_core.reconfig_clk
-add_connection sys_clk.clk_reset xcvr_core.jesd204_tx_avs_rst_n
-add_connection sys_clk.clk xcvr_core.jesd204_tx_avs_clk
-add_connection sys_clk.clk_reset xcvr_core.jesd204_rx_avs_rst_n
-add_connection sys_clk.clk xcvr_core.jesd204_rx_avs_clk
-add_connection xcvr_core.alldev_lane_aligned xcvr_core.dev_lane_aligned
-add_connection xcvr_core.tx_dev_sync_n xcvr_core.mdev_sync_n
-add_connection sys_cpu.data_master xcvr_core.reconfig_avmm
-add_connection sys_cpu.data_master xcvr_core.jesd204_tx_avs
-add_connection sys_cpu.data_master xcvr_core.jesd204_rx_avs
-add_interface tx_data conduit end
-add_interface rx_data conduit end
-set_interface_property tx_data EXPORT_OF xcvr_core.tx_serial_data
-set_interface_property rx_data EXPORT_OF xcvr_core.rx_serial_data
+# ad9144-xcvr
 
-# ad9144
+add_instance axi_ad9144_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_ad9144_xcvr {ID} {0}
+set_instance_parameter_value axi_ad9144_xcvr {TX_OR_RX_N} {1}
+set_instance_parameter_value axi_ad9144_xcvr {NUM_OF_LANES} {4}
+
+add_connection sys_clk.clk axi_ad9144_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9144_xcvr.s_axi_reset
+add_connection axi_ad9144_xcvr.if_up_rst avl_ad9144_xcvr.rst
+add_connection avl_ad9144_xcvr.ready axi_ad9144_xcvr.ready
+add_connection axi_ad9144_xcvr.core_pll_locked avl_ad9144_xcvr.core_pll_locked
+add_connection sys_cpu.data_master axi_ad9144_xcvr.s_axi
+
+# ad9144-core
 
 add_instance axi_ad9144_core axi_ad9144 1.0
 set_instance_parameter_value axi_ad9144_core {QUAD_OR_DUAL_N} {0}
 
-add_connection xcvr_tx_pll.outclk0 axi_ad9144_core.if_tx_clk
-add_connection axi_jesd_xcvr.if_tx_data axi_ad9144_core.if_tx_data
+add_connection avl_ad9144_xcvr.core_clk axi_ad9144_core.if_tx_clk
+add_connection axi_ad9144_core.if_tx_data avl_ad9144_xcvr.ip_data
 add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
 add_connection sys_cpu.data_master axi_ad9144_core.s_axi
@@ -188,7 +75,7 @@ add_instance util_ad9144_upack util_upack 1.0
 set_instance_parameter_value util_ad9144_upack {CHANNEL_DATA_WIDTH} {64}
 set_instance_parameter_value util_ad9144_upack {NUM_OF_CHANNELS} {2}
 
-add_connection xcvr_tx_pll.outclk0 util_ad9144_upack.if_dac_clk
+add_connection avl_ad9144_xcvr.core_clk util_ad9144_upack.if_dac_clk
 add_connection axi_ad9144_core.dac_ch_0 util_ad9144_upack.dac_ch_0
 add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1
 
@@ -201,7 +88,7 @@ set_instance_parameter_value axi_ad9144_dma {DMA_2D_TRANSFER} {0}
 set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_DEST} {2}
 set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_SRC} {0}
 
-add_connection xcvr_tx_pll.outclk0 axi_ad9144_dma.if_fifo_rd_clk
+add_connection avl_ad9144_xcvr.core_clk axi_ad9144_dma.if_fifo_rd_clk
 add_connection util_ad9144_upack.if_dac_valid axi_ad9144_dma.if_fifo_rd_en
 add_connection util_ad9144_upack.if_dac_data axi_ad9144_dma.if_fifo_rd_dout
 add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf
@@ -213,18 +100,67 @@ add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9144_dma.m_src_axi_clock
 add_connection axi_ad9144_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
 add_connection sys_cpu.irq axi_ad9144_dma.interrupt_sender
 
+# ad9680-xcvr
+
+add_instance avl_ad9680_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_ad9680_xcvr {ID} {1}
+set_instance_parameter_value avl_ad9680_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value avl_ad9680_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value avl_ad9680_xcvr {LANE_RATE} {10000.0}
+set_instance_parameter_value avl_ad9680_xcvr {PLLCLK_FREQUENCY} {5000.0}
+set_instance_parameter_value avl_ad9680_xcvr {REFCLK_FREQUENCY} {500.0}
+set_instance_parameter_value avl_ad9680_xcvr {CORECLK_FREQUENCY} {250.0}
+set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_LANES} {4}
+set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_CONVS} {2}
+set_instance_parameter_value avl_ad9680_xcvr {FRM_BCNT} {1}
+set_instance_parameter_value avl_ad9680_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_ad9680_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_ad9680_xcvr {HD} {1}
+
+add_connection sys_clk.clk avl_ad9680_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_ad9680_xcvr.sys_resetn
+add_interface rx_ref_clk clock sink
+set_interface_property rx_ref_clk EXPORT_OF avl_ad9680_xcvr.ref_clk
+add_interface rx_data_0 conduit end
+set_interface_property rx_data_0 EXPORT_OF avl_ad9680_xcvr.rx_data_0
+add_interface rx_data_1 conduit end
+set_interface_property rx_data_1 EXPORT_OF avl_ad9680_xcvr.rx_data_1
+add_interface rx_data_2 conduit end
+set_interface_property rx_data_2 EXPORT_OF avl_ad9680_xcvr.rx_data_2
+add_interface rx_data_3 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_ad9680_xcvr.rx_data_3
+add_interface rx_sysref conduit end
+set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref
+add_interface rx_sync conduit end
+set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync
+add_connection sys_cpu.data_master avl_ad9680_xcvr.core_pll_reconfig
+add_connection sys_cpu.data_master avl_ad9680_xcvr.ip_reconfig
+
+# ad9680-xcvr
+
+add_instance axi_ad9680_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_ad9680_xcvr {ID} {1}
+set_instance_parameter_value axi_ad9680_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value axi_ad9680_xcvr {NUM_OF_LANES} {4}
+
+add_connection sys_clk.clk axi_ad9680_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset
+add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst
+add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready
+add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked
+add_connection sys_cpu.data_master axi_ad9680_xcvr.s_axi
+
 # ad9680
 
 add_instance axi_ad9680_core axi_ad9680 1.0
 
-add_connection xcvr_rx_pll.outclk0 axi_ad9680_core.if_rx_clk
+add_connection avl_ad9680_xcvr.core_clk axi_ad9680_core.if_rx_clk
+add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof
+add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
 add_connection sys_cpu.data_master axi_ad9680_core.s_axi
 
-add_connection xcvr_core.jesd204_rx_link axi_ad9680_core.if_rx_ip_avl
-add_connection xcvr_core.rx_sof axi_ad9680_core.if_rx_sof
-
 # ad9680-pack
 
 add_instance util_ad9680_cpack util_cpack 1.0
@@ -233,7 +169,7 @@ set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
 
 add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
 add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst
-add_connection xcvr_rx_pll.outclk0 util_ad9680_cpack.if_adc_clk
+add_connection avl_ad9680_xcvr.core_clk util_ad9680_cpack.if_adc_clk
 add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
 add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
 
@@ -246,7 +182,7 @@ set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
 
 add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
 add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst
-add_connection xcvr_rx_pll.outclk0 ad9680_adcfifo.if_adc_clk
+add_connection avl_ad9680_xcvr.core_clk ad9680_adcfifo.if_adc_clk
 add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
 add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
 add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk
@@ -277,24 +213,65 @@ add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
 add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
 add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
 
+# reconfig sharing
+
+add_instance avl_adxcfg_0 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
+add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s0
+add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s1
+add_connection avl_adxcfg_0.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_0
+add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0
+
+add_instance avl_adxcfg_1 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
+add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s0
+add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s1
+add_connection avl_adxcfg_1.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_1
+add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1
+
+add_instance avl_adxcfg_2 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
+add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s0
+add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s1
+add_connection avl_adxcfg_2.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_2
+add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2
+
+add_instance avl_adxcfg_3 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
+add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s0
+add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s1
+add_connection avl_adxcfg_3.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_3
+add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3
 
 # addresses
 
-set_connection_parameter_value sys_cpu.data_master/xcvr_rx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d800}
-set_connection_parameter_value sys_cpu.data_master/xcvr_tx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0        baseAddress {0x1003c000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi                   baseAddress {0x10034000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi                  baseAddress {0x10010000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9144_dma.s_axi                   baseAddress {0x10038000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9144_core.s_axi                  baseAddress {0x10020000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_core.reconfig_avmm                baseAddress {0x10030000}
-set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi                    baseAddress {0x10000000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_tx_avs               baseAddress {0x1003e000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_rx_avs               baseAddress {0x1003e400}
-set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.core_pll_reconfig      baseAddress {0x10400000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.ip_reconfig            baseAddress {0x10401000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.lane_pll_reconfig      baseAddress {0x10402000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9144_dma.s_axi                   baseAddress {0x1040c000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9144_xcvr.s_axi                  baseAddress {0x10410000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9144_core.s_axi                  baseAddress {0x10420000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.core_pll_reconfig      baseAddress {0x10500000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.ip_reconfig            baseAddress {0x10501000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi                   baseAddress {0x1050c000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_xcvr.s_axi                  baseAddress {0x10510000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi                  baseAddress {0x10520000}
 set_connection_parameter_value axi_ad9144_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
+set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s0                   baseAddress {0x10404000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s0                   baseAddress {0x10405000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s0                   baseAddress {0x10406000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s0                   baseAddress {0x10407000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s1                   baseAddress {0x10504000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s1                   baseAddress {0x10505000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s1                   baseAddress {0x10506000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s1                   baseAddress {0x10507000}
 
 # interrupts
 
-set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}
 set_connection_parameter_value sys_cpu.irq/axi_ad9144_dma.interrupt_sender irqNumber {11}
+set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}

From 01b7662e051aff8c5ebf322477c030bfb2216107 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:52:28 -0400
Subject: [PATCH 470/972] axi_ad9680- qsys updates

---
 library/axi_ad9680/axi_ad9680_hw.tcl | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl
index eb90f4386..3d91a4ecc 100755
--- a/library/axi_ad9680/axi_ad9680_hw.tcl
+++ b/library/axi_ad9680/axi_ad9680_hw.tcl
@@ -84,12 +84,12 @@ add_interface_port s_axi s_axi_rready rready Input 1
 ad_alt_intf clock   rx_clk        input   1
 ad_alt_intf signal  rx_sof        input   4 export
 
-add_interface if_rx_ip_avl avalon_streaming sink
-add_interface_port if_rx_ip_avl rx_data  data  input 128
-add_interface_port if_rx_ip_avl rx_valid valid input 1
-add_interface_port if_rx_ip_avl rx_ready ready output 1
-set_interface_property if_rx_ip_avl associatedClock if_rx_clk
-set_interface_property if_rx_ip_avl dataBitsPerSymbol 128
+add_interface if_rx_data avalon_streaming sink
+add_interface_port if_rx_data rx_data  data  input 128
+add_interface_port if_rx_data rx_valid valid input 1
+add_interface_port if_rx_data rx_ready ready output 1
+set_interface_property if_rx_data associatedClock if_rx_clk
+set_interface_property if_rx_data dataBitsPerSymbol 128
 
 # dma interface
 

From bced17a16fbd7f6ac53f28ebf69cbb51bf22b8b8 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 12 Sep 2016 14:55:02 -0400
Subject: [PATCH 471/972] axi_ad9144- qsys updates

---
 library/axi_ad9144/axi_ad9144.v      | 142 ++++++++++++++-------------
 library/axi_ad9144/axi_ad9144_hw.tcl |  15 ++-
 library/axi_ad9144/axi_ad9144_if.v   |  72 +++++++-------
 library/axi_ad9144/axi_ad9144_ip.tcl |   1 +
 4 files changed, 124 insertions(+), 106 deletions(-)

diff --git a/library/axi_ad9144/axi_ad9144.v b/library/axi_ad9144/axi_ad9144.v
index aace45040..5aa391974 100644
--- a/library/axi_ad9144/axi_ad9144.v
+++ b/library/axi_ad9144/axi_ad9144.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -45,7 +43,9 @@ module axi_ad9144 (
   // tx_clk is (line-rate/40)
 
   tx_clk,
+  tx_valid,
   tx_data,
+  tx_ready,
 
   // dma interface
 
@@ -92,90 +92,93 @@ module axi_ad9144 (
   // parameters
 
   parameter   ID = 0;
+  parameter   DEVICE_TYPE = 0;
   parameter   QUAD_OR_DUAL_N = 1;
   parameter   DAC_DATAPATH_DISABLE = 0;
 
   // jesd interface
   // tx_clk is (line-rate/40)
 
-  input                                     tx_clk;
-  output  [(128*QUAD_OR_DUAL_N)+127:0]   tx_data;
+  input                                   tx_clk;
+  output                                  tx_valid;
+  output  [(128*QUAD_OR_DUAL_N)+127:0]    tx_data;
+  input                                   tx_ready;
 
   // dma interface
 
-  output                                    dac_clk;
-  output                                    dac_valid_0;
-  output                                    dac_enable_0;
-  input   [63:0]                            dac_ddata_0;
-  output                                    dac_valid_1;
-  output                                    dac_enable_1;
-  input   [63:0]                            dac_ddata_1;
-  output                                    dac_valid_2;
-  output                                    dac_enable_2;
-  input   [63:0]                            dac_ddata_2;
-  output                                    dac_valid_3;
-  output                                    dac_enable_3;
-  input   [63:0]                            dac_ddata_3;
-  input                                     dac_dovf;
-  input                                     dac_dunf;
+  output                                  dac_clk;
+  output                                  dac_valid_0;
+  output                                  dac_enable_0;
+  input   [63:0]                          dac_ddata_0;
+  output                                  dac_valid_1;
+  output                                  dac_enable_1;
+  input   [63:0]                          dac_ddata_1;
+  output                                  dac_valid_2;
+  output                                  dac_enable_2;
+  input   [63:0]                          dac_ddata_2;
+  output                                  dac_valid_3;
+  output                                  dac_enable_3;
+  input   [63:0]                          dac_ddata_3;
+  input                                   dac_dovf;
+  input                                   dac_dunf;
 
   // axi interface
 
-  input                                     s_axi_aclk;
-  input                                     s_axi_aresetn;
-  input                                     s_axi_awvalid;
-  input   [ 31:0]                           s_axi_awaddr;
-  input   [  2:0]                           s_axi_awprot;
-  output                                    s_axi_awready;
-  input                                     s_axi_wvalid;
-  input   [ 31:0]                           s_axi_wdata;
-  input   [  3:0]                           s_axi_wstrb;
-  output                                    s_axi_wready;
-  output                                    s_axi_bvalid;
-  output  [  1:0]                           s_axi_bresp;
-  input                                     s_axi_bready;
-  input                                     s_axi_arvalid;
-  input   [ 31:0]                           s_axi_araddr;
-  input   [  2:0]                           s_axi_arprot;
-  output                                    s_axi_arready;
-  output                                    s_axi_rvalid;
-  output  [ 31:0]                           s_axi_rdata;
-  output  [  1:0]                           s_axi_rresp;
-  input                                     s_axi_rready;
+  input                                   s_axi_aclk;
+  input                                   s_axi_aresetn;
+  input                                   s_axi_awvalid;
+  input   [ 31:0]                         s_axi_awaddr;
+  input   [  2:0]                         s_axi_awprot;
+  output                                  s_axi_awready;
+  input                                   s_axi_wvalid;
+  input   [ 31:0]                         s_axi_wdata;
+  input   [  3:0]                         s_axi_wstrb;
+  output                                  s_axi_wready;
+  output                                  s_axi_bvalid;
+  output  [  1:0]                         s_axi_bresp;
+  input                                   s_axi_bready;
+  input                                   s_axi_arvalid;
+  input   [ 31:0]                         s_axi_araddr;
+  input   [  2:0]                         s_axi_arprot;
+  output                                  s_axi_arready;
+  output                                  s_axi_rvalid;
+  output  [ 31:0]                         s_axi_rdata;
+  output  [  1:0]                         s_axi_rresp;
+  input                                   s_axi_rready;
 
   // internal clocks and resets
 
-  wire                                      dac_rst;
-  wire                                      up_clk;
-  wire                                      up_rstn;
+  wire                                    dac_rst;
+  wire                                    up_clk;
+  wire                                    up_rstn;
 
   // internal signals
 
-  wire    [255:0]                           tx_data_s;
-  wire    [ 15:0]                           dac_data_0_0_s;
-  wire    [ 15:0]                           dac_data_0_1_s;
-  wire    [ 15:0]                           dac_data_0_2_s;
-  wire    [ 15:0]                           dac_data_0_3_s;
-  wire    [ 15:0]                           dac_data_1_0_s;
-  wire    [ 15:0]                           dac_data_1_1_s;
-  wire    [ 15:0]                           dac_data_1_2_s;
-  wire    [ 15:0]                           dac_data_1_3_s;
-  wire    [ 15:0]                           dac_data_2_0_s;
-  wire    [ 15:0]                           dac_data_2_1_s;
-  wire    [ 15:0]                           dac_data_2_2_s;
-  wire    [ 15:0]                           dac_data_2_3_s;
-  wire    [ 15:0]                           dac_data_3_0_s;
-  wire    [ 15:0]                           dac_data_3_1_s;
-  wire    [ 15:0]                           dac_data_3_2_s;
-  wire    [ 15:0]                           dac_data_3_3_s;
-  wire                                      up_wreq_s;
-  wire    [ 13:0]                           up_waddr_s;
-  wire    [ 31:0]                           up_wdata_s;
-  wire                                      up_wack_s;
-  wire                                      up_rreq_s;
-  wire    [ 13:0]                           up_raddr_s;
-  wire    [ 31:0]                           up_rdata_s;
-  wire                                      up_rack_s;
+  wire    [255:0]                         tx_data_s;
+  wire    [ 15:0]                         dac_data_0_0_s;
+  wire    [ 15:0]                         dac_data_0_1_s;
+  wire    [ 15:0]                         dac_data_0_2_s;
+  wire    [ 15:0]                         dac_data_0_3_s;
+  wire    [ 15:0]                         dac_data_1_0_s;
+  wire    [ 15:0]                         dac_data_1_1_s;
+  wire    [ 15:0]                         dac_data_1_2_s;
+  wire    [ 15:0]                         dac_data_1_3_s;
+  wire    [ 15:0]                         dac_data_2_0_s;
+  wire    [ 15:0]                         dac_data_2_1_s;
+  wire    [ 15:0]                         dac_data_2_2_s;
+  wire    [ 15:0]                         dac_data_2_3_s;
+  wire    [ 15:0]                         dac_data_3_0_s;
+  wire    [ 15:0]                         dac_data_3_1_s;
+  wire    [ 15:0]                         dac_data_3_2_s;
+  wire    [ 15:0]                         dac_data_3_3_s;
+  wire                                    up_wreq_s;
+  wire    [ 13:0]                         up_waddr_s;
+  wire    [ 31:0]                         up_wdata_s;
+  wire                                    up_wack_s;
+  wire                                    up_rreq_s;
+  wire    [ 13:0]                         up_raddr_s;
+  wire    [ 31:0]                         up_rdata_s;
+  wire                                    up_rack_s;
 
   // signal name changes
 
@@ -184,11 +187,12 @@ module axi_ad9144 (
 
   // dual/quad cores
 
+  assign tx_valid = 1'b1;
   assign tx_data = (QUAD_OR_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0];
 
   // device interface
 
-  axi_ad9144_if i_if (
+  axi_ad9144_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
     .tx_clk (tx_clk),
     .tx_data (tx_data_s),
     .dac_clk (dac_clk),
diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl
index 1bd871a6e..a30d9aa5e 100755
--- a/library/axi_ad9144/axi_ad9144_hw.tcl
+++ b/library/axi_ad9144/axi_ad9144_hw.tcl
@@ -48,6 +48,13 @@ set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
 set_parameter_property QUAD_OR_DUAL_N UNITS None
 set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
 
+add_parameter DEVICE_TYPE INTEGER 0
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
 # axi4 slave
 
 add_interface s_axi_clock clock end
@@ -83,7 +90,13 @@ add_interface_port s_axi s_axi_rready rready Input 1
 # transceiver interface
 
 ad_alt_intf clock   tx_clk        input   1
-ad_alt_intf signal  tx_data       output  128*(QUAD_OR_DUAL_N+1) data
+
+add_interface if_tx_data avalon_streaming source
+add_interface_port if_tx_data tx_data data output 128*(QUAD_OR_DUAL_N+1)
+add_interface_port if_tx_data tx_valid valid output 1
+add_interface_port if_tx_data tx_ready ready input 1
+set_interface_property if_tx_data associatedClock if_tx_clk
+set_interface_property if_tx_data dataBitsPerSymbol 128
 
 # dma interface
 
diff --git a/library/axi_ad9144/axi_ad9144_if.v b/library/axi_ad9144/axi_ad9144_if.v
index 09ee3b6fe..7d3836631 100644
--- a/library/axi_ad9144/axi_ad9144_if.v
+++ b/library/axi_ad9144/axi_ad9144_if.v
@@ -34,10 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// This is the dac physical interface (drives samples from the low speed clock to the
-// dac clock domain.
 
 `timescale 1ns/100ps
 
@@ -70,6 +66,10 @@ module axi_ad9144_if (
   dac_data_3_2,
   dac_data_3_3);
 
+  // altera (0x1) or xilinx (0x0)
+
+  parameter DEVICE_TYPE = 0;
+
   // jesd interface
   // tx_clk is (line-rate/40)
 
@@ -109,38 +109,38 @@ module axi_ad9144_if (
     if (dac_rst == 1'b1) begin
       tx_data <= 256'd0;
     end else begin
-      tx_data[255:248] <= dac_data_3_3[ 7: 0];
-      tx_data[247:240] <= dac_data_3_2[ 7: 0];
-      tx_data[239:232] <= dac_data_3_1[ 7: 0];
-      tx_data[231:224] <= dac_data_3_0[ 7: 0];
-      tx_data[223:216] <= dac_data_3_3[15: 8];
-      tx_data[215:208] <= dac_data_3_2[15: 8];
-      tx_data[207:200] <= dac_data_3_1[15: 8];
-      tx_data[199:192] <= dac_data_3_0[15: 8];
-      tx_data[191:184] <= dac_data_2_3[ 7: 0];
-      tx_data[183:176] <= dac_data_2_2[ 7: 0];
-      tx_data[175:168] <= dac_data_2_1[ 7: 0];
-      tx_data[167:160] <= dac_data_2_0[ 7: 0];
-      tx_data[159:152] <= dac_data_2_3[15: 8];
-      tx_data[151:144] <= dac_data_2_2[15: 8];
-      tx_data[143:136] <= dac_data_2_1[15: 8];
-      tx_data[135:128] <= dac_data_2_0[15: 8];
-      tx_data[127:120] <= dac_data_1_3[ 7: 0];
-      tx_data[119:112] <= dac_data_1_2[ 7: 0];
-      tx_data[111:104] <= dac_data_1_1[ 7: 0];
-      tx_data[103: 96] <= dac_data_1_0[ 7: 0];
-      tx_data[ 95: 88] <= dac_data_1_3[15: 8];
-      tx_data[ 87: 80] <= dac_data_1_2[15: 8];
-      tx_data[ 79: 72] <= dac_data_1_1[15: 8];
-      tx_data[ 71: 64] <= dac_data_1_0[15: 8];
-      tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
-      tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
-      tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
-      tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
-      tx_data[ 31: 24] <= dac_data_0_3[15: 8];
-      tx_data[ 23: 16] <= dac_data_0_2[15: 8];
-      tx_data[ 15:  8] <= dac_data_0_1[15: 8];
-      tx_data[  7:  0] <= dac_data_0_0[15: 8];
+      tx_data[255:248] <= (DEVICE_TYPE == 1) ? dac_data_3_0[ 7: 0] : dac_data_3_3[ 7: 0];
+      tx_data[247:240] <= (DEVICE_TYPE == 1) ? dac_data_3_1[ 7: 0] : dac_data_3_2[ 7: 0];
+      tx_data[239:232] <= (DEVICE_TYPE == 1) ? dac_data_3_2[ 7: 0] : dac_data_3_1[ 7: 0];
+      tx_data[231:224] <= (DEVICE_TYPE == 1) ? dac_data_3_3[ 7: 0] : dac_data_3_0[ 7: 0];
+      tx_data[223:216] <= (DEVICE_TYPE == 1) ? dac_data_3_0[15: 8] : dac_data_3_3[15: 8];
+      tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data_3_1[15: 8] : dac_data_3_2[15: 8];
+      tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data_3_2[15: 8] : dac_data_3_1[15: 8];
+      tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data_3_3[15: 8] : dac_data_3_0[15: 8];
+      tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data_2_0[ 7: 0] : dac_data_2_3[ 7: 0];
+      tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data_2_1[ 7: 0] : dac_data_2_2[ 7: 0];
+      tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data_2_2[ 7: 0] : dac_data_2_1[ 7: 0];
+      tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data_2_3[ 7: 0] : dac_data_2_0[ 7: 0];
+      tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data_2_0[15: 8] : dac_data_2_3[15: 8];
+      tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data_2_1[15: 8] : dac_data_2_2[15: 8];
+      tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data_2_2[15: 8] : dac_data_2_1[15: 8];
+      tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data_2_3[15: 8] : dac_data_2_0[15: 8];
+      tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data_1_0[ 7: 0] : dac_data_1_3[ 7: 0];
+      tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data_1_1[ 7: 0] : dac_data_1_2[ 7: 0];
+      tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data_1_2[ 7: 0] : dac_data_1_1[ 7: 0];
+      tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data_1_3[ 7: 0] : dac_data_1_0[ 7: 0];
+      tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data_1_0[15: 8] : dac_data_1_3[15: 8];
+      tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data_1_1[15: 8] : dac_data_1_2[15: 8];
+      tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data_1_2[15: 8] : dac_data_1_1[15: 8];
+      tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data_1_3[15: 8] : dac_data_1_0[15: 8];
+      tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data_0_0[ 7: 0] : dac_data_0_3[ 7: 0];
+      tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data_0_1[ 7: 0] : dac_data_0_2[ 7: 0];
+      tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data_0_2[ 7: 0] : dac_data_0_1[ 7: 0];
+      tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data_0_3[ 7: 0] : dac_data_0_0[ 7: 0];
+      tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data_0_0[15: 8] : dac_data_0_3[15: 8];
+      tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data_0_1[15: 8] : dac_data_0_2[15: 8];
+      tx_data[ 15:  8] <= (DEVICE_TYPE == 1) ? dac_data_0_2[15: 8] : dac_data_0_1[15: 8];
+      tx_data[  7:  0] <= (DEVICE_TYPE == 1) ? dac_data_0_3[15: 8] : dac_data_0_0[15: 8];
     end
   end
 
diff --git a/library/axi_ad9144/axi_ad9144_ip.tcl b/library/axi_ad9144/axi_ad9144_ip.tcl
index 13f868e4d..7482746dd 100644
--- a/library/axi_ad9144/axi_ad9144_ip.tcl
+++ b/library/axi_ad9144/axi_ad9144_ip.tcl
@@ -29,6 +29,7 @@ adi_ip_constraints axi_ad9144 [list \
 
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]
 

From 9a2d2e8a02fd5b8c4675bdfbba4c1bd295211dda Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 13 Sep 2016 15:04:11 +0300
Subject: [PATCH 472/972] version_upgrade: Update FMCADC4 to 2016.2

---
 projects/fmcadc4/common/fmcadc4_bd.tcl | 2 +-
 projects/fmcadc4/zc706/system_bd.tcl   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl
index ae3537bd6..c4a910818 100644
--- a/projects/fmcadc4/common/fmcadc4_bd.tcl
+++ b/projects/fmcadc4/common/fmcadc4_bd.tcl
@@ -14,7 +14,7 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0
 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1]
 set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1
 
-set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
+set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd
 
diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl
index a20c17b24..59392004d 100644
--- a/projects/fmcadc4/zc706/system_bd.tcl
+++ b/projects/fmcadc4/zc706/system_bd.tcl
@@ -21,14 +21,14 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
 
 source ../common/fmcadc4_bd.tcl
 
-# ila 
+# ila
 
 set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc]
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc
 set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
 set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
 
-set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
+set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
 set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc

From cf9ac730a86d792b315ffba086189585eef75c7d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 13 Sep 2016 10:31:54 -0400
Subject: [PATCH 473/972] pzsdr1- new rev. board delays

---
 projects/common/pzsdr1/pzsdr1_system_ps7.tcl | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/projects/common/pzsdr1/pzsdr1_system_ps7.tcl b/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
index 916b5c86b..d66e148d7 100755
--- a/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
+++ b/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
@@ -32,12 +32,12 @@ set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF             {0}
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL             {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE               {1}                     [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE                {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {0.066}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {0.029}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {-0.017}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {-0.038}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.301}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.330}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.314}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.333}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {0.110}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {0.095}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {0.249}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {0.249}                [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.202}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.217}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.216}                 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.217}                 [get_bd_cells sys_ps7]
 

From 734b39a8ed32c41065a60e786618f1e47091d039 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 13 Sep 2016 17:39:54 +0300
Subject: [PATCH 474/972] alt_serdes: Fix some issues in the _hw.tcl script

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index a9ec823ec..fe7b464c9 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -98,8 +98,8 @@ proc p_alt_serdes {} {
 
   if {$m_mode == "IN"} {
 
-    add_hdl_instance alt_serdes_in altera_lvds
-    set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo}
+    add_instance alt_serdes_in altera_lvds
+    set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO}
     set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
     set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate
     set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor
@@ -108,11 +108,11 @@ proc p_alt_serdes {} {
     set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
     add_interface data_in conduit end
     set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in
-    add_interface clk clock sink
+    add_interface clk conduit end
     set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk
     add_interface loaden conduit end
     set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden
-    add_interface div_clk clock sink
+    add_interface div_clk conduit end
     set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock
     add_interface hs_phase conduit end
     set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph
@@ -126,7 +126,7 @@ proc p_alt_serdes {} {
 
   if {$m_mode == "OUT"} {
 
-    add_hdl_instance alt_serdes_out altera_lvds
+    add_instance alt_serdes_out altera_lvds
     set_instance_parameter_value alt_serdes_out {MODE} {TX}
     set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
     set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate
@@ -137,11 +137,11 @@ proc p_alt_serdes {} {
     set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
     add_interface data_out conduit end
     set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out
-    add_interface clk clock sink
+    add_interface clk conduit end
     set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk
     add_interface loaden conduit end
     set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden
-    add_interface div_clk clock sink
+    add_interface div_clk conduit end
     set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock
     add_interface data_s conduit end
     set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in

From a0318ae8683097be85e9404bb6622510f077aa18 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 13 Sep 2016 14:02:11 -0400
Subject: [PATCH 475/972] ad_serdes_clk- syntax errors

---
 library/altera/common/ad_serdes_clk.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
index b417627d7..c065dd061 100644
--- a/library/altera/common/ad_serdes_clk.v
+++ b/library/altera/common/ad_serdes_clk.v
@@ -78,7 +78,7 @@ module ad_serdes_clk (
 
   // internal signals
 
-  wire    [31:0]  up_drp_rdata_int_s,
+  wire    [31:0]  up_drp_rdata_int_s;
   wire            up_drp_busy_int_s;
   wire            up_drp_locked_int_s;
 

From 9118ca3986180036db5bd954f16de3b5ad63d397 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 14 Sep 2016 10:58:06 +0300
Subject: [PATCH 476/972] version_upgrade: Update MOTCON2 to 2016.2

---
 projects/motcon2_fmc/common/motcon2_fmc_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
index 1cdf24f90..ac2ce0bfa 100644
--- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
+++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
@@ -160,7 +160,7 @@
   set iic_ee2  [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ]
 
   # xadc
-  set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.2 xadc_core ]
+  set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_core ]
   set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core
   set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core
   set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL  {VAUXP0_VAUXN0} ] $xadc_core

From 343056b67425d1a700d2f3e7bdc0d839d0461316 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 14 Sep 2016 15:40:42 +0300
Subject: [PATCH 477/972] axi_usb_fx3: Update IP to work with 2016.2

---
 library/axi_usb_fx3/axi_usb_fx3_ip.tcl | 18 +-----------------
 1 file changed, 1 insertion(+), 17 deletions(-)

diff --git a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
index fc62ff2c6..d7d0d1633 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
+++ b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
@@ -12,25 +12,9 @@ adi_ip_files axi_usb_fx3 [list \
   "axi_usb_fx3.v"]
 
 adi_ip_properties axi_usb_fx3
-
-ipx::remove_bus_interface rst [ipx::current_core]
-ipx::remove_bus_interface clk [ipx::current_core]
-ipx::remove_bus_interface l_clk [ipx::current_core]
-ipx::remove_bus_interface delay_clk [ipx::current_core]
+adi_ip_infer_interfaces axi_usb_fx3
 
 adi_add_bus_clock "s_axi_aclk" "s_axis"
 adi_add_bus_clock "s_axi_aclk" "m_axis"
 
-ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
-  -of_objects [ipx::current_core]]
-set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-  -of_objects [ipx::get_bus_interfaces s_axi_aclk \
-  -of_objects [ipx::current_core]]]
-
-#adi_ip_constraints axi_usb_fx3 [list \
-#  "axi_usb_fx3_constr.xdc" ]
-
-#set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
-#set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
-
 ipx::save_core [ipx::current_core]

From 631923e9f04ba47d96e683ffcc607ffd8535fdf7 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 14 Sep 2016 15:41:27 +0300
Subject: [PATCH 478/972] usb_fx3: Update to Vivado 2016.2

---
 projects/usb_fx3/common/usb_fx3_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl
index a497bbd2c..3dbcdde85 100644
--- a/projects/usb_fx3/common/usb_fx3_bd.tcl
+++ b/projects/usb_fx3/common/usb_fx3_bd.tcl
@@ -65,7 +65,7 @@ ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM
 
 # test
 
-set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila]
+set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila]
 
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila
 set_property -dict [list CONFIG.C_NUM_OF_PROBES {11}] $ila

From 4a6b554c0aed5c7e23c3f764b1ab6099d4eeb88f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 14 Sep 2016 11:12:53 -0400
Subject: [PATCH 479/972] ad_serdes- updates

---
 library/altera/common/ad_serdes_in.v  | 31 ++++++++++++++-------------
 library/altera/common/ad_serdes_out.v | 24 ++++++++++-----------
 2 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 9b99895a8..04cb86321 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -47,6 +47,7 @@ module ad_serdes_in (
   input           div_clk,
   input           loaden,
   input           hs_phase,
+  input           locked,
 
   // data interface
 
@@ -81,21 +82,21 @@ module ad_serdes_in (
   // instantiations
 
   alt_serdes_in_core i_core (
-    .data_in (data_in_p),
-    .clk (clk),
-    .loaden (loaden),
-    .div_clk (div_clk),
-    .hs_phase (hs_phase),
-    .locked (locked),
-    .data_s ({data_s7,
-              data_s6,
-              data_s5,
-              data_s4,
-              data_s3,
-              data_s2,
-              data_s1,
-              data_s0}),
-    .delay_locked (delay_locked));
+    .clk_export (clk),
+    .div_clk_export (div_clk),
+    .hs_phase_export (hs_phase),
+    .loaden_export (loaden),
+    .locked_export (locked),
+    .data_in_export (data_in_p),
+    .data_s_export ({ data_s7,
+                      data_s6,
+                      data_s5,
+                      data_s4,
+                      data_s3,
+                      data_s2,
+                      data_s1,
+                      data_s0}),
+    .delay_locked_export (delay_locked));
 
 endmodule
 
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index 45ccc4036..e0e98d3ee 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -80,18 +80,18 @@ module ad_serdes_out (
   generate
   for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
   alt_serdes_out_core i_core (
-    .data_out (data_out_p[l_inst]),
-    .clk (clk),
-    .loaden (loaden),
-    .div_clk (div_clk),
-    .data_s ({data_s7[l_inst],
-      data_s6[l_inst],
-      data_s5[l_inst],
-      data_s4[l_inst],
-      data_s3[l_inst],
-      data_s2[l_inst],
-      data_s1[l_inst],
-      data_s0[l_inst]}));
+    .clk_export (clk),
+    .div_clk_export (div_clk),
+    .loaden_export (loaden),
+    .data_out_export (data_out_p[l_inst]),
+    .data_s_export ({ data_s7[l_inst],
+                      data_s6[l_inst],
+                      data_s5[l_inst],
+                      data_s4[l_inst],
+                      data_s3[l_inst],
+                      data_s2[l_inst],
+                      data_s1[l_inst],
+                      data_s0[l_inst]}));
   end
   endgenerate
 

From 16046a984cea46e74188b2577d68f5bc4253db05 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 14 Sep 2016 12:05:48 -0400
Subject: [PATCH 480/972] alt_serdes- updates

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 3 ++-
 library/altera/common/ad_serdes_clk.v       | 3 +++
 library/altera/common/ad_serdes_in.v        | 4 ++++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index fe7b464c9..56fdd9586 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -131,10 +131,11 @@ proc p_alt_serdes {} {
     set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
     set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate
     set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor
+    set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
+    set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
     set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
     set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
     set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
-    set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
     add_interface data_out conduit end
     set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out
     add_interface clk conduit end
diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
index c065dd061..75492f68d 100644
--- a/library/altera/common/ad_serdes_clk.v
+++ b/library/altera/common/ad_serdes_clk.v
@@ -85,6 +85,9 @@ module ad_serdes_clk (
   // defaults
 
   assign out_clk = div_clk;
+  assign up_drp_rdata = up_drp_rdata_int;
+  assign up_drp_ready = up_drp_ready_int;
+  assign up_drp_locked = up_drp_locked_int;
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 1'b0) begin
diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 04cb86321..545051797 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -79,6 +79,10 @@ module ad_serdes_in (
 
   parameter       DEVICE_TYPE  = 0;
 
+  // assignments
+
+  assign up_drdata = 5'd0;
+
   // instantiations
 
   alt_serdes_in_core i_core (

From fe133a7c39f04a6c9cd287e2c5e9d7f167313d7f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 14 Sep 2016 15:47:45 -0400
Subject: [PATCH 481/972] v2001- parameter defines

---
 library/altera/avl_adxphy/avl_adxphy.v    | 10 +++++-----
 library/altera/axi_adxcvr/axi_adxcvr.v    | 14 +++++++-------
 library/altera/axi_adxcvr/axi_adxcvr_up.v | 11 +++++++----
 3 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/library/altera/avl_adxphy/avl_adxphy.v b/library/altera/avl_adxphy/avl_adxphy.v
index 36428fa2d..e8590ae81 100644
--- a/library/altera/avl_adxphy/avl_adxphy.v
+++ b/library/altera/avl_adxphy/avl_adxphy.v
@@ -38,7 +38,11 @@
 
 `timescale 1ns/1ps
 
-module avl_adxphy (
+module avl_adxphy #(
+
+  // parameters
+
+  parameter   integer NUM_OF_LANES = 4) (
 
   // rx-ip interface
 
@@ -369,10 +373,6 @@ module avl_adxphy (
   input   [((NUM_OF_LANES* 1)-1):0]   tx_core_digitalreset,
   output  [((NUM_OF_LANES* 1)-1):0]   tx_core_cal_busy);
 
-  // parameters
-
-  parameter   integer NUM_OF_LANES = 4;
-
   // rx assignments
 
   generate
diff --git a/library/altera/axi_adxcvr/axi_adxcvr.v b/library/altera/axi_adxcvr/axi_adxcvr.v
index ff28d082b..c2d3b6ea0 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr.v
@@ -37,7 +37,13 @@
 
 `timescale 1ns/1ps
 
-module axi_adxcvr (
+module axi_adxcvr #(
+
+  // parameters
+
+  parameter   integer ID = 0,
+  parameter   integer TX_OR_RX_N = 0,
+  parameter   integer NUM_OF_LANES = 4) (
 
   // xcvr, lane-pll and ref-pll are shared
 
@@ -67,12 +73,6 @@ module axi_adxcvr (
   output  [31:0]                s_axi_rdata,
   input                         s_axi_rready);
 
-  // parameters
-
-  parameter   integer ID = 0;
-  parameter   integer TX_OR_RX_N = 0;
-  parameter   integer NUM_OF_LANES = 4;
-
   // internal signals
 
   wire                          up_rstn;
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v
index 88418242f..0ef6c3082 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v
@@ -37,7 +37,13 @@
 
 `timescale 1ns/100ps
 
-module axi_adxcvr_up (
+module axi_adxcvr_up #(
+
+  // parameters
+
+  parameter   integer ID = 0,
+  parameter   integer TX_OR_RX_N = 0,
+  parameter   integer NUM_OF_LANES = 4) (
 
   // xcvr, lane-pll and ref-pll are shared
 
@@ -61,9 +67,6 @@ module axi_adxcvr_up (
   // parameters
 
   localparam  [31:0]  VERSION = 32'h00100161;
-  parameter   integer ID = 0;
-  parameter   integer TX_OR_RX_N = 0;
-  parameter   integer NUM_OF_LANES = 4;
 
   // internal registers
 

From 3cbbc771a8eed4b4e55bfb7ee9256d5984682330 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 15 Sep 2016 11:36:47 +0300
Subject: [PATCH 482/972] axi_adcfifo: Move IP to library/xilinx

---
 library/{ => xilinx}/axi_adcfifo/Makefile            | 12 ++++++------
 library/{ => xilinx}/axi_adcfifo/axi_adcfifo.v       |  0
 library/{ => xilinx}/axi_adcfifo/axi_adcfifo_adc.v   |  0
 .../{ => xilinx}/axi_adcfifo/axi_adcfifo_constr.xdc  |  0
 library/{ => xilinx}/axi_adcfifo/axi_adcfifo_dma.v   |  0
 library/{ => xilinx}/axi_adcfifo/axi_adcfifo_ip.tcl  |  2 +-
 library/{ => xilinx}/axi_adcfifo/axi_adcfifo_rd.v    |  0
 library/{ => xilinx}/axi_adcfifo/axi_adcfifo_wr.v    |  0
 8 files changed, 7 insertions(+), 7 deletions(-)
 rename library/{ => xilinx}/axi_adcfifo/Makefile (85%)
 rename library/{ => xilinx}/axi_adcfifo/axi_adcfifo.v (100%)
 rename library/{ => xilinx}/axi_adcfifo/axi_adcfifo_adc.v (100%)
 rename library/{ => xilinx}/axi_adcfifo/axi_adcfifo_constr.xdc (100%)
 rename library/{ => xilinx}/axi_adcfifo/axi_adcfifo_dma.v (100%)
 rename library/{ => xilinx}/axi_adcfifo/axi_adcfifo_ip.tcl (98%)
 rename library/{ => xilinx}/axi_adcfifo/axi_adcfifo_rd.v (100%)
 rename library/{ => xilinx}/axi_adcfifo/axi_adcfifo_wr.v (100%)

diff --git a/library/axi_adcfifo/Makefile b/library/xilinx/axi_adcfifo/Makefile
similarity index 85%
rename from library/axi_adcfifo/Makefile
rename to library/xilinx/axi_adcfifo/Makefile
index ce104a3bc..75a50ff56 100644
--- a/library/axi_adcfifo/Makefile
+++ b/library/xilinx/axi_adcfifo/Makefile
@@ -6,12 +6,12 @@
 ####################################################################################
 
 M_DEPS := axi_adcfifo_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_mem.v
-M_DEPS += ../common/ad_mem_asym.v
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/ad_axis_inf_rx.v
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip.tcl
+M_DEPS += ../../common/ad_mem.v
+M_DEPS += ../../common/ad_mem_asym.v
+M_DEPS += ../../common/up_xfer_status.v
+M_DEPS += ../../common/ad_axis_inf_rx.v
 M_DEPS += axi_adcfifo_adc.v
 M_DEPS += axi_adcfifo_dma.v
 M_DEPS += axi_adcfifo_wr.v
diff --git a/library/axi_adcfifo/axi_adcfifo.v b/library/xilinx/axi_adcfifo/axi_adcfifo.v
similarity index 100%
rename from library/axi_adcfifo/axi_adcfifo.v
rename to library/xilinx/axi_adcfifo/axi_adcfifo.v
diff --git a/library/axi_adcfifo/axi_adcfifo_adc.v b/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
similarity index 100%
rename from library/axi_adcfifo/axi_adcfifo_adc.v
rename to library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
diff --git a/library/axi_adcfifo/axi_adcfifo_constr.xdc b/library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc
similarity index 100%
rename from library/axi_adcfifo/axi_adcfifo_constr.xdc
rename to library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc
diff --git a/library/axi_adcfifo/axi_adcfifo_dma.v b/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
similarity index 100%
rename from library/axi_adcfifo/axi_adcfifo_dma.v
rename to library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
diff --git a/library/axi_adcfifo/axi_adcfifo_ip.tcl b/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl
similarity index 98%
rename from library/axi_adcfifo/axi_adcfifo_ip.tcl
rename to library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl
index 7343caa24..cfce4030d 100644
--- a/library/axi_adcfifo/axi_adcfifo_ip.tcl
+++ b/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl
@@ -1,6 +1,6 @@
 # ip
 
-source ../scripts/adi_env.tcl
+source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create axi_adcfifo
diff --git a/library/axi_adcfifo/axi_adcfifo_rd.v b/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
similarity index 100%
rename from library/axi_adcfifo/axi_adcfifo_rd.v
rename to library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
diff --git a/library/axi_adcfifo/axi_adcfifo_wr.v b/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v
similarity index 100%
rename from library/axi_adcfifo/axi_adcfifo_wr.v
rename to library/xilinx/axi_adcfifo/axi_adcfifo_wr.v

From 3b0c1e02fc05bf39d16937315ce6ca6df94ecd67 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 15 Sep 2016 11:38:16 +0300
Subject: [PATCH 483/972] axi_dacfifo: Move IP to library/xilinx

---
 library/{ => xilinx}/axi_dacfifo/Makefile              | 10 +++++-----
 library/{ => xilinx}/axi_dacfifo/axi_dacfifo.v         |  0
 .../{ => xilinx}/axi_dacfifo/axi_dacfifo_constr.xdc    |  0
 library/{ => xilinx}/axi_dacfifo/axi_dacfifo_dac.v     |  0
 library/{ => xilinx}/axi_dacfifo/axi_dacfifo_ip.tcl    |  2 +-
 library/{ => xilinx}/axi_dacfifo/axi_dacfifo_rd.v      |  0
 library/{ => xilinx}/axi_dacfifo/axi_dacfifo_wr.v      |  0
 7 files changed, 6 insertions(+), 6 deletions(-)
 rename library/{ => xilinx}/axi_dacfifo/Makefile (86%)
 rename library/{ => xilinx}/axi_dacfifo/axi_dacfifo.v (100%)
 rename library/{ => xilinx}/axi_dacfifo/axi_dacfifo_constr.xdc (100%)
 rename library/{ => xilinx}/axi_dacfifo/axi_dacfifo_dac.v (100%)
 rename library/{ => xilinx}/axi_dacfifo/axi_dacfifo_ip.tcl (94%)
 rename library/{ => xilinx}/axi_dacfifo/axi_dacfifo_rd.v (100%)
 rename library/{ => xilinx}/axi_dacfifo/axi_dacfifo_wr.v (100%)

diff --git a/library/axi_dacfifo/Makefile b/library/xilinx/axi_dacfifo/Makefile
similarity index 86%
rename from library/axi_dacfifo/Makefile
rename to library/xilinx/axi_dacfifo/Makefile
index 0734805a6..16c5919b7 100644
--- a/library/axi_dacfifo/Makefile
+++ b/library/xilinx/axi_dacfifo/Makefile
@@ -6,11 +6,11 @@
 ####################################################################################
 
 M_DEPS := axi_dacfifo_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_mem_asym.v
-M_DEPS += ../common/ad_axis_inf_rx.v
-M_DEPS += ../util_axis_resize/util_axis_resize.v
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip.tcl
+M_DEPS += ../../common/ad_mem_asym.v
+M_DEPS += ../../common/ad_axis_inf_rx.v
+M_DEPS += ../../util_axis_resize/util_axis_resize.v
 M_DEPS += axi_dacfifo_constr.xdc
 M_DEPS += axi_dacfifo_dac.v
 M_DEPS += axi_dacfifo_wr.v
diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
similarity index 100%
rename from library/axi_dacfifo/axi_dacfifo.v
rename to library/xilinx/axi_dacfifo/axi_dacfifo.v
diff --git a/library/axi_dacfifo/axi_dacfifo_constr.xdc b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
similarity index 100%
rename from library/axi_dacfifo/axi_dacfifo_constr.xdc
rename to library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v
similarity index 100%
rename from library/axi_dacfifo/axi_dacfifo_dac.v
rename to library/xilinx/axi_dacfifo/axi_dacfifo_dac.v
diff --git a/library/axi_dacfifo/axi_dacfifo_ip.tcl b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
similarity index 94%
rename from library/axi_dacfifo/axi_dacfifo_ip.tcl
rename to library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
index 77c5b2acc..67a819ed8 100644
--- a/library/axi_dacfifo/axi_dacfifo_ip.tcl
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
@@ -1,6 +1,6 @@
 # ip
 
-source ../scripts/adi_env.tcl
+source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create axi_dacfifo
diff --git a/library/axi_dacfifo/axi_dacfifo_rd.v b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
similarity index 100%
rename from library/axi_dacfifo/axi_dacfifo_rd.v
rename to library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
similarity index 100%
rename from library/axi_dacfifo/axi_dacfifo_wr.v
rename to library/xilinx/axi_dacfifo/axi_dacfifo_wr.v

From 16ee1336c3a6fb377a29935239fd5f89d626966a Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 15 Sep 2016 11:41:06 +0300
Subject: [PATCH 484/972] Makefile: Update make files

---
 library/Makefile                    |  8 ++++----
 projects/adrv9371x/a10gx/Makefile   | 21 +++++++++++++++++++++
 projects/adrv9371x/a10soc/Makefile  | 10 ++++++++++
 projects/adrv9371x/zc706/Makefile   |  6 +++---
 projects/arradio/c5soc/Makefile     |  7 +++++++
 projects/daq1/zc706/Makefile        |  6 +++---
 projects/daq2/a10gx/Makefile        | 16 ++++++++++++----
 projects/daq2/zc706/Makefile        |  6 +++---
 projects/daq3/a10gx/Makefile        | 17 +++++++++++++++++
 projects/daq3/zc706/Makefile        |  6 +++---
 projects/fmcadc2/zc706/Makefile     |  6 +++---
 projects/fmcadc4/zc706/Makefile     |  6 +++---
 projects/fmcjesdadc1/a5gt/Makefile  |  9 +++++++++
 projects/fmcjesdadc1/a5soc/Makefile |  7 +++++++
 projects/fmcomms11/zc706/Makefile   |  6 +++---
 projects/fmcomms2/a10gx/Makefile    | 11 +++++++++++
 projects/fmcomms7/zc706/Makefile    |  6 +++---
 projects/usdrx1/a5gt/Makefile       |  8 ++++++++
 projects/usdrx1/zc706/Makefile      |  6 +++---
 19 files changed, 133 insertions(+), 35 deletions(-)

diff --git a/library/Makefile b/library/Makefile
index 58ebfc6c1..0ab77fac5 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -30,9 +30,7 @@ clean:
 	make -C axi_ad9680 clean
 	make -C axi_ad9684 clean
 	make -C axi_ad9739a clean
-	make -C axi_adcfifo clean
 	make -C axi_clkgen clean
-	make -C axi_dacfifo clean
 	make -C axi_dmac clean
 	make -C axi_generic_adc clean
 	make -C axi_gpreg clean
@@ -73,7 +71,9 @@ clean:
 	make -C util_tdd_sync clean
 	make -C util_upack clean
 	make -C util_wfifo clean
+	make -C xilinx/axi_adcfifo clean
 	make -C xilinx/axi_adxcvr clean
+	make -C xilinx/axi_dacfifo clean
 	make -C xilinx/util_adxcvr clean
 
 
@@ -101,9 +101,7 @@ lib:
 	-make -C axi_ad9680
 	-make -C axi_ad9684
 	-make -C axi_ad9739a
-	-make -C axi_adcfifo
 	-make -C axi_clkgen
-	-make -C axi_dacfifo
 	-make -C axi_dmac
 	-make -C axi_generic_adc
 	-make -C axi_gpreg
@@ -144,7 +142,9 @@ lib:
 	-make -C util_tdd_sync
 	-make -C util_upack
 	-make -C util_wfifo
+	-make -C xilinx/axi_adcfifo
 	-make -C xilinx/axi_adxcvr
+	-make -C xilinx/axi_dacfifo
 	-make -C xilinx/util_adxcvr
 
 ####################################################################################
diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile
index d35c8155c..67daaba73 100644
--- a/projects/adrv9371x/a10gx/Makefile
+++ b/projects/adrv9371x/a10gx/Makefile
@@ -21,6 +21,23 @@ M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
+M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
+M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
+M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
+M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
+M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
+M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
+M_DEPS += ../../../library/altera_iopll/altera_iopll_hw.tcl
+M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
+M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
+M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
+M_DEPS += ../../../library/altera_pll_reconfig/altera_pll_reconfig_hw.tcl
+M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
+M_DEPS += ../../../library/altera_xcvr_atx_pll_a10/altera_xcvr_atx_pll_a10_hw.tcl
+M_DEPS += ../../../library/altera_xcvr_reset_control/altera_xcvr_reset_control_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v
@@ -68,6 +85,10 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 74abe24c5..29443506c 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -21,6 +21,16 @@ M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera_arria10_hps/altera_arria10_hps_hw.tcl
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
+M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
+M_DEPS += ../../../library/altera_emif_a10_hps/altera_emif_a10_hps_hw.tcl
+M_DEPS += ../../../library/altera_iopll/altera_iopll_hw.tcl
+M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
+M_DEPS += ../../../library/altera_pll_reconfig/altera_pll_reconfig_hw.tcl
+M_DEPS += ../../../library/altera_xcvr_atx_pll_a10/altera_xcvr_atx_pll_a10_hw.tcl
+M_DEPS += ../../../library/altera_xcvr_reset_control/altera_xcvr_reset_control_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v
diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
index e47ee3670..31f8999fe 100644
--- a/projects/adrv9371x/zc706/Makefile
+++ b/projects/adrv9371x/zc706/Makefile
@@ -21,7 +21,7 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dacfifo/axi_dacfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
@@ -60,7 +60,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9371 clean
 	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dacfifo clean
+	make -C ../../../library/xilinx/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_jesd_gt clean
@@ -79,7 +79,7 @@ adrv9371x_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9371
 	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dacfifo
+	make -C ../../../library/xilinx/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_jesd_gt
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 165776141..78da3a934 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -27,6 +27,13 @@ M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
 M_DEPS += ../../../library/altera/common/ad_lvds_in.v
 M_DEPS += ../../../library/altera/common/ad_lvds_out.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
+M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
+M_DEPS += ../../../library/altera_hps/altera_hps_hw.tcl
+M_DEPS += ../../../library/altera_irq_bridge/altera_irq_bridge_hw.tcl
+M_DEPS += ../../../library/altera_pll/altera_pll_hw.tcl
+M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile
index 26a7a7ca0..16bd8a371 100644
--- a/projects/daq1/zc706/Makefile
+++ b/projects/daq1/zc706/Makefile
@@ -22,7 +22,7 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684.xpr
-M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -59,7 +59,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9122 clean
 	make -C ../../../library/axi_ad9684 clean
-	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
@@ -76,7 +76,7 @@ daq1_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9122
 	make -C ../../../library/axi_ad9684
-	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index 96cd875de..53b4fffc6 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -21,6 +21,17 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
+M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
+M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
+M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
+M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
+M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
+M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
+M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
+M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
@@ -31,6 +42,7 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
+M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr_hw.tcl
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
@@ -50,13 +62,10 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
-M_DEPS += ../../../library/common/ad_jesd_align.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
@@ -69,7 +78,6 @@ M_DEPS += ../../../library/common/up_clock_mon.v
 M_DEPS += ../../../library/common/up_dac_channel.v
 M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
 M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile
index b079f8b90..2f5448e0e 100644
--- a/projects/daq2/zc706/Makefile
+++ b/projects/daq2/zc706/Makefile
@@ -23,7 +23,7 @@ M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
-M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -63,7 +63,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
-	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adcfifo clean
 	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
@@ -83,7 +83,7 @@ daq2_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
-	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adcfifo
 	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index 190c0bc8c..368afc7da 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -21,6 +21,23 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
+M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
+M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
+M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
+M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
+M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
+M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
+M_DEPS += ../../../library/altera_iopll/altera_iopll_hw.tcl
+M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
+M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
+M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
+M_DEPS += ../../../library/altera_pll_reconfig/altera_pll_reconfig_hw.tcl
+M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
+M_DEPS += ../../../library/altera_xcvr_atx_pll_a10/altera_xcvr_atx_pll_a10_hw.tcl
+M_DEPS += ../../../library/altera_xcvr_reset_control/altera_xcvr_reset_control_hw.tcl
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_core.v
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index 0de7f04db..052ed222b 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -23,7 +23,7 @@ M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
-M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -64,7 +64,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9152 clean
 	make -C ../../../library/axi_ad9680 clean
-	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
@@ -85,7 +85,7 @@ daq3_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9152
 	make -C ../../../library/axi_ad9680
-	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 74b389f1e..6323ddb91 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -21,7 +21,7 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
-M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -57,7 +57,7 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9625 clean
-	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
@@ -73,7 +73,7 @@ fmcadc2_zc706.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9625
-	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index fbcd95760..e939d348d 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -21,7 +21,7 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
-M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -60,7 +60,7 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
-	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
@@ -79,7 +79,7 @@ fmcadc4_zc706.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9680
-	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index 9f80abb77..6de430a93 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -20,6 +20,15 @@ M_DEPS += ../common/fmcjesdadc1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
+M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
+M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
+M_DEPS += ../../../library/altera_irq_bridge/altera_irq_bridge_hw.tcl
+M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
+M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
+M_DEPS += ../../../library/altera_pll/altera_pll_hw.tcl
+M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 99701e708..d60b5f51e 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -20,6 +20,13 @@ M_DEPS += ../common/fmcjesdadc1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5soc/a5soc_system_bd.qsys
 M_DEPS += ../../common/a5soc/a5soc_system_assign.tcl
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
+M_DEPS += ../../../library/altera_hps/altera_hps_hw.tcl
+M_DEPS += ../../../library/altera_irq_bridge/altera_irq_bridge_hw.tcl
+M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
+M_DEPS += ../../../library/altera_pll/altera_pll_hw.tcl
+M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index befa85363..6ac361e20 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -23,7 +23,7 @@ M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9162/axi_ad9162.xpr
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
-M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -61,7 +61,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9162 clean
 	make -C ../../../library/axi_ad9625 clean
-	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
@@ -79,7 +79,7 @@ fmcomms11_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9162
 	make -C ../../../library/axi_ad9625
-	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 9ce6cb4a7..29c327f15 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -27,6 +27,17 @@ M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
 M_DEPS += ../../../library/altera/common/ad_lvds_in.v
 M_DEPS += ../../../library/altera/common/ad_lvds_out.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
+M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
+M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
+M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
+M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
+M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
+M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
+M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
+M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index f3fba2e0a..9343fc02c 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -23,7 +23,7 @@ M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
-M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -63,7 +63,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
-	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
@@ -83,7 +83,7 @@ fmcomms7_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
-	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index 8850eed3e..7615b7656 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -18,6 +18,14 @@ M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
 M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v
 M_DEPS += ../../../library/common/altera/ad_jesd_align.v
+M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
+M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
+M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
+M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
+M_DEPS += ../../../library/altera_irq_bridge/altera_irq_bridge_hw.tcl
+M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
+M_DEPS += ../../../library/altera_pll/altera_pll_hw.tcl
+M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index cb594bbe8..c29b78937 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -20,7 +20,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr
-M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -56,7 +56,7 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9671 clean
-	make -C ../../../library/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adcfifo clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
@@ -72,7 +72,7 @@ usdrx1_zc706.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9671
-	make -C ../../../library/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adcfifo
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx

From 5986f45cba530ac2539b3ae402584822dc3d6655 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 15 Sep 2016 09:38:11 -0400
Subject: [PATCH 485/972] altera/ad_serdes_out- updates

---
 library/altera/common/ad_serdes_out.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index e0e98d3ee..bdb5f3eb4 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -38,7 +38,12 @@
 
 `timescale 1ps/1ps
 
-module ad_serdes_out (
+module ad_serdes_out #(
+
+  // parameters
+
+  parameter   DEVICE_TYPE = 0,
+  parameter   DATA_WIDTH = 16) (
 
   // reset and clocks
 
@@ -60,11 +65,6 @@ module ad_serdes_out (
   output  [(DATA_WIDTH-1):0]  data_out_p,
   output  [(DATA_WIDTH-1):0]  data_out_n);
 
-  // parameters
-
-  parameter   DEVICE_TYPE = 0;
-  parameter   DATA_WIDTH = 16;
-
   // internal signals
 
   wire    [(DATA_WIDTH-1):0]  data_out_s;

From 02dfd2d2e2ea99e0db3d3315ccf950f79d35637c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 15 Sep 2016 10:28:34 -0400
Subject: [PATCH 486/972] altera/ad_serdes_out- sample transmit order

---
 library/altera/common/ad_serdes_out.v | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index bdb5f3eb4..fe464baea 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -84,14 +84,14 @@ module ad_serdes_out #(
     .div_clk_export (div_clk),
     .loaden_export (loaden),
     .data_out_export (data_out_p[l_inst]),
-    .data_s_export ({ data_s7[l_inst],
-                      data_s6[l_inst],
-                      data_s5[l_inst],
-                      data_s4[l_inst],
-                      data_s3[l_inst],
-                      data_s2[l_inst],
+    .data_s_export ({ data_s0[l_inst],
                       data_s1[l_inst],
-                      data_s0[l_inst]}));
+                      data_s2[l_inst],
+                      data_s3[l_inst],
+                      data_s4[l_inst],
+                      data_s5[l_inst],
+                      data_s6[l_inst],
+                      data_s7[l_inst]}));
   end
   endgenerate
 

From 63696c1a28ebffb21c330c02d6864f4c9e1668e9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 15 Sep 2016 11:12:18 -0400
Subject: [PATCH 487/972] alt_serdes- data-width parameter

---
 library/altera/common/ad_serdes_in.v  | 107 ++++++++++++++------------
 library/altera/common/ad_serdes_out.v |   5 --
 2 files changed, 59 insertions(+), 53 deletions(-)

diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 545051797..2235e7f37 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -38,69 +38,80 @@
 
 `timescale 1ps/1ps
 
-module ad_serdes_in (
-
-  // reset and clocks
-
-  input           rst,
-  input           clk,
-  input           div_clk,
-  input           loaden,
-  input           hs_phase,
-  input           locked,
-
-  // data interface
-
-  output          data_s0,
-  output          data_s1,
-  output          data_s2,
-  output          data_s3,
-  output          data_s4,
-  output          data_s5,
-  output          data_s6,
-  output          data_s7,
-  input           data_in_p,
-  input           data_in_n,
-
-  // delay-data interface
-
-  input           up_clk,
-  input           up_dld,
-  input    [ 4:0] up_dwdata,
-  output   [ 4:0] up_drdata,
-
-  // delay-control interface
-
-  input           delay_clk,
-  input           delay_rst,
-  output          delay_locked);
+module ad_serdes_in #(
 
   // parameters
 
-  parameter       DEVICE_TYPE  = 0;
+  parameter   DEVICE_TYPE = 0,
+  parameter   DATA_WIDTH = 16) (
+
+  // reset and clocks
+
+  input                       rst,
+  input                       clk,
+  input                       div_clk,
+  input                       loaden,
+  input   [ 7:0]              phase,
+  input                       locked,
+
+  // data interface
+
+  output  [(DATA_WIDTH-1):0]  data_s0,
+  output  [(DATA_WIDTH-1):0]  data_s1,
+  output  [(DATA_WIDTH-1):0]  data_s2,
+  output  [(DATA_WIDTH-1):0]  data_s3,
+  output  [(DATA_WIDTH-1):0]  data_s4,
+  output  [(DATA_WIDTH-1):0]  data_s5,
+  output  [(DATA_WIDTH-1):0]  data_s6,
+  output  [(DATA_WIDTH-1):0]  data_s7,
+  input   [(DATA_WIDTH-1):0]  data_in_p,
+  input   [(DATA_WIDTH-1):0]  data_in_n,
+
+  // delay-data interface
+
+  input                       up_clk,
+  input                       up_dld,
+  input   [ 4:0]              up_dwdata,
+  output  [ 4:0]              up_drdata,
+
+  // delay-control interface
+
+  input                       delay_clk,
+  input                       delay_rst,
+  output                      delay_locked);
+
+  // internal signals
+
+  wire    [(DATA_WIDTH-1):0]  delay_locked_s;
 
   // assignments
 
   assign up_drdata = 5'd0;
+  assign delay_locked = & delay_locked_s;
 
   // instantiations
 
+  genvar l_inst;
+  generate
+  for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
   alt_serdes_in_core i_core (
     .clk_export (clk),
     .div_clk_export (div_clk),
-    .hs_phase_export (hs_phase),
+    .hs_phase_export (phase),
     .loaden_export (loaden),
     .locked_export (locked),
-    .data_in_export (data_in_p),
-    .data_s_export ({ data_s7,
-                      data_s6,
-                      data_s5,
-                      data_s4,
-                      data_s3,
-                      data_s2,
-                      data_s1,
-                      data_s0}),
-    .delay_locked_export (delay_locked));
+    .data_in_export (data_in_p[l_inst]),
+    .data_s_export ({ data_s0[l_inst],
+                      data_s1[l_inst],
+                      data_s2[l_inst],
+                      data_s3[l_inst],
+                      data_s4[l_inst],
+                      data_s5[l_inst],
+                      data_s6[l_inst],
+                      data_s7[l_inst]}),
+    .delay_locked_export (delay_locked_s[l_inst]));
+  end
+  endgenerate
 
 endmodule
 
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index fe464baea..159a9dbb4 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -65,11 +65,6 @@ module ad_serdes_out #(
   output  [(DATA_WIDTH-1):0]  data_out_p,
   output  [(DATA_WIDTH-1):0]  data_out_n);
 
-  // internal signals
-
-  wire    [(DATA_WIDTH-1):0]  data_out_s;
-  wire    [ 7:0]              data_in_s[(DATA_WIDTH-1):0];
-
   // defaults
 
   assign data_out_n = 'd0;

From 67d4e71ff0bff92f04541d5a72313170b13b9210 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 15 Sep 2016 12:41:24 -0400
Subject: [PATCH 488/972] pzsdr1- disable gpreg constraints

---
 projects/pzsdr1/ccbrk/system_project.tcl | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/projects/pzsdr1/ccbrk/system_project.tcl b/projects/pzsdr1/ccbrk/system_project.tcl
index 046012886..21967b370 100644
--- a/projects/pzsdr1/ccbrk/system_project.tcl
+++ b/projects/pzsdr1/ccbrk/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl 
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
@@ -13,6 +11,7 @@ adi_project_files ccbrk_pzsdr1 [list \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run ccbrk_pzsdr1
 
 

From a2d15acb8947d4c7f79d1343e43206307bdbfd94 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 15 Sep 2016 13:33:55 -0400
Subject: [PATCH 489/972] ad_serdes- altera/xilinx sync

---
 library/altera/common/ad_serdes_in.v  |  48 +--
 library/xilinx/common/ad_serdes_clk.v |  76 ++--
 library/xilinx/common/ad_serdes_in.v  | 558 +++++++++++---------------
 library/xilinx/common/ad_serdes_out.v |  96 ++---
 4 files changed, 322 insertions(+), 456 deletions(-)

diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 2235e7f37..0e091afc8 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -47,42 +47,42 @@ module ad_serdes_in #(
 
   // reset and clocks
 
-  input                       rst,
-  input                       clk,
-  input                       div_clk,
-  input                       loaden,
-  input   [ 7:0]              phase,
-  input                       locked,
+  input                           rst,
+  input                           clk,
+  input                           div_clk,
+  input                           loaden,
+  input   [ 7:0]                  phase,
+  input                           locked,
 
   // data interface
 
-  output  [(DATA_WIDTH-1):0]  data_s0,
-  output  [(DATA_WIDTH-1):0]  data_s1,
-  output  [(DATA_WIDTH-1):0]  data_s2,
-  output  [(DATA_WIDTH-1):0]  data_s3,
-  output  [(DATA_WIDTH-1):0]  data_s4,
-  output  [(DATA_WIDTH-1):0]  data_s5,
-  output  [(DATA_WIDTH-1):0]  data_s6,
-  output  [(DATA_WIDTH-1):0]  data_s7,
-  input   [(DATA_WIDTH-1):0]  data_in_p,
-  input   [(DATA_WIDTH-1):0]  data_in_n,
+  output  [(DATA_WIDTH-1):0]      data_s0,
+  output  [(DATA_WIDTH-1):0]      data_s1,
+  output  [(DATA_WIDTH-1):0]      data_s2,
+  output  [(DATA_WIDTH-1):0]      data_s3,
+  output  [(DATA_WIDTH-1):0]      data_s4,
+  output  [(DATA_WIDTH-1):0]      data_s5,
+  output  [(DATA_WIDTH-1):0]      data_s6,
+  output  [(DATA_WIDTH-1):0]      data_s7,
+  input   [(DATA_WIDTH-1):0]      data_in_p,
+  input   [(DATA_WIDTH-1):0]      data_in_n,
 
   // delay-data interface
 
-  input                       up_clk,
-  input                       up_dld,
-  input   [ 4:0]              up_dwdata,
-  output  [ 4:0]              up_drdata,
+  input                           up_clk;
+  input   [(DATA_WIDTH-1):0]      up_dld;
+  input   [((DATA_WIDTH*5)-1):0]  up_dwdata;
+  output  [((DATA_WIDTH*5)-1):0]  up_drdata;
 
   // delay-control interface
 
-  input                       delay_clk,
-  input                       delay_rst,
-  output                      delay_locked);
+  input                           delay_clk,
+  input                           delay_rst,
+  output                          delay_locked);
 
   // internal signals
 
-  wire    [(DATA_WIDTH-1):0]  delay_locked_s;
+  wire    [(DATA_WIDTH-1):0]      delay_locked_s;
 
   // assignments
 
diff --git a/library/xilinx/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v
index bbcd0c8ef..5c647de1d 100644
--- a/library/xilinx/common/ad_serdes_clk.v
+++ b/library/xilinx/common/ad_serdes_clk.v
@@ -34,54 +34,35 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// serial data output interface: serdes(x8) or oddr(x2) output module
+// serial data output interface: serdes(x8)
 
 `timescale 1ps/1ps
 
-module ad_serdes_clk (
-
-  // clock and divided clock
-
-  mmcm_rst,
-  clk_in_p,
-  clk_in_n,
-
-  clk,
-  div_clk,
-  out_clk,
-
-  // drp interface
-
-  up_clk,
-  up_rstn,
-  up_drp_sel,
-  up_drp_wr,
-  up_drp_addr,
-  up_drp_wdata,
-  up_drp_rdata,
-  up_drp_ready,
-  up_drp_locked);
+module ad_serdes_clk #(
 
   // parameters
 
-  parameter   SERDES_OR_DDR_N = 1;
-  parameter   MMCM_OR_BUFR_N = 1;
-  parameter   MMCM_DEVICE_TYPE = 0;
-  parameter   MMCM_CLKIN_PERIOD  = 1.667;
-  parameter   MMCM_VCO_DIV  = 6;
-  parameter   MMCM_VCO_MUL = 12.000;
-  parameter   MMCM_CLK0_DIV = 2.000;
-  parameter   MMCM_CLK1_DIV = 6;
+  parameter   DDR_OR_SDR_N = 1,
+  parameter   SERDES_FACTOR = 8,
+  parameter   MMCM_OR_BUFR_N = 1,
+  parameter   MMCM_DEVICE_TYPE = 0,
+  parameter   MMCM_CLKIN_PERIOD  = 1.667,
+  parameter   MMCM_VCO_DIV  = 6,
+  parameter   MMCM_VCO_MUL = 12.000,
+  parameter   MMCM_CLK0_DIV = 2.000,
+  parameter   MMCM_CLK1_DIV = 6) (
 
   // clock and divided clock
 
-  input           mmcm_rst;
+  input           rst;
   input           clk_in_p;
   input           clk_in_n;
 
   output          clk;
   output          div_clk;
   output          out_clk;
+  output          loaden;
+  output  [ 7:0]  phase,
 
   // drp interface
 
@@ -90,8 +71,8 @@ module ad_serdes_clk (
   input           up_drp_sel;
   input           up_drp_wr;
   input   [11:0]  up_drp_addr;
-  input   [15:0]  up_drp_wdata;
-  output  [15:0]  up_drp_rdata;
+  input   [31:0]  up_drp_wdata;
+  output  [31:0]  up_drp_rdata;
   output          up_drp_ready;
   output          up_drp_locked;
 
@@ -99,6 +80,12 @@ module ad_serdes_clk (
 
   wire            clk_in_s;
 
+  // defaults
+
+  assign loaden = 'd0;
+  assign phase = 'd0;
+  assign up_drp_rdata[31:16] = 'd0;
+
   // instantiations
 
   IBUFGDS i_clk_in_ibuf (
@@ -124,7 +111,7 @@ module ad_serdes_clk (
     .clk (clk_in_s),
     .clk2 (1'b0),
     .clk_sel (1'b1),
-    .mmcm_rst (mmcm_rst),
+    .mmcm_rst (rst),
     .mmcm_clk_0 (clk),
     .mmcm_clk_1 (div_clk),
     .mmcm_clk_2 (out_clk),
@@ -133,24 +120,13 @@ module ad_serdes_clk (
     .up_drp_sel (up_drp_sel),
     .up_drp_wr (up_drp_wr),
     .up_drp_addr (up_drp_addr),
-    .up_drp_wdata (up_drp_wdata),
-    .up_drp_rdata (up_drp_rdata),
+    .up_drp_wdata (up_drp_wdata[15:0]),
+    .up_drp_rdata (up_drp_rdata[15:0]),
     .up_drp_ready (up_drp_ready),
     .up_drp_locked (up_drp_locked));
   end
 
-  if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 0)) begin
-  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf (
-    .CLR (1'b0),
-    .CE (1'b1),
-    .I (clk_in_s),
-    .O (clk));
-
-  assign div_clk = clk;
-  assign out_clk = clk;
-  end
-
-  if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 1)) begin
+  if (MMCM_OR_BUFR_N == 0) begin
   BUFIO i_clk_buf (
     .I (clk_in_s),
     .O (clk));
diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v
index b4d8f0d36..748b070b8 100644
--- a/library/xilinx/common/ad_serdes_in.v
+++ b/library/xilinx/common/ad_serdes_in.v
@@ -35,96 +35,67 @@
 // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
+
 `timescale 1ps/1ps
 
-module ad_serdes_in (
-
-  // reset and clocks
-
-  rst,
-  clk,
-  div_clk,
-
-  // data interface
-
-  data_s0,
-  data_s1,
-  data_s2,
-  data_s3,
-  data_s4,
-  data_s5,
-  data_s6,
-  data_s7,
-  data_in_p,
-  data_in_n,
-
-  // delay-data interface
-
-  up_clk,
-  up_dld,
-  up_dwdata,
-  up_drdata,
-
-  // delay-control interface
-
-  delay_clk,
-  delay_rst,
-  delay_locked);
+module ad_serdes_in #(
 
   // parameters
 
-  parameter   DEVICE_TYPE     = 0;
-  parameter   IODELAY_CTRL    = 0;
-  parameter   IODELAY_GROUP   = "dev_if_delay_group";
-  // SDR = 0 / DDR = 1
-  parameter   DDR_OR_SDR_N         = 0;
-  // serialization factor
-  parameter   DATA_WIDTH  = 8;
-
-  localparam  DEVICE_6SERIES  = 1;
-  localparam  DEVICE_7SERIES  = 0;
-  localparam  SDR             = 0;
-  localparam  DDR             = 1;
+  parameter   DEVICE_TYPE = 0,
+  parameter   DDR_OR_SDR_N = 0,
+  parameter   SERDES_FACTOR = 8,
+  parameter   DATA_WIDTH = 16,
+  parameter   IODELAY_CTRL = 0,
+  parameter   IODELAY_GROUP = "dev_if_delay_group") (
 
   // reset and clocks
 
-  input           rst;
-  input           clk;
-  input           div_clk;
+  input                           rst;
+  input                           clk;
+  input                           div_clk;
+  input                           loaden,
+  input   [ 7:0]                  phase,
+  input                           locked,
 
   // data interface
 
-  output          data_s0;
-  output          data_s1;
-  output          data_s2;
-  output          data_s3;
-  output          data_s4;
-  output          data_s5;
-  output          data_s6;
-  output          data_s7;
-  input           data_in_p;
-  input           data_in_n;
+  output  [(DATA_WIDTH-1):0]      data_s0;
+  output  [(DATA_WIDTH-1):0]      data_s1;
+  output  [(DATA_WIDTH-1):0]      data_s2;
+  output  [(DATA_WIDTH-1):0]      data_s3;
+  output  [(DATA_WIDTH-1):0]      data_s4;
+  output  [(DATA_WIDTH-1):0]      data_s5;
+  output  [(DATA_WIDTH-1):0]      data_s6;
+  output  [(DATA_WIDTH-1):0]      data_s7;
+  input   [(DATA_WIDTH-1):0]      data_in_p;
+  input   [(DATA_WIDTH-1):0]      data_in_n;
 
   // delay-data interface
 
-  input           up_clk;
-  input           up_dld;
-  input    [ 4:0] up_dwdata;
-  output   [ 4:0] up_drdata;
+  input                           up_clk;
+  input   [(DATA_WIDTH-1):0]      up_dld;
+  input   [((DATA_WIDTH*5)-1):0]  up_dwdata;
+  output  [((DATA_WIDTH*5)-1):0]  up_drdata;
 
   // delay-control interface
-  input           delay_clk;
-  input           delay_rst;
-  output          delay_locked;
+
+  input                           delay_clk;
+  input                           delay_rst;
+  output                          delay_locked;
 
   // internal signals
 
-  wire            data_in_ibuf_s;
-  wire            data_in_idelay_s;
-  wire            data_shift1_s;
-  wire            data_shift2_s;
+  wire    [(DATA_WIDTH-1):0]      data_in_ibuf_s;
+  wire    [(DATA_WIDTH-1):0]      data_in_idelay_s;
+  wire    [(DATA_WIDTH-1):0]      data_shift1_s;
+  wire    [(DATA_WIDTH-1):0]      data_shift2_s;
+
+  // parameters
+
+  localparam  DEVICE_6SERIES  = 1;
+  localparam  DEVICE_7SERIES  = 0;
+  localparam  DATA_RATE = (DDR_OR_SDR_N == 1) ? "DDR" : "SDR";
 
   // delay controller
 
@@ -142,257 +113,210 @@ module ad_serdes_in (
 
   // received data interface: ibuf -> idelay -> iserdes
 
+  genvar l_inst;
+  generate
+  for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
+
   IBUFDS i_ibuf (
-    .O(data_in_ibuf_s),
-    .I(data_in_p),
-    .IB(data_in_n)
-  );
+    .I (data_in_p[l_inst]),
+    .IB (data_in_n[l_inst]),
+    .O (data_in_ibuf_s[l_inst]));
 
-  if(DEVICE_TYPE == DEVICE_7SERIES) begin
-    (* IODELAY_GROUP = IODELAY_GROUP *)
-
-    IDELAYE2 #(
-      .CINVCTRL_SEL ("FALSE"),
-      .DELAY_SRC ("IDATAIN"),
-      .HIGH_PERFORMANCE_MODE ("FALSE"),
-      .IDELAY_TYPE ("VAR_LOAD"),
-      .IDELAY_VALUE (0),
-      .REFCLK_FREQUENCY (200.0),
-      .PIPE_SEL ("FALSE"),
-      .SIGNAL_PATTERN ("DATA"))
-    i_rx_data_idelay (
-      .CE (1'b0),
-      .INC (1'b0),
-      .DATAIN (1'b0),
-      .LDPIPEEN (1'b0),
-      .CINVCTRL (1'b0),
-      .REGRST (1'b0),
-      .C (up_clk),
-      .IDATAIN (data_in_ibuf_s),
-      .DATAOUT (data_in_idelay_s),
-      .LD (up_dld),
-      .CNTVALUEIN (up_dwdata),
-      .CNTVALUEOUT (up_drdata));
-
-    // Note: The first sample in time will be data_s7, the last data_s0!
-    if(DDR_OR_SDR_N == SDR) begin
-      ISERDESE2  #(
-        .DATA_RATE("SDR"),
-        .DATA_WIDTH(DATA_WIDTH),
-        .DYN_CLKDIV_INV_EN("FALSE"),
-        .DYN_CLK_INV_EN("FALSE"),
-        .INIT_Q1(1'b0),
-        .INIT_Q2(1'b0),
-        .INIT_Q3(1'b0),
-        .INIT_Q4(1'b0),
-        .INTERFACE_TYPE("NETWORKING"),
-        .IOBDELAY("IFD"),
-        .NUM_CE(2),
-        .OFB_USED("FALSE"),
-        .SERDES_MODE("MASTER"),
-        .SRVAL_Q1(1'b0),
-        .SRVAL_Q2(1'b0),
-        .SRVAL_Q3(1'b0),
-        .SRVAL_Q4(1'b0))
-      ISERDESE2_inst (
-        .O(),
-        .Q1(data_s0),
-        .Q2(data_s1),
-        .Q3(data_s2),
-        .Q4(data_s3),
-        .Q5(data_s4),
-        .Q6(data_s5),
-        .Q7(data_s6),
-        .Q8(data_s7),
-        .SHIFTOUT1(),
-        .SHIFTOUT2(),
-        .BITSLIP(1'b0),
-        .CE1(1'b1),
-        .CE2(1'b1),
-        .CLKDIVP(1'b0),
-        .CLK(clk),
-        .CLKB(~clk),
-        .CLKDIV(div_clk),
-        .OCLK(1'b0),
-        .DYNCLKDIVSEL(1'b0),
-        .DYNCLKSEL(1'b0),
-        .D(1'b0),
-        .DDLY(data_in_idelay_s),
-        .OFB(1'b0),
-        .OCLKB(1'b0),
-        .RST(rst),
-        .SHIFTIN1(1'b0),
-        .SHIFTIN2(1'b0)
-      );
-    end else begin
-
-      ISERDESE2 #(
-        .DATA_RATE("DDR"),
-        .DATA_WIDTH(DATA_WIDTH),
-        .DYN_CLKDIV_INV_EN("FALSE"),
-        .DYN_CLK_INV_EN("FALSE"),
-        .INIT_Q1(1'b0),
-        .INIT_Q2(1'b0),
-        .INIT_Q3(1'b0),
-        .INIT_Q4(1'b0),
-        .INTERFACE_TYPE("NETWORKING"),
-        .IOBDELAY("IFD"),
-        .NUM_CE(2),
-        .OFB_USED("FALSE"),
-        .SERDES_MODE("MASTER"),
-        .SRVAL_Q1(1'b0),
-        .SRVAL_Q2(1'b0),
-        .SRVAL_Q3(1'b0),
-        .SRVAL_Q4(1'b0))
-      ISERDESE2_inst (
-        .O(),
-        .Q1(data_s0),
-        .Q2(data_s1),
-        .Q3(data_s2),
-        .Q4(data_s3),
-        .Q5(data_s4),
-        .Q6(data_s5),
-        .Q7(data_s6),
-        .Q8(data_s7),
-        .SHIFTOUT1(),
-        .SHIFTOUT2(),
-        .BITSLIP(1'b0),
-        .CE1(1'b1),
-        .CE2(1'b1),
-        .CLKDIVP(1'b0),
-        .CLK(clk),
-        .CLKB(~clk),
-        .CLKDIV(div_clk),
-        .OCLK(1'b0),
-        .DYNCLKDIVSEL(1'b0),
-        .DYNCLKSEL(1'b0),
-        .D(1'b0),
-        .DDLY(data_in_idelay_s),
-        .OFB(1'b0),
-        .OCLKB(1'b0),
-        .RST(rst),
-        .SHIFTIN1(1'b0),
-        .SHIFTIN2(1'b0)
-      );
-    end
+  if (DEVICE_TYPE == DEVICE_7SERIES) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYE2 #(
+    .CINVCTRL_SEL ("FALSE"),
+    .DELAY_SRC ("IDATAIN"),
+    .HIGH_PERFORMANCE_MODE ("FALSE"),
+    .IDELAY_TYPE ("VAR_LOAD"),
+    .IDELAY_VALUE (0),
+    .REFCLK_FREQUENCY (200.0),
+    .PIPE_SEL ("FALSE"),
+    .SIGNAL_PATTERN ("DATA"))
+  i_idelay (
+    .CE (1'b0),
+    .INC (1'b0),
+    .DATAIN (1'b0),
+    .LDPIPEEN (1'b0),
+    .CINVCTRL (1'b0),
+    .REGRST (1'b0),
+    .C (up_clk),
+    .IDATAIN (data_in_ibuf_s[l_inst]),
+    .DATAOUT (data_in_idelay_s[l_inst]),
+    .LD (up_dld[l_inst]),
+    .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)),
+    .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)));
+  end
+  if(DEVICE_TYPE == DEVICE_6SERIES) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IODELAYE1 #(
+    .CINVCTRL_SEL ("FALSE"),
+    .DELAY_SRC ("I"),
+    .HIGH_PERFORMANCE_MODE ("TRUE"),
+    .IDELAY_TYPE ("VAR_LOADABLE"),
+    .IDELAY_VALUE (0),
+    .ODELAY_TYPE ("FIXED"),
+    .ODELAY_VALUE (0),
+    .REFCLK_FREQUENCY (200.0),
+    .SIGNAL_PATTERN ("DATA"))
+  i_idelay (
+    .T (1'b1),
+    .CE (1'b0),
+    .INC (1'b0),
+    .CLKIN (1'b0),
+    .DATAIN (1'b0),
+    .ODATAIN (1'b0),
+    .CINVCTRL (1'b0),
+    .C (up_clk),
+    .IDATAIN (data_in_ibuf_s[l_inst]),
+    .DATAOUT (data_in_idelay_s[l_inst]),
+    .RST (up_dld[l_inst]),
+    .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
+    .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
   end
 
-    if(DEVICE_TYPE == DEVICE_6SERIES) begin
-      (* IODELAY_GROUP = IODELAY_GROUP *)
-      IODELAYE1 #(
-        .CINVCTRL_SEL ("FALSE"),
-        .DELAY_SRC ("I"),
-        .HIGH_PERFORMANCE_MODE ("TRUE"),
-        .IDELAY_TYPE ("VAR_LOADABLE"),
-        .IDELAY_VALUE (0),
-        .ODELAY_TYPE ("FIXED"),
-        .ODELAY_VALUE (0),
-        .REFCLK_FREQUENCY (200.0),
-        .SIGNAL_PATTERN ("DATA"))
-      i_rx_data_idelay (
-        .T (1'b1),
-        .CE (1'b0),
-        .INC (1'b0),
-        .CLKIN (1'b0),
-        .DATAIN (1'b0),
-        .ODATAIN (1'b0),
-        .CINVCTRL (1'b0),
-        .C (up_clk),
-        .IDATAIN (data_in_ibuf_s),
-        .DATAOUT (data_in_idelay_s),
-        .RST (up_dld),
-        .CNTVALUEIN (up_dwdata),
-        .CNTVALUEOUT (up_drdata));
+  if (DEVICE_TYPE == DEVICE_7SERIES) begin
+  ISERDESE2  #(
+    .DATA_RATE (DATA_RATE),
+    .DATA_WIDTH (8),
+    .DYN_CLKDIV_INV_EN ("FALSE"),
+    .DYN_CLK_INV_EN ("FALSE"),
+    .INIT_Q1 (1'b0),
+    .INIT_Q2 (1'b0),
+    .INIT_Q3 (1'b0),
+    .INIT_Q4 (1'b0),
+    .INTERFACE_TYPE ("NETWORKING"),
+    .IOBDELAY ("IFD"),
+    .NUM_CE (2),
+    .OFB_USED ("FALSE"),
+    .SERDES_MODE ("MASTER"),
+    .SRVAL_Q1 (1'b0),
+    .SRVAL_Q2 (1'b0),
+    .SRVAL_Q3 (1'b0),
+    .SRVAL_Q4 (1'b0))
+  i_iserdes (
+    .O (),
+    .Q1 (data_s0[l_inst]),
+    .Q2 (data_s1[l_inst]),
+    .Q3 (data_s2[l_inst]),
+    .Q4 (data_s3[l_inst]),
+    .Q5 (data_s4[l_inst]),
+    .Q6 (data_s5[l_inst]),
+    .Q7 (data_s6[l_inst]),
+    .Q8 (data_s7[l_inst]),
+    .SHIFTOUT1 (),
+    .SHIFTOUT2 (),
+    .BITSLIP (1'b0),
+    .CE1 (1'b1),
+    .CE2 (1'b1),
+    .CLKDIVP (1'b0),
+    .CLK (clk),
+    .CLKB (~clk),
+    .CLKDIV (div_clk),
+    .OCLK (1'b0),
+    .DYNCLKDIVSEL (1'b0),
+    .DYNCLKSEL (1'b0),
+    .D (1'b0),
+    .DDLY (data_in_idelay_s[l_inst]),
+    .OFB (1'b0),
+    .OCLKB (1'b0),
+    .RST (rst),
+    .SHIFTIN1 (1'b0),
+    .SHIFTIN2 (1'b0));
+  end
+  if (DEVICE_TYPE == DEVICE_6SERIES) begin
+  ISERDESE1 #(
+    .DATA_RATE (DATA_RATE),
+    .DATA_WIDTH (8),
+    .DYN_CLKDIV_INV_EN ("FALSE"),
+    .DYN_CLK_INV_EN ("FALSE"),
+    .INIT_Q1 (1'b0),
+    .INIT_Q2 (1'b0),
+    .INIT_Q3 (1'b0),
+    .INIT_Q4 (1'b0),
+    .INTERFACE_TYPE ("NETWORKING"),
+    .IOBDELAY ("NONE"),
+    .NUM_CE (1),
+    .OFB_USED ("FALSE"),
+    .SERDES_MODE ("MASTER"),
+    .SRVAL_Q1 (1'b0),
+    .SRVAL_Q2 (1'b0),
+    .SRVAL_Q3 (1'b0),
+    .SRVAL_Q4 (1'b0))
+  i_iserdes_m (
+    .O (),
+    .Q1 (data_s0[l_inst]),
+    .Q2 (data_s1[l_inst]),
+    .Q3 (data_s2[l_inst]),
+    .Q4 (data_s3[l_inst]),
+    .Q5 (data_s4[l_inst]),
+    .Q6 (data_s5[l_inst]),
+    .SHIFTOUT1 (data_shift1_s[l_inst]),
+    .SHIFTOUT2 (data_shift2_s[l_inst]),
+    .BITSLIP (1'b0),
+    .CE1 (1'b1),
+    .CE2 (1'b1),
+    .CLK (clk),
+    .CLKB (~clk),
+    .CLKDIV (div_clk),
+    .OCLK (1'b0),
+    .DYNCLKDIVSEL (1'b0),
+    .DYNCLKSEL (1'b0),
+    .D (1'b0),
+    .DDLY (data_in_idelay_s[l_inst]),
+    .OFB (1'b0),
+    .RST (rst),
+    .SHIFTIN1 (1'b0),
+    .SHIFTIN2 (1'b0));
 
-      ISERDESE1 #(
-        .DATA_RATE("DDR"),
-        .DATA_WIDTH(DATA_WIDTH),
-        .DYN_CLKDIV_INV_EN("FALSE"),
-        .DYN_CLK_INV_EN("FALSE"),
-        .INIT_Q1(1'b0),
-        .INIT_Q2(1'b0),
-        .INIT_Q3(1'b0),
-        .INIT_Q4(1'b0),
-        .INTERFACE_TYPE("NETWORKING"),
-        .IOBDELAY("NONE"),
-        .NUM_CE(1),
-        .OFB_USED("FALSE"),
-        .SERDES_MODE("MASTER"),
-        .SRVAL_Q1(1'b0),
-        .SRVAL_Q2(1'b0),
-        .SRVAL_Q3(1'b0),
-        .SRVAL_Q4(1'b0))
-      i_serdes_m (
-        .O(),
-        .Q1(data_s0),
-        .Q2(data_s1),
-        .Q3(data_s2),
-        .Q4(data_s3),
-        .Q5(data_s4),
-        .Q6(data_s5),
-        .SHIFTOUT1(data_shift1_s),
-        .SHIFTOUT2(data_shift2_s),
-        .BITSLIP(1'b0),
-        .CE1(1'b1),
-        .CE2(1'b1),
-        .CLK(clk),
-        .CLKB(1'b0),
-        .CLKDIV(div_clk),
-        .OCLK(1'b0),
-        .DYNCLKDIVSEL(1'b0),
-        .DYNCLKSEL(1'b0),
-        .D(data_in_idelay_s),
-        .DDLY(1'b0),
-        .OFB(1'b0),
-        .RST(rst),
-        .SHIFTIN1(1'b0),
-        .SHIFTIN2(1'b0)
-      );
-
-      ISERDESE1 #(
-        .DATA_RATE("DDR"),
-        .DATA_WIDTH(DATA_WIDTH),
-        .DYN_CLKDIV_INV_EN("FALSE"),
-        .DYN_CLK_INV_EN("FALSE"),
-        .INIT_Q1(1'b0),
-        .INIT_Q2(1'b0),
-        .INIT_Q3(1'b0),
-        .INIT_Q4(1'b0),
-        .INTERFACE_TYPE("NETWORKING"),
-        .IOBDELAY("NONE"),
-        .NUM_CE(1),
-        .OFB_USED("FALSE"),
-        .SERDES_MODE("SLAVE"),
-        .SRVAL_Q1(1'b0),
-        .SRVAL_Q2(1'b0),
-        .SRVAL_Q3(1'b0),
-        .SRVAL_Q4(1'b0))
-      i_serdes_s (
-        .O(),
-        .Q1(),
-        .Q2(),
-        .Q3(data_s6),
-        .Q4(data_s7),
-        .Q5(),
-        .Q6(),
-        .SHIFTOUT1(),
-        .SHIFTOUT2(),
-        .BITSLIP(1'b0),
-        .CE1(1'b1),
-        .CE2(1'b1),
-        .CLK(clk),
-        .CLKB(1'b0),
-        .CLKDIV(div_clk),
-        .OCLK(1'b0),
-        .DYNCLKDIVSEL(1'b0),
-        .DYNCLKSEL(1'b0),
-        .D(1'b0),
-        .DDLY(1'b0),
-        .OFB(1'b0),
-        .RST(rst),
-        .SHIFTIN1(data_shift1_s),
-        .SHIFTIN2(data_shift2_s));
-      end
+  ISERDESE1 #(
+    .DATA_RATE (DATA_RATE),
+    .DATA_WIDTH (8),
+    .DYN_CLKDIV_INV_EN ("FALSE"),
+    .DYN_CLK_INV_EN ("FALSE"),
+    .INIT_Q1 (1'b0),
+    .INIT_Q2 (1'b0),
+    .INIT_Q3 (1'b0),
+    .INIT_Q4 (1'b0),
+    .INTERFACE_TYPE ("NETWORKING"),
+    .IOBDELAY ("NONE"),
+    .NUM_CE (1),
+    .OFB_USED ("FALSE"),
+    .SERDES_MODE ("SLAVE"),
+    .SRVAL_Q1 (1'b0),
+    .SRVAL_Q2 (1'b0),
+    .SRVAL_Q3 (1'b0),
+    .SRVAL_Q4 (1'b0))
+  i_iserdes_s (
+    .O (),
+    .Q1 (),
+    .Q2 (),
+    .Q3 (data_s6[l_inst]),
+    .Q4 (data_s7[l_inst]),
+    .Q5 (),
+    .Q6 (),
+    .SHIFTOUT1 (),
+    .SHIFTOUT2 (),
+    .BITSLIP (1'b0),
+    .CE1 (1'b1),
+    .CE2 (1'b1),
+    .CLK (clk),
+    .CLKB (~clk),
+    .CLKDIV (div_clk),
+    .OCLK (1'b0),
+    .DYNCLKDIVSEL (1'b0),
+    .DYNCLKSEL (1'b0),
+    .D (1'b0),
+    .DDLY (data_in_idelay_s[l_inst]),
+    .OFB (1'b0),
+    .RST (rst),
+    .SHIFTIN1 (data_shift1_s[l_inst]),
+    .SHIFTIN2 (data_shift2_s[l_inst]));
+  end
+  end
+  endgenerate
 
 endmodule
 
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v
index 334785720..dabb6fd86 100644
--- a/library/xilinx/common/ad_serdes_out.v
+++ b/library/xilinx/common/ad_serdes_out.v
@@ -34,91 +34,57 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// serial data output interface: serdes(x8) or oddr(x2) output module
+// serial data output interface: serdes(x8)
 
 `timescale 1ps/1ps
 
-module ad_serdes_out (
-
-  // reset and clocks
-
-  rst,
-  clk,
-  div_clk,
-
-  // data interface
-
-  data_s0,
-  data_s1,
-  data_s2,
-  data_s3,
-  data_s4,
-  data_s5,
-  data_s6,
-  data_s7,
-  data_out_p,
-  data_out_n);
+module ad_serdes_out #(
 
   // parameters
 
-  parameter   DEVICE_TYPE = 0;
-  parameter   SERDES_OR_DDR_N = 1;
-  parameter   DATA_WIDTH = 16;
-
-
-  localparam  DEVICE_6SERIES = 1;
-  localparam  DEVICE_7SERIES = 0;
-  localparam  DW = DATA_WIDTH - 1;
+  parameter   DEVICE_TYPE = 0,
+  parameter   DDR_OR_SDR_N = 1,
+  parameter   SERDES_FACTOR = 8,
+  parameter   DATA_WIDTH = 16) (
 
   // reset and clocks
 
-  input           rst;
-  input           clk;
-  input           div_clk;
+  input                       rst;
+  input                       clk;
+  input                       div_clk;
+  input                       loaden;
 
   // data interface
 
-  input   [DW:0]  data_s0;
-  input   [DW:0]  data_s1;
-  input   [DW:0]  data_s2;
-  input   [DW:0]  data_s3;
-  input   [DW:0]  data_s4;
-  input   [DW:0]  data_s5;
-  input   [DW:0]  data_s6;
-  input   [DW:0]  data_s7;
-  output  [DW:0]  data_out_p;
-  output  [DW:0]  data_out_n;
+  input   [(DATA_WIDTH-1):0]  data_s0;
+  input   [(DATA_WIDTH-1):0]  data_s1;
+  input   [(DATA_WIDTH-1):0]  data_s2;
+  input   [(DATA_WIDTH-1):0]  data_s3;
+  input   [(DATA_WIDTH-1):0]  data_s4;
+  input   [(DATA_WIDTH-1):0]  data_s5;
+  input   [(DATA_WIDTH-1):0]  data_s6;
+  input   [(DATA_WIDTH-1):0]  data_s7;
+  output  [(DATA_WIDTH-1):0]  data_out_p;
+  output  [(DATA_WIDTH-1):0]  data_out_n;
 
   // internal signals
 
-  wire    [DW:0]  data_out_s;
-  wire    [DW:0]  serdes_shift1_s;
-  wire    [DW:0]  serdes_shift2_s;
+  wire    [(DATA_WIDTH-1):0]  data_out_s;
+  wire    [(DATA_WIDTH-1):0]  serdes_shift1_s;
+  wire    [(DATA_WIDTH-1):0]  serdes_shift2_s;
+
+  // parameters
+
+  localparam  DEVICE_6SERIES = 1;
+  localparam  DEVICE_7SERIES = 0;
 
   // instantiations
 
   genvar l_inst;
   generate
-  for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data
+  for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
 
-  if (SERDES_OR_DDR_N == 0) begin
-  ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_oddr (
-    .S (1'b0),
-    .CE (1'b1),
-    .R (rst),
-    .C (clk),
-    .D1 (data_s0[l_inst]),
-    .D2 (data_s1[l_inst]),
-    .Q (data_out_s[l_inst]));
-  end
-
-  if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin
+  if (DEVICE_TYPE == DEVICE_7SERIES) begin
   OSERDESE2  #(
     .DATA_RATE_OQ ("DDR"),
     .DATA_RATE_TQ ("SDR"),
@@ -155,7 +121,7 @@ module ad_serdes_out (
     .RST (rst));
   end
 
-  if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin
+  if (DEVICE_TYPE == DEVICE_6SERIES) begin
   OSERDESE1  #(
     .DATA_RATE_OQ ("DDR"),
     .DATA_RATE_TQ ("SDR"),

From 2a7bc31c01635f3681cf927177cff1712a7a9aa1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 15 Sep 2016 13:48:49 -0400
Subject: [PATCH 490/972] pzsdr1- disable gpreg constraints

---
 projects/pzsdr1/ccbrk_cmos/system_project.tcl | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/projects/pzsdr1/ccbrk_cmos/system_project.tcl b/projects/pzsdr1/ccbrk_cmos/system_project.tcl
index 45d3a4c8d..4ad543633 100644
--- a/projects/pzsdr1/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr1/ccbrk_cmos/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl 
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
@@ -13,6 +11,7 @@ adi_project_files ccbrk_cmos_pzsdr1 [list \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run ccbrk_cmos_pzsdr1
 
 

From 858ea09048fd6636765de6e78ca8a5f80be4de14 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 16 Sep 2016 10:56:16 +0300
Subject: [PATCH 491/972] altera/ad_serdes_in: Fix some typos

---
 library/altera/common/ad_serdes_in.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 0e091afc8..a84bb0c8c 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -69,10 +69,10 @@ module ad_serdes_in #(
 
   // delay-data interface
 
-  input                           up_clk;
-  input   [(DATA_WIDTH-1):0]      up_dld;
-  input   [((DATA_WIDTH*5)-1):0]  up_dwdata;
-  output  [((DATA_WIDTH*5)-1):0]  up_drdata;
+  input                           up_clk,
+  input   [(DATA_WIDTH-1):0]      up_dld,
+  input   [((DATA_WIDTH*5)-1):0]  up_dwdata,
+  output  [((DATA_WIDTH*5)-1):0]  up_drdata,
 
   // delay-control interface
 

From 13a35f7a2af1830519aa02c66390155123013efb Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri, 16 Sep 2016 14:20:39 +0300
Subject: [PATCH 492/972] altera/ad_serdes_clk: The IO_PLL reset is active
 heigh

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 4 ++--
 library/altera/common/ad_serdes_clk.v       | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index 56fdd9586..3aa7a5374 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -90,8 +90,8 @@ proc p_alt_serdes {} {
     add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
     add_interface drp_clk clock sink
     set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
-    add_interface drp_rstn reset sink
-    set_interface_property drp_rstn EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
+    add_interface drp_rst reset sink
+    set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
     add_interface pll_reconfig avalon slave
     set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
   }
diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
index 75492f68d..6ba9770e4 100644
--- a/library/altera/common/ad_serdes_clk.v
+++ b/library/altera/common/ad_serdes_clk.v
@@ -77,13 +77,14 @@ module ad_serdes_clk (
   reg             up_drp_locked_int = 'd0;
 
   // internal signals
-
+  wire            up_drp_reset;
   wire    [31:0]  up_drp_rdata_int_s;
   wire            up_drp_busy_int_s;
   wire            up_drp_locked_int_s;
 
   // defaults
 
+  assign up_drp_reset = ~up_rstn;
   assign out_clk = div_clk;
   assign up_drp_rdata = up_drp_rdata_int;
   assign up_drp_ready = up_drp_ready_int;
@@ -144,7 +145,7 @@ module ad_serdes_clk (
     .loaden_loaden (loaden),
     .ls_clk_clk (div_clk),
     .drp_clk_clk (up_clk),
-    .drp_rstn_reset (up_rstn),
+    .drp_rst_reset (up_drp_reset),
     .pll_reconfig_waitrequest (up_drp_busy_int_s),
     .pll_reconfig_read (up_drp_rd_int),
     .pll_reconfig_write (up_drp_wr_int),

From 6510f92c12cb3945e0ce2ead91679a0d9275523c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 16 Sep 2016 11:35:29 +0300
Subject: [PATCH 493/972] ad_serdes : Cosmetic changes

---
 library/altera/common/ad_serdes_out.v |  29 ++-
 library/xilinx/common/ad_serdes_clk.v |  63 +++---
 library/xilinx/common/ad_serdes_in.v  |  52 +++--
 library/xilinx/common/ad_serdes_out.v | 276 +++++++++++++-------------
 4 files changed, 204 insertions(+), 216 deletions(-)

diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index 159a9dbb4..c5a9ac648 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -40,8 +40,6 @@
 
 module ad_serdes_out #(
 
-  // parameters
-
   parameter   DEVICE_TYPE = 0,
   parameter   DATA_WIDTH = 16) (
 
@@ -74,19 +72,20 @@ module ad_serdes_out #(
   genvar l_inst;
   generate
   for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
-  alt_serdes_out_core i_core (
-    .clk_export (clk),
-    .div_clk_export (div_clk),
-    .loaden_export (loaden),
-    .data_out_export (data_out_p[l_inst]),
-    .data_s_export ({ data_s0[l_inst],
-                      data_s1[l_inst],
-                      data_s2[l_inst],
-                      data_s3[l_inst],
-                      data_s4[l_inst],
-                      data_s5[l_inst],
-                      data_s6[l_inst],
-                      data_s7[l_inst]}));
+
+    alt_serdes_out_core i_core (
+      .clk_export (clk),
+      .div_clk_export (div_clk),
+      .loaden_export (loaden),
+      .data_out_export (data_out_p[l_inst]),
+      .data_s_export ({ data_s0[l_inst],
+                        data_s1[l_inst],
+                        data_s2[l_inst],
+                        data_s3[l_inst],
+                        data_s4[l_inst],
+                        data_s5[l_inst],
+                        data_s6[l_inst],
+                        data_s7[l_inst]}));
   end
   endgenerate
 
diff --git a/library/xilinx/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v
index 5c647de1d..e3ebad19c 100644
--- a/library/xilinx/common/ad_serdes_clk.v
+++ b/library/xilinx/common/ad_serdes_clk.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -40,41 +40,38 @@
 
 module ad_serdes_clk #(
 
-  // parameters
-
-  parameter   DDR_OR_SDR_N = 1,
-  parameter   SERDES_FACTOR = 8,
-  parameter   MMCM_OR_BUFR_N = 1,
-  parameter   MMCM_DEVICE_TYPE = 0,
-  parameter   MMCM_CLKIN_PERIOD  = 1.667,
-  parameter   MMCM_VCO_DIV  = 6,
-  parameter   MMCM_VCO_MUL = 12.000,
-  parameter   MMCM_CLK0_DIV = 2.000,
-  parameter   MMCM_CLK1_DIV = 6) (
+  parameter       DDR_OR_SDR_N = 1,
+  parameter       SERDES_FACTOR = 8,
+  parameter       MMCM_OR_BUFR_N = 1,
+  parameter       MMCM_DEVICE_TYPE = 0,
+  parameter       MMCM_CLKIN_PERIOD  = 1.667,
+  parameter       MMCM_VCO_DIV  = 6,
+  parameter       MMCM_VCO_MUL = 12.000,
+  parameter       MMCM_CLK0_DIV = 2.000,
+  parameter       MMCM_CLK1_DIV = 6) (
 
   // clock and divided clock
 
-  input           rst;
-  input           clk_in_p;
-  input           clk_in_n;
-
-  output          clk;
-  output          div_clk;
-  output          out_clk;
-  output          loaden;
+  input           rst,
+  input           clk_in_p,
+  input           clk_in_n,
+  output          clk,
+  output          div_clk,
+  output          out_clk,
+  output          loaden,
   output  [ 7:0]  phase,
 
   // drp interface
 
-  input           up_clk;
-  input           up_rstn;
-  input           up_drp_sel;
-  input           up_drp_wr;
-  input   [11:0]  up_drp_addr;
-  input   [31:0]  up_drp_wdata;
-  output  [31:0]  up_drp_rdata;
-  output          up_drp_ready;
-  output          up_drp_locked;
+  input           up_clk,
+  input           up_rstn,
+  input           up_drp_sel,
+  input           up_drp_wr,
+  input   [11:0]  up_drp_addr,
+  input   [31:0]  up_drp_wdata,
+  output  [31:0]  up_drp_rdata,
+  output          up_drp_ready,
+  output          up_drp_locked);
 
   // internal signals
 
diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v
index 748b070b8..af09de886 100644
--- a/library/xilinx/common/ad_serdes_in.v
+++ b/library/xilinx/common/ad_serdes_in.v
@@ -40,8 +40,6 @@
 
 module ad_serdes_in #(
 
-  // parameters
-
   parameter   DEVICE_TYPE = 0,
   parameter   DDR_OR_SDR_N = 0,
   parameter   SERDES_FACTOR = 8,
@@ -51,38 +49,42 @@ module ad_serdes_in #(
 
   // reset and clocks
 
-  input                           rst;
-  input                           clk;
-  input                           div_clk;
+  input                           rst,
+  input                           clk,
+  input                           div_clk,
   input                           loaden,
   input   [ 7:0]                  phase,
   input                           locked,
 
   // data interface
 
-  output  [(DATA_WIDTH-1):0]      data_s0;
-  output  [(DATA_WIDTH-1):0]      data_s1;
-  output  [(DATA_WIDTH-1):0]      data_s2;
-  output  [(DATA_WIDTH-1):0]      data_s3;
-  output  [(DATA_WIDTH-1):0]      data_s4;
-  output  [(DATA_WIDTH-1):0]      data_s5;
-  output  [(DATA_WIDTH-1):0]      data_s6;
-  output  [(DATA_WIDTH-1):0]      data_s7;
-  input   [(DATA_WIDTH-1):0]      data_in_p;
-  input   [(DATA_WIDTH-1):0]      data_in_n;
+  output  [(DATA_WIDTH-1):0]      data_s0,
+  output  [(DATA_WIDTH-1):0]      data_s1,
+  output  [(DATA_WIDTH-1):0]      data_s2,
+  output  [(DATA_WIDTH-1):0]      data_s3,
+  output  [(DATA_WIDTH-1):0]      data_s4,
+  output  [(DATA_WIDTH-1):0]      data_s5,
+  output  [(DATA_WIDTH-1):0]      data_s6,
+  output  [(DATA_WIDTH-1):0]      data_s7,
+  input   [(DATA_WIDTH-1):0]      data_in_p,
+  input   [(DATA_WIDTH-1):0]      data_in_n,
 
   // delay-data interface
 
-  input                           up_clk;
-  input   [(DATA_WIDTH-1):0]      up_dld;
-  input   [((DATA_WIDTH*5)-1):0]  up_dwdata;
-  output  [((DATA_WIDTH*5)-1):0]  up_drdata;
+  input                           up_clk,
+  input   [(DATA_WIDTH-1):0]      up_dld,
+  input   [((DATA_WIDTH*5)-1):0]  up_dwdata,
+  output  [((DATA_WIDTH*5)-1):0]  up_drdata,
 
   // delay-control interface
 
-  input                           delay_clk;
-  input                           delay_rst;
-  output                          delay_locked;
+  input                           delay_clk,
+  input                           delay_rst,
+  output                          delay_locked);
+
+  localparam  DEVICE_6SERIES  = 1;
+  localparam  DEVICE_7SERIES  = 0;
+  localparam  DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR";
 
   // internal signals
 
@@ -91,12 +93,6 @@ module ad_serdes_in #(
   wire    [(DATA_WIDTH-1):0]      data_shift1_s;
   wire    [(DATA_WIDTH-1):0]      data_shift2_s;
 
-  // parameters
-
-  localparam  DEVICE_6SERIES  = 1;
-  localparam  DEVICE_7SERIES  = 0;
-  localparam  DATA_RATE = (DDR_OR_SDR_N == 1) ? "DDR" : "SDR";
-
   // delay controller
 
   generate
diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v
index dabb6fd86..c11072177 100644
--- a/library/xilinx/common/ad_serdes_out.v
+++ b/library/xilinx/common/ad_serdes_out.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -40,8 +40,6 @@
 
 module ad_serdes_out #(
 
-  // parameters
-
   parameter   DEVICE_TYPE = 0,
   parameter   DDR_OR_SDR_N = 1,
   parameter   SERDES_FACTOR = 8,
@@ -49,23 +47,26 @@ module ad_serdes_out #(
 
   // reset and clocks
 
-  input                       rst;
-  input                       clk;
-  input                       div_clk;
-  input                       loaden;
+  input                       rst,
+  input                       clk,
+  input                       div_clk,
+  input                       loaden,
 
   // data interface
 
-  input   [(DATA_WIDTH-1):0]  data_s0;
-  input   [(DATA_WIDTH-1):0]  data_s1;
-  input   [(DATA_WIDTH-1):0]  data_s2;
-  input   [(DATA_WIDTH-1):0]  data_s3;
-  input   [(DATA_WIDTH-1):0]  data_s4;
-  input   [(DATA_WIDTH-1):0]  data_s5;
-  input   [(DATA_WIDTH-1):0]  data_s6;
-  input   [(DATA_WIDTH-1):0]  data_s7;
-  output  [(DATA_WIDTH-1):0]  data_out_p;
-  output  [(DATA_WIDTH-1):0]  data_out_n;
+  input   [(DATA_WIDTH-1):0]  data_s0,
+  input   [(DATA_WIDTH-1):0]  data_s1,
+  input   [(DATA_WIDTH-1):0]  data_s2,
+  input   [(DATA_WIDTH-1):0]  data_s3,
+  input   [(DATA_WIDTH-1):0]  data_s4,
+  input   [(DATA_WIDTH-1):0]  data_s5,
+  input   [(DATA_WIDTH-1):0]  data_s6,
+  input   [(DATA_WIDTH-1):0]  data_s7,
+  output  [(DATA_WIDTH-1):0]  data_out_p,
+  output  [(DATA_WIDTH-1):0]  data_out_n);
+
+  localparam  DEVICE_6SERIES = 1;
+  localparam  DEVICE_7SERIES = 0;
 
   // internal signals
 
@@ -73,134 +74,129 @@ module ad_serdes_out #(
   wire    [(DATA_WIDTH-1):0]  serdes_shift1_s;
   wire    [(DATA_WIDTH-1):0]  serdes_shift2_s;
 
-  // parameters
-
-  localparam  DEVICE_6SERIES = 1;
-  localparam  DEVICE_7SERIES = 0;
-
   // instantiations
 
   genvar l_inst;
   generate
   for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
 
-  if (DEVICE_TYPE == DEVICE_7SERIES) begin
-  OSERDESE2  #(
-    .DATA_RATE_OQ ("DDR"),
-    .DATA_RATE_TQ ("SDR"),
-    .DATA_WIDTH (8),
-    .TRISTATE_WIDTH (1),
-    .SERDES_MODE ("MASTER"))
-  i_serdes (
-    .D1 (data_s0[l_inst]),
-    .D2 (data_s1[l_inst]),
-    .D3 (data_s2[l_inst]),
-    .D4 (data_s3[l_inst]),
-    .D5 (data_s4[l_inst]),
-    .D6 (data_s5[l_inst]),
-    .D7 (data_s6[l_inst]),
-    .D8 (data_s7[l_inst]),
-    .T1 (1'b0),
-    .T2 (1'b0),
-    .T3 (1'b0),
-    .T4 (1'b0),
-    .SHIFTIN1 (1'b0),
-    .SHIFTIN2 (1'b0),
-    .SHIFTOUT1 (),
-    .SHIFTOUT2 (),
-    .OCE (1'b1),
-    .CLK (clk),
-    .CLKDIV (div_clk),
-    .OQ (data_out_s[l_inst]),
-    .TQ (),
-    .OFB (),
-    .TFB (),
-    .TBYTEIN (1'b0),
-    .TBYTEOUT (),
-    .TCE (1'b0),
-    .RST (rst));
-  end
+    if (DEVICE_TYPE == DEVICE_7SERIES) begin
+      OSERDESE2  #(
+        .DATA_RATE_OQ ("DDR"),
+        .DATA_RATE_TQ ("SDR"),
+        .DATA_WIDTH (8),
+        .TRISTATE_WIDTH (1),
+        .SERDES_MODE ("MASTER"))
+      i_serdes (
+        .D1 (data_s0[l_inst]),
+        .D2 (data_s1[l_inst]),
+        .D3 (data_s2[l_inst]),
+        .D4 (data_s3[l_inst]),
+        .D5 (data_s4[l_inst]),
+        .D6 (data_s5[l_inst]),
+        .D7 (data_s6[l_inst]),
+        .D8 (data_s7[l_inst]),
+        .T1 (1'b0),
+        .T2 (1'b0),
+        .T3 (1'b0),
+        .T4 (1'b0),
+        .SHIFTIN1 (1'b0),
+        .SHIFTIN2 (1'b0),
+        .SHIFTOUT1 (),
+        .SHIFTOUT2 (),
+        .OCE (1'b1),
+        .CLK (clk),
+        .CLKDIV (div_clk),
+        .OQ (data_out_s[l_inst]),
+        .TQ (),
+        .OFB (),
+        .TFB (),
+        .TBYTEIN (1'b0),
+        .TBYTEOUT (),
+        .TCE (1'b0),
+        .RST (rst));
+    end
 
-  if (DEVICE_TYPE == DEVICE_6SERIES) begin
-  OSERDESE1  #(
-    .DATA_RATE_OQ ("DDR"),
-    .DATA_RATE_TQ ("SDR"),
-    .DATA_WIDTH (8),
-    .INTERFACE_TYPE ("DEFAULT"),
-    .TRISTATE_WIDTH (1),
-    .SERDES_MODE ("MASTER"))
-  i_serdes_m (
-    .D1 (data_s0[l_inst]),
-    .D2 (data_s1[l_inst]),
-    .D3 (data_s2[l_inst]),
-    .D4 (data_s3[l_inst]),
-    .D5 (data_s4[l_inst]),
-    .D6 (data_s5[l_inst]),
-    .T1 (1'b0),
-    .T2 (1'b0),
-    .T3 (1'b0),
-    .T4 (1'b0),
-    .SHIFTIN1 (serdes_shift1_s[l_inst]),
-    .SHIFTIN2 (serdes_shift2_s[l_inst]),
-    .SHIFTOUT1 (),
-    .SHIFTOUT2 (),
-    .OCE (1'b1),
-    .CLK (clk),
-    .CLKDIV (div_clk),
-    .CLKPERF (1'b0),
-    .CLKPERFDELAY (1'b0),
-    .WC (1'b0),
-    .ODV (1'b0),
-    .OQ (data_out_s[l_inst]),
-    .TQ (),
-    .OCBEXTEND (),
-    .OFB (),
-    .TFB (),
-    .TCE (1'b0),
-    .RST (rst));
+    if (DEVICE_TYPE == DEVICE_6SERIES) begin
+      OSERDESE1  #(
+        .DATA_RATE_OQ ("DDR"),
+        .DATA_RATE_TQ ("SDR"),
+        .DATA_WIDTH (8),
+        .INTERFACE_TYPE ("DEFAULT"),
+        .TRISTATE_WIDTH (1),
+        .SERDES_MODE ("MASTER"))
+      i_serdes_m (
+        .D1 (data_s0[l_inst]),
+        .D2 (data_s1[l_inst]),
+        .D3 (data_s2[l_inst]),
+        .D4 (data_s3[l_inst]),
+        .D5 (data_s4[l_inst]),
+        .D6 (data_s5[l_inst]),
+        .T1 (1'b0),
+        .T2 (1'b0),
+        .T3 (1'b0),
+        .T4 (1'b0),
+        .SHIFTIN1 (serdes_shift1_s[l_inst]),
+        .SHIFTIN2 (serdes_shift2_s[l_inst]),
+        .SHIFTOUT1 (),
+        .SHIFTOUT2 (),
+        .OCE (1'b1),
+        .CLK (clk),
+        .CLKDIV (div_clk),
+        .CLKPERF (1'b0),
+        .CLKPERFDELAY (1'b0),
+        .WC (1'b0),
+        .ODV (1'b0),
+        .OQ (data_out_s[l_inst]),
+        .TQ (),
+        .OCBEXTEND (),
+        .OFB (),
+        .TFB (),
+        .TCE (1'b0),
+        .RST (rst));
 
-  OSERDESE1  #(
-    .DATA_RATE_OQ ("DDR"),
-    .DATA_RATE_TQ ("SDR"),
-    .DATA_WIDTH (8),
-    .INTERFACE_TYPE ("DEFAULT"),
-    .TRISTATE_WIDTH (1),
-    .SERDES_MODE ("SLAVE"))
-  i_serdes_s (
-    .D1 (1'b0), 
-    .D2 (1'b0), 
-    .D3 (data_s6[l_inst]),
-    .D4 (data_s7[l_inst]),
-    .D5 (1'b0),
-    .D6 (1'b0),
-    .T1 (1'b0),
-    .T2 (1'b0),
-    .T3 (1'b0),
-    .T4 (1'b0),
-    .SHIFTIN1 (1'b0),
-    .SHIFTIN2 (1'b0),
-    .SHIFTOUT1 (serdes_shift1_s[l_inst]),
-    .SHIFTOUT2 (serdes_shift2_s[l_inst]),
-    .OCE (1'b1),
-    .CLK (clk),
-    .CLKDIV (div_clk),
-    .CLKPERF (1'b0),
-    .CLKPERFDELAY (1'b0),
-    .WC (1'b0),
-    .ODV (1'b0),
-    .OQ (),
-    .TQ (),
-    .OCBEXTEND (),
-    .OFB (),
-    .TFB (),
-    .TCE (1'b0),
-    .RST (rst));
-  end
+      OSERDESE1  #(
+        .DATA_RATE_OQ ("DDR"),
+        .DATA_RATE_TQ ("SDR"),
+        .DATA_WIDTH (8),
+        .INTERFACE_TYPE ("DEFAULT"),
+        .TRISTATE_WIDTH (1),
+        .SERDES_MODE ("SLAVE"))
+      i_serdes_s (
+        .D1 (1'b0),
+        .D2 (1'b0),
+        .D3 (data_s6[l_inst]),
+        .D4 (data_s7[l_inst]),
+        .D5 (1'b0),
+        .D6 (1'b0),
+        .T1 (1'b0),
+        .T2 (1'b0),
+        .T3 (1'b0),
+        .T4 (1'b0),
+        .SHIFTIN1 (1'b0),
+        .SHIFTIN2 (1'b0),
+        .SHIFTOUT1 (serdes_shift1_s[l_inst]),
+        .SHIFTOUT2 (serdes_shift2_s[l_inst]),
+        .OCE (1'b1),
+        .CLK (clk),
+        .CLKDIV (div_clk),
+        .CLKPERF (1'b0),
+        .CLKPERFDELAY (1'b0),
+        .WC (1'b0),
+        .ODV (1'b0),
+        .OQ (),
+        .TQ (),
+        .OCBEXTEND (),
+        .OFB (),
+        .TFB (),
+        .TCE (1'b0),
+        .RST (rst));
+    end
 
-  OBUFDS i_obuf (
-    .I (data_out_s[l_inst]),
-    .O (data_out_p[l_inst]),
-    .OB (data_out_n[l_inst]));
+    OBUFDS i_obuf (
+      .I (data_out_s[l_inst]),
+      .O (data_out_p[l_inst]),
+      .OB (data_out_n[l_inst]));
 
   end
   endgenerate

From f1e787f86b8337196280871fab7b8dd117459f61 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 16 Sep 2016 14:43:28 +0300
Subject: [PATCH 494/972] fmcomms2: TDD control is enabled by default

---
 projects/fmcomms2/common/fmcomms2_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl
index 2dbf3d04e..f9e2f4532 100644
--- a/projects/fmcomms2/common/fmcomms2_bd.tcl
+++ b/projects/fmcomms2/common/fmcomms2_bd.tcl
@@ -27,6 +27,7 @@ create_bd_port -dir O tdd_sync_t
 # ad9361 core
 
 set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
+set_property -dict [list CONFIG.TDD_CONTROL_EN {1}] $axi_ad9361
 set_property -dict [list CONFIG.ID {0}] $axi_ad9361
 
 set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]

From 2159f78c808b624e160cdb091ddb3e5a09a9cbe3 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 16 Sep 2016 17:38:08 +0300
Subject: [PATCH 495/972] axi_ad9361: Delete invalid assignment of a generated
 wire

---
 library/axi_ad9361/axi_ad9361.v | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 32e768afb..9fe9e6547 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -575,7 +575,6 @@ module axi_ad9361 (
     // TDD control bypass
 
     assign tdd_mode_s     = 1'b0;
-    assign tdd_status_s   = 8'b0;
     assign tdd_enable_s   = 1'b0;
     assign tdd_txnrx_s    = 1'b0;
     assign adc_data_i0    = adc_data_i0_s;

From 3ca9fe09195c2065f018ab938e7a1f98e057bf8b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 16 Sep 2016 14:05:53 -0400
Subject: [PATCH 496/972] sdrstk- remove critical warnings from ps7

---
 projects/sdrstk/system_constr.xdc  | 135 +++++++++++++++++++++++++++++
 projects/sdrstk/system_project.tcl |   1 +
 2 files changed, 136 insertions(+)

diff --git a/projects/sdrstk/system_constr.xdc b/projects/sdrstk/system_constr.xdc
index c87ebe980..d41a6f328 100644
--- a/projects/sdrstk/system_constr.xdc
+++ b/projects/sdrstk/system_constr.xdc
@@ -64,4 +64,139 @@ set_property  -dict {PACKAGE_PIN  P8   IOSTANDARD LVCMOS18} [get_ports clk_out]
 
 create_clock -name rx_clk -period  16 [get_ports rx_clk_in]
 
+# probably gone in 2016.4
+
+create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"]
+create_clock -name clk_fpga_1 -period  5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"]
+
+set_input_jitter clk_fpga_0 0.3
+set_input_jitter clk_fpga_1 0.15
+
+set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*]
+set_property SLEW SLOW [get_ports *fixed_io_mio*]
+set_property DRIVE 8 [get_ports *fixed_io_mio*]
+set_property  -dict {PACKAGE_PIN D8   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]]
+set_property  -dict {PACKAGE_PIN A5   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]]
+set_property  -dict {PACKAGE_PIN A8                  } [get_ports fixed_io_mio[ 2]]
+set_property  -dict {PACKAGE_PIN A7                  } [get_ports fixed_io_mio[ 3]]
+set_property  -dict {PACKAGE_PIN C8                  } [get_ports fixed_io_mio[ 4]]
+set_property  -dict {PACKAGE_PIN A9                  } [get_ports fixed_io_mio[ 5]]
+set_property  -dict {PACKAGE_PIN A10                 } [get_ports fixed_io_mio[ 6]]
+set_property  -dict {PACKAGE_PIN D9                  } [get_ports fixed_io_mio[ 7]]
+set_property  -dict {PACKAGE_PIN B6                  } [get_ports fixed_io_mio[ 8]]
+set_property  -dict {PACKAGE_PIN B5   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]]
+set_property  -dict {PACKAGE_PIN D6   PULLTYPE PULLUP} [get_ports fixed_io_mio[10]]
+set_property  -dict {PACKAGE_PIN B10  PULLTYPE PULLUP} [get_ports fixed_io_mio[11]]
+set_property  -dict {PACKAGE_PIN B7   PULLTYPE PULLUP} [get_ports fixed_io_mio[12]]
+set_property  -dict {PACKAGE_PIN C6   PULLTYPE PULLUP} [get_ports fixed_io_mio[13]]
+set_property  -dict {PACKAGE_PIN B9   PULLTYPE PULLUP} [get_ports fixed_io_mio[14]]
+set_property  -dict {PACKAGE_PIN D10  PULLTYPE PULLUP} [get_ports fixed_io_mio[15]]
+set_property  -dict {PACKAGE_PIN A15  PULLTYPE PULLUP} [get_ports fixed_io_mio[16]]
+set_property  -dict {PACKAGE_PIN D11  PULLTYPE PULLUP} [get_ports fixed_io_mio[17]]
+set_property  -dict {PACKAGE_PIN B15  PULLTYPE PULLUP} [get_ports fixed_io_mio[18]]
+set_property  -dict {PACKAGE_PIN C12  PULLTYPE PULLUP} [get_ports fixed_io_mio[19]]
+set_property  -dict {PACKAGE_PIN E15  PULLTYPE PULLUP} [get_ports fixed_io_mio[20]]
+set_property  -dict {PACKAGE_PIN C11  PULLTYPE PULLUP} [get_ports fixed_io_mio[21]]
+set_property  -dict {PACKAGE_PIN D15  PULLTYPE PULLUP} [get_ports fixed_io_mio[22]]
+set_property  -dict {PACKAGE_PIN A14  PULLTYPE PULLUP} [get_ports fixed_io_mio[23]]
+set_property  -dict {PACKAGE_PIN B14  PULLTYPE PULLUP} [get_ports fixed_io_mio[24]]
+set_property  -dict {PACKAGE_PIN C14  PULLTYPE PULLUP} [get_ports fixed_io_mio[25]]
+set_property  -dict {PACKAGE_PIN A13  PULLTYPE PULLUP} [get_ports fixed_io_mio[26]]
+set_property  -dict {PACKAGE_PIN D14  PULLTYPE PULLUP} [get_ports fixed_io_mio[27]]
+set_property  -dict {PACKAGE_PIN B12  PULLTYPE PULLUP} [get_ports fixed_io_mio[28]]
+set_property  -dict {PACKAGE_PIN D13  PULLTYPE PULLUP} [get_ports fixed_io_mio[29]]
+set_property  -dict {PACKAGE_PIN A12  PULLTYPE PULLUP} [get_ports fixed_io_mio[30]]
+set_property  -dict {PACKAGE_PIN C13  PULLTYPE PULLUP} [get_ports fixed_io_mio[31]]
+
+set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*]
+set_property SLEW SLOW [get_ports *fixed_io_ps*]
+set_property DRIVE 8 [get_ports *fixed_io_ps*]
+set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk]
+set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb]
+
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*]
+set_property SLEW FAST [get_ports *fixed_io_ddr_vr*]
+set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp]
+set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn]
+
+set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*]
+set_property SLEW FAST [get_ports *ddr_ck*]
+set_property PACKAGE_PIN N3 [get_ports ddr_ck_p]
+set_property PACKAGE_PIN N2 [get_ports ddr_ck_n]
+
+set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*]
+set_property SLEW SLOW [get_ports *ddr_addr*]
+set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]]
+set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]]
+set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]]
+set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]]
+set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]]
+set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]]
+set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]]
+set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]]
+set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]]
+set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]]
+set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]]
+set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]]
+set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]]
+set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]]
+set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]]
+
+set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*]
+set_property SLEW SLOW [get_ports *ddr_ba*]
+set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]]
+set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]]
+set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]]
+
+set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n]
+set_property SLEW FAST [get_ports ddr_reset_n]
+set_property PACKAGE_PIN L4 [get_ports ddr_reset_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n]
+set_property SLEW SLOW [get_ports ddr_cs_n]
+set_property PACKAGE_PIN R2 [get_ports ddr_cs_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n]
+set_property SLEW SLOW [get_ports ddr_ras_n]
+set_property PACKAGE_PIN R6 [get_ports ddr_ras_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n]
+set_property SLEW SLOW [get_ports ddr_cas_n]
+set_property PACKAGE_PIN R5 [get_ports ddr_cas_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_we_n]
+set_property SLEW SLOW [get_ports ddr_we_n]
+set_property PACKAGE_PIN R3 [get_ports ddr_we_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cke]
+set_property SLEW SLOW [get_ports ddr_cke]
+set_property PACKAGE_PIN L3 [get_ports ddr_cke]
+set_property IOSTANDARD SSTL15 [get_ports ddr_odt]
+set_property SLEW SLOW [get_ports ddr_odt]
+set_property PACKAGE_PIN K3 [get_ports ddr_odt]
+
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]]
+set_property SLEW FAST [get_ports *ddr_dq[*]]
+set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]]
+set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]]
+set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]]
+set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]]
+set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]]
+set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]]
+set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]]
+set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]]
+set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]]
+set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]]
+set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]]
+set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]]
+set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]]
+set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]]
+set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]]
+set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]]
+set_property SLEW FAST [get_ports *ddr_dm[*]]
+set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]]
+set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]]
+set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*]
+set_property SLEW FAST [get_ports *ddr_dqs*]
+set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]]
+set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]]
+set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]]
+set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]]
+
 
diff --git a/projects/sdrstk/system_project.tcl b/projects/sdrstk/system_project.tcl
index 3e639ce8e..97bd1b8d7 100644
--- a/projects/sdrstk/system_project.tcl
+++ b/projects/sdrstk/system_project.tcl
@@ -11,6 +11,7 @@ adi_project_files sdrstk [list \
   "system_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
+set_property is_enabled false [get_files  *system_sys_ps7_0.xdc]
 adi_project_run sdrstk
 
 

From ff0f659a33b99fb9559b6f1cfe6a43d1574b4a7b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Sep 2016 16:02:06 +0300
Subject: [PATCH 497/972] xilinx/ad_serdes_clk : Rename parameter
 MMCM_DEVICE_TYPE to DEVICE_TYPE

---
 library/xilinx/common/ad_serdes_clk.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/xilinx/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v
index e3ebad19c..495f584f6 100644
--- a/library/xilinx/common/ad_serdes_clk.v
+++ b/library/xilinx/common/ad_serdes_clk.v
@@ -40,10 +40,10 @@
 
 module ad_serdes_clk #(
 
+  parameter       DEVICE_TYPE = 0,
   parameter       DDR_OR_SDR_N = 1,
   parameter       SERDES_FACTOR = 8,
   parameter       MMCM_OR_BUFR_N = 1,
-  parameter       MMCM_DEVICE_TYPE = 0,
   parameter       MMCM_CLKIN_PERIOD  = 1.667,
   parameter       MMCM_VCO_DIV  = 6,
   parameter       MMCM_VCO_MUL = 12.000,
@@ -93,7 +93,7 @@ module ad_serdes_clk #(
   generate
   if (MMCM_OR_BUFR_N == 1) begin
   ad_mmcm_drp #(
-    .MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE),
+    .MMCM_DEVICE_TYPE (DEVICE_TYPE),
     .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
     .MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD),
     .MMCM_VCO_DIV (MMCM_VCO_DIV),

From 38f15218617f81e2e6e2f1058fa19fc037077de1 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Sep 2016 16:02:52 +0300
Subject: [PATCH 498/972] xilinx/ad_serdes_in : Fix some typos

---
 library/xilinx/common/ad_serdes_in.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v
index af09de886..08ea2b4a6 100644
--- a/library/xilinx/common/ad_serdes_in.v
+++ b/library/xilinx/common/ad_serdes_in.v
@@ -140,8 +140,8 @@ module ad_serdes_in #(
     .IDATAIN (data_in_ibuf_s[l_inst]),
     .DATAOUT (data_in_idelay_s[l_inst]),
     .LD (up_dld[l_inst]),
-    .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)),
-    .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)));
+    .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
+    .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
   end
   if(DEVICE_TYPE == DEVICE_6SERIES) begin
   (* IODELAY_GROUP = IODELAY_GROUP *)

From 5592c2780e8a532dbf6021dd1c2e9a9fca07b07b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 19 Sep 2016 11:56:44 -0400
Subject: [PATCH 499/972] axi_xcvrlb- loopback version

---
 library/xilinx/axi_xcvrlb/Makefile          |  57 ++++
 library/xilinx/axi_xcvrlb/axi_xcvrlb.v      | 200 ++++++++++++
 library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v    | 321 ++++++++++++++++++++
 library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl |  58 ++++
 4 files changed, 636 insertions(+)
 create mode 100644 library/xilinx/axi_xcvrlb/Makefile
 create mode 100644 library/xilinx/axi_xcvrlb/axi_xcvrlb.v
 create mode 100644 library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
 create mode 100644 library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl

diff --git a/library/xilinx/axi_xcvrlb/Makefile b/library/xilinx/axi_xcvrlb/Makefile
new file mode 100644
index 000000000..34d8a9662
--- /dev/null
+++ b/library/xilinx/axi_xcvrlb/Makefile
@@ -0,0 +1,57 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := axi_adxcvr_ip.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip.tcl
+M_DEPS += ../../common/up_axi.v
+M_DEPS += axi_adxcvr_es.v
+M_DEPS += axi_adxcvr_up.v
+M_DEPS += axi_adxcvr_mdrp.v
+M_DEPS += axi_adxcvr_mstatus.v
+M_DEPS += axi_adxcvr.v
+M_DEPS += ../../interfaces/if_xcvr_cm.xml
+M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
+M_DEPS += ../../interfaces/if_xcvr_ch.xml
+M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all dep clean clean-all
+all: dep axi_adxcvr.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_adxcvr.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_adxcvr_ip.tcl  >> axi_adxcvr_ip.log 2>&1
+
+dep:
+	make -C ../../interfaces
+####################################################################################
+####################################################################################
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v
new file mode 100644
index 000000000..5c10c5572
--- /dev/null
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v
@@ -0,0 +1,200 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module axi_xcvrlb #(
+
+  // parameters
+
+  parameter   NUM_OF_LANES = 1) (
+
+  // transceiver interface
+
+  input                         ref_clk,
+  input   [(NUM_OF_LANES-1):0]  rx_p,
+  input   [(NUM_OF_LANES-1):0]  rx_n,
+  output  [(NUM_OF_LANES-1):0]  tx_p,
+  output  [(NUM_OF_LANES-1):0]  tx_n,
+
+  // axi interface
+
+  input                         s_axi_aclk,
+  input                         s_axi_aresetn,
+  input                         s_axi_awvalid,
+  input   [31:0]                s_axi_awaddr,
+  input   [ 2:0]                s_axi_awprot,
+  output                        s_axi_awready,
+  input                         s_axi_wvalid,
+  input   [31:0]                s_axi_wdata,
+  input   [ 3:0]                s_axi_wstrb,
+  output                        s_axi_wready,
+  output                        s_axi_bvalid,
+  output  [ 1:0]                s_axi_bresp,
+  input                         s_axi_bready,
+  input                         s_axi_arvalid,
+  input   [31:0]                s_axi_araddr,
+  input   [ 2:0]                s_axi_arprot,
+  output                        s_axi_arready,
+  output                        s_axi_rvalid,
+  output  [ 1:0]                s_axi_rresp,
+  output  [31:0]                s_axi_rdata,
+  input                         s_axi_rready);
+
+  // internal registers
+
+  reg                           up_wack = 'd0;
+  reg     [31:0]                up_scratch = 'd0;
+  reg                           up_resetn = 'd0;
+  reg     [31:0]                up_status = 'd0;
+  reg                           up_rack = 'd0;
+  reg     [31:0]                up_rdata = 'd0;
+
+  // internal signals
+
+  wire                          up_rstn;
+  wire                          up_clk;
+  wire                          up_wreq_s;
+  wire    [ 7:0]                up_waddr_s;
+  wire    [31:0]                up_wdata_s;
+  wire                          up_rreq_s;
+  wire    [ 7:0]                up_raddr_s;
+  wire    [31:0]                up_status_s;
+
+  // defaults
+
+  assign up_rstn = s_axi_aresetn;
+  assign up_clk = s_axi_aclk;
+  assign up_status_s[31:NUM_OF_LANES] = 'd0;
+
+  // register access
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_scratch <= 'd0;
+      up_resetn <= 'd0;
+      up_status <= 'd0;
+    end else begin
+      up_wack <= up_wreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
+        up_scratch <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h04)) begin
+        up_resetn <= up_wdata[0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h05)) begin
+        up_status <= up_status_s | (up_status & ~up_wdata);
+      end else begin
+        up_status <= up_status_s | up_status;
+      end
+    end
+  end
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_rack <= up_rreq_s;
+      if (up_rreq_s == 1'b1) begin
+        case (up_raddr_s)
+          10'h000: up_rdata <= VERSION;
+          10'h001: up_rdata <= ID;
+          10'h002: up_rdata <= up_scratch;
+          10'h004: up_rdata <= {31'd0, up_resetn};
+          10'h005: up_rdata <= up_status;
+          default: up_rdata <= 32'd0;
+        endcase
+      end else begin
+        up_rdata <= 32'd0;
+      end
+    end
+  end
+
+  // instantiations
+
+  genvar n;
+  generate
+  for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lanes
+  axi_xcvrlb_1 i_xcvrlb_1 (
+    .ref_clk (ref_clk),
+    .rx_p (rx_p[n]),
+    .rx_n (rx_n[n]),
+    .tx_p (tx_p[n]),
+    .tx_n (tx_n[n]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_resetn (up_resetn),
+    .up_status (up_status_s[n]));
+  end
+  endgenerate
+
+  up_axi #(.ADDRESS_WIDTH (8)) i_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
new file mode 100644
index 000000000..610ef3b5f
--- /dev/null
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
@@ -0,0 +1,321 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module axi_xcvrlb_1 (
+
+  // transceiver interface
+
+  input           ref_clk,
+  input           rx_p,
+  input           rx_n,
+  output          tx_p,
+  output          tx_n,
+
+  // processor interface
+
+  input           up_rstn,
+  input           up_clk,
+  input           up_resetn,
+  output          up_status);
+
+  // internal registers
+
+  reg     [ 3:0]  rx_kcount = 'd0;
+  reg             rx_calign = 'd0;
+  reg     [31:0]  rx_data = 'd0;
+  reg     [31:0]  rx_pn_data = 'd0;
+  reg     [ 3:0]  tx_charisk = 'd0;
+  reg     [31:0]  tx_data = 'd0;
+  reg     [31:0]  tx_pn_data = 'd0;
+  reg     [ 3:0]  up_pll_rst_cnt = 'd0;
+  reg     [ 3:0]  up_rst_cnt = 'd0;
+  reg     [ 6:0]  up_user_ready_cnt = 'd0;
+  reg             up_status_int = 'd1;
+
+  // internal signals
+
+  wire            rx_status_s;
+  wire    [31:0]  rx_pn_data_s;
+  wire            rx_pn_oos_s;
+  wire            rx_pn_err_s;
+  wire    [ 3:0]  rx_charisk_s;
+  wire    [ 7:0]  rx_error_s;
+  wire    [31:0]  rx_data_s;
+  wire            up_pll_rst_s;
+  wire            up_rst_s;
+  wire            up_user_ready_s;
+  wire            up_pll_locked_s;
+  wire            up_rst_done_s;
+  wire            up_pn_oos_s;
+  wire            up_pn_err_s;
+  wire            up_rx_pll_locked_s;
+  wire            up_rx_rst_done_s;
+  wire            up_tx_pll_locked_s;
+  wire            up_tx_rst_done_s;
+
+  // pn31 function
+
+  function [31:0] pn31;
+    input [31:0] din;
+    reg   [31:0] dout;
+    begin
+      dout[31] = din[31] ^ din[28];
+      dout[30] = din[30] ^ din[27];
+      dout[29] = din[29] ^ din[26];
+      dout[28] = din[28] ^ din[25];
+      dout[27] = din[27] ^ din[24];
+      dout[26] = din[26] ^ din[23];
+      dout[25] = din[25] ^ din[22];
+      dout[24] = din[24] ^ din[21];
+      dout[23] = din[23] ^ din[20];
+      dout[22] = din[22] ^ din[19];
+      dout[21] = din[21] ^ din[18];
+      dout[20] = din[20] ^ din[17];
+      dout[19] = din[19] ^ din[16];
+      dout[18] = din[18] ^ din[15];
+      dout[17] = din[17] ^ din[14];
+      dout[16] = din[16] ^ din[13];
+      dout[15] = din[15] ^ din[12];
+      dout[14] = din[14] ^ din[11];
+      dout[13] = din[13] ^ din[10];
+      dout[12] = din[12] ^ din[ 9];
+      dout[11] = din[11] ^ din[ 8];
+      dout[10] = din[10] ^ din[ 7];
+      dout[ 9] = din[ 9] ^ din[ 6];
+      dout[ 8] = din[ 8] ^ din[ 5];
+      dout[ 7] = din[ 7] ^ din[ 4];
+      dout[ 6] = din[ 6] ^ din[ 3];
+      dout[ 5] = din[ 5] ^ din[ 2];
+      dout[ 4] = din[ 4] ^ din[ 1];
+      dout[ 3] = din[ 3] ^ din[ 0];
+      dout[ 2] = din[ 2] ^ din[31] ^ din[28];
+      dout[ 1] = din[ 1] ^ din[30] ^ din[27];
+      dout[ 0] = din[ 0] ^ din[29] ^ din[26];
+      pn31 = dout;
+    end
+  endfunction
+
+  // receive
+
+  assign rx_status_s = ~(| rx_error_s);
+  assign rx_pn_data_s = (rx_pn_oos_s == 1'b1) ? rx_data_s : rx_pn_data;
+
+  always @(posedge clk) begin
+    if (rx_status_s == 1'b0) begin
+      rx_kcount <= 4'd0;
+      rx_calign <= 1'd1;
+    end else if ((rx_charisk_s == 4'hf) && (rx_data_s == {4{8'hbc}})) begin
+      rx_kcount <= rx_kcount + 1'b1;
+      if (rx_kcount == 4'hf) begin
+        rx_calign <= 1'd0;
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (rx_status_s == 1'b1) begin
+      rx_data[31:24] = rx_data_s[ 7: 0];
+      rx_data[23:16] = rx_data_s[15: 8];
+      rx_data[15: 8] = rx_data_s[23:16];
+      rx_data[ 7: 0] = rx_data_s[31:24];
+    end else begin
+      rx_data[31:24] = 8'hff;
+      rx_data[23:16] = 8'hff;
+      rx_data[15: 8] = 8'hff;
+      rx_data[ 7: 0] = 8'hff;
+    end
+    rx_pn_data <= pn31(rx_pn_data_s);
+  end
+
+  // transmit
+
+  always @(posedge clk) begin
+    if (rx_calign == 1'b0) begin
+      tx_charisk <= 1'd0;
+      tx_data[31:24] <= tx_pn_data[ 7: 0];
+      tx_data[23:16] <= tx_pn_data[15: 8];
+      tx_data[15: 8] <= tx_pn_data[23:16];
+      tx_data[ 7: 0] <= tx_pn_data[31:24];
+      tx_pn_data <= pn31(tx_pn_data);
+    end else begin
+      tx_charisk <= 1'd1;
+      tx_data[31:24] <= 8'hbc;
+      tx_data[23:16] <= 8'hbc;
+      tx_data[15: 8] <= 8'hbc;
+      tx_data[ 7: 0] <= 8'hbc;
+      tx_pn_data <= {32{1'b1}};
+    end
+  end
+
+  // reset & init
+
+  assign up_status = up_status_int;
+  assign up_pll_rst_s = up_pll_rst_cnt[3];
+  assign up_rst_s = up_rst_cnt[3];
+  assign up_user_ready_s = up_user_ready_cnt[6];
+  assign up_pll_locked_s = up_rx_pll_locked_s & up_tx_pll_locked_s;
+  assign up_rst_done_s = up_rx_rst_done_s & up_tx_rst_done_s;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_pll_rst_cnt <= 4'h8;
+      up_rst_cnt <= 4'h8;
+      up_user_ready_cnt <= 7'h00;
+      up_status_int <= 1'b1;
+    end else begin
+      if (up_resetn == 1'b0) begin
+        up_pll_rst_cnt <= 4'h8;
+      end else if (up_pll_rst_cnt[3] == 1'b1) begin
+        up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1;
+      end
+      if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) ||
+        (up_pll_locked_s == 1'b0)) begin
+        up_rst_cnt <= 4'h8;
+      end else if (up_rst_cnt[3] == 1'b1) begin
+        up_rst_cnt <= up_rst_cnt + 1'b1;
+      end
+      if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin
+        up_user_ready_cnt <= 7'h00;
+      end else if (up_user_ready_cnt[6] == 1'b0) begin
+        up_user_ready_cnt <= up_user_ready_cnt + 1'b1;
+      end
+      if ((up_resetn == 1'b0) || (up_rst_done_s == 1'b0)) begin
+        up_status_int <= 1'b1;
+      end else begin
+        up_status_int <= up_pn_oos_s | up_pn_err_s;
+      end
+    end
+  end
+
+  // instantiations
+
+  ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
+    .adc_clk (clk),
+    .adc_valid_in (1'b1),
+    .adc_data_in (rx_data),
+    .adc_data_pn (rx_pn_data),
+    .adc_pn_oos (rx_pn_oos_s),
+    .adc_pn_err (rx_pn_err_s));
+
+  up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_data_status ({up_pn_err_s, up_pn_oos_s}),
+    .d_rst (1'b0),
+    .d_clk (clk),
+    .d_data_status ({rx_pn_err_s, rx_pn_oos_s}));
+
+  util_adxcvr_xch #(
+    .XCVR_ID (15),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .CPLL_TX_OR_RX_N (0),
+    .CPLL_FBDIV (2),
+    .RX_OUT_DIV (1),
+    .RX_CLK25_DIV (10),
+    .TX_OUT_DIV (1),
+    .TX_CLK25_DIV (10),
+    .PMA_RSV ('h00018480),
+    .RX_CDR_CFG ('h03000023ff20400020))
+  i_xch (
+    .qpll2ch_clk (1'b0),
+    .qpll2ch_ref_clk (1'b0),
+    .qpll2ch_locked (1'b1),
+    .cpll_ref_clk (ref_clk),
+    .rx_p (rx_p),
+    .rx_n (rx_n),
+    .rx_out_clk (clk),
+    .rx_clk (rx_clk),
+    .rx_charisk (rx_charisk_s),
+    .rx_disperr (rx_error_s[3:0]),
+    .rx_notintable (rx_error_s[7:4]),
+    .rx_data (rx_data_s),
+    .rx_calign (rx_calign),
+    .tx_p (tx_p),
+    .tx_n (tx_n),
+    .tx_out_clk (),
+    .tx_clk (clk),
+    .tx_charisk ({4{tx_charisk}}),
+    .tx_data (tx_data),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_es_sel (1'd0),
+    .up_es_enb (1'd0),
+    .up_es_addr (12'd0),
+    .up_es_wr (1'd0),
+    .up_es_wdata (16'd0),
+    .up_es_rdata (),
+    .up_es_ready (),
+    .up_rx_pll_rst (up_pll_rst_s),
+    .up_rx_pll_locked (up_rx_pll_locked_s),
+    .up_rx_rst (up_rst_s),
+    .up_rx_user_ready (up_user_ready_s),
+    .up_rx_rst_done (up_rx_rst_done_s),
+    .up_rx_lpm_dfe_n (1'd0),
+    .up_rx_rate (3'd0),
+    .up_rx_sys_clk_sel (2'd0),
+    .up_rx_out_clk_sel (3'd2),
+    .up_rx_sel (1'd0),
+    .up_rx_enb (1'd0),
+    .up_rx_addr (12'd0),
+    .up_rx_wr (1'd0),
+    .up_rx_wdata (16'd0),
+    .up_rx_rdata (),
+    .up_rx_ready (),
+    .up_tx_pll_rst (up_pll_rst_s),
+    .up_tx_pll_locked (up_tx_pll_locked_s),
+    .up_tx_rst (up_rst_s),
+    .up_tx_user_ready (up_user_ready_s),
+    .up_tx_rst_done (up_tx_rst_done_s),
+    .up_tx_lpm_dfe_n (1'd0),
+    .up_tx_rate (3'd0),
+    .up_tx_sys_clk_sel (2'd0),
+    .up_tx_out_clk_sel (3'd2),
+    .up_tx_sel (1'd0),
+    .up_tx_enb (1'd0),
+    .up_tx_addr (12'd0),
+    .up_tx_wr (1'd0),
+    .up_tx_wdata (16'd0),
+    .up_tx_rdata (),
+    .up_tx_ready ());
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl b/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl
new file mode 100644
index 000000000..c7c179d37
--- /dev/null
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl
@@ -0,0 +1,58 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_xcvrlb
+adi_ip_files axi_xcvrlb [list \
+  "$ad_hdl_dir/library/xilinx/util_adxcvr/util_adxcvr_xch.v" \
+  "$ad_hdl_dir/library/common/up_xfer_status.v" \
+  "$ad_hdl_dir/library/common/ad_pnmon.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "axi_xcvrlb_1.v" \
+  "axi_xcvrlb.v" ]
+
+adi_ip_properties_lite axi_xcvrlb
+
+ipx::remove_all_bus_interface [ipx::current_core]
+
+set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
+
+ipx::infer_bus_interface {\
+  s_axi_awvalid \
+  s_axi_awaddr \
+  s_axi_awprot \
+  s_axi_awready \
+  s_axi_wvalid \
+  s_axi_wdata \
+  s_axi_wstrb \
+  s_axi_wready \
+  s_axi_bvalid \
+  s_axi_bresp \
+  s_axi_bready \
+  s_axi_arvalid \
+  s_axi_araddr \
+  s_axi_arprot \
+  s_axi_arready \
+  s_axi_rvalid \
+  s_axi_rdata \
+  s_axi_rresp \
+  s_axi_rready} \
+xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
+ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
+  -of_objects [ipx::current_core]]
+set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
+  -of_objects [ipx::get_bus_interfaces s_axi_aclk \
+  -of_objects [ipx::current_core]]]
+
+ipx::add_memory_map {s_axi} [ipx::current_core]
+set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
+ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
+set_property range {1024} [ipx::get_address_blocks axi_lite \
+  -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
+
+ipx::save_core [ipx::current_core]
+

From 1860d72df6af5f8279ae51cb4268fd9c7f4bf6af Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 19 Sep 2016 12:39:39 -0400
Subject: [PATCH 500/972] axi_xcvrlb- updates

---
 library/xilinx/axi_xcvrlb/Makefile       | 26 +++++++++---------------
 library/xilinx/axi_xcvrlb/axi_xcvrlb.v   | 13 +++++++-----
 library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v |  7 ++++---
 3 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/library/xilinx/axi_xcvrlb/Makefile b/library/xilinx/axi_xcvrlb/Makefile
index 34d8a9662..3baba09b3 100644
--- a/library/xilinx/axi_xcvrlb/Makefile
+++ b/library/xilinx/axi_xcvrlb/Makefile
@@ -5,19 +5,15 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_adxcvr_ip.tcl
+M_DEPS := axi_xcvrlb_ip.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
+M_DEPS += ../../xilinx/util_adxcvr/util_adxcvr_xch.v
+M_DEPS += ../../common/up_xfer_status.v
+M_DEPS += ../../common/ad_pnmon.v
 M_DEPS += ../../common/up_axi.v
-M_DEPS += axi_adxcvr_es.v
-M_DEPS += axi_adxcvr_up.v
-M_DEPS += axi_adxcvr_mdrp.v
-M_DEPS += axi_adxcvr_mstatus.v
-M_DEPS += axi_adxcvr.v
-M_DEPS += ../../interfaces/if_xcvr_cm.xml
-M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
-M_DEPS += ../../interfaces/if_xcvr_ch.xml
-M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
+M_DEPS += axi_xcvrlb_1.v
+M_DEPS += axi_xcvrlb.v
 
 M_VIVADO := vivado -mode batch -source
 
@@ -36,8 +32,8 @@ M_FLIST += .Xil
 
 
 
-.PHONY: all dep clean clean-all
-all: dep axi_adxcvr.xpr
+.PHONY: all clean clean-all
+all: axi_xcvrlb.xpr
 
 
 clean:clean-all
@@ -47,11 +43,9 @@ clean-all:
 	rm -rf $(M_FLIST)
 
 
-axi_adxcvr.xpr: $(M_DEPS)
+axi_xcvrlb.xpr: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) axi_adxcvr_ip.tcl  >> axi_adxcvr_ip.log 2>&1
+	$(M_VIVADO) axi_xcvrlb_ip.tcl  >> axi_xcvrlb_ip.log 2>&1
 
-dep:
-	make -C ../../interfaces
 ####################################################################################
 ####################################################################################
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v
index 5c10c5572..ffa9fb9e3 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v
@@ -95,6 +95,10 @@ module axi_xcvrlb #(
   wire    [ 7:0]                up_raddr_s;
   wire    [31:0]                up_status_s;
 
+  // parameters
+
+  localparam  [31:0]  VERSION = 32'h00100161;
+
   // defaults
 
   assign up_rstn = s_axi_aresetn;
@@ -112,13 +116,13 @@ module axi_xcvrlb #(
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
-        up_scratch <= up_wdata;
+        up_scratch <= up_wdata_s;
       end
       if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h04)) begin
-        up_resetn <= up_wdata[0];
+        up_resetn <= up_wdata_s[0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h05)) begin
-        up_status <= up_status_s | (up_status & ~up_wdata);
+        up_status <= up_status_s | (up_status & ~up_wdata_s);
       end else begin
         up_status <= up_status_s | up_status;
       end
@@ -134,7 +138,6 @@ module axi_xcvrlb #(
       if (up_rreq_s == 1'b1) begin
         case (up_raddr_s)
           10'h000: up_rdata <= VERSION;
-          10'h001: up_rdata <= ID;
           10'h002: up_rdata <= up_scratch;
           10'h004: up_rdata <= {31'd0, up_resetn};
           10'h005: up_rdata <= up_status;
@@ -187,7 +190,7 @@ module axi_xcvrlb #(
     .up_wreq (up_wreq_s),
     .up_waddr (up_waddr_s),
     .up_wdata (up_wdata_s),
-    .up_wack (up_wack_s),
+    .up_wack (up_wack),
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata),
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
index 610ef3b5f..9b0e383b4 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
@@ -60,7 +60,7 @@ module axi_xcvrlb_1 (
   reg             rx_calign = 'd0;
   reg     [31:0]  rx_data = 'd0;
   reg     [31:0]  rx_pn_data = 'd0;
-  reg     [ 3:0]  tx_charisk = 'd0;
+  reg             tx_charisk = 'd0;
   reg     [31:0]  tx_data = 'd0;
   reg     [31:0]  tx_pn_data = 'd0;
   reg     [ 3:0]  up_pll_rst_cnt = 'd0;
@@ -70,6 +70,7 @@ module axi_xcvrlb_1 (
 
   // internal signals
 
+  wire            clk;
   wire            rx_status_s;
   wire    [31:0]  rx_pn_data_s;
   wire            rx_pn_oos_s;
@@ -243,7 +244,7 @@ module axi_xcvrlb_1 (
 
   util_adxcvr_xch #(
     .XCVR_ID (15),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .GTH_OR_GTX_N (0),
     .CPLL_TX_OR_RX_N (0),
     .CPLL_FBDIV (2),
     .RX_OUT_DIV (1),
@@ -260,7 +261,7 @@ module axi_xcvrlb_1 (
     .rx_p (rx_p),
     .rx_n (rx_n),
     .rx_out_clk (clk),
-    .rx_clk (rx_clk),
+    .rx_clk (clk),
     .rx_charisk (rx_charisk_s),
     .rx_disperr (rx_error_s[3:0]),
     .rx_notintable (rx_error_s[7:4]),

From 10408b8c884c8c567a660b1681f6085c4b2c4077 Mon Sep 17 00:00:00 2001
From: Dragos Bogdan <dragos.bogdan@analog.com>
Date: Wed, 21 Sep 2016 10:27:28 +0300
Subject: [PATCH 501/972] up_tdd_cntrl: Set PCORE version to 1.00.a

---
 library/common/up_tdd_cntrl.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v
index 9ef59b490..2a83d7b94 100644
--- a/library/common/up_tdd_cntrl.v
+++ b/library/common/up_tdd_cntrl.v
@@ -97,7 +97,7 @@ module up_tdd_cntrl (
 
   // parameters
 
-  localparam  PCORE_VERSION = 32'h00010001;
+  localparam  PCORE_VERSION = 32'h00010061;
   parameter   ID = 0;
 
   input           clk;

From 913eafed489a1f543a057b022107922009988e1c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 21 Sep 2016 15:00:45 +0300
Subject: [PATCH 502/972] up_drp : Update the DRP interface to support Altera
 platforms

---
 library/axi_ad6676/axi_ad6676.v           |  2 +-
 library/axi_ad9144/axi_ad9144_core.v      |  2 +-
 library/axi_ad9152/axi_ad9152_core.v      |  2 +-
 library/axi_ad9162/axi_ad9162_core.v      |  2 +-
 library/axi_ad9234/axi_ad9234.v           |  2 +-
 library/axi_ad9250/axi_ad9250.v           |  2 +-
 library/axi_ad9265/axi_ad9265.v           |  2 +-
 library/axi_ad9361/axi_ad9361_rx.v        |  2 +-
 library/axi_ad9361/axi_ad9361_tx.v        |  2 +-
 library/axi_ad9371/axi_ad9371_rx.v        |  2 +-
 library/axi_ad9371/axi_ad9371_rx_os.v     |  2 +-
 library/axi_ad9371/axi_ad9371_tx.v        |  2 +-
 library/axi_ad9625/axi_ad9625.v           |  2 +-
 library/axi_ad9643/axi_ad9643.v           |  2 +-
 library/axi_ad9652/axi_ad9652.v           |  2 +-
 library/axi_ad9671/axi_ad9671.v           |  2 +-
 library/axi_ad9680/axi_ad9680.v           |  2 +-
 library/axi_ad9739a/axi_ad9739a_core.v    |  2 +-
 library/axi_generic_adc/axi_generic_adc.v |  2 +-
 library/common/up_adc_common.v            | 34 +++++++++++++----------
 library/common/up_dac_common.v            | 32 +++++++++++----------
 21 files changed, 56 insertions(+), 48 deletions(-)

diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v
index 7131e97fa..de5b289da 100755
--- a/library/axi_ad6676/axi_ad6676.v
+++ b/library/axi_ad6676/axi_ad6676.v
@@ -278,7 +278,7 @@ module axi_ad6676 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v
index 9535c2764..145ba8b1e 100644
--- a/library/axi_ad9144/axi_ad9144_core.v
+++ b/library/axi_ad9144/axi_ad9144_core.v
@@ -300,7 +300,7 @@ module axi_ad9144_core (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v
index 93cb929ea..f98d8b26b 100644
--- a/library/axi_ad9152/axi_ad9152_core.v
+++ b/library/axi_ad9152/axi_ad9152_core.v
@@ -224,7 +224,7 @@ module axi_ad9152_core (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v
index eea944f67..7bfbbdcd7 100644
--- a/library/axi_ad9162/axi_ad9162_core.v
+++ b/library/axi_ad9162/axi_ad9162_core.v
@@ -179,7 +179,7 @@ module axi_ad9162_core (
       .up_drp_wr (),
       .up_drp_addr (),
       .up_drp_wdata (),
-      .up_drp_rdata (16'd0),
+      .up_drp_rdata (32'd0),
       .up_drp_ready (1'd0),
       .up_drp_locked (1'd1),
       .up_usr_chanmax (),
diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v
index 53680519b..d26b48102 100644
--- a/library/axi_ad9234/axi_ad9234.v
+++ b/library/axi_ad9234/axi_ad9234.v
@@ -276,7 +276,7 @@ module axi_ad9234 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v
index 679c22af1..cd63f98b6 100644
--- a/library/axi_ad9250/axi_ad9250.v
+++ b/library/axi_ad9250/axi_ad9250.v
@@ -277,7 +277,7 @@ module axi_ad9250 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v
index 1afb8111a..0ed145d04 100644
--- a/library/axi_ad9265/axi_ad9265.v
+++ b/library/axi_ad9265/axi_ad9265.v
@@ -299,7 +299,7 @@ module axi_ad9265 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v
index db4044d1a..4c4a60ab7 100644
--- a/library/axi_ad9361/axi_ad9361_rx.v
+++ b/library/axi_ad9361/axi_ad9361_rx.v
@@ -370,7 +370,7 @@ module axi_ad9361_rx (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v
index 42ac81421..a6312493f 100644
--- a/library/axi_ad9361/axi_ad9361_tx.v
+++ b/library/axi_ad9361/axi_ad9361_tx.v
@@ -377,7 +377,7 @@ module axi_ad9361_tx (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9371/axi_ad9371_rx.v b/library/axi_ad9371/axi_ad9371_rx.v
index 55c7ce5c9..a0f5e6b12 100644
--- a/library/axi_ad9371/axi_ad9371_rx.v
+++ b/library/axi_ad9371/axi_ad9371_rx.v
@@ -319,7 +319,7 @@ module axi_ad9371_rx (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9371/axi_ad9371_rx_os.v b/library/axi_ad9371/axi_ad9371_rx_os.v
index ec839738f..8bbb1afc9 100644
--- a/library/axi_ad9371/axi_ad9371_rx_os.v
+++ b/library/axi_ad9371/axi_ad9371_rx_os.v
@@ -236,7 +236,7 @@ module axi_ad9371_rx_os (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v
index 4bd197b48..b53f625f0 100644
--- a/library/axi_ad9371/axi_ad9371_tx.v
+++ b/library/axi_ad9371/axi_ad9371_tx.v
@@ -305,7 +305,7 @@ module axi_ad9371_tx (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v
index 8fd860fc3..bd23692d6 100644
--- a/library/axi_ad9625/axi_ad9625.v
+++ b/library/axi_ad9625/axi_ad9625.v
@@ -242,7 +242,7 @@ module axi_ad9625 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9643/axi_ad9643.v b/library/axi_ad9643/axi_ad9643.v
index 312036814..4fbb67a54 100644
--- a/library/axi_ad9643/axi_ad9643.v
+++ b/library/axi_ad9643/axi_ad9643.v
@@ -335,7 +335,7 @@ module axi_ad9643 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9652/axi_ad9652.v b/library/axi_ad9652/axi_ad9652.v
index f706e1494..4b51be6ea 100644
--- a/library/axi_ad9652/axi_ad9652.v
+++ b/library/axi_ad9652/axi_ad9652.v
@@ -333,7 +333,7 @@ module axi_ad9652 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v
index 46406cfab..1b524ca70 100644
--- a/library/axi_ad9671/axi_ad9671.v
+++ b/library/axi_ad9671/axi_ad9671.v
@@ -290,7 +290,7 @@ module axi_ad9671 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v
index a7b50c7c5..0f404143c 100644
--- a/library/axi_ad9680/axi_ad9680.v
+++ b/library/axi_ad9680/axi_ad9680.v
@@ -281,7 +281,7 @@ module axi_ad9680 (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd0),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v
index 12a2a34bc..0f8387866 100644
--- a/library/axi_ad9739a/axi_ad9739a_core.v
+++ b/library/axi_ad9739a/axi_ad9739a_core.v
@@ -227,7 +227,7 @@ module axi_ad9739a_core (
     .up_drp_wr (),
     .up_drp_addr (),
     .up_drp_wdata (),
-    .up_drp_rdata (16'd0),
+    .up_drp_rdata (32'd0),
     .up_drp_ready (1'd1),
     .up_drp_locked (1'd1),
     .up_usr_chanmax (),
diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v
index c466ec2eb..b7c899abe 100644
--- a/library/axi_generic_adc/axi_generic_adc.v
+++ b/library/axi_generic_adc/axi_generic_adc.v
@@ -101,7 +101,7 @@ up_adc_common #(.ID(ID)) i_up_adc_common (
 	.up_drp_wr (),
 	.up_drp_addr (),
 	.up_drp_wdata (),
-	.up_drp_rdata (16'd0),
+	.up_drp_rdata (32'd0),
 	.up_drp_ready (1'd0),
 	.up_drp_locked (1'd1),
 	.up_usr_chanmax (),
diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index 2a9738b8d..bc6c7dda3 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -130,8 +130,8 @@ module up_adc_common (
   output          up_drp_sel;
   output          up_drp_wr;
   output  [11:0]  up_drp_addr;
-  output  [15:0]  up_drp_wdata;
-  input   [15:0]  up_drp_rdata;
+  output  [31:0]  up_drp_wdata;
+  input   [31:0]  up_drp_rdata;
   input           up_drp_ready;
   input           up_drp_locked;
 
@@ -156,7 +156,7 @@ module up_adc_common (
   output          up_rack;
 
   // internal registers
-  
+
   reg             up_core_preset = 'd0;
   reg             up_mmcm_preset = 'd0;
   reg             up_wack = 'd0;
@@ -171,8 +171,8 @@ module up_adc_common (
   reg             up_drp_status = 'd0;
   reg             up_drp_rwn = 'd0;
   reg     [11:0]  up_drp_addr = 'd0;
-  reg     [15:0]  up_drp_wdata = 'd0;
-  reg     [15:0]  up_drp_rdata_hold = 'd0;
+  reg     [31:0]  up_drp_wdata = 'd0;
+  reg     [31:0]  up_drp_rdata_hold = 'd0;
   reg             up_status_ovf = 'd0;
   reg             up_status_unf = 'd0;
   reg     [ 7:0]  up_usr_chanmax = 'd0;
@@ -259,9 +259,11 @@ module up_adc_common (
         up_drp_status <= 1'b0;
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
-        up_drp_rwn <= up_wdata[28];
-        up_drp_addr <= up_wdata[27:16];
-        up_drp_wdata <= up_wdata[15:0];
+        up_drp_rwn <= up_wdata[12];
+        up_drp_addr <= up_wdata[11:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
+        up_drp_wdata <= up_wdata;
       end
       if (up_drp_ready == 1'b1) begin
         up_drp_rdata_hold <= up_drp_rdata;
@@ -307,8 +309,10 @@ module up_adc_common (
           8'h16: up_rdata <= adc_clk_ratio;
           8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
           8'h1a: up_rdata <= {31'd0, up_sync_status_s};
-          8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
-          8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
+          8'h1c: up_rdata <= {19'd0, up_drp_rwn, up_drp_addr};
+          8'h1d: up_rdata <= {30'd0, up_drp_locked, up_drp_status};
+          8'h1e: up_rdata <= up_drp_wdata;
+          8'h1f: up_rdata <= up_drp_rdata_hold;
           8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
           8'h23: up_rdata <= 32'd8;
           8'h28: up_rdata <= {24'd0, adc_usr_chanmax};
diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index 82e5d1f45..02900c7b9 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -122,8 +122,8 @@ module up_dac_common (
   output          up_drp_sel;
   output          up_drp_wr;
   output  [11:0]  up_drp_addr;
-  output  [15:0]  up_drp_wdata;
-  input   [15:0]  up_drp_rdata;
+  output  [31:0]  up_drp_wdata;
+  input   [31:0]  up_drp_rdata;
   input           up_drp_ready;
   input           up_drp_locked;
 
@@ -168,8 +168,8 @@ module up_dac_common (
   reg             up_drp_status = 'd0;
   reg             up_drp_rwn = 'd0;
   reg     [11:0]  up_drp_addr = 'd0;
-  reg     [15:0]  up_drp_wdata = 'd0;
-  reg     [15:0]  up_drp_rdata_hold = 'd0;
+  reg     [31:0]  up_drp_wdata = 'd0;
+  reg     [31:0]  up_drp_rdata_hold = 'd0;
   reg             up_status_ovf = 'd0;
   reg             up_status_unf = 'd0;
   reg     [ 7:0]  up_usr_chanmax = 'd0;
@@ -280,9 +280,11 @@ module up_dac_common (
         up_drp_status <= 1'b0;
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
-        up_drp_rwn <= up_wdata[28];
-        up_drp_addr <= up_wdata[27:16];
-        up_drp_wdata <= up_wdata[15:0];
+        up_drp_rwn <= up_wdata[12];
+        up_drp_addr <= up_wdata[11:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
+        up_drp_wdata <= up_wdata;
       end
       if (up_drp_ready == 1'b1) begin
         up_drp_rdata_hold <= up_drp_rdata;
@@ -329,8 +331,10 @@ module up_dac_common (
           8'h16: up_rdata <= dac_clk_ratio;
           8'h17: up_rdata <= {31'd0, up_status_s};
           8'h18: up_rdata <= {31'd0, up_dac_clksel};
-          8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
-          8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
+          8'h1c: up_rdata <= {19'd0, up_drp_rwn, up_drp_addr};
+          8'h1d: up_rdata <= {30'd0, up_drp_locked, up_drp_status};
+          8'h1e: up_rdata <= up_drp_wdata;
+          8'h1f: up_rdata <= up_drp_rdata_hold;
           8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};
           8'h28: up_rdata <= {24'd0, dac_usr_chanmax};
           8'h2e: up_rdata <= up_dac_gpio_in;

From 781702c1b98205d3c0e6a2e2e2e5779d26ecd3ca Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 21 Sep 2016 15:12:59 +0300
Subject: [PATCH 503/972] axi_ad9434: Update the core to the new DRP interface

---
 library/axi_ad9434/axi_ad9434.v      |  4 +-
 library/axi_ad9434/axi_ad9434_core.v |  4 +-
 library/axi_ad9434/axi_ad9434_if.v   | 88 +++++++++++++++-------------
 3 files changed, 50 insertions(+), 46 deletions(-)

diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v
index b8e9d96db..83e32fa8c 100644
--- a/library/axi_ad9434/axi_ad9434.v
+++ b/library/axi_ad9434/axi_ad9434.v
@@ -167,8 +167,8 @@ module axi_ad9434 (
   wire            up_drp_sel_s;
   wire            up_drp_wr_s;
   wire    [11:0]  up_drp_addr_s;
-  wire    [15:0]  up_drp_wdata_s;
-  wire    [15:0]  up_drp_rdata_s;
+  wire    [31:0]  up_drp_wdata_s;
+  wire    [31:0]  up_drp_rdata_s;
   wire            up_drp_ready_s;
   wire            up_drp_locked_s;
 
diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v
index a0d94d6af..e0f614b40 100644
--- a/library/axi_ad9434/axi_ad9434_core.v
+++ b/library/axi_ad9434/axi_ad9434_core.v
@@ -109,8 +109,8 @@ module axi_ad9434_core (
   output          up_drp_sel;
   output          up_drp_wr;
   output  [11:0]  up_drp_addr;
-  output  [15:0]  up_drp_wdata;
-  input   [15:0]  up_drp_rdata;
+  output  [31:0]  up_drp_wdata;
+  input   [31:0]  up_drp_rdata;
   input           up_drp_ready;
   input           up_drp_locked;
 
diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v
index 88eaff972..bb4da7915 100644
--- a/library/axi_ad9434/axi_ad9434_if.v
+++ b/library/axi_ad9434/axi_ad9434_if.v
@@ -124,8 +124,8 @@ module axi_ad9434_if (
   input           up_drp_sel;
   input           up_drp_wr;
   input   [11:0]  up_drp_addr;
-  input   [15:0]  up_drp_wdata;
-  output  [15:0]  up_drp_rdata;
+  input   [31:0]  up_drp_wdata;
+  output  [31:0]  up_drp_rdata;
   output          up_drp_ready;
   output          up_drp_locked;
 
@@ -147,37 +147,36 @@ module axi_ad9434_if (
   assign  adc_clk = adc_div_clk;
 
   // data interface
-  generate
-  for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
-    ad_serdes_in #(
-      .DEVICE_TYPE(DEVICE_TYPE),
-      .IODELAY_CTRL(0),
-      .IODELAY_GROUP(IO_DELAY_GROUP),
-      .DDR_OR_SDR_N(SDR),
-      .DATA_WIDTH(4))
-    i_adc_data (
-      .rst(adc_rst),
-      .clk(adc_clk_in),
-      .div_clk(adc_div_clk),
-      .data_s0(adc_data[(3*12)+l_inst]),
-      .data_s1(adc_data[(2*12)+l_inst]),
-      .data_s2(adc_data[(1*12)+l_inst]),
-      .data_s3(adc_data[(0*12)+l_inst]),
-      .data_s4(),
-      .data_s5(),
-      .data_s6(),
-      .data_s7(),
-      .data_in_p(adc_data_in_p[l_inst]),
-      .data_in_n(adc_data_in_n[l_inst]),
-      .up_clk (up_clk),
-      .up_dld (up_adc_dld[l_inst]),
-      .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
-      .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
-      .delay_clk(delay_clk),
-      .delay_rst(delay_rst),
-      .delay_locked());
-    end
-  endgenerate
+  ad_serdes_in #(
+    .DEVICE_TYPE(DEVICE_TYPE),
+    .IODELAY_CTRL(0),
+    .IODELAY_GROUP(IO_DELAY_GROUP),
+    .DDR_OR_SDR_N(SDR),
+    .DATA_WIDTH(12))
+  i_adc_data (
+    .rst(adc_rst),
+    .clk(adc_clk_in),
+    .div_clk(adc_div_clk),
+    .loaden(1'b0),
+    .phase(8'b0),
+    .locked(1'b0),
+    .data_s0(adc_data[47:36]),
+    .data_s1(adc_data[35:24]),
+    .data_s2(adc_data[23:12]),
+    .data_s3(adc_data[11: 0]),
+    .data_s4(),
+    .data_s5(),
+    .data_s6(),
+    .data_s7(),
+    .data_in_p(adc_data_in_p),
+    .data_in_n(adc_data_in_n),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[11:0]),
+    .up_dwdata (up_adc_dwdata[59:0]),
+    .up_drdata (up_adc_drdata[59:0]),
+    .delay_clk(delay_clk),
+    .delay_rst(delay_rst),
+    .delay_locked());
 
   // over-range interface
   ad_serdes_in #(
@@ -185,15 +184,18 @@ module axi_ad9434_if (
     .IODELAY_CTRL(1),
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(SDR),
-    .DATA_WIDTH(4))
-  i_adc_data (
+    .DATA_WIDTH(1))
+  i_adc_or (
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
-    .data_s0(adc_or_s[0]),
-    .data_s1(adc_or_s[1]),
-    .data_s2(adc_or_s[2]),
-    .data_s3(adc_or_s[3]),
+    .loaden(1'b0),
+    .phase(8'b0),
+    .locked(1'b0),
+    .data_s0(adc_or_s[3]),
+    .data_s1(adc_or_s[2]),
+    .data_s2(adc_or_s[1]),
+    .data_s3(adc_or_s[0]),
     .data_s4(),
     .data_s5(),
     .data_s6(),
@@ -210,19 +212,21 @@ module axi_ad9434_if (
 
   // clock input buffers and MMCM_OR_BUFR_N
   ad_serdes_clk #(
-    .MMCM_DEVICE_TYPE (DEVICE_TYPE),
+    .DEVICE_TYPE (DEVICE_TYPE),
     .MMCM_CLKIN_PERIOD (2),
     .MMCM_VCO_DIV (6),
     .MMCM_VCO_MUL (12),
     .MMCM_CLK0_DIV (2),
     .MMCM_CLK1_DIV (8))
   i_serdes_clk (
-    .mmcm_rst (mmcm_rst),
+    .rst (mmcm_rst),
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk_in),
     .div_clk (adc_div_clk),
     .out_clk (),
+    .loaden (),
+    .phase (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),
@@ -233,7 +237,7 @@ module axi_ad9434_if (
     .up_drp_ready (up_drp_ready),
     .up_drp_locked (up_drp_locked));
 
-  // adc overange
+  // adc over range
   assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3];
 
   // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up

From bae839acd4fa3dbce821b78231a059a89cc3ac59 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 21 Sep 2016 15:23:08 +0300
Subject: [PATCH 504/972] axi_ad9739a: Update core to the new DRP interface

---
 library/axi_ad9739a/axi_ad9739a_if.v | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v
index f84187f69..c333ca06f 100644
--- a/library/axi_ad9739a/axi_ad9739a_if.v
+++ b/library/axi_ad9739a/axi_ad9739a_if.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -143,13 +143,14 @@ module axi_ad9739a_if (
   // dac data output serdes(s) & buffers
 
   ad_serdes_out #(
-    .SERDES_OR_DDR_N(1),
+    .DDR_OR_SDR_N(1),
     .DATA_WIDTH(14),
     .DEVICE_TYPE (DEVICE_TYPE))
   i_serdes_out_data_a (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
+    .loaden (1'b0),
     .data_s0 (dac_data_00[15:2]),
     .data_s1 (dac_data_02[15:2]),
     .data_s2 (dac_data_04[15:2]),
@@ -162,15 +163,16 @@ module axi_ad9739a_if (
     .data_out_n (dac_data_out_a_n));
 
   // dac data output serdes(s) & buffers
-  
+
   ad_serdes_out #(
-    .SERDES_OR_DDR_N(1),
+    .DDR_OR_SDR_N(1),
     .DATA_WIDTH(14),
     .DEVICE_TYPE (DEVICE_TYPE))
   i_serdes_out_data_b (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
+    .loaden (1'b0),
     .data_s0 (dac_data_01[15:2]),
     .data_s1 (dac_data_03[15:2]),
     .data_s2 (dac_data_05[15:2]),
@@ -183,15 +185,16 @@ module axi_ad9739a_if (
     .data_out_n (dac_data_out_b_n));
 
   // dac clock output serdes & buffer
-  
+
   ad_serdes_out #(
-    .SERDES_OR_DDR_N(1),
+    .DDR_OR_SDR_N(1),
     .DATA_WIDTH(1),
     .DEVICE_TYPE (DEVICE_TYPE))
   i_serdes_out_clk (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
+    .loaden (1'b0),
     .data_s0 (1'b1),
     .data_s1 (1'b0),
     .data_s2 (1'b1),

From 64cd7dc002909083dc7aa4bb9a3cd63b57e2a732 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 21 Sep 2016 16:09:55 +0300
Subject: [PATCH 505/972] axi_ad9122: Update core to the new DRP interface

---
 library/axi_ad9122/axi_ad9122.v         | 14 +++++-----
 library/axi_ad9122/axi_ad9122_channel.v | 20 +++++++-------
 library/axi_ad9122/axi_ad9122_core.v    |  4 +--
 library/axi_ad9122/axi_ad9122_if.v      | 35 ++++++++++++++-----------
 4 files changed, 39 insertions(+), 34 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v
index 69eb7d9f5..c20ceeb8d 100644
--- a/library/axi_ad9122/axi_ad9122.v
+++ b/library/axi_ad9122/axi_ad9122.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -187,8 +187,8 @@ module axi_ad9122 (
   wire            up_drp_sel_s;
   wire            up_drp_wr_s;
   wire    [11:0]  up_drp_addr_s;
-  wire    [15:0]  up_drp_wdata_s;
-  wire    [15:0]  up_drp_rdata_s;
+  wire    [31:0]  up_drp_wdata_s;
+  wire    [31:0]  up_drp_rdata_s;
   wire            up_drp_ready_s;
   wire            up_drp_locked_s;
   wire            up_wreq_s;
diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v
index 93bb5a3e8..d2bf47c45 100644
--- a/library/axi_ad9122/axi_ad9122_channel.v
+++ b/library/axi_ad9122/axi_ad9122_channel.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -197,7 +197,7 @@ module axi_ad9122_channel (
     .dds_data (dac_dds_data_0_s));
   end
   endgenerate
-  
+
   generate
   if (DATAPATH_DISABLE == 1) begin
   assign dac_dds_data_1_s = 16'd0;
@@ -212,7 +212,7 @@ module axi_ad9122_channel (
     .dds_data (dac_dds_data_1_s));
   end
   endgenerate
-  
+
   generate
   if (DATAPATH_DISABLE == 1) begin
   assign dac_dds_data_2_s = 16'd0;
@@ -227,7 +227,7 @@ module axi_ad9122_channel (
     .dds_data (dac_dds_data_2_s));
   end
   endgenerate
-  
+
   generate
   if (DATAPATH_DISABLE == 1) begin
   assign dac_dds_data_3_s = 16'd0;
@@ -242,7 +242,7 @@ module axi_ad9122_channel (
     .dds_data (dac_dds_data_3_s));
   end
   endgenerate
-  
+
   // single channel processor
 
   up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
@@ -284,7 +284,7 @@ module axi_ad9122_channel (
     .up_raddr (up_raddr),
     .up_rdata (up_rdata),
     .up_rack (up_rack));
-  
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v
index e3c91a1e9..fdc16674f 100644
--- a/library/axi_ad9122/axi_ad9122_core.v
+++ b/library/axi_ad9122/axi_ad9122_core.v
@@ -156,8 +156,8 @@ module axi_ad9122_core (
   output          up_drp_sel;
   output          up_drp_wr;
   output  [11:0]  up_drp_addr;
-  output  [15:0]  up_drp_wdata;
-  input   [15:0]  up_drp_rdata;
+  output  [31:0]  up_drp_wdata;
+  input   [31:0]  up_drp_rdata;
   input           up_drp_ready;
   input           up_drp_locked;
 
diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v
index 598978c47..7f5a64658 100644
--- a/library/axi_ad9122/axi_ad9122_if.v
+++ b/library/axi_ad9122/axi_ad9122_if.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -156,8 +156,8 @@ module axi_ad9122_if (
   input           up_drp_sel;
   input           up_drp_wr;
   input   [11:0]  up_drp_addr;
-  input   [15:0]  up_drp_wdata;
-  output  [15:0]  up_drp_rdata;
+  input   [31:0]  up_drp_wdata;
+  output  [31:0]  up_drp_rdata;
   output          up_drp_ready;
   output          up_drp_locked;
 
@@ -186,12 +186,13 @@ module axi_ad9122_if (
 
   ad_serdes_out #(
     .DEVICE_TYPE (DEVICE_TYPE),
-    .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
+    .DDR_OR_SDR_N (SERDES_OR_DDR_N),
     .DATA_WIDTH (16))
   i_serdes_out_data (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
+    .loaden (1'b0),
     .data_s0 (dac_data_i0),
     .data_s1 (dac_data_q0),
     .data_s2 (dac_data_i1),
@@ -204,15 +205,16 @@ module axi_ad9122_if (
     .data_out_n (dac_data_out_n));
 
   // dac frame output serdes & buffer
-  
+
   ad_serdes_out #(
     .DEVICE_TYPE (DEVICE_TYPE),
-    .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
+    .DDR_OR_SDR_N (SERDES_OR_DDR_N),
     .DATA_WIDTH (1))
   i_serdes_out_frame (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
+    .loaden (1'b0),
     .data_s0 (dac_frame_i0),
     .data_s1 (dac_frame_q0),
     .data_s2 (dac_frame_i1),
@@ -225,15 +227,16 @@ module axi_ad9122_if (
     .data_out_n (dac_frame_out_n));
 
   // dac clock output serdes & buffer
-  
+
   ad_serdes_out #(
     .DEVICE_TYPE (DEVICE_TYPE),
-    .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
+    .DDR_OR_SDR_N (SERDES_OR_DDR_N),
     .DATA_WIDTH (1))
   i_serdes_out_clk (
     .rst (dac_rst),
     .clk (dac_out_clk),
     .div_clk (dac_div_clk),
+    .loaden (1'b0),
     .data_s0 (1'b1),
     .data_s1 (1'b0),
     .data_s2 (1'b1),
@@ -248,21 +251,23 @@ module axi_ad9122_if (
   // dac clock input buffers
 
   ad_serdes_clk #(
-    .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
+    .DDR_OR_SDR_N (SERDES_OR_DDR_N),
     .MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N),
-    .MMCM_DEVICE_TYPE (DEVICE_TYPE),
+    .DEVICE_TYPE (DEVICE_TYPE),
     .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
     .MMCM_VCO_DIV (MMCM_VCO_DIV),
     .MMCM_VCO_MUL (MMCM_VCO_MUL),
     .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
     .MMCM_CLK1_DIV (MMCM_CLK1_DIV))
   i_serdes_clk (
-    .mmcm_rst (mmcm_rst),
+    .rst (mmcm_rst),
     .clk_in_p (dac_clk_in_p),
     .clk_in_n (dac_clk_in_n),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
     .out_clk (dac_out_clk),
+    .loaden (),
+    .phase (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),

From a21b9fe8ffce014942e363900f1c0d99d2f4b0c9 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 21 Sep 2016 17:55:58 +0300
Subject: [PATCH 506/972] up_drp: Fix up_drp_wr

---
 library/common/up_adc_common.v | 2 +-
 library/common/up_dac_common.v | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index bc6c7dda3..e47c99e68 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -248,7 +248,7 @@ module up_adc_common (
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_sel <= 1'b1;
-        up_drp_wr <= ~up_wdata[28];
+        up_drp_wr <= ~up_wdata[12];
       end else begin
         up_drp_sel <= 1'b0;
         up_drp_wr <= 1'b0;
diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index 02900c7b9..2966e14ae 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -269,7 +269,7 @@ module up_dac_common (
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_sel <= 1'b1;
-        up_drp_wr <= ~up_wdata[28];
+        up_drp_wr <= ~up_wdata[12];
       end else begin
         up_drp_sel <= 1'b0;
         up_drp_wr <= 1'b0;

From d497a7b0aebac5c4946de1091b8c3afbca364c94 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 19 Sep 2016 13:27:17 -0400
Subject: [PATCH 507/972] axi_xcvrlb- constraints

---
 library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc | 16 ++++++++++++++++
 library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl     |  2 ++
 2 files changed, 18 insertions(+)
 create mode 100644 library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc

diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc b/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc
new file mode 100644
index 000000000..bdc2b27e5
--- /dev/null
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc
@@ -0,0 +1,16 @@
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_rate*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_rate*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
+
+set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}]
+
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl b/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl
index c7c179d37..965d9a64b 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl
@@ -8,10 +8,12 @@ adi_ip_files axi_xcvrlb [list \
   "$ad_hdl_dir/library/common/up_xfer_status.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/up_axi.v" \
+  "axi_xcvrlb_constr.xdc" \
   "axi_xcvrlb_1.v" \
   "axi_xcvrlb.v" ]
 
 adi_ip_properties_lite axi_xcvrlb
+adi_ip_constraints axi_xcvrlb "axi_xcvrlb_constr.xdc"
 
 ipx::remove_all_bus_interface [ipx::current_core]
 

From 0def596b43a969f3e0be5fa9ed9da0557d7eda62 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Sep 2016 11:01:54 -0400
Subject: [PATCH 508/972] axi_xcvrlb- updates

---
 library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v        | 4 ++--
 library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc | 4 ----
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
index 9b0e383b4..3ddfbc829 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
@@ -135,7 +135,7 @@ module axi_xcvrlb_1 (
   // receive
 
   assign rx_status_s = ~(| rx_error_s);
-  assign rx_pn_data_s = (rx_pn_oos_s == 1'b1) ? rx_data_s : rx_pn_data;
+  assign rx_pn_data_s = (rx_pn_oos_s == 1'b1) ? rx_data : rx_pn_data;
 
   always @(posedge clk) begin
     if (rx_status_s == 1'b0) begin
@@ -243,7 +243,7 @@ module axi_xcvrlb_1 (
     .d_data_status ({rx_pn_err_s, rx_pn_oos_s}));
 
   util_adxcvr_xch #(
-    .XCVR_ID (15),
+    .XCVR_ID (0),
     .GTH_OR_GTX_N (0),
     .CPLL_TX_OR_RX_N (0),
     .CPLL_FBDIV (2),
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc b/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc
index bdc2b27e5..89ed37ca6 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc
@@ -1,13 +1,9 @@
 
-set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_rate*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_rate*}]
 set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}]
 set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
 set_property shreg_extract no [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
 set_property shreg_extract no [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
 
-set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}]
 set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
 set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
 set_false_path -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}]

From a2e60cf6939ea99287e5723dfcf2214ac9aa93f9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Sep 2016 11:02:49 -0400
Subject: [PATCH 509/972] ccbrk - test

---
 projects/pzsdr/common/ccbrk_bd.tcl | 176 ++++-------------------------
 1 file changed, 19 insertions(+), 157 deletions(-)

diff --git a/projects/pzsdr/common/ccbrk_bd.tcl b/projects/pzsdr/common/ccbrk_bd.tcl
index a91b0dafe..b4e3c00cd 100644
--- a/projects/pzsdr/common/ccbrk_bd.tcl
+++ b/projects/pzsdr/common/ccbrk_bd.tcl
@@ -6,186 +6,48 @@ ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
 
 # un-used io (gt)
 
-set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_pzslb_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_2 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_3 {3}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_pzslb_gt
-
-set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0]
-set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1]
-set util_pzslb_gtlb_2 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_2]
-set util_pzslb_gtlb_3 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_3]
-
-ad_cpu_interconnect 0x44A60000 axi_pzslb_gt
-ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi
+set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_pz_xcvrlb
 
 create_bd_port -dir I gt_ref_clk
-create_bd_port -dir I gt_rx_0_p
-create_bd_port -dir I gt_rx_0_n
-create_bd_port -dir O gt_tx_0_p
-create_bd_port -dir O gt_tx_0_n
-create_bd_port -dir I gt_rx_1_p
-create_bd_port -dir I gt_rx_1_n
-create_bd_port -dir O gt_tx_1_p
-create_bd_port -dir O gt_tx_1_n
-create_bd_port -dir I gt_rx_2_p
-create_bd_port -dir I gt_rx_2_n
-create_bd_port -dir O gt_tx_2_p
-create_bd_port -dir O gt_tx_2_n
-create_bd_port -dir I gt_rx_3_p
-create_bd_port -dir I gt_rx_3_n
-create_bd_port -dir O gt_tx_3_p
-create_bd_port -dir O gt_tx_3_n
+create_bd_port -dir I -from 3 -to 0 gt_rx_p
+create_bd_port -dir I -from 3 -to 0 gt_rx_n
+create_bd_port -dir O -from 3 -to 0 gt_tx_p
+create_bd_port -dir O -from 3 -to 0 gt_tx_n
 
-ad_connect  sys_cpu_clk util_pzslb_gtlb_0/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_0/up_rstn
-ad_connect  util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_0/rx_p gt_rx_0_p
-ad_connect  util_pzslb_gtlb_0/rx_n gt_rx_0_n
-ad_connect  util_pzslb_gtlb_0/tx_p gt_tx_0_p
-ad_connect  util_pzslb_gtlb_0/tx_n gt_tx_0_n
-ad_connect  sys_cpu_clk util_pzslb_gtlb_1/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_1/up_rstn
-ad_connect  util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_1/rx_p gt_rx_1_p
-ad_connect  util_pzslb_gtlb_1/rx_n gt_rx_1_n
-ad_connect  util_pzslb_gtlb_1/tx_p gt_tx_1_p
-ad_connect  util_pzslb_gtlb_1/tx_n gt_tx_1_n
-ad_connect  sys_cpu_clk util_pzslb_gtlb_2/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_2/up_rstn
-ad_connect  util_pzslb_gtlb_2/qpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_2/cpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_2/rx_p gt_rx_2_p
-ad_connect  util_pzslb_gtlb_2/rx_n gt_rx_2_n
-ad_connect  util_pzslb_gtlb_2/tx_p gt_tx_2_p
-ad_connect  util_pzslb_gtlb_2/tx_n gt_tx_2_n
-ad_connect  sys_cpu_clk util_pzslb_gtlb_3/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_3/up_rstn
-ad_connect  util_pzslb_gtlb_3/qpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_3/cpll_ref_clk gt_ref_clk
-ad_connect  util_pzslb_gtlb_3/rx_p gt_rx_3_p
-ad_connect  util_pzslb_gtlb_3/rx_n gt_rx_3_n
-ad_connect  util_pzslb_gtlb_3/tx_p gt_tx_3_p
-ad_connect  util_pzslb_gtlb_3/tx_n gt_tx_3_n
-ad_connect  axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0
-ad_connect  axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0 
-ad_connect  axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0 
-ad_connect  axi_pzslb_gt/gt_pll_2 util_pzslb_gtlb_2/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_2 util_pzslb_gtlb_2/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_2 util_pzslb_gtlb_2/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_2 util_pzslb_gtlb_2/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_2 util_pzslb_gtlb_2/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_2 util_pzslb_gtlb_2/rx_gt_comma_align_enb_0 
-ad_connect  axi_pzslb_gt/gt_pll_3 util_pzslb_gtlb_3/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_3 util_pzslb_gtlb_3/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_3 util_pzslb_gtlb_3/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_3 util_pzslb_gtlb_3/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_3 util_pzslb_gtlb_3/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_3 util_pzslb_gtlb_3/rx_gt_comma_align_enb_0 
+ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb
+ad_connect  axi_pz_xcvrlb/ref_clk gt_ref_clk
+ad_connect  axi_pz_xcvrlb/rx_p gt_rx_p
+ad_connect  axi_pz_xcvrlb/rx_n gt_rx_n
+ad_connect  axi_pz_xcvrlb/tx_p gt_tx_p
+ad_connect  axi_pz_xcvrlb/tx_n gt_tx_n
 
 # un-used io (regular)
 
 set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
-set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_0 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_1 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_2 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_5 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg
-set_property -dict [list CONFIG.NUM_OF_IO {7}] $axi_gpreg
-
-ad_cpu_interconnect 0x41200000 axi_gpreg
-
-ad_connect  util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_0
-ad_connect  util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_1
-ad_connect  util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_2
-ad_connect  util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_3
-ad_connect  util_pzslb_gtlb_2/rx_clk axi_gpreg/d_clk_4
-ad_connect  util_pzslb_gtlb_2/tx_clk axi_gpreg/d_clk_5
-ad_connect  util_pzslb_gtlb_3/rx_clk axi_gpreg/d_clk_6
-ad_connect  util_pzslb_gtlb_3/tx_clk axi_gpreg/d_clk_7
+set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg
 
 create_bd_port -dir I -from 31 -to 0 gp_in_0
 create_bd_port -dir I -from 31 -to 0 gp_in_1
 create_bd_port -dir I -from 31 -to 0 gp_in_2
+create_bd_port -dir I -from 31 -to 0 gp_in_3
 create_bd_port -dir O -from 31 -to 0 gp_out_0
 create_bd_port -dir O -from 31 -to 0 gp_out_1
 create_bd_port -dir O -from 31 -to 0 gp_out_2
+create_bd_port -dir O -from 31 -to 0 gp_out_3
 
 ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
 ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
 ad_connect  gp_in_2 axi_gpreg/up_gp_in_2
+ad_connect  gp_in_3 axi_gpreg/up_gp_in_3
 ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
 ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
 ad_connect  gp_out_2 axi_gpreg/up_gp_out_2
-ad_connect  axi_gpreg/up_gp_in_3 util_pzslb_gtlb_0/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_3 util_pzslb_gtlb_0/up_gp_in
-ad_connect  axi_gpreg/up_gp_in_4 util_pzslb_gtlb_1/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_4 util_pzslb_gtlb_1/up_gp_in
-ad_connect  axi_gpreg/up_gp_in_5 util_pzslb_gtlb_2/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_5 util_pzslb_gtlb_2/up_gp_in
-ad_connect  axi_gpreg/up_gp_in_6 util_pzslb_gtlb_3/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_6 util_pzslb_gtlb_3/up_gp_in
+ad_connect  gp_out_3 axi_gpreg/up_gp_out_3
+ad_cpu_interconnect 0x41200000 axi_gpreg
 
 ## temporary (remove ila indirectly)
 
 delete_bd_objs [get_bd_cells ila_adc]
-delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
 

From 79f34c9de79def90800192c9d9c7de44cb4f1ad4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Sep 2016 11:03:21 -0400
Subject: [PATCH 510/972] ccbrk- test updates

---
 projects/pzsdr/ccbrk/Makefile           |   9 +-
 projects/pzsdr/ccbrk/system_constr.xdc  |  42 ++---
 projects/pzsdr/ccbrk/system_project.tcl |   7 +-
 projects/pzsdr/ccbrk/system_top.v       | 223 ++++++++----------------
 4 files changed, 90 insertions(+), 191 deletions(-)

diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile
index 41615cbcf..1ee659550 100644
--- a/projects/pzsdr/ccbrk/Makefile
+++ b/projects/pzsdr/ccbrk/Makefile
@@ -24,9 +24,8 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -61,9 +60,8 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_gpreg clean
-	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/xilinx/axi_xcvrlb clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_gtlb clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -78,9 +76,8 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_gpreg
-	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/xilinx/axi_xcvrlb
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_gtlb
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr/ccbrk/system_constr.xdc b/projects/pzsdr/ccbrk/system_constr.xdc
index 05083fdc9..ca0b31e54 100644
--- a/projects/pzsdr/ccbrk/system_constr.xdc
+++ b/projects/pzsdr/ccbrk/system_constr.xdc
@@ -1,6 +1,6 @@
 
 ## constraints
-## loopback
+## loopback (P2/P13 are pin swapped on board - so skip gp_*[65]) 
 ## p4
 
 set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33              
@@ -220,39 +220,19 @@ set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]
 set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111              
 set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111              
 
-## clocks
-
-create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-
-## MIO loopbacks (fixed-io)
-## the following are connected to AD9361 GPIO
-
-##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
-##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
-##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
-##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
-
-## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
-
-##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
-
-## the following are mio-to-pl loopback
-
-##  JX4.97    E26   PS_MIO00_500_JX4    <==>  JX1.76    K3    IO_L11N_T1_SRCC_33        
-##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
-##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
-##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
+## mio
 
 set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33        
 set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34             
 set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34              
 set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34             
 
+## clocks
+
+create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
+create_clock -name xcvr_clk_0   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+create_clock -name xcvr_clk_1   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+create_clock -name xcvr_clk_2   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[2].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+create_clock -name xcvr_clk_3   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[3].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+
+
diff --git a/projects/pzsdr/ccbrk/system_project.tcl b/projects/pzsdr/ccbrk/system_project.tcl
index 1aabab6f4..fe13d542f 100644
--- a/projects/pzsdr/ccbrk/system_project.tcl
+++ b/projects/pzsdr/ccbrk/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl 
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
@@ -14,10 +12,7 @@ adi_project_files ccbrk_pzsdr [list \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
+set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run ccbrk_pzsdr
 
 
diff --git a/projects/pzsdr/ccbrk/system_top.v b/projects/pzsdr/ccbrk/system_top.v
index 585b2022d..c3d296b81 100644
--- a/projects/pzsdr/ccbrk/system_top.v
+++ b/projects/pzsdr/ccbrk/system_top.v
@@ -39,147 +39,79 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  gpio_bd,
+  inout   [11:0]  gpio_bd,
 
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
 
-  enable,
-  txnrx,
-  clk_out,
+  output          enable,
+  output          txnrx,
+  input           clk_out,
 
-  gpio_clksel,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso,
 
-  gp_out,
-  gp_in,
-  gp_in_mio,
-  gp_in_1,
+  output  [87:0]  gp_out,
+  input   [87:0]  gp_in,
+  input   [ 3:0]  gp_in_mio,
+  input           gp_in_1,
 
-  gt_ref_clk_p,
-  gt_ref_clk_n,
-  gt_tx_p,
-  gt_tx_n,
-  gt_rx_p,
-  gt_rx_n);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  inout   [11:0]  gpio_bd;
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  output          enable;
-  output          txnrx;
-  input           clk_out;
-
-  inout           gpio_clksel;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
-
-  output  [87:0]  gp_out;
-  input   [87:0]  gp_in;
-  input   [ 3:0]  gp_in_mio;
-  input           gp_in_1;
-
-  input           gt_ref_clk_p;
-  input           gt_ref_clk_n;
-  output  [ 3:0]  gt_tx_p;
-  output  [ 3:0]  gt_tx_n;
-  input   [ 3:0]  gt_rx_p;
-  input   [ 3:0]  gt_rx_n;
+  input           gt_ref_clk_p,
+  input           gt_ref_clk_n,
+  output  [ 3:0]  gt_tx_p,
+  output  [ 3:0]  gt_tx_n,
+  input   [ 3:0]  gt_rx_p,
+  input   [ 3:0]  gt_rx_n);
 
   // internal signals
 
   wire            gt_ref_clk;
+  wire    [31:0]  gp_misc_s;
   wire    [95:0]  gp_out_s;
   wire    [95:0]  gp_in_s;
   wire    [63:0]  gpio_i;
@@ -192,10 +124,15 @@ module system_top (
   assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
   assign gp_out[41: 0] = gp_out_s[41: 0];
 
-  assign gp_in_s[95:93] = 3'd0;
-  assign gp_in_s[92:92] = gp_in_1;
-  assign gp_in_s[91:88] = gp_in_mio;
-  assign gp_in_s[87: 0] = gp_in;
+  assign gp_in_s[95:88] = gp_out_s[95:88];
+  assign gp_in_s[87:66] = gp_in[87:66];
+  assign gp_in_s[65:65] = gp_out_s[65];
+  assign gp_in_s[64: 0] = gp_in[64:0];
+
+  assign gp_misc_s[31: 9] = 23'd0;
+  assign gp_misc_s[ 8: 8] = gp_in_1;
+  assign gp_misc_s[ 7: 4] = 4'd0;
+  assign gp_misc_s[ 3: 0] = gp_in_mio;
 
   // instantiations
 
@@ -249,29 +186,19 @@ module system_top (
     .gp_in_0 (gp_in_s[31:0]),
     .gp_in_1 (gp_in_s[63:32]),
     .gp_in_2 (gp_in_s[95:64]),
+    .gp_in_3 (gp_misc_s),
     .gp_out_0 (gp_out_s[31:0]),
     .gp_out_1 (gp_out_s[63:32]),
     .gp_out_2 (gp_out_s[95:64]),
+    .gp_out_3 (),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
     .gt_ref_clk (gt_ref_clk),
-    .gt_rx_0_n (gt_rx_n[0]),
-    .gt_rx_0_p (gt_rx_p[0]),
-    .gt_rx_1_n (gt_rx_n[1]),
-    .gt_rx_1_p (gt_rx_p[1]),
-    .gt_rx_2_n (gt_rx_n[2]),
-    .gt_rx_2_p (gt_rx_p[2]),
-    .gt_rx_3_n (gt_rx_n[3]),
-    .gt_rx_3_p (gt_rx_p[3]),
-    .gt_tx_0_n (gt_tx_n[0]),
-    .gt_tx_0_p (gt_tx_p[0]),
-    .gt_tx_1_n (gt_tx_n[1]),
-    .gt_tx_1_p (gt_tx_p[1]),
-    .gt_tx_2_n (gt_tx_n[2]),
-    .gt_tx_2_p (gt_tx_p[2]),
-    .gt_tx_3_n (gt_tx_n[3]),
-    .gt_tx_3_p (gt_tx_p[3]),
+    .gt_rx_n (gt_rx_n),
+    .gt_rx_p (gt_rx_p),
+    .gt_tx_n (gt_tx_n),
+    .gt_tx_p (gt_tx_p),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),

From 500d8bfb9033c24b773f33c0c065eba9829c87ef Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 21 Sep 2016 18:11:35 +0300
Subject: [PATCH 511/972] adrv9371x: A10GX, fix makefile and system_qsys.tcl
 script

---
 projects/adrv9371x/a10gx/Makefile        | 17 -----------------
 projects/adrv9371x/a10gx/system_qsys.tcl |  1 -
 2 files changed, 18 deletions(-)

diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile
index 67daaba73..6971a502c 100644
--- a/projects/adrv9371x/a10gx/Makefile
+++ b/projects/adrv9371x/a10gx/Makefile
@@ -21,23 +21,6 @@ M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
-M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
-M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
-M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
-M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
-M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
-M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
-M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
-M_DEPS += ../../../library/altera_iopll/altera_iopll_hw.tcl
-M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
-M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
-M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
-M_DEPS += ../../../library/altera_pll_reconfig/altera_pll_reconfig_hw.tcl
-M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
-M_DEPS += ../../../library/altera_xcvr_atx_pll_a10/altera_xcvr_atx_pll_a10_hw.tcl
-M_DEPS += ../../../library/altera_xcvr_reset_control/altera_xcvr_reset_control_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v
diff --git a/projects/adrv9371x/a10gx/system_qsys.tcl b/projects/adrv9371x/a10gx/system_qsys.tcl
index 0af153b03..755fe771c 100644
--- a/projects/adrv9371x/a10gx/system_qsys.tcl
+++ b/projects/adrv9371x/a10gx/system_qsys.tcl
@@ -1,6 +1,5 @@
 
 
-source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/adrv9371x_qsys.tcl
 

From 143423e3b9de321e1b0dfa98ef6a0ef6cd1bfc28 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 21 Sep 2016 18:13:02 +0300
Subject: [PATCH 512/972] adrv9371x: A10SOC, fix Makefile and system scripts to
 be compatible with altera

---
 projects/adrv9371x/a10soc/Makefile            | 10 --------
 projects/adrv9371x/a10soc/system_qsys.tcl     |  1 -
 .../common/a10soc/a10soc_system_assign.tcl    | 25 ++-----------------
 3 files changed, 2 insertions(+), 34 deletions(-)

diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 29443506c..74abe24c5 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -21,16 +21,6 @@ M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
-M_DEPS += ../../../library/altera_arria10_hps/altera_arria10_hps_hw.tcl
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
-M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
-M_DEPS += ../../../library/altera_emif_a10_hps/altera_emif_a10_hps_hw.tcl
-M_DEPS += ../../../library/altera_iopll/altera_iopll_hw.tcl
-M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
-M_DEPS += ../../../library/altera_pll_reconfig/altera_pll_reconfig_hw.tcl
-M_DEPS += ../../../library/altera_xcvr_atx_pll_a10/altera_xcvr_atx_pll_a10_hw.tcl
-M_DEPS += ../../../library/altera_xcvr_reset_control/altera_xcvr_reset_control_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v
diff --git a/projects/adrv9371x/a10soc/system_qsys.tcl b/projects/adrv9371x/a10soc/system_qsys.tcl
index b34fcb1a6..2b861df8a 100644
--- a/projects/adrv9371x/a10soc/system_qsys.tcl
+++ b/projects/adrv9371x/a10soc/system_qsys.tcl
@@ -1,6 +1,5 @@
 
 
-source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
 source ../common/adrv9371x_qsys.tcl
 
diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
index f39acc047..8ad011f59 100755
--- a/projects/common/a10soc/a10soc_system_assign.tcl
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -264,27 +264,6 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
 set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
-# set libraries
+# source defaults
 
-set ad_lib_folders "$ad_hdl_dir/library/**/*;$ad_phdl_dir/library/**/*"
-
-set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
-set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
-
-# generate qsys
-# move this to a project script
-
-set mmu_enabled 1
-if [info exists ::env(ALT_NIOS_MMU_ENABLED)] {
-  set mmu_enabled $::env(ALT_NIOS_MMU_ENABLED)
-}
-
-if {$mmu_enabled == 0} {
-  set cmd_str "set mmu_enabled 0"
-  exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
-    --cmd=$cmd_str --script=system_qsys.tcl
-} else {
-  set cmd_str "set mmu_enabled 1"
-  exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
-    --cmd=$cmd_str --script=system_qsys.tcl
-}
+source $ad_hdl_dir/projects/common/altera/sys_gen.tcl

From 21b5e9c6340e6c1969964691ec0129d7272a5f00 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Sep 2016 11:56:03 -0400
Subject: [PATCH 513/972] hdlmake- updates

---
 library/Makefile                   | 2 ++
 library/xilinx/axi_xcvrlb/Makefile | 1 +
 projects/pzsdr/ccbrk_cmos/Makefile | 9 +++------
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/library/Makefile b/library/Makefile
index 0ab77fac5..358764b35 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -74,6 +74,7 @@ clean:
 	make -C xilinx/axi_adcfifo clean
 	make -C xilinx/axi_adxcvr clean
 	make -C xilinx/axi_dacfifo clean
+	make -C xilinx/axi_xcvrlb clean
 	make -C xilinx/util_adxcvr clean
 
 
@@ -145,6 +146,7 @@ lib:
 	-make -C xilinx/axi_adcfifo
 	-make -C xilinx/axi_adxcvr
 	-make -C xilinx/axi_dacfifo
+	-make -C xilinx/axi_xcvrlb
 	-make -C xilinx/util_adxcvr
 
 ####################################################################################
diff --git a/library/xilinx/axi_xcvrlb/Makefile b/library/xilinx/axi_xcvrlb/Makefile
index 3baba09b3..8cad2cac1 100644
--- a/library/xilinx/axi_xcvrlb/Makefile
+++ b/library/xilinx/axi_xcvrlb/Makefile
@@ -12,6 +12,7 @@ M_DEPS += ../../xilinx/util_adxcvr/util_adxcvr_xch.v
 M_DEPS += ../../common/up_xfer_status.v
 M_DEPS += ../../common/ad_pnmon.v
 M_DEPS += ../../common/up_axi.v
+M_DEPS += axi_xcvrlb_constr.xdc
 M_DEPS += axi_xcvrlb_1.v
 M_DEPS += axi_xcvrlb.v
 
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
index bfb0de681..b89aaf1d3 100644
--- a/projects/pzsdr/ccbrk_cmos/Makefile
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -24,9 +24,8 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -61,9 +60,8 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_gpreg clean
-	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/xilinx/axi_xcvrlb clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_gtlb clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -78,9 +76,8 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_gpreg
-	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/xilinx/axi_xcvrlb
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_gtlb
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo

From 14ad1ea74190a77daaff7a7a8f87000acf5d182f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Sep 2016 13:15:40 -0400
Subject: [PATCH 514/972] pzsdr- swap clear-up

---
 projects/common/pzsdr/pzsdr_cmos_system_constr.xdc   | 2 +-
 projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
index 3a1144c80..35d05f7b9 100644
--- a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
+++ b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
@@ -1,6 +1,6 @@
 
 # constraints
-# ad9361
+# ad9361 (SWAP == 0x1)
 
 set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports rx_clk_in]       ; ## IO_L12P_T1_MRCC_35
 set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18} [get_ports rx_frame_in]     ; ## IO_L7P_T1_AD2P_35
diff --git a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
index 8ee340902..72876707c 100644
--- a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
+++ b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
@@ -1,6 +1,6 @@
 
 # constraints
-# ad9361
+# ad9361 (SWAP == 0x0)
 
 set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVCMOS25} [get_ports rx_clk_in]                         ; ## IO_L12P_T1_MRCC_35
 set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVCMOS25} [get_ports rx_frame_in]                       ; ## IO_L7P_T1_AD2P_35
@@ -34,6 +34,7 @@ set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVCMOS25} [get_ports tx_data_o
 
 set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVCMOS25} [get_ports tx_gnd[0]]                         ; ## IO_L8N_T1_AD10N_35
 set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVCMOS25} [get_ports tx_gnd[1]]                         ; ## IO_L9N_T1_DQS_AD3N_35
+
 # clocks
 
 create_clock -name rx_clk       -period  8 [get_ports rx_clk_in]

From 0e2572bbd871ba15833f51fa6d85bf2c3c0b0e7c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Sep 2016 13:16:04 -0400
Subject: [PATCH 515/972] pzsdr- ccbrk_cmos- loopback changes

---
 projects/pzsdr/ccbrk_cmos/system_project.tcl |   3 +-
 projects/pzsdr/ccbrk_cmos/system_top.v       | 208 +++++++------------
 2 files changed, 71 insertions(+), 140 deletions(-)

diff --git a/projects/pzsdr/ccbrk_cmos/system_project.tcl b/projects/pzsdr/ccbrk_cmos/system_project.tcl
index fc22d310b..5f0c51de7 100644
--- a/projects/pzsdr/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr/ccbrk_cmos/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl 
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
@@ -14,6 +12,7 @@ adi_project_files ccbrk_cmos_pzsdr [list \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run ccbrk_cmos_pzsdr
 
 
diff --git a/projects/pzsdr/ccbrk_cmos/system_top.v b/projects/pzsdr/ccbrk_cmos/system_top.v
index a45ae66eb..4e99e5daf 100644
--- a/projects/pzsdr/ccbrk_cmos/system_top.v
+++ b/projects/pzsdr/ccbrk_cmos/system_top.v
@@ -39,137 +39,74 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  gpio_bd,
+  inout   [11:0]  gpio_bd,
 
-  rx_clk_in,
-  rx_frame_in,
-  rx_data_in,
-  tx_clk_out,
-  tx_frame_out,
-  tx_data_out,
-  tx_gnd,
+  input           rx_clk_in,
+  input           rx_frame_in,
+  input   [11:0]  rx_data_in,
+  output          tx_clk_out,
+  output          tx_frame_out,
+  output  [11:0]  tx_data_out,
+  output  [ 1:0]  tx_gnd,
 
-  enable,
-  txnrx,
-  clk_out,
+  output          enable,
+  output          txnrx,
+  input           clk_out,
 
-  gpio_clksel,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso,
 
-  gp_out,
-  gp_in,
-  gp_in_mio,
-  gp_in_1,
+  output  [87:0]  gp_out,
+  input   [87:0]  gp_in,
+  input   [ 3:0]  gp_in_mio,
+  input           gp_in_1,
 
-  gt_ref_clk_p,
-  gt_ref_clk_n,
-  gt_tx_p,
-  gt_tx_n,
-  gt_rx_p,
-  gt_rx_n);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  inout   [11:0]  gpio_bd;
-
-  input           rx_clk_in;
-  input           rx_frame_in;
-  input   [11:0]  rx_data_in;
-  output          tx_clk_out;
-  output          tx_frame_out;
-  output  [11:0]  tx_data_out;
-  output  [ 1:0]  tx_gnd;
-
-  output          enable;
-  output          txnrx;
-  input           clk_out;
-
-  inout           gpio_clksel;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
-
-  output  [87:0]  gp_out;
-  input   [87:0]  gp_in;
-  input   [ 3:0]  gp_in_mio;
-  input           gp_in_1;
-
-  input           gt_ref_clk_p;
-  input           gt_ref_clk_n;
-  output  [ 3:0]  gt_tx_p;
-  output  [ 3:0]  gt_tx_n;
-  input   [ 3:0]  gt_rx_p;
-  input   [ 3:0]  gt_rx_n;
+  input           gt_ref_clk_p,
+  input           gt_ref_clk_n,
+  output  [ 3:0]  gt_tx_p,
+  output  [ 3:0]  gt_tx_n,
+  input   [ 3:0]  gt_rx_p,
+  input   [ 3:0]  gt_rx_n);
 
   // internal signals
 
   wire            gt_ref_clk;
+  wire    [31:0]  gp_misc_s;
   wire    [95:0]  gp_out_s;
   wire    [95:0]  gp_in_s;
   wire    [63:0]  gpio_i;
@@ -184,10 +121,15 @@ module system_top (
   assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
   assign gp_out[41: 0] = gp_out_s[41: 0];
 
-  assign gp_in_s[95:93] = 3'd0;
-  assign gp_in_s[92:92] = gp_in_1;
-  assign gp_in_s[91:88] = gp_in_mio;
-  assign gp_in_s[87: 0] = gp_in;
+  assign gp_in_s[95:88] = gp_out_s[95:88];
+  assign gp_in_s[87:66] = gp_in[87:66];
+  assign gp_in_s[65:65] = gp_out_s[65];
+  assign gp_in_s[64: 0] = gp_in[64:0];
+
+  assign gp_misc_s[31: 9] = 23'd0;
+  assign gp_misc_s[ 8: 8] = gp_in_1;
+  assign gp_misc_s[ 7: 4] = 4'd0;
+  assign gp_misc_s[ 3: 0] = gp_in_mio;
 
   // instantiations
 
@@ -241,29 +183,19 @@ module system_top (
     .gp_in_0 (gp_in_s[31:0]),
     .gp_in_1 (gp_in_s[63:32]),
     .gp_in_2 (gp_in_s[95:64]),
+    .gp_in_3 (gp_misc_s),
     .gp_out_0 (gp_out_s[31:0]),
     .gp_out_1 (gp_out_s[63:32]),
     .gp_out_2 (gp_out_s[95:64]),
+    .gp_out_3 (),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
     .gt_ref_clk (gt_ref_clk),
-    .gt_rx_0_n (gt_rx_n[0]),
-    .gt_rx_0_p (gt_rx_p[0]),
-    .gt_rx_1_n (gt_rx_n[1]),
-    .gt_rx_1_p (gt_rx_p[1]),
-    .gt_rx_2_n (gt_rx_n[2]),
-    .gt_rx_2_p (gt_rx_p[2]),
-    .gt_rx_3_n (gt_rx_n[3]),
-    .gt_rx_3_p (gt_rx_p[3]),
-    .gt_tx_0_n (gt_tx_n[0]),
-    .gt_tx_0_p (gt_tx_p[0]),
-    .gt_tx_1_n (gt_tx_n[1]),
-    .gt_tx_1_p (gt_tx_p[1]),
-    .gt_tx_2_n (gt_tx_n[2]),
-    .gt_tx_2_p (gt_tx_p[2]),
-    .gt_tx_3_n (gt_tx_n[3]),
-    .gt_tx_3_p (gt_tx_p[3]),
+    .gt_rx_n (gt_rx_n),
+    .gt_rx_p (gt_rx_p),
+    .gt_tx_n (gt_tx_n),
+    .gt_tx_p (gt_tx_p),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),

From 2b6eb1d65ef1ba29867eda811ee23d8a1a343699 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 22 Sep 2016 16:28:44 +0300
Subject: [PATCH 516/972] up_drp: Revert some bit locations

Linuxe drivers are checking the drp_locked status even if the
core does not contains a clock generation/managment module. To
not break all the designs, revert all the status and control bits to
there old locations.
---
 library/common/up_adc_common.v | 10 +++++-----
 library/common/up_dac_common.v | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index e47c99e68..787b727ea 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -248,7 +248,7 @@ module up_adc_common (
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_sel <= 1'b1;
-        up_drp_wr <= ~up_wdata[12];
+        up_drp_wr <= ~up_wdata[28];
       end else begin
         up_drp_sel <= 1'b0;
         up_drp_wr <= 1'b0;
@@ -259,8 +259,8 @@ module up_adc_common (
         up_drp_status <= 1'b0;
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
-        up_drp_rwn <= up_wdata[12];
-        up_drp_addr <= up_wdata[11:0];
+        up_drp_rwn <= up_wdata[28];
+        up_drp_addr <= up_wdata[27:16];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
         up_drp_wdata <= up_wdata;
@@ -309,8 +309,8 @@ module up_adc_common (
           8'h16: up_rdata <= adc_clk_ratio;
           8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
           8'h1a: up_rdata <= {31'd0, up_sync_status_s};
-          8'h1c: up_rdata <= {19'd0, up_drp_rwn, up_drp_addr};
-          8'h1d: up_rdata <= {30'd0, up_drp_locked, up_drp_status};
+          8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, 16'b0};
+          8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, 16'b0};
           8'h1e: up_rdata <= up_drp_wdata;
           8'h1f: up_rdata <= up_drp_rdata_hold;
           8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index 2966e14ae..a15349e6b 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -269,7 +269,7 @@ module up_dac_common (
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_sel <= 1'b1;
-        up_drp_wr <= ~up_wdata[12];
+        up_drp_wr <= ~up_wdata[28];
       end else begin
         up_drp_sel <= 1'b0;
         up_drp_wr <= 1'b0;
@@ -280,8 +280,8 @@ module up_dac_common (
         up_drp_status <= 1'b0;
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
-        up_drp_rwn <= up_wdata[12];
-        up_drp_addr <= up_wdata[11:0];
+        up_drp_rwn <= up_wdata[28];
+        up_drp_addr <= up_wdata[27:16];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
         up_drp_wdata <= up_wdata;
@@ -331,8 +331,8 @@ module up_dac_common (
           8'h16: up_rdata <= dac_clk_ratio;
           8'h17: up_rdata <= {31'd0, up_status_s};
           8'h18: up_rdata <= {31'd0, up_dac_clksel};
-          8'h1c: up_rdata <= {19'd0, up_drp_rwn, up_drp_addr};
-          8'h1d: up_rdata <= {30'd0, up_drp_locked, up_drp_status};
+          8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, 16'b0};
+          8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, 16'b0};
           8'h1e: up_rdata <= up_drp_wdata;
           8'h1f: up_rdata <= up_drp_rdata_hold;
           8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};

From dc6f7bbc4e49a87f9f88821dc7035b69790a2f80 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 22 Sep 2016 11:17:42 -0400
Subject: [PATCH 517/972] pzsdr/ccfmc - loopback updates

---
 projects/pzsdr/ccfmc/Makefile           |   9 +-
 projects/pzsdr/ccfmc/system_constr.xdc  | 395 +++++++++++-----------
 projects/pzsdr/ccfmc/system_project.tcl |   6 -
 projects/pzsdr/ccfmc/system_top.v       | 431 ++++++++----------------
 projects/pzsdr/common/ccfmc_bd.tcl      | 130 ++-----
 5 files changed, 382 insertions(+), 589 deletions(-)

diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile
index 3d51c29c6..09dac0fe2 100644
--- a/projects/pzsdr/ccfmc/Makefile
+++ b/projects/pzsdr/ccfmc/Makefile
@@ -27,10 +27,9 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -68,10 +67,9 @@ clean-all:clean
 	make -C ../../../library/axi_gpreg clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_i2s_adi clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/axi_xcvrlb clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_gtlb clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -89,10 +87,9 @@ lib:
 	make -C ../../../library/axi_gpreg
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_i2s_adi
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/axi_xcvrlb
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_gtlb
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr/ccfmc/system_constr.xdc b/projects/pzsdr/ccfmc/system_constr.xdc
index 8ddea307b..eb0702fb3 100644
--- a/projects/pzsdr/ccfmc/system_constr.xdc
+++ b/projects/pzsdr/ccfmc/system_constr.xdc
@@ -1,77 +1,77 @@
 
 # rf-board
 
-set_property  -dict {PACKAGE_PIN  K10  IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable]              ; ## IO_25_VRP_34
-set_property  -dict {PACKAGE_PIN  AA20 IOSTANDARD LVCMOS25} [get_ports gpio_rf0]                       ; ## IO_L20_13_JX2_P
-set_property  -dict {PACKAGE_PIN  AB20 IOSTANDARD LVCMOS25} [get_ports gpio_rf1]                       ; ## IO_L20_13_JX2_N
-set_property  -dict {PACKAGE_PIN  AA14 IOSTANDARD LVCMOS25} [get_ports gpio_rf2]                       ; ## IO_L22_12_JX2_N
-set_property  -dict {PACKAGE_PIN  J9   IOSTANDARD LVCMOS18} [get_ports gpio_rf3]                       ; ## IO_L05_34_JX4_N
+set_property  -dict {PACKAGE_PIN  K10  IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable]             ; ## IO_25_VRP_34
+set_property  -dict {PACKAGE_PIN  AA20 IOSTANDARD LVCMOS25} [get_ports gpio_rf0]                      ; ## IO_L20_13_JX2_P
+set_property  -dict {PACKAGE_PIN  AB20 IOSTANDARD LVCMOS25} [get_ports gpio_rf1]                      ; ## IO_L20_13_JX2_N
+set_property  -dict {PACKAGE_PIN  AA14 IOSTANDARD LVCMOS25} [get_ports gpio_rf2]                      ; ## IO_L22_12_JX2_N
+set_property  -dict {PACKAGE_PIN  J9   IOSTANDARD LVCMOS18} [get_ports gpio_rf3]                      ; ## IO_L05_34_JX4_N
 
 # ethernet-1
 
-set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD LVCMOS18} [get_ports eth1_mdc]                      ; ## IO_L16P_T2_34      
-set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD LVCMOS18} [get_ports eth1_mdio]                     ; ## IO_L16N_T2_34      
-set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk]              ; ## IO_L12P_T1_MRCC_34 
-set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl]              ; ## IO_L12N_T1_MRCC_34 
-set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]]          ; ## IO_L10P_T1_34      
-set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]]          ; ## IO_L10N_T1_34      
-set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]]          ; ## IO_L11P_T1_SRCC_34 
-set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]]          ; ## IO_L11N_T1_SRCC_34 
-set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk]              ; ## IO_L13P_T2_MRCC_34 
-set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl]              ; ## IO_L13N_T2_MRCC_34 
-set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]]          ; ## IO_L14P_T2_SRCC_34 
-set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]]          ; ## IO_L14N_T2_SRCC_34 
-set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]]          ; ## IO_L15P_T2_DQS_34  
-set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]]          ; ## IO_L15N_T2_DQS_34  
+set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD LVCMOS18} [get_ports eth1_mdc]                     ; ## IO_L16P_T2_34      
+set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD LVCMOS18} [get_ports eth1_mdio]                    ; ## IO_L16N_T2_34      
+set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk]             ; ## IO_L12P_T1_MRCC_34 
+set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl]             ; ## IO_L12N_T1_MRCC_34 
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]]         ; ## IO_L10P_T1_34      
+set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]]         ; ## IO_L10N_T1_34      
+set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]]         ; ## IO_L11P_T1_SRCC_34 
+set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]]         ; ## IO_L11N_T1_SRCC_34 
+set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk]             ; ## IO_L13P_T2_MRCC_34 
+set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl]             ; ## IO_L13N_T2_MRCC_34 
+set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]]         ; ## IO_L14P_T2_SRCC_34 
+set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]]         ; ## IO_L14N_T2_SRCC_34 
+set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]]         ; ## IO_L15P_T2_DQS_34  
+set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]]         ; ## IO_L15N_T2_DQS_34  
 
 # hdmi
 
-set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD LVCMOS18}             [get_ports hdmi_out_clk]      ; ## IO_L11P_T1_SRCC_33       
-set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_vsync]        ; ## IO_L2P_T0_33             
-set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_hsync]        ; ## IO_L2N_T0_33             
-set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data_e]       ; ## IO_L11N_T1_SRCC_33       
-set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[0]]      ; ## IO_L3P_T0_DQS_33         
-set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[1]]      ; ## IO_L3N_T0_DQS_33         
-set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[2]]      ; ## IO_L4P_T0_33             
-set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[3]]      ; ## IO_L4N_T0_33             
-set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[4]]      ; ## IO_L5P_T0_33             
-set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[5]]      ; ## IO_L5N_T0_33             
-set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[6]]      ; ## IO_L6P_T0_33             
-set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[7]]      ; ## IO_L6N_T0_VREF_33        
-set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[8]]      ; ## IO_L7P_T1_33             
-set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[9]]      ; ## IO_L7N_T1_33             
-set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[10]]     ; ## IO_L8P_T1_33             
-set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[11]]     ; ## IO_L8N_T1_33             
-set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[12]]     ; ## IO_L9P_T1_DQS_33         
-set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[13]]     ; ## IO_L9N_T1_DQS_33         
-set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[14]]     ; ## IO_L10P_T1_33            
-set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[15]]     ; ## IO_L10N_T1_33 
-set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD LVCMOS18}             [get_ports hdmi_pd]           ; ## IO_0_VRN_33              
-set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD LVCMOS18}             [get_ports hdmi_intn]         ; ## IO_25_VRP_33             
+set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD LVCMOS18}             [get_ports hdmi_out_clk]     ; ## IO_L11P_T1_SRCC_33       
+set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_vsync]       ; ## IO_L2P_T0_33             
+set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_hsync]       ; ## IO_L2N_T0_33             
+set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data_e]      ; ## IO_L11N_T1_SRCC_33       
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[0]]     ; ## IO_L3P_T0_DQS_33         
+set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[1]]     ; ## IO_L3N_T0_DQS_33         
+set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[2]]     ; ## IO_L4P_T0_33             
+set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[3]]     ; ## IO_L4N_T0_33             
+set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[4]]     ; ## IO_L5P_T0_33             
+set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[5]]     ; ## IO_L5N_T0_33             
+set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[6]]     ; ## IO_L6P_T0_33             
+set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[7]]     ; ## IO_L6N_T0_VREF_33        
+set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[8]]     ; ## IO_L7P_T1_33             
+set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[9]]     ; ## IO_L7N_T1_33             
+set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[10]]    ; ## IO_L8P_T1_33             
+set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[11]]    ; ## IO_L8N_T1_33             
+set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[12]]    ; ## IO_L9P_T1_DQS_33         
+set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[13]]    ; ## IO_L9N_T1_DQS_33         
+set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[14]]    ; ## IO_L10P_T1_33            
+set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[15]]    ; ## IO_L10N_T1_33 
+set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD LVCMOS18}             [get_ports hdmi_pd]          ; ## IO_0_VRN_33              
+set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD LVCMOS18}             [get_ports hdmi_intn]        ; ## IO_25_VRP_33             
 
 # hdmi-spdif
 
-set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD LVCMOS18} [get_ports spdif]                         ; ## IO_L1P_T0_33             
-set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD LVCMOS18} [get_ports spdif_in]                      ; ## IO_L1N_T0_33             
+set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD LVCMOS18} [get_ports spdif]                        ; ## IO_L1P_T0_33             
+set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD LVCMOS18} [get_ports spdif_in]                     ; ## IO_L1N_T0_33             
 
 # audio
 
-set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD LVCMOS18} [get_ports i2s_mclk]                      ; ## IO_L6P_T0_34             
-set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD LVCMOS18} [get_ports i2s_bclk]                      ; ## IO_L6N_T0_VREF_34        
-set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD LVCMOS18} [get_ports i2s_lrclk]                     ; ## IO_L7P_T1_34             
-set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out]                 ; ## IO_L7N_T1_34             
-set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in]                  ; ## IO_L8P_T1_34             
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD LVCMOS18} [get_ports i2s_mclk]                     ; ## IO_L6P_T0_34             
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD LVCMOS18} [get_ports i2s_bclk]                     ; ## IO_L6N_T0_VREF_34        
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD LVCMOS18} [get_ports i2s_lrclk]                    ; ## IO_L7P_T1_34             
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out]                ; ## IO_L7N_T1_34             
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in]                 ; ## IO_L8P_T1_34             
 
 # ad9517
 
-set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD LVCMOS18} [get_ports ad9517_csn]                    ; ## IO_L20N_T3_34             
-set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD LVCMOS18} [get_ports ad9517_clk]                    ; ## IO_L19P_T3_34             
-set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD LVCMOS18} [get_ports ad9517_mosi]                   ; ## IO_L19N_T3_VREF_34        
-set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD LVCMOS18} [get_ports ad9517_miso]                   ; ## IO_L20P_T3_34             
-set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD LVCMOS18} [get_ports ad9517_pdn]                    ; ## IO_L21P_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel]                ; ## IO_L21N_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD LVCMOS18} [get_ports ad9517_ld]                     ; ## IO_L22P_T3_34             
-set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD LVCMOS18} [get_ports ad9517_status]                 ; ## IO_L22N_T3_34             
+set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD LVCMOS18} [get_ports ad9517_csn]                   ; ## IO_L20N_T3_34             
+set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD LVCMOS18} [get_ports ad9517_clk]                   ; ## IO_L19P_T3_34             
+set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD LVCMOS18} [get_ports ad9517_mosi]                  ; ## IO_L19N_T3_VREF_34        
+set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD LVCMOS18} [get_ports ad9517_miso]                  ; ## IO_L20P_T3_34             
+set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD LVCMOS18} [get_ports ad9517_pdn]                   ; ## IO_L21P_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel]               ; ## IO_L21N_T3_DQS_34         
+set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD LVCMOS18} [get_ports ad9517_ld]                    ; ## IO_L22P_T3_34             
+set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD LVCMOS18} [get_ports ad9517_status]                ; ## IO_L22N_T3_34             
 
 # clocks
 
@@ -90,161 +90,158 @@ set_property IODELAY_GROUP gmii2rgmii_iodelay_group\
 
 # fan control/sense
 
-set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD LVCMOS18} [get_ports fan_pwm]    ; ## IO_L18P_T2_34
-set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD LVCMOS18} [get_ports fan_tach]   ; ## IO_L18N_T2_34
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD LVCMOS18} [get_ports fan_pwm]                      ; ## IO_L18P_T2_34
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD LVCMOS18} [get_ports fan_tach]                     ; ## IO_L18N_T2_34
 
 # unused io (gpio/gt)
 
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p]            ; ## IO_L13P_T2_MRCC_12 (fmc_clk0_p)
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n]            ; ## IO_L13N_T2_MRCC_12 (fmc_clk0_n)
-set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p]            ; ## IO_L13P_T2_MRCC_13 (fmc_clk1_p)
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n]            ; ## IO_L13N_T2_MRCC_13 (fmc_clk1_n)
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p]        ; ## IO_L13P_T2_MRCC_12       (fmc_clk0_p)
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n]        ; ## IO_L13N_T2_MRCC_12       (fmc_clk0_n)
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p]        ; ## IO_L13P_T2_MRCC_13       (fmc_clk1_p)
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n]        ; ## IO_L13N_T2_MRCC_13       (fmc_clk1_n)
 
-set_property  -dict {PACKAGE_PIN  W6}   [get_ports gt_ref_clk_0_p]                                        ; ## MGTREFCLK0P_111 (fmc_gt_ref_clk_p)         
-set_property  -dict {PACKAGE_PIN  W5}   [get_ports gt_ref_clk_0_n]                                        ; ## MGTREFCLK0N_111 (fmc_gt_ref_clk_n)         
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports gt_tx_0_p]                                             ; ## MGTXTXP0_111    (fmc_gt_tx_p)              
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports gt_tx_0_n]                                             ; ## MGTXTXN0_111    (fmc_gt_tx_n)              
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports gt_rx_0_p]                                             ; ## MGTXRXP0_111    (fmc_gt_rx_p)              
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports gt_rx_0_n]                                             ; ## MGTXRXN0_111    (fmc_gt_rx_n)              
+set_property  -dict {PACKAGE_PIN  W6}   [get_ports gt_ref_clk_p]                                      ; ## MGTREFCLK0P_111          (fmc_gt_ref_clk_p)         
+set_property  -dict {PACKAGE_PIN  W5}   [get_ports gt_ref_clk_n]                                      ; ## MGTREFCLK0N_111          (fmc_gt_ref_clk_n)         
+set_property  -dict {PACKAGE_PIN  AF8}  [get_ports gt_tx_p[0]]                                        ; ## MGTXTXP0_111             (fmc_gt_tx_p)              
+set_property  -dict {PACKAGE_PIN  AF7}  [get_ports gt_tx_n[0]]                                        ; ## MGTXTXN0_111             (fmc_gt_tx_n)              
+set_property  -dict {PACKAGE_PIN  AD8}  [get_ports gt_rx_p[0]]                                        ; ## MGTXRXP0_111             (fmc_gt_rx_p)              
+set_property  -dict {PACKAGE_PIN  AD7}  [get_ports gt_rx_n[0]]                                        ; ## MGTXRXN0_111             (fmc_gt_rx_n)              
 
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD LVCMOS25} [get_ports gp_in_0]                          ; ## IO_25_13 (fmc_prstn)
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD LVCMOS25} [get_ports gp_in_0]                      ; ## IO_25_13                 (fmc_prstn)
 
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVCMOS25} [get_ports gp_out[0]]                        ; ## IO_L12P_T1_MRCC_12  (fmc_la_p[ 0])  
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVCMOS25} [get_ports gp_out[1]]                        ; ## IO_L12N_T1_MRCC_12  (fmc_la_n[ 0])  
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVCMOS25} [get_ports gp_out[2]]                        ; ## IO_L11P_T1_SRCC_12  (fmc_la_p[ 1])  
-set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD LVCMOS25} [get_ports gp_out[3]]                        ; ## IO_L11N_T1_SRCC_12  (fmc_la_n[ 1])  
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD LVCMOS25} [get_ports gp_out[4]]                        ; ## IO_L1P_T0_12        (fmc_la_p[ 2])  
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD LVCMOS25} [get_ports gp_out[5]]                        ; ## IO_L1N_T0_12        (fmc_la_n[ 2])  
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVCMOS25} [get_ports gp_out[6]]                        ; ## IO_L2P_T0_12        (fmc_la_p[ 3])  
-set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD LVCMOS25} [get_ports gp_out[7]]                        ; ## IO_L2N_T0_12        (fmc_la_n[ 3])  
-set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD LVCMOS25} [get_ports gp_out[8]]                        ; ## IO_L3P_T0_DQS_12    (fmc_la_p[ 4])  
-set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD LVCMOS25} [get_ports gp_out[9]]                        ; ## IO_L3N_T0_DQS_12    (fmc_la_n[ 4])  
-set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD LVCMOS25} [get_ports gp_out[10]]                       ; ## IO_L4P_T0_12        (fmc_la_p[ 5])  
-set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD LVCMOS25} [get_ports gp_out[11]]                       ; ## IO_L4N_T0_12        (fmc_la_n[ 5])  
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD LVCMOS25} [get_ports gp_out[12]]                       ; ## IO_L5P_T0_12        (fmc_la_p[ 6])  
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD LVCMOS25} [get_ports gp_out[13]]                       ; ## IO_L5N_T0_12        (fmc_la_n[ 6])  
-set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD LVCMOS25} [get_ports gp_out[14]]                       ; ## IO_L6P_T0_12        (fmc_la_p[ 7])  
-set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS25} [get_ports gp_out[15]]                       ; ## IO_L6N_T0_VREF_12   (fmc_la_n[ 7])  
-set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD LVCMOS25} [get_ports gp_out[16]]                       ; ## IO_L7P_T1_12        (fmc_la_p[ 8])  
-set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD LVCMOS25} [get_ports gp_out[17]]                       ; ## IO_L7N_T1_12        (fmc_la_n[ 8])  
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVCMOS25} [get_ports gp_out[18]]                       ; ## IO_L8P_T1_12        (fmc_la_p[ 9])  
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVCMOS25} [get_ports gp_out[19]]                       ; ## IO_L8N_T1_12        (fmc_la_n[ 9])  
-set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD LVCMOS25} [get_ports gp_out[20]]                       ; ## IO_L9P_T1_DQS_12    (fmc_la_p[10])  
-set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD LVCMOS25} [get_ports gp_out[21]]                       ; ## IO_L9N_T1_DQS_12    (fmc_la_n[10])  
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVCMOS25} [get_ports gp_out[22]]                       ; ## IO_L10P_T1_12       (fmc_la_p[11])  
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVCMOS25} [get_ports gp_out[23]]                       ; ## IO_L10N_T1_12       (fmc_la_n[11])  
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25} [get_ports gp_out[24]]                       ; ## IO_L14P_T2_SRCC_12  (fmc_la_p[12])  
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25} [get_ports gp_out[25]]                       ; ## IO_L14N_T2_SRCC_12  (fmc_la_n[12])  
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVCMOS25} [get_ports gp_out[26]]                       ; ## IO_L15P_T2_DQS_12   (fmc_la_p[13])  
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVCMOS25} [get_ports gp_out[27]]                       ; ## IO_L15N_T2_DQS_12   (fmc_la_n[13])  
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVCMOS25} [get_ports gp_out[28]]                       ; ## IO_L16P_T2_12       (fmc_la_p[14])  
-set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD LVCMOS25} [get_ports gp_out[29]]                       ; ## IO_L16N_T2_12       (fmc_la_n[14])  
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVCMOS25} [get_ports gp_out[30]]                       ; ## IO_L17P_T2_12       (fmc_la_p[15])  
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVCMOS25} [get_ports gp_out[31]]                       ; ## IO_L17N_T2_12       (fmc_la_n[15])  
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports gp_out[32]]                       ; ## IO_L18P_T2_12       (fmc_la_p[16])  
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVCMOS25} [get_ports gp_out[33]]                       ; ## IO_L18N_T2_12       (fmc_la_n[16])  
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVCMOS25} [get_ports gp_out[0]]                    ; ## IO_L12P_T1_MRCC_12       (fmc_la_p[ 0])  
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVCMOS25} [get_ports gp_out[1]]                    ; ## IO_L12N_T1_MRCC_12       (fmc_la_n[ 0])  
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVCMOS25} [get_ports gp_out[2]]                    ; ## IO_L11P_T1_SRCC_12       (fmc_la_p[ 1])  
+set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD LVCMOS25} [get_ports gp_out[3]]                    ; ## IO_L11N_T1_SRCC_12       (fmc_la_n[ 1])  
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD LVCMOS25} [get_ports gp_out[4]]                    ; ## IO_L1P_T0_12             (fmc_la_p[ 2])  
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD LVCMOS25} [get_ports gp_out[5]]                    ; ## IO_L1N_T0_12             (fmc_la_n[ 2])  
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVCMOS25} [get_ports gp_out[6]]                    ; ## IO_L2P_T0_12             (fmc_la_p[ 3])  
+set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD LVCMOS25} [get_ports gp_out[7]]                    ; ## IO_L2N_T0_12             (fmc_la_n[ 3])  
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD LVCMOS25} [get_ports gp_out[8]]                    ; ## IO_L3P_T0_DQS_12         (fmc_la_p[ 4])  
+set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD LVCMOS25} [get_ports gp_out[9]]                    ; ## IO_L3N_T0_DQS_12         (fmc_la_n[ 4])  
+set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD LVCMOS25} [get_ports gp_out[10]]                   ; ## IO_L4P_T0_12             (fmc_la_p[ 5])  
+set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD LVCMOS25} [get_ports gp_out[11]]                   ; ## IO_L4N_T0_12             (fmc_la_n[ 5])  
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD LVCMOS25} [get_ports gp_out[12]]                   ; ## IO_L5P_T0_12             (fmc_la_p[ 6])  
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD LVCMOS25} [get_ports gp_out[13]]                   ; ## IO_L5N_T0_12             (fmc_la_n[ 6])  
+set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD LVCMOS25} [get_ports gp_out[14]]                   ; ## IO_L6P_T0_12             (fmc_la_p[ 7])  
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS25} [get_ports gp_out[15]]                   ; ## IO_L6N_T0_VREF_12        (fmc_la_n[ 7])  
+set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD LVCMOS25} [get_ports gp_out[16]]                   ; ## IO_L7P_T1_12             (fmc_la_p[ 8])  
+set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD LVCMOS25} [get_ports gp_out[17]]                   ; ## IO_L7N_T1_12             (fmc_la_n[ 8])  
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVCMOS25} [get_ports gp_out[18]]                   ; ## IO_L8P_T1_12             (fmc_la_p[ 9])  
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVCMOS25} [get_ports gp_out[19]]                   ; ## IO_L8N_T1_12             (fmc_la_n[ 9])  
+set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD LVCMOS25} [get_ports gp_out[20]]                   ; ## IO_L9P_T1_DQS_12         (fmc_la_p[10])  
+set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD LVCMOS25} [get_ports gp_out[21]]                   ; ## IO_L9N_T1_DQS_12         (fmc_la_n[10])  
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVCMOS25} [get_ports gp_out[22]]                   ; ## IO_L10P_T1_12            (fmc_la_p[11])  
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVCMOS25} [get_ports gp_out[23]]                   ; ## IO_L10N_T1_12            (fmc_la_n[11])  
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25} [get_ports gp_out[24]]                   ; ## IO_L14P_T2_SRCC_12       (fmc_la_p[12])  
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25} [get_ports gp_out[25]]                   ; ## IO_L14N_T2_SRCC_12       (fmc_la_n[12])  
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVCMOS25} [get_ports gp_out[26]]                   ; ## IO_L15P_T2_DQS_12        (fmc_la_p[13])  
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVCMOS25} [get_ports gp_out[27]]                   ; ## IO_L15N_T2_DQS_12        (fmc_la_n[13])  
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVCMOS25} [get_ports gp_out[28]]                   ; ## IO_L16P_T2_12            (fmc_la_p[14])  
+set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD LVCMOS25} [get_ports gp_out[29]]                   ; ## IO_L16N_T2_12            (fmc_la_n[14])  
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVCMOS25} [get_ports gp_out[30]]                   ; ## IO_L17P_T2_12            (fmc_la_p[15])  
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVCMOS25} [get_ports gp_out[31]]                   ; ## IO_L17N_T2_12            (fmc_la_n[15])  
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports gp_out[32]]                   ; ## IO_L18P_T2_12            (fmc_la_p[16])  
+set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVCMOS25} [get_ports gp_out[33]]                   ; ## IO_L18N_T2_12            (fmc_la_n[16])  
 
-set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD LVCMOS25} [get_ports gp_in[0]]                         ; ## IO_L12P_T1_MRCC_13  (fmc_la_p[17])
-set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD LVCMOS25} [get_ports gp_in[1]]                         ; ## IO_L12N_T1_MRCC_13  (fmc_la_n[17])
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports gp_in[2]]                         ; ## IO_L11P_T1_SRCC_13  (fmc_la_p[18])
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVCMOS25} [get_ports gp_in[3]]                         ; ## IO_L11N_T1_SRCC_13  (fmc_la_n[18])
-set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD LVCMOS25} [get_ports gp_in[4]]                         ; ## IO_L1P_T0_13        (fmc_la_p[19])
-set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD LVCMOS25} [get_ports gp_in[5]]                         ; ## IO_L1N_T0_13        (fmc_la_n[19])
-set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD LVCMOS25} [get_ports gp_in[6]]                         ; ## IO_L2P_T0_13        (fmc_la_p[20])
-set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD LVCMOS25} [get_ports gp_in[7]]                         ; ## IO_L2N_T0_13        (fmc_la_n[20])
-set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVCMOS25} [get_ports gp_in[8]]                         ; ## IO_L3P_T0_DQS_13    (fmc_la_p[21])
-set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVCMOS25} [get_ports gp_in[9]]                         ; ## IO_L3N_T0_DQS_13    (fmc_la_n[21])
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVCMOS25} [get_ports gp_in[10]]                        ; ## IO_L4P_T0_13        (fmc_la_p[22])
-set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD LVCMOS25} [get_ports gp_in[11]]                        ; ## IO_L4N_T0_13        (fmc_la_n[22])
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25} [get_ports gp_in[12]]                        ; ## IO_L6P_T0_13        (fmc_la_p[23])
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25} [get_ports gp_in[13]]                        ; ## IO_L6N_T0_VREF_13   (fmc_la_n[23])
-set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD LVCMOS25} [get_ports gp_in[14]]                        ; ## IO_L7P_T1_13        (fmc_la_p[24])
-set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD LVCMOS25} [get_ports gp_in[15]]                        ; ## IO_L7N_T1_13        (fmc_la_n[24])
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports gp_in[16]]                        ; ## IO_L8P_T1_13        (fmc_la_p[25])
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports gp_in[17]]                        ; ## IO_L8N_T1_13        (fmc_la_n[25])
-set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD LVCMOS25} [get_ports gp_in[18]]                        ; ## IO_L9P_T1_DQS_13    (fmc_la_p[26])
-set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD LVCMOS25} [get_ports gp_in[19]]                        ; ## IO_L9N_T1_DQS_13    (fmc_la_n[26])
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports gp_in[20]]                        ; ## IO_L10P_T1_13       (fmc_la_p[27])
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports gp_in[21]]                        ; ## IO_L10N_T1_13       (fmc_la_n[27])
-set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD LVCMOS25} [get_ports gp_in[22]]                        ; ## IO_L14P_T2_SRCC_13  (fmc_la_p[28])
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS25} [get_ports gp_in[23]]                        ; ## IO_L14N_T2_SRCC_13  (fmc_la_n[28])
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports gp_in[24]]                        ; ## IO_L15P_T2_DQS_13   (fmc_la_p[29])
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVCMOS25} [get_ports gp_in[25]]                        ; ## IO_L15N_T2_DQS_13   (fmc_la_n[29])
-set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD LVCMOS25} [get_ports gp_in[26]]                        ; ## IO_L16P_T2_13       (fmc_la_p[30])
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports gp_in[27]]                        ; ## IO_L16N_T2_13       (fmc_la_n[30])
-set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD LVCMOS25} [get_ports gp_in[28]]                        ; ## IO_L17P_T2_13       (fmc_la_p[31])
-set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD LVCMOS25} [get_ports gp_in[29]]                        ; ## IO_L17N_T2_13       (fmc_la_n[31])
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports gp_in[30]]                        ; ## IO_L18P_T2_13       (fmc_la_p[32])
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVCMOS25} [get_ports gp_in[31]]                        ; ## IO_L18N_T2_13       (fmc_la_n[32])
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports gp_in[32]]                        ; ## IO_L19P_T3_13       (fmc_la_p[33])
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD LVCMOS25} [get_ports gp_in[33]]                        ; ## IO_L19N_T3_VREF_13  (fmc_la_n[33])
+set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD LVCMOS25} [get_ports gp_in[0]]                     ; ## IO_L12P_T1_MRCC_13       (fmc_la_p[17])
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD LVCMOS25} [get_ports gp_in[1]]                     ; ## IO_L12N_T1_MRCC_13       (fmc_la_n[17])
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports gp_in[2]]                     ; ## IO_L11P_T1_SRCC_13       (fmc_la_p[18])
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVCMOS25} [get_ports gp_in[3]]                     ; ## IO_L11N_T1_SRCC_13       (fmc_la_n[18])
+set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD LVCMOS25} [get_ports gp_in[4]]                     ; ## IO_L1P_T0_13             (fmc_la_p[19])
+set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD LVCMOS25} [get_ports gp_in[5]]                     ; ## IO_L1N_T0_13             (fmc_la_n[19])
+set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD LVCMOS25} [get_ports gp_in[6]]                     ; ## IO_L2P_T0_13             (fmc_la_p[20])
+set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD LVCMOS25} [get_ports gp_in[7]]                     ; ## IO_L2N_T0_13             (fmc_la_n[20])
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVCMOS25} [get_ports gp_in[8]]                     ; ## IO_L3P_T0_DQS_13         (fmc_la_p[21])
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVCMOS25} [get_ports gp_in[9]]                     ; ## IO_L3N_T0_DQS_13         (fmc_la_n[21])
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVCMOS25} [get_ports gp_in[10]]                    ; ## IO_L4P_T0_13             (fmc_la_p[22])
+set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD LVCMOS25} [get_ports gp_in[11]]                    ; ## IO_L4N_T0_13             (fmc_la_n[22])
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25} [get_ports gp_in[12]]                    ; ## IO_L6P_T0_13             (fmc_la_p[23])
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25} [get_ports gp_in[13]]                    ; ## IO_L6N_T0_VREF_13        (fmc_la_n[23])
+set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD LVCMOS25} [get_ports gp_in[14]]                    ; ## IO_L7P_T1_13             (fmc_la_p[24])
+set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD LVCMOS25} [get_ports gp_in[15]]                    ; ## IO_L7N_T1_13             (fmc_la_n[24])
+set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports gp_in[16]]                    ; ## IO_L8P_T1_13             (fmc_la_p[25])
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports gp_in[17]]                    ; ## IO_L8N_T1_13             (fmc_la_n[25])
+set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD LVCMOS25} [get_ports gp_in[18]]                    ; ## IO_L9P_T1_DQS_13         (fmc_la_p[26])
+set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD LVCMOS25} [get_ports gp_in[19]]                    ; ## IO_L9N_T1_DQS_13         (fmc_la_n[26])
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports gp_in[20]]                    ; ## IO_L10P_T1_13            (fmc_la_p[27])
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports gp_in[21]]                    ; ## IO_L10N_T1_13            (fmc_la_n[27])
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD LVCMOS25} [get_ports gp_in[22]]                    ; ## IO_L14P_T2_SRCC_13       (fmc_la_p[28])
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS25} [get_ports gp_in[23]]                    ; ## IO_L14N_T2_SRCC_13       (fmc_la_n[28])
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports gp_in[24]]                    ; ## IO_L15P_T2_DQS_13        (fmc_la_p[29])
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVCMOS25} [get_ports gp_in[25]]                    ; ## IO_L15N_T2_DQS_13        (fmc_la_n[29])
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD LVCMOS25} [get_ports gp_in[26]]                    ; ## IO_L16P_T2_13            (fmc_la_p[30])
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports gp_in[27]]                    ; ## IO_L16N_T2_13            (fmc_la_n[30])
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD LVCMOS25} [get_ports gp_in[28]]                    ; ## IO_L17P_T2_13            (fmc_la_p[31])
+set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD LVCMOS25} [get_ports gp_in[29]]                    ; ## IO_L17N_T2_13            (fmc_la_n[31])
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports gp_in[30]]                    ; ## IO_L18P_T2_13            (fmc_la_p[32])
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVCMOS25} [get_ports gp_in[31]]                    ; ## IO_L18N_T2_13            (fmc_la_n[32])
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports gp_in[32]]                    ; ## IO_L19P_T3_13            (fmc_la_p[33])
+set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD LVCMOS25} [get_ports gp_in[33]]                    ; ## IO_L19N_T3_VREF_13       (fmc_la_n[33])
 
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD LVCMOS25} [get_ports gp_out[34]]                       ; ## IO_L21P_T3_DQS_13 (pmod0[0])     
-set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD LVCMOS25} [get_ports gp_inout_0]                       ; ## IO_L21N_T3_DQS_13 (pmod0[1])       
-set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD LVCMOS25} [get_ports gp_out[35]]                       ; ## IO_L22P_T3_13     (pmod0[2])     
-set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD LVCMOS25} [get_ports gp_out[36]]                       ; ## IO_L22N_T3_13     (pmod0[3])     
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS25} [get_ports gp_in[34]]                        ; ## IO_L23P_T3_13     (pmod0[4])     
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD LVCMOS25} [get_ports gp_inout_1]                       ; ## IO_L23N_T3_13     (pmod0[5]) + (TDD_SYNC)            
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD LVCMOS25} [get_ports gp_in[35]]                        ; ## IO_L24P_T3_13     (pmod0[6])     
-set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD LVCMOS25} [get_ports gp_in[36]]                        ; ## IO_L24N_T3_13     (pmod0[7])     
+set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD LVCMOS25} [get_ports gp_out[34]]                   ; ## IO_L21P_T3_DQS_13        (pmod0[0])     
+set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD LVCMOS25} [get_ports gp_in_1]                      ; ## IO_L21N_T3_DQS_13        (pmod0[1])       
+set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD LVCMOS25} [get_ports gp_out[35]]                   ; ## IO_L22P_T3_13            (pmod0[2])     
+set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD LVCMOS25} [get_ports gp_out[36]]                   ; ## IO_L22N_T3_13            (pmod0[3])     
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS25} [get_ports gp_in[34]]                    ; ## IO_L23P_T3_13            (pmod0[4])     
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD LVCMOS25} [get_ports tdd_sync]                     ; ## IO_L23N_T3_13            (pmod0[5]) + (TDD_SYNC)            
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD LVCMOS25} [get_ports gp_in[35]]                    ; ## IO_L24P_T3_13            (pmod0[6])     
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD LVCMOS25} [get_ports gp_in[36]]                    ; ## IO_L24N_T3_13            (pmod0[7])     
 
-set_property  -dict {PACKAGE_PIN  AA6}  [get_ports gt_ref_clk_1_p]                                        ; ## MGTREFCLK1P_111   (ad9517_gt_ref_clk_p)
-set_property  -dict {PACKAGE_PIN  AA5}  [get_ports gt_ref_clk_1_n]                                        ; ## MGTREFCLK1N_111   (ad9517_gt_ref_clk_n)
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports gt_tx_1_p]                                             ; ## MGTXTXP1_111      (sfp_gt_tx_p)
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports gt_tx_1_n]                                             ; ## MGTXTXN1_111      (sfp_gt_tx_n)
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports gt_rx_1_p]                                             ; ## MGTXRXP1_111      (sfp_gt_rx_p)
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports gt_rx_1_n]                                             ; ## MGTXRXN1_111      (sfp_gt_rx_n)
+set_property  -dict {PACKAGE_PIN  AA6}  [get_ports clk_2_p]                                           ; ## MGTREFCLK1P_111          (ad9517_gt_ref_clk_p)
+set_property  -dict {PACKAGE_PIN  AA5}  [get_ports clk_2_n]                                           ; ## MGTREFCLK1N_111          (ad9517_gt_ref_clk_n)
+set_property  -dict {PACKAGE_PIN  AF4}  [get_ports gt_tx_p[1]]                                        ; ## MGTXTXP1_111             (sfp_gt_tx_p)
+set_property  -dict {PACKAGE_PIN  AF3}  [get_ports gt_tx_n[1]]                                        ; ## MGTXTXN1_111             (sfp_gt_tx_n)
+set_property  -dict {PACKAGE_PIN  AE6}  [get_ports gt_rx_p[1]]                                        ; ## MGTXRXP1_111             (sfp_gt_rx_p)
+set_property  -dict {PACKAGE_PIN  AE5}  [get_ports gt_rx_n[1]]                                        ; ## MGTXRXN1_111             (sfp_gt_rx_n)
 
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports gp_in[37]]                        ; ## IO_L1P_T0_34            (CAM_GPIO_0  ) 
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports gp_in[38]]                        ; ## IO_L1N_T0_34            (CAM_GPIO_1  ) 
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports gp_in[39]]                        ; ## IO_L3P_T0_DQS_PUDC_B_34 (CAM_GPIO_4  ) 
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports gp_in[40]]                        ; ## IO_L3N_T0_DQS_34        (CAM_GPIO_5  ) 
-set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD LVCMOS18} [get_ports gp_in[41]]                        ; ## IO_L13P_T2_MRCC_33      (CAM_CLK_P   )     
-set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD LVCMOS18} [get_ports gp_in[42]]                        ; ## IO_L13N_T2_MRCC_33      (CAM_CLK_N   )     
-set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD LVCMOS18} [get_ports gp_in[43]]                        ; ## IO_L16P_T2_33           (CAM_DATA1_P )     
-set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD LVCMOS18} [get_ports gp_in[44]]                        ; ## IO_L16N_T2_33           (CAM_DATA1_N )     
-set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD LVCMOS18} [get_ports gp_in[45]]                        ; ## IO_L18P_T2_33           (CAM_DATA3_P )     
-set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD LVCMOS18} [get_ports gp_in[46]]                        ; ## IO_L18N_T2_33           (CAM_DATA3_N )     
-set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD LVCMOS18} [get_ports gp_in[47]]                        ; ## IO_L20P_T3_33           (CAM_DATA5_P )     
-set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD LVCMOS18} [get_ports gp_in[48]]                        ; ## IO_L20N_T3_33           (CAM_DATA5_N )     
-set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD LVCMOS18} [get_ports gp_in[49]]                        ; ## IO_L22P_T3_33           (CAM_DATA7_P ) 
-set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD LVCMOS18} [get_ports gp_in[50]]                        ; ## IO_L22N_T3_33           (CAM_DATA7_N ) 
-set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD LVCMOS18} [get_ports gp_in[51]]                        ; ## IO_L23P_T3_33           (CAM_SPI_CSN ) 
-set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD LVCMOS18} [get_ports gp_in[52]]                        ; ## IO_L23N_T3_33           (CAM_SPI_CLK ) 
-set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD LVCMOS18} [get_ports gp_in[53]]                        ; ## IO_L12P_T1_MRCC_33      (CAM_REFCLK  ) 
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports gp_out[37]]                       ; ## IO_L2P_T0_34            (CAM_GPIO_2  ) 
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports gp_out[38]]                       ; ## IO_L2N_T0_34            (CAM_GPIO_3  ) 
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports gp_out[39]]                       ; ## IO_L4P_T0_34            (CAM_GPIO_6  ) 
-set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD LVCMOS18} [get_ports gp_out[40]]                       ; ## IO_L4N_T0_34            (CAM_GPIO_7  ) 
-set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD LVCMOS18} [get_ports gp_out[41]]                       ; ## IO_L15P_T2_DQS_33       (CAM_DATA0_P )     
-set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD LVCMOS18} [get_ports gp_out[42]]                       ; ## IO_L15N_T2_DQS_33       (CAM_DATA0_N )     
-set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD LVCMOS18} [get_ports gp_out[43]]                       ; ## IO_L17P_T2_33           (CAM_DATA2_P )     
-set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD LVCMOS18} [get_ports gp_out[44]]                       ; ## IO_L17N_T2_33           (CAM_DATA2_N )     
-set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD LVCMOS18} [get_ports gp_out[45]]                       ; ## IO_L19P_T3_33           (CAM_DATA4_P )     
-set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD LVCMOS18} [get_ports gp_out[46]]                       ; ## IO_L19N_T3_VREF_33      (CAM_DATA4_N )     
-set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD LVCMOS18} [get_ports gp_out[47]]                       ; ## IO_L21P_T3_DQS_33       (CAM_DATA6_P )     
-set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD LVCMOS18} [get_ports gp_out[48]]                       ; ## IO_L21N_T3_DQS_33       (CAM_DATA6_N ) 
-set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD LVCMOS18} [get_ports gp_out[49]]                       ; ## IO_L14P_T2_SRCC_33      (CAM_SYNC_P  )     
-set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD LVCMOS18} [get_ports gp_out[50]]                       ; ## IO_L14N_T2_SRCC_33      (CAM_SYNC_N  )     
-set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD LVCMOS18} [get_ports gp_out[51]]                       ; ## IO_L24P_T3_33           (CAM_SPI_MISO) 
-set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD LVCMOS18} [get_ports gp_out[52]]                       ; ## IO_L24N_T3_33           (CAM_SPI_MOSI) 
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports gp_out[53]]                       ; ## IO_L5P_T0_34            (CAM_GPIO_8  ) 
-
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD LVCMOS25} [get_ports gp_inout[0]]                      ; ## IO_L19P_T3_12           (sfp_gpio[0])
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS25} [get_ports gp_inout[1]]                      ; ## IO_L19N_T3_VREF_12      (sfp_gpio[1])
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gp_inout[2]]                      ; ## IO_L20P_T3_12           (sfp_gpio[2])
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS25} [get_ports gp_inout[3]]                      ; ## IO_L20N_T3_12           (sfp_gpio[3])
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gp_inout[4]]                      ; ## IO_L21P_T3_DQS_12       (sfp_gpio[4])
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gp_inout[5]]                      ; ## IO_L21N_T3_DQS_12       (sfp_gpio[5])
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVCMOS25} [get_ports gp_inout[6]]                      ; ## IO_L22P_T3_12           (sfp_gpio[6])
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports gp_in[37]]                    ; ## IO_L1P_T0_34             (CAM_GPIO_0  ) 
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports gp_in[38]]                    ; ## IO_L1N_T0_34             (CAM_GPIO_1  ) 
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports gp_in[39]]                    ; ## IO_L3P_T0_DQS_PUDC_B_34  (CAM_GPIO_4  ) 
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports gp_in[40]]                    ; ## IO_L3N_T0_DQS_34         (CAM_GPIO_5  ) 
+set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD LVCMOS18} [get_ports gp_in[41]]                    ; ## IO_L13P_T2_MRCC_33       (CAM_CLK_P   )     
+set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD LVCMOS18} [get_ports gp_in[42]]                    ; ## IO_L13N_T2_MRCC_33       (CAM_CLK_N   )     
+set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD LVCMOS18} [get_ports gp_in[43]]                    ; ## IO_L16P_T2_33            (CAM_DATA1_P )     
+set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD LVCMOS18} [get_ports gp_in[44]]                    ; ## IO_L16N_T2_33            (CAM_DATA1_N )     
+set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD LVCMOS18} [get_ports gp_in[45]]                    ; ## IO_L18P_T2_33            (CAM_DATA3_P )     
+set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD LVCMOS18} [get_ports gp_in[46]]                    ; ## IO_L18N_T2_33            (CAM_DATA3_N )     
+set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD LVCMOS18} [get_ports gp_in[47]]                    ; ## IO_L20P_T3_33            (CAM_DATA5_P )     
+set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD LVCMOS18} [get_ports gp_in[48]]                    ; ## IO_L20N_T3_33            (CAM_DATA5_N )     
+set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD LVCMOS18} [get_ports gp_in[49]]                    ; ## IO_L22P_T3_33            (CAM_DATA7_P ) 
+set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD LVCMOS18} [get_ports gp_in[50]]                    ; ## IO_L22N_T3_33            (CAM_DATA7_N ) 
+set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD LVCMOS18} [get_ports gp_in[51]]                    ; ## IO_L23P_T3_33            (CAM_SPI_CSN ) 
+set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD LVCMOS18} [get_ports gp_in[52]]                    ; ## IO_L23N_T3_33            (CAM_SPI_CLK ) 
+set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD LVCMOS18} [get_ports gp_in[53]]                    ; ## IO_L12P_T1_MRCC_33       (CAM_REFCLK  ) 
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports gp_out[37]]                   ; ## IO_L2P_T0_34             (CAM_GPIO_2  ) 
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports gp_out[38]]                   ; ## IO_L2N_T0_34             (CAM_GPIO_3  ) 
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports gp_out[39]]                   ; ## IO_L4P_T0_34             (CAM_GPIO_6  ) 
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD LVCMOS18} [get_ports gp_out[40]]                   ; ## IO_L4N_T0_34             (CAM_GPIO_7  ) 
+set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD LVCMOS18} [get_ports gp_out[41]]                   ; ## IO_L15P_T2_DQS_33        (CAM_DATA0_P )     
+set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD LVCMOS18} [get_ports gp_out[42]]                   ; ## IO_L15N_T2_DQS_33        (CAM_DATA0_N )     
+set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD LVCMOS18} [get_ports gp_out[43]]                   ; ## IO_L17P_T2_33            (CAM_DATA2_P )     
+set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD LVCMOS18} [get_ports gp_out[44]]                   ; ## IO_L17N_T2_33            (CAM_DATA2_N )     
+set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD LVCMOS18} [get_ports gp_out[45]]                   ; ## IO_L19P_T3_33            (CAM_DATA4_P )     
+set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD LVCMOS18} [get_ports gp_out[46]]                   ; ## IO_L19N_T3_VREF_33       (CAM_DATA4_N )     
+set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD LVCMOS18} [get_ports gp_out[47]]                   ; ## IO_L21P_T3_DQS_33        (CAM_DATA6_P )     
+set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD LVCMOS18} [get_ports gp_out[48]]                   ; ## IO_L21N_T3_DQS_33        (CAM_DATA6_N ) 
+set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD LVCMOS18} [get_ports gp_out[49]]                   ; ## IO_L14P_T2_SRCC_33       (CAM_SYNC_P  )     
+set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD LVCMOS18} [get_ports gp_out[50]]                   ; ## IO_L14N_T2_SRCC_33       (CAM_SYNC_N  )     
+set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD LVCMOS18} [get_ports gp_out[51]]                   ; ## IO_L24P_T3_33            (CAM_SPI_MISO) 
+set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD LVCMOS18} [get_ports gp_out[52]]                   ; ## IO_L24N_T3_33            (CAM_SPI_MOSI) 
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports gp_out[53]]                   ; ## IO_L5P_T0_34             (CAM_GPIO_8  ) 
+                                                                                                                                    
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD LVCMOS25} [get_ports gp_inout[0]]                  ; ## IO_L19P_T3_12            (sfp_gpio[0])
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS25} [get_ports gp_inout[1]]                  ; ## IO_L19N_T3_VREF_12       (sfp_gpio[1])
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gp_inout[2]]                  ; ## IO_L20P_T3_12            (sfp_gpio[2])
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS25} [get_ports gp_inout[3]]                  ; ## IO_L20N_T3_12            (sfp_gpio[3])
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gp_inout[4]]                  ; ## IO_L21P_T3_DQS_12        (sfp_gpio[4])
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gp_inout[5]]                  ; ## IO_L21N_T3_DQS_12        (sfp_gpio[5])
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVCMOS25} [get_ports gp_inout[6]]                  ; ## IO_L22P_T3_12            (sfp_gpio[6])
 
 # clocks
 
-create_clock -name ref_clk_0      -period  4.00 [get_ports gt_ref_clk_0_p]
-create_clock -name ref_clk_1      -period  4.00 [get_ports gt_ref_clk_1_p]
-create_clock -name tx_div_clk_0   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk_0   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-create_clock -name tx_div_clk_1   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk_1   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name ref_clk        -period  4.00 [get_ports gt_ref_clk_p]
+create_clock -name xcvr_clk_0     -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+create_clock -name xcvr_clk_1     -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
 
 
diff --git a/projects/pzsdr/ccfmc/system_project.tcl b/projects/pzsdr/ccfmc/system_project.tcl
index 5550de22b..2cd3504f1 100644
--- a/projects/pzsdr/ccfmc/system_project.tcl
+++ b/projects/pzsdr/ccfmc/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
@@ -14,10 +12,6 @@ adi_project_files ccfmc_pzsdr [list \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
 adi_project_run ccfmc_pzsdr
 
 
diff --git a/projects/pzsdr/ccfmc/system_top.v b/projects/pzsdr/ccfmc/system_top.v
index 95a24d9a1..3cfeaa8ee 100644
--- a/projects/pzsdr/ccfmc/system_top.v
+++ b/projects/pzsdr/ccfmc/system_top.v
@@ -39,254 +39,125 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  eth1_mdc,
-  eth1_mdio,
-  eth1_rgmii_rxclk,
-  eth1_rgmii_rxctl,
-  eth1_rgmii_rxdata,
-  eth1_rgmii_txclk,
-  eth1_rgmii_txctl,
-  eth1_rgmii_txdata,
+  output          eth1_mdc,
+  inout           eth1_mdio,
+  input           eth1_rgmii_rxclk,
+  input           eth1_rgmii_rxctl,
+  input   [ 3:0]  eth1_rgmii_rxdata,
+  output          eth1_rgmii_txclk,
+  output          eth1_rgmii_txctl,
+  output  [ 3:0]  eth1_rgmii_txdata,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
-  hdmi_pd,
-  hdmi_intn,
+  output          hdmi_out_clk,
+  output          hdmi_vsync,
+  output          hdmi_hsync,
+  output          hdmi_data_e,
+  output  [15:0]  hdmi_data,
+  output          hdmi_pd,
+  input           hdmi_intn,
 
-  spdif,
-  spdif_in,
+  output          spdif,
+  input           spdif_in,
 
-  i2s_mclk,
-  i2s_bclk,
-  i2s_lrclk,
-  i2s_sdata_out,
-  i2s_sdata_in,
+  output          i2s_mclk,
+  output          i2s_bclk,
+  output          i2s_lrclk,
+  output          i2s_sdata_out,
+  input           i2s_sdata_in,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  gpio_bd,
+  inout   [11:0]  gpio_bd,
 
-  fan_pwm,
-  fan_tach,
+  output          fan_pwm,
+  input           fan_tach,
 
-  clk_0_p,
-  clk_0_n,
-  clk_1_p,
-  clk_1_n,
-  gp_in_0,
-  gp_inout_0,
-  gp_inout_1,
-  gp_inout,
-  gp_out,
-  gp_in,
+  input           clk_0_p,
+  input           clk_0_n,
+  input           clk_1_p,
+  input           clk_1_n,
+  input           clk_2_p,
+  input           clk_2_n,
+  input           gp_in_0,
+  input           gp_in_1,
+  inout   [ 6:0]  gp_inout,
+  output  [53:0]  gp_out,
+  input   [53:0]  gp_in,
 
-  gt_ref_clk_0_p,
-  gt_ref_clk_0_n,
-  gt_ref_clk_1_p,
-  gt_ref_clk_1_n,
-  gt_tx_0_p,
-  gt_tx_0_n,
-  gt_rx_0_p,
-  gt_rx_0_n,
-  gt_tx_1_p,
-  gt_tx_1_n,
-  gt_rx_1_p,
-  gt_rx_1_n,
+  input           gt_ref_clk_p,
+  input           gt_ref_clk_n,
+  output  [ 1:0]  gt_tx_p,
+  output  [ 1:0]  gt_tx_n,
+  input   [ 1:0]  gt_rx_p,
+  input   [ 1:0]  gt_rx_n,
 
-  ad9517_csn,
-  ad9517_clk,
-  ad9517_mosi,
-  ad9517_miso,
-  ad9517_pdn,
-  ad9517_ref_sel,
-  ad9517_ld,
-  ad9517_status,
+  output          ad9517_csn,
+  output          ad9517_clk,
+  output          ad9517_mosi,
+  input           ad9517_miso,
+  inout           ad9517_pdn,
+  inout           ad9517_ref_sel,
+  inout           ad9517_ld,
+  inout           ad9517_status,
 
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
 
-  enable,
-  txnrx,
-  clk_out,
+  output          enable,
+  output          txnrx,
+  input           clk_out,
+  inout           tdd_sync,
 
-  gpio_rf0,
-  gpio_rf1,
-  gpio_rf2,
-  gpio_rf3,
-  gpio_rfpwr_enable,
-  gpio_clksel,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
+  inout           gpio_rf0,
+  inout           gpio_rf1,
+  inout           gpio_rf2,
+  inout           gpio_rf3,
+  inout           gpio_rfpwr_enable,
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso);
-
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  output          eth1_mdc;
-  inout           eth1_mdio;
-  input           eth1_rgmii_rxclk;
-  input           eth1_rgmii_rxctl;
-  input   [ 3:0]  eth1_rgmii_rxdata;
-  output          eth1_rgmii_txclk;
-  output          eth1_rgmii_txctl;
-  output  [ 3:0]  eth1_rgmii_txdata;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [15:0]  hdmi_data;
-  output          hdmi_pd;
-  input           hdmi_intn;
-
-  output          spdif;
-  input           spdif_in;
-
-  output          i2s_mclk;
-  output          i2s_bclk;
-  output          i2s_lrclk;
-  output          i2s_sdata_out;
-  input           i2s_sdata_in;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  inout   [11:0]  gpio_bd;
-
-  output          fan_pwm;
-  input           fan_tach;
-
-  input           clk_0_p;
-  input           clk_0_n;
-  input           clk_1_p;
-  input           clk_1_n;
-  input           gp_in_0;
-  inout           gp_inout_0;
-  inout           gp_inout_1;
-  inout   [ 6:0]  gp_inout;
-  output  [53:0]  gp_out;
-  input   [53:0]  gp_in;
-
-  input           gt_ref_clk_0_p;
-  input           gt_ref_clk_0_n;
-  input           gt_ref_clk_1_p;
-  input           gt_ref_clk_1_n;
-  output          gt_tx_0_p;
-  output          gt_tx_0_n;
-  input           gt_rx_0_p;
-  input           gt_rx_0_n;
-  output          gt_tx_1_p;
-  output          gt_tx_1_n;
-  input           gt_rx_1_p;
-  input           gt_rx_1_n;
-
-  output          ad9517_csn;
-  output          ad9517_clk;
-  output          ad9517_mosi;
-  input           ad9517_miso;
-  inout           ad9517_pdn;
-  inout           ad9517_ref_sel;
-  inout           ad9517_ld;
-  inout           ad9517_status;
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  output          enable;
-  output          txnrx;
-  input           clk_out;
-
-  inout           gpio_rf0;
-  inout           gpio_rf1;
-  inout           gpio_rf2;
-  inout           gpio_rf3;
-  inout           gpio_rfpwr_enable;
-  inout           gpio_clksel;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso);
 
   // internal signals
 
@@ -296,11 +167,13 @@ module system_top (
   wire            spi_miso_s;
   wire            clk_0;
   wire            clk_1;
-  wire            gt_ref_clk_0;
-  wire            gt_ref_clk_1;
-  wire    [63:0]  gp_ioenb_s;
+  wire            clk_2;
+  wire            gt_ref_clk;
   wire    [63:0]  gp_out_s;
   wire    [63:0]  gp_in_s;
+  wire    [63:0]  gp_misc_out_s;
+  wire    [63:0]  gp_misc_in_s;
+  wire    [63:0]  gp_misc_ioenb_s;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
@@ -320,6 +193,15 @@ module system_top (
   assign ad9517_mosi = spi_mosi_s;
   assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); 
 
+  assign gp_misc_in_s[63:10] = gp_misc_out_s[63:18];
+  assign gp_misc_in_s[9] = gp_in_1;
+  assign gp_misc_in_s[8] = gp_in_0;
+  assign gp_misc_in_s[7] = gp_misc_out_s[7];
+
+  assign gp_out[53:0] = gp_out_s[53:0];
+  assign gp_in_s[63:54] = gp_out_s[63:54];
+  assign gp_in_s[53:0] = gp_in[53:0];
+
   // instantiations
 
   IBUFDS i_ibufds_clk_0 (
@@ -332,48 +214,31 @@ module system_top (
     .IB (clk_1_n),
     .O (clk_1));
 
-  IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 (
+  IBUFDS_GTE2 i_ibufds_clk_2 (
     .CEB (1'd0),
-    .I (gt_ref_clk_0_p),
-    .IB (gt_ref_clk_0_n),
-    .O (gt_ref_clk_0),
+    .I (clk_2_p),
+    .IB (clk_2_n),
+    .O (clk_2),
     .ODIV2 ());
 
-  IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 (
+  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
     .CEB (1'd0),
-    .I (gt_ref_clk_1_p),
-    .IB (gt_ref_clk_1_n),
-    .O (gt_ref_clk_1),
+    .I (gt_ref_clk_p),
+    .IB (gt_ref_clk_n),
+    .O (gt_ref_clk),
     .ODIV2 ());
 
-  assign gp_out[53:0] = gp_out_s[53:0];
-  assign gp_in_s[53:0] = gp_in[53:0];
-
-  assign gp_in_s[63:63] = gp_in_0;
-  assign gp_in_s[62:62] = gp_out_s[62];
-  assign gp_in_s[54:54] = gp_out_s[62] & gpio_tdd_sync_i;
-
-  ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_61_55 (
-    .dio_t (gp_ioenb_s[61:55]),
-    .dio_i (gp_out_s[61:55]),
-    .dio_o (gp_in_s[61:55]),
+  ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_sfp (
+    .dio_t (gp_misc_ioenb_s[6:0]),
+    .dio_i (gp_misc_out_s[6:0]),
+    .dio_o (gp_misc_in_s[6:0]),
     .dio_p (gp_inout));
 
-  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_0 (
-    .dio_t (1'b0),
-    .dio_i (gp_out_s[54]),
-    .dio_o (),
-    .dio_p (gp_inout_0));
-
-  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_1 (
-    .dio_t (gpio_tdd_sync_t),
-    .dio_i (gpio_tdd_sync_o),
-    .dio_o (gpio_tdd_sync_i),
-    .dio_p (gp_inout_1));
-
-  assign gpio_tdd_sync_t = gp_out_s[62] | tdd_sync_t;
-  assign gpio_tdd_sync_o = gp_out_s[62] | tdd_sync_o;
-  assign tdd_sync_i = ~gp_out_s[62] & gpio_tdd_sync_i;
+  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
+    .dio_t (tdd_sync_t),
+    .dio_i (tdd_sync_o),
+    .dio_o (tdd_sync_i),
+    .dio_p (tdd_sync));
 
   ad_iobuf #(.DATA_WIDTH(25)) i_iobuf (
     .dio_t ({gpio_t[60:51], gpio_t[46:32]}),
@@ -404,6 +269,7 @@ module system_top (
   system_wrapper i_system_wrapper (
     .clk_0 (clk_0),
     .clk_1 (clk_1),
+    .clk_2 (clk_2),
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),
     .ddr_cas_n (ddr_cas_n),
@@ -445,23 +311,24 @@ module system_top (
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
     .gp_in_0 (gp_in_s[31:0]),
     .gp_in_1 (gp_in_s[63:32]),
-    .gp_ioenb_0 (gp_ioenb_s[31:0]),
-    .gp_ioenb_1 (gp_ioenb_s[63:32]),
+    .gp_in_2 (gp_misc_in_s[31:0]),
+    .gp_in_3 (gp_misc_in_s[63:32]),
+    .gp_ioenb_0 (),
+    .gp_ioenb_1 (),
+    .gp_ioenb_2 (gp_misc_ioenb_s[31:0]),
+    .gp_ioenb_3 (gp_misc_ioenb_s[63:32]),
     .gp_out_0 (gp_out_s[31:0]),
     .gp_out_1 (gp_out_s[63:32]),
+    .gp_out_2 (gp_misc_out_s[31:0]),
+    .gp_out_3 (gp_misc_out_s[63:32]),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .gt_ref_clk_0 (gt_ref_clk_0),
-    .gt_ref_clk_1 (gt_ref_clk_1),
-    .gt_rx_0_n (gt_rx_0_n),
-    .gt_rx_0_p (gt_rx_0_p),
-    .gt_rx_1_n (gt_rx_1_n),
-    .gt_rx_1_p (gt_rx_1_p),
-    .gt_tx_0_n (gt_tx_0_n),
-    .gt_tx_0_p (gt_tx_0_p),
-    .gt_tx_1_n (gt_tx_1_n),
-    .gt_tx_1_p (gt_tx_1_p),
+    .gt_ref_clk (gt_ref_clk),
+    .gt_rx_n (gt_rx_n),
+    .gt_rx_p (gt_rx_p),
+    .gt_tx_n (gt_tx_n),
+    .gt_tx_p (gt_tx_p),
     .hdmi_data (hdmi_data),
     .hdmi_data_e (hdmi_data_e),
     .hdmi_hsync (hdmi_hsync),
diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr/common/ccfmc_bd.tcl
index dfeff9174..258b47121 100644
--- a/projects/pzsdr/common/ccfmc_bd.tcl
+++ b/projects/pzsdr/common/ccfmc_bd.tcl
@@ -155,127 +155,65 @@ ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
 
 # un-used io (gt)
 
-set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt
+set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb]
+set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pz_xcvrlb
 
-set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0]
-set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1]
+create_bd_port -dir I gt_ref_clk
+create_bd_port -dir I -from 1 -to 0 gt_rx_p
+create_bd_port -dir I -from 1 -to 0 gt_rx_n
+create_bd_port -dir O -from 1 -to 0 gt_tx_p
+create_bd_port -dir O -from 1 -to 0 gt_tx_n
 
-ad_cpu_interconnect 0x44A60000 axi_pzslb_gt
-ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi
-
-create_bd_port -dir I gt_ref_clk_0
-create_bd_port -dir I gt_ref_clk_1
-create_bd_port -dir I gt_rx_0_p
-create_bd_port -dir I gt_rx_0_n
-create_bd_port -dir O gt_tx_0_p
-create_bd_port -dir O gt_tx_0_n
-create_bd_port -dir I gt_rx_1_p
-create_bd_port -dir I gt_rx_1_n
-create_bd_port -dir O gt_tx_1_p
-create_bd_port -dir O gt_tx_1_n
-
-ad_connect  sys_cpu_clk util_pzslb_gtlb_0/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_0/up_rstn
-ad_connect  util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk_0
-ad_connect  util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk_0
-ad_connect  util_pzslb_gtlb_0/rx_p gt_rx_0_p
-ad_connect  util_pzslb_gtlb_0/rx_n gt_rx_0_n
-ad_connect  util_pzslb_gtlb_0/tx_p gt_tx_0_p
-ad_connect  util_pzslb_gtlb_0/tx_n gt_tx_0_n
-ad_connect  sys_cpu_clk util_pzslb_gtlb_1/up_clk
-ad_connect  sys_cpu_resetn util_pzslb_gtlb_1/up_rstn
-ad_connect  util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk_0
-ad_connect  util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk_0
-ad_connect  util_pzslb_gtlb_1/rx_p gt_rx_1_p
-ad_connect  util_pzslb_gtlb_1/rx_n gt_rx_1_n
-ad_connect  util_pzslb_gtlb_1/tx_p gt_tx_1_p
-ad_connect  util_pzslb_gtlb_1/tx_n gt_tx_1_n
-ad_connect  axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0
-ad_connect  axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0
-ad_connect  axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0
-ad_connect  axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0
-ad_connect  axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0
-ad_connect  axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
-ad_connect  axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
-ad_connect  axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0
+ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb
+ad_connect  axi_pz_xcvrlb/ref_clk gt_ref_clk
+ad_connect  axi_pz_xcvrlb/rx_p gt_rx_p
+ad_connect  axi_pz_xcvrlb/rx_n gt_rx_n
+ad_connect  axi_pz_xcvrlb/tx_p gt_tx_p
+ad_connect  axi_pz_xcvrlb/tx_n gt_tx_n
 
 # un-used io (regular)
 
 set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
-set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_CLK_MONS {3}] $axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg
 set_property -dict [list CONFIG.BUF_ENABLE_0 {1}] $axi_gpreg
 set_property -dict [list CONFIG.BUF_ENABLE_1 {1}] $axi_gpreg
 set_property -dict [list CONFIG.BUF_ENABLE_2 {1}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_5 {1}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg
-set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg
-set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg
-
-ad_cpu_interconnect 0x41200000 axi_gpreg
-
-create_bd_port -dir I clk_0
-create_bd_port -dir I clk_1
-ad_connect  clk_0 axi_gpreg/d_clk_0
-ad_connect  clk_1 axi_gpreg/d_clk_1
-ad_connect  gt_ref_clk_0 axi_gpreg/d_clk_2
-ad_connect  util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_3
-ad_connect  util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_4
-ad_connect  gt_ref_clk_1 axi_gpreg/d_clk_5
-ad_connect  util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_6
-ad_connect  util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_7
 
 create_bd_port -dir I -from 31 -to 0 gp_in_0
 create_bd_port -dir I -from 31 -to 0 gp_in_1
+create_bd_port -dir I -from 31 -to 0 gp_in_2
+create_bd_port -dir I -from 31 -to 0 gp_in_3
 create_bd_port -dir O -from 31 -to 0 gp_out_0
 create_bd_port -dir O -from 31 -to 0 gp_out_1
+create_bd_port -dir O -from 31 -to 0 gp_out_2
+create_bd_port -dir O -from 31 -to 0 gp_out_3
 create_bd_port -dir O -from 31 -to 0 gp_ioenb_0
 create_bd_port -dir O -from 31 -to 0 gp_ioenb_1
+create_bd_port -dir O -from 31 -to 0 gp_ioenb_2
+create_bd_port -dir O -from 31 -to 0 gp_ioenb_3
+create_bd_port -dir I clk_0
+create_bd_port -dir I clk_1
+create_bd_port -dir I clk_2
 
+ad_connect  clk_0 axi_gpreg/d_clk_0
+ad_connect  clk_1 axi_gpreg/d_clk_1
+ad_connect  clk_2 axi_gpreg/d_clk_2
 ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
 ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
+ad_connect  gp_in_2 axi_gpreg/up_gp_in_2
+ad_connect  gp_in_3 axi_gpreg/up_gp_in_3
 ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
 ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
+ad_connect  gp_out_2 axi_gpreg/up_gp_out_2
+ad_connect  gp_out_3 axi_gpreg/up_gp_out_3
 ad_connect  gp_ioenb_0 axi_gpreg/up_gp_ioenb_0
 ad_connect  gp_ioenb_1 axi_gpreg/up_gp_ioenb_1
-ad_connect  axi_gpreg/up_gp_in_2 util_pzslb_gtlb_0/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_2 util_pzslb_gtlb_0/up_gp_in
-ad_connect  axi_gpreg/up_gp_in_3 util_pzslb_gtlb_1/up_gp_out
-ad_connect  axi_gpreg/up_gp_out_3 util_pzslb_gtlb_1/up_gp_in
+ad_connect  gp_ioenb_2 axi_gpreg/up_gp_ioenb_2
+ad_connect  gp_ioenb_3 axi_gpreg/up_gp_ioenb_3
+ad_cpu_interconnect 0x41200000 axi_gpreg
 
 ## temporary (remove ila indirectly)
 
 delete_bd_objs [get_bd_cells ila_adc]
-delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
 

From df37a23a489db10e77bd93d39ae6d72a6574cf03 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 22 Sep 2016 11:38:43 -0400
Subject: [PATCH 518/972] pzsdr/ccfmc- rgmii critical warnings fix

---
 projects/pzsdr/ccfmc/system_top.v  |  8 --------
 projects/pzsdr/common/ccfmc_bd.tcl | 16 ----------------
 2 files changed, 24 deletions(-)

diff --git a/projects/pzsdr/ccfmc/system_top.v b/projects/pzsdr/ccfmc/system_top.v
index 3cfeaa8ee..05dd525aa 100644
--- a/projects/pzsdr/ccfmc/system_top.v
+++ b/projects/pzsdr/ccfmc/system_top.v
@@ -286,23 +286,15 @@ module system_top (
     .ddr_reset_n (ddr_reset_n),
     .ddr_we_n (ddr_we_n),
     .enable (enable),
-    .eth1_125mclk (),
-    .eth1_25mclk (),
-    .eth1_2m5clk (),
-    .eth1_clock_speed (),
-    .eth1_duplex_status (),
     .eth1_intn (1'b1),
-    .eth1_link_status (),
     .eth1_mdio_mdc (eth1_mdc),
     .eth1_mdio_mdio_io (eth1_mdio),
-    .eth1_refclk (),
     .eth1_rgmii_rd (eth1_rgmii_rxdata),
     .eth1_rgmii_rx_ctl (eth1_rgmii_rxctl),
     .eth1_rgmii_rxc (eth1_rgmii_rxclk),
     .eth1_rgmii_td (eth1_rgmii_txdata),
     .eth1_rgmii_tx_ctl (eth1_rgmii_txctl),
     .eth1_rgmii_txc (eth1_rgmii_txclk),
-    .eth1_speed_mode (),
     .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
     .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
     .fixed_io_mio (fixed_io_mio),
diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr/common/ccfmc_bd.tcl
index 258b47121..2af9f4dc3 100644
--- a/projects/pzsdr/common/ccfmc_bd.tcl
+++ b/projects/pzsdr/common/ccfmc_bd.tcl
@@ -5,15 +5,7 @@
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 eth1_mdio
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii
 
-create_bd_port -dir O eth1_link_status
-create_bd_port -dir O eth1_duplex_status
-create_bd_port -dir O -type clk eth1_refclk
-create_bd_port -dir O -type clk eth1_125mclk
-create_bd_port -dir O -type clk eth1_25mclk
-create_bd_port -dir O -type clk eth1_2m5clk
 create_bd_port -dir I -type intr eth1_intn
-create_bd_port -dir O -from 1 -to 0 eth1_clock_speed
-create_bd_port -dir O -from 1 -to 0 eth1_speed_mode
 
 # hdmi interface
 
@@ -80,14 +72,6 @@ ad_connect  sys_ps7/MDIO_ETHERNET_1 sys_rgmii/MDIO_GEM
 ad_connect  sys_ps7/GMII_ETHERNET_1 sys_rgmii/GMII
 ad_connect  sys_rgmii/MDIO_PHY eth1_mdio
 ad_connect  sys_rgmii/RGMII eth1_rgmii
-ad_connect  sys_rgmii/ref_clk_out eth1_refclk
-ad_connect  sys_rgmii/gmii_clk_125m_out eth1_125mclk
-ad_connect  sys_rgmii/gmii_clk_25m_out eth1_25mclk
-ad_connect  sys_rgmii/gmii_clk_2_5m_out eth1_2m5clk
-ad_connect  sys_rgmii/link_status eth1_link_status
-ad_connect  sys_rgmii/duplex_status eth1_duplex_status
-ad_connect  sys_rgmii/clock_speed eth1_clock_speed
-ad_connect  sys_rgmii/speed_mode eth1_speed_mode
 ad_connect  sys_ps7/ENET1_EXT_INTIN eth1_intn
 ad_connect  sys_200m_clk sys_rgmii_rstgen/slowest_sync_clk
 ad_connect  sys_200m_clk sys_rgmii/clkin

From 78f7384150ad38afde1ffa695f011763685b4376 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 22 Sep 2016 13:41:18 -0400
Subject: [PATCH 519/972] ad9361- vivado synthesis warnings fix

---
 library/axi_ad9361/axi_ad9361_rx_channel.v |  3 ---
 library/axi_ad9361/axi_ad9361_tx_channel.v |  3 +--
 library/common/up_adc_common.v             | 13 ++++++------
 library/common/up_delay_cntrl.v            | 23 ++++++++++++----------
 4 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_rx_channel.v b/library/axi_ad9361/axi_ad9361_rx_channel.v
index 558ea2a80..ecffad89a 100644
--- a/library/axi_ad9361/axi_ad9361_rx_channel.v
+++ b/library/axi_ad9361/axi_ad9361_rx_channel.v
@@ -34,9 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ADC channel-need to work on dual mode for pn sequence
 
 `timescale 1ns/100ps
 
diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v
index f64859640..53d63f473 100644
--- a/library/axi_ad9361/axi_ad9361_tx_channel.v
+++ b/library/axi_ad9361/axi_ad9361_tx_channel.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -389,6 +387,7 @@ module axi_ad9361_tx_channel (
     .dac_pat_data_1 (dac_pat_data_1_s),
     .dac_pat_data_2 (dac_pat_data_2_s),
     .dac_data_sel (dac_data_sel_s),
+    .dac_iq_mode (),
     .dac_iqcor_enb (dac_iqcor_enb_s),
     .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
     .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index 787b727ea..d2158813c 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -163,6 +163,7 @@ module up_adc_common (
   reg     [31:0]  up_scratch = 'd0;
   reg             up_mmcm_resetn = 'd0;
   reg             up_resetn = 'd0;
+  reg             up_adc_sync = 'd0;
   reg             up_adc_r1_mode = 'd0;
   reg             up_adc_ddr_edgesel = 'd0;
   reg             up_adc_pin_mode = 'd0;
@@ -176,9 +177,8 @@ module up_adc_common (
   reg             up_status_ovf = 'd0;
   reg             up_status_unf = 'd0;
   reg     [ 7:0]  up_usr_chanmax = 'd0;
-  reg     [31:0]  up_adc_gpio_out = 'd0;
   reg     [31:0]  up_adc_start_code = 'd0;
-  reg             up_adc_sync = 'd0;
+  reg     [31:0]  up_adc_gpio_out = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
 
@@ -190,7 +190,7 @@ module up_adc_common (
   wire            up_sync_status_s;
   wire            up_status_ovf_s;
   wire            up_status_unf_s;
-  wire            up_cntrl_xfer_done;
+  wire            up_cntrl_xfer_done_s;
   wire    [31:0]  up_adc_clk_count_s;
 
   // decode block select
@@ -208,6 +208,7 @@ module up_adc_common (
       up_scratch <= 'd0;
       up_mmcm_resetn <= 'd0;
       up_resetn <= 'd0;
+      up_adc_sync <= 'd0;
       up_adc_r1_mode <= 'd0;
       up_adc_ddr_edgesel <= 'd0;
       up_adc_pin_mode <= 'd0;
@@ -221,8 +222,8 @@ module up_adc_common (
       up_status_ovf <= 'd0;
       up_status_unf <= 'd0;
       up_usr_chanmax <= 'd0;
-      up_adc_gpio_out <= 'd0;
       up_adc_start_code <= 'd0;
+      up_adc_gpio_out <= 'd0;
     end else begin
       up_core_preset <= ~up_resetn;
       up_mmcm_preset <= ~up_mmcm_resetn;
@@ -235,7 +236,7 @@ module up_adc_common (
         up_resetn <= up_wdata[0];
       end
       if (up_adc_sync == 1'b1) begin
-        if (up_cntrl_xfer_done == 1'b1) begin
+        if (up_cntrl_xfer_done_s == 1'b1) begin
           up_adc_sync <= 1'b0;
         end
       end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
@@ -342,7 +343,7 @@ module up_adc_common (
                       up_adc_r1_mode,
                       up_adc_ddr_edgesel,
                       up_adc_pin_mode}),
-    .up_xfer_done (up_cntrl_xfer_done),
+    .up_xfer_done (up_cntrl_xfer_done_s),
     .d_rst (adc_rst),
     .d_clk (adc_clk),
     .d_data_cntrl ({  adc_sync,
diff --git a/library/common/up_delay_cntrl.v b/library/common/up_delay_cntrl.v
index e4dfbe6ef..ab63c9a9f 100644
--- a/library/common/up_delay_cntrl.v
+++ b/library/common/up_delay_cntrl.v
@@ -115,6 +115,8 @@ module up_delay_cntrl (
   wire    [(DATA_WIDTH-1):0]      up_drdata2_s;
   wire    [(DATA_WIDTH-1):0]      up_drdata1_s;
   wire    [(DATA_WIDTH-1):0]      up_drdata0_s;
+  wire    [(DATA_WIDTH-1):0]      up_dld_s;
+  wire    [((DATA_WIDTH*5)-1):0]  up_dwdata_s;
 
   // variables
 
@@ -172,22 +174,23 @@ module up_delay_cntrl (
 
   generate
   for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
+  assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0;
+  assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ?
+    up_wdata[4:0] : up_dwdata[((n*5)+4):(n*5)];
+  end
+  endgenerate
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_dld[n] <= 'd0;
-      up_dwdata[((n*5)+4):(n*5)] <= 'd0;
+      up_dld <= 'd0;
+      up_dwdata <= 'd0;
     end else begin
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin
-        up_dld[n] <= 1'd1;
-        up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0];
-      end else begin
-        up_dld[n] <= 1'd0;
-        up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)];
+      up_dld <= up_dld_s;
+      if (up_wreq_s == 1'b1) begin
+        up_dwdata <= up_dwdata_s;
       end
     end
   end
-  end
-  endgenerate
 
   // resets
 

From 8729af1b919b8b2fafc8e9cbede1fc267d380ce6 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 23 Sep 2016 13:40:35 -0400
Subject: [PATCH 520/972] common- adc- data path disable split

---
 library/common/ad_datafmt.v     |  85 +++---
 library/common/ad_dcfilter.v    |  71 ++---
 library/common/ad_iqcor.v       |  62 ++--
 library/common/up_adc_channel.v | 491 +++++++++++++++++++-------------
 library/common/up_adc_common.v  | 318 +++++++++++----------
 5 files changed, 560 insertions(+), 467 deletions(-)

diff --git a/library/common/ad_datafmt.v b/library/common/ad_datafmt.v
index c92350f7c..28a5ee2cb 100644
--- a/library/common/ad_datafmt.v
+++ b/library/common/ad_datafmt.v
@@ -34,72 +34,73 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 // data format (offset binary or 2's complement only)
 
 `timescale 1ps/1ps
 
-module ad_datafmt (
+module ad_datafmt #(
+
+  // data bus width
+
+  parameter   DATA_WIDTH = 16,
+  parameter   DISABLE = 0) (
 
   // data path
 
-  clk,
-  valid,
-  data,
-  valid_out,
-  data_out,
+  input                       clk,
+  input                       valid,
+  input   [(DATA_WIDTH-1):0]  data,
+  output                      valid_out,
+  output  [15:0]              data_out,
 
   // control signals
 
-  dfmt_enable,
-  dfmt_type,
-  dfmt_se);
-
-  // delayed data bus width
-
-  parameter   DATA_WIDTH = 16;
-  localparam  DW = DATA_WIDTH - 1;
-
-  // data path
-
-  input           clk;
-  input           valid;
-  input   [DW:0]  data;
-  output          valid_out;
-  output  [15:0]  data_out;
-
-  // control signals
-
-  input           dfmt_enable;
-  input           dfmt_type;
-  input           dfmt_se;
+  input                       dfmt_enable,
+  input                       dfmt_type,
+  input                       dfmt_se);
 
   // internal registers
 
-  reg             valid_out = 'd0;
-  reg     [15:0]  data_out = 'd0;
+  reg                         valid_int = 'd0;
+  reg     [15:0]              data_int = 'd0;
 
   // internal signals
 
-  wire            type_s;
-  wire            signext_s;
-  wire    [DW:0]  data_s;
-  wire    [23:0]  sign_s;
-  wire    [23:0]  data_out_s;
+  wire                        type_s;
+  wire                        signext_s;
+  wire                        sign_s;
+  wire    [15:0]              data_out_s;
+
+  // data-path disable
+
+  generate
+  if (DISABLE == 1) begin
+  assign valid_out = valid;
+  assign data_out = data;
+  end else begin
+  assign valid_out = valid_int;
+  assign data_out = data_int;
+  end
+  endgenerate
 
   // if offset-binary convert to 2's complement first
 
   assign type_s = dfmt_enable & dfmt_type;
   assign signext_s = dfmt_enable & dfmt_se;
+  assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
 
-  assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data;
-  assign sign_s = (signext_s == 1'b1) ? {{24{data_s[DW]}}} : 24'd0;
-  assign data_out_s = {sign_s[23:(DW+1)], data_s};
+  generate
+  if (DATA_WIDTH < 16) begin
+  assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
+  end
+  endgenerate
+  
+  assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)];
+  assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0];
 
   always @(posedge clk) begin
-    valid_out <= valid;
-    data_out <= data_out_s[15:0];
+    valid_int <= valid;
+    data_int <= data_out_s[15:0];
   end
 
 endmodule
diff --git a/library/common/ad_dcfilter.v b/library/common/ad_dcfilter.v
index 5ee1909ed..70795286c 100644
--- a/library/common/ad_dcfilter.v
+++ b/library/common/ad_dcfilter.v
@@ -34,44 +34,33 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 // dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
 
 `timescale 1ps/1ps
 
-module ad_dcfilter (
+module ad_dcfilter #(
+
+  // data path disable
+
+  parameter   DISABLE = 0) (
 
   // data interface
 
-  clk,
-  valid,
-  data,
-  valid_out,
-  data_out,
+  input           clk,
+  input           valid,
+  input   [15:0]  data,
+  output          valid_out,
+  output  [15:0]  data_out,
 
   // control interface
 
-  dcfilt_enb,
-  dcfilt_coeff,
-  dcfilt_offset);
-
-  // data interface
-
-  input           clk;
-  input           valid;
-  input   [15:0]  data;
-  output          valid_out;
-  output  [15:0]  data_out;
-
-  // control interface
-
-  input           dcfilt_enb;
-  input   [15:0]  dcfilt_coeff;
-  input   [15:0]  dcfilt_offset;
+  input           dcfilt_enb,
+  input   [15:0]  dcfilt_coeff,
+  input   [15:0]  dcfilt_offset);
 
   // internal registers
 
+  reg     [15:0]  dcfilt_coeff_d = 'd0;
   reg     [47:0]  dc_offset = 'd0;
   reg     [47:0]  dc_offset_d = 'd0;
   reg             valid_d = 'd0;
@@ -79,21 +68,33 @@ module ad_dcfilter (
   reg             valid_2d = 'd0;
   reg     [15:0]  data_2d = 'd0;
   reg     [15:0]  data_dcfilt = 'd0;
-  reg             valid_out = 'd0;
-  reg     [15:0]  data_out = 'd0;
-  reg     [15:0]  dcfilt_coeff_r;
+  reg             valid_int = 'd0;
+  reg     [15:0]  data_int = 'd0;
 
   // internal signals
 
   wire    [47:0]  dc_offset_s;
 
-  // cancelling the dc offset
+  // data-path disable
+
+  generate
+  if (DISABLE == 1) begin
+  assign valid_out = valid;
+  assign data_out = data;
+  end else begin
+  assign valid_out = valid_int;
+  assign data_out = data_int;
+  end
+  endgenerate
 
   // dcfilt_coeff is flopped so to remove warnings from vivado
+
   always @(posedge clk) begin
-    dcfilt_coeff_r <= dcfilt_coeff;
+    dcfilt_coeff_d <= dcfilt_coeff;
   end
 
+  // removing dc offset
+
   always @(posedge clk) begin
     dc_offset   <= dc_offset_s;
     dc_offset_d <= dc_offset;
@@ -105,11 +106,11 @@ module ad_dcfilter (
     data_2d  <= data_d;
     data_dcfilt <= data_d - dc_offset[32:17];
     if (dcfilt_enb == 1'b1) begin
-      valid_out <= valid_2d;
-      data_out  <= data_dcfilt;
+      valid_int <= valid_2d;
+      data_int  <= data_dcfilt;
     end else begin
-      valid_out <= valid_2d;
-      data_out  <= data_2d;
+      valid_int <= valid_2d;
+      data_int  <= data_2d;
     end
   end
 
@@ -144,7 +145,7 @@ module ad_dcfilter (
   i_dsp48e1 (
     .CLK (clk),
     .A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}),
-    .B ({{2{dcfilt_coeff_r[15]}}, dcfilt_coeff_r}),
+    .B ({{2{dcfilt_coeff_d[15]}}, dcfilt_coeff_d}),
     .C (dc_offset_d),
     .D ({{9{data_d[15]}}, data_d}),
     .MULTSIGNIN (1'd0),
diff --git a/library/common/ad_iqcor.v b/library/common/ad_iqcor.v
index 5d78a9aad..d8543e972 100644
--- a/library/common/ad_iqcor.v
+++ b/library/common/ad_iqcor.v
@@ -38,41 +38,27 @@
 
 `timescale 1ns/100ps
 
-module ad_iqcor (
-
-  // data interface
-
-  clk,
-  valid,
-  data_in,
-  data_iq,
-  valid_out,
-  data_out,
-
-  // control interface
-
-  iqcor_enable,
-  iqcor_coeff_1,
-  iqcor_coeff_2);
+module ad_iqcor #(
 
   // select i/q if disabled
 
-  parameter Q_OR_I_N = 0;
+  parameter   Q_OR_I_N = 0,
+  parameter   DISABLE = 0) (
 
   // data interface
 
-  input           clk;
-  input           valid;
-  input   [15:0]  data_in;
-  input   [15:0]  data_iq;
-  output          valid_out;
-  output  [15:0]  data_out;
+  input           clk,
+  input           valid,
+  input   [15:0]  data_in,
+  input   [15:0]  data_iq,
+  output          valid_out,
+  output  [15:0]  data_out,
 
   // control interface
 
-  input           iqcor_enable;
-  input   [15:0]  iqcor_coeff_1;
-  input   [15:0]  iqcor_coeff_2;
+  input           iqcor_enable,
+  input   [15:0]  iqcor_coeff_1,
+  input   [15:0]  iqcor_coeff_2);
 
   // internal registers
 
@@ -80,8 +66,8 @@ module ad_iqcor (
   reg     [15:0]  p1_data_i = 'd0;
   reg     [15:0]  p1_data_q = 'd0;
   reg     [33:0]  p1_data_p = 'd0;
-  reg             valid_out = 'd0;
-  reg     [15:0]  data_out = 'd0;
+  reg             valid_int = 'd0;
+  reg     [15:0]  data_int = 'd0;
   reg     [15:0]  iqcor_coeff_1_r = 'd0;
   reg     [15:0]  iqcor_coeff_2_r = 'd0;
 
@@ -95,6 +81,18 @@ module ad_iqcor (
   wire    [33:0]  p1_data_p_q_s;
   wire    [15:0]  p1_data_q_s;
 
+  // data-path disable
+
+  generate
+  if (DISABLE == 1) begin
+  assign valid_out = valid;
+  assign data_out = data_in;
+  end else begin
+  assign valid_out = valid_int;
+  assign data_out = data_int;
+  end
+  endgenerate
+
   // swap i & q
 
   assign data_i_s = (Q_OR_I_N == 1) ? data_iq : data_in;
@@ -139,13 +137,13 @@ module ad_iqcor (
   // output registers
 
   always @(posedge clk) begin
-    valid_out <= p1_valid;
+    valid_int <= p1_valid;
     if (iqcor_enable == 1'b1) begin
-      data_out <= p1_data_p[29:14];
+      data_int <= p1_data_p[29:14];
     end else if (Q_OR_I_N == 1) begin
-      data_out <= p1_data_q;
+      data_int <= p1_data_q;
     end else begin
-      data_out <= p1_data_i;
+      data_int <= p1_data_i;
     end
   end
 
diff --git a/library/common/up_adc_channel.v b/library/common/up_adc_channel.v
index f52319ab9..06004bc98 100644
--- a/library/common/up_adc_channel.v
+++ b/library/common/up_adc_channel.v
@@ -34,127 +34,76 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
-module up_adc_channel (
-
-  // adc interface
-
-  adc_clk,
-  adc_rst,
-  adc_enable,
-  adc_iqcor_enb,
-  adc_dcfilt_enb,
-  adc_dfmt_se,
-  adc_dfmt_type,
-  adc_dfmt_enable,
-  adc_dcfilt_offset,
-  adc_dcfilt_coeff,
-  adc_iqcor_coeff_1,
-  adc_iqcor_coeff_2,
-  adc_pnseq_sel,
-  adc_data_sel,
-  adc_pn_err,
-  adc_pn_oos,
-  adc_or,
-  up_adc_pn_err,
-  up_adc_pn_oos,
-  up_adc_or,
-
-  // user controls
-
-  up_usr_datatype_be,
-  up_usr_datatype_signed,
-  up_usr_datatype_shift,
-  up_usr_datatype_total_bits,
-  up_usr_datatype_bits,
-  up_usr_decimation_m,
-  up_usr_decimation_n,
-  adc_usr_datatype_be,
-  adc_usr_datatype_signed,
-  adc_usr_datatype_shift,
-  adc_usr_datatype_total_bits,
-  adc_usr_datatype_bits,
-  adc_usr_decimation_m,
-  adc_usr_decimation_n,
-
-  // bus interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module up_adc_channel #(
 
   // parameters
 
-  parameter ADC_COMMON_ID = 6'h01;
-  parameter ADC_CHANNEL_ID = 4'h0;
+  parameter   COMMON_ID = 6'h01,
+  parameter   CHANNEL_ID = 4'h0,
+  parameter   USERPORTS_DISABLE = 0,
+  parameter   DATAFORMAT_DISABLE = 0,
+  parameter   DCFILTER_DISABLE = 0,
+  parameter   IQCORRECTION_DISABLE = 0) (
 
   // adc interface
 
-  input           adc_clk;
-  input           adc_rst;
-  output          adc_enable;
-  output          adc_iqcor_enb;
-  output          adc_dcfilt_enb;
-  output          adc_dfmt_se;
-  output          adc_dfmt_type;
-  output          adc_dfmt_enable;
-  output  [15:0]  adc_dcfilt_offset;
-  output  [15:0]  adc_dcfilt_coeff;
-  output  [15:0]  adc_iqcor_coeff_1;
-  output  [15:0]  adc_iqcor_coeff_2;
-  output  [ 3:0]  adc_pnseq_sel;
-  output  [ 3:0]  adc_data_sel;
-  input           adc_pn_err;
-  input           adc_pn_oos;
-  input           adc_or;
-  output          up_adc_pn_err;
-  output          up_adc_pn_oos;
-  output          up_adc_or;
+  input           adc_clk,
+  input           adc_rst,
+  output          adc_enable,
+  output          adc_iqcor_enb,
+  output          adc_dcfilt_enb,
+  output          adc_dfmt_se,
+  output          adc_dfmt_type,
+  output          adc_dfmt_enable,
+  output  [15:0]  adc_dcfilt_offset,
+  output  [15:0]  adc_dcfilt_coeff,
+  output  [15:0]  adc_iqcor_coeff_1,
+  output  [15:0]  adc_iqcor_coeff_2,
+  output  [ 3:0]  adc_pnseq_sel,
+  output  [ 3:0]  adc_data_sel,
+  input           adc_pn_err,
+  input           adc_pn_oos,
+  input           adc_or,
+  output          up_adc_pn_err,
+  output          up_adc_pn_oos,
+  output          up_adc_or,
 
   // user controls
 
-  output          up_usr_datatype_be;
-  output          up_usr_datatype_signed;
-  output  [ 7:0]  up_usr_datatype_shift;
-  output  [ 7:0]  up_usr_datatype_total_bits;
-  output  [ 7:0]  up_usr_datatype_bits;
-  output  [15:0]  up_usr_decimation_m;
-  output  [15:0]  up_usr_decimation_n;
-  input           adc_usr_datatype_be;
-  input           adc_usr_datatype_signed;
-  input   [ 7:0]  adc_usr_datatype_shift;
-  input   [ 7:0]  adc_usr_datatype_total_bits;
-  input   [ 7:0]  adc_usr_datatype_bits;
-  input   [15:0]  adc_usr_decimation_m;
-  input   [15:0]  adc_usr_decimation_n;
+  output          up_usr_datatype_be,
+  output          up_usr_datatype_signed,
+  output  [ 7:0]  up_usr_datatype_shift,
+  output  [ 7:0]  up_usr_datatype_total_bits,
+  output  [ 7:0]  up_usr_datatype_bits,
+  output  [15:0]  up_usr_decimation_m,
+  output  [15:0]  up_usr_decimation_n,
+  input           adc_usr_datatype_be,
+  input           adc_usr_datatype_signed,
+  input   [ 7:0]  adc_usr_datatype_shift,
+  input   [ 7:0]  adc_usr_datatype_total_bits,
+  input   [ 7:0]  adc_usr_datatype_bits,
+  input   [15:0]  adc_usr_decimation_m,
+  input   [15:0]  adc_usr_decimation_n,
 
   // bus interface
 
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
 
   // internal registers
 
-  reg             up_wack = 'd0;
+  reg             up_wack_int = 'd0;
   reg             up_adc_lb_enb = 'd0;
   reg             up_adc_pn_sel = 'd0;
   reg             up_adc_iqcor_enb = 'd0;
@@ -164,24 +113,24 @@ module up_adc_channel (
   reg             up_adc_dfmt_enable = 'd0;
   reg             up_adc_pn_type = 'd0;
   reg             up_adc_enable = 'd0;
-  reg             up_adc_pn_err = 'd0;
-  reg             up_adc_pn_oos = 'd0;
-  reg             up_adc_or = 'd0;
+  reg             up_adc_pn_err_int = 'd0;
+  reg             up_adc_pn_oos_int = 'd0;
+  reg             up_adc_or_int = 'd0;
   reg     [15:0]  up_adc_dcfilt_offset = 'd0;
   reg     [15:0]  up_adc_dcfilt_coeff = 'd0;
   reg     [15:0]  up_adc_iqcor_coeff_1 = 'd0;
   reg     [15:0]  up_adc_iqcor_coeff_2 = 'd0;
   reg     [ 3:0]  up_adc_pnseq_sel = 'd0;
   reg     [ 3:0]  up_adc_data_sel = 'd0;
-  reg             up_usr_datatype_be = 'd0;
-  reg             up_usr_datatype_signed = 'd0;
-  reg     [ 7:0]  up_usr_datatype_shift = 'd0;
-  reg     [ 7:0]  up_usr_datatype_total_bits = 'd0;
-  reg     [ 7:0]  up_usr_datatype_bits = 'd0;
-  reg     [15:0]  up_usr_decimation_m = 'd0;
-  reg     [15:0]  up_usr_decimation_n = 'd0;
-  reg             up_rack = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
+  reg             up_usr_datatype_be_int = 'd0;
+  reg             up_usr_datatype_signed_int = 'd0;
+  reg     [ 7:0]  up_usr_datatype_shift_int = 'd0;
+  reg     [ 7:0]  up_usr_datatype_total_bits_int = 'd0;
+  reg     [ 7:0]  up_usr_datatype_bits_int = 'd0;
+  reg     [15:0]  up_usr_decimation_m_int = 'd0;
+  reg     [15:0]  up_usr_decimation_n_int = 'd0;
+  reg             up_rack_int = 'd0;
+  reg     [31:0]  up_rdata_int = 'd0;
   reg     [15:0]  up_adc_iqcor_coeff_tc_1 = 'd0;
   reg     [15:0]  up_adc_iqcor_coeff_tc_2 = 'd0;
   reg     [ 3:0]  up_adc_pnseq_sel_m = 'd0;
@@ -210,121 +159,253 @@ module up_adc_channel (
     end
   endfunction
 
+  // up control/status
+
+  assign up_adc_pn_err = up_adc_pn_err_int;
+  assign up_adc_pn_oos = up_adc_pn_oos_int;
+  assign up_adc_or = up_adc_or_int;
+  assign up_usr_datatype_be = up_usr_datatype_be_int;
+  assign up_usr_datatype_signed = up_usr_datatype_signed_int;
+  assign up_usr_datatype_shift = up_usr_datatype_shift_int;
+  assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int;
+  assign up_usr_datatype_bits = up_usr_datatype_bits_int;
+  assign up_usr_decimation_m = up_usr_decimation_m_int;
+  assign up_usr_decimation_n = up_usr_decimation_n_int;
+
   // decode block select
 
-  assign up_wreq_s = ((up_waddr[13:8] == ADC_COMMON_ID) && (up_waddr[7:4] == ADC_CHANNEL_ID)) ? up_wreq : 1'b0;
-  assign up_rreq_s = ((up_raddr[13:8] == ADC_COMMON_ID) && (up_raddr[7:4] == ADC_CHANNEL_ID)) ? up_rreq : 1'b0;
+  assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0;
+  assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0;
 
   // processor write interface
 
+  assign up_wack = up_wack_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_wack <= 'd0;
+      up_wack_int <= 'd0;
       up_adc_lb_enb <= 'd0;
       up_adc_pn_sel <= 'd0;
-      up_adc_iqcor_enb <= 'd0;
-      up_adc_dcfilt_enb <= 'd0;
-      up_adc_dfmt_se <= 'd0;
-      up_adc_dfmt_type <= 'd0;
-      up_adc_dfmt_enable <= 'd0;
-      up_adc_pn_type <= 'd0;
-      up_adc_enable <= 'd0;
-      up_adc_pn_err <= 'd0;
-      up_adc_pn_oos <= 'd0;
-      up_adc_or <= 'd0;
-      up_adc_dcfilt_offset <= 'd0;
-      up_adc_dcfilt_coeff <= 'd0;
-      up_adc_iqcor_coeff_1 <= 'd0;
-      up_adc_iqcor_coeff_2 <= 'd0;
-      up_adc_pnseq_sel <= 'd0;
-      up_adc_data_sel <= 'd0;
-      up_usr_datatype_be <= 'd0;
-      up_usr_datatype_signed <= 'd0;
-      up_usr_datatype_shift <= 'd0;
-      up_usr_datatype_total_bits <= 'd0;
-      up_usr_datatype_bits <= 'd0;
-      up_usr_decimation_m <= 'd0;
-      up_usr_decimation_n <= 'd0;
     end else begin
-      up_wack <= up_wreq_s;
+      up_wack_int <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
         up_adc_lb_enb <= up_wdata[11];
         up_adc_pn_sel <= up_wdata[10];
-        up_adc_iqcor_enb <= up_wdata[9];
-        up_adc_dcfilt_enb <= up_wdata[8];
-        up_adc_dfmt_se <= up_wdata[6];
-        up_adc_dfmt_type <= up_wdata[5];
-        up_adc_dfmt_enable <= up_wdata[4];
-        up_adc_pn_type <= up_wdata[1];
-        up_adc_enable <= up_wdata[0];
-      end
-      if (up_adc_pn_err_s == 1'b1) begin
-        up_adc_pn_err <= 1'b1;
-      end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
-        up_adc_pn_err <= up_adc_pn_err & ~up_wdata[2];
-      end
-      if (up_adc_pn_oos_s == 1'b1) begin
-        up_adc_pn_oos <= 1'b1;
-      end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
-        up_adc_pn_oos <= up_adc_pn_oos & ~up_wdata[1];
-      end
-      if (up_adc_or_s == 1'b1) begin
-        up_adc_or <= 1'b1;
-      end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
-        up_adc_or <= up_adc_or & ~up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
-        up_adc_dcfilt_offset <= up_wdata[31:16];
-        up_adc_dcfilt_coeff <= up_wdata[15:0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
-        up_adc_iqcor_coeff_1 <= up_wdata[31:16];
-        up_adc_iqcor_coeff_2 <= up_wdata[15:0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
-        up_adc_pnseq_sel <= up_wdata[19:16];
-        up_adc_data_sel <= up_wdata[3:0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
-        up_usr_datatype_be <= up_wdata[25];
-        up_usr_datatype_signed <= up_wdata[24];
-        up_usr_datatype_shift <= up_wdata[23:16];
-        up_usr_datatype_total_bits <= up_wdata[15:8];
-        up_usr_datatype_bits <= up_wdata[7:0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin
-        up_usr_decimation_m <= up_wdata[31:16];
-        up_usr_decimation_n <= up_wdata[15:0];
       end
     end
   end
 
-  // processor read interface
+  generate
+  if (IQCORRECTION_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_adc_iqcor_enb <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_adc_iqcor_enb <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
+        up_adc_iqcor_enb <= up_wdata[9];
+      end
+    end
+  end
+  end
+  endgenerate
+
+  generate
+  if (DCFILTER_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_adc_dcfilt_enb <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_adc_dcfilt_enb <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
+        up_adc_dcfilt_enb <= up_wdata[8];
+      end
+    end
+  end
+  end
+  endgenerate
+
+  generate
+  if (DATAFORMAT_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_adc_dfmt_se <= 'd0;
+    up_adc_dfmt_type <= 'd0;
+    up_adc_dfmt_enable <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_adc_dfmt_se <= 'd0;
+      up_adc_dfmt_type <= 'd0;
+      up_adc_dfmt_enable <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
+        up_adc_dfmt_se <= up_wdata[6];
+        up_adc_dfmt_type <= up_wdata[5];
+        up_adc_dfmt_enable <= up_wdata[4];
+      end
+    end
+  end
+  end
+  endgenerate
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
+      up_adc_pn_type <= 'd0;
+      up_adc_enable <= 'd0;
+      up_adc_pn_err_int <= 'd0;
+      up_adc_pn_oos_int <= 'd0;
+      up_adc_or_int <= 'd0;
     end else begin
-      up_rack <= up_rreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
+        up_adc_pn_type <= up_wdata[1];
+        up_adc_enable <= up_wdata[0];
+      end
+      if (up_adc_pn_err_s == 1'b1) begin
+        up_adc_pn_err_int <= 1'b1;
+      end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
+        up_adc_pn_err_int <= up_adc_pn_err_int & ~up_wdata[2];
+      end
+      if (up_adc_pn_oos_s == 1'b1) begin
+        up_adc_pn_oos_int <= 1'b1;
+      end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
+        up_adc_pn_oos_int <= up_adc_pn_oos_int & ~up_wdata[1];
+      end
+      if (up_adc_or_s == 1'b1) begin
+        up_adc_or_int <= 1'b1;
+      end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
+        up_adc_or_int <= up_adc_or_int & ~up_wdata[0];
+      end
+    end
+  end
+
+  generate
+  if (DCFILTER_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_adc_dcfilt_offset <= 'd0;
+    up_adc_dcfilt_coeff <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_adc_dcfilt_offset <= 'd0;
+      up_adc_dcfilt_coeff <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
+        up_adc_dcfilt_offset <= up_wdata[31:16];
+        up_adc_dcfilt_coeff <= up_wdata[15:0];
+      end
+    end
+  end
+  end
+  endgenerate
+
+  generate
+  if (IQCORRECTION_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_adc_iqcor_coeff_1 <= 'd0;
+    up_adc_iqcor_coeff_2 <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_adc_iqcor_coeff_1 <= 'd0;
+      up_adc_iqcor_coeff_2 <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
+        up_adc_iqcor_coeff_1 <= up_wdata[31:16];
+        up_adc_iqcor_coeff_2 <= up_wdata[15:0];
+      end
+    end
+  end
+  end
+  endgenerate
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_adc_pnseq_sel <= 'd0;
+      up_adc_data_sel <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
+        up_adc_pnseq_sel <= up_wdata[19:16];
+        up_adc_data_sel <= up_wdata[3:0];
+      end
+    end
+  end
+
+  generate
+  if (USERPORTS_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_usr_datatype_be_int <= 'd0;
+    up_usr_datatype_signed_int <= 'd0;
+    up_usr_datatype_shift_int <= 'd0;
+    up_usr_datatype_total_bits_int <= 'd0;
+    up_usr_datatype_bits_int <= 'd0;
+    up_usr_decimation_m_int <= 'd0;
+    up_usr_decimation_n_int <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_usr_datatype_be_int <= 'd0;
+      up_usr_datatype_signed_int <= 'd0;
+      up_usr_datatype_shift_int <= 'd0;
+      up_usr_datatype_total_bits_int <= 'd0;
+      up_usr_datatype_bits_int <= 'd0;
+      up_usr_decimation_m_int <= 'd0;
+      up_usr_decimation_n_int <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
+        up_usr_datatype_be_int <= up_wdata[25];
+        up_usr_datatype_signed_int <= up_wdata[24];
+        up_usr_datatype_shift_int <= up_wdata[23:16];
+        up_usr_datatype_total_bits_int <= up_wdata[15:8];
+        up_usr_datatype_bits_int <= up_wdata[7:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin
+        up_usr_decimation_m_int <= up_wdata[31:16];
+        up_usr_decimation_n_int <= up_wdata[15:0];
+      end
+    end
+  end
+  end
+  endgenerate
+
+  // processor read interface
+
+  assign up_rack = up_rack_int;
+  assign up_rdata = up_rdata_int;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rack_int <= 'd0;
+      up_rdata_int <= 'd0;
+    end else begin
+      up_rack_int <= up_rreq_s;
       if (up_rreq_s == 1'b1) begin
         case (up_raddr[3:0])
-          4'h0: up_rdata <= {20'd0, up_adc_lb_enb, up_adc_pn_sel,
-                              up_adc_iqcor_enb, up_adc_dcfilt_enb,
-                              1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
-                              2'd0, up_adc_pn_type, up_adc_enable};
-          4'h1: up_rdata <= {29'd0, up_adc_pn_err, up_adc_pn_oos, up_adc_or};
-          4'h4: up_rdata <= {up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
-          4'h5: up_rdata <= {up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};
-          4'h6: up_rdata <= {12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel};
-          4'h8: up_rdata <= {6'd0, adc_usr_datatype_be, adc_usr_datatype_signed,
-                              adc_usr_datatype_shift, adc_usr_datatype_total_bits,
-                              adc_usr_datatype_bits};
-          4'h9: up_rdata <= {adc_usr_decimation_m, adc_usr_decimation_n};
-          default: up_rdata <= 0;
+          4'h0: up_rdata_int <= { 20'd0, up_adc_lb_enb, up_adc_pn_sel,
+                                  up_adc_iqcor_enb, up_adc_dcfilt_enb,
+                                  1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
+                                  2'd0, up_adc_pn_type, up_adc_enable};
+          4'h1: up_rdata_int <= { 29'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int};
+          4'h4: up_rdata_int <= { up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
+          4'h5: up_rdata_int <= { up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};
+          4'h6: up_rdata_int <= { 12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel};
+          4'h8: up_rdata_int <= { 6'd0, adc_usr_datatype_be, adc_usr_datatype_signed,
+                                  adc_usr_datatype_shift, adc_usr_datatype_total_bits,
+                                  adc_usr_datatype_bits};
+          4'h9: up_rdata_int <= { adc_usr_decimation_m, adc_usr_decimation_n};
+          default: up_rdata_int <= 0;
         endcase
       end else begin
-        up_rdata <= 32'd0;
+        up_rdata_int <= 32'd0;
       end
     end
   end
diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index d2158813c..8101fa038 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -37,129 +37,80 @@
 
 `timescale 1ns/100ps
 
-module up_adc_common (
-
-  // clock reset
-
-  mmcm_rst,
-
-  // adc interface
-
-  adc_clk,
-  adc_rst,
-  adc_r1_mode,
-  adc_ddr_edgesel,
-  adc_pin_mode,
-  adc_status,
-  adc_sync_status,
-  adc_status_ovf,
-  adc_status_unf,
-  adc_clk_ratio,
-  adc_start_code,
-  adc_sync,
-
-  // channel interface
-
-  up_status_pn_err,
-  up_status_pn_oos,
-  up_status_or,
-
-  // drp interface
-
-  up_drp_sel,
-  up_drp_wr,
-  up_drp_addr,
-  up_drp_wdata,
-  up_drp_rdata,
-  up_drp_ready,
-  up_drp_locked,
-
-  // user channel control
-
-  up_usr_chanmax,
-  adc_usr_chanmax,
-  up_adc_gpio_in,
-  up_adc_gpio_out,
-
-  // bus interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module up_adc_common #(
 
   // parameters
 
-  localparam  PCORE_VERSION = 32'h00090062;
-  parameter   ID = 0;
-  parameter   ADC_COMMON_ID = 6'h00;
+  parameter   ID = 0,
+  parameter   CONFIG = 0,
+  parameter   COMMON_ID = 6'h00,
+  parameter   DRP_DISABLE = 6'h00,
+  parameter   USERPORTS_DISABLE = 0) (
 
   // clock reset
 
-  output          mmcm_rst;
+  output          mmcm_rst,
 
   // adc interface
 
-  input           adc_clk;
-  output          adc_rst;
-  output          adc_r1_mode;
-  output          adc_ddr_edgesel;
-  output          adc_pin_mode;
-  input           adc_status;
-  input           adc_sync_status;
-  input           adc_status_ovf;
-  input           adc_status_unf;
-  input   [31:0]  adc_clk_ratio;
-  output  [31:0]  adc_start_code;
-  output          adc_sync;
+  input           adc_clk,
+  output          adc_rst,
+  output          adc_r1_mode,
+  output          adc_ddr_edgesel,
+  output          adc_pin_mode,
+  input           adc_status,
+  input           adc_sync_status,
+  input           adc_status_ovf,
+  input           adc_status_unf,
+  input   [31:0]  adc_clk_ratio,
+  output  [31:0]  adc_start_code,
+  output          adc_sync,
 
   // channel interface
 
-  input           up_status_pn_err;
-  input           up_status_pn_oos;
-  input           up_status_or;
+  input           up_status_pn_err,
+  input           up_status_pn_oos,
+  input           up_status_or,
 
   // drp interface
 
-  output          up_drp_sel;
-  output          up_drp_wr;
-  output  [11:0]  up_drp_addr;
-  output  [31:0]  up_drp_wdata;
-  input   [31:0]  up_drp_rdata;
-  input           up_drp_ready;
-  input           up_drp_locked;
+  output          up_drp_sel,
+  output          up_drp_wr,
+  output  [11:0]  up_drp_addr,
+  output  [31:0]  up_drp_wdata,
+  input   [31:0]  up_drp_rdata,
+  input           up_drp_ready,
+  input           up_drp_locked,
 
   // user channel control
 
-  output  [ 7:0]  up_usr_chanmax;
-  input   [ 7:0]  adc_usr_chanmax;
-  input   [31:0]  up_adc_gpio_in;
-  output  [31:0]  up_adc_gpio_out;
+  output  [ 7:0]  up_usr_chanmax,
+  input   [ 7:0]  adc_usr_chanmax,
+  input   [31:0]  up_adc_gpio_in,
+  output  [31:0]  up_adc_gpio_out,
 
   // bus interface
 
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
+
+  // parameters
+
+  localparam  VERSION = 32'h000a0062;
 
   // internal registers
 
   reg             up_core_preset = 'd0;
   reg             up_mmcm_preset = 'd0;
-  reg             up_wack = 'd0;
+  reg             up_wack_int = 'd0;
   reg     [31:0]  up_scratch = 'd0;
   reg             up_mmcm_resetn = 'd0;
   reg             up_resetn = 'd0;
@@ -167,20 +118,20 @@ module up_adc_common (
   reg             up_adc_r1_mode = 'd0;
   reg             up_adc_ddr_edgesel = 'd0;
   reg             up_adc_pin_mode = 'd0;
-  reg             up_drp_sel = 'd0;
-  reg             up_drp_wr = 'd0;
+  reg             up_drp_sel_int = 'd0;
+  reg             up_drp_wr_int = 'd0;
   reg             up_drp_status = 'd0;
   reg             up_drp_rwn = 'd0;
-  reg     [11:0]  up_drp_addr = 'd0;
-  reg     [31:0]  up_drp_wdata = 'd0;
+  reg     [11:0]  up_drp_addr_int = 'd0;
+  reg     [31:0]  up_drp_wdata_int = 'd0;
   reg     [31:0]  up_drp_rdata_hold = 'd0;
   reg             up_status_ovf = 'd0;
   reg             up_status_unf = 'd0;
-  reg     [ 7:0]  up_usr_chanmax = 'd0;
+  reg     [ 7:0]  up_usr_chanmax_int = 'd0;
   reg     [31:0]  up_adc_start_code = 'd0;
-  reg     [31:0]  up_adc_gpio_out = 'd0;
-  reg             up_rack = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
+  reg     [31:0]  up_adc_gpio_out_int = 'd0;
+  reg             up_rack_int = 'd0;
+  reg     [31:0]  up_rdata_int = 'd0;
 
   // internal signals
 
@@ -195,16 +146,18 @@ module up_adc_common (
 
   // decode block select
 
-  assign up_wreq_s = (up_waddr[13:8] == ADC_COMMON_ID) ? up_wreq : 1'b0;
-  assign up_rreq_s = (up_raddr[13:8] == ADC_COMMON_ID) ? up_rreq : 1'b0;
+  assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
+  assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
 
   // processor write interface
 
+  assign up_wack = up_wack_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_core_preset <= 1'd1;
       up_mmcm_preset <= 1'd1;
-      up_wack <= 'd0;
+      up_wack_int <= 'd0;
       up_scratch <= 'd0;
       up_mmcm_resetn <= 'd0;
       up_resetn <= 'd0;
@@ -212,22 +165,10 @@ module up_adc_common (
       up_adc_r1_mode <= 'd0;
       up_adc_ddr_edgesel <= 'd0;
       up_adc_pin_mode <= 'd0;
-      up_drp_sel <= 'd0;
-      up_drp_wr <= 'd0;
-      up_drp_status <= 'd0;
-      up_drp_rwn <= 'd0;
-      up_drp_addr <= 'd0;
-      up_drp_wdata <= 'd0;
-      up_drp_rdata_hold <= 'd0;
-      up_status_ovf <= 'd0;
-      up_status_unf <= 'd0;
-      up_usr_chanmax <= 'd0;
-      up_adc_start_code <= 'd0;
-      up_adc_gpio_out <= 'd0;
     end else begin
       up_core_preset <= ~up_resetn;
       up_mmcm_preset <= ~up_mmcm_resetn;
-      up_wack <= up_wreq_s;
+      up_wack_int <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
         up_scratch <= up_wdata;
       end
@@ -247,12 +188,42 @@ module up_adc_common (
         up_adc_ddr_edgesel <= up_wdata[1];
         up_adc_pin_mode <= up_wdata[0];
       end
+    end
+  end
+
+  assign up_drp_sel = up_drp_sel_int;
+  assign up_drp_wr = up_drp_wr_int;
+  assign up_drp_addr = up_drp_addr_int;
+  assign up_drp_wdata = up_drp_wdata_int;
+
+  generate
+  if (DRP_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_drp_sel_int <= 'd0;
+    up_drp_wr_int <= 'd0;
+    up_drp_status <= 'd0;
+    up_drp_rwn <= 'd0;
+    up_drp_addr_int <= 'd0;
+    up_drp_wdata_int <= 'd0;
+    up_drp_rdata_hold <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_drp_sel_int <= 'd0;
+      up_drp_wr_int <= 'd0;
+      up_drp_status <= 'd0;
+      up_drp_rwn <= 'd0;
+      up_drp_addr_int <= 'd0;
+      up_drp_wdata_int <= 'd0;
+      up_drp_rdata_hold <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
-        up_drp_sel <= 1'b1;
-        up_drp_wr <= ~up_wdata[28];
+        up_drp_sel_int <= 1'b1;
+        up_drp_wr_int <= ~up_wdata[28];
       end else begin
-        up_drp_sel <= 1'b0;
-        up_drp_wr <= 1'b0;
+        up_drp_sel_int <= 1'b0;
+        up_drp_wr_int <= 1'b0;
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_status <= 1'b1;
@@ -261,14 +232,24 @@ module up_adc_common (
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_rwn <= up_wdata[28];
-        up_drp_addr <= up_wdata[27:16];
+        up_drp_addr_int <= up_wdata[27:16];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
-        up_drp_wdata <= up_wdata;
+        up_drp_wdata_int <= up_wdata;
       end
       if (up_drp_ready == 1'b1) begin
         up_drp_rdata_hold <= up_drp_rdata;
       end
+    end
+  end
+  end
+  endgenerate
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_status_ovf <= 'd0;
+      up_status_unf <= 'd0;
+    end else begin
       if (up_status_ovf_s == 1'b1) begin
         up_status_ovf <= 1'b1;
       end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
@@ -279,51 +260,82 @@ module up_adc_common (
       end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
         up_status_unf <= up_status_unf & ~up_wdata[1];
       end
+    end
+  end
+
+  assign up_usr_chanmax = up_usr_chanmax_int;
+
+  generate
+  if (USERPORTS_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_usr_chanmax_int <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_usr_chanmax_int <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
-        up_usr_chanmax <= up_wdata[7:0];
+        up_usr_chanmax_int <= up_wdata[7:0];
       end
+    end
+  end
+  end
+  endgenerate
+
+  assign up_adc_gpio_out = up_adc_gpio_out_int;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_adc_start_code <= 'd0;
+      up_adc_gpio_out_int <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
         up_adc_start_code <= up_wdata[31:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
-        up_adc_gpio_out <= up_wdata;
+        up_adc_gpio_out_int <= up_wdata;
       end
     end
   end
 
   // processor read interface
 
+  assign up_rack = up_rack_int;
+  assign up_rdata = up_rdata_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
+      up_rack_int <= 'd0;
+      up_rdata_int <= 'd0;
     end else begin
-      up_rack <= up_rreq_s;
+      up_rack_int <= up_rreq_s;
       if (up_rreq_s == 1'b1) begin
         case (up_raddr[7:0])
-          8'h00: up_rdata <= PCORE_VERSION;
-          8'h01: up_rdata <= ID;
-          8'h02: up_rdata <= up_scratch;
-          8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
-          8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
-          8'h15: up_rdata <= up_adc_clk_count_s;
-          8'h16: up_rdata <= adc_clk_ratio;
-          8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
-          8'h1a: up_rdata <= {31'd0, up_sync_status_s};
-          8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, 16'b0};
-          8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, 16'b0};
-          8'h1e: up_rdata <= up_drp_wdata;
-          8'h1f: up_rdata <= up_drp_rdata_hold;
-          8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
-          8'h23: up_rdata <= 32'd8;
-          8'h28: up_rdata <= {24'd0, adc_usr_chanmax};
-          8'h29: up_rdata <= up_adc_start_code;
-          8'h2e: up_rdata <= up_adc_gpio_in;
-          8'h2f: up_rdata <= up_adc_gpio_out;
-          default: up_rdata <= 0;
+          8'h00: up_rdata_int <= VERSION;
+          8'h01: up_rdata_int <= ID;
+          8'h02: up_rdata_int <= up_scratch;
+          8'h03: up_rdata_int <= CONFIG;
+          8'h10: up_rdata_int <= {30'd0, up_mmcm_resetn, up_resetn};
+          8'h11: up_rdata_int <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
+          8'h15: up_rdata_int <= up_adc_clk_count_s;
+          8'h16: up_rdata_int <= adc_clk_ratio;
+          8'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
+          8'h1a: up_rdata_int <= {31'd0, up_sync_status_s};
+          8'h1c: up_rdata_int <= {3'd0, up_drp_rwn, up_drp_addr_int, 16'b0};
+          8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status, 16'b0};
+          8'h1e: up_rdata_int <= up_drp_wdata_int;
+          8'h1f: up_rdata_int <= up_drp_rdata_hold;
+          8'h22: up_rdata_int <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
+          8'h23: up_rdata_int <= 32'd8;
+          8'h28: up_rdata_int <= {24'd0, adc_usr_chanmax};
+          8'h29: up_rdata_int <= up_adc_start_code;
+          8'h2e: up_rdata_int <= up_adc_gpio_in;
+          8'h2f: up_rdata_int <= up_adc_gpio_out_int;
+          default: up_rdata_int <= 0;
         endcase
       end else begin
-        up_rdata <= 32'd0;
+        up_rdata_int <= 32'd0;
       end
     end
   end

From 7be6168b2e2b3a2d6c51752d19b9acbc745ac054 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 23 Sep 2016 13:42:14 -0400
Subject: [PATCH 521/972] ad9361- adc data path split

---
 library/axi_ad9361/axi_ad9361.v            |   7 +-
 library/axi_ad9361/axi_ad9361_rx.v         | 248 +++++++++------------
 library/axi_ad9361/axi_ad9361_rx_channel.v | 167 +++++++-------
 3 files changed, 193 insertions(+), 229 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 9fe9e6547..531f85e4d 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -602,8 +602,11 @@ module axi_ad9361 (
 
   axi_ad9361_rx #(
     .ID (ID),
-    .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE),
-    .R1_MODE_EN (R1_MODE_EN))
+    .MODE_1R1T (R1_MODE_EN),
+    .USERPORTS_DISABLE (ADC_DATAPATH_DISABLE),
+    .DATAFORMAT_DISABLE (ADC_DATAPATH_DISABLE),
+    .DCFILTER_DISABLE (ADC_DATAPATH_DISABLE),
+    .IQCORRECTION_DISABLE (ADC_DATAPATH_DISABLE))
   i_rx (
     .mmcm_rst (mmcm_rst),
     .adc_rst (rst),
diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v
index 4c4a60ab7..133850bea 100644
--- a/library/axi_ad9361/axi_ad9361_rx.v
+++ b/library/axi_ad9361/axi_ad9361_rx.v
@@ -38,140 +38,92 @@
 
 `timescale 1ns/100ps
 
-module axi_ad9361_rx (
-
-  // common
-
-  mmcm_rst,
-
-  // adc interface
-
-  adc_rst,
-  adc_clk,
-  adc_valid,
-  adc_data,
-  adc_status,
-  adc_r1_mode,
-  adc_ddr_edgesel,
-  dac_data,
-
-  // delay interface
-
-  up_dld,
-  up_dwdata,
-  up_drdata,
-  delay_clk,
-  delay_rst,
-  delay_locked,
-
-  // dma interface
-
-  adc_enable_i0,
-  adc_valid_i0,
-  adc_data_i0,
-  adc_enable_q0,
-  adc_valid_q0,
-  adc_data_q0,
-  adc_enable_i1,
-  adc_valid_i1,
-  adc_data_i1,
-  adc_enable_q1,
-  adc_valid_q1,
-  adc_data_q1,
-  adc_dovf,
-  adc_dunf,
-
-  // gpio
-
-  up_adc_gpio_in,
-  up_adc_gpio_out,
-
-  // processor interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module axi_ad9361_rx #(
 
   // parameters
 
-  parameter   DATAPATH_DISABLE = 0;
-  parameter   ID = 0;
-  parameter   R1_MODE_EN = 0;
+  parameter   ID = 0,
+  parameter   MODE_1R1T = 0,
+  parameter   USERPORTS_DISABLE = 0,
+  parameter   DATAFORMAT_DISABLE = 0,
+  parameter   DCFILTER_DISABLE = 0,
+  parameter   IQCORRECTION_DISABLE = 0) (
 
   // common
 
-  output          mmcm_rst;
+  output          mmcm_rst,
 
   // adc interface
 
-  output          adc_rst;
-  input           adc_clk;
-  input           adc_valid;
-  input   [47:0]  adc_data;
-  input           adc_status;
-  output          adc_r1_mode;
-  output          adc_ddr_edgesel;
-  input   [47:0]  dac_data;
+  output          adc_rst,
+  input           adc_clk,
+  input           adc_valid,
+  input   [47:0]  adc_data,
+  input           adc_status,
+  output          adc_r1_mode,
+  output          adc_ddr_edgesel,
+  input   [47:0]  dac_data,
 
   // delay interface
 
-  output  [12:0]  up_dld;
-  output  [64:0]  up_dwdata;
-  input   [64:0]  up_drdata;
-  input           delay_clk;
-  output          delay_rst;
-  input           delay_locked;
+  output  [12:0]  up_dld,
+  output  [64:0]  up_dwdata,
+  input   [64:0]  up_drdata,
+  input           delay_clk,
+  output          delay_rst,
+  input           delay_locked,
 
   // dma interface
 
-  output          adc_enable_i0;
-  output          adc_valid_i0;
-  output  [15:0]  adc_data_i0;
-  output          adc_enable_q0;
-  output          adc_valid_q0;
-  output  [15:0]  adc_data_q0;
-  output          adc_enable_i1;
-  output          adc_valid_i1;
-  output  [15:0]  adc_data_i1;
-  output          adc_enable_q1;
-  output          adc_valid_q1;
-  output  [15:0]  adc_data_q1;
-  input           adc_dovf;
-  input           adc_dunf;
+  output          adc_enable_i0,
+  output          adc_valid_i0,
+  output  [15:0]  adc_data_i0,
+  output          adc_enable_q0,
+  output          adc_valid_q0,
+  output  [15:0]  adc_data_q0,
+  output          adc_enable_i1,
+  output          adc_valid_i1,
+  output  [15:0]  adc_data_i1,
+  output          adc_enable_q1,
+  output          adc_valid_q1,
+  output  [15:0]  adc_data_q1,
+  input           adc_dovf,
+  input           adc_dunf,
 
   // gpio
 
-  input   [31:0]  up_adc_gpio_in;
-  output  [31:0]  up_adc_gpio_out;
+  input   [31:0]  up_adc_gpio_in,
+  output  [31:0]  up_adc_gpio_out,
 
   // processor interface
 
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
+
+  // configuration settings
+
+  localparam  CONFIG =  (MODE_1R1T * 16) +
+                        (USERPORTS_DISABLE * 8) +
+                        (DATAFORMAT_DISABLE * 4) +
+                        (DCFILTER_DISABLE * 2) +
+                        (IQCORRECTION_DISABLE * 1);
 
   // internal registers
 
   reg             up_status_pn_err = 'd0;
   reg             up_status_pn_oos = 'd0;
   reg             up_status_or = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
-  reg             up_rack = 'd0;
-  reg             up_wack = 'd0;
+  reg     [31:0]  up_rdata_int = 'd0;
+  reg             up_rack_int = 'd0;
+  reg             up_wack_int = 'd0;
 
   // internal signals
 
@@ -183,38 +135,44 @@ module axi_ad9361_rx (
   wire    [ 3:0]  up_adc_pn_oos_s;
   wire    [ 3:0]  up_adc_or_s;
   wire    [31:0]  up_rdata_s[0:5];
-  wire            up_rack_s[0:5];
-  wire            up_wack_s[0:5];
+  wire    [ 5:0]  up_rack_s;
+  wire    [ 5:0]  up_wack_s;
 
   // processor read interface
 
+  assign up_wack = up_wack_int;
+  assign up_rack = up_rack_int;
+  assign up_rdata = up_rdata_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_status_pn_err <= 'd0;
       up_status_pn_oos <= 'd0;
       up_status_or <= 'd0;
-      up_rdata <= 'd0;
-      up_rack <= 'd0;
-      up_wack <= 'd0;
+      up_rdata_int <= 'd0;
+      up_rack_int <= 'd0;
+      up_wack_int <= 'd0;
     end else begin
       up_status_pn_err <= | up_adc_pn_err_s;
       up_status_pn_oos <= | up_adc_pn_oos_s;
       up_status_or <= | up_adc_or_s;
-      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
-                  up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
-      up_rack <=  up_rack_s[0]  | up_rack_s[1]  | up_rack_s[2]  |
-                  up_rack_s[3]  | up_rack_s[4]  | up_rack_s[5];
-      up_wack <=  up_wack_s[0]  | up_wack_s[1]  | up_wack_s[2]  |
-                  up_wack_s[3]  | up_wack_s[4]  | up_wack_s[5];
+      up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
+        up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
+      up_rack_int <=  | up_rack_s;
+      up_wack_int <=  | up_wack_s;
     end
   end
 
   // channel 0 (i)
 
   axi_ad9361_rx_channel #(
-    .Q_OR_I_N(0),
-    .CHANNEL_ID(0),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    .Q_OR_I_N (0),
+    .CHANNEL_ID (0),
+    .DISABLE (0),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+    .DCFILTER_DISABLE (DCFILTER_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
   i_rx_channel_0 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -245,9 +203,13 @@ module axi_ad9361_rx (
   // channel 1 (q)
 
   axi_ad9361_rx_channel #(
-    .Q_OR_I_N(1),
-    .CHANNEL_ID(1),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    .Q_OR_I_N (1),
+    .CHANNEL_ID (1),
+    .DISABLE (0),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+    .DCFILTER_DISABLE (DCFILTER_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
   i_rx_channel_1 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -275,15 +237,16 @@ module axi_ad9361_rx (
     .up_rdata (up_rdata_s[1]),
     .up_rack (up_rack_s[1]));
 
-  generate
-  if (R1_MODE_EN == 0) begin
-
   // channel 2 (i)
 
   axi_ad9361_rx_channel #(
-    .Q_OR_I_N(0),
-    .CHANNEL_ID(2),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    .Q_OR_I_N (0),
+    .CHANNEL_ID (2),
+    .DISABLE (MODE_1R1T),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+    .DCFILTER_DISABLE (DCFILTER_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
   i_rx_channel_2 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -314,9 +277,13 @@ module axi_ad9361_rx (
   // channel 3 (q)
 
   axi_ad9361_rx_channel #(
-    .Q_OR_I_N(1),
-    .CHANNEL_ID(3),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    .Q_OR_I_N (1),
+    .CHANNEL_ID (3),
+    .DISABLE (MODE_1R1T),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+    .DCFILTER_DISABLE (DCFILTER_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
   i_rx_channel_3 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -344,12 +311,14 @@ module axi_ad9361_rx (
     .up_rdata (up_rdata_s[3]),
     .up_rack (up_rack_s[3]));
 
-  end
-  endgenerate
-
   // common processor control
 
-  up_adc_common #(.ID (ID)) i_up_adc_common (
+  up_adc_common #(
+    .ID (ID),
+    .CONFIG (CONFIG),
+    .DRP_DISABLE (1),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE))
+  i_up_adc_common (
     .mmcm_rst (mmcm_rst),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -390,7 +359,10 @@ module axi_ad9361_rx (
 
   // adc delay control
 
-  up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
+  up_delay_cntrl #(
+    .DATA_WIDTH (13),
+    .BASE_ADDRESS (6'h02))
+  i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked),
diff --git a/library/axi_ad9361/axi_ad9361_rx_channel.v b/library/axi_ad9361/axi_ad9361_rx_channel.v
index ecffad89a..1f63e1617 100644
--- a/library/axi_ad9361/axi_ad9361_rx_channel.v
+++ b/library/axi_ad9361/axi_ad9361_rx_channel.v
@@ -37,81 +37,51 @@
 
 `timescale 1ns/100ps
 
-module axi_ad9361_rx_channel (
-
-  // adc interface
-
-  adc_clk,
-  adc_rst,
-  adc_valid,
-  adc_data,
-  adc_data_q,
-  adc_or,
-  dac_data,
-
-  // channel interface
-
-  adc_dcfilter_data_out,
-  adc_dcfilter_data_in,
-  adc_iqcor_valid,
-  adc_iqcor_data,
-  adc_enable,
-  up_adc_pn_err,
-  up_adc_pn_oos,
-  up_adc_or,
-
-  // processor interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module axi_ad9361_rx_channel #(
 
   // parameters
 
-  parameter Q_OR_I_N = 0;
-  parameter CHANNEL_ID = 0;
-  parameter DATAPATH_DISABLE = 0;
+  parameter   Q_OR_I_N = 0,
+  parameter   CHANNEL_ID = 0,
+  parameter   DISABLE = 0,
+  parameter   USERPORTS_DISABLE = 0,
+  parameter   DATAFORMAT_DISABLE = 0,
+  parameter   DCFILTER_DISABLE = 0,
+  parameter   IQCORRECTION_DISABLE = 0) (
 
   // adc interface
 
-  input           adc_clk;
-  input           adc_rst;
-  input           adc_valid;
-  input   [11:0]  adc_data;
-  input   [11:0]  adc_data_q;
-  input           adc_or;
-  input   [11:0]  dac_data;
+  input           adc_clk,
+  input           adc_rst,
+  input           adc_valid,
+  input   [11:0]  adc_data,
+  input   [11:0]  adc_data_q,
+  input           adc_or,
+  input   [11:0]  dac_data,
 
   // channel interface
 
-  output  [15:0]  adc_dcfilter_data_out;
-  input   [15:0]  adc_dcfilter_data_in;
-  output          adc_iqcor_valid;
-  output  [15:0]  adc_iqcor_data;
-  output          adc_enable;
-  output          up_adc_pn_err;
-  output          up_adc_pn_oos;
-  output          up_adc_or;
+  output  [15:0]  adc_dcfilter_data_out,
+  input   [15:0]  adc_dcfilter_data_in,
+  output          adc_iqcor_valid,
+  output  [15:0]  adc_iqcor_data,
+  output          adc_enable,
+  output          up_adc_pn_err,
+  output          up_adc_pn_oos,
+  output          up_adc_or,
 
   // processor interface
 
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
 
   // internal signals
 
@@ -134,12 +104,35 @@ module axi_ad9361_rx_channel (
   wire            adc_pn_err_s;
   wire            adc_pn_oos_s;
 
+  // data-path disable
+
+  generate
+  if (DISABLE == 1) begin
+  assign adc_dcfilter_data_out = 16'd0;
+  assign adc_iqcor_valid = 1'd0;
+  assign adc_iqcor_data = 16'd0;
+  assign adc_enable = 1'd0;
+  assign up_adc_pn_err = 1'd0;
+  assign up_adc_pn_oos = 1'd0;
+  assign up_adc_or = 1'd0;
+  assign up_wack = 1'd0;
+  assign up_rdata = 32'd0;
+  assign up_rack = 1'd0;
+  end
+  endgenerate
+
+  generate
+  if (DISABLE == 0) begin
+
   // iq correction inputs
 
   assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data;
   assign adc_dcfilter_data_out = adc_dcfilter_data_s;
 
-  axi_ad9361_rx_pnmon #(.Q_OR_I_N (Q_OR_I_N), .PRBS_SEL (CHANNEL_ID)) i_rx_pnmon (
+  axi_ad9361_rx_pnmon #(
+    .Q_OR_I_N (Q_OR_I_N),
+    .PRBS_SEL (CHANNEL_ID))
+  i_rx_pnmon (
     .adc_clk (adc_clk),
     .adc_valid (adc_valid),
     .adc_data_i (adc_data),
@@ -148,12 +141,10 @@ module axi_ad9361_rx_channel (
     .adc_pn_oos (adc_pn_oos_s),
     .adc_pn_err (adc_pn_err_s));
 
-  generate
-  if (DATAPATH_DISABLE == 1) begin
-  assign adc_dfmt_valid_s = adc_valid;
-  assign adc_dfmt_data_s = {4'd0, adc_data_s};
-  end else begin
-  ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt (
+  ad_datafmt #(
+    .DATA_WIDTH (12),
+    .DISABLE (DATAFORMAT_DISABLE))
+  i_ad_datafmt (
     .clk (adc_clk),
     .valid (adc_valid),
     .data (adc_data_s),
@@ -162,15 +153,10 @@ module axi_ad9361_rx_channel (
     .dfmt_enable (adc_dfmt_enable_s),
     .dfmt_type (adc_dfmt_type_s),
     .dfmt_se (adc_dfmt_se_s));
-  end
-  endgenerate
 
-  generate
-  if (DATAPATH_DISABLE == 1) begin
-  assign adc_dcfilter_valid_s = adc_dfmt_valid_s;
-  assign adc_dcfilter_data_s = adc_dfmt_data_s;
-  end else begin
-  ad_dcfilter i_ad_dcfilter (
+  ad_dcfilter #(
+    .DISABLE (DCFILTER_DISABLE))
+  i_ad_dcfilter (
     .clk (adc_clk),
     .valid (adc_dfmt_valid_s),
     .data (adc_dfmt_data_s),
@@ -179,15 +165,11 @@ module axi_ad9361_rx_channel (
     .dcfilt_enb (adc_dcfilt_enb_s),
     .dcfilt_coeff (adc_dcfilt_coeff_s),
     .dcfilt_offset (adc_dcfilt_offset_s));
-  end
-  endgenerate
 
-  generate
-  if (DATAPATH_DISABLE == 1) begin
-  assign adc_iqcor_valid = adc_dcfilter_valid_s;
-  assign adc_iqcor_data = adc_dcfilter_data_s;
-  end else begin
-  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
+  ad_iqcor #(
+    .Q_OR_I_N (Q_OR_I_N),
+    .DISABLE (IQCORRECTION_DISABLE))
+  i_ad_iqcor (
     .clk (adc_clk),
     .valid (adc_dcfilter_valid_s),
     .data_in (adc_dcfilter_data_s),
@@ -197,10 +179,14 @@ module axi_ad9361_rx_channel (
     .iqcor_enable (adc_iqcor_enb_s),
     .iqcor_coeff_1 (adc_iqcor_coeff_1_s),
     .iqcor_coeff_2 (adc_iqcor_coeff_2_s));
-  end
-  endgenerate
 
-  up_adc_channel #(.ADC_CHANNEL_ID (CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(
+    .CHANNEL_ID (CHANNEL_ID),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+    .DCFILTER_DISABLE (DCFILTER_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
+  i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -246,6 +232,9 @@ module axi_ad9361_rx_channel (
     .up_rdata (up_rdata),
     .up_rack (up_rack));
 
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************

From 68371431103b3d885393b1c554669e4dd7bd592e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 23 Sep 2016 13:44:47 -0400
Subject: [PATCH 522/972] library/ adc parameter changes

---
 library/axi_ad6676/axi_ad6676_channel.v                 | 2 +-
 library/axi_ad9234/axi_ad9234_channel.v                 | 2 +-
 library/axi_ad9250/axi_ad9250_channel.v                 | 2 +-
 library/axi_ad9265/axi_ad9265_channel.v                 | 2 +-
 library/axi_ad9371/axi_ad9371_rx.v                      | 2 +-
 library/axi_ad9371/axi_ad9371_rx_channel.v              | 4 ++--
 library/axi_ad9371/axi_ad9371_rx_os.v                   | 2 +-
 library/axi_ad9434/axi_ad9434_core.v                    | 2 +-
 library/axi_ad9467/axi_ad9467_channel.v                 | 2 +-
 library/axi_ad9625/axi_ad9625_channel.v                 | 2 +-
 library/axi_ad9643/axi_ad9643_channel.v                 | 2 +-
 library/axi_ad9652/axi_ad9652_channel.v                 | 2 +-
 library/axi_ad9671/axi_ad9671_channel.v                 | 2 +-
 library/axi_ad9680/axi_ad9680_channel.v                 | 2 +-
 library/axi_ad9684/axi_ad9684_channel.v                 | 2 +-
 library/axi_generic_adc/axi_generic_adc.v               | 2 +-
 library/axi_mc_current_monitor/axi_mc_current_monitor.v | 6 +++---
 17 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/library/axi_ad6676/axi_ad6676_channel.v b/library/axi_ad6676/axi_ad6676_channel.v
index 69b4c273c..63299c6ff 100755
--- a/library/axi_ad6676/axi_ad6676_channel.v
+++ b/library/axi_ad6676/axi_ad6676_channel.v
@@ -120,7 +120,7 @@ module axi_ad6676_channel (
 
   assign adc_dfmt_data = adc_data;
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v
index 0c3878127..6bb5c98dd 100644
--- a/library/axi_ad9234/axi_ad9234_channel.v
+++ b/library/axi_ad9234/axi_ad9234_channel.v
@@ -120,7 +120,7 @@ module axi_ad9234_channel (
 
   assign adc_dfmt_data = adc_data;
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9250/axi_ad9250_channel.v b/library/axi_ad9250/axi_ad9250_channel.v
index c5e6b2e6b..41c766ad9 100644
--- a/library/axi_ad9250/axi_ad9250_channel.v
+++ b/library/axi_ad9250/axi_ad9250_channel.v
@@ -136,7 +136,7 @@ module axi_ad9250_channel (
   end
   endgenerate
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9265/axi_ad9265_channel.v b/library/axi_ad9265/axi_ad9265_channel.v
index 7c4504b0f..cb5e76bca 100644
--- a/library/axi_ad9265/axi_ad9265_channel.v
+++ b/library/axi_ad9265/axi_ad9265_channel.v
@@ -159,7 +159,7 @@ module axi_ad9265_channel (
   end
   endgenerate
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9371/axi_ad9371_rx.v b/library/axi_ad9371/axi_ad9371_rx.v
index a0f5e6b12..6d37e9577 100644
--- a/library/axi_ad9371/axi_ad9371_rx.v
+++ b/library/axi_ad9371/axi_ad9371_rx.v
@@ -296,7 +296,7 @@ module axi_ad9371_rx (
   // common processor control
 
   up_adc_common #(
-    .ADC_COMMON_ID ('h00),
+    .COMMON_ID ('h00),
     .ID (ID))
   i_up_adc_common (
     .mmcm_rst (),
diff --git a/library/axi_ad9371/axi_ad9371_rx_channel.v b/library/axi_ad9371/axi_ad9371_rx_channel.v
index 9c47e188b..040a6180c 100644
--- a/library/axi_ad9371/axi_ad9371_rx_channel.v
+++ b/library/axi_ad9371/axi_ad9371_rx_channel.v
@@ -201,8 +201,8 @@ module axi_ad9371_rx_channel (
   endgenerate
 
   up_adc_channel #(
-    .ADC_COMMON_ID (COMMON_ID),
-    .ADC_CHANNEL_ID (CHANNEL_ID))
+    .COMMON_ID (COMMON_ID),
+    .CHANNEL_ID (CHANNEL_ID))
   i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
diff --git a/library/axi_ad9371/axi_ad9371_rx_os.v b/library/axi_ad9371/axi_ad9371_rx_os.v
index 8bbb1afc9..81304a5c5 100644
--- a/library/axi_ad9371/axi_ad9371_rx_os.v
+++ b/library/axi_ad9371/axi_ad9371_rx_os.v
@@ -213,7 +213,7 @@ module axi_ad9371_rx_os (
   // common processor control
 
   up_adc_common #(
-    .ADC_COMMON_ID ('h20),
+    .COMMON_ID ('h20),
     .ID (ID))
   i_up_adc_common (
     .mmcm_rst (),
diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v
index e0f614b40..84d6c2203 100644
--- a/library/axi_ad9434/axi_ad9434_core.v
+++ b/library/axi_ad9434/axi_ad9434_core.v
@@ -246,7 +246,7 @@ module axi_ad9434_core (
     .up_rack (up_rack_s[0]));
 
   up_adc_channel #(
-    .ADC_CHANNEL_ID(0))
+    .CHANNEL_ID(0))
   i_adc_channel(
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
diff --git a/library/axi_ad9467/axi_ad9467_channel.v b/library/axi_ad9467/axi_ad9467_channel.v
index 75eb42672..4ecb883f0 100644
--- a/library/axi_ad9467/axi_ad9467_channel.v
+++ b/library/axi_ad9467/axi_ad9467_channel.v
@@ -127,7 +127,7 @@ module axi_ad9467_channel(
     .dfmt_type(adc_dfmt_type_s),
     .dfmt_se(adc_dfmt_se_s));
 
-  up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(0)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9625/axi_ad9625_channel.v b/library/axi_ad9625/axi_ad9625_channel.v
index 1b9c38960..e2f8460fc 100644
--- a/library/axi_ad9625/axi_ad9625_channel.v
+++ b/library/axi_ad9625/axi_ad9625_channel.v
@@ -131,7 +131,7 @@ module axi_ad9625_channel (
   end
   endgenerate
 
-  up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(0)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9643/axi_ad9643_channel.v b/library/axi_ad9643/axi_ad9643_channel.v
index 093e05da1..78072d2ad 100644
--- a/library/axi_ad9643/axi_ad9643_channel.v
+++ b/library/axi_ad9643/axi_ad9643_channel.v
@@ -183,7 +183,7 @@ module axi_ad9643_channel (
   end
   endgenerate
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9652/axi_ad9652_channel.v b/library/axi_ad9652/axi_ad9652_channel.v
index 1c3f5adb5..63747b9de 100644
--- a/library/axi_ad9652/axi_ad9652_channel.v
+++ b/library/axi_ad9652/axi_ad9652_channel.v
@@ -165,7 +165,7 @@ module axi_ad9652_channel (
   end
   endgenerate
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9671/axi_ad9671_channel.v b/library/axi_ad9671/axi_ad9671_channel.v
index 939fe8cdf..68bd4778f 100644
--- a/library/axi_ad9671/axi_ad9671_channel.v
+++ b/library/axi_ad9671/axi_ad9671_channel.v
@@ -135,7 +135,7 @@ module axi_ad9671_channel (
     .dfmt_type (adc_dfmt_type_s),
     .dfmt_se (adc_dfmt_se_s));
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9680/axi_ad9680_channel.v b/library/axi_ad9680/axi_ad9680_channel.v
index de0b8094a..56b2dbe18 100644
--- a/library/axi_ad9680/axi_ad9680_channel.v
+++ b/library/axi_ad9680/axi_ad9680_channel.v
@@ -135,7 +135,7 @@ module axi_ad9680_channel (
   end
   endgenerate
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9684/axi_ad9684_channel.v b/library/axi_ad9684/axi_ad9684_channel.v
index fe0de9d22..04b99873c 100644
--- a/library/axi_ad9684/axi_ad9684_channel.v
+++ b/library/axi_ad9684/axi_ad9684_channel.v
@@ -141,7 +141,7 @@ module axi_ad9684_channel (
 
   assign adc_valid = adc_dfmt_valid_s[0] | adc_dfmt_valid_s[1];
 
-  up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v
index b7c899abe..32d4cc389 100644
--- a/library/axi_generic_adc/axi_generic_adc.v
+++ b/library/axi_generic_adc/axi_generic_adc.v
@@ -154,7 +154,7 @@ generate
 genvar i;
 
 for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin
-	up_adc_channel #(.ADC_CHANNEL_ID(i)) i_up_adc_channel (
+	up_adc_channel #(.CHANNEL_ID(i)) i_up_adc_channel (
 		.adc_clk (adc_clk),
 		.adc_rst (adc_rst),
 		.adc_enable (adc_enable[i]),
diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor.v b/library/axi_mc_current_monitor/axi_mc_current_monitor.v
index bc735f0d5..fff50d92e 100644
--- a/library/axi_mc_current_monitor/axi_mc_current_monitor.v
+++ b/library/axi_mc_current_monitor/axi_mc_current_monitor.v
@@ -196,7 +196,7 @@ ad7401 vbus_if(
     .data_rd_ready_o(),
     .adc_mdata_i(adc_vbus_dat_i));
 
-up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel_ia(
+up_adc_channel #(.CHANNEL_ID(0)) i_up_adc_channel_ia(
     .adc_clk(adc_clk_o),
     .adc_rst(adc_rst),
     .adc_enable(adc_enable_ia),
@@ -242,7 +242,7 @@ up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel_ia(
     .up_rdata (up_rdata_0_s),
     .up_rack (up_rack_0_s));
 
-up_adc_channel #(.ADC_CHANNEL_ID(1)) i_up_adc_channel_ib(
+up_adc_channel #(.CHANNEL_ID(1)) i_up_adc_channel_ib(
     .adc_clk(adc_clk_o),
     .adc_rst(adc_rst),
     .adc_enable(adc_enable_ib),
@@ -288,7 +288,7 @@ up_adc_channel #(.ADC_CHANNEL_ID(1)) i_up_adc_channel_ib(
     .up_rdata (up_rdata_1_s),
     .up_rack (up_rack_1_s));
 
-up_adc_channel #(.ADC_CHANNEL_ID(2)) i_up_adc_channel_vbus(
+up_adc_channel #(.CHANNEL_ID(2)) i_up_adc_channel_vbus(
     .adc_clk(adc_clk_o),
     .adc_rst(adc_rst),
     .adc_enable(adc_enable_vbus),

From 6735333aea14927df6211c3436c6bf5fc2bbf223 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 23 Sep 2016 16:13:24 -0400
Subject: [PATCH 523/972] common- dac data path split

---
 library/common/ad_dds.v         |  54 +++--
 library/common/up_dac_channel.v | 346 +++++++++++++++++++-------------
 library/common/up_dac_common.v  | 323 +++++++++++++++--------------
 library/common/up_delay_cntrl.v | 112 +++++------
 4 files changed, 446 insertions(+), 389 deletions(-)

diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v
index 3a09e6ec7..5a91a1143 100644
--- a/library/common/ad_dds.v
+++ b/library/common/ad_dds.v
@@ -34,63 +34,59 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
-module ad_dds (
+module ad_dds #(
+
+  // data path disable
+
+  parameter   DISABLE = 0) (
 
   // interface
 
-  clk,
-  dds_format,
-  dds_phase_0,
-  dds_scale_0,
-  dds_phase_1,
-  dds_scale_1,
-  dds_data);
-
-  // interface
-
-  input           clk;
-  input           dds_format;
-  input   [15:0]  dds_phase_0;
-  input   [15:0]  dds_scale_0;
-  input   [15:0]  dds_phase_1;
-  input   [15:0]  dds_scale_1;
-  output  [15:0]  dds_data;
+  input           clk,
+  input           dds_format,
+  input   [15:0]  dds_phase_0,
+  input   [15:0]  dds_scale_0,
+  input   [15:0]  dds_phase_1,
+  input   [15:0]  dds_scale_1,
+  output  [15:0]  dds_data);
 
   // internal registers
 
   reg     [15:0]  dds_data_int = 'd0;
-  reg     [15:0]  dds_data = 'd0;
+  reg     [15:0]  dds_data_out = 'd0;
+  reg     [15:0]  dds_scale_0_d = 'd0;
+  reg     [15:0]  dds_scale_1_d = 'd0;
 
-  reg     [15:0]  dds_scale_0_r = 'd0;
-  reg     [15:0]  dds_scale_1_r = 'd0;
   // internal signals
 
   wire    [15:0]  dds_data_0_s;
   wire    [15:0]  dds_data_1_s;
 
+  // disable
+
+  assign dds_data = (DISABLE == 1) ? 16'd0 : dds_data_out;
+
   // dds channel output
 
   always @(posedge clk) begin
     dds_data_int <= dds_data_0_s + dds_data_1_s;
-    dds_data[15:15] <= dds_data_int[15] ^ dds_format;
-    dds_data[14: 0] <= dds_data_int[14:0];
+    dds_data_out[15:15] <= dds_data_int[15] ^ dds_format;
+    dds_data_out[14: 0] <= dds_data_int[14:0];
   end
 
   always @(posedge clk) begin
-    dds_scale_0_r <= dds_scale_0;
-    dds_scale_1_r <= dds_scale_1;
+    dds_scale_0_d <= dds_scale_0;
+    dds_scale_1_d <= dds_scale_1;
   end
   // dds-1
 
   ad_dds_1 i_dds_1_0 (
     .clk (clk),
     .angle (dds_phase_0),
-    .scale (dds_scale_0_r),
+    .scale (dds_scale_0_d),
     .dds_data (dds_data_0_s));
 
   // dds-2
@@ -98,7 +94,7 @@ module ad_dds (
   ad_dds_1 i_dds_1_1 (
     .clk (clk),
     .angle (dds_phase_1),
-    .scale (dds_scale_1_r),
+    .scale (dds_scale_1_d),
     .dds_data (dds_data_1_s));
 
 endmodule
diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v
index 7cb96f3e7..700458f4e 100644
--- a/library/common/up_dac_channel.v
+++ b/library/common/up_dac_channel.v
@@ -37,112 +37,67 @@
 
 `timescale 1ns/100ps
 
-module up_dac_channel (
-
-  // dac interface
-
-  dac_clk,
-  dac_rst,
-  dac_dds_scale_1,
-  dac_dds_init_1,
-  dac_dds_incr_1,
-  dac_dds_scale_2,
-  dac_dds_init_2,
-  dac_dds_incr_2,
-  dac_pat_data_1,
-  dac_pat_data_2,
-  dac_data_sel,
-  dac_iq_mode,
-  dac_iqcor_enb,
-  dac_iqcor_coeff_1,
-  dac_iqcor_coeff_2,
-
-  // user controls
-
-  up_usr_datatype_be,
-  up_usr_datatype_signed,
-  up_usr_datatype_shift,
-  up_usr_datatype_total_bits,
-  up_usr_datatype_bits,
-  up_usr_interpolation_m,
-  up_usr_interpolation_n,
-  dac_usr_datatype_be,
-  dac_usr_datatype_signed,
-  dac_usr_datatype_shift,
-  dac_usr_datatype_total_bits,
-  dac_usr_datatype_bits,
-  dac_usr_interpolation_m,
-  dac_usr_interpolation_n,
-
-  // bus interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module up_dac_channel #(
 
   // parameters
 
-  parameter DAC_COMMON_ID = 6'h11;
-  parameter DAC_CHANNEL_ID = 4'h0;
+  parameter   COMMON_ID = 6'h11,
+  parameter   CHANNEL_ID = 4'h0,
+  parameter   DDS_DISABLE = 0,
+  parameter   USERPORTS_DISABLE = 0,
+  parameter   IQCORRECTION_DISABLE = 0) (
 
   // dac interface
 
-  input           dac_clk;
-  input           dac_rst;
-  output  [15:0]  dac_dds_scale_1;
-  output  [15:0]  dac_dds_init_1;
-  output  [15:0]  dac_dds_incr_1;
-  output  [15:0]  dac_dds_scale_2;
-  output  [15:0]  dac_dds_init_2;
-  output  [15:0]  dac_dds_incr_2;
-  output  [15:0]  dac_pat_data_1;
-  output  [15:0]  dac_pat_data_2;
-  output  [ 3:0]  dac_data_sel;
-  output          dac_iq_mode;
-  output          dac_iqcor_enb;
-  output  [15:0]  dac_iqcor_coeff_1;
-  output  [15:0]  dac_iqcor_coeff_2;
+  input           dac_clk,
+  input           dac_rst,
+  output  [15:0]  dac_dds_scale_1,
+  output  [15:0]  dac_dds_init_1,
+  output  [15:0]  dac_dds_incr_1,
+  output  [15:0]  dac_dds_scale_2,
+  output  [15:0]  dac_dds_init_2,
+  output  [15:0]  dac_dds_incr_2,
+  output  [15:0]  dac_pat_data_1,
+  output  [15:0]  dac_pat_data_2,
+  output  [ 3:0]  dac_data_sel,
+  output          dac_iq_mode,
+  output          dac_iqcor_enb,
+  output  [15:0]  dac_iqcor_coeff_1,
+  output  [15:0]  dac_iqcor_coeff_2,
 
   // user controls
 
-  output          up_usr_datatype_be;
-  output          up_usr_datatype_signed;
-  output  [ 7:0]  up_usr_datatype_shift;
-  output  [ 7:0]  up_usr_datatype_total_bits;
-  output  [ 7:0]  up_usr_datatype_bits;
-  output  [15:0]  up_usr_interpolation_m;
-  output  [15:0]  up_usr_interpolation_n;
-  input           dac_usr_datatype_be;
-  input           dac_usr_datatype_signed;
-  input   [ 7:0]  dac_usr_datatype_shift;
-  input   [ 7:0]  dac_usr_datatype_total_bits;
-  input   [ 7:0]  dac_usr_datatype_bits;
-  input   [15:0]  dac_usr_interpolation_m;
-  input   [15:0]  dac_usr_interpolation_n;
+  output          up_usr_datatype_be,
+  output          up_usr_datatype_signed,
+  output  [ 7:0]  up_usr_datatype_shift,
+  output  [ 7:0]  up_usr_datatype_total_bits,
+  output  [ 7:0]  up_usr_datatype_bits,
+  output  [15:0]  up_usr_interpolation_m,
+  output  [15:0]  up_usr_interpolation_n,
+  input           dac_usr_datatype_be,
+  input           dac_usr_datatype_signed,
+  input   [ 7:0]  dac_usr_datatype_shift,
+  input   [ 7:0]  dac_usr_datatype_total_bits,
+  input   [ 7:0]  dac_usr_datatype_bits,
+  input   [15:0]  dac_usr_interpolation_m,
+  input   [15:0]  dac_usr_interpolation_n,
 
   // bus interface
 
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
 
   // internal registers
 
-  reg             up_wack = 'd0;
+  reg             up_wack_int = 'd0;
   reg     [15:0]  up_dac_dds_scale_1 = 'd0;
   reg     [15:0]  up_dac_dds_init_1 = 'd0;
   reg     [15:0]  up_dac_dds_incr_1 = 'd0;
@@ -157,16 +112,16 @@ module up_dac_channel (
   reg     [ 3:0]  up_dac_data_sel = 'd0;
   reg     [15:0]  up_dac_iqcor_coeff_1 = 'd0;
   reg     [15:0]  up_dac_iqcor_coeff_2 = 'd0;
-  reg             up_usr_datatype_be = 'd0;
-  reg             up_usr_datatype_signed = 'd0;
-  reg     [ 7:0]  up_usr_datatype_shift = 'd0;
-  reg     [ 7:0]  up_usr_datatype_total_bits = 'd0;
-  reg     [ 7:0]  up_usr_datatype_bits = 'd0;
-  reg     [15:0]  up_usr_interpolation_m = 'd0;
-  reg     [15:0]  up_usr_interpolation_n = 'd0;
+  reg             up_usr_datatype_be_int = 'd0;
+  reg             up_usr_datatype_signed_int = 'd0;
+  reg     [ 7:0]  up_usr_datatype_shift_int = 'd0;
+  reg     [ 7:0]  up_usr_datatype_total_bits_int = 'd0;
+  reg     [ 7:0]  up_usr_datatype_bits_int = 'd0;
+  reg     [15:0]  up_usr_interpolation_m_int = 'd0;
+  reg     [15:0]  up_usr_interpolation_n_int = 'd0;
   reg             up_dac_iq_mode = 'd0;
-  reg             up_rack = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
+  reg             up_rack_int = 'd0;
+  reg     [31:0]  up_rdata_int = 'd0;
   reg     [15:0]  up_dac_dds_scale_tc_1 = 'd0;
   reg     [15:0]  up_dac_dds_scale_tc_2 = 'd0;
   reg     [15:0]  up_dac_iqcor_coeff_tc_1 = 'd0;
@@ -195,38 +150,41 @@ module up_dac_channel (
 
   // decode block select
 
-  assign up_wreq_s = ((up_waddr[13:8] == DAC_COMMON_ID) && (up_waddr[7:4] == DAC_CHANNEL_ID)) ? up_wreq : 1'b0;
-  assign up_rreq_s = ((up_raddr[13:8] == DAC_COMMON_ID) && (up_raddr[7:4] == DAC_CHANNEL_ID)) ? up_rreq : 1'b0;
+  assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0;
+  assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0;
 
   // processor write interface
 
+  assign up_wack = up_wack_int;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack_int <= 'd0;
+    end else begin
+      up_wack_int <= up_wreq_s;
+    end
+  end
+
+  generate
+  if (DDS_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_dac_dds_scale_1 <= 'd0;
+    up_dac_dds_init_1 <= 'd0;
+    up_dac_dds_incr_1 <= 'd0;
+    up_dac_dds_scale_2 <= 'd0;
+    up_dac_dds_init_2 <= 'd0;
+    up_dac_dds_incr_2 <= 'd0;
+  end
+  end else begin
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_wack <= 'd0;
       up_dac_dds_scale_1 <= 'd0;
       up_dac_dds_init_1 <= 'd0;
       up_dac_dds_incr_1 <= 'd0;
       up_dac_dds_scale_2 <= 'd0;
       up_dac_dds_init_2 <= 'd0;
       up_dac_dds_incr_2 <= 'd0;
-      up_dac_pat_data_2 <= 'd0;
-      up_dac_pat_data_1 <= 'd0;
-      up_dac_iqcor_enb <= 'd0;
-      up_dac_lb_enb <= 'd0;
-      up_dac_pn_enb <= 'd0;
-      up_dac_data_sel <= 'd0;
-      up_dac_iqcor_coeff_1 <= 'd0;
-      up_dac_iqcor_coeff_2 <= 'd0;
-      up_usr_datatype_be <= 'd0;
-      up_usr_datatype_signed <= 'd0;
-      up_usr_datatype_shift <= 'd0;
-      up_usr_datatype_total_bits <= 'd0;
-      up_usr_datatype_bits <= 'd0;
-      up_usr_interpolation_m <= 'd0;
-      up_usr_interpolation_n <= 'd0;
-      up_dac_iq_mode <= 'd0;
     end else begin
-      up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
         up_dac_dds_scale_1 <= up_wdata[15:0];
       end
@@ -241,33 +199,128 @@ module up_dac_channel (
         up_dac_dds_init_2 <= up_wdata[31:16];
         up_dac_dds_incr_2 <= up_wdata[15:0];
       end
+    end
+  end
+  end
+  endgenerate
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_dac_pat_data_2 <= 'd0;
+      up_dac_pat_data_1 <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
         up_dac_pat_data_2 <= up_wdata[31:16];
         up_dac_pat_data_1 <= up_wdata[15:0];
       end
+    end
+  end
+
+  generate
+  if (IQCORRECTION_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_dac_iqcor_enb <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_dac_iqcor_enb <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
         up_dac_iqcor_enb <= up_wdata[2];
+      end
+    end
+  end
+  end
+  endgenerate
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_dac_lb_enb <= 'd0;
+      up_dac_pn_enb <= 'd0;
+      up_dac_data_sel <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
         up_dac_lb_enb <= up_wdata[1];
         up_dac_pn_enb <= up_wdata[0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
         up_dac_data_sel <= up_wdata[3:0];
       end
+    end
+  end
+
+  generate
+  if (IQCORRECTION_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_dac_iqcor_coeff_1 <= 'd0;
+    up_dac_iqcor_coeff_2 <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_dac_iqcor_coeff_1 <= 'd0;
+      up_dac_iqcor_coeff_2 <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7)) begin
         up_dac_iqcor_coeff_1 <= up_wdata[31:16];
         up_dac_iqcor_coeff_2 <= up_wdata[15:0];
       end
+    end
+  end
+  end
+  endgenerate
+
+  assign up_usr_datatype_be = up_usr_datatype_be_int;
+  assign up_usr_datatype_signed = up_usr_datatype_signed_int;
+  assign up_usr_datatype_shift = up_usr_datatype_shift_int;
+  assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int;
+  assign up_usr_datatype_bits = up_usr_datatype_bits_int;
+  assign up_usr_interpolation_m = up_usr_interpolation_m_int;
+  assign up_usr_interpolation_n = up_usr_interpolation_n_int;
+
+  generate
+  if (USERPORTS_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_usr_datatype_be_int <= 'd0;
+    up_usr_datatype_signed_int <= 'd0;
+    up_usr_datatype_shift_int <= 'd0;
+    up_usr_datatype_total_bits_int <= 'd0;
+    up_usr_datatype_bits_int <= 'd0;
+    up_usr_interpolation_m_int <= 'd0;
+    up_usr_interpolation_n_int <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_usr_datatype_be_int <= 'd0;
+      up_usr_datatype_signed_int <= 'd0;
+      up_usr_datatype_shift_int <= 'd0;
+      up_usr_datatype_total_bits_int <= 'd0;
+      up_usr_datatype_bits_int <= 'd0;
+      up_usr_interpolation_m_int <= 'd0;
+      up_usr_interpolation_n_int <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
-        up_usr_datatype_be <= up_wdata[25];
-        up_usr_datatype_signed <= up_wdata[24];
-        up_usr_datatype_shift <= up_wdata[23:16];
-        up_usr_datatype_total_bits <= up_wdata[15:8];
-        up_usr_datatype_bits <= up_wdata[7:0];
+        up_usr_datatype_be_int <= up_wdata[25];
+        up_usr_datatype_signed_int <= up_wdata[24];
+        up_usr_datatype_shift_int <= up_wdata[23:16];
+        up_usr_datatype_total_bits_int <= up_wdata[15:8];
+        up_usr_datatype_bits_int <= up_wdata[7:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin
-        up_usr_interpolation_m <= up_wdata[31:16];
-        up_usr_interpolation_n <= up_wdata[15:0];
+        up_usr_interpolation_m_int <= up_wdata[31:16];
+        up_usr_interpolation_n_int <= up_wdata[15:0];
       end
+    end
+  end
+  end
+  endgenerate
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_dac_iq_mode <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin
         up_dac_iq_mode <= up_wdata[0];
       end
@@ -276,31 +329,34 @@ module up_dac_channel (
 
   // processor read interface
 
+  assign up_rack = up_rack_int;
+  assign up_rdata = up_rdata_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
+      up_rack_int <= 'd0;
+      up_rdata_int <= 'd0;
     end else begin
-      up_rack <= up_rreq_s;
+      up_rack_int <= up_rreq_s;
       if (up_rreq_s == 1'b1) begin
         case (up_raddr[3:0])
-          4'h0: up_rdata <= {16'd0, up_dac_dds_scale_1};
-          4'h1: up_rdata <= {up_dac_dds_init_1, up_dac_dds_incr_1};
-          4'h2: up_rdata <= {16'd0, up_dac_dds_scale_2};
-          4'h3: up_rdata <= {up_dac_dds_init_2, up_dac_dds_incr_2};
-          4'h4: up_rdata <= {up_dac_pat_data_2, up_dac_pat_data_1};
-          4'h5: up_rdata <= {29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb};
-          4'h6: up_rdata <= {28'd0, up_dac_data_sel_m};
-          4'h7: up_rdata <= {up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2};
-          4'h8: up_rdata <= {6'd0, dac_usr_datatype_be, dac_usr_datatype_signed,
-                              dac_usr_datatype_shift, dac_usr_datatype_total_bits,
-                              dac_usr_datatype_bits};
-          4'h9: up_rdata <= {dac_usr_interpolation_m, dac_usr_interpolation_n};
-          4'ha: up_rdata <= {31'd0, up_dac_iq_mode};
-          default: up_rdata <= 0;
+          4'h0: up_rdata_int <= { 16'd0, up_dac_dds_scale_1};
+          4'h1: up_rdata_int <= { up_dac_dds_init_1, up_dac_dds_incr_1};
+          4'h2: up_rdata_int <= { 16'd0, up_dac_dds_scale_2};
+          4'h3: up_rdata_int <= { up_dac_dds_init_2, up_dac_dds_incr_2};
+          4'h4: up_rdata_int <= { up_dac_pat_data_2, up_dac_pat_data_1};
+          4'h5: up_rdata_int <= { 29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb};
+          4'h6: up_rdata_int <= { 28'd0, up_dac_data_sel_m};
+          4'h7: up_rdata_int <= { up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2};
+          4'h8: up_rdata_int <= { 6'd0, dac_usr_datatype_be, dac_usr_datatype_signed,
+                                  dac_usr_datatype_shift, dac_usr_datatype_total_bits,
+                                  dac_usr_datatype_bits};
+          4'h9: up_rdata_int <= { dac_usr_interpolation_m, dac_usr_interpolation_n};
+          4'ha: up_rdata_int <= { 31'd0, up_dac_iq_mode};
+          default: up_rdata_int <= 0;
         endcase
       end else begin
-        up_rdata <= 32'd0;
+        up_rdata_int <= 32'd0;
       end
     end
   end
diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index a15349e6b..39c4de5e2 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -37,121 +37,76 @@
 
 `timescale 1ns/100ps
 
-module up_dac_common (
-
-  // mmcm reset
-
-  mmcm_rst,
-
-  // dac interface
-
-  dac_clk,
-  dac_rst,
-  dac_sync,
-  dac_frame,
-  dac_clksel,
-  dac_par_type,
-  dac_par_enb,
-  dac_r1_mode,
-  dac_datafmt,
-  dac_datarate,
-  dac_status,
-  dac_status_ovf,
-  dac_status_unf,
-  dac_clk_ratio,
-
-  // drp interface
-
-  up_drp_sel,
-  up_drp_wr,
-  up_drp_addr,
-  up_drp_wdata,
-  up_drp_rdata,
-  up_drp_ready,
-  up_drp_locked,
-
-  // user channel control
-
-  up_usr_chanmax,
-  dac_usr_chanmax,
-  up_dac_gpio_in,
-  up_dac_gpio_out,
-
-  // bus interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module up_dac_common #(
 
   // parameters
 
-  localparam  PCORE_VERSION = 32'h00080062;
-  parameter   ID = 0;
-  parameter   DAC_COMMON_ID = 6'h10;
+  parameter   ID = 0,
+  parameter   CONFIG = 0,
+  parameter   COMMON_ID = 6'h10,
+  parameter   DRP_DISABLE = 6'h00,
+  parameter   USERPORTS_DISABLE = 0) (
 
   // mmcm reset
 
-  output          mmcm_rst;
+  output          mmcm_rst,
 
   // dac interface
 
-  input           dac_clk;
-  output          dac_rst;
-  output          dac_sync;
-  output          dac_frame;
-  output          dac_clksel;
-  output          dac_par_type;
-  output          dac_par_enb;
-  output          dac_r1_mode;
-  output          dac_datafmt;
-  output  [ 7:0]  dac_datarate;
-  input           dac_status;
-  input           dac_status_ovf;
-  input           dac_status_unf;
-  input   [31:0]  dac_clk_ratio;
+  input           dac_clk,
+  output          dac_rst,
+  output          dac_sync,
+  output          dac_frame,
+  output          dac_clksel,
+  output          dac_par_type,
+  output          dac_par_enb,
+  output          dac_r1_mode,
+  output          dac_datafmt,
+  output  [ 7:0]  dac_datarate,
+  input           dac_status,
+  input           dac_status_ovf,
+  input           dac_status_unf,
+  input   [31:0]  dac_clk_ratio,
 
   // drp interface
 
-  output          up_drp_sel;
-  output          up_drp_wr;
-  output  [11:0]  up_drp_addr;
-  output  [31:0]  up_drp_wdata;
-  input   [31:0]  up_drp_rdata;
-  input           up_drp_ready;
-  input           up_drp_locked;
+  output          up_drp_sel,
+  output          up_drp_wr,
+  output  [11:0]  up_drp_addr,
+  output  [31:0]  up_drp_wdata,
+  input   [31:0]  up_drp_rdata,
+  input           up_drp_ready,
+  input           up_drp_locked,
 
   // user channel control
 
-  output  [ 7:0]  up_usr_chanmax;
-  input   [ 7:0]  dac_usr_chanmax;
-  input   [31:0]  up_dac_gpio_in;
-  output  [31:0]  up_dac_gpio_out;
+  output  [ 7:0]  up_usr_chanmax,
+  input   [ 7:0]  dac_usr_chanmax,
+  input   [31:0]  up_dac_gpio_in,
+  output  [31:0]  up_dac_gpio_out,
 
   // bus interface
 
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
+
+  // parameters
+
+  localparam  VERSION = 32'h00090062;
 
   // internal registers
 
   reg             up_core_preset = 'd0;
   reg             up_mmcm_preset = 'd0;
-  reg             up_wack = 'd0;
+  reg             up_wack_int = 'd0;
   reg     [31:0]  up_scratch = 'd0;
   reg             up_mmcm_resetn = 'd0;
   reg             up_resetn = 'd0;
@@ -163,26 +118,26 @@ module up_dac_common (
   reg     [ 7:0]  up_dac_datarate = 'd0;
   reg             up_dac_frame = 'd0;
   reg             up_dac_clksel = 'd0;
-  reg             up_drp_sel = 'd0;
-  reg             up_drp_wr = 'd0;
+  reg             up_drp_sel_int = 'd0;
+  reg             up_drp_wr_int = 'd0;
   reg             up_drp_status = 'd0;
   reg             up_drp_rwn = 'd0;
-  reg     [11:0]  up_drp_addr = 'd0;
-  reg     [31:0]  up_drp_wdata = 'd0;
+  reg     [11:0]  up_drp_addr_int = 'd0;
+  reg     [31:0]  up_drp_wdata_int = 'd0;
   reg     [31:0]  up_drp_rdata_hold = 'd0;
   reg             up_status_ovf = 'd0;
   reg             up_status_unf = 'd0;
-  reg     [ 7:0]  up_usr_chanmax = 'd0;
-  reg     [31:0]  up_dac_gpio_out = 'd0;
-  reg             up_rack = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
+  reg     [ 7:0]  up_usr_chanmax_int = 'd0;
+  reg     [31:0]  up_dac_gpio_out_int = 'd0;
+  reg             up_rack_int = 'd0;
+  reg     [31:0]  up_rdata_int = 'd0;
   reg             dac_sync_d = 'd0;
   reg             dac_sync_2d = 'd0;
   reg     [ 5:0]  dac_sync_count = 'd0;
-  reg             dac_sync = 'd0;
+  reg             dac_sync_int = 'd0;
   reg             dac_frame_d = 'd0;
   reg             dac_frame_2d = 'd0;
-  reg             dac_frame = 'd0;
+  reg             dac_frame_int = 'd0;
 
   // internal signals
 
@@ -198,16 +153,18 @@ module up_dac_common (
 
   // decode block select
 
-  assign up_wreq_s = (up_waddr[13:8] == DAC_COMMON_ID) ? up_wreq : 1'b0;
-  assign up_rreq_s = (up_raddr[13:8] == DAC_COMMON_ID) ? up_rreq : 1'b0;
+  assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
+  assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
 
   // processor write interface
 
+  assign up_wack = up_wack_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_core_preset <= 1'd1;
       up_mmcm_preset <= 1'd1;
-      up_wack <= 'd0;
+      up_wack_int <= 'd0;
       up_scratch <= 'd0;
       up_mmcm_resetn <= 'd0;
       up_resetn <= 'd0;
@@ -219,21 +176,10 @@ module up_dac_common (
       up_dac_datarate <= 'd0;
       up_dac_frame <= 'd0;
       up_dac_clksel <= 'd0;
-      up_drp_sel <= 'd0;
-      up_drp_wr <= 'd0;
-      up_drp_status <= 'd0;
-      up_drp_rwn <= 'd0;
-      up_drp_addr <= 'd0;
-      up_drp_wdata <= 'd0;
-      up_drp_rdata_hold <= 'd0;
-      up_status_ovf <= 'd0;
-      up_status_unf <= 'd0;
-      up_usr_chanmax <= 'd0;
-      up_dac_gpio_out <= 'd0;
     end else begin
       up_core_preset <= ~up_resetn;
       up_mmcm_preset <= ~up_mmcm_resetn;
-      up_wack <= up_wreq_s;
+      up_wack_int <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
         up_scratch <= up_wdata;
       end
@@ -267,12 +213,42 @@ module up_dac_common (
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
         up_dac_clksel <= up_wdata[0];
       end
+    end
+  end
+
+  assign up_drp_sel = up_drp_sel_int;
+  assign up_drp_wr = up_drp_wr_int;
+  assign up_drp_addr = up_drp_addr_int;
+  assign up_drp_wdata = up_drp_wdata_int;
+
+  generate
+  if (DRP_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_drp_sel_int <= 'd0;
+    up_drp_wr_int <= 'd0;
+    up_drp_status <= 'd0;
+    up_drp_rwn <= 'd0;
+    up_drp_addr_int <= 'd0;
+    up_drp_wdata_int <= 'd0;
+    up_drp_rdata_hold <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_drp_sel_int <= 'd0;
+      up_drp_wr_int <= 'd0;
+      up_drp_status <= 'd0;
+      up_drp_rwn <= 'd0;
+      up_drp_addr_int <= 'd0;
+      up_drp_wdata_int <= 'd0;
+      up_drp_rdata_hold <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
-        up_drp_sel <= 1'b1;
-        up_drp_wr <= ~up_wdata[28];
+        up_drp_sel_int <= 1'b1;
+        up_drp_wr_int <= ~up_wdata[28];
       end else begin
-        up_drp_sel <= 1'b0;
-        up_drp_wr <= 1'b0;
+        up_drp_sel_int <= 1'b0;
+        up_drp_wr_int <= 1'b0;
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_status <= 1'b1;
@@ -281,14 +257,24 @@ module up_dac_common (
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_rwn <= up_wdata[28];
-        up_drp_addr <= up_wdata[27:16];
+        up_drp_addr_int <= up_wdata[27:16];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
-        up_drp_wdata <= up_wdata;
+        up_drp_wdata_int <= up_wdata;
       end
       if (up_drp_ready == 1'b1) begin
         up_drp_rdata_hold <= up_drp_rdata;
       end
+    end
+  end
+  end
+  endgenerate
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_status_ovf <= 'd0;
+      up_status_unf <= 'd0;
+    end else begin
       if (up_status_ovf_s == 1'b1) begin
         up_status_ovf <= 1'b1;
       end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
@@ -299,50 +285,80 @@ module up_dac_common (
       end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
         up_status_unf <= up_status_unf & ~up_wdata[0];
       end
+    end
+  end
+
+  assign up_usr_chanmax = up_usr_chanmax_int;
+
+  generate
+  if (USERPORTS_DISABLE == 1) begin
+  always @(posedge up_clk) begin
+    up_usr_chanmax_int <= 'd0;
+  end
+  end else begin
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_usr_chanmax_int <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
-        up_usr_chanmax <= up_wdata[7:0];
+        up_usr_chanmax_int <= up_wdata[7:0];
       end
+    end
+  end
+  end
+  endgenerate
+
+  assign up_dac_gpio_out = up_dac_gpio_out_int;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_dac_gpio_out_int <= 'd0;
+    end else begin
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
-        up_dac_gpio_out <= up_wdata;
+        up_dac_gpio_out_int <= up_wdata;
       end
     end
   end
 
   // processor read interface
 
+  assign up_rack = up_rack_int;
+  assign up_rdata = up_rdata_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
+      up_rack_int <= 'd0;
+      up_rdata_int <= 'd0;
     end else begin
-      up_rack <= up_rreq_s;
+      up_rack_int <= up_rreq_s;
       if (up_rreq_s == 1'b1) begin
         case (up_raddr[7:0])
-          8'h00: up_rdata <= PCORE_VERSION;
-          8'h01: up_rdata <= ID;
-          8'h02: up_rdata <= up_scratch;
-          8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
-          8'h11: up_rdata <= {31'd0, up_dac_sync};
-          8'h12: up_rdata <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
+          8'h00: up_rdata_int <= VERSION;
+          8'h01: up_rdata_int <= ID;
+          8'h02: up_rdata_int <= up_scratch;
+          8'h03: up_rdata_int <= CONFIG;
+          8'h10: up_rdata_int <= {30'd0, up_mmcm_resetn, up_resetn};
+          8'h11: up_rdata_int <= {31'd0, up_dac_sync};
+          8'h12: up_rdata_int <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
                               up_dac_datafmt, 4'd0};
-          8'h13: up_rdata <= {24'd0, up_dac_datarate};
-          8'h14: up_rdata <= {31'd0, up_dac_frame};
-          8'h15: up_rdata <= up_dac_clk_count_s;
-          8'h16: up_rdata <= dac_clk_ratio;
-          8'h17: up_rdata <= {31'd0, up_status_s};
-          8'h18: up_rdata <= {31'd0, up_dac_clksel};
-          8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, 16'b0};
-          8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, 16'b0};
-          8'h1e: up_rdata <= up_drp_wdata;
-          8'h1f: up_rdata <= up_drp_rdata_hold;
-          8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};
-          8'h28: up_rdata <= {24'd0, dac_usr_chanmax};
-          8'h2e: up_rdata <= up_dac_gpio_in;
-          8'h2f: up_rdata <= up_dac_gpio_out;
-          default: up_rdata <= 0;
+          8'h13: up_rdata_int <= {24'd0, up_dac_datarate};
+          8'h14: up_rdata_int <= {31'd0, up_dac_frame};
+          8'h15: up_rdata_int <= up_dac_clk_count_s;
+          8'h16: up_rdata_int <= dac_clk_ratio;
+          8'h17: up_rdata_int <= {31'd0, up_status_s};
+          8'h18: up_rdata_int <= {31'd0, up_dac_clksel};
+          8'h1c: up_rdata_int <= {3'd0, up_drp_rwn, up_drp_addr_int, 16'b0};
+          8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status, 16'b0};
+          8'h1e: up_rdata_int <= up_drp_wdata_int;
+          8'h1f: up_rdata_int <= up_drp_rdata_hold;
+          8'h22: up_rdata_int <= {30'd0, up_status_ovf, up_status_unf};
+          8'h28: up_rdata_int <= {24'd0, dac_usr_chanmax};
+          8'h2e: up_rdata_int <= up_dac_gpio_in;
+          8'h2f: up_rdata_int <= up_dac_gpio_out_int;
+          default: up_rdata_int <= 0;
         endcase
       end else begin
-        up_rdata <= 32'd0;
+        up_rdata_int <= 32'd0;
       end
     end
   end
@@ -391,6 +407,9 @@ module up_dac_common (
 
   // generate frame and enable
 
+  assign dac_sync = dac_sync_int;
+  assign dac_frame = dac_frame_int;
+
   always @(posedge dac_clk) begin
     dac_sync_d <= dac_sync_s;
     dac_sync_2d <= dac_sync_d;
@@ -399,10 +418,10 @@ module up_dac_common (
     end else if ((dac_sync_d == 1'b1) && (dac_sync_2d == 1'b0)) begin
       dac_sync_count <= 6'h20;
     end
-    dac_sync <= dac_sync_count[5];
+    dac_sync_int <= dac_sync_count[5];
     dac_frame_d <= dac_frame_s;
     dac_frame_2d <= dac_frame_d;
-    dac_frame <= dac_frame_d & ~dac_frame_2d;
+    dac_frame_int <= dac_frame_d & ~dac_frame_2d;
   end
 
   // dac clock monitor
diff --git a/library/common/up_delay_cntrl.v b/library/common/up_delay_cntrl.v
index ab63c9a9f..68d6fdb1f 100644
--- a/library/common/up_delay_cntrl.v
+++ b/library/common/up_delay_cntrl.v
@@ -37,73 +37,49 @@
 
 `timescale 1ns/100ps
 
-module up_delay_cntrl (
-
-  // delay interface
-
-  delay_clk,
-  delay_rst,
-  delay_locked,
-
-  // io interface
-
-  up_dld,
-  up_dwdata,
-  up_drdata,
-
-  // processor interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module up_delay_cntrl #(
 
   // parameters
 
-  parameter   DATA_WIDTH = 8;
-  parameter   BASE_ADDRESS = 6'h02;
+  parameter   DISABLE = 0,
+  parameter   DATA_WIDTH = 8,
+  parameter   BASE_ADDRESS = 6'h02) (
 
   // delay interface
 
-  input                           delay_clk;
-  output                          delay_rst;
-  input                           delay_locked;
+  input                           delay_clk,
+  output                          delay_rst,
+  input                           delay_locked,
 
   // io interface
 
-  output  [(DATA_WIDTH-1):0]      up_dld;
-  output  [((DATA_WIDTH*5)-1):0]  up_dwdata;
-  input   [((DATA_WIDTH*5)-1):0]  up_drdata;
+  output  [(DATA_WIDTH-1):0]      up_dld,
+  output  [((DATA_WIDTH*5)-1):0]  up_dwdata,
+  input   [((DATA_WIDTH*5)-1):0]  up_drdata,
 
   // processor interface
 
-  input                           up_rstn;
-  input                           up_clk;
-  input                           up_wreq;
-  input   [13:0]                  up_waddr;
-  input   [31:0]                  up_wdata;
-  output                          up_wack;
-  input                           up_rreq;
-  input   [13:0]                  up_raddr;
-  output  [31:0]                  up_rdata;
-  output                          up_rack;
+  input                           up_rstn,
+  input                           up_clk,
+  input                           up_wreq,
+  input   [13:0]                  up_waddr,
+  input   [31:0]                  up_wdata,
+  output                          up_wack,
+  input                           up_rreq,
+  input   [13:0]                  up_raddr,
+  output  [31:0]                  up_rdata,
+  output                          up_rack);
 
   // internal registers
   
   reg                             up_preset = 'd0;
-  reg                             up_wack = 'd0;
-  reg                             up_rack = 'd0;
-  reg     [31:0]                  up_rdata = 'd0;
+  reg                             up_wack_int = 'd0;
+  reg                             up_rack_int = 'd0;
+  reg     [31:0]                  up_rdata_int = 'd0;
   reg                             up_dlocked_m1 = 'd0;
   reg                             up_dlocked = 'd0;
-  reg     [(DATA_WIDTH-1):0]      up_dld = 'd0;
-  reg     [((DATA_WIDTH*5)-1):0]  up_dwdata = 'd0;
+  reg     [(DATA_WIDTH-1):0]      up_dld_int = 'd0;
+  reg     [((DATA_WIDTH*5)-1):0]  up_dwdata_int = 'd0;
 
   // internal signals
 
@@ -117,6 +93,7 @@ module up_delay_cntrl (
   wire    [(DATA_WIDTH-1):0]      up_drdata0_s;
   wire    [(DATA_WIDTH-1):0]      up_dld_s;
   wire    [((DATA_WIDTH*5)-1):0]  up_dwdata_s;
+  wire                            delay_rst_s;
 
   // variables
 
@@ -144,26 +121,30 @@ module up_delay_cntrl (
 
   // processor interface
 
+  assign up_wack = (DISABLE == 1) ? 1'd0 : up_wack_int;
+  assign up_rack = (DISABLE == 1) ? 1'd0 : up_rack_int;
+  assign up_rdata = (DISABLE == 1) ? 32'd0 : up_rdata_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_preset <= 1'd1;
-      up_wack <= 'd0;
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
+      up_wack_int <= 'd0;
+      up_rack_int <= 'd0;
+      up_rdata_int <= 'd0;
       up_dlocked_m1 <= 'd0;
       up_dlocked <= 'd0;
     end else begin
       up_preset <= 1'd0;
-      up_wack <= up_wreq_s;
-      up_rack <= up_rreq_s;
+      up_wack_int <= up_wreq_s;
+      up_rack_int <= up_rreq_s;
       if (up_rreq_s == 1'b1) begin
         if (up_dlocked == 1'b0) begin
-          up_rdata <= 32'hffffffff;
+          up_rdata_int <= 32'hffffffff;
         end else begin
-          up_rdata <= {27'd0, up_rdata_s};
+          up_rdata_int <= {27'd0, up_rdata_s};
         end
       end else begin
-        up_rdata <= 32'd0;
+        up_rdata_int <= 32'd0;
       end
       up_dlocked_m1 <= delay_locked;
       up_dlocked <= up_dlocked_m1;
@@ -176,28 +157,33 @@ module up_delay_cntrl (
   for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
   assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0;
   assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ?
-    up_wdata[4:0] : up_dwdata[((n*5)+4):(n*5)];
+    up_wdata[4:0] : up_dwdata_int[((n*5)+4):(n*5)];
   end
   endgenerate
 
+  assign up_dld = (DISABLE == 1) ? 'd0 : up_dld_int;
+  assign up_dwdata = (DISABLE == 1) ? 'd0 : up_dwdata_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_dld <= 'd0;
-      up_dwdata <= 'd0;
+      up_dld_int <= 'd0;
+      up_dwdata_int <= 'd0;
     end else begin
-      up_dld <= up_dld_s;
+      up_dld_int <= up_dld_s;
       if (up_wreq_s == 1'b1) begin
-        up_dwdata <= up_dwdata_s;
+        up_dwdata_int <= up_dwdata_s;
       end
     end
   end
 
   // resets
 
+  assign delay_rst = (DISABLE == 1) ? 1'd0 : delay_rst_s;
+
   ad_rst i_delay_rst_reg (
     .preset (up_preset),
     .clk (delay_clk),
-    .rst (delay_rst));
+    .rst (delay_rst_s));
 
 endmodule
 

From 1a11e28821223f3d61aa14094eedff6fe80983ec Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 23 Sep 2016 16:13:46 -0400
Subject: [PATCH 524/972] ad9361- dac data path split

---
 library/axi_ad9361/axi_ad9361.v            |   7 +-
 library/axi_ad9361/axi_ad9361_tx.v         | 260 ++++++++++-----------
 library/axi_ad9361/axi_ad9361_tx_channel.v | 175 +++++++-------
 3 files changed, 203 insertions(+), 239 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 531f85e4d..73c378e98 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -654,8 +654,11 @@ module axi_ad9361 (
 
   axi_ad9361_tx #(
     .ID (ID),
-    .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE),
-    .R1_MODE_EN (R1_MODE_EN))
+    .MODE_1R1T (R1_MODE_EN),
+    .DDS_DISABLE (DAC_DATAPATH_DISABLE),
+    .USERPORTS_DISABLE (DAC_DATAPATH_DISABLE),
+    .DELAYCNTRL_DISABLE (DAC_DATAPATH_DISABLE),
+    .IQCORRECTION_DISABLE (DAC_DATAPATH_DISABLE))
   i_tx (
     .dac_clk (clk),
     .dac_valid (dac_valid_s),
diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v
index a6312493f..c6484a5e6 100644
--- a/library/axi_ad9361/axi_ad9361_tx.v
+++ b/library/axi_ad9361/axi_ad9361_tx.v
@@ -37,142 +37,95 @@
 
 `timescale 1ns/100ps
 
-module axi_ad9361_tx (
-
-  // dac interface
-
-  dac_clk,
-  dac_valid,
-  dac_data,
-  dac_clksel,
-  dac_r1_mode,
-  adc_data,
-
-  // delay interface
-
-  up_dld,
-  up_dwdata,
-  up_drdata,
-  delay_clk,
-  delay_rst,
-  delay_locked,
-
-  // master/slave
-
-  dac_sync_in,
-  dac_sync_out,
-
-  // dma interface
-
-  dac_enable_i0,
-  dac_valid_i0,
-  dac_data_i0,
-  dac_enable_q0,
-  dac_valid_q0,
-  dac_data_q0,
-  dac_enable_i1,
-  dac_valid_i1,
-  dac_data_i1,
-  dac_enable_q1,
-  dac_valid_q1,
-  dac_data_q1,
-  dac_dovf,
-  dac_dunf,
-
-  // gpio
-
-  up_dac_gpio_in,
-  up_dac_gpio_out,
-
-  // processor interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module axi_ad9361_tx #(
 
   // parameters
 
-  parameter   DATAPATH_DISABLE = 0;
-  parameter   ID = 0;
-  parameter   R1_MODE_EN = 0;
+  parameter   ID = 0,
+  parameter   MODE_1R1T = 0,
+  parameter   DDS_DISABLE = 0,
+  parameter   USERPORTS_DISABLE = 0,
+  parameter   DELAYCNTRL_DISABLE = 0,
+  parameter   IQCORRECTION_DISABLE = 0) (
 
   // dac interface
 
-  input           dac_clk;
-  output          dac_valid;
-  output  [47:0]  dac_data;
-  output          dac_clksel;
-  output          dac_r1_mode;
-  input   [47:0]  adc_data;
+  input           dac_clk,
+  output          dac_valid,
+  output  [47:0]  dac_data,
+  output          dac_clksel,
+  output          dac_r1_mode,
+  input   [47:0]  adc_data,
 
   // delay interface
 
-  output  [15:0]  up_dld;
-  output  [79:0]  up_dwdata;
-  input   [79:0]  up_drdata;
-  input           delay_clk;
-  output          delay_rst;
-  input           delay_locked;
+  output  [15:0]  up_dld,
+  output  [79:0]  up_dwdata,
+  input   [79:0]  up_drdata,
+  input           delay_clk,
+  output          delay_rst,
+  input           delay_locked,
 
   // master/slave
 
-  input           dac_sync_in;
-  output          dac_sync_out;
+  input           dac_sync_in,
+  output          dac_sync_out,
 
   // dma interface
 
-  output          dac_enable_i0;
-  output          dac_valid_i0;
-  input   [15:0]  dac_data_i0;
-  output          dac_enable_q0;
-  output          dac_valid_q0;
-  input   [15:0]  dac_data_q0;
-  output          dac_enable_i1;
-  output          dac_valid_i1;
-  input   [15:0]  dac_data_i1;
-  output          dac_enable_q1;
-  output          dac_valid_q1;
-  input   [15:0]  dac_data_q1;
-  input           dac_dovf;
-  input           dac_dunf;
+  output          dac_enable_i0,
+  output          dac_valid_i0,
+  input   [15:0]  dac_data_i0,
+  output          dac_enable_q0,
+  output          dac_valid_q0,
+  input   [15:0]  dac_data_q0,
+  output          dac_enable_i1,
+  output          dac_valid_i1,
+  input   [15:0]  dac_data_i1,
+  output          dac_enable_q1,
+  output          dac_valid_q1,
+  input   [15:0]  dac_data_q1,
+  input           dac_dovf,
+  input           dac_dunf,
 
   // gpio
 
-  input   [31:0]  up_dac_gpio_in;
-  output  [31:0]  up_dac_gpio_out;
+  input   [31:0]  up_dac_gpio_in,
+  output  [31:0]  up_dac_gpio_out,
 
   // processor interface
 
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
+
+  // configuration settings
+
+  localparam  CONFIG =  (DDS_DISABLE * 64) +
+                        (DELAYCNTRL_DISABLE * 32) +
+                        (MODE_1R1T * 16) +
+                        (USERPORTS_DISABLE * 8) +
+                        (IQCORRECTION_DISABLE * 1);
 
   // internal registers
 
   reg             dac_data_sync = 'd0;
   reg     [ 7:0]  dac_rate_cnt = 'd0;
-  reg             dac_valid = 'd0;
-  reg             dac_valid_i0 = 'd0;
-  reg             dac_valid_q0 = 'd0;
-  reg             dac_valid_i1 = 'd0;
-  reg             dac_valid_q1 = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
-  reg             up_rack = 'd0;
-  reg             up_wack = 'd0;
+  reg             dac_valid_int = 'd0;
+  reg             dac_valid_i0_int = 'd0;
+  reg             dac_valid_q0_int = 'd0;
+  reg             dac_valid_i1_int = 'd0;
+  reg             dac_valid_q1_int = 'd0;
+  reg             up_wack_int = 'd0;
+  reg             up_rack_int = 'd0;
+  reg     [31:0]  up_rdata_int = 'd0;
 
   // internal clock and resets
 
@@ -184,9 +137,9 @@ module axi_ad9361_tx (
   wire            dac_dds_format_s;
   wire    [ 7:0]  dac_datarate_s;
   wire    [47:0]  dac_data_int_s;
+  wire    [ 5:0]  up_wack_s;
+  wire    [ 5:0]  up_rack_s;
   wire    [31:0]  up_rdata_s[0:5];
-  wire            up_rack_s[0:5];
-  wire            up_wack_s[0:5];
 
   // master/slave
 
@@ -208,28 +161,36 @@ module axi_ad9361_tx (
 
   // dma interface
 
+  assign dac_valid = dac_valid_int;
+  assign dac_valid_i0 = dac_valid_i0_int;
+  assign dac_valid_q0 = dac_valid_q0_int;
+  assign dac_valid_i1 = dac_valid_i1_int;
+  assign dac_valid_q1 = dac_valid_q1_int;
+
   always @(posedge dac_clk) begin
-    dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
-    dac_valid_i0 <= dac_valid;
-    dac_valid_q0 <= dac_valid;
-    dac_valid_i1 <= dac_valid & ~dac_r1_mode;
-    dac_valid_q1 <= dac_valid & ~dac_r1_mode;
+    dac_valid_int <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
+    dac_valid_i0_int <= dac_valid_int;
+    dac_valid_q0_int <= dac_valid_int;
+    dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode;
+    dac_valid_q1_int <= dac_valid_int & ~dac_r1_mode;
   end
 
   // processor read interface
 
+  assign up_wack = up_wack_int;
+  assign up_rack = up_rack_int;
+  assign up_rdata = up_rdata_int;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_rdata <= 'd0;
-      up_rack <= 'd0;
-      up_wack <= 'd0;
+      up_wack_int <= 'd0;
+      up_rack_int <= 'd0;
+      up_rdata_int <= 'd0;
     end else begin
-      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
-                  up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
-      up_rack <=  up_rack_s[0]  | up_rack_s[1]  | up_rack_s[2]  |
-                  up_rack_s[3]  | up_rack_s[4]  | up_rack_s[5];
-      up_wack <=  up_wack_s[0]  | up_wack_s[1]  | up_wack_s[2]  |
-                  up_wack_s[3]  | up_wack_s[4]  | up_wack_s[5];
+      up_wack_int <=  | up_wack_s;
+      up_rack_int <=  | up_rack_s;
+      up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
+        up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
     end
   end
 
@@ -238,11 +199,14 @@ module axi_ad9361_tx (
   axi_ad9361_tx_channel #(
     .CHANNEL_ID (0),
     .Q_OR_I_N (0),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    .DISABLE (0),
+    .DDS_DISABLE (DDS_DISABLE),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
   i_tx_channel_0 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
-    .dac_valid (dac_valid),
+    .dac_valid (dac_valid_int),
     .dma_data (dac_data_i0),
     .adc_data (adc_data[11:0]),
     .dac_data (dac_data[11:0]),
@@ -267,11 +231,14 @@ module axi_ad9361_tx (
   axi_ad9361_tx_channel #(
     .CHANNEL_ID (1),
     .Q_OR_I_N (1),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    .DISABLE (0),
+    .DDS_DISABLE (DDS_DISABLE),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
   i_tx_channel_1 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
-    .dac_valid (dac_valid),
+    .dac_valid (dac_valid_int),
     .dma_data (dac_data_q0),
     .adc_data (adc_data[23:12]),
     .dac_data (dac_data[23:12]),
@@ -291,19 +258,19 @@ module axi_ad9361_tx (
     .up_rdata (up_rdata_s[1]),
     .up_rack (up_rack_s[1]));
 
-  generate
-  if (R1_MODE_EN == 0) begin
-
   // dac channel
 
   axi_ad9361_tx_channel #(
     .CHANNEL_ID (2),
     .Q_OR_I_N (0),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    .DISABLE (MODE_1R1T),
+    .DDS_DISABLE (DDS_DISABLE),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
   i_tx_channel_2 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
-    .dac_valid (dac_valid),
+    .dac_valid (dac_valid_int),
     .dma_data (dac_data_i1),
     .adc_data (adc_data[35:24]),
     .dac_data (dac_data[35:24]),
@@ -328,11 +295,14 @@ module axi_ad9361_tx (
   axi_ad9361_tx_channel #(
     .CHANNEL_ID (3),
     .Q_OR_I_N (1),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+    .DISABLE (MODE_1R1T),
+    .DDS_DISABLE (DDS_DISABLE),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
   i_tx_channel_3 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
-    .dac_valid (dac_valid),
+    .dac_valid (dac_valid_int),
     .dma_data (dac_data_q1),
     .adc_data (adc_data[47:36]),
     .dac_data (dac_data[47:36]),
@@ -352,12 +322,14 @@ module axi_ad9361_tx (
     .up_rdata (up_rdata_s[3]),
     .up_rack (up_rack_s[3]));
 
-  end
-  endgenerate
-
   // dac common processor interface
 
-  up_dac_common #(.ID (ID)) i_up_dac_common (
+  up_dac_common #(
+    .ID (ID),
+    .CONFIG (CONFIG),
+    .DRP_DISABLE (1),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE))
+  i_up_dac_common (
     .mmcm_rst (),
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
@@ -397,7 +369,11 @@ module axi_ad9361_tx (
 
   // dac delay control
 
-  up_delay_cntrl #(.DATA_WIDTH(16), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
+  up_delay_cntrl #(
+    .DISABLE (DELAYCNTRL_DISABLE),
+    .DATA_WIDTH(16),
+    .BASE_ADDRESS(6'h12))
+  i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked),
diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v
index 53d63f473..f69ea52f9 100644
--- a/library/axi_ad9361/axi_ad9361_tx_channel.v
+++ b/library/axi_ad9361/axi_ad9361_tx_channel.v
@@ -37,85 +37,61 @@
 
 `timescale 1ns/100ps
 
-module axi_ad9361_tx_channel (
-
-  // dac interface
-
-  dac_clk,
-  dac_rst,
-  dac_valid,
-  dma_data,
-  adc_data,
-  dac_data,
-  dac_data_out,
-  dac_data_in,
-
-  // processor interface
-
-  dac_enable,
-  dac_data_sync,
-  dac_dds_format,
-
-  // bus interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
+module axi_ad9361_tx_channel #(
+
+  // parameters
+
+  parameter   Q_OR_I_N = 0,
+  parameter   CHANNEL_ID = 32'h0,
+  parameter   DISABLE = 0,
+  parameter   DDS_DISABLE = 0,
+  parameter   USERPORTS_DISABLE = 0,
+  parameter   IQCORRECTION_DISABLE = 0) (
+
+  // dac interface
+
+  input           dac_clk,
+  input           dac_rst,
+  input           dac_valid,
+  input   [15:0]  dma_data,
+  input   [11:0]  adc_data,
+  output  [11:0]  dac_data,
+  output  [11:0]  dac_data_out,
+  input   [11:0]  dac_data_in,
+
+  // processor interface
+
+  output          dac_enable,
+  input           dac_data_sync,
+  input           dac_dds_format,
+
+  // bus interface
+
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
 
   // parameters
 
-  parameter   CHANNEL_ID = 32'h0;
-  parameter   Q_OR_I_N = 0;
-  parameter   DATAPATH_DISABLE = 0;
   localparam  PRBS_SEL = CHANNEL_ID;
   localparam  PRBS_P09  = 0;
   localparam  PRBS_P11  = 1;
   localparam  PRBS_P15  = 2;
   localparam  PRBS_P20  = 3;
 
-  // dac interface
-
-  input           dac_clk;
-  input           dac_rst;
-  input           dac_valid;
-  input   [15:0]  dma_data;
-  input   [11:0]  adc_data;
-  output  [11:0]  dac_data;
-  output  [11:0]  dac_data_out;
-  input   [11:0]  dac_data_in;
-
-  // processor interface
-
-  output          dac_enable;
-  input           dac_data_sync;
-  input           dac_dds_format;
-
-  // bus interface
-
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
-
   // internal registers
 
   reg             dac_valid_sel = 'd0;
-  reg             dac_enable = 'd0;
-  reg     [11:0]  dac_data = 'd0;
-  reg     [11:0]  dac_data_out = 'd0;
+  reg             dac_enable_int = 'd0;
+  reg     [11:0]  dac_data_int = 'd0;
+  reg     [11:0]  dac_data_out_int = 'd0;
   reg     [23:0]  dac_pn_seq = 'd0;
   reg     [11:0]  dac_pn_data = 'd0;
   reg     [15:0]  dac_pat_data = 'd0;
@@ -142,6 +118,9 @@ module axi_ad9361_tx_channel (
   wire            dac_iqcor_enb_s;
   wire    [15:0]  dac_iqcor_coeff_1_s;
   wire    [15:0]  dac_iqcor_coeff_2_s;
+  wire            up_wack_s;
+  wire            up_rack_s;
+  wire    [31:0]  up_rdata_s;
 
   // standard prbs functions
 
@@ -271,41 +250,42 @@ module axi_ad9361_tx_channel (
 
   // dac iq correction
 
+  assign dac_enable = (DISABLE == 1) ? 'd0 : dac_enable_int;
+  assign dac_data = (DISABLE == 1) ? 'd0 : dac_data_int;
+
   always @(posedge dac_clk) begin
-    dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
+    dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
     if (dac_iqcor_valid_s == 1'b1) begin
-      dac_data <= dac_iqcor_data_s[15:4];
+      dac_data_int <= dac_iqcor_data_s[15:4];
     end
   end
 
-  generate
-  if (DATAPATH_DISABLE == 1) begin
-  assign dac_iqcor_valid_s = dac_valid;
-  assign dac_iqcor_data_s = {dac_data_out, 4'd0};
-  end else begin
-  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
+  ad_iqcor #(
+    .Q_OR_I_N (Q_OR_I_N),
+    .DISABLE (IQCORRECTION_DISABLE))
+  i_ad_iqcor (
     .clk (dac_clk),
     .valid (dac_valid),
-    .data_in ({dac_data_out, 4'd0}),
+    .data_in ({dac_data_out_int, 4'd0}),
     .data_iq ({dac_data_in, 4'd0}),
     .valid_out (dac_iqcor_valid_s),
     .data_out (dac_iqcor_data_s),
     .iqcor_enable (dac_iqcor_enb_s),
     .iqcor_coeff_1 (dac_iqcor_coeff_1_s),
     .iqcor_coeff_2 (dac_iqcor_coeff_2_s));
-  end
-  endgenerate
 
   // dac mux
 
+  assign dac_data_out = (DISABLE == 1) ? 'd0 : dac_data_out_int;
+
   always @(posedge dac_clk) begin
     case (dac_data_sel_s)
-      4'h9: dac_data_out <= dac_pn_data;
-      4'h8: dac_data_out <= adc_data;
-      4'h3: dac_data_out <= 12'd0;
-      4'h2: dac_data_out <= dma_data[15:4];
-      4'h1: dac_data_out <= dac_pat_data[15:4];
-      default: dac_data_out <= dac_dds_data[15:4];
+      4'h9: dac_data_out_int <= dac_pn_data;
+      4'h8: dac_data_out_int <= adc_data;
+      4'h3: dac_data_out_int <= 12'd0;
+      4'h2: dac_data_out_int <= dma_data[15:4];
+      4'h1: dac_data_out_int <= dac_pat_data[15:4];
+      default: dac_data_out_int <= dac_dds_data[15:4];
     endcase
   end
 
@@ -358,11 +338,9 @@ module axi_ad9361_tx_channel (
 
   // dds
 
-  generate
-  if (DATAPATH_DISABLE == 1) begin
-  assign dac_dds_data_s = 16'd0;
-  end else begin
-  ad_dds i_dds (
+  ad_dds #(
+    .DISABLE (DDS_DISABLE))
+  i_dds (
     .clk (dac_clk),
     .dds_format (dac_dds_format),
     .dds_phase_0 (dac_dds_phase_0),
@@ -370,12 +348,19 @@ module axi_ad9361_tx_channel (
     .dds_phase_1 (dac_dds_phase_1),
     .dds_scale_1 (dac_dds_scale_2_s),
     .dds_data (dac_dds_data_s));
-  end
-  endgenerate
 
   // single channel processor
 
-  up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+  assign up_wack = (DISABLE == 1) ? 'd0 : up_wack_s;
+  assign up_rack = (DISABLE == 1) ? 'd0 : up_rack_s;
+  assign up_rdata = (DISABLE == 1) ? 'd0 : up_rdata_s;
+
+  up_dac_channel #(
+    .CHANNEL_ID (CHANNEL_ID),
+    .DDS_DISABLE (DDS_DISABLE),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
+  i_up_dac_channel (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
@@ -410,11 +395,11 @@ module axi_ad9361_tx_channel (
     .up_wreq (up_wreq),
     .up_waddr (up_waddr),
     .up_wdata (up_wdata),
-    .up_wack (up_wack),
+    .up_wack (up_wack_s),
     .up_rreq (up_rreq),
     .up_raddr (up_raddr),
-    .up_rdata (up_rdata),
-    .up_rack (up_rack));
+    .up_rdata (up_rdata_s),
+    .up_rack (up_rack_s));
   
 endmodule
 

From f6c7aa9005ee16fc82f428c19fc5454554453eaa Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 23 Sep 2016 16:15:59 -0400
Subject: [PATCH 525/972] library- dac parameter changes

---
 library/axi_ad9122/axi_ad9122_channel.v    | 2 +-
 library/axi_ad9144/axi_ad9144_channel.v    | 2 +-
 library/axi_ad9152/axi_ad9152_channel.v    | 2 +-
 library/axi_ad9162/axi_ad9162_channel.v    | 2 +-
 library/axi_ad9371/axi_ad9371_tx_channel.v | 2 +-
 library/axi_ad9739a/axi_ad9739a_channel.v  | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v
index d2bf47c45..31ac94a4b 100644
--- a/library/axi_ad9122/axi_ad9122_channel.v
+++ b/library/axi_ad9122/axi_ad9122_channel.v
@@ -245,7 +245,7 @@ module axi_ad9122_channel (
 
   // single channel processor
 
-  up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+  up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v
index 2559eb86d..7794a4a5c 100644
--- a/library/axi_ad9144/axi_ad9144_channel.v
+++ b/library/axi_ad9144/axi_ad9144_channel.v
@@ -410,7 +410,7 @@ module axi_ad9144_channel (
   
   // single channel processor
 
-  up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+  up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
diff --git a/library/axi_ad9152/axi_ad9152_channel.v b/library/axi_ad9152/axi_ad9152_channel.v
index dd5c0d1b0..a597e025f 100644
--- a/library/axi_ad9152/axi_ad9152_channel.v
+++ b/library/axi_ad9152/axi_ad9152_channel.v
@@ -556,7 +556,7 @@ module axi_ad9152_channel (
   
   // single channel processor
 
-  up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+  up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v
index 249510144..c15a3a996 100644
--- a/library/axi_ad9162/axi_ad9162_channel.v
+++ b/library/axi_ad9162/axi_ad9162_channel.v
@@ -600,7 +600,7 @@ module axi_ad9162_channel (
     
     // single channel processor
     
-    up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+    up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
       .dac_clk (dac_clk),
       .dac_rst (dac_rst),
       .dac_dds_scale_1 (dac_dds_scale_1_s),
diff --git a/library/axi_ad9371/axi_ad9371_tx_channel.v b/library/axi_ad9371/axi_ad9371_tx_channel.v
index 6dc5f100d..32da01b64 100644
--- a/library/axi_ad9371/axi_ad9371_tx_channel.v
+++ b/library/axi_ad9371/axi_ad9371_tx_channel.v
@@ -237,7 +237,7 @@ module axi_ad9371_tx_channel (
 
   // single channel processor
 
-  up_dac_channel #(.DAC_CHANNEL_ID (CHANNEL_ID)) i_up_dac_channel (
+  up_dac_channel #(.CHANNEL_ID (CHANNEL_ID)) i_up_dac_channel (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
diff --git a/library/axi_ad9739a/axi_ad9739a_channel.v b/library/axi_ad9739a/axi_ad9739a_channel.v
index 3e8605054..d6cb660e8 100644
--- a/library/axi_ad9739a/axi_ad9739a_channel.v
+++ b/library/axi_ad9739a/axi_ad9739a_channel.v
@@ -638,7 +638,7 @@ module axi_ad9739a_channel (
   
   // single channel processor
 
-  up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+  up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),

From 2d307d5f58ab857a82913cf766d12db8a3c18a9a Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Sat, 24 Sep 2016 10:06:35 +0300
Subject: [PATCH 526/972] a10soc: Added system reset bridge. Using F2SDRAM port
 used in the previous Qsys design

---
 projects/common/a10soc/a10soc_system_qsys.tcl | 32 +++++++++++++------
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl
index 837a92860..c3e4e33e0 100755
--- a/projects/common/a10soc/a10soc_system_qsys.tcl
+++ b/projects/common/a10soc/a10soc_system_qsys.tcl
@@ -14,6 +14,12 @@ set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
 set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
 set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
 
+add_instance sys_rst altera_reset_bridge 16.0
+set_instance_parameter_value sys_rst {ACTIVE_LOW_RESET} {0}
+set_instance_parameter_value sys_rst {SYNCHRONOUS_EDGES} {deassert}
+set_instance_parameter_value sys_rst {NUM_RESET_OUTPUTS} {1}
+set_instance_parameter_value sys_rst {USE_RESET_REQUEST} {0}
+
 # HPS
 add_instance arria10_hps_0 altera_arria10_hps 16.0
 set_instance_parameter_value arria10_hps_0 {MPU_EVENTS_Enable} {0}
@@ -30,9 +36,9 @@ set_instance_parameter_value arria10_hps_0 {F2S_Width} {0}
 set_instance_parameter_value arria10_hps_0 {S2F_Width} {0}
 set_instance_parameter_value arria10_hps_0 {LWH2F_Enable} {1}
 set_instance_parameter_value arria10_hps_0 {RUN_INTERNAL_BUILD_CHECKS} {0}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {6}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {1}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {0}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {5}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {0}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {1}
 set_instance_parameter_value arria10_hps_0 {F2SDRAM2_ENABLED} {0}
 set_instance_parameter_value arria10_hps_0 {F2SDRAM_READY_LATENCY} {0}
 set_instance_parameter_value arria10_hps_0 {F2SDRAM2_DELAY} {4}
@@ -94,8 +100,8 @@ set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2
 set_instance_parameter_value arria10_hps_0 {MPU_CLK_VCCL} {0}
 set_instance_parameter_value arria10_hps_0 {USE_DEFAULT_MPU_CLK} {0}
 set_instance_parameter_value arria10_hps_0 {CUSTOM_MPU_CLK} {800}
-set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {1}
-set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {150}
+set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {0}
+set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {400}
 set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_Enable} {0}
 set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_FREQ} {400}
 set_instance_parameter_value arria10_hps_0 {HMC_PLL_REF_CLK} {800}
@@ -1242,16 +1248,24 @@ add_connection sys_clk.clk arria10_hps_0.h2f_lw_axi_clock clock
 add_connection sys_clk.clk sys_spi.clk clock
 add_connection sys_clk.clk gpio_i.clk clock
 add_connection sys_clk.clk gpio_o.clk clock
+add_connection sys_clk.clk sys_rst.clk clock
 
-add_connection arria10_hps_0.h2f_user0_clock arria10_hps_0.f2sdram0_clock clock
+add_connection sys_clk.clk arria10_hps_0.f2sdram1_clock clock
 
 add_connection emif_a10_hps_0.hps_emif_conduit_end arria10_hps_0.emif conduit
+set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif endPort {}
+set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif endPortLSB {0}
+set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif startPort {}
+set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif startPortLSB {0}
+set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif width {0}
 
 add_connection sys_clk.clk_reset arria10_hps_0.f2h_cold_reset_req reset
 add_connection sys_clk.clk_reset emif_a10_hps_0.global_reset_reset_sink reset
-add_connection sys_clk.clk_reset sys_spi.reset reset
-add_connection sys_clk.clk_reset gpio_i.reset reset
-add_connection sys_clk.clk_reset gpio_o.reset reset
+add_connection sys_clk.clk_reset sys_rst.in_reset reset
+add_connection arria10_hps_0.h2f_reset sys_rst.in_reset reset
+add_connection sys_rst.out_reset sys_spi.reset reset
+add_connection sys_rst.out_reset gpio_i.reset reset
+add_connection sys_rst.out_reset gpio_o.reset reset
 
 # exported interfaces
 add_interface hps_ddr conduit end

From f5809b88174a9a9e71fd4710ba4d9bcdf3841abe Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Sat, 24 Sep 2016 10:09:05 +0300
Subject: [PATCH 527/972] adrv9371x: a10soc, added adcfifos; connected the new
 reset to all peripherals; used the new f2sdram1 port

---
 projects/adrv9371x/common/adrv9371x_qsys.tcl | 58 ++++++++++++++------
 1 file changed, 40 insertions(+), 18 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index dd237be5e..dc98fb212 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -162,11 +162,9 @@ set_instance_parameter_value xcvr_tx_lane_pll {enable_8G_path} {1}
 set_instance_parameter_value xcvr_tx_lane_pll {enable_16G_path} {0}
 set_instance_parameter_value xcvr_tx_lane_pll {enable_pcie_clk} {0}
 set_instance_parameter_value xcvr_tx_lane_pll {enable_cascade_out} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_atx_to_fpll_cascade_out} {0}
 set_instance_parameter_value xcvr_tx_lane_pll {enable_hip_cal_done_port} {0}
 set_instance_parameter_value xcvr_tx_lane_pll {set_hip_cal_en} {0}
 set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {2457.6}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_fractional} {0}
 set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {122.88}
 set_instance_parameter_value xcvr_tx_lane_pll {set_manual_reference_clock_frequency} {200.0}
 set_instance_parameter_value xcvr_tx_lane_pll {set_fref_clock_frequency} {156.25}
@@ -453,7 +451,7 @@ set_instance_parameter_value rx_os_adcfifo {DMA_ADDRESS_WIDTH} {16}
 add_instance axi_adc_dma axi_dmac 1.0
 set_instance_parameter_value axi_adc_dma {ID} {0}
 set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {256}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
 set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
 set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
 set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
@@ -470,7 +468,7 @@ set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {16}
 add_instance axi_os_adc_dma axi_dmac 1.0
 set_instance_parameter_value axi_os_adc_dma {ID} {0}
 set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {256}
+set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {64}
 set_instance_parameter_value axi_os_adc_dma {DMA_LENGTH_WIDTH} {24}
 set_instance_parameter_value axi_os_adc_dma {DMA_2D_TRANSFER} {0}
 set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_REQ_SRC} {1}
@@ -486,7 +484,7 @@ set_instance_parameter_value axi_os_adc_dma {FIFO_SIZE} {16}
 
 add_instance axi_dac_dma axi_dmac 1.0
 set_instance_parameter_value axi_dac_dma {ID} {0}
-set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {256}
+set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {128}
 set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {128}
 set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
 set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
@@ -541,6 +539,7 @@ add_connection sys_clk.clk axi_ad9371.s_axi_clock
 add_connection sys_clk.clk axi_os_adc_dma.s_axi_clock
 add_connection sys_clk.clk ad9371_gpio.clk
 
+add_connection sys_clk.clk_reset xcvr_rx_core.jesd204_rx_avs_rst_n
 add_connection sys_clk.clk_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n
 add_connection sys_clk.clk_reset xcvr_tx_core.jesd204_tx_avs_rst_n
 add_connection sys_clk.clk_reset xcvr_pll_reconfig.mgmt_reset
@@ -562,6 +561,30 @@ add_connection sys_clk.clk_reset ad9371_gpio.reset
 add_connection sys_clk.clk_reset rx_adcfifo.if_adc_rst
 add_connection sys_clk.clk_reset rx_os_adcfifo.if_adc_rst
 
+if { $system_type=="a10soc" } {
+  add_connection sys_rst.out_reset xcvr_rx_core.jesd204_rx_avs_rst_n
+  add_connection sys_rst.out_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n
+  add_connection sys_rst.out_reset xcvr_tx_core.jesd204_tx_avs_rst_n
+  add_connection sys_rst.out_reset xcvr_pll_reconfig.mgmt_reset
+  add_connection sys_rst.out_reset xcvr_tx_lane_pll.reconfig_reset0
+  add_connection sys_rst.out_reset xcvr_pll.reset
+  add_connection sys_rst.out_reset xcvr_rx_rst_cntrl.reset
+  add_connection sys_rst.out_reset xcvr_tx_rst_cntrl.reset
+  add_connection sys_rst.out_reset xcvr_rx_os_rst_cntrl.reset
+  #add_connection sys_rst.out_reset xcvr_rx_core.reconfig_reset
+  #add_connection sys_rst.out_reset xcvr_rx_os_core.reconfig_reset
+  add_connection sys_rst.out_reset xcvr_tx_core.reconfig_reset
+  add_connection sys_rst.out_reset axi_adc_dma.s_axi_reset
+  add_connection sys_rst.out_reset axi_dac_dma.s_axi_reset
+  add_connection sys_rst.out_reset axi_jesd_xcvr.s_axi_reset
+  add_connection sys_rst.out_reset axi_os_jesd_xcvr.s_axi_reset
+  add_connection sys_rst.out_reset axi_ad9371.s_axi_reset
+  add_connection sys_rst.out_reset axi_os_adc_dma.s_axi_reset
+  add_connection sys_rst.out_reset ad9371_gpio.reset
+  add_connection sys_rst.out_reset rx_adcfifo.if_adc_rst
+  add_connection sys_rst.out_reset rx_os_adcfifo.if_adc_rst
+}
+
 add_connection xcvr_pll.outclk0 axi_ad9371.if_dac_clk
 add_connection xcvr_pll.outclk0 dac_upack.if_dac_clk
 add_connection xcvr_pll.outclk0 axi_dac_dma.if_fifo_rd_clk
@@ -594,12 +617,12 @@ if { $system_type=="nios" } {
 
 # SOC
 if { $system_type=="a10soc" } {
-  add_connection arria10_hps_0.h2f_user0_clock axi_adc_dma.m_dest_axi_clock
-  add_connection arria10_hps_0.h2f_user0_clock axi_os_adc_dma.m_dest_axi_clock
-  add_connection arria10_hps_0.h2f_user0_clock axi_dac_dma.m_src_axi_clock
-  add_connection sys_clk.clk_reset axi_adc_dma.m_dest_axi_reset
-  add_connection sys_clk.clk_reset axi_os_adc_dma.m_dest_axi_reset
-  add_connection sys_clk.clk_reset axi_dac_dma.m_src_axi_reset
+  add_connection xcvr_pll.outclk1 axi_adc_dma.m_dest_axi_clock
+  add_connection xcvr_pll.outclk2 axi_os_adc_dma.m_dest_axi_clock
+  add_connection xcvr_pll.outclk0 axi_dac_dma.m_src_axi_clock
+  add_connection sys_rst.out_reset axi_adc_dma.m_dest_axi_reset
+  add_connection sys_rst.out_reset axi_os_adc_dma.m_dest_axi_reset
+  add_connection sys_rst.out_reset axi_dac_dma.m_src_axi_reset
 }
 
 add_connection adc_pack.adc_ch_0 axi_ad9371.adc_ch_0
@@ -683,7 +706,6 @@ add_connection axi_jesd_xcvr.if_rx_rstn xcvr_rx_core.rxlink_rst_n
 add_connection axi_os_jesd_xcvr.if_rx_rstn xcvr_rx_os_core.rxlink_rst_n
 add_connection axi_jesd_xcvr.if_tx_rstn xcvr_tx_core.txlink_rst_n
 
-add_connection sys_clk.clk_reset xcvr_rx_core.jesd204_rx_avs_rst_n
 
 add_interface rx_data conduit end
 set_interface_property rx_data EXPORT_OF xcvr_rx_core.rx_serial_data
@@ -778,9 +800,9 @@ if { $system_type=="a10soc" } {
   add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.jesd204_tx_avs
   add_connection arria10_hps_0.h2f_lw_axi_master ad9371_gpio.s1
 
-  add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data
-  add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data
-  add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram0_data
+  add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram1_data
+  add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram1_data
+  add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram1_data
 
   set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/ad9371_gpio.s1 baseAddress {0x00001000}
   set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_pll_reconfig.mgmt_avalon_slave baseAddress {0x00010000}
@@ -796,9 +818,9 @@ if { $system_type=="a10soc" } {
   set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_adc_dma.s_axi baseAddress {0x0090000}
   set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_adc_dma.s_axi baseAddress {0x000a0000}
 
-  set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
-  set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
-  set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
+  set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000}
+  set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000}
+  set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000}
 }
 
 # interrupts

From ad16aec101ba104da7c6246cd4a4b9a043ddbe53 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 23 Sep 2016 16:46:03 +0300
Subject: [PATCH 528/972] axi_ad9684: Fix SERDES modules

---
 library/axi_ad9684/axi_ad9684.v    |  6 +--
 library/axi_ad9684/axi_ad9684_if.v | 72 ++++++++++--------------------
 2 files changed, 27 insertions(+), 51 deletions(-)

diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v
index 010bcf5fd..8a0c51d27 100644
--- a/library/axi_ad9684/axi_ad9684.v
+++ b/library/axi_ad9684/axi_ad9684.v
@@ -191,7 +191,7 @@ module axi_ad9684 (
   wire    [15:0]  up_drp_rdata_s;
   wire            up_drp_ready_s;
   wire            up_drp_locked_s;
-  wire            mmcm_rst_s;
+  wire            rst_s;
 
   //defaults
 
@@ -239,7 +239,7 @@ module axi_ad9684 (
     .delay_wdata (up_dwdata_s),
     .delay_rdata (up_drdata_s),
     .delay_locked (delay_locked_s),
-    .mmcm_rst (mmcm_rst_s),
+    .rst (rst_s),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel_s),
@@ -259,7 +259,7 @@ module axi_ad9684 (
   up_adc_common #(
     .ID(ID))
   i_up_adc_common (
-    .mmcm_rst (mmcm_rst_s),
+    .mmcm_rst (rst_s),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_r1_mode (),
diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v
index 14f49babe..abceac525 100644
--- a/library/axi_ad9684/axi_ad9684_if.v
+++ b/library/axi_ad9684/axi_ad9684_if.v
@@ -67,8 +67,8 @@ module axi_ad9684_if (
   delay_rdata,
   delay_locked,
 
-  // mmcm_rst
-  mmcm_rst,
+  // reset
+  rst,
 
   // drp interface
   up_clk,
@@ -114,7 +114,7 @@ module axi_ad9684_if (
   output  [74:0]  delay_rdata;
   output          delay_locked;
 
-  input           mmcm_rst;
+  input           rst;
 
   input           up_clk;
   input           up_rstn;
@@ -152,61 +152,32 @@ module axi_ad9684_if (
     .IODELAY_CTRL(1),
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(DDR_OR_SDR_N),
-    .DATA_WIDTH(4))
+    .DATA_WIDTH(14))
   i_adc_data (
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
-    .data_s0(adc_data_b[(1*14)]),
-    .data_s1(adc_data_a[(1*14)]),
-    .data_s2(adc_data_b[(0*14)]),
-    .data_s3(adc_data_a[(0*14)]),
+    .loaden(1'b0),
+    .phase(8'b0),
+    .locked(1'b0),
+    .data_s0(adc_data_b[27:14]),
+    .data_s1(adc_data_a[27:14]),
+    .data_s2(adc_data_b[13: 0]),
+    .data_s3(adc_data_a[13: 0]),
     .data_s4(),
     .data_s5(),
     .data_s6(),
     .data_s7(),
-    .data_in_p(adc_data_in_p[0]),
-    .data_in_n(adc_data_in_n[0]),
+    .data_in_p(adc_data_in_p[13:0]),
+    .data_in_n(adc_data_in_n[13:0]),
     .up_clk (up_clk),
-    .up_dld (delay_dload[0]),
-    .up_dwdata (delay_wdata[4:0]),
-    .up_drdata (delay_rdata[4:0]),
+    .up_dld (delay_dload[13:0]),
+    .up_dwdata (delay_wdata[69:0]),
+    .up_drdata (delay_rdata[69:0]),
     .delay_clk(delay_clk),
     .delay_rst(delay_rst),
     .delay_locked(delay_locked));
 
-  generate
-  for (l_inst = 1; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
-    ad_serdes_in #(
-      .DEVICE_TYPE(DEVICE_TYPE),
-      .IODELAY_CTRL(0),
-      .IODELAY_GROUP(IO_DELAY_GROUP),
-      .DDR_OR_SDR_N(DDR_OR_SDR_N),
-      .DATA_WIDTH(4))
-    i_adc_data (
-      .rst(adc_rst),
-      .clk(adc_clk_in),
-      .div_clk(adc_div_clk),
-      .data_s0(adc_data_b[(1*14)+l_inst]),
-      .data_s1(adc_data_a[(1*14)+l_inst]),
-      .data_s2(adc_data_b[(0*14)+l_inst]),
-      .data_s3(adc_data_a[(0*14)+l_inst]),
-      .data_s4(),
-      .data_s5(),
-      .data_s6(),
-      .data_s7(),
-      .data_in_p(adc_data_in_p[l_inst]),
-      .data_in_n(adc_data_in_n[l_inst]),
-      .up_clk (up_clk),
-      .up_dld (delay_dload[l_inst]),
-      .up_dwdata (delay_wdata[((l_inst*5)+4):(l_inst*5)]),
-      .up_drdata (delay_rdata[((l_inst*5)+4):(l_inst*5)]),
-      .delay_clk(delay_clk),
-      .delay_rst(delay_rst),
-      .delay_locked());
-    end
-  endgenerate
-
   generate if (OR_STATUS == 1) begin
 
     ad_serdes_in #(
@@ -214,11 +185,14 @@ module axi_ad9684_if (
       .IODELAY_CTRL(0),
       .IODELAY_GROUP(IO_DELAY_GROUP),
       .DDR_OR_SDR_N(DDR_OR_SDR_N),
-      .DATA_WIDTH(4))
+      .DATA_WIDTH(1))
     i_adc_or (
       .rst(adc_rst),
       .clk(adc_clk_in),
       .div_clk(adc_div_clk),
+      .loaden(1'b0),
+      .phase(8'b0),
+      .locked(1'b0),
       .data_s0(adc_data_or_b_s[1]),
       .data_s1(adc_data_or_a_s[1]),
       .data_s2(adc_data_or_b_s[0]),
@@ -251,19 +225,21 @@ module axi_ad9684_if (
   // clock input buffers and MMCM_OR_BUFR_N
 
   ad_serdes_clk #(
-    .MMCM_DEVICE_TYPE (DEVICE_TYPE),
+    .DEVICE_TYPE (DEVICE_TYPE),
     .MMCM_CLKIN_PERIOD (2),
     .MMCM_VCO_DIV (6),
     .MMCM_VCO_MUL (12),
     .MMCM_CLK0_DIV (2),
     .MMCM_CLK1_DIV (4))
   i_serdes_clk (
-    .mmcm_rst (mmcm_rst),
+    .rst (rst),
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk_in),
     .div_clk (adc_div_clk),
     .out_clk (),
+    .loaden (),
+    .phase (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),

From 7fd9280cbfa129bc2a16b9c566f7307b207a4c63 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 26 Sep 2016 15:19:05 -0400
Subject: [PATCH 529/972] fmcomms11- xcvr updates

---
 projects/fmcomms11/zc706/Makefile          | 12 +++---
 projects/fmcomms11/zc706/system_constr.xdc |  7 +++-
 projects/fmcomms11/zc706/system_top.v      | 47 +++++++++++++++++-----
 3 files changed, 49 insertions(+), 17 deletions(-)

diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile
index 6ac361e20..2fe7881e4 100644
--- a/projects/fmcomms11/zc706/Makefile
+++ b/projects/fmcomms11/zc706/Makefile
@@ -24,13 +24,13 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9162/axi_ad9162.xpr
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -62,13 +62,13 @@ clean-all:clean
 	make -C ../../../library/axi_ad9162 clean
 	make -C ../../../library/axi_ad9625 clean
 	make -C ../../../library/xilinx/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_jesd_gt clean
 
 
 fmcomms11_zc706.sdk/system_top.hdf: $(M_DEPS)
@@ -80,13 +80,13 @@ lib:
 	make -C ../../../library/axi_ad9162
 	make -C ../../../library/axi_ad9625
 	make -C ../../../library/xilinx/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc
index 4f0d4369d..89407b217 100644
--- a/projects/fmcomms11/zc706/system_constr.xdc
+++ b/projects/fmcomms11/zc706/system_constr.xdc
@@ -67,6 +67,9 @@ set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports ad9162_i
 
 create_clock -name tx_ref_clk   -period  6.40 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  6.40 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_fmcomms11_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_fmcomms11_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9162_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
 
diff --git a/projects/fmcomms11/zc706/system_top.v b/projects/fmcomms11/zc706/system_top.v
index c124326ad..bdad159a4 100644
--- a/projects/fmcomms11/zc706/system_top.v
+++ b/projects/fmcomms11/zc706/system_top.v
@@ -279,10 +279,25 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_data_4_n (rx_data_n[4]),
+    .rx_data_4_p (rx_data_p[4]),
+    .rx_data_5_n (rx_data_n[5]),
+    .rx_data_5_p (rx_data_p[5]),
+    .rx_data_6_n (rx_data_n[6]),
+    .rx_data_6_p (rx_data_p[6]),
+    .rx_data_7_n (rx_data_n[7]),
+    .rx_data_7_p (rx_data_p[7]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),
@@ -305,11 +320,25 @@ module system_top (
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
-    .sysref (sysref),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync));
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
+    .tx_data_4_n (tx_data_n[4]),
+    .tx_data_4_p (tx_data_p[4]),
+    .tx_data_5_n (tx_data_n[5]),
+    .tx_data_5_p (tx_data_p[5]),
+    .tx_data_6_n (tx_data_n[6]),
+    .tx_data_6_p (tx_data_p[6]),
+    .tx_data_7_n (tx_data_n[7]),
+    .tx_data_7_p (tx_data_p[7]),
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (sysref));
 
 endmodule
 

From 8314efd4e9e9f8ad822ee7b0ef6411d9cc50c4fe Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 26 Sep 2016 15:19:29 -0400
Subject: [PATCH 530/972] fmcomms11- xcvr updates

---
 projects/fmcomms11/common/fmcomms11_bd.tcl | 329 +++------------------
 1 file changed, 36 insertions(+), 293 deletions(-)

diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index 59c36419a..609abb8aa 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -1,23 +1,14 @@
 
-# fmcomms11
-
-create_bd_port -dir I sysref
-
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir I -from 7 -to 0 rx_data_p
-create_bd_port -dir I -from 7 -to 0 rx_data_n
-
-create_bd_port -dir I tx_ref_clk
-create_bd_port -dir I tx_sync
-create_bd_port -dir O -from 7 -to 0 tx_data_p
-create_bd_port -dir O -from 7 -to 0 tx_data_n
-
 # dac peripherals
 
+set axi_ad9162_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9162_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9162_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9162_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9162_xcvr
+
 set axi_ad9162_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9162:1.0 axi_ad9162_core]
 
-set axi_ad9162_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9162_jesd]
+set axi_ad9162_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9162_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9162_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9162_jesd
 
@@ -35,9 +26,14 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9162_dma
 
 # adc peripherals
 
+set axi_ad9625_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_xcvr
+
 set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
 
-set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd]
+set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
 
@@ -54,162 +50,26 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 
-# dac/adc common gt
+# shared transceiver core
 
-set axi_fmcomms11_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcomms11_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL1_REFCLK_DIV {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL0_CFG {0x0680181}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL1_CFG {0x0680181}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL0_FBDIV_RATIO {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL1_FBDIV_RATIO {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL0_FBDIV {"0100100000"}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL1_FBDIV {"0100100000"}] $axi_fmcomms11_gt   
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff10400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff10400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_2 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff10400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_3 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff10400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_4 {4}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_4 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_4 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff10400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_5 {4}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_5 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_5 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff10400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_6 {4}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_6 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_6 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff10400020}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_7 {4}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_7 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_7 {7}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcomms11_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff10400020}] $axi_fmcomms11_gt
+set util_fmcomms11_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms11_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {7}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.PMA_RSV {0x00018480}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr
 
-set util_fmcomms11_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcomms11_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_fmcomms11_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $util_fmcomms11_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcomms11_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcomms11_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_gt
-set_property -dict [list CONFIG.TX_ENABLE {1}] $util_fmcomms11_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_gt
-
-# connections (gt)
-
-ad_connect  util_fmcomms11_gt/qpll_ref_clk tx_ref_clk
-ad_connect  util_fmcomms11_gt/cpll_ref_clk tx_ref_clk
-
-ad_connect  axi_fmcomms11_gt/gt_qpll_0 util_fmcomms11_gt/gt_qpll_0
-ad_connect  axi_fmcomms11_gt/gt_qpll_1 util_fmcomms11_gt/gt_qpll_1
-ad_connect  axi_fmcomms11_gt/gt_pll_0 util_fmcomms11_gt/gt_pll_0
-ad_connect  axi_fmcomms11_gt/gt_pll_1 util_fmcomms11_gt/gt_pll_1
-ad_connect  axi_fmcomms11_gt/gt_pll_2 util_fmcomms11_gt/gt_pll_2
-ad_connect  axi_fmcomms11_gt/gt_pll_3 util_fmcomms11_gt/gt_pll_3
-ad_connect  axi_fmcomms11_gt/gt_pll_4 util_fmcomms11_gt/gt_pll_4
-ad_connect  axi_fmcomms11_gt/gt_pll_5 util_fmcomms11_gt/gt_pll_5
-ad_connect  axi_fmcomms11_gt/gt_pll_6 util_fmcomms11_gt/gt_pll_6
-ad_connect  axi_fmcomms11_gt/gt_pll_7 util_fmcomms11_gt/gt_pll_7
-ad_connect  axi_fmcomms11_gt/gt_rx_0 util_fmcomms11_gt/gt_rx_0
-ad_connect  axi_fmcomms11_gt/gt_rx_1 util_fmcomms11_gt/gt_rx_1
-ad_connect  axi_fmcomms11_gt/gt_rx_2 util_fmcomms11_gt/gt_rx_2
-ad_connect  axi_fmcomms11_gt/gt_rx_3 util_fmcomms11_gt/gt_rx_3
-ad_connect  axi_fmcomms11_gt/gt_rx_4 util_fmcomms11_gt/gt_rx_4
-ad_connect  axi_fmcomms11_gt/gt_rx_5 util_fmcomms11_gt/gt_rx_5
-ad_connect  axi_fmcomms11_gt/gt_rx_6 util_fmcomms11_gt/gt_rx_6
-ad_connect  axi_fmcomms11_gt/gt_rx_7 util_fmcomms11_gt/gt_rx_7
-ad_connect  axi_fmcomms11_gt/gt_rx_ip_0 axi_ad9625_jesd/gt0_rx
-ad_connect  axi_fmcomms11_gt/gt_rx_ip_1 axi_ad9625_jesd/gt1_rx
-ad_connect  axi_fmcomms11_gt/gt_rx_ip_2 axi_ad9625_jesd/gt2_rx
-ad_connect  axi_fmcomms11_gt/gt_rx_ip_3 axi_ad9625_jesd/gt3_rx
-ad_connect  axi_fmcomms11_gt/gt_rx_ip_4 axi_ad9625_jesd/gt4_rx
-ad_connect  axi_fmcomms11_gt/gt_rx_ip_5 axi_ad9625_jesd/gt5_rx
-ad_connect  axi_fmcomms11_gt/gt_rx_ip_6 axi_ad9625_jesd/gt6_rx
-ad_connect  axi_fmcomms11_gt/gt_rx_ip_7 axi_ad9625_jesd/gt7_rx
-ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_0 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_1 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_2 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_3 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_4 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_5 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_6 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms11_gt/rx_gt_comma_align_enb_7 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms11_gt/gt_tx_0 util_fmcomms11_gt/gt_tx_0
-ad_connect  axi_fmcomms11_gt/gt_tx_1 util_fmcomms11_gt/gt_tx_1
-ad_connect  axi_fmcomms11_gt/gt_tx_2 util_fmcomms11_gt/gt_tx_2
-ad_connect  axi_fmcomms11_gt/gt_tx_3 util_fmcomms11_gt/gt_tx_3
-ad_connect  axi_fmcomms11_gt/gt_tx_4 util_fmcomms11_gt/gt_tx_4
-ad_connect  axi_fmcomms11_gt/gt_tx_5 util_fmcomms11_gt/gt_tx_5
-ad_connect  axi_fmcomms11_gt/gt_tx_6 util_fmcomms11_gt/gt_tx_6
-ad_connect  axi_fmcomms11_gt/gt_tx_7 util_fmcomms11_gt/gt_tx_7
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_0 axi_ad9162_jesd/gt0_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_1 axi_ad9162_jesd/gt1_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_2 axi_ad9162_jesd/gt2_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_3 axi_ad9162_jesd/gt3_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_4 axi_ad9162_jesd/gt4_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_5 axi_ad9162_jesd/gt5_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_6 axi_ad9162_jesd/gt6_tx
-ad_connect  axi_fmcomms11_gt/gt_tx_ip_7 axi_ad9162_jesd/gt7_tx
+ad_connect  sys_cpu_resetn util_fmcomms11_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_fmcomms11_xcvr/up_clk
 
 # connections (dac)
 
-ad_connect  util_fmcomms11_gt/tx_sysref sysref
-ad_connect  util_fmcomms11_gt/tx_p tx_data_p
-ad_connect  util_fmcomms11_gt/tx_n tx_data_n
-ad_connect  util_fmcomms11_gt/tx_sync tx_sync
-ad_connect  util_fmcomms11_gt/tx_out_clk util_fmcomms11_gt/tx_clk
-ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9162_jesd/tx_core_clk
-ad_connect  util_fmcomms11_gt/tx_ip_rst axi_ad9162_jesd/tx_reset
-ad_connect  util_fmcomms11_gt/tx_ip_rst_done axi_ad9162_jesd/tx_reset_done
-ad_connect  util_fmcomms11_gt/tx_ip_sysref axi_ad9162_jesd/tx_sysref
-ad_connect  util_fmcomms11_gt/tx_ip_sync axi_ad9162_jesd/tx_sync
-ad_connect  util_fmcomms11_gt/tx_ip_data axi_ad9162_jesd/tx_tdata
-ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9162_core/tx_clk
-ad_connect  util_fmcomms11_gt/tx_data axi_ad9162_core/tx_data
-ad_connect  util_fmcomms11_gt/tx_out_clk axi_ad9162_fifo/dac_clk
+ad_xcvrcon  util_fmcomms11_xcvr axi_ad9162_xcvr axi_ad9162_jesd
+ad_connect  util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_core/tx_clk
+ad_connect  axi_ad9162_jesd/tx_tdata axi_ad9162_core/tx_data
+ad_connect  util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_fifo/dac_clk
 ad_connect  axi_ad9162_core/dac_valid axi_ad9162_fifo/dac_valid
 ad_connect  axi_ad9162_core/dac_ddata axi_ad9162_fifo/dac_data
 ad_connect  sys_cpu_clk axi_ad9162_fifo/dma_clk
@@ -224,24 +84,12 @@ ad_connect  axi_ad9162_fifo/dma_xfer_last axi_ad9162_dma/m_axis_last
 
 # connections (adc)
 
-ad_connect  util_fmcomms11_gt/rx_sysref sysref
-ad_connect  util_fmcomms11_gt/rx_p rx_data_p
-ad_connect  util_fmcomms11_gt/rx_n rx_data_n
-ad_connect  util_fmcomms11_gt/rx_sync rx_sync
-ad_connect  util_fmcomms11_gt/rx_out_clk util_fmcomms11_gt/rx_clk
-ad_connect  util_fmcomms11_gt/rx_out_clk axi_ad9625_jesd/rx_core_clk
-ad_connect  util_fmcomms11_gt/rx_ip_rst axi_ad9625_jesd/rx_reset
-ad_connect  util_fmcomms11_gt/rx_ip_rst_done axi_ad9625_jesd/rx_reset_done
-ad_connect  util_fmcomms11_gt/rx_ip_sysref axi_ad9625_jesd/rx_sysref
-ad_connect  util_fmcomms11_gt/rx_ip_sync axi_ad9625_jesd/rx_sync
-ad_connect  util_fmcomms11_gt/rx_ip_sof axi_ad9625_jesd/rx_start_of_frame
-ad_connect  util_fmcomms11_gt/rx_ip_data axi_ad9625_jesd/rx_tdata
-ad_connect  util_fmcomms11_gt/rx_out_clk axi_ad9625_core/rx_clk
-ad_connect  util_fmcomms11_gt/rx_data axi_ad9625_core/rx_data
-ad_connect  axi_ad9625_core/adc_raddr_in GND
-ad_connect  axi_ad9625_core/adc_dunf GND
-ad_connect  util_fmcomms11_gt/rx_out_clk axi_ad9625_fifo/adc_clk
-ad_connect  util_fmcomms11_gt/rx_rst axi_ad9625_fifo/adc_rst
+ad_xcvrcon  util_fmcomms11_xcvr axi_ad9625_xcvr axi_ad9625_jesd
+ad_connect  util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk
+ad_connect  axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof
+ad_connect  axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data
+ad_connect  util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk
+ad_connect  axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
 ad_connect  axi_ad9625_core/adc_valid axi_ad9625_fifo/adc_wr
 ad_connect  axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
 ad_connect  sys_cpu_clk axi_ad9625_fifo/dma_clk
@@ -255,10 +103,11 @@ ad_connect  axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_fmcomms11_gt
+ad_cpu_interconnect 0x44A60000 axi_ad9162_xcvr
 ad_cpu_interconnect 0x44A00000 axi_ad9162_core
 ad_cpu_interconnect 0x44A90000 axi_ad9162_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9162_dma
+ad_cpu_interconnect 0x44A50000 axi_ad9625_xcvr
 ad_cpu_interconnect 0x44A10000 axi_ad9625_core
 ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9625_dma
@@ -266,7 +115,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9625_dma
 # gt uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_fmcomms11_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_xcvr/m_axi
 
 # interconnect (mem/dac)
 
@@ -284,109 +133,3 @@ ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
 
 ad_connect  axi_ad9162_fifo/dac_fifo_bypass GND
 
-# ila
-
-create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ad9625_ila
-set_property CONFIG.C_MONITOR_TYPE {Native} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_NUM_OF_PROBES {33} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE0_WIDTH  {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE1_WIDTH  {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE2_WIDTH  {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE3_WIDTH  {32} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE4_WIDTH  {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE5_WIDTH  {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE6_WIDTH  {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE7_WIDTH  {32} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE8_WIDTH  {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE9_WIDTH  {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE10_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE11_WIDTH {32} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE12_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE13_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE14_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE15_WIDTH {32} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE16_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE17_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE18_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE19_WIDTH {32} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE20_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE21_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE22_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE23_WIDTH {32} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE24_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE25_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE26_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE27_WIDTH {32} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE28_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE29_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE30_WIDTH {4}  [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE31_WIDTH {32} [get_bd_cells ad9625_ila]
-set_property CONFIG.C_PROBE32_WIDTH {1}  [get_bd_cells ad9625_ila]
-
-ad_connect  axi_ad9625_jesd/gt0_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_0   
-ad_connect  axi_ad9625_jesd/gt0_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_0   
-ad_connect  axi_ad9625_jesd/gt0_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_0
-ad_connect  axi_ad9625_jesd/gt0_rxdata       axi_fmcomms11_gt/rx_gt_data_0      
-ad_connect  axi_ad9625_jesd/gt1_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_1   
-ad_connect  axi_ad9625_jesd/gt1_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_1   
-ad_connect  axi_ad9625_jesd/gt1_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_1
-ad_connect  axi_ad9625_jesd/gt1_rxdata       axi_fmcomms11_gt/rx_gt_data_1      
-ad_connect  axi_ad9625_jesd/gt2_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_2   
-ad_connect  axi_ad9625_jesd/gt2_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_2   
-ad_connect  axi_ad9625_jesd/gt2_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_2
-ad_connect  axi_ad9625_jesd/gt2_rxdata       axi_fmcomms11_gt/rx_gt_data_2      
-ad_connect  axi_ad9625_jesd/gt3_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_3   
-ad_connect  axi_ad9625_jesd/gt3_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_3   
-ad_connect  axi_ad9625_jesd/gt3_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_3
-ad_connect  axi_ad9625_jesd/gt3_rxdata       axi_fmcomms11_gt/rx_gt_data_3      
-ad_connect  axi_ad9625_jesd/gt4_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_4   
-ad_connect  axi_ad9625_jesd/gt4_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_4   
-ad_connect  axi_ad9625_jesd/gt4_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_4
-ad_connect  axi_ad9625_jesd/gt4_rxdata       axi_fmcomms11_gt/rx_gt_data_4      
-ad_connect  axi_ad9625_jesd/gt5_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_5   
-ad_connect  axi_ad9625_jesd/gt5_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_5   
-ad_connect  axi_ad9625_jesd/gt5_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_5
-ad_connect  axi_ad9625_jesd/gt5_rxdata       axi_fmcomms11_gt/rx_gt_data_5      
-ad_connect  axi_ad9625_jesd/gt6_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_6   
-ad_connect  axi_ad9625_jesd/gt6_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_6   
-ad_connect  axi_ad9625_jesd/gt6_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_6
-ad_connect  axi_ad9625_jesd/gt6_rxdata       axi_fmcomms11_gt/rx_gt_data_6      
-ad_connect  axi_ad9625_jesd/gt7_rxcharisk    axi_fmcomms11_gt/rx_gt_charisk_7   
-ad_connect  axi_ad9625_jesd/gt7_rxdisperr    axi_fmcomms11_gt/rx_gt_disperr_7   
-ad_connect  axi_ad9625_jesd/gt7_rxnotintable axi_fmcomms11_gt/rx_gt_notintable_7
-ad_connect  axi_ad9625_jesd/gt7_rxdata       axi_fmcomms11_gt/rx_gt_data_7      
-
-ad_connect  axi_fmcomms11_gt/rx_gt_charisk_0    ad9625_ila/probe0
-ad_connect  axi_fmcomms11_gt/rx_gt_disperr_0    ad9625_ila/probe1
-ad_connect  axi_fmcomms11_gt/rx_gt_notintable_0 ad9625_ila/probe2
-ad_connect  axi_fmcomms11_gt/rx_gt_data_0       ad9625_ila/probe3
-ad_connect  axi_fmcomms11_gt/rx_gt_charisk_1    ad9625_ila/probe4
-ad_connect  axi_fmcomms11_gt/rx_gt_disperr_1    ad9625_ila/probe5
-ad_connect  axi_fmcomms11_gt/rx_gt_notintable_1 ad9625_ila/probe6
-ad_connect  axi_fmcomms11_gt/rx_gt_data_1       ad9625_ila/probe7
-ad_connect  axi_fmcomms11_gt/rx_gt_charisk_2    ad9625_ila/probe8
-ad_connect  axi_fmcomms11_gt/rx_gt_disperr_2    ad9625_ila/probe9
-ad_connect  axi_fmcomms11_gt/rx_gt_notintable_2 ad9625_ila/probe10
-ad_connect  axi_fmcomms11_gt/rx_gt_data_2       ad9625_ila/probe11
-ad_connect  axi_fmcomms11_gt/rx_gt_charisk_3    ad9625_ila/probe12
-ad_connect  axi_fmcomms11_gt/rx_gt_disperr_3    ad9625_ila/probe13
-ad_connect  axi_fmcomms11_gt/rx_gt_notintable_3 ad9625_ila/probe14
-ad_connect  axi_fmcomms11_gt/rx_gt_data_3       ad9625_ila/probe15
-ad_connect  axi_fmcomms11_gt/rx_gt_charisk_4    ad9625_ila/probe16
-ad_connect  axi_fmcomms11_gt/rx_gt_disperr_4    ad9625_ila/probe17
-ad_connect  axi_fmcomms11_gt/rx_gt_notintable_4 ad9625_ila/probe18
-ad_connect  axi_fmcomms11_gt/rx_gt_data_4       ad9625_ila/probe19
-ad_connect  axi_fmcomms11_gt/rx_gt_charisk_5    ad9625_ila/probe20
-ad_connect  axi_fmcomms11_gt/rx_gt_disperr_5    ad9625_ila/probe21
-ad_connect  axi_fmcomms11_gt/rx_gt_notintable_5 ad9625_ila/probe22
-ad_connect  axi_fmcomms11_gt/rx_gt_data_5       ad9625_ila/probe23
-ad_connect  axi_fmcomms11_gt/rx_gt_charisk_6    ad9625_ila/probe24
-ad_connect  axi_fmcomms11_gt/rx_gt_disperr_6    ad9625_ila/probe25
-ad_connect  axi_fmcomms11_gt/rx_gt_notintable_6 ad9625_ila/probe26
-ad_connect  axi_fmcomms11_gt/rx_gt_data_6       ad9625_ila/probe27
-ad_connect  axi_fmcomms11_gt/rx_gt_charisk_7    ad9625_ila/probe28
-ad_connect  axi_fmcomms11_gt/rx_gt_disperr_7    ad9625_ila/probe29
-ad_connect  axi_fmcomms11_gt/rx_gt_notintable_7 ad9625_ila/probe30
-ad_connect  axi_fmcomms11_gt/rx_gt_data_7       ad9625_ila/probe31
-ad_connect  axi_ad9625_jesd/rx_sync             ad9625_ila/probe32
-ad_connect  util_fmcomms11_gt/rx_out_clk        ad9625_ila/clk

From 79b9e21be8c9cc4c123c3f21370a708c30291ce0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 26 Sep 2016 15:20:18 -0400
Subject: [PATCH 531/972] board- xcvr procedure

---
 projects/scripts/adi_board.tcl | 81 ++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 175db0a7b..0df39b0d6 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -8,6 +8,9 @@ variable sys_hp2_interconnect_index
 variable sys_hp3_interconnect_index
 variable sys_mem_interconnect_index
 
+variable xcvr_tx_index
+variable xcvr_rx_index
+
 ###################################################################################################
 ###################################################################################################
 
@@ -18,6 +21,9 @@ set sys_hp2_interconnect_index -1
 set sys_hp3_interconnect_index -1
 set sys_mem_interconnect_index -1
 
+set xcvr_tx_index 0
+set xcvr_rx_index 0
+
 ###################################################################################################
 ###################################################################################################
 
@@ -94,6 +100,81 @@ proc ad_connect {p_name_1 p_name_2} {
   }
 }
 
+proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
+
+  global xcvr_tx_index
+  global xcvr_rx_index
+
+  set no_of_lanes [get_property CONFIG.NUM_OF_LANES [get_bd_cells $a_xcvr]]
+  set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
+  set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
+
+  set txrx "rx"
+  set data_dir "I"
+  set ctrl_dir "O"
+  set index $xcvr_rx_index
+
+  if {$tx_or_rx_n == 1} {
+
+    set txrx "tx"
+    set data_dir "O"
+    set ctrl_dir "I"
+    set index $xcvr_tx_index
+  }
+
+  create_bd_port -dir I ${txrx}_ref_clk_${index}
+  create_bd_port -dir I ${txrx}_sysref_${index}
+  create_bd_port -dir ${ctrl_dir} ${txrx}_sync_${index}
+  create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ${a_jesd}_rstgen
+
+  for {set n 0} {$n < $no_of_lanes} {incr n} {
+
+    set m [expr ($n + $index)]
+
+    if {$tx_or_rx_n == 0} {
+      ad_connect  ${a_xcvr}/up_es_${m} ${u_xcvr}/up_es_${m}
+      ad_connect  ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${m}
+    }
+
+    if {(($m%4) == 0) && ($qpll_enable == 1)} {
+      ad_connect  ${a_xcvr}/up_cm_${m} ${u_xcvr}/up_cm_${m}
+    }
+
+    ad_connect  ${a_xcvr}/up_ch_${m} ${u_xcvr}/up_${txrx}_${m}
+    ad_connect  ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${m}_${txrx}
+    ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
+
+    if {(($m%4) == 0) && ($qpll_enable == 1)} {
+      ad_connect  ${u_xcvr}/qpll_ref_clk_${m} ${txrx}_ref_clk_${index}
+    }
+
+    if {$qpll_enable == 0} {
+      ad_connect  ${u_xcvr}/cpll_ref_clk_${m} ${txrx}_ref_clk_${index}
+    }
+
+    create_bd_port -dir ${data_dir} ${txrx}_data_${m}_p
+    create_bd_port -dir ${data_dir} ${txrx}_data_${m}_n
+    ad_connect  ${u_xcvr}/${txrx}_${m}_p ${txrx}_data_${m}_p
+    ad_connect  ${u_xcvr}/${txrx}_${m}_n ${txrx}_data_${m}_n
+  }
+
+  ad_connect  ${a_jesd}/${txrx}_sysref ${txrx}_sysref_${index}
+  ad_connect  ${a_jesd}/${txrx}_sync ${txrx}_sync_${index}
+  ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk
+  ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
+  ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk
+  ad_connect  sys_cpu_resetn ${a_jesd}_rstgen/ext_reset_in
+  ad_connect  ${a_jesd}_rstgen/peripheral_reset ${a_jesd}/${txrx}_reset
+
+  if {$tx_or_rx_n == 0} {
+    set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]
+  }
+
+  if {$tx_or_rx_n == 1} {
+    set xcvr_tx_index [expr ($xcvr_tx_index + $no_of_lanes)]
+  }
+}
+
 proc ad_disconnect {p_name_1 p_name_2} {
 
   set m_name_1 [ad_connect_type $p_name_1]

From 751a66eb724b6c0b88fb1d6539039296df06c503 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 26 Sep 2016 15:20:37 -0400
Subject: [PATCH 532/972] plddr3/zc706- board pin warning

---
 projects/common/zc706/zc706_system_plddr3_adcfifo.tcl | 2 --
 1 file changed, 2 deletions(-)

diff --git a/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
index d71ee94f6..4460b7d72 100644
--- a/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
@@ -37,8 +37,6 @@ proc p_plddr3_adcfifo {p_name m_name adc_data_width} {
   set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
 
   set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
-  set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
-  set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
 
   set axi_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_adcfifo:1.0 axi_adcfifo]
   set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_adcfifo

From 692cb10fb234bf5a24ea4034c9c967c721899a1f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 26 Sep 2016 15:21:11 -0400
Subject: [PATCH 533/972] ad9625- xcvr updates

---
 library/axi_ad9625/axi_ad9625.v      | 18 ++++++++++---
 library/axi_ad9625/axi_ad9625_if.v   | 40 ++++++++++++++++++++--------
 library/axi_ad9625/axi_ad9625_ip.tcl |  2 ++
 3 files changed, 46 insertions(+), 14 deletions(-)

diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v
index bd23692d6..59bdaa00b 100644
--- a/library/axi_ad9625/axi_ad9625.v
+++ b/library/axi_ad9625/axi_ad9625.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -45,7 +43,10 @@ module axi_ad9625 (
   // rx_clk is (line-rate/40)
 
   rx_clk,
+  rx_sof,
+  rx_valid,
   rx_data,
+  rx_ready,
 
   // dma interface
 
@@ -92,7 +93,10 @@ module axi_ad9625 (
   // rx_clk is (line-rate/40)
 
   input           rx_clk;
+  input   [  3:0] rx_sof;
+  input           rx_valid;
   input   [255:0] rx_data;
+  output          rx_ready;
 
   // dma interface
 
@@ -166,6 +170,10 @@ module axi_ad9625 (
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
 
+  // defaults
+
+  assign rx_ready = 1'b1;
+
   // processor read interface
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -184,8 +192,12 @@ module axi_ad9625 (
 
   assign adc_valid = 1'b1;
 
-  axi_ad9625_if #(.ID(ID)) i_if (
+  axi_ad9625_if #(
+    .ID (ID),
+    .DEVICE_TYPE (DEVICE_TYPE))
+  i_if (
     .rx_clk (rx_clk),
+    .rx_sof (rx_sof),
     .rx_data (rx_data),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
diff --git a/library/axi_ad9625/axi_ad9625_if.v b/library/axi_ad9625/axi_ad9625_if.v
index 51d2827ac..2e0f78f18 100644
--- a/library/axi_ad9625/axi_ad9625_if.v
+++ b/library/axi_ad9625/axi_ad9625_if.v
@@ -34,9 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// This is the LVDS/DDR interface
 
 `timescale 1ns/100ps
 
@@ -46,6 +43,7 @@ module axi_ad9625_if (
   // rx_clk is (line-rate/40)
 
   rx_clk,
+  rx_sof,
   rx_data,
 
   // adc data output
@@ -59,12 +57,16 @@ module axi_ad9625_if (
   adc_raddr_in,
   adc_raddr_out);
 
+  // parameters
+
   parameter   ID = 0;
+  parameter   DEVICE_TYPE = 0;
 
   // jesd interface 
   // rx_clk is ref_clk/4
 
   input           rx_clk;
+  input   [  3:0] rx_sof;
   input   [255:0] rx_data;
 
   // adc data output
@@ -119,6 +121,7 @@ module axi_ad9625_if (
   wire    [ 31:0] rx_data5_s;
   wire    [ 31:0] rx_data6_s;
   wire    [ 31:0] rx_data7_s;
+  wire    [255:0] rx_data_s;
 
   // nothing much to do on clock & over-range
 
@@ -198,14 +201,14 @@ module axi_ad9625_if (
   assign adc_data_s01_s = {rx_data3_s[ 3: 0], rx_data2_s[ 7: 0], rx_data3_s[ 7: 4]};
   assign adc_data_s00_s = {rx_data1_s[ 3: 0], rx_data0_s[ 7: 0], rx_data1_s[ 7: 4]};
 
-  assign rx_data0_s = rx_data[ 31:  0];
-  assign rx_data1_s = rx_data[ 63: 32];
-  assign rx_data2_s = rx_data[ 95: 64];
-  assign rx_data3_s = rx_data[127: 96];
-  assign rx_data4_s = rx_data[159:128];
-  assign rx_data5_s = rx_data[191:160];
-  assign rx_data6_s = rx_data[223:192];
-  assign rx_data7_s = rx_data[255:224];
+  assign rx_data0_s = rx_data_s[ 31:  0];
+  assign rx_data1_s = rx_data_s[ 63: 32];
+  assign rx_data2_s = rx_data_s[ 95: 64];
+  assign rx_data3_s = rx_data_s[127: 96];
+  assign rx_data4_s = rx_data_s[159:128];
+  assign rx_data5_s = rx_data_s[191:160];
+  assign rx_data6_s = rx_data_s[223:192];
+  assign rx_data7_s = rx_data_s[255:224];
 
   // status
 
@@ -228,6 +231,21 @@ module axi_ad9625_if (
     .addrb (adc_raddr_s),
     .doutb (adc_rdata_s));
 
+  // frame-alignment
+
+  genvar n;
+
+  generate
+  for (n = 0; n < 8; n = n + 1) begin: g_xcvr_if
+  ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
+    .rx_clk (rx_clk),
+    .rx_ip_sof (rx_sof),
+    .rx_ip_data (rx_data[((n*32)+31):(n*32)]),
+    .rx_sof (),
+    .rx_data (rx_data_s[((n*32)+31):(n*32)]));
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/axi_ad9625/axi_ad9625_ip.tcl b/library/axi_ad9625/axi_ad9625_ip.tcl
index c046b62ba..5500260f1 100644
--- a/library/axi_ad9625/axi_ad9625_ip.tcl
+++ b/library/axi_ad9625/axi_ad9625_ip.tcl
@@ -16,6 +16,7 @@ adi_ip_files axi_ad9625 [list \
   "$ad_hdl_dir/library/common/up_adc_common.v" \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
   "axi_ad9625_pnmon.v" \
   "axi_ad9625_channel.v" \
   "axi_ad9625_if.v" \
@@ -31,6 +32,7 @@ adi_ip_constraints axi_ad9625 [list \
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]
 

From c98e2e95dda498dc44a5c9627819ad414be7d224 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 26 Sep 2016 15:21:45 -0400
Subject: [PATCH 534/972] ad9162- xcvr updates

---
 library/axi_ad9162/axi_ad9162.v      | 15 ++++--
 library/axi_ad9162/axi_ad9162_if.v   | 68 +++++++++++++++-------------
 library/axi_ad9162/axi_ad9162_ip.tcl |  1 +
 3 files changed, 48 insertions(+), 36 deletions(-)

diff --git a/library/axi_ad9162/axi_ad9162.v b/library/axi_ad9162/axi_ad9162.v
index 6fff5f0c7..0912cbc2d 100644
--- a/library/axi_ad9162/axi_ad9162.v
+++ b/library/axi_ad9162/axi_ad9162.v
@@ -43,7 +43,9 @@ module axi_ad9162 (
     // tx_clk is (line-rate/40)
     
     tx_clk,
+    tx_valid,
     tx_data,
+    tx_ready,
     
     // dma interface
     
@@ -81,13 +83,16 @@ module axi_ad9162 (
     // parameters
     
     parameter   ID = 0;
+    parameter   DEVICE_TYPE = 0;
     parameter   DAC_DATAPATH_DISABLE = 0;
     
     // jesd interface
     // tx_clk is (line-rate/40)
     
     input             tx_clk;
+    output            tx_valid;
     output  [255:0]   tx_data;
+    input             tx_ready;
     
     // dma interface
     
@@ -130,7 +135,6 @@ module axi_ad9162 (
     
     // internal signals
     
-    wire    [255:0]   tx_data_s;
     wire    [255:0]   dac_data_s;
     wire              up_wreq_s;
     wire    [ 13:0]   up_waddr_s;
@@ -145,13 +149,16 @@ module axi_ad9162 (
     
     assign up_clk = s_axi_aclk;
     assign up_rstn = s_axi_aresetn;
-    assign tx_data = tx_data_s;
+
+    // defaults
+
+    assign tx_valid = 1'b1;
     
     // device interface
     
-    axi_ad9162_if i_if (
+    axi_ad9162_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
       .tx_clk (tx_clk),
-      .tx_data (tx_data_s),
+      .tx_data (tx_data),
       .dac_clk (dac_clk),
       .dac_rst (dac_rst),
       .dac_data (dac_data_s));
diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v
index c1d9cb2a3..59362b429 100644
--- a/library/axi_ad9162/axi_ad9162_if.v
+++ b/library/axi_ad9162/axi_ad9162_if.v
@@ -51,6 +51,10 @@ module axi_ad9162_if (
     dac_rst,
     dac_data);
     
+    // altera (0x1) or xilinx (0x0)
+
+    parameter DEVICE_TYPE = 0;
+
     // jesd interface
     // tx_clk is (line-rate/40)
     
@@ -72,38 +76,38 @@ module axi_ad9162_if (
     assign dac_clk = tx_clk;
 
     always @(posedge tx_clk) begin
-      tx_data[255:248] <= dac_data[247:240];
-      tx_data[247:240] <= dac_data[183:176];
-      tx_data[239:232] <= dac_data[119:112];
-      tx_data[231:224] <= dac_data[ 55: 48];
-      tx_data[223:216] <= dac_data[255:248];
-      tx_data[215:208] <= dac_data[191:184];
-      tx_data[207:200] <= dac_data[127:120];
-      tx_data[199:192] <= dac_data[ 63: 56];
-      tx_data[191:184] <= dac_data[215:208];
-      tx_data[183:176] <= dac_data[151:144];
-      tx_data[175:168] <= dac_data[ 87: 80];
-      tx_data[167:160] <= dac_data[ 23: 16];
-      tx_data[159:152] <= dac_data[223:216];
-      tx_data[151:144] <= dac_data[159:152];
-      tx_data[143:136] <= dac_data[ 95: 88];
-      tx_data[135:128] <= dac_data[ 31: 24];
-      tx_data[127:120] <= dac_data[231:224];
-      tx_data[119:112] <= dac_data[167:160];
-      tx_data[111:104] <= dac_data[103: 96];
-      tx_data[103: 96] <= dac_data[ 39: 32];
-      tx_data[ 95: 88] <= dac_data[239:232];
-      tx_data[ 87: 80] <= dac_data[175:168];
-      tx_data[ 79: 72] <= dac_data[111:104];
-      tx_data[ 71: 64] <= dac_data[ 47: 40];
-      tx_data[ 63: 56] <= dac_data[199:192];
-      tx_data[ 55: 48] <= dac_data[135:128];
-      tx_data[ 47: 40] <= dac_data[ 71: 64];
-      tx_data[ 39: 32] <= dac_data[  7:  0];
-      tx_data[ 31: 24] <= dac_data[207:200];
-      tx_data[ 23: 16] <= dac_data[143:136];
-      tx_data[ 15:  8] <= dac_data[ 79: 72];
-      tx_data[  7:  0] <= dac_data[ 15:  8];
+      tx_data[255:248] <= (DEVICE_TYPE == 1) ? dac_data[ 55: 48] : dac_data[247:240];
+      tx_data[247:240] <= (DEVICE_TYPE == 1) ? dac_data[119:112] : dac_data[183:176];
+      tx_data[239:232] <= (DEVICE_TYPE == 1) ? dac_data[183:176] : dac_data[119:112];
+      tx_data[231:224] <= (DEVICE_TYPE == 1) ? dac_data[247:240] : dac_data[ 55: 48];
+      tx_data[223:216] <= (DEVICE_TYPE == 1) ? dac_data[ 63: 56] : dac_data[255:248];
+      tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data[127:120] : dac_data[191:184];
+      tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data[191:184] : dac_data[127:120];
+      tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data[255:248] : dac_data[ 63: 56];
+      tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data[ 23: 16] : dac_data[215:208];
+      tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data[ 87: 80] : dac_data[151:144];
+      tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data[151:144] : dac_data[ 87: 80];
+      tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data[215:208] : dac_data[ 23: 16];
+      tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data[ 31: 24] : dac_data[223:216];
+      tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data[ 95: 88] : dac_data[159:152];
+      tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data[159:152] : dac_data[ 95: 88];
+      tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data[223:216] : dac_data[ 31: 24];
+      tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data[ 39: 32] : dac_data[231:224];
+      tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data[103: 96] : dac_data[167:160];
+      tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data[167:160] : dac_data[103: 96];
+      tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data[231:224] : dac_data[ 39: 32];
+      tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data[ 47: 40] : dac_data[239:232];
+      tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data[111:104] : dac_data[175:168];
+      tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data[175:168] : dac_data[111:104];
+      tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data[239:232] : dac_data[ 47: 40];
+      tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data[  7:  0] : dac_data[199:192];
+      tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data[ 71: 64] : dac_data[135:128];
+      tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data[135:128] : dac_data[ 71: 64];
+      tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data[199:192] : dac_data[  7:  0];
+      tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data[ 15:  8] : dac_data[207:200];
+      tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data[ 79: 72] : dac_data[143:136];
+      tx_data[ 15:  8] <= (DEVICE_TYPE == 1) ? dac_data[143:136] : dac_data[ 79: 72];
+      tx_data[  7:  0] <= (DEVICE_TYPE == 1) ? dac_data[207:200] : dac_data[ 15:  8];
     end
    
 endmodule
diff --git a/library/axi_ad9162/axi_ad9162_ip.tcl b/library/axi_ad9162/axi_ad9162_ip.tcl
index 07312eb24..2439aebe4 100644
--- a/library/axi_ad9162/axi_ad9162_ip.tcl
+++ b/library/axi_ad9162/axi_ad9162_ip.tcl
@@ -29,6 +29,7 @@ adi_ip_constraints axi_ad9162 [list \
 
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]
 

From 9defccef7014b90afb6192eeaff74603f18ca7e6 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 27 Sep 2016 14:48:23 -0400
Subject: [PATCH 535/972] dacfifo- axi address map fixes

---
 library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl | 61 ++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
index 67a819ed8..be08c967a 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
@@ -19,7 +19,66 @@ adi_ip_properties_lite axi_dacfifo
 adi_ip_constraints axi_dacfifo [list \
   "axi_dacfifo_constr.xdc" ]
 
-ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]
+ipx::infer_bus_interface {\
+  axi_awvalid \
+  axi_awid \
+  axi_awburst \
+  axi_awlock \
+  axi_awcache \
+  axi_awprot \
+  axi_awqos \
+  axi_awuser \
+  axi_awlen \
+  axi_awsize \
+  axi_awaddr \
+  axi_awready \
+  axi_wvalid \
+  axi_wdata \
+  axi_wstrb \
+  axi_wlast \
+  axi_wuser \
+  axi_wready \
+  axi_bvalid \
+  axi_bid \
+  axi_bresp \
+  axi_buser \
+  axi_bready \
+  axi_arvalid \
+  axi_arid \
+  axi_arburst \
+  axi_arlock \
+  axi_arcache \
+  axi_arprot \
+  axi_arqos \
+  axi_aruser \
+  axi_arlen \
+  axi_arsize \
+  axi_araddr \
+  axi_arready \
+  axi_rvalid \
+  axi_rid \
+  axi_ruser \
+  axi_rresp \
+  axi_rlast \
+  axi_rdata \
+  axi_rready} \
+xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
+  -of_objects [ipx::current_core]]
+set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
+  -of_objects [ipx::get_bus_interfaces axi_clk \
+  -of_objects [ipx::current_core]]]
+
+ipx::add_address_space axi [ipx::current_core]
+set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
+  -of_objects [ipx::current_core]]
+set_property range 4294967296 [ipx::get_address_spaces axi \
+  -of_objects [ipx::current_core]]
+set_property width 512 [ipx::get_address_spaces axi \
+  -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]
 

From 4239f6412502ba54897f0d5cbcb78e1685f91844 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 27 Sep 2016 14:49:20 -0400
Subject: [PATCH 536/972] dacfifo- board pin warnings

---
 projects/common/zc706/zc706_system_plddr3_dacfifo.tcl | 2 --
 1 file changed, 2 deletions(-)

diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index c59030039..13cc3cb3f 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -41,8 +41,6 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
 
   set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
-  set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
-  set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
 
   set axi_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_dacfifo:1.0 axi_dacfifo]
   set_property -dict [list CONFIG.DAC_DATA_WIDTH $dac_data_width] $axi_dacfifo

From df485d787878acdf3cad9d58db0ba71af9299b81 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 27 Sep 2016 14:45:34 +0300
Subject: [PATCH 537/972] axi_ad9684: Fix the PN9 PRBS sequence monitor

---
 library/axi_ad9684/axi_ad9684_pnmon.v | 68 +++++++++++++++------------
 1 file changed, 37 insertions(+), 31 deletions(-)

diff --git a/library/axi_ad9684/axi_ad9684_pnmon.v b/library/axi_ad9684/axi_ad9684_pnmon.v
index 2936c2cb4..e57102e9d 100644
--- a/library/axi_ad9684/axi_ad9684_pnmon.v
+++ b/library/axi_ad9684/axi_ad9684_pnmon.v
@@ -78,6 +78,7 @@ module axi_ad9684_pnmon (
   // internal signals
 
   wire    [27:0]  adc_pn_data_pn_s;
+  wire    [31:0]  adc_pn_data_pn9_s;
 
   // PN23 function
 
@@ -119,38 +120,42 @@ module axi_ad9684_pnmon (
 
   // PN9 function
 
-  function [27:0] pn9;
+  function [31:0] pn9;
     input [27:0] din;
-    reg   [27:0] dout;
+    reg   [31:0] dout;
     begin
-      dout[27] = din[ 8] ^ din[ 4];
-      dout[26] = din[ 7] ^ din[ 3];
-      dout[25] = din[ 6] ^ din[ 2];
-      dout[24] = din[ 5] ^ din[ 1];
-      dout[23] = din[ 4] ^ din[ 0];
-      dout[22] = din[ 3] ^ din[ 8] ^ din[ 4];
-      dout[21] = din[ 2] ^ din[ 7] ^ din[ 3];
-      dout[20] = din[ 1] ^ din[ 6] ^ din[ 2];
-      dout[19] = din[ 0] ^ din[ 5] ^ din[ 1];
-      dout[18] = din[ 8] ^ din[ 0];
-      dout[17] = din[ 7] ^ din[ 8] ^ din[ 4];
-      dout[16] = din[ 6] ^ din[ 7] ^ din[ 3];
-      dout[15] = din[ 5] ^ din[ 6] ^ din[ 2];
-      dout[14] = din[ 4] ^ din[ 5] ^ din[ 1];
-      dout[13] = din[ 3] ^ din[ 4] ^ din[ 0];
-      dout[12] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
-      dout[11] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
-      dout[10] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
-      dout[ 9] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
-      dout[ 8] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
-      dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
-      dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
-      dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
-      dout[ 4] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
-      dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
-      dout[ 2] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
-      dout[ 1] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
-      dout[ 0] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
+      dout[31] = din[ 8] ^ din[ 4];
+      dout[30] = din[ 7] ^ din[ 3];
+      dout[29] = din[ 6] ^ din[ 2];
+      dout[28] = din[ 5] ^ din[ 1];
+      dout[27] = din[ 4] ^ din[ 0];
+      dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
+      dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
+      dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
+      dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
+      dout[22] = din[ 8] ^ din[ 0];
+      dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
+      dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
+      dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
+      dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
+      dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
+      dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
+      dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
+      dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
+      dout[13] = din[ 8] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 4];
+      dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
+      dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
+      dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
+      dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
+      dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
+      dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
+      dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
+      dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
+      dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
+      dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
+      dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
+      dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
+      dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
       pn9 = dout;
     end
   endfunction
@@ -158,12 +163,13 @@ module axi_ad9684_pnmon (
   // pn sequence select
 
   assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
+  assign adc_pn_data_pn9_s = pn9(adc_pn_data_pn_s);
 
   always @(posedge adc_clk) begin
     adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0],
                         ~adc_data[27], adc_data[26:14]};
     if (adc_pnseq_sel == 4'd0) begin
-      adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
+      adc_pn_data_pn <= {adc_pn_data_pn9_s[29:16], adc_pn_data_pn9_s[13:0]};
     end else begin
       adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
     end

From f7fb3ccaca9178a0b4dac8a8392c5e42317f53b4 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 28 Sep 2016 16:36:13 +0300
Subject: [PATCH 538/972] axi_ad9361: Change the data path gating

Bring up the datapath gating from the TDD controller module.
---
 library/axi_ad9361/axi_ad9361.v     | 60 ++++++----------------
 library/axi_ad9361/axi_ad9361_tdd.v | 79 ++++-------------------------
 2 files changed, 25 insertions(+), 114 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 73c378e98..581333990 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -300,10 +300,6 @@ module axi_ad9361 (
   reg             up_wack = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
-  reg     [15:0]  adc_data_i0_b = 16'b0;
-  reg     [15:0]  adc_data_q0_b = 16'b0;
-  reg     [15:0]  adc_data_i1_b = 16'b0;
-  reg     [15:0]  adc_data_q1_b = 16'b0;
 
   // internal clocks and resets
 
@@ -503,20 +499,6 @@ module axi_ad9361 (
     wire            tdd_tx_rf_en_s;
     wire    [ 7:0]  tdd_status_s;
 
-    // additional flop to keep control and data synced
-
-    assign adc_data_i0 = adc_data_i0_b;
-    assign adc_data_q0 = adc_data_q0_b;
-    assign adc_data_i1 = adc_data_i1_b;
-    assign adc_data_q1 = adc_data_q1_b;
-
-    always @(posedge clk) begin
-      adc_data_i0_b <= adc_data_i0_s;
-      adc_data_q0_b <= adc_data_q0_s;
-      adc_data_i1_b <= adc_data_i1_s;
-      adc_data_q1_b <= adc_data_q1_s;
-    end
-
     axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
       .clk (clk),
       .rst (rst),
@@ -528,6 +510,16 @@ module axi_ad9361 (
       .ad9361_enable (tdd_enable_s),
       .ad9361_tdd_status (tdd_status_s));
 
+    assign g_dac_valid_s = dac_valid_s;
+    assign dac_valid_i0  = tdd_tx_valid_s & dac_valid_i0_s;
+    assign dac_valid_q0  = tdd_tx_valid_s & dac_valid_q0_s;
+    assign dac_valid_i1  = tdd_tx_valid_s & dac_valid_i1_s;
+    assign dac_valid_q1  = tdd_tx_valid_s & dac_valid_q1_s;
+    assign adc_valid_i0  = tdd_rx_valid_s & adc_valid_i0_s;
+    assign adc_valid_q0  = tdd_rx_valid_s & adc_valid_q0_s;
+    assign adc_valid_i1  = tdd_rx_valid_s & adc_valid_i1_s;
+    assign adc_valid_q1  = tdd_rx_valid_s & adc_valid_q1_s;
+
     // TDD control
 
     axi_ad9361_tdd i_tdd (
@@ -541,24 +533,8 @@ module axi_ad9361 (
       .tdd_status (tdd_status_s),
       .tdd_sync (tdd_sync),
       .tdd_sync_cntr (tdd_sync_cntr),
-      .tx_valid (dac_valid_s),
-      .tx_valid_i0 (dac_valid_i0_s),
-      .tx_valid_q0 (dac_valid_q0_s),
-      .tx_valid_i1 (dac_valid_i1_s),
-      .tx_valid_q1 (dac_valid_q1_s),
-      .tdd_tx_valid (g_dac_valid_s),
-      .tdd_tx_valid_i0 (dac_valid_i0),
-      .tdd_tx_valid_q0 (dac_valid_q0),
-      .tdd_tx_valid_i1 (dac_valid_i1),
-      .tdd_tx_valid_q1 (dac_valid_q1),
-      .rx_valid_i0 (adc_valid_i0_s),
-      .rx_valid_q0 (adc_valid_q0_s),
-      .rx_valid_i1 (adc_valid_i1_s),
-      .rx_valid_q1 (adc_valid_q1_s),
-      .tdd_rx_valid_i0 (adc_valid_i0),
-      .tdd_rx_valid_q0 (adc_valid_q0),
-      .tdd_rx_valid_i1 (adc_valid_i1),
-      .tdd_rx_valid_q1 (adc_valid_q1),
+      .tdd_tx_valid (tdd_tx_valid_s),
+      .tdd_rx_valid (tdd_rx_valid_s),
       .up_rstn (up_rstn),
       .up_clk (up_clk),
       .up_wreq (up_wreq_s),
@@ -577,10 +553,6 @@ module axi_ad9361 (
     assign tdd_mode_s     = 1'b0;
     assign tdd_enable_s   = 1'b0;
     assign tdd_txnrx_s    = 1'b0;
-    assign adc_data_i0    = adc_data_i0_s;
-    assign adc_data_q0    = adc_data_q0_s;
-    assign adc_data_i1    = adc_data_i1_s;
-    assign adc_data_q1    = adc_data_q1_s;
     assign tdd_sync_cntr  = 1'b0;
     assign g_dac_valid_s  = dac_valid_s;
     assign dac_valid_i0   = dac_valid_i0_s;
@@ -625,16 +597,16 @@ module axi_ad9361 (
     .delay_locked (delay_locked_s),
     .adc_enable_i0 (adc_enable_i0),
     .adc_valid_i0 (adc_valid_i0_s),
-    .adc_data_i0 (adc_data_i0_s),
+    .adc_data_i0 (adc_data_i0),
     .adc_enable_q0 (adc_enable_q0),
     .adc_valid_q0 (adc_valid_q0_s),
-    .adc_data_q0 (adc_data_q0_s),
+    .adc_data_q0 (adc_data_q0),
     .adc_enable_i1 (adc_enable_i1),
     .adc_valid_i1 (adc_valid_i1_s),
-    .adc_data_i1 (adc_data_i1_s),
+    .adc_data_i1 (adc_data_i1),
     .adc_enable_q1 (adc_enable_q1),
     .adc_valid_q1 (adc_valid_q1_s),
-    .adc_data_q1 (adc_data_q1_s),
+    .adc_data_q1 (adc_data_q1),
     .adc_dovf (adc_dovf),
     .adc_dunf (adc_dunf),
     .up_adc_gpio_in (up_adc_gpio_in),
diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index 84b17d2a9..273129d3d 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -65,27 +65,8 @@ module axi_ad9361_tdd (
 
   // tx/rx data flow control
 
-  tx_valid,
-  tx_valid_i0,
-  tx_valid_q0,
-  tx_valid_i1,
-  tx_valid_q1,
-
   tdd_tx_valid,
-  tdd_tx_valid_i0,
-  tdd_tx_valid_q0,
-  tdd_tx_valid_i1,
-  tdd_tx_valid_q1,
-
-  rx_valid_i0,
-  rx_valid_q0,
-  rx_valid_i1,
-  rx_valid_q1,
-
-  tdd_rx_valid_i0,
-  tdd_rx_valid_q0,
-  tdd_rx_valid_i1,
-  tdd_rx_valid_q1,
+  tdd_rx_valid,
 
   // bus interface
 
@@ -116,31 +97,10 @@ module axi_ad9361_tdd (
   input             tdd_sync;
   output            tdd_sync_cntr;
 
-  // tx data flow control
-
-  input             tx_valid;
-  input             tx_valid_i0;
-  input             tx_valid_q0;
-  input             tx_valid_i1;
-  input             tx_valid_q1;
+  // data flow control
 
   output            tdd_tx_valid;
-  output            tdd_tx_valid_i0;
-  output            tdd_tx_valid_q0;
-  output            tdd_tx_valid_i1;
-  output            tdd_tx_valid_q1;
-
-  // rx data flow control
-
-  input             rx_valid_i0;
-  input             rx_valid_q0;
-  input             rx_valid_i1;
-  input             rx_valid_q1;
-
-  output            tdd_rx_valid_i0;
-  output            tdd_rx_valid_q0;
-  output            tdd_rx_valid_i1;
-  output            tdd_rx_valid_q1;
+  output            tdd_rx_valid;
 
   // bus interface
 
@@ -157,15 +117,8 @@ module axi_ad9361_tdd (
 
   reg               tdd_slave_synced = 1'b0;
 
-  reg               tdd_tx_valid    = 1'b0;
-  reg               tdd_tx_valid_i0 = 1'b0;
-  reg               tdd_tx_valid_q0 = 1'b0;
-  reg               tdd_tx_valid_i1 = 1'b0;
-  reg               tdd_tx_valid_q1 = 1'b0;
-  reg               tdd_rx_valid_i0 = 1'b0;
-  reg               tdd_rx_valid_q0 = 1'b0;
-  reg               tdd_rx_valid_i1 = 1'b0;
-  reg               tdd_rx_valid_q1 = 1'b0;
+  reg               tdd_tx_valid = 1'b0;
+  reg               tdd_rx_valid = 1'b0;
 
   // internal signals
 
@@ -218,31 +171,17 @@ module axi_ad9361_tdd (
 
   always @(posedge clk) begin
     if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
-      tdd_tx_valid    <= tx_valid & tdd_tx_dp_en_s;
-      tdd_tx_valid_i0 <= tx_valid_i0 & tdd_tx_dp_en_s;
-      tdd_tx_valid_q0 <= tx_valid_q0 & tdd_tx_dp_en_s;
-      tdd_tx_valid_i1 <= tx_valid_i1 & tdd_tx_dp_en_s;
-      tdd_tx_valid_q1 <= tx_valid_q1 & tdd_tx_dp_en_s;
+      tdd_tx_valid <= tdd_tx_dp_en_s;
     end else begin
-      tdd_tx_valid    <= tx_valid;
-      tdd_tx_valid_i0 <= tx_valid_i0;
-      tdd_tx_valid_q0 <= tx_valid_q0;
-      tdd_tx_valid_i1 <= tx_valid_i1;
-      tdd_tx_valid_q1 <= tx_valid_q1;
+      tdd_tx_valid <= 1'b1;
     end
   end
 
   always @(posedge clk) begin
     if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
-      tdd_rx_valid_i0 <= rx_valid_i0 & tdd_rx_dp_en_s;
-      tdd_rx_valid_q0 <= rx_valid_q0 & tdd_rx_dp_en_s;
-      tdd_rx_valid_i1 <= rx_valid_i1 & tdd_rx_dp_en_s;
-      tdd_rx_valid_q1 <= rx_valid_q1 & tdd_rx_dp_en_s;
+      tdd_rx_valid <= tdd_rx_dp_en_s;
     end else begin
-      tdd_rx_valid_i0 <= rx_valid_i0;
-      tdd_rx_valid_q0 <= rx_valid_q0;
-      tdd_rx_valid_i1 <= rx_valid_i1;
-      tdd_rx_valid_q1 <= rx_valid_q1;
+      tdd_rx_valid <= 1'b1;
     end
   end
 

From b4fac96aad95b03f5183037fa5375c70c7e7ef24 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 28 Sep 2016 15:45:27 -0400
Subject: [PATCH 539/972] axi_ad9361- independent disables

---
 library/axi_ad9361/axi_ad9361.v | 505 +++++++++++++-------------------
 1 file changed, 196 insertions(+), 309 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 581333990..d24226da7 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -37,263 +37,159 @@
 
 `timescale 1ns/100ps
 
-module axi_ad9361 (
-
-  // physical interface (receive-lvds)
-
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-
-  // physical interface (receive-cmos)
-
-  rx_clk_in,
-  rx_frame_in,
-  rx_data_in,
-
-  // physical interface (transmit-lvds)
-
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
-
-  // physical interface (transmit-cmos)
-
-  tx_clk_out,
-  tx_frame_out,
-  tx_data_out,
-
-  // ensm control
-
-  enable,
-  txnrx,
-
-  // transmit master/slave
-
-  dac_sync_in,
-  dac_sync_out,
-
-  // tdd sync (1s pulse)
-
-  tdd_sync,
-  tdd_sync_cntr,
-
-  // delay clock
-
-  delay_clk,
-
-  // master interface
-
-  l_clk,
-  clk,
-  rst,
-
-  // dma interface
-
-  adc_enable_i0,
-  adc_valid_i0,
-  adc_data_i0,
-  adc_enable_q0,
-  adc_valid_q0,
-  adc_data_q0,
-  adc_enable_i1,
-  adc_valid_i1,
-  adc_data_i1,
-  adc_enable_q1,
-  adc_valid_q1,
-  adc_data_q1,
-  adc_dovf,
-  adc_dunf,
-  adc_r1_mode,
-
-  dac_enable_i0,
-  dac_valid_i0,
-  dac_data_i0,
-  dac_enable_q0,
-  dac_valid_q0,
-  dac_data_q0,
-  dac_enable_i1,
-  dac_valid_i1,
-  dac_data_i1,
-  dac_enable_q1,
-  dac_valid_q1,
-  dac_data_q1,
-  dac_dovf,
-  dac_dunf,
-  dac_r1_mode,
-
-  // axi interface
-
-  s_axi_aclk,
-  s_axi_aresetn,
-  s_axi_awvalid,
-  s_axi_awaddr,
-  s_axi_awprot,
-  s_axi_awready,
-  s_axi_wvalid,
-  s_axi_wdata,
-  s_axi_wstrb,
-  s_axi_wready,
-  s_axi_bvalid,
-  s_axi_bresp,
-  s_axi_bready,
-  s_axi_arvalid,
-  s_axi_araddr,
-  s_axi_arprot,
-  s_axi_arready,
-  s_axi_rvalid,
-  s_axi_rdata,
-  s_axi_rresp,
-  s_axi_rready,
-
-  // gpio
-
-  up_enable,
-  up_txnrx,
-  up_dac_gpio_in,
-  up_dac_gpio_out,
-  up_adc_gpio_in,
-  up_adc_gpio_out);
+module axi_ad9361 #(
 
   // parameters
 
-  parameter   ID = 0;
-  parameter   DEVICE_TYPE = 0;
-  parameter   CMOS_OR_LVDS_N = 0;
-  parameter   DAC_IODELAY_ENABLE = 0;
-  parameter   IO_DELAY_GROUP = "dev_if_delay_group";
-  parameter   DAC_DATAPATH_DISABLE = 0;
-  parameter   ADC_DATAPATH_DISABLE = 0;
-  parameter   TDD_CONTROL_EN = 0;
-  parameter   R1_MODE_EN = 0;
+  parameter   ID = 0,
+  parameter   MODE_1R1T = 0,
+  parameter   DEVICE_TYPE = 0,
+  parameter   TDD_DISABLE = 0,
+  parameter   CMOS_OR_LVDS_N = 0,
+  parameter   ADC_DATAPATH_DISABLE = 0,
+  parameter   ADC_USERPORTS_DISABLE = 0,
+  parameter   ADC_DATAFORMAT_DISABLE = 0,
+  parameter   ADC_DCFILTER_DISABLE = 0,
+  parameter   ADC_IQCORRECTION_DISABLE = 0,
+  parameter   DAC_IODELAY_ENABLE = 0,
+  parameter   DAC_DATAPATH_DISABLE = 0,
+  parameter   DAC_DDS_DISABLE = 0,
+  parameter   DAC_USERPORTS_DISABLE = 0,
+  parameter   DAC_IQCORRECTION_DISABLE = 0,
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group") (
 
   // physical interface (receive-lvds)
 
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
 
   // physical interface (receive-cmos)
 
-  input           rx_clk_in;
-  input           rx_frame_in;
-  input   [11:0]  rx_data_in;
+  input           rx_clk_in,
+  input           rx_frame_in,
+  input   [11:0]  rx_data_in,
 
   // physical interface (transmit-lvds)
 
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
 
   // physical interface (transmit-cmos)
 
-  output          tx_clk_out;
-  output          tx_frame_out;
-  output  [11:0]  tx_data_out;
+  output          tx_clk_out,
+  output          tx_frame_out,
+  output  [11:0]  tx_data_out,
 
   // ensm control
 
-  output          enable;
-  output          txnrx;
+  output          enable,
+  output          txnrx,
 
   // transmit master/slave
 
-  input           dac_sync_in;
-  output          dac_sync_out;
+  input           dac_sync_in,
+  output          dac_sync_out,
 
   // tdd sync
 
-  input           tdd_sync;
-  output          tdd_sync_cntr;
+  input           tdd_sync,
+  output          tdd_sync_cntr,
 
   // delay clock
 
-  input           delay_clk;
+  input           delay_clk,
 
   // master interface
 
-  output          l_clk;
-  input           clk;
-  output          rst;
+  output          l_clk,
+  input           clk,
+  output          rst,
 
   // dma interface
 
-  output          adc_enable_i0;
-  output          adc_valid_i0;
-  output  [15:0]  adc_data_i0;
-  output          adc_enable_q0;
-  output          adc_valid_q0;
-  output  [15:0]  adc_data_q0;
-  output          adc_enable_i1;
-  output          adc_valid_i1;
-  output  [15:0]  adc_data_i1;
-  output          adc_enable_q1;
-  output          adc_valid_q1;
-  output  [15:0]  adc_data_q1;
-  input           adc_dovf;
-  input           adc_dunf;
-  output          adc_r1_mode;
+  output          adc_enable_i0,
+  output          adc_valid_i0,
+  output  [15:0]  adc_data_i0,
+  output          adc_enable_q0,
+  output          adc_valid_q0,
+  output  [15:0]  adc_data_q0,
+  output          adc_enable_i1,
+  output          adc_valid_i1,
+  output  [15:0]  adc_data_i1,
+  output          adc_enable_q1,
+  output          adc_valid_q1,
+  output  [15:0]  adc_data_q1,
+  input           adc_dovf,
+  input           adc_dunf,
+  output          adc_r1_mode,
 
-  output          dac_enable_i0;
-  output          dac_valid_i0;
-  input   [15:0]  dac_data_i0;
-  output          dac_enable_q0;
-  output          dac_valid_q0;
-  input   [15:0]  dac_data_q0;
-  output          dac_enable_i1;
-  output          dac_valid_i1;
-  input   [15:0]  dac_data_i1;
-  output          dac_enable_q1;
-  output          dac_valid_q1;
-  input   [15:0]  dac_data_q1;
-  input           dac_dovf;
-  input           dac_dunf;
-  output          dac_r1_mode;
+  output          dac_enable_i0,
+  output          dac_valid_i0,
+  input   [15:0]  dac_data_i0,
+  output          dac_enable_q0,
+  output          dac_valid_q0,
+  input   [15:0]  dac_data_q0,
+  output          dac_enable_i1,
+  output          dac_valid_i1,
+  input   [15:0]  dac_data_i1,
+  output          dac_enable_q1,
+  output          dac_valid_q1,
+  input   [15:0]  dac_data_q1,
+  input           dac_dovf,
+  input           dac_dunf,
+  output          dac_r1_mode,
 
   // axi interface
 
-  input           s_axi_aclk;
-  input           s_axi_aresetn;
-  input           s_axi_awvalid;
-  input   [31:0]  s_axi_awaddr;
-  input   [ 2:0]  s_axi_awprot;
-  output          s_axi_awready;
-  input           s_axi_wvalid;
-  input   [31:0]  s_axi_wdata;
-  input   [ 3:0]  s_axi_wstrb;
-  output          s_axi_wready;
-  output          s_axi_bvalid;
-  output  [ 1:0]  s_axi_bresp;
-  input           s_axi_bready;
-  input           s_axi_arvalid;
-  input   [31:0]  s_axi_araddr;
-  input   [ 2:0]  s_axi_arprot;
-  output          s_axi_arready;
-  output          s_axi_rvalid;
-  output  [31:0]  s_axi_rdata;
-  output  [ 1:0]  s_axi_rresp;
-  input           s_axi_rready;
+  input           s_axi_aclk,
+  input           s_axi_aresetn,
+  input           s_axi_awvalid,
+  input   [31:0]  s_axi_awaddr,
+  input   [ 2:0]  s_axi_awprot,
+  output          s_axi_awready,
+  input           s_axi_wvalid,
+  input   [31:0]  s_axi_wdata,
+  input   [ 3:0]  s_axi_wstrb,
+  output          s_axi_wready,
+  output          s_axi_bvalid,
+  output  [ 1:0]  s_axi_bresp,
+  input           s_axi_bready,
+  input           s_axi_arvalid,
+  input   [31:0]  s_axi_araddr,
+  input   [ 2:0]  s_axi_arprot,
+  output          s_axi_arready,
+  output          s_axi_rvalid,
+  output  [31:0]  s_axi_rdata,
+  output  [ 1:0]  s_axi_rresp,
+  input           s_axi_rready,
 
   // gpio
 
-  input           up_enable;
-  input           up_txnrx;
-  input   [31:0]  up_dac_gpio_in;
-  output  [31:0]  up_dac_gpio_out;
-  input   [31:0]  up_adc_gpio_in;
-  output  [31:0]  up_adc_gpio_out;
+  input           up_enable,
+  input           up_txnrx,
+  input   [31:0]  up_dac_gpio_in,
+  output  [31:0]  up_dac_gpio_out,
+  input   [31:0]  up_adc_gpio_in,
+  output  [31:0]  up_adc_gpio_out);
+
+  // derived parameters
+
+  localparam  ADC_USERPORTS_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_USERPORTS_DISABLE;
+  localparam  ADC_DATAFORMAT_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DATAFORMAT_DISABLE;
+  localparam  ADC_DCFILTER_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DCFILTER_DISABLE;
+  localparam  ADC_IQCORRECTION_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_IQCORRECTION_DISABLE;
+  localparam  DAC_DDS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_DDS_DISABLE;
+  localparam  DAC_USERPORTS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_USERPORTS_DISABLE;
+  localparam  DAC_DELAYCNTRL_DISABLE_INT = (DAC_IODELAY_ENABLE == 1) ? 0 : 1;
+  localparam  DAC_IQCORRECTION_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_IQCORRECTION_DISABLE;
 
   // internal registers
 
@@ -316,7 +212,6 @@ module axi_ad9361 (
   wire            adc_status_s;
   wire            dac_clksel_s;
   wire            dac_valid_s;
-  wire            g_dac_valid_s;
   wire    [47:0]  dac_data_s;
   wire            dac_valid_i0_s;
   wire            dac_valid_q0_s;
@@ -343,18 +238,20 @@ module axi_ad9361 (
   wire            up_wack_tdd_s;
   wire            up_rack_tdd_s;
   wire    [31:0]  up_rdata_tdd_s;
-  wire            tdd_tx_dp_en_s;
   wire            tdd_enable_s;
   wire            tdd_txnrx_s;
   wire            tdd_mode_s;
+  wire            tdd_tx_valid_s;
+  wire            tdd_rx_valid_s;
+  wire            tdd_rx_vco_en_s;
+  wire            tdd_tx_vco_en_s;
+  wire            tdd_rx_rf_en_s;
+  wire            tdd_tx_rf_en_s;
+  wire    [ 7:0]  tdd_status_s;
   wire            adc_valid_i0_s;
   wire            adc_valid_q0_s;
   wire            adc_valid_i1_s;
   wire            adc_valid_q1_s;
-  wire    [15:0]  adc_data_i0_s;
-  wire    [15:0]  adc_data_q0_s;
-  wire    [15:0]  adc_data_i1_s;
-  wire    [15:0]  adc_data_q1_s;
 
   // signal name changes
 
@@ -408,7 +305,7 @@ module axi_ad9361 (
     .adc_status (adc_status_s),
     .adc_r1_mode (adc_r1_mode),
     .adc_ddr_edgesel (adc_ddr_edgesel_s),
-    .dac_valid (g_dac_valid_s),
+    .dac_valid (dac_valid_s),
     .dac_data (dac_data_s),
     .dac_clksel (dac_clksel_s),
     .dac_r1_mode (dac_r1_mode),
@@ -467,7 +364,7 @@ module axi_ad9361 (
     .adc_status (adc_status_s),
     .adc_r1_mode (adc_r1_mode),
     .adc_ddr_edgesel (adc_ddr_edgesel_s),
-    .dac_valid (g_dac_valid_s),
+    .dac_valid (dac_valid_s),
     .dac_data (dac_data_s),
     .dac_clksel (dac_clksel_s),
     .dac_r1_mode (dac_r1_mode),
@@ -490,83 +387,73 @@ module axi_ad9361 (
   end
   endgenerate
 
+  assign dac_valid_i0 = tdd_tx_valid_s & dac_valid_i0_s;
+  assign dac_valid_q0 = tdd_tx_valid_s & dac_valid_q0_s;
+  assign dac_valid_i1 = tdd_tx_valid_s & dac_valid_i1_s;
+  assign dac_valid_q1 = tdd_tx_valid_s & dac_valid_q1_s;
+  assign adc_valid_i0 = tdd_rx_valid_s & adc_valid_i0_s;
+  assign adc_valid_q0 = tdd_rx_valid_s & adc_valid_q0_s;
+  assign adc_valid_i1 = tdd_rx_valid_s & adc_valid_i1_s;
+  assign adc_valid_q1 = tdd_rx_valid_s & adc_valid_q1_s;
+
+  // tdd
+
   generate
-  if (TDD_CONTROL_EN) begin
+  if (TDD_DISABLE == 1) begin
+  assign tdd_enable_s = 1'b0;
+  assign tdd_txnrx_s = 1'b0;
+  assign tdd_txnrx_s = 1'b0;
+  assign tdd_mode_s = 1'b0;
+  assign tdd_rx_vco_en_s = 1'b0;
+  assign tdd_tx_vco_en_s = 1'b0;
+  assign tdd_rx_rf_en_s = 1'b0;
+  assign tdd_tx_rf_en_s = 1'b0;
+  assign tdd_status_s = 8'd0;
+  assign tdd_sync_cntr  = 1'b0;
+  assign tdd_tx_valid_s = 1'b1;
+  assign tdd_rx_valid_s = 1'b1;
+  assign up_wack_tdd_s  = 1'b0;
+  assign up_rack_tdd_s  = 1'b0;
+  assign up_rdata_tdd_s = 32'b0;
+  end
+  endgenerate
 
-    wire            tdd_rx_vco_en_s;
-    wire            tdd_tx_vco_en_s;
-    wire            tdd_rx_rf_en_s;
-    wire            tdd_tx_rf_en_s;
-    wire    [ 7:0]  tdd_status_s;
-
-    axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
-      .clk (clk),
-      .rst (rst),
-      .tdd_rx_vco_en (tdd_rx_vco_en_s),
-      .tdd_tx_vco_en (tdd_tx_vco_en_s),
-      .tdd_rx_rf_en (tdd_rx_rf_en_s),
-      .tdd_tx_rf_en (tdd_tx_rf_en_s),
-      .ad9361_txnrx (tdd_txnrx_s),
-      .ad9361_enable (tdd_enable_s),
-      .ad9361_tdd_status (tdd_status_s));
-
-    assign g_dac_valid_s = dac_valid_s;
-    assign dac_valid_i0  = tdd_tx_valid_s & dac_valid_i0_s;
-    assign dac_valid_q0  = tdd_tx_valid_s & dac_valid_q0_s;
-    assign dac_valid_i1  = tdd_tx_valid_s & dac_valid_i1_s;
-    assign dac_valid_q1  = tdd_tx_valid_s & dac_valid_q1_s;
-    assign adc_valid_i0  = tdd_rx_valid_s & adc_valid_i0_s;
-    assign adc_valid_q0  = tdd_rx_valid_s & adc_valid_q0_s;
-    assign adc_valid_i1  = tdd_rx_valid_s & adc_valid_i1_s;
-    assign adc_valid_q1  = tdd_rx_valid_s & adc_valid_q1_s;
-
-    // TDD control
-
-    axi_ad9361_tdd i_tdd (
-      .clk (clk),
-      .rst (rst),
-      .tdd_rx_vco_en (tdd_rx_vco_en_s),
-      .tdd_tx_vco_en (tdd_tx_vco_en_s),
-      .tdd_rx_rf_en (tdd_rx_rf_en_s),
-      .tdd_tx_rf_en (tdd_tx_rf_en_s),
-      .tdd_enabled (tdd_mode_s),
-      .tdd_status (tdd_status_s),
-      .tdd_sync (tdd_sync),
-      .tdd_sync_cntr (tdd_sync_cntr),
-      .tdd_tx_valid (tdd_tx_valid_s),
-      .tdd_rx_valid (tdd_rx_valid_s),
-      .up_rstn (up_rstn),
-      .up_clk (up_clk),
-      .up_wreq (up_wreq_s),
-      .up_waddr (up_waddr_s),
-      .up_wdata (up_wdata_s),
-      .up_wack (up_wack_tdd_s),
-      .up_rreq (up_rreq_s),
-      .up_raddr (up_raddr_s),
-      .up_rdata (up_rdata_tdd_s),
-      .up_rack (up_rack_tdd_s));
-
-  end else begin
-
-    // TDD control bypass
-
-    assign tdd_mode_s     = 1'b0;
-    assign tdd_enable_s   = 1'b0;
-    assign tdd_txnrx_s    = 1'b0;
-    assign tdd_sync_cntr  = 1'b0;
-    assign g_dac_valid_s  = dac_valid_s;
-    assign dac_valid_i0   = dac_valid_i0_s;
-    assign dac_valid_q0   = dac_valid_q0_s;
-    assign dac_valid_i1   = dac_valid_i1_s;
-    assign dac_valid_q1   = dac_valid_q1_s;
-    assign adc_valid_i0   = adc_valid_i0_s;
-    assign adc_valid_q0   = adc_valid_q0_s;
-    assign adc_valid_i1   = adc_valid_i1_s;
-    assign adc_valid_q1   = adc_valid_q1_s;
-    assign up_wack_tdd_s  = 1'b0;
-    assign up_rack_tdd_s  = 1'b0;
-    assign up_rdata_tdd_s = 32'b0;
+  generate
+  if (TDD_DISABLE == 0) begin
+  axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
+    .clk (clk),
+    .rst (rst),
+    .tdd_rx_vco_en (tdd_rx_vco_en_s),
+    .tdd_tx_vco_en (tdd_tx_vco_en_s),
+    .tdd_rx_rf_en (tdd_rx_rf_en_s),
+    .tdd_tx_rf_en (tdd_tx_rf_en_s),
+    .ad9361_txnrx (tdd_txnrx_s),
+    .ad9361_enable (tdd_enable_s),
+    .ad9361_tdd_status (tdd_status_s));
 
+  axi_ad9361_tdd i_tdd (
+    .clk (clk),
+    .rst (rst),
+    .tdd_rx_vco_en (tdd_rx_vco_en_s),
+    .tdd_tx_vco_en (tdd_tx_vco_en_s),
+    .tdd_rx_rf_en (tdd_rx_rf_en_s),
+    .tdd_tx_rf_en (tdd_tx_rf_en_s),
+    .tdd_enabled (tdd_mode_s),
+    .tdd_status (tdd_status_s),
+    .tdd_sync (tdd_sync),
+    .tdd_sync_cntr (tdd_sync_cntr),
+    .tdd_tx_valid (tdd_tx_valid_s),
+    .tdd_rx_valid (tdd_rx_valid_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_tdd_s),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_tdd_s),
+    .up_rack (up_rack_tdd_s));
   end
   endgenerate
 
@@ -574,11 +461,11 @@ module axi_ad9361 (
 
   axi_ad9361_rx #(
     .ID (ID),
-    .MODE_1R1T (R1_MODE_EN),
-    .USERPORTS_DISABLE (ADC_DATAPATH_DISABLE),
-    .DATAFORMAT_DISABLE (ADC_DATAPATH_DISABLE),
-    .DCFILTER_DISABLE (ADC_DATAPATH_DISABLE),
-    .IQCORRECTION_DISABLE (ADC_DATAPATH_DISABLE))
+    .MODE_1R1T (MODE_1R1T),
+    .USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
+    .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
+    .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
+    .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
   i_rx (
     .mmcm_rst (mmcm_rst),
     .adc_rst (rst),
@@ -626,11 +513,11 @@ module axi_ad9361 (
 
   axi_ad9361_tx #(
     .ID (ID),
-    .MODE_1R1T (R1_MODE_EN),
-    .DDS_DISABLE (DAC_DATAPATH_DISABLE),
-    .USERPORTS_DISABLE (DAC_DATAPATH_DISABLE),
-    .DELAYCNTRL_DISABLE (DAC_DATAPATH_DISABLE),
-    .IQCORRECTION_DISABLE (DAC_DATAPATH_DISABLE))
+    .MODE_1R1T (MODE_1R1T),
+    .DDS_DISABLE (DAC_DDS_DISABLE_INT),
+    .USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
+    .DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
+    .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT))
   i_tx (
     .dac_clk (clk),
     .dac_valid (dac_valid_s),

From e40311eee94a6a1a272416df6f2b88bd660beb13 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 29 Sep 2016 09:14:37 +0100
Subject: [PATCH 540/972] adrv9371x: A10soc, connected DMAs through 128 bit
 SDRAM0 port at 175MHz

---
 projects/adrv9371x/common/adrv9371x_qsys.tcl  | 22 +++++++++----------
 projects/common/a10soc/a10soc_system_qsys.tcl | 12 +++++-----
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index dc98fb212..2913a0b8b 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -451,7 +451,7 @@ set_instance_parameter_value rx_os_adcfifo {DMA_ADDRESS_WIDTH} {16}
 add_instance axi_adc_dma axi_dmac 1.0
 set_instance_parameter_value axi_adc_dma {ID} {0}
 set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {128}
 set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
 set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
 set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
@@ -468,7 +468,7 @@ set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {16}
 add_instance axi_os_adc_dma axi_dmac 1.0
 set_instance_parameter_value axi_os_adc_dma {ID} {0}
 set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {128}
 set_instance_parameter_value axi_os_adc_dma {DMA_LENGTH_WIDTH} {24}
 set_instance_parameter_value axi_os_adc_dma {DMA_2D_TRANSFER} {0}
 set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_REQ_SRC} {1}
@@ -617,9 +617,9 @@ if { $system_type=="nios" } {
 
 # SOC
 if { $system_type=="a10soc" } {
-  add_connection xcvr_pll.outclk1 axi_adc_dma.m_dest_axi_clock
-  add_connection xcvr_pll.outclk2 axi_os_adc_dma.m_dest_axi_clock
-  add_connection xcvr_pll.outclk0 axi_dac_dma.m_src_axi_clock
+  add_connection arria10_hps_0.h2f_user0_clock axi_adc_dma.m_dest_axi_clock
+  add_connection arria10_hps_0.h2f_user0_clock axi_os_adc_dma.m_dest_axi_clock
+  add_connection arria10_hps_0.h2f_user0_clock axi_dac_dma.m_src_axi_clock
   add_connection sys_rst.out_reset axi_adc_dma.m_dest_axi_reset
   add_connection sys_rst.out_reset axi_os_adc_dma.m_dest_axi_reset
   add_connection sys_rst.out_reset axi_dac_dma.m_src_axi_reset
@@ -800,9 +800,9 @@ if { $system_type=="a10soc" } {
   add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.jesd204_tx_avs
   add_connection arria10_hps_0.h2f_lw_axi_master ad9371_gpio.s1
 
-  add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram1_data
-  add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram1_data
-  add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram1_data
+  add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data
+  add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data
+  add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram0_data
 
   set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/ad9371_gpio.s1 baseAddress {0x00001000}
   set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_pll_reconfig.mgmt_avalon_slave baseAddress {0x00010000}
@@ -818,9 +818,9 @@ if { $system_type=="a10soc" } {
   set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_adc_dma.s_axi baseAddress {0x0090000}
   set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_adc_dma.s_axi baseAddress {0x000a0000}
 
-  set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000}
-  set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000}
-  set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000}
+  set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
+  set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
+  set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
 }
 
 # interrupts
diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl
index c3e4e33e0..5df47d810 100755
--- a/projects/common/a10soc/a10soc_system_qsys.tcl
+++ b/projects/common/a10soc/a10soc_system_qsys.tcl
@@ -36,9 +36,9 @@ set_instance_parameter_value arria10_hps_0 {F2S_Width} {0}
 set_instance_parameter_value arria10_hps_0 {S2F_Width} {0}
 set_instance_parameter_value arria10_hps_0 {LWH2F_Enable} {1}
 set_instance_parameter_value arria10_hps_0 {RUN_INTERNAL_BUILD_CHECKS} {0}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {5}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {0}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {1}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {6}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {1}
+set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {0}
 set_instance_parameter_value arria10_hps_0 {F2SDRAM2_ENABLED} {0}
 set_instance_parameter_value arria10_hps_0 {F2SDRAM_READY_LATENCY} {0}
 set_instance_parameter_value arria10_hps_0 {F2SDRAM2_DELAY} {4}
@@ -100,8 +100,8 @@ set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2
 set_instance_parameter_value arria10_hps_0 {MPU_CLK_VCCL} {0}
 set_instance_parameter_value arria10_hps_0 {USE_DEFAULT_MPU_CLK} {0}
 set_instance_parameter_value arria10_hps_0 {CUSTOM_MPU_CLK} {800}
-set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {400}
+set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {1}
+set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {175}
 set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_Enable} {0}
 set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_FREQ} {400}
 set_instance_parameter_value arria10_hps_0 {HMC_PLL_REF_CLK} {800}
@@ -1250,7 +1250,7 @@ add_connection sys_clk.clk gpio_i.clk clock
 add_connection sys_clk.clk gpio_o.clk clock
 add_connection sys_clk.clk sys_rst.clk clock
 
-add_connection sys_clk.clk arria10_hps_0.f2sdram1_clock clock
+add_connection arria10_hps_0.h2f_user0_clock arria10_hps_0.f2sdram0_clock clock
 
 add_connection emif_a10_hps_0.hps_emif_conduit_end arria10_hps_0.emif conduit
 set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif endPort {}

From ffec95f220c88f36ff297eb645d94bb453f1f672 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 29 Sep 2016 11:47:56 -0400
Subject: [PATCH 541/972] ad9371- xcvr updates

---
 library/axi_ad9371/axi_ad9371.v      |  29 +++++++-
 library/axi_ad9371/axi_ad9371_if.v   | 102 ++++++++++++++++++---------
 library/axi_ad9371/axi_ad9371_ip.tcl |   6 +-
 3 files changed, 101 insertions(+), 36 deletions(-)

diff --git a/library/axi_ad9371/axi_ad9371.v b/library/axi_ad9371/axi_ad9371.v
index 1adef14f0..2d82d45c8 100644
--- a/library/axi_ad9371/axi_ad9371.v
+++ b/library/axi_ad9371/axi_ad9371.v
@@ -42,14 +42,22 @@ module axi_ad9371 (
   // receive
 
   adc_clk,
+  adc_rx_valid,
+  adc_rx_sof,
   adc_rx_data,
+  adc_rx_ready,
   adc_os_clk,
+  adc_rx_os_valid,
+  adc_rx_os_sof,
   adc_rx_os_data,
+  adc_rx_os_ready,
 
   // transmit
 
   dac_clk,
+  dac_tx_valid,
   dac_tx_data,
+  dac_tx_ready,
 
   // master/slave
 
@@ -124,20 +132,29 @@ module axi_ad9371 (
   // parameters
 
   parameter   ID = 0;
+  parameter   DEVICE_TYPE = 0;
   parameter   DAC_DATAPATH_DISABLE = 0;
   parameter   ADC_DATAPATH_DISABLE = 0;
 
   // receive
 
   input             adc_clk;
+  input             adc_rx_valid;
+  input   [  3:0]   adc_rx_sof;
   input   [ 63:0]   adc_rx_data;
+  output            adc_rx_ready;
   input             adc_os_clk;
+  input             adc_rx_os_valid;
+  input   [  3:0]   adc_rx_os_sof;
   input   [ 63:0]   adc_rx_os_data;
+  output            adc_rx_os_ready;
 
   // transmit
 
   input             dac_clk;
+  output            dac_tx_valid;
   output  [127:0]   dac_tx_data;
+  input             dac_tx_ready;
 
   // master/slave
 
@@ -237,6 +254,12 @@ module axi_ad9371 (
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
 
+  // defaults
+
+  assign dac_tx_valid = 1'b1;
+  assign adc_rx_ready = 1'b1;
+  assign adc_rx_os_ready = 1'b1;
+
   // processor read interface
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -253,10 +276,14 @@ module axi_ad9371 (
 
   // device interface
 
-  axi_ad9371_if i_if (
+  axi_ad9371_if #(
+    .DEVICE_TYPE (DEVICE_TYPE))
+  i_if (
     .adc_clk (adc_clk),
+    .adc_rx_sof (adc_rx_sof),
     .adc_rx_data (adc_rx_data),
     .adc_os_clk (adc_os_clk),
+    .adc_rx_os_sof (adc_rx_os_sof),
     .adc_rx_os_data (adc_rx_os_data),
     .adc_data (adc_data_s),
     .adc_os_valid (adc_os_valid_s),
diff --git a/library/axi_ad9371/axi_ad9371_if.v b/library/axi_ad9371/axi_ad9371_if.v
index df834e204..476c08012 100644
--- a/library/axi_ad9371/axi_ad9371_if.v
+++ b/library/axi_ad9371/axi_ad9371_if.v
@@ -42,8 +42,10 @@ module axi_ad9371_if (
   // receive
 
   adc_clk,
+  adc_rx_sof,
   adc_rx_data,
   adc_os_clk,
+  adc_rx_os_sof,
   adc_rx_os_data,
 
   adc_data,
@@ -57,13 +59,18 @@ module axi_ad9371_if (
 
   dac_data);
 
+  // parameters
+
+  parameter   DEVICE_TYPE = 0;
+
   // receive
 
   input             adc_clk;
+  input   [  3:0]   adc_rx_sof;
   input   [ 63:0]   adc_rx_data;
   input             adc_os_clk;
+  input   [  3:0]   adc_rx_os_sof;
   input   [ 63:0]   adc_rx_os_data;
-
   output  [ 63:0]   adc_data;
   output            adc_os_valid;
   output  [ 63:0]   adc_os_data;
@@ -72,46 +79,73 @@ module axi_ad9371_if (
 
   input             dac_clk;
   output  [127:0]   dac_tx_data;
-
   input   [127:0]   dac_data;
 
+  // internal signals
+
+  wire    [ 63:0]   adc_rx_data_s;
+  wire    [ 63:0]   adc_rx_os_data_s;
+
   // delineating
 
-  assign adc_data[((8* 7)+7):(8* 7)] = adc_rx_data[((8* 6)+7):(8* 6)];
-  assign adc_data[((8* 6)+7):(8* 6)] = adc_rx_data[((8* 7)+7):(8* 7)];
-  assign adc_data[((8* 5)+7):(8* 5)] = adc_rx_data[((8* 4)+7):(8* 4)];
-  assign adc_data[((8* 4)+7):(8* 4)] = adc_rx_data[((8* 5)+7):(8* 5)];
-  assign adc_data[((8* 3)+7):(8* 3)] = adc_rx_data[((8* 2)+7):(8* 2)];
-  assign adc_data[((8* 2)+7):(8* 2)] = adc_rx_data[((8* 3)+7):(8* 3)];
-  assign adc_data[((8* 1)+7):(8* 1)] = adc_rx_data[((8* 0)+7):(8* 0)];
-  assign adc_data[((8* 0)+7):(8* 0)] = adc_rx_data[((8* 1)+7):(8* 1)];
+  assign adc_data[((8* 7)+7):(8* 7)] = adc_rx_data_s[((8* 6)+7):(8* 6)];
+  assign adc_data[((8* 6)+7):(8* 6)] = adc_rx_data_s[((8* 7)+7):(8* 7)];
+  assign adc_data[((8* 5)+7):(8* 5)] = adc_rx_data_s[((8* 4)+7):(8* 4)];
+  assign adc_data[((8* 4)+7):(8* 4)] = adc_rx_data_s[((8* 5)+7):(8* 5)];
+  assign adc_data[((8* 3)+7):(8* 3)] = adc_rx_data_s[((8* 2)+7):(8* 2)];
+  assign adc_data[((8* 2)+7):(8* 2)] = adc_rx_data_s[((8* 3)+7):(8* 3)];
+  assign adc_data[((8* 1)+7):(8* 1)] = adc_rx_data_s[((8* 0)+7):(8* 0)];
+  assign adc_data[((8* 0)+7):(8* 0)] = adc_rx_data_s[((8* 1)+7):(8* 1)];
 
   assign adc_os_valid = 'd1;
-  assign adc_os_data[((8* 7)+7):(8* 7)] = adc_rx_os_data[((8* 6)+7):(8* 6)];
-  assign adc_os_data[((8* 6)+7):(8* 6)] = adc_rx_os_data[((8* 7)+7):(8* 7)];
-  assign adc_os_data[((8* 5)+7):(8* 5)] = adc_rx_os_data[((8* 4)+7):(8* 4)];
-  assign adc_os_data[((8* 4)+7):(8* 4)] = adc_rx_os_data[((8* 5)+7):(8* 5)];
-  assign adc_os_data[((8* 3)+7):(8* 3)] = adc_rx_os_data[((8* 2)+7):(8* 2)];
-  assign adc_os_data[((8* 2)+7):(8* 2)] = adc_rx_os_data[((8* 3)+7):(8* 3)];
-  assign adc_os_data[((8* 1)+7):(8* 1)] = adc_rx_os_data[((8* 0)+7):(8* 0)];
-  assign adc_os_data[((8* 0)+7):(8* 0)] = adc_rx_os_data[((8* 1)+7):(8* 1)];
+  assign adc_os_data[((8* 7)+7):(8* 7)] = adc_rx_os_data_s[((8* 6)+7):(8* 6)];
+  assign adc_os_data[((8* 6)+7):(8* 6)] = adc_rx_os_data_s[((8* 7)+7):(8* 7)];
+  assign adc_os_data[((8* 5)+7):(8* 5)] = adc_rx_os_data_s[((8* 4)+7):(8* 4)];
+  assign adc_os_data[((8* 4)+7):(8* 4)] = adc_rx_os_data_s[((8* 5)+7):(8* 5)];
+  assign adc_os_data[((8* 3)+7):(8* 3)] = adc_rx_os_data_s[((8* 2)+7):(8* 2)];
+  assign adc_os_data[((8* 2)+7):(8* 2)] = adc_rx_os_data_s[((8* 3)+7):(8* 3)];
+  assign adc_os_data[((8* 1)+7):(8* 1)] = adc_rx_os_data_s[((8* 0)+7):(8* 0)];
+  assign adc_os_data[((8* 0)+7):(8* 0)] = adc_rx_os_data_s[((8* 1)+7):(8* 1)];
 
-  assign dac_tx_data[((8*15)+7):(8*15)] = dac_data[((8*14)+7):(8*14)];
-  assign dac_tx_data[((8*14)+7):(8*14)] = dac_data[((8*15)+7):(8*15)];
-  assign dac_tx_data[((8*13)+7):(8*13)] = dac_data[((8*12)+7):(8*12)];
-  assign dac_tx_data[((8*12)+7):(8*12)] = dac_data[((8*13)+7):(8*13)];
-  assign dac_tx_data[((8*11)+7):(8*11)] = dac_data[((8*10)+7):(8*10)];
-  assign dac_tx_data[((8*10)+7):(8*10)] = dac_data[((8*11)+7):(8*11)];
-  assign dac_tx_data[((8* 9)+7):(8* 9)] = dac_data[((8* 8)+7):(8* 8)];
-  assign dac_tx_data[((8* 8)+7):(8* 8)] = dac_data[((8* 9)+7):(8* 9)];
-  assign dac_tx_data[((8* 7)+7):(8* 7)] = dac_data[((8* 6)+7):(8* 6)];
-  assign dac_tx_data[((8* 6)+7):(8* 6)] = dac_data[((8* 7)+7):(8* 7)];
-  assign dac_tx_data[((8* 5)+7):(8* 5)] = dac_data[((8* 4)+7):(8* 4)];
-  assign dac_tx_data[((8* 4)+7):(8* 4)] = dac_data[((8* 5)+7):(8* 5)];
-  assign dac_tx_data[((8* 3)+7):(8* 3)] = dac_data[((8* 2)+7):(8* 2)];
-  assign dac_tx_data[((8* 2)+7):(8* 2)] = dac_data[((8* 3)+7):(8* 3)];
-  assign dac_tx_data[((8* 1)+7):(8* 1)] = dac_data[((8* 0)+7):(8* 0)];
-  assign dac_tx_data[((8* 0)+7):(8* 0)] = dac_data[((8* 1)+7):(8* 1)];
+  assign dac_tx_data[((8*15)+7):(8*15)] = (DEVICE_TYPE == 1) ? dac_data[((8*13)+7):(8*13)] : dac_data[((8*14)+7):(8*14)];
+  assign dac_tx_data[((8*14)+7):(8*14)] = (DEVICE_TYPE == 1) ? dac_data[((8*12)+7):(8*12)] : dac_data[((8*15)+7):(8*15)];
+  assign dac_tx_data[((8*13)+7):(8*13)] = (DEVICE_TYPE == 1) ? dac_data[((8*15)+7):(8*15)] : dac_data[((8*12)+7):(8*12)];
+  assign dac_tx_data[((8*12)+7):(8*12)] = (DEVICE_TYPE == 1) ? dac_data[((8*14)+7):(8*14)] : dac_data[((8*13)+7):(8*13)];
+  assign dac_tx_data[((8*11)+7):(8*11)] = (DEVICE_TYPE == 1) ? dac_data[((8* 9)+7):(8* 9)] : dac_data[((8*10)+7):(8*10)];
+  assign dac_tx_data[((8*10)+7):(8*10)] = (DEVICE_TYPE == 1) ? dac_data[((8* 8)+7):(8* 8)] : dac_data[((8*11)+7):(8*11)];
+  assign dac_tx_data[((8* 9)+7):(8* 9)] = (DEVICE_TYPE == 1) ? dac_data[((8*11)+7):(8*11)] : dac_data[((8* 8)+7):(8* 8)];
+  assign dac_tx_data[((8* 8)+7):(8* 8)] = (DEVICE_TYPE == 1) ? dac_data[((8*10)+7):(8*10)] : dac_data[((8* 9)+7):(8* 9)];
+  assign dac_tx_data[((8* 7)+7):(8* 7)] = (DEVICE_TYPE == 1) ? dac_data[((8* 5)+7):(8* 5)] : dac_data[((8* 6)+7):(8* 6)];
+  assign dac_tx_data[((8* 6)+7):(8* 6)] = (DEVICE_TYPE == 1) ? dac_data[((8* 4)+7):(8* 4)] : dac_data[((8* 7)+7):(8* 7)];
+  assign dac_tx_data[((8* 5)+7):(8* 5)] = (DEVICE_TYPE == 1) ? dac_data[((8* 7)+7):(8* 7)] : dac_data[((8* 4)+7):(8* 4)];
+  assign dac_tx_data[((8* 4)+7):(8* 4)] = (DEVICE_TYPE == 1) ? dac_data[((8* 6)+7):(8* 6)] : dac_data[((8* 5)+7):(8* 5)];
+  assign dac_tx_data[((8* 3)+7):(8* 3)] = (DEVICE_TYPE == 1) ? dac_data[((8* 1)+7):(8* 1)] : dac_data[((8* 2)+7):(8* 2)];
+  assign dac_tx_data[((8* 2)+7):(8* 2)] = (DEVICE_TYPE == 1) ? dac_data[((8* 0)+7):(8* 0)] : dac_data[((8* 3)+7):(8* 3)];
+  assign dac_tx_data[((8* 1)+7):(8* 1)] = (DEVICE_TYPE == 1) ? dac_data[((8* 3)+7):(8* 3)] : dac_data[((8* 0)+7):(8* 0)];
+  assign dac_tx_data[((8* 0)+7):(8* 0)] = (DEVICE_TYPE == 1) ? dac_data[((8* 2)+7):(8* 2)] : dac_data[((8* 1)+7):(8* 1)];
+
+  // instantiations
+
+  genvar n;
+
+  generate
+  for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
+
+  ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_rx_if (
+    .rx_clk (adc_clk),
+    .rx_ip_sof (adc_rx_sof),
+    .rx_ip_data (adc_rx_data[((n*32)+31):(n*32)]),
+    .rx_sof (),
+    .rx_data (adc_rx_data_s[((n*32)+31):(n*32)]));
+
+  ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_rx_os_if (
+    .rx_clk (adc_os_clk),
+    .rx_ip_sof (adc_rx_os_sof),
+    .rx_ip_data (adc_rx_os_data[((n*32)+31):(n*32)]),
+    .rx_sof (),
+    .rx_data (adc_rx_os_data_s[((n*32)+31):(n*32)]));
+  end
+  endgenerate
 
 endmodule
 
diff --git a/library/axi_ad9371/axi_ad9371_ip.tcl b/library/axi_ad9371/axi_ad9371_ip.tcl
index 7f5e2afe6..551e3289a 100755
--- a/library/axi_ad9371/axi_ad9371_ip.tcl
+++ b/library/axi_ad9371/axi_ad9371_ip.tcl
@@ -22,6 +22,7 @@ adi_ip_files axi_ad9371 [list \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
   "$ad_hdl_dir/library/common/up_dac_common.v" \
   "$ad_hdl_dir/library/common/up_dac_channel.v" \
+  "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
   "axi_ad9371_if.v" \
   "axi_ad9371_rx_channel.v" \
   "axi_ad9371_rx.v" \
@@ -35,9 +36,12 @@ adi_ip_properties axi_ad9371
 adi_ip_constraints axi_jesd_gt [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
 
-set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]
 

From 4a5b7fc7230845801a81c4d058f20726bcb44ba8 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 29 Sep 2016 11:49:17 -0400
Subject: [PATCH 542/972] scripts- reconnect added

---
 projects/scripts/adi_board.tcl | 43 +++++++++++++++++++++++++++-------
 1 file changed, 35 insertions(+), 8 deletions(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 0df39b0d6..4c5abefc2 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -132,16 +132,16 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
     set m [expr ($n + $index)]
 
     if {$tx_or_rx_n == 0} {
-      ad_connect  ${a_xcvr}/up_es_${m} ${u_xcvr}/up_es_${m}
+      ad_connect  ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${m}
       ad_connect  ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${m}
     }
 
     if {(($m%4) == 0) && ($qpll_enable == 1)} {
-      ad_connect  ${a_xcvr}/up_cm_${m} ${u_xcvr}/up_cm_${m}
+      ad_connect  ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
     }
 
-    ad_connect  ${a_xcvr}/up_ch_${m} ${u_xcvr}/up_${txrx}_${m}
-    ad_connect  ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${m}_${txrx}
+    ad_connect  ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${m}
+    ad_connect  ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx}
     ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
 
     if {(($m%4) == 0) && ($qpll_enable == 1)} {
@@ -181,10 +181,32 @@ proc ad_disconnect {p_name_1 p_name_2} {
   set m_name_2 [ad_connect_type $p_name_2]
 
   if {[get_property CLASS $m_name_1] eq "bd_net"} {
-    puts "disconnect_bd_net $m_name_1 $m_name_2"
     disconnect_bd_net $m_name_1 $m_name_2
     return
   }
+
+}
+
+proc ad_reconct {p_name_1 p_name_2} {
+
+  set m_name_1 [ad_connect_type $p_name_1]
+  set m_name_2 [ad_connect_type $p_name_2]
+
+  if {[get_property CLASS $m_name_1] eq "bd_pin"} {
+    delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
+      [find_bd_objs -relation connected_to $m_name_1]]
+    delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
+      [find_bd_objs -relation connected_to $m_name_2]]
+  }
+
+  if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
+    delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
+      [find_bd_objs -relation connected_to $m_name_1]]
+    delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
+      [find_bd_objs -relation connected_to $m_name_2]]
+  }
+
+  ad_connect $p_name_1 $p_name_2
 }
 
 ###################################################################################################
@@ -356,12 +378,17 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     set p_intf_clock ""
   }
 
+  regsub clk $p_clk resetn p_rst
+  if {[get_bd_nets -quiet $p_rst] eq ""} {
+    set p_rst sys_cpu_resetn
+  }
+
   if {$m_interconnect_index == 0} {
     set_property CONFIG.NUM_MI 1 $m_interconnect_cell
     set_property CONFIG.NUM_SI 1 $m_interconnect_cell
-    ad_connect sys_cpu_resetn $m_interconnect_cell/ARESETN
+    ad_connect $p_rst $m_interconnect_cell/ARESETN
     ad_connect $p_clk $m_interconnect_cell/ACLK
-    ad_connect sys_cpu_resetn $m_interconnect_cell/M00_ARESETN
+    ad_connect $p_rst $m_interconnect_cell/M00_ARESETN
     ad_connect $p_clk $m_interconnect_cell/M00_ACLK
     ad_connect $m_interconnect_cell/M00_AXI $p_name_int
     if {$p_intf_clock ne ""} {
@@ -369,7 +396,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
     }
   } else {
     set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
-    ad_connect sys_cpu_resetn $m_interconnect_cell/${i_str}_ARESETN
+    ad_connect $p_rst $m_interconnect_cell/${i_str}_ARESETN
     ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
     ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
     if {$p_intf_clock ne ""} {

From 4950c6c773603ba1eff2b7ba250a047af175d2c6 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 29 Sep 2016 11:49:49 -0400
Subject: [PATCH 543/972] adrv9371x - xcvr updates

---
 projects/adrv9371x/common/adrv9371x_bd.tcl | 420 ++++++++-------------
 projects/adrv9371x/zc706/system_constr.xdc |  13 +-
 projects/adrv9371x/zc706/system_top.v      |  74 ++--
 3 files changed, 204 insertions(+), 303 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index ea73cb727..d071fe59b 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -1,38 +1,30 @@
 
 # ad9371
 
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir I rx_sysref
-create_bd_port -dir I -from 1 -to 0 rx_p
-create_bd_port -dir I -from 1 -to 0 rx_n
-create_bd_port -dir O rx_sync
-create_bd_port -dir I -from 1 -to 0 rx_os_p
-create_bd_port -dir I -from 1 -to 0 rx_os_n
-create_bd_port -dir O rx_os_sync
-
-create_bd_port -dir I tx_ref_clk
-create_bd_port -dir I tx_sysref
-create_bd_port -dir O -from 3 -to 0 tx_p
-create_bd_port -dir O -from 3 -to 0 tx_n
-create_bd_port -dir I tx_sync
-
 create_bd_port -dir I dac_fifo_bypass
 
-# dma clock
-
-set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150}] $sys_ps7
-
-set sys_dma_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_dma_rstgen]
-set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_dma_rstgen
-
-ad_connect  sys_dma_clk sys_ps7/FCLK_CLK2
-ad_connect  sys_dma_reset sys_dma_rstgen/peripheral_reset
-ad_connect  sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
-ad_connect  sys_dma_clk sys_dma_rstgen/slowest_sync_clk
-ad_connect  sys_dma_rstgen/ext_reset_in sys_ps7/FCLK_RESET2_N
-
 # dac peripherals
 
+set axi_ad9371_tx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_tx_clkgen]
+set_property -dict [list CONFIG.ID {2}] $axi_ad9371_tx_clkgen
+set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_tx_clkgen
+set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_tx_clkgen
+set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_tx_clkgen
+set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_tx_clkgen
+
+set axi_ad9371_tx_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_tx_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9371_tx_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9371_tx_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9371_tx_xcvr
+
+set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_tx_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9371_tx_jesd
+set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9371_tx_jesd
+
+set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
+
 set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_tx_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma
@@ -45,28 +37,31 @@ set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_tx_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9371_tx_dma
 
-set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
-
-set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_tx_jesd]
-set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9371_tx_jesd
-set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9371_tx_jesd
-
 # adc peripherals
 
+set axi_ad9371_rx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_rx_clkgen]
+set_property -dict [list CONFIG.ID {2}] $axi_ad9371_rx_clkgen
+set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_rx_clkgen
+set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_rx_clkgen
+set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_rx_clkgen
+set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_rx_clkgen
+
+set axi_ad9371_rx_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_rx_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad9371_rx_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9371_rx_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9371_rx_xcvr
+
 set axi_ad9371_rx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_jesd
 set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_jesd
 
-set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_os_jesd]
-set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_os_jesd
-set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_os_jesd
+set util_ad9371_rx_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_cpack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9371_rx_cpack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_rx_cpack
 
 set axi_ad9371_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma
-set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_dma
@@ -77,6 +72,28 @@ set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_dma
 
+# adc-os peripherals
+
+set axi_ad9371_rx_os_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_rx_os_clkgen]
+set_property -dict [list CONFIG.ID {2}] $axi_ad9371_rx_os_clkgen
+set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_rx_os_clkgen
+set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_rx_os_clkgen
+set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_rx_os_clkgen
+set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_rx_os_clkgen
+
+set axi_ad9371_rx_os_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_rx_os_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad9371_rx_os_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9371_rx_os_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9371_rx_os_xcvr
+
+set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_os_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_os_jesd
+set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_os_jesd
+
+set util_ad9371_rx_os_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_os_cpack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_rx_os_cpack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9371_rx_os_cpack
+
 set axi_ad9371_rx_os_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_os_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_os_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_os_dma
@@ -90,155 +107,68 @@ set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_os_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_os_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_os_dma
 
-set util_ad9371_rx_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_cpack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9371_rx_cpack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_rx_cpack
-
-set util_ad9371_rx_os_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_os_cpack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_rx_os_cpack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9371_rx_os_cpack
-
-# ad9371 gt & core
+# common cores
 
 set axi_ad9371_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9371:1.0 axi_ad9371_core]
 
-set axi_ad9371_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9371_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9371_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_ad9371_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9371_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {5}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {5}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_0 {3}] $axi_ad9371_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9371_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {5}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {0}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {5}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {0}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_1 {0}] $axi_ad9371_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9371_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {5}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_2 {5}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {0}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9371_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {5}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {0}] $axi_ad9371_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_3 {5}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {0}] $axi_ad9371_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_ad9371_gt
+set util_ad9371_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad9371_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {5}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {5}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.PMA_RSV {0x00018480}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_ad9371_xcvr
 
-set util_ad9371_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9371_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_ad9371_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9371_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_ad9371_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9371_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad9371_gt
-set_property -dict [list CONFIG.TX_ENABLE {1}] $util_ad9371_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_ad9371_gt
+# xcvr interfaces
 
-set util_ad9371_os_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9371_os_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9371_os_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9371_os_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad9371_os_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9371_os_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad9371_os_gt
-set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9371_os_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {2}] $util_ad9371_os_gt
+ad_connect  sys_cpu_resetn util_ad9371_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_ad9371_xcvr/up_clk
 
-# ad9371 data path clocks
+ad_xcvrcon  util_ad9371_xcvr axi_ad9371_tx_xcvr axi_ad9371_tx_jesd
+ad_reconct  util_ad9371_xcvr/tx_out_clk_0 axi_ad9371_tx_clkgen/clk
+ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_0
+ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_1
+ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_2
+ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_3
+ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk
+ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd_rstgen/slowest_sync_clk
+ad_reconct  util_ad9371_xcvr/tx_0 axi_ad9371_tx_jesd/gt3_tx
+ad_reconct  util_ad9371_xcvr/tx_1 axi_ad9371_tx_jesd/gt0_tx
+ad_reconct  util_ad9371_xcvr/tx_2 axi_ad9371_tx_jesd/gt1_tx
+ad_reconct  util_ad9371_xcvr/tx_3 axi_ad9371_tx_jesd/gt2_tx
+ad_xcvrcon  util_ad9371_xcvr axi_ad9371_rx_xcvr axi_ad9371_rx_jesd
+ad_reconct  util_ad9371_xcvr/rx_out_clk_0 axi_ad9371_rx_clkgen/clk
+ad_connect  axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_0
+ad_connect  axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_1
+ad_connect  axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk
+ad_connect  axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd_rstgen/slowest_sync_clk
+ad_xcvrcon  util_ad9371_xcvr axi_ad9371_rx_os_xcvr axi_ad9371_rx_os_jesd
+ad_reconct  util_ad9371_xcvr/rx_out_clk_2 axi_ad9371_rx_os_clkgen/clk
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_2
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_3
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd_rstgen/slowest_sync_clk
 
-set axi_tx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_tx_clkgen]
-set_property -dict [list CONFIG.ID {2}] $axi_tx_clkgen
-set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_tx_clkgen
-set_property -dict [list CONFIG.VCO_DIV {1}] $axi_tx_clkgen
-set_property -dict [list CONFIG.VCO_MUL {8}] $axi_tx_clkgen
-set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_tx_clkgen
+# dma clock & reset
 
-set axi_rx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_rx_clkgen]
-set_property -dict [list CONFIG.ID {2}] $axi_rx_clkgen
-set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_rx_clkgen
-set_property -dict [list CONFIG.VCO_DIV {1}] $axi_rx_clkgen
-set_property -dict [list CONFIG.VCO_MUL {8}] $axi_rx_clkgen
-set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_rx_clkgen
+set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150}] $sys_ps7
 
-set axi_rx_os_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_rx_os_clkgen]
-set_property -dict [list CONFIG.ID {2}] $axi_rx_os_clkgen
-set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_rx_os_clkgen
-set_property -dict [list CONFIG.VCO_DIV {1}] $axi_rx_os_clkgen
-set_property -dict [list CONFIG.VCO_MUL {8}] $axi_rx_os_clkgen
-set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_rx_os_clkgen
+set sys_dma_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_dma_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_dma_rstgen
 
-# connections (gt)
-
-ad_connect  util_ad9371_gt/qpll_ref_clk rx_ref_clk
-ad_connect  util_ad9371_gt/cpll_ref_clk tx_ref_clk
-ad_connect  util_ad9371_os_gt/qpll_ref_clk rx_ref_clk
-ad_connect  util_ad9371_os_gt/cpll_ref_clk tx_ref_clk
-
-ad_connect  axi_ad9371_gt/gt_qpll_0 util_ad9371_gt/gt_qpll_0
-ad_connect  axi_ad9371_gt/gt_pll_0 util_ad9371_gt/gt_pll_0
-ad_connect  axi_ad9371_gt/gt_pll_1 util_ad9371_gt/gt_pll_1
-ad_connect  axi_ad9371_gt/gt_pll_2 util_ad9371_gt/gt_pll_2
-ad_connect  axi_ad9371_gt/gt_pll_3 util_ad9371_gt/gt_pll_3
-ad_connect  axi_ad9371_gt/gt_rx_0 util_ad9371_gt/gt_rx_0
-ad_connect  axi_ad9371_gt/gt_rx_1 util_ad9371_gt/gt_rx_1
-ad_connect  axi_ad9371_gt/gt_rx_ip_0 axi_ad9371_rx_jesd/gt0_rx
-ad_connect  axi_ad9371_gt/gt_rx_ip_1 axi_ad9371_rx_jesd/gt1_rx
-ad_connect  axi_ad9371_gt/rx_gt_comma_align_enb_0 axi_ad9371_rx_jesd/rxencommaalign_out
-ad_connect  axi_ad9371_gt/rx_gt_comma_align_enb_1 axi_ad9371_rx_jesd/rxencommaalign_out
-ad_connect  axi_ad9371_gt/gt_rx_2 util_ad9371_os_gt/gt_rx_0
-ad_connect  axi_ad9371_gt/gt_rx_3 util_ad9371_os_gt/gt_rx_1
-ad_connect  axi_ad9371_gt/gt_rx_ip_2 axi_ad9371_rx_os_jesd/gt0_rx
-ad_connect  axi_ad9371_gt/gt_rx_ip_3 axi_ad9371_rx_os_jesd/gt1_rx
-ad_connect  axi_ad9371_gt/rx_gt_comma_align_enb_2 axi_ad9371_rx_os_jesd/rxencommaalign_out
-ad_connect  axi_ad9371_gt/rx_gt_comma_align_enb_3 axi_ad9371_rx_os_jesd/rxencommaalign_out
-ad_connect  axi_ad9371_gt/gt_tx_0 util_ad9371_gt/gt_tx_0
-ad_connect  axi_ad9371_gt/gt_tx_1 util_ad9371_gt/gt_tx_1
-ad_connect  axi_ad9371_gt/gt_tx_2 util_ad9371_gt/gt_tx_2
-ad_connect  axi_ad9371_gt/gt_tx_3 util_ad9371_gt/gt_tx_3
-ad_connect  axi_ad9371_gt/gt_tx_ip_0 axi_ad9371_tx_jesd/gt0_tx
-ad_connect  axi_ad9371_gt/gt_tx_ip_1 axi_ad9371_tx_jesd/gt1_tx
-ad_connect  axi_ad9371_gt/gt_tx_ip_2 axi_ad9371_tx_jesd/gt2_tx
-ad_connect  axi_ad9371_gt/gt_tx_ip_3 axi_ad9371_tx_jesd/gt3_tx
+ad_connect  sys_dma_clk sys_ps7/FCLK_CLK2
+ad_connect  sys_dma_clk sys_dma_rstgen/slowest_sync_clk
+ad_connect  sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in
+ad_connect  sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
 
 # connections (dac)
 
-ad_connect  util_ad9371_gt/tx_sysref tx_sysref
-ad_connect  util_ad9371_gt/tx_p tx_p
-ad_connect  util_ad9371_gt/tx_n tx_n
-ad_connect  util_ad9371_gt/tx_sync tx_sync
-ad_connect  util_ad9371_gt/tx_out_clk axi_tx_clkgen/clk
-ad_connect  axi_tx_clkgen/clk_0 util_ad9371_gt/tx_clk
-ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk
-ad_connect  util_ad9371_gt/tx_ip_rst axi_ad9371_tx_jesd/tx_reset
-ad_connect  util_ad9371_gt/tx_ip_rst_done axi_ad9371_tx_jesd/tx_reset_done
-ad_connect  util_ad9371_gt/tx_ip_sysref axi_ad9371_tx_jesd/tx_sysref
-ad_connect  util_ad9371_gt/tx_ip_sync axi_ad9371_tx_jesd/tx_sync
-ad_connect  util_ad9371_gt/tx_ip_data axi_ad9371_tx_jesd/tx_tdata
-ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_core/dac_clk
-ad_connect  util_ad9371_gt/tx_data axi_ad9371_core/dac_tx_data
-ad_connect  axi_tx_clkgen/clk_0 util_ad9371_tx_upack/dac_clk
+ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_core/dac_clk
+ad_connect  axi_ad9371_tx_jesd/tx_tdata axi_ad9371_core/dac_tx_data
+ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_tx_upack/dac_clk
 ad_connect  axi_ad9371_core/dac_valid_i0 util_ad9371_tx_upack/dac_valid_0
 ad_connect  axi_ad9371_core/dac_enable_i0 util_ad9371_tx_upack/dac_enable_0
 ad_connect  axi_ad9371_core/dac_data_i0 util_ad9371_tx_upack/dac_data_0
@@ -251,60 +181,29 @@ ad_connect  axi_ad9371_core/dac_data_i1 util_ad9371_tx_upack/dac_data_2
 ad_connect  axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
 ad_connect  axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
 ad_connect  axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
-
-ad_connect  pl_ddr_clk axi_ad9371_dacfifo/ddr_clk
-ad_connect  pl_ddr_clk axi_ad9371_tx_dma/m_axis_aclk
-ad_connect  pl_ddr_clk axi_ad9371_dacfifo/dma_clk
-ad_connect  sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
-ad_connect  util_ad9371_gt/tx_rst axi_ad9371_dacfifo/dac_rst
-ad_connect  util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out
-ad_connect  axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
+ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
+ad_connect  axi_ad9371_rx_jesd_rstgen/peripheral_reset axi_ad9371_dacfifo/dac_rst
 ad_connect  util_ad9371_tx_upack/dac_valid axi_ad9371_dacfifo/dac_valid
 ad_connect  util_ad9371_tx_upack/dac_data axi_ad9371_dacfifo/dac_data
-
-ad_connect  axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
-ad_connect  axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready
-ad_connect  axi_ad9371_dacfifo/dma_rdata axi_ad9371_tx_dma/m_axis_data
+ad_connect  util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out
+ad_connect  axi_ad9371_dacfifo/ddr_clk axi_ad9371_dacfifo/dma_clk
+ad_connect  axi_ad9371_dacfifo/ddr_clk axi_ad9371_tx_dma/m_axis_aclk
 ad_connect  axi_ad9371_dacfifo/dma_rvalid axi_ad9371_tx_dma/m_axis_valid
+ad_connect  axi_ad9371_dacfifo/dma_rdata axi_ad9371_tx_dma/m_axis_data
+ad_connect  axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready
+ad_connect  axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
 ad_connect  axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
-
-ad_connect  dac_fifo_bypass axi_ad9371_dacfifo/dac_fifo_bypass
 ad_connect  axi_ad9371_dacfifo/dac_dunf axi_ad9371_core/dac_dunf
+ad_connect  axi_ad9371_dacfifo/dac_fifo_bypass dac_fifo_bypass
+ad_connect  sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
 
 # connections (adc)
 
-ad_connect  util_ad9371_gt/rx_sysref rx_sysref
-ad_connect  util_ad9371_gt/rx_p rx_p
-ad_connect  util_ad9371_gt/rx_n rx_n
-ad_connect  util_ad9371_gt/rx_sync rx_sync
-ad_connect  util_ad9371_os_gt/rx_p rx_os_p
-ad_connect  util_ad9371_os_gt/rx_n rx_os_n
-ad_connect  util_ad9371_os_gt/rx_sysref rx_sysref
-ad_connect  util_ad9371_os_gt/rx_sync rx_os_sync
-ad_connect  util_ad9371_gt/rx_out_clk axi_rx_clkgen/clk
-ad_connect  axi_rx_clkgen/clk_0 util_ad9371_gt/rx_clk
-ad_connect  axi_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk
-ad_connect  util_ad9371_gt/rx_ip_rst axi_ad9371_rx_jesd/rx_reset
-ad_connect  util_ad9371_gt/rx_ip_rst_done axi_ad9371_rx_jesd/rx_reset_done
-ad_connect  util_ad9371_gt/rx_ip_sysref axi_ad9371_rx_jesd/rx_sysref
-ad_connect  util_ad9371_gt/rx_ip_sync axi_ad9371_rx_jesd/rx_sync
-ad_connect  util_ad9371_gt/rx_ip_sof axi_ad9371_rx_jesd/rx_start_of_frame
-ad_connect  util_ad9371_gt/rx_ip_data axi_ad9371_rx_jesd/rx_tdata
-ad_connect  util_ad9371_os_gt/rx_out_clk axi_rx_os_clkgen/clk
-ad_connect  axi_rx_os_clkgen/clk_0 util_ad9371_os_gt/rx_clk
-ad_connect  axi_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk
-ad_connect  util_ad9371_os_gt/rx_ip_rst axi_ad9371_rx_os_jesd/rx_reset
-ad_connect  util_ad9371_os_gt/rx_ip_rst_done axi_ad9371_rx_os_jesd/rx_reset_done
-ad_connect  util_ad9371_os_gt/rx_ip_sysref axi_ad9371_rx_os_jesd/rx_sysref
-ad_connect  util_ad9371_os_gt/rx_ip_sync axi_ad9371_rx_os_jesd/rx_sync
-ad_connect  util_ad9371_os_gt/rx_ip_sof axi_ad9371_rx_jesd/rx_start_of_frame
-ad_connect  util_ad9371_os_gt/rx_ip_data axi_ad9371_rx_os_jesd/rx_tdata
-ad_connect  axi_rx_clkgen/clk_0 axi_ad9371_core/adc_clk
-ad_connect  util_ad9371_gt/rx_data axi_ad9371_core/adc_rx_data
-ad_connect  axi_rx_os_clkgen/clk_0 axi_ad9371_core/adc_os_clk
-ad_connect  util_ad9371_os_gt/rx_data axi_ad9371_core/adc_rx_os_data
-ad_connect  axi_rx_clkgen/clk_0 util_ad9371_rx_cpack/adc_clk
-ad_connect  util_ad9371_gt/rx_rst util_ad9371_rx_cpack/adc_rst
+ad_connect  axi_ad9371_rx_clkgen/clk_0 axi_ad9371_core/adc_clk
+ad_connect  axi_ad9371_rx_jesd/rx_start_of_frame axi_ad9371_core/adc_rx_sof
+ad_connect  axi_ad9371_rx_jesd/rx_tdata axi_ad9371_core/adc_rx_data
+ad_connect  axi_ad9371_rx_clkgen/clk_0 util_ad9371_rx_cpack/adc_clk
+ad_connect  axi_ad9371_rx_jesd_rstgen/peripheral_reset util_ad9371_rx_cpack/adc_rst
 ad_connect  axi_ad9371_core/adc_enable_i0 util_ad9371_rx_cpack/adc_enable_0
 ad_connect  axi_ad9371_core/adc_valid_i0 util_ad9371_rx_cpack/adc_valid_0
 ad_connect  axi_ad9371_core/adc_data_i0 util_ad9371_rx_cpack/adc_data_0
@@ -317,45 +216,54 @@ ad_connect  axi_ad9371_core/adc_data_i1 util_ad9371_rx_cpack/adc_data_2
 ad_connect  axi_ad9371_core/adc_enable_q1 util_ad9371_rx_cpack/adc_enable_3
 ad_connect  axi_ad9371_core/adc_valid_q1 util_ad9371_rx_cpack/adc_valid_3
 ad_connect  axi_ad9371_core/adc_data_q1 util_ad9371_rx_cpack/adc_data_3
-ad_connect  axi_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk
-ad_connect  sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn
+ad_connect  axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk
 ad_connect  util_ad9371_rx_cpack/adc_valid axi_ad9371_rx_dma/fifo_wr_en
 ad_connect  util_ad9371_rx_cpack/adc_sync axi_ad9371_rx_dma/fifo_wr_sync
 ad_connect  util_ad9371_rx_cpack/adc_data axi_ad9371_rx_dma/fifo_wr_din
 ad_connect  axi_ad9371_rx_dma/fifo_wr_overflow axi_ad9371_core/adc_dovf
-ad_connect  axi_rx_os_clkgen/clk_0 util_ad9371_rx_os_cpack/adc_clk
-ad_connect  util_ad9371_os_gt/rx_rst util_ad9371_rx_os_cpack/adc_rst
+ad_connect  sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn
+
+# connections (adc-os)
+
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_core/adc_os_clk
+ad_connect  axi_ad9371_rx_os_jesd/rx_start_of_frame axi_ad9371_core/adc_rx_os_sof
+ad_connect  axi_ad9371_rx_os_jesd/rx_tdata axi_ad9371_core/adc_rx_os_data
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_rx_os_cpack/adc_clk
+ad_connect  axi_ad9371_rx_os_jesd_rstgen/peripheral_reset util_ad9371_rx_os_cpack/adc_rst
 ad_connect  axi_ad9371_core/adc_os_enable_i0 util_ad9371_rx_os_cpack/adc_enable_0
 ad_connect  axi_ad9371_core/adc_os_valid_i0 util_ad9371_rx_os_cpack/adc_valid_0
 ad_connect  axi_ad9371_core/adc_os_data_i0 util_ad9371_rx_os_cpack/adc_data_0
 ad_connect  axi_ad9371_core/adc_os_enable_q0 util_ad9371_rx_os_cpack/adc_enable_1
 ad_connect  axi_ad9371_core/adc_os_valid_q0 util_ad9371_rx_os_cpack/adc_valid_1
 ad_connect  axi_ad9371_core/adc_os_data_q0 util_ad9371_rx_os_cpack/adc_data_1
-ad_connect  axi_rx_os_clkgen/clk_0 axi_ad9371_rx_os_dma/fifo_wr_clk
-ad_connect  sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_dma/fifo_wr_clk
 ad_connect  util_ad9371_rx_os_cpack/adc_valid axi_ad9371_rx_os_dma/fifo_wr_en
 ad_connect  util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync
 ad_connect  util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din
 ad_connect  axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf
+ad_connect  sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_ad9371_gt
 ad_cpu_interconnect 0x44A00000 axi_ad9371_core
-ad_cpu_interconnect 0x43C00000 axi_tx_clkgen
+ad_cpu_interconnect 0x44A60000 axi_ad9371_tx_xcvr
+ad_cpu_interconnect 0x43C00000 axi_ad9371_tx_clkgen
 ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma
-ad_cpu_interconnect 0x43C10000 axi_rx_clkgen
-ad_cpu_interconnect 0x43C20000 axi_rx_os_clkgen
+ad_cpu_interconnect 0x44A61000 axi_ad9371_rx_xcvr
+ad_cpu_interconnect 0x43C10000 axi_ad9371_rx_clkgen
 ad_cpu_interconnect 0x44A91000 axi_ad9371_rx_jesd
-ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9371_rx_dma
+ad_cpu_interconnect 0x44A62000 axi_ad9371_rx_os_xcvr
+ad_cpu_interconnect 0x43C20000 axi_ad9371_rx_os_clkgen
+ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd
 ad_cpu_interconnect 0x7c440000 axi_ad9371_rx_os_dma
 
 # gt uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_rx_xcvr/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_rx_os_xcvr/m_axi
 
 # interconnect (mem/dac)
 
@@ -365,22 +273,6 @@ ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
 ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_dma/m_dest_axi
 ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_os_dma/m_dest_axi
 
-ad_disconnect sys_cpu_resetn axi_hp1_interconnect/ARESETN
-ad_disconnect sys_cpu_resetn axi_hp1_interconnect/M00_ARESETN
-ad_disconnect sys_cpu_resetn axi_hp1_interconnect/S00_ARESETN
-ad_disconnect sys_cpu_resetn axi_hp2_interconnect/ARESETN
-ad_disconnect sys_cpu_resetn axi_hp2_interconnect/M00_ARESETN
-ad_disconnect sys_cpu_resetn axi_hp2_interconnect/S00_ARESETN
-ad_disconnect sys_cpu_resetn axi_hp2_interconnect/S01_ARESETN
-
-ad_connect  sys_dma_resetn axi_hp1_interconnect/ARESETN
-ad_connect  sys_dma_resetn axi_hp1_interconnect/M00_ARESETN
-ad_connect  sys_dma_resetn axi_hp1_interconnect/S00_ARESETN
-ad_connect  sys_dma_resetn axi_hp2_interconnect/ARESETN
-ad_connect  sys_dma_resetn axi_hp2_interconnect/M00_ARESETN
-ad_connect  sys_dma_resetn axi_hp2_interconnect/S00_ARESETN
-ad_connect  sys_dma_resetn axi_hp2_interconnect/S01_ARESETN
-
 # interrupts
 
 ad_cpu_interrupt ps-11 mb-11 axi_ad9371_rx_os_dma/irq
@@ -399,11 +291,11 @@ set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}]  $ila_adc
 set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
 
-ad_connect  axi_rx_clkgen/clk_0                   ila_adc/clk
-ad_connect  axi_ad9371_core/adc_data_i0           ila_adc/probe0
-ad_connect  axi_ad9371_core/adc_data_q0           ila_adc/probe1
-ad_connect  axi_ad9371_core/adc_data_i1           ila_adc/probe2
-ad_connect  axi_ad9371_core/adc_data_q1           ila_adc/probe3
+ad_connect  axi_ad9371_rx_clkgen/clk_0 ila_adc/clk
+ad_connect  axi_ad9371_core/adc_data_i0 ila_adc/probe0
+ad_connect  axi_ad9371_core/adc_data_q0 ila_adc/probe1
+ad_connect  axi_ad9371_core/adc_data_i1 ila_adc/probe2
+ad_connect  axi_ad9371_core/adc_data_q1 ila_adc/probe3
 
 set bsplit_os_adc_0 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 bsplit_os_adc_0]
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_0
@@ -425,13 +317,13 @@ set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_os_adc
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}]  $ila_os_adc
 set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_os_adc
 
-ad_connect  axi_ad9371_core/adc_os_data_i0        bsplit_os_adc_0/data
-ad_connect  axi_ad9371_core/adc_os_data_q0        bsplit_os_adc_1/data
-ad_connect  axi_rx_os_clkgen/clk_0                ila_os_adc/clk
-ad_connect  axi_ad9371_core/adc_os_valid_i0       ila_os_adc/probe0
-ad_connect  bsplit_os_adc_0/split_data_0          ila_os_adc/probe1
-ad_connect  bsplit_os_adc_0/split_data_1          ila_os_adc/probe2
-ad_connect  axi_ad9371_core/adc_os_valid_q0       ila_os_adc/probe3
-ad_connect  bsplit_os_adc_1/split_data_0          ila_os_adc/probe4
-ad_connect  bsplit_os_adc_1/split_data_1          ila_os_adc/probe5
+ad_connect  axi_ad9371_core/adc_os_data_i0 bsplit_os_adc_0/data
+ad_connect  axi_ad9371_core/adc_os_data_q0 bsplit_os_adc_1/data
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 ila_os_adc/clk
+ad_connect  axi_ad9371_core/adc_os_valid_i0 ila_os_adc/probe0
+ad_connect  bsplit_os_adc_0/split_data_0 ila_os_adc/probe1
+ad_connect  bsplit_os_adc_0/split_data_1 ila_os_adc/probe2
+ad_connect  axi_ad9371_core/adc_os_valid_q0 ila_os_adc/probe3
+ad_connect  bsplit_os_adc_1/split_data_0 ila_os_adc/probe4
+ad_connect  bsplit_os_adc_1/split_data_1 ila_os_adc/probe5
 
diff --git a/projects/adrv9371x/zc706/system_constr.xdc b/projects/adrv9371x/zc706/system_constr.xdc
index 944b90df3..f6b98aab8 100644
--- a/projects/adrv9371x/zc706/system_constr.xdc
+++ b/projects/adrv9371x/zc706/system_constr.xdc
@@ -68,13 +68,10 @@ set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports ad9371_g
 
 # clocks
 
-create_clock -name tx_ref_clk   -period  6.25 [get_ports ref_clk0_p]
-create_clock -name rx_ref_clk   -period  6.25 [get_ports ref_clk1_p]
-create_clock -name tx_div_clk   -period  6.25 [get_pins i_system_wrapper/system_i/axi_ad9371_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  6.25 [get_pins i_system_wrapper/system_i/axi_ad9371_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_ref_clk     -period  8.00 [get_ports ref_clk0_p]
+create_clock -name rx_ref_clk     -period  8.00 [get_ports ref_clk1_p]
+create_clock -name tx_div_clk     -period  8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk     -period  8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_os_div_clk  -period  8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
 
-# sync is also sampled at the cpu clock by the ip.
-
-set_false_path -from [get_cells -hier -filter {name =~ *axi_ad9371_gt*tx_ip_sync*  && IS_SEQUENTIAL}] \
-  -to [get_cells -hier -filter {name =~ *axi_ad9371_tx_jesd*sync_tx_sync*data_sync* && IS_SEQUENTIAL}]
 
diff --git a/projects/adrv9371x/zc706/system_top.v b/projects/adrv9371x/zc706/system_top.v
index c5ee99b82..ddda7293e 100644
--- a/projects/adrv9371x/zc706/system_top.v
+++ b/projects/adrv9371x/zc706/system_top.v
@@ -346,6 +346,22 @@ module system_top (
     .dio_p (gpio_bd));
 
   system_wrapper i_system_wrapper (
+    .dac_fifo_bypass (gpio_o[60]),
+    .ddr3_addr (ddr3_addr),
+    .ddr3_ba (ddr3_ba),
+    .ddr3_cas_n (ddr3_cas_n),
+    .ddr3_ck_n (ddr3_ck_n),
+    .ddr3_ck_p (ddr3_ck_p),
+    .ddr3_cke (ddr3_cke),
+    .ddr3_cs_n (ddr3_cs_n),
+    .ddr3_dm (ddr3_dm),
+    .ddr3_dq (ddr3_dq),
+    .ddr3_dqs_n (ddr3_dqs_n),
+    .ddr3_dqs_p (ddr3_dqs_p),
+    .ddr3_odt (ddr3_odt),
+    .ddr3_ras_n (ddr3_ras_n),
+    .ddr3_reset_n (ddr3_reset_n),
+    .ddr3_we_n (ddr3_we_n),
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),
     .ddr_cas_n (ddr_cas_n),
@@ -388,14 +404,20 @@ module system_top (
     .ps_intr_08 (1'b0),
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
-    .rx_n (rx_data_n[1:0]),
-    .rx_os_n (rx_data_n[3:2]),
-    .rx_os_p (rx_data_p[3:2]),
-    .rx_os_sync (rx_os_sync),
-    .rx_p (rx_data_p[1:0]),
-    .rx_ref_clk (ref_clk1),
-    .rx_sync (rx_sync),
-    .rx_sysref (sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_ref_clk_0 (ref_clk1),
+    .rx_ref_clk_2 (ref_clk1),
+    .rx_sync_0 (rx_sync),
+    .rx_sync_2 (rx_os_sync),
+    .rx_sysref_0 (sysref),
+    .rx_sysref_2 (sysref),
     .spdif (spdif),
     .spi0_clk_i (spi_clk),
     .spi0_clk_o (spi_clk),
@@ -415,30 +437,20 @@ module system_top (
     .spi1_sdi_i (1'd0),
     .spi1_sdo_i (1'd0),
     .spi1_sdo_o (),
-    .tx_n (tx_data_n),
-    .tx_p (tx_data_p),
-    .tx_ref_clk (ref_clk1),
-    .tx_sync (tx_sync),
-    .tx_sysref (sysref),
-    .dac_fifo_bypass(gpio_o[60]),
-    .sys_rst(sys_rst),
-    .sys_clk_clk_p (sys_clk_p),
     .sys_clk_clk_n (sys_clk_n),
-    .ddr3_addr (ddr3_addr),
-    .ddr3_ba (ddr3_ba),
-    .ddr3_cas_n (ddr3_cas_n),
-    .ddr3_ck_n (ddr3_ck_n),
-    .ddr3_ck_p (ddr3_ck_p),
-    .ddr3_cke (ddr3_cke),
-    .ddr3_cs_n (ddr3_cs_n),
-    .ddr3_dm (ddr3_dm),
-    .ddr3_dq (ddr3_dq),
-    .ddr3_dqs_n (ddr3_dqs_n),
-    .ddr3_dqs_p (ddr3_dqs_p),
-    .ddr3_odt (ddr3_odt),
-    .ddr3_ras_n (ddr3_ras_n),
-    .ddr3_reset_n (ddr3_reset_n),
-    .ddr3_we_n (ddr3_we_n));
+    .sys_clk_clk_p (sys_clk_p),
+    .sys_rst(sys_rst),
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
+    .tx_ref_clk_0 (ref_clk1),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (sysref));
 
 endmodule
 

From 7290bcc81aeee6ea287d1e807076679b2d1d3261 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 29 Sep 2016 11:50:48 -0400
Subject: [PATCH 544/972] hdlmake- updates

---
 library/axi_ad9371/Makefile       |  1 +
 library/axi_ad9625/Makefile       |  1 +
 projects/adrv9371x/zc706/Makefile | 12 ++++++------
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/library/axi_ad9371/Makefile b/library/axi_ad9371/Makefile
index 3dd9fb20c..e27d4464c 100644
--- a/library/axi_ad9371/Makefile
+++ b/library/axi_ad9371/Makefile
@@ -25,6 +25,7 @@ M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_adc_channel.v
 M_DEPS += ../common/up_dac_common.v
 M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
 M_DEPS += axi_ad9371_if.v
 M_DEPS += axi_ad9371_rx_channel.v
 M_DEPS += axi_ad9371_rx.v
diff --git a/library/axi_ad9625/Makefile b/library/axi_ad9625/Makefile
index cae11d228..d8ff97721 100644
--- a/library/axi_ad9625/Makefile
+++ b/library/axi_ad9625/Makefile
@@ -19,6 +19,7 @@ M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_adc_channel.v
 M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../common/ad_xcvr_rx_if.v
 M_DEPS += axi_ad9625_pnmon.v
 M_DEPS += axi_ad9625_channel.v
 M_DEPS += axi_ad9625_if.v
diff --git a/projects/adrv9371x/zc706/Makefile b/projects/adrv9371x/zc706/Makefile
index 31f8999fe..f2145cd19 100644
--- a/projects/adrv9371x/zc706/Makefile
+++ b/projects/adrv9371x/zc706/Makefile
@@ -20,15 +20,15 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -59,15 +59,15 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9371 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/xilinx/axi_dacfifo clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_bsplit clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_upack clean
 
 
@@ -78,15 +78,15 @@ adrv9371x_zc706.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9371
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/xilinx/axi_dacfifo
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_bsplit
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_upack
 
 ####################################################################################

From c072c2f89ae5fa3681faabce162b6e09988b7a63 Mon Sep 17 00:00:00 2001
From: Costina <Adrian.Costina@analog.com>
Date: Fri, 30 Sep 2016 17:13:51 +0300
Subject: [PATCH 545/972] util_clkdiv: Add IP

---
 library/Makefile                       |  2 +
 library/util_clkdiv/Makefile           | 46 ++++++++++++++++++
 library/util_clkdiv/util_clkdiv.v      | 64 ++++++++++++++++++++++++++
 library/util_clkdiv/util_clkdiv_ip.tcl | 10 ++++
 4 files changed, 122 insertions(+)
 create mode 100644 library/util_clkdiv/Makefile
 create mode 100644 library/util_clkdiv/util_clkdiv.v
 create mode 100644 library/util_clkdiv/util_clkdiv_ip.tcl

diff --git a/library/Makefile b/library/Makefile
index 358764b35..ae0d5eb7a 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -57,6 +57,7 @@ clean:
 	make -C util_axis_resize clean
 	make -C util_bsplit clean
 	make -C util_ccat clean
+	make -C util_clkdiv clean
 	make -C util_cpack clean
 	make -C util_dacfifo clean
 	make -C util_gmii_to_rgmii clean
@@ -129,6 +130,7 @@ lib:
 	-make -C util_axis_resize
 	-make -C util_bsplit
 	-make -C util_ccat
+	-make -C util_clkdiv
 	-make -C util_cpack
 	-make -C util_dacfifo
 	-make -C util_gmii_to_rgmii
diff --git a/library/util_clkdiv/Makefile b/library/util_clkdiv/Makefile
new file mode 100644
index 000000000..b80a36fd4
--- /dev/null
+++ b/library/util_clkdiv/Makefile
@@ -0,0 +1,46 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := util_clkdiv_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += util_clkdiv.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: util_clkdiv.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+util_clkdiv.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) util_clkdiv_ip.tcl  >> util_clkdiv_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v
new file mode 100644
index 000000000..712375621
--- /dev/null
+++ b/library/util_clkdiv/util_clkdiv.v
@@ -0,0 +1,64 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_clkdiv (
+	clk,
+	clk_out
+ );
+
+  input   clk;
+  output  clk_out;
+  
+  BUFR #(
+    .BUFR_DIVIDE("4"),
+    .SIM_DEVICE("7SERIES")
+  ) clk_divide (
+    .I(clk),
+    .CE(1),
+    .CLR(0),
+    .O(clk_div_s));
+   
+  BUFG i_div_clk_gbuf (
+    .I (clk_div_s),
+    .O (clk_out));
+
+endmodule  // util_clkdiv
+
diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl
new file mode 100644
index 000000000..66286de2a
--- /dev/null
+++ b/library/util_clkdiv/util_clkdiv_ip.tcl
@@ -0,0 +1,10 @@
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+ 
+adi_ip_create util_clkdiv
+adi_ip_files util_clkdiv [list \
+"util_clkdiv.v" ]
+ 
+adi_ip_properties_lite util_clkdiv
+ 
+ipx::save_core [ipx::current_core]

From 0ded52d8f6358d0fd2ebe0c8f0ba3aefa61a655b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 10:50:10 -0400
Subject: [PATCH 546/972] daq2/zcu102- kcu105 copy

---
 projects/daq2/zcu102/Makefile           |  87 ++++++
 projects/daq2/zcu102/system_bd.tcl      |  15 +
 projects/daq2/zcu102/system_constr.xdc  |  72 +++++
 projects/daq2/zcu102/system_project.tcl |  16 +
 projects/daq2/zcu102/system_top.v       | 369 ++++++++++++++++++++++++
 5 files changed, 559 insertions(+)
 create mode 100644 projects/daq2/zcu102/Makefile
 create mode 100644 projects/daq2/zcu102/system_bd.tcl
 create mode 100644 projects/daq2/zcu102/system_constr.xdc
 create mode 100644 projects/daq2/zcu102/system_project.tcl
 create mode 100644 projects/daq2/zcu102/system_top.v

diff --git a/projects/daq2/zcu102/Makefile b/projects/daq2/zcu102/Makefile
new file mode 100644
index 000000000..30c090bd7
--- /dev/null
+++ b/projects/daq2/zcu102/Makefile
@@ -0,0 +1,87 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/daq2_spi.v
+M_DEPS += ../common/daq2_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
+M_DEPS += ../../common/xilinx/sys_adcfifo.tcl
+M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
+M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib daq2_kcu105.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9144 clean
+	make -C ../../../library/axi_ad9680 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/xilinx/util_adxcvr clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_dacfifo clean
+	make -C ../../../library/util_upack clean
+
+
+daq2_kcu105.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> daq2_kcu105_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9144
+	make -C ../../../library/axi_ad9680
+	make -C ../../../library/xilinx/axi_adxcvr
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/util_adcfifo
+	make -C ../../../library/xilinx/util_adxcvr
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_dacfifo
+	make -C ../../../library/util_upack
+
+####################################################################################
+####################################################################################
diff --git a/projects/daq2/zcu102/system_bd.tcl b/projects/daq2/zcu102/system_bd.tcl
new file mode 100644
index 000000000..7b40605ee
--- /dev/null
+++ b/projects/daq2/zcu102/system_bd.tcl
@@ -0,0 +1,15 @@
+
+source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
+source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
+
+p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
+p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
+
+source ../common/daq2_bd.tcl
+
+set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $util_daq2_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq2_xcvr
+set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq2_xcvr
+
+
diff --git a/projects/daq2/zcu102/system_constr.xdc b/projects/daq2/zcu102/system_constr.xdc
new file mode 100644
index 000000000..ac806dd2d
--- /dev/null
+++ b/projects/daq2/zcu102/system_constr.xdc
@@ -0,0 +1,72 @@
+
+# daq2
+
+set_property  -dict {PACKAGE_PIN  H6} [get_ports rx_ref_clk_p]                                              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  H5} [get_ports rx_ref_clk_n]                                              ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  G9  IOSTANDARD LVDS} [get_ports rx_sync_p]                                ; ## D08  FMC_HPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  F9  IOSTANDARD LVDS} [get_ports rx_sync_n]                                ; ## D09  FMC_HPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  A13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p]       ; ## G09  FMC_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  A12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n]       ; ## G10  FMC_HPC_LA03_N
+
+set_property  -dict {PACKAGE_PIN  K6} [get_ports tx_ref_clk_p]                                              ; ## D04  FMC_HPC_GBTCLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  K5} [get_ports tx_ref_clk_n]                                              ; ## D05  FMC_HPC_GBTCLK0_M2C_N
+set_property  -dict {PACKAGE_PIN  K10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p]         ; ## H07  FMC_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  J10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n]         ; ## H08  FMC_HPC_LA02_N
+set_property  -dict {PACKAGE_PIN  L12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p]       ; ## H10  FMC_HPC_LA04_P
+set_property  -dict {PACKAGE_PIN  K12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n]       ; ## H11  FMC_HPC_LA04_N
+
+set_property  -dict {PACKAGE_PIN  L13 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk]                          ; ## D11  FMC_HPC_LA05_P
+set_property  -dict {PACKAGE_PIN  L8  IOSTANDARD LVCMOS18} [get_ports spi_csn_dac]                          ; ## C14  FMC_HPC_LA10_P
+set_property  -dict {PACKAGE_PIN  H9  IOSTANDARD LVCMOS18} [get_ports spi_csn_adc]                          ; ## D15  FMC_HPC_LA09_N
+set_property  -dict {PACKAGE_PIN  K13 IOSTANDARD LVCMOS18} [get_ports spi_clk]                              ; ## D12  FMC_HPC_LA05_N
+set_property  -dict {PACKAGE_PIN  J9  IOSTANDARD LVCMOS18} [get_ports spi_sdio]                             ; ## D14  FMC_HPC_LA09_P
+set_property  -dict {PACKAGE_PIN  H8  IOSTANDARD LVCMOS18} [get_ports spi_dir]                              ; ## G13  FMC_HPC_LA08_N
+
+set_property  -dict {PACKAGE_PIN  J8  IOSTANDARD LVCMOS18} [get_ports clkd_sync]                            ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  K8  IOSTANDARD LVCMOS18} [get_ports dac_reset]                            ; ## C15  FMC_HPC_LA10_N
+set_property  -dict {PACKAGE_PIN  D10 IOSTANDARD LVCMOS18} [get_ports dac_txen]                             ; ## G16  FMC_HPC_LA12_N
+set_property  -dict {PACKAGE_PIN  D13 IOSTANDARD LVCMOS18} [get_ports adc_pd]                               ; ## C10  FMC_HPC_LA06_P
+
+set_property  -dict {PACKAGE_PIN  D9  IOSTANDARD LVCMOS18} [get_ports clkd_status[0]]                       ; ## D17  FMC_HPC_LA13_P
+set_property  -dict {PACKAGE_PIN  C9  IOSTANDARD LVCMOS18} [get_ports clkd_status[1]]                       ; ## D18  FMC_HPC_LA13_N
+set_property  -dict {PACKAGE_PIN  E10 IOSTANDARD LVCMOS18} [get_ports dac_irq]                              ; ## G15  FMC_HPC_LA12_P
+set_property  -dict {PACKAGE_PIN  K11 IOSTANDARD LVCMOS18} [get_ports adc_fda]                              ; ## H16  FMC_HPC_LA11_P
+set_property  -dict {PACKAGE_PIN  J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb]                              ; ## H17  FMC_HPC_LA11_N
+
+set_property  -dict {PACKAGE_PIN  F8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p]            ; ## H13  FMC_HPC_LA07_P          
+set_property  -dict {PACKAGE_PIN  E8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n]            ; ## H14  FMC_HPC_LA07_N          
+
+# clocks
+
+create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
+create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
+
+# gt pin assignments below are for reference only and are ignored by the tool!
+
+##  set_property  -dict {PACKAGE_PIN  A4} [get_ports rx_data_p[0]] ; ## A10  FMC_HPC_DP3_M2C_P
+##  set_property  -dict {PACKAGE_PIN  A3} [get_ports rx_data_n[0]] ; ## A11  FMC_HPC_DP3_M2C_N
+##  set_property  -dict {PACKAGE_PIN  E4} [get_ports rx_data_p[1]] ; ## C06  FMC_HPC_DP0_M2C_P
+##  set_property  -dict {PACKAGE_PIN  E3} [get_ports rx_data_n[1]] ; ## C07  FMC_HPC_DP0_M2C_N
+##  set_property  -dict {PACKAGE_PIN  B2} [get_ports rx_data_p[2]] ; ## A06  FMC_HPC_DP2_M2C_P
+##  set_property  -dict {PACKAGE_PIN  B1} [get_ports rx_data_n[2]] ; ## A07  FMC_HPC_DP2_M2C_N
+##  set_property  -dict {PACKAGE_PIN  D2} [get_ports rx_data_p[3]] ; ## A02  FMC_HPC_DP1_M2C_P
+##  set_property  -dict {PACKAGE_PIN  D1} [get_ports rx_data_n[3]] ; ## A03  FMC_HPC_DP1_M2C_N
+##  set_property  -dict {PACKAGE_PIN  B6} [get_ports tx_data_p[0]] ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[0])
+##  set_property  -dict {PACKAGE_PIN  B5} [get_ports tx_data_n[0]] ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[0])
+##  set_property  -dict {PACKAGE_PIN  F6} [get_ports tx_data_p[1]] ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[3])
+##  set_property  -dict {PACKAGE_PIN  F5} [get_ports tx_data_n[1]] ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[3])
+##  set_property  -dict {PACKAGE_PIN  C4} [get_ports tx_data_p[2]] ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[1])
+##  set_property  -dict {PACKAGE_PIN  C3} [get_ports tx_data_n[2]] ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[1])
+##  set_property  -dict {PACKAGE_PIN  D6} [get_ports tx_data_p[3]] ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
+##  set_property  -dict {PACKAGE_PIN  D5} [get_ports tx_data_n[3]] ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
+
+set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_1/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9144_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9680_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
diff --git a/projects/daq2/zcu102/system_project.tcl b/projects/daq2/zcu102/system_project.tcl
new file mode 100644
index 000000000..ad3fad935
--- /dev/null
+++ b/projects/daq2/zcu102/system_project.tcl
@@ -0,0 +1,16 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create daq2_kcu105
+adi_project_files daq2_kcu105 [list \
+  "../common/daq2_spi.v" \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
+
+adi_project_run daq2_kcu105
+
+
diff --git a/projects/daq2/zcu102/system_top.v b/projects/daq2/zcu102/system_top.v
new file mode 100644
index 000000000..4af3f1aa8
--- /dev/null
+++ b/projects/daq2/zcu102/system_top.v
@@ -0,0 +1,369 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  sys_rst,
+  sys_clk_p,
+  sys_clk_n,
+
+  uart_sin,
+  uart_sout,
+
+  ddr4_act_n,
+  ddr4_addr,
+  ddr4_ba,
+  ddr4_bg,
+  ddr4_ck_p,
+  ddr4_ck_n,
+  ddr4_cke,
+  ddr4_cs_n,
+  ddr4_dm_n,
+  ddr4_dq,
+  ddr4_dqs_p,
+  ddr4_dqs_n,
+  ddr4_odt,
+  ddr4_reset_n,
+
+  mdio_mdc,
+  mdio_mdio,
+  phy_clk_p,
+  phy_clk_n,
+  phy_rst_n,
+  phy_rx_p,
+  phy_rx_n,
+  phy_tx_p,
+  phy_tx_n,
+
+  fan_pwm,
+
+  gpio_bd,
+
+  iic_scl,
+  iic_sda,
+
+  rx_ref_clk_p,
+  rx_ref_clk_n,
+  rx_sysref_p,
+  rx_sysref_n,
+  rx_sync_p,
+  rx_sync_n,
+  rx_data_p,
+  rx_data_n,
+
+  tx_ref_clk_p,
+  tx_ref_clk_n,
+  tx_sysref_p,
+  tx_sysref_n,
+  tx_sync_p,
+  tx_sync_n,
+  tx_data_p,
+  tx_data_n,
+
+  trig_p,
+  trig_n,
+
+  adc_fdb,
+  adc_fda,
+  dac_irq,
+  clkd_status,
+
+  adc_pd,
+  dac_txen,
+  dac_reset,
+  clkd_sync,
+
+  spi_csn_clk,
+  spi_csn_dac,
+  spi_csn_adc,
+  spi_clk,
+  spi_sdio,
+  spi_dir);
+
+  input           sys_rst;
+  input           sys_clk_p;
+  input           sys_clk_n;
+
+  input           uart_sin;
+  output          uart_sout;
+
+  output          ddr4_act_n;
+  output  [16:0]  ddr4_addr;
+  output  [ 1:0]  ddr4_ba;
+  output  [ 0:0]  ddr4_bg;
+  output          ddr4_ck_p;
+  output          ddr4_ck_n;
+  output  [ 0:0]  ddr4_cke;
+  output  [ 0:0]  ddr4_cs_n;
+  inout   [ 7:0]  ddr4_dm_n;
+  inout   [63:0]  ddr4_dq;
+  inout   [ 7:0]  ddr4_dqs_p;
+  inout   [ 7:0]  ddr4_dqs_n;
+  output  [ 0:0]  ddr4_odt;
+  output          ddr4_reset_n;
+
+  output          mdio_mdc;
+  inout           mdio_mdio;
+  input           phy_clk_p;
+  input           phy_clk_n;
+  output          phy_rst_n;
+  input           phy_rx_p;
+  input           phy_rx_n;
+  output          phy_tx_p;
+  output          phy_tx_n;
+
+  output          fan_pwm;
+
+  inout   [16:0]  gpio_bd;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  input           rx_ref_clk_p;
+  input           rx_ref_clk_n;
+  input           rx_sysref_p;
+  input           rx_sysref_n;
+  output          rx_sync_p;
+  output          rx_sync_n;
+  input   [ 3:0]  rx_data_p;
+  input   [ 3:0]  rx_data_n;
+
+  input           tx_ref_clk_p;
+  input           tx_ref_clk_n;
+  input           tx_sysref_p;
+  input           tx_sysref_n;
+  input           tx_sync_p;
+  input           tx_sync_n;
+  output  [ 3:0]  tx_data_p;
+  output  [ 3:0]  tx_data_n;
+
+  input           trig_p;
+  input           trig_n;
+
+  inout           adc_fdb;
+  inout           adc_fda;
+  inout           dac_irq;
+  inout   [ 1:0]  clkd_status;
+
+  inout           adc_pd;
+  inout           dac_txen;
+  inout           dac_reset;
+  inout           clkd_sync;
+
+  output          spi_csn_clk;
+  output          spi_csn_dac;
+  output          spi_csn_adc;
+  output          spi_clk;
+  inout           spi_sdio;
+  output          spi_dir;
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire    [ 7:0]  spi_csn;
+  wire            spi_mosi;
+  wire            spi_miso;
+  wire            trig;
+  wire            rx_ref_clk;
+  wire            rx_sysref;
+  wire            rx_sync;
+  wire            tx_ref_clk;
+  wire            tx_sysref;
+  wire            tx_sync;
+
+  // spi
+
+  assign spi_csn_adc = spi_csn[2];
+  assign spi_csn_dac = spi_csn[1];
+  assign spi_csn_clk = spi_csn[0];
+
+  // default logic
+
+  assign fan_pwm = 1'b1;
+
+  // instantiations
+
+  IBUFDS_GTE3 i_ibufds_rx_ref_clk (
+    .CEB (1'd0),
+    .I (rx_ref_clk_p),
+    .IB (rx_ref_clk_n),
+    .O (rx_ref_clk),
+    .ODIV2 ());
+
+  IBUFDS i_ibufds_rx_sysref (
+    .I (rx_sysref_p),
+    .IB (rx_sysref_n),
+    .O (rx_sysref));
+
+  OBUFDS i_obufds_rx_sync (
+    .I (rx_sync),
+    .O (rx_sync_p),
+    .OB (rx_sync_n));
+
+  IBUFDS_GTE3 i_ibufds_tx_ref_clk (
+    .CEB (1'd0),
+    .I (tx_ref_clk_p),
+    .IB (tx_ref_clk_n),
+    .O (tx_ref_clk),
+    .ODIV2 ());
+
+  IBUFDS i_ibufds_tx_sysref (
+    .I (tx_sysref_p),
+    .IB (tx_sysref_n),
+    .O (tx_sysref));
+
+  IBUFDS i_ibufds_tx_sync (
+    .I (tx_sync_p),
+    .IB (tx_sync_n),
+    .O (tx_sync));
+
+  daq2_spi i_spi (
+    .spi_csn (spi_csn[2:0]),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_sdio (spi_sdio),
+    .spi_dir (spi_dir));
+
+  IBUFDS i_ibufds_trig (
+    .I (trig_p),
+    .IB (trig_n),
+    .O (trig));
+
+  assign gpio_i[43] = trig;
+
+  ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
+    .dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
+    .dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
+    .dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
+    .dio_p ({ adc_pd,           // 42
+              dac_txen,         // 41
+              dac_reset,        // 40
+              clkd_sync,        // 38
+              adc_fdb,          // 36
+              adc_fda,          // 35
+              dac_irq,          // 34
+              clkd_status}));   // 32
+
+  ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
+    .dio_t (gpio_t[16:0]),
+    .dio_i (gpio_o[16:0]),
+    .dio_o (gpio_i[16:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .c0_ddr4_act_n (ddr4_act_n),
+    .c0_ddr4_adr (ddr4_addr),
+    .c0_ddr4_ba (ddr4_ba),
+    .c0_ddr4_bg (ddr4_bg),
+    .c0_ddr4_ck_c (ddr4_ck_n),
+    .c0_ddr4_ck_t (ddr4_ck_p),
+    .c0_ddr4_cke (ddr4_cke),
+    .c0_ddr4_cs_n (ddr4_cs_n),
+    .c0_ddr4_dm_n (ddr4_dm_n),
+    .c0_ddr4_dq (ddr4_dq),
+    .c0_ddr4_dqs_c (ddr4_dqs_n),
+    .c0_ddr4_dqs_t (ddr4_dqs_p),
+    .c0_ddr4_odt (ddr4_odt),
+    .c0_ddr4_reset_n (ddr4_reset_n),
+    .gpio0_i (gpio_i[31:0]),
+    .gpio0_o (gpio_o[31:0]),
+    .gpio0_t (gpio_t[31:0]),
+    .gpio1_i (gpio_i[63:32]),
+    .gpio1_o (gpio_o[63:32]),
+    .gpio1_t (gpio_t[63:32]),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .mb_intr_05 (1'b0),
+    .mb_intr_06 (1'b0),
+    .mb_intr_07 (1'b0),
+    .mb_intr_08 (1'b0),
+    .mb_intr_14 (1'b0),
+    .mb_intr_15 (1'b0),
+    .mdio_mdc (mdio_mdc),
+    .mdio_mdio_io (mdio_mdio),
+    .phy_clk_clk_n (phy_clk_n),
+    .phy_clk_clk_p (phy_clk_p),
+    .phy_rst_n (phy_rst_n),
+    .phy_sd (1'b1),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_ref_clk (rx_ref_clk),
+    .rx_sync (rx_sync),
+    .rx_sysref (rx_sysref),
+    .sgmii_rxn (phy_rx_n),
+    .sgmii_rxp (phy_rx_p),
+    .sgmii_txn (phy_tx_n),
+    .sgmii_txp (phy_tx_p),
+    .spi_clk_i (spi_clk),
+    .spi_clk_o (spi_clk),
+    .spi_csn_i (spi_csn),
+    .spi_csn_o (spi_csn),
+    .spi_sdi_i (spi_miso),
+    .spi_sdo_i (spi_mosi),
+    .spi_sdo_o (spi_mosi),
+    .sys_clk_clk_n (sys_clk_n),
+    .sys_clk_clk_p (sys_clk_p),
+    .sys_rst (sys_rst),
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
+    .tx_ref_clk (tx_ref_clk),
+    .tx_sync (tx_sync),
+    .tx_sysref (tx_sysref),
+    .uart_sin (uart_sin),
+    .uart_sout (uart_sout));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From e9105faae1e16bac01291a35b0f3d2de0edaee93 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 11:50:56 -0400
Subject: [PATCH 547/972] library/scripts- add beta devices

---
 library/scripts/adi_ip.tcl | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl
index c11f2a03e..f0430eff3 100644
--- a/library/scripts/adi_ip.tcl
+++ b/library/scripts/adi_ip.tcl
@@ -131,9 +131,9 @@ proc adi_ip_infer_interfaces {ip_name} {
 proc adi_ip_properties_lite {ip_name} {
 
   ipx::package_project -root_dir . \
-    -vendor {analog.com} \
-    -library {user} \
-    -taxonomy {{/AXI_Infrastructure}} 
+    -vendor analog.com \
+    -library user \
+    -taxonomy /Analog_Devices 
 
   set_property vendor_display_name {Analog Devices} [ipx::current_core]
   set_property company_url {www.analog.com} [ipx::current_core]
@@ -155,7 +155,25 @@ proc adi_ip_properties_lite {ip_name} {
     virtexu       Production
     kintexuplus   Production
     zynquplus     Production
-    kintexu       Production}\
+    kintexu       Production
+    virtex7       Beta
+    qvirtex7      Beta
+    kintex7       Beta
+    kintex7l      Beta
+    qkintex7      Beta
+    qkintex7l     Beta
+    artix7        Beta
+    artix7l       Beta
+    aartix7       Beta
+    qartix7       Beta
+    zynq          Beta 
+    qzynq         Beta
+    azynq         Beta
+    virtexu       Beta
+    virtexuplus   Beta
+    kintexuplus   Beta
+    zynquplus     Beta
+    kintexu       Beta}\
   [ipx::current_core]
 
   ipx::remove_all_bus_interface -quiet [ipx::current_core]

From 6b956066ef298e72b6ade25d5932032501d1d1fc Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 11:52:00 -0400
Subject: [PATCH 548/972] xilinx/ad_lvds*- ultrascale+

---
 library/xilinx/common/ad_lvds_in.v  | 53 +++++++++++++++++++++++++++--
 library/xilinx/common/ad_lvds_out.v | 18 ++++++++--
 2 files changed, 66 insertions(+), 5 deletions(-)

diff --git a/library/xilinx/common/ad_lvds_in.v b/library/xilinx/common/ad_lvds_in.v
index 4d53c3e0c..38d804ca2 100644
--- a/library/xilinx/common/ad_lvds_in.v
+++ b/library/xilinx/common/ad_lvds_in.v
@@ -68,8 +68,9 @@ module ad_lvds_in (
   parameter   DEVICE_TYPE = 0;
   parameter   IODELAY_CTRL = 0;
   parameter   IODELAY_GROUP = "dev_if_delay_group";
-  localparam  SERIES7 = 0;
+  localparam  VIRTEX7 = 0;
   localparam  VIRTEX6 = 1;
+  localparam  ULTRASCALE = 2;
 
   // data interface
 
@@ -101,6 +102,7 @@ module ad_lvds_in (
   wire                rx_data_n_s;
   wire                rx_data_ibuf_s;
   wire                rx_data_idelay_s;
+  wire        [ 8:0]  up_drdata_s;
 
   // delay controller
 
@@ -131,6 +133,7 @@ module ad_lvds_in (
   end
   endgenerate
 
+  generate
   if (DEVICE_TYPE == VIRTEX6) begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
   IODELAYE1 #(
@@ -157,7 +160,11 @@ module ad_lvds_in (
     .RST (up_dld),
     .CNTVALUEIN (up_dwdata),
     .CNTVALUEOUT (up_drdata));
-  end else begin
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == VIRTEX7) begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
   IDELAYE2 #(
     .CINVCTRL_SEL ("FALSE"),
@@ -182,7 +189,47 @@ module ad_lvds_in (
     .CNTVALUEIN (up_dwdata),
     .CNTVALUEOUT (up_drdata));
   end
+  endgenerate
 
+  generate
+  if (DEVICE_TYPE == ULTRASCALE) begin
+  assign up_drdata = up_drdata_s[8:4];
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYE3 #(
+    .DELAY_SRC ("IDATAIN"),
+    .DELAY_TYPE ("VAR_LOAD"),
+    .REFCLK_FREQUENCY (200.0),
+    .DELAY_FORMAT ("COUNT"))
+  i_rx_data_idelay (
+    .CASC_RETURN (1'b0),
+    .CASC_IN (1'b0),
+    .CASC_OUT (),
+    .CE (1'b0),
+    .CLK (up_clk),
+    .INC (1'b0),
+    .LOAD (up_dld),
+    .CNTVALUEIN ({up_dwdata, 4'd0}),
+    .CNTVALUEOUT (up_drdata_s),
+    .DATAIN (1'b0),
+    .IDATAIN (rx_data_ibuf_s),
+    .DATAOUT (rx_data_idelay_s),
+    .RST (1'b0),
+    .EN_VTC (~up_dld));
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == ULTRASCALE) begin
+  IDDRE1 #(
+    .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
+  i_rx_data_iddr (
+    .R (1'b0),
+    .C (rx_clk),
+    .CB (~rx_clk),
+    .D (rx_data_idelay_s),
+    .Q1 (rx_data_p),
+    .Q2 (rx_data_n_s));
+  end else begin
   IDDR #(
     .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
     .INIT_Q1 (1'b0),
@@ -196,6 +243,8 @@ module ad_lvds_in (
     .D (rx_data_idelay_s),
     .Q1 (rx_data_p),
     .Q2 (rx_data_n_s));
+  end
+  endgenerate
 
   always @(posedge rx_clk) begin
     rx_data_n <= rx_data_n_s;
diff --git a/library/xilinx/common/ad_lvds_out.v b/library/xilinx/common/ad_lvds_out.v
index 5c3cdfd88..1cbc93389 100644
--- a/library/xilinx/common/ad_lvds_out.v
+++ b/library/xilinx/common/ad_lvds_out.v
@@ -67,8 +67,9 @@ module ad_lvds_out (
   parameter   IODELAY_ENABLE = 0;
   parameter   IODELAY_CTRL = 0;
   parameter   IODELAY_GROUP = "dev_if_delay_group";
-  localparam  SERIES7 = 0;
+  localparam  VIRTEX7 = 0;
   localparam  VIRTEX6 = 1;
+  localparam  ULTRASCALE = 2;
 
   // data interface
 
@@ -99,7 +100,7 @@ module ad_lvds_out (
   // delay controller
 
   generate
-  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
+  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == VIRTEX7) && (IODELAY_CTRL == 1)) begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
   IDELAYCTRL i_delay_ctrl (
     .RST (delay_rst),
@@ -112,6 +113,15 @@ module ad_lvds_out (
 
   // transmit data interface, oddr -> odelay -> obuf
 
+  generate
+  if (DEVICE_TYPE == ULTRASCALE) begin
+  ODDRE1 i_tx_data_oddr (
+    .SR (1'b0),
+    .C (tx_clk),
+    .D1 (tx_data_p),
+    .D2 (tx_data_n),
+    .Q (tx_data_oddr_s));
+  end else begin
   ODDR #(
     .DDR_CLK_EDGE ("SAME_EDGE"),
     .INIT (1'b0),
@@ -124,9 +134,11 @@ module ad_lvds_out (
     .D1 (tx_data_p),
     .D2 (tx_data_n),
     .Q (tx_data_oddr_s));
+  end
+  endgenerate
 
   generate
-  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin
+  if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == VIRTEX7)) begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
   ODELAYE2 #(
     .CINVCTRL_SEL ("FALSE"),

From 33f9ed33c7f6d5ae3b13d13b8cb1095a3fb8061c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 11:52:40 -0400
Subject: [PATCH 549/972] projects- ultrascale+

---
 projects/scripts/adi_project.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index 4aba77ace..53de82995 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -86,8 +86,8 @@ proc adi_project_create {project_name {mode 0}} {
     set sys_zynq 1
   }
   if [regexp "_zcu102$" $project_name] {
-    set p_device "xczu9eg-ffvb1156-1-i-EVAL"
-    set p_board "not-applicable"
+    set p_device "xczu9eg-ffvb1156-1-i-es1"
+    set p_board "xilinx.com:zcu102:part0:1.2"
     set sys_zynq 2
   }
 

From 9afff7ae60aef5c176b2bb9d5cb3b137fe3e41aa Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 11:53:15 -0400
Subject: [PATCH 550/972] common/zcu102- 2016.2 updates

---
 projects/common/zcu102/zcu102_system_bd.tcl | 2611 +++++++++++++++++--
 1 file changed, 2367 insertions(+), 244 deletions(-)

diff --git a/projects/common/zcu102/zcu102_system_bd.tcl b/projects/common/zcu102/zcu102_system_bd.tcl
index 07895c315..3cea2924f 100644
--- a/projects/common/zcu102/zcu102_system_bd.tcl
+++ b/projects/common/zcu102/zcu102_system_bd.tcl
@@ -36,30 +36,1276 @@ create_bd_port -dir I -type intr ps_intr_15
 
 # instance: sys_ps8
 
-set sys_ps8  [create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:1.0 sys_ps8]
+set sys_ps8  [create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:1.2 sys_ps8]
 
 # defaults -- remove after board is supported in the tool
-set_property -dict [list\
+
+set_property -dict [list \
+  CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS33} \
+  CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS33} \
+  CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS33} \
+  CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
+  CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x80000000} \
+  CONFIG.PSU_MIO_0_DIRECTION {out} \
+  CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_0_SLEW {slow} \
+  CONFIG.PSU_MIO_10_DIRECTION {inout} \
+  CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_10_SLEW {slow} \
+  CONFIG.PSU_MIO_11_DIRECTION {inout} \
+  CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_11_SLEW {slow} \
+  CONFIG.PSU_MIO_12_DIRECTION {out} \
+  CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_12_SLEW {slow} \
+  CONFIG.PSU_MIO_13_DIRECTION {inout} \
+  CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_13_SLEW {slow} \
+  CONFIG.PSU_MIO_14_DIRECTION {inout} \
+  CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_14_SLEW {slow} \
+  CONFIG.PSU_MIO_15_DIRECTION {inout} \
+  CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_15_SLEW {slow} \
+  CONFIG.PSU_MIO_16_DIRECTION {inout} \
+  CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_16_SLEW {slow} \
+  CONFIG.PSU_MIO_17_DIRECTION {inout} \
+  CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_17_SLEW {slow} \
+  CONFIG.PSU_MIO_18_DIRECTION {in} \
+  CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_18_SLEW {slow} \
+  CONFIG.PSU_MIO_19_DIRECTION {out} \
+  CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_19_SLEW {slow} \
+  CONFIG.PSU_MIO_1_DIRECTION {inout} \
+  CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_1_SLEW {slow} \
+  CONFIG.PSU_MIO_20_DIRECTION {out} \
+  CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_20_SLEW {slow} \
+  CONFIG.PSU_MIO_21_DIRECTION {in} \
+  CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_21_SLEW {slow} \
+  CONFIG.PSU_MIO_22_DIRECTION {inout} \
+  CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_22_SLEW {slow} \
+  CONFIG.PSU_MIO_23_DIRECTION {inout} \
+  CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_23_SLEW {slow} \
+  CONFIG.PSU_MIO_24_DIRECTION {out} \
+  CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_24_SLEW {slow} \
+  CONFIG.PSU_MIO_25_DIRECTION {in} \
+  CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_25_SLEW {slow} \
+  CONFIG.PSU_MIO_26_DIRECTION {inout} \
+  CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_26_SLEW {slow} \
+  CONFIG.PSU_MIO_27_DIRECTION {inout} \
+  CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_27_SLEW {slow} \
+  CONFIG.PSU_MIO_28_DIRECTION {inout} \
+  CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_28_SLEW {slow} \
+  CONFIG.PSU_MIO_29_DIRECTION {inout} \
+  CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_29_SLEW {slow} \
+  CONFIG.PSU_MIO_2_DIRECTION {inout} \
+  CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_2_SLEW {slow} \
+  CONFIG.PSU_MIO_30_DIRECTION {inout} \
+  CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_30_SLEW {slow} \
+  CONFIG.PSU_MIO_31_DIRECTION {out} \
+  CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_31_SLEW {slow} \
+  CONFIG.PSU_MIO_32_DIRECTION {inout} \
+  CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_32_SLEW {slow} \
+  CONFIG.PSU_MIO_33_DIRECTION {inout} \
+  CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_33_SLEW {slow} \
+  CONFIG.PSU_MIO_34_DIRECTION {inout} \
+  CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_34_SLEW {slow} \
+  CONFIG.PSU_MIO_35_DIRECTION {inout} \
+  CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_35_SLEW {slow} \
+  CONFIG.PSU_MIO_36_DIRECTION {inout} \
+  CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_36_SLEW {slow} \
+  CONFIG.PSU_MIO_37_DIRECTION {inout} \
+  CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_37_SLEW {slow} \
+  CONFIG.PSU_MIO_38_DIRECTION {inout} \
+  CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_38_SLEW {slow} \
+  CONFIG.PSU_MIO_39_DIRECTION {inout} \
+  CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_39_SLEW {slow} \
+  CONFIG.PSU_MIO_3_DIRECTION {inout} \
+  CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_3_SLEW {slow} \
+  CONFIG.PSU_MIO_40_DIRECTION {inout} \
+  CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_40_SLEW {slow} \
+  CONFIG.PSU_MIO_41_DIRECTION {inout} \
+  CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_41_SLEW {slow} \
+  CONFIG.PSU_MIO_42_DIRECTION {inout} \
+  CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_42_SLEW {slow} \
+  CONFIG.PSU_MIO_43_DIRECTION {out} \
+  CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_43_SLEW {slow} \
+  CONFIG.PSU_MIO_44_DIRECTION {in} \
+  CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_44_SLEW {slow} \
+  CONFIG.PSU_MIO_45_DIRECTION {in} \
+  CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_45_SLEW {slow} \
+  CONFIG.PSU_MIO_46_DIRECTION {inout} \
+  CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_46_SLEW {slow} \
+  CONFIG.PSU_MIO_47_DIRECTION {inout} \
+  CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_47_SLEW {slow} \
+  CONFIG.PSU_MIO_48_DIRECTION {inout} \
+  CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_48_SLEW {slow} \
+  CONFIG.PSU_MIO_49_DIRECTION {inout} \
+  CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_49_SLEW {slow} \
+  CONFIG.PSU_MIO_4_DIRECTION {inout} \
+  CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_4_SLEW {slow} \
+  CONFIG.PSU_MIO_50_DIRECTION {inout} \
+  CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_50_SLEW {slow} \
+  CONFIG.PSU_MIO_51_DIRECTION {out} \
+  CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_51_SLEW {slow} \
+  CONFIG.PSU_MIO_52_DIRECTION {in} \
+  CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_52_SLEW {slow} \
+  CONFIG.PSU_MIO_53_DIRECTION {in} \
+  CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_53_SLEW {slow} \
+  CONFIG.PSU_MIO_54_DIRECTION {inout} \
+  CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_54_SLEW {slow} \
+  CONFIG.PSU_MIO_55_DIRECTION {in} \
+  CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_55_SLEW {slow} \
+  CONFIG.PSU_MIO_56_DIRECTION {inout} \
+  CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_56_SLEW {slow} \
+  CONFIG.PSU_MIO_57_DIRECTION {inout} \
+  CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_57_SLEW {slow} \
+  CONFIG.PSU_MIO_58_DIRECTION {out} \
+  CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_58_SLEW {slow} \
+  CONFIG.PSU_MIO_59_DIRECTION {inout} \
+  CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_59_SLEW {slow} \
+  CONFIG.PSU_MIO_5_DIRECTION {out} \
+  CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_5_SLEW {slow} \
+  CONFIG.PSU_MIO_60_DIRECTION {inout} \
+  CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_60_SLEW {slow} \
+  CONFIG.PSU_MIO_61_DIRECTION {inout} \
+  CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_61_SLEW {slow} \
+  CONFIG.PSU_MIO_62_DIRECTION {inout} \
+  CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_62_SLEW {slow} \
+  CONFIG.PSU_MIO_63_DIRECTION {inout} \
+  CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_63_SLEW {slow} \
+  CONFIG.PSU_MIO_64_DIRECTION {out} \
+  CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_64_SLEW {slow} \
+  CONFIG.PSU_MIO_65_DIRECTION {out} \
+  CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_65_SLEW {slow} \
+  CONFIG.PSU_MIO_66_DIRECTION {out} \
+  CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_66_SLEW {slow} \
+  CONFIG.PSU_MIO_67_DIRECTION {out} \
+  CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_67_SLEW {slow} \
+  CONFIG.PSU_MIO_68_DIRECTION {out} \
+  CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_68_SLEW {slow} \
+  CONFIG.PSU_MIO_69_DIRECTION {out} \
+  CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_69_SLEW {slow} \
+  CONFIG.PSU_MIO_6_DIRECTION {out} \
+  CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_6_SLEW {slow} \
+  CONFIG.PSU_MIO_70_DIRECTION {in} \
+  CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_70_SLEW {slow} \
+  CONFIG.PSU_MIO_71_DIRECTION {in} \
+  CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_71_SLEW {slow} \
+  CONFIG.PSU_MIO_72_DIRECTION {in} \
+  CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_72_SLEW {slow} \
+  CONFIG.PSU_MIO_73_DIRECTION {in} \
+  CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_73_SLEW {slow} \
+  CONFIG.PSU_MIO_74_DIRECTION {in} \
+  CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_74_SLEW {slow} \
+  CONFIG.PSU_MIO_75_DIRECTION {in} \
+  CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_75_SLEW {slow} \
+  CONFIG.PSU_MIO_76_DIRECTION {out} \
+  CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_76_SLEW {slow} \
+  CONFIG.PSU_MIO_77_DIRECTION {inout} \
+  CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_77_SLEW {slow} \
+  CONFIG.PSU_MIO_7_DIRECTION {out} \
+  CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_7_SLEW {slow} \
+  CONFIG.PSU_MIO_8_DIRECTION {inout} \
+  CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_8_SLEW {slow} \
+  CONFIG.PSU_MIO_9_DIRECTION {inout} \
+  CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
+  CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \
+  CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
+  CONFIG.PSU_MIO_9_SLEW {slow} \
+  CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PCIE#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
+  CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#so_mo1#mo2#mo3#si_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#reset_n#gpio1[32]#gpio1[33]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \
+  CONFIG.PSU_PACKAGE_DDR_BOARD_DELAY3 {0.100} \
+  CONFIG.PSU_PRESET_BANK0_VOLTAGE {<Select>} \
+  CONFIG.PSU_PRESET_BANK1_VOLTAGE {<Select>} \
+  CONFIG.PSU_UIPARAM_GENERATE_SUMMARY {<Select>} \
+  CONFIG.PSU__ACPU0__POWER__ON {1} \
+  CONFIG.PSU__ACPU1__POWER__ON {1} \
+  CONFIG.PSU__ACPU2__POWER__ON {1} \
+  CONFIG.PSU__ACPU3__POWER__ON {1} \
+  CONFIG.PSU__ACT_DDR_FREQ_MHZ {1} \
+  CONFIG.PSU__ADMA_COHERENCY {1} \
+  CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
+  CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
+  CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
+  CONFIG.PSU__CAN0__GRP_CLK__IO {<Select>} \
+  CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__CAN0__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+  CONFIG.PSU__CAN1__GRP_CLK__IO {<Select>} \
   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+  CONFIG.PSU__CPU_CPU_6X4X_MAX_RANGE {1} \
+  CONFIG.PSU__CPU_R5__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1099.989014} \
+  CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+  CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+  CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__ACPU__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
+  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
+  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
+  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
+  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
+  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
+  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {66} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+  CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
+  CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
+  CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
+  CONFIG.PSU__CRF_APB__APM_CTRL__SRCSEL {<Select>} \
+  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \
+  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__DBG_FPD__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {249.997498} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__DIVISOR0 {10} \
+  CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__DIVISOR0 {5} \
+  CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__DIVISOR0 {5} \
+  CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__DIVISOR0 {4} \
+  CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {549.994507} \
+  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__DPDMA__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__SRCSEL {DPLL} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {39} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {27.000} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {17} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {269.997} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {320} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {549.994507} \
+  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+  CONFIG.PSU__CRF_APB__GDMA__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.994995} \
+  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__GPU__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {124.998749} \
+  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {4} \
+  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {125} \
+  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {249.997498} \
+  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \
+  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {479.228546} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN__ENABLE {1} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {57} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.508} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+  CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__SRCSEL {VPLL} \
+  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \
+  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__ADMA__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {499.995} \
+  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {2} \
+  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
+  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {20} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__AMS__ENABLE {0} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {99.999} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \
+  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {399.996012} \
+  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {500} \
+  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \
+  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__DBG_LPD__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
+  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
+  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500} \
+  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
+  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {124.999} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {124.999} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {124.999} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {216.664} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+  CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {99.999} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {199.998006} \
+  CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__PCAP__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__ACT_FREQMHZ {1300} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__DIVISOR0 {32} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__FREQMHZ {1300} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__ACT_FREQMHZ {1300} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__DIVISOR0 {1} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__FREQMHZ {1300} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__ACT_FREQMHZ {300} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__DIVISOR0 {1} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__FREQMHZ {300} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {324.997} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {400} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {324.997} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {400} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {324.997} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {400} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {72} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+  CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+  CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+  CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {185.712} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {199.998006} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {185.712} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {185.712} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP__ENABLE {1} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.998999} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.997} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+  CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+  CONFIG.PSU__CRYSTAL__PERIPHERAL__FREQMHZ {33.333} \
+  CONFIG.PSU__CSU_COHERENCY {1} \
+  CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_0__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_10__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_11__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_12__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_1__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_2__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_3__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_4__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_5__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_6__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_7__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_8__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
+  CONFIG.PSU__CSU__CSU_TAMPER_9__RESPONSE {<Select>} \
+  CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__CSU__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__DAP_COHERENCY {1} \
+  CONFIG.PSU__DDRC__ADDR_MIRROR {NA} \
+  CONFIG.PSU__DDRC__AL {0} \
+  CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+  CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \
+  CONFIG.PSU__DDRC__BL {8} \
+  CONFIG.PSU__DDRC__BOARD_DELAY0 {1} \
+  CONFIG.PSU__DDRC__BOARD_DELAY1 {1} \
+  CONFIG.PSU__DDRC__BOARD_DELAY2 {1} \
+  CONFIG.PSU__DDRC__BOARD_DELAY3 {1} \
+  CONFIG.PSU__DDRC__BRC_MAPPING {0} \
+  CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+  CONFIG.PSU__DDRC__CL {15} \
+  CONFIG.PSU__DDRC__CLOCK_0_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__CLOCK_0_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__CLOCK_0_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__CLOCK_1_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__CLOCK_1_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__CLOCK_1_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__CLOCK_2_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__CLOCK_2_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__CLOCK_2_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__CLOCK_3_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__CLOCK_3_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__CLOCK_3_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+  CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+  CONFIG.PSU__DDRC__CWL {14} \
+  CONFIG.PSU__DDRC__DATA_MASK {1} \
+  CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+  CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+  CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+  CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
+  CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+  CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {0} \
+  CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+  CONFIG.PSU__DDRC__DERATE_INT_D {<Select>} \
+  CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+  CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+  CONFIG.PSU__DDRC__DQS_0_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__DQS_0_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__DQS_0_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__DQS_1_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__DQS_1_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__DQS_1_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__DQS_2_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__DQS_2_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__DQS_2_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__DQS_3_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__DQS_3_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__DQS_3_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_0 {0.00} \
+  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_1 {0.05} \
+  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_2 {0.10} \
+  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_3 {0.15} \
+  CONFIG.PSU__DDRC__DQ_0_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__DQ_0_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__DQ_0_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__DQ_1_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__DQ_1_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__DQ_1_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__DQ_2_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__DQ_2_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__DQ_2_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__DQ_3_LENGTH_MM {1} \
+  CONFIG.PSU__DDRC__DQ_3_PACKAGE_LENGTH {1} \
+  CONFIG.PSU__DDRC__DQ_3_PROPOGATION_DELAY {1} \
+  CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \
+  CONFIG.PSU__DDRC__ECC {0} \
+  CONFIG.PSU__DDRC__ECC_SCRUB {0} \
+  CONFIG.PSU__DDRC__ENABLE {1} \
+  CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
+  CONFIG.PSU__DDRC__FGRM {0} \
+  CONFIG.PSU__DDRC__FREQ_MHZ {1066.50} \
+  CONFIG.PSU__DDRC__HIGH_TEMP {<Select>} \
+  CONFIG.PSU__DDRC__LP_ASR {0} \
+  CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+  CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+  CONFIG.PSU__DDRC__PARTNO {<Select>} \
+  CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+  CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+  CONFIG.PSU__DDRC__PLL_BYPASS {0} \
+  CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
+  CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+  CONFIG.PSU__DDRC__RDIMM_INDICATOR {0} \
+  CONFIG.PSU__DDRC__RD_DBI_ENABLE {0} \
+  CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+  CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+  CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+  CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+  CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+  CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+  CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+  CONFIG.PSU__DDRC__T_FAW {21.0} \
+  CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+  CONFIG.PSU__DDRC__T_RC {46.5} \
+  CONFIG.PSU__DDRC__T_RCD {15} \
+  CONFIG.PSU__DDRC__T_RP {15} \
+  CONFIG.PSU__DDRC__UDIMM_INDICATOR {1} \
+  CONFIG.PSU__DDRC__USE_INTERNAL_VREF {0} \
+  CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
+  CONFIG.PSU__DDRC__VREF {1} \
+  CONFIG.PSU__DDRC__WR_DBI_ENABLE {0} \
+  CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
+  CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+  CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {<Select>} \
+  CONFIG.PSU__DISPLAYPORT__LANE0__IO {<Select>} \
+  CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {<Select>} \
+  CONFIG.PSU__DISPLAYPORT__LANE1__IO {<Select>} \
+  CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__DPAUX__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__DP__LANE_SEL {<Select>} \
+  CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
+  CONFIG.PSU__ENET0__GRP_MDIO__IO {<Select>} \
+  CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__ENET0__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
+  CONFIG.PSU__ENET1__GRP_MDIO__IO {<Select>} \
+  CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__ENET1__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
+  CONFIG.PSU__ENET2__GRP_MDIO__IO {<Select>} \
+  CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__ENET2__PERIPHERAL__IO {<Select>} \
   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
   CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+  CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+  CONFIG.PSU__FP__POWER__ON {1} \
+  CONFIG.PSU__GEM0_COHERENCY {1} \
+  CONFIG.PSU__GEM1_COHERENCY {0} \
+  CONFIG.PSU__GEM2_COHERENCY {1} \
+  CONFIG.PSU__GEM3_COHERENCY {1} \
+  CONFIG.PSU__GEM__TSU__ENABLE {0} \
+  CONFIG.PSU__GEM__TSU__IO {<Select>} \
+  CONFIG.PSU__GENERATE_SECURITY_REGISTERS {0} \
+  CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
+  CONFIG.PSU__GEN_IPI_10__MASTER {S_AXI_LPD} \
+  CONFIG.PSU__GEN_IPI_1__MASTER {RPU} \
+  CONFIG.PSU__GEN_IPI_2__MASTER {RPU} \
+  CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
+  CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
+  CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
+  CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
+  CONFIG.PSU__GEN_IPI_7__MASTER {S_AXI_HP1_FPD} \
+  CONFIG.PSU__GEN_IPI_8__MASTER {S_AXI_HP2_FPD} \
+  CONFIG.PSU__GEN_IPI_9__MASTER {S_AXI_HP3_FPD} \
   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__GPIO2_MIO__IO {<Select>} \
+  CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
+  CONFIG.PSU__GPU_PP0__POWER__ON {1} \
+  CONFIG.PSU__GPU_PP1__POWER__ON {1} \
+  CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
+  CONFIG.PSU__GT__LANE0_REF_SEL {Ref Clk0} \
+  CONFIG.PSU__GT__LANE1_REF_SEL {Ref Clk0} \
+  CONFIG.PSU__GT__LANE2_REF_SEL {Ref Clk2} \
+  CONFIG.PSU__GT__LANE3_REF_SEL {Ref Clk1} \
+  CONFIG.PSU__GT__LINK_SPEED {<Select>} \
+  CONFIG.PSU__GT__REF_SEL0 {100} \
+  CONFIG.PSU__GT__REF_SEL1 {100} \
+  CONFIG.PSU__GT__REF_SEL2 {26} \
+  CONFIG.PSU__GT__REF_SEL3 {125} \
+  CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
+  CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
+  CONFIG.PSU__I2C0__GRP_INT__IO {<Select>} \
   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
+  CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
+  CONFIG.PSU__I2C1__GRP_INT__IO {<Select>} \
   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
-  CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__L2_BANK0__POWER__ON {1} \
+  CONFIG.PSU__MAXIGP2__DATA_WIDTH {64} \
+  CONFIG.PSU__NAND_COHERENCY {1} \
+  CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
+  CONFIG.PSU__NAND__CHIP_ENABLE__IO {<Select>} \
+  CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
+  CONFIG.PSU__NAND__DATA_STROBE__IO {<Select>} \
+  CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__NAND__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
+  CONFIG.PSU__NAND__READY_BUSY__IO {<Select>} \
+  CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
+  CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
+  CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
+  CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
+  CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+  CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
+  CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
+  CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
+  CONFIG.PSU__PCIE__BAR0_64BIT {0} \
+  CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
+  CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
+  CONFIG.PSU__PCIE__BAR0_SCALE {<Select>} \
+  CONFIG.PSU__PCIE__BAR0_SIZE {<Select>} \
+  CONFIG.PSU__PCIE__BAR0_TYPE {<Select>} \
+  CONFIG.PSU__PCIE__BAR0_VAL {0x0} \
+  CONFIG.PSU__PCIE__BAR1_64BIT {0} \
+  CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
+  CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
+  CONFIG.PSU__PCIE__BAR1_SCALE {<Select>} \
+  CONFIG.PSU__PCIE__BAR1_SIZE {<Select>} \
+  CONFIG.PSU__PCIE__BAR1_TYPE {<Select>} \
+  CONFIG.PSU__PCIE__BAR1_VAL {0x0} \
+  CONFIG.PSU__PCIE__BAR2_64BIT {0} \
+  CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
+  CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
+  CONFIG.PSU__PCIE__BAR2_SCALE {<Select>} \
+  CONFIG.PSU__PCIE__BAR2_SIZE {<Select>} \
+  CONFIG.PSU__PCIE__BAR2_TYPE {<Select>} \
+  CONFIG.PSU__PCIE__BAR2_VAL {0x0} \
+  CONFIG.PSU__PCIE__BAR3_64BIT {0} \
+  CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
+  CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
+  CONFIG.PSU__PCIE__BAR3_SCALE {<Select>} \
+  CONFIG.PSU__PCIE__BAR3_SIZE {<Select>} \
+  CONFIG.PSU__PCIE__BAR3_TYPE {<Select>} \
+  CONFIG.PSU__PCIE__BAR3_VAL {0x0} \
+  CONFIG.PSU__PCIE__BAR4_64BIT {0} \
+  CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
+  CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
+  CONFIG.PSU__PCIE__BAR4_SCALE {<Select>} \
+  CONFIG.PSU__PCIE__BAR4_SIZE {<Select>} \
+  CONFIG.PSU__PCIE__BAR4_TYPE {<Select>} \
+  CONFIG.PSU__PCIE__BAR4_VAL {0x0} \
+  CONFIG.PSU__PCIE__BAR5_64BIT {0} \
+  CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
+  CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
+  CONFIG.PSU__PCIE__BAR5_SCALE {<Select>} \
+  CONFIG.PSU__PCIE__BAR5_SIZE {<Select>} \
+  CONFIG.PSU__PCIE__BAR5_TYPE {<Select>} \
+  CONFIG.PSU__PCIE__BAR5_VAL {0x0} \
+  CONFIG.PSU__PCIE__BASE_CLASS_MENU {<Select>} \
+  CONFIG.PSU__PCIE__BRIDGE_BAR_INDICATOR {<Select>} \
+  CONFIG.PSU__PCIE__CAP_SLOT_IMPLEMENTED {<Select>} \
+  CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
+  CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \
+  CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
+  CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \
+  CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
+  CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
+  CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
+  CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
+  CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
+  CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
+  CONFIG.PSU__PCIE__ECRC_CHECK {0} \
+  CONFIG.PSU__PCIE__ECRC_ERR {0} \
+  CONFIG.PSU__PCIE__ECRC_GEN {0} \
+  CONFIG.PSU__PCIE__EROM_ENABLE {0} \
+  CONFIG.PSU__PCIE__EROM_SCALE {<Select>} \
+  CONFIG.PSU__PCIE__EROM_SIZE {<Select>} \
+  CONFIG.PSU__PCIE__EROM_VAL {0x0} \
+  CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
+  CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
+  CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
+  CONFIG.PSU__PCIE__INTERFACE_WIDTH {<Select>} \
+  CONFIG.PSU__PCIE__INTX_GENERATION {0} \
+  CONFIG.PSU__PCIE__INTX_PIN {<Select>} \
+  CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
+  CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
+  CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
+  CONFIG.PSU__PCIE__LANE1__IO {<Select>} \
+  CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
+  CONFIG.PSU__PCIE__LANE2__IO {<Select>} \
+  CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
+  CONFIG.PSU__PCIE__LANE3__IO {<Select>} \
+  CONFIG.PSU__PCIE__LEGACY_INTERRUPT {<Select>} \
+  CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
+  CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \
+  CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \
+  CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
+  CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {<Select>} \
+  CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
+  CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {<Select>} \
+  CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
+  CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
+  CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
+  CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
+  CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
+  CONFIG.PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE {<Select>} \
+  CONFIG.PSU__PCIE__MULTIHEADER {0} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO {<Select>} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
+  CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
+  CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
+  CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
+  CONFIG.PSU__PCIE__REVISION_ID {0x0} \
+  CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \
+  CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \
+  CONFIG.PSU__PCIE__SUB_CLASS_INTERFACE_MENU {<Select>} \
+  CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
+  CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
+  CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
+  CONFIG.PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT {<Select>} \
+  CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \
+  CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__PJTAG__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__PL__POWER__ON {1} \
+  CONFIG.PSU__PMU_COHERENCY {1} \
+  CONFIG.PSU__PMU__EMIO_GPI__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__EMIO_GPO__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPI0__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPI0__IO {<Select>} \
+  CONFIG.PSU__PMU__GPI1__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPI1__IO {<Select>} \
+  CONFIG.PSU__PMU__GPI2__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPI2__IO {<Select>} \
+  CONFIG.PSU__PMU__GPI3__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPI3__IO {<Select>} \
+  CONFIG.PSU__PMU__GPI4__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPI4__IO {<Select>} \
+  CONFIG.PSU__PMU__GPI5__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPI5__IO {<Select>} \
+  CONFIG.PSU__PMU__GPO0__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPO0__IO {<Select>} \
+  CONFIG.PSU__PMU__GPO1__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPO1__IO {<Select>} \
+  CONFIG.PSU__PMU__GPO2__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPO2__IO {<Select>} \
+  CONFIG.PSU__PMU__GPO3__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPO3__IO {<Select>} \
+  CONFIG.PSU__PMU__GPO4__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPO4__IO {<Select>} \
+  CONFIG.PSU__PMU__GPO5__ENABLE {<Select>} \
+  CONFIG.PSU__PMU__GPO5__IO {<Select>} \
+  CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__PMU__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__ANALOG {0.004} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__DDR {0.711} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__FPD {1.163} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__LPD {0.288} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__MIO {0.161} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__PLL {0.067} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__SERDES {0.160} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__TOTAL {2.554} \
+  CONFIG.PSU__POWER_SUMMARY__ONCHIP {4.001} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__ANALOG {0.034} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__DDR {0.000} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__FPD {1.785} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__LPD {0.366} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__MIO {0.000} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__PLL {0.003} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__SERDES {0.000} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__TOTAL {1.447} \
+  CONFIG.PSU__POWER__ACPU__VCCPSINTFP {0.440} \
+  CONFIG.PSU__POWER__AFI_FPD__VCCPSINTFP {0.113} \
+  CONFIG.PSU__POWER__AFI_LPD__VCCPSINTLP {0.028} \
+  CONFIG.PSU__POWER__APLL__VCCPSPLL {0.016} \
+  CONFIG.PSU__POWER__CAN0__VCCPSIO {0} \
+  CONFIG.PSU__POWER__CAN1__VCCPSIO {0.004} \
+  CONFIG.PSU__POWER__CSU__VCCPSIO {0} \
+  CONFIG.PSU__POWER__DDR__VCCPSDDR {0.711} \
+  CONFIG.PSU__POWER__DDR__VCCPSINTFP {0} \
+  CONFIG.PSU__POWER__DPAUX__VCCPSIO {0} \
+  CONFIG.PSU__POWER__DPLL__VCCPSPLL {0} \
+  CONFIG.PSU__POWER__DP__VCCPSGTA {0.000} \
+  CONFIG.PSU__POWER__DP__VCCPSINTFP {0.000} \
+  CONFIG.PSU__POWER__FPINT__VCCPSINTFP {0.232} \
+  CONFIG.PSU__POWER__GEM0__VCCPSINTLP {0.000} \
+  CONFIG.PSU__POWER__GEM0__VCCPSIO {0} \
+  CONFIG.PSU__POWER__GEM1__VCCPSINTLP {0.000} \
+  CONFIG.PSU__POWER__GEM1__VCCPSIO {0} \
+  CONFIG.PSU__POWER__GEM2__VCCPSINTLP {0.000} \
+  CONFIG.PSU__POWER__GEM2__VCCPSIO {0} \
+  CONFIG.PSU__POWER__GEM3__VCCPSINTLP {0.006} \
+  CONFIG.PSU__POWER__GEM3__VCCPSIO {0.034} \
+  CONFIG.PSU__POWER__GPIO0__VCCPSIO {0} \
+  CONFIG.PSU__POWER__GPIO1__VCCPSIO {0} \
+  CONFIG.PSU__POWER__GPIO2__VCCPSIO {0} \
+  CONFIG.PSU__POWER__GPU__VCCPSINTFP {0.318} \
+  CONFIG.PSU__POWER__IOPLL__VCCPSPLL {0.018} \
+  CONFIG.PSU__POWER__LPINT__VCCPSINTLP {0.115} \
+  CONFIG.PSU__POWER__NAND__VCCPSINTLP {0.000} \
+  CONFIG.PSU__POWER__NAND__VCCPSIO {0} \
+  CONFIG.PSU__POWER__PCIE__VCCPSGTA {0.043} \
+  CONFIG.PSU__POWER__PCIE__VCCPSINTFP {0.014} \
+  CONFIG.PSU__POWER__PJTAG__VCCPSIO {0} \
+  CONFIG.PSU__POWER__PMU__VCCPSIO {0} \
+  CONFIG.PSU__POWER__QSPI__VCCPSINTLP {0.002} \
+  CONFIG.PSU__POWER__QSPI__VCCPSIO {0.018} \
+  CONFIG.PSU__POWER__RPLL__VCCPSPLL {0.016} \
+  CONFIG.PSU__POWER__RPU__VCCPSINTLP {0.109} \
+  CONFIG.PSU__POWER__SATA__VCCPSGTA {0.060} \
+  CONFIG.PSU__POWER__SATA__VCCPSINTFP {0.005} \
+  CONFIG.PSU__POWER__SD0__VCCPSIO {0} \
+  CONFIG.PSU__POWER__SD1__VCCPSIO {0.047} \
+  CONFIG.PSU__POWER__SGMII__VCCPSGTA {0.000} \
+  CONFIG.PSU__POWER__SPI0__VCCPSIO {0} \
+  CONFIG.PSU__POWER__SPI1__VCCPSIO {0} \
+  CONFIG.PSU__POWER__TRACE__VCCPSIO {0} \
+  CONFIG.PSU__POWER__TTC0__VCCPSIO {0} \
+  CONFIG.PSU__POWER__TTC1__VCCPSIO {0} \
+  CONFIG.PSU__POWER__TTC2__VCCPSIO {0} \
+  CONFIG.PSU__POWER__TTC3__VCCPSIO {0} \
+  CONFIG.PSU__POWER__UART0__VCCPSIO {0.004} \
+  CONFIG.PSU__POWER__UART1__VCCPSIO {0.004} \
+  CONFIG.PSU__POWER__USB0__VCCPSINTLP {0.017} \
+  CONFIG.PSU__POWER__USB0__VCCPSIO {0.046} \
+  CONFIG.PSU__POWER__USB1__VCCPSINTLP {0.000} \
+  CONFIG.PSU__POWER__USB1__VCCPSIO {0} \
+  CONFIG.PSU__POWER__USB3__VCCPSGTA {0.057} \
+  CONFIG.PSU__POWER__VPLL__VCCPSPLL {0.017} \
+  CONFIG.PSU__POWER__WDT0__VCCPSIO {0} \
+  CONFIG.PSU__POWER__WDT1__VCCPSIO {0} \
+  CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
+  CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \
+  CONFIG.PSU__QSPI_COHERENCY {1} \
   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
   CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
   CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+  CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
   CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
+  CONFIG.PSU__RPU_COHERENCY {0} \
+  CONFIG.PSU__RPU__POWER__ON {1} \
+  CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+  CONFIG.PSU__SATA__LANE0__IO {<Select>} \
+  CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+  CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+  CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__SD0_COHERENCY {1} \
+  CONFIG.PSU__SD0__DATA_TRANSFER_MODE {<Select>} \
+  CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
+  CONFIG.PSU__SD0__GRP_CD__IO {<Select>} \
+  CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+  CONFIG.PSU__SD0__GRP_POW__IO {<Select>} \
+  CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+  CONFIG.PSU__SD0__GRP_WP__IO {<Select>} \
+  CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__SD0__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__SD0__RESET__ENABLE {0} \
+  CONFIG.PSU__SD0__SLOT_TYPE {<Select>} \
+  CONFIG.PSU__SD1_COHERENCY {1} \
+  CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
   CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
   CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
   CONFIG.PSU__SD1__GRP_POW__ENABLE {1} \
@@ -68,257 +1314,1134 @@ set_property -dict [list\
   CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+  CONFIG.PSU__SD1__RESET__ENABLE {<Select>} \
   CONFIG.PSU__SD1__SLOT_TYPE {SD} \
+  CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
+  CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
+  CONFIG.PSU__SPI0__GRP_SS0__IO {<Select>} \
+  CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+  CONFIG.PSU__SPI0__GRP_SS1__IO {<Select>} \
+  CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+  CONFIG.PSU__SPI0__GRP_SS2__IO {<Select>} \
+  CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__SPI0__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
+  CONFIG.PSU__SPI1__GRP_SS0__IO {<Select>} \
+  CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+  CONFIG.PSU__SPI1__GRP_SS1__IO {<Select>} \
+  CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+  CONFIG.PSU__SPI1__GRP_SS2__IO {<Select>} \
+  CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__SPI1__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__SWDT0__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__SWDT1__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__TCM0A__POWER__ON {1} \
+  CONFIG.PSU__TCM0B__POWER__ON {1} \
+  CONFIG.PSU__TCM1A__POWER__ON {1} \
+  CONFIG.PSU__TCM1B__POWER__ON {1} \
+  CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__TRACE__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__TRACE__WIDTH {<Select>} \
+  CONFIG.PSU__TRISTATE__INVERTED {0} \
+  CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+  CONFIG.PSU__TTC0__PERIPHERAL__IO {EMIO} \
+  CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__TTC1__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__TTC2__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__TTC3__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
+  CONFIG.PSU__UART0__BAUD_RATE {115200} \
+  CONFIG.PSU__UART0__MODEM__ENABLE {0} \
   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+  CONFIG.PSU__UART1__BAUD_RATE {115200} \
+  CONFIG.PSU__UART1__MODEM__ENABLE {0} \
   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+  CONFIG.PSU__USB0_COHERENCY {1} \
   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
-  CONFIG.PSU__USE__M_AXI_GP2 {1} \
-  CONFIG.PSU__MAXIGP2__DATA_WIDTH {64} \
-  CONFIG.PSU__GT__LANE0_REF_SEL {Ref Clk0} \
-  CONFIG.PSU__GT__LANE1_REF_SEL {Ref Clk0} \
-  CONFIG.PSU__GT__LANE2_REF_SEL {Ref Clk2} \
-  CONFIG.PSU__GT__LANE3_REF_SEL {Ref Clk1} \
-  CONFIG.PSU__GT__REF_SEL0 {100} \
-  CONFIG.PSU__GT__REF_SEL1 {100} \
-  CONFIG.PSU__GT__REF_SEL2 {26} \
-  CONFIG.PSU__GT__REF_SEL3 {125} \
-  CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
-  CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
-  CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
-  CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
-  CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
-  CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
-  CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
-  CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
-  CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
-  CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
-  CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
-  CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \
-  CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
-  CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
-  CONFIG.PSU__SATA__LANE1__ENABLE {1} \
-  CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+  CONFIG.PSU__USB1_COHERENCY {1} \
+  CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__USB1__PERIPHERAL__IO {<Select>} \
   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
-  CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
-  CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
-  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
-  CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
-  CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
-  CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
-  CONFIG.PSU__DDRC__VREF {1} \
-  CONFIG.PSU__DDRC__ECC {0} \
-  CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
-  CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \
-  CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
-  CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
-  CONFIG.PSU__DDRC__FREQ_MHZ {1066.50} \
-  CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
-  CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
-  CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
-  CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \
-  CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
-  CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
-  CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
-  CONFIG.PSU__DDRC__CL {15} \
-  CONFIG.PSU__DDRC__T_RCD {15} \
-  CONFIG.PSU__DDRC__T_RP {15} \
-  CONFIG.PSU__DDRC__CWL {14} \
-  CONFIG.PSU__DDRC__AL {0} \
-  CONFIG.PSU__DDRC__BL {8} \
-  CONFIG.PSU__DDRC__T_RC {46.5} \
-  CONFIG.PSU__DDRC__T_RAS_MIN {33} \
-  CONFIG.PSU__DDRC__T_FAW {21.0} \
-  CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
-  CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
-  CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {0} \
-  CONFIG.PSU__DDRC__RD_DBI_ENABLE {0} \
-  CONFIG.PSU__DDRC__WR_DBI_ENABLE {0} \
-  CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
-  CONFIG.PSU__DDRC__DATA_MASK {1} \
-  CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
-  CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
-  CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
-  CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
-  CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
-  CONFIG.PSU__DDRC__BRC_MAPPING {0} \
-  CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
-  CONFIG.PSU__DDRC__FGRM {0} \
-  CONFIG.PSU__DDRC__LP_ASR {0} \
-  CONFIG.PSU__DDRC__UDIMM_INDICATOR {1} \
-  CONFIG.PSU__DDRC__RDIMM_INDICATOR {0} \
-  CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
-  CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
-  CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
-  CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
-  CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \
-  CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
-  CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
-  CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {66} \
-  CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
-  CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
-  CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
-  CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
-  CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
-  CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {57} \
-  CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
-  CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.508} \
-  CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
-  CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
-  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
-  CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
-  CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
-  CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {72} \
-  CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__SRCSEL {APLL} \
-  CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__SRCSEL {DPLL} \
-  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__SRCSEL {VPLL} \
-  CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
-  CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
-  CONFIG.PSU__CRF_APB__DBG_TRACE__ENABLE {1} \
-  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__DBG_FPD__ENABLE {1} \
-  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__DBG_TSTMP__ENABLE {1} \
-  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \
-  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {39} \
-  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {17} \
-  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRF_APB__DPDMA__ENABLE {1} \
-  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
-  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
-  CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
-  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__GDMA__ENABLE {1} \
-  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
-  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {1} \
-  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {4} \
-  CONFIG.PSU__CRF_APB__TOPSW_MAIN__ENABLE {1} \
-  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \
-  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
-  CONFIG.PSU__CRF_APB__TOPSW_LSBUS__ENABLE {1} \
-  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
-  CONFIG.PSU__CRL_APB__IOU_SWITCH__ENABLE {1} \
-  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
-  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
-  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
-  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
-  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
-  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
-  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
-  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
-  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__ADMA__ENABLE {1} \
-  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRL_APB__DBG_LPD__ENABLE {1} \
-  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRL_APB__PCAP__ENABLE {1} \
-  CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {RPLL} \
-  CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {6} \
-  CONFIG.PSU__CRL_APB__LPD_LSBUS__ENABLE {1} \
-  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__LPD_SWITCH__ENABLE {1} \
-  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
-  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
-  CONFIG.PSU__CRL_APB__TIMESTAMP__ENABLE {1} \
-  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__FPGA_PL0_ENABLE {1} \
-  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
-  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
-  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+  CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
+  CONFIG.PSU__USB3_1__PERIPHERAL__IO {<Select>} \
+  CONFIG.PSU__USE__FABRIC__RST {1} \
+  CONFIG.PSU__USE__IRQ0 {1} \
+  CONFIG.PSU__USE__M_AXI_GP2 {1} \
+  CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
 ] $sys_ps8
 
+set_property -dict [list \
+  CONFIG.PSU_BANK_0_IO_STANDARD.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_BANK_1_IO_STANDARD.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_BANK_2_IO_STANDARD.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_DDR_RAM_HIGHADDR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_0_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_0_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_0_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_0_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_0_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_10_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_10_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_10_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_10_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_10_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_11_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_11_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_11_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_11_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_11_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_12_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_12_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_12_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_12_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_12_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_13_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_13_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_13_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_13_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_13_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_14_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_14_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_14_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_14_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_14_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_15_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_15_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_15_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_15_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_15_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_16_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_16_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_16_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_16_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_16_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_17_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_17_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_17_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_17_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_17_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_18_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_18_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_18_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_18_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_18_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_19_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_19_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_19_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_19_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_19_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_1_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_1_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_1_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_1_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_1_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_20_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_20_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_20_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_20_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_20_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_21_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_21_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_21_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_21_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_21_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_22_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_22_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_22_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_22_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_22_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_23_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_23_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_23_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_23_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_23_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_24_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_24_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_24_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_24_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_24_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_25_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_25_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_25_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_25_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_25_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_26_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_26_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_26_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_26_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_26_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_27_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_27_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_27_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_27_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_27_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_28_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_28_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_28_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_28_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_28_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_29_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_29_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_29_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_29_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_29_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_2_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_2_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_2_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_2_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_2_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_30_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_30_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_30_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_30_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_30_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_31_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_31_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_31_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_31_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_31_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_32_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_32_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_32_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_32_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_32_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_33_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_33_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_33_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_33_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_33_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_34_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_34_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_34_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_34_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_34_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_35_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_35_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_35_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_35_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_35_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_36_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_36_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_36_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_36_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_36_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_37_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_37_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_37_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_37_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_37_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_38_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_38_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_38_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_38_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_38_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_39_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_39_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_39_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_39_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_39_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_3_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_3_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_3_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_3_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_3_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_40_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_40_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_40_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_40_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_40_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_41_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_41_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_41_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_41_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_41_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_42_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_42_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_42_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_42_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_42_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_43_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_43_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_43_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_43_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_43_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_44_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_44_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_44_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_44_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_44_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_45_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_45_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_45_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_45_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_45_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_46_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_46_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_46_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_46_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_46_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_47_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_47_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_47_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_47_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_47_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_48_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_48_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_48_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_48_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_48_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_49_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_49_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_49_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_49_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_49_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_4_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_4_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_4_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_4_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_4_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_50_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_50_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_50_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_50_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_50_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_51_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_51_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_51_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_51_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_51_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_52_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_52_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_52_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_52_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_52_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_53_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_53_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_53_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_53_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_53_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_54_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_54_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_54_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_54_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_54_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_55_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_55_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_55_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_55_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_55_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_56_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_56_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_56_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_56_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_56_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_57_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_57_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_57_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_57_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_57_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_58_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_58_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_58_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_58_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_58_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_59_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_59_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_59_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_59_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_59_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_5_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_5_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_5_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_5_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_5_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_60_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_60_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_60_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_60_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_60_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_61_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_61_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_61_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_61_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_61_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_62_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_62_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_62_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_62_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_62_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_63_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_63_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_63_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_63_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_63_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_64_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_64_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_64_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_64_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_64_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_65_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_65_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_65_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_65_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_65_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_66_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_66_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_66_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_66_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_66_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_67_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_67_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_67_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_67_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_67_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_68_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_68_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_68_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_68_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_68_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_69_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_69_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_69_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_69_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_69_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_6_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_6_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_6_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_6_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_6_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_70_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_70_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_70_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_70_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_70_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_71_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_71_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_71_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_71_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_71_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_72_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_72_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_72_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_72_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_72_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_73_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_73_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_73_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_73_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_73_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_74_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_74_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_74_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_74_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_74_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_75_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_75_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_75_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_75_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_75_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_76_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_76_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_76_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_76_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_76_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_77_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_77_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_77_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_77_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_77_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_7_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_7_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_7_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_7_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_7_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_8_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_8_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_8_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_8_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_8_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_9_DIRECTION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_9_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_9_INPUT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_9_PULLUPDOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_9_SLEW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_TREE_PERIPHERALS.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_MIO_TREE_SIGNALS.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_PACKAGE_DDR_BOARD_DELAY3.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_PRESET_BANK0_VOLTAGE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_PRESET_BANK1_VOLTAGE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU_UIPARAM_GENERATE_SUMMARY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ACPU0__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ACPU1__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ACPU2__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ACPU3__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ACT_DDR_FREQ_MHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ADMA_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__AUX_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CAN0__GRP_CLK__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CAN0__GRP_CLK__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CAN0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CAN0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CAN1__GRP_CLK__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CAN1__GRP_CLK__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CPU_CPU_6X4X_MAX_RANGE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CPU_R5__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__ACPU__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__APM_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__GPU__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AFI6__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__AMS__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__OCM_MAIN__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CRYSTAL__PERIPHERAL__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_0__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_10__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_11__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_12__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_1__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_2__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_3__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_4__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_5__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_6__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_7__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_8__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__CSU_TAMPER_9__RESPONSE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__CSU__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DAP_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__BOARD_DELAY0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__BOARD_DELAY1.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__BOARD_DELAY2.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__BOARD_DELAY3.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__CLOCK_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DERATE_INT_D.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_0.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_1.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_2.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_3.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__DQ_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__ECC_SCRUB.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__EN_2ND_CLK.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__HIGH_TEMP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__PARTNO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__PLL_BYPASS.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__PWR_DOWN_EN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__USE_INTERNAL_VREF.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DDR__INTERFACE__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DISPLAYPORT__LANE0__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DISPLAYPORT__LANE1__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DPAUX__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__DP__LANE_SEL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET0__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET0__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET1__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET1__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET2__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET2__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET2__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__ENET2__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__FP__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEM0_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEM1_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEM2_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEM3_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEM__TSU__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEM__TSU__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GENERATE_SECURITY_REGISTERS.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_0__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_10__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_1__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_2__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_3__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_4__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_5__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_6__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_7__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_8__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GEN_IPI_9__MASTER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GPIO2_MIO__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GPIO_EMIO__WIDTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GPU_PP0__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GPU_PP1__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GT_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__GT__LINK_SPEED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__I2C0__GRP_INT__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__I2C0__GRP_INT__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__I2C1__GRP_INT__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__I2C1__GRP_INT__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__L2_BANK0__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND__CHIP_ENABLE__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND__DATA_STROBE__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND__DATA_STROBE__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND__READY_BUSY__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__NAND__READY_BUSY__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__OCM_BANK0__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__OCM_BANK1__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__OCM_BANK2__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__OCM_BANK3__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__ACS_VIOLATION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__AER_CAPABILITY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR0_64BIT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR0_PREFETCHABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR0_SCALE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR0_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR0_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR0_VAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR1_64BIT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR1_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR1_PREFETCHABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR1_SCALE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR1_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR1_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR1_VAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR2_64BIT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR2_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR2_PREFETCHABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR2_SCALE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR2_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR2_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR2_VAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR3_64BIT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR3_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR3_PREFETCHABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR3_SCALE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR3_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR3_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR3_VAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR4_64BIT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR4_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR4_PREFETCHABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR4_SCALE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR4_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR4_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR4_VAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR5_64BIT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR5_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR5_PREFETCHABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR5_SCALE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR5_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR5_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BAR5_VAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BASE_CLASS_MENU.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__BRIDGE_BAR_INDICATOR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__CAP_SLOT_IMPLEMENTED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__CLASS_CODE_VALUE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__COMPLETER_ABORT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__COMPLTION_TIMEOUT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__ECRC_CHECK.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__ECRC_ERR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__ECRC_GEN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__EROM_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__EROM_SCALE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__EROM_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__EROM_VAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__FLOW_CONTROL_ERR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__INTERFACE_WIDTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__INTX_GENERATION.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__INTX_PIN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__LANE1__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__LANE2__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__LANE2__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__LANE3__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__LANE3__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__LEGACY_INTERRUPT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MC_BLOCKED_TLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSIX_CAPABILITY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSIX_PBA_OFFSET.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSIX_TABLE_SIZE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSI_CAPABILITY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__MULTIHEADER.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__RECEIVER_ERR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__RECEIVER_OVERFLOW.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__REVISION_ID.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__SUBSYSTEM_ID.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__SUB_CLASS_INTERFACE_MENU.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__SURPRISE_DOWN.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PCIE__VENDOR_ID.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PJTAG__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PL__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__EMIO_GPI__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__EMIO_GPO__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI0__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI0__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI1__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI2__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI2__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI3__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI3__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI4__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI4__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI5__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPI5__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO0__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO0__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO1__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO2__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO2__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO3__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO3__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO4__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO4__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO5__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__GPO5__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PMU__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__ANALOG.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__DDR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__FPD.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__LPD.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__MIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__PLL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__SERDES.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__TOTAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__ONCHIP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__ANALOG.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__DDR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__FPD.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__LPD.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__MIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__PLL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__SERDES.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER_SUMMARY__STATIC__TOTAL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__ACPU__VCCPSINTFP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__AFI_FPD__VCCPSINTFP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__AFI_LPD__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__APLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__CAN0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__CAN1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__CSU__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__DDR__VCCPSDDR.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__DDR__VCCPSINTFP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__DPAUX__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__DPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__DP__VCCPSGTA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__DP__VCCPSINTFP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__FPINT__VCCPSINTFP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GEM0__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GEM0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GEM1__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GEM1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GEM2__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GEM2__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GEM3__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GEM3__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GPIO0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GPIO1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GPIO2__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__GPU__VCCPSINTFP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__IOPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__LPINT__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__NAND__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__NAND__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__PCIE__VCCPSGTA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__PCIE__VCCPSINTFP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__PJTAG__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__PMU__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__QSPI__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__QSPI__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__RPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__RPU__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__SATA__VCCPSGTA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__SATA__VCCPSINTFP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__SD0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__SD1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__SGMII__VCCPSGTA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__SPI0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__SPI1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__TRACE__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__TTC0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__TTC1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__TTC2__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__TTC3__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__UART0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__UART1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__USB0__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__USB0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__USB1__VCCPSINTLP.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__USB1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__USB3__VCCPSGTA.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__VPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__WDT0__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__POWER__WDT1__VCCPSIO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__QSPI_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__RPU_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__RPU__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SATA__LANE0__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SATA__LANE0__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__DATA_TRANSFER_MODE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__GRP_CD__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__GRP_CD__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__GRP_POW__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__GRP_POW__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__GRP_WP__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__GRP_WP__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__RESET__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD0__SLOT_TYPE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD1_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SD1__RESET__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0__GRP_SS0__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0__GRP_SS0__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0__GRP_SS1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0__GRP_SS1__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0__GRP_SS2__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0__GRP_SS2__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI1__GRP_SS0__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI1__GRP_SS0__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI1__GRP_SS1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI1__GRP_SS1__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI1__GRP_SS2__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI1__GRP_SS2__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SPI1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SWDT0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__SWDT1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TCM0A__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TCM0B__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TCM1A__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TCM1B__POWER__ON.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TRACE__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TRACE__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TRACE__WIDTH.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TRISTATE__INVERTED.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TTC1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TTC1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TTC2__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TTC2__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TTC3__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__TTC3__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__UART0_LOOP_UART1__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__UART0__BAUD_RATE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__UART0__MODEM__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__UART1__BAUD_RATE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__USB0_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__USB1_COHERENCY.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__USB1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__USB1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__USB3_1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__USE__FABRIC__RST.VALUE_SRC {DEFAULT} \
+  CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
+] $sys_ps8
+
+
 set_property CONFIG.PSU__USE__M_AXI_GP2 {1} $sys_ps8
 set_property CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} $sys_ps8
 set_property CONFIG.PSU__FPGA_PL0_ENABLE {1} $sys_ps8
@@ -327,7 +2450,7 @@ set_property CONFIG.PSU__FPGA_PL1_ENABLE {1} $sys_ps8
 set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {200} $sys_ps8
 set_property CONFIG.PSU__USE__IRQ0 {1} $sys_ps8
 set_property CONFIG.PSU__USE__IRQ1 {1} $sys_ps8
-set_property CONFIG.PSU__GPIO0_EMIO__PERIPHERAL__ENABLE {1} $sys_ps8
+set_property CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} $sys_ps8
 
 set_property -dict [list\
   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \

From 8e1034946f3a560350043a2552dc17e378dea3ea Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 11:53:48 -0400
Subject: [PATCH 551/972] fmcomms2/zcu102- 2016.2 updates

---
 projects/fmcomms2/common/fmcomms2_bd.tcl | 1 -
 projects/fmcomms2/zcu102/system_bd.tcl   | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl
index f9e2f4532..2dbf3d04e 100644
--- a/projects/fmcomms2/common/fmcomms2_bd.tcl
+++ b/projects/fmcomms2/common/fmcomms2_bd.tcl
@@ -27,7 +27,6 @@ create_bd_port -dir O tdd_sync_t
 # ad9361 core
 
 set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
-set_property -dict [list CONFIG.TDD_CONTROL_EN {1}] $axi_ad9361
 set_property -dict [list CONFIG.ID {0}] $axi_ad9361
 
 set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
diff --git a/projects/fmcomms2/zcu102/system_bd.tcl b/projects/fmcomms2/zcu102/system_bd.tcl
index ffeb9f0ee..c5e28355f 100755
--- a/projects/fmcomms2/zcu102/system_bd.tcl
+++ b/projects/fmcomms2/zcu102/system_bd.tcl
@@ -2,3 +2,5 @@
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
 source ../common/fmcomms2_bd.tcl
 
+set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361]
+

From 27c9bdddb6f866c906337400c765bd36ac31db78 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 11:54:15 -0400
Subject: [PATCH 552/972] daq2/zcu102- 2016.2 updates

---
 projects/daq2/zcu102/system_bd.tcl      |   2 +-
 projects/daq2/zcu102/system_constr.xdc  | 102 ++++++++++++------------
 projects/daq2/zcu102/system_project.tcl |   8 +-
 3 files changed, 56 insertions(+), 56 deletions(-)

diff --git a/projects/daq2/zcu102/system_bd.tcl b/projects/daq2/zcu102/system_bd.tcl
index 7b40605ee..735376cdc 100644
--- a/projects/daq2/zcu102/system_bd.tcl
+++ b/projects/daq2/zcu102/system_bd.tcl
@@ -1,5 +1,5 @@
 
-source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
+source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
diff --git a/projects/daq2/zcu102/system_constr.xdc b/projects/daq2/zcu102/system_constr.xdc
index ac806dd2d..a898a2bf5 100644
--- a/projects/daq2/zcu102/system_constr.xdc
+++ b/projects/daq2/zcu102/system_constr.xdc
@@ -1,40 +1,40 @@
 
 # daq2
 
-set_property  -dict {PACKAGE_PIN  H6} [get_ports rx_ref_clk_p]                                              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
-set_property  -dict {PACKAGE_PIN  H5} [get_ports rx_ref_clk_n]                                              ; ## B21  FMC_HPC_GBTCLK1_M2C_N
-set_property  -dict {PACKAGE_PIN  G9  IOSTANDARD LVDS} [get_ports rx_sync_p]                                ; ## D08  FMC_HPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN  F9  IOSTANDARD LVDS} [get_ports rx_sync_n]                                ; ## D09  FMC_HPC_LA01_CC_N
-set_property  -dict {PACKAGE_PIN  A13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p]       ; ## G09  FMC_HPC_LA03_P
-set_property  -dict {PACKAGE_PIN  A12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n]       ; ## G10  FMC_HPC_LA03_N
+set_property  -dict {PACKAGE_PIN  L7} [get_ports rx_ref_clk_p]                                              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  L8} [get_ports rx_ref_clk_n]                                              ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  W2  IOSTANDARD LVDS} [get_ports rx_sync_p]                                ; ## D08  FMC_HPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  W1  IOSTANDARD LVDS} [get_ports rx_sync_n]                                ; ## D09  FMC_HPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  Y2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p]       ; ## G09  FMC_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  Y1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n]       ; ## G10  FMC_HPC_LA03_N
 
-set_property  -dict {PACKAGE_PIN  K6} [get_ports tx_ref_clk_p]                                              ; ## D04  FMC_HPC_GBTCLK0_M2C_P
-set_property  -dict {PACKAGE_PIN  K5} [get_ports tx_ref_clk_n]                                              ; ## D05  FMC_HPC_GBTCLK0_M2C_N
-set_property  -dict {PACKAGE_PIN  K10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p]         ; ## H07  FMC_HPC_LA02_P
-set_property  -dict {PACKAGE_PIN  J10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n]         ; ## H08  FMC_HPC_LA02_N
-set_property  -dict {PACKAGE_PIN  L12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p]       ; ## H10  FMC_HPC_LA04_P
-set_property  -dict {PACKAGE_PIN  K12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n]       ; ## H11  FMC_HPC_LA04_N
+set_property  -dict {PACKAGE_PIN  G8} [get_ports tx_ref_clk_p]                                              ; ## D04  FMC_HPC_GBTCLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  G7} [get_ports tx_ref_clk_n]                                              ; ## D05  FMC_HPC_GBTCLK0_M2C_N
+set_property  -dict {PACKAGE_PIN  V2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p]         ; ## H07  FMC_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  V1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n]         ; ## H08  FMC_HPC_LA02_N
+set_property  -dict {PACKAGE_PIN  AA2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p]       ; ## H10  FMC_HPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AA1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n]       ; ## H11  FMC_HPC_LA04_N
 
-set_property  -dict {PACKAGE_PIN  L13 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk]                          ; ## D11  FMC_HPC_LA05_P
-set_property  -dict {PACKAGE_PIN  L8  IOSTANDARD LVCMOS18} [get_ports spi_csn_dac]                          ; ## C14  FMC_HPC_LA10_P
-set_property  -dict {PACKAGE_PIN  H9  IOSTANDARD LVCMOS18} [get_ports spi_csn_adc]                          ; ## D15  FMC_HPC_LA09_N
-set_property  -dict {PACKAGE_PIN  K13 IOSTANDARD LVCMOS18} [get_ports spi_clk]                              ; ## D12  FMC_HPC_LA05_N
-set_property  -dict {PACKAGE_PIN  J9  IOSTANDARD LVCMOS18} [get_ports spi_sdio]                             ; ## D14  FMC_HPC_LA09_P
-set_property  -dict {PACKAGE_PIN  H8  IOSTANDARD LVCMOS18} [get_ports spi_dir]                              ; ## G13  FMC_HPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AB3 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk]                          ; ## D11  FMC_HPC_LA05_P
+set_property  -dict {PACKAGE_PIN  W5  IOSTANDARD LVCMOS18} [get_ports spi_csn_dac]                          ; ## C14  FMC_HPC_LA10_P
+set_property  -dict {PACKAGE_PIN  AC4 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc]                          ; ## D15  FMC_HPC_LA09_N
+set_property  -dict {PACKAGE_PIN  AC3 IOSTANDARD LVCMOS18} [get_ports spi_clk]                              ; ## D12  FMC_HPC_LA05_N
+set_property  -dict {PACKAGE_PIN  AB4 IOSTANDARD LVCMOS18} [get_ports spi_sdio]                             ; ## D14  FMC_HPC_LA09_P
+set_property  -dict {PACKAGE_PIN  V3  IOSTANDARD LVCMOS18} [get_ports spi_dir]                              ; ## G13  FMC_HPC_LA08_N
 
-set_property  -dict {PACKAGE_PIN  J8  IOSTANDARD LVCMOS18} [get_ports clkd_sync]                            ; ## G12  FMC_HPC_LA08_P
-set_property  -dict {PACKAGE_PIN  K8  IOSTANDARD LVCMOS18} [get_ports dac_reset]                            ; ## C15  FMC_HPC_LA10_N
-set_property  -dict {PACKAGE_PIN  D10 IOSTANDARD LVCMOS18} [get_ports dac_txen]                             ; ## G16  FMC_HPC_LA12_N
-set_property  -dict {PACKAGE_PIN  D13 IOSTANDARD LVCMOS18} [get_ports adc_pd]                               ; ## C10  FMC_HPC_LA06_P
+set_property  -dict {PACKAGE_PIN  V4  IOSTANDARD LVCMOS18} [get_ports clkd_sync]                            ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  W4  IOSTANDARD LVCMOS18} [get_ports dac_reset]                            ; ## C15  FMC_HPC_LA10_N
+set_property  -dict {PACKAGE_PIN  W6  IOSTANDARD LVCMOS18} [get_ports dac_txen]                             ; ## G16  FMC_HPC_LA12_N
+set_property  -dict {PACKAGE_PIN  AC2 IOSTANDARD LVCMOS18} [get_ports adc_pd]                               ; ## C10  FMC_HPC_LA06_P
 
-set_property  -dict {PACKAGE_PIN  D9  IOSTANDARD LVCMOS18} [get_ports clkd_status[0]]                       ; ## D17  FMC_HPC_LA13_P
-set_property  -dict {PACKAGE_PIN  C9  IOSTANDARD LVCMOS18} [get_ports clkd_status[1]]                       ; ## D18  FMC_HPC_LA13_N
-set_property  -dict {PACKAGE_PIN  E10 IOSTANDARD LVCMOS18} [get_ports dac_irq]                              ; ## G15  FMC_HPC_LA12_P
-set_property  -dict {PACKAGE_PIN  K11 IOSTANDARD LVCMOS18} [get_ports adc_fda]                              ; ## H16  FMC_HPC_LA11_P
-set_property  -dict {PACKAGE_PIN  J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb]                              ; ## H17  FMC_HPC_LA11_N
+set_property  -dict {PACKAGE_PIN  AB8 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]]                       ; ## D17  FMC_HPC_LA13_P
+set_property  -dict {PACKAGE_PIN  AC8 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]]                       ; ## D18  FMC_HPC_LA13_N
+set_property  -dict {PACKAGE_PIN  W7  IOSTANDARD LVCMOS18} [get_ports dac_irq]                              ; ## G15  FMC_HPC_LA12_P
+set_property  -dict {PACKAGE_PIN  AB6 IOSTANDARD LVCMOS18} [get_ports adc_fda]                              ; ## H16  FMC_HPC_LA11_P
+set_property  -dict {PACKAGE_PIN  AB5 IOSTANDARD LVCMOS18} [get_ports adc_fdb]                              ; ## H17  FMC_HPC_LA11_N
 
-set_property  -dict {PACKAGE_PIN  F8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p]            ; ## H13  FMC_HPC_LA07_P          
-set_property  -dict {PACKAGE_PIN  E8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n]            ; ## H14  FMC_HPC_LA07_N          
+set_property  -dict {PACKAGE_PIN  U5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p]            ; ## H13  FMC_HPC_LA07_P          
+set_property  -dict {PACKAGE_PIN  U4  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n]            ; ## H14  FMC_HPC_LA07_N          
 
 # clocks
 
@@ -45,28 +45,28 @@ create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_
 
 # gt pin assignments below are for reference only and are ignored by the tool!
 
-##  set_property  -dict {PACKAGE_PIN  A4} [get_ports rx_data_p[0]] ; ## A10  FMC_HPC_DP3_M2C_P
-##  set_property  -dict {PACKAGE_PIN  A3} [get_ports rx_data_n[0]] ; ## A11  FMC_HPC_DP3_M2C_N
-##  set_property  -dict {PACKAGE_PIN  E4} [get_ports rx_data_p[1]] ; ## C06  FMC_HPC_DP0_M2C_P
-##  set_property  -dict {PACKAGE_PIN  E3} [get_ports rx_data_n[1]] ; ## C07  FMC_HPC_DP0_M2C_N
-##  set_property  -dict {PACKAGE_PIN  B2} [get_ports rx_data_p[2]] ; ## A06  FMC_HPC_DP2_M2C_P
-##  set_property  -dict {PACKAGE_PIN  B1} [get_ports rx_data_n[2]] ; ## A07  FMC_HPC_DP2_M2C_N
-##  set_property  -dict {PACKAGE_PIN  D2} [get_ports rx_data_p[3]] ; ## A02  FMC_HPC_DP1_M2C_P
-##  set_property  -dict {PACKAGE_PIN  D1} [get_ports rx_data_n[3]] ; ## A03  FMC_HPC_DP1_M2C_N
-##  set_property  -dict {PACKAGE_PIN  B6} [get_ports tx_data_p[0]] ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[0])
-##  set_property  -dict {PACKAGE_PIN  B5} [get_ports tx_data_n[0]] ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[0])
-##  set_property  -dict {PACKAGE_PIN  F6} [get_ports tx_data_p[1]] ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[3])
-##  set_property  -dict {PACKAGE_PIN  F5} [get_ports tx_data_n[1]] ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[3])
-##  set_property  -dict {PACKAGE_PIN  C4} [get_ports tx_data_p[2]] ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[1])
-##  set_property  -dict {PACKAGE_PIN  C3} [get_ports tx_data_n[2]] ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[1])
-##  set_property  -dict {PACKAGE_PIN  D6} [get_ports tx_data_p[3]] ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
-##  set_property  -dict {PACKAGE_PIN  D5} [get_ports tx_data_n[3]] ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
+##  set_property  -dict {PACKAGE_PIN  K2} [get_ports rx_data_p[0]] ; ## A10  FMC_HPC_DP3_M2C_P
+##  set_property  -dict {PACKAGE_PIN  K1} [get_ports rx_data_n[0]] ; ## A11  FMC_HPC_DP3_M2C_N
+##  set_property  -dict {PACKAGE_PIN  H2} [get_ports rx_data_p[1]] ; ## C06  FMC_HPC_DP0_M2C_P
+##  set_property  -dict {PACKAGE_PIN  H1} [get_ports rx_data_n[1]] ; ## C07  FMC_HPC_DP0_M2C_N
+##  set_property  -dict {PACKAGE_PIN  F2} [get_ports rx_data_p[2]] ; ## A06  FMC_HPC_DP2_M2C_P
+##  set_property  -dict {PACKAGE_PIN  F1} [get_ports rx_data_n[2]] ; ## A07  FMC_HPC_DP2_M2C_N
+##  set_property  -dict {PACKAGE_PIN  J4} [get_ports rx_data_p[3]] ; ## A02  FMC_HPC_DP1_M2C_P
+##  set_property  -dict {PACKAGE_PIN  J3} [get_ports rx_data_n[3]] ; ## A03  FMC_HPC_DP1_M2C_N
+##  set_property  -dict {PACKAGE_PIN  K6} [get_ports tx_data_p[0]] ; ## A30  FMC_HPC_DP3_C2M_P (tx_data_p[0])
+##  set_property  -dict {PACKAGE_PIN  K5} [get_ports tx_data_n[0]] ; ## A31  FMC_HPC_DP3_C2M_N (tx_data_n[0])
+##  set_property  -dict {PACKAGE_PIN  G4} [get_ports tx_data_p[1]] ; ## C02  FMC_HPC_DP0_C2M_P (tx_data_p[3])
+##  set_property  -dict {PACKAGE_PIN  G3} [get_ports tx_data_n[1]] ; ## C03  FMC_HPC_DP0_C2M_N (tx_data_n[3])
+##  set_property  -dict {PACKAGE_PIN  F6} [get_ports tx_data_p[2]] ; ## A26  FMC_HPC_DP2_C2M_P (tx_data_p[1])
+##  set_property  -dict {PACKAGE_PIN  F5} [get_ports tx_data_n[2]] ; ## A27  FMC_HPC_DP2_C2M_N (tx_data_n[1])
+##  set_property  -dict {PACKAGE_PIN  H6} [get_ports tx_data_p[3]] ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
+##  set_property  -dict {PACKAGE_PIN  H5} [get_ports tx_data_n[3]] ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
 
-set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_1/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}]
+set_property LOC GTHE4_CHANNEL_X1Y8  [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel}]
+set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_1/i_gthe3_channel}]
+set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}]
+set_property LOC GTHE4_CHANNEL_X1Y9  [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}]
 
-set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9144_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
-set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9680_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+#set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9144_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+#set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9680_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
diff --git a/projects/daq2/zcu102/system_project.tcl b/projects/daq2/zcu102/system_project.tcl
index ad3fad935..4bb1f028f 100644
--- a/projects/daq2/zcu102/system_project.tcl
+++ b/projects/daq2/zcu102/system_project.tcl
@@ -3,14 +3,14 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create daq2_kcu105
-adi_project_files daq2_kcu105 [list \
+adi_project_create daq2_zcu102
+adi_project_files daq2_zcu102 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
 
-adi_project_run daq2_kcu105
+adi_project_run daq2_zcu102
 
 

From 0208335ef3e4748dbacfd55a4058d48338d5ad4e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 13:20:22 -0400
Subject: [PATCH 553/972] hdlmake- updates

---
 projects/daq2/Makefile        |  3 +++
 projects/daq2/zcu102/Makefile | 10 +++++-----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/projects/daq2/Makefile b/projects/daq2/Makefile
index a6441f0c6..337f26381 100644
--- a/projects/daq2/Makefile
+++ b/projects/daq2/Makefile
@@ -12,6 +12,7 @@ all:
 	-make -C kcu105 all
 	-make -C vc707 all
 	-make -C zc706 all
+	-make -C zcu102 all
 
 
 clean: 
@@ -20,6 +21,7 @@ clean:
 	make -C kcu105 clean
 	make -C vc707 clean
 	make -C zc706 clean
+	make -C zcu102 clean
 
 
 clean-all:
@@ -28,6 +30,7 @@ clean-all:
 	make -C kcu105 clean-all
 	make -C vc707 clean-all
 	make -C zc706 clean-all
+	make -C zcu102 clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/daq2/zcu102/Makefile b/projects/daq2/zcu102/Makefile
index 30c090bd7..72ff9fbcd 100644
--- a/projects/daq2/zcu102/Makefile
+++ b/projects/daq2/zcu102/Makefile
@@ -14,10 +14,10 @@ M_DEPS += ../common/daq2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
+M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
 M_DEPS += ../../common/xilinx/sys_dacfifo.tcl
 M_DEPS += ../../common/xilinx/sys_adcfifo.tcl
-M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
-M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
@@ -48,7 +48,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib daq2_kcu105.sdk/system_top.hdf
+all: lib daq2_zcu102.sdk/system_top.hdf
 
 
 clean: 
@@ -67,9 +67,9 @@ clean-all:clean
 	make -C ../../../library/util_upack clean
 
 
-daq2_kcu105.sdk/system_top.hdf: $(M_DEPS)
+daq2_zcu102.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> daq2_kcu105_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> daq2_zcu102_vivado.log 2>&1
 
 
 lib:

From 8e25bc01b3ddf7ee17a8c8c72fb364bcfdb76579 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Sat, 1 Oct 2016 18:13:42 +0300
Subject: [PATCH 554/972] all: Change tab to double space

Occasional file parsing and restructuring become a pain, if tabs exists
in code. General rule of the repos is tab always a double space.
---
 library/axi_dmac/2d_transfer.v                |  142 +--
 library/axi_dmac/address_generator.v          |  114 +-
 library/axi_dmac/axi_dmac.v                   |  724 +++++------
 library/axi_dmac/axi_register_slice.v         |   56 +-
 library/axi_dmac/data_mover.v                 |  134 +--
 library/axi_dmac/dest_axi_mm.v                |  252 ++--
 library/axi_dmac/dest_axi_stream.v            |  118 +-
 library/axi_dmac/dest_fifo_inf.v              |  132 +-
 library/axi_dmac/request_arb.v                | 1064 ++++++++---------
 library/axi_dmac/request_generator.v          |   58 +-
 library/axi_dmac/response_generator.v         |   54 +-
 library/axi_dmac/response_handler.v           |   60 +-
 library/axi_dmac/splitter.v                   |   28 +-
 library/axi_dmac/src_axi_mm.v                 |  202 ++--
 library/axi_dmac/src_axi_stream.v             |  106 +-
 library/axi_dmac/src_fifo_inf.v               |  126 +-
 library/axi_generic_adc/axi_generic_adc.v     |  292 ++---
 .../cn0363_dma_sequencer.v                    |  230 ++--
 .../cn0363_phase_data_sync.v                  |  146 +--
 library/common/sync_bits.v                    |   22 +-
 library/common/sync_gray.v                    |   76 +-
 library/common/up_hdmi_tx.v                   |    2 +-
 library/cordic_demod/cordic_demod.v           |  254 ++--
 .../spi_engine_interconnect.v                 |  106 +-
 .../spi_engine_offload/spi_engine_offload.v   |  128 +-
 library/util_axis_fifo/address_gray.v         |  116 +-
 .../util_axis_fifo/address_gray_pipelined.v   |  124 +-
 library/util_axis_fifo/address_sync.v         |   78 +-
 library/util_axis_fifo/util_axis_fifo.v       |  156 +--
 library/util_axis_resize/util_axis_resize.v   |  110 +-
 library/util_clkdiv/util_clkdiv.v             |    4 +-
 .../util_sigma_delta_spi.v                    |   62 +-
 32 files changed, 2638 insertions(+), 2638 deletions(-)

diff --git a/library/axi_dmac/2d_transfer.v b/library/axi_dmac/2d_transfer.v
index 6f9c25549..13f4e2dff 100644
--- a/library/axi_dmac/2d_transfer.v
+++ b/library/axi_dmac/2d_transfer.v
@@ -37,28 +37,28 @@
 // ***************************************************************************
 
 module dmac_2d_transfer (
-	input req_aclk,
-	input req_aresetn,
+  input req_aclk,
+  input req_aresetn,
 
-	input req_valid,
-	output reg req_ready,
+  input req_valid,
+  output reg req_ready,
 
-	input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
-	input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
-	input [DMA_LENGTH_WIDTH-1:0] req_x_length,
-	input [DMA_LENGTH_WIDTH-1:0] req_y_length,
-	input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
-	input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
-	input req_sync_transfer_start,
-	output reg req_eot,
-	
-	output reg out_req_valid,
-	input out_req_ready,
-	output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
-	output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
-	output [DMA_LENGTH_WIDTH-1:0] out_req_length,
-	output reg out_req_sync_transfer_start,
-	input out_eot
+  input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
+  input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
+  input [DMA_LENGTH_WIDTH-1:0] req_x_length,
+  input [DMA_LENGTH_WIDTH-1:0] req_y_length,
+  input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
+  input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
+  input req_sync_transfer_start,
+  output reg req_eot,
+  
+  output reg out_req_valid,
+  input out_req_ready,
+  output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
+  output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
+  output [DMA_LENGTH_WIDTH-1:0] out_req_length,
+  output reg out_req_sync_transfer_start,
+  input out_eot
 );
 
 parameter DMA_LENGTH_WIDTH = 24;
@@ -82,61 +82,61 @@ assign out_req_length = x_length;
 
 always @(posedge req_aclk)
 begin
-	if (req_aresetn == 1'b0) begin
-		req_id <= 2'b0;
-		eot_id <= 2'b0;
-		req_eot <= 1'b0;
-	end else begin
-		if (out_req_valid && out_req_ready) begin
-			req_id <= req_id + 1'b1;
-			last_req[req_id] <= y_length == 0;
-		end
-		req_eot <= 1'b0;
-		if (out_eot) begin
-			eot_id <= eot_id + 1'b1;
-			req_eot <= last_req[eot_id];
-		end
-	end
+  if (req_aresetn == 1'b0) begin
+    req_id <= 2'b0;
+    eot_id <= 2'b0;
+    req_eot <= 1'b0;
+  end else begin
+    if (out_req_valid && out_req_ready) begin
+      req_id <= req_id + 1'b1;
+      last_req[req_id] <= y_length == 0;
+    end
+    req_eot <= 1'b0;
+    if (out_eot) begin
+      eot_id <= eot_id + 1'b1;
+      req_eot <= last_req[eot_id];
+    end
+  end
 end
 
 always @(posedge req_aclk)
 begin
-	if (req_aresetn == 1'b0) begin
-		dest_address <= 'h00;
-		src_address <= 'h00;
-		x_length <= 'h00;
-		y_length <= 'h00;
-		dest_stride <= 'h00;
-		src_stride <= 'h00;
-		req_ready <= 1'b1;
-		out_req_valid <= 1'b0;
-		out_req_sync_transfer_start <= 1'b0;
-	end else begin
-		if (req_ready) begin
-			if (req_valid) begin
-				dest_address <= req_dest_address;
-				src_address <= req_src_address;
-				x_length <= req_x_length;
-				y_length <= req_y_length;
-				dest_stride <= req_dest_stride;
-				src_stride <= req_src_stride;
-				out_req_sync_transfer_start <= req_sync_transfer_start;
-				req_ready <= 1'b0;
-				out_req_valid <= 1'b1;
-			end
-		end else begin
-			if (out_req_valid && out_req_ready) begin
-				dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
-				src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
-				y_length <= y_length - 1'b1;
-				out_req_sync_transfer_start <= 1'b0;
-				if (y_length == 0) begin
-					out_req_valid <= 1'b0;
-					req_ready <= 1'b1;
-				end
-			end
-		end
-	end
+  if (req_aresetn == 1'b0) begin
+    dest_address <= 'h00;
+    src_address <= 'h00;
+    x_length <= 'h00;
+    y_length <= 'h00;
+    dest_stride <= 'h00;
+    src_stride <= 'h00;
+    req_ready <= 1'b1;
+    out_req_valid <= 1'b0;
+    out_req_sync_transfer_start <= 1'b0;
+  end else begin
+    if (req_ready) begin
+      if (req_valid) begin
+        dest_address <= req_dest_address;
+        src_address <= req_src_address;
+        x_length <= req_x_length;
+        y_length <= req_y_length;
+        dest_stride <= req_dest_stride;
+        src_stride <= req_src_stride;
+        out_req_sync_transfer_start <= req_sync_transfer_start;
+        req_ready <= 1'b0;
+        out_req_valid <= 1'b1;
+      end
+    end else begin
+      if (out_req_valid && out_req_ready) begin
+        dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
+        src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
+        y_length <= y_length - 1'b1;
+        out_req_sync_transfer_start <= 1'b0;
+        if (y_length == 0) begin
+          out_req_valid <= 1'b0;
+          req_ready <= 1'b1;
+        end
+      end
+    end
+  end
 end
 
 endmodule
diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v
index 56320b605..8e38486d5 100644
--- a/library/axi_dmac/address_generator.v
+++ b/library/axi_dmac/address_generator.v
@@ -36,32 +36,32 @@
 // ***************************************************************************
 
 module dmac_address_generator (
-	input                        clk,
-	input                        resetn,
+  input                        clk,
+  input                        resetn,
 
-	input                        req_valid,
-	output reg                   req_ready,
-	input [31:BYTES_PER_BEAT_WIDTH] req_address,
-	input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input                        req_valid,
+  output reg                   req_ready,
+  input [31:BYTES_PER_BEAT_WIDTH] req_address,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
 
-	output reg [ID_WIDTH-1:0]  id,
-	input [ID_WIDTH-1:0]       request_id,
-	input                        sync_id,
+  output reg [ID_WIDTH-1:0]  id,
+  input [ID_WIDTH-1:0]       request_id,
+  input                        sync_id,
 
-	input                        eot,
+  input                        eot,
 
-	input                        enable,
-	input                        pause,
-	output reg                   enabled,
+  input                        enable,
+  input                        pause,
+  output reg                   enabled,
 
-	input                        addr_ready,
-	output reg                   addr_valid,
-	output     [31:0]            addr,
-	output     [ 7:0]            len,
-	output     [ 2:0]            size,
-	output     [ 1:0]            burst,
-	output     [ 2:0]            prot,
-	output     [ 3:0]            cache
+  input                        addr_ready,
+  output reg                   addr_valid,
+  output     [31:0]            addr,
+  output     [ 7:0]            len,
+  output     [ 2:0]            size,
+  output     [ 1:0]            burst,
+  output     [ 2:0]            prot,
+  output     [ 3:0]            cache
 );
 
 
@@ -110,52 +110,52 @@ always @(posedge clk) begin
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		last <= 1'b0;
-	end else if (addr_valid == 1'b0) begin
-		last <= eot;
-	end
+  if (resetn == 1'b0) begin
+    last <= 1'b0;
+  end else if (addr_valid == 1'b0) begin
+    last <= eot;
+  end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		address <= 'h00;
-		last_burst_len <= 'h00;
-		req_ready <= 1'b1;
-		addr_valid <= 1'b0;
-	end else begin
-		if (~enabled) begin
-			req_ready <= 1'b1;
-		end else if (req_ready) begin
-			if (req_valid && enable) begin
-				address <= req_address;
-				req_ready <= 1'b0;
-				last_burst_len <= req_last_burst_length;
-			end
-		end else begin
-			if (addr_valid && addr_ready) begin
-				address <= address + MAX_BEATS_PER_BURST;
-				addr_valid <= 1'b0;
-				if (last)
-					req_ready <= 1'b1;
-			end else if (id != request_id && enable) begin
-				addr_valid <= 1'b1;
-			end
-		end
-	end
+  if (resetn == 1'b0) begin
+    address <= 'h00;
+    last_burst_len <= 'h00;
+    req_ready <= 1'b1;
+    addr_valid <= 1'b0;
+  end else begin
+    if (~enabled) begin
+      req_ready <= 1'b1;
+    end else if (req_ready) begin
+      if (req_valid && enable) begin
+        address <= req_address;
+        req_ready <= 1'b0;
+        last_burst_len <= req_last_burst_length;
+      end
+    end else begin
+      if (addr_valid && addr_ready) begin
+        address <= address + MAX_BEATS_PER_BURST;
+        addr_valid <= 1'b0;
+        if (last)
+          req_ready <= 1'b1;
+      end else if (id != request_id && enable) begin
+        addr_valid <= 1'b1;
+      end
+    end
+  end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		id <='h0;
+  if (resetn == 1'b0) begin
+    id <='h0;
     addr_valid_d1 <= 1'b0;
-	end else begin
+  end else begin
     addr_valid_d1 <= addr_valid;
     if ((addr_valid && ~addr_valid_d1) ||
-			(sync_id && id != request_id))
-			id <= inc_id(id);
+      (sync_id && id != request_id))
+      id <= inc_id(id);
 
-	end
+  end
 end
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
index b2503d91c..ac698bd36 100644
--- a/library/axi_dmac/axi_dmac.v
+++ b/library/axi_dmac/axi_dmac.v
@@ -37,141 +37,141 @@
 // ***************************************************************************
 
 module axi_dmac (
-	// Slave AXI interface
-	input s_axi_aclk,
-	input s_axi_aresetn,
+  // Slave AXI interface
+  input s_axi_aclk,
+  input s_axi_aresetn,
 
-	input         s_axi_awvalid,
-	input  [13:0] s_axi_awaddr,
-	output        s_axi_awready,
-	input   [2:0] s_axi_awprot,
-	input         s_axi_wvalid,
-	input  [31:0] s_axi_wdata,
-	input  [ 3:0] s_axi_wstrb,
-	output        s_axi_wready,
-	output        s_axi_bvalid,
-	output [ 1:0] s_axi_bresp,
-	input         s_axi_bready,
-	input         s_axi_arvalid,
-	input  [13:0] s_axi_araddr,
-	output        s_axi_arready,
-	input   [2:0] s_axi_arprot,
-	output        s_axi_rvalid,
-	input         s_axi_rready,
-	output [ 1:0] s_axi_rresp,
-	output [31:0] s_axi_rdata,
+  input         s_axi_awvalid,
+  input  [13:0] s_axi_awaddr,
+  output        s_axi_awready,
+  input   [2:0] s_axi_awprot,
+  input         s_axi_wvalid,
+  input  [31:0] s_axi_wdata,
+  input  [ 3:0] s_axi_wstrb,
+  output        s_axi_wready,
+  output        s_axi_bvalid,
+  output [ 1:0] s_axi_bresp,
+  input         s_axi_bready,
+  input         s_axi_arvalid,
+  input  [13:0] s_axi_araddr,
+  output        s_axi_arready,
+  input   [2:0] s_axi_arprot,
+  output        s_axi_rvalid,
+  input         s_axi_rready,
+  output [ 1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata,
 
-	// Interrupt
-	output reg irq,
+  // Interrupt
+  output reg irq,
 
-	// Master AXI interface
-	input                                    m_dest_axi_aclk,
-	input                                    m_dest_axi_aresetn,
+  // Master AXI interface
+  input                                    m_dest_axi_aclk,
+  input                                    m_dest_axi_aresetn,
 
-	// Write address
-	output [31:0]                            m_dest_axi_awaddr,
-	output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
-	output [ 2:0]                            m_dest_axi_awsize,
-	output [ 1:0]                            m_dest_axi_awburst,
-	output [ 2:0]                            m_dest_axi_awprot,
-	output [ 3:0]                            m_dest_axi_awcache,
-	output                                   m_dest_axi_awvalid,
-	input                                    m_dest_axi_awready,
+  // Write address
+  output [31:0]                            m_dest_axi_awaddr,
+  output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
+  output [ 2:0]                            m_dest_axi_awsize,
+  output [ 1:0]                            m_dest_axi_awburst,
+  output [ 2:0]                            m_dest_axi_awprot,
+  output [ 3:0]                            m_dest_axi_awcache,
+  output                                   m_dest_axi_awvalid,
+  input                                    m_dest_axi_awready,
 
-	// Write data
-	output [DMA_DATA_WIDTH_DEST-1:0]       m_dest_axi_wdata,
-	output [(DMA_DATA_WIDTH_DEST/8)-1:0]   m_dest_axi_wstrb,
-	input                                    m_dest_axi_wready,
-	output                                   m_dest_axi_wvalid,
-	output                                   m_dest_axi_wlast,
+  // Write data
+  output [DMA_DATA_WIDTH_DEST-1:0]       m_dest_axi_wdata,
+  output [(DMA_DATA_WIDTH_DEST/8)-1:0]   m_dest_axi_wstrb,
+  input                                    m_dest_axi_wready,
+  output                                   m_dest_axi_wvalid,
+  output                                   m_dest_axi_wlast,
 
-	// Write response
-	input                                    m_dest_axi_bvalid,
-	input  [ 1:0]                            m_dest_axi_bresp,
-	output                                   m_dest_axi_bready,
+  // Write response
+  input                                    m_dest_axi_bvalid,
+  input  [ 1:0]                            m_dest_axi_bresp,
+  output                                   m_dest_axi_bready,
 
-	// Unused read interface
-	output                                   m_dest_axi_arvalid,
-	output [31:0]                            m_dest_axi_araddr,
-	output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
-	output [ 2:0]                            m_dest_axi_arsize,
-	output [ 1:0]                            m_dest_axi_arburst,
-	output [ 3:0]                            m_dest_axi_arcache,
-	output [ 2:0]                            m_dest_axi_arprot,
-	input                                    m_dest_axi_arready,
-	input                                    m_dest_axi_rvalid,
-	input  [ 1:0]                            m_dest_axi_rresp,
-	input  [DMA_DATA_WIDTH_DEST-1:0]       m_dest_axi_rdata,
-	output                                   m_dest_axi_rready,
+  // Unused read interface
+  output                                   m_dest_axi_arvalid,
+  output [31:0]                            m_dest_axi_araddr,
+  output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
+  output [ 2:0]                            m_dest_axi_arsize,
+  output [ 1:0]                            m_dest_axi_arburst,
+  output [ 3:0]                            m_dest_axi_arcache,
+  output [ 2:0]                            m_dest_axi_arprot,
+  input                                    m_dest_axi_arready,
+  input                                    m_dest_axi_rvalid,
+  input  [ 1:0]                            m_dest_axi_rresp,
+  input  [DMA_DATA_WIDTH_DEST-1:0]       m_dest_axi_rdata,
+  output                                   m_dest_axi_rready,
 
-	// Master AXI interface
-	input                                    m_src_axi_aclk,
-	input                                    m_src_axi_aresetn,
+  // Master AXI interface
+  input                                    m_src_axi_aclk,
+  input                                    m_src_axi_aresetn,
 
-	// Read address
-	input                                    m_src_axi_arready,
-	output                                   m_src_axi_arvalid,
-	output [31:0]                            m_src_axi_araddr,
-	output [7-(4*DMA_AXI_PROTOCOL_SRC):0]  m_src_axi_arlen,
-	output [ 2:0]                            m_src_axi_arsize,
-	output [ 1:0]                            m_src_axi_arburst,
-	output [ 2:0]                            m_src_axi_arprot,
-	output [ 3:0]                            m_src_axi_arcache,
+  // Read address
+  input                                    m_src_axi_arready,
+  output                                   m_src_axi_arvalid,
+  output [31:0]                            m_src_axi_araddr,
+  output [7-(4*DMA_AXI_PROTOCOL_SRC):0]  m_src_axi_arlen,
+  output [ 2:0]                            m_src_axi_arsize,
+  output [ 1:0]                            m_src_axi_arburst,
+  output [ 2:0]                            m_src_axi_arprot,
+  output [ 3:0]                            m_src_axi_arcache,
 
-	// Read data and response
-	input  [DMA_DATA_WIDTH_SRC-1:0]        m_src_axi_rdata,
-	output                                   m_src_axi_rready,
-	input                                    m_src_axi_rvalid,
-	input  [ 1:0]                            m_src_axi_rresp,
+  // Read data and response
+  input  [DMA_DATA_WIDTH_SRC-1:0]        m_src_axi_rdata,
+  output                                   m_src_axi_rready,
+  input                                    m_src_axi_rvalid,
+  input  [ 1:0]                            m_src_axi_rresp,
 
-	// Unused write interface
-	output                                   m_src_axi_awvalid,
-	output [31:0]                            m_src_axi_awaddr,
-	output [7-(4*DMA_AXI_PROTOCOL_SRC):0]  m_src_axi_awlen,
-	output [ 2:0]                            m_src_axi_awsize,
-	output [ 1:0]                            m_src_axi_awburst,
-	output [ 3:0]                            m_src_axi_awcache,
-	output [ 2:0]                            m_src_axi_awprot,
-	input                                    m_src_axi_awready,
-	output                                   m_src_axi_wvalid,
-	output [DMA_DATA_WIDTH_SRC-1:0]        m_src_axi_wdata,
-	output [(DMA_DATA_WIDTH_SRC/8)-1:0]    m_src_axi_wstrb,
-	output                                   m_src_axi_wlast,
-	input                                    m_src_axi_wready,
-	input                                    m_src_axi_bvalid,
-	input  [ 1:0]                            m_src_axi_bresp,
-	output                                   m_src_axi_bready,
+  // Unused write interface
+  output                                   m_src_axi_awvalid,
+  output [31:0]                            m_src_axi_awaddr,
+  output [7-(4*DMA_AXI_PROTOCOL_SRC):0]  m_src_axi_awlen,
+  output [ 2:0]                            m_src_axi_awsize,
+  output [ 1:0]                            m_src_axi_awburst,
+  output [ 3:0]                            m_src_axi_awcache,
+  output [ 2:0]                            m_src_axi_awprot,
+  input                                    m_src_axi_awready,
+  output                                   m_src_axi_wvalid,
+  output [DMA_DATA_WIDTH_SRC-1:0]        m_src_axi_wdata,
+  output [(DMA_DATA_WIDTH_SRC/8)-1:0]    m_src_axi_wstrb,
+  output                                   m_src_axi_wlast,
+  input                                    m_src_axi_wready,
+  input                                    m_src_axi_bvalid,
+  input  [ 1:0]                            m_src_axi_bresp,
+  output                                   m_src_axi_bready,
 
-	// Slave streaming AXI interface
-	input                                    s_axis_aclk,
-	output                                   s_axis_ready,
-	input                                    s_axis_valid,
-	input  [DMA_DATA_WIDTH_SRC-1:0]        s_axis_data,
-	input  [0:0]                             s_axis_user,
-	output                                   s_axis_xfer_req,
+  // Slave streaming AXI interface
+  input                                    s_axis_aclk,
+  output                                   s_axis_ready,
+  input                                    s_axis_valid,
+  input  [DMA_DATA_WIDTH_SRC-1:0]        s_axis_data,
+  input  [0:0]                             s_axis_user,
+  output                                   s_axis_xfer_req,
 
-	// Master streaming AXI interface
-	input                                    m_axis_aclk,
-	input                                    m_axis_ready,
-	output                                   m_axis_valid,
-	output [DMA_DATA_WIDTH_DEST-1:0]       m_axis_data,
+  // Master streaming AXI interface
+  input                                    m_axis_aclk,
+  input                                    m_axis_ready,
+  output                                   m_axis_valid,
+  output [DMA_DATA_WIDTH_DEST-1:0]       m_axis_data,
         output                                   m_axis_last,
         output                                   m_axis_xfer_req,
 
-	// Input FIFO interface
-	input                                    fifo_wr_clk,
-	input                                    fifo_wr_en,
-	input  [DMA_DATA_WIDTH_SRC-1:0]        fifo_wr_din,
-	output                                   fifo_wr_overflow,
-	input                                    fifo_wr_sync,
-	output                                   fifo_wr_xfer_req,
+  // Input FIFO interface
+  input                                    fifo_wr_clk,
+  input                                    fifo_wr_en,
+  input  [DMA_DATA_WIDTH_SRC-1:0]        fifo_wr_din,
+  output                                   fifo_wr_overflow,
+  input                                    fifo_wr_sync,
+  output                                   fifo_wr_xfer_req,
 
-	// Input FIFO interface
-	input                                    fifo_rd_clk,
-	input                                    fifo_rd_en,
-	output                                   fifo_rd_valid,
-	output [DMA_DATA_WIDTH_DEST-1:0]       fifo_rd_dout,
-	output                                   fifo_rd_underflow,
+  // Input FIFO interface
+  input                                    fifo_rd_clk,
+  input                                    fifo_rd_en,
+  output                                   fifo_rd_valid,
+  output [DMA_DATA_WIDTH_DEST-1:0]       fifo_rd_dout,
+  output                                   fifo_rd_underflow,
         output                                   fifo_rd_xfer_req
 );
 
@@ -210,21 +210,21 @@ localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
 
 // Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
 localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
-	DMA_DATA_WIDTH_DEST > 512 ? 7 :
-	DMA_DATA_WIDTH_DEST > 256 ? 6 :
-	DMA_DATA_WIDTH_DEST > 128 ? 5 :
-	DMA_DATA_WIDTH_DEST > 64 ? 4 :
-	DMA_DATA_WIDTH_DEST > 32 ? 3 :
-	DMA_DATA_WIDTH_DEST > 16 ? 2 :
-	DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
+  DMA_DATA_WIDTH_DEST > 512 ? 7 :
+  DMA_DATA_WIDTH_DEST > 256 ? 6 :
+  DMA_DATA_WIDTH_DEST > 128 ? 5 :
+  DMA_DATA_WIDTH_DEST > 64 ? 4 :
+  DMA_DATA_WIDTH_DEST > 32 ? 3 :
+  DMA_DATA_WIDTH_DEST > 16 ? 2 :
+  DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
 localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
-	DMA_DATA_WIDTH_SRC > 512 ? 7 :
-	DMA_DATA_WIDTH_SRC > 256 ? 6 :
-	DMA_DATA_WIDTH_SRC > 128 ? 5 :
-	DMA_DATA_WIDTH_SRC > 64 ? 4 :
-	DMA_DATA_WIDTH_SRC > 32 ? 3 :
-	DMA_DATA_WIDTH_SRC > 16 ? 2 :
-	DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
+  DMA_DATA_WIDTH_SRC > 512 ? 7 :
+  DMA_DATA_WIDTH_SRC > 256 ? 6 :
+  DMA_DATA_WIDTH_SRC > 128 ? 5 :
+  DMA_DATA_WIDTH_SRC > 64 ? 4 :
+  DMA_DATA_WIDTH_SRC > 32 ? 3 :
+  DMA_DATA_WIDTH_SRC > 16 ? 2 :
+  DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
 
 // Register interface signals
 reg  [31:0]  up_rdata = 'd0;
@@ -300,35 +300,35 @@ assign m_src_axi_wstrb = 'd0;
 assign m_src_axi_wlast = 'd0;
 
 up_axi #(
-	.ADDRESS_WIDTH (12)
+  .ADDRESS_WIDTH (12)
 ) i_up_axi (
-	.up_rstn(s_axi_aresetn),
-	.up_clk(s_axi_aclk),
-	.up_axi_awvalid(s_axi_awvalid),
-	.up_axi_awaddr(s_axi_awaddr),
-	.up_axi_awready(s_axi_awready),
-	.up_axi_wvalid(s_axi_wvalid),
-	.up_axi_wdata(s_axi_wdata),
-	.up_axi_wstrb(s_axi_wstrb),
-	.up_axi_wready(s_axi_wready),
-	.up_axi_bvalid(s_axi_bvalid),
-	.up_axi_bresp(s_axi_bresp),
-	.up_axi_bready(s_axi_bready),
-	.up_axi_arvalid(s_axi_arvalid),
-	.up_axi_araddr(s_axi_araddr),
-	.up_axi_arready(s_axi_arready),
-	.up_axi_rvalid(s_axi_rvalid),
-	.up_axi_rresp(s_axi_rresp),
-	.up_axi_rdata(s_axi_rdata),
-	.up_axi_rready(s_axi_rready),
-	.up_wreq(up_wreq),
-	.up_waddr(up_waddr),
-	.up_wdata(up_wdata),
-	.up_wack(up_wack),
-	.up_rreq(up_rreq),
-	.up_raddr(up_raddr),
-	.up_rdata(up_rdata),
-	.up_rack(up_rack)
+  .up_rstn(s_axi_aresetn),
+  .up_clk(s_axi_aclk),
+  .up_axi_awvalid(s_axi_awvalid),
+  .up_axi_awaddr(s_axi_awaddr),
+  .up_axi_awready(s_axi_awready),
+  .up_axi_wvalid(s_axi_wvalid),
+  .up_axi_wdata(s_axi_wdata),
+  .up_axi_wstrb(s_axi_wstrb),
+  .up_axi_wready(s_axi_wready),
+  .up_axi_bvalid(s_axi_bvalid),
+  .up_axi_bresp(s_axi_bresp),
+  .up_axi_bready(s_axi_bready),
+  .up_axi_arvalid(s_axi_arvalid),
+  .up_axi_araddr(s_axi_araddr),
+  .up_axi_arready(s_axi_arready),
+  .up_axi_rvalid(s_axi_rvalid),
+  .up_axi_rresp(s_axi_rresp),
+  .up_axi_rdata(s_axi_rdata),
+  .up_axi_rready(s_axi_rready),
+  .up_wreq(up_wreq),
+  .up_waddr(up_waddr),
+  .up_wdata(up_wdata),
+  .up_wack(up_wack),
+  .up_rreq(up_rreq),
+  .up_raddr(up_raddr),
+  .up_rdata(up_rdata),
+  .up_rack(up_rack)
 );
 
 // IRQ handling
@@ -338,124 +338,124 @@ assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 12'h021) ? up_wdata
 
 always @(posedge s_axi_aclk)
 begin
-	if (s_axi_aresetn == 1'b0)
-		irq <= 1'b0;
-	else
-		irq <= |up_irq_pending;
+  if (s_axi_aresetn == 1'b0)
+    irq <= 1'b0;
+  else
+    irq <= |up_irq_pending;
 end
 
 always @(posedge s_axi_aclk)
 begin
-	if (s_axi_aresetn == 1'b0) begin
-		up_irq_source <= 2'b00;
-	end else begin
-		up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
-	end
+  if (s_axi_aresetn == 1'b0) begin
+    up_irq_source <= 2'b00;
+  end else begin
+    up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
+  end
 end
 
 // Register Interface
 
 always @(posedge s_axi_aclk)
 begin
-	if (s_axi_aresetn == 1'b0) begin
-		up_enable <= 'h00;
-		up_pause <= 'h00;
-		up_dma_src_address <= 'h00;
-		up_dma_dest_address <= 'h00;
-		up_dma_y_length <= 'h00;
-		up_dma_x_length <= 'h00;
-		up_dma_dest_stride <= 'h00;
-		up_dma_src_stride <= 'h00;
-		up_irq_mask <= 3'b11;
-		up_dma_req_valid <= 1'b0;
-		up_scratch <= 'h00;
-		up_wack <= 1'b0;
-	end else begin
-		up_wack <= up_wreq;
-		if (up_enable == 1'b1) begin
-			if (up_wreq && up_waddr == 12'h102) begin
-				up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
-			end else if (up_sot) begin
-				up_dma_req_valid <= 1'b0;
-			end
-		end else begin
-			up_dma_req_valid <= 1'b0;
-		end
+  if (s_axi_aresetn == 1'b0) begin
+    up_enable <= 'h00;
+    up_pause <= 'h00;
+    up_dma_src_address <= 'h00;
+    up_dma_dest_address <= 'h00;
+    up_dma_y_length <= 'h00;
+    up_dma_x_length <= 'h00;
+    up_dma_dest_stride <= 'h00;
+    up_dma_src_stride <= 'h00;
+    up_irq_mask <= 3'b11;
+    up_dma_req_valid <= 1'b0;
+    up_scratch <= 'h00;
+    up_wack <= 1'b0;
+  end else begin
+    up_wack <= up_wreq;
+    if (up_enable == 1'b1) begin
+      if (up_wreq && up_waddr == 12'h102) begin
+        up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
+      end else if (up_sot) begin
+        up_dma_req_valid <= 1'b0;
+      end
+    end else begin
+      up_dma_req_valid <= 1'b0;
+    end
 
-		if (up_wreq) begin
-			case (up_waddr)
-			12'h002: up_scratch <= up_wdata;
-			12'h020: up_irq_mask <= up_wdata;
-			12'h100: {up_pause, up_enable} <= up_wdata[1:0];
+    if (up_wreq) begin
+      case (up_waddr)
+      12'h002: up_scratch <= up_wdata;
+      12'h020: up_irq_mask <= up_wdata;
+      12'h100: {up_pause, up_enable} <= up_wdata[1:0];
                         12'h103: begin
                           if (CYCLIC) up_dma_cyclic <= up_wdata[0];
                           up_axis_xlast <= up_wdata[1];
                         end
-			12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
-			12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
-			12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
-			12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
-			12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
-			12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
-			endcase
-		end
-	end
+      12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
+      12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
+      12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+      12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+      12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+      12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+      endcase
+    end
+  end
 end
 
 always @(posedge s_axi_aclk)
 begin
-	if (s_axi_aresetn == 1'b0) begin
+  if (s_axi_aresetn == 1'b0) begin
     up_rack <= 'd0;
-		up_rdata <= 'h00;
-	end else begin
+    up_rdata <= 'h00;
+  end else begin
     up_rack <= up_rreq;
-		case (up_raddr)
-		12'h000: up_rdata <= PCORE_VERSION;
-		12'h001: up_rdata <= ID;
-		12'h002: up_rdata <= up_scratch;
-		12'h020: up_rdata <= up_irq_mask;
-		12'h021: up_rdata <= up_irq_pending;
-		12'h022: up_rdata <= up_irq_source;
-		12'h100: up_rdata <= {up_pause, up_enable};
-		12'h101: up_rdata <= up_transfer_id;
-		12'h102: up_rdata <= up_dma_req_valid;
-		12'h103: up_rdata <= {30'h00, up_axis_xlast, up_dma_cyclic}; // Flags
-		12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
-		12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
-		12'h106: up_rdata <= up_dma_x_length;
-		12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00;
-		12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00;
-		12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00;
-		12'h10a: up_rdata <= up_transfer_done_bitmap;
-		12'h10b: up_rdata <= up_transfer_id_eot;
-		12'h10c: up_rdata <= 'h00; // Status
-		12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
-		12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
-		12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id,
-							1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id};
-		12'h110: up_rdata <= dbg_status;
-		default: up_rdata <= 'h00;
-		endcase
-	end
+    case (up_raddr)
+    12'h000: up_rdata <= PCORE_VERSION;
+    12'h001: up_rdata <= ID;
+    12'h002: up_rdata <= up_scratch;
+    12'h020: up_rdata <= up_irq_mask;
+    12'h021: up_rdata <= up_irq_pending;
+    12'h022: up_rdata <= up_irq_source;
+    12'h100: up_rdata <= {up_pause, up_enable};
+    12'h101: up_rdata <= up_transfer_id;
+    12'h102: up_rdata <= up_dma_req_valid;
+    12'h103: up_rdata <= {30'h00, up_axis_xlast, up_dma_cyclic}; // Flags
+    12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
+    12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
+    12'h106: up_rdata <= up_dma_x_length;
+    12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00;
+    12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00;
+    12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00;
+    12'h10a: up_rdata <= up_transfer_done_bitmap;
+    12'h10b: up_rdata <= up_transfer_id_eot;
+    12'h10c: up_rdata <= 'h00; // Status
+    12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
+    12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
+    12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id,
+              1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id};
+    12'h110: up_rdata <= dbg_status;
+    default: up_rdata <= 'h00;
+    endcase
+  end
 end
 
 // Request ID and Request done bitmap handling
 always @(posedge s_axi_aclk)
 begin
-	if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin
-		up_transfer_id <= 'h0;
-		up_transfer_id_eot <= 'h0;
-		up_transfer_done_bitmap <= 'h0;
-	end begin
-		if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin
-			up_transfer_id <= up_transfer_id + 1'b1;
-			up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
-		end
-		if (up_eot == 1'b1) begin
-			up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
-			up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
-		end
-	end
+  if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin
+    up_transfer_id <= 'h0;
+    up_transfer_id_eot <= 'h0;
+    up_transfer_done_bitmap <= 'h0;
+  end begin
+    if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin
+      up_transfer_id <= up_transfer_id + 1'b1;
+      up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
+    end
+    if (up_eot == 1'b1) begin
+      up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
+      up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
+    end
+  end
 end
 
 wire dma_req_valid;
@@ -474,32 +474,32 @@ assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot;
 generate if (DMA_2D_TRANSFER == 1) begin
 
 dmac_2d_transfer #(
-	.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
-	.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
-	.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
+  .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+  .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
+  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
 ) i_2d_transfer (
-	.req_aclk(s_axi_aclk),
-	.req_aresetn(s_axi_aresetn),
+  .req_aclk(s_axi_aclk),
+  .req_aresetn(s_axi_aresetn),
 
-	.req_eot(up_req_eot),
+  .req_eot(up_req_eot),
 
-	.req_valid(up_dma_req_valid),
-	.req_ready(up_dma_req_ready),
-	.req_dest_address(up_dma_dest_address),
-	.req_src_address(up_dma_src_address),
-	.req_x_length(up_dma_x_length),
-	.req_y_length(up_dma_y_length),
-	.req_dest_stride(up_dma_dest_stride),
-	.req_src_stride(up_dma_src_stride),
-	.req_sync_transfer_start(up_dma_sync_transfer_start),
+  .req_valid(up_dma_req_valid),
+  .req_ready(up_dma_req_ready),
+  .req_dest_address(up_dma_dest_address),
+  .req_src_address(up_dma_src_address),
+  .req_x_length(up_dma_x_length),
+  .req_y_length(up_dma_y_length),
+  .req_dest_stride(up_dma_dest_stride),
+  .req_src_stride(up_dma_src_stride),
+  .req_sync_transfer_start(up_dma_sync_transfer_start),
 
-	.out_req_valid(dma_req_valid),
-	.out_req_ready(dma_req_ready),
-	.out_req_dest_address(dma_req_dest_address),
-	.out_req_src_address(dma_req_src_address),
-	.out_req_length(dma_req_length),
-	.out_req_sync_transfer_start(dma_req_sync_transfer_start),
-	.out_eot(dma_req_eot)
+  .out_req_valid(dma_req_valid),
+  .out_req_ready(dma_req_ready),
+  .out_req_dest_address(dma_req_dest_address),
+  .out_req_src_address(dma_req_src_address),
+  .out_req_length(dma_req_length),
+  .out_req_sync_transfer_start(dma_req_sync_transfer_start),
+  .out_eot(dma_req_eot)
 );
 
 end else begin
@@ -515,123 +515,123 @@ assign up_req_eot = dma_req_eot;
 end endgenerate
 
 dmac_request_arb #(
-	.DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
-	.DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
-	.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
-	.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
-	.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
-	.DMA_TYPE_DEST(DMA_TYPE_DEST),
-	.DMA_TYPE_SRC(DMA_TYPE_SRC),
-	.ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
-	.ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
-	.ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
-	.AXI_SLICE_DEST(AXI_SLICE_DEST),
-	.AXI_SLICE_SRC(AXI_SLICE_SRC),
-	.MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
-	.FIFO_SIZE(FIFO_SIZE)
+  .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
+  .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
+  .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+  .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
+  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
+  .DMA_TYPE_DEST(DMA_TYPE_DEST),
+  .DMA_TYPE_SRC(DMA_TYPE_SRC),
+  .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
+  .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
+  .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
+  .AXI_SLICE_DEST(AXI_SLICE_DEST),
+  .AXI_SLICE_SRC(AXI_SLICE_SRC),
+  .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
+  .FIFO_SIZE(FIFO_SIZE)
 ) i_request_arb (
-	.req_aclk(s_axi_aclk),
-	.req_aresetn(s_axi_aresetn),
+  .req_aclk(s_axi_aclk),
+  .req_aresetn(s_axi_aresetn),
 
-	.enable(up_enable),
-	.pause(up_pause),
+  .enable(up_enable),
+  .pause(up_pause),
 
-	.req_valid(dma_req_valid),
-	.req_ready(dma_req_ready),
-	.req_dest_address(dma_req_dest_address),
-	.req_src_address(dma_req_src_address),
-	.req_length(dma_req_length),
+  .req_valid(dma_req_valid),
+  .req_ready(dma_req_ready),
+  .req_dest_address(dma_req_dest_address),
+  .req_src_address(dma_req_src_address),
+  .req_length(dma_req_length),
         .req_xlast(up_axis_xlast),
-	.req_sync_transfer_start(dma_req_sync_transfer_start),
+  .req_sync_transfer_start(dma_req_sync_transfer_start),
 
-	.eot(dma_req_eot),
+  .eot(dma_req_eot),
 
 
-	.m_dest_axi_aclk(m_dest_axi_aclk),
-	.m_dest_axi_aresetn(m_dest_axi_aresetn),
-	.m_src_axi_aclk(m_src_axi_aclk),
-	.m_src_axi_aresetn(m_src_axi_aresetn),
+  .m_dest_axi_aclk(m_dest_axi_aclk),
+  .m_dest_axi_aresetn(m_dest_axi_aresetn),
+  .m_src_axi_aclk(m_src_axi_aclk),
+  .m_src_axi_aresetn(m_src_axi_aresetn),
 
 
-	.m_axi_awaddr(m_dest_axi_awaddr),
-	.m_axi_awlen(m_dest_axi_awlen),
-	.m_axi_awsize(m_dest_axi_awsize),
-	.m_axi_awburst(m_dest_axi_awburst),
-	.m_axi_awprot(m_dest_axi_awprot),
-	.m_axi_awcache(m_dest_axi_awcache),
-	.m_axi_awvalid(m_dest_axi_awvalid),
-	.m_axi_awready(m_dest_axi_awready),
+  .m_axi_awaddr(m_dest_axi_awaddr),
+  .m_axi_awlen(m_dest_axi_awlen),
+  .m_axi_awsize(m_dest_axi_awsize),
+  .m_axi_awburst(m_dest_axi_awburst),
+  .m_axi_awprot(m_dest_axi_awprot),
+  .m_axi_awcache(m_dest_axi_awcache),
+  .m_axi_awvalid(m_dest_axi_awvalid),
+  .m_axi_awready(m_dest_axi_awready),
 
 
-	.m_axi_wdata(m_dest_axi_wdata),
-	.m_axi_wstrb(m_dest_axi_wstrb),
-	.m_axi_wready(m_dest_axi_wready),
-	.m_axi_wvalid(m_dest_axi_wvalid),
-	.m_axi_wlast(m_dest_axi_wlast),
+  .m_axi_wdata(m_dest_axi_wdata),
+  .m_axi_wstrb(m_dest_axi_wstrb),
+  .m_axi_wready(m_dest_axi_wready),
+  .m_axi_wvalid(m_dest_axi_wvalid),
+  .m_axi_wlast(m_dest_axi_wlast),
 
 
-	.m_axi_bvalid(m_dest_axi_bvalid),
-	.m_axi_bresp(m_dest_axi_bresp),
-	.m_axi_bready(m_dest_axi_bready),
+  .m_axi_bvalid(m_dest_axi_bvalid),
+  .m_axi_bresp(m_dest_axi_bresp),
+  .m_axi_bready(m_dest_axi_bready),
 
 
-	.m_axi_arready(m_src_axi_arready),
-	.m_axi_arvalid(m_src_axi_arvalid),
-	.m_axi_araddr(m_src_axi_araddr),
-	.m_axi_arlen(m_src_axi_arlen),
-	.m_axi_arsize(m_src_axi_arsize),
-	.m_axi_arburst(m_src_axi_arburst),
-	.m_axi_arprot(m_src_axi_arprot),
-	.m_axi_arcache(m_src_axi_arcache),
+  .m_axi_arready(m_src_axi_arready),
+  .m_axi_arvalid(m_src_axi_arvalid),
+  .m_axi_araddr(m_src_axi_araddr),
+  .m_axi_arlen(m_src_axi_arlen),
+  .m_axi_arsize(m_src_axi_arsize),
+  .m_axi_arburst(m_src_axi_arburst),
+  .m_axi_arprot(m_src_axi_arprot),
+  .m_axi_arcache(m_src_axi_arcache),
 
 
-	.m_axi_rdata(m_src_axi_rdata),
-	.m_axi_rready(m_src_axi_rready),
-	.m_axi_rvalid(m_src_axi_rvalid),
-	.m_axi_rresp(m_src_axi_rresp),
+  .m_axi_rdata(m_src_axi_rdata),
+  .m_axi_rready(m_src_axi_rready),
+  .m_axi_rvalid(m_src_axi_rvalid),
+  .m_axi_rresp(m_src_axi_rresp),
 
 
-	.s_axis_aclk(s_axis_aclk),
-	.s_axis_ready(s_axis_ready),
-	.s_axis_valid(s_axis_valid),
-	.s_axis_data(s_axis_data),
-	.s_axis_user(s_axis_user),
-	.s_axis_xfer_req(s_axis_xfer_req),
+  .s_axis_aclk(s_axis_aclk),
+  .s_axis_ready(s_axis_ready),
+  .s_axis_valid(s_axis_valid),
+  .s_axis_data(s_axis_data),
+  .s_axis_user(s_axis_user),
+  .s_axis_xfer_req(s_axis_xfer_req),
 
 
-	.m_axis_aclk(m_axis_aclk),
-	.m_axis_ready(m_axis_ready),
-	.m_axis_valid(m_axis_valid),
-	.m_axis_data(m_axis_data),
+  .m_axis_aclk(m_axis_aclk),
+  .m_axis_ready(m_axis_ready),
+  .m_axis_valid(m_axis_valid),
+  .m_axis_data(m_axis_data),
         .m_axis_last(m_axis_last),
         .m_axis_xfer_req(m_axis_xfer_req),
 
 
-	.fifo_wr_clk(fifo_wr_clk),
-	.fifo_wr_en(fifo_wr_en),
-	.fifo_wr_din(fifo_wr_din),
-	.fifo_wr_overflow(fifo_wr_overflow),
-	.fifo_wr_sync(fifo_wr_sync),
-	.fifo_wr_xfer_req(fifo_wr_xfer_req),
+  .fifo_wr_clk(fifo_wr_clk),
+  .fifo_wr_en(fifo_wr_en),
+  .fifo_wr_din(fifo_wr_din),
+  .fifo_wr_overflow(fifo_wr_overflow),
+  .fifo_wr_sync(fifo_wr_sync),
+  .fifo_wr_xfer_req(fifo_wr_xfer_req),
 
 
-	.fifo_rd_clk(fifo_rd_clk),
-	.fifo_rd_en(fifo_rd_en),
-	.fifo_rd_valid(fifo_rd_valid),
-	.fifo_rd_dout(fifo_rd_dout),
-	.fifo_rd_underflow(fifo_rd_underflow),
+  .fifo_rd_clk(fifo_rd_clk),
+  .fifo_rd_en(fifo_rd_en),
+  .fifo_rd_valid(fifo_rd_valid),
+  .fifo_rd_dout(fifo_rd_dout),
+  .fifo_rd_underflow(fifo_rd_underflow),
         .fifo_rd_xfer_req(fifo_rd_xfer_req),
 
-	// DBG
-	.dbg_dest_request_id(dest_request_id),
-	.dbg_dest_address_id(dest_address_id),
-	.dbg_dest_data_id(dest_data_id),
-	.dbg_dest_response_id(dest_response_id),
-	.dbg_src_request_id(src_request_id),
-	.dbg_src_address_id(src_address_id),
-	.dbg_src_data_id(src_data_id),
-	.dbg_src_response_id(src_response_id),
-	.dbg_status(dbg_status)
+  // DBG
+  .dbg_dest_request_id(dest_request_id),
+  .dbg_dest_address_id(dest_address_id),
+  .dbg_dest_data_id(dest_data_id),
+  .dbg_dest_response_id(dest_response_id),
+  .dbg_src_request_id(src_request_id),
+  .dbg_src_address_id(src_address_id),
+  .dbg_src_data_id(src_data_id),
+  .dbg_src_response_id(src_response_id),
+  .dbg_status(dbg_status)
 );
 
 assign m_dest_axi_arvalid = 1'b0;
diff --git a/library/axi_dmac/axi_register_slice.v b/library/axi_dmac/axi_register_slice.v
index d685b8db6..159f0d0fe 100644
--- a/library/axi_dmac/axi_register_slice.v
+++ b/library/axi_dmac/axi_register_slice.v
@@ -36,16 +36,16 @@
 // ***************************************************************************
 
 module axi_register_slice (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input s_axi_valid,
-	output s_axi_ready,
-	input [DATA_WIDTH-1:0] s_axi_data,
+  input s_axi_valid,
+  output s_axi_ready,
+  input [DATA_WIDTH-1:0] s_axi_data,
 
-	output m_axi_valid,
-	input m_axi_ready,
-	output [DATA_WIDTH-1:0] m_axi_data
+  output m_axi_valid,
+  input m_axi_ready,
+  output [DATA_WIDTH-1:0] m_axi_data
 );
 
 parameter DATA_WIDTH = 32;
@@ -79,19 +79,19 @@ assign fwd_valid_s = fwd_valid;
 assign fwd_data_s = fwd_data;
 
 always @(posedge clk) begin
-	if (~fwd_valid | m_axi_ready)
-		fwd_data <= bwd_data_s;
+  if (~fwd_valid | m_axi_ready)
+    fwd_data <= bwd_data_s;
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		fwd_valid <= 1'b0;
-	end else begin 
-		if (bwd_valid_s)
-			fwd_valid <= 1'b1;
-		else if (m_axi_ready)
-			fwd_valid <= 1'b0;
-	end
+  if (resetn == 1'b0) begin
+    fwd_valid <= 1'b0;
+  end else begin 
+    if (bwd_valid_s)
+      fwd_valid <= 1'b1;
+    else if (m_axi_ready)
+      fwd_valid <= 1'b0;
+  end
 end
 
 end else begin
@@ -111,19 +111,19 @@ assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
 assign bwd_ready_s = bwd_ready;
 
 always @(posedge clk) begin
-	if (bwd_ready)
-		bwd_data <= s_axi_data;
+  if (bwd_ready)
+    bwd_data <= s_axi_data;
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		bwd_ready <= 1'b1;
-	end else begin
-		if (fwd_ready_s)
-			bwd_ready <= 1'b1;
-		else if (s_axi_valid)
-			bwd_ready <= 1'b0;
-	end
+  if (resetn == 1'b0) begin
+    bwd_ready <= 1'b1;
+  end else begin
+    if (fwd_ready_s)
+      bwd_ready <= 1'b1;
+    else if (s_axi_valid)
+      bwd_ready <= 1'b0;
+  end
 end
 
 end else begin
diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v
index 714e28cb2..1f1b9dc04 100644
--- a/library/axi_dmac/data_mover.v
+++ b/library/axi_dmac/data_mover.v
@@ -37,31 +37,31 @@
 // ***************************************************************************
 
 module dmac_data_mover (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input [ID_WIDTH-1:0] request_id,
-	output [ID_WIDTH-1:0] response_id,
-	input sync_id,
-	input eot,
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  input sync_id,
+  input eot,
 
-	input enable,
-	output reg enabled,
+  input enable,
+  output reg enabled,
 
-	output xfer_req,
+  output xfer_req,
 
-	output s_axi_ready,
-	input s_axi_valid,
-	input [DATA_WIDTH-1:0] s_axi_data,
+  output s_axi_ready,
+  input s_axi_valid,
+  input [DATA_WIDTH-1:0] s_axi_data,
 
-	input m_axi_ready,
-	output m_axi_valid,
-	output [DATA_WIDTH-1:0] m_axi_data,
-	output m_axi_last,
+  input m_axi_ready,
+  output m_axi_valid,
+  output [DATA_WIDTH-1:0] m_axi_data,
+  output m_axi_last,
 
-	input req_valid,
-	output req_ready,
-	input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
 );
 
 parameter ID_WIDTH = 3;
@@ -104,73 +104,73 @@ assign last_load = s_axi_ready && s_axi_valid && last_eot && eot;
 assign req_ready = last_load || ~active;
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		enabled <= 1'b0;
-	end else begin
-		if (enable) begin
-			enabled <= 1'b1;
-		end else begin
-			if (DISABLE_WAIT_FOR_ID == 0) begin
-				// We are not allowed to just deassert valid, so wait until the
-				// current beat has been accepted
-				if (~s_axi_valid || m_axi_ready)
-					enabled <= 1'b0;
-			end else begin
-				// For memory mapped AXI busses we have to complete all pending
-				// burst requests before we can disable the data mover.
-				if (response_id == request_id)
-					enabled <= 1'b0;
-			end
-		end
-	end
+  if (resetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+    if (enable) begin
+      enabled <= 1'b1;
+    end else begin
+      if (DISABLE_WAIT_FOR_ID == 0) begin
+        // We are not allowed to just deassert valid, so wait until the
+        // current beat has been accepted
+        if (~s_axi_valid || m_axi_ready)
+          enabled <= 1'b0;
+      end else begin
+        // For memory mapped AXI busses we have to complete all pending
+        // burst requests before we can disable the data mover.
+        if (response_id == request_id)
+          enabled <= 1'b0;
+      end
+    end
+  end
 end
 
 always @(posedge clk) begin
-	if (req_ready) begin
-		last_eot <= req_last_burst_length == 'h0; 
-		last_non_eot <= 1'b0;
-		beat_counter <= 'h1;
-	end else if (s_axi_ready && s_axi_valid) begin
-		last_eot <= beat_counter == last_burst_length;
-		last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1;
-		beat_counter <= beat_counter + 1;
-	end
+  if (req_ready) begin
+    last_eot <= req_last_burst_length == 'h0; 
+    last_non_eot <= 1'b0;
+    beat_counter <= 'h1;
+  end else if (s_axi_ready && s_axi_valid) begin
+    last_eot <= beat_counter == last_burst_length;
+    last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1;
+    beat_counter <= beat_counter + 1;
+  end
 end
 
 always @(posedge clk) begin
-	if (req_ready)
-		last_burst_length <= req_last_burst_length;
+  if (req_ready)
+    last_burst_length <= req_last_burst_length;
 end
 
 always @(posedge clk) begin
-	if (enabled == 1'b0 || resetn == 1'b0) begin
-		active <= 1'b0;
-	end else if (req_valid) begin
-		active <= 1'b1;
-	end else if (last_load) begin
-		active <= 1'b0;
-	end
+  if (enabled == 1'b0 || resetn == 1'b0) begin
+    active <= 1'b0;
+  end else if (req_valid) begin
+    active <= 1'b1;
+  end else if (last_load) begin
+    active <= 1'b0;
+  end
 end
 
 always @(*)
 begin
-	if ((s_axi_ready && s_axi_valid && last) ||
-		(sync_id && pending_burst))
-		id_next <= inc_id(id);
-	else
-		id_next <= id;
+  if ((s_axi_ready && s_axi_valid && last) ||
+    (sync_id && pending_burst))
+    id_next <= inc_id(id);
+  else
+    id_next <= id;
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		id <= 'h0;
-	end else begin
-		id <= id_next;
-	end
+  if (resetn == 1'b0) begin
+    id <= 'h0;
+  end else begin
+    id <= id_next;
+  end
 end
 
 always @(posedge clk) begin
-	pending_burst <= id_next != request_id;
+  pending_burst <= id_next != request_id;
 end
 
 endmodule
diff --git a/library/axi_dmac/dest_axi_mm.v b/library/axi_dmac/dest_axi_mm.v
index ddf995c93..93f351e3f 100644
--- a/library/axi_dmac/dest_axi_mm.v
+++ b/library/axi_dmac/dest_axi_mm.v
@@ -37,60 +37,60 @@
 // ***************************************************************************
 
 module dmac_dest_mm_axi (
-	input                               m_axi_aclk,
-	input                               m_axi_aresetn,
+  input                               m_axi_aclk,
+  input                               m_axi_aresetn,
 
-	input                               req_valid,
-	output                              req_ready,
-	input [31:BYTES_PER_BEAT_WIDTH]   req_address,
-	input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
-	input [BYTES_PER_BEAT_WIDTH-1:0]  req_last_beat_bytes,
+  input                               req_valid,
+  output                              req_ready,
+  input [31:BYTES_PER_BEAT_WIDTH]   req_address,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input [BYTES_PER_BEAT_WIDTH-1:0]  req_last_beat_bytes,
 
-	input                               enable,
-	output                              enabled,
-	input                               pause,
-	input                               sync_id,
-	output                              sync_id_ret,
+  input                               enable,
+  output                              enabled,
+  input                               pause,
+  input                               sync_id,
+  output                              sync_id_ret,
 
-	output                              response_valid,
-	input                               response_ready,
-	output [1:0]                        response_resp,
-	output                              response_resp_eot,
+  output                              response_valid,
+  input                               response_ready,
+  output [1:0]                        response_resp,
+  output                              response_resp_eot,
 
-	input  [ID_WIDTH-1:0]             request_id,
-	output [ID_WIDTH-1:0]             response_id,
+  input  [ID_WIDTH-1:0]             request_id,
+  output [ID_WIDTH-1:0]             response_id,
 
-	output [ID_WIDTH-1:0]             data_id,
-	output [ID_WIDTH-1:0]             address_id,
-	input                               data_eot,
-	input                               address_eot,
-	input                               response_eot,
+  output [ID_WIDTH-1:0]             data_id,
+  output [ID_WIDTH-1:0]             address_id,
+  input                               data_eot,
+  input                               address_eot,
+  input                               response_eot,
 
-	input                               fifo_valid,
-	output                              fifo_ready,
-	input [DMA_DATA_WIDTH-1:0]        fifo_data,
+  input                               fifo_valid,
+  output                              fifo_ready,
+  input [DMA_DATA_WIDTH-1:0]        fifo_data,
 
-	// Write address
-	input                               m_axi_awready,
-	output                              m_axi_awvalid,
-	output [31:0]                       m_axi_awaddr,
-	output [ 7:0]                       m_axi_awlen,
-	output [ 2:0]                       m_axi_awsize,
-	output [ 1:0]                       m_axi_awburst,
-	output [ 2:0]                       m_axi_awprot,
-	output [ 3:0]                       m_axi_awcache,
+  // Write address
+  input                               m_axi_awready,
+  output                              m_axi_awvalid,
+  output [31:0]                       m_axi_awaddr,
+  output [ 7:0]                       m_axi_awlen,
+  output [ 2:0]                       m_axi_awsize,
+  output [ 1:0]                       m_axi_awburst,
+  output [ 2:0]                       m_axi_awprot,
+  output [ 3:0]                       m_axi_awcache,
 
-	// Write data
-	output [DMA_DATA_WIDTH-1:0]     m_axi_wdata,
-	output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb,
-	input                               m_axi_wready,
-	output                              m_axi_wvalid,
-	output                              m_axi_wlast,
+  // Write data
+  output [DMA_DATA_WIDTH-1:0]     m_axi_wdata,
+  output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb,
+  input                               m_axi_wready,
+  output                              m_axi_wvalid,
+  output                              m_axi_wlast,
 
-	// Write response
-	input                               m_axi_bvalid,
-	input  [ 1:0]                       m_axi_bresp,
-	output                              m_axi_bready
+  // Write response
+  input                               m_axi_bvalid,
+  input  [ 1:0]                       m_axi_bresp,
+  output                              m_axi_bready
 );
 
 parameter ID_WIDTH = 3;
@@ -113,120 +113,120 @@ wire _fifo_ready;
 assign fifo_ready = _fifo_ready | ~enabled;
 
 splitter #(
-	.NUM_M(2)
+  .NUM_M(2)
 ) i_req_splitter (
-	.clk(m_axi_aclk),
-	.resetn(m_axi_aresetn),
-	.s_valid(req_valid),
-	.s_ready(req_ready),
-	.m_valid({
-		address_req_valid,
-		data_req_valid
-	}),
-	.m_ready({
-		address_req_ready,
-		data_req_ready
-	})
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+  .s_valid(req_valid),
+  .s_ready(req_ready),
+  .m_valid({
+    address_req_valid,
+    data_req_valid
+  }),
+  .m_ready({
+    address_req_ready,
+    data_req_ready
+  })
 );
 
 dmac_address_generator #(
-	.ID_WIDTH(ID_WIDTH),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
-	.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
-	.DMA_DATA_WIDTH(DMA_DATA_WIDTH)
+  .ID_WIDTH(ID_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
+  .DMA_DATA_WIDTH(DMA_DATA_WIDTH)
 ) i_addr_gen (
-	.clk(m_axi_aclk),
-	.resetn(m_axi_aresetn),
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
 
-	.enable(enable),
-	.enabled(address_enabled),
-	.pause(pause),
+  .enable(enable),
+  .enabled(address_enabled),
+  .pause(pause),
 
-	.id(address_id),
-	.request_id(request_id),
-	.sync_id(sync_id),
+  .id(address_id),
+  .request_id(request_id),
+  .sync_id(sync_id),
 
-	.req_valid(address_req_valid),
-	.req_ready(address_req_ready),
-	.req_address(req_address),
-	.req_last_burst_length(req_last_burst_length),
+  .req_valid(address_req_valid),
+  .req_ready(address_req_ready),
+  .req_address(req_address),
+  .req_last_burst_length(req_last_burst_length),
 
-	.eot(address_eot),
+  .eot(address_eot),
 
-	.addr_ready(m_axi_awready),
-	.addr_valid(m_axi_awvalid),
-	.addr(m_axi_awaddr),
-	.len(m_axi_awlen),
-	.size(m_axi_awsize),
-	.burst(m_axi_awburst),
-	.prot(m_axi_awprot),
-	.cache(m_axi_awcache)
+  .addr_ready(m_axi_awready),
+  .addr_valid(m_axi_awvalid),
+  .addr(m_axi_awaddr),
+  .len(m_axi_awlen),
+  .size(m_axi_awsize),
+  .burst(m_axi_awburst),
+  .prot(m_axi_awprot),
+  .cache(m_axi_awcache)
 );
 
 dmac_data_mover # (
-	.ID_WIDTH(ID_WIDTH),
-	.DATA_WIDTH(DMA_DATA_WIDTH),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DMA_DATA_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
 ) i_data_mover (
-	.clk(m_axi_aclk),
-	.resetn(m_axi_aresetn),
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
 
-	.enable(address_enabled),
-	.enabled(data_enabled),
+  .enable(address_enabled),
+  .enabled(data_enabled),
 
-	.xfer_req(),
+  .xfer_req(),
 
-	.request_id(address_id),
-	.response_id(data_id),
-	.sync_id(sync_id),
-	.eot(data_eot),
+  .request_id(address_id),
+  .response_id(data_id),
+  .sync_id(sync_id),
+  .eot(data_eot),
 
-	.req_valid(data_req_valid),
-	.req_ready(data_req_ready),
-	.req_last_burst_length(req_last_burst_length),
+  .req_valid(data_req_valid),
+  .req_ready(data_req_ready),
+  .req_last_burst_length(req_last_burst_length),
 
-	.s_axi_valid(fifo_valid),
-	.s_axi_ready(_fifo_ready),
-	.s_axi_data(fifo_data),
-	.m_axi_valid(m_axi_wvalid),
-	.m_axi_ready(m_axi_wready),
-	.m_axi_data(m_axi_wdata),
-	.m_axi_last(m_axi_wlast)
+  .s_axi_valid(fifo_valid),
+  .s_axi_ready(_fifo_ready),
+  .s_axi_data(fifo_data),
+  .m_axi_valid(m_axi_wvalid),
+  .m_axi_ready(m_axi_wready),
+  .m_axi_data(m_axi_wdata),
+  .m_axi_last(m_axi_wlast)
 );
 
 always @(*)
 begin
-	if (data_eot & m_axi_wlast) begin
-		wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
-	end else begin
-		wstrb <= {(DMA_DATA_WIDTH/8){1'b1}};
-	end
+  if (data_eot & m_axi_wlast) begin
+    wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
+  end else begin
+    wstrb <= {(DMA_DATA_WIDTH/8){1'b1}};
+  end
 end
 
 assign m_axi_wstrb = wstrb;
  
 dmac_response_handler #(
-	.ID_WIDTH(ID_WIDTH)
+  .ID_WIDTH(ID_WIDTH)
 ) i_response_handler (
-	.clk(m_axi_aclk),
-	.resetn(m_axi_aresetn),
-	.bvalid(m_axi_bvalid),
-	.bready(m_axi_bready),
-	.bresp(m_axi_bresp),
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+  .bvalid(m_axi_bvalid),
+  .bready(m_axi_bready),
+  .bresp(m_axi_bresp),
 
-	.enable(data_enabled),
-	.enabled(enabled),
+  .enable(data_enabled),
+  .enabled(enabled),
 
-	.id(response_id),
-	.request_id(data_id),
-	.sync_id(sync_id),
+  .id(response_id),
+  .request_id(data_id),
+  .sync_id(sync_id),
 
-	.eot(response_eot),
+  .eot(response_eot),
 
-	.resp_valid(response_valid),
-	.resp_ready(response_ready),
-	.resp_resp(response_resp),
-	.resp_eot(response_resp_eot)
+  .resp_valid(response_valid),
+  .resp_ready(response_ready),
+  .resp_resp(response_resp),
+  .resp_eot(response_resp_eot)
 );
 
 endmodule
diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v
index 48c5dea55..3b3da3397 100644
--- a/library/axi_dmac/dest_axi_stream.v
+++ b/library/axi_dmac/dest_axi_stream.v
@@ -37,39 +37,39 @@
 // ***************************************************************************
 
 module dmac_dest_axi_stream (
-	input s_axis_aclk,
-	input s_axis_aresetn,
+  input s_axis_aclk,
+  input s_axis_aresetn,
 
-	input enable,
-	output enabled,
-	input sync_id,
-	output sync_id_ret,
+  input enable,
+  output enabled,
+  input sync_id,
+  output sync_id_ret,
         output xfer_req,
 
-	input [ID_WIDTH-1:0] request_id,
-	output [ID_WIDTH-1:0] response_id,
-	output [ID_WIDTH-1:0] data_id,
-	input data_eot,
-	input response_eot,
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  output [ID_WIDTH-1:0] data_id,
+  input data_eot,
+  input response_eot,
 
-	input m_axis_ready,
-	output m_axis_valid,
-	output [S_AXIS_DATA_WIDTH-1:0] m_axis_data,
+  input m_axis_ready,
+  output m_axis_valid,
+  output [S_AXIS_DATA_WIDTH-1:0] m_axis_data,
         output m_axis_last,
 
-	output fifo_ready,
-	input fifo_valid,
-	input [S_AXIS_DATA_WIDTH-1:0] fifo_data,
+  output fifo_ready,
+  input fifo_valid,
+  input [S_AXIS_DATA_WIDTH-1:0] fifo_data,
 
-	input req_valid,
-	output req_ready,
-	input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
         input req_xlast,
 
-	output response_valid,
-	input response_ready,
-	output response_resp_eot,
-	output [1:0] response_resp
+  output response_valid,
+  input response_ready,
+  output response_resp_eot,
+  output [1:0] response_resp
 );
 
 parameter ID_WIDTH = 3;
@@ -97,56 +97,56 @@ end
 assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0;
 
 dmac_data_mover # (
-	.ID_WIDTH(ID_WIDTH),
-	.DATA_WIDTH(S_AXIS_DATA_WIDTH),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
-	.DISABLE_WAIT_FOR_ID(0),
-	.LAST(1)
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(S_AXIS_DATA_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+  .DISABLE_WAIT_FOR_ID(0),
+  .LAST(1)
 ) i_data_mover (
-	.clk(s_axis_aclk),
-	.resetn(s_axis_aresetn),
+  .clk(s_axis_aclk),
+  .resetn(s_axis_aresetn),
 
-	.enable(enable),
-	.enabled(data_enabled),
-	.sync_id(sync_id),
+  .enable(enable),
+  .enabled(data_enabled),
+  .sync_id(sync_id),
         .xfer_req(xfer_req),
 
-	.request_id(request_id),
-	.response_id(data_id),
-	.eot(data_eot),
+  .request_id(request_id),
+  .response_id(data_id),
+  .eot(data_eot),
 
-	.req_valid(req_valid),
-	.req_ready(req_ready),
-	.req_last_burst_length(req_last_burst_length),
+  .req_valid(req_valid),
+  .req_ready(req_ready),
+  .req_last_burst_length(req_last_burst_length),
 
-	.m_axi_ready(m_axis_ready),
-	.m_axi_valid(m_axis_valid),
-	.m_axi_data(m_axis_data),
+  .m_axi_ready(m_axis_ready),
+  .m_axi_valid(m_axis_valid),
+  .m_axi_data(m_axis_data),
         .m_axi_last(m_axis_last_s),
-	.s_axi_ready(_fifo_ready),
-	.s_axi_valid(fifo_valid),
-	.s_axi_data(fifo_data)
+  .s_axi_ready(_fifo_ready),
+  .s_axi_valid(fifo_valid),
+  .s_axi_data(fifo_data)
 );
 
 dmac_response_generator # (
-	.ID_WIDTH(ID_WIDTH)
+  .ID_WIDTH(ID_WIDTH)
 ) i_response_generator (
-	.clk(s_axis_aclk),
-	.resetn(s_axis_aresetn),
+  .clk(s_axis_aclk),
+  .resetn(s_axis_aresetn),
 
-	.enable(data_enabled),
-	.enabled(enabled),
-	.sync_id(sync_id),
+  .enable(data_enabled),
+  .enabled(enabled),
+  .sync_id(sync_id),
 
-	.request_id(data_id),
-	.response_id(response_id),
+  .request_id(data_id),
+  .response_id(response_id),
 
-	.eot(response_eot),
+  .eot(response_eot),
 
-	.resp_valid(response_valid),
-	.resp_ready(response_ready),
-	.resp_eot(response_resp_eot),
-	.resp_resp(response_resp)
+  .resp_valid(response_valid),
+  .resp_ready(response_ready),
+  .resp_eot(response_resp_eot),
+  .resp_resp(response_resp)
 );
 
 assign fifo_ready = _fifo_ready | ~enabled;
diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v
index 3e5c1d0eb..fccac5d7a 100644
--- a/library/axi_dmac/dest_fifo_inf.v
+++ b/library/axi_dmac/dest_fifo_inf.v
@@ -37,39 +37,39 @@
 // ***************************************************************************
 
 module dmac_dest_fifo_inf (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input enable,
-	output enabled,
-	input sync_id,
-	output sync_id_ret,
+  input enable,
+  output enabled,
+  input sync_id,
+  output sync_id_ret,
 
-	input [ID_WIDTH-1:0] request_id,
-	output [ID_WIDTH-1:0] response_id,
-	output [ID_WIDTH-1:0] data_id,
-	input data_eot,
-	input response_eot,
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  output [ID_WIDTH-1:0] data_id,
+  input data_eot,
+  input response_eot,
 
-	input en,
-	output [DATA_WIDTH-1:0] dout,
-	output valid,
-	output underflow,
+  input en,
+  output [DATA_WIDTH-1:0] dout,
+  output valid,
+  output underflow,
 
         output xfer_req,
 
-	output fifo_ready,
-	input fifo_valid,
-	input [DATA_WIDTH-1:0] fifo_data,
+  output fifo_ready,
+  input fifo_valid,
+  input [DATA_WIDTH-1:0] fifo_data,
 
-	input req_valid,
-	output req_ready,
-	input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
 
-	output response_valid,
-	input response_ready,
-	output response_resp_eot,
-	output [1:0] response_resp
+  output response_valid,
+  input response_ready,
+  output response_resp_eot,
+  output [1:0] response_resp
 );
 
 parameter ID_WIDTH = 3;
@@ -88,11 +88,11 @@ wire data_valid;
 
 always @(posedge clk)
 begin
-	if (resetn == 1'b0) begin
-		en_d1 <= 1'b0;
-	end else begin
-		en_d1 <= en;
-	end
+  if (resetn == 1'b0) begin
+    en_d1 <= 1'b0;
+  end else begin
+    en_d1 <= en;
+  end
 end
 
 assign underflow = en_d1 & (~data_valid | ~enable);
@@ -100,55 +100,55 @@ assign data_ready = en_d1 & (data_valid | ~enable);
 assign valid = en_d1 & data_valid & enable;
 
 dmac_data_mover # (
-	.ID_WIDTH(ID_WIDTH),
-	.DATA_WIDTH(DATA_WIDTH),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
-	.DISABLE_WAIT_FOR_ID(0)
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DATA_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+  .DISABLE_WAIT_FOR_ID(0)
 ) i_data_mover (
-	.clk(clk),
-	.resetn(resetn),
+  .clk(clk),
+  .resetn(resetn),
 
-	.enable(enable),
-	.enabled(data_enabled),
-	.sync_id(sync_id),
+  .enable(enable),
+  .enabled(data_enabled),
+  .sync_id(sync_id),
         .xfer_req(xfer_req),
 
-	.request_id(request_id),
-	.response_id(data_id),
-	.eot(data_eot),
-	
-	.req_valid(req_valid),
-	.req_ready(req_ready),
-	.req_last_burst_length(req_last_burst_length),
+  .request_id(request_id),
+  .response_id(data_id),
+  .eot(data_eot),
+  
+  .req_valid(req_valid),
+  .req_ready(req_ready),
+  .req_last_burst_length(req_last_burst_length),
 
-	.s_axi_ready(_fifo_ready),
-	.s_axi_valid(fifo_valid),
-	.s_axi_data(fifo_data),
-	.m_axi_ready(data_ready),
-	.m_axi_valid(data_valid),
-	.m_axi_data(dout),
-	.m_axi_last()
+  .s_axi_ready(_fifo_ready),
+  .s_axi_valid(fifo_valid),
+  .s_axi_data(fifo_data),
+  .m_axi_ready(data_ready),
+  .m_axi_valid(data_valid),
+  .m_axi_data(dout),
+  .m_axi_last()
 );
 
 dmac_response_generator # (
-	.ID_WIDTH(ID_WIDTH)
+  .ID_WIDTH(ID_WIDTH)
 ) i_response_generator (
-	.clk(clk),
-	.resetn(resetn),
+  .clk(clk),
+  .resetn(resetn),
 
-	.enable(data_enabled),
-	.enabled(enabled),
-	.sync_id(sync_id),
+  .enable(data_enabled),
+  .enabled(enabled),
+  .sync_id(sync_id),
 
-	.request_id(data_id),
-	.response_id(response_id),
+  .request_id(data_id),
+  .response_id(response_id),
 
-	.eot(response_eot),
+  .eot(response_eot),
 
-	.resp_valid(response_valid),
-	.resp_ready(response_ready),
-	.resp_eot(response_resp_eot),
-	.resp_resp(response_resp)
+  .resp_valid(response_valid),
+  .resp_ready(response_ready),
+  .resp_eot(response_resp_eot),
+  .resp_resp(response_resp)
 );
 
 endmodule
diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v
index 2e622403a..706d2cedc 100644
--- a/library/axi_dmac/request_arb.v
+++ b/library/axi_dmac/request_arb.v
@@ -37,107 +37,107 @@
 // ***************************************************************************
 
 module dmac_request_arb (
-	input req_aclk,
-	input req_aresetn,
+  input req_aclk,
+  input req_aresetn,
 
-	input req_valid,
-	output req_ready,
-	input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
-	input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
-	input [DMA_LENGTH_WIDTH-1:0] req_length,
+  input req_valid,
+  output req_ready,
+  input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
+  input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
+  input [DMA_LENGTH_WIDTH-1:0] req_length,
         input req_xlast,
-	input req_sync_transfer_start,
+  input req_sync_transfer_start,
 
-	output reg eot,
+  output reg eot,
 
-	input                               enable,
-	input                               pause,
+  input                               enable,
+  input                               pause,
 
-	// Master AXI interface
-	input                               m_dest_axi_aclk,
-	input                               m_dest_axi_aresetn,
-	input                               m_src_axi_aclk,
-	input                               m_src_axi_aresetn,
+  // Master AXI interface
+  input                               m_dest_axi_aclk,
+  input                               m_dest_axi_aresetn,
+  input                               m_src_axi_aclk,
+  input                               m_src_axi_aresetn,
 
-	// Write address
-	output [31:0]                       m_axi_awaddr,
-	output [ 7:0]                       m_axi_awlen,
-	output [ 2:0]                       m_axi_awsize,
-	output [ 1:0]                       m_axi_awburst,
-	output [ 2:0]                       m_axi_awprot,
-	output [ 3:0]                       m_axi_awcache,
-	output                              m_axi_awvalid,
-	input                               m_axi_awready,
+  // Write address
+  output [31:0]                       m_axi_awaddr,
+  output [ 7:0]                       m_axi_awlen,
+  output [ 2:0]                       m_axi_awsize,
+  output [ 1:0]                       m_axi_awburst,
+  output [ 2:0]                       m_axi_awprot,
+  output [ 3:0]                       m_axi_awcache,
+  output                              m_axi_awvalid,
+  input                               m_axi_awready,
 
-	// Write data
-	output [DMA_DATA_WIDTH_DEST-1:0]     m_axi_wdata,
-	output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb,
-	input                               m_axi_wready,
-	output                              m_axi_wvalid,
-	output                              m_axi_wlast,
+  // Write data
+  output [DMA_DATA_WIDTH_DEST-1:0]     m_axi_wdata,
+  output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb,
+  input                               m_axi_wready,
+  output                              m_axi_wvalid,
+  output                              m_axi_wlast,
 
-	// Write response
-	input                               m_axi_bvalid,
-	input  [ 1:0]                       m_axi_bresp,
-	output                              m_axi_bready,
+  // Write response
+  input                               m_axi_bvalid,
+  input  [ 1:0]                       m_axi_bresp,
+  output                              m_axi_bready,
 
-	// Read address
-	input                               m_axi_arready,
-	output                              m_axi_arvalid,
-	output [31:0]                       m_axi_araddr,
-	output [ 7:0]                       m_axi_arlen,
-	output [ 2:0]                       m_axi_arsize,
-	output [ 1:0]                       m_axi_arburst,
-	output [ 2:0]                       m_axi_arprot,
-	output [ 3:0]                       m_axi_arcache,
+  // Read address
+  input                               m_axi_arready,
+  output                              m_axi_arvalid,
+  output [31:0]                       m_axi_araddr,
+  output [ 7:0]                       m_axi_arlen,
+  output [ 2:0]                       m_axi_arsize,
+  output [ 1:0]                       m_axi_arburst,
+  output [ 2:0]                       m_axi_arprot,
+  output [ 3:0]                       m_axi_arcache,
 
-	// Read data and response
-	input  [DMA_DATA_WIDTH_SRC-1:0]   m_axi_rdata,
-	output                              m_axi_rready,
-	input                               m_axi_rvalid,
-	input  [ 1:0]                       m_axi_rresp,
+  // Read data and response
+  input  [DMA_DATA_WIDTH_SRC-1:0]   m_axi_rdata,
+  output                              m_axi_rready,
+  input                               m_axi_rvalid,
+  input  [ 1:0]                       m_axi_rresp,
 
-	// Slave streaming AXI interface
-	input                               s_axis_aclk,
-	output                              s_axis_ready,
-	input                               s_axis_valid,
-	input  [DMA_DATA_WIDTH_SRC-1:0]   s_axis_data,
-	input  [0:0]                        s_axis_user,
-	output                              s_axis_xfer_req,
+  // Slave streaming AXI interface
+  input                               s_axis_aclk,
+  output                              s_axis_ready,
+  input                               s_axis_valid,
+  input  [DMA_DATA_WIDTH_SRC-1:0]   s_axis_data,
+  input  [0:0]                        s_axis_user,
+  output                              s_axis_xfer_req,
 
-	// Master streaming AXI interface
-	input                               m_axis_aclk,
-	input                               m_axis_ready,
-	output                              m_axis_valid,
-	output [DMA_DATA_WIDTH_DEST-1:0]  m_axis_data,
+  // Master streaming AXI interface
+  input                               m_axis_aclk,
+  input                               m_axis_ready,
+  output                              m_axis_valid,
+  output [DMA_DATA_WIDTH_DEST-1:0]  m_axis_data,
         output                              m_axis_last,
         output                              m_axis_xfer_req,
 
-	// Input FIFO interface
-	input                               fifo_wr_clk,
-	input                               fifo_wr_en,
-	input  [DMA_DATA_WIDTH_SRC-1:0]   fifo_wr_din,
-	output                              fifo_wr_overflow,
-	input                               fifo_wr_sync,
-	output                              fifo_wr_xfer_req,
+  // Input FIFO interface
+  input                               fifo_wr_clk,
+  input                               fifo_wr_en,
+  input  [DMA_DATA_WIDTH_SRC-1:0]   fifo_wr_din,
+  output                              fifo_wr_overflow,
+  input                               fifo_wr_sync,
+  output                              fifo_wr_xfer_req,
 
-	// Input FIFO interface
-	input                               fifo_rd_clk,
-	input                               fifo_rd_en,
-	output                              fifo_rd_valid,
-	output [DMA_DATA_WIDTH_DEST-1:0]  fifo_rd_dout,
-	output                              fifo_rd_underflow,
+  // Input FIFO interface
+  input                               fifo_rd_clk,
+  input                               fifo_rd_en,
+  output                              fifo_rd_valid,
+  output [DMA_DATA_WIDTH_DEST-1:0]  fifo_rd_dout,
+  output                              fifo_rd_underflow,
         output                              fifo_rd_xfer_req,
 
-	output [ID_WIDTH-1:0]				dbg_dest_request_id,
-	output [ID_WIDTH-1:0]				dbg_dest_address_id,
-	output [ID_WIDTH-1:0]				dbg_dest_data_id,
-	output [ID_WIDTH-1:0]				dbg_dest_response_id,
-	output [ID_WIDTH-1:0]				dbg_src_request_id,
-	output [ID_WIDTH-1:0]				dbg_src_address_id,
-	output [ID_WIDTH-1:0]				dbg_src_data_id,
-	output [ID_WIDTH-1:0]				dbg_src_response_id,
-	output [7:0]                        dbg_status
+  output [ID_WIDTH-1:0]        dbg_dest_request_id,
+  output [ID_WIDTH-1:0]        dbg_dest_address_id,
+  output [ID_WIDTH-1:0]        dbg_dest_data_id,
+  output [ID_WIDTH-1:0]        dbg_dest_response_id,
+  output [ID_WIDTH-1:0]        dbg_src_request_id,
+  output [ID_WIDTH-1:0]        dbg_src_address_id,
+  output [ID_WIDTH-1:0]        dbg_src_data_id,
+  output [ID_WIDTH-1:0]        dbg_src_response_id,
+  output [7:0]                        dbg_status
 );
 
 parameter DMA_DATA_WIDTH_SRC = 64;
@@ -170,7 +170,7 @@ localparam DMA_ADDRESS_WIDTH_DEST = 32 - BYTES_PER_BEAT_WIDTH_DEST;
 localparam DMA_ADDRESS_WIDTH_SRC = 32 - BYTES_PER_BEAT_WIDTH_SRC;
 
 localparam DMA_DATA_WIDTH = DMA_DATA_WIDTH_SRC < DMA_DATA_WIDTH_DEST ?
-	DMA_DATA_WIDTH_DEST : DMA_DATA_WIDTH_SRC;
+  DMA_DATA_WIDTH_DEST : DMA_DATA_WIDTH_SRC;
 
 
 
@@ -294,49 +294,49 @@ reg do_enable;
 // Enable src and dest if we are in sync
 always @(posedge req_aclk)
 begin
-	if (req_aresetn == 1'b0) begin
-		do_enable <= 1'b0;
-	end else begin
-		if (enable) begin
-			// First make sure we are fully disabled
-			if (~sync_id_ret_dest && ~sync_id_ret_src &&
-				response_id == request_id && ~enabled_dest && ~enabled_src &&
-				req_dest_empty && req_src_empty && fifo_empty)
-				do_enable <= 1'b1;
-		end else begin
-			do_enable <= 1'b0;
-		end
-	end
+  if (req_aresetn == 1'b0) begin
+    do_enable <= 1'b0;
+  end else begin
+    if (enable) begin
+      // First make sure we are fully disabled
+      if (~sync_id_ret_dest && ~sync_id_ret_src &&
+        response_id == request_id && ~enabled_dest && ~enabled_src &&
+        req_dest_empty && req_src_empty && fifo_empty)
+        do_enable <= 1'b1;
+    end else begin
+      do_enable <= 1'b0;
+    end
+  end
 end
 
 // Flag enabled once both src and dest are enabled
 always @(posedge req_aclk)
 begin
-	if (req_aresetn == 1'b0) begin
-		enabled <= 1'b0;
-	end else begin
-		if (do_enable == 1'b0)
-			enabled <= 1'b0;
-		else if (enabled_dest && enabled_src)
-			enabled <= 1'b1;
-	end
+  if (req_aresetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+    if (do_enable == 1'b0)
+      enabled <= 1'b0;
+    else if (enabled_dest && enabled_src)
+      enabled <= 1'b1;
+  end
 end
 
 assign dbg_status = {do_enable, enabled, enabled_dest, enabled_src, fifo_empty,
-	sync_id, sync_id_ret_dest, sync_id_ret_src};
+  sync_id, sync_id_ret_dest, sync_id_ret_src};
 
 always @(posedge req_aclk)
 begin
-	eot_mem[request_id] <= request_eot;
+  eot_mem[request_id] <= request_eot;
 end
 
 always @(posedge req_aclk)
 begin
-	if (req_aresetn == 1'b0) begin
-		eot <= 1'b0;
-	end else begin
-		eot <= response_dest_valid & response_dest_ready & response_dest_resp_eot;
-	end
+  if (req_aresetn == 1'b0) begin
+    eot <= 1'b0;
+  end else begin
+    eot <= response_dest_valid & response_dest_ready & response_dest_resp_eot;
+  end
 end
 
 generate if (ASYNC_CLK_REQ_SRC) begin
@@ -353,10 +353,10 @@ reg [2:0] src_reset_shift = 3'b111;
 assign src_resetn = ~src_reset_shift[2];
 
 always @(negedge src_async_resetn_source or posedge src_clk) begin
-	if (src_async_resetn_source == 1'b0)
-		src_reset_shift <= 3'b111;
-	else
-		src_reset_shift <= {src_reset_shift[1:0], 1'b0};
+  if (src_async_resetn_source == 1'b0)
+    src_reset_shift <= 3'b111;
+  else
+    src_reset_shift <= {src_reset_shift[1:0], 1'b0};
 end
 
 end else begin
@@ -376,10 +376,10 @@ reg [2:0] dest_reset_shift = 3'b111;
 assign dest_resetn = ~dest_reset_shift[2];
 
 always @(negedge dest_async_resetn_source or posedge dest_clk) begin
-	if (dest_async_resetn_source == 1'b0)
-		dest_reset_shift <= 3'b111;
-	else
-		dest_reset_shift <= {dest_reset_shift[1:0], 1'b0};
+  if (dest_async_resetn_source == 1'b0)
+    dest_reset_shift <= 3'b111;
+  else
+    dest_reset_shift <= {dest_reset_shift[1:0], 1'b0};
 end
 
 end else begin
@@ -400,62 +400,62 @@ assign dbg_dest_address_id = dest_address_id;
 assign dbg_dest_data_id = dest_data_id;
 
 dmac_dest_mm_axi #(
-	.ID_WIDTH(ID_WIDTH),
-	.DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
-	.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST)
+  .ID_WIDTH(ID_WIDTH),
+  .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
+  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST)
 ) i_dest_dma_mm (
-	.m_axi_aclk(m_dest_axi_aclk),
-	.m_axi_aresetn(dest_resetn),
+  .m_axi_aclk(m_dest_axi_aclk),
+  .m_axi_aresetn(dest_resetn),
 
-	.enable(dest_enable),
-	.enabled(dest_enabled),
-	.pause(dest_pause),
+  .enable(dest_enable),
+  .enabled(dest_enabled),
+  .pause(dest_pause),
 
-	.req_valid(dest_req_valid),
-	.req_ready(dest_req_ready),
-	.req_address(dest_req_address),
-	.req_last_burst_length(dest_req_last_burst_length),
-	.req_last_beat_bytes(dest_req_last_beat_bytes),
+  .req_valid(dest_req_valid),
+  .req_ready(dest_req_ready),
+  .req_address(dest_req_address),
+  .req_last_burst_length(dest_req_last_burst_length),
+  .req_last_beat_bytes(dest_req_last_beat_bytes),
 
-	.response_valid(dest_response_valid),
-	.response_ready(dest_response_ready),
-	.response_resp(dest_response_resp),
-	.response_resp_eot(dest_response_resp_eot),
+  .response_valid(dest_response_valid),
+  .response_ready(dest_response_ready),
+  .response_resp(dest_response_resp),
+  .response_resp_eot(dest_response_resp_eot),
 
-	.request_id(dest_request_id),
-	.response_id(dest_response_id),
-	.sync_id(dest_sync_id),
-	.sync_id_ret(dest_sync_id_ret),
+  .request_id(dest_request_id),
+  .response_id(dest_response_id),
+  .sync_id(dest_sync_id),
+  .sync_id_ret(dest_sync_id_ret),
 
-	.data_id(dest_data_id),
-	.address_id(dest_address_id),
+  .data_id(dest_data_id),
+  .address_id(dest_address_id),
 
-	.address_eot(dest_address_eot),
-	.data_eot(dest_data_eot),
-	.response_eot(dest_response_eot),
+  .address_eot(dest_address_eot),
+  .data_eot(dest_data_eot),
+  .response_eot(dest_response_eot),
 
-	.fifo_valid(dest_valid),
-	.fifo_ready(dest_ready),
-	.fifo_data(dest_data),
+  .fifo_valid(dest_valid),
+  .fifo_ready(dest_ready),
+  .fifo_data(dest_data),
 
-	.m_axi_awready(m_axi_awready),
-	.m_axi_awvalid(m_axi_awvalid),
-	.m_axi_awaddr(m_axi_awaddr),
-	.m_axi_awlen(m_axi_awlen),
-	.m_axi_awsize(m_axi_awsize),
-	.m_axi_awburst(m_axi_awburst),
-	.m_axi_awprot(m_axi_awprot),
-	.m_axi_awcache(m_axi_awcache),
-	.m_axi_wready(m_axi_wready),
-	.m_axi_wvalid(m_axi_wvalid),
-	.m_axi_wdata(m_axi_wdata),
-	.m_axi_wstrb(m_axi_wstrb),
-	.m_axi_wlast(m_axi_wlast),
+  .m_axi_awready(m_axi_awready),
+  .m_axi_awvalid(m_axi_awvalid),
+  .m_axi_awaddr(m_axi_awaddr),
+  .m_axi_awlen(m_axi_awlen),
+  .m_axi_awsize(m_axi_awsize),
+  .m_axi_awburst(m_axi_awburst),
+  .m_axi_awprot(m_axi_awprot),
+  .m_axi_awcache(m_axi_awcache),
+  .m_axi_wready(m_axi_wready),
+  .m_axi_wvalid(m_axi_wvalid),
+  .m_axi_wdata(m_axi_wdata),
+  .m_axi_wstrb(m_axi_wstrb),
+  .m_axi_wlast(m_axi_wlast),
 
-	.m_axi_bvalid(m_axi_bvalid),
-	.m_axi_bresp(m_axi_bresp),
-	.m_axi_bready(m_axi_bready)
+  .m_axi_bvalid(m_axi_bvalid),
+  .m_axi_bresp(m_axi_bresp),
+  .m_axi_bready(m_axi_bready)
 );
 
 end else begin
@@ -490,43 +490,43 @@ assign dbg_dest_address_id = 'h00;
 assign dbg_dest_data_id = data_id;
 
 dmac_dest_axi_stream #(
-	.ID_WIDTH(ID_WIDTH),
-	.S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
+  .ID_WIDTH(ID_WIDTH),
+  .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
 ) i_dest_dma_stream (
-	.s_axis_aclk(m_axis_aclk),
-	.s_axis_aresetn(dest_resetn),
+  .s_axis_aclk(m_axis_aclk),
+  .s_axis_aresetn(dest_resetn),
 
-	.enable(dest_enable),
-	.enabled(dest_enabled),
+  .enable(dest_enable),
+  .enabled(dest_enabled),
 
-	.req_valid(dest_req_valid),
-	.req_ready(dest_req_ready),
-	.req_last_burst_length(dest_req_last_burst_length),
+  .req_valid(dest_req_valid),
+  .req_ready(dest_req_ready),
+  .req_last_burst_length(dest_req_last_burst_length),
         .req_xlast(dest_req_xlast),
 
-	.response_valid(dest_response_valid),
-	.response_ready(dest_response_ready),
-	.response_resp(dest_response_resp),
-	.response_resp_eot(dest_response_resp_eot),
+  .response_valid(dest_response_valid),
+  .response_ready(dest_response_ready),
+  .response_resp(dest_response_resp),
+  .response_resp_eot(dest_response_resp_eot),
 
-	.request_id(dest_request_id),
-	.response_id(dest_response_id),
-	.data_id(data_id),
-	.sync_id(dest_sync_id),
-	.sync_id_ret(dest_sync_id_ret),
+  .request_id(dest_request_id),
+  .response_id(dest_response_id),
+  .data_id(data_id),
+  .sync_id(dest_sync_id),
+  .sync_id_ret(dest_sync_id_ret),
         .xfer_req(m_axis_xfer_req),
 
-	.data_eot(data_eot),
-	.response_eot(response_eot),
+  .data_eot(data_eot),
+  .response_eot(response_eot),
 
-	.fifo_valid(dest_valid),
-	.fifo_ready(dest_ready),
-	.fifo_data(dest_data),
+  .fifo_valid(dest_valid),
+  .fifo_ready(dest_ready),
+  .fifo_data(dest_data),
 
-	.m_axis_valid(m_axis_valid),
-	.m_axis_ready(m_axis_ready),
-	.m_axis_data(m_axis_data),
+  .m_axis_valid(m_axis_valid),
+  .m_axis_ready(m_axis_ready),
+  .m_axis_data(m_axis_data),
         .m_axis_last(m_axis_last)
 );
 
@@ -552,42 +552,42 @@ assign dbg_dest_address_id = 'h00;
 assign dbg_dest_data_id = data_id;
 
 dmac_dest_fifo_inf #(
-	.ID_WIDTH(ID_WIDTH),
-	.DATA_WIDTH(DMA_DATA_WIDTH_DEST),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
 ) i_dest_dma_fifo (
-	.clk(fifo_rd_clk),
-	.resetn(dest_resetn),
+  .clk(fifo_rd_clk),
+  .resetn(dest_resetn),
 
-	.enable(dest_enable),
-	.enabled(dest_enabled),
+  .enable(dest_enable),
+  .enabled(dest_enabled),
 
-	.req_valid(dest_req_valid),
-	.req_ready(dest_req_ready),
-	.req_last_burst_length(dest_req_last_burst_length),
+  .req_valid(dest_req_valid),
+  .req_ready(dest_req_ready),
+  .req_last_burst_length(dest_req_last_burst_length),
 
-	.response_valid(dest_response_valid),
-	.response_ready(dest_response_ready),
-	.response_resp(dest_response_resp),
-	.response_resp_eot(dest_response_resp_eot),
+  .response_valid(dest_response_valid),
+  .response_ready(dest_response_ready),
+  .response_resp(dest_response_resp),
+  .response_resp_eot(dest_response_resp_eot),
 
-	.request_id(dest_request_id),
-	.response_id(dest_response_id),
-	.data_id(data_id),
-	.sync_id(dest_sync_id),
-	.sync_id_ret(dest_sync_id_ret),
+  .request_id(dest_request_id),
+  .response_id(dest_response_id),
+  .data_id(data_id),
+  .sync_id(dest_sync_id),
+  .sync_id_ret(dest_sync_id_ret),
 
-	.data_eot(data_eot),
-	.response_eot(response_eot),
+  .data_eot(data_eot),
+  .response_eot(response_eot),
 
-	.fifo_valid(dest_valid),
-	.fifo_ready(dest_ready),
-	.fifo_data(dest_data),
+  .fifo_valid(dest_valid),
+  .fifo_ready(dest_ready),
+  .fifo_data(dest_data),
 
-	.en(fifo_rd_en),
-	.valid(fifo_rd_valid),
-	.dout(fifo_rd_dout),
-	.underflow(fifo_rd_underflow),
+  .en(fifo_rd_en),
+  .valid(fifo_rd_valid),
+  .dout(fifo_rd_dout),
+  .underflow(fifo_rd_underflow),
         .xfer_req(fifo_rd_xfer_req)
 );
 
@@ -613,54 +613,54 @@ assign dbg_src_address_id = src_address_id;
 assign dbg_src_data_id = src_data_id;
 
 dmac_src_mm_axi #(
-	.ID_WIDTH(ID_WIDTH),
-	.DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
-	.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC)
+  .ID_WIDTH(ID_WIDTH),
+  .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
+  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC)
 ) i_src_dma_mm (
-	.m_axi_aclk(m_src_axi_aclk),
-	.m_axi_aresetn(src_resetn),
+  .m_axi_aclk(m_src_axi_aclk),
+  .m_axi_aresetn(src_resetn),
 
-	.pause(src_pause),
-	.enable(src_enable),
-	.enabled(src_enabled),
-	.sync_id(src_sync_id),
-	.sync_id_ret(src_sync_id_ret),
+  .pause(src_pause),
+  .enable(src_enable),
+  .enabled(src_enabled),
+  .sync_id(src_sync_id),
+  .sync_id_ret(src_sync_id_ret),
 
-	.req_valid(src_req_valid),
-	.req_ready(src_req_ready),
-	.req_address(src_req_address),
-	.req_last_burst_length(src_req_last_burst_length),
+  .req_valid(src_req_valid),
+  .req_ready(src_req_ready),
+  .req_address(src_req_address),
+  .req_last_burst_length(src_req_last_burst_length),
 
-	.response_valid(src_response_valid),
-	.response_ready(src_response_ready),
-	.response_resp(src_response_resp),
+  .response_valid(src_response_valid),
+  .response_ready(src_response_ready),
+  .response_resp(src_response_resp),
 
-	.request_id(src_request_id),
-	.response_id(src_response_id),
-	.address_id(src_address_id),
-	.data_id(src_data_id),
+  .request_id(src_request_id),
+  .response_id(src_response_id),
+  .address_id(src_address_id),
+  .data_id(src_data_id),
 
-	.address_eot(src_address_eot),
-	.data_eot(src_data_eot),
+  .address_eot(src_address_eot),
+  .data_eot(src_data_eot),
 
-	.fifo_valid(src_valid),
-	.fifo_ready(src_ready),
-	.fifo_data(src_data),
+  .fifo_valid(src_valid),
+  .fifo_ready(src_ready),
+  .fifo_data(src_data),
 
-	.m_axi_arready(m_axi_arready),
-	.m_axi_arvalid(m_axi_arvalid),
-	.m_axi_araddr(m_axi_araddr),
-	.m_axi_arlen(m_axi_arlen),
-	.m_axi_arsize(m_axi_arsize),
-	.m_axi_arburst(m_axi_arburst),
-	.m_axi_arprot(m_axi_arprot),
-	.m_axi_arcache(m_axi_arcache),
+  .m_axi_arready(m_axi_arready),
+  .m_axi_arvalid(m_axi_arvalid),
+  .m_axi_araddr(m_axi_araddr),
+  .m_axi_arlen(m_axi_arlen),
+  .m_axi_arsize(m_axi_arsize),
+  .m_axi_arburst(m_axi_arburst),
+  .m_axi_arprot(m_axi_arprot),
+  .m_axi_arcache(m_axi_arcache),
 
-	.m_axi_rready(m_axi_rready),
-	.m_axi_rvalid(m_axi_rvalid),
-	.m_axi_rdata(m_axi_rdata),
-	.m_axi_rresp(m_axi_rresp)
+  .m_axi_rready(m_axi_rready),
+  .m_axi_rvalid(m_axi_rvalid),
+  .m_axi_rdata(m_axi_rdata),
+  .m_axi_rresp(m_axi_rresp)
 );
 
 end else begin
@@ -690,37 +690,37 @@ assign src_response_valid = 1'b0;
 assign src_response_resp = 2'b0;
 
 dmac_src_axi_stream #(
-	.ID_WIDTH(ID_WIDTH),
-	.S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
+  .ID_WIDTH(ID_WIDTH),
+  .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
 ) i_src_dma_stream (
-	.s_axis_aclk(s_axis_aclk),
-	.s_axis_aresetn(src_resetn),
+  .s_axis_aclk(s_axis_aclk),
+  .s_axis_aresetn(src_resetn),
 
-	.enable(src_enable),
-	.enabled(src_enabled),
-	.sync_id(src_sync_id),
-	.sync_id_ret(src_sync_id_ret),
+  .enable(src_enable),
+  .enabled(src_enabled),
+  .sync_id(src_sync_id),
+  .sync_id_ret(src_sync_id_ret),
 
-	.req_valid(src_req_valid),
-	.req_ready(src_req_ready),
-	.req_last_burst_length(src_req_last_burst_length),
-	.req_sync_transfer_start(src_req_sync_transfer_start),
+  .req_valid(src_req_valid),
+  .req_ready(src_req_ready),
+  .req_last_burst_length(src_req_last_burst_length),
+  .req_sync_transfer_start(src_req_sync_transfer_start),
 
-	.request_id(src_request_id),
-	.response_id(src_response_id),
+  .request_id(src_request_id),
+  .response_id(src_response_id),
 
-	.eot(src_eot),
+  .eot(src_eot),
 
-	.fifo_valid(src_valid),
-	.fifo_ready(src_ready),
-	.fifo_data(src_data),
+  .fifo_valid(src_valid),
+  .fifo_ready(src_ready),
+  .fifo_data(src_data),
 
-	.s_axis_valid(s_axis_valid),
-	.s_axis_ready(s_axis_ready),
-	.s_axis_data(s_axis_data),
-	.s_axis_user(s_axis_user),
-	.s_axis_xfer_req(s_axis_xfer_req)
+  .s_axis_valid(s_axis_valid),
+  .s_axis_ready(s_axis_ready),
+  .s_axis_data(s_axis_data),
+  .s_axis_user(s_axis_user),
+  .s_axis_xfer_req(s_axis_xfer_req)
 );
 
 end else begin
@@ -744,37 +744,37 @@ assign src_response_valid = 1'b0;
 assign src_response_resp = 2'b0;
 
 dmac_src_fifo_inf #(
-	.ID_WIDTH(ID_WIDTH),
-	.DATA_WIDTH(DMA_DATA_WIDTH_SRC),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
 ) i_src_dma_fifo (
-	.clk(fifo_wr_clk),
-	.resetn(src_resetn),
+  .clk(fifo_wr_clk),
+  .resetn(src_resetn),
 
-	.enable(src_enable),
-	.enabled(src_enabled),
-	.sync_id(src_sync_id),
-	.sync_id_ret(src_sync_id_ret),
+  .enable(src_enable),
+  .enabled(src_enabled),
+  .sync_id(src_sync_id),
+  .sync_id_ret(src_sync_id_ret),
 
-	.req_valid(src_req_valid),
-	.req_ready(src_req_ready),
-	.req_last_burst_length(src_req_last_burst_length),
-	.req_sync_transfer_start(src_req_sync_transfer_start),
+  .req_valid(src_req_valid),
+  .req_ready(src_req_ready),
+  .req_last_burst_length(src_req_last_burst_length),
+  .req_sync_transfer_start(src_req_sync_transfer_start),
 
-	.request_id(src_request_id),
-	.response_id(src_response_id),
+  .request_id(src_request_id),
+  .response_id(src_response_id),
 
-	.eot(src_eot),
+  .eot(src_eot),
 
-	.fifo_valid(src_valid),
-	.fifo_ready(src_ready),
-	.fifo_data(src_data),
+  .fifo_valid(src_valid),
+  .fifo_ready(src_ready),
+  .fifo_data(src_data),
 
-	.en(fifo_wr_en),
-	.din(fifo_wr_din),
-	.overflow(fifo_wr_overflow),
-	.sync(fifo_wr_sync),
-	.xfer_req(fifo_wr_xfer_req)
+  .en(fifo_wr_en),
+  .din(fifo_wr_din),
+  .overflow(fifo_wr_overflow),
+  .sync(fifo_wr_sync),
+  .xfer_req(fifo_wr_xfer_req)
 );
 
 end else begin
@@ -785,97 +785,97 @@ assign fifo_wr_xfer_req = 1'b0;
 end endgenerate
 
 sync_bits #(
-	.NUM_OF_BITS(ID_WIDTH),
-	.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  .NUM_OF_BITS(ID_WIDTH),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
 ) i_sync_src_request_id (
-	.out_clk(src_clk),
-	.out_resetn(src_resetn),
-	.in(request_id),
-	.out(src_request_id)
+  .out_clk(src_clk),
+  .out_resetn(src_resetn),
+  .in(request_id),
+  .out(src_request_id)
 );
 
 sync_bits #(
-	.NUM_OF_BITS(ID_WIDTH),
-	.ASYNC_CLK(ASYNC_CLK_SRC_DEST)
+  .NUM_OF_BITS(ID_WIDTH),
+  .ASYNC_CLK(ASYNC_CLK_SRC_DEST)
 ) i_sync_dest_request_id (
-	.out_clk(dest_clk),
-	.out_resetn(dest_resetn),
-	.in(src_response_id),
-	.out(dest_request_id)
+  .out_clk(dest_clk),
+  .out_resetn(dest_resetn),
+  .in(src_response_id),
+  .out(dest_request_id)
 );
 
 sync_bits #(
-	.NUM_OF_BITS(ID_WIDTH),
-	.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+  .NUM_OF_BITS(ID_WIDTH),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
 ) i_sync_req_response_id (
-	.out_clk(req_aclk),
-	.out_resetn(req_aresetn),
-	.in(dest_response_id),
-	.out(response_id)
+  .out_clk(req_aclk),
+  .out_resetn(req_aresetn),
+  .in(dest_response_id),
+  .out(response_id)
 );
 
 axi_register_slice #(
-	.DATA_WIDTH(DMA_DATA_WIDTH_SRC),
-	.FORWARD_REGISTERED(AXI_SLICE_SRC),
-	.BACKWARD_REGISTERED(AXI_SLICE_SRC)
+  .DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .FORWARD_REGISTERED(AXI_SLICE_SRC),
+  .BACKWARD_REGISTERED(AXI_SLICE_SRC)
 ) i_src_slice (
-	.clk(src_clk),
-	.resetn(src_resetn),
-	.s_axi_valid(src_valid),
-	.s_axi_ready(src_ready),
-	.s_axi_data(src_data),
-	.m_axi_valid(src_fifo_valid),
-	.m_axi_ready(src_fifo_ready),
-	.m_axi_data(src_fifo_data)
+  .clk(src_clk),
+  .resetn(src_resetn),
+  .s_axi_valid(src_valid),
+  .s_axi_ready(src_ready),
+  .s_axi_data(src_data),
+  .m_axi_valid(src_fifo_valid),
+  .m_axi_ready(src_fifo_ready),
+  .m_axi_data(src_fifo_data)
 );
 
 util_axis_resize #(
-	.SLAVE_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
-	.MASTER_DATA_WIDTH(DMA_DATA_WIDTH)
+  .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+  .MASTER_DATA_WIDTH(DMA_DATA_WIDTH)
 ) i_src_repack (
-	.clk(src_clk),
-	.resetn(src_resetn & src_enable),
-	.s_valid(src_fifo_valid),
-	.s_ready(src_fifo_ready),
-	.s_data(src_fifo_data),
-	.m_valid(src_fifo_repacked_valid),
-	.m_ready(src_fifo_repacked_ready),
-	.m_data(src_fifo_repacked_data)
+  .clk(src_clk),
+  .resetn(src_resetn & src_enable),
+  .s_valid(src_fifo_valid),
+  .s_ready(src_fifo_ready),
+  .s_data(src_fifo_data),
+  .m_valid(src_fifo_repacked_valid),
+  .m_ready(src_fifo_repacked_ready),
+  .m_data(src_fifo_repacked_data)
 );
 
 util_axis_fifo #(
-	.DATA_WIDTH(DMA_DATA_WIDTH),
-	.ADDRESS_WIDTH($clog2(MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * FIFO_SIZE)),
-	.ASYNC_CLK(ASYNC_CLK_SRC_DEST)
+  .DATA_WIDTH(DMA_DATA_WIDTH),
+  .ADDRESS_WIDTH($clog2(MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * FIFO_SIZE)),
+  .ASYNC_CLK(ASYNC_CLK_SRC_DEST)
 ) i_fifo (
-	.s_axis_aclk(src_clk),
-	.s_axis_aresetn(src_resetn),
-	.s_axis_valid(src_fifo_repacked_valid),
-	.s_axis_ready(src_fifo_repacked_ready),
-	.s_axis_data(src_fifo_repacked_data),
-	.s_axis_empty(src_fifo_empty),
-	.s_axis_room(),
+  .s_axis_aclk(src_clk),
+  .s_axis_aresetn(src_resetn),
+  .s_axis_valid(src_fifo_repacked_valid),
+  .s_axis_ready(src_fifo_repacked_ready),
+  .s_axis_data(src_fifo_repacked_data),
+  .s_axis_empty(src_fifo_empty),
+  .s_axis_room(),
 
-	.m_axis_aclk(dest_clk),
-	.m_axis_aresetn(dest_resetn),
-	.m_axis_valid(dest_fifo_valid),
-	.m_axis_ready(dest_fifo_ready),
-	.m_axis_data(dest_fifo_data),
-	.m_axis_level()
+  .m_axis_aclk(dest_clk),
+  .m_axis_aresetn(dest_resetn),
+  .m_axis_valid(dest_fifo_valid),
+  .m_axis_ready(dest_fifo_ready),
+  .m_axis_data(dest_fifo_data),
+  .m_axis_level()
 );
 
 util_axis_resize #(
-	.SLAVE_DATA_WIDTH(DMA_DATA_WIDTH),
-	.MASTER_DATA_WIDTH(DMA_DATA_WIDTH_DEST)
+  .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH),
+  .MASTER_DATA_WIDTH(DMA_DATA_WIDTH_DEST)
 ) i_dest_repack (
-	.clk(dest_clk),
-	.resetn(dest_resetn & dest_enable),
-	.s_valid(dest_fifo_valid),
-	.s_ready(dest_fifo_ready),
-	.s_data(dest_fifo_data),
-	.m_valid(dest_fifo_repacked_valid),
-	.m_ready(dest_fifo_repacked_ready),
-	.m_data(dest_fifo_repacked_data)
+  .clk(dest_clk),
+  .resetn(dest_resetn & dest_enable),
+  .s_valid(dest_fifo_valid),
+  .s_ready(dest_fifo_ready),
+  .s_data(dest_fifo_data),
+  .m_valid(dest_fifo_repacked_valid),
+  .m_ready(dest_fifo_repacked_ready),
+  .m_data(dest_fifo_repacked_data)
 );
 
 wire _dest_valid;
@@ -883,32 +883,32 @@ wire _dest_ready;
 wire [DMA_DATA_WIDTH_DEST-1:0] _dest_data;
 
 axi_register_slice #(
-	.DATA_WIDTH(DMA_DATA_WIDTH_DEST),
-	.FORWARD_REGISTERED(AXI_SLICE_DEST)
+  .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .FORWARD_REGISTERED(AXI_SLICE_DEST)
 ) i_dest_slice2 (
-	.clk(dest_clk),
-	.resetn(dest_resetn),
-	.s_axi_valid(dest_fifo_repacked_valid),
-	.s_axi_ready(dest_fifo_repacked_ready),
-	.s_axi_data(dest_fifo_repacked_data),
-	.m_axi_valid(_dest_valid),
-	.m_axi_ready(_dest_ready),
-	.m_axi_data(_dest_data)
+  .clk(dest_clk),
+  .resetn(dest_resetn),
+  .s_axi_valid(dest_fifo_repacked_valid),
+  .s_axi_ready(dest_fifo_repacked_ready),
+  .s_axi_data(dest_fifo_repacked_data),
+  .m_axi_valid(_dest_valid),
+  .m_axi_ready(_dest_ready),
+  .m_axi_data(_dest_data)
 );
 
 axi_register_slice #(
-	.DATA_WIDTH(DMA_DATA_WIDTH_DEST),
-	.FORWARD_REGISTERED(AXI_SLICE_DEST),
-	.BACKWARD_REGISTERED(AXI_SLICE_DEST)
+  .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+  .FORWARD_REGISTERED(AXI_SLICE_DEST),
+  .BACKWARD_REGISTERED(AXI_SLICE_DEST)
 ) i_dest_slice (
-	.clk(dest_clk),
-	.resetn(dest_resetn),
-	.s_axi_valid(_dest_valid),
-	.s_axi_ready(_dest_ready),
-	.s_axi_data(_dest_data),
-	.m_axi_valid(dest_valid),
-	.m_axi_ready(dest_ready),
-	.m_axi_data(dest_data)
+  .clk(dest_clk),
+  .resetn(dest_resetn),
+  .s_axi_valid(_dest_valid),
+  .s_axi_ready(_dest_ready),
+  .s_axi_data(_dest_data),
+  .m_axi_valid(dest_valid),
+  .m_axi_ready(dest_ready),
+  .m_axi_data(dest_data)
 );
 
 
@@ -918,198 +918,198 @@ wire _req_ready;
 
 always @(posedge req_aclk)
 begin
-	if (req_aresetn == 1'b0) begin
-		_req_valid <= 1'b0;
-	end else begin
-		if (_req_valid == 1'b1 && _req_ready == 1'b1) begin
-			_req_valid <= 1'b0;
-		end else if (req_valid == 1'b1 && enabled == 1'b1) begin
-			_req_valid <= 1'b1;
-		end
-	end
+  if (req_aresetn == 1'b0) begin
+    _req_valid <= 1'b0;
+  end else begin
+    if (_req_valid == 1'b1 && _req_ready == 1'b1) begin
+      _req_valid <= 1'b0;
+    end else if (req_valid == 1'b1 && enabled == 1'b1) begin
+      _req_valid <= 1'b1;
+    end
+  end
 end
 
 assign req_ready = _req_ready & _req_valid & enable;
 
 splitter #(
-	.NUM_M(3)
+  .NUM_M(3)
 ) i_req_splitter (
-	.clk(req_aclk),
-	.resetn(req_aresetn),
-	.s_valid(_req_valid),
-	.s_ready(_req_ready),
-	.m_valid({
-		req_gen_valid,
-		req_dest_valid,
-		req_src_valid
-	}),
-	.m_ready({
-		req_gen_ready,
-		req_dest_ready,
-		req_src_ready
-	})
+  .clk(req_aclk),
+  .resetn(req_aresetn),
+  .s_valid(_req_valid),
+  .s_ready(_req_ready),
+  .m_valid({
+    req_gen_valid,
+    req_dest_valid,
+    req_src_valid
+  }),
+  .m_ready({
+    req_gen_ready,
+    req_dest_ready,
+    req_src_ready
+  })
 );
 
 util_axis_fifo #(
-	.DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1),
-	.ADDRESS_WIDTH(0),
-	.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+  .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1),
+  .ADDRESS_WIDTH(0),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
 ) i_dest_req_fifo (
-	.s_axis_aclk(req_aclk),
-	.s_axis_aresetn(req_aresetn),
-	.s_axis_valid(req_dest_valid),
-	.s_axis_ready(req_dest_ready),
-	.s_axis_empty(req_dest_empty),
-	.s_axis_data({
-		req_dest_address,
-		req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST],
-		req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0],
+  .s_axis_aclk(req_aclk),
+  .s_axis_aresetn(req_aresetn),
+  .s_axis_valid(req_dest_valid),
+  .s_axis_ready(req_dest_ready),
+  .s_axis_empty(req_dest_empty),
+  .s_axis_data({
+    req_dest_address,
+    req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST],
+    req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0],
                 req_xlast
-	}),
-	.s_axis_room(),
+  }),
+  .s_axis_room(),
 
-	.m_axis_aclk(dest_clk),
-	.m_axis_aresetn(dest_resetn),
-	.m_axis_valid(dest_req_valid),
-	.m_axis_ready(dest_req_ready),
-	.m_axis_data({
-		dest_req_address,
-		dest_req_last_burst_length,
-		dest_req_last_beat_bytes,
+  .m_axis_aclk(dest_clk),
+  .m_axis_aresetn(dest_resetn),
+  .m_axis_valid(dest_req_valid),
+  .m_axis_ready(dest_req_ready),
+  .m_axis_data({
+    dest_req_address,
+    dest_req_last_burst_length,
+    dest_req_last_beat_bytes,
                 dest_req_xlast
-	}),
-	.m_axis_level()
+  }),
+  .m_axis_level()
 );
 
 util_axis_fifo #(
-	.DATA_WIDTH(DMA_ADDRESS_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1),
-	.ADDRESS_WIDTH(0),
-	.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  .DATA_WIDTH(DMA_ADDRESS_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1),
+  .ADDRESS_WIDTH(0),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
 ) i_src_req_fifo (
-	.s_axis_aclk(req_aclk),
-	.s_axis_aresetn(req_aresetn),
-	.s_axis_valid(req_src_valid),
-	.s_axis_ready(req_src_ready),
-	.s_axis_empty(req_src_empty),
-	.s_axis_data({
-		req_src_address,
-		req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC],
-		req_sync_transfer_start
-	}),
-	.s_axis_room(),
+  .s_axis_aclk(req_aclk),
+  .s_axis_aresetn(req_aresetn),
+  .s_axis_valid(req_src_valid),
+  .s_axis_ready(req_src_ready),
+  .s_axis_empty(req_src_empty),
+  .s_axis_data({
+    req_src_address,
+    req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC],
+    req_sync_transfer_start
+  }),
+  .s_axis_room(),
 
-	.m_axis_aclk(src_clk),
-	.m_axis_aresetn(src_resetn),
-	.m_axis_valid(src_req_valid),
-	.m_axis_ready(src_req_ready),
-	.m_axis_data({
-		src_req_address,
-		src_req_last_burst_length,
-		src_req_sync_transfer_start
-	}),
-	.m_axis_level()
+  .m_axis_aclk(src_clk),
+  .m_axis_aresetn(src_resetn),
+  .m_axis_valid(src_req_valid),
+  .m_axis_ready(src_req_ready),
+  .m_axis_data({
+    src_req_address,
+    src_req_last_burst_length,
+    src_req_sync_transfer_start
+  }),
+  .m_axis_level()
 );
 
 util_axis_fifo #(
-	.DATA_WIDTH(1),
-	.ADDRESS_WIDTH(0),
-	.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+  .DATA_WIDTH(1),
+  .ADDRESS_WIDTH(0),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
 ) i_dest_response_fifo (
-	.s_axis_aclk(dest_clk),
-	.s_axis_aresetn(dest_resetn),
-	.s_axis_valid(dest_response_valid),
-	.s_axis_ready(dest_response_ready),
-	.s_axis_empty(dest_response_empty),
-	.s_axis_data(dest_response_resp_eot),
-	.s_axis_room(),
+  .s_axis_aclk(dest_clk),
+  .s_axis_aresetn(dest_resetn),
+  .s_axis_valid(dest_response_valid),
+  .s_axis_ready(dest_response_ready),
+  .s_axis_empty(dest_response_empty),
+  .s_axis_data(dest_response_resp_eot),
+  .s_axis_room(),
 
-	.m_axis_aclk(req_aclk),
-	.m_axis_aresetn(req_aresetn),
-	.m_axis_valid(response_dest_valid),
-	.m_axis_ready(response_dest_ready),
-	.m_axis_data(response_dest_resp_eot),
-	.m_axis_level()
+  .m_axis_aclk(req_aclk),
+  .m_axis_aresetn(req_aresetn),
+  .m_axis_valid(response_dest_valid),
+  .m_axis_ready(response_dest_ready),
+  .m_axis_data(response_dest_resp_eot),
+  .m_axis_level()
 );
 
 /* Unused for now
 util_axis_fifo #(
-	.DATA_WIDTH(2),
-	.ADDRESS_WIDTH(0),
-	.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  .DATA_WIDTH(2),
+  .ADDRESS_WIDTH(0),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
 ) i_src_response_fifo (
-	.s_axis_aclk(src_clk),
-	.s_axis_aresetn(src_resetn),
-	.s_axis_valid(src_response_valid),
-	.s_axis_ready(src_response_ready),
-	.s_axis_empty(src_response_empty),
-	.s_axis_data(src_response_resp),
-	.m_axis_aclk(req_aclk),
-	.m_axis_aresetn(req_aresetn),
-	.m_axis_valid(response_src_valid),
-	.m_axis_ready(response_src_ready),
-	.m_axis_data(response_src_resp)
+  .s_axis_aclk(src_clk),
+  .s_axis_aresetn(src_resetn),
+  .s_axis_valid(src_response_valid),
+  .s_axis_ready(src_response_ready),
+  .s_axis_empty(src_response_empty),
+  .s_axis_data(src_response_resp),
+  .m_axis_aclk(req_aclk),
+  .m_axis_aresetn(req_aresetn),
+  .m_axis_valid(response_src_valid),
+  .m_axis_ready(response_src_ready),
+  .m_axis_data(response_src_resp)
 );*/
 assign src_response_empty = 1'b1;
 assign src_response_ready = 1'b1;
 
 dmac_request_generator #(
-	.ID_WIDTH(ID_WIDTH),
-	.BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH)
+  .ID_WIDTH(ID_WIDTH),
+  .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH)
 ) i_req_gen (
-	.req_aclk(req_aclk),
-	.req_aresetn(req_aresetn),
+  .req_aclk(req_aclk),
+  .req_aresetn(req_aresetn),
 
-	.request_id(request_id),
-	.response_id(response_id),
+  .request_id(request_id),
+  .response_id(response_id),
 
-	.req_valid(req_gen_valid),
-	.req_ready(req_gen_ready),
-	.req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]),
+  .req_valid(req_gen_valid),
+  .req_ready(req_gen_ready),
+  .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]),
 
-	.enable(do_enable),
-	.pause(pause),
+  .enable(do_enable),
+  .pause(pause),
 
-	.eot(request_eot)
+  .eot(request_eot)
 );
 
 sync_bits #(
-	.NUM_OF_BITS(3),
-	.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+  .NUM_OF_BITS(3),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
 ) i_sync_control_dest (
-	.out_clk(dest_clk),
-	.out_resetn(dest_resetn),
-	.in({do_enable, pause, sync_id}),
-	.out({dest_enable, dest_pause, dest_sync_id})
+  .out_clk(dest_clk),
+  .out_resetn(dest_resetn),
+  .in({do_enable, pause, sync_id}),
+  .out({dest_enable, dest_pause, dest_sync_id})
 );
 
 sync_bits #(
-	.NUM_OF_BITS(2),
-	.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+  .NUM_OF_BITS(2),
+  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
 ) i_sync_status_dest (
-	.out_clk(req_aclk),
-	.out_resetn(req_aresetn),
-	.in({dest_enabled | ~dest_response_empty, dest_sync_id_ret}),
-	.out({enabled_dest, sync_id_ret_dest})
+  .out_clk(req_aclk),
+  .out_resetn(req_aresetn),
+  .in({dest_enabled | ~dest_response_empty, dest_sync_id_ret}),
+  .out({enabled_dest, sync_id_ret_dest})
 );
 
 sync_bits #(
-	.NUM_OF_BITS(3),
-	.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  .NUM_OF_BITS(3),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
 ) i_sync_control_src (
-	.out_clk(src_clk),
-	.out_resetn(src_resetn),
-	.in({do_enable, pause, sync_id}),
-	.out({src_enable, src_pause, src_sync_id})
+  .out_clk(src_clk),
+  .out_resetn(src_resetn),
+  .in({do_enable, pause, sync_id}),
+  .out({src_enable, src_pause, src_sync_id})
 );
 
 sync_bits #(
-	.NUM_OF_BITS(3),
-	.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  .NUM_OF_BITS(3),
+  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
 ) i_sync_status_src (
-	.out_clk(req_aclk),
-	.out_resetn(req_aresetn),
-	.in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}),
-	.out({enabled_src, sync_id_ret_src, fifo_empty})
+  .out_clk(req_aclk),
+  .out_resetn(req_aresetn),
+  .in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}),
+  .out({enabled_src, sync_id_ret_src, fifo_empty})
 );
 
 endmodule
diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v
index 7a6df253d..d56a5e8c5 100644
--- a/library/axi_dmac/request_generator.v
+++ b/library/axi_dmac/request_generator.v
@@ -37,20 +37,20 @@
 // ***************************************************************************
 
 module dmac_request_generator (
-	input req_aclk,
-	input req_aresetn,
+  input req_aclk,
+  input req_aresetn,
 
-	output [ID_WIDTH-1:0] request_id,
-	input [ID_WIDTH-1:0] response_id,
+  output [ID_WIDTH-1:0] request_id,
+  input [ID_WIDTH-1:0] response_id,
 
-	input req_valid,
-	output reg req_ready,
-	input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
+  input req_valid,
+  output reg req_ready,
+  input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
 
-	input enable,
-	input pause,
+  input enable,
+  input pause,
 
-	output eot
+  output eot
 );
 
 parameter ID_WIDTH = 3;
@@ -74,25 +74,25 @@ assign request_id = id;
 
 always @(posedge req_aclk)
 begin
-	if (req_aresetn == 1'b0) begin
-		burst_count <= 'h00;
-		id <= 'h0;
-		req_ready <= 1'b1;
-	end else if (enable == 1'b0) begin
-		req_ready <= 1'b1;
-	end else begin
-		if (req_ready) begin
-			if (req_valid && enable) begin
-				burst_count <= req_burst_count;
-				req_ready <= 1'b0;
-			end
-		end else if (response_id != id_next && ~pause) begin
-			if (eot)
-				req_ready <= 1'b1;
-			burst_count <= burst_count - 1'b1;
-			id <= id_next;
-		end
-	end
+  if (req_aresetn == 1'b0) begin
+    burst_count <= 'h00;
+    id <= 'h0;
+    req_ready <= 1'b1;
+  end else if (enable == 1'b0) begin
+    req_ready <= 1'b1;
+  end else begin
+    if (req_ready) begin
+      if (req_valid && enable) begin
+        burst_count <= req_burst_count;
+        req_ready <= 1'b0;
+      end
+    end else if (response_id != id_next && ~pause) begin
+      if (eot)
+        req_ready <= 1'b1;
+      burst_count <= burst_count - 1'b1;
+      id <= id_next;
+    end
+  end
 end
 
 endmodule
diff --git a/library/axi_dmac/response_generator.v b/library/axi_dmac/response_generator.v
index 1ed4aae02..61104d36f 100644
--- a/library/axi_dmac/response_generator.v
+++ b/library/axi_dmac/response_generator.v
@@ -37,22 +37,22 @@
 // ***************************************************************************
 
 module dmac_response_generator (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input enable,
-	output reg enabled,
+  input enable,
+  output reg enabled,
 
-	input [ID_WIDTH-1:0] request_id,
-	output reg [ID_WIDTH-1:0] response_id,
-	input sync_id,
+  input [ID_WIDTH-1:0] request_id,
+  output reg [ID_WIDTH-1:0] response_id,
+  input sync_id,
 
-	input eot,
+  input eot,
 
-	output resp_valid,
-	input resp_ready,
-	output resp_eot,
-	output [1:0] resp_resp
+  output resp_valid,
+  input resp_ready,
+  output resp_eot,
+  output [1:0] resp_resp
 );
 
 parameter ID_WIDTH = 3;
@@ -67,24 +67,24 @@ assign resp_valid = request_id != response_id && enabled;
 
 // We have to wait for all responses before we can disable the response handler
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		enabled <= 1'b0;
-	end else begin
-		if (enable)
-			enabled <= 1'b1;
-		else if (request_id == response_id)
-			enabled <= 1'b0;
-	end
+  if (resetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+    if (enable)
+      enabled <= 1'b1;
+    else if (request_id == response_id)
+      enabled <= 1'b0;
+  end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		response_id <= 'h0;
-	end else begin
-		if ((resp_valid && resp_ready) ||
-			(sync_id && response_id != request_id))
-			response_id <= inc_id(response_id);
-	end
+  if (resetn == 1'b0) begin
+    response_id <= 'h0;
+  end else begin
+    if ((resp_valid && resp_ready) ||
+      (sync_id && response_id != request_id))
+      response_id <= inc_id(response_id);
+  end
 end
 
 endmodule
diff --git a/library/axi_dmac/response_handler.v b/library/axi_dmac/response_handler.v
index 3c62915f6..cd64ba7e7 100644
--- a/library/axi_dmac/response_handler.v
+++ b/library/axi_dmac/response_handler.v
@@ -37,26 +37,26 @@
 // ***************************************************************************
 
 module dmac_response_handler (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input bvalid,
-	output bready,
-	input [1:0] bresp,
+  input bvalid,
+  output bready,
+  input [1:0] bresp,
 
-	output reg [ID_WIDTH-1:0] id,
-	input [ID_WIDTH-1:0] request_id,
-	input sync_id,
+  output reg [ID_WIDTH-1:0] id,
+  input [ID_WIDTH-1:0] request_id,
+  input sync_id,
 
-	input enable,
-	output reg enabled,
+  input enable,
+  output reg enabled,
 
-	input eot,
+  input eot,
 
-	output resp_valid,
-	input resp_ready,
-	output resp_eot,
-	output [1:0] resp_resp
+  output resp_valid,
+  input resp_ready,
+  output resp_eot,
+  output [1:0] resp_resp
 );
 
 parameter ID_WIDTH = 3;
@@ -74,24 +74,24 @@ assign resp_valid = active && bvalid;
 
 // We have to wait for all responses before we can disable the response handler
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		enabled <= 1'b0;
-	end else begin
-	if (enable)
-	    enabled <= 1'b1;
-	else if (request_id == id)
-	    enabled <= 1'b0;
-	end
+  if (resetn == 1'b0) begin
+    enabled <= 1'b0;
+  end else begin
+  if (enable)
+      enabled <= 1'b1;
+  else if (request_id == id)
+      enabled <= 1'b0;
+  end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		id <= 'h0;
-	end else begin
-		if ((bready && bvalid) ||
-		    (sync_id && id != request_id))
-			id <= inc_id(id);
-	end
+  if (resetn == 1'b0) begin
+    id <= 'h0;
+  end else begin
+    if ((bready && bvalid) ||
+        (sync_id && id != request_id))
+      id <= inc_id(id);
+  end
 end
 
 endmodule
diff --git a/library/axi_dmac/splitter.v b/library/axi_dmac/splitter.v
index 3d262c54e..4fee19f95 100644
--- a/library/axi_dmac/splitter.v
+++ b/library/axi_dmac/splitter.v
@@ -37,14 +37,14 @@
 
 
 module splitter (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input s_valid,
-	output s_ready,
+  input s_valid,
+  output s_ready,
 
-	output [NUM_M-1:0] m_valid,
-	input [NUM_M-1:0] m_ready
+  output [NUM_M-1:0] m_valid,
+  input [NUM_M-1:0] m_ready
 );
 
 parameter NUM_M = 2;
@@ -56,14 +56,14 @@ assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
 
 always @(posedge clk)
 begin
-	if (resetn == 1'b0) begin
-		acked <= {NUM_M{1'b0}};
-	end else begin
-		if (s_valid & s_ready)
-			acked <= {NUM_M{1'b0}};
-		else
-			acked <= acked | (m_ready & m_valid);
-	end
+  if (resetn == 1'b0) begin
+    acked <= {NUM_M{1'b0}};
+  end else begin
+    if (s_valid & s_ready)
+      acked <= {NUM_M{1'b0}};
+    else
+      acked <= acked | (m_ready & m_valid);
+  end
 end
 
 endmodule
diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v
index 4fb149fb1..c1a06b0d8 100644
--- a/library/axi_dmac/src_axi_mm.v
+++ b/library/axi_dmac/src_axi_mm.v
@@ -37,51 +37,51 @@
 // ***************************************************************************
 
 module dmac_src_mm_axi (
-	input                           m_axi_aclk,
-	input                           m_axi_aresetn,
+  input                           m_axi_aclk,
+  input                           m_axi_aresetn,
 
-	input                           req_valid,
-	output                          req_ready,
-	input [31:BYTES_PER_BEAT_WIDTH]    req_address,
-	input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input                           req_valid,
+  output                          req_ready,
+  input [31:BYTES_PER_BEAT_WIDTH]    req_address,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
 
-	input                           enable,
-	output                          enabled,
-	input                           pause,
-	input                           sync_id,
-	output                          sync_id_ret,
+  input                           enable,
+  output                          enabled,
+  input                           pause,
+  input                           sync_id,
+  output                          sync_id_ret,
 
-	output                          response_valid,
-	input                           response_ready,
-	output [1:0]                    response_resp,
+  output                          response_valid,
+  input                           response_ready,
+  output [1:0]                    response_resp,
 
-	input  [ID_WIDTH-1:0]         request_id,
-	output [ID_WIDTH-1:0]         response_id,
+  input  [ID_WIDTH-1:0]         request_id,
+  output [ID_WIDTH-1:0]         response_id,
 
-	output [ID_WIDTH-1:0]         data_id,
-	output [ID_WIDTH-1:0]         address_id,
-	input                           data_eot,
-	input                           address_eot,
+  output [ID_WIDTH-1:0]         data_id,
+  output [ID_WIDTH-1:0]         address_id,
+  input                           data_eot,
+  input                           address_eot,
 
-	output                          fifo_valid,
-	input                           fifo_ready,
-	output [DMA_DATA_WIDTH-1:0]   fifo_data,
+  output                          fifo_valid,
+  input                           fifo_ready,
+  output [DMA_DATA_WIDTH-1:0]   fifo_data,
 
-	// Read address
-	input                            m_axi_arready,
-	output                           m_axi_arvalid,
-	output [31:0]                    m_axi_araddr,
-	output [ 7:0]                    m_axi_arlen,
-	output [ 2:0]                    m_axi_arsize,
-	output [ 1:0]                    m_axi_arburst,
-	output [ 2:0]                    m_axi_arprot,
-	output [ 3:0]                    m_axi_arcache,
+  // Read address
+  input                            m_axi_arready,
+  output                           m_axi_arvalid,
+  output [31:0]                    m_axi_araddr,
+  output [ 7:0]                    m_axi_arlen,
+  output [ 2:0]                    m_axi_arsize,
+  output [ 1:0]                    m_axi_arburst,
+  output [ 2:0]                    m_axi_arprot,
+  output [ 3:0]                    m_axi_arcache,
 
-	// Read data and response
-	input  [DMA_DATA_WIDTH-1:0]    m_axi_rdata,
-	output                           m_axi_rready,
-	input                            m_axi_rvalid,
-	input  [ 1:0]                    m_axi_rresp
+  // Read data and response
+  input  [DMA_DATA_WIDTH-1:0]    m_axi_rdata,
+  output                           m_axi_rready,
+  input                            m_axi_rvalid,
+  input  [ 1:0]                    m_axi_rresp
 );
 
 parameter ID_WIDTH = 3;
@@ -105,95 +105,95 @@ assign response_valid = 1'b0;
 assign response_resp = RESP_OKAY;
 
 splitter #(
-	.NUM_M(2)
+  .NUM_M(2)
 ) i_req_splitter (
-	.clk(m_axi_aclk),
-	.resetn(m_axi_aresetn),
-	.s_valid(req_valid),
-	.s_ready(req_ready),
-	.m_valid({
-		address_req_valid,
-		data_req_valid
-	}),
-	.m_ready({
-		address_req_ready,
-		data_req_ready
-	})
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
+  .s_valid(req_valid),
+  .s_ready(req_ready),
+  .m_valid({
+    address_req_valid,
+    data_req_valid
+  }),
+  .m_ready({
+    address_req_ready,
+    data_req_ready
+  })
 );
 
 dmac_address_generator #(
-	.ID_WIDTH(ID_WIDTH),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
-	.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
-	.DMA_DATA_WIDTH(DMA_DATA_WIDTH)
+  .ID_WIDTH(ID_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
+  .DMA_DATA_WIDTH(DMA_DATA_WIDTH)
 ) i_addr_gen (
-	.clk(m_axi_aclk),
-	.resetn(m_axi_aresetn),
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
 
-	.enable(enable),
-	.enabled(address_enabled),
-	.pause(pause),
-	.sync_id(sync_id),
+  .enable(enable),
+  .enabled(address_enabled),
+  .pause(pause),
+  .sync_id(sync_id),
 
-	.request_id(request_id),
-	.id(address_id),
+  .request_id(request_id),
+  .id(address_id),
 
-	.req_valid(address_req_valid),
-	.req_ready(address_req_ready),
-	.req_address(req_address),
-	.req_last_burst_length(req_last_burst_length),
+  .req_valid(address_req_valid),
+  .req_ready(address_req_ready),
+  .req_address(req_address),
+  .req_last_burst_length(req_last_burst_length),
 
-	.eot(address_eot),
+  .eot(address_eot),
 
-	.addr_ready(m_axi_arready),
-	.addr_valid(m_axi_arvalid),
-	.addr(m_axi_araddr),
-	.len(m_axi_arlen),
-	.size(m_axi_arsize),
-	.burst(m_axi_arburst),
-	.prot(m_axi_arprot),
-	.cache(m_axi_arcache)
+  .addr_ready(m_axi_arready),
+  .addr_valid(m_axi_arvalid),
+  .addr(m_axi_araddr),
+  .len(m_axi_arlen),
+  .size(m_axi_arsize),
+  .burst(m_axi_arburst),
+  .prot(m_axi_arprot),
+  .cache(m_axi_arcache)
 );
 
 dmac_data_mover # (
-	.ID_WIDTH(ID_WIDTH),
-	.DATA_WIDTH(DMA_DATA_WIDTH),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DMA_DATA_WIDTH),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
 ) i_data_mover (
-	.clk(m_axi_aclk),
-	.resetn(m_axi_aresetn),
+  .clk(m_axi_aclk),
+  .resetn(m_axi_aresetn),
 
-	.enable(address_enabled),
-	.enabled(enabled),
-	.sync_id(sync_id),
+  .enable(address_enabled),
+  .enabled(enabled),
+  .sync_id(sync_id),
 
-	.xfer_req(),
+  .xfer_req(),
 
-	.request_id(address_id),
-	.response_id(data_id),
-	.eot(data_eot),
+  .request_id(address_id),
+  .response_id(data_id),
+  .eot(data_eot),
 
-	.req_valid(data_req_valid),
-	.req_ready(data_req_ready),
-	.req_last_burst_length(req_last_burst_length),
+  .req_valid(data_req_valid),
+  .req_ready(data_req_ready),
+  .req_last_burst_length(req_last_burst_length),
 
-	.s_axi_valid(m_axi_rvalid),
-	.s_axi_ready(m_axi_rready),
-	.s_axi_data(m_axi_rdata),
-	.m_axi_valid(fifo_valid),
-	.m_axi_ready(fifo_ready),
-	.m_axi_data(fifo_data),
-	.m_axi_last()
+  .s_axi_valid(m_axi_rvalid),
+  .s_axi_ready(m_axi_rready),
+  .s_axi_data(m_axi_rdata),
+  .m_axi_valid(fifo_valid),
+  .m_axi_ready(fifo_ready),
+  .m_axi_data(fifo_data),
+  .m_axi_last()
 );
 
 reg [1:0] rresp;
 
 always @(posedge m_axi_aclk)
 begin
-	if (m_axi_rvalid && m_axi_rready) begin
-		if (m_axi_rresp != 2'b0)
-			rresp <= m_axi_rresp;
-	end
+  if (m_axi_rvalid && m_axi_rready) begin
+    if (m_axi_rresp != 2'b0)
+      rresp <= m_axi_rresp;
+  end
 end
 
 endmodule
diff --git a/library/axi_dmac/src_axi_stream.v b/library/axi_dmac/src_axi_stream.v
index 4d281f7e1..a2c41a928 100644
--- a/library/axi_dmac/src_axi_stream.v
+++ b/library/axi_dmac/src_axi_stream.v
@@ -37,32 +37,32 @@
 // ***************************************************************************
 
 module dmac_src_axi_stream (
-	input s_axis_aclk,
-	input s_axis_aresetn,
+  input s_axis_aclk,
+  input s_axis_aresetn,
 
-	input enable,
-	output enabled,
-	input sync_id,
-	output sync_id_ret,
+  input enable,
+  output enabled,
+  input sync_id,
+  output sync_id_ret,
 
-	input [ID_WIDTH-1:0] request_id,
-	output [ID_WIDTH-1:0] response_id,
-	input eot,
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  input eot,
 
-	output s_axis_ready,
-	input s_axis_valid,
-	input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,
-	input [0:0] s_axis_user,
-	output s_axis_xfer_req,
+  output s_axis_ready,
+  input s_axis_valid,
+  input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,
+  input [0:0] s_axis_user,
+  output s_axis_xfer_req,
 
-	input fifo_ready,
-	output fifo_valid,
-	output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
+  input fifo_ready,
+  output fifo_valid,
+  output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
 
-	input req_valid,
-	output req_ready,
-	input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
-	input req_sync_transfer_start
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input req_sync_transfer_start
 );
 
 parameter ID_WIDTH = 3;
@@ -78,46 +78,46 @@ assign sync_id_ret = sync_id;
 
 always @(posedge s_axis_aclk)
 begin
-	if (s_axis_aresetn == 1'b0) begin
-		needs_sync <= 1'b0;
-	end else begin
-		if (s_axis_valid && s_axis_ready && sync) begin
-			needs_sync <= 1'b0;
-		end else if (req_valid && req_ready) begin
-			needs_sync <= req_sync_transfer_start;
-		end
-	end
+  if (s_axis_aresetn == 1'b0) begin
+    needs_sync <= 1'b0;
+  end else begin
+    if (s_axis_valid && s_axis_ready && sync) begin
+      needs_sync <= 1'b0;
+    end else if (req_valid && req_ready) begin
+      needs_sync <= req_sync_transfer_start;
+    end
+  end
 end
 
 dmac_data_mover # (
-	.ID_WIDTH(ID_WIDTH),
-	.DATA_WIDTH(S_AXIS_DATA_WIDTH),
-	.DISABLE_WAIT_FOR_ID(0),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(S_AXIS_DATA_WIDTH),
+  .DISABLE_WAIT_FOR_ID(0),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
 ) i_data_mover (
-	.clk(s_axis_aclk),
-	.resetn(s_axis_aresetn),
+  .clk(s_axis_aclk),
+  .resetn(s_axis_aresetn),
 
-	.enable(enable),
-	.enabled(enabled),
-	.sync_id(sync_id),
+  .enable(enable),
+  .enabled(enabled),
+  .sync_id(sync_id),
 
-	.xfer_req(s_axis_xfer_req),
+  .xfer_req(s_axis_xfer_req),
 
-	.request_id(request_id),
-	.response_id(response_id),
-	.eot(eot),
-	
-	.req_valid(req_valid),
-	.req_ready(req_ready),
-	.req_last_burst_length(req_last_burst_length),
+  .request_id(request_id),
+  .response_id(response_id),
+  .eot(eot),
+  
+  .req_valid(req_valid),
+  .req_ready(req_ready),
+  .req_last_burst_length(req_last_burst_length),
 
-	.s_axi_ready(s_axis_ready),
-	.s_axi_valid(sync_valid),
-	.s_axi_data(s_axis_data),
-	.m_axi_ready(fifo_ready),
-	.m_axi_valid(fifo_valid),
-	.m_axi_data(fifo_data)
+  .s_axi_ready(s_axis_ready),
+  .s_axi_valid(sync_valid),
+  .s_axi_data(s_axis_data),
+  .m_axi_ready(fifo_ready),
+  .m_axi_valid(fifo_valid),
+  .m_axi_data(fifo_data)
 );
 
 endmodule
diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v
index bb28ce421..633cc1ab4 100644
--- a/library/axi_dmac/src_fifo_inf.v
+++ b/library/axi_dmac/src_fifo_inf.v
@@ -37,32 +37,32 @@
 // ***************************************************************************
 
 module dmac_src_fifo_inf (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input enable,
-	output enabled,
-	input sync_id,
-	output sync_id_ret,
+  input enable,
+  output enabled,
+  input sync_id,
+  output sync_id_ret,
 
-	input [ID_WIDTH-1:0] request_id,
-	output [ID_WIDTH-1:0] response_id,
-	input eot,
+  input [ID_WIDTH-1:0] request_id,
+  output [ID_WIDTH-1:0] response_id,
+  input eot,
 
-	input en,
-	input [DATA_WIDTH-1:0] din,
-	output reg overflow,
-	input sync,
-	output xfer_req,
+  input en,
+  input [DATA_WIDTH-1:0] din,
+  output reg overflow,
+  input sync,
+  output xfer_req,
 
-	input fifo_ready,
-	output fifo_valid,
-	output [DATA_WIDTH-1:0] fifo_data,
+  input fifo_ready,
+  output fifo_valid,
+  output [DATA_WIDTH-1:0] fifo_data,
 
-	input req_valid,
-	output req_ready,
-	input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
-	input req_sync_transfer_start
+  input req_valid,
+  output req_ready,
+  input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
+  input req_sync_transfer_start
 );
 
 parameter ID_WIDTH = 3;
@@ -77,62 +77,62 @@ wire sync_valid = en & ready & has_sync;
 
 always @(posedge clk)
 begin
-	if (resetn == 1'b0) begin
-		needs_sync <= 1'b0;
-	end else begin
-		if (ready && en && sync) begin
-			needs_sync <= 1'b0;
-		end else if (req_valid && req_ready) begin
-			needs_sync <= req_sync_transfer_start;
-		end
-	end
+  if (resetn == 1'b0) begin
+    needs_sync <= 1'b0;
+  end else begin
+    if (ready && en && sync) begin
+      needs_sync <= 1'b0;
+    end else if (req_valid && req_ready) begin
+      needs_sync <= req_sync_transfer_start;
+    end
+  end
 end
 
 always @(posedge clk)
 begin
-	if (resetn == 1'b0) begin
-		overflow <= 1'b0;
-	end else begin
-		if (enable) begin
-			overflow <= en & ~ready;
-		end else begin
-			overflow <= en;
-		end
-	end
+  if (resetn == 1'b0) begin
+    overflow <= 1'b0;
+  end else begin
+    if (enable) begin
+      overflow <= en & ~ready;
+    end else begin
+      overflow <= en;
+    end
+  end
 end
 
 assign sync_id_ret = sync_id;
 
 dmac_data_mover # (
-	.ID_WIDTH(ID_WIDTH),
-	.DATA_WIDTH(DATA_WIDTH),
-	.DISABLE_WAIT_FOR_ID(0),
-	.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+  .ID_WIDTH(ID_WIDTH),
+  .DATA_WIDTH(DATA_WIDTH),
+  .DISABLE_WAIT_FOR_ID(0),
+  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
 ) i_data_mover (
-	.clk(clk),
-	.resetn(resetn),
+  .clk(clk),
+  .resetn(resetn),
 
-	.enable(enable),
-	.enabled(enabled),
-	.sync_id(sync_id),
+  .enable(enable),
+  .enabled(enabled),
+  .sync_id(sync_id),
 
-	.xfer_req(xfer_req),
+  .xfer_req(xfer_req),
 
-	.request_id(request_id),
-	.response_id(response_id),
-	.eot(eot),
-	
-	.req_valid(req_valid),
-	.req_ready(req_ready),
-	.req_last_burst_length(req_last_burst_length),
+  .request_id(request_id),
+  .response_id(response_id),
+  .eot(eot),
+  
+  .req_valid(req_valid),
+  .req_ready(req_ready),
+  .req_last_burst_length(req_last_burst_length),
 
-	.s_axi_ready(ready),
-	.s_axi_valid(sync_valid),
-	.s_axi_data(din),
-	.m_axi_ready(fifo_ready),
-	.m_axi_valid(fifo_valid),
-	.m_axi_data(fifo_data),
-	.m_axi_last()
+  .s_axi_ready(ready),
+  .s_axi_valid(sync_valid),
+  .s_axi_data(din),
+  .m_axi_ready(fifo_ready),
+  .m_axi_valid(fifo_valid),
+  .m_axi_data(fifo_data),
+  .m_axi_last()
 );
 
 endmodule
diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v
index 32d4cc389..a9f20b320 100644
--- a/library/axi_generic_adc/axi_generic_adc.v
+++ b/library/axi_generic_adc/axi_generic_adc.v
@@ -1,27 +1,27 @@
 module axi_generic_adc (
-	input adc_clk,
-	output [NUM_OF_CHANNELS-1:0] adc_enable,
-	input adc_dovf,
+  input adc_clk,
+  output [NUM_OF_CHANNELS-1:0] adc_enable,
+  input adc_dovf,
 
-	input		s_axi_aclk,
-	input		s_axi_aresetn,
-	input		s_axi_awvalid,
-	input	 [31:0]	s_axi_awaddr,
-	output		s_axi_awready,
-	input		s_axi_wvalid,
-	input	 [31:0]	s_axi_wdata,
-	input	 [ 3:0]	s_axi_wstrb,
-	output		s_axi_wready,
-	output		s_axi_bvalid,
-	output	[ 1:0]	s_axi_bresp,
-	input		s_axi_bready,
-	input		s_axi_arvalid,
-	input	 [31:0]	s_axi_araddr,
-	output		s_axi_arready,
-	output		s_axi_rvalid,
-	output	[ 1:0]	s_axi_rresp,
-	output	[31:0]	s_axi_rdata,
-	input		s_axi_rready,
+  input    s_axi_aclk,
+  input    s_axi_aresetn,
+  input    s_axi_awvalid,
+  input   [31:0]  s_axi_awaddr,
+  output    s_axi_awready,
+  input    s_axi_wvalid,
+  input   [31:0]  s_axi_wdata,
+  input   [ 3:0]  s_axi_wstrb,
+  output    s_axi_wready,
+  output    s_axi_bvalid,
+  output  [ 1:0]  s_axi_bresp,
+  input    s_axi_bready,
+  input    s_axi_arvalid,
+  input   [31:0]  s_axi_araddr,
+  output    s_axi_arready,
+  output    s_axi_rvalid,
+  output  [ 1:0]  s_axi_rresp,
+  output  [31:0]  s_axi_rdata,
+  input    s_axi_rready,
   input   [ 2:0]  s_axi_awprot,
   input   [ 2:0]  s_axi_arprot
 
@@ -30,7 +30,7 @@ module axi_generic_adc (
 parameter NUM_OF_CHANNELS = 2;
 parameter ID = 0;
 
-reg	[31:0] up_rdata = 'd0;
+reg  [31:0] up_rdata = 'd0;
 reg        up_rack = 'd0;
 reg        up_wack = 'd0;
 
@@ -60,145 +60,145 @@ assign up_rstn = s_axi_aresetn;
 integer j;
 always @(*)
 begin
-	up_rdata_r = 'h00;
-	up_rack_r = 'h00;
-	up_wack_r = 'h00;
-	for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin
-		up_rack_r = up_rack_r | up_rack_s[j];
-		up_wack_r = up_wack_r | up_wack_s[j];
-		up_rdata_r = up_rdata_r | up_rdata_s[j];
-	end
+  up_rdata_r = 'h00;
+  up_rack_r = 'h00;
+  up_wack_r = 'h00;
+  for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin
+    up_rack_r = up_rack_r | up_rack_s[j];
+    up_wack_r = up_wack_r | up_wack_s[j];
+    up_rdata_r = up_rdata_r | up_rdata_s[j];
+  end
 end
 
 always @(negedge up_rstn or posedge up_clk) begin
-	if (up_rstn == 0) begin
-		up_rdata <= 'd0;
-		up_rack <= 'd0;
-		up_wack <= 'd0;
-	end else begin
-		up_rdata <= up_rdata_r;
-		up_rack <= up_rack_r;
-		up_wack <= up_wack_r;
-	end
+  if (up_rstn == 0) begin
+    up_rdata <= 'd0;
+    up_rack <= 'd0;
+    up_wack <= 'd0;
+  end else begin
+    up_rdata <= up_rdata_r;
+    up_rack <= up_rack_r;
+    up_wack <= up_wack_r;
+  end
 end
  
 up_adc_common #(.ID(ID)) i_up_adc_common (
-	.mmcm_rst (),
-	.adc_clk (adc_clk),
-	.adc_rst (adc_rst),
-	.adc_r1_mode (),
-	.adc_ddr_edgesel (),
-	.adc_pin_mode (),
-	.adc_status ('h00),
-	.adc_status_ovf (adc_dovf),
-	.adc_status_unf (1'b0),
-	.adc_clk_ratio (32'd1),
+  .mmcm_rst (),
+  .adc_clk (adc_clk),
+  .adc_rst (adc_rst),
+  .adc_r1_mode (),
+  .adc_ddr_edgesel (),
+  .adc_pin_mode (),
+  .adc_status ('h00),
+  .adc_status_ovf (adc_dovf),
+  .adc_status_unf (1'b0),
+  .adc_clk_ratio (32'd1),
 
-	.up_status_pn_err (1'b0),
-	.up_status_pn_oos (1'b0),
-	.up_status_or (1'b0),
-	.up_drp_sel (),
-	.up_drp_wr (),
-	.up_drp_addr (),
-	.up_drp_wdata (),
-	.up_drp_rdata (32'd0),
-	.up_drp_ready (1'd0),
-	.up_drp_locked (1'd1),
-	.up_usr_chanmax (),
-	.adc_usr_chanmax (8'd0),
-	.up_adc_gpio_in (),
-	.up_adc_gpio_out (),
-	.up_rstn (up_rstn),
-	.up_clk (up_clk),
-	.up_wreq (up_wreq_s),
-	.up_waddr (up_waddr_s),
-	.up_wdata (up_wdata_s),
-	.up_wack (up_wack_s[NUM_OF_CHANNELS]),
-	.up_rreq (up_rreq_s),
-	.up_raddr (up_raddr_s),
-	.up_rdata (up_rdata_s[NUM_OF_CHANNELS]),
-	.up_rack (up_rack_s[NUM_OF_CHANNELS]));
+  .up_status_pn_err (1'b0),
+  .up_status_pn_oos (1'b0),
+  .up_status_or (1'b0),
+  .up_drp_sel (),
+  .up_drp_wr (),
+  .up_drp_addr (),
+  .up_drp_wdata (),
+  .up_drp_rdata (32'd0),
+  .up_drp_ready (1'd0),
+  .up_drp_locked (1'd1),
+  .up_usr_chanmax (),
+  .adc_usr_chanmax (8'd0),
+  .up_adc_gpio_in (),
+  .up_adc_gpio_out (),
+  .up_rstn (up_rstn),
+  .up_clk (up_clk),
+  .up_wreq (up_wreq_s),
+  .up_waddr (up_waddr_s),
+  .up_wdata (up_wdata_s),
+  .up_wack (up_wack_s[NUM_OF_CHANNELS]),
+  .up_rreq (up_rreq_s),
+  .up_raddr (up_raddr_s),
+  .up_rdata (up_rdata_s[NUM_OF_CHANNELS]),
+  .up_rack (up_rack_s[NUM_OF_CHANNELS]));
 
 // up bus interface
 
 up_axi i_up_axi (
-	.up_rstn (up_rstn),
-	.up_clk (up_clk),
-	.up_axi_awvalid (s_axi_awvalid),
-	.up_axi_awaddr (s_axi_awaddr),
-	.up_axi_awready (s_axi_awready),
-	.up_axi_wvalid (s_axi_wvalid),
-	.up_axi_wdata (s_axi_wdata),
-	.up_axi_wstrb (s_axi_wstrb),
-	.up_axi_wready (s_axi_wready),
-	.up_axi_bvalid (s_axi_bvalid),
-	.up_axi_bresp (s_axi_bresp),
-	.up_axi_bready (s_axi_bready),
-	.up_axi_arvalid (s_axi_arvalid),
-	.up_axi_araddr (s_axi_araddr),
-	.up_axi_arready (s_axi_arready),
-	.up_axi_rvalid (s_axi_rvalid),
-	.up_axi_rresp (s_axi_rresp),
-	.up_axi_rdata (s_axi_rdata),
-	.up_axi_rready (s_axi_rready),
-	.up_wreq (up_wreq_s),
-	.up_waddr (up_waddr_s),
-	.up_wdata (up_wdata_s),
-	.up_wack (up_wack),
-	.up_rreq (up_rreq_s),
-	.up_raddr (up_raddr_s),
-	.up_rdata (up_rdata),
-	.up_rack (up_rack));
+  .up_rstn (up_rstn),
+  .up_clk (up_clk),
+  .up_axi_awvalid (s_axi_awvalid),
+  .up_axi_awaddr (s_axi_awaddr),
+  .up_axi_awready (s_axi_awready),
+  .up_axi_wvalid (s_axi_wvalid),
+  .up_axi_wdata (s_axi_wdata),
+  .up_axi_wstrb (s_axi_wstrb),
+  .up_axi_wready (s_axi_wready),
+  .up_axi_bvalid (s_axi_bvalid),
+  .up_axi_bresp (s_axi_bresp),
+  .up_axi_bready (s_axi_bready),
+  .up_axi_arvalid (s_axi_arvalid),
+  .up_axi_araddr (s_axi_araddr),
+  .up_axi_arready (s_axi_arready),
+  .up_axi_rvalid (s_axi_rvalid),
+  .up_axi_rresp (s_axi_rresp),
+  .up_axi_rdata (s_axi_rdata),
+  .up_axi_rready (s_axi_rready),
+  .up_wreq (up_wreq_s),
+  .up_waddr (up_waddr_s),
+  .up_wdata (up_wdata_s),
+  .up_wack (up_wack),
+  .up_rreq (up_rreq_s),
+  .up_raddr (up_raddr_s),
+  .up_rdata (up_rdata),
+  .up_rack (up_rack));
 
 generate
 genvar i;
 
 for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin
-	up_adc_channel #(.CHANNEL_ID(i)) i_up_adc_channel (
-		.adc_clk (adc_clk),
-		.adc_rst (adc_rst),
-		.adc_enable (adc_enable[i]),
-		.adc_iqcor_enb (),
-		.adc_dcfilt_enb (),
-		.adc_dfmt_se (),
-		.adc_dfmt_type (),
-		.adc_dfmt_enable (),
-		.adc_dcfilt_offset (),
-		.adc_dcfilt_coeff (),
-		.adc_iqcor_coeff_1 (),
-		.adc_iqcor_coeff_2 (),
-		.adc_pnseq_sel (),
-		.adc_data_sel (),
-		.adc_pn_err (),
-		.adc_pn_oos (),
-		.adc_or (),
-		.up_adc_pn_err (),
-		.up_adc_pn_oos (),
-		.up_adc_or (),
-		.up_usr_datatype_be (),
-		.up_usr_datatype_signed (),
-		.up_usr_datatype_shift (),
-		.up_usr_datatype_total_bits (),
-		.up_usr_datatype_bits (),
-		.up_usr_decimation_m (),
-		.up_usr_decimation_n (),
-		.adc_usr_datatype_be (1'b0),
-		.adc_usr_datatype_signed (1'b1),
-		.adc_usr_datatype_shift (8'd0),
-		.adc_usr_datatype_total_bits (8'd32),
-		.adc_usr_datatype_bits (8'd32),
-		.adc_usr_decimation_m (16'd1),
-		.adc_usr_decimation_n (16'd1),
-		.up_rstn (up_rstn),
-		.up_clk (up_clk),
-		.up_wreq (up_wreq_s),
-		.up_waddr (up_waddr_s),
-		.up_wdata (up_wdata_s),
-		.up_wack (up_wack_s[i]),
-		.up_rreq (up_rreq_s),
-		.up_raddr (up_raddr_s),
-		.up_rdata (up_rdata_s[i]),
-		.up_rack (up_rack_s[i]));
+  up_adc_channel #(.CHANNEL_ID(i)) i_up_adc_channel (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_enable (adc_enable[i]),
+    .adc_iqcor_enb (),
+    .adc_dcfilt_enb (),
+    .adc_dfmt_se (),
+    .adc_dfmt_type (),
+    .adc_dfmt_enable (),
+    .adc_dcfilt_offset (),
+    .adc_dcfilt_coeff (),
+    .adc_iqcor_coeff_1 (),
+    .adc_iqcor_coeff_2 (),
+    .adc_pnseq_sel (),
+    .adc_data_sel (),
+    .adc_pn_err (),
+    .adc_pn_oos (),
+    .adc_or (),
+    .up_adc_pn_err (),
+    .up_adc_pn_oos (),
+    .up_adc_or (),
+    .up_usr_datatype_be (),
+    .up_usr_datatype_signed (),
+    .up_usr_datatype_shift (),
+    .up_usr_datatype_total_bits (),
+    .up_usr_datatype_bits (),
+    .up_usr_decimation_m (),
+    .up_usr_decimation_n (),
+    .adc_usr_datatype_be (1'b0),
+    .adc_usr_datatype_signed (1'b1),
+    .adc_usr_datatype_shift (8'd0),
+    .adc_usr_datatype_total_bits (8'd32),
+    .adc_usr_datatype_bits (8'd32),
+    .adc_usr_decimation_m (16'd1),
+    .adc_usr_decimation_n (16'd1),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[i]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[i]),
+    .up_rack (up_rack_s[i]));
 end
 
 endgenerate
diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
index dac6814b8..9db2eb39d 100644
--- a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
+++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
@@ -1,38 +1,38 @@
 module cn0363_dma_sequencer (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input [31:0] phase,
-	input phase_valid,
-	output reg phase_ready,
+  input [31:0] phase,
+  input phase_valid,
+  output reg phase_ready,
 
-	input [23:0] data,
-	input data_valid,
-	output reg data_ready,
+  input [23:0] data,
+  input data_valid,
+  output reg data_ready,
 
-	input [31:0] data_filtered,
-	input data_filtered_valid,
-	output reg data_filtered_ready,
+  input [31:0] data_filtered,
+  input data_filtered_valid,
+  output reg data_filtered_ready,
 
-	input [31:0] i_q,
-	input i_q_valid,
-	output reg i_q_ready,
+  input [31:0] i_q,
+  input i_q_valid,
+  output reg i_q_ready,
 
-	input [31:0] i_q_filtered,
-	input i_q_filtered_valid,
-	output reg i_q_filtered_ready,
+  input [31:0] i_q_filtered,
+  input i_q_filtered_valid,
+  output reg i_q_filtered_ready,
 
-	output overflow,
+  output overflow,
 
-	output reg [31:0] dma_wr_data,
-	output reg dma_wr_en,
-	output reg dma_wr_sync,
-	input dma_wr_overflow,
-	input dma_wr_xfer_req,
+  output reg [31:0] dma_wr_data,
+  output reg dma_wr_en,
+  output reg dma_wr_sync,
+  input dma_wr_overflow,
+  input dma_wr_xfer_req,
 
-	input [13:0] channel_enable,
+  input [13:0] channel_enable,
 
-	output processing_resetn
+  output processing_resetn
 );
 
 reg [3:0] count = 'h00;
@@ -41,120 +41,120 @@ assign overflow = dma_wr_overflow;
 assign processing_resetn = dma_wr_xfer_req;
 
 always @(posedge clk) begin
-	if (processing_resetn == 1'b0) begin
-		count <= 'h0;
-	end else begin
-		case (count)
-		'h0: if (phase_valid) count <= count + 1;
-		'h1: if (data_valid) count <= count + 1;
-		'h2: if (data_filtered_valid) count <= count + 1;
-		'h3: if (i_q_valid) count <= count + 1;
-		'h4: if (i_q_valid) count <= count + 1;
-		'h5: if (i_q_filtered_valid) count <= count + 1;
-		'h6: if (i_q_filtered_valid) count <= count + 1;
-		'h7: if (phase_valid) count <= count + 1;
-		'h8: if (data_valid) count <= count + 1;
-		'h9: if (data_filtered_valid) count <= count + 1;
-		'ha: if (i_q_valid) count <= count + 1;
-		'hb: if (i_q_valid) count <= count + 1;
-		'hc: if (i_q_filtered_valid) count <= count + 1;
-		'hd: if (i_q_filtered_valid) count <= 'h00;
-		endcase
-	end
+  if (processing_resetn == 1'b0) begin
+    count <= 'h0;
+  end else begin
+    case (count)
+    'h0: if (phase_valid) count <= count + 1;
+    'h1: if (data_valid) count <= count + 1;
+    'h2: if (data_filtered_valid) count <= count + 1;
+    'h3: if (i_q_valid) count <= count + 1;
+    'h4: if (i_q_valid) count <= count + 1;
+    'h5: if (i_q_filtered_valid) count <= count + 1;
+    'h6: if (i_q_filtered_valid) count <= count + 1;
+    'h7: if (phase_valid) count <= count + 1;
+    'h8: if (data_valid) count <= count + 1;
+    'h9: if (data_filtered_valid) count <= count + 1;
+    'ha: if (i_q_valid) count <= count + 1;
+    'hb: if (i_q_valid) count <= count + 1;
+    'hc: if (i_q_filtered_valid) count <= count + 1;
+    'hd: if (i_q_filtered_valid) count <= 'h00;
+    endcase
+  end
 end
 
 always @(posedge clk) begin
-	case (count)
-	'h0: dma_wr_data <= phase;
-	'h1: dma_wr_data <= {8'h00,data[23:0]};
-	'h2: dma_wr_data <= data_filtered;
-	'h3: dma_wr_data <= i_q;
-	'h4: dma_wr_data <= i_q;
-	'h5: dma_wr_data <= i_q_filtered;
-	'h6: dma_wr_data <= i_q_filtered;
-	'h7: dma_wr_data <= phase;
-	'h8: dma_wr_data <= {8'h00,data[23:0]};
-	'h9: dma_wr_data <= data_filtered;
-	'ha: dma_wr_data <= i_q;
-	'hb: dma_wr_data <= i_q;
-	'hc: dma_wr_data <= i_q_filtered;
-	'hd: dma_wr_data <= i_q_filtered;
-	endcase
+  case (count)
+  'h0: dma_wr_data <= phase;
+  'h1: dma_wr_data <= {8'h00,data[23:0]};
+  'h2: dma_wr_data <= data_filtered;
+  'h3: dma_wr_data <= i_q;
+  'h4: dma_wr_data <= i_q;
+  'h5: dma_wr_data <= i_q_filtered;
+  'h6: dma_wr_data <= i_q_filtered;
+  'h7: dma_wr_data <= phase;
+  'h8: dma_wr_data <= {8'h00,data[23:0]};
+  'h9: dma_wr_data <= data_filtered;
+  'ha: dma_wr_data <= i_q;
+  'hb: dma_wr_data <= i_q;
+  'hc: dma_wr_data <= i_q_filtered;
+  'hd: dma_wr_data <= i_q_filtered;
+  endcase
 end
 
 always @(posedge clk) begin
-	if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin
-		dma_wr_en <= 1'b0;
-	end else begin
-		case (count)
-		'h0: dma_wr_en <= phase_valid;
-		'h1: dma_wr_en <= data_valid;
-		'h2: dma_wr_en <= data_filtered_valid;
-		'h3: dma_wr_en <= i_q_valid;
-		'h4: dma_wr_en <= i_q_valid;
-		'h5: dma_wr_en <= i_q_filtered_valid;
-		'h6: dma_wr_en <= i_q_filtered_valid;
-		'h7: dma_wr_en <= phase_valid;
-		'h8: dma_wr_en <= data_valid;
-		'h9: dma_wr_en <= data_filtered_valid;
-		'ha: dma_wr_en <= i_q_valid;
-		'hb: dma_wr_en <= i_q_valid;
-		'hc: dma_wr_en <= i_q_filtered_valid;
-		'hd: dma_wr_en <= i_q_filtered_valid;
-		endcase
-	end
+  if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin
+    dma_wr_en <= 1'b0;
+  end else begin
+    case (count)
+    'h0: dma_wr_en <= phase_valid;
+    'h1: dma_wr_en <= data_valid;
+    'h2: dma_wr_en <= data_filtered_valid;
+    'h3: dma_wr_en <= i_q_valid;
+    'h4: dma_wr_en <= i_q_valid;
+    'h5: dma_wr_en <= i_q_filtered_valid;
+    'h6: dma_wr_en <= i_q_filtered_valid;
+    'h7: dma_wr_en <= phase_valid;
+    'h8: dma_wr_en <= data_valid;
+    'h9: dma_wr_en <= data_filtered_valid;
+    'ha: dma_wr_en <= i_q_valid;
+    'hb: dma_wr_en <= i_q_valid;
+    'hc: dma_wr_en <= i_q_filtered_valid;
+    'hd: dma_wr_en <= i_q_filtered_valid;
+    endcase
+  end
 end
 
 always @(posedge clk) begin
-	if (count == 'h00) begin
-		dma_wr_sync <= 1'b1;
-	end else if (dma_wr_en == 1'b1) begin
-		dma_wr_sync = 1'b0;
-	end
+  if (count == 'h00) begin
+    dma_wr_sync <= 1'b1;
+  end else if (dma_wr_en == 1'b1) begin
+    dma_wr_sync = 1'b0;
+  end
 end
 
 always @(*) begin
-	case (count)
-	'h0: phase_ready <= 1'b1;
-	'h7: phase_ready <= 1'b1;
-	default: phase_ready <= 1'b0;
-	endcase
+  case (count)
+  'h0: phase_ready <= 1'b1;
+  'h7: phase_ready <= 1'b1;
+  default: phase_ready <= 1'b0;
+  endcase
 end
 
 always @(*) begin
-	case (count)
-	'h1: data_ready <= 1'b1;
-	'h8: data_ready <= 1'b1;
-	default: data_ready <= 1'b0;
-	endcase
+  case (count)
+  'h1: data_ready <= 1'b1;
+  'h8: data_ready <= 1'b1;
+  default: data_ready <= 1'b0;
+  endcase
 end
 
 always @(*) begin
-	case (count)
-	'h2: data_filtered_ready <= 1'b1;
-	'h9: data_filtered_ready <= 1'b1;
-	default: data_filtered_ready <= 1'b0;
-	endcase
+  case (count)
+  'h2: data_filtered_ready <= 1'b1;
+  'h9: data_filtered_ready <= 1'b1;
+  default: data_filtered_ready <= 1'b0;
+  endcase
 end
 
 always @(*) begin
-	case (count)
-	'h3: i_q_ready <= 1'b1;
-	'h4: i_q_ready <= 1'b1;
-	'ha: i_q_ready <= 1'b1;
-	'hb: i_q_ready <= 1'b1;
-	default: i_q_ready <= 1'b0;
-	endcase
+  case (count)
+  'h3: i_q_ready <= 1'b1;
+  'h4: i_q_ready <= 1'b1;
+  'ha: i_q_ready <= 1'b1;
+  'hb: i_q_ready <= 1'b1;
+  default: i_q_ready <= 1'b0;
+  endcase
 end
 
 always @(*) begin
-	case (count)
-	'h5: i_q_filtered_ready <= 1'b1;
-	'h6: i_q_filtered_ready <= 1'b1;
-	'hc: i_q_filtered_ready <= 1'b1;
-	'hd: i_q_filtered_ready <= 1'b1;
-	default: i_q_filtered_ready <= 1'b0;
-	endcase
+  case (count)
+  'h5: i_q_filtered_ready <= 1'b1;
+  'h6: i_q_filtered_ready <= 1'b1;
+  'hc: i_q_filtered_ready <= 1'b1;
+  'hd: i_q_filtered_ready <= 1'b1;
+  default: i_q_filtered_ready <= 1'b0;
+  endcase
 end
 
 endmodule
diff --git a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
index c2bb1310b..d0e4baf58 100644
--- a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
+++ b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
@@ -1,29 +1,29 @@
 
 
 module cn0363_phase_data_sync (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input processing_resetn,
+  input processing_resetn,
 
-	output s_axis_sample_ready,
-	input s_axis_sample_valid,
-	input [7:0] s_axis_sample_data,
+  output s_axis_sample_ready,
+  input s_axis_sample_valid,
+  input [7:0] s_axis_sample_data,
 
-	input sample_has_stat,
+  input sample_has_stat,
 
-	input conv_done,
-	input [31:0] phase,
+  input conv_done,
+  input [31:0] phase,
 
-	output reg m_axis_sample_valid,
-	input m_axis_sample_ready,
-	output [23:0] m_axis_sample_data,
+  output reg m_axis_sample_valid,
+  input m_axis_sample_ready,
+  output [23:0] m_axis_sample_data,
 
-	output reg m_axis_phase_valid,
-	input m_axis_phase_ready,
-	output [31:0] m_axis_phase_data,
+  output reg m_axis_phase_valid,
+  input m_axis_phase_ready,
+  output [31:0] m_axis_phase_data,
 
-	output reg overflow
+  output reg overflow
 );
 
 reg [1:0] data_counter = 'h00;
@@ -46,38 +46,38 @@ assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]};
 assign m_axis_phase_data = phase_hold;
 
 always @(posedge clk) begin
-	if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin
-		// Is the processing pipeline ready to accept data?
-		if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin
-			overflow <= 1'b1;
-		end else begin
-			phase_hold <= phase;
-			overflow <= 1'b0;
-		end
-	end else begin
-		overflow <= 1'b0;
-	end
-	conv_done_d1 <= conv_done;
+  if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin
+    // Is the processing pipeline ready to accept data?
+    if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin
+      overflow <= 1'b1;
+    end else begin
+      phase_hold <= phase;
+      overflow <= 1'b0;
+    end
+  end else begin
+    overflow <= 1'b0;
+  end
+  conv_done_d1 <= conv_done;
 end
 
 always @(posedge clk) begin
-	if (processing_resetn == 1'b0) begin
-		m_axis_phase_valid <= 1'b0;
-		m_axis_sample_valid <= 1'b0;
-	end else begin
-		/* Data and phase become valid once we have both */
-		if (sample_hold_valid == 1'b1) begin
-			m_axis_phase_valid <= 1'b1;
-			m_axis_sample_valid <= 1'b1;
-		end else begin
-			if (m_axis_phase_ready == 1'b1) begin
-				m_axis_phase_valid <= 1'b0;
-			end
-			if (m_axis_sample_ready == 1'b1) begin
-				m_axis_sample_valid <= 1'b0;
-			end
-		end
-	end
+  if (processing_resetn == 1'b0) begin
+    m_axis_phase_valid <= 1'b0;
+    m_axis_sample_valid <= 1'b0;
+  end else begin
+    /* Data and phase become valid once we have both */
+    if (sample_hold_valid == 1'b1) begin
+      m_axis_phase_valid <= 1'b1;
+      m_axis_sample_valid <= 1'b1;
+    end else begin
+      if (m_axis_phase_ready == 1'b1) begin
+        m_axis_phase_valid <= 1'b0;
+      end
+      if (m_axis_sample_ready == 1'b1) begin
+        m_axis_sample_valid <= 1'b0;
+      end
+    end
+  end
 end
 
 /* If the STAT register is included in the sample we get 4 bytes per sample and
@@ -87,45 +87,45 @@ end
  * channel */
 
 always @(posedge clk) begin
-	sample_hold_valid <= 1'b0;
-	if (sample_has_stat == 1'b0) begin
-		if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin
-			sample_hold_valid <= 1'b1;
-		end
-	end else begin
-		if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 &&
-			(sync == 1'b1 || synced == 1'b1)) begin
-			sample_hold_valid <= 1'b1;
-		end
-	end
+  sample_hold_valid <= 1'b0;
+  if (sample_has_stat == 1'b0) begin
+    if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin
+      sample_hold_valid <= 1'b1;
+    end
+  end else begin
+    if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 &&
+      (sync == 1'b1 || synced == 1'b1)) begin
+      sample_hold_valid <= 1'b1;
+    end
+  end
 end
 
 always @(posedge clk) begin
-	if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin
-		sample_hold <= {sample_hold[15:0],s_axis_sample_data};
-	end
+  if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin
+    sample_hold <= {sample_hold[15:0],s_axis_sample_data};
+  end
 end
 
 always @(posedge clk) begin
-	if (s_axis_sample_valid == 1'b1) begin
-		if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin
-			data_counter <= 2'h0;
-		end else begin
-			data_counter <= data_counter + 1'b1;
-		end
-	end
+  if (s_axis_sample_valid == 1'b1) begin
+    if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin
+      data_counter <= 2'h0;
+    end else begin
+      data_counter <= data_counter + 1'b1;
+    end
+  end
 end
 
 assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3;
 
 always @(posedge clk) begin
-	if (processing_resetn == 1'b0) begin
-		synced <= ~sample_has_stat;
-	end else begin
-		if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin
-			synced <= 1'b1;
-		end
-	end
+  if (processing_resetn == 1'b0) begin
+    synced <= ~sample_has_stat;
+  end else begin
+    if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin
+      synced <= 1'b1;
+    end
+  end
 end
 
 endmodule
diff --git a/library/common/sync_bits.v b/library/common/sync_bits.v
index cec9f09ec..2530f047b 100644
--- a/library/common/sync_bits.v
+++ b/library/common/sync_bits.v
@@ -45,10 +45,10 @@
  */
 module sync_bits
 (
-	input [NUM_OF_BITS-1:0] in,
-	input out_resetn,
-	input out_clk,
-	output [NUM_OF_BITS-1:0] out
+  input [NUM_OF_BITS-1:0] in,
+  input out_resetn,
+  input out_clk,
+  output [NUM_OF_BITS-1:0] out
 );
 
 // Number of bits to synchronize
@@ -62,13 +62,13 @@ reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
 
 always @(posedge out_clk)
 begin
-	if (out_resetn == 1'b0) begin
-		cdc_sync_stage1 <= 'b0;
-		cdc_sync_stage2 <= 'b0;
-	end else begin
-		cdc_sync_stage1 <= in;
-		cdc_sync_stage2 <= cdc_sync_stage1;
-	end
+  if (out_resetn == 1'b0) begin
+    cdc_sync_stage1 <= 'b0;
+    cdc_sync_stage2 <= 'b0;
+  end else begin
+    cdc_sync_stage1 <= in;
+    cdc_sync_stage2 <= cdc_sync_stage1;
+  end
 end
 
 assign out = ASYNC_CLK ? cdc_sync_stage2 : in;
diff --git a/library/common/sync_gray.v b/library/common/sync_gray.v
index 701dfe37c..2b67e1266 100644
--- a/library/common/sync_gray.v
+++ b/library/common/sync_gray.v
@@ -43,12 +43,12 @@
  * change by either -1, 0 or +1.
  */
 module sync_gray (
-	input in_clk,
-	input in_resetn,
-	input [DATA_WIDTH-1:0] in_count,
-	input out_resetn,
-	input out_clk,
-	output [DATA_WIDTH-1:0] out_count
+  input in_clk,
+  input in_resetn,
+  input [DATA_WIDTH-1:0] in_count,
+  input out_resetn,
+  input out_clk,
+  output [DATA_WIDTH-1:0] out_count
 );
 
 // Bit-width of the counter
@@ -63,47 +63,47 @@ reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
 reg [DATA_WIDTH-1:0] out_count_m = 'h0;
 
 function [DATA_WIDTH-1:0] g2b;
-	input [DATA_WIDTH-1:0] g;
-	reg   [DATA_WIDTH-1:0] b;
-	integer i;
-	begin
-		b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
-		for (i = DATA_WIDTH - 2; i >= 0; i =  i - 1)
-			b[i] = b[i + 1] ^ g[i];
-		g2b = b;
-	end
+  input [DATA_WIDTH-1:0] g;
+  reg   [DATA_WIDTH-1:0] b;
+  integer i;
+  begin
+    b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
+    for (i = DATA_WIDTH - 2; i >= 0; i =  i - 1)
+      b[i] = b[i + 1] ^ g[i];
+    g2b = b;
+  end
 endfunction
 
 function [DATA_WIDTH-1:0] b2g;
-	input [DATA_WIDTH-1:0] b;
-	reg [DATA_WIDTH-1:0] g;
-	integer i;
-	begin
-		g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
-		for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
-				g[i] = b[i + 1] ^ b[i];
-		b2g = g;
-	end
+  input [DATA_WIDTH-1:0] b;
+  reg [DATA_WIDTH-1:0] g;
+  integer i;
+  begin
+    g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
+    for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
+        g[i] = b[i + 1] ^ b[i];
+    b2g = g;
+  end
 endfunction
 
 always @(posedge in_clk) begin
-	if (in_resetn == 1'b0) begin
-		cdc_sync_stage0 <= 'h00;
-	end else begin
-		cdc_sync_stage0 <= b2g(in_count);
-	end
+  if (in_resetn == 1'b0) begin
+    cdc_sync_stage0 <= 'h00;
+  end else begin
+    cdc_sync_stage0 <= b2g(in_count);
+  end
 end
 
 always @(posedge out_clk) begin
-	if (out_resetn == 1'b0) begin
-		cdc_sync_stage1 <= 'h00;
-		cdc_sync_stage2 <= 'h00;
-		out_count_m <= 'h00;
-	end else begin
-		cdc_sync_stage1 <= cdc_sync_stage0;
-		cdc_sync_stage2 <= cdc_sync_stage1;
-		out_count_m <= g2b(cdc_sync_stage2);
-	end
+  if (out_resetn == 1'b0) begin
+    cdc_sync_stage1 <= 'h00;
+    cdc_sync_stage2 <= 'h00;
+    out_count_m <= 'h00;
+  end else begin
+    cdc_sync_stage1 <= cdc_sync_stage0;
+    cdc_sync_stage2 <= cdc_sync_stage1;
+    out_count_m <= g2b(cdc_sync_stage2);
+  end
 end
 
 assign out_count = ASYNC_CLK ? out_count_m : in_count;
diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v
index 64099b9e3..bbef0119e 100644
--- a/library/common/up_hdmi_tx.v
+++ b/library/common/up_hdmi_tx.v
@@ -249,7 +249,7 @@ module up_hdmi_tx (
       if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin
         up_clip_max <= up_wdata[23:0];
       end
-	  if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin
+    if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin
         up_clip_min <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
diff --git a/library/cordic_demod/cordic_demod.v b/library/cordic_demod/cordic_demod.v
index bb2e25e41..49b1fd474 100644
--- a/library/cordic_demod/cordic_demod.v
+++ b/library/cordic_demod/cordic_demod.v
@@ -1,14 +1,14 @@
 module cordic_demod (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input s_axis_valid,
-	output s_axis_ready,
-	input [63:0] s_axis_data,
+  input s_axis_valid,
+  output s_axis_ready,
+  input [63:0] s_axis_data,
 
-	output m_axis_valid,
-	input m_axis_ready,
-	output [63:0] m_axis_data
+  output m_axis_valid,
+  input m_axis_ready,
+  output [63:0] m_axis_data
 );
 
 reg [4:0] step_counter;
@@ -34,135 +34,135 @@ localparam STATE_DONE = 4;
 reg [31:0] angle[0:30];
 
 initial begin
-	angle[0] = 32'h20000000;
-	angle[1] = 32'h12e4051e;
-	angle[2] = 32'h09fb385b;
-	angle[3] = 32'h051111d4;
-	angle[4] = 32'h028b0d43;
-	angle[5] = 32'h0145d7e1;
-	angle[6] = 32'h00a2f61e;
-	angle[7] = 32'h00517c55;
-	angle[8] = 32'h0028be53;
-	angle[9] = 32'h00145f2f;
-	angle[10] = 32'h000a2f98;
-	angle[11] = 32'h000517cc;
-	angle[12] = 32'h00028be6;
-	angle[13] = 32'h000145f3;
-	angle[14] = 32'h0000a2fa;
-	angle[15] = 32'h0000517d;
-	angle[16] = 32'h000028be;
-	angle[17] = 32'h0000145f;
-	angle[18] = 32'h00000a30;
-	angle[19] = 32'h00000518;
-	angle[20] = 32'h0000028c;
-	angle[21] = 32'h00000146;
-	angle[22] = 32'h000000a3;
-	angle[23] = 32'h00000051;
-	angle[24] = 32'h00000029;
-	angle[25] = 32'h00000014;
-	angle[26] = 32'h0000000a;
-	angle[27] = 32'h00000005;
-	angle[28] = 32'h00000003;
-	angle[29] = 32'h00000001;
-	angle[30] = 32'h00000001;
+  angle[0] = 32'h20000000;
+  angle[1] = 32'h12e4051e;
+  angle[2] = 32'h09fb385b;
+  angle[3] = 32'h051111d4;
+  angle[4] = 32'h028b0d43;
+  angle[5] = 32'h0145d7e1;
+  angle[6] = 32'h00a2f61e;
+  angle[7] = 32'h00517c55;
+  angle[8] = 32'h0028be53;
+  angle[9] = 32'h00145f2f;
+  angle[10] = 32'h000a2f98;
+  angle[11] = 32'h000517cc;
+  angle[12] = 32'h00028be6;
+  angle[13] = 32'h000145f3;
+  angle[14] = 32'h0000a2fa;
+  angle[15] = 32'h0000517d;
+  angle[16] = 32'h000028be;
+  angle[17] = 32'h0000145f;
+  angle[18] = 32'h00000a30;
+  angle[19] = 32'h00000518;
+  angle[20] = 32'h0000028c;
+  angle[21] = 32'h00000146;
+  angle[22] = 32'h000000a3;
+  angle[23] = 32'h00000051;
+  angle[24] = 32'h00000029;
+  angle[25] = 32'h00000014;
+  angle[26] = 32'h0000000a;
+  angle[27] = 32'h00000005;
+  angle[28] = 32'h00000003;
+  angle[29] = 32'h00000001;
+  angle[30] = 32'h00000001;
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		state <= STATE_IDLE;
-	end else begin
-		case (state)
-		STATE_IDLE: begin
-			if (s_axis_valid == 1'b1) begin
-				state <= STATE_SHIFT_LOAD;
-			end
-		end
-		STATE_SHIFT_LOAD: begin
-			if (step_counter == 'h00) begin
-				state <= STATE_ADD;
-			end else begin
-				state <= STATE_SHIFT;
-			end
-		end
-		STATE_SHIFT: begin
-			if (shift_counter == 'h01) begin
-				state <= STATE_ADD;
-			end
-		end
-		STATE_ADD: begin
-			if (step_counter == 'd30) begin
-				state <= STATE_DONE;
-			end else begin
-				state <= STATE_SHIFT_LOAD;
-			end
-		end
-		STATE_DONE: begin
-			if (m_axis_ready == 1'b1)
-				state <= STATE_IDLE;
-		end
-		endcase
-	end
+  if (resetn == 1'b0) begin
+    state <= STATE_IDLE;
+  end else begin
+    case (state)
+    STATE_IDLE: begin
+      if (s_axis_valid == 1'b1) begin
+        state <= STATE_SHIFT_LOAD;
+      end
+    end
+    STATE_SHIFT_LOAD: begin
+      if (step_counter == 'h00) begin
+        state <= STATE_ADD;
+      end else begin
+        state <= STATE_SHIFT;
+      end
+    end
+    STATE_SHIFT: begin
+      if (shift_counter == 'h01) begin
+        state <= STATE_ADD;
+      end
+    end
+    STATE_ADD: begin
+      if (step_counter == 'd30) begin
+        state <= STATE_DONE;
+      end else begin
+        state <= STATE_SHIFT_LOAD;
+      end
+    end
+    STATE_DONE: begin
+      if (m_axis_ready == 1'b1)
+        state <= STATE_IDLE;
+    end
+    endcase
+  end
 end
 
 always @(posedge clk) begin
-	case(state)
-	STATE_SHIFT_LOAD: begin
-		shift_counter <= step_counter;
-	end
-	STATE_SHIFT: begin
-		shift_counter <= shift_counter - 1'b1;
-	end
-	endcase
+  case(state)
+  STATE_SHIFT_LOAD: begin
+    shift_counter <= step_counter;
+  end
+  STATE_SHIFT: begin
+    shift_counter <= shift_counter - 1'b1;
+  end
+  endcase
 end
 
 always @(posedge clk)
 begin
-	case(state)
-	STATE_IDLE:
-		if (s_axis_valid == 1'b1) begin
-			step_counter <= 'h00;
-			phase <= {1'b0,s_axis_data[61:32]};
-			step_counter <= 'h00;
-			case (s_axis_data[63:62])
-			2'b00: begin
-				i <= {s_axis_data[31],s_axis_data[31:0]};
-				q <= 'h00;
-			end
-			2'b01: begin
-				i <= 'h00;
-				q <= ~{s_axis_data[31],s_axis_data[31:0]};
-			end
-			2'b10: begin
-				i <= ~{s_axis_data[31],s_axis_data[31:0]};
-				q <= 'h00;
-			end
-			2'b11: begin
-				i <= 'h00;
-				q <= {s_axis_data[31],s_axis_data[31:0]};
-			end
-			endcase
-		end
-	STATE_SHIFT_LOAD: begin
-		i_shift <= i;
-		q_shift <= q;
-	end
-	STATE_SHIFT: begin
-		i_shift <= {i_shift[32],i_shift[32:1]};
-		q_shift <= {q_shift[32],q_shift[32:1]};
-	end
-	STATE_ADD: begin
-		if (phase[30] == 1'b0) begin
-			i <= i + q_shift;
-			q <= q - i_shift;
-			phase <= phase - angle[step_counter];
-		end else begin
-			i <= i - q_shift;
-			q <= q + i_shift;
-			phase <= phase + angle[step_counter];
-		end
-		step_counter <= step_counter + 1'b1;
-	end
-	endcase
+  case(state)
+  STATE_IDLE:
+    if (s_axis_valid == 1'b1) begin
+      step_counter <= 'h00;
+      phase <= {1'b0,s_axis_data[61:32]};
+      step_counter <= 'h00;
+      case (s_axis_data[63:62])
+      2'b00: begin
+        i <= {s_axis_data[31],s_axis_data[31:0]};
+        q <= 'h00;
+      end
+      2'b01: begin
+        i <= 'h00;
+        q <= ~{s_axis_data[31],s_axis_data[31:0]};
+      end
+      2'b10: begin
+        i <= ~{s_axis_data[31],s_axis_data[31:0]};
+        q <= 'h00;
+      end
+      2'b11: begin
+        i <= 'h00;
+        q <= {s_axis_data[31],s_axis_data[31:0]};
+      end
+      endcase
+    end
+  STATE_SHIFT_LOAD: begin
+    i_shift <= i;
+    q_shift <= q;
+  end
+  STATE_SHIFT: begin
+    i_shift <= {i_shift[32],i_shift[32:1]};
+    q_shift <= {q_shift[32],q_shift[32:1]};
+  end
+  STATE_ADD: begin
+    if (phase[30] == 1'b0) begin
+      i <= i + q_shift;
+      q <= q - i_shift;
+      phase <= phase - angle[step_counter];
+    end else begin
+      i <= i - q_shift;
+      q <= q + i_shift;
+      phase <= phase + angle[step_counter];
+    end
+    step_counter <= step_counter + 1'b1;
+  end
+  endcase
 end
 
 endmodule
diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
index bd8cc6c48..52bdf0ca5 100644
--- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
+++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
@@ -1,58 +1,58 @@
 
 
 module spi_engine_interconnect (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	output m_cmd_valid,
-	input m_cmd_ready,
-	output [15:0] m_cmd_data,
+  output m_cmd_valid,
+  input m_cmd_ready,
+  output [15:0] m_cmd_data,
 
-	output m_sdo_valid,
-	input m_sdo_ready,
-	output [(DATA_WIDTH-1):0] m_sdo_data,
+  output m_sdo_valid,
+  input m_sdo_ready,
+  output [(DATA_WIDTH-1):0] m_sdo_data,
 
-	input m_sdi_valid,
-	output m_sdi_ready,
-	input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
+  input m_sdi_valid,
+  output m_sdi_ready,
+  input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
 
-	input m_sync_valid,
-	output m_sync_ready,
-	input [7:0] m_sync,
+  input m_sync_valid,
+  output m_sync_ready,
+  input [7:0] m_sync,
 
 
-	input s0_cmd_valid,
-	output s0_cmd_ready,
-	input [15:0] s0_cmd_data,
+  input s0_cmd_valid,
+  output s0_cmd_ready,
+  input [15:0] s0_cmd_data,
 
-	input s0_sdo_valid,
-	output s0_sdo_ready,
-	input [(DATA_WIDTH-1):0] s0_sdo_data,
+  input s0_sdo_valid,
+  output s0_sdo_ready,
+  input [(DATA_WIDTH-1):0] s0_sdo_data,
 
-	output s0_sdi_valid,
-	input s0_sdi_ready,
-	output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
+  output s0_sdi_valid,
+  input s0_sdi_ready,
+  output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
 
-	output s0_sync_valid,
-	input s0_sync_ready,
-	output [7:0] s0_sync,
+  output s0_sync_valid,
+  input s0_sync_ready,
+  output [7:0] s0_sync,
 
 
-	input s1_cmd_valid,
-	output s1_cmd_ready,
-	input [15:0] s1_cmd_data,
+  input s1_cmd_valid,
+  output s1_cmd_ready,
+  input [15:0] s1_cmd_data,
 
-	input s1_sdo_valid,
-	output s1_sdo_ready,
-	input [(DATA_WIDTH-1):0] s1_sdo_data,
+  input s1_sdo_valid,
+  output s1_sdo_ready,
+  input [(DATA_WIDTH-1):0] s1_sdo_data,
 
-	output s1_sdi_valid,
-	input s1_sdi_ready,
-	output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
+  output s1_sdi_valid,
+  input s1_sdi_ready,
+  output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
 
-	output s1_sync_valid,
-	input s1_sync_ready,
-	output [7:0] s1_sync
+  output s1_sync_valid,
+  input s1_sync_ready,
+  output [7:0] s1_sync
 );
 
 parameter DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
@@ -87,24 +87,24 @@ assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
 assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
 
 always @(posedge clk) begin
-	if (idle == 1'b1) begin
-		if (s0_cmd_valid)
-			s_active <= 1'b0;
-		else if (s1_cmd_valid)
-			s_active <= 1'b1;
-	end
+  if (idle == 1'b1) begin
+    if (s0_cmd_valid)
+      s_active <= 1'b0;
+    else if (s1_cmd_valid)
+      s_active <= 1'b1;
+  end
 end
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		idle = 1'b1;
-	end else begin
-		if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
-			idle <= 1'b1;
-		end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
-			idle <= 1'b0;
-		end
-	end
+  if (resetn == 1'b0) begin
+    idle = 1'b1;
+  end else begin
+    if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
+      idle <= 1'b1;
+    end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
+      idle <= 1'b0;
+    end
+  end
 end
 
 endmodule
diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
index 80563a17f..37242d137 100644
--- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v
+++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
@@ -1,41 +1,41 @@
 
 module spi_engine_offload (
-	input ctrl_clk,
+  input ctrl_clk,
 
-	input ctrl_cmd_wr_en,
-	input [15:0] ctrl_cmd_wr_data,
+  input ctrl_cmd_wr_en,
+  input [15:0] ctrl_cmd_wr_data,
 
-	input ctrl_sdo_wr_en,
-	input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
+  input ctrl_sdo_wr_en,
+  input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
 
-	input ctrl_enable,
-	output ctrl_enabled,
-	input ctrl_mem_reset,
+  input ctrl_enable,
+  output ctrl_enabled,
+  input ctrl_mem_reset,
 
-	input spi_clk,
-	input spi_resetn,
+  input spi_clk,
+  input spi_resetn,
 
-	input trigger,
+  input trigger,
 
-	output cmd_valid,
-	input cmd_ready,
-	output [15:0] cmd,
+  output cmd_valid,
+  input cmd_ready,
+  output [15:0] cmd,
 
-	output sdo_data_valid,
-	input sdo_data_ready,
-	output [(DATA_WIDTH-1):0] sdo_data,
+  output sdo_data_valid,
+  input sdo_data_ready,
+  output [(DATA_WIDTH-1):0] sdo_data,
 
-	input sdi_data_valid,
-	output sdi_data_ready,
-	input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
+  input sdi_data_valid,
+  output sdi_data_ready,
+  input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
 
-	input sync_valid,
-	output sync_ready,
-	input [7:0] sync_data,
+  input sync_valid,
+  output sync_ready,
+  input [7:0] sync_data,
 
-	output offload_sdi_valid,
-	input offload_sdi_ready,
-	output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
+  output offload_sdi_valid,
+  input offload_sdi_ready,
+  output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
 );
 
 parameter ASYNC_SPI_CLK = 0;
@@ -84,17 +84,17 @@ wire ctrl_is_enabled;
 reg spi_enabled = 1'b0;
 
 always @(posedge ctrl_clk) begin
-	if (ctrl_enable == 1'b1) begin
-		ctrl_do_enable <= 1'b1;
-	end else if (ctrl_is_enabled == 1'b1) begin
-		ctrl_do_enable <= 1'b0;
-	end
+  if (ctrl_enable == 1'b1) begin
+    ctrl_do_enable <= 1'b1;
+  end else if (ctrl_is_enabled == 1'b1) begin
+    ctrl_do_enable <= 1'b0;
+  end
 end
 
 assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
 
 always @(posedge spi_clk) begin
-	spi_enabled <= spi_enable | spi_active;
+  spi_enabled <= spi_enable | spi_active;
 end
 
 sync_bits # (
@@ -125,56 +125,56 @@ end endgenerate
 assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
 
 always @(posedge spi_clk) begin
-	if (spi_resetn == 1'b0) begin
-		spi_active <= 1'b0;
-	end else begin
-		if (spi_active == 1'b0) begin
-			if (trigger == 1'b1 && spi_enable == 1'b1)
-				spi_active <= 1'b1;
-		end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
-			spi_active <= 1'b0;
-		end
-	end
+  if (spi_resetn == 1'b0) begin
+    spi_active <= 1'b0;
+  end else begin
+    if (spi_active == 1'b0) begin
+      if (trigger == 1'b1 && spi_enable == 1'b1)
+        spi_active <= 1'b1;
+    end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
+      spi_active <= 1'b0;
+    end
+  end
 end
 
 always @(posedge spi_clk) begin
-	if (cmd_valid == 1'b0) begin
-		spi_cmd_rd_addr <= 'h00;
-	end else if (cmd_ready == 1'b1) begin
-		spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
-	end
+  if (cmd_valid == 1'b0) begin
+    spi_cmd_rd_addr <= 'h00;
+  end else if (cmd_ready == 1'b1) begin
+    spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
+  end
 end
 
 always @(posedge spi_clk) begin
-	if (spi_active == 1'b0) begin
-		spi_sdo_rd_addr <= 'h00;
-	end else if (sdo_data_ready == 1'b1) begin
-		spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
-	end
+  if (spi_active == 1'b0) begin
+    spi_sdo_rd_addr <= 'h00;
+  end else if (sdo_data_ready == 1'b1) begin
+    spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
+  end
 end
 
 always @(posedge ctrl_clk) begin
-	if (ctrl_mem_reset == 1'b1)
-		ctrl_cmd_wr_addr <= 'h00;
-	else if (ctrl_cmd_wr_en == 1'b1)
-		ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
+  if (ctrl_mem_reset == 1'b1)
+    ctrl_cmd_wr_addr <= 'h00;
+  else if (ctrl_cmd_wr_en == 1'b1)
+    ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
 end
 
 always @(posedge ctrl_clk) begin
-	if (ctrl_cmd_wr_en == 1'b1)
-		cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
+  if (ctrl_cmd_wr_en == 1'b1)
+    cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
 end
 
 always @(posedge ctrl_clk) begin
-	if (ctrl_mem_reset == 1'b1)
-		ctrl_sdo_wr_addr <= 'h00;
-	else if (ctrl_sdo_wr_en == 1'b1)
-		ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
+  if (ctrl_mem_reset == 1'b1)
+    ctrl_sdo_wr_addr <= 'h00;
+  else if (ctrl_sdo_wr_en == 1'b1)
+    ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
 end
 
 always @(posedge ctrl_clk) begin
-	if (ctrl_sdo_wr_en == 1'b1)
-		sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
+  if (ctrl_sdo_wr_en == 1'b1)
+    sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
 end
 
 endmodule
diff --git a/library/util_axis_fifo/address_gray.v b/library/util_axis_fifo/address_gray.v
index a75d3368d..5c912179d 100644
--- a/library/util_axis_fifo/address_gray.v
+++ b/library/util_axis_fifo/address_gray.v
@@ -37,19 +37,19 @@
 // ***************************************************************************
 
 module fifo_address_gray (
-	input m_axis_aclk,
-	input m_axis_aresetn,
-	input m_axis_ready,
-	output reg m_axis_valid,
-	output reg [ADDRESS_WIDTH:0] m_axis_level,
+  input m_axis_aclk,
+  input m_axis_aresetn,
+  input m_axis_ready,
+  output reg m_axis_valid,
+  output reg [ADDRESS_WIDTH:0] m_axis_level,
 
-	input s_axis_aclk,
-	input s_axis_aresetn,
-	output reg s_axis_ready,
-	input s_axis_valid,
-	output reg s_axis_empty,
-	output [ADDRESS_WIDTH-1:0] s_axis_waddr,
-	output reg [ADDRESS_WIDTH:0] s_axis_room
+  input s_axis_aclk,
+  input s_axis_aresetn,
+  output reg s_axis_ready,
+  input s_axis_valid,
+  output reg s_axis_empty,
+  output [ADDRESS_WIDTH-1:0] s_axis_waddr,
+  output reg [ADDRESS_WIDTH:0] s_axis_room
 );
 
 parameter ADDRESS_WIDTH = 4;
@@ -72,84 +72,84 @@ assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
 
 always @(*)
 begin
-	if (s_axis_ready && s_axis_valid)
-		_s_axis_waddr_next <= _s_axis_waddr + 1;
-	else
-		_s_axis_waddr_next <= _s_axis_waddr;
+  if (s_axis_ready && s_axis_valid)
+    _s_axis_waddr_next <= _s_axis_waddr + 1;
+  else
+    _s_axis_waddr_next <= _s_axis_waddr;
 end
 
 assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1];
 
 always @(posedge s_axis_aclk)
 begin
-	if (s_axis_aresetn == 1'b0) begin
-		_s_axis_waddr <= 'h00;
-		s_axis_waddr_gray <= 'h00;
-	end else begin
-		_s_axis_waddr <= _s_axis_waddr_next;
-		s_axis_waddr_gray <= s_axis_waddr_gray_next;
-	end
+  if (s_axis_aresetn == 1'b0) begin
+    _s_axis_waddr <= 'h00;
+    s_axis_waddr_gray <= 'h00;
+  end else begin
+    _s_axis_waddr <= _s_axis_waddr_next;
+    s_axis_waddr_gray <= s_axis_waddr_gray_next;
+  end
 end
 
 always @(*)
 begin
-	if (m_axis_ready && m_axis_valid)
-		_m_axis_raddr_next <= _m_axis_raddr + 1;
-	else
-		_m_axis_raddr_next <= _m_axis_raddr;
+  if (m_axis_ready && m_axis_valid)
+    _m_axis_raddr_next <= _m_axis_raddr + 1;
+  else
+    _m_axis_raddr_next <= _m_axis_raddr;
 end
 
 assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1];
 
 always @(posedge m_axis_aclk)
 begin
-	if (m_axis_aresetn == 1'b0) begin
-		_m_axis_raddr <= 'h00;
-		m_axis_raddr_gray <= 'h00;
-	end else begin
-		_m_axis_raddr <= _m_axis_raddr_next;
-		m_axis_raddr_gray <= m_axis_raddr_gray_next;
-	end
+  if (m_axis_aresetn == 1'b0) begin
+    _m_axis_raddr <= 'h00;
+    m_axis_raddr_gray <= 'h00;
+  end else begin
+    _m_axis_raddr <= _m_axis_raddr_next;
+    m_axis_raddr_gray <= m_axis_raddr_gray_next;
+  end
 end
 
 sync_bits #(
-	.NUM_OF_BITS(ADDRESS_WIDTH + 1)
+  .NUM_OF_BITS(ADDRESS_WIDTH + 1)
 ) i_waddr_sync (
-	.out_clk(m_axis_aclk),
-	.out_resetn(m_axis_aresetn),
-	.in(s_axis_waddr_gray),
-	.out(m_axis_waddr_gray)
+  .out_clk(m_axis_aclk),
+  .out_resetn(m_axis_aresetn),
+  .in(s_axis_waddr_gray),
+  .out(m_axis_waddr_gray)
 );
 
 sync_bits #(
-	.NUM_OF_BITS(ADDRESS_WIDTH + 1)
+  .NUM_OF_BITS(ADDRESS_WIDTH + 1)
 ) i_raddr_sync (
-	.out_clk(s_axis_aclk),
-	.out_resetn(s_axis_aresetn),
-	.in(m_axis_raddr_gray),
-	.out(s_axis_raddr_gray)
+  .out_clk(s_axis_aclk),
+  .out_resetn(s_axis_aresetn),
+  .in(m_axis_raddr_gray),
+  .out(s_axis_raddr_gray)
 );
 
 always @(posedge s_axis_aclk)
 begin
-	if (s_axis_aresetn == 1'b0) begin
-		s_axis_ready <= 1'b1;
-		s_axis_empty <= 1'b1;
-	end else begin
-		s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] ||
-			s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] ||
-			s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]);
-		s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
-	end
+  if (s_axis_aresetn == 1'b0) begin
+    s_axis_ready <= 1'b1;
+    s_axis_empty <= 1'b1;
+  end else begin
+    s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] ||
+      s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] ||
+      s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]);
+    s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
+  end
 end
 
 always @(posedge m_axis_aclk)
 begin
-	if (s_axis_aresetn == 1'b0)
-		m_axis_valid <= 1'b0;
-	else begin
-		m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
-	end
+  if (s_axis_aresetn == 1'b0)
+    m_axis_valid <= 1'b0;
+  else begin
+    m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
+  end
 end
 
 endmodule
diff --git a/library/util_axis_fifo/address_gray_pipelined.v b/library/util_axis_fifo/address_gray_pipelined.v
index 5541091c0..ed7055b39 100644
--- a/library/util_axis_fifo/address_gray_pipelined.v
+++ b/library/util_axis_fifo/address_gray_pipelined.v
@@ -37,20 +37,20 @@
 // ***************************************************************************
 
 module fifo_address_gray_pipelined (
-	input m_axis_aclk,
-	input m_axis_aresetn,
-	input m_axis_ready,
-	output reg m_axis_valid,
-	output [ADDRESS_WIDTH-1:0] m_axis_raddr,
-	output reg [ADDRESS_WIDTH:0] m_axis_level,
+  input m_axis_aclk,
+  input m_axis_aresetn,
+  input m_axis_ready,
+  output reg m_axis_valid,
+  output [ADDRESS_WIDTH-1:0] m_axis_raddr,
+  output reg [ADDRESS_WIDTH:0] m_axis_level,
 
-	input s_axis_aclk,
-	input s_axis_aresetn,
-	output reg s_axis_ready,
-	input s_axis_valid,
-	output reg s_axis_empty,
-	output [ADDRESS_WIDTH-1:0] s_axis_waddr,
-	output reg [ADDRESS_WIDTH:0] s_axis_room
+  input s_axis_aclk,
+  input s_axis_aresetn,
+  output reg s_axis_ready,
+  input s_axis_valid,
+  output reg s_axis_empty,
+  output [ADDRESS_WIDTH-1:0] s_axis_waddr,
+  output reg [ADDRESS_WIDTH:0] s_axis_room
 );
 
 parameter ADDRESS_WIDTH = 4;
@@ -68,83 +68,83 @@ assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
 
 always @(*)
 begin
-	if (s_axis_ready && s_axis_valid)
-		_s_axis_waddr_next <= _s_axis_waddr + 1;
-	else
-		_s_axis_waddr_next <= _s_axis_waddr;
+  if (s_axis_ready && s_axis_valid)
+    _s_axis_waddr_next <= _s_axis_waddr + 1;
+  else
+    _s_axis_waddr_next <= _s_axis_waddr;
 end
 
 always @(posedge s_axis_aclk)
 begin
-	if (s_axis_aresetn == 1'b0) begin
-		_s_axis_waddr <= 'h00;
-	end else begin
-		_s_axis_waddr <= _s_axis_waddr_next;
-	end
+  if (s_axis_aresetn == 1'b0) begin
+    _s_axis_waddr <= 'h00;
+  end else begin
+    _s_axis_waddr <= _s_axis_waddr_next;
+  end
 end
 
 always @(*)
 begin
-	if (m_axis_ready && m_axis_valid)
-		_m_axis_raddr_next <= _m_axis_raddr + 1;
-	else
-		_m_axis_raddr_next <= _m_axis_raddr;
+  if (m_axis_ready && m_axis_valid)
+    _m_axis_raddr_next <= _m_axis_raddr + 1;
+  else
+    _m_axis_raddr_next <= _m_axis_raddr;
 end
 
 always @(posedge m_axis_aclk)
 begin
-	if (m_axis_aresetn == 1'b0) begin
-		_m_axis_raddr <= 'h00;
-	end else begin
-		_m_axis_raddr <= _m_axis_raddr_next;
-	end
+  if (m_axis_aresetn == 1'b0) begin
+    _m_axis_raddr <= 'h00;
+  end else begin
+    _m_axis_raddr <= _m_axis_raddr_next;
+  end
 end
 
 sync_gray #(
-	.DATA_WIDTH(ADDRESS_WIDTH + 1)
+  .DATA_WIDTH(ADDRESS_WIDTH + 1)
 ) i_waddr_sync (
-	.in_clk(s_axis_aclk),
-	.in_resetn(s_axis_aresetn),
-	.out_clk(m_axis_aclk),
-	.out_resetn(m_axis_aresetn),
-	.in_count(_s_axis_waddr),
-	.out_count(_m_axis_waddr)
+  .in_clk(s_axis_aclk),
+  .in_resetn(s_axis_aresetn),
+  .out_clk(m_axis_aclk),
+  .out_resetn(m_axis_aresetn),
+  .in_count(_s_axis_waddr),
+  .out_count(_m_axis_waddr)
 );
 
 sync_gray #(
-	.DATA_WIDTH(ADDRESS_WIDTH + 1)
+  .DATA_WIDTH(ADDRESS_WIDTH + 1)
 ) i_raddr_sync (
-	.in_clk(m_axis_aclk),
-	.in_resetn(m_axis_aresetn),
-	.out_clk(s_axis_aclk),
-	.out_resetn(s_axis_aresetn),
-	.in_count(_m_axis_raddr),
-	.out_count(_s_axis_raddr)
+  .in_clk(m_axis_aclk),
+  .in_resetn(m_axis_aresetn),
+  .out_clk(s_axis_aclk),
+  .out_resetn(s_axis_aresetn),
+  .in_count(_m_axis_raddr),
+  .out_count(_s_axis_raddr)
 );
 
 always @(posedge s_axis_aclk)
 begin
-	if (s_axis_aresetn == 1'b0) begin
-		s_axis_ready <= 1'b1;
-		s_axis_empty <= 1'b1;
-		s_axis_room <= 2**ADDRESS_WIDTH;
-	end else begin
-		s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
-			_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
-		s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
-		s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH;
-	end
+  if (s_axis_aresetn == 1'b0) begin
+    s_axis_ready <= 1'b1;
+    s_axis_empty <= 1'b1;
+    s_axis_room <= 2**ADDRESS_WIDTH;
+  end else begin
+    s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
+      _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
+    s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
+    s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH;
+  end
 end
 
 always @(posedge m_axis_aclk)
 begin
-	if (m_axis_aresetn == 1'b0) begin
-		m_axis_valid <= 1'b0;
-		m_axis_level <= 'h00;
-	end else begin
-		m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
-		m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
-	end
+  if (m_axis_aresetn == 1'b0) begin
+    m_axis_valid <= 1'b0;
+    m_axis_level <= 'h00;
+  end else begin
+    m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
+    m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
+  end
 end
 
 endmodule
diff --git a/library/util_axis_fifo/address_sync.v b/library/util_axis_fifo/address_sync.v
index 7b02b6e13..6c94dba9c 100644
--- a/library/util_axis_fifo/address_sync.v
+++ b/library/util_axis_fifo/address_sync.v
@@ -37,19 +37,19 @@
 // ***************************************************************************
 
 module fifo_address_sync (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input m_axis_ready,
-	output reg m_axis_valid,
-	output reg  [ADDRESS_WIDTH-1:0] m_axis_raddr,
-	output [ADDRESS_WIDTH:0] m_axis_level,
+  input m_axis_ready,
+  output reg m_axis_valid,
+  output reg  [ADDRESS_WIDTH-1:0] m_axis_raddr,
+  output [ADDRESS_WIDTH:0] m_axis_level,
 
-	output reg s_axis_ready,
-	input s_axis_valid,
-	output reg s_axis_empty,
-	output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
-	output [ADDRESS_WIDTH:0] s_axis_room
+  output reg s_axis_ready,
+  input s_axis_valid,
+  output reg s_axis_empty,
+  output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
+  output [ADDRESS_WIDTH:0] s_axis_room
 );
 
 parameter ADDRESS_WIDTH = 4;
@@ -66,42 +66,42 @@ wire write = s_axis_ready & s_axis_valid;
 
 always @(posedge clk)
 begin
-	if (resetn == 1'b0) begin
-		s_axis_waddr <= 'h00;
-		m_axis_raddr <= 'h00;
-	end else begin
-		if (write)
-			s_axis_waddr <= s_axis_waddr + 1'b1;
-		if (read)
-			m_axis_raddr <= m_axis_raddr + 1'b1;
-	end
+  if (resetn == 1'b0) begin
+    s_axis_waddr <= 'h00;
+    m_axis_raddr <= 'h00;
+  end else begin
+    if (write)
+      s_axis_waddr <= s_axis_waddr + 1'b1;
+    if (read)
+      m_axis_raddr <= m_axis_raddr + 1'b1;
+  end
 end
 
 always @(*)
 begin
-	if (read & ~write)
-		level_next <= level - 1'b1;
-	else if (~read & write)
-		level_next <= level + 1'b1;
-	else
-		level_next <= level;
+  if (read & ~write)
+    level_next <= level - 1'b1;
+  else if (~read & write)
+    level_next <= level + 1'b1;
+  else
+    level_next <= level;
 end
 
 always @(posedge clk)
 begin
-	if (resetn == 1'b0) begin
-		m_axis_valid <= 1'b0;
-		s_axis_ready <= 1'b0;
-		level <= 'h00;
-		room <= 2**ADDRESS_WIDTH;
-		s_axis_empty <= 'h00;
-	end else begin
-		level <= level_next;
-		room <= 2**ADDRESS_WIDTH - level_next;
-		m_axis_valid <= level_next != 0;
-		s_axis_ready <= level_next != 2**ADDRESS_WIDTH;
-		s_axis_empty <= level_next == 0;
-	end
+  if (resetn == 1'b0) begin
+    m_axis_valid <= 1'b0;
+    s_axis_ready <= 1'b0;
+    level <= 'h00;
+    room <= 2**ADDRESS_WIDTH;
+    s_axis_empty <= 'h00;
+  end else begin
+    level <= level_next;
+    room <= 2**ADDRESS_WIDTH - level_next;
+    m_axis_valid <= level_next != 0;
+    s_axis_ready <= level_next != 2**ADDRESS_WIDTH;
+    s_axis_empty <= level_next == 0;
+  end
 end
 
 endmodule
diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v
index 8b30190d8..a590d6b21 100644
--- a/library/util_axis_fifo/util_axis_fifo.v
+++ b/library/util_axis_fifo/util_axis_fifo.v
@@ -37,20 +37,20 @@
 // ***************************************************************************
 
 module util_axis_fifo (
-	input m_axis_aclk,
-	input m_axis_aresetn,
-	input m_axis_ready,
-	output m_axis_valid,
-	output [DATA_WIDTH-1:0] m_axis_data,
-	output [ADDRESS_WIDTH:0] m_axis_level,
+  input m_axis_aclk,
+  input m_axis_aresetn,
+  input m_axis_ready,
+  output m_axis_valid,
+  output [DATA_WIDTH-1:0] m_axis_data,
+  output [ADDRESS_WIDTH:0] m_axis_level,
 
-	input s_axis_aclk,
-	input s_axis_aresetn,
-	output s_axis_ready,
-	input s_axis_valid,
-	input [DATA_WIDTH-1:0] s_axis_data,
-	output s_axis_empty,
-	output [ADDRESS_WIDTH:0] s_axis_room
+  input s_axis_aclk,
+  input s_axis_aresetn,
+  output s_axis_ready,
+  input s_axis_valid,
+  input [DATA_WIDTH-1:0] s_axis_data,
+  output s_axis_empty,
+  output [ADDRESS_WIDTH:0] s_axis_room
 );
 
 parameter DATA_WIDTH = 64;
@@ -68,23 +68,23 @@ wire m_axis_waddr;
 wire s_axis_raddr;
 
 sync_bits #(
-	.NUM_OF_BITS(1),
-	.ASYNC_CLK(ASYNC_CLK)
+  .NUM_OF_BITS(1),
+  .ASYNC_CLK(ASYNC_CLK)
 ) i_waddr_sync (
-	.out_clk(m_axis_aclk),
-	.out_resetn(m_axis_aresetn),
-	.in(s_axis_waddr),
-	.out(m_axis_waddr)
+  .out_clk(m_axis_aclk),
+  .out_resetn(m_axis_aresetn),
+  .in(s_axis_waddr),
+  .out(m_axis_waddr)
 );
 
 sync_bits #(
-	.NUM_OF_BITS(1),
-	.ASYNC_CLK(ASYNC_CLK)
+  .NUM_OF_BITS(1),
+  .ASYNC_CLK(ASYNC_CLK)
 ) i_raddr_sync (
-	.out_clk(s_axis_aclk),
-	.out_resetn(s_axis_aresetn),
-	.in(m_axis_raddr),
-	.out(s_axis_raddr)
+  .out_clk(s_axis_aclk),
+  .out_resetn(s_axis_aresetn),
+  .in(m_axis_raddr),
+  .out(s_axis_raddr)
 );
 
 assign m_axis_valid = m_axis_raddr != m_axis_waddr;
@@ -94,27 +94,27 @@ assign s_axis_empty = s_axis_ready;
 assign s_axis_room = s_axis_ready;
 
 always @(posedge s_axis_aclk) begin
-	if (s_axis_ready)
-		cdc_sync_fifo_ram <= s_axis_data;
+  if (s_axis_ready)
+    cdc_sync_fifo_ram <= s_axis_data;
 end
 
 always @(posedge s_axis_aclk) begin
-	if (s_axis_aresetn == 1'b0) begin
-		s_axis_waddr <= 1'b0;
-	end else begin
-		if (s_axis_ready & s_axis_valid) begin
-			s_axis_waddr <= s_axis_waddr + 1'b1;
-		end
-	end
+  if (s_axis_aresetn == 1'b0) begin
+    s_axis_waddr <= 1'b0;
+  end else begin
+    if (s_axis_ready & s_axis_valid) begin
+      s_axis_waddr <= s_axis_waddr + 1'b1;
+    end
+  end
 end
 
 always @(posedge m_axis_aclk) begin
-	if (m_axis_aresetn == 1'b0) begin
-		m_axis_raddr <= 1'b0;
-	end else begin
-		if (m_axis_valid & m_axis_ready)
-			m_axis_raddr <= m_axis_raddr + 1'b1;
-	end
+  if (m_axis_aresetn == 1'b0) begin
+    m_axis_raddr <= 1'b0;
+  end else begin
+    if (m_axis_valid & m_axis_ready)
+      m_axis_raddr <= m_axis_raddr + 1'b1;
+  end
 end
 
 assign m_axis_data = cdc_sync_fifo_ram;
@@ -131,48 +131,48 @@ wire _m_axis_valid;
 if (ASYNC_CLK == 1) begin
 
 fifo_address_gray_pipelined #(
-	.ADDRESS_WIDTH(ADDRESS_WIDTH)
+  .ADDRESS_WIDTH(ADDRESS_WIDTH)
 ) i_address_gray (
-	.m_axis_aclk(m_axis_aclk),
-	.m_axis_aresetn(m_axis_aresetn),
-	.m_axis_ready(_m_axis_ready),
-	.m_axis_valid(_m_axis_valid),
-	.m_axis_raddr(m_axis_raddr),
-	.m_axis_level(m_axis_level),
+  .m_axis_aclk(m_axis_aclk),
+  .m_axis_aresetn(m_axis_aresetn),
+  .m_axis_ready(_m_axis_ready),
+  .m_axis_valid(_m_axis_valid),
+  .m_axis_raddr(m_axis_raddr),
+  .m_axis_level(m_axis_level),
 
-	.s_axis_aclk(s_axis_aclk),
-	.s_axis_aresetn(s_axis_aresetn),
-	.s_axis_ready(s_axis_ready),
-	.s_axis_valid(s_axis_valid),
-	.s_axis_empty(s_axis_empty),
-	.s_axis_waddr(s_axis_waddr),
-	.s_axis_room(s_axis_room)
+  .s_axis_aclk(s_axis_aclk),
+  .s_axis_aresetn(s_axis_aresetn),
+  .s_axis_ready(s_axis_ready),
+  .s_axis_valid(s_axis_valid),
+  .s_axis_empty(s_axis_empty),
+  .s_axis_waddr(s_axis_waddr),
+  .s_axis_room(s_axis_room)
 );
 
 end else begin
 
 fifo_address_sync #(
-	.ADDRESS_WIDTH(ADDRESS_WIDTH)
+  .ADDRESS_WIDTH(ADDRESS_WIDTH)
 ) i_address_sync (
-	.clk(m_axis_aclk),
-	.resetn(m_axis_aresetn),
-	.m_axis_ready(_m_axis_ready),
-	.m_axis_valid(_m_axis_valid),
-	.m_axis_raddr(m_axis_raddr),
-	.m_axis_level(m_axis_level),
+  .clk(m_axis_aclk),
+  .resetn(m_axis_aresetn),
+  .m_axis_ready(_m_axis_ready),
+  .m_axis_valid(_m_axis_valid),
+  .m_axis_raddr(m_axis_raddr),
+  .m_axis_level(m_axis_level),
 
-	.s_axis_ready(s_axis_ready),
-	.s_axis_valid(s_axis_valid),
-	.s_axis_empty(s_axis_empty),
-	.s_axis_waddr(s_axis_waddr),
-	.s_axis_room(s_axis_room)
+  .s_axis_ready(s_axis_ready),
+  .s_axis_valid(s_axis_valid),
+  .s_axis_empty(s_axis_empty),
+  .s_axis_waddr(s_axis_waddr),
+  .s_axis_room(s_axis_room)
 );
 
 end
 
 always @(posedge s_axis_aclk) begin
-	if (s_axis_ready)
-		ram[s_axis_waddr] <= s_axis_data;
+  if (s_axis_ready)
+    ram[s_axis_waddr] <= s_axis_data;
 end
 
 if (S_AXIS_REGISTERED == 1) begin
@@ -181,19 +181,19 @@ reg [DATA_WIDTH-1:0] data;
 reg valid;
 
 always @(posedge m_axis_aclk) begin
-	if (m_axis_aresetn == 1'b0) begin
-		valid <= 1'b0;
-	end else begin
-		if (_m_axis_valid)
-			valid <= 1'b1;
-		else if (m_axis_ready)
-			valid <= 1'b0;
-	end
+  if (m_axis_aresetn == 1'b0) begin
+    valid <= 1'b0;
+  end else begin
+    if (_m_axis_valid)
+      valid <= 1'b1;
+    else if (m_axis_ready)
+      valid <= 1'b0;
+  end
 end
 
 always @(posedge m_axis_aclk) begin
-	if (~valid || m_axis_ready)
-		data <= ram[m_axis_raddr];
+  if (~valid || m_axis_ready)
+    data <= ram[m_axis_raddr];
 end
 
 assign _m_axis_ready = ~valid || m_axis_ready;
diff --git a/library/util_axis_resize/util_axis_resize.v b/library/util_axis_resize/util_axis_resize.v
index 13a6e5634..b7694d7bf 100644
--- a/library/util_axis_resize/util_axis_resize.v
+++ b/library/util_axis_resize/util_axis_resize.v
@@ -37,16 +37,16 @@
 // ***************************************************************************
 
 module util_axis_resize (
-	input                       clk,
-	input                       resetn,
+  input                       clk,
+  input                       resetn,
 
-	input                       s_valid,
-	output                      s_ready,
-	input [SLAVE_DATA_WIDTH-1:0]  s_data,
+  input                       s_valid,
+  output                      s_ready,
+  input [SLAVE_DATA_WIDTH-1:0]  s_data,
 
-	output                      m_valid,
-	input                       m_ready,
-	output [MASTER_DATA_WIDTH-1:0] m_data
+  output                      m_valid,
+  input                       m_ready,
+  output [MASTER_DATA_WIDTH-1:0] m_data
 );
 
 parameter MASTER_DATA_WIDTH = 64;
@@ -69,32 +69,32 @@ reg valid;
 
 always @(posedge clk)
 begin
-	if (resetn == 1'b0) begin
-		count <= RATIO - 1;
-		valid <= 1'b0;
-	end else begin
-		if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
-			valid <= 1'b1;
-		else if (m_ready == 1'b1)
-			valid <= 1'b0;
+  if (resetn == 1'b0) begin
+    count <= RATIO - 1;
+    valid <= 1'b0;
+  end else begin
+    if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
+      valid <= 1'b1;
+    else if (m_ready == 1'b1)
+      valid <= 1'b0;
 
-		if (s_ready == 1'b1 && s_valid == 1'b1) begin
-			if (count == 'h00)
-				count <= RATIO - 1;
-			else
-				count <= count - 1'b1;
-		end
-	end
+    if (s_ready == 1'b1 && s_valid == 1'b1) begin
+      if (count == 'h00)
+        count <= RATIO - 1;
+      else
+        count <= count - 1'b1;
+    end
+  end
 end
 
 always @(posedge clk)
 begin
-	if (s_ready == 1'b1 && s_valid == 1'b1)
-		if (BIG_ENDIAN == 1) begin
-			data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data};
-		end else begin
-			data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]};
-		end
+  if (s_ready == 1'b1 && s_valid == 1'b1)
+    if (BIG_ENDIAN == 1) begin
+      data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data};
+    end else begin
+      data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]};
+    end
 end
 
 assign s_ready = ~valid || m_ready;
@@ -111,42 +111,42 @@ reg valid;
 
 always @(posedge clk)
 begin
-	if (resetn == 1'b0) begin
-		count <= RATIO - 1;
-		valid <= 1'b0;
-	end else begin
-		if (s_valid == 1'b1 && s_ready == 1'b1)
-			valid <= 1'b1;
-		else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
-			valid <= 1'b0;
+  if (resetn == 1'b0) begin
+    count <= RATIO - 1;
+    valid <= 1'b0;
+  end else begin
+    if (s_valid == 1'b1 && s_ready == 1'b1)
+      valid <= 1'b1;
+    else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
+      valid <= 1'b0;
 
-		if (m_ready == 1'b1 && m_valid == 1'b1) begin
-			if (count == 'h00)
-				count <= RATIO - 1;
-			else
-				count <= count - 1'b1;
-		end
-	end
+    if (m_ready == 1'b1 && m_valid == 1'b1) begin
+      if (count == 'h00)
+        count <= RATIO - 1;
+      else
+        count <= count - 1'b1;
+    end
+  end
 end
 
 always @(posedge clk)
 begin
-	if (s_ready == 1'b1 && s_valid == 1'b1) begin
-		data <= s_data;
-	end else if (m_ready == 1'b1 && m_valid == 1'b1) begin
-		if (BIG_ENDIAN == 1) begin
-			data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0];
-		end else begin
-			data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH];
-		end
-	end
+  if (s_ready == 1'b1 && s_valid == 1'b1) begin
+    data <= s_data;
+  end else if (m_ready == 1'b1 && m_valid == 1'b1) begin
+    if (BIG_ENDIAN == 1) begin
+      data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0];
+    end else begin
+      data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH];
+    end
+  end
 end
 
 assign s_ready = ~valid || (m_ready && count == 'h0);
 assign m_valid = valid;
 assign m_data = BIG_ENDIAN == 1 ?
-	data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] :
-	data[MASTER_DATA_WIDTH-1:0];
+  data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] :
+  data[MASTER_DATA_WIDTH-1:0];
 
 end
 endgenerate
diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v
index 712375621..a9b96a551 100644
--- a/library/util_clkdiv/util_clkdiv.v
+++ b/library/util_clkdiv/util_clkdiv.v
@@ -40,8 +40,8 @@
 `timescale 1ns/100ps
 
 module util_clkdiv (
-	clk,
-	clk_out
+  clk,
+  clk_out
  );
 
   input   clk;
diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi.v b/library/util_sigma_delta_spi/util_sigma_delta_spi.v
index 9a9f3fa3f..48fd94965 100644
--- a/library/util_sigma_delta_spi/util_sigma_delta_spi.v
+++ b/library/util_sigma_delta_spi/util_sigma_delta_spi.v
@@ -1,23 +1,23 @@
 
 module util_sigma_delta_spi (
-	input clk,
-	input resetn,
+  input clk,
+  input resetn,
 
-	input spi_active,
+  input spi_active,
 
-	input s_sclk,
-	input s_sdo,
-	input s_sdo_t,
-	output s_sdi,
-	input [NUM_OF_CS-1:0] s_cs,
+  input s_sclk,
+  input s_sdo,
+  input s_sdo_t,
+  output s_sdi,
+  input [NUM_OF_CS-1:0] s_cs,
 
-	output m_sclk,
-	output m_sdo,
-	output m_sdo_t,
-	input m_sdi,
-	output [NUM_OF_CS-1:0] m_cs,
+  output m_sclk,
+  output m_sdo,
+  output m_sdo_t,
+  input m_sdi,
+  output [NUM_OF_CS-1:0] m_cs,
 
-	output reg data_ready
+  output reg data_ready
 );
 
 parameter NUM_OF_CS = 1;
@@ -46,29 +46,29 @@ reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;
 reg [2:0] sdi_d = 'h00;
 
 always @(posedge clk) begin
-	if (resetn == 1'b0) begin
-		counter <= IDLE_TIMEOUT;
-	end else begin
-		if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
-			if (counter != 'h00)
-				counter <= counter - 1'b1;
-		end else begin
-			counter <= IDLE_TIMEOUT;
-		end
-	end
+  if (resetn == 1'b0) begin
+    counter <= IDLE_TIMEOUT;
+  end else begin
+    if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
+      if (counter != 'h00)
+        counter <= counter - 1'b1;
+    end else begin
+      counter <= IDLE_TIMEOUT;
+    end
+  end
 end
 
 always @(posedge clk) begin
-	/* The data ready signal is fully asynchronous */
-	sdi_d <= {sdi_d[1:0], m_sdi};
+  /* The data ready signal is fully asynchronous */
+  sdi_d <= {sdi_d[1:0], m_sdi};
 end
 
 always @(posedge clk) begin
-	if (counter == 'h00 && sdi_d[2] == 1'b0) begin
-		data_ready <= 1'b1;
-	end else begin
-		data_ready <= 1'b0;
-	end
+  if (counter == 'h00 && sdi_d[2] == 1'b0) begin
+    data_ready <= 1'b1;
+  end else begin
+    data_ready <= 1'b0;
+  end
 end
 
 endmodule

From 43b3761b807d8bcbb430b3616308fd0ada532f08 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 3 Oct 2016 12:24:04 +0300
Subject: [PATCH 555/972] axi_ad9361: Flop the tx and rx valid

---
 library/axi_ad9361/axi_ad9361.v | 207 +++++++++++++++++---------------
 1 file changed, 112 insertions(+), 95 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index d24226da7..f3101e55a 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -69,116 +69,116 @@ module axi_ad9361 #(
 
   // physical interface (receive-cmos)
 
-  input           rx_clk_in,
-  input           rx_frame_in,
-  input   [11:0]  rx_data_in,
+  input               rx_clk_in,
+  input               rx_frame_in,
+  input   [11:0]      rx_data_in,
 
   // physical interface (transmit-lvds)
 
-  output          tx_clk_out_p,
-  output          tx_clk_out_n,
-  output          tx_frame_out_p,
-  output          tx_frame_out_n,
-  output  [ 5:0]  tx_data_out_p,
-  output  [ 5:0]  tx_data_out_n,
+  output              tx_clk_out_p,
+  output              tx_clk_out_n,
+  output              tx_frame_out_p,
+  output              tx_frame_out_n,
+  output  [ 5:0]      tx_data_out_p,
+  output  [ 5:0]      tx_data_out_n,
 
   // physical interface (transmit-cmos)
 
-  output          tx_clk_out,
-  output          tx_frame_out,
-  output  [11:0]  tx_data_out,
+  output              tx_clk_out,
+  output              tx_frame_out,
+  output  [11:0]      tx_data_out,
 
   // ensm control
 
-  output          enable,
-  output          txnrx,
+  output              enable,
+  output              txnrx,
 
   // transmit master/slave
 
-  input           dac_sync_in,
-  output          dac_sync_out,
+  input               dac_sync_in,
+  output              dac_sync_out,
 
   // tdd sync
 
-  input           tdd_sync,
-  output          tdd_sync_cntr,
+  input               tdd_sync,
+  output              tdd_sync_cntr,
 
   // delay clock
 
-  input           delay_clk,
+  input               delay_clk,
 
   // master interface
 
-  output          l_clk,
-  input           clk,
-  output          rst,
+  output              l_clk,
+  input               clk,
+  output              rst,
 
   // dma interface
 
-  output          adc_enable_i0,
-  output          adc_valid_i0,
-  output  [15:0]  adc_data_i0,
-  output          adc_enable_q0,
-  output          adc_valid_q0,
-  output  [15:0]  adc_data_q0,
-  output          adc_enable_i1,
-  output          adc_valid_i1,
-  output  [15:0]  adc_data_i1,
-  output          adc_enable_q1,
-  output          adc_valid_q1,
-  output  [15:0]  adc_data_q1,
-  input           adc_dovf,
-  input           adc_dunf,
-  output          adc_r1_mode,
+  output              adc_enable_i0,
+  output  reg         adc_valid_i0,
+  output  reg [15:0]  adc_data_i0,
+  output              adc_enable_q0,
+  output  reg         adc_valid_q0,
+  output  reg [15:0]  adc_data_q0,
+  output              adc_enable_i1,
+  output  reg         adc_valid_i1,
+  output  reg [15:0]  adc_data_i1,
+  output              adc_enable_q1,
+  output  reg         adc_valid_q1,
+  output  reg [15:0]  adc_data_q1,
+  input               adc_dovf,
+  input               adc_dunf,
+  output              adc_r1_mode,
 
-  output          dac_enable_i0,
-  output          dac_valid_i0,
-  input   [15:0]  dac_data_i0,
-  output          dac_enable_q0,
-  output          dac_valid_q0,
-  input   [15:0]  dac_data_q0,
-  output          dac_enable_i1,
-  output          dac_valid_i1,
-  input   [15:0]  dac_data_i1,
-  output          dac_enable_q1,
-  output          dac_valid_q1,
-  input   [15:0]  dac_data_q1,
-  input           dac_dovf,
-  input           dac_dunf,
-  output          dac_r1_mode,
+  output              dac_enable_i0,
+  output  reg         dac_valid_i0,
+  input       [15:0]  dac_data_i0,
+  output              dac_enable_q0,
+  output  reg         dac_valid_q0,
+  input       [15:0]  dac_data_q0,
+  output              dac_enable_i1,
+  output  reg         dac_valid_i1,
+  input       [15:0]  dac_data_i1,
+  output              dac_enable_q1,
+  output  reg         dac_valid_q1,
+  input       [15:0]  dac_data_q1,
+  input               dac_dovf,
+  input               dac_dunf,
+  output              dac_r1_mode,
 
   // axi interface
 
-  input           s_axi_aclk,
-  input           s_axi_aresetn,
-  input           s_axi_awvalid,
-  input   [31:0]  s_axi_awaddr,
-  input   [ 2:0]  s_axi_awprot,
-  output          s_axi_awready,
-  input           s_axi_wvalid,
-  input   [31:0]  s_axi_wdata,
-  input   [ 3:0]  s_axi_wstrb,
-  output          s_axi_wready,
-  output          s_axi_bvalid,
-  output  [ 1:0]  s_axi_bresp,
-  input           s_axi_bready,
-  input           s_axi_arvalid,
-  input   [31:0]  s_axi_araddr,
-  input   [ 2:0]  s_axi_arprot,
-  output          s_axi_arready,
-  output          s_axi_rvalid,
-  output  [31:0]  s_axi_rdata,
-  output  [ 1:0]  s_axi_rresp,
-  input           s_axi_rready,
+  input               s_axi_aclk,
+  input               s_axi_aresetn,
+  input               s_axi_awvalid,
+  input   [31:0]      s_axi_awaddr,
+  input   [ 2:0]      s_axi_awprot,
+  output              s_axi_awready,
+  input               s_axi_wvalid,
+  input   [31:0]      s_axi_wdata,
+  input   [ 3:0]      s_axi_wstrb,
+  output              s_axi_wready,
+  output              s_axi_bvalid,
+  output  [ 1:0]      s_axi_bresp,
+  input               s_axi_bready,
+  input               s_axi_arvalid,
+  input   [31:0]      s_axi_araddr,
+  input   [ 2:0]      s_axi_arprot,
+  output              s_axi_arready,
+  output              s_axi_rvalid,
+  output  [31:0]      s_axi_rdata,
+  output  [ 1:0]      s_axi_rresp,
+  input               s_axi_rready,
 
   // gpio
 
-  input           up_enable,
-  input           up_txnrx,
-  input   [31:0]  up_dac_gpio_in,
-  output  [31:0]  up_dac_gpio_out,
-  input   [31:0]  up_adc_gpio_in,
-  output  [31:0]  up_adc_gpio_out);
+  input               up_enable,
+  input               up_txnrx,
+  input   [31:0]      up_dac_gpio_in,
+  output  [31:0]      up_dac_gpio_out,
+  input   [31:0]      up_adc_gpio_in,
+  output  [31:0]      up_adc_gpio_out);
 
   // derived parameters
 
@@ -208,6 +208,14 @@ module axi_ad9361 #(
 
   wire            adc_ddr_edgesel_s;
   wire            adc_valid_s;
+  wire            adc_valid_i0_s;
+  wire            adc_valid_q0_s;
+  wire            adc_valid_i1_s;
+  wire            adc_valid_q1_s;
+  wire    [15:0]  adc_data_i0_s;
+  wire    [15:0]  adc_data_q0_s;
+  wire    [15:0]  adc_data_i1_s;
+  wire    [15:0]  adc_data_q1_s;
   wire    [47:0]  adc_data_s;
   wire            adc_status_s;
   wire            dac_clksel_s;
@@ -217,6 +225,10 @@ module axi_ad9361 #(
   wire            dac_valid_q0_s;
   wire            dac_valid_i1_s;
   wire            dac_valid_q1_s;
+  wire            dac_data_i0_s;
+  wire            dac_data_q0_s;
+  wire            dac_data_i1_s;
+  wire            dac_data_q1_s;
   wire    [12:0]  up_adc_dld_s;
   wire    [64:0]  up_adc_dwdata_s;
   wire    [64:0]  up_adc_drdata_s;
@@ -248,10 +260,6 @@ module axi_ad9361 #(
   wire            tdd_rx_rf_en_s;
   wire            tdd_tx_rf_en_s;
   wire    [ 7:0]  tdd_status_s;
-  wire            adc_valid_i0_s;
-  wire            adc_valid_q0_s;
-  wire            adc_valid_i1_s;
-  wire            adc_valid_q1_s;
 
   // signal name changes
 
@@ -387,14 +395,23 @@ module axi_ad9361 #(
   end
   endgenerate
 
-  assign dac_valid_i0 = tdd_tx_valid_s & dac_valid_i0_s;
-  assign dac_valid_q0 = tdd_tx_valid_s & dac_valid_q0_s;
-  assign dac_valid_i1 = tdd_tx_valid_s & dac_valid_i1_s;
-  assign dac_valid_q1 = tdd_tx_valid_s & dac_valid_q1_s;
-  assign adc_valid_i0 = tdd_rx_valid_s & adc_valid_i0_s;
-  assign adc_valid_q0 = tdd_rx_valid_s & adc_valid_q0_s;
-  assign adc_valid_i1 = tdd_rx_valid_s & adc_valid_i1_s;
-  assign adc_valid_q1 = tdd_rx_valid_s & adc_valid_q1_s;
+  always @(posedge clk) begin
+
+    dac_valid_i0 <= tdd_tx_valid_s & dac_valid_i0_s;
+    dac_valid_q0 <= tdd_tx_valid_s & dac_valid_q0_s;
+    dac_valid_i1 <= tdd_tx_valid_s & dac_valid_i1_s;
+    dac_valid_q1 <= tdd_tx_valid_s & dac_valid_q1_s;
+
+    adc_valid_i0 <= tdd_rx_valid_s & adc_valid_i0_s;
+    adc_valid_q0 <= tdd_rx_valid_s & adc_valid_q0_s;
+    adc_valid_i1 <= tdd_rx_valid_s & adc_valid_i1_s;
+    adc_valid_q1 <= tdd_rx_valid_s & adc_valid_q1_s;
+    adc_data_i0 <= adc_data_i0_s;
+    adc_data_q0 <= adc_data_q0_s;
+    adc_data_i1 <= adc_data_i1_s;
+    adc_data_q1 <= adc_data_q1_s;
+
+  end
 
   // tdd
 
@@ -484,16 +501,16 @@ module axi_ad9361 #(
     .delay_locked (delay_locked_s),
     .adc_enable_i0 (adc_enable_i0),
     .adc_valid_i0 (adc_valid_i0_s),
-    .adc_data_i0 (adc_data_i0),
+    .adc_data_i0 (adc_data_i0_s),
     .adc_enable_q0 (adc_enable_q0),
     .adc_valid_q0 (adc_valid_q0_s),
-    .adc_data_q0 (adc_data_q0),
+    .adc_data_q0 (adc_data_q0_s),
     .adc_enable_i1 (adc_enable_i1),
     .adc_valid_i1 (adc_valid_i1_s),
-    .adc_data_i1 (adc_data_i1),
+    .adc_data_i1 (adc_data_i1_s),
     .adc_enable_q1 (adc_enable_q1),
     .adc_valid_q1 (adc_valid_q1_s),
-    .adc_data_q1 (adc_data_q1),
+    .adc_data_q1 (adc_data_q1_s),
     .adc_dovf (adc_dovf),
     .adc_dunf (adc_dunf),
     .up_adc_gpio_in (up_adc_gpio_in),

From 8e0dc859af0ec52e18ca9863725fa91ebe524c8f Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 3 Oct 2016 15:17:01 +0300
Subject: [PATCH 556/972] axi_usb_fx3: Update

- added 1 clock delay for slrd_n signal
- rearrange databytes
---
 library/axi_usb_fx3/axi_usb_fx3_if.v | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/library/axi_usb_fx3/axi_usb_fx3_if.v b/library/axi_usb_fx3/axi_usb_fx3_if.v
index 088e4a01e..0f78d5608 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_if.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_if.v
@@ -139,13 +139,14 @@ module axi_usb_fx3_if (
   reg         fx32dma_sop;
   reg         fx32dma_sop_d1;
   reg         pktend_n;
+  reg         slcs_n_d1;
 
   localparam IDLE         = 4'b0001;
   localparam READ_START   = 4'b0010;
   localparam READ_DATA    = 4'b0100;
   localparam WRITE_DATA   = 4'b1000;
 
-  assign data = (state_gpif_ii == WRITE_DATA && dma2fx3_valid && current_fifo) ? {dma2fx3_data[7:0],dma2fx3_data[15:8],dma2fx3_data[23:16], dma2fx3_data[31:24]}  : 32'hz;
+  assign data = (state_gpif_ii == WRITE_DATA && dma2fx3_valid && current_fifo) ? dma2fx3_data  : 32'hz;
   assign epswitch_n = 1'b1;
 
   always @(fifo_num, fifo_rdy, fifo_direction) begin
@@ -256,7 +257,7 @@ module axi_usb_fx3_if (
       READ_START: begin
         slcs_n        = 1'b0;
         sloe_n        = 1'b0;
-        slrd_n        = 1'b0;
+        slrd_n        = slcs_n_d1;
         fx32dma_valid = 1'b0;
         fx32dma_sop   = 1'b0;
         fx32dma_data  = 32'h0;
@@ -271,8 +272,7 @@ module axi_usb_fx3_if (
         slrd_n        = !current_fifo_d3;
         fx32dma_valid = !sloe_n_d3;
         fx32dma_sop   = fx32dma_sop_d1;
-        fx32dma_data  = {data[7:0],data[15:8],data[23:16], data[31:24]};
-        //fx32dma_data  =  data;
+        fx32dma_data  = data;
         slwr_n        = 1'b1;
         pktend_n      = 1'b1;
         dma2fx3_ready = 1'b0;
@@ -306,6 +306,7 @@ module axi_usb_fx3_if (
   end
 
   always @(posedge pclk) begin
+    slcs_n_d1 <= slcs_n;
     current_fifo_d1 <= current_fifo;
     current_fifo_d2 <= current_fifo_d1;
     current_fifo_d3 <= current_fifo_d2;

From 63ddcf1e268730b1f0e6ac79f64322765a98af0c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 30 Sep 2016 15:25:03 -0400
Subject: [PATCH 557/972] util_adxcvr- synthesis warnings fix

---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 33 ++++++++++++++------
 1 file changed, 24 insertions(+), 9 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 34250b24f..98ac15199 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -164,10 +164,10 @@ module util_adxcvr_xch (
   wire            tx_rst_done_s;
   wire    [ 1:0]  rx_pll_clk_sel_s;
   wire    [ 1:0]  tx_pll_clk_sel_s;
-  wire    [ 3:0]  rx_charisk_open_s;
-  wire    [ 3:0]  rx_disperr_open_s;
+  wire    [11:0]  rx_charisk_open_s;
+  wire    [11:0]  rx_disperr_open_s;
   wire    [ 3:0]  rx_notintable_open_s;
-  wire    [31:0]  rx_data_open_s;
+  wire    [95:0]  rx_data_open_s;
   wire            cpll_locked_s;
 
   // pll
@@ -303,8 +303,23 @@ module util_adxcvr_xch (
 
   generate
   if (GTH_OR_GTX_N == 1) begin
-  BUFG_GT i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk));
-  BUFG_GT i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk));
+  BUFG_GT i_rx_bufg (
+    .CE (1'b1),
+    .CEMASK (1'b0),
+    .CLR (1'b0),
+    .CLRMASK (1'b0),
+    .DIV (3'd0),
+    .I (rx_out_clk_s),
+    .O (rx_out_clk));
+
+  BUFG_GT i_tx_bufg (
+    .CE (1'b1),
+    .CEMASK (1'b0),
+    .CLR (1'b0),
+    .CLRMASK (1'b0),
+    .DIV (3'd0),
+    .I (tx_out_clk_s),
+    .O (tx_out_clk));
   end
   endgenerate
 
@@ -579,14 +594,14 @@ module util_adxcvr_xch (
     .RX8B10BEN (1'd1),
     .RXUSRCLK (rx_clk),
     .RXUSRCLK2 (rx_clk),
-    .RXDATA ({rx_data_open_s, rx_data}),
+    .RXDATA ({rx_data_open_s[31:0], rx_data}),
     .RXPRBSERR (),
     .RXPRBSSEL (3'd0),
     .RXPRBSCNTRESET (1'd0),
     .RXDFEXYDEN (1'd0),
     .RXDFEXYDHOLD (1'd0),
     .RXDFEXYDOVRDEN (1'd0),
-    .RXDISPERR ({rx_disperr_open_s, rx_disperr}),
+    .RXDISPERR ({rx_disperr_open_s[3:0], rx_disperr}),
     .RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
     .GTXRXP (rx_p),
     .GTXRXN (rx_n),
@@ -671,7 +686,7 @@ module util_adxcvr_xch (
     .RXPOLARITY (1'd0),
     .RXSLIDE (1'd0),
     .RXCHARISCOMMA (),
-    .RXCHARISK ({rx_charisk_open_s, rx_charisk}),
+    .RXCHARISK ({rx_charisk_open_s[3:0], rx_charisk}),
     .RXCHBONDI (5'd0),
     .RXRESETDONE (rx_rst_done_s),
     .RXQPIEN (1'd0),
@@ -1324,7 +1339,7 @@ module util_adxcvr_xch (
     .TXCTRL0 (16'd0),
     .TXCTRL1 (16'd0),
     .TXCTRL2 ({4'd0, tx_charisk}),
-    .TXDATA ({32'd0, tx_data}),
+    .TXDATA ({96'd0, tx_data}),
     .TXDATAEXTENDRSVD (8'd0),
     .TXDEEMPH (1'd0),
     .TXDETECTRX (1'd0),

From b4652650e42721da2870b2e6a34d1cbb9eb1ba61 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 3 Oct 2016 14:08:19 -0400
Subject: [PATCH 558/972] util_adxcvr- xcvr_type parameter

---
 library/xilinx/util_adxcvr/util_adxcvr.v     | 76 ++++++++++----------
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 40 +++++------
 library/xilinx/util_adxcvr/util_adxcvr_xcm.v | 24 +++----
 3 files changed, 71 insertions(+), 69 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v
index 03ea527f7..a847e3ea6 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr.v
@@ -38,7 +38,25 @@
 
 `timescale 1ns/1ps
 
-module util_adxcvr (
+module util_adxcvr #(
+
+  // parameters
+
+  parameter   integer RX_NUM_OF_LANES = 8,
+  parameter   integer TX_NUM_OF_LANES = 8,
+  parameter   integer XCVR_TYPE = 0,
+  parameter   integer CPLL_TX_OR_RX_N = 0,
+  parameter   integer CPLL_FBDIV = 2,
+  parameter   integer QPLL_REFCLK_DIV = 1,
+  parameter   integer QPLL_FBDIV_RATIO = 1,
+  parameter   integer RX_OUT_DIV = 1,
+  parameter   integer RX_CLK25_DIV = 20,
+  parameter   integer TX_OUT_DIV = 1,
+  parameter   integer TX_CLK25_DIV = 20,
+  parameter   [31:0]  PMA_RSV = 32'h001e7080,
+  parameter   [72:0]  RX_CDR_CFG = 72'h0b000023ff10400020,
+  parameter   [26:0]  QPLL_CFG = 27'h0680181,
+  parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000) (
 
   input           up_rstn,
   input           up_clk,
@@ -1021,22 +1039,6 @@ module util_adxcvr (
 
   // parameters
 
-  parameter   integer RX_NUM_OF_LANES = 8;
-  parameter   integer TX_NUM_OF_LANES = 8;
-  parameter   integer GTH_OR_GTX_N = 0;
-  parameter   integer CPLL_TX_OR_RX_N = 0;
-  parameter   integer CPLL_FBDIV = 2;
-  parameter   integer QPLL_REFCLK_DIV = 1;
-  parameter   integer QPLL_FBDIV_RATIO = 1;
-  parameter   integer RX_OUT_DIV = 1;
-  parameter   integer RX_CLK25_DIV = 20;
-  parameter   integer TX_OUT_DIV = 1;
-  parameter   integer TX_CLK25_DIV = 20;
-  parameter   [31:0]  PMA_RSV = 32'h001e7080;
-  parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff10400020;
-  parameter   [26:0]  QPLL_CFG = 27'h0680181;
-  parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000;
-
   localparam  integer NUM_OF_LANES = (TX_NUM_OF_LANES > RX_NUM_OF_LANES) ?
     TX_NUM_OF_LANES : RX_NUM_OF_LANES;
 
@@ -1072,7 +1074,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 1) begin
   util_adxcvr_xcm #(
     .XCVR_ID (0),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
     .QPLL_CFG (QPLL_CFG),
@@ -1105,7 +1107,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 1) begin
   util_adxcvr_xch #(
     .XCVR_ID (0),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1202,7 +1204,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 2) begin
   util_adxcvr_xch #(
     .XCVR_ID (1),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1299,7 +1301,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 3) begin
   util_adxcvr_xch #(
     .XCVR_ID (2),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1396,7 +1398,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 4) begin
   util_adxcvr_xch #(
     .XCVR_ID (3),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1492,7 +1494,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 5) begin
   util_adxcvr_xcm #(
     .XCVR_ID (4),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
     .QPLL_CFG (QPLL_CFG),
@@ -1525,7 +1527,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 5) begin
   util_adxcvr_xch #(
     .XCVR_ID (4),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1622,7 +1624,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 6) begin
   util_adxcvr_xch #(
     .XCVR_ID (5),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1719,7 +1721,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 7) begin
   util_adxcvr_xch #(
     .XCVR_ID (6),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1816,7 +1818,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 8) begin
   util_adxcvr_xch #(
     .XCVR_ID (7),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1912,7 +1914,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 9) begin
   util_adxcvr_xcm #(
     .XCVR_ID (8),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
     .QPLL_CFG (QPLL_CFG),
@@ -1945,7 +1947,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 9) begin
   util_adxcvr_xch #(
     .XCVR_ID (8),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2042,7 +2044,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 10) begin
   util_adxcvr_xch #(
     .XCVR_ID (9),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2139,7 +2141,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 11) begin
   util_adxcvr_xch #(
     .XCVR_ID (10),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2236,7 +2238,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 12) begin
   util_adxcvr_xch #(
     .XCVR_ID (11),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2332,7 +2334,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 13) begin
   util_adxcvr_xcm #(
     .XCVR_ID (12),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
     .QPLL_CFG (QPLL_CFG),
@@ -2365,7 +2367,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 13) begin
   util_adxcvr_xch #(
     .XCVR_ID (12),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2462,7 +2464,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 14) begin
   util_adxcvr_xch #(
     .XCVR_ID (13),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2559,7 +2561,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 15) begin
   util_adxcvr_xch #(
     .XCVR_ID (14),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2656,7 +2658,7 @@ module util_adxcvr (
   if (NUM_OF_LANES >= 16) begin
   util_adxcvr_xch #(
     .XCVR_ID (15),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
+    .XCVR_TYPE (XCVR_TYPE),
     .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
     .RX_OUT_DIV (RX_OUT_DIV),
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 98ac15199..5dc0d6836 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -37,7 +37,20 @@
 
 `timescale 1ns/1ps
 
-module util_adxcvr_xch (
+module util_adxcvr_xch #(
+
+  // parameters
+
+  parameter   integer XCVR_ID = 0,
+  parameter   integer XCVR_TYPE = 0,
+  parameter   integer CPLL_TX_OR_RX_N = 0,
+  parameter   integer CPLL_FBDIV = 2,
+  parameter   integer RX_OUT_DIV = 1,
+  parameter   integer RX_CLK25_DIV = 10,
+  parameter   integer TX_OUT_DIV = 1,
+  parameter   integer TX_CLK25_DIV = 10,
+  parameter   [31:0]  PMA_RSV = 32'h00018480,
+  parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff20400020) (
 
   // pll interface
 
@@ -113,19 +126,6 @@ module util_adxcvr_xch (
   output  [15:0]  up_tx_rdata,
   output          up_tx_ready);
 
-  // parameters
-
-  parameter   integer XCVR_ID = 0;
-  parameter   integer GTH_OR_GTX_N = 0;
-  parameter   integer CPLL_TX_OR_RX_N = 0;
-  parameter   integer CPLL_FBDIV = 2;
-  parameter   integer RX_OUT_DIV = 1;
-  parameter   integer RX_CLK25_DIV = 10;
-  parameter   integer TX_OUT_DIV = 1;
-  parameter   integer TX_CLK25_DIV = 10;
-  parameter   [31:0]  PMA_RSV = 32'h00018480;
-  parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff20400020;
-
   // internal registers
 
   reg     [15:0]  up_es_rdata_int = 'd0;
@@ -295,14 +295,14 @@ module util_adxcvr_xch (
   // instantiations
 
   generate
-  if (GTH_OR_GTX_N == 0) begin
+  if (XCVR_TYPE == 0) begin
   BUFG i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk));
   BUFG i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk));
   end
   endgenerate
 
   generate
-  if (GTH_OR_GTX_N == 1) begin
+  if (XCVR_TYPE == 1) begin
   BUFG_GT i_rx_bufg (
     .CE (1'b1),
     .CEMASK (1'b0),
@@ -324,7 +324,7 @@ module util_adxcvr_xch (
   endgenerate
 
   generate
-  if (GTH_OR_GTX_N == 0) begin
+  if (XCVR_TYPE == 0) begin
   assign rx_sys_clk_sel_s = up_rx_sys_clk_sel;
   assign tx_sys_clk_sel_s = up_tx_sys_clk_sel;
   assign rx_pll_clk_sel_s = 2'd0;
@@ -333,7 +333,7 @@ module util_adxcvr_xch (
   endgenerate
 
   generate
-  if (GTH_OR_GTX_N == 0) begin
+  if (XCVR_TYPE == 0) begin
   GTXE2_CHANNEL #(
     .SIM_RECEIVER_DETECT_PASS ("TRUE"),
     .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), 
@@ -769,7 +769,7 @@ module util_adxcvr_xch (
   endgenerate
 
   generate
-  if (GTH_OR_GTX_N == 1) begin
+  if (XCVR_TYPE == 1) begin
   assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
   assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
   assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
@@ -778,7 +778,7 @@ module util_adxcvr_xch (
   endgenerate
 
   generate
-  if (GTH_OR_GTX_N == 1) begin
+  if (XCVR_TYPE == 1) begin
   GTHE3_CHANNEL #(
     .ACJTAG_DEBUG_MODE (1'b0),
     .ACJTAG_MODE (1'b0),
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
index ba3c88785..b627eafcf 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
@@ -37,7 +37,16 @@
 
 `timescale 1ns/1ps
 
-module util_adxcvr_xcm (
+module util_adxcvr_xcm #(
+
+  // parameters
+
+  parameter   integer XCVR_ID = 0,
+  parameter   integer XCVR_TYPE = 0,
+  parameter   integer QPLL_REFCLK_DIV = 2,
+  parameter   integer QPLL_FBDIV_RATIO = 1,
+  parameter   [26:0]  QPLL_CFG = 27'h06801C1,
+  parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000) (
 
   // reset and clocks
 
@@ -59,15 +68,6 @@ module util_adxcvr_xcm (
   output  [15:0]  up_cm_rdata,
   output          up_cm_ready);
 
-  // parameters
-
-  parameter   integer XCVR_ID = 0;
-  parameter   integer GTH_OR_GTX_N = 0;
-  parameter   integer QPLL_REFCLK_DIV = 2;
-  parameter   integer QPLL_FBDIV_RATIO = 1;
-  parameter   [26:0]  QPLL_CFG = 27'h06801C1;
-  parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000;
-
   // internal registers
 
   reg             up_enb_int = 'd0;
@@ -117,7 +117,7 @@ module util_adxcvr_xcm (
   // instantiations
 
   generate
-  if (GTH_OR_GTX_N == 0) begin
+  if (XCVR_TYPE == 0) begin
   GTXE2_COMMON #(
     .SIM_RESET_SPEEDUP ("TRUE"),
     .SIM_QPLLREFCLK_SEL (3'b001),
@@ -178,7 +178,7 @@ module util_adxcvr_xcm (
   endgenerate
 
   generate
-  if (GTH_OR_GTX_N == 1) begin
+  if (XCVR_TYPE == 1) begin
   GTHE3_COMMON #(
     .SIM_RESET_SPEEDUP ("TRUE"),
     .SIM_VERSION (2),

From 0e8551545c25c6b7bf196689cca24a17201054a1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 3 Oct 2016 15:13:03 -0400
Subject: [PATCH 559/972] util_adxcvr- ultrascale+ initial commit

---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 859 +++++++++++++++++++
 1 file changed, 859 insertions(+)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 5dc0d6836..b74f917cc 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -1500,6 +1500,865 @@ module util_adxcvr_xch #(
   end
   endgenerate
 
+  generate
+  if (XCVR_TYPE == 1) begin
+  assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
+  assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
+  assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
+  assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
+  end
+  endgenerate
+
+  generate
+  if (XCVR_TYPE == 1) begin
+  GTHE4_CHANNEL #(
+    .ACJTAG_DEBUG_MODE (1'b0),
+    .ACJTAG_MODE (1'b0),
+    .ACJTAG_RESET (1'b0),
+    .ADAPT_CFG0 (16'h1000),
+    .ADAPT_CFG1 (16'hc800),
+    .ADAPT_CFG2 (16'h0000),
+    .ALIGN_COMMA_DOUBLE ("FALSE"),
+    .ALIGN_COMMA_ENABLE (10'b1111111111),
+    .ALIGN_COMMA_WORD (1),
+    .ALIGN_MCOMMA_DET ("TRUE"),
+    .ALIGN_MCOMMA_VALUE (10'b1010000011),
+    .ALIGN_PCOMMA_DET ("TRUE"),
+    .ALIGN_PCOMMA_VALUE (10'b0101111100),
+    .A_RXOSCALRESET (1'b0),
+    .A_RXPROGDIVRESET (1'b0),
+    .A_RXTERMINATION (1'b1),
+    .A_TXDIFFCTRL (5'b01100),
+    .A_TXPROGDIVRESET (1'b0),
+    .CAPBYPASS_FORCE (1'b0),
+    .CBCC_DATA_SOURCE_SEL ("DECODED"),
+    .CDR_SWAP_MODE_EN (1'b0),
+    .CFOK_PWRSVE_EN (1'b1),
+    .CHAN_BOND_KEEP_ALIGN ("FALSE"),
+    .CHAN_BOND_MAX_SKEW (1),
+    .CHAN_BOND_SEQ_1_1 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_2 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_3 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_4 (10'b0000000000),
+    .CHAN_BOND_SEQ_1_ENABLE (4'b1111),
+    .CHAN_BOND_SEQ_2_1 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_2 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_3 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_4 (10'b0000000000),
+    .CHAN_BOND_SEQ_2_ENABLE (4'b1111),
+    .CHAN_BOND_SEQ_2_USE ("FALSE"),
+    .CHAN_BOND_SEQ_LEN (1),
+    .CH_HSPMUX (16'h2424),
+    .CKCAL1_CFG_0 (16'b1100000011000000),
+    .CKCAL1_CFG_1 (16'b0101000011000000),
+    .CKCAL1_CFG_2 (16'b0000000000001010),
+    .CKCAL1_CFG_3 (16'b0000000000000000),
+    .CKCAL2_CFG_0 (16'b1100000011000000),
+    .CKCAL2_CFG_1 (16'b1000000011000000),
+    .CKCAL2_CFG_2 (16'b0000000000000000),
+    .CKCAL2_CFG_3 (16'b0000000000000000),
+    .CKCAL2_CFG_4 (16'b0000000000000000),
+    .CKCAL_RSVD0 (16'h0080),
+    .CKCAL_RSVD1 (16'h0400),
+    .CLK_CORRECT_USE ("FALSE"),
+    .CLK_COR_KEEP_IDLE ("FALSE"),
+    .CLK_COR_MAX_LAT (12),
+    .CLK_COR_MIN_LAT (8),
+    .CLK_COR_PRECEDENCE ("TRUE"),
+    .CLK_COR_REPEAT_WAIT (0),
+    .CLK_COR_SEQ_1_1 (10'b0100000000),
+    .CLK_COR_SEQ_1_2 (10'b0100000000),
+    .CLK_COR_SEQ_1_3 (10'b0100000000),
+    .CLK_COR_SEQ_1_4 (10'b0100000000),
+    .CLK_COR_SEQ_1_ENABLE (4'b1111),
+    .CLK_COR_SEQ_2_1 (10'b0100000000),
+    .CLK_COR_SEQ_2_2 (10'b0100000000),
+    .CLK_COR_SEQ_2_3 (10'b0100000000),
+    .CLK_COR_SEQ_2_4 (10'b0100000000),
+    .CLK_COR_SEQ_2_ENABLE (4'b1111),
+    .CLK_COR_SEQ_2_USE ("FALSE"),
+    .CLK_COR_SEQ_LEN (1),
+    .CPLL_CFG0 (16'h01fa),
+    .CPLL_CFG1 (16'h0023),
+    .CPLL_CFG2 (16'h0002),
+    .CPLL_CFG3 (16'h0000),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .CPLL_FBDIV_45 (5),
+    .CPLL_INIT_CFG0 (16'h02b2),
+    .CPLL_LOCK_CFG (16'h01e8),
+    .CPLL_REFCLK_DIV (1),
+    .CTLE3_OCAP_EXT_CTRL (3'b000),
+    .CTLE3_OCAP_EXT_EN (1'b0),
+    .DDI_CTRL (2'b00),
+    .DDI_REALIGN_WAIT (15),
+    .DEC_MCOMMA_DETECT ("TRUE"),
+    .DEC_PCOMMA_DETECT ("TRUE"),
+    .DEC_VALID_COMMA_ONLY ("FALSE"),
+    .DELAY_ELEC (1'b0),
+    .DMONITOR_CFG0 (10'h000),
+    .DMONITOR_CFG1 (8'h00),
+    .ES_CLK_PHASE_SEL (1'b0),
+    .ES_CONTROL (6'b000000),
+    .ES_ERRDET_EN ("TRUE"),
+    .ES_EYE_SCAN_EN ("TRUE"),
+    .ES_HORZ_OFFSET (12'h000),
+    .ES_PRESCALE (5'b00000),
+    .ES_QUALIFIER0 (16'h0000),
+    .ES_QUALIFIER1 (16'h0000),
+    .ES_QUALIFIER2 (16'h0000),
+    .ES_QUALIFIER3 (16'h0000),
+    .ES_QUALIFIER4 (16'h0000),
+    .ES_QUALIFIER5 (16'h0000),
+    .ES_QUALIFIER6 (16'h0000),
+    .ES_QUALIFIER7 (16'h0000),
+    .ES_QUALIFIER8 (16'h0000),
+    .ES_QUALIFIER9 (16'h0000),
+    .ES_QUAL_MASK0 (16'h0000),
+    .ES_QUAL_MASK1 (16'h0000),
+    .ES_QUAL_MASK2 (16'h0000),
+    .ES_QUAL_MASK3 (16'h0000),
+    .ES_QUAL_MASK4 (16'h0000),
+    .ES_QUAL_MASK5 (16'h0000),
+    .ES_QUAL_MASK6 (16'h0000),
+    .ES_QUAL_MASK7 (16'h0000),
+    .ES_QUAL_MASK8 (16'h0000),
+    .ES_QUAL_MASK9 (16'h0000),
+    .ES_SDATA_MASK0 (16'h0000),
+    .ES_SDATA_MASK1 (16'h0000),
+    .ES_SDATA_MASK2 (16'h0000),
+    .ES_SDATA_MASK3 (16'h0000),
+    .ES_SDATA_MASK4 (16'h0000),
+    .ES_SDATA_MASK5 (16'h0000),
+    .ES_SDATA_MASK6 (16'h0000),
+    .ES_SDATA_MASK7 (16'h0000),
+    .ES_SDATA_MASK8 (16'h0000),
+    .ES_SDATA_MASK9 (16'h0000),
+    .EYE_SCAN_SWAP_EN (1'b0),
+    .FTS_DESKEW_SEQ_ENABLE (4'b1111),
+    .FTS_LANE_DESKEW_CFG (4'b1111),
+    .FTS_LANE_DESKEW_EN ("FALSE"),
+    .GEARBOX_MODE (5'b00000),
+    .ISCAN_CK_PH_SEL2 (1'b0),
+    .LOCAL_MASTER (1'b1),
+    .LPBK_BIAS_CTRL (3'b100),
+    .LPBK_EN_RCAL_B (1'b0),
+    .LPBK_EXT_RCAL (4'b1000),
+    .LPBK_IND_CTRL0 (3'b000),
+    .LPBK_IND_CTRL1 (3'b000),
+    .LPBK_IND_CTRL2 (3'b000),
+    .LPBK_RG_CTRL (4'b1110),
+    .OOBDIVCTL (2'b00),
+    .OOB_PWRUP (1'b0),
+    .PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
+    .PCI3_PIPE_RX_ELECIDLE (1'b0),
+    .PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
+    .PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
+    .PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
+    .PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
+    .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
+    .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
+    .PCI3_RX_FIFO_DISABLE (1'b0),
+    .PCIE3_CLK_COR_EMPTY_THRSH (5'b00000),
+    .PCIE3_CLK_COR_FULL_THRSH (6'b010000),
+    .PCIE3_CLK_COR_MAX_LAT (5'b00100),
+    .PCIE3_CLK_COR_MIN_LAT (5'b00000),
+    .PCIE3_CLK_COR_THRSH_TIMER (6'b001000),
+    .PCIE_BUFG_DIV_CTRL (16'h3500),
+    .PCIE_PLL_SEL_MODE_GEN12 (2'h2),
+    .PCIE_PLL_SEL_MODE_GEN3 (2'h2),
+    .PCIE_PLL_SEL_MODE_GEN4 (2'h2),
+    .PCIE_RXPCS_CFG_GEN3 (16'h0aa5),
+    .PCIE_RXPMA_CFG (16'h280a),
+    .PCIE_TXPCS_CFG_GEN3 (16'h24a4),
+    .PCIE_TXPMA_CFG (16'h280a),
+    .PCS_PCIE_EN ("FALSE"),
+    .PCS_RSVD0 (16'b0000000000000000),
+    .PD_TRANS_TIME_FROM_P2 (12'h03c),
+    .PD_TRANS_TIME_NONE_P2 (8'h19),
+    .PD_TRANS_TIME_TO_P2 (8'h64),
+    .PREIQ_FREQ_BST (0),
+    .PROCESS_PAR (3'b010),
+    .RATE_SW_USE_DRP (1'b1),
+    .RCLK_SIPO_DLY_ENB (1'b0),
+    .RCLK_SIPO_INV_EN (1'b0),
+    .RESET_POWERSAVE_DISABLE (1'b0),
+    .RTX_BUF_CML_CTRL (3'b010),
+    .RTX_BUF_TERM_CTRL (2'b00),
+    .RXBUFRESET_TIME (5'b00011),
+    .RXBUF_ADDR_MODE ("FAST"),
+    .RXBUF_EIDLE_HI_CNT (4'b1000),
+    .RXBUF_EIDLE_LO_CNT (4'b0000),
+    .RXBUF_EN ("TRUE"),
+    .RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
+    .RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
+    .RXBUF_RESET_ON_EIDLE ("FALSE"),
+    .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
+    .RXBUF_THRESH_OVFLW (57),
+    .RXBUF_THRESH_OVRD ("TRUE"),
+    .RXBUF_THRESH_UNDFLW (3),
+    .RXCDRFREQRESET_TIME (5'b00001),
+    .RXCDRPHRESET_TIME (5'b00001),
+    .RXCDR_CFG0 (16'h0002),
+    .RXCDR_CFG0_GEN3 (16'h0003),
+    .RXCDR_CFG1 (16'h0000),
+    .RXCDR_CFG1_GEN3 (16'h0000),
+    .RXCDR_CFG2 (16'h0265),
+    .RXCDR_CFG2_GEN3 (16'h0265),
+    .RXCDR_CFG2_GEN4 (16'h00b4),
+    .RXCDR_CFG3 (16'h0012),
+    .RXCDR_CFG3_GEN3 (16'h0012),
+    .RXCDR_CFG3_GEN4 (16'h0024),
+    .RXCDR_CFG4 (16'h5cf6),
+    .RXCDR_CFG4_GEN3 (16'h5cf6),
+    .RXCDR_CFG5 (16'hb46b),
+    .RXCDR_CFG5_GEN3 (16'h146b),
+    .RXCDR_FR_RESET_ON_EIDLE (1'b0),
+    .RXCDR_HOLD_DURING_EIDLE (1'b0),
+    .RXCDR_LOCK_CFG0 (16'h2201),
+    .RXCDR_LOCK_CFG1 (16'h9fff),
+    .RXCDR_LOCK_CFG2 (16'h77c3),
+    .RXCDR_LOCK_CFG3 (16'h0001),
+    .RXCDR_LOCK_CFG4 (16'h0000),
+    .RXCDR_PH_RESET_ON_EIDLE (1'b0),
+    .RXCFOK_CFG0 (16'h0000),
+    .RXCFOK_CFG1 (16'h8015),
+    .RXCFOK_CFG2 (16'h02ae),
+    .RXCKCAL1_IQ_LOOP_RST_CFG (16'h0004),
+    .RXCKCAL1_I_LOOP_RST_CFG (16'h0004),
+    .RXCKCAL1_Q_LOOP_RST_CFG (16'h0004),
+    .RXCKCAL2_DX_LOOP_RST_CFG (16'h0004),
+    .RXCKCAL2_D_LOOP_RST_CFG (16'h0004),
+    .RXCKCAL2_S_LOOP_RST_CFG (16'h0004),
+    .RXCKCAL2_X_LOOP_RST_CFG (16'h0004),
+    .RXDFELPMRESET_TIME (7'b0001111),
+    .RXDFELPM_KL_CFG0 (16'h0000),
+    .RXDFELPM_KL_CFG1 (16'ha0e2),
+    .RXDFELPM_KL_CFG2 (16'h0100),
+    .RXDFE_CFG0 (16'h0a00),
+    .RXDFE_CFG1 (16'h0280),
+    .RXDFE_GC_CFG0 (16'h0000),
+    .RXDFE_GC_CFG1 (16'h8000),
+    .RXDFE_GC_CFG2 (16'hffe0),
+    .RXDFE_H2_CFG0 (16'h0000),
+    .RXDFE_H2_CFG1 (16'h0002),
+    .RXDFE_H3_CFG0 (16'h0000),
+    .RXDFE_H3_CFG1 (16'h8002),
+    .RXDFE_H4_CFG0 (16'h0000),
+    .RXDFE_H4_CFG1 (16'h8002),
+    .RXDFE_H5_CFG0 (16'h0000),
+    .RXDFE_H5_CFG1 (16'h8002),
+    .RXDFE_H6_CFG0 (16'h0000),
+    .RXDFE_H6_CFG1 (16'h8002),
+    .RXDFE_H7_CFG0 (16'h0000),
+    .RXDFE_H7_CFG1 (16'h8002),
+    .RXDFE_H8_CFG0 (16'h0000),
+    .RXDFE_H8_CFG1 (16'h8002),
+    .RXDFE_H9_CFG0 (16'h0000),
+    .RXDFE_H9_CFG1 (16'h8002),
+    .RXDFE_HA_CFG0 (16'h0000),
+    .RXDFE_HA_CFG1 (16'h8002),
+    .RXDFE_HB_CFG0 (16'h0000),
+    .RXDFE_HB_CFG1 (16'h8002),
+    .RXDFE_HC_CFG0 (16'h0000),
+    .RXDFE_HC_CFG1 (16'h8002),
+    .RXDFE_HD_CFG0 (16'h0000),
+    .RXDFE_HD_CFG1 (16'h8002),
+    .RXDFE_HE_CFG0 (16'h0000),
+    .RXDFE_HE_CFG1 (16'h8002),
+    .RXDFE_HF_CFG0 (16'h0000),
+    .RXDFE_HF_CFG1 (16'h8002),
+    .RXDFE_KH_CFG0 (16'h0000),
+    .RXDFE_KH_CFG1 (16'h8000),
+    .RXDFE_KH_CFG2 (16'h2613),
+    .RXDFE_KH_CFG3 (16'h411c),
+    .RXDFE_OS_CFG0 (16'h0000),
+    .RXDFE_OS_CFG1 (16'h8002),
+    .RXDFE_PWR_SAVING (1'b1),
+    .RXDFE_UT_CFG0 (16'h0000),
+    .RXDFE_UT_CFG1 (16'h0003),
+    .RXDFE_UT_CFG2 (16'h0000),
+    .RXDFE_VP_CFG0 (16'h0000),
+    .RXDFE_VP_CFG1 (16'h8033),
+    .RXDLY_CFG (16'h0010),
+    .RXDLY_LCFG (16'h0030),
+    .RXELECIDLE_CFG ("SIGCFG_4"),
+    .RXGBOX_FIFO_INIT_RD_ADDR (4),
+    .RXGEARBOX_EN ("FALSE"),
+    .RXISCANRESET_TIME (5'b00001),
+    .RXLPM_CFG (16'h0000),
+    .RXLPM_GC_CFG (16'h8000),
+    .RXLPM_KH_CFG0 (16'h0000),
+    .RXLPM_KH_CFG1 (16'h0002),
+    .RXLPM_OS_CFG0 (16'h0000),
+    .RXLPM_OS_CFG1 (16'h8002),
+    .RXOOB_CFG (9'b000000110),
+    .RXOOB_CLK_CFG ("PMA"),
+    .RXOSCALRESET_TIME (5'b00011),
+    .RXOUT_DIV (RX_OUT_DIV),
+    .RXPCSRESET_TIME (5'b00011),
+    .RXPHBEACON_CFG (16'h0000),
+    .RXPHDLY_CFG (16'h2070),
+    .RXPHSAMP_CFG (16'h2100),
+    .RXPHSLIP_CFG (16'h9933),
+    .RXPH_MONITOR_SEL (5'b00000),
+    .RXPI_AUTO_BW_SEL_BYPASS (1'b0),
+    .RXPI_CFG0 (16'h0002),
+    .RXPI_CFG1 (16'b0000000000010101),
+    .RXPI_LPM (1'b0),
+    .RXPI_SEL_LC (2'b00),
+    .RXPI_STARTCODE (2'b00),
+    .RXPI_VREFSEL (1'b0),
+    .RXPMACLK_SEL ("DATA"),
+    .RXPMARESET_TIME (5'b00011),
+    .RXPRBS_ERR_LOOPBACK (1'b0),
+    .RXPRBS_LINKACQ_CNT (15),
+    .RXREFCLKDIV2_SEL (1'b0),
+    .RXSLIDE_AUTO_WAIT (7),
+    .RXSLIDE_MODE ("OFF"),
+    .RXSYNC_MULTILANE (1'b1),
+    .RXSYNC_OVRD (1'b0),
+    .RXSYNC_SKIP_DA (1'b0),
+    .RX_AFE_CM_EN (1'b0),
+    .RX_BIAS_CFG0 (16'h1554),
+    .RX_BUFFER_CFG (6'b000000),
+    .RX_CAPFF_SARC_ENB (1'b0),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKMUX_EN (1'b1),
+    .RX_CLK_SLIP_OVRD (5'b00000),
+    .RX_CM_BUF_CFG (4'b1010),
+    .RX_CM_BUF_PD (1'b0),
+    .RX_CM_SEL (3),
+    .RX_CM_TRIM (10),
+    .RX_CTLE3_LPF (8'b11111111),
+    .RX_DATA_WIDTH (40),
+    .RX_DDI_SEL (6'b000000),
+    .RX_DEFER_RESET_BUF_EN ("TRUE"),
+    .RX_DEGEN_CTRL (3'b011),
+    .RX_DFELPM_CFG0 (6),
+    .RX_DFELPM_CFG1 (1'b1),
+    .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
+    .RX_DFE_AGC_CFG0 (2'b10),
+    .RX_DFE_AGC_CFG1 (4),
+    .RX_DFE_KL_LPM_KH_CFG0 (1),
+    .RX_DFE_KL_LPM_KH_CFG1 (4),
+    .RX_DFE_KL_LPM_KL_CFG0 (2'b01),
+    .RX_DFE_KL_LPM_KL_CFG1 (4),
+    .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
+    .RX_DISPERR_SEQ_MATCH ("TRUE"),
+    .RX_DIV2_MODE_B (1'b0),
+    .RX_DIVRESET_TIME (5'b00001),
+    .RX_EN_CTLE_RCAL_B (1'b0),
+    .RX_EN_HI_LR (1'b1),
+    .RX_EXT_RL_CTRL (9'b000000000),
+    .RX_EYESCAN_VS_CODE (7'b0000000),
+    .RX_EYESCAN_VS_NEG_DIR (1'b0),
+    .RX_EYESCAN_VS_RANGE (2'b00),
+    .RX_EYESCAN_VS_UT_SIGN (1'b0),
+    .RX_FABINT_USRCLK_FLOP (1'b0),
+    .RX_INT_DATAWIDTH (1),
+    .RX_PMA_POWER_SAVE (1'b0),
+    .RX_PMA_RSV0 (16'h0000),
+    .RX_PROGDIV_CFG (0.000000),
+    .RX_PROGDIV_RATE (16'h0001),
+    .RX_RESLOAD_CTRL (4'b0000),
+    .RX_RESLOAD_OVRD (1'b0),
+    .RX_SAMPLE_PERIOD (3'b111),
+    .RX_SIG_VALID_DLY (11),
+    .RX_SUM_DFETAPREP_EN (1'b0),
+    .RX_SUM_IREF_TUNE (4'b0100),
+    .RX_SUM_RESLOAD_CTRL (4'b0011),
+    .RX_SUM_VCMTUNE (4'b0110),
+    .RX_SUM_VCM_OVWR (1'b0),
+    .RX_SUM_VREF_TUNE (3'b100),
+    .RX_TUNE_AFE_OS (2'b00),
+    .RX_VREG_CTRL (3'b101),
+    .RX_VREG_PDB (1'b1),
+    .RX_WIDEMODE_CDR (2'b00),
+    .RX_WIDEMODE_CDR_GEN3 (2'b00),
+    .RX_WIDEMODE_CDR_GEN4 (2'b01),
+    .RX_XCLK_SEL ("RXDES"),
+    .RX_XMODE_SEL (1'b0),
+    .SAMPLE_CLK_PHASE (1'b0),
+    .SAS_12G_MODE (1'b0),
+    .SATA_BURST_SEQ_LEN (4'b1111),
+    .SATA_BURST_VAL (3'b100),
+    .SATA_CPLL_CFG ("VCO_3000MHZ"),
+    .SATA_EIDLE_VAL (3'b100),
+    .SHOW_REALIGN_COMMA ("TRUE"),
+    .SIM_MODE ("FAST"),
+    .SIM_RECEIVER_DETECT_PASS ("TRUE"),
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_TX_EIDLE_DRIVE_LEVEL ("Z"),
+    .SIM_VERSION (1),
+    .SRSTMODE (1'b0),
+    .TAPDLY_SET_TX (2'h0),
+    .TEMPERATURE_PAR (4'b0010),
+    .TERM_RCAL_CFG (15'b100001000010001),
+    .TERM_RCAL_OVRD (3'b000),
+    .TRANS_TIME_RATE (8'h0e),
+    .TST_RSV0 (8'h00),
+    .TST_RSV1 (8'h00),
+    .TXBUF_EN ("TRUE"),
+    .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
+    .TXDLY_CFG (16'h8010),
+    .TXDLY_LCFG (16'h0030),
+    .TXDRVBIAS_N (4'b1010),
+    .TXFIFO_ADDR_CFG ("LOW"),
+    .TXGBOX_FIFO_INIT_RD_ADDR (4),
+    .TXGEARBOX_EN ("FALSE"),
+    .TXOUT_DIV (TX_OUT_DIV),
+    .TXPCSRESET_TIME (5'b00011),
+    .TXPHDLY_CFG0 (16'h6070),
+    .TXPHDLY_CFG1 (16'h000f),
+    .TXPH_CFG (16'h0323),
+    .TXPH_CFG2 (16'h0000),
+    .TXPH_MONITOR_SEL (5'b00000),
+    .TXPI_CFG (16'h0054),
+    .TXPI_CFG0 (2'b00),
+    .TXPI_CFG1 (2'b00),
+    .TXPI_CFG2 (2'b00),
+    .TXPI_CFG3 (1'b0),
+    .TXPI_CFG4 (1'b0),
+    .TXPI_CFG5 (3'b000),
+    .TXPI_GRAY_SEL (1'b0),
+    .TXPI_INVSTROBE_SEL (1'b0),
+    .TXPI_LPM (1'b0),
+    .TXPI_PPM (1'b0),
+    .TXPI_PPMCLK_SEL ("TXUSRCLK2"),
+    .TXPI_PPM_CFG (8'b00000000),
+    .TXPI_SYNFREQ_PPM (3'b001),
+    .TXPI_VREFSEL (1'b0),
+    .TXPMARESET_TIME (5'b00011),
+    .TXREFCLKDIV2_SEL (1'b0),
+    .TXSYNC_MULTILANE (1'b1),
+    .TXSYNC_OVRD (1'b0),
+    .TXSYNC_SKIP_DA (1'b0),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKMUX_EN (1'b1),
+    .TX_DATA_WIDTH (40),
+    .TX_DCC_LOOP_RST_CFG (16'h0004),
+    .TX_DEEMPH0 (6'b000000),
+    .TX_DEEMPH1 (6'b000000),
+    .TX_DEEMPH2 (6'b000000),
+    .TX_DEEMPH3 (6'b000000),
+    .TX_DIVRESET_TIME (5'b00001),
+    .TX_DRIVE_MODE ("DIRECT"),
+    .TX_DRVMUX_CTRL (2),
+    .TX_EIDLE_ASSERT_DELAY (3'b100),
+    .TX_EIDLE_DEASSERT_DELAY (3'b011),
+    .TX_FABINT_USRCLK_FLOP (1'b0),
+    .TX_FIFO_BYP_EN (1'b0),
+    .TX_IDLE_DATA_ZERO (1'b0),
+    .TX_INT_DATAWIDTH (1),
+    .TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
+    .TX_MAINCURSOR_SEL (1'b0),
+    .TX_MARGIN_FULL_0 (7'b1011111),
+    .TX_MARGIN_FULL_1 (7'b1011110),
+    .TX_MARGIN_FULL_2 (7'b1011100),
+    .TX_MARGIN_FULL_3 (7'b1011010),
+    .TX_MARGIN_FULL_4 (7'b1011000),
+    .TX_MARGIN_LOW_0 (7'b1000110),
+    .TX_MARGIN_LOW_1 (7'b1000101),
+    .TX_MARGIN_LOW_2 (7'b1000011),
+    .TX_MARGIN_LOW_3 (7'b1000010),
+    .TX_MARGIN_LOW_4 (7'b1000000),
+    .TX_PHICAL_CFG0 (16'h0000),
+    .TX_PHICAL_CFG1 (16'h7e00),
+    .TX_PHICAL_CFG2 (16'h0201),
+    .TX_PI_BIASSET (1),
+    .TX_PI_IBIAS_MID (2'b00),
+    .TX_PMADATA_OPT (1'b0),
+    .TX_PMA_POWER_SAVE (1'b0),
+    .TX_PMA_RSV0 (16'h0008),
+    .TX_PREDRV_CTRL (2),
+    .TX_PROGCLK_SEL ("PREPI"),
+    .TX_PROGDIV_CFG (0.000000),
+    .TX_PROGDIV_RATE (16'h0001),
+    .TX_QPI_STATUS_EN (1'b0),
+    .TX_RXDETECT_CFG (14'h0032),
+    .TX_RXDETECT_REF (4),
+    .TX_SAMPLE_PERIOD (3'b111),
+    .TX_SARC_LPBK_ENB (1'b0),
+    .TX_SW_MEAS (2'b00),
+    .TX_VREG_CTRL (3'b000),
+    .TX_VREG_PDB (1'b0),
+    .TX_VREG_VREFSEL (2'b00),
+    .TX_XCLK_SEL ("TXOUT"),
+    .USB_BOTH_BURST_IDLE (1'b0),
+    .USB_BURSTMAX_U3WAKE (7'b1111111),
+    .USB_BURSTMIN_U3WAKE (7'b1100011),
+    .USB_CLK_COR_EQ_EN (1'b0),
+    .USB_EXT_CNTL (1'b1),
+    .USB_IDLEMAX_POLLING (10'b1010111011),
+    .USB_IDLEMIN_POLLING (10'b0100101011),
+    .USB_LFPSPING_BURST (9'b000000101),
+    .USB_LFPSPOLLING_BURST (9'b000110001),
+    .USB_LFPSPOLLING_IDLE_MS (9'b000000100),
+    .USB_LFPSU1EXIT_BURST (9'b000011101),
+    .USB_LFPSU2LPEXIT_BURST_MS (9'b001100011),
+    .USB_LFPSU3WAKE_BURST_MS (9'b111110011),
+    .USB_LFPS_TPERIOD (4'b0011),
+    .USB_LFPS_TPERIOD_ACCURATE (1'b1),
+    .USB_MODE (1'b0),
+    .USB_PCIE_ERR_REP_DIS (1'b0),
+    .USB_PING_SATA_MAX_INIT (21),
+    .USB_PING_SATA_MIN_INIT (12),
+    .USB_POLL_SATA_MAX_BURST (8),
+    .USB_POLL_SATA_MIN_BURST (4),
+    .USB_RAW_ELEC (1'b0),
+    .USB_RXIDLE_P0_CTRL (1'b1),
+    .USB_TXIDLE_TUNE_ENABLE (1'b1),
+    .USB_U1_SATA_MAX_WAKE (7),
+    .USB_U1_SATA_MIN_WAKE (4),
+    .USB_U2_SAS_MAX_COM (64),
+    .USB_U2_SAS_MIN_COM (36),
+    .USE_PCS_CLK_PHASE_SEL (1'b0),
+    .Y_ALL_MODE (1'b0)) 
+  i_gthe4_channel (
+    .BUFGTCE (),
+    .BUFGTCEMASK (),
+    .BUFGTDIV (),
+    .BUFGTRESET (),
+    .BUFGTRSTMASK (),
+    .CDRSTEPDIR (1'd0),
+    .CDRSTEPSQ (1'd0),
+    .CDRSTEPSX (1'd0),
+    .CFGRESET (1'd0),
+    .CLKRSVD0 (1'd0),
+    .CLKRSVD1 (1'd0),
+    .CPLLFBCLKLOST (),
+    .CPLLFREQLOCK (1'd0),
+    .CPLLLOCK (cpll_locked_s),
+    .CPLLLOCKDETCLK (up_clk),
+    .CPLLLOCKEN (1'd1),
+    .CPLLPD (1'b0),
+    .CPLLREFCLKLOST (),
+    .CPLLREFCLKSEL (3'b001),
+    .CPLLRESET (up_cpll_rst),
+    .DMONFIFORESET (1'd0),
+    .DMONITORCLK (1'd0),
+    .DMONITOROUT (),
+    .DMONITOROUTCLK (),
+    .DRPADDR (up_addr_int[9:0]),
+    .DRPCLK (up_clk),
+    .DRPDI (up_wdata_int),
+    .DRPDO (up_rdata_s),
+    .DRPEN (up_enb_int),
+    .DRPRDY (up_ready_s),
+    .DRPRST (1'd0),
+    .DRPWE (up_wr_int),
+    .EYESCANDATAERROR (),
+    .EYESCANRESET (1'd0),
+    .EYESCANTRIGGER (1'd0),
+    .FREQOS (1'd0),
+    .GTGREFCLK (1'd0),
+    .GTHRXN (rx_n),
+    .GTHRXP (rx_p),
+    .GTHTXN (tx_n),
+    .GTHTXP (tx_p),
+    .GTNORTHREFCLK0 (1'd0),
+    .GTNORTHREFCLK1 (1'd0),
+    .GTPOWERGOOD (),
+    .GTREFCLK0 (cpll_ref_clk),
+    .GTREFCLK1 (1'd0),
+    .GTREFCLKMONITOR (),
+    .GTRSVD (15'd0),
+    .GTRXRESET (up_rx_rst),
+    .GTRXRESETSEL (1'd0),
+    .GTSOUTHREFCLK0 (1'd0),
+    .GTSOUTHREFCLK1 (1'd0),
+    .GTTXRESET (up_tx_rst),
+    .GTTXRESETSEL (1'd0),
+    .INCPCTRL (1'd0),
+    .LOOPBACK (3'd0),
+    .PCIEEQRXEQADAPTDONE (1'd0),
+    .PCIERATEGEN3 (),
+    .PCIERATEIDLE (),
+    .PCIERATEQPLLPD (),
+    .PCIERATEQPLLRESET (),
+    .PCIERSTIDLE (1'd0),
+    .PCIERSTTXSYNCSTART (1'd0),
+    .PCIESYNCTXSYNCDONE (),
+    .PCIEUSERGEN3RDY (),
+    .PCIEUSERPHYSTATUSRST (),
+    .PCIEUSERRATEDONE (1'd0),
+    .PCIEUSERRATESTART (),
+    .PCSRSVDIN (16'd0),
+    .PCSRSVDOUT (),
+    .PHYSTATUS (),
+    .PINRSRVDAS (),
+    .POWERPRESENT (),
+    .QPLL0CLK (qpll2ch_clk),
+    .QPLL0FREQLOCK (1'd0),
+    .QPLL0REFCLK (qpll2ch_ref_clk),
+    .QPLL1CLK (1'd0),
+    .QPLL1FREQLOCK (1'd0),
+    .QPLL1REFCLK (1'd0),
+    .RESETEXCEPTION (),
+    .RESETOVRD (1'd0),
+    .RX8B10BEN (1'd1),
+    .RXAFECFOKEN (1'b1),
+    .RXBUFRESET (1'd0),
+    .RXBUFSTATUS (),
+    .RXBYTEISALIGNED (),
+    .RXBYTEREALIGN (),
+    .RXCDRFREQRESET (1'd0),
+    .RXCDRHOLD (1'd0),
+    .RXCDRLOCK (),
+    .RXCDROVRDEN (1'd0),
+    .RXCDRPHDONE (),
+    .RXCDRRESET (1'd0),
+    .RXCHANBONDSEQ (),
+    .RXCHANISALIGNED (),
+    .RXCHANREALIGN (),
+    .RXCHBONDEN (1'd0),
+    .RXCHBONDI (5'd0),
+    .RXCHBONDLEVEL (3'd0),
+    .RXCHBONDMASTER (1'd0),
+    .RXCHBONDO (),
+    .RXCHBONDSLAVE (1'd0),
+    .RXCKCALDONE (),
+    .RXCKCALRESET (1'd0),
+    .RXCKCALSTART (7'd0),
+    .RXCLKCORCNT (),
+    .RXCOMINITDET (),
+    .RXCOMMADET (),
+    .RXCOMMADETEN (1'd1),
+    .RXCOMSASDET (),
+    .RXCOMWAKEDET (),
+    .RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
+    .RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
+    .RXCTRL2 (),
+    .RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
+    .RXDATA ({rx_data_open_s, rx_data}),
+    .RXDATAEXTENDRSVD (),
+    .RXDATAVALID (),
+    .RXDFEAGCCTRL (2'b01),
+    .RXDFEAGCHOLD (1'd0),
+    .RXDFEAGCOVRDEN (1'd0),
+    .RXDFECFOKFCNUM (4'b1101),
+    .RXDFECFOKFEN (1'd0),
+    .RXDFECFOKFPULSE (1'd0),
+    .RXDFECFOKHOLD (1'd0),
+    .RXDFECFOKOVREN (1'd0),
+    .RXDFEKHHOLD (1'd0),
+    .RXDFEKHOVRDEN (1'd0),
+    .RXDFELFHOLD (1'd0),
+    .RXDFELFOVRDEN (1'd0),
+    .RXDFELPMRESET (1'd0),
+    .RXDFETAP10HOLD (1'd0),
+    .RXDFETAP10OVRDEN (1'd0),
+    .RXDFETAP11HOLD (1'd0),
+    .RXDFETAP11OVRDEN (1'd0),
+    .RXDFETAP12HOLD (1'd0),
+    .RXDFETAP12OVRDEN (1'd0),
+    .RXDFETAP13HOLD (1'd0),
+    .RXDFETAP13OVRDEN (1'd0),
+    .RXDFETAP14HOLD (1'd0),
+    .RXDFETAP14OVRDEN (1'd0),
+    .RXDFETAP15HOLD (1'd0),
+    .RXDFETAP15OVRDEN (1'd0),
+    .RXDFETAP2HOLD (1'd0),
+    .RXDFETAP2OVRDEN (1'd0),
+    .RXDFETAP3HOLD (1'd0),
+    .RXDFETAP3OVRDEN (1'd0),
+    .RXDFETAP4HOLD (1'd0),
+    .RXDFETAP4OVRDEN (1'd0),
+    .RXDFETAP5HOLD (1'd0),
+    .RXDFETAP5OVRDEN (1'd0),
+    .RXDFETAP6HOLD (1'd0),
+    .RXDFETAP6OVRDEN (1'd0),
+    .RXDFETAP7HOLD (1'd0),
+    .RXDFETAP7OVRDEN (1'd0),
+    .RXDFETAP8HOLD (1'd0),
+    .RXDFETAP8OVRDEN (1'd0),
+    .RXDFETAP9HOLD (1'd0),
+    .RXDFETAP9OVRDEN (1'd0),
+    .RXDFEUTHOLD (1'd0),
+    .RXDFEUTOVRDEN (1'd0),
+    .RXDFEVPHOLD (1'd0),
+    .RXDFEVPOVRDEN (1'd0),
+    .RXDFEXYDEN (1'd1),
+    .RXDLYBYPASS (1'd1),
+    .RXDLYEN (1'd0),
+    .RXDLYOVRDEN (1'd0),
+    .RXDLYSRESET (1'd0),
+    .RXDLYSRESETDONE (),
+    .RXELECIDLE (),
+    .RXELECIDLEMODE (2'b11),
+    .RXEQTRAINING (1'd0),
+    .RXGEARBOXSLIP (1'd0),
+    .RXHEADER (),
+    .RXHEADERVALID (),
+    .RXLATCLK (1'd0),
+    .RXLFPSTRESETDET (),
+    .RXLFPSU2LPEXITDET (),
+    .RXLFPSU3WAKEDET (),
+    .RXLPMEN (up_rx_lpm_dfe_n),
+    .RXLPMGCHOLD (1'd0),
+    .RXLPMGCOVRDEN (1'd0),
+    .RXLPMHFHOLD (1'd0),
+    .RXLPMHFOVRDEN (1'd0),
+    .RXLPMLFHOLD (1'd0),
+    .RXLPMLFKLOVRDEN (1'd0),
+    .RXLPMOSHOLD (1'd0),
+    .RXLPMOSOVRDEN (1'd0),
+    .RXMCOMMAALIGNEN (rx_calign),
+    .RXMONITOROUT (),
+    .RXMONITORSEL (2'd0),
+    .RXOOBRESET (1'd0),
+    .RXOSCALRESET (1'd0),
+    .RXOSHOLD (1'd0),
+    .RXOSINTDONE (),
+    .RXOSINTSTARTED (),
+    .RXOSINTSTROBEDONE (),
+    .RXOSINTSTROBESTARTED (),
+    .RXOSOVRDEN (1'd0),
+    .RXOUTCLK (rx_out_clk_s),
+    .RXOUTCLKFABRIC (),
+    .RXOUTCLKPCS (),
+    .RXOUTCLKSEL (up_rx_out_clk_sel),
+    .RXPCOMMAALIGNEN (rx_calign),
+    .RXPCSRESET (1'd0),
+    .RXPD (2'd0),
+    .RXPHALIGN (1'd0),
+    .RXPHALIGNDONE (),
+    .RXPHALIGNEN (1'd0),
+    .RXPHALIGNERR (),
+    .RXPHDLYPD (1'd1),
+    .RXPHDLYRESET (1'd0),
+    .RXPHOVRDEN (1'd0),
+    .RXPLLCLKSEL (rx_pll_clk_sel_s),
+    .RXPMARESET (1'd0),
+    .RXPMARESETDONE (),
+    .RXPOLARITY (1'd0),
+    .RXPRBSCNTRESET (1'd0),
+    .RXPRBSERR (),
+    .RXPRBSLOCKED (),
+    .RXPRBSSEL (4'd0),
+    .RXPRGDIVRESETDONE (),
+    .RXPROGDIVRESET (1'd0),
+    .RXQPIEN (1'd0),
+    .RXQPISENN (),
+    .RXQPISENP (),
+    .RXRATE (rx_rate_m2),
+    .RXRATEDONE (),
+    .RXRATEMODE (1'd0),
+    .RXRECCLKOUT (),
+    .RXRESETDONE (rx_rst_done_s),
+    .RXSLIDE (1'd0),
+    .RXSLIDERDY (),
+    .RXSLIPDONE (),
+    .RXSLIPOUTCLK (1'd0),
+    .RXSLIPOUTCLKRDY (),
+    .RXSLIPPMA (1'd0),
+    .RXSLIPPMARDY (),
+    .RXSTARTOFSEQ (),
+    .RXSTATUS (),
+    .RXSYNCALLIN (1'd0),
+    .RXSYNCDONE (),
+    .RXSYNCIN (1'd0),
+    .RXSYNCMODE (1'd0),
+    .RXSYNCOUT (),
+    .RXSYSCLKSEL (rx_sys_clk_sel_s),
+    .RXTERMINATION (1'd0),
+    .RXUSERRDY (up_rx_user_ready),
+    .RXUSRCLK (rx_clk),
+    .RXUSRCLK2 (rx_clk),
+    .RXVALID (),
+    .SIGVALIDCLK (1'd0),
+    .TSTIN (20'd0),
+    .TX8B10BBYPASS (8'd0),
+    .TX8B10BEN (1'd1),
+    .TXBUFSTATUS (),
+    .TXCOMFINISH (),
+    .TXCOMINIT (1'd0),
+    .TXCOMSAS (1'd0),
+    .TXCOMWAKE (1'd0),
+    .TXCTRL0 (16'd0),
+    .TXCTRL1 (16'd0),
+    .TXCTRL2 ({4'd0, tx_charisk}),
+    .TXDATA ({96'd0, tx_data}),
+    .TXDATAEXTENDRSVD (8'd0),
+    .TXDCCDONE (),
+    .TXDCCFORCESTART (1'd0),
+    .TXDCCRESET (1'd0),
+    .TXDEEMPH (2'd0),
+    .TXDETECTRX (1'd0),
+    .TXDIFFCTRL (5'b00000),
+    .TXDLYBYPASS (1'd1),
+    .TXDLYEN (1'd0),
+    .TXDLYHOLD (1'd0),
+    .TXDLYOVRDEN (1'd0),
+    .TXDLYSRESET (1'd0),
+    .TXDLYSRESETDONE (),
+    .TXDLYUPDOWN (1'd0),
+    .TXELECIDLE (1'd0),
+    .TXHEADER (6'd0),
+    .TXINHIBIT (1'd0),
+    .TXLATCLK (1'd0),
+    .TXLFPSTRESET (1'd0),
+    .TXLFPSU2LPEXIT (1'd0),
+    .TXLFPSU3WAKE (1'd0),
+    .TXMAINCURSOR (7'b1000000),
+    .TXMARGIN (3'd0),
+    .TXMUXDCDEXHOLD (1'd0),
+    .TXMUXDCDORWREN (1'd0),
+    .TXONESZEROS (1'd0),
+    .TXOUTCLK (tx_out_clk_s),
+    .TXOUTCLKFABRIC (),
+    .TXOUTCLKPCS (),
+    .TXOUTCLKSEL (up_tx_out_clk_sel),
+    .TXPCSRESET (1'd0),
+    .TXPD (2'd0),
+    .TXPDELECIDLEMODE (1'd0),
+    .TXPHALIGN (1'd0),
+    .TXPHALIGNDONE (),
+    .TXPHALIGNEN (1'd0),
+    .TXPHDLYPD (1'd1),
+    .TXPHDLYRESET (1'd0),
+    .TXPHDLYTSTCLK (1'd0),
+    .TXPHINIT (1'd0),
+    .TXPHINITDONE (),
+    .TXPHOVRDEN (1'd0),
+    .TXPIPPMEN (1'd0),
+    .TXPIPPMOVRDEN (1'd0),
+    .TXPIPPMPD (1'd0),
+    .TXPIPPMSEL (1'd0),
+    .TXPIPPMSTEPSIZE (5'd0),
+    .TXPISOPD (1'd0),
+    .TXPLLCLKSEL (tx_pll_clk_sel_s),
+    .TXPMARESET (1'd0),
+    .TXPMARESETDONE (),
+    .TXPOLARITY (1'd0),
+    .TXPOSTCURSOR (5'd0),
+    .TXPRBSFORCEERR (1'd0),
+    .TXPRBSSEL (4'd0),
+    .TXPRECURSOR (5'd0),
+    .TXPRGDIVRESETDONE (),
+    .TXPROGDIVRESET (up_tx_rst),
+    .TXQPIBIASEN (1'd0),
+    .TXQPISENN (),
+    .TXQPISENP (),
+    .TXQPIWEAKPUP (1'd0),
+    .TXRATE (tx_rate_m2),
+    .TXRATEDONE (),
+    .TXRATEMODE (1'd0),
+    .TXRESETDONE (tx_rst_done_s),
+    .TXSEQUENCE (7'd0),
+    .TXSWING (1'd0),
+    .TXSYNCALLIN (1'd0),
+    .TXSYNCDONE (),
+    .TXSYNCIN (1'd0),
+    .TXSYNCMODE (1'd0),
+    .TXSYNCOUT (),
+    .TXSYSCLKSEL (tx_sys_clk_sel_s),
+    .TXUSERRDY (up_tx_user_ready),
+    .TXUSRCLK (tx_clk),
+    .TXUSRCLK2 (tx_clk));
+  end
+  endgenerate
+
 endmodule     
 
 // ***************************************************************************

From 48dd4880a3e3061fea0fc7aab10d70bfee526c44 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 3 Oct 2016 16:11:15 -0400
Subject: [PATCH 560/972] util_adxcvr- ultrascale+ initial commit

---
 library/xilinx/util_adxcvr/util_adxcvr_xcm.v | 176 +++++++++++++++++++
 1 file changed, 176 insertions(+)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
index b627eafcf..fa94f3cdf 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
@@ -322,6 +322,182 @@ module util_adxcvr_xcm #(
   end
   endgenerate
 
+  generate
+  if (XCVR_TYPE == 2) begin
+  GTHE4_COMMON #(
+    .AEN_QPLL0_FBDIV (1'b1),
+    .AEN_QPLL1_FBDIV (1'b1),
+    .AEN_SDM0TOGGLE (1'b0),
+    .AEN_SDM1TOGGLE (1'b0),
+    .A_SDM0TOGGLE (1'b0),
+    .A_SDM1DATA_HIGH (9'b000000000),
+    .A_SDM1DATA_LOW (16'b0000000000000000),
+    .A_SDM1TOGGLE (1'b0),
+    .BIAS_CFG0 (16'h0000),
+    .BIAS_CFG1 (16'h0000),
+    .BIAS_CFG2 (16'h0124),
+    .BIAS_CFG3 (16'h0041),
+    .BIAS_CFG4 (16'h0010),
+    .BIAS_CFG_RSVD (16'h0000),
+    .COMMON_CFG0 (16'h0000),
+    .COMMON_CFG1 (16'h0000),
+    .POR_CFG (16'h0006),
+    .PPF0_CFG (16'h0600),
+    .PPF1_CFG (16'h0600),
+    .QPLL0CLKOUT_RATE ("HALF"),
+    .QPLL0_CFG0 (16'h331c),
+    .QPLL0_CFG1 (16'hd038),
+    .QPLL0_CFG1_G3 (16'hd038),
+    .QPLL0_CFG2 (16'h0fc0),
+    .QPLL0_CFG2_G3 (16'h0fc0),
+    .QPLL0_CFG3 (16'h0120),
+    .QPLL0_CFG4 (16'h0003),
+    .QPLL0_CP (10'b0001111111),
+    .QPLL0_CP_G3 (10'b0000011111),
+    .QPLL0_FBDIV (QPLL_FBDIV),
+    .QPLL0_FBDIV_G3 (160),
+    .QPLL0_INIT_CFG0 (16'h02b2),
+    .QPLL0_INIT_CFG1 (8'h00),
+    .QPLL0_LOCK_CFG (16'h25e8),
+    .QPLL0_LOCK_CFG_G3 (16'h25e8),
+    .QPLL0_LPF (10'b0100110111),
+    .QPLL0_LPF_G3 (10'b0111010101),
+    .QPLL0_PCI_EN (1'b0),
+    .QPLL0_RATE_SW_USE_DRP (1'b1),
+    .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
+    .QPLL0_SDM_CFG0 (16'h0080),
+    .QPLL0_SDM_CFG1 (16'h0000),
+    .QPLL0_SDM_CFG2 (16'h0000),
+    .QPLL1CLKOUT_RATE ("HALF"),
+    .QPLL1_CFG0 (16'h331c),
+    .QPLL1_CFG1 (16'hd038),
+    .QPLL1_CFG1_G3 (16'hd038),
+    .QPLL1_CFG2 (16'h0fc0),
+    .QPLL1_CFG2_G3 (16'h0fc0),
+    .QPLL1_CFG3 (16'h0120),
+    .QPLL1_CFG4 (16'h0003),
+    .QPLL1_CP (10'b1111111111),
+    .QPLL1_CP_G3 (10'b0011111111),
+    .QPLL1_FBDIV (QPLL_FBDIV),
+    .QPLL1_FBDIV_G3 (80),
+    .QPLL1_INIT_CFG0 (16'h02b2),
+    .QPLL1_INIT_CFG1 (8'h00),
+    .QPLL1_LOCK_CFG (16'h25e8),
+    .QPLL1_LOCK_CFG_G3 (16'h25e8),
+    .QPLL1_LPF (10'b0100110101),
+    .QPLL1_LPF_G3 (10'b0111010100),
+    .QPLL1_PCI_EN (1'b0),
+    .QPLL1_RATE_SW_USE_DRP (1'b1),
+    .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
+    .QPLL1_SDM_CFG0 (16'h0080),
+    .QPLL1_SDM_CFG1 (16'h0000),
+    .QPLL1_SDM_CFG2 (16'h0000),
+    .RSVD_ATTR0 (16'h0000),
+    .RSVD_ATTR1 (16'h0000),
+    .RSVD_ATTR2 (16'h0000),
+    .RSVD_ATTR3 (16'h0000),
+    .RXRECCLKOUT0_SEL (2'b00),
+    .RXRECCLKOUT1_SEL (2'b00),
+    .SARC_ENB (1'b0),
+    .SARC_SEL (1'b0),
+    .SDM0INITSEED0_0 (16'b0000000100010001),
+    .SDM0INITSEED0_1 (9'b000010001),
+    .SDM1INITSEED0_0 (16'b0000000100010001),
+    .SDM1INITSEED0_1 (9'b000010001),
+    .SIM_MODE ("FAST"),
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_VERSION (1)) 
+  i_gthe4_common (
+    .BGBYPASSB (1'd1),
+    .BGMONITORENB (1'd1),
+    .BGPDB (1'd1),
+    .BGRCALOVRD (5'b11111),
+    .BGRCALOVRDENB (1'd1),
+    .DRPADDR ({4'd0, up_addr_int}),
+    .DRPCLK (up_clk),
+    .DRPDI (up_wdata_int),
+    .DRPDO (up_rdata_s),
+    .DRPEN (up_enb_int),
+    .DRPRDY (up_ready_s),
+    .DRPWE (up_wr_int),
+    .GTGREFCLK0 (1'd0),
+    .GTGREFCLK1 (1'd0),
+    .GTNORTHREFCLK00 (1'd0),
+    .GTNORTHREFCLK01 (1'd0),
+    .GTNORTHREFCLK10 (1'd0),
+    .GTNORTHREFCLK11 (1'd0),
+    .GTREFCLK00 (qpll_ref_clk),
+    .GTREFCLK01 (1'd0),
+    .GTREFCLK10 (1'd0),
+    .GTREFCLK11 (1'd0),
+    .GTSOUTHREFCLK00 (1'd0),
+    .GTSOUTHREFCLK01 (1'd0),
+    .GTSOUTHREFCLK10 (1'd0),
+    .GTSOUTHREFCLK11 (1'd0),
+    .PCIERATEQPLL0 (3'd0),
+    .PCIERATEQPLL1 (3'd0),
+    .PMARSVD0 (8'd0),
+    .PMARSVD1 (8'd0),
+    .PMARSVDOUT0 (),
+    .PMARSVDOUT1 (),
+    .QPLL0CLKRSVD0 (1'd0),
+    .QPLL0CLKRSVD1 (1'd0),
+    .QPLL0FBCLKLOST (),
+    .QPLL0FBDIV (8'd0),
+    .QPLL0LOCK (qpll2ch_locked),
+    .QPLL0LOCKDETCLK (up_clk),
+    .QPLL0LOCKEN (1'd1),
+    .QPLL0OUTCLK (qpll2ch_clk),
+    .QPLL0OUTREFCLK (qpll2ch_ref_clk),
+    .QPLL0PD (1'd0),
+    .QPLL0REFCLKLOST (),
+    .QPLL0REFCLKSEL (3'b001),
+    .QPLL0RESET (up_qpll_rst),
+    .QPLL1CLKRSVD0 (1'd0),
+    .QPLL1CLKRSVD1 (1'd0),
+    .QPLL1FBCLKLOST (),
+    .QPLL1FBDIV (8'd0),
+    .QPLL1LOCK (),
+    .QPLL1LOCKDETCLK (1'd0),
+    .QPLL1LOCKEN (1'd0),
+    .QPLL1OUTCLK (),
+    .QPLL1OUTREFCLK (),
+    .QPLL1PD (1'd1),
+    .QPLL1REFCLKLOST (),
+    .QPLL1REFCLKSEL (3'b001),
+    .QPLL1RESET (1'd1),
+    .QPLLDMONITOR0 (),
+    .QPLLDMONITOR1 (),
+    .QPLLRSVD1 (8'd0),
+    .QPLLRSVD2 (5'd0),
+    .QPLLRSVD3 (5'd0),
+    .QPLLRSVD4 (8'd0),
+    .RCALENB (1'd1),
+    .REFCLKOUTMONITOR0 (),
+    .REFCLKOUTMONITOR1 (),
+    .RXRECCLK0SEL (),
+    .RXRECCLK1SEL (),
+    .SDM0DATA (25'd0),
+    .SDM0FINALOUT (),
+    .SDM0RESET (1'd0),
+    .SDM0TESTDATA (),
+    .SDM0TOGGLE (1'd0),
+    .SDM0WIDTH (2'd0),
+    .SDM1DATA (25'd0),
+    .SDM1FINALOUT (),
+    .SDM1RESET (1'd0),
+    .SDM1TESTDATA (),
+    .SDM1TOGGLE (1'd0),
+    .SDM1WIDTH (2'd0),
+    .TCONGPI (10'd0),
+    .TCONGPO (),
+    .TCONPOWERUP (1'd0),
+    .TCONRESET (2'd0),
+    .TCONRSVDIN1 (2'd0),
+    .TCONRSVDOUT0 ());
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************

From ddceff2b5c1d999f8d85d701090f5bd37adb14d7 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 4 Oct 2016 16:11:24 +0300
Subject: [PATCH 561/972] axi_usb_fx3: Updated header/footer signature

---
 library/axi_usb_fx3/axi_usb_fx3_core.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/axi_usb_fx3/axi_usb_fx3_core.v b/library/axi_usb_fx3/axi_usb_fx3_core.v
index e8fe956b8..4747553d4 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_core.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_core.v
@@ -496,7 +496,7 @@ module axi_usb_fx3_core (
     if (state_fx32dma == IDLE) begin
       if (fx32dma_sop == 1'b1) begin
         header_pointer <= 8'h4;
-        if (fx32dma_data != 32'hf00ff00f) begin
+        if (fx32dma_data != 32'h0ff00ff0) begin
           error_fx32dma <= 1'b1;
         end else begin
           error_fx32dma <= 1'b0;
@@ -650,7 +650,7 @@ module axi_usb_fx3_core (
         if (dma2fx3_ready == 1'b1) begin
           dma2fx3_counter <= dma2fx3_counter + 4;
           if (dma2fx3_counter >= buffer_size_current - 4) begin
-            dma2fx3_data_reg <= 32'hf00ff00f;
+            dma2fx3_data_reg <= 32'h0ff00ff0;
           end else begin
             case (test_mode_tpg)
               4'h1: dma2fx3_data_reg <= ~dma2fx3_data_reg;
@@ -663,7 +663,7 @@ module axi_usb_fx3_core (
           end
         end
       end else begin
-          dma2fx3_data_reg <= 32'hf00ff00f;
+          dma2fx3_data_reg <= 32'h0ff00ff0;
         if (s_axis_tvalid== 1'b1 && s_axis_tready == 1'b1) begin
           case (s_axis_tkeep)
             1: dma2fx3_counter <= dma2fx3_counter + 1;

From c196b5bf68ee96a3578335512f374259f3f5b128 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 5 Oct 2016 15:50:43 +0300
Subject: [PATCH 562/972] ad6676evb: VC707, fixed system top gpio_bd datawidth

---
 projects/ad6676evb/vc707/system_top.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v
index 160ea710b..80dab57c3 100644
--- a/projects/ad6676evb/vc707/system_top.v
+++ b/projects/ad6676evb/vc707/system_top.v
@@ -240,10 +240,10 @@ module system_top (
               adc_agc3,
               adc_agc4}));
 
-  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
-    .dio_t (gpio_t[14:0]),
-    .dio_i (gpio_o[14:0]),
-    .dio_o (gpio_i[14:0]),
+  ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
+    .dio_t (gpio_t[20:0]),
+    .dio_i (gpio_o[20:0]),
+    .dio_o (gpio_i[20:0]),
     .dio_p (gpio_bd));
 
   system_wrapper i_system_wrapper (

From 1b9d2d434cfed4770fffd887dfe8804a4ff779b8 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 4 Oct 2016 17:18:52 +0300
Subject: [PATCH 563/972] axi_ad9361_tdd: Delete unused register

---
 library/axi_ad9361/axi_ad9361_tdd.v | 2 --
 1 file changed, 2 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index 273129d3d..d0955817f 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -115,8 +115,6 @@ module axi_ad9361_tdd (
   output  [31:0]    up_rdata;
   output            up_rack;
 
-  reg               tdd_slave_synced = 1'b0;
-
   reg               tdd_tx_valid = 1'b0;
   reg               tdd_rx_valid = 1'b0;
 

From bab9b2df0b476886644a64681afec2a97470451c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 5 Oct 2016 12:08:11 +0300
Subject: [PATCH 564/972] daq3/zc706: Update project with the new transceiver
 modules

---
 projects/daq3/common/daq3_bd.tcl      | 143 ++++++++------------------
 projects/daq3/zc706/system_bd.tcl     |  10 +-
 projects/daq3/zc706/system_constr.xdc |  78 +++++++-------
 projects/daq3/zc706/system_top.v      |  32 ++++--
 4 files changed, 109 insertions(+), 154 deletions(-)

diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl
index d8d7dc6be..35ded3e5f 100644
--- a/projects/daq3/common/daq3_bd.tcl
+++ b/projects/daq3/common/daq3_bd.tcl
@@ -1,20 +1,13 @@
 
-# daq3
-
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir I rx_sysref
-create_bd_port -dir I -from 3 -to 0 rx_data_p
-create_bd_port -dir I -from 3 -to 0 rx_data_n
-
-create_bd_port -dir I tx_ref_clk
-create_bd_port -dir I tx_sync
-create_bd_port -dir I tx_sysref
-create_bd_port -dir O -from 3 -to 0 tx_data_p
-create_bd_port -dir O -from 3 -to 0 tx_data_n
-
 # dac peripherals
 
+set axi_ad9152_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9152_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9152_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9152_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9152_xcvr
+
+set sys_ad9152_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9152_rstgen]
+
 set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
 
 set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9152_jesd]
@@ -39,6 +32,13 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack
 
 # adc peripherals
 
+set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
+
+set sys_ad9680_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9680_rstgen]
+
 set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
 
 set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
@@ -62,85 +62,32 @@ set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
 
-# dac/adc common gt
+# shared transceiver core
 
-set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq3_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq3_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq3_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq3_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt
-set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq3_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq3_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq3_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq3_gt
+set util_daq3_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq3_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_xcvr
 
-set util_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq3_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq3_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq3_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq3_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq3_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_gt
-set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq3_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_gt
-
-# connections (gt)
-
-ad_connect  util_daq3_gt/qpll_ref_clk rx_ref_clk
-ad_connect  util_daq3_gt/cpll_ref_clk tx_ref_clk
-
-ad_connect  axi_daq3_gt/gt_qpll_0 util_daq3_gt/gt_qpll_0
-ad_connect  axi_daq3_gt/gt_pll_0 util_daq3_gt/gt_pll_0
-ad_connect  axi_daq3_gt/gt_pll_1 util_daq3_gt/gt_pll_1
-ad_connect  axi_daq3_gt/gt_pll_2 util_daq3_gt/gt_pll_2
-ad_connect  axi_daq3_gt/gt_pll_3 util_daq3_gt/gt_pll_3
-ad_connect  axi_daq3_gt/gt_rx_0 util_daq3_gt/gt_rx_0
-ad_connect  axi_daq3_gt/gt_rx_1 util_daq3_gt/gt_rx_1
-ad_connect  axi_daq3_gt/gt_rx_2 util_daq3_gt/gt_rx_2
-ad_connect  axi_daq3_gt/gt_rx_3 util_daq3_gt/gt_rx_3
-ad_connect  axi_daq3_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
-ad_connect  axi_daq3_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
-ad_connect  axi_daq3_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
-ad_connect  axi_daq3_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
-ad_connect  axi_daq3_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq3_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq3_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq3_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_daq3_gt/gt_tx_0 util_daq3_gt/gt_tx_0
-ad_connect  axi_daq3_gt/gt_tx_1 util_daq3_gt/gt_tx_1
-ad_connect  axi_daq3_gt/gt_tx_2 util_daq3_gt/gt_tx_2
-ad_connect  axi_daq3_gt/gt_tx_3 util_daq3_gt/gt_tx_3
-ad_connect  axi_daq3_gt/gt_tx_ip_0 axi_ad9152_jesd/gt0_tx
-ad_connect  axi_daq3_gt/gt_tx_ip_1 axi_ad9152_jesd/gt1_tx
-ad_connect  axi_daq3_gt/gt_tx_ip_2 axi_ad9152_jesd/gt2_tx
-ad_connect  axi_daq3_gt/gt_tx_ip_3 axi_ad9152_jesd/gt3_tx
+ad_connect  sys_cpu_resetn util_daq3_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_daq3_xcvr/up_clk
 
 # connections (dac)
 
-ad_connect  util_daq3_gt/tx_sysref tx_sysref
-ad_connect  util_daq3_gt/tx_p tx_data_p
-ad_connect  util_daq3_gt/tx_n tx_data_n
-ad_connect  util_daq3_gt/tx_sync tx_sync
-ad_connect  util_daq3_gt/tx_out_clk util_daq3_gt/tx_clk
-ad_connect  util_daq3_gt/tx_out_clk axi_ad9152_jesd/tx_core_clk
-ad_connect  util_daq3_gt/tx_ip_rst axi_ad9152_jesd/tx_reset
-ad_connect  util_daq3_gt/tx_ip_rst_done axi_ad9152_jesd/tx_reset_done
-ad_connect  util_daq3_gt/tx_ip_sysref axi_ad9152_jesd/tx_sysref
-ad_connect  util_daq3_gt/tx_ip_sync axi_ad9152_jesd/tx_sync
-ad_connect  util_daq3_gt/tx_ip_data axi_ad9152_jesd/tx_tdata
-ad_connect  util_daq3_gt/tx_out_clk axi_ad9152_core/tx_clk
-ad_connect  util_daq3_gt/tx_data axi_ad9152_core/tx_data
-ad_connect  util_daq3_gt/tx_out_clk axi_ad9152_upack/dac_clk
+ad_xcvrcon  util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd
+ad_connect  util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk
+ad_connect  axi_ad9152_jesd/tx_tdata axi_ad9152_core/tx_data
+ad_connect  util_daq3_xcvr/tx_out_clk_0 sys_ad9152_rstgen/slowest_sync_clk
+ad_connect  util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
+ad_connect  util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk
 ad_connect  axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0
 ad_connect  axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0
 ad_connect  axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0
 ad_connect  axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1
 ad_connect  axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1
 ad_connect  axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1
-ad_connect  util_daq3_gt/tx_out_clk axi_ad9152_fifo/dac_clk
 ad_connect  axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid
 ad_connect  axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data
+ad_connect  axi_ad9152_upack/dma_xfer_in axi_ad9152_fifo/dac_xfer_out
 ad_connect  sys_cpu_clk axi_ad9152_fifo/dma_clk
 ad_connect  sys_cpu_reset axi_ad9152_fifo/dma_rst
 ad_connect  sys_cpu_clk axi_ad9152_dma/m_axis_aclk
@@ -153,30 +100,21 @@ ad_connect  axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last
 
 # connections (adc)
 
-ad_connect  util_daq3_gt/rx_sysref rx_sysref
-ad_connect  util_daq3_gt/rx_p rx_data_p
-ad_connect  util_daq3_gt/rx_n rx_data_n
-ad_connect  util_daq3_gt/rx_sync rx_sync
-ad_connect  util_daq3_gt/rx_out_clk util_daq3_gt/rx_clk
-ad_connect  util_daq3_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
-ad_connect  util_daq3_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
-ad_connect  util_daq3_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
-ad_connect  util_daq3_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
-ad_connect  util_daq3_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
-ad_connect  util_daq3_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
-ad_connect  util_daq3_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
-ad_connect  util_daq3_gt/rx_out_clk axi_ad9680_core/rx_clk
-ad_connect  util_daq3_gt/rx_data axi_ad9680_core/rx_data
-ad_connect  util_daq3_gt/rx_out_clk axi_ad9680_cpack/adc_clk
-ad_connect  util_daq3_gt/rx_rst axi_ad9680_cpack/adc_rst
+ad_xcvrcon  util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd
+ad_connect  util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
+ad_connect  axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
+ad_connect  axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
+ad_connect  util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
+ad_connect  util_daq3_xcvr/tx_out_clk_0 sys_ad9680_rstgen/slowest_sync_clk
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
+ad_connect  util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
+ad_connect  sys_ad9680_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
 ad_connect  axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
 ad_connect  axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
 ad_connect  axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
 ad_connect  axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
 ad_connect  axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
 ad_connect  axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
-ad_connect  util_daq3_gt/rx_out_clk axi_ad9680_fifo/adc_clk
-ad_connect  util_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst
 ad_connect  axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
 ad_connect  axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
 ad_connect  sys_cpu_clk axi_ad9680_fifo/dma_clk
@@ -190,10 +128,11 @@ ad_connect  axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_daq3_gt
+ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr
 ad_cpu_interconnect 0x44A00000 axi_ad9152_core
 ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9152_dma
+ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
 ad_cpu_interconnect 0x44A10000 axi_ad9680_core
 ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
@@ -201,7 +140,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
 # gt uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_daq3_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
 
 # interconnect (mem/dac)
 
@@ -215,3 +154,7 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
 ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq
 ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
 
+# unused
+
+ad_connect  axi_ad9152_fifo/dac_fifo_bypass GND
+
diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl
index 8b2be9f57..1c2f1794c 100644
--- a/projects/daq3/zc706/system_bd.tcl
+++ b/projects/daq3/zc706/system_bd.tcl
@@ -39,14 +39,14 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
 set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
 set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
 
-ad_connect  util_daq3_gt/rx_rst mfifo_adc/din_rst
-ad_connect  util_daq3_gt/rx_out_clk mfifo_adc/din_clk
+ad_connect  util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/din_rst
+ad_connect  util_daq3_xcvr/rx_out_clk_0 mfifo_adc/din_clk
 ad_connect  axi_ad9680_core/adc_valid_0 mfifo_adc/din_valid
 ad_connect  axi_ad9680_core/adc_data_0 mfifo_adc/din_data_0
 ad_connect  axi_ad9680_core/adc_data_1 mfifo_adc/din_data_1
-ad_connect  util_daq3_gt/rx_rst mfifo_adc/dout_rst
-ad_connect  util_daq3_gt/rx_out_clk mfifo_adc/dout_clk
-ad_connect  util_daq3_gt/rx_out_clk ila_adc/clk
+ad_connect  util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/dout_rst
+ad_connect  util_daq3_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
+ad_connect  util_daq3_xcvr/rx_out_clk_0 ila_adc/clk
 ad_connect  mfifo_adc/dout_valid ila_adc/probe0
 ad_connect  mfifo_adc/dout_data_0 ila_adc/probe1
 ad_connect  mfifo_adc/dout_data_1 ila_adc/probe2
diff --git a/projects/daq3/zc706/system_constr.xdc b/projects/daq3/zc706/system_constr.xdc
index fd45dcf08..3728fe6f9 100644
--- a/projects/daq3/zc706/system_constr.xdc
+++ b/projects/daq3/zc706/system_constr.xdc
@@ -1,21 +1,21 @@
 
-set_property  -dict {PACKAGE_PIN  AA8 } [get_ports rx_ref_clk_p]                                      ; ## B20  FMC_HPC_GBTCLK1_M2C_P     
-set_property  -dict {PACKAGE_PIN  AA7 } [get_ports rx_ref_clk_n]                                      ; ## B21  FMC_HPC_GBTCLK1_M2C_N     
-set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[0]]                                      ; ## A10  FMC_HPC_DP3_M2C_P         
-set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[0]]                                      ; ## A11  FMC_HPC_DP3_M2C_N         
-set_property  -dict {PACKAGE_PIN  AH10} [get_ports rx_data_p[1]]                                      ; ## C06  FMC_HPC_DP0_M2C_P         
-set_property  -dict {PACKAGE_PIN  AH9 } [get_ports rx_data_n[1]]                                      ; ## C07  FMC_HPC_DP0_M2C_N         
-set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[2]]                                      ; ## A06  FMC_HPC_DP2_M2C_P         
-set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[2]]                                      ; ## A07  FMC_HPC_DP2_M2C_N         
-set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[3]]                                      ; ## A02  FMC_HPC_DP1_M2C_P         
-set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[3]]                                      ; ## A03  FMC_HPC_DP1_M2C_N         
-set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## D08  FMC_HPC_LA01_CC_P         
-set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## D09  FMC_HPC_LA01_CC_N         
-set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]    ; ## G09  FMC_HPC_LA03_P            
-set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]    ; ## G10  FMC_HPC_LA03_N            
+set_property  -dict {PACKAGE_PIN  AA8 } [get_ports rx_ref_clk_p]                                      ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  AA7 } [get_ports rx_ref_clk_n]                                      ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[0]]                                      ; ## A10  FMC_HPC_DP3_M2C_P
+set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[0]]                                      ; ## A11  FMC_HPC_DP3_M2C_N
+set_property  -dict {PACKAGE_PIN  AH10} [get_ports rx_data_p[1]]                                      ; ## C06  FMC_HPC_DP0_M2C_P
+set_property  -dict {PACKAGE_PIN  AH9 } [get_ports rx_data_n[1]]                                      ; ## C07  FMC_HPC_DP0_M2C_N
+set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[2]]                                      ; ## A06  FMC_HPC_DP2_M2C_P
+set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[2]]                                      ; ## A07  FMC_HPC_DP2_M2C_N
+set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[3]]                                      ; ## A02  FMC_HPC_DP1_M2C_P
+set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[3]]                                      ; ## A03  FMC_HPC_DP1_M2C_N
+set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## D08  FMC_HPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## D09  FMC_HPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]    ; ## G09  FMC_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]    ; ## G10  FMC_HPC_LA03_N
 
-set_property  -dict {PACKAGE_PIN  AD10} [get_ports tx_ref_clk_p]                                      ; ## D04  FMC_HPC_GBTCLK0_M2C_P     
-set_property  -dict {PACKAGE_PIN  AD9 } [get_ports tx_ref_clk_n]                                      ; ## D05  FMC_HPC_GBTCLK0_M2C_N     
+set_property  -dict {PACKAGE_PIN  AD10} [get_ports tx_ref_clk_p]                                      ; ## D04  FMC_HPC_GBTCLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  AD9 } [get_ports tx_ref_clk_n]                                      ; ## D05  FMC_HPC_GBTCLK0_M2C_N
 set_property  -dict {PACKAGE_PIN  AK2 } [get_ports tx_data_p[0]]                                      ; ## A30  FMC_HPC_DP3_C2M_P  (tx_data_p[0])
 set_property  -dict {PACKAGE_PIN  AK1 } [get_ports tx_data_n[0]]                                      ; ## A31  FMC_HPC_DP3_C2M_N  (tx_data_n[0])
 set_property  -dict {PACKAGE_PIN  AK10} [get_ports tx_data_p[1]]                                      ; ## C02  FMC_HPC_DP0_C2M_P  (tx_data_p[3])
@@ -24,36 +24,36 @@ set_property  -dict {PACKAGE_PIN  AJ4 } [get_ports tx_data_p[2]]
 set_property  -dict {PACKAGE_PIN  AJ3 } [get_ports tx_data_n[2]]                                      ; ## A27  FMC_HPC_DP2_C2M_N  (tx_data_n[1])
 set_property  -dict {PACKAGE_PIN  AK6 } [get_ports tx_data_p[3]]                                      ; ## A22  FMC_HPC_DP1_C2M_P  (tx_data_p[2])
 set_property  -dict {PACKAGE_PIN  AK5 } [get_ports tx_data_n[3]]                                      ; ## A23  FMC_HPC_DP1_C2M_N  (tx_data_n[2])
-set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p]      ; ## H07  FMC_HPC_LA02_P            
-set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n]      ; ## H08  FMC_HPC_LA02_N            
-set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p]    ; ## H10  FMC_HPC_LA04_P            
-set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n]    ; ## H11  FMC_HPC_LA04_N            
+set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p]      ; ## H07  FMC_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n]      ; ## H08  FMC_HPC_LA02_N
+set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p]    ; ## H10  FMC_HPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n]    ; ## H11  FMC_HPC_LA04_N
 
-set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVCMOS25} [get_ports spi_csn_clk]                  ; ## D11  FMC_HPC_LA05_P            
-set_property  -dict {PACKAGE_PIN  AG24  IOSTANDARD LVCMOS25} [get_ports spi_csn_dac]                  ; ## C14  FMC_HPC_LA10_P            
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports spi_csn_adc]                  ; ## D15  FMC_HPC_LA09_N            
-set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## D12  FMC_HPC_LA05_N            
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS25} [get_ports spi_sdio]                     ; ## D14  FMC_HPC_LA09_P            
-set_property  -dict {PACKAGE_PIN  AH22  IOSTANDARD LVCMOS25} [get_ports spi_dir]                      ; ## C11  FMC_HPC_LA06_N            
+set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVCMOS25} [get_ports spi_csn_clk]                  ; ## D11  FMC_HPC_LA05_P
+set_property  -dict {PACKAGE_PIN  AG24  IOSTANDARD LVCMOS25} [get_ports spi_csn_dac]                  ; ## C14  FMC_HPC_LA10_P
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports spi_csn_adc]                  ; ## D15  FMC_HPC_LA09_N
+set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## D12  FMC_HPC_LA05_N
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS25} [get_ports spi_sdio]                     ; ## D14  FMC_HPC_LA09_P
+set_property  -dict {PACKAGE_PIN  AH22  IOSTANDARD LVCMOS25} [get_ports spi_dir]                      ; ## C11  FMC_HPC_LA06_N
 
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVDS_25}  [get_ports sysref_p]                     ; ## D17  FMC_HPC_LA13_P            
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVDS_25}  [get_ports sysref_n]                     ; ## D18  FMC_HPC_LA13_N            
-set_property  -dict {PACKAGE_PIN  AF24  IOSTANDARD LVCMOS25} [get_ports dac_txen]                     ; ## G16  FMC_HPC_LA12_N            
-set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports adc_pd]                       ; ## C10  FMC_HPC_LA06_P            
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVDS_25}  [get_ports sysref_p]                     ; ## D17  FMC_HPC_LA13_P
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVDS_25}  [get_ports sysref_n]                     ; ## D18  FMC_HPC_LA13_N
+set_property  -dict {PACKAGE_PIN  AF24  IOSTANDARD LVCMOS25} [get_ports dac_txen]                     ; ## G16  FMC_HPC_LA12_N
+set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports adc_pd]                       ; ## C10  FMC_HPC_LA06_P
 
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports clkd_status[0]]               ; ## G12  FMC_HPC_LA08_P            
-set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVCMOS25} [get_ports clkd_status[1]]               ; ## G13  FMC_HPC_LA08_N            
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports dac_irq]                      ; ## G15  FMC_HPC_LA12_P            
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports adc_fda]                      ; ## H16  FMC_HPC_LA11_P            
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports adc_fdb]                      ; ## H17  FMC_HPC_LA11_N            
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports clkd_status[0]]               ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVCMOS25} [get_ports clkd_status[1]]               ; ## G13  FMC_HPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports dac_irq]                      ; ## G15  FMC_HPC_LA12_P
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports adc_fda]                      ; ## H16  FMC_HPC_LA11_P
+set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports adc_fdb]                      ; ## H17  FMC_HPC_LA11_N
 
-set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p]         ; ## H13  FMC_HPC_LA07_P            
-set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n]         ; ## H14  FMC_HPC_LA07_N            
+set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p]         ; ## H13  FMC_HPC_LA07_P
+set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n]         ; ## H14  FMC_HPC_LA07_N
 
 # clocks
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v
index 1bec5296e..6273a25a0 100644
--- a/projects/daq3/zc706/system_top.v
+++ b/projects/daq3/zc706/system_top.v
@@ -390,11 +390,17 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),
@@ -417,11 +423,17 @@ module system_top (
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref));
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (tx_sysref));
 
 endmodule
 

From 4f587d2e48760c41f27d17bec9fea147e78f35d7 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 5 Oct 2016 13:51:39 +0300
Subject: [PATCH 565/972] util_adxcvr: Delete trailing whitespaces

---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 26 ++++++++++----------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index b74f917cc..5c9dbca23 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -336,7 +336,7 @@ module util_adxcvr_xch #(
   if (XCVR_TYPE == 0) begin
   GTXE2_CHANNEL #(
     .SIM_RECEIVER_DETECT_PASS ("TRUE"),
-    .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), 
+    .SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
     .SIM_RESET_SPEEDUP ("TRUE"),
     .SIM_CPLLREFCLK_SEL (3'b001),
     .SIM_VERSION ("3.0"),
@@ -1163,11 +1163,11 @@ module util_adxcvr_xch #(
     .TX_RXDETECT_CFG (14'b00000000110010),
     .TX_RXDETECT_REF (3'b100),
     .TX_SAMPLE_PERIOD (3'b101),
-    .TX_SARC_LPBK_ENB (1'b0),                   
-    .TX_XCLK_SEL ("TXOUT"),                     
-    .USE_PCS_CLK_PHASE_SEL (1'b0),              
-    .WB_MODE (2'b00))                                                                        
-  i_gthe3_channel (                                                            
+    .TX_SARC_LPBK_ENB (1'b0),
+    .TX_XCLK_SEL ("TXOUT"),
+    .USE_PCS_CLK_PHASE_SEL (1'b0),
+    .WB_MODE (2'b00))
+  i_gthe3_channel (
     .CFGRESET (1'd0),
     .CLKRSVD0 (1'd0),
     .CLKRSVD1 (1'd0),
@@ -2013,7 +2013,7 @@ module util_adxcvr_xch #(
     .USB_U2_SAS_MAX_COM (64),
     .USB_U2_SAS_MIN_COM (36),
     .USE_PCS_CLK_PHASE_SEL (1'b0),
-    .Y_ALL_MODE (1'b0)) 
+    .Y_ALL_MODE (1'b0))
   i_gthe4_channel (
     .BUFGTCE (),
     .BUFGTCEMASK (),
@@ -2359,7 +2359,7 @@ module util_adxcvr_xch #(
   end
   endgenerate
 
-endmodule     
+endmodule
 
 // ***************************************************************************
 // ***************************************************************************

From 7ec93ce8e0d7ea9d3b2fd16b162c1e48735abb94 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 5 Oct 2016 13:52:09 +0300
Subject: [PATCH 566/972] util_adxcvr: Fix some typo

GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 5c9dbca23..e35a4438a 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -1501,7 +1501,7 @@ module util_adxcvr_xch #(
   endgenerate
 
   generate
-  if (XCVR_TYPE == 1) begin
+  if (XCVR_TYPE == 2) begin
   assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
   assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
   assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
@@ -1510,7 +1510,7 @@ module util_adxcvr_xch #(
   endgenerate
 
   generate
-  if (XCVR_TYPE == 1) begin
+  if (XCVR_TYPE == 2) begin
   GTHE4_CHANNEL #(
     .ACJTAG_DEBUG_MODE (1'b0),
     .ACJTAG_MODE (1'b0),

From 39fdf11ef3783d6f063e6882d416902df0a85611 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 5 Oct 2016 13:53:02 -0400
Subject: [PATCH 567/972] util_adxcvr- rx/tx clocks

---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 66 +++++++++++++-------
 1 file changed, 44 insertions(+), 22 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index e35a4438a..39c323af2 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -301,28 +301,6 @@ module util_adxcvr_xch #(
   end
   endgenerate
 
-  generate
-  if (XCVR_TYPE == 1) begin
-  BUFG_GT i_rx_bufg (
-    .CE (1'b1),
-    .CEMASK (1'b0),
-    .CLR (1'b0),
-    .CLRMASK (1'b0),
-    .DIV (3'd0),
-    .I (rx_out_clk_s),
-    .O (rx_out_clk));
-
-  BUFG_GT i_tx_bufg (
-    .CE (1'b1),
-    .CEMASK (1'b0),
-    .CLR (1'b0),
-    .CLRMASK (1'b0),
-    .DIV (3'd0),
-    .I (tx_out_clk_s),
-    .O (tx_out_clk));
-  end
-  endgenerate
-
   generate
   if (XCVR_TYPE == 0) begin
   assign rx_sys_clk_sel_s = up_rx_sys_clk_sel;
@@ -768,6 +746,28 @@ module util_adxcvr_xch #(
   end
   endgenerate
 
+  generate
+  if (XCVR_TYPE == 1) begin
+  BUFG_GT i_rx_bufg (
+    .CE (1'b1),
+    .CEMASK (1'b0),
+    .CLR (1'b0),
+    .CLRMASK (1'b0),
+    .DIV (3'd0),
+    .I (rx_out_clk_s),
+    .O (rx_out_clk));
+
+  BUFG_GT i_tx_bufg (
+    .CE (1'b1),
+    .CEMASK (1'b0),
+    .CLR (1'b0),
+    .CLRMASK (1'b0),
+    .DIV (3'd0),
+    .I (tx_out_clk_s),
+    .O (tx_out_clk));
+  end
+  endgenerate
+
   generate
   if (XCVR_TYPE == 1) begin
   assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
@@ -1500,6 +1500,28 @@ module util_adxcvr_xch #(
   end
   endgenerate
 
+  generate
+  if (XCVR_TYPE == 2) begin
+  BUFG_GT i_rx_bufg (
+    .CE (1'b1),
+    .CEMASK (1'b0),
+    .CLR (1'b0),
+    .CLRMASK (1'b0),
+    .DIV (3'd0),
+    .I (rx_out_clk_s),
+    .O (rx_out_clk));
+
+  BUFG_GT i_tx_bufg (
+    .CE (1'b1),
+    .CEMASK (1'b0),
+    .CLR (1'b0),
+    .CLRMASK (1'b0),
+    .DIV (3'd0),
+    .I (tx_out_clk_s),
+    .O (tx_out_clk));
+  end
+  endgenerate
+
   generate
   if (XCVR_TYPE == 2) begin
   assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;

From baabe207660c7d6ee34c7d6241fd12c257bc80a5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 5 Oct 2016 14:01:59 -0400
Subject: [PATCH 568/972] common/zcu102- spi connections & clock

---
 projects/common/zcu102/zcu102_system_bd.tcl | 35 +++++++++++----------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/projects/common/zcu102/zcu102_system_bd.tcl b/projects/common/zcu102/zcu102_system_bd.tcl
index 3cea2924f..c010ea941 100644
--- a/projects/common/zcu102/zcu102_system_bd.tcl
+++ b/projects/common/zcu102/zcu102_system_bd.tcl
@@ -12,8 +12,8 @@ create_bd_port -dir O spi1_sclk
 create_bd_port -dir O spi1_mosi
 create_bd_port -dir I spi1_miso
 
-create_bd_port -dir I -from 95 -to 0 gpio_i
-create_bd_port -dir O -from 95 -to 0 gpio_o
+create_bd_port -dir I -from 94 -to 0 gpio_i
+create_bd_port -dir O -from 94 -to 0 gpio_o
 
 # interrupts
 
@@ -2459,6 +2459,11 @@ set_property -dict [list\
   CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \
 ] $sys_ps8
 
+set_property -dict [list\
+  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \
+  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \
+] $sys_ps8
+
 set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
 set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
 
@@ -2478,23 +2483,21 @@ ad_connect  gpio_o sys_ps8/emio_gpio_o
 
 # spi
 
+ad_connect  sys_ps8/emio_spi0_ss_o_n spi0_csn
+ad_connect  sys_ps8/emio_spi0_sclk_o spi0_sclk
+ad_connect  sys_ps8/emio_spi0_m_o spi0_mosi
+ad_connect  sys_ps8/emio_spi0_m_i spi0_miso
 ad_connect  sys_ps8/emio_spi0_ss_i_n VCC
-ad_connect  sys_ps8/emio_spi0_sclk_i sys_ps8/emio_spi0_sclk_o
-ad_connect  sys_ps8/emio_spi0_m_i sys_ps8/emio_spi0_m_o
-
-ad_connect  spi0_csn sys_ps8/emio_spi0_ss_o_n
-ad_connect  spi0_sclk sys_ps8/emio_spi0_sclk_o
-ad_connect  spi0_mosi sys_ps8/emio_spi0_m_o
-ad_connect  spi0_miso sys_ps8/emio_spi0_s_i
+ad_connect  sys_ps8/emio_spi0_sclk_i GND
+ad_connect  sys_ps8/emio_spi0_s_i GND
 
+ad_connect  sys_ps8/emio_spi1_ss_o_n spi1_csn
+ad_connect  sys_ps8/emio_spi1_sclk_o spi1_sclk
+ad_connect  sys_ps8/emio_spi1_m_o spi1_mosi
+ad_connect  sys_ps8/emio_spi1_m_i spi1_miso
 ad_connect  sys_ps8/emio_spi1_ss_i_n VCC
-ad_connect  sys_ps8/emio_spi1_sclk_i sys_ps8/emio_spi1_sclk_o
-ad_connect  sys_ps8/emio_spi1_m_i sys_ps8/emio_spi1_m_o
-
-ad_connect  spi1_csn sys_ps8/emio_spi1_ss_o_n
-ad_connect  spi1_sclk sys_ps8/emio_spi1_sclk_o
-ad_connect  spi1_mosi sys_ps8/emio_spi1_m_o
-ad_connect  spi1_miso sys_ps8/emio_spi1_s_i
+ad_connect  sys_ps8/emio_spi1_sclk_i GND
+ad_connect  sys_ps8/emio_spi1_s_i GND
 
 # interrupts
 

From ca4dca87e2c21c0e22d10eaa6fe4869d601021a5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 5 Oct 2016 14:02:59 -0400
Subject: [PATCH 569/972] daq2- updates

---
 projects/daq2/zcu102/system_bd.tcl     |   3 +-
 projects/daq2/zcu102/system_constr.xdc |  14 +-
 projects/daq2/zcu102/system_top.v      | 308 +++++++------------------
 3 files changed, 87 insertions(+), 238 deletions(-)

diff --git a/projects/daq2/zcu102/system_bd.tcl b/projects/daq2/zcu102/system_bd.tcl
index 735376cdc..84f00d318 100644
--- a/projects/daq2/zcu102/system_bd.tcl
+++ b/projects/daq2/zcu102/system_bd.tcl
@@ -8,8 +8,7 @@ p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
 
 source ../common/daq2_bd.tcl
 
-set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $util_daq2_xcvr
+set_property -dict [list CONFIG.XCVR_TYPE {2}] $util_daq2_xcvr
 set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq2_xcvr
 set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq2_xcvr
 
-
diff --git a/projects/daq2/zcu102/system_constr.xdc b/projects/daq2/zcu102/system_constr.xdc
index a898a2bf5..96dcf2313 100644
--- a/projects/daq2/zcu102/system_constr.xdc
+++ b/projects/daq2/zcu102/system_constr.xdc
@@ -40,8 +40,8 @@ set_property  -dict {PACKAGE_PIN  U4  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [g
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
 
 # gt pin assignments below are for reference only and are ignored by the tool!
 
@@ -62,11 +62,9 @@ create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_
 ##  set_property  -dict {PACKAGE_PIN  H6} [get_ports tx_data_p[3]] ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
 ##  set_property  -dict {PACKAGE_PIN  H5} [get_ports tx_data_n[3]] ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
 
-set_property LOC GTHE4_CHANNEL_X1Y8  [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel}]
-set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_1/i_gthe3_channel}]
-set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}]
-set_property LOC GTHE4_CHANNEL_X1Y9  [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}]
+set_property LOC GTHE4_CHANNEL_X1Y8  [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel}]
+set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_1/i_gthe4_channel}]
+set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe4_channel}]
+set_property LOC GTHE4_CHANNEL_X1Y9  [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe4_channel}]
 
-#set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9144_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
-#set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9680_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
diff --git a/projects/daq2/zcu102/system_top.v b/projects/daq2/zcu102/system_top.v
index 4af3f1aa8..08aced720 100644
--- a/projects/daq2/zcu102/system_top.v
+++ b/projects/daq2/zcu102/system_top.v
@@ -39,166 +39,52 @@
 
 module system_top (
 
-  sys_rst,
-  sys_clk_p,
-  sys_clk_n,
+  input   [12:0]  gpio_bd_i,
+  output  [ 7:0]  gpio_bd_o,
 
-  uart_sin,
-  uart_sout,
+  input           rx_ref_clk_p,
+  input           rx_ref_clk_n,
+  input           rx_sysref_p,
+  input           rx_sysref_n,
+  output          rx_sync_p,
+  output          rx_sync_n,
+  input   [ 3:0]  rx_data_p,
+  input   [ 3:0]  rx_data_n,
 
-  ddr4_act_n,
-  ddr4_addr,
-  ddr4_ba,
-  ddr4_bg,
-  ddr4_ck_p,
-  ddr4_ck_n,
-  ddr4_cke,
-  ddr4_cs_n,
-  ddr4_dm_n,
-  ddr4_dq,
-  ddr4_dqs_p,
-  ddr4_dqs_n,
-  ddr4_odt,
-  ddr4_reset_n,
+  input           tx_ref_clk_p,
+  input           tx_ref_clk_n,
+  input           tx_sysref_p,
+  input           tx_sysref_n,
+  input           tx_sync_p,
+  input           tx_sync_n,
+  output  [ 3:0]  tx_data_p,
+  output  [ 3:0]  tx_data_n,
 
-  mdio_mdc,
-  mdio_mdio,
-  phy_clk_p,
-  phy_clk_n,
-  phy_rst_n,
-  phy_rx_p,
-  phy_rx_n,
-  phy_tx_p,
-  phy_tx_n,
+  input           trig_p,
+  input           trig_n,
 
-  fan_pwm,
+  inout           adc_fdb,
+  inout           adc_fda,
+  inout           dac_irq,
+  inout   [ 1:0]  clkd_status,
 
-  gpio_bd,
+  inout           adc_pd,
+  inout           dac_txen,
+  inout           dac_reset,
+  inout           clkd_sync,
 
-  iic_scl,
-  iic_sda,
-
-  rx_ref_clk_p,
-  rx_ref_clk_n,
-  rx_sysref_p,
-  rx_sysref_n,
-  rx_sync_p,
-  rx_sync_n,
-  rx_data_p,
-  rx_data_n,
-
-  tx_ref_clk_p,
-  tx_ref_clk_n,
-  tx_sysref_p,
-  tx_sysref_n,
-  tx_sync_p,
-  tx_sync_n,
-  tx_data_p,
-  tx_data_n,
-
-  trig_p,
-  trig_n,
-
-  adc_fdb,
-  adc_fda,
-  dac_irq,
-  clkd_status,
-
-  adc_pd,
-  dac_txen,
-  dac_reset,
-  clkd_sync,
-
-  spi_csn_clk,
-  spi_csn_dac,
-  spi_csn_adc,
-  spi_clk,
-  spi_sdio,
-  spi_dir);
-
-  input           sys_rst;
-  input           sys_clk_p;
-  input           sys_clk_n;
-
-  input           uart_sin;
-  output          uart_sout;
-
-  output          ddr4_act_n;
-  output  [16:0]  ddr4_addr;
-  output  [ 1:0]  ddr4_ba;
-  output  [ 0:0]  ddr4_bg;
-  output          ddr4_ck_p;
-  output          ddr4_ck_n;
-  output  [ 0:0]  ddr4_cke;
-  output  [ 0:0]  ddr4_cs_n;
-  inout   [ 7:0]  ddr4_dm_n;
-  inout   [63:0]  ddr4_dq;
-  inout   [ 7:0]  ddr4_dqs_p;
-  inout   [ 7:0]  ddr4_dqs_n;
-  output  [ 0:0]  ddr4_odt;
-  output          ddr4_reset_n;
-
-  output          mdio_mdc;
-  inout           mdio_mdio;
-  input           phy_clk_p;
-  input           phy_clk_n;
-  output          phy_rst_n;
-  input           phy_rx_p;
-  input           phy_rx_n;
-  output          phy_tx_p;
-  output          phy_tx_n;
-
-  output          fan_pwm;
-
-  inout   [16:0]  gpio_bd;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  input           rx_ref_clk_p;
-  input           rx_ref_clk_n;
-  input           rx_sysref_p;
-  input           rx_sysref_n;
-  output          rx_sync_p;
-  output          rx_sync_n;
-  input   [ 3:0]  rx_data_p;
-  input   [ 3:0]  rx_data_n;
-
-  input           tx_ref_clk_p;
-  input           tx_ref_clk_n;
-  input           tx_sysref_p;
-  input           tx_sysref_n;
-  input           tx_sync_p;
-  input           tx_sync_n;
-  output  [ 3:0]  tx_data_p;
-  output  [ 3:0]  tx_data_n;
-
-  input           trig_p;
-  input           trig_n;
-
-  inout           adc_fdb;
-  inout           adc_fda;
-  inout           dac_irq;
-  inout   [ 1:0]  clkd_status;
-
-  inout           adc_pd;
-  inout           dac_txen;
-  inout           dac_reset;
-  inout           clkd_sync;
-
-  output          spi_csn_clk;
-  output          spi_csn_dac;
-  output          spi_csn_adc;
-  output          spi_clk;
-  inout           spi_sdio;
-  output          spi_dir;
+  output          spi_csn_clk,
+  output          spi_csn_dac,
+  output          spi_csn_adc,
+  output          spi_clk,
+  inout           spi_sdio,
+  output          spi_dir);
 
   // internal signals
 
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire    [ 7:0]  spi_csn;
+  wire    [94:0]  gpio_i;
+  wire    [94:0]  gpio_o;
+  wire    [ 2:0]  spi_csn;
   wire            spi_mosi;
   wire            spi_miso;
   wire            trig;
@@ -215,13 +101,9 @@ module system_top (
   assign spi_csn_dac = spi_csn[1];
   assign spi_csn_clk = spi_csn[0];
 
-  // default logic
-
-  assign fan_pwm = 1'b1;
-
   // instantiations
 
-  IBUFDS_GTE3 i_ibufds_rx_ref_clk (
+  IBUFDS_GTE4 i_ibufds_rx_ref_clk (
     .CEB (1'd0),
     .I (rx_ref_clk_p),
     .IB (rx_ref_clk_n),
@@ -238,7 +120,7 @@ module system_top (
     .O (rx_sync_p),
     .OB (rx_sync_n));
 
-  IBUFDS_GTE3 i_ibufds_tx_ref_clk (
+  IBUFDS_GTE4 i_ibufds_tx_ref_clk (
     .CEB (1'd0),
     .I (tx_ref_clk_p),
     .IB (tx_ref_clk_n),
@@ -256,7 +138,7 @@ module system_top (
     .O (tx_sync));
 
   daq2_spi i_spi (
-    .spi_csn (spi_csn[2:0]),
+    .spi_csn (spi_csn),
     .spi_clk (spi_clk),
     .spi_mosi (spi_mosi),
     .spi_miso (spi_miso),
@@ -268,62 +150,40 @@ module system_top (
     .IB (trig_n),
     .O (trig));
 
-  assign gpio_i[43] = trig;
+  assign adc_pd = gpio_o[42];
+  assign dac_txen = gpio_o[41];
+  assign dac_reset = gpio_o[40];
+  assign clkd_sync = gpio_o[38];
+  assign gpio_bd_o = gpio_o[7:0];
 
-  ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
-    .dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
-    .dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
-    .dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
-    .dio_p ({ adc_pd,           // 42
-              dac_txen,         // 41
-              dac_reset,        // 40
-              clkd_sync,        // 38
-              adc_fdb,          // 36
-              adc_fda,          // 35
-              dac_irq,          // 34
-              clkd_status}));   // 32
-
-  ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
-    .dio_t (gpio_t[16:0]),
-    .dio_i (gpio_o[16:0]),
-    .dio_o (gpio_i[16:0]),
-    .dio_p (gpio_bd));
+  assign gpio_i[94:44] = gpio_o[94:44];
+  assign gpio_i[43:43] = trig;
+  assign gpio_i[42:37] = gpio_o[42:37];
+  assign gpio_i[36:36] = adc_fdb;
+  assign gpio_i[35:35] = adc_fda;
+  assign gpio_i[34:34] = dac_irq;
+  assign gpio_i[33:32] = clkd_status;
+  assign gpio_i[31:21] = gpio_o[31:21];
+  assign gpio_i[20: 8] = gpio_bd_i;
+  assign gpio_i[ 7: 0] = gpio_o[7:0];
 
   system_wrapper i_system_wrapper (
-    .c0_ddr4_act_n (ddr4_act_n),
-    .c0_ddr4_adr (ddr4_addr),
-    .c0_ddr4_ba (ddr4_ba),
-    .c0_ddr4_bg (ddr4_bg),
-    .c0_ddr4_ck_c (ddr4_ck_n),
-    .c0_ddr4_ck_t (ddr4_ck_p),
-    .c0_ddr4_cke (ddr4_cke),
-    .c0_ddr4_cs_n (ddr4_cs_n),
-    .c0_ddr4_dm_n (ddr4_dm_n),
-    .c0_ddr4_dq (ddr4_dq),
-    .c0_ddr4_dqs_c (ddr4_dqs_n),
-    .c0_ddr4_dqs_t (ddr4_dqs_p),
-    .c0_ddr4_odt (ddr4_odt),
-    .c0_ddr4_reset_n (ddr4_reset_n),
-    .gpio0_i (gpio_i[31:0]),
-    .gpio0_o (gpio_o[31:0]),
-    .gpio0_t (gpio_t[31:0]),
-    .gpio1_i (gpio_i[63:32]),
-    .gpio1_o (gpio_o[63:32]),
-    .gpio1_t (gpio_t[63:32]),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
-    .mb_intr_05 (1'b0),
-    .mb_intr_06 (1'b0),
-    .mb_intr_07 (1'b0),
-    .mb_intr_08 (1'b0),
-    .mb_intr_14 (1'b0),
-    .mb_intr_15 (1'b0),
-    .mdio_mdc (mdio_mdc),
-    .mdio_mdio_io (mdio_mdio),
-    .phy_clk_clk_n (phy_clk_n),
-    .phy_clk_clk_p (phy_clk_p),
-    .phy_rst_n (phy_rst_n),
-    .phy_sd (1'b1),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .ps_intr_00 (1'd0),
+    .ps_intr_01 (1'd0),
+    .ps_intr_02 (1'd0),
+    .ps_intr_03 (1'd0),
+    .ps_intr_04 (1'd0),
+    .ps_intr_05 (1'd0),
+    .ps_intr_06 (1'd0),
+    .ps_intr_07 (1'd0),
+    .ps_intr_08 (1'd0),
+    .ps_intr_09 (1'd0),
+    .ps_intr_10 (1'd0),
+    .ps_intr_11 (1'd0),
+    .ps_intr_14 (1'd0),
+    .ps_intr_15 (1'd0),
     .rx_data_0_n (rx_data_n[0]),
     .rx_data_0_p (rx_data_p[0]),
     .rx_data_1_n (rx_data_n[1]),
@@ -335,20 +195,14 @@ module system_top (
     .rx_ref_clk (rx_ref_clk),
     .rx_sync (rx_sync),
     .rx_sysref (rx_sysref),
-    .sgmii_rxn (phy_rx_n),
-    .sgmii_rxp (phy_rx_p),
-    .sgmii_txn (phy_tx_n),
-    .sgmii_txp (phy_tx_p),
-    .spi_clk_i (spi_clk),
-    .spi_clk_o (spi_clk),
-    .spi_csn_i (spi_csn),
-    .spi_csn_o (spi_csn),
-    .spi_sdi_i (spi_miso),
-    .spi_sdo_i (spi_mosi),
-    .spi_sdo_o (spi_mosi),
-    .sys_clk_clk_n (sys_clk_n),
-    .sys_clk_clk_p (sys_clk_p),
-    .sys_rst (sys_rst),
+    .spi0_csn (spi_csn),
+    .spi0_miso (spi_miso),
+    .spi0_mosi (spi_mosi),
+    .spi0_sclk (spi_clk),
+    .spi1_csn (),
+    .spi1_miso (1'd0),
+    .spi1_mosi (),
+    .spi1_sclk (),
     .tx_data_0_n (tx_data_n[0]),
     .tx_data_0_p (tx_data_p[0]),
     .tx_data_1_n (tx_data_n[1]),
@@ -359,9 +213,7 @@ module system_top (
     .tx_data_3_p (tx_data_p[3]),
     .tx_ref_clk (tx_ref_clk),
     .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref),
-    .uart_sin (uart_sin),
-    .uart_sout (uart_sout));
+    .tx_sysref (tx_sysref));
 
 endmodule
 

From 58c4abd8af1598d33a3b01ee474c61c47cd29d6e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 6 Oct 2016 10:23:52 +0300
Subject: [PATCH 570/972] daq3/kcu105: Update project to the new GT framework

---
 projects/daq3/kcu105/system_bd.tcl     |  7 +++---
 projects/daq3/kcu105/system_constr.xdc | 16 ++++++-------
 projects/daq3/kcu105/system_top.v      | 32 ++++++++++++++++++--------
 3 files changed, 33 insertions(+), 22 deletions(-)

diff --git a/projects/daq3/kcu105/system_bd.tcl b/projects/daq3/kcu105/system_bd.tcl
index 694fbc6f9..a4f92f78a 100644
--- a/projects/daq3/kcu105/system_bd.tcl
+++ b/projects/daq3/kcu105/system_bd.tcl
@@ -8,8 +8,7 @@ p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
 
 source ../common/daq3_bd.tcl
 
-set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $axi_daq3_gt
-set_property -dict [list CONFIG.QPLL0_FBDIV {20}] $axi_daq3_gt
-set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_daq3_gt
-
+set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq3_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq3_xcvr
+set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq3_xcvr
 
diff --git a/projects/daq3/kcu105/system_constr.xdc b/projects/daq3/kcu105/system_constr.xdc
index 1a8301883..2c97c6270 100644
--- a/projects/daq3/kcu105/system_constr.xdc
+++ b/projects/daq3/kcu105/system_constr.xdc
@@ -33,15 +33,15 @@ set_property  -dict {PACKAGE_PIN  E10 IOSTANDARD LVCMOS18} [get_ports dac_irq]
 set_property  -dict {PACKAGE_PIN  K11 IOSTANDARD LVCMOS18} [get_ports adc_fda]                              ; ## H16  FMC_HPC_LA11_P
 set_property  -dict {PACKAGE_PIN  J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb]                              ; ## H17  FMC_HPC_LA11_N
 
-set_property  -dict {PACKAGE_PIN  F8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p]            ; ## H13  FMC_HPC_LA07_P          
-set_property  -dict {PACKAGE_PIN  E8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n]            ; ## H14  FMC_HPC_LA07_N          
+set_property  -dict {PACKAGE_PIN  F8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p]            ; ## H13  FMC_HPC_LA07_P
+set_property  -dict {PACKAGE_PIN  E8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n]            ; ## H14  FMC_HPC_LA07_N
 
 # clocks
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
 
 # gt pin assignments below are for reference only and are ignored by the tool!
 
@@ -62,8 +62,8 @@ create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_
 ##  set_property  -dict {PACKAGE_PIN  D6} [get_ports tx_data_p[3]] ; ## A22  FMC_HPC_DP1_C2M_P (tx_data_p[2])
 ##  set_property  -dict {PACKAGE_PIN  D5} [get_ports tx_data_n[3]] ; ## A23  FMC_HPC_DP1_C2M_N (tx_data_n[2])
 
-set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *axi_daq3_gt/inst/g_lane_1[1].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *axi_daq3_gt/inst/g_lane_1[2].i_channel/i_gt/i_gthe3_channel}]
-set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *axi_daq3_gt/inst/g_lane_1[3].i_channel/i_gt/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_1/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe3_channel}]
+set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe3_channel}]
 
diff --git a/projects/daq3/kcu105/system_top.v b/projects/daq3/kcu105/system_top.v
index 41b045656..4396a35bf 100644
--- a/projects/daq3/kcu105/system_top.v
+++ b/projects/daq3/kcu105/system_top.v
@@ -329,11 +329,17 @@ module system_top (
     .phy_clk_clk_p (phy_clk_p),
     .phy_rst_n (phy_rst_n),
     .phy_sd (1'b1),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .sgmii_rxn (phy_rx_n),
     .sgmii_rxp (phy_rx_p),
     .sgmii_txn (phy_tx_n),
@@ -348,11 +354,17 @@ module system_top (
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref),
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (tx_sysref),
     .uart_sin (uart_sin),
     .uart_sout (uart_sout));
 

From 9ace02a227a6127686ac11f5575b1560ab5cf9bf Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 6 Oct 2016 10:25:25 +0300
Subject: [PATCH 571/972] daq3/a10gx: Update project to the new GT framework

---
 projects/daq3/a10gx/system_qsys.tcl | 1 -
 projects/daq3/common/daq3_qsys.tcl  | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/projects/daq3/a10gx/system_qsys.tcl b/projects/daq3/a10gx/system_qsys.tcl
index b6503f47a..b2209593e 100644
--- a/projects/daq3/a10gx/system_qsys.tcl
+++ b/projects/daq3/a10gx/system_qsys.tcl
@@ -1,6 +1,5 @@
 
 
-source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/daq3_qsys.tcl
 
diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl
index e428a6a5c..75e3def09 100644
--- a/projects/daq3/common/daq3_qsys.tcl
+++ b/projects/daq3/common/daq3_qsys.tcl
@@ -222,7 +222,7 @@ add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
 add_connection sys_cpu.data_master axi_ad9680_core.s_axi
 
-add_connection xcvr_core.jesd204_rx_link axi_ad9680_core.if_rx_ip_avl
+add_connection xcvr_core.jesd204_rx_link axi_ad9680_core.if_rx_data
 add_connection xcvr_core.rx_sof axi_ad9680_core.if_rx_sof
 
 # ad9680-pack

From 8965bcffb700c28ac002de779c0b22e2f9a2cb19 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 6 Oct 2016 10:27:00 +0300
Subject: [PATCH 572/972] make: Update make files for DAQ3

---
 projects/daq3/a10gx/Makefile  | 17 -----------------
 projects/daq3/kcu105/Makefile | 12 ++++++------
 projects/daq3/zc706/Makefile  | 12 ++++++------
 3 files changed, 12 insertions(+), 29 deletions(-)

diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index 368afc7da..190c0bc8c 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -21,23 +21,6 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_mul.v
-M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
-M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
-M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
-M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
-M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
-M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
-M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
-M_DEPS += ../../../library/altera_iopll/altera_iopll_hw.tcl
-M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
-M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
-M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
-M_DEPS += ../../../library/altera_pll_reconfig/altera_pll_reconfig_hw.tcl
-M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
-M_DEPS += ../../../library/altera_xcvr_atx_pll_a10/altera_xcvr_atx_pll_a10_hw.tcl
-M_DEPS += ../../../library/altera_xcvr_reset_control/altera_xcvr_reset_control_hw.tcl
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_core.v
diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile
index 892a5ed02..881140d7d 100644
--- a/projects/daq3/kcu105/Makefile
+++ b/projects/daq3/kcu105/Makefile
@@ -21,12 +21,12 @@ M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -58,12 +58,12 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9152 clean
 	make -C ../../../library/axi_ad9680 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_upack clean
 
 
@@ -75,12 +75,12 @@ daq3_kcu105.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9152
 	make -C ../../../library/axi_ad9680
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_adcfifo
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_upack
 
 ####################################################################################
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index 052ed222b..752c5d6ff 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -24,14 +24,14 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
@@ -65,14 +65,14 @@ clean-all:clean
 	make -C ../../../library/axi_ad9152 clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/xilinx/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_mfifo clean
 	make -C ../../../library/util_upack clean
 
@@ -86,14 +86,14 @@ lib:
 	make -C ../../../library/axi_ad9152
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/xilinx/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_mfifo
 	make -C ../../../library/util_upack
 

From 721ee98a062287c6fc9a743e0530d002758f56c7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 6 Oct 2016 10:18:02 -0400
Subject: [PATCH 573/972] zcu102- misc fixes

---
 projects/common/zcu102/zcu102_system_bd.tcl |  2 +-
 projects/daq2/zcu102/system_top.v           | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/projects/common/zcu102/zcu102_system_bd.tcl b/projects/common/zcu102/zcu102_system_bd.tcl
index c010ea941..f79590967 100644
--- a/projects/common/zcu102/zcu102_system_bd.tcl
+++ b/projects/common/zcu102/zcu102_system_bd.tcl
@@ -2474,7 +2474,7 @@ ad_connect  sys_200m_clk sys_ps8/pl_clk1
 ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
 ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
 ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
-ad_connect  sys_rstgen/ext_reset_in GND
+ad_connect  sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
 
 # gpio
 
diff --git a/projects/daq2/zcu102/system_top.v b/projects/daq2/zcu102/system_top.v
index 08aced720..82412a53d 100644
--- a/projects/daq2/zcu102/system_top.v
+++ b/projects/daq2/zcu102/system_top.v
@@ -63,15 +63,15 @@ module system_top (
   input           trig_p,
   input           trig_n,
 
-  inout           adc_fdb,
-  inout           adc_fda,
-  inout           dac_irq,
-  inout   [ 1:0]  clkd_status,
+  input           adc_fdb,
+  input           adc_fda,
+  input           dac_irq,
+  input   [ 1:0]  clkd_status,
 
-  inout           adc_pd,
-  inout           dac_txen,
-  inout           dac_reset,
-  inout           clkd_sync,
+  output          adc_pd,
+  output          dac_txen,
+  output          dac_reset,
+  output          clkd_sync,
 
   output          spi_csn_clk,
   output          spi_csn_dac,

From 3b55822db39f8a954f51c8cd842e67681d271874 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 6 Oct 2016 14:09:27 -0400
Subject: [PATCH 574/972] daq2- xcvr connect

---
 projects/daq2/common/daq2_bd.tcl  | 132 +++++-------------------------
 projects/daq2/zcu102/system_top.v |  12 +--
 2 files changed, 26 insertions(+), 118 deletions(-)

diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index ae51b664d..5fc4f268d 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -1,30 +1,4 @@
 
-# daq2
-
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir I rx_sysref
-create_bd_port -dir I rx_data_0_p
-create_bd_port -dir I rx_data_0_n
-create_bd_port -dir I rx_data_1_p
-create_bd_port -dir I rx_data_1_n
-create_bd_port -dir I rx_data_2_p
-create_bd_port -dir I rx_data_2_n
-create_bd_port -dir I rx_data_3_p
-create_bd_port -dir I rx_data_3_n
-
-create_bd_port -dir I tx_ref_clk
-create_bd_port -dir I tx_sync
-create_bd_port -dir I tx_sysref
-create_bd_port -dir O tx_data_0_p
-create_bd_port -dir O tx_data_0_n
-create_bd_port -dir O tx_data_1_p
-create_bd_port -dir O tx_data_1_n
-create_bd_port -dir O tx_data_2_p
-create_bd_port -dir O tx_data_2_n
-create_bd_port -dir O tx_data_3_p
-create_bd_port -dir O tx_data_3_n
-
 # dac peripherals
 
 set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr]
@@ -32,14 +6,16 @@ set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9144_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9144_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9144_xcvr
 
-set sys_ad9144_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9144_rstgen]
+set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd]
+set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
+set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
 
 set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
 set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core
 
-set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd]
-set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
-set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
+set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack
 
 set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma
@@ -53,10 +29,6 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
 
-set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack
-
 # adc peripherals
 
 set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
@@ -64,14 +36,16 @@ set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
 
-set sys_ad9680_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9680_rstgen]
-
-set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
-
 set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
 
+set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
+
+set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
+
 set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
@@ -85,10 +59,6 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
 
-set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
-
 # shared transceiver core
 
 set util_daq2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq2_xcvr]
@@ -100,26 +70,11 @@ ad_connect  sys_cpu_clk util_daq2_xcvr/up_clk
 
 # connections (dac)
 
-ad_connect  axi_ad9144_xcvr/up_cm_0 util_daq2_xcvr/up_cm_0
-ad_connect  axi_ad9144_xcvr/up_ch_0 util_daq2_xcvr/up_tx_0
-ad_connect  axi_ad9144_xcvr/up_ch_1 util_daq2_xcvr/up_tx_1
-ad_connect  axi_ad9144_xcvr/up_ch_2 util_daq2_xcvr/up_tx_2
-ad_connect  axi_ad9144_xcvr/up_ch_3 util_daq2_xcvr/up_tx_3
-ad_connect  axi_ad9144_jesd/gt0_tx util_daq2_xcvr/tx_0
-ad_connect  axi_ad9144_jesd/gt3_tx util_daq2_xcvr/tx_1
-ad_connect  axi_ad9144_jesd/gt1_tx util_daq2_xcvr/tx_2
-ad_connect  axi_ad9144_jesd/gt2_tx util_daq2_xcvr/tx_3
-ad_connect  util_daq2_xcvr/tx_out_clk_0 util_daq2_xcvr/tx_clk_0
-ad_connect  util_daq2_xcvr/tx_out_clk_0 util_daq2_xcvr/tx_clk_1
-ad_connect  util_daq2_xcvr/tx_out_clk_0 util_daq2_xcvr/tx_clk_2
-ad_connect  util_daq2_xcvr/tx_out_clk_0 util_daq2_xcvr/tx_clk_3
-ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_jesd/tx_core_clk
-ad_connect  util_daq2_xcvr/tx_out_clk_0 sys_ad9144_rstgen/slowest_sync_clk
-ad_connect  sys_cpu_resetn sys_ad9144_rstgen/ext_reset_in
-ad_connect  tx_sysref axi_ad9144_jesd/tx_sysref
-ad_connect  tx_sync axi_ad9144_jesd/tx_sync
-ad_connect  sys_ad9144_rstgen/peripheral_reset axi_ad9144_jesd/tx_reset
-ad_connect  axi_ad9144_xcvr/up_status axi_ad9144_jesd/tx_reset_done
+ad_xcvrcon  util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd
+ad_reconct  util_daq2_xcvr/tx_0 axi_ad9144_jesd/gt0_tx
+ad_reconct  util_daq2_xcvr/tx_1 axi_ad9144_jesd/gt3_tx
+ad_reconct  util_daq2_xcvr/tx_2 axi_ad9144_jesd/gt1_tx
+ad_reconct  util_daq2_xcvr/tx_3 axi_ad9144_jesd/gt2_tx
 ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
 ad_connect  axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data
 ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk
@@ -142,53 +97,15 @@ ad_connect  axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready
 ad_connect  axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data
 ad_connect  axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid
 ad_connect  axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
-ad_connect  util_daq2_xcvr/cpll_ref_clk_0 tx_ref_clk
-ad_connect  util_daq2_xcvr/cpll_ref_clk_1 tx_ref_clk
-ad_connect  util_daq2_xcvr/cpll_ref_clk_2 tx_ref_clk
-ad_connect  util_daq2_xcvr/cpll_ref_clk_3 tx_ref_clk
-ad_connect  util_daq2_xcvr/tx_0_p tx_data_0_p
-ad_connect  util_daq2_xcvr/tx_0_n tx_data_0_n
-ad_connect  util_daq2_xcvr/tx_1_p tx_data_1_p
-ad_connect  util_daq2_xcvr/tx_1_n tx_data_1_n
-ad_connect  util_daq2_xcvr/tx_2_p tx_data_2_p
-ad_connect  util_daq2_xcvr/tx_2_n tx_data_2_n
-ad_connect  util_daq2_xcvr/tx_3_p tx_data_3_p
-ad_connect  util_daq2_xcvr/tx_3_n tx_data_3_n
 
 # connections (adc)
 
-ad_connect  axi_ad9680_xcvr/up_es_0 util_daq2_xcvr/up_es_0
-ad_connect  axi_ad9680_xcvr/up_es_1 util_daq2_xcvr/up_es_1
-ad_connect  axi_ad9680_xcvr/up_es_2 util_daq2_xcvr/up_es_2
-ad_connect  axi_ad9680_xcvr/up_es_3 util_daq2_xcvr/up_es_3
-ad_connect  axi_ad9680_xcvr/up_ch_0 util_daq2_xcvr/up_rx_0
-ad_connect  axi_ad9680_xcvr/up_ch_1 util_daq2_xcvr/up_rx_1
-ad_connect  axi_ad9680_xcvr/up_ch_2 util_daq2_xcvr/up_rx_2
-ad_connect  axi_ad9680_xcvr/up_ch_3 util_daq2_xcvr/up_rx_3
-ad_connect  axi_ad9680_jesd/gt0_rx util_daq2_xcvr/rx_0
-ad_connect  axi_ad9680_jesd/gt1_rx util_daq2_xcvr/rx_1
-ad_connect  axi_ad9680_jesd/gt2_rx util_daq2_xcvr/rx_2
-ad_connect  axi_ad9680_jesd/gt3_rx util_daq2_xcvr/rx_3
-ad_connect  axi_ad9680_jesd/rxencommaalign_out util_daq2_xcvr/rx_calign_0
-ad_connect  axi_ad9680_jesd/rxencommaalign_out util_daq2_xcvr/rx_calign_1
-ad_connect  axi_ad9680_jesd/rxencommaalign_out util_daq2_xcvr/rx_calign_2
-ad_connect  axi_ad9680_jesd/rxencommaalign_out util_daq2_xcvr/rx_calign_3
-ad_connect  util_daq2_xcvr/rx_out_clk_0 util_daq2_xcvr/rx_clk_0
-ad_connect  util_daq2_xcvr/rx_out_clk_0 util_daq2_xcvr/rx_clk_1
-ad_connect  util_daq2_xcvr/rx_out_clk_0 util_daq2_xcvr/rx_clk_2
-ad_connect  util_daq2_xcvr/rx_out_clk_0 util_daq2_xcvr/rx_clk_3
-ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_jesd/rx_core_clk
-ad_connect  util_daq2_xcvr/tx_out_clk_0 sys_ad9680_rstgen/slowest_sync_clk
-ad_connect  sys_cpu_resetn sys_ad9680_rstgen/ext_reset_in
-ad_connect  rx_sysref axi_ad9680_jesd/rx_sysref
-ad_connect  rx_sync axi_ad9680_jesd/rx_sync
-ad_connect  sys_ad9680_rstgen/peripheral_reset axi_ad9680_jesd/rx_reset
-ad_connect  axi_ad9680_xcvr/up_status axi_ad9680_jesd/rx_reset_done
+ad_xcvrcon  util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd
 ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
 ad_connect  axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
 ad_connect  axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
 ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
-ad_connect  sys_ad9680_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
 ad_connect  axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
 ad_connect  axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
 ad_connect  axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
@@ -196,7 +113,7 @@ ad_connect  axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
 ad_connect  axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
 ad_connect  axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
 ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
-ad_connect  sys_ad9680_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
 ad_connect  axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
 ad_connect  axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
 ad_connect  sys_cpu_clk axi_ad9680_fifo/dma_clk
@@ -207,15 +124,6 @@ ad_connect  axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
 ad_connect  axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
 ad_connect  axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
 ad_connect  axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
-ad_connect  util_daq2_xcvr/qpll_ref_clk_0 rx_ref_clk
-ad_connect  util_daq2_xcvr/rx_0_p rx_data_0_p
-ad_connect  util_daq2_xcvr/rx_0_n rx_data_0_n
-ad_connect  util_daq2_xcvr/rx_1_p rx_data_1_p
-ad_connect  util_daq2_xcvr/rx_1_n rx_data_1_n
-ad_connect  util_daq2_xcvr/rx_2_p rx_data_2_p
-ad_connect  util_daq2_xcvr/rx_2_n rx_data_2_n
-ad_connect  util_daq2_xcvr/rx_3_p rx_data_3_p
-ad_connect  util_daq2_xcvr/rx_3_n rx_data_3_n
 
 # interconnect (cpu)
 
diff --git a/projects/daq2/zcu102/system_top.v b/projects/daq2/zcu102/system_top.v
index 82412a53d..f54d5e0de 100644
--- a/projects/daq2/zcu102/system_top.v
+++ b/projects/daq2/zcu102/system_top.v
@@ -192,9 +192,9 @@ module system_top (
     .rx_data_2_p (rx_data_p[2]),
     .rx_data_3_n (rx_data_n[3]),
     .rx_data_3_p (rx_data_p[3]),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spi0_csn (spi_csn),
     .spi0_miso (spi_miso),
     .spi0_mosi (spi_mosi),
@@ -211,9 +211,9 @@ module system_top (
     .tx_data_2_p (tx_data_p[2]),
     .tx_data_3_n (tx_data_n[3]),
     .tx_data_3_p (tx_data_p[3]),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref));
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (tx_sysref));
 
 endmodule
 

From ffaf78665fe23d9609179583562866142f010951 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 6 Oct 2016 14:44:20 -0400
Subject: [PATCH 575/972] daq2- xcvr procedures

---
 projects/daq2/zc706/system_top.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v
index 5a7d3d58a..e9f01032c 100644
--- a/projects/daq2/zc706/system_top.v
+++ b/projects/daq2/zc706/system_top.v
@@ -392,9 +392,9 @@ module system_top (
     .rx_data_2_p (rx_data_p[2]),
     .rx_data_3_n (rx_data_n[3]),
     .rx_data_3_p (rx_data_p[3]),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),
@@ -425,9 +425,9 @@ module system_top (
     .tx_data_2_p (tx_data_p[2]),
     .tx_data_3_n (tx_data_n[3]),
     .tx_data_3_p (tx_data_p[3]),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref));
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (tx_sysref));
 
 endmodule
 

From 111adac825f052b7fc994c44f99829fc076bde13 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 10:33:37 +0300
Subject: [PATCH 576/972] axi_usb_fx3: Updated core

- trig signal will reset state machine
- slrd_n delay will be absorbed by the axi_usb_fx3_if module, when Xilinx DMA is not ready to receive data during a packet
- fx32dma_eop signals when the FX3 DMA buffer should be empty. slrd_n set high and sloe_n set low for another two clock cycles
- eot_fx32dma signals the interface that the packet has been fully transfered. No need for watermark signals
- added length_fx32dma and length_dma2fx3 as requested
---
 library/axi_usb_fx3/axi_usb_fx3.v      |  12 +++
 library/axi_usb_fx3/axi_usb_fx3_core.v |  30 +++++--
 library/axi_usb_fx3/axi_usb_fx3_if.v   | 108 +++++++++++--------------
 library/axi_usb_fx3/axi_usb_fx3_reg.v  |   9 +++
 4 files changed, 92 insertions(+), 67 deletions(-)

diff --git a/library/axi_usb_fx3/axi_usb_fx3.v b/library/axi_usb_fx3/axi_usb_fx3.v
index d409b42b4..97c3ab930 100644
--- a/library/axi_usb_fx3/axi_usb_fx3.v
+++ b/library/axi_usb_fx3/axi_usb_fx3.v
@@ -65,6 +65,7 @@ module axi_usb_fx3 (
   irq,
 
   // DEBUG
+
   debug_fx32dma,
   debug_dma2fx3,
   debug_status,
@@ -129,6 +130,7 @@ module axi_usb_fx3 (
   output          epswitch_n;
 
   // DEBUG
+
   output  [74:0]  debug_fx32dma;
   output  [73:0]  debug_dma2fx3;
   output  [14:0]  debug_status;
@@ -250,6 +252,9 @@ module axi_usb_fx3 (
   wire    [ 4:0]  fifo_num;
   wire    [10:0]  fifo_ready;
 
+  wire    [31:0]  length_fx32dma;
+  wire    [31:0]  length_dma2fx3;
+
   // signal name changes
 
   assign up_clk   = s_axi_aclk;
@@ -305,6 +310,9 @@ module axi_usb_fx3 (
     .fifoa_header_size(fifoa_header_size),
     .fifoa_buffer_size(fifoa_buffer_size),
 
+    .length_fx32dma(length_fx32dma),
+    .length_dma2fx3(length_dma2fx3),
+
     .fx32dma_valid(fx32dma_valid),
     .fx32dma_ready(fx32dma_ready),
     .fx32dma_data(fx32dma_data),
@@ -389,6 +397,9 @@ module axi_usb_fx3 (
     .fifoa_header_size(fifoa_header_size),
     .fifoa_buffer_size(fifoa_buffer_size),
 
+    .length_fx32dma(length_fx32dma),
+    .length_dma2fx3(length_dma2fx3),
+
     .up_rstn(up_rstn),
     .up_clk(up_clk),
     .up_wreq(up_wreq),
@@ -430,6 +441,7 @@ module axi_usb_fx3 (
     .fx32dma_data(fx32dma_data),
     .fx32dma_sop(fx32dma_sop),
     .fx32dma_eop(fx32dma_eop),
+    .eot_fx32dma(eot_fx32dma),
 
     .dma2fx3_ready(dma2fx3_ready),
     .dma2fx3_valid(dma2fx3_valid),
diff --git a/library/axi_usb_fx3/axi_usb_fx3_core.v b/library/axi_usb_fx3/axi_usb_fx3_core.v
index 4747553d4..51877fe88 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_core.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_core.v
@@ -111,6 +111,9 @@ module axi_usb_fx3_core (
   fifof_header_size,
   fifof_buffer_size,
 
+  length_fx32dma,
+  length_dma2fx3,
+
   // fx3 interface
   // IN -> TO HOST / FX3
   // OUT -> FROM HOST / FX3
@@ -205,6 +208,9 @@ module axi_usb_fx3_core (
   input   [ 7:0]  fifof_header_size;
   input   [15:0]  fifof_buffer_size;
 
+  output  [31:0]  length_fx32dma;
+  output  [31:0]  length_dma2fx3;
+
   // FX3 interface
   // IN -> ZYNQ TO HOST / FX3
   // OUT -> ZYNQ FROM HOST / FX3
@@ -213,7 +219,7 @@ module axi_usb_fx3_core (
   output          fx32dma_ready;
   input   [31:0]  fx32dma_data;
   input           fx32dma_sop;
-  input           fx32dma_eop;
+  output          fx32dma_eop;
 
   input           dma2fx3_ready;
   output          dma2fx3_valid;
@@ -244,7 +250,7 @@ module axi_usb_fx3_core (
 
   // internal registers
 
-  reg     [31:0]  data_size_transaction = 32'h0;
+  reg     [31:0]  data_size_transaction = 32'hffffffff;
   reg     [15:0]  buffer_size_current = 16'h0;
   reg     [ 7:0]  header_size_current = 8'h0;
 
@@ -281,6 +287,11 @@ module axi_usb_fx3_core (
   reg             monitor_error = 1'b0;
   reg             first_transfer = 1'b0;
 
+  reg     [31:0]  length_fx32dma = 0;
+  reg     [31:0]  length_dma2fx3 = 0;
+
+  reg             fx32dma_eop = 1'b0;
+
   function [31:0] pn23;
     input [31:0] din;
     reg   [31:0] dout;
@@ -447,11 +458,12 @@ module axi_usb_fx3_core (
 
   always @(*) begin
     m_axis_tdata = fx32dma_data;
+    fx32dma_eop = 1'b0;
+    m_axis_tlast = 1'b0;
     case(state_fx32dma)
       IDLE: begin
         m_axis_tvalid = 1'b0;
         m_axis_tkeep = 4'h0;
-        m_axis_tlast = 1'b0;
         eot_fx32dma  = 1'b0;
       end
       READ_HEADER: begin
@@ -462,13 +474,18 @@ module axi_usb_fx3_core (
       end
       READ_DATA: begin
         m_axis_tvalid = fx32dma_valid;
-        m_axis_tlast = fx32dma_eop;
-        eot_fx32dma = fx32dma_eop;
         if (fx32dma_valid == 1'b1) begin
+          if (data_size_transaction > 12 ) begin
+            fx32dma_eop = 1'b0;
+          end else begin
+            fx32dma_eop = 1'b1;
+          end
           if (data_size_transaction > 4) begin
+            m_axis_tlast = 1'b0;
             m_axis_tkeep = 4'hf;
             eot_fx32dma  = 1'b0;
           end else begin
+            m_axis_tlast = 1'b1;
             eot_fx32dma  = 1'b1;
             m_axis_tlast = 1'b1;
             case (data_size_transaction)
@@ -491,6 +508,7 @@ module axi_usb_fx3_core (
       end
     endcase
   end
+
   always @(posedge clk) begin
     header_read <= 1'b0;
     if (state_fx32dma == IDLE) begin
@@ -516,6 +534,7 @@ module axi_usb_fx3_core (
         end
         if (header_pointer == 4) begin
           data_size_transaction <= fx32dma_data;
+          length_fx32dma <= fx32dma_data;
           if (fx32dma_data > buffer_size_current) begin
             error_fx32dma <= 1'b1;
           end
@@ -677,6 +696,7 @@ module axi_usb_fx3_core (
 
     if(state_dma2fx3 == ADD_FOOTER) begin
       footer_pointer <= footer_pointer + 4;
+      length_dma2fx3 <= dma2fx3_counter;
       case(footer_pointer)
         32'h4: dma2fx3_data_reg <= dma2fx3_counter;
         32'h8: dma2fx3_data_reg <= 32'h0;
diff --git a/library/axi_usb_fx3/axi_usb_fx3_if.v b/library/axi_usb_fx3/axi_usb_fx3_if.v
index 0f78d5608..45b6c05e5 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_if.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_if.v
@@ -67,6 +67,7 @@ module axi_usb_fx3_if (
   fx32dma_data,
   fx32dma_sop,
   fx32dma_eop,
+  eot_fx32dma,
 
   dma2fx3_ready,
   dma2fx3_valid,
@@ -101,7 +102,8 @@ module axi_usb_fx3_if (
   input           fx32dma_ready;
   output  [31:0]  fx32dma_data;
   output          fx32dma_sop;
-  output          fx32dma_eop;
+  input           fx32dma_eop;
+  input           eot_fx32dma;
 
   input           dma2fx3_valid;
   output          dma2fx3_ready;
@@ -110,36 +112,33 @@ module axi_usb_fx3_if (
 
   // internal registers
 
-
-  reg [10:0]  fifo_ready;
+  reg [10:0]  fifo_ready = 0;
 
   reg [31:0]  fx32dma_data = 0;
-  reg         fx32dma_eop;
-
-  reg [ 1:0]  rd_oe_delay;
 
   reg [ 3:0]  state_gpif_ii = 4'h0;
   reg [ 3:0]  next_state_gpif_ii = 4'h0;
 
-  reg         current_direction;
-  reg         current_fifo;
-  reg         current_fifo_d1;
-  reg         current_fifo_d2;
-  reg         current_fifo_d3;
-  reg         slcs_n;
-  reg         slrd_n;
-  reg         sloe_n;
-  reg [ 1:0]  addr;
-  reg         sloe_n_d1;
-  reg         sloe_n_d2;
-  reg         sloe_n_d3;
-  reg         slwr_n;
-  reg         fx32dma_valid;
-  reg         dma2fx3_ready;
-  reg         fx32dma_sop;
-  reg         fx32dma_sop_d1;
-  reg         pktend_n;
-  reg         slcs_n_d1;
+  reg         current_direction = 0;
+  reg         current_fifo = 0;
+  reg         slcs_n = 0;
+  reg         slcs_n_d1 = 0;
+  reg         slcs_n_d2 = 0;
+  reg         slcs_n_d3 = 0;
+  reg         slcs_n_d4 = 0;
+  reg         slrd_n = 0;
+  reg         slrd_n_d1 = 0;
+  reg         slrd_n_d2 = 0;
+  reg         slrd_n_d3 = 0;
+  reg         sloe_n = 0;
+  reg [ 1:0]  addr = 0;
+  reg         sloe_n_d1 = 0;
+  reg         slwr_n = 0;
+  reg         fx32dma_valid = 0;
+  reg         dma2fx3_ready = 0;
+  reg         fx32dma_sop = 0;
+  reg         pktend_n = 0;
+  reg         pip = 0;
 
   localparam IDLE         = 4'b0001;
   localparam READ_START   = 4'b0010;
@@ -198,8 +197,9 @@ module axi_usb_fx3_if (
     endcase
   end
 
+  // STATE MACHINE GPIF II
   always @(posedge pclk) begin
-    if (reset_n == 1'b0) begin
+    if (reset_n == 1'b0 || trig == 1'b0 ) begin
       state_gpif_ii <= IDLE;
     end else begin
       state_gpif_ii <= next_state_gpif_ii;
@@ -219,13 +219,9 @@ module axi_usb_fx3_if (
           next_state_gpif_ii = IDLE;
         end
       READ_START:
-        if(rd_oe_delay == 2'h3) begin
           next_state_gpif_ii = READ_DATA;
-        end else begin
-          next_state_gpif_ii = READ_START;
-        end
       READ_DATA:
-        if (sloe_n == 1'b1) begin
+        if (eot_fx32dma == 1'b1) begin
           next_state_gpif_ii = IDLE;
         end else begin
           next_state_gpif_ii = READ_DATA;
@@ -252,31 +248,28 @@ module axi_usb_fx3_if (
         slwr_n        = 1'b1;
         pktend_n      = 1'b1;
         dma2fx3_ready = 1'b0;
-        fx32dma_eop   = 1'b0;
       end
       READ_START: begin
         slcs_n        = 1'b0;
         sloe_n        = 1'b0;
-        slrd_n        = slcs_n_d1;
+        slrd_n        = 1'b1;
         fx32dma_valid = 1'b0;
         fx32dma_sop   = 1'b0;
         fx32dma_data  = 32'h0;
         slwr_n        = 1'b1;
         pktend_n      = 1'b1;
         dma2fx3_ready = 1'b0;
-        fx32dma_eop   = 1'b0;
       end
       READ_DATA: begin
         slcs_n        = 1'b0;
-        sloe_n        = sloe_n_d2;
-        slrd_n        = !current_fifo_d3;
-        fx32dma_valid = !sloe_n_d3;
-        fx32dma_sop   = fx32dma_sop_d1;
+        sloe_n        = 1'b0;
+        slrd_n        = !fx32dma_ready | fx32dma_eop;
+        fx32dma_valid = !slcs_n_d4 & !slrd_n_d3;
+        fx32dma_sop   = !slcs_n_d4 & !slrd_n_d3 & pip;
         fx32dma_data  = data;
         slwr_n        = 1'b1;
         pktend_n      = 1'b1;
         dma2fx3_ready = 1'b0;
-        fx32dma_eop   = sloe_n_d2;
       end
       WRITE_DATA: begin
         slcs_n        = 1'b0;
@@ -285,10 +278,9 @@ module axi_usb_fx3_if (
         fx32dma_valid = 1'b0;
         fx32dma_sop   = 1'b0;
         fx32dma_data  = 32'h0;
-        slwr_n = (state_gpif_ii == WRITE_DATA) ? (!dma2fx3_valid | !current_fifo) : 1'b1;
+        slwr_n =  !dma2fx3_valid | !current_fifo;
         dma2fx3_ready = current_fifo;
-        pktend_n = (state_gpif_ii == WRITE_DATA ) ? !dma2fx3_eop : 1'b1;
-        fx32dma_eop   = 1'b0;
+        pktend_n = !dma2fx3_eop;
       end
       default: begin
         slcs_n        = 1'b1;
@@ -300,35 +292,27 @@ module axi_usb_fx3_if (
         slwr_n        = 1'b1;
         pktend_n      = 1'b1;
         dma2fx3_ready = 1'b0;
-        fx32dma_eop   = 1'b0;
       end
     endcase
   end
 
   always @(posedge pclk) begin
-    slcs_n_d1 <= slcs_n;
-    current_fifo_d1 <= current_fifo;
-    current_fifo_d2 <= current_fifo_d1;
-    current_fifo_d3 <= current_fifo_d2;
     fifo_ready <= {7'h0,fifo_rdy};
-    if(state_gpif_ii == READ_DATA) begin
-      fx32dma_sop_d1 <= 1'b0;
-    end else begin
-      fx32dma_sop_d1 <= 1'b1;
-    end
-
-    sloe_n_d1     <= slrd_n;
-    sloe_n_d2     <= sloe_n_d1;
-    sloe_n_d3     <= sloe_n_d2;
-
+    slrd_n_d1     <= slrd_n;
+    slrd_n_d2     <= slrd_n_d1;
+    slrd_n_d3     <= slrd_n_d2;
+    slcs_n_d1     <= slcs_n;
+    slcs_n_d2     <= slcs_n_d1;
+    slcs_n_d3     <= slcs_n_d2;
+    slcs_n_d4     <= slcs_n_d3;
     addr          <= fifo_num[1:0];
-
-    if(state_gpif_ii == READ_START) begin
-      rd_oe_delay   <= rd_oe_delay + 1'b1;
+    if (state_gpif_ii == IDLE) begin
+      pip <= 1'b1;
     end else begin
-      rd_oe_delay   <= 2'h0;
+      if (fx32dma_sop == 1'b1) begin
+        pip <= 1'b0;
+      end
     end
-
   end
 
 endmodule
diff --git a/library/axi_usb_fx3/axi_usb_fx3_reg.v b/library/axi_usb_fx3/axi_usb_fx3_reg.v
index 3d9c6e750..f4df03f94 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_reg.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_reg.v
@@ -102,6 +102,9 @@ module axi_usb_fx3_reg (
   fifoa_header_size,
   fifoa_buffer_size,
 
+  length_fx32dma,
+  length_dma2fx3,
+
   // bus interface
 
   up_rstn,
@@ -176,6 +179,9 @@ module axi_usb_fx3_reg (
   output  [ 7:0]  fifoa_header_size;
   output  [15:0]  fifoa_buffer_size;
 
+  input   [31:0]  length_fx32dma;
+  input   [31:0]  length_dma2fx3;
+
  // bus interface
 
   input           up_rstn;
@@ -325,6 +331,7 @@ module axi_usb_fx3_reg (
       tpm_status <= 32'h0;
       tpg_config <= 32'h0;
       tpg_status <= 32'h0;
+      fifo_status <= 32'h0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h0)) begin
@@ -420,6 +427,8 @@ module axi_usb_fx3_reg (
           5'h15: up_rdata <= tpm_status;
           5'h16: up_rdata <= tpg_config;
           5'h17: up_rdata <= tpg_status;
+          5'h18: up_rdata <= length_fx32dma;
+          5'h19: up_rdata <= length_dma2fx3;
           default: up_rdata <= 0;
         endcase
       end else begin

From 74faac921092d71df37616e051b17d6a2f9cf9fe Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 13:19:55 +0300
Subject: [PATCH 577/972] ad9467_fmc: KC705, updated system_top to remove part
 of the Warnings

---
 projects/ad9467_fmc/kc705/system_top.v | 46 +++++++++-----------------
 1 file changed, 15 insertions(+), 31 deletions(-)

diff --git a/projects/ad9467_fmc/kc705/system_top.v b/projects/ad9467_fmc/kc705/system_top.v
index 85e60b69b..a44c82b11 100644
--- a/projects/ad9467_fmc/kc705/system_top.v
+++ b/projects/ad9467_fmc/kc705/system_top.v
@@ -95,14 +95,6 @@ module system_top (
   iic_scl,
   iic_sda,
 
-  hdmi_out_clk,
-  hdmi_hsync,
-  hdmi_vsync,
-  hdmi_data_e,
-  hdmi_data,
-
-  spdif,
-
   adc_clk_in_n,
   adc_clk_in_p,
   adc_data_in_n,
@@ -169,14 +161,6 @@ module system_top (
   inout           iic_scl;
   inout           iic_sda;
 
-  output          hdmi_out_clk;
-  output          hdmi_hsync;
-  output          hdmi_vsync;
-  output          hdmi_data_e;
-  output  [15:0]  hdmi_data;
-
-  output          spdif;
-
   input           adc_clk_in_n;
   input           adc_clk_in_p;
   input  [ 7:0]   adc_data_in_n;
@@ -189,7 +173,7 @@ module system_top (
   inout           spi_sdio;
 
   // internal signals
-  wire   [ 1:0]   spi_csn;
+  wire   [ 7:0]   spi_csn;
   wire            spi_miso;
   wire            spi_mosi;
 
@@ -206,7 +190,7 @@ module system_top (
   assign spi_csn_clk = spi_csn[1];
 
   ad9467_spi i_spi (
-      .spi_csn(spi_csn),
+      .spi_csn(spi_csn[1:0]),
       .spi_clk(spi_clk),
       .spi_mosi(spi_mosi),
       .spi_miso(spi_miso),
@@ -275,19 +259,19 @@ module system_top (
       .sys_rst (sys_rst),
       .uart_sin (uart_sin),
       .uart_sout (uart_sout),
-      .adc_clk_in_n(adc_clk_in_n),
-      .adc_clk_in_p(adc_clk_in_p),
-      .adc_data_in_n(adc_data_in_n),
-      .adc_data_in_p(adc_data_in_p),
-      .adc_data_or_n(adc_data_or_n),
-      .adc_data_or_p(adc_data_or_p),
-      .spi_clk_i(1'b0),
-      .spi_clk_o(spi_clk),
-      .spi_csn_i(1'b1),
-      .spi_csn_o(spi_csn),
-      .spi_sdi_i(spi_miso),
-      .spi_sdo_i(1'b0),
-      .spi_sdo_o(spi_mosi));
+      .adc_clk_in_n (adc_clk_in_n),
+      .adc_clk_in_p (adc_clk_in_p),
+      .adc_data_in_n (adc_data_in_n),
+      .adc_data_in_p (adc_data_in_p),
+      .adc_data_or_n (adc_data_or_n),
+      .adc_data_or_p (adc_data_or_p),
+      .spi_clk_i (1'b0),
+      .spi_clk_o (spi_clk),
+      .spi_csn_i (1'b1),
+      .spi_csn_o (spi_csn),
+      .spi_sdi_i (spi_miso),
+      .spi_sdo_i (1'b0),
+      .spi_sdo_o (spi_mosi));
 
   endmodule
 

From c737afebf8597cacd7b55bced64d1462be2a916a Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 13:24:40 +0300
Subject: [PATCH 578/972] adv7511: KC705, updated system_top to remove part of
 the Warnings

---
 projects/adv7511/kc705/system_top.v | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/projects/adv7511/kc705/system_top.v b/projects/adv7511/kc705/system_top.v
index c5588cfdc..6be7fd3ed 100644
--- a/projects/adv7511/kc705/system_top.v
+++ b/projects/adv7511/kc705/system_top.v
@@ -223,6 +223,21 @@ module system_top (
     .mb_intr_13 (1'b0),
     .mb_intr_14 (1'b0),
     .mb_intr_15 (1'b0),
+    .hdmi_24_data (),
+    .hdmi_24_data_e (),
+    .hdmi_24_hsync (),
+    .hdmi_24_vsync (),
+    .hdmi_36_data (),
+    .hdmi_36_data_e (),
+    .hdmi_36_hsync (),
+    .hdmi_36_vsync (),
+    .spi_clk_i (1'b0),
+    .spi_clk_o (),
+    .spi_csn_i (1'b0),
+    .spi_csn_o (),
+    .spi_sdi_i (1'b0),
+    .spi_sdo_i (1'b0),
+    .spi_sdo_o (),
     .mdio_mdc (mdio_mdc),
     .mdio_mdio_io (mdio_mdio),
     .mii_col (mii_col),

From a12d34a98bcb112863fce43173f38392f67c232d Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 15:54:34 +0300
Subject: [PATCH 579/972] adv7511: Zed, updated system_top to remove part of
 the Warnings

---
 projects/adv7511/zed/system_top.v | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/projects/adv7511/zed/system_top.v b/projects/adv7511/zed/system_top.v
index c0514e529..67f4c72c8 100644
--- a/projects/adv7511/zed/system_top.v
+++ b/projects/adv7511/zed/system_top.v
@@ -146,6 +146,8 @@ module system_top (
   wire    [ 1:0]  iic_mux_sda_o_s;
   wire            iic_mux_sda_t_s;
 
+  assign gpio_i[63:32] = gpio_o[63:32];
+
   // instantiations
 
   ad_iobuf #(
@@ -229,7 +231,25 @@ module system_top (
     .ps_intr_12 (1'b0),
     .ps_intr_13 (1'b0),
     .otg_vbusoc (otg_vbusoc),
-    .spdif (spdif));
+    .spdif (spdif),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (),
+    .spi0_csn_0_o (),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (1'b0),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o ());
 
 endmodule
 

From 2e605fc060a4212887fda588d867304abb1c59eb Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 15:56:46 +0300
Subject: [PATCH 580/972] cn0363: Zed, update system_top to remove part of the
 Warnings

---
 projects/cn0363/zed/system_top.v | 39 ++++++++++++++++++++++++--------
 1 file changed, 30 insertions(+), 9 deletions(-)

diff --git a/projects/cn0363/zed/system_top.v b/projects/cn0363/zed/system_top.v
index 5a1df69a1..4c13ce0f5 100644
--- a/projects/cn0363/zed/system_top.v
+++ b/projects/cn0363/zed/system_top.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -91,7 +91,7 @@ module system_top (
   led_clk_o,
   gain0_o,
   gain1_o,
-  
+
   otg_vbusoc);
 
   inout   [14:0]  ddr_addr;
@@ -138,7 +138,7 @@ module system_top (
   inout           iic_sda;
   inout   [ 1:0]  iic_mux_scl;
   inout   [ 1:0]  iic_mux_sda;
-  
+
   input           spi_sdi;
   inout           spi_sdo;
   output          spi_sclk;
@@ -168,8 +168,10 @@ module system_top (
 
   assign gain0_o = gpio_o[32];
   assign gain1_o = gpio_o[33];
-  
+
   assign gpio_i[34] = spi_sdi; // Interrupt
+  assign gpio_i[33] = gpio_o[33];
+  assign gpio_i[32] = gpio_o[32];
   assign led_clk_o = excitation;
 
   ad_iobuf #(
@@ -177,6 +179,7 @@ module system_top (
   ) i_sdo_iobuf (
     .dio_t(spi_sdo_t),
     .dio_i(spi_sdo_o),
+    .dio_o(),
     .dio_p(spi_sdo)
   );
 
@@ -268,7 +271,25 @@ module system_top (
     .spi_sclk (spi_sclk),
     .excitation (excitation),
     .otg_vbusoc (otg_vbusoc),
-    .spdif (spdif));
+    .spdif (spdif),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (),
+    .spi0_csn_0_o (),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (1'b0),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o ());
 
 endmodule
 

From f464497062b971bf1c7d341c803d50d89095770c Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 16:00:03 +0300
Subject: [PATCH 581/972] cn0363: Microzed, updated system_top to remove part
 of the Warnings

---
 projects/cn0363/microzed/system_top.v | 37 ++++++++++++++++++++++-----
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/projects/cn0363/microzed/system_top.v b/projects/cn0363/microzed/system_top.v
index f6ea4ce35..d123450d7 100644
--- a/projects/cn0363/microzed/system_top.v
+++ b/projects/cn0363/microzed/system_top.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -70,7 +70,7 @@ module system_top (
   led_clk_o,
   gain0_o,
   gain1_o,
-  
+
   otg_vbusoc);
 
   inout   [14:0]  ddr_addr;
@@ -119,8 +119,9 @@ module system_top (
 
   assign gain0_o = gpio_o[32];
   assign gain1_o = gpio_o[33];
-  
+
   assign gpio_i[34] = spi_sdi; // Interrupt
+  assign gpio_i[33:0] = gpio_o[33:0];
   assign led_clk_o = excitation;
 
   ad_iobuf #(
@@ -128,6 +129,7 @@ module system_top (
   ) i_sdo_iobuf (
     .dio_t(spi_sdo_t),
     .dio_i(spi_sdo_o),
+    .dio_o(),
     .dio_p(spi_sdo)
   );
 
@@ -166,7 +168,28 @@ module system_top (
     .ps_intr_07 (1'b0),
     .ps_intr_08 (1'b0),
     .ps_intr_09 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_14 (1'b0),
+    .ps_intr_15 (1'b0),
     .ps_intr_10 (1'b0),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (),
+    .spi0_csn_0_o (),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
     .spi_sdo (spi_sdo_o),
     .spi_sdo_t (spi_sdo_t),
     .spi_sdi (spi_sdi),

From 94f55f20e9a2801ded857b601ae752fee58b2558 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 16:12:17 +0300
Subject: [PATCH 582/972] adv7511: KCU105, updated system_top to remove part of
 the Warnings

---
 projects/adv7511/kcu105/system_top.v | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/projects/adv7511/kcu105/system_top.v b/projects/adv7511/kcu105/system_top.v
index cd7993914..751017452 100644
--- a/projects/adv7511/kcu105/system_top.v
+++ b/projects/adv7511/kcu105/system_top.v
@@ -144,6 +144,7 @@ module system_top (
   // default logic
 
   assign fan_pwm = 1'b1;
+  assign gpio_i[63:17] = gpio_o[63:17];
 
   // instantiations
 
@@ -195,6 +196,13 @@ module system_top (
     .mb_intr_13 (1'b0),
     .mb_intr_14 (1'b0),
     .mb_intr_15 (1'b0),
+    .spi_clk_i (1'b0),
+    .spi_clk_o (),
+    .spi_csn_i (1'b1),
+    .spi_csn_o (),
+    .spi_sdi_i (1'b0),
+    .spi_sdo_i (1'b0),
+    .spi_sdo_o (),
     .mdio_mdc (mdio_mdc),
     .mdio_mdio_io (mdio_mdio),
     .phy_clk_clk_n (phy_clk_n),

From 15f36af4c273ac96138ee0ce56836d8c54436eb2 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 10 Oct 2016 13:29:50 +0300
Subject: [PATCH 583/972] axi_ad9152: Update core to support Altera platforms

---
 library/axi_ad9152/axi_ad9152.v      | 12 +++-
 library/axi_ad9152/axi_ad9152_hw.tcl | 15 ++++-
 library/axi_ad9152/axi_ad9152_if.v   | 85 +++++++++++-----------------
 3 files changed, 56 insertions(+), 56 deletions(-)

diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v
index cc9c36e45..192c65a80 100644
--- a/library/axi_ad9152/axi_ad9152.v
+++ b/library/axi_ad9152/axi_ad9152.v
@@ -46,6 +46,8 @@ module axi_ad9152 (
 
   tx_clk,
   tx_data,
+  tx_valid,
+  tx_ready,
 
   // dma interface
 
@@ -87,12 +89,15 @@ module axi_ad9152 (
 
   parameter   ID = 0;
   parameter   DAC_DATAPATH_DISABLE = 0;
+  parameter   DEVICE_TYPE = 0;
 
   // jesd interface
   // tx_clk is (line-rate/40)
 
   input             tx_clk;
   output  [127:0]   tx_data;
+  output            tx_valid;
+  input             tx_ready;
 
   // dma interface
 
@@ -112,7 +117,7 @@ module axi_ad9152 (
   input             s_axi_aresetn;
   input             s_axi_awvalid;
   input   [ 31:0]   s_axi_awaddr;
-  input   [  2:0]                           s_axi_awprot;
+  input   [  2:0]   s_axi_awprot;
   output            s_axi_awready;
   input             s_axi_wvalid;
   input   [ 31:0]   s_axi_wdata;
@@ -123,7 +128,7 @@ module axi_ad9152 (
   input             s_axi_bready;
   input             s_axi_arvalid;
   input   [ 31:0]   s_axi_araddr;
-  input   [  2:0]                           s_axi_arprot;
+  input   [  2:0]   s_axi_arprot;
   output            s_axi_arready;
   output            s_axi_rvalid;
   output  [ 31:0]   s_axi_rdata;
@@ -159,10 +164,11 @@ module axi_ad9152 (
 
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
+  assign tx_valid = 1'b1;
 
   // device interface
 
-  axi_ad9152_if i_if (
+  axi_ad9152_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
     .tx_clk (tx_clk),
     .tx_data (tx_data),
     .dac_clk (dac_clk),
diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl
index c9e0af707..4e86938d7 100755
--- a/library/axi_ad9152/axi_ad9152_hw.tcl
+++ b/library/axi_ad9152/axi_ad9152_hw.tcl
@@ -40,6 +40,13 @@ set_parameter_property ID TYPE INTEGER
 set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
+add_parameter DEVICE_TYPE INTEGER 0
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
 # axi4 slave
 
 add_interface s_axi_clock clock end
@@ -75,7 +82,13 @@ add_interface_port s_axi s_axi_rready rready Input 1
 # transceiver interface
 
 ad_alt_intf clock   tx_clk        input   1
-ad_alt_intf signal  tx_data       output  128 data
+
+add_interface if_tx_data avalon_streaming source
+add_interface_port if_tx_data tx_data data output 128
+add_interface_port if_tx_data tx_valid valid output 1
+add_interface_port if_tx_data tx_ready ready input 1
+set_interface_property if_tx_data associatedClock if_tx_clk
+set_interface_property if_tx_data dataBitsPerSymbol 128
 
 # dma interface
 
diff --git a/library/axi_ad9152/axi_ad9152_if.v b/library/axi_ad9152/axi_ad9152_if.v
index 9275f809b..523888e03 100644
--- a/library/axi_ad9152/axi_ad9152_if.v
+++ b/library/axi_ad9152/axi_ad9152_if.v
@@ -41,49 +41,30 @@
 
 `timescale 1ns/100ps
 
-module axi_ad9152_if (
+module axi_ad9152_if #(
+
+  // altera (0x1) or xilinx (0x0)
+
+  parameter DEVICE_TYPE = 0)(
 
   // jesd interface
   // tx_clk is (line-rate/40)
 
-  tx_clk,
-  tx_data,
+  input                tx_clk,
+  output reg  [127:0]  tx_data,
 
   // dac interface
 
-  dac_clk,
-  dac_rst,
-  dac_data_0_0,
-  dac_data_0_1,
-  dac_data_0_2,
-  dac_data_0_3,
-  dac_data_1_0,
-  dac_data_1_1,
-  dac_data_1_2,
-  dac_data_1_3);
-
-  // jesd interface
-  // tx_clk is (line-rate/40)
-
-  input           tx_clk;
-  output [127:0]  tx_data;
-
-  // dac interface
-
-  output          dac_clk;
-  input           dac_rst;
-  input   [15:0]  dac_data_0_0;
-  input   [15:0]  dac_data_0_1;
-  input   [15:0]  dac_data_0_2;
-  input   [15:0]  dac_data_0_3;
-  input   [15:0]  dac_data_1_0;
-  input   [15:0]  dac_data_1_1;
-  input   [15:0]  dac_data_1_2;
-  input   [15:0]  dac_data_1_3;
-
-  // internal registers
-
-  reg    [127:0]  tx_data = 'd0;
+  output               dac_clk,
+  input                dac_rst,
+  input       [15:0]   dac_data_0_0,
+  input       [15:0]   dac_data_0_1,
+  input       [15:0]   dac_data_0_2,
+  input       [15:0]   dac_data_0_3,
+  input       [15:0]   dac_data_1_0,
+  input       [15:0]   dac_data_1_1,
+  input       [15:0]   dac_data_1_2,
+  input       [15:0]   dac_data_1_3);
 
   // reorder data for the jesd links
 
@@ -93,22 +74,22 @@ module axi_ad9152_if (
     if (dac_rst == 1'b1) begin
       tx_data <= 128'd0;
     end else begin
-      tx_data[127:120] <= dac_data_1_3[ 7: 0];
-      tx_data[119:112] <= dac_data_1_2[ 7: 0];
-      tx_data[111:104] <= dac_data_1_1[ 7: 0];
-      tx_data[103: 96] <= dac_data_1_0[ 7: 0];
-      tx_data[ 95: 88] <= dac_data_1_3[15: 8];
-      tx_data[ 87: 80] <= dac_data_1_2[15: 8];
-      tx_data[ 79: 72] <= dac_data_1_1[15: 8];
-      tx_data[ 71: 64] <= dac_data_1_0[15: 8];
-      tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
-      tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
-      tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
-      tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
-      tx_data[ 31: 24] <= dac_data_0_3[15: 8];
-      tx_data[ 23: 16] <= dac_data_0_2[15: 8];
-      tx_data[ 15:  8] <= dac_data_0_1[15: 8];
-      tx_data[  7:  0] <= dac_data_0_0[15: 8];
+      tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data_1_0[ 7: 0] : dac_data_1_3[ 7: 0];
+      tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data_1_1[ 7: 0] : dac_data_1_2[ 7: 0];
+      tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data_1_2[ 7: 0] : dac_data_1_1[ 7: 0];
+      tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data_1_3[ 7: 0] : dac_data_1_0[ 7: 0];
+      tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data_1_0[15: 8] : dac_data_1_3[15: 8];
+      tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data_1_1[15: 8] : dac_data_1_2[15: 8];
+      tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data_1_2[15: 8] : dac_data_1_1[15: 8];
+      tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data_1_3[15: 8] : dac_data_1_0[15: 8];
+      tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data_0_0[ 7: 0] : dac_data_0_3[ 7: 0];
+      tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data_0_1[ 7: 0] : dac_data_0_2[ 7: 0];
+      tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data_0_2[ 7: 0] : dac_data_0_1[ 7: 0];
+      tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data_0_3[ 7: 0] : dac_data_0_0[ 7: 0];
+      tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data_0_0[15: 8] : dac_data_0_3[15: 8];
+      tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data_0_1[15: 8] : dac_data_0_2[15: 8];
+      tx_data[ 15:  8] <= (DEVICE_TYPE == 1) ? dac_data_0_2[15: 8] : dac_data_0_1[15: 8];
+      tx_data[  7:  0] <= (DEVICE_TYPE == 1) ? dac_data_0_3[15: 8] : dac_data_0_0[15: 8];
     end
   end
 

From fcd56a2f9066ccc6c61ee88fab8215a2507c94be Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 10 Oct 2016 13:36:48 +0300
Subject: [PATCH 584/972] daq3/a10gx: Update project to the new GT framework

- Update common script
- Update system_top, some port names were changed
- Update constraint files
---
 projects/daq3/a10gx/system_constr.sdc  |  14 +-
 projects/daq3/a10gx/system_project.tcl |  10 +
 projects/daq3/a10gx/system_top.v       |  18 +-
 projects/daq3/common/daq3_qsys.tcl     | 357 ++++++++++++-------------
 4 files changed, 195 insertions(+), 204 deletions(-)

diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc
index a1450327d..6fd93ff6b 100644
--- a/projects/daq3/a10gx/system_constr.sdc
+++ b/projects/daq3/a10gx/system_constr.sdc
@@ -13,31 +13,31 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
   i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \
   i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \
   i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}]
- 
+
 set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
   i_system_bd|sys_ddr3_cntrl_core_nios_clk}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|avl_ad9152_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
+  -to [get_clocks {i_system_bd||avl_ad9152_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]
+  -to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9152_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9152_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl
index e2541bda9..e8487746b 100644
--- a/projects/daq3/a10gx/system_project.tcl
+++ b/projects/daq3/a10gx/system_project.tcl
@@ -60,6 +60,16 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
 set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
 
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3]
+
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
+set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
+
 # gpio
 
 set_location_assignment PIN_AT17  -to trig                  ; ## H13  FMCA_LA07_P
diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v
index 5cf8b702a..750e39e3f 100644
--- a/projects/daq3/a10gx/system_top.v
+++ b/projects/daq3/a10gx/system_top.v
@@ -268,14 +268,20 @@ module system_top (
     .sys_spi_MOSI (spi_mosi_s),
     .sys_spi_SCLK (spi_clk),
     .sys_spi_SS_n (spi_csn_s),
-    .rx_data_rx_serial_data (rx_data),
+    .rx_data_0_rx_serial_data (rx_data[0]),
+    .rx_data_1_rx_serial_data (rx_data[1]),
+    .rx_data_2_rx_serial_data (rx_data[2]),
+    .rx_data_3_rx_serial_data (rx_data[3]),
     .rx_ref_clk_clk (rx_ref_clk),
-    .rx_sync_rx_sync (rx_sync),
-    .rx_sysref_rx_ext_sysref_in (rx_sysref),
-    .tx_data_tx_serial_data (tx_data),
+    .rx_sync_export (rx_sync),
+    .rx_sysref_export (rx_sysref),
+    .tx_data_0_tx_serial_data (tx_data[0]),
+    .tx_data_1_tx_serial_data (tx_data[1]),
+    .tx_data_2_tx_serial_data (tx_data[2]),
+    .tx_data_3_tx_serial_data (tx_data[3]),
     .tx_ref_clk_clk (tx_ref_clk),
-    .tx_sync_tx_sync (tx_sync),
-    .tx_sysref_tx_ext_sysref_in (tx_sysref),
+    .tx_sync_export (tx_sync),
+    .tx_sysref_export (tx_sysref),
     .sys_clk_clk (sys_clk),
     .sys_rst_reset_n (sys_resetn));
 
diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl
index 75e3def09..14441c9f2 100644
--- a/projects/daq3/common/daq3_qsys.tcl
+++ b/projects/daq3/common/daq3_qsys.tcl
@@ -1,183 +1,68 @@
 
-# transmit-path (refclk)
+# ad9152-xcvr
 
-add_instance xcvr_tx_ref_clk altera_clock_bridge 16.0
-set_instance_parameter_value xcvr_tx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
+add_instance avl_ad9152_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_ad9152_xcvr {ID} {0}
+set_instance_parameter_value avl_ad9152_xcvr {TX_OR_RX_N} {1}
+set_instance_parameter_value avl_ad9152_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value avl_ad9152_xcvr {LANE_RATE} {10000.0}
+set_instance_parameter_value avl_ad9152_xcvr {PLLCLK_FREQUENCY} {5000.0}
+set_instance_parameter_value avl_ad9152_xcvr {REFCLK_FREQUENCY} {500.0}
+set_instance_parameter_value avl_ad9152_xcvr {CORECLK_FREQUENCY} {250.0}
+set_instance_parameter_value avl_ad9152_xcvr {NUM_OF_LANES} {4}
+set_instance_parameter_value avl_ad9152_xcvr {NUM_OF_CONVS} {2}
+set_instance_parameter_value avl_ad9152_xcvr {FRM_BCNT} {1}
+set_instance_parameter_value avl_ad9152_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_ad9152_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_ad9152_xcvr {HD} {1}
 
-# transmit-path (pll-core)
-
-add_instance xcvr_tx_pll altera_iopll 16.0
-add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 16.0
-set_instance_parameter_value xcvr_tx_pll {gui_en_reconf} {1}
-set_instance_parameter_value xcvr_tx_pll {gui_reference_clock_frequency} {500.0}
-set_instance_parameter_value xcvr_tx_pll {gui_use_locked} {0}
-set_instance_parameter_value xcvr_tx_pll {gui_output_clock_frequency0} {250.0}
-
-# transmit-path (pll-atx)
-
-add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 16.0
-set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_csr_soft_logic_enable} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {5000.0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {500.0}
-
-# receive-path (refclk)
-
-add_instance xcvr_rx_ref_clk altera_clock_bridge 16.0
-set_instance_parameter_value xcvr_rx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
-
-# receive-path (pll-core)
-
-add_instance xcvr_rx_pll altera_iopll 16.0
-add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 16.0
-set_instance_parameter_value xcvr_rx_pll {gui_en_reconf} {1}
-set_instance_parameter_value xcvr_rx_pll {gui_reference_clock_frequency} {500.0}
-set_instance_parameter_value xcvr_rx_pll {gui_use_locked} {0}
-set_instance_parameter_value xcvr_rx_pll {gui_output_clock_frequency0} {250.0}
-
-# transceiver-control
-
-add_instance axi_jesd_xcvr axi_jesd_xcvr 1.0
-set_instance_parameter_value axi_jesd_xcvr {DEVICE_TYPE} {0}
-set_instance_parameter_value axi_jesd_xcvr {TX_NUM_OF_LANES} {4}
-set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {4}
-
-# transceiver-reset
-
-add_instance xcvr_rst_cntrl altera_xcvr_reset_control 16.0
-set_instance_parameter_value xcvr_rst_cntrl {CHANNELS} {4}
-set_instance_parameter_value xcvr_rst_cntrl {SYS_CLK_IN_MHZ} {100}
-set_instance_parameter_value xcvr_rst_cntrl {TX_PLL_ENABLE} {1}
-set_instance_parameter_value xcvr_rst_cntrl {T_PLL_POWERDOWN} {1000}
-set_instance_parameter_value xcvr_rst_cntrl {TX_ENABLE} {1}
-set_instance_parameter_value xcvr_rst_cntrl {T_TX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_rst_cntrl {T_TX_DIGITALRESET} {70000}
-set_instance_parameter_value xcvr_rst_cntrl {gui_pll_cal_busy} {1}
-set_instance_parameter_value xcvr_rst_cntrl {RX_ENABLE} {1}
-set_instance_parameter_value xcvr_rst_cntrl {T_RX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_rst_cntrl {T_RX_DIGITALRESET} {4000}
-
-# transceiver-core (+ jesd)
-
-add_instance xcvr_core altera_jesd204 16.0
-set_instance_parameter_value xcvr_core {wrapper_opt} {base_phy}
-set_instance_parameter_value xcvr_core {DATA_PATH} {RX_TX}
-set_instance_parameter_value xcvr_core {lane_rate} {10000.0}
-set_instance_parameter_value xcvr_core {PCS_CONFIG} {JESD_PCS_CFG2}
-set_instance_parameter_value xcvr_core {bonded_mode} {non_bonded}
-set_instance_parameter_value xcvr_core {REFCLK_FREQ} {500.0}
-set_instance_parameter_value xcvr_core {pll_reconfig_enable} {1}
-set_instance_parameter_value xcvr_core {set_capability_reg_enable} {1}
-set_instance_parameter_value xcvr_core {set_csr_soft_logic_enable} {1}
-set_instance_parameter_value xcvr_core {L} {4}
-set_instance_parameter_value xcvr_core {M} {2}
-set_instance_parameter_value xcvr_core {GUI_EN_CFG_F} {1}
-set_instance_parameter_value xcvr_core {GUI_CFG_F} {1}
-set_instance_parameter_value xcvr_core {N} {16}
-set_instance_parameter_value xcvr_core {S} {1}
-set_instance_parameter_value xcvr_core {K} {32}
-set_instance_parameter_value xcvr_core {SCR} {1}
-set_instance_parameter_value xcvr_core {HD} {1}
-
-# transceiver + jesd interfaces
-
-add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_pll.refclk
-add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_lane_pll.pll_refclk0
+add_connection sys_clk.clk avl_ad9152_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_ad9152_xcvr.sys_resetn
 add_interface tx_ref_clk clock sink
-set_interface_property tx_ref_clk EXPORT_OF xcvr_tx_ref_clk.in_clk
-
-add_connection xcvr_rx_ref_clk.out_clk xcvr_rx_pll.refclk
-add_connection xcvr_rx_ref_clk.out_clk xcvr_core.rx_pll_ref_clk
-add_interface rx_ref_clk clock sink
-set_interface_property rx_ref_clk EXPORT_OF xcvr_rx_ref_clk.in_clk
-
-add_connection sys_clk.clk_reset xcvr_tx_pll.reset
-add_connection axi_jesd_xcvr.if_rst xcvr_tx_pll.reset
-add_connection xcvr_tx_pll.outclk0 xcvr_core.txlink_clk
-add_connection sys_clk.clk_reset xcvr_tx_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk xcvr_tx_pll_reconfig.mgmt_clk
-add_connection sys_cpu.data_master xcvr_tx_pll_reconfig.mgmt_avalon_slave
-add_connection xcvr_tx_pll_reconfig.reconfig_from_pll xcvr_tx_pll.reconfig_from_pll
-add_connection xcvr_tx_pll.reconfig_to_pll xcvr_tx_pll_reconfig.reconfig_to_pll
-
-add_connection sys_clk.clk_reset xcvr_rx_pll.reset
-add_connection axi_jesd_xcvr.if_rst xcvr_rx_pll.reset
-add_connection xcvr_rx_pll.outclk0 xcvr_core.rxlink_clk
-add_connection sys_clk.clk_reset xcvr_rx_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk xcvr_rx_pll_reconfig.mgmt_clk
-add_connection sys_cpu.data_master xcvr_rx_pll_reconfig.mgmt_avalon_slave
-add_connection xcvr_rx_pll.reconfig_from_pll xcvr_rx_pll_reconfig.reconfig_from_pll
-add_connection xcvr_rx_pll_reconfig.reconfig_to_pll xcvr_rx_pll.reconfig_to_pll
-
-add_connection xcvr_rst_cntrl.pll_powerdown xcvr_tx_lane_pll.pll_powerdown
-add_connection xcvr_tx_lane_pll.pll_cal_busy xcvr_rst_cntrl.pll_cal_busy
-add_connection xcvr_tx_lane_pll.pll_locked xcvr_rst_cntrl.pll_locked
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch0
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch1
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch2
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch3
-add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
-add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0
-add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
-
-add_connection sys_clk.clk_reset xcvr_rst_cntrl.reset
-add_connection sys_clk.clk xcvr_rst_cntrl.clock
-add_connection xcvr_rst_cntrl.tx_analogreset xcvr_core.tx_analogreset
-add_connection xcvr_rst_cntrl.tx_digitalreset xcvr_core.tx_digitalreset
-add_connection xcvr_rst_cntrl.tx_cal_busy xcvr_core.tx_cal_busy
-add_connection xcvr_rst_cntrl.rx_analogreset xcvr_core.rx_analogreset
-add_connection xcvr_rst_cntrl.rx_digitalreset xcvr_core.rx_digitalreset
-add_connection xcvr_rst_cntrl.rx_cal_busy xcvr_core.rx_cal_busy
-add_connection xcvr_rst_cntrl.rx_is_lockedtodata xcvr_core.rx_islockedtodata
-add_connection axi_jesd_xcvr.if_rst xcvr_rst_cntrl.reset
-add_connection xcvr_tx_pll.outclk0 axi_jesd_xcvr.if_tx_clk
-add_connection axi_jesd_xcvr.if_tx_rstn xcvr_core.txlink_rst_n
-add_connection axi_jesd_xcvr.if_tx_ready xcvr_rst_cntrl.tx_ready
-add_connection axi_jesd_xcvr.if_tx_ip_sysref xcvr_core.tx_sysref
-add_connection axi_jesd_xcvr.if_tx_ip_sync xcvr_core.sync_n
-add_connection axi_jesd_xcvr.if_tx_ip_avl xcvr_core.jesd204_tx_link
-add_connection xcvr_rx_pll.outclk0 axi_jesd_xcvr.if_rx_clk
-add_connection axi_jesd_xcvr.if_rx_rstn xcvr_core.rxlink_rst_n
-add_connection axi_jesd_xcvr.if_rx_ready xcvr_rst_cntrl.rx_ready
-add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_core.rx_sysref
-add_connection axi_jesd_xcvr.if_rx_ip_sync xcvr_core.rx_dev_sync_n
-add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
-add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
-add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
+set_interface_property tx_ref_clk EXPORT_OF avl_ad9152_xcvr.ref_clk
+add_interface tx_data_0 conduit end
+set_interface_property tx_data_0 EXPORT_OF avl_ad9152_xcvr.tx_data_0
+add_interface tx_data_1 conduit end
+set_interface_property tx_data_1 EXPORT_OF avl_ad9152_xcvr.tx_data_1
+add_interface tx_data_2 conduit end
+set_interface_property tx_data_2 EXPORT_OF avl_ad9152_xcvr.tx_data_2
+add_interface tx_data_3 conduit end
+set_interface_property tx_data_3 EXPORT_OF avl_ad9152_xcvr.tx_data_3
 add_interface tx_sysref conduit end
+set_interface_property tx_sysref EXPORT_OF avl_ad9152_xcvr.sysref
 add_interface tx_sync conduit end
-add_interface rx_sysref conduit end
-add_interface rx_sync conduit end
-set_interface_property tx_sysref EXPORT_OF axi_jesd_xcvr.if_tx_ext_sysref_in
-set_interface_property tx_sync EXPORT_OF axi_jesd_xcvr.if_tx_sync
-set_interface_property rx_sysref EXPORT_OF axi_jesd_xcvr.if_rx_ext_sysref_in
-set_interface_property rx_sync EXPORT_OF axi_jesd_xcvr.if_rx_sync
+set_interface_property tx_sync EXPORT_OF avl_ad9152_xcvr.sync
+add_connection avl_ad9152_xcvr.tx_phy_s_0 avl_ad9152_xcvr.tx_ip_s_0
+add_connection avl_ad9152_xcvr.tx_phy_s_1 avl_ad9152_xcvr.tx_ip_s_3
+add_connection avl_ad9152_xcvr.tx_phy_s_2 avl_ad9152_xcvr.tx_ip_s_1
+add_connection avl_ad9152_xcvr.tx_phy_s_3 avl_ad9152_xcvr.tx_ip_s_2
+add_connection avl_ad9152_xcvr.tx_ip_d_0 avl_ad9152_xcvr.tx_phy_d_0
+add_connection avl_ad9152_xcvr.tx_ip_d_3 avl_ad9152_xcvr.tx_phy_d_1
+add_connection avl_ad9152_xcvr.tx_ip_d_1 avl_ad9152_xcvr.tx_phy_d_2
+add_connection avl_ad9152_xcvr.tx_ip_d_2 avl_ad9152_xcvr.tx_phy_d_3
+add_connection sys_cpu.data_master avl_ad9152_xcvr.core_pll_reconfig
+add_connection sys_cpu.data_master avl_ad9152_xcvr.lane_pll_reconfig
+add_connection sys_cpu.data_master avl_ad9152_xcvr.ip_reconfig
 
-add_connection sys_clk.clk_reset xcvr_core.reconfig_reset
-add_connection sys_clk.clk xcvr_core.reconfig_clk
-add_connection sys_clk.clk_reset xcvr_core.jesd204_tx_avs_rst_n
-add_connection sys_clk.clk xcvr_core.jesd204_tx_avs_clk
-add_connection sys_clk.clk_reset xcvr_core.jesd204_rx_avs_rst_n
-add_connection sys_clk.clk xcvr_core.jesd204_rx_avs_clk
-add_connection xcvr_core.alldev_lane_aligned xcvr_core.dev_lane_aligned
-add_connection xcvr_core.tx_dev_sync_n xcvr_core.mdev_sync_n
-add_connection sys_cpu.data_master xcvr_core.reconfig_avmm
-add_connection sys_cpu.data_master xcvr_core.jesd204_tx_avs
-add_connection sys_cpu.data_master xcvr_core.jesd204_rx_avs
-add_interface tx_data conduit end
-add_interface rx_data conduit end
-set_interface_property tx_data EXPORT_OF xcvr_core.tx_serial_data
-set_interface_property rx_data EXPORT_OF xcvr_core.rx_serial_data
+add_instance axi_ad9152_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_ad9152_xcvr {ID} {0}
+set_instance_parameter_value axi_ad9152_xcvr {TX_OR_RX_N} {1}
+set_instance_parameter_value axi_ad9152_xcvr {NUM_OF_LANES} {4}
 
-# ad9152
+add_connection sys_clk.clk axi_ad9152_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9152_xcvr.s_axi_reset
+add_connection axi_ad9152_xcvr.if_up_rst avl_ad9152_xcvr.rst
+add_connection avl_ad9152_xcvr.ready axi_ad9152_xcvr.ready
+add_connection axi_ad9152_xcvr.core_pll_locked avl_ad9152_xcvr.core_pll_locked
+add_connection sys_cpu.data_master axi_ad9152_xcvr.s_axi
+
+# ad9152-core
 
 add_instance axi_ad9152_core axi_ad9152 1.0
-#set_instance_parameter_value axi_ad9152_core {QUAD_OR_DUAL_N} {0}
+set_instance_parameter_value axi_ad9152_core {DEVICE_TYPE} {1}
 
-add_connection xcvr_tx_pll.outclk0 axi_ad9152_core.if_tx_clk
-add_connection axi_jesd_xcvr.if_tx_data axi_ad9152_core.if_tx_data
+add_connection avl_ad9152_xcvr.core_clk axi_ad9152_core.if_tx_clk
+add_connection axi_ad9152_core.if_tx_data avl_ad9152_xcvr.ip_data
 add_connection sys_clk.clk_reset axi_ad9152_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9152_core.s_axi_clock
 add_connection sys_cpu.data_master axi_ad9152_core.s_axi
@@ -188,7 +73,7 @@ add_instance util_ad9152_upack util_upack 1.0
 set_instance_parameter_value util_ad9152_upack {CHANNEL_DATA_WIDTH} {64}
 set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} {2}
 
-add_connection xcvr_tx_pll.outclk0 util_ad9152_upack.if_dac_clk
+add_connection avl_ad9152_xcvr.core_clk util_ad9152_upack.if_dac_clk
 add_connection axi_ad9152_core.dac_ch_0 util_ad9152_upack.dac_ch_0
 add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1
 
@@ -201,7 +86,7 @@ set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0}
 set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {2}
 set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0}
 
-add_connection xcvr_tx_pll.outclk0 axi_ad9152_dma.if_fifo_rd_clk
+add_connection avl_ad9152_xcvr.core_clk axi_ad9152_dma.if_fifo_rd_clk
 add_connection util_ad9152_upack.if_dac_valid axi_ad9152_dma.if_fifo_rd_en
 add_connection util_ad9152_upack.if_dac_data axi_ad9152_dma.if_fifo_rd_dout
 add_connection axi_ad9152_dma.if_fifo_rd_underflow axi_ad9152_core.if_dac_dunf
@@ -213,18 +98,67 @@ add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9152_dma.m_src_axi_clock
 add_connection axi_ad9152_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
 add_connection sys_cpu.irq axi_ad9152_dma.interrupt_sender
 
+# ad9680-xcvr
+
+add_instance avl_ad9680_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_ad9680_xcvr {ID} {1}
+set_instance_parameter_value avl_ad9680_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value avl_ad9680_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value avl_ad9680_xcvr {LANE_RATE} {10000.0}
+set_instance_parameter_value avl_ad9680_xcvr {PLLCLK_FREQUENCY} {5000.0}
+set_instance_parameter_value avl_ad9680_xcvr {REFCLK_FREQUENCY} {500.0}
+set_instance_parameter_value avl_ad9680_xcvr {CORECLK_FREQUENCY} {250.0}
+set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_LANES} {4}
+set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_CONVS} {2}
+set_instance_parameter_value avl_ad9680_xcvr {FRM_BCNT} {1}
+set_instance_parameter_value avl_ad9680_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_ad9680_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_ad9680_xcvr {HD} {1}
+
+add_connection sys_clk.clk avl_ad9680_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_ad9680_xcvr.sys_resetn
+add_interface rx_ref_clk clock sink
+set_interface_property rx_ref_clk EXPORT_OF avl_ad9680_xcvr.ref_clk
+add_interface rx_data_0 conduit end
+set_interface_property rx_data_0 EXPORT_OF avl_ad9680_xcvr.rx_data_0
+add_interface rx_data_1 conduit end
+set_interface_property rx_data_1 EXPORT_OF avl_ad9680_xcvr.rx_data_1
+add_interface rx_data_2 conduit end
+set_interface_property rx_data_2 EXPORT_OF avl_ad9680_xcvr.rx_data_2
+add_interface rx_data_3 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_ad9680_xcvr.rx_data_3
+add_interface rx_sysref conduit end
+set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref
+add_interface rx_sync conduit end
+set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync
+add_connection sys_cpu.data_master avl_ad9680_xcvr.core_pll_reconfig
+add_connection sys_cpu.data_master avl_ad9680_xcvr.ip_reconfig
+
+# ad9680-xcvr
+
+add_instance axi_ad9680_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_ad9680_xcvr {ID} {1}
+set_instance_parameter_value axi_ad9680_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value axi_ad9680_xcvr {NUM_OF_LANES} {4}
+
+add_connection sys_clk.clk axi_ad9680_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset
+add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst
+add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready
+add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked
+add_connection sys_cpu.data_master axi_ad9680_xcvr.s_axi
+
 # ad9680
 
 add_instance axi_ad9680_core axi_ad9680 1.0
 
-add_connection xcvr_rx_pll.outclk0 axi_ad9680_core.if_rx_clk
+add_connection avl_ad9680_xcvr.core_clk axi_ad9680_core.if_rx_clk
+add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof
+add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
 add_connection sys_cpu.data_master axi_ad9680_core.s_axi
 
-add_connection xcvr_core.jesd204_rx_link axi_ad9680_core.if_rx_data
-add_connection xcvr_core.rx_sof axi_ad9680_core.if_rx_sof
-
 # ad9680-pack
 
 add_instance util_ad9680_cpack util_cpack 1.0
@@ -233,7 +167,7 @@ set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
 
 add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
 add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst
-add_connection xcvr_rx_pll.outclk0 util_ad9680_cpack.if_adc_clk
+add_connection avl_ad9680_xcvr.core_clk util_ad9680_cpack.if_adc_clk
 add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
 add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
 
@@ -246,7 +180,7 @@ set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
 
 add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
 add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst
-add_connection xcvr_rx_pll.outclk0 ad9680_adcfifo.if_adc_clk
+add_connection avl_ad9680_xcvr.core_clk ad9680_adcfifo.if_adc_clk
 add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
 add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
 add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk
@@ -262,8 +196,6 @@ set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {1}
 set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0}
 set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0}
 set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
-set_instance_parameter_value axi_ad9680_dma {FIFO_SIZE} {8}
-
 
 add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk
 add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid
@@ -279,23 +211,66 @@ add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
 add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
 add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
 
+# reconfig sharing
+
+add_instance avl_adxcfg_0 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
+add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s0
+add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s1
+add_connection avl_adxcfg_0.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_0
+add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0
+
+add_instance avl_adxcfg_1 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
+add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s0
+add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s1
+add_connection avl_adxcfg_1.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_1
+add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1
+
+add_instance avl_adxcfg_2 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
+add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s0
+add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s1
+add_connection avl_adxcfg_2.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_2
+add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2
+
+add_instance avl_adxcfg_3 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
+add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s0
+add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s1
+add_connection avl_adxcfg_3.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_3
+add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3
+
 # addresses
 
-set_connection_parameter_value sys_cpu.data_master/xcvr_rx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d800}
-set_connection_parameter_value sys_cpu.data_master/xcvr_tx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0        baseAddress {0x1003c000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi                   baseAddress {0x10034000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi                  baseAddress {0x10010000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9152_dma.s_axi                   baseAddress {0x10038000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9152_core.s_axi                  baseAddress {0x10020000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_core.reconfig_avmm                baseAddress {0x10030000}
-set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi                    baseAddress {0x10000000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_tx_avs               baseAddress {0x1003e000}
-set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_rx_avs               baseAddress {0x1003e400}
-set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9152_xcvr.core_pll_reconfig      baseAddress {0x10400000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9152_xcvr.ip_reconfig            baseAddress {0x10401000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9152_xcvr.lane_pll_reconfig      baseAddress {0x10402000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9152_dma.s_axi                   baseAddress {0x1040c000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9152_xcvr.s_axi                  baseAddress {0x10410000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9152_core.s_axi                  baseAddress {0x10420000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.core_pll_reconfig      baseAddress {0x10500000}
+set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.ip_reconfig            baseAddress {0x10501000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi                   baseAddress {0x1050c000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_xcvr.s_axi                  baseAddress {0x10510000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi                  baseAddress {0x10520000}
 set_connection_parameter_value axi_ad9152_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
+set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s0                   baseAddress {0x10404000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s0                   baseAddress {0x10405000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s0                   baseAddress {0x10406000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s0                   baseAddress {0x10407000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s1                   baseAddress {0x10504000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s1                   baseAddress {0x10505000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s1                   baseAddress {0x10506000}
+set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s1                   baseAddress {0x10507000}
 
 # interrupts
 
 set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}
 set_connection_parameter_value sys_cpu.irq/axi_ad9152_dma.interrupt_sender irqNumber {11}
+

From f34aa6702930e87ab022f9870b311d5567330dbb Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 10 Oct 2016 13:44:53 +0300
Subject: [PATCH 585/972] axi_hdmi: Fix a typo

---
 library/axi_hdmi_rx/axi_hdmi_rx_core.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_core.v b/library/axi_hdmi_rx/axi_hdmi_rx_core.v
index c1df3ab67..dc9e277cb 100644
--- a/library/axi_hdmi_rx/axi_hdmi_rx_core.v
+++ b/library/axi_hdmi_rx/axi_hdmi_rx_core.v
@@ -347,7 +347,7 @@ module axi_hdmi_rx_core (
     .hdmi_hs_de (hdmi_hs_de_s),
     .hdmi_data_de (hdmi_data_de_s));
 
-  // test patttern matcher
+  // test pattern matcher
 
   axi_hdmi_rx_tpm i_tpm (
     .hdmi_clk (hdmi_clk),

From ff980551e687a7dbec831657899ebcf58d79582c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 10 Oct 2016 16:38:42 +0300
Subject: [PATCH 586/972] ad_serdes: SERDES_FACTOR handover missing

In modules ad_serdes_in/ad_serdes_out the handover of the parameter
SERDES_FACTOR did not exist, causing unwanted behavioral in case of
factors less than 8.
SERDES_FACTOR must be hand over to DATA_WIDTH parameter of the SERDES
primitive.
---
 library/xilinx/common/ad_serdes_in.v  | 6 +++---
 library/xilinx/common/ad_serdes_out.v | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v
index 08ea2b4a6..84520379f 100644
--- a/library/xilinx/common/ad_serdes_in.v
+++ b/library/xilinx/common/ad_serdes_in.v
@@ -174,7 +174,7 @@ module ad_serdes_in #(
   if (DEVICE_TYPE == DEVICE_7SERIES) begin
   ISERDESE2  #(
     .DATA_RATE (DATA_RATE),
-    .DATA_WIDTH (8),
+    .DATA_WIDTH (SERDES_FACTOR),
     .DYN_CLKDIV_INV_EN ("FALSE"),
     .DYN_CLK_INV_EN ("FALSE"),
     .INIT_Q1 (1'b0),
@@ -223,7 +223,7 @@ module ad_serdes_in #(
   if (DEVICE_TYPE == DEVICE_6SERIES) begin
   ISERDESE1 #(
     .DATA_RATE (DATA_RATE),
-    .DATA_WIDTH (8),
+    .DATA_WIDTH (SERDES_FACTOR),
     .DYN_CLKDIV_INV_EN ("FALSE"),
     .DYN_CLK_INV_EN ("FALSE"),
     .INIT_Q1 (1'b0),
@@ -267,7 +267,7 @@ module ad_serdes_in #(
 
   ISERDESE1 #(
     .DATA_RATE (DATA_RATE),
-    .DATA_WIDTH (8),
+    .DATA_WIDTH (SERDES_FACTOR),
     .DYN_CLKDIV_INV_EN ("FALSE"),
     .DYN_CLK_INV_EN ("FALSE"),
     .INIT_Q1 (1'b0),
diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v
index c11072177..22b801b9e 100644
--- a/library/xilinx/common/ad_serdes_out.v
+++ b/library/xilinx/common/ad_serdes_out.v
@@ -84,7 +84,7 @@ module ad_serdes_out #(
       OSERDESE2  #(
         .DATA_RATE_OQ ("DDR"),
         .DATA_RATE_TQ ("SDR"),
-        .DATA_WIDTH (8),
+        .DATA_WIDTH (SERDES_FACTOR),
         .TRISTATE_WIDTH (1),
         .SERDES_MODE ("MASTER"))
       i_serdes (
@@ -121,7 +121,7 @@ module ad_serdes_out #(
       OSERDESE1  #(
         .DATA_RATE_OQ ("DDR"),
         .DATA_RATE_TQ ("SDR"),
-        .DATA_WIDTH (8),
+        .DATA_WIDTH (SERDES_FACTOR),
         .INTERFACE_TYPE ("DEFAULT"),
         .TRISTATE_WIDTH (1),
         .SERDES_MODE ("MASTER"))
@@ -158,7 +158,7 @@ module ad_serdes_out #(
       OSERDESE1  #(
         .DATA_RATE_OQ ("DDR"),
         .DATA_RATE_TQ ("SDR"),
-        .DATA_WIDTH (8),
+        .DATA_WIDTH (SERDES_FACTOR),
         .INTERFACE_TYPE ("DEFAULT"),
         .TRISTATE_WIDTH (1),
         .SERDES_MODE ("SLAVE"))

From 8875c5bef3841b365d020a8d7d6636f85f47d9b6 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 16:43:23 +0300
Subject: [PATCH 587/972] fmcomms6: ZC706, updated system_top to remove part of
 the Warnings

---
 projects/fmcomms6/zc706/system_top.v | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/fmcomms6/zc706/system_top.v b/projects/fmcomms6/zc706/system_top.v
index d2c0bd8d6..4c2565856 100644
--- a/projects/fmcomms6/zc706/system_top.v
+++ b/projects/fmcomms6/zc706/system_top.v
@@ -155,6 +155,9 @@ module system_top (
   wire            spi1_mosi;
   wire            spi1_miso;
 
+  assign gpio_i[63:33] = gpio_o[63:33];
+  assign gpio_i[31:15] = gpio_o[31:15];
+
   // spi
 
   assign spi_clk = spi0_clk;

From 121b341b45de4be281819be10e88916ea73facd6 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 17:30:13 +0300
Subject: [PATCH 588/972] axi_spdif_rx: Fixed version register issue. Added
 sampled_data to sensitivity list

---
 library/axi_spdif_rx/axi_spdif_rx.vhd | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/library/axi_spdif_rx/axi_spdif_rx.vhd b/library/axi_spdif_rx/axi_spdif_rx.vhd
index 5738ab596..88975beba 100644
--- a/library/axi_spdif_rx/axi_spdif_rx.vhd
+++ b/library/axi_spdif_rx/axi_spdif_rx.vhd
@@ -411,7 +411,6 @@ begin
   begin
     if rising_edge(S_AXI_ACLK) then
       if S_AXI_ARESETN = '0' then
-        version_reg <= (others => '0');
         control_reg <= (others => '0');
       else
         if wr_stb = '1' then
@@ -424,7 +423,7 @@ begin
     end if;
   end process;
 
-  process (rd_addr, version_reg, control_reg, chstatus_reg)
+  process (rd_addr, version_reg, control_reg, chstatus_reg, sampled_data)
   begin
     case rd_addr is
       when 0 => rd_data <= version_reg;

From 9efc45f0b6947fc388905486a69c908ec2dee48d Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 17:31:25 +0300
Subject: [PATCH 589/972] imageon: Zed, updated system_top to remove part of
 the Warnings.

- spi csn signals should be tied to 1 if spi is not used
- constraints fixed so Vivado doesn't issue a Warning
---
 projects/imageon/zed/system_constr.xdc | 2 +-
 projects/imageon/zed/system_top.v      | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/projects/imageon/zed/system_constr.xdc b/projects/imageon/zed/system_constr.xdc
index d94f1220b..220b0da90 100644
--- a/projects/imageon/zed/system_constr.xdc
+++ b/projects/imageon/zed/system_constr.xdc
@@ -50,7 +50,7 @@ set_property  -dict {PACKAGE_PIN   N20    IOSTANDARD LVCMOS25}    [get_ports  hd
 
 # clock definition
 
-create_clock -period 6.66667  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
+create_clock -period 6.667  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
 
 # i2s
 
diff --git a/projects/imageon/zed/system_top.v b/projects/imageon/zed/system_top.v
index 41c79230c..79a80762d 100644
--- a/projects/imageon/zed/system_top.v
+++ b/projects/imageon/zed/system_top.v
@@ -156,6 +156,8 @@ module system_top (
   wire    [ 1:0]  iic_mux_sda_o_s;
   wire            iic_mux_sda_t_s;
 
+  assign gpio_i[63:34] = gpio_o[63:34];
+
   // instantiations
 
   ad_iobuf #(.DATA_WIDTH(2)) i_gpio (
@@ -252,7 +254,7 @@ module system_top (
     .spi0_csn_0_o (),
     .spi0_csn_1_o (),
     .spi0_csn_2_o (),
-    .spi0_csn_i (1'b0),
+    .spi0_csn_i (1'b1),
     .spi0_sdi_i (1'b0),
     .spi0_sdo_i (1'b0),
     .spi0_sdo_o (),
@@ -261,7 +263,7 @@ module system_top (
     .spi1_csn_0_o (),
     .spi1_csn_1_o (),
     .spi1_csn_2_o (),
-    .spi1_csn_i (1'b0),
+    .spi1_csn_i (1'b1),
     .spi1_sdi_i (1'b0),
     .spi1_sdo_i (1'b0),
     .spi1_sdo_o ());

From b3d3876dc5dbabfc5d6b81e600abb7d3dbfd846b Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 10 Oct 2016 17:33:42 +0300
Subject: [PATCH 590/972] imageon: ZC706, updated system_top to remove part of
 the Warnings.

- constraints fixed so Vivado doesn't issue a Warning
---
 projects/imageon/zc706/system_constr.xdc | 2 +-
 projects/imageon/zc706/system_top.v      | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/projects/imageon/zc706/system_constr.xdc b/projects/imageon/zc706/system_constr.xdc
index 919fc0dd9..9d024d35d 100644
--- a/projects/imageon/zc706/system_constr.xdc
+++ b/projects/imageon/zc706/system_constr.xdc
@@ -50,7 +50,7 @@ set_property  -dict {PACKAGE_PIN   AG15   IOSTANDARD LVCMOS25}    [get_ports  hd
 
 # clock definition
 
-create_clock -period 6.66667  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
+create_clock -period 6.667  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
 
 # default constraints
 
diff --git a/projects/imageon/zc706/system_top.v b/projects/imageon/zc706/system_top.v
index 9cd1cd2f6..6d3b3318e 100644
--- a/projects/imageon/zc706/system_top.v
+++ b/projects/imageon/zc706/system_top.v
@@ -127,6 +127,9 @@ module system_top (
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
+  assign gpio_i[63:34] = gpio_o[63:34];
+  assign gpio_i[31:15] = gpio_o[31:15];
+
   // instantiations
 
   ad_iobuf #(.DATA_WIDTH(2)) i_gpio (

From cc6ca4f0f200e5fc7a7ac27fd5be48c4b26e6eda Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 10 Oct 2016 10:39:35 -0400
Subject: [PATCH 591/972] ad_lvds_in- ultrascale sim device

---
 library/xilinx/common/ad_lvds_in.v | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/library/xilinx/common/ad_lvds_in.v b/library/xilinx/common/ad_lvds_in.v
index 38d804ca2..b6f6ef257 100644
--- a/library/xilinx/common/ad_lvds_in.v
+++ b/library/xilinx/common/ad_lvds_in.v
@@ -108,11 +108,19 @@ module ad_lvds_in (
 
   generate
   if (IODELAY_CTRL == 1) begin
+  if (DEVICE_TYPE == ULTRASCALE) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl (
+    .RST (delay_rst),
+    .REFCLK (delay_clk),
+    .RDY (delay_locked));
+  end else begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
   IDELAYCTRL i_delay_ctrl (
     .RST (delay_rst),
     .REFCLK (delay_clk),
     .RDY (delay_locked));
+  end
   end else begin
   assign delay_locked = 1'b1;
   end
@@ -196,6 +204,7 @@ module ad_lvds_in (
   assign up_drdata = up_drdata_s[8:4];
   (* IODELAY_GROUP = IODELAY_GROUP *)
   IDELAYE3 #(
+    .SIM_DEVICE ("ULTRASCALE_PLUS_ES1"),
     .DELAY_SRC ("IDATAIN"),
     .DELAY_TYPE ("VAR_LOAD"),
     .REFCLK_FREQUENCY (200.0),

From 273073a584e78a3b0024d55bf33cb5cf460e18da Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 10 Oct 2016 11:12:34 -0400
Subject: [PATCH 592/972] daq2/kcu105- xcvr procedure

---
 projects/daq2/kcu105/system_bd.tcl     |  2 +-
 projects/daq2/kcu105/system_constr.xdc |  4 ++--
 projects/daq2/kcu105/system_top.v      | 12 ++++++------
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl
index 7b40605ee..c8e4c814d 100644
--- a/projects/daq2/kcu105/system_bd.tcl
+++ b/projects/daq2/kcu105/system_bd.tcl
@@ -8,7 +8,7 @@ p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
 
 source ../common/daq2_bd.tcl
 
-set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $util_daq2_xcvr
+set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq2_xcvr
 set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq2_xcvr
 set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq2_xcvr
 
diff --git a/projects/daq2/kcu105/system_constr.xdc b/projects/daq2/kcu105/system_constr.xdc
index ac806dd2d..3d2bc6a53 100644
--- a/projects/daq2/kcu105/system_constr.xdc
+++ b/projects/daq2/kcu105/system_constr.xdc
@@ -67,6 +67,6 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *
 set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}]
 set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}]
 
-set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9144_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
-set_false_path -from [get_cells i_system_wrapper/system_i/sys_ad9680_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9144_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v
index 4af3f1aa8..46331eaa8 100644
--- a/projects/daq2/kcu105/system_top.v
+++ b/projects/daq2/kcu105/system_top.v
@@ -332,9 +332,9 @@ module system_top (
     .rx_data_2_p (rx_data_p[2]),
     .rx_data_3_n (rx_data_n[3]),
     .rx_data_3_p (rx_data_p[3]),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .sgmii_rxn (phy_rx_n),
     .sgmii_rxp (phy_rx_p),
     .sgmii_txn (phy_tx_n),
@@ -357,9 +357,9 @@ module system_top (
     .tx_data_2_p (tx_data_p[2]),
     .tx_data_3_n (tx_data_n[3]),
     .tx_data_3_p (tx_data_p[3]),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref),
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (tx_sysref),
     .uart_sin (uart_sin),
     .uart_sout (uart_sout));
 

From e5cf417576a93f64f152a3f0a58ebf96c024c792 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 10 Oct 2016 12:51:30 -0400
Subject: [PATCH 593/972] daq2/mb- xcvr procedures

---
 projects/daq2/kc705/system_top.v | 12 ++++++------
 projects/daq2/vc707/system_top.v | 12 ++++++------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/projects/daq2/kc705/system_top.v b/projects/daq2/kc705/system_top.v
index 66a8137a2..aac500993 100644
--- a/projects/daq2/kc705/system_top.v
+++ b/projects/daq2/kc705/system_top.v
@@ -380,9 +380,9 @@ module system_top (
     .rx_data_2_p (rx_data_p[2]),
     .rx_data_3_n (rx_data_n[3]),
     .rx_data_3_p (rx_data_p[3]),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spi_clk_i (spi_clk),
     .spi_clk_o (spi_clk),
     .spi_csn_i (spi_csn),
@@ -401,9 +401,9 @@ module system_top (
     .tx_data_2_p (tx_data_p[2]),
     .tx_data_3_n (tx_data_n[3]),
     .tx_data_3_p (tx_data_p[3]),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref),
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (tx_sysref),
     .uart_sin (uart_sin),
     .uart_sout (uart_sout));
 
diff --git a/projects/daq2/vc707/system_top.v b/projects/daq2/vc707/system_top.v
index 1239a57e6..ad633cc7f 100644
--- a/projects/daq2/vc707/system_top.v
+++ b/projects/daq2/vc707/system_top.v
@@ -362,9 +362,9 @@ module system_top (
     .rx_data_2_p (rx_data_p[2]),
     .rx_data_3_n (rx_data_n[3]),
     .rx_data_3_p (rx_data_p[3]),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .sgmii_rxn (sgmii_rxn),
     .sgmii_rxp (sgmii_rxp),
     .sgmii_txn (sgmii_txn),
@@ -387,9 +387,9 @@ module system_top (
     .tx_data_2_p (tx_data_p[2]),
     .tx_data_3_n (tx_data_n[3]),
     .tx_data_3_p (tx_data_p[3]),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref),
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (tx_sysref),
     .uart_sin (uart_sin),
     .uart_sout (uart_sout));
 

From 905e29eb0143eccdec9a8b585d5c29d7f2e9dee5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 10 Oct 2016 12:55:55 -0400
Subject: [PATCH 594/972] hdlmake- altera

---
 projects/arradio/c5soc/Makefile     |  7 -------
 projects/daq2/a10gx/Makefile        | 11 -----------
 projects/daq3/a10gx/Makefile        |  5 +----
 projects/fmcjesdadc1/a5gt/Makefile  |  9 ---------
 projects/fmcjesdadc1/a5soc/Makefile |  7 -------
 projects/fmcomms2/a10gx/Makefile    | 11 -----------
 projects/usdrx1/a5gt/Makefile       |  8 --------
 7 files changed, 1 insertion(+), 57 deletions(-)

diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 78da3a934..165776141 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -27,13 +27,6 @@ M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
 M_DEPS += ../../../library/altera/common/ad_lvds_in.v
 M_DEPS += ../../../library/altera/common/ad_lvds_out.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
-M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
-M_DEPS += ../../../library/altera_hps/altera_hps_hw.tcl
-M_DEPS += ../../../library/altera_irq_bridge/altera_irq_bridge_hw.tcl
-M_DEPS += ../../../library/altera_pll/altera_pll_hw.tcl
-M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index 53b4fffc6..ccf31f48e 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -21,17 +21,6 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_mul.v
-M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
-M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
-M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
-M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
-M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
-M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
-M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
-M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
-M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index 190c0bc8c..ab104d4c5 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -31,6 +31,7 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
+M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr_hw.tcl
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
@@ -50,13 +51,10 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
-M_DEPS += ../../../library/common/ad_jesd_align.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
@@ -69,7 +67,6 @@ M_DEPS += ../../../library/common/up_clock_mon.v
 M_DEPS += ../../../library/common/up_dac_channel.v
 M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
 M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index 6de430a93..9f80abb77 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -20,15 +20,6 @@ M_DEPS += ../common/fmcjesdadc1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
-M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
-M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
-M_DEPS += ../../../library/altera_irq_bridge/altera_irq_bridge_hw.tcl
-M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
-M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
-M_DEPS += ../../../library/altera_pll/altera_pll_hw.tcl
-M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index d60b5f51e..99701e708 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -20,13 +20,6 @@ M_DEPS += ../common/fmcjesdadc1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5soc/a5soc_system_bd.qsys
 M_DEPS += ../../common/a5soc/a5soc_system_assign.tcl
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
-M_DEPS += ../../../library/altera_hps/altera_hps_hw.tcl
-M_DEPS += ../../../library/altera_irq_bridge/altera_irq_bridge_hw.tcl
-M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
-M_DEPS += ../../../library/altera_pll/altera_pll_hw.tcl
-M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 29c327f15..9ce6cb4a7 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -27,17 +27,6 @@ M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
 M_DEPS += ../../../library/altera/common/ad_lvds_in.v
 M_DEPS += ../../../library/altera/common/ad_lvds_out.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
-M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
-M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
-M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
-M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
-M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
-M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
-M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
-M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
-M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index 7615b7656..8850eed3e 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -18,14 +18,6 @@ M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
 M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v
 M_DEPS += ../../../library/common/altera/ad_jesd_align.v
-M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
-M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
-M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
-M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
-M_DEPS += ../../../library/altera_irq_bridge/altera_irq_bridge_hw.tcl
-M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
-M_DEPS += ../../../library/altera_pll/altera_pll_hw.tcl
-M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 

From 5bb77109ca009c68f25c241ecabdade7467fa8a1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 10 Oct 2016 13:03:44 -0400
Subject: [PATCH 595/972] daq2/a10gx- make fix

---
 projects/daq2/a10gx/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index ccf31f48e..9b0cc3321 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -31,7 +31,7 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
-M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v

From 7194d2eccc18f6e9fe5d9ad1beadda50edcca048 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 16:34:58 +0300
Subject: [PATCH 596/972] axi_ad9361: Grup interfaces to add support for more
 carriers

---
 library/axi_ad9361/axi_ad9361_ip.tcl          |  4 +-
 .../{ => xilinx}/axi_ad9361_cmos_if.v         | 10 ++--
 .../{ => xilinx}/axi_ad9361_lvds_if.v         | 46 ++++++++++++++++---
 3 files changed, 47 insertions(+), 13 deletions(-)
 rename library/axi_ad9361/{ => xilinx}/axi_ad9361_cmos_if.v (99%)
 rename library/axi_ad9361/{ => xilinx}/axi_ad9361_lvds_if.v (96%)

diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl
index f18ba9d09..e70ad8387 100755
--- a/library/axi_ad9361/axi_ad9361_ip.tcl
+++ b/library/axi_ad9361/axi_ad9361_ip.tcl
@@ -34,8 +34,8 @@ adi_ip_files axi_ad9361 [list \
   "$ad_hdl_dir/library/common/up_dac_channel.v" \
   "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
   "axi_ad9361_constr.xdc" \
-  "axi_ad9361_lvds_if.v" \
-  "axi_ad9361_cmos_if.v" \
+  "xilinx/axi_ad9361_lvds_if.v" \
+  "xilinx/axi_ad9361_cmos_if.v" \
   "axi_ad9361_rx_pnmon.v" \
   "axi_ad9361_rx_channel.v" \
   "axi_ad9361_rx.v" \
diff --git a/library/axi_ad9361/axi_ad9361_cmos_if.v b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
similarity index 99%
rename from library/axi_ad9361/axi_ad9361_cmos_if.v
rename to library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
index e54935390..0ce506d71 100644
--- a/library/axi_ad9361/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
diff --git a/library/axi_ad9361/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
similarity index 96%
rename from library/axi_ad9361/axi_ad9361_lvds_if.v
rename to library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
index cd74b05f0..05c84d27a 100644
--- a/library/axi_ad9361/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -103,7 +103,17 @@ module axi_ad9361_lvds_if (
   up_dac_drdata,
   delay_clk,
   delay_rst,
-  delay_locked);
+  delay_locked,
+
+  //drp interface
+
+  up_drp_sel,
+  up_drp_wr,
+  up_drp_addr,
+  up_drp_wdata,
+  up_drp_rdata,
+  up_drp_ready,
+  up_drp_locked);
 
   // this parameter controls the buffer type based on the target device.
 
@@ -177,6 +187,16 @@ module axi_ad9361_lvds_if (
   input           delay_rst;
   output          delay_locked;
 
+  //drp interface
+
+  input               up_drp_sel;
+  input               up_drp_wr;
+  input   [11:0]      up_drp_addr;
+  input   [31:0]      up_drp_wdata;
+  output  [31:0]      up_drp_rdata;
+  output              up_drp_ready;
+  output              up_drp_locked;
+
   // internal registers
 
   reg     [ 5:0]  rx_data_p = 0;
@@ -245,6 +265,12 @@ module axi_ad9361_lvds_if (
   wire            rx_frame_n_s;
   wire            locked_s;
 
+  // drp interface signals
+
+  assign up_drp_rdata = 32'd0;
+  assign up_drp_ready = 1'd0;
+  assign up_drp_locked = 1'd1;
+
   genvar          l_inst;
 
   // receive data path interface
@@ -633,6 +659,14 @@ module axi_ad9361_lvds_if (
     .clk_in_n (rx_clk_in_n),
     .clk (l_clk));
 
+  // debug
+	ila_TEST_DAC_MODE ila_dac_mode (
+	.clk(clk),
+	.probe0(dac_r1_mode),
+	.probe1(dac_valid));
+
+// end debug
+
 endmodule
 
 // ***************************************************************************

From 52194f0fea09262218e3926f1e3c1bc69b6c364e Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 16:38:42 +0300
Subject: [PATCH 597/972] axi_ad9361: Add DRP connection to the interface
 module

---
 library/axi_ad9361/axi_ad9361.v    | 22 ++++++++++++++++++++--
 library/axi_ad9361/axi_ad9361_rx.v | 26 ++++++++++++++++++--------
 2 files changed, 38 insertions(+), 10 deletions(-)

diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index f3101e55a..8927db039 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -292,6 +292,10 @@ module axi_ad9361 #(
   assign tx_data_out_p = 6'h00;
   assign tx_data_out_n = 6'h3f;
 
+  assign up_drp_rdata = 32'd0;
+  assign up_drp_ready = 1'd0;
+  assign up_drp_locked = 1'd1;
+
   axi_ad9361_cmos_if #(
     .DEVICE_TYPE (DEVICE_TYPE),
     .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
@@ -391,7 +395,14 @@ module axi_ad9361 #(
     .up_dac_drdata (up_dac_drdata_s[49:0]),
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
-    .delay_locked (delay_locked_s));
+    .delay_locked (delay_locked_s),
+    .up_drp_sel (up_drp_sel),
+    .up_drp_wr (up_drp_wr),
+    .up_drp_addr (up_drp_addr),
+    .up_drp_wdata (up_drp_wdata),
+    .up_drp_rdata (up_drp_rdata),
+    .up_drp_ready (up_drp_ready),
+    .up_drp_locked(up_drp_locked));
   end
   endgenerate
 
@@ -524,7 +535,14 @@ module axi_ad9361 #(
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata_rx_s),
-    .up_rack (up_rack_rx_s));
+    .up_rack (up_rack_rx_s),
+    .up_drp_sel (up_drp_sel),
+    .up_drp_wr (up_drp_wr),
+    .up_drp_addr (up_drp_addr),
+    .up_drp_wdata (up_drp_wdata),
+    .up_drp_rdata (up_drp_rdata),
+    .up_drp_ready (up_drp_ready),
+    .up_drp_locked(up_drp_locked));
 
   // transmit
 
diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v
index 133850bea..589c9b648 100644
--- a/library/axi_ad9361/axi_ad9361_rx.v
+++ b/library/axi_ad9361/axi_ad9361_rx.v
@@ -106,7 +106,17 @@ module axi_ad9361_rx #(
   input           up_rreq,
   input   [13:0]  up_raddr,
   output  [31:0]  up_rdata,
-  output          up_rack);
+  output          up_rack,
+
+  // drp interface
+
+  output          up_drp_sel,
+  output          up_drp_wr,
+  output   [11:0] up_drp_addr,
+  output   [31:0] up_drp_wdata,
+  input    [31:0] up_drp_rdata,
+  input           up_drp_ready,
+  input           up_drp_locked);
 
   // configuration settings
 
@@ -335,13 +345,13 @@ module axi_ad9361_rx #(
     .up_status_pn_err (up_status_pn_err),
     .up_status_pn_oos (up_status_pn_oos),
     .up_status_or (up_status_or),
-    .up_drp_sel (),
-    .up_drp_wr (),
-    .up_drp_addr (),
-    .up_drp_wdata (),
-    .up_drp_rdata (32'd0),
-    .up_drp_ready (1'd0),
-    .up_drp_locked (1'd1),
+    .up_drp_sel (up_drp_sel),
+    .up_drp_wr (up_drp_wr),
+    .up_drp_addr (up_drp_addr),
+    .up_drp_wdata (up_drp_wdata),
+    .up_drp_rdata (up_drp_rdata),
+    .up_drp_ready (up_drp_ready),
+    .up_drp_locked (up_drp_locked),
     .up_usr_chanmax (),
     .adc_usr_chanmax (8'd3),
     .up_adc_gpio_in (up_adc_gpio_in),

From d41945f568f1a57bb2abe8fc8850722ee21a1770 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 17:02:46 +0300
Subject: [PATCH 598/972] altera/ad_serdes: Add support for any SERDES factor
 less than 8

---
 library/altera/common/ad_serdes_in.v  | 33 ++++++++++++++++-------
 library/altera/common/ad_serdes_out.v | 39 ++++++++++++++++++++-------
 2 files changed, 54 insertions(+), 18 deletions(-)

diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index a84bb0c8c..20716cf1e 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -43,6 +43,7 @@ module ad_serdes_in #(
   // parameters
 
   parameter   DEVICE_TYPE = 0,
+  parameter   SERDES_FACTOR = 8,
   parameter   DATA_WIDTH = 16) (
 
   // reset and clocks
@@ -83,17 +84,31 @@ module ad_serdes_in #(
   // internal signals
 
   wire    [(DATA_WIDTH-1):0]      delay_locked_s;
+  wire    [(DATA_WIDTH-1):0]      data_out_s[ 7:0];
+  wire    [(DATA_WIDTH-1):0]      data_sel_s[ 7:0];
 
   // assignments
 
   assign up_drdata = 5'd0;
   assign delay_locked = & delay_locked_s;
 
+  assign data_s0 = data_sel_s[0];
+  assign data_s1 = data_sel_s[1];
+  assign data_s2 = data_sel_s[2];
+  assign data_s3 = data_sel_s[3];
+  assign data_s4 = data_sel_s[4];
+  assign data_s5 = data_sel_s[5];
+  assign data_s6 = data_sel_s[6];
+  assign data_s7 = data_sel_s[7];
+
   // instantiations
 
-  genvar l_inst;
+  genvar l_inst, l_order;
   generate
   for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
+    for (l_order = 0; l_order < SERDES_FACTOR; l_order = l_order + 1) begin: g_order
+      assign data_sel_s[l_order][l_inst] = data_out_s[8 - SERDES_FACTOR + l_order][l_inst];
+    end
   alt_serdes_in_core i_core (
     .clk_export (clk),
     .div_clk_export (div_clk),
@@ -101,14 +116,14 @@ module ad_serdes_in #(
     .loaden_export (loaden),
     .locked_export (locked),
     .data_in_export (data_in_p[l_inst]),
-    .data_s_export ({ data_s0[l_inst],
-                      data_s1[l_inst],
-                      data_s2[l_inst],
-                      data_s3[l_inst],
-                      data_s4[l_inst],
-                      data_s5[l_inst],
-                      data_s6[l_inst],
-                      data_s7[l_inst]}),
+    .data_s_export ({data_out_s[0][l_inst],
+                     data_out_s[1][l_inst],
+                     data_out_s[2][l_inst],
+                     data_out_s[3][l_inst],
+                     data_out_s[4][l_inst],
+                     data_out_s[5][l_inst],
+                     data_out_s[6][l_inst],
+                     data_out_s[7][l_inst]}),
     .delay_locked_export (delay_locked_s[l_inst]));
   end
   endgenerate
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index c5a9ac648..6857b5fd5 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -41,6 +41,7 @@
 module ad_serdes_out #(
 
   parameter   DEVICE_TYPE = 0,
+  parameter   SERDES_FACTOR = 8,
   parameter   DATA_WIDTH = 16) (
 
   // reset and clocks
@@ -63,29 +64,49 @@ module ad_serdes_out #(
   output  [(DATA_WIDTH-1):0]  data_out_p,
   output  [(DATA_WIDTH-1):0]  data_out_n);
 
+  // internal signals
+
+  wire    [(DATA_WIDTH-1):0]  data_in_s[ 7:0];
+  wire    [(DATA_WIDTH-1):0]  data_in_s2[ 7:0];
+
   // defaults
 
   assign data_out_n = 'd0;
 
   // instantiations
 
+    assign data_in_s[0] = data_s0;
+    assign data_in_s[1] = data_s1;
+    assign data_in_s[2] = data_s2;
+    assign data_in_s[3] = data_s3;
+    assign data_in_s[4] = data_s4;
+    assign data_in_s[5] = data_s5;
+    assign data_in_s[6] = data_s6;
+    assign data_in_s[7] = data_s7;
+
+  genvar l_order;
+  generate
+    for (l_order = 0; l_order < 8; l_order = l_order + 1) begin: g_order
+      assign data_in_s2[l_order] = (l_order < 8-SERDES_FACTOR) ? 1'b0 : data_in_s[l_order -8 + SERDES_FACTOR];
+    end
+  endgenerate
+
   genvar l_inst;
   generate
   for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
-
     alt_serdes_out_core i_core (
       .clk_export (clk),
       .div_clk_export (div_clk),
       .loaden_export (loaden),
       .data_out_export (data_out_p[l_inst]),
-      .data_s_export ({ data_s0[l_inst],
-                        data_s1[l_inst],
-                        data_s2[l_inst],
-                        data_s3[l_inst],
-                        data_s4[l_inst],
-                        data_s5[l_inst],
-                        data_s6[l_inst],
-                        data_s7[l_inst]}));
+      .data_s_export ({data_in_s2[0][l_inst],
+                       data_in_s2[1][l_inst],
+                       data_in_s2[2][l_inst],
+                       data_in_s2[3][l_inst],
+                       data_in_s2[4][l_inst],
+                       data_in_s2[5][l_inst],
+                       data_in_s2[6][l_inst],
+                       data_in_s2[7][l_inst]}));
   end
   endgenerate
 

From ae47895666988039922f43b6554ba1c3f7f92599 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 17:09:39 +0300
Subject: [PATCH 599/972] altera/alt_serdes: Fixed SERDES 4 factor
 initialization

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index 3aa7a5374..abd523dc9 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -47,9 +47,13 @@ proc p_alt_serdes {} {
 
   set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
   set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
-  set m_ls_phase 315.0
+  set m_ls_phase 22.5
+  set m_ld_phase 315.0
+  set m_ld_duty_cycle 12.5
   if {$m_serdes_factor == 4} {
-    set m_ls_phase 270.0
+    set m_ls_phase 45
+    set m_ld_phase 270.0
+    set m_ld_duty_cycle 25.0
   }
 
   if {$m_mode == "CLK"} {
@@ -66,9 +70,10 @@ proc p_alt_serdes {} {
     set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
     set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
     set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
-    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ls_phase
-    set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} {12.5}
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
+    set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
     set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
     set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
     add_interface rst reset sink
     set_interface_property rst EXPORT_OF alt_serdes_pll.reset
@@ -148,5 +153,3 @@ proc p_alt_serdes {} {
     set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
   }
 }
-
-

From 369dad60b0928667b8e0d438591f1a6a46cb95bb Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 17:16:45 +0300
Subject: [PATCH 600/972] axi_ad9361: Add Altera SERDES interface support

---
 .../axi_ad9361/altera/axi_ad9361_cmos_if.v    | 583 ++++++++++++++++++
 .../axi_ad9361/altera/axi_ad9361_lvds_if.v    | 567 +++++++++++++++++
 library/axi_ad9361/axi_ad9361_hw.tcl          |  33 +-
 3 files changed, 1172 insertions(+), 11 deletions(-)
 create mode 100644 library/axi_ad9361/altera/axi_ad9361_cmos_if.v
 create mode 100644 library/axi_ad9361/altera/axi_ad9361_lvds_if.v

diff --git a/library/axi_ad9361/altera/axi_ad9361_cmos_if.v b/library/axi_ad9361/altera/axi_ad9361_cmos_if.v
new file mode 100644
index 000000000..0ce506d71
--- /dev/null
+++ b/library/axi_ad9361/altera/axi_ad9361_cmos_if.v
@@ -0,0 +1,583 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9361_cmos_if (
+
+  // physical interface (receive)
+
+  rx_clk_in,
+  rx_frame_in,
+  rx_data_in,
+
+  // physical interface (transmit)
+
+  tx_clk_out,
+  tx_frame_out,
+  tx_data_out,
+
+  // ensm control
+
+  enable,
+  txnrx,
+
+  // clock (common to both receive and transmit)
+
+  rst,
+  clk,
+  l_clk,
+
+  // receive data path interface
+
+  adc_valid,
+  adc_data,
+  adc_status,
+  adc_r1_mode,
+  adc_ddr_edgesel,
+
+  // transmit data path interface
+
+  dac_valid,
+  dac_data,
+  dac_clksel,
+  dac_r1_mode,
+
+  // tdd interface
+
+  tdd_enable,
+  tdd_txnrx,
+  tdd_mode,
+
+  // delay interface
+
+  mmcm_rst,
+  up_clk,
+  up_enable,
+  up_txnrx,
+  up_adc_dld,
+  up_adc_dwdata,
+  up_adc_drdata,
+  up_dac_dld,
+  up_dac_dwdata,
+  up_dac_drdata,
+  delay_clk,
+  delay_rst,
+  delay_locked);
+
+  // this parameter controls the buffer type based on the target device.
+
+  parameter   DEVICE_TYPE = 0;
+  parameter   DAC_IODELAY_ENABLE = 0;
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group";
+
+  // physical interface (receive)
+
+  input           rx_clk_in;
+  input           rx_frame_in;
+  input   [11:0]  rx_data_in;
+
+  // physical interface (transmit)
+
+  output          tx_clk_out;
+  output          tx_frame_out;
+  output  [11:0]  tx_data_out;
+
+  // ensm control
+
+  output          enable;
+  output          txnrx;
+
+  // clock (common to both receive and transmit)
+
+  input           rst;
+  input           clk;
+  output          l_clk;
+
+  // receive data path interface
+
+  output          adc_valid;
+  output  [47:0]  adc_data;
+  output          adc_status;
+  input           adc_r1_mode;
+  input           adc_ddr_edgesel;
+
+  // transmit data path interface
+
+  input           dac_valid;
+  input   [47:0]  dac_data;
+  input           dac_clksel;
+  input           dac_r1_mode;
+
+  // tdd interface
+
+  input           tdd_enable;
+  input           tdd_txnrx;
+  input           tdd_mode;
+
+  // delay interface
+
+  input           mmcm_rst;
+  input           up_clk;
+  input           up_enable;
+  input           up_txnrx;
+  input   [12:0]  up_adc_dld;
+  input   [64:0]  up_adc_dwdata;
+  output  [64:0]  up_adc_drdata;
+  input   [15:0]  up_dac_dld;
+  input   [79:0]  up_dac_dwdata;
+  output  [79:0]  up_dac_drdata;
+  input           delay_clk;
+  input           delay_rst;
+  output          delay_locked;
+
+  // internal registers
+
+  reg     [ 1:0]  rx_frame = 0;
+  reg     [11:0]  rx_data_p = 0;
+  reg             rx_error_r1 = 'd0;
+  reg             rx_valid_r1 = 'd0;
+  reg     [23:0]  rx_data_r1 = 'd0;
+  reg             rx_error_r2 = 'd0;
+  reg             rx_valid_r2 = 'd0;
+  reg     [47:0]  rx_data_r2 = 'd0;
+  reg             adc_p_valid = 'd0;
+  reg     [47:0]  adc_p_data = 'd0;
+  reg             adc_p_status = 'd0;
+  reg             adc_n_valid = 'd0;
+  reg     [47:0]  adc_n_data = 'd0;
+  reg             adc_n_status = 'd0;
+  reg             adc_valid_int = 'd0;
+  reg     [47:0]  adc_data_int = 'd0;
+  reg             adc_status_int = 'd0;
+  reg             adc_valid = 'd0;
+  reg     [47:0]  adc_data = 'd0;
+  reg             adc_status = 'd0;
+  reg     [ 1:0]  tx_data_cnt = 'd0;
+  reg     [47:0]  tx_data = 'd0;
+  reg             tx_frame_p = 'd0;
+  reg             tx_frame_n = 'd0;
+  reg     [11:0]  tx_data_p = 'd0;
+  reg     [11:0]  tx_data_n = 'd0;
+  reg             tx_n_frame_p = 'd0;
+  reg             tx_n_frame_n = 'd0;
+  reg     [11:0]  tx_n_data_p = 'd0;
+  reg     [11:0]  tx_n_data_n = 'd0;
+  reg             tx_p_frame_p = 'd0;
+  reg             tx_p_frame_n = 'd0;
+  reg     [11:0]  tx_p_data_p = 'd0;
+  reg     [11:0]  tx_p_data_n = 'd0;
+  reg             up_enable_int = 'd0;
+  reg             up_txnrx_int = 'd0;
+  reg             enable_up_m1 = 'd0;
+  reg             txnrx_up_m1 = 'd0;
+  reg             enable_up = 'd0;
+  reg             txnrx_up = 'd0;
+  reg             enable_int = 'd0;
+  reg             txnrx_int = 'd0;
+  reg             enable_n_int = 'd0;
+  reg             txnrx_n_int = 'd0;
+  reg             enable_p_int = 'd0;
+  reg             txnrx_p_int = 'd0;
+  reg             dac_clkdata_p = 'd0;
+  reg             dac_clkdata_n = 'd0;
+  reg             locked_m1 = 'd0;
+  reg             locked = 'd0;
+
+  // internal signals
+
+  wire    [ 1:0]  rx_frame_s;
+  wire    [ 3:0]  rx_frame_4_s;
+  wire    [ 2:0]  tx_data_sel_s;
+  wire    [11:0]  rx_data_p_s;
+  wire    [11:0]  rx_data_n_s;
+  wire            rx_frame_p_s;
+  wire            rx_frame_n_s;
+  wire            locked_s;
+
+  genvar          l_inst;
+
+  // receive data path interface
+
+  assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s};
+  assign rx_frame_4_s = {rx_frame_s, rx_frame};
+
+  always @(posedge l_clk) begin
+    rx_frame <= rx_frame_s;
+    rx_data_p <= rx_data_p_s;
+  end
+
+  // receive data path for single rf, frame is expected to qualify i only
+
+  always @(posedge l_clk) begin
+    rx_error_r1 <= ~^ rx_frame_s;
+    rx_valid_r1 <= ^ rx_frame_s;
+    case (rx_frame_s)
+      2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s};
+      2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p};
+      default: rx_data_r1 <= 24'd0;
+    endcase
+  end
+
+  // receive data path for dual rf, frame is expected to qualify iq for rf-1 only
+
+  always @(posedge l_clk) begin
+    rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) ||
+      (rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1;
+    rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) ||
+      (rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0;
+    case (rx_frame_s)
+      2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s};
+      2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p};
+      default: rx_data_r2[23: 0] <= rx_data_r2[23: 0];
+    endcase
+    case (rx_frame_s)
+      2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s};
+      2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p};
+      default: rx_data_r2[47:24] <= rx_data_r2[47:24];
+    endcase
+  end
+
+  // receive data path mux
+
+  always @(posedge l_clk) begin
+    if (adc_r1_mode == 1'b1) begin
+      adc_p_valid <= rx_valid_r1;
+      adc_p_data <= {24'd0, rx_data_r1};
+      adc_p_status <= ~rx_error_r1;
+    end else begin
+      adc_p_valid <= rx_valid_r2;
+      adc_p_data <= rx_data_r2;
+      adc_p_status <= ~rx_error_r2;
+    end
+  end
+
+  // transfer to a synchronous common clock
+
+  always @(negedge l_clk) begin
+    adc_n_valid <= adc_p_valid;
+    adc_n_data <= adc_p_data;
+    adc_n_status <= adc_p_status;
+  end
+
+  always @(posedge clk) begin
+    adc_valid_int <= adc_n_valid;
+    adc_data_int <= adc_n_data;
+    adc_status_int <= adc_n_status;
+    adc_valid <= adc_valid_int;
+    if (adc_valid_int == 1'b1) begin
+      adc_data <= adc_data_int;
+    end
+    adc_status <= adc_status_int & locked;
+  end
+
+  // transmit data path mux (reverse of what receive does above)
+  // the count simply selets the data muxing on the ddr outputs
+
+  assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]};
+
+  always @(posedge clk) begin
+    if (dac_valid == 1'b1) begin
+      tx_data_cnt <= 2'b10;
+    end else if (tx_data_cnt[1] == 1'b1) begin
+      tx_data_cnt <= tx_data_cnt + 1'b1;
+    end
+    if (dac_valid == 1'b1) begin
+      tx_data <= dac_data;
+    end
+    case (tx_data_sel_s)
+      3'b101: begin
+        tx_frame_p <= 1'b0;
+        tx_frame_n <= 1'b0;
+        tx_data_p <= tx_data[35:24];
+        tx_data_n <= tx_data[47:36];
+      end
+      3'b100: begin
+        tx_frame_p <= 1'b1;
+        tx_frame_n <= 1'b1;
+        tx_data_p <= tx_data[11: 0];
+        tx_data_n <= tx_data[23:12];
+      end
+      3'b110: begin
+        tx_frame_p <= 1'b1;
+        tx_frame_n <= 1'b0;
+        tx_data_p <= tx_data[11: 0];
+        tx_data_n <= tx_data[23:12];
+      end
+      default: begin
+        tx_frame_p <= 1'd0;
+        tx_frame_n <= 1'd0;
+        tx_data_p <= 12'd0;
+        tx_data_n <= 12'd0;
+      end
+    endcase
+  end
+
+  // transfer data from a synchronous clock (skew less than 2ns)
+
+  always @(negedge clk) begin
+    tx_n_frame_p <= tx_frame_p;
+    tx_n_frame_n <= tx_frame_n;
+    tx_n_data_p <= tx_data_p;
+    tx_n_data_n <= tx_data_n;
+  end
+
+  always @(posedge l_clk) begin
+    tx_p_frame_p <= tx_n_frame_p;
+    tx_p_frame_n <= tx_n_frame_n;
+    tx_p_data_p <= tx_n_data_p;
+    tx_p_data_n <= tx_n_data_n;
+  end
+
+  // tdd/ensm control
+
+  always @(posedge up_clk) begin
+    up_enable_int <= up_enable;
+    up_txnrx_int <= up_txnrx;
+  end
+
+  always @(posedge clk or posedge rst) begin
+    if (rst == 1'b1) begin
+      enable_up_m1 <= 1'b0;
+      txnrx_up_m1 <= 1'b0;
+      enable_up <= 1'b0;
+      txnrx_up <= 1'b0;
+    end else begin
+      enable_up_m1 <= up_enable_int;
+      txnrx_up_m1 <= up_txnrx_int;
+      enable_up <= enable_up_m1;
+      txnrx_up <= txnrx_up_m1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (tdd_mode == 1'b1) begin
+      enable_int <= tdd_enable;
+      txnrx_int <= tdd_txnrx;
+    end else begin
+      enable_int <= enable_up;
+      txnrx_int <= txnrx_up;
+    end
+  end
+
+  always @(negedge clk) begin
+    enable_n_int <= enable_int;
+    txnrx_n_int <= txnrx_int;
+  end
+
+  always @(posedge l_clk) begin
+    enable_p_int <= enable_n_int;
+    txnrx_p_int <= txnrx_n_int;
+  end
+
+  always @(posedge l_clk) begin
+    dac_clkdata_p <= dac_clksel;
+    dac_clkdata_n <= ~dac_clksel;
+  end
+
+  // receive data interface, ibuf -> idelay -> iddr
+
+  generate
+  for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
+  ad_cmos_in #(
+    .SINGLE_ENDED (1),
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_rx_data (
+    .rx_clk (l_clk),
+    .rx_data_in (rx_data_in[l_inst]),
+    .rx_data_p (rx_data_p_s[l_inst]),
+    .rx_data_n (rx_data_n_s[l_inst]),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[l_inst]),
+    .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+  end
+  endgenerate
+
+  // receive frame interface, ibuf -> idelay -> iddr
+
+  ad_cmos_in #(
+    .SINGLE_ENDED (1),
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .IODELAY_CTRL (1),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_rx_frame (
+    .rx_clk (l_clk),
+    .rx_data_in (rx_frame_in),
+    .rx_data_p (rx_frame_p_s),
+    .rx_data_n (rx_frame_n_s),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[12]),
+    .up_dwdata (up_adc_dwdata[64:60]),
+    .up_drdata (up_adc_drdata[64:60]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked));
+
+  // transmit data interface, oddr -> obuf
+
+  generate
+  for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_data (
+    .tx_clk (l_clk),
+    .tx_data_p (tx_p_data_p[l_inst]),
+    .tx_data_n (tx_p_data_n[l_inst]),
+    .tx_data_out (tx_data_out[l_inst]),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[l_inst]),
+    .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+  end
+  endgenerate
+
+  // transmit frame interface, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_frame (
+    .tx_clk (l_clk),
+    .tx_data_p (tx_p_frame_p),
+    .tx_data_n (tx_p_frame_n),
+    .tx_data_out (tx_frame_out),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[12]),
+    .up_dwdata (up_dac_dwdata[64:60]),
+    .up_drdata (up_dac_drdata[64:60]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // transmit clock interface, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_clk (
+    .tx_clk (l_clk),
+    .tx_data_p (dac_clkdata_p),
+    .tx_data_n (dac_clkdata_n),
+    .tx_data_out (tx_clk_out),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[13]),
+    .up_dwdata (up_dac_dwdata[69:65]),
+    .up_drdata (up_dac_drdata[69:65]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // enable, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_enable (
+    .tx_clk (l_clk),
+    .tx_data_p (enable_p_int),
+    .tx_data_n (enable_p_int),
+    .tx_data_out (enable),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[14]),
+    .up_dwdata (up_dac_dwdata[74:70]),
+    .up_drdata (up_dac_drdata[74:70]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // txnrx, oddr -> obuf
+
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_txnrx (
+    .tx_clk (l_clk),
+    .tx_data_p (txnrx_p_int),
+    .tx_data_n (txnrx_p_int),
+    .tx_data_out (txnrx),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[15]),
+    .up_dwdata (up_dac_dwdata[79:75]),
+    .up_drdata (up_dac_drdata[79:75]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // device clock interface (receive clock)
+
+  always @(posedge clk) begin
+    locked_m1 <= locked_s;
+    locked <= locked_m1;
+  end
+
+  ad_cmos_clk #(
+    .DEVICE_TYPE (DEVICE_TYPE))
+  i_clk (
+    .rst (mmcm_rst),
+    .locked (locked_s),
+    .clk_in (rx_clk_in),
+    .clk (l_clk));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
new file mode 100644
index 000000000..144855ec8
--- /dev/null
+++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
@@ -0,0 +1,567 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9361_lvds_if #(
+
+  parameter   DEVICE_TYPE = 0,
+  parameter   DAC_IODELAY_ENABLE = 0,
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group") (
+
+  // physical interface (receive)
+
+  input               rx_clk_in_p,
+  input               rx_clk_in_n,
+  input               rx_frame_in_p,
+  input               rx_frame_in_n,
+  input   [ 5:0]      rx_data_in_p,
+  input   [ 5:0]      rx_data_in_n,
+
+  // physical interface (transmit)
+
+  output              tx_clk_out_p,
+  output              tx_clk_out_n,
+  output              tx_frame_out_p,
+  output              tx_frame_out_n,
+  output  [ 5:0]      tx_data_out_p,
+  output  [ 5:0]      tx_data_out_n,
+
+  // ensm control
+
+  output              enable,
+  output              txnrx,
+
+  // clock (common to both receive and transmit)
+
+  input               rst,
+  input               clk,
+  output              l_clk,
+
+  // receive data path interface
+
+  output  reg         adc_valid,
+  output  reg [47:0]  adc_data,
+  output  reg         adc_status,
+  input               adc_r1_mode,
+  input               adc_ddr_edgesel,
+
+  // transmit data path interface
+
+  input               dac_valid,
+  input   [47:0]      dac_data,
+  input               dac_clksel,
+  input               dac_r1_mode,
+
+  // tdd interface
+
+  input               tdd_enable,
+  input               tdd_txnrx,
+  input               tdd_mode,
+
+  // delay interface
+
+  input               mmcm_rst,
+  input               up_clk,
+  input               up_rstn,
+  input               up_enable,
+  input               up_txnrx,
+  input   [ 6:0]      up_adc_dld,
+  input   [34:0]      up_adc_dwdata,
+  output  [34:0]      up_adc_drdata,
+  input   [ 9:0]      up_dac_dld,
+  input   [49:0]      up_dac_dwdata,
+  output  [49:0]      up_dac_drdata,
+  input               delay_clk,
+  input               delay_rst,
+  output              delay_locked,
+
+  // drp interface
+
+  input               up_drp_sel,
+  input               up_drp_wr,
+  input   [11:0]      up_drp_addr,
+  input   [31:0]      up_drp_wdata,
+  output  [31:0]      up_drp_rdata,
+  output              up_drp_ready,
+  output              up_drp_locked);
+
+  // internal registers
+
+  reg     [ 3:0]  rx_frame = 'd0;
+  reg             rx_error = 'd0;
+  reg             rx_valid = 'd0;
+  reg     [ 5:0]  rx_data_3 = 'd0;
+  reg     [ 5:0]  rx_data_2 = 'd0;
+  reg     [ 5:0]  rx_data_1 = 'd0;
+  reg     [ 5:0]  rx_data_0 = 'd0;
+  reg     [23:0]  rx_data = 'd0;
+  reg     [ 3:0]  tx_frame = 'd0;
+  reg     [ 3:0]  tx_p_frame = 'd0;
+  reg     [ 3:0]  tx_n_frame = 'd0;
+  reg     [ 5:0]  tx_data_d_0 = 'd0;
+  reg     [ 5:0]  tx_data_d_1 = 'd0;
+  reg     [ 5:0]  tx_data_d_2 = 'd0;
+  reg     [ 5:0]  tx_data_d_3 = 'd0;
+  reg             tx_data_sel  = 'd0;
+  reg             up_enable_int = 'd0;
+  reg             up_txnrx_int = 'd0;
+  reg             enable_up_m1 = 'd0;
+  reg             txnrx_up_m1 = 'd0;
+  reg             enable_up = 'd0;
+  reg             txnrx_up = 'd0;
+  reg             enable_int = 'd0;
+  reg             txnrx_int = 'd0;
+  reg             enable_n_int = 'd0;
+  reg             txnrx_n_int = 'd0;
+  reg             enable_p_int = 'd0;
+  reg             txnrx_p_int = 'd0;
+  reg    [47:0]   tx_data_lclk = 'd0;
+  reg    [ 5:0]   tx_p_data_d_0 = 'd0;
+  reg    [ 5:0]   tx_p_data_d_1 = 'd0;
+  reg    [ 5:0]   tx_p_data_d_2 = 'd0;
+  reg    [ 5:0]   tx_p_data_d_3 = 'd0;
+  reg    [ 5:0]   tx_n_data_d_0 = 'd0;
+  reg    [ 5:0]   tx_n_data_d_1 = 'd0;
+  reg    [ 5:0]   tx_n_data_d_2 = 'd0;
+  reg    [ 5:0]   tx_n_data_d_3 = 'd0;
+  reg             adc_n_valid = 'd0;
+  reg             adc_p_valid = 'd0;
+  reg             adc_n_status = 'd0;
+  reg             adc_p_status = 'd0;
+  reg    [47:0]   adc_n_data = 'd0;
+  reg    [47:0]   adc_p_data = 'd0;
+
+  // internal signals
+
+  wire            s_clk;
+  wire            loaden;
+  wire    [ 7:0]  phase_s;
+  wire    [ 3:0]  rx_frame_s;
+  wire    [ 5:0]  rx_data_s_3;
+  wire    [ 5:0]  rx_data_s_2;
+  wire    [ 5:0]  rx_data_s_1;
+  wire    [ 5:0]  rx_data_s_0;
+  wire    [ 3:0]  rx_frame_inv_s;
+
+  // unused interface signals
+
+  assign up_adc_drdata = 35'b0;
+  assign up_dac_drdata = 50'b0;
+  assign delay_locked = 1'b1;
+
+  assign rx_frame_inv_s = ~rx_frame;
+
+  always @(posedge l_clk) begin
+    rx_frame <= rx_frame_s;
+    rx_data_3 <= rx_data_s_3;
+    rx_data_2 <= rx_data_s_2;
+    rx_data_1 <= rx_data_s_1;
+    rx_data_0 <= rx_data_s_0;
+    if (rx_frame_inv_s == rx_frame_s) begin
+      rx_error <= 1'b0;
+    end else begin
+      rx_error <= 1'b1;
+    end
+    case ({adc_r1_mode, rx_frame})
+      // R2 Mode
+      5'b01111: begin
+        rx_valid <= 1'b1;
+        rx_data[23:12] <= {rx_data_1,   rx_data_3};
+        rx_data[11: 0] <= {rx_data_0,   rx_data_2};
+      end
+      5'b01110: begin
+        rx_valid <= 1'b1;
+        rx_data[23:12] <= {rx_data_2,   rx_data_s_0};
+        rx_data[11: 0] <= {rx_data_1,   rx_data_3};
+      end
+      5'b01100: begin
+        rx_valid <= 1'b1;
+        rx_data[23:12] <= {rx_data_3,   rx_data_s_1};
+        rx_data[11: 0] <= {rx_data_2,   rx_data_s_0};
+      end
+      5'b01000: begin
+        rx_valid <= 1'b1;
+        rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
+        rx_data[11: 0] <= {rx_data_3,   rx_data_s_1};
+      end
+      5'b00000: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= {rx_data_1,   rx_data_3};
+        rx_data[11: 0] <= {rx_data_0,   rx_data_2};
+      end
+      5'b00001: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= {rx_data_2,   rx_data_s_0};
+        rx_data[11: 0] <= {rx_data_1,   rx_data_3};
+      end
+      5'b00011: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= {rx_data_3,   rx_data_s_1};
+        rx_data[11: 0] <= {rx_data_2,   rx_data_s_0};
+      end
+      5'b00111: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
+        rx_data[11: 0] <= {rx_data_3,   rx_data_s_1};
+      end
+      // R1 Mode
+      5'b11100: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= {rx_data_s_1, rx_data_s_3};
+        rx_data[11: 0] <= {rx_data_s_0, rx_data_s_2};
+      end
+      5'b10110: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= {rx_data_2, rx_data_s_0};
+        rx_data[11: 0] <= {rx_data_1, rx_data_3};
+      end
+      5'b11001: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
+        rx_data[11: 0] <= {rx_data_3, rx_data_s_1};
+      end
+      5'b10011: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= {rx_data_3, rx_data_s_1};
+        rx_data[11: 0] <= {rx_data_2, rx_data_s_0};
+      end
+      default: begin
+        rx_valid <= 1'b0;
+        rx_data[23:12] <= 12'd0;
+        rx_data[11: 0] <= 12'd0;
+      end
+    endcase
+    if (rx_valid == 1'b1) begin
+      adc_p_valid <= 1'b0;
+      adc_p_data <= {24'd0, rx_data};
+    end else begin
+      adc_p_valid <= 1'b1;
+      adc_p_data <= (adc_r1_mode) ? {24'd0, rx_data} : {rx_data, adc_p_data[23:0]};
+    end
+    adc_p_status <= ~rx_error & up_drp_locked;
+  end
+
+  // transfer to a synchronous common clock
+
+  always @(negedge l_clk) begin
+    adc_n_valid <= adc_p_valid;
+    adc_n_data <= adc_p_data;
+    adc_n_status <= adc_p_status;
+  end
+
+  always @(posedge clk) begin
+    adc_valid <= adc_n_valid;
+    adc_data <= adc_n_data;
+    adc_status <= adc_n_status;
+  end
+
+  always @(posedge clk) begin
+    if (dac_r1_mode == 1'b0) begin
+      tx_data_sel <= ~tx_data_sel;
+    end else begin
+      tx_data_sel <= 1'b0;
+    end
+
+    case ({dac_r1_mode, tx_data_sel})
+      2'b10: begin
+         tx_frame <= 4'b1100;
+         tx_data_d_0 <= dac_data[11: 6]; // i msb
+         tx_data_d_1 <= dac_data[23:18]; // q msb
+         tx_data_d_2 <= dac_data[ 5: 0]; // i lsb
+         tx_data_d_3 <= dac_data[17:12]; // q lsb
+      end
+      2'b00: begin
+         tx_frame <= 4'b1111;
+         tx_data_d_0 <= dac_data[11: 6]; // i msb 0
+         tx_data_d_1 <= dac_data[23:18]; // q msb 0
+         tx_data_d_2 <= dac_data[ 5: 0]; // i lsb 0
+         tx_data_d_3 <= dac_data[17:12]; // q lsb 0
+      end
+      2'b01: begin
+         tx_frame <= 4'b0000;
+         tx_data_d_0 <= dac_data[35:30]; // i msb 1
+         tx_data_d_1 <= dac_data[47:42]; // q msb 1
+         tx_data_d_2 <= dac_data[29:24]; // i lsb 1
+         tx_data_d_3 <= dac_data[41:36]; // q lsb 1
+      end
+    endcase
+
+  end
+
+  // transfer data from a synchronous clock (skew less than 2ns)
+
+  always @(negedge clk) begin
+    tx_n_frame <= tx_frame;
+    tx_n_data_d_0 <= tx_data_d_0;
+    tx_n_data_d_1 <= tx_data_d_1;
+    tx_n_data_d_2 <= tx_data_d_2;
+    tx_n_data_d_3 <= tx_data_d_3;
+  end
+
+  always @(posedge l_clk) begin
+    tx_p_frame <= tx_n_frame;
+    tx_p_data_d_0 <= tx_n_data_d_0;
+    tx_p_data_d_1 <= tx_n_data_d_1;
+    tx_p_data_d_2 <= tx_n_data_d_2;
+    tx_p_data_d_3 <= tx_n_data_d_3;
+  end
+
+  // tdd/ensm control
+
+  always @(posedge up_clk) begin
+    up_enable_int <= up_enable;
+    up_txnrx_int <= up_txnrx;
+  end
+
+  always @(posedge clk or posedge rst) begin
+    if (rst == 1'b1) begin
+      enable_up_m1 <= 1'b0;
+      txnrx_up_m1 <= 1'b0;
+      enable_up <= 1'b0;
+      txnrx_up <= 1'b0;
+    end else begin
+      enable_up_m1 <= up_enable_int;
+      txnrx_up_m1 <= up_txnrx_int;
+      enable_up <= enable_up_m1;
+      txnrx_up <= txnrx_up_m1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (tdd_mode == 1'b1) begin
+      enable_int <= tdd_enable;
+      txnrx_int <= tdd_txnrx;
+    end else begin
+      enable_int <= enable_up;
+      txnrx_int <= txnrx_up;
+    end
+  end
+
+  always @(negedge clk) begin
+    enable_n_int <= enable_int;
+    txnrx_n_int <= txnrx_int;
+  end
+
+  always @(posedge l_clk) begin
+    enable_p_int <= enable_n_int;
+    txnrx_p_int <= txnrx_n_int;
+  end
+
+  // receive data path interface
+
+  ad_serdes_in #(
+    .DATA_WIDTH(6),
+    .SERDES_FACTOR(4),
+    .DEVICE_TYPE(DEVICE_TYPE))
+  ad_serdes_data_in (
+    .rst (mmcm_rst),
+    .clk (s_clk),
+    .div_clk (l_clk),
+    .loaden (loaden),
+    .locked (up_drp_locked),
+    .phase (phase_s),
+    .data_s0 (rx_data_s_0),
+    .data_s1 (rx_data_s_1),
+    .data_s2 (rx_data_s_2),
+    .data_s3 (rx_data_s_3),
+    .data_s4 (),
+    .data_s5 (),
+    .data_s6 (),
+    .data_s7 (),
+    .data_in_p (rx_data_in_p),
+    .data_in_n (rx_data_in_n));
+
+  // receive frame interface
+
+  ad_serdes_in #(
+    .DATA_WIDTH(1),
+    .SERDES_FACTOR(4),
+    .DEVICE_TYPE(DEVICE_TYPE))
+  ad_serdes_frame_in (
+    .rst (mmcm_rst),
+    .clk (s_clk),
+    .div_clk (l_clk),
+    .loaden (loaden),
+    .locked (up_drp_locked),
+    .phase (phase_s),
+    .data_s0 (rx_frame_s[0]),
+    .data_s1 (rx_frame_s[1]),
+    .data_s2 (rx_frame_s[2]),
+    .data_s3 (rx_frame_s[3]),
+    .data_s4 (),
+    .data_s5 (),
+    .data_s6 (),
+    .data_s7 (),
+    .data_in_p (rx_frame_in_p),
+    .data_in_n (rx_frame_in_n));
+
+  // transmit data interface
+
+  ad_serdes_out #(
+    .DATA_WIDTH(6),
+    .SERDES_FACTOR(4),
+    .DEVICE_TYPE(DEVICE_TYPE))
+  ad_serdes_data_out (
+    .rst (mmcm_rst),
+    .clk (s_clk),
+    .div_clk (l_clk),
+    .loaden (loaden),
+    .data_s0 (tx_p_data_d_0),
+    .data_s1 (tx_p_data_d_1),
+    .data_s2 (tx_p_data_d_2),
+    .data_s3 (tx_p_data_d_3),
+    .data_s4 (6'b0),
+    .data_s5 (6'b0),
+    .data_s6 (6'b0),
+    .data_s7 (6'b0),
+    .data_out_p (tx_data_out_p),
+    .data_out_n (tx_data_out_n));
+
+  // transmit frame interface
+
+  ad_serdes_out #(
+    .DATA_WIDTH(1),
+    .SERDES_FACTOR(4),
+    .DEVICE_TYPE(DEVICE_TYPE))
+  ad_serdes_frame_out (
+    .rst (mmcm_rst),
+    .clk (s_clk),
+    .div_clk (l_clk),
+    .loaden (loaden),
+    .data_s0 (tx_p_frame[0]),
+    .data_s1 (tx_p_frame[1]),
+    .data_s2 (tx_p_frame[2]),
+    .data_s3 (tx_p_frame[3]),
+    .data_s4 (1'b1),
+    .data_s5 (1'b1),
+    .data_s6 (1'b1),
+    .data_s7 (1'b1),
+    .data_out_p (tx_frame_out_p),
+    .data_out_n (tx_frame_out_n));
+
+  // transmit clock interface
+
+  ad_serdes_out #(
+    .DATA_WIDTH(1),
+    .SERDES_FACTOR(4),
+    .DEVICE_TYPE(DEVICE_TYPE))
+  ad_serdes_tx_clock_out(
+    .rst (mmcm_rst),
+    .clk (s_clk),
+    .div_clk (l_clk),
+    .loaden (loaden),
+    .data_s0 (dac_clksel),
+    .data_s1 (~dac_clksel),
+    .data_s2 (dac_clksel),
+    .data_s3 (~dac_clksel),
+    .data_s4 (1'b0),
+    .data_s5 (1'b0),
+    .data_s6 (1'b0),
+    .data_s7 (1'b0),
+    .data_out_p (tx_clk_out_p),
+    .data_out_n (tx_clk_out_n));
+
+  // serdes clock interface
+
+  ad_serdes_clk ad_serdes_clk (
+    .rst (mmcm_rst),
+    .clk_in_p (rx_clk_in_p),
+    .clk_in_n (rx_clk_in_n),
+    .clk (s_clk),
+    .div_clk (l_clk),
+    .out_clk (),
+    .loaden (loaden),
+    .phase (phase_s),
+    .up_clk (up_clk),
+    .up_rstn (up_rstn),
+    .up_drp_sel (up_drp_sel),
+    .up_drp_wr (up_drp_wr),
+    .up_drp_addr (up_drp_addr),
+    .up_drp_wdata (up_drp_wdata),
+    .up_drp_rdata (up_drp_rdata),
+    .up_drp_ready (up_drp_ready),
+    .up_drp_locked (up_drp_locked));
+
+ // enable
+
+  ad_serdes_out #(
+    .DATA_WIDTH(1),
+    .SERDES_FACTOR(4),
+    .DEVICE_TYPE(DEVICE_TYPE))
+  i_enable(
+    .rst (mmcm_rst),
+    .clk (s_clk),
+    .div_clk (l_clk),
+    .loaden (loaden),
+    .data_s0 (enable_p_int),
+    .data_s1 (enable_p_int),
+    .data_s2 (enable_p_int),
+    .data_s3 (enable_p_int),
+    .data_s4 (1'b0),
+    .data_s5 (1'b0),
+    .data_s6 (1'b0),
+    .data_s7 (1'b0),
+    .data_out_p (enable),
+    .data_out_n ());
+
+  // txnrx
+
+    ad_serdes_out #(
+    .DATA_WIDTH(1),
+    .SERDES_FACTOR(4),
+    .DEVICE_TYPE(DEVICE_TYPE))
+  i_txnrx(
+    .rst (mmcm_rst),
+    .clk (s_clk),
+    .div_clk (l_clk),
+    .loaden (loaden),
+    .data_s0 (txnrx_p_int),
+    .data_s1 (txnrx_p_int),
+    .data_s2 (txnrx_p_int),
+    .data_s3 (txnrx_p_int),
+    .data_s4 (1'b0),
+    .data_s5 (1'b0),
+    .data_s6 (1'b0),
+    .data_s7 (1'b0),
+    .data_out_p (txnrx),
+    .data_out_n ());
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 6f4d84346..7f2729e29 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -17,6 +17,9 @@ add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
 add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_lvds_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_clk.v
+add_fileset_file ad_serdes_clk.v          VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v
+add_fileset_file ad_serdes_in.v           VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v
+add_fileset_file ad_serdes_out.v          VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v
 add_fileset_file ad_lvds_in.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_in.v
 add_fileset_file ad_lvds_out.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_out.v
 add_fileset_file ad_cmos_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_clk.v
@@ -42,8 +45,8 @@ add_fileset_file up_adc_channel.v         VERILOG PATH $ad_hdl_dir/library/commo
 add_fileset_file up_dac_common.v          VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
 add_fileset_file up_dac_channel.v         VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
 add_fileset_file up_tdd_cntrl.v           VERILOG PATH $ad_hdl_dir/library/common/up_tdd_cntrl.v
-add_fileset_file axi_ad9361_lvds_if.v     VERILOG PATH axi_ad9361_lvds_if.v
-add_fileset_file axi_ad9361_cmos_if.v     VERILOG PATH axi_ad9361_cmos_if.v
+add_fileset_file axi_ad9361_lvds_if.v     VERILOG PATH altera/axi_ad9361_lvds_if.v
+add_fileset_file axi_ad9361_cmos_if.v     VERILOG PATH altera/axi_ad9361_cmos_if.v
 add_fileset_file axi_ad9361_rx_pnmon.v    VERILOG PATH axi_ad9361_rx_pnmon.v
 add_fileset_file axi_ad9361_rx_channel.v  VERILOG PATH axi_ad9361_rx_channel.v
 add_fileset_file axi_ad9361_rx.v          VERILOG PATH axi_ad9361_rx.v
@@ -235,15 +238,23 @@ set_instance_parameter_value alt_ddio_out {SIZE} {1}
 set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
 set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
 
-add_hdl_instance alt_clk altera_iopll
-set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
-set_instance_parameter_value alt_clk {gui_use_locked} {1}
-set_instance_parameter_value alt_clk {gui_operation_mode} {source synchronous}
-set_instance_parameter_value alt_clk {gui_number_of_clocks} {1}
-set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
-set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
-set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
-set_instance_parameter_value alt_clk {system_info_device_family} DEVICE_FAMILY
+add_hdl_instance alt_serdes_clk_core alt_serdes
+set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK}
+set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1}
+set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4}
+set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
+
+add_hdl_instance alt_serdes_in_core alt_serdes
+set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
+set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
+set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
+set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0}
+
+add_hdl_instance alt_serdes_out_core alt_serdes
+set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
+set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
+set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4}
+set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0}
 
 # updates
 

From 2d93d787ab3f958496e514469c88074e1bb4c2d1 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 17:32:43 +0300
Subject: [PATCH 601/972] altera/ad_cdfilter: Update interface to Verilog 2001
 standard

---
 library/altera/common/ad_dcfilter.v | 38 ++++++++++-------------------
 1 file changed, 13 insertions(+), 25 deletions(-)

diff --git a/library/altera/common/ad_dcfilter.v b/library/altera/common/ad_dcfilter.v
index 8aac6dfc4..820ad731e 100755
--- a/library/altera/common/ad_dcfilter.v
+++ b/library/altera/common/ad_dcfilter.v
@@ -39,35 +39,25 @@
 
 `timescale 1ps/1ps
 
-module ad_dcfilter (
+module ad_dcfilter #(
+
+  // data path disable
+
+  parameter   DISABLE = 0) (
 
   // data interface
 
-  clk,
-  valid,
-  data,
-  valid_out,
-  data_out,
+  input               clk,
+  input               valid,
+  input       [15:0]  data,
+  output reg          valid_out,
+  output reg  [15:0]  data_out,
 
   // control interface
 
-  dcfilt_enb,
-  dcfilt_coeff,
-  dcfilt_offset);
-
-  // data interface
-
-  input           clk;
-  input           valid;
-  input   [15:0]  data;
-  output          valid_out;
-  output  [15:0]  data_out;
-
-  // control interface
-
-  input           dcfilt_enb;
-  input   [15:0]  dcfilt_coeff;
-  input   [15:0]  dcfilt_offset;
+  input           dcfilt_enb,
+  input   [15:0]  dcfilt_coeff,
+  input   [15:0]  dcfilt_offset);
 
   // internal registers
 
@@ -75,8 +65,6 @@ module ad_dcfilter (
   reg     [15:0]  data_d = 'd0;
   reg             valid_2d = 'd0;
   reg     [15:0]  data_2d = 'd0;
-  reg             valid_out = 'd0;
-  reg     [15:0]  data_out = 'd0;
 
   // internal signals
 

From b7767aa18fee466bb52d652c9199fa707d67cd5a Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 18:13:45 +0300
Subject: [PATCH 602/972] xilinx/axi_ad9361_lvds_if: Remove ila

---
 library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
index 05c84d27a..77a974b5e 100644
--- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
@@ -659,14 +659,6 @@ module axi_ad9361_lvds_if (
     .clk_in_n (rx_clk_in_n),
     .clk (l_clk));
 
-  // debug
-	ila_TEST_DAC_MODE ila_dac_mode (
-	.clk(clk),
-	.probe0(dac_r1_mode),
-	.probe1(dac_valid));
-
-// end debug
-
 endmodule
 
 // ***************************************************************************

From 1131be91ed8ead92c4843cf78133917b502cdfe4 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 23:34:13 +0300
Subject: [PATCH 603/972] axi_ad9361: Makefile update

---
 library/axi_ad9361/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile
index 7752839e6..929c08fff 100644
--- a/library/axi_ad9361/Makefile
+++ b/library/axi_ad9361/Makefile
@@ -37,8 +37,8 @@ M_DEPS += ../common/up_dac_common.v
 M_DEPS += ../common/up_dac_channel.v
 M_DEPS += ../common/up_tdd_cntrl.v
 M_DEPS += axi_ad9361_constr.xdc
-M_DEPS += axi_ad9361_lvds_if.v
-M_DEPS += axi_ad9361_cmos_if.v
+M_DEPS += xilinx/axi_ad9361_lvds_if.v
+M_DEPS += xilinx/axi_ad9361_cmos_if.v
 M_DEPS += axi_ad9361_rx_pnmon.v
 M_DEPS += axi_ad9361_rx_channel.v
 M_DEPS += axi_ad9361_rx.v

From 43ee917d530ba482b5bad273d019e1d6dffade62 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 12 Oct 2016 12:40:34 +0300
Subject: [PATCH 604/972] Add up_dac_channel missing connections

---
 library/axi_ad9122/axi_ad9122_channel.v    | 1 +
 library/axi_ad9152/axi_ad9152_channel.v    | 1 +
 library/axi_ad9162/axi_ad9162_channel.v    | 1 +
 library/axi_ad9371/axi_ad9371_tx_channel.v | 1 +
 library/axi_ad9739a/axi_ad9739a_channel.v  | 1 +
 5 files changed, 5 insertions(+)

diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v
index 31ac94a4b..d936f9048 100644
--- a/library/axi_ad9122/axi_ad9122_channel.v
+++ b/library/axi_ad9122/axi_ad9122_channel.v
@@ -257,6 +257,7 @@ module axi_ad9122_channel (
     .dac_pat_data_1 (dac_pat_data_1_s),
     .dac_pat_data_2 (dac_pat_data_2_s),
     .dac_data_sel (dac_data_sel_s),
+    .dac_iq_mode (),
     .dac_iqcor_enb (),
     .dac_iqcor_coeff_1 (),
     .dac_iqcor_coeff_2 (),
diff --git a/library/axi_ad9152/axi_ad9152_channel.v b/library/axi_ad9152/axi_ad9152_channel.v
index a597e025f..3d77dcaba 100644
--- a/library/axi_ad9152/axi_ad9152_channel.v
+++ b/library/axi_ad9152/axi_ad9152_channel.v
@@ -568,6 +568,7 @@ module axi_ad9152_channel (
     .dac_pat_data_1 (dac_pat_data_1_s),
     .dac_pat_data_2 (dac_pat_data_2_s),
     .dac_data_sel (dac_data_sel_s),
+    .dac_iq_mode (),
     .dac_iqcor_enb (),
     .dac_iqcor_coeff_1 (),
     .dac_iqcor_coeff_2 (),
diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v
index c15a3a996..001ae3be9 100644
--- a/library/axi_ad9162/axi_ad9162_channel.v
+++ b/library/axi_ad9162/axi_ad9162_channel.v
@@ -613,6 +613,7 @@ module axi_ad9162_channel (
       .dac_pat_data_2 (dac_pat_data_2_s),
       .dac_data_sel (dac_data_sel_s),
       .dac_iq_mode (dac_iq_mode_s),
+      .dac_iq_mode (),
       .dac_iqcor_enb (),
       .dac_iqcor_coeff_1 (),
       .dac_iqcor_coeff_2 (),
diff --git a/library/axi_ad9371/axi_ad9371_tx_channel.v b/library/axi_ad9371/axi_ad9371_tx_channel.v
index 32da01b64..6755ee133 100644
--- a/library/axi_ad9371/axi_ad9371_tx_channel.v
+++ b/library/axi_ad9371/axi_ad9371_tx_channel.v
@@ -249,6 +249,7 @@ module axi_ad9371_tx_channel (
     .dac_pat_data_1 (dac_pat_data_1_s),
     .dac_pat_data_2 (dac_pat_data_2_s),
     .dac_data_sel (dac_data_sel_s),
+    .dac_iq_mode (),
     .dac_iqcor_enb (dac_iqcor_enb_s),
     .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
     .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
diff --git a/library/axi_ad9739a/axi_ad9739a_channel.v b/library/axi_ad9739a/axi_ad9739a_channel.v
index d6cb660e8..37b99bf45 100644
--- a/library/axi_ad9739a/axi_ad9739a_channel.v
+++ b/library/axi_ad9739a/axi_ad9739a_channel.v
@@ -650,6 +650,7 @@ module axi_ad9739a_channel (
     .dac_pat_data_1 (dac_pat_data_1_s),
     .dac_pat_data_2 (dac_pat_data_2_s),
     .dac_data_sel (dac_data_sel_s),
+    .dac_iq_mode (),
     .dac_iqcor_enb (),
     .dac_iqcor_coeff_1 (),
     .dac_iqcor_coeff_2 (),

From a505d304afaa124d0ce8fd3c6bcae337916c4f2a Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 12 Oct 2016 12:56:09 +0300
Subject: [PATCH 605/972] Add up_dac_common missing connections

---
 library/axi_ad9122/axi_ad9122_core.v   | 1 +
 library/axi_ad9144/axi_ad9144_core.v   | 1 +
 library/axi_ad9152/axi_ad9152_core.v   | 1 +
 library/axi_ad9371/axi_ad9371_tx.v     | 1 +
 library/axi_ad9739a/axi_ad9739a_core.v | 1 +
 5 files changed, 5 insertions(+)

diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v
index fdc16674f..d3b79271c 100644
--- a/library/axi_ad9122/axi_ad9122_core.v
+++ b/library/axi_ad9122/axi_ad9122_core.v
@@ -278,6 +278,7 @@ module axi_ad9122_core (
     .dac_rst (dac_rst),
     .dac_sync (dac_sync_out),
     .dac_frame (dac_frame_s),
+    .dac_clksel (),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),
diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v
index 145ba8b1e..8d4f9b0a1 100644
--- a/library/axi_ad9144/axi_ad9144_core.v
+++ b/library/axi_ad9144/axi_ad9144_core.v
@@ -287,6 +287,7 @@ module axi_ad9144_core (
     .dac_rst (dac_rst),
     .dac_sync (dac_sync_s),
     .dac_frame (),
+    .dac_clksel (),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),
diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v
index f98d8b26b..e61643f74 100644
--- a/library/axi_ad9152/axi_ad9152_core.v
+++ b/library/axi_ad9152/axi_ad9152_core.v
@@ -211,6 +211,7 @@ module axi_ad9152_core (
     .dac_rst (dac_rst),
     .dac_sync (dac_sync_s),
     .dac_frame (),
+    .dac_clksel (),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),
diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v
index b53f625f0..ce64c0e6a 100644
--- a/library/axi_ad9371/axi_ad9371_tx.v
+++ b/library/axi_ad9371/axi_ad9371_tx.v
@@ -292,6 +292,7 @@ module axi_ad9371_tx (
     .dac_rst (dac_rst),
     .dac_sync (dac_sync_out),
     .dac_frame (),
+    .dac_clksel (),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),
diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v
index 0f8387866..0e8ed94f7 100644
--- a/library/axi_ad9739a/axi_ad9739a_core.v
+++ b/library/axi_ad9739a/axi_ad9739a_core.v
@@ -214,6 +214,7 @@ module axi_ad9739a_core (
     .dac_rst (dac_rst),
     .dac_sync (dac_sync_s),
     .dac_frame (),
+    .dac_clksel (),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),

From 91995c082d6f5c021c020a2afc36af7d06744575 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 12 Oct 2016 13:02:54 +0300
Subject: [PATCH 606/972] axi_ad9684: Fixed up_drp_*data width

---
 library/axi_ad9684/axi_ad9684.v    | 4 ++--
 library/axi_ad9684/axi_ad9684_if.v | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v
index 8a0c51d27..b878bec4d 100644
--- a/library/axi_ad9684/axi_ad9684.v
+++ b/library/axi_ad9684/axi_ad9684.v
@@ -187,8 +187,8 @@ module axi_ad9684 (
   wire            up_drp_sel_s;
   wire            up_drp_wr_s;
   wire    [11:0]  up_drp_addr_s;
-  wire    [15:0]  up_drp_wdata_s;
-  wire    [15:0]  up_drp_rdata_s;
+  wire    [31:0]  up_drp_wdata_s;
+  wire    [31:0]  up_drp_rdata_s;
   wire            up_drp_ready_s;
   wire            up_drp_locked_s;
   wire            rst_s;
diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v
index abceac525..d2672bf9a 100644
--- a/library/axi_ad9684/axi_ad9684_if.v
+++ b/library/axi_ad9684/axi_ad9684_if.v
@@ -121,8 +121,8 @@ module axi_ad9684_if (
   input           up_drp_sel;
   input           up_drp_wr;
   input   [11:0]  up_drp_addr;
-  input   [15:0]  up_drp_wdata;
-  output  [15:0]  up_drp_rdata;
+  input   [31:0]  up_drp_wdata;
+  output  [31:0]  up_drp_rdata;
   output          up_drp_ready;
   output          up_drp_locked;
 

From b5434020510c6118153cbda448b5e808f321d2f0 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 12 Oct 2016 13:11:31 +0300
Subject: [PATCH 607/972] axi_mc_current_monitor: Add missing up_axi connection

---
 library/axi_mc_current_monitor/axi_mc_current_monitor.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor.v b/library/axi_mc_current_monitor/axi_mc_current_monitor.v
index fff50d92e..89ededd6b 100644
--- a/library/axi_mc_current_monitor/axi_mc_current_monitor.v
+++ b/library/axi_mc_current_monitor/axi_mc_current_monitor.v
@@ -404,6 +404,7 @@ up_axi i_up_axi(
         .up_wreq (up_wreq_s),
         .up_waddr (up_waddr_s),
         .up_wdata (up_wdata_s),
+        .up_wack (up_wack),
         .up_rreq (up_rreq_s),
         .up_raddr (up_raddr_s),
         .up_rdata (up_rdata),

From a026d444358e2f033a3eda0675d093f7c0899084 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 12 Oct 2016 13:14:20 +0300
Subject: [PATCH 608/972] axi_generic_adc: Add missing up_adc_common
 connections

---
 library/axi_generic_adc/axi_generic_adc.v | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v
index a9f20b320..f2acc457f 100644
--- a/library/axi_generic_adc/axi_generic_adc.v
+++ b/library/axi_generic_adc/axi_generic_adc.v
@@ -90,9 +90,12 @@ up_adc_common #(.ID(ID)) i_up_adc_common (
   .adc_ddr_edgesel (),
   .adc_pin_mode (),
   .adc_status ('h00),
+  .adc_sync_status (1'b1),
   .adc_status_ovf (adc_dovf),
   .adc_status_unf (1'b0),
   .adc_clk_ratio (32'd1),
+  .adc_start_code (),
+  .adc_sync (),
 
   .up_status_pn_err (1'b0),
   .up_status_pn_oos (1'b0),

From 1d1fe26624de84127e1c52e326f571cbf0bee59c Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 14 Oct 2016 17:32:23 +0300
Subject: [PATCH 609/972] fmcomms7: ZC706, Update project to new GT framework

---
 projects/fmcomms7/common/fmcomms7_bd.tcl  | 159 ++++++----------------
 projects/fmcomms7/zc706/Makefile          |  12 +-
 projects/fmcomms7/zc706/system_bd.tcl     |   1 -
 projects/fmcomms7/zc706/system_constr.xdc |  90 ++++++------
 projects/fmcomms7/zc706/system_top.v      |  40 ++++--
 5 files changed, 125 insertions(+), 177 deletions(-)

diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl
index d5af8eb08..7db4d8c02 100644
--- a/projects/fmcomms7/common/fmcomms7_bd.tcl
+++ b/projects/fmcomms7/common/fmcomms7_bd.tcl
@@ -1,18 +1,4 @@
 
-# fmcomms7
-
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir I rx_sysref
-create_bd_port -dir I -from 3 -to 0 rx_data_p
-create_bd_port -dir I -from 3 -to 0 rx_data_n
-
-create_bd_port -dir I tx_ref_clk
-create_bd_port -dir I tx_sync
-create_bd_port -dir I tx_sysref
-create_bd_port -dir O -from 7 -to 0 tx_data_p
-create_bd_port -dir O -from 7 -to 0 tx_data_n
-
 create_bd_port -dir O -from 11 -to 0 spi2_csn_o
 create_bd_port -dir I -from 11 -to 0 spi2_csn_i
 create_bd_port -dir I spi2_clk_i
@@ -23,13 +9,18 @@ create_bd_port -dir I spi2_sdi_i
 
 # dac peripherals
 
-set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
-set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core
+set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9144_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9144_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9144_xcvr
 
 set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd
 
+set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
+set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core
+
 set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma
@@ -48,12 +39,17 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack
 
 # adc peripherals
 
-set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
+set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
 
 set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
 
+set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
+
 set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
@@ -73,26 +69,9 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
 
 # dac/adc common gt
 
-set axi_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcomms7_gt]
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_0 {5}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_2 {6}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_3 {7}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_4 {2}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_5 {0}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_6 {1}] $axi_fmcomms7_gt
-set_property -dict [list CONFIG.TX_DATA_SEL_7 {4}] $axi_fmcomms7_gt
-
-set util_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcomms7_gt]
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_fmcomms7_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcomms7_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcomms7_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_gt
-set_property -dict [list CONFIG.TX_ENABLE {1}] $util_fmcomms7_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_gt
+set util_fmcomms7_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms7_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_xcvr
 
 set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi]
 set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi
@@ -110,65 +89,22 @@ ad_connect  spi2_sdo_o axi_fmcomms7_spi/io0_o
 ad_connect  spi2_sdi_i axi_fmcomms7_spi/io1_i
 ad_connect  sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk
 
-# connections (gt)
-
-ad_connect  util_fmcomms7_gt/qpll_ref_clk rx_ref_clk
-ad_connect  util_fmcomms7_gt/cpll_ref_clk tx_ref_clk
-
-ad_connect  axi_fmcomms7_gt/gt_qpll_0 util_fmcomms7_gt/gt_qpll_0
-ad_connect  axi_fmcomms7_gt/gt_pll_0 util_fmcomms7_gt/gt_pll_0
-ad_connect  axi_fmcomms7_gt/gt_pll_1 util_fmcomms7_gt/gt_pll_1
-ad_connect  axi_fmcomms7_gt/gt_pll_2 util_fmcomms7_gt/gt_pll_2
-ad_connect  axi_fmcomms7_gt/gt_pll_3 util_fmcomms7_gt/gt_pll_3
-ad_connect  axi_fmcomms7_gt/gt_pll_4 util_fmcomms7_gt/gt_pll_4
-ad_connect  axi_fmcomms7_gt/gt_pll_5 util_fmcomms7_gt/gt_pll_5
-ad_connect  axi_fmcomms7_gt/gt_pll_6 util_fmcomms7_gt/gt_pll_6
-ad_connect  axi_fmcomms7_gt/gt_pll_7 util_fmcomms7_gt/gt_pll_7
-ad_connect  axi_fmcomms7_gt/gt_rx_0 util_fmcomms7_gt/gt_rx_0
-ad_connect  axi_fmcomms7_gt/gt_rx_1 util_fmcomms7_gt/gt_rx_1
-ad_connect  axi_fmcomms7_gt/gt_rx_2 util_fmcomms7_gt/gt_rx_2
-ad_connect  axi_fmcomms7_gt/gt_rx_3 util_fmcomms7_gt/gt_rx_3
-ad_connect  axi_fmcomms7_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
-ad_connect  axi_fmcomms7_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
-ad_connect  axi_fmcomms7_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
-ad_connect  axi_fmcomms7_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
-ad_connect  axi_fmcomms7_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms7_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms7_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms7_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcomms7_gt/gt_tx_0 util_fmcomms7_gt/gt_tx_0
-ad_connect  axi_fmcomms7_gt/gt_tx_1 util_fmcomms7_gt/gt_tx_1
-ad_connect  axi_fmcomms7_gt/gt_tx_2 util_fmcomms7_gt/gt_tx_2
-ad_connect  axi_fmcomms7_gt/gt_tx_3 util_fmcomms7_gt/gt_tx_3
-ad_connect  axi_fmcomms7_gt/gt_tx_4 util_fmcomms7_gt/gt_tx_4
-ad_connect  axi_fmcomms7_gt/gt_tx_5 util_fmcomms7_gt/gt_tx_5
-ad_connect  axi_fmcomms7_gt/gt_tx_6 util_fmcomms7_gt/gt_tx_6
-ad_connect  axi_fmcomms7_gt/gt_tx_7 util_fmcomms7_gt/gt_tx_7
-ad_connect  axi_fmcomms7_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx
-ad_connect  axi_fmcomms7_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx
-ad_connect  axi_fmcomms7_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx
-ad_connect  axi_fmcomms7_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx
-ad_connect  axi_fmcomms7_gt/gt_tx_ip_4 axi_ad9144_jesd/gt4_tx
-ad_connect  axi_fmcomms7_gt/gt_tx_ip_5 axi_ad9144_jesd/gt5_tx
-ad_connect  axi_fmcomms7_gt/gt_tx_ip_6 axi_ad9144_jesd/gt6_tx
-ad_connect  axi_fmcomms7_gt/gt_tx_ip_7 axi_ad9144_jesd/gt7_tx
-
 # connections (dac)
 
-ad_connect  util_fmcomms7_gt/tx_sysref tx_sysref
-ad_connect  util_fmcomms7_gt/tx_p tx_data_p
-ad_connect  util_fmcomms7_gt/tx_n tx_data_n
-ad_connect  util_fmcomms7_gt/tx_sync tx_sync
-ad_connect  util_fmcomms7_gt/tx_out_clk util_fmcomms7_gt/tx_clk
-ad_connect  util_fmcomms7_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk
-ad_connect  util_fmcomms7_gt/tx_ip_rst axi_ad9144_jesd/tx_reset
-ad_connect  util_fmcomms7_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done
-ad_connect  util_fmcomms7_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref
-ad_connect  util_fmcomms7_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
-ad_connect  util_fmcomms7_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
-ad_connect  util_fmcomms7_gt/tx_out_clk axi_ad9144_core/tx_clk
-ad_connect  util_fmcomms7_gt/tx_data axi_ad9144_core/tx_data
-ad_connect  util_fmcomms7_gt/tx_out_clk axi_ad9144_upack/dac_clk
+ad_xcvrcon  util_fmcomms7_xcvr axi_ad9144_xcvr axi_ad9144_jesd
+ad_reconct  util_fmcomms7_xcvr/tx_0 axi_ad9144_jesd/gt5_tx
+ad_reconct  util_fmcomms7_xcvr/tx_1 axi_ad9144_jesd/gt3_tx
+ad_reconct  util_fmcomms7_xcvr/tx_2 axi_ad9144_jesd/gt6_tx
+ad_reconct  util_fmcomms7_xcvr/tx_3 axi_ad9144_jesd/gt7_tx
+ad_reconct  util_fmcomms7_xcvr/tx_4 axi_ad9144_jesd/gt2_tx
+ad_reconct  util_fmcomms7_xcvr/tx_5 axi_ad9144_jesd/gt0_tx
+ad_reconct  util_fmcomms7_xcvr/tx_6 axi_ad9144_jesd/gt1_tx
+ad_reconct  util_fmcomms7_xcvr/tx_7 axi_ad9144_jesd/gt4_tx
+
+ad_connect  util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
+ad_connect  axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data
+
+ad_connect  util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk
 ad_connect  axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
 ad_connect  axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
 ad_connect  axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
@@ -181,7 +117,7 @@ ad_connect  axi_ad9144_core/dac_valid_2 axi_ad9144_upack/dac_valid_2
 ad_connect  axi_ad9144_core/dac_enable_3 axi_ad9144_upack/dac_enable_3
 ad_connect  axi_ad9144_core/dac_ddata_3 axi_ad9144_upack/dac_data_3
 ad_connect  axi_ad9144_core/dac_valid_3 axi_ad9144_upack/dac_valid_3
-ad_connect  util_fmcomms7_gt/tx_out_clk axi_ad9144_fifo/dac_clk
+ad_connect  util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk
 ad_connect  axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
 ad_connect  axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
 ad_connect  sys_cpu_clk axi_ad9144_fifo/dma_clk
@@ -196,30 +132,21 @@ ad_connect  axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
 
 # connections (adc)
 
-ad_connect  util_fmcomms7_gt/rx_sysref rx_sysref
-ad_connect  util_fmcomms7_gt/rx_p rx_data_p
-ad_connect  util_fmcomms7_gt/rx_n rx_data_n
-ad_connect  util_fmcomms7_gt/rx_sync rx_sync
-ad_connect  util_fmcomms7_gt/rx_out_clk util_fmcomms7_gt/rx_clk
-ad_connect  util_fmcomms7_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
-ad_connect  util_fmcomms7_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
-ad_connect  util_fmcomms7_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
-ad_connect  util_fmcomms7_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
-ad_connect  util_fmcomms7_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
-ad_connect  util_fmcomms7_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
-ad_connect  util_fmcomms7_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
-ad_connect  util_fmcomms7_gt/rx_out_clk axi_ad9680_core/rx_clk
-ad_connect  util_fmcomms7_gt/rx_data axi_ad9680_core/rx_data
-ad_connect  util_fmcomms7_gt/rx_out_clk axi_ad9680_cpack/adc_clk
-ad_connect  util_fmcomms7_gt/rx_rst axi_ad9680_cpack/adc_rst
+ad_xcvrcon  util_fmcomms7_xcvr axi_ad9680_xcvr axi_ad9680_jesd
+ad_connect  util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
+ad_connect  axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
+ad_connect  axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
+
+ad_connect  util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
 ad_connect  axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
 ad_connect  axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
 ad_connect  axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
 ad_connect  axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
 ad_connect  axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
 ad_connect  axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
-ad_connect  util_fmcomms7_gt/rx_out_clk axi_ad9680_fifo/adc_clk
-ad_connect  util_fmcomms7_gt/rx_rst axi_ad9680_fifo/adc_rst
+ad_connect  util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
 ad_connect  axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
 ad_connect  axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
 ad_connect  sys_cpu_clk axi_ad9680_fifo/dma_clk
@@ -233,10 +160,11 @@ ad_connect  axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_fmcomms7_gt
+ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
 ad_cpu_interconnect 0x44A00000 axi_ad9144_core
 ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
+ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
 ad_cpu_interconnect 0x44A10000 axi_ad9680_core
 ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
@@ -245,7 +173,7 @@ ad_cpu_interconnect 0x44A80000 axi_fmcomms7_spi
 # gt uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_fmcomms7_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
 
 # interconnect (mem/dac)
 
@@ -260,3 +188,4 @@ ad_cpu_interrupt ps-9  mb-9  axi_ad9144_dma/irq
 ad_cpu_interrupt ps-10 mb-10 axi_ad9680_dma/irq
 ad_cpu_interrupt ps-12 mb-12 axi_fmcomms7_spi/ip2intc_irpt
 
+ad_connect  axi_ad9144_fifo/dac_fifo_bypass GND
diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile
index 9343fc02c..f51629899 100644
--- a/projects/fmcomms7/zc706/Makefile
+++ b/projects/fmcomms7/zc706/Makefile
@@ -24,14 +24,14 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -64,14 +64,14 @@ clean-all:clean
 	make -C ../../../library/axi_ad9144 clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/xilinx/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_upack clean
 
 
@@ -84,14 +84,14 @@ lib:
 	make -C ../../../library/axi_ad9144
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/xilinx/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_upack
 
 ####################################################################################
diff --git a/projects/fmcomms7/zc706/system_bd.tcl b/projects/fmcomms7/zc706/system_bd.tcl
index dc501e7f8..e2fd79784 100644
--- a/projects/fmcomms7/zc706/system_bd.tcl
+++ b/projects/fmcomms7/zc706/system_bd.tcl
@@ -22,4 +22,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
   SEG_axi_ddr_cntrl_memaddr
 
 source ../common/fmcomms7_bd.tcl
-
diff --git a/projects/fmcomms7/zc706/system_constr.xdc b/projects/fmcomms7/zc706/system_constr.xdc
index 998181c81..ec16a9a01 100644
--- a/projects/fmcomms7/zc706/system_constr.xdc
+++ b/projects/fmcomms7/zc706/system_constr.xdc
@@ -1,22 +1,22 @@
 # fmcomms7
 
-set_property  -dict {PACKAGE_PIN  AA8 } [get_ports rx_ref_clk_p]                                      ; ## B20  FMC_HPC_GBTCLK1_M2C_P  
-set_property  -dict {PACKAGE_PIN  AA7 } [get_ports rx_ref_clk_n]                                      ; ## B21  FMC_HPC_GBTCLK1_M2C_N  
-set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[0]]                                      ; ## A10  FMC_HPC_DP3_M2C_P      
-set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[0]]                                      ; ## A11  FMC_HPC_DP3_M2C_N      
-set_property  -dict {PACKAGE_PIN  AH10} [get_ports rx_data_p[1]]                                      ; ## C06  FMC_HPC_DP0_M2C_P      
-set_property  -dict {PACKAGE_PIN  AH9 } [get_ports rx_data_n[1]]                                      ; ## C07  FMC_HPC_DP0_M2C_N      
-set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[2]]                                      ; ## A06  FMC_HPC_DP2_M2C_P      
-set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[2]]                                      ; ## A07  FMC_HPC_DP2_M2C_N      
-set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[3]]                                      ; ## A02  FMC_HPC_DP1_M2C_P      
-set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[3]]                                      ; ## A03  FMC_HPC_DP1_M2C_N      
-set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## D08  FMC_HPC_LA01_CC_P      
-set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## D09  FMC_HPC_LA01_CC_N      
-set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]    ; ## G09  FMC_HPC_LA03_P         
-set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]    ; ## G10  FMC_HPC_LA03_N         
+set_property  -dict {PACKAGE_PIN  AA8 } [get_ports rx_ref_clk_p]                                      ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  AA7 } [get_ports rx_ref_clk_n]                                      ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[0]]                                      ; ## A10  FMC_HPC_DP3_M2C_P
+set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[0]]                                      ; ## A11  FMC_HPC_DP3_M2C_N
+set_property  -dict {PACKAGE_PIN  AH10} [get_ports rx_data_p[1]]                                      ; ## C06  FMC_HPC_DP0_M2C_P
+set_property  -dict {PACKAGE_PIN  AH9 } [get_ports rx_data_n[1]]                                      ; ## C07  FMC_HPC_DP0_M2C_N
+set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[2]]                                      ; ## A06  FMC_HPC_DP2_M2C_P
+set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[2]]                                      ; ## A07  FMC_HPC_DP2_M2C_N
+set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[3]]                                      ; ## A02  FMC_HPC_DP1_M2C_P
+set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[3]]                                      ; ## A03  FMC_HPC_DP1_M2C_N
+set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## D08  FMC_HPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## D09  FMC_HPC_LA01_CC_N
+set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]    ; ## G09  FMC_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]    ; ## G10  FMC_HPC_LA03_N
 
-set_property  -dict {PACKAGE_PIN  AD10} [get_ports tx_ref_clk_p]                                      ; ## D04  FMC_HPC_GBTCLK0_M2C_P   
-set_property  -dict {PACKAGE_PIN  AD9 } [get_ports tx_ref_clk_n]                                      ; ## D05  FMC_HPC_GBTCLK0_M2C_N   
+set_property  -dict {PACKAGE_PIN  AD10} [get_ports tx_ref_clk_p]                                      ; ## D04  FMC_HPC_GBTCLK0_M2C_P
+set_property  -dict {PACKAGE_PIN  AD9 } [get_ports tx_ref_clk_n]                                      ; ## D05  FMC_HPC_GBTCLK0_M2C_N
 set_property  -dict {PACKAGE_PIN  AK2 } [get_ports tx_data_p[0]]                                      ; ## A30  FMC_HPC_DP3_C2M_P      (tx_data_p[5])
 set_property  -dict {PACKAGE_PIN  AK1 } [get_ports tx_data_n[0]]                                      ; ## A31  FMC_HPC_DP3_C2M_N      (tx_data_n[5])
 set_property  -dict {PACKAGE_PIN  AK10} [get_ports tx_data_p[1]]                                      ; ## C02  FMC_HPC_DP0_C2M_P      (tx_data_p[3])
@@ -51,24 +51,24 @@ set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports spi_dir]
 
 # spi (others, sdi and/or sdo)
 
-set_property  -dict {PACKAGE_PIN  T24   IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_1]           ; ## H22  FMC_HPC_LA19_P             
-set_property  -dict {PACKAGE_PIN  T25   IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_2]           ; ## H23  FMC_HPC_LA19_N             
-set_property  -dict {PACKAGE_PIN  W29   IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_1]           ; ## H25  FMC_HPC_LA21_P             
-set_property  -dict {PACKAGE_PIN  W30   IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_2]           ; ## H26  FMC_HPC_LA21_N             
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_3]           ; ## G19  FMC_HPC_LA16_N             
-set_property  -dict {PACKAGE_PIN  V23   IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_1]           ; ## D20  FMC_HPC_LA17_CC_P          
-set_property  -dict {PACKAGE_PIN  W24   IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_2]           ; ## D21  FMC_HPC_LA17_CC_N          
-set_property  -dict {PACKAGE_PIN  U25   IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_1]            ; ## G21  FMC_HPC_LA20_P             
-set_property  -dict {PACKAGE_PIN  V26   IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_2]            ; ## G22  FMC_HPC_LA20_N             
-set_property  -dict {PACKAGE_PIN  V28   IOSTANDARD LVCMOS25} [get_ports spi2_clk]                     ; ## C26  FMC_HPC_LA27_P             
-set_property  -dict {PACKAGE_PIN  V29   IOSTANDARD LVCMOS25} [get_ports spi2_sdo]                     ; ## C27  FMC_HPC_LA27_N             
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_1]            ; ## D17  FMC_HPC_LA13_P             
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_2]            ; ## D18  FMC_HPC_LA13_N             
+set_property  -dict {PACKAGE_PIN  T24   IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_1]           ; ## H22  FMC_HPC_LA19_P
+set_property  -dict {PACKAGE_PIN  T25   IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_2]           ; ## H23  FMC_HPC_LA19_N
+set_property  -dict {PACKAGE_PIN  W29   IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_1]           ; ## H25  FMC_HPC_LA21_P
+set_property  -dict {PACKAGE_PIN  W30   IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_2]           ; ## H26  FMC_HPC_LA21_N
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_3]           ; ## G19  FMC_HPC_LA16_N
+set_property  -dict {PACKAGE_PIN  V23   IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_1]           ; ## D20  FMC_HPC_LA17_CC_P
+set_property  -dict {PACKAGE_PIN  W24   IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_2]           ; ## D21  FMC_HPC_LA17_CC_N
+set_property  -dict {PACKAGE_PIN  U25   IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_1]            ; ## G21  FMC_HPC_LA20_P
+set_property  -dict {PACKAGE_PIN  V26   IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_2]            ; ## G22  FMC_HPC_LA20_N
+set_property  -dict {PACKAGE_PIN  V28   IOSTANDARD LVCMOS25} [get_ports spi2_clk]                     ; ## C26  FMC_HPC_LA27_P
+set_property  -dict {PACKAGE_PIN  V29   IOSTANDARD LVCMOS25} [get_ports spi2_sdo]                     ; ## C27  FMC_HPC_LA27_N
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_1]            ; ## D17  FMC_HPC_LA13_P
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_2]            ; ## D18  FMC_HPC_LA13_N
 
 # external trigger
 
-set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p]         ; ## H13  FMC_HPC_LA07_P          
-set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n]         ; ## H14  FMC_HPC_LA07_N          
+set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p]         ; ## H13  FMC_HPC_LA07_P
+set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n]         ; ## H14  FMC_HPC_LA07_N
 
 # clock gpio
 
@@ -77,7 +77,7 @@ set_property  -dict {PACKAGE_PIN  U29   IOSTANDARD LVCMOS25} [get_ports clk_gpio
 set_property  -dict {PACKAGE_PIN  T30   IOSTANDARD LVCMOS25} [get_ports clk_gpio[2]]                  ; ## H28  FMC_HPC_LA24_P
 set_property  -dict {PACKAGE_PIN  U30   IOSTANDARD LVCMOS25} [get_ports clk_gpio[3]]                  ; ## H29  FMC_HPC_LA24_N
 
-# status                              
+# status
 
 set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports adc_fda]                      ; ## H16  FMC_HPC_LA11_P
 set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports adc_fdb]                      ; ## H17  FMC_HPC_LA11_N
@@ -85,23 +85,23 @@ set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVCMOS25} [get_ports dac_irq]
 set_property  -dict {PACKAGE_PIN  R28   IOSTANDARD LVCMOS25} [get_ports adf4355_1_ld]                 ; ## D26  FMC_HPC_LA26_P
 set_property  -dict {PACKAGE_PIN  T28   IOSTANDARD LVCMOS25} [get_ports adf4355_2_ld]                 ; ## D27  FMC_HPC_LA26_N
 
-# control                             
+# control
 
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25} [get_ports xo_en]                        ; ## G18  FMC_HPC_LA16_P             
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports clk_sync]                     ; ## G12  FMC_HPC_LA08_P             
-set_property  -dict {PACKAGE_PIN  W25   IOSTANDARD LVCMOS25} [get_ports adf4355_2_pd]                 ; ## C22  FMC_HPC_LA18_CC_P          
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports dac_txen0]                    ; ## G15  FMC_HPC_LA12_P             
-set_property  -dict {PACKAGE_PIN  AF24  IOSTANDARD LVCMOS25} [get_ports dac_txen1]                    ; ## G16  FMC_HPC_LA12_N             
-set_property  -dict {PACKAGE_PIN  V27   IOSTANDARD LVCMOS25} [get_ports hmc271_1_reset]               ; ## G24  FMC_HPC_LA22_P             
-set_property  -dict {PACKAGE_PIN  W28   IOSTANDARD LVCMOS25} [get_ports hmc271_2_reset]               ; ## G25  FMC_HPC_LA22_N             
-set_property  -dict {PACKAGE_PIN  W26   IOSTANDARD LVCMOS25} [get_ports hmc349_sel]                   ; ## C23  FMC_HPC_LA18_CC_N          
-set_property  -dict {PACKAGE_PIN  P25   IOSTANDARD LVCMOS25} [get_ports hmc922_a]                     ; ## D23  FMC_HPC_LA23_P             
-set_property  -dict {PACKAGE_PIN  P26   IOSTANDARD LVCMOS25} [get_ports hmc922_b]                     ; ## D24  FMC_HPC_LA23_N             
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25} [get_ports xo_en]                        ; ## G18  FMC_HPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports clk_sync]                     ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  W25   IOSTANDARD LVCMOS25} [get_ports adf4355_2_pd]                 ; ## C22  FMC_HPC_LA18_CC_P
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports dac_txen0]                    ; ## G15  FMC_HPC_LA12_P
+set_property  -dict {PACKAGE_PIN  AF24  IOSTANDARD LVCMOS25} [get_ports dac_txen1]                    ; ## G16  FMC_HPC_LA12_N
+set_property  -dict {PACKAGE_PIN  V27   IOSTANDARD LVCMOS25} [get_ports hmc271_1_reset]               ; ## G24  FMC_HPC_LA22_P
+set_property  -dict {PACKAGE_PIN  W28   IOSTANDARD LVCMOS25} [get_ports hmc271_2_reset]               ; ## G25  FMC_HPC_LA22_N
+set_property  -dict {PACKAGE_PIN  W26   IOSTANDARD LVCMOS25} [get_ports hmc349_sel]                   ; ## C23  FMC_HPC_LA18_CC_N
+set_property  -dict {PACKAGE_PIN  P25   IOSTANDARD LVCMOS25} [get_ports hmc922_a]                     ; ## D23  FMC_HPC_LA23_P
+set_property  -dict {PACKAGE_PIN  P26   IOSTANDARD LVCMOS25} [get_ports hmc922_b]                     ; ## D24  FMC_HPC_LA23_N
 
 # clocks
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_fmcomms7_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_fmcomms7_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
diff --git a/projects/fmcomms7/zc706/system_top.v b/projects/fmcomms7/zc706/system_top.v
index 3dffcd50b..2bd1e4b40 100644
--- a/projects/fmcomms7/zc706/system_top.v
+++ b/projects/fmcomms7/zc706/system_top.v
@@ -477,11 +477,17 @@ module system_top (
     .ps_intr_07 (1'b0),
     .ps_intr_08 (1'b0),
     .ps_intr_11 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),
@@ -511,11 +517,25 @@ module system_top (
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
-    .tx_data_n (tx_data_n),
-    .tx_data_p (tx_data_p),
-    .tx_ref_clk (tx_ref_clk),
-    .tx_sync (tx_sync),
-    .tx_sysref (tx_sysref));
+    .tx_data_0_n (tx_data_n[0]),
+    .tx_data_0_p (tx_data_p[0]),
+    .tx_data_1_n (tx_data_n[1]),
+    .tx_data_1_p (tx_data_p[1]),
+    .tx_data_2_n (tx_data_n[2]),
+    .tx_data_2_p (tx_data_p[2]),
+    .tx_data_3_n (tx_data_n[3]),
+    .tx_data_3_p (tx_data_p[3]),
+    .tx_data_4_n (tx_data_n[4]),
+    .tx_data_4_p (tx_data_p[4]),
+    .tx_data_5_n (tx_data_n[5]),
+    .tx_data_5_p (tx_data_p[5]),
+    .tx_data_6_n (tx_data_n[6]),
+    .tx_data_6_p (tx_data_p[6]),
+    .tx_data_7_n (tx_data_n[7]),
+    .tx_data_7_p (tx_data_p[7]),
+    .tx_ref_clk_0 (tx_ref_clk),
+    .tx_sync_0 (tx_sync),
+    .tx_sysref_0 (tx_sysref));
 
 endmodule
 

From 7c541c704a36a6f0b8c97bd7fde589ac621ecfa9 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 14 Oct 2016 18:08:08 +0300
Subject: [PATCH 610/972] usdrx1: ZC706, Update project to the new GT framework

---
 projects/usdrx1/common/usdrx1_bd.tcl    | 202 +++++++-----------------
 projects/usdrx1/zc706/Makefile          |  12 +-
 projects/usdrx1/zc706/system_constr.xdc |   2 +-
 projects/usdrx1/zc706/system_top.v      |  39 +++--
 4 files changed, 81 insertions(+), 174 deletions(-)

diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl
index 4b9f89177..c6cdbd191 100644
--- a/projects/usdrx1/common/usdrx1_bd.tcl
+++ b/projects/usdrx1/common/usdrx1_bd.tcl
@@ -9,12 +9,6 @@ create_bd_port -dir I spi_sdo_i
 create_bd_port -dir O spi_sdo_o
 create_bd_port -dir I spi_sdi_i
 
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir O rx_sysref
-create_bd_port -dir I -from 7 -to 0 rx_data_p
-create_bd_port -dir I -from 7 -to 0 rx_data_n
-
 create_bd_port -dir O -from 255 -to 0 gt_rx_data
 create_bd_port -dir I -from 63 -to 0 gt_rx_data_0
 create_bd_port -dir I -from 63 -to 0 gt_rx_data_1
@@ -58,82 +52,20 @@ set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:
 set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_3
 set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3
 
-set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_usdrx1_jesd]
+set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_usdrx1_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
 set_property -dict [list CONFIG.GT_Line_Rate {3.2}  ] $axi_usdrx1_jesd
 set_property -dict [list CONFIG.GT_REFCLK_FREQ {80.000} ]  $axi_usdrx1_jesd
 
-set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_2 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_3 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_4 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_4 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_4 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_5 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_5 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_5 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_6 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_6 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_6 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_7 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_7 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_7 {4}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_usdrx1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_usdrx1_gt
+set axi_usdrx1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_usdrx1_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_usdrx1_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_usdrx1_xcvr
 
-set util_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_usdrx1_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_usdrx1_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_usdrx1_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_usdrx1_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_usdrx1_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_usdrx1_gt
-set_property -dict [list CONFIG.TX_ENABLE {0}] $util_usdrx1_gt
+set util_usdrx1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_usdrx1_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_usdrx1_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_usdrx1_xcvr
 
 set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_usdrx1_dma
@@ -154,6 +86,30 @@ set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
 set_property -dict [list CONFIG.C_NUM_SS_BITS {5}] $axi_usdrx1_spi
 set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi
 
+set data_slice_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0]
+set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_0
+set_property -dict [list CONFIG.DIN_TO {0}] $data_slice_0
+set_property -dict [list CONFIG.DIN_FROM {63}] $data_slice_0
+set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_0
+
+set data_slice_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1]
+set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_1
+set_property -dict [list CONFIG.DIN_TO {64}] $data_slice_1
+set_property -dict [list CONFIG.DIN_FROM {127}] $data_slice_1
+set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_1
+
+set data_slice_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2]
+set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_2
+set_property -dict [list CONFIG.DIN_TO {128}] $data_slice_2
+set_property -dict [list CONFIG.DIN_FROM {191}] $data_slice_2
+set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_2
+
+set data_slice_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3]
+set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_3
+set_property -dict [list CONFIG.DIN_TO {192}] $data_slice_3
+set_property -dict [list CONFIG.DIN_FROM {255}] $data_slice_3
+set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_3
+
 # connections (spi)
 
 ad_connect  spi_csn_i   axi_usdrx1_spi/ss_i
@@ -165,78 +121,29 @@ ad_connect  spi_sdo_o   axi_usdrx1_spi/io0_o
 ad_connect  spi_sdi_i   axi_usdrx1_spi/io1_i
 ad_connect  sys_cpu_clk axi_usdrx1_spi/ext_spi_clk
 
-# connections (gt)
-
-ad_connect util_usdrx1_gt/qpll_ref_clk rx_ref_clk
-ad_connect util_usdrx1_gt/cpll_ref_clk rx_ref_clk
-
-ad_connect  axi_usdrx1_gt/gt_pll_0 util_usdrx1_gt/gt_pll_0
-ad_connect  axi_usdrx1_gt/gt_pll_1 util_usdrx1_gt/gt_pll_1
-ad_connect  axi_usdrx1_gt/gt_pll_2 util_usdrx1_gt/gt_pll_2
-ad_connect  axi_usdrx1_gt/gt_pll_3 util_usdrx1_gt/gt_pll_3
-ad_connect  axi_usdrx1_gt/gt_pll_4 util_usdrx1_gt/gt_pll_4
-ad_connect  axi_usdrx1_gt/gt_pll_5 util_usdrx1_gt/gt_pll_5
-ad_connect  axi_usdrx1_gt/gt_pll_6 util_usdrx1_gt/gt_pll_6
-ad_connect  axi_usdrx1_gt/gt_pll_7 util_usdrx1_gt/gt_pll_7
-
-ad_connect  axi_usdrx1_gt/gt_rx_0 util_usdrx1_gt/gt_rx_0
-ad_connect  axi_usdrx1_gt/gt_rx_1 util_usdrx1_gt/gt_rx_1
-ad_connect  axi_usdrx1_gt/gt_rx_2 util_usdrx1_gt/gt_rx_2
-ad_connect  axi_usdrx1_gt/gt_rx_3 util_usdrx1_gt/gt_rx_3
-ad_connect  axi_usdrx1_gt/gt_rx_4 util_usdrx1_gt/gt_rx_4
-ad_connect  axi_usdrx1_gt/gt_rx_5 util_usdrx1_gt/gt_rx_5
-ad_connect  axi_usdrx1_gt/gt_rx_6 util_usdrx1_gt/gt_rx_6
-ad_connect  axi_usdrx1_gt/gt_rx_7 util_usdrx1_gt/gt_rx_7
-
-ad_connect  axi_usdrx1_gt/gt_rx_ip_0 axi_usdrx1_jesd/gt0_rx
-ad_connect  axi_usdrx1_gt/gt_rx_ip_1 axi_usdrx1_jesd/gt1_rx
-ad_connect  axi_usdrx1_gt/gt_rx_ip_2 axi_usdrx1_jesd/gt2_rx
-ad_connect  axi_usdrx1_gt/gt_rx_ip_3 axi_usdrx1_jesd/gt3_rx
-ad_connect  axi_usdrx1_gt/gt_rx_ip_4 axi_usdrx1_jesd/gt4_rx
-ad_connect  axi_usdrx1_gt/gt_rx_ip_5 axi_usdrx1_jesd/gt5_rx
-ad_connect  axi_usdrx1_gt/gt_rx_ip_6 axi_usdrx1_jesd/gt6_rx
-ad_connect  axi_usdrx1_gt/gt_rx_ip_7 axi_usdrx1_jesd/gt7_rx
-
-ad_connect  axi_usdrx1_gt/rx_gt_comma_align_enb_0 axi_usdrx1_jesd/rxencommaalign_out
-ad_connect  axi_usdrx1_gt/rx_gt_comma_align_enb_1 axi_usdrx1_jesd/rxencommaalign_out
-ad_connect  axi_usdrx1_gt/rx_gt_comma_align_enb_2 axi_usdrx1_jesd/rxencommaalign_out
-ad_connect  axi_usdrx1_gt/rx_gt_comma_align_enb_3 axi_usdrx1_jesd/rxencommaalign_out
-ad_connect  axi_usdrx1_gt/rx_gt_comma_align_enb_4 axi_usdrx1_jesd/rxencommaalign_out
-ad_connect  axi_usdrx1_gt/rx_gt_comma_align_enb_5 axi_usdrx1_jesd/rxencommaalign_out
-ad_connect  axi_usdrx1_gt/rx_gt_comma_align_enb_6 axi_usdrx1_jesd/rxencommaalign_out
-ad_connect  axi_usdrx1_gt/rx_gt_comma_align_enb_7 axi_usdrx1_jesd/rxencommaalign_out
-
 # connections (adc)
 
-ad_connect  rx_data_p   util_usdrx1_gt/rx_p
-ad_connect  rx_data_n   util_usdrx1_gt/rx_n
-ad_connect  rx_sync     util_usdrx1_gt/rx_sync
-ad_connect  rx_sysref   util_usdrx1_gt/rx_ip_sysref
+ad_xcvrcon  util_usdrx1_xcvr axi_usdrx1_xcvr axi_usdrx1_jesd
+ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_0/rx_clk
+ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_1/rx_clk
+ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_2/rx_clk
+ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_3/rx_clk
+ad_connect  axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_0/rx_sof
+ad_connect  axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_1/rx_sof
+ad_connect  axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_2/rx_sof
+ad_connect  axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_3/rx_sof
 
-ad_connect  util_usdrx1_gt/rx_out_clk     util_usdrx1_gt/rx_clk
-ad_connect  util_usdrx1_gt/rx_out_clk     axi_usdrx1_jesd/rx_core_clk
+ad_connect  axi_usdrx1_jesd/rx_tdata data_slice_0/Din
+ad_connect  axi_usdrx1_jesd/rx_tdata data_slice_1/Din
+ad_connect  axi_usdrx1_jesd/rx_tdata data_slice_2/Din
+ad_connect  axi_usdrx1_jesd/rx_tdata data_slice_3/Din
 
-ad_connect  util_usdrx1_gt/rx_ip_rst      axi_usdrx1_jesd/rx_reset
-ad_connect  util_usdrx1_gt/rx_ip_rst_done axi_usdrx1_jesd/rx_reset_done
-ad_connect  util_usdrx1_gt/rx_ip_sysref   axi_usdrx1_jesd/rx_sysref
-ad_connect  util_usdrx1_gt/rx_ip_sync     axi_usdrx1_jesd/rx_sync
-ad_connect  util_usdrx1_gt/rx_ip_sof      axi_usdrx1_jesd/rx_start_of_frame
-ad_connect  util_usdrx1_gt/rx_ip_data     axi_usdrx1_jesd/rx_tdata
+ad_connect  data_slice_0/Dout axi_ad9671_core_0/rx_data
+ad_connect  data_slice_1/Dout axi_ad9671_core_1/rx_data
+ad_connect  data_slice_2/Dout axi_ad9671_core_2/rx_data
+ad_connect  data_slice_3/Dout axi_ad9671_core_3/rx_data
 
-ad_connect gt_rx_data                       util_usdrx1_gt/rx_data
-ad_connect util_usdrx1_gt/rx_out_clk        axi_ad9671_core_0/rx_clk
-ad_connect gt_rx_data_0                     axi_ad9671_core_0/rx_data
-ad_connect util_usdrx1_gt/rx_sof            axi_ad9671_core_0/rx_sof
-ad_connect util_usdrx1_gt/rx_out_clk        axi_ad9671_core_1/rx_clk
-ad_connect gt_rx_data_1                     axi_ad9671_core_1/rx_data
-ad_connect util_usdrx1_gt/rx_sof            axi_ad9671_core_1/rx_sof
-ad_connect util_usdrx1_gt/rx_out_clk        axi_ad9671_core_2/rx_clk
-ad_connect gt_rx_data_2                     axi_ad9671_core_2/rx_data
-ad_connect util_usdrx1_gt/rx_sof            axi_ad9671_core_2/rx_sof
-ad_connect util_usdrx1_gt/rx_out_clk        axi_ad9671_core_3/rx_clk
-ad_connect gt_rx_data_3                     axi_ad9671_core_3/rx_data
-ad_connect util_usdrx1_gt/rx_sof            axi_ad9671_core_3/rx_sof
-ad_connect axi_ad9671_core_0/adc_clk        usdrx1_fifo/adc_clk
+ad_connect util_usdrx1_xcvr/rx_out_clk_0    usdrx1_fifo/adc_clk
 ad_connect adc_data_0                       axi_ad9671_core_0/adc_data
 ad_connect adc_data_1                       axi_ad9671_core_1/adc_data
 ad_connect adc_data_2                       axi_ad9671_core_2/adc_data
@@ -264,7 +171,8 @@ ad_connect axi_ad9671_adc_sync              axi_ad9671_core_1/adc_sync_in
 ad_connect axi_ad9671_adc_sync              axi_ad9671_core_2/adc_sync_in
 ad_connect axi_ad9671_adc_sync              axi_ad9671_core_3/adc_sync_in
 
-ad_connect util_usdrx1_gt/rx_rst            usdrx1_fifo/adc_rst
+ad_connect axi_usdrx1_jesd_rstgen/peripheral_reset   usdrx1_fifo/adc_rst
+
 ad_connect adc_dovf                         usdrx1_fifo/adc_wovf
 
 ad_connect usdrx1_fifo/dma_wdata            axi_usdrx1_dma/s_axis_data
@@ -281,7 +189,7 @@ ad_cpu_interconnect  0x44A10000 axi_ad9671_core_1
 ad_cpu_interconnect  0x44A20000 axi_ad9671_core_2
 ad_cpu_interconnect  0x44A30000 axi_ad9671_core_3
 
-ad_cpu_interconnect  0x44A60000 axi_usdrx1_gt
+ad_cpu_interconnect  0x44A60000 axi_usdrx1_xcvr
 ad_cpu_interconnect  0x44A91000 axi_usdrx1_jesd
 ad_cpu_interconnect  0x7c400000 axi_usdrx1_dma
 ad_cpu_interconnect  0x7c420000 axi_usdrx1_spi
@@ -291,7 +199,7 @@ ad_mem_hp2_interconnect sys_200m_clk axi_usdrx1_dma/m_dest_axi
 ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_xcvr/m_axi
 
 #interrupts
 
@@ -300,7 +208,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq
 
 # ila
 
-set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_ad9671]
+set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_ad9671]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671
 set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_ad9671
 set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index c29b78937..e1acdb44d 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -21,12 +21,12 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -57,12 +57,12 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9671 clean
 	make -C ../../../library/xilinx/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_jesd_gt clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 
 
 usdrx1_zc706.sdk/system_top.hdf: $(M_DEPS)
@@ -73,12 +73,12 @@ usdrx1_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9671
 	make -C ../../../library/xilinx/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_jesd_gt
+	make -C ../../../library/xilinx/util_adxcvr
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/usdrx1/zc706/system_constr.xdc b/projects/usdrx1/zc706/system_constr.xdc
index e86c8c2d2..a162916e4 100644
--- a/projects/usdrx1/zc706/system_constr.xdc
+++ b/projects/usdrx1/zc706/system_constr.xdc
@@ -82,4 +82,4 @@ set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVCMOS25} [get_ports dac_data
 # clocks
 
 create_clock -name rx_ref_clk   -period 12.50 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk]
+create_clock -name rx_div_clk   -period 12.50 [get_pins i_system_wrapper/system_i/util_usdrx1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v
index f782ab0ae..082184c74 100644
--- a/projects/usdrx1/zc706/system_top.v
+++ b/projects/usdrx1/zc706/system_top.v
@@ -265,11 +265,6 @@ module system_top (
   wire            adc_dovf_1;
   wire            adc_dovf_2;
   wire            adc_dovf_3;
-  wire   [255:0]  gt_rx_data;
-  wire    [63:0]  gt_rx_data_0;
-  wire    [63:0]  gt_rx_data_1;
-  wire    [63:0]  gt_rx_data_2;
-  wire    [63:0]  gt_rx_data_3;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
@@ -301,11 +296,6 @@ module system_top (
 
   // single dma for all channels
 
-  assign gt_rx_data_3 = gt_rx_data[255:192];
-  assign gt_rx_data_2 = gt_rx_data[191:128];
-  assign gt_rx_data_1 = gt_rx_data[127: 64];
-  assign gt_rx_data_0 = gt_rx_data[ 63:  0];
-
   assign adc_data   = {adc_data_3, adc_data_2, adc_data_1, adc_data_0};
   assign adc_valid  = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ;
   assign adc_dovf_0 = adc_dovf;
@@ -452,11 +442,6 @@ module system_top (
     .adc_dovf_1 (adc_dovf_1),
     .adc_dovf_2 (adc_dovf_2),
     .adc_dovf_3 (adc_dovf_3),
-    .gt_rx_data (gt_rx_data),
-    .gt_rx_data_0 (gt_rx_data_0),
-    .gt_rx_data_1 (gt_rx_data_1),
-    .gt_rx_data_2 (gt_rx_data_2),
-    .gt_rx_data_3 (gt_rx_data_3),
     .hdmi_data (hdmi_data),
     .hdmi_data_e (hdmi_data_e),
     .hdmi_hsync (hdmi_hsync),
@@ -476,11 +461,25 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_data_4_n (rx_data_n[4]),
+    .rx_data_4_p (rx_data_p[4]),
+    .rx_data_5_n (rx_data_n[5]),
+    .rx_data_5_p (rx_data_p[5]),
+    .rx_data_6_n (rx_data_n[6]),
+    .rx_data_6_p (rx_data_p[6]),
+    .rx_data_7_n (rx_data_n[7]),
+    .rx_data_7_p (rx_data_p[7]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spdif (spdif),
     .spi_clk_i (spi_clk),
     .spi_clk_o (spi_clk),

From 1b3fcb586397790000dd0f4b567a455e8c671e7e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 17 Oct 2016 16:10:48 -0400
Subject: [PATCH 611/972] util_adxcvr- parameter defaults

---
 library/xilinx/util_adxcvr/util_adxcvr.v     | 179 ++---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 673 +++++++++----------
 library/xilinx/util_adxcvr/util_adxcvr_xcm.v |  66 +-
 3 files changed, 462 insertions(+), 456 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v
index a847e3ea6..43e0aafa3 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr.v
@@ -40,23 +40,36 @@
 
 module util_adxcvr #(
 
-  // parameters
+  // gtxe2(0), gthe3(1), gthe4(2)
 
-  parameter   integer RX_NUM_OF_LANES = 8,
-  parameter   integer TX_NUM_OF_LANES = 8,
   parameter   integer XCVR_TYPE = 0,
-  parameter   integer CPLL_TX_OR_RX_N = 0,
-  parameter   integer CPLL_FBDIV = 2,
+
+  // qpll-configuration
+
   parameter   integer QPLL_REFCLK_DIV = 1,
   parameter   integer QPLL_FBDIV_RATIO = 1,
-  parameter   integer RX_OUT_DIV = 1,
-  parameter   integer RX_CLK25_DIV = 20,
+  parameter   [26:0]  QPLL_CFG = 27'h0680181,
+  parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000,
+
+  // cpll-configuration
+
+  parameter   integer CPLL_FBDIV = 2,
+  parameter   integer CPLL_FBDIV_4_5 = 5,
+  parameter   integer CPLL_TX_OR_RX_N = 0,
+
+  // tx-configuration
+
+  parameter   integer TX_NUM_OF_LANES = 8,
   parameter   integer TX_OUT_DIV = 1,
   parameter   integer TX_CLK25_DIV = 20,
-  parameter   [31:0]  PMA_RSV = 32'h001e7080,
-  parameter   [72:0]  RX_CDR_CFG = 72'h0b000023ff10400020,
-  parameter   [26:0]  QPLL_CFG = 27'h0680181,
-  parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000) (
+
+  // rx-configuration
+
+  parameter   integer RX_NUM_OF_LANES = 8,
+  parameter   integer RX_OUT_DIV = 1,
+  parameter   integer RX_CLK25_DIV = 20,
+  parameter   [31:0]  RX_PMA_CFG = 32'h001e7080,
+  parameter   [72:0]  RX_CDR_CFG = 72'h0b000023ff10400020) (
 
   input           up_rstn,
   input           up_clk,
@@ -1108,13 +1121,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (0),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_0 (
     .qpll2ch_clk (qpll2ch_clk_0),
@@ -1205,13 +1219,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (1),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_1 (
     .qpll2ch_clk (qpll2ch_clk_0),
@@ -1302,13 +1317,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (2),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_2 (
     .qpll2ch_clk (qpll2ch_clk_0),
@@ -1399,13 +1415,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (3),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_3 (
     .qpll2ch_clk (qpll2ch_clk_0),
@@ -1528,13 +1545,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (4),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_4 (
     .qpll2ch_clk (qpll2ch_clk_4),
@@ -1625,13 +1643,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (5),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_5 (
     .qpll2ch_clk (qpll2ch_clk_4),
@@ -1722,13 +1741,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (6),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_6 (
     .qpll2ch_clk (qpll2ch_clk_4),
@@ -1819,13 +1839,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (7),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_7 (
     .qpll2ch_clk (qpll2ch_clk_4),
@@ -1948,13 +1969,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (8),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_8 (
     .qpll2ch_clk (qpll2ch_clk_8),
@@ -2045,13 +2067,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (9),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_9 (
     .qpll2ch_clk (qpll2ch_clk_8),
@@ -2142,13 +2165,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (10),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_10 (
     .qpll2ch_clk (qpll2ch_clk_8),
@@ -2239,13 +2263,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (11),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_11 (
     .qpll2ch_clk (qpll2ch_clk_8),
@@ -2368,13 +2393,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (12),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_12 (
     .qpll2ch_clk (qpll2ch_clk_12),
@@ -2465,13 +2491,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (13),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_13 (
     .qpll2ch_clk (qpll2ch_clk_12),
@@ -2562,13 +2589,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (14),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_14 (
     .qpll2ch_clk (qpll2ch_clk_12),
@@ -2659,13 +2687,14 @@ module util_adxcvr #(
   util_adxcvr_xch #(
     .XCVR_ID (15),
     .XCVR_TYPE (XCVR_TYPE),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .RX_OUT_DIV (RX_OUT_DIV),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
+    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
-    .PMA_RSV (PMA_RSV),
+    .RX_OUT_DIV (RX_OUT_DIV),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_15 (
     .qpll2ch_clk (qpll2ch_clk_12),
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 39c323af2..14b477914 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -43,14 +43,18 @@ module util_adxcvr_xch #(
 
   parameter   integer XCVR_ID = 0,
   parameter   integer XCVR_TYPE = 0,
-  parameter   integer CPLL_TX_OR_RX_N = 0,
+
   parameter   integer CPLL_FBDIV = 2,
-  parameter   integer RX_OUT_DIV = 1,
-  parameter   integer RX_CLK25_DIV = 10,
+  parameter   integer CPLL_FBDIV_4_5 = 5,
+  parameter   integer CPLL_TX_OR_RX_N = 0,
+
   parameter   integer TX_OUT_DIV = 1,
-  parameter   integer TX_CLK25_DIV = 10,
-  parameter   [31:0]  PMA_RSV = 32'h00018480,
-  parameter   [72:0]  RX_CDR_CFG = 72'h03000023ff20400020) (
+  parameter   integer TX_CLK25_DIV = 20,
+
+  parameter   integer RX_OUT_DIV = 1,
+  parameter   integer RX_CLK25_DIV = 20,
+  parameter   [31:0]  RX_PMA_CFG = 32'h001e7080,
+  parameter   [72:0]  RX_CDR_CFG = 72'h0b000023ff10400020) (
 
   // pll interface
 
@@ -313,48 +317,16 @@ module util_adxcvr_xch #(
   generate
   if (XCVR_TYPE == 0) begin
   GTXE2_CHANNEL #(
-    .SIM_RECEIVER_DETECT_PASS ("TRUE"),
-    .SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
-    .SIM_RESET_SPEEDUP ("TRUE"),
-    .SIM_CPLLREFCLK_SEL (3'b001),
-    .SIM_VERSION ("3.0"),
     .ALIGN_COMMA_DOUBLE ("FALSE"),
     .ALIGN_COMMA_ENABLE (10'b1111111111),
-    .ALIGN_COMMA_WORD (1),
+    .ALIGN_COMMA_WORD (4),
     .ALIGN_MCOMMA_DET ("TRUE"),
     .ALIGN_MCOMMA_VALUE (10'b1010000011),
     .ALIGN_PCOMMA_DET ("TRUE"),
     .ALIGN_PCOMMA_VALUE (10'b0101111100),
-    .SHOW_REALIGN_COMMA ("TRUE"),
-    .RXSLIDE_AUTO_WAIT (7),
-    .RXSLIDE_MODE ("OFF"),
-    .RX_SIG_VALID_DLY (10),
-    .RX_DISPERR_SEQ_MATCH ("TRUE"),
-    .DEC_MCOMMA_DETECT ("TRUE"),
-    .DEC_PCOMMA_DETECT ("TRUE"),
-    .DEC_VALID_COMMA_ONLY ("FALSE"),
     .CBCC_DATA_SOURCE_SEL ("DECODED"),
-    .CLK_COR_SEQ_2_USE ("FALSE"),
-    .CLK_COR_KEEP_IDLE ("FALSE"),
-    .CLK_COR_MAX_LAT (35),
-    .CLK_COR_MIN_LAT (31),
-    .CLK_COR_PRECEDENCE ("TRUE"),
-    .CLK_COR_REPEAT_WAIT (0),
-    .CLK_COR_SEQ_LEN (1),
-    .CLK_COR_SEQ_1_ENABLE (4'b1111),
-    .CLK_COR_SEQ_1_1 (10'b0000000000),
-    .CLK_COR_SEQ_1_2 (10'b0000000000),
-    .CLK_COR_SEQ_1_3 (10'b0000000000),
-    .CLK_COR_SEQ_1_4 (10'b0000000000),
-    .CLK_CORRECT_USE ("FALSE"),
-    .CLK_COR_SEQ_2_ENABLE (4'b1111),
-    .CLK_COR_SEQ_2_1 (10'b0000000000),
-    .CLK_COR_SEQ_2_2 (10'b0000000000),
-    .CLK_COR_SEQ_2_3 (10'b0000000000),
-    .CLK_COR_SEQ_2_4 (10'b0000000000),
     .CHAN_BOND_KEEP_ALIGN ("FALSE"),
-    .CHAN_BOND_MAX_SKEW (7),
-    .CHAN_BOND_SEQ_LEN (1),
+    .CHAN_BOND_MAX_SKEW (1),
     .CHAN_BOND_SEQ_1_1 (10'b0000000000),
     .CHAN_BOND_SEQ_1_2 (10'b0000000000),
     .CHAN_BOND_SEQ_1_3 (10'b0000000000),
@@ -366,9 +338,35 @@ module util_adxcvr_xch #(
     .CHAN_BOND_SEQ_2_4 (10'b0000000000),
     .CHAN_BOND_SEQ_2_ENABLE (4'b1111),
     .CHAN_BOND_SEQ_2_USE ("FALSE"),
-    .FTS_DESKEW_SEQ_ENABLE (4'b1111),
-    .FTS_LANE_DESKEW_CFG (4'b1111),
-    .FTS_LANE_DESKEW_EN ("FALSE"),
+    .CHAN_BOND_SEQ_LEN (1),
+    .CLK_CORRECT_USE ("FALSE"),
+    .CLK_COR_KEEP_IDLE ("FALSE"),
+    .CLK_COR_MAX_LAT (12),
+    .CLK_COR_MIN_LAT (8),
+    .CLK_COR_PRECEDENCE ("TRUE"),
+    .CLK_COR_REPEAT_WAIT (0),
+    .CLK_COR_SEQ_1_1 (10'b0100000000),
+    .CLK_COR_SEQ_1_2 (10'b0000000000),
+    .CLK_COR_SEQ_1_3 (10'b0000000000),
+    .CLK_COR_SEQ_1_4 (10'b0000000000),
+    .CLK_COR_SEQ_1_ENABLE (4'b1111),
+    .CLK_COR_SEQ_2_1 (10'b0100000000),
+    .CLK_COR_SEQ_2_2 (10'b0000000000),
+    .CLK_COR_SEQ_2_3 (10'b0000000000),
+    .CLK_COR_SEQ_2_4 (10'b0000000000),
+    .CLK_COR_SEQ_2_ENABLE (4'b1111),
+    .CLK_COR_SEQ_2_USE ("FALSE"),
+    .CLK_COR_SEQ_LEN (1),
+    .CPLL_CFG (24'hBC07DC),
+    .CPLL_FBDIV (CPLL_FBDIV),
+    .CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
+    .CPLL_INIT_CFG (24'h00001E),
+    .CPLL_LOCK_CFG (16'h01E8),
+    .CPLL_REFCLK_DIV (1),
+    .DEC_MCOMMA_DETECT ("TRUE"),
+    .DEC_PCOMMA_DETECT ("TRUE"),
+    .DEC_VALID_COMMA_ONLY ("FALSE"),
+    .DMONITOR_CFG (24'h000A00),
     .ES_CONTROL (6'b000000),
     .ES_ERRDET_EN ("TRUE"),
     .ES_EYE_SCAN_EN ("TRUE"),
@@ -379,94 +377,137 @@ module util_adxcvr_xch #(
     .ES_QUAL_MASK (80'h00000000000000000000),
     .ES_SDATA_MASK (80'h00000000000000000000),
     .ES_VERT_OFFSET (9'b000000000),
-    .RX_DATA_WIDTH (40),
+    .FTS_DESKEW_SEQ_ENABLE (4'b1111),
+    .FTS_LANE_DESKEW_CFG (4'b1111),
+    .FTS_LANE_DESKEW_EN ("FALSE"),
+    .GEARBOX_MODE (3'b000),
+    .IS_CPLLLOCKDETCLK_INVERTED (1'b0),
+    .IS_DRPCLK_INVERTED (1'b0),
+    .IS_GTGREFCLK_INVERTED (1'b0),
+    .IS_RXUSRCLK2_INVERTED (1'b0),
+    .IS_RXUSRCLK_INVERTED (1'b0),
+    .IS_TXPHDLYTSTCLK_INVERTED (1'b0),
+    .IS_TXUSRCLK2_INVERTED (1'b0),
+    .IS_TXUSRCLK_INVERTED (1'b0),
     .OUTREFCLK_SEL_INV (2'b11),
-    .PMA_RSV (PMA_RSV),
-    .PMA_RSV2 (16'h2070),
-    .PMA_RSV3 (2'b00),
-    .PMA_RSV4 (32'h00000000),
-    .RX_BIAS_CFG (12'b000000000100),
-    .DMONITOR_CFG (24'h000A00),
-    .RX_CM_SEL (2'b11),
-    .RX_CM_TRIM (3'b010),
-    .RX_DEBUG_CFG (12'b000000000000),
-    .RX_OS_CFG (13'b0000010000000),
-    .TERM_RCAL_CFG (5'b10000),
-    .TERM_RCAL_OVRD (1'b0),
-    .TST_RSV (32'h00000000),
-    .RX_CLK25_DIV (RX_CLK25_DIV),
-    .TX_CLK25_DIV (TX_CLK25_DIV),
-    .UCODEER_CLR (1'b0),
     .PCS_PCIE_EN ("FALSE"),
     .PCS_RSVD_ATTR (48'h000000000000),
-    .RXBUF_ADDR_MODE ("FULL"),
+    .PD_TRANS_TIME_FROM_P2 (12'h03c),
+    .PD_TRANS_TIME_NONE_P2 (8'h3c),
+    .PD_TRANS_TIME_TO_P2 (8'h64),
+    .PMA_RSV (RX_PMA_CFG),
+    .PMA_RSV2 (16'h2050),
+    .PMA_RSV3 (2'b00),
+    .PMA_RSV4 (32'h00000000),
+    .RXBUFRESET_TIME (5'b00001),
+    .RXBUF_ADDR_MODE ("FAST"),
     .RXBUF_EIDLE_HI_CNT (4'b1000),
     .RXBUF_EIDLE_LO_CNT (4'b0000),
     .RXBUF_EN ("TRUE"),
-    .RX_BUFFER_CFG (6'b000000),
     .RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
     .RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
     .RXBUF_RESET_ON_EIDLE ("FALSE"),
     .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
-    .RXBUFRESET_TIME (5'b00001),
-    .RXBUF_THRESH_OVFLW (61),
-    .RXBUF_THRESH_OVRD ("FALSE"),
-    .RXBUF_THRESH_UNDFLW (4),
-    .RXDLY_CFG (16'h001F),
-    .RXDLY_LCFG (9'h030),
-    .RXDLY_TAP_CFG (16'h0000),
-    .RXPH_CFG (24'h000000),
-    .RXPHDLY_CFG (24'h084020),
-    .RXPH_MONITOR_SEL (5'b00000),
-    .RX_XCLK_SEL ("RXREC"),
-    .RX_DDI_SEL (6'b000000),
-    .RX_DEFER_RESET_BUF_EN ("TRUE"),
+    .RXBUF_THRESH_OVFLW (57),
+    .RXBUF_THRESH_OVRD ("TRUE"),
+    .RXBUF_THRESH_UNDFLW (3),
+    .RXCDRFREQRESET_TIME (5'b00001),
+    .RXCDRPHRESET_TIME (5'b00001),
     .RXCDR_CFG (RX_CDR_CFG),
     .RXCDR_FR_RESET_ON_EIDLE (1'b0),
     .RXCDR_HOLD_DURING_EIDLE (1'b0),
-    .RXCDR_PH_RESET_ON_EIDLE (1'b0),
     .RXCDR_LOCK_CFG (6'b010101),
-    .RXCDRFREQRESET_TIME (5'b00001),
-    .RXCDRPHRESET_TIME (5'b00001),
-    .RXISCANRESET_TIME (5'b00001),
-    .RXPCSRESET_TIME (5'b00001),
-    .RXPMARESET_TIME (5'b00011),
-    .RXOOB_CFG (7'b0000110),
+    .RXCDR_PH_RESET_ON_EIDLE (1'b0),
+    .RXDFELPMRESET_TIME (7'b0001111),
+    .RXDLY_CFG (16'h001F),
+    .RXDLY_LCFG (9'h030),
+    .RXDLY_TAP_CFG (16'h0000),
     .RXGEARBOX_EN ("FALSE"),
-    .GEARBOX_MODE (3'b000),
+    .RXISCANRESET_TIME (5'b00001),
+    .RXLPM_HF_CFG (14'b00000011110000),
+    .RXLPM_LF_CFG (14'b00000011110000),
+    .RXOOB_CFG (7'b0000110),
+    .RXOUT_DIV (RX_OUT_DIV),
+    .RXPCSRESET_TIME (5'b00001),
+    .RXPHDLY_CFG (24'h084020),
+    .RXPH_CFG (24'h000000),
+    .RXPH_MONITOR_SEL (5'b00000),
+    .RXPMARESET_TIME (5'b00011),
     .RXPRBS_ERR_LOOPBACK (1'b0),
-    .PD_TRANS_TIME_FROM_P2 (12'h03c),
-    .PD_TRANS_TIME_NONE_P2 (8'h3c),
-    .PD_TRANS_TIME_TO_P2 (8'h64),
+    .RXSLIDE_AUTO_WAIT (7),
+    .RXSLIDE_MODE ("OFF"),
+    .RX_BIAS_CFG (12'b000000000100),
+    .RX_BUFFER_CFG (6'b000000),
+    .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_CLKMUX_PD (1'b1),
+    .RX_CM_SEL (2'b11),
+    .RX_CM_TRIM (3'b010),
+    .RX_DATA_WIDTH (40),
+    .RX_DDI_SEL (6'b000000),
+    .RX_DEBUG_CFG (12'b000000000000),
+    .RX_DEFER_RESET_BUF_EN ("TRUE"),
+    .RX_DFE_GAIN_CFG (23'h020FEA),
+    .RX_DFE_H2_CFG (12'b000000000000),
+    .RX_DFE_H3_CFG (12'b000001000000),
+    .RX_DFE_H4_CFG (11'b00011110000),
+    .RX_DFE_H5_CFG (11'b00011100000),
+    .RX_DFE_KL_CFG (13'b0000011111110),
+    .RX_DFE_KL_CFG2 (32'h301148AC),
+    .RX_DFE_LPM_CFG (16'h0104),
+    .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
+    .RX_DFE_UT_CFG (17'b10001111000000000),
+    .RX_DFE_VP_CFG (17'b00011111100000011),
+    .RX_DFE_XYD_CFG (13'b0000000000000),
+    .RX_DISPERR_SEQ_MATCH ("TRUE"),
+    .RX_INT_DATAWIDTH (1),
+    .RX_OS_CFG (13'b0000010000000),
+    .RX_SIG_VALID_DLY (10),
+    .RX_XCLK_SEL ("RXREC"),
     .SAS_MAX_COM (64),
     .SAS_MIN_COM (36),
-    .SATA_BURST_SEQ_LEN (4'b1111),
-    .SATA_BURST_VAL (3'b100),
-    .SATA_EIDLE_VAL (3'b100),
+    .SATA_BURST_SEQ_LEN (4'b0101),
+    .SATA_BURST_VAL (3'b111),
+    .SATA_CPLL_CFG ("VCO_3000MHZ"),
+    .SATA_EIDLE_VAL (3'b111),
     .SATA_MAX_BURST (8),
     .SATA_MAX_INIT (21),
     .SATA_MAX_WAKE (7),
     .SATA_MIN_BURST (4),
     .SATA_MIN_INIT (12),
     .SATA_MIN_WAKE (4),
+    .SHOW_REALIGN_COMMA ("TRUE"),
+    .SIM_CPLLREFCLK_SEL (3'b001),
+    .SIM_RECEIVER_DETECT_PASS ("TRUE"),
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
+    .SIM_VERSION ("4.0"),
+    .TERM_RCAL_CFG (5'b10000),
+    .TERM_RCAL_OVRD (1'b0),
     .TRANS_TIME_RATE (8'h0E),
+    .TST_RSV (32'h00000000),
     .TXBUF_EN ("TRUE"),
     .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
     .TXDLY_CFG (16'h001F),
     .TXDLY_LCFG (9'h030),
     .TXDLY_TAP_CFG (16'h0000),
-    .TXPH_CFG (16'h0780),
+    .TXGEARBOX_EN ("FALSE"),
+    .TXOUT_DIV (TX_OUT_DIV),
+    .TXPCSRESET_TIME (5'b00001),
     .TXPHDLY_CFG (24'h084020),
+    .TXPH_CFG (16'h0780),
     .TXPH_MONITOR_SEL (5'b00000),
-    .TX_XCLK_SEL ("TXOUT"),
+    .TXPMARESET_TIME (5'b00001),
+    .TX_CLK25_DIV (TX_CLK25_DIV),
+    .TX_CLKMUX_PD (1'b1),
     .TX_DATA_WIDTH (40),
     .TX_DEEMPH0 (5'b00000),
     .TX_DEEMPH1 (5'b00000),
+    .TX_DRIVE_MODE ("DIRECT"),
     .TX_EIDLE_ASSERT_DELAY (3'b110),
     .TX_EIDLE_DEASSERT_DELAY (3'b100),
+    .TX_INT_DATAWIDTH (1),
     .TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
     .TX_MAINCURSOR_SEL (1'b0),
-    .TX_DRIVE_MODE ("DIRECT"),
     .TX_MARGIN_FULL_0 (7'b1001110),
     .TX_MARGIN_FULL_1 (7'b1001001),
     .TX_MARGIN_FULL_2 (7'b1000101),
@@ -477,65 +518,24 @@ module util_adxcvr_xch #(
     .TX_MARGIN_LOW_2 (7'b1000010),
     .TX_MARGIN_LOW_3 (7'b1000000),
     .TX_MARGIN_LOW_4 (7'b1000000),
-    .TXGEARBOX_EN ("FALSE"),
-    .TXPCSRESET_TIME (5'b00001),
-    .TXPMARESET_TIME (5'b00001),
+    .TX_PREDRIVER_MODE (1'b0),
+    .TX_QPI_STATUS_EN (1'b0),
     .TX_RXDETECT_CFG (14'h1832),
     .TX_RXDETECT_REF (3'b100),
-    .CPLL_CFG (24'hBC07DC),
-    .CPLL_FBDIV (CPLL_FBDIV),
-    .CPLL_FBDIV_45 (5),
-    .CPLL_INIT_CFG (24'h00001E),
-    .CPLL_LOCK_CFG (16'h01E8),
-    .CPLL_REFCLK_DIV (1),
-    .RXOUT_DIV (RX_OUT_DIV),
-    .TXOUT_DIV (TX_OUT_DIV),
-    .SATA_CPLL_CFG ("VCO_3000MHZ"),
-    .RXDFELPMRESET_TIME (7'b0001111),
-    .RXLPM_HF_CFG (14'b00000011110000),
-    .RXLPM_LF_CFG (14'b00000011110000),
-    .RX_DFE_GAIN_CFG (23'h020FEA),
-    .RX_DFE_H2_CFG (12'b000000000000),
-    .RX_DFE_H3_CFG (12'b000001000000),
-    .RX_DFE_H4_CFG (11'b00011110000),
-    .RX_DFE_H5_CFG (11'b00011100000),
-    .RX_DFE_KL_CFG (13'b0000011111110),
-    .RX_DFE_LPM_CFG (16'h0954),
-    .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
-    .RX_DFE_UT_CFG (17'b10001111000000000),
-    .RX_DFE_VP_CFG (17'b00011111100000011),
-    .RX_CLKMUX_PD (1'b1),
-    .TX_CLKMUX_PD (1'b1),
-    .RX_INT_DATAWIDTH (1),
-    .TX_INT_DATAWIDTH (1),
-    .TX_QPI_STATUS_EN (1'b0),
-    .RX_DFE_KL_CFG2 (32'h3010D90C),
-    .RX_DFE_XYD_CFG (13'b0001100010000),
-    .TX_PREDRIVER_MODE (1'b0))
+    .TX_XCLK_SEL ("TXOUT"),
+    .UCODEER_CLR (1'b0))
   i_gtxe2_channel (
+    .CFGRESET (1'h0),
+    .CLKRSVD (4'h0),
     .CPLLFBCLKLOST (),
     .CPLLLOCK (cpll_locked_s),
     .CPLLLOCKDETCLK (up_clk),
-    .CPLLLOCKEN (1'd1),
-    .CPLLPD (1'b0),
+    .CPLLLOCKEN (1'h1),
+    .CPLLPD (1'h0),
     .CPLLREFCLKLOST (),
-    .CPLLREFCLKSEL (3'b001),
+    .CPLLREFCLKSEL (3'h1),
     .CPLLRESET (up_cpll_rst),
-    .GTRSVD (16'b0000000000000000),
-    .PCSRSVDIN (16'b0000000000000000),
-    .PCSRSVDIN2 (5'b00000),
-    .PMARSVDIN (5'b00000),
-    .PMARSVDIN2 (5'b00000),
-    .TSTIN (20'b11111111111111111111),
-    .TSTOUT (),
-    .CLKRSVD (4'b0000),
-    .GTGREFCLK (1'd0),
-    .GTNORTHREFCLK0 (1'd0),
-    .GTNORTHREFCLK1 (1'd0),
-    .GTREFCLK0 (cpll_ref_clk),
-    .GTREFCLK1 (1'd0),
-    .GTSOUTHREFCLK0 (1'd0),
-    .GTSOUTHREFCLK1 (1'd0),
+    .DMONITOROUT (),
     .DRPADDR (up_addr_int[8:0]),
     .DRPCLK (up_clk),
     .DRPDI (up_wdata_int),
@@ -543,206 +543,183 @@ module util_adxcvr_xch #(
     .DRPEN (up_enb_int),
     .DRPRDY (up_ready_s),
     .DRPWE (up_wr_int),
-    .GTREFCLKMONITOR (),
+    .EYESCANDATAERROR (),
+    .EYESCANMODE (1'h0),
+    .EYESCANRESET (1'h0),
+    .EYESCANTRIGGER (1'h0),
+    .GTGREFCLK (1'h0),
+    .GTNORTHREFCLK0 (1'h0),
+    .GTNORTHREFCLK1 (1'h0),
+    .GTREFCLK0 (cpll_ref_clk),
+    .GTREFCLK1 (1'h0),
+    .GTRESETSEL (1'h0),
+    .GTRSVD (16'h0),
+    .GTRXRESET (up_rx_rst),
+    .GTSOUTHREFCLK0 (1'h0),
+    .GTSOUTHREFCLK1 (1'h0),
+    .GTTXRESET (up_tx_rst),
+    .GTXRXN (rx_n),
+    .GTXRXP (rx_p),
+    .GTXTXN (tx_n),
+    .GTXTXP (tx_p),
+    .LOOPBACK (3'h0),
+    .PCSRSVDIN (16'h0),
+    .PCSRSVDIN2 (5'h0),
+    .PMARSVDIN (5'h0),
+    .PMARSVDIN2 (5'h0),
     .QPLLCLK (qpll2ch_clk),
     .QPLLREFCLK (qpll2ch_ref_clk),
-    .RXSYSCLKSEL (rx_sys_clk_sel_s),
-    .TXSYSCLKSEL (tx_sys_clk_sel_s),
-    .DMONITOROUT (),
-    .TX8B10BEN (1'd1),
-    .LOOPBACK (3'd0),
-    .PHYSTATUS (),
-    .RXRATE (rx_rate_m2),
-    .RXVALID (),
-    .RXPD (2'b00),
-    .TXPD (2'b00),
-    .SETERRSTATUS (1'd0),
-    .EYESCANRESET (1'd0),
-    .RXUSERRDY (up_rx_user_ready),
-    .EYESCANDATAERROR (),
-    .EYESCANMODE (1'd0),
-    .EYESCANTRIGGER (1'd0),
-    .RXCDRFREQRESET (1'd0),
-    .RXCDRHOLD (1'd0),
-    .RXCDRLOCK (),
-    .RXCDROVRDEN (1'd0),
-    .RXCDRRESET (1'd0),
-    .RXCDRRESETRSV (1'd0),
-    .RXCLKCORCNT (),
-    .RX8B10BEN (1'd1),
-    .RXUSRCLK (rx_clk),
-    .RXUSRCLK2 (rx_clk),
-    .RXDATA ({rx_data_open_s[31:0], rx_data}),
-    .RXPRBSERR (),
-    .RXPRBSSEL (3'd0),
-    .RXPRBSCNTRESET (1'd0),
-    .RXDFEXYDEN (1'd0),
-    .RXDFEXYDHOLD (1'd0),
-    .RXDFEXYDOVRDEN (1'd0),
-    .RXDISPERR ({rx_disperr_open_s[3:0], rx_disperr}),
-    .RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
-    .GTXRXP (rx_p),
-    .GTXRXN (rx_n),
-    .RXBUFRESET (1'd0),
+    .RESETOVRD (1'h0),
+    .RX8B10BEN (1'h1),
+    .RXBUFRESET (1'h0),
     .RXBUFSTATUS (),
-    .RXDDIEN (1'd0),
-    .RXDLYBYPASS (1'd1),
-    .RXDLYEN (1'd0),
-    .RXDLYOVRDEN (1'd0),
-    .RXDLYSRESET (1'd0),
-    .RXDLYSRESETDONE (),
-    .RXPHALIGN (1'd0),
-    .RXPHALIGNDONE (),
-    .RXPHALIGNEN (1'd0),
-    .RXPHDLYPD (1'd0),
-    .RXPHDLYRESET (1'd0),
-    .RXPHMONITOR (),
-    .RXPHOVRDEN (1'd0),
-    .RXPHSLIPMONITOR (),
-    .RXSTATUS (),
     .RXBYTEISALIGNED (),
     .RXBYTEREALIGN (),
-    .RXCOMMADET (),
-    .RXCOMMADETEN (1'd1),
-    .RXMCOMMAALIGNEN (rx_calign),
-    .RXPCOMMAALIGNEN (rx_calign),
-    .RXCHANBONDSEQ (),
-    .RXCHBONDEN (1'd0),
-    .RXCHBONDLEVEL (3'd0),
-    .RXCHBONDMASTER (1'd1),
-    .RXCHBONDO (),
-    .RXCHBONDSLAVE (1'd0),
-    .RXCHANISALIGNED (),
-    .RXCHANREALIGN (),
-    .RXDFEAGCHOLD (1'd0),
-    .RXDFEAGCOVRDEN (1'd0),
-    .RXDFECM1EN (1'd0),
-    .RXDFELFHOLD (1'd0),
-    .RXDFELFOVRDEN (1'd1),
-    .RXDFELPMRESET (1'd0),
-    .RXDFETAP2HOLD (1'd0),
-    .RXDFETAP2OVRDEN (1'd0),
-    .RXDFETAP3HOLD (1'd0),
-    .RXDFETAP3OVRDEN (1'd0),
-    .RXDFETAP4HOLD (1'd0),
-    .RXDFETAP4OVRDEN (1'd0),
-    .RXDFETAP5HOLD (1'd0),
-    .RXDFETAP5OVRDEN (1'd0),
-    .RXDFEUTHOLD (1'd0),
-    .RXDFEUTOVRDEN (1'd0),
-    .RXDFEVPHOLD (1'd0),
-    .RXDFEVPOVRDEN (1'd0),
-    .RXDFEVSEN (1'd0),
-    .RXLPMLFKLOVRDEN (1'd0),
-    .RXMONITOROUT (),
-    .RXMONITORSEL (2'd0),
-    .RXOSHOLD (1'd0),
-    .RXOSOVRDEN (1'd0),
-    .RXLPMHFHOLD (1'd0),
-    .RXLPMHFOVRDEN (1'd0),
-    .RXLPMLFHOLD (1'd0),
-    .RXRATEDONE (),
-    .RXOUTCLK (rx_out_clk_s),
-    .RXOUTCLKFABRIC (),
-    .RXOUTCLKPCS (),
-    .RXOUTCLKSEL (up_rx_out_clk_sel),
-    .RXDATAVALID (),
-    .RXHEADER (),
-    .RXHEADERVALID (),
-    .RXSTARTOFSEQ (),
-    .RXGEARBOXSLIP (1'd0),
-    .GTRXRESET (up_rx_rst),
-    .RXOOBRESET (1'd0),
-    .RXPCSRESET (1'd0),
-    .RXPMARESET (1'd0),
-    .RXLPMEN (up_rx_lpm_dfe_n),
-    .RXCOMSASDET (),
-    .RXCOMWAKEDET (),
-    .RXCOMINITDET (),
-    .RXELECIDLE (),
-    .RXELECIDLEMODE (2'b10),
-    .RXPOLARITY (1'd0),
-    .RXSLIDE (1'd0),
+    .RXCDRFREQRESET (1'h0),
+    .RXCDRHOLD (1'h0),
+    .RXCDROVRDEN (1'h0),
+    .RXCDRRESET (1'h0),
+    .RXCDRRESETRSV (1'h0),
     .RXCHARISCOMMA (),
     .RXCHARISK ({rx_charisk_open_s[3:0], rx_charisk}),
-    .RXCHBONDI (5'd0),
+    .RXCHBONDEN (1'h0),
+    .RXCHBONDI (5'h0),
+    .RXCHBONDLEVEL (3'h0),
+    .RXCHBONDMASTER (1'h1),
+    .RXCHBONDSLAVE (1'h0),
+    .RXCOMMADET (),
+    .RXCOMMADETEN (1'h1),
+    .RXDATA ({rx_data_open_s[31:0], rx_data}),
+    .RXDDIEN (1'h0),
+    .RXDFEAGCHOLD (1'h0),
+    .RXDFEAGCOVRDEN (1'h0),
+    .RXDFECM1EN (1'h0),
+    .RXDFELFHOLD (1'h0),
+    .RXDFELFOVRDEN (1'h0),
+    .RXDFELPMRESET (1'h0),
+    .RXDFETAP2HOLD (1'h0),
+    .RXDFETAP2OVRDEN (1'h0),
+    .RXDFETAP3HOLD (1'h0),
+    .RXDFETAP3OVRDEN (1'h0),
+    .RXDFETAP4HOLD (1'h0),
+    .RXDFETAP4OVRDEN (1'h0),
+    .RXDFETAP5HOLD (1'h0),
+    .RXDFETAP5OVRDEN (1'h0),
+    .RXDFEUTHOLD (1'h0),
+    .RXDFEUTOVRDEN (1'h0),
+    .RXDFEVPHOLD (1'h0),
+    .RXDFEVPOVRDEN (1'h0),
+    .RXDFEVSEN (1'h0),
+    .RXDFEXYDEN (1'h1),
+    .RXDFEXYDHOLD (1'h0),
+    .RXDFEXYDOVRDEN (1'h0),
+    .RXDISPERR ({rx_disperr_open_s[3:0], rx_disperr}),
+    .RXDLYBYPASS (1'h1),
+    .RXDLYEN (1'h0),
+    .RXDLYOVRDEN (1'h0),
+    .RXDLYSRESET (1'h0),
+    .RXELECIDLEMODE (2'h3),
+    .RXGEARBOXSLIP (1'h0),
+    .RXLPMEN (up_rx_lpm_dfe_n),
+    .RXLPMHFHOLD (1'h0),
+    .RXLPMHFOVRDEN (1'h0),
+    .RXLPMLFHOLD (1'h0),
+    .RXLPMLFKLOVRDEN (1'h0),
+    .RXMCOMMAALIGNEN (rx_calign),
+    .RXMONITOROUT (),
+    .RXMONITORSEL (2'h0),
+    .RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
+    .RXOOBRESET (1'h0),
+    .RXOSHOLD (1'h0),
+    .RXOSOVRDEN (1'h0),
+    .RXOUTCLK (rx_out_clk_s),
+    .RXOUTCLKFABRIC (),
+    .RXOUTCLKSEL (up_rx_out_clk_sel),
+    .RXPCOMMAALIGNEN (rx_calign),
+    .RXPCSRESET (1'h0),
+    .RXPD (2'h0),
+    .RXPHALIGN (1'h0),
+    .RXPHALIGNEN (1'h0),
+    .RXPHDLYPD (1'h0),
+    .RXPHDLYRESET (1'h0),
+    .RXPHOVRDEN (1'h0),
+    .RXPMARESET (1'h0),
+    .RXPOLARITY (1'h0),
+    .RXPRBSCNTRESET (1'h0),
+    .RXPRBSERR (),
+    .RXPRBSSEL (3'h0),
+    .RXQPIEN (1'h0),
+    .RXRATE (rx_rate_m2),
     .RXRESETDONE (rx_rst_done_s),
-    .RXQPIEN (1'd0),
-    .RXQPISENN (),
-    .RXQPISENP (),
-    .TXPHDLYTSTCLK (1'd0),
-    .TXPOSTCURSOR (5'd0),
-    .TXPOSTCURSORINV (1'd0),
-    .TXPRECURSOR (5'd0),
-    .TXPRECURSORINV (1'd0),
-    .TXQPIBIASEN (1'd0),
-    .TXQPISTRONGPDOWN (1'd0),
-    .TXQPIWEAKPUP (1'd0),
-    .CFGRESET (1'd0),
-    .GTTXRESET (up_tx_rst),
-    .PCSRSVDOUT (),
-    .TXUSERRDY (up_tx_user_ready),
-    .GTRESETSEL (1'd0),
-    .RESETOVRD (1'd0),
-    .TXCHARDISPMODE (8'd0),
-    .TXCHARDISPVAL (8'd0),
-    .TXUSRCLK (tx_clk),
-    .TXUSRCLK2 (tx_clk),
-    .TXELECIDLE (1'd0),
-    .TXMARGIN (3'd0),
-    .TXRATE (tx_rate_m2),
-    .TXSWING (1'd0),
-    .TXPRBSFORCEERR (1'd0),
-    .TXDLYBYPASS (1'd1),
-    .TXDLYEN (1'd0),
-    .TXDLYHOLD (1'd0),
-    .TXDLYOVRDEN (1'd0),
-    .TXDLYSRESET (1'd0),
-    .TXDLYSRESETDONE (),
-    .TXDLYUPDOWN (1'd0),
-    .TXPHALIGN (1'd0),
-    .TXPHALIGNDONE (),
-    .TXPHALIGNEN (1'd0),
-    .TXPHDLYPD (1'd0),
-    .TXPHDLYRESET (1'd0),
-    .TXPHINIT (1'd0),
-    .TXPHINITDONE (),
-    .TXPHOVRDEN (1'd0),
+    .RXSLIDE (1'h0),
+    .RXSTATUS (),
+    .RXSYSCLKSEL (rx_sys_clk_sel_s),
+    .RXUSERRDY (up_rx_user_ready),
+    .RXUSRCLK (rx_clk),
+    .RXUSRCLK2 (rx_clk),
+    .SETERRSTATUS (1'h0),
+    .TSTIN (20'hfffff),
+    .TX8B10BBYPASS (8'h0),
+    .TX8B10BEN (1'h1),
+    .TXBUFDIFFCTRL (3'h4),
     .TXBUFSTATUS (),
-    .TXBUFDIFFCTRL (3'b100),
-    .TXDEEMPH (1'd0),
-    .TXDIFFCTRL (4'b1000),
-    .TXDIFFPD (1'd0),
-    .TXINHIBIT (1'd0),
-    .TXMAINCURSOR (7'b0000000),
-    .TXPISOPD (1'd0),
+    .TXCHARDISPMODE (8'h0),
+    .TXCHARDISPVAL (8'h0),
+    .TXCHARISK ({4'd0, tx_charisk}),
+    .TXCOMINIT (1'h0),
+    .TXCOMSAS (1'h0),
+    .TXCOMWAKE (1'h0),
     .TXDATA ({32'd0, tx_data}),
-    .GTXTXP (tx_p),
-    .GTXTXN (tx_n),
+    .TXDEEMPH (1'h0),
+    .TXDETECTRX (1'h0),
+    .TXDIFFCTRL (4'h8),
+    .TXDIFFPD (1'h0),
+    .TXDLYBYPASS (1'h1),
+    .TXDLYEN (1'h0),
+    .TXDLYHOLD (1'h0),
+    .TXDLYOVRDEN (1'h0),
+    .TXDLYSRESET (1'h0),
+    .TXDLYUPDOWN (1'h0),
+    .TXELECIDLE (1'h0),
+    .TXHEADER (3'h0),
+    .TXINHIBIT (1'h0),
+    .TXMAINCURSOR (7'h0),
+    .TXMARGIN (3'h0),
     .TXOUTCLK (tx_out_clk_s),
     .TXOUTCLKFABRIC (),
     .TXOUTCLKPCS (),
     .TXOUTCLKSEL (up_tx_out_clk_sel),
-    .TXRATEDONE (),
-    .TXCHARISK ({4'd0, tx_charisk}),
-    .TXGEARBOXREADY (),
-    .TXHEADER (3'd0),
-    .TXSEQUENCE (7'd0),
-    .TXSTARTSEQ (1'd0),
-    .TXPCSRESET (1'd0),
-    .TXPMARESET (1'd0),
-    .TXRESETDONE (tx_rst_done_s),
-    .TXCOMFINISH (),
-    .TXCOMINIT (1'd0),
-    .TXCOMSAS (1'd0),
-    .TXCOMWAKE (1'd0),
-    .TXPDELECIDLEMODE (1'd0),
-    .TXPOLARITY (1'd0),
-    .TXDETECTRX (1'd0),
-    .TX8B10BBYPASS (8'd0),
+    .TXPCSRESET (1'h0),
+    .TXPD (2'h0),
+    .TXPDELECIDLEMODE (1'h0),
+    .TXPHALIGN (1'h0),
+    .TXPHALIGNEN (1'h0),
+    .TXPHDLYPD (1'h0),
+    .TXPHDLYRESET (1'h0),
+    .TXPHDLYTSTCLK (1'h0),
+    .TXPHINIT (1'h0),
+    .TXPHOVRDEN (1'h0),
+    .TXPISOPD (1'h0),
+    .TXPMARESET (1'h0),
+    .TXPOLARITY (1'h0),
+    .TXPOSTCURSOR (5'h0),
+    .TXPOSTCURSORINV (1'h0),
+    .TXPRBSFORCEERR (1'h0),
     .TXPRBSSEL (3'd0),
-    .TXQPISENP (),
-    .TXQPISENN ());
+    .TXPRECURSOR (5'h0),
+    .TXPRECURSORINV (1'h0),
+    .TXQPIBIASEN (1'h0),
+    .TXQPISTRONGPDOWN (1'h0),
+    .TXQPIWEAKPUP (1'h0),
+    .TXRATE (tx_rate_m2),
+    .TXRESETDONE (tx_rst_done_s),
+    .TXSEQUENCE (7'h0),
+    .TXSTARTSEQ (1'h0),
+    .TXSWING (1'h0),
+    .TXSYSCLKSEL (tx_sys_clk_sel_s),
+    .TXUSERRDY (up_tx_user_ready),
+    .TXUSRCLK (tx_clk),
+    .TXUSRCLK2 (tx_clk));
   end
   endgenerate
 
@@ -787,7 +764,7 @@ module util_adxcvr_xch #(
     .ADAPT_CFG1 (16'b0000000000000000),
     .ALIGN_COMMA_DOUBLE ("FALSE"),
     .ALIGN_COMMA_ENABLE (10'b1111111111),
-    .ALIGN_COMMA_WORD (1),
+    .ALIGN_COMMA_WORD (1'h1),
     .ALIGN_MCOMMA_DET ("TRUE"),
     .ALIGN_MCOMMA_VALUE (10'b1010000011),
     .ALIGN_PCOMMA_DET ("TRUE"),
@@ -798,7 +775,7 @@ module util_adxcvr_xch #(
     .CBCC_DATA_SOURCE_SEL ("DECODED"),
     .CDR_SWAP_MODE_EN (1'b0),
     .CHAN_BOND_KEEP_ALIGN ("FALSE"),
-    .CHAN_BOND_MAX_SKEW (1),
+    .CHAN_BOND_MAX_SKEW (1'h1),
     .CHAN_BOND_SEQ_1_1 (10'b0000000000),
     .CHAN_BOND_SEQ_1_2 (10'b0000000000),
     .CHAN_BOND_SEQ_1_3 (10'b0000000000),
@@ -810,13 +787,13 @@ module util_adxcvr_xch #(
     .CHAN_BOND_SEQ_2_4 (10'b0000000000),
     .CHAN_BOND_SEQ_2_ENABLE (4'b1111),
     .CHAN_BOND_SEQ_2_USE ("FALSE"),
-    .CHAN_BOND_SEQ_LEN (1),
+    .CHAN_BOND_SEQ_LEN (1'h1),
     .CLK_CORRECT_USE ("FALSE"),
     .CLK_COR_KEEP_IDLE ("FALSE"),
     .CLK_COR_MAX_LAT (12),
     .CLK_COR_MIN_LAT (8),
     .CLK_COR_PRECEDENCE ("TRUE"),
-    .CLK_COR_REPEAT_WAIT (0),
+    .CLK_COR_REPEAT_WAIT (1'h0),
     .CLK_COR_SEQ_1_1 (10'b0100000000),
     .CLK_COR_SEQ_1_2 (10'b0100000000),
     .CLK_COR_SEQ_1_3 (10'b0100000000),
@@ -828,7 +805,7 @@ module util_adxcvr_xch #(
     .CLK_COR_SEQ_2_4 (10'b0100000000),
     .CLK_COR_SEQ_2_ENABLE (4'b1111),
     .CLK_COR_SEQ_2_USE ("FALSE"),
-    .CLK_COR_SEQ_LEN (1),
+    .CLK_COR_SEQ_LEN (1'h1),
     .CPLL_CFG0 (16'b0110011111111010),
     .CPLL_CFG1 (16'b1010010010010100),
     .CPLL_CFG2 (16'b1111000000000111),
@@ -838,7 +815,7 @@ module util_adxcvr_xch #(
     .CPLL_INIT_CFG0 (16'b0000000000011110),
     .CPLL_INIT_CFG1 (8'b00000000),
     .CPLL_LOCK_CFG (16'b0000000111101000),
-    .CPLL_REFCLK_DIV (1),
+    .CPLL_REFCLK_DIV (1'h1),
     .DDI_CTRL (2'b00),
     .DDI_REALIGN_WAIT (15),
     .DEC_MCOMMA_DETECT ("TRUE"),
@@ -1057,7 +1034,7 @@ module util_adxcvr_xch #(
     .RX_EYESCAN_VS_RANGE (2'b00),
     .RX_EYESCAN_VS_UT_SIGN (1'b0),
     .RX_FABINT_USRCLK_FLOP (1'b0),
-    .RX_INT_DATAWIDTH (1),
+    .RX_INT_DATAWIDTH (1'h1),
     .RX_PMA_POWER_SAVE (1'b0),
     .RX_PROGDIV_CFG (20.0),
     .RX_SAMPLE_PERIOD (3'b101),
@@ -1141,7 +1118,7 @@ module util_adxcvr_xch #(
     .TX_EML_PHI_TUNE (1'b0),
     .TX_FABINT_USRCLK_FLOP (1'b0),
     .TX_IDLE_DATA_ZERO (1'b0),
-    .TX_INT_DATAWIDTH (1),
+    .TX_INT_DATAWIDTH (1'h1),
     .TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
     .TX_MAINCURSOR_SEL (1'b0),
     .TX_MARGIN_FULL_0 (7'b1001111),
@@ -1542,7 +1519,7 @@ module util_adxcvr_xch #(
     .ADAPT_CFG2 (16'h0000),
     .ALIGN_COMMA_DOUBLE ("FALSE"),
     .ALIGN_COMMA_ENABLE (10'b1111111111),
-    .ALIGN_COMMA_WORD (1),
+    .ALIGN_COMMA_WORD (1'h1),
     .ALIGN_MCOMMA_DET ("TRUE"),
     .ALIGN_MCOMMA_VALUE (10'b1010000011),
     .ALIGN_PCOMMA_DET ("TRUE"),
@@ -1557,7 +1534,7 @@ module util_adxcvr_xch #(
     .CDR_SWAP_MODE_EN (1'b0),
     .CFOK_PWRSVE_EN (1'b1),
     .CHAN_BOND_KEEP_ALIGN ("FALSE"),
-    .CHAN_BOND_MAX_SKEW (1),
+    .CHAN_BOND_MAX_SKEW (1'h1),
     .CHAN_BOND_SEQ_1_1 (10'b0000000000),
     .CHAN_BOND_SEQ_1_2 (10'b0000000000),
     .CHAN_BOND_SEQ_1_3 (10'b0000000000),
@@ -1569,7 +1546,7 @@ module util_adxcvr_xch #(
     .CHAN_BOND_SEQ_2_4 (10'b0000000000),
     .CHAN_BOND_SEQ_2_ENABLE (4'b1111),
     .CHAN_BOND_SEQ_2_USE ("FALSE"),
-    .CHAN_BOND_SEQ_LEN (1),
+    .CHAN_BOND_SEQ_LEN (1'h1),
     .CH_HSPMUX (16'h2424),
     .CKCAL1_CFG_0 (16'b1100000011000000),
     .CKCAL1_CFG_1 (16'b0101000011000000),
@@ -1587,7 +1564,7 @@ module util_adxcvr_xch #(
     .CLK_COR_MAX_LAT (12),
     .CLK_COR_MIN_LAT (8),
     .CLK_COR_PRECEDENCE ("TRUE"),
-    .CLK_COR_REPEAT_WAIT (0),
+    .CLK_COR_REPEAT_WAIT (1'h0),
     .CLK_COR_SEQ_1_1 (10'b0100000000),
     .CLK_COR_SEQ_1_2 (10'b0100000000),
     .CLK_COR_SEQ_1_3 (10'b0100000000),
@@ -1599,7 +1576,7 @@ module util_adxcvr_xch #(
     .CLK_COR_SEQ_2_4 (10'b0100000000),
     .CLK_COR_SEQ_2_ENABLE (4'b1111),
     .CLK_COR_SEQ_2_USE ("FALSE"),
-    .CLK_COR_SEQ_LEN (1),
+    .CLK_COR_SEQ_LEN (1'h1),
     .CPLL_CFG0 (16'h01fa),
     .CPLL_CFG1 (16'h0023),
     .CPLL_CFG2 (16'h0002),
@@ -1608,7 +1585,7 @@ module util_adxcvr_xch #(
     .CPLL_FBDIV_45 (5),
     .CPLL_INIT_CFG0 (16'h02b2),
     .CPLL_LOCK_CFG (16'h01e8),
-    .CPLL_REFCLK_DIV (1),
+    .CPLL_REFCLK_DIV (1'h1),
     .CTLE3_OCAP_EXT_CTRL (3'b000),
     .CTLE3_OCAP_EXT_EN (1'b0),
     .DDI_CTRL (2'b00),
@@ -1698,7 +1675,7 @@ module util_adxcvr_xch #(
     .PD_TRANS_TIME_FROM_P2 (12'h03c),
     .PD_TRANS_TIME_NONE_P2 (8'h19),
     .PD_TRANS_TIME_TO_P2 (8'h64),
-    .PREIQ_FREQ_BST (0),
+    .PREIQ_FREQ_BST (1'h0),
     .PROCESS_PAR (3'b010),
     .RATE_SW_USE_DRP (1'b1),
     .RCLK_SIPO_DLY_ENB (1'b0),
@@ -1861,7 +1838,7 @@ module util_adxcvr_xch #(
     .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
     .RX_DFE_AGC_CFG0 (2'b10),
     .RX_DFE_AGC_CFG1 (4),
-    .RX_DFE_KL_LPM_KH_CFG0 (1),
+    .RX_DFE_KL_LPM_KH_CFG0 (1'h1),
     .RX_DFE_KL_LPM_KH_CFG1 (4),
     .RX_DFE_KL_LPM_KL_CFG0 (2'b01),
     .RX_DFE_KL_LPM_KL_CFG1 (4),
@@ -1877,7 +1854,7 @@ module util_adxcvr_xch #(
     .RX_EYESCAN_VS_RANGE (2'b00),
     .RX_EYESCAN_VS_UT_SIGN (1'b0),
     .RX_FABINT_USRCLK_FLOP (1'b0),
-    .RX_INT_DATAWIDTH (1),
+    .RX_INT_DATAWIDTH (1'h1),
     .RX_PMA_POWER_SAVE (1'b0),
     .RX_PMA_RSV0 (16'h0000),
     .RX_PROGDIV_CFG (0.000000),
@@ -1911,7 +1888,7 @@ module util_adxcvr_xch #(
     .SIM_RECEIVER_DETECT_PASS ("TRUE"),
     .SIM_RESET_SPEEDUP ("TRUE"),
     .SIM_TX_EIDLE_DRIVE_LEVEL ("Z"),
-    .SIM_VERSION (1),
+    .SIM_VERSION (1'h1),
     .SRSTMODE (1'b0),
     .TAPDLY_SET_TX (2'h0),
     .TEMPERATURE_PAR (4'b0010),
@@ -1971,7 +1948,7 @@ module util_adxcvr_xch #(
     .TX_FABINT_USRCLK_FLOP (1'b0),
     .TX_FIFO_BYP_EN (1'b0),
     .TX_IDLE_DATA_ZERO (1'b0),
-    .TX_INT_DATAWIDTH (1),
+    .TX_INT_DATAWIDTH (1'h1),
     .TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
     .TX_MAINCURSOR_SEL (1'b0),
     .TX_MARGIN_FULL_0 (7'b1011111),
@@ -1987,7 +1964,7 @@ module util_adxcvr_xch #(
     .TX_PHICAL_CFG0 (16'h0000),
     .TX_PHICAL_CFG1 (16'h7e00),
     .TX_PHICAL_CFG2 (16'h0201),
-    .TX_PI_BIASSET (1),
+    .TX_PI_BIASSET (1'h1),
     .TX_PI_IBIAS_MID (2'b00),
     .TX_PMADATA_OPT (1'b0),
     .TX_PMA_POWER_SAVE (1'b0),
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
index fa94f3cdf..6c65ec311 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
@@ -43,9 +43,9 @@ module util_adxcvr_xcm #(
 
   parameter   integer XCVR_ID = 0,
   parameter   integer XCVR_TYPE = 0,
-  parameter   integer QPLL_REFCLK_DIV = 2,
+  parameter   integer QPLL_REFCLK_DIV = 1,
   parameter   integer QPLL_FBDIV_RATIO = 1,
-  parameter   [26:0]  QPLL_CFG = 27'h06801C1,
+  parameter   [26:0]  QPLL_CFG = 27'h0680181,
   parameter   [ 9:0]  QPLL_FBDIV =  10'b0000110000) (
 
   // reset and clocks
@@ -119,11 +119,11 @@ module util_adxcvr_xcm #(
   generate
   if (XCVR_TYPE == 0) begin
   GTXE2_COMMON #(
-    .SIM_RESET_SPEEDUP ("TRUE"),
-    .SIM_QPLLREFCLK_SEL (3'b001),
-    .SIM_VERSION ("3.0"),
     .BIAS_CFG (64'h0000040000001000),
     .COMMON_CFG (32'h00000000),
+    .IS_DRPCLK_INVERTED (1'b0),
+    .IS_GTGREFCLK_INVERTED (1'b0),
+    .IS_QPLLLOCKDETCLK_INVERTED (1'b0),
     .QPLL_CFG (QPLL_CFG),
     .QPLL_CLKOUT_CFG (4'b0000),
     .QPLL_COARSE_FREQ_OVRD (6'b010000),
@@ -137,43 +137,43 @@ module util_adxcvr_xcm #(
     .QPLL_INIT_CFG (24'h000006),
     .QPLL_LOCK_CFG (16'h21E8),
     .QPLL_LPF (4'b1111),
-    .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
+    .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
+    .SIM_QPLLREFCLK_SEL (3'b001),
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_VERSION ("4.0"))
   i_gtxe2_common (
-    .DRPCLK (up_clk),
-    .DRPEN (up_enb_int),
+    .BGBYPASSB (1'h1),
+    .BGMONITORENB (1'h1),
+    .BGPDB (1'h1),
+    .BGRCALOVRD (5'h1f),
     .DRPADDR (up_addr_int[7:0]),
-    .DRPWE (up_wr_int),
+    .DRPCLK (up_clk),
     .DRPDI (up_wdata_int),
     .DRPDO (up_rdata_s),
+    .DRPEN (up_enb_int),
     .DRPRDY (up_ready_s),
-    .GTGREFCLK (1'd0),
-    .GTNORTHREFCLK0 (1'd0),
-    .GTNORTHREFCLK1 (1'd0),
+    .DRPWE (up_wr_int),
+    .GTGREFCLK (1'h0),
+    .GTNORTHREFCLK0 (1'h0),
+    .GTNORTHREFCLK1 (1'h0),
     .GTREFCLK0 (qpll_ref_clk),
-    .GTREFCLK1 (1'd0),
-    .GTSOUTHREFCLK0 (1'd0),
-    .GTSOUTHREFCLK1 (1'd0),
-    .QPLLDMONITOR (),
-    .QPLLOUTCLK (qpll2ch_clk),
-    .QPLLOUTREFCLK (qpll2ch_ref_clk),
-    .REFCLKOUTMONITOR (),
-    .QPLLFBCLKLOST (),
+    .GTREFCLK1 (1'h0),
+    .GTSOUTHREFCLK0 (1'h0),
+    .GTSOUTHREFCLK1 (1'h0),
+    .PMARSVD (8'h0),
     .QPLLLOCK (qpll2ch_locked),
     .QPLLLOCKDETCLK (up_clk),
-    .QPLLLOCKEN (1'd1),
-    .QPLLOUTRESET (1'd0),
-    .QPLLPD (1'd0),
+    .QPLLLOCKEN (1'h1),
+    .QPLLOUTCLK (qpll2ch_clk),
+    .QPLLOUTREFCLK (qpll2ch_ref_clk),
+    .QPLLOUTRESET (1'h0),
+    .QPLLPD (1'h0),
     .QPLLREFCLKLOST (),
-    .QPLLREFCLKSEL (3'b001),
+    .QPLLREFCLKSEL (3'h1),
     .QPLLRESET (up_qpll_rst),
-    .QPLLRSVD1 (16'b0000000000000000),
-    .QPLLRSVD2 (5'b11111),
-    .BGBYPASSB (1'd1),
-    .BGMONITORENB (1'd1),
-    .BGPDB (1'd1),
-    .BGRCALOVRD (5'b00000),
-    .PMARSVD (8'b00000000),
-    .RCALENB (1'd1));
+    .QPLLRSVD1 (16'h0),
+    .QPLLRSVD2 (5'h1f),
+    .RCALENB (1'h1));
   end
   endgenerate
 
@@ -406,7 +406,7 @@ module util_adxcvr_xcm #(
     .SDM1INITSEED0_1 (9'b000010001),
     .SIM_MODE ("FAST"),
     .SIM_RESET_SPEEDUP ("TRUE"),
-    .SIM_VERSION (1)) 
+    .SIM_VERSION (1'h1)) 
   i_gthe4_common (
     .BGBYPASSB (1'd1),
     .BGMONITORENB (1'd1),

From bf949f1a883fe583cf99f3e14509937a1b7a0d7a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 17 Oct 2016 16:16:49 -0400
Subject: [PATCH 612/972] axi_xcvrlb- xcvr updates

---
 library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
index 3ddfbc829..9cd02f4a8 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
@@ -244,14 +244,15 @@ module axi_xcvrlb_1 (
 
   util_adxcvr_xch #(
     .XCVR_ID (0),
-    .GTH_OR_GTX_N (0),
-    .CPLL_TX_OR_RX_N (0),
+    .XCVR_TYPE (0),
     .CPLL_FBDIV (2),
-    .RX_OUT_DIV (1),
-    .RX_CLK25_DIV (10),
+    .CPLL_FBDIV_4_5 (5),
+    .CPLL_TX_OR_RX_N (0),
     .TX_OUT_DIV (1),
     .TX_CLK25_DIV (10),
-    .PMA_RSV ('h00018480),
+    .RX_OUT_DIV (1),
+    .RX_CLK25_DIV (10),
+    .RX_PMA_CFG ('h00018480),
     .RX_CDR_CFG ('h03000023ff20400020))
   i_xch (
     .qpll2ch_clk (1'b0),

From 950acaed1500edc8582b8e52b3acda515b6bb9ce Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 17 Oct 2016 14:09:14 -0400
Subject: [PATCH 613/972] ccbox- copy

---
 projects/pzsdr1/ccbox_lvds/Makefile           |  82 +++++
 projects/pzsdr1/ccbox_lvds/system_bd.tcl      |   4 +
 projects/pzsdr1/ccbox_lvds/system_constr.xdc  |  97 ++++++
 projects/pzsdr1/ccbox_lvds/system_project.tcl |  17 ++
 projects/pzsdr1/ccbox_lvds/system_top.v       | 287 ++++++++++++++++++
 projects/pzsdr1/common/ccbox_bd.tcl           |  29 ++
 6 files changed, 516 insertions(+)
 create mode 100644 projects/pzsdr1/ccbox_lvds/Makefile
 create mode 100644 projects/pzsdr1/ccbox_lvds/system_bd.tcl
 create mode 100644 projects/pzsdr1/ccbox_lvds/system_constr.xdc
 create mode 100644 projects/pzsdr1/ccbox_lvds/system_project.tcl
 create mode 100644 projects/pzsdr1/ccbox_lvds/system_top.v
 create mode 100644 projects/pzsdr1/common/ccbox_bd.tcl

diff --git a/projects/pzsdr1/ccbox_lvds/Makefile b/projects/pzsdr1/ccbox_lvds/Makefile
new file mode 100644
index 000000000..20dd931d1
--- /dev/null
+++ b/projects/pzsdr1/ccbox_lvds/Makefile
@@ -0,0 +1,82 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
+M_DEPS += ../../common/xilinx/sys_wfifo.tcl
+M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
+M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
+M_DEPS += ../../common/pzsdr1/pzsdr1_lvds_system_constr.xdc
+M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib ccbrk_pzsdr1.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+ccbrk_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr1_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_gpreg
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/pzsdr1/ccbox_lvds/system_bd.tcl b/projects/pzsdr1/ccbox_lvds/system_bd.tcl
new file mode 100644
index 000000000..aa8108693
--- /dev/null
+++ b/projects/pzsdr1/ccbox_lvds/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_bd.tcl
+source ../common/ccbrk_bd.tcl
+
diff --git a/projects/pzsdr1/ccbox_lvds/system_constr.xdc b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
new file mode 100644
index 000000000..e54ad79c8
--- /dev/null
+++ b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
@@ -0,0 +1,97 @@
+
+## constraints
+## loopback
+## p6
+
+set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[0]]        ; ## JX4.20  IO_L2P_T0_34                  
+set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[0]]         ; ## JX4.19  IO_L1P_T0_34                  
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[1]]        ; ## JX4.22  IO_L2N_T0_34                  
+set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[1]]         ; ## JX4.21  IO_L1N_T0_34                  
+set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[2]]        ; ## JX4.26  IO_L4P_T0_34                  
+set_property  -dict {PACKAGE_PIN  U13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[2]]         ; ## JX4.25  IO_L3P_T0_DQS_PUDC_B_34       
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_out[3]]        ; ## JX4.28  IO_L4N_T0_34                  
+set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[3]]         ; ## JX4.27  IO_L3N_T0_DQS_34              
+set_property  -dict {PACKAGE_PIN  P14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[4]]        ; ## JX4.32  IO_L6P_T0_34                  
+set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD  LVCMOS25} [get_ports  gp_in[4]]         ; ## JX4.31  IO_L5P_T0_34                  
+set_property  -dict {PACKAGE_PIN  R14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[5]]        ; ## JX4.34  IO_L6N_T0_VREF_34             
+set_property  -dict {PACKAGE_PIN  T15   IOSTANDARD  LVCMOS25} [get_ports  gp_in[5]]         ; ## JX4.33  IO_L5N_T0_34                  
+set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[6]]        ; ## JX4.36  IO_L8P_T1_34                  
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD  LVCMOS25} [get_ports  gp_in[6]]         ; ## JX4.35  IO_L7P_T1_34                  
+set_property  -dict {PACKAGE_PIN  U18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[7]]        ; ## JX4.46  IO_L12P_T1_MRCC_34            
+set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD  LVCMOS25} [get_ports  gp_in[7]]         ; ## JX4.45  IO_L11P_T1_SRCC_34            
+set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD  LVCMOS25} [get_ports  gp_out[8]]        ; ## JX4.48  IO_L12N_T1_MRCC_34            
+set_property  -dict {PACKAGE_PIN  U15   IOSTANDARD  LVCMOS25} [get_ports  gp_in[8]]         ; ## JX4.47  IO_L11N_T1_SRCC_34            
+
+## p7
+
+set_property  -dict {PACKAGE_PIN  N20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[9]]        ; ## JX4.52  IO_L14P_T2_SRCC_34            
+set_property  -dict {PACKAGE_PIN  N18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[9]]         ; ## JX4.51  IO_L13P_T2_MRCC_34            
+set_property  -dict {PACKAGE_PIN  P20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[10]]       ; ## JX4.54  IO_L14N_T2_SRCC_34            
+set_property  -dict {PACKAGE_PIN  P19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[10]]        ; ## JX4.53  IO_L13N_T2_MRCC_34            
+set_property  -dict {PACKAGE_PIN  V20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[11]]       ; ## JX4.58  IO_L16P_T2_34                 
+set_property  -dict {PACKAGE_PIN  T20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[11]]        ; ## JX4.57  IO_L15P_T2_DQS_34             
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[12]]       ; ## JX4.60  IO_L16N_T2_34                 
+set_property  -dict {PACKAGE_PIN  U20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[12]]        ; ## JX4.59  IO_L15N_T2_DQS_34             
+set_property  -dict {PACKAGE_PIN  T17   IOSTANDARD  LVCMOS25} [get_ports  gp_out[13]]       ; ## JX4.74  IO_L20P_T3_34                 
+set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD  LVCMOS25} [get_ports  gp_in[13]]        ; ## JX4.73  IO_L19P_T3_34                 
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[14]]       ; ## JX4.76  IO_L20N_T3_34                 
+set_property  -dict {PACKAGE_PIN  R17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[14]]        ; ## JX4.75  IO_L19N_T3_VREF_34            
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[15]]       ; ## JX4.78  IO_L22P_T3_34                 
+set_property  -dict {PACKAGE_PIN  V17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[15]]        ; ## JX4.77  IO_L21P_T3_DQS_34             
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_out[16]]       ; ## JX4.80  IO_L22N_T3_34                 
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[16]]        ; ## JX4.79  IO_L21N_T3_DQS_34             
+
+## p2
+
+set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[17]]       ; ## JX2.36  IO_L12P_T1_MRCC_13            
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[17]]        ; ## JX2.35  IO_L11P_T1_SRCC_13            
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  gp_out[18]]       ; ## JX2.38  IO_L12N_T1_MRCC_13            
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[18]]        ; ## JX2.37  IO_L11N_T1_SRCC_13            
+set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[19]]       ; ## JX2.42  IO_L14P_T2_SRCC_13            
+set_property  -dict {PACKAGE_PIN  Y7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[19]]        ; ## JX2.41  IO_L13P_T2_MRCC_13            
+set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD  LVCMOS25} [get_ports  gp_out[20]]       ; ## JX2.44  IO_L14N_T2_SRCC_13            
+set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD  LVCMOS25} [get_ports  gp_in[20]]        ; ## JX2.43  IO_L13N_T2_MRCC_13            
+set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  gp_out[21]]       ; ## JX2.48  IO_L16P_T2_13                 
+set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[21]]        ; ## JX2.47  IO_L15P_T2_DQS_13             
+set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[22]]       ; ## JX2.50  IO_L16N_T2_13                 
+set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[22]]        ; ## JX2.49  IO_L15N_T2_DQS_13             
+set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD  LVCMOS25} [get_ports  gp_out[23]]       ; ## JX2.54  IO_L18P_T2_13                 
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  gp_in[23]]        ; ## JX2.53  IO_L17P_T2_13                 
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_out[24]]       ; ## JX2.56  IO_L18N_T2_13                 
+set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[24]]        ; ## JX2.55  IO_L17N_T2_13                 
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[25]]       ; ## JX2.62  IO_L20P_T3_13                 
+set_property  -dict {PACKAGE_PIN  T5    IOSTANDARD  LVCMOS25} [get_ports  gp_in[25]]        ; ## JX2.61  IO_L19P_T3_13                 
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_out[26]]       ; ## JX2.64  IO_L20N_T3_13                 
+set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD  LVCMOS25} [get_ports  gp_in[26]]        ; ## JX2.63  IO_L19N_T3_VREF_13            
+
+## vcc
+
+set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[0]]    ; ## JX2.18  IO_L6N_T0_VREF_13 
+set_property  -dict {PACKAGE_PIN  V16   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[1]]    ; ## JX4.68  IO_L18P_T2_34                 
+set_property  -dict {PACKAGE_PIN  W16   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[2]]    ; ## JX4.70  IO_L18N_T2_34                 
+set_property  -dict {PACKAGE_PIN  V11   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[3]]    ; ## JX2.67  IO_L21P_T3_DQS_13             
+set_property  -dict {PACKAGE_PIN  V10   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[4]]    ; ## JX2.69  IO_L21N_T3_DQS_13             
+
+## MIO loopbacks (fixed-io)
+## the following are connected to AD9361 GPIO
+
+##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
+##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
+##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
+##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
+
+## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
+
+##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
+
+## the following are mio-to-pl loopback
+
+##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
+##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
+##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
+
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[0]]     ; ## JX4.67  IO_L17P_T2_34                 
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[1]]     ; ## JX4.37  IO_L7N_T1_34                  
+set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[2]]     ; ## JX4.42  IO_L10P_T1_34                 
+
+
diff --git a/projects/pzsdr1/ccbox_lvds/system_project.tcl b/projects/pzsdr1/ccbox_lvds/system_project.tcl
new file mode 100644
index 000000000..21967b370
--- /dev/null
+++ b/projects/pzsdr1/ccbox_lvds/system_project.tcl
@@ -0,0 +1,17 @@
+
+source ../../scripts/adi_env.tcl 
+source $ad_hdl_dir/projects/scripts/adi_project.tcl 
+source $ad_hdl_dir/projects/scripts/adi_board.tcl 
+
+adi_project_create ccbrk_pzsdr1
+adi_project_files ccbrk_pzsdr1 [list \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
+
+set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
+adi_project_run ccbrk_pzsdr1
+
+
diff --git a/projects/pzsdr1/ccbox_lvds/system_top.v b/projects/pzsdr1/ccbox_lvds/system_top.v
new file mode 100644
index 000000000..643b39163
--- /dev/null
+++ b/projects/pzsdr1/ccbox_lvds/system_top.v
@@ -0,0 +1,287 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  ddr_addr,
+  ddr_ba,
+  ddr_cas_n,
+  ddr_ck_n,
+  ddr_ck_p,
+  ddr_cke,
+  ddr_cs_n,
+  ddr_dm,
+  ddr_dq,
+  ddr_dqs_n,
+  ddr_dqs_p,
+  ddr_odt,
+  ddr_ras_n,
+  ddr_reset_n,
+  ddr_we_n,
+
+  fixed_io_ddr_vrn,
+  fixed_io_ddr_vrp,
+  fixed_io_mio,
+  fixed_io_ps_clk,
+  fixed_io_ps_porb,
+  fixed_io_ps_srstb,
+
+  iic_scl,
+  iic_sda,
+
+  gpio_bd,
+
+  rx_clk_in_p,
+  rx_clk_in_n,
+  rx_frame_in_p,
+  rx_frame_in_n,
+  rx_data_in_p,
+  rx_data_in_n,
+  tx_clk_out_p,
+  tx_clk_out_n,
+  tx_frame_out_p,
+  tx_frame_out_n,
+  tx_data_out_p,
+  tx_data_out_n,
+
+  enable,
+  txnrx,
+  clk_out,
+
+  gpio_clksel,
+  gpio_resetb,
+  gpio_sync,
+  gpio_en_agc,
+  gpio_ctl,
+  gpio_status,
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  gp_out,
+  gp_in,
+  gp_in_mio,
+  gp_in_open);
+
+
+  inout   [14:0]  ddr_addr;
+  inout   [ 2:0]  ddr_ba;
+  inout           ddr_cas_n;
+  inout           ddr_ck_n;
+  inout           ddr_ck_p;
+  inout           ddr_cke;
+  inout           ddr_cs_n;
+  inout   [ 3:0]  ddr_dm;
+  inout   [31:0]  ddr_dq;
+  inout   [ 3:0]  ddr_dqs_n;
+  inout   [ 3:0]  ddr_dqs_p;
+  inout           ddr_odt;
+  inout           ddr_ras_n;
+  inout           ddr_reset_n;
+  inout           ddr_we_n;
+
+  inout           fixed_io_ddr_vrn;
+  inout           fixed_io_ddr_vrp;
+  inout   [53:0]  fixed_io_mio;
+  inout           fixed_io_ps_clk;
+  inout           fixed_io_ps_porb;
+  inout           fixed_io_ps_srstb;
+
+  inout           iic_scl;
+  inout           iic_sda;
+
+  inout   [ 3:0]  gpio_bd;
+
+  input           rx_clk_in_p;
+  input           rx_clk_in_n;
+  input           rx_frame_in_p;
+  input           rx_frame_in_n;
+  input   [ 5:0]  rx_data_in_p;
+  input   [ 5:0]  rx_data_in_n;
+  output          tx_clk_out_p;
+  output          tx_clk_out_n;
+  output          tx_frame_out_p;
+  output          tx_frame_out_n;
+  output  [ 5:0]  tx_data_out_p;
+  output  [ 5:0]  tx_data_out_n;
+
+  output          enable;
+  output          txnrx;
+  input           clk_out;
+
+  inout           gpio_clksel;
+  inout           gpio_resetb;
+  inout           gpio_sync;
+  inout           gpio_en_agc;
+  inout   [ 3:0]  gpio_ctl;
+  inout   [ 7:0]  gpio_status;
+
+  output          spi_csn;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  output  [26:0]  gp_out;
+  input   [26:0]  gp_in;
+  input   [ 2:0]  gp_in_mio;
+  input   [ 4:0]  gp_in_open;
+
+  // internal signals
+
+  wire    [63:0]  gp_out_s;
+  wire    [63:0]  gp_in_s;
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+
+  assign gp_out[26:0] = gp_out_s[26:0];
+  assign gp_in_s[34:30] = gp_in_open;
+  assign gp_in_s[29:27] = gp_in_mio;
+  assign gp_in_s[26: 0] = gp_in;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
+    .dio_t ({gpio_t[51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[51], gpio_i[46:32]}),
+    .dio_p ({ gpio_clksel,        // 51:51
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_bd (
+    .dio_t (gpio_t[3:0]),
+    .dio_i (gpio_o[3:0]),
+    .dio_o (gpio_i[3:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gp_in_0 (gp_in_s[31:0]),
+    .gp_in_1 (gp_in_s[63:32]),
+    .gp_out_0 (gp_out_s[31:0]),
+    .gp_out_1 (gp_out_s[63:32]),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .otg_vbusoc (1'b0),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/pzsdr1/common/ccbox_bd.tcl b/projects/pzsdr1/common/ccbox_bd.tcl
new file mode 100644
index 000000000..204545923
--- /dev/null
+++ b/projects/pzsdr1/common/ccbox_bd.tcl
@@ -0,0 +1,29 @@
+
+# lbfmc
+
+ad_connect  sys_ps7/ENET1_GMII_RX_CLK GND
+ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
+
+# un-used io
+
+set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
+set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg
+
+ad_cpu_interconnect 0x41200000 axi_gpreg
+
+create_bd_port -dir I -from 31 -to 0 gp_in_0
+create_bd_port -dir I -from 31 -to 0 gp_in_1
+create_bd_port -dir O -from 31 -to 0 gp_out_0
+create_bd_port -dir O -from 31 -to 0 gp_out_1
+
+ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
+ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
+ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
+ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
+
+## temporary (remove ila indirectly)
+
+delete_bd_objs [get_bd_cells ila_adc]
+delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
+

From cb97bc500aca1a9ceccf44e863bb42ac09a2d8c4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 17 Oct 2016 15:32:01 -0400
Subject: [PATCH 614/972] hdlmake updates

---
 projects/adrv9371x/a10gx/Makefile             |   4 +-
 projects/adrv9371x/a10soc/Makefile            |   4 +-
 projects/arradio/c5soc/Makefile               |   7 +-
 .../common/pzsdr1/pzsdr1_system_constr.xdc    |   7 -
 projects/daq2/a10gx/Makefile                  |  11 +-
 projects/daq3/a10gx/Makefile                  |  11 +-
 projects/fmcomms2/a10gx/Makefile              |   7 +-
 projects/pzsdr/Makefile                       |   3 +
 projects/pzsdr1/Makefile                      |   3 +
 projects/pzsdr1/ccbox_lvds/Makefile           |  14 +-
 projects/pzsdr1/ccbox_lvds/system_bd.tcl      |   2 +-
 projects/pzsdr1/ccbox_lvds/system_constr.xdc  | 134 ++++-----
 projects/pzsdr1/ccbox_lvds/system_project.tcl |   6 +-
 projects/pzsdr1/ccbox_lvds/system_top.v       | 266 +++++++++---------
 projects/pzsdr1/ccbrk/system_constr.xdc       |   7 +
 projects/pzsdr1/common/ccbox_bd.tcl           |  49 ++--
 16 files changed, 267 insertions(+), 268 deletions(-)

diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile
index 6971a502c..947157310 100644
--- a/projects/adrv9371x/a10gx/Makefile
+++ b/projects/adrv9371x/a10gx/Makefile
@@ -50,12 +50,14 @@ M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
 M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
 M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
@@ -68,8 +70,6 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 74abe24c5..fe52269d0 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -50,12 +50,14 @@ M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
 M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
 M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
@@ -68,8 +70,6 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 165776141..46f14dfd4 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -19,6 +19,8 @@ M_DEPS += ../common/arradio_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys
 M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
+M_DEPS += ../../../altera/axi_ad9361_cmos_if.v
+M_DEPS += ../../../altera/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
 M_DEPS += ../../../library/altera/common/ad_cmos_in.v
 M_DEPS += ../../../library/altera/common/ad_cmos_out.v
@@ -27,10 +29,11 @@ M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
 M_DEPS += ../../../library/altera/common/ad_lvds_in.v
 M_DEPS += ../../../library/altera/common/ad_lvds_out.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera/common/ad_serdes_clk.v
+M_DEPS += ../../../library/altera/common/ad_serdes_in.v
+M_DEPS += ../../../library/altera/common/ad_serdes_out.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
diff --git a/projects/common/pzsdr1/pzsdr1_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
index 7bf9c821c..63540970b 100644
--- a/projects/common/pzsdr1/pzsdr1_system_constr.xdc
+++ b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
@@ -34,10 +34,3 @@ set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS25} [get_ports clk_out]
 set_property  -dict {PACKAGE_PIN  W6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L22N_T3_13              
 set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L22P_T3_13              
 
-# gpio
-
-set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
-set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
-
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index 9b0cc3321..b7184d3c7 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -20,6 +20,12 @@ M_DEPS += ../common/daq2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
+M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
+M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
 M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
@@ -31,7 +37,6 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
-M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
@@ -51,10 +56,12 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
@@ -69,8 +76,6 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index ab104d4c5..1e067a108 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -20,6 +20,12 @@ M_DEPS += ../common/daq3_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
+M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
+M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
 M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
@@ -31,7 +37,6 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
-M_DEPS += ../../../library/axi_adxcvr/axi_adxcvr_hw.tcl
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
@@ -51,10 +56,12 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
@@ -69,8 +76,6 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
-M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 9ce6cb4a7..6011b3a7a 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -19,6 +19,8 @@ M_DEPS += ../common/fmcomms2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../altera/axi_ad9361_cmos_if.v
+M_DEPS += ../../../altera/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
 M_DEPS += ../../../library/altera/common/ad_cmos_in.v
 M_DEPS += ../../../library/altera/common/ad_cmos_out.v
@@ -27,10 +29,11 @@ M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
 M_DEPS += ../../../library/altera/common/ad_lvds_in.v
 M_DEPS += ../../../library/altera/common/ad_lvds_out.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera/common/ad_serdes_clk.v
+M_DEPS += ../../../library/altera/common/ad_serdes_in.v
+M_DEPS += ../../../library/altera/common/ad_serdes_out.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
diff --git a/projects/pzsdr/Makefile b/projects/pzsdr/Makefile
index d1fa90bc2..5643ce37c 100644
--- a/projects/pzsdr/Makefile
+++ b/projects/pzsdr/Makefile
@@ -11,6 +11,7 @@ all:
 	-make -C ccbrk_cmos all
 	-make -C ccfmc all
 	-make -C ccpci all
+	-make -C ccbox_lvds all
 	-make -C ccbrk all
 	-make -C ccbrk_cmos all
 
@@ -20,6 +21,7 @@ clean:
 	make -C ccbrk_cmos clean
 	make -C ccfmc clean
 	make -C ccpci clean
+	make -C ccbox_lvds clean
 	make -C ccbrk clean
 	make -C ccbrk_cmos clean
 
@@ -29,6 +31,7 @@ clean-all:
 	make -C ccbrk_cmos clean-all
 	make -C ccfmc clean-all
 	make -C ccpci clean-all
+	make -C ccbox_lvds clean-all
 	make -C ccbrk clean-all
 	make -C ccbrk_cmos clean-all
 
diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile
index 1f80db157..914b3e1fc 100644
--- a/projects/pzsdr1/Makefile
+++ b/projects/pzsdr1/Makefile
@@ -7,16 +7,19 @@
 
 .PHONY: all clean clean-all 
 all:
+	-make -C ccbox_lvds all
 	-make -C ccbrk all
 	-make -C ccbrk_cmos all
 
 
 clean: 
+	make -C ccbox_lvds clean
 	make -C ccbrk clean
 	make -C ccbrk_cmos clean
 
 
 clean-all:
+	make -C ccbox_lvds clean-all
 	make -C ccbrk clean-all
 	make -C ccbrk_cmos clean-all
 
diff --git a/projects/pzsdr1/ccbox_lvds/Makefile b/projects/pzsdr1/ccbox_lvds/Makefile
index 20dd931d1..8d86c618d 100644
--- a/projects/pzsdr1/ccbox_lvds/Makefile
+++ b/projects/pzsdr1/ccbox_lvds/Makefile
@@ -9,7 +9,7 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
-M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../common/ccbox_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
@@ -22,7 +22,7 @@ M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
@@ -47,7 +47,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_pzsdr1.sdk/system_top.hdf
+all: lib ccbox_lvds_pzsdr1.sdk/system_top.hdf
 
 
 clean: 
@@ -57,22 +57,22 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/axi_i2s_adi clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
+ccbox_lvds_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr1_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ccbox_lvds_pzsdr1_vivado.log 2>&1
 
 
 lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_gpreg
+	make -C ../../../library/axi_i2s_adi
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
diff --git a/projects/pzsdr1/ccbox_lvds/system_bd.tcl b/projects/pzsdr1/ccbox_lvds/system_bd.tcl
index aa8108693..875b6e891 100644
--- a/projects/pzsdr1/ccbox_lvds/system_bd.tcl
+++ b/projects/pzsdr1/ccbox_lvds/system_bd.tcl
@@ -1,4 +1,4 @@
 
 source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_bd.tcl
-source ../common/ccbrk_bd.tcl
+source ../common/ccbox_bd.tcl
 
diff --git a/projects/pzsdr1/ccbox_lvds/system_constr.xdc b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
index e54ad79c8..523ccadae 100644
--- a/projects/pzsdr1/ccbox_lvds/system_constr.xdc
+++ b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
@@ -1,97 +1,71 @@
 
-## constraints
-## loopback
-## p6
+# pzsr1 (rev.b) + ccbox (rev.a)
+# rf-gpio
 
-set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[0]]        ; ## JX4.20  IO_L2P_T0_34                  
-set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[0]]         ; ## JX4.19  IO_L1P_T0_34                  
-set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[1]]        ; ## JX4.22  IO_L2N_T0_34                  
-set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[1]]         ; ## JX4.21  IO_L1N_T0_34                  
-set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[2]]        ; ## JX4.26  IO_L4P_T0_34                  
-set_property  -dict {PACKAGE_PIN  U13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[2]]         ; ## JX4.25  IO_L3P_T0_DQS_PUDC_B_34       
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_out[3]]        ; ## JX4.28  IO_L4N_T0_34                  
-set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[3]]         ; ## JX4.27  IO_L3N_T0_DQS_34              
-set_property  -dict {PACKAGE_PIN  P14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[4]]        ; ## JX4.32  IO_L6P_T0_34                  
-set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD  LVCMOS25} [get_ports  gp_in[4]]         ; ## JX4.31  IO_L5P_T0_34                  
-set_property  -dict {PACKAGE_PIN  R14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[5]]        ; ## JX4.34  IO_L6N_T0_VREF_34             
-set_property  -dict {PACKAGE_PIN  T15   IOSTANDARD  LVCMOS25} [get_ports  gp_in[5]]         ; ## JX4.33  IO_L5N_T0_34                  
-set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[6]]        ; ## JX4.36  IO_L8P_T1_34                  
-set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD  LVCMOS25} [get_ports  gp_in[6]]         ; ## JX4.35  IO_L7P_T1_34                  
-set_property  -dict {PACKAGE_PIN  U18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[7]]        ; ## JX4.46  IO_L12P_T1_MRCC_34            
-set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD  LVCMOS25} [get_ports  gp_in[7]]         ; ## JX4.45  IO_L11P_T1_SRCC_34            
-set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD  LVCMOS25} [get_ports  gp_out[8]]        ; ## JX4.48  IO_L12N_T1_MRCC_34            
-set_property  -dict {PACKAGE_PIN  U15   IOSTANDARD  LVCMOS25} [get_ports  gp_in[8]]         ; ## JX4.47  IO_L11N_T1_SRCC_34            
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[0]]       ; ## JX4.22   IO_L2N_T0_34
+set_property  -dict {PACKAGE_PIN  U13   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[1]]       ; ## JX4.25   IO_L3P_T0_DQS_PUDC_B_34
+set_property  -dict {PACKAGE_PIN  T15   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[2]]       ; ## JX4.33   IO_L5N_T0_34
+set_property  -dict {PACKAGE_PIN  R14   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[3]]       ; ## JX4.34   IO_L6N_T0_VREF_34
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[4]]       ; ## JX4.35   IO_L7P_T1_34
+set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[5]]       ; ## JX4.36   IO_L8P_T1_34
 
-## p7
+# push-button
 
-set_property  -dict {PACKAGE_PIN  N20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[9]]        ; ## JX4.52  IO_L14P_T2_SRCC_34            
-set_property  -dict {PACKAGE_PIN  N18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[9]]         ; ## JX4.51  IO_L13P_T2_MRCC_34            
-set_property  -dict {PACKAGE_PIN  P20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[10]]       ; ## JX4.54  IO_L14N_T2_SRCC_34            
-set_property  -dict {PACKAGE_PIN  P19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[10]]        ; ## JX4.53  IO_L13N_T2_MRCC_34            
-set_property  -dict {PACKAGE_PIN  V20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[11]]       ; ## JX4.58  IO_L16P_T2_34                 
-set_property  -dict {PACKAGE_PIN  T20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[11]]        ; ## JX4.57  IO_L15P_T2_DQS_34             
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[12]]       ; ## JX4.60  IO_L16N_T2_34                 
-set_property  -dict {PACKAGE_PIN  U20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[12]]        ; ## JX4.59  IO_L15N_T2_DQS_34             
-set_property  -dict {PACKAGE_PIN  T17   IOSTANDARD  LVCMOS25} [get_ports  gp_out[13]]       ; ## JX4.74  IO_L20P_T3_34                 
-set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD  LVCMOS25} [get_ports  gp_in[13]]        ; ## JX4.73  IO_L19P_T3_34                 
-set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[14]]       ; ## JX4.76  IO_L20N_T3_34                 
-set_property  -dict {PACKAGE_PIN  R17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[14]]        ; ## JX4.75  IO_L19N_T3_VREF_34            
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[15]]       ; ## JX4.78  IO_L22P_T3_34                 
-set_property  -dict {PACKAGE_PIN  V17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[15]]        ; ## JX4.77  IO_L21P_T3_DQS_34             
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_out[16]]       ; ## JX4.80  IO_L22N_T3_34                 
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[16]]        ; ## JX4.79  IO_L21N_T3_DQS_34             
+set_property  -dict {PACKAGE_PIN  P14   IOSTANDARD  LVCMOS25} [get_ports  ltc2955_kill_n]   ; ## JX4.32   IO_L6P_T0_34
+set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD  LVCMOS25} [get_ports  ltc2955_int_n]    ; ## JX4.31   IO_L5P_T0_34
 
-## p2
+# oled
 
-set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[17]]       ; ## JX2.36  IO_L12P_T1_MRCC_13            
-set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[17]]        ; ## JX2.35  IO_L11P_T1_SRCC_13            
-set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  gp_out[18]]       ; ## JX2.38  IO_L12N_T1_MRCC_13            
-set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[18]]        ; ## JX2.37  IO_L11N_T1_SRCC_13            
-set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[19]]       ; ## JX2.42  IO_L14P_T2_SRCC_13            
-set_property  -dict {PACKAGE_PIN  Y7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[19]]        ; ## JX2.41  IO_L13P_T2_MRCC_13            
-set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD  LVCMOS25} [get_ports  gp_out[20]]       ; ## JX2.44  IO_L14N_T2_SRCC_13            
-set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD  LVCMOS25} [get_ports  gp_in[20]]        ; ## JX2.43  IO_L13N_T2_MRCC_13            
-set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  gp_out[21]]       ; ## JX2.48  IO_L16P_T2_13                 
-set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[21]]        ; ## JX2.47  IO_L15P_T2_DQS_13             
-set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[22]]       ; ## JX2.50  IO_L16N_T2_13                 
-set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[22]]        ; ## JX2.49  IO_L15N_T2_DQS_13             
-set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD  LVCMOS25} [get_ports  gp_out[23]]       ; ## JX2.54  IO_L18P_T2_13                 
-set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  gp_in[23]]        ; ## JX2.53  IO_L17P_T2_13                 
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_out[24]]       ; ## JX2.56  IO_L18N_T2_13                 
-set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[24]]        ; ## JX2.55  IO_L17N_T2_13                 
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[25]]       ; ## JX2.62  IO_L20P_T3_13                 
-set_property  -dict {PACKAGE_PIN  T5    IOSTANDARD  LVCMOS25} [get_ports  gp_in[25]]        ; ## JX2.61  IO_L19P_T3_13                 
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_out[26]]       ; ## JX2.64  IO_L20N_T3_13                 
-set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD  LVCMOS25} [get_ports  gp_in[26]]        ; ## JX2.63  IO_L19N_T3_VREF_13            
+set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  oled_cs_n]        ; ## JX2.18   IO_L6N_T0_VREF_13
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  oled_scl]         ; ## JX2.37   IO_L11N_T1_SRCC_13
+set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  oled_sdi]         ; ## JX2.36   IO_L12P_T1_MRCC_13
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  oled_d_c]         ; ## JX2.38   IO_L12N_T1_MRCC_13
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  oled_res          ; ## JX2.35   IO_L11P_T1_SRCC_13
 
-## vcc
+# adp5061
 
-set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[0]]    ; ## JX2.18  IO_L6N_T0_VREF_13 
-set_property  -dict {PACKAGE_PIN  V16   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[1]]    ; ## JX4.68  IO_L18P_T2_34                 
-set_property  -dict {PACKAGE_PIN  W16   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[2]]    ; ## JX4.70  IO_L18N_T2_34                 
-set_property  -dict {PACKAGE_PIN  V11   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[3]]    ; ## JX2.67  IO_L21P_T3_DQS_13             
-set_property  -dict {PACKAGE_PIN  V10   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[4]]    ; ## JX2.69  IO_L21N_T3_DQS_13             
+set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io1]      ; ## JX4.19   IO_L1P_T0_34
+set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io2]      ; ## JX4.21   IO_L1N_T0_34
+set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io3]      ; ## JX4.20   IO_L2P_T0_34
 
-## MIO loopbacks (fixed-io)
-## the following are connected to AD9361 GPIO
+# GPS
 
-##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
-##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
-##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
-##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
+set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD  LVCMOS25} [get_ports  gps_reset]        ; ## JX2,63   IO_L19N_T3_VREF_13
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gps_force_on]     ; ## JX2,62   IO_L20P_T3_13
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gps_standby]      ; ## JX2,64   IO_L20N_T3_13
+set_property  -dict {PACKAGE_PIN  T5    IOSTANDARD  LVCMOS25} [get_ports  gps_pps]          ; ## JX2,61   IO_L19P_T3_13
 
-## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
+# imu
 
-##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
+set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  imu_rst_n]        ; ## JX2,49   IO_L15N_T2_DQS_13
+set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  imu_cs_n]         ; ## JX2,48   IO_L16P_T2_13
+set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  imu_sclk]         ; ## JX2,50   IO_L16N_T2_13
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  imu_din]          ; ## JX2,53   IO_L17P_T2_13
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  imu_dout]         ; ## JX2,56   IO_L18N_T2_13
+set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  imu_dr]           ; ## JX2,55   IO_L17N_T2_13
+set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD  LVCMOS25} [get_ports  imu_sync]         ; ## JX2,54   IO_L18P_T2_13
 
-## the following are mio-to-pl loopback
+# audio
 
-##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
-##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
-##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
+set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD  LVCMOS25} [get_ports  i2s_bclk]         ; ## JX2,43   IO_L13N_T2_MRCC_13
+set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD  LVCMOS25} [get_ports  i2s_lrclk]        ; ## JX2,42   IO_L14P_T2_SRCC_13
+set_property  -dict {PACKAGE_PIN  Y7    IOSTANDARD  LVCMOS25} [get_ports  i2s_mclk]         ; ## JX2,41   IO_L13P_T2_MRCC_13
+set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD  LVCMOS25} [get_ports  i2s_sdata_in]     ; ## JX2,44   IO_L14N_T2_SRCC_13
+set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD  LVCMOS25} [get_ports  i2s_sdata_out]    ; ## JX2,47   IO_L15P_T2_DQS_13
 
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[0]]     ; ## JX4.67  IO_L17P_T2_34                 
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[1]]     ; ## JX4.37  IO_L7N_T1_34                  
-set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[2]]     ; ## JX4.42  IO_L10P_T1_34                 
+set_property  -dict {PACKAGE_PIN  U17   IOSTANDARD  LVCMOS25} [get_ports  mic_present_n]    ; ## JX4,43   IO_L9N_T1_DQS_34
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  ts3a227_int_n]    ; ## JX4,37   IO_L7N_T1_34
+
+# switch-led
+
+set_property  -dict {PACKAGE_PIN  Y14   IOSTANDARD  LVCMOS25} [get_ports  switch_led_r]     ; ## JX4,38   IO_L8N_T1_34
+set_property  -dict {PACKAGE_PIN  T16   IOSTANDARD  LVCMOS25} [get_ports  switch_led_g]     ; ## JX4,41   IO_L9P_T1_DQS_34
+set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD  LVCMOS25} [get_ports  switch_led_b]     ; ## JX4,42   IO_L10P_T1_34
+
+# power source
+
+set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid1_n]     ; ## JX4,27   IO_L3N_T0_DQS_34
+set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  pss_valid2_n]     ; ## JX4,26   IO_L4P_T0_34
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid3_n]     ; ## JX4,28   IO_L4N_T0_34
 
 
diff --git a/projects/pzsdr1/ccbox_lvds/system_project.tcl b/projects/pzsdr1/ccbox_lvds/system_project.tcl
index 21967b370..48b499451 100644
--- a/projects/pzsdr1/ccbox_lvds/system_project.tcl
+++ b/projects/pzsdr1/ccbox_lvds/system_project.tcl
@@ -3,8 +3,8 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
 
-adi_project_create ccbrk_pzsdr1
-adi_project_files ccbrk_pzsdr1 [list \
+adi_project_create ccbox_lvds_pzsdr1
+adi_project_files ccbox_lvds_pzsdr1 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
@@ -12,6 +12,6 @@ adi_project_files ccbrk_pzsdr1 [list \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
-adi_project_run ccbrk_pzsdr1
+adi_project_run ccbox_lvds_pzsdr1
 
 
diff --git a/projects/pzsdr1/ccbox_lvds/system_top.v b/projects/pzsdr1/ccbox_lvds/system_top.v
index 643b39163..203fe5bb9 100644
--- a/projects/pzsdr1/ccbox_lvds/system_top.v
+++ b/projects/pzsdr1/ccbox_lvds/system_top.v
@@ -39,164 +39,151 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  gpio_bd,
+  output          i2s_mclk,
+  output          i2s_bclk,
+  output          i2s_lrclk,
+  output          i2s_sdata_out,
+  input           i2s_sdata_in,
 
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
+  inout           imu_rst_n,
+  inout           imu_cs_n,
+  inout           imu_sclk,
+  inout           imu_din,
+  inout           imu_dout,
+  inout           imu_dr,
+  inout           imu_sync,
+  inout           oled_cs_n,
+  inout           oled_scl,
+  inout           oled_sdi,
+  inout           oled_d_c,
+  inout           oled_res,
+  inout           ltc2955_kill_n,
+  inout           ltc2955_int_n,
+  inout           adp5061_io1,
+  inout           adp5061_io2,
+  inout           adp5061_io3,
+  inout           gps_reset,
+  inout           gps_force_on,
+  inout           gps_standby,
+  inout           gps_pps,
+  inout           mic_present_n,
+  inout           ts3a227_int_n,
+  inout           switch_led_r,
+  inout           switch_led_g,
+  inout           switch_led_b,
+  inout           pss_valid1_n,
+  inout           pss_valid2_n,
+  inout           pss_valid3_n,
 
-  enable,
-  txnrx,
-  clk_out,
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
 
-  gpio_clksel,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
+  output          enable,
+  output          txnrx,
+  input           clk_out,
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
+  inout   [ 5:0]  gpio_rf,
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
 
-  gp_out,
-  gp_in,
-  gp_in_mio,
-  gp_in_open);
-
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  inout   [ 3:0]  gpio_bd;
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  output          enable;
-  output          txnrx;
-  input           clk_out;
-
-  inout           gpio_clksel;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
-
-  output  [26:0]  gp_out;
-  input   [26:0]  gp_in;
-  input   [ 2:0]  gp_in_mio;
-  input   [ 4:0]  gp_in_open;
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso);
 
   // internal signals
 
-  wire    [63:0]  gp_out_s;
-  wire    [63:0]  gp_in_s;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
-  // assignments
-
-  assign gp_out[26:0] = gp_out_s[26:0];
-  assign gp_in_s[34:30] = gp_in_open;
-  assign gp_in_s[29:27] = gp_in_mio;
-  assign gp_in_s[26: 0] = gp_in;
-
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
-    .dio_t ({gpio_t[51], gpio_t[46:32]}),
-    .dio_i ({gpio_o[51], gpio_o[46:32]}),
-    .dio_o ({gpio_i[51], gpio_i[46:32]}),
-    .dio_p ({ gpio_clksel,        // 51:51
+  ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
+    .dio_t ({gpio_t[57:51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[57:51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[57:51], gpio_i[46:32]}),
+    .dio_p ({ gpio_rf,            // 57:52
+              gpio_clksel,        // 51:51
               gpio_resetb,        // 46:46
               gpio_sync,          // 45:45
               gpio_en_agc,        // 44:44
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_bd (
-    .dio_t (gpio_t[3:0]),
-    .dio_i (gpio_o[3:0]),
-    .dio_o (gpio_i[3:0]),
-    .dio_p (gpio_bd));
+  ad_iobuf #(.DATA_WIDTH(29)) i_iobuf_bd (
+    .dio_t (gpio_t[28:0]),
+    .dio_i (gpio_o[28:0]),
+    .dio_o (gpio_i[28:0]),
+    .dio_p ({ imu_rst_n,
+              imu_cs_n,
+              imu_sclk,
+              imu_din,
+              imu_dout,
+              imu_dr,
+              imu_sync,
+              oled_cs_n,
+              oled_scl,
+              oled_sdi,
+              oled_d_c,
+              oled_res,
+              ltc2955_kill_n,
+              ltc2955_int_n,
+              adp5061_io1,
+              adp5061_io2,
+              adp5061_io3,
+              gps_reset,
+              gps_force_on,
+              gps_standby,
+              gps_pps,
+              mic_present_n,
+              ts3a227_int_n,
+              switch_led_r,
+              switch_led_g,
+              switch_led_b,
+              pss_valid1_n,
+              pss_valid2_n,
+              pss_valid3_n}));
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
@@ -221,13 +208,14 @@ module system_top (
     .fixed_io_ps_clk (fixed_io_ps_clk),
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gp_in_0 (gp_in_s[31:0]),
-    .gp_in_1 (gp_in_s[63:32]),
-    .gp_out_0 (gp_out_s[31:0]),
-    .gp_out_1 (gp_out_s[63:32]),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
+    .i2s_bclk (i2s_bclk),
+    .i2s_lrclk (i2s_lrclk),
+    .i2s_mclk (i2s_mclk),
+    .i2s_sdata_in (i2s_sdata_in),
+    .i2s_sdata_out (i2s_sdata_out),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
diff --git a/projects/pzsdr1/ccbrk/system_constr.xdc b/projects/pzsdr1/ccbrk/system_constr.xdc
index e54ad79c8..5b91e2425 100644
--- a/projects/pzsdr1/ccbrk/system_constr.xdc
+++ b/projects/pzsdr1/ccbrk/system_constr.xdc
@@ -1,4 +1,11 @@
 
+# gpio
+
+set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
+set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
+set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
+
 ## constraints
 ## loopback
 ## p6
diff --git a/projects/pzsdr1/common/ccbox_bd.tcl b/projects/pzsdr1/common/ccbox_bd.tcl
index 204545923..322433dd6 100644
--- a/projects/pzsdr1/common/ccbox_bd.tcl
+++ b/projects/pzsdr1/common/ccbox_bd.tcl
@@ -1,29 +1,44 @@
 
-# lbfmc
+# unused
 
 ad_connect  sys_ps7/ENET1_GMII_RX_CLK GND
 ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
 
-# un-used io
+# GPS-UART
 
-set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
-set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg
-set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg
+set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
 
-ad_cpu_interconnect 0x41200000 axi_gpreg
+# i2s
 
-create_bd_port -dir I -from 31 -to 0 gp_in_0
-create_bd_port -dir I -from 31 -to 0 gp_in_1
-create_bd_port -dir O -from 31 -to 0 gp_out_0
-create_bd_port -dir O -from 31 -to 0 gp_out_1
+create_bd_port -dir O -type clk i2s_mclk
+create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
 
-ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
-ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
-ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
-ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
+set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
 
-## temporary (remove ila indirectly)
+set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
+set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
+set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
 
-delete_bd_objs [get_bd_cells ila_adc]
-delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
+ad_connect  sys_200m_clk sys_audio_clkgen/clk_in1
+ad_connect  sys_cpu_resetn sys_audio_clkgen/resetn
+ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
+ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA1_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA2_ACLK
+ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
+ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
+ad_connect  sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
+ad_connect  sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
+ad_connect  sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
+ad_connect  sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
+ad_connect  sys_audio_clkgen/clk_out1 i2s_mclk
+ad_connect  sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
+ad_connect  i2s axi_i2s_adi/I2S
+
+ad_cpu_interconnect 0x77600000 axi_i2s_adi
 

From 918ce45e2af567c6957710aabde91bb9ecceac15 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 17 Oct 2016 16:29:43 -0400
Subject: [PATCH 615/972] pzsdr1/ccbox- updates

---
 projects/pzsdr1/ccbox_lvds/system_constr.xdc  | 2 +-
 projects/pzsdr1/ccbox_lvds/system_project.tcl | 1 -
 projects/pzsdr1/common/ccbox_bd.tcl           | 2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/projects/pzsdr1/ccbox_lvds/system_constr.xdc b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
index 523ccadae..279f0ff21 100644
--- a/projects/pzsdr1/ccbox_lvds/system_constr.xdc
+++ b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
@@ -20,7 +20,7 @@ set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  oled_c
 set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  oled_scl]         ; ## JX2.37   IO_L11N_T1_SRCC_13
 set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  oled_sdi]         ; ## JX2.36   IO_L12P_T1_MRCC_13
 set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  oled_d_c]         ; ## JX2.38   IO_L12N_T1_MRCC_13
-set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  oled_res          ; ## JX2.35   IO_L11P_T1_SRCC_13
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  oled_res]         ; ## JX2.35   IO_L11P_T1_SRCC_13
 
 # adp5061
 
diff --git a/projects/pzsdr1/ccbox_lvds/system_project.tcl b/projects/pzsdr1/ccbox_lvds/system_project.tcl
index 48b499451..d751a0f29 100644
--- a/projects/pzsdr1/ccbox_lvds/system_project.tcl
+++ b/projects/pzsdr1/ccbox_lvds/system_project.tcl
@@ -11,7 +11,6 @@ adi_project_files ccbox_lvds_pzsdr1 [list \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
 adi_project_run ccbox_lvds_pzsdr1
 
 
diff --git a/projects/pzsdr1/common/ccbox_bd.tcl b/projects/pzsdr1/common/ccbox_bd.tcl
index 322433dd6..a60e9dd58 100644
--- a/projects/pzsdr1/common/ccbox_bd.tcl
+++ b/projects/pzsdr1/common/ccbox_bd.tcl
@@ -8,6 +8,8 @@ ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
 
 set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USE_DMA2 1 [get_bd_cells sys_ps7]
 
 # i2s
 

From ecc0addb8c396fe508beace40360c56296807764 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 18 Oct 2016 11:25:06 +0300
Subject: [PATCH 616/972] scripts/adi_ip_alt.tcl: Script is case insensitive
 for its arguments

---
 library/scripts/adi_ip_alt.tcl | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl
index 664b1d5d1..f8e36343d 100644
--- a/library/scripts/adi_ip_alt.tcl
+++ b/library/scripts/adi_ip_alt.tcl
@@ -3,26 +3,26 @@
 
 proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
 
-  if {(($type eq "clock") && ($dir eq "input"))} {
+  if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "input"])} {
     add_interface if_${name} clock sink
     add_interface_port if_${name} ${name} clk ${dir} ${width}
     return
   }
 
-  if {(($type eq "clock") && ($dir eq "output"))} {
+  if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "output"])} {
     add_interface if_${name} clock source
     add_interface_port if_${name} ${name} clk ${dir} ${width}
     return
   }
 
-  if {(($type eq "reset") && ($dir eq "input"))} {
+  if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "input"])} {
     add_interface if_${name} reset sink
     add_interface_port if_${name} ${name} reset ${dir} ${width}
     set_interface_property if_${name} associatedclock ${arg_1}
     return
   }
 
-  if {(($type eq "reset") && ($dir eq "output"))} {
+  if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "output"])} {
     add_interface if_${name} reset source
     add_interface_port if_${name} ${name} reset ${dir} ${width}
     set_interface_property if_${name} associatedclock ${arg_1}
@@ -30,14 +30,14 @@ proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
     return
   }
 
-  if {(($type eq "reset-n") && ($dir eq "input"))} {
+  if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "input"])} {
     add_interface if_${name} reset sink
     add_interface_port if_${name} ${name} reset_n ${dir} ${width}
     set_interface_property if_${name} associatedclock ${arg_1}
     return
   }
 
-  if {(($type eq "reset-n") && ($dir eq "output"))} {
+  if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "output"])} {
     add_interface if_${name} reset source
     add_interface_port if_${name} ${name} reset_n ${dir} ${width}
     set_interface_property if_${name} associatedclock ${arg_1}
@@ -45,7 +45,7 @@ proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
     return
   }
 
-  if {(($type eq "intr") && ($dir eq "output"))} {
+  if {([string equal -nocase ${type} "intr"]) && ([string equal -nocase ${dir} "output"])} {
     add_interface if_${name} interrupt source
     add_interface_port if_${name} ${name} irq ${dir} ${width}
     set_interface_property if_${name} associatedclock ${arg_1}
@@ -57,7 +57,7 @@ proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
     set remap $name
   }
 
-  if {$type eq "signal"} {
+  if {[string equal -nocase ${type} "signal"]} {
     add_interface if_${name} conduit end
     add_interface_port if_${name} ${name} ${remap} ${dir} ${width}
     return

From 17cfdd6be9d8549f8c4042d41ef6c5886900747e Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 18 Oct 2016 12:42:14 +0300
Subject: [PATCH 617/972] fmcomms2/a10gx: Update Makefile and qsys script

---
 projects/fmcomms2/a10gx/Makefile        | 4 ++--
 projects/fmcomms2/a10gx/system_qsys.tcl | 1 -
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 6011b3a7a..51fde8d74 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -19,8 +19,8 @@ M_DEPS += ../common/fmcomms2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
-M_DEPS += ../../../altera/axi_ad9361_cmos_if.v
-M_DEPS += ../../../altera/axi_ad9361_lvds_if.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_cmos_if.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
 M_DEPS += ../../../library/altera/common/ad_cmos_in.v
 M_DEPS += ../../../library/altera/common/ad_cmos_out.v
diff --git a/projects/fmcomms2/a10gx/system_qsys.tcl b/projects/fmcomms2/a10gx/system_qsys.tcl
index 07a5e1a90..04e76cacf 100644
--- a/projects/fmcomms2/a10gx/system_qsys.tcl
+++ b/projects/fmcomms2/a10gx/system_qsys.tcl
@@ -1,5 +1,4 @@
 
-source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/fmcomms2_qsys.tcl
 

From c1b7c5e77a5313fd6ad00af905dc02e2f8614e64 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 19 Oct 2016 09:30:51 +0300
Subject: [PATCH 618/972] usb_fx3: Added FIFO on the FX3 to Zynq path, between
 FX3 core and DMA core

---
 projects/usb_fx3/common/usb_fx3_bd.tcl | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl
index 3dbcdde85..9091adbae 100644
--- a/projects/usb_fx3/common/usb_fx3_bd.tcl
+++ b/projects/usb_fx3/common/usb_fx3_bd.tcl
@@ -28,9 +28,16 @@ set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma
 set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma
 set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
 
-ad_connect axi_usb_fx3_dma/S_AXIS_S2MM axi_usb_fx3/m_axis
+set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ]
+
 ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
 
+ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk
+ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn
+
+ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS
+ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS
+
 ad_connect axi_uart/rx usb_fx3_uart_tx
 ad_connect axi_uart/tx usb_fx3_uart_rx
 
@@ -50,6 +57,7 @@ ad_connect axi_usb_fx3/slwr_n slwr_n
 ad_connect axi_usb_fx3/pktend_n pktend_n
 ad_connect axi_usb_fx3/epswitch_n epswitch_n
 
+
 ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
 ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
 ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut

From 72c05e8635107b0d11a002228f536b6c5fd88c79 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Wed, 19 Oct 2016 13:44:51 +0200
Subject: [PATCH 619/972] axi_dmac: Fix constraints for ultrascale

Replace "PRIMITIVE_SUBGROUP == flop" with "IS_SEQUENTIAL" as the former is
series7 specific while the later works on all platforms. This fixes the
axi_dmac timing constraints for ultrascale based platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_dmac/axi_dmac_constr.ttcl | 56 +++++++++++++--------------
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl
index 2ca055ecf..a2cabf55f 100644
--- a/library/axi_dmac/axi_dmac_constr.ttcl
+++ b/library/axi_dmac/axi_dmac_constr.ttcl
@@ -21,40 +21,40 @@ set_property ASYNC_REG TRUE \
 set_max_delay -quiet -datapath_only \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $req_clk]
 
 set_false_path -quiet \
 	-from $src_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}]
+		-filter {NAME =~ *i_sync_status_src* && IS_SEQUENTIAL}]
 
 set_false_path -quiet \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}]
+		-filter {NAME =~ *i_sync_control_src* && IS_SEQUENTIAL}]
 
 set_max_delay -quiet -datapath_only \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $req_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $src_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $src_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
-		-filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_src_req_fifo* && IS_SEQUENTIAL}] \
 	-to $src_clk \
 	[get_property -min PERIOD $src_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from [get_cells -quiet -hier *eot_mem_reg* \
-		-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \
 	-to $src_clk \
 	[get_property -min PERIOD $src_clk]
 
@@ -63,57 +63,57 @@ set_max_delay -quiet -datapath_only \
 set_max_delay -quiet -datapath_only \
 	-from $dest_clk \
 	-to [get_cells -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_sync_req_response_id* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $dest_clk]
 
 set_false_path -quiet \
 	-from $dest_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}]
+		-filter {NAME =~ *i_sync_status_dest* && IS_SEQUENTIAL}]
 
 set_false_path -quiet \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}]
+		-filter {NAME =~ *i_sync_control_dest* && IS_SEQUENTIAL}]
 
 set_max_delay -quiet -datapath_only \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $req_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $dest_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $dest_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
-		-filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_dest_req_fifo* && IS_SEQUENTIAL}] \
 	-to $dest_clk \
 	[get_property -min PERIOD $dest_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $dest_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $dest_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $req_clk]
 set_max_delay -quiet -datapath_only \
 	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
-		-filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_dest_response_fifo* && IS_SEQUENTIAL}] \
 	-to $req_clk \
 	[get_property -min PERIOD $req_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from [get_cells -quiet -hier *eot_mem_reg* \
-		-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \
 	-to $dest_clk \
 	[get_property -min PERIOD $dest_clk]
 
@@ -122,19 +122,19 @@ set_max_delay -quiet -datapath_only \
 set_max_delay -quiet -datapath_only \
 	-from $src_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $src_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $src_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $src_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $dest_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
+		-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $dest_clk]
 
 # In SDP mode REGCEB should not be connected. When inferring the BRAM the tools
@@ -153,15 +153,15 @@ set_false_path -quiet \
 # Ignore timing for debug signals to register map
 set_false_path -quiet \
 	-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
-		-filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \
-	-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
+		-filter {name =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
 set_false_path -quiet \
 	-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
-		-filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \
-	-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
+		-filter {name =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
 set_false_path -quiet \
-	-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \
-	-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
+	-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && IS_SEQUENTIAL}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
 set_false_path -quiet \
-	-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \
-	-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
+	-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && IS_SEQUENTIAL}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]

From 7db0c03a92a5c8569c624cf0d54708b766686a6f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 19 Oct 2016 10:32:04 -0400
Subject: [PATCH 620/972] pzsdr1+ccbox -- updates

---
 projects/pzsdr1/ccbox_lvds/system_constr.xdc |  34 ++--
 projects/pzsdr1/ccbox_lvds/system_top.v      | 160 +++++++++++--------
 2 files changed, 112 insertions(+), 82 deletions(-)

diff --git a/projects/pzsdr1/ccbox_lvds/system_constr.xdc b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
index 279f0ff21..f72968bf4 100644
--- a/projects/pzsdr1/ccbox_lvds/system_constr.xdc
+++ b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
@@ -16,17 +16,17 @@ set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD  LVCMOS25} [get_ports  ltc295
 
 # oled
 
-set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  oled_cs_n]        ; ## JX2.18   IO_L6N_T0_VREF_13
-set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  oled_scl]         ; ## JX2.37   IO_L11N_T1_SRCC_13
-set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  oled_sdi]         ; ## JX2.36   IO_L12P_T1_MRCC_13
-set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  oled_d_c]         ; ## JX2.38   IO_L12N_T1_MRCC_13
-set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  oled_res]         ; ## JX2.35   IO_L11P_T1_SRCC_13
+set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  oled_csn]         ; ## JX2.18   IO_L6N_T0_VREF_13
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  oled_clk]         ; ## JX2.37   IO_L11N_T1_SRCC_13
+set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  oled_mosi]        ; ## JX2.36   IO_L12P_T1_MRCC_13
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  oled_rst]         ; ## JX2.35   IO_L11P_T1_SRCC_13
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  oled_dc]          ; ## JX2.38   IO_L12N_T1_MRCC_13
 
 # adp5061
 
-set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io1]      ; ## JX4.19   IO_L1P_T0_34
-set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io2]      ; ## JX4.21   IO_L1N_T0_34
-set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io3]      ; ## JX4.20   IO_L2P_T0_34
+set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[0]]    ; ## JX4.19   IO_L1P_T0_34
+set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[1]]    ; ## JX4.21   IO_L1N_T0_34
+set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[2]]    ; ## JX4.20   IO_L2P_T0_34
 
 # GPS
 
@@ -37,13 +37,13 @@ set_property  -dict {PACKAGE_PIN  T5    IOSTANDARD  LVCMOS25} [get_ports  gps_pp
 
 # imu
 
-set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  imu_rst_n]        ; ## JX2,49   IO_L15N_T2_DQS_13
-set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  imu_cs_n]         ; ## JX2,48   IO_L16P_T2_13
-set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  imu_sclk]         ; ## JX2,50   IO_L16N_T2_13
-set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  imu_din]          ; ## JX2,53   IO_L17P_T2_13
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  imu_dout]         ; ## JX2,56   IO_L18N_T2_13
-set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  imu_dr]           ; ## JX2,55   IO_L17N_T2_13
+set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  imu_csn]          ; ## JX2,48   IO_L16P_T2_13
+set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  imu_clk]          ; ## JX2,50   IO_L16N_T2_13
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  imu_mosi]         ; ## JX2,53   IO_L17P_T2_13
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  imu_miso]         ; ## JX2,56   IO_L18N_T2_13
+set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  imu_rstn]         ; ## JX2,49   IO_L15N_T2_DQS_13
 set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD  LVCMOS25} [get_ports  imu_sync]         ; ## JX2,54   IO_L18P_T2_13
+set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  imu_ready]        ; ## JX2,55   IO_L17N_T2_13
 
 # audio
 
@@ -64,8 +64,8 @@ set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD  LVCMOS25} [get_ports  switch
 
 # power source
 
-set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid1_n]     ; ## JX4,27   IO_L3N_T0_DQS_34
-set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  pss_valid2_n]     ; ## JX4,26   IO_L4P_T0_34
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid3_n]     ; ## JX4,28   IO_L4N_T0_34
+set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[0]]   ; ## JX4,27   IO_L3N_T0_DQS_34
+set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[1]]   ; ## JX4,26   IO_L4P_T0_34
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[2]]   ; ## JX4,28   IO_L4N_T0_34
 
 
diff --git a/projects/pzsdr1/ccbox_lvds/system_top.v b/projects/pzsdr1/ccbox_lvds/system_top.v
index 203fe5bb9..7b51d5d94 100644
--- a/projects/pzsdr1/ccbox_lvds/system_top.v
+++ b/projects/pzsdr1/ccbox_lvds/system_top.v
@@ -71,35 +71,36 @@ module system_top (
   output          i2s_sdata_out,
   input           i2s_sdata_in,
 
-  inout           imu_rst_n,
-  inout           imu_cs_n,
-  inout           imu_sclk,
-  inout           imu_din,
-  inout           imu_dout,
-  inout           imu_dr,
+  output          imu_csn,
+  output          imu_clk,
+  output          imu_mosi,
+  input           imu_miso,
+  input           imu_ready,
+  output          imu_rstn,
   inout           imu_sync,
-  inout           oled_cs_n,
-  inout           oled_scl,
-  inout           oled_sdi,
-  inout           oled_d_c,
-  inout           oled_res,
+
+  output          oled_csn,
+  output          oled_clk,
+  output          oled_mosi,
+  output          oled_rst,
+  output          oled_dc,
+
+  output          switch_led_r,
+  output          switch_led_g,
+  output          switch_led_b,
+
+  output          gps_reset,
+  output          gps_force_on,
+  output          gps_standby,
+  input           gps_pps,
+
+  input   [ 2:0]  pss_valid_n,
+  inout   [ 2:0]  adp5061_io,
+
   inout           ltc2955_kill_n,
   inout           ltc2955_int_n,
-  inout           adp5061_io1,
-  inout           adp5061_io2,
-  inout           adp5061_io3,
-  inout           gps_reset,
-  inout           gps_force_on,
-  inout           gps_standby,
-  inout           gps_pps,
   inout           mic_present_n,
   inout           ts3a227_int_n,
-  inout           switch_led_r,
-  inout           switch_led_g,
-  inout           switch_led_b,
-  inout           pss_valid1_n,
-  inout           pss_valid2_n,
-  inout           pss_valid3_n,
 
   input           rx_clk_in_p,
   input           rx_clk_in_n,
@@ -137,7 +138,68 @@ module system_top (
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
-  // instantiations
+  // assignments
+
+  assign oled_clk = spi_clk;
+  assign oled_mosi = spi_mosi;
+  assign gpio_i[31:24] = gpio_o[31:24];
+
+  // gpio[23:20] controls misc stuff (keep as io)
+
+  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_misc (
+    .dio_t (gpio_t[23:20]),
+    .dio_i (gpio_o[23:20]),
+    .dio_o (gpio_i[23:20]),
+    .dio_p ({ ltc2955_kill_n,
+              ltc2955_int_n,
+              ts3a227_int_n,
+              mic_present_n}));
+
+  // gpio[19:16] controls adp5061 (keep as io)
+
+  assign gpio_i[19] = gpio_o[19];
+
+  ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_adp5061 (
+    .dio_t (gpio_t[18:16]),
+    .dio_i (gpio_o[18:16]),
+    .dio_o (gpio_i[18:16]),
+    .dio_p (adp5061_io));
+
+  // gpio[15:12] reads power source select valids
+
+  assign gpio_i[15:12] = {gpio_o[15], pss_valid_n};
+
+  // gpio[11:8] controls the imu/oled reset & such.
+
+  assign oled_dc = gpio_o[11];
+  assign oled_rst = gpio_o[10];
+  assign imu_rstn = gpio_o[9];
+  assign gpio_i[11:9] = gpio_o[11:9];
+
+  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_imu_sync (
+    .dio_t (gpio_t[8]),
+    .dio_i (gpio_o[8]),
+    .dio_o (gpio_i[8]),
+    .dio_p (imu_sync));
+
+  // gpio[7:4] controls the gps
+
+  assign gps_reset = gpio_o[6];
+  assign gps_force_on = gpio_o[5];
+  assign gps_standby = gpio_o[4];
+  assign gpio_i[7:4] = {gps_pps, gpio_o[6:4]};
+
+  // gpio[3:0] controls the power switch led colors
+
+  assign switch_led_r = gpio_o[2];
+  assign switch_led_g = gpio_o[1];
+  assign switch_led_b = gpio_o[0];
+  assign gpio_i[3:0] = gpio_o[3:0];
+
+  // ad9361 gpio
+
+  assign gpio_i[63:58] = gpio_o[63:58];
+  assign gpio_i[50:47] = gpio_o[50:47];
 
   ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
     .dio_t ({gpio_t[57:51], gpio_t[46:32]}),
@@ -151,39 +213,7 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(29)) i_iobuf_bd (
-    .dio_t (gpio_t[28:0]),
-    .dio_i (gpio_o[28:0]),
-    .dio_o (gpio_i[28:0]),
-    .dio_p ({ imu_rst_n,
-              imu_cs_n,
-              imu_sclk,
-              imu_din,
-              imu_dout,
-              imu_dr,
-              imu_sync,
-              oled_cs_n,
-              oled_scl,
-              oled_sdi,
-              oled_d_c,
-              oled_res,
-              ltc2955_kill_n,
-              ltc2955_int_n,
-              adp5061_io1,
-              adp5061_io2,
-              adp5061_io3,
-              gps_reset,
-              gps_force_on,
-              gps_standby,
-              gps_pps,
-              mic_present_n,
-              ts3a227_int_n,
-              switch_led_r,
-              switch_led_g,
-              switch_led_b,
-              pss_valid1_n,
-              pss_valid2_n,
-              pss_valid3_n}));
+  // instantiations
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
@@ -219,7 +249,7 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
-    .ps_intr_00 (1'b0),
+    .ps_intr_00 (imu_ready),
     .ps_intr_01 (1'b0),
     .ps_intr_02 (1'b0),
     .ps_intr_03 (1'b0),
@@ -241,22 +271,22 @@ module system_top (
     .spi0_clk_i (1'b0),
     .spi0_clk_o (spi_clk),
     .spi0_csn_0_o (spi_csn),
-    .spi0_csn_1_o (),
+    .spi0_csn_1_o (oled_csn),
     .spi0_csn_2_o (),
     .spi0_csn_i (1'b1),
     .spi0_sdi_i (spi_miso),
     .spi0_sdo_i (1'b0),
     .spi0_sdo_o (spi_mosi),
     .spi1_clk_i (1'b0),
-    .spi1_clk_o (),
-    .spi1_csn_0_o (),
+    .spi1_clk_o (imu_clk),
+    .spi1_csn_0_o (imu_csn),
     .spi1_csn_1_o (),
     .spi1_csn_2_o (),
     .spi1_csn_i (1'b1),
-    .spi1_sdi_i (1'b0),
+    .spi1_sdi_i (imu_miso),
     .spi1_sdo_i (1'b0),
-    .spi1_sdo_o (),
-    .tdd_sync_i (1'b0),
+    .spi1_sdo_o (imu_mosi),
+    .tdd_sync_i (gps_pps),
     .tdd_sync_o (),
     .tdd_sync_t (),
     .tx_clk_out_n (tx_clk_out_n),

From 0beecea02d63670d0c17ca42b5fa8750803c86ab Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 19 Oct 2016 13:05:59 -0400
Subject: [PATCH 621/972] util_adxcvr- ultrascale updates

---
 library/xilinx/util_adxcvr/util_adxcvr_xch.v | 771 ++++++++++---------
 library/xilinx/util_adxcvr/util_adxcvr_xcm.v | 211 ++---
 2 files changed, 492 insertions(+), 490 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 14b477914..435207e6a 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -760,11 +760,11 @@ module util_adxcvr_xch #(
     .ACJTAG_DEBUG_MODE (1'b0),
     .ACJTAG_MODE (1'b0),
     .ACJTAG_RESET (1'b0),
-    .ADAPT_CFG0 (16'b1111100000000000),
-    .ADAPT_CFG1 (16'b0000000000000000),
+    .ADAPT_CFG0 (16'hf800),
+    .ADAPT_CFG1 (16'h0000),
     .ALIGN_COMMA_DOUBLE ("FALSE"),
     .ALIGN_COMMA_ENABLE (10'b1111111111),
-    .ALIGN_COMMA_WORD (1'h1),
+    .ALIGN_COMMA_WORD (1),
     .ALIGN_MCOMMA_DET ("TRUE"),
     .ALIGN_MCOMMA_VALUE (10'b1010000011),
     .ALIGN_PCOMMA_DET ("TRUE"),
@@ -775,7 +775,7 @@ module util_adxcvr_xch #(
     .CBCC_DATA_SOURCE_SEL ("DECODED"),
     .CDR_SWAP_MODE_EN (1'b0),
     .CHAN_BOND_KEEP_ALIGN ("FALSE"),
-    .CHAN_BOND_MAX_SKEW (1'h1),
+    .CHAN_BOND_MAX_SKEW (1),
     .CHAN_BOND_SEQ_1_1 (10'b0000000000),
     .CHAN_BOND_SEQ_1_2 (10'b0000000000),
     .CHAN_BOND_SEQ_1_3 (10'b0000000000),
@@ -787,13 +787,13 @@ module util_adxcvr_xch #(
     .CHAN_BOND_SEQ_2_4 (10'b0000000000),
     .CHAN_BOND_SEQ_2_ENABLE (4'b1111),
     .CHAN_BOND_SEQ_2_USE ("FALSE"),
-    .CHAN_BOND_SEQ_LEN (1'h1),
+    .CHAN_BOND_SEQ_LEN (1),
     .CLK_CORRECT_USE ("FALSE"),
     .CLK_COR_KEEP_IDLE ("FALSE"),
     .CLK_COR_MAX_LAT (12),
     .CLK_COR_MIN_LAT (8),
     .CLK_COR_PRECEDENCE ("TRUE"),
-    .CLK_COR_REPEAT_WAIT (1'h0),
+    .CLK_COR_REPEAT_WAIT (0),
     .CLK_COR_SEQ_1_1 (10'b0100000000),
     .CLK_COR_SEQ_1_2 (10'b0100000000),
     .CLK_COR_SEQ_1_3 (10'b0100000000),
@@ -805,17 +805,17 @@ module util_adxcvr_xch #(
     .CLK_COR_SEQ_2_4 (10'b0100000000),
     .CLK_COR_SEQ_2_ENABLE (4'b1111),
     .CLK_COR_SEQ_2_USE ("FALSE"),
-    .CLK_COR_SEQ_LEN (1'h1),
-    .CPLL_CFG0 (16'b0110011111111010),
-    .CPLL_CFG1 (16'b1010010010010100),
-    .CPLL_CFG2 (16'b1111000000000111),
-    .CPLL_CFG3 (6'b000000),
+    .CLK_COR_SEQ_LEN (1),
+    .CPLL_CFG0 (16'h67f8),
+    .CPLL_CFG1 (16'ha4ac),
+    .CPLL_CFG2 (16'h0007),
+    .CPLL_CFG3 (6'h00),
     .CPLL_FBDIV (CPLL_FBDIV),
-    .CPLL_FBDIV_45 (5),
-    .CPLL_INIT_CFG0 (16'b0000000000011110),
-    .CPLL_INIT_CFG1 (8'b00000000),
-    .CPLL_LOCK_CFG (16'b0000000111101000),
-    .CPLL_REFCLK_DIV (1'h1),
+    .CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
+    .CPLL_INIT_CFG0 (16'h02b2),
+    .CPLL_INIT_CFG1 (8'h00),
+    .CPLL_LOCK_CFG (16'h01e8),
+    .CPLL_REFCLK_DIV (1),
     .DDI_CTRL (2'b00),
     .DDI_REALIGN_WAIT (15),
     .DEC_MCOMMA_DETECT ("TRUE"),
@@ -823,30 +823,30 @@ module util_adxcvr_xch #(
     .DEC_VALID_COMMA_ONLY ("FALSE"),
     .DFE_D_X_REL_POS (1'b0),
     .DFE_VCM_COMP_EN (1'b0),
-    .DMONITOR_CFG0 (10'b0000000000),
-    .DMONITOR_CFG1 (8'b00000000),
+    .DMONITOR_CFG0 (10'h000),
+    .DMONITOR_CFG1 (8'h00),
     .ES_CLK_PHASE_SEL (1'b0),
     .ES_CONTROL (6'b000000),
     .ES_ERRDET_EN ("TRUE"),
     .ES_EYE_SCAN_EN ("TRUE"),
-    .ES_HORZ_OFFSET (12'b000000000000),
+    .ES_HORZ_OFFSET (12'h000),
     .ES_PMA_CFG (10'b0000000000),
     .ES_PRESCALE (5'b00000),
-    .ES_QUALIFIER0 (16'b0000000000000000),
-    .ES_QUALIFIER1 (16'b0000000000000000),
-    .ES_QUALIFIER2 (16'b0000000000000000),
-    .ES_QUALIFIER3 (16'b0000000000000000),
-    .ES_QUALIFIER4 (16'b0000000000000000),
-    .ES_QUAL_MASK0 (16'b0000000000000000),
-    .ES_QUAL_MASK1 (16'b0000000000000000),
-    .ES_QUAL_MASK2 (16'b0000000000000000),
-    .ES_QUAL_MASK3 (16'b0000000000000000),
-    .ES_QUAL_MASK4 (16'b0000000000000000),
-    .ES_SDATA_MASK0 (16'b0000000000000000),
-    .ES_SDATA_MASK1 (16'b0000000000000000),
-    .ES_SDATA_MASK2 (16'b0000000000000000),
-    .ES_SDATA_MASK3 (16'b0000000000000000),
-    .ES_SDATA_MASK4 (16'b0000000000000000),
+    .ES_QUALIFIER0 (16'h0000),
+    .ES_QUALIFIER1 (16'h0000),
+    .ES_QUALIFIER2 (16'h0000),
+    .ES_QUALIFIER3 (16'h0000),
+    .ES_QUALIFIER4 (16'h0000),
+    .ES_QUAL_MASK0 (16'h0000),
+    .ES_QUAL_MASK1 (16'h0000),
+    .ES_QUAL_MASK2 (16'h0000),
+    .ES_QUAL_MASK3 (16'h0000),
+    .ES_QUAL_MASK4 (16'h0000),
+    .ES_SDATA_MASK0 (16'h0000),
+    .ES_SDATA_MASK1 (16'h0000),
+    .ES_SDATA_MASK2 (16'h0000),
+    .ES_SDATA_MASK3 (16'h0000),
+    .ES_SDATA_MASK4 (16'h0000),
     .EVODD_PHI_CFG (11'b00000000000),
     .EYE_SCAN_SWAP_EN (1'b0),
     .FTS_DESKEW_SEQ_ENABLE (4'b1111),
@@ -866,22 +866,22 @@ module util_adxcvr_xch #(
     .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
     .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
     .PCI3_RX_FIFO_DISABLE (1'b0),
-    .PCIE_BUFG_DIV_CTRL (16'b0011010100001001),
-    .PCIE_RXPCS_CFG_GEN3 (16'b0000001010100100),
-    .PCIE_RXPMA_CFG (16'b0000000000001010),
-    .PCIE_TXPCS_CFG_GEN3 (16'b0010010010100000),
-    .PCIE_TXPMA_CFG (16'b0000000000001010),
+    .PCIE_BUFG_DIV_CTRL (16'h1000),
+    .PCIE_RXPCS_CFG_GEN3 (16'h02a4),
+    .PCIE_RXPMA_CFG (16'h000a),
+    .PCIE_TXPCS_CFG_GEN3 (16'h24a4),
+    .PCIE_TXPMA_CFG (16'h000a),
     .PCS_PCIE_EN ("FALSE"),
     .PCS_RSVD0 (16'b0000000000000000),
     .PCS_RSVD1 (3'b000),
-    .PD_TRANS_TIME_FROM_P2 (12'b000000111100),
-    .PD_TRANS_TIME_NONE_P2 (8'b00011001),
-    .PD_TRANS_TIME_TO_P2 (8'b01100100),
-    .PLL_SEL_MODE_GEN12 (2'b11),
-    .PLL_SEL_MODE_GEN3 (2'b11),
-    .PMA_RSV1 (16'b0001000000000000),
+    .PD_TRANS_TIME_FROM_P2 (12'h03c),
+    .PD_TRANS_TIME_NONE_P2 (8'h19),
+    .PD_TRANS_TIME_TO_P2 (8'h64),
+    .PLL_SEL_MODE_GEN12 (2'h3),
+    .PLL_SEL_MODE_GEN3 (2'h3),
+    .PMA_RSV1 (16'hf000),
     .PROCESS_PAR (3'b010),
-    .RATE_SW_USE_DRP (1'b0),
+    .RATE_SW_USE_DRP (1'b1),
     .RESET_POWERSAVE_DISABLE (1'b0),
     .RXBUFRESET_TIME (5'b00011),
     .RXBUF_ADDR_MODE ("FAST"),
@@ -891,105 +891,105 @@ module util_adxcvr_xch #(
     .RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
     .RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
     .RXBUF_RESET_ON_EIDLE ("FALSE"),
-    .RXBUF_RESET_ON_RATE_CHANGE ("FALSE"),
+    .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
     .RXBUF_THRESH_OVFLW (57),
     .RXBUF_THRESH_OVRD ("TRUE"),
     .RXBUF_THRESH_UNDFLW (3),
     .RXCDRFREQRESET_TIME (5'b00001),
     .RXCDRPHRESET_TIME (5'b00001),
-    .RXCDR_CFG0 (16'b0000000000000000),
-    .RXCDR_CFG0_GEN3 (16'b0000000000000000),
-    .RXCDR_CFG1 (16'b0000000000000000),
-    .RXCDR_CFG1_GEN3 (16'b0000000000000000),
-    .RXCDR_CFG2 (16'b0000011101100110),
-    .RXCDR_CFG2_GEN3 (16'b0000011101100110),
-    .RXCDR_CFG3 (16'b0000000000000000),
-    .RXCDR_CFG3_GEN3 (16'b0000000000000000),
-    .RXCDR_CFG4 (16'b0000000000000000),
-    .RXCDR_CFG4_GEN3 (16'b0000000000000000),
-    .RXCDR_CFG5 (16'b0000000000000000),
-    .RXCDR_CFG5_GEN3 (16'b0000000000000000),
+    .RXCDR_CFG0 (16'h0000),
+    .RXCDR_CFG0_GEN3 (16'h0000),
+    .RXCDR_CFG1 (16'h0000),
+    .RXCDR_CFG1_GEN3 (16'h0000),
+    .RXCDR_CFG2 (16'h0766),
+    .RXCDR_CFG2_GEN3 (16'h07e6),
+    .RXCDR_CFG3 (16'h0000),
+    .RXCDR_CFG3_GEN3 (16'h0000),
+    .RXCDR_CFG4 (16'h0000),
+    .RXCDR_CFG4_GEN3 (16'h0000),
+    .RXCDR_CFG5 (16'h0000),
+    .RXCDR_CFG5_GEN3 (16'h0000),
     .RXCDR_FR_RESET_ON_EIDLE (1'b0),
     .RXCDR_HOLD_DURING_EIDLE (1'b0),
-    .RXCDR_LOCK_CFG0 (16'b0100010010000000),
-    .RXCDR_LOCK_CFG1 (16'b0101111111111111),
-    .RXCDR_LOCK_CFG2 (16'b0111011111000011),
+    .RXCDR_LOCK_CFG0 (16'h4480),
+    .RXCDR_LOCK_CFG1 (16'h5fff),
+    .RXCDR_LOCK_CFG2 (16'h77c3),
     .RXCDR_PH_RESET_ON_EIDLE (1'b0),
-    .RXCFOK_CFG0 (16'b0100000000000000),
-    .RXCFOK_CFG1 (16'b0000000001100101),
-    .RXCFOK_CFG2 (16'b0000000000101110),
+    .RXCFOK_CFG0 (16'h4000),
+    .RXCFOK_CFG1 (16'h0065),
+    .RXCFOK_CFG2 (16'h002e),
     .RXDFELPMRESET_TIME (7'b0001111),
-    .RXDFELPM_KL_CFG0 (16'b0000000000000000),
-    .RXDFELPM_KL_CFG1 (16'b0000000000000010),
-    .RXDFELPM_KL_CFG2 (16'b0000000000000000),
-    .RXDFE_CFG0 (16'b0000101000000000),
-    .RXDFE_CFG1 (16'b0000000000000000),
-    .RXDFE_GC_CFG0 (16'b0000000000000000),
-    .RXDFE_GC_CFG1 (16'b0111100001100000),
-    .RXDFE_GC_CFG2 (16'b0000000000000000),
-    .RXDFE_H2_CFG0 (16'b0000000000000000),
-    .RXDFE_H2_CFG1 (16'b0000000000000000),
-    .RXDFE_H3_CFG0 (16'b0100000000000000),
-    .RXDFE_H3_CFG1 (16'b0000000000000000),
-    .RXDFE_H4_CFG0 (16'b0010000000000000),
-    .RXDFE_H4_CFG1 (16'b0000000000000011),
-    .RXDFE_H5_CFG0 (16'b0010000000000000),
-    .RXDFE_H5_CFG1 (16'b0000000000000011),
-    .RXDFE_H6_CFG0 (16'b0010000000000000),
-    .RXDFE_H6_CFG1 (16'b0000000000000000),
-    .RXDFE_H7_CFG0 (16'b0010000000000000),
-    .RXDFE_H7_CFG1 (16'b0000000000000000),
-    .RXDFE_H8_CFG0 (16'b0010000000000000),
-    .RXDFE_H8_CFG1 (16'b0000000000000000),
-    .RXDFE_H9_CFG0 (16'b0010000000000000),
-    .RXDFE_H9_CFG1 (16'b0000000000000000),
-    .RXDFE_HA_CFG0 (16'b0010000000000000),
-    .RXDFE_HA_CFG1 (16'b0000000000000000),
-    .RXDFE_HB_CFG0 (16'b0010000000000000),
-    .RXDFE_HB_CFG1 (16'b0000000000000000),
-    .RXDFE_HC_CFG0 (16'b0000000000000000),
-    .RXDFE_HC_CFG1 (16'b0000000000000000),
-    .RXDFE_HD_CFG0 (16'b0000000000000000),
-    .RXDFE_HD_CFG1 (16'b0000000000000000),
-    .RXDFE_HE_CFG0 (16'b0000000000000000),
-    .RXDFE_HE_CFG1 (16'b0000000000000000),
-    .RXDFE_HF_CFG0 (16'b0000000000000000),
-    .RXDFE_HF_CFG1 (16'b0000000000000000),
-    .RXDFE_OS_CFG0 (16'b1000000000000000),
-    .RXDFE_OS_CFG1 (16'b0000000000000000),
-    .RXDFE_UT_CFG0 (16'b1000000000000000),
-    .RXDFE_UT_CFG1 (16'b0000000000000011),
-    .RXDFE_VP_CFG0 (16'b1010101000000000),
-    .RXDFE_VP_CFG1 (16'b0000000000110011),
-    .RXDLY_CFG (16'b0000000000011111),
-    .RXDLY_LCFG (16'b0000000000110000),
+    .RXDFELPM_KL_CFG0 (16'h0000),
+    .RXDFELPM_KL_CFG1 (16'h0032),
+    .RXDFELPM_KL_CFG2 (16'h0000),
+    .RXDFE_CFG0 (16'h0a00),
+    .RXDFE_CFG1 (16'h0000),
+    .RXDFE_GC_CFG0 (16'h0000),
+    .RXDFE_GC_CFG1 (16'h7870),
+    .RXDFE_GC_CFG2 (16'h0000),
+    .RXDFE_H2_CFG0 (16'h0000),
+    .RXDFE_H2_CFG1 (16'h0000),
+    .RXDFE_H3_CFG0 (16'h4000),
+    .RXDFE_H3_CFG1 (16'h0000),
+    .RXDFE_H4_CFG0 (16'h2000),
+    .RXDFE_H4_CFG1 (16'h0003),
+    .RXDFE_H5_CFG0 (16'h2000),
+    .RXDFE_H5_CFG1 (16'h0003),
+    .RXDFE_H6_CFG0 (16'h2000),
+    .RXDFE_H6_CFG1 (16'h0000),
+    .RXDFE_H7_CFG0 (16'h2000),
+    .RXDFE_H7_CFG1 (16'h0000),
+    .RXDFE_H8_CFG0 (16'h2000),
+    .RXDFE_H8_CFG1 (16'h0000),
+    .RXDFE_H9_CFG0 (16'h2000),
+    .RXDFE_H9_CFG1 (16'h0000),
+    .RXDFE_HA_CFG0 (16'h2000),
+    .RXDFE_HA_CFG1 (16'h0000),
+    .RXDFE_HB_CFG0 (16'h2000),
+    .RXDFE_HB_CFG1 (16'h0000),
+    .RXDFE_HC_CFG0 (16'h0000),
+    .RXDFE_HC_CFG1 (16'h0000),
+    .RXDFE_HD_CFG0 (16'h0000),
+    .RXDFE_HD_CFG1 (16'h0000),
+    .RXDFE_HE_CFG0 (16'h0000),
+    .RXDFE_HE_CFG1 (16'h0000),
+    .RXDFE_HF_CFG0 (16'h0000),
+    .RXDFE_HF_CFG1 (16'h0000),
+    .RXDFE_OS_CFG0 (16'h8000),
+    .RXDFE_OS_CFG1 (16'h0000),
+    .RXDFE_UT_CFG0 (16'h8000),
+    .RXDFE_UT_CFG1 (16'h0003),
+    .RXDFE_VP_CFG0 (16'haa00),
+    .RXDFE_VP_CFG1 (16'h0033),
+    .RXDLY_CFG (16'h001f),
+    .RXDLY_LCFG (16'h0030),
     .RXELECIDLE_CFG ("Sigcfg_4"),
     .RXGBOX_FIFO_INIT_RD_ADDR (4),
     .RXGEARBOX_EN ("FALSE"),
     .RXISCANRESET_TIME (5'b00001),
-    .RXLPM_CFG (16'b0000000000000000),
-    .RXLPM_GC_CFG (16'b0000000000000000),
-    .RXLPM_KH_CFG0 (16'b0000000000000000),
-    .RXLPM_KH_CFG1 (16'b0000000000000010),
-    .RXLPM_OS_CFG0 (16'b1000000000000000),
-    .RXLPM_OS_CFG1 (16'b0000000000000010),
+    .RXLPM_CFG (16'h0000),
+    .RXLPM_GC_CFG (16'h1000),
+    .RXLPM_KH_CFG0 (16'h0000),
+    .RXLPM_KH_CFG1 (16'h0002),
+    .RXLPM_OS_CFG0 (16'h8000),
+    .RXLPM_OS_CFG1 (16'h0002),
     .RXOOB_CFG (9'b000000110),
     .RXOOB_CLK_CFG ("PMA"),
     .RXOSCALRESET_TIME (5'b00011),
     .RXOUT_DIV (RX_OUT_DIV),
     .RXPCSRESET_TIME (5'b00011),
-    .RXPHBEACON_CFG (16'b0000000000000000),
-    .RXPHDLY_CFG (16'b0010000000100000),
-    .RXPHSAMP_CFG (16'b0010000100000000),
-    .RXPHSLIP_CFG (16'b0110011000100010),
+    .RXPHBEACON_CFG (16'h0000),
+    .RXPHDLY_CFG (16'h2020),
+    .RXPHSAMP_CFG (16'h2100),
+    .RXPHSLIP_CFG (16'h6622),
     .RXPH_MONITOR_SEL (5'b00000),
-    .RXPI_CFG0 (2'b00),
-    .RXPI_CFG1 (2'b00),
-    .RXPI_CFG2 (2'b00),
-    .RXPI_CFG3 (2'b00),
+    .RXPI_CFG0 (2'b01),
+    .RXPI_CFG1 (2'b01),
+    .RXPI_CFG2 (2'b01),
+    .RXPI_CFG3 (2'b01),
     .RXPI_CFG4 (1'b0),
     .RXPI_CFG5 (1'b1),
-    .RXPI_CFG6 (3'b000),
+    .RXPI_CFG6 (3'b011),
     .RXPI_LPM (1'b0),
     .RXPI_VREFSEL (1'b0),
     .RXPMACLK_SEL ("DATA"),
@@ -1002,7 +1002,7 @@ module util_adxcvr_xch #(
     .RXSYNC_OVRD (1'b0),
     .RXSYNC_SKIP_DA (1'b0),
     .RX_AFE_CM_EN (1'b0),
-    .RX_BIAS_CFG0 (16'b0000101010110100),
+    .RX_BIAS_CFG0 (16'h0ab4),
     .RX_BUFFER_CFG (6'b000000),
     .RX_CAPFF_SARC_ENB (1'b0),
     .RX_CLK25_DIV (RX_CLK25_DIV),
@@ -1020,11 +1020,11 @@ module util_adxcvr_xch #(
     .RX_DFELPM_CFG1 (1'b1),
     .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
     .RX_DFE_AGC_CFG0 (2'b10),
-    .RX_DFE_AGC_CFG1 (3'b100),
+    .RX_DFE_AGC_CFG1 (3'b000),
     .RX_DFE_KL_LPM_KH_CFG0 (2'b01),
-    .RX_DFE_KL_LPM_KH_CFG1 (3'b100),
+    .RX_DFE_KL_LPM_KH_CFG1 (3'b000),
     .RX_DFE_KL_LPM_KL_CFG0 (2'b01),
-    .RX_DFE_KL_LPM_KL_CFG1 (3'b100),
+    .RX_DFE_KL_LPM_KL_CFG1 (3'b000),
     .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
     .RX_DISPERR_SEQ_MATCH ("TRUE"),
     .RX_DIVRESET_TIME (5'b00001),
@@ -1034,14 +1034,14 @@ module util_adxcvr_xch #(
     .RX_EYESCAN_VS_RANGE (2'b00),
     .RX_EYESCAN_VS_UT_SIGN (1'b0),
     .RX_FABINT_USRCLK_FLOP (1'b0),
-    .RX_INT_DATAWIDTH (1'h1),
+    .RX_INT_DATAWIDTH (1),
     .RX_PMA_POWER_SAVE (1'b0),
-    .RX_PROGDIV_CFG (20.0),
-    .RX_SAMPLE_PERIOD (3'b101),
+    .RX_PROGDIV_CFG (0.000000),
+    .RX_SAMPLE_PERIOD (3'b111),
     .RX_SIG_VALID_DLY (11),
     .RX_SUM_DFETAPREP_EN (1'b0),
-    .RX_SUM_IREF_TUNE (4'b0000),
-    .RX_SUM_RES_CTRL (2'b00),
+    .RX_SUM_IREF_TUNE (4'b1100),
+    .RX_SUM_RES_CTRL (2'b11),
     .RX_SUM_VCMTUNE (4'b0000),
     .RX_SUM_VCM_OVWR (1'b0),
     .RX_SUM_VREF_TUNE (3'b000),
@@ -1050,7 +1050,7 @@ module util_adxcvr_xch #(
     .RX_XCLK_SEL ("RXDES"),
     .SAS_MAX_COM (64),
     .SAS_MIN_COM (36),
-    .SATA_BURST_SEQ_LEN (4'b1111),
+    .SATA_BURST_SEQ_LEN (4'b1110),
     .SATA_BURST_VAL (3'b100),
     .SATA_CPLL_CFG ("VCO_3000MHZ"),
     .SATA_EIDLE_VAL (3'b100),
@@ -1061,21 +1061,22 @@ module util_adxcvr_xch #(
     .SATA_MIN_INIT (12),
     .SATA_MIN_WAKE (4),
     .SHOW_REALIGN_COMMA ("TRUE"),
+    .SIM_MODE ("FAST"),
     .SIM_RECEIVER_DETECT_PASS ("TRUE"),
     .SIM_RESET_SPEEDUP ("TRUE"),
     .SIM_TX_EIDLE_DRIVE_LEVEL (1'b0),
     .SIM_VERSION (2),
-    .TAPDLY_SET_TX (2'b00),
+    .TAPDLY_SET_TX (2'h0),
     .TEMPERATUR_PAR (4'b0010),
     .TERM_RCAL_CFG (15'b100001000010000),
     .TERM_RCAL_OVRD (3'b000),
-    .TRANS_TIME_RATE (8'b00001110),
-    .TST_RSV0 (8'b00000000),
-    .TST_RSV1 (8'b00000000),
+    .TRANS_TIME_RATE (8'h0e),
+    .TST_RSV0 (8'h00),
+    .TST_RSV1 (8'h00),
     .TXBUF_EN ("TRUE"),
     .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
-    .TXDLY_CFG (16'b0000000000001001),
-    .TXDLY_LCFG (16'b0000000001010000),
+    .TXDLY_CFG (16'h0009),
+    .TXDLY_LCFG (16'h0050),
     .TXDRVBIAS_N (4'b1010),
     .TXDRVBIAS_P (4'b1010),
     .TXFIFO_ADDR_CFG ("LOW"),
@@ -1083,22 +1084,22 @@ module util_adxcvr_xch #(
     .TXGEARBOX_EN ("FALSE"),
     .TXOUT_DIV (TX_OUT_DIV),
     .TXPCSRESET_TIME (5'b00011),
-    .TXPHDLY_CFG0 (16'b0010000000100000),
-    .TXPHDLY_CFG1 (16'b0000000011010101),
-    .TXPH_CFG (16'b0000100110000000),
+    .TXPHDLY_CFG0 (16'h2020),
+    .TXPHDLY_CFG1 (16'h0075),
+    .TXPH_CFG (16'h0980),
     .TXPH_MONITOR_SEL (5'b00000),
-    .TXPI_CFG0 (2'b00),
-    .TXPI_CFG1 (2'b00),
-    .TXPI_CFG2 (2'b00),
+    .TXPI_CFG0 (2'b01),
+    .TXPI_CFG1 (2'b01),
+    .TXPI_CFG2 (2'b01),
     .TXPI_CFG3 (1'b0),
     .TXPI_CFG4 (1'b1),
-    .TXPI_CFG5 (3'b000),
+    .TXPI_CFG5 (3'b011),
     .TXPI_GRAY_SEL (1'b0),
     .TXPI_INVSTROBE_SEL (1'b0),
     .TXPI_LPM (1'b0),
     .TXPI_PPMCLK_SEL ("TXUSRCLK2"),
     .TXPI_PPM_CFG (8'b00000000),
-    .TXPI_SYNFREQ_PPM (3'b000),
+    .TXPI_SYNFREQ_PPM (3'b001),
     .TXPI_VREFSEL (1'b0),
     .TXPMARESET_TIME (5'b00011),
     .TXSYNC_MULTILANE (1'b1),
@@ -1118,7 +1119,7 @@ module util_adxcvr_xch #(
     .TX_EML_PHI_TUNE (1'b0),
     .TX_FABINT_USRCLK_FLOP (1'b0),
     .TX_IDLE_DATA_ZERO (1'b0),
-    .TX_INT_DATAWIDTH (1'h1),
+    .TX_INT_DATAWIDTH (1),
     .TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
     .TX_MAINCURSOR_SEL (1'b0),
     .TX_MARGIN_FULL_0 (7'b1001111),
@@ -1135,288 +1136,122 @@ module util_adxcvr_xch #(
     .TX_PMADATA_OPT (1'b0),
     .TX_PMA_POWER_SAVE (1'b0),
     .TX_PROGCLK_SEL ("PREPI"),
-    .TX_PROGDIV_CFG (20.0),
+    .TX_PROGDIV_CFG (0.000000),
     .TX_QPI_STATUS_EN (1'b0),
-    .TX_RXDETECT_CFG (14'b00000000110010),
+    .TX_RXDETECT_CFG (14'h0032),
     .TX_RXDETECT_REF (3'b100),
-    .TX_SAMPLE_PERIOD (3'b101),
+    .TX_SAMPLE_PERIOD (3'b111),
     .TX_SARC_LPBK_ENB (1'b0),
     .TX_XCLK_SEL ("TXOUT"),
     .USE_PCS_CLK_PHASE_SEL (1'b0),
     .WB_MODE (2'b00))
   i_gthe3_channel (
-    .CFGRESET (1'd0),
-    .CLKRSVD0 (1'd0),
-    .CLKRSVD1 (1'd0),
-    .CPLLLOCKDETCLK (up_clk),
-    .CPLLLOCKEN (1'd1),
-    .CPLLPD (1'b0),
-    .CPLLREFCLKSEL (3'b001),
-    .CPLLRESET (up_cpll_rst),
-    .DMONFIFORESET (1'd0),
-    .DMONITORCLK (1'd0),
-    .DRPADDR (up_addr_int[8:0]),
-    .DRPCLK (up_clk),
-    .DRPDI (up_wdata_int),
-    .DRPEN (up_enb_int),
-    .DRPWE (up_wr_int),
-    .EVODDPHICALDONE (1'd0),
-    .EVODDPHICALSTART (1'd0),
-    .EVODDPHIDRDEN (1'd0),
-    .EVODDPHIDWREN (1'd0),
-    .EVODDPHIXRDEN (1'd0),
-    .EVODDPHIXWREN (1'd0),
-    .EYESCANMODE (1'd0),
-    .EYESCANRESET (1'd0),
-    .EYESCANTRIGGER (1'd0),
-    .GTGREFCLK (1'd0),
-    .GTHRXN (rx_n),
-    .GTHRXP (rx_p),
-    .GTNORTHREFCLK0 (1'd0),
-    .GTNORTHREFCLK1 (1'd0),
-    .GTREFCLK0 (cpll_ref_clk),
-    .GTREFCLK1 (1'd0),
-    .GTRESETSEL (1'd0),
-    .GTRSVD (15'd0),
-    .GTRXRESET (up_rx_rst),
-    .GTSOUTHREFCLK0 (1'd0),
-    .GTSOUTHREFCLK1 (1'd0),
-    .GTTXRESET (up_tx_rst),
-    .LOOPBACK (3'd0),
-    .LPBKRXTXSEREN (1'd0),
-    .LPBKTXRXSEREN (1'd0),
-    .PCIEEQRXEQADAPTDONE (1'd0),
-    .PCIERSTIDLE (1'd0),
-    .PCIERSTTXSYNCSTART (1'd0),
-    .PCIEUSERRATEDONE (1'd0),
-    .PCSRSVDIN (16'd0),
-    .PCSRSVDIN2 (5'd0),
-    .PMARSVDIN (5'd0),
-    .QPLL0CLK (qpll2ch_clk),
-    .QPLL0REFCLK (qpll2ch_ref_clk),
-    .QPLL1CLK (1'd0),
-    .QPLL1REFCLK (1'd0),
-    .RESETOVRD (1'd0),
-    .RSTCLKENTX (1'd0),
-    .RXBUFRESET (1'd0),
-    .RXCDRFREQRESET (1'd0),
-    .RXCDRHOLD (1'd0),
-    .RXCDROVRDEN (1'd0),
-    .RXCDRRESET (1'd0),
-    .RXCDRRESETRSV (1'd0),
-    .RXCHBONDEN (1'd0),
-    .RXCHBONDI (5'd0),
-    .RXCHBONDLEVEL (2'd0),
-    .RXCHBONDMASTER (1'd0),
-    .RXCHBONDSLAVE (1'd0),
-    .RXCOMMADETEN (1'd1),
-    .RXDFEAGCCTRL (2'b01),
-    .RXDFEAGCHOLD (1'd0),
-    .RXDFEAGCOVRDEN (1'd0),
-    .RXDFELFHOLD (1'd0),
-    .RXDFELFOVRDEN (1'd0),
-    .RXDFELPMRESET (1'd0),
-    .RXDFETAP10HOLD (1'd0),
-    .RXDFETAP10OVRDEN (1'd0),
-    .RXDFETAP11HOLD (1'd0),
-    .RXDFETAP11OVRDEN (1'd0),
-    .RXDFETAP12HOLD (1'd0),
-    .RXDFETAP12OVRDEN (1'd0),
-    .RXDFETAP13HOLD (1'd0),
-    .RXDFETAP13OVRDEN (1'd0),
-    .RXDFETAP14HOLD (1'd0),
-    .RXDFETAP14OVRDEN (1'd0),
-    .RXDFETAP15HOLD (1'd0),
-    .RXDFETAP15OVRDEN (1'd0),
-    .RXDFETAP2HOLD (1'd0),
-    .RXDFETAP2OVRDEN (1'd0),
-    .RXDFETAP3HOLD (1'd0),
-    .RXDFETAP3OVRDEN (1'd0),
-    .RXDFETAP4HOLD (1'd0),
-    .RXDFETAP4OVRDEN (1'd0),
-    .RXDFETAP5HOLD (1'd0),
-    .RXDFETAP5OVRDEN (1'd0),
-    .RXDFETAP6HOLD (1'd0),
-    .RXDFETAP6OVRDEN (1'd0),
-    .RXDFETAP7HOLD (1'd0),
-    .RXDFETAP7OVRDEN (1'd0),
-    .RXDFETAP8HOLD (1'd0),
-    .RXDFETAP8OVRDEN (1'd0),
-    .RXDFETAP9HOLD (1'd0),
-    .RXDFETAP9OVRDEN (1'd0),
-    .RXDFEUTHOLD (1'd0),
-    .RXDFEUTOVRDEN (1'd0),
-    .RXDFEVPHOLD (1'd0),
-    .RXDFEVPOVRDEN (1'd0),
-    .RXDFEVSEN (1'd0),
-    .RXDFEXYDEN (1'd1),
-    .RXDLYBYPASS (1'd1),
-    .RXDLYEN (1'd0),
-    .RXDLYOVRDEN (1'd0),
-    .RXDLYSRESET (1'd0),
-    .RXELECIDLEMODE (2'b11),
-    .RXGEARBOXSLIP (1'd0),
-    .RXLATCLK (1'd0),
-    .RXLPMEN (up_rx_lpm_dfe_n),
-    .RXLPMGCHOLD (1'd0),
-    .RXLPMGCOVRDEN (1'd0),
-    .RXLPMHFHOLD (1'd0),
-    .RXLPMHFOVRDEN (1'd0),
-    .RXLPMLFHOLD (1'd0),
-    .RXLPMLFKLOVRDEN (1'd0),
-    .RXLPMOSHOLD (1'd0),
-    .RXLPMOSOVRDEN (1'd0),
-    .RXMCOMMAALIGNEN (rx_calign),
-    .RXMONITORSEL (2'd0),
-    .RXOOBRESET (1'd0),
-    .RXOSCALRESET (1'd0),
-    .RXOSHOLD (1'd0),
-    .RXOSINTCFG (4'b1101),
-    .RXOSINTEN (1'd1),
-    .RXOSINTHOLD (1'd0),
-    .RXOSINTOVRDEN (1'd0),
-    .RXOSINTSTROBE (1'd0),
-    .RXOSINTTESTOVRDEN (1'd0),
-    .RXOSOVRDEN (1'd0),
-    .RXOUTCLKSEL (up_rx_out_clk_sel),
-    .RXPCOMMAALIGNEN (rx_calign),
-    .RXPCSRESET (1'd0),
-    .RXPD (2'd0),
-    .RXPHALIGN (1'd0),
-    .RXPHALIGNEN (1'd0),
-    .RXPHDLYPD (1'd1),
-    .RXPHDLYRESET (1'd0),
-    .RXPHOVRDEN (1'd0),
-    .RXPLLCLKSEL (rx_pll_clk_sel_s),
-    .RXPMARESET (1'd0),
-    .RXPOLARITY (1'd0),
-    .RXPRBSCNTRESET (1'd0),
-    .RXPRBSSEL (4'd0),
-    .RXPROGDIVRESET (1'd0),
-    .RXQPIEN (1'd0),
-    .RXRATE (rx_rate_m2),
-    .RXRATEMODE (1'd0),
-    .RXSLIDE (1'd0),
-    .RXSLIPOUTCLK (1'd0),
-    .RXSLIPPMA (1'd0),
-    .RXSYNCALLIN (1'd0),
-    .RXSYNCIN (1'd0),
-    .RXSYNCMODE (1'd0),
-    .RXSYSCLKSEL (rx_sys_clk_sel_s),
-    .RXUSERRDY (up_rx_user_ready),
-    .RXUSRCLK (rx_clk),
-    .RXUSRCLK2 (rx_clk),
-    .RX8B10BEN (1'd1),
-    .SIGVALIDCLK (1'd0),
-    .TSTIN (20'd0),
-    .TXBUFDIFFCTRL (3'd0),
-    .TXCOMINIT (1'd0),
-    .TXCOMSAS (1'd0),
-    .TXCOMWAKE (1'd0),
-    .TXCTRL0 (16'd0),
-    .TXCTRL1 (16'd0),
-    .TXCTRL2 ({4'd0, tx_charisk}),
-    .TXDATA ({96'd0, tx_data}),
-    .TXDATAEXTENDRSVD (8'd0),
-    .TXDEEMPH (1'd0),
-    .TXDETECTRX (1'd0),
-    .TXDIFFCTRL (4'b1100),
-    .TXDIFFPD (1'd0),
-    .TXDLYBYPASS (1'd1),
-    .TXDLYEN (1'd0),
-    .TXDLYHOLD (1'd0),
-    .TXDLYOVRDEN (1'd0),
-    .TXDLYSRESET (1'd0),
-    .TXDLYUPDOWN (1'd0),
-    .TXELECIDLE (1'd0),
-    .TXHEADER (6'd0),
-    .TXINHIBIT (1'd0),
-    .TXLATCLK (1'd0),
-    .TXMAINCURSOR (7'b1000000),
-    .TXMARGIN (3'd0),
-    .TXOUTCLKSEL (up_tx_out_clk_sel),
-    .TXPCSRESET (1'd0),
-    .TXPD (2'd0),
-    .TXPDELECIDLEMODE (1'd0),
-    .TXPHALIGN (1'd0),
-    .TXPHALIGNEN (1'd0),
-    .TXPHDLYPD (1'd1),
-    .TXPHDLYRESET (1'd0),
-    .TXPHDLYTSTCLK (1'd0),
-    .TXPHINIT (1'd0),
-    .TXPHOVRDEN (1'd0),
-    .TXPIPPMEN (1'd0),
-    .TXPIPPMOVRDEN (1'd0),
-    .TXPIPPMPD (1'd0),
-    .TXPIPPMSEL (1'd0),
-    .TXPIPPMSTEPSIZE (5'd0),
-    .TXPISOPD (1'd0),
-    .TXPLLCLKSEL (tx_pll_clk_sel_s),
-    .TXPMARESET (1'd0),
-    .TXPOLARITY (1'd0),
-    .TXPOSTCURSOR (5'd0),
-    .TXPOSTCURSORINV (1'd0),
-    .TXPRBSFORCEERR (1'd0),
-    .TXPRBSSEL (4'd0),
-    .TXPRECURSOR (5'd0),
-    .TXPRECURSORINV (1'd0),
-    .TXPROGDIVRESET (up_tx_rst),
-    .TXQPIBIASEN (1'd0),
-    .TXQPISTRONGPDOWN (1'd0),
-    .TXQPIWEAKPUP (1'd0),
-    .TXRATE (tx_rate_m2),
-    .TXRATEMODE (1'd0),
-    .TXSEQUENCE (7'd0),
-    .TXSWING (1'd0),
-    .TXSYNCALLIN (1'd0),
-    .TXSYNCIN (1'd0),
-    .TXSYNCMODE (1'd0),
-    .TXSYSCLKSEL (tx_sys_clk_sel_s),
-    .TXUSERRDY (up_tx_user_ready),
-    .TXUSRCLK (tx_clk),
-    .TXUSRCLK2 (tx_clk),
-    .TX8B10BBYPASS (8'd0),
-    .TX8B10BEN (1'd1),
     .BUFGTCE (),
     .BUFGTCEMASK (),
     .BUFGTDIV (),
     .BUFGTRESET (),
     .BUFGTRSTMASK (),
+    .CFGRESET (1'h0),
+    .CLKRSVD0 (1'h0),
+    .CLKRSVD1 (1'h0),
     .CPLLFBCLKLOST (),
     .CPLLLOCK (cpll_locked_s),
+    .CPLLLOCKDETCLK (up_clk),
+    .CPLLLOCKEN (1'h1),
+    .CPLLPD (1'h0),
     .CPLLREFCLKLOST (),
+    .CPLLREFCLKSEL (3'h1),
+    .CPLLRESET (up_cpll_rst),
+    .DMONFIFORESET (1'h0),
+    .DMONITORCLK (1'h0),
     .DMONITOROUT (),
+    .DRPADDR (up_addr_int[8:0]),
+    .DRPCLK (up_clk),
+    .DRPDI (up_wdata_int),
     .DRPDO (up_rdata_s),
+    .DRPEN (up_enb_int),
     .DRPRDY (up_ready_s),
+    .DRPWE (up_wr_int),
+    .EVODDPHICALDONE (1'h0),
+    .EVODDPHICALSTART (1'h0),
+    .EVODDPHIDRDEN (1'h0),
+    .EVODDPHIDWREN (1'h0),
+    .EVODDPHIXRDEN (1'h0),
+    .EVODDPHIXWREN (1'h0),
     .EYESCANDATAERROR (),
+    .EYESCANMODE (1'h0),
+    .EYESCANRESET (1'h0),
+    .EYESCANTRIGGER (1'h0),
+    .GTGREFCLK (1'h0),
+    .GTHRXN (rx_n),
+    .GTHRXP (rx_p),
     .GTHTXN (tx_n),
     .GTHTXP (tx_p),
+    .GTNORTHREFCLK0 (1'h0),
+    .GTNORTHREFCLK1 (1'h0),
     .GTPOWERGOOD (),
+    .GTREFCLK0 (cpll_ref_clk),
+    .GTREFCLK1 (1'h0),
     .GTREFCLKMONITOR (),
+    .GTRESETSEL (1'h0),
+    .GTRSVD (16'h0),
+    .GTRXRESET (up_rx_rst),
+    .GTSOUTHREFCLK0 (1'h0),
+    .GTSOUTHREFCLK1 (1'h0),
+    .GTTXRESET (up_tx_rst),
+    .LOOPBACK (3'h0),
+    .LPBKRXTXSEREN (1'h0),
+    .LPBKTXRXSEREN (1'h0),
+    .PCIEEQRXEQADAPTDONE (1'h0),
     .PCIERATEGEN3 (),
     .PCIERATEIDLE (),
     .PCIERATEQPLLPD (),
     .PCIERATEQPLLRESET (),
+    .PCIERSTIDLE (1'h0),
+    .PCIERSTTXSYNCSTART (1'h0),
     .PCIESYNCTXSYNCDONE (),
     .PCIEUSERGEN3RDY (),
     .PCIEUSERPHYSTATUSRST (),
+    .PCIEUSERRATEDONE (1'h0),
     .PCIEUSERRATESTART (),
+    .PCSRSVDIN (16'h0),
+    .PCSRSVDIN2 (5'h0),
     .PCSRSVDOUT (),
     .PHYSTATUS (),
     .PINRSRVDAS (),
+    .PMARSVDIN (5'h0),
+    .QPLL0CLK (qpll2ch_clk),
+    .QPLL0REFCLK (qpll2ch_ref_clk),
+    .QPLL1CLK (1'h0),
+    .QPLL1REFCLK (1'h0),
     .RESETEXCEPTION (),
+    .RESETOVRD (1'h0),
+    .RSTCLKENTX (1'h0),
+    .RX8B10BEN (1'h1),
+    .RXBUFRESET (1'h0),
     .RXBUFSTATUS (),
     .RXBYTEISALIGNED (),
     .RXBYTEREALIGN (),
+    .RXCDRFREQRESET (1'h0),
+    .RXCDRHOLD (1'h0),
     .RXCDRLOCK (),
+    .RXCDROVRDEN (1'h0),
     .RXCDRPHDONE (),
+    .RXCDRRESET (1'h0),
+    .RXCDRRESETRSV (1'h0),
     .RXCHANBONDSEQ (),
     .RXCHANISALIGNED (),
     .RXCHANREALIGN (),
+    .RXCHBONDEN (1'h0),
+    .RXCHBONDI (5'h0),
+    .RXCHBONDLEVEL (3'h0),
+    .RXCHBONDMASTER (1'h0),
     .RXCHBONDO (),
+    .RXCHBONDSLAVE (1'h0),
     .RXCLKCORCNT (),
     .RXCOMINITDET (),
     .RXCOMMADET (),
+    .RXCOMMADETEN (1'h1),
     .RXCOMSASDET (),
     .RXCOMWAKEDET (),
     .RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
@@ -1426,54 +1261,220 @@ module util_adxcvr_xch #(
     .RXDATA ({rx_data_open_s, rx_data}),
     .RXDATAEXTENDRSVD (),
     .RXDATAVALID (),
+    .RXDFEAGCCTRL (2'h1),
+    .RXDFEAGCHOLD (1'h0),
+    .RXDFEAGCOVRDEN (1'h0),
+    .RXDFELFHOLD (1'h0),
+    .RXDFELFOVRDEN (1'h0),
+    .RXDFELPMRESET (1'h0),
+    .RXDFETAP10HOLD (1'h0),
+    .RXDFETAP10OVRDEN (1'h0),
+    .RXDFETAP11HOLD (1'h0),
+    .RXDFETAP11OVRDEN (1'h0),
+    .RXDFETAP12HOLD (1'h0),
+    .RXDFETAP12OVRDEN (1'h0),
+    .RXDFETAP13HOLD (1'h0),
+    .RXDFETAP13OVRDEN (1'h0),
+    .RXDFETAP14HOLD (1'h0),
+    .RXDFETAP14OVRDEN (1'h0),
+    .RXDFETAP15HOLD (1'h0),
+    .RXDFETAP15OVRDEN (1'h0),
+    .RXDFETAP2HOLD (1'h0),
+    .RXDFETAP2OVRDEN (1'h0),
+    .RXDFETAP3HOLD (1'h0),
+    .RXDFETAP3OVRDEN (1'h0),
+    .RXDFETAP4HOLD (1'h0),
+    .RXDFETAP4OVRDEN (1'h0),
+    .RXDFETAP5HOLD (1'h0),
+    .RXDFETAP5OVRDEN (1'h0),
+    .RXDFETAP6HOLD (1'h0),
+    .RXDFETAP6OVRDEN (1'h0),
+    .RXDFETAP7HOLD (1'h0),
+    .RXDFETAP7OVRDEN (1'h0),
+    .RXDFETAP8HOLD (1'h0),
+    .RXDFETAP8OVRDEN (1'h0),
+    .RXDFETAP9HOLD (1'h0),
+    .RXDFETAP9OVRDEN (1'h0),
+    .RXDFEUTHOLD (1'h0),
+    .RXDFEUTOVRDEN (1'h0),
+    .RXDFEVPHOLD (1'h0),
+    .RXDFEVPOVRDEN (1'h0),
+    .RXDFEVSEN (1'h0),
+    .RXDFEXYDEN (1'h1),
+    .RXDLYBYPASS (1'h1),
+    .RXDLYEN (1'h0),
+    .RXDLYOVRDEN (1'h0),
+    .RXDLYSRESET (1'h0),
     .RXDLYSRESETDONE (),
     .RXELECIDLE (),
+    .RXELECIDLEMODE (2'h3),
+    .RXGEARBOXSLIP (1'h0),
     .RXHEADER (),
     .RXHEADERVALID (),
+    .RXLATCLK (1'h0),
+    .RXLPMEN (up_rx_lpm_dfe_n),
+    .RXLPMGCHOLD (1'h0),
+    .RXLPMGCOVRDEN (1'h0),
+    .RXLPMHFHOLD (1'h0),
+    .RXLPMHFOVRDEN (1'h0),
+    .RXLPMLFHOLD (1'h0),
+    .RXLPMLFKLOVRDEN (1'h0),
+    .RXLPMOSHOLD (1'h0),
+    .RXLPMOSOVRDEN (1'h0),
+    .RXMCOMMAALIGNEN (rx_calign),
     .RXMONITOROUT (),
+    .RXMONITORSEL (2'h0),
+    .RXOOBRESET (1'h0),
+    .RXOSCALRESET (1'h0),
+    .RXOSHOLD (1'h0),
+    .RXOSINTCFG (4'hd),
     .RXOSINTDONE (),
+    .RXOSINTEN (1'h1),
+    .RXOSINTHOLD (1'h0),
+    .RXOSINTOVRDEN (1'h0),
     .RXOSINTSTARTED (),
+    .RXOSINTSTROBE (1'h0),
     .RXOSINTSTROBEDONE (),
     .RXOSINTSTROBESTARTED (),
+    .RXOSINTTESTOVRDEN (1'h0),
+    .RXOSOVRDEN (1'h0),
     .RXOUTCLK (rx_out_clk_s),
     .RXOUTCLKFABRIC (),
     .RXOUTCLKPCS (),
+    .RXOUTCLKSEL (up_rx_out_clk_sel),
+    .RXPCOMMAALIGNEN (rx_calign),
+    .RXPCSRESET (1'h0),
+    .RXPD (2'h0),
+    .RXPHALIGN (1'h0),
     .RXPHALIGNDONE (),
+    .RXPHALIGNEN (1'h0),
     .RXPHALIGNERR (),
+    .RXPHDLYPD (1'h1),
+    .RXPHDLYRESET (1'h0),
+    .RXPHOVRDEN (1'h0),
+    .RXPLLCLKSEL (rx_pll_clk_sel_s),
+    .RXPMARESET (1'h0),
     .RXPMARESETDONE (),
+    .RXPOLARITY (1'h0),
+    .RXPRBSCNTRESET (1'h0),
     .RXPRBSERR (),
     .RXPRBSLOCKED (),
+    .RXPRBSSEL (4'h0),
     .RXPRGDIVRESETDONE (),
+    .RXPROGDIVRESET (1'h0),
+    .RXQPIEN (1'h0),
     .RXQPISENN (),
     .RXQPISENP (),
+    .RXRATE (rx_rate_m2),
     .RXRATEDONE (),
+    .RXRATEMODE (1'h0),
     .RXRECCLKOUT (),
     .RXRESETDONE (rx_rst_done_s),
+    .RXSLIDE (1'h0),
     .RXSLIDERDY (),
     .RXSLIPDONE (),
+    .RXSLIPOUTCLK (1'h0),
     .RXSLIPOUTCLKRDY (),
+    .RXSLIPPMA (1'h0),
     .RXSLIPPMARDY (),
     .RXSTARTOFSEQ (),
     .RXSTATUS (),
+    .RXSYNCALLIN (1'h0),
     .RXSYNCDONE (),
+    .RXSYNCIN (1'h0),
+    .RXSYNCMODE (1'h0),
     .RXSYNCOUT (),
+    .RXSYSCLKSEL (rx_sys_clk_sel_s),
+    .RXUSERRDY (up_rx_user_ready),
+    .RXUSRCLK (rx_clk),
+    .RXUSRCLK2 (rx_clk),
     .RXVALID (),
+    .SIGVALIDCLK (1'h0),
+    .TSTIN (20'h0),
+    .TX8B10BBYPASS (8'h0),
+    .TX8B10BEN (1'h1),
+    .TXBUFDIFFCTRL (3'h0),
     .TXBUFSTATUS (),
     .TXCOMFINISH (),
+    .TXCOMINIT (1'h0),
+    .TXCOMSAS (1'h0),
+    .TXCOMWAKE (1'h0),
+    .TXCTRL0 (16'h0),
+    .TXCTRL1 (16'h0),
+    .TXCTRL2 ({4'd0, tx_charisk}),
+    .TXDATA ({96'd0, tx_data}),
+    .TXDATAEXTENDRSVD (8'h0),
+    .TXDEEMPH (1'h0),
+    .TXDETECTRX (1'h0),
+    .TXDIFFCTRL (4'h8),
+    .TXDIFFPD (1'h0),
+    .TXDLYBYPASS (1'h1),
+    .TXDLYEN (1'h0),
+    .TXDLYHOLD (1'h0),
+    .TXDLYOVRDEN (1'h0),
+    .TXDLYSRESET (1'h0),
     .TXDLYSRESETDONE (),
+    .TXDLYUPDOWN (1'h0),
+    .TXELECIDLE (1'h0),
+    .TXHEADER (6'h0),
+    .TXINHIBIT (1'h0),
+    .TXLATCLK (1'h0),
+    .TXMAINCURSOR (7'h40),
+    .TXMARGIN (3'h0),
     .TXOUTCLK (tx_out_clk_s),
     .TXOUTCLKFABRIC (),
     .TXOUTCLKPCS (),
+    .TXOUTCLKSEL (up_tx_out_clk_sel),
+    .TXPCSRESET (1'h0),
+    .TXPD (2'h0),
+    .TXPDELECIDLEMODE (1'h0),
+    .TXPHALIGN (1'h0),
     .TXPHALIGNDONE (),
+    .TXPHALIGNEN (1'h0),
+    .TXPHDLYPD (1'h1),
+    .TXPHDLYRESET (1'h0),
+    .TXPHDLYTSTCLK (1'h0),
+    .TXPHINIT (1'h0),
     .TXPHINITDONE (),
+    .TXPHOVRDEN (1'h0),
+    .TXPIPPMEN (1'h0),
+    .TXPIPPMOVRDEN (1'h0),
+    .TXPIPPMPD (1'h0),
+    .TXPIPPMSEL (1'h0),
+    .TXPIPPMSTEPSIZE (5'h0),
+    .TXPISOPD (1'h0),
+    .TXPLLCLKSEL (tx_pll_clk_sel_s),
+    .TXPMARESET (1'h0),
     .TXPMARESETDONE (),
+    .TXPOLARITY (1'h0),
+    .TXPOSTCURSOR (5'h0),
+    .TXPOSTCURSORINV (1'h0),
+    .TXPRBSFORCEERR (1'h0),
+    .TXPRBSSEL (4'h0),
+    .TXPRECURSOR (5'h0),
+    .TXPRECURSORINV (1'h0),
     .TXPRGDIVRESETDONE (),
+    .TXPROGDIVRESET (up_tx_rst),
+    .TXQPIBIASEN (1'h0),
     .TXQPISENN (),
     .TXQPISENP (),
+    .TXQPISTRONGPDOWN (1'h0),
+    .TXQPIWEAKPUP (1'h0),
+    .TXRATE (tx_rate_m2),
     .TXRATEDONE (),
+    .TXRATEMODE (1'h0),
     .TXRESETDONE (tx_rst_done_s),
+    .TXSEQUENCE (7'h0),
+    .TXSWING (1'h0),
+    .TXSYNCALLIN (1'h0),
     .TXSYNCDONE (),
-    .TXSYNCOUT ());
+    .TXSYNCIN (1'h0),
+    .TXSYNCMODE (1'h0),
+    .TXSYNCOUT (),
+    .TXSYSCLKSEL (tx_sys_clk_sel_s),
+    .TXUSERRDY (up_tx_user_ready),
+    .TXUSRCLK (tx_clk),
+    .TXUSRCLK2 (tx_clk));
   end
   endgenerate
 
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
index 6c65ec311..a13956ab7 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
@@ -180,141 +180,142 @@ module util_adxcvr_xcm #(
   generate
   if (XCVR_TYPE == 1) begin
   GTHE3_COMMON #(
-    .SIM_RESET_SPEEDUP ("TRUE"),
-    .SIM_VERSION (2),
-    .SARC_EN (1'b1),
-    .SARC_SEL (1'b0),
-    .SDM0_DATA_PIN_SEL (1'b0),
-    .SDM0_WIDTH_PIN_SEL (1'b0),
-    .SDM1_DATA_PIN_SEL (1'b0),
-    .SDM1_WIDTH_PIN_SEL (1'b0),
-    .BIAS_CFG0 (16'b0000000000000000),
-    .BIAS_CFG1 (16'b0000000000000000),
-    .BIAS_CFG2 (16'b0000000000000000),
-    .BIAS_CFG3 (16'b0000000001000000),
-    .BIAS_CFG4 (16'b0000000000000000),
-    .COMMON_CFG0 (16'b0000000000000000),
-    .COMMON_CFG1 (16'b0000000000000000),
-    .POR_CFG (16'b0000000000000100),
-    .QPLL0_CFG0 (16'b0011000000011100),
-    .QPLL0_CFG1 (16'b0000000000011000),
-    .QPLL0_CFG1_G3 (16'b0000000000011000),
-    .QPLL0_CFG2 (16'b0000000001001000),
-    .QPLL0_CFG2_G3 (16'b0000000001001000),
-    .QPLL0_CFG3 (16'b0000000100100000),
-    .QPLL0_CFG4 (16'b0000000000001001),
-    .QPLL0_INIT_CFG0 (16'b0000000000000000),
-    .QPLL0_LOCK_CFG (16'b0010010111101000),
-    .QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
+    .BIAS_CFG0 (16'h0000),
+    .BIAS_CFG1 (16'h0000),
+    .BIAS_CFG2 (16'h0000),
+    .BIAS_CFG3 (16'h0040),
+    .BIAS_CFG4 (16'h0000),
+    .BIAS_CFG_RSVD (10'b0000000000),
+    .COMMON_CFG0 (16'h0000),
+    .COMMON_CFG1 (16'h0000),
+    .POR_CFG (16'h0004),
+    .QPLL0_CFG0 (16'h321c),
+    .QPLL0_CFG1 (16'h1018),
+    .QPLL0_CFG1_G3 (16'h1018),
+    .QPLL0_CFG2 (16'h0048),
+    .QPLL0_CFG2_G3 (16'h0048),
+    .QPLL0_CFG3 (16'h0120),
+    .QPLL0_CFG4 (16'h0000),
+    .QPLL0_CP (10'b0000011111),
+    .QPLL0_CP_G3 (10'b1111111111),
+    .QPLL0_FBDIV (QPLL_FBDIV),
+    .QPLL0_FBDIV_G3 (80),
+    .QPLL0_INIT_CFG0 (16'h02b2),
+    .QPLL0_INIT_CFG1 (8'h00),
+    .QPLL0_LOCK_CFG (16'h21e8),
+    .QPLL0_LOCK_CFG_G3 (16'h21e8),
+    .QPLL0_LPF (10'b1111111111),
+    .QPLL0_LPF_G3 (10'b0000010101),
+    .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL0_SDM_CFG0 (16'b0000000000000000),
     .QPLL0_SDM_CFG1 (16'b0000000000000000),
     .QPLL0_SDM_CFG2 (16'b0000000000000000),
-    .QPLL1_CFG0 (16'b0011000000011100),
-    .QPLL1_CFG1 (16'b0000000000011000),
-    .QPLL1_CFG1_G3 (16'b0000000000011000),
-    .QPLL1_CFG2 (16'b0000000001000000),
-    .QPLL1_CFG2_G3 (16'b0000000001000000),
-    .QPLL1_CFG3 (16'b0000000100100000),
-    .QPLL1_CFG4 (16'b0000000000001001),
-    .QPLL1_INIT_CFG0 (16'b0000000000000000),
-    .QPLL1_LOCK_CFG (16'b0010010111101000),
-    .QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
+    .QPLL1_CFG0 (16'h321c),
+    .QPLL1_CFG1 (16'h1018),
+    .QPLL1_CFG1_G3 (16'h1018),
+    .QPLL1_CFG2 (16'h0040),
+    .QPLL1_CFG2_G3 (16'h0040),
+    .QPLL1_CFG3 (16'h0120),
+    .QPLL1_CFG4 (16'h0000),
+    .QPLL1_CP (10'b0000011111),
+    .QPLL1_CP_G3 (10'b1111111111),
+    .QPLL1_FBDIV (QPLL_FBDIV),
+    .QPLL1_FBDIV_G3 (80),
+    .QPLL1_INIT_CFG0 (16'h02b2),
+    .QPLL1_INIT_CFG1 (8'h00),
+    .QPLL1_LOCK_CFG (16'h21e8),
+    .QPLL1_LOCK_CFG_G3 (16'h21e8),
+    .QPLL1_LPF (10'b1111111111),
+    .QPLL1_LPF_G3 (10'b0000010101),
+    .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
     .QPLL1_SDM_CFG0 (16'b0000000000000000),
     .QPLL1_SDM_CFG1 (16'b0000000000000000),
     .QPLL1_SDM_CFG2 (16'b0000000000000000),
-    .RSVD_ATTR0 (16'b0000000000000000),
-    .RSVD_ATTR1 (16'b0000000000000000),
-    .RSVD_ATTR2 (16'b0000000000000000),
-    .RSVD_ATTR3 (16'b0000000000000000),
-    .SDM0DATA1_0 (16'b0000000000000000),
-    .SDM0INITSEED0_0 (16'b0000000000000000),
-    .SDM1DATA1_0 (16'b0000000000000000),
-    .SDM1INITSEED0_0 (16'b0000000000000000),
+    .RSVD_ATTR0 (16'h0000),
+    .RSVD_ATTR1 (16'h0000),
+    .RSVD_ATTR2 (16'h0000),
+    .RSVD_ATTR3 (16'h0000),
     .RXRECCLKOUT0_SEL (2'b00),
     .RXRECCLKOUT1_SEL (2'b00),
-    .QPLL0_INIT_CFG1 (8'b00000000),
-    .QPLL1_INIT_CFG1 (8'b00000000),
+    .SARC_EN (1'b1),
+    .SARC_SEL (1'b0),
+    .SDM0DATA1_0 (16'b0000000000000000),
     .SDM0DATA1_1 (9'b000000000),
+    .SDM0INITSEED0_0 (16'b0000000000000000),
     .SDM0INITSEED0_1 (9'b000000000),
+    .SDM0_DATA_PIN_SEL (1'b0),
+    .SDM0_WIDTH_PIN_SEL (1'b0),
+    .SDM1DATA1_0 (16'b0000000000000000),
     .SDM1DATA1_1 (9'b000000000),
+    .SDM1INITSEED0_0 (16'b0000000000000000),
     .SDM1INITSEED0_1 (9'b000000000),
-    .BIAS_CFG_RSVD (10'b0000000000),
-    .QPLL0_CP (10'b0000011111),
-    .QPLL0_CP_G3 (10'b1111111111),
-    .QPLL0_LPF (10'b1111111111),
-    .QPLL0_LPF_G3 (10'b0000010101),
-    .QPLL1_CP (10'b0000011111),
-    .QPLL1_CP_G3 (10'b1111111111),
-    .QPLL1_LPF (10'b1111111111),
-    .QPLL1_LPF_G3 (10'b0000010101),
-    .QPLL0_FBDIV (QPLL_FBDIV),
-    .QPLL0_FBDIV_G3 (80),
-    .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
-    .QPLL1_FBDIV (QPLL_FBDIV),
-    .QPLL1_FBDIV_G3 (80),
-    .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV))
+    .SDM1_DATA_PIN_SEL (1'b0),
+    .SDM1_WIDTH_PIN_SEL (1'b0),
+    .SIM_MODE ("FAST"),
+    .SIM_RESET_SPEEDUP ("TRUE"),
+    .SIM_VERSION (2))
   i_gthe3_common (
-    .BGBYPASSB (1'd1),
-    .BGMONITORENB (1'd1),
-    .BGPDB (1'd1),
-    .BGRCALOVRD (5'b11111),
-    .BGRCALOVRDENB (1'd1),
+    .BGBYPASSB (1'h1),
+    .BGMONITORENB (1'h1),
+    .BGPDB (1'h1),
+    .BGRCALOVRD (5'h1f),
+    .BGRCALOVRDENB (1'h1),
     .DRPADDR (up_addr_int[8:0]),
     .DRPCLK (up_clk),
     .DRPDI (up_wdata_int),
-    .DRPEN (up_enb_int),
-    .DRPWE (up_wr_int),
-    .GTGREFCLK0 (1'd0),
-    .GTGREFCLK1 (1'd0),
-    .GTNORTHREFCLK00 (1'd0),
-    .GTNORTHREFCLK01 (1'd0),
-    .GTNORTHREFCLK10 (1'd0),
-    .GTNORTHREFCLK11 (1'd0),
-    .GTREFCLK00 (qpll_ref_clk),
-    .GTREFCLK01 (1'd0),
-    .GTREFCLK10 (1'd0),
-    .GTREFCLK11 (1'd0),
-    .GTSOUTHREFCLK00 (1'd0),
-    .GTSOUTHREFCLK01 (1'd0),
-    .GTSOUTHREFCLK10 (1'd0),
-    .GTSOUTHREFCLK11 (1'd0),
-    .PMARSVD0 (8'd0),
-    .PMARSVD1 (8'd0),
-    .QPLLRSVD1 (8'd0),
-    .QPLLRSVD2 (5'd0),
-    .QPLLRSVD3 (5'd0),
-    .QPLLRSVD4 (8'd0),
-    .QPLL0CLKRSVD0 (1'd0),
-    .QPLL0CLKRSVD1 (1'd0),
-    .QPLL0LOCKDETCLK (up_clk),
-    .QPLL0LOCKEN (1'd1),
-    .QPLL0PD (1'd0),
-    .QPLL0REFCLKSEL (3'b001),
-    .QPLL0RESET (up_qpll_rst),
-    .QPLL1CLKRSVD0 (1'd0),
-    .QPLL1CLKRSVD1 (1'd0),
-    .QPLL1LOCKDETCLK (1'd0),
-    .QPLL1LOCKEN (1'd0),
-    .QPLL1PD (1'd1),
-    .QPLL1REFCLKSEL (3'b001),
-    .QPLL1RESET (1'd1),
-    .RCALENB (1'd1),
     .DRPDO (up_rdata_s),
+    .DRPEN (up_enb_int),
     .DRPRDY (up_ready_s),
+    .DRPWE (up_wr_int),
+    .GTGREFCLK0 (1'h0),
+    .GTGREFCLK1 (1'h0),
+    .GTNORTHREFCLK00 (1'h0),
+    .GTNORTHREFCLK01 (1'h0),
+    .GTNORTHREFCLK10 (1'h0),
+    .GTNORTHREFCLK11 (1'h0),
+    .GTREFCLK00 (qpll_ref_clk),
+    .GTREFCLK01 (1'h0),
+    .GTREFCLK10 (1'h0),
+    .GTREFCLK11 (1'h0),
+    .GTSOUTHREFCLK00 (1'h0),
+    .GTSOUTHREFCLK01 (1'h0),
+    .GTSOUTHREFCLK10 (1'h0),
+    .GTSOUTHREFCLK11 (1'h0),
+    .PMARSVD0 (8'h0),
+    .PMARSVD1 (8'h0),
     .PMARSVDOUT0 (),
     .PMARSVDOUT1 (),
-    .QPLLDMONITOR0 (),
-    .QPLLDMONITOR1 (),
+    .QPLL0CLKRSVD0 (1'h0),
+    .QPLL0CLKRSVD1 (1'h0),
     .QPLL0FBCLKLOST (),
     .QPLL0LOCK (qpll2ch_locked),
+    .QPLL0LOCKDETCLK (up_clk),
+    .QPLL0LOCKEN (1'h1),
     .QPLL0OUTCLK (qpll2ch_clk),
     .QPLL0OUTREFCLK (qpll2ch_ref_clk),
+    .QPLL0PD (1'h0),
     .QPLL0REFCLKLOST (),
+    .QPLL0REFCLKSEL (3'h1),
+    .QPLL0RESET (up_qpll_rst),
+    .QPLL1CLKRSVD0 (1'h0),
+    .QPLL1CLKRSVD1 (1'h0),
     .QPLL1FBCLKLOST (),
     .QPLL1LOCK (),
+    .QPLL1LOCKDETCLK (1'h0),
+    .QPLL1LOCKEN (1'h0),
     .QPLL1OUTCLK (),
     .QPLL1OUTREFCLK (),
+    .QPLL1PD (1'h0),
     .QPLL1REFCLKLOST (),
+    .QPLL1REFCLKSEL (3'h1),
+    .QPLL1RESET (1'h1),
+    .QPLLDMONITOR0 (),
+    .QPLLDMONITOR1 (),
+    .QPLLRSVD1 (8'h0),
+    .QPLLRSVD2 (5'h0),
+    .QPLLRSVD3 (5'h0),
+    .QPLLRSVD4 (8'h0),
+    .RCALENB (1'h1),
     .REFCLKOUTMONITOR0 (),
     .REFCLKOUTMONITOR1 (),
     .RXRECCLK0_SEL (),

From 3abd87631a85d0ae19c74056dd22b21d423af706 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 21 Oct 2016 12:49:48 +0300
Subject: [PATCH 622/972] fmcomms11: Fix parameter name

---
 projects/fmcomms11/common/fmcomms11_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index 609abb8aa..dccad947b 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -58,7 +58,7 @@ set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.TX_CLK25_DIV {7}] $util_fmcomms11_xcvr
-set_property -dict [list CONFIG.PMA_RSV {0x00018480}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr
 
 ad_connect  sys_cpu_resetn util_fmcomms11_xcvr/up_rstn

From 801f980aeb2a443b697f5537c500a7dca91ed490 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 21 Oct 2016 12:50:20 +0300
Subject: [PATCH 623/972] adrv9371: Fix parameter name

---
 projects/adrv9371x/common/adrv9371x_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index d071fe59b..f36ba1345 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -118,7 +118,7 @@ set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_ad9371_xcvr
 set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_ad9371_xcvr
 set_property -dict [list CONFIG.RX_CLK25_DIV {5}] $util_ad9371_xcvr
 set_property -dict [list CONFIG.TX_CLK25_DIV {5}] $util_ad9371_xcvr
-set_property -dict [list CONFIG.PMA_RSV {0x00018480}] $util_ad9371_xcvr
+set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_ad9371_xcvr
 set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad9371_xcvr
 set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_ad9371_xcvr
 

From 8dbfe9258f77a4dcd860445cff8777f0319aaee9 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 21 Oct 2016 13:47:01 +0300
Subject: [PATCH 624/972] axi_ad9162: Delete duplicated port

---
 library/axi_ad9162/axi_ad9162_channel.v | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v
index 001ae3be9..c15a3a996 100644
--- a/library/axi_ad9162/axi_ad9162_channel.v
+++ b/library/axi_ad9162/axi_ad9162_channel.v
@@ -613,7 +613,6 @@ module axi_ad9162_channel (
       .dac_pat_data_2 (dac_pat_data_2_s),
       .dac_data_sel (dac_data_sel_s),
       .dac_iq_mode (dac_iq_mode_s),
-      .dac_iq_mode (),
       .dac_iqcor_enb (),
       .dac_iqcor_coeff_1 (),
       .dac_iqcor_coeff_2 (),

From 48e90f0e9b342c7dd782775b33e28b21191a6134 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 20 Oct 2016 12:32:20 -0400
Subject: [PATCH 625/972] usrpe31x- added

---
 projects/usrpe31x/Makefile           |  66 +++++++
 projects/usrpe31x/system_bd.tcl      | 265 +++++++++++++++++++++++++++
 projects/usrpe31x/system_constr.xdc  | 202 ++++++++++++++++++++
 projects/usrpe31x/system_project.tcl |  16 ++
 projects/usrpe31x/system_top.v       | 172 +++++++++++++++++
 5 files changed, 721 insertions(+)
 create mode 100644 projects/usrpe31x/Makefile
 create mode 100644 projects/usrpe31x/system_bd.tcl
 create mode 100644 projects/usrpe31x/system_constr.xdc
 create mode 100644 projects/usrpe31x/system_project.tcl
 create mode 100644 projects/usrpe31x/system_top.v

diff --git a/projects/usrpe31x/Makefile b/projects/usrpe31x/Makefile
new file mode 100644
index 000000000..b554b4b1f
--- /dev/null
+++ b/projects/usrpe31x/Makefile
@@ -0,0 +1,66 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../scripts/adi_project.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_board.tcl
+M_DEPS += ../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../library/util_upack/util_upack.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib sdrstk.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../library/axi_ad9361 clean
+	make -C ../../library/axi_dmac clean
+	make -C ../../library/util_cpack clean
+	make -C ../../library/util_upack clean
+
+
+sdrstk.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> sdrstk_vivado.log 2>&1
+
+
+lib:
+	make -C ../../library/axi_ad9361
+	make -C ../../library/axi_dmac
+	make -C ../../library/util_cpack
+	make -C ../../library/util_upack
+
+####################################################################################
+####################################################################################
diff --git a/projects/usrpe31x/system_bd.tcl b/projects/usrpe31x/system_bd.tcl
new file mode 100644
index 000000000..5ca44c4a5
--- /dev/null
+++ b/projects/usrpe31x/system_bd.tcl
@@ -0,0 +1,265 @@
+# create board design
+# default ports
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
+create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+
+create_bd_port -dir O spi0_csn_2_o
+create_bd_port -dir O spi0_csn_1_o
+create_bd_port -dir O spi0_csn_0_o
+create_bd_port -dir I spi0_csn_i
+create_bd_port -dir I spi0_clk_i
+create_bd_port -dir O spi0_clk_o
+create_bd_port -dir I spi0_sdo_i
+create_bd_port -dir O spi0_sdo_o
+create_bd_port -dir I spi0_sdi_i
+
+create_bd_port -dir I -from 16 -to 0 gpio_i
+create_bd_port -dir O -from 16 -to 0 gpio_o
+create_bd_port -dir O -from 16 -to 0 gpio_t
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_11
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+create_bd_port -dir I -type intr ps_intr_14
+create_bd_port -dir I -type intr ps_intr_15
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+
+# ps7 settings
+
+set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+
+# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
+
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+
+# interface connections
+
+ad_connect  ddr sys_ps7/DDR
+ad_connect  gpio_i sys_ps7/GPIO_I
+ad_connect  gpio_o sys_ps7/GPIO_O
+ad_connect  gpio_t sys_ps7/GPIO_T
+ad_connect  fixed_io sys_ps7/FIXED_IO
+
+# spi connections
+
+ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
+ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
+ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
+ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
+ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
+ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
+ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
+ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
+ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+
+# interrupts
+
+ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15 ps_intr_15
+ad_connect  sys_concat_intc/In14 ps_intr_14
+ad_connect  sys_concat_intc/In13 ps_intr_13
+ad_connect  sys_concat_intc/In12 ps_intr_12
+ad_connect  sys_concat_intc/In11 ps_intr_11
+ad_connect  sys_concat_intc/In10 ps_intr_10
+ad_connect  sys_concat_intc/In9 ps_intr_09
+ad_connect  sys_concat_intc/In8 ps_intr_08
+ad_connect  sys_concat_intc/In7 ps_intr_07
+ad_connect  sys_concat_intc/In6 ps_intr_06
+ad_connect  sys_concat_intc/In5 ps_intr_05
+ad_connect  sys_concat_intc/In4 ps_intr_04
+ad_connect  sys_concat_intc/In3 ps_intr_03
+ad_connect  sys_concat_intc/In2 ps_intr_02
+ad_connect  sys_concat_intc/In1 ps_intr_01
+ad_connect  sys_concat_intc/In0 ps_intr_00
+
+# iic
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+
+ad_connect  iic_main axi_iic_main/iic
+ad_cpu_interconnect 0x41600000 axi_iic_main
+ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt
+
+# ad9361
+
+create_bd_port -dir I rx_clk_in
+create_bd_port -dir I rx_frame_in
+create_bd_port -dir I -from 11 -to 0 rx_data_in
+
+create_bd_port -dir O tx_clk_out
+create_bd_port -dir O tx_frame_out
+create_bd_port -dir O -from 11 -to 0 tx_data_out
+
+create_bd_port -dir O enable
+create_bd_port -dir O txnrx
+create_bd_port -dir I up_enable
+create_bd_port -dir I up_txnrx
+
+# ad9361 core(s)
+
+set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
+set_property -dict [list CONFIG.ID {0}] $axi_ad9361
+set_property -dict [list CONFIG.CMOS_OR_LVDS_N {1}] $axi_ad9361
+
+set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {32}] $axi_ad9361_dac_dma
+
+set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_dac_upack
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack
+
+set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}]  $axi_ad9361_adc_dma
+
+set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_adc_pack
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack
+
+# connections
+
+ad_connect  rx_clk_in axi_ad9361/rx_clk_in
+ad_connect  rx_frame_in axi_ad9361/rx_frame_in
+ad_connect  rx_data_in axi_ad9361/rx_data_in
+ad_connect  tx_clk_out axi_ad9361/tx_clk_out
+ad_connect  tx_frame_out axi_ad9361/tx_frame_out
+ad_connect  tx_data_out axi_ad9361/tx_data_out
+ad_connect  enable axi_ad9361/enable
+ad_connect  txnrx axi_ad9361/txnrx
+ad_connect  up_enable axi_ad9361/up_enable
+ad_connect  up_txnrx axi_ad9361/up_txnrx
+
+ad_connect  axi_ad9361/tdd_sync GND
+ad_connect  sys_200m_clk axi_ad9361/delay_clk
+ad_connect  axi_ad9361/l_clk axi_ad9361/clk
+
+ad_connect  axi_ad9361/l_clk util_ad9361_adc_pack/adc_clk
+ad_connect  axi_ad9361/rst util_ad9361_adc_pack/adc_rst
+ad_connect  axi_ad9361/adc_enable_i0 util_ad9361_adc_pack/adc_enable_0
+ad_connect  axi_ad9361/adc_valid_i0 util_ad9361_adc_pack/adc_valid_0
+ad_connect  axi_ad9361/adc_data_i0 util_ad9361_adc_pack/adc_data_0
+ad_connect  axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1
+ad_connect  axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1
+ad_connect  axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1
+ad_connect  axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
+ad_connect  util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
+ad_connect  util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
+ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf
+ad_connect  axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk
+ad_connect  axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0
+ad_connect  axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0
+ad_connect  util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
+ad_connect  axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1
+ad_connect  axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1
+ad_connect  util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
+ad_connect  axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk
+ad_connect  util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
+ad_connect  axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data
+ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
+ad_connect  axi_ad9361/dac_data_i1 GND
+ad_connect  axi_ad9361/dac_data_q1 GND
+
+# interconnects
+
+ad_cpu_interconnect 0x79020000 axi_ad9361
+ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
+ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
+ad_connect  sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
+ad_connect  sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
+
+# interrupts
+
+ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
+ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
+
+
diff --git a/projects/usrpe31x/system_constr.xdc b/projects/usrpe31x/system_constr.xdc
new file mode 100644
index 000000000..d41a6f328
--- /dev/null
+++ b/projects/usrpe31x/system_constr.xdc
@@ -0,0 +1,202 @@
+# constraints
+# ad9361 (SWAP == 0x1)
+
+set_property  -dict {PACKAGE_PIN  L12  IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
+set_property  -dict {PACKAGE_PIN  N13  IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
+set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
+set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
+set_property  -dict {PACKAGE_PIN  H11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
+set_property  -dict {PACKAGE_PIN  J11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
+
+set_property  -dict {PACKAGE_PIN  P10  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
+set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
+set_property  -dict {PACKAGE_PIN  R13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
+set_property  -dict {PACKAGE_PIN  R15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
+set_property  -dict {PACKAGE_PIN  P11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
+set_property  -dict {PACKAGE_PIN  R11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
+set_property  -dict {PACKAGE_PIN  R12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
+set_property  -dict {PACKAGE_PIN  P14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
+set_property  -dict {PACKAGE_PIN  P13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
+set_property  -dict {PACKAGE_PIN  N9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
+set_property  -dict {PACKAGE_PIN  M9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
+set_property  -dict {PACKAGE_PIN  R8   IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
+set_property  -dict {PACKAGE_PIN  R7   IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
+
+set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
+set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
+set_property  -dict {PACKAGE_PIN  N11  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]
+set_property  -dict {PACKAGE_PIN  N12  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]
+set_property  -dict {PACKAGE_PIN  M10  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]
+set_property  -dict {PACKAGE_PIN  M11  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]
+set_property  -dict {PACKAGE_PIN  N7   IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]
+set_property  -dict {PACKAGE_PIN  N8   IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]
+
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]
+set_property  -dict {PACKAGE_PIN  F14  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]
+
+set_property  -dict {PACKAGE_PIN  L13  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]
+set_property  -dict {PACKAGE_PIN  P9   IOSTANDARD LVCMOS18} [get_ports gpio_resetb]
+
+set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports enable]
+set_property  -dict {PACKAGE_PIN  K11  IOSTANDARD LVCMOS18} [get_ports txnrx]
+
+set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  N14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]
+
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports spi_clk]
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports spi_mosi]
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports spi_miso]
+
+set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports gpio_bd]
+set_property  -dict {PACKAGE_PIN  P8   IOSTANDARD LVCMOS18} [get_ports clk_out]
+
+create_clock -name rx_clk -period  16 [get_ports rx_clk_in]
+
+# probably gone in 2016.4
+
+create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"]
+create_clock -name clk_fpga_1 -period  5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"]
+
+set_input_jitter clk_fpga_0 0.3
+set_input_jitter clk_fpga_1 0.15
+
+set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*]
+set_property SLEW SLOW [get_ports *fixed_io_mio*]
+set_property DRIVE 8 [get_ports *fixed_io_mio*]
+set_property  -dict {PACKAGE_PIN D8   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]]
+set_property  -dict {PACKAGE_PIN A5   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]]
+set_property  -dict {PACKAGE_PIN A8                  } [get_ports fixed_io_mio[ 2]]
+set_property  -dict {PACKAGE_PIN A7                  } [get_ports fixed_io_mio[ 3]]
+set_property  -dict {PACKAGE_PIN C8                  } [get_ports fixed_io_mio[ 4]]
+set_property  -dict {PACKAGE_PIN A9                  } [get_ports fixed_io_mio[ 5]]
+set_property  -dict {PACKAGE_PIN A10                 } [get_ports fixed_io_mio[ 6]]
+set_property  -dict {PACKAGE_PIN D9                  } [get_ports fixed_io_mio[ 7]]
+set_property  -dict {PACKAGE_PIN B6                  } [get_ports fixed_io_mio[ 8]]
+set_property  -dict {PACKAGE_PIN B5   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]]
+set_property  -dict {PACKAGE_PIN D6   PULLTYPE PULLUP} [get_ports fixed_io_mio[10]]
+set_property  -dict {PACKAGE_PIN B10  PULLTYPE PULLUP} [get_ports fixed_io_mio[11]]
+set_property  -dict {PACKAGE_PIN B7   PULLTYPE PULLUP} [get_ports fixed_io_mio[12]]
+set_property  -dict {PACKAGE_PIN C6   PULLTYPE PULLUP} [get_ports fixed_io_mio[13]]
+set_property  -dict {PACKAGE_PIN B9   PULLTYPE PULLUP} [get_ports fixed_io_mio[14]]
+set_property  -dict {PACKAGE_PIN D10  PULLTYPE PULLUP} [get_ports fixed_io_mio[15]]
+set_property  -dict {PACKAGE_PIN A15  PULLTYPE PULLUP} [get_ports fixed_io_mio[16]]
+set_property  -dict {PACKAGE_PIN D11  PULLTYPE PULLUP} [get_ports fixed_io_mio[17]]
+set_property  -dict {PACKAGE_PIN B15  PULLTYPE PULLUP} [get_ports fixed_io_mio[18]]
+set_property  -dict {PACKAGE_PIN C12  PULLTYPE PULLUP} [get_ports fixed_io_mio[19]]
+set_property  -dict {PACKAGE_PIN E15  PULLTYPE PULLUP} [get_ports fixed_io_mio[20]]
+set_property  -dict {PACKAGE_PIN C11  PULLTYPE PULLUP} [get_ports fixed_io_mio[21]]
+set_property  -dict {PACKAGE_PIN D15  PULLTYPE PULLUP} [get_ports fixed_io_mio[22]]
+set_property  -dict {PACKAGE_PIN A14  PULLTYPE PULLUP} [get_ports fixed_io_mio[23]]
+set_property  -dict {PACKAGE_PIN B14  PULLTYPE PULLUP} [get_ports fixed_io_mio[24]]
+set_property  -dict {PACKAGE_PIN C14  PULLTYPE PULLUP} [get_ports fixed_io_mio[25]]
+set_property  -dict {PACKAGE_PIN A13  PULLTYPE PULLUP} [get_ports fixed_io_mio[26]]
+set_property  -dict {PACKAGE_PIN D14  PULLTYPE PULLUP} [get_ports fixed_io_mio[27]]
+set_property  -dict {PACKAGE_PIN B12  PULLTYPE PULLUP} [get_ports fixed_io_mio[28]]
+set_property  -dict {PACKAGE_PIN D13  PULLTYPE PULLUP} [get_ports fixed_io_mio[29]]
+set_property  -dict {PACKAGE_PIN A12  PULLTYPE PULLUP} [get_ports fixed_io_mio[30]]
+set_property  -dict {PACKAGE_PIN C13  PULLTYPE PULLUP} [get_ports fixed_io_mio[31]]
+
+set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*]
+set_property SLEW SLOW [get_ports *fixed_io_ps*]
+set_property DRIVE 8 [get_ports *fixed_io_ps*]
+set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk]
+set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb]
+
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*]
+set_property SLEW FAST [get_ports *fixed_io_ddr_vr*]
+set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp]
+set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn]
+
+set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*]
+set_property SLEW FAST [get_ports *ddr_ck*]
+set_property PACKAGE_PIN N3 [get_ports ddr_ck_p]
+set_property PACKAGE_PIN N2 [get_ports ddr_ck_n]
+
+set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*]
+set_property SLEW SLOW [get_ports *ddr_addr*]
+set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]]
+set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]]
+set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]]
+set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]]
+set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]]
+set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]]
+set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]]
+set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]]
+set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]]
+set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]]
+set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]]
+set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]]
+set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]]
+set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]]
+set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]]
+
+set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*]
+set_property SLEW SLOW [get_ports *ddr_ba*]
+set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]]
+set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]]
+set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]]
+
+set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n]
+set_property SLEW FAST [get_ports ddr_reset_n]
+set_property PACKAGE_PIN L4 [get_ports ddr_reset_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n]
+set_property SLEW SLOW [get_ports ddr_cs_n]
+set_property PACKAGE_PIN R2 [get_ports ddr_cs_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n]
+set_property SLEW SLOW [get_ports ddr_ras_n]
+set_property PACKAGE_PIN R6 [get_ports ddr_ras_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n]
+set_property SLEW SLOW [get_ports ddr_cas_n]
+set_property PACKAGE_PIN R5 [get_ports ddr_cas_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_we_n]
+set_property SLEW SLOW [get_ports ddr_we_n]
+set_property PACKAGE_PIN R3 [get_ports ddr_we_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cke]
+set_property SLEW SLOW [get_ports ddr_cke]
+set_property PACKAGE_PIN L3 [get_ports ddr_cke]
+set_property IOSTANDARD SSTL15 [get_ports ddr_odt]
+set_property SLEW SLOW [get_ports ddr_odt]
+set_property PACKAGE_PIN K3 [get_ports ddr_odt]
+
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]]
+set_property SLEW FAST [get_ports *ddr_dq[*]]
+set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]]
+set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]]
+set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]]
+set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]]
+set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]]
+set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]]
+set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]]
+set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]]
+set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]]
+set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]]
+set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]]
+set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]]
+set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]]
+set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]]
+set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]]
+set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]]
+set_property SLEW FAST [get_ports *ddr_dm[*]]
+set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]]
+set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]]
+set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*]
+set_property SLEW FAST [get_ports *ddr_dqs*]
+set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]]
+set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]]
+set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]]
+set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]]
+
+
diff --git a/projects/usrpe31x/system_project.tcl b/projects/usrpe31x/system_project.tcl
new file mode 100644
index 000000000..4586ed0c6
--- /dev/null
+++ b/projects/usrpe31x/system_project.tcl
@@ -0,0 +1,16 @@
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+set p_device "xc7z020clg484-1"
+adi_project_create usrpe31x
+
+adi_project_files usrpe31x [list \
+  "system_top.v" \
+  "system_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
+
+adi_project_run usrpe31x
+
+
diff --git a/projects/usrpe31x/system_top.v b/projects/usrpe31x/system_top.v
new file mode 100644
index 000000000..c74269645
--- /dev/null
+++ b/projects/usrpe31x/system_top.v
@@ -0,0 +1,172 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 1:0]  ddr_dm,
+  inout   [15:0]  ddr_dq,
+  inout   [ 1:0]  ddr_dqs_n,
+  inout   [ 1:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [31:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout           iic_scl,
+  inout           iic_sda,
+
+  inout           gpio_bd,
+
+  input           rx_clk_in,
+  input           rx_frame_in,
+  input   [11:0]  rx_data_in,
+  output          tx_clk_out,
+  output          tx_frame_out,
+  output  [11:0]  tx_data_out,
+
+  output          enable,
+  output          txnrx,
+  input           clk_out,
+
+  inout           gpio_resetb,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
+
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso);
+
+  // internal signals
+
+  wire    [16:0]  gpio_i;
+  wire    [16:0]  gpio_o;
+  wire    [16:0]  gpio_t;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
+    .dio_t (gpio_t[14:0]),
+    .dio_i (gpio_o[14:0]),
+    .dio_o (gpio_i[14:0]),
+    .dio_p ({ gpio_bd,            // 14:14
+              gpio_resetb,        // 13:13
+              gpio_en_agc,        // 12:12
+              gpio_ctl,           // 11: 8
+              gpio_status}));     //  7: 0
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_14 (1'b0),
+    .rx_clk_in (rx_clk_in),
+    .rx_data_in (rx_data_in),
+    .rx_frame_in (rx_frame_in),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .tx_clk_out (tx_clk_out),
+    .tx_data_out (tx_data_out),
+    .tx_frame_out (tx_frame_out),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[15]),
+    .up_txnrx (gpio_o[16]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 7b958fed870eb9d01295f688e011a3f25900a993 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 20 Oct 2016 12:37:38 -0400
Subject: [PATCH 626/972] hdlmake- updates

---
 projects/Makefile                |  3 ++
 projects/fmcomms2/a10gx/Makefile |  4 +--
 projects/usrpe31x/Makefile       | 57 ++++----------------------------
 projects/usrpe31x/system_bd.tcl  |  5 ++-
 4 files changed, 13 insertions(+), 56 deletions(-)

diff --git a/projects/Makefile b/projects/Makefile
index 47e5dee81..d4ea0ef46 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -41,6 +41,7 @@ all:
 	-make -C sdrstk all
 	-make -C usb_fx3 all
 	-make -C usdrx1 all
+	-make -C usrpe31x all
 
 
 clean:
@@ -78,6 +79,7 @@ clean:
 	make -C sdrstk clean
 	make -C usb_fx3 clean
 	make -C usdrx1 clean
+	make -C usrpe31x clean
 
 
 clean-all:
@@ -115,6 +117,7 @@ clean-all:
 	make -C sdrstk clean-all
 	make -C usb_fx3 clean-all
 	make -C usdrx1 clean-all
+	make -C usrpe31x clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 51fde8d74..6011b3a7a 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -19,8 +19,8 @@ M_DEPS += ../common/fmcomms2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
-M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_cmos_if.v
-M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+M_DEPS += ../../../altera/axi_ad9361_cmos_if.v
+M_DEPS += ../../../altera/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
 M_DEPS += ../../../library/altera/common/ad_cmos_in.v
 M_DEPS += ../../../library/altera/common/ad_cmos_out.v
diff --git a/projects/usrpe31x/Makefile b/projects/usrpe31x/Makefile
index b554b4b1f..620ee8f00 100644
--- a/projects/usrpe31x/Makefile
+++ b/projects/usrpe31x/Makefile
@@ -5,62 +5,17 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../scripts/adi_project.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_board.tcl
-M_DEPS += ../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
-M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../library/util_upack/util_upack.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib sdrstk.sdk/system_top.hdf
+.PHONY: all clean clean-all 
+all:
+	-make -C system_project.tcl all
 
 
 clean: 
-	rm -rf $(M_FLIST)
+	make -C system_project.tcl clean
 
 
-clean-all:clean
-	make -C ../../library/axi_ad9361 clean
-	make -C ../../library/axi_dmac clean
-	make -C ../../library/util_cpack clean
-	make -C ../../library/util_upack clean
-
-
-sdrstk.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> sdrstk_vivado.log 2>&1
-
-
-lib:
-	make -C ../../library/axi_ad9361
-	make -C ../../library/axi_dmac
-	make -C ../../library/util_cpack
-	make -C ../../library/util_upack
+clean-all:
+	make -C system_project.tcl clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/usrpe31x/system_bd.tcl b/projects/usrpe31x/system_bd.tcl
index 5ca44c4a5..a46f53d99 100644
--- a/projects/usrpe31x/system_bd.tcl
+++ b/projects/usrpe31x/system_bd.tcl
@@ -45,7 +45,6 @@ set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5
 
 set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
 set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
-set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7
 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
@@ -54,8 +53,8 @@ set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7
 set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7

From c9ac8700862301dfced841b38e04645883a58135 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 21 Oct 2016 13:59:27 -0400
Subject: [PATCH 627/972] usrpe31x- updates

---
 projects/usrpe31x/Makefile          |  60 +++++-
 projects/usrpe31x/system_bd.tcl     | 152 +++++++++-----
 projects/usrpe31x/system_constr.xdc | 309 ++++++++++++----------------
 projects/usrpe31x/system_top.v      | 229 +++++++++++++++++----
 4 files changed, 465 insertions(+), 285 deletions(-)

diff --git a/projects/usrpe31x/Makefile b/projects/usrpe31x/Makefile
index 620ee8f00..6d71eb7cc 100644
--- a/projects/usrpe31x/Makefile
+++ b/projects/usrpe31x/Makefile
@@ -5,17 +5,65 @@
 ####################################################################################
 ####################################################################################
 
-.PHONY: all clean clean-all 
-all:
-	-make -C system_project.tcl all
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../scripts/adi_project.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_board.tcl
+M_DEPS += ../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../library/util_upack/util_upack.xpr
+M_DEPS += ../../library/util_tdd_sync/util_tdd_sync.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib usrpe31x.sdk/system_top.hdf
 
 
 clean: 
-	make -C system_project.tcl clean
+	rm -rf $(M_FLIST)
 
 
-clean-all:
-	make -C system_project.tcl clean-all
+clean-all:clean
+	make -C ../../library/axi_ad9361 clean
+	make -C ../../library/axi_dmac clean
+	make -C ../../library/util_cpack clean
+	make -C ../../library/util_upack clean
+	make -C ../../library/util_tdd_sync clean
+
+
+usrpe31x.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> usrpe31x_vivado.log 2>&1
+
+
+lib:
+	make -C ../../library/axi_ad9361
+	make -C ../../library/axi_dmac
+	make -C ../../library/util_cpack
+	make -C ../../library/util_upack
+	make -C ../../library/util_tdd_sync
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/usrpe31x/system_bd.tcl b/projects/usrpe31x/system_bd.tcl
index a46f53d99..bf5dbf721 100644
--- a/projects/usrpe31x/system_bd.tcl
+++ b/projects/usrpe31x/system_bd.tcl
@@ -4,19 +4,21 @@
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
 create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
 
-create_bd_port -dir O spi0_csn_2_o
-create_bd_port -dir O spi0_csn_1_o
-create_bd_port -dir O spi0_csn_0_o
-create_bd_port -dir I spi0_csn_i
-create_bd_port -dir I spi0_clk_i
-create_bd_port -dir O spi0_clk_o
-create_bd_port -dir I spi0_sdo_i
-create_bd_port -dir O spi0_sdo_o
-create_bd_port -dir I spi0_sdi_i
+create_bd_port -dir O spi0_csn_0
+create_bd_port -dir O spi0_csn_1
+create_bd_port -dir O spi0_csn_2
+create_bd_port -dir O spi0_clk
+create_bd_port -dir O spi0_mosi
+create_bd_port -dir I spi0_miso
 
-create_bd_port -dir I -from 16 -to 0 gpio_i
-create_bd_port -dir O -from 16 -to 0 gpio_o
-create_bd_port -dir O -from 16 -to 0 gpio_t
+create_bd_port -dir I spi1_csn
+create_bd_port -dir I spi1_clk
+create_bd_port -dir I spi1_mosi
+create_bd_port -dir O spi1_miso
+
+create_bd_port -dir I -from 63 -to 0 ps_gpio_i
+create_bd_port -dir O -from 63 -to 0 ps_gpio_o
+create_bd_port -dir O -from 63 -to 0 ps_gpio_t
 
 # interrupts
 
@@ -51,40 +53,52 @@ set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7
-set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
-set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 11}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39}] $sys_ps7
 set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 9}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
 
 # DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
 
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_CWL {6}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_RC {48.75}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7
-set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7
 
 set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
 set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
@@ -104,22 +118,28 @@ ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
 # interface connections
 
 ad_connect  ddr sys_ps7/DDR
-ad_connect  gpio_i sys_ps7/GPIO_I
-ad_connect  gpio_o sys_ps7/GPIO_O
-ad_connect  gpio_t sys_ps7/GPIO_T
+ad_connect  ps_gpio_i sys_ps7/GPIO_I
+ad_connect  ps_gpio_o sys_ps7/GPIO_O
+ad_connect  ps_gpio_t sys_ps7/GPIO_T
 ad_connect  fixed_io sys_ps7/FIXED_IO
 
 # spi connections
 
-ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
-ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
-ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
-ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
-ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
-ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
-ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
-ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
-ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+ad_connect  sys_ps7/SPI0_SS_O spi0_csn_0
+ad_connect  sys_ps7/SPI0_SS1_O spi0_csn_1
+ad_connect  sys_ps7/SPI0_SS2_O spi0_csn_2
+ad_connect  sys_ps7/SPI0_SCLK_O spi0_clk
+ad_connect  sys_ps7/SPI0_MOSI_O spi0_mosi
+ad_connect  sys_ps7/SPI0_MISO_I spi0_miso 
+ad_connect  sys_ps7/SPI0_SS_I VCC
+ad_connect  sys_ps7/SPI0_SCLK_I GND
+ad_connect  sys_ps7/SPI0_MOSI_I GND
+
+ad_connect  sys_ps7/SPI1_SS_I spi1_csn
+ad_connect  sys_ps7/SPI1_SCLK_I spi1_clk
+ad_connect  sys_ps7/SPI1_MOSI_I spi1_mosi
+ad_connect  sys_ps7/SPI1_MISO_O spi1_miso
+ad_connect  sys_ps7/SPI1_MISO_I GND 
 
 # interrupts
 
@@ -141,16 +161,6 @@ ad_connect  sys_concat_intc/In2 ps_intr_02
 ad_connect  sys_concat_intc/In1 ps_intr_01
 ad_connect  sys_concat_intc/In0 ps_intr_00
 
-# iic
-
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
-
-set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
-
-ad_connect  iic_main axi_iic_main/iic
-ad_cpu_interconnect 0x41600000 axi_iic_main
-ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt
-
 # ad9361
 
 create_bd_port -dir I rx_clk_in
@@ -213,7 +223,6 @@ ad_connect  txnrx axi_ad9361/txnrx
 ad_connect  up_enable axi_ad9361/up_enable
 ad_connect  up_txnrx axi_ad9361/up_txnrx
 
-ad_connect  axi_ad9361/tdd_sync GND
 ad_connect  sys_200m_clk axi_ad9361/delay_clk
 ad_connect  axi_ad9361/l_clk axi_ad9361/clk
 
@@ -261,4 +270,33 @@ ad_connect  sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
 ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
 ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
 
+# tdd-sync
+
+set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
+set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
+
+create_bd_port -dir I tdd_sync
+
+ad_connect  tdd_sync util_ad9361_tdd_sync/sync_in
+ad_connect  sys_cpu_clk util_ad9361_tdd_sync/clk
+ad_connect  sys_cpu_resetn util_ad9361_tdd_sync/rstn
+ad_connect  util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
+ad_connect  util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
+
+# gpio
+
+create_bd_port -dir I -from 31 -to 0 pl_gpio_i
+create_bd_port -dir O -from 31 -to 0 pl_gpio_o
+create_bd_port -dir O -from 31 -to 0 pl_gpio_t
+
+set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio]
+set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio
+set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio
+
+ad_connect  pl_gpio_i axi_gpio/gpio_io_i
+ad_connect  pl_gpio_o axi_gpio/gpio_io_o
+ad_connect  pl_gpio_t axi_gpio/gpio_io_t
+
+ad_cpu_interconnect 0x41600000 axi_gpio
+ad_cpu_interrupt ps-15 mb-15 axi_gpio/ip2intc_irpt
 
diff --git a/projects/usrpe31x/system_constr.xdc b/projects/usrpe31x/system_constr.xdc
index d41a6f328..5c79afb70 100644
--- a/projects/usrpe31x/system_constr.xdc
+++ b/projects/usrpe31x/system_constr.xdc
@@ -1,202 +1,157 @@
-# constraints
+
 # ad9361 (SWAP == 0x1)
 
-set_property  -dict {PACKAGE_PIN  L12  IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
-set_property  -dict {PACKAGE_PIN  N13  IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
-set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
-set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
-set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
-set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
-set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
-set_property  -dict {PACKAGE_PIN  H11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
-set_property  -dict {PACKAGE_PIN  J11  IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
+set_property  -dict {PACKAGE_PIN  L18   IOSTANDARD  LVCMOS18} [get_ports rx_clk_in]
+set_property  -dict {PACKAGE_PIN  N18   IOSTANDARD  LVCMOS18} [get_ports rx_frame_in]
+set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[0]]
+set_property  -dict {PACKAGE_PIN  K18   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[1]]
+set_property  -dict {PACKAGE_PIN  L17   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[2]]
+set_property  -dict {PACKAGE_PIN  J17   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[3]]
+set_property  -dict {PACKAGE_PIN  M16   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[4]]
+set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[5]]
+set_property  -dict {PACKAGE_PIN  K16   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[6]]
+set_property  -dict {PACKAGE_PIN  J16   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[7]]
+set_property  -dict {PACKAGE_PIN  N20   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[8]]
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[9]]
+set_property  -dict {PACKAGE_PIN  N17   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[10]]
+set_property  -dict {PACKAGE_PIN  M17   IOSTANDARD  LVCMOS18} [get_ports rx_data_in[11]]
 
-set_property  -dict {PACKAGE_PIN  P10  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
-set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
-set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
-set_property  -dict {PACKAGE_PIN  R13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
-set_property  -dict {PACKAGE_PIN  R15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
-set_property  -dict {PACKAGE_PIN  P11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
-set_property  -dict {PACKAGE_PIN  R11  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
-set_property  -dict {PACKAGE_PIN  R12  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
-set_property  -dict {PACKAGE_PIN  P14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
-set_property  -dict {PACKAGE_PIN  P13  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
-set_property  -dict {PACKAGE_PIN  N9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
-set_property  -dict {PACKAGE_PIN  M9   IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
-set_property  -dict {PACKAGE_PIN  R8   IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
-set_property  -dict {PACKAGE_PIN  R7   IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
+set_property  -dict {PACKAGE_PIN  R21   IOSTANDARD  LVCMOS18} [get_ports tx_clk_out]
+set_property  -dict {PACKAGE_PIN  P22   IOSTANDARD  LVCMOS18} [get_ports tx_frame_out]
+set_property  -dict {PACKAGE_PIN  N19   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[0]]
+set_property  -dict {PACKAGE_PIN  M21   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[1]]
+set_property  -dict {PACKAGE_PIN  P20   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[2]]
+set_property  -dict {PACKAGE_PIN  P15   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[3]]
+set_property  -dict {PACKAGE_PIN  P17   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[4]]
+set_property  -dict {PACKAGE_PIN  P18   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[5]]
+set_property  -dict {PACKAGE_PIN  R20   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[6]]
+set_property  -dict {PACKAGE_PIN  P21   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[7]]
+set_property  -dict {PACKAGE_PIN  M22   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[8]]
+set_property  -dict {PACKAGE_PIN  T17   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[9]]
+set_property  -dict {PACKAGE_PIN  N22   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[10]]
+set_property  -dict {PACKAGE_PIN  N15   IOSTANDARD  LVCMOS18} [get_ports tx_data_out[11]]
 
-set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
-set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
-set_property  -dict {PACKAGE_PIN  N11  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]
-set_property  -dict {PACKAGE_PIN  N12  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]
-set_property  -dict {PACKAGE_PIN  M10  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]
-set_property  -dict {PACKAGE_PIN  M11  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]
-set_property  -dict {PACKAGE_PIN  N7   IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]
-set_property  -dict {PACKAGE_PIN  N8   IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]
+set_property  -dict {PACKAGE_PIN  AB4   IOSTANDARD  LVCMOS18} [get_ports enable]
+set_property  -dict {PACKAGE_PIN  AB1   IOSTANDARD  LVCMOS18} [get_ports txnrx]
+set_property  -dict {PACKAGE_PIN  M19   IOSTANDARD  LVCMOS18} [get_ports out_clk]
 
-set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]
-set_property  -dict {PACKAGE_PIN  F14  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]
-set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]
-set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]
+set_property  -dict {PACKAGE_PIN  U11   IOSTANDARD  LVCMOS18} [get_ports gpio_resetb]
+set_property  -dict {PACKAGE_PIN  T16   IOSTANDARD  LVCMOS18} [get_ports gpio_sync]
+set_property  -dict {PACKAGE_PIN  AB2   IOSTANDARD  LVCMOS18} [get_ports gpio_en_agc]
+set_property  -dict {PACKAGE_PIN  V4    IOSTANDARD  LVCMOS18} [get_ports gpio_ctl[0]]
+set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS18} [get_ports gpio_ctl[1]]
+set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD  LVCMOS18} [get_ports gpio_ctl[2]]
+set_property  -dict {PACKAGE_PIN  U6    IOSTANDARD  LVCMOS18} [get_ports gpio_ctl[3]]
+set_property  -dict {PACKAGE_PIN  AB5   IOSTANDARD  LVCMOS18} [get_ports gpio_status[0]]
+set_property  -dict {PACKAGE_PIN  AB6   IOSTANDARD  LVCMOS18} [get_ports gpio_status[1]]
+set_property  -dict {PACKAGE_PIN  AB7   IOSTANDARD  LVCMOS18} [get_ports gpio_status[2]]
+set_property  -dict {PACKAGE_PIN  AA4   IOSTANDARD  LVCMOS18} [get_ports gpio_status[3]]
+set_property  -dict {PACKAGE_PIN  K20   IOSTANDARD  LVCMOS18} [get_ports gpio_status[4]]
+set_property  -dict {PACKAGE_PIN  L19   IOSTANDARD  LVCMOS18} [get_ports gpio_status[5]]
+set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS18} [get_ports gpio_status[6]]
+set_property  -dict {PACKAGE_PIN  W12   IOSTANDARD  LVCMOS18} [get_ports gpio_status[7]]
 
-set_property  -dict {PACKAGE_PIN  L13  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]
-set_property  -dict {PACKAGE_PIN  P9   IOSTANDARD LVCMOS18} [get_ports gpio_resetb]
+# not-connected?
 
-set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports enable]
-set_property  -dict {PACKAGE_PIN  K11  IOSTANDARD LVCMOS18} [get_ports txnrx]
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD  LVCMOS18} [get_ports gpio_rf[0]]
+set_property  -dict {PACKAGE_PIN  T18   IOSTANDARD  LVCMOS18} [get_ports gpio_rf[1]]
+set_property  -dict {PACKAGE_PIN  M15   IOSTANDARD  LVCMOS18} [get_ports gpio_rf[2]]
+set_property  -dict {PACKAGE_PIN  J18   IOSTANDARD  LVCMOS18} [get_ports gpio_rf[3]]
+set_property  -dict {PACKAGE_PIN  J20   IOSTANDARD  LVCMOS18} [get_ports gpio_rf[4]]
+set_property  -dict {PACKAGE_PIN  K19   IOSTANDARD  LVCMOS18} [get_ports gpio_rf[5]]
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS18} [get_ports gpio_rf[6]]
+set_property  -dict {PACKAGE_PIN  T6    IOSTANDARD  LVCMOS18} [get_ports gpio_rf[7]]
+set_property  -dict {PACKAGE_PIN  R6    IOSTANDARD  LVCMOS18} [get_ports gpio_rf[8]]
 
-set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]
-set_property  -dict {PACKAGE_PIN  N14  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]
+# forwarded clocks (not-connected?)
 
-set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]
-set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports spi_clk]
-set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports spi_mosi]
-set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports spi_miso]
+set_property  -dict {PACKAGE_PIN  U4    IOSTANDARD  LVCMOS18} [get_ports gpio_tcxo_clk]
+set_property  -dict {PACKAGE_PIN  T4    IOSTANDARD  LVCMOS18} [get_ports gpio_out_clk]
 
-set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports gpio_bd]
-set_property  -dict {PACKAGE_PIN  P8   IOSTANDARD LVCMOS18} [get_ports clk_out]
+# spi
+
+set_property  -dict {PACKAGE_PIN  W6    IOSTANDARD  LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]
+set_property  -dict {PACKAGE_PIN  W5    IOSTANDARD  LVCMOS18} [get_ports spi_clk]
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS18} [get_ports spi_mosi]
+set_property  -dict {PACKAGE_PIN  W7    IOSTANDARD  LVCMOS18} [get_ports spi_miso]
 
 create_clock -name rx_clk -period  16 [get_ports rx_clk_in]
 
-# probably gone in 2016.4
+# rf filter selects
 
-create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"]
-create_clock -name clk_fpga_1 -period  5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"]
+set_property  -dict {PACKAGE_PIN  F22   IOSTANDARD  LVCMOS33} [get_ports tx_bandsel[0]]
+set_property  -dict {PACKAGE_PIN  F21   IOSTANDARD  LVCMOS33} [get_ports tx_bandsel[1]]
+set_property  -dict {PACKAGE_PIN  H19   IOSTANDARD  LVCMOS33} [get_ports tx_bandsel[2]]
+set_property  -dict {PACKAGE_PIN  E19   IOSTANDARD  LVCMOS33} [get_ports rx_bandsel_1[0]]
+set_property  -dict {PACKAGE_PIN  G21   IOSTANDARD  LVCMOS33} [get_ports rx_bandsel_1[1]]
+set_property  -dict {PACKAGE_PIN  G20   IOSTANDARD  LVCMOS33} [get_ports rx_bandsel_1[2]]
+set_property  -dict {PACKAGE_PIN  F19   IOSTANDARD  LVCMOS33} [get_ports rx_bandsel_1b[0]]
+set_property  -dict {PACKAGE_PIN  G19   IOSTANDARD  LVCMOS33} [get_ports rx_bandsel_1b[1]]
+set_property  -dict {PACKAGE_PIN  A19   IOSTANDARD  LVCMOS33} [get_ports rx_bandsel_1c[0]]
+set_property  -dict {PACKAGE_PIN  B15   IOSTANDARD  LVCMOS33} [get_ports rx_bandsel_1c[1]]
+set_property  -dict {PACKAGE_PIN  AB9   IOSTANDARD  LVCMOS18} [get_ports rx_bandsel_2[0]]
+set_property  -dict {PACKAGE_PIN  AA9   IOSTANDARD  LVCMOS18} [get_ports rx_bandsel_2[1]]
+set_property  -dict {PACKAGE_PIN  AA8   IOSTANDARD  LVCMOS18} [get_ports rx_bandsel_2[2]]
+set_property  -dict {PACKAGE_PIN  Y4    IOSTANDARD  LVCMOS18} [get_ports rx_bandsel_2b[0]]
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS18} [get_ports rx_bandsel_2b[1]]
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS18} [get_ports rx_bandsel_2c[0]]
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS18} [get_ports rx_bandsel_2c[1]]
 
-set_input_jitter clk_fpga_0 0.3
-set_input_jitter clk_fpga_1 0.15
+# rf enables
 
-set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*]
-set_property SLEW SLOW [get_ports *fixed_io_mio*]
-set_property DRIVE 8 [get_ports *fixed_io_mio*]
-set_property  -dict {PACKAGE_PIN D8   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]]
-set_property  -dict {PACKAGE_PIN A5   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]]
-set_property  -dict {PACKAGE_PIN A8                  } [get_ports fixed_io_mio[ 2]]
-set_property  -dict {PACKAGE_PIN A7                  } [get_ports fixed_io_mio[ 3]]
-set_property  -dict {PACKAGE_PIN C8                  } [get_ports fixed_io_mio[ 4]]
-set_property  -dict {PACKAGE_PIN A9                  } [get_ports fixed_io_mio[ 5]]
-set_property  -dict {PACKAGE_PIN A10                 } [get_ports fixed_io_mio[ 6]]
-set_property  -dict {PACKAGE_PIN D9                  } [get_ports fixed_io_mio[ 7]]
-set_property  -dict {PACKAGE_PIN B6                  } [get_ports fixed_io_mio[ 8]]
-set_property  -dict {PACKAGE_PIN B5   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]]
-set_property  -dict {PACKAGE_PIN D6   PULLTYPE PULLUP} [get_ports fixed_io_mio[10]]
-set_property  -dict {PACKAGE_PIN B10  PULLTYPE PULLUP} [get_ports fixed_io_mio[11]]
-set_property  -dict {PACKAGE_PIN B7   PULLTYPE PULLUP} [get_ports fixed_io_mio[12]]
-set_property  -dict {PACKAGE_PIN C6   PULLTYPE PULLUP} [get_ports fixed_io_mio[13]]
-set_property  -dict {PACKAGE_PIN B9   PULLTYPE PULLUP} [get_ports fixed_io_mio[14]]
-set_property  -dict {PACKAGE_PIN D10  PULLTYPE PULLUP} [get_ports fixed_io_mio[15]]
-set_property  -dict {PACKAGE_PIN A15  PULLTYPE PULLUP} [get_ports fixed_io_mio[16]]
-set_property  -dict {PACKAGE_PIN D11  PULLTYPE PULLUP} [get_ports fixed_io_mio[17]]
-set_property  -dict {PACKAGE_PIN B15  PULLTYPE PULLUP} [get_ports fixed_io_mio[18]]
-set_property  -dict {PACKAGE_PIN C12  PULLTYPE PULLUP} [get_ports fixed_io_mio[19]]
-set_property  -dict {PACKAGE_PIN E15  PULLTYPE PULLUP} [get_ports fixed_io_mio[20]]
-set_property  -dict {PACKAGE_PIN C11  PULLTYPE PULLUP} [get_ports fixed_io_mio[21]]
-set_property  -dict {PACKAGE_PIN D15  PULLTYPE PULLUP} [get_ports fixed_io_mio[22]]
-set_property  -dict {PACKAGE_PIN A14  PULLTYPE PULLUP} [get_ports fixed_io_mio[23]]
-set_property  -dict {PACKAGE_PIN B14  PULLTYPE PULLUP} [get_ports fixed_io_mio[24]]
-set_property  -dict {PACKAGE_PIN C14  PULLTYPE PULLUP} [get_ports fixed_io_mio[25]]
-set_property  -dict {PACKAGE_PIN A13  PULLTYPE PULLUP} [get_ports fixed_io_mio[26]]
-set_property  -dict {PACKAGE_PIN D14  PULLTYPE PULLUP} [get_ports fixed_io_mio[27]]
-set_property  -dict {PACKAGE_PIN B12  PULLTYPE PULLUP} [get_ports fixed_io_mio[28]]
-set_property  -dict {PACKAGE_PIN D13  PULLTYPE PULLUP} [get_ports fixed_io_mio[29]]
-set_property  -dict {PACKAGE_PIN A12  PULLTYPE PULLUP} [get_ports fixed_io_mio[30]]
-set_property  -dict {PACKAGE_PIN C13  PULLTYPE PULLUP} [get_ports fixed_io_mio[31]]
+set_property  -dict {PACKAGE_PIN  G22   IOSTANDARD  LVCMOS33} [get_ports tx_enable_1a]
+set_property  -dict {PACKAGE_PIN  H22   IOSTANDARD  LVCMOS33} [get_ports tx_enable_2a]
+set_property  -dict {PACKAGE_PIN  A17   IOSTANDARD  LVCMOS33} [get_ports tx_enable_1b]
+set_property  -dict {PACKAGE_PIN  B16   IOSTANDARD  LVCMOS33} [get_ports tx_enable_2b]
 
-set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*]
-set_property SLEW SLOW [get_ports *fixed_io_ps*]
-set_property DRIVE 8 [get_ports *fixed_io_ps*]
-set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk]
-set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb]
+# antennae selects
 
-set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*]
-set_property SLEW FAST [get_ports *fixed_io_ddr_vr*]
-set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp]
-set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn]
+set_property  -dict {PACKAGE_PIN  C15   IOSTANDARD  LVCMOS33} [get_ports txrx1_antsel_v1]
+set_property  -dict {PACKAGE_PIN  B17   IOSTANDARD  LVCMOS33} [get_ports txrx1_antsel_v2]
+set_property  -dict {PACKAGE_PIN  A16   IOSTANDARD  LVCMOS33} [get_ports txrx2_antsel_v1]
+set_property  -dict {PACKAGE_PIN  E20   IOSTANDARD  LVCMOS33} [get_ports txrx2_antsel_v2]
+set_property  -dict {PACKAGE_PIN  E18   IOSTANDARD  LVCMOS33} [get_ports rx1_antsel_v1]
+set_property  -dict {PACKAGE_PIN  F18   IOSTANDARD  LVCMOS33} [get_ports rx1_antsel_v2]
+set_property  -dict {PACKAGE_PIN  F17   IOSTANDARD  LVCMOS33} [get_ports rx2_antsel_v1]
+set_property  -dict {PACKAGE_PIN  G17   IOSTANDARD  LVCMOS33} [get_ports rx2_antsel_v2]
 
-set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*]
-set_property SLEW FAST [get_ports *ddr_ck*]
-set_property PACKAGE_PIN N3 [get_ports ddr_ck_p]
-set_property PACKAGE_PIN N2 [get_ports ddr_ck_n]
+# fancy stuff
 
-set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*]
-set_property SLEW SLOW [get_ports *ddr_addr*]
-set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]]
-set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]]
-set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]]
-set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]]
-set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]]
-set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]]
-set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]]
-set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]]
-set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]]
-set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]]
-set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]]
-set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]]
-set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]]
-set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]]
-set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]]
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS18} [get_ports txrx1_tx_led]
+set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS18} [get_ports txrx1_rx_led]
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD  LVCMOS18} [get_ports txrx2_tx_led]
+set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS18} [get_ports txrx2_rx_led]
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS18} [get_ports rx1_rx_led]
+set_property  -dict {PACKAGE_PIN  AA11  IOSTANDARD  LVCMOS18} [get_ports rx2_rx_led]
 
-set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*]
-set_property SLEW SLOW [get_ports *ddr_ba*]
-set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]]
-set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]]
-set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]]
+# xtal tuning (ad5662)
 
-set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n]
-set_property SLEW FAST [get_ports ddr_reset_n]
-set_property PACKAGE_PIN L4 [get_ports ddr_reset_n]
-set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n]
-set_property SLEW SLOW [get_ports ddr_cs_n]
-set_property PACKAGE_PIN R2 [get_ports ddr_cs_n]
-set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n]
-set_property SLEW SLOW [get_ports ddr_ras_n]
-set_property PACKAGE_PIN R6 [get_ports ddr_ras_n]
-set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n]
-set_property SLEW SLOW [get_ports ddr_cas_n]
-set_property PACKAGE_PIN R5 [get_ports ddr_cas_n]
-set_property IOSTANDARD SSTL15 [get_ports ddr_we_n]
-set_property SLEW SLOW [get_ports ddr_we_n]
-set_property PACKAGE_PIN R3 [get_ports ddr_we_n]
-set_property IOSTANDARD SSTL15 [get_ports ddr_cke]
-set_property SLEW SLOW [get_ports ddr_cke]
-set_property PACKAGE_PIN L3 [get_ports ddr_cke]
-set_property IOSTANDARD SSTL15 [get_ports ddr_odt]
-set_property SLEW SLOW [get_ports ddr_odt]
-set_property PACKAGE_PIN K3 [get_ports ddr_odt]
+set_property  -dict {PACKAGE_PIN  K21   IOSTANDARD  LVCMOS18} [get_ports tcxo_dac_csn]
+set_property  -dict {PACKAGE_PIN  L22   IOSTANDARD  LVCMOS18} [get_ports tcxo_dac_clk]
+set_property  -dict {PACKAGE_PIN  L21   IOSTANDARD  LVCMOS18} [get_ports tcxo_dac_mosi]
+set_property  -dict {PACKAGE_PIN  M20   IOSTANDARD  LVCMOS18} [get_ports tcxo_clk]
 
-set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]]
-set_property SLEW FAST [get_ports *ddr_dq[*]]
-set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]]
-set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]]
-set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]]
-set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]]
-set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]]
-set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]]
-set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]]
-set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]]
-set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]]
-set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]]
-set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]]
-set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]]
-set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]]
-set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]]
-set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]]
-set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]]
-set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]]
-set_property SLEW FAST [get_ports *ddr_dm[*]]
-set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]]
-set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]]
-set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*]
-set_property SLEW FAST [get_ports *ddr_dqs*]
-set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]]
-set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]]
-set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]]
-set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]]
+# board power
 
+set_property  -dict {PACKAGE_PIN  A22   IOSTANDARD  LVCMOS33} [get_ports avr_csn]
+set_property  -dict {PACKAGE_PIN  D22   IOSTANDARD  LVCMOS33} [get_ports avr_clk]
+set_property  -dict {PACKAGE_PIN  A21   IOSTANDARD  LVCMOS33} [get_ports avr_mosi]
+set_property  -dict {PACKAGE_PIN  C22   IOSTANDARD  LVCMOS33} [get_ports avr_miso]
+set_property  -dict {PACKAGE_PIN  B22   IOSTANDARD  LVCMOS33} [get_ports avr_irq]
+
+set_property  -dict {PACKAGE_PIN  E21   IOSTANDARD  LVCMOS33} [get_ports pwr_switch]
+
+# gps-sync
+
+set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD  LVCMOS18} [get_ports pps_gps]
+set_property  -dict {PACKAGE_PIN  D18   IOSTANDARD  LVCMOS33} [get_ports pps_ext]
+
+# board-gpio
+
+set_property  -dict {PACKAGE_PIN  E16   IOSTANDARD  LVCMOS33} [get_ports gpio_bd[0]]
+set_property  -dict {PACKAGE_PIN  C18   IOSTANDARD  LVCMOS33} [get_ports gpio_bd[1]]
+set_property  -dict {PACKAGE_PIN  D17   IOSTANDARD  LVCMOS33} [get_ports gpio_bd[2]]
+set_property  -dict {PACKAGE_PIN  D16   IOSTANDARD  LVCMOS33} [get_ports gpio_bd[3]]
+set_property  -dict {PACKAGE_PIN  D15   IOSTANDARD  LVCMOS33} [get_ports gpio_bd[4]]
+set_property  -dict {PACKAGE_PIN  E15   IOSTANDARD  LVCMOS33} [get_ports gpio_bd[5]]
 
diff --git a/projects/usrpe31x/system_top.v b/projects/usrpe31x/system_top.v
index c74269645..dc7238fe5 100644
--- a/projects/usrpe31x/system_top.v
+++ b/projects/usrpe31x/system_top.v
@@ -46,10 +46,10 @@ module system_top (
   inout           ddr_ck_p,
   inout           ddr_cke,
   inout           ddr_cs_n,
-  inout   [ 1:0]  ddr_dm,
-  inout   [15:0]  ddr_dq,
-  inout   [ 1:0]  ddr_dqs_n,
-  inout   [ 1:0]  ddr_dqs_p,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
   inout           ddr_odt,
   inout           ddr_ras_n,
   inout           ddr_reset_n,
@@ -57,16 +57,11 @@ module system_top (
 
   inout           fixed_io_ddr_vrn,
   inout           fixed_io_ddr_vrp,
-  inout   [31:0]  fixed_io_mio,
+  inout   [53:0]  fixed_io_mio,
   inout           fixed_io_ps_clk,
   inout           fixed_io_ps_porb,
   inout           fixed_io_ps_srstb,
 
-  inout           iic_scl,
-  inout           iic_sda,
-
-  inout           gpio_bd,
-
   input           rx_clk_in,
   input           rx_frame_in,
   input   [11:0]  rx_data_in,
@@ -76,36 +71,177 @@ module system_top (
 
   output          enable,
   output          txnrx,
-  input           clk_out,
+  input           out_clk,
 
-  inout           gpio_resetb,
-  inout           gpio_en_agc,
-  inout   [ 3:0]  gpio_ctl,
-  inout   [ 7:0]  gpio_status,
+  output          gpio_resetb,
+  output          gpio_sync,
+  output          gpio_en_agc,
+  output  [ 3:0]  gpio_ctl,
+  input   [ 7:0]  gpio_status,
+  inout   [ 8:0]  gpio_rf,
+  output          gpio_tcxo_clk,
+  output          gpio_out_clk,
 
   output          spi_csn,
   output          spi_clk,
   output          spi_mosi,
-  input           spi_miso);
+  input           spi_miso,
+
+  output  [ 2:0]  tx_bandsel,
+  output  [ 2:0]  rx_bandsel_1,
+  output  [ 1:0]  rx_bandsel_1b,
+  output  [ 1:0]  rx_bandsel_1c,
+  output  [ 2:0]  rx_bandsel_2,
+  output  [ 1:0]  rx_bandsel_2b,
+  output  [ 1:0]  rx_bandsel_2c,
+
+  output          tx_enable_1a,
+  output          tx_enable_2a,
+  output          tx_enable_1b,
+  output          tx_enable_2b,
+
+  output          txrx1_antsel_v1,
+  output          txrx1_antsel_v2,
+  output          txrx2_antsel_v1,
+  output          txrx2_antsel_v2,
+  output          rx1_antsel_v1,
+  output          rx1_antsel_v2,
+  output          rx2_antsel_v1,
+  output          rx2_antsel_v2,
+
+  output          txrx1_tx_led,
+  output          txrx1_rx_led,
+  output          txrx2_tx_led,
+  output          txrx2_rx_led,
+  output          rx1_rx_led,
+  output          rx2_rx_led,
+
+  output          tcxo_dac_csn,
+  output          tcxo_dac_clk,
+  output          tcxo_dac_mosi,
+  input           tcxo_clk,
+
+  input           avr_csn,
+  input           avr_clk,
+  input           avr_mosi,
+  output          avr_miso,
+  output          avr_irq,
+
+  input           pwr_switch,
+
+  input           pps_gps,
+  input           pps_ext,
+
+  inout   [ 5:0]  gpio_bd);
 
   // internal signals
 
-  wire    [16:0]  gpio_i;
-  wire    [16:0]  gpio_o;
-  wire    [16:0]  gpio_t;
+  wire            pps_s;
+  wire    [31:0]  pl_gpio_i;
+  wire    [31:0]  pl_gpio_o;
+  wire    [31:0]  pl_gpio_t;
+  wire    [63:0]  ps_gpio_i;
+  wire    [63:0]  ps_gpio_o;
+  wire    [63:0]  ps_gpio_t;
+
+  // assignments
+
+  assign pps_s = pps_gps | pps_ext;
+  assign tcxo_dac_clk = spi_clk;
+  assign tcxo_dac_mosi = spi_mosi;
+
+  // gpio-rf (pl)
+
+  assign gpio_tcxo_clk = tcxo_clk;
+  assign gpio_out_clk = out_clk;
+  assign pl_gpio_i[31:9] = pl_gpio_o[31:9];
+
+  ad_iobuf #(.DATA_WIDTH(9)) i_iobuf_rf (
+    .dio_t (pl_gpio_t[8:0]),
+    .dio_i (pl_gpio_o[8:0]),
+    .dio_o (pl_gpio_i[8:0]),
+    .dio_p (gpio_rf));
+
+  // gpio[63:56] - antennae selects
+
+  assign ps_gpio_i[63:56] = ps_gpio_o[63:56];
+  assign txrx1_antsel_v1 = ps_gpio_o[63];
+  assign txrx1_antsel_v2 = ps_gpio_o[62];
+  assign txrx2_antsel_v1 = ps_gpio_o[61];
+  assign txrx2_antsel_v2 = ps_gpio_o[60];
+  assign rx1_antsel_v1 = ps_gpio_o[59];
+  assign rx1_antsel_v2 = ps_gpio_o[58];
+  assign rx2_antsel_v1 = ps_gpio_o[57];
+  assign rx2_antsel_v2 = ps_gpio_o[56];
+
+  // gpio[55:48] - antennae leds
+
+  assign ps_gpio_i[55:49] = ps_gpio_o[55:49];
+  assign txrx1_tx_led = ps_gpio_o[55];
+  assign txrx1_rx_led = ps_gpio_o[54];
+  assign txrx2_tx_led = ps_gpio_o[53];
+  assign txrx2_rx_led = ps_gpio_o[52];
+  assign rx1_rx_led = ps_gpio_o[51];
+  assign rx2_rx_led = ps_gpio_o[50];
+
+  // gpio[48:32] - ad9361
+
+  assign ps_gpio_i[48:44] = ps_gpio_o[48:44];
+  assign gpio_resetb = ps_gpio_o[46];
+  assign gpio_sync = ps_gpio_o[45];
+  assign gpio_en_agc = ps_gpio_o[44];
+
+  assign ps_gpio_i[43:40] = ps_gpio_o[43:40];
+  assign gpio_ctl = ps_gpio_o[43:40];
+
+  assign ps_gpio_i[39:32] = gpio_status;
+
+  // gpio[31:28] - tx_enable
+
+  assign ps_gpio_i[31:28] = ps_gpio_o[31:28];
+
+  assign tx_enable_1a = ps_gpio_o[31];
+  assign tx_enable_2a = ps_gpio_o[30];
+  assign tx_enable_1b = ps_gpio_o[29];
+  assign tx_enable_2b = ps_gpio_o[28];
+
+  // gpio[27:24] - tx_bandsel
+
+  assign ps_gpio_i[27:24] = ps_gpio_o[27:24];
+
+  assign tx_bandsel = ps_gpio_o[26:24];
+
+  // gpio[23:16] - rx_bandsel(1)
+
+  assign ps_gpio_i[23:16] = ps_gpio_o[23:16];
+
+  assign rx_bandsel_1 = ps_gpio_o[22:20];
+  assign rx_bandsel_1b = ps_gpio_o[19:18];
+  assign rx_bandsel_1c = ps_gpio_o[17:16];
+
+  // gpio[15:8] - rx_bandsel(2)
+
+  assign ps_gpio_i[15:8] = ps_gpio_o[15:8];
+
+  assign rx_bandsel_2 = ps_gpio_o[14:12];
+  assign rx_bandsel_2b = ps_gpio_o[11:10];
+  assign rx_bandsel_2c = ps_gpio_o[9:8];
+
+  // gpio[7:0] - board stuff (+ pwr_switch, avr_irq)
+
+  assign ps_gpio_i[7] = ps_gpio_o[7];
+  assign avr_irq = ps_gpio_o[7];
+
+  assign ps_gpio_i[6] = pwr_switch;
+
+  ad_iobuf #(.DATA_WIDTH(6)) i_iobuf_bd (
+    .dio_t (ps_gpio_t[5:0]),
+    .dio_i (ps_gpio_o[5:0]),
+    .dio_o (ps_gpio_i[5:0]),
+    .dio_p (gpio_bd));
 
   // instantiations
 
-  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
-    .dio_t (gpio_t[14:0]),
-    .dio_i (gpio_o[14:0]),
-    .dio_o (gpio_i[14:0]),
-    .dio_p ({ gpio_bd,            // 14:14
-              gpio_resetb,        // 13:13
-              gpio_en_agc,        // 12:12
-              gpio_ctl,           // 11: 8
-              gpio_status}));     //  7: 0
-
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),
@@ -129,11 +265,12 @@ module system_top (
     .fixed_io_ps_clk (fixed_io_ps_clk),
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gpio_i (gpio_i),
-    .gpio_o (gpio_o),
-    .gpio_t (gpio_t),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
+    .pl_gpio_i (pl_gpio_i),
+    .pl_gpio_o (pl_gpio_o),
+    .pl_gpio_t (pl_gpio_t),
+    .ps_gpio_i (ps_gpio_i),
+    .ps_gpio_o (ps_gpio_o),
+    .ps_gpio_t (ps_gpio_t),
     .ps_intr_00 (1'b0),
     .ps_intr_01 (1'b0),
     .ps_intr_02 (1'b0),
@@ -150,21 +287,23 @@ module system_top (
     .rx_clk_in (rx_clk_in),
     .rx_data_in (rx_data_in),
     .rx_frame_in (rx_frame_in),
-    .spi0_clk_i (1'b0),
-    .spi0_clk_o (spi_clk),
-    .spi0_csn_0_o (spi_csn),
-    .spi0_csn_1_o (),
-    .spi0_csn_2_o (),
-    .spi0_csn_i (1'b1),
-    .spi0_sdi_i (spi_miso),
-    .spi0_sdo_i (1'b0),
-    .spi0_sdo_o (spi_mosi),
+    .spi0_clk (spi_clk),
+    .spi0_csn_0 (spi_csn),
+    .spi0_csn_1 (tcxo_dac_csn),
+    .spi0_csn_2 (),
+    .spi0_miso (spi_miso),
+    .spi0_mosi (spi_mosi),
+    .spi1_clk (avr_clk),
+    .spi1_csn (avr_csn),
+    .spi1_miso (avr_miso),
+    .spi1_mosi (avr_mosi),
+    .tdd_sync (pps_s),
     .tx_clk_out (tx_clk_out),
     .tx_data_out (tx_data_out),
     .tx_frame_out (tx_frame_out),
     .txnrx (txnrx),
-    .up_enable (gpio_o[15]),
-    .up_txnrx (gpio_o[16]));
+    .up_enable (ps_gpio_o[47]),
+    .up_txnrx (ps_gpio_o[48]));
 
 endmodule
 

From 707038937a3f7484378f5c3c1b75434a16cce9d8 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 21 Oct 2016 16:52:48 +0300
Subject: [PATCH 628/972] alt_serdes: Add additional parameters

Add additional parameters to keep the top of ad_serdes_* modules
consistant through differente carriers.
---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 51 +++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index abd523dc9..2ea54f709 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -38,6 +38,57 @@ set_parameter_property CLKIN_FREQUENCY UNITS None
 set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
 set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
 
+# these paramteres are needed just because of cross-platform requirments
+# are NOT used in the core
+
+add_parameter DEVICE_TYPE INTEGER 0
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER false
+
+add_parameter MMCM_OR_BUFR_N INTEGER 0
+set_parameter_property MMCM_OR_BUFR_N DEFAULT_VALUE 0
+set_parameter_property MMCM_OR_BUFR_N DISPLAY_NAME MMCM_OR_BUFIO_N
+set_parameter_property MMCM_OR_BUFR_N TYPE INTEGER
+set_parameter_property MMCM_OR_BUFR_N UNITS None
+set_parameter_property MMCM_OR_BUFR_N HDL_PARAMETER false
+
+add_parameter MMCM_CLKIN_PERIOD FLOAT 0
+set_parameter_property MMCM_CLKIN_PERIOD DEFAULT_VALUE 1.667
+set_parameter_property MMCM_CLKIN_PERIOD DISPLAY_NAME MMCM_CLKIN_PERIOD
+set_parameter_property MMCM_CLKIN_PERIOD TYPE INTEGER
+set_parameter_property MMCM_CLKIN_PERIOD UNITS None
+set_parameter_property MMCM_CLKIN_PERIOD HDL_PARAMETER false
+
+add_parameter MMCM_VCO_DIV INTEGER 0
+set_parameter_property MMCM_VCO_DIV DEFAULT_VALUE 2
+set_parameter_property MMCM_VCO_DIV DISPLAY_NAME MMCM_VCO_DIV
+set_parameter_property MMCM_VCO_DIV TYPE INTEGER
+set_parameter_property MMCM_VCO_DIV UNITS None
+set_parameter_property MMCM_VCO_DIV HDL_PARAMETER false
+
+add_parameter MMCM_VCO_MUL INTEGER 0
+set_parameter_property MMCM_VCO_MUL DEFAULT_VALUE 4
+set_parameter_property MMCM_VCO_MUL DISPLAY_NAME MMCM_VCO_MUL
+set_parameter_property MMCM_VCO_MUL TYPE INTEGER
+set_parameter_property MMCM_VCO_MUL UNITS None
+set_parameter_property MMCM_VCO_MUL HDL_PARAMETER false
+
+add_parameter MMCM_CLK0_DIV INTEGER 0
+set_parameter_property MMCM_CLK0_DIV DEFAULT_VALUE 2
+set_parameter_property MMCM_CLK0_DIV DISPLAY_NAME MMCM_CLK0_DIV
+set_parameter_property MMCM_CLK0_DIV TYPE INTEGER
+set_parameter_property MMCM_CLK0_DIV UNITS None
+set_parameter_property MMCM_CLK0_DIV HDL_PARAMETER false
+
+add_parameter MMCM_CLK1_DIV INTEGER 0
+set_parameter_property MMCM_CLK1_DIV DEFAULT_VALUE 8
+set_parameter_property MMCM_CLK1_DIV DISPLAY_NAME MMCM_CLK1_DIV
+set_parameter_property MMCM_CLK1_DIV TYPE INTEGER
+set_parameter_property MMCM_CLK1_DIV UNITS None
+set_parameter_property MMCM_CLK1_DIV HDL_PARAMETER false
+
 proc p_alt_serdes {} {
 
   set m_mode [get_parameter_value "MODE"]

From aa46de5e5e10396536e6e69ba57bb12b9f9df5a1 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 21 Oct 2016 16:55:35 +0300
Subject: [PATCH 629/972] adi_ip_alt: Add ad_generate_module_inst proc

Add a tcl process, which can be used to generate custom module
names during the generation phase. This will be used to create
different ad_serdes_clk module, in case when independent IOPLLs are
needed for TX and RX.
---
 library/scripts/adi_ip_alt.tcl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl
index f8e36343d..3fcc3cba8 100644
--- a/library/scripts/adi_ip_alt.tcl
+++ b/library/scripts/adi_ip_alt.tcl
@@ -70,3 +70,22 @@ proc ad_conduit {if_name if_port port dir width} {
   add_interface_port $if_name $port $if_port $dir $width
 }
 
+proc ad_generate_module_inst { inst_name mark source_file target_file } {
+
+  set fp_source [open $source_file "r"]
+  set fp_target [open $target_file "w+"]
+
+  fconfigure $fp_source -buffering line
+
+  while { [gets $fp_source data] >= 0 } {
+
+    # update the required module name
+    regsub $inst_name $data "&_$mark" data
+    puts $data
+    puts $fp_target $data
+  }
+
+  close $fp_source
+  close $fp_target
+}
+

From 3f3606d3181e63805674162152b5ff3b80efb8d5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 24 Oct 2016 10:54:40 +0300
Subject: [PATCH 630/972] axi_ad9122: Add Altera support for the core

---
 library/axi_ad9122/axi_ad9122_constr.sdc |   1 +
 library/axi_ad9122/axi_ad9122_hw.tcl     | 220 +++++++++++++++++++++++
 2 files changed, 221 insertions(+)
 create mode 100644 library/axi_ad9122/axi_ad9122_constr.sdc
 create mode 100644 library/axi_ad9122/axi_ad9122_hw.tcl

diff --git a/library/axi_ad9122/axi_ad9122_constr.sdc b/library/axi_ad9122/axi_ad9122_constr.sdc
new file mode 100644
index 000000000..ca63ab22f
--- /dev/null
+++ b/library/axi_ad9122/axi_ad9122_constr.sdc
@@ -0,0 +1 @@
+# false path definitions will come here
diff --git a/library/axi_ad9122/axi_ad9122_hw.tcl b/library/axi_ad9122/axi_ad9122_hw.tcl
new file mode 100644
index 000000000..8d17ab522
--- /dev/null
+++ b/library/axi_ad9122/axi_ad9122_hw.tcl
@@ -0,0 +1,220 @@
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+set_module_property NAME axi_ad9122
+set_module_property DESCRIPTION "AXI AD9122 Interface"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME axi_ad9122
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "ad9122_fileset_callback" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL axi_ad9122
+
+add_fileset_file ad_mul.v                 VERILOG PATH  $ad_hdl_dir/library/xilinx/common/ad_mul.v
+add_fileset_file ad_dds_sine.v            VERILOG PATH  $ad_hdl_dir/library/common/ad_dds_sine.v
+add_fileset_file ad_dds_1.v               VERILOG PATH  $ad_hdl_dir/library/common/ad_dds_1.v
+add_fileset_file ad_dds.v                 VERILOG PATH  $ad_hdl_dir/library/common/ad_dds.v
+add_fileset_file ad_rst.v                 VERILOG PATH  $ad_hdl_dir/library/common/ad_rst.v
+add_fileset_file ad_mmcm_drp.v            VERILOG PATH  $ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v
+add_fileset_file ad_serdes_out.v          VERILOG PATH  $ad_hdl_dir/library/xilinx/common/ad_serdes_out.v
+add_fileset_file up_axi.v                 VERILOG PATH  $ad_hdl_dir/library/common/up_axi.v
+add_fileset_file up_xfer_cntrl.v          VERILOG PATH  $ad_hdl_dir/library/common/up_xfer_cntrl.v
+add_fileset_file up_xfer_status.v         VERILOG PATH  $ad_hdl_dir/library/common/up_xfer_status.v
+add_fileset_file up_clock_mon.v           VERILOG PATH  $ad_hdl_dir/library/common/up_clock_mon.v
+add_fileset_file up_dac_common.v          VERILOG PATH  $ad_hdl_dir/library/common/up_dac_common.v
+add_fileset_file up_dac_channel.v         VERILOG PATH  $ad_hdl_dir/library/common/up_dac_channel.v
+add_fileset_file axi_ad9122_channel.v     VERILOG PATH  axi_ad9122_channel.v
+add_fileset_file axi_ad9122_core.v        VERILOG PATH  axi_ad9122_core.v
+add_fileset_file axi_ad9122_if.v          VERILOG PATH  axi_ad9122_if.v
+add_fileset_file axi_ad9122.v             VERILOG PATH  axi_ad9122.v TOP_LEVEL_FILE
+add_fileset_file ad_axi_ip_constr.sdc     SDC     PATH  $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file axi_ad9122_constr.sdc    SDC     PATH  axi_ad9122_constr.sdc
+
+# paramter for fileset callback
+
+add_parameter HDL_LIB_PATH STRING $ad_hdl_dir
+set_parameter_property HDL_LIB_PATH TYPE STRING
+set_parameter_property HDL_LIB_PATH HDL_PARAMETER false
+
+# parameters
+
+add_parameter ID INTEGER 0
+set_parameter_property ID DEFAULT_VALUE 0
+set_parameter_property ID DISPLAY_NAME ID
+set_parameter_property ID TYPE INTEGER
+set_parameter_property ID UNITS None
+set_parameter_property ID HDL_PARAMETER true
+
+add_parameter DEVICE_TYPE INTEGER 0
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
+add_parameter SERDES_OR_DDR_N INTEGER 0
+set_parameter_property SERDES_OR_DDR_N DEFAULT_VALUE 1
+set_parameter_property SERDES_OR_DDR_N DISPLAY_NAME SERDES_OR_DDR_N
+set_parameter_property SERDES_OR_DDR_N TYPE INTEGER
+set_parameter_property SERDES_OR_DDR_N UNITS None
+set_parameter_property SERDES_OR_DDR_N HDL_PARAMETER true
+
+add_parameter MMCM_OR_BUFIO_N INTEGER 0
+set_parameter_property MMCM_OR_BUFIO_N DEFAULT_VALUE 0
+set_parameter_property MMCM_OR_BUFIO_N DISPLAY_NAME MMCM_OR_BUFIO_N
+set_parameter_property MMCM_OR_BUFIO_N TYPE INTEGER
+set_parameter_property MMCM_OR_BUFIO_N UNITS None
+set_parameter_property MMCM_OR_BUFIO_N HDL_PARAMETER false
+
+add_parameter MMCM_CLKIN_PERIOD FLOAT 0
+set_parameter_property MMCM_CLKIN_PERIOD DEFAULT_VALUE 1.667
+set_parameter_property MMCM_CLKIN_PERIOD DISPLAY_NAME MMCM_CLKIN_PERIOD
+set_parameter_property MMCM_CLKIN_PERIOD TYPE INTEGER
+set_parameter_property MMCM_CLKIN_PERIOD UNITS None
+set_parameter_property MMCM_CLKIN_PERIOD HDL_PARAMETER false
+
+add_parameter MMCM_VCO_DIV INTEGER 0
+set_parameter_property MMCM_VCO_DIV DEFAULT_VALUE 2
+set_parameter_property MMCM_VCO_DIV DISPLAY_NAME MMCM_VCO_DIV
+set_parameter_property MMCM_VCO_DIV TYPE INTEGER
+set_parameter_property MMCM_VCO_DIV UNITS None
+set_parameter_property MMCM_VCO_DIV HDL_PARAMETER false
+
+add_parameter MMCM_VCO_MUL INTEGER 0
+set_parameter_property MMCM_VCO_MUL DEFAULT_VALUE 4
+set_parameter_property MMCM_VCO_MUL DISPLAY_NAME MMCM_VCO_MUL
+set_parameter_property MMCM_VCO_MUL TYPE INTEGER
+set_parameter_property MMCM_VCO_MUL UNITS None
+set_parameter_property MMCM_VCO_MUL HDL_PARAMETER false
+
+add_parameter MMCM_CLK0_DIV INTEGER 0
+set_parameter_property MMCM_CLK0_DIV DEFAULT_VALUE 2
+set_parameter_property MMCM_CLK0_DIV DISPLAY_NAME MMCM_CLK0_DIV
+set_parameter_property MMCM_CLK0_DIV TYPE INTEGER
+set_parameter_property MMCM_CLK0_DIV UNITS None
+set_parameter_property MMCM_CLK0_DIV HDL_PARAMETER false
+
+add_parameter MMCM_CLK1_DIV INTEGER 0
+set_parameter_property MMCM_CLK1_DIV DEFAULT_VALUE 8
+set_parameter_property MMCM_CLK1_DIV DISPLAY_NAME MMCM_CLK1_DIV
+set_parameter_property MMCM_CLK1_DIV TYPE INTEGER
+set_parameter_property MMCM_CLK1_DIV UNITS None
+set_parameter_property MMCM_CLK1_DIV HDL_PARAMETER false
+
+add_parameter DAC_DATAPATH_DISABLE INTEGER 0
+set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 8
+set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
+set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
+set_parameter_property DAC_DATAPATH_DISABLE UNITS None
+set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
+
+add_parameter IO_DELAY_GROUP INTEGER 0
+set_parameter_property IO_DELAY_GROUP DEFAULT_VALUE 8
+set_parameter_property IO_DELAY_GROUP DISPLAY_NAME IO_DELAY_GROUP
+set_parameter_property IO_DELAY_GROUP TYPE INTEGER
+set_parameter_property IO_DELAY_GROUP UNITS None
+set_parameter_property IO_DELAY_GROUP HDL_PARAMETER true
+
+# axi4 slave
+
+add_interface s_axi_clock clock end
+add_interface_port s_axi_clock s_axi_aclk clk Input 1
+
+add_interface s_axi_reset reset end
+set_interface_property s_axi_reset associatedClock s_axi_clock
+add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
+
+add_interface s_axi axi4lite end
+set_interface_property s_axi associatedClock s_axi_clock
+set_interface_property s_axi associatedReset s_axi_reset
+add_interface_port s_axi s_axi_awvalid awvalid Input 1
+add_interface_port s_axi s_axi_awaddr awaddr Input 16
+add_interface_port s_axi s_axi_awprot awprot Input 3
+add_interface_port s_axi s_axi_awready awready Output 1
+add_interface_port s_axi s_axi_wvalid wvalid Input 1
+add_interface_port s_axi s_axi_wdata wdata Input 32
+add_interface_port s_axi s_axi_wstrb wstrb Input 4
+add_interface_port s_axi s_axi_wready wready Output 1
+add_interface_port s_axi s_axi_bvalid bvalid Output 1
+add_interface_port s_axi s_axi_bresp bresp Output 2
+add_interface_port s_axi s_axi_bready bready Input 1
+add_interface_port s_axi s_axi_arvalid arvalid Input 1
+add_interface_port s_axi s_axi_araddr araddr Input 16
+add_interface_port s_axi s_axi_arprot arprot Input 3
+add_interface_port s_axi s_axi_arready arready Output 1
+add_interface_port s_axi s_axi_rvalid rvalid Output 1
+add_interface_port s_axi s_axi_rresp rresp Output 2
+add_interface_port s_axi s_axi_rdata rdata Output 32
+add_interface_port s_axi s_axi_rready rready Input 1
+
+# dac device interface
+
+add_interface device_if conduit end
+set_interface_property device_if associatedClock none
+set_interface_property device_if associatedReset none
+
+add_interface_port device_if dac_clk_in_p dac_clk_in_p Input 1
+add_interface_port device_if dac_clk_in_n dac_clk_in_n Input 1
+add_interface_port device_if dac_clk_out_p dac_clk_out_p Output 1
+add_interface_port device_if dac_clk_out_n dac_clk_out_n Output 1
+add_interface_port device_if dac_frame_out_p dac_frame_out_p Output 1
+add_interface_port device_if dac_frame_out_n dac_frame_out_n Output 1
+add_interface_port device_if dac_data_out_p dac_data_out_p Output 16
+add_interface_port device_if dac_data_out_n dac_data_out_n Output 16
+
+add_interface_port device_if dac_sync_out dac_sync_out Output 1
+add_interface_port device_if dac_sync_in  dac_sync_in  Input 1
+
+# dma interface
+
+ad_alt_intf clock dac_div_clk Output 1
+
+add_interface dac_ch_0 conduit end
+add_interface_port dac_ch_0 dac_valid_0   valid  Output 1
+add_interface_port dac_ch_0 dac_enable_0  enable Output 1
+add_interface_port dac_ch_0 dac_ddata_0   data   Input 64
+set_interface_property dac_ch_0 associatedClock if_dac_div_clk
+set_interface_property dac_ch_0 associatedReset none
+
+add_interface dac_ch_1 conduit end
+add_interface_port dac_ch_1 dac_valid_1   valid  Output 1
+add_interface_port dac_ch_1 dac_enable_1  enable Output 1
+add_interface_port dac_ch_1 dac_ddata_1   data   Input 64
+set_interface_property dac_ch_1 associatedClock if_dac_div_clk
+set_interface_property dac_ch_1 associatedReset none
+
+ad_alt_intf signal dac_dovf input 1 ovf
+ad_alt_intf signal dac_dunf input 1 unf
+
+# SERDES instances and configurations
+
+add_hdl_instance alt_serdes_clk_core_tx alt_serdes
+set_instance_parameter_value alt_serdes_clk_core_tx {MODE} {CLK}
+set_instance_parameter_value alt_serdes_clk_core_tx {DDR_OR_SDR_N} {1}
+set_instance_parameter_value alt_serdes_clk_core_tx {SERDES_FACTOR} {8}
+set_instance_parameter_value alt_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0}
+
+add_hdl_instance alt_serdes_out_core alt_serdes
+set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
+set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
+set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {8}
+set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {500.0}
+
+# fileset callback to create the SERDES CLOCK instances
+
+proc ad9122_fileset_callback { entityName } {
+
+  send_message INFO "Generating SERDES clock instance for $entityName"
+  set ad_hdl_dir [get_parameter_value HDL_LIB_PATH]
+  exec mkdir -p generated
+
+  # copy the generic ad_serdes_clk into working directory with modified ALT_IOPLL instance name
+  ad_generate_module_inst "alt_serdes_clk_core" "tx" $ad_hdl_dir/library/altera/common/ad_serdes_clk.v generated/ad_serdes_clk.v
+
+  add_fileset_file  generated/ad_serdes_clk.v   VERILOG PATH  generated/ad_serdes_clk.v
+}
+

From de0c487195f7da042efc8d0aac87128e407c1662 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 24 Oct 2016 10:55:39 +0300
Subject: [PATCH 631/972] axi_ad9684: Add Altera support for the core

---
 library/axi_ad9684/axi_ad9684_constr.sdc |   0
 library/axi_ad9684/axi_ad9684_hw.tcl     | 170 +++++++++++++++++++++++
 2 files changed, 170 insertions(+)
 create mode 100644 library/axi_ad9684/axi_ad9684_constr.sdc
 create mode 100644 library/axi_ad9684/axi_ad9684_hw.tcl

diff --git a/library/axi_ad9684/axi_ad9684_constr.sdc b/library/axi_ad9684/axi_ad9684_constr.sdc
new file mode 100644
index 000000000..e69de29bb
diff --git a/library/axi_ad9684/axi_ad9684_hw.tcl b/library/axi_ad9684/axi_ad9684_hw.tcl
new file mode 100644
index 000000000..cc88b7c67
--- /dev/null
+++ b/library/axi_ad9684/axi_ad9684_hw.tcl
@@ -0,0 +1,170 @@
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+set_module_property NAME axi_ad9684
+set_module_property DESCRIPTION "AXI ad9684 Interface"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME axi_ad9684
+set_module_property ELABORATION_CALLBACK p_axi_ad9684
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "ad9684_fileset_callback" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL axi_ad9684
+
+add_fileset_file  ad_rst.v               VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
+add_fileset_file  ad_serdes_in.v         VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v
+add_fileset_file  ad_datafmt.v           VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
+add_fileset_file  ad_pnmon.v             VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
+add_fileset_file  up_xfer_status.v       VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
+add_fileset_file  up_xfer_cntrl.v        VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
+add_fileset_file  up_clock_mon.v         VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
+add_fileset_file  up_delay_cntrl.v       VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
+add_fileset_file  up_adc_common.v        VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
+add_fileset_file  up_adc_channel.v       VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
+add_fileset_file  up_axi.v               VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
+add_fileset_file  axi_ad9684_pnmon.v     VERILOG PATH axi_ad9684_pnmon.v
+add_fileset_file  axi_ad9684_if.v        VERILOG PATH axi_ad9684_if.v
+add_fileset_file  axi_ad9684_channel.v   VERILOG PATH axi_ad9684_channel.v
+add_fileset_file  axi_ad9684.v           VERILOG PATH axi_ad9684.v TOP_LEVEL_FILE
+add_fileset_file  ad_axi_ip_constr.sdc   SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file  axi_ad9684_constr.sdc  SDC     PATH axi_ad9684_constr.sdc
+
+# paramter for fileset callback
+
+add_parameter HDL_LIB_PATH STRING $ad_hdl_dir
+set_parameter_property HDL_LIB_PATH TYPE STRING
+set_parameter_property HDL_LIB_PATH HDL_PARAMETER false
+
+# parameters
+
+add_parameter DEVICE_TYPE INTEGER 0
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE DESCRIPTION "Specify the FPGA device type"
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
+add_parameter DAC_DATAPATH_DISABLE INTEGER 0
+set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
+set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
+set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
+set_parameter_property DAC_DATAPATH_DISABLE DESCRIPTION "If active, all the data processing logic will be left out from the IP"
+set_parameter_property DAC_DATAPATH_DISABLE UNITS None
+set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
+
+add_parameter OR_STATUS INTEGER 1
+set_parameter_property OR_STATUS DEFAULT_VALUE 1
+set_parameter_property OR_STATUS DISPLAY_NAME OR_STATUS
+set_parameter_property OR_STATUS TYPE INTEGER
+set_parameter_property OR_STATUS DESCRIPTION "This parameter enables the OVER RANGE line at the physical interface"
+set_parameter_property OR_STATUS UNITS None
+set_parameter_property OR_STATUS HDL_PARAMETER true
+
+# axi4 slave
+
+add_interface s_axi_clock clock end
+add_interface_port s_axi_clock s_axi_aclk clk Input 1
+
+add_interface s_axi_reset reset end
+set_interface_property s_axi_reset associatedClock s_axi_clock
+add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
+
+add_interface s_axi axi4lite end
+set_interface_property s_axi associatedClock s_axi_clock
+set_interface_property s_axi associatedReset s_axi_reset
+add_interface_port s_axi s_axi_awvalid awvalid Input 1
+add_interface_port s_axi s_axi_awaddr awaddr Input 16
+add_interface_port s_axi s_axi_awprot awprot Input 3
+add_interface_port s_axi s_axi_awready awready Output 1
+add_interface_port s_axi s_axi_wvalid wvalid Input 1
+add_interface_port s_axi s_axi_wdata wdata Input 32
+add_interface_port s_axi s_axi_wstrb wstrb Input 4
+add_interface_port s_axi s_axi_wready wready Output 1
+add_interface_port s_axi s_axi_bvalid bvalid Output 1
+add_interface_port s_axi s_axi_bresp bresp Output 2
+add_interface_port s_axi s_axi_bready bready Input 1
+add_interface_port s_axi s_axi_arvalid arvalid Input 1
+add_interface_port s_axi s_axi_araddr araddr Input 16
+add_interface_port s_axi s_axi_arprot arprot Input 3
+add_interface_port s_axi s_axi_arready arready Output 1
+add_interface_port s_axi s_axi_rvalid rvalid Output 1
+add_interface_port s_axi s_axi_rresp rresp Output 2
+add_interface_port s_axi s_axi_rdata rdata Output 32
+add_interface_port s_axi s_axi_rready rready Input 1
+
+# adc device interface
+
+add_interface device_if conduit end
+set_interface_property device_if associatedClock none
+set_interface_property device_if associatedReset none
+
+add_interface_port device_if adc_clk_in_p adc_clk_in_p Input 1
+add_interface_port device_if adc_clk_in_n adc_clk_in_n Input 1
+add_interface_port device_if adc_data_in_p adc_data_in_p Input 14
+add_interface_port device_if adc_data_in_n adc_data_in_n Input 14
+
+# dma interface
+
+ad_alt_intf clock adc_clk output 1
+ad_alt_intf reset adc_rst output 1 if_adc_clk
+
+add_interface adc_ch_0 conduit end
+add_interface_port adc_ch_0 adc_valid_0   valid   Output 1
+add_interface_port adc_ch_0 adc_enable_0  enable  Output 1
+add_interface_port adc_ch_0 adc_ddata_0   data    Output 32
+set_interface_property adc_ch_0 associatedClock if_adc_clk
+set_interface_property adc_ch_0 associatedReset none
+
+add_interface adc_ch_1 conduit end
+add_interface_port adc_ch_1 adc_valid_1   valid   Output 1
+add_interface_port adc_ch_1 adc_enable_1  enable  Output 1
+add_interface_port adc_ch_1 adc_ddata_1   data    Output 32
+set_interface_property adc_ch_1 associatedClock if_adc_clk
+set_interface_property adc_ch_1 associatedReset none
+
+ad_alt_intf signal adc_dovf input 1 ovf
+ad_alt_intf signal adc_dunf input 1 unf
+
+# SERDES instances and configurations
+
+add_hdl_instance alt_serdes_clk_core_rx alt_serdes
+set_instance_parameter_value alt_serdes_clk_core_rx {MODE} {CLK}
+set_instance_parameter_value alt_serdes_clk_core_rx {DDR_OR_SDR_N} {1}
+set_instance_parameter_value alt_serdes_clk_core_rx {SERDES_FACTOR} {4}
+set_instance_parameter_value alt_serdes_clk_core_rx {CLKIN_FREQUENCY} {500.0}
+
+add_hdl_instance alt_serdes_in_core alt_serdes
+set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
+set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
+set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
+set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {500.0}
+
+proc p_axi_ad9684 {} {
+
+  set or_status [get_parameter_value OR_STATUS]
+
+  if {$or_status == 1} {
+    add_interface_port device_if adc_data_or_p adc_data_or_p Input 1
+    add_interface_port device_if adc_data_or_n adc_data_or_n Input 1
+  }
+}
+
+# fileset callback to create the SERDES CLOCK instances
+
+proc ad9684_fileset_callback { entityName } {
+
+  send_message INFO "Generating SERDES clock instance for $entityName"
+  set ad_hdl_dir [get_parameter_value HDL_LIB_PATH]
+  exec mkdir -p generated
+
+  # copy the generic ad_serdes_clk into working directory with modified ALT_IOPLL instance name
+  ad_generate_module_inst "alt_serdes_clk_core" "rx" $ad_hdl_dir/library/altera/common/ad_serdes_clk.v generated/ad_serdes_clk.v
+
+  add_fileset_file  generated/ad_serdes_clk.v   VERILOG PATH  generated/ad_serdes_clk.v
+}
+

From 7e57a89ce58ca0c58284f80bb87518b0f8b093a9 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 24 Oct 2016 10:59:07 +0300
Subject: [PATCH 632/972] daq1: Add support for A10GX

---
 projects/daq1/Makefile                 |   3 +
 projects/daq1/a10gx/Makefile           | 140 ++++++++++++++++++
 projects/daq1/a10gx/system_constr.sdc  |   8 +
 projects/daq1/a10gx/system_project.tcl | 137 +++++++++++++++++
 projects/daq1/a10gx/system_qsys.tcl    |   6 +
 projects/daq1/a10gx/system_top.v       | 195 +++++++++++++++++++++++++
 projects/daq1/common/daq1_qsys.tcl     | 139 ++++++++++++++++++
 7 files changed, 628 insertions(+)
 create mode 100644 projects/daq1/a10gx/Makefile
 create mode 100644 projects/daq1/a10gx/system_constr.sdc
 create mode 100644 projects/daq1/a10gx/system_project.tcl
 create mode 100644 projects/daq1/a10gx/system_qsys.tcl
 create mode 100644 projects/daq1/a10gx/system_top.v
 create mode 100644 projects/daq1/common/daq1_qsys.tcl

diff --git a/projects/daq1/Makefile b/projects/daq1/Makefile
index 5b866a1ac..9d9772a62 100644
--- a/projects/daq1/Makefile
+++ b/projects/daq1/Makefile
@@ -7,14 +7,17 @@
 
 .PHONY: all clean clean-all 
 all:
+	-make -C a10gx all
 	-make -C zc706 all
 
 
 clean: 
+	make -C a10gx clean
 	make -C zc706 clean
 
 
 clean-all:
+	make -C a10gx clean-all
 	make -C zc706 clean-all
 
 ####################################################################################
diff --git a/projects/daq1/a10gx/Makefile b/projects/daq1/a10gx/Makefile
new file mode 100644
index 000000000..3ce97770a
--- /dev/null
+++ b/projects/daq1/a10gx/Makefile
@@ -0,0 +1,140 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+ifeq ($(MMU),)
+  MMU := 1
+endif
+
+export ALT_NIOS_MMU_ENABLED := $(MMU)
+
+M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.sdc
+M_DEPS += ../common/daq1_qsys.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/axi_ad9122/axi_ad9122.v
+M_DEPS += ../../../library/axi_ad9122/axi_ad9122_channel.v
+M_DEPS += ../../../library/axi_ad9122/axi_ad9122_core.v
+M_DEPS += ../../../library/axi_ad9122/axi_ad9122_hw.tcl
+M_DEPS += ../../../library/axi_ad9122/axi_ad9122_if.v
+M_DEPS += ../../../library/axi_ad9684/axi_ad9684.v
+M_DEPS += ../../../library/axi_ad9684/axi_ad9684_channel.v
+M_DEPS += ../../../library/axi_ad9684/axi_ad9684_hw.tcl
+M_DEPS += ../../../library/axi_ad9684/axi_ad9684_if.v
+M_DEPS += ../../../library/axi_ad9684/axi_ad9684_pnmon.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+M_DEPS += ../../../library/xilinx/common/ad_mmcm_drp.v
+M_DEPS += ../../../library/xilinx/common/ad_mul.v
+M_DEPS += ../../../library/xilinx/common/ad_serdes_clk.v
+M_DEPS += ../../../library/xilinx/common/ad_serdes_in.v
+M_DEPS += ../../../library/xilinx/common/ad_serdes_out.v
+
+
+M_ALTERA := quartus_sh --64bit -t 
+
+
+M_FLIST += *.log
+M_FLIST += *_INFO.txt
+M_FLIST += *_dump.txt
+M_FLIST += db
+M_FLIST += *.asm.rpt
+M_FLIST += *.done
+M_FLIST += *.eda.rpt
+M_FLIST += *.fit.*
+M_FLIST += *.map.*
+M_FLIST += *.sta.*
+M_FLIST += *.qsf
+M_FLIST += *.qpf
+M_FLIST += *.qws
+M_FLIST += *.sof
+M_FLIST += *.cdf
+M_FLIST += *.sld
+M_FLIST += *.qdf
+M_FLIST += hc_output
+M_FLIST += system_bd
+M_FLIST += hps_isw_handoff
+M_FLIST += hps_sdram_*.csv
+M_FLIST += *ddr3_*.csv
+M_FLIST += incremental_db
+M_FLIST += reconfig_mif
+M_FLIST += *.sopcinfo
+M_FLIST +=  *.jdi
+M_FLIST += *.pin
+M_FLIST += *_summary.csv
+M_FLIST += *.dpf
+
+
+
+.PHONY: all clean clean-all
+all: daq1_a10gx.sof
+
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+daq1_a10gx.sof: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_ALTERA) system_project.tcl  >> daq1_a10gx_quartus.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/projects/daq1/a10gx/system_constr.sdc b/projects/daq1/a10gx/system_constr.sdc
new file mode 100644
index 000000000..b47af1682
--- /dev/null
+++ b/projects/daq1/a10gx/system_constr.sdc
@@ -0,0 +1,8 @@
+
+create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
+create_clock -period "2.000 ns"   -name rx_clk_500mhz       [get_ports {adc_clk_in}]
+create_clock -period "2.000 ns"   -name tx_clk_500mhz       [get_ports {dac_clk_in}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
diff --git a/projects/daq1/a10gx/system_project.tcl b/projects/daq1/a10gx/system_project.tcl
new file mode 100644
index 000000000..64233ee76
--- /dev/null
+++ b/projects/daq1/a10gx/system_project.tcl
@@ -0,0 +1,137 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new daq1_a10gx -overwrite
+
+source "../../common/a10gx/a10gx_system_assign.tcl"
+
+set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name QSYS_FILE system_bd.qsys
+
+set_global_assignment -name SDC_FILE system_constr.sdc
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
+
+# physical interface
+
+
+set_location_assignment PIN_AC28  -to dac_clk_in                  ; ##  G02  FMC_LPC_CLK1_M2C_P
+set_location_assignment PIN_AD28  -to "dac_clk_in(n)"             ; ##  G03  FMC_LPC_CLK1_M2C_N
+set_location_assignment PIN_AF29  -to dac_clk_out                 ; ##  G27  FMC_LPC_LA25_P
+set_location_assignment PIN_AG29  -to "dac_clk_out(n)"            ; ##  G28  FMC_LPC_LA25_N
+set_location_assignment PIN_Y26   -to dac_frame_out               ; ##  H37  FMC_LPC_LA32_P
+set_location_assignment PIN_Y27   -to "dac_frame_out(n)"          ; ##  H38  FMC_LPC_LA32_N
+set_location_assignment PIN_AB15  -to dac_data_out[0]             ; ##  H19  FMC_LPC_LA15_P
+set_location_assignment PIN_AB14  -to "dac_data_out[0](n)"        ; ##  H20  FMC_LPC_LA15_N
+set_location_assignment PIN_AG26  -to dac_data_out[1]             ; ##  G21  FMC_LPC_LA20_P
+set_location_assignment PIN_AG27  -to "dac_data_out[1](n)"        ; ##  G22  FMC_LPC_LA20_N
+set_location_assignment PIN_AH26  -to dac_data_out[2]             ; ##  H22  FMC_LPC_LA19_P
+set_location_assignment PIN_AH27  -to "dac_data_out[2](n)"        ; ##  H23  FMC_LPC_LA19_N
+set_location_assignment PIN_AB27  -to dac_data_out[3]             ; ##  D20  FMC_LPC_LA17_CC_P
+set_location_assignment PIN_AC27  -to "dac_data_out[3](n)"        ; ##  D21  FMC_LPC_LA17_CC_N
+set_location_assignment PIN_AJ26  -to dac_data_out[4]             ; ##  D23  FMC_LPC_LA23_P
+set_location_assignment PIN_AK26  -to "dac_data_out[4](n)"        ; ##  D24  FMC_LPC_LA23_N
+set_location_assignment PIN_AK27  -to dac_data_out[5]             ; ##  G24  FMC_LPC_LA22_P
+set_location_assignment PIN_AK28  -to "dac_data_out[5](n)"        ; ##  G25  FMC_LPC_LA22_N
+set_location_assignment PIN_AE27  -to dac_data_out[6]             ; ##  C22  FMC_LPC_LA18_CC_P
+set_location_assignment PIN_AF27  -to "dac_data_out[6](n)"        ; ##  C23  FMC_LPC_LA18_CC_N
+set_location_assignment PIN_AH28  -to dac_data_out[7]             ; ##  H25  FMC_LPC_LA21_P
+set_location_assignment PIN_AH29  -to "dac_data_out[7](n)"        ; ##  H26  FMC_LPC_LA21_N
+set_location_assignment PIN_AJ30  -to dac_data_out[8]             ; ##  D26  FMC_LPC_LA26_P
+set_location_assignment PIN_AK30  -to "dac_data_out[8](n)"        ; ##  D27  FMC_LPC_LA26_N
+set_location_assignment PIN_AF30  -to dac_data_out[9]             ; ##  H28  FMC_LPC_LA24_P
+set_location_assignment PIN_AG30  -to "dac_data_out[9](n)"        ; ##  H29  FMC_LPC_LA24_N
+set_location_assignment PIN_AJ28  -to dac_data_out[10]            ; ##  C26  FMC_LPC_LA27_P
+set_location_assignment PIN_AJ29  -to "dac_data_out[10](n)"       ; ##  C27  FMC_LPC_LA27_N
+set_location_assignment PIN_AE25  -to dac_data_out[11]            ; ##  G30  FMC_LPC_LA29_P
+set_location_assignment PIN_AF25  -to "dac_data_out[11](n)"       ; ##  G31  FMC_LPC_LA29_N
+set_location_assignment PIN_AD25  -to dac_data_out[12]            ; ##  H31  FMC_LPC_LA28_P
+set_location_assignment PIN_AE26  -to "dac_data_out[12](n)"       ; ##  H32  FMC_LPC_LA28_N
+set_location_assignment PIN_AC29  -to dac_data_out[13]            ; ##  G33  FMC_LPC_LA31_P
+set_location_assignment PIN_AD29  -to "dac_data_out[13](n)"       ; ##  G34  FMC_LPC_LA31_N
+set_location_assignment PIN_AB29  -to dac_data_out[14]            ; ##  H34  FMC_LPC_LA30_P
+set_location_assignment PIN_AB30  -to "dac_data_out[14](n)"       ; ##  H35  FMC_LPC_LA30_N
+set_location_assignment PIN_Y30   -to dac_data_out[15]            ; ##  G36  FMC_LPC_LA33_P
+set_location_assignment PIN_AA30  -to "dac_data_out[15](n)"       ; ##  G37  FMC_LPC_LA33_N
+
+set_location_assignment PIN_AE13  -to adc_clk_in                  ; ##    G06  FMC_LPC_LA00_CC_P
+set_location_assignment PIN_AF13  -to "adc_clk_in(n)"             ; ##  G07  FMC_LPC_LA00_CC_N
+set_location_assignment PIN_AC14  -to adc_data_in[0]              ; ##  C14  FMC_LPC_LA10_P
+set_location_assignment PIN_AC13  -to "adc_data_in[0](n)"         ; ##  C15  FMC_LPC_LA10_N
+set_location_assignment PIN_AF18  -to adc_data_in[1]              ; ##  C18  FMC_LPC_LA14_P
+set_location_assignment PIN_AF17  -to "adc_data_in[1](n)"         ; ##  C19  FMC_LPC_LA14_N
+set_location_assignment PIN_AH17  -to adc_data_in[2]              ; ##  D17  FMC_LPC_LA13_P
+set_location_assignment PIN_AH16  -to "adc_data_in[2](n)"         ; ##  D18  FMC_LPC_LA13_N
+set_location_assignment PIN_AJ16  -to adc_data_in[3]              ; ##  H16  FMC_LPC_LA11_P
+set_location_assignment PIN_AK16  -to "adc_data_in[3](n)"         ; ##  H17  FMC_LPC_LA11_N
+set_location_assignment PIN_AD16  -to adc_data_in[4]              ; ##  G15  FMC_LPC_LA12_P
+set_location_assignment PIN_AD15  -to "adc_data_in[4](n)"         ; ##  G16  FMC_LPC_LA12_N
+set_location_assignment PIN_AH14  -to adc_data_in[5]              ; ##  D14  FMC_LPC_LA09_P
+set_location_assignment PIN_AH13  -to "adc_data_in[5](n)"         ; ##  D15  FMC_LPC_LA09_N
+set_location_assignment PIN_AA15  -to adc_data_in[6]              ; ##  H13  FMC_LPC_LA07_P
+set_location_assignment PIN_AA14  -to "adc_data_in[6](n)"         ; ##  H14  FMC_LPC_LA07_N
+set_location_assignment PIN_AD14  -to adc_data_in[7]              ; ##  G12  FMC_LPC_LA08_P
+set_location_assignment PIN_AD13  -to "adc_data_in[7](n)"         ; ##  G13  FMC_LPC_LA08_N
+set_location_assignment PIN_AE16  -to adc_data_in[8]              ; ##  D11  FMC_LPC_LA05_P
+set_location_assignment PIN_AE15  -to "adc_data_in[8](n)"         ; ##  D12  FMC_LPC_LA05_N
+set_location_assignment PIN_AJ15  -to adc_data_in[9]              ; ##  H10  FMC_LPC_LA04_P
+set_location_assignment PIN_AK15  -to "adc_data_in[9](n)"         ; ##  H11  FMC_LPC_LA04_N
+set_location_assignment PIN_AG12  -to adc_data_in[10]             ; ##  G09  FMC_LPC_LA03_P
+set_location_assignment PIN_AH12  -to "adc_data_in[10](n)"        ; ##  G10  FMC_LPC_LA03_N
+set_location_assignment PIN_AB12  -to adc_data_in[11]             ; ##  C10  FMC_LPC_LA06_P
+set_location_assignment PIN_AC12  -to "adc_data_in[11](n)"        ; ##  C11  FMC_LPC_LA06_N
+set_location_assignment PIN_AE12  -to adc_data_in[12]             ; ##  H07  FMC_LPC_LA02_P
+set_location_assignment PIN_AF12  -to "adc_data_in[12](n)"        ; ##  H08  FMC_LPC_LA02_N
+set_location_assignment PIN_AF15  -to adc_data_in[13]             ; ##  D08  FMC_LPC_LA01_CC_P
+set_location_assignment PIN_AG15  -to "adc_data_in[13](n)"        ; ##  D09  FMC_LPC_LA01_CC_N
+
+set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_in
+set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_out
+set_instance_assignment -name IO_STANDARD LVDS -to dac_frame_out
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[0]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[1]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[2]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[3]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[4]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[5]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[6]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[7]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[8]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[9]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[10]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[11]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[12]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[13]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[14]
+set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[15]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_clk_in
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[0]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[1]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[2]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[3]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[4]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[5]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[6]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[7]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[8]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[9]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[10]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[11]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[12]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[13]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[14]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[15]
+
+# SPI interface
+
+set_location_assignment PIN_AG16  -to spi_csn                                ; ##  H05  FMC_LPC_CLK0_M2C_N
+set_location_assignment PIN_AG17  -to spi_clk                                ; ##  H04  FMC_LPC_CLK0_M2C_P
+set_location_assignment PIN_AE18  -to spi_sdio                               ; ##  G18  FMC_LPC_LA16_P
+set_location_assignment PIN_AE17  -to spi_int                                ; ##  G19  FMC_LPC_LA16_N
+
+set_instance_assignment -name IO_STANDARD "1.8V" -to spi_csn
+set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clk
+set_instance_assignment -name IO_STANDARD "1.8V" -to spi_sdio
+set_instance_assignment -name IO_STANDARD "1.8V" -to spi_int
+
+execute_flow -compile
diff --git a/projects/daq1/a10gx/system_qsys.tcl b/projects/daq1/a10gx/system_qsys.tcl
new file mode 100644
index 000000000..aceed4aac
--- /dev/null
+++ b/projects/daq1/a10gx/system_qsys.tcl
@@ -0,0 +1,6 @@
+
+source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
+source ../common/daq1_qsys.tcl
+
+save_system "system_bd.qsys"
+
diff --git a/projects/daq1/a10gx/system_top.v b/projects/daq1/a10gx/system_top.v
new file mode 100644
index 000000000..4d5791245
--- /dev/null
+++ b/projects/daq1/a10gx/system_top.v
@@ -0,0 +1,195 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  input               sys_clk,
+  input               sys_resetn,
+
+  // ddr3
+
+  output              ddr3_clk_p,
+  output              ddr3_clk_n,
+  output  [ 14:0]     ddr3_a,
+  output  [  2:0]     ddr3_ba,
+  output              ddr3_cke,
+  output              ddr3_cs_n,
+  output              ddr3_odt,
+  output              ddr3_reset_n,
+  output              ddr3_we_n,
+  output              ddr3_ras_n,
+  output              ddr3_cas_n,
+  inout   [  7:0]     ddr3_dqs_p,
+  inout   [  7:0]     ddr3_dqs_n,
+  inout   [ 63:0]     ddr3_dq,
+  output  [  7:0]     ddr3_dm,
+  input               ddr3_rzq,
+  input               ddr3_ref_clk,
+
+  // ethernet
+
+  input               eth_ref_clk,
+  input               eth_rxd,
+  output              eth_txd,
+  output              eth_mdc,
+  inout               eth_mdio,
+  output              eth_resetn,
+  input               eth_intn,
+
+  // board gpio
+
+  input   [ 10:0]     gpio_bd_i,
+  output  [ 15:0]     gpio_bd_o,
+
+  // daq1 interface
+
+  input               dac_clk_in_p,
+  input               dac_clk_in_n,
+  output              dac_clk_out_p,
+  output              dac_clk_out_n,
+  output              dac_frame_out_p,
+  output              dac_frame_out_n,
+  output  [15:0]      dac_data_out_p,
+  output  [15:0]      dac_data_out_n,
+
+  input               adc_clk_in_p,
+  input               adc_clk_in_n,
+  input  [13:0]       adc_data_in_p,
+  input  [13:0]       adc_data_in_n,
+
+  output              spi_clk,
+  output              spi_csn,
+  inout               spi_sdio,
+  input               spi_int);
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire            spi_mosi;
+  wire            spi_miso;
+
+  // board specific connections
+
+  assign eth_resetn = ~eth_reset;
+  assign eth_mdio_i = eth_mdio;
+  assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
+
+  assign ddr3_a[14:12] = 3'd0;
+
+  assign gpio_i[31:27] = gpio_o[31:27];
+  assign gpio_i[26:16] = gpio_bd_i;
+  assign gpio_i[15: 0] = gpio_o[15:0];
+
+  assign gpio_bd_o = gpio_o[15:0];
+
+  // instantiations
+
+ daq1_spi i_spi (
+    .spi_csn (spi_csn),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_sdio (spi_sdio));
+
+ system_bd i_system_bd (
+    .sys_clk_clk (sys_clk),
+    .sys_rst_reset_n (sys_resetn),
+
+    .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
+    .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
+    .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
+    .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
+    .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
+    .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
+
+    .sys_ethernet_mdio_mdc (eth_mdc),
+    .sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .sys_ethernet_ref_clk_clk (eth_ref_clk),
+    .sys_ethernet_reset_reset (eth_reset),
+    .sys_ethernet_sgmii_rxp_0 (eth_rxd),
+    .sys_ethernet_sgmii_txp_0 (eth_txd),
+
+    .sys_gpio_bd_in_port (gpio_i[31:0]),
+    .sys_gpio_bd_out_port (gpio_o[31:0]),
+    .sys_gpio_in_export (gpio_i[63:32]),
+    .sys_gpio_out_export (gpio_o[63:32]),
+
+    .sys_spi_MISO (spi_miso),
+    .sys_spi_MOSI (spi_mosi),
+    .sys_spi_SCLK (spi_clk),
+    .sys_spi_SS_n (spi_csn),
+
+    .spi_int(spi_int),
+
+    .adc_clk_in_n (adc_clk_in_n),
+    .adc_clk_in_p (adc_clk_in_p),
+    .adc_data_in_n (adc_data_in_n),
+    .adc_data_in_p (adc_data_in_p),
+    .dac_clk_in_n (dac_clk_in_n),
+    .dac_clk_in_p (dac_clk_in_p),
+    .dac_clk_out_n (dac_clk_out_n),
+    .dac_clk_out_p (dac_clk_out_p),
+    .dac_data_out_n (dac_data_out_n),
+    .dac_data_out_p (dac_data_out_p),
+    .dac_frame_out_n (dac_frame_out_n),
+    .dac_frame_out_p (dac_frame_out_p)
+);
+
+endmodule
+
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/daq1/common/daq1_qsys.tcl b/projects/daq1/common/daq1_qsys.tcl
new file mode 100644
index 000000000..c23a6a97a
--- /dev/null
+++ b/projects/daq1/common/daq1_qsys.tcl
@@ -0,0 +1,139 @@
+
+# DAQ1
+
+# DAC core
+
+add_instance axi_ad9122 axi_ad9122 1.0
+set_instance_parameter_value axi_ad9122 {ID} {0}
+
+add_connection sys_clk.clk_reset axi_ad9122.s_axi_reset
+add_connection sys_clk.clk axi_ad9122.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9122.s_axi
+
+# DAC unpack
+
+add_instance util_ad9122_upack util_upack 1.0
+set_instance_parameter_value util_ad9122_upack {CHANNEL_DATA_WIDTH} {64}
+set_instance_parameter_value util_ad9122_upack {NUM_OF_CHANNELS} {2}
+
+# DAC DMA
+
+add_instance axi_ad9122_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9122_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9122_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_SRC} {0}
+set_instance_parameter_value axi_ad9122_dma {CYCLIC} {1}
+set_instance_parameter_value axi_ad9122_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_ad9122_dma {DMA_LENGTH_WIDTH} {24}
+
+add_connection sys_clk.clk_reset axi_ad9122_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9122_dma.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9122_dma.s_axi
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9122_dma.m_src_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9122_dma.m_src_axi_clock
+add_connection axi_ad9122_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.irq axi_ad9122_dma.interrupt_sender
+add_connection sys_clk.clk axi_ad9122_dma.if_fifo_rd_clk
+
+# DAC path
+
+add_connection axi_ad9122.if_dac_div_clk util_ad9122_upack.if_dac_clk
+add_connection util_ad9122_upack.if_dac_valid axi_ad9122_dma.if_fifo_rd_en
+add_connection util_ad9122_upack.if_dac_data axi_ad9122_dma.if_fifo_rd_dout
+add_connection axi_ad9122_dma.if_fifo_rd_underflow axi_ad9122.if_dac_dunf
+add_connection util_ad9122_upack.dac_ch_0 axi_ad9122.dac_ch_0
+add_connection util_ad9122_upack.dac_ch_1 axi_ad9122.dac_ch_1
+
+# ADC core
+
+add_instance axi_ad9684 axi_ad9684 1.0
+set_instance_parameter_value axi_ad9684 {OR_STATUS} {0}
+
+add_connection sys_clk.clk_reset axi_ad9684.s_axi_reset
+add_connection sys_clk.clk axi_ad9684.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9684.s_axi
+
+# ADC pack
+
+add_instance util_ad9684_cpack util_cpack 1.0
+set_instance_parameter_value util_ad9684_cpack {CHANNEL_DATA_WIDTH} {32}
+set_instance_parameter_value util_ad9684_cpack {NUM_OF_CHANNELS} {2}
+
+add_connection sys_clk.clk_reset util_ad9684_cpack.if_adc_rst
+add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9684_cpack.if_adc_rst
+add_connection axi_ad9684.if_adc_clk util_ad9684_cpack.if_adc_clk
+add_connection util_ad9684_cpack.adc_ch_0 axi_ad9684.adc_ch_0
+add_connection util_ad9684_cpack.adc_ch_1 axi_ad9684.adc_ch_1
+
+# ADC FIFO
+
+add_instance ad9684_adcfifo util_adcfifo 1.0
+set_instance_parameter_value ad9684_adcfifo {ADC_DATA_WIDTH} {64}
+set_instance_parameter_value ad9684_adcfifo {DMA_DATA_WIDTH} {64}
+set_instance_parameter_value ad9684_adcfifo {DMA_ADDRESS_WIDTH} {16}
+
+add_connection sys_clk.clk_reset ad9684_adcfifo.if_adc_rst
+add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9684_adcfifo.if_adc_rst
+add_connection axi_ad9684.if_adc_clk ad9684_adcfifo.if_adc_clk
+add_connection util_ad9684_cpack.if_adc_valid ad9684_adcfifo.if_adc_wr
+add_connection util_ad9684_cpack.if_adc_data ad9684_adcfifo.if_adc_wdata
+add_connection sys_ddr3_cntrl.emif_usr_clk ad9684_adcfifo.if_dma_clk
+
+# ADC DMA
+
+add_instance axi_ad9684_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_SRC} {1}
+set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9684_dma {ID} {1}
+set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_ad9684_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9684_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9684_dma {FIFO_SIZE} {16}
+set_instance_parameter_value axi_ad9684_dma {CYCLIC} {0}
+
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.if_s_axis_aclk
+add_connection ad9684_adcfifo.if_dma_wr axi_ad9684_dma.if_s_axis_valid
+add_connection ad9684_adcfifo.if_dma_wdata axi_ad9684_dma.if_s_axis_data
+add_connection ad9684_adcfifo.if_dma_wready axi_ad9684_dma.if_s_axis_ready
+add_connection ad9684_adcfifo.if_dma_xfer_req axi_ad9684_dma.if_s_axis_xfer_req
+add_connection sys_clk.clk_reset axi_ad9684_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9684_dma.s_axi_clock
+add_connection sys_cpu.data_master axi_ad9684_dma.s_axi
+add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9684_dma.m_dest_axi_reset
+add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.m_dest_axi_clock
+add_connection axi_ad9684_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
+add_connection sys_cpu.irq axi_ad9684_dma.interrupt_sender
+
+# setting interface property
+
+set_interface_property axi_ad9122_device_if EXPORT_OF axi_ad9122.device_if
+set_interface_property axi_ad9684_device_if EXPORT_OF axi_ad9684.device_if
+
+# IRQ bridge for the CPLD IRQ signal
+
+add_instance irq_bridge altera_irq_bridge 16.0
+set_instance_parameter_value irq_bridge {IRQ_WIDTH} {1}
+
+add_connection sys_clk.clk_reset irq_bridge.clk_reset
+add_connection sys_clk.clk irq_bridge.clk
+add_connection sys_cpu.irq irq_bridge.sender0_irq
+
+set_interface_property spi_int EXPORT_OF irq_bridge.receiver_irq
+
+# addresses
+
+set_connection_parameter_value sys_cpu.data_master/axi_ad9122.s_axi baseAddress {0x44A00000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9684.s_axi baseAddress {0x44A20000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9122_dma.s_axi baseAddress {0x44A40000}
+set_connection_parameter_value sys_cpu.data_master/axi_ad9684_dma.s_axi baseAddress {0x44A60000}
+
+# interrupts
+
+set_connection_parameter_value sys_cpu.irq/irq_bridge.sender0_irq irqNumber {9}
+set_connection_parameter_value sys_cpu.irq/axi_ad9122_dma.interrupt_sender irqNumber {10}
+set_connection_parameter_value sys_cpu.irq/axi_ad9684_dma.interrupt_sender irqNumber {11}
+

From 5731ba330076fd3eac91b50c74131ea104c02a1a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 24 Oct 2016 09:51:29 -0400
Subject: [PATCH 633/972] fmcomms11- xcvr updates

---
 library/xilinx/util_adxcvr/util_adxcvr.v     | 17 +++++++++++++++++
 library/xilinx/util_adxcvr/util_adxcvr_xch.v |  3 ++-
 projects/fmcomms11/common/fmcomms11_bd.tcl   |  3 ++-
 projects/fmcomms11/zc706/system_top.v        |  2 +-
 4 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v
index 43e0aafa3..fffe54b67 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr.v
@@ -68,6 +68,7 @@ module util_adxcvr #(
   parameter   integer RX_NUM_OF_LANES = 8,
   parameter   integer RX_OUT_DIV = 1,
   parameter   integer RX_CLK25_DIV = 20,
+  parameter   [15:0]  RX_DFE_LPM_CFG = 16'h0104,
   parameter   [31:0]  RX_PMA_CFG = 32'h001e7080,
   parameter   [72:0]  RX_CDR_CFG = 72'h0b000023ff10400020) (
 
@@ -1128,6 +1129,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_0 (
@@ -1226,6 +1228,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_1 (
@@ -1324,6 +1327,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_2 (
@@ -1422,6 +1426,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_3 (
@@ -1552,6 +1557,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_4 (
@@ -1650,6 +1656,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_5 (
@@ -1748,6 +1755,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_6 (
@@ -1846,6 +1854,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_7 (
@@ -1976,6 +1985,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_8 (
@@ -2074,6 +2084,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_9 (
@@ -2172,6 +2183,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_10 (
@@ -2270,6 +2282,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_11 (
@@ -2400,6 +2413,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_12 (
@@ -2498,6 +2512,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_13 (
@@ -2596,6 +2611,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_14 (
@@ -2694,6 +2710,7 @@ module util_adxcvr #(
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
     .RX_CLK25_DIV (RX_CLK25_DIV),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_PMA_CFG (RX_PMA_CFG),
     .RX_CDR_CFG (RX_CDR_CFG))
   i_xch_15 (
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 435207e6a..01624a725 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -53,6 +53,7 @@ module util_adxcvr_xch #(
 
   parameter   integer RX_OUT_DIV = 1,
   parameter   integer RX_CLK25_DIV = 20,
+  parameter   [15:0]  RX_DFE_LPM_CFG = 16'h0104,
   parameter   [31:0]  RX_PMA_CFG = 32'h001e7080,
   parameter   [72:0]  RX_CDR_CFG = 72'h0b000023ff10400020) (
 
@@ -453,7 +454,7 @@ module util_adxcvr_xch #(
     .RX_DFE_H5_CFG (11'b00011100000),
     .RX_DFE_KL_CFG (13'b0000011111110),
     .RX_DFE_KL_CFG2 (32'h301148AC),
-    .RX_DFE_LPM_CFG (16'h0104),
+    .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
     .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
     .RX_DFE_UT_CFG (17'b10001111000000000),
     .RX_DFE_VP_CFG (17'b00011111100000011),
diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index dccad947b..09f47d2a1 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -58,7 +58,8 @@ set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.TX_CLK25_DIV {7}] $util_fmcomms11_xcvr
-set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10400020}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr
 
 ad_connect  sys_cpu_resetn util_fmcomms11_xcvr/up_rstn
diff --git a/projects/fmcomms11/zc706/system_top.v b/projects/fmcomms11/zc706/system_top.v
index bdad159a4..adc00d9b2 100644
--- a/projects/fmcomms11/zc706/system_top.v
+++ b/projects/fmcomms11/zc706/system_top.v
@@ -295,7 +295,7 @@ module system_top (
     .rx_data_6_p (rx_data_p[6]),
     .rx_data_7_n (rx_data_n[7]),
     .rx_data_7_p (rx_data_p[7]),
-    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_ref_clk_0 (tx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (sysref),
     .spdif (spdif),

From 138eeebc9b076c3189c9b5df6b5d253f6d2b7717 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 25 Oct 2016 16:32:44 +0300
Subject: [PATCH 634/972] ccusb_lvds: Initial commit

---
 projects/pzsdr/Makefile                      |   3 +
 projects/pzsdr/ccusb_lvds/Makefile           |  82 +++++++
 projects/pzsdr/ccusb_lvds/system_bd.tcl      |   4 +
 projects/pzsdr/ccusb_lvds/system_constr.xdc  |  60 +++++
 projects/pzsdr/ccusb_lvds/system_project.tcl |  16 ++
 projects/pzsdr/ccusb_lvds/system_top.v       | 231 +++++++++++++++++++
 projects/pzsdr/common/ccusb_lvds_bd.tcl      |  71 ++++++
 7 files changed, 467 insertions(+)
 create mode 100644 projects/pzsdr/ccusb_lvds/Makefile
 create mode 100644 projects/pzsdr/ccusb_lvds/system_bd.tcl
 create mode 100644 projects/pzsdr/ccusb_lvds/system_constr.xdc
 create mode 100644 projects/pzsdr/ccusb_lvds/system_project.tcl
 create mode 100644 projects/pzsdr/ccusb_lvds/system_top.v
 create mode 100644 projects/pzsdr/common/ccusb_lvds_bd.tcl

diff --git a/projects/pzsdr/Makefile b/projects/pzsdr/Makefile
index 5643ce37c..f75ab9a0e 100644
--- a/projects/pzsdr/Makefile
+++ b/projects/pzsdr/Makefile
@@ -11,6 +11,7 @@ all:
 	-make -C ccbrk_cmos all
 	-make -C ccfmc all
 	-make -C ccpci all
+	-make -C ccusb_lvds all
 	-make -C ccbox_lvds all
 	-make -C ccbrk all
 	-make -C ccbrk_cmos all
@@ -21,6 +22,7 @@ clean:
 	make -C ccbrk_cmos clean
 	make -C ccfmc clean
 	make -C ccpci clean
+	make -C ccusb_lvds clean
 	make -C ccbox_lvds clean
 	make -C ccbrk clean
 	make -C ccbrk_cmos clean
@@ -31,6 +33,7 @@ clean-all:
 	make -C ccbrk_cmos clean-all
 	make -C ccfmc clean-all
 	make -C ccpci clean-all
+	make -C ccusb_lvds clean-all
 	make -C ccbox_lvds clean-all
 	make -C ccbrk clean-all
 	make -C ccbrk_cmos clean-all
diff --git a/projects/pzsdr/ccusb_lvds/Makefile b/projects/pzsdr/ccusb_lvds/Makefile
new file mode 100644
index 000000000..b78944d15
--- /dev/null
+++ b/projects/pzsdr/ccusb_lvds/Makefile
@@ -0,0 +1,82 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/ccusb_lvds_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
+M_DEPS += ../../common/xilinx/sys_wfifo.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
+M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
+M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib ccusb_lvds_pzsdr.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_usb_fx3 clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+ccusb_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> ccusb_lvds_pzsdr_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_usb_fx3
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/pzsdr/ccusb_lvds/system_bd.tcl b/projects/pzsdr/ccusb_lvds/system_bd.tcl
new file mode 100644
index 000000000..0019e5509
--- /dev/null
+++ b/projects/pzsdr/ccusb_lvds/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/ccusb_lvds_bd.tcl
+
diff --git a/projects/pzsdr/ccusb_lvds/system_constr.xdc b/projects/pzsdr/ccusb_lvds/system_constr.xdc
new file mode 100644
index 000000000..4f5b6ed5d
--- /dev/null
+++ b/projects/pzsdr/ccusb_lvds/system_constr.xdc
@@ -0,0 +1,60 @@
+
+# USB_FX3
+
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports data[0]]        ; ## IO_L01_34_JX4_P
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports data[1]]        ; ## IO_L01_34_JX4_N
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports data[2]]        ; ## IO_L03_34_JX4_P
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports data[3]]        ; ## IO_L03_34_JX4_N
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports data[4]]        ; ## IO_L05_34_JX4_P
+set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD LVCMOS18} [get_ports data[5]]        ; ## IO_L05_34_JX4_N
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD LVCMOS18} [get_ports data[6]]        ; ## IO_L07_34_JX4_P
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD LVCMOS18} [get_ports data[7]]        ; ## IO_L07_34_JX4_N
+set_property  -dict {PACKAGE_PIN  F9    IOSTANDARD LVCMOS18} [get_ports data[8]]        ; ## IO_L09_34_JX4_P
+set_property  -dict {PACKAGE_PIN  E8    IOSTANDARD LVCMOS18} [get_ports data[9]]        ; ## IO_L09_34_JX4_N
+set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD LVCMOS18} [get_ports data[10]]       ; ## IO_L11_SRCC_34_JX4_P
+set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD LVCMOS18} [get_ports data[11]]       ; ## IO_L11_SRCC_34_JX4_N
+set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD LVCMOS18} [get_ports data[12]]       ; ## IO_L13_MRCC_34_JX4_P
+set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD LVCMOS18} [get_ports data[13]]       ; ## IO_L13_MRCC_34_JX4_N
+set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD LVCMOS18} [get_ports data[14]]       ; ## IO_L15_34_JX4_P
+set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD LVCMOS18} [get_ports data[15]]       ; ## IO_L15_34_JX4_N
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD LVCMOS18} [get_ports data[16]]       ; ## IO_L06_34_JX4_P
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD LVCMOS18} [get_ports data[17]]       ; ## IO_L06_34_JX4_N
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD LVCMOS18} [get_ports data[18]]       ; ## IO_L08_34_JX4_P
+set_property  -dict {PACKAGE_PIN  D8    IOSTANDARD LVCMOS18} [get_ports data[19]]       ; ## IO_L08_34_JX4_N
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD LVCMOS18} [get_ports data[20]]       ; ## IO_L10_34_JX4_P
+set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD LVCMOS18} [get_ports data[21]]       ; ## IO_L10_34_JX4_N
+set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD LVCMOS18} [get_ports data[22]]       ; ## IO_L12_MRCC_34_JX4_P
+set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD LVCMOS18} [get_ports data[23]]       ; ## IO_L12_MRCC_34_JX4_N
+set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD LVCMOS18} [get_ports data[24]]       ; ## IO_L14_SRCC_34_JX4_P
+set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD LVCMOS18} [get_ports data[25]]       ; ## IO_L14_SRCC_34_JX4_N
+set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD LVCMOS18} [get_ports data[26]]       ; ## IO_L16_34_JX4_P
+set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD LVCMOS18} [get_ports data[27]]       ; ## IO_L16_34_JX4_N
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD LVCMOS18} [get_ports data[28]]       ; ## IO_L18_34_JX4_P
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD LVCMOS18} [get_ports data[29]]       ; ## IO_L18_34_JX4_N
+set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD LVCMOS18} [get_ports data[30]]       ; ## IO_L20_34_JX4_P
+set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD LVCMOS18} [get_ports data[31]]       ; ## IO_L20_34_JX4_N
+
+set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD LVCMOS18} [get_ports pclk]           ; ## IO_L17_34_JX4_P
+
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports addr[0]]        ; ## IO_L02_34_JX4_P
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD LVCMOS18} [get_ports addr[1]]        ; ## IO_L17_13_JX2_P
+#set_property  -dict {PACKAGE_PIN  AD29  IOSTANDARD LVCMOS18} [get_ports addr[2]]        ; ## G34   FMC_LPC_LA31_N
+#set_property  -dict {PACKAGE_PIN  AC29  IOSTANDARD LVCMOS18} [get_ports addr[3]]        ; ## G33   FMC_LPC_LA31_P
+#set_property  -dict {PACKAGE_PIN  AF25  IOSTANDARD LVCMOS18} [get_ports addr[4]]        ; ## G31   FMC_LPC_LA29_N
+
+set_property  -dict {PACKAGE_PIN  A8    IOSTANDARD LVCMOS18} [get_ports slcs_n]         ; ## IO_L17_34_JX4_N
+set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD LVCMOS18} [get_ports slwr_n]         ; ## IO_L19_34_JX4_P
+set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD LVCMOS18} [get_ports sloe_n]         ; ## IO_L19_34_JX4_N
+set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD LVCMOS18} [get_ports slrd_n]         ; ## IO_L21_34_JX4_P
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD LVCMOS18} [get_ports pktend_n]       ; ## IO_L13_MRCC_13_JX2_P
+
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_tx] ; ## IO_L14_SRCC_13_JX2_N
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_rx] ; ## IO_L16_13_JX2_P
+
+set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[0]]       ; ## IO_L21_34_JX4_N
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS18} [get_ports fifo_rdy[1]]       ; ## IO_L11_SRCC_13_JX2_P
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVCMOS18} [get_ports fifo_rdy[2]]       ; ## IO_L11_SRCC_13_JX2_N
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS18} [get_ports fifo_rdy[3]]       ; ## IO_L13_MRCC_13_JX2_N
+
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports pmode[0]]       ; ## IO_L02_34_JX4_N
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports pmode[1]]       ; ## IO_L04_34_JX4_P
diff --git a/projects/pzsdr/ccusb_lvds/system_project.tcl b/projects/pzsdr/ccusb_lvds/system_project.tcl
new file mode 100644
index 000000000..f65d6123d
--- /dev/null
+++ b/projects/pzsdr/ccusb_lvds/system_project.tcl
@@ -0,0 +1,16 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create ccusb_lvds_pzsdr
+adi_project_files ccusb_lvds_pzsdr [list \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
+
+adi_project_run ccusb_lvds_pzsdr
+
+
diff --git a/projects/pzsdr/ccusb_lvds/system_top.v b/projects/pzsdr/ccusb_lvds/system_top.v
new file mode 100644
index 000000000..c865d7b8c
--- /dev/null
+++ b/projects/pzsdr/ccusb_lvds/system_top.v
@@ -0,0 +1,231 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout           iic_scl,
+  inout           iic_sda,
+
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
+
+  output          enable,
+  output          txnrx,
+  input           clk_out,
+
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
+
+  input           usb_fx3_uart_tx,
+  output          usb_fx3_uart_rx,
+
+  input   [ 3:0]  fifo_rdy,
+
+  inout   [31:0]  data,
+  output  [1:0]   addr,
+  output          pclk,
+  output          slcs_n,
+  output          slrd_n,
+  output          sloe_n,
+  output          slwr_n,
+  output          pktend_n,
+
+  output  [ 1:0]  pmode,
+
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso);
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+
+  assign pmode = 2'b11;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
+    .dio_t ({gpio_t[51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[51], gpio_i[46:32]}),
+    .dio_p ({ gpio_clksel,        // 51:51
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .otg_vbusoc (1'b0),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]),
+    .usb_fx3_uart_tx(usb_fx3_uart_tx),
+    .usb_fx3_uart_rx(usb_fx3_uart_rx),
+    .dma_rdy(),
+    .dma_wmk(),
+    .fifo_rdy(fifo_rdy),
+    .pclk(pclk),
+    .data(data),
+    .addr(addr),
+    .slcs_n(slcs_n),
+    .slrd_n(slrd_n),
+    .sloe_n(sloe_n),
+    .slwr_n(slwr_n),
+    // .epswitch_n(epswitch_n),
+    .pktend_n(pktend_n)
+  );
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/pzsdr/common/ccusb_lvds_bd.tcl b/projects/pzsdr/common/ccusb_lvds_bd.tcl
new file mode 100644
index 000000000..dee7493c1
--- /dev/null
+++ b/projects/pzsdr/common/ccusb_lvds_bd.tcl
@@ -0,0 +1,71 @@
+
+create_bd_port -dir I usb_fx3_uart_tx
+create_bd_port -dir O usb_fx3_uart_rx
+
+create_bd_port -dir I dma_rdy
+create_bd_port -dir I dma_wmk
+create_bd_port -dir I -from 3 -to 0 fifo_rdy
+create_bd_port -dir O pclk
+create_bd_port -dir IO -from 31 -to 0 data
+create_bd_port -dir O -from 1 -to 0 addr
+create_bd_port -dir O slcs_n
+create_bd_port -dir O slrd_n
+create_bd_port -dir O sloe_n
+create_bd_port -dir O slwr_n
+create_bd_port -dir O pktend_n
+create_bd_port -dir O epswitch_n
+
+set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
+set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
+
+set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3]
+
+set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma]
+set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
+
+set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ]
+
+ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
+
+ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk
+ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn
+
+ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS
+ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS
+
+ad_connect axi_uart/rx usb_fx3_uart_tx
+ad_connect axi_uart/tx usb_fx3_uart_rx
+
+ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk
+ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn
+
+ad_connect axi_usb_fx3/dma_rdy dma_rdy
+ad_connect axi_usb_fx3/dma_wmk dma_wmk
+ad_connect axi_usb_fx3/fifo_rdy fifo_rdy
+ad_connect axi_usb_fx3/pclk pclk
+ad_connect axi_usb_fx3/data data
+ad_connect axi_usb_fx3/addr addr
+ad_connect axi_usb_fx3/slcs_n slcs_n
+ad_connect axi_usb_fx3/slrd_n slrd_n
+ad_connect axi_usb_fx3/sloe_n sloe_n
+ad_connect axi_usb_fx3/slwr_n slwr_n
+ad_connect axi_usb_fx3/pktend_n pktend_n
+ad_connect axi_usb_fx3/epswitch_n epswitch_n
+
+
+ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
+ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
+ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut
+ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt
+
+ad_cpu_interconnect 0x50000000 axi_usb_fx3
+ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma
+ad_cpu_interconnect 0x40600000 axi_uart
+
+ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
+ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG
+ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S
+ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM

From 08cef5a7458cfaaf6e938d4db0f3a4aebbe653db Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 25 Oct 2016 20:17:29 +0300
Subject: [PATCH 635/972] axi_ad9361: Add Cyclone V SERDES support

---
 library/axi_ad9361/altera/axi_ad9361_lvds_if.v | 5 +++--
 library/axi_ad9361/axi_ad9361_hw.tcl           | 3 ---
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
index 144855ec8..45d930c2d 100644
--- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
@@ -150,7 +150,6 @@ module axi_ad9361_lvds_if #(
   reg             txnrx_n_int = 'd0;
   reg             enable_p_int = 'd0;
   reg             txnrx_p_int = 'd0;
-  reg    [47:0]   tx_data_lclk = 'd0;
   reg    [ 5:0]   tx_p_data_d_0 = 'd0;
   reg    [ 5:0]   tx_p_data_d_1 = 'd0;
   reg    [ 5:0]   tx_p_data_d_2 = 'd0;
@@ -498,7 +497,9 @@ module axi_ad9361_lvds_if #(
 
   // serdes clock interface
 
-  ad_serdes_clk ad_serdes_clk (
+  ad_serdes_clk #(
+    .DEVICE_TYPE(DEVICE_TYPE))
+  ad_serdes_clk (
     .rst (mmcm_rst),
     .clk_in_p (rx_clk_in_p),
     .clk_in_n (rx_clk_in_n),
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 7f2729e29..d8696c7a9 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -16,12 +16,9 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9361
 add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
 add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file ad_lvds_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_clk.v
 add_fileset_file ad_serdes_clk.v          VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v
 add_fileset_file ad_serdes_in.v           VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v
 add_fileset_file ad_serdes_out.v          VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v
-add_fileset_file ad_lvds_in.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_in.v
-add_fileset_file ad_lvds_out.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_out.v
 add_fileset_file ad_cmos_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_clk.v
 add_fileset_file ad_cmos_in.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_in.v
 add_fileset_file ad_cmos_out.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_out.v

From 6f611e0d10bd78f9732b1ac1509dcfaaae602f07 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 25 Oct 2016 20:19:39 +0300
Subject: [PATCH 636/972] altera/alt_serdes: Add support for Cyclone V

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 133 ++++++++++++++------
 library/altera/common/ad_serdes_clk.v       |  76 ++++++++---
 library/altera/common/ad_serdes_in.v        | 131 ++++++++++++++++---
 library/altera/common/ad_serdes_out.v       |  88 +++++++++++--
 4 files changed, 340 insertions(+), 88 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index 2ea54f709..6d88be1fd 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -41,6 +41,12 @@ set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
 # these paramteres are needed just because of cross-platform requirments
 # are NOT used in the core
 
+add_parameter DEVICE_FAMILY STRING
+set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
+set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
+set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
+set_parameter_property DEVICE_FAMILY ENABLED false
+
 add_parameter DEVICE_TYPE INTEGER 0
 set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
 set_parameter_property DEVICE_TYPE TYPE INTEGER
@@ -95,6 +101,7 @@ proc p_alt_serdes {} {
   set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
   set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
   set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
+  set m_device_family [get_parameter_value DEVICE_FAMILY]
 
   set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
   set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
@@ -109,47 +116,93 @@ proc p_alt_serdes {} {
 
   if {$m_mode == "CLK"} {
 
-    add_instance alt_serdes_pll altera_iopll
-    set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
-    set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
-    set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
-    set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
-    set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
-    set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
-    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
-    set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
-    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
-    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
-    set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
-    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
-    set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
-    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
-    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
-    set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
-    add_interface rst reset sink
-    set_interface_property rst EXPORT_OF alt_serdes_pll.reset
-    add_interface ref_clk clock sink
-    set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
-    add_interface locked conduit end
-    set_interface_property locked EXPORT_OF alt_serdes_pll.locked
-    add_interface hs_phase conduit end
-    set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
-    add_interface hs_clk conduit end
-    set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
-    add_interface loaden conduit end
-    set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
-    add_interface ls_clk clock source
-    set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
+    if {$m_device_family == "Arria 10"} {
+      add_instance alt_serdes_pll altera_iopll
+      set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
+      set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
+      set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
+      set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
+      set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
+      set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
+      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
+      set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
+      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
+      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
+      set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
+      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
+      set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
+      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
+      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
+      set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
+      add_interface rst reset sink
+      set_interface_property rst EXPORT_OF alt_serdes_pll.reset
+      add_interface ref_clk clock sink
+      set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
+      add_interface locked conduit end
+      set_interface_property locked EXPORT_OF alt_serdes_pll.locked
+      add_interface hs_phase conduit end
+      set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
+      add_interface hs_clk conduit end
+      set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
+      add_interface loaden conduit end
+      set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
+      add_interface ls_clk clock source
+      set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
 
-    add_instance alt_serdes_pll_reconfig altera_pll_reconfig
-    add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
-    add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
-    add_interface drp_clk clock sink
-    set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
-    add_interface drp_rst reset sink
-    set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
-    add_interface pll_reconfig avalon slave
-    set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
+      add_instance alt_serdes_pll_reconfig altera_pll_reconfig
+      add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
+      add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
+      add_interface drp_clk clock sink
+      set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
+      add_interface drp_rst reset sink
+      set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
+      add_interface pll_reconfig avalon slave
+      set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
+    }
+
+    if {$m_device_family == "Cyclone V"} {
+      add_instance alt_serdes_pll altera_pll
+      set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
+      set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
+      set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
+      set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3}
+      set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
+      set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
+      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
+      set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
+      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
+      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
+      set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
+      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
+      set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
+      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
+      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
+      set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
+      add_interface rst reset sink
+      set_interface_property rst EXPORT_OF alt_serdes_pll.reset
+      add_interface ref_clk clock sink
+      set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
+      add_interface locked conduit end
+      set_interface_property locked EXPORT_OF alt_serdes_pll.locked
+      add_interface hs_phase conduit end
+      set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
+      add_interface hs_clk clock source
+      set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0
+      add_interface loaden clock source
+      set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1
+      add_interface ls_clk clock source
+      set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
+
+      add_instance alt_serdes_pll_reconfig altera_pll_reconfig
+      add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
+      add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
+      add_interface drp_clk clock sink
+      set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
+      add_interface drp_rst reset sink
+      set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
+      add_interface pll_reconfig avalon slave
+      set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
+    }
   }
 
   if {$m_mode == "IN"} {
diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
index 6ba9770e4..48ae32999 100644
--- a/library/altera/common/ad_serdes_clk.v
+++ b/library/altera/common/ad_serdes_clk.v
@@ -38,7 +38,11 @@
 
 `timescale 1ps/1ps
 
-module ad_serdes_clk (
+module ad_serdes_clk #(
+
+  // parameters
+
+	parameter DEVICE_TYPE = 0 ) (
 
   // clock and divided clock
 
@@ -64,6 +68,10 @@ module ad_serdes_clk (
   output          up_drp_ready,
   output          up_drp_locked);
 
+  // local parameter
+
+  localparam C5SOC = 1;
+
   // internal registers
 
   reg             up_drp_sel_int = 'd0;
@@ -81,6 +89,8 @@ module ad_serdes_clk (
   wire    [31:0]  up_drp_rdata_int_s;
   wire            up_drp_busy_int_s;
   wire            up_drp_locked_int_s;
+  wire            buf_loaden;
+  wire            buf_lvdsclk;
 
   // defaults
 
@@ -134,25 +144,53 @@ module ad_serdes_clk (
     end
   end
 
-  // instantiations (ip- hw.tcl must generate this core)
+  generate
+    if (DEVICE_TYPE == C5SOC) begin
+      alt_serdes_clk_core i_core (
+        .rst_reset (rst),
+        .ref_clk_clk (clk_in_p),
+        .locked_export (up_drp_locked_int_s),
+        .hs_phase_phout (phase),
+        .hs_clk_clk (buf_lvdsclk),
+        .loaden_clk (buf_loaden),
+        .ls_clk_clk (div_clk),
+        .drp_clk_clk (up_clk),
+        .drp_rst_reset (up_drp_reset),
+        .pll_reconfig_waitrequest (up_drp_busy_int_s),
+        .pll_reconfig_read (up_drp_rd_int),
+        .pll_reconfig_write (up_drp_wr_int),
+        .pll_reconfig_readdata (up_drp_rdata_int_s),
+        .pll_reconfig_address (up_drp_addr_int),
+        .pll_reconfig_writedata (up_drp_wdata_int));
 
-  alt_serdes_clk_core i_core (
-    .rst_reset (rst),
-    .ref_clk_clk (clk_in_p),
-    .locked_export (up_drp_locked_int_s),
-    .hs_phase_phout (phase),
-    .hs_clk_lvds_clk (clk),
-    .loaden_loaden (loaden),
-    .ls_clk_clk (div_clk),
-    .drp_clk_clk (up_clk),
-    .drp_rst_reset (up_drp_reset),
-    .pll_reconfig_waitrequest (up_drp_busy_int_s),
-    .pll_reconfig_read (up_drp_rd_int),
-    .pll_reconfig_write (up_drp_wr_int),
-    .pll_reconfig_readdata (up_drp_rdata_int_s),
-    .pll_reconfig_address (up_drp_addr_int),
-    .pll_reconfig_writedata (up_drp_wdata_int));
-  
+      // clock buffer
+      cyclonev_pll_lvds_output #(
+        .pll_loaden_enable_disable("true"),
+        .pll_lvdsclk_enable_disable("true"))
+      cyclonev_pll_lvds_output_inst (
+        .ccout({buf_loaden, buf_lvdsclk}),
+        .loaden(loaden),
+        .lvdsclk(clk));
+
+    end else begin
+      alt_serdes_clk_core i_core (
+        .rst_reset (rst),
+        .ref_clk_clk (clk_in_p),
+        .locked_export (up_drp_locked_int_s),
+        .hs_phase_phout (phase),
+        .hs_clk_lvds_clk (clk),
+        .loaden_loaden (loaden),
+        .ls_clk_clk (div_clk),
+        .drp_clk_clk (up_clk),
+        .drp_rst_reset (up_drp_reset),
+        .pll_reconfig_waitrequest (up_drp_busy_int_s),
+        .pll_reconfig_read (up_drp_rd_int),
+        .pll_reconfig_write (up_drp_wr_int),
+        .pll_reconfig_readdata (up_drp_rdata_int_s),
+        .pll_reconfig_address (up_drp_addr_int),
+        .pll_reconfig_writedata (up_drp_wdata_int));
+    end
+  endgenerate
 endmodule
 
 // ***************************************************************************
diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 20716cf1e..59183d49a 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -81,6 +81,10 @@ module ad_serdes_in #(
   input                           delay_rst,
   output                          delay_locked);
 
+  // local parameter
+
+  localparam C5SOC = 1;
+
   // internal signals
 
   wire    [(DATA_WIDTH-1):0]      delay_locked_s;
@@ -109,22 +113,117 @@ module ad_serdes_in #(
     for (l_order = 0; l_order < SERDES_FACTOR; l_order = l_order + 1) begin: g_order
       assign data_sel_s[l_order][l_inst] = data_out_s[8 - SERDES_FACTOR + l_order][l_inst];
     end
-  alt_serdes_in_core i_core (
-    .clk_export (clk),
-    .div_clk_export (div_clk),
-    .hs_phase_export (phase),
-    .loaden_export (loaden),
-    .locked_export (locked),
-    .data_in_export (data_in_p[l_inst]),
-    .data_s_export ({data_out_s[0][l_inst],
-                     data_out_s[1][l_inst],
-                     data_out_s[2][l_inst],
-                     data_out_s[3][l_inst],
-                     data_out_s[4][l_inst],
-                     data_out_s[5][l_inst],
-                     data_out_s[6][l_inst],
-                     data_out_s[7][l_inst]}),
-    .delay_locked_export (delay_locked_s[l_inst]));
+
+    if (DEVICE_TYPE == C5SOC ) begin
+      altlvds_rx #(
+        .buffer_implementation ("RAM"),
+        .cds_mode ("UNUSED"),
+        .common_rx_tx_pll ("ON"),
+        .data_align_rollover (4),
+        .data_rate ("500.0 Mbps"),
+        .deserialization_factor (4),
+        .dpa_initial_phase_value (0),
+        .dpll_lock_count (0),
+        .dpll_lock_window (0),
+        .enable_clock_pin_mode ("UNUSED"),
+        .enable_dpa_align_to_rising_edge_only ("OFF"),
+        .enable_dpa_calibration ("ON"),
+        .enable_dpa_fifo ("UNUSED"),
+        .enable_dpa_initial_phase_selection ("OFF"),
+        .enable_dpa_mode ("OFF"),
+        .enable_dpa_pll_calibration ("OFF"),
+        .enable_soft_cdr_mode ("OFF"),
+        .implement_in_les ("OFF"),
+        .inclock_boost (0),
+        .inclock_data_alignment ("EDGE_ALIGNED"),
+        .inclock_period (4000),
+        .inclock_phase_shift (0),
+        .input_data_rate (500),
+        .intended_device_family ("Cyclone V"),
+        .lose_lock_on_one_change ("UNUSED"),
+        .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_in"),
+        .lpm_type ("altlvds_rx"),
+        .number_of_channels (DATA_WIDTH),
+        .outclock_resource ("Regional clock"),
+        .pll_operation_mode ("NORMAL"),
+        .pll_self_reset_on_loss_lock ("UNUSED"),
+        .port_rx_channel_data_align ("PORT_UNUSED"),
+        .port_rx_data_align ("PORT_UNUSED"),
+        .refclk_frequency ("250.000000 MHz"),
+        .registered_data_align_input ("UNUSED"),
+        .registered_output ("ON"),
+        .reset_fifo_at_first_lock ("UNUSED"),
+        .rx_align_data_reg ("RISING_EDGE"),
+        .sim_dpa_is_negative_ppm_drift ("OFF"),
+        .sim_dpa_net_ppm_variation (0),
+        .sim_dpa_output_clock_phase_shift (0),
+        .use_coreclock_input ("OFF"),
+        .use_dpll_rawperror ("OFF"),
+        .use_external_pll ("ON"),
+        .use_no_phase_shift ("ON"),
+        .x_on_bitslip ("ON"),
+        .clk_src_is_pll ("off"))
+      i_altlvds_rx (
+        .rx_inclock (clk),
+        .rx_in (data_in_p[l_inst]),
+        .rx_outclock (),
+        .rx_out ({data_out_s[0][l_inst],
+                  data_out_s[1][l_inst],
+                  data_out_s[2][l_inst],
+                  data_out_s[3][l_inst],
+                  data_out_s[4][l_inst],
+                  data_out_s[5][l_inst],
+                  data_out_s[6][l_inst],
+                  data_out_s[7][l_inst]}),
+        .rx_locked (),
+        .dpa_pll_cal_busy (),
+        .dpa_pll_recal (1'b0),
+        .pll_areset (~locked),
+        .pll_phasecounterselect (),
+        .pll_phasedone (1'b1),
+        .pll_phasestep (),
+        .pll_phaseupdown (),
+        .pll_scanclk (),
+        .rx_cda_max (),
+        .rx_cda_reset ({7{1'b0}}),
+        .rx_channel_data_align ({7{1'b0}}),
+        .rx_coreclk (1'b1),
+        .rx_data_align (1'b0),
+        .rx_data_align_reset (1'b0),
+        .rx_data_reset (1'b0),
+        .rx_deskew (1'b0),
+        .rx_divfwdclk (),
+        .rx_dpa_lock_reset ({7{1'b0}}),
+        .rx_dpa_locked (),
+        .rx_dpaclock (1'b0),
+        .rx_dpll_enable ({7{1'b1}}),
+        .rx_dpll_hold ({7{1'b0}}),
+        .rx_dpll_reset ({7{1'b0}}),
+        .rx_enable (loaden),
+        .rx_fifo_reset ({7{1'b0}}),
+        .rx_pll_enable (1'b1),
+        .rx_readclock (1'b0),
+        .rx_reset ({7{1'b0}}),
+        .rx_syncclock (1'b0));
+
+    end else begin
+      alt_serdes_in_core i_core (
+        .clk_export (clk),
+        .div_clk_export (div_clk),
+        .hs_phase_export (phase),
+        .loaden_export (loaden),
+        .locked_export (locked),
+        .data_in_export (data_in_p[l_inst]),
+        .data_s_export ({data_out_s[0][l_inst],
+                         data_out_s[1][l_inst],
+                         data_out_s[2][l_inst],
+                         data_out_s[3][l_inst],
+                         data_out_s[4][l_inst],
+                         data_out_s[5][l_inst],
+                         data_out_s[6][l_inst],
+                         data_out_s[7][l_inst]}),
+        .delay_locked_export (delay_locked_s[l_inst]));
+    end
   end
   endgenerate
 
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index 6857b5fd5..fd5cad778 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -64,6 +64,10 @@ module ad_serdes_out #(
   output  [(DATA_WIDTH-1):0]  data_out_p,
   output  [(DATA_WIDTH-1):0]  data_out_n);
 
+  // local parameter
+
+  localparam C5SOC = 1;
+
   // internal signals
 
   wire    [(DATA_WIDTH-1):0]  data_in_s[ 7:0];
@@ -94,19 +98,77 @@ module ad_serdes_out #(
   genvar l_inst;
   generate
   for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
-    alt_serdes_out_core i_core (
-      .clk_export (clk),
-      .div_clk_export (div_clk),
-      .loaden_export (loaden),
-      .data_out_export (data_out_p[l_inst]),
-      .data_s_export ({data_in_s2[0][l_inst],
-                       data_in_s2[1][l_inst],
-                       data_in_s2[2][l_inst],
-                       data_in_s2[3][l_inst],
-                       data_in_s2[4][l_inst],
-                       data_in_s2[5][l_inst],
-                       data_in_s2[6][l_inst],
-                       data_in_s2[7][l_inst]}));
+    if (DEVICE_TYPE == C5SOC) begin
+      altlvds_tx #(
+        .center_align_msb ("UNUSED"),
+        .common_rx_tx_pll ("ON"),
+        .coreclock_divide_by (1),
+        .data_rate ("500.0 Mbps"),
+        .deserialization_factor (4),
+        .differential_drive (0),
+        .enable_clock_pin_mode ("UNUSED"),
+        .implement_in_les ("OFF"),
+        .inclock_boost (0),
+        .inclock_data_alignment ("EDGE_ALIGNED"),
+        .inclock_period (4000),
+        .inclock_phase_shift (0),
+        .intended_device_family ("Cyclone V"),
+        .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_out"),
+        .lpm_type ("altlvds_tx"),
+        .multi_clock ("OFF"),
+        .number_of_channels (DATA_WIDTH),
+        .outclock_alignment ("EDGE_ALIGNED"),
+        .outclock_divide_by (2),
+        .outclock_duty_cycle (50),
+        .outclock_multiply_by (1),
+        .outclock_phase_shift (0),
+        .outclock_resource ("Regional clock"),
+        .output_data_rate (500),
+        .pll_compensation_mode ("AUTO"),
+        .pll_self_reset_on_loss_lock ("OFF"),
+        .preemphasis_setting (0),
+        .refclk_frequency ("250.000000 MHz"),
+        .registered_input ("TX_CORECLK"),
+        .use_external_pll ("ON"),
+        .use_no_phase_shift ("ON"),
+        .vod_setting (0),
+        .clk_src_is_pll ("off"))
+      i_altlvds_tx (
+        .tx_inclock (clk),
+        .tx_coreclock (div_clk),
+        .tx_in ({data_in_s2[0][l_inst],
+                 data_in_s2[1][l_inst],
+                 data_in_s2[2][l_inst],
+                 data_in_s2[3][l_inst],
+                 data_in_s2[4][l_inst],
+                 data_in_s2[5][l_inst],
+                 data_in_s2[6][l_inst],
+                 data_in_s2[7][l_inst]}),
+        .tx_outclock (),
+        .tx_out (data_out_p[l_inst]),
+        .tx_locked (),
+        .pll_areset (1'b0),
+        .sync_inclock (1'b0),
+        .tx_data_reset (1'b0),
+        .tx_enable (loaden),
+        .tx_pll_enable (1'b1),
+        .tx_syncclock (1'b0));
+
+    end else begin
+      alt_serdes_out_core i_core (
+        .clk_export (clk),
+        .div_clk_export (div_clk),
+        .loaden_export (loaden),
+        .data_out_export (data_out_p[l_inst]),
+        .data_s_export ({data_in_s2[0][l_inst],
+                         data_in_s2[1][l_inst],
+                         data_in_s2[2][l_inst],
+                         data_in_s2[3][l_inst],
+                         data_in_s2[4][l_inst],
+                         data_in_s2[5][l_inst],
+                         data_in_s2[6][l_inst],
+                         data_in_s2[7][l_inst]}));
+    end
   end
   endgenerate
 

From b8363d778d8a84a25f9df7b246ed9c6c8ce0d616 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 25 Oct 2016 20:36:56 +0300
Subject: [PATCH 637/972] arradio: Makefile update

---
 projects/arradio/c5soc/Makefile | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 46f14dfd4..6918a8b80 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -19,20 +19,17 @@ M_DEPS += ../common/arradio_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys
 M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
-M_DEPS += ../../../altera/axi_ad9361_cmos_if.v
-M_DEPS += ../../../altera/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
 M_DEPS += ../../../library/altera/common/ad_cmos_in.v
 M_DEPS += ../../../library/altera/common/ad_cmos_out.v
 M_DEPS += ../../../library/altera/common/ad_dcfilter.v
-M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
-M_DEPS += ../../../library/altera/common/ad_lvds_in.v
-M_DEPS += ../../../library/altera/common/ad_lvds_out.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/altera/common/ad_serdes_clk.v
 M_DEPS += ../../../library/altera/common/ad_serdes_in.v
 M_DEPS += ../../../library/altera/common/ad_serdes_out.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_cmos_if.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v

From 9ff92fdf5b0b4eef2b44a748e3fafd6728b3c87b Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 26 Oct 2016 11:07:29 +0300
Subject: [PATCH 638/972] pzsdr: Renamed projects to have lvds/cmos sufix

---
 projects/pzsdr/Makefile                       |  25 +-
 projects/pzsdr/ccbrk_cmos/Makefile            |   2 +-
 projects/pzsdr/ccbrk_cmos/system_project.tcl  |   8 +-
 projects/pzsdr/{ccbrk => ccbrk_lvds}/Makefile |   6 +-
 .../pzsdr/{ccbrk => ccbrk_lvds}/system_bd.tcl |   0
 .../{ccbrk => ccbrk_lvds}/system_constr.xdc   | 400 +++++++++---------
 .../{ccbrk => ccbrk_lvds}/system_project.tcl  |  12 +-
 .../pzsdr/{ccbrk => ccbrk_lvds}/system_top.v  |   0
 projects/pzsdr/{ccfmc => ccfmc_lvds}/Makefile |   6 +-
 .../pzsdr/{ccfmc => ccfmc_lvds}/system_bd.tcl |   0
 .../{ccfmc => ccfmc_lvds}/system_constr.xdc   |   0
 .../{ccfmc => ccfmc_lvds}/system_project.tcl  |   6 +-
 .../pzsdr/{ccfmc => ccfmc_lvds}/system_top.v  |   0
 projects/pzsdr/{ccpci => ccpci_lvds}/Makefile |   6 +-
 .../pzsdr/{ccpci => ccpci_lvds}/system_bd.tcl |   2 +-
 .../{ccpci => ccpci_lvds}/system_constr.xdc   |   0
 .../{ccpci => ccpci_lvds}/system_project.tcl  |   8 +-
 .../pzsdr/{ccpci => ccpci_lvds}/system_top.v  |   0
 projects/pzsdr/ccusb_lvds/Makefile            |   2 +-
 projects/pzsdr/ccusb_lvds/system_bd.tcl       |   2 +-
 .../{ccusb_lvds_bd.tcl => ccusb_bd.tcl}       |   0
 21 files changed, 239 insertions(+), 246 deletions(-)
 rename projects/pzsdr/{ccbrk => ccbrk_lvds}/Makefile (94%)
 rename projects/pzsdr/{ccbrk => ccbrk_lvds}/system_bd.tcl (100%)
 rename projects/pzsdr/{ccbrk => ccbrk_lvds}/system_constr.xdc (53%)
 rename projects/pzsdr/{ccbrk => ccbrk_lvds}/system_project.tcl (59%)
 rename projects/pzsdr/{ccbrk => ccbrk_lvds}/system_top.v (100%)
 rename projects/pzsdr/{ccfmc => ccfmc_lvds}/Makefile (95%)
 rename projects/pzsdr/{ccfmc => ccfmc_lvds}/system_bd.tcl (100%)
 rename projects/pzsdr/{ccfmc => ccfmc_lvds}/system_constr.xdc (100%)
 rename projects/pzsdr/{ccfmc => ccfmc_lvds}/system_project.tcl (79%)
 rename projects/pzsdr/{ccfmc => ccfmc_lvds}/system_top.v (100%)
 rename projects/pzsdr/{ccpci => ccpci_lvds}/Makefile (93%)
 rename projects/pzsdr/{ccpci => ccpci_lvds}/system_bd.tcl (96%)
 rename projects/pzsdr/{ccpci => ccpci_lvds}/system_constr.xdc (100%)
 rename projects/pzsdr/{ccpci => ccpci_lvds}/system_project.tcl (77%)
 rename projects/pzsdr/{ccpci => ccpci_lvds}/system_top.v (100%)
 rename projects/pzsdr/common/{ccusb_lvds_bd.tcl => ccusb_bd.tcl} (100%)

diff --git a/projects/pzsdr/Makefile b/projects/pzsdr/Makefile
index f75ab9a0e..a51f74003 100644
--- a/projects/pzsdr/Makefile
+++ b/projects/pzsdr/Makefile
@@ -7,36 +7,29 @@
 
 .PHONY: all clean clean-all 
 all:
-	-make -C ccbrk all
 	-make -C ccbrk_cmos all
-	-make -C ccfmc all
-	-make -C ccpci all
+	-make -C ccbrk_lvds all
+	-make -C ccfmc_lvds all
+	-make -C ccpci_lvds all
 	-make -C ccusb_lvds all
 	-make -C ccbox_lvds all
-	-make -C ccbrk all
-	-make -C ccbrk_cmos all
 
 
 clean: 
-	make -C ccbrk clean
 	make -C ccbrk_cmos clean
-	make -C ccfmc clean
-	make -C ccpci clean
+	make -C ccbrk_lvds clean
+	make -C ccfmc_lvds clean
+	make -C ccpci_lvds clean
 	make -C ccusb_lvds clean
 	make -C ccbox_lvds clean
-	make -C ccbrk clean
-	make -C ccbrk_cmos clean
-
 
 clean-all:
-	make -C ccbrk clean-all
 	make -C ccbrk_cmos clean-all
-	make -C ccfmc clean-all
-	make -C ccpci clean-all
+	make -C ccbrk_lvds clean-all
+	make -C ccfmc_lvds clean-all
+	make -C ccpci_lvds clean-all
 	make -C ccusb_lvds clean-all
 	make -C ccbox_lvds clean-all
-	make -C ccbrk clean-all
-	make -C ccbrk_cmos clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr/ccbrk_cmos/Makefile
index b89aaf1d3..4bdcdd903 100644
--- a/projects/pzsdr/ccbrk_cmos/Makefile
+++ b/projects/pzsdr/ccbrk_cmos/Makefile
@@ -9,7 +9,7 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_bd.tcl
 M_DEPS += ../common/ccbrk_bd.tcl
-M_DEPS += ../ccbrk/system_constr.xdc
+M_DEPS += ../ccbrk_lvds/system_constr.xdc
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
diff --git a/projects/pzsdr/ccbrk_cmos/system_project.tcl b/projects/pzsdr/ccbrk_cmos/system_project.tcl
index 5f0c51de7..8158fb805 100644
--- a/projects/pzsdr/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr/ccbrk_cmos/system_project.tcl
@@ -1,12 +1,12 @@
 
-source ../../scripts/adi_env.tcl 
-source $ad_hdl_dir/projects/scripts/adi_project.tcl 
-source $ad_hdl_dir/projects/scripts/adi_board.tcl 
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project_create ccbrk_cmos_pzsdr
 adi_project_files ccbrk_cmos_pzsdr [list \
   "system_top.v" \
-  "../ccbrk/system_constr.xdc"\
+  "../ccbrk_lvds/system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk_lvds/Makefile
similarity index 94%
rename from projects/pzsdr/ccbrk/Makefile
rename to projects/pzsdr/ccbrk_lvds/Makefile
index 1ee659550..3888e48e1 100644
--- a/projects/pzsdr/ccbrk/Makefile
+++ b/projects/pzsdr/ccbrk_lvds/Makefile
@@ -49,7 +49,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_pzsdr.sdk/system_top.hdf
+all: lib ccbrk_lvds_pzsdr.sdk/system_top.hdf
 
 
 clean: 
@@ -67,9 +67,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+ccbrk_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ccbrk_lvds_pzsdr_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr/ccbrk/system_bd.tcl b/projects/pzsdr/ccbrk_lvds/system_bd.tcl
similarity index 100%
rename from projects/pzsdr/ccbrk/system_bd.tcl
rename to projects/pzsdr/ccbrk_lvds/system_bd.tcl
diff --git a/projects/pzsdr/ccbrk/system_constr.xdc b/projects/pzsdr/ccbrk_lvds/system_constr.xdc
similarity index 53%
rename from projects/pzsdr/ccbrk/system_constr.xdc
rename to projects/pzsdr/ccbrk_lvds/system_constr.xdc
index ca0b31e54..d079c4d97 100644
--- a/projects/pzsdr/ccbrk/system_constr.xdc
+++ b/projects/pzsdr/ccbrk_lvds/system_constr.xdc
@@ -1,231 +1,231 @@
 
 ## constraints
-## loopback (P2/P13 are pin swapped on board - so skip gp_*[65]) 
+## loopback (P2/P13 are pin swapped on board - so skip gp_*[65])
 ## p4
 
-set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33              
-set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33              
-set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33              
-set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33              
-set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33              
-set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33          
-set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33              
-set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33          
-set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33              
-set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33              
-set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33         
-set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33              
-set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33              
-set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33              
-set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33              
-set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33              
-set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33             
-set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33          
-set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33             
-set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33          
-set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33        
-set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33        
+set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33
+set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33
+set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33
+set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33
+set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33
+set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33
+set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33
+set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33
+set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33
+set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33
+set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33
+set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33
+set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33
+set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33
+set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33
+set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33
+set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33
+set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33
+set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33
+set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33
+set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33
 
 ## p5
 
-set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33             
-set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33             
-set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33             
-set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33             
-set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33             
-set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33             
-set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33        
-set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33             
-set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33             
-set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33         
-set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33             
-set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33         
-set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33             
-set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33             
-set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33             
-set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33             
-set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34              
-set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34             
-set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33        
-set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33             
-set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33        
-set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33             
-set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33        
-set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33         
-set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33        
-set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33         
+set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33
+set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33
+set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33
+set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33
+set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33
+set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33
+set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33
+set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33
+set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33
+set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33
+set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33
+set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33
+set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33
+set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33
+set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33
+set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33
+set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34
+set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34
+set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33
+set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33
+set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33
+set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33
+set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33
+set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33
+set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33
+set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33
 
 ## p6
 
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34              
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34              
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34              
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34              
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34              
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34   
-set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34              
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34          
-set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34              
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34              
-set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34         
-set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34              
-set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34              
-set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34              
-set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34        
-set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34        
-set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34        
-set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34        
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34
+set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34
+set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34
+set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34
+set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34
+set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34
 
 ## p7
 
-set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34        
-set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34        
-set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34        
-set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34        
-set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34             
-set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34         
-set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34             
-set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34         
-set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34             
-set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34             
-set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34             
-set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34        
-set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34             
-set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34             
-set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33               
-set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34             
-set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34             
-set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33              
+set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34
+set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34
+set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34
+set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34
+set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34
+set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34
+set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34
+set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34
+set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34
+set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34
+set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34
+set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34
+set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34
+set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34
+set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34
+set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34
+set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34
+set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33
 
 ## p13
 
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12             
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12         
-set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12             
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12         
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12        
-set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12        
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12             
-set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12          
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12             
-set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12          
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12              
-set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12              
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12              
-set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12              
-set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12              
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12              
-set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12         
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12              
-set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12              
-set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12          
-set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12              
-set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12          
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12              
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12              
-set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12              
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12              
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12             
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12             
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12             
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12             
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12             
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12             
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12             
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12        
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12             
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12         
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12             
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12         
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12
+set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12
+set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12
+set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12
+set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12
+set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12
+set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12
+set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12
+set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12
+set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12
+set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12
+set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12
+set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12
 
 ## p2
 
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13                  
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13              
-set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13              
-set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13              
-set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13              
-set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13              
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13              
-set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13          
-set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13              
-set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13          
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13              
-set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13              
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13              
-set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13              
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13             
-set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13          
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13             
-set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13          
-set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13        
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13        
-set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13             
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13         
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13             
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13         
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13             
-set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13             
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13             
-set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13             
-set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13             
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13             
-set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13             
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13        
-set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13             
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13         
-set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13             
-set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13         
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13             
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13             
-set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13             
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13             
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13
+set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13
+set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13
+set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13
+set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13
+set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13
+set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13
+set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13
+set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13
+set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13
+set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13
+set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13
+set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13
+set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13
+set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13
+set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13
+set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13
+set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13
+set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13
 
 ## vcc
 
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13         
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13
 
 ## on board
 
-set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111           
-set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111           
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111              
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111              
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111              
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111              
-set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111              
-set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111              
-set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111              
-set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111              
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111              
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111              
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111              
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111              
-set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111              
-set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111              
-set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111              
-set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111              
+set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111
+set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111
+set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111
+set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111
+set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111
+set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111
+set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111
+set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111
+set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111
+set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111
+set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111
+set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111
+set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111
+set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111
+set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111
+set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111
+set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111
+set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111
 
 ## mio
 
-set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33        
-set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34             
-set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34              
-set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34             
+set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33
+set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34
 
 ## clocks
 
diff --git a/projects/pzsdr/ccbrk/system_project.tcl b/projects/pzsdr/ccbrk_lvds/system_project.tcl
similarity index 59%
rename from projects/pzsdr/ccbrk/system_project.tcl
rename to projects/pzsdr/ccbrk_lvds/system_project.tcl
index fe13d542f..f111b377b 100644
--- a/projects/pzsdr/ccbrk/system_project.tcl
+++ b/projects/pzsdr/ccbrk_lvds/system_project.tcl
@@ -1,10 +1,10 @@
 
-source ../../scripts/adi_env.tcl 
-source $ad_hdl_dir/projects/scripts/adi_project.tcl 
-source $ad_hdl_dir/projects/scripts/adi_board.tcl 
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccbrk_pzsdr
-adi_project_files ccbrk_pzsdr [list \
+adi_project_create ccbrk_lvds_pzsdr
+adi_project_files ccbrk_lvds_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
@@ -13,6 +13,6 @@ adi_project_files ccbrk_pzsdr [list \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
-adi_project_run ccbrk_pzsdr
+adi_project_run ccbrk_lvds_pzsdr
 
 
diff --git a/projects/pzsdr/ccbrk/system_top.v b/projects/pzsdr/ccbrk_lvds/system_top.v
similarity index 100%
rename from projects/pzsdr/ccbrk/system_top.v
rename to projects/pzsdr/ccbrk_lvds/system_top.v
diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc_lvds/Makefile
similarity index 95%
rename from projects/pzsdr/ccfmc/Makefile
rename to projects/pzsdr/ccfmc_lvds/Makefile
index 09dac0fe2..493f28e4e 100644
--- a/projects/pzsdr/ccfmc/Makefile
+++ b/projects/pzsdr/ccfmc_lvds/Makefile
@@ -53,7 +53,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccfmc_pzsdr.sdk/system_top.hdf
+all: lib ccfmc_lvds_pzsdr.sdk/system_top.hdf
 
 
 clean: 
@@ -75,9 +75,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccfmc_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+ccfmc_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccfmc_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ccfmc_lvds_pzsdr_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr/ccfmc/system_bd.tcl b/projects/pzsdr/ccfmc_lvds/system_bd.tcl
similarity index 100%
rename from projects/pzsdr/ccfmc/system_bd.tcl
rename to projects/pzsdr/ccfmc_lvds/system_bd.tcl
diff --git a/projects/pzsdr/ccfmc/system_constr.xdc b/projects/pzsdr/ccfmc_lvds/system_constr.xdc
similarity index 100%
rename from projects/pzsdr/ccfmc/system_constr.xdc
rename to projects/pzsdr/ccfmc_lvds/system_constr.xdc
diff --git a/projects/pzsdr/ccfmc/system_project.tcl b/projects/pzsdr/ccfmc_lvds/system_project.tcl
similarity index 79%
rename from projects/pzsdr/ccfmc/system_project.tcl
rename to projects/pzsdr/ccfmc_lvds/system_project.tcl
index 2cd3504f1..1cb1a010f 100644
--- a/projects/pzsdr/ccfmc/system_project.tcl
+++ b/projects/pzsdr/ccfmc_lvds/system_project.tcl
@@ -3,8 +3,8 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccfmc_pzsdr
-adi_project_files ccfmc_pzsdr [list \
+adi_project_create ccfmc_lvds_pzsdr
+adi_project_files ccfmc_lvds_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
@@ -12,6 +12,6 @@ adi_project_files ccfmc_pzsdr [list \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
-adi_project_run ccfmc_pzsdr
+adi_project_run ccfmc_lvds_pzsdr
 
 
diff --git a/projects/pzsdr/ccfmc/system_top.v b/projects/pzsdr/ccfmc_lvds/system_top.v
similarity index 100%
rename from projects/pzsdr/ccfmc/system_top.v
rename to projects/pzsdr/ccfmc_lvds/system_top.v
diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci_lvds/Makefile
similarity index 93%
rename from projects/pzsdr/ccpci/Makefile
rename to projects/pzsdr/ccpci_lvds/Makefile
index d0b9f415c..c7f6462e1 100644
--- a/projects/pzsdr/ccpci/Makefile
+++ b/projects/pzsdr/ccpci_lvds/Makefile
@@ -46,7 +46,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccpci_pzsdr.sdk/system_top.hdf
+all: lib ccpci_lvds_pzsdr.sdk/system_top.hdf
 
 
 clean: 
@@ -62,9 +62,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccpci_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+ccpci_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccpci_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ccpci_lvds_pzsdr_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr/ccpci/system_bd.tcl b/projects/pzsdr/ccpci_lvds/system_bd.tcl
similarity index 96%
rename from projects/pzsdr/ccpci/system_bd.tcl
rename to projects/pzsdr/ccpci_lvds/system_bd.tcl
index c3d58daac..d2b0d9edb 100644
--- a/projects/pzsdr/ccpci/system_bd.tcl
+++ b/projects/pzsdr/ccpci_lvds/system_bd.tcl
@@ -3,7 +3,7 @@ source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
 source ../common/ccpci_bd.tcl
 
 ## temporary
-## ila 
+## ila
 
 delete_bd_objs [get_bd_cells ila_adc]
 delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
diff --git a/projects/pzsdr/ccpci/system_constr.xdc b/projects/pzsdr/ccpci_lvds/system_constr.xdc
similarity index 100%
rename from projects/pzsdr/ccpci/system_constr.xdc
rename to projects/pzsdr/ccpci_lvds/system_constr.xdc
diff --git a/projects/pzsdr/ccpci/system_project.tcl b/projects/pzsdr/ccpci_lvds/system_project.tcl
similarity index 77%
rename from projects/pzsdr/ccpci/system_project.tcl
rename to projects/pzsdr/ccpci_lvds/system_project.tcl
index 8c9076c3a..21d73dd03 100644
--- a/projects/pzsdr/ccpci/system_project.tcl
+++ b/projects/pzsdr/ccpci_lvds/system_project.tcl
@@ -1,12 +1,12 @@
 
 
 
-source ../../scripts/adi_env.tcl 
+source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccpci_pzsdr
-adi_project_files ccpci_pzsdr [list \
+adi_project_create ccpci_lvds_pzsdr
+adi_project_files ccpci_lvds_pzsdr [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
@@ -16,6 +16,6 @@ adi_project_files ccpci_pzsdr [list \
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
 set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
 
-adi_project_run ccpci_pzsdr
+adi_project_run ccpci_lvds_pzsdr
 
 
diff --git a/projects/pzsdr/ccpci/system_top.v b/projects/pzsdr/ccpci_lvds/system_top.v
similarity index 100%
rename from projects/pzsdr/ccpci/system_top.v
rename to projects/pzsdr/ccpci_lvds/system_top.v
diff --git a/projects/pzsdr/ccusb_lvds/Makefile b/projects/pzsdr/ccusb_lvds/Makefile
index b78944d15..79dff492e 100644
--- a/projects/pzsdr/ccusb_lvds/Makefile
+++ b/projects/pzsdr/ccusb_lvds/Makefile
@@ -9,7 +9,7 @@ M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
-M_DEPS += ../common/ccusb_lvds_bd.tcl
+M_DEPS += ../common/ccusb_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
diff --git a/projects/pzsdr/ccusb_lvds/system_bd.tcl b/projects/pzsdr/ccusb_lvds/system_bd.tcl
index 0019e5509..a4a35835f 100644
--- a/projects/pzsdr/ccusb_lvds/system_bd.tcl
+++ b/projects/pzsdr/ccusb_lvds/system_bd.tcl
@@ -1,4 +1,4 @@
 
 source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
-source ../common/ccusb_lvds_bd.tcl
+source ../common/ccusb_bd.tcl
 
diff --git a/projects/pzsdr/common/ccusb_lvds_bd.tcl b/projects/pzsdr/common/ccusb_bd.tcl
similarity index 100%
rename from projects/pzsdr/common/ccusb_lvds_bd.tcl
rename to projects/pzsdr/common/ccusb_bd.tcl

From 6607aa707da321546e322a5e7a9d6e8b226a8b41 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 26 Oct 2016 11:09:43 +0300
Subject: [PATCH 639/972] pzsdr1: Renamed projects to have lvds/cmos sufix

---
 projects/pzsdr1/Makefile                             |  6 +++---
 projects/pzsdr1/{ccbrk => ccbrk_lvds}/Makefile       |  6 +++---
 projects/pzsdr1/{ccbrk => ccbrk_lvds}/system_bd.tcl  |  0
 .../pzsdr1/{ccbrk => ccbrk_lvds}/system_constr.xdc   |  0
 .../pzsdr1/{ccbrk => ccbrk_lvds}/system_project.tcl  | 12 ++++++------
 projects/pzsdr1/{ccbrk => ccbrk_lvds}/system_top.v   |  0
 6 files changed, 12 insertions(+), 12 deletions(-)
 rename projects/pzsdr1/{ccbrk => ccbrk_lvds}/Makefile (93%)
 rename projects/pzsdr1/{ccbrk => ccbrk_lvds}/system_bd.tcl (100%)
 rename projects/pzsdr1/{ccbrk => ccbrk_lvds}/system_constr.xdc (100%)
 rename projects/pzsdr1/{ccbrk => ccbrk_lvds}/system_project.tcl (54%)
 rename projects/pzsdr1/{ccbrk => ccbrk_lvds}/system_top.v (100%)

diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile
index 914b3e1fc..5db7627e6 100644
--- a/projects/pzsdr1/Makefile
+++ b/projects/pzsdr1/Makefile
@@ -8,19 +8,19 @@
 .PHONY: all clean clean-all 
 all:
 	-make -C ccbox_lvds all
-	-make -C ccbrk all
+	-make -C ccbrk_lvds all
 	-make -C ccbrk_cmos all
 
 
 clean: 
 	make -C ccbox_lvds clean
-	make -C ccbrk clean
+	make -C ccbrk_lvds clean
 	make -C ccbrk_cmos clean
 
 
 clean-all:
 	make -C ccbox_lvds clean-all
-	make -C ccbrk clean-all
+	make -C ccbrk_lvds clean-all
 	make -C ccbrk_cmos clean-all
 
 ####################################################################################
diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk_lvds/Makefile
similarity index 93%
rename from projects/pzsdr1/ccbrk/Makefile
rename to projects/pzsdr1/ccbrk_lvds/Makefile
index 20dd931d1..916b03227 100644
--- a/projects/pzsdr1/ccbrk/Makefile
+++ b/projects/pzsdr1/ccbrk_lvds/Makefile
@@ -47,7 +47,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_pzsdr1.sdk/system_top.hdf
+all: lib ccbrk_lvds_pzsdr1.sdk/system_top.hdf
 
 
 clean: 
@@ -64,9 +64,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
+ccbrk_lvds_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_pzsdr1_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> ccbrk_lvds_pzsdr1_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr1/ccbrk/system_bd.tcl b/projects/pzsdr1/ccbrk_lvds/system_bd.tcl
similarity index 100%
rename from projects/pzsdr1/ccbrk/system_bd.tcl
rename to projects/pzsdr1/ccbrk_lvds/system_bd.tcl
diff --git a/projects/pzsdr1/ccbrk/system_constr.xdc b/projects/pzsdr1/ccbrk_lvds/system_constr.xdc
similarity index 100%
rename from projects/pzsdr1/ccbrk/system_constr.xdc
rename to projects/pzsdr1/ccbrk_lvds/system_constr.xdc
diff --git a/projects/pzsdr1/ccbrk/system_project.tcl b/projects/pzsdr1/ccbrk_lvds/system_project.tcl
similarity index 54%
rename from projects/pzsdr1/ccbrk/system_project.tcl
rename to projects/pzsdr1/ccbrk_lvds/system_project.tcl
index 21967b370..f43f24109 100644
--- a/projects/pzsdr1/ccbrk/system_project.tcl
+++ b/projects/pzsdr1/ccbrk_lvds/system_project.tcl
@@ -1,10 +1,10 @@
 
-source ../../scripts/adi_env.tcl 
-source $ad_hdl_dir/projects/scripts/adi_project.tcl 
-source $ad_hdl_dir/projects/scripts/adi_board.tcl 
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccbrk_pzsdr1
-adi_project_files ccbrk_pzsdr1 [list \
+adi_project_create ccbrk_lvds_pzsdr1
+adi_project_files ccbrk_lvds_pzsdr1 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
@@ -12,6 +12,6 @@ adi_project_files ccbrk_pzsdr1 [list \
   "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
-adi_project_run ccbrk_pzsdr1
+adi_project_run ccbrk_lvds_pzsdr1
 
 
diff --git a/projects/pzsdr1/ccbrk/system_top.v b/projects/pzsdr1/ccbrk_lvds/system_top.v
similarity index 100%
rename from projects/pzsdr1/ccbrk/system_top.v
rename to projects/pzsdr1/ccbrk_lvds/system_top.v

From d4c7b7ca57d8f5f6972bab394b9e5cf4b1ae07d6 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 26 Oct 2016 11:12:02 +0300
Subject: [PATCH 640/972] ccusb_lvds: Fixed IIC constraints

---
 projects/pzsdr/ccusb_lvds/system_constr.xdc  | 3 +++
 projects/pzsdr/ccusb_lvds/system_project.tcl | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/projects/pzsdr/ccusb_lvds/system_constr.xdc b/projects/pzsdr/ccusb_lvds/system_constr.xdc
index 4f5b6ed5d..00a92a674 100644
--- a/projects/pzsdr/ccusb_lvds/system_constr.xdc
+++ b/projects/pzsdr/ccusb_lvds/system_constr.xdc
@@ -1,3 +1,6 @@
+# Default constraints have LVCMOS25, overwite it
+set_property  -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl]                                           ; ## IO_L5P_T0_13
+set_property  -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda]                                           ; ## IO_L5N_T0_13
 
 # USB_FX3
 
diff --git a/projects/pzsdr/ccusb_lvds/system_project.tcl b/projects/pzsdr/ccusb_lvds/system_project.tcl
index f65d6123d..244812979 100644
--- a/projects/pzsdr/ccusb_lvds/system_project.tcl
+++ b/projects/pzsdr/ccusb_lvds/system_project.tcl
@@ -11,6 +11,9 @@ adi_project_files ccusb_lvds_pzsdr [list \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
   "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
 
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
+set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
+
 adi_project_run ccusb_lvds_pzsdr
 
 

From f7e3703b98a6ae76b169ff45eecdee08b318a345 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 26 Oct 2016 13:12:53 -0400
Subject: [PATCH 641/972] axi_ad9371- avalon-s interfaces

---
 library/axi_ad9371/axi_ad9371_hw.tcl | 37 +++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 6 deletions(-)

diff --git a/library/axi_ad9371/axi_ad9371_hw.tcl b/library/axi_ad9371/axi_ad9371_hw.tcl
index a99138f28..cf1e4ca6b 100755
--- a/library/axi_ad9371/axi_ad9371_hw.tcl
+++ b/library/axi_ad9371/axi_ad9371_hw.tcl
@@ -30,6 +30,7 @@ add_fileset_file up_adc_common.v            VERILOG PATH $ad_hdl_dir/library/com
 add_fileset_file up_adc_channel.v           VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
 add_fileset_file up_dac_common.v            VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
 add_fileset_file up_dac_channel.v           VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
+add_fileset_file ad_xcvr_rx_if.v            VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
 add_fileset_file axi_ad9371_if.v            VERILOG PATH axi_ad9371_if.v
 add_fileset_file axi_ad9371_rx_channel.v    VERILOG PATH axi_ad9371_rx_channel.v
 add_fileset_file axi_ad9371_rx.v            VERILOG PATH axi_ad9371_rx.v
@@ -48,6 +49,13 @@ set_parameter_property ID TYPE INTEGER
 set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
+add_parameter DEVICE_TYPE INTEGER 0
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
 add_parameter DAC_DATAPATH_DISABLE INTEGER 0
 set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
 set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
@@ -96,14 +104,31 @@ add_interface_port s_axi s_axi_rready rready Input 1
 
 # transceiver interface
 
-ad_alt_intf clock   adc_clk         input   1
-ad_alt_intf signal  adc_rx_data     input   64  data
+ad_alt_intf clock adc_clk input 1
+ad_alt_intf signal adc_rx_sof input 4 export
+add_interface if_adc_rx_data avalon_streaming sink
+add_interface_port if_adc_rx_data adc_rx_data  data  input 64
+add_interface_port if_adc_rx_data adc_rx_valid valid input 1
+add_interface_port if_adc_rx_data adc_rx_ready ready output 1
+set_interface_property if_adc_rx_data associatedClock if_adc_clk
+set_interface_property if_adc_rx_data dataBitsPerSymbol 64
 
-ad_alt_intf clock   adc_os_clk      input   1
-ad_alt_intf signal  adc_rx_os_data  input   64  data
+ad_alt_intf clock adc_os_clk input 1
+ad_alt_intf signal adc_rx_os_sof input 4 export
+add_interface if_adc_rx_os_data avalon_streaming sink
+add_interface_port if_adc_rx_os_data adc_rx_os_data  data  input 64
+add_interface_port if_adc_rx_os_data adc_rx_os_valid valid input 1
+add_interface_port if_adc_rx_os_data adc_rx_os_ready ready output 1
+set_interface_property if_adc_rx_os_data associatedClock if_adc_os_clk
+set_interface_property if_adc_rx_os_data dataBitsPerSymbol 64
 
-ad_alt_intf clock   dac_clk         input   1
-ad_alt_intf signal  dac_tx_data     output  128 data
+ad_alt_intf clock dac_clk input 1
+add_interface if_dac_tx_data avalon_streaming source
+add_interface_port if_dac_tx_data dac_tx_data data output 128
+add_interface_port if_dac_tx_data dac_tx_valid valid output 1
+add_interface_port if_dac_tx_data dac_tx_ready ready input 1
+set_interface_property if_dac_tx_data associatedClock if_dac_clk
+set_interface_property if_dac_tx_data dataBitsPerSymbol 128
 
 # master/slave
 

From f752f0c9d7dc5a6bc5332c0f5a014a404f261084 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 26 Oct 2016 13:13:49 -0400
Subject: [PATCH 642/972] a10soc- xcvr updates

---
 projects/adrv9371x/a10soc/system_top.v        |  178 +-
 projects/adrv9371x/common/adrv9371x_qsys.tcl  | 1119 ++++---------
 projects/common/a10soc/a10soc_system_qsys.tcl | 1491 +++--------------
 3 files changed, 635 insertions(+), 2153 deletions(-)

diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v
index 1a350c207..c56298487 100644
--- a/projects/adrv9371x/a10soc/system_top.v
+++ b/projects/adrv9371x/a10soc/system_top.v
@@ -140,6 +140,9 @@ module system_top (
 
   // internal signals
 
+  wire              sys_hps_resetn;
+  wire              sys_resetn_s;
+  wire    [  7:0]   spi_csn;
   wire    [ 31:0]   gpio_i;
   wire    [ 31:0]   gpio_o;
 
@@ -160,95 +163,112 @@ module system_top (
   
   // gpio (max-v-u21)
 
-  assign gpio_i[15:8] = gpio_o[15:8];
-  assign gpio_i[ 7:0] = gpio_bd_i;
+  assign gpio_i[15:12] = gpio_o[15:12];
+  assign gpio_i[11: 4] = gpio_bd_i;
+  assign gpio_i[ 3: 0] = gpio_o[3:0];
 
   assign gpio_bd_o = gpio_o[3:0];
 
+  // spi
+
+  assign spi_csn_ad9528 = spi_csn[1];
+  assign spi_csn_ad9371 = spi_csn[0];
+  assign sys_resetn_s = sys_resetn & sys_hps_resetn;
+
   // instantiations
 
   system_bd i_system_bd (
-    .ad9371_gpio_export (ad9371_gpio),
-    .hps_ddr_mem_ck (hps_ddr_clk_p),
-    .hps_ddr_mem_ck_n (hps_ddr_clk_n),
-    .hps_ddr_mem_a (hsp_ddr_a),
-    .hps_ddr_mem_act_n (hps_ddr_act_n),
-    .hps_ddr_mem_ba (hps_ddr_ba),
-    .hps_ddr_mem_bg (hps_ddr_bg),
-    .hps_ddr_mem_cke (hps_ddr_cke),
-    .hps_ddr_mem_cs_n (hps_ddr_cs_n),
-    .hps_ddr_mem_odt (hps_ddr_odt),
-    .hps_ddr_mem_reset_n (hps_ddr_reset_n),
-    .hps_ddr_mem_par (hps_ddr_par),
-    .hps_ddr_mem_alert_n (hps_ddr_alert_n),
-    .hps_ddr_mem_dqs (hps_ddr_dqs_p),
-    .hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
-    .hps_ddr_mem_dq (hps_ddr_dq),
-    .hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
-    .hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
-    .hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
-    .hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
-    .hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
-    .hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
-    .hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
-    .hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
-    .hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
-    .hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
-    .hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
-    .hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
-    .hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
-    .hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
-    .hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
-    .hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
-    .hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
-    .hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
-    .hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
-    .hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
-    .hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
-    .hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
-    .hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
-    .hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
-    .hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
-    .hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
-    .hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
-    .hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
-    .hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
-    .hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
-    .hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
-    .hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
-    .hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
-    .hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
-    .hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
-    .hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
-    .hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
-    .hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
-    .hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
-    .hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
-    .hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
-    .hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
-    .hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
-    .hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
-    .hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
-    .hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
-    .hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
-    .xcvr_ref_clk_clk (ref_clk1),
-    .rx_data_rx_serial_data (rx_data[1:0]),
-    .rx_os_data_rx_serial_data (rx_data[3:2]),
-    .rx_os_sync_rx_sync (rx_os_sync),
-    .rx_os_sysref_rx_ext_sysref_in (sysref),
-    .rx_sync_rx_sync (rx_sync),
-    .rx_sysref_rx_ext_sysref_in (sysref),
+    .avl_ad9371_gpio_export (ad9371_gpio),
+    .rx_data_0_rx_serial_data (rx_data[0]),
+    .rx_data_1_rx_serial_data (rx_data[1]),
+    .rx_data_2_rx_serial_data (rx_data[2]),
+    .rx_data_3_rx_serial_data (rx_data[3]),
+    .rx_os_ref_clk_clk (ref_clk1),
+    .rx_os_sync_export (rx_os_sync),
+    .rx_os_sysref_export (sysref),
+    .rx_ref_clk_clk (ref_clk1),
+    .rx_sync_export (rx_sync),
+    .rx_sysref_export (sysref),
     .sys_clk_clk (sys_clk),
-    .sys_rst_reset_n (sys_resetn),
-    .tx_data_tx_serial_data ({tx_data[0],tx_data[3],tx_data[2],tx_data[1]}),
-    .tx_sync_tx_sync (tx_sync),
-    .tx_sysref_tx_ext_sysref_in (sysref),
-    .gpio_i_export (gpio_i),
-    .gpio_o_export (gpio_o),
+    .sys_gpio_in_export (gpio_i),
+    .sys_gpio_out_export (gpio_o),
+    .sys_hps_ddr_mem_ck (hps_ddr_clk_p),
+    .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
+    .sys_hps_ddr_mem_a (hsp_ddr_a),
+    .sys_hps_ddr_mem_act_n (hps_ddr_act_n),
+    .sys_hps_ddr_mem_ba (hps_ddr_ba),
+    .sys_hps_ddr_mem_bg (hps_ddr_bg),
+    .sys_hps_ddr_mem_cke (hps_ddr_cke),
+    .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
+    .sys_hps_ddr_mem_odt (hps_ddr_odt),
+    .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
+    .sys_hps_ddr_mem_par (hps_ddr_par),
+    .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
+    .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
+    .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
+    .sys_hps_ddr_mem_dq (hps_ddr_dq),
+    .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
+    .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
+    .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
+    .sys_hps_ddr_rstn_reset_n (sys_resetn),
+    .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
+    .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
+    .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
+    .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
+    .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
+    .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
+    .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
+    .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
+    .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
+    .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
+    .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
+    .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
+    .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
+    .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
+    .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
+    .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
+    .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
+    .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
+    .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
+    .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
+    .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
+    .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
+    .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
+    .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
+    .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
+    .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
+    .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
+    .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
+    .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
+    .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
+    .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
+    .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
+    .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
+    .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
+    .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
+    .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
+    .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
+    .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
+    .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
+    .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
+    .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
+    .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
+    .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
+    .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
+    .sys_hps_out_rstn_reset_n (sys_hps_resetn),
+    .sys_hps_rstn_reset_n (sys_resetn),
+    .sys_rstn_reset_n (sys_resetn_s),
     .sys_spi_MISO (spi_miso),
     .sys_spi_MOSI (spi_mosi),
     .sys_spi_SCLK (spi_clk),
-    .sys_spi_SS_n ({spi_csn_ad9528, spi_csn_ad9371}));
+    .sys_spi_SS_n (spi_csn),
+    .tx_data_0_tx_serial_data (tx_data[0]),
+    .tx_data_1_tx_serial_data (tx_data[1]),
+    .tx_data_2_tx_serial_data (tx_data[2]),
+    .tx_data_3_tx_serial_data (tx_data[3]),
+    .tx_ref_clk_clk (ref_clk1),
+    .tx_sync_export (tx_sync),
+    .tx_sysref_export (sysref));
 
 endmodule
 
diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index 2913a0b8b..01df30849 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -1,848 +1,361 @@
-# overwrite default settings
 
-set_instance_parameter_value sys_spi {clockPhase} {1}
-set_instance_parameter_value sys_spi {clockPolarity} {1}
-set_instance_parameter_value sys_spi {targetClockRate} {5000000.0}
+# ad9371_tx-xcvr
 
-# Add adrv9371x
+add_instance avl_ad9371_tx_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_ad9371_tx_xcvr {ID} {0}
+set_instance_parameter_value avl_ad9371_tx_xcvr {TX_OR_RX_N} {1}
+set_instance_parameter_value avl_ad9371_tx_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value avl_ad9371_tx_xcvr {LANE_RATE} {4915.2}
+set_instance_parameter_value avl_ad9371_tx_xcvr {PLLCLK_FREQUENCY} {2457.6}
+set_instance_parameter_value avl_ad9371_tx_xcvr {REFCLK_FREQUENCY} {122.88}
+set_instance_parameter_value avl_ad9371_tx_xcvr {CORECLK_FREQUENCY} {122.88}
+set_instance_parameter_value avl_ad9371_tx_xcvr {NUM_OF_LANES} {4}
+set_instance_parameter_value avl_ad9371_tx_xcvr {NUM_OF_CONVS} {4}
+set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_BCNT} {2}
+set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_ad9371_tx_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_ad9371_tx_xcvr {HD} {1}
+add_connection sys_clk.clk avl_ad9371_tx_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_ad9371_tx_xcvr.sys_resetn
+add_interface tx_ref_clk clock sink
+set_interface_property tx_ref_clk EXPORT_OF avl_ad9371_tx_xcvr.ref_clk
+add_interface tx_data_0 conduit end
+set_interface_property tx_data_0 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_0
+add_interface tx_data_1 conduit end
+set_interface_property tx_data_1 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_1
+add_interface tx_data_2 conduit end
+set_interface_property tx_data_2 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_2
+add_interface tx_data_3 conduit end
+set_interface_property tx_data_3 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_3
+add_interface tx_sysref conduit end
+set_interface_property tx_sysref EXPORT_OF avl_ad9371_tx_xcvr.sysref
+add_interface tx_sync conduit end
+set_interface_property tx_sync EXPORT_OF avl_ad9371_tx_xcvr.sync
+add_connection avl_ad9371_tx_xcvr.tx_phy_s_0 avl_ad9371_tx_xcvr.tx_ip_s_3
+add_connection avl_ad9371_tx_xcvr.tx_phy_s_1 avl_ad9371_tx_xcvr.tx_ip_s_0
+add_connection avl_ad9371_tx_xcvr.tx_phy_s_2 avl_ad9371_tx_xcvr.tx_ip_s_1
+add_connection avl_ad9371_tx_xcvr.tx_phy_s_3 avl_ad9371_tx_xcvr.tx_ip_s_2
+add_connection avl_ad9371_tx_xcvr.tx_ip_d_3 avl_ad9371_tx_xcvr.tx_phy_d_0
+add_connection avl_ad9371_tx_xcvr.tx_ip_d_0 avl_ad9371_tx_xcvr.tx_phy_d_1
+add_connection avl_ad9371_tx_xcvr.tx_ip_d_1 avl_ad9371_tx_xcvr.tx_phy_d_2
+add_connection avl_ad9371_tx_xcvr.tx_ip_d_2 avl_ad9371_tx_xcvr.tx_phy_d_3
 
-add_instance xcvr_ref_clk altera_clock_bridge 16.0
-set_instance_parameter_value xcvr_ref_clk {EXPLICIT_CLOCK_RATE} {122880000.0}
-set_instance_parameter_value xcvr_ref_clk {NUM_CLOCK_OUTPUTS} {1}
+# ad9371_tx-xcvr
 
-add_instance xcvr_pll altera_iopll 16.0
-set_instance_parameter_value xcvr_pll {gui_device_speed_grade} {1}
-set_instance_parameter_value xcvr_pll {gui_en_reconf} {1}
-set_instance_parameter_value xcvr_pll {gui_en_dps_ports} {0}
-set_instance_parameter_value xcvr_pll {gui_pll_mode} {Integer-N PLL}
-set_instance_parameter_value xcvr_pll {gui_reference_clock_frequency} {122.88}
-set_instance_parameter_value xcvr_pll {gui_fractional_cout} {32}
-set_instance_parameter_value xcvr_pll {gui_dsm_out_sel} {1st_order}
-set_instance_parameter_value xcvr_pll {gui_use_locked} {0}
-set_instance_parameter_value xcvr_pll {gui_en_adv_params} {0}
-set_instance_parameter_value xcvr_pll {gui_pll_bandwidth_preset} {Low}
-set_instance_parameter_value xcvr_pll {gui_lock_setting} {Low Lock Time}
-set_instance_parameter_value xcvr_pll {gui_pll_auto_reset} {0}
-set_instance_parameter_value xcvr_pll {gui_en_lvds_ports} {Disabled}
-set_instance_parameter_value xcvr_pll {gui_operation_mode} {direct}
-set_instance_parameter_value xcvr_pll {gui_feedback_clock} {Global Clock}
-set_instance_parameter_value xcvr_pll {gui_clock_to_compensate} {0}
-set_instance_parameter_value xcvr_pll {gui_use_NDFB_modes} {0}
-set_instance_parameter_value xcvr_pll {gui_refclk_switch} {0}
-set_instance_parameter_value xcvr_pll {gui_refclk1_frequency} {100.0}
-set_instance_parameter_value xcvr_pll {gui_en_phout_ports} {0}
-set_instance_parameter_value xcvr_pll {gui_phout_division} {1}
-set_instance_parameter_value xcvr_pll {gui_en_extclkout_ports} {0}
-set_instance_parameter_value xcvr_pll {gui_number_of_clocks} {3}
-set_instance_parameter_value xcvr_pll {gui_multiply_factor} {6}
-set_instance_parameter_value xcvr_pll {gui_divide_factor_n} {1}
-set_instance_parameter_value xcvr_pll {gui_frac_multiply_factor} {1.0}
-set_instance_parameter_value xcvr_pll {gui_fix_vco_frequency} {0}
-set_instance_parameter_value xcvr_pll {gui_fixed_vco_frequency} {600.0}
-set_instance_parameter_value xcvr_pll {gui_vco_frequency} {600.0}
-set_instance_parameter_value xcvr_pll {gui_enable_output_counter_cascading} {0}
-set_instance_parameter_value xcvr_pll {gui_mif_gen_options} {Generate New MIF File}
-set_instance_parameter_value xcvr_pll {gui_new_mif_file_path} {~/pll.mif}
-set_instance_parameter_value xcvr_pll {gui_existing_mif_file_path} {~/pll.mif}
-set_instance_parameter_value xcvr_pll {gui_mif_config_name} {unnamed}
-set_instance_parameter_value xcvr_pll {gui_active_clk} {0}
-set_instance_parameter_value xcvr_pll {gui_clk_bad} {0}
-set_instance_parameter_value xcvr_pll {gui_switchover_mode} {Automatic Switchover}
-set_instance_parameter_value xcvr_pll {gui_switchover_delay} {0}
-set_instance_parameter_value xcvr_pll {gui_enable_cascade_out} {0}
-set_instance_parameter_value xcvr_pll {gui_cascade_outclk_index} {0}
-set_instance_parameter_value xcvr_pll {gui_enable_cascade_in} {0}
-set_instance_parameter_value xcvr_pll {gui_pll_cascading_mode} {adjpllin}
-set_instance_parameter_value xcvr_pll {gui_enable_mif_dps} {0}
-set_instance_parameter_value xcvr_pll {gui_dps_cntr} {C0}
-set_instance_parameter_value xcvr_pll {gui_dps_num} {1}
-set_instance_parameter_value xcvr_pll {gui_dps_dir} {Positive}
-set_instance_parameter_value xcvr_pll {gui_extclkout_0_source} {C0}
-set_instance_parameter_value xcvr_pll {gui_extclkout_1_source} {C0}
-set_instance_parameter_value xcvr_pll {gui_clock_name_global} {0}
-set_instance_parameter_value xcvr_pll {gui_clock_name_string0} {tx_dac_clk}
-set_instance_parameter_value xcvr_pll {gui_clock_name_string1} {rx_adc_clk}
-set_instance_parameter_value xcvr_pll {gui_clock_name_string2} {rx_adc_os_clk}
-set_instance_parameter_value xcvr_pll {gui_divide_factor_c0} {6}
-set_instance_parameter_value xcvr_pll {gui_divide_factor_c1} {6}
-set_instance_parameter_value xcvr_pll {gui_divide_factor_c2} {6}
-set_instance_parameter_value xcvr_pll {gui_cascade_counter0} {0}
-set_instance_parameter_value xcvr_pll {gui_cascade_counter1} {0}
-set_instance_parameter_value xcvr_pll {gui_cascade_counter2} {0}
-set_instance_parameter_value xcvr_pll {gui_output_clock_frequency0} {122.88}
-set_instance_parameter_value xcvr_pll {gui_output_clock_frequency1} {122.88}
-set_instance_parameter_value xcvr_pll {gui_output_clock_frequency2} {122.88}
-set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency0} {100.0}
-set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency1} {100.0}
-set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency2} {100.0}
-set_instance_parameter_value xcvr_pll {gui_ps_units0} {ps}
-set_instance_parameter_value xcvr_pll {gui_ps_units1} {ps}
-set_instance_parameter_value xcvr_pll {gui_ps_units2} {ps}
-set_instance_parameter_value xcvr_pll {gui_phase_shift0} {0.0}
-set_instance_parameter_value xcvr_pll {gui_phase_shift1} {0.0}
-set_instance_parameter_value xcvr_pll {gui_phase_shift2} {0.0}
-set_instance_parameter_value xcvr_pll {gui_phase_shift_deg0} {0.0}
-set_instance_parameter_value xcvr_pll {gui_phase_shift_deg1} {0.0}
-set_instance_parameter_value xcvr_pll {gui_phase_shift_deg2} {0.0}
-set_instance_parameter_value xcvr_pll {gui_actual_phase_shift0} {0.0}
-set_instance_parameter_value xcvr_pll {gui_actual_phase_shift1} {0.0}
-set_instance_parameter_value xcvr_pll {gui_actual_phase_shift2} {0.0}
-set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg0} {0.0}
-set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg1} {0.0}
-set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg2} {0.0}
-set_instance_parameter_value xcvr_pll {gui_duty_cycle0} {50.0}
-set_instance_parameter_value xcvr_pll {gui_duty_cycle1} {50.0}
-set_instance_parameter_value xcvr_pll {gui_duty_cycle2} {50.0}
-set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle0} {50.0}
-set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle1} {50.0}
-set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle2} {50.0}
+add_instance axi_ad9371_tx_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_ad9371_tx_xcvr {ID} {0}
+set_instance_parameter_value axi_ad9371_tx_xcvr {TX_OR_RX_N} {1}
+set_instance_parameter_value axi_ad9371_tx_xcvr {NUM_OF_LANES} {4}
+add_connection sys_clk.clk axi_ad9371_tx_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9371_tx_xcvr.s_axi_reset
+add_connection axi_ad9371_tx_xcvr.if_up_rst avl_ad9371_tx_xcvr.rst
+add_connection avl_ad9371_tx_xcvr.ready axi_ad9371_tx_xcvr.ready
+add_connection axi_ad9371_tx_xcvr.core_pll_locked avl_ad9371_tx_xcvr.core_pll_locked
 
-add_instance xcvr_pll_reconfig altera_pll_reconfig 16.0
-set_instance_parameter_value xcvr_pll_reconfig {ENABLE_MIF} {0}
-set_instance_parameter_value xcvr_pll_reconfig {MIF_FILE_NAME} {}
-set_instance_parameter_value xcvr_pll_reconfig {ENABLE_BYTEENABLE} {0}
+# ad9371_rx-xcvr
 
-add_instance xcvr_tx_rst_cntrl altera_xcvr_reset_control 16.0
-set_instance_parameter_value xcvr_tx_rst_cntrl {CHANNELS} {4}
-set_instance_parameter_value xcvr_tx_rst_cntrl {PLLS} {1}
-set_instance_parameter_value xcvr_tx_rst_cntrl {SYS_CLK_IN_MHZ} {100}
-set_instance_parameter_value xcvr_tx_rst_cntrl {SYNCHRONIZE_RESET} {1}
-set_instance_parameter_value xcvr_tx_rst_cntrl {REDUCED_SIM_TIME} {1}
-set_instance_parameter_value xcvr_tx_rst_cntrl {gui_split_interfaces} {0}
-set_instance_parameter_value xcvr_tx_rst_cntrl {TX_PLL_ENABLE} {1}
-set_instance_parameter_value xcvr_tx_rst_cntrl {T_PLL_POWERDOWN} {1000}
-set_instance_parameter_value xcvr_tx_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0}
-set_instance_parameter_value xcvr_tx_rst_cntrl {TX_ENABLE} {1}
-set_instance_parameter_value xcvr_tx_rst_cntrl {TX_PER_CHANNEL} {0}
-set_instance_parameter_value xcvr_tx_rst_cntrl {gui_tx_auto_reset} {0}
-set_instance_parameter_value xcvr_tx_rst_cntrl {T_TX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_tx_rst_cntrl {T_TX_DIGITALRESET} {70000}
-set_instance_parameter_value xcvr_tx_rst_cntrl {T_PLL_LOCK_HYST} {0}
-set_instance_parameter_value xcvr_tx_rst_cntrl {gui_pll_cal_busy} {1}
-set_instance_parameter_value xcvr_tx_rst_cntrl {RX_ENABLE} {0}
-set_instance_parameter_value xcvr_tx_rst_cntrl {RX_PER_CHANNEL} {0}
-set_instance_parameter_value xcvr_tx_rst_cntrl {gui_rx_auto_reset} {0}
-set_instance_parameter_value xcvr_tx_rst_cntrl {T_RX_ANALOGRESET} {40}
-set_instance_parameter_value xcvr_tx_rst_cntrl {T_RX_DIGITALRESET} {4000}
+add_instance avl_ad9371_rx_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_ad9371_rx_xcvr {ID} {1}
+set_instance_parameter_value avl_ad9371_rx_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value avl_ad9371_rx_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value avl_ad9371_rx_xcvr {LANE_RATE} {4915.2}
+set_instance_parameter_value avl_ad9371_rx_xcvr {PLLCLK_FREQUENCY} {2457.6}
+set_instance_parameter_value avl_ad9371_rx_xcvr {REFCLK_FREQUENCY} {122.88}
+set_instance_parameter_value avl_ad9371_rx_xcvr {CORECLK_FREQUENCY} {122.88}
+set_instance_parameter_value avl_ad9371_rx_xcvr {NUM_OF_LANES} {2}
+set_instance_parameter_value avl_ad9371_rx_xcvr {NUM_OF_CONVS} {4}
+set_instance_parameter_value avl_ad9371_rx_xcvr {FRM_BCNT} {4}
+set_instance_parameter_value avl_ad9371_rx_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_ad9371_rx_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_ad9371_rx_xcvr {HD} {1}
+add_connection sys_clk.clk avl_ad9371_rx_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_ad9371_rx_xcvr.sys_resetn
+add_interface rx_ref_clk clock sink
+set_interface_property rx_ref_clk EXPORT_OF avl_ad9371_rx_xcvr.ref_clk
+add_interface rx_data_0 conduit end
+set_interface_property rx_data_0 EXPORT_OF avl_ad9371_rx_xcvr.rx_data_0
+add_interface rx_data_1 conduit end
+set_interface_property rx_data_1 EXPORT_OF avl_ad9371_rx_xcvr.rx_data_1
+add_interface rx_sysref conduit end
+set_interface_property rx_sysref EXPORT_OF avl_ad9371_rx_xcvr.sysref
+add_interface rx_sync conduit end
+set_interface_property rx_sync EXPORT_OF avl_ad9371_rx_xcvr.sync
 
-add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 16.0
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_debug} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_jtag_enable} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_enable_avmm_busy_port} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_user_identifier} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_csr_soft_logic_enable} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_file_prefix} {altera_xcvr_atx_pll_a10}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_sv_file_enable} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_h_file_enable} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_txt_file_enable} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_mif_file_enable} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_multi_enable} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_profile_cnt} {2}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_profile_select} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_param_vals1} {}
-set_instance_parameter_value xcvr_tx_lane_pll {rcfg_param_vals2} {}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_manual_configuration} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {generate_docs} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {generate_add_hdl_instance_example} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {test_mode} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_pld_atx_cal_busy_port} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_debug_ports_parameters} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {support_mode} {user_mode}
-set_instance_parameter_value xcvr_tx_lane_pll {message_level} {error}
-set_instance_parameter_value xcvr_tx_lane_pll {prot_mode} {Basic}
-set_instance_parameter_value xcvr_tx_lane_pll {bw_sel} {medium}
-set_instance_parameter_value xcvr_tx_lane_pll {refclk_cnt} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {refclk_index} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {silicon_rev} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {primary_pll_buffer} {GX clock output buffer}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_8G_path} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_16G_path} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_pcie_clk} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_cascade_out} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_hip_cal_done_port} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_hip_cal_en} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {2457.6}
-set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {122.88}
-set_instance_parameter_value xcvr_tx_lane_pll {set_manual_reference_clock_frequency} {200.0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_fref_clock_frequency} {156.25}
-set_instance_parameter_value xcvr_tx_lane_pll {select_manual_config} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_m_counter} {24}
-set_instance_parameter_value xcvr_tx_lane_pll {set_ref_clk_div} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_l_counter} {16}
-set_instance_parameter_value xcvr_tx_lane_pll {set_l_cascade_counter} {15}
-set_instance_parameter_value xcvr_tx_lane_pll {set_l_cascade_predivider} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {set_k_counter} {2000000000.0}
-set_instance_parameter_value xcvr_tx_lane_pll {set_altera_xcvr_atx_pll_a10_calibration_en} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_analog_resets} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_mcgb} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {mcgb_div} {1}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_hfreq_clk} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_mcgb_pcie_clksw} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {mcgb_aux_clkin_cnt} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_bonding_clks} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_fb_comp_bonding} {0}
-set_instance_parameter_value xcvr_tx_lane_pll {pma_width} {64}
-set_instance_parameter_value xcvr_tx_lane_pll {enable_pld_mcgb_cal_busy_port} {0}
+# ad9371_rx-xcvr
 
-add_instance xcvr_tx_core altera_jesd204 16.0
-set_instance_parameter_value xcvr_tx_core {wrapper_opt} {base_phy}
-set_instance_parameter_value xcvr_tx_core {sdc_constraint} {1.0}
-set_instance_parameter_value xcvr_tx_core {DATA_PATH} {TX}
-set_instance_parameter_value xcvr_tx_core {SUBCLASSV} {1}
-set_instance_parameter_value xcvr_tx_core {lane_rate} {4915.2}
-set_instance_parameter_value xcvr_tx_core {PCS_CONFIG} {JESD_PCS_CFG1}
-set_instance_parameter_value xcvr_tx_core {pll_type} {CMU}
-set_instance_parameter_value xcvr_tx_core {bonded_mode} {non_bonded}
-set_instance_parameter_value xcvr_tx_core {REFCLK_FREQ} {125.0}
-set_instance_parameter_value xcvr_tx_core {bitrev_en} {0}
-set_instance_parameter_value xcvr_tx_core {pll_reconfig_enable} {1}
-set_instance_parameter_value xcvr_tx_core {rcfg_jtag_enable} {0}
-set_instance_parameter_value xcvr_tx_core {set_capability_reg_enable} {1}
-set_instance_parameter_value xcvr_tx_core {set_user_identifier} {0}
-set_instance_parameter_value xcvr_tx_core {set_csr_soft_logic_enable} {1}
-set_instance_parameter_value xcvr_tx_core {set_prbs_soft_logic_enable} {0}
-set_instance_parameter_value xcvr_tx_core {L} {4}
-set_instance_parameter_value xcvr_tx_core {M} {4}
-set_instance_parameter_value xcvr_tx_core {GUI_EN_CFG_F} {0}
-set_instance_parameter_value xcvr_tx_core {GUI_CFG_F} {4}
-set_instance_parameter_value xcvr_tx_core {N} {16}
-set_instance_parameter_value xcvr_tx_core {N_PRIME} {16}
-set_instance_parameter_value xcvr_tx_core {S} {1}
-set_instance_parameter_value xcvr_tx_core {K} {32}
-set_instance_parameter_value xcvr_tx_core {SCR} {1}
-set_instance_parameter_value xcvr_tx_core {CS} {0}
-set_instance_parameter_value xcvr_tx_core {CF} {0}
-set_instance_parameter_value xcvr_tx_core {HD} {0}
-set_instance_parameter_value xcvr_tx_core {ECC_EN} {0}
-set_instance_parameter_value xcvr_tx_core {DLB_TEST} {0}
-set_instance_parameter_value xcvr_tx_core {PHADJ} {0}
-set_instance_parameter_value xcvr_tx_core {ADJCNT} {0}
-set_instance_parameter_value xcvr_tx_core {ADJDIR} {0}
-set_instance_parameter_value xcvr_tx_core {OPTIMIZE} {0}
-set_instance_parameter_value xcvr_tx_core {DID} {0}
-set_instance_parameter_value xcvr_tx_core {BID} {0}
-set_instance_parameter_value xcvr_tx_core {LID0} {0}
-set_instance_parameter_value xcvr_tx_core {LID1} {1}
-set_instance_parameter_value xcvr_tx_core {LID2} {2}
-set_instance_parameter_value xcvr_tx_core {LID3} {3}
-set_instance_parameter_value xcvr_tx_core {LID4} {4}
-set_instance_parameter_value xcvr_tx_core {LID5} {5}
-set_instance_parameter_value xcvr_tx_core {LID6} {6}
-set_instance_parameter_value xcvr_tx_core {LID7} {7}
-set_instance_parameter_value xcvr_tx_core {JESDV} {1}
-set_instance_parameter_value xcvr_tx_core {RES1} {0}
-set_instance_parameter_value xcvr_tx_core {RES2} {0}
-set_instance_parameter_value xcvr_tx_core {TEST_COMPONENTS_EN} {0}
-set_instance_parameter_value xcvr_tx_core {TERMINATE_RECONFIG_EN} {0}
-set_instance_parameter_value xcvr_tx_core {ED_GENERIC_5SERIES} {No}
-set_instance_parameter_value xcvr_tx_core {ED_GENERIC_A10} {No}
-set_instance_parameter_value xcvr_tx_core {ED_FILESET_SIM} {0}
-set_instance_parameter_value xcvr_tx_core {ED_FILESET_SYNTH} {0}
-set_instance_parameter_value xcvr_tx_core {ED_HDL_FORMAT_SIM} {VERILOG}
-set_instance_parameter_value xcvr_tx_core {ED_HDL_FORMAT_SYNTH} {VERILOG}
-set_instance_parameter_value xcvr_tx_core {ED_DEV_KIT} {NONE}
+add_instance axi_ad9371_rx_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_ad9371_rx_xcvr {ID} {1}
+set_instance_parameter_value axi_ad9371_rx_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value axi_ad9371_rx_xcvr {NUM_OF_LANES} {2}
+add_connection sys_clk.clk axi_ad9371_rx_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9371_rx_xcvr.s_axi_reset
+add_connection axi_ad9371_rx_xcvr.if_up_rst avl_ad9371_rx_xcvr.rst
+add_connection avl_ad9371_rx_xcvr.ready axi_ad9371_rx_xcvr.ready
+add_connection axi_ad9371_rx_xcvr.core_pll_locked avl_ad9371_rx_xcvr.core_pll_locked
 
-add_instance axi_jesd_xcvr axi_jesd_xcvr 1.0
-set_instance_parameter_value axi_jesd_xcvr {ID} {0}
-set_instance_parameter_value axi_jesd_xcvr {DEVICE_TYPE} {0}
-set_instance_parameter_value axi_jesd_xcvr {TX_NUM_OF_LANES} {4}
-set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {2}
+# ad9371_rx_os-xcvr
 
-add_instance xcvr_rx_rst_cntrl altera_xcvr_reset_control 16.0
-set_instance_parameter_value xcvr_rx_rst_cntrl {CHANNELS} {2}
-set_instance_parameter_value xcvr_rx_rst_cntrl {PLLS} {1}
-set_instance_parameter_value xcvr_rx_rst_cntrl {SYS_CLK_IN_MHZ} {100}
-set_instance_parameter_value xcvr_rx_rst_cntrl {SYNCHRONIZE_RESET} {1}
-set_instance_parameter_value xcvr_rx_rst_cntrl {REDUCED_SIM_TIME} {1}
-set_instance_parameter_value xcvr_rx_rst_cntrl {gui_split_interfaces} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {TX_PLL_ENABLE} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {T_PLL_POWERDOWN} {1000}
-set_instance_parameter_value xcvr_rx_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {TX_ENABLE} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {TX_PER_CHANNEL} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {gui_tx_auto_reset} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {T_TX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_rx_rst_cntrl {T_TX_DIGITALRESET} {70000}
-set_instance_parameter_value xcvr_rx_rst_cntrl {T_PLL_LOCK_HYST} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {gui_pll_cal_busy} {1}
-set_instance_parameter_value xcvr_rx_rst_cntrl {RX_ENABLE} {1}
-set_instance_parameter_value xcvr_rx_rst_cntrl {RX_PER_CHANNEL} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {gui_rx_auto_reset} {0}
-set_instance_parameter_value xcvr_rx_rst_cntrl {T_RX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_rx_rst_cntrl {T_RX_DIGITALRESET} {4000}
+add_instance avl_ad9371_rx_os_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {ID} {1}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {LANE_RATE} {10000.0}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {PLLCLK_FREQUENCY} {5000.0}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {REFCLK_FREQUENCY} {500.0}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {CORECLK_FREQUENCY} {250.0}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_LANES} {2}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_CONVS} {2}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_BCNT} {2}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {HD} {1}
+add_connection sys_clk.clk avl_ad9371_rx_os_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_ad9371_rx_os_xcvr.sys_resetn
+add_interface rx_os_ref_clk clock sink
+set_interface_property rx_os_ref_clk EXPORT_OF avl_ad9371_rx_os_xcvr.ref_clk
+add_interface rx_data_2 conduit end
+set_interface_property rx_data_2 EXPORT_OF avl_ad9371_rx_os_xcvr.rx_data_0
+add_interface rx_data_3 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_ad9371_rx_os_xcvr.rx_data_1
+add_interface rx_os_sysref conduit end
+set_interface_property rx_os_sysref EXPORT_OF avl_ad9371_rx_os_xcvr.sysref
+add_interface rx_os_sync conduit end
+set_interface_property rx_os_sync EXPORT_OF avl_ad9371_rx_os_xcvr.sync
 
-add_instance xcvr_rx_core altera_jesd204 16.0
-set_instance_parameter_value xcvr_rx_core {wrapper_opt} {base_phy}
-set_instance_parameter_value xcvr_rx_core {sdc_constraint} {1.0}
-set_instance_parameter_value xcvr_rx_core {DATA_PATH} {RX}
-set_instance_parameter_value xcvr_rx_core {SUBCLASSV} {1}
-set_instance_parameter_value xcvr_rx_core {lane_rate} {4915.2}
-set_instance_parameter_value xcvr_rx_core {PCS_CONFIG} {JESD_PCS_CFG1}
-set_instance_parameter_value xcvr_rx_core {pll_type} {CMU}
-set_instance_parameter_value xcvr_rx_core {bonded_mode} {non_bonded}
-set_instance_parameter_value xcvr_rx_core {REFCLK_FREQ} {122.88}
-set_instance_parameter_value xcvr_rx_core {bitrev_en} {0}
-set_instance_parameter_value xcvr_rx_core {pll_reconfig_enable} {0}
-set_instance_parameter_value xcvr_rx_core {rcfg_jtag_enable} {0}
-set_instance_parameter_value xcvr_rx_core {set_capability_reg_enable} {0}
-set_instance_parameter_value xcvr_rx_core {set_user_identifier} {0}
-set_instance_parameter_value xcvr_rx_core {set_csr_soft_logic_enable} {0}
-set_instance_parameter_value xcvr_rx_core {set_prbs_soft_logic_enable} {0}
-set_instance_parameter_value xcvr_rx_core {L} {2}
-set_instance_parameter_value xcvr_rx_core {M} {4}
-set_instance_parameter_value xcvr_rx_core {GUI_EN_CFG_F} {0}
-set_instance_parameter_value xcvr_rx_core {GUI_CFG_F} {4}
-set_instance_parameter_value xcvr_rx_core {N} {16}
-set_instance_parameter_value xcvr_rx_core {N_PRIME} {16}
-set_instance_parameter_value xcvr_rx_core {S} {1}
-set_instance_parameter_value xcvr_rx_core {K} {32}
-set_instance_parameter_value xcvr_rx_core {SCR} {1}
-set_instance_parameter_value xcvr_rx_core {CS} {0}
-set_instance_parameter_value xcvr_rx_core {CF} {0}
-set_instance_parameter_value xcvr_rx_core {HD} {0}
-set_instance_parameter_value xcvr_rx_core {ECC_EN} {0}
-set_instance_parameter_value xcvr_rx_core {DLB_TEST} {0}
-set_instance_parameter_value xcvr_rx_core {PHADJ} {0}
-set_instance_parameter_value xcvr_rx_core {ADJCNT} {0}
-set_instance_parameter_value xcvr_rx_core {ADJDIR} {0}
-set_instance_parameter_value xcvr_rx_core {OPTIMIZE} {0}
-set_instance_parameter_value xcvr_rx_core {DID} {0}
-set_instance_parameter_value xcvr_rx_core {BID} {0}
-set_instance_parameter_value xcvr_rx_core {LID0} {0}
-set_instance_parameter_value xcvr_rx_core {LID1} {1}
-set_instance_parameter_value xcvr_rx_core {LID2} {2}
-set_instance_parameter_value xcvr_rx_core {LID3} {3}
-set_instance_parameter_value xcvr_rx_core {LID4} {4}
-set_instance_parameter_value xcvr_rx_core {LID5} {5}
-set_instance_parameter_value xcvr_rx_core {LID6} {6}
-set_instance_parameter_value xcvr_rx_core {LID7} {7}
-set_instance_parameter_value xcvr_rx_core {JESDV} {1}
-set_instance_parameter_value xcvr_rx_core {RES1} {0}
-set_instance_parameter_value xcvr_rx_core {RES2} {0}
-set_instance_parameter_value xcvr_rx_core {TEST_COMPONENTS_EN} {0}
-set_instance_parameter_value xcvr_rx_core {TERMINATE_RECONFIG_EN} {0}
-set_instance_parameter_value xcvr_rx_core {ED_GENERIC_5SERIES} {No}
-set_instance_parameter_value xcvr_rx_core {ED_GENERIC_A10} {No}
-set_instance_parameter_value xcvr_rx_core {ED_FILESET_SIM} {0}
-set_instance_parameter_value xcvr_rx_core {ED_FILESET_SYNTH} {0}
-set_instance_parameter_value xcvr_rx_core {ED_HDL_FORMAT_SIM} {VERILOG}
-set_instance_parameter_value xcvr_rx_core {ED_HDL_FORMAT_SYNTH} {VERILOG}
-set_instance_parameter_value xcvr_rx_core {ED_DEV_KIT} {NONE}
+# ad9371_rx_os-xcvr
 
-add_instance axi_os_jesd_xcvr axi_jesd_xcvr 1.0
-set_instance_parameter_value axi_os_jesd_xcvr {ID} {1}
-set_instance_parameter_value axi_os_jesd_xcvr {DEVICE_TYPE} {0}
-set_instance_parameter_value axi_os_jesd_xcvr {TX_NUM_OF_LANES} {0}
-set_instance_parameter_value axi_os_jesd_xcvr {RX_NUM_OF_LANES} {2}
+add_instance axi_ad9371_rx_os_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_ad9371_rx_os_xcvr {ID} {2}
+set_instance_parameter_value axi_ad9371_rx_os_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value axi_ad9371_rx_os_xcvr {NUM_OF_LANES} {2}
+add_connection sys_clk.clk axi_ad9371_rx_os_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9371_rx_os_xcvr.s_axi_reset
+add_connection axi_ad9371_rx_os_xcvr.if_up_rst avl_ad9371_rx_os_xcvr.rst
+add_connection avl_ad9371_rx_os_xcvr.ready axi_ad9371_rx_os_xcvr.ready
+add_connection axi_ad9371_rx_os_xcvr.core_pll_locked avl_ad9371_rx_os_xcvr.core_pll_locked
 
-add_instance xcvr_rx_os_rst_cntrl altera_xcvr_reset_control 16.0
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {CHANNELS} {2}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {PLLS} {1}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYS_CLK_IN_MHZ} {100}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYNCHRONIZE_RESET} {1}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {REDUCED_SIM_TIME} {1}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_split_interfaces} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_PLL_ENABLE} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_PLL_POWERDOWN} {1000}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_ENABLE} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_PER_CHANNEL} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_tx_auto_reset} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_TX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_TX_DIGITALRESET} {70000}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_PLL_LOCK_HYST} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_pll_cal_busy} {1}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {RX_ENABLE} {1}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {RX_PER_CHANNEL} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_rx_auto_reset} {0}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_RX_ANALOGRESET} {70000}
-set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_RX_DIGITALRESET} {4000}
-
-add_instance xcvr_rx_os_core altera_jesd204 16.0
-set_instance_parameter_value xcvr_rx_os_core {wrapper_opt} {base_phy}
-set_instance_parameter_value xcvr_rx_os_core {sdc_constraint} {1.0}
-set_instance_parameter_value xcvr_rx_os_core {DATA_PATH} {RX}
-set_instance_parameter_value xcvr_rx_os_core {SUBCLASSV} {1}
-set_instance_parameter_value xcvr_rx_os_core {lane_rate} {4915.2}
-set_instance_parameter_value xcvr_rx_os_core {PCS_CONFIG} {JESD_PCS_CFG1}
-set_instance_parameter_value xcvr_rx_os_core {pll_type} {CMU}
-set_instance_parameter_value xcvr_rx_os_core {bonded_mode} {non_bonded}
-set_instance_parameter_value xcvr_rx_os_core {REFCLK_FREQ} {122.88}
-set_instance_parameter_value xcvr_rx_os_core {bitrev_en} {0}
-set_instance_parameter_value xcvr_rx_os_core {pll_reconfig_enable} {0}
-set_instance_parameter_value xcvr_rx_os_core {rcfg_jtag_enable} {0}
-set_instance_parameter_value xcvr_rx_os_core {set_capability_reg_enable} {0}
-set_instance_parameter_value xcvr_rx_os_core {set_user_identifier} {0}
-set_instance_parameter_value xcvr_rx_os_core {set_csr_soft_logic_enable} {0}
-set_instance_parameter_value xcvr_rx_os_core {set_prbs_soft_logic_enable} {0}
-set_instance_parameter_value xcvr_rx_os_core {L} {2}
-set_instance_parameter_value xcvr_rx_os_core {M} {2}
-set_instance_parameter_value xcvr_rx_os_core {GUI_EN_CFG_F} {0}
-set_instance_parameter_value xcvr_rx_os_core {GUI_CFG_F} {4}
-set_instance_parameter_value xcvr_rx_os_core {N} {16}
-set_instance_parameter_value xcvr_rx_os_core {N_PRIME} {16}
-set_instance_parameter_value xcvr_rx_os_core {S} {1}
-set_instance_parameter_value xcvr_rx_os_core {K} {16}
-set_instance_parameter_value xcvr_rx_os_core {SCR} {1}
-set_instance_parameter_value xcvr_rx_os_core {CS} {0}
-set_instance_parameter_value xcvr_rx_os_core {CF} {0}
-set_instance_parameter_value xcvr_rx_os_core {HD} {0}
-set_instance_parameter_value xcvr_rx_os_core {ECC_EN} {0}
-set_instance_parameter_value xcvr_rx_os_core {DLB_TEST} {0}
-set_instance_parameter_value xcvr_rx_os_core {PHADJ} {0}
-set_instance_parameter_value xcvr_rx_os_core {ADJCNT} {0}
-set_instance_parameter_value xcvr_rx_os_core {ADJDIR} {0}
-set_instance_parameter_value xcvr_rx_os_core {OPTIMIZE} {0}
-set_instance_parameter_value xcvr_rx_os_core {DID} {0}
-set_instance_parameter_value xcvr_rx_os_core {BID} {0}
-set_instance_parameter_value xcvr_rx_os_core {LID0} {0}
-set_instance_parameter_value xcvr_rx_os_core {LID1} {1}
-set_instance_parameter_value xcvr_rx_os_core {LID2} {2}
-set_instance_parameter_value xcvr_rx_os_core {LID3} {3}
-set_instance_parameter_value xcvr_rx_os_core {LID4} {4}
-set_instance_parameter_value xcvr_rx_os_core {LID5} {5}
-set_instance_parameter_value xcvr_rx_os_core {LID6} {6}
-set_instance_parameter_value xcvr_rx_os_core {LID7} {7}
-set_instance_parameter_value xcvr_rx_os_core {JESDV} {1}
-set_instance_parameter_value xcvr_rx_os_core {RES1} {0}
-set_instance_parameter_value xcvr_rx_os_core {RES2} {0}
-set_instance_parameter_value xcvr_rx_os_core {TEST_COMPONENTS_EN} {0}
-set_instance_parameter_value xcvr_rx_os_core {TERMINATE_RECONFIG_EN} {0}
-set_instance_parameter_value xcvr_rx_os_core {ED_GENERIC_5SERIES} {No}
-set_instance_parameter_value xcvr_rx_os_core {ED_GENERIC_A10} {No}
-set_instance_parameter_value xcvr_rx_os_core {ED_FILESET_SIM} {0}
-set_instance_parameter_value xcvr_rx_os_core {ED_FILESET_SYNTH} {0}
-set_instance_parameter_value xcvr_rx_os_core {ED_HDL_FORMAT_SIM} {VERILOG}
-set_instance_parameter_value xcvr_rx_os_core {ED_HDL_FORMAT_SYNTH} {VERILOG}
-set_instance_parameter_value xcvr_rx_os_core {ED_DEV_KIT} {NONE}
+# ad9371-core
 
 add_instance axi_ad9371 axi_ad9371 1.0
-set_instance_parameter_value axi_ad9371 {ID} {0}
-set_instance_parameter_value axi_ad9371 {DAC_DATAPATH_DISABLE} {0}
-set_instance_parameter_value axi_ad9371 {ADC_DATAPATH_DISABLE} {0}
-
-add_instance adc_pack util_cpack 1.0
-set_instance_parameter_value adc_pack {CHANNEL_DATA_WIDTH} {16}
-set_instance_parameter_value adc_pack {NUM_OF_CHANNELS} {4}
-
-add_instance dac_upack util_upack 1.0
-set_instance_parameter_value dac_upack {CHANNEL_DATA_WIDTH} {32}
-set_instance_parameter_value dac_upack {NUM_OF_CHANNELS} {4}
-
-add_instance adc_os_pack util_cpack 1.0
-set_instance_parameter_value adc_os_pack {CHANNEL_DATA_WIDTH} {32}
-set_instance_parameter_value adc_os_pack {NUM_OF_CHANNELS} {2}
-
-add_instance rx_adcfifo util_adcfifo 1.0
-set_instance_parameter_value rx_adcfifo {ADC_DATA_WIDTH} {64}
-set_instance_parameter_value rx_adcfifo {DMA_DATA_WIDTH} {64}
-set_instance_parameter_value rx_adcfifo {DMA_READY_ENABLE} {1}
-set_instance_parameter_value rx_adcfifo {DMA_ADDRESS_WIDTH} {16}
-
-add_instance rx_os_adcfifo util_adcfifo 1.0
-set_instance_parameter_value rx_os_adcfifo {ADC_DATA_WIDTH} {64}
-set_instance_parameter_value rx_os_adcfifo {DMA_DATA_WIDTH} {64}
-set_instance_parameter_value rx_os_adcfifo {DMA_READY_ENABLE} {1}
-set_instance_parameter_value rx_os_adcfifo {DMA_ADDRESS_WIDTH} {16}
-
-add_instance axi_adc_dma axi_dmac 1.0
-set_instance_parameter_value axi_adc_dma {ID} {0}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {128}
-set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
-set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
-set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
-set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {0}
-set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
-set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {1}
-set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {16}
-
-add_instance axi_os_adc_dma axi_dmac 1.0
-set_instance_parameter_value axi_os_adc_dma {ID} {0}
-set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {128}
-set_instance_parameter_value axi_os_adc_dma {DMA_LENGTH_WIDTH} {24}
-set_instance_parameter_value axi_os_adc_dma {DMA_2D_TRANSFER} {0}
-set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_REQ_SRC} {1}
-set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_SRC_DEST} {1}
-set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_DEST_REQ} {1}
-set_instance_parameter_value axi_os_adc_dma {AXI_SLICE_DEST} {0}
-set_instance_parameter_value axi_os_adc_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_os_adc_dma {SYNC_TRANSFER_START} {0}
-set_instance_parameter_value axi_os_adc_dma {CYCLIC} {0}
-set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_SRC} {1}
-set_instance_parameter_value axi_os_adc_dma {FIFO_SIZE} {16}
-
-add_instance axi_dac_dma axi_dmac 1.0
-set_instance_parameter_value axi_dac_dma {ID} {0}
-set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {128}
-set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {128}
-set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
-set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1}
-set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
-set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
-set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
-set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
-set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
-set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {16}
-
-add_instance ad9371_gpio altera_avalon_pio 16.0
-set_instance_parameter_value ad9371_gpio {bitClearingEdgeCapReg} {0}
-set_instance_parameter_value ad9371_gpio {bitModifyingOutReg} {1}
-set_instance_parameter_value ad9371_gpio {captureEdge} {0}
-set_instance_parameter_value ad9371_gpio {direction} {Bidir}
-set_instance_parameter_value ad9371_gpio {edgeType} {RISING}
-set_instance_parameter_value ad9371_gpio {generateIRQ} {0}
-set_instance_parameter_value ad9371_gpio {irqType} {LEVEL}
-set_instance_parameter_value ad9371_gpio {resetValue} {0.0}
-set_instance_parameter_value ad9371_gpio {simDoTestBenchWiring} {0}
-set_instance_parameter_value ad9371_gpio {simDrivenValue} {0.0}
-set_instance_parameter_value ad9371_gpio {width} {19}
-
-# connections
-
-add_connection axi_jesd_xcvr.if_tx_ip_avl xcvr_tx_core.jesd204_tx_link
-
-add_connection xcvr_rx_core.jesd204_rx_link axi_jesd_xcvr.if_rx_ip_avl
-
-add_connection xcvr_rx_os_core.jesd204_rx_link axi_os_jesd_xcvr.if_rx_ip_avl
-
-add_connection sys_clk.clk xcvr_tx_rst_cntrl.clock
-add_connection sys_clk.clk xcvr_rx_rst_cntrl.clock
-add_connection sys_clk.clk xcvr_rx_os_rst_cntrl.clock
-add_connection sys_clk.clk xcvr_rx_core.jesd204_rx_avs_clk
-add_connection sys_clk.clk xcvr_rx_os_core.jesd204_rx_avs_clk
-add_connection sys_clk.clk xcvr_tx_core.jesd204_tx_avs_clk
-add_connection sys_clk.clk xcvr_pll_reconfig.mgmt_clk
-#add_connection sys_clk.clk xcvr_rx_core.reconfig_clk
-#add_connection sys_clk.clk xcvr_rx_os_core.reconfig_clk
-add_connection sys_clk.clk xcvr_tx_core.reconfig_clk
-add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0
-add_connection sys_clk.clk axi_adc_dma.s_axi_clock
-add_connection sys_clk.clk axi_dac_dma.s_axi_clock
-add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
-add_connection sys_clk.clk axi_os_jesd_xcvr.s_axi_clock
+add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371.if_dac_clk
+add_connection axi_ad9371.if_dac_tx_data avl_ad9371_tx_xcvr.ip_data
+add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371.if_adc_clk
+add_connection avl_ad9371_rx_xcvr.ip_sof axi_ad9371.if_adc_rx_sof
+add_connection avl_ad9371_rx_xcvr.ip_data axi_ad9371.if_adc_rx_data
+add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371.if_adc_os_clk
+add_connection avl_ad9371_rx_os_xcvr.ip_sof axi_ad9371.if_adc_rx_os_sof
+add_connection avl_ad9371_rx_os_xcvr.ip_data axi_ad9371.if_adc_rx_os_data
 add_connection sys_clk.clk axi_ad9371.s_axi_clock
-add_connection sys_clk.clk axi_os_adc_dma.s_axi_clock
-add_connection sys_clk.clk ad9371_gpio.clk
-
-add_connection sys_clk.clk_reset xcvr_rx_core.jesd204_rx_avs_rst_n
-add_connection sys_clk.clk_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n
-add_connection sys_clk.clk_reset xcvr_tx_core.jesd204_tx_avs_rst_n
-add_connection sys_clk.clk_reset xcvr_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
-add_connection sys_clk.clk_reset xcvr_pll.reset
-add_connection sys_clk.clk_reset xcvr_rx_rst_cntrl.reset
-add_connection sys_clk.clk_reset xcvr_tx_rst_cntrl.reset
-add_connection sys_clk.clk_reset xcvr_rx_os_rst_cntrl.reset
-#add_connection sys_clk.clk_reset xcvr_rx_core.reconfig_reset
-#add_connection sys_clk.clk_reset xcvr_rx_os_core.reconfig_reset
-add_connection sys_clk.clk_reset xcvr_tx_core.reconfig_reset
-add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
-add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
-add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
-add_connection sys_clk.clk_reset axi_os_jesd_xcvr.s_axi_reset
 add_connection sys_clk.clk_reset axi_ad9371.s_axi_reset
-add_connection sys_clk.clk_reset axi_os_adc_dma.s_axi_reset
-add_connection sys_clk.clk_reset ad9371_gpio.reset
-add_connection sys_clk.clk_reset rx_adcfifo.if_adc_rst
-add_connection sys_clk.clk_reset rx_os_adcfifo.if_adc_rst
 
-if { $system_type=="a10soc" } {
-  add_connection sys_rst.out_reset xcvr_rx_core.jesd204_rx_avs_rst_n
-  add_connection sys_rst.out_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n
-  add_connection sys_rst.out_reset xcvr_tx_core.jesd204_tx_avs_rst_n
-  add_connection sys_rst.out_reset xcvr_pll_reconfig.mgmt_reset
-  add_connection sys_rst.out_reset xcvr_tx_lane_pll.reconfig_reset0
-  add_connection sys_rst.out_reset xcvr_pll.reset
-  add_connection sys_rst.out_reset xcvr_rx_rst_cntrl.reset
-  add_connection sys_rst.out_reset xcvr_tx_rst_cntrl.reset
-  add_connection sys_rst.out_reset xcvr_rx_os_rst_cntrl.reset
-  #add_connection sys_rst.out_reset xcvr_rx_core.reconfig_reset
-  #add_connection sys_rst.out_reset xcvr_rx_os_core.reconfig_reset
-  add_connection sys_rst.out_reset xcvr_tx_core.reconfig_reset
-  add_connection sys_rst.out_reset axi_adc_dma.s_axi_reset
-  add_connection sys_rst.out_reset axi_dac_dma.s_axi_reset
-  add_connection sys_rst.out_reset axi_jesd_xcvr.s_axi_reset
-  add_connection sys_rst.out_reset axi_os_jesd_xcvr.s_axi_reset
-  add_connection sys_rst.out_reset axi_ad9371.s_axi_reset
-  add_connection sys_rst.out_reset axi_os_adc_dma.s_axi_reset
-  add_connection sys_rst.out_reset ad9371_gpio.reset
-  add_connection sys_rst.out_reset rx_adcfifo.if_adc_rst
-  add_connection sys_rst.out_reset rx_os_adcfifo.if_adc_rst
-}
+# pack(s) & unpack(s)
 
-add_connection xcvr_pll.outclk0 axi_ad9371.if_dac_clk
-add_connection xcvr_pll.outclk0 dac_upack.if_dac_clk
-add_connection xcvr_pll.outclk0 axi_dac_dma.if_fifo_rd_clk
-add_connection xcvr_pll.outclk0 axi_jesd_xcvr.if_tx_clk
-add_connection xcvr_pll.outclk0 xcvr_tx_core.txlink_clk
-add_connection xcvr_pll.outclk1 adc_pack.if_adc_clk
-add_connection xcvr_pll.outclk1 axi_ad9371.if_adc_clk
-add_connection xcvr_pll.outclk1 axi_jesd_xcvr.if_rx_clk
-add_connection xcvr_pll.outclk1 xcvr_rx_core.rxlink_clk
-add_connection xcvr_pll.outclk1 rx_adcfifo.if_adc_clk
-add_connection xcvr_pll.outclk1 rx_adcfifo.if_dma_clk
-add_connection xcvr_pll.outclk1 axi_adc_dma.if_s_axis_aclk
-add_connection xcvr_pll.outclk2 adc_os_pack.if_adc_clk
-add_connection xcvr_pll.outclk2 axi_ad9371.if_adc_os_clk
-add_connection xcvr_pll.outclk2 axi_os_jesd_xcvr.if_rx_clk
-add_connection xcvr_pll.outclk2 xcvr_rx_os_core.rxlink_clk
-add_connection xcvr_pll.outclk2 rx_os_adcfifo.if_adc_clk
-add_connection xcvr_pll.outclk2 rx_os_adcfifo.if_dma_clk
-add_connection xcvr_pll.outclk2 axi_os_adc_dma.if_s_axis_aclk
+add_instance axi_ad9371_tx_upack util_upack 1.0
+set_instance_parameter_value axi_ad9371_tx_upack {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value axi_ad9371_tx_upack {CHANNEL_DATA_WIDTH} {32}
+add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_upack.if_dac_clk
+add_connection axi_ad9371_tx_upack.dac_ch_0 axi_ad9371.dac_ch_0
+add_connection axi_ad9371_tx_upack.dac_ch_1 axi_ad9371.dac_ch_1
+add_connection axi_ad9371_tx_upack.dac_ch_2 axi_ad9371.dac_ch_2
+add_connection axi_ad9371_tx_upack.dac_ch_3 axi_ad9371.dac_ch_3
 
-# NIOS
-if { $system_type=="nios" } {
-  add_connection sys_ddr3_cntrl.emif_usr_clk axi_adc_dma.m_dest_axi_clock
-  add_connection sys_ddr3_cntrl.emif_usr_clk axi_os_adc_dma.m_dest_axi_clock
-  add_connection sys_ddr3_cntrl.emif_usr_clk axi_dac_dma.m_src_axi_clock
-  add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_adc_dma.m_dest_axi_reset
-  add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_os_adc_dma.m_dest_axi_reset
-  add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_dac_dma.m_src_axi_reset
-}
+add_instance axi_ad9371_rx_cpack util_cpack 1.0
+set_instance_parameter_value axi_ad9371_rx_cpack {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value axi_ad9371_rx_cpack {CHANNEL_DATA_WIDTH} {16}
+add_connection sys_clk.clk_reset axi_ad9371_rx_cpack.if_adc_rst
+add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_cpack.if_adc_clk
+add_connection axi_ad9371.adc_ch_0 axi_ad9371_rx_cpack.adc_ch_0
+add_connection axi_ad9371.adc_ch_1 axi_ad9371_rx_cpack.adc_ch_1
+add_connection axi_ad9371.adc_ch_2 axi_ad9371_rx_cpack.adc_ch_2
+add_connection axi_ad9371.adc_ch_3 axi_ad9371_rx_cpack.adc_ch_3
 
-# SOC
-if { $system_type=="a10soc" } {
-  add_connection arria10_hps_0.h2f_user0_clock axi_adc_dma.m_dest_axi_clock
-  add_connection arria10_hps_0.h2f_user0_clock axi_os_adc_dma.m_dest_axi_clock
-  add_connection arria10_hps_0.h2f_user0_clock axi_dac_dma.m_src_axi_clock
-  add_connection sys_rst.out_reset axi_adc_dma.m_dest_axi_reset
-  add_connection sys_rst.out_reset axi_os_adc_dma.m_dest_axi_reset
-  add_connection sys_rst.out_reset axi_dac_dma.m_src_axi_reset
-}
+add_instance axi_ad9371_rx_os_cpack util_cpack 1.0
+set_instance_parameter_value axi_ad9371_rx_os_cpack {NUM_OF_CHANNELS} {2}
+set_instance_parameter_value axi_ad9371_rx_os_cpack {CHANNEL_DATA_WIDTH} {32}
+add_connection sys_clk.clk_reset axi_ad9371_rx_os_cpack.if_adc_rst
+add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_cpack.if_adc_clk
+add_connection axi_ad9371.adc_os_ch_0 axi_ad9371_rx_os_cpack.adc_ch_0
+add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1
 
-add_connection adc_pack.adc_ch_0 axi_ad9371.adc_ch_0
-add_connection adc_pack.adc_ch_1 axi_ad9371.adc_ch_1
-add_connection adc_pack.adc_ch_2 axi_ad9371.adc_ch_2
-add_connection adc_pack.adc_ch_3 axi_ad9371.adc_ch_3
+# dac & adc fifos
 
-add_connection adc_pack.if_adc_valid rx_adcfifo.if_adc_wr
-add_connection adc_pack.if_adc_data rx_adcfifo.if_adc_wdata
+add_instance axi_ad9371_rx_fifo util_adcfifo 1.0
+set_instance_parameter_value axi_ad9371_rx_fifo {ADC_DATA_WIDTH} {64}
+set_instance_parameter_value axi_ad9371_rx_fifo {DMA_DATA_WIDTH} {64}
+set_instance_parameter_value axi_ad9371_rx_fifo {DMA_READY_ENABLE} {1}
+set_instance_parameter_value axi_ad9371_rx_fifo {DMA_ADDRESS_WIDTH} {16}
+add_connection sys_clk.clk_reset axi_ad9371_rx_fifo.if_adc_rst
+add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_fifo.if_adc_clk
+add_connection axi_ad9371_rx_cpack.if_adc_valid axi_ad9371_rx_fifo.if_adc_wr
+add_connection axi_ad9371_rx_cpack.if_adc_data axi_ad9371_rx_fifo.if_adc_wdata
+add_connection axi_ad9371_rx_fifo.if_adc_wovf axi_ad9371.if_adc_dovf
 
-add_connection rx_adcfifo.if_dma_wr axi_adc_dma.if_s_axis_valid
-add_connection rx_adcfifo.if_dma_wdata axi_adc_dma.if_s_axis_data
-add_connection rx_adcfifo.if_dma_wready axi_adc_dma.if_s_axis_ready
-add_connection rx_adcfifo.if_dma_xfer_req axi_adc_dma.if_s_axis_xfer_req
-add_connection rx_adcfifo.if_adc_wovf axi_ad9371.if_adc_dovf
+add_instance axi_ad9371_rx_os_fifo util_adcfifo 1.0
+set_instance_parameter_value axi_ad9371_rx_os_fifo {ADC_DATA_WIDTH} {64}
+set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_DATA_WIDTH} {64}
+set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_READY_ENABLE} {1}
+set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_ADDRESS_WIDTH} {16}
 
-add_connection adc_os_pack.adc_ch_0 axi_ad9371.adc_os_ch_0
-add_connection adc_os_pack.adc_ch_1 axi_ad9371.adc_os_ch_1
+add_connection sys_clk.clk_reset axi_ad9371_rx_os_fifo.if_adc_rst
+add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_fifo.if_adc_clk
+add_connection axi_ad9371_rx_os_cpack.if_adc_valid axi_ad9371_rx_os_fifo.if_adc_wr
+add_connection axi_ad9371_rx_os_cpack.if_adc_data axi_ad9371_rx_os_fifo.if_adc_wdata
+add_connection axi_ad9371_rx_os_fifo.if_adc_wovf axi_ad9371.if_adc_dovf
 
-add_connection adc_os_pack.if_adc_valid rx_os_adcfifo.if_adc_wr
-add_connection adc_os_pack.if_adc_data rx_os_adcfifo.if_adc_wdata
+# dac & adc dma
 
-add_connection rx_os_adcfifo.if_dma_wr axi_os_adc_dma.if_s_axis_valid
-add_connection rx_os_adcfifo.if_dma_wdata axi_os_adc_dma.if_s_axis_data
-add_connection rx_os_adcfifo.if_dma_wready axi_os_adc_dma.if_s_axis_ready
-add_connection rx_os_adcfifo.if_dma_xfer_req axi_os_adc_dma.if_s_axis_xfer_req
-add_connection rx_os_adcfifo.if_adc_wovf axi_ad9371.if_adc_dovf
+add_instance axi_ad9371_tx_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9371_tx_dma {ID} {0}
+set_instance_parameter_value axi_ad9371_tx_dma {DMA_DATA_WIDTH_SRC} {128}
+set_instance_parameter_value axi_ad9371_tx_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9371_tx_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9371_tx_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9371_tx_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_ad9371_tx_dma {CYCLIC} {1}
+set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_SRC} {0}
+set_instance_parameter_value axi_ad9371_tx_dma {FIFO_SIZE} {16}
+add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_dma.if_fifo_rd_clk
+add_connection axi_ad9371_tx_upack.if_dac_valid axi_ad9371_tx_dma.if_fifo_rd_en
+add_connection axi_ad9371_tx_dma.if_fifo_rd_dout axi_ad9371_tx_upack.if_dac_data
+add_connection axi_ad9371_tx_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf
+add_connection sys_clk.clk axi_ad9371_tx_dma.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9371_tx_dma.s_axi_reset
+add_connection sys_dma_clk.clk axi_ad9371_tx_dma.m_src_axi_clock
+add_connection sys_dma_clk.clk_reset axi_ad9371_tx_dma.m_src_axi_reset
 
-add_connection dac_upack.dac_ch_0 axi_ad9371.dac_ch_0
-add_connection dac_upack.dac_ch_1 axi_ad9371.dac_ch_1
-add_connection dac_upack.dac_ch_2 axi_ad9371.dac_ch_2
-add_connection dac_upack.dac_ch_3 axi_ad9371.dac_ch_3
+add_instance axi_ad9371_rx_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9371_rx_dma {ID} {0}
+set_instance_parameter_value axi_ad9371_rx_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_ad9371_rx_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9371_rx_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9371_rx_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9371_rx_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_ad9371_rx_dma {CYCLIC} {0}
+set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_SRC} {1}
+set_instance_parameter_value axi_ad9371_rx_dma {FIFO_SIZE} {16}
+add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_fifo.if_dma_clk
+add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_dma.if_s_axis_aclk
+add_connection axi_ad9371_rx_fifo.if_dma_wr axi_ad9371_rx_dma.if_s_axis_valid
+add_connection axi_ad9371_rx_fifo.if_dma_wdata axi_ad9371_rx_dma.if_s_axis_data
+add_connection axi_ad9371_rx_dma.if_s_axis_ready axi_ad9371_rx_fifo.if_dma_wready
+add_connection axi_ad9371_rx_dma.if_s_axis_xfer_req axi_ad9371_rx_fifo.if_dma_xfer_req
+add_connection sys_clk.clk axi_ad9371_rx_dma.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9371_rx_dma.s_axi_reset
+add_connection sys_dma_clk.clk axi_ad9371_rx_dma.m_dest_axi_clock
+add_connection sys_dma_clk.clk_reset axi_ad9371_rx_dma.m_dest_axi_reset
 
-add_connection xcvr_rx_os_core.alldev_lane_aligned xcvr_rx_os_core.dev_lane_aligned
-add_connection xcvr_rx_core.dev_lane_aligned xcvr_rx_core.alldev_lane_aligned
-add_connection xcvr_rx_core.dev_sync_n axi_jesd_xcvr.if_rx_ip_sync
-add_connection xcvr_tx_core.dev_sync_n xcvr_tx_core.mdev_sync_n
+add_instance axi_ad9371_rx_os_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9371_rx_os_dma {ID} {0}
+set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9371_rx_os_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_ad9371_rx_os_dma {CYCLIC} {0}
+set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_SRC} {1}
+set_instance_parameter_value axi_ad9371_rx_os_dma {FIFO_SIZE} {16}
+add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_fifo.if_dma_clk
+add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_dma.if_s_axis_aclk
+add_connection axi_ad9371_rx_os_fifo.if_dma_wr axi_ad9371_rx_os_dma.if_s_axis_valid
+add_connection axi_ad9371_rx_os_fifo.if_dma_wdata axi_ad9371_rx_os_dma.if_s_axis_data
+add_connection axi_ad9371_rx_os_dma.if_s_axis_ready axi_ad9371_rx_os_fifo.if_dma_wready
+add_connection axi_ad9371_rx_os_dma.if_s_axis_xfer_req axi_ad9371_rx_os_fifo.if_dma_xfer_req
+add_connection sys_clk.clk axi_ad9371_rx_os_dma.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9371_rx_os_dma.s_axi_reset
+add_connection sys_dma_clk.clk axi_ad9371_rx_os_dma.m_dest_axi_clock
+add_connection sys_dma_clk.clk_reset axi_ad9371_rx_os_dma.m_dest_axi_reset
 
-add_connection axi_ad9371.if_adc_rx_data axi_jesd_xcvr.if_rx_data
-add_connection axi_ad9371.if_adc_rx_os_data axi_os_jesd_xcvr.if_rx_data
-add_connection dac_upack.if_dac_data axi_dac_dma.if_fifo_rd_dout
-add_connection axi_dac_dma.if_fifo_rd_en dac_upack.if_dac_valid
-add_connection axi_dac_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf
-add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_rx_core.sof
-add_connection axi_os_jesd_xcvr.if_rx_ip_sync xcvr_rx_os_core.dev_sync_n
-add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_rx_core.sysref
-add_connection axi_jesd_xcvr.if_rx_ready xcvr_rx_rst_cntrl.rx_ready
-add_connection axi_jesd_xcvr.if_tx_data axi_ad9371.if_dac_tx_data
-add_connection axi_jesd_xcvr.if_tx_ip_sync xcvr_tx_core.sync_n
-add_connection axi_jesd_xcvr.if_tx_ip_sysref xcvr_tx_core.sysref
-add_connection xcvr_tx_lane_pll.pll_cal_busy xcvr_tx_rst_cntrl.pll_cal_busy
-add_connection xcvr_tx_lane_pll.pll_locked xcvr_tx_rst_cntrl.pll_locked
-add_connection xcvr_tx_lane_pll.pll_powerdown xcvr_tx_rst_cntrl.pll_powerdown
-add_connection xcvr_pll_reconfig.reconfig_from_pll xcvr_pll.reconfig_from_pll
-add_connection xcvr_pll_reconfig.reconfig_to_pll xcvr_pll.reconfig_to_pll
-add_connection xcvr_rx_core.rx_analogreset xcvr_rx_rst_cntrl.rx_analogreset
-add_connection xcvr_rx_os_core.rx_analogreset xcvr_rx_os_rst_cntrl.rx_analogreset
-add_connection xcvr_rx_rst_cntrl.rx_cal_busy xcvr_rx_core.rx_cal_busy
-add_connection xcvr_rx_os_rst_cntrl.rx_cal_busy xcvr_rx_os_core.rx_cal_busy
-add_connection xcvr_rx_rst_cntrl.rx_digitalreset xcvr_rx_core.rx_digitalreset
-add_connection xcvr_rx_os_rst_cntrl.rx_digitalreset xcvr_rx_os_core.rx_digitalreset
-add_connection xcvr_rx_core.rx_islockedtodata xcvr_rx_rst_cntrl.rx_is_lockedtodata
-add_connection xcvr_rx_os_core.rx_islockedtodata xcvr_rx_os_rst_cntrl.rx_is_lockedtodata
-add_connection xcvr_rx_os_rst_cntrl.rx_ready axi_os_jesd_xcvr.if_rx_ready
-add_connection xcvr_rx_os_core.sof axi_os_jesd_xcvr.if_rx_ip_sof
-add_connection xcvr_rx_os_core.sysref axi_os_jesd_xcvr.if_rx_ip_sysref
-add_connection xcvr_tx_core.tx_analogreset xcvr_tx_rst_cntrl.tx_analogreset
-add_connection xcvr_tx_core.tx_cal_busy xcvr_tx_rst_cntrl.tx_cal_busy
-add_connection xcvr_tx_rst_cntrl.tx_digitalreset xcvr_tx_core.tx_digitalreset
-add_connection xcvr_tx_rst_cntrl.tx_ready axi_jesd_xcvr.if_tx_ready
+# ad9371 gpio
 
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch0
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch1
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch2
-add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch3
-add_connection axi_jesd_xcvr.if_rst xcvr_tx_rst_cntrl.reset
-add_connection axi_os_jesd_xcvr.if_rst xcvr_rx_os_rst_cntrl.reset
-add_connection axi_jesd_xcvr.if_rx_rstn adc_pack.if_adc_rst
-add_connection axi_os_jesd_xcvr.if_rx_rstn adc_os_pack.if_adc_rst
-add_connection axi_jesd_xcvr.if_rx_rstn xcvr_rx_core.rxlink_rst_n
-add_connection axi_os_jesd_xcvr.if_rx_rstn xcvr_rx_os_core.rxlink_rst_n
-add_connection axi_jesd_xcvr.if_tx_rstn xcvr_tx_core.txlink_rst_n
+add_instance avl_ad9371_gpio altera_avalon_pio 16.0
+set_instance_parameter_value avl_ad9371_gpio {direction} {Bidir}
+set_instance_parameter_value avl_ad9371_gpio {generateIRQ} {1}
+set_instance_parameter_value avl_ad9371_gpio {width} {19}
+add_connection sys_clk.clk avl_ad9371_gpio.clk
+add_connection sys_clk.clk_reset avl_ad9371_gpio.reset
+add_interface avl_ad9371_gpio conduit end
+set_interface_property avl_ad9371_gpio EXPORT_OF avl_ad9371_gpio.external_connection
 
+# reconfig sharing
 
-add_interface rx_data conduit end
-set_interface_property rx_data EXPORT_OF xcvr_rx_core.rx_serial_data
-add_interface rx_os_data conduit end
-set_interface_property rx_os_data EXPORT_OF xcvr_rx_os_core.rx_serial_data
-add_interface rx_os_sync conduit end
-set_interface_property rx_os_sync EXPORT_OF axi_os_jesd_xcvr.if_rx_sync
-add_interface rx_os_sysref conduit end
-set_interface_property rx_os_sysref EXPORT_OF axi_os_jesd_xcvr.if_rx_ext_sysref_in
-add_interface rx_sync conduit end
-set_interface_property rx_sync EXPORT_OF axi_jesd_xcvr.if_rx_sync
-add_interface rx_sysref conduit end
-set_interface_property rx_sysref EXPORT_OF axi_jesd_xcvr.if_rx_ext_sysref_in
-add_interface tx_data conduit end
-set_interface_property tx_data EXPORT_OF xcvr_tx_core.tx_serial_data
-add_interface tx_sync conduit end
-set_interface_property tx_sync EXPORT_OF axi_jesd_xcvr.if_tx_sync
-add_interface tx_sysref conduit end
-set_interface_property tx_sysref EXPORT_OF axi_jesd_xcvr.if_tx_ext_sysref_in
+add_instance avl_adxcfg_0 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
+add_connection avl_adxcfg_0.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_0
+add_connection avl_adxcfg_0.rcfg_m1 avl_ad9371_rx_xcvr.phy_reconfig_0
 
-add_interface xcvr_ref_clk clock sink
-set_interface_property xcvr_ref_clk EXPORT_OF xcvr_ref_clk.in_clk
+add_instance avl_adxcfg_1 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
+add_connection avl_adxcfg_1.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_1
+add_connection avl_adxcfg_1.rcfg_m1 avl_ad9371_rx_xcvr.phy_reconfig_1
 
-add_connection xcvr_ref_clk.out_clk xcvr_pll.refclk
-add_connection xcvr_ref_clk.out_clk xcvr_rx_core.pll_ref_clk
-add_connection xcvr_ref_clk.out_clk xcvr_rx_os_core.pll_ref_clk
-add_connection xcvr_ref_clk.out_clk xcvr_tx_lane_pll.pll_refclk0
+add_instance avl_adxcfg_2 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
+add_connection avl_adxcfg_2.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_2
+add_connection avl_adxcfg_2.rcfg_m1 avl_ad9371_rx_os_xcvr.phy_reconfig_0
 
-add_interface ad9371_gpio conduit end
-set_interface_property ad9371_gpio EXPORT_OF ad9371_gpio.external_connection
+add_instance avl_adxcfg_3 avl_adxcfg 1.0
+add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
+add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
+add_connection avl_adxcfg_3.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_3
+add_connection avl_adxcfg_3.rcfg_m1 avl_ad9371_rx_os_xcvr.phy_reconfig_1
 
 # addresses
 
-# NIOS
-if { $system_type=="nios" } {
-  add_connection sys_cpu.data_master xcvr_pll_reconfig.mgmt_avalon_slave
-  add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
-  add_connection sys_cpu.data_master axi_adc_dma.s_axi
-  add_connection sys_cpu.data_master axi_dac_dma.s_axi
-  add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
-  add_connection sys_cpu.data_master axi_os_jesd_xcvr.s_axi
-  add_connection sys_cpu.data_master axi_ad9371.s_axi
-  add_connection sys_cpu.data_master axi_os_adc_dma.s_axi
-  #add_connection sys_cpu.data_master xcvr_rx_core.reconfig_avmm
-  add_connection sys_cpu.data_master xcvr_rx_core.jesd204_rx_avs
-  #add_connection sys_cpu.data_master xcvr_rx_os_core.reconfig_avmm
-  add_connection sys_cpu.data_master xcvr_rx_os_core.jesd204_rx_avs
-  add_connection sys_cpu.data_master xcvr_tx_core.reconfig_avmm
-  add_connection sys_cpu.data_master xcvr_tx_core.jesd204_tx_avs
-  add_connection sys_cpu.data_master ad9371_gpio.s1
+ad_cpu_interconnect 0x00010000 avl_adxcfg_0.rcfg_s0
+ad_cpu_interconnect 0x00011000 avl_adxcfg_0.rcfg_s1
+ad_cpu_interconnect 0x00012000 avl_adxcfg_1.rcfg_s0
+ad_cpu_interconnect 0x00013000 avl_adxcfg_1.rcfg_s1
+ad_cpu_interconnect 0x00014000 avl_adxcfg_2.rcfg_s0
+ad_cpu_interconnect 0x00015000 avl_adxcfg_2.rcfg_s1
+ad_cpu_interconnect 0x00016000 avl_adxcfg_3.rcfg_s0
+ad_cpu_interconnect 0x00017000 avl_adxcfg_3.rcfg_s1
+ad_cpu_interconnect 0x00018000 avl_ad9371_tx_xcvr.core_pll_reconfig
+ad_cpu_interconnect 0x00019000 avl_ad9371_tx_xcvr.ip_reconfig
+ad_cpu_interconnect 0x0001a000 avl_ad9371_tx_xcvr.lane_pll_reconfig
+ad_cpu_interconnect 0x0001b000 avl_ad9371_rx_xcvr.core_pll_reconfig
+ad_cpu_interconnect 0x0001c000 avl_ad9371_rx_xcvr.ip_reconfig
+ad_cpu_interconnect 0x0001d000 avl_ad9371_rx_os_xcvr.core_pll_reconfig
+ad_cpu_interconnect 0x0001e000 avl_ad9371_rx_os_xcvr.ip_reconfig
+ad_cpu_interconnect 0x00020000 axi_ad9371_tx_xcvr.s_axi
+ad_cpu_interconnect 0x00030000 axi_ad9371_rx_xcvr.s_axi
+ad_cpu_interconnect 0x00040000 axi_ad9371_rx_os_xcvr.s_axi
+ad_cpu_interconnect 0x00050000 axi_ad9371_tx_dma.s_axi
+ad_cpu_interconnect 0x00060000 axi_ad9371_rx_dma.s_axi
+ad_cpu_interconnect 0x00070000 axi_ad9371_rx_os_dma.s_axi
+ad_cpu_interconnect 0x00080000 axi_ad9371.s_axi
+ad_cpu_interconnect 0x00090000 avl_ad9371_gpio.s1
 
-  add_connection axi_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
-  add_connection axi_os_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
-  add_connection axi_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
+# dma interconnects
 
-  set_connection_parameter_value sys_cpu.data_master/xcvr_pll_reconfig.mgmt_avalon_slave  baseAddress {0x1003d800}
-  set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0      baseAddress {0x1003c000}
-  set_connection_parameter_value sys_cpu.data_master/axi_adc_dma.s_axi                    baseAddress {0x10034000}
-  set_connection_parameter_value sys_cpu.data_master/axi_dac_dma.s_axi                    baseAddress {0x10010000}
-  set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi                  baseAddress {0x10040000}
-  set_connection_parameter_value sys_cpu.data_master/axi_os_jesd_xcvr.s_axi               baseAddress {0x10020000}
-  set_connection_parameter_value sys_cpu.data_master/axi_ad9371.s_axi                     baseAddress {0x10000000}
-  set_connection_parameter_value sys_cpu.data_master/axi_os_adc_dma.s_axi                 baseAddress {0x10500000}
-  #set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.reconfig_avmm           baseAddress {0x10030000}
-  set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.jesd204_rx_avs          baseAddress {0x1003e400}
-  #set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.reconfig_avmm        baseAddress {0x10130000}
-  set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.jesd204_rx_avs       baseAddress {0x1013e400}
-  set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.reconfig_avmm           baseAddress {0x10050000}
-  set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.jesd204_tx_avs          baseAddress {0x1005e400}
-  set_connection_parameter_value sys_cpu.data_master/ad9371_gpio.s1                       baseAddress {0x10060000}
-
-  set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
-  set_connection_parameter_value axi_os_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0      baseAddress {0x00000000}
-  set_connection_parameter_value axi_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0          baseAddress {0x00000000}
-}
-
-# SOC
-if { $system_type=="a10soc" } {
-  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_pll_reconfig.mgmt_avalon_slave
-  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_lane_pll.reconfig_avmm0
-  add_connection arria10_hps_0.h2f_lw_axi_master axi_adc_dma.s_axi
-  add_connection arria10_hps_0.h2f_lw_axi_master axi_dac_dma.s_axi
-  add_connection arria10_hps_0.h2f_lw_axi_master axi_jesd_xcvr.s_axi
-  add_connection arria10_hps_0.h2f_lw_axi_master axi_os_jesd_xcvr.s_axi
-  add_connection arria10_hps_0.h2f_lw_axi_master axi_ad9371.s_axi
-  add_connection arria10_hps_0.h2f_lw_axi_master axi_os_adc_dma.s_axi
-  #add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_core.reconfig_avmm
-  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_core.jesd204_rx_avs
-  #add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_os_core.reconfig_avmm
-  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_os_core.jesd204_rx_avs
-  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.reconfig_avmm
-  add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.jesd204_tx_avs
-  add_connection arria10_hps_0.h2f_lw_axi_master ad9371_gpio.s1
-
-  add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data
-  add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data
-  add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram0_data
-
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/ad9371_gpio.s1 baseAddress {0x00001000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_pll_reconfig.mgmt_avalon_slave baseAddress {0x00010000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_lane_pll.reconfig_avmm0 baseAddress {0x00011000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_jesd_xcvr.s_axi baseAddress {0x00020000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_rx_core.jesd204_rx_avs baseAddress {0x00030000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_jesd_xcvr.s_axi baseAddress {0x00040000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_rx_os_core.jesd204_rx_avs baseAddress {0x00050000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_core.jesd204_tx_avs baseAddress {0x00060000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_core.reconfig_avmm baseAddress {0x00064000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_ad9371.s_axi baseAddress {0x00070000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_dac_dma.s_axi baseAddress {0x00080000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_adc_dma.s_axi baseAddress {0x0090000}
-  set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_adc_dma.s_axi baseAddress {0x000a0000}
-
-  set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
-  set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
-  set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000}
-}
+ad_dma_interconnect axi_ad9371_tx_dma.m_src_axi
+ad_dma_interconnect axi_ad9371_rx_dma.m_dest_axi
+ad_dma_interconnect axi_ad9371_rx_os_dma.m_dest_axi
 
 # interrupts
 
-# NIOS
-if { $system_type=="nios" } {
-  add_connection sys_cpu.irq axi_adc_dma.interrupt_sender
-  add_connection sys_cpu.irq axi_dac_dma.interrupt_sender
-  add_connection sys_cpu.irq axi_os_adc_dma.interrupt_sender
+ad_cpu_interrupt 11 axi_ad9371_tx_dma.interrupt_sender
+ad_cpu_interrupt 12 axi_ad9371_rx_dma.interrupt_sender
+ad_cpu_interrupt 13 axi_ad9371_rx_os_dma.interrupt_sender
+ad_cpu_interrupt 14 avl_ad9371_gpio.irq
 
-  set_connection_parameter_value sys_cpu.irq/axi_adc_dma.interrupt_sender irqNumber {10}
-  set_connection_parameter_value sys_cpu.irq/axi_dac_dma.interrupt_sender irqNumber {11}
-  set_connection_parameter_value sys_cpu.irq/axi_os_adc_dma.interrupt_sender irqNumber {12}
-}
-
-# SOC
-if { $system_type=="a10soc" } {
-  add_connection arria10_hps_0.f2h_irq0 axi_adc_dma.interrupt_sender
-  add_connection arria10_hps_0.f2h_irq0 axi_dac_dma.interrupt_sender
-  add_connection arria10_hps_0.f2h_irq0 axi_os_adc_dma.interrupt_sender
-
-  set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_adc_dma.interrupt_sender irqNumber {10}
-  set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_dac_dma.interrupt_sender irqNumber {11}
-  set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_os_adc_dma.interrupt_sender irqNumber {12}
-}
diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl
index 5df47d810..935e9bc0a 100755
--- a/projects/common/a10soc/a10soc_system_qsys.tcl
+++ b/projects/common/a10soc/a10soc_system_qsys.tcl
@@ -1,3 +1,4 @@
+
 package require qsys
 
 set_module_property NAME {system_bd}
@@ -7,1292 +8,240 @@ set_project_property DEVICE {10AS066N3F40E2SGE2}
 set system_type a10soc
 
 add_instance sys_clk clock_source 16.0
-add_interface sys_rst reset sink
+add_interface sys_clk clock sink
 set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
-set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
+add_interface sys_rstn reset sink
+set_interface_property sys_rstn EXPORT_OF sys_clk.clk_in_reset
 set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
 set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
 set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
 
-add_instance sys_rst altera_reset_bridge 16.0
-set_instance_parameter_value sys_rst {ACTIVE_LOW_RESET} {0}
-set_instance_parameter_value sys_rst {SYNCHRONOUS_EDGES} {deassert}
-set_instance_parameter_value sys_rst {NUM_RESET_OUTPUTS} {1}
-set_instance_parameter_value sys_rst {USE_RESET_REQUEST} {0}
+# hps
+# round-about way - qsys-script doesn't support {*}?
 
-# HPS
-add_instance arria10_hps_0 altera_arria10_hps 16.0
-set_instance_parameter_value arria10_hps_0 {MPU_EVENTS_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {GP_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {DEBUG_APB_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {STM_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {CTI_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {JTAG_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {TEST_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {BOOT_FROM_FPGA_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {BSEL_EN} {0}
-set_instance_parameter_value arria10_hps_0 {BSEL} {1}
-set_instance_parameter_value arria10_hps_0 {F2S_Width} {0}
-set_instance_parameter_value arria10_hps_0 {S2F_Width} {0}
-set_instance_parameter_value arria10_hps_0 {LWH2F_Enable} {1}
-set_instance_parameter_value arria10_hps_0 {RUN_INTERNAL_BUILD_CHECKS} {0}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {6}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {1}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {0}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM2_ENABLED} {0}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM_READY_LATENCY} {0}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM2_DELAY} {4}
-set_instance_parameter_value arria10_hps_0 {F2SDRAM_ADDRESS_WIDTH} {32}
-set_instance_parameter_value arria10_hps_0 {DMA_Enable} {No No No No No No No No}
-set_instance_parameter_value arria10_hps_0 {SECURITY_MODULE_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {EMAC0_SWITCH_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {EMAC1_SWITCH_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {EMAC2_SWITCH_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {F2SINTERRUPT_Enable} {1}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_CTI_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_DMA_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC0_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC1_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC2_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_GPIO_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_HMC_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC0_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC1_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC2_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2C0_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2C1_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_L4TIMER_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_NAND_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_QSPI_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SYSTIMER_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SDMMC_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIM0_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIM1_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIS0_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIS1_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SYSTEMMANAGER_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_UART0_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_UART1_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_USB0_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_USB1_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_WATCHDOG_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {eosc1_clk_mhz} {25.0}
-set_instance_parameter_value arria10_hps_0 {INTERNAL_OSCILLATOR_ENABLE} {60}
-set_instance_parameter_value arria10_hps_0 {F2H_FREE_CLK_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {F2H_FREE_CLK_FREQ} {200}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK} {2.5}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK} {2.5}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK} {2.5}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {MPU_CLK_VCCL} {0}
-set_instance_parameter_value arria10_hps_0 {USE_DEFAULT_MPU_CLK} {0}
-set_instance_parameter_value arria10_hps_0 {CUSTOM_MPU_CLK} {800}
-set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {1}
-set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {175}
-set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_FREQ} {400}
-set_instance_parameter_value arria10_hps_0 {HMC_PLL_REF_CLK} {800}
-set_instance_parameter_value arria10_hps_0 {EMAC_PTP_REF_CLK} {100}
-set_instance_parameter_value arria10_hps_0 {SDMMC_REF_CLK} {200}
-set_instance_parameter_value arria10_hps_0 {GPIO_REF_CLK} {4}
-set_instance_parameter_value arria10_hps_0 {L3_MAIN_FREE_CLK} {400}
-set_instance_parameter_value arria10_hps_0 {L4_SYS_FREE_CLK} {1}
-set_instance_parameter_value arria10_hps_0 {NOCDIV_L4MAINCLK} {0}
-set_instance_parameter_value arria10_hps_0 {NOCDIV_L4MPCLK} {1}
-set_instance_parameter_value arria10_hps_0 {NOCDIV_L4SPCLK} {2}
-set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_ATCLK} {0}
-set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_PDBGCLK} {1}
-set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_TRACECLK} {0}
-set_instance_parameter_value arria10_hps_0 {HPS_DIV_GPIO_FREQ} {125}
-set_instance_parameter_value arria10_hps_0 {EMAC0_CLK} {250}
-set_instance_parameter_value arria10_hps_0 {EMAC1_CLK} {250}
-set_instance_parameter_value arria10_hps_0 {EMAC2_CLK} {250}
-set_instance_parameter_value arria10_hps_0 {DISABLE_PERI_PLL} {0}
-set_instance_parameter_value arria10_hps_0 {OVERIDE_PERI_PLL} {0}
-set_instance_parameter_value arria10_hps_0 {PERI_PLL_MANUAL_VCO_FREQ} {2000}
-set_instance_parameter_value arria10_hps_0 {CLK_MAIN_PLL_SOURCE2} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_PERI_PLL_SOURCE2} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_MPU_SOURCE} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_MPU_CNT} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_NOC_SOURCE} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_NOC_CNT} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_S2F_USER0_SOURCE} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_S2F_USER1_SOURCE} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_HMC_PLL_SOURCE} {0}
-set_instance_parameter_value arria10_hps_0 {CLK_EMAC_PTP_SOURCE} {1}
-set_instance_parameter_value arria10_hps_0 {CLK_GPIO_SOURCE} {1}
-set_instance_parameter_value arria10_hps_0 {CLK_SDMMC_SOURCE} {1}
-set_instance_parameter_value arria10_hps_0 {CLK_EMACA_SOURCE} {1}
-set_instance_parameter_value arria10_hps_0 {CLK_EMACB_SOURCE} {1}
-set_instance_parameter_value arria10_hps_0 {H2F_PENDING_RST_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {H2F_COLD_RST_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {F2H_DBG_RST_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {F2H_WARM_RST_Enable} {0}
-set_instance_parameter_value arria10_hps_0 {F2H_COLD_RST_Enable} {1}
-set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_MAINCLKSEL} {8}
-set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_PERICLKSEL} {8}
-set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_DEBUGCLKSEL} {16}
-set_instance_parameter_value arria10_hps_0 {EMIF_CONDUIT_Enable} {1}
-set_instance_parameter_value arria10_hps_0 {EMIF_BYPASS_CHECK} {0}
-set_instance_parameter_value arria10_hps_0 {EMAC0_PTP} {0}
-set_instance_parameter_value arria10_hps_0 {EMAC1_PTP} {0}
-set_instance_parameter_value arria10_hps_0 {EMAC2_PTP} {0}
-set_instance_parameter_value arria10_hps_0 {EMAC0_PinMuxing} {IO}
-set_instance_parameter_value arria10_hps_0 {EMAC0_Mode} {RGMII_with_MDIO}
-set_instance_parameter_value arria10_hps_0 {EMAC1_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {EMAC1_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {EMAC2_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {EMAC2_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {NAND_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {NAND_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {QSPI_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {QSPI_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {SDMMC_PinMuxing} {IO}
-set_instance_parameter_value arria10_hps_0 {SDMMC_Mode} {8-bit}
-set_instance_parameter_value arria10_hps_0 {USB0_PinMuxing} {IO}
-set_instance_parameter_value arria10_hps_0 {USB0_Mode} {default}
-set_instance_parameter_value arria10_hps_0 {USB1_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {USB1_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {SPIM0_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {SPIM0_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {SPIM1_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {SPIM1_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {SPIS0_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {SPIS0_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {SPIS1_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {SPIS1_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {UART0_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {UART0_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {UART1_PinMuxing} {IO}
-set_instance_parameter_value arria10_hps_0 {UART1_Mode} {No_flow_control}
-set_instance_parameter_value arria10_hps_0 {I2C0_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {I2C0_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {I2C1_PinMuxing} {IO}
-set_instance_parameter_value arria10_hps_0 {I2C1_Mode} {default}
-set_instance_parameter_value arria10_hps_0 {I2CEMAC0_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {I2CEMAC0_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {I2CEMAC1_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {I2CEMAC1_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {I2CEMAC2_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {I2CEMAC2_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {TRACE_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {TRACE_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {CM_PinMuxing} {Unused}
-set_instance_parameter_value arria10_hps_0 {CM_Mode} {N/A}
-set_instance_parameter_value arria10_hps_0 {PLL_CLK0} {Unused}
-set_instance_parameter_value arria10_hps_0 {PLL_CLK1} {Unused}
-set_instance_parameter_value arria10_hps_0 {PLL_CLK2} {Unused}
-set_instance_parameter_value arria10_hps_0 {PLL_CLK3} {Unused}
-set_instance_parameter_value arria10_hps_0 {PLL_CLK4} {Unused}
-set_instance_parameter_value arria10_hps_0 {HPS_IO_Enable} {SDMMC:D0 SDMMC:CMD SDMMC:CCLK SDMMC:D1 SDMMC:D2 SDMMC:D3 NONE NONE SDMMC:D4 SDMMC:D5 SDMMC:D6 SDMMC:D7 UART1:TX UART1:RX USB0:CLK USB0:STP USB0:DIR USB0:DATA0 USB0:DATA1 USB0:NXT USB0:DATA2 USB0:DATA3 USB0:DATA4 USB0:DATA5 USB0:DATA6 USB0:DATA7 EMAC0:TX_CLK EMAC0:TX_CTL EMAC0:RX_CLK EMAC0:RX_CTL EMAC0:TXD0 EMAC0:TXD1 EMAC0:RXD0 EMAC0:RXD1 EMAC0:TXD2 EMAC0:TXD3 EMAC0:RXD2 EMAC0:RXD3 NONE NONE NONE NONE NONE GPIO NONE NONE NONE NONE MDIO0:MDIO MDIO0:MDC I2C1:SDA I2C1:SCL GPIO NONE GPIO GPIO NONE NONE NONE NONE NONE NONE}
+variable  hps_io_list
 
-add_instance emif_a10_hps_0 altera_emif_a10_hps 16.0
-set_instance_parameter_value emif_a10_hps_0 {PROTOCOL_ENUM} {PROTOCOL_DDR4}
-set_instance_parameter_value emif_a10_hps_0 {IS_ED_SLAVE} {0}
-set_instance_parameter_value emif_a10_hps_0 {INTERNAL_TESTING_MODE} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_ADD_EXTRA_CLKS} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_USER_NUM_OF_EXTRA_CLKS} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5} {100.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5} {100.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6} {100.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6} {100.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7} {100.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7} {100.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8} {100.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8} {100.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8} {0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PING_PONG_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_MEM_CLK_FREQ_MHZ} {1066.667}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_DEFAULT_REF_CLK_FREQ} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_REF_CLK_FREQ_MHZ} {133.333}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_REF_CLK_JITTER_PS} {10.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_RATE_ENUM} {RATE_HALF}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_IO_VOLTAGE} {1.5}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_DEFAULT_IO} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_HPS_ENABLE_EARLY_RELEASE} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ADDR0} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ADDR1} {8}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ENABLE_NON_DES} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_OUT_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_RZQ_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PING_PONG_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_REF_CLK_JITTER_PS} {10.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_RATE_ENUM} {RATE_HALF}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_IO_VOLTAGE} {1.2}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_DEFAULT_IO} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_STARTING_VREFIN} {70.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_HPS_ENABLE_EARLY_RELEASE} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_12}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_MODE_ENUM} {OUT_OCT_40_CAL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_12}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_MODE_ENUM} {OUT_OCT_40_CAL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_CMOS_12}
-set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PING_PONG_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_MEM_CLK_FREQ_MHZ} {633.333}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_DEFAULT_REF_CLK_FREQ} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_REF_CLK_FREQ_MHZ} {-1.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_REF_CLK_JITTER_PS} {10.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_RATE_ENUM} {RATE_HALF}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_IO_VOLTAGE} {1.5}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_DEFAULT_IO} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_HPS_ENABLE_EARLY_RELEASE} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_OUT_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_IN_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_RZQ_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PING_PONG_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_MEM_CLK_FREQ_MHZ} {1066.667}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_DEFAULT_REF_CLK_FREQ} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_REF_CLK_FREQ_MHZ} {-1.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_REF_CLK_JITTER_PS} {10.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_RATE_ENUM} {RATE_QUARTER}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_IO_VOLTAGE} {1.2}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_DEFAULT_IO} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_STARTING_VREFIN} {70.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_HPS_ENABLE_EARLY_RELEASE} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_OUT_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_IN_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_RZQ_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PING_PONG_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_MEM_CLK_FREQ_MHZ} {533.333}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_DEFAULT_REF_CLK_FREQ} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_REF_CLK_FREQ_MHZ} {-1.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_REF_CLK_JITTER_PS} {10.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_RATE_ENUM} {RATE_HALF}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_IO_VOLTAGE} {1.8}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_DEFAULT_IO} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_HPS_ENABLE_EARLY_RELEASE} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_OUT_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_IN_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_RZQ_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_CONFIG_ENUM} {CONFIG_PHY_ONLY}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PING_PONG_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_MEM_CLK_FREQ_MHZ} {1066.667}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_DEFAULT_REF_CLK_FREQ} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_REF_CLK_FREQ_MHZ} {-1.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_REF_CLK_JITTER_PS} {10.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_RATE_ENUM} {RATE_QUARTER}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_IO_VOLTAGE} {1.2}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_DEFAULT_IO} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_HPS_ENABLE_EARLY_RELEASE} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_OUT_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_IN_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_RZQ_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PING_PONG_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_MEM_CLK_FREQ_MHZ} {800.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_DEFAULT_REF_CLK_FREQ} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ} {-1.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_REF_CLK_JITTER_PS} {10.0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_RATE_ENUM} {RATE_HALF}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_IO_VOLTAGE} {1.2}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_DEFAULT_IO} {1}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE} {0}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_IN_MODE_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_RZQ_IO_STD_ENUM} {unset}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_FORMAT_ENUM} {MEM_FORMAT_UDIMM}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DQ_WIDTH} {32}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DQ_PER_DQS} {8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DISCRETE_CS_WIDTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_NUM_OF_DIMMS} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RANKS_PER_DIMM} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_CKE_PER_DIMM} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_CK_WIDTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ROW_ADDR_WIDTH} {15}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_COL_ADDR_WIDTH} {10}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BANK_ADDR_WIDTH} {3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DM_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_MIRROR_ADDRESSING_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_HIDE_ADV_MR_SETTINGS} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RDIMM_CONFIG} {0000000000000000}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_LRDIMM_EXTENDED_CONFIG} {000000000000000000}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ALERT_N_PLACEMENT_ENUM} {DDR3_ALERT_N_PLACEMENT_AC_LANES}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ALERT_N_DQS_GROUP} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BL_ENUM} {DDR3_BL_BL8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BT_ENUM} {DDR3_BT_SEQUENTIAL}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ASR_ENUM} {DDR3_ASR_MANUAL}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_SRT_ENUM} {DDR3_SRT_NORMAL}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_PD_ENUM} {DDR3_PD_OFF}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DRV_STR_ENUM} {DDR3_DRV_STR_RZQ_7}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DLL_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RTT_NOM_ENUM} {DDR3_RTT_NOM_ODT_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RTT_WR_ENUM} {DDR3_RTT_WR_RZQ_4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_WTCL} {10}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ATCL_ENUM} {DDR3_ATCL_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TCL} {14}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_USE_DEFAULT_ODT} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_1X1} {Rank\ 0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_1X1} {off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_1X1} {Rank\ 0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_1X1} {on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_2X2} {Rank\ 0 Rank\ 1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_2X2} {off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_2X2} {off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_2X2} {Rank\ 0 Rank\ 1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_2X2} {on off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_2X2} {off on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_4X2} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_4X2} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_4X2} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_4X2} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_4X4} {off off off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_4X4} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT2_4X4} {off off off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT3_4X4} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_4X4} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_4X4} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT2_4X4} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT3_4X4} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_SPEEDBIN_ENUM} {DDR3_SPEEDBIN_2133}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIS_PS} {60}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIS_AC_MV} {135}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIH_PS} {95}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIH_DC_MV} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDS_PS} {53}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDS_AC_MV} {135}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDH_PS} {55}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDH_DC_MV} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSQ_PS} {75}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TQH_CYC} {0.38}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSCK_PS} {180}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSS_CYC} {0.27}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TQSH_CYC} {0.4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDSH_CYC} {0.18}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWLS_PS} {125.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWLH_PS} {125.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDSS_CYC} {0.18}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TINIT_US} {500}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TMRD_CK_CYC} {4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRAS_NS} {33.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRCD_NS} {13.09}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRP_NS} {13.09}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TREFI_US} {7.8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRFC_NS} {160.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWR_NS} {15.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWTR_CYC} {8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TFAW_NS} {25.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRRD_CYC} {6}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRTP_CYC} {8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_FORMAT_ENUM} {MEM_FORMAT_UDIMM}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DQ_WIDTH} {32}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DQ_PER_DQS} {8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DISCRETE_CS_WIDTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_NUM_OF_DIMMS} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RANKS_PER_DIMM} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CKE_PER_DIMM} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CK_WIDTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ROW_ADDR_WIDTH} {15}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_COL_ADDR_WIDTH} {10}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BANK_ADDR_WIDTH} {2}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BANK_GROUP_WIDTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CHIP_ID_WIDTH} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DM_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_PAR_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_PLACEMENT_ENUM} {DDR4_ALERT_N_PLACEMENT_DATA_LANES}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_DQS_GROUP} {3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_AC_LANE} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_AC_PIN} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MIRROR_ADDRESSING_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_HIDE_ADV_MR_SETTINGS} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BL_ENUM} {DDR4_BL_BL8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BT_ENUM} {DDR4_BT_SEQUENTIAL}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCL} {20}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_NOM_ENUM} {DDR4_RTT_NOM_RZQ_6}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DLL_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ATCL_ENUM} {DDR4_ATCL_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DRV_STR_ENUM} {DDR4_DRV_STR_RZQ_7}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ASR_ENUM} {DDR4_ASR_MANUAL_NORMAL}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_WR_ENUM} {DDR4_RTT_WR_ODT_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WTCL} {18}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_CRC} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_GEARDOWN} {DDR4_GEARDOWN_HR}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_PER_DRAM_ADDR} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_SENSOR_READOUT} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_FINE_GRANULARITY_REFRESH} {DDR4_FINE_REFRESH_FIXED_1X}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MPR_READ_FORMAT} {DDR4_MPR_READ_FORMAT_SERIAL}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MAX_POWERDOWN} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE} {DDR4_TEMP_CONTROLLED_RFSH_NORMAL}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_INTERNAL_VREFDQ_MONITOR} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CAL_MODE} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SELF_RFSH_ABORT} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_PREAMBLE_TRAINING} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_PREAMBLE} {2}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_PREAMBLE} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_AC_PARITY_LATENCY} {DDR4_AC_PARITY_LATENCY_DISABLE}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ODT_IN_POWERDOWN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_PARK} {DDR4_RTT_PARK_ODT_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_AC_PERSISTENT_ERROR} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_DBI} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_DBI} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DEFAULT_VREFOUT} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USER_VREFDQ_TRAINING_VALUE} {56.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USER_VREFDQ_TRAINING_RANGE} {DDR4_VREFDQ_TRAINING_RANGE_1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CA_IBT_ENUM} {DDR4_RCD_CA_IBT_100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CS_IBT_ENUM} {DDR4_RCD_CS_IBT_100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CKE_IBT_ENUM} {DDR4_RCD_CKE_IBT_100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_ODT_IBT_ENUM} {DDR4_RCD_ODT_IBT_100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_NOM_ENUM} {DDR4_DB_RTT_NOM_ODT_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_WR_ENUM} {DDR4_DB_RTT_WR_RZQ_3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_PARK_ENUM} {DDR4_DB_RTT_PARK_ODT_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_DQ_DRV_ENUM} {DDR4_DB_DRV_STR_RZQ_7}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_137_RCD_CA_DRV} {101}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_138_RCD_CK_DRV} {5}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_140_DRAM_VREFDQ_R0} {29}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_141_DRAM_VREFDQ_R1} {29}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_142_DRAM_VREFDQ_R2} {29}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_143_DRAM_VREFDQ_R3} {29}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_144_DB_VREFDQ} {37}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_145_DB_MDQ_DRV} {21}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_148_DRAM_DRV} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM} {20}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_152_DRAM_RTT_PARK} {39}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_135_RCD_REV} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_139_DB_REV} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_ODT_LESS_BS} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM} {240}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USE_DEFAULT_ODT} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_1X1} {Rank\ 0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_1X1} {off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_1X1} {Rank\ 0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_1X1} {on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_2X2} {Rank\ 0 Rank\ 1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_2X2} {off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_2X2} {off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_2X2} {Rank\ 0 Rank\ 1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_2X2} {on off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_2X2} {off on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_4X2} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_4X2} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_4X2} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_4X2} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_4X4} {off off off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_4X4} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT2_4X4} {off off off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT3_4X4} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_4X4} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_4X4} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT2_4X4} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT3_4X4} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIS_PS} {60}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIS_AC_MV} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIH_PS} {95}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIH_DC_MV} {75}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDIVW_TOTAL_UI} {0.2}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_VDIVW_TOTAL} {136}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSQ_UI} {0.16}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQH_UI} {0.76}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDVWP_UI} {0.72}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSCK_PS} {165}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSS_CYC} {0.27}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQSH_CYC} {0.38}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDSH_CYC} {0.18}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDSS_CYC} {0.18}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWLS_PS} {108.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWLH_PS} {108.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TINIT_US} {500}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TMRD_CK_CYC} {8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRAS_NS} {32.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRCD_NS} {14.25}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRP_NS} {14.25}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TREFI_US} {7.8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRFC_NS} {260.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWR_NS} {15.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWTR_L_CYC} {10}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWTR_S_CYC} {4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TFAW_NS} {30.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRRD_L_CYC} {8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRRD_S_CYC} {7}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCCD_L_CYC} {6}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCCD_S_CYC} {4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDIVW_DJ_CYC} {0.1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSQ_PS} {66}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQH_CYC} {0.38}
-set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_VREFDQ_VALUE} {1D}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_WIDTH_EXPANDED} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_DATA_PER_DEVICE} {36}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_ADDR_WIDTH} {19}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_BWS_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_BL} {4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_SPEEDBIN_ENUM} {QDR2_SPEEDBIN_633}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TRL_CYC} {2.5}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TSA_NS} {0.23}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_THA_NS} {0.18}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TSD_NS} {0.23}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_THD_NS} {0.18}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQD_NS} {0.09}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQDOH_NS} {-0.09}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_INTERNAL_JITTER_NS} {0.08}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQH_NS} {0.71}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCCQO_NS} {0.45}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_WIDTH_EXPANDED} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DQ_PER_PORT_PER_DEVICE} {36}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_ADDR_WIDTH} {21}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_CK_ODT_MODE_ENUM} {QDR4_ODT_25_PCT}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_AC_ODT_MODE_ENUM} {QDR4_ODT_25_PCT}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DATA_ODT_MODE_ENUM} {QDR4_ODT_25_PCT}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM} {QDR4_OUTPUT_DRIVE_25_PCT}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM} {QDR4_OUTPUT_DRIVE_25_PCT}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DATA_INV_ENA} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_ADDR_INV_ENA} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_SPEEDBIN_ENUM} {QDR4_SPEEDBIN_2133}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TISH_PS} {150}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TQKQ_MAX_PS} {75}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TQH_CYC} {0.4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKDK_MAX_PS} {150}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKDK_MIN_PS} {-150}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKQK_MAX_PS} {225}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TASH_PS} {170}
-set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCSH_PS} {170}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_WIDTH_EXPANDED} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DQ_PER_DEVICE} {9}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_ADDR_WIDTH} {21}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_BANK_ADDR_WIDTH} {3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DM_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_BL} {4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_CONFIG_ENUM} {RLD2_CONFIG_TRC_8_TRL_8_TWL_9}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DRIVE_IMPEDENCE_ENUM} {RLD2_DRIVE_IMPEDENCE_INTERNAL_50}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_ODT_MODE_ENUM} {RLD2_ODT_ON}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_SPEEDBIN_ENUM} {RLD2_SPEEDBIN_18}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_REFRESH_INTERVAL_US} {0.24}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKH_CYC} {0.45}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKH_HCYC} {0.9}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TAS_NS} {0.3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TAH_NS} {0.3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TDS_NS} {0.17}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TDH_NS} {0.17}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKQ_MAX_NS} {0.12}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKQ_MIN_NS} {-0.12}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKDK_MAX_NS} {0.3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKDK_MIN_NS} {-0.3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKQK_MAX_NS} {0.2}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_WIDTH_EXPANDED} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DEPTH_EXPANDED} {0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DQ_PER_DEVICE} {36}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_ADDR_WIDTH} {20}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_BANK_ADDR_WIDTH} {4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DM_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_BL} {2}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DATA_LATENCY_MODE_ENUM} {RLD3_DL_RL16_WL17}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_T_RC_MODE_ENUM} {RLD3_TRC_9}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM} {RLD3_OUTPUT_DRIVE_40}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_ODT_MODE_ENUM} {RLD3_ODT_40}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_AREF_PROTOCOL_ENUM} {RLD3_AREF_BAC}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_WRITE_PROTOCOL_ENUM} {RLD3_WRITE_1BANK}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_SPEEDBIN_ENUM} {RLD3_SPEEDBIN_093E}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDS_PS} {-30}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDS_AC_MV} {150}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDH_PS} {5}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDH_DC_MV} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TQKQ_MAX_PS} {75}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TQH_CYC} {0.38}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKDK_MAX_CYC} {0.27}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKDK_MIN_CYC} {-0.27}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKQK_MAX_PS} {135}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIS_PS} {85}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIS_AC_MV} {150}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIH_PS} {65}
-set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIH_DC_MV} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DQ_WIDTH} {32}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DISCRETE_CS_WIDTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_CK_WIDTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DM_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_ROW_ADDR_WIDTH} {15}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_COL_ADDR_WIDTH} {10}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_BANK_ADDR_WIDTH} {3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_BL} {LPDDR3_BL_BL8}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DATA_LATENCY} {LPDDR3_DL_RL12_WL6}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_NWR} {LPDDR3_NWR_NWR10}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DRV_STR} {LPDDR3_DRV_STR_40D_40U}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DQODT} {LPDDR3_DQODT_DISABLE}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_PDODT} {LPDDR3_PDODT_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_USE_DEFAULT_ODT} {1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_1X1} {Rank\ 0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_1X1} {off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_1X1} {Rank\ 0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_1X1} {on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_2X2} {Rank\ 0 Rank\ 1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_2X2} {off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT1_2X2} {off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_2X2} {Rank\ 0 Rank\ 1}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_2X2} {on off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT1_2X2} {off on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_4X4} {off off on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT1_4X4} {off off off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT2_4X4} {on on off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT3_4X4} {off off off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_4X4} {on on on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT1_4X4} {off off off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT2_4X4} {on on on on}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT3_4X4} {off off off off}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_SPEEDBIN_ENUM} {LPDDR3_SPEEDBIN_1600}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIS_PS} {75}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIS_AC_MV} {150}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIH_PS} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIH_DC_MV} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDS_PS} {75}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDS_AC_MV} {150}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDH_PS} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDH_DC_MV} {100}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSQ_PS} {135}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TQH_CYC} {0.38}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSCKDL} {614}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSS_CYC} {1.25}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TQSH_CYC} {0.38}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDSH_CYC} {0.2}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWLS_PS} {175.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWLH_PS} {175.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDSS_CYC} {0.2}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TINIT_US} {500}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TMRR_CK_CYC} {4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TMRW_CK_CYC} {10}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRAS_NS} {42.5}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRCD_NS} {18.75}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRP_NS} {18.75}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TREFI_US} {3.9}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRFC_NS} {210.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWR_NS} {15.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWTR_CYC} {4}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TFAW_NS} {50.0}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRRD_CYC} {2}
-set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRTP_CYC} {4}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USE_DEFAULT_SLEW_RATES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USE_DEFAULT_ISI_VALUES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_CK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_AC_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RCLK_SLEW_RATE} {5.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WCLK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RDATA_SLEW_RATE} {2.5}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WDATA_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_AC_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED} {0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_DQS_TO_CK_SKEW_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS} {0.05}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_SKEW_BETWEEN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_AC_TO_CK_SKEW_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_MAX_CK_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_MAX_DQS_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USE_DEFAULT_SLEW_RATES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USE_DEFAULT_ISI_VALUES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_CK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_AC_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RCLK_SLEW_RATE} {8.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WCLK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RDATA_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WDATA_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_AC_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED} {0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_DQS_TO_CK_SKEW_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS} {0.05}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_SKEW_BETWEEN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_AC_TO_CK_SKEW_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_MAX_CK_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_MAX_DQS_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USE_DEFAULT_SLEW_RATES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USE_DEFAULT_ISI_VALUES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_K_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_AC_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RCLK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RDATA_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WDATA_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_AC_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED} {0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED} {0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_D_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_AC_TO_K_SKEW_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_MAX_K_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USE_DEFAULT_SLEW_RATES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USE_DEFAULT_ISI_VALUES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_CK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_AC_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RCLK_SLEW_RATE} {5.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WCLK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RDATA_SLEW_RATE} {2.5}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WDATA_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_AC_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED} {0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_DK_TO_CK_SKEW_NS} {-0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS} {0.05}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_SKEW_BETWEEN_DK_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_AC_TO_CK_SKEW_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_MAX_CK_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_MAX_DK_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USE_DEFAULT_SLEW_RATES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USE_DEFAULT_ISI_VALUES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_CK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_AC_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RCLK_SLEW_RATE} {7.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WCLK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RDATA_SLEW_RATE} {3.5}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WDATA_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_AC_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED} {0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_DK_TO_CK_SKEW_NS} {-0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS} {0.05}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_SKEW_BETWEEN_DK_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_AC_TO_CK_SKEW_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_MAX_CK_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_MAX_DK_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_CK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_AC_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RCLK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WCLK_SLEW_RATE} {4.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RDATA_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WDATA_SLEW_RATE} {2.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_AC_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WCLK_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WDATA_ISI_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED} {0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED} {1}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_DQS_TO_CK_SKEW_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS} {0.05}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS} {0.02}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_AC_TO_CK_SKEW_NS} {0.0}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_MAX_CK_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_MAX_DQS_DELAY_NS} {0.6}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_SELF_REFRESH_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_POWER_DOWN_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_POWER_DOWN_CYCS} {32}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_USER_REFRESH_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_USER_PRIORITY_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_PRECHARGE_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ADDR_ORDER_ENUM} {DDR3_CTRL_ADDR_ORDER_CS_R_B_C}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ECC_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ECC_AUTO_CORRECTION_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_REORDER_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_STARVE_LIMIT} {10}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_MMR_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_SELF_REFRESH_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_POWER_DOWN_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_POWER_DOWN_CYCS} {32}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_USER_REFRESH_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_USER_PRIORITY_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_PRECHARGE_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ADDR_ORDER_ENUM} {DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ECC_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ECC_AUTO_CORRECTION_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_REORDER_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_STARVE_LIMIT} {10}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_MMR_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_MAX_BURST_COUNT} {4}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_MAX_BURST_COUNT} {4}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD2_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD3_ADDR_ORDER_ENUM} {RLD3_CTRL_ADDR_ORDER_CS_R_B_C}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_SELF_REFRESH_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_POWER_DOWN_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS} {32}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_USER_REFRESH_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_USER_PRIORITY_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_PRECHARGE_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_ADDR_ORDER_ENUM} {LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_REORDER_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_STARVE_LIMIT} {10}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_MMR_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_SIM_REGTEST_MODE} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_TIMING_REGTEST_MODE} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_SYNTH_FOR_SIM} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_FAST_SIM_OVERRIDE} {FAST_SIM_OVERRIDE_DEFAULT}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_VERBOSE_IOAUX} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_ECLIPSE_DEBUG} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_EXPORT_VJI} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_JTAG_UART} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_JTAG_UART_HEX} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_HPS_EMIF_DEBUG} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_SOFT_NIOS_MODE} {SOFT_NIOS_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_SOFT_NIOS_CLOCK_FREQUENCY} {100}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_USE_RS232_UART} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RS232_UART_BAUDRATE} {57600}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_EX_DESIGN_ADD_TEST_EMIFS} {}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_EX_DESIGN_SEPARATE_RESETS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_EXPOSE_DFT_SIGNALS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_EXTRA_CONFIGS} {}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_USE_BOARD_DELAY_MODEL} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_BOARD_DELAY_CONFIG_STR} {}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_TG_AVL_2_NUM_CFG_INTERFACES} {0}
-set_instance_parameter_value emif_a10_hps_0 {SHORT_QSYS_INTERFACE_NAMES} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_ISSP_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_INTERFACE_ID} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_USE_TG_AVL_2} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_ABSTRACT_PHY} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_DEFAULT_PATTERN} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_USER_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_REPEAT_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_STRESS_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_TG_DATA_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_TG_BE_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_SEPARATE_READ_WRITE_ITFS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CA_LEVEL_EN} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ADDR0} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ADDR1} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ENABLE_NON_DES} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_FULL_CAL_ON_RESET} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_ISSP_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_INTERFACE_ID} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_USE_TG_AVL_2} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_ABSTRACT_PHY} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_DEFAULT_PATTERN} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_USER_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_REPEAT_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_STRESS_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_TG_DATA_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_TG_BE_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SEPARATE_READ_WRITE_ITFS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_CA_LEVEL} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_CA_DESKEW} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_VREF_CAL} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ADDR0} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ADDR1} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ENABLE_NON_DES} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_FULL_CAL_ON_RESET} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_ISSP_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_INTERFACE_ID} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_USE_TG_AVL_2} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_ABSTRACT_PHY} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_DEFAULT_PATTERN} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_USER_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_REPEAT_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_STRESS_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_TG_DATA_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_TG_BE_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_SEPARATE_READ_WRITE_ITFS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_ISSP_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_INTERFACE_ID} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_USE_TG_AVL_2} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_ABSTRACT_PHY} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_DEFAULT_PATTERN} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_USER_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_REPEAT_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_STRESS_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_TG_DATA_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_TG_BE_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SEPARATE_READ_WRITE_ITFS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SKIP_VREF_CAL} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_ISSP_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_INTERFACE_ID} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_USE_TG_AVL_2} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_ABSTRACT_PHY} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_DEFAULT_PATTERN} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_USER_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_REPEAT_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_STRESS_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_TG_DATA_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_TG_BE_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_SEPARATE_READ_WRITE_ITFS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_ISSP_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_INTERFACE_ID} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_USE_TG_AVL_2} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_ABSTRACT_PHY} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_DEFAULT_PATTERN} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_USER_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_REPEAT_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_STRESS_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_TG_DATA_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_TG_BE_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_SEPARATE_READ_WRITE_ITFS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_ISSP_EN} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_INTERFACE_ID} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_USE_TG_AVL_2} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_ABSTRACT_PHY} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_USER_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_REPEAT_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_STRESS_STAGE} {1}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_TG_BE_PATTERN_LENGTH} {8}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SKIP_CA_LEVEL} {0}
-set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SKIP_CA_DESKEW} {0}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_GEN_SIM} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_GEN_SYNTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_HDL_FORMAT} {HDL_FORMAT_VERILOG}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_PREV_PRESET} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_GEN_SIM} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_GEN_SYNTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_HDL_FORMAT} {HDL_FORMAT_VERILOG}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_PREV_PRESET} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_GEN_SIM} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_GEN_SYNTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_HDL_FORMAT} {HDL_FORMAT_VERILOG}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_PREV_PRESET} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_GEN_SIM} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_GEN_SYNTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_HDL_FORMAT} {HDL_FORMAT_VERILOG}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_PREV_PRESET} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_GEN_SIM} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_GEN_SYNTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_HDL_FORMAT} {HDL_FORMAT_VERILOG}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_PREV_PRESET} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_GEN_SIM} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_GEN_SYNTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_HDL_FORMAT} {HDL_FORMAT_VERILOG}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_PREV_PRESET} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_GEN_SIM} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_GEN_SYNTH} {1}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_HDL_FORMAT} {HDL_FORMAT_VERILOG}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE}
-set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_PREV_PRESET} {TARGET_DEV_KIT_NONE}
+proc set_hps_io {io_index io_type} {
+
+  global hps_io_list
+  lappend hps_io_list $io_type
+}
+
+set_hps_io  IO_DEDICATED_04   SDMMC:D0
+set_hps_io  IO_DEDICATED_05   SDMMC:CMD
+set_hps_io  IO_DEDICATED_06   SDMMC:CCLK
+set_hps_io  IO_DEDICATED_07   SDMMC:D1
+set_hps_io  IO_DEDICATED_08   SDMMC:D2
+set_hps_io  IO_DEDICATED_09   SDMMC:D3
+set_hps_io  IO_DEDICATED_10   NONE
+set_hps_io  IO_DEDICATED_11   NONE
+set_hps_io  IO_DEDICATED_12   SDMMC:D4
+set_hps_io  IO_DEDICATED_13   SDMMC:D5
+set_hps_io  IO_DEDICATED_14   SDMMC:D6
+set_hps_io  IO_DEDICATED_15   SDMMC:D7
+set_hps_io  IO_DEDICATED_16   UART1:TX
+set_hps_io  IO_DEDICATED_17   UART1:RX
+set_hps_io  IO_SHARED_Q1_01   USB0:CLK
+set_hps_io  IO_SHARED_Q1_02   USB0:STP
+set_hps_io  IO_SHARED_Q1_03   USB0:DIR
+set_hps_io  IO_SHARED_Q1_04   USB0:DATA0
+set_hps_io  IO_SHARED_Q1_05   USB0:DATA1
+set_hps_io  IO_SHARED_Q1_06   USB0:NXT
+set_hps_io  IO_SHARED_Q1_07   USB0:DATA2
+set_hps_io  IO_SHARED_Q1_08   USB0:DATA3
+set_hps_io  IO_SHARED_Q1_09   USB0:DATA4
+set_hps_io  IO_SHARED_Q1_10   USB0:DATA5
+set_hps_io  IO_SHARED_Q1_11   USB0:DATA6
+set_hps_io  IO_SHARED_Q1_12   USB0:DATA7
+set_hps_io  IO_SHARED_Q2_01   EMAC0:TX_CLK
+set_hps_io  IO_SHARED_Q2_02   EMAC0:TX_CTL
+set_hps_io  IO_SHARED_Q2_03   EMAC0:RX_CLK
+set_hps_io  IO_SHARED_Q2_04   EMAC0:RX_CTL
+set_hps_io  IO_SHARED_Q2_05   EMAC0:TXD0
+set_hps_io  IO_SHARED_Q2_06   EMAC0:TXD1
+set_hps_io  IO_SHARED_Q2_07   EMAC0:RXD0
+set_hps_io  IO_SHARED_Q2_08   EMAC0:RXD1
+set_hps_io  IO_SHARED_Q2_09   EMAC0:TXD2
+set_hps_io  IO_SHARED_Q2_10   EMAC0:TXD3
+set_hps_io  IO_SHARED_Q2_11   EMAC0:RXD2
+set_hps_io  IO_SHARED_Q2_12   EMAC0:RXD3
+set_hps_io  IO_SHARED_Q3_01   NONE
+set_hps_io  IO_SHARED_Q3_02   NONE
+set_hps_io  IO_SHARED_Q3_03   NONE
+set_hps_io  IO_SHARED_Q3_04   NONE
+set_hps_io  IO_SHARED_Q3_05   NONE
+set_hps_io  IO_SHARED_Q3_06   GPIO
+set_hps_io  IO_SHARED_Q3_07   NONE
+set_hps_io  IO_SHARED_Q3_08   NONE
+set_hps_io  IO_SHARED_Q3_09   NONE
+set_hps_io  IO_SHARED_Q3_10   NONE
+set_hps_io  IO_SHARED_Q3_11   MDIO0:MDIO
+set_hps_io  IO_SHARED_Q3_12   MDIO0:MDC
+set_hps_io  IO_SHARED_Q4_01   I2C1:SDA
+set_hps_io  IO_SHARED_Q4_02   I2C1:SCL
+set_hps_io  IO_SHARED_Q4_03   GPIO
+set_hps_io  IO_SHARED_Q4_04   NONE
+set_hps_io  IO_SHARED_Q4_05   GPIO
+set_hps_io  IO_SHARED_Q4_06   GPIO
+set_hps_io  IO_SHARED_Q4_07   NONE
+set_hps_io  IO_SHARED_Q4_08   NONE
+set_hps_io  IO_SHARED_Q4_09   NONE
+set_hps_io  IO_SHARED_Q4_10   NONE
+set_hps_io  IO_SHARED_Q4_11   NONE
+set_hps_io  IO_SHARED_Q4_12   NONE
+
+add_instance sys_hps altera_arria10_hps 16.0
+set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value sys_hps {F2S_Width} {0}
+set_instance_parameter_value sys_hps {S2F_Width} {0}
+set_instance_parameter_value sys_hps {LWH2F_Enable} {1}
+set_instance_parameter_value sys_hps {F2SDRAM_PORT_CONFIG} {6}
+set_instance_parameter_value sys_hps {F2SDRAM0_ENABLED} {1}
+set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
+set_instance_parameter_value sys_hps {HPS_IO_Enable} $hps_io_list
+set_instance_parameter_value sys_hps {SDMMC_PinMuxing} {IO}
+set_instance_parameter_value sys_hps {SDMMC_Mode} {8-bit}
+set_instance_parameter_value sys_hps {USB0_PinMuxing} {IO}
+set_instance_parameter_value sys_hps {USB0_Mode} {default}
+set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {IO}
+set_instance_parameter_value sys_hps {EMAC0_Mode} {RGMII_with_MDIO}
+set_instance_parameter_value sys_hps {UART1_PinMuxing} {IO}
+set_instance_parameter_value sys_hps {UART1_Mode} {No_flow_control}
+set_instance_parameter_value sys_hps {I2C1_PinMuxing} {IO}
+set_instance_parameter_value sys_hps {I2C1_Mode} {default}
+set_instance_parameter_value sys_hps {F2H_COLD_RST_Enable} {1}
+set_instance_parameter_value sys_hps {H2F_USER0_CLK_Enable} {1}
+set_instance_parameter_value sys_hps {H2F_USER0_CLK_FREQ} {175}
+set_instance_parameter_value sys_hps {CLK_SDMMC_SOURCE} {1}
+
+add_interface sys_hps_rstn reset sink
+set_interface_property sys_hps_rstn EXPORT_OF sys_hps.f2h_cold_reset_req
+add_interface sys_hps_out_rstn reset source
+set_interface_property sys_hps_out_rstn EXPORT_OF sys_hps.h2f_reset
+add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
+add_connection sys_hps.h2f_user0_clock sys_hps.f2sdram0_clock
+add_interface sys_hps_io conduit end
+set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io
+
+# ddr4 interface
+
+add_instance sys_hps_ddr4_cntrl altera_emif_a10_hps 16.0
+set_instance_parameter_value sys_hps_ddr4_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR4}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_BANK_GROUP_WIDTH} {1}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_ALERT_N_PLACEMENT_ENUM} {DDR4_ALERT_N_PLACEMENT_DATA_LANES}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_ALERT_N_DQS_GROUP} {3}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_READ_DBI} {1}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TCL} {20}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_WTCL} {18}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_RTT_NOM_ENUM} {DDR4_RTT_NOM_RZQ_6}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_DEFAULT_IO} {0}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_12}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_AC_MODE_ENUM} {OUT_OCT_40_CAL}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_12}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_MODE_ENUM} {OUT_OCT_40_CAL}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_CMOS_12}
+set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRCD_NS} {14.25}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRP_NS} {14.25}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRRD_S_CYC} {7}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRRD_L_CYC} {8}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TFAW_NS} {30.0}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TWTR_S_CYC} {4}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TWTR_L_CYC} {10}
+set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_LRDIMM_VREFDQ_VALUE} {1D}
+set_instance_parameter_value sys_hps_ddr4_cntrl {DIAG_DDR4_SKIP_CA_LEVEL} {1}
+set_instance_parameter_value sys_hps_ddr4_cntrl {SHORT_QSYS_INTERFACE_NAMES} {0}
+
+add_interface sys_hps_ddr_rstn reset sink
+set_interface_property sys_hps_ddr_rstn EXPORT_OF sys_hps_ddr4_cntrl.global_reset_reset_sink
+add_connection sys_hps_ddr4_cntrl.hps_emif_conduit_end sys_hps.emif
+add_interface sys_hps_ddr conduit end
+set_interface_property sys_hps_ddr EXPORT_OF sys_hps_ddr4_cntrl.mem_conduit_end
+add_interface sys_hps_ddr_oct conduit end
+set_interface_property sys_hps_ddr_oct EXPORT_OF sys_hps_ddr4_cntrl.oct_conduit_end
+add_interface sys_hps_ddr_ref_clk clock sink
+set_interface_property sys_hps_ddr_ref_clk EXPORT_OF sys_hps_ddr4_cntrl.pll_ref_clk_clock_sink
+
+# cpu/hps handling
+
+proc ad_cpu_interrupt {m_irq m_port} {
+
+  add_connection sys_hps.f2h_irq0 ${m_port}
+  set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
+}
+
+proc ad_cpu_interconnect {m_base m_port} {
+
+  add_connection sys_hps.h2f_lw_axi_master ${m_port}
+  set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
+}
+
+proc ad_dma_interconnect {m_port} {
+
+  add_connection ${m_port} sys_hps.f2sdram0_data
+  set_connection_parameter_value ${m_port}/sys_hps.f2sdram0_data baseAddress {0x0}
+}
+
+# gpio-in
+
+add_instance sys_gpio_in altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_in {direction} {Input}
+set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_in {width} {32}
+
+add_connection sys_clk.clk_reset sys_gpio_in.reset
+add_connection sys_clk.clk sys_gpio_in.clk
+add_interface sys_gpio_in conduit end
+set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
+
+# gpio-out
+
+add_instance sys_gpio_out altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_out {direction} {Output}
+set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
+set_instance_parameter_value sys_gpio_out {width} {32}
+
+add_connection sys_clk.clk_reset sys_gpio_out.reset
+add_connection sys_clk.clk sys_gpio_out.clk
+add_interface sys_gpio_out conduit end
+set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
+
+# spi
 
 add_instance sys_spi altera_avalon_spi 16.0
-set_instance_parameter_value sys_spi {clockPhase} {1}
-set_instance_parameter_value sys_spi {clockPolarity} {1}
+set_instance_parameter_value sys_spi {clockPhase} {0}
+set_instance_parameter_value sys_spi {clockPolarity} {0}
 set_instance_parameter_value sys_spi {dataWidth} {8}
-set_instance_parameter_value sys_spi {disableAvalonFlowControl} {0}
-set_instance_parameter_value sys_spi {insertDelayBetweenSlaveSelectAndSClk} {0}
-set_instance_parameter_value sys_spi {insertSync} {0}
-set_instance_parameter_value sys_spi {lsbOrderedFirst} {0}
 set_instance_parameter_value sys_spi {masterSPI} {1}
-set_instance_parameter_value sys_spi {numberOfSlaves} {2}
-set_instance_parameter_value sys_spi {syncRegDepth} {2}
-set_instance_parameter_value sys_spi {targetClockRate} {5000000.0}
-set_instance_parameter_value sys_spi {targetSlaveSelectToSClkDelay} {0.0}
-
-add_instance gpio_i altera_avalon_pio 16.0
-set_instance_parameter_value gpio_i {bitClearingEdgeCapReg} {0}
-set_instance_parameter_value gpio_i {bitModifyingOutReg} {0}
-set_instance_parameter_value gpio_i {captureEdge} {0}
-set_instance_parameter_value gpio_i {direction} {Input}
-set_instance_parameter_value gpio_i {edgeType} {RISING}
-set_instance_parameter_value gpio_i {generateIRQ} {0}
-set_instance_parameter_value gpio_i {irqType} {LEVEL}
-set_instance_parameter_value gpio_i {resetValue} {0.0}
-set_instance_parameter_value gpio_i {simDoTestBenchWiring} {0}
-set_instance_parameter_value gpio_i {simDrivenValue} {0.0}
-set_instance_parameter_value gpio_i {width} {32}
-
-add_instance gpio_o altera_avalon_pio 16.0
-set_instance_parameter_value gpio_o {bitClearingEdgeCapReg} {0}
-set_instance_parameter_value gpio_o {bitModifyingOutReg} {1}
-set_instance_parameter_value gpio_o {captureEdge} {0}
-set_instance_parameter_value gpio_o {direction} {Output}
-set_instance_parameter_value gpio_o {edgeType} {RISING}
-set_instance_parameter_value gpio_o {generateIRQ} {0}
-set_instance_parameter_value gpio_o {irqType} {LEVEL}
-set_instance_parameter_value gpio_o {resetValue} {0.0}
-set_instance_parameter_value gpio_o {simDoTestBenchWiring} {0}
-set_instance_parameter_value gpio_o {simDrivenValue} {0.0}
-set_instance_parameter_value gpio_o {width} {32}
-
-# connections and connection parameters
-add_connection sys_clk.clk arria10_hps_0.h2f_lw_axi_clock clock
-add_connection sys_clk.clk sys_spi.clk clock
-add_connection sys_clk.clk gpio_i.clk clock
-add_connection sys_clk.clk gpio_o.clk clock
-add_connection sys_clk.clk sys_rst.clk clock
-
-add_connection arria10_hps_0.h2f_user0_clock arria10_hps_0.f2sdram0_clock clock
-
-add_connection emif_a10_hps_0.hps_emif_conduit_end arria10_hps_0.emif conduit
-set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif endPort {}
-set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif endPortLSB {0}
-set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif startPort {}
-set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif startPortLSB {0}
-set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif width {0}
-
-add_connection sys_clk.clk_reset arria10_hps_0.f2h_cold_reset_req reset
-add_connection sys_clk.clk_reset emif_a10_hps_0.global_reset_reset_sink reset
-add_connection sys_clk.clk_reset sys_rst.in_reset reset
-add_connection arria10_hps_0.h2f_reset sys_rst.in_reset reset
-add_connection sys_rst.out_reset sys_spi.reset reset
-add_connection sys_rst.out_reset gpio_i.reset reset
-add_connection sys_rst.out_reset gpio_o.reset reset
-
-# exported interfaces
-add_interface hps_ddr conduit end
-set_interface_property hps_ddr EXPORT_OF emif_a10_hps_0.mem_conduit_end
-add_interface hps_ddr_oct conduit end
-set_interface_property hps_ddr_oct EXPORT_OF emif_a10_hps_0.oct_conduit_end
-add_interface hps_ddr_ref_clk clock sink
-set_interface_property hps_ddr_ref_clk EXPORT_OF emif_a10_hps_0.pll_ref_clk_clock_sink
-
-add_interface hps_io conduit end
-set_interface_property hps_io EXPORT_OF arria10_hps_0.hps_io
-add_interface hps_s1_axi altera_axi slave
+set_instance_parameter_value sys_spi {numberOfSlaves} {8}
+set_instance_parameter_value sys_spi {targetClockRate} {128000.0}
 
+add_connection sys_clk.clk_reset sys_spi.reset
+add_connection sys_clk.clk sys_spi.clk
+add_interface sys_spi conduit end
 set_interface_property sys_spi EXPORT_OF sys_spi.external
-set_interface_property gpio_o EXPORT_OF gpio_o.external_connection
-set_interface_property gpio_i EXPORT_OF gpio_i.external_connection
+
+# base-addresses
+
+ad_cpu_interconnect 0x00000000 sys_gpio_in.s1
+ad_cpu_interconnect 0x00000020 sys_gpio_out.s1
+ad_cpu_interconnect 0x00000040 sys_spi.spi_control_port
 
 # interrupts
-add_connection arria10_hps_0.f2h_irq0 sys_spi.irq
-set_connection_parameter_value arria10_hps_0.f2h_irq0/sys_spi.irq irqNumber {1}
 
-# cpu connections
-add_connection arria10_hps_0.h2f_lw_axi_master sys_spi.spi_control_port
-add_connection arria10_hps_0.h2f_lw_axi_master gpio_i.s1
-add_connection arria10_hps_0.h2f_lw_axi_master gpio_o.s1
+ad_cpu_interrupt 5 sys_gpio_in.irq
+ad_cpu_interrupt 7 sys_spi.irq
 
-set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/sys_spi.spi_control_port baseAddress {0x00000000}
-set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/gpio_i.s1 baseAddress {0x00000020}
-set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/gpio_o.s1 baseAddress {0x00000040}
+# common dma interfaces
+
+add_instance sys_dma_clk clock_source 16.0
+add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
+add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
 

From 50552ce7d6f40f808a5ef732cd184963cd5a9e55 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 27 Oct 2016 09:24:47 -0400
Subject: [PATCH 643/972] adrv9371x- altera updates

---
 projects/adrv9371x/a10gx/system_top.v         | 202 ++++++------------
 projects/common/a10gx/a10gx_system_qsys.tcl   | 139 ++++++------
 projects/common/a10soc/a10soc_system_qsys.tcl |  12 +-
 3 files changed, 139 insertions(+), 214 deletions(-)

diff --git a/projects/adrv9371x/a10gx/system_top.v b/projects/adrv9371x/a10gx/system_top.v
index abf241fc9..d795e8f6d 100644
--- a/projects/adrv9371x/a10gx/system_top.v
+++ b/projects/adrv9371x/a10gx/system_top.v
@@ -41,140 +41,72 @@ module system_top (
 
   // clock and resets
 
-  sys_clk,
-  sys_resetn,
+  input             sys_clk,
+  input             sys_resetn,
 
   // ddr3
 
-  ddr3_clk_p,
-  ddr3_clk_n,
-  ddr3_a,
-  ddr3_ba,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_odt,
-  ddr3_reset_n,
-  ddr3_we_n,
-  ddr3_ras_n,
-  ddr3_cas_n,
-  ddr3_dqs_p,
-  ddr3_dqs_n,
-  ddr3_dq,
-  ddr3_dm,
-  ddr3_rzq,
-  ddr3_ref_clk,
+  output            ddr3_clk_p,
+  output            ddr3_clk_n,
+  output  [ 14:0]   ddr3_a,
+  output  [  2:0]   ddr3_ba,
+  output            ddr3_cke,
+  output            ddr3_cs_n,
+  output            ddr3_odt,
+  output            ddr3_reset_n,
+  output            ddr3_we_n,
+  output            ddr3_ras_n,
+  output            ddr3_cas_n,
+  inout   [  7:0]   ddr3_dqs_p,
+  inout   [  7:0]   ddr3_dqs_n,
+  inout   [ 63:0]   ddr3_dq,
+  output  [  7:0]   ddr3_dm,
+  input             ddr3_rzq,
+  input             ddr3_ref_clk,
 
   // ethernet
 
-  eth_ref_clk,
-  eth_rxd,
-  eth_txd,
-  eth_mdc,
-  eth_mdio,
-  eth_resetn,
-  eth_intn,
+  input             eth_ref_clk,
+  input             eth_rxd,
+  output            eth_txd,
+  output            eth_mdc,
+  inout             eth_mdio,
+  output            eth_resetn,
+  input             eth_intn,
 
   // board gpio
 
-  gpio_bd_i,
-  gpio_bd_o,
+  input   [ 10:0]   gpio_bd_i,
+  output  [ 15:0]   gpio_bd_o,
 
   // lane interface
 
-  ref_clk0,
-  ref_clk1,
-  rx_data,
-  tx_data,
-  rx_sync,
-  rx_os_sync,
-  tx_sync,
-  sysref,
+  input             ref_clk0,
+  input             ref_clk1,
+  input   [  3:0]   rx_data,
+  output  [  3:0]   tx_data,
+  output            rx_sync,
+  output            rx_os_sync,
+  input             tx_sync,
+  input             sysref,
 
-  ad9528_reset_b,
-  ad9528_sysref_req,
-  ad9371_tx1_enable,
-  ad9371_tx2_enable,
-  ad9371_rx1_enable,
-  ad9371_rx2_enable,
-  ad9371_test,
-  ad9371_reset_b,
-  ad9371_gpint,
-  ad9371_gpio,
+  output            ad9528_reset_b,
+  output            ad9528_sysref_req,
+  output            ad9371_tx1_enable,
+  output            ad9371_tx2_enable,
+  output            ad9371_rx1_enable,
+  output            ad9371_rx2_enable,
+  output            ad9371_test,
+  output            ad9371_reset_b,
+  input             ad9371_gpint,
 
-  spi_csn_ad9528,
-  spi_csn_ad9371,
-  spi_clk,
-  spi_mosi,
-  spi_miso);
+  inout   [ 18:0]   ad9371_gpio,
 
-  // clock and resets
-
-  input             sys_clk;
-  input             sys_resetn;
-
-  // ddr3
-
-  output            ddr3_clk_p;
-  output            ddr3_clk_n;
-  output  [ 14:0]   ddr3_a;
-  output  [  2:0]   ddr3_ba;
-  output            ddr3_cke;
-  output            ddr3_cs_n;
-  output            ddr3_odt;
-  output            ddr3_reset_n;
-  output            ddr3_we_n;
-  output            ddr3_ras_n;
-  output            ddr3_cas_n;
-  inout   [  7:0]   ddr3_dqs_p;
-  inout   [  7:0]   ddr3_dqs_n;
-  inout   [ 63:0]   ddr3_dq;
-  output  [  7:0]   ddr3_dm;
-  input             ddr3_rzq;
-  input             ddr3_ref_clk;
-
-  // ethernet
-
-  input             eth_ref_clk;
-  input             eth_rxd;
-  output            eth_txd;
-  output            eth_mdc;
-  inout             eth_mdio;
-  output            eth_resetn;
-  input             eth_intn;
-
-  // board gpio
-
-  input   [ 10:0]   gpio_bd_i;
-  output  [ 15:0]   gpio_bd_o;
-
-  // lane interface
-
-  input             ref_clk0;
-  input             ref_clk1;
-  input   [  3:0]   rx_data;
-  output  [  3:0]   tx_data;
-  output            rx_sync;
-  output            rx_os_sync;
-  input             tx_sync;
-  input             sysref;
-
-  output            ad9528_reset_b;
-  output            ad9528_sysref_req;
-  output            ad9371_tx1_enable;
-  output            ad9371_tx2_enable;
-  output            ad9371_rx1_enable;
-  output            ad9371_rx2_enable;
-  output            ad9371_test;
-  output            ad9371_reset_b;
-  input             ad9371_gpint;
-
-  inout   [ 18:0]   ad9371_gpio;
-
-  output            spi_csn_ad9528;
-  output            spi_csn_ad9371;
-  output            spi_clk;
-  output            spi_mosi;
-  input             spi_miso;
+  output            spi_csn_ad9528,
+  output            spi_csn_ad9371,
+  output            spi_clk,
+  output            spi_mosi,
+  input             spi_miso);
 
   // internal signals
 
@@ -186,6 +118,8 @@ module system_top (
   wire    [ 63:0]   gpio_o;
   wire    [  7:0]   spi_csn_s;
 
+  // assignments
+
   assign spi_csn_ad9371 = spi_csn_s[0];
   assign spi_csn_ad9528 = spi_csn_s[1];
 
@@ -219,6 +153,17 @@ module system_top (
   assign gpio_bd_o = gpio_o[15:0];
 
   system_bd i_system_bd (
+    .avl_ad9371_gpio_export(ad9371_gpio),
+    .rx_data_0_rx_serial_data (rx_data[0]),
+    .rx_data_1_rx_serial_data (rx_data[1]),
+    .rx_data_2_rx_serial_data (rx_data[2]),
+    .rx_data_3_rx_serial_data (rx_data[3]),
+    .rx_os_ref_clk_clk (ref_clk1),
+    .rx_os_sync_export (rx_os_sync),
+    .rx_os_sysref_export (sysref),
+    .rx_ref_clk_clk (ref_clk1),
+    .rx_sync_export (rx_sync),
+    .rx_sysref_export (sysref),
     .sys_clk_clk (sys_clk),
     .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
     .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
@@ -254,18 +199,13 @@ module system_top (
     .sys_spi_MOSI (spi_mosi),
     .sys_spi_SCLK (spi_clk),
     .sys_spi_SS_n (spi_csn_s),
-    .ad9371_gpio_export(ad9371_gpio),
-    .xcvr_ref_clk_clk(ref_clk1),
-    .rx_data_rx_serial_data (rx_data[1:0]),
-    .rx_os_data_rx_serial_data (rx_data[3:2]),
-    .rx_os_sync_rx_sync (rx_os_sync),
-    .rx_os_sysref_rx_ext_sysref_in (sysref),
-    .rx_sync_rx_sync (rx_sync),
-    .rx_sysref_rx_ext_sysref_in (sysref),
-    .tx_data_tx_serial_data ({tx_data[0],tx_data[3],tx_data[2],tx_data[1]}),
-    .tx_sync_tx_sync (tx_sync),
-    .tx_sysref_tx_ext_sysref_in (sysref)
-  );
+    .tx_data_0_tx_serial_data (tx_data[0]),
+    .tx_data_1_tx_serial_data (tx_data[1]),
+    .tx_data_2_tx_serial_data (tx_data[2]),
+    .tx_data_3_tx_serial_data (tx_data[3]),
+    .tx_ref_clk_clk (ref_clk1),
+    .tx_sync_export (tx_sync),
+    .tx_sysref_export (sysref));
 
 endmodule
 
diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl
index b19a8d54e..ce0bf0b5c 100644
--- a/projects/common/a10gx/a10gx_system_qsys.tcl
+++ b/projects/common/a10gx/a10gx_system_qsys.tcl
@@ -25,7 +25,6 @@ set_instance_parameter_value sys_int_mem {dataWidth} {32}
 set_instance_parameter_value sys_int_mem {dualPort} {0}
 set_instance_parameter_value sys_int_mem {initMemContent} {0}
 set_instance_parameter_value sys_int_mem {memorySize} {163840.0}
-
 add_connection sys_clk.clk sys_int_mem.clk1
 add_connection sys_clk.clk_reset sys_int_mem.reset1
 
@@ -36,7 +35,6 @@ set_instance_parameter_value sys_tlb_mem {dataWidth} {32}
 set_instance_parameter_value sys_tlb_mem {dualPort} {1}
 set_instance_parameter_value sys_tlb_mem {initMemContent} {1}
 set_instance_parameter_value sys_tlb_mem {memorySize} {163840.0}
-
 add_connection sys_clk.clk sys_tlb_mem.clk1
 add_connection sys_clk.clk_reset sys_tlb_mem.reset1
 add_connection sys_clk.clk sys_tlb_mem.clk2
@@ -72,12 +70,10 @@ set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRCD_NS} {10.285}
 set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {10.285}
 set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {4.0}
 set_instance_parameter_value sys_ddr3_cntrl {SHORT_QSYS_INTERFACE_NAMES} {1}
-
 add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset_n
 add_interface sys_ddr3_cntrl_mem conduit end
 add_interface sys_ddr3_cntrl_oct conduit end
 add_interface sys_ddr3_cntrl_pll_ref_clk clock sink
-
 set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.mem
 set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct
 set_interface_property sys_ddr3_cntrl_pll_ref_clk EXPORT_OF sys_ddr3_cntrl.pll_ref_clk
@@ -103,19 +99,47 @@ set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
 set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
 set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
 set_instance_parameter_value sys_cpu {mmu_enabled} $mmu_enabled
-
 add_connection sys_clk.clk sys_cpu.clk
 add_connection sys_clk.clk_reset sys_cpu.reset
 add_connection sys_cpu.debug_reset_request sys_cpu.reset
-
 add_connection sys_cpu.instruction_master sys_cpu.debug_mem_slave
-add_connection sys_cpu.data_master sys_cpu.debug_mem_slave
 add_connection sys_cpu.instruction_master sys_int_mem.s1
-add_connection sys_cpu.data_master sys_int_mem.s1
 add_connection sys_cpu.tightly_coupled_instruction_master_0 sys_tlb_mem.s2
 add_connection sys_cpu.tightly_coupled_data_master_0 sys_tlb_mem.s1
 add_connection sys_cpu.instruction_master sys_ddr3_cntrl.ctrl_amm_0
 add_connection sys_cpu.data_master sys_ddr3_cntrl.ctrl_amm_0
+set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0}
+set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0}
+set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave baseAddress {0x10180800}
+set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1 baseAddress {0x10140000}
+set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2 baseAddress {0x10200000}
+set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1 baseAddress {0x10200000}
+
+# cpu/hps handling
+
+proc ad_cpu_interrupt {m_irq m_port} {
+
+  add_connection sys_cpu.irq ${m_port}
+  set_connection_parameter_value sys_cpu.irq/${m_port} irqNumber ${m_irq}
+}
+
+proc ad_cpu_interconnect {m_base m_port} {
+
+  add_connection sys_cpu.data_master ${m_port}
+  set_connection_parameter_value sys_cpu.data_master/${m_port} baseAddress [expr ($m_base + 0x10000000)]
+}
+
+proc ad_dma_interconnect {m_port} {
+
+  add_connection ${m_port} sys_ddr3_cntrl.ctrl_amm_0
+  set_connection_parameter_value ${m_port}/sys_ddr3_cntrl.ctrl_amm_0  baseAddress {0x0}
+}
+
+# common dma interfaces
+
+add_instance sys_dma_clk clock_source 16.0
+add_connection sys_ddr3_cntrl.emif_usr_clk sys_dma_clk.clk_in
+add_connection sys_ddr3_cntrl.emif_usr_reset_n sys_dma_clk.clk_in_reset
 
 # ethernet
 
@@ -172,18 +196,8 @@ add_connection sys_clk.clk sys_ethernet.transmit_clock_connection
 add_connection sys_clk.clk sys_ethernet_dma_rx.clock
 add_connection sys_clk.clk sys_ethernet_dma_tx.clock
 add_connection sys_clk.clk sys_ethernet_reset.clk
-add_connection sys_cpu.data_master sys_ethernet.control_port
-add_connection sys_cpu.data_master sys_ethernet_dma_rx.csr
-add_connection sys_cpu.data_master sys_ethernet_dma_rx.response
-add_connection sys_cpu.data_master sys_ethernet_dma_rx.descriptor_slave
-add_connection sys_cpu.data_master sys_ethernet_dma_tx.csr
-add_connection sys_cpu.data_master sys_ethernet_dma_tx.descriptor_slave
-add_connection sys_cpu.irq sys_ethernet_dma_rx.csr_irq
-add_connection sys_cpu.irq sys_ethernet_dma_tx.csr_irq
 add_connection sys_ethernet.receive sys_ethernet_dma_rx.st_sink
 add_connection sys_ethernet_dma_tx.st_source sys_ethernet.transmit
-add_connection sys_ethernet_dma_rx.mm_write sys_ddr3_cntrl.ctrl_amm_0
-add_connection sys_ethernet_dma_tx.mm_read sys_ddr3_cntrl.ctrl_amm_0
 add_interface sys_ethernet_reset reset source
 add_interface sys_ethernet_ref_clk clock sink
 add_interface sys_ethernet_mdio conduit end
@@ -198,40 +212,29 @@ set_interface_property sys_ethernet_sgmii EXPORT_OF sys_ethernet.serial_connecti
 
 add_instance sys_id altera_avalon_sysid_qsys 16.0
 set_instance_parameter_value sys_id {id} {182193580}
-
 add_connection sys_clk.clk_reset sys_id.reset
 add_connection sys_clk.clk sys_id.clk
-add_connection sys_cpu.data_master sys_id.control_slave
 
 # timer-1
 
 add_instance sys_timer_1 altera_avalon_timer 16.0
 set_instance_parameter_value sys_timer_1 {counterSize} {32}
-
 add_connection sys_clk.clk_reset sys_timer_1.reset
 add_connection sys_clk.clk sys_timer_1.clk
-add_connection sys_cpu.data_master sys_timer_1.s1
-add_connection sys_cpu.irq sys_timer_1.irq
 
 # timer-2
 
 add_instance sys_timer_2 altera_avalon_timer 16.0
 set_instance_parameter_value sys_timer_2 {counterSize} {32}
-
 add_connection sys_clk.clk_reset sys_timer_2.reset
 add_connection sys_clk.clk sys_timer_2.clk
-add_connection sys_cpu.data_master sys_timer_2.s1
-add_connection sys_cpu.irq sys_timer_2.irq
 
 # uart
 
 add_instance sys_uart altera_avalon_jtag_uart 16.0
 set_instance_parameter_value sys_uart {allowMultipleConnections} {0}
-
 add_connection sys_clk.clk_reset sys_uart.reset
 add_connection sys_clk.clk sys_uart.clk
-add_connection sys_cpu.data_master sys_uart.avalon_jtag_slave
-add_connection sys_cpu.irq sys_uart.irq
 
 # gpio-bd
 
@@ -239,13 +242,9 @@ add_instance sys_gpio_bd altera_avalon_pio 16.0
 set_instance_parameter_value sys_gpio_bd {direction} {InOut}
 set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
 set_instance_parameter_value sys_gpio_bd {width} {32}
-
 add_connection sys_clk.clk_reset sys_gpio_bd.reset
 add_connection sys_clk.clk sys_gpio_bd.clk
-add_connection sys_cpu.data_master sys_gpio_bd.s1
-add_connection sys_cpu.irq sys_gpio_bd.irq
 add_interface sys_gpio_bd conduit end
-
 set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
 
 # gpio-in
@@ -254,13 +253,9 @@ add_instance sys_gpio_in altera_avalon_pio 16.0
 set_instance_parameter_value sys_gpio_in {direction} {Input}
 set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
 set_instance_parameter_value sys_gpio_in {width} {32}
-
 add_connection sys_clk.clk_reset sys_gpio_in.reset
 add_connection sys_clk.clk sys_gpio_in.clk
-add_connection sys_cpu.data_master sys_gpio_in.s1
-add_connection sys_cpu.irq sys_gpio_in.irq
 add_interface sys_gpio_in conduit end
-
 set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
 
 # gpio-out
@@ -269,12 +264,9 @@ add_instance sys_gpio_out altera_avalon_pio 16.0
 set_instance_parameter_value sys_gpio_out {direction} {Output}
 set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
 set_instance_parameter_value sys_gpio_out {width} {32}
-
 add_connection sys_clk.clk_reset sys_gpio_out.reset
 add_connection sys_clk.clk sys_gpio_out.clk
-add_connection sys_cpu.data_master sys_gpio_out.s1
 add_interface sys_gpio_out conduit end
-
 set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
 
 # spi
@@ -286,51 +278,44 @@ set_instance_parameter_value sys_spi {dataWidth} {8}
 set_instance_parameter_value sys_spi {masterSPI} {1}
 set_instance_parameter_value sys_spi {numberOfSlaves} {8}
 set_instance_parameter_value sys_spi {targetClockRate} {128000.0}
-
 add_connection sys_clk.clk_reset sys_spi.reset
 add_connection sys_clk.clk sys_spi.clk
-add_connection sys_cpu.data_master sys_spi.spi_control_port
-add_connection sys_cpu.irq sys_spi.irq
 add_interface sys_spi conduit end
-
 set_interface_property sys_spi EXPORT_OF sys_spi.external
 
-# addresses
+# base-addresses
 
-set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.ctrl_amm_0                baseAddress {0x00000000}
-set_connection_parameter_value sys_cpu.data_master/sys_int_mem.s1                           baseAddress {0x10140000}
-set_connection_parameter_value sys_cpu.data_master/sys_cpu.debug_mem_slave                  baseAddress {0x10180800}
-set_connection_parameter_value sys_cpu.data_master/sys_uart.avalon_jtag_slave               baseAddress {0x101814f0}
-set_connection_parameter_value sys_cpu.data_master/sys_ethernet.control_port                baseAddress {0x10181000}
-set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.csr                  baseAddress {0x101814a0}
-set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.response             baseAddress {0x101814e0}
-set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.descriptor_slave     baseAddress {0x10181440}
-set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_tx.csr                  baseAddress {0x10181480}
-set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_tx.descriptor_slave     baseAddress {0x10181460}
-set_connection_parameter_value sys_cpu.data_master/sys_spi.spi_control_port                 baseAddress {0x10181400}
-set_connection_parameter_value sys_cpu.data_master/sys_gpio_out.s1                          baseAddress {0x10181500}
-set_connection_parameter_value sys_cpu.data_master/sys_gpio_in.s1                           baseAddress {0x101814c0}
-set_connection_parameter_value sys_cpu.data_master/sys_gpio_bd.s1                           baseAddress {0x101814d0}
-set_connection_parameter_value sys_cpu.data_master/sys_timer_2.s1                           baseAddress {0x10181520}
-set_connection_parameter_value sys_cpu.data_master/sys_timer_1.s1                           baseAddress {0x10181420}
-set_connection_parameter_value sys_cpu.data_master/sys_id.control_slave                     baseAddress {0x101814e8}
-set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
-set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave           baseAddress {0x10180800}
-set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1                    baseAddress {0x10140000}
-set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2  baseAddress {0x10200000}
-set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1         baseAddress {0x10200000}
-set_connection_parameter_value sys_ethernet_dma_tx.mm_read/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
-set_connection_parameter_value sys_ethernet_dma_rx.mm_write/sys_ddr3_cntrl.ctrl_amm_0       baseAddress {0x00000000}
+ad_cpu_interconnect 0x00180800 sys_cpu.debug_mem_slave
+ad_cpu_interconnect 0x00140000 sys_int_mem.s1
+ad_cpu_interconnect 0x00181000 sys_ethernet.control_port
+ad_cpu_interconnect 0x001814a0 sys_ethernet_dma_rx.csr
+ad_cpu_interconnect 0x001814e0 sys_ethernet_dma_rx.response
+ad_cpu_interconnect 0x00181440 sys_ethernet_dma_rx.descriptor_slave
+ad_cpu_interconnect 0x00181480 sys_ethernet_dma_tx.csr
+ad_cpu_interconnect 0x00181460 sys_ethernet_dma_tx.descriptor_slave
+ad_cpu_interconnect 0x001814e8 sys_id.control_slave
+ad_cpu_interconnect 0x00181420 sys_timer_1.s1
+ad_cpu_interconnect 0x00181520 sys_timer_2.s1
+ad_cpu_interconnect 0x001814f0 sys_uart.avalon_jtag_slave
+ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1
+ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1
+ad_cpu_interconnect 0x00181500 sys_gpio_out.s1
+ad_cpu_interconnect 0x00181400 sys_spi.spi_control_port
 
-set_connection_parameter_value sys_cpu.irq/sys_ethernet_dma_rx.csr_irq irqNumber  {0}
-set_connection_parameter_value sys_cpu.irq/sys_ethernet_dma_tx.csr_irq irqNumber  {1}
-set_connection_parameter_value sys_cpu.irq/sys_uart.irq irqNumber                 {2}
-set_connection_parameter_value sys_cpu.irq/sys_timer_2.irq irqNumber              {3}
-set_connection_parameter_value sys_cpu.irq/sys_timer_1.irq irqNumber              {4}
-set_connection_parameter_value sys_cpu.irq/sys_gpio_in.irq irqNumber              {5}
-set_connection_parameter_value sys_cpu.irq/sys_gpio_bd.irq irqNumber              {6}
-set_connection_parameter_value sys_cpu.irq/sys_spi.irq irqNumber                  {7}
+# dma interconnects
+
+ad_dma_interconnect sys_ethernet_dma_tx.mm_read
+ad_dma_interconnect sys_ethernet_dma_rx.mm_write
 
 # interrupts
 
+ad_cpu_interrupt 0 sys_ethernet_dma_rx.csr_irq
+ad_cpu_interrupt 1 sys_ethernet_dma_tx.csr_irq
+ad_cpu_interrupt 2 sys_uart.irq
+ad_cpu_interrupt 3 sys_timer_2.irq
+ad_cpu_interrupt 4 sys_timer_1.irq
+ad_cpu_interrupt 5 sys_gpio_in.irq
+ad_cpu_interrupt 6 sys_gpio_bd.irq
+ad_cpu_interrupt 7 sys_spi.irq
+
 
diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl
index 935e9bc0a..9e725a863 100755
--- a/projects/common/a10soc/a10soc_system_qsys.tcl
+++ b/projects/common/a10soc/a10soc_system_qsys.tcl
@@ -189,6 +189,12 @@ proc ad_dma_interconnect {m_port} {
   set_connection_parameter_value ${m_port}/sys_hps.f2sdram0_data baseAddress {0x0}
 }
 
+# common dma interfaces
+
+add_instance sys_dma_clk clock_source 16.0
+add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
+add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
+
 # gpio-in
 
 add_instance sys_gpio_in altera_avalon_pio 16.0
@@ -239,9 +245,3 @@ ad_cpu_interconnect 0x00000040 sys_spi.spi_control_port
 ad_cpu_interrupt 5 sys_gpio_in.irq
 ad_cpu_interrupt 7 sys_spi.irq
 
-# common dma interfaces
-
-add_instance sys_dma_clk clock_source 16.0
-add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
-add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
-

From 8107514ddef7bb6aa181c70aef9ae4d3f98fcfb6 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 27 Oct 2016 09:40:45 -0400
Subject: [PATCH 644/972] altera/common- ad_serdes_clk

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 229 ++++++++------------
 library/altera/common/ad_serdes_clk.v       | 119 +++++-----
 2 files changed, 158 insertions(+), 190 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index 6d88be1fd..a1cebcaa5 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -38,63 +38,12 @@ set_parameter_property CLKIN_FREQUENCY UNITS None
 set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
 set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
 
-# these paramteres are needed just because of cross-platform requirments
-# are NOT used in the core
-
 add_parameter DEVICE_FAMILY STRING
 set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
 set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
 set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
 set_parameter_property DEVICE_FAMILY ENABLED false
 
-add_parameter DEVICE_TYPE INTEGER 0
-set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
-set_parameter_property DEVICE_TYPE TYPE INTEGER
-set_parameter_property DEVICE_TYPE UNITS None
-set_parameter_property DEVICE_TYPE HDL_PARAMETER false
-
-add_parameter MMCM_OR_BUFR_N INTEGER 0
-set_parameter_property MMCM_OR_BUFR_N DEFAULT_VALUE 0
-set_parameter_property MMCM_OR_BUFR_N DISPLAY_NAME MMCM_OR_BUFIO_N
-set_parameter_property MMCM_OR_BUFR_N TYPE INTEGER
-set_parameter_property MMCM_OR_BUFR_N UNITS None
-set_parameter_property MMCM_OR_BUFR_N HDL_PARAMETER false
-
-add_parameter MMCM_CLKIN_PERIOD FLOAT 0
-set_parameter_property MMCM_CLKIN_PERIOD DEFAULT_VALUE 1.667
-set_parameter_property MMCM_CLKIN_PERIOD DISPLAY_NAME MMCM_CLKIN_PERIOD
-set_parameter_property MMCM_CLKIN_PERIOD TYPE INTEGER
-set_parameter_property MMCM_CLKIN_PERIOD UNITS None
-set_parameter_property MMCM_CLKIN_PERIOD HDL_PARAMETER false
-
-add_parameter MMCM_VCO_DIV INTEGER 0
-set_parameter_property MMCM_VCO_DIV DEFAULT_VALUE 2
-set_parameter_property MMCM_VCO_DIV DISPLAY_NAME MMCM_VCO_DIV
-set_parameter_property MMCM_VCO_DIV TYPE INTEGER
-set_parameter_property MMCM_VCO_DIV UNITS None
-set_parameter_property MMCM_VCO_DIV HDL_PARAMETER false
-
-add_parameter MMCM_VCO_MUL INTEGER 0
-set_parameter_property MMCM_VCO_MUL DEFAULT_VALUE 4
-set_parameter_property MMCM_VCO_MUL DISPLAY_NAME MMCM_VCO_MUL
-set_parameter_property MMCM_VCO_MUL TYPE INTEGER
-set_parameter_property MMCM_VCO_MUL UNITS None
-set_parameter_property MMCM_VCO_MUL HDL_PARAMETER false
-
-add_parameter MMCM_CLK0_DIV INTEGER 0
-set_parameter_property MMCM_CLK0_DIV DEFAULT_VALUE 2
-set_parameter_property MMCM_CLK0_DIV DISPLAY_NAME MMCM_CLK0_DIV
-set_parameter_property MMCM_CLK0_DIV TYPE INTEGER
-set_parameter_property MMCM_CLK0_DIV UNITS None
-set_parameter_property MMCM_CLK0_DIV HDL_PARAMETER false
-
-add_parameter MMCM_CLK1_DIV INTEGER 0
-set_parameter_property MMCM_CLK1_DIV DEFAULT_VALUE 8
-set_parameter_property MMCM_CLK1_DIV DISPLAY_NAME MMCM_CLK1_DIV
-set_parameter_property MMCM_CLK1_DIV TYPE INTEGER
-set_parameter_property MMCM_CLK1_DIV UNITS None
-set_parameter_property MMCM_CLK1_DIV HDL_PARAMETER false
-
 proc p_alt_serdes {} {
 
   set m_mode [get_parameter_value "MODE"]
@@ -105,6 +54,7 @@ proc p_alt_serdes {} {
 
   set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
   set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
+
   set m_ls_phase 22.5
   set m_ld_phase 315.0
   set m_ld_duty_cycle 12.5
@@ -114,98 +64,54 @@ proc p_alt_serdes {} {
     set m_ld_duty_cycle 25.0
   }
 
-  if {$m_mode == "CLK"} {
+  ## arria 10, serdes clock, data-in and data-out
 
-    if {$m_device_family == "Arria 10"} {
-      add_instance alt_serdes_pll altera_iopll
-      set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
-      set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
-      set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
-      set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
-      set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
-      set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
-      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
-      set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
-      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
-      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
-      set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
-      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
-      set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
-      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
-      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
-      set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
-      add_interface rst reset sink
-      set_interface_property rst EXPORT_OF alt_serdes_pll.reset
-      add_interface ref_clk clock sink
-      set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
-      add_interface locked conduit end
-      set_interface_property locked EXPORT_OF alt_serdes_pll.locked
-      add_interface hs_phase conduit end
-      set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
-      add_interface hs_clk conduit end
-      set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
-      add_interface loaden conduit end
-      set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
-      add_interface ls_clk clock source
-      set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
+  if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} {
 
-      add_instance alt_serdes_pll_reconfig altera_pll_reconfig
-      add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
-      add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
-      add_interface drp_clk clock sink
-      set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
-      add_interface drp_rst reset sink
-      set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
-      add_interface pll_reconfig avalon slave
-      set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
-    }
+    add_instance alt_serdes_pll altera_iopll
+    set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
+    set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
+    set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
+    set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
+    set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
+    set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
+    set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
+    add_interface rst reset sink
+    set_interface_property rst EXPORT_OF alt_serdes_pll.reset
+    add_interface ref_clk clock sink
+    set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
+    add_interface locked conduit end
+    set_interface_property locked EXPORT_OF alt_serdes_pll.locked
+    add_interface hs_phase conduit end
+    set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
+    add_interface hs_clk conduit end
+    set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
+    add_interface loaden conduit end
+    set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
+    add_interface ls_clk clock source
+    set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
 
-    if {$m_device_family == "Cyclone V"} {
-      add_instance alt_serdes_pll altera_pll
-      set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
-      set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
-      set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
-      set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3}
-      set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
-      set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
-      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
-      set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
-      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
-      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
-      set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
-      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
-      set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
-      set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
-      set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
-      set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
-      add_interface rst reset sink
-      set_interface_property rst EXPORT_OF alt_serdes_pll.reset
-      add_interface ref_clk clock sink
-      set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
-      add_interface locked conduit end
-      set_interface_property locked EXPORT_OF alt_serdes_pll.locked
-      add_interface hs_phase conduit end
-      set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
-      add_interface hs_clk clock source
-      set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0
-      add_interface loaden clock source
-      set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1
-      add_interface ls_clk clock source
-      set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
-
-      add_instance alt_serdes_pll_reconfig altera_pll_reconfig
-      add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
-      add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
-      add_interface drp_clk clock sink
-      set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
-      add_interface drp_rst reset sink
-      set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
-      add_interface pll_reconfig avalon slave
-      set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
-    }
+    add_instance alt_serdes_pll_reconfig altera_pll_reconfig
+    add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
+    add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
+    add_interface drp_clk clock sink
+    set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
+    add_interface drp_rst reset sink
+    set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
+    add_interface pll_reconfig avalon slave
+    set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
   }
 
-  if {$m_mode == "IN"} {
+  if {($m_mode == "IN") && ($m_device_family == "Arria 10")} {
 
     add_instance alt_serdes_in altera_lvds
     set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO}
@@ -233,7 +139,7 @@ proc p_alt_serdes {} {
     set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked
   }
 
-  if {$m_mode == "OUT"} {
+  if {($m_mode == "OUT") && ($m_device_family == "Arria 10")} {
 
     add_instance alt_serdes_out altera_lvds
     set_instance_parameter_value alt_serdes_out {MODE} {TX}
@@ -256,4 +162,49 @@ proc p_alt_serdes {} {
     add_interface data_s conduit end
     set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
   }
+
+  ## cyclone v, serdes clock, data-in and data-out
+
+  if {($m_mode == "CLK") && ($m_device_family == "Cyclone V")} {
+
+    add_instance alt_serdes_pll altera_pll
+    set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
+    set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
+    set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
+    set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3}
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
+    set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
+    set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
+    set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
+    set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
+    set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
+    add_interface rst reset sink
+    set_interface_property rst EXPORT_OF alt_serdes_pll.reset
+    add_interface ref_clk clock sink
+    set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
+    add_interface locked conduit end
+    set_interface_property locked EXPORT_OF alt_serdes_pll.locked
+    add_interface hs_clk clock source
+    set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0
+    add_interface loaden clock source
+    set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1
+    add_interface ls_clk clock source
+    set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
+
+    add_instance alt_serdes_pll_reconfig altera_pll_reconfig
+    add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
+    add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
+    add_interface drp_clk clock sink
+    set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
+    add_interface drp_rst reset sink
+    set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
+    add_interface pll_reconfig avalon slave
+    set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
+  }
 }
+
diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
index 48ae32999..0761bf5f7 100644
--- a/library/altera/common/ad_serdes_clk.v
+++ b/library/altera/common/ad_serdes_clk.v
@@ -35,21 +35,30 @@
 // ***************************************************************************
 // ***************************************************************************
 // serial data output interface: serdes(x8)
+// do NOT use this module AS IT IS, the sub modules must be generated inside _hw.tcl file.
+// replace __*__ names with the component names
 
 `timescale 1ps/1ps
 
-module ad_serdes_clk #(
+module __ad_serdes_clk__ #(
 
   // parameters
 
-	parameter DEVICE_TYPE = 0 ) (
+  parameter       DEVICE_TYPE = 0,
+  parameter       DDR_OR_SDR_N = 1,
+  parameter       SERDES_FACTOR = 8,
+  parameter       MMCM_OR_BUFR_N = 1,
+  parameter       MMCM_CLKIN_PERIOD  = 1.667,
+  parameter       MMCM_VCO_DIV  = 6,
+  parameter       MMCM_VCO_MUL = 12.000,
+  parameter       MMCM_CLK0_DIV = 2.000,
+  parameter       MMCM_CLK1_DIV = 6) (
 
   // clock and divided clock
 
   input           rst,
   input           clk_in_p,
   input           clk_in_n,
-
   output          clk,
   output          div_clk,
   output          out_clk,
@@ -70,7 +79,8 @@ module ad_serdes_clk #(
 
   // local parameter
 
-  localparam C5SOC = 1;
+  localparam ARRIA10 = 0;
+  localparam CYCLONE5 = 1;
 
   // internal registers
 
@@ -85,12 +95,13 @@ module ad_serdes_clk #(
   reg             up_drp_locked_int = 'd0;
 
   // internal signals
+
   wire            up_drp_reset;
   wire    [31:0]  up_drp_rdata_int_s;
   wire            up_drp_busy_int_s;
   wire            up_drp_locked_int_s;
-  wire            buf_loaden;
-  wire            buf_lvdsclk;
+  wire            loaden_s;
+  wire            clk_s;
 
   // defaults
 
@@ -145,52 +156,58 @@ module ad_serdes_clk #(
   end
 
   generate
-    if (DEVICE_TYPE == C5SOC) begin
-      alt_serdes_clk_core i_core (
-        .rst_reset (rst),
-        .ref_clk_clk (clk_in_p),
-        .locked_export (up_drp_locked_int_s),
-        .hs_phase_phout (phase),
-        .hs_clk_clk (buf_lvdsclk),
-        .loaden_clk (buf_loaden),
-        .ls_clk_clk (div_clk),
-        .drp_clk_clk (up_clk),
-        .drp_rst_reset (up_drp_reset),
-        .pll_reconfig_waitrequest (up_drp_busy_int_s),
-        .pll_reconfig_read (up_drp_rd_int),
-        .pll_reconfig_write (up_drp_wr_int),
-        .pll_reconfig_readdata (up_drp_rdata_int_s),
-        .pll_reconfig_address (up_drp_addr_int),
-        .pll_reconfig_writedata (up_drp_wdata_int));
-
-      // clock buffer
-      cyclonev_pll_lvds_output #(
-        .pll_loaden_enable_disable("true"),
-        .pll_lvdsclk_enable_disable("true"))
-      cyclonev_pll_lvds_output_inst (
-        .ccout({buf_loaden, buf_lvdsclk}),
-        .loaden(loaden),
-        .lvdsclk(clk));
-
-    end else begin
-      alt_serdes_clk_core i_core (
-        .rst_reset (rst),
-        .ref_clk_clk (clk_in_p),
-        .locked_export (up_drp_locked_int_s),
-        .hs_phase_phout (phase),
-        .hs_clk_lvds_clk (clk),
-        .loaden_loaden (loaden),
-        .ls_clk_clk (div_clk),
-        .drp_clk_clk (up_clk),
-        .drp_rst_reset (up_drp_reset),
-        .pll_reconfig_waitrequest (up_drp_busy_int_s),
-        .pll_reconfig_read (up_drp_rd_int),
-        .pll_reconfig_write (up_drp_wr_int),
-        .pll_reconfig_readdata (up_drp_rdata_int_s),
-        .pll_reconfig_address (up_drp_addr_int),
-        .pll_reconfig_writedata (up_drp_wdata_int));
-    end
+  if (DEVICE_TYPE == ARRIA10) begin
+  __alt_serdes_clk_core__ i_core (
+    .rst_reset (rst),
+    .ref_clk_clk (clk_in_p),
+    .locked_export (up_drp_locked_int_s),
+    .hs_phase_phout (phase),
+    .hs_clk_lvds_clk (clk),
+    .loaden_loaden (loaden),
+    .ls_clk_clk (div_clk),
+    .drp_clk_clk (up_clk),
+    .drp_rst_reset (up_drp_reset),
+    .pll_reconfig_waitrequest (up_drp_busy_int_s),
+    .pll_reconfig_read (up_drp_rd_int),
+    .pll_reconfig_write (up_drp_wr_int),
+    .pll_reconfig_readdata (up_drp_rdata_int_s),
+    .pll_reconfig_address (up_drp_addr_int),
+    .pll_reconfig_writedata (up_drp_wdata_int));
+  end
   endgenerate
+
+  generate
+  if (DEVICE_TYPE == CYCLONE5) begin
+
+  assign phase = 8'd0;
+
+  __alt_serdes_clk_core__ i_core (
+    .rst_reset (rst),
+    .ref_clk_clk (clk_in_p),
+    .locked_export (up_drp_locked_int_s),
+    .hs_clk_clk (clk_s),
+    .loaden_clk (loaden_s),
+    .ls_clk_clk (div_clk),
+    .drp_clk_clk (up_clk),
+    .drp_rst_reset (up_drp_reset),
+    .pll_reconfig_waitrequest (up_drp_busy_int_s),
+    .pll_reconfig_read (up_drp_rd_int),
+    .pll_reconfig_write (up_drp_wr_int),
+    .pll_reconfig_readdata (up_drp_rdata_int_s),
+    .pll_reconfig_address (up_drp_addr_int),
+    .pll_reconfig_writedata (up_drp_wdata_int));
+
+  cyclonev_pll_lvds_output #(
+    .pll_loaden_enable_disable ("true"),
+    .pll_lvdsclk_enable_disable ("true"))
+  i_clk_buf (
+    .ccout ({loaden_s, clk_s}),
+    .loaden (loaden),
+    .lvdsclk (clk));
+
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************

From 30314e44920fde5e4b489ade520dc667ea4178da Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 27 Oct 2016 19:31:50 +0300
Subject: [PATCH 645/972] library: Added util_fir_int and util_fir_dec
 interpolation/decimation filters

---
 library/Makefile                         |   4 +
 library/util_fir_dec/Makefile            |  46 ++++++++
 library/util_fir_dec/coefile_dec.coe     | 134 +++++++++++++++++++++++
 library/util_fir_dec/util_fir_dec.v      |  73 ++++++++++++
 library/util_fir_dec/util_fir_dec_ip.tcl |  39 +++++++
 library/util_fir_int/Makefile            |  46 ++++++++
 library/util_fir_int/coefile_int.coe     | 134 +++++++++++++++++++++++
 library/util_fir_int/util_fir_int.v      |  70 ++++++++++++
 library/util_fir_int/util_fir_int_ip.tcl |  40 +++++++
 9 files changed, 586 insertions(+)
 create mode 100644 library/util_fir_dec/Makefile
 create mode 100644 library/util_fir_dec/coefile_dec.coe
 create mode 100644 library/util_fir_dec/util_fir_dec.v
 create mode 100644 library/util_fir_dec/util_fir_dec_ip.tcl
 create mode 100644 library/util_fir_int/Makefile
 create mode 100644 library/util_fir_int/coefile_int.coe
 create mode 100644 library/util_fir_int/util_fir_int.v
 create mode 100644 library/util_fir_int/util_fir_int_ip.tcl

diff --git a/library/Makefile b/library/Makefile
index ae0d5eb7a..775c86da1 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -60,6 +60,8 @@ clean:
 	make -C util_clkdiv clean
 	make -C util_cpack clean
 	make -C util_dacfifo clean
+	make -C util_fir_dec clean
+	make -C util_fir_int clean
 	make -C util_gmii_to_rgmii clean
 	make -C util_gtlb clean
 	make -C util_i2c_mixer clean
@@ -133,6 +135,8 @@ lib:
 	-make -C util_clkdiv
 	-make -C util_cpack
 	-make -C util_dacfifo
+	-make -C util_fir_dec
+	-make -C util_fir_int
 	-make -C util_gmii_to_rgmii
 	-make -C util_gtlb
 	-make -C util_i2c_mixer
diff --git a/library/util_fir_dec/Makefile b/library/util_fir_dec/Makefile
new file mode 100644
index 000000000..b6ba6e8f6
--- /dev/null
+++ b/library/util_fir_dec/Makefile
@@ -0,0 +1,46 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := util_fir_dec_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += util_fir_dec.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: util_fir_dec.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+util_fir_dec.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) util_fir_dec_ip.tcl  >> util_fir_dec_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/util_fir_dec/coefile_dec.coe b/library/util_fir_dec/coefile_dec.coe
new file mode 100644
index 000000000..06a603964
--- /dev/null
+++ b/library/util_fir_dec/coefile_dec.coe
@@ -0,0 +1,134 @@
+; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
+; Generated by MATLAB(R) 9.0 and the DSP System Toolbox 9.2.
+; Generated on: 24-Oct-2016 14:07:18
+Radix = 10; 
+Coefficient_Width = 16; 
+CoefData =     0,
+   -1,
+   -2,
+   -4,
+   -6,
+   -8,
+   -8,
+   -5,
+    0,
+    8,
+   18,
+   29,
+   37,
+   41,
+   37,
+   23,
+    0,
+  -31,
+  -67,
+ -100,
+ -124,
+ -130,
+ -113,
+  -69,
+    0,
+   87,
+  181,
+  263,
+  318,
+  326,
+  277,
+  166,
+    0,
+ -202,
+ -410,
+ -589,
+ -700,
+ -709,
+ -594,
+ -352,
+    0,
+  420,
+  848,
+ 1211,
+ 1432,
+ 1446,
+ 1210,
+  717,
+    0,
+ -863,
+-1756,
+-2535,
+-3043,
+-3133,
+-2690,
+-1646,
+    0,
+ 2180,
+ 4757,
+ 7534,
+10278,
+12743,
+14697,
+15951,
+16384,
+15951,
+14697,
+12743,
+10278,
+ 7534,
+ 4757,
+ 2180,
+    0,
+-1646,
+-2690,
+-3133,
+-3043,
+-2535,
+-1756,
+ -863,
+    0,
+  717,
+ 1210,
+ 1446,
+ 1432,
+ 1211,
+  848,
+  420,
+    0,
+ -352,
+ -594,
+ -709,
+ -700,
+ -589,
+ -410,
+ -202,
+    0,
+  166,
+  277,
+  326,
+  318,
+  263,
+  181,
+   87,
+    0,
+  -69,
+ -113,
+ -130,
+ -124,
+ -100,
+  -67,
+  -31,
+    0,
+   23,
+   37,
+   41,
+   37,
+   29,
+   18,
+    8,
+    0,
+   -5,
+   -8,
+   -8,
+   -6,
+   -4,
+   -2,
+   -1,
+    0;
diff --git a/library/util_fir_dec/util_fir_dec.v b/library/util_fir_dec/util_fir_dec.v
new file mode 100644
index 000000000..f4e367960
--- /dev/null
+++ b/library/util_fir_dec/util_fir_dec.v
@@ -0,0 +1,73 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// This IP allows the decimation by 8 of the data from the input channels
+// 0 and 1. The decimation filter is implemented using a fir_compiler IP from
+// Xilinx.
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_fir_dec (
+  input               aclk,
+  input               s_axis_data_tvalid,
+  output              s_axis_data_tready,
+  input       [15:0]  channel_0,
+  input       [15:0]  channel_1,
+  input               decimate,
+  output              m_axis_data_tvalid,
+  output      [31:0]  m_axis_data_tdata);
+
+  wire [31:0] s_axis_data_tdata;
+
+  wire        m_axis_data_tvalid_s;
+  wire [31:0] m_axis_data_tdata_s;
+
+  assign s_axis_data_tdata = {channel_1, channel_0};
+
+  assign m_axis_data_tvalid = (decimate == 1'b1) ? m_axis_data_tvalid_s : s_axis_data_tvalid;
+  assign m_axis_data_tdata = (decimate == 1'b1) ? m_axis_data_tdata_s : {channel_1, channel_0};
+
+  fir_decim decimator (
+    .aclk(aclk),
+    .s_axis_data_tvalid(s_axis_data_tvalid),
+    .s_axis_data_tready(s_axis_data_tready),
+    .s_axis_data_tdata(s_axis_data_tdata),
+    .m_axis_data_tvalid(m_axis_data_tvalid_s),
+    .m_axis_data_tdata(m_axis_data_tdata_s)
+  );
+
+endmodule  // util_fir_dec
+
diff --git a/library/util_fir_dec/util_fir_dec_ip.tcl b/library/util_fir_dec/util_fir_dec_ip.tcl
new file mode 100644
index 000000000..71dc0ef8c
--- /dev/null
+++ b/library/util_fir_dec/util_fir_dec_ip.tcl
@@ -0,0 +1,39 @@
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create util_fir_dec
+
+set fir_decim [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_decim]
+ set_property -dict [ list \
+CONFIG.Clock_Frequency {128.8} \
+CONFIG.CoefficientSource {COE_File} \
+CONFIG.Coefficient_File {../../../../coefile_dec.coe} \
+CONFIG.Coefficient_Fractional_Bits {0} \
+CONFIG.Coefficient_Sets {1} \
+CONFIG.Coefficient_Sign {Signed} \
+CONFIG.Coefficient_Structure {Inferred} \
+CONFIG.Coefficient_Width {16} \
+CONFIG.ColumnConfig {5} \
+CONFIG.Decimation_Rate {8} \
+CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
+CONFIG.Filter_Type {Decimation} \
+CONFIG.Interpolation_Rate {1} \
+CONFIG.Number_Channels {1} \
+CONFIG.Number_Paths {2} \
+CONFIG.Output_Rounding_Mode {Truncate_LSBs} \
+CONFIG.Output_Width {16} \
+CONFIG.Quantization {Integer_Coefficients} \
+CONFIG.RateSpecification {Frequency_Specification} \
+CONFIG.Sample_Frequency {64.4} \
+CONFIG.Zero_Pack_Factor {1} \
+ ] [get_ips fir_decim]
+
+generate_target {all} [get_files util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci]
+
+
+adi_ip_files util_fir_dec [list \
+"util_fir_dec.v" ]
+
+adi_ip_properties_lite util_fir_dec
+
+ipx::save_core [ipx::current_core]
diff --git a/library/util_fir_int/Makefile b/library/util_fir_int/Makefile
new file mode 100644
index 000000000..9bc6768ba
--- /dev/null
+++ b/library/util_fir_int/Makefile
@@ -0,0 +1,46 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := util_fir_int_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += util_fir_int.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: util_fir_int.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+util_fir_int.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) util_fir_int_ip.tcl  >> util_fir_int_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/util_fir_int/coefile_int.coe b/library/util_fir_int/coefile_int.coe
new file mode 100644
index 000000000..10c6cfe27
--- /dev/null
+++ b/library/util_fir_int/coefile_int.coe
@@ -0,0 +1,134 @@
+; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
+; Generated by MATLAB(R) 9.0 and the DSP System Toolbox 9.2.
+; Generated on: 21-Oct-2016 22:25:08
+Radix = 10; 
+Coefficient_Width = 16; 
+CoefData =     0,
+   -1,
+   -2,
+   -4,
+   -6,
+   -8,
+   -8,
+   -5,
+    0,
+    8,
+   18,
+   29,
+   37,
+   41,
+   37,
+   23,
+    0,
+  -31,
+  -67,
+ -100,
+ -124,
+ -130,
+ -113,
+  -69,
+    0,
+   87,
+  181,
+  263,
+  318,
+  326,
+  277,
+  166,
+    0,
+ -202,
+ -410,
+ -589,
+ -700,
+ -709,
+ -594,
+ -352,
+    0,
+  420,
+  848,
+ 1211,
+ 1432,
+ 1446,
+ 1210,
+  717,
+    0,
+ -863,
+-1756,
+-2535,
+-3043,
+-3133,
+-2690,
+-1646,
+    0,
+ 2180,
+ 4757,
+ 7534,
+10278,
+12743,
+14697,
+15951,
+16384,
+15951,
+14697,
+12743,
+10278,
+ 7534,
+ 4757,
+ 2180,
+    0,
+-1646,
+-2690,
+-3133,
+-3043,
+-2535,
+-1756,
+ -863,
+    0,
+  717,
+ 1210,
+ 1446,
+ 1432,
+ 1211,
+  848,
+  420,
+    0,
+ -352,
+ -594,
+ -709,
+ -700,
+ -589,
+ -410,
+ -202,
+    0,
+  166,
+  277,
+  326,
+  318,
+  263,
+  181,
+   87,
+    0,
+  -69,
+ -113,
+ -130,
+ -124,
+ -100,
+  -67,
+  -31,
+    0,
+   23,
+   37,
+   41,
+   37,
+   29,
+   18,
+    8,
+    0,
+   -5,
+   -8,
+   -8,
+   -6,
+   -4,
+   -2,
+   -1,
+    0;
diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v
new file mode 100644
index 000000000..183a41409
--- /dev/null
+++ b/library/util_fir_int/util_fir_int.v
@@ -0,0 +1,70 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// This IP allows the interpolation by 8 of the data from the input
+// The interpolation filter is implemented using a fir_compiler IP from
+// Xilinx.
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_fir_int (
+  input               aclk,
+  input               s_axis_data_tvalid,
+  output              s_axis_data_tready,
+  input       [31:0]  s_axis_data_tdata,
+  output      [15:0]  channel_0,
+  output      [15:0]  channel_1,
+  output              m_axis_data_tvalid,
+  input               interpolate,
+  input               dac_read);
+
+  wire [31:0] m_axis_data_tdata_s;
+  wire        s_axis_data_tready_s;
+
+  assign {channel_1, channel_0} = (interpolate == 1'b1) ? m_axis_data_tdata_s : s_axis_data_tdata;
+  assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_s : dac_read;
+
+  fir_interp interpolator (
+    .aclk(aclk),
+    .s_axis_data_tvalid(s_axis_data_tvalid),
+    .s_axis_data_tready(s_axis_data_tready_s),
+    .s_axis_data_tdata(s_axis_data_tdata),
+    .m_axis_data_tvalid(m_axis_data_tvalid),
+    .m_axis_data_tdata(m_axis_data_tdata_s)
+  );
+
+endmodule  // util_fir_int
+
diff --git a/library/util_fir_int/util_fir_int_ip.tcl b/library/util_fir_int/util_fir_int_ip.tcl
new file mode 100644
index 000000000..f7fa5c528
--- /dev/null
+++ b/library/util_fir_int/util_fir_int_ip.tcl
@@ -0,0 +1,40 @@
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create util_fir_int
+
+set fir_interp [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_interp]
+ set_property -dict [ list \
+CONFIG.Clock_Frequency {128.8} \
+CONFIG.CoefficientSource {COE_File} \
+CONFIG.Coefficient_File {../../../../coefile_int.coe} \
+CONFIG.Coefficient_Fractional_Bits {0} \
+CONFIG.Coefficient_Sets {1} \
+CONFIG.Coefficient_Sign {Signed} \
+CONFIG.Coefficient_Structure {Inferred} \
+CONFIG.Coefficient_Width {16} \
+CONFIG.ColumnConfig {5} \
+CONFIG.Decimation_Rate {1} \
+CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
+CONFIG.Filter_Type {Interpolation} \
+CONFIG.Interpolation_Rate {8} \
+CONFIG.M_DATA_Has_TREADY {false} \
+CONFIG.Number_Channels {1} \
+CONFIG.Number_Paths {2} \
+CONFIG.Output_Rounding_Mode {Truncate_LSBs} \
+CONFIG.Output_Width {16} \
+CONFIG.Quantization {Integer_Coefficients} \
+CONFIG.RateSpecification {Frequency_Specification} \
+CONFIG.Sample_Frequency {8} \
+CONFIG.Zero_Pack_Factor {1} \
+ ] [get_ips fir_interp]
+
+generate_target {all} [get_files util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci]
+
+
+adi_ip_files util_fir_int [list \
+"util_fir_int.v" ]
+
+adi_ip_properties_lite util_fir_int
+
+ipx::save_core [ipx::current_core]

From ac8a6124af72169957a7aca120ab5a4ba959b1e9 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 27 Oct 2016 19:33:28 +0300
Subject: [PATCH 646/972] sdrstk: Added interpolation and decimation filters.
 Removed cpack/upack

---
 projects/sdrstk/system_bd.tcl     | 51 +++++++++++++++----------------
 projects/sdrstk/system_constr.xdc |  4 ++-
 2 files changed, 27 insertions(+), 28 deletions(-)

diff --git a/projects/sdrstk/system_bd.tcl b/projects/sdrstk/system_bd.tcl
index 5ca44c4a5..75981cd4e 100644
--- a/projects/sdrstk/system_bd.tcl
+++ b/projects/sdrstk/system_bd.tcl
@@ -183,23 +183,21 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {32}] $axi_ad9361_dac_dma
 
-set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_dac_upack
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack
+set fir_interpolator [ create_bd_cell -type ip -vlnv analog.com:user:util_fir_int:1.0 fir_interpolator ]
+set interp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 interp_slice ]
 
 set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
-set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}]  $axi_ad9361_adc_dma
 
-set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_adc_pack
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack
+set fir_decimator [ create_bd_cell -type ip -vlnv analog.com:user:util_fir_dec:1.0 fir_decimator ]
+set decim_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 decim_slice ]
 
 # connections
 
@@ -218,29 +216,28 @@ ad_connect  axi_ad9361/tdd_sync GND
 ad_connect  sys_200m_clk axi_ad9361/delay_clk
 ad_connect  axi_ad9361/l_clk axi_ad9361/clk
 
-ad_connect  axi_ad9361/l_clk util_ad9361_adc_pack/adc_clk
-ad_connect  axi_ad9361/rst util_ad9361_adc_pack/adc_rst
-ad_connect  axi_ad9361/adc_enable_i0 util_ad9361_adc_pack/adc_enable_0
-ad_connect  axi_ad9361/adc_valid_i0 util_ad9361_adc_pack/adc_valid_0
-ad_connect  axi_ad9361/adc_data_i0 util_ad9361_adc_pack/adc_data_0
-ad_connect  axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1
-ad_connect  axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1
-ad_connect  axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1
+ad_connect axi_ad9361/l_clk fir_decimator/aclk
+ad_connect axi_ad9361/adc_data_i0 fir_decimator/channel_0
+ad_connect axi_ad9361/adc_data_q0 fir_decimator/channel_1
+ad_connect axi_ad9361/adc_valid_i0 fir_decimator/s_axis_data_tvalid
+ad_connect axi_ad9361_adc_dma/fifo_wr_din fir_decimator/m_axis_data_tdata
+ad_connect axi_ad9361_adc_dma/fifo_wr_en fir_decimator/m_axis_data_tvalid
+ad_connect axi_ad9361/up_adc_gpio_out decim_slice/Din
+ad_connect fir_decimator/decimate decim_slice/Dout
+
+ad_connect axi_ad9361/l_clk fir_interpolator/aclk
+ad_connect axi_ad9361_dac_dma/fifo_rd_dout fir_interpolator/s_axis_data_tdata
+ad_connect axi_ad9361_dac_dma/fifo_rd_valid fir_interpolator/s_axis_data_tvalid
+ad_connect axi_ad9361/dac_valid_i0 fir_interpolator/dac_read
+ad_connect axi_ad9361_dac_dma/fifo_rd_en fir_interpolator/s_axis_data_tready
+ad_connect axi_ad9361/dac_data_i0 fir_interpolator/channel_0
+ad_connect axi_ad9361/dac_data_q0 fir_interpolator/channel_1
+ad_connect axi_ad9361/up_dac_gpio_out interp_slice/Din
+ad_connect fir_interpolator/interpolate interp_slice/Dout
+
 ad_connect  axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk
-ad_connect  util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
-ad_connect  util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
-ad_connect  util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
 ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf
-ad_connect  axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk
-ad_connect  axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0
-ad_connect  axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0
-ad_connect  util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
-ad_connect  axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1
-ad_connect  axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1
-ad_connect  util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
 ad_connect  axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk
-ad_connect  util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
-ad_connect  axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data
 ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
 ad_connect  axi_ad9361/dac_data_i1 GND
 ad_connect  axi_ad9361/dac_data_q1 GND
diff --git a/projects/sdrstk/system_constr.xdc b/projects/sdrstk/system_constr.xdc
index d41a6f328..c7e4264ca 100644
--- a/projects/sdrstk/system_constr.xdc
+++ b/projects/sdrstk/system_constr.xdc
@@ -62,7 +62,7 @@ set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports spi_miso]
 set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports gpio_bd]
 set_property  -dict {PACKAGE_PIN  P8   IOSTANDARD LVCMOS18} [get_ports clk_out]
 
-create_clock -name rx_clk -period  16 [get_ports rx_clk_in]
+create_clock -name rx_clk -period  7.77 [get_ports rx_clk_in]
 
 # probably gone in 2016.4
 
@@ -199,4 +199,6 @@ set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]]
 set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]]
 set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]]
 
+set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/up_adc_gpio_out_int_reg[0]/C}]
+set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/up_dac_gpio_out_int_reg[0]/C}]
 

From d9b756e7ad840eab9ba66302f7517594529b369d Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 28 Oct 2016 15:17:30 +0300
Subject: [PATCH 647/972] util_fir_int: Shifted the output data to the left so
 that the amplitude remains constant

---
 library/util_fir_int/util_fir_int.v      | 2 +-
 library/util_fir_int/util_fir_int_ip.tcl | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v
index 183a41409..47ea8c566 100644
--- a/library/util_fir_int/util_fir_int.v
+++ b/library/util_fir_int/util_fir_int.v
@@ -54,7 +54,7 @@ module util_fir_int (
   wire [31:0] m_axis_data_tdata_s;
   wire        s_axis_data_tready_s;
 
-  assign {channel_1, channel_0} = (interpolate == 1'b1) ? m_axis_data_tdata_s : s_axis_data_tdata;
+  assign {channel_1, channel_0} = (interpolate == 1'b1) ? {m_axis_data_tdata_s[30:16], 1'b0, m_axis_data_tdata_s[14:0], 1'b0} : s_axis_data_tdata;
   assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_s : dac_read;
 
   fir_interp interpolator (
diff --git a/library/util_fir_int/util_fir_int_ip.tcl b/library/util_fir_int/util_fir_int_ip.tcl
index f7fa5c528..1a0fbe32b 100644
--- a/library/util_fir_int/util_fir_int_ip.tcl
+++ b/library/util_fir_int/util_fir_int_ip.tcl
@@ -9,6 +9,7 @@ CONFIG.Clock_Frequency {128.8} \
 CONFIG.CoefficientSource {COE_File} \
 CONFIG.Coefficient_File {../../../../coefile_int.coe} \
 CONFIG.Coefficient_Fractional_Bits {0} \
+CONFIG.Data_Fractional_Bits {15} \
 CONFIG.Coefficient_Sets {1} \
 CONFIG.Coefficient_Sign {Signed} \
 CONFIG.Coefficient_Structure {Inferred} \

From f2e12cc88f814e1f266686fec5992288c81b22e3 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 28 Oct 2016 15:18:36 +0300
Subject: [PATCH 648/972] util_fir_dec: Shifted the output data to the left so
 that the amplitude remains constant

---
 library/util_fir_dec/util_fir_dec.v      | 2 +-
 library/util_fir_dec/util_fir_dec_ip.tcl | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/library/util_fir_dec/util_fir_dec.v b/library/util_fir_dec/util_fir_dec.v
index f4e367960..3a7239957 100644
--- a/library/util_fir_dec/util_fir_dec.v
+++ b/library/util_fir_dec/util_fir_dec.v
@@ -58,7 +58,7 @@ module util_fir_dec (
   assign s_axis_data_tdata = {channel_1, channel_0};
 
   assign m_axis_data_tvalid = (decimate == 1'b1) ? m_axis_data_tvalid_s : s_axis_data_tvalid;
-  assign m_axis_data_tdata = (decimate == 1'b1) ? m_axis_data_tdata_s : {channel_1, channel_0};
+  assign m_axis_data_tdata = (decimate == 1'b1) ? {m_axis_data_tdata_s[30:16], 1'b0, m_axis_data_tdata_s[14:0], 1'b0} : {channel_1, channel_0};
 
   fir_decim decimator (
     .aclk(aclk),
diff --git a/library/util_fir_dec/util_fir_dec_ip.tcl b/library/util_fir_dec/util_fir_dec_ip.tcl
index 71dc0ef8c..76b2709d9 100644
--- a/library/util_fir_dec/util_fir_dec_ip.tcl
+++ b/library/util_fir_dec/util_fir_dec_ip.tcl
@@ -9,6 +9,7 @@ CONFIG.Clock_Frequency {128.8} \
 CONFIG.CoefficientSource {COE_File} \
 CONFIG.Coefficient_File {../../../../coefile_dec.coe} \
 CONFIG.Coefficient_Fractional_Bits {0} \
+CONFIG.Data_Fractional_Bits {15} \
 CONFIG.Coefficient_Sets {1} \
 CONFIG.Coefficient_Sign {Signed} \
 CONFIG.Coefficient_Structure {Inferred} \

From d010f3e6872522048146746785d124a0d4b9702b Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 28 Oct 2016 16:13:52 +0300
Subject: [PATCH 649/972] sdrstk: Update Makefile to remove pack/cpack
 dependancy and add util_fir_dec/util_fir_int dependancy

---
 projects/sdrstk/Makefile | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/projects/sdrstk/Makefile b/projects/sdrstk/Makefile
index b554b4b1f..c13c4de3e 100644
--- a/projects/sdrstk/Makefile
+++ b/projects/sdrstk/Makefile
@@ -15,8 +15,8 @@ M_DEPS += ../scripts/adi_board.tcl
 M_DEPS += ../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../library/util_upack/util_upack.xpr
+M_DEPS += ../../library/util_fir_dec/util_fir_dec.xpr
+M_DEPS += ../../library/util_fir_int/util_fir_int.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -47,8 +47,8 @@ clean:
 clean-all:clean
 	make -C ../../library/axi_ad9361 clean
 	make -C ../../library/axi_dmac clean
-	make -C ../../library/util_cpack clean
-	make -C ../../library/util_upack clean
+	make -C ../../library/util_fir_dec clean
+	make -C ../../library/util_fir_int clean
 
 
 sdrstk.sdk/system_top.hdf: $(M_DEPS)
@@ -59,8 +59,8 @@ sdrstk.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../library/axi_ad9361
 	make -C ../../library/axi_dmac
-	make -C ../../library/util_cpack
-	make -C ../../library/util_upack
+	make -C ../../library/util_fir_dec
+	make -C ../../library/util_fir_int
 
 ####################################################################################
 ####################################################################################

From a9d03af771528570df96d4ba3eb7a5c09fddb487 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 28 Oct 2016 14:09:04 -0400
Subject: [PATCH 650/972] altera- serdes changes

---
 library/altera/common/ad_serdes_clk.v         |   7 +-
 library/altera/common/ad_serdes_in.v          | 263 +++++++++---------
 library/altera/common/ad_serdes_out.v         | 210 +++++++-------
 .../axi_ad9361/altera/axi_ad9361_lvds_if.v    |  18 +-
 library/axi_ad9361/axi_ad9361.v               | 214 ++++++++------
 library/axi_ad9361/axi_ad9361_hw.tcl          | 174 +++++-------
 library/scripts/adi_ip_alt.tcl                |  57 ++++
 7 files changed, 504 insertions(+), 439 deletions(-)

diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
index 0761bf5f7..2ed1b58f5 100644
--- a/library/altera/common/ad_serdes_clk.v
+++ b/library/altera/common/ad_serdes_clk.v
@@ -34,9 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// serial data output interface: serdes(x8)
-// do NOT use this module AS IT IS, the sub modules must be generated inside _hw.tcl file.
-// replace __*__ names with the component names
 
 `timescale 1ps/1ps
 
@@ -157,7 +154,7 @@ module __ad_serdes_clk__ #(
 
   generate
   if (DEVICE_TYPE == ARRIA10) begin
-  __alt_serdes_clk_core__ i_core (
+  __ad_serdes_clk_1__ i_core (
     .rst_reset (rst),
     .ref_clk_clk (clk_in_p),
     .locked_export (up_drp_locked_int_s),
@@ -181,7 +178,7 @@ module __ad_serdes_clk__ #(
 
   assign phase = 8'd0;
 
-  __alt_serdes_clk_core__ i_core (
+  __ad_serdes_clk_1__ i_core (
     .rst_reset (rst),
     .ref_clk_clk (clk_in_p),
     .locked_export (up_drp_locked_int_s),
diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 59183d49a..abadf7bae 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -38,13 +38,16 @@
 
 `timescale 1ps/1ps
 
-module ad_serdes_in #(
+module __ad_serdes_in__ #(
 
   // parameters
 
   parameter   DEVICE_TYPE = 0,
+  parameter   DDR_OR_SDR_N = 0,
   parameter   SERDES_FACTOR = 8,
-  parameter   DATA_WIDTH = 16) (
+  parameter   DATA_WIDTH = 16,
+  parameter   IODELAY_CTRL = 0,
+  parameter   IODELAY_GROUP = "dev_if_delay_group") (
 
   // reset and clocks
 
@@ -83,150 +86,156 @@ module ad_serdes_in #(
 
   // local parameter
 
-  localparam C5SOC = 1;
+  localparam ARRIA10 = 0;
+  localparam CYCLONE5 = 1;
 
   // internal signals
 
   wire    [(DATA_WIDTH-1):0]      delay_locked_s;
-  wire    [(DATA_WIDTH-1):0]      data_out_s[ 7:0];
-  wire    [(DATA_WIDTH-1):0]      data_sel_s[ 7:0];
+  wire    [(DATA_WIDTH-1):0]      data_samples_s[0:(SERDES_FACTOR-1)];
+  wire    [(SERDES_FACTOR-1):0]   data_out_s[0:(DATA_WIDTH-1)];
 
   // assignments
 
   assign up_drdata = 5'd0;
   assign delay_locked = & delay_locked_s;
 
-  assign data_s0 = data_sel_s[0];
-  assign data_s1 = data_sel_s[1];
-  assign data_s2 = data_sel_s[2];
-  assign data_s3 = data_sel_s[3];
-  assign data_s4 = data_sel_s[4];
-  assign data_s5 = data_sel_s[5];
-  assign data_s6 = data_sel_s[6];
-  assign data_s7 = data_sel_s[7];
-
   // instantiations
 
-  genvar l_inst, l_order;
+  genvar n;
+  genvar i;
+
   generate
-  for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
-    for (l_order = 0; l_order < SERDES_FACTOR; l_order = l_order + 1) begin: g_order
-      assign data_sel_s[l_order][l_inst] = data_out_s[8 - SERDES_FACTOR + l_order][l_inst];
-    end
+  if (SERDES_FACTOR == 8) begin
+  assign data_s7 = data_samples_s[7];
+  assign data_s6 = data_samples_s[6];
+  assign data_s5 = data_samples_s[5];
+  assign data_s4 = data_samples_s[4];
+  end else begin
+  assign data_s7 = 'd0;
+  assign data_s6 = 'd0;
+  assign data_s5 = 'd0;
+  assign data_s4 = 'd0;
+  end
+  endgenerate
 
-    if (DEVICE_TYPE == C5SOC ) begin
-      altlvds_rx #(
-        .buffer_implementation ("RAM"),
-        .cds_mode ("UNUSED"),
-        .common_rx_tx_pll ("ON"),
-        .data_align_rollover (4),
-        .data_rate ("500.0 Mbps"),
-        .deserialization_factor (4),
-        .dpa_initial_phase_value (0),
-        .dpll_lock_count (0),
-        .dpll_lock_window (0),
-        .enable_clock_pin_mode ("UNUSED"),
-        .enable_dpa_align_to_rising_edge_only ("OFF"),
-        .enable_dpa_calibration ("ON"),
-        .enable_dpa_fifo ("UNUSED"),
-        .enable_dpa_initial_phase_selection ("OFF"),
-        .enable_dpa_mode ("OFF"),
-        .enable_dpa_pll_calibration ("OFF"),
-        .enable_soft_cdr_mode ("OFF"),
-        .implement_in_les ("OFF"),
-        .inclock_boost (0),
-        .inclock_data_alignment ("EDGE_ALIGNED"),
-        .inclock_period (4000),
-        .inclock_phase_shift (0),
-        .input_data_rate (500),
-        .intended_device_family ("Cyclone V"),
-        .lose_lock_on_one_change ("UNUSED"),
-        .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_in"),
-        .lpm_type ("altlvds_rx"),
-        .number_of_channels (DATA_WIDTH),
-        .outclock_resource ("Regional clock"),
-        .pll_operation_mode ("NORMAL"),
-        .pll_self_reset_on_loss_lock ("UNUSED"),
-        .port_rx_channel_data_align ("PORT_UNUSED"),
-        .port_rx_data_align ("PORT_UNUSED"),
-        .refclk_frequency ("250.000000 MHz"),
-        .registered_data_align_input ("UNUSED"),
-        .registered_output ("ON"),
-        .reset_fifo_at_first_lock ("UNUSED"),
-        .rx_align_data_reg ("RISING_EDGE"),
-        .sim_dpa_is_negative_ppm_drift ("OFF"),
-        .sim_dpa_net_ppm_variation (0),
-        .sim_dpa_output_clock_phase_shift (0),
-        .use_coreclock_input ("OFF"),
-        .use_dpll_rawperror ("OFF"),
-        .use_external_pll ("ON"),
-        .use_no_phase_shift ("ON"),
-        .x_on_bitslip ("ON"),
-        .clk_src_is_pll ("off"))
-      i_altlvds_rx (
-        .rx_inclock (clk),
-        .rx_in (data_in_p[l_inst]),
-        .rx_outclock (),
-        .rx_out ({data_out_s[0][l_inst],
-                  data_out_s[1][l_inst],
-                  data_out_s[2][l_inst],
-                  data_out_s[3][l_inst],
-                  data_out_s[4][l_inst],
-                  data_out_s[5][l_inst],
-                  data_out_s[6][l_inst],
-                  data_out_s[7][l_inst]}),
-        .rx_locked (),
-        .dpa_pll_cal_busy (),
-        .dpa_pll_recal (1'b0),
-        .pll_areset (~locked),
-        .pll_phasecounterselect (),
-        .pll_phasedone (1'b1),
-        .pll_phasestep (),
-        .pll_phaseupdown (),
-        .pll_scanclk (),
-        .rx_cda_max (),
-        .rx_cda_reset ({7{1'b0}}),
-        .rx_channel_data_align ({7{1'b0}}),
-        .rx_coreclk (1'b1),
-        .rx_data_align (1'b0),
-        .rx_data_align_reset (1'b0),
-        .rx_data_reset (1'b0),
-        .rx_deskew (1'b0),
-        .rx_divfwdclk (),
-        .rx_dpa_lock_reset ({7{1'b0}}),
-        .rx_dpa_locked (),
-        .rx_dpaclock (1'b0),
-        .rx_dpll_enable ({7{1'b1}}),
-        .rx_dpll_hold ({7{1'b0}}),
-        .rx_dpll_reset ({7{1'b0}}),
-        .rx_enable (loaden),
-        .rx_fifo_reset ({7{1'b0}}),
-        .rx_pll_enable (1'b1),
-        .rx_readclock (1'b0),
-        .rx_reset ({7{1'b0}}),
-        .rx_syncclock (1'b0));
+  assign data_s3 = data_samples_s[3];
+  assign data_s2 = data_samples_s[2];
+  assign data_s1 = data_samples_s[1];
+  assign data_s0 = data_samples_s[0];
 
-    end else begin
-      alt_serdes_in_core i_core (
-        .clk_export (clk),
-        .div_clk_export (div_clk),
-        .hs_phase_export (phase),
-        .loaden_export (loaden),
-        .locked_export (locked),
-        .data_in_export (data_in_p[l_inst]),
-        .data_s_export ({data_out_s[0][l_inst],
-                         data_out_s[1][l_inst],
-                         data_out_s[2][l_inst],
-                         data_out_s[3][l_inst],
-                         data_out_s[4][l_inst],
-                         data_out_s[5][l_inst],
-                         data_out_s[6][l_inst],
-                         data_out_s[7][l_inst]}),
-        .delay_locked_export (delay_locked_s[l_inst]));
+  generate
+  for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
+    for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
+      assign data_samples_s[i][n] = data_out_s[n][((SERDES_FACTOR-1)-i)];
     end
   end
   endgenerate
 
+  generate
+  for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
+
+  if (DEVICE_TYPE == CYCLONE5) begin
+  altlvds_rx #(
+    .buffer_implementation ("RAM"),
+    .cds_mode ("UNUSED"),
+    .common_rx_tx_pll ("ON"),
+    .data_align_rollover (4),
+    .data_rate ("500.0 Mbps"),
+    .deserialization_factor (4),
+    .dpa_initial_phase_value (0),
+    .dpll_lock_count (0),
+    .dpll_lock_window (0),
+    .enable_clock_pin_mode ("UNUSED"),
+    .enable_dpa_align_to_rising_edge_only ("OFF"),
+    .enable_dpa_calibration ("ON"),
+    .enable_dpa_fifo ("UNUSED"),
+    .enable_dpa_initial_phase_selection ("OFF"),
+    .enable_dpa_mode ("OFF"),
+    .enable_dpa_pll_calibration ("OFF"),
+    .enable_soft_cdr_mode ("OFF"),
+    .implement_in_les ("OFF"),
+    .inclock_boost (0),
+    .inclock_data_alignment ("EDGE_ALIGNED"),
+    .inclock_period (4000),
+    .inclock_phase_shift (0),
+    .input_data_rate (500),
+    .intended_device_family ("Cyclone V"),
+    .lose_lock_on_one_change ("UNUSED"),
+    .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_in"),
+    .lpm_type ("altlvds_rx"),
+    .number_of_channels (DATA_WIDTH),
+    .outclock_resource ("Regional clock"),
+    .pll_operation_mode ("NORMAL"),
+    .pll_self_reset_on_loss_lock ("UNUSED"),
+    .port_rx_channel_data_align ("PORT_UNUSED"),
+    .port_rx_data_align ("PORT_UNUSED"),
+    .refclk_frequency ("250.000000 MHz"),
+    .registered_data_align_input ("UNUSED"),
+    .registered_output ("ON"),
+    .reset_fifo_at_first_lock ("UNUSED"),
+    .rx_align_data_reg ("RISING_EDGE"),
+    .sim_dpa_is_negative_ppm_drift ("OFF"),
+    .sim_dpa_net_ppm_variation (0),
+    .sim_dpa_output_clock_phase_shift (0),
+    .use_coreclock_input ("OFF"),
+    .use_dpll_rawperror ("OFF"),
+    .use_external_pll ("ON"),
+    .use_no_phase_shift ("ON"),
+    .x_on_bitslip ("ON"),
+    .clk_src_is_pll ("off"))
+  i_altlvds_rx (
+    .rx_inclock (clk),
+    .rx_in (data_in_p[n]),
+    .rx_outclock (),
+    .rx_out (data_out_s[n]),
+    .rx_locked (),
+    .dpa_pll_cal_busy (),
+    .dpa_pll_recal (1'b0),
+    .pll_areset (~locked),
+    .pll_phasecounterselect (),
+    .pll_phasedone (1'b1),
+    .pll_phasestep (),
+    .pll_phaseupdown (),
+    .pll_scanclk (),
+    .rx_cda_max (),
+    .rx_cda_reset ({7{1'b0}}),
+    .rx_channel_data_align ({7{1'b0}}),
+    .rx_coreclk (1'b1),
+    .rx_data_align (1'b0),
+    .rx_data_align_reset (1'b0),
+    .rx_data_reset (1'b0),
+    .rx_deskew (1'b0),
+    .rx_divfwdclk (),
+    .rx_dpa_lock_reset ({7{1'b0}}),
+    .rx_dpa_locked (),
+    .rx_dpaclock (1'b0),
+    .rx_dpll_enable ({7{1'b1}}),
+    .rx_dpll_hold ({7{1'b0}}),
+    .rx_dpll_reset ({7{1'b0}}),
+    .rx_enable (loaden),
+    .rx_fifo_reset ({7{1'b0}}),
+    .rx_pll_enable (1'b1),
+    .rx_readclock (1'b0),
+    .rx_reset ({7{1'b0}}),
+    .rx_syncclock (1'b0));
+  end
+
+  if (DEVICE_TYPE == ARRIA10) begin
+  __ad_serdes_in_1__ i_core (
+    .clk_export (clk),
+    .div_clk_export (div_clk),
+    .hs_phase_export (phase),
+    .loaden_export (loaden),
+    .locked_export (locked),
+    .data_in_export (data_in_p[n]),
+    .data_s_export (data_out_s[n]),
+    .delay_locked_export (delay_locked_s[n]));
+  end
+
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index fd5cad778..47298a0dc 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -34,44 +34,45 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// serial data output interface: serdes(x8)
 
 `timescale 1ps/1ps
 
-module ad_serdes_out #(
+module __ad_serdes_out__ #(
 
   parameter   DEVICE_TYPE = 0,
+  parameter   DDR_OR_SDR_N = 1,
   parameter   SERDES_FACTOR = 8,
   parameter   DATA_WIDTH = 16) (
 
   // reset and clocks
 
-  input                       rst,
-  input                       clk,
-  input                       div_clk,
-  input                       loaden,
-
-  // data interface
-
-  input   [(DATA_WIDTH-1):0]  data_s0,
-  input   [(DATA_WIDTH-1):0]  data_s1,
-  input   [(DATA_WIDTH-1):0]  data_s2,
-  input   [(DATA_WIDTH-1):0]  data_s3,
-  input   [(DATA_WIDTH-1):0]  data_s4,
-  input   [(DATA_WIDTH-1):0]  data_s5,
-  input   [(DATA_WIDTH-1):0]  data_s6,
-  input   [(DATA_WIDTH-1):0]  data_s7,
-  output  [(DATA_WIDTH-1):0]  data_out_p,
-  output  [(DATA_WIDTH-1):0]  data_out_n);
+  input                           rst,
+  input                           clk,
+  input                           div_clk,
+  input                           loaden,
+                                  
+  // data interface               
+                                  
+  input   [(DATA_WIDTH-1):0]      data_s0,
+  input   [(DATA_WIDTH-1):0]      data_s1,
+  input   [(DATA_WIDTH-1):0]      data_s2,
+  input   [(DATA_WIDTH-1):0]      data_s3,
+  input   [(DATA_WIDTH-1):0]      data_s4,
+  input   [(DATA_WIDTH-1):0]      data_s5,
+  input   [(DATA_WIDTH-1):0]      data_s6,
+  input   [(DATA_WIDTH-1):0]      data_s7,
+  output  [(DATA_WIDTH-1):0]      data_out_p,
+  output  [(DATA_WIDTH-1):0]      data_out_n);
 
   // local parameter
 
-  localparam C5SOC = 1;
+  localparam ARRIA10 = 0;
+  localparam CYCLONE5 = 1;
 
   // internal signals
 
-  wire    [(DATA_WIDTH-1):0]  data_in_s[ 7:0];
-  wire    [(DATA_WIDTH-1):0]  data_in_s2[ 7:0];
+  wire    [(DATA_WIDTH-1):0]      data_samples_s[0:(SERDES_FACTOR-1)];
+  wire    [(SERDES_FACTOR-1):0]   data_in_s[0:(DATA_WIDTH-1)];
 
   // defaults
 
@@ -79,99 +80,96 @@ module ad_serdes_out #(
 
   // instantiations
 
-    assign data_in_s[0] = data_s0;
-    assign data_in_s[1] = data_s1;
-    assign data_in_s[2] = data_s2;
-    assign data_in_s[3] = data_s3;
-    assign data_in_s[4] = data_s4;
-    assign data_in_s[5] = data_s5;
-    assign data_in_s[6] = data_s6;
-    assign data_in_s[7] = data_s7;
+  genvar n;
+  genvar i;
 
-  genvar l_order;
   generate
-    for (l_order = 0; l_order < 8; l_order = l_order + 1) begin: g_order
-      assign data_in_s2[l_order] = (l_order < 8-SERDES_FACTOR) ? 1'b0 : data_in_s[l_order -8 + SERDES_FACTOR];
-    end
+  if (SERDES_FACTOR == 8) begin
+  assign data_samples_s[7] = data_s7;
+  assign data_samples_s[6] = data_s6;
+  assign data_samples_s[5] = data_s5;
+  assign data_samples_s[4] = data_s4;
+  end
   endgenerate
 
-  genvar l_inst;
-  generate
-  for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
-    if (DEVICE_TYPE == C5SOC) begin
-      altlvds_tx #(
-        .center_align_msb ("UNUSED"),
-        .common_rx_tx_pll ("ON"),
-        .coreclock_divide_by (1),
-        .data_rate ("500.0 Mbps"),
-        .deserialization_factor (4),
-        .differential_drive (0),
-        .enable_clock_pin_mode ("UNUSED"),
-        .implement_in_les ("OFF"),
-        .inclock_boost (0),
-        .inclock_data_alignment ("EDGE_ALIGNED"),
-        .inclock_period (4000),
-        .inclock_phase_shift (0),
-        .intended_device_family ("Cyclone V"),
-        .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_out"),
-        .lpm_type ("altlvds_tx"),
-        .multi_clock ("OFF"),
-        .number_of_channels (DATA_WIDTH),
-        .outclock_alignment ("EDGE_ALIGNED"),
-        .outclock_divide_by (2),
-        .outclock_duty_cycle (50),
-        .outclock_multiply_by (1),
-        .outclock_phase_shift (0),
-        .outclock_resource ("Regional clock"),
-        .output_data_rate (500),
-        .pll_compensation_mode ("AUTO"),
-        .pll_self_reset_on_loss_lock ("OFF"),
-        .preemphasis_setting (0),
-        .refclk_frequency ("250.000000 MHz"),
-        .registered_input ("TX_CORECLK"),
-        .use_external_pll ("ON"),
-        .use_no_phase_shift ("ON"),
-        .vod_setting (0),
-        .clk_src_is_pll ("off"))
-      i_altlvds_tx (
-        .tx_inclock (clk),
-        .tx_coreclock (div_clk),
-        .tx_in ({data_in_s2[0][l_inst],
-                 data_in_s2[1][l_inst],
-                 data_in_s2[2][l_inst],
-                 data_in_s2[3][l_inst],
-                 data_in_s2[4][l_inst],
-                 data_in_s2[5][l_inst],
-                 data_in_s2[6][l_inst],
-                 data_in_s2[7][l_inst]}),
-        .tx_outclock (),
-        .tx_out (data_out_p[l_inst]),
-        .tx_locked (),
-        .pll_areset (1'b0),
-        .sync_inclock (1'b0),
-        .tx_data_reset (1'b0),
-        .tx_enable (loaden),
-        .tx_pll_enable (1'b1),
-        .tx_syncclock (1'b0));
+  assign data_samples_s[3] = data_s3;
+  assign data_samples_s[2] = data_s2;
+  assign data_samples_s[1] = data_s1;
+  assign data_samples_s[0] = data_s0;
 
-    end else begin
-      alt_serdes_out_core i_core (
-        .clk_export (clk),
-        .div_clk_export (div_clk),
-        .loaden_export (loaden),
-        .data_out_export (data_out_p[l_inst]),
-        .data_s_export ({data_in_s2[0][l_inst],
-                         data_in_s2[1][l_inst],
-                         data_in_s2[2][l_inst],
-                         data_in_s2[3][l_inst],
-                         data_in_s2[4][l_inst],
-                         data_in_s2[5][l_inst],
-                         data_in_s2[6][l_inst],
-                         data_in_s2[7][l_inst]}));
+  generate
+  for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
+    for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
+      assign data_in_s[n][((SERDES_FACTOR-1)-i)] = data_samples_s[i][n];
     end
   end
   endgenerate
 
+  generate
+  for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
+
+  if (DEVICE_TYPE == CYCLONE5) begin
+  altlvds_tx #(
+    .center_align_msb ("UNUSED"),
+    .common_rx_tx_pll ("ON"),
+    .coreclock_divide_by (1),
+    .data_rate ("500.0 Mbps"),
+    .deserialization_factor (4),
+    .differential_drive (0),
+    .enable_clock_pin_mode ("UNUSED"),
+    .implement_in_les ("OFF"),
+    .inclock_boost (0),
+    .inclock_data_alignment ("EDGE_ALIGNED"),
+    .inclock_period (4000),
+    .inclock_phase_shift (0),
+    .intended_device_family ("Cyclone V"),
+    .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_out"),
+    .lpm_type ("altlvds_tx"),
+    .multi_clock ("OFF"),
+    .number_of_channels (DATA_WIDTH),
+    .outclock_alignment ("EDGE_ALIGNED"),
+    .outclock_divide_by (2),
+    .outclock_duty_cycle (50),
+    .outclock_multiply_by (1),
+    .outclock_phase_shift (0),
+    .outclock_resource ("Regional clock"),
+    .output_data_rate (500),
+    .pll_compensation_mode ("AUTO"),
+    .pll_self_reset_on_loss_lock ("OFF"),
+    .preemphasis_setting (0),
+    .refclk_frequency ("250.000000 MHz"),
+    .registered_input ("TX_CORECLK"),
+    .use_external_pll ("ON"),
+    .use_no_phase_shift ("ON"),
+    .vod_setting (0),
+    .clk_src_is_pll ("off"))
+  i_altlvds_tx (
+    .tx_inclock (clk),
+    .tx_coreclock (div_clk),
+    .tx_in (data_in_s[n]),
+    .tx_outclock (),
+    .tx_out (data_out_p[n]),
+    .tx_locked (),
+    .pll_areset (1'b0),
+    .sync_inclock (1'b0),
+    .tx_data_reset (1'b0),
+    .tx_enable (loaden),
+    .tx_pll_enable (1'b1),
+    .tx_syncclock (1'b0));
+  end
+
+  if (DEVICE_TYPE == ARRIA10) begin
+  __ad_serdes_out_1__ i_core (
+    .clk_export (clk),
+    .div_clk_export (div_clk),
+    .loaden_export (loaden),
+    .data_out_export (data_out_p[n]),
+    .data_s_export (data_in_s[n]));
+  end
+
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
index 45d930c2d..e3940d312 100644
--- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
@@ -403,7 +403,14 @@ module axi_ad9361_lvds_if #(
     .data_s6 (),
     .data_s7 (),
     .data_in_p (rx_data_in_p),
-    .data_in_n (rx_data_in_n));
+    .data_in_n (rx_data_in_n),
+    .up_clk (1'd0),
+    .up_dld (6'd0),
+    .up_dwdata (30'd0),
+    .up_drdata (),
+    .delay_clk (1'd0),
+    .delay_rst (1'd0),
+    .delay_locked ());
 
   // receive frame interface
 
@@ -427,7 +434,14 @@ module axi_ad9361_lvds_if #(
     .data_s6 (),
     .data_s7 (),
     .data_in_p (rx_frame_in_p),
-    .data_in_n (rx_frame_in_n));
+    .data_in_n (rx_frame_in_n),
+    .up_clk (1'd0),
+    .up_dld (6'd0),
+    .up_dwdata (30'd0),
+    .up_drdata (),
+    .delay_clk (1'd0),
+    .delay_rst (1'd0),
+    .delay_locked ());
 
   // transmit data interface
 
diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 8927db039..af6ea017b 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -69,116 +69,116 @@ module axi_ad9361 #(
 
   // physical interface (receive-cmos)
 
-  input               rx_clk_in,
-  input               rx_frame_in,
-  input   [11:0]      rx_data_in,
+  input           rx_clk_in,
+  input           rx_frame_in,
+  input   [11:0]  rx_data_in,
 
   // physical interface (transmit-lvds)
 
-  output              tx_clk_out_p,
-  output              tx_clk_out_n,
-  output              tx_frame_out_p,
-  output              tx_frame_out_n,
-  output  [ 5:0]      tx_data_out_p,
-  output  [ 5:0]      tx_data_out_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
 
   // physical interface (transmit-cmos)
 
-  output              tx_clk_out,
-  output              tx_frame_out,
-  output  [11:0]      tx_data_out,
+  output          tx_clk_out,
+  output          tx_frame_out,
+  output  [11:0]  tx_data_out,
 
   // ensm control
 
-  output              enable,
-  output              txnrx,
+  output          enable,
+  output          txnrx,
 
   // transmit master/slave
 
-  input               dac_sync_in,
-  output              dac_sync_out,
+  input           dac_sync_in,
+  output          dac_sync_out,
 
   // tdd sync
 
-  input               tdd_sync,
-  output              tdd_sync_cntr,
+  input           tdd_sync,
+  output          tdd_sync_cntr,
 
   // delay clock
 
-  input               delay_clk,
+  input           delay_clk,
 
   // master interface
 
-  output              l_clk,
-  input               clk,
-  output              rst,
+  output          l_clk,
+  input           clk,
+  output          rst,
 
   // dma interface
 
-  output              adc_enable_i0,
-  output  reg         adc_valid_i0,
-  output  reg [15:0]  adc_data_i0,
-  output              adc_enable_q0,
-  output  reg         adc_valid_q0,
-  output  reg [15:0]  adc_data_q0,
-  output              adc_enable_i1,
-  output  reg         adc_valid_i1,
-  output  reg [15:0]  adc_data_i1,
-  output              adc_enable_q1,
-  output  reg         adc_valid_q1,
-  output  reg [15:0]  adc_data_q1,
-  input               adc_dovf,
-  input               adc_dunf,
-  output              adc_r1_mode,
+  output          adc_enable_i0,
+  output          adc_valid_i0,
+  output  [15:0]  adc_data_i0,
+  output          adc_enable_q0,
+  output          adc_valid_q0,
+  output  [15:0]  adc_data_q0,
+  output          adc_enable_i1,
+  output          adc_valid_i1,
+  output  [15:0]  adc_data_i1,
+  output          adc_enable_q1,
+  output          adc_valid_q1,
+  output  [15:0]  adc_data_q1,
+  input           adc_dovf,
+  input           adc_dunf,
+  output          adc_r1_mode,
 
-  output              dac_enable_i0,
-  output  reg         dac_valid_i0,
-  input       [15:0]  dac_data_i0,
-  output              dac_enable_q0,
-  output  reg         dac_valid_q0,
-  input       [15:0]  dac_data_q0,
-  output              dac_enable_i1,
-  output  reg         dac_valid_i1,
-  input       [15:0]  dac_data_i1,
-  output              dac_enable_q1,
-  output  reg         dac_valid_q1,
-  input       [15:0]  dac_data_q1,
-  input               dac_dovf,
-  input               dac_dunf,
-  output              dac_r1_mode,
+  output          dac_enable_i0,
+  output          dac_valid_i0,
+  input   [15:0]  dac_data_i0,
+  output          dac_enable_q0,
+  output          dac_valid_q0,
+  input   [15:0]  dac_data_q0,
+  output          dac_enable_i1,
+  output          dac_valid_i1,
+  input   [15:0]  dac_data_i1,
+  output          dac_enable_q1,
+  output          dac_valid_q1,
+  input   [15:0]  dac_data_q1,
+  input           dac_dovf,
+  input           dac_dunf,
+  output          dac_r1_mode,
 
   // axi interface
 
-  input               s_axi_aclk,
-  input               s_axi_aresetn,
-  input               s_axi_awvalid,
-  input   [31:0]      s_axi_awaddr,
-  input   [ 2:0]      s_axi_awprot,
-  output              s_axi_awready,
-  input               s_axi_wvalid,
-  input   [31:0]      s_axi_wdata,
-  input   [ 3:0]      s_axi_wstrb,
-  output              s_axi_wready,
-  output              s_axi_bvalid,
-  output  [ 1:0]      s_axi_bresp,
-  input               s_axi_bready,
-  input               s_axi_arvalid,
-  input   [31:0]      s_axi_araddr,
-  input   [ 2:0]      s_axi_arprot,
-  output              s_axi_arready,
-  output              s_axi_rvalid,
-  output  [31:0]      s_axi_rdata,
-  output  [ 1:0]      s_axi_rresp,
-  input               s_axi_rready,
+  input           s_axi_aclk,
+  input           s_axi_aresetn,
+  input           s_axi_awvalid,
+  input   [31:0]  s_axi_awaddr,
+  input   [ 2:0]  s_axi_awprot,
+  output          s_axi_awready,
+  input           s_axi_wvalid,
+  input   [31:0]  s_axi_wdata,
+  input   [ 3:0]  s_axi_wstrb,
+  output          s_axi_wready,
+  output          s_axi_bvalid,
+  output  [ 1:0]  s_axi_bresp,
+  input           s_axi_bready,
+  input           s_axi_arvalid,
+  input   [31:0]  s_axi_araddr,
+  input   [ 2:0]  s_axi_arprot,
+  output          s_axi_arready,
+  output          s_axi_rvalid,
+  output  [31:0]  s_axi_rdata,
+  output  [ 1:0]  s_axi_rresp,
+  input           s_axi_rready,
 
   // gpio
 
-  input               up_enable,
-  input               up_txnrx,
-  input   [31:0]      up_dac_gpio_in,
-  output  [31:0]      up_dac_gpio_out,
-  input   [31:0]      up_adc_gpio_in,
-  output  [31:0]      up_adc_gpio_out);
+  input           up_enable,
+  input           up_txnrx,
+  input   [31:0]  up_dac_gpio_in,
+  output  [31:0]  up_dac_gpio_out,
+  input   [31:0]  up_adc_gpio_in,
+  output  [31:0]  up_adc_gpio_out);
 
   // derived parameters
 
@@ -193,6 +193,18 @@ module axi_ad9361 #(
 
   // internal registers
 
+  reg             adc_valid_i0_int = 'd0;
+  reg             adc_valid_q0_int = 'd0;
+  reg             adc_valid_i1_int = 'd0;
+  reg             adc_valid_q1_int = 'd0;
+  reg     [15:0]  adc_data_i0_int = 'd0;
+  reg     [15:0]  adc_data_q0_int = 'd0;
+  reg     [15:0]  adc_data_i1_int = 'd0;
+  reg     [15:0]  adc_data_q1_int = 'd0;
+  reg             dac_valid_i0_int = 'd0;
+  reg             dac_valid_q0_int = 'd0;
+  reg             dac_valid_i1_int = 'd0;
+  reg             dac_valid_q1_int = 'd0;
   reg             up_wack = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
@@ -260,7 +272,7 @@ module axi_ad9361 #(
   wire            tdd_rx_rf_en_s;
   wire            tdd_tx_rf_en_s;
   wire    [ 7:0]  tdd_status_s;
-
+    
   // signal name changes
 
   assign up_clk = s_axi_aclk;
@@ -406,22 +418,40 @@ module axi_ad9361 #(
   end
   endgenerate
 
+  assign adc_valid_i0 = adc_valid_i0_int;
+  assign adc_valid_q0 = adc_valid_q0_int;
+  assign adc_valid_i1 = adc_valid_i1_int;
+  assign adc_valid_q1 = adc_valid_q1_int;
+
   always @(posedge clk) begin
+    adc_valid_i0_int <= tdd_rx_valid_s & adc_valid_i0_s;
+    adc_valid_q0_int <= tdd_rx_valid_s & adc_valid_q0_s;
+    adc_valid_i1_int <= tdd_rx_valid_s & adc_valid_i1_s;
+    adc_valid_q1_int <= tdd_rx_valid_s & adc_valid_q1_s;
+  end
 
-    dac_valid_i0 <= tdd_tx_valid_s & dac_valid_i0_s;
-    dac_valid_q0 <= tdd_tx_valid_s & dac_valid_q0_s;
-    dac_valid_i1 <= tdd_tx_valid_s & dac_valid_i1_s;
-    dac_valid_q1 <= tdd_tx_valid_s & dac_valid_q1_s;
+  assign adc_data_i0 = adc_data_i0_int;
+  assign adc_data_q0 = adc_data_q0_int;
+  assign adc_data_i1 = adc_data_i1_int;
+  assign adc_data_q1 = adc_data_q1_int;
 
-    adc_valid_i0 <= tdd_rx_valid_s & adc_valid_i0_s;
-    adc_valid_q0 <= tdd_rx_valid_s & adc_valid_q0_s;
-    adc_valid_i1 <= tdd_rx_valid_s & adc_valid_i1_s;
-    adc_valid_q1 <= tdd_rx_valid_s & adc_valid_q1_s;
-    adc_data_i0 <= adc_data_i0_s;
-    adc_data_q0 <= adc_data_q0_s;
-    adc_data_i1 <= adc_data_i1_s;
-    adc_data_q1 <= adc_data_q1_s;
+  always @(posedge clk) begin
+    adc_data_i0_int <= adc_data_i0_s;
+    adc_data_q0_int <= adc_data_q0_s;
+    adc_data_i1_int <= adc_data_i1_s;
+    adc_data_q1_int <= adc_data_q1_s;
+  end
 
+  assign dac_valid_i0 = dac_valid_i0_int;
+  assign dac_valid_q0 = dac_valid_q0_int;
+  assign dac_valid_i1 = dac_valid_i1_int;
+  assign dac_valid_q1 = dac_valid_q1_int;
+
+  always @(posedge clk) begin
+    dac_valid_i0_int <= tdd_tx_valid_s & dac_valid_i0_s;
+    dac_valid_q0_int <= tdd_tx_valid_s & dac_valid_q0_s;
+    dac_valid_i1_int <= tdd_tx_valid_s & dac_valid_i1_s;
+    dac_valid_q1_int <= tdd_tx_valid_s & dac_valid_q1_s;
   end
 
   // tdd
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index d8696c7a9..c14fff648 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -13,22 +13,16 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9361
 
 # files
 
-add_fileset quartus_synth QUARTUS_SYNTH "" ""
+add_fileset quartus_synth QUARTUS_SYNTH "p_axi_ad9361_fset" ""
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
 add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file ad_serdes_clk.v          VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v
-add_fileset_file ad_serdes_in.v           VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v
-add_fileset_file ad_serdes_out.v          VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v
-add_fileset_file ad_cmos_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_clk.v
-add_fileset_file ad_cmos_in.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_in.v
-add_fileset_file ad_cmos_out.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_out.v
 add_fileset_file ad_mul.v                 VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
+add_fileset_file ad_dcfilter.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
 add_fileset_file ad_pnmon.v               VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
 add_fileset_file ad_dds_sine.v            VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
 add_fileset_file ad_dds_1.v               VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
 add_fileset_file ad_dds.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
 add_fileset_file ad_datafmt.v             VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
-add_fileset_file ad_dcfilter.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
 add_fileset_file ad_iqcor.v               VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
 add_fileset_file ad_addsub.v              VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v
 add_fileset_file ad_tdd_control.v         VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v
@@ -57,79 +51,33 @@ add_fileset_file axi_ad9361_constr.sdc    SDC     PATH axi_ad9361_constr.sdc
 
 # parameters
 
-add_parameter ID INTEGER 0
-set_parameter_property ID DEFAULT_VALUE 0
-set_parameter_property ID DISPLAY_NAME ID
-set_parameter_property ID TYPE INTEGER
-set_parameter_property ID UNITS None
-set_parameter_property ID HDL_PARAMETER true
-
-add_parameter DEVICE_TYPE INTEGER 0
-set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
-set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
-set_parameter_property DEVICE_TYPE TYPE INTEGER
-set_parameter_property DEVICE_TYPE UNITS None
-set_parameter_property DEVICE_TYPE HDL_PARAMETER true
-
-add_parameter CMOS_OR_LVDS_N INTEGER 0
-set_parameter_property CMOS_OR_LVDS_N DEFAULT_VALUE 0
-set_parameter_property CMOS_OR_LVDS_N DISPLAY_NAME CMOS_OR_LVDS_N
-set_parameter_property CMOS_OR_LVDS_N TYPE INTEGER
-set_parameter_property CMOS_OR_LVDS_N UNITS None
-set_parameter_property CMOS_OR_LVDS_N HDL_PARAMETER true
-
-add_parameter DAC_DATAPATH_DISABLE INTEGER 0
-set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
-set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
-set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
-set_parameter_property DAC_DATAPATH_DISABLE UNITS None
-set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
-
-add_parameter ADC_DATAPATH_DISABLE INTEGER 0
-set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0
-set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE
-set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
-set_parameter_property ADC_DATAPATH_DISABLE UNITS None
-set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
-
 add_parameter DEVICE_FAMILY STRING
 set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
 set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
 set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
 set_parameter_property DEVICE_FAMILY ENABLED false
 
-# axi4 slave interface
+add_parameter ID INTEGER 0
+add_parameter MODE_1R1T INTEGER 0
+add_parameter DEVICE_TYPE INTEGER 0
+add_parameter TDD_DISABLE INTEGER 0
+add_parameter CMOS_OR_LVDS_N INTEGER 0
+add_parameter ADC_DATAPATH_DISABLE INTEGER 0
+add_parameter ADC_USERPORTS_DISABLE INTEGER 0
+add_parameter ADC_DATAFORMAT_DISABLE INTEGER 0
+add_parameter ADC_DCFILTER_DISABLE INTEGER 0
+add_parameter ADC_IQCORRECTION_DISABLE INTEGER 0
+add_parameter DAC_IODELAY_ENABLE INTEGER 0
+add_parameter DAC_DATAPATH_DISABLE INTEGER 0
+add_parameter DAC_DDS_DISABLE INTEGER 0
+add_parameter DAC_USERPORTS_DISABLE INTEGER 0
+add_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
+add_parameter IO_DELAY_GROUP STRING "dev_if_delay_group"
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+# interfaces
 
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
+ 
 # master-slave interface
 
 ad_alt_intf signal dac_sync_in input 1
@@ -223,42 +171,11 @@ ad_alt_intf signal up_dac_gpio_out output 32
 ad_alt_intf signal up_adc_gpio_in input 32
 ad_alt_intf signal up_adc_gpio_out output 32
 
-add_hdl_instance alt_ddio_in altera_gpio
-set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
-set_instance_parameter_value alt_ddio_in {SIZE} {1}
-set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
-set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
-
-add_hdl_instance alt_ddio_out altera_gpio
-set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
-set_instance_parameter_value alt_ddio_out {SIZE} {1}
-set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
-set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
-
-add_hdl_instance alt_serdes_clk_core alt_serdes
-set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK}
-set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1}
-set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4}
-set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
-
-add_hdl_instance alt_serdes_in_core alt_serdes
-set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
-set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
-set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
-set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0}
-
-add_hdl_instance alt_serdes_out_core alt_serdes
-set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
-set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
-set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4}
-set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0}
-
 # updates
 
 proc p_axi_ad9361 {} {
 
   set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N]
-  set m_device_type [get_parameter_value DEVICE_TYPE]
   set m_device_family [get_parameter_value DEVICE_FAMILY]
 
   add_interface device_if conduit end
@@ -294,14 +211,57 @@ proc p_axi_ad9361 {} {
   add_interface_port device_if enable enable Output 1
   add_interface_port device_if txnrx txnrx Output 1
 
-  if {$m_device_type == 1} {
+  if {$m_device_family == "Arria 10"} {
 
-    ## add_hdl_instance do not work here (pending altera support)
+    add_hdl_instance alt_serdes_clk_core alt_serdes
+    set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK}
+    set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1}
+    set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4}
+    set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
+
+    add_hdl_instance alt_serdes_in_core alt_serdes
+    set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
+    set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
+    set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
+    set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0}
+
+    add_hdl_instance alt_serdes_out_core alt_serdes
+    set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
+    set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
+    set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4}
+    set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0}
+
+    add_hdl_instance alt_ddio_in altera_gpio
+    set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
+    set_instance_parameter_value alt_ddio_in {SIZE} {1}
+    set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
+    set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
+
+    add_hdl_instance alt_ddio_out altera_gpio
+    set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
+    set_instance_parameter_value alt_ddio_out {SIZE} {1}
+    set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
+    set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
   }
 
-  if {$m_device_type == 0} {
+  if {$m_device_family == "Cyclone V"} {
 
     ## add_hdl_instance do not work here (pending altera support)
   }
 }
 
+proc p_axi_ad9361_fset {entityName} {
+
+  ad_ip_file ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
+  ad_ip_file ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
+  ad_ip_file ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
+  ad_ip_file ad_cmos_in.v ad_cmos_in.v ad_cmos_in_core
+  ad_ip_file ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core
+
+  add_fileset_file ad_serdes_in.v VERILOG PATH ad_serdes_in.v
+  add_fileset_file ad_serdes_out.v VERILOG PATH ad_serdes_out.v
+  add_fileset_file ad_serdes_clk.v VERILOG PATH ad_serdes_clk.v
+  add_fileset_file ad_cmos_in.v VERILOG PATH ad_cmos_in.v
+  add_fileset_file ad_cmos_out.v VERILOG PATH ad_cmos_out.v
+}
+
diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl
index 3fcc3cba8..a26b5336d 100644
--- a/library/scripts/adi_ip_alt.tcl
+++ b/library/scripts/adi_ip_alt.tcl
@@ -89,3 +89,60 @@ proc ad_generate_module_inst { inst_name mark source_file target_file } {
   close $fp_target
 }
 
+proc ad_ip_intf_s_axi {aclk arstn} {
+
+  add_interface s_axi_clock clock end
+  add_interface_port s_axi_clock ${aclk} clk Input 1
+
+  add_interface s_axi_reset reset end
+  set_interface_property s_axi_reset associatedClock s_axi_clock
+  add_interface_port s_axi_reset ${arstn} reset_n Input 1
+
+  add_interface s_axi axi4lite end
+  set_interface_property s_axi associatedClock s_axi_clock
+  set_interface_property s_axi associatedReset s_axi_reset
+  add_interface_port s_axi s_axi_awvalid awvalid Input 1
+  add_interface_port s_axi s_axi_awaddr awaddr Input 16
+  add_interface_port s_axi s_axi_awprot awprot Input 3
+  add_interface_port s_axi s_axi_awready awready Output 1
+  add_interface_port s_axi s_axi_wvalid wvalid Input 1
+  add_interface_port s_axi s_axi_wdata wdata Input 32
+  add_interface_port s_axi s_axi_wstrb wstrb Input 4
+  add_interface_port s_axi s_axi_wready wready Output 1
+  add_interface_port s_axi s_axi_bvalid bvalid Output 1
+  add_interface_port s_axi s_axi_bresp bresp Output 2
+  add_interface_port s_axi s_axi_bready bready Input 1
+  add_interface_port s_axi s_axi_arvalid arvalid Input 1
+  add_interface_port s_axi s_axi_araddr araddr Input 16
+  add_interface_port s_axi s_axi_arprot arprot Input 3
+  add_interface_port s_axi s_axi_arready arready Output 1
+  add_interface_port s_axi s_axi_rvalid rvalid Output 1
+  add_interface_port s_axi s_axi_rresp rresp Output 2
+  add_interface_port s_axi s_axi_rdata rdata Output 32
+  add_interface_port s_axi s_axi_rready rready Input 1
+}
+
+proc ad_ip_file {ifile ofile flist} {
+
+  global ad_hdl_dir
+
+  set srcfile [open ${ad_hdl_dir}/library/altera/common/${ifile} r]
+  set dstfile [open ${ofile} w]
+
+  regsub {\..$} $ifile {} imodule
+  regsub {\..$} $ofile {} omodule
+
+  while {[gets $srcfile srcline] >= 0} {
+    regsub __${imodule}__ $srcline $omodule dstline
+    set index 0
+    foreach fword $flist {
+      incr index
+      regsub __${imodule}_${index}__ $dstline $fword dstline
+    }
+    puts $dstfile $dstline
+  }
+
+  close $srcfile
+  close $dstfile
+}
+

From cc75fa3dfe65dbc5542fd9be1d163161a3933b75 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 31 Oct 2016 10:54:07 -0400
Subject: [PATCH 651/972] altera- java/tcl mess handling

---
 library/altera/common/ad_serdes_clk.v         |  2 +-
 library/altera/common/ad_serdes_in.v          | 94 +++----------------
 library/altera/common/ad_serdes_out.v         | 55 ++---------
 .../axi_ad9361/altera/axi_ad9361_lvds_if.v    |  4 +-
 library/scripts/adi_ip_alt.tcl                | 35 +++++++
 5 files changed, 57 insertions(+), 133 deletions(-)

diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v
index 2ed1b58f5..e708404f2 100644
--- a/library/altera/common/ad_serdes_clk.v
+++ b/library/altera/common/ad_serdes_clk.v
@@ -191,7 +191,7 @@ module __ad_serdes_clk__ #(
     .pll_reconfig_read (up_drp_rd_int),
     .pll_reconfig_write (up_drp_wr_int),
     .pll_reconfig_readdata (up_drp_rdata_int_s),
-    .pll_reconfig_address (up_drp_addr_int),
+    .pll_reconfig_address (up_drp_addr_int[5:0]),
     .pll_reconfig_writedata (up_drp_wdata_int));
 
   cyclonev_pll_lvds_output #(
diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index abadf7bae..9b147d698 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -136,89 +136,17 @@ module __ad_serdes_in__ #(
   for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
 
   if (DEVICE_TYPE == CYCLONE5) begin
-  altlvds_rx #(
-    .buffer_implementation ("RAM"),
-    .cds_mode ("UNUSED"),
-    .common_rx_tx_pll ("ON"),
-    .data_align_rollover (4),
-    .data_rate ("500.0 Mbps"),
-    .deserialization_factor (4),
-    .dpa_initial_phase_value (0),
-    .dpll_lock_count (0),
-    .dpll_lock_window (0),
-    .enable_clock_pin_mode ("UNUSED"),
-    .enable_dpa_align_to_rising_edge_only ("OFF"),
-    .enable_dpa_calibration ("ON"),
-    .enable_dpa_fifo ("UNUSED"),
-    .enable_dpa_initial_phase_selection ("OFF"),
-    .enable_dpa_mode ("OFF"),
-    .enable_dpa_pll_calibration ("OFF"),
-    .enable_soft_cdr_mode ("OFF"),
-    .implement_in_les ("OFF"),
-    .inclock_boost (0),
-    .inclock_data_alignment ("EDGE_ALIGNED"),
-    .inclock_period (4000),
-    .inclock_phase_shift (0),
-    .input_data_rate (500),
-    .intended_device_family ("Cyclone V"),
-    .lose_lock_on_one_change ("UNUSED"),
-    .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_in"),
-    .lpm_type ("altlvds_rx"),
-    .number_of_channels (DATA_WIDTH),
-    .outclock_resource ("Regional clock"),
-    .pll_operation_mode ("NORMAL"),
-    .pll_self_reset_on_loss_lock ("UNUSED"),
-    .port_rx_channel_data_align ("PORT_UNUSED"),
-    .port_rx_data_align ("PORT_UNUSED"),
-    .refclk_frequency ("250.000000 MHz"),
-    .registered_data_align_input ("UNUSED"),
-    .registered_output ("ON"),
-    .reset_fifo_at_first_lock ("UNUSED"),
-    .rx_align_data_reg ("RISING_EDGE"),
-    .sim_dpa_is_negative_ppm_drift ("OFF"),
-    .sim_dpa_net_ppm_variation (0),
-    .sim_dpa_output_clock_phase_shift (0),
-    .use_coreclock_input ("OFF"),
-    .use_dpll_rawperror ("OFF"),
-    .use_external_pll ("ON"),
-    .use_no_phase_shift ("ON"),
-    .x_on_bitslip ("ON"),
-    .clk_src_is_pll ("off"))
-  i_altlvds_rx (
-    .rx_inclock (clk),
-    .rx_in (data_in_p[n]),
-    .rx_outclock (),
-    .rx_out (data_out_s[n]),
-    .rx_locked (),
-    .dpa_pll_cal_busy (),
-    .dpa_pll_recal (1'b0),
-    .pll_areset (~locked),
-    .pll_phasecounterselect (),
-    .pll_phasedone (1'b1),
-    .pll_phasestep (),
-    .pll_phaseupdown (),
-    .pll_scanclk (),
-    .rx_cda_max (),
-    .rx_cda_reset ({7{1'b0}}),
-    .rx_channel_data_align ({7{1'b0}}),
-    .rx_coreclk (1'b1),
-    .rx_data_align (1'b0),
-    .rx_data_align_reset (1'b0),
-    .rx_data_reset (1'b0),
-    .rx_deskew (1'b0),
-    .rx_divfwdclk (),
-    .rx_dpa_lock_reset ({7{1'b0}}),
-    .rx_dpa_locked (),
-    .rx_dpaclock (1'b0),
-    .rx_dpll_enable ({7{1'b1}}),
-    .rx_dpll_hold ({7{1'b0}}),
-    .rx_dpll_reset ({7{1'b0}}),
-    .rx_enable (loaden),
-    .rx_fifo_reset ({7{1'b0}}),
-    .rx_pll_enable (1'b1),
-    .rx_readclock (1'b0),
-    .rx_reset ({7{1'b0}}),
-    .rx_syncclock (1'b0));
+
+  assign delay_locked_s[n] = 1'b1;
+
+  ad_serdes_in_core_c5 #(
+    .SERDES_FACTOR (SERDES_FACTOR))
+  i_core (
+    .clk (clk),
+    .div_clk (div_clk),
+    .enable (loaden),
+    .data_in (data_in_p[n]),
+    .data (data_out_s[n]));
   end
 
   if (DEVICE_TYPE == ARRIA10) begin
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index 47298a0dc..8bca8ffd5 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -109,53 +109,14 @@ module __ad_serdes_out__ #(
   for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
 
   if (DEVICE_TYPE == CYCLONE5) begin
-  altlvds_tx #(
-    .center_align_msb ("UNUSED"),
-    .common_rx_tx_pll ("ON"),
-    .coreclock_divide_by (1),
-    .data_rate ("500.0 Mbps"),
-    .deserialization_factor (4),
-    .differential_drive (0),
-    .enable_clock_pin_mode ("UNUSED"),
-    .implement_in_les ("OFF"),
-    .inclock_boost (0),
-    .inclock_data_alignment ("EDGE_ALIGNED"),
-    .inclock_period (4000),
-    .inclock_phase_shift (0),
-    .intended_device_family ("Cyclone V"),
-    .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_out"),
-    .lpm_type ("altlvds_tx"),
-    .multi_clock ("OFF"),
-    .number_of_channels (DATA_WIDTH),
-    .outclock_alignment ("EDGE_ALIGNED"),
-    .outclock_divide_by (2),
-    .outclock_duty_cycle (50),
-    .outclock_multiply_by (1),
-    .outclock_phase_shift (0),
-    .outclock_resource ("Regional clock"),
-    .output_data_rate (500),
-    .pll_compensation_mode ("AUTO"),
-    .pll_self_reset_on_loss_lock ("OFF"),
-    .preemphasis_setting (0),
-    .refclk_frequency ("250.000000 MHz"),
-    .registered_input ("TX_CORECLK"),
-    .use_external_pll ("ON"),
-    .use_no_phase_shift ("ON"),
-    .vod_setting (0),
-    .clk_src_is_pll ("off"))
-  i_altlvds_tx (
-    .tx_inclock (clk),
-    .tx_coreclock (div_clk),
-    .tx_in (data_in_s[n]),
-    .tx_outclock (),
-    .tx_out (data_out_p[n]),
-    .tx_locked (),
-    .pll_areset (1'b0),
-    .sync_inclock (1'b0),
-    .tx_data_reset (1'b0),
-    .tx_enable (loaden),
-    .tx_pll_enable (1'b1),
-    .tx_syncclock (1'b0));
+  ad_serdes_out_core_c5 #(
+    .SERDES_FACTOR (SERDES_FACTOR))
+  i_core (
+    .clk (clk),
+    .div_clk (div_clk),
+    .enable (loaden),
+    .data_out (data_out_p[n]),
+    .data (data_in_s[n]));
   end
 
   if (DEVICE_TYPE == ARRIA10) begin
diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
index e3940d312..1763d272b 100644
--- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
@@ -436,8 +436,8 @@ module axi_ad9361_lvds_if #(
     .data_in_p (rx_frame_in_p),
     .data_in_n (rx_frame_in_n),
     .up_clk (1'd0),
-    .up_dld (6'd0),
-    .up_dwdata (30'd0),
+    .up_dld (1'd0),
+    .up_dwdata (5'd0),
     .up_drdata (),
     .delay_clk (1'd0),
     .delay_rst (1'd0),
diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl
index a26b5336d..c1db04ff4 100644
--- a/library/scripts/adi_ip_alt.tcl
+++ b/library/scripts/adi_ip_alt.tcl
@@ -89,6 +89,41 @@ proc ad_generate_module_inst { inst_name mark source_file target_file } {
   close $fp_target
 }
 
+proc ad_ip_parameter {pname ptype pdefault} {
+
+  add_parameter $pname $ptype $pdefault
+  set_parameter_property $pname HDL_PARAMETER true
+  set_parameter_property $pname ENABLED true
+}
+
+proc ad_ip_files {pname pfiles {pfunction ""}} {
+
+  set ftopfile [lindex $pfiles end]
+  set pfiles [lreplace $pfiles end end]
+
+  add_fileset quartus_synth QUARTUS_SYNTH $pfunction ""
+  set_fileset_property quartus_synth TOP_LEVEL $pname
+
+  foreach pfile $pfiles {
+    set pmodule [file tail $pfile]
+    add_fileset_file $pmodule VERILOG PATH $pfile
+  }
+  set pfile $ftopfile
+  set pmodule [file tail $pfile]
+  add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
+
+  add_fileset quartus_sim SIM_VERILOG $pfunction ""
+  set_fileset_property quartus_sim TOP_LEVEL $pname
+
+  foreach pfile $pfiles {
+    set pmodule [file tail $pfile]
+    add_fileset_file $pmodule VERILOG PATH $pfile
+  }
+  set pfile $ftopfile
+  set pmodule [file tail $pfile]
+  add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
+}
+
 proc ad_ip_intf_s_axi {aclk arstn} {
 
   add_interface s_axi_clock clock end

From e0459df0f3fa6be6cbb67ec6a7f50865a14b3e69 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 31 Oct 2016 11:18:27 -0400
Subject: [PATCH 652/972] altera -c5 qsys alternative

---
 library/altera/common/ad_serdes_in_core_c5.v  | 146 ++++++++++++++++++
 library/altera/common/ad_serdes_out_core_c5.v | 107 +++++++++++++
 2 files changed, 253 insertions(+)
 create mode 100644 library/altera/common/ad_serdes_in_core_c5.v
 create mode 100644 library/altera/common/ad_serdes_out_core_c5.v

diff --git a/library/altera/common/ad_serdes_in_core_c5.v b/library/altera/common/ad_serdes_in_core_c5.v
new file mode 100644
index 000000000..05e34b8eb
--- /dev/null
+++ b/library/altera/common/ad_serdes_in_core_c5.v
@@ -0,0 +1,146 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ps/1ps
+
+module ad_serdes_in_core_c5 #(
+
+  parameter       SERDES_FACTOR = 8) (
+
+  input                           clk,
+  input                           div_clk,
+  input                           enable,
+  input                           data_in,
+  output  [(SERDES_FACTOR-1):0]   data);
+
+  reg     [(SERDES_FACTOR-1):0]   data_int = 'd0;
+  wire    [(SERDES_FACTOR-1):0]   data_s;
+
+  assign data = data_int;
+
+  always @(posedge div_clk) begin
+    data_int <= data_s;
+  end
+
+  altlvds_rx i_altlvds_rx (
+    .rx_enable (enable),
+    .rx_in (data_in),
+    .rx_inclock (clk),
+    .rx_out (data_s),
+    .dpa_pll_cal_busy (),
+    .dpa_pll_recal (1'b0),
+    .pll_areset (1'b0),
+    .pll_phasecounterselect (),
+    .pll_phasedone (1'b1),
+    .pll_phasestep (),
+    .pll_phaseupdown (),
+    .pll_scanclk (),
+    .rx_cda_max (),
+    .rx_cda_reset (1'b0),
+    .rx_channel_data_align (1'b0),
+    .rx_coreclk (1'b1),
+    .rx_data_align (1'b0),
+    .rx_data_align_reset (1'b0),
+    .rx_data_reset (1'b0),
+    .rx_deskew (1'b0),
+    .rx_divfwdclk (),
+    .rx_dpa_lock_reset (1'b0),
+    .rx_dpa_locked (),
+    .rx_dpaclock (1'b0),
+    .rx_dpll_enable (1'b1),
+    .rx_dpll_hold (1'b0),
+    .rx_dpll_reset (1'b0),
+    .rx_fifo_reset (1'b0),
+    .rx_locked (),
+    .rx_outclock (),
+    .rx_pll_enable (1'b1),
+    .rx_readclock (1'b0),
+    .rx_reset (1'b0),
+    .rx_syncclock (1'b0));
+  defparam
+    i_altlvds_rx.buffer_implementation = "RAM",
+    i_altlvds_rx.cds_mode = "UNUSED",
+    i_altlvds_rx.common_rx_tx_pll = "OFF",
+    i_altlvds_rx.data_align_rollover = 4,
+    i_altlvds_rx.data_rate = "800.0 Mbps",
+    i_altlvds_rx.deserialization_factor = SERDES_FACTOR,
+    i_altlvds_rx.dpa_initial_phase_value = 0,
+    i_altlvds_rx.dpll_lock_count = 0,
+    i_altlvds_rx.dpll_lock_window = 0,
+    i_altlvds_rx.enable_clock_pin_mode = "UNUSED",
+    i_altlvds_rx.enable_dpa_align_to_rising_edge_only = "OFF",
+    i_altlvds_rx.enable_dpa_calibration = "ON",
+    i_altlvds_rx.enable_dpa_fifo = "UNUSED",
+    i_altlvds_rx.enable_dpa_initial_phase_selection = "OFF",
+    i_altlvds_rx.enable_dpa_mode = "OFF",
+    i_altlvds_rx.enable_dpa_pll_calibration = "OFF",
+    i_altlvds_rx.enable_soft_cdr_mode = "OFF",
+    i_altlvds_rx.implement_in_les = "OFF",
+    i_altlvds_rx.inclock_boost = 0,
+    i_altlvds_rx.inclock_data_alignment = "EDGE_ALIGNED",
+    i_altlvds_rx.inclock_period = 50000,
+    i_altlvds_rx.inclock_phase_shift = 0,
+    i_altlvds_rx.input_data_rate = 800,
+    i_altlvds_rx.intended_device_family = "Cyclone V",
+    i_altlvds_rx.lose_lock_on_one_change = "UNUSED",
+    i_altlvds_rx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_in_core_c5",
+    i_altlvds_rx.lpm_type = "altlvds_rx",
+    i_altlvds_rx.number_of_channels = 1,
+    i_altlvds_rx.outclock_resource = "Dual-Regional clock",
+    i_altlvds_rx.pll_operation_mode = "NORMAL",
+    i_altlvds_rx.pll_self_reset_on_loss_lock = "UNUSED",
+    i_altlvds_rx.port_rx_channel_data_align = "PORT_UNUSED",
+    i_altlvds_rx.port_rx_data_align = "PORT_UNUSED",
+    i_altlvds_rx.refclk_frequency = "20.000000 MHz",
+    i_altlvds_rx.registered_data_align_input = "UNUSED",
+    i_altlvds_rx.registered_output = "OFF",
+    i_altlvds_rx.reset_fifo_at_first_lock = "UNUSED",
+    i_altlvds_rx.rx_align_data_reg = "RISING_EDGE",
+    i_altlvds_rx.sim_dpa_is_negative_ppm_drift = "OFF",
+    i_altlvds_rx.sim_dpa_net_ppm_variation = 0,
+    i_altlvds_rx.sim_dpa_output_clock_phase_shift = 0,
+    i_altlvds_rx.use_coreclock_input = "OFF",
+    i_altlvds_rx.use_dpll_rawperror = "OFF",
+    i_altlvds_rx.use_external_pll = "ON",
+    i_altlvds_rx.use_no_phase_shift = "ON",
+    i_altlvds_rx.x_on_bitslip = "ON",
+    i_altlvds_rx.clk_src_is_pll = "off";
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/altera/common/ad_serdes_out_core_c5.v b/library/altera/common/ad_serdes_out_core_c5.v
new file mode 100644
index 000000000..07d627fe6
--- /dev/null
+++ b/library/altera/common/ad_serdes_out_core_c5.v
@@ -0,0 +1,107 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ps/1ps
+
+module ad_serdes_out_core_c5 #(
+
+  parameter       SERDES_FACTOR = 8) (
+
+  input                           clk,
+  input                           div_clk,
+  input                           enable,
+  output                          data_out,
+  input   [(SERDES_FACTOR-1):0]   data);
+
+  reg     [(SERDES_FACTOR-1):0]   data_int = 'd0;
+
+  always @(posedge div_clk) begin
+    data_int <= data;
+  end
+
+  altlvds_tx  i_altlvds_tx (
+    .tx_enable (enable),
+    .tx_in (data),
+    .tx_inclock (clk),
+    .tx_out (data_out),
+    .pll_areset (1'b0),
+    .sync_inclock (1'b0),
+    .tx_coreclock (),
+    .tx_data_reset (1'b0),
+    .tx_locked (),
+    .tx_outclock (),
+    .tx_pll_enable (1'b1),
+    .tx_syncclock (1'b0));
+  defparam
+    i_altlvds_tx.center_align_msb = "UNUSED",
+    i_altlvds_tx.common_rx_tx_pll = "OFF",
+    i_altlvds_tx.coreclock_divide_by = 1,
+    i_altlvds_tx.data_rate = "800.0 Mbps",
+    i_altlvds_tx.deserialization_factor = SERDES_FACTOR,
+    i_altlvds_tx.differential_drive = 0,
+    i_altlvds_tx.enable_clock_pin_mode = "UNUSED",
+    i_altlvds_tx.implement_in_les = "OFF",
+    i_altlvds_tx.inclock_boost = 0,
+    i_altlvds_tx.inclock_data_alignment = "EDGE_ALIGNED",
+    i_altlvds_tx.inclock_period = 50000,
+    i_altlvds_tx.inclock_phase_shift = 0,
+    i_altlvds_tx.intended_device_family = "Cyclone V",
+    i_altlvds_tx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_out_core_c5",
+    i_altlvds_tx.lpm_type = "altlvds_tx",
+    i_altlvds_tx.multi_clock = "OFF",
+    i_altlvds_tx.number_of_channels = 1,
+    i_altlvds_tx.outclock_alignment = "EDGE_ALIGNED",
+    i_altlvds_tx.outclock_divide_by = 1,
+    i_altlvds_tx.outclock_duty_cycle = 50,
+    i_altlvds_tx.outclock_multiply_by = 1,
+    i_altlvds_tx.outclock_phase_shift = 0,
+    i_altlvds_tx.outclock_resource = "Dual-Regional clock",
+    i_altlvds_tx.output_data_rate = 800,
+    i_altlvds_tx.pll_compensation_mode = "AUTO",
+    i_altlvds_tx.pll_self_reset_on_loss_lock = "OFF",
+    i_altlvds_tx.preemphasis_setting = 0,
+    i_altlvds_tx.refclk_frequency = "20.000000 MHz",
+    i_altlvds_tx.registered_input = "OFF",
+    i_altlvds_tx.use_external_pll = "ON",
+    i_altlvds_tx.use_no_phase_shift = "ON",
+    i_altlvds_tx.vod_setting = 0,
+    i_altlvds_tx.clk_src_is_pll = "off";
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From b94cc8afb148191137e79a1344440c9d0c7ef24e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 31 Oct 2016 13:13:48 -0400
Subject: [PATCH 653/972] altera- cmos cores

---
 library/altera/common/ad_cmos_out.v           |  81 +++++---------
 library/altera/common/ad_cmos_out_core_c5.v   |  69 ++++++++++++
 .../axi_ad9361/altera/axi_ad9361_lvds_if.v    | 102 +++++++-----------
 3 files changed, 136 insertions(+), 116 deletions(-)
 create mode 100644 library/altera/common/ad_cmos_out_core_c5.v

diff --git a/library/altera/common/ad_cmos_out.v b/library/altera/common/ad_cmos_out.v
index c54d53d5d..edbc797fa 100644
--- a/library/altera/common/ad_cmos_out.v
+++ b/library/altera/common/ad_cmos_out.v
@@ -37,55 +37,38 @@
 
 `timescale 1ns/100ps
 
-module ad_cmos_out (
+module __ad_cmos_out__ #(
+
+  parameter   DEVICE_TYPE = 0,
+  parameter   SINGLE_ENDED = 0,
+  parameter   IODELAY_ENABLE = 0,
+  parameter   IODELAY_CTRL = 0,
+  parameter   IODELAY_GROUP = "dev_if_delay_group") (
 
   // data interface
 
-  tx_clk,
-  tx_data_p,
-  tx_data_n,
-  tx_data_out,
+  input               tx_clk,
+  input               tx_data_p,
+  input               tx_data_n,
+  output              tx_data_out,
 
   // delay-data interface
 
-  up_clk,
-  up_dld,
-  up_dwdata,
-  up_drdata,
+  input               up_clk,
+  input               up_dld,
+  input       [ 4:0]  up_dwdata,
+  output      [ 4:0]  up_drdata,
 
   // delay-cntrl interface
 
-  delay_clk,
-  delay_rst,
-  delay_locked);
+  input               delay_clk,
+  input               delay_rst,
+  output              delay_locked);
 
-  // parameters
+  // local parameter
 
-  parameter   DEVICE_TYPE = 0;
-  parameter   SINGLE_ENDED = 0;
-  parameter   IODELAY_ENABLE = 0;
-  parameter   IODELAY_CTRL = 0;
-  parameter   IODELAY_GROUP = "dev_if_delay_group";
-
-  // data interface
-
-  input               tx_clk;
-  input               tx_data_p;
-  input               tx_data_n;
-  output              tx_data_out;
-
-  // delay-data interface
-
-  input               up_clk;
-  input               up_dld;
-  input       [ 4:0]  up_dwdata;
-  output      [ 4:0]  up_drdata;
-
-  // delay-cntrl interface
-
-  input               delay_clk;
-  input               delay_rst;
-  output              delay_locked;
+  localparam ARRIA10 = 0;
+  localparam CYCLONE5 = 1;
 
   // defaults
 
@@ -95,8 +78,8 @@ module ad_cmos_out (
   // instantiations
 
   generate
-  if (DEVICE_TYPE == 0) begin
-  alt_ddio_out i_tx_data_oddr (
+  if (DEVICE_TYPE == ARRIA10) begin
+  __ad_cmos_out_1__ i_tx_data_oddr (
     .ck (tx_clk),
     .din ({tx_data_p, tx_data_n}),
     .pad_out (tx_data_out));
@@ -104,19 +87,11 @@ module ad_cmos_out (
   endgenerate
 
   generate
-  if (DEVICE_TYPE == 1) begin
-  altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
-    .outclock (tx_clk),
-    .datain_h (tx_data_p),
-    .datain_l (tx_data_n),
-    .dataout (tx_data_out),
-    .outclocken (1'b1),
-    .oe_out (),
-    .oe (1'b1),
-    .aclr (1'b0),
-    .aset (1'b0),
-    .sclr (1'b0),
-    .sset (1'b0));
+  if (DEVICE_TYPE == CYCLONE5) begin
+  ad_cmos_out_core_c5 i_tx_data_oddr (
+    .clk (tx_clk),
+    .din ({tx_data_p, tx_data_n}),
+    .pad_out (tx_data_out));
   end
   endgenerate
 
diff --git a/library/altera/common/ad_cmos_out_core_c5.v b/library/altera/common/ad_cmos_out_core_c5.v
new file mode 100644
index 000000000..972362e25
--- /dev/null
+++ b/library/altera/common/ad_cmos_out_core_c5.v
@@ -0,0 +1,69 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+module ad_cmos_out_core_c5 (
+
+  // data interface
+
+  input               clk,
+  input   [ 1:0]      din,
+  output              pad_out);
+
+  // instantiations
+
+  altddio_out #(
+    .width (1),
+    .lpm_hint ("UNUSED"))
+  i_altddio_out (
+    .outclock (clk),
+    .datain_h (din[1]),
+    .datain_l (din[0]),
+    .dataout (pad_out),
+    .outclocken (1'b1),
+    .oe_out (),
+    .oe (1'b1),
+    .aclr (1'b0),
+    .aset (1'b0),
+    .sclr (1'b0),
+    .sset (1'b0));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
index 1763d272b..f9ebfbcba 100644
--- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
@@ -384,9 +384,9 @@ module axi_ad9361_lvds_if #(
   // receive data path interface
 
   ad_serdes_in #(
-    .DATA_WIDTH(6),
-    .SERDES_FACTOR(4),
-    .DEVICE_TYPE(DEVICE_TYPE))
+    .DATA_WIDTH (6),
+    .SERDES_FACTOR (4),
+    .DEVICE_TYPE (DEVICE_TYPE))
   ad_serdes_data_in (
     .rst (mmcm_rst),
     .clk (s_clk),
@@ -415,9 +415,9 @@ module axi_ad9361_lvds_if #(
   // receive frame interface
 
   ad_serdes_in #(
-    .DATA_WIDTH(1),
-    .SERDES_FACTOR(4),
-    .DEVICE_TYPE(DEVICE_TYPE))
+    .DATA_WIDTH (1),
+    .SERDES_FACTOR (4),
+    .DEVICE_TYPE (DEVICE_TYPE))
   ad_serdes_frame_in (
     .rst (mmcm_rst),
     .clk (s_clk),
@@ -446,9 +446,9 @@ module axi_ad9361_lvds_if #(
   // transmit data interface
 
   ad_serdes_out #(
-    .DATA_WIDTH(6),
-    .SERDES_FACTOR(4),
-    .DEVICE_TYPE(DEVICE_TYPE))
+    .DATA_WIDTH (6),
+    .SERDES_FACTOR (4),
+    .DEVICE_TYPE (DEVICE_TYPE))
   ad_serdes_data_out (
     .rst (mmcm_rst),
     .clk (s_clk),
@@ -458,19 +458,19 @@ module axi_ad9361_lvds_if #(
     .data_s1 (tx_p_data_d_1),
     .data_s2 (tx_p_data_d_2),
     .data_s3 (tx_p_data_d_3),
-    .data_s4 (6'b0),
-    .data_s5 (6'b0),
-    .data_s6 (6'b0),
-    .data_s7 (6'b0),
+    .data_s4 (6'd0),
+    .data_s5 (6'd0),
+    .data_s6 (6'd0),
+    .data_s7 (6'd0),
     .data_out_p (tx_data_out_p),
     .data_out_n (tx_data_out_n));
 
   // transmit frame interface
 
   ad_serdes_out #(
-    .DATA_WIDTH(1),
-    .SERDES_FACTOR(4),
-    .DEVICE_TYPE(DEVICE_TYPE))
+    .DATA_WIDTH (1),
+    .SERDES_FACTOR (4),
+    .DEVICE_TYPE (DEVICE_TYPE))
   ad_serdes_frame_out (
     .rst (mmcm_rst),
     .clk (s_clk),
@@ -480,10 +480,10 @@ module axi_ad9361_lvds_if #(
     .data_s1 (tx_p_frame[1]),
     .data_s2 (tx_p_frame[2]),
     .data_s3 (tx_p_frame[3]),
-    .data_s4 (1'b1),
-    .data_s5 (1'b1),
-    .data_s6 (1'b1),
-    .data_s7 (1'b1),
+    .data_s4 (1'd0),
+    .data_s5 (1'd0),
+    .data_s6 (1'd0),
+    .data_s7 (1'd0),
     .data_out_p (tx_frame_out_p),
     .data_out_n (tx_frame_out_n));
 
@@ -502,17 +502,17 @@ module axi_ad9361_lvds_if #(
     .data_s1 (~dac_clksel),
     .data_s2 (dac_clksel),
     .data_s3 (~dac_clksel),
-    .data_s4 (1'b0),
-    .data_s5 (1'b0),
-    .data_s6 (1'b0),
-    .data_s7 (1'b0),
+    .data_s4 (1'd0),
+    .data_s5 (1'd0),
+    .data_s6 (1'd0),
+    .data_s7 (1'd0),
     .data_out_p (tx_clk_out_p),
     .data_out_n (tx_clk_out_n));
 
   // serdes clock interface
 
   ad_serdes_clk #(
-    .DEVICE_TYPE(DEVICE_TYPE))
+    .DEVICE_TYPE (DEVICE_TYPE))
   ad_serdes_clk (
     .rst (mmcm_rst),
     .clk_in_p (rx_clk_in_p),
@@ -534,47 +534,23 @@ module axi_ad9361_lvds_if #(
 
  // enable
 
-  ad_serdes_out #(
-    .DATA_WIDTH(1),
-    .SERDES_FACTOR(4),
-    .DEVICE_TYPE(DEVICE_TYPE))
-  i_enable(
-    .rst (mmcm_rst),
-    .clk (s_clk),
-    .div_clk (l_clk),
-    .loaden (loaden),
-    .data_s0 (enable_p_int),
-    .data_s1 (enable_p_int),
-    .data_s2 (enable_p_int),
-    .data_s3 (enable_p_int),
-    .data_s4 (1'b0),
-    .data_s5 (1'b0),
-    .data_s6 (1'b0),
-    .data_s7 (1'b0),
-    .data_out_p (enable),
-    .data_out_n ());
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE))
+  i_enable (
+    .tx_clk (l_clk),
+    .tx_data_p (enable_p_int),
+    .tx_data_n (enable_p_int),
+    .tx_data_out (enable));
 
   // txnrx
 
-    ad_serdes_out #(
-    .DATA_WIDTH(1),
-    .SERDES_FACTOR(4),
-    .DEVICE_TYPE(DEVICE_TYPE))
-  i_txnrx(
-    .rst (mmcm_rst),
-    .clk (s_clk),
-    .div_clk (l_clk),
-    .loaden (loaden),
-    .data_s0 (txnrx_p_int),
-    .data_s1 (txnrx_p_int),
-    .data_s2 (txnrx_p_int),
-    .data_s3 (txnrx_p_int),
-    .data_s4 (1'b0),
-    .data_s5 (1'b0),
-    .data_s6 (1'b0),
-    .data_s7 (1'b0),
-    .data_out_p (txnrx),
-    .data_out_n ());
+  ad_cmos_out #(
+    .DEVICE_TYPE (DEVICE_TYPE))
+  i_txnrx (
+    .tx_clk (l_clk),
+    .tx_data_p (txnrx_p_int),
+    .tx_data_n (txnrx_p_int),
+    .tx_data_out (txnrx));
 
 endmodule
 

From 9f4c5f806037f9f3008b96b074c083d2f95c5bc4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 31 Oct 2016 15:34:32 -0400
Subject: [PATCH 654/972] arradio/ad9361- updates

---
 library/altera/alt_serdes/alt_serdes_hw.tcl |  26 ++-
 library/axi_ad9361/axi_ad9361_hw.tcl        | 209 +++++++++-----------
 library/scripts/adi_ip_alt.tcl              |  89 +++++++--
 3 files changed, 185 insertions(+), 139 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index a1cebcaa5..a56e51f96 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -29,7 +29,7 @@ set_parameter_property SERDES_FACTOR DISPLAY_NAME SERDES_FACTOR
 set_parameter_property SERDES_FACTOR TYPE INTEGER
 set_parameter_property SERDES_FACTOR UNITS None
 set_parameter_property SERDES_FACTOR HDL_PARAMETER false
-set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
+set_parameter_property SERDES_FACTOR ALLOWED_RANGES {2 4 8}
 
 add_parameter CLKIN_FREQUENCY FLOAT 500.0
 set_parameter_property CLKIN_FREQUENCY DISPLAY_NAME CLKIN_FREQUENCY
@@ -66,6 +66,22 @@ proc p_alt_serdes {} {
 
   ## arria 10, serdes clock, data-in and data-out
 
+  if {($m_serdes_factor == 2) && ($m_device_family == "Arria 10")} {
+
+    add_hdl_instance alt_serdes_out altera_gpio
+    set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output}
+    set_instance_parameter_value alt_serdes_out {SIZE} {1}
+    set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0}
+    set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO}
+
+    return
+  }
+
+  if {($m_serdes_factor == 2) && ($m_device_family == "Cyclone V")} {
+
+    return
+  }
+
   if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} {
 
     add_instance alt_serdes_pll altera_iopll
@@ -109,6 +125,8 @@ proc p_alt_serdes {} {
     set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
     add_interface pll_reconfig avalon slave
     set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
+
+    return
   }
 
   if {($m_mode == "IN") && ($m_device_family == "Arria 10")} {
@@ -137,6 +155,8 @@ proc p_alt_serdes {} {
     set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out
     add_interface delay_locked conduit end
     set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked
+
+    return
   }
 
   if {($m_mode == "OUT") && ($m_device_family == "Arria 10")} {
@@ -161,6 +181,8 @@ proc p_alt_serdes {} {
     set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock
     add_interface data_s conduit end
     set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
+
+    return
   }
 
   ## cyclone v, serdes clock, data-in and data-out
@@ -205,6 +227,8 @@ proc p_alt_serdes {} {
     set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
     add_interface pll_reconfig avalon slave
     set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
+
+    return
   }
 }
 
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index c14fff648..397e8a0ea 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -1,85 +1,72 @@
 
-
 package require -exact qsys 13.0
 source ../scripts/adi_env.tcl
 source ../scripts/adi_ip_alt.tcl
 
-set_module_property NAME axi_ad9361
-set_module_property DESCRIPTION "AXI AD9361 Interface"
-set_module_property VERSION 1.0
-set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME axi_ad9361
-set_module_property ELABORATION_CALLBACK p_axi_ad9361
-
-# files
-
-add_fileset quartus_synth QUARTUS_SYNTH "p_axi_ad9361_fset" ""
-set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
-add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file ad_mul.v                 VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
-add_fileset_file ad_dcfilter.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
-add_fileset_file ad_pnmon.v               VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
-add_fileset_file ad_dds_sine.v            VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
-add_fileset_file ad_dds_1.v               VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
-add_fileset_file ad_dds.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
-add_fileset_file ad_datafmt.v             VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
-add_fileset_file ad_iqcor.v               VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
-add_fileset_file ad_addsub.v              VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v
-add_fileset_file ad_tdd_control.v         VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v
-add_fileset_file up_axi.v                 VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
-add_fileset_file up_xfer_cntrl.v          VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
-add_fileset_file up_xfer_status.v         VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
-add_fileset_file up_clock_mon.v           VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
-add_fileset_file up_delay_cntrl.v         VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
-add_fileset_file up_adc_common.v          VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
-add_fileset_file up_adc_channel.v         VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
-add_fileset_file up_dac_common.v          VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
-add_fileset_file up_dac_channel.v         VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
-add_fileset_file up_tdd_cntrl.v           VERILOG PATH $ad_hdl_dir/library/common/up_tdd_cntrl.v
-add_fileset_file axi_ad9361_lvds_if.v     VERILOG PATH altera/axi_ad9361_lvds_if.v
-add_fileset_file axi_ad9361_cmos_if.v     VERILOG PATH altera/axi_ad9361_cmos_if.v
-add_fileset_file axi_ad9361_rx_pnmon.v    VERILOG PATH axi_ad9361_rx_pnmon.v
-add_fileset_file axi_ad9361_rx_channel.v  VERILOG PATH axi_ad9361_rx_channel.v
-add_fileset_file axi_ad9361_rx.v          VERILOG PATH axi_ad9361_rx.v
-add_fileset_file axi_ad9361_tx_channel.v  VERILOG PATH axi_ad9361_tx_channel.v
-add_fileset_file axi_ad9361_tx.v          VERILOG PATH axi_ad9361_tx.v
-add_fileset_file axi_ad9361_tdd.v         VERILOG PATH axi_ad9361_tdd.v
-add_fileset_file axi_ad9361_tdd_if.v      VERILOG PATH axi_ad9361_tdd_if.v
-add_fileset_file axi_ad9361.v             VERILOG PATH axi_ad9361.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc     SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
-add_fileset_file axi_ad9361_constr.sdc    SDC     PATH axi_ad9361_constr.sdc
+ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab
+ad_ip_files axi_ad9361 [list\
+  $ad_hdl_dir/library/altera/common/ad_cmos_out_core_c5.v \
+  $ad_hdl_dir/library/altera/common/ad_serdes_in_core_c5.v \
+  $ad_hdl_dir/library/altera/common/ad_serdes_out_core_c5.v \
+  $ad_hdl_dir/library/altera/common/ad_mul.v \
+  $ad_hdl_dir/library/altera/common/ad_dcfilter.v \
+  $ad_hdl_dir/library/common/ad_rst.v \
+  $ad_hdl_dir/library/common/ad_pnmon.v \
+  $ad_hdl_dir/library/common/ad_dds_sine.v \
+  $ad_hdl_dir/library/common/ad_dds_1.v \
+  $ad_hdl_dir/library/common/ad_dds.v \
+  $ad_hdl_dir/library/common/ad_datafmt.v \
+  $ad_hdl_dir/library/common/ad_iqcor.v \
+  $ad_hdl_dir/library/common/ad_addsub.v \
+  $ad_hdl_dir/library/common/ad_tdd_control.v \
+  $ad_hdl_dir/library/common/up_axi.v \
+  $ad_hdl_dir/library/common/up_xfer_cntrl.v \
+  $ad_hdl_dir/library/common/up_xfer_status.v \
+  $ad_hdl_dir/library/common/up_clock_mon.v \
+  $ad_hdl_dir/library/common/up_delay_cntrl.v \
+  $ad_hdl_dir/library/common/up_adc_common.v \
+  $ad_hdl_dir/library/common/up_adc_channel.v \
+  $ad_hdl_dir/library/common/up_dac_common.v \
+  $ad_hdl_dir/library/common/up_dac_channel.v \
+  $ad_hdl_dir/library/common/up_tdd_cntrl.v \
+  altera/axi_ad9361_lvds_if.v \
+  altera/axi_ad9361_cmos_if.v \
+  axi_ad9361_rx_pnmon.v \
+  axi_ad9361_rx_channel.v \
+  axi_ad9361_rx.v \
+  axi_ad9361_tx_channel.v \
+  axi_ad9361_tx.v \
+  axi_ad9361_tdd.v \
+  axi_ad9361_tdd_if.v \
+  axi_ad9361.v \
+  $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
+  axi_ad9361_constr.sdc] \
+  axi_ad9361_fileset
 
 # parameters
 
-add_parameter DEVICE_FAMILY STRING
-set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
-set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
-set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
-set_parameter_property DEVICE_FAMILY ENABLED false
-
-add_parameter ID INTEGER 0
-add_parameter MODE_1R1T INTEGER 0
-add_parameter DEVICE_TYPE INTEGER 0
-add_parameter TDD_DISABLE INTEGER 0
-add_parameter CMOS_OR_LVDS_N INTEGER 0
-add_parameter ADC_DATAPATH_DISABLE INTEGER 0
-add_parameter ADC_USERPORTS_DISABLE INTEGER 0
-add_parameter ADC_DATAFORMAT_DISABLE INTEGER 0
-add_parameter ADC_DCFILTER_DISABLE INTEGER 0
-add_parameter ADC_IQCORRECTION_DISABLE INTEGER 0
-add_parameter DAC_IODELAY_ENABLE INTEGER 0
-add_parameter DAC_DATAPATH_DISABLE INTEGER 0
-add_parameter DAC_DDS_DISABLE INTEGER 0
-add_parameter DAC_USERPORTS_DISABLE INTEGER 0
-add_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
-add_parameter IO_DELAY_GROUP STRING "dev_if_delay_group"
+ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
+ad_ip_parameter ID INTEGER 0
+ad_ip_parameter MODE_1R1T INTEGER 0
+ad_ip_parameter DEVICE_TYPE INTEGER 0
+ad_ip_parameter TDD_DISABLE INTEGER 0
+ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0
+ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0
+ad_ip_parameter ADC_USERPORTS_DISABLE INTEGER 0
+ad_ip_parameter ADC_DATAFORMAT_DISABLE INTEGER 0
+ad_ip_parameter ADC_DCFILTER_DISABLE INTEGER 0
+ad_ip_parameter ADC_IQCORRECTION_DISABLE INTEGER 0
+ad_ip_parameter DAC_IODELAY_ENABLE INTEGER 0
+ad_ip_parameter DAC_DATAPATH_DISABLE INTEGER 0
+ad_ip_parameter DAC_DDS_DISABLE INTEGER 0
+ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0
+ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
+ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group}
 
 # interfaces
 
 ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
  
-# master-slave interface
-
 ad_alt_intf signal dac_sync_in input 1
 ad_alt_intf signal dac_sync_out output 1
 ad_alt_intf signal tdd_sync input 1
@@ -171,12 +158,37 @@ ad_alt_intf signal up_dac_gpio_out output 32
 ad_alt_intf signal up_adc_gpio_in input 32
 ad_alt_intf signal up_adc_gpio_out output 32
 
+# generated cores
+
+add_hdl_instance ad_serdes_clk_core alt_serdes
+set_instance_parameter_value ad_serdes_clk_core {MODE} {CLK}
+set_instance_parameter_value ad_serdes_clk_core {DDR_OR_SDR_N} {1}
+set_instance_parameter_value ad_serdes_clk_core {SERDES_FACTOR} {4}
+set_instance_parameter_value ad_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
+
+add_hdl_instance ad_serdes_in_core_a10 alt_serdes
+set_instance_parameter_value ad_serdes_in_core_a10 {MODE} {IN}
+set_instance_parameter_value ad_serdes_in_core_a10 {DDR_OR_SDR_N} {1}
+set_instance_parameter_value ad_serdes_in_core_a10 {SERDES_FACTOR} {4}
+set_instance_parameter_value ad_serdes_in_core_a10 {CLKIN_FREQUENCY} {250.0}
+
+add_hdl_instance ad_serdes_out_core_a10 alt_serdes
+set_instance_parameter_value ad_serdes_out_core_a10 {MODE} {OUT}
+set_instance_parameter_value ad_serdes_out_core_a10 {DDR_OR_SDR_N} {1}
+set_instance_parameter_value ad_serdes_out_core_a10 {SERDES_FACTOR} {4}
+set_instance_parameter_value ad_serdes_out_core_a10 {CLKIN_FREQUENCY} {250.0}
+
+add_hdl_instance ad_cmos_out_core_a10 alt_serdes
+set_instance_parameter_value ad_cmos_out_core_a10 {MODE} {OUT}
+set_instance_parameter_value ad_cmos_out_core_a10 {DDR_OR_SDR_N} {1}
+set_instance_parameter_value ad_cmos_out_core_a10 {SERDES_FACTOR} {2}
+set_instance_parameter_value ad_cmos_out_core_a10 {CLKIN_FREQUENCY} {250.0}
+
 # updates
 
-proc p_axi_ad9361 {} {
+proc axi_ad9361_elab {} {
 
   set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N]
-  set m_device_family [get_parameter_value DEVICE_FAMILY]
 
   add_interface device_if conduit end
   set_interface_property device_if associatedClock none
@@ -210,58 +222,13 @@ proc p_axi_ad9361 {} {
 
   add_interface_port device_if enable enable Output 1
   add_interface_port device_if txnrx txnrx Output 1
-
-  if {$m_device_family == "Arria 10"} {
-
-    add_hdl_instance alt_serdes_clk_core alt_serdes
-    set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK}
-    set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1}
-    set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4}
-    set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
-
-    add_hdl_instance alt_serdes_in_core alt_serdes
-    set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
-    set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
-    set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
-    set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0}
-
-    add_hdl_instance alt_serdes_out_core alt_serdes
-    set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
-    set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
-    set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4}
-    set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0}
-
-    add_hdl_instance alt_ddio_in altera_gpio
-    set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
-    set_instance_parameter_value alt_ddio_in {SIZE} {1}
-    set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
-    set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
-
-    add_hdl_instance alt_ddio_out altera_gpio
-    set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
-    set_instance_parameter_value alt_ddio_out {SIZE} {1}
-    set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
-    set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
-  }
-
-  if {$m_device_family == "Cyclone V"} {
-
-    ## add_hdl_instance do not work here (pending altera support)
-  }
 }
 
-proc p_axi_ad9361_fset {entityName} {
+proc axi_ad9361_fileset {entityName} {
 
-  ad_ip_file ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
-  ad_ip_file ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
-  ad_ip_file ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
-  ad_ip_file ad_cmos_in.v ad_cmos_in.v ad_cmos_in_core
-  ad_ip_file ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core
-
-  add_fileset_file ad_serdes_in.v VERILOG PATH ad_serdes_in.v
-  add_fileset_file ad_serdes_out.v VERILOG PATH ad_serdes_out.v
-  add_fileset_file ad_serdes_clk.v VERILOG PATH ad_serdes_clk.v
-  add_fileset_file ad_cmos_in.v VERILOG PATH ad_cmos_in.v
-  add_fileset_file ad_cmos_out.v VERILOG PATH ad_cmos_out.v
+  ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core
+  ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
+  ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
+  ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
 }
 
diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl
index c1db04ff4..e00ad3a7a 100644
--- a/library/scripts/adi_ip_alt.tcl
+++ b/library/scripts/adi_ip_alt.tcl
@@ -1,4 +1,5 @@
-
+###################################################################################################
+###################################################################################################
 # keep interface-mess out of the way - keeping it pretty is a waste of time
 
 proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
@@ -89,41 +90,87 @@ proc ad_generate_module_inst { inst_name mark source_file target_file } {
   close $fp_target
 }
 
+###################################################################################################
+###################################################################################################
+
+proc ad_ip_create {pname pdesc {pelabfunction ""} {pcomposefunction ""}} {
+
+  set_module_property NAME $pname
+  set_module_property DESCRIPTION $pdesc
+  set_module_property VERSION 1.0
+  set_module_property GROUP "Analog Devices"
+  set_module_property DISPLAY_NAME $pname
+  
+  if {$pelabfunction ne ""} {
+    set_module_property ELABORATION_CALLBACK $pelabfunction
+  }
+
+  if {$pcomposefunction ne ""} {
+    set_module_property ELABORATION_CALLBACK $pcomposefunction
+  }
+}
+
+###################################################################################################
+###################################################################################################
+
 proc ad_ip_parameter {pname ptype pdefault} {
 
+  if {$pname eq "DEVICE_FAMILY"} {
+    add_parameter DEVICE_FAMILY STRING
+    set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
+    set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
+    set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
+    set_parameter_property DEVICE_FAMILY ENABLED false
+    return
+  }
+
   add_parameter $pname $ptype $pdefault
   set_parameter_property $pname HDL_PARAMETER true
   set_parameter_property $pname ENABLED true
 }
 
-proc ad_ip_files {pname pfiles {pfunction ""}} {
+###################################################################################################
+###################################################################################################
 
-  set ftopfile [lindex $pfiles end]
-  set pfiles [lreplace $pfiles end end]
+proc ad_ip_addfile {pname pfile} {
+
+  set pmodule [file tail $pfile]  
+
+  regsub {\..$} $pmodule {} mname
+  if {$pname eq $mname} {
+    add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
+    return
+  }
+
+  set ptype [file extension $pfile]
+  if {$ptype eq ".v"} {
+    add_fileset_file $pmodule VERILOG PATH $pfile
+    return
+  }
+  if {$ptype eq ".sdc"} {
+    add_fileset_file $pmodule SDC PATH $pfile
+    return
+  }
+}
+
+proc ad_ip_files {pname pfiles {pfunction ""}} {
 
   add_fileset quartus_synth QUARTUS_SYNTH $pfunction ""
   set_fileset_property quartus_synth TOP_LEVEL $pname
-
   foreach pfile $pfiles {
-    set pmodule [file tail $pfile]
-    add_fileset_file $pmodule VERILOG PATH $pfile
+    ad_ip_addfile $pname $pfile
   }
-  set pfile $ftopfile
-  set pmodule [file tail $pfile]
-  add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
 
   add_fileset quartus_sim SIM_VERILOG $pfunction ""
   set_fileset_property quartus_sim TOP_LEVEL $pname
-
   foreach pfile $pfiles {
-    set pmodule [file tail $pfile]
-    add_fileset_file $pmodule VERILOG PATH $pfile
+    ad_ip_addfile $pname $pfile
   }
-  set pfile $ftopfile
-  set pmodule [file tail $pfile]
-  add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
 }
 
+###################################################################################################
+###################################################################################################
+
 proc ad_ip_intf_s_axi {aclk arstn} {
 
   add_interface s_axi_clock clock end
@@ -157,7 +204,10 @@ proc ad_ip_intf_s_axi {aclk arstn} {
   add_interface_port s_axi s_axi_rready rready Input 1
 }
 
-proc ad_ip_file {ifile ofile flist} {
+###################################################################################################
+###################################################################################################
+
+proc ad_ip_modfile {ifile ofile flist} {
 
   global ad_hdl_dir
 
@@ -179,5 +229,10 @@ proc ad_ip_file {ifile ofile flist} {
 
   close $srcfile
   close $dstfile
+
+  ad_ip_addfile ad_ip_addfile $ofile
 }
 
+###################################################################################################
+###################################################################################################
+

From 5eff357568243bea9fc77178274c6097e16ed53d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 1 Nov 2016 10:06:57 +0200
Subject: [PATCH 655/972] up_tdd_cntrl: Fix memory map register writes

---
 library/common/up_tdd_cntrl.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v
index 2a83d7b94..71c7ce4e8 100644
--- a/library/common/up_tdd_cntrl.v
+++ b/library/common/up_tdd_cntrl.v
@@ -332,13 +332,13 @@ module up_tdd_cntrl (
         up_tdd_tx_on_2 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
-        up_tdd_rx_off_2 <= up_wdata[23:0];
+        up_tdd_tx_off_2 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
         up_tdd_rx_dp_on_2 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
-        up_tdd_tx_dp_off_2 <= up_wdata[23:0];
+        up_tdd_rx_dp_off_2 <= up_wdata[23:0];
       end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin
         up_tdd_tx_dp_on_2 <= up_wdata[23:0];

From 671a547c2bd91967d94a3154aee5fe4eac8085ac Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 31 Oct 2016 15:45:26 -0400
Subject: [PATCH 656/972] hdlmake- updates

---
 projects/adrv9371x/a10gx/Makefile  | 11 ++++--
 projects/adrv9371x/a10soc/Makefile | 11 ++++--
 projects/arradio/c5soc/Makefile    | 36 ------------------
 projects/daq1/a10gx/Makefile       |  9 ++++-
 projects/fmcomms2/a10gx/Makefile   | 39 -------------------
 projects/pzsdr/Makefile            |  7 ++++
 projects/pzsdr1/Makefile           |  6 +--
 projects/usrpe31x/Makefile         | 60 +++---------------------------
 8 files changed, 37 insertions(+), 142 deletions(-)

diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile
index 947157310..ce1259b4a 100644
--- a/projects/adrv9371x/a10gx/Makefile
+++ b/projects/adrv9371x/a10gx/Makefile
@@ -19,6 +19,12 @@ M_DEPS += ../common/adrv9371x_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
+M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
+M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
 M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
@@ -48,17 +54,15 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_iqcor.v
-M_DEPS += ../../../library/common/ad_jesd_align.v
 M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
 M_DEPS += ../../../library/common/up_adc_channel.v
@@ -67,7 +71,6 @@ M_DEPS += ../../../library/common/up_axi.v
 M_DEPS += ../../../library/common/up_clock_mon.v
 M_DEPS += ../../../library/common/up_dac_channel.v
 M_DEPS += ../../../library/common/up_dac_common.v
-M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index fe52269d0..1999474d0 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -19,6 +19,12 @@ M_DEPS += ../common/adrv9371x_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
+M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
+M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
+M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
 M_DEPS += ../../../library/altera/common/ad_dcfilter.v
 M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
@@ -48,17 +54,15 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
 M_DEPS += ../../../library/common/ad_iqcor.v
-M_DEPS += ../../../library/common/ad_jesd_align.v
 M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
 M_DEPS += ../../../library/common/up_adc_channel.v
@@ -67,7 +71,6 @@ M_DEPS += ../../../library/common/up_axi.v
 M_DEPS += ../../../library/common/up_clock_mon.v
 M_DEPS += ../../../library/common/up_dac_channel.v
 M_DEPS += ../../../library/common/up_dac_common.v
-M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 6918a8b80..4de40a701 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -19,25 +19,7 @@ M_DEPS += ../common/arradio_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys
 M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
-M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
-M_DEPS += ../../../library/altera/common/ad_cmos_in.v
-M_DEPS += ../../../library/altera/common/ad_cmos_out.v
-M_DEPS += ../../../library/altera/common/ad_dcfilter.v
-M_DEPS += ../../../library/altera/common/ad_mul.v
-M_DEPS += ../../../library/altera/common/ad_serdes_clk.v
-M_DEPS += ../../../library/altera/common/ad_serdes_in.v
-M_DEPS += ../../../library/altera/common/ad_serdes_out.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
-M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_cmos_if.v
-M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
@@ -57,28 +39,10 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/common/ad_addsub.v
-M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_dds.v
-M_DEPS += ../../../library/common/ad_dds_1.v
-M_DEPS += ../../../library/common/ad_dds_sine.v
-M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_mem.v
-M_DEPS += ../../../library/common/ad_pnmon.v
-M_DEPS += ../../../library/common/ad_rst.v
-M_DEPS += ../../../library/common/ad_tdd_control.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
-M_DEPS += ../../../library/common/up_adc_channel.v
-M_DEPS += ../../../library/common/up_adc_common.v
 M_DEPS += ../../../library/common/up_axi.v
-M_DEPS += ../../../library/common/up_clock_mon.v
-M_DEPS += ../../../library/common/up_dac_channel.v
-M_DEPS += ../../../library/common/up_dac_common.v
-M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_tdd_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_status.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
diff --git a/projects/daq1/a10gx/Makefile b/projects/daq1/a10gx/Makefile
index 3ce97770a..8d7088479 100644
--- a/projects/daq1/a10gx/Makefile
+++ b/projects/daq1/a10gx/Makefile
@@ -19,11 +19,14 @@ M_DEPS += ../common/daq1_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/common/ad_serdes_in.v
+M_DEPS += ../../../library/axi_ad9122/PATH
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_channel.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_core.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_hw.tcl
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_if.v
+M_DEPS += ../../../library/axi_ad9684/PATH
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684.v
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684_channel.v
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684_hw.tcl
@@ -48,10 +51,12 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
 M_DEPS += ../../../library/common/ad_dds_1.v
 M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/sync_bits.v
@@ -65,6 +70,8 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
@@ -80,8 +87,6 @@ M_DEPS += ../../../library/util_upack/util_upack_dsf.v
 M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
 M_DEPS += ../../../library/xilinx/common/ad_mmcm_drp.v
 M_DEPS += ../../../library/xilinx/common/ad_mul.v
-M_DEPS += ../../../library/xilinx/common/ad_serdes_clk.v
-M_DEPS += ../../../library/xilinx/common/ad_serdes_in.v
 M_DEPS += ../../../library/xilinx/common/ad_serdes_out.v
 
 
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 6011b3a7a..8776a9a5e 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -19,28 +19,7 @@ M_DEPS += ../common/fmcomms2_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
-M_DEPS += ../../../altera/axi_ad9361_cmos_if.v
-M_DEPS += ../../../altera/axi_ad9361_lvds_if.v
-M_DEPS += ../../../library/altera/common/ad_cmos_clk.v
-M_DEPS += ../../../library/altera/common/ad_cmos_in.v
-M_DEPS += ../../../library/altera/common/ad_cmos_out.v
-M_DEPS += ../../../library/altera/common/ad_dcfilter.v
-M_DEPS += ../../../library/altera/common/ad_lvds_clk.v
-M_DEPS += ../../../library/altera/common/ad_lvds_in.v
-M_DEPS += ../../../library/altera/common/ad_lvds_out.v
-M_DEPS += ../../../library/altera/common/ad_mul.v
-M_DEPS += ../../../library/altera/common/ad_serdes_clk.v
-M_DEPS += ../../../library/altera/common/ad_serdes_in.v
-M_DEPS += ../../../library/altera/common/ad_serdes_out.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
@@ -60,28 +39,10 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/common/ad_addsub.v
-M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_dds.v
-M_DEPS += ../../../library/common/ad_dds_1.v
-M_DEPS += ../../../library/common/ad_dds_sine.v
-M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_mem.v
-M_DEPS += ../../../library/common/ad_pnmon.v
-M_DEPS += ../../../library/common/ad_rst.v
-M_DEPS += ../../../library/common/ad_tdd_control.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
-M_DEPS += ../../../library/common/up_adc_channel.v
-M_DEPS += ../../../library/common/up_adc_common.v
 M_DEPS += ../../../library/common/up_axi.v
-M_DEPS += ../../../library/common/up_clock_mon.v
-M_DEPS += ../../../library/common/up_dac_channel.v
-M_DEPS += ../../../library/common/up_dac_common.v
-M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_tdd_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_status.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
diff --git a/projects/pzsdr/Makefile b/projects/pzsdr/Makefile
index a51f74003..6ee1e9a38 100644
--- a/projects/pzsdr/Makefile
+++ b/projects/pzsdr/Makefile
@@ -13,6 +13,8 @@ all:
 	-make -C ccpci_lvds all
 	-make -C ccusb_lvds all
 	-make -C ccbox_lvds all
+	-make -C ccbrk_cmos all
+	-make -C ccbrk_lvds all
 
 
 clean: 
@@ -22,6 +24,9 @@ clean:
 	make -C ccpci_lvds clean
 	make -C ccusb_lvds clean
 	make -C ccbox_lvds clean
+	make -C ccbrk_cmos clean
+	make -C ccbrk_lvds clean
+
 
 clean-all:
 	make -C ccbrk_cmos clean-all
@@ -30,6 +35,8 @@ clean-all:
 	make -C ccpci_lvds clean-all
 	make -C ccusb_lvds clean-all
 	make -C ccbox_lvds clean-all
+	make -C ccbrk_cmos clean-all
+	make -C ccbrk_lvds clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile
index 5db7627e6..d31684d1c 100644
--- a/projects/pzsdr1/Makefile
+++ b/projects/pzsdr1/Makefile
@@ -8,20 +8,20 @@
 .PHONY: all clean clean-all 
 all:
 	-make -C ccbox_lvds all
-	-make -C ccbrk_lvds all
 	-make -C ccbrk_cmos all
+	-make -C ccbrk_lvds all
 
 
 clean: 
 	make -C ccbox_lvds clean
-	make -C ccbrk_lvds clean
 	make -C ccbrk_cmos clean
+	make -C ccbrk_lvds clean
 
 
 clean-all:
 	make -C ccbox_lvds clean-all
-	make -C ccbrk_lvds clean-all
 	make -C ccbrk_cmos clean-all
+	make -C ccbrk_lvds clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/usrpe31x/Makefile b/projects/usrpe31x/Makefile
index 6d71eb7cc..620ee8f00 100644
--- a/projects/usrpe31x/Makefile
+++ b/projects/usrpe31x/Makefile
@@ -5,65 +5,17 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../scripts/adi_project.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_board.tcl
-M_DEPS += ../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
-M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../library/util_upack/util_upack.xpr
-M_DEPS += ../../library/util_tdd_sync/util_tdd_sync.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib usrpe31x.sdk/system_top.hdf
+.PHONY: all clean clean-all 
+all:
+	-make -C system_project.tcl all
 
 
 clean: 
-	rm -rf $(M_FLIST)
+	make -C system_project.tcl clean
 
 
-clean-all:clean
-	make -C ../../library/axi_ad9361 clean
-	make -C ../../library/axi_dmac clean
-	make -C ../../library/util_cpack clean
-	make -C ../../library/util_upack clean
-	make -C ../../library/util_tdd_sync clean
-
-
-usrpe31x.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> usrpe31x_vivado.log 2>&1
-
-
-lib:
-	make -C ../../library/axi_ad9361
-	make -C ../../library/axi_dmac
-	make -C ../../library/util_cpack
-	make -C ../../library/util_upack
-	make -C ../../library/util_tdd_sync
+clean-all:
+	make -C system_project.tcl clean-all
 
 ####################################################################################
 ####################################################################################

From 1e0fed82f766d20fcdecc44903d35865a1f52719 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 1 Nov 2016 12:40:48 -0400
Subject: [PATCH 657/972] alt_serdes- a10 ddio fixes

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 14 ++++++++++++--
 library/altera/common/ad_cmos_out.v         |  6 +++---
 library/axi_ad9361/axi_ad9361_hw.tcl        |  6 +++---
 projects/fmcomms2/common/fmcomms2_qsys.tcl  |  1 +
 4 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index a56e51f96..e66c515dc 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -64,24 +64,34 @@ proc p_alt_serdes {} {
     set m_ld_duty_cycle 25.0
   }
 
-  ## arria 10, serdes clock, data-in and data-out
+  ## arria 10, cmos data-in and data-out
 
   if {($m_serdes_factor == 2) && ($m_device_family == "Arria 10")} {
 
-    add_hdl_instance alt_serdes_out altera_gpio
+    add_instance alt_serdes_out altera_gpio
     set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output}
     set_instance_parameter_value alt_serdes_out {SIZE} {1}
     set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0}
     set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO}
+    add_interface clk conduit end
+    set_interface_property clk EXPORT_OF alt_serdes_out.ck
+    add_interface din conduit end
+    set_interface_property din EXPORT_OF alt_serdes_out.din
+    add_interface pad_out conduit end
+    set_interface_property pad_out EXPORT_OF alt_serdes_out.pad_out
 
     return
   }
 
+  ## cyclone v, cmos data-in and data-out
+
   if {($m_serdes_factor == 2) && ($m_device_family == "Cyclone V")} {
 
     return
   }
 
+  ## arria 10, serdes clock, data-in and data-out
+
   if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} {
 
     add_instance alt_serdes_pll altera_iopll
diff --git a/library/altera/common/ad_cmos_out.v b/library/altera/common/ad_cmos_out.v
index edbc797fa..cdec954dd 100644
--- a/library/altera/common/ad_cmos_out.v
+++ b/library/altera/common/ad_cmos_out.v
@@ -80,9 +80,9 @@ module __ad_cmos_out__ #(
   generate
   if (DEVICE_TYPE == ARRIA10) begin
   __ad_cmos_out_1__ i_tx_data_oddr (
-    .ck (tx_clk),
-    .din ({tx_data_p, tx_data_n}),
-    .pad_out (tx_data_out));
+    .clk_export (tx_clk),
+    .din_export ({tx_data_p, tx_data_n}),
+    .pad_out_export (tx_data_out));
   end
   endgenerate
 
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 397e8a0ea..eb936d355 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -226,9 +226,9 @@ proc axi_ad9361_elab {} {
 
 proc axi_ad9361_fileset {entityName} {
 
-  ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core
-  ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
-  ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
+  ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core_a10
+  ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core_a10
+  ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core_a10
   ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
 }
 
diff --git a/projects/fmcomms2/common/fmcomms2_qsys.tcl b/projects/fmcomms2/common/fmcomms2_qsys.tcl
index 2196c97b0..77b96aa51 100644
--- a/projects/fmcomms2/common/fmcomms2_qsys.tcl
+++ b/projects/fmcomms2/common/fmcomms2_qsys.tcl
@@ -5,6 +5,7 @@
 
 add_instance axi_ad9361 axi_ad9361 1.0
 set_instance_parameter_value axi_ad9361 {ID} {0}
+set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {0}
 
 add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
 add_connection sys_clk.clk axi_ad9361.s_axi_clock

From 1cbea90bac1836bbffdd93392c9f8e075e9f29d2 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 1 Nov 2016 12:41:11 -0400
Subject: [PATCH 658/972] altera - a10gx bank swap

---
 projects/fmcomms2/a10gx/system_project.tcl | 74 +++++++++++-----------
 1 file changed, 38 insertions(+), 36 deletions(-)

diff --git a/projects/fmcomms2/a10gx/system_project.tcl b/projects/fmcomms2/a10gx/system_project.tcl
index 903b406b3..5a2fb02c5 100644
--- a/projects/fmcomms2/a10gx/system_project.tcl
+++ b/projects/fmcomms2/a10gx/system_project.tcl
@@ -14,40 +14,38 @@ set_global_assignment -name TOP_LEVEL_ENTITY system_top
 
 # lane interface
 
-set_location_assignment PIN_AV15 -to rx_clk_in             ; ## G6   FMC_LPC_LA00_CC_P
-set_location_assignment PIN_AU15 -to "rx_clk_in(n)"        ; ## G7   FMC_LPC_LA00_CC_N
-set_location_assignment PIN_AT10 -to rx_frame_in           ; ## D8   FMC_LPC_LA01_CC_P
-set_location_assignment PIN_AR11 -to "rx_frame_in(n)"      ; ## D9   FMC_LPC_LA01_CC_N
-set_location_assignment PIN_AR22 -to rx_data_in[0]         ; ## H7   FMC_LPC_LA02_P
-set_location_assignment PIN_AT22 -to "rx_data_in[0](n)"    ; ## H8   FMC_LPC_LA02_N
-set_location_assignment PIN_AR20 -to rx_data_in[1]         ; ## G9   FMC_LPC_LA03_P
-set_location_assignment PIN_AR19 -to "rx_data_in[1](n)"    ; ## G10  FMC_LPC_LA03_N
-set_location_assignment PIN_AN20 -to rx_data_in[2]         ; ## H10  FMC_LPC_LA04_P
-set_location_assignment PIN_AP19 -to "rx_data_in[2](n)"    ; ## H11  FMC_LPC_LA04_N
-set_location_assignment PIN_AV11 -to rx_data_in[3]         ; ## D11  FMC_LPC_LA05_P
-set_location_assignment PIN_AW11 -to "rx_data_in[3](n)"    ; ## D12  FMC_LPC_LA05_N
-set_location_assignment PIN_AV14 -to rx_data_in[4]         ; ## C10  FMC_LPC_LA06_P
-set_location_assignment PIN_AW14 -to "rx_data_in[4](n)"    ; ## C11  FMC_LPC_LA06_N
-set_location_assignment PIN_AT17 -to rx_data_in[5]         ; ## H13  FMC_LPC_LA07_P
-set_location_assignment PIN_AU17 -to "rx_data_in[5](n)"    ; ## H14  FMC_LPC_LA07_N
-set_location_assignment PIN_AP18 -to tx_clk_out            ; ## G12  FMC_LPC_LA08_P
-set_location_assignment PIN_AN19 -to "tx_clk_out(n)"       ; ## G13  FMC_LPC_LA08_N
-set_location_assignment PIN_AW13 -to tx_frame_out          ; ## D14  FMC_LPC_LA09_P
-set_location_assignment PIN_AV13 -to "tx_frame_out(n)"     ; ## D15  FMC_LPC_LA09_N
-set_location_assignment PIN_AT14 -to tx_data_out[0]        ; ## H16  FMC_LPC_LA11_P
-set_location_assignment PIN_AR14 -to "tx_data_out[0](n)"   ; ## H17  FMC_LPC_LA11_N
-set_location_assignment PIN_AR16 -to tx_data_out[1]        ; ## G15  FMC_LPC_LA12_P
-set_location_assignment PIN_AP16 -to "tx_data_out[1](n)"   ; ## G16  FMC_LPC_LA12_N
-set_location_assignment PIN_AR17 -to tx_data_out[2]        ; ## D17  FMC_LPC_LA13_P
-set_location_assignment PIN_AP17 -to "tx_data_out[2](n)"   ; ## D18  FMC_LPC_LA13_N
-set_location_assignment PIN_AR15 -to tx_data_out[3]        ; ## C14  FMC_LPC_LA10_P
-set_location_assignment PIN_AT15 -to "tx_data_out[3](n)"   ; ## C15  FMC_LPC_LA10_N
-set_location_assignment PIN_AW18 -to tx_data_out[4]        ; ## C18  FMC_LPC_LA14_P
-set_location_assignment PIN_AV18 -to "tx_data_out[4](n)"   ; ## C19  FMC_LPC_LA14_N
-set_location_assignment PIN_AR9  -to tx_data_out[5]        ; ## H19  FMC_LPC_LA15_P
-set_location_assignment PIN_AT9  -to "tx_data_out[5](n)"   ; ## H20  FMC_LPC_LA15_N
-set_location_assignment PIN_AT13 -to enable]               ; ## G18  FMC_LPC_LA16_P
-set_location_assignment PIN_AU13 -to txnrx]                ; ## G19  FMC_LPC_LA16_N
+set_location_assignment PIN_AV15 -to rx_clk_in             ; ## G6   FMC_LPC_LA00_CC_P (3B)
+set_location_assignment PIN_AU15 -to "rx_clk_in(n)"        ; ## G7   FMC_LPC_LA00_CC_N (3B)
+set_location_assignment PIN_AV19 -to rx_frame_in           ; ## D20  FMC_LPC_LA17_CC_P (3B) ## D8   FMC_LPC_LA01_CC_P (3C) PIN_AT10
+set_location_assignment PIN_AW19 -to "rx_frame_in(n)"      ; ## D21  FMC_LPC_LA17_CC_N (3B) ## D9   FMC_LPC_LA01_CC_N (3C) PIN_AR11
+set_location_assignment PIN_AR22 -to rx_data_in[0]         ; ## H7   FMC_LPC_LA02_P (3B)
+set_location_assignment PIN_AT22 -to "rx_data_in[0](n)"    ; ## H8   FMC_LPC_LA02_N (3B)
+set_location_assignment PIN_AR20 -to rx_data_in[1]         ; ## G9   FMC_LPC_LA03_P (3B)
+set_location_assignment PIN_AR19 -to "rx_data_in[1](n)"    ; ## G10  FMC_LPC_LA03_N (3B)
+set_location_assignment PIN_AN20 -to rx_data_in[2]         ; ## H10  FMC_LPC_LA04_P (3B)
+set_location_assignment PIN_AP19 -to "rx_data_in[2](n)"    ; ## H11  FMC_LPC_LA04_N (3B)
+set_location_assignment PIN_AU21 -to rx_data_in[3]         ; ## C22  FMC_LPC_LA18_CC_P (3B) ## D11  FMC_LPC_LA05_P (3C) PIN_AV11 
+set_location_assignment PIN_AV21 -to "rx_data_in[3](n)"    ; ## C23  FMC_LPC_LA18_CC_N (3B) ## D12  FMC_LPC_LA05_N (3C) PIN_AW11 
+set_location_assignment PIN_AV14 -to rx_data_in[4]         ; ## C10  FMC_LPC_LA06_P (3B)
+set_location_assignment PIN_AW14 -to "rx_data_in[4](n)"    ; ## C11  FMC_LPC_LA06_N (3B)
+set_location_assignment PIN_AT17 -to rx_data_in[5]         ; ## H13  FMC_LPC_LA07_P (3B)
+set_location_assignment PIN_AU17 -to "rx_data_in[5](n)"    ; ## H14  FMC_LPC_LA07_N (3B)
+set_location_assignment PIN_AP18 -to tx_clk_out            ; ## G12  FMC_LPC_LA08_P (3B)
+set_location_assignment PIN_AN19 -to "tx_clk_out(n)"       ; ## G13  FMC_LPC_LA08_N (3B)
+set_location_assignment PIN_AV20 -to tx_frame_out          ; ## H37  FMC_LPC_LA32_P (3B) ## D14  FMC_LPC_LA09_P (3C) PIN_AW13 
+set_location_assignment PIN_AU20 -to "tx_frame_out(n)"     ; ## H38  FMC_LPC_LA32_N (3B) ## D15  FMC_LPC_LA09_N (3C) PIN_AV13 
+set_location_assignment PIN_AT14 -to tx_data_out[0]        ; ## H16  FMC_LPC_LA11_P (3B)
+set_location_assignment PIN_AR14 -to "tx_data_out[0](n)"   ; ## H17  FMC_LPC_LA11_N (3B)
+set_location_assignment PIN_AR16 -to tx_data_out[1]        ; ## G15  FMC_LPC_LA12_P (3B)
+set_location_assignment PIN_AP16 -to "tx_data_out[1](n)"   ; ## G16  FMC_LPC_LA12_N (3B)
+set_location_assignment PIN_AR17 -to tx_data_out[2]        ; ## D17  FMC_LPC_LA13_P (3B)
+set_location_assignment PIN_AP17 -to "tx_data_out[2](n)"   ; ## D18  FMC_LPC_LA13_N (3B)
+set_location_assignment PIN_AR15 -to tx_data_out[3]        ; ## C14  FMC_LPC_LA10_P (3B)
+set_location_assignment PIN_AT15 -to "tx_data_out[3](n)"   ; ## C15  FMC_LPC_LA10_N (3B)
+set_location_assignment PIN_AW18 -to tx_data_out[4]        ; ## C18  FMC_LPC_LA14_P (3B)
+set_location_assignment PIN_AV18 -to "tx_data_out[4](n)"   ; ## C19  FMC_LPC_LA14_N (3B)
+set_location_assignment PIN_AY17 -to tx_data_out[5]        ; ## G36  FMC_LPC_LA33_P (3B) ## H19  FMC_LPC_LA15_P (3C) PIN_AR9  
+set_location_assignment PIN_AW17 -to "tx_data_out[5](n)"   ; ## G37  FMC_LPC_LA33_N (3B) ## H20  FMC_LPC_LA15_N (3C) PIN_AT9  
 
 set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
 set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
@@ -65,8 +63,12 @@ set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2]
 set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3]
 set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4]
 set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5]
-set_instance_assignment -name IO_STANDARD LVDS -to enable
-set_instance_assignment -name IO_STANDARD LVDS -to txnrx
+
+set_location_assignment PIN_AT13 -to enable]               ; ## G18  FMC_LPC_LA16_P
+set_location_assignment PIN_AU13 -to txnrx]                ; ## G19  FMC_LPC_LA16_N
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to enable
+set_instance_assignment -name IO_STANDARD "1.8 V" -to txnrx
 
 # gpio
 

From 128ca7719aca01542c0b5bf4bd18d33001bd4322 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 2 Nov 2016 16:41:04 -0400
Subject: [PATCH 659/972] ccpci_lvds- rev.d. xcvr pin changes

---
 projects/pzsdr/ccpci_lvds/system_constr.xdc | 44 ++++++++++-----------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/projects/pzsdr/ccpci_lvds/system_constr.xdc b/projects/pzsdr/ccpci_lvds/system_constr.xdc
index 149a2c1de..bfc2f8efd 100644
--- a/projects/pzsdr/ccpci_lvds/system_constr.xdc
+++ b/projects/pzsdr/ccpci_lvds/system_constr.xdc
@@ -1,38 +1,36 @@
 
 # constraints
+# reference-only & not-effective
+# (axi_pcie_x0y0.xdc)
 
-set_property  -dict {PACKAGE_PIN  AA6}  [get_ports pcie_ref_clk_p]                                      ; ## MGTREFCLK1P_111
-set_property  -dict {PACKAGE_PIN  AA5}  [get_ports pcie_ref_clk_n]                                      ; ## MGTREFCLK1N_111
-set_property  -dict {PACKAGE_PIN  AD4}  [get_ports pcie_data_rx_p[0]]                                   ; ## MGTXRXP3_111
-set_property  -dict {PACKAGE_PIN  AD3}  [get_ports pcie_data_rx_n[0]]                                   ; ## MGTXRXN3_111
-set_property  -dict {PACKAGE_PIN  AC6}  [get_ports pcie_data_rx_p[1]]                                   ; ## MGTXRXP2_111
-set_property  -dict {PACKAGE_PIN  AC5}  [get_ports pcie_data_rx_n[1]]                                   ; ## MGTXRXN2_111
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports pcie_data_rx_p[2]]                                   ; ## MGTXRXP1_111
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports pcie_data_rx_n[2]]                                   ; ## MGTXRXN1_111
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports pcie_data_rx_p[3]]                                   ; ## MGTXRXP0_111
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports pcie_data_rx_n[3]]                                   ; ## MGTXRXN0_111
-set_property  -dict {PACKAGE_PIN  AC2}  [get_ports pcie_data_tx_p[0]]                                   ; ## MGTXTXP3_111
-set_property  -dict {PACKAGE_PIN  AC1}  [get_ports pcie_data_tx_n[0]]                                   ; ## MGTXTXN3_111
-set_property  -dict {PACKAGE_PIN  AE2}  [get_ports pcie_data_tx_p[1]]                                   ; ## MGTXTXP2_111
-set_property  -dict {PACKAGE_PIN  AE1}  [get_ports pcie_data_tx_n[1]]                                   ; ## MGTXTXN2_111
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports pcie_data_tx_p[2]]                                   ; ## MGTXTXP1_111
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports pcie_data_tx_n[2]]                                   ; ## MGTXTXN1_111
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports pcie_data_tx_p[3]]                                   ; ## MGTXTXP0_111
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports pcie_data_tx_n[3]]                                   ; ## MGTXTXN0_111
+set_property  -dict {PACKAGE_PIN  U6 }  [get_ports pcie_ref_clk_p]                                      ; ## MGTREFCLK1P_112 (JX3.2) (P2.A13)
+set_property  -dict {PACKAGE_PIN  U5 }  [get_ports pcie_ref_clk_n]                                      ; ## MGTREFCLK1N_112 (JX3.4) (P2.A14)
+set_property  -dict {PACKAGE_PIN  T4 }  [get_ports pcie_data_rx_p[0]]                                   ; ## MGTXRXP3_112 (JX1.97) (P2.B14)
+set_property  -dict {PACKAGE_PIN  T3 }  [get_ports pcie_data_rx_n[0]]                                   ; ## MGTXRXN3_112 (JX1.99) (P2.B15)
+set_property  -dict {PACKAGE_PIN  V4 }  [get_ports pcie_data_rx_p[1]]                                   ; ## MGTXRXP2_112 (JX1.92) (P2.B19)
+set_property  -dict {PACKAGE_PIN  V3 }  [get_ports pcie_data_rx_n[1]]                                   ; ## MGTXRXN2_112 (JX1.94) (P2.B20)
+set_property  -dict {PACKAGE_PIN  Y4 }  [get_ports pcie_data_rx_p[2]]                                   ; ## MGTXRXP1_112 (JX1.91) (P2.B23)
+set_property  -dict {PACKAGE_PIN  Y3 }  [get_ports pcie_data_rx_n[2]]                                   ; ## MGTXRXN1_112 (JX1.93) (P2.B24)
+set_property  -dict {PACKAGE_PIN  AB4}  [get_ports pcie_data_rx_p[3]]                                   ; ## MGTXRXP0_112 (JX1.88) (P2.B27)
+set_property  -dict {PACKAGE_PIN  AB3}  [get_ports pcie_data_rx_n[3]]                                   ; ## MGTXRXN0_112 (JX1.90) (P2.B28)
+set_property  -dict {PACKAGE_PIN  R2 }  [get_ports pcie_data_tx_p[0]]                                   ; ## MGTXTXP3_112 (JX3.19) (P2.A16)
+set_property  -dict {PACKAGE_PIN  R1 }  [get_ports pcie_data_tx_n[0]]                                   ; ## MGTXTXN3_112 (JX3.21) (P2.A17)
+set_property  -dict {PACKAGE_PIN  U2 }  [get_ports pcie_data_tx_p[1]]                                   ; ## MGTXTXP2_112 (JX3.14) (P2.A21)
+set_property  -dict {PACKAGE_PIN  U1 }  [get_ports pcie_data_tx_n[1]]                                   ; ## MGTXTXN2_112 (JX3.16) (P2.A22)
+set_property  -dict {PACKAGE_PIN  W2 }  [get_ports pcie_data_tx_p[2]]                                   ; ## MGTXTXP1_112 (JX3.13) (P2.A25)
+set_property  -dict {PACKAGE_PIN  W1 }  [get_ports pcie_data_tx_n[2]]                                   ; ## MGTXTXN1_112 (JX3.15) (P2.A26)
+set_property  -dict {PACKAGE_PIN  AA2}  [get_ports pcie_data_tx_p[3]]                                   ; ## MGTXTXP0_112 (JX3.8 ) (P2.A29)
+set_property  -dict {PACKAGE_PIN  AA1}  [get_ports pcie_data_tx_n[3]]                                   ; ## MGTXTXN0_112 (JX3.10) (P2.A30)
 set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS33} [get_ports pcie_rstn]                      ; ## IO_L19P_T3_13
 set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS33} [get_ports pcie_waken]                     ; ## IO_L20N_T3_13
 set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS33} [get_ports pcie_rstn_good]                 ; ## IO_L22N_T3_12
 
 # Default constraints have LVCMOS25, overwite it
+
 set_property  -dict {IOSTANDARD LVCMOS33} [get_ports iic_scl]                                           ; ## IO_L5P_T0_13
 set_property  -dict {IOSTANDARD LVCMOS33} [get_ports iic_sda]                                           ; ## IO_L5N_T0_13
 
 set_property PULLUP true [get_ports pcie_rstn]
-set_property LOC IBUFDS_GTE2_X0Y5 [get_cells i_ibufds_pcie_ref_clk]
 create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p]
 
-set_property LOC GTXE2_CHANNEL_X0Y8  [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
-set_property LOC GTXE2_CHANNEL_X0Y9  [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
-set_property LOC GTXE2_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
-set_property LOC GTXE2_CHANNEL_X0Y11 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
 

From 9dc7f16d80f4a84a3ae0e85aa1e5e6ea16ef4b6c Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 3 Nov 2016 15:29:56 +0200
Subject: [PATCH 660/972] axi_usb_fx3: Added zero length packet capability

---
 library/axi_usb_fx3/axi_usb_fx3.v      |  6 +++++
 library/axi_usb_fx3/axi_usb_fx3_core.v | 35 ++++++++++++++++++--------
 library/axi_usb_fx3/axi_usb_fx3_if.v   |  4 +--
 library/axi_usb_fx3/axi_usb_fx3_reg.v  |  4 +++
 4 files changed, 36 insertions(+), 13 deletions(-)

diff --git a/library/axi_usb_fx3/axi_usb_fx3.v b/library/axi_usb_fx3/axi_usb_fx3.v
index 97c3ab930..4478990d2 100644
--- a/library/axi_usb_fx3/axi_usb_fx3.v
+++ b/library/axi_usb_fx3/axi_usb_fx3.v
@@ -255,6 +255,9 @@ module axi_usb_fx3 (
   wire    [31:0]  length_fx32dma;
   wire    [31:0]  length_dma2fx3;
 
+  wire            trig;
+  wire            zlp;
+
   // signal name changes
 
   assign up_clk   = s_axi_aclk;
@@ -332,6 +335,8 @@ module axi_usb_fx3 (
     .test_mode_tpg(test_mode_tpg),
     .monitor_error(monitor_error),
 
+    .zlp(zlp),
+
     .fifo_num(fifo_num));
 
   // register map
@@ -343,6 +348,7 @@ module axi_usb_fx3 (
     .eot_fx32dma(eot_fx32dma),
     .eot_dma2fx3(eot_dma2fx3),
     .trig(trig),
+    .zlp(zlp),
     .fifo_num(fifo_num),
 
     .error(error),
diff --git a/library/axi_usb_fx3/axi_usb_fx3_core.v b/library/axi_usb_fx3/axi_usb_fx3_core.v
index 51877fe88..943354361 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_core.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_core.v
@@ -35,8 +35,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -137,6 +135,8 @@ module axi_usb_fx3_core (
   test_mode_tpg,
   monitor_error,
 
+  zlp,
+
   fifo_num);
 
   input           clk;
@@ -234,6 +234,8 @@ module axi_usb_fx3_core (
   input   [ 2:0]  test_mode_tpg;
   output          monitor_error;
 
+  input           zlp;
+
   input   [ 4:0]  fifo_num;
 
   // internal parameters
@@ -527,6 +529,9 @@ module axi_usb_fx3_core (
     end
     if (state_fx32dma == READ_HEADER) begin
       if (fx32dma_valid == 1'b1) begin
+        if (m_axis_tready == 1'b0) begin
+          error_fx32dma <= 1'b1;
+        end
         if(header_pointer < header_size_current - 4) begin
           header_pointer <= header_pointer + 8;
         end else begin
@@ -549,7 +554,9 @@ module axi_usb_fx3_core (
           data_size_transaction <= data_size_transaction - 4;
         end
       end
+
       // monitor
+
       if (test_mode_active_tpm == 1'b1) begin
         if (first_transfer == 1) begin
           expected_data <= fx32dma_data;
@@ -586,7 +593,11 @@ module axi_usb_fx3_core (
     case(state_dma2fx3)
       IDLE:
         if(dma2fx3_ready == 1'b1) begin
-          next_state_dma2fx3 = READ_DATA;
+          if  (zlp == 1'b1) begin
+            next_state_dma2fx3 = ADD_FOOTER;
+          end else begin
+            next_state_dma2fx3 = READ_DATA;
+          end
         end else begin
           next_state_dma2fx3 = IDLE;
         end
@@ -611,9 +622,9 @@ module axi_usb_fx3_core (
       IDLE: begin
         s_axis_tready = 1'b0;
         dma2fx3_valid = 1'b0;
-        eot_dma2fx3 = 1'b0;
-        dma2fx3_eop = 1'b0;
-        dma2fx3_data = dma2fx3_data_reg;
+        eot_dma2fx3   = 1'b0;
+        dma2fx3_eop   = 1'b0;
+        dma2fx3_data  = dma2fx3_data_reg;
       end
       READ_DATA: begin
         eot_dma2fx3 = 1'b0;
@@ -646,25 +657,27 @@ module axi_usb_fx3_core (
       default: begin
         s_axis_tready = 1'b0;
         dma2fx3_valid = 1'b0;
-        eot_dma2fx3 = 1'b0;
-        dma2fx3_eop = 1'b0;
-        dma2fx3_data = dma2fx3_data_reg;
+        eot_dma2fx3   = 1'b0;
+        dma2fx3_eop   = 1'b0;
+        dma2fx3_data  = dma2fx3_data_reg;
       end
     endcase
   end
 
   always @(posedge clk) begin
     if(state_dma2fx3 == IDLE) begin
-      footer_pointer <= 0;
+      footer_pointer <= 4;
       dma2fx3_counter <= 0;
       case (test_mode_tpg)
         4'h1: dma2fx3_data_reg <= 32'haaaaaaaa;
         default:  dma2fx3_data_reg <= 32'hffffffff;
       endcase
+      if (zlp == 1'b1) begin
+        dma2fx3_data_reg <= 32'h0ff00ff0;
+      end
     end
 
     if(state_dma2fx3 == READ_DATA) begin
-      footer_pointer <= 4;
       if (test_mode_active_tpg == 1'b1) begin
         if (dma2fx3_ready == 1'b1) begin
           dma2fx3_counter <= dma2fx3_counter + 4;
diff --git a/library/axi_usb_fx3/axi_usb_fx3_if.v b/library/axi_usb_fx3/axi_usb_fx3_if.v
index 45b6c05e5..2a0a387ba 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_if.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_if.v
@@ -278,9 +278,9 @@ module axi_usb_fx3_if (
         fx32dma_valid = 1'b0;
         fx32dma_sop   = 1'b0;
         fx32dma_data  = 32'h0;
-        slwr_n =  !dma2fx3_valid | !current_fifo;
+        slwr_n        = !dma2fx3_valid | !current_fifo;
         dma2fx3_ready = current_fifo;
-        pktend_n = !dma2fx3_eop;
+        pktend_n      = !dma2fx3_eop;
       end
       default: begin
         slcs_n        = 1'b1;
diff --git a/library/axi_usb_fx3/axi_usb_fx3_reg.v b/library/axi_usb_fx3/axi_usb_fx3_reg.v
index f4df03f94..2bf33d20a 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_reg.v
+++ b/library/axi_usb_fx3/axi_usb_fx3_reg.v
@@ -48,6 +48,7 @@ module axi_usb_fx3_reg (
   eot_fx32dma,
   eot_dma2fx3,
   trig,
+  zlp,
   fifo_num,
 
   error,
@@ -125,6 +126,7 @@ module axi_usb_fx3_reg (
   input           eot_fx32dma;
   input           eot_dma2fx3;
   output          trig;
+  output          zlp;
   output  [ 4:0]  fifo_num;
 
   input           error;
@@ -241,6 +243,7 @@ module axi_usb_fx3_reg (
   assign up_rreq_s = ((up_raddr[13:8] == 6'h00)) ? up_rreq : 1'b0;
 
   assign trig       = transfer_config[31];
+  assign zlp        = transfer_config[30];
   assign fifo_num   = transfer_config[4:0];
 
   assign test_mode_tpm = tpm_config[2:0];
@@ -373,6 +376,7 @@ module axi_usb_fx3_reg (
       end
       if (eot_fx32dma == 1'b1 || eot_dma2fx3 == 1'b1 || error == 1'b1) begin
         transfer_config[31] <= 1'b0;
+        transfer_config[30] <= 1'b0;
       end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
         transfer_config <= up_wdata;
       end

From 0dfbb0af116310138413c6b6ae36ce84eb0ddea4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 3 Nov 2016 11:25:41 -0400
Subject: [PATCH 661/972] arradio/c5soc- constraints changes- interface 1r1t

---
 projects/arradio/c5soc/system_constr.sdc | 98 ++++++++++++++++--------
 1 file changed, 66 insertions(+), 32 deletions(-)

diff --git a/projects/arradio/c5soc/system_constr.sdc b/projects/arradio/c5soc/system_constr.sdc
index 2848a0de7..a641e75ca 100644
--- a/projects/arradio/c5soc/system_constr.sdc
+++ b/projects/arradio/c5soc/system_constr.sdc
@@ -1,43 +1,77 @@
 
 create_clock -period "20.000 ns" -name sys_clk  [get_ports {sys_clk}]
-create_clock -period "12.500 ns" -name dma_clk  [get_pins {*sys_hps*h2f_user0_clk}]
-
 create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}]
 
 derive_pll_clocks
 derive_clock_uncertainty
 
-#create_clock -period 4.0 -name v_rx_clk
-#create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}]
+create_clock -period 4.0 -name v_rx_clk
 
-#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_frame_in}]
-#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[0]}]
-#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[1]}]
-#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[2]}]
-#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[3]}]
-#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[4]}]
-#set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[5]}]
-#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_frame_in}]     -clock_fall -add_delay
-#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[0]}]   -clock_fall -add_delay
-#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[1]}]   -clock_fall -add_delay
-#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[2]}]   -clock_fall -add_delay
-#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[3]}]   -clock_fall -add_delay
-#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[4]}]   -clock_fall -add_delay
-#set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[5]}]   -clock_fall -add_delay
+set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_frame_in}]
+set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
+set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
+set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
+set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
+set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
+set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
+set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_frame_in}]
+set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
+set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
+set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
+set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
+set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
+set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
+set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_frame_in}]  
+set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
+set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
+set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
+set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
+set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
+set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
+set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_frame_in}]  
+set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
+set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
+set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
+set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
+set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
+set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
+
+create_generated_clock -name v_tx_clk_reg \
+  -source [get_pins -hierarchical *counter\[0\]*divclk*] \
+  [get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*]
+
+create_generated_clock -name v_tx_clk \
+  -source [get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*] \
+  [get_ports {tx_clk_out}]
+
+set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
+set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
+set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
+set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
+set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
+set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
+set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
+set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
+set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
+set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
+set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
+set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
+set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
+set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
+set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
+set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
+set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
+set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
+set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
+set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
+set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
+set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
+set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
+set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
+set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
+set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
+set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
+set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
 
 
-#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_frame_out}]
-#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[0]}]
-#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[1]}]
-#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[2]}]
-#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[3]}]
-#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[4]}]
-#set_output_delay  -clock {v_fb_clk} -max  1.2 [get_ports {tx_data_out[5]}]
-#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_frame_out}]    -clock_fall -add_delay
-#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[0]}]  -clock_fall -add_delay
-#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[1]}]  -clock_fall -add_delay
-#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[2]}]  -clock_fall -add_delay
-#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[3]}]  -clock_fall -add_delay
-#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[4]}]  -clock_fall -add_delay
-#set_output_delay  -clock {v_fb_clk} -min  0.2 [get_ports {tx_data_out[5]}]  -clock_fall -add_delay
 

From ce3b6a2d3f1cfeeb9e355f4028a7792a17454223 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 4 Nov 2016 18:20:46 +0200
Subject: [PATCH 662/972] adrv9371x: Updated constraints for altera projects

---
 projects/adrv9371x/a10gx/system_constr.sdc  | 16 ++++++++--------
 projects/adrv9371x/a10soc/system_constr.sdc | 16 ++++++++--------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/projects/adrv9371x/a10gx/system_constr.sdc b/projects/adrv9371x/a10gx/system_constr.sdc
index 1241a1b8f..e4b436327 100644
--- a/projects/adrv9371x/a10gx/system_constr.sdc
+++ b/projects/adrv9371x/a10gx/system_constr.sdc
@@ -8,33 +8,33 @@ derive_clock_uncertainty
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
+  -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
+  -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0k}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
+  -to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
+  -to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc
index adfd88a83..029e779b7 100644
--- a/projects/adrv9371x/a10soc/system_constr.sdc
+++ b/projects/adrv9371x/a10soc/system_constr.sdc
@@ -8,33 +8,33 @@ derive_clock_uncertainty
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
+  -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
+  -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
+  -to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
-  -to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
+  -to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
+set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 

From 4e99c3be9a5d51f3adb31ebac4e07026ab853ccf Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Nov 2016 13:20:44 -0400
Subject: [PATCH 663/972] a5soc- tcl flow updates

---
 projects/common/a5soc/a5soc_system_assign.tcl |   22 +-
 projects/common/a5soc/a5soc_system_bd.qsys    | 1113 -----------------
 projects/common/a5soc/a5soc_system_qsys.tcl   |  197 +++
 3 files changed, 200 insertions(+), 1132 deletions(-)
 delete mode 100644 projects/common/a5soc/a5soc_system_bd.qsys
 create mode 100644 projects/common/a5soc/a5soc_system_qsys.tcl

diff --git a/projects/common/a5soc/a5soc_system_assign.tcl b/projects/common/a5soc/a5soc_system_assign.tcl
index 4f5d287e8..f7d916fe3 100755
--- a/projects/common/a5soc/a5soc_system_assign.tcl
+++ b/projects/common/a5soc/a5soc_system_assign.tcl
@@ -4,17 +4,6 @@
 set_global_assignment -name FAMILY "Arria V"
 set_global_assignment -name DEVICE 5ASTFD5K3F40I3ES
 
-# i2c (fmc)
-
-set_location_assignment PIN_F26 -to hdmi_scl
-set_location_assignment PIN_G26 -to hdmi_sda
-set_location_assignment PIN_N23 -to hdmi_rstn
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_scl
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_sda
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_rstn
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdmi_scl
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdmi_sda
-
 # led & switches
 
 set_location_assignment PIN_AH24  -to gpio_bd[0]    ; ## led[0]
@@ -434,14 +423,9 @@ set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
 set_global_assignment -name ECO_REGENERATE_REPORT ON
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
-set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
+# source defaults
+
+source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
 
diff --git a/projects/common/a5soc/a5soc_system_bd.qsys b/projects/common/a5soc/a5soc_system_bd.qsys
deleted file mode 100644
index 3013f7056..000000000
--- a/projects/common/a5soc/a5soc_system_bd.qsys
+++ /dev/null
@@ -1,1113 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_cpu_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element sys_cpu_interconnect.s0
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_gpio
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element sys_gpio.s1
-   {
-      datum baseAddress
-      {
-         value = "1048592";
-         type = "String";
-      }
-   }
-   element sys_gpio_bd
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element sys_gpio_bd.s1
-   {
-      datum baseAddress
-      {
-         value = "1048576";
-         type = "String";
-      }
-   }
-   element sys_hps
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_hps.f2h_axi_slave
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element sys_id.control_slave
-   {
-      datum baseAddress
-      {
-         value = "1048608";
-         type = "String";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-   element sys_int_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_intr
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element sys_rst_out
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5ASTFD5K3F40I3ES" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName">fmcjesdadc1_a5soc.qpf</parameter>
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="hps_0_emac0" internal="sys_hps.emac0" />
- <interface name="hps_0_emac0_gtx_clk" internal="sys_hps.emac0_gtx_clk" />
- <interface name="hps_0_emac0_md_clk" internal="sys_hps.emac0_md_clk" />
- <interface name="hps_0_emac0_rx_clk_in" internal="sys_hps.emac0_rx_clk_in" />
- <interface name="hps_0_emac0_rx_reset" internal="sys_hps.emac0_rx_reset" />
- <interface name="hps_0_emac0_tx_clk_in" internal="sys_hps.emac0_tx_clk_in" />
- <interface name="hps_0_emac0_tx_reset" internal="sys_hps.emac0_tx_reset" />
- <interface name="hps_0_emac_ptp_ref_clock" internal="sys_hps.emac_ptp_ref_clock" />
- <interface name="sys_clk" internal="sys_clk.out_clk" type="clock" dir="start" />
- <interface
-   name="sys_cpu_interconnect_m0"
-   internal="sys_cpu_interconnect.m0"
-   type="avalon"
-   dir="start" />
- <interface
-   name="sys_gpio_bd_external_connection"
-   internal="sys_gpio_bd.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_external_connection"
-   internal="sys_gpio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_f2h_cold_reset_req"
-   internal="sys_hps.f2h_cold_reset_req" />
- <interface
-   name="sys_hps_f2h_debug_reset_req"
-   internal="sys_hps.f2h_debug_reset_req" />
- <interface name="sys_hps_f2h_stm_hw_events" internal="sys_hps.f2h_stm_hw_events" />
- <interface
-   name="sys_hps_f2h_warm_reset_req"
-   internal="sys_hps.f2h_warm_reset_req" />
- <interface name="sys_hps_i2c0" internal="sys_hps.i2c0" type="conduit" dir="end" />
- <interface
-   name="sys_hps_i2c0_clk"
-   internal="sys_hps.i2c0_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_hps_i2c0_scl_in"
-   internal="sys_hps.i2c0_scl_in"
-   type="clock"
-   dir="end" />
- <interface name="sys_hps_io" internal="sys_hps.hps_io" type="conduit" dir="end" />
- <interface
-   name="sys_hps_memory"
-   internal="sys_hps.memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_s_axi"
-   internal="sys_hps.f2h_axi_slave"
-   type="axi"
-   dir="end" />
- <interface
-   name="sys_hps_spim0"
-   internal="sys_hps.spim0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_spim0_sclk_out"
-   internal="sys_hps.spim0_sclk_out"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_intr"
-   internal="sys_intr.receiver_irq"
-   type="interrupt"
-   dir="start" />
- <interface
-   name="sys_rst"
-   internal="sys_rst_out.out_reset"
-   type="reset"
-   dir="start" />
- <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="100000000" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module
-   name="sys_cpu_interconnect"
-   kind="altera_avalon_mm_bridge"
-   version="15.0"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="20" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="DATA_WIDTH" value="32" />
-  <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="MAX_PENDING_RESPONSES" value="4" />
-  <parameter name="PIPELINE_COMMAND" value="1" />
-  <parameter name="PIPELINE_RESPONSE" value="1" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
-  <parameter name="USE_RESPONSE" value="0" />
- </module>
- <module name="sys_gpio" kind="altera_avalon_pio" version="15.0" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="true" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="true" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="FALLING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="EDGE" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_bd"
-   kind="altera_avalon_pio"
-   version="15.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="true" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="FALLING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module name="sys_hps" kind="altera_hps" version="15.0" enabled="1">
-  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-  <parameter name="AC_PACKAGE_DESKEW" value="false" />
-  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-  <parameter name="ADDR_ORDER" value="0" />
-  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
-  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-  <parameter name="ADVANCED_CK_PHASES" value="false" />
-  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
-  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-  <parameter name="AP_MODE" value="false" />
-  <parameter name="AP_MODE_EN" value="0" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_PD_CYCLES" value="0" />
-  <parameter name="AUTO_POWERDN_EN" value="false" />
-  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-  <parameter name="AVL_MAX_SIZE" value="4" />
-  <parameter name="BONDING_OUT_ENABLED" value="false" />
-  <parameter name="BOOTFROMFPGA_Enable" value="false" />
-  <parameter name="BSEL" value="1" />
-  <parameter name="BSEL_EN" value="false" />
-  <parameter name="BYTE_ENABLE" value="true" />
-  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="CALIBRATION_MODE" value="Skip" />
-  <parameter name="CALIB_REG_WIDTH" value="8" />
-  <parameter name="CAN0_Mode" value="N/A" />
-  <parameter name="CAN0_PinMuxing" value="Unused" />
-  <parameter name="CAN1_Mode" value="N/A" />
-  <parameter name="CAN1_PinMuxing" value="Unused" />
-  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-  <parameter name="CFG_REORDER_DATA" value="true" />
-  <parameter name="CFG_TCCD_NS" value="2.5" />
-  <parameter name="COMMAND_PHASE" value="0.0" />
-  <parameter name="CONTROLLER_LATENCY" value="5" />
-  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
-  <parameter name="CSEL" value="0" />
-  <parameter name="CSEL_EN" value="false" />
-  <parameter name="CTI_Enable" value="false" />
-  <parameter name="CTL_AUTOPCH_EN" value="false" />
-  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
-  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="CTL_CSR_ENABLED" value="false" />
-  <parameter name="CTL_CSR_READ_ONLY" value="1" />
-  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
-  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-  <parameter name="CTL_ECC_ENABLED" value="false" />
-  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
-  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="true" />
-  <parameter name="CTL_HRB_ENABLED" value="false" />
-  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTL_USR_REFRESH_EN" value="false" />
-  <parameter name="CTL_ZQCAL_EN" value="false" />
-  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
-  <parameter name="DAT_DATA_WIDTH" value="32" />
-  <parameter name="DEBUGAPB_Enable" value="false" />
-  <parameter name="DEBUG_MODE" value="false" />
-  <parameter name="DEVICE_DEPTH" value="1" />
-  <parameter name="DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
-  <parameter name="DISCRETE_FLY_BY" value="true" />
-  <parameter name="DLL_SHARING_MODE" value="None" />
-  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
-  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
-  <parameter name="DUPLICATE_AC" value="false" />
-  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
-  <parameter name="EMAC0_Mode" value="N/A" />
-  <parameter name="EMAC0_PinMuxing" value="Unused" />
-  <parameter name="EMAC1_Mode" value="RGMII" />
-  <parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-  <parameter name="ENABLE_BONDING" value="false" />
-  <parameter name="ENABLE_BURST_MERGE" value="false" />
-  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
-  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
-  <parameter name="ENABLE_ISS_PROBES" value="false" />
-  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
-  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-  <parameter name="ENABLE_USER_ECC" value="false" />
-  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
-  <parameter name="EXTRA_SETTINGS" value="" />
-  <parameter name="F2H_AXI_CLOCK_FREQ" value="100000000" />
-  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
-  <parameter name="F2SCLK_COLDRST_Enable" value="false" />
-  <parameter name="F2SCLK_DBGRST_Enable" value="false" />
-  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
-  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
-  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
-  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
-  <parameter name="F2SCLK_WARMRST_Enable" value="false" />
-  <parameter name="F2SDRAM_Type" value="" />
-  <parameter name="F2SDRAM_Width" value="" />
-  <parameter name="F2SINTERRUPT_Enable" value="true" />
-  <parameter name="F2S_Width" value="2" />
-  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
-  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
-  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
-  <parameter
-     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
-     value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="0" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="100.0" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="100.0" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
-  <parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
-  <parameter name="GP_Enable" value="false" />
-  <parameter name="H2F_AXI_CLOCK_FREQ" value="100000000" />
-  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="100000000" />
-  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
-  <parameter name="HARD_EMIF" value="true" />
-  <parameter name="HCX_COMPAT_MODE" value="false" />
-  <parameter name="HHP_HPS" value="true" />
-  <parameter name="HHP_HPS_SIMULATION" value="false" />
-  <parameter name="HHP_HPS_VERIFICATION" value="false" />
-  <parameter name="HLGPI_Enable" value="false" />
-  <parameter name="HPS_PROTOCOL" value="DDR3" />
-  <parameter name="I2C0_Mode" value="Full" />
-  <parameter name="I2C0_PinMuxing" value="FPGA" />
-  <parameter name="I2C1_Mode" value="N/A" />
-  <parameter name="I2C1_PinMuxing" value="Unused" />
-  <parameter name="I2C2_Mode" value="N/A" />
-  <parameter name="I2C2_PinMuxing" value="Unused" />
-  <parameter name="I2C3_Mode" value="N/A" />
-  <parameter name="I2C3_PinMuxing" value="Unused" />
-  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="IS_ES_DEVICE" value="false" />
-  <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
-  <parameter name="LOCAL_ID_WIDTH" value="8" />
-  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
-  <parameter name="LWH2F_Enable" value="true" />
-  <parameter name="MARGIN_VARIATION_TEST" value="false" />
-  <parameter name="MAX_PENDING_RD_CMD" value="16" />
-  <parameter name="MAX_PENDING_WR_CMD" value="8" />
-  <parameter name="MEM_ASR" value="Manual" />
-  <parameter name="MEM_ATCL" value="Disabled" />
-  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
-  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
-  <parameter name="MEM_BL" value="OTF" />
-  <parameter name="MEM_BT" value="Sequential" />
-  <parameter name="MEM_CK_PHASE" value="0.0" />
-  <parameter name="MEM_CK_WIDTH" value="1" />
-  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
-  <parameter name="MEM_CLK_FREQ" value="400.0" />
-  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
-  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_CS_WIDTH" value="1" />
-  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
-  <parameter name="MEM_DLL_EN" value="true" />
-  <parameter name="MEM_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DQ_WIDTH" value="40" />
-  <parameter name="MEM_DRV_STR" value="RZQ/6" />
-  <parameter name="MEM_FORMAT" value="DISCRETE" />
-  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
-  <parameter name="MEM_IF_DQSN_EN" value="true" />
-  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-  <parameter name="MEM_INIT_EN" value="false" />
-  <parameter name="MEM_INIT_FILE" value="" />
-  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
-  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_PD" value="DLL off" />
-  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
-  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
-  <parameter name="MEM_SRT" value="Normal" />
-  <parameter name="MEM_TCL" value="7" />
-  <parameter name="MEM_TFAW_NS" value="35.0" />
-  <parameter name="MEM_TINIT_US" value="500" />
-  <parameter name="MEM_TMRD_CK" value="4" />
-  <parameter name="MEM_TRAS_NS" value="35.0" />
-  <parameter name="MEM_TRCD_NS" value="13.75" />
-  <parameter name="MEM_TREFI_US" value="7.8" />
-  <parameter name="MEM_TRFC_NS" value="260.0" />
-  <parameter name="MEM_TRP_NS" value="13.75" />
-  <parameter name="MEM_TRRD_NS" value="6.0" />
-  <parameter name="MEM_TRTP_NS" value="7.5" />
-  <parameter name="MEM_TWR_NS" value="15.0" />
-  <parameter name="MEM_TWTR" value="4" />
-  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
-  <parameter name="MEM_VENDOR" value="JEDEC" />
-  <parameter name="MEM_VERBOSE" value="true" />
-  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
-  <parameter name="MEM_WTCL" value="6" />
-  <parameter name="MPU_EVENTS_Enable" value="false" />
-  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-  <parameter name="MULTICAST_EN" value="false" />
-  <parameter name="NAND_Mode" value="N/A" />
-  <parameter name="NAND_PinMuxing" value="Unused" />
-  <parameter name="NEXTGEN" value="true" />
-  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
-  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
-  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_OF_PORTS" value="1" />
-  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
-  <parameter name="OCT_SHARING_MODE" value="None" />
-  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="PACKAGE_DESKEW" value="false" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="PHY_CSR_ENABLED" value="false" />
-  <parameter name="PHY_ONLY" value="false" />
-  <parameter name="PINGPONGPHY_EN" value="false" />
-  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
-  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_LOCATION" value="Top_Bottom" />
-  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_SHARING_MODE" value="None" />
-  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="POWER_OF_TWO_BUS" value="false" />
-  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-  <parameter name="QSPI_Mode" value="1 SS" />
-  <parameter name="QSPI_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="RATE" value="Full" />
-  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-  <parameter name="READ_FIFO_SIZE" value="8" />
-  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
-  <parameter name="REFRESH_INTERVAL" value="15000" />
-  <parameter name="REF_CLK_FREQ" value="25.0" />
-  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
-  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
-  <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
-  <parameter name="S2FCLK_USER1CLK_Enable" value="false" />
-  <parameter name="S2FCLK_USER1CLK_FREQ" value="150.0" />
-  <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
-  <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
-  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
-  <parameter name="S2F_Width" value="2" />
-  <parameter name="SDIO_Mode" value="4-bit Data" />
-  <parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="SEQUENCER_TYPE" value="NIOS" />
-  <parameter name="SEQ_MODE" value="0" />
-  <parameter name="SKIP_MEM_INIT" value="true" />
-  <parameter name="SOPC_COMPAT_RESET" value="false" />
-  <parameter name="SPEED_GRADE" value="7" />
-  <parameter name="SPIM0_Mode" value="Full" />
-  <parameter name="SPIM0_PinMuxing" value="FPGA" />
-  <parameter name="SPIM1_Mode" value="N/A" />
-  <parameter name="SPIM1_PinMuxing" value="Unused" />
-  <parameter name="SPIS0_Mode" value="N/A" />
-  <parameter name="SPIS0_PinMuxing" value="Unused" />
-  <parameter name="SPIS1_Mode" value="N/A" />
-  <parameter name="SPIS1_PinMuxing" value="Unused" />
-  <parameter name="STARVE_LIMIT" value="10" />
-  <parameter name="STM_Enable" value="false" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="TEST_Enable" value="false" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
-  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_TDH" value="0.0" />
-  <parameter name="TIMING_BOARD_TDS" value="0.0" />
-  <parameter name="TIMING_BOARD_TIH" value="0.0" />
-  <parameter name="TIMING_BOARD_TIS" value="0.0" />
-  <parameter name="TIMING_TDH" value="45" />
-  <parameter name="TIMING_TDQSCK" value="225" />
-  <parameter name="TIMING_TDQSCKDL" value="1200" />
-  <parameter name="TIMING_TDQSCKDM" value="900" />
-  <parameter name="TIMING_TDQSCKDS" value="450" />
-  <parameter name="TIMING_TDQSH" value="0.35" />
-  <parameter name="TIMING_TDQSQ" value="100" />
-  <parameter name="TIMING_TDQSS" value="0.27" />
-  <parameter name="TIMING_TDS" value="10" />
-  <parameter name="TIMING_TDSH" value="0.18" />
-  <parameter name="TIMING_TDSS" value="0.18" />
-  <parameter name="TIMING_TIH" value="120" />
-  <parameter name="TIMING_TIS" value="170" />
-  <parameter name="TIMING_TQH" value="0.38" />
-  <parameter name="TIMING_TQHS" value="300" />
-  <parameter name="TIMING_TQSH" value="0.4" />
-  <parameter name="TPIUFPGA_Enable" value="false" />
-  <parameter name="TPIUFPGA_alt" value="false" />
-  <parameter name="TRACE_Mode" value="N/A" />
-  <parameter name="TRACE_PinMuxing" value="Unused" />
-  <parameter name="TRACKING_ERROR_TEST" value="false" />
-  <parameter name="TRACKING_WATCH_TEST" value="false" />
-  <parameter name="TREFI" value="35100" />
-  <parameter name="TRFC" value="350" />
-  <parameter name="UART0_Mode" value="No Flow Control" />
-  <parameter name="UART0_PinMuxing" value="HPS I/O Set 1" />
-  <parameter name="UART1_Mode" value="N/A" />
-  <parameter name="UART1_PinMuxing" value="Unused" />
-  <parameter name="USB0_Mode" value="N/A" />
-  <parameter name="USB0_PinMuxing" value="Unused" />
-  <parameter name="USB1_Mode" value="SDR" />
-  <parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="USER_DEBUG_LEVEL" value="1" />
-  <parameter name="USE_AXI_ADAPTOR" value="false" />
-  <parameter name="USE_FAKE_PHY" value="false" />
-  <parameter name="USE_MEM_CLK_FREQ" value="false" />
-  <parameter name="USE_MM_ADAPTOR" value="true" />
-  <parameter name="USE_SEQUENCER_BFM" value="false" />
-  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
-  <parameter name="can0_clk_div" value="1" />
-  <parameter name="can1_clk_div" value="1" />
-  <parameter name="configure_advanced_parameters" value="false" />
-  <parameter name="customize_device_pll_info" value="false" />
-  <parameter name="dbctrl_stayosc1" value="true" />
-  <parameter name="dbg_at_clk_div" value="0" />
-  <parameter name="dbg_clk_div" value="1" />
-  <parameter name="dbg_trace_clk_div" value="0" />
-  <parameter name="desired_can0_clk_mhz" value="100.0" />
-  <parameter name="desired_can1_clk_mhz" value="100.0" />
-  <parameter name="desired_cfg_clk_mhz" value="100.0" />
-  <parameter name="desired_emac0_clk_mhz" value="250.0" />
-  <parameter name="desired_emac1_clk_mhz" value="250.0" />
-  <parameter name="desired_gpio_db_clk_hz" value="32000" />
-  <parameter name="desired_l4_mp_clk_mhz" value="100.0" />
-  <parameter name="desired_l4_sp_clk_mhz" value="100.0" />
-  <parameter name="desired_mpu_clk_mhz" value="800.0" />
-  <parameter name="desired_nand_clk_mhz" value="12.5" />
-  <parameter name="desired_qspi_clk_mhz" value="400.0" />
-  <parameter name="desired_sdmmc_clk_mhz" value="200.0" />
-  <parameter name="desired_spi_m_clk_mhz" value="200.0" />
-  <parameter name="desired_usb_mp_clk_mhz" value="200.0" />
-  <parameter name="device_name" value="5ASTFD5K3F40I3ES" />
-  <parameter name="device_pll_info_manual">{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}</parameter>
-  <parameter name="eosc1_clk_mhz" value="25.0" />
-  <parameter name="eosc2_clk_mhz" value="25.0" />
-  <parameter name="gpio_db_clk_div" value="6249" />
-  <parameter name="l3_mp_clk_div" value="1" />
-  <parameter name="l3_sp_clk_div" value="1" />
-  <parameter name="l4_mp_clk_div" value="1" />
-  <parameter name="l4_mp_clk_source" value="1" />
-  <parameter name="l4_sp_clk_div" value="1" />
-  <parameter name="l4_sp_clk_source" value="1" />
-  <parameter name="main_pll_c3" value="3" />
-  <parameter name="main_pll_c4" value="3" />
-  <parameter name="main_pll_c5" value="15" />
-  <parameter name="main_pll_m" value="63" />
-  <parameter name="main_pll_n" value="0" />
-  <parameter name="nand_clk_source" value="2" />
-  <parameter name="periph_pll_c0" value="3" />
-  <parameter name="periph_pll_c1" value="3" />
-  <parameter name="periph_pll_c2" value="1" />
-  <parameter name="periph_pll_c3" value="19" />
-  <parameter name="periph_pll_c4" value="4" />
-  <parameter name="periph_pll_c5" value="9" />
-  <parameter name="periph_pll_m" value="79" />
-  <parameter name="periph_pll_n" value="1" />
-  <parameter name="periph_pll_source" value="0" />
-  <parameter name="qspi_clk_source" value="1" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
-     value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
-     value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
-     value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
-  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
-  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
-  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
-  <parameter name="sdmmc_clk_source" value="2" />
-  <parameter name="show_advanced_parameters" value="false" />
-  <parameter name="show_debug_info_as_warning_msg" value="false" />
-  <parameter name="show_warning_as_error_msg" value="false" />
-  <parameter name="spi_m_clk_div" value="0" />
-  <parameter name="usb_mp_clk_div" value="0" />
-  <parameter name="use_default_mpu_clk" value="false" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="15.0"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="id" value="-1395322095" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="15.0"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="64" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_memory2_0" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="65536" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module name="sys_intr" kind="altera_irq_bridge" version="15.0" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
-  <parameter name="IRQ_N" value="0" />
-  <parameter name="IRQ_WIDTH" value="8" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module
-   name="sys_rst_out"
-   kind="altera_reset_bridge"
-   version="15.0"
-   enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="sys_hps.h2f_axi_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00100020" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_cpu_interconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_gpio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00100010" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_gpio_bd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00100000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_rst.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_id.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_gpio.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_gpio_bd.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_rst_out.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_cpu_interconnect.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_intr.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_hps.f2h_axi_clock" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_hps.h2f_axi_clock" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_hps.h2f_lw_axi_clock" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_clk.in_clk" />
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_gpio.irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_gpio_bd.irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender0_irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender1_irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender2_irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender3_irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender4_irq">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender5_irq">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender6_irq">
-  <parameter name="irqNumber" value="8" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender7_irq">
-  <parameter name="irqNumber" value="9" />
- </connection>
- <connection
-   kind="reset"
-   version="15.0"
-   start="sys_hps.h2f_reset"
-   end="sys_rst.in_reset" />
- <connection
-   kind="reset"
-   version="15.0"
-   start="sys_hps.h2f_reset"
-   end="sys_rst_out.in_reset" />
- <connection
-   kind="reset"
-   version="15.0"
-   start="sys_rst.out_reset"
-   end="sys_intr.clk_reset" />
- <connection
-   kind="reset"
-   version="15.0"
-   start="sys_rst.out_reset"
-   end="sys_gpio_bd.reset" />
- <connection
-   kind="reset"
-   version="15.0"
-   start="sys_rst.out_reset"
-   end="sys_gpio.reset" />
- <connection
-   kind="reset"
-   version="15.0"
-   start="sys_rst.out_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="15.0"
-   start="sys_rst.out_reset"
-   end="sys_cpu_interconnect.reset" />
- <connection
-   kind="reset"
-   version="15.0"
-   start="sys_rst.out_reset"
-   end="sys_int_mem.reset1" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/common/a5soc/a5soc_system_qsys.tcl b/projects/common/a5soc/a5soc_system_qsys.tcl
new file mode 100644
index 000000000..7cd68f8fe
--- /dev/null
+++ b/projects/common/a5soc/a5soc_system_qsys.tcl
@@ -0,0 +1,197 @@
+
+package require qsys
+
+set_module_property NAME {system_bd}
+set_project_property DEVICE_FAMILY {Arria 10}
+set_project_property DEVICE {10AX115S3F45E2SGE3}
+
+set system_type nios
+
+# clock-&-reset
+
+add_instance sys_clk clock_source 16.0
+add_interface sys_clk clock sink
+add_interface sys_rst reset sink
+set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
+set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
+set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
+set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
+
+# memory (int)
+
+add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
+set_instance_parameter_value sys_int_mem {dataWidth} {64}
+set_instance_parameter_value sys_int_mem {dualPort} {0}
+set_instance_parameter_value sys_int_mem {initMemContent} {0}
+set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
+add_connection sys_clk.clk sys_int_mem.clk1
+add_connection sys_clk.clk_reset sys_int_mem.reset1
+
+# hps
+
+add_instance sys_hps altera_hps 16.0
+set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value sys_hps {F2SDRAM_Type} {}
+set_instance_parameter_value sys_hps {F2SDRAM_Width} {}
+set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
+set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
+set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
+set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
+set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
+set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {FPGA}
+set_instance_parameter_value sys_hps {SPIM0_Mode} {Full}
+set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 1}
+set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
+set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
+set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
+set_instance_parameter_value sys_hps {use_default_mpu_clk} {0}
+set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
+set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_Enable} {0}
+set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {150.0}
+set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
+set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
+set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
+set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
+set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
+set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {40}
+set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
+set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
+set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
+set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
+set_instance_parameter_value sys_hps {TIMING_TIS} {170}
+set_instance_parameter_value sys_hps {TIMING_TIH} {120}
+set_instance_parameter_value sys_hps {TIMING_TDS} {10}
+set_instance_parameter_value sys_hps {TIMING_TDH} {45}
+set_instance_parameter_value sys_hps {TIMING_TDQSQ} {100}
+set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
+set_instance_parameter_value sys_hps {TIMING_TDQSCK} {225}
+set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.27}
+set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
+set_instance_parameter_value sys_hps {TIMING_TDSH} {0.18}
+set_instance_parameter_value sys_hps {TIMING_TDSS} {0.18}
+set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
+set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
+set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
+set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
+set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
+set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
+set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
+set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
+set_instance_parameter_value sys_hps {MEM_TWTR} {4}
+set_instance_parameter_value sys_hps {MEM_TFAW_NS} {35.0}
+set_instance_parameter_value sys_hps {MEM_TRRD_NS} {6.0}
+set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
+
+add_interface sys_hps_clk clock source
+set_interface_property sys_hps_clk EXPORT_OF sys_hps.h2f_user0_clock
+add_interface sys_hps_spim0 conduit end
+set_interface_property sys_hps_spim0 EXPORT_OF sys_hps.spim0
+add_interface sys_hps_spim0_sclk clock source
+set_interface_property sys_hps_spim0_sclk EXPORT_OF sys_hps.spim0_sclk_out
+add_interface sys_hps_i2c0_scl clock sink
+set_interface_property sys_hps_i2c0_scl EXPORT_OF sys_hps.i2c0_scl_in
+add_interface sys_hps_i2c0_clk clock source
+set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
+add_interface sys_hps_i2c0 conduit end
+set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
+add_interface sys_hps_ddr3 conduit end
+set_interface_property sys_hps_ddr3 EXPORT_OF sys_hps.memory
+add_interface sys_hps_io conduit end
+set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io
+add_interface sys_hps_rstn conduit end
+set_interface_property sys_hps_rstn EXPORT_OF sys_hps.h2f_reset
+add_connection sys_clk.clk sys_hps.h2f_axi_clock
+add_connection sys_hps.h2f_axi_master sys_int_mem.s1
+set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0}
+add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
+
+# cpu/hps handling
+
+proc ad_cpu_interrupt {m_irq m_port} {
+
+  add_connection sys_hps.f2h_irq0 ${m_port}
+  set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
+}
+
+proc ad_cpu_interconnect {m_base m_port} {
+
+  add_connection sys_hps.h2f_lw_axi_master ${m_port}
+  set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress $m_base
+}
+
+proc ad_dma_interconnect {m_port} {
+
+  add_connection ${m_port} sys_hps.f2h_axi_slave
+  set_connection_parameter_value ${m_port}/sys_hps.f2h_axi_slave baseAddress {0x0}
+}
+
+# common dma interfaces
+
+add_instance sys_dma_clk clock_source 16.0
+add_interface sys_dma_clk clock sink
+add_interface sys_dma_rst reset sink
+set_interface_property sys_dma_clk EXPORT_OF sys_dma_clk.clk_in
+set_interface_property sys_dma_rst EXPORT_OF sys_dma_clk.clk_in_reset
+set_instance_parameter_value sys_dma_clk {clockFrequency} {100000000.0}
+set_instance_parameter_value sys_dma_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_dma_clk {resetSynchronousEdges} {DEASSERT}
+add_connection sys_dma_clk.clk sys_hps.f2h_axi_clock
+
+# sys-id
+
+add_instance sys_id altera_avalon_sysid_qsys 16.0
+set_instance_parameter_value sys_id {id} {182193580}
+add_connection sys_clk.clk_reset sys_id.reset
+add_connection sys_clk.clk sys_id.clk
+
+# gpio-bd
+
+add_instance sys_gpio_bd altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_bd {direction} {InOut}
+set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_bd {width} {32}
+add_connection sys_clk.clk_reset sys_gpio_bd.reset
+add_connection sys_clk.clk sys_gpio_bd.clk
+add_interface sys_gpio_bd conduit end
+set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
+
+# gpio-in
+
+add_instance sys_gpio_in altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_in {direction} {Input}
+set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_in {width} {32}
+add_connection sys_clk.clk_reset sys_gpio_in.reset
+add_connection sys_clk.clk sys_gpio_in.clk
+add_interface sys_gpio_in conduit end
+set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
+
+# gpio-out
+
+add_instance sys_gpio_out altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_out {direction} {Output}
+set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
+set_instance_parameter_value sys_gpio_out {width} {32}
+add_connection sys_clk.clk_reset sys_gpio_out.reset
+add_connection sys_clk.clk sys_gpio_out.clk
+add_interface sys_gpio_out conduit end
+set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
+
+# base-addresses
+
+ad_cpu_interconnect 0x001814e8 sys_id.control_slave
+ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1
+ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1
+ad_cpu_interconnect 0x00181500 sys_gpio_out.s1
+
+# interrupts
+
+ad_cpu_interrupt 0 sys_gpio_in.irq
+ad_cpu_interrupt 1 sys_gpio_bd.irq
+

From 8ea9beffaf7ce0187e4b5d040aee390eb279a8b0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Nov 2016 15:00:29 -0400
Subject: [PATCH 664/972] fmcjesdadc1- a5soc tcl updates

---
 projects/common/a5soc/a5soc_system_qsys.tcl   |    4 +-
 projects/fmcjesdadc1/a5soc/system_bd.qsys     |  313 ----
 projects/fmcjesdadc1/a5soc/system_project.tcl |    4 +-
 projects/fmcjesdadc1/a5soc/system_qsys.tcl    |    6 +
 .../fmcjesdadc1/common/fmcjesdadc1_bd.qsys    | 1284 -----------------
 .../fmcjesdadc1/common/fmcjesdadc1_qsys.tcl   |  138 ++
 6 files changed, 147 insertions(+), 1602 deletions(-)
 delete mode 100644 projects/fmcjesdadc1/a5soc/system_bd.qsys
 create mode 100644 projects/fmcjesdadc1/a5soc/system_qsys.tcl
 delete mode 100644 projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys
 create mode 100644 projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl

diff --git a/projects/common/a5soc/a5soc_system_qsys.tcl b/projects/common/a5soc/a5soc_system_qsys.tcl
index 7cd68f8fe..f25bbd34d 100644
--- a/projects/common/a5soc/a5soc_system_qsys.tcl
+++ b/projects/common/a5soc/a5soc_system_qsys.tcl
@@ -2,8 +2,8 @@
 package require qsys
 
 set_module_property NAME {system_bd}
-set_project_property DEVICE_FAMILY {Arria 10}
-set_project_property DEVICE {10AX115S3F45E2SGE3}
+set_project_property DEVICE_FAMILY {Arria V}
+set_project_property DEVICE {5ASTFD5K3F40I3ES}
 
 set system_type nios
 
diff --git a/projects/fmcjesdadc1/a5soc/system_bd.qsys b/projects/fmcjesdadc1/a5soc/system_bd.qsys
deleted file mode 100644
index 67c2527a4..000000000
--- a/projects/fmcjesdadc1/a5soc/system_bd.qsys
+++ /dev/null
@@ -1,313 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element a5soc_base
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element a5soc_base.sys_hps_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element fmcjesdadc1.axi_ad9250_0_s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_ad9250_1_s_axi
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_dmac_0_s_axi
-   {
-      datum baseAddress
-      {
-         value = "212992";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_dmac_1_s_axi
-   {
-      datum baseAddress
-      {
-         value = "196608";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_jesd_xcvr_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5ASTFD5K3F40I3ES" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName">fmcjesdadc1_a5soc.qpf</parameter>
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="a5soc_base_sys_gpio_bd_external_connection"
-   internal="a5soc_base.sys_gpio_bd_external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5soc_base_sys_gpio_external_connection"
-   internal="a5soc_base.sys_gpio_external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5soc_base_sys_hps_i2c0"
-   internal="a5soc_base.sys_hps_i2c0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5soc_base_sys_hps_i2c0_clk"
-   internal="a5soc_base.sys_hps_i2c0_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="a5soc_base_sys_hps_i2c0_scl_in"
-   internal="a5soc_base.sys_hps_i2c0_scl_in"
-   type="clock"
-   dir="end" />
- <interface
-   name="a5soc_base_sys_hps_io"
-   internal="a5soc_base.sys_hps_io"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5soc_base_sys_hps_memory"
-   internal="a5soc_base.sys_hps_memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5soc_base_sys_hps_spim0"
-   internal="a5soc_base.sys_hps_spim0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5soc_base_sys_hps_spim0_sclk_out"
-   internal="a5soc_base.sys_hps_spim0_sclk_out"
-   type="clock"
-   dir="start" />
- <interface
-   name="fmcjesdadc1_rx_data"
-   internal="fmcjesdadc1.rx_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="fmcjesdadc1_rx_ref_clk"
-   internal="fmcjesdadc1.rx_ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="fmcjesdadc1_rx_sync"
-   internal="fmcjesdadc1.rx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="fmcjesdadc1_rx_sysref"
-   internal="fmcjesdadc1.rx_sysref"
-   type="conduit"
-   dir="end" />
- <module name="a5soc_base" kind="a5soc_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcjesdadc1_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='fmcjesdadc1_axi_ad9250_1.s_axi' start='0x10000' end='0x20000' /><slave name='fmcjesdadc1_axi_ad9250_0.s_axi' start='0x20000' end='0x30000' /><slave name='fmcjesdadc1_axi_dmac_1.s_axi' start='0x30000' end='0x34000' /><slave name='fmcjesdadc1_axi_dmac_0.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
-     value="AddressWidth = 18" />
-  <parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_CLOCK_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_RESET_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a5soc_base</parameter>
- </module>
- <module name="fmcjesdadc1" kind="fmcjesdadc1_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5soc_base_sys_hps_axi_sdram.axi_slave0' start='0x0' end='0x80000000' /><slave name='a5soc_base_sys_hps_gmac0.axi_slave0' start='0xFF700000' end='0xFF702000' /><slave name='a5soc_base_sys_hps_gmac1.axi_slave0' start='0xFF702000' end='0xFF704000' /><slave name='a5soc_base_sys_hps_sdmmc.axi_slave0' start='0xFF704000' end='0xFF705000' /><slave name='a5soc_base_sys_hps_qspi.axi_slave0' start='0xFF705000' end='0xFF705100' /><slave name='a5soc_base_sys_hps_fpgamgr.axi_slave0' start='0xFF706000' end='0xFF707000' /><slave name='a5soc_base_sys_hps_gpio0.axi_slave0' start='0xFF708000' end='0xFF708100' /><slave name='a5soc_base_sys_hps_gpio1.axi_slave0' start='0xFF709000' end='0xFF709100' /><slave name='a5soc_base_sys_hps_gpio2.axi_slave0' start='0xFF70A000' end='0xFF70A100' /><slave name='a5soc_base_sys_hps_l3regs.axi_slave0' start='0xFF800000' end='0xFF801000' /><slave name='a5soc_base_sys_hps_nand0.axi_slave0' start='0xFF900000' end='0xFF910000' /><slave name='a5soc_base_sys_hps_qspi.axi_slave1' start='0xFFA00000' end='0xFFA00100' /><slave name='a5soc_base_sys_hps_usb0.axi_slave0' start='0xFFB00000' end='0xFFB40000' /><slave name='a5soc_base_sys_hps_usb1.axi_slave0' start='0xFFB40000' end='0xFFB80000' /><slave name='a5soc_base_sys_hps_nand0.axi_slave1' start='0xFFB80000' end='0xFFB90000' /><slave name='a5soc_base_sys_hps_fpgamgr.axi_slave1' start='0xFFB90000' end='0xFFB90100' /><slave name='a5soc_base_sys_hps_dcan0.axi_slave0' start='0xFFC00000' end='0xFFC01000' /><slave name='a5soc_base_sys_hps_dcan1.axi_slave0' start='0xFFC01000' end='0xFFC02000' /><slave name='a5soc_base_sys_hps_uart0.axi_slave0' start='0xFFC02000' end='0xFFC02100' /><slave name='a5soc_base_sys_hps_uart1.axi_slave0' start='0xFFC03000' end='0xFFC03100' /><slave name='a5soc_base_sys_hps_i2c0.axi_slave0' start='0xFFC04000' end='0xFFC04100' /><slave name='a5soc_base_sys_hps_i2c1.axi_slave0' start='0xFFC05000' end='0xFFC05100' /><slave name='a5soc_base_sys_hps_i2c2.axi_slave0' start='0xFFC06000' end='0xFFC06100' /><slave name='a5soc_base_sys_hps_i2c3.axi_slave0' start='0xFFC07000' end='0xFFC07100' /><slave name='a5soc_base_sys_hps_timer0.axi_slave0' start='0xFFC08000' end='0xFFC08100' /><slave name='a5soc_base_sys_hps_timer1.axi_slave0' start='0xFFC09000' end='0xFFC09100' /><slave name='a5soc_base_sys_hps_sdrctl.axi_slave0' start='0xFFC25000' end='0xFFC26000' /><slave name='a5soc_base_sys_hps_timer2.axi_slave0' start='0xFFD00000' end='0xFFD00100' /><slave name='a5soc_base_sys_hps_timer3.axi_slave0' start='0xFFD01000' end='0xFFD01100' /><slave name='a5soc_base_sys_hps_clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' /><slave name='a5soc_base_sys_hps_rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD05100' /><slave name='a5soc_base_sys_hps_sysmgr.axi_slave0' start='0xFFD08000' end='0xFFD08400' /><slave name='a5soc_base_sys_hps_dma.axi_slave0' start='0xFFE01000' end='0xFFE02000' /><slave name='a5soc_base_sys_hps_spim0.axi_slave0' start='0xFFF00000' end='0xFFF00100' /><slave name='a5soc_base_sys_hps_spim1.axi_slave0' start='0xFFF01000' end='0xFFF01100' /><slave name='a5soc_base_sys_hps_arm_gic_0.axi_slave1' start='0xFFFEC100' end='0xFFFEC200' /><slave name='a5soc_base_sys_hps_timer.axi_slave0' start='0xFFFEC600' end='0xFFFEC700' /><slave name='a5soc_base_sys_hps_arm_gic_0.axi_slave0' start='0xFFFED000' end='0xFFFEE000' /><slave name='a5soc_base_sys_hps_L2.axi_slave0' start='0xFFFEF000' end='0xFFFF0000' /><slave name='a5soc_base_sys_hps_axi_ocram.axi_slave0' start='0xFFFF0000' end='0x100000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 32" />
-  <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5soc_base_sys_hps_axi_sdram.axi_slave0' start='0x0' end='0x80000000' /><slave name='a5soc_base_sys_hps_gmac0.axi_slave0' start='0xFF700000' end='0xFF702000' /><slave name='a5soc_base_sys_hps_gmac1.axi_slave0' start='0xFF702000' end='0xFF704000' /><slave name='a5soc_base_sys_hps_sdmmc.axi_slave0' start='0xFF704000' end='0xFF705000' /><slave name='a5soc_base_sys_hps_qspi.axi_slave0' start='0xFF705000' end='0xFF705100' /><slave name='a5soc_base_sys_hps_fpgamgr.axi_slave0' start='0xFF706000' end='0xFF707000' /><slave name='a5soc_base_sys_hps_gpio0.axi_slave0' start='0xFF708000' end='0xFF708100' /><slave name='a5soc_base_sys_hps_gpio1.axi_slave0' start='0xFF709000' end='0xFF709100' /><slave name='a5soc_base_sys_hps_gpio2.axi_slave0' start='0xFF70A000' end='0xFF70A100' /><slave name='a5soc_base_sys_hps_l3regs.axi_slave0' start='0xFF800000' end='0xFF801000' /><slave name='a5soc_base_sys_hps_nand0.axi_slave0' start='0xFF900000' end='0xFF910000' /><slave name='a5soc_base_sys_hps_qspi.axi_slave1' start='0xFFA00000' end='0xFFA00100' /><slave name='a5soc_base_sys_hps_usb0.axi_slave0' start='0xFFB00000' end='0xFFB40000' /><slave name='a5soc_base_sys_hps_usb1.axi_slave0' start='0xFFB40000' end='0xFFB80000' /><slave name='a5soc_base_sys_hps_nand0.axi_slave1' start='0xFFB80000' end='0xFFB90000' /><slave name='a5soc_base_sys_hps_fpgamgr.axi_slave1' start='0xFFB90000' end='0xFFB90100' /><slave name='a5soc_base_sys_hps_dcan0.axi_slave0' start='0xFFC00000' end='0xFFC01000' /><slave name='a5soc_base_sys_hps_dcan1.axi_slave0' start='0xFFC01000' end='0xFFC02000' /><slave name='a5soc_base_sys_hps_uart0.axi_slave0' start='0xFFC02000' end='0xFFC02100' /><slave name='a5soc_base_sys_hps_uart1.axi_slave0' start='0xFFC03000' end='0xFFC03100' /><slave name='a5soc_base_sys_hps_i2c0.axi_slave0' start='0xFFC04000' end='0xFFC04100' /><slave name='a5soc_base_sys_hps_i2c1.axi_slave0' start='0xFFC05000' end='0xFFC05100' /><slave name='a5soc_base_sys_hps_i2c2.axi_slave0' start='0xFFC06000' end='0xFFC06100' /><slave name='a5soc_base_sys_hps_i2c3.axi_slave0' start='0xFFC07000' end='0xFFC07100' /><slave name='a5soc_base_sys_hps_timer0.axi_slave0' start='0xFFC08000' end='0xFFC08100' /><slave name='a5soc_base_sys_hps_timer1.axi_slave0' start='0xFFC09000' end='0xFFC09100' /><slave name='a5soc_base_sys_hps_sdrctl.axi_slave0' start='0xFFC25000' end='0xFFC26000' /><slave name='a5soc_base_sys_hps_timer2.axi_slave0' start='0xFFD00000' end='0xFFD00100' /><slave name='a5soc_base_sys_hps_timer3.axi_slave0' start='0xFFD01000' end='0xFFD01100' /><slave name='a5soc_base_sys_hps_clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' /><slave name='a5soc_base_sys_hps_rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD05100' /><slave name='a5soc_base_sys_hps_sysmgr.axi_slave0' start='0xFFD08000' end='0xFFD08400' /><slave name='a5soc_base_sys_hps_dma.axi_slave0' start='0xFFE01000' end='0xFFE02000' /><slave name='a5soc_base_sys_hps_spim0.axi_slave0' start='0xFFF00000' end='0xFFF00100' /><slave name='a5soc_base_sys_hps_spim1.axi_slave0' start='0xFFF01000' end='0xFFF01100' /><slave name='a5soc_base_sys_hps_arm_gic_0.axi_slave1' start='0xFFFEC100' end='0xFFFEC200' /><slave name='a5soc_base_sys_hps_timer.axi_slave0' start='0xFFFEC600' end='0xFFFEC700' /><slave name='a5soc_base_sys_hps_arm_gic_0.axi_slave0' start='0xFFFED000' end='0xFFFEE000' /><slave name='a5soc_base_sys_hps_L2.axi_slave0' start='0xFFFEF000' end='0xFFFF0000' /><slave name='a5soc_base_sys_hps_axi_ocram.axi_slave0' start='0xFFFF0000' end='0x100000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 32" />
-  <parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="50000000" />
-  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcjesdadc1</parameter>
- </module>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="fmcjesdadc1.axi_dmac_0_m_axi"
-   end="a5soc_base.sys_hps_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="fmcjesdadc1.axi_dmac_1_m_axi"
-   end="a5soc_base.sys_hps_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="a5soc_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_ad9250_0_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="a5soc_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_ad9250_1_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="a5soc_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_dmac_0_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00034000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="a5soc_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_dmac_1_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.0"
-   start="a5soc_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_jesd_xcvr_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="15.0"
-   start="a5soc_base.sys_clk"
-   end="fmcjesdadc1.mem_clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="a5soc_base.sys_clk"
-   end="fmcjesdadc1.sys_clk" />
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="a5soc_base.sys_intr"
-   end="fmcjesdadc1.axi_dmac_0_intr">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="a5soc_base.sys_intr"
-   end="fmcjesdadc1.axi_dmac_1_intr">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="reset"
-   version="15.0"
-   start="a5soc_base.sys_rst"
-   end="fmcjesdadc1.mem_rst" />
- <connection
-   kind="reset"
-   version="15.0"
-   start="a5soc_base.sys_rst"
-   end="fmcjesdadc1.sys_rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/fmcjesdadc1/a5soc/system_project.tcl b/projects/fmcjesdadc1/a5soc/system_project.tcl
index 27d33b6d2..5fe987c65 100755
--- a/projects/fmcjesdadc1/a5soc/system_project.tcl
+++ b/projects/fmcjesdadc1/a5soc/system_project.tcl
@@ -5,12 +5,10 @@ source ../../scripts/adi_env.tcl
 project_new fmcjesdadc1_a5soc -overwrite
 
 source "../../common/a5soc/a5soc_system_assign.tcl"
-set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a5soc;../../../library/**/*"
-set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a5soc/;../../../library/**/*"
-set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
diff --git a/projects/fmcjesdadc1/a5soc/system_qsys.tcl b/projects/fmcjesdadc1/a5soc/system_qsys.tcl
new file mode 100644
index 000000000..3537ec761
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/system_qsys.tcl
@@ -0,0 +1,6 @@
+
+source $ad_hdl_dir/projects/common/a5soc/a5soc_system_qsys.tcl
+source ../common/fmcjesdadc1_qsys.tcl
+
+save_system "system_bd.qsys"
+
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys
deleted file mode 100644
index 780a3c68b..000000000
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys
+++ /dev/null
@@ -1,1284 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element axi_ad9250_0
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9250_0.s_axi
-   {
-      datum baseAddress
-      {
-         value = "272695296";
-         type = "String";
-      }
-   }
-   element axi_ad9250_1
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9250_1.s_axi
-   {
-      datum baseAddress
-      {
-         value = "272760832";
-         type = "String";
-      }
-   }
-   element axi_dmac_0
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dmac_0.s_axi
-   {
-      datum baseAddress
-      {
-         value = "272842752";
-         type = "String";
-      }
-   }
-   element axi_dmac_1
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dmac_1.s_axi
-   {
-      datum baseAddress
-      {
-         value = "272826368";
-         type = "String";
-      }
-   }
-   element axi_jesd_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_jesd_xcvr.s_axi
-   {
-      datum baseAddress
-      {
-         value = "272629760";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element mem_clk
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element mem_rst
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element rx_ref_clk
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element util_bsplit
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element util_cpack_0
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element util_cpack_1
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element xcvr_core
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-   }
-   element xcvr_rst_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element xcvr_rx_pll
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5AGTFD7K3F40I3" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="axi_ad9250_0_adc_clock" internal="axi_ad9250_0.adc_clock" />
- <interface name="axi_ad9250_0_adc_dma_if" internal="axi_ad9250_0.adc_dma_if" />
- <interface name="axi_ad9250_0_adc_mon_if" internal="axi_ad9250_0.adc_mon_if" />
- <interface
-   name="axi_ad9250_0_s_axi"
-   internal="axi_ad9250_0.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface name="axi_ad9250_0_xcvr_clk" internal="axi_ad9250_0.xcvr_clk" />
- <interface name="axi_ad9250_0_xcvr_data" internal="axi_ad9250_0.xcvr_data" />
- <interface name="axi_ad9250_1_adc_clock" internal="axi_ad9250_1.adc_clock" />
- <interface name="axi_ad9250_1_adc_dma_if" internal="axi_ad9250_1.adc_dma_if" />
- <interface name="axi_ad9250_1_adc_mon_if" internal="axi_ad9250_1.adc_mon_if" />
- <interface
-   name="axi_ad9250_1_s_axi"
-   internal="axi_ad9250_1.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface name="axi_ad9250_1_xcvr_clk" internal="axi_ad9250_1.xcvr_clk" />
- <interface name="axi_ad9250_1_xcvr_data" internal="axi_ad9250_1.xcvr_data" />
- <interface name="axi_dmac_0_fifo_wr_clock" internal="axi_dmac_0.fifo_wr_clock" />
- <interface name="axi_dmac_0_fifo_wr_if" internal="axi_dmac_0.fifo_wr_if" />
- <interface
-   name="axi_dmac_0_intr"
-   internal="axi_dmac_0.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_0_m_axi"
-   internal="axi_dmac_0.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_0_s_axi"
-   internal="axi_dmac_0.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface name="axi_dmac_1_fifo_wr_clock" internal="axi_dmac_1.fifo_wr_clock" />
- <interface name="axi_dmac_1_fifo_wr_if" internal="axi_dmac_1.fifo_wr_if" />
- <interface
-   name="axi_dmac_1_intr"
-   internal="axi_dmac_1.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_1_m_axi"
-   internal="axi_dmac_1.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_1_s_axi"
-   internal="axi_dmac_1.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_jesd204_rx_avs"
-   internal="xcvr_core.jesd204_rx_avs"
-   type="avalon"
-   dir="end" />
- <interface
-   name="axi_jesd_xcvr_s_axi"
-   internal="axi_jesd_xcvr.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface name="cpu_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface name="cpu_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
- <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="rx_data"
-   internal="xcvr_core.rx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface name="rx_ref_clk" internal="rx_ref_clk.in_clk" type="clock" dir="end" />
- <interface
-   name="rx_sync"
-   internal="axi_jesd_xcvr.if_rx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sysref"
-   internal="axi_jesd_xcvr.if_rx_ext_sysref_out"
-   type="conduit"
-   dir="end" />
- <interface name="tx_ref_clk" internal="axi_jesd_xcvr.if_tx_ref_clk" />
- <module name="axi_ad9250_0" kind="axi_ad9250" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_ad9250_1" kind="axi_ad9250" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_dmac_0" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="256" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="64" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
- </module>
- <module name="axi_dmac_1" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="256" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="64" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
- </module>
- <module name="axi_jesd_xcvr" kind="axi_jesd_xcvr" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
-  <parameter name="RX_NUM_OF_LANES" value="4" />
-  <parameter name="TX_NUM_OF_LANES" value="4" />
- </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module
-   name="rx_ref_clk"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="250000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="util_bsplit" kind="util_bsplit" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="64" />
-  <parameter name="NUM_OF_CHANNELS" value="2" />
- </module>
- <module name="util_cpack_0" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
-  <parameter name="NUM_OF_CHANNELS" value="2" />
- </module>
- <module name="util_cpack_1" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
-  <parameter name="NUM_OF_CHANNELS" value="2" />
- </module>
- <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX" />
-  <parameter name="DEVICE_FAMILY" value="Arria V" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="ED_DEV_KIT" value="NONE" />
-  <parameter name="ED_FILESET_SIM" value="false" />
-  <parameter name="ED_FILESET_SYNTH" value="false" />
-  <parameter name="ED_GENERIC_5SERIES" value="No" />
-  <parameter name="ED_GENERIC_A10" value="No" />
-  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
-  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
-  <parameter name="GUI_CFG_F" value="4" />
-  <parameter name="GUI_EN_CFG_F" value="false" />
-  <parameter name="HD" value="0" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="32" />
-  <parameter name="L" value="4" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="4" />
-  <parameter name="N" value="16" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="250.0" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="1" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="bonded" />
-  <parameter name="lane_rate" value="5000.0" />
-  <parameter name="part_trait_bd" value="ARRIAVB7" />
-  <parameter name="part_trait_dp" value="5AGTFD7K3F40I3" />
-  <parameter name="pll_reconfig_enable" value="false" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="set_capability_reg_enable" value="false" />
-  <parameter name="set_csr_soft_logic_enable" value="false" />
-  <parameter name="set_prbs_soft_logic_enable" value="false" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module
-   name="xcvr_rst_cntrl"
-   kind="altera_xcvr_reset_control"
-   version="15.1"
-   enabled="1">
-  <parameter name="CHANNELS" value="4" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="1" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="100" />
-  <parameter name="TX_ENABLE" value="0" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="0" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_ANALOGRESET" value="0" />
-  <parameter name="T_TX_DIGITALRESET" value="20" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="gui_pll_cal_busy" value="0" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="1" />
- </module>
- <module name="xcvr_rx_pll" kind="altera_pll" version="15.1" enabled="1">
-  <parameter name="debug_print_output" value="false" />
-  <parameter name="debug_use_rbc_taf_method" value="false" />
-  <parameter name="device" value="5AGTFD7K3F40I3" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
-  <parameter name="gui_actual_phase_shift0" value="0" />
-  <parameter name="gui_actual_phase_shift1" value="0" />
-  <parameter name="gui_actual_phase_shift10" value="0" />
-  <parameter name="gui_actual_phase_shift11" value="0" />
-  <parameter name="gui_actual_phase_shift12" value="0" />
-  <parameter name="gui_actual_phase_shift13" value="0" />
-  <parameter name="gui_actual_phase_shift14" value="0" />
-  <parameter name="gui_actual_phase_shift15" value="0" />
-  <parameter name="gui_actual_phase_shift16" value="0" />
-  <parameter name="gui_actual_phase_shift17" value="0" />
-  <parameter name="gui_actual_phase_shift2" value="0" />
-  <parameter name="gui_actual_phase_shift3" value="0" />
-  <parameter name="gui_actual_phase_shift4" value="0" />
-  <parameter name="gui_actual_phase_shift5" value="0" />
-  <parameter name="gui_actual_phase_shift6" value="0" />
-  <parameter name="gui_actual_phase_shift7" value="0" />
-  <parameter name="gui_actual_phase_shift8" value="0" />
-  <parameter name="gui_actual_phase_shift9" value="0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_channel_spacing" value="0.0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_device_speed_grade" value="2" />
-  <parameter name="gui_divide_factor_c0" value="1" />
-  <parameter name="gui_divide_factor_c1" value="1" />
-  <parameter name="gui_divide_factor_c10" value="1" />
-  <parameter name="gui_divide_factor_c11" value="1" />
-  <parameter name="gui_divide_factor_c12" value="1" />
-  <parameter name="gui_divide_factor_c13" value="1" />
-  <parameter name="gui_divide_factor_c14" value="1" />
-  <parameter name="gui_divide_factor_c15" value="1" />
-  <parameter name="gui_divide_factor_c16" value="1" />
-  <parameter name="gui_divide_factor_c17" value="1" />
-  <parameter name="gui_divide_factor_c2" value="1" />
-  <parameter name="gui_divide_factor_c3" value="1" />
-  <parameter name="gui_divide_factor_c4" value="1" />
-  <parameter name="gui_divide_factor_c5" value="1" />
-  <parameter name="gui_divide_factor_c6" value="1" />
-  <parameter name="gui_divide_factor_c7" value="1" />
-  <parameter name="gui_divide_factor_c8" value="1" />
-  <parameter name="gui_divide_factor_c9" value="1" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50" />
-  <parameter name="gui_duty_cycle1" value="50" />
-  <parameter name="gui_duty_cycle10" value="50" />
-  <parameter name="gui_duty_cycle11" value="50" />
-  <parameter name="gui_duty_cycle12" value="50" />
-  <parameter name="gui_duty_cycle13" value="50" />
-  <parameter name="gui_duty_cycle14" value="50" />
-  <parameter name="gui_duty_cycle15" value="50" />
-  <parameter name="gui_duty_cycle16" value="50" />
-  <parameter name="gui_duty_cycle17" value="50" />
-  <parameter name="gui_duty_cycle2" value="50" />
-  <parameter name="gui_duty_cycle3" value="50" />
-  <parameter name="gui_duty_cycle4" value="50" />
-  <parameter name="gui_duty_cycle5" value="50" />
-  <parameter name="gui_duty_cycle6" value="50" />
-  <parameter name="gui_duty_cycle7" value="50" />
-  <parameter name="gui_duty_cycle8" value="50" />
-  <parameter name="gui_duty_cycle9" value="50" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_number_of_clocks" value="1" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="125.0" />
-  <parameter name="gui_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0" />
-  <parameter name="gui_phase_shift1" value="0" />
-  <parameter name="gui_phase_shift10" value="0" />
-  <parameter name="gui_phase_shift11" value="0" />
-  <parameter name="gui_phase_shift12" value="0" />
-  <parameter name="gui_phase_shift13" value="0" />
-  <parameter name="gui_phase_shift14" value="0" />
-  <parameter name="gui_phase_shift15" value="0" />
-  <parameter name="gui_phase_shift16" value="0" />
-  <parameter name="gui_phase_shift17" value="0" />
-  <parameter name="gui_phase_shift2" value="0" />
-  <parameter name="gui_phase_shift3" value="0" />
-  <parameter name="gui_phase_shift4" value="0" />
-  <parameter name="gui_phase_shift5" value="0" />
-  <parameter name="gui_phase_shift6" value="0" />
-  <parameter name="gui_phase_shift7" value="0" />
-  <parameter name="gui_phase_shift8" value="0" />
-  <parameter name="gui_phase_shift9" value="0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="Off" />
-  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
-  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="250.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_locked" value="true" />
- </module>
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="xcvr_core.jesd204_rx_link"
-   end="axi_jesd_xcvr.if_rx_ip_avl" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9250_0.if_adc_clk"
-   end="util_cpack_0.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9250_1.if_adc_clk"
-   end="util_cpack_1.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9250_1.if_adc_clk"
-   end="axi_dmac_1.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9250_0.if_adc_clk"
-   end="axi_dmac_0.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_rst_cntrl.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="xcvr_core.jesd204_rx_avs_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_dmac_1.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_dmac_0.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="rx_ref_clk.out_clk"
-   end="xcvr_core.pll_ref_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="rx_ref_clk.out_clk"
-   end="xcvr_rx_pll.refclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9250_1.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_0.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dmac_1.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_jesd_xcvr.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9250_0.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_ad9250_1.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_ad9250_0.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_jesd_xcvr.if_rx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_jesd_xcvr.if_tx_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="xcvr_rx_pll.outclk0"
-   end="xcvr_core.rxlink_clk" />
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.dev_lane_aligned"
-   end="xcvr_core.alldev_lane_aligned">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9250_0.fifo_ch_0_in"
-   end="util_cpack_0.fifo_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9250_1.fifo_ch_0_in"
-   end="util_cpack_1.fifo_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9250_0.fifo_ch_1_in"
-   end="util_cpack_0.fifo_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9250_1.fifo_ch_1_in"
-   end="util_cpack_1.fifo_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_cpack_0.if_adc_data"
-   end="axi_dmac_0.if_fifo_wr_din">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_cpack_1.if_adc_data"
-   end="axi_dmac_1.if_fifo_wr_din">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_cpack_0.if_adc_sync"
-   end="axi_dmac_0.if_fifo_wr_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_cpack_1.if_adc_sync"
-   end="axi_dmac_1.if_fifo_wr_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_0.if_fifo_wr_en"
-   end="util_cpack_0.if_adc_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_1.if_fifo_wr_en"
-   end="util_cpack_1.if_adc_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_0.if_fifo_wr_overflow"
-   end="axi_ad9250_0.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dmac_1.if_fifo_wr_overflow"
-   end="axi_ad9250_1.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_data"
-   end="util_bsplit.if_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9250_0.if_rx_data"
-   end="util_bsplit.if_split_data_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sync"
-   end="xcvr_core.dev_sync_n">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_ip_sysref"
-   end="xcvr_core.sysref">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_bsplit.if_split_data_1"
-   end="axi_ad9250_1.if_rx_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.rx_analogreset"
-   end="xcvr_core.rx_analogreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.rx_cal_busy"
-   end="xcvr_rst_cntrl.rx_cal_busy">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.rx_digitalreset"
-   end="xcvr_rst_cntrl.rx_digitalreset">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.rx_is_lockedtodata"
-   end="xcvr_core.rx_islockedtodata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_rst_cntrl.rx_ready"
-   end="axi_jesd_xcvr.if_rx_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="xcvr_core.sof"
-   end="axi_jesd_xcvr.if_rx_ip_sof">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_ad9250_1.if_adc_rst"
-   end="util_cpack_1.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_ad9250_0.if_adc_rst"
-   end="util_cpack_0.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_rx_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_jesd_xcvr.if_rx_rstn"
-   end="xcvr_core.rxlink_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="xcvr_core.jesd204_rx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="axi_dmac_1.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="axi_dmac_0.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9250_1.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_0.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dmac_1.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_jesd_xcvr.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9250_0.s_axi_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
new file mode 100644
index 000000000..4b8962212
--- /dev/null
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
@@ -0,0 +1,138 @@
+
+# ad9250-xcvr
+
+add_instance avl_ad9250_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_ad9250_xcvr {ID} {1}
+set_instance_parameter_value avl_ad9250_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value avl_ad9250_xcvr {PCS_CONFIG} {JESD_PCS_CFG1}
+set_instance_parameter_value avl_ad9250_xcvr {LANE_RATE} {5000.0}
+set_instance_parameter_value avl_ad9250_xcvr {PLLCLK_FREQUENCY} {2500.0}
+set_instance_parameter_value avl_ad9250_xcvr {REFCLK_FREQUENCY} {250.0}
+set_instance_parameter_value avl_ad9250_xcvr {CORECLK_FREQUENCY} {125.0}
+set_instance_parameter_value avl_ad9250_xcvr {NUM_OF_LANES} {4}
+set_instance_parameter_value avl_ad9250_xcvr {NUM_OF_CONVS} {4}
+set_instance_parameter_value avl_ad9250_xcvr {FRM_BCNT} {4}
+set_instance_parameter_value avl_ad9250_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_ad9250_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_ad9250_xcvr {HD} {0}
+
+add_connection sys_clk.clk avl_ad9250_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_ad9250_xcvr.sys_resetn
+add_interface rx_ref_clk clock sink
+set_interface_property rx_ref_clk EXPORT_OF avl_ad9250_xcvr.ref_clk
+add_interface rx_data_0 conduit end
+set_interface_property rx_data_0 EXPORT_OF avl_ad9250_xcvr.rx_data_0
+add_interface rx_data_1 conduit end
+set_interface_property rx_data_1 EXPORT_OF avl_ad9250_xcvr.rx_data_1
+add_interface rx_data_2 conduit end
+set_interface_property rx_data_2 EXPORT_OF avl_ad9250_xcvr.rx_data_2
+add_interface rx_data_3 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_ad9250_xcvr.rx_data_3
+add_interface rx_sysref conduit end
+set_interface_property rx_sysref EXPORT_OF avl_ad9250_xcvr.sysref
+add_interface rx_sync conduit end
+set_interface_property rx_sync EXPORT_OF avl_ad9250_xcvr.sync
+
+# ad9250-xcvr
+
+add_instance axi_ad9250_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_ad9250_xcvr {ID} {1}
+set_instance_parameter_value axi_ad9250_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value axi_ad9250_xcvr {NUM_OF_LANES} {4}
+
+add_connection sys_clk.clk axi_ad9250_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9250_xcvr.s_axi_reset
+add_connection axi_ad9250_xcvr.if_up_rst avl_ad9250_xcvr.rst
+add_connection avl_ad9250_xcvr.ready axi_ad9250_xcvr.ready
+add_connection axi_ad9250_xcvr.core_pll_locked avl_ad9250_xcvr.core_pll_locked
+
+# ad9250
+
+add_instance axi_ad9250_core_0 axi_ad9250 1.0
+
+add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_0.if_rx_clk
+add_connection avl_ad9250_xcvr.ip_sof axi_ad9250_core_0.if_rx_sof
+add_connection avl_ad9250_xcvr.ip_data axi_ad9250_core_0.if_rx_data
+add_connection sys_clk.clk_reset axi_ad9250_core_0.s_axi_reset
+add_connection sys_clk.clk axi_ad9250_core_0.s_axi_clock
+
+add_instance axi_ad9250_core_1 axi_ad9250 1.0
+
+add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_1.if_rx_clk
+add_connection avl_ad9250_xcvr.ip_sof axi_ad9250_core_1.if_rx_sof
+add_connection avl_ad9250_xcvr.ip_data axi_ad9250_core_1.if_rx_data
+add_connection sys_clk.clk_reset axi_ad9250_core_1.s_axi_reset
+add_connection sys_clk.clk axi_ad9250_core_1.s_axi_clock
+
+# ad9250-pack
+
+add_instance util_ad9250_cpack util_cpack 1.0
+set_instance_parameter_value util_ad9250_cpack {CHANNEL_DATA_WIDTH} {32}
+set_instance_parameter_value util_ad9250_cpack {NUM_OF_CHANNELS} {4}
+
+add_connection sys_clk.clk_reset util_ad9250_cpack.if_adc_rst
+add_connection sys_dma_clk.clk_reset util_ad9250_cpack.if_adc_rst
+add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack.if_adc_clk
+add_connection axi_ad9250_core_0.adc_ch_0 util_ad9250_cpack.adc_ch_0
+add_connection axi_ad9250_core_0.adc_ch_1 util_ad9250_cpack.adc_ch_1
+add_connection axi_ad9250_core_1.adc_ch_0 util_ad9250_cpack.adc_ch_2
+add_connection axi_ad9250_core_1.adc_ch_1 util_ad9250_cpack.adc_ch_3
+
+# ad9250-fifo
+
+add_instance ad9250_adcfifo util_adcfifo 1.0
+set_instance_parameter_value ad9250_adcfifo {ADC_DATA_WIDTH} {128}
+set_instance_parameter_value ad9250_adcfifo {DMA_DATA_WIDTH} {128}
+set_instance_parameter_value ad9250_adcfifo {DMA_ADDRESS_WIDTH} {16}
+
+add_connection sys_clk.clk_reset ad9250_adcfifo.if_adc_rst
+add_connection sys_dma_clk.clk_reset ad9250_adcfifo.if_adc_rst
+add_connection avl_ad9250_xcvr.core_clk ad9250_adcfifo.if_adc_clk
+add_connection util_ad9250_cpack.if_adc_valid ad9250_adcfifo.if_adc_wr
+add_connection util_ad9250_cpack.if_adc_data ad9250_adcfifo.if_adc_wdata
+add_connection sys_dma_clk.clk ad9250_adcfifo.if_dma_clk
+
+# ad9250-dma
+
+add_instance axi_ad9250_dma axi_dmac 1.0
+set_instance_parameter_value axi_ad9250_dma {DMA_DATA_WIDTH_SRC} {128}
+set_instance_parameter_value axi_ad9250_dma {DMA_DATA_WIDTH_DEST} {128}
+set_instance_parameter_value axi_ad9250_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9250_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9250_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_ad9250_dma {CYCLIC} {0}
+set_instance_parameter_value axi_ad9250_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9250_dma {DMA_TYPE_SRC} {1}
+
+add_connection sys_dma_clk.clk axi_ad9250_dma.if_s_axis_aclk
+add_connection ad9250_adcfifo.if_dma_wr axi_ad9250_dma.if_s_axis_valid
+add_connection ad9250_adcfifo.if_dma_wdata axi_ad9250_dma.if_s_axis_data
+add_connection ad9250_adcfifo.if_dma_wready axi_ad9250_dma.if_s_axis_ready
+add_connection ad9250_adcfifo.if_dma_xfer_req axi_ad9250_dma.if_s_axis_xfer_req
+add_connection ad9250_adcfifo.if_adc_wovf axi_ad9250_core_0.if_adc_dovf
+add_connection sys_clk.clk_reset axi_ad9250_dma.s_axi_reset
+add_connection sys_clk.clk axi_ad9250_dma.s_axi_clock
+add_connection sys_dma_clk.clk_reset axi_ad9250_dma.m_dest_axi_reset
+add_connection sys_dma_clk.clk axi_ad9250_dma.m_dest_axi_clock
+
+# addresses
+
+ad_cpu_interconnect 0x00010000 avl_ad9250_xcvr.phy_reconfig_0
+ad_cpu_interconnect 0x00011000 avl_ad9250_xcvr.phy_reconfig_1
+ad_cpu_interconnect 0x00012000 avl_ad9250_xcvr.phy_reconfig_2
+ad_cpu_interconnect 0x00013000 avl_ad9250_xcvr.phy_reconfig_3
+ad_cpu_interconnect 0x00018000 avl_ad9250_xcvr.core_pll_reconfig
+ad_cpu_interconnect 0x00019000 avl_ad9250_xcvr.ip_reconfig
+ad_cpu_interconnect 0x00020000 axi_ad9250_xcvr.s_axi
+ad_cpu_interconnect 0x00050000 axi_ad9250_core_0.s_axi
+ad_cpu_interconnect 0x00060000 axi_ad9250_core_1.s_axi
+ad_cpu_interconnect 0x00070000 axi_ad9250_dma.s_axi
+
+# dma interconnects
+
+ad_dma_interconnect axi_ad9250_dma.m_dest_axi
+
+# interrupts
+
+ad_cpu_interrupt 11 axi_ad9250_dma.interrupt_sender
+

From 6b492b79db02526f7c53df9222a00dd0f6024217 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Nov 2016 15:00:49 -0400
Subject: [PATCH 665/972] a10soc - remove default assignments

---
 projects/common/a10soc/a10soc_system_assign.tcl | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
index 8ad011f59..80b9fcd7d 100755
--- a/projects/common/a10soc/a10soc_system_assign.tcl
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -254,16 +254,6 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[1]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[2]
 set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[3]
 
-# globals
-
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
-set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
-
 # source defaults
 
 source $ad_hdl_dir/projects/common/altera/sys_gen.tcl

From ee9c8b884d3aeab5e38c6ede654874eac0b1989c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Nov 2016 15:01:09 -0400
Subject: [PATCH 666/972] avlxcvr- add arria v support

---
 library/altera/avl_adxcvr/avl_adxcvr_hw.tcl | 81 ++++++++++++++++-----
 1 file changed, 64 insertions(+), 17 deletions(-)

diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
index 0a480a619..382d3845f 100755
--- a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
@@ -124,15 +124,30 @@ proc p_avl_adxcvr {} {
   add_interface ref_clk clock sink
   set_interface_property ref_clk EXPORT_OF alt_ref_clk.in_clk
 
-  add_instance alt_core_pll altera_iopll 16.0
-  set_instance_parameter_value alt_core_pll {gui_en_reconf} {1}
-  set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency
-  set_instance_parameter_value alt_core_pll {gui_use_locked} {1}
-  set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency
-  add_connection alt_ref_clk.out_clk alt_core_pll.refclk
-  add_connection alt_sys_clk.clk_reset alt_core_pll.reset
-  add_interface core_pll_locked conduit end
-  set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked
+  if {$m_device_family eq "Arria V"} {
+
+    add_instance alt_core_pll altera_pll 16.0
+    set_instance_parameter_value alt_core_pll {gui_en_reconf} {1}
+    set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency
+    set_instance_parameter_value alt_core_pll {gui_use_locked} {1}
+    set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency
+    add_connection alt_ref_clk.out_clk alt_core_pll.refclk
+    add_connection alt_sys_clk.clk_reset alt_core_pll.reset
+    add_interface core_pll_locked conduit end
+    set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked
+
+  } else {
+
+    add_instance alt_core_pll altera_iopll 16.0
+    set_instance_parameter_value alt_core_pll {gui_en_reconf} {1}
+    set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency
+    set_instance_parameter_value alt_core_pll {gui_use_locked} {1}
+    set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency
+    add_connection alt_ref_clk.out_clk alt_core_pll.refclk
+    add_connection alt_sys_clk.clk_reset alt_core_pll.reset
+    add_interface core_pll_locked conduit end
+    set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked
+  }
 
   add_instance alt_core_pll_reconfig altera_pll_reconfig 16.0
   add_connection alt_sys_clk.clk_reset alt_core_pll_reconfig.mgmt_reset
@@ -257,10 +272,26 @@ proc p_avl_adxcvr {} {
       add_connection alt_xphy.tx_phy${n}_analogreset alt_phy_${n}.tx_analogreset
       add_connection alt_xphy.tx_phy${n}_digitalreset alt_phy_${n}.tx_digitalreset
       add_connection alt_lane_pll.tx_serial_clk alt_phy_${n}.tx_serial_clk0
-      add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk
-      add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset
-      add_interface phy_reconfig_${n} avalon slave
-      set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm
+
+      if {$m_device_family eq "Arria V"} {
+
+        add_instance alt_phy_reconfig_${n} alt_xcvr_reconfig 16.0
+        set_instance_parameter_value alt_phy_reconfig_${n} {number_of_reconfig_interfaces} {1}
+        add_connection alt_sys_clk.clk alt_phy_reconfig_${n}.mgmt_clk_clk
+        add_connection alt_sys_clk.clk_reset alt_phy_reconfig_${n}.mgmt_rst_reset
+        add_interface phy_reconfig_${n} avalon slave
+        set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_reconfig_${n}.reconfig_mgmt
+        add_connection alt_phy_reconfig_${n}.reconfig_to_xcvr alt_phy_${n}.reconfig_to_xcvr
+        add_connection alt_phy_${n}.reconfig_from_xcvr alt_phy_reconfig_${n}.reconfig_from_xcvr
+
+      } else {
+
+        add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk
+        add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset
+        add_interface phy_reconfig_${n} avalon slave
+        set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm
+      }
+
       add_connection alt_phy_${n}.tx_cal_busy alt_xphy.tx_phy${n}_cal_busy
       add_connection alt_phy_${n}.phy_csr_tx_pcfifo_full alt_xphy.tx_phy${n}_pcfifo_full
       add_connection alt_phy_${n}.phy_csr_tx_pcfifo_empty alt_xphy.tx_phy${n}_pcfifo_empty
@@ -355,10 +386,26 @@ proc p_avl_adxcvr {} {
       set_instance_parameter_value alt_phy_${n} {set_user_identifier} $m_id
       set_instance_parameter_value alt_phy_${n} {set_csr_soft_logic_enable} {1}
       set_instance_parameter_value alt_phy_${n} {L} 1
-      add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk
-      add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset
-      add_interface phy_reconfig_${n} avalon slave
-      set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm
+
+      if {$m_device_family eq "Arria V"} {
+
+        add_instance alt_phy_reconfig_${n} alt_xcvr_reconfig 16.0
+        set_instance_parameter_value alt_phy_reconfig_${n} {number_of_reconfig_interfaces} {1}
+        add_connection alt_sys_clk.clk alt_phy_reconfig_${n}.mgmt_clk_clk
+        add_connection alt_sys_clk.clk_reset alt_phy_reconfig_${n}.mgmt_rst_reset
+        add_interface phy_reconfig_${n} avalon slave
+        set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_reconfig_${n}.reconfig_mgmt
+        add_connection alt_phy_reconfig_${n}.reconfig_to_xcvr alt_phy_${n}.reconfig_to_xcvr
+        add_connection alt_phy_${n}.reconfig_from_xcvr alt_phy_reconfig_${n}.reconfig_from_xcvr
+
+      } else {
+
+        add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk
+        add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset
+        add_interface phy_reconfig_${n} avalon slave
+        set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm
+      }
+
       add_connection alt_ref_clk.out_clk alt_phy_${n}.pll_ref_clk
       add_connection alt_core_pll.outclk0 alt_phy_${n}.rxlink_clk
       add_connection alt_sys_clk.clk_reset alt_phy_${n}.rxlink_rst_n

From acb9bf39026ac7e72fc3562c83e6b40cdcd3896c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Nov 2016 15:02:57 -0400
Subject: [PATCH 667/972] hdlmake- a5soc/a5gt- updates

---
 projects/fmcjesdadc1/a5gt/Makefile  | 52 -----------------------------
 projects/fmcjesdadc1/a5soc/Makefile | 20 ++++++-----
 2 files changed, 11 insertions(+), 61 deletions(-)

diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index 9f80abb77..1d45efd24 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -16,61 +16,9 @@ M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += system_bd.qsys
 M_DEPS += ../common/fmcjesdadc1_spi.v
-M_DEPS += ../common/fmcjesdadc1_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
-M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
-M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
-M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
-M_DEPS += ../../../library/axi_ad9250/axi_ad9250_if.v
-M_DEPS += ../../../library/axi_ad9250/axi_ad9250_pnmon.v
-M_DEPS += ../../../library/axi_dmac/2d_transfer.v
-M_DEPS += ../../../library/axi_dmac/address_generator.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
-M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
-M_DEPS += ../../../library/axi_dmac/data_mover.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
-M_DEPS += ../../../library/axi_dmac/inc_id.h
-M_DEPS += ../../../library/axi_dmac/request_arb.v
-M_DEPS += ../../../library/axi_dmac/request_generator.v
-M_DEPS += ../../../library/axi_dmac/resp.h
-M_DEPS += ../../../library/axi_dmac/response_generator.v
-M_DEPS += ../../../library/axi_dmac/response_handler.v
-M_DEPS += ../../../library/axi_dmac/splitter.v
-M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
-M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_jesd_align.v
-M_DEPS += ../../../library/common/ad_pnmon.v
-M_DEPS += ../../../library/common/ad_rst.v
-M_DEPS += ../../../library/common/sync_bits.v
-M_DEPS += ../../../library/common/sync_gray.v
-M_DEPS += ../../../library/common/up_adc_channel.v
-M_DEPS += ../../../library/common/up_adc_common.v
-M_DEPS += ../../../library/common/up_axi.v
-M_DEPS += ../../../library/common/up_clock_mon.v
-M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_xcvr.v
-M_DEPS += ../../../library/common/up_xfer_cntrl.v
-M_DEPS += ../../../library/common/up_xfer_status.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
-M_DEPS += ../../../library/util_axis_fifo/address_sync.v
-M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
-M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
-M_DEPS += ../../../library/util_bsplit/util_bsplit.v
-M_DEPS += ../../../library/util_bsplit/util_bsplit_hw.tcl
-M_DEPS += ../../../library/util_cpack/util_cpack.v
-M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
-M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
-M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 99701e708..0e8d4771c 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -12,14 +12,18 @@ endif
 export ALT_NIOS_MMU_ENABLED := $(MMU)
 
 M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
-M_DEPS += system_bd.qsys
 M_DEPS += ../common/fmcjesdadc1_spi.v
-M_DEPS += ../common/fmcjesdadc1_bd.qsys
+M_DEPS += ../common/fmcjesdadc1_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/a5soc/a5soc_system_bd.qsys
+M_DEPS += ../../common/a5soc/a5soc_system_qsys.tcl
 M_DEPS += ../../common/a5soc/a5soc_system_assign.tcl
+M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
@@ -44,10 +48,9 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
-M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/sync_bits.v
@@ -57,16 +60,15 @@ M_DEPS += ../../../library/common/up_adc_common.v
 M_DEPS += ../../../library/common/up_axi.v
 M_DEPS += ../../../library/common/up_clock_mon.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
-M_DEPS += ../../../library/common/up_xcvr.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
 M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
 M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
-M_DEPS += ../../../library/util_bsplit/util_bsplit.v
-M_DEPS += ../../../library/util_bsplit/util_bsplit_hw.tcl
 M_DEPS += ../../../library/util_cpack/util_cpack.v
 M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
 M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

From d7357d781ba34744a8f093f3ef0a9f418d090817 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 4 Nov 2016 15:30:39 -0400
Subject: [PATCH 668/972] axi_ad9250 - avalon/axi streaming + sof

---
 library/axi_ad9250/axi_ad9250.v      | 16 +++++++++----
 library/axi_ad9250/axi_ad9250_hw.tcl | 36 ++++++++++++++++++----------
 library/axi_ad9250/axi_ad9250_if.v   | 32 +++++++++++++++++++------
 3 files changed, 61 insertions(+), 23 deletions(-)

diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v
index cd63f98b6..0367c7722 100644
--- a/library/axi_ad9250/axi_ad9250.v
+++ b/library/axi_ad9250/axi_ad9250.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -45,7 +43,10 @@ module axi_ad9250 (
   // rx_clk is (line-rate/40)
 
   rx_clk,
+  rx_sof,
+  rx_valid,
   rx_data,
+  rx_ready,
 
   // dma interface
 
@@ -86,13 +87,15 @@ module axi_ad9250 (
 
   parameter ID = 0;
   parameter DEVICE_TYPE = 0;
-  parameter IO_DELAY_GROUP = "adc_if_delay_group";
 
   // jesd interface 
   // rx_clk is (line-rate/40)
 
   input           rx_clk;
+  input  [  3:0]  rx_sof;
+  input           rx_valid;
   input   [63:0]  rx_data;
+  output          rx_ready;
 
   // dma interface
 
@@ -170,6 +173,10 @@ module axi_ad9250 (
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
 
+  // defaults
+
+  assign rx_ready = 1'b1;
+
   // processor read interface
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -197,8 +204,9 @@ module axi_ad9250 (
 
   // main (device interface)
 
-  axi_ad9250_if i_if (
+  axi_ad9250_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
     .rx_clk (rx_clk),
+    .rx_sof (rx_sof),
     .rx_data (rx_data),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl
index 6cbfe65f2..66ae542d7 100755
--- a/library/axi_ad9250/axi_ad9250_hw.tcl
+++ b/library/axi_ad9250/axi_ad9250_hw.tcl
@@ -24,6 +24,7 @@ add_fileset_file up_clock_mon.v       VERILOG PATH $ad_hdl_dir/library/common/up
 add_fileset_file up_delay_cntrl.v     VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
 add_fileset_file up_adc_common.v      VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
 add_fileset_file up_adc_channel.v     VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
+add_fileset_file ad_xcvr_rx_if.v      VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
 add_fileset_file axi_ad9250_pnmon.v   VERILOG PATH axi_ad9250_pnmon.v
 add_fileset_file axi_ad9250_if.v      VERILOG PATH axi_ad9250_if.v
 add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v
@@ -40,7 +41,7 @@ set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
 add_parameter DEVICE_TYPE INTEGER 0
-set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
 set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
 set_parameter_property DEVICE_TYPE TYPE INTEGER
 set_parameter_property DEVICE_TYPE UNITS None
@@ -81,24 +82,35 @@ add_interface_port s_axi s_axi_rready rready Input 1
 # transceiver interface
 
 ad_alt_intf clock   rx_clk        input   1
-ad_alt_intf signal  rx_data       input   64    data
+ad_alt_intf signal  rx_sof        input   4 export
+
+add_interface if_rx_data avalon_streaming sink
+add_interface_port if_rx_data rx_data  data  input 64
+add_interface_port if_rx_data rx_valid valid input 1
+add_interface_port if_rx_data rx_ready ready output 1
+set_interface_property if_rx_data associatedClock if_rx_clk
+set_interface_property if_rx_data dataBitsPerSymbol 64
 
 # dma interface
 
 ad_alt_intf clock   adc_clk     output  1
 ad_alt_intf reset   adc_rst     output  1 if_adc_clk
 
-add_interface fifo_ch_0_in conduit end
-#set_interface_property fifo_ch_0_in associatedClock if_adc_clk
-add_interface_port fifo_ch_0_in  adc_enable_a enable   Output  1
-add_interface_port fifo_ch_0_in  adc_valid_a  valid    Output  1
-add_interface_port fifo_ch_0_in  adc_data_a   data     Output  32
+add_interface adc_ch_0 conduit end
+add_interface_port adc_ch_0  adc_enable_a enable   Output  1
+add_interface_port adc_ch_0  adc_valid_a  valid    Output  1
+add_interface_port adc_ch_0  adc_data_a   data     Output  32
 
-add_interface fifo_ch_1_in conduit end
-#set_interface_property fifo_ch_1_in associatedClock if_adc_clk
-add_interface_port fifo_ch_1_in  adc_enable_b enable   Output  1
-add_interface_port fifo_ch_1_in  adc_valid_b  valid    Output  1
-add_interface_port fifo_ch_1_in  adc_data_b   data     Output  32
+set_interface_property adc_ch_0 associatedClock if_rx_clk
+set_interface_property adc_ch_0 associatedReset none
+
+add_interface adc_ch_1 conduit end
+add_interface_port adc_ch_1  adc_enable_b enable   Output  1
+add_interface_port adc_ch_1  adc_valid_b  valid    Output  1
+add_interface_port adc_ch_1  adc_data_b   data     Output  32
+
+set_interface_property adc_ch_1 associatedClock if_rx_clk
+set_interface_property adc_ch_1 associatedReset none
 
 ad_alt_intf signal  adc_dovf      input   1     ovf
 ad_alt_intf signal  adc_dunf      input   1     unf
diff --git a/library/axi_ad9250/axi_ad9250_if.v b/library/axi_ad9250/axi_ad9250_if.v
index b3274c275..ad8f71d08 100644
--- a/library/axi_ad9250/axi_ad9250_if.v
+++ b/library/axi_ad9250/axi_ad9250_if.v
@@ -34,9 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// This is the LVDS/DDR interface
 
 `timescale 1ns/100ps
 
@@ -46,6 +43,7 @@ module axi_ad9250_if (
   // rx_clk is (line-rate/40)
 
   rx_clk,
+  rx_sof,
   rx_data,
 
   // adc data output
@@ -58,10 +56,15 @@ module axi_ad9250_if (
   adc_or_b,
   adc_status);
 
+  // parameters
+
+  parameter DEVICE_TYPE = 0;
+
   // jesd interface 
   // rx_clk is (line-rate/40)
 
   input           rx_clk;
+  input  [  3:0]  rx_sof;
   input   [63:0]  rx_data;
 
   // adc data output
@@ -98,10 +101,10 @@ module axi_ad9250_if (
 
   // data multiplex
 
-  assign adc_data_a_s1_s = {rx_data[25:24], rx_data[23:16], rx_data[31:26]}; 
-  assign adc_data_a_s0_s = {rx_data[ 9: 8], rx_data[ 7: 0], rx_data[15:10]};
-  assign adc_data_b_s1_s = {rx_data[57:56], rx_data[55:48], rx_data[63:58]}; 
-  assign adc_data_b_s0_s = {rx_data[41:40], rx_data[39:32], rx_data[47:42]};
+  assign adc_data_a_s1_s = {rx_data_s[25:24], rx_data_s[23:16], rx_data_s[31:26]}; 
+  assign adc_data_a_s0_s = {rx_data_s[ 9: 8], rx_data_s[ 7: 0], rx_data_s[15:10]};
+  assign adc_data_b_s1_s = {rx_data_s[57:56], rx_data_s[55:48], rx_data_s[63:58]}; 
+  assign adc_data_b_s0_s = {rx_data_s[41:40], rx_data_s[39:32], rx_data_s[47:42]};
 
   // status
 
@@ -113,6 +116,21 @@ module axi_ad9250_if (
     end
   end
 
+  // frame-alignment
+
+  genvar n;
+
+  generate
+  for (n = 0; n < 4; n = n + 1) begin: g_xcvr_if
+  ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
+    .rx_clk (rx_clk),
+    .rx_ip_sof (rx_sof),
+    .rx_ip_data (rx_data[((n*32)+31):(n*32)]),
+    .rx_sof (),
+    .rx_data (rx_data_s[((n*32)+31):(n*32)]));
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************

From a58597c13a9aefe6c8f1d6e1341f68a072b67d06 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 8 Nov 2016 15:17:54 -0500
Subject: [PATCH 669/972] ad9250 - build fixes

---
 library/axi_ad9250/axi_ad9250_if.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/library/axi_ad9250/axi_ad9250_if.v b/library/axi_ad9250/axi_ad9250_if.v
index ad8f71d08..0b8e603ff 100644
--- a/library/axi_ad9250/axi_ad9250_if.v
+++ b/library/axi_ad9250/axi_ad9250_if.v
@@ -87,6 +87,7 @@ module axi_ad9250_if (
   wire    [15:0]  adc_data_a_s0_s;
   wire    [15:0]  adc_data_b_s1_s;
   wire    [15:0]  adc_data_b_s0_s;
+  wire    [63:0]  rx_data_s;
 
   // adc clock is the reference clock
 
@@ -121,7 +122,7 @@ module axi_ad9250_if (
   genvar n;
 
   generate
-  for (n = 0; n < 4; n = n + 1) begin: g_xcvr_if
+  for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
   ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
     .rx_clk (rx_clk),
     .rx_ip_sof (rx_sof),

From d9cfccc05f74fc896fe60055e62e8bdbad8e1265 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 8 Nov 2016 15:19:02 -0500
Subject: [PATCH 670/972] common/a5soc- gpio in/out separation

---
 projects/common/a5soc/a5soc_system_assign.tcl | 57 +++++++++++--------
 1 file changed, 33 insertions(+), 24 deletions(-)

diff --git a/projects/common/a5soc/a5soc_system_assign.tcl b/projects/common/a5soc/a5soc_system_assign.tcl
index f7d916fe3..2491a667b 100755
--- a/projects/common/a5soc/a5soc_system_assign.tcl
+++ b/projects/common/a5soc/a5soc_system_assign.tcl
@@ -4,33 +4,42 @@
 set_global_assignment -name FAMILY "Arria V"
 set_global_assignment -name DEVICE 5ASTFD5K3F40I3ES
 
+# i2c (fmc)
+
+set_location_assignment PIN_F26 -to fmca_scl
+set_location_assignment PIN_G26 -to fmca_sda
+set_instance_assignment -name IO_STANDARD "2.5 V" -to fmca_scl
+set_instance_assignment -name IO_STANDARD "2.5 V" -to fmca_sda
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fmca_scl
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fmca_sda
+
 # led & switches
 
-set_location_assignment PIN_AH24  -to gpio_bd[0]    ; ## led[0]
-set_location_assignment PIN_AU24  -to gpio_bd[1]    ; ## led[1]
-set_location_assignment PIN_AT24  -to gpio_bd[2]    ; ## led[2]
-set_location_assignment PIN_AD24  -to gpio_bd[3]    ; ## led[3]
-set_location_assignment PIN_AT23  -to gpio_bd[4]    ; ## push_buttons[0]
-set_location_assignment PIN_AP24  -to gpio_bd[5]    ; ## push_buttons[1]
-set_location_assignment PIN_AW24  -to gpio_bd[6]    ; ## push_buttons[2]
-set_location_assignment PIN_AW23  -to gpio_bd[7]    ; ## push_buttons[3]
-set_location_assignment PIN_AL24  -to gpio_bd[8]    ; ## dip_switches[0]
-set_location_assignment PIN_AF24  -to gpio_bd[9]    ; ## dip_switches[1]
-set_location_assignment PIN_AE24  -to gpio_bd[10]   ; ## dip_switches[2]
-set_location_assignment PIN_AU23  -to gpio_bd[11]   ; ## dip_switches[3]
+set_location_assignment PIN_AH24  -to gpio_bd_o[0]   ; ## led[0]
+set_location_assignment PIN_AU24  -to gpio_bd_o[1]   ; ## led[1]
+set_location_assignment PIN_AT24  -to gpio_bd_o[2]   ; ## led[2]
+set_location_assignment PIN_AD24  -to gpio_bd_o[3]   ; ## led[3]
+set_location_assignment PIN_AT23  -to gpio_bd_i[0]   ; ## push_buttons[0]
+set_location_assignment PIN_AP24  -to gpio_bd_i[1]   ; ## push_buttons[1]
+set_location_assignment PIN_AW24  -to gpio_bd_i[2]   ; ## push_buttons[2]
+set_location_assignment PIN_AW23  -to gpio_bd_i[3]   ; ## push_buttons[3]
+set_location_assignment PIN_AL24  -to gpio_bd_i[4]   ; ## dip_switches[0]
+set_location_assignment PIN_AF24  -to gpio_bd_i[5]   ; ## dip_switches[1]
+set_location_assignment PIN_AE24  -to gpio_bd_i[6]   ; ## dip_switches[2]
+set_location_assignment PIN_AU23  -to gpio_bd_i[7]   ; ## dip_switches[3]
 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[0] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[1] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[2] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[3] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[4] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[5] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[6] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[7] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[8] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[9] 
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[10]
-set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[11]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[0] 
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[1] 
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[2] 
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[3] 
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[0]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[1]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[2]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[3]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[4]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[5]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[6]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[7]
 
 # uart
 

From f0af8216ce808ccca30d1ccebd94783e1ff461e1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 8 Nov 2016 15:19:23 -0500
Subject: [PATCH 671/972] common/a5soc- device can not run at 100M cpu clock

---
 projects/common/a5soc/a5soc_system_qsys.tcl | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/projects/common/a5soc/a5soc_system_qsys.tcl b/projects/common/a5soc/a5soc_system_qsys.tcl
index f25bbd34d..5699a3a26 100644
--- a/projects/common/a5soc/a5soc_system_qsys.tcl
+++ b/projects/common/a5soc/a5soc_system_qsys.tcl
@@ -50,10 +50,11 @@ set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
 set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
 set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
 set_instance_parameter_value sys_hps {use_default_mpu_clk} {0}
+set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {50.0}
 set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
-set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {1}
 set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_Enable} {0}
-set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {150.0}
+set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
 set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
 set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
 set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
@@ -88,8 +89,10 @@ set_instance_parameter_value sys_hps {MEM_TFAW_NS} {35.0}
 set_instance_parameter_value sys_hps {MEM_TRRD_NS} {6.0}
 set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
 
-add_interface sys_hps_clk clock source
-set_interface_property sys_hps_clk EXPORT_OF sys_hps.h2f_user0_clock
+add_interface sys_hps_cpu_clk clock source
+set_interface_property sys_hps_cpu_clk EXPORT_OF sys_hps.h2f_user0_clock
+add_interface sys_hps_dma_clk clock source
+set_interface_property sys_hps_dma_clk EXPORT_OF sys_hps.h2f_user1_clock
 add_interface sys_hps_spim0 conduit end
 set_interface_property sys_hps_spim0 EXPORT_OF sys_hps.spim0
 add_interface sys_hps_spim0_sclk clock source

From 48ee72090108395e1172e1885e131e51ea6153aa Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 8 Nov 2016 15:20:01 -0500
Subject: [PATCH 672/972] avl_adxcvr- a5 requires single transceiver controller

---
 library/altera/avl_adxcvr/avl_adxcvr_hw.tcl | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
index 382d3845f..0d8b53ad1 100755
--- a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
@@ -389,14 +389,10 @@ proc p_avl_adxcvr {} {
 
       if {$m_device_family eq "Arria V"} {
 
-        add_instance alt_phy_reconfig_${n} alt_xcvr_reconfig 16.0
-        set_instance_parameter_value alt_phy_reconfig_${n} {number_of_reconfig_interfaces} {1}
-        add_connection alt_sys_clk.clk alt_phy_reconfig_${n}.mgmt_clk_clk
-        add_connection alt_sys_clk.clk_reset alt_phy_reconfig_${n}.mgmt_rst_reset
-        add_interface phy_reconfig_${n} avalon slave
-        set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_reconfig_${n}.reconfig_mgmt
-        add_connection alt_phy_reconfig_${n}.reconfig_to_xcvr alt_phy_${n}.reconfig_to_xcvr
-        add_connection alt_phy_${n}.reconfig_from_xcvr alt_phy_reconfig_${n}.reconfig_from_xcvr
+        add_interface phy_reconfig_to_xcvr_${n} conduit end
+        set_interface_property phy_reconfig_to_xcvr_${n} EXPORT_OF alt_phy_${n}.reconfig_to_xcvr
+        add_interface phy_reconfig_from_xcvr_${n} conduit end
+        set_interface_property phy_reconfig_from_xcvr_${n} EXPORT_OF alt_phy_${n}.reconfig_from_xcvr
 
       } else {
 

From 53c2f0642b22faa9640b0a2bb5f8065971943c1e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 8 Nov 2016 15:20:33 -0500
Subject: [PATCH 673/972] fmcjesdadc1/a5soc -- xcvr frame work updates

---
 projects/fmcjesdadc1/a5soc/system_constr.sdc  |  16 +-
 projects/fmcjesdadc1/a5soc/system_project.tcl |   1 -
 projects/fmcjesdadc1/a5soc/system_top.v       | 430 ++++++++----------
 3 files changed, 213 insertions(+), 234 deletions(-)

diff --git a/projects/fmcjesdadc1/a5soc/system_constr.sdc b/projects/fmcjesdadc1/a5soc/system_constr.sdc
index e01240f42..cc0a871d7 100644
--- a/projects/fmcjesdadc1/a5soc/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5soc/system_constr.sdc
@@ -1,8 +1,22 @@
 
-create_clock -period  "4.000 ns" -name clk_250m [get_ports {ref_clk}]
+create_clock -period  "4.000 ns" -name ref_clk [get_ports {ref_clk}]
+create_clock -period "20.000 ns" -name sys_cpu_clk [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
+create_clock -period "10.000 ns" -name sys_dma_clk [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user1_clk}]
 
 derive_pll_clocks
 derive_clock_uncertainty
 
+set_false_path -to [get_registers {rx_sysref_m1}]
 
+set_false_path -from [get_clocks {sys_cpu_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\
+  -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
+
+set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
+  -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_cpu_clk}]
+
+set_false_path -from [get_clocks {sys_cpu_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
+
+set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_cpu_clk}]
 
diff --git a/projects/fmcjesdadc1/a5soc/system_project.tcl b/projects/fmcjesdadc1/a5soc/system_project.tcl
index 5fe987c65..e0e780765 100755
--- a/projects/fmcjesdadc1/a5soc/system_project.tcl
+++ b/projects/fmcjesdadc1/a5soc/system_project.tcl
@@ -62,7 +62,6 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
 
 set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
 set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
-set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xcvr
 
 execute_flow -compile
 
diff --git a/projects/fmcjesdadc1/a5soc/system_top.v b/projects/fmcjesdadc1/a5soc/system_top.v
index 161b9c694..b409dc062 100644
--- a/projects/fmcjesdadc1/a5soc/system_top.v
+++ b/projects/fmcjesdadc1/a5soc/system_top.v
@@ -41,179 +41,128 @@ module system_top (
 
   // hps
 
-  ddr3_a,
-  ddr3_ba,
-  ddr3_ck_p,
-  ddr3_ck_n,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_ras_n,
-  ddr3_cas_n,
-  ddr3_we_n,
-  ddr3_reset_n,
-  ddr3_dq,
-  ddr3_dqs_p,
-  ddr3_dqs_n,
-  ddr3_odt,
-  ddr3_dm,
-  ddr3_oct_rzqin,
-  eth1_tx_clk,
-  eth1_tx_ctl,
-  eth1_txd0,
-  eth1_txd1,
-  eth1_txd2,
-  eth1_txd3,
-  eth1_rx_clk,
-  eth1_rx_ctl,
-  eth1_rxd0,
-  eth1_rxd1,
-  eth1_rxd2,
-  eth1_rxd3,
-  eth1_mdc,
-  eth1_mdio,
-  qspi_ss0,
-  qspi_clk,
-  qspi_io0,
-  qspi_io1,
-  qspi_io2,
-  qspi_io3,
-  sdio_clk,
-  sdio_cmd,
-  sdio_d0,
-  sdio_d1,
-  sdio_d2,
-  sdio_d3,
-  usb1_clk,
-  usb1_stp,
-  usb1_dir,
-  usb1_nxt,
-  usb1_d0,
-  usb1_d1,
-  usb1_d2,
-  usb1_d3,
-  usb1_d4,
-  usb1_d5,
-  usb1_d6,
-  usb1_d7,
-  uart0_rx,
-  uart0_tx,
+  output  [ 14:0]   ddr3_a,
+  output  [  2:0]   ddr3_ba,
+  output            ddr3_ck_p,
+  output            ddr3_ck_n,
+  output            ddr3_cke,
+  output            ddr3_cs_n,
+  output            ddr3_ras_n,
+  output            ddr3_cas_n,
+  output            ddr3_we_n,
+  output            ddr3_reset_n,
+  inout   [ 39:0]   ddr3_dq,
+  inout   [  4:0]   ddr3_dqs_p,
+  inout   [  4:0]   ddr3_dqs_n,
+  output            ddr3_odt,
+  output  [  4:0]   ddr3_dm,
+  input             ddr3_oct_rzqin,
+  output            eth1_tx_clk,
+  output            eth1_tx_ctl,
+  output            eth1_txd0,
+  output            eth1_txd1,
+  output            eth1_txd2,
+  output            eth1_txd3,
+  input             eth1_rx_clk,
+  input             eth1_rx_ctl,
+  input             eth1_rxd0,
+  input             eth1_rxd1,
+  input             eth1_rxd2,
+  input             eth1_rxd3,
+  output            eth1_mdc,
+  inout             eth1_mdio,
+  output            qspi_ss0,
+  output            qspi_clk,
+  inout             qspi_io0,
+  inout             qspi_io1,
+  inout             qspi_io2,
+  inout             qspi_io3,
+  output            sdio_clk,
+  inout             sdio_cmd,
+  inout             sdio_d0,
+  inout             sdio_d1,
+  inout             sdio_d2,
+  inout             sdio_d3,
+  input             usb1_clk,
+  output            usb1_stp,
+  input             usb1_dir,
+  input             usb1_nxt,
+  inout             usb1_d0,
+  inout             usb1_d1,
+  inout             usb1_d2,
+  inout             usb1_d3,
+  inout             usb1_d4,
+  inout             usb1_d5,
+  inout             usb1_d6,
+  inout             usb1_d7,
+  input             uart0_rx,
+  output            uart0_tx,
 
   // board gpio
 
-  gpio_bd,
+  output  [  3:0]   gpio_bd_o,
+  input   [  7:0]   gpio_bd_i,
 
   // i2c
 
-  fmc_a_scl,
-  fmc_a_sda,
+  inout             fmca_scl,
+  inout             fmca_sda,
 
   // lane interface
 
-  ref_clk,
-  rx_data,
-  rx_sync,
-  rx_sysref,
+  input             ref_clk,
+  input   [  3:0]   rx_data,
+  output            rx_sync,
+  output            rx_sysref,
 
   // spi
 
-  spi_csn,
-  spi_clk,
-  spi_sdio);
+  output            spi_csn,
+  output            spi_clk,
+  inout             spi_sdio);
 
-  // hps
+  // internal registers
 
-  output  [ 14:0]   ddr3_a;
-  output  [  2:0]   ddr3_ba;
-  output            ddr3_ck_p;
-  output            ddr3_ck_n;
-  output            ddr3_cke;
-  output            ddr3_cs_n;
-  output            ddr3_ras_n;
-  output            ddr3_cas_n;
-  output            ddr3_we_n;
-  output            ddr3_reset_n;
-  inout   [ 39:0]   ddr3_dq;
-  inout   [  4:0]   ddr3_dqs_p;
-  inout   [  4:0]   ddr3_dqs_n;
-  output            ddr3_odt;
-  output  [  4:0]   ddr3_dm;
-  input             ddr3_oct_rzqin;
-  output            eth1_tx_clk;
-  output            eth1_tx_ctl;
-  output            eth1_txd0;
-  output            eth1_txd1;
-  output            eth1_txd2;
-  output            eth1_txd3;
-  input             eth1_rx_clk;
-  input             eth1_rx_ctl;
-  input             eth1_rxd0;
-  input             eth1_rxd1;
-  input             eth1_rxd2;
-  input             eth1_rxd3;
-  output            eth1_mdc;
-  inout             eth1_mdio;
-  output            qspi_ss0;
-  output            qspi_clk;
-  inout             qspi_io0;
-  inout             qspi_io1;
-  inout             qspi_io2;
-  inout             qspi_io3;
-  output            sdio_clk;
-  inout             sdio_cmd;
-  inout             sdio_d0;
-  inout             sdio_d1;
-  inout             sdio_d2;
-  inout             sdio_d3;
-  input             usb1_clk;
-  output            usb1_stp;
-  input             usb1_dir;
-  input             usb1_nxt;
-  inout             usb1_d0;
-  inout             usb1_d1;
-  inout             usb1_d2;
-  inout             usb1_d3;
-  inout             usb1_d4;
-  inout             usb1_d5;
-  inout             usb1_d6;
-  inout             usb1_d7;
-  input             uart0_rx;
-  output            uart0_tx;
-
-  // board gpio
-
-  inout   [ 11:0]   gpio_bd;
-
-  // i2c
-
-  inout             fmc_a_scl;
-  inout             fmc_a_sda;
-
-  // lane interface
-
-  input             ref_clk;
-  input   [  3:0]   rx_data;
-  output            rx_sync;
-  output            rx_sysref;
-
-  // spi
-
-  output            spi_csn;
-  output            spi_clk;
-  inout             spi_sdio;
+  reg               rx_sysref_m1 = 'd0;
+  reg               rx_sysref_m2 = 'd0;
+  reg               rx_sysref_int = 'd0;
 
   // internal signals
 
+  wire              sys_cpu_clk;
+  wire              sys_dma_clk;
+  wire              sys_rstn;
+  wire              rx_clk;
+  wire    [  3:0]   rx_ip_sof;
+  wire    [127:0]   rx_ip_data;
   wire    [ 63:0]   gpio_i;
   wire    [ 63:0]   gpio_o;
   wire              spi_mosi;
   wire              spi_miso;
-  wire              fmc_a_scl_oe;
-  wire              fmc_a_sda_oe;
+  wire              fmca_scl_oe;
+  wire              fmca_sda_oe;
 
   // i2c
 
-  assign fmc_a_scl = (fmc_a_scl_oe == 1'b1) ? 1'b0 : 1'bz;
-  assign fmc_a_sda = (fmc_a_sda_oe == 1'b1) ? 1'b0 : 1'bz;
+  assign fmca_scl = (fmca_scl_oe == 1'b1) ? 1'b0 : 1'bz;
+  assign fmca_sda = (fmca_sda_oe == 1'b1) ? 1'b0 : 1'bz;
+
+  // gpio
+
+  assign gpio_i[63: 8] = gpio_o[63:8];
+  assign gpio_i[ 7: 0] = gpio_bd_i;
+
+  assign gpio_bd_o = gpio_o[11:8];
+
+  // sysref
+
+  assign rx_sysref = rx_sysref_int;
+
+  always @(posedge rx_clk) begin
+    rx_sysref_m1 <= gpio_o[12];
+    rx_sysref_m2 <= rx_sysref_m1;
+    rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
+  end
 
   // instantiations
 
@@ -224,90 +173,107 @@ module system_top (
     .spi_miso (spi_miso),
     .spi_sdio (spi_sdio));
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
-    .dio_t ({8'hff, 4'h0}),
-    .dio_i (gpio_o[11:0]),
-    .dio_o (gpio_i[11:0]),
-    .dio_p (gpio_bd));
-
   system_bd i_system_bd (
-    .a5soc_base_sys_gpio_bd_external_connection_in_port (gpio_i[63:32]),
-    .a5soc_base_sys_gpio_bd_external_connection_out_port (gpio_o[63:32]),
-    .a5soc_base_sys_gpio_external_connection_in_port (gpio_i[31:0]),
-    .a5soc_base_sys_gpio_external_connection_out_port (gpio_o[31:0]),
-    .a5soc_base_sys_hps_i2c0_out_data (fmc_a_sda_oe),
-    .a5soc_base_sys_hps_i2c0_sda (fmc_a_sda),
-    .a5soc_base_sys_hps_i2c0_clk_clk (fmc_a_scl_oe),
-    .a5soc_base_sys_hps_i2c0_scl_in_clk (fmc_a_scl),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
-    .a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
-    .a5soc_base_sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
-    .a5soc_base_sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
-    .a5soc_base_sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
-    .a5soc_base_sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
-    .a5soc_base_sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
-    .a5soc_base_sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
-    .a5soc_base_sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
-    .a5soc_base_sys_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
-    .a5soc_base_sys_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
-    .a5soc_base_sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
-    .a5soc_base_sys_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
-    .a5soc_base_sys_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_STP (usb1_stp),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
-    .a5soc_base_sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
-    .a5soc_base_sys_hps_io_hps_io_uart0_inst_RX (uart0_rx),
-    .a5soc_base_sys_hps_io_hps_io_uart0_inst_TX (uart0_tx),
-    .a5soc_base_sys_hps_memory_mem_a (ddr3_a),
-    .a5soc_base_sys_hps_memory_mem_ba (ddr3_ba),
-    .a5soc_base_sys_hps_memory_mem_ck (ddr3_ck_p),
-    .a5soc_base_sys_hps_memory_mem_ck_n (ddr3_ck_n),
-    .a5soc_base_sys_hps_memory_mem_cke (ddr3_cke),
-    .a5soc_base_sys_hps_memory_mem_cs_n (ddr3_cs_n),
-    .a5soc_base_sys_hps_memory_mem_ras_n (ddr3_ras_n),
-    .a5soc_base_sys_hps_memory_mem_cas_n (ddr3_cas_n),
-    .a5soc_base_sys_hps_memory_mem_we_n (ddr3_we_n),
-    .a5soc_base_sys_hps_memory_mem_reset_n (ddr3_reset_n),
-    .a5soc_base_sys_hps_memory_mem_dq (ddr3_dq),
-    .a5soc_base_sys_hps_memory_mem_dqs (ddr3_dqs_p),
-    .a5soc_base_sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
-    .a5soc_base_sys_hps_memory_mem_odt (ddr3_odt),
-    .a5soc_base_sys_hps_memory_mem_dm (ddr3_dm),
-    .a5soc_base_sys_hps_memory_oct_rzqin (ddr3_oct_rzqin),
-    .a5soc_base_sys_hps_spim0_txd (spi_mosi),
-    .a5soc_base_sys_hps_spim0_rxd (spi_miso),
-    .a5soc_base_sys_hps_spim0_ss_in_n (1'b1),
-    .a5soc_base_sys_hps_spim0_ssi_oe_n (spi_csn),
-    .a5soc_base_sys_hps_spim0_ss_0_n (),
-    .a5soc_base_sys_hps_spim0_ss_1_n (),
-    .a5soc_base_sys_hps_spim0_ss_2_n (),
-    .a5soc_base_sys_hps_spim0_ss_3_n (),
-    .a5soc_base_sys_hps_spim0_sclk_out_clk (spi_clk),
-    .fmcjesdadc1_rx_data_rx_serial_data (rx_data),
-    .fmcjesdadc1_rx_ref_clk_clk (ref_clk),
-    .fmcjesdadc1_rx_sync_rx_sync (rx_sync),
-    .fmcjesdadc1_rx_sysref_rx_ext_sysref_out (rx_sysref));
+    .rx_core_clk_clk (rx_clk),
+    .rx_data_0_rx_serial_data (rx_data[0]),
+    .rx_data_1_rx_serial_data (rx_data[1]),
+    .rx_data_2_rx_serial_data (rx_data[2]),
+    .rx_data_3_rx_serial_data (rx_data[3]),
+    .rx_ip_data_data (rx_ip_data),
+    .rx_ip_data_valid (),
+    .rx_ip_data_ready (1'b1),
+    .rx_ip_data_0_data (rx_ip_data[63:0]),
+    .rx_ip_data_0_valid (1'b1),
+    .rx_ip_data_0_ready (),
+    .rx_ip_data_1_data (rx_ip_data[127:64]),
+    .rx_ip_data_1_valid (1'b1),
+    .rx_ip_data_1_ready (),
+    .rx_ip_sof_export (rx_ip_sof),
+    .rx_ip_sof_0_export (rx_ip_sof),
+    .rx_ip_sof_1_export (rx_ip_sof),
+    .rx_ref_clk_clk (ref_clk),
+    .rx_sync_export (rx_sync),
+    .rx_sysref_export (rx_sysref_int),
+    .sys_clk_clk (sys_cpu_clk),
+    .sys_dma_clk_clk (sys_dma_clk),
+    .sys_dma_rst_reset_n (sys_rstn),
+    .sys_gpio_bd_in_port (gpio_i[31:0]),
+    .sys_gpio_bd_out_port (gpio_o[31:0]),
+    .sys_gpio_in_export (gpio_i[63:32]),
+    .sys_gpio_out_export (gpio_o[63:32]),
+    .sys_hps_cpu_clk_clk (sys_cpu_clk),
+    .sys_hps_ddr3_mem_a (ddr3_a),
+    .sys_hps_ddr3_mem_ba (ddr3_ba),
+    .sys_hps_ddr3_mem_ck (ddr3_ck_p),
+    .sys_hps_ddr3_mem_ck_n (ddr3_ck_n),
+    .sys_hps_ddr3_mem_cke (ddr3_cke),
+    .sys_hps_ddr3_mem_cs_n (ddr3_cs_n),
+    .sys_hps_ddr3_mem_ras_n (ddr3_ras_n),
+    .sys_hps_ddr3_mem_cas_n (ddr3_cas_n),
+    .sys_hps_ddr3_mem_we_n (ddr3_we_n),
+    .sys_hps_ddr3_mem_reset_n (ddr3_reset_n),
+    .sys_hps_ddr3_mem_dq (ddr3_dq),
+    .sys_hps_ddr3_mem_dqs (ddr3_dqs_p),
+    .sys_hps_ddr3_mem_dqs_n (ddr3_dqs_n),
+    .sys_hps_ddr3_mem_odt (ddr3_odt),
+    .sys_hps_ddr3_mem_dm (ddr3_dm),
+    .sys_hps_ddr3_oct_rzqin (ddr3_oct_rzqin),
+    .sys_hps_dma_clk_clk (sys_dma_clk),
+    .sys_hps_i2c0_out_data (fmca_sda_oe),
+    .sys_hps_i2c0_sda (fmca_sda),
+    .sys_hps_i2c0_clk_clk (fmca_scl_oe),
+    .sys_hps_i2c0_scl_clk (fmca_scl),
+    .sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
+    .sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
+    .sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
+    .sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
+    .sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
+    .sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
+    .sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
+    .sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
+    .sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
+    .sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
+    .sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
+    .sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
+    .sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
+    .sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
+    .sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
+    .sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
+    .sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
+    .sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
+    .sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
+    .sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
+    .sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
+    .sys_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
+    .sys_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
+    .sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
+    .sys_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
+    .sys_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
+    .sys_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
+    .sys_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
+    .sys_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
+    .sys_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
+    .sys_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
+    .sys_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
+    .sys_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
+    .sys_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
+    .sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
+    .sys_hps_io_hps_io_usb1_inst_STP (usb1_stp),
+    .sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
+    .sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
+    .sys_hps_io_hps_io_uart0_inst_RX (uart0_rx),
+    .sys_hps_io_hps_io_uart0_inst_TX (uart0_tx),
+    .sys_hps_rstn_reset_n (sys_rstn),
+    .sys_hps_spim0_txd (spi_mosi),
+    .sys_hps_spim0_rxd (spi_miso),
+    .sys_hps_spim0_ss_in_n (1'b1),
+    .sys_hps_spim0_ssi_oe_n (spi_csn),
+    .sys_hps_spim0_ss_0_n (),
+    .sys_hps_spim0_ss_1_n (),
+    .sys_hps_spim0_ss_2_n (),
+    .sys_hps_spim0_ss_3_n (),
+    .sys_hps_spim0_sclk_clk (spi_clk),
+    .sys_rst_reset_n (sys_rstn));
 
 endmodule
 

From aef3e87d7e462088b6c88fe7facc304b54e2fd7e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 8 Nov 2016 15:20:48 -0500
Subject: [PATCH 674/972] fmcjesdadc1/a5soc -- xcvr frame work updates

---
 .../fmcjesdadc1/common/fmcjesdadc1_qsys.tcl   | 44 +++++++++++++++----
 1 file changed, 36 insertions(+), 8 deletions(-)

diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
index 4b8962212..14f2ab91e 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
@@ -32,6 +32,10 @@ add_interface rx_sysref conduit end
 set_interface_property rx_sysref EXPORT_OF avl_ad9250_xcvr.sysref
 add_interface rx_sync conduit end
 set_interface_property rx_sync EXPORT_OF avl_ad9250_xcvr.sync
+add_interface rx_ip_sof conduit end
+set_interface_property rx_ip_sof EXPORT_OF avl_ad9250_xcvr.ip_sof
+add_interface rx_ip_data avalon_streaming source
+set_interface_property rx_ip_data EXPORT_OF avl_ad9250_xcvr.ip_data
 
 # ad9250-xcvr
 
@@ -51,16 +55,20 @@ add_connection axi_ad9250_xcvr.core_pll_locked avl_ad9250_xcvr.core_pll_locked
 add_instance axi_ad9250_core_0 axi_ad9250 1.0
 
 add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_0.if_rx_clk
-add_connection avl_ad9250_xcvr.ip_sof axi_ad9250_core_0.if_rx_sof
-add_connection avl_ad9250_xcvr.ip_data axi_ad9250_core_0.if_rx_data
+add_interface rx_ip_sof_0 conduit end
+set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9250_core_0.if_rx_sof
+add_interface rx_ip_data_0 avalon_streaming sink
+set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9250_core_0.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9250_core_0.s_axi_reset
 add_connection sys_clk.clk axi_ad9250_core_0.s_axi_clock
 
 add_instance axi_ad9250_core_1 axi_ad9250 1.0
 
 add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_1.if_rx_clk
-add_connection avl_ad9250_xcvr.ip_sof axi_ad9250_core_1.if_rx_sof
-add_connection avl_ad9250_xcvr.ip_data axi_ad9250_core_1.if_rx_data
+add_interface rx_ip_sof_1 conduit end
+set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9250_core_1.if_rx_sof
+add_interface rx_ip_data_1 avalon_streaming sink
+set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9250_core_1.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9250_core_1.s_axi_reset
 add_connection sys_clk.clk axi_ad9250_core_1.s_axi_clock
 
@@ -115,12 +123,32 @@ add_connection sys_clk.clk axi_ad9250_dma.s_axi_clock
 add_connection sys_dma_clk.clk_reset axi_ad9250_dma.m_dest_axi_reset
 add_connection sys_dma_clk.clk axi_ad9250_dma.m_dest_axi_clock
 
+# core-clock
+
+add_instance rx_core_clk altera_clock_bridge 16.0
+add_connection avl_ad9250_xcvr.core_clk rx_core_clk.in_clk
+add_interface rx_core_clk clock source
+set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk
+
+# phy reconfiguration
+
+add_instance avl_phy_reconfig alt_xcvr_reconfig 16.0
+set_instance_parameter_value avl_phy_reconfig {number_of_reconfig_interfaces} {4}
+set_instance_parameter_value avl_phy_reconfig {gui_split_sizes} {1,1,1,1}
+add_connection avl_phy_reconfig.ch0_0_to_xcvr avl_ad9250_xcvr.phy_reconfig_to_xcvr_0 
+add_connection avl_ad9250_xcvr.phy_reconfig_from_xcvr_0 avl_phy_reconfig.ch0_0_from_xcvr 
+add_connection avl_phy_reconfig.ch1_1_to_xcvr avl_ad9250_xcvr.phy_reconfig_to_xcvr_1 
+add_connection avl_ad9250_xcvr.phy_reconfig_from_xcvr_1 avl_phy_reconfig.ch1_1_from_xcvr 
+add_connection avl_phy_reconfig.ch2_2_to_xcvr avl_ad9250_xcvr.phy_reconfig_to_xcvr_2 
+add_connection avl_ad9250_xcvr.phy_reconfig_from_xcvr_2 avl_phy_reconfig.ch2_2_from_xcvr 
+add_connection avl_phy_reconfig.ch3_3_to_xcvr avl_ad9250_xcvr.phy_reconfig_to_xcvr_3 
+add_connection avl_ad9250_xcvr.phy_reconfig_from_xcvr_3 avl_phy_reconfig.ch3_3_from_xcvr 
+add_connection sys_clk.clk_reset avl_phy_reconfig.mgmt_rst_reset
+add_connection sys_clk.clk avl_phy_reconfig.mgmt_clk_clk
+
 # addresses
 
-ad_cpu_interconnect 0x00010000 avl_ad9250_xcvr.phy_reconfig_0
-ad_cpu_interconnect 0x00011000 avl_ad9250_xcvr.phy_reconfig_1
-ad_cpu_interconnect 0x00012000 avl_ad9250_xcvr.phy_reconfig_2
-ad_cpu_interconnect 0x00013000 avl_ad9250_xcvr.phy_reconfig_3
+ad_cpu_interconnect 0x00010000 avl_phy_reconfig.reconfig_mgmt
 ad_cpu_interconnect 0x00018000 avl_ad9250_xcvr.core_pll_reconfig
 ad_cpu_interconnect 0x00019000 avl_ad9250_xcvr.ip_reconfig
 ad_cpu_interconnect 0x00020000 axi_ad9250_xcvr.s_axi

From 0b58a2a1dbd3a713a2db49e1fdf1b0ffda400613 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 9 Nov 2016 09:21:07 -0500
Subject: [PATCH 675/972] avl_adxcvr- sysclk frequency

---
 library/altera/avl_adxcvr/avl_adxcvr_hw.tcl      | 13 ++++++++++---
 projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl |  1 +
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
index 0d8b53ad1..f0efb0df7 100755
--- a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
@@ -41,6 +41,12 @@ set_parameter_property LANE_RATE UNITS None
 set_parameter_property LANE_RATE DISPLAY_UNITS "Mbps"
 set_parameter_property LANE_RATE HDL_PARAMETER false
 
+add_parameter SYSCLK_FREQUENCY FLOAT 100.0
+set_parameter_property SYSCLK_FREQUENCY DISPLAY_NAME SYSCLK_FREQUENCY
+set_parameter_property SYSCLK_FREQUENCY TYPE FLOAT
+set_parameter_property SYSCLK_FREQUENCY UNITS Megahertz
+set_parameter_property SYSCLK_FREQUENCY HDL_PARAMETER false
+
 add_parameter PLLCLK_FREQUENCY FLOAT 5000.0
 set_parameter_property PLLCLK_FREQUENCY DISPLAY_NAME PLLCLK_FREQUENCY
 set_parameter_property PLLCLK_FREQUENCY TYPE FLOAT
@@ -103,6 +109,7 @@ proc p_avl_adxcvr {} {
   set m_tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
   set m_num_of_lanes [get_parameter_value "NUM_OF_LANES"]
   set m_device_family [get_parameter_value "DEVICE_FAMILY"]
+  set m_sysclk_frequency [get_parameter_value "SYSCLK_FREQUENCY"]
   set m_pllclk_frequency [get_parameter_value "PLLCLK_FREQUENCY"]
   set m_refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
   set m_coreclk_frequency [get_parameter_value "CORECLK_FREQUENCY"]
@@ -113,7 +120,7 @@ proc p_avl_adxcvr {} {
   set m_hd [get_parameter_value "HD"]
 
   add_instance alt_sys_clk clock_source 16.0
-  set_instance_parameter_value alt_sys_clk {clockFrequency} {100000000.0}
+  set_instance_parameter_value alt_sys_clk {clockFrequency} [expr $m_sysclk_frequency*1000000]
   add_interface sys_clk clock sink
   set_interface_property sys_clk EXPORT_OF alt_sys_clk.clk_in
   add_interface sys_resetn reset sink
@@ -167,7 +174,7 @@ proc p_avl_adxcvr {} {
 
     add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0
     set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes
-    set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} {100}
+    set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} $m_sysclk_frequency
     set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {1}
     set_instance_parameter_value alt_rst_cntrol {T_PLL_POWERDOWN} {1000}
     set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {1}
@@ -309,7 +316,7 @@ proc p_avl_adxcvr {} {
 
     add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0
     set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes
-    set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} {100}
+    set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} $m_sysclk_frequency
     set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {0}
     set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {0}
     set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {1}
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
index 14f2ab91e..8b0c7fb14 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
@@ -6,6 +6,7 @@ set_instance_parameter_value avl_ad9250_xcvr {ID} {1}
 set_instance_parameter_value avl_ad9250_xcvr {TX_OR_RX_N} {0}
 set_instance_parameter_value avl_ad9250_xcvr {PCS_CONFIG} {JESD_PCS_CFG1}
 set_instance_parameter_value avl_ad9250_xcvr {LANE_RATE} {5000.0}
+set_instance_parameter_value avl_ad9250_xcvr {SYSCLK_FREQUENCY} {50.0}
 set_instance_parameter_value avl_ad9250_xcvr {PLLCLK_FREQUENCY} {2500.0}
 set_instance_parameter_value avl_ad9250_xcvr {REFCLK_FREQUENCY} {250.0}
 set_instance_parameter_value avl_ad9250_xcvr {CORECLK_FREQUENCY} {125.0}

From 35c2dd5d6d6354afe30df41d5a71378fcac58a2d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 9 Nov 2016 16:34:08 +0200
Subject: [PATCH 676/972] adrv9371x/zc706: Fix constraints

---
 projects/adrv9371x/zc706/system_constr.xdc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/adrv9371x/zc706/system_constr.xdc b/projects/adrv9371x/zc706/system_constr.xdc
index f6b98aab8..49481db99 100644
--- a/projects/adrv9371x/zc706/system_constr.xdc
+++ b/projects/adrv9371x/zc706/system_constr.xdc
@@ -74,4 +74,5 @@ create_clock -name tx_div_clk     -period  8.00 [get_pins i_system_wrapper/syste
 create_clock -name rx_div_clk     -period  8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 create_clock -name rx_os_div_clk  -period  8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
 
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 

From 3cc416ca609f9ec2fc7b961f70fabc10ddc6f3bc Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 9 Nov 2016 12:04:30 -0500
Subject: [PATCH 677/972] pzsdr1- fix typo on system_ps7

---
 projects/common/pzsdr1/pzsdr1_system_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/common/pzsdr1/pzsdr1_system_bd.tcl b/projects/common/pzsdr1/pzsdr1_system_bd.tcl
index 96c08cb92..94027513c 100644
--- a/projects/common/pzsdr1/pzsdr1_system_bd.tcl
+++ b/projects/common/pzsdr1/pzsdr1_system_bd.tcl
@@ -55,7 +55,7 @@ create_bd_port -dir I -type intr ps_intr_15
 # instance: sys_ps7
 
 set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_ps7.tcl
+source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
 set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7

From 8493bd432996af172e9467d247ce0c02e05608d3 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 9 Nov 2016 16:42:42 +0200
Subject: [PATCH 678/972] axi_ad6676: Update the core, sof interface added

---
 library/axi_ad6676/Makefile          |  1 +
 library/axi_ad6676/axi_ad6676.v      | 59 ++++++++++++++++------------
 library/axi_ad6676/axi_ad6676_if.v   | 39 +++++++++++++-----
 library/axi_ad6676/axi_ad6676_ip.tcl |  2 +
 4 files changed, 67 insertions(+), 34 deletions(-)

diff --git a/library/axi_ad6676/Makefile b/library/axi_ad6676/Makefile
index 07bef5ad4..7e7660720 100644
--- a/library/axi_ad6676/Makefile
+++ b/library/axi_ad6676/Makefile
@@ -16,6 +16,7 @@ M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
 M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += axi_ad6676_pnmon.v
 M_DEPS += axi_ad6676_channel.v
diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v
index de5b289da..4de586635 100755
--- a/library/axi_ad6676/axi_ad6676.v
+++ b/library/axi_ad6676/axi_ad6676.v
@@ -45,18 +45,21 @@ module axi_ad6676 (
   // rx_clk is (line-rate/40)
 
   rx_clk,
+  rx_sof,
+  rx_valid,
+  rx_ready,
   rx_data,
 
   // dma interface
 
   adc_clk,
   adc_rst,
-  adc_valid_a,
-  adc_enable_a,
-  adc_data_a,
-  adc_valid_b,
-  adc_enable_b,
-  adc_data_b,
+  adc_valid_0,
+  adc_enable_0,
+  adc_data_0,
+  adc_valid_1,
+  adc_enable_1,
+  adc_data_1,
   adc_dovf,
   adc_dunf,
 
@@ -92,18 +95,21 @@ module axi_ad6676 (
   // rx_clk is (line-rate/40)
 
   input           rx_clk;
+  input   [ 3:0]  rx_sof;
+  input           rx_valid;
+  output          rx_ready;
   input   [63:0]  rx_data;
 
   // dma interface
 
   output          adc_clk;
   output          adc_rst;
-  output          adc_valid_a;
-  output          adc_enable_a;
-  output  [31:0]  adc_data_a;
-  output          adc_valid_b;
-  output          adc_enable_b;
-  output  [31:0]  adc_data_b;
+  output          adc_valid_0;
+  output          adc_enable_0;
+  output  [31:0]  adc_data_0;
+  output          adc_valid_1;
+  output          adc_enable_1;
+  output  [31:0]  adc_data_1;
   input           adc_dovf;
   input           adc_dunf;
 
@@ -149,8 +155,8 @@ module axi_ad6676 (
 
   // internal signals
 
-  wire    [31:0]  adc_data_a_s;
-  wire    [31:0]  adc_data_b_s;
+  wire    [31:0]  adc_data_0_s;
+  wire    [31:0]  adc_data_1_s;
   wire            adc_or_a_s;
   wire            adc_or_b_s;
   wire            adc_status_s;
@@ -171,6 +177,8 @@ module axi_ad6676 (
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
 
+  assign rx_ready = 1'b1;
+
   // processor read interface
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -193,18 +201,19 @@ module axi_ad6676 (
 
   // adc valid
 
-  assign adc_valid_a = 1'b1;
-  assign adc_valid_b = 1'b1;
+  assign adc_valid_0 = 1'b1;
+  assign adc_valid_1 = 1'b1;
 
   // main (device interface)
 
-  axi_ad6676_if i_if (
+  axi_ad6676_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
     .rx_clk (rx_clk),
+    .rx_sof (rx_sof),
     .rx_data (rx_data),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
-    .adc_data_a (adc_data_a_s),
-    .adc_data_b (adc_data_b_s),
+    .adc_data_a (adc_data_0_s),
+    .adc_data_b (adc_data_1_s),
     .adc_or_a (adc_or_a_s),
     .adc_or_b (adc_or_b_s),
     .adc_status (adc_status_s));
@@ -214,10 +223,10 @@ module axi_ad6676 (
   axi_ad6676_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
-    .adc_data (adc_data_a_s),
+    .adc_data (adc_data_0_s),
     .adc_or (adc_or_a_s),
-    .adc_dfmt_data (adc_data_a),
-    .adc_enable (adc_enable_a),
+    .adc_dfmt_data (adc_data_0),
+    .adc_enable (adc_enable_0),
     .up_adc_pn_err (up_status_pn_err_s[0]),
     .up_adc_pn_oos (up_status_pn_oos_s[0]),
     .up_adc_or (up_status_or_s[0]),
@@ -237,10 +246,10 @@ module axi_ad6676 (
   axi_ad6676_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
-    .adc_data (adc_data_b_s),
+    .adc_data (adc_data_1_s),
     .adc_or (adc_or_b_s),
-    .adc_dfmt_data (adc_data_b),
-    .adc_enable (adc_enable_b),
+    .adc_dfmt_data (adc_data_1),
+    .adc_enable (adc_enable_1),
     .up_adc_pn_err (up_status_pn_err_s[1]),
     .up_adc_pn_oos (up_status_pn_oos_s[1]),
     .up_adc_or (up_status_or_s[1]),
diff --git a/library/axi_ad6676/axi_ad6676_if.v b/library/axi_ad6676/axi_ad6676_if.v
index b0ddedbb1..ecd68a454 100755
--- a/library/axi_ad6676/axi_ad6676_if.v
+++ b/library/axi_ad6676/axi_ad6676_if.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -41,10 +41,11 @@
 
 module axi_ad6676_if (
 
-  // jesd interface 
+  // jesd interface
   // rx_clk is (line-rate/40)
 
   rx_clk,
+  rx_sof,
   rx_data,
 
   // adc data output
@@ -57,10 +58,14 @@ module axi_ad6676_if (
   adc_or_b,
   adc_status);
 
-  // jesd interface 
-  // rx_clk is (line-rate/40)
+  // parameters
+
+  parameter DEVICE_TYPE = 0;
+
+  // jesd interface
 
   input           rx_clk;
+  input   [ 3:0]  rx_sof;
   input   [63:0]  rx_data;
 
   // adc data output
@@ -83,6 +88,7 @@ module axi_ad6676_if (
   wire    [15:0]  adc_data_a_s0_s;
   wire    [15:0]  adc_data_b_s1_s;
   wire    [15:0]  adc_data_b_s0_s;
+  wire    [63:0]  rx_data_s;
 
   // adc clock is the reference clock
 
@@ -99,7 +105,7 @@ module axi_ad6676_if (
 
   assign adc_data_a_s1_s = {rx_data[23:16], rx_data[31:24]};
   assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[15: 8]};
-  assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]}; 
+  assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]};
   assign adc_data_b_s0_s = {rx_data[39:32], rx_data[47:40]};
 
   // status
@@ -112,6 +118,21 @@ module axi_ad6676_if (
     end
   end
 
+  // frame-alignment
+
+  genvar n;
+
+  generate
+  for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
+  ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
+    .rx_clk (rx_clk),
+    .rx_ip_sof (rx_sof),
+    .rx_ip_data (rx_data[((n*32)+31):(n*32)]),
+    .rx_sof (),
+    .rx_data (rx_data_s[((n*32)+31):(n*32)]));
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/axi_ad6676/axi_ad6676_ip.tcl b/library/axi_ad6676/axi_ad6676_ip.tcl
index 3480d7115..ec91fcdc6 100644
--- a/library/axi_ad6676/axi_ad6676_ip.tcl
+++ b/library/axi_ad6676/axi_ad6676_ip.tcl
@@ -13,6 +13,7 @@ adi_ip_files axi_ad6676 [list \
   "$ad_hdl_dir/library/common/up_clock_mon.v" \
   "$ad_hdl_dir/library/common/up_adc_common.v" \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad6676_pnmon.v" \
   "axi_ad6676_channel.v" \
@@ -25,6 +26,7 @@ adi_ip_constraints axi_ad6676 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad6676_constr.xdc" ]
 
+set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 

From d6918de19ed2652213313b5c7abb671e2deb8ebd Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 9 Nov 2016 16:47:31 +0200
Subject: [PATCH 679/972] ad6676: Update projects to xcvr frame work

---
 projects/ad6676evb/common/ad6676evb_bd.tcl  | 119 ++++++--------------
 projects/ad6676evb/vc707/Makefile           |  12 +-
 projects/ad6676evb/vc707/system_constr.xdc  |  15 ++-
 projects/ad6676evb/vc707/system_project.tcl |   2 -
 projects/ad6676evb/vc707/system_top.v       |  12 +-
 projects/ad6676evb/zc706/Makefile           |  12 +-
 projects/ad6676evb/zc706/system_constr.xdc  |  37 +++---
 projects/ad6676evb/zc706/system_project.tcl |   2 -
 projects/ad6676evb/zc706/system_top.v       |  12 +-
 9 files changed, 88 insertions(+), 135 deletions(-)

diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl
index 7424ec3eb..52a442b35 100644
--- a/projects/ad6676evb/common/ad6676evb_bd.tcl
+++ b/projects/ad6676evb/common/ad6676evb_bd.tcl
@@ -1,48 +1,19 @@
 
-# ad6676
-
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir O rx_sysref
-create_bd_port -dir I -from 1 -to 0 rx_data_p
-create_bd_port -dir I -from 1 -to 0 rx_data_n
-
 # adc peripherals
 
-set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
+set axi_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad6676_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad6676_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad6676_xcvr
 
 set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad6676_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd
 set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd
 
-set axi_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad6676_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_gt
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad6676_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad6676_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_ad6676_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad6676_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_ad6676_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad6676_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad6676_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {13}] $axi_ad6676_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {13}] $axi_ad6676_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad6676_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad6676_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_ad6676_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad6676_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad6676_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {13}] $axi_ad6676_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {13}] $axi_ad6676_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad6676_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad6676_gt
+set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
 
-set util_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad6676_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad6676_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad6676_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad6676_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad6676_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_gt
-set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad6676_gt
+set axi_ad6676_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad6676_cpack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad6676_cpack
 
 set axi_ad6676_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad6676_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad6676_dma
@@ -57,71 +28,47 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
 
-set adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 adc_pack]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $adc_pack
+# transceiver core
 
-# connections (gt)
+set util_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad6676_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_ad6676_xcvr
 
-ad_connect util_ad6676_gt/qpll_ref_clk rx_ref_clk
-ad_connect util_ad6676_gt/cpll_ref_clk rx_ref_clk
-
-ad_connect  axi_ad6676_gt/gt_pll_0 util_ad6676_gt/gt_pll_0
-ad_connect  axi_ad6676_gt/gt_pll_1 util_ad6676_gt/gt_pll_1
-
-ad_connect  axi_ad6676_gt/gt_rx_0 util_ad6676_gt/gt_rx_0
-ad_connect  axi_ad6676_gt/gt_rx_1 util_ad6676_gt/gt_rx_1
-
-ad_connect  axi_ad6676_gt/gt_rx_ip_0 axi_ad6676_jesd/gt0_rx
-ad_connect  axi_ad6676_gt/gt_rx_ip_1 axi_ad6676_jesd/gt1_rx
-
-ad_connect  axi_ad6676_gt/rx_gt_comma_align_enb_0 axi_ad6676_jesd/rxencommaalign_out
-ad_connect  axi_ad6676_gt/rx_gt_comma_align_enb_1 axi_ad6676_jesd/rxencommaalign_out
+ad_connect  sys_cpu_resetn util_ad6676_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_ad6676_xcvr/up_clk
 
 # connections (adc)
 
-ad_connect  util_ad6676_gt/rx_p         rx_data_p
-ad_connect  util_ad6676_gt/rx_n         rx_data_n
-ad_connect  util_ad6676_gt/rx_sync      rx_sync
-ad_connect  util_ad6676_gt/rx_ip_sysref rx_sysref
+ad_xcvrcon  util_ad6676_xcvr  axi_ad6676_xcvr axi_ad6676_jesd
+ad_connect  util_ad6676_xcvr/rx_out_clk_0   axi_ad6676_core/rx_clk
+ad_connect  axi_ad6676_jesd/rx_start_of_frame   axi_ad6676_core/rx_sof
+ad_connect  axi_ad6676_jesd/rx_tdata  axi_ad6676_core/rx_data
+ad_connect  util_ad6676_xcvr/rx_out_clk_0   axi_ad6676_cpack/adc_clk
+ad_connect  axi_ad6676_jesd_rstgen/peripheral_reset   axi_ad6676_cpack/adc_rst
+ad_connect  axi_ad6676_core/adc_enable_0  axi_ad6676_cpack/adc_enable_0
+ad_connect  axi_ad6676_core/adc_valid_0   axi_ad6676_cpack/adc_valid_0
+ad_connect  axi_ad6676_core/adc_data_0  axi_ad6676_cpack/adc_data_0
+ad_connect  axi_ad6676_core/adc_enable_1  axi_ad6676_cpack/adc_enable_1
+ad_connect  axi_ad6676_core/adc_valid_1   axi_ad6676_cpack/adc_valid_1
+ad_connect  axi_ad6676_core/adc_data_1  axi_ad6676_cpack/adc_data_1
 
-ad_connect  util_ad6676_gt/rx_out_clk     util_ad6676_gt/rx_clk
-ad_connect  util_ad6676_gt/rx_out_clk     axi_ad6676_jesd/rx_core_clk
-ad_connect  util_ad6676_gt/rx_ip_rst      axi_ad6676_jesd/rx_reset
-ad_connect  util_ad6676_gt/rx_ip_rst_done axi_ad6676_jesd/rx_reset_done
-ad_connect  util_ad6676_gt/rx_ip_sysref   axi_ad6676_jesd/rx_sysref
-ad_connect  util_ad6676_gt/rx_ip_sync     axi_ad6676_jesd/rx_sync
-ad_connect  util_ad6676_gt/rx_ip_sof      axi_ad6676_jesd/rx_start_of_frame
-ad_connect  util_ad6676_gt/rx_ip_data     axi_ad6676_jesd/rx_tdata
-
-ad_connect  axi_ad6676_core/adc_clk   adc_pack/adc_clk
-ad_connect  axi_ad6676_core/adc_rst   adc_pack/adc_rst
-ad_connect  util_ad6676_gt/rx_out_clk axi_ad6676_core/rx_clk
-ad_connect  util_ad6676_gt/rx_data    axi_ad6676_core/rx_data
-
-ad_connect  axi_ad6676_core/adc_enable_a  adc_pack/adc_enable_0
-ad_connect  axi_ad6676_core/adc_valid_a   adc_pack/adc_valid_0
-ad_connect  axi_ad6676_core/adc_data_a    adc_pack/adc_data_0
-ad_connect  axi_ad6676_core/adc_enable_b  adc_pack/adc_enable_1
-ad_connect  axi_ad6676_core/adc_valid_b   adc_pack/adc_valid_1
-ad_connect  axi_ad6676_core/adc_data_b    adc_pack/adc_data_1
-
-ad_connect  axi_ad6676_core/adc_clk       axi_ad6676_dma/fifo_wr_clk
-ad_connect  axi_ad6676_dma/fifo_wr_en     adc_pack/adc_valid
-ad_connect  axi_ad6676_dma/fifo_wr_sync   adc_pack/adc_sync
-ad_connect  axi_ad6676_dma/fifo_wr_din    adc_pack/adc_data
-ad_connect  axi_ad6676_core/adc_dovf      axi_ad6676_dma/fifo_wr_overflow
+ad_connect  axi_ad6676_core/adc_clk   axi_ad6676_dma/fifo_wr_clk
+ad_connect  axi_ad6676_dma/fifo_wr_en   axi_ad6676_cpack/adc_valid
+ad_connect  axi_ad6676_dma/fifo_wr_sync   axi_ad6676_cpack/adc_sync
+ad_connect  axi_ad6676_dma/fifo_wr_din  axi_ad6676_cpack/adc_data
+ad_connect  axi_ad6676_core/adc_dovf  axi_ad6676_dma/fifo_wr_overflow
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_ad6676_gt
+ad_cpu_interconnect 0x44A60000 axi_ad6676_xcvr
 ad_cpu_interconnect 0x44A10000 axi_ad6676_core
 ad_cpu_interconnect 0x44A91000 axi_ad6676_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad6676_dma
 
-# gt uses hp3, and 100MHz clock for both DRP and AXI4
+# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_xcvr/m_axi
 
 # interconnect (adc)
 
diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile
index f37c1c0ef..3ecc4452d 100644
--- a/projects/ad6676evb/vc707/Makefile
+++ b/projects/ad6676evb/vc707/Makefile
@@ -18,10 +18,10 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -51,10 +51,10 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad6676 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_jesd_gt clean
 
 
 ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS)
@@ -64,10 +64,10 @@ ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad6676
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc
index a7ad92199..4d650e118 100644
--- a/projects/ad6676evb/vc707/system_constr.xdc
+++ b/projects/ad6676evb/vc707/system_constr.xdc
@@ -17,11 +17,11 @@ set_property  -dict {PACKAGE_PIN  H41  IOSTANDARD LVCMOS18} [get_ports spi_clk]
 set_property  -dict {PACKAGE_PIN  H40  IOSTANDARD LVCMOS18} [get_ports spi_mosi]                   ; ## H10  FMC_HPC_LA04_P
 set_property  -dict {PACKAGE_PIN  M41  IOSTANDARD LVCMOS18} [get_ports spi_miso]                   ; ## D11  FMC_HPC_LA05_P
 
-set_property  -dict {PACKAGE_PIN  J42  IOSTANDARD LVCMOS18} [get_ports adc_oen]                    ; ## C11  FMC_HPC_LA06_N             
-set_property  -dict {PACKAGE_PIN  M37  IOSTANDARD LVCMOS18} [get_ports adc_sela]                   ; ## G12  FMC_HPC_LA08_P             
-set_property  -dict {PACKAGE_PIN  M38  IOSTANDARD LVCMOS18} [get_ports adc_selb]                   ; ## G13  FMC_HPC_LA08_N             
-set_property  -dict {PACKAGE_PIN  G41  IOSTANDARD LVCMOS18} [get_ports adc_s0]                     ; ## H13  FMC_HPC_LA07_P             
-set_property  -dict {PACKAGE_PIN  G42  IOSTANDARD LVCMOS18} [get_ports adc_s1]                     ; ## H14  FMC_HPC_LA07_N             
+set_property  -dict {PACKAGE_PIN  J42  IOSTANDARD LVCMOS18} [get_ports adc_oen]                    ; ## C11  FMC_HPC_LA06_N
+set_property  -dict {PACKAGE_PIN  M37  IOSTANDARD LVCMOS18} [get_ports adc_sela]                   ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  M38  IOSTANDARD LVCMOS18} [get_ports adc_selb]                   ; ## G13  FMC_HPC_LA08_N
+set_property  -dict {PACKAGE_PIN  G41  IOSTANDARD LVCMOS18} [get_ports adc_s0]                     ; ## H13  FMC_HPC_LA07_P
+set_property  -dict {PACKAGE_PIN  G42  IOSTANDARD LVCMOS18} [get_ports adc_s1]                     ; ## H14  FMC_HPC_LA07_N
 set_property  -dict {PACKAGE_PIN  K42  IOSTANDARD LVCMOS18} [get_ports adc_resetb]                 ; ## C10  FMC_HPC_LA06_P
 set_property  -dict {PACKAGE_PIN  P41  IOSTANDARD LVCMOS18} [get_ports adc_agc1]                   ; ## H07  FMC_HPC_LA02_P
 set_property  -dict {PACKAGE_PIN  N41  IOSTANDARD LVCMOS18} [get_ports adc_agc2]                   ; ## H08  FMC_HPC_LA02_N
@@ -31,4 +31,7 @@ set_property  -dict {PACKAGE_PIN  L42  IOSTANDARD LVCMOS18} [get_ports adc_agc4]
 # clocks
 
 create_clock -name rx_ref_clk   -period  3.30 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_div_clk   -period  6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl
index 5c7821c5b..8ee83f3a3 100644
--- a/projects/ad6676evb/vc707/system_project.tcl
+++ b/projects/ad6676evb/vc707/system_project.tcl
@@ -12,8 +12,6 @@ adi_project_files ad6676evb_vc707 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
-
 adi_project_run ad6676evb_vc707
 
 
diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v
index 80dab57c3..017dd51e0 100644
--- a/projects/ad6676evb/vc707/system_top.v
+++ b/projects/ad6676evb/vc707/system_top.v
@@ -289,11 +289,13 @@ module system_top (
     .mgt_clk_clk_p (mgt_clk_p),
     .phy_rstn (phy_rstn),
     .phy_sd (1'b1),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .sgmii_rxn (sgmii_rxn),
     .sgmii_rxp (sgmii_rxp),
     .sgmii_txn (sgmii_txn),
diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile
index 149104d87..fd9ba7c07 100644
--- a/projects/ad6676evb/zc706/Makefile
+++ b/projects/ad6676evb/zc706/Makefile
@@ -17,13 +17,13 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -53,13 +53,13 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad6676 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_jesd_gt clean
 
 
 ad6676evb_zc706.sdk/system_top.hdf: $(M_DEPS)
@@ -69,13 +69,13 @@ ad6676evb_zc706.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad6676
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc
index 44e3a8ee7..f5d2f91db 100644
--- a/projects/ad6676evb/zc706/system_constr.xdc
+++ b/projects/ad6676evb/zc706/system_constr.xdc
@@ -9,26 +9,29 @@ set_property  -dict {PACKAGE_PIN  AJ8 } [get_ports rx_data_p[1]]
 set_property  -dict {PACKAGE_PIN  AJ7 } [get_ports rx_data_n[1]]                                      ; ## A03  FMC_HPC_DP1_M2C_N
 set_property  -dict {PACKAGE_PIN  AG21  IOSTANDARD LVDS_25} [get_ports rx_sync_p]                     ; ## D08  FMC_HPC_LA01_CC_P
 set_property  -dict {PACKAGE_PIN  AH21  IOSTANDARD LVDS_25} [get_ports rx_sync_n]                     ; ## D09  FMC_HPC_LA01_CC_N
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]    ; ## G06  FMC_HPC_LA00_CC_P       
-set_property  -dict {PACKAGE_PIN  AG20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]    ; ## G07  FMC_HPC_LA00_CC_N       
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p]    ; ## G06  FMC_HPC_LA00_CC_P
+set_property  -dict {PACKAGE_PIN  AG20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n]    ; ## G07  FMC_HPC_LA00_CC_N
 
-set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports spi_csn]                      ; ## D12  FMC_HPC_LA05_N          
-set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## H11  FMC_HPC_LA04_N          
-set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                     ; ## H10  FMC_HPC_LA04_P          
-set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVCMOS25} [get_ports spi_miso]                     ; ## D11  FMC_HPC_LA05_P          
+set_property  -dict {PACKAGE_PIN  AH24  IOSTANDARD LVCMOS25} [get_ports spi_csn]                      ; ## D12  FMC_HPC_LA05_N
+set_property  -dict {PACKAGE_PIN  AK20  IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## H11  FMC_HPC_LA04_N
+set_property  -dict {PACKAGE_PIN  AJ20  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                     ; ## H10  FMC_HPC_LA04_P
+set_property  -dict {PACKAGE_PIN  AH23  IOSTANDARD LVCMOS25} [get_ports spi_miso]                     ; ## D11  FMC_HPC_LA05_P
 
-set_property  -dict {PACKAGE_PIN  AH22  IOSTANDARD LVCMOS25} [get_ports adc_oen]                      ; ## C11  FMC_HPC_LA06_N             
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports adc_sela]                     ; ## G12  FMC_HPC_LA08_P             
-set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVCMOS25} [get_ports adc_selb]                     ; ## G13  FMC_HPC_LA08_N             
-set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVCMOS25} [get_ports adc_s0]                       ; ## H13  FMC_HPC_LA07_P             
-set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVCMOS25} [get_ports adc_s1]                       ; ## H14  FMC_HPC_LA07_N             
-set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports adc_resetb]                   ; ## C10  FMC_HPC_LA06_P          
-set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVCMOS25} [get_ports adc_agc1]                     ; ## H07  FMC_HPC_LA02_P          
-set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVCMOS25} [get_ports adc_agc2]                     ; ## H08  FMC_HPC_LA02_N          
-set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVCMOS25} [get_ports adc_agc3]                     ; ## G09  FMC_HPC_LA03_P          
-set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVCMOS25} [get_ports adc_agc4]                     ; ## G10  FMC_HPC_LA03_N          
+set_property  -dict {PACKAGE_PIN  AH22  IOSTANDARD LVCMOS25} [get_ports adc_oen]                      ; ## C11  FMC_HPC_LA06_N
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports adc_sela]                     ; ## G12  FMC_HPC_LA08_P
+set_property  -dict {PACKAGE_PIN  AG19  IOSTANDARD LVCMOS25} [get_ports adc_selb]                     ; ## G13  FMC_HPC_LA08_N
+set_property  -dict {PACKAGE_PIN  AJ23  IOSTANDARD LVCMOS25} [get_ports adc_s0]                       ; ## H13  FMC_HPC_LA07_P
+set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVCMOS25} [get_ports adc_s1]                       ; ## H14  FMC_HPC_LA07_N
+set_property  -dict {PACKAGE_PIN  AG22  IOSTANDARD LVCMOS25} [get_ports adc_resetb]                   ; ## C10  FMC_HPC_LA06_P
+set_property  -dict {PACKAGE_PIN  AK17  IOSTANDARD LVCMOS25} [get_ports adc_agc1]                     ; ## H07  FMC_HPC_LA02_P
+set_property  -dict {PACKAGE_PIN  AK18  IOSTANDARD LVCMOS25} [get_ports adc_agc2]                     ; ## H08  FMC_HPC_LA02_N
+set_property  -dict {PACKAGE_PIN  AH19  IOSTANDARD LVCMOS25} [get_ports adc_agc3]                     ; ## G09  FMC_HPC_LA03_P
+set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVCMOS25} [get_ports adc_agc4]                     ; ## G10  FMC_HPC_LA03_N
 
 # clocks
 
 create_clock -name rx_ref_clk   -period  3.30 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_div_clk   -period  6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
diff --git a/projects/ad6676evb/zc706/system_project.tcl b/projects/ad6676evb/zc706/system_project.tcl
index debd98e9f..22443724f 100644
--- a/projects/ad6676evb/zc706/system_project.tcl
+++ b/projects/ad6676evb/zc706/system_project.tcl
@@ -12,8 +12,6 @@ adi_project_files ad6676evb_zc706 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
-
 adi_project_run ad6676evb_zc706
 
 
diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v
index 043fdbc68..d873226f1 100644
--- a/projects/ad6676evb/zc706/system_top.v
+++ b/projects/ad6676evb/zc706/system_top.v
@@ -270,11 +270,13 @@ module system_top (
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
     .ps_intr_12 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),

From 8845aeb6abc3505570180d42ec14be83d018087e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 10 Nov 2016 10:48:46 +0200
Subject: [PATCH 680/972] axi_ad9250: Add missing file to Make and script

---
 library/axi_ad9250/Makefile          | 1 +
 library/axi_ad9250/axi_ad9250_ip.tcl | 1 +
 2 files changed, 2 insertions(+)

diff --git a/library/axi_ad9250/Makefile b/library/axi_ad9250/Makefile
index 02c8ac556..3db35f835 100644
--- a/library/axi_ad9250/Makefile
+++ b/library/axi_ad9250/Makefile
@@ -17,6 +17,7 @@ M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
 M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += axi_ad9250_pnmon.v
 M_DEPS += axi_ad9250_channel.v
diff --git a/library/axi_ad9250/axi_ad9250_ip.tcl b/library/axi_ad9250/axi_ad9250_ip.tcl
index 390d75954..9f92a4e8a 100644
--- a/library/axi_ad9250/axi_ad9250_ip.tcl
+++ b/library/axi_ad9250/axi_ad9250_ip.tcl
@@ -14,6 +14,7 @@ adi_ip_files axi_ad9250 [list \
   "$ad_hdl_dir/library/common/up_clock_mon.v" \
   "$ad_hdl_dir/library/common/up_adc_common.v" \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9250_pnmon.v" \
   "axi_ad9250_channel.v" \

From 6073cdded45e1e008c0a11bccbe41c5a0e9a1d5c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 10 Nov 2016 10:52:37 +0200
Subject: [PATCH 681/972] axi_ad9250: Tie rx_valid to ground

---
 library/axi_ad9250/axi_ad9250_ip.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_ad9250/axi_ad9250_ip.tcl b/library/axi_ad9250/axi_ad9250_ip.tcl
index 9f92a4e8a..46055f829 100644
--- a/library/axi_ad9250/axi_ad9250_ip.tcl
+++ b/library/axi_ad9250/axi_ad9250_ip.tcl
@@ -28,6 +28,7 @@ adi_ip_constraints axi_ad9250 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9250_constr.xdc" ]
 
+set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 

From a54092c9bb8bdf7246c9669c34761aeec94f5b35 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 10 Nov 2016 10:59:52 +0200
Subject: [PATCH 682/972] fmcjesdadc1: Update projects to xcvr framework

This commit contains modifications for Xilinx only
---
 .../fmcjesdadc1/common/fmcjesdadc1_bd.tcl     | 203 ++++++------------
 projects/fmcjesdadc1/kc705/Makefile           |  12 +-
 projects/fmcjesdadc1/kc705/system_constr.xdc  |   5 +-
 projects/fmcjesdadc1/kc705/system_project.tcl |   3 +-
 projects/fmcjesdadc1/kc705/system_top.v       |  16 +-
 projects/fmcjesdadc1/vc707/Makefile           |  12 +-
 projects/fmcjesdadc1/vc707/system_constr.xdc  |   5 +-
 projects/fmcjesdadc1/vc707/system_project.tcl |   2 -
 projects/fmcjesdadc1/vc707/system_top.v       |  16 +-
 projects/fmcjesdadc1/zc706/Makefile           |  12 +-
 projects/fmcjesdadc1/zc706/system_constr.xdc  |   5 +-
 projects/fmcjesdadc1/zc706/system_project.tcl |   5 -
 projects/fmcjesdadc1/zc706/system_top.v       |  16 +-
 13 files changed, 131 insertions(+), 181 deletions(-)

diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
index a6cc87cb7..fd10f8ec0 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
@@ -1,63 +1,26 @@
 
-# ad9250
-
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir O rx_sysref
-create_bd_port -dir I -from 3 -to 0 rx_data_p
-create_bd_port -dir I -from 3 -to 0 rx_data_n
-
 # adc peripherals
 
-set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
-set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
+set axi_ad9250_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9250_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9250_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9250_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9250_xcvr
 
 set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9250_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd
 
-set axi_ad9250_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9250_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9250_gt
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad9250_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad9250_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_ad9250_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9250_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_ad9250_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9250_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_ad9250_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9250_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_ad9250_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_ad9250_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9250_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9250_gt
+set data_bsplit [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 data_bsplit]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64} ] $data_bsplit
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_bsplit
 
-set util_fmcjesdadc1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcjesdadc1_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_fmcjesdadc1_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_fmcjesdadc1_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_fmcjesdadc1_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcjesdadc1_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_gt
-set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcjesdadc1_gt
+set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
+set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
+
+set axi_ad9250_0_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9250_0_cpack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9250_0_cpack
+set axi_ad9250_1_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9250_1_cpack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9250_1_cpack
 
 set axi_ad9250_0_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_0_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9250_0_dma
@@ -85,111 +48,79 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_1_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma
 
-set data_bsplit [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 data_bsplit]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64} ] $data_bsplit
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_bsplit
+# transceiver core
 
-set data_pack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack_0]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack_0
+set util_fmcjesdadc1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcjesdadc1_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcjesdadc1_xcvr
 
-set data_pack_1 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack_1]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack_1
-
-# connections (gt)
-
-ad_connect util_fmcjesdadc1_gt/qpll_ref_clk rx_ref_clk
-ad_connect util_fmcjesdadc1_gt/cpll_ref_clk rx_ref_clk
-
-ad_connect  axi_ad9250_gt/gt_pll_0 util_fmcjesdadc1_gt/gt_pll_0
-ad_connect  axi_ad9250_gt/gt_pll_1 util_fmcjesdadc1_gt/gt_pll_1
-ad_connect  axi_ad9250_gt/gt_pll_2 util_fmcjesdadc1_gt/gt_pll_2
-ad_connect  axi_ad9250_gt/gt_pll_3 util_fmcjesdadc1_gt/gt_pll_3
-
-ad_connect  axi_ad9250_gt/gt_rx_0 util_fmcjesdadc1_gt/gt_rx_0
-ad_connect  axi_ad9250_gt/gt_rx_1 util_fmcjesdadc1_gt/gt_rx_1
-ad_connect  axi_ad9250_gt/gt_rx_2 util_fmcjesdadc1_gt/gt_rx_2
-ad_connect  axi_ad9250_gt/gt_rx_3 util_fmcjesdadc1_gt/gt_rx_3
-
-ad_connect  axi_ad9250_gt/gt_rx_ip_0 axi_ad9250_jesd/gt0_rx
-ad_connect  axi_ad9250_gt/gt_rx_ip_1 axi_ad9250_jesd/gt1_rx
-ad_connect  axi_ad9250_gt/gt_rx_ip_2 axi_ad9250_jesd/gt2_rx
-ad_connect  axi_ad9250_gt/gt_rx_ip_3 axi_ad9250_jesd/gt3_rx
-
-ad_connect  axi_ad9250_gt/rx_gt_comma_align_enb_0 axi_ad9250_jesd/rxencommaalign_out
-ad_connect  axi_ad9250_gt/rx_gt_comma_align_enb_1 axi_ad9250_jesd/rxencommaalign_out
-ad_connect  axi_ad9250_gt/rx_gt_comma_align_enb_2 axi_ad9250_jesd/rxencommaalign_out
-ad_connect  axi_ad9250_gt/rx_gt_comma_align_enb_3 axi_ad9250_jesd/rxencommaalign_out
+ad_connect  sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk
 
 # connections (adc)
 
-ad_connect  util_fmcjesdadc1_gt/rx_ip_sysref rx_sysref
-ad_connect  util_fmcjesdadc1_gt/rx_p rx_data_p
-ad_connect  util_fmcjesdadc1_gt/rx_n rx_data_n
-ad_connect  util_fmcjesdadc1_gt/rx_sync rx_sync
+ad_xcvrcon  util_fmcjesdadc1_xcvr  axi_ad9250_xcvr axi_ad9250_jesd
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0   axi_ad9250_0_core/rx_clk
+ad_connect  axi_ad9250_jesd/rx_start_of_frame   axi_ad9250_0_core/rx_sof
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0   axi_ad9250_1_core/rx_clk
+ad_connect  axi_ad9250_jesd/rx_start_of_frame   axi_ad9250_1_core/rx_sof
 
-ad_connect  util_fmcjesdadc1_gt/rx_out_clk      util_fmcjesdadc1_gt/rx_clk
-ad_connect  util_fmcjesdadc1_gt/rx_out_clk      axi_ad9250_jesd/rx_core_clk
-ad_connect  util_fmcjesdadc1_gt/rx_ip_rst       axi_ad9250_jesd/rx_reset
-ad_connect  util_fmcjesdadc1_gt/rx_ip_rst_done  axi_ad9250_jesd/rx_reset_done
-ad_connect  util_fmcjesdadc1_gt/rx_ip_sysref    axi_ad9250_jesd/rx_sysref
-ad_connect  util_fmcjesdadc1_gt/rx_ip_sync      axi_ad9250_jesd/rx_sync
-ad_connect  util_fmcjesdadc1_gt/rx_ip_sof       axi_ad9250_jesd/rx_start_of_frame
-ad_connect  util_fmcjesdadc1_gt/rx_ip_data      axi_ad9250_jesd/rx_tdata
+ad_connect  axi_ad9250_jesd/rx_tdata  data_bsplit/data
+ad_connect  axi_ad9250_0_core/rx_data   data_bsplit/split_data_0
+ad_connect  axi_ad9250_1_core/rx_data   data_bsplit/split_data_1
 
-ad_connect  data_bsplit/data util_fmcjesdadc1_gt/rx_data
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0   axi_ad9250_0_cpack/adc_clk
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0   axi_ad9250_1_cpack/adc_clk
+ad_connect  axi_ad9250_jesd_rstgen/peripheral_reset   axi_ad9250_0_cpack/adc_rst
+ad_connect  axi_ad9250_jesd_rstgen/peripheral_reset   axi_ad9250_1_cpack/adc_rst
 
-ad_connect  axi_ad9250_0_core/adc_clk       data_pack_0/adc_clk
-ad_connect  axi_ad9250_0_core/adc_rst       data_pack_0/adc_rst
-ad_connect  util_fmcjesdadc1_gt/rx_out_clk  axi_ad9250_0_core/rx_clk
-ad_connect  data_bsplit/split_data_0        axi_ad9250_0_core/rx_data
-ad_connect  axi_ad9250_0_core/adc_enable_a  data_pack_0/adc_enable_0
-ad_connect  axi_ad9250_0_core/adc_valid_a   data_pack_0/adc_valid_0
-ad_connect  axi_ad9250_0_core/adc_data_a    data_pack_0/adc_data_0
-ad_connect  axi_ad9250_0_core/adc_enable_b  data_pack_0/adc_enable_1
-ad_connect  axi_ad9250_0_core/adc_valid_b   data_pack_0/adc_valid_1
-ad_connect  axi_ad9250_0_core/adc_data_b    data_pack_0/adc_data_1
-ad_connect  axi_ad9250_0_core/adc_clk       axi_ad9250_0_dma/fifo_wr_clk
-ad_connect  axi_ad9250_0_dma/fifo_wr_en     data_pack_0/adc_valid
-ad_connect  axi_ad9250_0_dma/fifo_wr_sync   data_pack_0/adc_sync
-ad_connect  axi_ad9250_0_dma/fifo_wr_din    data_pack_0/adc_data
-ad_connect  axi_ad9250_0_core/adc_dovf      axi_ad9250_0_dma/fifo_wr_overflow
+ad_connect  axi_ad9250_0_core/adc_enable_a  axi_ad9250_0_cpack/adc_enable_0
+ad_connect  axi_ad9250_0_core/adc_valid_a   axi_ad9250_0_cpack/adc_valid_0
+ad_connect  axi_ad9250_0_core/adc_data_a  axi_ad9250_0_cpack/adc_data_0
+ad_connect  axi_ad9250_0_core/adc_enable_b  axi_ad9250_0_cpack/adc_enable_1
+ad_connect  axi_ad9250_0_core/adc_valid_b   axi_ad9250_0_cpack/adc_valid_1
+ad_connect  axi_ad9250_0_core/adc_data_b  axi_ad9250_0_cpack/adc_data_1
+ad_connect  axi_ad9250_1_core/adc_enable_a  axi_ad9250_1_cpack/adc_enable_0
+ad_connect  axi_ad9250_1_core/adc_valid_a   axi_ad9250_1_cpack/adc_valid_0
+ad_connect  axi_ad9250_1_core/adc_data_a  axi_ad9250_1_cpack/adc_data_0
+ad_connect  axi_ad9250_1_core/adc_enable_b  axi_ad9250_1_cpack/adc_enable_1
+ad_connect  axi_ad9250_1_core/adc_valid_b   axi_ad9250_1_cpack/adc_valid_1
+ad_connect  axi_ad9250_1_core/adc_data_b  axi_ad9250_1_cpack/adc_data_1
 
-ad_connect  axi_ad9250_1_core/adc_clk       data_pack_1/adc_clk
-ad_connect  axi_ad9250_1_core/adc_rst       data_pack_1/adc_rst
-ad_connect  util_fmcjesdadc1_gt/rx_out_clk  axi_ad9250_1_core/rx_clk
-ad_connect  data_bsplit/split_data_1        axi_ad9250_1_core/rx_data
-ad_connect  axi_ad9250_1_core/adc_enable_a  data_pack_1/adc_enable_0
-ad_connect  axi_ad9250_1_core/adc_valid_a   data_pack_1/adc_valid_0
-ad_connect  axi_ad9250_1_core/adc_data_a    data_pack_1/adc_data_0
-ad_connect  axi_ad9250_1_core/adc_enable_b  data_pack_1/adc_enable_1
-ad_connect  axi_ad9250_1_core/adc_valid_b   data_pack_1/adc_valid_1
-ad_connect  axi_ad9250_1_core/adc_data_b    data_pack_1/adc_data_1
+ad_connect  axi_ad9250_0_core/adc_clk   axi_ad9250_0_dma/fifo_wr_clk
+ad_connect  axi_ad9250_0_dma/fifo_wr_en   axi_ad9250_0_cpack/adc_valid
+ad_connect  axi_ad9250_0_dma/fifo_wr_sync   axi_ad9250_0_cpack/adc_sync
+ad_connect  axi_ad9250_0_dma/fifo_wr_din  axi_ad9250_0_cpack/adc_data
+ad_connect  axi_ad9250_0_core/adc_dovf  axi_ad9250_0_dma/fifo_wr_overflow
+ad_connect  axi_ad9250_1_core/adc_clk   axi_ad9250_1_dma/fifo_wr_clk
+ad_connect  axi_ad9250_1_dma/fifo_wr_en   axi_ad9250_1_cpack/adc_valid
+ad_connect  axi_ad9250_1_dma/fifo_wr_sync   axi_ad9250_1_cpack/adc_sync
+ad_connect  axi_ad9250_1_dma/fifo_wr_din  axi_ad9250_1_cpack/adc_data
+ad_connect  axi_ad9250_1_core/adc_dovf  axi_ad9250_1_dma/fifo_wr_overflow
 
-ad_connect  axi_ad9250_1_core/adc_clk       axi_ad9250_1_dma/fifo_wr_clk
+# interconnect (cpu)
 
-ad_connect  axi_ad9250_1_dma/fifo_wr_en     data_pack_1/adc_valid
-ad_connect  axi_ad9250_1_dma/fifo_wr_sync   data_pack_1/adc_sync
-ad_connect  axi_ad9250_1_dma/fifo_wr_din    data_pack_1/adc_data
-ad_connect  axi_ad9250_1_core/adc_dovf      axi_ad9250_1_dma/fifo_wr_overflow
+ad_cpu_interconnect 0x44A60000 axi_ad9250_xcvr
+ad_cpu_interconnect 0x44A10000 axi_ad9250_0_core
+ad_cpu_interconnect 0x44A20000 axi_ad9250_1_core
+ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd
+ad_cpu_interconnect 0x7c420000 axi_ad9250_0_dma
+ad_cpu_interconnect 0x7c430000 axi_ad9250_1_dma
 
-# interconnects
+# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
 
-ad_cpu_interconnect 0x44A10000  axi_ad9250_0_core
-ad_cpu_interconnect 0x44A20000  axi_ad9250_1_core
-ad_cpu_interconnect 0x44A60000  axi_ad9250_gt
-ad_cpu_interconnect 0x44A91000  axi_ad9250_jesd
-ad_cpu_interconnect 0x7c420000  axi_ad9250_0_dma
-ad_cpu_interconnect 0x7c430000  axi_ad9250_1_dma
+ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9250_xcvr/m_axi
+
+# interconnect (adc)
 
 ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
 ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_0_dma/m_dest_axi
 ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_1_dma/m_dest_axi
+
 ad_connect  sys_cpu_resetn axi_ad9250_0_dma/m_dest_axi_aresetn
 ad_connect  sys_cpu_resetn axi_ad9250_1_dma/m_dest_axi_aresetn
 
-ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_ad9250_gt/m_axi
-
 #interrupts
 
 ad_cpu_interrupt ps-13 mb-13 axi_ad9250_0_dma/irq
diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile
index f2d344498..d704ece29 100644
--- a/projects/fmcjesdadc1/kc705/Makefile
+++ b/projects/fmcjesdadc1/kc705/Makefile
@@ -19,11 +19,11 @@ M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -53,11 +53,11 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9250 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_bsplit clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_jesd_gt clean
 
 
 fmcjesdadc1_kc705.sdk/system_top.hdf: $(M_DEPS)
@@ -67,11 +67,11 @@ fmcjesdadc1_kc705.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9250
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_bsplit
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcjesdadc1/kc705/system_constr.xdc b/projects/fmcjesdadc1/kc705/system_constr.xdc
index 66d941e14..8a06d8d97 100644
--- a/projects/fmcjesdadc1/kc705/system_constr.xdc
+++ b/projects/fmcjesdadc1/kc705/system_constr.xdc
@@ -21,4 +21,7 @@ set_property  -dict {PACKAGE_PIN  D21   IOSTANDARD LVCMOS25} [get_ports spi_sdio
 # clocks
 
 create_clock -name rx_ref_clk   -period  4.00 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
diff --git a/projects/fmcjesdadc1/kc705/system_project.tcl b/projects/fmcjesdadc1/kc705/system_project.tcl
index 3b094ef0e..33fe320b7 100644
--- a/projects/fmcjesdadc1/kc705/system_project.tcl
+++ b/projects/fmcjesdadc1/kc705/system_project.tcl
@@ -11,6 +11,5 @@ adi_project_files fmcjesdadc1_kc705 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
-  
 adi_project_run fmcjesdadc1_kc705
+
diff --git a/projects/fmcjesdadc1/kc705/system_top.v b/projects/fmcjesdadc1/kc705/system_top.v
index cac2d30e7..c8b9cbd1c 100644
--- a/projects/fmcjesdadc1/kc705/system_top.v
+++ b/projects/fmcjesdadc1/kc705/system_top.v
@@ -266,11 +266,17 @@ module system_top (
     .sys_rst (sys_rst),
     .uart_sin (uart_sin),
     .uart_sout (uart_sout),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spi_clk_i (spi_clk),
     .spi_clk_o (spi_clk),
     .spi_csn_i (spi_csn),
diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile
index 9d3448e72..c62009f4f 100644
--- a/projects/fmcjesdadc1/vc707/Makefile
+++ b/projects/fmcjesdadc1/vc707/Makefile
@@ -19,11 +19,11 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -53,11 +53,11 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9250 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_bsplit clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_jesd_gt clean
 
 
 fmcjesdadc1_vc707.sdk/system_top.hdf: $(M_DEPS)
@@ -67,11 +67,11 @@ fmcjesdadc1_vc707.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9250
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_bsplit
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcjesdadc1/vc707/system_constr.xdc b/projects/fmcjesdadc1/vc707/system_constr.xdc
index 89ae7c053..f7ad93138 100644
--- a/projects/fmcjesdadc1/vc707/system_constr.xdc
+++ b/projects/fmcjesdadc1/vc707/system_constr.xdc
@@ -21,4 +21,7 @@ set_property  -dict {PACKAGE_PIN  V29   IOSTANDARD LVCMOS18} [get_ports spi_sdio
 # clocks
 
 create_clock -name rx_ref_clk   -period  4.00 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
diff --git a/projects/fmcjesdadc1/vc707/system_project.tcl b/projects/fmcjesdadc1/vc707/system_project.tcl
index 64689dc0e..7835780ea 100644
--- a/projects/fmcjesdadc1/vc707/system_project.tcl
+++ b/projects/fmcjesdadc1/vc707/system_project.tcl
@@ -11,6 +11,4 @@ adi_project_files fmcjesdadc1_vc707 [list \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
-  
 adi_project_run fmcjesdadc1_vc707
diff --git a/projects/fmcjesdadc1/vc707/system_top.v b/projects/fmcjesdadc1/vc707/system_top.v
index 5bbc6ab0b..639a85eee 100644
--- a/projects/fmcjesdadc1/vc707/system_top.v
+++ b/projects/fmcjesdadc1/vc707/system_top.v
@@ -256,11 +256,17 @@ module system_top (
     .sys_rst (sys_rst),
     .uart_sin (uart_sin),
     .uart_sout (uart_sout),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spi_clk_i (1'b0),
     .spi_clk_o (spi_clk),
     .spi_csn_i (8'hff),
diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile
index f9fe02005..f472a6ae2 100644
--- a/projects/fmcjesdadc1/zc706/Makefile
+++ b/projects/fmcjesdadc1/zc706/Makefile
@@ -18,14 +18,14 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -55,14 +55,14 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9250 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_bsplit clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_jesd_gt clean
 
 
 fmcjesdadc1_zc706.sdk/system_top.hdf: $(M_DEPS)
@@ -72,14 +72,14 @@ fmcjesdadc1_zc706.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9250
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_bsplit
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcjesdadc1/zc706/system_constr.xdc b/projects/fmcjesdadc1/zc706/system_constr.xdc
index 71b03d0fb..eff780e85 100644
--- a/projects/fmcjesdadc1/zc706/system_constr.xdc
+++ b/projects/fmcjesdadc1/zc706/system_constr.xdc
@@ -21,4 +21,7 @@ set_property  -dict {PACKAGE_PIN  P21   IOSTANDARD LVCMOS25} [get_ports spi_sdio
 # clocks
 
 create_clock -name rx_ref_clk   -period  4.00 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
diff --git a/projects/fmcjesdadc1/zc706/system_project.tcl b/projects/fmcjesdadc1/zc706/system_project.tcl
index 8d06f1806..0a0531c5f 100644
--- a/projects/fmcjesdadc1/zc706/system_project.tcl
+++ b/projects/fmcjesdadc1/zc706/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
@@ -13,8 +11,5 @@ adi_project_files fmcjesdadc1_zc706 [list \
   "system_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
-  
 adi_project_run fmcjesdadc1_zc706
 
-
diff --git a/projects/fmcjesdadc1/zc706/system_top.v b/projects/fmcjesdadc1/zc706/system_top.v
index 6037cc59c..dc4e9f375 100644
--- a/projects/fmcjesdadc1/zc706/system_top.v
+++ b/projects/fmcjesdadc1/zc706/system_top.v
@@ -224,11 +224,17 @@ module system_top (
     .ps_intr_09 (1'b0),
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),

From d29ef14f369d29c54aea038fd29e54d61ebfb081 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 10 Nov 2016 17:06:42 +0200
Subject: [PATCH 683/972] sdrstk: Configured ad9361 in 1r1t mode

---
 projects/sdrstk/system_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/sdrstk/system_bd.tcl b/projects/sdrstk/system_bd.tcl
index 75981cd4e..61c72a602 100644
--- a/projects/sdrstk/system_bd.tcl
+++ b/projects/sdrstk/system_bd.tcl
@@ -172,6 +172,7 @@ create_bd_port -dir I up_txnrx
 set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
 set_property -dict [list CONFIG.ID {0}] $axi_ad9361
 set_property -dict [list CONFIG.CMOS_OR_LVDS_N {1}] $axi_ad9361
+set_property -dict [list CONFIG.MODE_1R1T {1}] $axi_ad9361
 
 set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma

From 66098b7ae70152fe3a5edb5e7caa7bf87e106199 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 10 Nov 2016 17:43:04 +0200
Subject: [PATCH 684/972] util_fir_dec: Update filter, as it's used with ad9361
 in CMOS mode

---
 library/util_fir_dec/util_fir_dec_ip.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/util_fir_dec/util_fir_dec_ip.tcl b/library/util_fir_dec/util_fir_dec_ip.tcl
index 76b2709d9..3fa105477 100644
--- a/library/util_fir_dec/util_fir_dec_ip.tcl
+++ b/library/util_fir_dec/util_fir_dec_ip.tcl
@@ -5,7 +5,7 @@ adi_ip_create util_fir_dec
 
 set fir_decim [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_decim]
  set_property -dict [ list \
-CONFIG.Clock_Frequency {128.8} \
+CONFIG.Clock_Frequency {61.44} \
 CONFIG.CoefficientSource {COE_File} \
 CONFIG.Coefficient_File {../../../../coefile_dec.coe} \
 CONFIG.Coefficient_Fractional_Bits {0} \
@@ -25,7 +25,7 @@ CONFIG.Output_Rounding_Mode {Truncate_LSBs} \
 CONFIG.Output_Width {16} \
 CONFIG.Quantization {Integer_Coefficients} \
 CONFIG.RateSpecification {Frequency_Specification} \
-CONFIG.Sample_Frequency {64.4} \
+CONFIG.Sample_Frequency {61.44} \
 CONFIG.Zero_Pack_Factor {1} \
  ] [get_ips fir_decim]
 

From 64d1d54ec04ba542314e531a787892cc7410da48 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 10 Nov 2016 17:45:03 +0200
Subject: [PATCH 685/972] util_fir_int: Update filter, as it's used with ad9361
 in CMOS mode

---
 library/util_fir_int/util_fir_int_ip.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/util_fir_int/util_fir_int_ip.tcl b/library/util_fir_int/util_fir_int_ip.tcl
index 1a0fbe32b..83d0b2dac 100644
--- a/library/util_fir_int/util_fir_int_ip.tcl
+++ b/library/util_fir_int/util_fir_int_ip.tcl
@@ -5,7 +5,7 @@ adi_ip_create util_fir_int
 
 set fir_interp [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_interp]
  set_property -dict [ list \
-CONFIG.Clock_Frequency {128.8} \
+CONFIG.Clock_Frequency {61.44} \
 CONFIG.CoefficientSource {COE_File} \
 CONFIG.Coefficient_File {../../../../coefile_int.coe} \
 CONFIG.Coefficient_Fractional_Bits {0} \
@@ -26,7 +26,7 @@ CONFIG.Output_Rounding_Mode {Truncate_LSBs} \
 CONFIG.Output_Width {16} \
 CONFIG.Quantization {Integer_Coefficients} \
 CONFIG.RateSpecification {Frequency_Specification} \
-CONFIG.Sample_Frequency {8} \
+CONFIG.Sample_Frequency {7.68} \
 CONFIG.Zero_Pack_Factor {1} \
  ] [get_ips fir_interp]
 

From 7a606cbae154f120656dcf53687692ffccd03f27 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 10 Nov 2016 17:45:35 +0200
Subject: [PATCH 686/972] sdrstk: Maximum clock frequency is 61.44 in CMOS mode

---
 projects/sdrstk/system_constr.xdc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/sdrstk/system_constr.xdc b/projects/sdrstk/system_constr.xdc
index c7e4264ca..5659c6cff 100644
--- a/projects/sdrstk/system_constr.xdc
+++ b/projects/sdrstk/system_constr.xdc
@@ -62,7 +62,7 @@ set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports spi_miso]
 set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports gpio_bd]
 set_property  -dict {PACKAGE_PIN  P8   IOSTANDARD LVCMOS18} [get_ports clk_out]
 
-create_clock -name rx_clk -period  7.77 [get_ports rx_clk_in]
+create_clock -name rx_clk -period  16.27 [get_ports rx_clk_in]
 
 # probably gone in 2016.4
 

From 8af0731bb0e07e6d5ec1de416c0e26199b6ea026 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Nov 2016 10:52:39 -0500
Subject: [PATCH 687/972] a5gt- qsys2tcl flow

---
 projects/common/a5gt/a5gt_system_bd.qsys  | 2326 ---------------------
 projects/common/a5gt/a5gt_system_qsys.tcl |  325 +++
 2 files changed, 325 insertions(+), 2326 deletions(-)
 delete mode 100644 projects/common/a5gt/a5gt_system_bd.qsys
 create mode 100644 projects/common/a5gt/a5gt_system_qsys.tcl

diff --git a/projects/common/a5gt/a5gt_system_bd.qsys b/projects/common/a5gt/a5gt_system_bd.qsys
deleted file mode 100644
index 37f968cb1..000000000
--- a/projects/common/a5gt/a5gt_system_bd.qsys
+++ /dev/null
@@ -1,2326 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element a5gt_system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element cpu_clk
-   {
-      datum _sortIndex
-      {
-         value = "21";
-         type = "int";
-      }
-   }
-   element cpu_reset
-   {
-      datum _sortIndex
-      {
-         value = "22";
-         type = "int";
-      }
-   }
-   element mem_clk
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element mem_rst
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_cpu
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_cpu.debug_mem_slave
-   {
-      datum baseAddress
-      {
-         value = "354473984";
-         type = "String";
-      }
-   }
-   element sys_cpu_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_cpu_interconnect.s0
-   {
-      datum baseAddress
-      {
-         value = "536870912";
-         type = "String";
-      }
-   }
-   element sys_ddr3_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ddr3_cntrl.avl
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_ethernet
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet.control_port
-   {
-      datum baseAddress
-      {
-         value = "354476032";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet_dma_rx.csr
-   {
-      datum baseAddress
-      {
-         value = "354477120";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx.descriptor_slave
-   {
-      datum baseAddress
-      {
-         value = "354477152";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx.response
-   {
-      datum baseAddress
-      {
-         value = "354477184";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_tx
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet_dma_tx.csr
-   {
-      datum baseAddress
-      {
-         value = "354477056";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_tx.descriptor_slave
-   {
-      datum baseAddress
-      {
-         value = "354477088";
-         type = "String";
-      }
-   }
-   element sys_gpio
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_gpio.s1
-   {
-      datum baseAddress
-      {
-         value = "354477248";
-         type = "String";
-      }
-   }
-   element sys_gpio_bd
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_gpio_bd.s1
-   {
-      datum baseAddress
-      {
-         value = "354477344";
-         type = "String";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_id.control_slave
-   {
-      datum baseAddress
-      {
-         value = "354477272";
-         type = "String";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_int_mem.s1
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "352321536";
-         type = "String";
-      }
-   }
-   element sys_int_mem.s2
-   {
-      datum baseAddress
-      {
-         value = "352321536";
-         type = "String";
-      }
-   }
-   element sys_intr
-   {
-      datum _sortIndex
-      {
-         value = "23";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_mem_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_pll
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element sys_spi
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_spi.spi_control_port
-   {
-      datum baseAddress
-      {
-         value = "354477312";
-         type = "String";
-      }
-   }
-   element sys_tcm_mem
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_tcm_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "354467840";
-         type = "String";
-      }
-   }
-   element sys_tcm_mem.s2
-   {
-      datum baseAddress
-      {
-         value = "354467840";
-         type = "String";
-      }
-   }
-   element sys_timer
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_timer.s1
-   {
-      datum baseAddress
-      {
-         value = "354477216";
-         type = "String";
-      }
-   }
-   element sys_timer_2nd
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_timer_2nd.s1
-   {
-      datum baseAddress
-      {
-         value = "354477376";
-         type = "String";
-      }
-   }
-   element sys_uart
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "0";
-         type = "boolean";
-      }
-   }
-   element sys_uart.avalon_jtag_slave
-   {
-      datum baseAddress
-      {
-         value = "354477280";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5AGTFD7K3F40I3" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="cpu_clk" internal="cpu_clk.out_clk" type="clock" dir="start" />
- <interface
-   name="cpu_rst"
-   internal="cpu_reset.out_reset"
-   type="reset"
-   dir="start" />
- <interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
- <interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
- <interface
-   name="sys_125m_clk"
-   internal="sys_pll.outclk0"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_25m_clk"
-   internal="sys_pll.outclk1"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_2m5_clk"
-   internal="sys_pll.outclk2"
-   type="clock"
-   dir="start" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface
-   name="sys_cpu_interconnect_m0"
-   internal="sys_cpu_interconnect.m0"
-   type="avalon"
-   dir="start" />
- <interface
-   name="sys_ddr3_oct"
-   internal="sys_ddr3_cntrl.oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ddr3_phy"
-   internal="sys_ddr3_cntrl.memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_mdio"
-   internal="sys_ethernet.mac_mdio_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_rgmii"
-   internal="sys_ethernet.mac_rgmii_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_rx_clk"
-   internal="sys_ethernet.pcs_mac_rx_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_ethernet_status"
-   internal="sys_ethernet.mac_status_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_tx_clk"
-   internal="sys_ethernet.pcs_mac_tx_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_gpio"
-   internal="sys_gpio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_bd"
-   internal="sys_gpio_bd.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_intr"
-   internal="sys_intr.receiver_irq"
-   type="interrupt"
-   dir="start" />
- <interface
-   name="sys_mem_interconnect_s0"
-   internal="sys_mem_interconnect.s0"
-   type="avalon"
-   dir="end" />
- <interface
-   name="sys_pll_locked"
-   internal="sys_pll.locked"
-   type="conduit"
-   dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module name="cpu_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="100000000" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module
-   name="cpu_reset"
-   kind="altera_reset_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="100000000" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="1000000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="14" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="14" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="bht_ramBlockType" value="Automatic" />
-  <parameter name="breakOffset" value="32" />
-  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
-  <parameter name="cdx_enabled" value="false" />
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="cpuArchRev" value="1" />
-  <parameter name="cpuID" value="0" />
-  <parameter name="cpuReset" value="false" />
-  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
-  <parameter name="dataAddrWidth" value="30" />
-  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s1' start='0x15000000' end='0x150C0000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x1520D800' end='0x1520E000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x1520E000' end='0x1520E400' type='altera_eth_tse.control_port' /><slave name='sys_ethernet_dma_tx.csr' start='0x1520E400' end='0x1520E420' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x1520E420' end='0x1520E440' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_rx.csr' start='0x1520E440' end='0x1520E460' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x1520E460' end='0x1520E480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_rx.response' start='0x1520E480' end='0x1520E488' type='altera_msgdma.response' /><slave name='sys_timer.s1' start='0x1520E4A0' end='0x1520E4C0' type='altera_avalon_timer.s1' /><slave name='sys_gpio.s1' start='0x1520E4C0' end='0x1520E4D0' type='altera_avalon_pio.s1' /><slave name='sys_id.control_slave' start='0x1520E4D8' end='0x1520E4E0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x1520E4E0' end='0x1520E4E8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_spi.spi_control_port' start='0x1520E500' end='0x1520E520' type='altera_avalon_spi.spi_control_port' /><slave name='sys_gpio_bd.s1' start='0x1520E520' end='0x1520E530' type='altera_avalon_pio.s1' /><slave name='sys_timer_2nd.s1' start='0x1520E540' end='0x1520E560' type='altera_avalon_timer.s1' /><slave name='sys_cpu_interconnect.s0' start='0x20000000' end='0x21000000' type='altera_avalon_mm_bridge.s0' /></address-map>]]></parameter>
-  <parameter name="data_master_high_performance_paddr_base" value="0" />
-  <parameter name="data_master_high_performance_paddr_size" value="0" />
-  <parameter name="data_master_paddr_base" value="0" />
-  <parameter name="data_master_paddr_size" value="0" />
-  <parameter name="dcache_bursts" value="false" />
-  <parameter name="dcache_numTCDM" value="1" />
-  <parameter name="dcache_ramBlockType" value="Automatic" />
-  <parameter name="dcache_size" value="32768" />
-  <parameter name="dcache_tagramBlockType" value="Automatic" />
-  <parameter name="dcache_victim_buf_impl" value="ram" />
-  <parameter name="debug_OCIOnchipTrace" value="_128" />
-  <parameter name="debug_assignJtagInstanceID" value="false" />
-  <parameter name="debug_datatrigger" value="0" />
-  <parameter name="debug_debugReqSignals" value="false" />
-  <parameter name="debug_enabled" value="true" />
-  <parameter name="debug_hwbreakpoint" value="0" />
-  <parameter name="debug_jtagInstanceID" value="0" />
-  <parameter name="debug_traceStorage" value="onchip_trace" />
-  <parameter name="debug_traceType" value="none" />
-  <parameter name="debug_triggerArming" value="true" />
-  <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dividerType" value="no_div" />
-  <parameter name="exceptionOffset" value="32" />
-  <parameter name="exceptionSlave" value="sys_ddr3_cntrl.avl" />
-  <parameter name="faAddrWidth" value="1" />
-  <parameter name="faSlaveMapParam" value="" />
-  <parameter name="fa_cache_line" value="2" />
-  <parameter name="fa_cache_linesize" value="0" />
-  <parameter name="flash_instruction_master_paddr_base" value="0" />
-  <parameter name="flash_instruction_master_paddr_size" value="0" />
-  <parameter name="icache_burstType" value="None" />
-  <parameter name="icache_numTCIM" value="1" />
-  <parameter name="icache_ramBlockType" value="Automatic" />
-  <parameter name="icache_size" value="32768" />
-  <parameter name="icache_tagramBlockType" value="Automatic" />
-  <parameter name="impl" value="Fast" />
-  <parameter name="instAddrWidth" value="29" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s2' start='0x15000000' end='0x150C0000' type='altera_avalon_onchip_memory2.s2' /><slave name='sys_cpu.debug_mem_slave' start='0x1520D800' end='0x1520E000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
-  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
-  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
-  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
-  <parameter name="instruction_master_paddr_base" value="0" />
-  <parameter name="instruction_master_paddr_size" value="0" />
-  <parameter name="internalIrqMaskSystemInfo" value="65535" />
-  <parameter name="io_regionbase" value="0" />
-  <parameter name="io_regionsize" value="0" />
-  <parameter name="master_addr_map" value="false" />
-  <parameter name="mmu_TLBMissExcOffset" value="4096" />
-  <parameter name="mmu_TLBMissExcSlave" value="sys_int_mem.s2" />
-  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="true" />
-  <parameter name="mmu_processIDNumBits" value="8" />
-  <parameter name="mmu_ramBlockType" value="Automatic" />
-  <parameter name="mmu_tlbNumWays" value="16" />
-  <parameter name="mmu_tlbPtrSz" value="7" />
-  <parameter name="mmu_udtlbNumEntries" value="6" />
-  <parameter name="mmu_uitlbNumEntries" value="4" />
-  <parameter name="mpu_enabled" value="false" />
-  <parameter name="mpu_minDataRegionSize" value="12" />
-  <parameter name="mpu_minInstRegionSize" value="12" />
-  <parameter name="mpu_numOfDataRegion" value="8" />
-  <parameter name="mpu_numOfInstRegion" value="8" />
-  <parameter name="mpu_useLimit" value="false" />
-  <parameter name="mpx_enabled" value="false" />
-  <parameter name="mul_32_impl" value="3" />
-  <parameter name="mul_64_impl" value="0" />
-  <parameter name="mul_shift_choice" value="0" />
-  <parameter name="ocimem_ramBlockType" value="Automatic" />
-  <parameter name="ocimem_ramInit" value="false" />
-  <parameter name="regfile_ramBlockType" value="Automatic" />
-  <parameter name="resetOffset" value="0" />
-  <parameter name="resetSlave" value="sys_ddr3_cntrl.avl" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="setting_HBreakTest" value="false" />
-  <parameter name="setting_HDLSimCachesCleared" value="true" />
-  <parameter name="setting_activateMonitors" value="true" />
-  <parameter name="setting_activateTestEndChecker" value="false" />
-  <parameter name="setting_activateTrace" value="true" />
-  <parameter name="setting_allow_break_inst" value="false" />
-  <parameter name="setting_alwaysEncrypt" value="true" />
-  <parameter name="setting_asic_add_scan_mode_input" value="false" />
-  <parameter name="setting_asic_enabled" value="false" />
-  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
-  <parameter name="setting_asic_third_party_synthesis" value="false" />
-  <parameter name="setting_avalonDebugPortPresent" value="false" />
-  <parameter name="setting_bhtPtrSz" value="8" />
-  <parameter name="setting_bigEndian" value="false" />
-  <parameter name="setting_branchpredictiontype" value="Dynamic" />
-  <parameter name="setting_breakslaveoveride" value="false" />
-  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
-  <parameter name="setting_dc_ecc_present" value="false" />
-  <parameter name="setting_disable_tmr_inj" value="false" />
-  <parameter name="setting_disableocitrace" value="false" />
-  <parameter name="setting_dtcm_ecc_present" value="false" />
-  <parameter name="setting_ecc_present" value="false" />
-  <parameter name="setting_ecc_sim_test_ports" value="false" />
-  <parameter name="setting_exportHostDebugPort" value="false" />
-  <parameter name="setting_exportPCB" value="false" />
-  <parameter name="setting_export_large_RAMs" value="false" />
-  <parameter name="setting_exportdebuginfo" value="false" />
-  <parameter name="setting_exportvectors" value="false" />
-  <parameter name="setting_fast_register_read" value="false" />
-  <parameter name="setting_ic_ecc_present" value="true" />
-  <parameter name="setting_interruptControllerType" value="Internal" />
-  <parameter name="setting_itcm_ecc_present" value="false" />
-  <parameter name="setting_mmu_ecc_present" value="true" />
-  <parameter name="setting_oci_export_jtag_signals" value="false" />
-  <parameter name="setting_oci_version" value="1" />
-  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
-  <parameter name="setting_removeRAMinit" value="false" />
-  <parameter name="setting_rf_ecc_present" value="true" />
-  <parameter name="setting_shadowRegisterSets" value="0" />
-  <parameter name="setting_showInternalSettings" value="false" />
-  <parameter name="setting_showUnpublishedSettings" value="false" />
-  <parameter name="setting_support31bitdcachebypass" value="true" />
-  <parameter name="setting_usedesignware" value="false" />
-  <parameter name="shift_rot_impl" value="0" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x1520C000' end='0x1520D000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s2' start='0x1520C000' end='0x1520D000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
-  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
-  <parameter name="tmr_enabled" value="false" />
-  <parameter name="tracefilename" value="" />
-  <parameter name="userDefinedSettings" value="" />
- </module>
- <module
-   name="sys_cpu_interconnect"
-   kind="altera_avalon_mm_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="24" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="DATA_WIDTH" value="32" />
-  <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="MAX_PENDING_RESPONSES" value="4" />
-  <parameter name="PIPELINE_COMMAND" value="1" />
-  <parameter name="PIPELINE_RESPONSE" value="1" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
-  <parameter name="USE_RESPONSE" value="0" />
- </module>
- <module
-   name="sys_ddr3_cntrl"
-   kind="altera_mem_if_ddr3_emif"
-   version="15.1"
-   enabled="1">
-  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-  <parameter name="AC_PACKAGE_DESKEW" value="false" />
-  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-  <parameter name="ADDR_ORDER" value="0" />
-  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
-  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-  <parameter name="ADVANCED_CK_PHASES" value="false" />
-  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
-  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-  <parameter name="AP_MODE" value="false" />
-  <parameter name="AP_MODE_EN" value="0" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_PD_CYCLES" value="0" />
-  <parameter name="AUTO_POWERDN_EN" value="false" />
-  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-  <parameter name="AVL_MAX_SIZE" value="256" />
-  <parameter name="BYTE_ENABLE" value="true" />
-  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="CALIBRATION_MODE" value="Skip" />
-  <parameter name="CALIB_REG_WIDTH" value="8" />
-  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-  <parameter name="CFG_REORDER_DATA" value="true" />
-  <parameter name="CFG_TCCD_NS" value="2.5" />
-  <parameter name="COMMAND_PHASE" value="0.0" />
-  <parameter name="CONTROLLER_LATENCY" value="5" />
-  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
-  <parameter name="CTL_AUTOPCH_EN" value="false" />
-  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
-  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="CTL_CSR_ENABLED" value="false" />
-  <parameter name="CTL_CSR_READ_ONLY" value="1" />
-  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
-  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-  <parameter name="CTL_ECC_ENABLED" value="false" />
-  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
-  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
-  <parameter name="CTL_HRB_ENABLED" value="false" />
-  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTL_USR_REFRESH_EN" value="false" />
-  <parameter name="CTL_ZQCAL_EN" value="false" />
-  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
-  <parameter name="DAT_DATA_WIDTH" value="32" />
-  <parameter name="DEBUG_MODE" value="false" />
-  <parameter name="DEVICE_DEPTH" value="1" />
-  <parameter name="DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
-  <parameter name="DISCRETE_FLY_BY" value="true" />
-  <parameter name="DLL_SHARING_MODE" value="None" />
-  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
-  <parameter name="DUPLICATE_AC" value="false" />
-  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
-  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-  <parameter name="ENABLE_BONDING" value="false" />
-  <parameter name="ENABLE_BURST_MERGE" value="false" />
-  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
-  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
-  <parameter name="ENABLE_ISS_PROBES" value="false" />
-  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
-  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-  <parameter name="ENABLE_USER_ECC" value="false" />
-  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
-  <parameter name="EXTRA_SETTINGS" value="" />
-  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
-  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
-  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-  <parameter name="HARD_EMIF" value="false" />
-  <parameter name="HCX_COMPAT_MODE" value="false" />
-  <parameter name="HHP_HPS" value="false" />
-  <parameter name="HHP_HPS_SIMULATION" value="false" />
-  <parameter name="HHP_HPS_VERIFICATION" value="false" />
-  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
-  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="IS_ES_DEVICE" value="false" />
-  <parameter name="LOCAL_ID_WIDTH" value="8" />
-  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x0" />
-  <parameter name="MARGIN_VARIATION_TEST" value="false" />
-  <parameter name="MAX_PENDING_RD_CMD" value="32" />
-  <parameter name="MAX_PENDING_WR_CMD" value="16" />
-  <parameter name="MEM_ASR" value="Manual" />
-  <parameter name="MEM_ATCL" value="Disabled" />
-  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
-  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
-  <parameter name="MEM_BL" value="OTF" />
-  <parameter name="MEM_BT" value="Sequential" />
-  <parameter name="MEM_CK_PHASE" value="0.0" />
-  <parameter name="MEM_CK_WIDTH" value="1" />
-  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
-  <parameter name="MEM_CLK_FREQ" value="400.0" />
-  <parameter name="MEM_CLK_FREQ_MAX" value="666.667" />
-  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_CS_WIDTH" value="1" />
-  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
-  <parameter name="MEM_DLL_EN" value="true" />
-  <parameter name="MEM_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DQ_WIDTH" value="64" />
-  <parameter name="MEM_DRV_STR" value="RZQ/6" />
-  <parameter name="MEM_FORMAT" value="DISCRETE" />
-  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
-  <parameter name="MEM_IF_DQSN_EN" value="true" />
-  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-  <parameter name="MEM_INIT_EN" value="false" />
-  <parameter name="MEM_INIT_FILE" value="" />
-  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
-  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_PD" value="DLL off" />
-  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-  <parameter name="MEM_ROW_ADDR_WIDTH" value="12" />
-  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
-  <parameter name="MEM_RTT_WR" value="RZQ/4" />
-  <parameter name="MEM_SRT" value="Normal" />
-  <parameter name="MEM_TCL" value="11" />
-  <parameter name="MEM_TFAW_NS" value="30.0" />
-  <parameter name="MEM_TINIT_US" value="500" />
-  <parameter name="MEM_TMRD_CK" value="4" />
-  <parameter name="MEM_TRAS_NS" value="35.0" />
-  <parameter name="MEM_TRCD_NS" value="13.75" />
-  <parameter name="MEM_TREFI_US" value="7.8" />
-  <parameter name="MEM_TRFC_NS" value="110.0" />
-  <parameter name="MEM_TRP_NS" value="13.75" />
-  <parameter name="MEM_TRRD_NS" value="6.0" />
-  <parameter name="MEM_TRTP_NS" value="7.5" />
-  <parameter name="MEM_TWR_NS" value="15.0" />
-  <parameter name="MEM_TWTR" value="6" />
-  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
-  <parameter name="MEM_VENDOR" value="Micron" />
-  <parameter name="MEM_VERBOSE" value="true" />
-  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
-  <parameter name="MEM_WTCL" value="8" />
-  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-  <parameter name="MULTICAST_EN" value="false" />
-  <parameter name="NEXTGEN" value="true" />
-  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
-  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
-  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_OF_PORTS" value="1" />
-  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
-  <parameter name="OCT_SHARING_MODE" value="None" />
-  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="PACKAGE_DESKEW" value="false" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="PHY_CSR_ENABLED" value="false" />
-  <parameter name="PHY_ONLY" value="false" />
-  <parameter name="PINGPONGPHY_EN" value="false" />
-  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
-  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_LOCATION" value="Top_Bottom" />
-  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_SHARING_MODE" value="None" />
-  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="POWER_OF_TWO_BUS" value="false" />
-  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-  <parameter name="RATE" value="Quarter" />
-  <parameter name="RDIMM_CONFIG" value="0" />
-  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-  <parameter name="READ_FIFO_SIZE" value="8" />
-  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
-  <parameter name="REFRESH_INTERVAL" value="15000" />
-  <parameter name="REF_CLK_FREQ" value="100.0" />
-  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-  <parameter name="SEQUENCER_TYPE" value="NIOS" />
-  <parameter name="SEQ_MODE" value="0" />
-  <parameter name="SKIP_MEM_INIT" value="true" />
-  <parameter name="SOPC_COMPAT_RESET" value="false" />
-  <parameter name="SPEED_GRADE" value="3" />
-  <parameter name="STARVE_LIMIT" value="10" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
-  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_TDH" value="0.0" />
-  <parameter name="TIMING_BOARD_TDS" value="0.0" />
-  <parameter name="TIMING_BOARD_TIH" value="0.0" />
-  <parameter name="TIMING_BOARD_TIS" value="0.0" />
-  <parameter name="TIMING_TDH" value="45" />
-  <parameter name="TIMING_TDQSCK" value="255" />
-  <parameter name="TIMING_TDQSCKDL" value="1200" />
-  <parameter name="TIMING_TDQSCKDM" value="900" />
-  <parameter name="TIMING_TDQSCKDS" value="450" />
-  <parameter name="TIMING_TDQSQ" value="100" />
-  <parameter name="TIMING_TDQSS" value="0.27" />
-  <parameter name="TIMING_TDS" value="10" />
-  <parameter name="TIMING_TDSH" value="0.18" />
-  <parameter name="TIMING_TDSS" value="0.18" />
-  <parameter name="TIMING_TIH" value="120" />
-  <parameter name="TIMING_TIS" value="170" />
-  <parameter name="TIMING_TQH" value="0.38" />
-  <parameter name="TIMING_TQSH" value="0.4" />
-  <parameter name="TRACKING_ERROR_TEST" value="false" />
-  <parameter name="TRACKING_WATCH_TEST" value="false" />
-  <parameter name="TREFI" value="35100" />
-  <parameter name="TRFC" value="350" />
-  <parameter name="USER_DEBUG_LEVEL" value="1" />
-  <parameter name="USE_AXI_ADAPTOR" value="false" />
-  <parameter name="USE_FAKE_PHY" value="false" />
-  <parameter name="USE_MEM_CLK_FREQ" value="false" />
-  <parameter name="USE_MM_ADAPTOR" value="true" />
-  <parameter name="USE_SEQUENCER_BFM" value="false" />
-  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
- </module>
- <module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="core_variation" value="MAC_ONLY" />
-  <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="eg_addr" value="11" />
-  <parameter name="ena_hash" value="false" />
-  <parameter name="enable_alt_reconfig" value="false" />
-  <parameter name="enable_ecc" value="false" />
-  <parameter name="enable_ena" value="32" />
-  <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_hd_logic" value="true" />
-  <parameter name="enable_mac_flow_ctrl" value="true" />
-  <parameter name="enable_mac_vlan" value="false" />
-  <parameter name="enable_magic_detect" value="true" />
-  <parameter name="enable_ptp_1step" value="false" />
-  <parameter name="enable_sgmii" value="false" />
-  <parameter name="enable_shift16" value="true" />
-  <parameter name="enable_sup_addr" value="false" />
-  <parameter name="enable_timestamping" value="false" />
-  <parameter name="enable_use_internal_fifo" value="true" />
-  <parameter name="export_pwrdn" value="false" />
-  <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ifGMII" value="RGMII" />
-  <parameter name="ing_addr" value="11" />
-  <parameter name="max_channels" value="1" />
-  <parameter name="mdio_clk_div" value="30" />
-  <parameter name="nf_phyip_rcfg_enable" value="false" />
-  <parameter name="phy_identifier" value="0" />
-  <parameter name="phyip_en_synce_support" value="false" />
-  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
-  <parameter name="phyip_pll_type" value="CMU" />
-  <parameter name="phyip_pma_bonding_mode" value="x1" />
-  <parameter name="starting_channel_number" value="0" />
-  <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="transceiver_type" value="NONE" />
-  <parameter name="tstamp_fp_width" value="4" />
-  <parameter name="useMDIO" value="true" />
-  <parameter name="use_mac_clken" value="false" />
-  <parameter name="use_misc_ports" value="true" />
- </module>
- <module
-   name="sys_ethernet_dma_rx"
-   kind="altera_msgdma"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="6" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="2" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="0" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_ethernet_dma_tx"
-   kind="altera_msgdma"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="1" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="1" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="2" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module name="sys_gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_bd"
-   kind="altera_avalon_pio"
-   version="15.1"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="id" value="0" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="786432" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module name="sys_intr" kind="altera_irq_bridge" version="15.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
-  <parameter name="IRQ_N" value="0" />
-  <parameter name="IRQ_WIDTH" value="8" />
- </module>
- <module
-   name="sys_mem_interconnect"
-   kind="altera_avalon_mm_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="29" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="DATA_WIDTH" value="256" />
-  <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="64" />
-  <parameter name="MAX_PENDING_RESPONSES" value="4" />
-  <parameter name="PIPELINE_COMMAND" value="1" />
-  <parameter name="PIPELINE_RESPONSE" value="1" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="28" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
-  <parameter name="USE_RESPONSE" value="0" />
- </module>
- <module name="sys_pll" kind="altera_pll" version="15.1" enabled="1">
-  <parameter name="debug_print_output" value="false" />
-  <parameter name="debug_use_rbc_taf_method" value="false" />
-  <parameter name="device" value="5AGTFD7K3F40I3" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency1" value="166.666666 MHz" />
-  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
-  <parameter name="gui_actual_phase_shift0" value="0" />
-  <parameter name="gui_actual_phase_shift1" value="0" />
-  <parameter name="gui_actual_phase_shift10" value="0" />
-  <parameter name="gui_actual_phase_shift11" value="0" />
-  <parameter name="gui_actual_phase_shift12" value="0" />
-  <parameter name="gui_actual_phase_shift13" value="0" />
-  <parameter name="gui_actual_phase_shift14" value="0" />
-  <parameter name="gui_actual_phase_shift15" value="0" />
-  <parameter name="gui_actual_phase_shift16" value="0" />
-  <parameter name="gui_actual_phase_shift17" value="0" />
-  <parameter name="gui_actual_phase_shift2" value="0" />
-  <parameter name="gui_actual_phase_shift3" value="0" />
-  <parameter name="gui_actual_phase_shift4" value="0" />
-  <parameter name="gui_actual_phase_shift5" value="0" />
-  <parameter name="gui_actual_phase_shift6" value="0" />
-  <parameter name="gui_actual_phase_shift7" value="0" />
-  <parameter name="gui_actual_phase_shift8" value="0" />
-  <parameter name="gui_actual_phase_shift9" value="0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_channel_spacing" value="0.0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_device_speed_grade" value="2" />
-  <parameter name="gui_divide_factor_c0" value="1" />
-  <parameter name="gui_divide_factor_c1" value="1" />
-  <parameter name="gui_divide_factor_c10" value="1" />
-  <parameter name="gui_divide_factor_c11" value="1" />
-  <parameter name="gui_divide_factor_c12" value="1" />
-  <parameter name="gui_divide_factor_c13" value="1" />
-  <parameter name="gui_divide_factor_c14" value="1" />
-  <parameter name="gui_divide_factor_c15" value="1" />
-  <parameter name="gui_divide_factor_c16" value="1" />
-  <parameter name="gui_divide_factor_c17" value="1" />
-  <parameter name="gui_divide_factor_c2" value="1" />
-  <parameter name="gui_divide_factor_c3" value="1" />
-  <parameter name="gui_divide_factor_c4" value="1" />
-  <parameter name="gui_divide_factor_c5" value="1" />
-  <parameter name="gui_divide_factor_c6" value="1" />
-  <parameter name="gui_divide_factor_c7" value="1" />
-  <parameter name="gui_divide_factor_c8" value="1" />
-  <parameter name="gui_divide_factor_c9" value="1" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50" />
-  <parameter name="gui_duty_cycle1" value="50" />
-  <parameter name="gui_duty_cycle10" value="50" />
-  <parameter name="gui_duty_cycle11" value="50" />
-  <parameter name="gui_duty_cycle12" value="50" />
-  <parameter name="gui_duty_cycle13" value="50" />
-  <parameter name="gui_duty_cycle14" value="50" />
-  <parameter name="gui_duty_cycle15" value="50" />
-  <parameter name="gui_duty_cycle16" value="50" />
-  <parameter name="gui_duty_cycle17" value="50" />
-  <parameter name="gui_duty_cycle2" value="50" />
-  <parameter name="gui_duty_cycle3" value="50" />
-  <parameter name="gui_duty_cycle4" value="50" />
-  <parameter name="gui_duty_cycle5" value="50" />
-  <parameter name="gui_duty_cycle6" value="50" />
-  <parameter name="gui_duty_cycle7" value="50" />
-  <parameter name="gui_duty_cycle8" value="50" />
-  <parameter name="gui_duty_cycle9" value="50" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_number_of_clocks" value="4" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="125.0" />
-  <parameter name="gui_output_clock_frequency1" value="25.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="2.5" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0" />
-  <parameter name="gui_phase_shift1" value="0" />
-  <parameter name="gui_phase_shift10" value="0" />
-  <parameter name="gui_phase_shift11" value="0" />
-  <parameter name="gui_phase_shift12" value="0" />
-  <parameter name="gui_phase_shift13" value="0" />
-  <parameter name="gui_phase_shift14" value="0" />
-  <parameter name="gui_phase_shift15" value="0" />
-  <parameter name="gui_phase_shift16" value="0" />
-  <parameter name="gui_phase_shift17" value="0" />
-  <parameter name="gui_phase_shift2" value="0" />
-  <parameter name="gui_phase_shift3" value="0" />
-  <parameter name="gui_phase_shift4" value="0" />
-  <parameter name="gui_phase_shift5" value="0" />
-  <parameter name="gui_phase_shift6" value="0" />
-  <parameter name="gui_phase_shift7" value="0" />
-  <parameter name="gui_phase_shift8" value="0" />
-  <parameter name="gui_phase_shift9" value="0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="Off" />
-  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
-  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="100.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_locked" value="true" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="15.1" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="0" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="100000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="1" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="128000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
- <module
-   name="sys_tcm_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tcm_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="4096" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sys_timer"
-   kind="altera_avalon_timer"
-   version="15.1"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_timer_2nd"
-   kind="altera_avalon_timer"
-   version="15.1"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_uart"
-   kind="altera_avalon_jtag_uart"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowMultipleConnections" value="false" />
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="100000000" />
-  <parameter name="hubInstanceID" value="0" />
-  <parameter name="readBufferDepth" value="64" />
-  <parameter name="readIRQThreshold" value="8" />
-  <parameter name="simInputCharacterStream" value="" />
-  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
-  <parameter name="useRegistersForReadBuffer" value="false" />
-  <parameter name="useRegistersForWriteBuffer" value="false" />
-  <parameter name="useRelativePathForSimFile" value="false" />
-  <parameter name="writeBufferDepth" value="64" />
-  <parameter name="writeIRQThreshold" value="8" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_uart.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e4e0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet.control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e4d8" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e440" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520d800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e460" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e420" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.response">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e480" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_cpu_interconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x20000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x15000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e4c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_timer.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e4a0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio_bd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e520" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_timer_2nd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e540" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.data_master"
-   end="sys_spi.spi_control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520e500" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520d800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.instruction_master"
-   end="sys_int_mem.s2">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x15000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_mem_interconnect.m0"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_ethernet_dma_tx.mm_read"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_ethernet_dma_rx.mm_write"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.tightly_coupled_data_master_0"
-   end="sys_tcm_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520c000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_cpu.tightly_coupled_instruction_master_0"
-   end="sys_tcm_mem.s2">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1520c000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="sys_ethernet.receive"
-   end="sys_ethernet_dma_rx.st_sink" />
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="sys_ethernet_dma_tx.st_source"
-   end="sys_ethernet.transmit" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_ddr3_cntrl.afi_clk"
-   end="sys_mem_interconnect.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_ddr3_cntrl.afi_clk"
-   end="mem_clk.in_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_ddr3_cntrl.pll_ref_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_pll.refclk" />
- <connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_cpu.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_timer.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_timer_2nd.clk" />
- <connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_id.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_gpio.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_gpio_bd.clk" />
- <connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_spi.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_cpu_interconnect.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_uart.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_intr.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_tcm_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_int_mem.clk2" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_tcm_mem.clk2" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_ethernet_dma_rx.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_ethernet_dma_tx.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_ethernet.control_port_clock_connection" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="cpu_clk.in_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_ethernet.receive_clock_connection" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_pll.outclk3"
-   end="sys_ethernet.transmit_clock_connection" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_rx.csr_irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_tx.csr_irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_uart.irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_timer.irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection kind="interrupt" version="15.1" start="sys_cpu.irq" end="sys_spi.irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_gpio.irq">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_gpio_bd.irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_timer_2nd.irq">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_intr.sender0_irq">
-  <parameter name="irqNumber" value="15" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_intr.sender1_irq">
-  <parameter name="irqNumber" value="8" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_intr.sender2_irq">
-  <parameter name="irqNumber" value="9" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_intr.sender3_irq">
-  <parameter name="irqNumber" value="10" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_intr.sender4_irq">
-  <parameter name="irqNumber" value="11" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_intr.sender5_irq">
-  <parameter name="irqNumber" value="12" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_intr.sender6_irq">
-  <parameter name="irqNumber" value="13" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_cpu.irq"
-   end="sys_intr.sender7_irq">
-  <parameter name="irqNumber" value="14" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_ddr3_cntrl.afi_reset"
-   end="mem_rst.in_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_ddr3_cntrl.afi_reset"
-   end="sys_mem_interconnect.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_cpu.debug_reset_request"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_intr.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ddr3_cntrl.global_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="cpu_reset.in_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_uart.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_timer.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio_bd.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_spi.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_cpu_interconnect.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_timer_2nd.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_int_mem.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_tcm_mem.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_int_mem.reset2" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_tcm_mem.reset2" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet.reset_connection" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet_dma_rx.reset_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ethernet_dma_tx.reset_n" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_ddr3_cntrl.soft_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/common/a5gt/a5gt_system_qsys.tcl b/projects/common/a5gt/a5gt_system_qsys.tcl
new file mode 100644
index 000000000..5431f19d8
--- /dev/null
+++ b/projects/common/a5gt/a5gt_system_qsys.tcl
@@ -0,0 +1,325 @@
+
+package require qsys
+
+set_module_property NAME {system_bd}
+set_project_property DEVICE_FAMILY {Arria V}
+set_project_property DEVICE {5AGTFD7K3F40I3}
+
+set system_type nios
+
+# clock-&-reset
+
+add_instance sys_clk clock_source 16.0
+add_interface sys_clk clock sink
+add_interface sys_rst reset sink
+set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
+set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
+set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
+set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
+
+# memory (int)
+
+add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
+set_instance_parameter_value sys_int_mem {dataWidth} {32}
+set_instance_parameter_value sys_int_mem {dualPort} {0}
+set_instance_parameter_value sys_int_mem {initMemContent} {0}
+set_instance_parameter_value sys_int_mem {memorySize} {163840.0}
+add_connection sys_clk.clk sys_int_mem.clk1
+add_connection sys_clk.clk_reset sys_int_mem.reset1
+
+# memory (tlb)
+
+add_instance sys_tlb_mem altera_avalon_onchip_memory2 16.0
+set_instance_parameter_value sys_tlb_mem {dataWidth} {32}
+set_instance_parameter_value sys_tlb_mem {dualPort} {1}
+set_instance_parameter_value sys_tlb_mem {initMemContent} {1}
+set_instance_parameter_value sys_tlb_mem {memorySize} {163840.0}
+add_connection sys_clk.clk sys_tlb_mem.clk1
+add_connection sys_clk.clk_reset sys_tlb_mem.reset1
+add_connection sys_clk.clk sys_tlb_mem.clk2
+add_connection sys_clk.clk_reset sys_tlb_mem.reset2
+
+# memory (ddr)
+
+add_instance sys_ddr3_cntrl altera_mem_if_ddr3_emif 16.0
+set_instance_parameter_value sys_ddr3_cntrl {SPEED_GRADE} {3}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_CLK_FREQ} {400.0}
+set_instance_parameter_value sys_ddr3_cntrl {REF_CLK_FREQ} {100.0}
+set_instance_parameter_value sys_ddr3_cntrl {RATE} {Quarter}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_VENDOR} {Micron}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_CLK_FREQ_MAX} {666.667}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_DQ_WIDTH} {64}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_ROW_ADDR_WIDTH} {12}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_COL_ADDR_WIDTH} {10}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TCL} {11}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_RTT_NOM} {RZQ/6}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_WTCL} {8}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_RTT_WR} {RZQ/4}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TIS} {170}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TIH} {120}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDS} {10}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDH} {45}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSQ} {100}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TQH} {0.38}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSCK} {255}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSS} {0.27}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TQSH} {0.4}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDSH} {0.18}
+set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDSS} {0.18}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TINIT_US} {500}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TMRD_CK} {4}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TRAS_NS} {35.0}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TRCD_NS} {13.75}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TRP_NS} {13.75}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TREFI_US} {7.8}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TRFC_NS} {110.0}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TWR_NS} {15.0}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TWTR} {6}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TFAW_NS} {30.0}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TRRD_NS} {6.0}
+set_instance_parameter_value sys_ddr3_cntrl {MEM_TRTP_NS} {7.5}
+set_instance_parameter_value sys_ddr3_cntrl {AVL_MAX_SIZE} {256}
+add_connection sys_clk.clk sys_ddr3_cntrl.pll_ref_clk
+add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset
+add_connection sys_clk.clk_reset sys_ddr3_cntrl.soft_reset
+add_interface sys_ddr3_cntrl_mem conduit end
+set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.memory
+add_interface sys_ddr3_cntrl_oct conduit end
+set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct
+
+
+# cpu
+
+add_instance sys_cpu altera_nios2_gen2 16.0
+set_instance_parameter_value sys_cpu {setting_support31bitdcachebypass} {0}
+set_instance_parameter_value sys_cpu {setting_activateTrace} {1}
+set_instance_parameter_value sys_cpu {mmu_autoAssignTlbPtrSz} {0}
+set_instance_parameter_value sys_cpu {mmu_TLBMissExcOffset} {4096}
+set_instance_parameter_value sys_cpu {resetSlave} {sys_ddr3_cntrl.avl}
+set_instance_parameter_value sys_cpu {mmu_TLBMissExcSlave} {sys_tlb_mem.s2}
+set_instance_parameter_value sys_cpu {exceptionSlave} {sys_ddr3_cntrl.avl}
+set_instance_parameter_value sys_cpu {breakSlave} {sys_cpu.jtag_debug_module}
+set_instance_parameter_value sys_cpu {mul_32_impl} {3}
+set_instance_parameter_value sys_cpu {shift_rot_impl} {0}
+set_instance_parameter_value sys_cpu {icache_size} {32768}
+set_instance_parameter_value sys_cpu {icache_numTCIM} {1}
+set_instance_parameter_value sys_cpu {dcache_size} {32768}
+set_instance_parameter_value sys_cpu {dcache_numTCDM} {1}
+set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
+set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
+set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
+set_instance_parameter_value sys_cpu {mmu_enabled} $mmu_enabled
+add_connection sys_clk.clk sys_cpu.clk
+add_connection sys_clk.clk_reset sys_cpu.reset
+add_connection sys_cpu.debug_reset_request sys_cpu.reset
+add_connection sys_cpu.instruction_master sys_cpu.debug_mem_slave
+add_connection sys_cpu.instruction_master sys_int_mem.s1
+add_connection sys_cpu.tightly_coupled_instruction_master_0 sys_tlb_mem.s2
+add_connection sys_cpu.tightly_coupled_data_master_0 sys_tlb_mem.s1
+add_connection sys_cpu.instruction_master sys_ddr3_cntrl.avl
+add_connection sys_cpu.data_master sys_ddr3_cntrl.avl
+set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.avl baseAddress {0x0}
+set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.avl baseAddress {0x0}
+set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave baseAddress {0x10180800}
+set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1 baseAddress {0x10140000}
+set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2 baseAddress {0x10200000}
+set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1 baseAddress {0x10200000}
+
+# cpu/hps handling
+
+proc ad_cpu_interrupt {m_irq m_port} {
+
+  add_connection sys_cpu.irq ${m_port}
+  set_connection_parameter_value sys_cpu.irq/${m_port} irqNumber ${m_irq}
+}
+
+proc ad_cpu_interconnect {m_base m_port} {
+
+  add_connection sys_cpu.data_master ${m_port}
+  set_connection_parameter_value sys_cpu.data_master/${m_port} baseAddress [expr ($m_base + 0x10000000)]
+}
+
+proc ad_dma_interconnect {m_port} {
+
+  add_connection ${m_port} sys_ddr3_cntrl.avl
+  set_connection_parameter_value ${m_port}/sys_ddr3_cntrl.avl  baseAddress {0x0}
+}
+
+# common dma interfaces
+
+add_instance sys_dma_clk clock_source 16.0
+add_connection sys_ddr3_cntrl.afi_clk sys_dma_clk.clk_in
+add_connection sys_ddr3_cntrl.afi_reset sys_dma_clk.clk_in_reset
+
+# ethernet
+
+add_instance sys_ethernet altera_eth_tse 16.0
+set_instance_parameter_value sys_ethernet {core_variation} {MAC_ONLY}
+set_instance_parameter_value sys_ethernet {ifGMII} {RGMII}
+set_instance_parameter_value sys_ethernet {enable_mac_flow_ctrl} {1}
+set_instance_parameter_value sys_ethernet {useMDIO} {1}
+set_instance_parameter_value sys_ethernet {mdio_clk_div} {30}
+
+add_instance sys_ethernet_dma_rx altera_msgdma 16.0
+set_instance_parameter_value sys_ethernet_dma_rx {MODE} {2}
+set_instance_parameter_value sys_ethernet_dma_rx {DATA_WIDTH} {64}
+set_instance_parameter_value sys_ethernet_dma_rx {DATA_FIFO_DEPTH} {256}
+set_instance_parameter_value sys_ethernet_dma_rx {DESCRIPTOR_FIFO_DEPTH} {512}
+set_instance_parameter_value sys_ethernet_dma_rx {RESPONSE_PORT} {0}
+set_instance_parameter_value sys_ethernet_dma_rx {MAX_BYTE} {2048}
+set_instance_parameter_value sys_ethernet_dma_rx {TRANSFER_TYPE} {Unaligned Accesses}
+set_instance_parameter_value sys_ethernet_dma_rx {BURST_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_rx {MAX_BURST_COUNT} {64}
+set_instance_parameter_value sys_ethernet_dma_rx {ENHANCED_FEATURES} {1}
+set_instance_parameter_value sys_ethernet_dma_rx {PACKET_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_rx {ERROR_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_rx {ERROR_WIDTH} {6}
+
+add_instance sys_ethernet_dma_tx altera_msgdma 16.0
+set_instance_parameter_value sys_ethernet_dma_tx {MODE} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {DATA_WIDTH} {64}
+set_instance_parameter_value sys_ethernet_dma_tx {DATA_FIFO_DEPTH} {256}
+set_instance_parameter_value sys_ethernet_dma_tx {DESCRIPTOR_FIFO_DEPTH} {512}
+set_instance_parameter_value sys_ethernet_dma_tx {MAX_BYTE} {2048}
+set_instance_parameter_value sys_ethernet_dma_tx {TRANSFER_TYPE} {Unaligned Accesses}
+set_instance_parameter_value sys_ethernet_dma_tx {BURST_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {MAX_BURST_COUNT} {64}
+set_instance_parameter_value sys_ethernet_dma_tx {ENHANCED_FEATURES} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {PACKET_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {ERROR_ENABLE} {1}
+set_instance_parameter_value sys_ethernet_dma_tx {ERROR_WIDTH} {1}
+
+add_connection sys_clk.clk_reset sys_ethernet.reset_connection
+add_connection sys_clk.clk_reset sys_ethernet_dma_rx.reset_n
+add_connection sys_clk.clk_reset sys_ethernet_dma_tx.reset_n
+add_connection sys_clk.clk sys_ethernet.control_port_clock_connection
+add_connection sys_clk.clk sys_ethernet.receive_clock_connection
+add_connection sys_clk.clk sys_ethernet.transmit_clock_connection
+add_connection sys_clk.clk sys_ethernet_dma_rx.clock
+add_connection sys_clk.clk sys_ethernet_dma_tx.clock
+add_connection sys_ethernet.receive sys_ethernet_dma_rx.st_sink
+add_connection sys_ethernet_dma_tx.st_source sys_ethernet.transmit
+add_interface sys_ethernet_rx_clk clock sink
+add_interface sys_ethernet_tx_clk clock sink
+add_interface sys_ethernet_rgmii conduit end
+add_interface sys_ethernet_mdio conduit end
+add_interface sys_ethernet_status conduit end
+
+set_interface_property sys_ethernet_rx_clk EXPORT_OF sys_ethernet.pcs_mac_rx_clock_connection
+set_interface_property sys_ethernet_tx_clk EXPORT_OF sys_ethernet.pcs_mac_tx_clock_connection
+set_interface_property sys_ethernet_status EXPORT_OF sys_ethernet.mac_status_connection
+set_interface_property sys_ethernet_rgmii EXPORT_OF sys_ethernet.mac_rgmii_connection
+set_interface_property sys_ethernet_mdio EXPORT_OF sys_ethernet.mac_mdio_connection
+
+# sys-id
+
+add_instance sys_id altera_avalon_sysid_qsys 16.0
+set_instance_parameter_value sys_id {id} {182193580}
+add_connection sys_clk.clk_reset sys_id.reset
+add_connection sys_clk.clk sys_id.clk
+
+# timer-1
+
+add_instance sys_timer_1 altera_avalon_timer 16.0
+set_instance_parameter_value sys_timer_1 {counterSize} {32}
+add_connection sys_clk.clk_reset sys_timer_1.reset
+add_connection sys_clk.clk sys_timer_1.clk
+
+# timer-2
+
+add_instance sys_timer_2 altera_avalon_timer 16.0
+set_instance_parameter_value sys_timer_2 {counterSize} {32}
+add_connection sys_clk.clk_reset sys_timer_2.reset
+add_connection sys_clk.clk sys_timer_2.clk
+
+# uart
+
+add_instance sys_uart altera_avalon_jtag_uart 16.0
+set_instance_parameter_value sys_uart {allowMultipleConnections} {0}
+add_connection sys_clk.clk_reset sys_uart.reset
+add_connection sys_clk.clk sys_uart.clk
+
+# gpio-bd
+
+add_instance sys_gpio_bd altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_bd {direction} {InOut}
+set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_bd {width} {32}
+add_connection sys_clk.clk_reset sys_gpio_bd.reset
+add_connection sys_clk.clk sys_gpio_bd.clk
+add_interface sys_gpio_bd conduit end
+set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
+
+# gpio-in
+
+add_instance sys_gpio_in altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_in {direction} {Input}
+set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_in {width} {32}
+add_connection sys_clk.clk_reset sys_gpio_in.reset
+add_connection sys_clk.clk sys_gpio_in.clk
+add_interface sys_gpio_in conduit end
+set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
+
+# gpio-out
+
+add_instance sys_gpio_out altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_out {direction} {Output}
+set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
+set_instance_parameter_value sys_gpio_out {width} {32}
+add_connection sys_clk.clk_reset sys_gpio_out.reset
+add_connection sys_clk.clk sys_gpio_out.clk
+add_interface sys_gpio_out conduit end
+set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
+
+# spi
+
+add_instance sys_spi altera_avalon_spi 16.0
+set_instance_parameter_value sys_spi {clockPhase} {0}
+set_instance_parameter_value sys_spi {clockPolarity} {0}
+set_instance_parameter_value sys_spi {dataWidth} {8}
+set_instance_parameter_value sys_spi {masterSPI} {1}
+set_instance_parameter_value sys_spi {numberOfSlaves} {8}
+set_instance_parameter_value sys_spi {targetClockRate} {128000.0}
+add_connection sys_clk.clk_reset sys_spi.reset
+add_connection sys_clk.clk sys_spi.clk
+add_interface sys_spi conduit end
+set_interface_property sys_spi EXPORT_OF sys_spi.external
+
+# base-addresses
+
+ad_cpu_interconnect 0x00180800 sys_cpu.debug_mem_slave
+ad_cpu_interconnect 0x00140000 sys_int_mem.s1
+ad_cpu_interconnect 0x00181000 sys_ethernet.control_port
+ad_cpu_interconnect 0x001814a0 sys_ethernet_dma_rx.csr
+ad_cpu_interconnect 0x001814e0 sys_ethernet_dma_rx.response
+ad_cpu_interconnect 0x00181440 sys_ethernet_dma_rx.descriptor_slave
+ad_cpu_interconnect 0x00181480 sys_ethernet_dma_tx.csr
+ad_cpu_interconnect 0x00181460 sys_ethernet_dma_tx.descriptor_slave
+ad_cpu_interconnect 0x001814e8 sys_id.control_slave
+ad_cpu_interconnect 0x00181420 sys_timer_1.s1
+ad_cpu_interconnect 0x00181520 sys_timer_2.s1
+ad_cpu_interconnect 0x001814f0 sys_uart.avalon_jtag_slave
+ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1
+ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1
+ad_cpu_interconnect 0x00181500 sys_gpio_out.s1
+ad_cpu_interconnect 0x00181400 sys_spi.spi_control_port
+
+# dma interconnects
+
+ad_dma_interconnect sys_ethernet_dma_tx.mm_read
+ad_dma_interconnect sys_ethernet_dma_rx.mm_write
+
+# interrupts
+
+ad_cpu_interrupt 0 sys_ethernet_dma_rx.csr_irq
+ad_cpu_interrupt 1 sys_ethernet_dma_tx.csr_irq
+ad_cpu_interrupt 2 sys_uart.irq
+ad_cpu_interrupt 3 sys_timer_2.irq
+ad_cpu_interrupt 4 sys_timer_1.irq
+ad_cpu_interrupt 5 sys_gpio_in.irq
+ad_cpu_interrupt 6 sys_gpio_bd.irq
+ad_cpu_interrupt 7 sys_spi.irq
+
+

From c207589f4b04e6d1460c920c061fad873f30aaf7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Nov 2016 11:32:29 -0500
Subject: [PATCH 688/972] fmcjesdadc1/a5gt - qsys2tcl flow

---
 projects/fmcjesdadc1/a5gt/system_bd.qsys  | 462 ----------------------
 projects/fmcjesdadc1/a5gt/system_qsys.tcl |   6 +
 2 files changed, 6 insertions(+), 462 deletions(-)
 delete mode 100644 projects/fmcjesdadc1/a5gt/system_bd.qsys
 create mode 100644 projects/fmcjesdadc1/a5gt/system_qsys.tcl

diff --git a/projects/fmcjesdadc1/a5gt/system_bd.qsys b/projects/fmcjesdadc1/a5gt/system_bd.qsys
deleted file mode 100644
index 482a3db95..000000000
--- a/projects/fmcjesdadc1/a5gt/system_bd.qsys
+++ /dev/null
@@ -1,462 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element a5gt_base
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element a5gt_base.sys_mem_interconnect_s0
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element fmcjesdadc1.axi_ad9250_0_s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_ad9250_1_s_axi
-   {
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_dmac_0_s_axi
-   {
-      datum baseAddress
-      {
-         value = "212992";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_dmac_1_s_axi
-   {
-      datum baseAddress
-      {
-         value = "196608";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_jesd204_rx_avs
-   {
-      datum baseAddress
-      {
-         value = "262144";
-         type = "String";
-      }
-   }
-   element fmcjesdadc1.axi_jesd_xcvr_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5AGTFD7K3F40I3" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName">fmcjesdadc1_a5gt.qpf</parameter>
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="a5gt_base_sys_125m_clk"
-   internal="a5gt_base.sys_125m_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="a5gt_base_sys_25m_clk"
-   internal="a5gt_base.sys_25m_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="a5gt_base_sys_2m5_clk"
-   internal="a5gt_base.sys_2m5_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="a5gt_base_sys_ddr3_oct"
-   internal="a5gt_base.sys_ddr3_oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_ddr3_phy"
-   internal="a5gt_base.sys_ddr3_phy"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_ethernet_mdio"
-   internal="a5gt_base.sys_ethernet_mdio"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_ethernet_rgmii"
-   internal="a5gt_base.sys_ethernet_rgmii"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_ethernet_rx_clk"
-   internal="a5gt_base.sys_ethernet_rx_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_ethernet_status"
-   internal="a5gt_base.sys_ethernet_status"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_ethernet_tx_clk"
-   internal="a5gt_base.sys_ethernet_tx_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_gpio"
-   internal="a5gt_base.sys_gpio"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_gpio_bd"
-   internal="a5gt_base.sys_gpio_bd"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_pll_locked"
-   internal="a5gt_base.sys_pll_locked"
-   type="conduit"
-   dir="end" />
- <interface
-   name="a5gt_base_sys_spi"
-   internal="a5gt_base.sys_spi"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data"
-   internal="fmcjesdadc1.rx_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ref_clk"
-   internal="fmcjesdadc1.rx_ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="rx_sync"
-   internal="fmcjesdadc1.rx_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sysref"
-   internal="fmcjesdadc1.rx_sysref"
-   type="conduit"
-   dir="end" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_reset"
-   internal="sys_clk.clk_in_reset"
-   type="reset"
-   dir="end" />
- <module name="a5gt_base" kind="a5gt_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="7" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="7" />
-  <parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcjesdadc1_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='fmcjesdadc1_axi_ad9250_1.s_axi' start='0x10000' end='0x20000' /><slave name='fmcjesdadc1_axi_ad9250_0.s_axi' start='0x20000' end='0x30000' /><slave name='fmcjesdadc1_axi_dmac_1.s_axi' start='0x30000' end='0x34000' /><slave name='fmcjesdadc1_axi_dmac_0.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
-     value="AddressWidth = 18" />
-  <parameter name="AUTO_SYS_ETHERNET_RX_CLK_CLOCK_DOMAIN" value="4" />
-  <parameter name="AUTO_SYS_ETHERNET_RX_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_ETHERNET_RX_CLK_RESET_DOMAIN" value="4" />
-  <parameter name="AUTO_SYS_ETHERNET_TX_CLK_CLOCK_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_ETHERNET_TX_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_SYS_ETHERNET_TX_CLK_RESET_DOMAIN" value="5" />
-  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a5gt_base</parameter>
- </module>
- <module name="fmcjesdadc1" kind="fmcjesdadc1_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="AUTO_CPU_CLK_CLOCK_DOMAIN" value="9" />
-  <parameter name="AUTO_CPU_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_CPU_CLK_RESET_DOMAIN" value="9" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="10" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="10" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="6" />
-  <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcjesdadc1</parameter>
- </module>
- <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fmcjesdadc1.axi_dmac_0_m_axi"
-   end="a5gt_base.sys_mem_interconnect_s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fmcjesdadc1.axi_dmac_1_m_axi"
-   end="a5gt_base.sys_mem_interconnect_s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a5gt_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_ad9250_0_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a5gt_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_ad9250_1_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a5gt_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_dmac_0_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00034000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a5gt_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_dmac_1_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="a5gt_base.sys_cpu_interconnect_m0"
-   end="fmcjesdadc1.axi_jesd_xcvr_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.clk"
-   end="a5gt_base.sys_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="a5gt_base.cpu_clk"
-   end="fmcjesdadc1.cpu_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="a5gt_base.mem_clk"
-   end="fmcjesdadc1.mem_clk" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a5gt_base.sys_intr"
-   end="fmcjesdadc1.axi_dmac_0_intr">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="a5gt_base.sys_intr"
-   end="fmcjesdadc1.axi_dmac_1_intr">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="a5gt_base.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="a5gt_base.cpu_rst"
-   end="fmcjesdadc1.cpu_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="a5gt_base.mem_rst"
-   end="fmcjesdadc1.mem_rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/fmcjesdadc1/a5gt/system_qsys.tcl b/projects/fmcjesdadc1/a5gt/system_qsys.tcl
new file mode 100644
index 000000000..3537ec761
--- /dev/null
+++ b/projects/fmcjesdadc1/a5gt/system_qsys.tcl
@@ -0,0 +1,6 @@
+
+source $ad_hdl_dir/projects/common/a5soc/a5soc_system_qsys.tcl
+source ../common/fmcjesdadc1_qsys.tcl
+
+save_system "system_bd.qsys"
+

From c6730ab2d7583129fe9c5712450bc156b3b50d0c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Nov 2016 11:36:41 -0500
Subject: [PATCH 689/972] fmcjesdadc1/a5gt- updates

---
 projects/common/a5gt/a5gt_system_assign.tcl  | 11 ++---------
 projects/fmcjesdadc1/a5gt/system_project.tcl |  5 +----
 projects/fmcjesdadc1/a5gt/system_qsys.tcl    |  2 +-
 3 files changed, 4 insertions(+), 14 deletions(-)

diff --git a/projects/common/a5gt/a5gt_system_assign.tcl b/projects/common/a5gt/a5gt_system_assign.tcl
index c26253e51..c927eb62f 100644
--- a/projects/common/a5gt/a5gt_system_assign.tcl
+++ b/projects/common/a5gt/a5gt_system_assign.tcl
@@ -807,14 +807,7 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[24]
 set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[25]
 set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[26]
 
-# globals
-
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
-set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+# source defaults
 
+source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
 
diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl
index f186b6135..f1ac15489 100755
--- a/projects/fmcjesdadc1/a5gt/system_project.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_project.tcl
@@ -5,12 +5,10 @@ source ../../scripts/adi_env.tcl
 project_new fmcjesdadc1_a5gt -overwrite
 
 source "../../common/a5gt/a5gt_system_assign.tcl"
-set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
-set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
-set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
@@ -64,7 +62,6 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
 
 set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
 set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
-set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xcvr
 
 execute_flow -compile
 
diff --git a/projects/fmcjesdadc1/a5gt/system_qsys.tcl b/projects/fmcjesdadc1/a5gt/system_qsys.tcl
index 3537ec761..d0094590a 100644
--- a/projects/fmcjesdadc1/a5gt/system_qsys.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_qsys.tcl
@@ -1,5 +1,5 @@
 
-source $ad_hdl_dir/projects/common/a5soc/a5soc_system_qsys.tcl
+source $ad_hdl_dir/projects/common/a5gt/a5gt_system_qsys.tcl
 source ../common/fmcjesdadc1_qsys.tcl
 
 save_system "system_bd.qsys"

From 7a2c713a4ed2adf1b32da8260d256cf8f998c974 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Nov 2016 11:37:06 -0500
Subject: [PATCH 690/972] fmcjesdadc1/a5* - hdlmake.pl

---
 projects/fmcjesdadc1/a5gt/Makefile  | 59 ++++++++++++++++++++++++++++-
 projects/fmcjesdadc1/a5soc/Makefile |  1 +
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index 1d45efd24..f67ee312d 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -12,13 +12,68 @@ endif
 export ALT_NIOS_MMU_ENABLED := $(MMU)
 
 M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
-M_DEPS += system_bd.qsys
 M_DEPS += ../common/fmcjesdadc1_spi.v
+M_DEPS += ../common/fmcjesdadc1_qsys.tcl
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
+M_DEPS += ../../common/a5gt/a5gt_system_qsys.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
+M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
+M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v
+M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v
+M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl
+M_DEPS += ../../../library/axi_ad9250/axi_ad9250_if.v
+M_DEPS += ../../../library/axi_ad9250/axi_ad9250_pnmon.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axis_inf_rx.v
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_mem_asym.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 0e8d4771c..39f2ebcb6 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -53,6 +53,7 @@ M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
 M_DEPS += ../../../library/common/up_adc_channel.v

From 959055bd54b0a752abd916fe49ede2ac2f467631 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Nov 2016 16:56:35 -0500
Subject: [PATCH 691/972] common/a5gt- updates

---
 projects/common/a5gt/a5gt_system_assign.tcl | 108 ++++++++++----------
 projects/common/a5gt/a5gt_system_qsys.tcl   |  20 ++++
 2 files changed, 74 insertions(+), 54 deletions(-)

diff --git a/projects/common/a5gt/a5gt_system_assign.tcl b/projects/common/a5gt/a5gt_system_assign.tcl
index c927eb62f..0d9830885 100644
--- a/projects/common/a5gt/a5gt_system_assign.tcl
+++ b/projects/common/a5gt/a5gt_system_assign.tcl
@@ -751,61 +751,61 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_rx_clk
 
 # leds
 
-set_location_assignment PIN_M19   -to gpio_bd[0]    ; ## led_grn[0]
-set_location_assignment PIN_L19   -to gpio_bd[1]    ; ## led_grn[1]
-set_location_assignment PIN_K19   -to gpio_bd[2]    ; ## led_grn[2]
-set_location_assignment PIN_J19   -to gpio_bd[3]    ; ## led_grn[3]
-set_location_assignment PIN_K20   -to gpio_bd[4]    ; ## led_grn[4]
-set_location_assignment PIN_J20   -to gpio_bd[5]    ; ## led_grn[5]
-set_location_assignment PIN_T20   -to gpio_bd[6]    ; ## led_grn[6]
-set_location_assignment PIN_R20   -to gpio_bd[7]    ; ## led_grn[7]
-set_location_assignment PIN_N20   -to gpio_bd[8]    ; ## led_red[0]
-set_location_assignment PIN_C15   -to gpio_bd[9]    ; ## led_red[1]
-set_location_assignment PIN_AL28  -to gpio_bd[10]   ; ## led_red[2]
-set_location_assignment PIN_F11   -to gpio_bd[11]   ; ## led_red[3]
-set_location_assignment PIN_AJ31  -to gpio_bd[12]   ; ## led_red[4]
-set_location_assignment PIN_AN34  -to gpio_bd[13]   ; ## led_red[5]
-set_location_assignment PIN_AJ34  -to gpio_bd[14]   ; ## led_red[6]
-set_location_assignment PIN_AK33  -to gpio_bd[15]   ; ## led_red[7]
-set_location_assignment PIN_C8    -to gpio_bd[16]   ; ## dip_switches[0]
-set_location_assignment PIN_D8    -to gpio_bd[17]   ; ## dip_switches[1]
-set_location_assignment PIN_E7    -to gpio_bd[18]   ; ## dip_switches[2]
-set_location_assignment PIN_E6    -to gpio_bd[19]   ; ## dip_switches[3]
-set_location_assignment PIN_G8    -to gpio_bd[20]   ; ## dip_switches[4]
-set_location_assignment PIN_F8    -to gpio_bd[21]   ; ## dip_switches[5]
-set_location_assignment PIN_D15   -to gpio_bd[22]   ; ## dip_switches[6]
-set_location_assignment PIN_G11   -to gpio_bd[23]   ; ## dip_switches[7]
-set_location_assignment PIN_D6    -to gpio_bd[24]   ; ## push_buttons[0]
-set_location_assignment PIN_C6    -to gpio_bd[25]   ; ## push_buttons[1]
-set_location_assignment PIN_K7    -to gpio_bd[26]   ; ## push_buttons[2]
+set_location_assignment PIN_M19   -to gpio_bd_o[0]    ; ## led_grn[0]
+set_location_assignment PIN_L19   -to gpio_bd_o[1]    ; ## led_grn[1]
+set_location_assignment PIN_K19   -to gpio_bd_o[2]    ; ## led_grn[2]
+set_location_assignment PIN_J19   -to gpio_bd_o[3]    ; ## led_grn[3]
+set_location_assignment PIN_K20   -to gpio_bd_o[4]    ; ## led_grn[4]
+set_location_assignment PIN_J20   -to gpio_bd_o[5]    ; ## led_grn[5]
+set_location_assignment PIN_T20   -to gpio_bd_o[6]    ; ## led_grn[6]
+set_location_assignment PIN_R20   -to gpio_bd_o[7]    ; ## led_grn[7]
+set_location_assignment PIN_N20   -to gpio_bd_o[8]    ; ## led_red[0]
+set_location_assignment PIN_C15   -to gpio_bd_o[9]    ; ## led_red[1]
+set_location_assignment PIN_AL28  -to gpio_bd_o[10]   ; ## led_red[2]
+set_location_assignment PIN_F11   -to gpio_bd_o[11]   ; ## led_red[3]
+set_location_assignment PIN_AJ31  -to gpio_bd_o[12]   ; ## led_red[4]
+set_location_assignment PIN_AN34  -to gpio_bd_o[13]   ; ## led_red[5]
+set_location_assignment PIN_AJ34  -to gpio_bd_o[14]   ; ## led_red[6]
+set_location_assignment PIN_AK33  -to gpio_bd_o[15]   ; ## led_red[7]
+set_location_assignment PIN_C8    -to gpio_bd_i[0]    ; ## dip_switches[0]
+set_location_assignment PIN_D8    -to gpio_bd_i[1]    ; ## dip_switches[1]
+set_location_assignment PIN_E7    -to gpio_bd_i[2]    ; ## dip_switches[2]
+set_location_assignment PIN_E6    -to gpio_bd_i[3]    ; ## dip_switches[3]
+set_location_assignment PIN_G8    -to gpio_bd_i[4]    ; ## dip_switches[4]
+set_location_assignment PIN_F8    -to gpio_bd_i[5]    ; ## dip_switches[5]
+set_location_assignment PIN_D15   -to gpio_bd_i[6]    ; ## dip_switches[6]
+set_location_assignment PIN_G11   -to gpio_bd_i[7]    ; ## dip_switches[7]
+set_location_assignment PIN_D6    -to gpio_bd_i[8]    ; ## push_buttons[0]
+set_location_assignment PIN_C6    -to gpio_bd_i[9]    ; ## push_buttons[1]
+set_location_assignment PIN_K7    -to gpio_bd_i[10]   ; ## push_buttons[2]
 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[0] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[1] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[2] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[3] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[4] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[5] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[6] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[7] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[8] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[9] 
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[18]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[19]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[20]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[21]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[22]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[23]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[24]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[25]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[26]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[0] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[1] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[2] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[3] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[4] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[5] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[6] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[7] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[8] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[9] 
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[13]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[14]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[15]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[10]
 
 # source defaults
 
diff --git a/projects/common/a5gt/a5gt_system_qsys.tcl b/projects/common/a5gt/a5gt_system_qsys.tcl
index 5431f19d8..f79d4d802 100644
--- a/projects/common/a5gt/a5gt_system_qsys.tcl
+++ b/projects/common/a5gt/a5gt_system_qsys.tcl
@@ -18,6 +18,26 @@ set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
 set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
 set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
 
+# system-pll
+
+add_instance sys_pll altera_pll 16.0
+set_instance_parameter_value sys_pll {gui_reference_clock_frequency} {100.0}
+set_instance_parameter_value sys_pll {gui_use_locked} {1}
+set_instance_parameter_value sys_pll {gui_number_of_clocks} {3}
+set_instance_parameter_value sys_pll {gui_output_clock_frequency0} {125.0}
+set_instance_parameter_value sys_pll {gui_output_clock_frequency1} {25.0}
+set_instance_parameter_value sys_pll {gui_output_clock_frequency2} {2.5}
+add_connection sys_clk.clk sys_pll.refclk
+add_connection sys_clk.clk_reset sys_pll.reset
+add_interface sys_125m_clk clock source
+add_interface sys_25m_clk clock source
+add_interface sys_2m5_clk clock source
+add_interface sys_pll_locked conduit end
+set_interface_property sys_125m_clk EXPORT_OF sys_pll.outclk0
+set_interface_property sys_25m_clk EXPORT_OF sys_pll.outclk1
+set_interface_property sys_2m5_clk EXPORT_OF sys_pll.outclk2
+set_interface_property sys_pll_locked EXPORT_OF sys_pll.locked
+
 # memory (int)
 
 add_instance sys_int_mem altera_avalon_onchip_memory2 16.0

From 85eac8c811275ef0087f016d0df35c0f44e26ef7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 10 Nov 2016 16:57:06 -0500
Subject: [PATCH 692/972] fmcjesdadc1/a5*- updates

---
 projects/fmcjesdadc1/a5gt/system_constr.sdc |  30 ++-
 projects/fmcjesdadc1/a5gt/system_top.v      | 282 +++++++++-----------
 projects/fmcjesdadc1/a5soc/system_top.v     |   2 +-
 3 files changed, 152 insertions(+), 162 deletions(-)

diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc
index ce12d1393..347372ac5 100644
--- a/projects/fmcjesdadc1/a5gt/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc
@@ -1,17 +1,27 @@
 
-create_clock -period "10.000 ns"  -name sys_clk_100mhz        [get_ports {sys_clk}]
-create_clock -period "4.000 ns"   -name ref_clk_250mhz        [get_ports {ref_clk}]
-create_clock -period "8.000 ns"   -name eth_rx_clk_125mhz     [get_ports {eth_rx_clk}]
+create_clock -period "10.000 ns"  -name sys_clk        [get_ports {sys_clk}]
+create_clock -period "4.000 ns"   -name ref_clk        [get_ports {ref_clk}]
+create_clock -period "8.000 ns"   -name eth_rx_clk     [get_ports {eth_rx_clk}]
 
 derive_pll_clocks
 derive_clock_uncertainty
 
 set_clock_groups -exclusive \
-  -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-  -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-  -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
+
+set_false_path -to [get_registers {rx_sysref_m1}]
+
+set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\
+  -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
+
+set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
+  -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_clk}]
+
+set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
+
+set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk}]
 
-set_clock_groups -asynchronous \
-  -group {ref_clk_250mhz} \
-  -group [get_clocks {i_system_bd|fmcjesdadc1|xcvr_rx_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-  -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
diff --git a/projects/fmcjesdadc1/a5gt/system_top.v b/projects/fmcjesdadc1/a5gt/system_top.v
index 07a150ddb..169e9da1e 100644
--- a/projects/fmcjesdadc1/a5gt/system_top.v
+++ b/projects/fmcjesdadc1/a5gt/system_top.v
@@ -41,136 +41,85 @@ module system_top (
 
   // clock and resets
 
-  sys_clk,
-  sys_resetn,
+  input             sys_clk,
+  input             sys_resetn,
 
   // ddr3
 
-  ddr3_clk_p,
-  ddr3_clk_n,
-  ddr3_a,
-  ddr3_ba,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_odt,
-  ddr3_reset_n,
-  ddr3_we_n,
-  ddr3_ras_n,
-  ddr3_cas_n,
-  ddr3_dqs_p,
-  ddr3_dqs_n,
-  ddr3_dq,
-  ddr3_dm,
-  ddr3_rzq,
+  output            ddr3_clk_p,
+  output            ddr3_clk_n,
+  output  [ 13:0]   ddr3_a,
+  output  [  2:0]   ddr3_ba,
+  output            ddr3_cke,
+  output            ddr3_cs_n,
+  output            ddr3_odt,
+  output            ddr3_reset_n,
+  output            ddr3_we_n,
+  output            ddr3_ras_n,
+  output            ddr3_cas_n,
+  inout   [  7:0]   ddr3_dqs_p,
+  inout   [  7:0]   ddr3_dqs_n,
+  inout   [ 63:0]   ddr3_dq,
+  output  [  7:0]   ddr3_dm,
+  input             ddr3_rzq,
 
   // ethernet
 
-  eth_rx_clk,
-  eth_rx_data,
-  eth_rx_cntrl,
-  eth_tx_clk_out,
-  eth_tx_data,
-  eth_tx_cntrl,
-  eth_mdc,
-  eth_mdio_i,
-  eth_mdio_o,
-  eth_mdio_t,
-  eth_phy_resetn,
+  input             eth_rx_clk,
+  input   [  3:0]   eth_rx_data,
+  input             eth_rx_cntrl,
+  output            eth_tx_clk_out,
+  output  [  3:0]   eth_tx_data,
+  output            eth_tx_cntrl,
+  output            eth_mdc,
+  input             eth_mdio_i,
+  output            eth_mdio_o,
+  output            eth_mdio_t,
+  output            eth_phy_resetn,
 
   // board gpio
 
-  gpio_bd,
+  output  [ 15:0]   gpio_bd_o,
+  input   [ 10:0]   gpio_bd_i,
 
   // lane interface
 
-  ref_clk,
-  rx_data,
-  rx_sync,
-  rx_sysref,
+  input             ref_clk,
+  input   [  3:0]   rx_data,
+  output            rx_sync,
+  output            rx_sysref,
 
   // spi
 
-  spi_csn,
-  spi_clk,
-  spi_sdio);
-
-  // clock and resets
-
-  input             sys_clk;
-  input             sys_resetn;
-
-  // ddr3
-
-  output            ddr3_clk_p;
-  output            ddr3_clk_n;
-  output  [ 13:0]   ddr3_a;
-  output  [  2:0]   ddr3_ba;
-  output            ddr3_cke;
-  output            ddr3_cs_n;
-  output            ddr3_odt;
-  output            ddr3_reset_n;
-  output            ddr3_we_n;
-  output            ddr3_ras_n;
-  output            ddr3_cas_n;
-  inout   [  7:0]   ddr3_dqs_p;
-  inout   [  7:0]   ddr3_dqs_n;
-  inout   [ 63:0]   ddr3_dq;
-  output  [  7:0]   ddr3_dm;
-  input             ddr3_rzq;
-
-  // ethernet
-
-  input             eth_rx_clk;
-  input   [  3:0]   eth_rx_data;
-  input             eth_rx_cntrl;
-  output            eth_tx_clk_out;
-  output  [  3:0]   eth_tx_data;
-  output            eth_tx_cntrl;
-  output            eth_mdc;
-  input             eth_mdio_i;
-  output            eth_mdio_o;
-  output            eth_mdio_t;
-  output            eth_phy_resetn;
-
-  // board gpio
-
-  output  [ 26:0]   gpio_bd;
-
-  // lane interface
-
-  input             ref_clk;
-  input   [  3:0]   rx_data;
-  output            rx_sync;
-  output            rx_sysref;
-
-  // spi
-
-  output            spi_csn;
-  output            spi_clk;
-  inout             spi_sdio;
+  output            spi_csn,
+  output            spi_clk,
+  inout             spi_sdio);
 
   // internal registers
 
   reg     [  3:0]   phy_rst_cnt = 0;
   reg               phy_rst_reg = 0;
+  reg               rx_sysref_m1 = 'd0;
+  reg               rx_sysref_m2 = 'd0;
+  reg               rx_sysref_int = 'd0;
 
-  // internal clocks and resets
+  // internal signals
 
   wire              sys_125m_clk;
   wire              sys_25m_clk;
   wire              sys_2m5_clk;
-  wire              eth_tx_clk;
-  wire              rx_clk;
-
-  // internal signals
-
   wire              sys_pll_locked;
+  wire              eth_tx_clk;
   wire              eth_tx_mode_1g;
   wire              eth_tx_mode_10m_100m_n;
+  wire              rx_clk;
+  wire    [  3:0]   rx_ip_sof;
+  wire    [127:0]   rx_ip_data;
   wire              spi_mosi;
   wire              spi_miso;
   wire    [ 63:0]   gpio_i;
   wire    [ 63:0]   gpio_o;
+  wire    [  7:0]   spi_csn_s;
 
   // ethernet transmit clock
 
@@ -186,19 +135,34 @@ module system_top (
     end
   end
 
+  // gpio
+
+  assign gpio_i[63:11] = gpio_o[63:11];
+  assign gpio_i[10: 0] = gpio_bd_i;
+
+  assign gpio_bd_o = gpio_o[26:11];
+
+  // sysref
+
+  assign rx_sysref = rx_sysref_int;
+
+  always @(posedge rx_clk) begin
+    rx_sysref_m1 <= gpio_o[32];
+    rx_sysref_m2 <= rx_sysref_m1;
+    rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
+  end
+
+  // instantiations
+
+  assign spi_csn = spi_csn_s[0];
+
   fmcjesdadc1_spi i_fmcjesdadc1_spi (
-    .spi_csn (spi_csn),
+    .spi_csn (spi_csn_s[0]),
     .spi_clk (spi_clk),
     .spi_mosi (spi_mosi),
     .spi_miso (spi_miso),
     .spi_sdio (spi_sdio));
 
-  ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
-    .dio_t ({11'h7ff, 16'h0}),
-    .dio_i (gpio_o[26:0]),
-    .dio_o (gpio_i[26:0]),
-    .dio_p (gpio_bd));
-
   altddio_out #(.width(1)) i_eth_tx_clk_out (
     .aset (1'b0),
     .sset (1'b0),
@@ -213,54 +177,70 @@ module system_top (
     .dataout (eth_tx_clk_out));
 
   system_bd i_system_bd (
-    .a5gt_base_sys_ddr3_oct_rzqin (ddr3_rzq),
-    .a5gt_base_sys_ddr3_phy_mem_a (ddr3_a),
-    .a5gt_base_sys_ddr3_phy_mem_ba (ddr3_ba),
-    .a5gt_base_sys_ddr3_phy_mem_ck (ddr3_clk_p),
-    .a5gt_base_sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
-    .a5gt_base_sys_ddr3_phy_mem_cke (ddr3_cke),
-    .a5gt_base_sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
-    .a5gt_base_sys_ddr3_phy_mem_dm (ddr3_dm),
-    .a5gt_base_sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
-    .a5gt_base_sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
-    .a5gt_base_sys_ddr3_phy_mem_we_n (ddr3_we_n),
-    .a5gt_base_sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
-    .a5gt_base_sys_ddr3_phy_mem_dq (ddr3_dq),
-    .a5gt_base_sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
-    .a5gt_base_sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
-    .a5gt_base_sys_ddr3_phy_mem_odt (ddr3_odt),
-    .a5gt_base_sys_125m_clk_clk (sys_125m_clk),
-    .a5gt_base_sys_25m_clk_clk (sys_25m_clk),
-    .a5gt_base_sys_2m5_clk_clk (sys_2m5_clk),
-    .a5gt_base_sys_ethernet_mdio_mdc (eth_mdc),
-    .a5gt_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
-    .a5gt_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
-    .a5gt_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
-    .a5gt_base_sys_ethernet_rgmii_rgmii_in (eth_rx_data),
-    .a5gt_base_sys_ethernet_rgmii_rgmii_out (eth_tx_data),
-    .a5gt_base_sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
-    .a5gt_base_sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
-    .a5gt_base_sys_ethernet_rx_clk_clk (eth_rx_clk),
-    .a5gt_base_sys_ethernet_status_set_10 (),
-    .a5gt_base_sys_ethernet_status_set_1000 (),
-    .a5gt_base_sys_ethernet_status_eth_mode (eth_tx_mode_1g),
-    .a5gt_base_sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
-    .a5gt_base_sys_ethernet_tx_clk_clk (eth_tx_clk),
-    .a5gt_base_sys_gpio_in_port (gpio_i[63:32]),
-    .a5gt_base_sys_gpio_out_port (gpio_o[63:32]),
-    .a5gt_base_sys_gpio_bd_in_port (gpio_i[31:0]),
-    .a5gt_base_sys_gpio_bd_out_port (gpio_o[31:0]),
-    .a5gt_base_sys_pll_locked_export (sys_pll_locked),
-    .a5gt_base_sys_spi_MISO (spi_miso),
-    .a5gt_base_sys_spi_MOSI (spi_mosi),
-    .a5gt_base_sys_spi_SCLK (spi_clk),
-    .a5gt_base_sys_spi_SS_n (spi_csn),
-    .rx_data_rx_serial_data (rx_data),
+    .rx_core_clk_clk (rx_clk),
+    .rx_data_0_rx_serial_data (rx_data[0]),
+    .rx_data_1_rx_serial_data (rx_data[1]),
+    .rx_data_2_rx_serial_data (rx_data[2]),
+    .rx_data_3_rx_serial_data (rx_data[3]),
+    .rx_ip_data_data (rx_ip_data),
+    .rx_ip_data_valid (),
+    .rx_ip_data_ready (1'b1),
+    .rx_ip_data_0_data (rx_ip_data[63:0]),
+    .rx_ip_data_0_valid (1'b1),
+    .rx_ip_data_0_ready (),
+    .rx_ip_data_1_data (rx_ip_data[127:64]),
+    .rx_ip_data_1_valid (1'b1),
+    .rx_ip_data_1_ready (),
+    .rx_ip_sof_export (rx_ip_sof),
+    .rx_ip_sof_0_export (rx_ip_sof),
+    .rx_ip_sof_1_export (rx_ip_sof),
     .rx_ref_clk_clk (ref_clk),
-    .rx_sync_rx_sync (rx_sync),
-    .rx_sysref_rx_ext_sysref_out (rx_sysref),
+    .rx_sync_export (rx_sync),
+    .rx_sysref_export (rx_sysref_int),
+    .sys_125m_clk_clk (sys_125m_clk),
+    .sys_25m_clk_clk (sys_25m_clk),
+    .sys_2m5_clk_clk (sys_2m5_clk),
     .sys_clk_clk (sys_clk),
-    .sys_reset_reset_n (sys_resetn));
+    .sys_ddr3_cntrl_mem_mem_a (ddr3_a),
+    .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm),
+    .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq),
+    .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p),
+    .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n),
+    .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .sys_ddr3_cntrl_oct_rzqin (ddr3_rzq),
+    .sys_ethernet_mdio_mdc (eth_mdc),
+    .sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .sys_ethernet_rgmii_rgmii_in (eth_rx_data),
+    .sys_ethernet_rgmii_rgmii_out (eth_tx_data),
+    .sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
+    .sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
+    .sys_ethernet_rx_clk_clk (eth_rx_clk),
+    .sys_ethernet_status_set_10 (),
+    .sys_ethernet_status_set_1000 (),
+    .sys_ethernet_status_eth_mode (eth_tx_mode_1g),
+    .sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
+    .sys_ethernet_tx_clk_clk (eth_tx_clk),
+    .sys_gpio_bd_in_port (gpio_i[31:0]),
+    .sys_gpio_bd_out_port (gpio_o[31:0]),
+    .sys_gpio_in_export (gpio_i[63:32]),
+    .sys_gpio_out_export (gpio_o[63:32]),
+    .sys_pll_locked_export (sys_pll_locked),
+    .sys_rst_reset_n (sys_resetn),
+    .sys_spi_MISO (spi_miso),
+    .sys_spi_MOSI (spi_mosi),
+    .sys_spi_SCLK (spi_clk),
+    .sys_spi_SS_n (spi_csn_s));
 
 endmodule
 
diff --git a/projects/fmcjesdadc1/a5soc/system_top.v b/projects/fmcjesdadc1/a5soc/system_top.v
index b409dc062..f5accbcd5 100644
--- a/projects/fmcjesdadc1/a5soc/system_top.v
+++ b/projects/fmcjesdadc1/a5soc/system_top.v
@@ -159,7 +159,7 @@ module system_top (
   assign rx_sysref = rx_sysref_int;
 
   always @(posedge rx_clk) begin
-    rx_sysref_m1 <= gpio_o[12];
+    rx_sysref_m1 <= gpio_o[32];
     rx_sysref_m2 <= rx_sysref_m1;
     rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
   end

From 7008c641b59dae55fe7e1f8a9515b4745de99a0c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 11 Nov 2016 10:35:09 +0200
Subject: [PATCH 693/972] axi_adrv9371/zc706: Constraints update

From source *jesd_rstgen* is a false path for TX and RX_OS too.
---
 projects/adrv9371x/zc706/system_constr.xdc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/projects/adrv9371x/zc706/system_constr.xdc b/projects/adrv9371x/zc706/system_constr.xdc
index 49481db99..fa75a515d 100644
--- a/projects/adrv9371x/zc706/system_constr.xdc
+++ b/projects/adrv9371x/zc706/system_constr.xdc
@@ -75,4 +75,6 @@ create_clock -name rx_div_clk     -period  8.00 [get_pins i_system_wrapper/syste
 create_clock -name rx_os_div_clk  -period  8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 

From 6f4dc92dd2e5573305f915e00fd8010ae1a909a2 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 11 Nov 2016 15:46:17 +0200
Subject: [PATCH 694/972] util_fir_int: Fix channel data assignment

---
 library/util_fir_int/util_fir_int.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v
index 47ea8c566..183a41409 100644
--- a/library/util_fir_int/util_fir_int.v
+++ b/library/util_fir_int/util_fir_int.v
@@ -54,7 +54,7 @@ module util_fir_int (
   wire [31:0] m_axis_data_tdata_s;
   wire        s_axis_data_tready_s;
 
-  assign {channel_1, channel_0} = (interpolate == 1'b1) ? {m_axis_data_tdata_s[30:16], 1'b0, m_axis_data_tdata_s[14:0], 1'b0} : s_axis_data_tdata;
+  assign {channel_1, channel_0} = (interpolate == 1'b1) ? m_axis_data_tdata_s : s_axis_data_tdata;
   assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_s : dac_read;
 
   fir_interp interpolator (

From e62fe0c086121143eb63772c07098895cc1acf74 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Nov 2016 10:34:09 -0500
Subject: [PATCH 695/972] fmcjesdadc1- a5gt/a5soc- sysclk is different

---
 projects/fmcjesdadc1/a5soc/system_qsys.tcl       | 1 +
 projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcjesdadc1/a5soc/system_qsys.tcl b/projects/fmcjesdadc1/a5soc/system_qsys.tcl
index 3537ec761..72ef9d073 100644
--- a/projects/fmcjesdadc1/a5soc/system_qsys.tcl
+++ b/projects/fmcjesdadc1/a5soc/system_qsys.tcl
@@ -2,5 +2,6 @@
 source $ad_hdl_dir/projects/common/a5soc/a5soc_system_qsys.tcl
 source ../common/fmcjesdadc1_qsys.tcl
 
+set_instance_parameter_value avl_ad9250_xcvr {SYSCLK_FREQUENCY} {50.0}
 save_system "system_bd.qsys"
 
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
index 8b0c7fb14..14f2ab91e 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
@@ -6,7 +6,6 @@ set_instance_parameter_value avl_ad9250_xcvr {ID} {1}
 set_instance_parameter_value avl_ad9250_xcvr {TX_OR_RX_N} {0}
 set_instance_parameter_value avl_ad9250_xcvr {PCS_CONFIG} {JESD_PCS_CFG1}
 set_instance_parameter_value avl_ad9250_xcvr {LANE_RATE} {5000.0}
-set_instance_parameter_value avl_ad9250_xcvr {SYSCLK_FREQUENCY} {50.0}
 set_instance_parameter_value avl_ad9250_xcvr {PLLCLK_FREQUENCY} {2500.0}
 set_instance_parameter_value avl_ad9250_xcvr {REFCLK_FREQUENCY} {250.0}
 set_instance_parameter_value avl_ad9250_xcvr {CORECLK_FREQUENCY} {125.0}

From c80033cb1b6b25f5a736a063dcef68603486a0f1 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 11 Nov 2016 17:52:19 +0200
Subject: [PATCH 696/972] util_fir_int: removed s_axis_data_tvalid and updated
 sdrstk

---
 library/util_fir_int/util_fir_int.v | 3 +--
 projects/sdrstk/system_bd.tcl       | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v
index 183a41409..3cb7ddcad 100644
--- a/library/util_fir_int/util_fir_int.v
+++ b/library/util_fir_int/util_fir_int.v
@@ -42,7 +42,6 @@
 
 module util_fir_int (
   input               aclk,
-  input               s_axis_data_tvalid,
   output              s_axis_data_tready,
   input       [31:0]  s_axis_data_tdata,
   output      [15:0]  channel_0,
@@ -59,7 +58,7 @@ module util_fir_int (
 
   fir_interp interpolator (
     .aclk(aclk),
-    .s_axis_data_tvalid(s_axis_data_tvalid),
+    .s_axis_data_tvalid(1'b1),
     .s_axis_data_tready(s_axis_data_tready_s),
     .s_axis_data_tdata(s_axis_data_tdata),
     .m_axis_data_tvalid(m_axis_data_tvalid),
diff --git a/projects/sdrstk/system_bd.tcl b/projects/sdrstk/system_bd.tcl
index 61c72a602..aab659151 100644
--- a/projects/sdrstk/system_bd.tcl
+++ b/projects/sdrstk/system_bd.tcl
@@ -180,7 +180,7 @@ set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
-set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {32}] $axi_ad9361_dac_dma
 
@@ -228,7 +228,6 @@ ad_connect fir_decimator/decimate decim_slice/Dout
 
 ad_connect axi_ad9361/l_clk fir_interpolator/aclk
 ad_connect axi_ad9361_dac_dma/fifo_rd_dout fir_interpolator/s_axis_data_tdata
-ad_connect axi_ad9361_dac_dma/fifo_rd_valid fir_interpolator/s_axis_data_tvalid
 ad_connect axi_ad9361/dac_valid_i0 fir_interpolator/dac_read
 ad_connect axi_ad9361_dac_dma/fifo_rd_en fir_interpolator/s_axis_data_tready
 ad_connect axi_ad9361/dac_data_i0 fir_interpolator/channel_0

From 2ececad58c00cdf5e5df28d535412fd570df8010 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Nov 2016 13:49:04 -0500
Subject: [PATCH 697/972] sdrstk-2-pluto

---
 projects/{sdrstk => pluto}/Makefile           | 0
 projects/{sdrstk => pluto}/system_bd.tcl      | 0
 projects/{sdrstk => pluto}/system_constr.xdc  | 0
 projects/{sdrstk => pluto}/system_project.tcl | 0
 projects/{sdrstk => pluto}/system_top.v       | 0
 5 files changed, 0 insertions(+), 0 deletions(-)
 rename projects/{sdrstk => pluto}/Makefile (100%)
 rename projects/{sdrstk => pluto}/system_bd.tcl (100%)
 rename projects/{sdrstk => pluto}/system_constr.xdc (100%)
 rename projects/{sdrstk => pluto}/system_project.tcl (100%)
 rename projects/{sdrstk => pluto}/system_top.v (100%)

diff --git a/projects/sdrstk/Makefile b/projects/pluto/Makefile
similarity index 100%
rename from projects/sdrstk/Makefile
rename to projects/pluto/Makefile
diff --git a/projects/sdrstk/system_bd.tcl b/projects/pluto/system_bd.tcl
similarity index 100%
rename from projects/sdrstk/system_bd.tcl
rename to projects/pluto/system_bd.tcl
diff --git a/projects/sdrstk/system_constr.xdc b/projects/pluto/system_constr.xdc
similarity index 100%
rename from projects/sdrstk/system_constr.xdc
rename to projects/pluto/system_constr.xdc
diff --git a/projects/sdrstk/system_project.tcl b/projects/pluto/system_project.tcl
similarity index 100%
rename from projects/sdrstk/system_project.tcl
rename to projects/pluto/system_project.tcl
diff --git a/projects/sdrstk/system_top.v b/projects/pluto/system_top.v
similarity index 100%
rename from projects/sdrstk/system_top.v
rename to projects/pluto/system_top.v

From f64b44c8acb2e313e14a14cc418270094a23d3ba Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 11 Nov 2016 13:52:57 -0500
Subject: [PATCH 698/972] sdrstk2pluto- contents

---
 projects/pluto/Makefile           | 6 +++---
 projects/pluto/system_project.tcl | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/projects/pluto/Makefile b/projects/pluto/Makefile
index c13c4de3e..c7fd953ff 100644
--- a/projects/pluto/Makefile
+++ b/projects/pluto/Makefile
@@ -37,7 +37,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib sdrstk.sdk/system_top.hdf
+all: lib pluto.sdk/system_top.hdf
 
 
 clean: 
@@ -51,9 +51,9 @@ clean-all:clean
 	make -C ../../library/util_fir_int clean
 
 
-sdrstk.sdk/system_top.hdf: $(M_DEPS)
+pluto.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> sdrstk_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pluto_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pluto/system_project.tcl b/projects/pluto/system_project.tcl
index 97bd1b8d7..e2dc6281e 100644
--- a/projects/pluto/system_project.tcl
+++ b/projects/pluto/system_project.tcl
@@ -4,14 +4,14 @@ source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 set p_device "xc7z010clg225-1"
-adi_project_create sdrstk
+adi_project_create pluto
 
-adi_project_files sdrstk [list \
+adi_project_files pluto [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
 set_property is_enabled false [get_files  *system_sys_ps7_0.xdc]
-adi_project_run sdrstk
+adi_project_run pluto
 
 

From 12d6e46ae726d7331f7d3e0a9ebd5d0072f1072b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 14 Nov 2016 10:43:46 +0200
Subject: [PATCH 699/972] clean: Delete deprecated source files

The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located
at library/xilinx and library/altera.
The axi_jesd_xcvr was an early version of axi_adxcvr.
The register map is moved to the IP's directory.
---
 library/axi_jesd_gt/Makefile                  |   72 -
 library/axi_jesd_gt/axi_jesd_gt.v             | 1689 -----------------
 library/axi_jesd_gt/axi_jesd_gt_constr.xdc    |    5 -
 library/axi_jesd_gt/axi_jesd_gt_ip.tcl        |  194 --
 library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc |   19 -
 library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc |   19 -
 library/axi_jesd_xcvr/axi_jesd_xcvr.v         |  318 ----
 .../axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc    |   12 -
 library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl    |  142 --
 library/common/up_xcvr.v                      |  344 ----
 10 files changed, 2814 deletions(-)
 delete mode 100644 library/axi_jesd_gt/Makefile
 delete mode 100644 library/axi_jesd_gt/axi_jesd_gt.v
 delete mode 100644 library/axi_jesd_gt/axi_jesd_gt_constr.xdc
 delete mode 100644 library/axi_jesd_gt/axi_jesd_gt_ip.tcl
 delete mode 100644 library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc
 delete mode 100644 library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc
 delete mode 100644 library/axi_jesd_xcvr/axi_jesd_xcvr.v
 delete mode 100644 library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc
 delete mode 100755 library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
 delete mode 100644 library/common/up_xcvr.v

diff --git a/library/axi_jesd_gt/Makefile b/library/axi_jesd_gt/Makefile
deleted file mode 100644
index 4c3764e55..000000000
--- a/library/axi_jesd_gt/Makefile
+++ /dev/null
@@ -1,72 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS := axi_jesd_gt_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_gt_channel.v
-M_DEPS += ../common/ad_gt_common.v
-M_DEPS += ../common/ad_gt_es.v
-M_DEPS += ../common/ad_gt_es_axi.v
-M_DEPS += ../common/ad_gt_channel_1.v
-M_DEPS += ../common/ad_gt_common_1.v
-M_DEPS += ../common/ad_jesd_align.v
-M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/up_gt_channel.v
-M_DEPS += ../common/up_gt.v
-M_DEPS += axi_jesd_gt_tx_constr.xdc
-M_DEPS += axi_jesd_gt_rx_constr.xdc
-M_DEPS += axi_jesd_gt_constr.xdc
-M_DEPS += axi_jesd_gt.v
-M_DEPS += ../interfaces/if_gt_qpll.xml
-M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
-M_DEPS += ../interfaces/if_gt_pll.xml
-M_DEPS += ../interfaces/if_gt_pll_rtl.xml
-M_DEPS += ../interfaces/if_gt_rx.xml
-M_DEPS += ../interfaces/if_gt_rx_rtl.xml
-M_DEPS += ../interfaces/if_gt_rx_ksig.xml
-M_DEPS += ../interfaces/if_gt_rx_ksig_rtl.xml
-M_DEPS += ../interfaces/if_gt_tx.xml
-M_DEPS += ../interfaces/if_gt_tx_rtl.xml
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += component.xml
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.ip_user_files
-M_FLIST += *.srcs
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-
-
-
-.PHONY: all dep clean clean-all
-all: dep axi_jesd_gt.xpr
-
-
-clean:clean-all
-
-
-clean-all:
-	rm -rf $(M_FLIST)
-
-
-axi_jesd_gt.xpr: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) axi_jesd_gt_ip.tcl  >> axi_jesd_gt_ip.log 2>&1
-
-dep:
-	make -C ../interfaces
-####################################################################################
-####################################################################################
diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v
deleted file mode 100644
index bb9030060..000000000
--- a/library/axi_jesd_gt/axi_jesd_gt.v
+++ /dev/null
@@ -1,1689 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module axi_jesd_gt #(
-
-  parameter   integer ID = 0,
-  parameter   integer NUM_OF_LANES = 8,
-  parameter   integer GTH_OR_GTX_N = 0,
-  parameter   integer QPLL0_ENABLE = 1,
-  parameter   integer QPLL0_REFCLK_DIV = 1,
-  parameter   [26:0]  QPLL0_CFG = 27'h0680181,
-  parameter   integer QPLL0_FBDIV_RATIO = 1'b1,
-  parameter   [ 9:0]  QPLL0_FBDIV = 10'b0000110000,
-  parameter   integer QPLL1_ENABLE = 1,
-  parameter   integer QPLL1_REFCLK_DIV = 1,
-  parameter   [26:0]  QPLL1_CFG = 27'h0680181,
-  parameter   integer QPLL1_FBDIV_RATIO = 1'b1,
-  parameter   [ 9:0]  QPLL1_FBDIV = 10'b0000110000,
-
-  parameter   [31:0]  PMA_RSV_0 = 32'h001E7080,
-  parameter   integer CPLL_FBDIV_0  = 2,
-  parameter   [31:0]  PMA_RSV_1 = 32'h001E7080,
-  parameter   integer CPLL_FBDIV_1  = 2,
-  parameter   [31:0]  PMA_RSV_2 = 32'h001E7080,
-  parameter   integer CPLL_FBDIV_2  = 2,
-  parameter   [31:0]  PMA_RSV_3 = 32'h001E7080,
-  parameter   integer CPLL_FBDIV_3  = 2,
-  parameter   [31:0]  PMA_RSV_4 = 32'h001E7080,
-  parameter   integer CPLL_FBDIV_4  = 2,
-  parameter   [31:0]  PMA_RSV_5 = 32'h001E7080,
-  parameter   integer CPLL_FBDIV_5  = 2,
-  parameter   [31:0]  PMA_RSV_6 = 32'h001E7080,
-  parameter   integer CPLL_FBDIV_6  = 2,
-  parameter   [31:0]  PMA_RSV_7 = 32'h001E7080,
-  parameter   integer CPLL_FBDIV_7  = 2,
-
-  parameter   integer RX_NUM_OF_LANES = 8,
-  parameter   integer RX_OUT_DIV_0  = 1,
-  parameter   integer RX_CLK25_DIV_0  = 20,
-  parameter   integer RX_CLKBUF_ENABLE_0 = 1,
-  parameter   [71:0]  RX_CDR_CFG_0  = 72'h0b000023ff10400020,
-  parameter   integer RX_OUT_DIV_1  = 1,
-  parameter   integer RX_CLK25_DIV_1  = 20,
-  parameter   integer RX_CLKBUF_ENABLE_1 = 1,
-  parameter   [71:0]  RX_CDR_CFG_1  = 72'h0b000023ff10400020,
-  parameter   integer RX_OUT_DIV_2  = 1,
-  parameter   integer RX_CLK25_DIV_2  = 20,
-  parameter   integer RX_CLKBUF_ENABLE_2 = 1,
-  parameter   [71:0]  RX_CDR_CFG_2  = 72'h0b000023ff10400020,
-  parameter   integer RX_OUT_DIV_3  = 1,
-  parameter   integer RX_CLK25_DIV_3  = 20,
-  parameter   integer RX_CLKBUF_ENABLE_3 = 1,
-  parameter   [71:0]  RX_CDR_CFG_3  = 72'h0b000023ff10400020,
-  parameter   integer RX_OUT_DIV_4  = 1,
-  parameter   integer RX_CLK25_DIV_4  = 20,
-  parameter   integer RX_CLKBUF_ENABLE_4 = 1,
-  parameter   [71:0]  RX_CDR_CFG_4  = 72'h0b000023ff10400020,
-  parameter   integer RX_OUT_DIV_5  = 1,
-  parameter   integer RX_CLK25_DIV_5  = 20,
-  parameter   integer RX_CLKBUF_ENABLE_5 = 1,
-  parameter   [71:0]  RX_CDR_CFG_5  = 72'h0b000023ff10400020,
-  parameter   integer RX_OUT_DIV_6  = 1,
-  parameter   integer RX_CLK25_DIV_6  = 20,
-  parameter   integer RX_CLKBUF_ENABLE_6 = 1,
-  parameter   [71:0]  RX_CDR_CFG_6  = 72'h0b000023ff10400020,
-  parameter   integer RX_OUT_DIV_7  = 1,
-  parameter   integer RX_CLK25_DIV_7  = 20,
-  parameter   integer RX_CLKBUF_ENABLE_7 = 1,
-  parameter   [71:0]  RX_CDR_CFG_7  = 72'h0b000023ff10400020,
-
-  parameter   integer TX_NUM_OF_LANES = 8,
-  parameter   integer TX_OUT_DIV_0  = 1,
-  parameter   integer TX_CLK25_DIV_0  = 20,
-  parameter   integer TX_CLKBUF_ENABLE_0 = 1,
-  parameter   integer TX_DATA_SEL_0 = 0,
-  parameter   integer TX_OUT_DIV_1  = 1,
-  parameter   integer TX_CLK25_DIV_1  = 20,
-  parameter   integer TX_CLKBUF_ENABLE_1 = 1,
-  parameter   integer TX_DATA_SEL_1 = 1,
-  parameter   integer TX_OUT_DIV_2  = 1,
-  parameter   integer TX_CLK25_DIV_2  = 20,
-  parameter   integer TX_CLKBUF_ENABLE_2 = 1,
-  parameter   integer TX_DATA_SEL_2 = 2,
-  parameter   integer TX_OUT_DIV_3  = 1,
-  parameter   integer TX_CLK25_DIV_3  = 20,
-  parameter   integer TX_CLKBUF_ENABLE_3 = 1,
-  parameter   integer TX_DATA_SEL_3 = 3,
-  parameter   integer TX_OUT_DIV_4  = 1,
-  parameter   integer TX_CLK25_DIV_4  = 20,
-  parameter   integer TX_CLKBUF_ENABLE_4 = 1,
-  parameter   integer TX_DATA_SEL_4 = 4,
-  parameter   integer TX_OUT_DIV_5  = 1,
-  parameter   integer TX_CLK25_DIV_5  = 20,
-  parameter   integer TX_CLKBUF_ENABLE_5 = 1,
-  parameter   integer TX_DATA_SEL_5 = 5,
-  parameter   integer TX_OUT_DIV_6  = 1,
-  parameter   integer TX_CLK25_DIV_6  = 20,
-  parameter   integer TX_CLKBUF_ENABLE_6 = 1,
-  parameter   integer TX_DATA_SEL_6 = 6,
-  parameter   integer TX_OUT_DIV_7  = 1,
-  parameter   integer TX_CLK25_DIV_7  = 20,
-  parameter   integer TX_CLKBUF_ENABLE_7 = 1,
-  parameter   integer TX_DATA_SEL_7 = 7)
-
- (
-
-  // pll clocks
-
-  input                                       qpll0_rst,
-  input                                       qpll0_ref_clk_in,
-  input                                       qpll1_rst,
-  input                                       qpll1_ref_clk_in,
-
-  // pll resets
-
-  input                                       cpll_rst_m_0,
-  input                                       cpll_ref_clk_in_0,
-  input                                       cpll_rst_m_1,
-  input                                       cpll_ref_clk_in_1,
-  input                                       cpll_rst_m_2,
-  input                                       cpll_ref_clk_in_2,
-  input                                       cpll_rst_m_3,
-  input                                       cpll_ref_clk_in_3,
-  input                                       cpll_rst_m_4,
-  input                                       cpll_ref_clk_in_4,
-  input                                       cpll_rst_m_5,
-  input                                       cpll_ref_clk_in_5,
-  input                                       cpll_rst_m_6,
-  input                                       cpll_ref_clk_in_6,
-  input                                       cpll_rst_m_7,
-  input                                       cpll_ref_clk_in_7,
-
-  // channel interface (rx)
-
-  input                                       rx_0_p,
-  input                                       rx_0_n,
-  output                                      rx_rst_0,
-  input                                       rx_rst_m_0,
-  output                                      rx_pll_rst_0,
-  output                                      rx_gt_rst_0,
-  input                                       rx_gt_rst_m_0,
-  output                                      rx_pll_locked_0,
-  input                                       rx_pll_locked_m_0,
-  output                                      rx_user_ready_0,
-  input                                       rx_user_ready_m_0,
-  output                                      rx_rst_done_0,
-  input                                       rx_rst_done_m_0,
-  output                                      rx_out_clk_0,
-  input                                       rx_clk_0,
-  input                                       rx_sysref_0,
-  output                                      rx_sync_0,
-  output                                      rx_sof_0,
-  output  [31:0]                              rx_data_0,
-  output  [ 3:0]                              rx_gt_charisk_0,
-  output  [ 3:0]                              rx_gt_disperr_0,
-  output  [ 3:0]                              rx_gt_notintable_0,
-  output  [31:0]                              rx_gt_data_0,
-  input                                       rx_gt_comma_align_enb_0,
-  output  [ 3:0]                              rx_gt_ilas_f_0,
-  output  [ 3:0]                              rx_gt_ilas_q_0,
-  output  [ 3:0]                              rx_gt_ilas_a_0,
-  output  [ 3:0]                              rx_gt_ilas_r_0,
-  output  [ 3:0]                              rx_gt_cgs_k_0,
-  output                                      rx_ip_rst_0,
-  input   [ 3:0]                              rx_ip_sof_0,
-  input   [31:0]                              rx_ip_data_0,
-  output                                      rx_ip_sysref_0,
-  input                                       rx_ip_sync_0,
-  output                                      rx_ip_rst_done_0,
-
-  input                                       rx_1_p,
-  input                                       rx_1_n,
-  output                                      rx_rst_1,
-  input                                       rx_rst_m_1,
-  output                                      rx_pll_rst_1,
-  output                                      rx_gt_rst_1,
-  input                                       rx_gt_rst_m_1,
-  output                                      rx_pll_locked_1,
-  input                                       rx_pll_locked_m_1,
-  output                                      rx_user_ready_1,
-  input                                       rx_user_ready_m_1,
-  output                                      rx_rst_done_1,
-  input                                       rx_rst_done_m_1,
-  output                                      rx_out_clk_1,
-  input                                       rx_clk_1,
-  input                                       rx_sysref_1,
-  output                                      rx_sync_1,
-  output                                      rx_sof_1,
-  output  [31:0]                              rx_data_1,
-  output  [ 3:0]                              rx_gt_charisk_1,
-  output  [ 3:0]                              rx_gt_disperr_1,
-  output  [ 3:0]                              rx_gt_notintable_1,
-  output  [31:0]                              rx_gt_data_1,
-  input                                       rx_gt_comma_align_enb_1,
-  output  [ 3:0]                              rx_gt_ilas_f_1,
-  output  [ 3:0]                              rx_gt_ilas_q_1,
-  output  [ 3:0]                              rx_gt_ilas_a_1,
-  output  [ 3:0]                              rx_gt_ilas_r_1,
-  output  [ 3:0]                              rx_gt_cgs_k_1,
-  output                                      rx_ip_rst_1,
-  input   [ 3:0]                              rx_ip_sof_1,
-  input   [31:0]                              rx_ip_data_1,
-  output                                      rx_ip_sysref_1,
-  input                                       rx_ip_sync_1,
-  output                                      rx_ip_rst_done_1,
-
-  input                                       rx_2_p,
-  input                                       rx_2_n,
-  output                                      rx_rst_2,
-  input                                       rx_rst_m_2,
-  output                                      rx_pll_rst_2,
-  output                                      rx_gt_rst_2,
-  input                                       rx_gt_rst_m_2,
-  output                                      rx_pll_locked_2,
-  input                                       rx_pll_locked_m_2,
-  output                                      rx_user_ready_2,
-  input                                       rx_user_ready_m_2,
-  output                                      rx_rst_done_2,
-  input                                       rx_rst_done_m_2,
-  output                                      rx_out_clk_2,
-  input                                       rx_clk_2,
-  input                                       rx_sysref_2,
-  output                                      rx_sync_2,
-  output                                      rx_sof_2,
-  output  [31:0]                              rx_data_2,
-  output  [ 3:0]                              rx_gt_charisk_2,
-  output  [ 3:0]                              rx_gt_disperr_2,
-  output  [ 3:0]                              rx_gt_notintable_2,
-  output  [31:0]                              rx_gt_data_2,
-  input                                       rx_gt_comma_align_enb_2,
-  output  [ 3:0]                              rx_gt_ilas_f_2,
-  output  [ 3:0]                              rx_gt_ilas_q_2,
-  output  [ 3:0]                              rx_gt_ilas_a_2,
-  output  [ 3:0]                              rx_gt_ilas_r_2,
-  output  [ 3:0]                              rx_gt_cgs_k_2,
-  output                                      rx_ip_rst_2,
-  input   [ 3:0]                              rx_ip_sof_2,
-  input   [31:0]                              rx_ip_data_2,
-  output                                      rx_ip_sysref_2,
-  input                                       rx_ip_sync_2,
-  output                                      rx_ip_rst_done_2,
-
-  input                                       rx_3_p,
-  input                                       rx_3_n,
-  output                                      rx_rst_3,
-  input                                       rx_rst_m_3,
-  output                                      rx_pll_rst_3,
-  output                                      rx_gt_rst_3,
-  input                                       rx_gt_rst_m_3,
-  output                                      rx_pll_locked_3,
-  input                                       rx_pll_locked_m_3,
-  output                                      rx_user_ready_3,
-  input                                       rx_user_ready_m_3,
-  output                                      rx_rst_done_3,
-  input                                       rx_rst_done_m_3,
-  output                                      rx_out_clk_3,
-  input                                       rx_clk_3,
-  input                                       rx_sysref_3,
-  output                                      rx_sync_3,
-  output                                      rx_sof_3,
-  output  [31:0]                              rx_data_3,
-  output  [ 3:0]                              rx_gt_charisk_3,
-  output  [ 3:0]                              rx_gt_disperr_3,
-  output  [ 3:0]                              rx_gt_notintable_3,
-  output  [31:0]                              rx_gt_data_3,
-  input                                       rx_gt_comma_align_enb_3,
-  output  [ 3:0]                              rx_gt_ilas_f_3,
-  output  [ 3:0]                              rx_gt_ilas_q_3,
-  output  [ 3:0]                              rx_gt_ilas_a_3,
-  output  [ 3:0]                              rx_gt_ilas_r_3,
-  output  [ 3:0]                              rx_gt_cgs_k_3,
-  output                                      rx_ip_rst_3,
-  input   [ 3:0]                              rx_ip_sof_3,
-  input   [31:0]                              rx_ip_data_3,
-  output                                      rx_ip_sysref_3,
-  input                                       rx_ip_sync_3,
-  output                                      rx_ip_rst_done_3,
-
-  input                                       rx_4_p,
-  input                                       rx_4_n,
-  output                                      rx_rst_4,
-  input                                       rx_rst_m_4,
-  output                                      rx_pll_rst_4,
-  output                                      rx_gt_rst_4,
-  input                                       rx_gt_rst_m_4,
-  output                                      rx_pll_locked_4,
-  input                                       rx_pll_locked_m_4,
-  output                                      rx_user_ready_4,
-  input                                       rx_user_ready_m_4,
-  output                                      rx_rst_done_4,
-  input                                       rx_rst_done_m_4,
-  output                                      rx_out_clk_4,
-  input                                       rx_clk_4,
-  input                                       rx_sysref_4,
-  output                                      rx_sync_4,
-  output                                      rx_sof_4,
-  output  [31:0]                              rx_data_4,
-  output  [ 3:0]                              rx_gt_charisk_4,
-  output  [ 3:0]                              rx_gt_disperr_4,
-  output  [ 3:0]                              rx_gt_notintable_4,
-  output  [31:0]                              rx_gt_data_4,
-  input                                       rx_gt_comma_align_enb_4,
-  output  [ 3:0]                              rx_gt_ilas_f_4,
-  output  [ 3:0]                              rx_gt_ilas_q_4,
-  output  [ 3:0]                              rx_gt_ilas_a_4,
-  output  [ 3:0]                              rx_gt_ilas_r_4,
-  output  [ 3:0]                              rx_gt_cgs_k_4,
-  output                                      rx_ip_rst_4,
-  input   [ 3:0]                              rx_ip_sof_4,
-  input   [31:0]                              rx_ip_data_4,
-  output                                      rx_ip_sysref_4,
-  input                                       rx_ip_sync_4,
-  output                                      rx_ip_rst_done_4,
-
-  input                                       rx_5_p,
-  input                                       rx_5_n,
-  output                                      rx_rst_5,
-  input                                       rx_rst_m_5,
-  output                                      rx_pll_rst_5,
-  output                                      rx_gt_rst_5,
-  input                                       rx_gt_rst_m_5,
-  output                                      rx_pll_locked_5,
-  input                                       rx_pll_locked_m_5,
-  output                                      rx_user_ready_5,
-  input                                       rx_user_ready_m_5,
-  output                                      rx_rst_done_5,
-  input                                       rx_rst_done_m_5,
-  output                                      rx_out_clk_5,
-  input                                       rx_clk_5,
-  input                                       rx_sysref_5,
-  output                                      rx_sync_5,
-  output                                      rx_sof_5,
-  output  [31:0]                              rx_data_5,
-  output  [ 3:0]                              rx_gt_charisk_5,
-  output  [ 3:0]                              rx_gt_disperr_5,
-  output  [ 3:0]                              rx_gt_notintable_5,
-  output  [31:0]                              rx_gt_data_5,
-  input                                       rx_gt_comma_align_enb_5,
-  output  [ 3:0]                              rx_gt_ilas_f_5,
-  output  [ 3:0]                              rx_gt_ilas_q_5,
-  output  [ 3:0]                              rx_gt_ilas_a_5,
-  output  [ 3:0]                              rx_gt_ilas_r_5,
-  output  [ 3:0]                              rx_gt_cgs_k_5,
-  output                                      rx_ip_rst_5,
-  input   [ 3:0]                              rx_ip_sof_5,
-  input   [31:0]                              rx_ip_data_5,
-  output                                      rx_ip_sysref_5,
-  input                                       rx_ip_sync_5,
-  output                                      rx_ip_rst_done_5,
-
-  input                                       rx_6_p,
-  input                                       rx_6_n,
-  output                                      rx_rst_6,
-  input                                       rx_rst_m_6,
-  output                                      rx_pll_rst_6,
-  output                                      rx_gt_rst_6,
-  input                                       rx_gt_rst_m_6,
-  output                                      rx_pll_locked_6,
-  input                                       rx_pll_locked_m_6,
-  output                                      rx_user_ready_6,
-  input                                       rx_user_ready_m_6,
-  output                                      rx_rst_done_6,
-  input                                       rx_rst_done_m_6,
-  output                                      rx_out_clk_6,
-  input                                       rx_clk_6,
-  input                                       rx_sysref_6,
-  output                                      rx_sync_6,
-  output                                      rx_sof_6,
-  output  [31:0]                              rx_data_6,
-  output  [ 3:0]                              rx_gt_charisk_6,
-  output  [ 3:0]                              rx_gt_disperr_6,
-  output  [ 3:0]                              rx_gt_notintable_6,
-  output  [31:0]                              rx_gt_data_6,
-  input                                       rx_gt_comma_align_enb_6,
-  output  [ 3:0]                              rx_gt_ilas_f_6,
-  output  [ 3:0]                              rx_gt_ilas_q_6,
-  output  [ 3:0]                              rx_gt_ilas_a_6,
-  output  [ 3:0]                              rx_gt_ilas_r_6,
-  output  [ 3:0]                              rx_gt_cgs_k_6,
-  output                                      rx_ip_rst_6,
-  input   [ 3:0]                              rx_ip_sof_6,
-  input   [31:0]                              rx_ip_data_6,
-  output                                      rx_ip_sysref_6,
-  input                                       rx_ip_sync_6,
-  output                                      rx_ip_rst_done_6,
-
-  input                                       rx_7_p,
-  input                                       rx_7_n,
-  output                                      rx_rst_7,
-  input                                       rx_rst_m_7,
-  output                                      rx_pll_rst_7,
-  output                                      rx_gt_rst_7,
-  input                                       rx_gt_rst_m_7,
-  output                                      rx_pll_locked_7,
-  input                                       rx_pll_locked_m_7,
-  output                                      rx_user_ready_7,
-  input                                       rx_user_ready_m_7,
-  output                                      rx_rst_done_7,
-  input                                       rx_rst_done_m_7,
-  output                                      rx_out_clk_7,
-  input                                       rx_clk_7,
-  input                                       rx_sysref_7,
-  output                                      rx_sync_7,
-  output                                      rx_sof_7,
-  output  [31:0]                              rx_data_7,
-  output  [ 3:0]                              rx_gt_charisk_7,
-  output  [ 3:0]                              rx_gt_disperr_7,
-  output  [ 3:0]                              rx_gt_notintable_7,
-  output  [31:0]                              rx_gt_data_7,
-  input                                       rx_gt_comma_align_enb_7,
-  output  [ 3:0]                              rx_gt_ilas_f_7,
-  output  [ 3:0]                              rx_gt_ilas_q_7,
-  output  [ 3:0]                              rx_gt_ilas_a_7,
-  output  [ 3:0]                              rx_gt_ilas_r_7,
-  output  [ 3:0]                              rx_gt_cgs_k_7,
-  output                                      rx_ip_rst_7,
-  input   [ 3:0]                              rx_ip_sof_7,
-  input   [31:0]                              rx_ip_data_7,
-  output                                      rx_ip_sysref_7,
-  input                                       rx_ip_sync_7,
-  output                                      rx_ip_rst_done_7,
-
-  // channel interface (tx)
-
-  output                                      tx_0_p,
-  output                                      tx_0_n,
-  output                                      tx_rst_0,
-  input                                       tx_rst_m_0,
-  output                                      tx_pll_rst_0,
-  output                                      tx_gt_rst_0,
-  input                                       tx_gt_rst_m_0,
-  output                                      tx_pll_locked_0,
-  input                                       tx_pll_locked_m_0,
-  output                                      tx_user_ready_0,
-  input                                       tx_user_ready_m_0,
-  output                                      tx_rst_done_0,
-  input                                       tx_rst_done_m_0,
-  output                                      tx_out_clk_0,
-  input                                       tx_clk_0,
-  input                                       tx_sysref_0,
-  input                                       tx_sync_0,
-  input   [31:0]                              tx_data_0,
-  input   [ 3:0]                              tx_gt_charisk_0,
-  input   [31:0]                              tx_gt_data_0,
-  output                                      tx_ip_rst_0,
-  output  [31:0]                              tx_ip_data_0,
-  output                                      tx_ip_sysref_0,
-  output                                      tx_ip_sync_0,
-  output                                      tx_ip_rst_done_0,
-
-  output                                      tx_1_p,
-  output                                      tx_1_n,
-  output                                      tx_rst_1,
-  input                                       tx_rst_m_1,
-  output                                      tx_pll_rst_1,
-  output                                      tx_gt_rst_1,
-  input                                       tx_gt_rst_m_1,
-  output                                      tx_pll_locked_1,
-  input                                       tx_pll_locked_m_1,
-  output                                      tx_user_ready_1,
-  input                                       tx_user_ready_m_1,
-  output                                      tx_rst_done_1,
-  input                                       tx_rst_done_m_1,
-  output                                      tx_out_clk_1,
-  input                                       tx_clk_1,
-  input                                       tx_sysref_1,
-  input                                       tx_sync_1,
-  input   [31:0]                              tx_data_1,
-  input   [ 3:0]                              tx_gt_charisk_1,
-  input   [31:0]                              tx_gt_data_1,
-  output                                      tx_ip_rst_1,
-  output  [31:0]                              tx_ip_data_1,
-  output                                      tx_ip_sysref_1,
-  output                                      tx_ip_sync_1,
-  output                                      tx_ip_rst_done_1,
-
-  output                                      tx_2_p,
-  output                                      tx_2_n,
-  output                                      tx_rst_2,
-  input                                       tx_rst_m_2,
-  output                                      tx_pll_rst_2,
-  output                                      tx_gt_rst_2,
-  input                                       tx_gt_rst_m_2,
-  output                                      tx_pll_locked_2,
-  input                                       tx_pll_locked_m_2,
-  output                                      tx_user_ready_2,
-  input                                       tx_user_ready_m_2,
-  output                                      tx_rst_done_2,
-  input                                       tx_rst_done_m_2,
-  output                                      tx_out_clk_2,
-  input                                       tx_clk_2,
-  input                                       tx_sysref_2,
-  input                                       tx_sync_2,
-  input   [31:0]                              tx_data_2,
-  input   [ 3:0]                              tx_gt_charisk_2,
-  input   [31:0]                              tx_gt_data_2,
-  output                                      tx_ip_rst_2,
-  output  [31:0]                              tx_ip_data_2,
-  output                                      tx_ip_sysref_2,
-  output                                      tx_ip_sync_2,
-  output                                      tx_ip_rst_done_2,
-
-  output                                      tx_3_p,
-  output                                      tx_3_n,
-  output                                      tx_rst_3,
-  input                                       tx_rst_m_3,
-  output                                      tx_pll_rst_3,
-  output                                      tx_gt_rst_3,
-  input                                       tx_gt_rst_m_3,
-  output                                      tx_pll_locked_3,
-  input                                       tx_pll_locked_m_3,
-  output                                      tx_user_ready_3,
-  input                                       tx_user_ready_m_3,
-  output                                      tx_rst_done_3,
-  input                                       tx_rst_done_m_3,
-  output                                      tx_out_clk_3,
-  input                                       tx_clk_3,
-  input                                       tx_sysref_3,
-  input                                       tx_sync_3,
-  input   [31:0]                              tx_data_3,
-  input   [ 3:0]                              tx_gt_charisk_3,
-  input   [31:0]                              tx_gt_data_3,
-  output                                      tx_ip_rst_3,
-  output  [31:0]                              tx_ip_data_3,
-  output                                      tx_ip_sysref_3,
-  output                                      tx_ip_sync_3,
-  output                                      tx_ip_rst_done_3,
-
-  output                                      tx_4_p,
-  output                                      tx_4_n,
-  output                                      tx_rst_4,
-  input                                       tx_rst_m_4,
-  output                                      tx_pll_rst_4,
-  output                                      tx_gt_rst_4,
-  input                                       tx_gt_rst_m_4,
-  output                                      tx_pll_locked_4,
-  input                                       tx_pll_locked_m_4,
-  output                                      tx_user_ready_4,
-  input                                       tx_user_ready_m_4,
-  output                                      tx_rst_done_4,
-  input                                       tx_rst_done_m_4,
-  output                                      tx_out_clk_4,
-  input                                       tx_clk_4,
-  input                                       tx_sysref_4,
-  input                                       tx_sync_4,
-  input   [31:0]                              tx_data_4,
-  input   [ 3:0]                              tx_gt_charisk_4,
-  input   [31:0]                              tx_gt_data_4,
-  output                                      tx_ip_rst_4,
-  output  [31:0]                              tx_ip_data_4,
-  output                                      tx_ip_sysref_4,
-  output                                      tx_ip_sync_4,
-  output                                      tx_ip_rst_done_4,
-
-  output                                      tx_5_p,
-  output                                      tx_5_n,
-  output                                      tx_rst_5,
-  input                                       tx_rst_m_5,
-  output                                      tx_pll_rst_5,
-  output                                      tx_gt_rst_5,
-  input                                       tx_gt_rst_m_5,
-  output                                      tx_pll_locked_5,
-  input                                       tx_pll_locked_m_5,
-  output                                      tx_user_ready_5,
-  input                                       tx_user_ready_m_5,
-  output                                      tx_rst_done_5,
-  input                                       tx_rst_done_m_5,
-  output                                      tx_out_clk_5,
-  input                                       tx_clk_5,
-  input                                       tx_sysref_5,
-  input                                       tx_sync_5,
-  input   [31:0]                              tx_data_5,
-  input   [ 3:0]                              tx_gt_charisk_5,
-  input   [31:0]                              tx_gt_data_5,
-  output                                      tx_ip_rst_5,
-  output  [31:0]                              tx_ip_data_5,
-  output                                      tx_ip_sysref_5,
-  output                                      tx_ip_sync_5,
-  output                                      tx_ip_rst_done_5,
-
-  output                                      tx_6_p,
-  output                                      tx_6_n,
-  output                                      tx_rst_6,
-  input                                       tx_rst_m_6,
-  output                                      tx_pll_rst_6,
-  output                                      tx_gt_rst_6,
-  input                                       tx_gt_rst_m_6,
-  output                                      tx_pll_locked_6,
-  input                                       tx_pll_locked_m_6,
-  output                                      tx_user_ready_6,
-  input                                       tx_user_ready_m_6,
-  output                                      tx_rst_done_6,
-  input                                       tx_rst_done_m_6,
-  output                                      tx_out_clk_6,
-  input                                       tx_clk_6,
-  input                                       tx_sysref_6,
-  input                                       tx_sync_6,
-  input   [31:0]                              tx_data_6,
-  input   [ 3:0]                              tx_gt_charisk_6,
-  input   [31:0]                              tx_gt_data_6,
-  output                                      tx_ip_rst_6,
-  output  [31:0]                              tx_ip_data_6,
-  output                                      tx_ip_sysref_6,
-  output                                      tx_ip_sync_6,
-  output                                      tx_ip_rst_done_6,
-
-  output                                      tx_7_p,
-  output                                      tx_7_n,
-  output                                      tx_rst_7,
-  input                                       tx_rst_m_7,
-  output                                      tx_pll_rst_7,
-  output                                      tx_gt_rst_7,
-  input                                       tx_gt_rst_m_7,
-  output                                      tx_pll_locked_7,
-  input                                       tx_pll_locked_m_7,
-  output                                      tx_user_ready_7,
-  input                                       tx_user_ready_m_7,
-  output                                      tx_rst_done_7,
-  input                                       tx_rst_done_m_7,
-  output                                      tx_out_clk_7,
-  input                                       tx_clk_7,
-  input                                       tx_sysref_7,
-  input                                       tx_sync_7,
-  input   [31:0]                              tx_data_7,
-  input   [ 3:0]                              tx_gt_charisk_7,
-  input   [31:0]                              tx_gt_data_7,
-  output                                      tx_ip_rst_7,
-  output  [31:0]                              tx_ip_data_7,
-  output                                      tx_ip_sysref_7,
-  output                                      tx_ip_sync_7,
-  output                                      tx_ip_rst_done_7,
-
-  // axi - clock & reset
-
-  input                                       s_axi_aclk,
-  input                                       s_axi_aresetn,
-
-  // axi interface
-
-  input                                       s_axi_awvalid,
-  input   [ 31:0]                             s_axi_awaddr,
-  output                                      s_axi_awready,
-  input                                       s_axi_wvalid,
-  input   [ 31:0]                             s_axi_wdata,
-  input   [  3:0]                             s_axi_wstrb,
-  output                                      s_axi_wready,
-  output                                      s_axi_bvalid,
-  output  [  1:0]                             s_axi_bresp,
-  input                                       s_axi_bready,
-  input                                       s_axi_arvalid,
-  input   [ 31:0]                             s_axi_araddr,
-  output                                      s_axi_arready,
-  output                                      s_axi_rvalid,
-  output  [ 31:0]                             s_axi_rdata,
-  output  [  1:0]                             s_axi_rresp,
-  input                                       s_axi_rready,
-  input   [ 2:0]                              s_axi_awprot,
-  input   [ 2:0]                              s_axi_arprot,
-
-  // master interface
-
-  output                                      m_axi_awvalid,
-  output  [ 31:0]                             m_axi_awaddr,
-  output  [  2:0]                             m_axi_awprot,
-  input                                       m_axi_awready,
-  output                                      m_axi_wvalid,
-  output  [ 31:0]                             m_axi_wdata,
-  output  [  3:0]                             m_axi_wstrb,
-  input                                       m_axi_wready,
-  input                                       m_axi_bvalid,
-  input   [  1:0]                             m_axi_bresp,
-  output                                      m_axi_bready,
-  output                                      m_axi_arvalid,
-  output  [ 31:0]                             m_axi_araddr,
-  output  [  2:0]                             m_axi_arprot,
-  input                                       m_axi_arready,
-  input                                       m_axi_rvalid,
-  input   [ 31:0]                             m_axi_rdata,
-  input   [  1:0]                             m_axi_rresp,
-  output                                      m_axi_rready);
-
-  // post-processing
-  
-  localparam  [31:0]  PMA_RSV[7:0] = {PMA_RSV_7, PMA_RSV_6, PMA_RSV_5, PMA_RSV_4,
-    PMA_RSV_3, PMA_RSV_2, PMA_RSV_1, PMA_RSV_0};
-  localparam  integer CPLL_FBDIV[7:0] = {CPLL_FBDIV_7, CPLL_FBDIV_6, CPLL_FBDIV_5, CPLL_FBDIV_4,
-    CPLL_FBDIV_3, CPLL_FBDIV_2, CPLL_FBDIV_1, CPLL_FBDIV_0};
-
-  localparam  integer RX_OUT_DIV[7:0] = {RX_OUT_DIV_7, RX_OUT_DIV_6, RX_OUT_DIV_5,
-    RX_OUT_DIV_4, RX_OUT_DIV_3, RX_OUT_DIV_2, RX_OUT_DIV_1, RX_OUT_DIV_0};
-  localparam  integer RX_CLK25_DIV[7:0] = {RX_CLK25_DIV_7, RX_CLK25_DIV_6, RX_CLK25_DIV_5,
-    RX_CLK25_DIV_4, RX_CLK25_DIV_3, RX_CLK25_DIV_2, RX_CLK25_DIV_1, RX_CLK25_DIV_0};
-  localparam  integer RX_CLKBUF_ENABLE[7:0] = {RX_CLKBUF_ENABLE_7, RX_CLKBUF_ENABLE_6,
-    RX_CLKBUF_ENABLE_5, RX_CLKBUF_ENABLE_4, RX_CLKBUF_ENABLE_3,
-    RX_CLKBUF_ENABLE_2, RX_CLKBUF_ENABLE_1, RX_CLKBUF_ENABLE_0};
-  localparam  [71:0] RX_CDR_CFG[7:0] = {RX_CDR_CFG_7, RX_CDR_CFG_6, RX_CDR_CFG_5,
-    RX_CDR_CFG_4, RX_CDR_CFG_3, RX_CDR_CFG_2, RX_CDR_CFG_1, RX_CDR_CFG_0};
-
-  localparam  integer TX_OUT_DIV[7:0] = {TX_OUT_DIV_7, TX_OUT_DIV_6, TX_OUT_DIV_5,
-    TX_OUT_DIV_4, TX_OUT_DIV_3, TX_OUT_DIV_2, TX_OUT_DIV_1, TX_OUT_DIV_0};
-  localparam  integer TX_CLK25_DIV[7:0] = {TX_CLK25_DIV_7, TX_CLK25_DIV_6, TX_CLK25_DIV_5,
-    TX_CLK25_DIV_4, TX_CLK25_DIV_3, TX_CLK25_DIV_2, TX_CLK25_DIV_1, TX_CLK25_DIV_0};
-  localparam  integer TX_CLKBUF_ENABLE[7:0] = {TX_CLKBUF_ENABLE_7, TX_CLKBUF_ENABLE_6,
-    TX_CLKBUF_ENABLE_5, TX_CLKBUF_ENABLE_4, TX_CLKBUF_ENABLE_3,
-    TX_CLKBUF_ENABLE_2, TX_CLKBUF_ENABLE_1, TX_CLKBUF_ENABLE_0};
-  localparam  integer TX_DATA_SEL[7:0] = {TX_DATA_SEL_7, TX_DATA_SEL_6, TX_DATA_SEL_5,
-    TX_DATA_SEL_4, TX_DATA_SEL_3, TX_DATA_SEL_2, TX_DATA_SEL_1, TX_DATA_SEL_0};
-
-  // internal registers
-
-  reg                                         up_wack_d = 'd0;
-  reg                                         up_rack_d = 'd0;
-  reg     [ 31:0]                             up_rdata_d = 'd0;
-
-  // internal signals
-
-  wire    [(( 1*8)-1):0]                      qpll_clk;
-  wire    [(( 1*8)-1):0]                      qpll_ref_clk;
-  wire    [(( 1*8)-1):0]                      qpll_locked;
-  wire    [(( 1*8)-1):0]                      cpll_rst_m;
-  wire    [(( 1*8)-1):0]                      cpll_ref_clk_in;
-  wire    [(( 1*8)-1):0]                      rx_p;
-  wire    [(( 1*8)-1):0]                      rx_n;
-  wire    [(( 1*8)-1):0]                      rx_out_clk;
-  wire    [(( 1*8)-1):0]                      rx_clk;
-  wire    [(( 1*8)-1):0]                      rx_rst;
-  wire    [(( 1*8)-1):0]                      rx_sof;
-  wire    [((32*8)-1):0]                      rx_data;
-  wire    [(( 1*8)-1):0]                      rx_sysref;
-  wire    [(( 1*8)-1):0]                      rx_sync;
-  wire    [(( 4*8)-1):0]                      rx_gt_charisk;
-  wire    [(( 4*8)-1):0]                      rx_gt_disperr;
-  wire    [(( 4*8)-1):0]                      rx_gt_notintable;
-  wire    [((32*8)-1):0]                      rx_gt_data;
-  wire    [(( 1*8)-1):0]                      rx_gt_comma_align_enb;
-  wire    [(( 4*8)-1):0]                      rx_gt_ilas_f;
-  wire    [(( 4*8)-1):0]                      rx_gt_ilas_q;
-  wire    [(( 4*8)-1):0]                      rx_gt_ilas_a;
-  wire    [(( 4*8)-1):0]                      rx_gt_ilas_r;
-  wire    [(( 4*8)-1):0]                      rx_gt_cgs_k;
-  wire    [(( 1*8)-1):0]                      rx_ip_rst;
-  wire    [(( 4*8)-1):0]                      rx_ip_sof;
-  wire    [((32*8)-1):0]                      rx_ip_data;
-  wire    [(( 1*8)-1):0]                      rx_ip_sysref;
-  wire    [(( 1*8)-1):0]                      rx_ip_sync;
-  wire    [(( 1*8)-1):0]                      rx_ip_rst_done;
-  wire    [(( 1*8)-1):0]                      rx_rst_m;
-  wire    [(( 1*8)-1):0]                      rx_pll_rst;
-  wire    [(( 1*8)-1):0]                      rx_gt_rst;
-  wire    [(( 1*8)-1):0]                      rx_gt_rst_m;
-  wire    [(( 1*8)-1):0]                      rx_user_ready;
-  wire    [(( 1*8)-1):0]                      rx_rst_done_m;
-  wire    [(( 1*8)-1):0]                      rx_pll_locked_m;
-  wire    [(( 1*8)-1):0]                      rx_user_ready_m;
-  wire    [(( 1*8)-1):0]                      rx_rst_done;
-  wire    [(( 1*8)-1):0]                      rx_pll_locked;
-  wire    [(( 1*8)-1):0]                      tx_p;
-  wire    [(( 1*8)-1):0]                      tx_n;
-  wire    [(( 1*8)-1):0]                      tx_out_clk;
-  wire    [(( 1*8)-1):0]                      tx_clk;
-  wire    [(( 1*8)-1):0]                      tx_rst;
-  wire    [((32*8)-1):0]                      tx_data;
-  wire    [(( 1*8)-1):0]                      tx_sysref;
-  wire    [(( 1*8)-1):0]                      tx_sync;
-  wire    [(( 4*8)-1):0]                      tx_gt_charisk;
-  wire    [((32*8)-1):0]                      tx_gt_data;
-  wire    [(( 1*8)-1):0]                      tx_ip_rst;
-  wire    [((32*8)-1):0]                      tx_ip_data;
-  wire    [(( 1*8)-1):0]                      tx_ip_sysref;
-  wire    [(( 1*8)-1):0]                      tx_ip_sync;
-  wire    [(( 1*8)-1):0]                      tx_ip_rst_done;
-  wire    [(( 1*8)-1):0]                      tx_rst_m;
-  wire    [(( 1*8)-1):0]                      tx_pll_rst;
-  wire    [(( 1*8)-1):0]                      tx_gt_rst;
-  wire    [(( 1*8)-1):0]                      tx_gt_rst_m;
-  wire    [(( 1*8)-1):0]                      tx_user_ready;
-  wire    [(( 1*8)-1):0]                      tx_rst_done_m;
-  wire    [(( 1*8)-1):0]                      tx_pll_locked_m;
-  wire    [(( 1*8)-1):0]                      tx_user_ready_m;
-  wire    [(( 1*8)-1):0]                      tx_rst_done;
-  wire    [(( 1*8)-1):0]                      tx_pll_locked;
-  wire                                        up_rstn;
-  wire                                        up_clk;
-  wire                                        up_wreq;
-  wire    [((14*1)-1):0]                      up_waddr;
-  wire    [((32*1)-1):0]                      up_wdata;
-  wire    [(( 1*9)-1):0]                      up_wack;
-  wire                                        up_rreq;
-  wire    [((14*1)-1):0]                      up_raddr;
-  wire    [((32*9)-1):0]                      up_rdata;
-  wire    [(( 1*9)-1):0]                      up_rack;
-  wire    [(( 1*8)-1):0]                      up_es_dma_req;
-  wire    [((32*8)-1):0]                      up_es_dma_addr;
-  wire    [((32*8)-1):0]                      up_es_dma_data;
-  wire    [(( 1*8)-1):0]                      up_es_dma_ack;
-  wire    [(( 1*8)-1):0]                      up_es_dma_err;
-
-  // signal name changes
-
-  assign up_rstn = s_axi_aresetn;
-  assign up_clk = s_axi_aclk;
-
-  // pll 
-
-  assign cpll_rst_m[0] = cpll_rst_m_0;
-  assign cpll_ref_clk_in[0] = cpll_ref_clk_in_0; 
-
-  assign cpll_rst_m[1] = cpll_rst_m_1;
-  assign cpll_ref_clk_in[1] = cpll_ref_clk_in_1;
-
-  assign cpll_rst_m[2] = cpll_rst_m_2;
-  assign cpll_ref_clk_in[2] = cpll_ref_clk_in_2;
-
-  assign cpll_rst_m[3] = cpll_rst_m_3;
-  assign cpll_ref_clk_in[3] = cpll_ref_clk_in_3;
-
-  assign cpll_rst_m[4] = cpll_rst_m_4;
-  assign cpll_ref_clk_in[4] = cpll_ref_clk_in_4;
-
-  assign cpll_rst_m[5] = cpll_rst_m_5;
-  assign cpll_ref_clk_in[5] = cpll_ref_clk_in_5;
-
-  assign cpll_rst_m[6] = cpll_rst_m_6;
-  assign cpll_ref_clk_in[6] = cpll_ref_clk_in_6;
-
-  assign cpll_rst_m[7] = cpll_rst_m_7;
-  assign cpll_ref_clk_in[7] = cpll_ref_clk_in_7;
-
-  // split-up interfaces
-
-  assign rx_out_clk_0 = rx_out_clk[0];
-  assign rx_rst_0 = rx_rst[0];
-  assign rx_sof_0 = rx_sof[0];
-  assign rx_data_0 = rx_data[((32*0)+31):(32*0)];
-  assign rx_sync_0 = rx_sync[0];
-  assign rx_gt_charisk_0 = rx_gt_charisk[((4*0)+3):(4*0)];
-  assign rx_gt_disperr_0 = rx_gt_disperr[((4*0)+3):(4*0)];
-  assign rx_gt_notintable_0 = rx_gt_notintable[((4*0)+3):(4*0)];
-  assign rx_gt_data_0 = rx_gt_data[((32*0)+31):(32*0)];
-  assign rx_gt_ilas_f_0 = rx_gt_ilas_f[((4*0)+3):(4*0)];
-  assign rx_gt_ilas_q_0 = rx_gt_ilas_q[((4*0)+3):(4*0)];
-  assign rx_gt_ilas_a_0 = rx_gt_ilas_a[((4*0)+3):(4*0)];
-  assign rx_gt_ilas_r_0 = rx_gt_ilas_r[((4*0)+3):(4*0)];
-  assign rx_gt_cgs_k_0 = rx_gt_cgs_k[((4*0)+3):(4*0)];
-  assign rx_ip_rst_0 = rx_ip_rst[0];
-  assign rx_ip_sysref_0 = rx_ip_sysref[0];
-  assign rx_ip_rst_done_0 = rx_ip_rst_done[0];
-  assign rx_rst_0 = rx_rst[0];
-  assign rx_pll_rst_0 = rx_pll_rst[0];
-  assign rx_gt_rst_0 = rx_gt_rst[0];
-  assign rx_pll_locked_0 = rx_pll_locked[0];
-  assign rx_user_ready_0 = rx_user_ready[0];
-  assign rx_rst_done_0 = rx_rst_done[0];
-
-  assign rx_p[0] = rx_0_p;
-  assign rx_n[0] = rx_0_n;
-  assign rx_clk[0] = rx_clk_0;
-  assign rx_sysref[0] = rx_sysref_0;
-  assign rx_gt_comma_align_enb[0] = rx_gt_comma_align_enb_0;
-  assign rx_ip_sof[((4*0)+3):(4*0)] = rx_ip_sof_0;
-  assign rx_ip_data[((32*0)+31):(32*0)] = rx_ip_data_0;
-  assign rx_ip_sync[0] = rx_ip_sync_0;
-  assign rx_rst_m[0] = rx_rst_m_0;
-  assign rx_gt_rst_m[0] = rx_gt_rst_m_0;
-  assign rx_pll_locked_m[0] = rx_pll_locked_m_0;
-  assign rx_user_ready_m[0] = rx_user_ready_m_0;
-  assign rx_rst_done_m[0] = rx_rst_done_m_0;
-
-  assign rx_out_clk_1 = rx_out_clk[1];
-  assign rx_rst_1 = rx_rst[1];
-  assign rx_sof_1 = rx_sof[1];
-  assign rx_data_1 = rx_data[((32*1)+31):(32*1)];
-  assign rx_sync_1 = rx_sync[1];
-  assign rx_gt_charisk_1 = rx_gt_charisk[((4*1)+3):(4*1)];
-  assign rx_gt_disperr_1 = rx_gt_disperr[((4*1)+3):(4*1)];
-  assign rx_gt_notintable_1 = rx_gt_notintable[((4*1)+3):(4*1)];
-  assign rx_gt_data_1 = rx_gt_data[((32*1)+31):(32*1)];
-  assign rx_gt_ilas_f_1 = rx_gt_ilas_f[((4*1)+3):(4*1)];
-  assign rx_gt_ilas_q_1 = rx_gt_ilas_q[((4*1)+3):(4*1)];
-  assign rx_gt_ilas_a_1 = rx_gt_ilas_a[((4*1)+3):(4*1)];
-  assign rx_gt_ilas_r_1 = rx_gt_ilas_r[((4*1)+3):(4*1)];
-  assign rx_gt_cgs_k_1 = rx_gt_cgs_k[((4*1)+3):(4*1)];
-  assign rx_ip_rst_1 = rx_ip_rst[1];
-  assign rx_ip_sysref_1 = rx_ip_sysref[1];
-  assign rx_ip_rst_done_1 = rx_ip_rst_done[1];
-  assign rx_rst_1 = rx_rst[1];
-  assign rx_pll_rst_1 = rx_pll_rst[1];
-  assign rx_gt_rst_1 = rx_gt_rst[1];
-  assign rx_pll_locked_1 = rx_pll_locked[1];
-  assign rx_user_ready_1 = rx_user_ready[1];
-  assign rx_rst_done_1 = rx_rst_done[1];
-
-  assign rx_p[1] = rx_1_p;
-  assign rx_n[1] = rx_1_n;
-  assign rx_clk[1] = rx_clk_1;
-  assign rx_sysref[1] = rx_sysref_1;
-  assign rx_gt_comma_align_enb[1] = rx_gt_comma_align_enb_1;
-  assign rx_ip_sof[((4*1)+3):(4*1)] = rx_ip_sof_1;
-  assign rx_ip_data[((32*1)+31):(32*1)] = rx_ip_data_1;
-  assign rx_ip_sync[1] = rx_ip_sync_1;
-  assign rx_rst_m[1] = rx_rst_m_1;
-  assign rx_gt_rst_m[1] = rx_gt_rst_m_1;
-  assign rx_pll_locked_m[1] = rx_pll_locked_m_1;
-  assign rx_user_ready_m[1] = rx_user_ready_m_1;
-  assign rx_rst_done_m[1] = rx_rst_done_m_1;
-
-  assign rx_out_clk_2 = rx_out_clk[2];
-  assign rx_rst_2 = rx_rst[2];
-  assign rx_sof_2 = rx_sof[2];
-  assign rx_data_2 = rx_data[((32*2)+31):(32*2)];
-  assign rx_sync_2 = rx_sync[2];
-  assign rx_gt_charisk_2 = rx_gt_charisk[((4*2)+3):(4*2)];
-  assign rx_gt_disperr_2 = rx_gt_disperr[((4*2)+3):(4*2)];
-  assign rx_gt_notintable_2 = rx_gt_notintable[((4*2)+3):(4*2)];
-  assign rx_gt_data_2 = rx_gt_data[((32*2)+31):(32*2)];
-  assign rx_gt_ilas_f_2 = rx_gt_ilas_f[((4*2)+3):(4*2)];
-  assign rx_gt_ilas_q_2 = rx_gt_ilas_q[((4*2)+3):(4*2)];
-  assign rx_gt_ilas_a_2 = rx_gt_ilas_a[((4*2)+3):(4*2)];
-  assign rx_gt_ilas_r_2 = rx_gt_ilas_r[((4*2)+3):(4*2)];
-  assign rx_gt_cgs_k_2 = rx_gt_cgs_k[((4*2)+3):(4*2)];
-  assign rx_ip_rst_2 = rx_ip_rst[2];
-  assign rx_ip_sysref_2 = rx_ip_sysref[2];
-  assign rx_ip_rst_done_2 = rx_ip_rst_done[2];
-  assign rx_rst_2 = rx_rst[2];
-  assign rx_pll_rst_2 = rx_pll_rst[2];
-  assign rx_gt_rst_2 = rx_gt_rst[2];
-  assign rx_pll_locked_2 = rx_pll_locked[2];
-  assign rx_user_ready_2 = rx_user_ready[2];
-  assign rx_rst_done_2 = rx_rst_done[2];
-
-  assign rx_p[2] = rx_2_p;
-  assign rx_n[2] = rx_2_n;
-  assign rx_clk[2] = rx_clk_2;
-  assign rx_sysref[2] = rx_sysref_2;
-  assign rx_gt_comma_align_enb[2] = rx_gt_comma_align_enb_2;
-  assign rx_ip_sof[((4*2)+3):(4*2)] = rx_ip_sof_2;
-  assign rx_ip_data[((32*2)+31):(32*2)] = rx_ip_data_2;
-  assign rx_ip_sync[2] = rx_ip_sync_2;
-  assign rx_rst_m[2] = rx_rst_m_2;
-  assign rx_gt_rst_m[2] = rx_gt_rst_m_2;
-  assign rx_pll_locked_m[2] = rx_pll_locked_m_2;
-  assign rx_user_ready_m[2] = rx_user_ready_m_2;
-  assign rx_rst_done_m[2] = rx_rst_done_m_2;
-
-  assign rx_out_clk_3 = rx_out_clk[3];
-  assign rx_rst_3 = rx_rst[3];
-  assign rx_sof_3 = rx_sof[3];
-  assign rx_data_3 = rx_data[((32*3)+31):(32*3)];
-  assign rx_sync_3 = rx_sync[3];
-  assign rx_gt_charisk_3 = rx_gt_charisk[((4*3)+3):(4*3)];
-  assign rx_gt_disperr_3 = rx_gt_disperr[((4*3)+3):(4*3)];
-  assign rx_gt_notintable_3 = rx_gt_notintable[((4*3)+3):(4*3)];
-  assign rx_gt_data_3 = rx_gt_data[((32*3)+31):(32*3)];
-  assign rx_gt_ilas_f_3 = rx_gt_ilas_f[((4*3)+3):(4*3)];
-  assign rx_gt_ilas_q_3 = rx_gt_ilas_q[((4*3)+3):(4*3)];
-  assign rx_gt_ilas_a_3 = rx_gt_ilas_a[((4*3)+3):(4*3)];
-  assign rx_gt_ilas_r_3 = rx_gt_ilas_r[((4*3)+3):(4*3)];
-  assign rx_gt_cgs_k_3 = rx_gt_cgs_k[((4*3)+3):(4*3)];
-  assign rx_ip_rst_3 = rx_ip_rst[3];
-  assign rx_ip_sysref_3 = rx_ip_sysref[3];
-  assign rx_ip_rst_done_3 = rx_ip_rst_done[3];
-  assign rx_rst_3 = rx_rst[3];
-  assign rx_pll_rst_3 = rx_pll_rst[3];
-  assign rx_gt_rst_3 = rx_gt_rst[3];
-  assign rx_pll_locked_3 = rx_pll_locked[3];
-  assign rx_user_ready_3 = rx_user_ready[3];
-  assign rx_rst_done_3 = rx_rst_done[3];
-
-  assign rx_p[3] = rx_3_p;
-  assign rx_n[3] = rx_3_n;
-  assign rx_clk[3] = rx_clk_3;
-  assign rx_sysref[3] = rx_sysref_3;
-  assign rx_gt_comma_align_enb[3] = rx_gt_comma_align_enb_3;
-  assign rx_ip_sof[((4*3)+3):(4*3)] = rx_ip_sof_3;
-  assign rx_ip_data[((32*3)+31):(32*3)] = rx_ip_data_3;
-  assign rx_ip_sync[3] = rx_ip_sync_3;
-  assign rx_rst_m[3] = rx_rst_m_3;
-  assign rx_gt_rst_m[3] = rx_gt_rst_m_3;
-  assign rx_pll_locked_m[3] = rx_pll_locked_m_3;
-  assign rx_user_ready_m[3] = rx_user_ready_m_3;
-  assign rx_rst_done_m[3] = rx_rst_done_m_3;
-
-  assign rx_out_clk_4 = rx_out_clk[4];
-  assign rx_rst_4 = rx_rst[4];
-  assign rx_sof_4 = rx_sof[4];
-  assign rx_data_4 = rx_data[((32*4)+31):(32*4)];
-  assign rx_sync_4 = rx_sync[4];
-  assign rx_gt_charisk_4 = rx_gt_charisk[((4*4)+3):(4*4)];
-  assign rx_gt_disperr_4 = rx_gt_disperr[((4*4)+3):(4*4)];
-  assign rx_gt_notintable_4 = rx_gt_notintable[((4*4)+3):(4*4)];
-  assign rx_gt_data_4 = rx_gt_data[((32*4)+31):(32*4)];
-  assign rx_gt_ilas_f_4 = rx_gt_ilas_f[((4*4)+3):(4*4)];
-  assign rx_gt_ilas_q_4 = rx_gt_ilas_q[((4*4)+3):(4*4)];
-  assign rx_gt_ilas_a_4 = rx_gt_ilas_a[((4*4)+3):(4*4)];
-  assign rx_gt_ilas_r_4 = rx_gt_ilas_r[((4*4)+3):(4*4)];
-  assign rx_gt_cgs_k_4 = rx_gt_cgs_k[((4*4)+3):(4*4)];
-  assign rx_ip_rst_4 = rx_ip_rst[4];
-  assign rx_ip_sysref_4 = rx_ip_sysref[4];
-  assign rx_ip_rst_done_4 = rx_ip_rst_done[4];
-  assign rx_rst_4 = rx_rst[4];
-  assign rx_pll_rst_4 = rx_pll_rst[4];
-  assign rx_gt_rst_4 = rx_gt_rst[4];
-  assign rx_pll_locked_4 = rx_pll_locked[4];
-  assign rx_user_ready_4 = rx_user_ready[4];
-  assign rx_rst_done_4 = rx_rst_done[4];
-
-  assign rx_p[4] = rx_4_p;
-  assign rx_n[4] = rx_4_n;
-  assign rx_clk[4] = rx_clk_4;
-  assign rx_sysref[4] = rx_sysref_4;
-  assign rx_gt_comma_align_enb[4] = rx_gt_comma_align_enb_4;
-  assign rx_ip_sof[((4*4)+3):(4*4)] = rx_ip_sof_4;
-  assign rx_ip_data[((32*4)+31):(32*4)] = rx_ip_data_4;
-  assign rx_ip_sync[4] = rx_ip_sync_4;
-  assign rx_rst_m[4] = rx_rst_m_4;
-  assign rx_gt_rst_m[4] = rx_gt_rst_m_4;
-  assign rx_pll_locked_m[4] = rx_pll_locked_m_4;
-  assign rx_user_ready_m[4] = rx_user_ready_m_4;
-  assign rx_rst_done_m[4] = rx_rst_done_m_4;
-
-  assign rx_out_clk_5 = rx_out_clk[5];
-  assign rx_rst_5 = rx_rst[5];
-  assign rx_sof_5 = rx_sof[5];
-  assign rx_data_5 = rx_data[((32*5)+31):(32*5)];
-  assign rx_sync_5 = rx_sync[5];
-  assign rx_gt_charisk_5 = rx_gt_charisk[((4*5)+3):(4*5)];
-  assign rx_gt_disperr_5 = rx_gt_disperr[((4*5)+3):(4*5)];
-  assign rx_gt_notintable_5 = rx_gt_notintable[((4*5)+3):(4*5)];
-  assign rx_gt_data_5 = rx_gt_data[((32*5)+31):(32*5)];
-  assign rx_gt_ilas_f_5 = rx_gt_ilas_f[((4*5)+3):(4*5)];
-  assign rx_gt_ilas_q_5 = rx_gt_ilas_q[((4*5)+3):(4*5)];
-  assign rx_gt_ilas_a_5 = rx_gt_ilas_a[((4*5)+3):(4*5)];
-  assign rx_gt_ilas_r_5 = rx_gt_ilas_r[((4*5)+3):(4*5)];
-  assign rx_gt_cgs_k_5 = rx_gt_cgs_k[((4*5)+3):(4*5)];
-  assign rx_ip_rst_5 = rx_ip_rst[5];
-  assign rx_ip_sysref_5 = rx_ip_sysref[5];
-  assign rx_ip_rst_done_5 = rx_ip_rst_done[5];
-  assign rx_rst_5 = rx_rst[5];
-  assign rx_pll_rst_5 = rx_pll_rst[5];
-  assign rx_gt_rst_5 = rx_gt_rst[5];
-  assign rx_pll_locked_5 = rx_pll_locked[5];
-  assign rx_user_ready_5 = rx_user_ready[5];
-  assign rx_rst_done_5 = rx_rst_done[5];
-
-  assign rx_p[5] = rx_5_p;
-  assign rx_n[5] = rx_5_n;
-  assign rx_clk[5] = rx_clk_5;
-  assign rx_sysref[5] = rx_sysref_5;
-  assign rx_gt_comma_align_enb[5] = rx_gt_comma_align_enb_5;
-  assign rx_ip_sof[((4*5)+3):(4*5)] = rx_ip_sof_5;
-  assign rx_ip_data[((32*5)+31):(32*5)] = rx_ip_data_5;
-  assign rx_ip_sync[5] = rx_ip_sync_5;
-  assign rx_rst_m[5] = rx_rst_m_5;
-  assign rx_gt_rst_m[5] = rx_gt_rst_m_5;
-  assign rx_pll_locked_m[5] = rx_pll_locked_m_5;
-  assign rx_user_ready_m[5] = rx_user_ready_m_5;
-  assign rx_rst_done_m[5] = rx_rst_done_m_5;
-
-  assign rx_out_clk_6 = rx_out_clk[6];
-  assign rx_rst_6 = rx_rst[6];
-  assign rx_sof_6 = rx_sof[6];
-  assign rx_data_6 = rx_data[((32*6)+31):(32*6)];
-  assign rx_sync_6 = rx_sync[6];
-  assign rx_gt_charisk_6 = rx_gt_charisk[((4*6)+3):(4*6)];
-  assign rx_gt_disperr_6 = rx_gt_disperr[((4*6)+3):(4*6)];
-  assign rx_gt_notintable_6 = rx_gt_notintable[((4*6)+3):(4*6)];
-  assign rx_gt_data_6 = rx_gt_data[((32*6)+31):(32*6)];
-  assign rx_gt_ilas_f_6 = rx_gt_ilas_f[((4*6)+3):(4*6)];
-  assign rx_gt_ilas_q_6 = rx_gt_ilas_q[((4*6)+3):(4*6)];
-  assign rx_gt_ilas_a_6 = rx_gt_ilas_a[((4*6)+3):(4*6)];
-  assign rx_gt_ilas_r_6 = rx_gt_ilas_r[((4*6)+3):(4*6)];
-  assign rx_gt_cgs_k_6 = rx_gt_cgs_k[((4*6)+3):(4*6)];
-  assign rx_ip_rst_6 = rx_ip_rst[6];
-  assign rx_ip_sysref_6 = rx_ip_sysref[6];
-  assign rx_ip_rst_done_6 = rx_ip_rst_done[6];
-  assign rx_rst_6 = rx_rst[6];
-  assign rx_pll_rst_6 = rx_pll_rst[6];
-  assign rx_gt_rst_6 = rx_gt_rst[6];
-  assign rx_pll_locked_6 = rx_pll_locked[6];
-  assign rx_user_ready_6 = rx_user_ready[6];
-  assign rx_rst_done_6 = rx_rst_done[6];
-
-  assign rx_p[6] = rx_6_p;
-  assign rx_n[6] = rx_6_n;
-  assign rx_clk[6] = rx_clk_6;
-  assign rx_sysref[6] = rx_sysref_6;
-  assign rx_gt_comma_align_enb[6] = rx_gt_comma_align_enb_6;
-  assign rx_ip_sof[((4*6)+3):(4*6)] = rx_ip_sof_6;
-  assign rx_ip_data[((32*6)+31):(32*6)] = rx_ip_data_6;
-  assign rx_ip_sync[6] = rx_ip_sync_6;
-  assign rx_rst_m[6] = rx_rst_m_6;
-  assign rx_gt_rst_m[6] = rx_gt_rst_m_6;
-  assign rx_pll_locked_m[6] = rx_pll_locked_m_6;
-  assign rx_user_ready_m[6] = rx_user_ready_m_6;
-  assign rx_rst_done_m[6] = rx_rst_done_m_6;
-
-  assign rx_out_clk_7 = rx_out_clk[7];
-  assign rx_rst_7 = rx_rst[7];
-  assign rx_sof_7 = rx_sof[7];
-  assign rx_data_7 = rx_data[((32*7)+31):(32*7)];
-  assign rx_sync_7 = rx_sync[7];
-  assign rx_gt_charisk_7 = rx_gt_charisk[((4*7)+3):(4*7)];
-  assign rx_gt_disperr_7 = rx_gt_disperr[((4*7)+3):(4*7)];
-  assign rx_gt_notintable_7 = rx_gt_notintable[((4*7)+3):(4*7)];
-  assign rx_gt_data_7 = rx_gt_data[((32*7)+31):(32*7)];
-  assign rx_gt_ilas_f_7 = rx_gt_ilas_f[((4*7)+3):(4*7)];
-  assign rx_gt_ilas_q_7 = rx_gt_ilas_q[((4*7)+3):(4*7)];
-  assign rx_gt_ilas_a_7 = rx_gt_ilas_a[((4*7)+3):(4*7)];
-  assign rx_gt_ilas_r_7 = rx_gt_ilas_r[((4*7)+3):(4*7)];
-  assign rx_gt_cgs_k_7 = rx_gt_cgs_k[((4*7)+3):(4*7)];
-  assign rx_ip_rst_7 = rx_ip_rst[7];
-  assign rx_ip_sysref_7 = rx_ip_sysref[7];
-  assign rx_ip_rst_done_7 = rx_ip_rst_done[7];
-  assign rx_rst_7 = rx_rst[7];
-  assign rx_pll_rst_7 = rx_pll_rst[7];
-  assign rx_gt_rst_7 = rx_gt_rst[7];
-  assign rx_pll_locked_7 = rx_pll_locked[7];
-  assign rx_user_ready_7 = rx_user_ready[7];
-  assign rx_rst_done_7 = rx_rst_done[7];
-
-  assign rx_p[7] = rx_7_p;
-  assign rx_n[7] = rx_7_n;
-  assign rx_clk[7] = rx_clk_7;
-  assign rx_sysref[7] = rx_sysref_7;
-  assign rx_gt_comma_align_enb[7] = rx_gt_comma_align_enb_7;
-  assign rx_ip_sof[((4*7)+3):(4*7)] = rx_ip_sof_7;
-  assign rx_ip_data[((32*7)+31):(32*7)] = rx_ip_data_7;
-  assign rx_ip_sync[7] = rx_ip_sync_7;
-  assign rx_rst_m[7] = rx_rst_m_7;
-  assign rx_gt_rst_m[7] = rx_gt_rst_m_7;
-  assign rx_pll_locked_m[7] = rx_pll_locked_m_7;
-  assign rx_user_ready_m[7] = rx_user_ready_m_7;
-  assign rx_rst_done_m[7] = rx_rst_done_m_7;
-
-  assign tx_0_p = tx_p[0];
-  assign tx_0_n = tx_n[0];
-  assign tx_out_clk_0 = tx_out_clk[0];
-  assign tx_rst_0 = tx_rst[0];
-  assign tx_ip_rst_0 = tx_ip_rst[0];
-  assign tx_ip_data_0 = tx_ip_data[((32*0)+31):(32*0)];
-  assign tx_ip_sysref_0 = tx_ip_sysref[0];
-  assign tx_ip_sync_0 = tx_ip_sync[0];
-  assign tx_ip_rst_done_0 = tx_ip_rst_done[0];
-  assign tx_rst_0 = tx_rst[0];
-  assign tx_pll_rst_0 = tx_pll_rst[0];
-  assign tx_gt_rst_0 = tx_gt_rst[0];
-  assign tx_pll_locked_0 = tx_pll_locked[0];
-  assign tx_user_ready_0 = tx_user_ready[0];
-  assign tx_rst_done_0 = tx_rst_done[0];
-
-  assign tx_clk[0] = tx_clk_0;
-  assign tx_data[((32*0)+31):(32*0)] = tx_data_0;
-  assign tx_sysref[0] = tx_sysref_0;
-  assign tx_sync[0] = tx_sync_0;
-  assign tx_gt_charisk[((4*0)+3):(4*0)] = tx_gt_charisk_0;
-  assign tx_gt_data[((32*0)+31):(32*0)] = tx_gt_data_0;
-  assign tx_rst_m[0] = tx_rst_m_0;
-  assign tx_gt_rst_m[0] = tx_gt_rst_m_0;
-  assign tx_pll_locked_m[0] = tx_pll_locked_m_0;
-  assign tx_user_ready_m[0] = tx_user_ready_m_0;
-  assign tx_rst_done_m[0] = tx_rst_done_m_0;
-
-  assign tx_1_p = tx_p[1];
-  assign tx_1_n = tx_n[1];
-  assign tx_out_clk_1 = tx_out_clk[1];
-  assign tx_rst_1 = tx_rst[1];
-  assign tx_ip_rst_1 = tx_ip_rst[1];
-  assign tx_ip_data_1 = tx_ip_data[((32*1)+31):(32*1)];
-  assign tx_ip_sysref_1 = tx_ip_sysref[1];
-  assign tx_ip_sync_1 = tx_ip_sync[1];
-  assign tx_ip_rst_done_1 = tx_ip_rst_done[1];
-  assign tx_rst_1 = tx_rst[1];
-  assign tx_pll_rst_1 = tx_pll_rst[1];
-  assign tx_gt_rst_1 = tx_gt_rst[1];
-  assign tx_pll_locked_1 = tx_pll_locked[1];
-  assign tx_user_ready_1 = tx_user_ready[1];
-  assign tx_rst_done_1 = tx_rst_done[1];
-
-  assign tx_clk[1] = tx_clk_1;
-  assign tx_data[((32*1)+31):(32*1)] = tx_data_1;
-  assign tx_sysref[1] = tx_sysref_1;
-  assign tx_sync[1] = tx_sync_1;
-  assign tx_gt_charisk[((4*1)+3):(4*1)] = tx_gt_charisk_1;
-  assign tx_gt_data[((32*1)+31):(32*1)] = tx_gt_data_1;
-  assign tx_rst_m[1] = tx_rst_m_1;
-  assign tx_gt_rst_m[1] = tx_gt_rst_m_1;
-  assign tx_pll_locked_m[1] = tx_pll_locked_m_1;
-  assign tx_user_ready_m[1] = tx_user_ready_m_1;
-  assign tx_rst_done_m[1] = tx_rst_done_m_1;
-
-  assign tx_2_p = tx_p[2];
-  assign tx_2_n = tx_n[2];
-  assign tx_out_clk_2 = tx_out_clk[2];
-  assign tx_rst_2 = tx_rst[2];
-  assign tx_ip_rst_2 = tx_ip_rst[2];
-  assign tx_ip_data_2 = tx_ip_data[((32*2)+31):(32*2)];
-  assign tx_ip_sysref_2 = tx_ip_sysref[2];
-  assign tx_ip_sync_2 = tx_ip_sync[2];
-  assign tx_ip_rst_done_2 = tx_ip_rst_done[2];
-  assign tx_rst_2 = tx_rst[2];
-  assign tx_pll_rst_2 = tx_pll_rst[2];
-  assign tx_gt_rst_2 = tx_gt_rst[2];
-  assign tx_pll_locked_2 = tx_pll_locked[2];
-  assign tx_user_ready_2 = tx_user_ready[2];
-  assign tx_rst_done_2 = tx_rst_done[2];
-
-  assign tx_clk[2] = tx_clk_2;
-  assign tx_data[((32*2)+31):(32*2)] = tx_data_2;
-  assign tx_sysref[2] = tx_sysref_2;
-  assign tx_sync[2] = tx_sync_2;
-  assign tx_gt_charisk[((4*2)+3):(4*2)] = tx_gt_charisk_2;
-  assign tx_gt_data[((32*2)+31):(32*2)] = tx_gt_data_2;
-  assign tx_rst_m[2] = tx_rst_m_2;
-  assign tx_gt_rst_m[2] = tx_gt_rst_m_2;
-  assign tx_pll_locked_m[2] = tx_pll_locked_m_2;
-  assign tx_user_ready_m[2] = tx_user_ready_m_2;
-  assign tx_rst_done_m[2] = tx_rst_done_m_2;
-
-  assign tx_3_p = tx_p[3];
-  assign tx_3_n = tx_n[3];
-  assign tx_out_clk_3 = tx_out_clk[3];
-  assign tx_rst_3 = tx_rst[3];
-  assign tx_ip_rst_3 = tx_ip_rst[3];
-  assign tx_ip_data_3 = tx_ip_data[((32*3)+31):(32*3)];
-  assign tx_ip_sysref_3 = tx_ip_sysref[3];
-  assign tx_ip_sync_3 = tx_ip_sync[3];
-  assign tx_ip_rst_done_3 = tx_ip_rst_done[3];
-  assign tx_rst_3 = tx_rst[3];
-  assign tx_pll_rst_3 = tx_pll_rst[3];
-  assign tx_gt_rst_3 = tx_gt_rst[3];
-  assign tx_pll_locked_3 = tx_pll_locked[3];
-  assign tx_user_ready_3 = tx_user_ready[3];
-  assign tx_rst_done_3 = tx_rst_done[3];
-
-  assign tx_clk[3] = tx_clk_3;
-  assign tx_data[((32*3)+31):(32*3)] = tx_data_3;
-  assign tx_sysref[3] = tx_sysref_3;
-  assign tx_sync[3] = tx_sync_3;
-  assign tx_gt_charisk[((4*3)+3):(4*3)] = tx_gt_charisk_3;
-  assign tx_gt_data[((32*3)+31):(32*3)] = tx_gt_data_3;
-  assign tx_rst_m[3] = tx_rst_m_3;
-  assign tx_gt_rst_m[3] = tx_gt_rst_m_3;
-  assign tx_pll_locked_m[3] = tx_pll_locked_m_3;
-  assign tx_user_ready_m[3] = tx_user_ready_m_3;
-  assign tx_rst_done_m[3] = tx_rst_done_m_3;
-
-  assign tx_4_p = tx_p[4];
-  assign tx_4_n = tx_n[4];
-  assign tx_out_clk_4 = tx_out_clk[4];
-  assign tx_rst_4 = tx_rst[4];
-  assign tx_ip_rst_4 = tx_ip_rst[4];
-  assign tx_ip_data_4 = tx_ip_data[((32*4)+31):(32*4)];
-  assign tx_ip_sysref_4 = tx_ip_sysref[4];
-  assign tx_ip_sync_4 = tx_ip_sync[4];
-  assign tx_ip_rst_done_4 = tx_ip_rst_done[4];
-  assign tx_rst_4 = tx_rst[4];
-  assign tx_pll_rst_4 = tx_pll_rst[4];
-  assign tx_gt_rst_4 = tx_gt_rst[4];
-  assign tx_pll_locked_4 = tx_pll_locked[4];
-  assign tx_user_ready_4 = tx_user_ready[4];
-  assign tx_rst_done_4 = tx_rst_done[4];
-
-  assign tx_clk[4] = tx_clk_4;
-  assign tx_data[((32*4)+31):(32*4)] = tx_data_4;
-  assign tx_sysref[4] = tx_sysref_4;
-  assign tx_sync[4] = tx_sync_4;
-  assign tx_gt_charisk[((4*4)+3):(4*4)] = tx_gt_charisk_4;
-  assign tx_gt_data[((32*4)+31):(32*4)] = tx_gt_data_4;
-  assign tx_rst_m[4] = tx_rst_m_4;
-  assign tx_gt_rst_m[4] = tx_gt_rst_m_4;
-  assign tx_pll_locked_m[4] = tx_pll_locked_m_4;
-  assign tx_user_ready_m[4] = tx_user_ready_m_4;
-  assign tx_rst_done_m[4] = tx_rst_done_m_4;
-
-  assign tx_5_p = tx_p[5];
-  assign tx_5_n = tx_n[5];
-  assign tx_out_clk_5 = tx_out_clk[5];
-  assign tx_rst_5 = tx_rst[5];
-  assign tx_ip_rst_5 = tx_ip_rst[5];
-  assign tx_ip_data_5 = tx_ip_data[((32*5)+31):(32*5)];
-  assign tx_ip_sysref_5 = tx_ip_sysref[5];
-  assign tx_ip_sync_5 = tx_ip_sync[5];
-  assign tx_ip_rst_done_5 = tx_ip_rst_done[5];
-  assign tx_rst_5 = tx_rst[5];
-  assign tx_pll_rst_5 = tx_pll_rst[5];
-  assign tx_gt_rst_5 = tx_gt_rst[5];
-  assign tx_pll_locked_5 = tx_pll_locked[5];
-  assign tx_user_ready_5 = tx_user_ready[5];
-  assign tx_rst_done_5 = tx_rst_done[5];
-
-  assign tx_clk[5] = tx_clk_5;
-  assign tx_data[((32*5)+31):(32*5)] = tx_data_5;
-  assign tx_sysref[5] = tx_sysref_5;
-  assign tx_sync[5] = tx_sync_5;
-  assign tx_gt_charisk[((4*5)+3):(4*5)] = tx_gt_charisk_5;
-  assign tx_gt_data[((32*5)+31):(32*5)] = tx_gt_data_5;
-  assign tx_rst_m[5] = tx_rst_m_5;
-  assign tx_gt_rst_m[5] = tx_gt_rst_m_5;
-  assign tx_pll_locked_m[5] = tx_pll_locked_m_5;
-  assign tx_user_ready_m[5] = tx_user_ready_m_5;
-  assign tx_rst_done_m[5] = tx_rst_done_m_5;
-
-  assign tx_6_p = tx_p[6];
-  assign tx_6_n = tx_n[6];
-  assign tx_out_clk_6 = tx_out_clk[6];
-  assign tx_rst_6 = tx_rst[6];
-  assign tx_ip_rst_6 = tx_ip_rst[6];
-  assign tx_ip_data_6 = tx_ip_data[((32*6)+31):(32*6)];
-  assign tx_ip_sysref_6 = tx_ip_sysref[6];
-  assign tx_ip_sync_6 = tx_ip_sync[6];
-  assign tx_ip_rst_done_6 = tx_ip_rst_done[6];
-  assign tx_rst_6 = tx_rst[6];
-  assign tx_pll_rst_6 = tx_pll_rst[6];
-  assign tx_gt_rst_6 = tx_gt_rst[6];
-  assign tx_pll_locked_6 = tx_pll_locked[6];
-  assign tx_user_ready_6 = tx_user_ready[6];
-  assign tx_rst_done_6 = tx_rst_done[6];
-
-  assign tx_clk[6] = tx_clk_6;
-  assign tx_data[((32*6)+31):(32*6)] = tx_data_6;
-  assign tx_sysref[6] = tx_sysref_6;
-  assign tx_sync[6] = tx_sync_6;
-  assign tx_gt_charisk[((4*6)+3):(4*6)] = tx_gt_charisk_6;
-  assign tx_gt_data[((32*6)+31):(32*6)] = tx_gt_data_6;
-  assign tx_rst_m[6] = tx_rst_m_6;
-  assign tx_gt_rst_m[6] = tx_gt_rst_m_6;
-  assign tx_pll_locked_m[6] = tx_pll_locked_m_6;
-  assign tx_user_ready_m[6] = tx_user_ready_m_6;
-  assign tx_rst_done_m[6] = tx_rst_done_m_6;
-
-  assign tx_7_p = tx_p[7];
-  assign tx_7_n = tx_n[7];
-  assign tx_out_clk_7 = tx_out_clk[7];
-  assign tx_rst_7 = tx_rst[7];
-  assign tx_ip_rst_7 = tx_ip_rst[7];
-  assign tx_ip_data_7 = tx_ip_data[((32*7)+31):(32*7)];
-  assign tx_ip_sysref_7 = tx_ip_sysref[7];
-  assign tx_ip_sync_7 = tx_ip_sync[7];
-  assign tx_ip_rst_done_7 = tx_ip_rst_done[7];
-  assign tx_rst_7 = tx_rst[7];
-  assign tx_pll_rst_7 = tx_pll_rst[7];
-  assign tx_gt_rst_7 = tx_gt_rst[7];
-  assign tx_pll_locked_7 = tx_pll_locked[7];
-  assign tx_user_ready_7 = tx_user_ready[7];
-  assign tx_rst_done_7 = tx_rst_done[7];
-
-  assign tx_clk[7] = tx_clk_7;
-  assign tx_data[((32*7)+31):(32*7)] = tx_data_7;
-  assign tx_sysref[7] = tx_sysref_7;
-  assign tx_sync[7] = tx_sync_7;
-  assign tx_gt_charisk[((4*7)+3):(4*7)] = tx_gt_charisk_7;
-  assign tx_gt_data[((32*7)+31):(32*7)] = tx_gt_data_7;
-  assign tx_rst_m[7] = tx_rst_m_7;
-  assign tx_gt_rst_m[7] = tx_gt_rst_m_7;
-  assign tx_pll_locked_m[7] = tx_pll_locked_m_7;
-  assign tx_user_ready_m[7] = tx_user_ready_m_7;
-  assign tx_rst_done_m[7] = tx_rst_done_m_7;
-
-  // up signals
-
-  always @(posedge up_clk or negedge up_rstn) begin
-    if (up_rstn == 1'b0) begin
-      up_wack_d <= 1'd0;
-      up_rack_d <= 1'd0;
-      up_rdata_d <= 32'd0;
-    end else begin
-      up_wack_d <= | up_wack;
-      up_rack_d <= | up_rack;
-      up_rdata_d <= up_rdata[((32*0)+31):(32*0)] |
-        up_rdata[((32*1)+31):(32*1)] |
-        up_rdata[((32*2)+31):(32*2)] |
-        up_rdata[((32*3)+31):(32*3)] |
-        up_rdata[((32*4)+31):(32*4)] |
-        up_rdata[((32*5)+31):(32*5)] |
-        up_rdata[((32*6)+31):(32*6)] |
-        up_rdata[((32*7)+31):(32*7)] |
-        up_rdata[((32*8)+31):(32*8)];
-    end
-  end
-
-  // instantiations
-
-  genvar n;
-  generate
-
-  if (NUM_OF_LANES < 8) begin
-  for (n = NUM_OF_LANES; n < 8; n = n + 1) begin: g_unused_1
-  assign rx_rst[n] = 1'd0;
-  assign rx_pll_rst[n] = 1'd0;
-  assign rx_gt_rst[n] = 1'd0;
-  assign rx_pll_locked[n] = 1'd0;
-  assign rx_user_ready[n] = 1'd0;
-  assign rx_rst_done[n] = 1'd0;
-  assign rx_out_clk[n] = 1'd0;
-  assign rx_rst[n] = 1'd0;
-  assign rx_sync[n] = 1'd0;
-  assign rx_sof[n] = 1'd0;
-  assign rx_data[((32*n)+31):(32*n)] = 32'd0;
-  assign rx_gt_charisk[((4*n)+3):(4*n)] = 4'd0;
-  assign rx_gt_disperr[((4*n)+3):(4*n)] = 4'd0;
-  assign rx_gt_notintable[((4*n)+3):(4*n)] = 4'd0;
-  assign rx_gt_data[((32*n)+31):(32*n)] = 32'd0;
-  assign rx_gt_ilas_f[((4*n)+3):(4*n)] = 4'd0;
-  assign rx_gt_ilas_q[((4*n)+3):(4*n)] = 4'd0;
-  assign rx_gt_ilas_a[((4*n)+3):(4*n)] = 4'd0;
-  assign rx_gt_ilas_r[((4*n)+3):(4*n)] = 4'd0;
-  assign rx_gt_cgs_k[((4*n)+3):(4*n)] = 4'd0;
-  assign rx_ip_rst[n] = 1'd0;
-  assign rx_ip_sysref[n] = 1'd0;
-  assign rx_ip_rst_done[n] = 1'd0;
-  assign tx_p[n] = 1'd0;
-  assign tx_n[n] = 1'd1;
-  assign tx_rst[n] = 1'd0;
-  assign tx_pll_rst[n] = 1'd0;
-  assign tx_gt_rst[n] = 1'd0;
-  assign tx_pll_locked[n] = 1'd0;
-  assign tx_user_ready[n] = 1'd0;
-  assign tx_rst_done[n] = 1'd0;
-  assign tx_out_clk[n] = 1'd0;
-  assign tx_rst[n] = 1'd0;
-  assign tx_ip_rst[n] = 1'd0;
-  assign tx_ip_data[((32*n)+31):(32*n)] = 32'd0;
-  assign tx_ip_sysref[n] = 1'd0;
-  assign tx_ip_sync[n] = 1'd0;
-  assign tx_ip_rst_done[n] = 1'd0;
-  end
-  end
-
-  for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane_1
-  ad_gt_channel_1 #(
-    .ID (n),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
-    .PMA_RSV (PMA_RSV[n]),
-    .CPLL_FBDIV (CPLL_FBDIV[n]),
-    .RX_OUT_DIV (RX_OUT_DIV[n]),
-    .RX_CLK25_DIV (RX_CLK25_DIV[n]),
-    .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE[n]),
-    .RX_CDR_CFG (RX_CDR_CFG[n]),
-    .TX_OUT_DIV (TX_OUT_DIV[n]),
-    .TX_CLK25_DIV (TX_CLK25_DIV[n]),
-    .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE[n]))
-  i_channel (
-    .cpll_rst_m (cpll_rst_m[n]),
-    .cpll_ref_clk_in (cpll_ref_clk_in[n]),
-    .qpll_ref_clk (qpll_ref_clk[n]),
-    .qpll_locked (qpll_locked[n]),
-    .qpll_clk (qpll_clk[n]),
-    .rx_p (rx_p[n]),
-    .rx_n (rx_n[n]),
-    .rx_out_clk (rx_out_clk[n]),
-    .rx_clk (rx_clk[n]),
-    .rx_rst (rx_rst[n]),
-    .rx_rst_m (rx_rst_m[n]),
-    .rx_sof (rx_sof[n]),
-    .rx_data (rx_data[((32*n)+31):(32*n)]),
-    .rx_sysref (rx_sysref[n]),
-    .rx_sync (rx_sync[n]),
-    .rx_pll_rst (rx_pll_rst[n]),
-    .rx_gt_rst (rx_gt_rst[n]),
-    .rx_gt_rst_m (rx_gt_rst_m[n]),
-    .rx_gt_charisk (rx_gt_charisk[((4*n)+3):(4*n)]),
-    .rx_gt_disperr (rx_gt_disperr[((4*n)+3):(4*n)]),
-    .rx_gt_notintable (rx_gt_notintable[((4*n)+3):(4*n)]),
-    .rx_gt_data (rx_gt_data[((32*n)+31):(32*n)]),
-    .rx_gt_comma_align_enb (rx_gt_comma_align_enb[n]),
-    .rx_gt_ilas_f (rx_gt_ilas_f[((4*n)+3):(4*n)]),
-    .rx_gt_ilas_q (rx_gt_ilas_q[((4*n)+3):(4*n)]),
-    .rx_gt_ilas_a (rx_gt_ilas_a[((4*n)+3):(4*n)]),
-    .rx_gt_ilas_r (rx_gt_ilas_r[((4*n)+3):(4*n)]),
-    .rx_gt_cgs_k (rx_gt_cgs_k[((4*n)+3):(4*n)]),
-    .rx_ip_rst (rx_ip_rst[n]),
-    .rx_ip_sof (rx_ip_sof[((4*n)+3):(4*n)]),
-    .rx_ip_data (rx_ip_data[((32*n)+31):(32*n)]),
-    .rx_ip_sysref (rx_ip_sysref[n]),
-    .rx_ip_sync (rx_ip_sync[n]),
-    .rx_ip_rst_done (rx_ip_rst_done[n]),
-    .rx_pll_locked (rx_pll_locked[n]),
-    .rx_user_ready (rx_user_ready[n]),
-    .rx_rst_done (rx_rst_done[n]),
-    .rx_pll_locked_m (rx_pll_locked_m[n]),
-    .rx_user_ready_m (rx_user_ready_m[n]),
-    .rx_rst_done_m (rx_rst_done_m[n]),
-    .tx_p (tx_p[n]),
-    .tx_n (tx_n[n]),
-    .tx_out_clk (tx_out_clk[n]),
-    .tx_clk (tx_clk[n]),
-    .tx_rst (tx_rst[n]),
-    .tx_rst_m (tx_rst_m[n]),
-    .tx_data (tx_data[((32*n)+31):(32*n)]),
-    .tx_sysref (tx_sysref[n]),
-    .tx_sync (tx_sync[n]),
-    .tx_pll_rst (tx_pll_rst[n]),
-    .tx_gt_rst (tx_gt_rst[n]),
-    .tx_gt_rst_m (tx_gt_rst_m[n]),
-    .tx_gt_charisk (tx_gt_charisk[((4*TX_DATA_SEL[n])+3):(4*TX_DATA_SEL[n])]),
-    .tx_gt_data (tx_gt_data[((32*TX_DATA_SEL[n])+31):(32*TX_DATA_SEL[n])]),
-    .tx_ip_rst (tx_ip_rst[n]),
-    .tx_ip_data (tx_ip_data[((32*n)+31):(32*n)]),
-    .tx_ip_sysref (tx_ip_sysref[n]),
-    .tx_ip_sync (tx_ip_sync[n]),
-    .tx_ip_rst_done (tx_ip_rst_done[n]),
-    .tx_pll_locked (tx_pll_locked[n]),
-    .tx_user_ready (tx_user_ready[n]),
-    .tx_rst_done (tx_rst_done[n]),
-    .tx_pll_locked_m (tx_pll_locked_m[n]),
-    .tx_user_ready_m (tx_user_ready_m[n]),
-    .tx_rst_done_m (tx_rst_done_m[n]),
-    .up_es_dma_req (up_es_dma_req[n]),
-    .up_es_dma_addr (up_es_dma_addr[((32*n)+31):(32*n)]),
-    .up_es_dma_data (up_es_dma_data[((32*n)+31):(32*n)]),
-    .up_es_dma_ack (up_es_dma_ack[n]),
-    .up_es_dma_err (up_es_dma_err[n]),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack[n]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata[((32*n)+31):(32*n)]),
-    .up_rack (up_rack[n]));
-  end
-  endgenerate
-
-  ad_gt_common_1 #(
-    .ID (0),
-    .GTH_OR_GTX_N (GTH_OR_GTX_N),
-    .QPLL0_ENABLE (QPLL0_ENABLE),
-    .QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV),
-    .QPLL0_CFG (QPLL0_CFG),
-    .QPLL0_FBDIV_RATIO (QPLL0_FBDIV_RATIO),
-    .QPLL0_FBDIV (QPLL0_FBDIV),
-    .QPLL1_ENABLE (QPLL1_ENABLE),
-    .QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV),
-    .QPLL1_CFG (QPLL1_CFG),
-    .QPLL1_FBDIV_RATIO (QPLL1_FBDIV_RATIO),
-    .QPLL1_FBDIV (QPLL1_FBDIV))
-  i_common (
-    .qpll0_rst (qpll0_rst),
-    .qpll0_ref_clk_in (qpll0_ref_clk_in),
-    .qpll1_rst (qpll1_rst),
-    .qpll1_ref_clk_in (qpll1_ref_clk_in),
-    .qpll_clk (qpll_clk),
-    .qpll_ref_clk (qpll_ref_clk),
-    .qpll_locked (qpll_locked),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack[8]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata[((32*8)+31):(32*8)]),
-    .up_rack (up_rack[8]));
-
-  ad_gt_es_axi i_es_axi (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_es_dma_req_0 (up_es_dma_req[0]),
-    .up_es_dma_addr_0 (up_es_dma_addr[((32*0)+31):(32*0)]),
-    .up_es_dma_data_0 (up_es_dma_data[((32*0)+31):(32*0)]),
-    .up_es_dma_ack_0 (up_es_dma_ack[0]),
-    .up_es_dma_err_0 (up_es_dma_err[0]),
-    .up_es_dma_req_1 (up_es_dma_req[1]),
-    .up_es_dma_addr_1 (up_es_dma_addr[((32*1)+31):(32*1)]),
-    .up_es_dma_data_1 (up_es_dma_data[((32*1)+31):(32*1)]),
-    .up_es_dma_ack_1 (up_es_dma_ack[1]),
-    .up_es_dma_err_1 (up_es_dma_err[1]),
-    .up_es_dma_req_2 (up_es_dma_req[2]),
-    .up_es_dma_addr_2 (up_es_dma_addr[((32*2)+31):(32*2)]),
-    .up_es_dma_data_2 (up_es_dma_data[((32*2)+31):(32*2)]),
-    .up_es_dma_ack_2 (up_es_dma_ack[2]),
-    .up_es_dma_err_2 (up_es_dma_err[2]),
-    .up_es_dma_req_3 (up_es_dma_req[3]),
-    .up_es_dma_addr_3 (up_es_dma_addr[((32*3)+31):(32*3)]),
-    .up_es_dma_data_3 (up_es_dma_data[((32*3)+31):(32*3)]),
-    .up_es_dma_ack_3 (up_es_dma_ack[3]),
-    .up_es_dma_err_3 (up_es_dma_err[3]),
-    .up_es_dma_req_4 (up_es_dma_req[4]),
-    .up_es_dma_addr_4 (up_es_dma_addr[((32*4)+31):(32*4)]),
-    .up_es_dma_data_4 (up_es_dma_data[((32*4)+31):(32*4)]),
-    .up_es_dma_ack_4 (up_es_dma_ack[4]),
-    .up_es_dma_err_4 (up_es_dma_err[4]),
-    .up_es_dma_req_5 (up_es_dma_req[5]),
-    .up_es_dma_addr_5 (up_es_dma_addr[((32*5)+31):(32*5)]),
-    .up_es_dma_data_5 (up_es_dma_data[((32*5)+31):(32*5)]),
-    .up_es_dma_ack_5 (up_es_dma_ack[5]),
-    .up_es_dma_err_5 (up_es_dma_err[5]),
-    .up_es_dma_req_6 (up_es_dma_req[6]),
-    .up_es_dma_addr_6 (up_es_dma_addr[((32*6)+31):(32*6)]),
-    .up_es_dma_data_6 (up_es_dma_data[((32*6)+31):(32*6)]),
-    .up_es_dma_ack_6 (up_es_dma_ack[6]),
-    .up_es_dma_err_6 (up_es_dma_err[6]),
-    .up_es_dma_req_7 (up_es_dma_req[7]),
-    .up_es_dma_addr_7 (up_es_dma_addr[((32*7)+31):(32*7)]),
-    .up_es_dma_data_7 (up_es_dma_data[((32*7)+31):(32*7)]),
-    .up_es_dma_ack_7 (up_es_dma_ack[7]),
-    .up_es_dma_err_7 (up_es_dma_err[7]),
-    .axi_awvalid (m_axi_awvalid),
-    .axi_awaddr (m_axi_awaddr),
-    .axi_awprot (m_axi_awprot),
-    .axi_awready (m_axi_awready),
-    .axi_wvalid (m_axi_wvalid),
-    .axi_wdata (m_axi_wdata),
-    .axi_wstrb (m_axi_wstrb),
-    .axi_wready (m_axi_wready),
-    .axi_bvalid (m_axi_bvalid),
-    .axi_bresp (m_axi_bresp),
-    .axi_bready (m_axi_bready),
-    .axi_arvalid (m_axi_arvalid),
-    .axi_araddr (m_axi_araddr),
-    .axi_arprot (m_axi_arprot),
-    .axi_arready (m_axi_arready),
-    .axi_rvalid (m_axi_rvalid),
-    .axi_rresp (m_axi_rresp),
-    .axi_rdata (m_axi_rdata),
-    .axi_rready (m_axi_rready));
-
-  up_axi i_up_axi (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_axi_awvalid (s_axi_awvalid),
-    .up_axi_awaddr (s_axi_awaddr),
-    .up_axi_awready (s_axi_awready),
-    .up_axi_wvalid (s_axi_wvalid),
-    .up_axi_wdata (s_axi_wdata),
-    .up_axi_wstrb (s_axi_wstrb),
-    .up_axi_wready (s_axi_wready),
-    .up_axi_bvalid (s_axi_bvalid),
-    .up_axi_bresp (s_axi_bresp),
-    .up_axi_bready (s_axi_bready),
-    .up_axi_arvalid (s_axi_arvalid),
-    .up_axi_araddr (s_axi_araddr),
-    .up_axi_arready (s_axi_arready),
-    .up_axi_rvalid (s_axi_rvalid),
-    .up_axi_rresp (s_axi_rresp),
-    .up_axi_rdata (s_axi_rdata),
-    .up_axi_rready (s_axi_rready),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_d),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_d),
-    .up_rack (up_rack_d));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_jesd_gt/axi_jesd_gt_constr.xdc b/library/axi_jesd_gt/axi_jesd_gt_constr.xdc
deleted file mode 100644
index 4aca3cd05..000000000
--- a/library/axi_jesd_gt/axi_jesd_gt_constr.xdc
+++ /dev/null
@@ -1,5 +0,0 @@
-
-set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
-
-
-
diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
deleted file mode 100644
index 5697a05f0..000000000
--- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl
+++ /dev/null
@@ -1,194 +0,0 @@
-# ip
-
-source ../scripts/adi_env.tcl
-source $ad_hdl_dir/library/scripts/adi_ip.tcl
-
-adi_ip_create axi_jesd_gt
-adi_ip_files axi_jesd_gt [list \
-  "$ad_hdl_dir/library/common/ad_rst.v" \
-  "$ad_hdl_dir/library/common/ad_gt_channel.v" \
-  "$ad_hdl_dir/library/common/ad_gt_common.v" \
-  "$ad_hdl_dir/library/common/ad_gt_es.v" \
-  "$ad_hdl_dir/library/common/ad_gt_es_axi.v" \
-  "$ad_hdl_dir/library/common/ad_gt_channel_1.v" \
-  "$ad_hdl_dir/library/common/ad_gt_common_1.v" \
-  "$ad_hdl_dir/library/common/ad_jesd_align.v" \
-  "$ad_hdl_dir/library/common/up_axi.v" \
-  "$ad_hdl_dir/library/common/up_gt_channel.v" \
-  "$ad_hdl_dir/library/common/up_gt.v" \
-  "axi_jesd_gt_tx_constr.xdc" \
-  "axi_jesd_gt_rx_constr.xdc" \
-  "axi_jesd_gt_constr.xdc" \
-  "axi_jesd_gt.v" ]
-
-adi_ip_properties axi_jesd_gt
-adi_ip_infer_interfaces axi_jesd_gt
-
-adi_ip_constraints axi_jesd_gt [list \
-  "axi_jesd_gt_tx_constr.xdc" \
-  "axi_jesd_gt_rx_constr.xdc" \
-  "axi_jesd_gt_constr.xdc" ]
-
-ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core]
-
-adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \
-  "qpll_rst            qpll0_rst              "\
-  "qpll_ref_clk        qpll0_ref_clk_in       "]
-
-adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_1 [list \
-  "qpll_rst            qpll1_rst              "\
-  "qpll_ref_clk        qpll1_ref_clk_in       "]
-
-for {set n 0} {$n < 8} {incr n} {
-
-  adi_if_infer_bus ADI:user:if_gt_pll slave gt_pll_${n} [list \
-    "cpll_rst_m          cpll_rst_m_${n}        "\
-    "cpll_ref_clk_in     cpll_ref_clk_in_${n}   "]
-
-  adi_if_infer_bus ADI:user:if_gt_rx slave gt_rx_${n} [list \
-    "rx_p                rx_${n}_p              "\
-    "rx_n                rx_${n}_n              "\
-    "rx_rst              rx_rst_${n}            "\
-    "rx_rst_m            rx_rst_m_${n}          "\
-    "rx_pll_rst          rx_pll_rst_${n}        "\
-    "rx_gt_rst           rx_gt_rst_${n}         "\
-    "rx_gt_rst_m         rx_gt_rst_m_${n}       "\
-    "rx_pll_locked       rx_pll_locked_${n}     "\
-    "rx_pll_locked_m     rx_pll_locked_m_${n}   "\
-    "rx_user_ready       rx_user_ready_${n}     "\
-    "rx_user_ready_m     rx_user_ready_m_${n}   "\
-    "rx_rst_done         rx_rst_done_${n}       "\
-    "rx_rst_done_m       rx_rst_done_m_${n}     "\
-    "rx_out_clk          rx_out_clk_${n}        "\
-    "rx_clk              rx_clk_${n}            "\
-    "rx_sysref           rx_sysref_${n}         "\
-    "rx_sync             rx_sync_${n}           "\
-    "rx_sof              rx_sof_${n}            "\
-    "rx_data             rx_data_${n}           "\
-    "rx_ip_rst           rx_ip_rst_${n}         "\
-    "rx_ip_sof           rx_ip_sof_${n}         "\
-    "rx_ip_data          rx_ip_data_${n}        "\
-    "rx_ip_sysref        rx_ip_sysref_${n}      "\
-    "rx_ip_sync          rx_ip_sync_${n}        "\
-    "rx_ip_rst_done      rx_ip_rst_done_${n}    "]
-
-  adi_if_infer_bus xilinx.com:display_jesd204:jesd204_rx_bus master gt_rx_ip_${n} [list \
-    "rxcharisk           rx_gt_charisk_${n}     "\
-    "rxdisperr           rx_gt_disperr_${n}     "\
-    "rxnotintable        rx_gt_notintable_${n}  "\
-    "rxdata              rx_gt_data_${n}        "]
-
-  adi_if_infer_bus ADI:user:if_gt_rx_ksig master gt_rx_ksig_${n} [list \
-    "rx_gt_ilas_f        rx_gt_ilas_f_${n}      "\
-    "rx_gt_ilas_q        rx_gt_ilas_q_${n}      "\
-    "rx_gt_ilas_a        rx_gt_ilas_a_${n}      "\
-    "rx_gt_ilas_r        rx_gt_ilas_r_${n}      "\
-    "rx_gt_cgs_k         rx_gt_cgs_k_${n}       "]
-
-  adi_if_infer_bus ADI:user:if_gt_tx slave gt_tx_${n} [list \
-    "tx_p                tx_${n}_p              "\
-    "tx_n                tx_${n}_n              "\
-    "tx_rst              tx_rst_${n}            "\
-    "tx_rst_m            tx_rst_m_${n}          "\
-    "tx_pll_rst          tx_pll_rst_${n}        "\
-    "tx_gt_rst           tx_gt_rst_${n}         "\
-    "tx_gt_rst_m         tx_gt_rst_m_${n}       "\
-    "tx_pll_locked       tx_pll_locked_${n}     "\
-    "tx_pll_locked_m     tx_pll_locked_m_${n}   "\
-    "tx_user_ready       tx_user_ready_${n}     "\
-    "tx_user_ready_m     tx_user_ready_m_${n}   "\
-    "tx_rst_done         tx_rst_done_${n}       "\
-    "tx_rst_done_m       tx_rst_done_m_${n}     "\
-    "tx_out_clk          tx_out_clk_${n}        "\
-    "tx_clk              tx_clk_${n}            "\
-    "tx_sysref           tx_sysref_${n}         "\
-    "tx_sync             tx_sync_${n}           "\
-    "tx_data             tx_data_${n}           "\
-    "tx_ip_rst           tx_ip_rst_${n}         "\
-    "tx_ip_data          tx_ip_data_${n}        "\
-    "tx_ip_sysref        tx_ip_sysref_${n}      "\
-    "tx_ip_sync          tx_ip_sync_${n}        "\
-    "tx_ip_rst_done      tx_ip_rst_done_${n}    "]
-
-  adi_if_infer_bus xilinx.com:display_jesd204:jesd204_tx_bus slave gt_tx_ip_${n} [list \
-    "txcharisk           tx_gt_charisk_${n}     "\
-    "txdata              tx_gt_data_${n}        "]
-}
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL0_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_qpll_0 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL1_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_qpll_1 -of_objects [ipx::current_core]]
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
-  [ipx::get_bus_interfaces gt_pll_0 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
-  [ipx::get_bus_interfaces gt_pll_1 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
-  [ipx::get_bus_interfaces gt_pll_2 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
-  [ipx::get_bus_interfaces gt_pll_3 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
-  [ipx::get_bus_interfaces gt_pll_4 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
-  [ipx::get_bus_interfaces gt_pll_5 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
-  [ipx::get_bus_interfaces gt_pll_6 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
-  [ipx::get_bus_interfaces gt_pll_7 -of_objects [ipx::current_core]]
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
-  [ipx::get_bus_interfaces gt_rx_*0 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
-  [ipx::get_bus_interfaces gt_rx_*1 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
-  [ipx::get_bus_interfaces gt_rx_*2 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
-  [ipx::get_bus_interfaces gt_rx_*3 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
-  [ipx::get_bus_interfaces gt_rx_*4 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
-  [ipx::get_bus_interfaces gt_rx_*5 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
-  [ipx::get_bus_interfaces gt_rx_*6 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
-  [ipx::get_bus_interfaces gt_rx_*7 -of_objects [ipx::current_core]]
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
-  [ipx::get_bus_interfaces gt_tx_*0 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
-  [ipx::get_bus_interfaces gt_tx_*1 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
-  [ipx::get_bus_interfaces gt_tx_*2 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
-  [ipx::get_bus_interfaces gt_tx_*3 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
-  [ipx::get_bus_interfaces gt_tx_*4 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
-  [ipx::get_bus_interfaces gt_tx_*5 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
-  [ipx::get_bus_interfaces gt_tx_*6 -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
-  [ipx::get_bus_interfaces gt_tx_*7 -of_objects [ipx::current_core]]
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
-  [ipx::get_ports *rx_*0* -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
-  [ipx::get_ports *rx_*1* -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
-  [ipx::get_ports *rx_*2* -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
-  [ipx::get_ports *rx_*3* -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
-  [ipx::get_ports *rx_*4* -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
-  [ipx::get_ports *rx_*5* -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
-  [ipx::get_ports *rx_*6* -of_objects [ipx::current_core]]
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
-  [ipx::get_ports *rx_*7* -of_objects [ipx::current_core]]
-
-set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
-
-ipx::save_core [ipx::current_core]
-
diff --git a/library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc b/library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc
deleted file mode 100644
index cd93336dc..000000000
--- a/library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc
+++ /dev/null
@@ -1,19 +0,0 @@
-
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync*}]
-
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync_m1_reg && IS_SEQUENTIAL}]
-
-set_false_path -from [get_cells -hier -filter {name =~ *up_rx_preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
-
diff --git a/library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc b/library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc
deleted file mode 100644
index cf1ba45a8..000000000
--- a/library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc
+++ /dev/null
@@ -1,19 +0,0 @@
-
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync*}]
-
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync_m1_reg && IS_SEQUENTIAL}]
-
-set_false_path -from [get_cells -hier -filter {name =~ *up_tx_preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
-
diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr.v b/library/axi_jesd_xcvr/axi_jesd_xcvr.v
deleted file mode 100644
index ada3f5ef7..000000000
--- a/library/axi_jesd_xcvr/axi_jesd_xcvr.v
+++ /dev/null
@@ -1,318 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module axi_jesd_xcvr (
-
-  rst,
-
-  // receive interface
-
-  rx_clk,
-  rx_rstn,
-  rx_ext_sysref_in,
-  rx_ext_sysref_out,
-  rx_sync,
-  rx_sof,
-  rx_data,
-  rx_ready,
-  rx_ip_sysref,
-  rx_ip_sync,
-  rx_ip_sof,
-  rx_ip_valid,
-  rx_ip_data,
-  rx_ip_ready,
-
-  // transmit interface
-
-  tx_clk,
-  tx_rstn,
-  tx_ext_sysref_in,
-  tx_ext_sysref_out,
-  tx_sync,
-  tx_data,
-  tx_ready,
-  tx_ip_sysref,
-  tx_ip_sync,
-  tx_ip_valid,
-  tx_ip_data,
-  tx_ip_ready,
-
-  // axi-lite (slave)
-
-  s_axi_aclk,
-  s_axi_aresetn,
-  s_axi_awvalid,
-  s_axi_awaddr,
-  s_axi_awprot,
-  s_axi_awready,
-  s_axi_wvalid,
-  s_axi_wdata,
-  s_axi_wstrb,
-  s_axi_wready,
-  s_axi_bvalid,
-  s_axi_bresp,
-  s_axi_bready,
-  s_axi_arvalid,
-  s_axi_araddr,
-  s_axi_arprot,
-  s_axi_arready,
-  s_axi_rvalid,
-  s_axi_rdata,
-  s_axi_rresp,
-  s_axi_rready);
-
-  parameter   ID = 0;
-  parameter   DEVICE_TYPE = 0;
-  parameter   TX_NUM_OF_LANES = 4;
-  parameter   RX_NUM_OF_LANES = 4;
-
-  localparam  TX_LANECNT  = (TX_NUM_OF_LANES == 0) ? 1 : TX_NUM_OF_LANES;
-  localparam  RX_LANECNT  = (RX_NUM_OF_LANES == 0) ? 1 : RX_NUM_OF_LANES;
-
-  output                                        rst;
-
-  // receive interface
-
-  input                                         rx_clk;
-  output                                        rx_rstn;
-  input                                         rx_ext_sysref_in;
-  output                                        rx_ext_sysref_out;
-  output                                        rx_sync;
-  output  [((RX_LANECNT* 1)-1):0]               rx_sof;
-  output  [((RX_LANECNT*32)-1):0]               rx_data;
-  input   [((RX_LANECNT* 1)-1):0]               rx_ready;
-  output                                        rx_ip_sysref;
-  input                                         rx_ip_sync;
-  input   [  3:0]                               rx_ip_sof;
-  input                                         rx_ip_valid;
-  input   [((RX_LANECNT*32)-1):0]               rx_ip_data;
-  output                                        rx_ip_ready;
-
-  // transmit interface
-
-  input                                         tx_clk;
-  output                                        tx_rstn;
-  input                                         tx_ext_sysref_in;
-  output                                        tx_ext_sysref_out;
-  input                                         tx_sync;
-  input   [((TX_LANECNT*32)-1):0]               tx_data;
-  input   [((TX_LANECNT* 1)-1):0]               tx_ready;
-  output                                        tx_ip_sysref;
-  output                                        tx_ip_sync;
-  output                                        tx_ip_valid;
-  output  [((TX_LANECNT*32)-1):0]               tx_ip_data;
-  input                                         tx_ip_ready;
-
-  // axi interface
-
-  input                                         s_axi_aclk;        
-  input                                         s_axi_aresetn;     
-  input                                         s_axi_awvalid;     
-  input   [ 31:0]                               s_axi_awaddr;      
-  input   [  2:0]                               s_axi_awprot;      
-  output                                        s_axi_awready;     
-  input                                         s_axi_wvalid;      
-  input   [ 31:0]                               s_axi_wdata;       
-  input   [  3:0]                               s_axi_wstrb;       
-  output                                        s_axi_wready;      
-  output                                        s_axi_bvalid;      
-  output  [  1:0]                               s_axi_bresp;       
-  input                                         s_axi_bready;      
-  input                                         s_axi_arvalid;     
-  input   [ 31:0]                               s_axi_araddr;      
-  input   [  2:0]                               s_axi_arprot;      
-  output                                        s_axi_arready;     
-  output                                        s_axi_rvalid;      
-  output  [ 31:0]                               s_axi_rdata;       
-  output  [  1:0]                               s_axi_rresp;       
-  input                                         s_axi_rready;      
-
-  // internal signals                                        
-
-  wire                                          up_rstn;
-  wire                                          up_clk;
-  wire    [  7:0]                               status_s;
-  wire    [  3:0]                               rx_ip_sof_s;
-  wire    [((RX_LANECNT*32)-1):0]               rx_ip_data_s;
-  wire    [  7:0]                               rx_status_s;
-  wire    [  7:0]                               tx_status_s;
-  wire                                          up_wreq_s;
-  wire    [ 13:0]                               up_waddr_s;
-  wire    [ 31:0]                               up_wdata_s;
-  wire                                          up_wack_s;
-  wire                                          up_rreq_s;
-  wire    [ 13:0]                               up_raddr_s;
-  wire    [ 31:0]                               up_rdata_s;
-  wire                                          up_rack_s;
- 
-  // variables
-                                               
-  genvar                                        n;
-
-  // assignments
-
-  assign status_s = 8'hff;
-  assign up_rstn = s_axi_aresetn;
-  assign up_clk = s_axi_aclk;
-
-  assign rx_ip_ready = 1'b1;
-  assign rx_ip_sysref = rx_ext_sysref_out;
-
-  assign rx_ip_sof_s[3] = rx_ip_sof[0];
-  assign rx_ip_sof_s[2] = rx_ip_sof[1];
-  assign rx_ip_sof_s[1] = rx_ip_sof[2];
-  assign rx_ip_sof_s[0] = rx_ip_sof[3];
-
-  generate
-  for (n = 0; n < RX_LANECNT; n = n + 1) begin: g_rx_swap
-  assign rx_ip_data_s[((n*32) + 31):((n*32) + 24)] = rx_ip_data[((n*32) +  7):((n*32) +  0)];
-  assign rx_ip_data_s[((n*32) + 23):((n*32) + 16)] = rx_ip_data[((n*32) + 15):((n*32) +  8)];
-  assign rx_ip_data_s[((n*32) + 15):((n*32) +  8)] = rx_ip_data[((n*32) + 23):((n*32) + 16)];
-  assign rx_ip_data_s[((n*32) +  7):((n*32) +  0)] = rx_ip_data[((n*32) + 31):((n*32) + 24)];
-  end
-  endgenerate
-
-  generate
-  if (RX_LANECNT < 8) begin
-  assign rx_status_s[7:RX_LANECNT] = status_s[7:RX_LANECNT];
-  assign rx_status_s[(RX_LANECNT-1):0] = rx_ready;
-  end else begin
-  assign rx_status_s = rx_ready[7:0];
-  end
-  endgenerate
-
-  generate
-  for (n = 0; n < RX_LANECNT; n = n + 1) begin: g_rx_align
-  ad_jesd_align i_jesd_align (
-    .rx_clk (rx_clk),
-    .rx_ip_sof (rx_ip_sof_s),
-    .rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
-    .rx_sof (rx_sof[n]),
-    .rx_data (rx_data[n*32+31:n*32]));
-  end
-  endgenerate
-
-  assign tx_ip_valid = 1'b1;
-  assign tx_ip_sysref = tx_ext_sysref_out;
-
-  generate
-  for (n = 0; n < TX_LANECNT; n = n + 1) begin: g_tx_swap
-  assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) +  7):((n*32) +  0)];
-  assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) +  8)];
-  assign tx_ip_data[((n*32) + 15):((n*32) +  8)] = tx_data[((n*32) + 23):((n*32) + 16)];
-  assign tx_ip_data[((n*32) +  7):((n*32) +  0)] = tx_data[((n*32) + 31):((n*32) + 24)];
-  end
-  endgenerate
-
-  generate
-  if (TX_LANECNT < 8) begin
-  assign tx_status_s[7:TX_LANECNT] = status_s[7:TX_LANECNT];
-  assign tx_status_s[(TX_LANECNT-1):0] = tx_ready;
-  end else begin
-  assign tx_status_s = tx_ready[7:0];
-  end
-  endgenerate
-
-  // processor
-    
-  up_xcvr #(
-    .ID(ID),
-    .DEVICE_TYPE(DEVICE_TYPE))
-  i_up_xcvr (
-    .rst (rst),
-    .rx_clk (rx_clk),
-    .rx_rstn (rx_rstn),
-    .rx_ext_sysref (rx_ext_sysref_in),
-    .rx_sysref (rx_ext_sysref_out),
-    .rx_ip_sync (rx_ip_sync),
-    .rx_sync (rx_sync),
-    .rx_status (rx_status_s),
-    .tx_clk (tx_clk),
-    .tx_rstn (tx_rstn),
-    .tx_ext_sysref (tx_ext_sysref_in),
-    .tx_sysref (tx_ext_sysref_out),
-    .tx_sync (tx_sync),
-    .tx_ip_sync (tx_ip_sync),
-    .tx_status (tx_status_s),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq_s),
-    .up_waddr (up_waddr_s),
-    .up_wdata (up_wdata_s),
-    .up_wack (up_wack_s),
-    .up_rreq (up_rreq_s),
-    .up_raddr (up_raddr_s),
-    .up_rdata (up_rdata_s),
-    .up_rack (up_rack_s));
-
-  // axi interface
-
-  up_axi i_up_axi (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_axi_awvalid (s_axi_awvalid),
-    .up_axi_awaddr (s_axi_awaddr),
-    .up_axi_awready (s_axi_awready),
-    .up_axi_wvalid (s_axi_wvalid),
-    .up_axi_wdata (s_axi_wdata),
-    .up_axi_wstrb (s_axi_wstrb),
-    .up_axi_wready (s_axi_wready),
-    .up_axi_bvalid (s_axi_bvalid),
-    .up_axi_bresp (s_axi_bresp),
-    .up_axi_bready (s_axi_bready),
-    .up_axi_arvalid (s_axi_arvalid),
-    .up_axi_araddr (s_axi_araddr),
-    .up_axi_arready (s_axi_arready),
-    .up_axi_rvalid (s_axi_rvalid),
-    .up_axi_rresp (s_axi_rresp),
-    .up_axi_rdata (s_axi_rdata),
-    .up_axi_rready (s_axi_rready),
-    .up_wreq (up_wreq_s),
-    .up_waddr (up_waddr_s),
-    .up_wdata (up_wdata_s),
-    .up_wack (up_wack_s),
-    .up_rreq (up_rreq_s),
-    .up_raddr (up_raddr_s),
-    .up_rdata (up_rdata_s),
-    .up_rack (up_rack_s));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc b/library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc
deleted file mode 100644
index 6f0442c15..000000000
--- a/library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc
+++ /dev/null
@@ -1,12 +0,0 @@
-
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sysref_sel*]        -to [get_registers *up_xcvr:i_up_xcvr|rx_sysref_sel_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sysref*]            -to [get_registers *up_xcvr:i_up_xcvr|rx_up_sysref_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sync*]              -to [get_registers *up_xcvr:i_up_xcvr|rx_up_sync_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sysref_sel*]        -to [get_registers *up_xcvr:i_up_xcvr|tx_sysref_sel_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sysref*]            -to [get_registers *up_xcvr:i_up_xcvr|tx_up_sysref_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sync*]              -to [get_registers *up_xcvr:i_up_xcvr|tx_up_sync_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|rx_sync*]                 -to [get_registers *up_xcvr:i_up_xcvr|up_rx_status_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|tx_ip_sync*]              -to [get_registers *up_xcvr:i_up_xcvr|up_tx_status_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|up_rx_reset*]             -to [get_registers *up_xcvr:i_up_xcvr|ad_rst:i_rx_rst_reg|ad_rst_sync_m1*]
-set_false_path  -from [get_registers *up_xcvr:i_up_xcvr|up_tx_reset*]             -to [get_registers *up_xcvr:i_up_xcvr|ad_rst:i_tx_rst_reg|ad_rst_sync_m1*]
-
diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl b/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
deleted file mode 100755
index 7415ce27a..000000000
--- a/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+++ /dev/null
@@ -1,142 +0,0 @@
-
-
-package require -exact qsys 13.0
-source ../scripts/adi_env.tcl
-source ../scripts/adi_ip_alt.tcl
-
-set_module_property NAME axi_jesd_xcvr
-set_module_property DESCRIPTION "AXI JESD XCVR Interface"
-set_module_property VERSION 1.0
-set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME axi_jesd_xcvr
-set_module_property ELABORATION_CALLBACK p_axi_jesd_xcvr
-
-# files
-
-add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
-set_fileset_property quartus_synth TOP_LEVEL axi_jesd_xcvr
-add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file ad_jesd_align.v          VERILOG PATH $ad_hdl_dir/library/common/ad_jesd_align.v
-add_fileset_file up_axi.v                 VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
-add_fileset_file up_xcvr.v                VERILOG PATH $ad_hdl_dir/library/common/up_xcvr.v
-add_fileset_file axi_jesd_xcvr.v          VERILOG PATH axi_jesd_xcvr.v TOP_LEVEL_FILE
-add_fileset_file axi_jesd_xcvr_constr.sdc SDC     PATH axi_jesd_xcvr_constr.sdc
-
-# parameters
-
-add_parameter ID INTEGER 0
-set_parameter_property ID DEFAULT_VALUE 0
-set_parameter_property ID DISPLAY_NAME ID
-set_parameter_property ID TYPE INTEGER
-set_parameter_property ID UNITS None
-set_parameter_property ID HDL_PARAMETER true
-
-add_parameter DEVICE_TYPE INTEGER 0
-set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
-set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
-set_parameter_property DEVICE_TYPE TYPE INTEGER
-set_parameter_property DEVICE_TYPE UNITS None
-set_parameter_property DEVICE_TYPE HDL_PARAMETER true
-
-add_parameter TX_NUM_OF_LANES INTEGER 0
-set_parameter_property TX_NUM_OF_LANES DEFAULT_VALUE 4
-set_parameter_property TX_NUM_OF_LANES DISPLAY_NAME TX_NUM_OF_LANES
-set_parameter_property TX_NUM_OF_LANES TYPE INTEGER
-set_parameter_property TX_NUM_OF_LANES UNITS None
-set_parameter_property TX_NUM_OF_LANES HDL_PARAMETER true
-
-add_parameter RX_NUM_OF_LANES INTEGER 0
-set_parameter_property RX_NUM_OF_LANES DEFAULT_VALUE 4
-set_parameter_property RX_NUM_OF_LANES DISPLAY_NAME RX_NUM_OF_LANES
-set_parameter_property RX_NUM_OF_LANES TYPE INTEGER
-set_parameter_property RX_NUM_OF_LANES UNITS None
-set_parameter_property RX_NUM_OF_LANES HDL_PARAMETER true
-
-# axi4 slave
-
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
-
-# transceiver interface
-
-ad_alt_intf reset   rst                 output  1 s_axi_clock s_axi_reset
-
-proc p_axi_jesd_xcvr {} {
-
-  set p_num_of_rx_lanes [get_parameter_value "RX_NUM_OF_LANES"]
-  set p_num_of_tx_lanes [get_parameter_value "TX_NUM_OF_LANES"]
-
-  if {$p_num_of_rx_lanes > 0} {
-
-    ad_alt_intf clock   rx_clk              input   1
-    ad_alt_intf reset-n rx_rstn             output  1 if_rx_clk s_axi_reset
-    ad_alt_intf signal  rx_ext_sysref_in    input   1
-    ad_alt_intf signal  rx_ext_sysref_out   output  1
-    ad_alt_intf signal  rx_sync             output  1
-    ad_alt_intf signal  rx_sof              output  $p_num_of_rx_lanes
-    ad_alt_intf signal  rx_data             output  $p_num_of_rx_lanes*32  data
-    ad_alt_intf signal  rx_ready            input   $p_num_of_rx_lanes rx_ready
-    ad_alt_intf signal  rx_ip_sysref        output  1 export
-    ad_alt_intf signal  rx_ip_sync          input   1 export
-    ad_alt_intf signal  rx_ip_sof           input   4 export
- 
-    add_interface if_rx_ip_avl avalon_streaming sink
-    add_interface_port if_rx_ip_avl rx_ip_data  data  input $p_num_of_rx_lanes*32
-    add_interface_port if_rx_ip_avl rx_ip_valid valid input 1
-    add_interface_port if_rx_ip_avl rx_ip_ready ready output 1
- 
-    set_interface_property if_rx_ip_avl associatedClock if_rx_clk
-    set_interface_property if_rx_ip_avl associatedReset if_rx_rstn
-    set_interface_property if_rx_ip_avl dataBitsPerSymbol [expr ($p_num_of_rx_lanes*32)]
-  }
-  
-  if {$p_num_of_tx_lanes > 0} {
-
-    ad_alt_intf clock   tx_clk              input   1
-    ad_alt_intf reset-n tx_rstn             output  1 if_tx_clk s_axi_reset
-    ad_alt_intf signal  tx_ext_sysref_in    input   1
-    ad_alt_intf signal  tx_ext_sysref_out   output  1
-    ad_alt_intf signal  tx_sync             input   1
-    ad_alt_intf signal  tx_data             input   $p_num_of_tx_lanes*32  data
-    ad_alt_intf signal  tx_ready            input   $p_num_of_tx_lanes tx_ready
-    ad_alt_intf signal  tx_ip_sysref        output  1 export
-    ad_alt_intf signal  tx_ip_sync          output  1 export
-
-    add_interface if_tx_ip_avl avalon_streaming source
-    add_interface_port if_tx_ip_avl tx_ip_data  data  output $p_num_of_tx_lanes*32
-    add_interface_port if_tx_ip_avl tx_ip_valid valid output 1
-    add_interface_port if_tx_ip_avl tx_ip_ready ready input 1
-
-    set_interface_property if_tx_ip_avl associatedClock if_tx_clk
-    set_interface_property if_tx_ip_avl associatedReset if_tx_rstn
-    set_interface_property if_tx_ip_avl dataBitsPerSymbol [expr ($p_num_of_tx_lanes*32)]
-  }
-}
-
diff --git a/library/common/up_xcvr.v b/library/common/up_xcvr.v
deleted file mode 100644
index 48d9b6b18..000000000
--- a/library/common/up_xcvr.v
+++ /dev/null
@@ -1,344 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module up_xcvr (
-
-  // common reset
-
-  rst,
-
-  // receive interface
-
-  rx_clk,
-  rx_rstn,
-  rx_ext_sysref,
-  rx_sysref,
-  rx_ip_sync,
-  rx_sync,
-  rx_status,
-
-  // transmit interface
-
-  tx_clk,
-  tx_rstn,
-  tx_ext_sysref,
-  tx_sysref,
-  tx_sync,
-  tx_ip_sync,
-  tx_status,
-
-  // bus interface
-
-  up_rstn,
-  up_clk,
-  up_wreq,
-  up_waddr,
-  up_wdata,
-  up_wack,
-  up_rreq,
-  up_raddr,
-  up_rdata,
-  up_rack);
-
-  // parameters
-
-  localparam  PCORE_VERSION = 32'h00060162;
-  parameter   ID = 0;
-  parameter   DEVICE_TYPE = 0;
-
-  // common reset
-
-  output          rst;
-
-  // receive interface
-
-  input           rx_clk;
-  output          rx_rstn;
-  input           rx_ext_sysref;
-  output          rx_sysref;
-  input           rx_ip_sync;
-  output          rx_sync;
-  input   [ 7:0]  rx_status;
-
-  // transmit interface
-
-  input           tx_clk;
-  output          tx_rstn;
-  input           tx_ext_sysref;
-  output          tx_sysref;
-  input           tx_sync;
-  output          tx_ip_sync;
-  input   [ 7:0]  tx_status;
-
-  // bus interface
-
-  input           up_rstn;
-  input           up_clk;
-  input           up_wreq;
-  input   [13:0]  up_waddr;
-  input   [31:0]  up_wdata;
-  output          up_wack;
-  input           up_rreq;
-  input   [13:0]  up_raddr;
-  output  [31:0]  up_rdata;
-  output          up_rack;
-
-  // internal registers
-
-  reg             up_reset = 'd1;
-  reg             up_rx_reset = 'd1;
-  reg             up_tx_reset = 'd1;
-  reg             up_wack = 'd0;
-  reg     [31:0]  up_scratch = 'd0;
-  reg             up_resetn = 'd0;
-  reg             up_rx_sysref_sel = 'd0;
-  reg             up_rx_sysref = 'd0;
-  reg             up_rx_sync = 'd0;
-  reg             up_rx_resetn = 'd0;
-  reg             up_tx_sysref_sel = 'd0;
-  reg             up_tx_sysref = 'd0;
-  reg             up_tx_sync = 'd0;
-  reg             up_tx_resetn = 'd0;
-  reg             up_rack = 'd0;
-  reg     [31:0]  up_rdata = 'd0;
-  reg             rx_rstn = 'd0;
-  reg             rx_sysref_sel_m1 = 'd0;
-  reg             rx_sysref_sel = 'd0;
-  reg             rx_up_sysref_m1 = 'd0;
-  reg             rx_up_sysref = 'd0;
-  reg             rx_sysref = 'd0;
-  reg             rx_up_sync_m1 = 'd0;
-  reg             rx_up_sync = 'd0;
-  reg             rx_sync = 'd0;
-  reg             tx_rstn = 'd0;
-  reg             tx_sysref_sel_m1 = 'd0;
-  reg             tx_sysref_sel = 'd0;
-  reg             tx_up_sysref_m1 = 'd0;
-  reg             tx_up_sysref = 'd0;
-  reg             tx_sysref = 'd0;
-  reg             tx_up_sync_m1 = 'd0;
-  reg             tx_up_sync = 'd0;
-  reg             tx_ip_sync = 'd0;
-  reg     [ 8:0]  up_rx_status_m1 = 'd0;
-  reg     [ 8:0]  up_rx_status = 'd0;
-  reg     [ 8:0]  up_tx_status_m1 = 'd0;
-  reg     [ 8:0]  up_tx_status = 'd0;
-
-  // internal signals
-
-  wire            rx_rst;
-  wire            tx_rst;
-  wire            up_wreq_s;
-  wire            up_rreq_s;
-
-  // decode block select
-
-  assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
-  assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
-
-  // processor write interface
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_reset <= 1'b1;
-      up_rx_reset <= 1'b1;
-      up_tx_reset <= 1'b1;
-      up_wack <= 'd0;
-      up_scratch <= 'd0;
-      up_resetn <= 'd0;
-      up_rx_sysref_sel <= 'd0;
-      up_rx_sysref <= 'd0;
-      up_rx_sync <= 'd0;
-      up_rx_resetn <= 'd0;
-      up_tx_sysref_sel <= 'd0;
-      up_tx_sysref <= 'd0;
-      up_tx_sync <= 'd0;
-      up_tx_resetn <= 'd0;
-    end else begin
-      up_reset <= ~up_resetn;
-      up_rx_reset <= ~(up_resetn & up_rx_resetn);
-      up_tx_reset <= ~(up_resetn & up_tx_resetn);
-      up_wack <= up_wreq_s;
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
-        up_scratch <= up_wdata;
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h03)) begin
-        up_resetn <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
-        up_rx_sysref_sel <= up_wdata[1];
-        up_rx_sysref <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
-        up_rx_sync <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
-        up_rx_resetn <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
-        up_tx_sysref_sel <= up_wdata[1];
-        up_tx_sysref <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
-        up_tx_sync <= up_wdata[0];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
-        up_tx_resetn <= up_wdata[0];
-      end
-    end
-  end
-
-  // processor read interface
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
-    end else begin
-      up_rack <= up_rreq_s;
-      if (up_rreq_s == 1'b1) begin
-        case (up_raddr[7:0])
-          8'h00: up_rdata <= PCORE_VERSION;
-          8'h01: up_rdata <= ID;
-          8'h02: up_rdata <= up_scratch;
-          8'h03: up_rdata <= {31'd0, up_resetn};
-          8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
-          8'h11: up_rdata <= {31'd0, up_rx_sync};
-          8'h12: up_rdata <= {23'd0, up_rx_status};
-          8'h13: up_rdata <= {31'd0, up_rx_resetn};
-          8'h20: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
-          8'h21: up_rdata <= {31'd0, up_tx_sync};
-          8'h22: up_rdata <= {23'd0, up_tx_status};
-          8'h23: up_rdata <= {31'd0, up_tx_resetn};
-          8'h30: up_rdata <= DEVICE_TYPE;
-          default: up_rdata <= 0;
-        endcase
-      end else begin
-        up_rdata <= 32'd0;
-      end
-    end
-  end
-
-  // resets
-
-  assign rst = up_reset;
-
-  ad_rst i_rx_rst_reg (.preset(up_rx_reset), .clk(rx_clk), .rst(rx_rst));
-  ad_rst i_tx_rst_reg (.preset(up_tx_reset), .clk(tx_clk), .rst(tx_rst));
-
-  // rx sysref & sync
-
-  always @(posedge rx_clk or posedge rx_rst) begin
-    if (rx_rst == 1'b1) begin
-      rx_rstn <= 'd0;
-      rx_sysref_sel_m1 <= 'd0;
-      rx_sysref_sel <= 'd0;
-      rx_up_sysref_m1 <= 'd0;
-      rx_up_sysref <= 'd0;
-      rx_sysref <= 'd0;
-      rx_up_sync_m1 <= 'd0;
-      rx_up_sync <= 'd0;
-      rx_sync <= 'd0;
-    end else begin
-      rx_rstn <= 1'd1;
-      rx_sysref_sel_m1 <= up_rx_sysref_sel;
-      rx_sysref_sel <= rx_sysref_sel_m1;
-      rx_up_sysref_m1 <= up_rx_sysref;
-      rx_up_sysref <= rx_up_sysref_m1;
-      if (rx_sysref_sel == 1'b1) begin
-        rx_sysref <= rx_ext_sysref;
-      end else begin
-        rx_sysref <= rx_up_sysref;
-      end
-      rx_up_sync_m1 <= up_rx_sync;
-      rx_up_sync <= rx_up_sync_m1;
-      rx_sync <= rx_up_sync & rx_ip_sync;
-    end
-  end
-
-  // tx sysref & sync
-
-  always @(posedge tx_clk or posedge tx_rst) begin
-    if (tx_rst == 1'b1) begin
-      tx_rstn <= 'd0;
-      tx_sysref_sel_m1 <= 'd0;
-      tx_sysref_sel <= 'd0;
-      tx_up_sysref_m1 <= 'd0;
-      tx_up_sysref <= 'd0;
-      tx_sysref <= 'd0;
-      tx_up_sync_m1 <= 'd0;
-      tx_up_sync <= 'd0;
-      tx_ip_sync <= 'd0;
-    end else begin
-      tx_rstn <= 1'd1;
-      tx_sysref_sel_m1 <= up_tx_sysref_sel;
-      tx_sysref_sel <= tx_sysref_sel_m1;
-      tx_up_sysref_m1 <= up_tx_sysref;
-      tx_up_sysref <= tx_up_sysref_m1;
-      if (tx_sysref_sel == 1'b1) begin
-        tx_sysref <= tx_ext_sysref;
-      end else begin
-        tx_sysref <= tx_up_sysref;
-      end
-      tx_up_sync_m1 <= up_tx_sync;
-      tx_up_sync <= tx_up_sync_m1;
-      tx_ip_sync <= tx_up_sync & tx_sync;
-    end
-  end
-
-  // status
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_rx_status_m1 <= 'd0;
-      up_rx_status <= 'd0;
-      up_tx_status_m1 <= 'd0;
-      up_tx_status <= 'd0;
-    end else begin
-      up_rx_status_m1 <= {rx_sync, rx_status};
-      up_rx_status <= up_rx_status_m1;
-      up_tx_status_m1 <= {tx_ip_sync, tx_status};
-      up_tx_status <= up_tx_status_m1;
-    end
-  end
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From 9d6c93a5d860e45405e133558f55722aec3cfe04 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Mon, 14 Nov 2016 15:17:15 +0200
Subject: [PATCH 700/972] Fix warnings

---
 library/axi_ad7616/axi_ad7616_control.v       |  1 +
 library/axi_ad9162/axi_ad9162_core.v          |  1 +
 library/axi_ad9361/axi_ad9361.v               |  9 ++++-
 library/axi_dmac/axi_dmac.v                   |  4 +--
 library/axi_mc_controller/control_registers.v |  1 +
 library/xilinx/util_adxcvr/util_adxcvr_xch.v  | 35 +++++++++++++++++++
 library/xilinx/util_adxcvr/util_adxcvr_xcm.v  |  3 ++
 7 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index bc40f101d..af013aa96 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -150,6 +150,7 @@ module axi_ad7616_control (
       up_cnvst_en <= 1'b0;
       up_conv_rate <= 32'b0;
       up_burst_length <= 5'h0;
+      up_write_data <= 16'h0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v
index 7bfbbdcd7..8f8555716 100644
--- a/library/axi_ad9162/axi_ad9162_core.v
+++ b/library/axi_ad9162/axi_ad9162_core.v
@@ -166,6 +166,7 @@ module axi_ad9162_core (
       .dac_rst (dac_rst),
       .dac_sync (dac_sync_s),
       .dac_frame (),
+      .dac_clksel (),
       .dac_par_type (),
       .dac_par_enb (),
       .dac_r1_mode (),
diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index af6ea017b..7324d28d6 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -272,7 +272,14 @@ module axi_ad9361 #(
   wire            tdd_rx_rf_en_s;
   wire            tdd_tx_rf_en_s;
   wire    [ 7:0]  tdd_status_s;
-    
+  wire            up_drp_sel;
+  wire            up_drp_wr;
+  wire    [11:0]  up_drp_addr;
+  wire    [31:0]  up_drp_wdata;
+  wire    [31:0]  up_drp_rdata;
+  wire            up_drp_ready;
+  wire            up_drp_locked;
+
   // signal name changes
 
   assign up_clk = s_axi_aclk;
diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
index ac698bd36..f5332bcfc 100644
--- a/library/axi_dmac/axi_dmac.v
+++ b/library/axi_dmac/axi_dmac.v
@@ -42,7 +42,7 @@ module axi_dmac (
   input s_axi_aresetn,
 
   input         s_axi_awvalid,
-  input  [13:0] s_axi_awaddr,
+  input  [31:0] s_axi_awaddr,
   output        s_axi_awready,
   input   [2:0] s_axi_awprot,
   input         s_axi_wvalid,
@@ -53,7 +53,7 @@ module axi_dmac (
   output [ 1:0] s_axi_bresp,
   input         s_axi_bready,
   input         s_axi_arvalid,
-  input  [13:0] s_axi_araddr,
+  input  [31:0] s_axi_araddr,
   output        s_axi_arready,
   input   [2:0] s_axi_arprot,
   output        s_axi_rvalid,
diff --git a/library/axi_mc_controller/control_registers.v b/library/axi_mc_controller/control_registers.v
index 589234e97..ed72e73dc 100644
--- a/library/axi_mc_controller/control_registers.v
+++ b/library/axi_mc_controller/control_registers.v
@@ -130,6 +130,7 @@ always @(negedge up_rstn or posedge up_clk)
 begin
    if (up_rstn == 0)
    begin
+       reserved_r1          <= 'd0;
        up_wack              <= 1'b0;
        control_r            <= 'h0;
        reference_speed_r    <= 'd1000;
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 01624a725..08066de4b 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -526,6 +526,41 @@ module util_adxcvr_xch #(
     .TX_XCLK_SEL ("TXOUT"),
     .UCODEER_CLR (1'b0))
   i_gtxe2_channel (
+    .RXOUTCLKPCS (),
+    .RXPHSLIPMONITOR (),
+    .PHYSTATUS (),
+    .RXCDRLOCK (),
+    .RXCHANBONDSEQ (),
+    .RXCHANISALIGNED (),
+    .RXCHANREALIGN (),
+    .RXCOMINITDET (),
+    .RXCOMSASDET (),
+    .RXCOMWAKEDET (),
+    .RXDATAVALID (),
+    .RXDLYSRESETDONE (),
+    .RXELECIDLE (),
+    .RXHEADERVALID (),
+    .RXPHALIGNDONE (),
+    .RXQPISENN (),
+    .RXQPISENP (),
+    .RXRATEDONE (),
+    .RXSTARTOFSEQ (),
+    .RXVALID (),
+    .TXCOMFINISH (),
+    .TXDLYSRESETDONE (),
+    .TXGEARBOXREADY (),
+    .TXPHALIGNDONE (),
+    .TXPHINITDONE (),
+    .TXQPISENN (),
+    .TXQPISENP (),
+    .TXRATEDONE (),
+    .PCSRSVDOUT (),
+    .RXCLKCORCNT (),
+    .RXHEADER (),
+    .RXCHBONDO (),
+    .RXPHMONITOR (),
+    .TSTOUT (),
+    .GTREFCLKMONITOR (),
     .CFGRESET (1'h0),
     .CLKRSVD (4'h0),
     .CPLLFBCLKLOST (),
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
index a13956ab7..75128cb50 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
@@ -142,6 +142,9 @@ module util_adxcvr_xcm #(
     .SIM_RESET_SPEEDUP ("TRUE"),
     .SIM_VERSION ("4.0"))
   i_gtxe2_common (
+    .QPLLDMONITOR (),
+    .QPLLFBCLKLOST (),
+    .REFCLKOUTMONITOR (),
     .BGBYPASSB (1'h1),
     .BGMONITORENB (1'h1),
     .BGPDB (1'h1),

From cfd3ea61f1496635ae7fc59d5821379b8eb0bbf7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 14 Nov 2016 14:12:22 -0500
Subject: [PATCH 701/972] pzsdr-to-pzsdr2

---
 projects/{pzsdr => pzsdr2}/Makefile                      | 0
 projects/{pzsdr => pzsdr2}/ccbrk_cmos/Makefile           | 0
 projects/{pzsdr => pzsdr2}/ccbrk_cmos/system_bd.tcl      | 0
 projects/{pzsdr => pzsdr2}/ccbrk_cmos/system_project.tcl | 0
 projects/{pzsdr => pzsdr2}/ccbrk_cmos/system_top.v       | 0
 projects/{pzsdr => pzsdr2}/ccbrk_lvds/Makefile           | 0
 projects/{pzsdr => pzsdr2}/ccbrk_lvds/system_bd.tcl      | 0
 projects/{pzsdr => pzsdr2}/ccbrk_lvds/system_constr.xdc  | 0
 projects/{pzsdr => pzsdr2}/ccbrk_lvds/system_project.tcl | 0
 projects/{pzsdr => pzsdr2}/ccbrk_lvds/system_top.v       | 0
 projects/{pzsdr => pzsdr2}/ccfmc_lvds/Makefile           | 0
 projects/{pzsdr => pzsdr2}/ccfmc_lvds/system_bd.tcl      | 0
 projects/{pzsdr => pzsdr2}/ccfmc_lvds/system_constr.xdc  | 0
 projects/{pzsdr => pzsdr2}/ccfmc_lvds/system_project.tcl | 0
 projects/{pzsdr => pzsdr2}/ccfmc_lvds/system_top.v       | 0
 projects/{pzsdr => pzsdr2}/ccpci_lvds/Makefile           | 0
 projects/{pzsdr => pzsdr2}/ccpci_lvds/system_bd.tcl      | 0
 projects/{pzsdr => pzsdr2}/ccpci_lvds/system_constr.xdc  | 0
 projects/{pzsdr => pzsdr2}/ccpci_lvds/system_project.tcl | 0
 projects/{pzsdr => pzsdr2}/ccpci_lvds/system_top.v       | 0
 projects/{pzsdr => pzsdr2}/ccusb_lvds/Makefile           | 0
 projects/{pzsdr => pzsdr2}/ccusb_lvds/system_bd.tcl      | 0
 projects/{pzsdr => pzsdr2}/ccusb_lvds/system_constr.xdc  | 0
 projects/{pzsdr => pzsdr2}/ccusb_lvds/system_project.tcl | 0
 projects/{pzsdr => pzsdr2}/ccusb_lvds/system_top.v       | 0
 projects/{pzsdr => pzsdr2}/common/ccbrk_bd.tcl           | 0
 projects/{pzsdr => pzsdr2}/common/ccfmc_bd.tcl           | 0
 projects/{pzsdr => pzsdr2}/common/ccpci_bd.tcl           | 0
 projects/{pzsdr => pzsdr2}/common/ccusb_bd.tcl           | 0
 29 files changed, 0 insertions(+), 0 deletions(-)
 rename projects/{pzsdr => pzsdr2}/Makefile (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_cmos/Makefile (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_cmos/system_bd.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_cmos/system_project.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_cmos/system_top.v (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_lvds/Makefile (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_lvds/system_bd.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_lvds/system_constr.xdc (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_lvds/system_project.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccbrk_lvds/system_top.v (100%)
 rename projects/{pzsdr => pzsdr2}/ccfmc_lvds/Makefile (100%)
 rename projects/{pzsdr => pzsdr2}/ccfmc_lvds/system_bd.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccfmc_lvds/system_constr.xdc (100%)
 rename projects/{pzsdr => pzsdr2}/ccfmc_lvds/system_project.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccfmc_lvds/system_top.v (100%)
 rename projects/{pzsdr => pzsdr2}/ccpci_lvds/Makefile (100%)
 rename projects/{pzsdr => pzsdr2}/ccpci_lvds/system_bd.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccpci_lvds/system_constr.xdc (100%)
 rename projects/{pzsdr => pzsdr2}/ccpci_lvds/system_project.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccpci_lvds/system_top.v (100%)
 rename projects/{pzsdr => pzsdr2}/ccusb_lvds/Makefile (100%)
 rename projects/{pzsdr => pzsdr2}/ccusb_lvds/system_bd.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccusb_lvds/system_constr.xdc (100%)
 rename projects/{pzsdr => pzsdr2}/ccusb_lvds/system_project.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/ccusb_lvds/system_top.v (100%)
 rename projects/{pzsdr => pzsdr2}/common/ccbrk_bd.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/common/ccfmc_bd.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/common/ccpci_bd.tcl (100%)
 rename projects/{pzsdr => pzsdr2}/common/ccusb_bd.tcl (100%)

diff --git a/projects/pzsdr/Makefile b/projects/pzsdr2/Makefile
similarity index 100%
rename from projects/pzsdr/Makefile
rename to projects/pzsdr2/Makefile
diff --git a/projects/pzsdr/ccbrk_cmos/Makefile b/projects/pzsdr2/ccbrk_cmos/Makefile
similarity index 100%
rename from projects/pzsdr/ccbrk_cmos/Makefile
rename to projects/pzsdr2/ccbrk_cmos/Makefile
diff --git a/projects/pzsdr/ccbrk_cmos/system_bd.tcl b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
similarity index 100%
rename from projects/pzsdr/ccbrk_cmos/system_bd.tcl
rename to projects/pzsdr2/ccbrk_cmos/system_bd.tcl
diff --git a/projects/pzsdr/ccbrk_cmos/system_project.tcl b/projects/pzsdr2/ccbrk_cmos/system_project.tcl
similarity index 100%
rename from projects/pzsdr/ccbrk_cmos/system_project.tcl
rename to projects/pzsdr2/ccbrk_cmos/system_project.tcl
diff --git a/projects/pzsdr/ccbrk_cmos/system_top.v b/projects/pzsdr2/ccbrk_cmos/system_top.v
similarity index 100%
rename from projects/pzsdr/ccbrk_cmos/system_top.v
rename to projects/pzsdr2/ccbrk_cmos/system_top.v
diff --git a/projects/pzsdr/ccbrk_lvds/Makefile b/projects/pzsdr2/ccbrk_lvds/Makefile
similarity index 100%
rename from projects/pzsdr/ccbrk_lvds/Makefile
rename to projects/pzsdr2/ccbrk_lvds/Makefile
diff --git a/projects/pzsdr/ccbrk_lvds/system_bd.tcl b/projects/pzsdr2/ccbrk_lvds/system_bd.tcl
similarity index 100%
rename from projects/pzsdr/ccbrk_lvds/system_bd.tcl
rename to projects/pzsdr2/ccbrk_lvds/system_bd.tcl
diff --git a/projects/pzsdr/ccbrk_lvds/system_constr.xdc b/projects/pzsdr2/ccbrk_lvds/system_constr.xdc
similarity index 100%
rename from projects/pzsdr/ccbrk_lvds/system_constr.xdc
rename to projects/pzsdr2/ccbrk_lvds/system_constr.xdc
diff --git a/projects/pzsdr/ccbrk_lvds/system_project.tcl b/projects/pzsdr2/ccbrk_lvds/system_project.tcl
similarity index 100%
rename from projects/pzsdr/ccbrk_lvds/system_project.tcl
rename to projects/pzsdr2/ccbrk_lvds/system_project.tcl
diff --git a/projects/pzsdr/ccbrk_lvds/system_top.v b/projects/pzsdr2/ccbrk_lvds/system_top.v
similarity index 100%
rename from projects/pzsdr/ccbrk_lvds/system_top.v
rename to projects/pzsdr2/ccbrk_lvds/system_top.v
diff --git a/projects/pzsdr/ccfmc_lvds/Makefile b/projects/pzsdr2/ccfmc_lvds/Makefile
similarity index 100%
rename from projects/pzsdr/ccfmc_lvds/Makefile
rename to projects/pzsdr2/ccfmc_lvds/Makefile
diff --git a/projects/pzsdr/ccfmc_lvds/system_bd.tcl b/projects/pzsdr2/ccfmc_lvds/system_bd.tcl
similarity index 100%
rename from projects/pzsdr/ccfmc_lvds/system_bd.tcl
rename to projects/pzsdr2/ccfmc_lvds/system_bd.tcl
diff --git a/projects/pzsdr/ccfmc_lvds/system_constr.xdc b/projects/pzsdr2/ccfmc_lvds/system_constr.xdc
similarity index 100%
rename from projects/pzsdr/ccfmc_lvds/system_constr.xdc
rename to projects/pzsdr2/ccfmc_lvds/system_constr.xdc
diff --git a/projects/pzsdr/ccfmc_lvds/system_project.tcl b/projects/pzsdr2/ccfmc_lvds/system_project.tcl
similarity index 100%
rename from projects/pzsdr/ccfmc_lvds/system_project.tcl
rename to projects/pzsdr2/ccfmc_lvds/system_project.tcl
diff --git a/projects/pzsdr/ccfmc_lvds/system_top.v b/projects/pzsdr2/ccfmc_lvds/system_top.v
similarity index 100%
rename from projects/pzsdr/ccfmc_lvds/system_top.v
rename to projects/pzsdr2/ccfmc_lvds/system_top.v
diff --git a/projects/pzsdr/ccpci_lvds/Makefile b/projects/pzsdr2/ccpci_lvds/Makefile
similarity index 100%
rename from projects/pzsdr/ccpci_lvds/Makefile
rename to projects/pzsdr2/ccpci_lvds/Makefile
diff --git a/projects/pzsdr/ccpci_lvds/system_bd.tcl b/projects/pzsdr2/ccpci_lvds/system_bd.tcl
similarity index 100%
rename from projects/pzsdr/ccpci_lvds/system_bd.tcl
rename to projects/pzsdr2/ccpci_lvds/system_bd.tcl
diff --git a/projects/pzsdr/ccpci_lvds/system_constr.xdc b/projects/pzsdr2/ccpci_lvds/system_constr.xdc
similarity index 100%
rename from projects/pzsdr/ccpci_lvds/system_constr.xdc
rename to projects/pzsdr2/ccpci_lvds/system_constr.xdc
diff --git a/projects/pzsdr/ccpci_lvds/system_project.tcl b/projects/pzsdr2/ccpci_lvds/system_project.tcl
similarity index 100%
rename from projects/pzsdr/ccpci_lvds/system_project.tcl
rename to projects/pzsdr2/ccpci_lvds/system_project.tcl
diff --git a/projects/pzsdr/ccpci_lvds/system_top.v b/projects/pzsdr2/ccpci_lvds/system_top.v
similarity index 100%
rename from projects/pzsdr/ccpci_lvds/system_top.v
rename to projects/pzsdr2/ccpci_lvds/system_top.v
diff --git a/projects/pzsdr/ccusb_lvds/Makefile b/projects/pzsdr2/ccusb_lvds/Makefile
similarity index 100%
rename from projects/pzsdr/ccusb_lvds/Makefile
rename to projects/pzsdr2/ccusb_lvds/Makefile
diff --git a/projects/pzsdr/ccusb_lvds/system_bd.tcl b/projects/pzsdr2/ccusb_lvds/system_bd.tcl
similarity index 100%
rename from projects/pzsdr/ccusb_lvds/system_bd.tcl
rename to projects/pzsdr2/ccusb_lvds/system_bd.tcl
diff --git a/projects/pzsdr/ccusb_lvds/system_constr.xdc b/projects/pzsdr2/ccusb_lvds/system_constr.xdc
similarity index 100%
rename from projects/pzsdr/ccusb_lvds/system_constr.xdc
rename to projects/pzsdr2/ccusb_lvds/system_constr.xdc
diff --git a/projects/pzsdr/ccusb_lvds/system_project.tcl b/projects/pzsdr2/ccusb_lvds/system_project.tcl
similarity index 100%
rename from projects/pzsdr/ccusb_lvds/system_project.tcl
rename to projects/pzsdr2/ccusb_lvds/system_project.tcl
diff --git a/projects/pzsdr/ccusb_lvds/system_top.v b/projects/pzsdr2/ccusb_lvds/system_top.v
similarity index 100%
rename from projects/pzsdr/ccusb_lvds/system_top.v
rename to projects/pzsdr2/ccusb_lvds/system_top.v
diff --git a/projects/pzsdr/common/ccbrk_bd.tcl b/projects/pzsdr2/common/ccbrk_bd.tcl
similarity index 100%
rename from projects/pzsdr/common/ccbrk_bd.tcl
rename to projects/pzsdr2/common/ccbrk_bd.tcl
diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr2/common/ccfmc_bd.tcl
similarity index 100%
rename from projects/pzsdr/common/ccfmc_bd.tcl
rename to projects/pzsdr2/common/ccfmc_bd.tcl
diff --git a/projects/pzsdr/common/ccpci_bd.tcl b/projects/pzsdr2/common/ccpci_bd.tcl
similarity index 100%
rename from projects/pzsdr/common/ccpci_bd.tcl
rename to projects/pzsdr2/common/ccpci_bd.tcl
diff --git a/projects/pzsdr/common/ccusb_bd.tcl b/projects/pzsdr2/common/ccusb_bd.tcl
similarity index 100%
rename from projects/pzsdr/common/ccusb_bd.tcl
rename to projects/pzsdr2/common/ccusb_bd.tcl

From cac4057449e72d226b419e3adaac2271bfac3f4b Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Thu, 10 Nov 2016 16:21:52 +0200
Subject: [PATCH 702/972] daq2/common: Altera updates

---
 projects/daq2/common/daq2_qsys.tcl | 72 +++++++++++-------------------
 1 file changed, 26 insertions(+), 46 deletions(-)

diff --git a/projects/daq2/common/daq2_qsys.tcl b/projects/daq2/common/daq2_qsys.tcl
index d831ead53..e4207aca3 100644
--- a/projects/daq2/common/daq2_qsys.tcl
+++ b/projects/daq2/common/daq2_qsys.tcl
@@ -40,9 +40,6 @@ add_connection avl_ad9144_xcvr.tx_ip_d_0 avl_ad9144_xcvr.tx_phy_d_0
 add_connection avl_ad9144_xcvr.tx_ip_d_3 avl_ad9144_xcvr.tx_phy_d_1
 add_connection avl_ad9144_xcvr.tx_ip_d_1 avl_ad9144_xcvr.tx_phy_d_2
 add_connection avl_ad9144_xcvr.tx_ip_d_2 avl_ad9144_xcvr.tx_phy_d_3
-add_connection sys_cpu.data_master avl_ad9144_xcvr.core_pll_reconfig
-add_connection sys_cpu.data_master avl_ad9144_xcvr.lane_pll_reconfig
-add_connection sys_cpu.data_master avl_ad9144_xcvr.ip_reconfig
 
 # ad9144-xcvr
 
@@ -56,7 +53,6 @@ add_connection sys_clk.clk_reset axi_ad9144_xcvr.s_axi_reset
 add_connection axi_ad9144_xcvr.if_up_rst avl_ad9144_xcvr.rst
 add_connection avl_ad9144_xcvr.ready axi_ad9144_xcvr.ready
 add_connection axi_ad9144_xcvr.core_pll_locked avl_ad9144_xcvr.core_pll_locked
-add_connection sys_cpu.data_master axi_ad9144_xcvr.s_axi
 
 # ad9144-core
 
@@ -67,7 +63,6 @@ add_connection avl_ad9144_xcvr.core_clk axi_ad9144_core.if_tx_clk
 add_connection axi_ad9144_core.if_tx_data avl_ad9144_xcvr.ip_data
 add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
-add_connection sys_cpu.data_master axi_ad9144_core.s_axi
 
 # ad9144-unpack
 
@@ -94,11 +89,8 @@ add_connection util_ad9144_upack.if_dac_data axi_ad9144_dma.if_fifo_rd_dout
 add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf
 add_connection sys_clk.clk_reset axi_ad9144_dma.s_axi_reset
 add_connection sys_clk.clk axi_ad9144_dma.s_axi_clock
-add_connection sys_cpu.data_master axi_ad9144_dma.s_axi
 add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9144_dma.m_src_axi_reset
 add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9144_dma.m_src_axi_clock
-add_connection axi_ad9144_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
-add_connection sys_cpu.irq axi_ad9144_dma.interrupt_sender
 
 # ad9680-xcvr
 
@@ -133,8 +125,6 @@ add_interface rx_sysref conduit end
 set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref
 add_interface rx_sync conduit end
 set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync
-add_connection sys_cpu.data_master avl_ad9680_xcvr.core_pll_reconfig
-add_connection sys_cpu.data_master avl_ad9680_xcvr.ip_reconfig
 
 # ad9680-xcvr
 
@@ -148,7 +138,6 @@ add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset
 add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst
 add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready
 add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked
-add_connection sys_cpu.data_master axi_ad9680_xcvr.s_axi
 
 # ad9680
 
@@ -159,7 +148,6 @@ add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof
 add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
 add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
-add_connection sys_cpu.data_master axi_ad9680_core.s_axi
 
 # ad9680-pack
 
@@ -207,71 +195,63 @@ add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
 add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
 add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
 add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
-add_connection sys_cpu.data_master axi_ad9680_dma.s_axi
 add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset
 add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
-add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
-add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
 
 # reconfig sharing
 
 add_instance avl_adxcfg_0 avl_adxcfg 1.0
 add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
 add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
-add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s0
-add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s1
 add_connection avl_adxcfg_0.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_0
 add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0
 
 add_instance avl_adxcfg_1 avl_adxcfg 1.0
 add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
 add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
-add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s0
-add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s1
 add_connection avl_adxcfg_1.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_1
 add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1
 
 add_instance avl_adxcfg_2 avl_adxcfg 1.0
 add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
 add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
-add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s0
-add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s1
 add_connection avl_adxcfg_2.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_2
 add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2
 
 add_instance avl_adxcfg_3 avl_adxcfg 1.0
 add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
 add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
-add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s0
-add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s1
 add_connection avl_adxcfg_3.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_3
 add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3
 
 # addresses
 
-set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.core_pll_reconfig      baseAddress {0x10400000}
-set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.ip_reconfig            baseAddress {0x10401000}
-set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.lane_pll_reconfig      baseAddress {0x10402000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9144_dma.s_axi                   baseAddress {0x1040c000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9144_xcvr.s_axi                  baseAddress {0x10410000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9144_core.s_axi                  baseAddress {0x10420000}
-set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.core_pll_reconfig      baseAddress {0x10500000}
-set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.ip_reconfig            baseAddress {0x10501000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi                   baseAddress {0x1050c000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9680_xcvr.s_axi                  baseAddress {0x10510000}
-set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi                  baseAddress {0x10520000}
-set_connection_parameter_value axi_ad9144_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0         baseAddress {0x00000000}
-set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0        baseAddress {0x00000000}
-set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s0                   baseAddress {0x10404000}
-set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s0                   baseAddress {0x10405000}
-set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s0                   baseAddress {0x10406000}
-set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s0                   baseAddress {0x10407000}
-set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s1                   baseAddress {0x10504000}
-set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s1                   baseAddress {0x10505000}
-set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s1                   baseAddress {0x10506000}
-set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s1                   baseAddress {0x10507000}
+ad_cpu_interconnect 0x10404000 avl_adxcfg_0.rcfg_s0
+ad_cpu_interconnect 0x10504000 avl_adxcfg_0.rcfg_s1
+ad_cpu_interconnect 0x10405000 avl_adxcfg_1.rcfg_s0
+ad_cpu_interconnect 0x10505000 avl_adxcfg_1.rcfg_s1
+ad_cpu_interconnect 0x10406000 avl_adxcfg_2.rcfg_s0
+ad_cpu_interconnect 0x10506000 avl_adxcfg_2.rcfg_s1
+ad_cpu_interconnect 0x10407000 avl_adxcfg_3.rcfg_s0
+ad_cpu_interconnect 0x10507000 avl_adxcfg_3.rcfg_s1
+ad_cpu_interconnect 0x10400000 avl_ad9144_xcvr.core_pll_reconfig
+ad_cpu_interconnect 0x10402000 avl_ad9144_xcvr.lane_pll_reconfig
+ad_cpu_interconnect 0x10401000 avl_ad9144_xcvr.ip_reconfig
+ad_cpu_interconnect 0x1040c000 axi_ad9144_dma.s_axi
+ad_cpu_interconnect 0x10410000 axi_ad9144_xcvr.s_axi
+ad_cpu_interconnect 0x10420000 axi_ad9144_core.s_axi
+ad_cpu_interconnect 0x10500000 avl_ad9680_xcvr.core_pll_reconfig
+ad_cpu_interconnect 0x10501000 avl_ad9680_xcvr.ip_reconfig
+ad_cpu_interconnect 0x1050c000 axi_ad9680_dma.s_axi
+ad_cpu_interconnect 0x10510000 axi_ad9680_xcvr.s_axi
+ad_cpu_interconnect 0x10520000 axi_ad9680_core.s_axi
+
+# dma interconnects
+
+ad_dma_interconnect axi_ad9144_dma.m_src_axi
+ad_dma_interconnect axi_ad9680_dma.m_dest_axi
 
 # interrupts
 
-set_connection_parameter_value sys_cpu.irq/axi_ad9144_dma.interrupt_sender irqNumber {11}
-set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}
+ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender
+ad_cpu_interrupt 11 axi_ad9144_dma.interrupt_sender

From 08977161670f02afaa53a317f482c0cde38142a7 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Mon, 14 Nov 2016 15:59:09 +0200
Subject: [PATCH 703/972] fmcadc4: xcvr updates

---
 projects/fmcadc4/common/fmcadc4_bd.tcl    | 101 +++++-----------------
 projects/fmcadc4/zc706/Makefile           |  12 +--
 projects/fmcadc4/zc706/system_bd.tcl      |  36 --------
 projects/fmcadc4/zc706/system_constr.xdc  |   3 +-
 projects/fmcadc4/zc706/system_project.tcl |   2 -
 projects/fmcadc4/zc706/system_top.v       |  24 +++--
 6 files changed, 48 insertions(+), 130 deletions(-)

diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl
index c4a910818..5c70a6179 100644
--- a/projects/fmcadc4/common/fmcadc4_bd.tcl
+++ b/projects/fmcadc4/common/fmcadc4_bd.tcl
@@ -1,12 +1,6 @@
 
 # fmcadc4
 
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir I rx_sysref
-create_bd_port -dir I -from 7 -to 0 rx_data_p
-create_bd_port -dir I -from 7 -to 0 rx_data_n
-
 # adc peripherals
 
 set axi_ad9680_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_0]
@@ -14,6 +8,11 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0
 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1]
 set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1
 
+set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9680_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9680_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
+
 set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd
@@ -37,22 +36,8 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9680_cpack
 
 # adc common gt
 
-set axi_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc4_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc4_gt
-set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $axi_fmcadc4_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $axi_fmcadc4_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc4_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc4_gt
-set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcadc4_gt
-
-set util_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc4_gt]
-set_property -dict [list CONFIG.QPLL_TX_OR_RX_N {0}] $util_fmcadc4_gt
-set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_fmcadc4_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $util_fmcadc4_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc4_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc4_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_gt
-set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc4_gt
+set util_fmcadc4_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc4_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_xcvr
 
 create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_data
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {128}] [get_bd_cells util_bsplit_rx_data]
@@ -60,64 +45,19 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_r
 
 # connections (gt)
 
-ad_connect  util_fmcadc4_gt/qpll_ref_clk rx_ref_clk
-
-ad_connect  axi_fmcadc4_gt/gt_qpll_0 util_fmcadc4_gt/gt_qpll_0
-ad_connect  axi_fmcadc4_gt/gt_qpll_1 util_fmcadc4_gt/gt_qpll_1
-ad_connect  axi_fmcadc4_gt/gt_pll_0 util_fmcadc4_gt/gt_pll_0
-ad_connect  axi_fmcadc4_gt/gt_pll_1 util_fmcadc4_gt/gt_pll_1
-ad_connect  axi_fmcadc4_gt/gt_pll_2 util_fmcadc4_gt/gt_pll_2
-ad_connect  axi_fmcadc4_gt/gt_pll_3 util_fmcadc4_gt/gt_pll_3
-ad_connect  axi_fmcadc4_gt/gt_pll_4 util_fmcadc4_gt/gt_pll_4
-ad_connect  axi_fmcadc4_gt/gt_pll_5 util_fmcadc4_gt/gt_pll_5
-ad_connect  axi_fmcadc4_gt/gt_pll_6 util_fmcadc4_gt/gt_pll_6
-ad_connect  axi_fmcadc4_gt/gt_pll_7 util_fmcadc4_gt/gt_pll_7
-ad_connect  axi_fmcadc4_gt/gt_rx_0 util_fmcadc4_gt/gt_rx_0
-ad_connect  axi_fmcadc4_gt/gt_rx_1 util_fmcadc4_gt/gt_rx_1
-ad_connect  axi_fmcadc4_gt/gt_rx_2 util_fmcadc4_gt/gt_rx_2
-ad_connect  axi_fmcadc4_gt/gt_rx_3 util_fmcadc4_gt/gt_rx_3
-ad_connect  axi_fmcadc4_gt/gt_rx_4 util_fmcadc4_gt/gt_rx_4
-ad_connect  axi_fmcadc4_gt/gt_rx_5 util_fmcadc4_gt/gt_rx_5
-ad_connect  axi_fmcadc4_gt/gt_rx_6 util_fmcadc4_gt/gt_rx_6
-ad_connect  axi_fmcadc4_gt/gt_rx_7 util_fmcadc4_gt/gt_rx_7
-ad_connect  axi_fmcadc4_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
-ad_connect  axi_fmcadc4_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
-ad_connect  axi_fmcadc4_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
-ad_connect  axi_fmcadc4_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
-ad_connect  axi_fmcadc4_gt/gt_rx_ip_4 axi_ad9680_jesd/gt4_rx
-ad_connect  axi_fmcadc4_gt/gt_rx_ip_5 axi_ad9680_jesd/gt5_rx
-ad_connect  axi_fmcadc4_gt/gt_rx_ip_6 axi_ad9680_jesd/gt6_rx
-ad_connect  axi_fmcadc4_gt/gt_rx_ip_7 axi_ad9680_jesd/gt7_rx
-ad_connect  axi_fmcadc4_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc4_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc4_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc4_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc4_gt/rx_gt_comma_align_enb_4 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc4_gt/rx_gt_comma_align_enb_5 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc4_gt/rx_gt_comma_align_enb_6 axi_ad9680_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc4_gt/rx_gt_comma_align_enb_7 axi_ad9680_jesd/rxencommaalign_out
+ad_xcvrcon  util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd
+ad_connect  util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
+ad_connect  util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_0/rx_clk
+ad_connect  util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_1/rx_clk
+ad_connect  axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_0/rx_sof
+ad_connect  axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_1/rx_sof
+ad_connect  axi_ad9680_jesd/rx_tdata util_bsplit_rx_data/data
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
 
 # connections (adc)
 
-ad_connect  util_fmcadc4_gt/rx_p rx_data_p
-ad_connect  util_fmcadc4_gt/rx_n rx_data_n
-ad_connect  util_fmcadc4_gt/rx_sysref rx_sysref
-ad_connect  util_fmcadc4_gt/rx_sync rx_sync
-ad_connect  util_fmcadc4_gt/rx_out_clk util_fmcadc4_gt/rx_clk
-ad_connect  util_fmcadc4_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
-ad_connect  util_fmcadc4_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
-ad_connect  util_fmcadc4_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
-ad_connect  util_fmcadc4_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
-ad_connect  util_fmcadc4_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
-ad_connect  util_fmcadc4_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
-ad_connect  util_fmcadc4_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
-ad_connect  util_fmcadc4_gt/rx_data util_bsplit_rx_data/data
-ad_connect  util_fmcadc4_gt/rx_out_clk axi_ad9680_core_0/rx_clk
-ad_connect  util_fmcadc4_gt/rx_out_clk axi_ad9680_core_1/rx_clk
 ad_connect  util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data
 ad_connect  util_bsplit_rx_data/split_data_1 axi_ad9680_core_1/rx_data
-ad_connect  util_fmcadc4_gt/rx_out_clk axi_ad9680_cpack/adc_clk
-ad_connect  util_fmcadc4_gt/rx_rst axi_ad9680_cpack/adc_rst
 ad_connect  axi_ad9680_core_0/adc_enable_0 axi_ad9680_cpack/adc_enable_0
 ad_connect  axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/adc_valid_0
 ad_connect  axi_ad9680_core_0/adc_data_0 axi_ad9680_cpack/adc_data_0
@@ -130,8 +70,8 @@ ad_connect  axi_ad9680_core_1/adc_data_0 axi_ad9680_cpack/adc_data_2
 ad_connect  axi_ad9680_core_1/adc_enable_1 axi_ad9680_cpack/adc_enable_3
 ad_connect  axi_ad9680_core_1/adc_valid_1 axi_ad9680_cpack/adc_valid_3
 ad_connect  axi_ad9680_core_1/adc_data_1 axi_ad9680_cpack/adc_data_3
-ad_connect  util_fmcadc4_gt/rx_out_clk axi_ad9680_fifo/adc_clk
-ad_connect  util_fmcadc4_gt/rx_rst axi_ad9680_fifo/adc_rst
+ad_connect  util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
 ad_connect  axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
 ad_connect  axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
 ad_connect  sys_cpu_clk axi_ad9680_fifo/dma_clk
@@ -143,9 +83,12 @@ ad_connect  axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
 ad_connect  axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
 ad_connect  axi_ad9680_core_0/adc_dovf axi_ad9680_fifo/adc_wovf
 
+ad_connect  sys_cpu_clk util_fmcadc4_xcvr/up_clk
+ad_connect  sys_cpu_resetn util_fmcadc4_xcvr/up_rstn
+
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_fmcadc4_gt
+ad_cpu_interconnect 0x44A60000 axi_ad9680_xcvr
 ad_cpu_interconnect 0x44A00000 axi_ad9680_core_0
 ad_cpu_interconnect 0x44A10000 axi_ad9680_core_1
 ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
@@ -154,7 +97,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
 # gt uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_fmcadc4_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
 
 # interconnect (mem/adc)
 
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index e939d348d..82a79c8d5 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -22,14 +22,14 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -61,14 +61,14 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9680 clean
 	make -C ../../../library/xilinx/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_bsplit clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_mfifo clean
 
 
@@ -80,14 +80,14 @@ fmcadc4_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9680
 	make -C ../../../library/xilinx/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_bsplit
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_mfifo
 
 ####################################################################################
diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl
index 59392004d..91e5cfa22 100644
--- a/projects/fmcadc4/zc706/system_bd.tcl
+++ b/projects/fmcadc4/zc706/system_bd.tcl
@@ -20,39 +20,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
   SEG_axi_ddr_cntrl_memaddr
 
 source ../common/fmcadc4_bd.tcl
-
-# ila
-
-set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc
-set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
-set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
-
-set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
-set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc
-
-ad_connect  util_fmcadc4_gt/rx_rst mfifo_adc/din_rst
-ad_connect  util_fmcadc4_gt/rx_out_clk mfifo_adc/din_clk
-ad_connect  axi_ad9680_core_0/adc_valid_0 mfifo_adc/din_valid
-ad_connect  axi_ad9680_core_0/adc_data_0 mfifo_adc/din_data_0
-ad_connect  axi_ad9680_core_0/adc_data_1 mfifo_adc/din_data_1
-ad_connect  axi_ad9680_core_1/adc_data_0 mfifo_adc/din_data_2
-ad_connect  axi_ad9680_core_1/adc_data_1 mfifo_adc/din_data_3
-ad_connect  util_fmcadc4_gt/rx_rst mfifo_adc/dout_rst
-ad_connect  util_fmcadc4_gt/rx_out_clk mfifo_adc/dout_clk
-ad_connect  util_fmcadc4_gt/rx_out_clk ila_adc/clk
-ad_connect  mfifo_adc/dout_valid ila_adc/probe0
-ad_connect  mfifo_adc/dout_data_0 ila_adc/probe1
-ad_connect  mfifo_adc/dout_data_1 ila_adc/probe2
-ad_connect  mfifo_adc/dout_data_2 ila_adc/probe3
-ad_connect  mfifo_adc/dout_data_3 ila_adc/probe4
-
-
diff --git a/projects/fmcadc4/zc706/system_constr.xdc b/projects/fmcadc4/zc706/system_constr.xdc
index 4f8607ec8..a3486e1e2 100644
--- a/projects/fmcadc4/zc706/system_constr.xdc
+++ b/projects/fmcadc4/zc706/system_constr.xdc
@@ -46,5 +46,4 @@ set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports ad9680_2
 # clocks
 
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_fmcadc4_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
-
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_fmcadc4_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
diff --git a/projects/fmcadc4/zc706/system_project.tcl b/projects/fmcadc4/zc706/system_project.tcl
index 787434877..63fe133b5 100644
--- a/projects/fmcadc4/zc706/system_project.tcl
+++ b/projects/fmcadc4/zc706/system_project.tcl
@@ -14,8 +14,6 @@ adi_project_files fmcadc4_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
-
 adi_project_run fmcadc4_zc706
 
 
diff --git a/projects/fmcadc4/zc706/system_top.v b/projects/fmcadc4/zc706/system_top.v
index 77be2f7b0..2f89d49b9 100644
--- a/projects/fmcadc4/zc706/system_top.v
+++ b/projects/fmcadc4/zc706/system_top.v
@@ -345,11 +345,25 @@ module system_top (
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
     .ps_intr_12 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_data_4_n (rx_data_n[4]),
+    .rx_data_4_p (rx_data_p[4]),
+    .rx_data_5_n (rx_data_n[5]),
+    .rx_data_5_p (rx_data_p[5]),
+    .rx_data_6_n (rx_data_n[6]),
+    .rx_data_6_p (rx_data_p[6]),
+    .rx_data_7_n (rx_data_n[7]),
+    .rx_data_7_p (rx_data_p[7]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),

From db243df97e77b65591497fd5afda89258f99eae1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 15 Nov 2016 14:15:55 -0500
Subject: [PATCH 704/972] pzsdr2- updates

---
 projects/pzsdr2/README.md                     |  26 ++
 projects/pzsdr2/ccbrk_cmos/system_bd.tcl      |  31 +-
 projects/pzsdr2/ccbrk_cmos/system_project.tcl |  16 +-
 projects/pzsdr2/ccbrk_cmos/system_top.v       |  40 +-
 projects/pzsdr2/ccbrk_lvds/system_bd.tcl      |  33 +-
 projects/pzsdr2/ccbrk_lvds/system_constr.xdc  | 238 ------------
 projects/pzsdr2/ccbrk_lvds/system_project.tcl |  16 +-
 projects/pzsdr2/ccbrk_lvds/system_top.v       |  39 +-
 projects/pzsdr2/common/ccbrk_bd.tcl           |   4 -
 projects/pzsdr2/common/ccbrk_constr.xdc       | 248 ++++++++++++
 projects/pzsdr2/common/pzsdr2_bd.tcl          | 365 ++++++++++++++++++
 projects/pzsdr2/common/pzsdr2_constr.xdc      | 195 ++++++++++
 projects/pzsdr2/common/pzsdr2_constr_cmos.xdc |  42 ++
 projects/pzsdr2/common/pzsdr2_constr_lvds.xdc |  42 ++
 14 files changed, 997 insertions(+), 338 deletions(-)
 create mode 100644 projects/pzsdr2/README.md
 delete mode 100644 projects/pzsdr2/ccbrk_lvds/system_constr.xdc
 create mode 100644 projects/pzsdr2/common/ccbrk_constr.xdc
 create mode 100644 projects/pzsdr2/common/pzsdr2_bd.tcl
 create mode 100644 projects/pzsdr2/common/pzsdr2_constr.xdc
 create mode 100644 projects/pzsdr2/common/pzsdr2_constr_cmos.xdc
 create mode 100644 projects/pzsdr2/common/pzsdr2_constr_lvds.xdc

diff --git a/projects/pzsdr2/README.md b/projects/pzsdr2/README.md
new file mode 100644
index 000000000..01526c903
--- /dev/null
+++ b/projects/pzsdr2/README.md
@@ -0,0 +1,26 @@
+# PicoZed SDR SOM (PZSDR2)
+
+This folder contains the PZSDR2 SOM projects for each of the carrier boards.
+
+## Board Design Files
+
+common/pzsdr2_bd.tcl ; pzsdr2 SOM module board design file.
+common/ccbrk_bd.tcl ; carrier, break out board design file.
+common/ccfmc_bd.tcl ; carrier, fmc board design file.
+common/ccpci_bd.tcl ; carrier, pci-e board design file.
+common/ccusb_bd.tcl ; carrier, usb board design file.
+
+## Board Constraint Files
+
+common/pzsdr2_constr.xdc ; pzsdr2 SOM base constraints file.
+common/pzsdr2_constr_cmos.xdc ; pzsdr2 SOM CMOS mode constraints file.
+common/pzsdr2_constr_lvds.xdc ; pzsdr2 SOM LVDS mode constraints file.
+
+common/ccbrk_constr.xdc ; carrier, break out board constraints file.*
+common/ccfmc_constr.xdc ; carrier, fmc board constraints file.*
+common/ccpci_constr.xdc ; carrier, pci-e board constraints file.
+common/ccusb_constr.xdc ; carrier, usb board constraints file.
+
+* FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
+
+
diff --git a/projects/pzsdr2/ccbrk_cmos/system_bd.tcl b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
index 0214a7513..6c6c3d30d 100644
--- a/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
+++ b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
@@ -1,34 +1,10 @@
 
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/pzsdr2_bd.tcl
 source ../common/ccbrk_bd.tcl
 
-# CMOS Mode 
+## core digital interface -- cmos (1) or lvds (0)
 
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_n]]]
-
-delete_bd_objs [get_bd_ports tx_clk_out_p]
-delete_bd_objs [get_bd_ports tx_clk_out_n]
-delete_bd_objs [get_bd_ports tx_frame_out_p]
-delete_bd_objs [get_bd_ports tx_frame_out_n]
-delete_bd_objs [get_bd_ports tx_data_out_p]
-delete_bd_objs [get_bd_ports tx_data_out_n]
-delete_bd_objs [get_bd_ports rx_clk_in_p]
-delete_bd_objs [get_bd_ports rx_clk_in_n]
-delete_bd_objs [get_bd_ports rx_frame_in_p]
-delete_bd_objs [get_bd_ports rx_frame_in_n]
-delete_bd_objs [get_bd_ports rx_data_in_p]
-delete_bd_objs [get_bd_ports rx_data_in_n]
+set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
 
 create_bd_port -dir I rx_clk_in
 create_bd_port -dir I rx_frame_in
@@ -37,7 +13,6 @@ create_bd_port -dir O tx_clk_out
 create_bd_port -dir O tx_frame_out
 create_bd_port -dir O -from 11 -to 0 tx_data_out
 
-set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
 
 ad_connect  rx_clk_in axi_ad9361/rx_clk_in
 ad_connect  rx_frame_in axi_ad9361/rx_frame_in
diff --git a/projects/pzsdr2/ccbrk_cmos/system_project.tcl b/projects/pzsdr2/ccbrk_cmos/system_project.tcl
index 8158fb805..9d8f3dfbb 100644
--- a/projects/pzsdr2/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr2/ccbrk_cmos/system_project.tcl
@@ -3,16 +3,16 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccbrk_cmos_pzsdr
-adi_project_files ccbrk_cmos_pzsdr [list \
-  "system_top.v" \
-  "../ccbrk_lvds/system_constr.xdc"\
+set p_device "xc7z035ifbg676-2L"
+adi_project_create pzsdr2_ccbrk_cmos
+adi_project_files pzsdr2_ccbrk_cmos [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc" ]
+  "../common/pzsdr2_constr.xdc" \
+  "../common/pzsdr2_constr_cmos.xdc" \
+  "../common/ccbrk_constr.xdc" \
+  "system_top.v" ]
 
 set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
-adi_project_run ccbrk_cmos_pzsdr
+adi_project_run pzsdr2_ccbrk_cmos
 
 
diff --git a/projects/pzsdr2/ccbrk_cmos/system_top.v b/projects/pzsdr2/ccbrk_cmos/system_top.v
index 4e99e5daf..bdaabf177 100644
--- a/projects/pzsdr2/ccbrk_cmos/system_top.v
+++ b/projects/pzsdr2/ccbrk_cmos/system_top.v
@@ -65,7 +65,7 @@ module system_top (
   inout           iic_scl,
   inout           iic_sda,
 
-  inout   [11:0]  gpio_bd,
+  inout   [19:0]  gpio_bd,
 
   input           rx_clk_in,
   input           rx_frame_in,
@@ -77,7 +77,8 @@ module system_top (
 
   output          enable,
   output          txnrx,
-  input           clk_out,
+  input           clkout_in,
+  output          clkout_out,
 
   inout           gpio_clksel,
   inout           gpio_resetb,
@@ -91,10 +92,8 @@ module system_top (
   output          spi_mosi,
   input           spi_miso,
 
-  output  [87:0]  gp_out,
-  input   [87:0]  gp_in,
-  input   [ 3:0]  gp_in_mio,
-  input           gp_in_1,
+  output  [85:0]  gp_out,
+  input   [85:0]  gp_in,
 
   input           gt_ref_clk_p,
   input           gt_ref_clk_n,
@@ -106,7 +105,6 @@ module system_top (
   // internal signals
 
   wire            gt_ref_clk;
-  wire    [31:0]  gp_misc_s;
   wire    [95:0]  gp_out_s;
   wire    [95:0]  gp_in_s;
   wire    [63:0]  gpio_i;
@@ -116,20 +114,10 @@ module system_top (
   // assignments
 
   assign tx_gnd = 2'd0;
-
-  assign gp_out[87:43] = gp_out_s[87:43];
-  assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
-  assign gp_out[41: 0] = gp_out_s[41: 0];
-
-  assign gp_in_s[95:88] = gp_out_s[95:88];
-  assign gp_in_s[87:66] = gp_in[87:66];
-  assign gp_in_s[65:65] = gp_out_s[65];
-  assign gp_in_s[64: 0] = gp_in[64:0];
-
-  assign gp_misc_s[31: 9] = 23'd0;
-  assign gp_misc_s[ 8: 8] = gp_in_1;
-  assign gp_misc_s[ 7: 4] = 4'd0;
-  assign gp_misc_s[ 3: 0] = gp_in_mio;
+  assign clkout_out = clkout_in;
+  assign gp_out[85:0] = gp_out_s[85:0];
+  assign gp_in_s[95:86] = gp_out_s[95:86];
+  assign gp_in_s[85: 0] = gp_in[85:0];
 
   // instantiations
 
@@ -151,10 +139,10 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
-    .dio_t (gpio_t[11:0]),
-    .dio_i (gpio_o[11:0]),
-    .dio_o (gpio_i[11:0]),
+  ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
+    .dio_t (gpio_t[19:0]),
+    .dio_i (gpio_o[19:0]),
+    .dio_o (gpio_i[19:0]),
     .dio_p (gpio_bd));
 
   system_wrapper i_system_wrapper (
@@ -183,7 +171,7 @@ module system_top (
     .gp_in_0 (gp_in_s[31:0]),
     .gp_in_1 (gp_in_s[63:32]),
     .gp_in_2 (gp_in_s[95:64]),
-    .gp_in_3 (gp_misc_s),
+    .gp_in_3 (32'd0),
     .gp_out_0 (gp_out_s[31:0]),
     .gp_out_1 (gp_out_s[63:32]),
     .gp_out_2 (gp_out_s[95:64]),
diff --git a/projects/pzsdr2/ccbrk_lvds/system_bd.tcl b/projects/pzsdr2/ccbrk_lvds/system_bd.tcl
index 4907eef1b..030c6a762 100644
--- a/projects/pzsdr2/ccbrk_lvds/system_bd.tcl
+++ b/projects/pzsdr2/ccbrk_lvds/system_bd.tcl
@@ -1,4 +1,35 @@
 
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/pzsdr2_bd.tcl
 source ../common/ccbrk_bd.tcl
 
+## core digital interface -- cmos (1) or lvds (0)
+
+set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
+
+create_bd_port -dir I rx_clk_in_p
+create_bd_port -dir I rx_clk_in_n
+create_bd_port -dir I rx_frame_in_p
+create_bd_port -dir I rx_frame_in_n
+create_bd_port -dir I -from 5 -to 0 rx_data_in_p
+create_bd_port -dir I -from 5 -to 0 rx_data_in_n
+
+create_bd_port -dir O tx_clk_out_p
+create_bd_port -dir O tx_clk_out_n
+create_bd_port -dir O tx_frame_out_p
+create_bd_port -dir O tx_frame_out_n
+create_bd_port -dir O -from 5 -to 0 tx_data_out_p
+create_bd_port -dir O -from 5 -to 0 tx_data_out_n
+
+ad_connect  rx_clk_in_p axi_ad9361/rx_clk_in_p
+ad_connect  rx_clk_in_n axi_ad9361/rx_clk_in_n
+ad_connect  rx_frame_in_p axi_ad9361/rx_frame_in_p
+ad_connect  rx_frame_in_n axi_ad9361/rx_frame_in_n
+ad_connect  rx_data_in_p axi_ad9361/rx_data_in_p
+ad_connect  rx_data_in_n axi_ad9361/rx_data_in_n
+ad_connect  tx_clk_out_p axi_ad9361/tx_clk_out_p
+ad_connect  tx_clk_out_n axi_ad9361/tx_clk_out_n
+ad_connect  tx_frame_out_p axi_ad9361/tx_frame_out_p
+ad_connect  tx_frame_out_n axi_ad9361/tx_frame_out_n
+ad_connect  tx_data_out_p axi_ad9361/tx_data_out_p
+ad_connect  tx_data_out_n axi_ad9361/tx_data_out_n
+
diff --git a/projects/pzsdr2/ccbrk_lvds/system_constr.xdc b/projects/pzsdr2/ccbrk_lvds/system_constr.xdc
deleted file mode 100644
index d079c4d97..000000000
--- a/projects/pzsdr2/ccbrk_lvds/system_constr.xdc
+++ /dev/null
@@ -1,238 +0,0 @@
-
-## constraints
-## loopback (P2/P13 are pin swapped on board - so skip gp_*[65])
-## p4
-
-set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]        ; ## IO_L2P_T0_33
-set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]         ; ## IO_L1P_T0_33
-set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]        ; ## IO_L2N_T0_33
-set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]         ; ## IO_L1N_T0_33
-set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]        ; ## IO_L4P_T0_33
-set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]         ; ## IO_L3P_T0_DQS_33
-set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]        ; ## IO_L4N_T0_33
-set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]         ; ## IO_L3N_T0_DQS_33
-set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]        ; ## IO_L6P_T0_33
-set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]         ; ## IO_L5P_T0_33
-set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]        ; ## IO_L6N_T0_VREF_33
-set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]         ; ## IO_L5N_T0_33
-set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]        ; ## IO_L8P_T1_33
-set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]         ; ## IO_L7P_T1_33
-set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]        ; ## IO_L8N_T1_33
-set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]         ; ## IO_L7N_T1_33
-set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]        ; ## IO_L10P_T1_33
-set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]         ; ## IO_L9P_T1_DQS_33
-set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]        ; ## IO_L10N_T1_33
-set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]         ; ## IO_L9N_T1_DQS_33
-set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]       ; ## IO_L12P_T1_MRCC_33
-set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]        ; ## IO_L11P_T1_SRCC_33
-
-## p5
-
-set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]       ; ## IO_L17P_T2_33
-set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]        ; ## IO_L16P_T2_33
-set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]       ; ## IO_L17N_T2_33
-set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]        ; ## IO_L16N_T2_33
-set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]       ; ## IO_L19P_T3_33
-set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]        ; ## IO_L18P_T2_33
-set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]       ; ## IO_L19N_T3_VREF_33
-set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]        ; ## IO_L18N_T2_33
-set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]       ; ## IO_L20P_T3_33
-set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]        ; ## IO_L21P_T3_DQS_33
-set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]       ; ## IO_L20N_T3_33
-set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]        ; ## IO_L21N_T3_DQS_33
-set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]       ; ## IO_L22P_T3_33
-set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]        ; ## IO_L23P_T3_33
-set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]       ; ## IO_L22N_T3_33
-set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]        ; ## IO_L23N_T3_33
-set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]       ; ## IO_25_VRP_34
-set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]        ; ## IO_L10N_T1_34
-set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]       ; ## IO_L14P_T2_SRCC_33
-set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]        ; ## IO_L24P_T3_33
-set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]       ; ## IO_L14N_T2_SRCC_33
-set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]        ; ## IO_L24N_T3_33
-set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]       ; ## IO_L13P_T2_MRCC_33
-set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]        ; ## IO_L15P_T2_DQS_33
-set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]       ; ## IO_L13N_T2_MRCC_33
-set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]        ; ## IO_L15N_T2_DQS_33
-
-## p6
-
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]       ; ## IO_L2P_T0_34
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]        ; ## IO_L1P_T0_34
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]       ; ## IO_L2N_T0_34
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]        ; ## IO_L1N_T0_34
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]       ; ## IO_L4P_T0_34
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]        ; ## IO_L3P_T0_DQS_PUDC_B_34
-set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]       ; ## IO_L4N_T0_34
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]        ; ## IO_L3N_T0_DQS_34
-set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]       ; ## IO_L6P_T0_34
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]        ; ## IO_L5P_T0_34
-set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]       ; ## IO_L6N_T0_VREF_34
-set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]        ; ## IO_L5N_T0_34
-set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]       ; ## IO_L8P_T1_34
-set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]        ; ## IO_L7P_T1_34
-set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]       ; ## IO_L12P_T1_MRCC_34
-set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]        ; ## IO_L11P_T1_SRCC_34
-set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]       ; ## IO_L12N_T1_MRCC_34
-set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]        ; ## IO_L11N_T1_SRCC_34
-
-## p7
-
-set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]       ; ## IO_L14P_T2_SRCC_34
-set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]        ; ## IO_L13P_T2_MRCC_34
-set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]       ; ## IO_L14N_T2_SRCC_34
-set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]        ; ## IO_L13N_T2_MRCC_34
-set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]       ; ## IO_L16P_T2_34
-set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]        ; ## IO_L15P_T2_DQS_34
-set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]       ; ## IO_L16N_T2_34
-set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]        ; ## IO_L15N_T2_DQS_34
-set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]       ; ## IO_L20P_T3_34
-set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]        ; ## IO_L19P_T3_34
-set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]       ; ## IO_L20N_T3_34
-set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]        ; ## IO_L19N_T3_VREF_34
-set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]       ; ## IO_L22P_T3_34
-set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]        ; ## IO_L21P_T3_DQS_34
-set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]       ; ## IO_L22N_T3_34
-set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]        ; ## IO_L21N_T3_DQS_34
-set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]       ; ## IO_0_VRN_33
-set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]        ; ## IO_L18P_T2_34
-set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]       ; ## IO_L18N_T2_34
-set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]        ; ## IO_25_VRP_33
-
-## p13
-
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[43]]       ; ## IO_L16P_T2_12
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[43]]        ; ## IO_L15P_T2_DQS_12
-set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[44]]       ; ## IO_L16N_T2_12
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[44]]        ; ## IO_L15N_T2_DQS_12
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[45]]       ; ## IO_L14P_T2_SRCC_12
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[45]]        ; ## IO_L13P_T2_MRCC_12
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[46]]       ; ## IO_L14N_T2_SRCC_12
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD  LVCMOS25} [get_ports  gp_in[46]]        ; ## IO_L13N_T2_MRCC_12
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[47]]       ; ## IO_L12P_T1_MRCC_12
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD  LVCMOS25} [get_ports  gp_in[47]]        ; ## IO_L11P_T1_SRCC_12
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[48]]       ; ## IO_L12N_T1_MRCC_12
-set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[48]]        ; ## IO_L11N_T1_SRCC_12
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[49]]       ; ## IO_L10P_T1_12
-set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD  LVCMOS25} [get_ports  gp_in[49]]        ; ## IO_L9P_T1_DQS_12
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[50]]       ; ## IO_L10N_T1_12
-set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[50]]        ; ## IO_L9N_T1_DQS_12
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[51]]       ; ## IO_L8P_T1_12
-set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[51]]        ; ## IO_L7P_T1_12
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[52]]       ; ## IO_L8N_T1_12
-set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[52]]        ; ## IO_L7N_T1_12
-set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS25} [get_ports  gp_out[53]]       ; ## IO_L6P_T0_12
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[53]]        ; ## IO_L5P_T0_12
-set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[54]]       ; ## IO_L6N_T0_VREF_12
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[54]]        ; ## IO_L5N_T0_12
-set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[55]]       ; ## IO_L4P_T0_12
-set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[55]]        ; ## IO_L3P_T0_DQS_12
-set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS25} [get_ports  gp_out[56]]       ; ## IO_L4N_T0_12
-set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS25} [get_ports  gp_in[56]]        ; ## IO_L3N_T0_DQS_12
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS25} [get_ports  gp_out[57]]       ; ## IO_L2P_T0_12
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_in[57]]        ; ## IO_L1P_T0_12
-set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD  LVCMOS25} [get_ports  gp_out[58]]       ; ## IO_L2N_T0_12
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[58]]        ; ## IO_L1N_T0_12
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[59]]       ; ## IO_L18P_T2_12
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[59]]        ; ## IO_L17P_T2_12
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[60]]       ; ## IO_L18N_T2_12
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD  LVCMOS25} [get_ports  gp_in[60]]        ; ## IO_L17N_T2_12
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD  LVCMOS25} [get_ports  gp_out[61]]       ; ## IO_L20P_T3_12
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[61]]        ; ## IO_L19P_T3_12
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD  LVCMOS25} [get_ports  gp_out[62]]       ; ## IO_L20N_T3_12
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[62]]        ; ## IO_L19N_T3_VREF_12
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD  LVCMOS25} [get_ports  gp_out[63]]       ; ## IO_L22P_T3_12
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  gp_in[63]]        ; ## IO_L21P_T3_DQS_12
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]       ; ## IO_L22N_T3_12
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]        ; ## IO_L21N_T3_DQS_12
-
-## p2
-
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]       ; ## IO_25_13
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]        ; ## IO_L6P_T0_13
-set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]       ; ## IO_L2P_T0_13
-set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]        ; ## IO_L1P_T0_13
-set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]       ; ## IO_L2N_T0_13
-set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]        ; ## IO_L1N_T0_13
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]       ; ## IO_L4P_T0_13
-set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]        ; ## IO_L3P_T0_DQS_13
-set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]       ; ## IO_L4N_T0_13
-set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]        ; ## IO_L3N_T0_DQS_13
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]       ; ## IO_L8P_T1_13
-set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]        ; ## IO_L7P_T1_13
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]       ; ## IO_L8N_T1_13
-set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]        ; ## IO_L7N_T1_13
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]       ; ## IO_L10P_T1_13
-set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]        ; ## IO_L9P_T1_DQS_13
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]       ; ## IO_L10N_T1_13
-set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]        ; ## IO_L9N_T1_DQS_13
-set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]       ; ## IO_L12P_T1_MRCC_13
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]        ; ## IO_L11P_T1_SRCC_13
-set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]       ; ## IO_L12N_T1_MRCC_13
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]        ; ## IO_L11N_T1_SRCC_13
-set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]       ; ## IO_L14P_T2_SRCC_13
-set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]        ; ## IO_L13P_T2_MRCC_13
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]       ; ## IO_L14N_T2_SRCC_13
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]        ; ## IO_L13N_T2_MRCC_13
-set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]       ; ## IO_L16P_T2_13
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]        ; ## IO_L15P_T2_DQS_13
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]       ; ## IO_L16N_T2_13
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]        ; ## IO_L15N_T2_DQS_13
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]       ; ## IO_L18P_T2_13
-set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]        ; ## IO_L17P_T2_13
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]       ; ## IO_L18N_T2_13
-set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]        ; ## IO_L17N_T2_13
-set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]       ; ## IO_L20P_T3_13
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]        ; ## IO_L19P_T3_13
-set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]       ; ## IO_L20N_T3_13
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]        ; ## IO_L19N_T3_VREF_13
-set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]       ; ## IO_L22P_T3_13
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]        ; ## IO_L21P_T3_DQS_13
-set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]       ; ## IO_L22N_T3_13
-set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]        ; ## IO_L21N_T3_DQS_13
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[86]]       ; ## IO_L24P_T3_13
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[86]]        ; ## IO_L23P_T3_13
-set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD  LVCMOS25} [get_ports  gp_out[87]]       ; ## IO_L24N_T3_13
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[87]]        ; ## IO_L23N_T3_13
-
-## vcc
-
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD  LVCMOS25} [get_ports  gp_in_1]          ; ## IO_L6N_T0_VREF_13
-
-## on board
-
-set_property  -dict {PACKAGE_PIN  W6}   [get_ports  gt_ref_clk_p]                           ; ## MGTREFCLK0P_111
-set_property  -dict {PACKAGE_PIN  W5}   [get_ports  gt_ref_clk_n]                           ; ## MGTREFCLK0N_111
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports  gt_rx_p[0]]                             ; ## MGTXRXP0_111
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports  gt_rx_n[0]]                             ; ## MGTXRXN0_111
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports  gt_rx_p[1]]                             ; ## MGTXRXP1_111
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports  gt_rx_n[1]]                             ; ## MGTXRXN1_111
-set_property  -dict {PACKAGE_PIN  AC6}  [get_ports  gt_rx_p[2]]                             ; ## MGTXRXP2_111
-set_property  -dict {PACKAGE_PIN  AC5}  [get_ports  gt_rx_n[2]]                             ; ## MGTXRXN2_111
-set_property  -dict {PACKAGE_PIN  AD4}  [get_ports  gt_rx_p[3]]                             ; ## MGTXRXP3_111
-set_property  -dict {PACKAGE_PIN  AD3}  [get_ports  gt_rx_n[3]]                             ; ## MGTXRXN3_111
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports  gt_tx_p[0]]                             ; ## MGTXTXP0_111
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports  gt_tx_n[0]]                             ; ## MGTXTXN0_111
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports  gt_tx_p[1]]                             ; ## MGTXTXP1_111
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports  gt_tx_n[1]]                             ; ## MGTXTXN1_111
-set_property  -dict {PACKAGE_PIN  AE2}  [get_ports  gt_tx_p[2]]                             ; ## MGTXTXP2_111
-set_property  -dict {PACKAGE_PIN  AE1}  [get_ports  gt_tx_n[2]]                             ; ## MGTXTXN2_111
-set_property  -dict {PACKAGE_PIN  AC2}  [get_ports  gt_tx_p[3]]                             ; ## MGTXTXP3_111
-set_property  -dict {PACKAGE_PIN  AC1}  [get_ports  gt_tx_n[3]]                             ; ## MGTXTXN3_111
-
-## mio
-
-set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[0]]     ; ## IO_L11N_T1_SRCC_33
-set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[1]]     ; ## IO_L17P_T2_34
-set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[2]]     ; ## IO_L7N_T1_34
-set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  gp_in_mio[3]]     ; ## IO_L10P_T1_34
-
-## clocks
-
-create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
-create_clock -name xcvr_clk_0   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
-create_clock -name xcvr_clk_1   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
-create_clock -name xcvr_clk_2   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[2].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
-create_clock -name xcvr_clk_3   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[3].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
-
-
diff --git a/projects/pzsdr2/ccbrk_lvds/system_project.tcl b/projects/pzsdr2/ccbrk_lvds/system_project.tcl
index f111b377b..8dc9a290f 100644
--- a/projects/pzsdr2/ccbrk_lvds/system_project.tcl
+++ b/projects/pzsdr2/ccbrk_lvds/system_project.tcl
@@ -3,16 +3,16 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccbrk_lvds_pzsdr
-adi_project_files ccbrk_lvds_pzsdr [list \
-  "system_top.v" \
-  "system_constr.xdc"\
+set p_device "xc7z035ifbg676-2L"
+adi_project_create pzsdr2_ccbrk_lvds
+adi_project_files pzsdr2_ccbrk_lvds [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
+  "../common/pzsdr2_constr.xdc" \
+  "../common/pzsdr2_constr_lvds.xdc" \
+  "../common/ccbrk_constr.xdc" \
+  "system_top.v" ]
 
 set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
-adi_project_run ccbrk_lvds_pzsdr
+adi_project_run pzsdr2_ccbrk_lvds
 
 
diff --git a/projects/pzsdr2/ccbrk_lvds/system_top.v b/projects/pzsdr2/ccbrk_lvds/system_top.v
index c3d296b81..167b4a465 100644
--- a/projects/pzsdr2/ccbrk_lvds/system_top.v
+++ b/projects/pzsdr2/ccbrk_lvds/system_top.v
@@ -65,7 +65,7 @@ module system_top (
   inout           iic_scl,
   inout           iic_sda,
 
-  inout   [11:0]  gpio_bd,
+  inout   [19:0]  gpio_bd,
 
   input           rx_clk_in_p,
   input           rx_clk_in_n,
@@ -82,7 +82,8 @@ module system_top (
 
   output          enable,
   output          txnrx,
-  input           clk_out,
+  input           clkout_in,
+  output          clkout_out,
 
   inout           gpio_clksel,
   inout           gpio_resetb,
@@ -96,10 +97,8 @@ module system_top (
   output          spi_mosi,
   input           spi_miso,
 
-  output  [87:0]  gp_out,
-  input   [87:0]  gp_in,
-  input   [ 3:0]  gp_in_mio,
-  input           gp_in_1,
+  output  [85:0]  gp_out,
+  input   [85:0]  gp_in,
 
   input           gt_ref_clk_p,
   input           gt_ref_clk_n,
@@ -111,7 +110,6 @@ module system_top (
   // internal signals
 
   wire            gt_ref_clk;
-  wire    [31:0]  gp_misc_s;
   wire    [95:0]  gp_out_s;
   wire    [95:0]  gp_in_s;
   wire    [63:0]  gpio_i;
@@ -120,19 +118,10 @@ module system_top (
 
   // assignments
 
-  assign gp_out[87:43] = gp_out_s[87:43];
-  assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
-  assign gp_out[41: 0] = gp_out_s[41: 0];
-
-  assign gp_in_s[95:88] = gp_out_s[95:88];
-  assign gp_in_s[87:66] = gp_in[87:66];
-  assign gp_in_s[65:65] = gp_out_s[65];
-  assign gp_in_s[64: 0] = gp_in[64:0];
-
-  assign gp_misc_s[31: 9] = 23'd0;
-  assign gp_misc_s[ 8: 8] = gp_in_1;
-  assign gp_misc_s[ 7: 4] = 4'd0;
-  assign gp_misc_s[ 3: 0] = gp_in_mio;
+  assign clkout_out = clkout_in;
+  assign gp_out[85:0] = gp_out_s[85:0];
+  assign gp_in_s[95:86] = gp_out_s[95:86];
+  assign gp_in_s[85: 0] = gp_in[85:0];
 
   // instantiations
 
@@ -154,10 +143,10 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
-    .dio_t (gpio_t[11:0]),
-    .dio_i (gpio_o[11:0]),
-    .dio_o (gpio_i[11:0]),
+  ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
+    .dio_t (gpio_t[19:0]),
+    .dio_i (gpio_o[19:0]),
+    .dio_o (gpio_i[19:0]),
     .dio_p (gpio_bd));
 
   system_wrapper i_system_wrapper (
@@ -186,7 +175,7 @@ module system_top (
     .gp_in_0 (gp_in_s[31:0]),
     .gp_in_1 (gp_in_s[63:32]),
     .gp_in_2 (gp_in_s[95:64]),
-    .gp_in_3 (gp_misc_s),
+    .gp_in_3 (32'd0),
     .gp_out_0 (gp_out_s[31:0]),
     .gp_out_1 (gp_out_s[63:32]),
     .gp_out_2 (gp_out_s[95:64]),
diff --git a/projects/pzsdr2/common/ccbrk_bd.tcl b/projects/pzsdr2/common/ccbrk_bd.tcl
index b4e3c00cd..a09cda635 100644
--- a/projects/pzsdr2/common/ccbrk_bd.tcl
+++ b/projects/pzsdr2/common/ccbrk_bd.tcl
@@ -47,7 +47,3 @@ ad_connect  gp_out_2 axi_gpreg/up_gp_out_2
 ad_connect  gp_out_3 axi_gpreg/up_gp_out_3
 ad_cpu_interconnect 0x41200000 axi_gpreg
 
-## temporary (remove ila indirectly)
-
-delete_bd_objs [get_bd_cells ila_adc]
-
diff --git a/projects/pzsdr2/common/ccbrk_constr.xdc b/projects/pzsdr2/common/ccbrk_constr.xdc
new file mode 100644
index 000000000..1321299c9
--- /dev/null
+++ b/projects/pzsdr2/common/ccbrk_constr.xdc
@@ -0,0 +1,248 @@
+
+## constraints (ccbrk.c + ccbrk_lb.a)
+## ad9361 clkout forward
+
+set_property  -dict {PACKAGE_PIN  A7      IOSTANDARD  LVCMOS18} [get_ports  clkout_out]   ; ## (lb: gpio_bd[15])  U1,A7,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32
+
+## push-buttons- led- dip-switches- loopbacks- (ps7 gpio)
+
+set_property  -dict {PACKAGE_PIN  J3      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[0]]   ; ## (lb: gpio_bd[4])   U1,J3,IO_L12_MRCC_33_JX1_N,JX1,83,PB_GPIO_0,P4,31
+set_property  -dict {PACKAGE_PIN  D8      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[1]]   ; ## (lb: gpio_bd[5])   U1,D8,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19
+set_property  -dict {PACKAGE_PIN  F9      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[2]]   ; ## (lb: gpio_bd[6])   U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26
+set_property  -dict {PACKAGE_PIN  E8      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[3]]   ; ## (lb: gpio_bd[12])  U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28
+set_property  -dict {PACKAGE_PIN  A8      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[4]]   ; ## (lb: gpio_bd[0])   U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16
+set_property  -dict {PACKAGE_PIN  W14     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[5]]   ; ## (lb: gpio_bd[1])   U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2,P13,3
+set_property  -dict {PACKAGE_PIN  W17     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[6]]   ; ## (lb: gpio_bd[2])   U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1,P13,4
+set_property  -dict {PACKAGE_PIN  Y16     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[7]]   ; ## (lb: i2c_scl)      U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 (U1,AF24,SCL,JX2,17,I2C_SCL,P2,14)
+set_property  -dict {PACKAGE_PIN  Y15     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[8]]   ; ## (lb: none)         U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0
+set_property  -dict {PACKAGE_PIN  W16     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[9]]   ; ## (lb: none)         U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1
+set_property  -dict {PACKAGE_PIN  W15     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[10]]  ; ## (lb: none)         U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2
+set_property  -dict {PACKAGE_PIN  V19     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[11]]  ; ## (lb: none)         U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3
+
+## orphans- io- (ps7 gpio)
+
+set_property  -dict {PACKAGE_PIN  V18     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[12]]  ; ## (lb: gpio_bd[3])   U1,V18,IO_25_13_JX2,JX2,14,IO_25_13_JX2,P2,3
+set_property  -dict {PACKAGE_PIN  AB24    IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[13]]  ; ## (lb: i2c_sda)      U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 (U1,AF25,SDA,JX2,19,I2C_SDA,P2,16)
+set_property  -dict {PACKAGE_PIN  AA24    IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[14]]  ; ## (lb: none)         U1,AA24,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P
+set_property  -dict {PACKAGE_PIN  N8      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[15]]  ; ## (lb: clkout_out)   U1,N8,IO_25_33_JX1,JX1,10,IO_25_33_JX1,P7,31
+
+## ps7- fixed io- to- fpga regular io (ps7 gpio)
+
+set_property  -dict {PACKAGE_PIN  K3      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[16]]  ; ## U1,K3,IO_L11_SRCC_33_JX1_N,JX1,76,IO_L11_SRCC_33_JX1_N,P4,32 (U1,E26,PS_MIO00_500_JX4,JX4,97,PS_MIO00_500_JX4,P5,21)
+set_property  -dict {PACKAGE_PIN  A9      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[17]]  ; ## U1,A9,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9            (U1,B20,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11)
+set_property  -dict {PACKAGE_PIN  E5      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[18]]  ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20           (U1,C24,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21)
+set_property  -dict {PACKAGE_PIN  E6      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[19]]  ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25           (U1,A25,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23)
+
+## ps7- fixed io- to- ps7- fixed io (reference only)
+## U1,B19,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,E17,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22
+
+## ps7- fixed io- orphans (reference only)
+## U1,B25,PS_MIO13_500_JX4,JX4,91,PS_MIO13_500_JX4,P5,9
+## U1,D23,PS_MIO14_500_JX4,JX4,93,PS_MIO14_500_JX4,P5,11
+## U1,B26,PS_MIO11_500_JX4,JX4,88,PS_MIO11_500_JX4,P7,12
+
+## fpga- regular io
+
+set_property  -dict {PACKAGE_PIN  AA25    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]    ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,IO_L01_13_JX2_P,P2,6
+set_property  -dict {PACKAGE_PIN  AB26    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]     ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,IO_L02_13_JX2_P,P2,5
+set_property  -dict {PACKAGE_PIN  AB25    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]    ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,IO_L01_13_JX2_N,P2,8
+set_property  -dict {PACKAGE_PIN  AC26    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]     ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,IO_L02_13_JX2_N,P2,7
+set_property  -dict {PACKAGE_PIN  AE25    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]    ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,IO_L03_13_JX2_P,P2,10
+set_property  -dict {PACKAGE_PIN  AD25    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]     ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,IO_L04_13_JX2_P,P2,9
+set_property  -dict {PACKAGE_PIN  AE26    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]    ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,IO_L03_13_JX2_N,P2,12
+set_property  -dict {PACKAGE_PIN  AD26    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]     ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,IO_L04_13_JX2_N,P2,11
+set_property  -dict {PACKAGE_PIN  AE22    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]    ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,IO_L07_13_JX2_P,P2,20
+set_property  -dict {PACKAGE_PIN  AE23    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]     ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,IO_L08_13_JX2_P,P2,19
+set_property  -dict {PACKAGE_PIN  AF22    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]    ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,IO_L07_13_JX2_N,P2,22
+set_property  -dict {PACKAGE_PIN  AF23    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]     ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,IO_L08_13_JX2_N,P2,21
+set_property  -dict {PACKAGE_PIN  AB21    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]    ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,IO_L09_13_JX2_P,P2,24
+set_property  -dict {PACKAGE_PIN  AA22    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]     ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,IO_L10_13_JX2_P,P2,23
+set_property  -dict {PACKAGE_PIN  AB22    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]    ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,IO_L09_13_JX2_N,P2,26
+set_property  -dict {PACKAGE_PIN  AA23    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]     ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,IO_L10_13_JX2_N,P2,25
+set_property  -dict {PACKAGE_PIN  AD23    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]    ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28
+set_property  -dict {PACKAGE_PIN  AC23    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]     ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27
+set_property  -dict {PACKAGE_PIN  AD24    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]    ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30
+set_property  -dict {PACKAGE_PIN  AC24    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]     ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29
+set_property  -dict {PACKAGE_PIN  AD20    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]   ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32
+set_property  -dict {PACKAGE_PIN  AC21    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]    ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31
+set_property  -dict {PACKAGE_PIN  AD21    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]   ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34
+set_property  -dict {PACKAGE_PIN  AC22    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]    ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33
+set_property  -dict {PACKAGE_PIN  AF19    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]   ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38
+set_property  -dict {PACKAGE_PIN  AE20    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]    ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37
+set_property  -dict {PACKAGE_PIN  AF20    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]   ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40
+set_property  -dict {PACKAGE_PIN  AE21    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]    ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39
+set_property  -dict {PACKAGE_PIN  AD18    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]   ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42
+set_property  -dict {PACKAGE_PIN  AE18    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]    ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41
+set_property  -dict {PACKAGE_PIN  AD19    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]   ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44
+set_property  -dict {PACKAGE_PIN  AF18    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]    ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43
+set_property  -dict {PACKAGE_PIN  W20     IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]   ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46
+set_property  -dict {PACKAGE_PIN  AA20    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]    ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45
+set_property  -dict {PACKAGE_PIN  Y20     IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]   ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48
+set_property  -dict {PACKAGE_PIN  AB20    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]    ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47
+set_property  -dict {PACKAGE_PIN  AC18    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]   ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52
+set_property  -dict {PACKAGE_PIN  AA19    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]    ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,IO_L22_13_JX2_P,P2,51
+set_property  -dict {PACKAGE_PIN  AC19    IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]   ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54
+set_property  -dict {PACKAGE_PIN  AB19    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]    ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,IO_L22_13_JX2_N,P2,53
+set_property  -dict {PACKAGE_PIN  W18     IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]   ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,IO_L23_13_JX2_P,P2,56
+set_property  -dict {PACKAGE_PIN  Y18     IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]    ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,IO_L24_13_JX2_P,P2,55
+set_property  -dict {PACKAGE_PIN  W19     IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]   ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,IO_L23_13_JX2_N,P2,58
+set_property  -dict {PACKAGE_PIN  AA18    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]    ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,IO_L24_13_JX2_N,P2,57
+set_property  -dict {PACKAGE_PIN  G4      IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]   ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,IO_L01_33_JX1_P,P4,2
+set_property  -dict {PACKAGE_PIN  D4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]    ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,IO_L02_33_JX1_P,P4,1
+set_property  -dict {PACKAGE_PIN  F4      IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]   ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,IO_L01_33_JX1_N,P4,4
+set_property  -dict {PACKAGE_PIN  D3      IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]    ; ## U1,D3,IO_L02_33_JX1_N,JX1,43,IO_L02_33_JX1_N,P4,3
+set_property  -dict {PACKAGE_PIN  G2      IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]   ; ## U1,G2,IO_L03_33_JX1_P,JX1,42,IO_L03_33_JX1_P,P4,6
+set_property  -dict {PACKAGE_PIN  D1      IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]    ; ## U1,D1,IO_L04_33_JX1_P,JX1,47,IO_L04_33_JX1_P,P4,5
+set_property  -dict {PACKAGE_PIN  F2      IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]   ; ## U1,F2,IO_L03_33_JX1_N,JX1,44,IO_L03_33_JX1_N,P4,8
+set_property  -dict {PACKAGE_PIN  C1      IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]    ; ## U1,C1,IO_L04_33_JX1_N,JX1,49,IO_L04_33_JX1_N,P4,7
+set_property  -dict {PACKAGE_PIN  E2      IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]   ; ## U1,E2,IO_L05_33_JX1_P,JX1,54,IO_L05_33_JX1_P,P4,14
+set_property  -dict {PACKAGE_PIN  F3      IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]    ; ## U1,F3,IO_L06_33_JX1_P,JX1,61,IO_L06_33_JX1_P,P4,13
+set_property  -dict {PACKAGE_PIN  E1      IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]   ; ## U1,E1,IO_L05_33_JX1_N,JX1,56,IO_L05_33_JX1_N,P4,16
+set_property  -dict {PACKAGE_PIN  E3      IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]    ; ## U1,E3,IO_L06_33_JX1_N,JX1,63,IO_L06_33_JX1_N,P4,15
+set_property  -dict {PACKAGE_PIN  J1      IOSTANDARD  LVCMOS18} [get_ports  gp_out[28]]   ; ## U1,J1,IO_L07_33_JX1_P,JX1,62,IO_L07_33_JX1_P,P4,18
+set_property  -dict {PACKAGE_PIN  H4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[28]]    ; ## U1,H4,IO_L08_33_JX1_P,JX1,67,IO_L08_33_JX1_P,P4,17
+set_property  -dict {PACKAGE_PIN  H1      IOSTANDARD  LVCMOS18} [get_ports  gp_out[29]]   ; ## U1,H1,IO_L07_33_JX1_N,JX1,64,IO_L07_33_JX1_N,P4,20
+set_property  -dict {PACKAGE_PIN  H3      IOSTANDARD  LVCMOS18} [get_ports  gp_in[29]]    ; ## U1,H3,IO_L08_33_JX1_N,JX1,69,IO_L08_33_JX1_N,P4,19
+set_property  -dict {PACKAGE_PIN  K2      IOSTANDARD  LVCMOS18} [get_ports  gp_out[30]]   ; ## U1,K2,IO_L09_33_JX1_P,JX1,68,IO_L09_33_JX1_P,P4,26
+set_property  -dict {PACKAGE_PIN  H2      IOSTANDARD  LVCMOS18} [get_ports  gp_in[30]]    ; ## U1,H2,IO_L10_33_JX1_P,JX1,73,IO_L10_33_JX1_P,P4,25
+set_property  -dict {PACKAGE_PIN  K1      IOSTANDARD  LVCMOS18} [get_ports  gp_out[31]]   ; ## U1,K1,IO_L09_33_JX1_N,JX1,70,IO_L09_33_JX1_N,P4,28
+set_property  -dict {PACKAGE_PIN  G1      IOSTANDARD  LVCMOS18} [get_ports  gp_in[31]]    ; ## U1,G1,IO_L10_33_JX1_N,JX1,75,IO_L10_33_JX1_N,P4,27
+set_property  -dict {PACKAGE_PIN  L3      IOSTANDARD  LVCMOS18} [get_ports  gp_out[32]]   ; ## U1,L3,IO_L11_SRCC_33_JX1_P,JX1,74,IO_L11_SRCC_33_JX1_P,P4,30
+set_property  -dict {PACKAGE_PIN  J4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[32]]    ; ## U1,J4,IO_L12_MRCC_33_JX1_P,JX1,81,IO_L12_MRCC_33_JX1_P,P4,29
+set_property  -dict {PACKAGE_PIN  M2      IOSTANDARD  LVCMOS18} [get_ports  gp_out[33]]   ; ## U1,M2,IO_L16_33_JX1_P,JX1,11,IO_L16_33_JX1_P,P5,2
+set_property  -dict {PACKAGE_PIN  N4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[33]]    ; ## U1,N4,IO_L17_33_JX1_P,JX1,12,IO_L17_33_JX1_P,P5,1
+set_property  -dict {PACKAGE_PIN  L2      IOSTANDARD  LVCMOS18} [get_ports  gp_out[34]]   ; ## U1,L2,IO_L16_33_JX1_N,JX1,13,IO_L16_33_JX1_N,P5,4
+set_property  -dict {PACKAGE_PIN  M4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[34]]    ; ## U1,M4,IO_L17_33_JX1_N,JX1,14,IO_L17_33_JX1_N,P5,3
+set_property  -dict {PACKAGE_PIN  N1      IOSTANDARD  LVCMOS18} [get_ports  gp_out[35]]   ; ## U1,N1,IO_L18_33_JX1_P,JX1,17,IO_L18_33_JX1_P,P5,6
+set_property  -dict {PACKAGE_PIN  M7      IOSTANDARD  LVCMOS18} [get_ports  gp_in[35]]    ; ## U1,M7,IO_L19_33_JX1_P,JX1,18,IO_L19_33_JX1_P,P5,5
+set_property  -dict {PACKAGE_PIN  M1      IOSTANDARD  LVCMOS18} [get_ports  gp_out[36]]   ; ## U1,M1,IO_L18_33_JX1_N,JX1,19,IO_L18_33_JX1_N,P5,8
+set_property  -dict {PACKAGE_PIN  L7      IOSTANDARD  LVCMOS18} [get_ports  gp_in[36]]    ; ## U1,L7,IO_L19_33_JX1_N,JX1,20,IO_L19_33_JX1_N,P5,7
+set_property  -dict {PACKAGE_PIN  M8      IOSTANDARD  LVCMOS18} [get_ports  gp_out[37]]   ; ## U1,M8,IO_L21_33_JX1_P,JX1,24,IO_L21_33_JX1_P,P5,14
+set_property  -dict {PACKAGE_PIN  K5      IOSTANDARD  LVCMOS18} [get_ports  gp_in[37]]    ; ## U1,K5,IO_L20_33_JX1_P,JX1,23,IO_L20_33_JX1_P,P5,13
+set_property  -dict {PACKAGE_PIN  L8      IOSTANDARD  LVCMOS18} [get_ports  gp_out[38]]   ; ## U1,L8,IO_L21_33_JX1_N,JX1,26,IO_L21_33_JX1_N,P5,16
+set_property  -dict {PACKAGE_PIN  J5      IOSTANDARD  LVCMOS18} [get_ports  gp_in[38]]    ; ## U1,J5,IO_L20_33_JX1_N,JX1,25,IO_L20_33_JX1_N,P5,15
+set_property  -dict {PACKAGE_PIN  N7      IOSTANDARD  LVCMOS18} [get_ports  gp_out[39]]   ; ## U1,N7,IO_L23_33_JX1_P,JX1,30,IO_L23_33_JX1_P,P5,18
+set_property  -dict {PACKAGE_PIN  K6      IOSTANDARD  LVCMOS18} [get_ports  gp_in[39]]    ; ## U1,K6,IO_L22_33_JX1_P,JX1,29,IO_L22_33_JX1_P,P5,17
+set_property  -dict {PACKAGE_PIN  N6      IOSTANDARD  LVCMOS18} [get_ports  gp_out[40]]   ; ## U1,N6,IO_L23_33_JX1_N,JX1,32,IO_L23_33_JX1_N,P5,20
+set_property  -dict {PACKAGE_PIN  J6      IOSTANDARD  LVCMOS18} [get_ports  gp_in[40]]    ; ## U1,J6,IO_L22_33_JX1_N,JX1,31,IO_L22_33_JX1_N,P5,19
+set_property  -dict {PACKAGE_PIN  D5      IOSTANDARD  LVCMOS18} [get_ports  gp_out[41]]   ; ## U1,D5,IO_L10_34_JX4_N,JX4,44,IO_L10_34_JX4_N,P6,27
+set_property  -dict {PACKAGE_PIN  K10     IOSTANDARD  LVCMOS18} [get_ports  gp_in[41]]    ; ## U1,K10,IO_25_34_JX4,JX4,64,IO_25_34_JX4,P5,23
+set_property  -dict {PACKAGE_PIN  K8      IOSTANDARD  LVCMOS18} [get_ports  gp_out[42]]   ; ## U1,K8,IO_L24_33_JX1_P,JX1,36,IO_L24_33_JX1_P,P5,26
+set_property  -dict {PACKAGE_PIN  L5      IOSTANDARD  LVCMOS18} [get_ports  gp_in[42]]    ; ## U1,L5,IO_L14_SRCC_33_JX1_P,JX1,48,IO_L14_SRCC_33_JX1_P,P5,25
+set_property  -dict {PACKAGE_PIN  K7      IOSTANDARD  LVCMOS18} [get_ports  gp_out[43]]   ; ## U1,K7,IO_L24_33_JX1_N,JX1,38,IO_L24_33_JX1_N,P5,28
+set_property  -dict {PACKAGE_PIN  L4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[43]]    ; ## U1,L4,IO_L14_SRCC_33_JX1_N,JX1,50,IO_L14_SRCC_33_JX1_N,P5,27
+set_property  -dict {PACKAGE_PIN  N3      IOSTANDARD  LVCMOS18} [get_ports  gp_out[44]]   ; ## U1,N3,IO_L15_33_JX1_P,JX1,53,IO_L15_33_JX1_P,P5,30
+set_property  -dict {PACKAGE_PIN  M6      IOSTANDARD  LVCMOS18} [get_ports  gp_in[44]]    ; ## U1,M6,IO_L13_MRCC_33_JX1_P,JX1,82,IO_L13_MRCC_33_JX1_P,P5,29
+set_property  -dict {PACKAGE_PIN  N2      IOSTANDARD  LVCMOS18} [get_ports  gp_out[45]]   ; ## U1,N2,IO_L15_33_JX1_N,JX1,55,IO_L15_33_JX1_N,P5,32
+set_property  -dict {PACKAGE_PIN  M5      IOSTANDARD  LVCMOS18} [get_ports  gp_in[45]]    ; ## U1,M5,IO_L13_MRCC_33_JX1_N,JX1,84,IO_L13_MRCC_33_JX1_N,P5,31
+set_property  -dict {PACKAGE_PIN  J11     IOSTANDARD  LVCMOS18} [get_ports  gp_out[46]]   ; ## U1,J11,IO_L01_34_JX4_P,JX4,19,IO_L01_34_JX4_P,P6,2
+set_property  -dict {PACKAGE_PIN  G6      IOSTANDARD  LVCMOS18} [get_ports  gp_in[46]]    ; ## U1,G6,IO_L02_34_JX4_P,JX4,20,IO_L02_34_JX4_P,P6,1
+set_property  -dict {PACKAGE_PIN  H11     IOSTANDARD  LVCMOS18} [get_ports  gp_out[47]]   ; ## U1,H11,IO_L01_34_JX4_N,JX4,21,IO_L01_34_JX4_N,P6,4
+set_property  -dict {PACKAGE_PIN  G5      IOSTANDARD  LVCMOS18} [get_ports  gp_in[47]]    ; ## U1,G5,IO_L02_34_JX4_N,JX4,22,IO_L02_34_JX4_N,P6,3
+set_property  -dict {PACKAGE_PIN  H9      IOSTANDARD  LVCMOS18} [get_ports  gp_out[48]]   ; ## U1,H9,IO_L03_34_JX4_P,JX4,25,IO_L03_34_JX4_P,P6,6
+set_property  -dict {PACKAGE_PIN  H7      IOSTANDARD  LVCMOS18} [get_ports  gp_in[48]]    ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,IO_L04_34_JX4_P,P6,5
+set_property  -dict {PACKAGE_PIN  G9      IOSTANDARD  LVCMOS18} [get_ports  gp_out[49]]   ; ## U1,G9,IO_L03_34_JX4_N,JX4,27,IO_L03_34_JX4_N,P6,8
+set_property  -dict {PACKAGE_PIN  H6      IOSTANDARD  LVCMOS18} [get_ports  gp_in[49]]    ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,IO_L04_34_JX4_N,P6,7
+set_property  -dict {PACKAGE_PIN  J10     IOSTANDARD  LVCMOS18} [get_ports  gp_out[50]]   ; ## U1,J10,IO_L05_34_JX4_P,JX4,31,IO_L05_34_JX4_P,P6,14
+set_property  -dict {PACKAGE_PIN  J8      IOSTANDARD  LVCMOS18} [get_ports  gp_in[50]]    ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,IO_L06_34_JX4_P,P6,13
+set_property  -dict {PACKAGE_PIN  J9      IOSTANDARD  LVCMOS18} [get_ports  gp_out[51]]   ; ## U1,J9,IO_L05_34_JX4_N,JX4,33,IO_L05_34_JX4_N,P6,16
+set_property  -dict {PACKAGE_PIN  H8      IOSTANDARD  LVCMOS18} [get_ports  gp_in[51]]    ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,IO_L06_34_JX4_N,P6,15
+set_property  -dict {PACKAGE_PIN  F5      IOSTANDARD  LVCMOS18} [get_ports  gp_out[52]]   ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,IO_L07_34_JX4_P,P6,18
+set_property  -dict {PACKAGE_PIN  D9      IOSTANDARD  LVCMOS18} [get_ports  gp_in[52]]    ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,IO_L08_34_JX4_P,P6,17
+set_property  -dict {PACKAGE_PIN  F8      IOSTANDARD  LVCMOS18} [get_ports  gp_out[53]]   ; ## U1,F8,IO_L11_SRCC_34_JX4_P,JX4,45,IO_L11_SRCC_34_JX4_P,P6,30
+set_property  -dict {PACKAGE_PIN  G7      IOSTANDARD  LVCMOS18} [get_ports  gp_in[53]]    ; ## U1,G7,IO_L12_MRCC_34_JX4_P,JX4,46,IO_L12_MRCC_34_JX4_P,P6,29
+set_property  -dict {PACKAGE_PIN  E7      IOSTANDARD  LVCMOS18} [get_ports  gp_out[54]]   ; ## U1,E7,IO_L11_SRCC_34_JX4_N,JX4,47,IO_L11_SRCC_34_JX4_N,P6,32
+set_property  -dict {PACKAGE_PIN  F7      IOSTANDARD  LVCMOS18} [get_ports  gp_in[54]]    ; ## U1,F7,IO_L12_MRCC_34_JX4_N,JX4,48,IO_L12_MRCC_34_JX4_N,P6,31
+set_property  -dict {PACKAGE_PIN  C8      IOSTANDARD  LVCMOS18} [get_ports  gp_out[55]]   ; ## U1,C8,IO_L13_MRCC_34_JX4_P,JX4,51,IO_L13_MRCC_34_JX4_P,P7,2
+set_property  -dict {PACKAGE_PIN  D6      IOSTANDARD  LVCMOS18} [get_ports  gp_in[55]]    ; ## U1,D6,IO_L14_SRCC_34_JX4_P,JX4,52,IO_L14_SRCC_34_JX4_P,P7,1
+set_property  -dict {PACKAGE_PIN  C7      IOSTANDARD  LVCMOS18} [get_ports  gp_out[56]]   ; ## U1,C7,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4
+set_property  -dict {PACKAGE_PIN  C6      IOSTANDARD  LVCMOS18} [get_ports  gp_in[56]]    ; ## U1,C6,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3
+set_property  -dict {PACKAGE_PIN  C9      IOSTANDARD  LVCMOS18} [get_ports  gp_out[57]]   ; ## U1,C9,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6
+set_property  -dict {PACKAGE_PIN  B10     IOSTANDARD  LVCMOS18} [get_ports  gp_in[57]]    ; ## U1,B10,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5
+set_property  -dict {PACKAGE_PIN  B9      IOSTANDARD  LVCMOS18} [get_ports  gp_out[58]]   ; ## U1,B9,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8
+set_property  -dict {PACKAGE_PIN  A10     IOSTANDARD  LVCMOS18} [get_ports  gp_in[58]]    ; ## U1,A10,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7
+set_property  -dict {PACKAGE_PIN  C4      IOSTANDARD  LVCMOS18} [get_ports  gp_out[59]]   ; ## U1,C4,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18
+set_property  -dict {PACKAGE_PIN  B5      IOSTANDARD  LVCMOS18} [get_ports  gp_in[59]]    ; ## U1,B5,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17
+set_property  -dict {PACKAGE_PIN  C3      IOSTANDARD  LVCMOS18} [get_ports  gp_out[60]]   ; ## U1,C3,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20
+set_property  -dict {PACKAGE_PIN  B4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[60]]    ; ## U1,B4,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19
+set_property  -dict {PACKAGE_PIN  B6      IOSTANDARD  LVCMOS18} [get_ports  gp_out[61]]   ; ## U1,B6,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26
+set_property  -dict {PACKAGE_PIN  A4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[61]]    ; ## U1,A4,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25
+set_property  -dict {PACKAGE_PIN  A5      IOSTANDARD  LVCMOS18} [get_ports  gp_out[62]]   ; ## U1,A5,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28
+set_property  -dict {PACKAGE_PIN  A3      IOSTANDARD  LVCMOS18} [get_ports  gp_in[62]]    ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27
+set_property  -dict {PACKAGE_PIN  B7      IOSTANDARD  LVCMOS18} [get_ports  gp_out[63]]   ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30
+set_property  -dict {PACKAGE_PIN  L9      IOSTANDARD  LVCMOS18} [get_ports  gp_in[63]]    ; ## U1,L9,IO_00_33_JX1,JX1,9,IO_00_33_JX1,P7,29
+set_property  -dict {PACKAGE_PIN  AD15    IOSTANDARD  LVCMOS18} [get_ports  gp_out[64]]   ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,IO_L15_12_JX3_N,P13,6
+set_property  -dict {PACKAGE_PIN  AF14    IOSTANDARD  LVCMOS18} [get_ports  gp_in[64]]    ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,IO_L16_12_JX3_N,P13,5
+set_property  -dict {PACKAGE_PIN  AD16    IOSTANDARD  LVCMOS18} [get_ports  gp_out[65]]   ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,IO_L15_12_JX3_P,P13,8
+set_property  -dict {PACKAGE_PIN  AF15    IOSTANDARD  LVCMOS18} [get_ports  gp_in[65]]    ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,IO_L16_12_JX3_P,P13,7
+set_property  -dict {PACKAGE_PIN  AD14    IOSTANDARD  LVCMOS18} [get_ports  gp_out[66]]   ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,IO_L13_MRCC_12_JX3_N,P13,10
+set_property  -dict {PACKAGE_PIN  AB14    IOSTANDARD  LVCMOS18} [get_ports  gp_in[66]]    ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,IO_L14_SRCC_12_JX3_N,P13,9
+set_property  -dict {PACKAGE_PIN  AC14    IOSTANDARD  LVCMOS18} [get_ports  gp_out[67]]   ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,IO_L13_MRCC_12_JX3_P,P13,12
+set_property  -dict {PACKAGE_PIN  AB15    IOSTANDARD  LVCMOS18} [get_ports  gp_in[67]]    ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,IO_L14_SRCC_12_JX3_P,P13,11
+set_property  -dict {PACKAGE_PIN  AD11    IOSTANDARD  LVCMOS18} [get_ports  gp_out[68]]   ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,IO_L11_SRCC_12_JX3_N,P13,14
+set_property  -dict {PACKAGE_PIN  AD13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[68]]    ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,IO_L12_MRCC_12_JX3_N,P13,13
+set_property  -dict {PACKAGE_PIN  AC12    IOSTANDARD  LVCMOS18} [get_ports  gp_out[69]]   ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,IO_L11_SRCC_12_JX3_P,P13,16
+set_property  -dict {PACKAGE_PIN  AC13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[69]]    ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,IO_L12_MRCC_12_JX3_P,P13,15
+set_property  -dict {PACKAGE_PIN  AF10    IOSTANDARD  LVCMOS18} [get_ports  gp_out[70]]   ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,IO_L09_12_JX3_N,P13,20
+set_property  -dict {PACKAGE_PIN  AF13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[70]]    ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,IO_L10_12_JX3_N,P13,19
+set_property  -dict {PACKAGE_PIN  AE11    IOSTANDARD  LVCMOS18} [get_ports  gp_out[71]]   ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,IO_L09_12_JX3_P,P13,22
+set_property  -dict {PACKAGE_PIN  AE13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[71]]    ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,IO_L10_12_JX3_P,P13,21
+set_property  -dict {PACKAGE_PIN  AD10    IOSTANDARD  LVCMOS18} [get_ports  gp_out[72]]   ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,IO_L07_12_JX3_N,P13,24
+set_property  -dict {PACKAGE_PIN  AF12    IOSTANDARD  LVCMOS18} [get_ports  gp_in[72]]    ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,IO_L08_12_JX3_N,P13,23
+set_property  -dict {PACKAGE_PIN  AE10    IOSTANDARD  LVCMOS18} [get_ports  gp_out[73]]   ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,IO_L07_12_JX3_P,P13,26
+set_property  -dict {PACKAGE_PIN  AE12    IOSTANDARD  LVCMOS18} [get_ports  gp_in[73]]    ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,IO_L08_12_JX3_P,P13,25
+set_property  -dict {PACKAGE_PIN  Y13     IOSTANDARD  LVCMOS18} [get_ports  gp_out[74]]   ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,IO_L05_12_JX3_N,P13,28
+set_property  -dict {PACKAGE_PIN  AA12    IOSTANDARD  LVCMOS18} [get_ports  gp_in[74]]    ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,IO_L06_12_JX3_N,P13,27
+set_property  -dict {PACKAGE_PIN  W13     IOSTANDARD  LVCMOS18} [get_ports  gp_out[75]]   ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,IO_L05_12_JX3_P,P13,30
+set_property  -dict {PACKAGE_PIN  AA13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[75]]    ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,IO_L06_12_JX3_P,P13,29
+set_property  -dict {PACKAGE_PIN  AA10    IOSTANDARD  LVCMOS18} [get_ports  gp_out[76]]   ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,IO_L03_12_JX3_N,P13,32
+set_property  -dict {PACKAGE_PIN  AB10    IOSTANDARD  LVCMOS18} [get_ports  gp_in[76]]    ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,IO_L04_12_JX3_N,P13,31
+set_property  -dict {PACKAGE_PIN  Y10     IOSTANDARD  LVCMOS18} [get_ports  gp_out[77]]   ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,IO_L03_12_JX3_P,P13,34
+set_property  -dict {PACKAGE_PIN  AB11    IOSTANDARD  LVCMOS18} [get_ports  gp_in[77]]    ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,IO_L04_12_JX3_P,P13,33
+set_property  -dict {PACKAGE_PIN  Y11     IOSTANDARD  LVCMOS18} [get_ports  gp_out[78]]   ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,IO_L01_12_JX3_N,P13,36
+set_property  -dict {PACKAGE_PIN  AC11    IOSTANDARD  LVCMOS18} [get_ports  gp_in[78]]    ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,IO_L02_12_JX3_N,P13,35
+set_property  -dict {PACKAGE_PIN  Y12     IOSTANDARD  LVCMOS18} [get_ports  gp_out[79]]   ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,IO_L01_12_JX3_P,P13,38
+set_property  -dict {PACKAGE_PIN  AB12    IOSTANDARD  LVCMOS18} [get_ports  gp_in[79]]    ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,IO_L02_12_JX3_P,P13,37
+set_property  -dict {PACKAGE_PIN  AE16    IOSTANDARD  LVCMOS18} [get_ports  gp_out[80]]   ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,IO_L17_12_JX2_P,P13,42
+set_property  -dict {PACKAGE_PIN  AE17    IOSTANDARD  LVCMOS18} [get_ports  gp_in[80]]    ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,IO_L18_12_JX2_P,P13,41
+set_property  -dict {PACKAGE_PIN  AE15    IOSTANDARD  LVCMOS18} [get_ports  gp_out[81]]   ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,IO_L17_12_JX2_N,P13,44
+set_property  -dict {PACKAGE_PIN  AF17    IOSTANDARD  LVCMOS18} [get_ports  gp_in[81]]    ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,IO_L18_12_JX2_N,P13,43
+set_property  -dict {PACKAGE_PIN  Y17     IOSTANDARD  LVCMOS18} [get_ports  gp_out[82]]   ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,IO_L19_12_JX2_P,P13,46
+set_property  -dict {PACKAGE_PIN  AB17    IOSTANDARD  LVCMOS18} [get_ports  gp_in[82]]    ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,IO_L20_12_JX2_P,P13,45
+set_property  -dict {PACKAGE_PIN  AA17    IOSTANDARD  LVCMOS18} [get_ports  gp_out[83]]   ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,IO_L19_12_JX2_N,P13,48
+set_property  -dict {PACKAGE_PIN  AB16    IOSTANDARD  LVCMOS18} [get_ports  gp_in[83]]    ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,IO_L20_12_JX2_N,P13,47
+set_property  -dict {PACKAGE_PIN  AC17    IOSTANDARD  LVCMOS18} [get_ports  gp_out[84]]   ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,IO_L21_12_JX2_P,P13,50
+set_property  -dict {PACKAGE_PIN  AA15    IOSTANDARD  LVCMOS18} [get_ports  gp_in[84]]    ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,IO_L22_12_JX2_P,P13,49
+set_property  -dict {PACKAGE_PIN  AC16    IOSTANDARD  LVCMOS18} [get_ports  gp_out[85]]   ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,IO_L21_12_JX2_N,P13,52
+set_property  -dict {PACKAGE_PIN  AA14    IOSTANDARD  LVCMOS18} [get_ports  gp_in[85]]    ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,IO_L22_12_JX2_N,P13,51
+
+## transceiver loop-backs (on-ccbrk)
+
+set_property  -dict {PACKAGE_PIN  R6}     [get_ports  gt_ref_clk_p]   ; ## U1,R6,MGTREFCLK0_112_JX1_P (JX1,87)
+set_property  -dict {PACKAGE_PIN  R5}     [get_ports  gt_ref_clk_n]   ; ## U1,R5,MGTREFCLK0_112_JX1_N (JX1,89)
+set_property  -dict {PACKAGE_PIN  AB4}    [get_ports  gt_rx_p[0]]     ; ## U1,AB4,MGTXRX0_112_JX1_P   (JX1,88)
+set_property  -dict {PACKAGE_PIN  AB3}    [get_ports  gt_rx_n[0]]     ; ## U1,AB3,MGTXRX0_112_JX1_N   (JX1,90)
+set_property  -dict {PACKAGE_PIN  Y4}     [get_ports  gt_rx_p[1]]     ; ## U1,Y4,MGTXRX1_112_JX1_P    (JX1,91)
+set_property  -dict {PACKAGE_PIN  Y3}     [get_ports  gt_rx_n[1]]     ; ## U1,Y3,MGTXRX1_112_JX1_N    (JX1,93)
+set_property  -dict {PACKAGE_PIN  V4}     [get_ports  gt_rx_p[2]]     ; ## U1,V4,MGTXRX2_112_JX1_P    (JX1,92)
+set_property  -dict {PACKAGE_PIN  V3}     [get_ports  gt_rx_n[2]]     ; ## U1,V3,MGTXRX2_112_JX1_N    (JX1,94)
+set_property  -dict {PACKAGE_PIN  T4}     [get_ports  gt_rx_p[3]]     ; ## U1,T4,MGTXRX3_112_JX1_P    (JX1,97)
+set_property  -dict {PACKAGE_PIN  T3}     [get_ports  gt_rx_n[3]]     ; ## U1,T3,MGTXRX3_112_JX1_N    (JX1,99)
+set_property  -dict {PACKAGE_PIN  AA2}    [get_ports  gt_tx_p[0]]     ; ## U1,AA2,MGTXTX0_112_JX3_P   (JX3,8)
+set_property  -dict {PACKAGE_PIN  AA1}    [get_ports  gt_tx_n[0]]     ; ## U1,AA1,MGTXTX0_112_JX3_N   (JX3,10)
+set_property  -dict {PACKAGE_PIN  W2}     [get_ports  gt_tx_p[1]]     ; ## U1,W2,MGTXTX1_112_JX3_P    (JX3,13)
+set_property  -dict {PACKAGE_PIN  W1}     [get_ports  gt_tx_n[1]]     ; ## U1,W1,MGTXTX1_112_JX3_N    (JX3,15)
+set_property  -dict {PACKAGE_PIN  U2}     [get_ports  gt_tx_p[2]]     ; ## U1,U2,MGTXTX2_112_JX3_P    (JX3,14)
+set_property  -dict {PACKAGE_PIN  U1}     [get_ports  gt_tx_n[2]]     ; ## U1,U1,MGTXTX2_112_JX3_N    (JX3,16)
+set_property  -dict {PACKAGE_PIN  R2}     [get_ports  gt_tx_p[3]]     ; ## U1,R2,MGTXTX3_112_JX3_P    (JX3,19)
+set_property  -dict {PACKAGE_PIN  R1}     [get_ports  gt_tx_n[3]]     ; ## U1,R1,MGTXTX3_112_JX3_N    (JX3,21)
+
+## clocks
+
+create_clock -name ref_clk      -period  4.00 [get_ports gt_ref_clk_p]
+create_clock -name xcvr_clk_0   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+create_clock -name xcvr_clk_1   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+create_clock -name xcvr_clk_2   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[2].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+create_clock -name xcvr_clk_3   -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[3].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+
+
diff --git a/projects/pzsdr2/common/pzsdr2_bd.tcl b/projects/pzsdr2/common/pzsdr2_bd.tcl
new file mode 100644
index 000000000..85a82ff18
--- /dev/null
+++ b/projects/pzsdr2/common/pzsdr2_bd.tcl
@@ -0,0 +1,365 @@
+
+# create board design
+# default ports
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
+create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+
+create_bd_port -dir O spi0_csn_2_o
+create_bd_port -dir O spi0_csn_1_o
+create_bd_port -dir O spi0_csn_0_o
+create_bd_port -dir I spi0_csn_i
+create_bd_port -dir I spi0_clk_i
+create_bd_port -dir O spi0_clk_o
+create_bd_port -dir I spi0_sdo_i
+create_bd_port -dir O spi0_sdo_o
+create_bd_port -dir I spi0_sdi_i
+
+create_bd_port -dir O spi1_csn_2_o
+create_bd_port -dir O spi1_csn_1_o
+create_bd_port -dir O spi1_csn_0_o
+create_bd_port -dir I spi1_csn_i
+create_bd_port -dir I spi1_clk_i
+create_bd_port -dir O spi1_clk_o
+create_bd_port -dir I spi1_sdo_i
+create_bd_port -dir O spi1_sdo_o
+create_bd_port -dir I spi1_sdi_i
+
+create_bd_port -dir I -from 63 -to 0 gpio_i
+create_bd_port -dir O -from 63 -to 0 gpio_o
+create_bd_port -dir O -from 63 -to 0 gpio_t
+
+# otg
+
+set otg_vbusoc      [create_bd_port -dir I otg_vbusoc]
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_11
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+create_bd_port -dir I -type intr ps_intr_15
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PACKAGE_NAME {fbg676}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET_RESET_SELECT {Separate reset pins}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 8}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET1_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET1_RESET_IO {MIO 51}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 50}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 7}] $sys_ps7
+set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.053}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.059}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.065}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.066}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.264}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.265}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.330}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.330}] $sys_ps7
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
+set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
+set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
+set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+
+# interface connections
+
+ad_connect  ddr sys_ps7/DDR
+ad_connect  gpio_i sys_ps7/GPIO_I
+ad_connect  gpio_o sys_ps7/GPIO_O
+ad_connect  gpio_t sys_ps7/GPIO_T
+ad_connect  fixed_io sys_ps7/FIXED_IO
+ad_connect  iic_main axi_iic_main/iic
+ad_connect  sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
+ad_connect  sys_logic_inv/Op1 otg_vbusoc
+
+# spi connections
+
+ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
+ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
+ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
+ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
+ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
+ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
+ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
+ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
+ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+
+ad_connect  spi1_csn_2_o sys_ps7/SPI1_SS2_O
+ad_connect  spi1_csn_1_o sys_ps7/SPI1_SS1_O
+ad_connect  spi1_csn_0_o sys_ps7/SPI1_SS_O
+ad_connect  spi1_csn_i sys_ps7/SPI1_SS_I
+ad_connect  spi1_clk_i sys_ps7/SPI1_SCLK_I
+ad_connect  spi1_clk_o sys_ps7/SPI1_SCLK_O
+ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
+ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
+ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
+
+# interrupts
+
+ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15 ps_intr_15
+ad_connect  sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
+ad_connect  sys_concat_intc/In13 ps_intr_13
+ad_connect  sys_concat_intc/In12 ps_intr_12
+ad_connect  sys_concat_intc/In11 ps_intr_11
+ad_connect  sys_concat_intc/In10 ps_intr_10
+ad_connect  sys_concat_intc/In9 ps_intr_09
+ad_connect  sys_concat_intc/In8 ps_intr_08
+ad_connect  sys_concat_intc/In7 ps_intr_07
+ad_connect  sys_concat_intc/In6 ps_intr_06
+ad_connect  sys_concat_intc/In5 ps_intr_05
+ad_connect  sys_concat_intc/In4 ps_intr_04
+ad_connect  sys_concat_intc/In3 ps_intr_03
+ad_connect  sys_concat_intc/In2 ps_intr_02
+ad_connect  sys_concat_intc/In1 ps_intr_01
+ad_connect  sys_concat_intc/In0 ps_intr_00
+
+# interconnects
+
+ad_cpu_interconnect 0x41600000 axi_iic_main
+
+# ad9361
+
+create_bd_port -dir O enable
+create_bd_port -dir O txnrx
+create_bd_port -dir I up_enable
+create_bd_port -dir I up_txnrx
+create_bd_port -dir O tdd_sync_o
+create_bd_port -dir I tdd_sync_i
+create_bd_port -dir O tdd_sync_t
+
+# ad9361 core
+
+set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
+set_property -dict [list CONFIG.ID {0}] $axi_ad9361
+set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361
+
+set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
+
+set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_dac_upack
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack
+
+set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}]  $axi_ad9361_adc_dma
+
+set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_pack
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack
+
+set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo
+set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo
+set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
+set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
+
+set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
+set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
+
+# connections
+
+ad_connect  sys_200m_clk axi_ad9361/delay_clk
+ad_connect  axi_ad9361_clk axi_ad9361/l_clk
+ad_connect  axi_ad9361_clk axi_ad9361/clk
+ad_connect  enable axi_ad9361/enable
+ad_connect  txnrx axi_ad9361/txnrx
+ad_connect  up_enable axi_ad9361/up_enable
+ad_connect  up_txnrx axi_ad9361/up_txnrx
+ad_connect  axi_ad9361_clk util_ad9361_adc_fifo/din_clk
+ad_connect  axi_ad9361/rst util_ad9361_adc_fifo/din_rst
+ad_connect  sys_cpu_clk util_ad9361_adc_fifo/dout_clk
+ad_connect  sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
+ad_connect  sys_cpu_clk util_ad9361_adc_pack/adc_clk
+ad_connect  sys_cpu_reset util_ad9361_adc_pack/adc_rst
+ad_connect  sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
+ad_connect  axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
+ad_connect  axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
+ad_connect  axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
+ad_connect  axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
+ad_connect  axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
+ad_connect  axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
+ad_connect  axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
+ad_connect  axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
+ad_connect  axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
+ad_connect  axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
+ad_connect  axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
+ad_connect  util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
+ad_connect  util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
+ad_connect  util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
+ad_connect  util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
+ad_connect  util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
+ad_connect  util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
+ad_connect  util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
+ad_connect  util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
+ad_connect  util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
+ad_connect  util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
+ad_connect  util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
+ad_connect  util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
+ad_connect  util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
+ad_connect  util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
+ad_connect  util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
+ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
+ad_connect  util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
+ad_connect  axi_ad9361_clk util_ad9361_dac_upack/dac_clk
+ad_connect  axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
+ad_connect  util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
+ad_connect  util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
+ad_connect  util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
+ad_connect  util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
+ad_connect  util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
+ad_connect  util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
+ad_connect  util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
+ad_connect  util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
+ad_connect  util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
+ad_connect  util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
+ad_connect  util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
+ad_connect  util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
+ad_connect  util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
+ad_connect  util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
+ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
+ad_connect  sys_cpu_clk util_ad9361_tdd_sync/clk
+ad_connect  sys_cpu_resetn util_ad9361_tdd_sync/rstn
+ad_connect  util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
+ad_connect  util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
+ad_connect  tdd_sync_t axi_ad9361/tdd_sync_cntr
+ad_connect  tdd_sync_o util_ad9361_tdd_sync/sync_out
+ad_connect  tdd_sync_i util_ad9361_tdd_sync/sync_in
+
+# interconnects
+
+ad_cpu_interconnect 0x79020000 axi_ad9361
+ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
+ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
+ad_connect  sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
+ad_connect  sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
+
+# interrupts
+
+ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
+ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
+
+## customization of core to disable data path logic (less resources)
+## interface type - 1R1T (1) or 2R2T (0) (default is 2R2T)
+## 2R2T supports 1R1T as a run time option.
+## 1R1T allows core to run at a lower rate (1/2 of 2R2T)
+
+set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361] 
+
+## interface type - CMOS (1) or LVDS (0) (default is LVDS)
+## CMOS allows core to run at a lower rate (1/2 of LVDS)
+
+set_property CONFIG.CMOS_OR_LVDS_N 0  [get_bd_cells axi_ad9361]
+
+## data-path disable (global control)- allows removal of DSP functions within the core.
+## also removes the corresponding AXI control interface registers
+
+set_property CONFIG.ADC_DATAPATH_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.DAC_DATAPATH_DISABLE 0  [get_bd_cells axi_ad9361]
+
+## data-path disable (individual control)- effective ONLY if DATAPATH_DISABLE is 0x0.
+
+set_property CONFIG.ADC_DATAFORMAT_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.ADC_DCFILTER_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.ADC_IQCORRECTION_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.ADC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
+
+set_property CONFIG.DAC_DDS_DISABLE 0 [get_bd_cells axi_ad9361]
+set_property CONFIG.DAC_IQCORRECTION_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
+
+## tdd-disable (control is moved exclusively to GPIO)
+
+set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361]
+
+
diff --git a/projects/pzsdr2/common/pzsdr2_constr.xdc b/projects/pzsdr2/common/pzsdr2_constr.xdc
new file mode 100644
index 000000000..a5681880f
--- /dev/null
+++ b/projects/pzsdr2/common/pzsdr2_constr.xdc
@@ -0,0 +1,195 @@
+
+# constraints (pzsdr2.e)
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35           U1,G14,IO_L11_35_ENABLE
+set_property  -dict {PACKAGE_PIN  F14  IOSTANDARD LVCMOS18} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35           U1,F14,IO_L11_35_TXNRX
+
+set_property  -dict {PACKAGE_PIN  D13  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35                U1,D13,IO_L19_35_CTRL_OUT0
+set_property  -dict {PACKAGE_PIN  C13  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35           U1,C13,IO_L19_35_CTRL_OUT1
+set_property  -dict {PACKAGE_PIN  C14  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35           U1,C14,IO_L20_35_CTRL_OUT2
+set_property  -dict {PACKAGE_PIN  B14  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35           U1,B14,IO_L20_35_CTRL_OUT3
+set_property  -dict {PACKAGE_PIN  A15  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35      U1,A15,IO_L21_35_CTRL_OUT4
+set_property  -dict {PACKAGE_PIN  A14  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35      U1,A14,IO_L21_35_CTRL_OUT5
+set_property  -dict {PACKAGE_PIN  C12  IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35           U1,C12,IO_L22_35_CTRL_OUT6
+set_property  -dict {PACKAGE_PIN  B12  IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35           U1,B12,IO_L22_35_CTRL_OUT7
+set_property  -dict {PACKAGE_PIN  C2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34                U1,C2,IO_L23_34_CTRL_IN0
+set_property  -dict {PACKAGE_PIN  B1   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34                U1,B1,IO_L23_34_CTRL_IN1
+set_property  -dict {PACKAGE_PIN  B2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34                U1,B2,IO_L24_34_CTRL_IN2
+set_property  -dict {PACKAGE_PIN  A2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34                U1,A2,IO_L24_34_CTRL_IN3
+set_property  -dict {PACKAGE_PIN  G16  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35          U1,G16,IO_L10_35_EN_AGC
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35          U1,G15,IO_L10_35_SYNC_IN
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS18} [get_ports gpio_resetb]                       ; ## IO_0_VRN_35                  U1,H16,IO_00_35_AD9361_RST
+set_property  -dict {PACKAGE_PIN  K11  IOSTANDARD LVCMOS18} [get_ports gpio_clksel]                       ; ## IO_0_VRN_34                  U1,K11,IO_00_34_AD9361_CLKSEL
+
+set_property  -dict {PACKAGE_PIN  C11  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35                U1,C11,IO_L23_35_SPI_ENB
+set_property  -dict {PACKAGE_PIN  B11  IOSTANDARD LVCMOS18} [get_ports spi_clk]                           ; ## IO_L23N_T3_35                U1,B11,IO_L23_35_SPI_CLK
+set_property  -dict {PACKAGE_PIN  A13  IOSTANDARD LVCMOS18} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35          U1,A13,IO_L24_35_SPI_DI
+set_property  -dict {PACKAGE_PIN  A12  IOSTANDARD LVCMOS18} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35          U1,A12,IO_L24_35_SPI_DO
+
+set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports clkout_in]                         ; ## IO_25_VRP_35                 U1,K12,IO_25_35_AD9361_CLKOUT
+
+# iic (ccbrk with loopback drives i2c back to the FPGA)
+
+set_property  -dict {PACKAGE_PIN  AF24 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L5P_T0_13                 U1,AF24,SCL,JX2,17,I2C_SCL,P2,14,P2,4,U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4
+set_property  -dict {PACKAGE_PIN  AF25 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L5N_T0_13                 U1,AF25,SDA,JX2,19,I2C_SDA,P2,16,P2,15,U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15
+
+##    reference-only
+##    --------------
+##    ad9361 (optional rf-card)
+##    --------------------------
+##    JX4,1,GPO0
+##    JX4,2,GPO1
+##    JX4,3,GPO2
+##    JX4,4,GPO3
+##    JX4,7,AUXADC
+##    JX4,8,AUXDAC1
+##    JX4,10,AUXDAC2
+##    JX4,63,AD9361_CLK
+
+##    fixed-io (ps7) (som only, others are carrier specific)
+##    ------------------------------------------------------
+##    U1,D26,PS_MIO01_500_QSPI0_SS_B
+##    U1,F23,PS_MIO06_500_QSPI0_SCLK
+##    U1,E25,PS_MIO02_500_QSPI0_IO0
+##    U1,D25,PS_MIO03_500_QSPI0_IO1
+##    U1,F24,PS_MIO04_500_QSPI0_IO2
+##    U1,C26,PS_MIO05_500_QSPI0_IO3
+##    U1,A24,PS_MIO08_500_ETH0_RESETN               (magnetics-RJ45- JX3,47,ETH_PHY_LED0)
+##    U1,A19,PS_MIO53_501_ETH0_MDIO                 (magnetics-RJ45- JX3,48,ETH_PHY_LED1)
+##    U1,A20,PS_MIO52_501_ETH0_MDC                  (magnetics-RJ45- JX3,51,ETH_MD1_P)
+##    U1,G22,PS_MIO22_501_ETH0_RX_CLK               (magnetics-RJ45- JX3,53,ETH_MD1_N)
+##    U1,F18,PS_MIO27_501_ETH0_RX_CTL               (magnetics-RJ45- JX3,52,ETH_MD2_P)
+##    U1,F20,PS_MIO23_501_ETH0_RX_D0                (magnetics-RJ45- JX3,54,ETH_MD2_N)
+##    U1,J19,PS_MIO24_501_ETH0_RX_D1                (magnetics-RJ45- JX3,57,ETH_MD3_P)
+##    U1,F19,PS_MIO25_501_ETH0_RX_D2                (magnetics-RJ45- JX3,59,ETH_MD3_N)
+##    U1,H17,PS_MIO26_501_ETH0_RX_D3                (magnetics-RJ45- JX3,58,ETH_MD4_P)
+##    U1,G21,PS_MIO16_501_ETH0_TX_CLK               (magnetics-RJ45- JX3,60,ETH_MD4_N)
+##    U1,F22,PS_MIO21_501_ETH0_TX_CTL
+##    U1,G17,PS_MIO17_501_ETH0_TX_D0
+##    U1,G20,PS_MIO18_501_ETH0_TX_D1
+##    U1,G19,PS_MIO19_501_ETH0_TX_D2
+##    U1,H19,PS_MIO20_501_ETH0_TX_D3
+##    U1,B21,PS_MIO48_501_JX4,JX4,99,USB_UART_RXD
+##    U1,A18,PS_MIO49_501_JX4,JX4,98,USB_UART_TXD
+##    U1,C22,PS_MIO40_501_SD0_CLK                   (off-board- JX3,43,SDIO_CLKB1)
+##    U1,C19,PS_MIO41_501_SD0_CMD                   (off-board- JX3,34,SDIO_CMDB1)
+##    U1,F17,PS_MIO42_501_SD0_DATA0                 (off-board- JX3,37,SDIO_DAT0B1)
+##    U1,D18,PS_MIO43_501_SD0_DATA1                 (off-board- JX3,36,SDIO_DAT1B1)
+##    U1,E18,PS_MIO44_501_SD0_DATA2                 (off-board- JX3,39,SDIO_DAT2B1)
+##    U1,C18,PS_MIO45_501_SD0_DATA3                 (off-board- JX3,38,SDIO_DAT3B1)
+##    U1,B22,PS_MIO50_501_SD0_CD                    (off-board- JX3,41,JX3_SD1_CDN)
+##    U1,E23,PS_MIO07_500_USB_RESET_B               (usb- JX3,63,USB_ID)
+##    U1,D24,PS_MIO09_500_USB_CLK_PD                (usb- JX3,67,USB_OTG_P)
+##    U1,E20,PS_MIO29_501_USB0_DIR                  (usb- JX3,69,USB_OTG_N)
+##    U1,K19,PS_MIO30_501_USB0_STP                  (usb- JX3,68,USB_VBUS_OTG)
+##    U1,E21,PS_MIO31_501_USB0_NXT                  (usb- JX3,70,USB_OTG_CPEN)
+##    U1,K16,PS_MIO36_501_USB0_CLK      
+##    U1,K17,PS_MIO32_501_USB0_D0
+##    U1,E22,PS_MIO33_501_USB0_D1
+##    U1,J16,PS_MIO34_501_USB0_D2
+##    U1,D19,PS_MIO35_501_USB0_D3
+##    U1,J18,PS_MIO28_501_USB0_D4
+##    U1,D20,PS_MIO37_501_USB0_D5
+##    U1,D21,PS_MIO38_501_USB0_D6
+##    U1,C21,PS_MIO39_501_USB0_D7
+##    U1,A23,UNNAMED_3_ICXC7Z035_I94_PSMIO12        (JX4,86,PS_MIO12_500_JX4)
+
+##    ddr (fixed-io)
+##    --------------
+##    U1,H24,DDR3_DQS0_P
+##    U1,G25,DDR3_DQS0_N
+##    U1,L24,DDR3_DQS1_P
+##    U1,L25,DDR3_DQS1_N
+##    U1,P25,DDR3_DQS2_P
+##    U1,R25,DDR3_DQS2_N
+##    U1,W24,DDR3_DQS3_P
+##    U1,W25,DDR3_DQS3_N
+##    U1,J26,DDR3_DQ0
+##    U1,F25,DDR3_DQ1
+##    U1,J25,DDR3_DQ2
+##    U1,G26,DDR3_DQ3
+##    U1,H26,DDR3_DQ4
+##    U1,H23,DDR3_DQ5
+##    U1,J24,DDR3_DQ6
+##    U1,J23,DDR3_DQ7
+##    U1,K26,DDR3_DQ8
+##    U1,L23,DDR3_DQ9
+##    U1,M26,DDR3_DQ10
+##    U1,K23,DDR3_DQ11
+##    U1,M25,DDR3_DQ12
+##    U1,N24,DDR3_DQ13
+##    U1,M24,DDR3_DQ14
+##    U1,N23,DDR3_DQ15
+##    U1,R26,DDR3_DQ16
+##    U1,P24,DDR3_DQ17
+##    U1,N26,DDR3_DQ18
+##    U1,P23,DDR3_DQ19
+##    U1,T24,DDR3_DQ20
+##    U1,T25,DDR3_DQ21
+##    U1,T23,DDR3_DQ22
+##    U1,R23,DDR3_DQ23
+##    U1,V24,DDR3_DQ24
+##    U1,U26,DDR3_DQ25
+##    U1,U24,DDR3_DQ26
+##    U1,U25,DDR3_DQ27
+##    U1,W26,DDR3_DQ28
+##    U1,Y25,DDR3_DQ29
+##    U1,Y26,DDR3_DQ30
+##    U1,W23,DDR3_DQ31
+##    U1,G24,DDR3_DM0
+##    U1,K25,DDR3_DM1
+##    U1,P26,DDR3_DM2
+##    U1,V26,DDR3_DM3
+##    U1,K22,DDR3_A0
+##    U1,K20,DDR3_A1
+##    U1,N21,DDR3_A2
+##    U1,L22,DDR3_A3
+##    U1,M20,DDR3_A4
+##    U1,N22,DDR3_A5
+##    U1,L20,DDR3_A6
+##    U1,J21,DDR3_A7
+##    U1,T20,DDR3_A8
+##    U1,U20,DDR3_A9
+##    U1,M22,DDR3_A10
+##    U1,H21,DDR3_A11
+##    U1,P20,DDR3_A12
+##    U1,J20,DDR3_A13
+##    U1,R20,DDR3_A14
+##    U1,U22,DDR3_BA0
+##    U1,T22,DDR3_BA1
+##    U1,R22,DDR3_BA2
+##    U1,R21,DDR3_CK_P
+##    U1,P21,DDR3_CK_N
+##    U1,U21,DDR3_CKE
+##    U1,H22,DDR3_RST#
+##    U1,Y21,DDR3_CS#
+##    U1,V22,DDR3_WE#
+##    U1,V23,DDR3_RAS#
+##    U1,Y23,DDR3_CAS#
+##    U1,Y22,DDR3_ODT
+
+##    resets, clock and power controls
+##    --------------------------------
+##    U1,B24,UNNAMED_3_ICXC7Z035_I94_PSCLK50,33.33MEGHZ
+##    U1,A22,PS-SRST#
+##    U1,C23,PWR_GD_1.35V
+##    JX2,10,PG_1P8V
+##    JX2,11,PG_MODULE
+##    JX1,5,PWR_ENABLE
+##    JX1,6,CARRIER_RESET
+
+##    JTAG
+##    ----
+##    U1,W11,JTAG_TMS,JX1,2,JTAG_TMS
+##    U1,W12,JTAG_TCK,JX1,1,JTAG_TCK
+##    U1,V11,JTAG_TDI,JX1,4,FPGA_TDI,JTAG_TDI
+##    U1,W9,FPGA_DONE,JX1,8,CFG_DONE
+
+##    GBT I/O (clocks)
+##    ----------------
+##    U1,R5,UNNAMED_7_CAP_I125_N2 (JX1,87,MGTREFCLK0_112_JX1_P)
+##    U1,R6,UNNAMED_7_CAP_I123_N2 (JX1,89,MGTREFCLK0_112_JX1_N)
+##    U1,U6,UNNAMED_7_CAP_I126_N2 (JX3,2,MGTREFCLK1_112_JX3_P)
+##    U1,U5,UNNAMED_7_CAP_I124_N2 (JX3,4,MGTREFCLK1_112_JX3_N)
+
diff --git a/projects/pzsdr2/common/pzsdr2_constr_cmos.xdc b/projects/pzsdr2/common/pzsdr2_constr_cmos.xdc
new file mode 100644
index 000000000..530511b80
--- /dev/null
+++ b/projects/pzsdr2/common/pzsdr2_constr_cmos.xdc
@@ -0,0 +1,42 @@
+
+# constraints (pzsdr2.e)
+# ad9361 (SWAP == 0x1)
+
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports rx_clk_in]       ; ## IO_L12P_T1_MRCC_35         U1,J14,IO_L12_MRCC_35_DATA_CLK_P
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18} [get_ports rx_frame_in]     ; ## IO_L7P_T1_AD2P_35          U1,H13,IO_L07_35_RX_FRAME_P
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]   ; ## IO_L1N_T0_AD0N_35          U1,E12,IO_L01_35_RX_D0_N
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]   ; ## IO_L1P_T0_AD0P_35          U1,F12,IO_L01_35_RX_D0_P
+set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]   ; ## IO_L2N_T0_AD8N_35          U1,D10,IO_L02_35_RX_D1_N
+set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]   ; ## IO_L2P_T0_AD8P_35          U1,E10,IO_L02_35_RX_D1_P
+set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]   ; ## IO_L3N_T0_DQS_AD1N_35      U1,F10,IO_L03_35_RX_D2_N
+set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]   ; ## IO_L3P_T0_DQS_AD1P_35      U1,G10,IO_L03_35_RX_D2_P
+set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]   ; ## IO_L4N_T0_35               U1,D11,IO_L04_35_RX_D3_N
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]   ; ## IO_L4P_T0_35               U1,E11,IO_L04_35_RX_D3_P
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]   ; ## IO_L5N_T0_AD9N_35          U1,G11,IO_L05_35_RX_D4_N
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]   ; ## IO_L5P_T0_AD9P_35          U1,G12,IO_L05_35_RX_D4_P
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]  ; ## IO_L6N_T0_VREF_35          U1,E13,IO_L06_35_RX_D5_N
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]  ; ## IO_L6P_T0_35               U1,F13,IO_L06_35_RX_D5_P
+
+set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]      ; ## IO_L8P_T1_AD10P_35         U1,K13,IO_L08_35_FB_CLK_P
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]    ; ## IO_L9P_T1_DQS_AD3P_35      U1,K15,IO_L09_35_TX_FRAME_P
+set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]  ; ## IO_L13N_T2_MRCC_35         U1,D14,IO_L13_35_TX_D0_N
+set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]  ; ## IO_L13P_T2_MRCC_35         U1,D15,IO_L13_35_TX_D0_P
+set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]  ; ## IO_L14N_T2_AD4N_SRCC_35    U1,E15,IO_L14_35_TX_D1_N
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]  ; ## IO_L14P_T2_AD4P_SRCC_35    U1,F15,IO_L14_35_TX_D1_P
+set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]  ; ## IO_L15N_T2_DQS_AD12N_35    U1,C16,IO_L15_35_TX_D2_N
+set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]  ; ## IO_L15P_T2_DQS_AD12P_35    U1,C17,IO_L15_35_TX_D2_P
+set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]  ; ## IO_L16N_T2_35              U1,D16,IO_L16_35_TX_D3_N
+set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]  ; ## IO_L16P_T2_35              U1,E16,IO_L16_35_TX_D3_P
+set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]  ; ## IO_L17N_T2_AD5N_35         U1,B15,IO_L17_35_TX_D4_N
+set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]  ; ## IO_L17P_T2_AD5P_35         U1,B16,IO_L17_35_TX_D4_P
+set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L18N_T2_AD13N_35        U1,A17,IO_L18_35_TX_D5_N
+set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L18P_T2_AD13P_35        U1,B17,IO_L18_35_TX_D5_P
+
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]]       ; ## IO_L8N_T1_AD10N_35         U1,J13,IO_L08_35_FB_CLK_N
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]]       ; ## IO_L9N_T1_DQS_AD3N_35      U1,J15,IO_L09_35_TX_FRAME_N
+
+# clocks
+
+create_clock -name rx_clk       -period  8 [get_ports rx_clk_in]
+create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+
diff --git a/projects/pzsdr2/common/pzsdr2_constr_lvds.xdc b/projects/pzsdr2/common/pzsdr2_constr_lvds.xdc
new file mode 100644
index 000000000..febfb5977
--- /dev/null
+++ b/projects/pzsdr2/common/pzsdr2_constr_lvds.xdc
@@ -0,0 +1,42 @@
+
+# constraints (pzsdr2.e)
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35           U1,J14,IO_L12_MRCC_35_DATA_CLK_P
+set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35           U1,H14,IO_L12_MRCC_35_DATA_CLK_N
+set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35            U1,H13,IO_L07_35_RX_FRAME_P
+set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35            U1,H12,IO_L07_35_RX_FRAME_N
+set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35            U1,F12,IO_L01_35_RX_D0_P
+set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35            U1,E12,IO_L01_35_RX_D0_N
+set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35            U1,E10,IO_L02_35_RX_D1_P
+set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35            U1,D10,IO_L02_35_RX_D1_N
+set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35        U1,G10,IO_L03_35_RX_D2_P
+set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35        U1,F10,IO_L03_35_RX_D2_N
+set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35                 U1,E11,IO_L04_35_RX_D3_P
+set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35                 U1,D11,IO_L04_35_RX_D3_N
+set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35            U1,G12,IO_L05_35_RX_D4_P
+set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35            U1,G11,IO_L05_35_RX_D4_N
+set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35                 U1,F13,IO_L06_35_RX_D5_P
+set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35            U1,E13,IO_L06_35_RX_D5_N
+set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVDS}     [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35           U1,K13,IO_L08_35_FB_CLK_P
+set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVDS}     [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35           U1,J13,IO_L08_35_FB_CLK_N
+set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVDS}     [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35        U1,K15,IO_L09_35_TX_FRAME_P
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVDS}     [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35        U1,J15,IO_L09_35_TX_FRAME_N
+set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35           U1,D15,IO_L13_35_TX_D0_P
+set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVDS}     [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35           U1,D14,IO_L13_35_TX_D0_N
+set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35      U1,F15,IO_L14_35_TX_D1_P
+set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35      U1,E15,IO_L14_35_TX_D1_N
+set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35      U1,C17,IO_L15_35_TX_D2_P
+set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35      U1,C16,IO_L15_35_TX_D2_N
+set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35                U1,E16,IO_L16_35_TX_D3_P
+set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35                U1,D16,IO_L16_35_TX_D3_N
+set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35           U1,B16,IO_L17_35_TX_D4_P
+set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35           U1,B15,IO_L17_35_TX_D4_N
+set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35          U1,B17,IO_L18_35_TX_D5_P
+set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVDS}     [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35          U1,A17,IO_L18_35_TX_D5_N
+
+# clocks
+
+create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+

From 4905e80df8cd7e26a94c22c094ed5737a78ba176 Mon Sep 17 00:00:00 2001
From: rejeesh kutty <rejeesh.kutty@analog.com>
Date: Tue, 15 Nov 2016 14:16:46 -0500
Subject: [PATCH 705/972] Update README.md

updated
---
 projects/pzsdr2/README.md | 28 +++++++++++++++-------------
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/projects/pzsdr2/README.md b/projects/pzsdr2/README.md
index 01526c903..97a32bb24 100644
--- a/projects/pzsdr2/README.md
+++ b/projects/pzsdr2/README.md
@@ -4,23 +4,25 @@ This folder contains the PZSDR2 SOM projects for each of the carrier boards.
 
 ## Board Design Files
 
-common/pzsdr2_bd.tcl ; pzsdr2 SOM module board design file.
-common/ccbrk_bd.tcl ; carrier, break out board design file.
-common/ccfmc_bd.tcl ; carrier, fmc board design file.
-common/ccpci_bd.tcl ; carrier, pci-e board design file.
-common/ccusb_bd.tcl ; carrier, usb board design file.
+#### common/pzsdr2_bd.tcl ; pzsdr2 SOM module board design file.
+#### common/ccbrk_bd.tcl ; carrier, break out board design file.
+#### common/ccfmc_bd.tcl ; carrier, fmc board design file.
+#### common/ccpci_bd.tcl ; carrier, pci-e board design file.
+#### common/ccusb_bd.tcl ; carrier, usb board design file.
+
+FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
 
 ## Board Constraint Files
 
-common/pzsdr2_constr.xdc ; pzsdr2 SOM base constraints file.
-common/pzsdr2_constr_cmos.xdc ; pzsdr2 SOM CMOS mode constraints file.
-common/pzsdr2_constr_lvds.xdc ; pzsdr2 SOM LVDS mode constraints file.
+#### common/pzsdr2_constr.xdc ; pzsdr2 SOM base constraints file.
+#### common/pzsdr2_constr_cmos.xdc ; pzsdr2 SOM CMOS mode constraints file.
+#### common/pzsdr2_constr_lvds.xdc ; pzsdr2 SOM LVDS mode constraints file.
 
-common/ccbrk_constr.xdc ; carrier, break out board constraints file.*
-common/ccfmc_constr.xdc ; carrier, fmc board constraints file.*
-common/ccpci_constr.xdc ; carrier, pci-e board constraints file.
-common/ccusb_constr.xdc ; carrier, usb board constraints file.
+#### common/ccbrk_constr.xdc ; carrier, break out board constraints file.
+#### common/ccfmc_constr.xdc ; carrier, fmc board constraints file.
+#### common/ccpci_constr.xdc ; carrier, pci-e board constraints file.
+#### common/ccusb_constr.xdc ; carrier, usb board constraints file.
 
-* FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
+FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
 
 

From 538a1c977f2a41c599f84b9812140d6fc9e3d0c7 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 15 Nov 2016 16:00:55 -0500
Subject: [PATCH 706/972] pzsdr2: make files

---
 projects/pzsdr2/Makefile            |  9 ---------
 projects/pzsdr2/ccbrk_cmos/Makefile | 18 +++++++-----------
 projects/pzsdr2/ccbrk_lvds/Makefile | 18 +++++++-----------
 3 files changed, 14 insertions(+), 31 deletions(-)

diff --git a/projects/pzsdr2/Makefile b/projects/pzsdr2/Makefile
index 6ee1e9a38..3d58fa671 100644
--- a/projects/pzsdr2/Makefile
+++ b/projects/pzsdr2/Makefile
@@ -12,9 +12,6 @@ all:
 	-make -C ccfmc_lvds all
 	-make -C ccpci_lvds all
 	-make -C ccusb_lvds all
-	-make -C ccbox_lvds all
-	-make -C ccbrk_cmos all
-	-make -C ccbrk_lvds all
 
 
 clean: 
@@ -23,9 +20,6 @@ clean:
 	make -C ccfmc_lvds clean
 	make -C ccpci_lvds clean
 	make -C ccusb_lvds clean
-	make -C ccbox_lvds clean
-	make -C ccbrk_cmos clean
-	make -C ccbrk_lvds clean
 
 
 clean-all:
@@ -34,9 +28,6 @@ clean-all:
 	make -C ccfmc_lvds clean-all
 	make -C ccpci_lvds clean-all
 	make -C ccusb_lvds clean-all
-	make -C ccbox_lvds clean-all
-	make -C ccbrk_cmos clean-all
-	make -C ccbrk_lvds clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr2/ccbrk_cmos/Makefile b/projects/pzsdr2/ccbrk_cmos/Makefile
index 4bdcdd903..f674cda7c 100644
--- a/projects/pzsdr2/ccbrk_cmos/Makefile
+++ b/projects/pzsdr2/ccbrk_cmos/Makefile
@@ -8,18 +8,14 @@
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr2_constr_cmos.xdc
+M_DEPS += ../common/pzsdr2_constr.xdc
+M_DEPS += ../common/pzsdr2_bd.tcl
+M_DEPS += ../common/ccbrk_constr.xdc
 M_DEPS += ../common/ccbrk_bd.tcl
-M_DEPS += ../ccbrk_lvds/system_constr.xdc
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_cmos_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -49,7 +45,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_cmos_pzsdr.sdk/system_top.hdf
+all: lib pzsdr2_ccbrk_cmos.sdk/system_top.hdf
 
 
 clean: 
@@ -67,9 +63,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_cmos_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+pzsdr2_ccbrk_cmos.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_cmos_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr2_ccbrk_cmos_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr2/ccbrk_lvds/Makefile b/projects/pzsdr2/ccbrk_lvds/Makefile
index 3888e48e1..5373dd43a 100644
--- a/projects/pzsdr2/ccbrk_lvds/Makefile
+++ b/projects/pzsdr2/ccbrk_lvds/Makefile
@@ -7,19 +7,15 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr2_constr_lvds.xdc
+M_DEPS += ../common/pzsdr2_constr.xdc
+M_DEPS += ../common/pzsdr2_bd.tcl
+M_DEPS += ../common/ccbrk_constr.xdc
 M_DEPS += ../common/ccbrk_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -49,7 +45,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_lvds_pzsdr.sdk/system_top.hdf
+all: lib pzsdr2_ccbrk_lvds.sdk/system_top.hdf
 
 
 clean: 
@@ -67,9 +63,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+pzsdr2_ccbrk_lvds.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_lvds_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr2_ccbrk_lvds_vivado.log 2>&1
 
 
 lib:

From fabbe4981ee71d620ec36da6279afd03375c322d Mon Sep 17 00:00:00 2001
From: rejeesh kutty <rejeesh.kutty@analog.com>
Date: Tue, 15 Nov 2016 16:15:55 -0500
Subject: [PATCH 707/972] Update README.md

updated
---
 projects/pzsdr2/README.md | 44 +++++++++++++++++++++++++++------------
 1 file changed, 31 insertions(+), 13 deletions(-)

diff --git a/projects/pzsdr2/README.md b/projects/pzsdr2/README.md
index 97a32bb24..a9c67b57b 100644
--- a/projects/pzsdr2/README.md
+++ b/projects/pzsdr2/README.md
@@ -3,26 +3,44 @@
 This folder contains the PZSDR2 SOM projects for each of the carrier boards.
 
 ## Board Design Files
+---
 
-#### common/pzsdr2_bd.tcl ; pzsdr2 SOM module board design file.
-#### common/ccbrk_bd.tcl ; carrier, break out board design file.
-#### common/ccfmc_bd.tcl ; carrier, fmc board design file.
-#### common/ccpci_bd.tcl ; carrier, pci-e board design file.
-#### common/ccusb_bd.tcl ; carrier, usb board design file.
+| Directory/File       | Description                            |
+|----------------------|----------------------------------------|
+| common/pzsdr2_bd.tcl | pzsdr2 SOM module board design file.   |
+| common/ccbrk_bd.tcl  | carrier, break out board design file.  |
+| common/ccfmc_bd.tcl  | carrier, fmc board design file.        |
+| common/ccpci_bd.tcl  | carrier, pci-e board design file.      |
+| common/ccusb_bd.tcl  | carrier, usb board design file.        |
 
 FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
 
 ## Board Constraint Files
+---
 
-#### common/pzsdr2_constr.xdc ; pzsdr2 SOM base constraints file.
-#### common/pzsdr2_constr_cmos.xdc ; pzsdr2 SOM CMOS mode constraints file.
-#### common/pzsdr2_constr_lvds.xdc ; pzsdr2 SOM LVDS mode constraints file.
-
-#### common/ccbrk_constr.xdc ; carrier, break out board constraints file.
-#### common/ccfmc_constr.xdc ; carrier, fmc board constraints file.
-#### common/ccpci_constr.xdc ; carrier, pci-e board constraints file.
-#### common/ccusb_constr.xdc ; carrier, usb board constraints file.
+| Directory/File                | Description                                   |
+|-------------------------------|-----------------------------------------------|
+| common/pzsdr2_constr.xdc      | pzsdr2 SOM base constraints file.             |
+| common/pzsdr2_constr_cmos.xdc | pzsdr2 SOM CMOS mode constraints file.        |
+| common/pzsdr2_constr_lvds.xdc | pzsdr2 SOM LVDS mode constraints file.        |
+| common/ccbrk_constr.xdc       | carrier, break out board constraints file.    |
+| common/ccfmc_constr.xdc       | carrier, fmc board constraints file.          |
+| common/ccpci_constr.xdc       | carrier, pci-e board constraints file.        |
+| common/ccusb_constr.xdc       | carrier, usb board constraints file.          |
 
 FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
 
+## Building, Generating Bit Files
+---
+[pzsdr2] cd ccbrk_cmos
+
+[pzsdr2/ccbrk_cmos] make
+
+The make in each carrier directory builds the corresponding project. The above example builds PZSDR2-CCBRK hardware bit files in CMOS mode.
+
+## Documentation
+---
+HDL User Guide
+HDL IP User Guide
+PZSDR2 Wiki
 

From 81e47edcd5fc97b7f3c3612573071d9b319dce8f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Wed, 16 Nov 2016 10:57:39 +0200
Subject: [PATCH 708/972] README: Set links for documentation

---
 projects/pzsdr2/README.md | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/projects/pzsdr2/README.md b/projects/pzsdr2/README.md
index a9c67b57b..a09923a13 100644
--- a/projects/pzsdr2/README.md
+++ b/projects/pzsdr2/README.md
@@ -40,7 +40,11 @@ The make in each carrier directory builds the corresponding project. The above e
 
 ## Documentation
 ---
-HDL User Guide
-HDL IP User Guide
-PZSDR2 Wiki
+ * [HDL Design User Guide]
+ * [IP User Guide]
+ * [PZSDR2 Wiki page]
+ 
+[HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl
+[IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361 
+[PZSDR2 Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr
 

From bdd14c38745c624c8168cff1a8b2bce3b03013dd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20Csomort=C3=A1ni?=
 <Csomi@users.noreply.github.com>
Date: Wed, 16 Nov 2016 11:04:43 +0200
Subject: [PATCH 709/972] README: Delete second rule under headers

By default there is a rule under each header, no need for another one.
---
 projects/pzsdr2/README.md | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/projects/pzsdr2/README.md b/projects/pzsdr2/README.md
index a09923a13..e59185903 100644
--- a/projects/pzsdr2/README.md
+++ b/projects/pzsdr2/README.md
@@ -3,7 +3,6 @@
 This folder contains the PZSDR2 SOM projects for each of the carrier boards.
 
 ## Board Design Files
----
 
 | Directory/File       | Description                            |
 |----------------------|----------------------------------------|
@@ -16,7 +15,6 @@ This folder contains the PZSDR2 SOM projects for each of the carrier boards.
 FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
 
 ## Board Constraint Files
----
 
 | Directory/File                | Description                                   |
 |-------------------------------|-----------------------------------------------|
@@ -31,7 +29,7 @@ FMC & BRK carrier designs includes loopback daughtercards for connectivity testi
 FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
 
 ## Building, Generating Bit Files
----
+
 [pzsdr2] cd ccbrk_cmos
 
 [pzsdr2/ccbrk_cmos] make
@@ -39,7 +37,7 @@ FMC & BRK carrier designs includes loopback daughtercards for connectivity testi
 The make in each carrier directory builds the corresponding project. The above example builds PZSDR2-CCBRK hardware bit files in CMOS mode.
 
 ## Documentation
----
+
  * [HDL Design User Guide]
  * [IP User Guide]
  * [PZSDR2 Wiki page]

From b85a2827488149b2b4620d91e9f0a7e6028ab152 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 16 Nov 2016 10:26:47 -0500
Subject: [PATCH 710/972] fmcomms11- lane swap

---
 library/axi_ad9162/axi_ad9162_channel.v    | 233 ++++-----------------
 library/axi_ad9162/axi_ad9162_if.v         |  32 +--
 projects/fmcomms11/zc706/system_constr.xdc |   2 +-
 3 files changed, 61 insertions(+), 206 deletions(-)

diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v
index c15a3a996..d13fd047e 100644
--- a/library/axi_ad9162/axi_ad9162_channel.v
+++ b/library/axi_ad9162/axi_ad9162_channel.v
@@ -100,8 +100,7 @@ module axi_ad9162_channel (
     
     reg               dac_enable = 'd0;
     reg     [255:0]   dac_data = 'd0;
-    reg     [255:0]   dac_pn7_data = 'd0;
-    reg     [255:0]   dac_pn15_data = 'd0;
+    reg     [255:0]   dac_data_int = 'd0;
     reg     [ 15:0]   dac_dds_phase_00_0 = 'd0;
     reg     [ 15:0]   dac_dds_phase_00_1 = 'd0;
     reg     [ 15:0]   dac_dds_phase_01_0 = 'd0;
@@ -150,65 +149,33 @@ module axi_ad9162_channel (
     wire    [ 15:0]   dac_pat_data_2_s;
     wire    [  3:0]   dac_data_sel_s;
     wire              dac_iq_mode_s;
-    wire    [255:0]   dac_pn7_data_i_s;
-    wire    [255:0]   dac_pn15_data_i_s;
-    wire    [255:0]   dac_pn7_data_s;
-    wire    [255:0]   dac_pn15_data_s;
     wire    [255:0]   dac_pat_data_s;
     wire    [255:0]   dac_dds_data_s;
+
+    // dac sample mux
+
+    always @(posedge dac_clk) begin
+      dac_data[255:240] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[255:240] : dac_data_int[255:240];
+      dac_data[239:224] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[223:208] : dac_data_int[239:224];
+      dac_data[223:208] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[239:224] : dac_data_int[223:208];
+      dac_data[207:192] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[207:192] : dac_data_int[207:192];
+      dac_data[191:176] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[191:176] : dac_data_int[191:176];
+      dac_data[175:160] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[159:144] : dac_data_int[175:160];
+      dac_data[159:144] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[175:160] : dac_data_int[159:144];
+      dac_data[143:128] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[143:128] : dac_data_int[143:128];
+      dac_data[127:112] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[127:112] : dac_data_int[127:112];
+      dac_data[111: 96] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 95: 80] : dac_data_int[111: 96];
+      dac_data[ 95: 80] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[111: 96] : dac_data_int[ 95: 80];
+      dac_data[ 79: 64] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 79: 64] : dac_data_int[ 79: 64];
+      dac_data[ 63: 48] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 63: 48] : dac_data_int[ 63: 48];
+      dac_data[ 47: 32] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 31: 16] : dac_data_int[ 47: 32];
+      dac_data[ 31: 16] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 47: 32] : dac_data_int[ 31: 16];
+      dac_data[ 15:  0] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 15:  0] : dac_data_int[ 15:  0];
+    end
     
+    // dac pattern data
+
     genvar n;
-
-    // PN7 function
-    
-    function [255:0] pn7;
-         input [7:0] din;
-         reg   [255:0] dout;
-         reg   [15:0] dout16;
-         reg   [7:0] din_reg;
-         integer i;
-         integer j;
-         begin
-         din_reg = din;
-           for ( j=0 ; j<16 ; j=j+1)begin
-             for ( i=0 ; i<16 ; i= i+1)begin
-                 din_reg = {din_reg,din_reg[6]^din_reg[5]};
-                 dout16[15-i] = din_reg[0];
-              end
-              dout = {dout16,dout[255:16]};
-           end         
-           pn7 = dout;
-         end
-    endfunction
-    
-    // PN15 function
-    
-    function [255:0] pn15;
-         input [15:0] din;
-         reg   [255:0] dout;
-         reg   [15:0] dout16;
-         reg   [15:0] din_reg;
-         integer i;
-         integer j;
-         begin
-         din_reg = din;
-           for (j=0 ; j<16 ; j=j+1)begin
-             for (i=0 ; i<16 ; i= i+1)begin
-                 din_reg = {din_reg,din_reg[14]^din_reg[13]};
-                 dout16[15-i] = din_reg[0];
-              end
-              dout = {dout16,dout[255:16]};
-           end         
-           pn15 = dout;
-         end
-    endfunction
-    
-    assign dac_pn7_data_i_s = ~dac_pn7_data;
-    assign dac_pn15_data_i_s = ~dac_pn15_data;
-    
-    assign dac_pn7_data_s = dac_pn7_data;
-    assign dac_pn15_data_s = dac_pn15_data;
-
     generate
     for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data
     assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s;
@@ -221,29 +188,13 @@ module axi_ad9162_channel (
     always @(posedge dac_clk) begin
       dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
       case (dac_data_sel_s)
-        4'h7: dac_data <= dac_pn15_data_s;
-        4'h6: dac_data <= dac_pn7_data_s;
-        4'h5: dac_data <= dac_pn15_data_i_s;
-        4'h4: dac_data <= dac_pn7_data_i_s;
-        4'h3: dac_data <= 256'd0;
-        4'h2: dac_data <= dma_data;
-        4'h1: dac_data <= dac_pat_data_s;
-        default: dac_data <= dac_dds_data;
+        4'h3: dac_data_int <= 256'd0;
+        4'h2: dac_data_int <= dma_data;
+        4'h1: dac_data_int <= dac_pat_data_s;
+        default: dac_data_int <= dac_dds_data;
       endcase
     end
     
-    // pn registers
-    
-    always @(posedge dac_clk) begin
-      if (dac_data_sync == 1'b1) begin
-        dac_pn7_data <= {255{1'd1}};
-        dac_pn15_data <= {255{1'd1}};
-      end else begin
-        dac_pn7_data <= pn7(dac_pn7_data[247:240]);
-        dac_pn15_data <= pn15(dac_pn15_data[255:240]);
-      end
-    end
-    
     // dds
     
     always @(posedge dac_clk) begin
@@ -358,11 +309,7 @@ module axi_ad9162_channel (
       end
     end
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[15:0] = 16'd0;
-    end else begin
-    ad_dds i_dds_00 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_00 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_00_0),
@@ -370,14 +317,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_00_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[15:0]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[31:16] = 16'd0;
-    end else begin
-    ad_dds i_dds_01 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_01 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_01_0),
@@ -385,14 +326,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_01_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[31:16]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[47:32] = 16'd0;
-    end else begin
-    ad_dds i_dds_02 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_02 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_02_0),
@@ -400,14 +335,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_02_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[47:32]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[63:48] = 16'd0;
-    end else begin
-    ad_dds i_dds_03 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_03 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_03_0),
@@ -415,14 +344,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_03_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[63:48]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[79:64] = 16'd0;
-    end else begin
-    ad_dds i_dds_04 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_04 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_04_0),
@@ -430,14 +353,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_04_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[79:64]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[95:80] = 16'd0;
-    end else begin
-    ad_dds i_dds_05 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_05 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_05_0),
@@ -445,14 +362,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_05_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[95:80]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[111:96] = 16'd0;
-    end else begin
-    ad_dds i_dds_06 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_06 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_06_0),
@@ -460,14 +371,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_06_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[111:96]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[127:112] = 16'd0;
-    end else begin
-    ad_dds i_dds_07 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_07 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_07_0),
@@ -475,14 +380,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_07_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[127:112]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[143:128] = 16'd0;
-    end else begin
-    ad_dds i_dds_08 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_08 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_08_0),
@@ -490,14 +389,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_08_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[143:128]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[159:144] = 16'd0;
-    end else begin
-    ad_dds i_dds_09 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_09 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_09_0),
@@ -505,14 +398,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_09_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[159:144]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[175:160] = 16'd0;
-    end else begin
-    ad_dds i_dds_10 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_10 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_10_0),
@@ -520,14 +407,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_10_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[175:160]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[191:176] = 16'd0;
-    end else begin
-    ad_dds i_dds_11 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_11 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_11_0),
@@ -535,14 +416,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_11_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[191:176]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[207:192] = 16'd0;
-    end else begin
-    ad_dds i_dds_12 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_12 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_12_0),
@@ -550,14 +425,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_12_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[207:192]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[223:208] = 16'd0;
-    end else begin
-    ad_dds i_dds_13 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_13 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_13_0),
@@ -565,14 +434,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_13_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[223:208]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[239:224] = 16'd0;
-    end else begin
-    ad_dds i_dds_14 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_14 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_14_0),
@@ -580,14 +443,8 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_14_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[239:224]));
-    end
-    endgenerate
     
-    generate
-    if (DATAPATH_DISABLE == 1) begin
-    assign dac_dds_data_s[255:240] = 16'd0;
-    end else begin
-    ad_dds i_dds_15 (
+    ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_15 (
       .clk (dac_clk),
       .dds_format (dac_dds_format),
       .dds_phase_0 (dac_dds_phase_15_0),
@@ -595,8 +452,6 @@ module axi_ad9162_channel (
       .dds_phase_1 (dac_dds_phase_15_1),
       .dds_scale_1 (dac_dds_scale_2_s),
       .dds_data (dac_dds_data_s[255:240]));
-    end
-    endgenerate
     
     // single channel processor
     
diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v
index 59362b429..f114420a4 100644
--- a/library/axi_ad9162/axi_ad9162_if.v
+++ b/library/axi_ad9162/axi_ad9162_if.v
@@ -84,22 +84,22 @@ module axi_ad9162_if (
       tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data[127:120] : dac_data[191:184];
       tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data[191:184] : dac_data[127:120];
       tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data[255:248] : dac_data[ 63: 56];
-      tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data[ 23: 16] : dac_data[215:208];
-      tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data[ 87: 80] : dac_data[151:144];
-      tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data[151:144] : dac_data[ 87: 80];
-      tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data[215:208] : dac_data[ 23: 16];
-      tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data[ 31: 24] : dac_data[223:216];
-      tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data[ 95: 88] : dac_data[159:152];
-      tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data[159:152] : dac_data[ 95: 88];
-      tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data[223:216] : dac_data[ 31: 24];
-      tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data[ 39: 32] : dac_data[231:224];
-      tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data[103: 96] : dac_data[167:160];
-      tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data[167:160] : dac_data[103: 96];
-      tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data[231:224] : dac_data[ 39: 32];
-      tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data[ 47: 40] : dac_data[239:232];
-      tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data[111:104] : dac_data[175:168];
-      tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data[175:168] : dac_data[111:104];
-      tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data[239:232] : dac_data[ 47: 40];
+      tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data[ 39: 32] : dac_data[231:224];
+      tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data[103: 96] : dac_data[167:160];
+      tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data[167:160] : dac_data[103: 96];
+      tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data[231:224] : dac_data[ 39: 32];
+      tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data[ 47: 40] : dac_data[239:232];
+      tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data[111:104] : dac_data[175:168];
+      tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data[175:168] : dac_data[111:104];
+      tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data[239:232] : dac_data[ 47: 40];
+      tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data[ 23: 16] : dac_data[215:208];
+      tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data[ 87: 80] : dac_data[151:144];
+      tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data[151:144] : dac_data[ 87: 80];
+      tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data[215:208] : dac_data[ 23: 16];
+      tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data[ 31: 24] : dac_data[223:216];
+      tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data[ 95: 88] : dac_data[159:152];
+      tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data[159:152] : dac_data[ 95: 88];
+      tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data[223:216] : dac_data[ 31: 24];
       tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data[  7:  0] : dac_data[199:192];
       tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data[ 71: 64] : dac_data[135:128];
       tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data[135:128] : dac_data[ 71: 64];
diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc
index 89407b217..a219f9335 100644
--- a/projects/fmcomms11/zc706/system_constr.xdc
+++ b/projects/fmcomms11/zc706/system_constr.xdc
@@ -67,7 +67,7 @@ set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports ad9162_i
 
 create_clock -name tx_ref_clk   -period  6.40 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  6.40 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name tx_div_clk   -period  3.20 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
 create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9162_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]

From 11347c49beba0dac7c753aa06f9707090f8fbf79 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 16 Nov 2016 13:43:07 -0500
Subject: [PATCH 711/972] fmcomms11- device set to -3

---
 projects/fmcomms11/zc706/system_project.tcl | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/projects/fmcomms11/zc706/system_project.tcl b/projects/fmcomms11/zc706/system_project.tcl
index d0c5093df..cdf235a0d 100644
--- a/projects/fmcomms11/zc706/system_project.tcl
+++ b/projects/fmcomms11/zc706/system_project.tcl
@@ -1,11 +1,11 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project_create fmcomms11_zc706
+
+set_property part xc7z045ffg900-3 [current_project]
 adi_project_files fmcomms11_zc706 [list \
   "../common/fmcomms11_spi.v" \
   "system_top.v" \
@@ -16,4 +16,3 @@ adi_project_files fmcomms11_zc706 [list \
 
 adi_project_run fmcomms11_zc706
 
-

From 95c44b687ea926466a26ffd3fb7700133b829251 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 16 Nov 2016 15:39:23 -0500
Subject: [PATCH 712/972] pzsdr2- fmc/pci constraints

---
 projects/pzsdr2/common/ccfmc_constr.xdc | 274 ++++++++++++++++++++++++
 projects/pzsdr2/common/ccpci_constr.xdc |  30 +++
 2 files changed, 304 insertions(+)
 create mode 100644 projects/pzsdr2/common/ccfmc_constr.xdc
 create mode 100644 projects/pzsdr2/common/ccpci_constr.xdc

diff --git a/projects/pzsdr2/common/ccfmc_constr.xdc b/projects/pzsdr2/common/ccfmc_constr.xdc
new file mode 100644
index 000000000..bec9d8b10
--- /dev/null
+++ b/projects/pzsdr2/common/ccfmc_constr.xdc
@@ -0,0 +1,274 @@
+
+# rf-board
+
+set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable]            ; ## U1,K10,IO_25_34_JX4,JX4,64,RF_GPIO4_BANK34
+set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD LVCMOS25} [get_ports gpio_rf0]                     ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,RF_GPIO0_BANK13
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS25} [get_ports gpio_rf1]                     ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,RF_GPIO1_BANK13
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS25} [get_ports gpio_rf2]                     ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,RF_GPIO2_BANK12
+set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD LVCMOS18} [get_ports gpio_rf3]                     ; ## U1,J9,IO_L05_34_JX4_N,JX4,33,RF_GPIO3_BANK34
+set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD LVCMOS18} [get_ports gpio_rf4]                     ; ## U1,A9,IO_L17_34_JX4_P,JX4,67,RF_GPIO5_BANK34
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD LVCMOS25} [get_ports tdd_sync]                     ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,PMOD0_D5,R105,1
+
+# ethernet-1 (U1,B20,PS_MIO51_501_JX4,JX4,100,ETH1_RESETN)
+
+set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD LVCMOS18} [get_ports eth1_mdc]                     ; ## U1,B10,IO_L16_34_JX4_P,JX4,58,ETH1_MDC         
+set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD LVCMOS18} [get_ports eth1_mdio]                    ; ## U1,A10,IO_L16_34_JX4_N,JX4,60,ETH1_MDIO        
+set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk]             ; ## U1,G7,IO_L12_MRCC_34_JX4_P,JX4,46,ETH1_RX_CLK      
+set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl]             ; ## U1,F7,IO_L12_MRCC_34_JX4_N,JX4,48,ETH1_RX_CTRL     
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]]         ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,ETH1_RXD0        
+set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]]         ; ## U1,D5,IO_L10_34_JX4_N,JX4,44,ETH1_RXD1        
+set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]]         ; ## U1,F8,IO_L11_SRCC_34_JX4_P,JX4,45,ETH1_RXD2        
+set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]]         ; ## U1,E7,IO_L11_SRCC_34_JX4_N,JX4,47,ETH1_RXD3        
+set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk]             ; ## U1,C8,IO_L13_MRCC_34_JX4_P,JX4,51,ETH1_TX_CLK      
+set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl]             ; ## U1,C7,IO_L13_MRCC_34_JX4_N,JX4,53,ETH1_TX_CTRL     
+set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]]         ; ## U1,D6,IO_L14_SRCC_34_JX4_P,JX4,52,ETH1_TXD0        
+set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]]         ; ## U1,C6,IO_L14_SRCC_34_JX4_N,JX4,54,ETH1_TXD1        
+set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]]         ; ## U1,C9,IO_L15_34_JX4_P,JX4,57,ETH1_TXD2        
+set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]]         ; ## U1,B9,IO_L15_34_JX4_N,JX4,59,ETH1_TXD3        
+
+# hdmi
+
+set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD LVCMOS18}             [get_ports hdmi_out_clk]     ; ## U1,L3,IO_L11_SRCC_33_JX1_P,JX1,74,HDMI_CLK         
+set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_vsync]       ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,HDMI_VSYNC       
+set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_hsync]       ; ## U1,D3,IO_L02_33_JX1_N,JX1,43,HDMI_HSYNC       
+set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data_e]      ; ## U1,K3,IO_L11_SRCC_33_JX1_N,JX1,76,HDMI_DE          
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[0]]     ; ## U1,G2,IO_L03_33_JX1_P,JX1,42,HDMI_D20         
+set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[1]]     ; ## U1,F2,IO_L03_33_JX1_N,JX1,44,HDMI_D21         
+set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[2]]     ; ## U1,D1,IO_L04_33_JX1_P,JX1,47,HDMI_D22         
+set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[3]]     ; ## U1,C1,IO_L04_33_JX1_N,JX1,49,HDMI_D23         
+set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[4]]     ; ## U1,E2,IO_L05_33_JX1_P,JX1,54,HDMI_D24         
+set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[5]]     ; ## U1,E1,IO_L05_33_JX1_N,JX1,56,HDMI_D25         
+set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[6]]     ; ## U1,F3,IO_L06_33_JX1_P,JX1,61,HDMI_D26         
+set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[7]]     ; ## U1,E3,IO_L06_33_JX1_N,JX1,63,HDMI_D27         
+set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[8]]     ; ## U1,J1,IO_L07_33_JX1_P,JX1,62,HDMI_D28         
+set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[9]]     ; ## U1,H1,IO_L07_33_JX1_N,JX1,64,HDMI_D29         
+set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[10]]    ; ## U1,H4,IO_L08_33_JX1_P,JX1,67,HDMI_D30         
+set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[11]]    ; ## U1,H3,IO_L08_33_JX1_N,JX1,69,HDMI_D31         
+set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[12]]    ; ## U1,K2,IO_L09_33_JX1_P,JX1,68,HDMI_D32         
+set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[13]]    ; ## U1,K1,IO_L09_33_JX1_N,JX1,70,HDMI_D33         
+set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[14]]    ; ## U1,H2,IO_L10_33_JX1_P,JX1,73,HDMI_D34         
+set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[15]]    ; ## U1,G1,IO_L10_33_JX1_N,JX1,75,HDMI_D35         
+set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD LVCMOS18}             [get_ports hdmi_pd]          ; ## U1,L9,IO_00_33_JX1,JX1,9,HDMI_PD          
+set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD LVCMOS18}             [get_ports hdmi_intn]        ; ## U1,N8,IO_25_33_JX1,JX1,10,HDMI_INTN        
+
+# hdmi-spdif
+
+set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD LVCMOS18} [get_ports spdif]                        ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,HDMI_SPDIF       
+set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD LVCMOS18} [get_ports spdif_in]                     ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,HDMI_SPDIF_OUT   
+
+# audio
+
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD LVCMOS18} [get_ports i2s_mclk]                     ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,I2S_MCLK         
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD LVCMOS18} [get_ports i2s_bclk]                     ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,I2S_BCLK         
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD LVCMOS18} [get_ports i2s_lrclk]                    ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,I2S_LRCLK        
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out]                ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,I2S_SDATA_OUT    
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in]                 ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,I2S_SDATA_IN     
+
+# ad9517
+
+set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD LVCMOS18} [get_ports ad9517_csn]                   ; ## U1,B4,IO_L20_34_JX4_N,JX4,76,PMOD1_D3         
+set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD LVCMOS18} [get_ports ad9517_clk]                   ; ## U1,C4,IO_L19_34_JX4_P,JX4,73,PMOD1_D0         
+set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD LVCMOS18} [get_ports ad9517_mosi]                  ; ## U1,C3,IO_L19_34_JX4_N,JX4,75,PMOD1_D1         
+set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD LVCMOS18} [get_ports ad9517_miso]                  ; ## U1,B5,IO_L20_34_JX4_P,JX4,74,PMOD1_D2         
+set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD LVCMOS18} [get_ports ad9517_pdn]                   ; ## U1,B6,IO_L21_34_JX4_P,JX4,77,PMOD1_D4         
+set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel]               ; ## U1,A5,IO_L21_34_JX4_N,JX4,79,PMOD1_D5         
+set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD LVCMOS18} [get_ports ad9517_ld]                    ; ## U1,A4,IO_L22_34_JX4_P,JX4,78,PMOD1_D6         
+set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD LVCMOS18} [get_ports ad9517_status]                ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,PMOD1_D7         
+
+# clocks
+
+create_clock -period 8.000 -name eth1_rgmii_rxclk [get_ports eth1_rgmii_rxclk]
+
+# bad ip- we have to do this
+
+set_property IDELAY_VALUE 16 \
+  [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \
+  [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}]
+
+set_property IODELAY_GROUP gmii2rgmii_iodelay_group\
+  [get_cells -hier -filter {name =~ *idelayctrl}] \
+  [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \
+  [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}]
+
+# fan control/sense
+
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD LVCMOS18} [get_ports fan_pwm]                      ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,FAN_PWM          
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD LVCMOS18} [get_ports fan_tach]                     ; ## U1,A7,IO_L18_34_JX4_N,JX4,70,FAN_TACH         
+
+## led, push buttons, dip switches
+
+set_property  -dict {PACKAGE_PIN  J3    IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]                   ; ## U1,J3,IO_L12_MRCC_33_JX1_N,JX1,83,PB_GPIO_0        
+set_property  -dict {PACKAGE_PIN  D8    IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]                   ; ## U1,D8,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1        
+set_property  -dict {PACKAGE_PIN  F9    IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]                   ; ## U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2        
+set_property  -dict {PACKAGE_PIN  E8    IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]                   ; ## U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3        
+set_property  -dict {PACKAGE_PIN  A8    IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]]                   ; ## U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0       
+set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]]                   ; ## U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1       
+set_property  -dict {PACKAGE_PIN  W17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]                   ; ## U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2       
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]                   ; ## U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3       
+set_property  -dict {PACKAGE_PIN  Y15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]]                   ; ## U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0       
+set_property  -dict {PACKAGE_PIN  W16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]                   ; ## U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1       
+set_property  -dict {PACKAGE_PIN  W15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]]                  ; ## U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2       
+set_property  -dict {PACKAGE_PIN  V19   IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]                  ; ## U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3       
+
+## orphans (ps7- gpio)
+
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]]                  ; ## U1,V18,IO_25_13_JX2,JX2,14,FMC_PRSNT        
+set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]]                  ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,PMOD0_D1,R103,1
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]]                  ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,SFP_GPIO_0       
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]]                  ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,SFP_GPIO_1       
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]]                  ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,SFP_GPIO_2       
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]]                  ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,SFP_GPIO_3       
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]]                  ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,SFP_GPIO_4       
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[19]]                  ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,SFP_GPIO_5       
+set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[20]]                  ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,SFP_GPIO_6       
+
+# unused io (clocks & gt)
+
+set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p]        ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,FMC_CLK0_M2C_P   
+set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n]        ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,FMC_CLK0_M2C_N   
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p]        ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,FMC_CLK1_M2C_P   
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n]        ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,FMC_CLK1_M2C_N   
+
+set_property  -dict {PACKAGE_PIN  R6}   [get_ports gt_ref_clk_0_p]                                    ; ## U1,R6,UNNAMED_7_CAP_I123_N2,JX1,87,MGTREFCLK0_112_JX1_P
+set_property  -dict {PACKAGE_PIN  R5}   [get_ports gt_ref_clk_0_n]                                    ; ## U1,R5,UNNAMED_7_CAP_I125_N2,JX1,89,MGTREFCLK0_112_JX1_N
+set_property  -dict {PACKAGE_PIN  U6}   [get_ports gt_ref_clk_1_p]                                    ; ## U1,U6,UNNAMED_7_CAP_I126_N2,JX3,2,MGTREFCLK1_112_JX3_P
+set_property  -dict {PACKAGE_PIN  U5}   [get_ports gt_ref_clk_1_n]                                    ; ## U1,U5,UNNAMED_7_CAP_I124_N2,JX3,4,MGTREFCLK1_112_JX3_N
+set_property  -dict {PACKAGE_PIN  AA2}  [get_ports gt_tx_p[0]]                                        ; ## U1,AA2,MGTXTX0_112_JX3_P,JX3,8,FMC_GBT_TX_P,P2,C2
+set_property  -dict {PACKAGE_PIN  AA1}  [get_ports gt_tx_n[0]]                                        ; ## U1,AA1,MGTXTX0_112_JX3_N,JX3,10,FMC_GBT_TX_N,P2,C3
+set_property  -dict {PACKAGE_PIN  AB4}  [get_ports gt_rx_p[0]]                                        ; ## U1,AB4,MGTXRX0_112_JX1_P,JX1,88,FMC_GBT_RX_P,P2,C6
+set_property  -dict {PACKAGE_PIN  AB3}  [get_ports gt_rx_n[0]]                                        ; ## U1,AB3,MGTXRX0_112_JX1_N,JX1,90,FMC_GBT_RX_N,P2,C7
+set_property  -dict {PACKAGE_PIN  AF4}  [get_ports gt_tx_p[1]]                                        ; ## U1,Y4,MGTXRX1_112_JX1_P,JX1,91,SFP_GBT_RX_P,P1,13
+set_property  -dict {PACKAGE_PIN  AF3}  [get_ports gt_tx_n[1]]                                        ; ## U1,Y3,MGTXRX1_112_JX1_N,JX1,93,SFP_GBT_RX_N,P1,12
+set_property  -dict {PACKAGE_PIN  AE6}  [get_ports gt_rx_p[1]]                                        ; ## U1,W2,MGTXTX1_112_JX3_P,JX3,13,SFP_GBT_TX_P,P1,18
+set_property  -dict {PACKAGE_PIN  AE5}  [get_ports gt_rx_n[1]]                                        ; ## U1,W1,MGTXTX1_112_JX3_N,JX3,15,SFP_GBT_TX_N,P1,19
+
+## clocks
+
+create_clock -name ref_clk        -period  4.00 [get_ports gt_ref_clk_0_p]
+create_clock -name xcvr_clk_0     -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+create_clock -name xcvr_clk_1     -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
+
+## loopback (regular io- fmc)
+
+set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVCMOS25} [get_ports gp_out[0]]                    ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,FMC_LA00_CC_P,P2,G6
+set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVCMOS25} [get_ports gp_out[1]]                    ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,FMC_LA00_CC_N,P2,G7
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVCMOS25} [get_ports gp_out[2]]                    ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,FMC_LA01_CC_P,P2,D8
+set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD LVCMOS25} [get_ports gp_out[3]]                    ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,FMC_LA01_CC_N,P2,D9
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD LVCMOS25} [get_ports gp_out[4]]                    ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,FMC_LA02_P,P2,H7
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD LVCMOS25} [get_ports gp_out[5]]                    ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,FMC_LA02_N,P2,H8
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVCMOS25} [get_ports gp_out[6]]                    ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,FMC_LA03_P,P2,G9
+set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD LVCMOS25} [get_ports gp_out[7]]                    ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,FMC_LA03_N,P2,G10
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD LVCMOS25} [get_ports gp_out[8]]                    ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,FMC_LA04_P,P2,H10
+set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD LVCMOS25} [get_ports gp_out[9]]                    ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,FMC_LA04_N,P2,H11
+set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD LVCMOS25} [get_ports gp_out[10]]                   ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,FMC_LA05_P,P2,D11
+set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD LVCMOS25} [get_ports gp_out[11]]                   ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,FMC_LA05_N,P2,D12
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD LVCMOS25} [get_ports gp_out[12]]                   ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,FMC_LA06_P,P2,C10
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD LVCMOS25} [get_ports gp_out[13]]                   ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,FMC_LA06_N,P2,C11
+set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD LVCMOS25} [get_ports gp_out[14]]                   ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,FMC_LA07_P,P2,H13
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS25} [get_ports gp_out[15]]                   ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,FMC_LA07_N,P2,H14
+set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD LVCMOS25} [get_ports gp_out[16]]                   ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,FMC_LA08_P,P2,G12
+set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD LVCMOS25} [get_ports gp_out[17]]                   ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,FMC_LA08_N,P2,G13
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVCMOS25} [get_ports gp_out[18]]                   ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,FMC_LA09_P,P2,D14
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVCMOS25} [get_ports gp_out[19]]                   ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,FMC_LA09_N,P2,D15
+set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD LVCMOS25} [get_ports gp_out[20]]                   ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,FMC_LA10_P,P2,C14
+set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD LVCMOS25} [get_ports gp_out[21]]                   ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,FMC_LA10_N,P2,C15
+set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVCMOS25} [get_ports gp_out[22]]                   ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,FMC_LA11_P,P2,H16
+set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVCMOS25} [get_ports gp_out[23]]                   ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,FMC_LA11_N,P2,H17
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25} [get_ports gp_out[24]]                   ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,FMC_LA12_P,P2,G15
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25} [get_ports gp_out[25]]                   ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,FMC_LA12_N,P2,G16
+set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVCMOS25} [get_ports gp_out[26]]                   ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,FMC_LA13_P,P2,D17
+set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVCMOS25} [get_ports gp_out[27]]                   ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,FMC_LA13_N,P2,D18
+set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVCMOS25} [get_ports gp_out[28]]                   ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,FMC_LA14_P,P2,C18
+set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD LVCMOS25} [get_ports gp_out[29]]                   ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,FMC_LA14_N,P2,C19
+set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVCMOS25} [get_ports gp_out[30]]                   ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,FMC_LA15_P,P2,H19
+set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVCMOS25} [get_ports gp_out[31]]                   ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,FMC_LA15_N,P2,H20
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports gp_out[32]]                   ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,FMC_LA16_P,P2,G18
+set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVCMOS25} [get_ports gp_out[33]]                   ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,FMC_LA16_N,P2,G19
+set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD LVCMOS25} [get_ports gp_in[0]]                     ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,FMC_LA17_CC_P,P2,D20
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD LVCMOS25} [get_ports gp_in[1]]                     ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,FMC_LA17_CC_N,P2,D21
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports gp_in[2]]                     ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,FMC_LA18_CC_P,P2,C22
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVCMOS25} [get_ports gp_in[3]]                     ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,FMC_LA18_CC_N,P2,C23
+set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD LVCMOS25} [get_ports gp_in[4]]                     ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,FMC_LA19_P,P2,H22
+set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD LVCMOS25} [get_ports gp_in[5]]                     ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,FMC_LA19_N,P2,H23
+set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD LVCMOS25} [get_ports gp_in[6]]                     ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,FMC_LA20_P,P2,G21
+set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD LVCMOS25} [get_ports gp_in[7]]                     ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,FMC_LA20_N,P2,G22
+set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVCMOS25} [get_ports gp_in[8]]                     ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,FMC_LA21_P,P2,H25
+set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVCMOS25} [get_ports gp_in[9]]                     ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,FMC_LA21_N,P2,H26
+set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVCMOS25} [get_ports gp_in[10]]                    ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,FMC_LA22_P,P2,G24
+set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD LVCMOS25} [get_ports gp_in[11]]                    ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,FMC_LA22_N,P2,G25
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25} [get_ports gp_in[12]]                    ; ## U1,AA24,IO_L06_13_JX2_P,JX2,18,FMC_LA23_P,P2,D23
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25} [get_ports gp_in[13]]                    ; ## U1,AB24,IO_L06_13_JX2_N,JX2,20,FMC_LA23_N,P2,D24
+set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD LVCMOS25} [get_ports gp_in[14]]                    ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,FMC_LA24_P,P2,H28
+set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD LVCMOS25} [get_ports gp_in[15]]                    ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,FMC_LA24_N,P2,H29
+set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports gp_in[16]]                    ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,FMC_LA25_P,P2,G27
+set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports gp_in[17]]                    ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,FMC_LA25_N,P2,G28
+set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD LVCMOS25} [get_ports gp_in[18]]                    ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,FMC_LA26_P,P2,D26
+set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD LVCMOS25} [get_ports gp_in[19]]                    ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,FMC_LA26_N,P2,D27
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports gp_in[20]]                    ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,FMC_LA27_P,P2,C26
+set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports gp_in[21]]                    ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,FMC_LA27_N,P2,C27
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD LVCMOS25} [get_ports gp_in[22]]                    ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,FMC_LA28_P,P2,H31
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS25} [get_ports gp_in[23]]                    ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,FMC_LA28_N,P2,H32
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports gp_in[24]]                    ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,FMC_LA29_P,P2,G30
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVCMOS25} [get_ports gp_in[25]]                    ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,FMC_LA29_N,P2,G31
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD LVCMOS25} [get_ports gp_in[26]]                    ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,FMC_LA30_P,P2,H34
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports gp_in[27]]                    ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,FMC_LA30_N,P2,H35
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD LVCMOS25} [get_ports gp_in[28]]                    ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,FMC_LA31_P,P2,G33
+set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD LVCMOS25} [get_ports gp_in[29]]                    ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,FMC_LA31_N,P2,G34
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports gp_in[30]]                    ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,FMC_LA32_P,P2,H37
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVCMOS25} [get_ports gp_in[31]]                    ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,FMC_LA32_N,P2,H38
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports gp_in[32]]                    ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,FMC_LA33_P,P2,G36
+set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD LVCMOS25} [get_ports gp_in[33]]                    ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,FMC_LA33_N,P2,G37
+
+## loopback (regular io- pmod)
+## U1,C24,PS_MIO15_500_JX4,JX4,85,PMOD_MIO_D0      
+## U1,A25,PS_MIO10_500_JX4,JX4,87,PMOD_MIO_D1      
+## U1,B26,PS_MIO11_500_JX4,JX4,88,PMOD_MIO_D3      
+## U1,B25,PS_MIO13_500_JX4,JX4,91,PMOD_MIO_D4      
+## U1,D23,PS_MIO14_500_JX4,JX4,93,PMOD_MIO_D5      
+## U1,E17,PS_MIO46_501_JX4,JX4,92,PMOD_MIO_D6      
+## U1,B19,PS_MIO47_501_JX4,JX4,94,PMOD_MIO_D7      
+
+set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD LVCMOS25} [get_ports gp_out[34]]                   ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,PMOD0_D0,R95,1
+set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD LVCMOS25} [get_ports gp_out[35]]                   ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,PMOD0_D2,R96,1
+set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD LVCMOS25} [get_ports gp_out[36]]                   ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,PMOD0_D3,R104,1
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS25} [get_ports gp_in[34]]                    ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,PMOD0_D4,R97,1
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD LVCMOS25} [get_ports gp_in[35]]                    ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,PMOD0_D6,R98,1
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD LVCMOS25} [get_ports gp_in[36]]                    ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,PMOD0_D7,R106,1
+
+## loopback (regular io- camera)
+
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports gp_out[37]]                   ; ## U1,G6,IO_L02_34_JX4_P,JX4,20,CAM_GPIO_2,P9,B23
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports gp_out[38]]                   ; ## U1,G5,IO_L02_34_JX4_N,JX4,22,CAM_GPIO_3,P9,B24
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports gp_out[39]]                   ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,CAM_GPIO_6,P9,B27
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD LVCMOS18} [get_ports gp_out[40]]                   ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,CAM_GPIO_7,P9,B29
+set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD LVCMOS18} [get_ports gp_out[41]]                   ; ## U1,N3,IO_L15_33_JX1_P,JX1,53,CAM_DATA0_P,P9,A7
+set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD LVCMOS18} [get_ports gp_out[42]]                   ; ## U1,N2,IO_L15_33_JX1_N,JX1,55,CAM_DATA0_N,P9,A8
+set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD LVCMOS18} [get_ports gp_out[43]]                   ; ## U1,N4,IO_L17_33_JX1_P,JX1,12,CAM_DATA2_P,P9,A13
+set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD LVCMOS18} [get_ports gp_out[44]]                   ; ## U1,M4,IO_L17_33_JX1_N,JX1,14,CAM_DATA2_N,P9,A14
+set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD LVCMOS18} [get_ports gp_out[45]]                   ; ## U1,M7,IO_L19_33_JX1_P,JX1,18,CAM_DATA4_P,P9,A19
+set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD LVCMOS18} [get_ports gp_out[46]]                   ; ## U1,L7,IO_L19_33_JX1_N,JX1,20,CAM_DATA4_N,P9,A20
+set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD LVCMOS18} [get_ports gp_out[47]]                   ; ## U1,M8,IO_L21_33_JX1_P,JX1,24,CAM_DATA6_P,P9,A25
+set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD LVCMOS18} [get_ports gp_out[48]]                   ; ## U1,L8,IO_L21_33_JX1_N,JX1,26,CAM_DATA6_N,P9,A26
+set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD LVCMOS18} [get_ports gp_out[49]]                   ; ## U1,L5,IO_L14_SRCC_33_JX1_P,JX1,48,CAM_SYNC_P,P9,A31
+set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD LVCMOS18} [get_ports gp_out[50]]                   ; ## U1,L4,IO_L14_SRCC_33_JX1_N,JX1,50,CAM_SYNC_N,P9,A32
+set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD LVCMOS18} [get_ports gp_out[51]]                   ; ## U1,K8,IO_L24_33_JX1_P,JX1,36,CAM_SPI_MISO,P9,B15
+set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD LVCMOS18} [get_ports gp_out[52]]                   ; ## U1,K7,IO_L24_33_JX1_N,JX1,38,CAM_SPI_MOSI,P9,B18
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports gp_out[53]]                   ; ## U1,J10,IO_L05_34_JX4_P,JX4,31,CAM_GPIO_8,P9,B30
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports gp_in[37]]                    ; ## U1,J11,IO_L01_34_JX4_P,JX4,19,CAM_GPIO_0,P9,B20
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports gp_in[38]]                    ; ## U1,H11,IO_L01_34_JX4_N,JX4,21,CAM_GPIO_1,P9,B21
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports gp_in[39]]                    ; ## U1,H9,IO_L03_34_JX4_P,JX4,25,CAM_GPIO_4,P9,B25
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports gp_in[40]]                    ; ## U1,G9,IO_L03_34_JX4_N,JX4,27,CAM_GPIO_5,P9,B26
+set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD LVCMOS18} [get_ports gp_in[41]]                    ; ## U1,M6,IO_L13_MRCC_33_JX1_P,JX1,82,CAM_CLK_P,P9,A4
+set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD LVCMOS18} [get_ports gp_in[42]]                    ; ## U1,M5,IO_L13_MRCC_33_JX1_N,JX1,84,CAM_CLK_N,P9,A5
+set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD LVCMOS18} [get_ports gp_in[43]]                    ; ## U1,M2,IO_L16_33_JX1_P,JX1,11,CAM_DATA1_P,P9,A10
+set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD LVCMOS18} [get_ports gp_in[44]]                    ; ## U1,L2,IO_L16_33_JX1_N,JX1,13,CAM_DATA1_N,P9,A11
+set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD LVCMOS18} [get_ports gp_in[45]]                    ; ## U1,N1,IO_L18_33_JX1_P,JX1,17,CAM_DATA3_P,P9,A16
+set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD LVCMOS18} [get_ports gp_in[46]]                    ; ## U1,M1,IO_L18_33_JX1_N,JX1,19,CAM_DATA3_N,P9,A17
+set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD LVCMOS18} [get_ports gp_in[47]]                    ; ## U1,K5,IO_L20_33_JX1_P,JX1,23,CAM_DATA5_P,P9,A22
+set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD LVCMOS18} [get_ports gp_in[48]]                    ; ## U1,J5,IO_L20_33_JX1_N,JX1,25,CAM_DATA5_N,P9,A23
+set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD LVCMOS18} [get_ports gp_in[49]]                    ; ## U1,K6,IO_L22_33_JX1_P,JX1,29,CAM_DATA7_P,P9,A28
+set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD LVCMOS18} [get_ports gp_in[50]]                    ; ## U1,J6,IO_L22_33_JX1_N,JX1,31,CAM_DATA7_N,P9,A29
+set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD LVCMOS18} [get_ports gp_in[51]]                    ; ## U1,N7,IO_L23_33_JX1_P,JX1,30,CAM_SPI_EN,P9,B14
+set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD LVCMOS18} [get_ports gp_in[52]]                    ; ## U1,N6,IO_L23_33_JX1_N,JX1,32,CAM_SPI_CLK,P9,B12
+set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD LVCMOS18} [get_ports gp_in[53]]                    ; ## U1,J4,IO_L12_MRCC_33_JX1_P,JX1,81,CAM_REFCLK,P9,A2
+                                                                                                                                    
diff --git a/projects/pzsdr2/common/ccpci_constr.xdc b/projects/pzsdr2/common/ccpci_constr.xdc
new file mode 100644
index 000000000..759e97b9e
--- /dev/null
+++ b/projects/pzsdr2/common/ccpci_constr.xdc
@@ -0,0 +1,30 @@
+
+# constraints (ccpci.b)
+# reference-only & not-effective
+# using axi_pcie_x0y0.xdc
+
+set_property  -dict {PACKAGE_PIN  U6 }  [get_ports pcie_ref_clk_p]                                      ; ## U1,U6,UNNAMED_7_CAP_I126_N2,JX3,2,MGTREFCLK1_112_JX3_P,P2,A13
+set_property  -dict {PACKAGE_PIN  U5 }  [get_ports pcie_ref_clk_n]                                      ; ## U1,U5,UNNAMED_7_CAP_I124_N2,JX3,4,MGTREFCLK1_112_JX3_N,P2,A14
+set_property  -dict {PACKAGE_PIN  T4 }  [get_ports pcie_data_rx_p[0]]                                   ; ## U1,T4,MGTXRX3_112_JX1_P,JX1,97,MGTXRX3_112_JX1_P,P2,B14
+set_property  -dict {PACKAGE_PIN  T3 }  [get_ports pcie_data_rx_n[0]]                                   ; ## U1,T3,MGTXRX3_112_JX1_N,JX1,99,MGTXRX3_112_JX1_N,P2,B15
+set_property  -dict {PACKAGE_PIN  V4 }  [get_ports pcie_data_rx_p[1]]                                   ; ## U1,V4,MGTXRX2_112_JX1_P,JX1,92,MGTXRX2_112_JX1_P,P2,B19
+set_property  -dict {PACKAGE_PIN  V3 }  [get_ports pcie_data_rx_n[1]]                                   ; ## U1,V3,MGTXRX2_112_JX1_N,JX1,94,MGTXRX2_112_JX1_N,P2,B20
+set_property  -dict {PACKAGE_PIN  Y4 }  [get_ports pcie_data_rx_p[2]]                                   ; ## U1,Y4,MGTXRX1_112_JX1_P,JX1,91,MGTXRX1_112_JX1_P,P2,B23
+set_property  -dict {PACKAGE_PIN  Y3 }  [get_ports pcie_data_rx_n[2]]                                   ; ## U1,Y3,MGTXRX1_112_JX1_N,JX1,93,MGTXRX1_112_JX1_N,P2,B24
+set_property  -dict {PACKAGE_PIN  AB4}  [get_ports pcie_data_rx_p[3]]                                   ; ## U1,AB4,MGTXRX0_112_JX1_P,JX1,88,MGTXRX0_112_JX1_P,P2,B27
+set_property  -dict {PACKAGE_PIN  AB3}  [get_ports pcie_data_rx_n[3]]                                   ; ## U1,AB3,MGTXRX0_112_JX1_N,JX1,90,MGTXRX0_112_JX1_N,P2,B28
+set_property  -dict {PACKAGE_PIN  R2 }  [get_ports pcie_data_tx_p[0]]                                   ; ## U1,R2,MGTXTX3_112_JX3_P,JX3,19,MGTXTX3_112_JX3_P,P2,A16
+set_property  -dict {PACKAGE_PIN  R1 }  [get_ports pcie_data_tx_n[0]]                                   ; ## U1,R1,MGTXTX3_112_JX3_N,JX3,21,MGTXTX3_112_JX3_N,P2,A17
+set_property  -dict {PACKAGE_PIN  U2 }  [get_ports pcie_data_tx_p[1]]                                   ; ## U1,U2,MGTXTX2_112_JX3_P,JX3,14,MGTXTX2_112_JX3_P,P2,A21
+set_property  -dict {PACKAGE_PIN  U1 }  [get_ports pcie_data_tx_n[1]]                                   ; ## U1,U1,MGTXTX2_112_JX3_N,JX3,16,MGTXTX2_112_JX3_N,P2,A22
+set_property  -dict {PACKAGE_PIN  W2 }  [get_ports pcie_data_tx_p[2]]                                   ; ## U1,W2,MGTXTX1_112_JX3_P,JX3,13,MGTXTX1_112_JX3_P,P2,A25
+set_property  -dict {PACKAGE_PIN  W1 }  [get_ports pcie_data_tx_n[2]]                                   ; ## U1,W1,MGTXTX1_112_JX3_N,JX3,15,MGTXTX1_112_JX3_N,P2,A26
+set_property  -dict {PACKAGE_PIN  AA2}  [get_ports pcie_data_tx_p[3]]                                   ; ## U1,AA2,MGTXTX0_112_JX3_P,JX3,8,MGTXTX0_112_JX3_P,P2,A29
+set_property  -dict {PACKAGE_PIN  AA1}  [get_ports pcie_data_tx_n[3]]                                   ; ## U1,AA1,MGTXTX0_112_JX3_N,JX3,10,MGTXTX0_112_JX3_N,P2,A30
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS18} [get_ports pcie_rstn]                      ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,PCIE_PRSNT,P2,A11
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS18} [get_ports pcie_waken]                     ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,PCIE_WAKEB,P2,B11
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS18} [get_ports pcie_rstn_good]                 ; ## IO_L22N_T3_12, NOT-CONNECTED ????
+
+set_property PULLUP true [get_ports pcie_rstn]
+create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p]
+

From fb5d36b250353f9b268b148cc34c0e1c9d3833f9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 16 Nov 2016 16:27:05 -0500
Subject: [PATCH 713/972] pzsdr2- update ccfmc

---
 projects/pzsdr2/ccbrk_cmos/system_bd.tcl      |  19 +-
 projects/pzsdr2/ccbrk_lvds/system_bd.tcl      |  31 +--
 projects/pzsdr2/ccfmc_lvds/Makefile           |  18 +-
 projects/pzsdr2/ccfmc_lvds/system_bd.tcl      |   4 +-
 projects/pzsdr2/ccfmc_lvds/system_constr.xdc  | 247 ------------------
 projects/pzsdr2/ccfmc_lvds/system_project.tcl |  16 +-
 projects/pzsdr2/ccfmc_lvds/system_top.v       |  80 ++----
 projects/pzsdr2/ccpci_lvds/Makefile           |  17 +-
 projects/pzsdr2/ccpci_lvds/system_bd.tcl      |  36 ++-
 projects/pzsdr2/ccpci_lvds/system_project.tcl |  20 +-
 projects/pzsdr2/common/ccbrk_constr.xdc       | 196 +++++++-------
 projects/pzsdr2/common/ccfmc_bd.tcl           |  26 +-
 projects/pzsdr2/common/pzsdr2_bd.tcl          |  62 +++++
 projects/pzsdr2/common/pzsdr2_constr.xdc      |   4 +-
 14 files changed, 262 insertions(+), 514 deletions(-)
 delete mode 100644 projects/pzsdr2/ccfmc_lvds/system_constr.xdc

diff --git a/projects/pzsdr2/ccbrk_cmos/system_bd.tcl b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
index 6c6c3d30d..de8969baf 100644
--- a/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
+++ b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
@@ -2,22 +2,5 @@
 source ../common/pzsdr2_bd.tcl
 source ../common/ccbrk_bd.tcl
 
-## core digital interface -- cmos (1) or lvds (0)
-
-set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
-
-create_bd_port -dir I rx_clk_in
-create_bd_port -dir I rx_frame_in
-create_bd_port -dir I -from 11 -to 0 rx_data_in
-create_bd_port -dir O tx_clk_out
-create_bd_port -dir O tx_frame_out
-create_bd_port -dir O -from 11 -to 0 tx_data_out
-
-
-ad_connect  rx_clk_in axi_ad9361/rx_clk_in
-ad_connect  rx_frame_in axi_ad9361/rx_frame_in
-ad_connect  rx_data_in axi_ad9361/rx_data_in
-ad_connect  tx_clk_out axi_ad9361/tx_clk_out
-ad_connect  tx_frame_out axi_ad9361/tx_frame_out
-ad_connect  tx_data_out axi_ad9361/tx_data_out
+cfg_ad9361_interface CMOS
 
diff --git a/projects/pzsdr2/ccbrk_lvds/system_bd.tcl b/projects/pzsdr2/ccbrk_lvds/system_bd.tcl
index 030c6a762..3c050c45d 100644
--- a/projects/pzsdr2/ccbrk_lvds/system_bd.tcl
+++ b/projects/pzsdr2/ccbrk_lvds/system_bd.tcl
@@ -2,34 +2,5 @@
 source ../common/pzsdr2_bd.tcl
 source ../common/ccbrk_bd.tcl
 
-## core digital interface -- cmos (1) or lvds (0)
-
-set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
-
-create_bd_port -dir I rx_clk_in_p
-create_bd_port -dir I rx_clk_in_n
-create_bd_port -dir I rx_frame_in_p
-create_bd_port -dir I rx_frame_in_n
-create_bd_port -dir I -from 5 -to 0 rx_data_in_p
-create_bd_port -dir I -from 5 -to 0 rx_data_in_n
-
-create_bd_port -dir O tx_clk_out_p
-create_bd_port -dir O tx_clk_out_n
-create_bd_port -dir O tx_frame_out_p
-create_bd_port -dir O tx_frame_out_n
-create_bd_port -dir O -from 5 -to 0 tx_data_out_p
-create_bd_port -dir O -from 5 -to 0 tx_data_out_n
-
-ad_connect  rx_clk_in_p axi_ad9361/rx_clk_in_p
-ad_connect  rx_clk_in_n axi_ad9361/rx_clk_in_n
-ad_connect  rx_frame_in_p axi_ad9361/rx_frame_in_p
-ad_connect  rx_frame_in_n axi_ad9361/rx_frame_in_n
-ad_connect  rx_data_in_p axi_ad9361/rx_data_in_p
-ad_connect  rx_data_in_n axi_ad9361/rx_data_in_n
-ad_connect  tx_clk_out_p axi_ad9361/tx_clk_out_p
-ad_connect  tx_clk_out_n axi_ad9361/tx_clk_out_n
-ad_connect  tx_frame_out_p axi_ad9361/tx_frame_out_p
-ad_connect  tx_frame_out_n axi_ad9361/tx_frame_out_n
-ad_connect  tx_data_out_p axi_ad9361/tx_data_out_p
-ad_connect  tx_data_out_n axi_ad9361/tx_data_out_n
+cfg_ad9361_interface LVDS
 
diff --git a/projects/pzsdr2/ccfmc_lvds/Makefile b/projects/pzsdr2/ccfmc_lvds/Makefile
index 493f28e4e..4c251d062 100644
--- a/projects/pzsdr2/ccfmc_lvds/Makefile
+++ b/projects/pzsdr2/ccfmc_lvds/Makefile
@@ -7,19 +7,15 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr2_constr_lvds.xdc
+M_DEPS += ../common/pzsdr2_constr.xdc
+M_DEPS += ../common/pzsdr2_bd.tcl
+M_DEPS += ../common/ccfmc_constr.xdc
 M_DEPS += ../common/ccfmc_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
@@ -53,7 +49,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccfmc_lvds_pzsdr.sdk/system_top.hdf
+all: lib pzsdr2_ccfmc_lvds.sdk/system_top.hdf
 
 
 clean: 
@@ -75,9 +71,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccfmc_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+pzsdr2_ccfmc_lvds.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccfmc_lvds_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr2_ccfmc_lvds_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr2/ccfmc_lvds/system_bd.tcl b/projects/pzsdr2/ccfmc_lvds/system_bd.tcl
index c71d9cd75..536e84f12 100644
--- a/projects/pzsdr2/ccfmc_lvds/system_bd.tcl
+++ b/projects/pzsdr2/ccfmc_lvds/system_bd.tcl
@@ -1,4 +1,6 @@
 
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/pzsdr2_bd.tcl
 source ../common/ccfmc_bd.tcl
 
+cfg_ad9361_interface LVDS
+
diff --git a/projects/pzsdr2/ccfmc_lvds/system_constr.xdc b/projects/pzsdr2/ccfmc_lvds/system_constr.xdc
deleted file mode 100644
index eb0702fb3..000000000
--- a/projects/pzsdr2/ccfmc_lvds/system_constr.xdc
+++ /dev/null
@@ -1,247 +0,0 @@
-
-# rf-board
-
-set_property  -dict {PACKAGE_PIN  K10  IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable]             ; ## IO_25_VRP_34
-set_property  -dict {PACKAGE_PIN  AA20 IOSTANDARD LVCMOS25} [get_ports gpio_rf0]                      ; ## IO_L20_13_JX2_P
-set_property  -dict {PACKAGE_PIN  AB20 IOSTANDARD LVCMOS25} [get_ports gpio_rf1]                      ; ## IO_L20_13_JX2_N
-set_property  -dict {PACKAGE_PIN  AA14 IOSTANDARD LVCMOS25} [get_ports gpio_rf2]                      ; ## IO_L22_12_JX2_N
-set_property  -dict {PACKAGE_PIN  J9   IOSTANDARD LVCMOS18} [get_ports gpio_rf3]                      ; ## IO_L05_34_JX4_N
-
-# ethernet-1
-
-set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD LVCMOS18} [get_ports eth1_mdc]                     ; ## IO_L16P_T2_34      
-set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD LVCMOS18} [get_ports eth1_mdio]                    ; ## IO_L16N_T2_34      
-set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk]             ; ## IO_L12P_T1_MRCC_34 
-set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl]             ; ## IO_L12N_T1_MRCC_34 
-set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]]         ; ## IO_L10P_T1_34      
-set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]]         ; ## IO_L10N_T1_34      
-set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]]         ; ## IO_L11P_T1_SRCC_34 
-set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]]         ; ## IO_L11N_T1_SRCC_34 
-set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk]             ; ## IO_L13P_T2_MRCC_34 
-set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl]             ; ## IO_L13N_T2_MRCC_34 
-set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]]         ; ## IO_L14P_T2_SRCC_34 
-set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]]         ; ## IO_L14N_T2_SRCC_34 
-set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]]         ; ## IO_L15P_T2_DQS_34  
-set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]]         ; ## IO_L15N_T2_DQS_34  
-
-# hdmi
-
-set_property  -dict {PACKAGE_PIN  L3    IOSTANDARD LVCMOS18}             [get_ports hdmi_out_clk]     ; ## IO_L11P_T1_SRCC_33       
-set_property  -dict {PACKAGE_PIN  D4    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_vsync]       ; ## IO_L2P_T0_33             
-set_property  -dict {PACKAGE_PIN  D3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_hsync]       ; ## IO_L2N_T0_33             
-set_property  -dict {PACKAGE_PIN  K3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data_e]      ; ## IO_L11N_T1_SRCC_33       
-set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[0]]     ; ## IO_L3P_T0_DQS_33         
-set_property  -dict {PACKAGE_PIN  F2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[1]]     ; ## IO_L3N_T0_DQS_33         
-set_property  -dict {PACKAGE_PIN  D1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[2]]     ; ## IO_L4P_T0_33             
-set_property  -dict {PACKAGE_PIN  C1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[3]]     ; ## IO_L4N_T0_33             
-set_property  -dict {PACKAGE_PIN  E2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[4]]     ; ## IO_L5P_T0_33             
-set_property  -dict {PACKAGE_PIN  E1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[5]]     ; ## IO_L5N_T0_33             
-set_property  -dict {PACKAGE_PIN  F3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[6]]     ; ## IO_L6P_T0_33             
-set_property  -dict {PACKAGE_PIN  E3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[7]]     ; ## IO_L6N_T0_VREF_33        
-set_property  -dict {PACKAGE_PIN  J1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[8]]     ; ## IO_L7P_T1_33             
-set_property  -dict {PACKAGE_PIN  H1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[9]]     ; ## IO_L7N_T1_33             
-set_property  -dict {PACKAGE_PIN  H4    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[10]]    ; ## IO_L8P_T1_33             
-set_property  -dict {PACKAGE_PIN  H3    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[11]]    ; ## IO_L8N_T1_33             
-set_property  -dict {PACKAGE_PIN  K2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[12]]    ; ## IO_L9P_T1_DQS_33         
-set_property  -dict {PACKAGE_PIN  K1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[13]]    ; ## IO_L9N_T1_DQS_33         
-set_property  -dict {PACKAGE_PIN  H2    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[14]]    ; ## IO_L10P_T1_33            
-set_property  -dict {PACKAGE_PIN  G1    IOSTANDARD LVCMOS18    IOB TRUE} [get_ports hdmi_data[15]]    ; ## IO_L10N_T1_33 
-set_property  -dict {PACKAGE_PIN  L9    IOSTANDARD LVCMOS18}             [get_ports hdmi_pd]          ; ## IO_0_VRN_33              
-set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD LVCMOS18}             [get_ports hdmi_intn]        ; ## IO_25_VRP_33             
-
-# hdmi-spdif
-
-set_property  -dict {PACKAGE_PIN  G4    IOSTANDARD LVCMOS18} [get_ports spdif]                        ; ## IO_L1P_T0_33             
-set_property  -dict {PACKAGE_PIN  F4    IOSTANDARD LVCMOS18} [get_ports spdif_in]                     ; ## IO_L1N_T0_33             
-
-# audio
-
-set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD LVCMOS18} [get_ports i2s_mclk]                     ; ## IO_L6P_T0_34             
-set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD LVCMOS18} [get_ports i2s_bclk]                     ; ## IO_L6N_T0_VREF_34        
-set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD LVCMOS18} [get_ports i2s_lrclk]                    ; ## IO_L7P_T1_34             
-set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out]                ; ## IO_L7N_T1_34             
-set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in]                 ; ## IO_L8P_T1_34             
-
-# ad9517
-
-set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD LVCMOS18} [get_ports ad9517_csn]                   ; ## IO_L20N_T3_34             
-set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD LVCMOS18} [get_ports ad9517_clk]                   ; ## IO_L19P_T3_34             
-set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD LVCMOS18} [get_ports ad9517_mosi]                  ; ## IO_L19N_T3_VREF_34        
-set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD LVCMOS18} [get_ports ad9517_miso]                  ; ## IO_L20P_T3_34             
-set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD LVCMOS18} [get_ports ad9517_pdn]                   ; ## IO_L21P_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel]               ; ## IO_L21N_T3_DQS_34         
-set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD LVCMOS18} [get_ports ad9517_ld]                    ; ## IO_L22P_T3_34             
-set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD LVCMOS18} [get_ports ad9517_status]                ; ## IO_L22N_T3_34             
-
-# clocks
-
-create_clock -period 8.000 -name eth1_rgmii_rxclk [get_ports eth1_rgmii_rxclk]
-
-# bad ip- we have to do this
-
-set_property IDELAY_VALUE 16 \
-  [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \
-  [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}]
-
-set_property IODELAY_GROUP gmii2rgmii_iodelay_group\
-  [get_cells -hier -filter {name =~ *idelayctrl}] \
-  [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \
-  [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}]
-
-# fan control/sense
-
-set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD LVCMOS18} [get_ports fan_pwm]                      ; ## IO_L18P_T2_34
-set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD LVCMOS18} [get_ports fan_tach]                     ; ## IO_L18N_T2_34
-
-# unused io (gpio/gt)
-
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p]        ; ## IO_L13P_T2_MRCC_12       (fmc_clk0_p)
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n]        ; ## IO_L13N_T2_MRCC_12       (fmc_clk0_n)
-set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p]        ; ## IO_L13P_T2_MRCC_13       (fmc_clk1_p)
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n]        ; ## IO_L13N_T2_MRCC_13       (fmc_clk1_n)
-
-set_property  -dict {PACKAGE_PIN  W6}   [get_ports gt_ref_clk_p]                                      ; ## MGTREFCLK0P_111          (fmc_gt_ref_clk_p)         
-set_property  -dict {PACKAGE_PIN  W5}   [get_ports gt_ref_clk_n]                                      ; ## MGTREFCLK0N_111          (fmc_gt_ref_clk_n)         
-set_property  -dict {PACKAGE_PIN  AF8}  [get_ports gt_tx_p[0]]                                        ; ## MGTXTXP0_111             (fmc_gt_tx_p)              
-set_property  -dict {PACKAGE_PIN  AF7}  [get_ports gt_tx_n[0]]                                        ; ## MGTXTXN0_111             (fmc_gt_tx_n)              
-set_property  -dict {PACKAGE_PIN  AD8}  [get_ports gt_rx_p[0]]                                        ; ## MGTXRXP0_111             (fmc_gt_rx_p)              
-set_property  -dict {PACKAGE_PIN  AD7}  [get_ports gt_rx_n[0]]                                        ; ## MGTXRXN0_111             (fmc_gt_rx_n)              
-
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD LVCMOS25} [get_ports gp_in_0]                      ; ## IO_25_13                 (fmc_prstn)
-
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVCMOS25} [get_ports gp_out[0]]                    ; ## IO_L12P_T1_MRCC_12       (fmc_la_p[ 0])  
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVCMOS25} [get_ports gp_out[1]]                    ; ## IO_L12N_T1_MRCC_12       (fmc_la_n[ 0])  
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVCMOS25} [get_ports gp_out[2]]                    ; ## IO_L11P_T1_SRCC_12       (fmc_la_p[ 1])  
-set_property  -dict {PACKAGE_PIN  AD11  IOSTANDARD LVCMOS25} [get_ports gp_out[3]]                    ; ## IO_L11N_T1_SRCC_12       (fmc_la_n[ 1])  
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD LVCMOS25} [get_ports gp_out[4]]                    ; ## IO_L1P_T0_12             (fmc_la_p[ 2])  
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD LVCMOS25} [get_ports gp_out[5]]                    ; ## IO_L1N_T0_12             (fmc_la_n[ 2])  
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVCMOS25} [get_ports gp_out[6]]                    ; ## IO_L2P_T0_12             (fmc_la_p[ 3])  
-set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD LVCMOS25} [get_ports gp_out[7]]                    ; ## IO_L2N_T0_12             (fmc_la_n[ 3])  
-set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD LVCMOS25} [get_ports gp_out[8]]                    ; ## IO_L3P_T0_DQS_12         (fmc_la_p[ 4])  
-set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD LVCMOS25} [get_ports gp_out[9]]                    ; ## IO_L3N_T0_DQS_12         (fmc_la_n[ 4])  
-set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD LVCMOS25} [get_ports gp_out[10]]                   ; ## IO_L4P_T0_12             (fmc_la_p[ 5])  
-set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD LVCMOS25} [get_ports gp_out[11]]                   ; ## IO_L4N_T0_12             (fmc_la_n[ 5])  
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD LVCMOS25} [get_ports gp_out[12]]                   ; ## IO_L5P_T0_12             (fmc_la_p[ 6])  
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD LVCMOS25} [get_ports gp_out[13]]                   ; ## IO_L5N_T0_12             (fmc_la_n[ 6])  
-set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD LVCMOS25} [get_ports gp_out[14]]                   ; ## IO_L6P_T0_12             (fmc_la_p[ 7])  
-set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS25} [get_ports gp_out[15]]                   ; ## IO_L6N_T0_VREF_12        (fmc_la_n[ 7])  
-set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD LVCMOS25} [get_ports gp_out[16]]                   ; ## IO_L7P_T1_12             (fmc_la_p[ 8])  
-set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD LVCMOS25} [get_ports gp_out[17]]                   ; ## IO_L7N_T1_12             (fmc_la_n[ 8])  
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVCMOS25} [get_ports gp_out[18]]                   ; ## IO_L8P_T1_12             (fmc_la_p[ 9])  
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVCMOS25} [get_ports gp_out[19]]                   ; ## IO_L8N_T1_12             (fmc_la_n[ 9])  
-set_property  -dict {PACKAGE_PIN  AE11  IOSTANDARD LVCMOS25} [get_ports gp_out[20]]                   ; ## IO_L9P_T1_DQS_12         (fmc_la_p[10])  
-set_property  -dict {PACKAGE_PIN  AF10  IOSTANDARD LVCMOS25} [get_ports gp_out[21]]                   ; ## IO_L9N_T1_DQS_12         (fmc_la_n[10])  
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVCMOS25} [get_ports gp_out[22]]                   ; ## IO_L10P_T1_12            (fmc_la_p[11])  
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVCMOS25} [get_ports gp_out[23]]                   ; ## IO_L10N_T1_12            (fmc_la_n[11])  
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25} [get_ports gp_out[24]]                   ; ## IO_L14P_T2_SRCC_12       (fmc_la_p[12])  
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25} [get_ports gp_out[25]]                   ; ## IO_L14N_T2_SRCC_12       (fmc_la_n[12])  
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVCMOS25} [get_ports gp_out[26]]                   ; ## IO_L15P_T2_DQS_12        (fmc_la_p[13])  
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVCMOS25} [get_ports gp_out[27]]                   ; ## IO_L15N_T2_DQS_12        (fmc_la_n[13])  
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVCMOS25} [get_ports gp_out[28]]                   ; ## IO_L16P_T2_12            (fmc_la_p[14])  
-set_property  -dict {PACKAGE_PIN  AF14  IOSTANDARD LVCMOS25} [get_ports gp_out[29]]                   ; ## IO_L16N_T2_12            (fmc_la_n[14])  
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVCMOS25} [get_ports gp_out[30]]                   ; ## IO_L17P_T2_12            (fmc_la_p[15])  
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVCMOS25} [get_ports gp_out[31]]                   ; ## IO_L17N_T2_12            (fmc_la_n[15])  
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25} [get_ports gp_out[32]]                   ; ## IO_L18P_T2_12            (fmc_la_p[16])  
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVCMOS25} [get_ports gp_out[33]]                   ; ## IO_L18N_T2_12            (fmc_la_n[16])  
-
-set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD LVCMOS25} [get_ports gp_in[0]]                     ; ## IO_L12P_T1_MRCC_13       (fmc_la_p[17])
-set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD LVCMOS25} [get_ports gp_in[1]]                     ; ## IO_L12N_T1_MRCC_13       (fmc_la_n[17])
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS25} [get_ports gp_in[2]]                     ; ## IO_L11P_T1_SRCC_13       (fmc_la_p[18])
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVCMOS25} [get_ports gp_in[3]]                     ; ## IO_L11N_T1_SRCC_13       (fmc_la_n[18])
-set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD LVCMOS25} [get_ports gp_in[4]]                     ; ## IO_L1P_T0_13             (fmc_la_p[19])
-set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD LVCMOS25} [get_ports gp_in[5]]                     ; ## IO_L1N_T0_13             (fmc_la_n[19])
-set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD LVCMOS25} [get_ports gp_in[6]]                     ; ## IO_L2P_T0_13             (fmc_la_p[20])
-set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD LVCMOS25} [get_ports gp_in[7]]                     ; ## IO_L2N_T0_13             (fmc_la_n[20])
-set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVCMOS25} [get_ports gp_in[8]]                     ; ## IO_L3P_T0_DQS_13         (fmc_la_p[21])
-set_property  -dict {PACKAGE_PIN  AE26  IOSTANDARD LVCMOS25} [get_ports gp_in[9]]                     ; ## IO_L3N_T0_DQS_13         (fmc_la_n[21])
-set_property  -dict {PACKAGE_PIN  AD25  IOSTANDARD LVCMOS25} [get_ports gp_in[10]]                    ; ## IO_L4P_T0_13             (fmc_la_p[22])
-set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD LVCMOS25} [get_ports gp_in[11]]                    ; ## IO_L4N_T0_13             (fmc_la_n[22])
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25} [get_ports gp_in[12]]                    ; ## IO_L6P_T0_13             (fmc_la_p[23])
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25} [get_ports gp_in[13]]                    ; ## IO_L6N_T0_VREF_13        (fmc_la_n[23])
-set_property  -dict {PACKAGE_PIN  AE22  IOSTANDARD LVCMOS25} [get_ports gp_in[14]]                    ; ## IO_L7P_T1_13             (fmc_la_p[24])
-set_property  -dict {PACKAGE_PIN  AF22  IOSTANDARD LVCMOS25} [get_ports gp_in[15]]                    ; ## IO_L7N_T1_13             (fmc_la_n[24])
-set_property  -dict {PACKAGE_PIN  AE23  IOSTANDARD LVCMOS25} [get_ports gp_in[16]]                    ; ## IO_L8P_T1_13             (fmc_la_p[25])
-set_property  -dict {PACKAGE_PIN  AF23  IOSTANDARD LVCMOS25} [get_ports gp_in[17]]                    ; ## IO_L8N_T1_13             (fmc_la_n[25])
-set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD LVCMOS25} [get_ports gp_in[18]]                    ; ## IO_L9P_T1_DQS_13         (fmc_la_p[26])
-set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD LVCMOS25} [get_ports gp_in[19]]                    ; ## IO_L9N_T1_DQS_13         (fmc_la_n[26])
-set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports gp_in[20]]                    ; ## IO_L10P_T1_13            (fmc_la_p[27])
-set_property  -dict {PACKAGE_PIN  AA23  IOSTANDARD LVCMOS25} [get_ports gp_in[21]]                    ; ## IO_L10N_T1_13            (fmc_la_n[27])
-set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD LVCMOS25} [get_ports gp_in[22]]                    ; ## IO_L14P_T2_SRCC_13       (fmc_la_p[28])
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS25} [get_ports gp_in[23]]                    ; ## IO_L14N_T2_SRCC_13       (fmc_la_n[28])
-set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS25} [get_ports gp_in[24]]                    ; ## IO_L15P_T2_DQS_13        (fmc_la_p[29])
-set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVCMOS25} [get_ports gp_in[25]]                    ; ## IO_L15N_T2_DQS_13        (fmc_la_n[29])
-set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD LVCMOS25} [get_ports gp_in[26]]                    ; ## IO_L16P_T2_13            (fmc_la_p[30])
-set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS25} [get_ports gp_in[27]]                    ; ## IO_L16N_T2_13            (fmc_la_n[30])
-set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD LVCMOS25} [get_ports gp_in[28]]                    ; ## IO_L17P_T2_13            (fmc_la_p[31])
-set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD LVCMOS25} [get_ports gp_in[29]]                    ; ## IO_L17N_T2_13            (fmc_la_n[31])
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25} [get_ports gp_in[30]]                    ; ## IO_L18P_T2_13            (fmc_la_p[32])
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVCMOS25} [get_ports gp_in[31]]                    ; ## IO_L18N_T2_13            (fmc_la_n[32])
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports gp_in[32]]                    ; ## IO_L19P_T3_13            (fmc_la_p[33])
-set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD LVCMOS25} [get_ports gp_in[33]]                    ; ## IO_L19N_T3_VREF_13       (fmc_la_n[33])
-
-set_property  -dict {PACKAGE_PIN  AC18  IOSTANDARD LVCMOS25} [get_ports gp_out[34]]                   ; ## IO_L21P_T3_DQS_13        (pmod0[0])     
-set_property  -dict {PACKAGE_PIN  AC19  IOSTANDARD LVCMOS25} [get_ports gp_in_1]                      ; ## IO_L21N_T3_DQS_13        (pmod0[1])       
-set_property  -dict {PACKAGE_PIN  AA19  IOSTANDARD LVCMOS25} [get_ports gp_out[35]]                   ; ## IO_L22P_T3_13            (pmod0[2])     
-set_property  -dict {PACKAGE_PIN  AB19  IOSTANDARD LVCMOS25} [get_ports gp_out[36]]                   ; ## IO_L22N_T3_13            (pmod0[3])     
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS25} [get_ports gp_in[34]]                    ; ## IO_L23P_T3_13            (pmod0[4])     
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD LVCMOS25} [get_ports tdd_sync]                     ; ## IO_L23N_T3_13            (pmod0[5]) + (TDD_SYNC)            
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD LVCMOS25} [get_ports gp_in[35]]                    ; ## IO_L24P_T3_13            (pmod0[6])     
-set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD LVCMOS25} [get_ports gp_in[36]]                    ; ## IO_L24N_T3_13            (pmod0[7])     
-
-set_property  -dict {PACKAGE_PIN  AA6}  [get_ports clk_2_p]                                           ; ## MGTREFCLK1P_111          (ad9517_gt_ref_clk_p)
-set_property  -dict {PACKAGE_PIN  AA5}  [get_ports clk_2_n]                                           ; ## MGTREFCLK1N_111          (ad9517_gt_ref_clk_n)
-set_property  -dict {PACKAGE_PIN  AF4}  [get_ports gt_tx_p[1]]                                        ; ## MGTXTXP1_111             (sfp_gt_tx_p)
-set_property  -dict {PACKAGE_PIN  AF3}  [get_ports gt_tx_n[1]]                                        ; ## MGTXTXN1_111             (sfp_gt_tx_n)
-set_property  -dict {PACKAGE_PIN  AE6}  [get_ports gt_rx_p[1]]                                        ; ## MGTXRXP1_111             (sfp_gt_rx_p)
-set_property  -dict {PACKAGE_PIN  AE5}  [get_ports gt_rx_n[1]]                                        ; ## MGTXRXN1_111             (sfp_gt_rx_n)
-
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports gp_in[37]]                    ; ## IO_L1P_T0_34             (CAM_GPIO_0  ) 
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports gp_in[38]]                    ; ## IO_L1N_T0_34             (CAM_GPIO_1  ) 
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports gp_in[39]]                    ; ## IO_L3P_T0_DQS_PUDC_B_34  (CAM_GPIO_4  ) 
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports gp_in[40]]                    ; ## IO_L3N_T0_DQS_34         (CAM_GPIO_5  ) 
-set_property  -dict {PACKAGE_PIN  M6    IOSTANDARD LVCMOS18} [get_ports gp_in[41]]                    ; ## IO_L13P_T2_MRCC_33       (CAM_CLK_P   )     
-set_property  -dict {PACKAGE_PIN  M5    IOSTANDARD LVCMOS18} [get_ports gp_in[42]]                    ; ## IO_L13N_T2_MRCC_33       (CAM_CLK_N   )     
-set_property  -dict {PACKAGE_PIN  M2    IOSTANDARD LVCMOS18} [get_ports gp_in[43]]                    ; ## IO_L16P_T2_33            (CAM_DATA1_P )     
-set_property  -dict {PACKAGE_PIN  L2    IOSTANDARD LVCMOS18} [get_ports gp_in[44]]                    ; ## IO_L16N_T2_33            (CAM_DATA1_N )     
-set_property  -dict {PACKAGE_PIN  N1    IOSTANDARD LVCMOS18} [get_ports gp_in[45]]                    ; ## IO_L18P_T2_33            (CAM_DATA3_P )     
-set_property  -dict {PACKAGE_PIN  M1    IOSTANDARD LVCMOS18} [get_ports gp_in[46]]                    ; ## IO_L18N_T2_33            (CAM_DATA3_N )     
-set_property  -dict {PACKAGE_PIN  K5    IOSTANDARD LVCMOS18} [get_ports gp_in[47]]                    ; ## IO_L20P_T3_33            (CAM_DATA5_P )     
-set_property  -dict {PACKAGE_PIN  J5    IOSTANDARD LVCMOS18} [get_ports gp_in[48]]                    ; ## IO_L20N_T3_33            (CAM_DATA5_N )     
-set_property  -dict {PACKAGE_PIN  K6    IOSTANDARD LVCMOS18} [get_ports gp_in[49]]                    ; ## IO_L22P_T3_33            (CAM_DATA7_P ) 
-set_property  -dict {PACKAGE_PIN  J6    IOSTANDARD LVCMOS18} [get_ports gp_in[50]]                    ; ## IO_L22N_T3_33            (CAM_DATA7_N ) 
-set_property  -dict {PACKAGE_PIN  N7    IOSTANDARD LVCMOS18} [get_ports gp_in[51]]                    ; ## IO_L23P_T3_33            (CAM_SPI_CSN ) 
-set_property  -dict {PACKAGE_PIN  N6    IOSTANDARD LVCMOS18} [get_ports gp_in[52]]                    ; ## IO_L23N_T3_33            (CAM_SPI_CLK ) 
-set_property  -dict {PACKAGE_PIN  J4    IOSTANDARD LVCMOS18} [get_ports gp_in[53]]                    ; ## IO_L12P_T1_MRCC_33       (CAM_REFCLK  ) 
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports gp_out[37]]                   ; ## IO_L2P_T0_34             (CAM_GPIO_2  ) 
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports gp_out[38]]                   ; ## IO_L2N_T0_34             (CAM_GPIO_3  ) 
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports gp_out[39]]                   ; ## IO_L4P_T0_34             (CAM_GPIO_6  ) 
-set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD LVCMOS18} [get_ports gp_out[40]]                   ; ## IO_L4N_T0_34             (CAM_GPIO_7  ) 
-set_property  -dict {PACKAGE_PIN  N3    IOSTANDARD LVCMOS18} [get_ports gp_out[41]]                   ; ## IO_L15P_T2_DQS_33        (CAM_DATA0_P )     
-set_property  -dict {PACKAGE_PIN  N2    IOSTANDARD LVCMOS18} [get_ports gp_out[42]]                   ; ## IO_L15N_T2_DQS_33        (CAM_DATA0_N )     
-set_property  -dict {PACKAGE_PIN  N4    IOSTANDARD LVCMOS18} [get_ports gp_out[43]]                   ; ## IO_L17P_T2_33            (CAM_DATA2_P )     
-set_property  -dict {PACKAGE_PIN  M4    IOSTANDARD LVCMOS18} [get_ports gp_out[44]]                   ; ## IO_L17N_T2_33            (CAM_DATA2_N )     
-set_property  -dict {PACKAGE_PIN  M7    IOSTANDARD LVCMOS18} [get_ports gp_out[45]]                   ; ## IO_L19P_T3_33            (CAM_DATA4_P )     
-set_property  -dict {PACKAGE_PIN  L7    IOSTANDARD LVCMOS18} [get_ports gp_out[46]]                   ; ## IO_L19N_T3_VREF_33       (CAM_DATA4_N )     
-set_property  -dict {PACKAGE_PIN  M8    IOSTANDARD LVCMOS18} [get_ports gp_out[47]]                   ; ## IO_L21P_T3_DQS_33        (CAM_DATA6_P )     
-set_property  -dict {PACKAGE_PIN  L8    IOSTANDARD LVCMOS18} [get_ports gp_out[48]]                   ; ## IO_L21N_T3_DQS_33        (CAM_DATA6_N ) 
-set_property  -dict {PACKAGE_PIN  L5    IOSTANDARD LVCMOS18} [get_ports gp_out[49]]                   ; ## IO_L14P_T2_SRCC_33       (CAM_SYNC_P  )     
-set_property  -dict {PACKAGE_PIN  L4    IOSTANDARD LVCMOS18} [get_ports gp_out[50]]                   ; ## IO_L14N_T2_SRCC_33       (CAM_SYNC_N  )     
-set_property  -dict {PACKAGE_PIN  K8    IOSTANDARD LVCMOS18} [get_ports gp_out[51]]                   ; ## IO_L24P_T3_33            (CAM_SPI_MISO) 
-set_property  -dict {PACKAGE_PIN  K7    IOSTANDARD LVCMOS18} [get_ports gp_out[52]]                   ; ## IO_L24N_T3_33            (CAM_SPI_MOSI) 
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports gp_out[53]]                   ; ## IO_L5P_T0_34             (CAM_GPIO_8  ) 
-                                                                                                                                    
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD LVCMOS25} [get_ports gp_inout[0]]                  ; ## IO_L19P_T3_12            (sfp_gpio[0])
-set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS25} [get_ports gp_inout[1]]                  ; ## IO_L19N_T3_VREF_12       (sfp_gpio[1])
-set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gp_inout[2]]                  ; ## IO_L20P_T3_12            (sfp_gpio[2])
-set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS25} [get_ports gp_inout[3]]                  ; ## IO_L20N_T3_12            (sfp_gpio[3])
-set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gp_inout[4]]                  ; ## IO_L21P_T3_DQS_12        (sfp_gpio[4])
-set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gp_inout[5]]                  ; ## IO_L21N_T3_DQS_12        (sfp_gpio[5])
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVCMOS25} [get_ports gp_inout[6]]                  ; ## IO_L22P_T3_12            (sfp_gpio[6])
-
-# clocks
-
-create_clock -name ref_clk        -period  4.00 [get_ports gt_ref_clk_p]
-create_clock -name xcvr_clk_0     -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
-create_clock -name xcvr_clk_1     -period  8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
-
-
diff --git a/projects/pzsdr2/ccfmc_lvds/system_project.tcl b/projects/pzsdr2/ccfmc_lvds/system_project.tcl
index 1cb1a010f..12d00b4ab 100644
--- a/projects/pzsdr2/ccfmc_lvds/system_project.tcl
+++ b/projects/pzsdr2/ccfmc_lvds/system_project.tcl
@@ -3,15 +3,15 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccfmc_lvds_pzsdr
-adi_project_files ccfmc_lvds_pzsdr [list \
-  "system_top.v" \
-  "system_constr.xdc"\
+set p_device "xc7z035ifbg676-2L"
+adi_project_create pzsdr2_ccfmc_lvds
+adi_project_files pzsdr2_ccfmc_lvds [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
+  "../common/pzsdr2_constr.xdc" \
+  "../common/pzsdr2_constr_lvds.xdc" \
+  "../common/ccfmc_constr.xdc" \
+  "system_top.v" ]
 
-adi_project_run ccfmc_lvds_pzsdr
+adi_project_run pzsdr2_ccfmc_lvds
 
 
diff --git a/projects/pzsdr2/ccfmc_lvds/system_top.v b/projects/pzsdr2/ccfmc_lvds/system_top.v
index 05dd525aa..83e24317f 100644
--- a/projects/pzsdr2/ccfmc_lvds/system_top.v
+++ b/projects/pzsdr2/ccfmc_lvds/system_top.v
@@ -91,7 +91,7 @@ module system_top (
   inout           iic_scl,
   inout           iic_sda,
 
-  inout   [11:0]  gpio_bd,
+  inout   [20:0]  gpio_bd,
 
   output          fan_pwm,
   input           fan_tach,
@@ -100,16 +100,13 @@ module system_top (
   input           clk_0_n,
   input           clk_1_p,
   input           clk_1_n,
-  input           clk_2_p,
-  input           clk_2_n,
-  input           gp_in_0,
-  input           gp_in_1,
-  inout   [ 6:0]  gp_inout,
   output  [53:0]  gp_out,
   input   [53:0]  gp_in,
 
-  input           gt_ref_clk_p,
-  input           gt_ref_clk_n,
+  input           gt_ref_clk_0_p,
+  input           gt_ref_clk_0_n,
+  input           gt_ref_clk_1_p,
+  input           gt_ref_clk_1_n,
   output  [ 1:0]  gt_tx_p,
   output  [ 1:0]  gt_tx_n,
   input   [ 1:0]  gt_rx_p,
@@ -139,13 +136,14 @@ module system_top (
 
   output          enable,
   output          txnrx,
-  input           clk_out,
+  input           clkout_in,
   inout           tdd_sync,
 
   inout           gpio_rf0,
   inout           gpio_rf1,
   inout           gpio_rf2,
   inout           gpio_rf3,
+  inout           gpio_rf4,
   inout           gpio_rfpwr_enable,
   inout           gpio_clksel,
   inout           gpio_resetb,
@@ -167,13 +165,10 @@ module system_top (
   wire            spi_miso_s;
   wire            clk_0;
   wire            clk_1;
-  wire            clk_2;
-  wire            gt_ref_clk;
+  wire            gt_ref_clk_1;
+  wire            gt_ref_clk_0;
   wire    [63:0]  gp_out_s;
   wire    [63:0]  gp_in_s;
-  wire    [63:0]  gp_misc_out_s;
-  wire    [63:0]  gp_misc_in_s;
-  wire    [63:0]  gp_misc_ioenb_s;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
@@ -193,10 +188,6 @@ module system_top (
   assign ad9517_mosi = spi_mosi_s;
   assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); 
 
-  assign gp_misc_in_s[63:10] = gp_misc_out_s[63:18];
-  assign gp_misc_in_s[9] = gp_in_1;
-  assign gp_misc_in_s[8] = gp_in_0;
-  assign gp_misc_in_s[7] = gp_misc_out_s[7];
 
   assign gp_out[53:0] = gp_out_s[53:0];
   assign gp_in_s[63:54] = gp_out_s[63:54];
@@ -214,37 +205,32 @@ module system_top (
     .IB (clk_1_n),
     .O (clk_1));
 
-  IBUFDS_GTE2 i_ibufds_clk_2 (
+  IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 (
     .CEB (1'd0),
-    .I (clk_2_p),
-    .IB (clk_2_n),
-    .O (clk_2),
+    .I (gt_ref_clk_0_p),
+    .IB (gt_ref_clk_0_n),
+    .O (gt_ref_clk_0),
     .ODIV2 ());
 
-  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
+  IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 (
     .CEB (1'd0),
-    .I (gt_ref_clk_p),
-    .IB (gt_ref_clk_n),
-    .O (gt_ref_clk),
+    .I (gt_ref_clk_1_p),
+    .IB (gt_ref_clk_1_n),
+    .O (gt_ref_clk_1),
     .ODIV2 ());
 
-  ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_sfp (
-    .dio_t (gp_misc_ioenb_s[6:0]),
-    .dio_i (gp_misc_out_s[6:0]),
-    .dio_o (gp_misc_in_s[6:0]),
-    .dio_p (gp_inout));
-
   ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
     .dio_t (tdd_sync_t),
     .dio_i (tdd_sync_o),
     .dio_o (tdd_sync_i),
     .dio_p (tdd_sync));
 
-  ad_iobuf #(.DATA_WIDTH(25)) i_iobuf (
-    .dio_t ({gpio_t[60:51], gpio_t[46:32]}),
-    .dio_i ({gpio_o[60:51], gpio_o[46:32]}),
-    .dio_o ({gpio_i[60:51], gpio_i[46:32]}),
-    .dio_p ({ ad9517_pdn,         // 60:60
+  ad_iobuf #(.DATA_WIDTH(26)) i_iobuf (
+    .dio_t ({gpio_t[61:51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[61:51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[61:51], gpio_i[46:32]}),
+    .dio_p ({ gpio_rf4,           // 61:61
+              ad9517_pdn,         // 60:60
               ad9517_ref_sel,     // 59:59
               ad9517_ld,          // 58:58
               ad9517_status,      // 57:57
@@ -260,16 +246,15 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
-    .dio_t (gpio_t[11:0]),
-    .dio_i (gpio_o[11:0]),
-    .dio_o (gpio_i[11:0]),
+  ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
+    .dio_t (gpio_t[20:0]),
+    .dio_i (gpio_o[20:0]),
+    .dio_o (gpio_i[20:0]),
     .dio_p (gpio_bd));
 
   system_wrapper i_system_wrapper (
     .clk_0 (clk_0),
     .clk_1 (clk_1),
-    .clk_2 (clk_2),
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),
     .ddr_cas_n (ddr_cas_n),
@@ -303,20 +288,13 @@ module system_top (
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
     .gp_in_0 (gp_in_s[31:0]),
     .gp_in_1 (gp_in_s[63:32]),
-    .gp_in_2 (gp_misc_in_s[31:0]),
-    .gp_in_3 (gp_misc_in_s[63:32]),
-    .gp_ioenb_0 (),
-    .gp_ioenb_1 (),
-    .gp_ioenb_2 (gp_misc_ioenb_s[31:0]),
-    .gp_ioenb_3 (gp_misc_ioenb_s[63:32]),
     .gp_out_0 (gp_out_s[31:0]),
     .gp_out_1 (gp_out_s[63:32]),
-    .gp_out_2 (gp_misc_out_s[31:0]),
-    .gp_out_3 (gp_misc_out_s[63:32]),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .gt_ref_clk (gt_ref_clk),
+    .gt_ref_clk_0 (gt_ref_clk_0),
+    .gt_ref_clk_1 (gt_ref_clk_1),
     .gt_rx_n (gt_rx_n),
     .gt_rx_p (gt_rx_p),
     .gt_tx_n (gt_tx_n),
diff --git a/projects/pzsdr2/ccpci_lvds/Makefile b/projects/pzsdr2/ccpci_lvds/Makefile
index c7f6462e1..a51a62c98 100644
--- a/projects/pzsdr2/ccpci_lvds/Makefile
+++ b/projects/pzsdr2/ccpci_lvds/Makefile
@@ -7,18 +7,15 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr2_constr_lvds.xdc
+M_DEPS += ../common/pzsdr2_constr.xdc
+M_DEPS += ../common/pzsdr2_bd.tcl
+M_DEPS += ../common/ccpci_constr.xdc
 M_DEPS += ../common/ccpci_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -46,7 +43,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccpci_lvds_pzsdr.sdk/system_top.hdf
+all: lib pzsdr2_ccpci_lvds.sdk/system_top.hdf
 
 
 clean: 
@@ -62,9 +59,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccpci_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+pzsdr2_ccpci_lvds.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccpci_lvds_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr2_ccpci_lvds_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr2/ccpci_lvds/system_bd.tcl b/projects/pzsdr2/ccpci_lvds/system_bd.tcl
index d2b0d9edb..fba5d9aa3 100644
--- a/projects/pzsdr2/ccpci_lvds/system_bd.tcl
+++ b/projects/pzsdr2/ccpci_lvds/system_bd.tcl
@@ -1,10 +1,36 @@
 
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/pzsdr2_bd.tcl
 source ../common/ccpci_bd.tcl
 
-## temporary
-## ila
+## core digital interface -- cmos (1) or lvds (0)
+
+set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
+
+create_bd_port -dir I rx_clk_in_p
+create_bd_port -dir I rx_clk_in_n
+create_bd_port -dir I rx_frame_in_p
+create_bd_port -dir I rx_frame_in_n
+create_bd_port -dir I -from 5 -to 0 rx_data_in_p
+create_bd_port -dir I -from 5 -to 0 rx_data_in_n
+
+create_bd_port -dir O tx_clk_out_p
+create_bd_port -dir O tx_clk_out_n
+create_bd_port -dir O tx_frame_out_p
+create_bd_port -dir O tx_frame_out_n
+create_bd_port -dir O -from 5 -to 0 tx_data_out_p
+create_bd_port -dir O -from 5 -to 0 tx_data_out_n
+
+ad_connect  rx_clk_in_p axi_ad9361/rx_clk_in_p
+ad_connect  rx_clk_in_n axi_ad9361/rx_clk_in_n
+ad_connect  rx_frame_in_p axi_ad9361/rx_frame_in_p
+ad_connect  rx_frame_in_n axi_ad9361/rx_frame_in_n
+ad_connect  rx_data_in_p axi_ad9361/rx_data_in_p
+ad_connect  rx_data_in_n axi_ad9361/rx_data_in_n
+ad_connect  tx_clk_out_p axi_ad9361/tx_clk_out_p
+ad_connect  tx_clk_out_n axi_ad9361/tx_clk_out_n
+ad_connect  tx_frame_out_p axi_ad9361/tx_frame_out_p
+ad_connect  tx_frame_out_n axi_ad9361/tx_frame_out_n
+ad_connect  tx_data_out_p axi_ad9361/tx_data_out_p
+ad_connect  tx_data_out_n axi_ad9361/tx_data_out_n
 
-delete_bd_objs [get_bd_cells ila_adc]
-delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
 
diff --git a/projects/pzsdr2/ccpci_lvds/system_project.tcl b/projects/pzsdr2/ccpci_lvds/system_project.tcl
index 21d73dd03..7922fb931 100644
--- a/projects/pzsdr2/ccpci_lvds/system_project.tcl
+++ b/projects/pzsdr2/ccpci_lvds/system_project.tcl
@@ -1,21 +1,17 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccpci_lvds_pzsdr
-adi_project_files ccpci_lvds_pzsdr [list \
-  "system_top.v" \
-  "system_constr.xdc"\
+set p_device "xc7z035ifbg676-2L"
+adi_project_create pzsdr2_ccpci_lvds
+adi_project_files pzsdr2_ccpci_lvds [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
+  "../common/pzsdr2_constr.xdc" \
+  "../common/pzsdr2_constr_lvds.xdc" \
+  "../common/ccpci_constr.xdc" \
+  "system_top.v" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
-set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
-
-adi_project_run ccpci_lvds_pzsdr
+adi_project_run pzsdr2_ccpci_lvds
 
 
diff --git a/projects/pzsdr2/common/ccbrk_constr.xdc b/projects/pzsdr2/common/ccbrk_constr.xdc
index 1321299c9..5af874e7c 100644
--- a/projects/pzsdr2/common/ccbrk_constr.xdc
+++ b/projects/pzsdr2/common/ccbrk_constr.xdc
@@ -11,19 +11,19 @@ set_property  -dict {PACKAGE_PIN  D8      IOSTANDARD  LVCMOS18} [get_ports  gpio
 set_property  -dict {PACKAGE_PIN  F9      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[2]]   ; ## (lb: gpio_bd[6])   U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26
 set_property  -dict {PACKAGE_PIN  E8      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[3]]   ; ## (lb: gpio_bd[12])  U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28
 set_property  -dict {PACKAGE_PIN  A8      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[4]]   ; ## (lb: gpio_bd[0])   U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16
-set_property  -dict {PACKAGE_PIN  W14     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[5]]   ; ## (lb: gpio_bd[1])   U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2,P13,3
-set_property  -dict {PACKAGE_PIN  W17     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[6]]   ; ## (lb: gpio_bd[2])   U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1,P13,4
-set_property  -dict {PACKAGE_PIN  Y16     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[7]]   ; ## (lb: i2c_scl)      U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 (U1,AF24,SCL,JX2,17,I2C_SCL,P2,14)
-set_property  -dict {PACKAGE_PIN  Y15     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[8]]   ; ## (lb: none)         U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0
-set_property  -dict {PACKAGE_PIN  W16     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[9]]   ; ## (lb: none)         U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1
-set_property  -dict {PACKAGE_PIN  W15     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[10]]  ; ## (lb: none)         U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2
-set_property  -dict {PACKAGE_PIN  V19     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[11]]  ; ## (lb: none)         U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3
+set_property  -dict {PACKAGE_PIN  W14     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[5]]   ; ## (lb: gpio_bd[1])   U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2,P13,3
+set_property  -dict {PACKAGE_PIN  W17     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[6]]   ; ## (lb: gpio_bd[2])   U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1,P13,4
+set_property  -dict {PACKAGE_PIN  Y16     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[7]]   ; ## (lb: i2c_scl)      U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 (U1,AF24,SCL,JX2,17,I2C_SCL,P2,14)
+set_property  -dict {PACKAGE_PIN  Y15     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[8]]   ; ## (lb: none)         U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0
+set_property  -dict {PACKAGE_PIN  W16     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[9]]   ; ## (lb: none)         U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1
+set_property  -dict {PACKAGE_PIN  W15     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[10]]  ; ## (lb: none)         U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2
+set_property  -dict {PACKAGE_PIN  V19     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[11]]  ; ## (lb: none)         U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3
 
 ## orphans- io- (ps7 gpio)
 
-set_property  -dict {PACKAGE_PIN  V18     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[12]]  ; ## (lb: gpio_bd[3])   U1,V18,IO_25_13_JX2,JX2,14,IO_25_13_JX2,P2,3
-set_property  -dict {PACKAGE_PIN  AB24    IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[13]]  ; ## (lb: i2c_sda)      U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 (U1,AF25,SDA,JX2,19,I2C_SDA,P2,16)
-set_property  -dict {PACKAGE_PIN  AA24    IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[14]]  ; ## (lb: none)         U1,AA24,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P
+set_property  -dict {PACKAGE_PIN  V18     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[12]]  ; ## (lb: gpio_bd[3])   U1,V18,IO_25_13_JX2,JX2,14,IO_25_13_JX2,P2,3
+set_property  -dict {PACKAGE_PIN  AB24    IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[13]]  ; ## (lb: i2c_sda)      U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 (U1,AF25,SDA,JX2,19,I2C_SDA,P2,16)
+set_property  -dict {PACKAGE_PIN  AA24    IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[14]]  ; ## (lb: none)         U1,AA24,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P
 set_property  -dict {PACKAGE_PIN  N8      IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[15]]  ; ## (lb: clkout_out)   U1,N8,IO_25_33_JX1,JX1,10,IO_25_33_JX1,P7,31
 
 ## ps7- fixed io- to- fpga regular io (ps7 gpio)
@@ -43,50 +43,50 @@ set_property  -dict {PACKAGE_PIN  E6      IOSTANDARD  LVCMOS18} [get_ports  gpio
 
 ## fpga- regular io
 
-set_property  -dict {PACKAGE_PIN  AA25    IOSTANDARD  LVCMOS18} [get_ports  gp_out[0]]    ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,IO_L01_13_JX2_P,P2,6
-set_property  -dict {PACKAGE_PIN  AB26    IOSTANDARD  LVCMOS18} [get_ports  gp_in[0]]     ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,IO_L02_13_JX2_P,P2,5
-set_property  -dict {PACKAGE_PIN  AB25    IOSTANDARD  LVCMOS18} [get_ports  gp_out[1]]    ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,IO_L01_13_JX2_N,P2,8
-set_property  -dict {PACKAGE_PIN  AC26    IOSTANDARD  LVCMOS18} [get_ports  gp_in[1]]     ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,IO_L02_13_JX2_N,P2,7
-set_property  -dict {PACKAGE_PIN  AE25    IOSTANDARD  LVCMOS18} [get_ports  gp_out[2]]    ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,IO_L03_13_JX2_P,P2,10
-set_property  -dict {PACKAGE_PIN  AD25    IOSTANDARD  LVCMOS18} [get_ports  gp_in[2]]     ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,IO_L04_13_JX2_P,P2,9
-set_property  -dict {PACKAGE_PIN  AE26    IOSTANDARD  LVCMOS18} [get_ports  gp_out[3]]    ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,IO_L03_13_JX2_N,P2,12
-set_property  -dict {PACKAGE_PIN  AD26    IOSTANDARD  LVCMOS18} [get_ports  gp_in[3]]     ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,IO_L04_13_JX2_N,P2,11
-set_property  -dict {PACKAGE_PIN  AE22    IOSTANDARD  LVCMOS18} [get_ports  gp_out[4]]    ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,IO_L07_13_JX2_P,P2,20
-set_property  -dict {PACKAGE_PIN  AE23    IOSTANDARD  LVCMOS18} [get_ports  gp_in[4]]     ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,IO_L08_13_JX2_P,P2,19
-set_property  -dict {PACKAGE_PIN  AF22    IOSTANDARD  LVCMOS18} [get_ports  gp_out[5]]    ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,IO_L07_13_JX2_N,P2,22
-set_property  -dict {PACKAGE_PIN  AF23    IOSTANDARD  LVCMOS18} [get_ports  gp_in[5]]     ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,IO_L08_13_JX2_N,P2,21
-set_property  -dict {PACKAGE_PIN  AB21    IOSTANDARD  LVCMOS18} [get_ports  gp_out[6]]    ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,IO_L09_13_JX2_P,P2,24
-set_property  -dict {PACKAGE_PIN  AA22    IOSTANDARD  LVCMOS18} [get_ports  gp_in[6]]     ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,IO_L10_13_JX2_P,P2,23
-set_property  -dict {PACKAGE_PIN  AB22    IOSTANDARD  LVCMOS18} [get_ports  gp_out[7]]    ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,IO_L09_13_JX2_N,P2,26
-set_property  -dict {PACKAGE_PIN  AA23    IOSTANDARD  LVCMOS18} [get_ports  gp_in[7]]     ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,IO_L10_13_JX2_N,P2,25
-set_property  -dict {PACKAGE_PIN  AD23    IOSTANDARD  LVCMOS18} [get_ports  gp_out[8]]    ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28
-set_property  -dict {PACKAGE_PIN  AC23    IOSTANDARD  LVCMOS18} [get_ports  gp_in[8]]     ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27
-set_property  -dict {PACKAGE_PIN  AD24    IOSTANDARD  LVCMOS18} [get_ports  gp_out[9]]    ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30
-set_property  -dict {PACKAGE_PIN  AC24    IOSTANDARD  LVCMOS18} [get_ports  gp_in[9]]     ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29
-set_property  -dict {PACKAGE_PIN  AD20    IOSTANDARD  LVCMOS18} [get_ports  gp_out[10]]   ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32
-set_property  -dict {PACKAGE_PIN  AC21    IOSTANDARD  LVCMOS18} [get_ports  gp_in[10]]    ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31
-set_property  -dict {PACKAGE_PIN  AD21    IOSTANDARD  LVCMOS18} [get_ports  gp_out[11]]   ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34
-set_property  -dict {PACKAGE_PIN  AC22    IOSTANDARD  LVCMOS18} [get_ports  gp_in[11]]    ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33
-set_property  -dict {PACKAGE_PIN  AF19    IOSTANDARD  LVCMOS18} [get_ports  gp_out[12]]   ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38
-set_property  -dict {PACKAGE_PIN  AE20    IOSTANDARD  LVCMOS18} [get_ports  gp_in[12]]    ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37
-set_property  -dict {PACKAGE_PIN  AF20    IOSTANDARD  LVCMOS18} [get_ports  gp_out[13]]   ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40
-set_property  -dict {PACKAGE_PIN  AE21    IOSTANDARD  LVCMOS18} [get_ports  gp_in[13]]    ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39
-set_property  -dict {PACKAGE_PIN  AD18    IOSTANDARD  LVCMOS18} [get_ports  gp_out[14]]   ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42
-set_property  -dict {PACKAGE_PIN  AE18    IOSTANDARD  LVCMOS18} [get_ports  gp_in[14]]    ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41
-set_property  -dict {PACKAGE_PIN  AD19    IOSTANDARD  LVCMOS18} [get_ports  gp_out[15]]   ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44
-set_property  -dict {PACKAGE_PIN  AF18    IOSTANDARD  LVCMOS18} [get_ports  gp_in[15]]    ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43
-set_property  -dict {PACKAGE_PIN  W20     IOSTANDARD  LVCMOS18} [get_ports  gp_out[16]]   ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46
-set_property  -dict {PACKAGE_PIN  AA20    IOSTANDARD  LVCMOS18} [get_ports  gp_in[16]]    ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45
-set_property  -dict {PACKAGE_PIN  Y20     IOSTANDARD  LVCMOS18} [get_ports  gp_out[17]]   ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48
-set_property  -dict {PACKAGE_PIN  AB20    IOSTANDARD  LVCMOS18} [get_ports  gp_in[17]]    ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47
-set_property  -dict {PACKAGE_PIN  AC18    IOSTANDARD  LVCMOS18} [get_ports  gp_out[18]]   ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52
-set_property  -dict {PACKAGE_PIN  AA19    IOSTANDARD  LVCMOS18} [get_ports  gp_in[18]]    ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,IO_L22_13_JX2_P,P2,51
-set_property  -dict {PACKAGE_PIN  AC19    IOSTANDARD  LVCMOS18} [get_ports  gp_out[19]]   ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54
-set_property  -dict {PACKAGE_PIN  AB19    IOSTANDARD  LVCMOS18} [get_ports  gp_in[19]]    ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,IO_L22_13_JX2_N,P2,53
-set_property  -dict {PACKAGE_PIN  W18     IOSTANDARD  LVCMOS18} [get_ports  gp_out[20]]   ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,IO_L23_13_JX2_P,P2,56
-set_property  -dict {PACKAGE_PIN  Y18     IOSTANDARD  LVCMOS18} [get_ports  gp_in[20]]    ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,IO_L24_13_JX2_P,P2,55
-set_property  -dict {PACKAGE_PIN  W19     IOSTANDARD  LVCMOS18} [get_ports  gp_out[21]]   ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,IO_L23_13_JX2_N,P2,58
-set_property  -dict {PACKAGE_PIN  AA18    IOSTANDARD  LVCMOS18} [get_ports  gp_in[21]]    ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,IO_L24_13_JX2_N,P2,57
+set_property  -dict {PACKAGE_PIN  AA25    IOSTANDARD  LVCMOS25} [get_ports  gp_out[0]]    ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,IO_L01_13_JX2_P,P2,6
+set_property  -dict {PACKAGE_PIN  AB26    IOSTANDARD  LVCMOS25} [get_ports  gp_in[0]]     ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,IO_L02_13_JX2_P,P2,5
+set_property  -dict {PACKAGE_PIN  AB25    IOSTANDARD  LVCMOS25} [get_ports  gp_out[1]]    ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,IO_L01_13_JX2_N,P2,8
+set_property  -dict {PACKAGE_PIN  AC26    IOSTANDARD  LVCMOS25} [get_ports  gp_in[1]]     ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,IO_L02_13_JX2_N,P2,7
+set_property  -dict {PACKAGE_PIN  AE25    IOSTANDARD  LVCMOS25} [get_ports  gp_out[2]]    ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,IO_L03_13_JX2_P,P2,10
+set_property  -dict {PACKAGE_PIN  AD25    IOSTANDARD  LVCMOS25} [get_ports  gp_in[2]]     ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,IO_L04_13_JX2_P,P2,9
+set_property  -dict {PACKAGE_PIN  AE26    IOSTANDARD  LVCMOS25} [get_ports  gp_out[3]]    ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,IO_L03_13_JX2_N,P2,12
+set_property  -dict {PACKAGE_PIN  AD26    IOSTANDARD  LVCMOS25} [get_ports  gp_in[3]]     ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,IO_L04_13_JX2_N,P2,11
+set_property  -dict {PACKAGE_PIN  AE22    IOSTANDARD  LVCMOS25} [get_ports  gp_out[4]]    ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,IO_L07_13_JX2_P,P2,20
+set_property  -dict {PACKAGE_PIN  AE23    IOSTANDARD  LVCMOS25} [get_ports  gp_in[4]]     ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,IO_L08_13_JX2_P,P2,19
+set_property  -dict {PACKAGE_PIN  AF22    IOSTANDARD  LVCMOS25} [get_ports  gp_out[5]]    ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,IO_L07_13_JX2_N,P2,22
+set_property  -dict {PACKAGE_PIN  AF23    IOSTANDARD  LVCMOS25} [get_ports  gp_in[5]]     ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,IO_L08_13_JX2_N,P2,21
+set_property  -dict {PACKAGE_PIN  AB21    IOSTANDARD  LVCMOS25} [get_ports  gp_out[6]]    ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,IO_L09_13_JX2_P,P2,24
+set_property  -dict {PACKAGE_PIN  AA22    IOSTANDARD  LVCMOS25} [get_ports  gp_in[6]]     ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,IO_L10_13_JX2_P,P2,23
+set_property  -dict {PACKAGE_PIN  AB22    IOSTANDARD  LVCMOS25} [get_ports  gp_out[7]]    ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,IO_L09_13_JX2_N,P2,26
+set_property  -dict {PACKAGE_PIN  AA23    IOSTANDARD  LVCMOS25} [get_ports  gp_in[7]]     ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,IO_L10_13_JX2_N,P2,25
+set_property  -dict {PACKAGE_PIN  AD23    IOSTANDARD  LVCMOS25} [get_ports  gp_out[8]]    ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28
+set_property  -dict {PACKAGE_PIN  AC23    IOSTANDARD  LVCMOS25} [get_ports  gp_in[8]]     ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27
+set_property  -dict {PACKAGE_PIN  AD24    IOSTANDARD  LVCMOS25} [get_ports  gp_out[9]]    ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30
+set_property  -dict {PACKAGE_PIN  AC24    IOSTANDARD  LVCMOS25} [get_ports  gp_in[9]]     ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29
+set_property  -dict {PACKAGE_PIN  AD20    IOSTANDARD  LVCMOS25} [get_ports  gp_out[10]]   ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32
+set_property  -dict {PACKAGE_PIN  AC21    IOSTANDARD  LVCMOS25} [get_ports  gp_in[10]]    ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31
+set_property  -dict {PACKAGE_PIN  AD21    IOSTANDARD  LVCMOS25} [get_ports  gp_out[11]]   ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34
+set_property  -dict {PACKAGE_PIN  AC22    IOSTANDARD  LVCMOS25} [get_ports  gp_in[11]]    ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33
+set_property  -dict {PACKAGE_PIN  AF19    IOSTANDARD  LVCMOS25} [get_ports  gp_out[12]]   ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38
+set_property  -dict {PACKAGE_PIN  AE20    IOSTANDARD  LVCMOS25} [get_ports  gp_in[12]]    ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37
+set_property  -dict {PACKAGE_PIN  AF20    IOSTANDARD  LVCMOS25} [get_ports  gp_out[13]]   ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40
+set_property  -dict {PACKAGE_PIN  AE21    IOSTANDARD  LVCMOS25} [get_ports  gp_in[13]]    ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39
+set_property  -dict {PACKAGE_PIN  AD18    IOSTANDARD  LVCMOS25} [get_ports  gp_out[14]]   ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42
+set_property  -dict {PACKAGE_PIN  AE18    IOSTANDARD  LVCMOS25} [get_ports  gp_in[14]]    ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41
+set_property  -dict {PACKAGE_PIN  AD19    IOSTANDARD  LVCMOS25} [get_ports  gp_out[15]]   ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44
+set_property  -dict {PACKAGE_PIN  AF18    IOSTANDARD  LVCMOS25} [get_ports  gp_in[15]]    ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43
+set_property  -dict {PACKAGE_PIN  W20     IOSTANDARD  LVCMOS25} [get_ports  gp_out[16]]   ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46
+set_property  -dict {PACKAGE_PIN  AA20    IOSTANDARD  LVCMOS25} [get_ports  gp_in[16]]    ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45
+set_property  -dict {PACKAGE_PIN  Y20     IOSTANDARD  LVCMOS25} [get_ports  gp_out[17]]   ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48
+set_property  -dict {PACKAGE_PIN  AB20    IOSTANDARD  LVCMOS25} [get_ports  gp_in[17]]    ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47
+set_property  -dict {PACKAGE_PIN  AC18    IOSTANDARD  LVCMOS25} [get_ports  gp_out[18]]   ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52
+set_property  -dict {PACKAGE_PIN  AA19    IOSTANDARD  LVCMOS25} [get_ports  gp_in[18]]    ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,IO_L22_13_JX2_P,P2,51
+set_property  -dict {PACKAGE_PIN  AC19    IOSTANDARD  LVCMOS25} [get_ports  gp_out[19]]   ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54
+set_property  -dict {PACKAGE_PIN  AB19    IOSTANDARD  LVCMOS25} [get_ports  gp_in[19]]    ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,IO_L22_13_JX2_N,P2,53
+set_property  -dict {PACKAGE_PIN  W18     IOSTANDARD  LVCMOS25} [get_ports  gp_out[20]]   ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,IO_L23_13_JX2_P,P2,56
+set_property  -dict {PACKAGE_PIN  Y18     IOSTANDARD  LVCMOS25} [get_ports  gp_in[20]]    ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,IO_L24_13_JX2_P,P2,55
+set_property  -dict {PACKAGE_PIN  W19     IOSTANDARD  LVCMOS25} [get_ports  gp_out[21]]   ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,IO_L23_13_JX2_N,P2,58
+set_property  -dict {PACKAGE_PIN  AA18    IOSTANDARD  LVCMOS25} [get_ports  gp_in[21]]    ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,IO_L24_13_JX2_N,P2,57
 set_property  -dict {PACKAGE_PIN  G4      IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]   ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,IO_L01_33_JX1_P,P4,2
 set_property  -dict {PACKAGE_PIN  D4      IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]    ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,IO_L02_33_JX1_P,P4,1
 set_property  -dict {PACKAGE_PIN  F4      IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]   ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,IO_L01_33_JX1_N,P4,4
@@ -171,50 +171,50 @@ set_property  -dict {PACKAGE_PIN  A5      IOSTANDARD  LVCMOS18} [get_ports  gp_o
 set_property  -dict {PACKAGE_PIN  A3      IOSTANDARD  LVCMOS18} [get_ports  gp_in[62]]    ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27
 set_property  -dict {PACKAGE_PIN  B7      IOSTANDARD  LVCMOS18} [get_ports  gp_out[63]]   ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30
 set_property  -dict {PACKAGE_PIN  L9      IOSTANDARD  LVCMOS18} [get_ports  gp_in[63]]    ; ## U1,L9,IO_00_33_JX1,JX1,9,IO_00_33_JX1,P7,29
-set_property  -dict {PACKAGE_PIN  AD15    IOSTANDARD  LVCMOS18} [get_ports  gp_out[64]]   ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,IO_L15_12_JX3_N,P13,6
-set_property  -dict {PACKAGE_PIN  AF14    IOSTANDARD  LVCMOS18} [get_ports  gp_in[64]]    ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,IO_L16_12_JX3_N,P13,5
-set_property  -dict {PACKAGE_PIN  AD16    IOSTANDARD  LVCMOS18} [get_ports  gp_out[65]]   ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,IO_L15_12_JX3_P,P13,8
-set_property  -dict {PACKAGE_PIN  AF15    IOSTANDARD  LVCMOS18} [get_ports  gp_in[65]]    ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,IO_L16_12_JX3_P,P13,7
-set_property  -dict {PACKAGE_PIN  AD14    IOSTANDARD  LVCMOS18} [get_ports  gp_out[66]]   ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,IO_L13_MRCC_12_JX3_N,P13,10
-set_property  -dict {PACKAGE_PIN  AB14    IOSTANDARD  LVCMOS18} [get_ports  gp_in[66]]    ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,IO_L14_SRCC_12_JX3_N,P13,9
-set_property  -dict {PACKAGE_PIN  AC14    IOSTANDARD  LVCMOS18} [get_ports  gp_out[67]]   ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,IO_L13_MRCC_12_JX3_P,P13,12
-set_property  -dict {PACKAGE_PIN  AB15    IOSTANDARD  LVCMOS18} [get_ports  gp_in[67]]    ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,IO_L14_SRCC_12_JX3_P,P13,11
-set_property  -dict {PACKAGE_PIN  AD11    IOSTANDARD  LVCMOS18} [get_ports  gp_out[68]]   ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,IO_L11_SRCC_12_JX3_N,P13,14
-set_property  -dict {PACKAGE_PIN  AD13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[68]]    ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,IO_L12_MRCC_12_JX3_N,P13,13
-set_property  -dict {PACKAGE_PIN  AC12    IOSTANDARD  LVCMOS18} [get_ports  gp_out[69]]   ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,IO_L11_SRCC_12_JX3_P,P13,16
-set_property  -dict {PACKAGE_PIN  AC13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[69]]    ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,IO_L12_MRCC_12_JX3_P,P13,15
-set_property  -dict {PACKAGE_PIN  AF10    IOSTANDARD  LVCMOS18} [get_ports  gp_out[70]]   ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,IO_L09_12_JX3_N,P13,20
-set_property  -dict {PACKAGE_PIN  AF13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[70]]    ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,IO_L10_12_JX3_N,P13,19
-set_property  -dict {PACKAGE_PIN  AE11    IOSTANDARD  LVCMOS18} [get_ports  gp_out[71]]   ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,IO_L09_12_JX3_P,P13,22
-set_property  -dict {PACKAGE_PIN  AE13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[71]]    ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,IO_L10_12_JX3_P,P13,21
-set_property  -dict {PACKAGE_PIN  AD10    IOSTANDARD  LVCMOS18} [get_ports  gp_out[72]]   ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,IO_L07_12_JX3_N,P13,24
-set_property  -dict {PACKAGE_PIN  AF12    IOSTANDARD  LVCMOS18} [get_ports  gp_in[72]]    ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,IO_L08_12_JX3_N,P13,23
-set_property  -dict {PACKAGE_PIN  AE10    IOSTANDARD  LVCMOS18} [get_ports  gp_out[73]]   ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,IO_L07_12_JX3_P,P13,26
-set_property  -dict {PACKAGE_PIN  AE12    IOSTANDARD  LVCMOS18} [get_ports  gp_in[73]]    ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,IO_L08_12_JX3_P,P13,25
-set_property  -dict {PACKAGE_PIN  Y13     IOSTANDARD  LVCMOS18} [get_ports  gp_out[74]]   ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,IO_L05_12_JX3_N,P13,28
-set_property  -dict {PACKAGE_PIN  AA12    IOSTANDARD  LVCMOS18} [get_ports  gp_in[74]]    ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,IO_L06_12_JX3_N,P13,27
-set_property  -dict {PACKAGE_PIN  W13     IOSTANDARD  LVCMOS18} [get_ports  gp_out[75]]   ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,IO_L05_12_JX3_P,P13,30
-set_property  -dict {PACKAGE_PIN  AA13    IOSTANDARD  LVCMOS18} [get_ports  gp_in[75]]    ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,IO_L06_12_JX3_P,P13,29
-set_property  -dict {PACKAGE_PIN  AA10    IOSTANDARD  LVCMOS18} [get_ports  gp_out[76]]   ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,IO_L03_12_JX3_N,P13,32
-set_property  -dict {PACKAGE_PIN  AB10    IOSTANDARD  LVCMOS18} [get_ports  gp_in[76]]    ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,IO_L04_12_JX3_N,P13,31
-set_property  -dict {PACKAGE_PIN  Y10     IOSTANDARD  LVCMOS18} [get_ports  gp_out[77]]   ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,IO_L03_12_JX3_P,P13,34
-set_property  -dict {PACKAGE_PIN  AB11    IOSTANDARD  LVCMOS18} [get_ports  gp_in[77]]    ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,IO_L04_12_JX3_P,P13,33
-set_property  -dict {PACKAGE_PIN  Y11     IOSTANDARD  LVCMOS18} [get_ports  gp_out[78]]   ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,IO_L01_12_JX3_N,P13,36
-set_property  -dict {PACKAGE_PIN  AC11    IOSTANDARD  LVCMOS18} [get_ports  gp_in[78]]    ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,IO_L02_12_JX3_N,P13,35
-set_property  -dict {PACKAGE_PIN  Y12     IOSTANDARD  LVCMOS18} [get_ports  gp_out[79]]   ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,IO_L01_12_JX3_P,P13,38
-set_property  -dict {PACKAGE_PIN  AB12    IOSTANDARD  LVCMOS18} [get_ports  gp_in[79]]    ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,IO_L02_12_JX3_P,P13,37
-set_property  -dict {PACKAGE_PIN  AE16    IOSTANDARD  LVCMOS18} [get_ports  gp_out[80]]   ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,IO_L17_12_JX2_P,P13,42
-set_property  -dict {PACKAGE_PIN  AE17    IOSTANDARD  LVCMOS18} [get_ports  gp_in[80]]    ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,IO_L18_12_JX2_P,P13,41
-set_property  -dict {PACKAGE_PIN  AE15    IOSTANDARD  LVCMOS18} [get_ports  gp_out[81]]   ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,IO_L17_12_JX2_N,P13,44
-set_property  -dict {PACKAGE_PIN  AF17    IOSTANDARD  LVCMOS18} [get_ports  gp_in[81]]    ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,IO_L18_12_JX2_N,P13,43
-set_property  -dict {PACKAGE_PIN  Y17     IOSTANDARD  LVCMOS18} [get_ports  gp_out[82]]   ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,IO_L19_12_JX2_P,P13,46
-set_property  -dict {PACKAGE_PIN  AB17    IOSTANDARD  LVCMOS18} [get_ports  gp_in[82]]    ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,IO_L20_12_JX2_P,P13,45
-set_property  -dict {PACKAGE_PIN  AA17    IOSTANDARD  LVCMOS18} [get_ports  gp_out[83]]   ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,IO_L19_12_JX2_N,P13,48
-set_property  -dict {PACKAGE_PIN  AB16    IOSTANDARD  LVCMOS18} [get_ports  gp_in[83]]    ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,IO_L20_12_JX2_N,P13,47
-set_property  -dict {PACKAGE_PIN  AC17    IOSTANDARD  LVCMOS18} [get_ports  gp_out[84]]   ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,IO_L21_12_JX2_P,P13,50
-set_property  -dict {PACKAGE_PIN  AA15    IOSTANDARD  LVCMOS18} [get_ports  gp_in[84]]    ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,IO_L22_12_JX2_P,P13,49
-set_property  -dict {PACKAGE_PIN  AC16    IOSTANDARD  LVCMOS18} [get_ports  gp_out[85]]   ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,IO_L21_12_JX2_N,P13,52
-set_property  -dict {PACKAGE_PIN  AA14    IOSTANDARD  LVCMOS18} [get_ports  gp_in[85]]    ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,IO_L22_12_JX2_N,P13,51
+set_property  -dict {PACKAGE_PIN  AD15    IOSTANDARD  LVCMOS25} [get_ports  gp_out[64]]   ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,IO_L15_12_JX3_N,P13,6
+set_property  -dict {PACKAGE_PIN  AF14    IOSTANDARD  LVCMOS25} [get_ports  gp_in[64]]    ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,IO_L16_12_JX3_N,P13,5
+set_property  -dict {PACKAGE_PIN  AD16    IOSTANDARD  LVCMOS25} [get_ports  gp_out[65]]   ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,IO_L15_12_JX3_P,P13,8
+set_property  -dict {PACKAGE_PIN  AF15    IOSTANDARD  LVCMOS25} [get_ports  gp_in[65]]    ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,IO_L16_12_JX3_P,P13,7
+set_property  -dict {PACKAGE_PIN  AD14    IOSTANDARD  LVCMOS25} [get_ports  gp_out[66]]   ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,IO_L13_MRCC_12_JX3_N,P13,10
+set_property  -dict {PACKAGE_PIN  AB14    IOSTANDARD  LVCMOS25} [get_ports  gp_in[66]]    ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,IO_L14_SRCC_12_JX3_N,P13,9
+set_property  -dict {PACKAGE_PIN  AC14    IOSTANDARD  LVCMOS25} [get_ports  gp_out[67]]   ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,IO_L13_MRCC_12_JX3_P,P13,12
+set_property  -dict {PACKAGE_PIN  AB15    IOSTANDARD  LVCMOS25} [get_ports  gp_in[67]]    ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,IO_L14_SRCC_12_JX3_P,P13,11
+set_property  -dict {PACKAGE_PIN  AD11    IOSTANDARD  LVCMOS25} [get_ports  gp_out[68]]   ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,IO_L11_SRCC_12_JX3_N,P13,14
+set_property  -dict {PACKAGE_PIN  AD13    IOSTANDARD  LVCMOS25} [get_ports  gp_in[68]]    ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,IO_L12_MRCC_12_JX3_N,P13,13
+set_property  -dict {PACKAGE_PIN  AC12    IOSTANDARD  LVCMOS25} [get_ports  gp_out[69]]   ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,IO_L11_SRCC_12_JX3_P,P13,16
+set_property  -dict {PACKAGE_PIN  AC13    IOSTANDARD  LVCMOS25} [get_ports  gp_in[69]]    ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,IO_L12_MRCC_12_JX3_P,P13,15
+set_property  -dict {PACKAGE_PIN  AF10    IOSTANDARD  LVCMOS25} [get_ports  gp_out[70]]   ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,IO_L09_12_JX3_N,P13,20
+set_property  -dict {PACKAGE_PIN  AF13    IOSTANDARD  LVCMOS25} [get_ports  gp_in[70]]    ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,IO_L10_12_JX3_N,P13,19
+set_property  -dict {PACKAGE_PIN  AE11    IOSTANDARD  LVCMOS25} [get_ports  gp_out[71]]   ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,IO_L09_12_JX3_P,P13,22
+set_property  -dict {PACKAGE_PIN  AE13    IOSTANDARD  LVCMOS25} [get_ports  gp_in[71]]    ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,IO_L10_12_JX3_P,P13,21
+set_property  -dict {PACKAGE_PIN  AD10    IOSTANDARD  LVCMOS25} [get_ports  gp_out[72]]   ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,IO_L07_12_JX3_N,P13,24
+set_property  -dict {PACKAGE_PIN  AF12    IOSTANDARD  LVCMOS25} [get_ports  gp_in[72]]    ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,IO_L08_12_JX3_N,P13,23
+set_property  -dict {PACKAGE_PIN  AE10    IOSTANDARD  LVCMOS25} [get_ports  gp_out[73]]   ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,IO_L07_12_JX3_P,P13,26
+set_property  -dict {PACKAGE_PIN  AE12    IOSTANDARD  LVCMOS25} [get_ports  gp_in[73]]    ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,IO_L08_12_JX3_P,P13,25
+set_property  -dict {PACKAGE_PIN  Y13     IOSTANDARD  LVCMOS25} [get_ports  gp_out[74]]   ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,IO_L05_12_JX3_N,P13,28
+set_property  -dict {PACKAGE_PIN  AA12    IOSTANDARD  LVCMOS25} [get_ports  gp_in[74]]    ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,IO_L06_12_JX3_N,P13,27
+set_property  -dict {PACKAGE_PIN  W13     IOSTANDARD  LVCMOS25} [get_ports  gp_out[75]]   ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,IO_L05_12_JX3_P,P13,30
+set_property  -dict {PACKAGE_PIN  AA13    IOSTANDARD  LVCMOS25} [get_ports  gp_in[75]]    ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,IO_L06_12_JX3_P,P13,29
+set_property  -dict {PACKAGE_PIN  AA10    IOSTANDARD  LVCMOS25} [get_ports  gp_out[76]]   ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,IO_L03_12_JX3_N,P13,32
+set_property  -dict {PACKAGE_PIN  AB10    IOSTANDARD  LVCMOS25} [get_ports  gp_in[76]]    ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,IO_L04_12_JX3_N,P13,31
+set_property  -dict {PACKAGE_PIN  Y10     IOSTANDARD  LVCMOS25} [get_ports  gp_out[77]]   ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,IO_L03_12_JX3_P,P13,34
+set_property  -dict {PACKAGE_PIN  AB11    IOSTANDARD  LVCMOS25} [get_ports  gp_in[77]]    ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,IO_L04_12_JX3_P,P13,33
+set_property  -dict {PACKAGE_PIN  Y11     IOSTANDARD  LVCMOS25} [get_ports  gp_out[78]]   ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,IO_L01_12_JX3_N,P13,36
+set_property  -dict {PACKAGE_PIN  AC11    IOSTANDARD  LVCMOS25} [get_ports  gp_in[78]]    ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,IO_L02_12_JX3_N,P13,35
+set_property  -dict {PACKAGE_PIN  Y12     IOSTANDARD  LVCMOS25} [get_ports  gp_out[79]]   ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,IO_L01_12_JX3_P,P13,38
+set_property  -dict {PACKAGE_PIN  AB12    IOSTANDARD  LVCMOS25} [get_ports  gp_in[79]]    ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,IO_L02_12_JX3_P,P13,37
+set_property  -dict {PACKAGE_PIN  AE16    IOSTANDARD  LVCMOS25} [get_ports  gp_out[80]]   ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,IO_L17_12_JX2_P,P13,42
+set_property  -dict {PACKAGE_PIN  AE17    IOSTANDARD  LVCMOS25} [get_ports  gp_in[80]]    ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,IO_L18_12_JX2_P,P13,41
+set_property  -dict {PACKAGE_PIN  AE15    IOSTANDARD  LVCMOS25} [get_ports  gp_out[81]]   ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,IO_L17_12_JX2_N,P13,44
+set_property  -dict {PACKAGE_PIN  AF17    IOSTANDARD  LVCMOS25} [get_ports  gp_in[81]]    ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,IO_L18_12_JX2_N,P13,43
+set_property  -dict {PACKAGE_PIN  Y17     IOSTANDARD  LVCMOS25} [get_ports  gp_out[82]]   ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,IO_L19_12_JX2_P,P13,46
+set_property  -dict {PACKAGE_PIN  AB17    IOSTANDARD  LVCMOS25} [get_ports  gp_in[82]]    ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,IO_L20_12_JX2_P,P13,45
+set_property  -dict {PACKAGE_PIN  AA17    IOSTANDARD  LVCMOS25} [get_ports  gp_out[83]]   ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,IO_L19_12_JX2_N,P13,48
+set_property  -dict {PACKAGE_PIN  AB16    IOSTANDARD  LVCMOS25} [get_ports  gp_in[83]]    ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,IO_L20_12_JX2_N,P13,47
+set_property  -dict {PACKAGE_PIN  AC17    IOSTANDARD  LVCMOS25} [get_ports  gp_out[84]]   ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,IO_L21_12_JX2_P,P13,50
+set_property  -dict {PACKAGE_PIN  AA15    IOSTANDARD  LVCMOS25} [get_ports  gp_in[84]]    ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,IO_L22_12_JX2_P,P13,49
+set_property  -dict {PACKAGE_PIN  AC16    IOSTANDARD  LVCMOS25} [get_ports  gp_out[85]]   ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,IO_L21_12_JX2_N,P13,52
+set_property  -dict {PACKAGE_PIN  AA14    IOSTANDARD  LVCMOS25} [get_ports  gp_in[85]]    ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,IO_L22_12_JX2_N,P13,51
 
 ## transceiver loop-backs (on-ccbrk)
 
diff --git a/projects/pzsdr2/common/ccfmc_bd.tcl b/projects/pzsdr2/common/ccfmc_bd.tcl
index 2af9f4dc3..09a99b468 100644
--- a/projects/pzsdr2/common/ccfmc_bd.tcl
+++ b/projects/pzsdr2/common/ccfmc_bd.tcl
@@ -142,14 +142,14 @@ ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
 set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb]
 set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pz_xcvrlb
 
-create_bd_port -dir I gt_ref_clk
+create_bd_port -dir I gt_ref_clk_0
 create_bd_port -dir I -from 1 -to 0 gt_rx_p
 create_bd_port -dir I -from 1 -to 0 gt_rx_n
 create_bd_port -dir O -from 1 -to 0 gt_tx_p
 create_bd_port -dir O -from 1 -to 0 gt_tx_n
 
 ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb
-ad_connect  axi_pz_xcvrlb/ref_clk gt_ref_clk
+ad_connect  axi_pz_xcvrlb/ref_clk gt_ref_clk_0
 ad_connect  axi_pz_xcvrlb/rx_p gt_rx_p
 ad_connect  axi_pz_xcvrlb/rx_n gt_rx_n
 ad_connect  axi_pz_xcvrlb/tx_p gt_tx_p
@@ -159,42 +159,26 @@ ad_connect  axi_pz_xcvrlb/tx_n gt_tx_n
 
 set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
 set_property -dict [list CONFIG.NUM_OF_CLK_MONS {3}] $axi_gpreg
-set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg
 set_property -dict [list CONFIG.BUF_ENABLE_0 {1}] $axi_gpreg
 set_property -dict [list CONFIG.BUF_ENABLE_1 {1}] $axi_gpreg
 set_property -dict [list CONFIG.BUF_ENABLE_2 {1}] $axi_gpreg
 
 create_bd_port -dir I -from 31 -to 0 gp_in_0
 create_bd_port -dir I -from 31 -to 0 gp_in_1
-create_bd_port -dir I -from 31 -to 0 gp_in_2
-create_bd_port -dir I -from 31 -to 0 gp_in_3
 create_bd_port -dir O -from 31 -to 0 gp_out_0
 create_bd_port -dir O -from 31 -to 0 gp_out_1
-create_bd_port -dir O -from 31 -to 0 gp_out_2
-create_bd_port -dir O -from 31 -to 0 gp_out_3
-create_bd_port -dir O -from 31 -to 0 gp_ioenb_0
-create_bd_port -dir O -from 31 -to 0 gp_ioenb_1
-create_bd_port -dir O -from 31 -to 0 gp_ioenb_2
-create_bd_port -dir O -from 31 -to 0 gp_ioenb_3
 create_bd_port -dir I clk_0
 create_bd_port -dir I clk_1
-create_bd_port -dir I clk_2
+create_bd_port -dir I gt_ref_clk_1
 
 ad_connect  clk_0 axi_gpreg/d_clk_0
 ad_connect  clk_1 axi_gpreg/d_clk_1
-ad_connect  clk_2 axi_gpreg/d_clk_2
+ad_connect  gt_ref_clk_1 axi_gpreg/d_clk_2
 ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
 ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
-ad_connect  gp_in_2 axi_gpreg/up_gp_in_2
-ad_connect  gp_in_3 axi_gpreg/up_gp_in_3
 ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
 ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
-ad_connect  gp_out_2 axi_gpreg/up_gp_out_2
-ad_connect  gp_out_3 axi_gpreg/up_gp_out_3
-ad_connect  gp_ioenb_0 axi_gpreg/up_gp_ioenb_0
-ad_connect  gp_ioenb_1 axi_gpreg/up_gp_ioenb_1
-ad_connect  gp_ioenb_2 axi_gpreg/up_gp_ioenb_2
-ad_connect  gp_ioenb_3 axi_gpreg/up_gp_ioenb_3
 ad_cpu_interconnect 0x41200000 axi_gpreg
 
 ## temporary (remove ila indirectly)
diff --git a/projects/pzsdr2/common/pzsdr2_bd.tcl b/projects/pzsdr2/common/pzsdr2_bd.tcl
index 85a82ff18..bafa5c799 100644
--- a/projects/pzsdr2/common/pzsdr2_bd.tcl
+++ b/projects/pzsdr2/common/pzsdr2_bd.tcl
@@ -362,4 +362,66 @@ set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
 
 set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361]
 
+## lvds/cmos configuration
+## core digital interface -- cmos (1) or lvds (0)
+
+proc cfg_ad9361_interface {cmos_or_lvds} {
+
+  if {$cmos_or_lvds eq "LVDS"} {
+
+    set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
+
+    create_bd_port -dir I rx_clk_in_p
+    create_bd_port -dir I rx_clk_in_n
+    create_bd_port -dir I rx_frame_in_p
+    create_bd_port -dir I rx_frame_in_n
+    create_bd_port -dir I -from 5 -to 0 rx_data_in_p
+    create_bd_port -dir I -from 5 -to 0 rx_data_in_n
+
+    create_bd_port -dir O tx_clk_out_p
+    create_bd_port -dir O tx_clk_out_n
+    create_bd_port -dir O tx_frame_out_p
+    create_bd_port -dir O tx_frame_out_n
+    create_bd_port -dir O -from 5 -to 0 tx_data_out_p
+    create_bd_port -dir O -from 5 -to 0 tx_data_out_n
+
+    ad_connect  rx_clk_in_p axi_ad9361/rx_clk_in_p
+    ad_connect  rx_clk_in_n axi_ad9361/rx_clk_in_n
+    ad_connect  rx_frame_in_p axi_ad9361/rx_frame_in_p
+    ad_connect  rx_frame_in_n axi_ad9361/rx_frame_in_n
+    ad_connect  rx_data_in_p axi_ad9361/rx_data_in_p
+    ad_connect  rx_data_in_n axi_ad9361/rx_data_in_n
+    ad_connect  tx_clk_out_p axi_ad9361/tx_clk_out_p
+    ad_connect  tx_clk_out_n axi_ad9361/tx_clk_out_n
+    ad_connect  tx_frame_out_p axi_ad9361/tx_frame_out_p
+    ad_connect  tx_frame_out_n axi_ad9361/tx_frame_out_n
+    ad_connect  tx_data_out_p axi_ad9361/tx_data_out_p
+    ad_connect  tx_data_out_n axi_ad9361/tx_data_out_n
+
+    return
+  }
+
+  if {$cmos_or_lvds eq "CMOS"} {
+
+    set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
+
+    create_bd_port -dir I rx_clk_in
+    create_bd_port -dir I rx_frame_in
+    create_bd_port -dir I -from 11 -to 0 rx_data_in
+    create_bd_port -dir O tx_clk_out
+    create_bd_port -dir O tx_frame_out
+    create_bd_port -dir O -from 11 -to 0 tx_data_out
+
+    ad_connect  rx_clk_in axi_ad9361/rx_clk_in
+    ad_connect  rx_frame_in axi_ad9361/rx_frame_in
+    ad_connect  rx_data_in axi_ad9361/rx_data_in
+    ad_connect  tx_clk_out axi_ad9361/tx_clk_out
+    ad_connect  tx_frame_out axi_ad9361/tx_frame_out
+    ad_connect  tx_data_out axi_ad9361/tx_data_out
+
+    return
+  }
+
+}
+
 
diff --git a/projects/pzsdr2/common/pzsdr2_constr.xdc b/projects/pzsdr2/common/pzsdr2_constr.xdc
index a5681880f..f7c98d224 100644
--- a/projects/pzsdr2/common/pzsdr2_constr.xdc
+++ b/projects/pzsdr2/common/pzsdr2_constr.xdc
@@ -31,8 +31,8 @@ set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports clkout_in
 
 # iic (ccbrk with loopback drives i2c back to the FPGA)
 
-set_property  -dict {PACKAGE_PIN  AF24 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L5P_T0_13                 U1,AF24,SCL,JX2,17,I2C_SCL,P2,14,P2,4,U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4
-set_property  -dict {PACKAGE_PIN  AF25 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L5N_T0_13                 U1,AF25,SDA,JX2,19,I2C_SDA,P2,16,P2,15,U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15
+set_property  -dict {PACKAGE_PIN  AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L5P_T0_13                 U1,AF24,SCL,JX2,17,I2C_SCL,P2,14,P2,4,U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4
+set_property  -dict {PACKAGE_PIN  AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L5N_T0_13                 U1,AF25,SDA,JX2,19,I2C_SDA,P2,16,P2,15,U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15
 
 ##    reference-only
 ##    --------------

From 5e6b931150dff88359631890052ab90af04893b4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 09:28:33 -0500
Subject: [PATCH 714/972] ccbox- added

---
 projects/pzsdr2/ccbox_lvds/Makefile           |  82 ++++++
 projects/pzsdr2/ccbox_lvds/system_bd.tcl      |   6 +
 projects/pzsdr2/ccbox_lvds/system_project.tcl |  18 ++
 projects/pzsdr2/ccbox_lvds/system_top.v       | 247 ++++++++++++++++++
 projects/pzsdr2/common/ccbox_bd.tcl           |  46 ++++
 5 files changed, 399 insertions(+)
 create mode 100644 projects/pzsdr2/ccbox_lvds/Makefile
 create mode 100644 projects/pzsdr2/ccbox_lvds/system_bd.tcl
 create mode 100644 projects/pzsdr2/ccbox_lvds/system_project.tcl
 create mode 100644 projects/pzsdr2/ccbox_lvds/system_top.v
 create mode 100644 projects/pzsdr2/common/ccbox_bd.tcl

diff --git a/projects/pzsdr2/ccbox_lvds/Makefile b/projects/pzsdr2/ccbox_lvds/Makefile
new file mode 100644
index 000000000..5373dd43a
--- /dev/null
+++ b/projects/pzsdr2/ccbox_lvds/Makefile
@@ -0,0 +1,82 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr2_constr_lvds.xdc
+M_DEPS += ../common/pzsdr2_constr.xdc
+M_DEPS += ../common/pzsdr2_bd.tcl
+M_DEPS += ../common/ccbrk_constr.xdc
+M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib pzsdr2_ccbrk_lvds.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/xilinx/axi_xcvrlb clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+pzsdr2_ccbrk_lvds.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> pzsdr2_ccbrk_lvds_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_gpreg
+	make -C ../../../library/xilinx/axi_xcvrlb
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/pzsdr2/ccbox_lvds/system_bd.tcl b/projects/pzsdr2/ccbox_lvds/system_bd.tcl
new file mode 100644
index 000000000..3c050c45d
--- /dev/null
+++ b/projects/pzsdr2/ccbox_lvds/system_bd.tcl
@@ -0,0 +1,6 @@
+
+source ../common/pzsdr2_bd.tcl
+source ../common/ccbrk_bd.tcl
+
+cfg_ad9361_interface LVDS
+
diff --git a/projects/pzsdr2/ccbox_lvds/system_project.tcl b/projects/pzsdr2/ccbox_lvds/system_project.tcl
new file mode 100644
index 000000000..8dc9a290f
--- /dev/null
+++ b/projects/pzsdr2/ccbox_lvds/system_project.tcl
@@ -0,0 +1,18 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+set p_device "xc7z035ifbg676-2L"
+adi_project_create pzsdr2_ccbrk_lvds
+adi_project_files pzsdr2_ccbrk_lvds [list \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "../common/pzsdr2_constr.xdc" \
+  "../common/pzsdr2_constr_lvds.xdc" \
+  "../common/ccbrk_constr.xdc" \
+  "system_top.v" ]
+
+set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
+adi_project_run pzsdr2_ccbrk_lvds
+
+
diff --git a/projects/pzsdr2/ccbox_lvds/system_top.v b/projects/pzsdr2/ccbox_lvds/system_top.v
new file mode 100644
index 000000000..167b4a465
--- /dev/null
+++ b/projects/pzsdr2/ccbox_lvds/system_top.v
@@ -0,0 +1,247 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout           iic_scl,
+  inout           iic_sda,
+
+  inout   [19:0]  gpio_bd,
+
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
+
+  output          enable,
+  output          txnrx,
+  input           clkout_in,
+  output          clkout_out,
+
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
+
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso,
+
+  output  [85:0]  gp_out,
+  input   [85:0]  gp_in,
+
+  input           gt_ref_clk_p,
+  input           gt_ref_clk_n,
+  output  [ 3:0]  gt_tx_p,
+  output  [ 3:0]  gt_tx_n,
+  input   [ 3:0]  gt_rx_p,
+  input   [ 3:0]  gt_rx_n);
+
+  // internal signals
+
+  wire            gt_ref_clk;
+  wire    [95:0]  gp_out_s;
+  wire    [95:0]  gp_in_s;
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+
+  assign clkout_out = clkout_in;
+  assign gp_out[85:0] = gp_out_s[85:0];
+  assign gp_in_s[95:86] = gp_out_s[95:86];
+  assign gp_in_s[85: 0] = gp_in[85:0];
+
+  // instantiations
+
+  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
+    .CEB (1'd0),
+    .I (gt_ref_clk_p),
+    .IB (gt_ref_clk_n),
+    .O (gt_ref_clk),
+    .ODIV2 ());
+
+  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
+    .dio_t ({gpio_t[51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[51], gpio_i[46:32]}),
+    .dio_p ({ gpio_clksel,        // 51:51
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
+    .dio_t (gpio_t[19:0]),
+    .dio_i (gpio_o[19:0]),
+    .dio_o (gpio_i[19:0]),
+    .dio_p (gpio_bd));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gp_in_0 (gp_in_s[31:0]),
+    .gp_in_1 (gp_in_s[63:32]),
+    .gp_in_2 (gp_in_s[95:64]),
+    .gp_in_3 (32'd0),
+    .gp_out_0 (gp_out_s[31:0]),
+    .gp_out_1 (gp_out_s[63:32]),
+    .gp_out_2 (gp_out_s[95:64]),
+    .gp_out_3 (),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .gt_ref_clk (gt_ref_clk),
+    .gt_rx_n (gt_rx_n),
+    .gt_rx_p (gt_rx_p),
+    .gt_tx_n (gt_tx_n),
+    .gt_tx_p (gt_tx_p),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .otg_vbusoc (1'b0),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/pzsdr2/common/ccbox_bd.tcl b/projects/pzsdr2/common/ccbox_bd.tcl
new file mode 100644
index 000000000..a60e9dd58
--- /dev/null
+++ b/projects/pzsdr2/common/ccbox_bd.tcl
@@ -0,0 +1,46 @@
+
+# unused
+
+ad_connect  sys_ps7/ENET1_GMII_RX_CLK GND
+ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
+
+# GPS-UART
+
+set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USE_DMA2 1 [get_bd_cells sys_ps7]
+
+# i2s
+
+create_bd_port -dir O -type clk i2s_mclk
+create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
+
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
+set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
+
+set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
+set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
+set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
+
+ad_connect  sys_200m_clk sys_audio_clkgen/clk_in1
+ad_connect  sys_cpu_resetn sys_audio_clkgen/resetn
+ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
+ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA1_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA2_ACLK
+ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
+ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
+ad_connect  sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
+ad_connect  sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
+ad_connect  sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
+ad_connect  sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
+ad_connect  sys_audio_clkgen/clk_out1 i2s_mclk
+ad_connect  sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
+ad_connect  i2s axi_i2s_adi/I2S
+
+ad_cpu_interconnect 0x77600000 axi_i2s_adi
+

From c2b7cbd61b365d604159d2a36e295f014c7f38a2 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 10:23:51 -0500
Subject: [PATCH 715/972] ccbox- constraints

---
 projects/pzsdr2/common/ccbox_constr.xdc | 76 +++++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 projects/pzsdr2/common/ccbox_constr.xdc

diff --git a/projects/pzsdr2/common/ccbox_constr.xdc b/projects/pzsdr2/common/ccbox_constr.xdc
new file mode 100644
index 000000000..94ffc8f27
--- /dev/null
+++ b/projects/pzsdr2/common/ccbox_constr.xdc
@@ -0,0 +1,76 @@
+
+## constraints (ccbox.a)
+## rf-gpio
+
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable]  ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,RF_GPIO4_BANK34
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports gpio_rf0]           ; ## U1,G5,IO_L02_34_JX4_N,JX4,22,RF_GPIO0_BANK34
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports gpio_rf1]           ; ## U1,H9,IO_L03_34_JX4_P,JX4,25,RF_GPIO1_BANK34
+set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD LVCMOS18} [get_ports gpio_rf2]           ; ## U1,J9,IO_L05_34_JX4_N,JX4,33,RF_GPIO2_BANK34
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD LVCMOS18} [get_ports gpio_rf3]           ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,RF_GPIO3_BANK34
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD LVCMOS18} [get_ports gpio_rf4]           ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,RF_GPIO5_BANK34
+
+## push-button
+
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD  LVCMOS18} [get_ports  ltc2955_kill_n]   ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,LTC2955_KILL_N
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD  LVCMOS18} [get_ports  ltc2955_int_n]    ; ## U1,J10,IO_L05_34_JX4_P,JX4,31,LTC2955_INT_N
+
+## oled
+
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD  LVCMOS25} [get_ports  oled_csn]         ; ## U1,AA24,IO_L06_13_JX2_P,JX2,18,OLED_CS#
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD  LVCMOS25} [get_ports  oled_clk]         ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,OLED_SCL
+set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD  LVCMOS25} [get_ports  oled_mosi]        ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,OLED_SDI
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD  LVCMOS25} [get_ports  oled_rst]         ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,OLED_/RES
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD  LVCMOS25} [get_ports  oled_dc]          ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,OLED_D/C
+
+## adp5061
+
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD  LVCMOS18} [get_ports  adp5061_io[0]]    ; ## U1,J11,IO_L01_34_JX4_P,JX4,19,ADP5061_IO1
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD  LVCMOS18} [get_ports  adp5061_io[1]]    ; ## U1,H11,IO_L01_34_JX4_N,JX4,21,ADP5061_IO2
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD  LVCMOS18} [get_ports  adp5061_io[2]]    ; ## U1,G6,IO_L02_34_JX4_P,JX4,20,ADP5061_IO3
+
+## GPS (DATA-UART)
+## U1,D23,PS_MIO14_500_JX4,JX4,93,GPS_TXD1_1V8
+## U1,C24,PS_MIO15_500_JX4,JX4,85,GPS_RXD1_1V8
+
+set_property  -dict {PACKAGE_PIN  Y20   IOSTANDARD  LVCMOS25} [get_ports  gps_reset]        ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,GPS_RESET
+set_property  -dict {PACKAGE_PIN  AA20  IOSTANDARD  LVCMOS25} [get_ports  gps_force_on]     ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,GPS_FORCE_ON
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD  LVCMOS25} [get_ports  gps_standby]      ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,GPS_STANDBY
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gps_pps]          ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,GPS_PPS
+
+## imu
+
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD  LVCMOS25} [get_ports  imu_csn]          ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IMU_CS_N
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD  LVCMOS25} [get_ports  imu_clk]          ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IMU_SCLK
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD  LVCMOS25} [get_ports  imu_mosi]         ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IMU_DIN
+set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD  LVCMOS25} [get_ports  imu_miso]         ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IMU_DOUT
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD  LVCMOS25} [get_ports  imu_rstn]         ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IMU_RST_N
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD  LVCMOS25} [get_ports  imu_sync]         ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IMU_SYNC
+set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD  LVCMOS25} [get_ports  imu_ready]        ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IMU_DR
+
+## audio
+
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD  LVCMOS25} [get_ports  i2s_bclk]         ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,AUD_BCLK
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD  LVCMOS25} [get_ports  i2s_lrclk]        ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,AUD_LRCLK
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD  LVCMOS25} [get_ports  i2s_mclk]         ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,AUD_MCLK
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD  LVCMOS25} [get_ports  i2s_sdata_in]     ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,AUD_SDATA_IN
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD  LVCMOS25} [get_ports  i2s_sdata_out]    ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,AUD_SDATA_OUT
+
+set_property  -dict {PACKAGE_PIN  E8    IOSTANDARD  LVCMOS18} [get_ports  mic_present_n]    ; ## U1,E8,IO_L09_34_JX4_N,JX4,43,MIC_PRESENT_N_1V8
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD  LVCMOS18} [get_ports  ts3a227_int_n]    ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,TS3A227_INT_N
+
+## switch-led
+
+set_property  -dict {PACKAGE_PIN  D8    IOSTANDARD  LVCMOS18} [get_ports  switch_led_r]     ; ## U1,D8,IO_L08_34_JX4_N,JX4,38,SWITCH_LED_R
+set_property  -dict {PACKAGE_PIN  F9    IOSTANDARD  LVCMOS18} [get_ports  switch_led_g]     ; ## U1,F9,IO_L09_34_JX4_P,JX4,41,SWITCH_LED_G
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD  LVCMOS18} [get_ports  switch_led_b]     ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,SWITCH_LED_B
+
+## power source
+
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD  LVCMOS18} [get_ports  pss_valid_n[0]]   ; ## U1,G9,IO_L03_34_JX4_N,JX4,27,PSS_VALID1_N
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD  LVCMOS18} [get_ports  pss_valid_n[1]]   ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,PSS_VALID2_N
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD  LVCMOS18} [get_ports  pss_valid_n[2]]   ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,PSS_VALID3_N
+
+## misc
+
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD  LVCMOS25} [get_ports  otg_ctrl]         ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,OTG_CTRL
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD  LVCMOS25} [get_ports  adp1614_en]       ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,ADP1614_EN

From d0166a4c7e0664d87d941e0b169f5f6068afbc03 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 10:24:11 -0500
Subject: [PATCH 716/972] ccbox- updates

---
 projects/pzsdr2/ccbox_lvds/system_bd.tcl      |   2 +-
 projects/pzsdr2/ccbox_lvds/system_project.tcl |   9 +-
 projects/pzsdr2/ccbox_lvds/system_top.v       | 188 ++++++++++++------
 3 files changed, 136 insertions(+), 63 deletions(-)

diff --git a/projects/pzsdr2/ccbox_lvds/system_bd.tcl b/projects/pzsdr2/ccbox_lvds/system_bd.tcl
index 3c050c45d..739e5a097 100644
--- a/projects/pzsdr2/ccbox_lvds/system_bd.tcl
+++ b/projects/pzsdr2/ccbox_lvds/system_bd.tcl
@@ -1,6 +1,6 @@
 
 source ../common/pzsdr2_bd.tcl
-source ../common/ccbrk_bd.tcl
+source ../common/ccbox_bd.tcl
 
 cfg_ad9361_interface LVDS
 
diff --git a/projects/pzsdr2/ccbox_lvds/system_project.tcl b/projects/pzsdr2/ccbox_lvds/system_project.tcl
index 8dc9a290f..8211b8ea2 100644
--- a/projects/pzsdr2/ccbox_lvds/system_project.tcl
+++ b/projects/pzsdr2/ccbox_lvds/system_project.tcl
@@ -4,15 +4,14 @@ source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 set p_device "xc7z035ifbg676-2L"
-adi_project_create pzsdr2_ccbrk_lvds
-adi_project_files pzsdr2_ccbrk_lvds [list \
+adi_project_create pzsdr2_ccbox_lvds
+adi_project_files pzsdr2_ccbox_lvds [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "../common/pzsdr2_constr.xdc" \
   "../common/pzsdr2_constr_lvds.xdc" \
-  "../common/ccbrk_constr.xdc" \
+  "../common/ccbox_constr.xdc" \
   "system_top.v" ]
 
-set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
-adi_project_run pzsdr2_ccbrk_lvds
+adi_project_run pzsdr2_ccbox_lvds
 
 
diff --git a/projects/pzsdr2/ccbox_lvds/system_top.v b/projects/pzsdr2/ccbox_lvds/system_top.v
index 167b4a465..6f1245eae 100644
--- a/projects/pzsdr2/ccbox_lvds/system_top.v
+++ b/projects/pzsdr2/ccbox_lvds/system_top.v
@@ -65,7 +65,44 @@ module system_top (
   inout           iic_scl,
   inout           iic_sda,
 
-  inout   [19:0]  gpio_bd,
+  output          i2s_mclk,
+  output          i2s_bclk,
+  output          i2s_lrclk,
+  output          i2s_sdata_out,
+  input           i2s_sdata_in,
+
+  output          imu_csn,
+  output          imu_clk,
+  output          imu_mosi,
+  input           imu_miso,
+  input           imu_ready,
+  output          imu_rstn,
+  inout           imu_sync,
+
+  output          oled_csn,
+  output          oled_clk,
+  output          oled_mosi,
+  output          oled_rst,
+  output          oled_dc,
+
+  output          switch_led_r,
+  output          switch_led_g,
+  output          switch_led_b,
+
+  output          gps_reset,
+  output          gps_force_on,
+  output          gps_standby,
+  input           gps_pps,
+
+  input   [ 2:0]  pss_valid_n,
+  inout   [ 2:0]  adp5061_io,
+
+  inout           otg_ctrl,
+  inout           adp1614_en,
+  inout           ltc2955_kill_n,
+  inout           ltc2955_int_n,
+  inout           mic_present_n,
+  inout           ts3a227_int_n,
 
   input           rx_clk_in_p,
   input           rx_clk_in_n,
@@ -83,8 +120,13 @@ module system_top (
   output          enable,
   output          txnrx,
   input           clkout_in,
-  output          clkout_out,
 
+  inout           gpio_rf0,
+  inout           gpio_rf1,
+  inout           gpio_rf2,
+  inout           gpio_rf3,
+  inout           gpio_rf4,
+  inout           gpio_rfpwr_enable,
   inout           gpio_clksel,
   inout           gpio_resetb,
   inout           gpio_sync,
@@ -95,59 +137,99 @@ module system_top (
   output          spi_csn,
   output          spi_clk,
   output          spi_mosi,
-  input           spi_miso,
-
-  output  [85:0]  gp_out,
-  input   [85:0]  gp_in,
-
-  input           gt_ref_clk_p,
-  input           gt_ref_clk_n,
-  output  [ 3:0]  gt_tx_p,
-  output  [ 3:0]  gt_tx_n,
-  input   [ 3:0]  gt_rx_p,
-  input   [ 3:0]  gt_rx_n);
+  input           spi_miso);
 
   // internal signals
 
-  wire            gt_ref_clk;
-  wire    [95:0]  gp_out_s;
-  wire    [95:0]  gp_in_s;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
   // assignments
 
-  assign clkout_out = clkout_in;
-  assign gp_out[85:0] = gp_out_s[85:0];
-  assign gp_in_s[95:86] = gp_out_s[95:86];
-  assign gp_in_s[85: 0] = gp_in[85:0];
+  assign oled_clk = spi_clk;
+  assign oled_mosi = spi_mosi;
 
-  // instantiations
+  // gpio[31:20] controls misc stuff (keep as io)
 
-  IBUFDS_GTE2 i_ibufds_gt_ref_clk (
-    .CEB (1'd0),
-    .I (gt_ref_clk_p),
-    .IB (gt_ref_clk_n),
-    .O (gt_ref_clk),
-    .ODIV2 ());
+  assign gpio_i[31:26] = gpio_o[31:26];
 
-  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
-    .dio_t ({gpio_t[51], gpio_t[46:32]}),
-    .dio_i ({gpio_o[51], gpio_o[46:32]}),
-    .dio_o ({gpio_i[51], gpio_i[46:32]}),
-    .dio_p ({ gpio_clksel,        // 51:51
+  ad_iobuf #(.DATA_WIDTH(6)) i_iobuf_misc (
+    .dio_t (gpio_t[25:20]),
+    .dio_i (gpio_o[25:20]),
+    .dio_o (gpio_i[25:20]),
+    .dio_p ({ adp1614_en,
+              otg_ctrl,
+              ltc2955_kill_n,
+              ltc2955_int_n,
+              ts3a227_int_n,
+              mic_present_n}));
+
+  // gpio[19:16] controls adp5061 (keep as io)
+
+  assign gpio_i[19] = gpio_o[19];
+
+  ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_adp5061 (
+    .dio_t (gpio_t[18:16]),
+    .dio_i (gpio_o[18:16]),
+    .dio_o (gpio_i[18:16]),
+    .dio_p (adp5061_io));
+
+  // gpio[15:12] reads power source select valids
+
+  assign gpio_i[15:12] = {gpio_o[15], pss_valid_n};
+
+  // gpio[11:8] controls the imu/oled reset & such.
+
+  assign oled_dc = gpio_o[11];
+  assign oled_rst = gpio_o[10];
+  assign imu_rstn = gpio_o[9];
+  assign gpio_i[11:9] = gpio_o[11:9];
+
+  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_imu_sync (
+    .dio_t (gpio_t[8]),
+    .dio_i (gpio_o[8]),
+    .dio_o (gpio_i[8]),
+    .dio_p (imu_sync));
+
+  // gpio[7:4] controls the gps
+
+  assign gps_reset = gpio_o[6];
+  assign gps_force_on = gpio_o[5];
+  assign gps_standby = gpio_o[4];
+  assign gpio_i[7:4] = {gps_pps, gpio_o[6:4]};
+
+  // gpio[3:0] controls the power switch led colors
+
+  assign switch_led_r = gpio_o[2];
+  assign switch_led_g = gpio_o[1];
+  assign switch_led_b = gpio_o[0];
+  assign gpio_i[3:0] = gpio_o[3:0];
+
+  // ad9361 gpio - 63-32
+
+  assign gpio_i[63:62] = gpio_o[63:62];
+  assign gpio_i[60:57] = gpio_o[60:57];
+  assign gpio_i[50:47] = gpio_o[50:47];
+
+  ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
+    .dio_t ({gpio_t[61:61], gpio_t[56:51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[61:61], gpio_o[56:51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[61:61], gpio_i[56:51], gpio_i[46:32]}),
+    .dio_p ({ gpio_rf4,           // 61:61
+              gpio_rf0,           // 56:56
+              gpio_rf1,           // 55:55
+              gpio_rf2,           // 54:54
+              gpio_rf3,           // 53:53
+              gpio_rfpwr_enable,  // 52:52
+              gpio_clksel,        // 51:51
               gpio_resetb,        // 46:46
               gpio_sync,          // 45:45
               gpio_en_agc,        // 44:44
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
-    .dio_t (gpio_t[19:0]),
-    .dio_i (gpio_o[19:0]),
-    .dio_o (gpio_i[19:0]),
-    .dio_p (gpio_bd));
+  // instantiations
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
@@ -172,26 +254,18 @@ module system_top (
     .fixed_io_ps_clk (fixed_io_ps_clk),
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gp_in_0 (gp_in_s[31:0]),
-    .gp_in_1 (gp_in_s[63:32]),
-    .gp_in_2 (gp_in_s[95:64]),
-    .gp_in_3 (32'd0),
-    .gp_out_0 (gp_out_s[31:0]),
-    .gp_out_1 (gp_out_s[63:32]),
-    .gp_out_2 (gp_out_s[95:64]),
-    .gp_out_3 (),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .gt_ref_clk (gt_ref_clk),
-    .gt_rx_n (gt_rx_n),
-    .gt_rx_p (gt_rx_p),
-    .gt_tx_n (gt_tx_n),
-    .gt_tx_p (gt_tx_p),
+    .i2s_bclk (i2s_bclk),
+    .i2s_lrclk (i2s_lrclk),
+    .i2s_mclk (i2s_mclk),
+    .i2s_sdata_in (i2s_sdata_in),
+    .i2s_sdata_out (i2s_sdata_out),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
-    .ps_intr_00 (1'b0),
+    .ps_intr_00 (imu_ready),
     .ps_intr_01 (1'b0),
     .ps_intr_02 (1'b0),
     .ps_intr_03 (1'b0),
@@ -213,22 +287,22 @@ module system_top (
     .spi0_clk_i (1'b0),
     .spi0_clk_o (spi_clk),
     .spi0_csn_0_o (spi_csn),
-    .spi0_csn_1_o (),
+    .spi0_csn_1_o (oled_csn),
     .spi0_csn_2_o (),
     .spi0_csn_i (1'b1),
     .spi0_sdi_i (spi_miso),
     .spi0_sdo_i (1'b0),
     .spi0_sdo_o (spi_mosi),
     .spi1_clk_i (1'b0),
-    .spi1_clk_o (),
-    .spi1_csn_0_o (),
+    .spi1_clk_o (imu_clk),
+    .spi1_csn_0_o (imu_csn),
     .spi1_csn_1_o (),
     .spi1_csn_2_o (),
     .spi1_csn_i (1'b1),
-    .spi1_sdi_i (1'b0),
+    .spi1_sdi_i (imu_miso),
     .spi1_sdo_i (1'b0),
-    .spi1_sdo_o (),
-    .tdd_sync_i (1'b0),
+    .spi1_sdo_o (imu_mosi),
+    .tdd_sync_i (gps_pps),
     .tdd_sync_o (),
     .tdd_sync_t (),
     .tx_clk_out_n (tx_clk_out_n),

From 74bf4dfb801ba1409ed79a526a6382fcf55f0fce Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 10:24:50 -0500
Subject: [PATCH 717/972] pzsdr2- gpio- turn-around

---
 projects/pzsdr2/ccbrk_cmos/system_top.v | 21 ++++++++++++++++-----
 projects/pzsdr2/ccbrk_lvds/system_top.v | 21 ++++++++++++++++-----
 projects/pzsdr2/ccfmc_lvds/system_top.v | 22 +++++++++++++++++-----
 3 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/projects/pzsdr2/ccbrk_cmos/system_top.v b/projects/pzsdr2/ccbrk_cmos/system_top.v
index bdaabf177..56fecd808 100644
--- a/projects/pzsdr2/ccbrk_cmos/system_top.v
+++ b/projects/pzsdr2/ccbrk_cmos/system_top.v
@@ -128,6 +128,21 @@ module system_top (
     .O (gt_ref_clk),
     .ODIV2 ());
 
+  // board gpio - 31-0
+
+  assign gpio_i[31:20] = gpio_o[31:20];
+
+  ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
+    .dio_t (gpio_t[19:0]),
+    .dio_i (gpio_o[19:0]),
+    .dio_o (gpio_i[19:0]),
+    .dio_p (gpio_bd));
+
+  // ad9361 gpio - 63-32
+
+  assign gpio_i[63:52] = gpio_o[63:52];
+  assign gpio_i[50:47] = gpio_o[50:47];
+
   ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
     .dio_t ({gpio_t[51], gpio_t[46:32]}),
     .dio_i ({gpio_o[51], gpio_o[46:32]}),
@@ -139,11 +154,7 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
-    .dio_t (gpio_t[19:0]),
-    .dio_i (gpio_o[19:0]),
-    .dio_o (gpio_i[19:0]),
-    .dio_p (gpio_bd));
+  // instantiations
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
diff --git a/projects/pzsdr2/ccbrk_lvds/system_top.v b/projects/pzsdr2/ccbrk_lvds/system_top.v
index 167b4a465..4abf4b607 100644
--- a/projects/pzsdr2/ccbrk_lvds/system_top.v
+++ b/projects/pzsdr2/ccbrk_lvds/system_top.v
@@ -132,6 +132,21 @@ module system_top (
     .O (gt_ref_clk),
     .ODIV2 ());
 
+  // board gpio - 31-0
+
+  assign gpio_i[31:20] = gpio_o[31:20];
+
+  ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
+    .dio_t (gpio_t[19:0]),
+    .dio_i (gpio_o[19:0]),
+    .dio_o (gpio_i[19:0]),
+    .dio_p (gpio_bd));
+
+  // ad9361 gpio - 63-32
+
+  assign gpio_i[63:52] = gpio_o[63:52];
+  assign gpio_i[50:47] = gpio_o[50:47];
+
   ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
     .dio_t ({gpio_t[51], gpio_t[46:32]}),
     .dio_i ({gpio_o[51], gpio_o[46:32]}),
@@ -143,11 +158,7 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
-    .dio_t (gpio_t[19:0]),
-    .dio_i (gpio_o[19:0]),
-    .dio_o (gpio_i[19:0]),
-    .dio_p (gpio_bd));
+  // instantiations
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
diff --git a/projects/pzsdr2/ccfmc_lvds/system_top.v b/projects/pzsdr2/ccfmc_lvds/system_top.v
index 83e24317f..8c8c9f891 100644
--- a/projects/pzsdr2/ccfmc_lvds/system_top.v
+++ b/projects/pzsdr2/ccfmc_lvds/system_top.v
@@ -188,6 +188,7 @@ module system_top (
   assign ad9517_mosi = spi_mosi_s;
   assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); 
 
+  // loopback signals
 
   assign gp_out[53:0] = gp_out_s[53:0];
   assign gp_in_s[63:54] = gp_out_s[63:54];
@@ -225,6 +226,21 @@ module system_top (
     .dio_o (tdd_sync_i),
     .dio_p (tdd_sync));
 
+  // board gpio - 31-0
+
+  assign gpio_i[31:21] = gpio_o[31:21];
+
+  ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
+    .dio_t (gpio_t[20:0]),
+    .dio_i (gpio_o[20:0]),
+    .dio_o (gpio_i[20:0]),
+    .dio_p (gpio_bd));
+
+  // ad9361 gpio - 63-32
+
+  assign gpio_i[63:62] = gpio_o[63:62];
+  assign gpio_i[50:47] = gpio_o[50:47];
+
   ad_iobuf #(.DATA_WIDTH(26)) i_iobuf (
     .dio_t ({gpio_t[61:51], gpio_t[46:32]}),
     .dio_i ({gpio_o[61:51], gpio_o[46:32]}),
@@ -246,11 +262,7 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
-    .dio_t (gpio_t[20:0]),
-    .dio_i (gpio_o[20:0]),
-    .dio_o (gpio_i[20:0]),
-    .dio_p (gpio_bd));
+  // instantiations
 
   system_wrapper i_system_wrapper (
     .clk_0 (clk_0),

From 778638a7a180cf384fe1ddf66f393148fd5ce602 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 10:26:45 -0500
Subject: [PATCH 718/972] pzsdr2- make updates

---
 projects/pzsdr2/Makefile            |  3 +++
 projects/pzsdr2/ccbox_lvds/Makefile | 19 ++++++++-----------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/projects/pzsdr2/Makefile b/projects/pzsdr2/Makefile
index 3d58fa671..bd4b8e2da 100644
--- a/projects/pzsdr2/Makefile
+++ b/projects/pzsdr2/Makefile
@@ -7,6 +7,7 @@
 
 .PHONY: all clean clean-all 
 all:
+	-make -C ccbox_lvds all
 	-make -C ccbrk_cmos all
 	-make -C ccbrk_lvds all
 	-make -C ccfmc_lvds all
@@ -15,6 +16,7 @@ all:
 
 
 clean: 
+	make -C ccbox_lvds clean
 	make -C ccbrk_cmos clean
 	make -C ccbrk_lvds clean
 	make -C ccfmc_lvds clean
@@ -23,6 +25,7 @@ clean:
 
 
 clean-all:
+	make -C ccbox_lvds clean-all
 	make -C ccbrk_cmos clean-all
 	make -C ccbrk_lvds clean-all
 	make -C ccfmc_lvds clean-all
diff --git a/projects/pzsdr2/ccbox_lvds/Makefile b/projects/pzsdr2/ccbox_lvds/Makefile
index 5373dd43a..114c11828 100644
--- a/projects/pzsdr2/ccbox_lvds/Makefile
+++ b/projects/pzsdr2/ccbox_lvds/Makefile
@@ -11,16 +11,15 @@ M_DEPS += system_bd.tcl
 M_DEPS += ../common/pzsdr2_constr_lvds.xdc
 M_DEPS += ../common/pzsdr2_constr.xdc
 M_DEPS += ../common/pzsdr2_bd.tcl
-M_DEPS += ../common/ccbrk_constr.xdc
-M_DEPS += ../common/ccbrk_bd.tcl
+M_DEPS += ../common/ccbox_constr.xdc
+M_DEPS += ../common/ccbox_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
-M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
+M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
@@ -45,7 +44,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib pzsdr2_ccbrk_lvds.sdk/system_top.hdf
+all: lib pzsdr2_ccbox_lvds.sdk/system_top.hdf
 
 
 clean: 
@@ -55,24 +54,22 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_gpreg clean
-	make -C ../../../library/xilinx/axi_xcvrlb clean
+	make -C ../../../library/axi_i2s_adi clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
 
 
-pzsdr2_ccbrk_lvds.sdk/system_top.hdf: $(M_DEPS)
+pzsdr2_ccbox_lvds.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> pzsdr2_ccbrk_lvds_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr2_ccbox_lvds_vivado.log 2>&1
 
 
 lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_gpreg
-	make -C ../../../library/xilinx/axi_xcvrlb
+	make -C ../../../library/axi_i2s_adi
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack

From 4dae754287dbfc292a53a11a9bbef55acdf103dd Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 11:29:01 -0500
Subject: [PATCH 719/972] pzsdr1- added readme

---
 projects/pzsdr1/README.md | 48 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 projects/pzsdr1/README.md

diff --git a/projects/pzsdr1/README.md b/projects/pzsdr1/README.md
new file mode 100644
index 000000000..e59185903
--- /dev/null
+++ b/projects/pzsdr1/README.md
@@ -0,0 +1,48 @@
+# PicoZed SDR SOM (PZSDR2)
+
+This folder contains the PZSDR2 SOM projects for each of the carrier boards.
+
+## Board Design Files
+
+| Directory/File       | Description                            |
+|----------------------|----------------------------------------|
+| common/pzsdr2_bd.tcl | pzsdr2 SOM module board design file.   |
+| common/ccbrk_bd.tcl  | carrier, break out board design file.  |
+| common/ccfmc_bd.tcl  | carrier, fmc board design file.        |
+| common/ccpci_bd.tcl  | carrier, pci-e board design file.      |
+| common/ccusb_bd.tcl  | carrier, usb board design file.        |
+
+FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
+
+## Board Constraint Files
+
+| Directory/File                | Description                                   |
+|-------------------------------|-----------------------------------------------|
+| common/pzsdr2_constr.xdc      | pzsdr2 SOM base constraints file.             |
+| common/pzsdr2_constr_cmos.xdc | pzsdr2 SOM CMOS mode constraints file.        |
+| common/pzsdr2_constr_lvds.xdc | pzsdr2 SOM LVDS mode constraints file.        |
+| common/ccbrk_constr.xdc       | carrier, break out board constraints file.    |
+| common/ccfmc_constr.xdc       | carrier, fmc board constraints file.          |
+| common/ccpci_constr.xdc       | carrier, pci-e board constraints file.        |
+| common/ccusb_constr.xdc       | carrier, usb board constraints file.          |
+
+FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
+
+## Building, Generating Bit Files
+
+[pzsdr2] cd ccbrk_cmos
+
+[pzsdr2/ccbrk_cmos] make
+
+The make in each carrier directory builds the corresponding project. The above example builds PZSDR2-CCBRK hardware bit files in CMOS mode.
+
+## Documentation
+
+ * [HDL Design User Guide]
+ * [IP User Guide]
+ * [PZSDR2 Wiki page]
+ 
+[HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl
+[IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361 
+[PZSDR2 Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr
+

From 8c25402d532a44b1da4704ca07a72e2bf470eec2 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 13:40:04 -0500
Subject: [PATCH 720/972] pzsdr1- common files

---
 projects/pzsdr1/common/pzsdr1_bd.tcl          | 427 ++++++++++++++++++
 projects/pzsdr1/common/pzsdr1_constr.xdc      | 188 ++++++++
 projects/pzsdr1/common/pzsdr1_constr_cmos.xdc |  42 ++
 projects/pzsdr1/common/pzsdr1_constr_lvds.xdc |  42 ++
 4 files changed, 699 insertions(+)
 create mode 100644 projects/pzsdr1/common/pzsdr1_bd.tcl
 create mode 100644 projects/pzsdr1/common/pzsdr1_constr.xdc
 create mode 100644 projects/pzsdr1/common/pzsdr1_constr_cmos.xdc
 create mode 100644 projects/pzsdr1/common/pzsdr1_constr_lvds.xdc

diff --git a/projects/pzsdr1/common/pzsdr1_bd.tcl b/projects/pzsdr1/common/pzsdr1_bd.tcl
new file mode 100644
index 000000000..4ab1d3de8
--- /dev/null
+++ b/projects/pzsdr1/common/pzsdr1_bd.tcl
@@ -0,0 +1,427 @@
+
+# create board design
+# default ports
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
+create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+
+create_bd_port -dir O spi0_csn_2_o
+create_bd_port -dir O spi0_csn_1_o
+create_bd_port -dir O spi0_csn_0_o
+create_bd_port -dir I spi0_csn_i
+create_bd_port -dir I spi0_clk_i
+create_bd_port -dir O spi0_clk_o
+create_bd_port -dir I spi0_sdo_i
+create_bd_port -dir O spi0_sdo_o
+create_bd_port -dir I spi0_sdi_i
+
+create_bd_port -dir O spi1_csn_2_o
+create_bd_port -dir O spi1_csn_1_o
+create_bd_port -dir O spi1_csn_0_o
+create_bd_port -dir I spi1_csn_i
+create_bd_port -dir I spi1_clk_i
+create_bd_port -dir O spi1_clk_o
+create_bd_port -dir I spi1_sdo_i
+create_bd_port -dir O spi1_sdo_o
+create_bd_port -dir I spi1_sdi_i
+
+create_bd_port -dir I -from 63 -to 0 gpio_i
+create_bd_port -dir O -from 63 -to 0 gpio_o
+create_bd_port -dir O -from 63 -to 0 gpio_t
+
+# otg
+
+set otg_vbusoc      [create_bd_port -dir I otg_vbusoc]
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_11
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+create_bd_port -dir I -type intr ps_intr_15
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PACKAGE_NAME {fbg676}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET_RESET_SELECT {Separate reset pins}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 8}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET1_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_ENET1_RESET_IO {MIO 51}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 50}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 7}] $sys_ps7
+set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.110}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.095}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.249}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.249}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.202}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.217}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.216}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.217}] $sys_ps7
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
+set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
+set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
+set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+
+# interface connections
+
+ad_connect  ddr sys_ps7/DDR
+ad_connect  gpio_i sys_ps7/GPIO_I
+ad_connect  gpio_o sys_ps7/GPIO_O
+ad_connect  gpio_t sys_ps7/GPIO_T
+ad_connect  fixed_io sys_ps7/FIXED_IO
+ad_connect  iic_main axi_iic_main/iic
+ad_connect  sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
+ad_connect  sys_logic_inv/Op1 otg_vbusoc
+
+# spi connections
+
+ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
+ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
+ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
+ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
+ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
+ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
+ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
+ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
+ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+
+ad_connect  spi1_csn_2_o sys_ps7/SPI1_SS2_O
+ad_connect  spi1_csn_1_o sys_ps7/SPI1_SS1_O
+ad_connect  spi1_csn_0_o sys_ps7/SPI1_SS_O
+ad_connect  spi1_csn_i sys_ps7/SPI1_SS_I
+ad_connect  spi1_clk_i sys_ps7/SPI1_SCLK_I
+ad_connect  spi1_clk_o sys_ps7/SPI1_SCLK_O
+ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
+ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
+ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
+
+# interrupts
+
+ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15 ps_intr_15
+ad_connect  sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
+ad_connect  sys_concat_intc/In13 ps_intr_13
+ad_connect  sys_concat_intc/In12 ps_intr_12
+ad_connect  sys_concat_intc/In11 ps_intr_11
+ad_connect  sys_concat_intc/In10 ps_intr_10
+ad_connect  sys_concat_intc/In9 ps_intr_09
+ad_connect  sys_concat_intc/In8 ps_intr_08
+ad_connect  sys_concat_intc/In7 ps_intr_07
+ad_connect  sys_concat_intc/In6 ps_intr_06
+ad_connect  sys_concat_intc/In5 ps_intr_05
+ad_connect  sys_concat_intc/In4 ps_intr_04
+ad_connect  sys_concat_intc/In3 ps_intr_03
+ad_connect  sys_concat_intc/In2 ps_intr_02
+ad_connect  sys_concat_intc/In1 ps_intr_01
+ad_connect  sys_concat_intc/In0 ps_intr_00
+
+# interconnects
+
+ad_cpu_interconnect 0x41600000 axi_iic_main
+
+# ad9361
+
+create_bd_port -dir O enable
+create_bd_port -dir O txnrx
+create_bd_port -dir I up_enable
+create_bd_port -dir I up_txnrx
+create_bd_port -dir O tdd_sync_o
+create_bd_port -dir I tdd_sync_i
+create_bd_port -dir O tdd_sync_t
+
+# ad9361 core
+
+set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
+set_property -dict [list CONFIG.ID {0}] $axi_ad9361
+set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {0}] $axi_ad9361
+
+set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
+
+set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_dac_upack
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack
+
+set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
+set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}]  $axi_ad9361_adc_dma
+
+set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_pack
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack
+
+set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo
+set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo
+set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
+set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
+
+set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
+set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
+
+# connections
+
+ad_connect  sys_200m_clk axi_ad9361/delay_clk
+ad_connect  axi_ad9361_clk axi_ad9361/l_clk
+ad_connect  axi_ad9361_clk axi_ad9361/clk
+ad_connect  enable axi_ad9361/enable
+ad_connect  txnrx axi_ad9361/txnrx
+ad_connect  up_enable axi_ad9361/up_enable
+ad_connect  up_txnrx axi_ad9361/up_txnrx
+ad_connect  axi_ad9361_clk util_ad9361_adc_fifo/din_clk
+ad_connect  axi_ad9361/rst util_ad9361_adc_fifo/din_rst
+ad_connect  sys_cpu_clk util_ad9361_adc_fifo/dout_clk
+ad_connect  sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
+ad_connect  sys_cpu_clk util_ad9361_adc_pack/adc_clk
+ad_connect  sys_cpu_reset util_ad9361_adc_pack/adc_rst
+ad_connect  sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
+ad_connect  axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
+ad_connect  axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
+ad_connect  axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
+ad_connect  axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
+ad_connect  axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
+ad_connect  axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
+ad_connect  axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
+ad_connect  axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
+ad_connect  axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
+ad_connect  axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
+ad_connect  axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
+ad_connect  util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
+ad_connect  util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
+ad_connect  util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
+ad_connect  util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
+ad_connect  util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
+ad_connect  util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
+ad_connect  util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
+ad_connect  util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
+ad_connect  util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
+ad_connect  util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
+ad_connect  util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
+ad_connect  util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
+ad_connect  util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
+ad_connect  util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
+ad_connect  util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
+ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
+ad_connect  util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
+ad_connect  axi_ad9361_clk util_ad9361_dac_upack/dac_clk
+ad_connect  axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
+ad_connect  util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
+ad_connect  util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
+ad_connect  util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
+ad_connect  util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
+ad_connect  util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
+ad_connect  util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
+ad_connect  util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
+ad_connect  util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
+ad_connect  util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
+ad_connect  util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
+ad_connect  util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
+ad_connect  util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
+ad_connect  util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
+ad_connect  util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
+ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
+ad_connect  sys_cpu_clk util_ad9361_tdd_sync/clk
+ad_connect  sys_cpu_resetn util_ad9361_tdd_sync/rstn
+ad_connect  util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
+ad_connect  util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
+ad_connect  tdd_sync_t axi_ad9361/tdd_sync_cntr
+ad_connect  tdd_sync_o util_ad9361_tdd_sync/sync_out
+ad_connect  tdd_sync_i util_ad9361_tdd_sync/sync_in
+
+# interconnects
+
+ad_cpu_interconnect 0x79020000 axi_ad9361
+ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
+ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
+ad_connect  sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
+ad_connect  sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
+
+# interrupts
+
+ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
+ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
+
+## customization of core to disable data path logic (less resources)
+## interface type - 1R1T (1) or 2R2T (0) (default is 2R2T)
+## 2R2T supports 1R1T as a run time option.
+## 1R1T allows core to run at a lower rate (1/2 of 2R2T)
+
+set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361] 
+
+## interface type - CMOS (1) or LVDS (0) (default is LVDS)
+## CMOS allows core to run at a lower rate (1/2 of LVDS)
+
+set_property CONFIG.CMOS_OR_LVDS_N 0  [get_bd_cells axi_ad9361]
+
+## data-path disable (global control)- allows removal of DSP functions within the core.
+## also removes the corresponding AXI control interface registers
+
+set_property CONFIG.ADC_DATAPATH_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.DAC_DATAPATH_DISABLE 0  [get_bd_cells axi_ad9361]
+
+## data-path disable (individual control)- effective ONLY if DATAPATH_DISABLE is 0x0.
+
+set_property CONFIG.ADC_DATAFORMAT_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.ADC_DCFILTER_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.ADC_IQCORRECTION_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.ADC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
+
+set_property CONFIG.DAC_DDS_DISABLE 0 [get_bd_cells axi_ad9361]
+set_property CONFIG.DAC_IQCORRECTION_DISABLE 0  [get_bd_cells axi_ad9361]
+set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
+
+## tdd-disable (control is moved exclusively to GPIO)
+
+set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361]
+
+## lvds/cmos configuration
+## core digital interface -- cmos (1) or lvds (0)
+
+proc cfg_ad9361_interface {cmos_or_lvds} {
+
+  if {$cmos_or_lvds eq "LVDS"} {
+
+    set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
+
+    create_bd_port -dir I rx_clk_in_p
+    create_bd_port -dir I rx_clk_in_n
+    create_bd_port -dir I rx_frame_in_p
+    create_bd_port -dir I rx_frame_in_n
+    create_bd_port -dir I -from 5 -to 0 rx_data_in_p
+    create_bd_port -dir I -from 5 -to 0 rx_data_in_n
+
+    create_bd_port -dir O tx_clk_out_p
+    create_bd_port -dir O tx_clk_out_n
+    create_bd_port -dir O tx_frame_out_p
+    create_bd_port -dir O tx_frame_out_n
+    create_bd_port -dir O -from 5 -to 0 tx_data_out_p
+    create_bd_port -dir O -from 5 -to 0 tx_data_out_n
+
+    ad_connect  rx_clk_in_p axi_ad9361/rx_clk_in_p
+    ad_connect  rx_clk_in_n axi_ad9361/rx_clk_in_n
+    ad_connect  rx_frame_in_p axi_ad9361/rx_frame_in_p
+    ad_connect  rx_frame_in_n axi_ad9361/rx_frame_in_n
+    ad_connect  rx_data_in_p axi_ad9361/rx_data_in_p
+    ad_connect  rx_data_in_n axi_ad9361/rx_data_in_n
+    ad_connect  tx_clk_out_p axi_ad9361/tx_clk_out_p
+    ad_connect  tx_clk_out_n axi_ad9361/tx_clk_out_n
+    ad_connect  tx_frame_out_p axi_ad9361/tx_frame_out_p
+    ad_connect  tx_frame_out_n axi_ad9361/tx_frame_out_n
+    ad_connect  tx_data_out_p axi_ad9361/tx_data_out_p
+    ad_connect  tx_data_out_n axi_ad9361/tx_data_out_n
+
+    return
+  }
+
+  if {$cmos_or_lvds eq "CMOS"} {
+
+    set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
+
+    create_bd_port -dir I rx_clk_in
+    create_bd_port -dir I rx_frame_in
+    create_bd_port -dir I -from 11 -to 0 rx_data_in
+    create_bd_port -dir O tx_clk_out
+    create_bd_port -dir O tx_frame_out
+    create_bd_port -dir O -from 11 -to 0 tx_data_out
+
+    ad_connect  rx_clk_in axi_ad9361/rx_clk_in
+    ad_connect  rx_frame_in axi_ad9361/rx_frame_in
+    ad_connect  rx_data_in axi_ad9361/rx_data_in
+    ad_connect  tx_clk_out axi_ad9361/tx_clk_out
+    ad_connect  tx_frame_out axi_ad9361/tx_frame_out
+    ad_connect  tx_data_out axi_ad9361/tx_data_out
+
+    return
+  }
+
+}
+
+
diff --git a/projects/pzsdr1/common/pzsdr1_constr.xdc b/projects/pzsdr1/common/pzsdr1_constr.xdc
new file mode 100644
index 000000000..ebfafbf8a
--- /dev/null
+++ b/projects/pzsdr1/common/pzsdr1_constr.xdc
@@ -0,0 +1,188 @@
+
+# constraints (pzsdr1.b)
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35           U1,L16,IO_L11_35_ENABLE
+set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35           U1,L17,IO_L11_35_TXNRX
+
+set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35                U1,H15,IO_L19_35_CTRL_OUT0
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35           U1,G15,IO_L19_35_CTRL_OUT1
+set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35           U1,K14,IO_L20_35_CTRL_OUT2
+set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35           U1,J14,IO_L20_35_CTRL_OUT3
+set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35      U1,N15,IO_L21_35_CTRL_OUT4
+set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35      U1,N16,IO_L21_35_CTRL_OUT5
+set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35           U1,L14,IO_L22_35_CTRL_OUT6
+set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35           U1,L15,IO_L22_35_CTRL_OUT7
+set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34                U1,N17,IO_L23_34_CTRL_IN0
+set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34                U1,P18,IO_L23_34_CTRL_IN1
+set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34                U1,P15,IO_L24_34_CTRL_IN2
+set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34                U1,P16,IO_L24_34_CTRL_IN3
+set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35          U1,K19,IO_L10_35_EN_AGC
+set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35          U1,J19,IO_L10_35_SYNC_IN
+set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                       ; ## IO_0_35                      U1,G14,IO_00_35_AD9364_RST
+set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS25} [get_ports gpio_clksel]                       ; ## IO_0_34                      U1,R19,IO_00_34_AD9364_CLKSEL
+
+set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35                U1,M14,IO_L23_35_SPI_ENB
+set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS25} [get_ports spi_clk]                           ; ## IO_L23N_T3_35                U1,M15,IO_L23_35_SPI_CLK
+set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35          U1,K16,IO_L24_35_SPI_DI
+set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS25} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35          U1,J16,IO_L24_35_SPI_DO
+
+set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS25} [get_ports clkout_in]                         ; ## IO_25_35                     U1,J15,IO_25_35_AD9364_CLKOUT
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  W6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L22N_T3_13                U1,W6,SCL,JX2,17,I2C_SCL
+set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L22P_T3_13                U1,V6,SDA,JX2,19,I2C_SDA
+
+##    reference-only
+##    --------------
+##    ad9361 (optional rf-card)
+##    --------------------------
+##    JX4,1,GPO0
+##    JX4,2,GPO1
+##    JX4,3,GPO2
+##    JX4,4,GPO3
+##    JX4,7,AUXADC
+##    JX4,8,AUXDAC1
+##    JX4,10,AUXDAC2
+##    JX4,63,AD9364_CLK
+
+##    fixed-io (ps7) (som only, others are carrier specific)
+##    ------------------------------------------------------
+##    U1,A7,PS_MIO01_500_QSPI0_SS_B
+##    U1,A5,PS_MIO06_500_QSPI0_SCLK
+##    U1,B8,PS_MIO02_500_QSPI0_IO0
+##    U1,D6,PS_MIO03_500_QSPI0_IO1
+##    U1,B7,PS_MIO04_500_QSPI0_IO2
+##    U1,A6,PS_MIO05_500_QSPI0_IO3
+##    U1,D5,PS_MIO08_500_ETH0_RESETN                (magnetics-RJ45- JX3,47,ETH_PHY_LED0)
+##    U1,C11,PS_MIO53_501_ETH0_MDIO                 (magnetics-RJ45- JX3,48,ETH_PHY_LED1)
+##    U1,C10,PS_MIO52_501_ETH0_MDC                  (magnetics-RJ45- JX3,51,ETH_MD1_P)
+##    U1,B17,PS_MIO22_501_ETH0_RX_CLK               (magnetics-RJ45- JX3,53,ETH_MD1_N)
+##    U1,D13,PS_MIO27_501_ETH0_RX_CTL               (magnetics-RJ45- JX3,52,ETH_MD2_P)
+##    U1,D11,PS_MIO23_501_ETH0_RX_D0                (magnetics-RJ45- JX3,54,ETH_MD2_N)
+##    U1,A16,PS_MIO24_501_ETH0_RX_D1                (magnetics-RJ45- JX3,57,ETH_MD3_P)
+##    U1,F15,PS_MIO25_501_ETH0_RX_D2                (magnetics-RJ45- JX3,59,ETH_MD3_P)
+##    U1,A15,PS_MIO26_501_ETH0_RX_D3                (magnetics-RJ45- JX3,58,ETH_MD4_P)
+##    U1,A19,PS_MIO16_501_ETH0_TX_CLK               (magnetics-RJ45- JX3,60,ETH_MD4_P)
+##    U1,F14,PS_MIO21_501_ETH0_TX_CTL
+##    U1,E14,PS_MIO17_501_ETH0_TX_D0
+##    U1,B18,PS_MIO18_501_ETH0_TX_D1
+##    U1,D10,PS_MIO19_501_ETH0_TX_D2
+##    U1,A17,PS_MIO20_501_ETH0_TX_D3
+##    U1,B12,PS_MIO48_501_JX4,JX4,99,USB_UART_RXD
+##    U1,C12,PS_MIO49_501_JX4,JX4,98,USB_UART_TXD
+##    U1,D14,PS_MIO40_501_SD0_CLK                   (off-board- JX3,43,SDIO_CLKB1)
+##    U1,C17,PS_MIO41_501_SD0_CMD                   (off-board- JX3,34,SDIO_CMDB1)
+##    U1,E12,PS_MIO42_501_SD0_DATA0                 (off-board- JX3,37,SDIO_DAT0B1)
+##    U1,A9,PS_MIO43_501_SD0_DATA1                  (off-board- JX3,36,SDIO_DAT1B1)
+##    U1,F13,PS_MIO44_501_SD0_DATA2                 (off-board- JX3,39,SDIO_DAT2B1)
+##    U1,B15,PS_MIO45_501_SD0_DATA3                 (off-board- JX3,38,SDIO_DAT3B1)
+##    U1,B13,PS_MIO50_501_SD0_CD                    (off-board- JX3,41,JX3_SD1_CDN)
+##    U1,D8,PS_MIO07_500_USB_RESET_B                (usb- JX3,63,USB_ID)
+##    U1,B5,PS_MIO09_500_USB_CLK_PD                 (usb- JX3,67,USB_OTG_P)
+##    U1,C13,PS_MIO29_501_USB0_DIR                  (usb- JX3,69,USB_OTG_N)
+##    U1,C15,PS_MIO30_501_USB0_STP                  (usb- JX3,68,USB_VBUS_OTG)
+##    U1,E16,PS_MIO31_501_USB0_NXT                  (usb- JX3,70,USB_OTG_CPEN)
+##    U1,A11,PS_MIO36_501_USB0_CLK
+##    U1,A14,PS_MIO32_501_USB0_D0
+##    U1,D15,PS_MIO33_501_USB0_D1
+##    U1,A12,PS_MIO34_501_USB0_D2
+##    U1,F12,PS_MIO35_501_USB0_D3
+##    U1,C16,PS_MIO28_501_USB0_D4
+##    U1,A10,PS_MIO37_501_USB0_D5
+##    U1,E13,PS_MIO38_501_USB0_D6
+##    U1,C18,PS_MIO39_501_USB0_D7
+
+##    ddr (fixed-io)
+##    --------------
+##    U1,C2,DDR3_DQS0_P
+##    U1,B2,DDR3_DQS0_N
+##    U1,G2,DDR3_DQS1_P
+##    U1,F2,DDR3_DQS1_N
+##    U1,R2,DDR3_DQS2_P
+##    U1,T2,DDR3_DQS2_N
+##    U1,W5,DDR3_DQS3_P
+##    U1,W4,DDR3_DQS3_N
+##    U1,C3,DDR3_DQ0
+##    U1,B3,DDR3_DQ1
+##    U1,A2,DDR3_DQ2
+##    U1,A4,DDR3_DQ3
+##    U1,D3,DDR3_DQ4
+##    U1,D1,DDR3_DQ5
+##    U1,C1,DDR3_DQ6
+##    U1,E1,DDR3_DQ7
+##    U1,E2,DDR3_DQ8
+##    U1,E3,DDR3_DQ9
+##    U1,G3,DDR3_DQ10
+##    U1,H3,DDR3_DQ11
+##    U1,J3,DDR3_DQ12
+##    U1,H2,DDR3_DQ13
+##    U1,H1,DDR3_DQ14
+##    U1,J1,DDR3_DQ15
+##    U1,P1,DDR3_DQ16
+##    U1,P3,DDR3_DQ17
+##    U1,R3,DDR3_DQ18
+##    U1,R1,DDR3_DQ19
+##    U1,T4,DDR3_DQ20
+##    U1,U4,DDR3_DQ21
+##    U1,U2,DDR3_DQ22
+##    U1,U3,DDR3_DQ23
+##    U1,V1,DDR3_DQ24
+##    U1,Y3,DDR3_DQ25
+##    U1,W1,DDR3_DQ26
+##    U1,Y4,DDR3_DQ27
+##    U1,Y2,DDR3_DQ28
+##    U1,W3,DDR3_DQ29
+##    U1,V2,DDR3_DQ30
+##    U1,V3,DDR3_DQ31
+##    U1,A1,DDR3_DM0
+##    U1,F1,DDR3_DM1
+##    U1,T1,DDR3_DM2
+##    U1,Y1,DDR3_DM3
+##    U1,N2,DDR3_A0
+##    U1,K2,DDR3_A1
+##    U1,M3,DDR3_A2
+##    U1,K3,DDR3_A3
+##    U1,M4,DDR3_A4
+##    U1,L1,DDR3_A5
+##    U1,L4,DDR3_A6
+##    U1,K4,DDR3_A7
+##    U1,K1,DDR3_A8
+##    U1,J4,DDR3_A9
+##    U1,F5,DDR3_A10
+##    U1,G4,DDR3_A11
+##    U1,E4,DDR3_A12
+##    U1,D4,DDR3_A13
+##    U1,F4,DDR3_A14
+##    U1,L5,DDR3_BA0
+##    U1,R4,DDR3_BA1
+##    U1,J5,DDR3_BA2
+##    U1,L2,DDR3_CK_P
+##    U1,M2,DDR3_CK_N
+##    U1,N3,DDR3_CKE
+##    U1,B4,DDR3_RST#
+##    U1,N1,DDR3_CS#
+##    U1,M5,DDR3_WE#
+##    U1,P4,DDR3_RAS#
+##    U1,P5,DDR3_CAS#
+##    U1,N5,DDR3_ODT
+
+##    resets, clock and power controls
+##    --------------------------------
+##    U1,E7,UNNAMED_3_ICXC7Z20_I217_PSCLK50,33.33MEGHZ
+##    U1,B10,PS-SRST#
+##    U1,C7,PWR_GD_1.35V
+##    JX2,10,PG_1P8V
+##    JX2,11,PG_MODULE
+##    JX1,5,PWR_ENABLE
+##    JX1,6,CARRIER_RESET
+
+##    JTAG
+##    ----
+##    U1,J6,JTAG_TMS,JX1,2,JTAG_TMS
+##    U1,F9,JTAG_TCK,JX1,1,JTAG_TCK
+##    U1,F6,JTAG_TDO,JX1,3,JTAG_TDO
+##    U1,G6,JTAG_TDI,JX1,4,JTAG_TDI
+##    U1,R11,FPGA_DONE,JX1,8,CFG_DONE
+
diff --git a/projects/pzsdr1/common/pzsdr1_constr_cmos.xdc b/projects/pzsdr1/common/pzsdr1_constr_cmos.xdc
new file mode 100644
index 000000000..1b2d85586
--- /dev/null
+++ b/projects/pzsdr1/common/pzsdr1_constr_cmos.xdc
@@ -0,0 +1,42 @@
+
+# constraints (pzsdr1.b)
+# ad9361 (SWAP == 0x0)
+
+set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVCMOS25} [get_ports rx_clk_in]       ; ## IO_L12P_T1_MRCC_35         U1,K17,IO_L12_MRCC_35_DATA_CLK_P
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVCMOS25} [get_ports rx_frame_in]     ; ## IO_L7P_T1_AD2P_35          U1,M19,IO_L07_35_RX_FRAME_P
+set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVCMOS25} [get_ports rx_data_in[0]]   ; ## IO_L13N_T2_MRCC_35         U1,H17,IO_L13_35_TX_D0_N
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS25} [get_ports rx_data_in[1]]   ; ## IO_L13P_T2_MRCC_35         U1,H16,IO_L13_35_TX_D0_P
+set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[2]]   ; ## IO_L14N_T2_AD4N_SRCC_35    U1,H18,IO_L14_35_TX_D1_N
+set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[3]]   ; ## IO_L14P_T2_AD4P_SRCC_35    U1,J18,IO_L14_35_TX_D1_P
+set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[4]]   ; ## IO_L15N_T2_DQS_AD12N_35    U1,F20,IO_L15_35_TX_D2_N
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVCMOS25} [get_ports rx_data_in[5]]   ; ## IO_L15P_T2_DQS_AD12P_35    U1,F19,IO_L15_35_TX_D2_P
+set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[6]]   ; ## IO_L16N_T2_35              U1,G18,IO_L16_35_TX_D3_N
+set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVCMOS25} [get_ports rx_data_in[7]]   ; ## IO_L16P_T2_35              U1,G17,IO_L16_35_TX_D3_P
+set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[8]]   ; ## IO_L17N_T2_AD5N_35         U1,H20,IO_L17_35_TX_D4_N
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[9]]   ; ## IO_L17P_T2_AD5P_35         U1,J20,IO_L17_35_TX_D4_P
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[10]]  ; ## IO_L18N_T2_AD13N_35        U1,G20,IO_L18_35_TX_D5_N
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVCMOS25} [get_ports rx_data_in[11]]  ; ## IO_L18P_T2_AD13P_35        U1,G19,IO_L18_35_TX_D5_P
+
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVCMOS25} [get_ports tx_clk_out]      ; ## IO_L8P_T1_AD10P_35         U1,M17,IO_L08_35_FB_CLK_P
+set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVCMOS25} [get_ports tx_frame_out]    ; ## IO_L9P_T1_DQS_AD3P_35      U1,L19,IO_L09_35_TX_FRAME_P
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[0]]  ; ## IO_L1N_T0_AD0N_35          U1,B20,IO_L01_35_RX_D0_N
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[1]]  ; ## IO_L1P_T0_AD0P_35          U1,C20,IO_L01_35_RX_D0_P
+set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[2]]  ; ## IO_L2N_T0_AD8N_35          U1,A20,IO_L02_35_RX_D1_N
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[3]]  ; ## IO_L2P_T0_AD8P_35          U1,B19,IO_L02_35_RX_D1_P
+set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVCMOS25} [get_ports tx_data_out[4]]  ; ## IO_L3N_T0_DQS_AD1N_35      U1,D18,IO_L03_35_RX_D2_N
+set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVCMOS25} [get_ports tx_data_out[5]]  ; ## IO_L3P_T0_DQS_AD1P_35      U1,E17,IO_L03_35_RX_D2_P
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[6]]  ; ## IO_L4N_T0_35               U1,D20,IO_L04_35_RX_D3_N
+set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[7]]  ; ## IO_L4P_T0_35               U1,D19,IO_L04_35_RX_D3_P
+set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[8]]  ; ## IO_L5N_T0_AD9N_35          U1,E19,IO_L05_35_RX_D4_N
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVCMOS25} [get_ports tx_data_out[9]]  ; ## IO_L5P_T0_AD9P_35          U1,E18,IO_L05_35_RX_D4_P
+set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVCMOS25} [get_ports tx_data_out[10]] ; ## IO_L6N_T0_VREF_35          U1,F17,IO_L06_35_RX_D5_N
+set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVCMOS25} [get_ports tx_data_out[11]] ; ## IO_L6P_T0_35               U1,F16,IO_L06_35_RX_D5_P
+
+set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVCMOS25} [get_ports tx_gnd[0]]       ; ## IO_L8N_T1_AD10N_35         U1,M18,IO_L08_35_FB_CLK_N
+set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVCMOS25} [get_ports tx_gnd[1]]       ; ## IO_L9N_T1_DQS_AD3N_35      U1,L20,IO_L09_35_TX_FRAME_N
+
+# clocks
+
+create_clock -name rx_clk       -period  8 [get_ports rx_clk_in]
+create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+
diff --git a/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc b/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc
new file mode 100644
index 000000000..c5e8e10c4
--- /dev/null
+++ b/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc
@@ -0,0 +1,42 @@
+
+# constraints (pzsdr1.b)
+# ad9361
+
+set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35           U1,K17,IO_L12_MRCC_35_DATA_CLK_P
+set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35           U1,K18,IO_L12_MRCC_35_DATA_CLK_N
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35            U1,M19,IO_L07_35_RX_FRAME_P
+set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35            U1,M20,IO_L07_35_RX_FRAME_N
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35            U1,C20,IO_L01_35_RX_D0_P
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35            U1,B20,IO_L01_35_RX_D0_N
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35            U1,B19,IO_L02_35_RX_D1_P
+set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35            U1,A20,IO_L02_35_RX_D1_N
+set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35        U1,E17,IO_L03_35_RX_D2_P
+set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35        U1,D18,IO_L03_35_RX_D2_N
+set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35                 U1,D19,IO_L04_35_RX_D3_P
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35                 U1,D20,IO_L04_35_RX_D3_N
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35            U1,E18,IO_L05_35_RX_D4_P
+set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35            U1,E19,IO_L05_35_RX_D4_N
+set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35                 U1,F16,IO_L06_35_RX_D5_P
+set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35            U1,F17,IO_L06_35_RX_D5_N
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35           U1,M17,IO_L08_35_FB_CLK_P
+set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35           U1,M18,IO_L08_35_FB_CLK_N
+set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35        U1,L19,IO_L09_35_TX_FRAME_P
+set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35        U1,L20,IO_L09_35_TX_FRAME_N
+set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35           U1,H16,IO_L13_35_TX_D0_P
+set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35           U1,H17,IO_L13_35_TX_D0_N
+set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35      U1,J18,IO_L14_35_TX_D1_P
+set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35      U1,H18,IO_L14_35_TX_D1_N
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35      U1,F19,IO_L15_35_TX_D2_P
+set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35      U1,F20,IO_L15_35_TX_D2_N
+set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35                U1,G17,IO_L16_35_TX_D3_P
+set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35                U1,G18,IO_L16_35_TX_D3_N
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35           U1,J20,IO_L17_35_TX_D4_P
+set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35           U1,H20,IO_L17_35_TX_D4_N
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35          U1,G19,IO_L18_35_TX_D5_P
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35          U1,G20,IO_L18_35_TX_D5_N
+
+# clocks
+
+create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+

From aa02ca875fc2ce400292b1cd6d5b4237cb11f854 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 13:40:25 -0500
Subject: [PATCH 721/972] pzsdr1- common files

---
 projects/pzsdr1/common/ccbrk_constr.xdc | 95 +++++++++++++++++++++++++
 1 file changed, 95 insertions(+)
 create mode 100644 projects/pzsdr1/common/ccbrk_constr.xdc

diff --git a/projects/pzsdr1/common/ccbrk_constr.xdc b/projects/pzsdr1/common/ccbrk_constr.xdc
new file mode 100644
index 000000000..3c0854b87
--- /dev/null
+++ b/projects/pzsdr1/common/ccbrk_constr.xdc
@@ -0,0 +1,95 @@
+
+## constraints (ccbrk.c + ccbrk_lb.a)
+## ad9361 clkout forward
+
+set_property  -dict {PACKAGE_PIN  W16     IOSTANDARD  LVCMOS18} [get_ports  clkout_out]   ; ## (lb: none)         U1,W16,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32
+
+## push-buttons- led- dip-switches- loopbacks- (ps7 gpio)
+
+set_property  -dict {PACKAGE_PIN  Y14     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[0]]   ; ## (lb: none)         U1,Y14,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19
+set_property  -dict {PACKAGE_PIN  T16     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[1]]   ; ## (lb: none)         U1,T16,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26
+set_property  -dict {PACKAGE_PIN  U17     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[2]]   ; ## (lb: none)         U1,U17,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28
+set_property  -dict {PACKAGE_PIN  Y19     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[3]]   ; ## (lb: none)         U1,Y19,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16
+
+## orphans- io- (ps7 gpio)
+
+set_property  -dict {PACKAGE_PIN  V5      IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[4]]   ; ## (lb: none)         U1,V5,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P
+set_property  -dict {PACKAGE_PIN  V11     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[5]]   ; ## (lb: none)         U1,V11,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52
+set_property  -dict {PACKAGE_PIN  V10     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[6]]   ; ## (lb: none)         U1,V10,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54
+set_property  -dict {PACKAGE_PIN  V16     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[7]]   ; ## (lb: none)         U1,V16,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30
+
+## ps7- fixed io- to- fpga regular io (ps7 gpio)
+
+set_property  -dict {PACKAGE_PIN  V15     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[8]]   ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,E9,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23)
+set_property  -dict {PACKAGE_PIN  Y18     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[9]]   ; ## U1,Y18,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9  (U1,B9,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11)
+set_property  -dict {PACKAGE_PIN  Y17     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[10]]  ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C8,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21)
+
+## ps7- fixed io- to- ps7- fixed io (reference only)
+## U1,B14,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,D16,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22
+
+## ps7- fixed io- orphans (reference only)
+## U1,E6,PS_MIO00_500_JX4,JX4,97,PS_MIO00_500_JX4,P5,21
+## U1,E8,PS_MIO13_500_JX4,JX4,91,PS_MIO13_500_JX4,P5,9
+## U1,C5,PS_MIO14_500_JX4,JX4,93,PS_MIO14_500_JX4,P5,11
+## U1,D9,PS_MIO12_500_JX4,JX4,86,PS_MIO12_500_JX4,P7,10
+## U1,C6,PS_MIO11_500_JX4,JX4,88,PS_MIO11_500_JX4,P7,12
+
+## fpga- regular io
+
+set_property  -dict {PACKAGE_PIN  U7      IOSTANDARD  LVCMOS25} [get_ports  gp_out[0]]    ; ## U1,U7,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28
+set_property  -dict {PACKAGE_PIN  T9      IOSTANDARD  LVCMOS25} [get_ports  gp_in[0]]     ; ## U1,T9,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27
+set_property  -dict {PACKAGE_PIN  V7      IOSTANDARD  LVCMOS25} [get_ports  gp_out[1]]    ; ## U1,V7,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30
+set_property  -dict {PACKAGE_PIN  U10     IOSTANDARD  LVCMOS25} [get_ports  gp_in[1]]     ; ## U1,U10,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29
+set_property  -dict {PACKAGE_PIN  Y7      IOSTANDARD  LVCMOS25} [get_ports  gp_out[2]]    ; ## U1,Y7,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32
+set_property  -dict {PACKAGE_PIN  Y9      IOSTANDARD  LVCMOS25} [get_ports  gp_in[2]]     ; ## U1,Y9,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31
+set_property  -dict {PACKAGE_PIN  Y6      IOSTANDARD  LVCMOS25} [get_ports  gp_out[3]]    ; ## U1,Y6,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34
+set_property  -dict {PACKAGE_PIN  Y8      IOSTANDARD  LVCMOS25} [get_ports  gp_in[3]]     ; ## U1,Y8,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33
+set_property  -dict {PACKAGE_PIN  V8      IOSTANDARD  LVCMOS25} [get_ports  gp_out[4]]    ; ## U1,V8,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38
+set_property  -dict {PACKAGE_PIN  W10     IOSTANDARD  LVCMOS25} [get_ports  gp_in[4]]     ; ## U1,W10,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37
+set_property  -dict {PACKAGE_PIN  W8      IOSTANDARD  LVCMOS25} [get_ports  gp_out[5]]    ; ## U1,W8,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40
+set_property  -dict {PACKAGE_PIN  W9      IOSTANDARD  LVCMOS25} [get_ports  gp_in[5]]     ; ## U1,W9,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39
+set_property  -dict {PACKAGE_PIN  U9      IOSTANDARD  LVCMOS25} [get_ports  gp_out[6]]    ; ## U1,U9,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42
+set_property  -dict {PACKAGE_PIN  W11     IOSTANDARD  LVCMOS25} [get_ports  gp_in[6]]     ; ## U1,W11,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41
+set_property  -dict {PACKAGE_PIN  U8      IOSTANDARD  LVCMOS25} [get_ports  gp_out[7]]    ; ## U1,U8,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44
+set_property  -dict {PACKAGE_PIN  Y11     IOSTANDARD  LVCMOS25} [get_ports  gp_in[7]]     ; ## U1,Y11,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43
+set_property  -dict {PACKAGE_PIN  T5      IOSTANDARD  LVCMOS25} [get_ports  gp_out[8]]    ; ## U1,T5,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46
+set_property  -dict {PACKAGE_PIN  Y12     IOSTANDARD  LVCMOS25} [get_ports  gp_in[8]]     ; ## U1,Y12,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45
+set_property  -dict {PACKAGE_PIN  U5      IOSTANDARD  LVCMOS25} [get_ports  gp_out[9]]    ; ## U1,U5,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48
+set_property  -dict {PACKAGE_PIN  Y13     IOSTANDARD  LVCMOS25} [get_ports  gp_in[9]]     ; ## U1,Y13,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47
+set_property  -dict {PACKAGE_PIN  W15     IOSTANDARD  LVCMOS25} [get_ports  gp_out[10]]   ; ## U1,W15,IO_L10_34_JX4_N,JX4,44,IO_L10_34_JX4_N,P6,27
+set_property  -dict {PACKAGE_PIN  T19     IOSTANDARD  LVCMOS25} [get_ports  gp_in[10]]    ; ## U1,T19,IO_25_34_JX4,JX4,64,IO_25_34_JX4,P5,23
+set_property  -dict {PACKAGE_PIN  T11     IOSTANDARD  LVCMOS25} [get_ports  gp_out[11]]   ; ## U1,T11,IO_L01_34_JX4_P,JX4,19,IO_L01_34_JX4_P,P6,2
+set_property  -dict {PACKAGE_PIN  T12     IOSTANDARD  LVCMOS25} [get_ports  gp_in[11]]    ; ## U1,T12,IO_L02_34_JX4_P,JX4,20,IO_L02_34_JX4_P,P6,1
+set_property  -dict {PACKAGE_PIN  T10     IOSTANDARD  LVCMOS25} [get_ports  gp_out[12]]   ; ## U1,T10,IO_L01_34_JX4_N,JX4,21,IO_L01_34_JX4_N,P6,4
+set_property  -dict {PACKAGE_PIN  U12     IOSTANDARD  LVCMOS25} [get_ports  gp_in[12]]    ; ## U1,U12,IO_L02_34_JX4_N,JX4,22,IO_L02_34_JX4_N,P6,3
+set_property  -dict {PACKAGE_PIN  U13     IOSTANDARD  LVCMOS25} [get_ports  gp_out[13]]   ; ## U1,U13,IO_L03_34_JX4_P,JX4,25,IO_L03_34_JX4_P,P6,6
+set_property  -dict {PACKAGE_PIN  V12     IOSTANDARD  LVCMOS25} [get_ports  gp_in[13]]    ; ## U1,V12,IO_L04_34_JX4_P,JX4,26,IO_L04_34_JX4_P,P6,5
+set_property  -dict {PACKAGE_PIN  V13     IOSTANDARD  LVCMOS25} [get_ports  gp_out[14]]   ; ## U1,V13,IO_L03_34_JX4_N,JX4,27,IO_L03_34_JX4_N,P6,8
+set_property  -dict {PACKAGE_PIN  W13     IOSTANDARD  LVCMOS25} [get_ports  gp_in[14]]    ; ## U1,W13,IO_L04_34_JX4_N,JX4,28,IO_L04_34_JX4_N,P6,7
+set_property  -dict {PACKAGE_PIN  T14     IOSTANDARD  LVCMOS25} [get_ports  gp_out[15]]   ; ## U1,T14,IO_L05_34_JX4_P,JX4,31,IO_L05_34_JX4_P,P6,14
+set_property  -dict {PACKAGE_PIN  P14     IOSTANDARD  LVCMOS25} [get_ports  gp_in[15]]    ; ## U1,P14,IO_L06_34_JX4_P,JX4,32,IO_L06_34_JX4_P,P6,13
+set_property  -dict {PACKAGE_PIN  T15     IOSTANDARD  LVCMOS25} [get_ports  gp_out[16]]   ; ## U1,T15,IO_L05_34_JX4_N,JX4,33,IO_L05_34_JX4_N,P6,16
+set_property  -dict {PACKAGE_PIN  R14     IOSTANDARD  LVCMOS25} [get_ports  gp_in[16]]    ; ## U1,R14,IO_L06_34_JX4_N,JX4,34,IO_L06_34_JX4_N,P6,15
+set_property  -dict {PACKAGE_PIN  Y16     IOSTANDARD  LVCMOS25} [get_ports  gp_out[17]]   ; ## U1,Y16,IO_L07_34_JX4_P,JX4,35,IO_L07_34_JX4_P,P6,18
+set_property  -dict {PACKAGE_PIN  W14     IOSTANDARD  LVCMOS25} [get_ports  gp_in[17]]    ; ## U1,W14,IO_L08_34_JX4_P,JX4,36,IO_L08_34_JX4_P,P6,17
+set_property  -dict {PACKAGE_PIN  U14     IOSTANDARD  LVCMOS25} [get_ports  gp_out[18]]   ; ## U1,U14,IO_L11_SRCC_34_JX4_P,JX4,45,IO_L11_SRCC_34_JX4_P,P6,30
+set_property  -dict {PACKAGE_PIN  U18     IOSTANDARD  LVCMOS25} [get_ports  gp_in[18]]    ; ## U1,U18,IO_L12_MRCC_34_JX4_P,JX4,46,IO_L12_MRCC_34_JX4_P,P6,29
+set_property  -dict {PACKAGE_PIN  U15     IOSTANDARD  LVCMOS25} [get_ports  gp_out[19]]   ; ## U1,U15,IO_L11_SRCC_34_JX4_N,JX4,47,IO_L11_SRCC_34_JX4_N,P6,32
+set_property  -dict {PACKAGE_PIN  U19     IOSTANDARD  LVCMOS25} [get_ports  gp_in[19]]    ; ## U1,U19,IO_L12_MRCC_34_JX4_N,JX4,48,IO_L12_MRCC_34_JX4_N,P6,31
+set_property  -dict {PACKAGE_PIN  N18     IOSTANDARD  LVCMOS25} [get_ports  gp_out[20]]   ; ## U1,N18,IO_L13_MRCC_34_JX4_P,JX4,51,IO_L13_MRCC_34_JX4_P,P7,2
+set_property  -dict {PACKAGE_PIN  N20     IOSTANDARD  LVCMOS25} [get_ports  gp_in[20]]    ; ## U1,N20,IO_L14_SRCC_34_JX4_P,JX4,52,IO_L14_SRCC_34_JX4_P,P7,1
+set_property  -dict {PACKAGE_PIN  P19     IOSTANDARD  LVCMOS25} [get_ports  gp_out[21]]   ; ## U1,P19,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4
+set_property  -dict {PACKAGE_PIN  P20     IOSTANDARD  LVCMOS25} [get_ports  gp_in[21]]    ; ## U1,P20,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3
+set_property  -dict {PACKAGE_PIN  T20     IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]   ; ## U1,T20,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6
+set_property  -dict {PACKAGE_PIN  V20     IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]    ; ## U1,V20,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5
+set_property  -dict {PACKAGE_PIN  U20     IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]   ; ## U1,U20,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8
+set_property  -dict {PACKAGE_PIN  W20     IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]    ; ## U1,W20,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7
+set_property  -dict {PACKAGE_PIN  R16     IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]   ; ## U1,R16,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18
+set_property  -dict {PACKAGE_PIN  T17     IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]    ; ## U1,T17,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17
+set_property  -dict {PACKAGE_PIN  R17     IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]   ; ## U1,R17,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20
+set_property  -dict {PACKAGE_PIN  R18     IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]    ; ## U1,R18,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19
+set_property  -dict {PACKAGE_PIN  V17     IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]   ; ## U1,V17,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26
+set_property  -dict {PACKAGE_PIN  W18     IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]    ; ## U1,W18,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25
+set_property  -dict {PACKAGE_PIN  V18     IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]   ; ## U1,V18,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28
+set_property  -dict {PACKAGE_PIN  W19     IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]    ; ## U1,W19,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27
+

From a61da1d2ac37cf65ab8d0791a99007a351eaf6ef Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 15:31:25 -0500
Subject: [PATCH 722/972] pzsdr1/common- updates

---
 projects/pzsdr1/common/ccbrk_bd.tcl     | 16 ++--------
 projects/pzsdr1/common/ccbrk_constr.xdc | 42 ++++++++++++-------------
 2 files changed, 24 insertions(+), 34 deletions(-)

diff --git a/projects/pzsdr1/common/ccbrk_bd.tcl b/projects/pzsdr1/common/ccbrk_bd.tcl
index 204545923..940a3869f 100644
--- a/projects/pzsdr1/common/ccbrk_bd.tcl
+++ b/projects/pzsdr1/common/ccbrk_bd.tcl
@@ -4,26 +4,16 @@
 ad_connect  sys_ps7/ENET1_GMII_RX_CLK GND
 ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
 
-# un-used io
+# un-used io (regular)
 
 set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
 set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg
-set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg
-
-ad_cpu_interconnect 0x41200000 axi_gpreg
+set_property -dict [list CONFIG.NUM_OF_IO {1}] $axi_gpreg
 
 create_bd_port -dir I -from 31 -to 0 gp_in_0
-create_bd_port -dir I -from 31 -to 0 gp_in_1
 create_bd_port -dir O -from 31 -to 0 gp_out_0
-create_bd_port -dir O -from 31 -to 0 gp_out_1
 
 ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
-ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
 ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
-ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
-
-## temporary (remove ila indirectly)
-
-delete_bd_objs [get_bd_cells ila_adc]
-delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
+ad_cpu_interconnect 0x41200000 axi_gpreg
 
diff --git a/projects/pzsdr1/common/ccbrk_constr.xdc b/projects/pzsdr1/common/ccbrk_constr.xdc
index 3c0854b87..950509512 100644
--- a/projects/pzsdr1/common/ccbrk_constr.xdc
+++ b/projects/pzsdr1/common/ccbrk_constr.xdc
@@ -2,27 +2,27 @@
 ## constraints (ccbrk.c + ccbrk_lb.a)
 ## ad9361 clkout forward
 
-set_property  -dict {PACKAGE_PIN  W16     IOSTANDARD  LVCMOS18} [get_ports  clkout_out]   ; ## (lb: none)         U1,W16,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32
+set_property  -dict {PACKAGE_PIN  W16     IOSTANDARD  LVCMOS25} [get_ports  clkout_out]   ; ## (lb: none)         U1,W16,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32
 
 ## push-buttons- led- dip-switches- loopbacks- (ps7 gpio)
 
-set_property  -dict {PACKAGE_PIN  Y14     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[0]]   ; ## (lb: none)         U1,Y14,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19
-set_property  -dict {PACKAGE_PIN  T16     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[1]]   ; ## (lb: none)         U1,T16,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26
-set_property  -dict {PACKAGE_PIN  U17     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[2]]   ; ## (lb: none)         U1,U17,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28
-set_property  -dict {PACKAGE_PIN  Y19     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[3]]   ; ## (lb: none)         U1,Y19,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16
+set_property  -dict {PACKAGE_PIN  Y14     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[0]]   ; ## (lb: none)         U1,Y14,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19
+set_property  -dict {PACKAGE_PIN  T16     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[1]]   ; ## (lb: none)         U1,T16,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26
+set_property  -dict {PACKAGE_PIN  U17     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[2]]   ; ## (lb: none)         U1,U17,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28
+set_property  -dict {PACKAGE_PIN  Y19     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[3]]   ; ## (lb: none)         U1,Y19,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16
 
 ## orphans- io- (ps7 gpio)
 
 set_property  -dict {PACKAGE_PIN  V5      IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[4]]   ; ## (lb: none)         U1,V5,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P
 set_property  -dict {PACKAGE_PIN  V11     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[5]]   ; ## (lb: none)         U1,V11,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52
 set_property  -dict {PACKAGE_PIN  V10     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[6]]   ; ## (lb: none)         U1,V10,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54
-set_property  -dict {PACKAGE_PIN  V16     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[7]]   ; ## (lb: none)         U1,V16,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30
+set_property  -dict {PACKAGE_PIN  V16     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[7]]   ; ## (lb: none)         U1,V16,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30
 
 ## ps7- fixed io- to- fpga regular io (ps7 gpio)
 
-set_property  -dict {PACKAGE_PIN  V15     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[8]]   ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,E9,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23)
-set_property  -dict {PACKAGE_PIN  Y18     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[9]]   ; ## U1,Y18,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9  (U1,B9,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11)
-set_property  -dict {PACKAGE_PIN  Y17     IOSTANDARD  LVCMOS18} [get_ports  gpio_bd[10]]  ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C8,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21)
+set_property  -dict {PACKAGE_PIN  V15     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[8]]   ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,E9,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23)
+set_property  -dict {PACKAGE_PIN  Y18     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[9]]   ; ## U1,Y18,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9  (U1,B9,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11)
+set_property  -dict {PACKAGE_PIN  Y17     IOSTANDARD  LVCMOS25} [get_ports  gpio_bd[10]]  ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C8,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21)
 
 ## ps7- fixed io- to- ps7- fixed io (reference only)
 ## U1,B14,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,D16,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22
@@ -80,16 +80,16 @@ set_property  -dict {PACKAGE_PIN  N18     IOSTANDARD  LVCMOS25} [get_ports  gp_o
 set_property  -dict {PACKAGE_PIN  N20     IOSTANDARD  LVCMOS25} [get_ports  gp_in[20]]    ; ## U1,N20,IO_L14_SRCC_34_JX4_P,JX4,52,IO_L14_SRCC_34_JX4_P,P7,1
 set_property  -dict {PACKAGE_PIN  P19     IOSTANDARD  LVCMOS25} [get_ports  gp_out[21]]   ; ## U1,P19,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4
 set_property  -dict {PACKAGE_PIN  P20     IOSTANDARD  LVCMOS25} [get_ports  gp_in[21]]    ; ## U1,P20,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3
-set_property  -dict {PACKAGE_PIN  T20     IOSTANDARD  LVCMOS18} [get_ports  gp_out[22]]   ; ## U1,T20,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6
-set_property  -dict {PACKAGE_PIN  V20     IOSTANDARD  LVCMOS18} [get_ports  gp_in[22]]    ; ## U1,V20,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5
-set_property  -dict {PACKAGE_PIN  U20     IOSTANDARD  LVCMOS18} [get_ports  gp_out[23]]   ; ## U1,U20,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8
-set_property  -dict {PACKAGE_PIN  W20     IOSTANDARD  LVCMOS18} [get_ports  gp_in[23]]    ; ## U1,W20,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7
-set_property  -dict {PACKAGE_PIN  R16     IOSTANDARD  LVCMOS18} [get_ports  gp_out[24]]   ; ## U1,R16,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18
-set_property  -dict {PACKAGE_PIN  T17     IOSTANDARD  LVCMOS18} [get_ports  gp_in[24]]    ; ## U1,T17,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17
-set_property  -dict {PACKAGE_PIN  R17     IOSTANDARD  LVCMOS18} [get_ports  gp_out[25]]   ; ## U1,R17,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20
-set_property  -dict {PACKAGE_PIN  R18     IOSTANDARD  LVCMOS18} [get_ports  gp_in[25]]    ; ## U1,R18,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19
-set_property  -dict {PACKAGE_PIN  V17     IOSTANDARD  LVCMOS18} [get_ports  gp_out[26]]   ; ## U1,V17,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26
-set_property  -dict {PACKAGE_PIN  W18     IOSTANDARD  LVCMOS18} [get_ports  gp_in[26]]    ; ## U1,W18,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25
-set_property  -dict {PACKAGE_PIN  V18     IOSTANDARD  LVCMOS18} [get_ports  gp_out[27]]   ; ## U1,V18,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28
-set_property  -dict {PACKAGE_PIN  W19     IOSTANDARD  LVCMOS18} [get_ports  gp_in[27]]    ; ## U1,W19,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27
+set_property  -dict {PACKAGE_PIN  T20     IOSTANDARD  LVCMOS25} [get_ports  gp_out[22]]   ; ## U1,T20,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6
+set_property  -dict {PACKAGE_PIN  V20     IOSTANDARD  LVCMOS25} [get_ports  gp_in[22]]    ; ## U1,V20,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5
+set_property  -dict {PACKAGE_PIN  U20     IOSTANDARD  LVCMOS25} [get_ports  gp_out[23]]   ; ## U1,U20,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8
+set_property  -dict {PACKAGE_PIN  W20     IOSTANDARD  LVCMOS25} [get_ports  gp_in[23]]    ; ## U1,W20,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7
+set_property  -dict {PACKAGE_PIN  R16     IOSTANDARD  LVCMOS25} [get_ports  gp_out[24]]   ; ## U1,R16,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18
+set_property  -dict {PACKAGE_PIN  T17     IOSTANDARD  LVCMOS25} [get_ports  gp_in[24]]    ; ## U1,T17,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17
+set_property  -dict {PACKAGE_PIN  R17     IOSTANDARD  LVCMOS25} [get_ports  gp_out[25]]   ; ## U1,R17,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20
+set_property  -dict {PACKAGE_PIN  R18     IOSTANDARD  LVCMOS25} [get_ports  gp_in[25]]    ; ## U1,R18,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19
+set_property  -dict {PACKAGE_PIN  V17     IOSTANDARD  LVCMOS25} [get_ports  gp_out[26]]   ; ## U1,V17,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26
+set_property  -dict {PACKAGE_PIN  W18     IOSTANDARD  LVCMOS25} [get_ports  gp_in[26]]    ; ## U1,W18,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25
+set_property  -dict {PACKAGE_PIN  V18     IOSTANDARD  LVCMOS25} [get_ports  gp_out[27]]   ; ## U1,V18,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28
+set_property  -dict {PACKAGE_PIN  W19     IOSTANDARD  LVCMOS25} [get_ports  gp_in[27]]    ; ## U1,W19,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27
 

From e85dd2740aee75f1a403a8a895fb0b5e1639c685 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 15:32:25 -0500
Subject: [PATCH 723/972] pzsdr1/ccbrk_lvds- updates

---
 projects/pzsdr1/ccbrk_lvds/Makefile           |  17 +-
 projects/pzsdr1/ccbrk_lvds/system_bd.tcl      |   4 +-
 projects/pzsdr1/ccbrk_lvds/system_constr.xdc  | 104 ---------
 projects/pzsdr1/ccbrk_lvds/system_project.tcl |  15 +-
 projects/pzsdr1/ccbrk_lvds/system_top.v       | 202 +++++++-----------
 5 files changed, 91 insertions(+), 251 deletions(-)
 delete mode 100644 projects/pzsdr1/ccbrk_lvds/system_constr.xdc

diff --git a/projects/pzsdr1/ccbrk_lvds/Makefile b/projects/pzsdr1/ccbrk_lvds/Makefile
index 916b03227..66bf7abe5 100644
--- a/projects/pzsdr1/ccbrk_lvds/Makefile
+++ b/projects/pzsdr1/ccbrk_lvds/Makefile
@@ -7,18 +7,15 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr1_constr_lvds.xdc
+M_DEPS += ../common/pzsdr1_constr.xdc
+M_DEPS += ../common/pzsdr1_bd.tcl
+M_DEPS += ../common/ccbrk_constr.xdc
 M_DEPS += ../common/ccbrk_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
-M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
-M_DEPS += ../../common/pzsdr1/pzsdr1_lvds_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -47,7 +44,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_lvds_pzsdr1.sdk/system_top.hdf
+all: lib pzsdr1_ccbrk_lvds.sdk/system_top.hdf
 
 
 clean: 
@@ -64,9 +61,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_lvds_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
+pzsdr1_ccbrk_lvds.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_lvds_pzsdr1_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr1_ccbrk_lvds_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr1/ccbrk_lvds/system_bd.tcl b/projects/pzsdr1/ccbrk_lvds/system_bd.tcl
index aa8108693..40c65fd14 100644
--- a/projects/pzsdr1/ccbrk_lvds/system_bd.tcl
+++ b/projects/pzsdr1/ccbrk_lvds/system_bd.tcl
@@ -1,4 +1,6 @@
 
-source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_bd.tcl
+source ../common/pzsdr1_bd.tcl
 source ../common/ccbrk_bd.tcl
 
+cfg_ad9361_interface LVDS
+
diff --git a/projects/pzsdr1/ccbrk_lvds/system_constr.xdc b/projects/pzsdr1/ccbrk_lvds/system_constr.xdc
deleted file mode 100644
index 5b91e2425..000000000
--- a/projects/pzsdr1/ccbrk_lvds/system_constr.xdc
+++ /dev/null
@@ -1,104 +0,0 @@
-
-# gpio
-
-set_property  -dict {PACKAGE_PIN  Y14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L8N_T1_34        
-set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L9P_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  U17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9N_T1_DQS_34    
-set_property  -dict {PACKAGE_PIN  Y19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]                        ; ## (led) IO_L17N_T2_34       
-
-## constraints
-## loopback
-## p6
-
-set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[0]]        ; ## JX4.20  IO_L2P_T0_34                  
-set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  gp_in[0]]         ; ## JX4.19  IO_L1P_T0_34                  
-set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[1]]        ; ## JX4.22  IO_L2N_T0_34                  
-set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  gp_in[1]]         ; ## JX4.21  IO_L1N_T0_34                  
-set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[2]]        ; ## JX4.26  IO_L4P_T0_34                  
-set_property  -dict {PACKAGE_PIN  U13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[2]]         ; ## JX4.25  IO_L3P_T0_DQS_PUDC_B_34       
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  gp_out[3]]        ; ## JX4.28  IO_L4N_T0_34                  
-set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  gp_in[3]]         ; ## JX4.27  IO_L3N_T0_DQS_34              
-set_property  -dict {PACKAGE_PIN  P14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[4]]        ; ## JX4.32  IO_L6P_T0_34                  
-set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD  LVCMOS25} [get_ports  gp_in[4]]         ; ## JX4.31  IO_L5P_T0_34                  
-set_property  -dict {PACKAGE_PIN  R14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[5]]        ; ## JX4.34  IO_L6N_T0_VREF_34             
-set_property  -dict {PACKAGE_PIN  T15   IOSTANDARD  LVCMOS25} [get_ports  gp_in[5]]         ; ## JX4.33  IO_L5N_T0_34                  
-set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD  LVCMOS25} [get_ports  gp_out[6]]        ; ## JX4.36  IO_L8P_T1_34                  
-set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD  LVCMOS25} [get_ports  gp_in[6]]         ; ## JX4.35  IO_L7P_T1_34                  
-set_property  -dict {PACKAGE_PIN  U18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[7]]        ; ## JX4.46  IO_L12P_T1_MRCC_34            
-set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD  LVCMOS25} [get_ports  gp_in[7]]         ; ## JX4.45  IO_L11P_T1_SRCC_34            
-set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD  LVCMOS25} [get_ports  gp_out[8]]        ; ## JX4.48  IO_L12N_T1_MRCC_34            
-set_property  -dict {PACKAGE_PIN  U15   IOSTANDARD  LVCMOS25} [get_ports  gp_in[8]]         ; ## JX4.47  IO_L11N_T1_SRCC_34            
-
-## p7
-
-set_property  -dict {PACKAGE_PIN  N20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[9]]        ; ## JX4.52  IO_L14P_T2_SRCC_34            
-set_property  -dict {PACKAGE_PIN  N18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[9]]         ; ## JX4.51  IO_L13P_T2_MRCC_34            
-set_property  -dict {PACKAGE_PIN  P20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[10]]       ; ## JX4.54  IO_L14N_T2_SRCC_34            
-set_property  -dict {PACKAGE_PIN  P19   IOSTANDARD  LVCMOS25} [get_ports  gp_in[10]]        ; ## JX4.53  IO_L13N_T2_MRCC_34            
-set_property  -dict {PACKAGE_PIN  V20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[11]]       ; ## JX4.58  IO_L16P_T2_34                 
-set_property  -dict {PACKAGE_PIN  T20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[11]]        ; ## JX4.57  IO_L15P_T2_DQS_34             
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD  LVCMOS25} [get_ports  gp_out[12]]       ; ## JX4.60  IO_L16N_T2_34                 
-set_property  -dict {PACKAGE_PIN  U20   IOSTANDARD  LVCMOS25} [get_ports  gp_in[12]]        ; ## JX4.59  IO_L15N_T2_DQS_34             
-set_property  -dict {PACKAGE_PIN  T17   IOSTANDARD  LVCMOS25} [get_ports  gp_out[13]]       ; ## JX4.74  IO_L20P_T3_34                 
-set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD  LVCMOS25} [get_ports  gp_in[13]]        ; ## JX4.73  IO_L19P_T3_34                 
-set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[14]]       ; ## JX4.76  IO_L20N_T3_34                 
-set_property  -dict {PACKAGE_PIN  R17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[14]]        ; ## JX4.75  IO_L19N_T3_VREF_34            
-set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD  LVCMOS25} [get_ports  gp_out[15]]       ; ## JX4.78  IO_L22P_T3_34                 
-set_property  -dict {PACKAGE_PIN  V17   IOSTANDARD  LVCMOS25} [get_ports  gp_in[15]]        ; ## JX4.77  IO_L21P_T3_DQS_34             
-set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports  gp_out[16]]       ; ## JX4.80  IO_L22N_T3_34                 
-set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD  LVCMOS25} [get_ports  gp_in[16]]        ; ## JX4.79  IO_L21N_T3_DQS_34             
-
-## p2
-
-set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[17]]       ; ## JX2.36  IO_L12P_T1_MRCC_13            
-set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[17]]        ; ## JX2.35  IO_L11P_T1_SRCC_13            
-set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  gp_out[18]]       ; ## JX2.38  IO_L12N_T1_MRCC_13            
-set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[18]]        ; ## JX2.37  IO_L11N_T1_SRCC_13            
-set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[19]]       ; ## JX2.42  IO_L14P_T2_SRCC_13            
-set_property  -dict {PACKAGE_PIN  Y7    IOSTANDARD  LVCMOS25} [get_ports  gp_in[19]]        ; ## JX2.41  IO_L13P_T2_MRCC_13            
-set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD  LVCMOS25} [get_ports  gp_out[20]]       ; ## JX2.44  IO_L14N_T2_SRCC_13            
-set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD  LVCMOS25} [get_ports  gp_in[20]]        ; ## JX2.43  IO_L13N_T2_MRCC_13            
-set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  gp_out[21]]       ; ## JX2.48  IO_L16P_T2_13                 
-set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[21]]        ; ## JX2.47  IO_L15P_T2_DQS_13             
-set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  gp_out[22]]       ; ## JX2.50  IO_L16N_T2_13                 
-set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[22]]        ; ## JX2.49  IO_L15N_T2_DQS_13             
-set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD  LVCMOS25} [get_ports  gp_out[23]]       ; ## JX2.54  IO_L18P_T2_13                 
-set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  gp_in[23]]        ; ## JX2.53  IO_L17P_T2_13                 
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  gp_out[24]]       ; ## JX2.56  IO_L18N_T2_13                 
-set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  gp_in[24]]        ; ## JX2.55  IO_L17N_T2_13                 
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gp_out[25]]       ; ## JX2.62  IO_L20P_T3_13                 
-set_property  -dict {PACKAGE_PIN  T5    IOSTANDARD  LVCMOS25} [get_ports  gp_in[25]]        ; ## JX2.61  IO_L19P_T3_13                 
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gp_out[26]]       ; ## JX2.64  IO_L20N_T3_13                 
-set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD  LVCMOS25} [get_ports  gp_in[26]]        ; ## JX2.63  IO_L19N_T3_VREF_13            
-
-## vcc
-
-set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[0]]    ; ## JX2.18  IO_L6N_T0_VREF_13 
-set_property  -dict {PACKAGE_PIN  V16   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[1]]    ; ## JX4.68  IO_L18P_T2_34                 
-set_property  -dict {PACKAGE_PIN  W16   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[2]]    ; ## JX4.70  IO_L18N_T2_34                 
-set_property  -dict {PACKAGE_PIN  V11   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[3]]    ; ## JX2.67  IO_L21P_T3_DQS_13             
-set_property  -dict {PACKAGE_PIN  V10   IOSTANDARD  LVCMOS25} [get_ports  gp_in_open[4]]    ; ## JX2.69  IO_L21N_T3_DQS_13             
-
-## MIO loopbacks (fixed-io)
-## the following are connected to AD9361 GPIO
-
-##  JX4.86    A23   PS_MIO12_500_JX4    <==>  JX4.2     NA    AD9361_GPO1           
-##  JX4.88    B26   PS_MIO11_500_JX4    <==>  JX4.1     NA    AD9361_GPO0           
-##  JX4.91    B25   PS_MIO13_500_JX4    <==>  JX4.3     NA    AD9361_GPO2           
-##  JX4.93    D23   PS_MIO14_500_JX4    <==>  JX4.4     NA    AD9361_GPO3           
-
-## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
-
-##  JX4.92    E17   PS_MIO46_501_JX4    <==>  JX4.94    B19   PS_MIO47_501_JX4
-
-## the following are mio-to-pl loopback
-
-##  JX4.100   B20   PS_MIO51_501_JX4    <==>  JX4.67    A9    IO_L17P_T2_34             
-##  JX4.85    C24   PS_MIO15_500_JX4    <==>  JX4.37    E5    IO_L7N_T1_34              
-##  JX4.87    A25   PS_MIO10_500_JX4    <==>  JX4.42    E6    IO_L10P_T1_34             
-
-set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[0]]     ; ## JX4.67  IO_L17P_T2_34                 
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[1]]     ; ## JX4.37  IO_L7N_T1_34                  
-set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD  LVCMOS25} [get_ports  gp_in_mio[2]]     ; ## JX4.42  IO_L10P_T1_34                 
-
-
diff --git a/projects/pzsdr1/ccbrk_lvds/system_project.tcl b/projects/pzsdr1/ccbrk_lvds/system_project.tcl
index f43f24109..1a40648ef 100644
--- a/projects/pzsdr1/ccbrk_lvds/system_project.tcl
+++ b/projects/pzsdr1/ccbrk_lvds/system_project.tcl
@@ -3,15 +3,16 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccbrk_lvds_pzsdr1
-adi_project_files ccbrk_lvds_pzsdr1 [list \
-  "system_top.v" \
-  "system_constr.xdc"\
+set p_device "xc7z020clg400-1"
+adi_project_create pzsdr1_ccbrk_lvds
+adi_project_files pzsdr1_ccbrk_lvds [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
+  "../common/pzsdr1_constr.xdc" \
+  "../common/pzsdr1_constr_lvds.xdc" \
+  "../common/ccbrk_constr.xdc" \
+  "system_top.v" ]
 
 set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
-adi_project_run ccbrk_lvds_pzsdr1
+adi_project_run pzsdr1_ccbrk_lvds
 
 
diff --git a/projects/pzsdr1/ccbrk_lvds/system_top.v b/projects/pzsdr1/ccbrk_lvds/system_top.v
index 643b39163..a0032c451 100644
--- a/projects/pzsdr1/ccbrk_lvds/system_top.v
+++ b/projects/pzsdr1/ccbrk_lvds/system_top.v
@@ -39,147 +39,97 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  gpio_bd,
+  inout   [10:0]  gpio_bd,
 
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
 
-  enable,
-  txnrx,
-  clk_out,
+  output          enable,
+  output          txnrx,
+  input           clkout_in,
+  output          clkout_out,
 
-  gpio_clksel,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso,
 
-  gp_out,
-  gp_in,
-  gp_in_mio,
-  gp_in_open);
+  output  [27:0]  gp_out,
+  input   [27:0]  gp_in);
 
 
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  inout   [ 3:0]  gpio_bd;
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  output          enable;
-  output          txnrx;
-  input           clk_out;
-
-  inout           gpio_clksel;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
-
-  output  [26:0]  gp_out;
-  input   [26:0]  gp_in;
-  input   [ 2:0]  gp_in_mio;
-  input   [ 4:0]  gp_in_open;
-
   // internal signals
 
-  wire    [63:0]  gp_out_s;
-  wire    [63:0]  gp_in_s;
+  wire    [31:0]  gp_out_s;
+  wire    [31:0]  gp_in_s;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
   // assignments
 
-  assign gp_out[26:0] = gp_out_s[26:0];
-  assign gp_in_s[34:30] = gp_in_open;
-  assign gp_in_s[29:27] = gp_in_mio;
-  assign gp_in_s[26: 0] = gp_in;
+  assign clkout_out = clkout_in;
+  assign gp_out[27:0] = gp_out_s[27:0];
+  assign gp_in_s[31:28] = gp_out_s[31:28];
+  assign gp_in_s[27: 0] = gp_in[27:0];
 
-  // instantiations
+  // board gpio - 31-0
+
+  assign gpio_i[31:11] = gpio_o[31:11];
+
+  ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd (
+    .dio_t (gpio_t[10:0]),
+    .dio_i (gpio_o[10:0]),
+    .dio_o (gpio_i[10:0]),
+    .dio_p (gpio_bd));
+
+  // ad9361 gpio - 63-32
+
+  assign gpio_i[63:52] = gpio_o[63:52];
+  assign gpio_i[50:47] = gpio_o[50:47];
 
   ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
     .dio_t ({gpio_t[51], gpio_t[46:32]}),
@@ -192,11 +142,7 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_bd (
-    .dio_t (gpio_t[3:0]),
-    .dio_i (gpio_o[3:0]),
-    .dio_o (gpio_i[3:0]),
-    .dio_p (gpio_bd));
+  // instantiations
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
@@ -222,9 +168,7 @@ module system_top (
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
     .gp_in_0 (gp_in_s[31:0]),
-    .gp_in_1 (gp_in_s[63:32]),
     .gp_out_0 (gp_out_s[31:0]),
-    .gp_out_1 (gp_out_s[63:32]),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),

From 4f65bcb3b28f484a4ef39468fa777c0ad74e9612 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 15:32:49 -0500
Subject: [PATCH 724/972] pzsdr1/ccbrk_cmos- updates

---
 projects/pzsdr1/ccbrk_cmos/Makefile           |  17 +-
 projects/pzsdr1/ccbrk_cmos/system_bd.tcl      |  46 +----
 projects/pzsdr1/ccbrk_cmos/system_project.tcl |  15 +-
 projects/pzsdr1/ccbrk_cmos/system_top.v       | 186 +++++++-----------
 4 files changed, 84 insertions(+), 180 deletions(-)

diff --git a/projects/pzsdr1/ccbrk_cmos/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile
index d8b08f86f..b15afc39a 100644
--- a/projects/pzsdr1/ccbrk_cmos/Makefile
+++ b/projects/pzsdr1/ccbrk_cmos/Makefile
@@ -8,17 +8,14 @@
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr1_constr_cmos.xdc
+M_DEPS += ../common/pzsdr1_constr.xdc
+M_DEPS += ../common/pzsdr1_bd.tcl
+M_DEPS += ../common/ccbrk_constr.xdc
 M_DEPS += ../common/ccbrk_bd.tcl
-M_DEPS += ../ccbrk/system_constr.xdc
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
-M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
-M_DEPS += ../../common/pzsdr1/pzsdr1_cmos_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -47,7 +44,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbrk_cmos_pzsdr1.sdk/system_top.hdf
+all: lib pzsdr1_ccbrk_cmos.sdk/system_top.hdf
 
 
 clean: 
@@ -64,9 +61,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbrk_cmos_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
+pzsdr1_ccbrk_cmos.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbrk_cmos_pzsdr1_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr1_ccbrk_cmos_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr1/ccbrk_cmos/system_bd.tcl b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
index 4b39a6ded..624697cbe 100644
--- a/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
+++ b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
@@ -1,48 +1,6 @@
 
-source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_bd.tcl
+source ../common/pzsdr1_bd.tcl
 source ../common/ccbrk_bd.tcl
 
-# CMOS Mode 
-
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_n]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_p]]]
-delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_n]]]
-
-delete_bd_objs [get_bd_ports tx_clk_out_p]
-delete_bd_objs [get_bd_ports tx_clk_out_n]
-delete_bd_objs [get_bd_ports tx_frame_out_p]
-delete_bd_objs [get_bd_ports tx_frame_out_n]
-delete_bd_objs [get_bd_ports tx_data_out_p]
-delete_bd_objs [get_bd_ports tx_data_out_n]
-delete_bd_objs [get_bd_ports rx_clk_in_p]
-delete_bd_objs [get_bd_ports rx_clk_in_n]
-delete_bd_objs [get_bd_ports rx_frame_in_p]
-delete_bd_objs [get_bd_ports rx_frame_in_n]
-delete_bd_objs [get_bd_ports rx_data_in_p]
-delete_bd_objs [get_bd_ports rx_data_in_n]
-
-create_bd_port -dir I rx_clk_in
-create_bd_port -dir I rx_frame_in
-create_bd_port -dir I -from 11 -to 0 rx_data_in
-create_bd_port -dir O tx_clk_out
-create_bd_port -dir O tx_frame_out
-create_bd_port -dir O -from 11 -to 0 tx_data_out
-
-set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
-
-ad_connect  rx_clk_in axi_ad9361/rx_clk_in
-ad_connect  rx_frame_in axi_ad9361/rx_frame_in
-ad_connect  rx_data_in axi_ad9361/rx_data_in
-ad_connect  tx_clk_out axi_ad9361/tx_clk_out
-ad_connect  tx_frame_out axi_ad9361/tx_frame_out
-ad_connect  tx_data_out axi_ad9361/tx_data_out
+cfg_ad9361_interface CMOS
 
diff --git a/projects/pzsdr1/ccbrk_cmos/system_project.tcl b/projects/pzsdr1/ccbrk_cmos/system_project.tcl
index 4ad543633..43da2c3f4 100644
--- a/projects/pzsdr1/ccbrk_cmos/system_project.tcl
+++ b/projects/pzsdr1/ccbrk_cmos/system_project.tcl
@@ -3,15 +3,16 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
 
-adi_project_create ccbrk_cmos_pzsdr1
-adi_project_files ccbrk_cmos_pzsdr1 [list \
-  "system_top.v" \
-  "../ccbrk/system_constr.xdc"\
+set p_device "xc7z020clg400-1"
+adi_project_create pzsdr1_ccbrk_cmos
+adi_project_files pzsdr1_ccbrk_cmos [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc" ]
+  "../common/pzsdr1_constr.xdc" \
+  "../common/pzsdr1_constr_cmos.xdc" \
+  "../common/ccbrk_constr.xdc" \
+  "system_top.v" ]
 
 set_property is_enabled false [get_files  *axi_gpreg_constr.xdc]
-adi_project_run ccbrk_cmos_pzsdr1
+adi_project_run pzsdr1_ccbrk_cmos
 
 
diff --git a/projects/pzsdr1/ccbrk_cmos/system_top.v b/projects/pzsdr1/ccbrk_cmos/system_top.v
index 5407b1081..52fb7cd66 100644
--- a/projects/pzsdr1/ccbrk_cmos/system_top.v
+++ b/projects/pzsdr1/ccbrk_cmos/system_top.v
@@ -39,125 +39,67 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  gpio_bd,
+  inout   [10:0]  gpio_bd,
 
-  rx_clk_in,
-  rx_frame_in,
-  rx_data_in,
-  tx_clk_out,
-  tx_frame_out,
-  tx_data_out,
-  tx_gnd,
+  input           rx_clk_in,
+  input           rx_frame_in,
+  input   [11:0]  rx_data_in,
+  output          tx_clk_out,
+  output          tx_frame_out,
+  output  [11:0]  tx_data_out,
+  output  [ 1:0]  tx_gnd,
 
-  enable,
-  txnrx,
-  clk_out,
+  output          enable,
+  output          txnrx,
+  input           clkout_in,
+  output          clkout_out,
 
-  gpio_clksel,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso,
 
-  gp_out,
-  gp_in,
-  gp_in_mio,
-  gp_in_open);
+  output  [27:0]  gp_out,
+  input   [27:0]  gp_in);
 
 
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  inout   [ 3:0]  gpio_bd;
-
-  input           rx_clk_in;
-  input           rx_frame_in;
-  input   [11:0]  rx_data_in;
-  output          tx_clk_out;
-  output          tx_frame_out;
-  output  [11:0]  tx_data_out;
-  output  [ 1:0]  tx_gnd;
-
-  output          enable;
-  output          txnrx;
-  input           clk_out;
-
-  inout           gpio_clksel;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
-
-  output  [26:0]  gp_out;
-  input   [26:0]  gp_in;
-  input   [ 2:0]  gp_in_mio;
-  input   [ 4:0]  gp_in_open;
-
   // internal signals
 
-  wire    [63:0]  gp_out_s;
-  wire    [63:0]  gp_in_s;
+  wire    [31:0]  gp_out_s;
+  wire    [31:0]  gp_in_s;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
@@ -165,13 +107,25 @@ module system_top (
   // assignments
 
   assign tx_gnd = 2'd0;
+  assign clkout_out = clkout_in;
+  assign gp_out[27:0] = gp_out_s[27:0];
+  assign gp_in_s[31:28] = gp_out_s[31:28];
+  assign gp_in_s[27: 0] = gp_in[27:0];
 
-  assign gp_out[26:0] = gp_out_s[26:0];
-  assign gp_in_s[34:30] = gp_in_open;
-  assign gp_in_s[29:27] = gp_in_mio;
-  assign gp_in_s[26: 0] = gp_in;
+  // board gpio - 31-0
 
-  // instantiations
+  assign gpio_i[31:11] = gpio_o[31:11];
+
+  ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd (
+    .dio_t (gpio_t[10:0]),
+    .dio_i (gpio_o[10:0]),
+    .dio_o (gpio_i[10:0]),
+    .dio_p (gpio_bd));
+
+  // ad9361 gpio - 63-32
+
+  assign gpio_i[63:52] = gpio_o[63:52];
+  assign gpio_i[50:47] = gpio_o[50:47];
 
   ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
     .dio_t ({gpio_t[51], gpio_t[46:32]}),
@@ -184,11 +138,7 @@ module system_top (
               gpio_ctl,           // 43:40
               gpio_status}));     // 39:32
 
-  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_bd (
-    .dio_t (gpio_t[3:0]),
-    .dio_i (gpio_o[3:0]),
-    .dio_o (gpio_i[3:0]),
-    .dio_p (gpio_bd));
+  // instantiations
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
@@ -214,9 +164,7 @@ module system_top (
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
     .gp_in_0 (gp_in_s[31:0]),
-    .gp_in_1 (gp_in_s[63:32]),
     .gp_out_0 (gp_out_s[31:0]),
-    .gp_out_1 (gp_out_s[63:32]),
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),

From 935f8a5c7bc24cff38df9fd1ebcabdb0bf7c7c6f Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 16:13:53 -0500
Subject: [PATCH 725/972] pzsdr1/ccbox- constraints

---
 projects/pzsdr1/common/ccbox_constr.xdc | 72 +++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 projects/pzsdr1/common/ccbox_constr.xdc

diff --git a/projects/pzsdr1/common/ccbox_constr.xdc b/projects/pzsdr1/common/ccbox_constr.xdc
new file mode 100644
index 000000000..a21d62099
--- /dev/null
+++ b/projects/pzsdr1/common/ccbox_constr.xdc
@@ -0,0 +1,72 @@
+
+## constraints (ccbox.a)
+## rf-gpio
+
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD LVCMOS25} [get_ports gpio_rfpwr_enable]  ; ## U1,Y16,IO_L07_34_JX4_P,JX4,35,RF_GPIO4_BANK34
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD LVCMOS25} [get_ports gpio_rf0]           ; ## U1,U12,IO_L02_34_JX4_N,JX4,22,RF_GPIO0_BANK34
+set_property  -dict {PACKAGE_PIN  U13   IOSTANDARD LVCMOS25} [get_ports gpio_rf1]           ; ## U1,U13,IO_L03_34_JX4_P,JX4,25,RF_GPIO1_BANK34
+set_property  -dict {PACKAGE_PIN  T15   IOSTANDARD LVCMOS25} [get_ports gpio_rf2]           ; ## U1,T15,IO_L05_34_JX4_N,JX4,33,RF_GPIO2_BANK34
+set_property  -dict {PACKAGE_PIN  R14   IOSTANDARD LVCMOS25} [get_ports gpio_rf3]           ; ## U1,R14,IO_L06_34_JX4_N,JX4,34,RF_GPIO3_BANK34
+set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD LVCMOS25} [get_ports gpio_rf4]           ; ## U1,W14,IO_L08_34_JX4_P,JX4,36,RF_GPIO5_BANK34
+
+## push-button
+
+set_property  -dict {PACKAGE_PIN  P14   IOSTANDARD  LVCMOS25} [get_ports  ltc2955_kill_n]   ; ## U1,P14,IO_L06_34_JX4_P,JX4,32,LTC2955_KILL_N
+set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD  LVCMOS25} [get_ports  ltc2955_int_n]    ; ## U1,T14,IO_L05_34_JX4_P,JX4,31,LTC2955_INT_N
+
+## oled
+
+set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  oled_csn]         ; ## U1,V5,IO_L06_13_JX2_P,JX2,18,OLED_CS#
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  oled_clk]         ; ## U1,V7,IO_L11_SRCC_13_JX2_N,JX2,37,OLED_SCL
+set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  oled_mosi]        ; ## U1,T9,IO_L12_MRCC_13_JX2_P,JX2,36,OLED_SDI
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  oled_rst]         ; ## U1,U7,IO_L11_SRCC_13_JX2_P,JX2,35,OLED_/RES
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  oled_dc]          ; ## U1,U10,IO_L12_MRCC_13_JX2_N,JX2,38,OLED_D/C
+
+## adp5061
+
+set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[0]]    ; ## U1,T11,IO_L01_34_JX4_P,JX4,19,ADP5061_IO1
+set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[1]]    ; ## U1,T10,IO_L01_34_JX4_N,JX4,21,ADP5061_IO2
+set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[2]]    ; ## U1,T12,IO_L02_34_JX4_P,JX4,20,ADP5061_IO3
+
+## GPS (DATA-UART)
+## U1,C5,PS_MIO14_500_JX4,JX4,93,GPS_TXD1_1V8
+## U1,C8,PS_MIO15_500_JX4,JX4,85,GPS_RXD1_1V8
+
+set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD  LVCMOS25} [get_ports  gps_reset]        ; ## U1,U5,IO_L19_13_JX2_N,JX2,63,GPS_RESET
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gps_force_on]     ; ## U1,Y12,IO_L20_13_JX2_P,JX2,62,GPS_FORCE_ON
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gps_standby]      ; ## U1,Y13,IO_L20_13_JX2_N,JX2,64,GPS_STANDBY
+set_property  -dict {PACKAGE_PIN  T5    IOSTANDARD  LVCMOS25} [get_ports  gps_pps]          ; ## U1,T5,IO_L19_13_JX2_P,JX2,61,GPS_PPS
+
+## imu
+
+set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  imu_csn]          ; ## U1,W10,IO_L16_13_JX2_P,JX2,48,IMU_CS_N
+set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  imu_clk]          ; ## U1,W9,IO_L16_13_JX2_N,JX2,50,IMU_SCLK
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  imu_mosi]         ; ## U1,U9,IO_L17_13_JX2_P,JX2,53,IMU_DIN
+set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  imu_miso]         ; ## U1,Y11,IO_L18_13_JX2_N,JX2,56,IMU_DOUT
+set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  imu_rstn]         ; ## U1,W8,IO_L15_13_JX2_N,JX2,49,IMU_RST_N
+set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD  LVCMOS25} [get_ports  imu_sync]         ; ## U1,W11,IO_L18_13_JX2_P,JX2,54,IMU_SYNC
+set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  imu_ready]        ; ## U1,U8,IO_L17_13_JX2_N,JX2,55,IMU_DR
+
+## audio
+
+set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD  LVCMOS25} [get_ports  i2s_bclk]         ; ## U1,Y6,IO_L13_MRCC_13_JX2_N,JX2,43,AUD_BCLK
+set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD  LVCMOS25} [get_ports  i2s_lrclk]        ; ## U1,Y9,IO_L14_SRCC_13_JX2_P,JX2,42,AUD_LRCLK
+set_property  -dict {PACKAGE_PIN  Y7    IOSTANDARD  LVCMOS25} [get_ports  i2s_mclk]         ; ## U1,Y7,IO_L13_MRCC_13_JX2_P,JX2,41,AUD_MCLK
+set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD  LVCMOS25} [get_ports  i2s_sdata_in]     ; ## U1,Y8,IO_L14_SRCC_13_JX2_N,JX2,44,AUD_SDATA_IN
+set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD  LVCMOS25} [get_ports  i2s_sdata_out]    ; ## U1,V8,IO_L15_13_JX2_P,JX2,47,AUD_SDATA_OUT
+
+set_property  -dict {PACKAGE_PIN  U17   IOSTANDARD  LVCMOS25} [get_ports  mic_present_n]    ; ## U1,U17,IO_L09_34_JX4_N,JX4,43,MIC_PRESENT_N_1V8
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  ts3a227_int_n]    ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,TS3A227_INT_N
+
+## switch-led
+
+set_property  -dict {PACKAGE_PIN  Y14   IOSTANDARD  LVCMOS25} [get_ports  switch_led_r]     ; ## U1,Y14,IO_L08_34_JX4_N,JX4,38,SWITCH_LED_R
+set_property  -dict {PACKAGE_PIN  T16   IOSTANDARD  LVCMOS25} [get_ports  switch_led_g]     ; ## U1,T16,IO_L09_34_JX4_P,JX4,41,SWITCH_LED_G
+set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD  LVCMOS25} [get_ports  switch_led_b]     ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,SWITCH_LED_B
+
+## power source
+
+set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[0]]   ; ## U1,V13,IO_L03_34_JX4_N,JX4,27,PSS_VALID1_N
+set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[1]]   ; ## U1,V12,IO_L04_34_JX4_P,JX4,26,PSS_VALID2_N
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[2]]   ; ## U1,W13,IO_L04_34_JX4_N,JX4,28,PSS_VALID3_N
+

From b62f60b0da27943ca77109324182de3d8193d095 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 17 Nov 2016 16:14:28 -0500
Subject: [PATCH 726/972] pzsdr1/ccbox- updates

---
 projects/pzsdr1/ccbox_lvds/Makefile           | 17 ++---
 projects/pzsdr1/ccbox_lvds/system_bd.tcl      |  4 +-
 projects/pzsdr1/ccbox_lvds/system_constr.xdc  | 71 -------------------
 projects/pzsdr1/ccbox_lvds/system_project.tcl | 15 ++--
 projects/pzsdr1/ccbox_lvds/system_top.v       | 32 ++++++---
 5 files changed, 40 insertions(+), 99 deletions(-)
 delete mode 100644 projects/pzsdr1/ccbox_lvds/system_constr.xdc

diff --git a/projects/pzsdr1/ccbox_lvds/Makefile b/projects/pzsdr1/ccbox_lvds/Makefile
index 8d86c618d..8174aca03 100644
--- a/projects/pzsdr1/ccbox_lvds/Makefile
+++ b/projects/pzsdr1/ccbox_lvds/Makefile
@@ -7,18 +7,15 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr1_constr_lvds.xdc
+M_DEPS += ../common/pzsdr1_constr.xdc
+M_DEPS += ../common/pzsdr1_bd.tcl
+M_DEPS += ../common/ccbox_constr.xdc
 M_DEPS += ../common/ccbox_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr1/pzsdr1_system_constr.xdc
-M_DEPS += ../../common/pzsdr1/pzsdr1_system_bd.tcl
-M_DEPS += ../../common/pzsdr1/pzsdr1_lvds_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -47,7 +44,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccbox_lvds_pzsdr1.sdk/system_top.hdf
+all: lib pzsdr1_ccbox_lvds.sdk/system_top.hdf
 
 
 clean: 
@@ -64,9 +61,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccbox_lvds_pzsdr1.sdk/system_top.hdf: $(M_DEPS)
+pzsdr1_ccbox_lvds.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccbox_lvds_pzsdr1_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr1_ccbox_lvds.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr1/ccbox_lvds/system_bd.tcl b/projects/pzsdr1/ccbox_lvds/system_bd.tcl
index 875b6e891..a870f5764 100644
--- a/projects/pzsdr1/ccbox_lvds/system_bd.tcl
+++ b/projects/pzsdr1/ccbox_lvds/system_bd.tcl
@@ -1,4 +1,6 @@
 
-source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_bd.tcl
+source ../common/pzsdr1_bd.tcl
 source ../common/ccbox_bd.tcl
 
+cfg_ad9361_interface LVDS
+
diff --git a/projects/pzsdr1/ccbox_lvds/system_constr.xdc b/projects/pzsdr1/ccbox_lvds/system_constr.xdc
deleted file mode 100644
index f72968bf4..000000000
--- a/projects/pzsdr1/ccbox_lvds/system_constr.xdc
+++ /dev/null
@@ -1,71 +0,0 @@
-
-# pzsr1 (rev.b) + ccbox (rev.a)
-# rf-gpio
-
-set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[0]]       ; ## JX4.22   IO_L2N_T0_34
-set_property  -dict {PACKAGE_PIN  U13   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[1]]       ; ## JX4.25   IO_L3P_T0_DQS_PUDC_B_34
-set_property  -dict {PACKAGE_PIN  T15   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[2]]       ; ## JX4.33   IO_L5N_T0_34
-set_property  -dict {PACKAGE_PIN  R14   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[3]]       ; ## JX4.34   IO_L6N_T0_VREF_34
-set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[4]]       ; ## JX4.35   IO_L7P_T1_34
-set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD  LVCMOS25} [get_ports  gpio_rf[5]]       ; ## JX4.36   IO_L8P_T1_34
-
-# push-button
-
-set_property  -dict {PACKAGE_PIN  P14   IOSTANDARD  LVCMOS25} [get_ports  ltc2955_kill_n]   ; ## JX4.32   IO_L6P_T0_34
-set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD  LVCMOS25} [get_ports  ltc2955_int_n]    ; ## JX4.31   IO_L5P_T0_34
-
-# oled
-
-set_property  -dict {PACKAGE_PIN  V5    IOSTANDARD  LVCMOS25} [get_ports  oled_csn]         ; ## JX2.18   IO_L6N_T0_VREF_13
-set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD  LVCMOS25} [get_ports  oled_clk]         ; ## JX2.37   IO_L11N_T1_SRCC_13
-set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD  LVCMOS25} [get_ports  oled_mosi]        ; ## JX2.36   IO_L12P_T1_MRCC_13
-set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD  LVCMOS25} [get_ports  oled_rst]         ; ## JX2.35   IO_L11P_T1_SRCC_13
-set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD  LVCMOS25} [get_ports  oled_dc]          ; ## JX2.38   IO_L12N_T1_MRCC_13
-
-# adp5061
-
-set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[0]]    ; ## JX4.19   IO_L1P_T0_34
-set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[1]]    ; ## JX4.21   IO_L1N_T0_34
-set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD  LVCMOS25} [get_ports  adp5061_io[2]]    ; ## JX4.20   IO_L2P_T0_34
-
-# GPS
-
-set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD  LVCMOS25} [get_ports  gps_reset]        ; ## JX2,63   IO_L19N_T3_VREF_13
-set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD  LVCMOS25} [get_ports  gps_force_on]     ; ## JX2,62   IO_L20P_T3_13
-set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD  LVCMOS25} [get_ports  gps_standby]      ; ## JX2,64   IO_L20N_T3_13
-set_property  -dict {PACKAGE_PIN  T5    IOSTANDARD  LVCMOS25} [get_ports  gps_pps]          ; ## JX2,61   IO_L19P_T3_13
-
-# imu
-
-set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD  LVCMOS25} [get_ports  imu_csn]          ; ## JX2,48   IO_L16P_T2_13
-set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD  LVCMOS25} [get_ports  imu_clk]          ; ## JX2,50   IO_L16N_T2_13
-set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD  LVCMOS25} [get_ports  imu_mosi]         ; ## JX2,53   IO_L17P_T2_13
-set_property  -dict {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS25} [get_ports  imu_miso]         ; ## JX2,56   IO_L18N_T2_13
-set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD  LVCMOS25} [get_ports  imu_rstn]         ; ## JX2,49   IO_L15N_T2_DQS_13
-set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD  LVCMOS25} [get_ports  imu_sync]         ; ## JX2,54   IO_L18P_T2_13
-set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD  LVCMOS25} [get_ports  imu_ready]        ; ## JX2,55   IO_L17N_T2_13
-
-# audio
-
-set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD  LVCMOS25} [get_ports  i2s_bclk]         ; ## JX2,43   IO_L13N_T2_MRCC_13
-set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD  LVCMOS25} [get_ports  i2s_lrclk]        ; ## JX2,42   IO_L14P_T2_SRCC_13
-set_property  -dict {PACKAGE_PIN  Y7    IOSTANDARD  LVCMOS25} [get_ports  i2s_mclk]         ; ## JX2,41   IO_L13P_T2_MRCC_13
-set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD  LVCMOS25} [get_ports  i2s_sdata_in]     ; ## JX2,44   IO_L14N_T2_SRCC_13
-set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD  LVCMOS25} [get_ports  i2s_sdata_out]    ; ## JX2,47   IO_L15P_T2_DQS_13
-
-set_property  -dict {PACKAGE_PIN  U17   IOSTANDARD  LVCMOS25} [get_ports  mic_present_n]    ; ## JX4,43   IO_L9N_T1_DQS_34
-set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD  LVCMOS25} [get_ports  ts3a227_int_n]    ; ## JX4,37   IO_L7N_T1_34
-
-# switch-led
-
-set_property  -dict {PACKAGE_PIN  Y14   IOSTANDARD  LVCMOS25} [get_ports  switch_led_r]     ; ## JX4,38   IO_L8N_T1_34
-set_property  -dict {PACKAGE_PIN  T16   IOSTANDARD  LVCMOS25} [get_ports  switch_led_g]     ; ## JX4,41   IO_L9P_T1_DQS_34
-set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD  LVCMOS25} [get_ports  switch_led_b]     ; ## JX4,42   IO_L10P_T1_34
-
-# power source
-
-set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[0]]   ; ## JX4,27   IO_L3N_T0_DQS_34
-set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[1]]   ; ## JX4,26   IO_L4P_T0_34
-set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD  LVCMOS25} [get_ports  pss_valid_n[2]]   ; ## JX4,28   IO_L4N_T0_34
-
-
diff --git a/projects/pzsdr1/ccbox_lvds/system_project.tcl b/projects/pzsdr1/ccbox_lvds/system_project.tcl
index d751a0f29..61ed874fb 100644
--- a/projects/pzsdr1/ccbox_lvds/system_project.tcl
+++ b/projects/pzsdr1/ccbox_lvds/system_project.tcl
@@ -3,14 +3,15 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 source $ad_hdl_dir/projects/scripts/adi_board.tcl 
 
-adi_project_create ccbox_lvds_pzsdr1
-adi_project_files ccbox_lvds_pzsdr1 [list \
-  "system_top.v" \
-  "system_constr.xdc"\
+set p_device "xc7z020clg400-1"
+adi_project_create pzsdr1_ccbox_lvds
+adi_project_files pzsdr1_ccbox_lvds [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc" ]
+  "../common/pzsdr1_constr.xdc" \
+  "../common/pzsdr1_constr_lvds.xdc" \
+  "../common/ccbox_constr.xdc" \
+  "system_top.v" ]
 
-adi_project_run ccbox_lvds_pzsdr1
+adi_project_run pzsdr1_ccbox_lvds
 
 
diff --git a/projects/pzsdr1/ccbox_lvds/system_top.v b/projects/pzsdr1/ccbox_lvds/system_top.v
index 7b51d5d94..30c536868 100644
--- a/projects/pzsdr1/ccbox_lvds/system_top.v
+++ b/projects/pzsdr1/ccbox_lvds/system_top.v
@@ -117,9 +117,14 @@ module system_top (
 
   output          enable,
   output          txnrx,
-  input           clk_out,
+  input           clkout_in,
 
-  inout   [ 5:0]  gpio_rf,
+  inout           gpio_rf0,
+  inout           gpio_rf1,
+  inout           gpio_rf2,
+  inout           gpio_rf3,
+  inout           gpio_rf4,
+  inout           gpio_rfpwr_enable,
   inout           gpio_clksel,
   inout           gpio_resetb,
   inout           gpio_sync,
@@ -142,9 +147,10 @@ module system_top (
 
   assign oled_clk = spi_clk;
   assign oled_mosi = spi_mosi;
-  assign gpio_i[31:24] = gpio_o[31:24];
 
-  // gpio[23:20] controls misc stuff (keep as io)
+  // gpio[31:20] controls misc stuff (keep as io)
+
+  assign gpio_i[31:24] = gpio_o[31:24];
 
   ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_misc (
     .dio_t (gpio_t[23:20]),
@@ -196,16 +202,22 @@ module system_top (
   assign switch_led_b = gpio_o[0];
   assign gpio_i[3:0] = gpio_o[3:0];
 
-  // ad9361 gpio
+  // ad9361 gpio - 63-32
 
-  assign gpio_i[63:58] = gpio_o[63:58];
+  assign gpio_i[63:62] = gpio_o[63:62];
+  assign gpio_i[60:57] = gpio_o[60:57];
   assign gpio_i[50:47] = gpio_o[50:47];
 
   ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
-    .dio_t ({gpio_t[57:51], gpio_t[46:32]}),
-    .dio_i ({gpio_o[57:51], gpio_o[46:32]}),
-    .dio_o ({gpio_i[57:51], gpio_i[46:32]}),
-    .dio_p ({ gpio_rf,            // 57:52
+    .dio_t ({gpio_t[61:61], gpio_t[56:51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[61:61], gpio_o[56:51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[61:61], gpio_i[56:51], gpio_i[46:32]}),
+    .dio_p ({ gpio_rf4,           // 61:61
+              gpio_rf0,           // 56:56
+              gpio_rf1,           // 55:55
+              gpio_rf2,           // 54:54
+              gpio_rf3,           // 53:53
+              gpio_rfpwr_enable,  // 52:52
               gpio_clksel,        // 51:51
               gpio_resetb,        // 46:46
               gpio_sync,          // 45:45

From 0d75bcb6064d76782fd82d3592db1e5d41cb57ca Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 18 Nov 2016 14:02:26 +0100
Subject: [PATCH 727/972] pzsdr2: ccbox: Use DMA interface 0+1 for audio

There is a bug in the ps7 component specification that causes critical
warnings to appear in the build log if DMA interface 0 is disabled, but any
other DMA interface is enabled.

Work around this issue by using DMA interface 0 and 1 instead of 1 and 2
for the I2S DMA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/pzsdr2/common/ccbox_bd.tcl | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/projects/pzsdr2/common/ccbox_bd.tcl b/projects/pzsdr2/common/ccbox_bd.tcl
index a60e9dd58..0b2c89ea0 100644
--- a/projects/pzsdr2/common/ccbox_bd.tcl
+++ b/projects/pzsdr2/common/ccbox_bd.tcl
@@ -8,8 +8,8 @@ ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
 
 set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_USE_DMA2 1 [get_bd_cells sys_ps7]
 
 # i2s
 
@@ -30,14 +30,14 @@ ad_connect  sys_200m_clk sys_audio_clkgen/clk_in1
 ad_connect  sys_cpu_resetn sys_audio_clkgen/resetn
 ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
 ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA0_ACLK
 ad_connect  sys_cpu_clk sys_ps7/DMA1_ACLK
-ad_connect  sys_cpu_clk sys_ps7/DMA2_ACLK
 ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
 ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
-ad_connect  sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
-ad_connect  sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
-ad_connect  sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
-ad_connect  sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
+ad_connect  sys_ps7/DMA0_REQ axi_i2s_adi/DMA_REQ_TX
+ad_connect  sys_ps7/DMA0_ACK axi_i2s_adi/DMA_ACK_TX
+ad_connect  sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_RX
+ad_connect  sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_RX
 ad_connect  sys_audio_clkgen/clk_out1 i2s_mclk
 ad_connect  sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
 ad_connect  i2s axi_i2s_adi/I2S

From 26907ef1fd11a5d151673c825503453c3e9979fe Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 18 Nov 2016 14:50:33 +0100
Subject: [PATCH 728/972] axi_i2s: Remove duplicated clock interface
 association

The I2S interface has a clock associated to it twice, this will generate a
critical warning when using the core, so remove one of them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_i2s_adi/axi_i2s_adi_ip.tcl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
index a64232731..fc2d934db 100644
--- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
+++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
@@ -98,7 +98,6 @@ adi_set_ports_dependency "DMA_REQ_RX_RSTN" \
 	"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
 
 ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core]
-ipx::associate_bus_interfaces -busif I2S -clock i2s_signal_clock [ipx::current_core]
 ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core]
 
 ipx::save_core [ipx::current_core]

From 43c74bf55c25ae3e59e21d2baac4ac6677c6b670 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 18 Nov 2016 14:51:27 +0100
Subject: [PATCH 729/972] axi_i2s: Tie-off optional inputs

Tie-off all optional inputs to 0 so that they are driven to a defined value
when not used.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_i2s_adi/axi_i2s_adi_ip.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
index fc2d934db..d1c2c96cd 100644
--- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
+++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
@@ -100,5 +100,8 @@ adi_set_ports_dependency "DMA_REQ_RX_RSTN" \
 ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core]
 ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core]
 
+# Tie-off optional inputs to 0
+set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}"  -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]
 

From 2f2570fcac5153ac4f5794c4cab829a9e77217bc Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 18 Nov 2016 14:52:07 +0100
Subject: [PATCH 730/972] axi_i2s: Remove incorrectly inferred interfaces

Remove interfaces that were incorrectly inferred by the tools.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_i2s_adi/axi_i2s_adi_ip.tcl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
index d1c2c96cd..bc6dedcde 100644
--- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
+++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
@@ -103,5 +103,11 @@ ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ip
 # Tie-off optional inputs to 0
 set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}"  -of_objects [ipx::current_core]]
 
+# Incorrectly inferred interfaces
+ipx::remove_bus_interface DMA_REQ_TX_RSTN [ipx::current_core]
+ipx::remove_bus_interface DMA_REQ_RX_RSTN [ipx::current_core]
+ipx::remove_bus_interface DMA_REQ_TX_ACLK [ipx::current_core]
+ipx::remove_bus_interface DMA_REQ_RX_ACLK [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 

From f43248c2bcf4527f2371f11e67113488e6a2b6bd Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 18 Nov 2016 11:32:43 -0500
Subject: [PATCH 731/972] common/pzsdr*- removed

---
 .../common/pzsdr/pzsdr_bd_system_constr.xdc   |  16 --
 .../common/pzsdr/pzsdr_cmos_system_constr.xdc |  42 -----
 .../common/pzsdr/pzsdr_lvds_system_constr.xdc |  42 -----
 projects/common/pzsdr/pzsdr_system_bd.tcl     | 163 ------------------
 projects/common/pzsdr/pzsdr_system_constr.xdc |  35 ----
 projects/common/pzsdr/pzsdr_system_ps7.tcl    |  43 -----
 .../pzsdr1/pzsdr1_cmos_system_constr.xdc      |  42 -----
 .../pzsdr1/pzsdr1_lvds_system_constr.xdc      |  42 -----
 projects/common/pzsdr1/pzsdr1_system_bd.tcl   | 163 ------------------
 .../common/pzsdr1/pzsdr1_system_constr.xdc    |  36 ----
 projects/common/pzsdr1/pzsdr1_system_ps7.tcl  |  43 -----
 projects/scripts/adi_project.tcl              |  10 --
 12 files changed, 677 deletions(-)
 delete mode 100644 projects/common/pzsdr/pzsdr_bd_system_constr.xdc
 delete mode 100644 projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
 delete mode 100644 projects/common/pzsdr/pzsdr_lvds_system_constr.xdc
 delete mode 100644 projects/common/pzsdr/pzsdr_system_bd.tcl
 delete mode 100644 projects/common/pzsdr/pzsdr_system_constr.xdc
 delete mode 100755 projects/common/pzsdr/pzsdr_system_ps7.tcl
 delete mode 100644 projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
 delete mode 100644 projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc
 delete mode 100644 projects/common/pzsdr1/pzsdr1_system_bd.tcl
 delete mode 100644 projects/common/pzsdr1/pzsdr1_system_constr.xdc
 delete mode 100755 projects/common/pzsdr1/pzsdr1_system_ps7.tcl

diff --git a/projects/common/pzsdr/pzsdr_bd_system_constr.xdc b/projects/common/pzsdr/pzsdr_bd_system_constr.xdc
deleted file mode 100644
index 1b84e3763..000000000
--- a/projects/common/pzsdr/pzsdr_bd_system_constr.xdc
+++ /dev/null
@@ -1,16 +0,0 @@
-
-# gpio
-
-set_property  -dict {PACKAGE_PIN  J3   IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]                        ; ## (pb)  IO_L12N_T1_MRCC_33
-set_property  -dict {PACKAGE_PIN  D8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]                        ; ## (pb)  IO_L8N_T1_34
-set_property  -dict {PACKAGE_PIN  F9   IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]                        ; ## (pb)  IO_L9P_T1_DQS_34
-set_property  -dict {PACKAGE_PIN  E8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]                        ; ## (pb)  IO_L9N_T1_DQS_34
-set_property  -dict {PACKAGE_PIN  A8   IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]]                        ; ## (led) IO_L17N_T2_34
-set_property  -dict {PACKAGE_PIN  W14  IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]]                        ; ## (led) IO_0_12
-set_property  -dict {PACKAGE_PIN  W17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]                        ; ## (led) IO_25_12
-set_property  -dict {PACKAGE_PIN  Y16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]                        ; ## (led) IO_L23P_T3_12
-set_property  -dict {PACKAGE_PIN  Y15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]]                        ; ## (dip) IO_L23N_T3_12
-set_property  -dict {PACKAGE_PIN  W16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]                        ; ## (dip) IO_L24P_T3_12
-set_property  -dict {PACKAGE_PIN  W15  IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]]                       ; ## (dip) IO_L24N_T3_12
-set_property  -dict {PACKAGE_PIN  V19  IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]                       ; ## (dip) IO_0_13
-
diff --git a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc b/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
deleted file mode 100644
index 35d05f7b9..000000000
--- a/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc
+++ /dev/null
@@ -1,42 +0,0 @@
-
-# constraints
-# ad9361 (SWAP == 0x1)
-
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS18} [get_ports rx_clk_in]       ; ## IO_L12P_T1_MRCC_35
-set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVCMOS18} [get_ports rx_frame_in]     ; ## IO_L7P_T1_AD2P_35
-set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]   ; ## IO_L1N_T0_AD0N_35    
-set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]   ; ## IO_L1P_T0_AD0P_35    
-set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]   ; ## IO_L2N_T0_AD8N_35    
-set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]   ; ## IO_L2P_T0_AD8P_35    
-set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]   ; ## IO_L3N_T0_DQS_AD1N_35
-set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]   ; ## IO_L3P_T0_DQS_AD1P_35
-set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]   ; ## IO_L4N_T0_35         
-set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]   ; ## IO_L4P_T0_35         
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]   ; ## IO_L5N_T0_AD9N_35    
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]   ; ## IO_L5P_T0_AD9P_35    
-set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]  ; ## IO_L6N_T0_VREF_35    
-set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]  ; ## IO_L6P_T0_35         
-
-set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVCMOS18} [get_ports tx_clk_out]      ; ## IO_L8P_T1_AD10P_35
-set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVCMOS18} [get_ports tx_frame_out]    ; ## IO_L9P_T1_DQS_AD3P_35
-set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]  ; ## IO_L13N_T2_MRCC_35     
-set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]  ; ## IO_L13P_T2_MRCC_35     
-set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]  ; ## IO_L14N_T2_AD4N_SRCC_35
-set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]  ; ## IO_L14P_T2_AD4P_SRCC_35
-set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]  ; ## IO_L15N_T2_DQS_AD12N_35
-set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]  ; ## IO_L15P_T2_DQS_AD12P_35
-set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]  ; ## IO_L16N_T2_35          
-set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]  ; ## IO_L16P_T2_35          
-set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]  ; ## IO_L17N_T2_AD5N_35     
-set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]  ; ## IO_L17P_T2_AD5P_35     
-set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L18N_T2_AD13N_35    
-set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L18P_T2_AD13P_35    
-
-set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]]       ; ## IO_L8N_T1_AD10N_35
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]]       ; ## IO_L9N_T1_DQS_AD3N_35
-
-# clocks
-
-create_clock -name rx_clk       -period  8 [get_ports rx_clk_in]
-create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
-
diff --git a/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc b/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc
deleted file mode 100644
index 0d471c6c8..000000000
--- a/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc
+++ /dev/null
@@ -1,42 +0,0 @@
-
-# constraints
-# ad9361
-
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35
-set_property  -dict {PACKAGE_PIN  H14  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35
-set_property  -dict {PACKAGE_PIN  H13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35
-set_property  -dict {PACKAGE_PIN  H12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35
-set_property  -dict {PACKAGE_PIN  F12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35
-set_property  -dict {PACKAGE_PIN  E12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35
-set_property  -dict {PACKAGE_PIN  E10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35
-set_property  -dict {PACKAGE_PIN  D10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35
-set_property  -dict {PACKAGE_PIN  G10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35
-set_property  -dict {PACKAGE_PIN  F10  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35
-set_property  -dict {PACKAGE_PIN  E11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35
-set_property  -dict {PACKAGE_PIN  D11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35
-set_property  -dict {PACKAGE_PIN  G12  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35
-set_property  -dict {PACKAGE_PIN  G11  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35
-set_property  -dict {PACKAGE_PIN  F13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35
-set_property  -dict {PACKAGE_PIN  E13  IOSTANDARD LVDS      DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35
-set_property  -dict {PACKAGE_PIN  K13  IOSTANDARD LVDS}     [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35
-set_property  -dict {PACKAGE_PIN  J13  IOSTANDARD LVDS}     [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35
-set_property  -dict {PACKAGE_PIN  K15  IOSTANDARD LVDS}     [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVDS}     [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35
-set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  D14  IOSTANDARD LVDS}     [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  F15  IOSTANDARD LVDS}     [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35
-set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35
-set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35
-set_property  -dict {PACKAGE_PIN  C16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35
-set_property  -dict {PACKAGE_PIN  E16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35
-set_property  -dict {PACKAGE_PIN  D16  IOSTANDARD LVDS}     [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35
-set_property  -dict {PACKAGE_PIN  B16  IOSTANDARD LVDS}     [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35
-set_property  -dict {PACKAGE_PIN  B15  IOSTANDARD LVDS}     [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35
-set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVDS}     [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35
-set_property  -dict {PACKAGE_PIN  A17  IOSTANDARD LVDS}     [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35
-
-# clocks
-
-create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
-create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
-
diff --git a/projects/common/pzsdr/pzsdr_system_bd.tcl b/projects/common/pzsdr/pzsdr_system_bd.tcl
deleted file mode 100644
index 6c442708f..000000000
--- a/projects/common/pzsdr/pzsdr_system_bd.tcl
+++ /dev/null
@@ -1,163 +0,0 @@
-
-# create board design
-# default ports
-
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
-create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
-
-create_bd_port -dir O spi0_csn_2_o
-create_bd_port -dir O spi0_csn_1_o
-create_bd_port -dir O spi0_csn_0_o
-create_bd_port -dir I spi0_csn_i
-create_bd_port -dir I spi0_clk_i
-create_bd_port -dir O spi0_clk_o
-create_bd_port -dir I spi0_sdo_i
-create_bd_port -dir O spi0_sdo_o
-create_bd_port -dir I spi0_sdi_i
-
-create_bd_port -dir O spi1_csn_2_o
-create_bd_port -dir O spi1_csn_1_o
-create_bd_port -dir O spi1_csn_0_o
-create_bd_port -dir I spi1_csn_i
-create_bd_port -dir I spi1_clk_i
-create_bd_port -dir O spi1_clk_o
-create_bd_port -dir I spi1_sdo_i
-create_bd_port -dir O spi1_sdo_o
-create_bd_port -dir I spi1_sdi_i
-
-create_bd_port -dir I -from 63 -to 0 gpio_i
-create_bd_port -dir O -from 63 -to 0 gpio_o
-create_bd_port -dir O -from 63 -to 0 gpio_t
-
-# otg
-
-set otg_vbusoc      [create_bd_port -dir I otg_vbusoc]
-
-# interrupts
-
-create_bd_port -dir I -type intr ps_intr_00
-create_bd_port -dir I -type intr ps_intr_01
-create_bd_port -dir I -type intr ps_intr_02
-create_bd_port -dir I -type intr ps_intr_03
-create_bd_port -dir I -type intr ps_intr_04
-create_bd_port -dir I -type intr ps_intr_05
-create_bd_port -dir I -type intr ps_intr_06
-create_bd_port -dir I -type intr ps_intr_07
-create_bd_port -dir I -type intr ps_intr_08
-create_bd_port -dir I -type intr ps_intr_09
-create_bd_port -dir I -type intr ps_intr_10
-create_bd_port -dir I -type intr ps_intr_11
-create_bd_port -dir I -type intr ps_intr_12
-create_bd_port -dir I -type intr ps_intr_13
-create_bd_port -dir I -type intr ps_intr_15
-
-# instance: sys_ps7
-
-set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_ps7.tcl
-set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
-
-set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
-set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
-
-set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
-set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
-
-set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
-set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
-
-set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
-set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
-set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
-
-# system reset/clock definitions
-
-ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
-ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
-ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
-ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
-ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
-ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
-
-# interface connections
-
-ad_connect  ddr sys_ps7/DDR
-ad_connect  gpio_i sys_ps7/GPIO_I
-ad_connect  gpio_o sys_ps7/GPIO_O
-ad_connect  gpio_t sys_ps7/GPIO_T
-ad_connect  fixed_io sys_ps7/FIXED_IO
-ad_connect  iic_main axi_iic_main/iic
-ad_connect  sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
-ad_connect  sys_logic_inv/Op1 otg_vbusoc
-
-# spi connections
-
-ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
-ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
-ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
-ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
-ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
-ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
-ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
-ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
-ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
-
-ad_connect  spi1_csn_2_o sys_ps7/SPI1_SS2_O
-ad_connect  spi1_csn_1_o sys_ps7/SPI1_SS1_O
-ad_connect  spi1_csn_0_o sys_ps7/SPI1_SS_O
-ad_connect  spi1_csn_i sys_ps7/SPI1_SS_I
-ad_connect  spi1_clk_i sys_ps7/SPI1_SCLK_I
-ad_connect  spi1_clk_o sys_ps7/SPI1_SCLK_O
-ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
-ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
-ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
-
-# interrupts
-
-ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
-ad_connect  sys_concat_intc/In15 ps_intr_15
-ad_connect  sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
-ad_connect  sys_concat_intc/In13 ps_intr_13
-ad_connect  sys_concat_intc/In12 ps_intr_12
-ad_connect  sys_concat_intc/In11 ps_intr_11
-ad_connect  sys_concat_intc/In10 ps_intr_10
-ad_connect  sys_concat_intc/In9 ps_intr_09
-ad_connect  sys_concat_intc/In8 ps_intr_08
-ad_connect  sys_concat_intc/In7 ps_intr_07
-ad_connect  sys_concat_intc/In6 ps_intr_06
-ad_connect  sys_concat_intc/In5 ps_intr_05
-ad_connect  sys_concat_intc/In4 ps_intr_04
-ad_connect  sys_concat_intc/In3 ps_intr_03
-ad_connect  sys_concat_intc/In2 ps_intr_02
-ad_connect  sys_concat_intc/In1 ps_intr_01
-ad_connect  sys_concat_intc/In0 ps_intr_00
-
-# interconnects
-
-ad_cpu_interconnect 0x41600000 axi_iic_main
-
-# module ad9361
-
-source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
-source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
-
-set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361
-
diff --git a/projects/common/pzsdr/pzsdr_system_constr.xdc b/projects/common/pzsdr/pzsdr_system_constr.xdc
deleted file mode 100644
index 0c941c9bf..000000000
--- a/projects/common/pzsdr/pzsdr_system_constr.xdc
+++ /dev/null
@@ -1,35 +0,0 @@
-
-# constraints
-# ad9361
-
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS18} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35
-set_property  -dict {PACKAGE_PIN  F14  IOSTANDARD LVCMOS18} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35
-
-set_property  -dict {PACKAGE_PIN  D13  IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35
-set_property  -dict {PACKAGE_PIN  C13  IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35
-set_property  -dict {PACKAGE_PIN  C14  IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35
-set_property  -dict {PACKAGE_PIN  B14  IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35
-set_property  -dict {PACKAGE_PIN  A15  IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35
-set_property  -dict {PACKAGE_PIN  A14  IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35
-set_property  -dict {PACKAGE_PIN  C12  IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35
-set_property  -dict {PACKAGE_PIN  B12  IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35
-set_property  -dict {PACKAGE_PIN  C2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34
-set_property  -dict {PACKAGE_PIN  B1   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34
-set_property  -dict {PACKAGE_PIN  B2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34
-set_property  -dict {PACKAGE_PIN  A2   IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34
-set_property  -dict {PACKAGE_PIN  G16  IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35
-set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS18} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35
-set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS18} [get_ports gpio_resetb]                       ; ## IO_0_VRN_35
-set_property  -dict {PACKAGE_PIN  K11  IOSTANDARD LVCMOS18} [get_ports gpio_clksel]                       ; ## IO_0_VRN_34
-
-set_property  -dict {PACKAGE_PIN  C11  IOSTANDARD LVCMOS18  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35
-set_property  -dict {PACKAGE_PIN  B11  IOSTANDARD LVCMOS18} [get_ports spi_clk]                           ; ## IO_L23N_T3_35
-set_property  -dict {PACKAGE_PIN  A13  IOSTANDARD LVCMOS18} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35
-set_property  -dict {PACKAGE_PIN  A12  IOSTANDARD LVCMOS18} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35
-
-set_property  -dict {PACKAGE_PIN  K12  IOSTANDARD LVCMOS18} [get_ports clk_out]                           ; ## IO_25_VRP_35
-
-# iic
-
-set_property  -dict {PACKAGE_PIN  AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L5P_T0_13             
-set_property  -dict {PACKAGE_PIN  AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L5N_T0_13             
diff --git a/projects/common/pzsdr/pzsdr_system_ps7.tcl b/projects/common/pzsdr/pzsdr_system_ps7.tcl
deleted file mode 100755
index fd86195cf..000000000
--- a/projects/common/pzsdr/pzsdr_system_ps7.tcl
+++ /dev/null
@@ -1,43 +0,0 @@
-
-set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_PACKAGE_NAME                              {fbg676}                [get_bd_cells sys_ps7]
-
-set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE                      {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_ENET0_IO                            {MIO 16 .. 27}          [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE                     {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET1_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7] 
-set_property CONFIG.PCW_ENET_RESET_SELECT                         {Separate reset pins}   [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_RESET_ENABLE                        {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_RESET_IO                            {MIO 8}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET1_RESET_ENABLE                        {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET1_RESET_IO                            {MIO 51}                [get_bd_cells sys_ps7]
-
-set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE                     {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_SD0_GRP_CD_ENABLE                         {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_SD0_GRP_CD_IO                             {MIO 50}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ                   {50}                    [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_USB0_RESET_ENABLE                         {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_USB0_RESET_IO                             {MIO 7}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
-
-## DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
-
-set_property CONFIG.PCW_UIPARAM_DDR_PARTNO                        {MT41K256M16 RE-125}    [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH                     {32 Bit}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF             {0}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL             {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE               {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE                {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {-0.053}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {-0.059}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {0.065}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {0.066}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.264}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.265}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.330}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.330}                 [get_bd_cells sys_ps7]
-
diff --git a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
deleted file mode 100644
index 72876707c..000000000
--- a/projects/common/pzsdr1/pzsdr1_cmos_system_constr.xdc
+++ /dev/null
@@ -1,42 +0,0 @@
-
-# constraints
-# ad9361 (SWAP == 0x0)
-
-set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVCMOS25} [get_ports rx_clk_in]                         ; ## IO_L12P_T1_MRCC_35
-set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVCMOS25} [get_ports rx_frame_in]                       ; ## IO_L7P_T1_AD2P_35
-set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVCMOS25} [get_ports rx_data_in[0]]                     ; ## IO_L13N_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVCMOS25} [get_ports rx_data_in[1]]                     ; ## IO_L13P_T2_MRCC_35
-set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[2]]                     ; ## IO_L14N_T2_AD4N_SRCC_35
-set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[3]]                     ; ## IO_L14P_T2_AD4P_SRCC_35
-set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[4]]                     ; ## IO_L15N_T2_DQS_AD12N_35
-set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVCMOS25} [get_ports rx_data_in[5]]                     ; ## IO_L15P_T2_DQS_AD12P_35
-set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVCMOS25} [get_ports rx_data_in[6]]                     ; ## IO_L16N_T2_35
-set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVCMOS25} [get_ports rx_data_in[7]]                     ; ## IO_L16P_T2_35
-set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[8]]                     ; ## IO_L17N_T2_AD5N_35
-set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[9]]                     ; ## IO_L17P_T2_AD5P_35
-set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVCMOS25} [get_ports rx_data_in[10]]                    ; ## IO_L18N_T2_AD13N_35
-set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVCMOS25} [get_ports rx_data_in[11]]                    ; ## IO_L18P_T2_AD13P_35
-
-set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVCMOS25} [get_ports tx_clk_out]                        ; ## IO_L8P_T1_AD10P_35
-set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVCMOS25} [get_ports tx_frame_out]                      ; ## IO_L9P_T1_DQS_AD3P_35
-set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[0]]                    ; ## IO_L1N_T0_AD0N_35
-set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[1]]                    ; ## IO_L1P_T0_AD0P_35
-set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[2]]                    ; ## IO_L2N_T0_AD8N_35
-set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[3]]                    ; ## IO_L2P_T0_AD8P_35
-set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVCMOS25} [get_ports tx_data_out[4]]                    ; ## IO_L3N_T0_DQS_AD1N_35
-set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVCMOS25} [get_ports tx_data_out[5]]                    ; ## IO_L3P_T0_DQS_AD1P_35
-set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVCMOS25} [get_ports tx_data_out[6]]                    ; ## IO_L4N_T0_35
-set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[7]]                    ; ## IO_L4P_T0_35
-set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVCMOS25} [get_ports tx_data_out[8]]                    ; ## IO_L5N_T0_AD9N_35
-set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVCMOS25} [get_ports tx_data_out[9]]                    ; ## IO_L5P_T0_AD9P_35
-set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVCMOS25} [get_ports tx_data_out[10]]                   ; ## IO_L6N_T0_VREF_35
-set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVCMOS25} [get_ports tx_data_out[11]]                   ; ## IO_L6P_T0_35
-
-set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVCMOS25} [get_ports tx_gnd[0]]                         ; ## IO_L8N_T1_AD10N_35
-set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVCMOS25} [get_ports tx_gnd[1]]                         ; ## IO_L9N_T1_DQS_AD3N_35
-
-# clocks
-
-create_clock -name rx_clk       -period  8 [get_ports rx_clk_in]
-create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
-
diff --git a/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc
deleted file mode 100644
index 73bd9923e..000000000
--- a/projects/common/pzsdr1/pzsdr1_lvds_system_constr.xdc
+++ /dev/null
@@ -1,42 +0,0 @@
-
-# constraints
-# ad9361
-
-set_property  -dict {PACKAGE_PIN  K17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_p]       ; ## IO_L12P_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  K18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_clk_in_n]       ; ## IO_L12N_T1_MRCC_35       
-set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_p]     ; ## IO_L7P_T1_AD2P_35        
-set_property  -dict {PACKAGE_PIN  M20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_frame_in_n]     ; ## IO_L7N_T1_AD2N_35        
-set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[0]]   ; ## IO_L1P_T0_AD0P_35        
-set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[0]]   ; ## IO_L1N_T0_AD0N_35        
-set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[1]]   ; ## IO_L2P_T0_AD8P_35        
-set_property  -dict {PACKAGE_PIN  A20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[1]]   ; ## IO_L2N_T0_AD8N_35        
-set_property  -dict {PACKAGE_PIN  E17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[2]]   ; ## IO_L3P_T0_DQS_AD1P_35    
-set_property  -dict {PACKAGE_PIN  D18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[2]]   ; ## IO_L3N_T0_DQS_AD1N_35    
-set_property  -dict {PACKAGE_PIN  D19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[3]]   ; ## IO_L4P_T0_35             
-set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[3]]   ; ## IO_L4N_T0_35             
-set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[4]]   ; ## IO_L5P_T0_AD9P_35        
-set_property  -dict {PACKAGE_PIN  E19  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[4]]   ; ## IO_L5N_T0_AD9N_35        
-set_property  -dict {PACKAGE_PIN  F16  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_p[5]]   ; ## IO_L6P_T0_35             
-set_property  -dict {PACKAGE_PIN  F17  IOSTANDARD LVDS_25   DIFF_TERM TRUE} [get_ports rx_data_in_n[5]]   ; ## IO_L6N_T0_VREF_35        
-set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_p]                      ; ## IO_L8P_T1_AD10P_35       
-set_property  -dict {PACKAGE_PIN  M18  IOSTANDARD LVDS_25}  [get_ports tx_clk_out_n]                      ; ## IO_L8N_T1_AD10N_35       
-set_property  -dict {PACKAGE_PIN  L19  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_p]                    ; ## IO_L9P_T1_DQS_AD3P_35    
-set_property  -dict {PACKAGE_PIN  L20  IOSTANDARD LVDS_25}  [get_ports tx_frame_out_n]                    ; ## IO_L9N_T1_DQS_AD3N_35    
-set_property  -dict {PACKAGE_PIN  H16  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[0]]                  ; ## IO_L13P_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  H17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[0]]                  ; ## IO_L13N_T2_MRCC_35       
-set_property  -dict {PACKAGE_PIN  J18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[1]]                  ; ## IO_L14P_T2_AD4P_SRCC_35  
-set_property  -dict {PACKAGE_PIN  H18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[1]]                  ; ## IO_L14N_T2_AD4N_SRCC_35  
-set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[2]]                  ; ## IO_L15P_T2_DQS_AD12P_35  
-set_property  -dict {PACKAGE_PIN  F20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[2]]                  ; ## IO_L15N_T2_DQS_AD12N_35  
-set_property  -dict {PACKAGE_PIN  G17  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[3]]                  ; ## IO_L16P_T2_35            
-set_property  -dict {PACKAGE_PIN  G18  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[3]]                  ; ## IO_L16N_T2_35            
-set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[4]]                  ; ## IO_L17P_T2_AD5P_35       
-set_property  -dict {PACKAGE_PIN  H20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[4]]                  ; ## IO_L17N_T2_AD5N_35       
-set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVDS_25}  [get_ports tx_data_out_p[5]]                  ; ## IO_L18P_T2_AD13P_35      
-set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_out_n[5]]                  ; ## IO_L18N_T2_AD13N_35      
-
-# clocks
-
-create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
-create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
-
diff --git a/projects/common/pzsdr1/pzsdr1_system_bd.tcl b/projects/common/pzsdr1/pzsdr1_system_bd.tcl
deleted file mode 100644
index 94027513c..000000000
--- a/projects/common/pzsdr1/pzsdr1_system_bd.tcl
+++ /dev/null
@@ -1,163 +0,0 @@
-
-# create board design
-# default ports
-
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
-create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
-
-create_bd_port -dir O spi0_csn_2_o
-create_bd_port -dir O spi0_csn_1_o
-create_bd_port -dir O spi0_csn_0_o
-create_bd_port -dir I spi0_csn_i
-create_bd_port -dir I spi0_clk_i
-create_bd_port -dir O spi0_clk_o
-create_bd_port -dir I spi0_sdo_i
-create_bd_port -dir O spi0_sdo_o
-create_bd_port -dir I spi0_sdi_i
-
-create_bd_port -dir O spi1_csn_2_o
-create_bd_port -dir O spi1_csn_1_o
-create_bd_port -dir O spi1_csn_0_o
-create_bd_port -dir I spi1_csn_i
-create_bd_port -dir I spi1_clk_i
-create_bd_port -dir O spi1_clk_o
-create_bd_port -dir I spi1_sdo_i
-create_bd_port -dir O spi1_sdo_o
-create_bd_port -dir I spi1_sdi_i
-
-create_bd_port -dir I -from 63 -to 0 gpio_i
-create_bd_port -dir O -from 63 -to 0 gpio_o
-create_bd_port -dir O -from 63 -to 0 gpio_t
-
-# otg
-
-set otg_vbusoc      [create_bd_port -dir I otg_vbusoc]
-
-# interrupts
-
-create_bd_port -dir I -type intr ps_intr_00
-create_bd_port -dir I -type intr ps_intr_01
-create_bd_port -dir I -type intr ps_intr_02
-create_bd_port -dir I -type intr ps_intr_03
-create_bd_port -dir I -type intr ps_intr_04
-create_bd_port -dir I -type intr ps_intr_05
-create_bd_port -dir I -type intr ps_intr_06
-create_bd_port -dir I -type intr ps_intr_07
-create_bd_port -dir I -type intr ps_intr_08
-create_bd_port -dir I -type intr ps_intr_09
-create_bd_port -dir I -type intr ps_intr_10
-create_bd_port -dir I -type intr ps_intr_11
-create_bd_port -dir I -type intr ps_intr_12
-create_bd_port -dir I -type intr ps_intr_13
-create_bd_port -dir I -type intr ps_intr_15
-
-# instance: sys_ps7
-
-set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
-source $ad_hdl_dir/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
-set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
-
-set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
-set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
-
-set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
-set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
-
-set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
-set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
-
-set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
-set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
-set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
-
-# system reset/clock definitions
-
-ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
-ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
-ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
-ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
-ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
-ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
-
-# interface connections
-
-ad_connect  ddr sys_ps7/DDR
-ad_connect  gpio_i sys_ps7/GPIO_I
-ad_connect  gpio_o sys_ps7/GPIO_O
-ad_connect  gpio_t sys_ps7/GPIO_T
-ad_connect  fixed_io sys_ps7/FIXED_IO
-ad_connect  iic_main axi_iic_main/iic
-ad_connect  sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
-ad_connect  sys_logic_inv/Op1 otg_vbusoc
-
-# spi connections
-
-ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
-ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
-ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
-ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
-ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
-ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
-ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
-ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
-ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
-
-ad_connect  spi1_csn_2_o sys_ps7/SPI1_SS2_O
-ad_connect  spi1_csn_1_o sys_ps7/SPI1_SS1_O
-ad_connect  spi1_csn_0_o sys_ps7/SPI1_SS_O
-ad_connect  spi1_csn_i sys_ps7/SPI1_SS_I
-ad_connect  spi1_clk_i sys_ps7/SPI1_SCLK_I
-ad_connect  spi1_clk_o sys_ps7/SPI1_SCLK_O
-ad_connect  spi1_sdo_i sys_ps7/SPI1_MOSI_I
-ad_connect  spi1_sdo_o sys_ps7/SPI1_MOSI_O
-ad_connect  spi1_sdi_i sys_ps7/SPI1_MISO_I
-
-# interrupts
-
-ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
-ad_connect  sys_concat_intc/In15 ps_intr_15
-ad_connect  sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
-ad_connect  sys_concat_intc/In13 ps_intr_13
-ad_connect  sys_concat_intc/In12 ps_intr_12
-ad_connect  sys_concat_intc/In11 ps_intr_11
-ad_connect  sys_concat_intc/In10 ps_intr_10
-ad_connect  sys_concat_intc/In9 ps_intr_09
-ad_connect  sys_concat_intc/In8 ps_intr_08
-ad_connect  sys_concat_intc/In7 ps_intr_07
-ad_connect  sys_concat_intc/In6 ps_intr_06
-ad_connect  sys_concat_intc/In5 ps_intr_05
-ad_connect  sys_concat_intc/In4 ps_intr_04
-ad_connect  sys_concat_intc/In3 ps_intr_03
-ad_connect  sys_concat_intc/In2 ps_intr_02
-ad_connect  sys_concat_intc/In1 ps_intr_01
-ad_connect  sys_concat_intc/In0 ps_intr_00
-
-# interconnects
-
-ad_cpu_interconnect 0x41600000 axi_iic_main
-
-# module ad9361
-
-source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
-source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
-
-set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {0}] $axi_ad9361
-
diff --git a/projects/common/pzsdr1/pzsdr1_system_constr.xdc b/projects/common/pzsdr1/pzsdr1_system_constr.xdc
deleted file mode 100644
index 63540970b..000000000
--- a/projects/common/pzsdr1/pzsdr1_system_constr.xdc
+++ /dev/null
@@ -1,36 +0,0 @@
-
-# constraints
-# ad9361
-
-set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35       
-set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35       
-
-set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35            
-set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS25} [get_ports gpio_status[1]]                    ; ## IO_L19N_T3_VREF_35       
-set_property  -dict {PACKAGE_PIN  K14  IOSTANDARD LVCMOS25} [get_ports gpio_status[2]]                    ; ## IO_L20P_T3_AD6P_35       
-set_property  -dict {PACKAGE_PIN  J14  IOSTANDARD LVCMOS25} [get_ports gpio_status[3]]                    ; ## IO_L20N_T3_AD6N_35       
-set_property  -dict {PACKAGE_PIN  N15  IOSTANDARD LVCMOS25} [get_ports gpio_status[4]]                    ; ## IO_L21P_T3_DQS_AD14P_35  
-set_property  -dict {PACKAGE_PIN  N16  IOSTANDARD LVCMOS25} [get_ports gpio_status[5]]                    ; ## IO_L21N_T3_DQS_AD14N_35  
-set_property  -dict {PACKAGE_PIN  L14  IOSTANDARD LVCMOS25} [get_ports gpio_status[6]]                    ; ## IO_L22P_T3_AD7P_35       
-set_property  -dict {PACKAGE_PIN  L15  IOSTANDARD LVCMOS25} [get_ports gpio_status[7]]                    ; ## IO_L22N_T3_AD7N_35       
-set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]]                       ; ## IO_L23P_T3_34            
-set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34            
-set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34            
-set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34            
-set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35      
-set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35      
-set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                       ; ## IO_0_35                  
-set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS25} [get_ports gpio_clksel]                       ; ## IO_0_34                  
-
-set_property  -dict {PACKAGE_PIN  M14  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_csn]          ; ## IO_L23P_T3_35        
-set_property  -dict {PACKAGE_PIN  M15  IOSTANDARD LVCMOS25} [get_ports spi_clk]                           ; ## IO_L23N_T3_35        
-set_property  -dict {PACKAGE_PIN  K16  IOSTANDARD LVCMOS25} [get_ports spi_mosi]                          ; ## IO_L24P_T3_AD15P_35  
-set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS25} [get_ports spi_miso]                          ; ## IO_L24N_T3_AD15N_35  
-
-set_property  -dict {PACKAGE_PIN  J15  IOSTANDARD LVCMOS25} [get_ports clk_out]                           ; ## IO_25_35
-
-# iic
-
-set_property  -dict {PACKAGE_PIN  W6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]           ; ## IO_L22N_T3_13              
-set_property  -dict {PACKAGE_PIN  V6   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]           ; ## IO_L22P_T3_13              
-
diff --git a/projects/common/pzsdr1/pzsdr1_system_ps7.tcl b/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
deleted file mode 100755
index d66e148d7..000000000
--- a/projects/common/pzsdr1/pzsdr1_system_ps7.tcl
+++ /dev/null
@@ -1,43 +0,0 @@
-
-set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE                      {LVCMOS 1.8V}           [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_PACKAGE_NAME                              {fbg676}                [get_bd_cells sys_ps7]
-
-set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE                      {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_ENET0_IO                            {MIO 16 .. 27}          [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE                     {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET1_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7] 
-set_property CONFIG.PCW_ENET_RESET_SELECT                         {Separate reset pins}   [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_RESET_ENABLE                        {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET0_RESET_IO                            {MIO 8}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET1_RESET_ENABLE                        {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_ENET1_RESET_IO                            {MIO 51}                [get_bd_cells sys_ps7]
-
-set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE                     {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_SD0_GRP_CD_ENABLE                         {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_SD0_GRP_CD_IO                             {MIO 50}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ                   {50}                    [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE                   {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_USB0_RESET_ENABLE                         {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_USB0_RESET_IO                             {MIO 7}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE                    {1}                     [get_bd_cells sys_ps7]
-
-## DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
-
-set_property CONFIG.PCW_UIPARAM_DDR_PARTNO                        {MT41K256M16 RE-125}    [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH                     {32 Bit}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF             {0}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL             {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE               {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE                {1}                     [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0            {0.110}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1            {0.095}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2            {0.249}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3            {0.249}                [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0                  {0.202}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1                  {0.217}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2                  {0.216}                 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3                  {0.217}                 [get_bd_cells sys_ps7]
-
diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
index 53de82995..3e61925e5 100644
--- a/projects/scripts/adi_project.tcl
+++ b/projects/scripts/adi_project.tcl
@@ -75,16 +75,6 @@ proc adi_project_create {project_name {mode 0}} {
     set p_board "not-applicable"
     set sys_zynq 1
   }
-  if [regexp "_pzsdr$" $project_name] {
-    set p_device "xc7z035ifbg676-2L"
-    set p_board "not-applicable"
-    set sys_zynq 1
-  }
-  if [regexp "_pzsdr1$" $project_name] {
-    set p_device "xc7z020clg400-1"
-    set p_board "not-applicable"
-    set sys_zynq 1
-  }
   if [regexp "_zcu102$" $project_name] {
     set p_device "xczu9eg-ffvb1156-1-i-es1"
     set p_board "xilinx.com:zcu102:part0:1.2"

From 4739d05269c4af6704b0d82f5e0d57302efc9d07 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 18 Nov 2016 14:52:39 -0500
Subject: [PATCH 732/972] zc706pr/common- removed

---
 projects/common/zc706pr/zc706pr_system_bd.tcl | 3 ---
 1 file changed, 3 deletions(-)
 delete mode 100644 projects/common/zc706pr/zc706pr_system_bd.tcl

diff --git a/projects/common/zc706pr/zc706pr_system_bd.tcl b/projects/common/zc706pr/zc706pr_system_bd.tcl
deleted file mode 100644
index d42c8bd3f..000000000
--- a/projects/common/zc706pr/zc706pr_system_bd.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-
-# place holder for partial reconfiguration bases -- use zc706 base
-

From 69ee410d3d4a8ce4eff915005b2bed97814e5745 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 21 Nov 2016 09:45:10 -0500
Subject: [PATCH 733/972] fmcomms2/zc706pr- bypass pr as default

---
 projects/fmcomms2/common/prcfg_bd.tcl        | 315 ++++++-------------
 projects/fmcomms2/zc706pr/Makefile           |  33 +-
 projects/fmcomms2/zc706pr/system_project.tcl |  26 +-
 projects/fmcomms2/zc706pr/system_top.v       |  55 +++-
 4 files changed, 188 insertions(+), 241 deletions(-)

diff --git a/projects/fmcomms2/common/prcfg_bd.tcl b/projects/fmcomms2/common/prcfg_bd.tcl
index d7313adcc..daf296b9c 100644
--- a/projects/fmcomms2/common/prcfg_bd.tcl
+++ b/projects/fmcomms2/common/prcfg_bd.tcl
@@ -3,238 +3,119 @@
 
 create_bd_port -dir O clk
 
-create_bd_port -dir I  dma_dac_i0_enable
-create_bd_port -dir O  dma_dac_i0_data
-create_bd_port -dir I  dma_dac_i0_valid
-create_bd_port -dir I  dma_dac_q0_enable
-create_bd_port -dir O  dma_dac_q0_data
-create_bd_port -dir I  dma_dac_q0_valid
-create_bd_port -dir I  dma_dac_i1_enable
-create_bd_port -dir O  dma_dac_i1_data
-create_bd_port -dir I  dma_dac_i1_valid
-create_bd_port -dir I  dma_dac_q1_enable
-create_bd_port -dir O  dma_dac_q1_data
-create_bd_port -dir I  dma_dac_q1_valid
 create_bd_port -dir O  core_dac_i0_enable
-create_bd_port -dir I  core_dac_i0_data
-create_bd_port -dir O  core_dac_i0_valid
 create_bd_port -dir O  core_dac_q0_enable
-create_bd_port -dir I  core_dac_q0_data
-create_bd_port -dir O  core_dac_q0_valid
 create_bd_port -dir O  core_dac_i1_enable
-create_bd_port -dir I  core_dac_i1_data
-create_bd_port -dir O  core_dac_i1_valid
 create_bd_port -dir O  core_dac_q1_enable
-create_bd_port -dir I  core_dac_q1_data
+create_bd_port -dir O  core_dac_i0_valid
+create_bd_port -dir O  core_dac_q0_valid
+create_bd_port -dir O  core_dac_i1_valid
 create_bd_port -dir O  core_dac_q1_valid
-create_bd_port -dir I  dma_adc_i0_enable
-create_bd_port -dir I  dma_adc_i0_data
-create_bd_port -dir I  dma_adc_i0_valid
-create_bd_port -dir I  dma_adc_q0_enable
-create_bd_port -dir I  dma_adc_q0_data
-create_bd_port -dir I  dma_adc_q0_valid
-create_bd_port -dir I  dma_adc_i1_enable
-create_bd_port -dir I  dma_adc_i1_data
-create_bd_port -dir I  dma_adc_i1_valid
-create_bd_port -dir I  dma_adc_q1_enable
-create_bd_port -dir I  dma_adc_q1_data
-create_bd_port -dir I  dma_adc_q1_valid
+create_bd_port -dir I  -from 15 -to 0 core_dac_i0_data
+create_bd_port -dir I  -from 15 -to 0 core_dac_q0_data
+create_bd_port -dir I  -from 15 -to 0 core_dac_i1_data
+create_bd_port -dir I  -from 15 -to 0 core_dac_q1_data
+
+create_bd_port -dir I  dma_dac_i0_enable
+create_bd_port -dir I  dma_dac_q0_enable
+create_bd_port -dir I  dma_dac_i1_enable
+create_bd_port -dir I  dma_dac_q1_enable
+create_bd_port -dir I  dma_dac_i0_valid
+create_bd_port -dir I  dma_dac_q0_valid
+create_bd_port -dir I  dma_dac_i1_valid
+create_bd_port -dir I  dma_dac_q1_valid
+create_bd_port -dir O  -from 15 -to 0 dma_dac_i0_data
+create_bd_port -dir O  -from 15 -to 0 dma_dac_q0_data
+create_bd_port -dir O  -from 15 -to 0 dma_dac_i1_data
+create_bd_port -dir O  -from 15 -to 0 dma_dac_q1_data
+
 create_bd_port -dir O  core_adc_i0_enable
-create_bd_port -dir O  core_adc_i0_data
-create_bd_port -dir O  core_adc_i0_valid
 create_bd_port -dir O  core_adc_q0_enable
-create_bd_port -dir O  core_adc_q0_data
-create_bd_port -dir O  core_adc_q0_valid
 create_bd_port -dir O  core_adc_i1_enable
-create_bd_port -dir O  core_adc_i1_data
-create_bd_port -dir O  core_adc_i1_valid
 create_bd_port -dir O  core_adc_q1_enable
-create_bd_port -dir O  core_adc_q1_data
+create_bd_port -dir O  core_adc_i0_valid
+create_bd_port -dir O  core_adc_q0_valid
+create_bd_port -dir O  core_adc_i1_valid
 create_bd_port -dir O  core_adc_q1_valid
+create_bd_port -dir O  -from 15 -to 0 core_adc_i0_data
+create_bd_port -dir O  -from 15 -to 0 core_adc_q0_data
+create_bd_port -dir O  -from 15 -to 0 core_adc_i1_data
+create_bd_port -dir O  -from 15 -to 0 core_adc_q1_data
 
-create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in
-create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in
-create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out
-create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out
+create_bd_port -dir I  dma_adc_i0_enable
+create_bd_port -dir I  dma_adc_q0_enable
+create_bd_port -dir I  dma_adc_i1_enable
+create_bd_port -dir I  dma_adc_q1_enable
+create_bd_port -dir I  dma_adc_i0_valid
+create_bd_port -dir I  dma_adc_q0_valid
+create_bd_port -dir I  dma_adc_i1_valid
+create_bd_port -dir I  dma_adc_q1_valid
+create_bd_port -dir I  -from 15 -to 0 dma_adc_i0_data
+create_bd_port -dir I  -from 15 -to 0 dma_adc_q0_data
+create_bd_port -dir I  -from 15 -to 0 dma_adc_i1_data
+create_bd_port -dir I  -from 15 -to 0 dma_adc_q1_data
 
-# re-wiring
+create_bd_port -dir I  -from 31 -to 0 up_dac_gpio_in
+create_bd_port -dir I  -from 31 -to 0 up_adc_gpio_in
+create_bd_port -dir O  -from 31 -to 0 up_dac_gpio_out
+create_bd_port -dir O  -from 31 -to 0 up_adc_gpio_out
 
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_0]] [get_bd_pins util_ad9361_dac_upack/dac_enable_0]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_0]] [get_bd_pins util_ad9361_dac_upack/dac_valid_0]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_0]] [get_bd_pins util_ad9361_dac_upack/dac_data_0]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_1]] [get_bd_pins util_ad9361_dac_upack/dac_enable_1]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_1]] [get_bd_pins util_ad9361_dac_upack/dac_valid_1]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_1]] [get_bd_pins util_ad9361_dac_upack/dac_data_1]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_2]] [get_bd_pins util_ad9361_dac_upack/dac_enable_2]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_2]] [get_bd_pins util_ad9361_dac_upack/dac_valid_2]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_2]] [get_bd_pins util_ad9361_dac_upack/dac_data_2]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_3]] [get_bd_pins util_ad9361_dac_upack/dac_enable_3]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_3]] [get_bd_pins util_ad9361_dac_upack/dac_valid_3]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_3]] [get_bd_pins util_ad9361_dac_upack/dac_data_3]
+# re-wiring, split between ad9361 core & upack/cpack modules
 
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_0]] [get_bd_pins util_ad9361_adc_pack/adc_enable_0]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_0]] [get_bd_pins util_ad9361_adc_pack/adc_valid_0]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_0]] [get_bd_pins util_ad9361_adc_pack/adc_data_0]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_1]] [get_bd_pins util_ad9361_adc_pack/adc_enable_1]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_1]] [get_bd_pins util_ad9361_adc_pack/adc_valid_1]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_1]] [get_bd_pins util_ad9361_adc_pack/adc_data_1]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_2]] [get_bd_pins util_ad9361_adc_pack/adc_enable_2]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_2]] [get_bd_pins util_ad9361_adc_pack/adc_valid_2]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_2]] [get_bd_pins util_ad9361_adc_pack/adc_data_2]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_3]] [get_bd_pins util_ad9361_adc_pack/adc_enable_3]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_3]] [get_bd_pins util_ad9361_adc_pack/adc_valid_3]
-disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_3]] [get_bd_pins util_ad9361_adc_pack/adc_data_3]
+ad_connect  axi_ad9361_clk clk
 
-ad_connect  clk axi_ad9361/clk
+ad_reconct  util_ad9361_dac_upack/dac_enable_0 dma_dac_i0_enable
+ad_reconct  util_ad9361_dac_upack/dac_enable_1 dma_dac_q0_enable
+ad_reconct  util_ad9361_dac_upack/dac_enable_2 dma_dac_i1_enable
+ad_reconct  util_ad9361_dac_upack/dac_enable_3 dma_dac_q1_enable
+ad_reconct  util_ad9361_dac_upack/dac_valid_0 dma_dac_i0_valid
+ad_reconct  util_ad9361_dac_upack/dac_valid_1 dma_dac_q0_valid
+ad_reconct  util_ad9361_dac_upack/dac_valid_2 dma_dac_i1_valid
+ad_reconct  util_ad9361_dac_upack/dac_valid_3 dma_dac_q1_valid
+ad_reconct  util_ad9361_dac_upack/dac_data_0 dma_dac_i0_data
+ad_reconct  util_ad9361_dac_upack/dac_data_1 dma_dac_q0_data
+ad_reconct  util_ad9361_dac_upack/dac_data_2 dma_dac_i1_data
+ad_reconct  util_ad9361_dac_upack/dac_data_3 dma_dac_q1_data
+ad_reconct  axi_ad9361/dac_enable_i0 core_dac_i0_enable
+ad_reconct  axi_ad9361/dac_enable_q0 core_dac_q0_enable
+ad_reconct  axi_ad9361/dac_enable_i1 core_dac_i1_enable
+ad_reconct  axi_ad9361/dac_enable_q1 core_dac_q1_enable
+ad_reconct  axi_ad9361/dac_valid_i0 core_dac_i0_valid
+ad_reconct  axi_ad9361/dac_valid_q0 core_dac_q0_valid
+ad_reconct  axi_ad9361/dac_valid_i1 core_dac_i1_valid
+ad_reconct  axi_ad9361/dac_valid_q1 core_dac_q1_valid
+ad_reconct  axi_ad9361/dac_data_i0 core_dac_i0_data
+ad_reconct  axi_ad9361/dac_data_q0 core_dac_q0_data
+ad_reconct  axi_ad9361/dac_data_i1 core_dac_i1_data
+ad_reconct  axi_ad9361/dac_data_q1 core_dac_q1_data
 
-# tx data path
-ad_connect  dma_dac_i0_enable util_ad9361_dac_upack/dac_enable_0
-ad_connect  dma_dac_i0_data util_ad9361_dac_upack/dac_data_0
-ad_connect  dma_dac_i0_valid util_ad9361_dac_upack/dac_valid_0
-ad_connect  dma_dac_q0_enable util_ad9361_dac_upack/dac_enable_1
-ad_connect  dma_dac_q0_data util_ad9361_dac_upack/dac_data_1
-ad_connect  dma_dac_q0_valid util_ad9361_dac_upack/dac_valid_1
-ad_connect  dma_dac_i1_enable util_ad9361_dac_upack/dac_enable_2
-ad_connect  dma_dac_i1_data util_ad9361_dac_upack/dac_data_2
-ad_connect  dma_dac_i1_valid util_ad9361_dac_upack/dac_valid_2
-ad_connect  dma_dac_q1_enable util_ad9361_dac_upack/dac_enable_3
-ad_connect  dma_dac_q1_data util_ad9361_dac_upack/dac_data_3
-ad_connect  dma_dac_q1_valid util_ad9361_dac_upack/dac_valid_3
+ad_reconct  util_ad9361_adc_fifo/din_enable_0 dma_adc_i0_enable
+ad_reconct  util_ad9361_adc_fifo/din_enable_1 dma_adc_q0_enable
+ad_reconct  util_ad9361_adc_fifo/din_enable_2 dma_adc_i1_enable
+ad_reconct  util_ad9361_adc_fifo/din_enable_3 dma_adc_q1_enable
+ad_reconct  util_ad9361_adc_fifo/din_valid_0 dma_adc_i0_valid
+ad_reconct  util_ad9361_adc_fifo/din_valid_1 dma_adc_q0_valid
+ad_reconct  util_ad9361_adc_fifo/din_valid_2 dma_adc_i1_valid
+ad_reconct  util_ad9361_adc_fifo/din_valid_3 dma_adc_q1_valid
+ad_reconct  util_ad9361_adc_fifo/din_data_0 dma_adc_i0_data
+ad_reconct  util_ad9361_adc_fifo/din_data_1 dma_adc_q0_data
+ad_reconct  util_ad9361_adc_fifo/din_data_2 dma_adc_i1_data
+ad_reconct  util_ad9361_adc_fifo/din_data_3 dma_adc_q1_data
+ad_reconct  axi_ad9361/adc_enable_i0 core_adc_i0_enable
+ad_reconct  axi_ad9361/adc_enable_q0 core_adc_q0_enable
+ad_reconct  axi_ad9361/adc_enable_i1 core_adc_i1_enable
+ad_reconct  axi_ad9361/adc_enable_q1 core_adc_q1_enable
+ad_reconct  axi_ad9361/adc_valid_i0 core_adc_i0_valid
+ad_reconct  axi_ad9361/adc_valid_q0 core_adc_q0_valid
+ad_reconct  axi_ad9361/adc_valid_i1 core_adc_i1_valid
+ad_reconct  axi_ad9361/adc_valid_q1 core_adc_q1_valid
+ad_reconct  axi_ad9361/adc_data_i0 core_adc_i0_data
+ad_reconct  axi_ad9361/adc_data_q0 core_adc_q0_data
+ad_reconct  axi_ad9361/adc_data_i1 core_adc_i1_data
+ad_reconct  axi_ad9361/adc_data_q1 core_adc_q1_data
 
-ad_connect  core_dac_i0_enable axi_ad9361/dac_enable_i0
-ad_connect  core_dac_i0_data axi_ad9361/dac_data_i0
-ad_connect  core_dac_i0_valid axi_ad9361/dac_valid_i0
-ad_connect  core_dac_q0_enable axi_ad9361/dac_enable_q0
-ad_connect  core_dac_q0_data axi_ad9361/dac_data_q0
-ad_connect  core_dac_q0_valid axi_ad9361/dac_valid_q0
-ad_connect  core_dac_i1_enable axi_ad9361/dac_enable_i1
-ad_connect  core_dac_i1_data axi_ad9361/dac_data_i1
-ad_connect  core_dac_i1_valid axi_ad9361/dac_valid_i1
-ad_connect  core_dac_q1_enable axi_ad9361/dac_enable_q1
-ad_connect  core_dac_q1_data axi_ad9361/dac_data_q1
-ad_connect  core_dac_q1_valid axi_ad9361/dac_valid_q1
-
-# rx data path
-ad_connect  dma_adc_i0_enable util_ad9361_adc_pack/adc_enable_0
-ad_connect  dma_adc_i0_data util_ad9361_adc_pack/adc_data_0
-ad_connect  dma_adc_i0_valid util_ad9361_adc_pack/adc_valid_0
-ad_connect  dma_adc_q0_enable util_ad9361_adc_pack/adc_enable_1
-ad_connect  dma_adc_q0_data util_ad9361_adc_pack/adc_data_1
-ad_connect  dma_adc_q0_valid util_ad9361_adc_pack/adc_valid_1
-ad_connect  dma_adc_i1_enable util_ad9361_adc_pack/adc_enable_2
-ad_connect  dma_adc_i1_data util_ad9361_adc_pack/adc_data_2
-ad_connect  dma_adc_i1_valid util_ad9361_adc_pack/adc_valid_2
-ad_connect  dma_adc_q1_enable util_ad9361_adc_pack/adc_enable_3
-ad_connect  dma_adc_q1_data util_ad9361_adc_pack/adc_data_3
-ad_connect  dma_adc_q1_valid util_ad9361_adc_pack/adc_valid_3
-
-ad_connect  core_adc_i0_enable util_ad9361_adc_fifo/dout_enable_0
-ad_connect  core_adc_i0_data util_ad9361_adc_fifo/dout_data_0
-ad_connect  core_adc_i0_valid util_ad9361_adc_fifo/dout_valid_0
-ad_connect  core_adc_q0_enable util_ad9361_adc_fifo/dout_enable_1
-ad_connect  core_adc_q0_data util_ad9361_adc_fifo/dout_data_1
-ad_connect  core_adc_q0_valid util_ad9361_adc_fifo/dout_valid_1
-ad_connect  core_adc_i1_enable util_ad9361_adc_fifo/dout_enable_2
-ad_connect  core_adc_i1_data util_ad9361_adc_fifo/dout_data_2
-ad_connect  core_adc_i1_valid util_ad9361_adc_fifo/dout_valid_2
-ad_connect  core_adc_q1_enable util_ad9361_adc_fifo/dout_enable_3
-ad_connect  core_adc_q1_data util_ad9361_adc_fifo/dout_data_3
-ad_connect  core_adc_q1_valid util_ad9361_adc_fifo/dout_valid_3
-
-ad_connect  up_dac_gpio_in axi_ad9361/up_dac_gpio_in
-ad_connect  up_adc_gpio_in axi_ad9361/up_adc_gpio_in
-ad_connect  up_dac_gpio_out axi_ad9361/up_dac_gpio_out
-ad_connect  up_adc_gpio_out axi_ad9361/up_adc_gpio_out
-
-# rx side monitoring
-
-set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_0]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_0
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_0
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_0
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_0
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_0
-
-ad_connect  sys_cpu_clk ila_rx_0/clk
-ad_connect  util_ad9361_adc_pack/adc_valid_0 ila_rx_0/probe0
-ad_connect  util_ad9361_adc_pack/adc_data_0 ila_rx_0/probe1
-
-set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_1]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_1
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_1
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_1
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_1
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_1
-
-ad_connect  sys_cpu_clk ila_rx_1/clk
-ad_connect  util_ad9361_adc_pack/adc_valid_0 ila_rx_1/probe0
-ad_connect  util_ad9361_adc_pack/adc_data_0 ila_rx_1/probe1
-
-set ila_rx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_2]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_2
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_2
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_2
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_2
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_2
-
-ad_connect  sys_cpu_clk ila_rx_2/clk
-ad_connect  util_ad9361_adc_pack/adc_valid_0 ila_rx_2/probe0
-ad_connect  util_ad9361_adc_pack/adc_data_0 ila_rx_2/probe1
-
-set ila_rx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_3]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_3
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_3
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_3
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_3
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_3
-
-ad_connect  sys_cpu_clk ila_rx_3/clk
-ad_connect  util_ad9361_adc_pack/adc_valid_0 ila_rx_3/probe0
-ad_connect  util_ad9361_adc_pack/adc_data_0 ila_rx_3/probe1
-
-# rx side monitoring
-
-set ila_tx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_0]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_0
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_0
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_0
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_0
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_0
-
-ad_connect  axi_ad9361/l_clk ila_tx_0/clk
-ad_connect  util_ad9361_adc_fifo/dout_valid_0 ila_tx_0/probe0
-ad_connect  util_ad9361_adc_fifo/dout_data_0 ila_tx_0/probe1
-
-set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_1]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_1
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_1
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_1
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_1
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_1
-
-ad_connect  axi_ad9361/l_clk ila_tx_1/clk
-ad_connect  util_ad9361_adc_fifo/dout_valid_1 ila_tx_1/probe0
-ad_connect  util_ad9361_adc_fifo/dout_data_1 ila_tx_1/probe1
-
-set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_2]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_2
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_2
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_2
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_2
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_2
-
-ad_connect  axi_ad9361/l_clk ila_tx_2/clk
-ad_connect  util_ad9361_adc_fifo/dout_valid_2 ila_tx_2/probe0
-ad_connect  util_ad9361_adc_fifo/dout_data_2 ila_tx_2/probe1
-
-set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_3]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_3
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_3
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_3
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_3
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_3
-
-ad_connect  axi_ad9361/l_clk ila_tx_3/clk
-ad_connect  util_ad9361_adc_fifo/dout_valid_3 ila_tx_3/probe0
-ad_connect  util_ad9361_adc_fifo/dout_data_3 ila_tx_3/probe1
+ad_reconct  axi_ad9361/up_dac_gpio_in up_dac_gpio_in
+ad_reconct  axi_ad9361/up_adc_gpio_in up_adc_gpio_in
+ad_reconct  axi_ad9361/up_dac_gpio_out up_dac_gpio_out
+ad_reconct  axi_ad9361/up_adc_gpio_out up_adc_gpio_out
 
diff --git a/projects/fmcomms2/zc706pr/Makefile b/projects/fmcomms2/zc706pr/Makefile
index 755bcedba..ec1850027 100644
--- a/projects/fmcomms2/zc706pr/Makefile
+++ b/projects/fmcomms2/zc706pr/Makefile
@@ -5,22 +5,30 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := system_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
-M_DEPS += ../zc706/system_bd.tcl
-M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../common/fmcomms2_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zc706/zc706_system_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+M_DEPS += ../zc706/system_bd.tcl
+M_DEPS += ../zc706/system_constr.xdc
+M_DEPS += ../common/prcfg_bd.tcl
+M_DEPS += ../common/prcfg_bb.v
 
 M_VIVADO := vivado -mode batch -source
 
@@ -33,12 +41,15 @@ M_FLIST +=  xgui
 M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
 M_FLIST += .Xil
+M_FLIST += *.ip_user_files
 
 
 
 .PHONY: all lib clean clean-all
-all: lib fmcomms2_zc706pr.sdk/system_top.hdf
+all: lib fmcomms2_zc706.sdk/system_top.hdf
 
 
 clean: 
@@ -52,13 +63,14 @@ clean-all:clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
 
 
-fmcomms2_zc706pr.sdk/system_top.hdf: $(M_DEPS)
-	rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms2_zc706pr_vivado.log 2>&1
+fmcomms2_zc706.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> fmcomms2_zc706_vivado.log 2>&1
 
 
 lib:
@@ -68,6 +80,7 @@ lib:
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
 
diff --git a/projects/fmcomms2/zc706pr/system_project.tcl b/projects/fmcomms2/zc706pr/system_project.tcl
index 2202cb71e..8d60e49bc 100755
--- a/projects/fmcomms2/zc706pr/system_project.tcl
+++ b/projects/fmcomms2/zc706pr/system_project.tcl
@@ -1,10 +1,32 @@
-
-
+## requires  partial reconfiguration license 
 
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
+set mode 0
+if {$::argc > 0} {
+  set mode [lindex $argv 0]
+}
+
+if {$mode == 0} {
+
+  adi_project_create fmcomms2_zc706
+  adi_project_files fmcomms2_zc706 [list \
+    "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
+    "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+    "$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \
+    "$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \
+    "$ad_hdl_dir/library/prcfg/default/prcfg_adc.v" \
+    "../common/prcfg.v" \
+    "../zc706/system_constr.xdc" \
+    "system_top.v" ]
+
+  adi_project_run fmcomms2_zc706
+
+  return
+}
+
 adi_project_create fmcomms2_zc706 1
 adi_project_synth fmcomms2_zc706 "" \
   [list "system_top.v" \
diff --git a/projects/fmcomms2/zc706pr/system_top.v b/projects/fmcomms2/zc706pr/system_top.v
index 2a8fff688..8ebbb1671 100644
--- a/projects/fmcomms2/zc706pr/system_top.v
+++ b/projects/fmcomms2/zc706pr/system_top.v
@@ -88,8 +88,13 @@ module system_top (
   tx_data_out_p,
   tx_data_out_n,
 
-  gpio_txnrx,
-  gpio_enable,
+  enable,
+  txnrx,
+
+  tdd_sync,
+
+  gpio_muxout_tx,
+  gpio_muxout_rx,
   gpio_resetb,
   gpio_sync,
   gpio_en_agc,
@@ -99,7 +104,12 @@ module system_top (
   spi_csn,
   spi_clk,
   spi_mosi,
-  spi_miso);
+  spi_miso,
+
+  spi_udc_csn_tx,
+  spi_udc_csn_rx,
+  spi_udc_sclk,
+  spi_udc_data);
 
   inout   [14:0]  ddr_addr;
   inout   [ 2:0]  ddr_ba;
@@ -150,8 +160,13 @@ module system_top (
   output  [ 5:0]  tx_data_out_p;
   output  [ 5:0]  tx_data_out_n;
 
-  inout           gpio_txnrx;
-  inout           gpio_enable;
+  output          enable;
+  output          txnrx;
+
+  inout           tdd_sync;
+
+  inout           gpio_muxout_tx;
+  inout           gpio_muxout_rx;
   inout           gpio_resetb;
   inout           gpio_sync;
   inout           gpio_en_agc;
@@ -163,12 +178,16 @@ module system_top (
   output          spi_mosi;
   input           spi_miso;
 
+  output          spi_udc_csn_tx;
+  output          spi_udc_csn_rx;
+  output          spi_udc_sclk;
+  output          spi_udc_data;
+
   // internal signals
 
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
-
   wire            clk;
   wire            dma_dac_i0_enable;
   wire    [15:0]  dma_dac_i0_data;
@@ -218,7 +237,6 @@ module system_top (
   wire            core_adc_q1_enable;
   wire    [15:0]  core_adc_q1_data;
   wire            core_adc_q1_valid;
-
   wire    [31:0]  adc_gpio_input;
   wire    [31:0]  adc_gpio_output;
   wire    [31:0]  dac_gpio_input;
@@ -254,6 +272,7 @@ module system_top (
     .dio_p (tdd_sync));
 
   // prcfg instance
+
   prcfg i_prcfg (
     .clk (clk),
     .adc_gpio_input (adc_gpio_input),
@@ -307,8 +326,7 @@ module system_top (
     .core_adc_i1_valid (core_adc_i1_valid),
     .core_adc_q1_enable (core_adc_q1_enable),
     .core_adc_q1_data (core_adc_q1_data),
-    .core_adc_q1_valid (core_adc_q1_valid)
-  );
+    .core_adc_q1_valid (core_adc_q1_valid));
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
@@ -371,13 +389,27 @@ module system_top (
     .spi0_sdi_i (spi_miso),
     .spi0_sdo_i (1'b0),
     .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (spi_udc_sclk),
+    .spi1_csn_0_o (spi_udc_csn_tx),
+    .spi1_csn_1_o (spi_udc_csn_rx),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (spi_udc_data),
+    .spi1_sdo_o (spi_udc_data),
+    .tdd_sync_i (tdd_sync_i),
+    .tdd_sync_o (tdd_sync_o),
+    .tdd_sync_t (tdd_sync_t),
     .tx_clk_out_n (tx_clk_out_n),
     .tx_clk_out_p (tx_clk_out_p),
     .tx_data_out_n (tx_data_out_n),
     .tx_data_out_p (tx_data_out_p),
     .tx_frame_out_n (tx_frame_out_n),
     .tx_frame_out_p (tx_frame_out_p),
-    // pr related ports
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]),
     .clk (clk),
     .up_adc_gpio_in (adc_gpio_input),
     .up_adc_gpio_out (adc_gpio_output),
@@ -430,8 +462,7 @@ module system_top (
     .core_adc_i1_valid (core_adc_i1_valid),
     .core_adc_q1_enable (core_adc_q1_enable),
     .core_adc_q1_data (core_adc_q1_data),
-    .core_adc_q1_valid (core_adc_q1_valid)
-  );
+    .core_adc_q1_valid (core_adc_q1_valid));
 
 endmodule
 

From aff45eae5fac6c0db8aff6223657ec190a070689 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Mon, 21 Nov 2016 18:45:38 +0200
Subject: [PATCH 734/972] fmcadc2: xcvr updates

---
 projects/fmcadc2/common/fmcadc2_bd.tcl    | 171 ++++------------------
 projects/fmcadc2/vc707/Makefile           |   9 +-
 projects/fmcadc2/vc707/system_constr.xdc  |   4 +-
 projects/fmcadc2/vc707/system_project.tcl |   2 -
 projects/fmcadc2/vc707/system_top.v       |  24 ++-
 projects/fmcadc2/zc706/Makefile           |   9 +-
 projects/fmcadc2/zc706/system_constr.xdc  |   4 +-
 projects/fmcadc2/zc706/system_project.tcl |   6 -
 projects/fmcadc2/zc706/system_top.v       |  24 ++-
 9 files changed, 81 insertions(+), 172 deletions(-)

diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl
index 516509a07..aa41370e8 100644
--- a/projects/fmcadc2/common/fmcadc2_bd.tcl
+++ b/projects/fmcadc2/common/fmcadc2_bd.tcl
@@ -1,12 +1,3 @@
-
-# ad9625
-
-create_bd_port -dir I rx_ref_clk
-create_bd_port -dir O rx_sync
-create_bd_port -dir O rx_sysref
-create_bd_port -dir I -from 7 -to 0 rx_data_p
-create_bd_port -dir I -from 7 -to 0 rx_data_n
-
 # adc peripherals
 
 set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
@@ -15,76 +6,10 @@ set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
 
-set axi_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_gt
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad9625_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad9625_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_0 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9625_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_1 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9625_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_2 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9625_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_3 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9625_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_4 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_ad9625_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_5 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_ad9625_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_6 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_ad9625_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.TX_CLK25_DIV_7 {25}] $axi_ad9625_gt
-set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_ad9625_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_ad9625_gt
-
-set util_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9625_gt]
-set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9625_gt
-set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9625_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_ad9625_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9625_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_ad9625_gt
-set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9625_gt
+set axi_ad9625_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_xcvr
 
 set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
@@ -99,76 +24,30 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 
+set util_fmcadc2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc2_xcvr]
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.CPLL_TX_OR_RX_N {0}] $util_fmcadc2_xcvr
+
 # connections (gt)
 
-ad_connect util_ad9625_gt/qpll_ref_clk rx_ref_clk
-ad_connect util_ad9625_gt/cpll_ref_clk rx_ref_clk
-
-ad_connect  axi_ad9625_gt/gt_pll_0 util_ad9625_gt/gt_pll_0
-ad_connect  axi_ad9625_gt/gt_pll_1 util_ad9625_gt/gt_pll_1
-ad_connect  axi_ad9625_gt/gt_pll_2 util_ad9625_gt/gt_pll_2
-ad_connect  axi_ad9625_gt/gt_pll_3 util_ad9625_gt/gt_pll_3
-ad_connect  axi_ad9625_gt/gt_pll_4 util_ad9625_gt/gt_pll_4
-ad_connect  axi_ad9625_gt/gt_pll_5 util_ad9625_gt/gt_pll_5
-ad_connect  axi_ad9625_gt/gt_pll_6 util_ad9625_gt/gt_pll_6
-ad_connect  axi_ad9625_gt/gt_pll_7 util_ad9625_gt/gt_pll_7
-
-ad_connect  axi_ad9625_gt/gt_rx_0 util_ad9625_gt/gt_rx_0
-ad_connect  axi_ad9625_gt/gt_rx_1 util_ad9625_gt/gt_rx_1
-ad_connect  axi_ad9625_gt/gt_rx_2 util_ad9625_gt/gt_rx_2
-ad_connect  axi_ad9625_gt/gt_rx_3 util_ad9625_gt/gt_rx_3
-ad_connect  axi_ad9625_gt/gt_rx_4 util_ad9625_gt/gt_rx_4
-ad_connect  axi_ad9625_gt/gt_rx_5 util_ad9625_gt/gt_rx_5
-ad_connect  axi_ad9625_gt/gt_rx_6 util_ad9625_gt/gt_rx_6
-ad_connect  axi_ad9625_gt/gt_rx_7 util_ad9625_gt/gt_rx_7
-
-ad_connect  axi_ad9625_gt/gt_rx_ip_0 axi_ad9625_jesd/gt0_rx
-ad_connect  axi_ad9625_gt/gt_rx_ip_1 axi_ad9625_jesd/gt1_rx
-ad_connect  axi_ad9625_gt/gt_rx_ip_2 axi_ad9625_jesd/gt2_rx
-ad_connect  axi_ad9625_gt/gt_rx_ip_3 axi_ad9625_jesd/gt3_rx
-ad_connect  axi_ad9625_gt/gt_rx_ip_4 axi_ad9625_jesd/gt4_rx
-ad_connect  axi_ad9625_gt/gt_rx_ip_5 axi_ad9625_jesd/gt5_rx
-ad_connect  axi_ad9625_gt/gt_rx_ip_6 axi_ad9625_jesd/gt6_rx
-ad_connect  axi_ad9625_gt/gt_rx_ip_7 axi_ad9625_jesd/gt7_rx
-
-ad_connect  axi_ad9625_gt/rx_gt_comma_align_enb_0 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_ad9625_gt/rx_gt_comma_align_enb_1 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_ad9625_gt/rx_gt_comma_align_enb_2 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_ad9625_gt/rx_gt_comma_align_enb_3 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_ad9625_gt/rx_gt_comma_align_enb_4 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_ad9625_gt/rx_gt_comma_align_enb_5 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_ad9625_gt/rx_gt_comma_align_enb_6 axi_ad9625_jesd/rxencommaalign_out
-ad_connect  axi_ad9625_gt/rx_gt_comma_align_enb_7 axi_ad9625_jesd/rxencommaalign_out
+ad_xcvrcon  util_fmcadc2_xcvr                 axi_ad9625_xcvr axi_ad9625_jesd
+ad_connect  sys_cpu_resetn                    util_fmcadc2_xcvr/up_rstn
+ad_connect  sys_cpu_clk                       util_fmcadc2_xcvr/up_clk
+ad_connect  util_fmcadc2_xcvr/rx_out_clk_0    axi_ad9625_core/rx_clk
+ad_connect  axi_ad9625_jesd/rx_tdata          axi_ad9625_core/rx_data
+ad_connect  axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof
 
 # connections (adc)
 
-ad_connect  util_ad9625_gt/rx_p         rx_data_p
-ad_connect  util_ad9625_gt/rx_n         rx_data_n
-ad_connect  util_ad9625_gt/rx_sync      rx_sync
-ad_connect  util_ad9625_gt/rx_ip_sysref rx_sysref
-
-ad_connect  util_ad9625_gt/rx_out_clk     util_ad9625_gt/rx_clk
-ad_connect  util_ad9625_gt/rx_out_clk     axi_ad9625_jesd/rx_core_clk
-ad_connect  util_ad9625_gt/rx_ip_rst      axi_ad9625_jesd/rx_reset
-ad_connect  util_ad9625_gt/rx_ip_rst_done axi_ad9625_jesd/rx_reset_done
-ad_connect  util_ad9625_gt/rx_ip_sysref   axi_ad9625_jesd/rx_sysref
-ad_connect  util_ad9625_gt/rx_ip_sync     axi_ad9625_jesd/rx_sync
-ad_connect  util_ad9625_gt/rx_ip_sof      axi_ad9625_jesd/rx_start_of_frame
-ad_connect  util_ad9625_gt/rx_ip_data     axi_ad9625_jesd/rx_tdata
-
-ad_connect  util_ad9625_gt/rx_out_clk axi_ad9625_core/rx_clk
-ad_connect  util_ad9625_gt/rx_data    axi_ad9625_core/rx_data
-
-ad_connect  axi_ad9625_core/adc_clk     axi_ad9625_fifo/adc_clk
-ad_connect  axi_ad9625_fifo/adc_rst     axi_ad9625_core/adc_rst
-ad_connect  axi_ad9625_core/adc_enable  axi_ad9625_fifo/adc_wr
-ad_connect  axi_ad9625_core/adc_data    axi_ad9625_fifo/adc_wdata
-ad_connect  axi_ad9625_core/adc_dovf    axi_ad9625_fifo/adc_wovf
-
-ad_connect  sys_cpu_clk     axi_ad9625_fifo/dma_clk
-ad_connect  sys_cpu_clk     axi_ad9625_dma/s_axis_aclk
-ad_connect  sys_cpu_resetn  axi_ad9625_dma/m_dest_axi_aresetn
-
+ad_connect  sys_cpu_clk                   axi_ad9625_fifo/dma_clk
+ad_connect  sys_cpu_clk                   axi_ad9625_dma/s_axis_aclk
+ad_connect  sys_cpu_resetn                axi_ad9625_dma/m_dest_axi_aresetn
+ad_connect  axi_ad9625_core/adc_clk       axi_ad9625_fifo/adc_clk
+ad_connect  axi_ad9625_fifo/adc_rst       axi_ad9625_core/adc_rst
+ad_connect  axi_ad9625_core/adc_enable    axi_ad9625_fifo/adc_wr
+ad_connect  axi_ad9625_core/adc_data      axi_ad9625_fifo/adc_wdata
+ad_connect  axi_ad9625_core/adc_dovf      axi_ad9625_fifo/adc_wovf
 ad_connect  axi_ad9625_fifo/dma_wr        axi_ad9625_dma/s_axis_valid
 ad_connect  axi_ad9625_fifo/dma_wdata     axi_ad9625_dma/s_axis_data
 ad_connect  axi_ad9625_fifo/dma_wready    axi_ad9625_dma/s_axis_ready
@@ -176,7 +55,7 @@ ad_connect  axi_ad9625_fifo/dma_xfer_req  axi_ad9625_dma/s_axis_xfer_req
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44A60000 axi_ad9625_gt
+ad_cpu_interconnect 0x44A60000 axi_ad9625_xcvr
 ad_cpu_interconnect 0x44A10000 axi_ad9625_core
 ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
@@ -184,7 +63,7 @@ ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
 # gt uses hp3, and 100MHz clock for both DRP and AXI4
 
 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_gt/m_axi
+ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_xcvr/m_axi
 
 # interconnect (mem/adc)
 
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index 6b8d54583..ffb6405ff 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -20,9 +20,10 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -53,9 +54,10 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9625 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_jesd_gt clean
 
 
@@ -66,9 +68,10 @@ fmcadc2_vc707.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9625
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_adcfifo
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc
index 47c95609b..23446dd50 100644
--- a/projects/fmcadc2/vc707/system_constr.xdc
+++ b/projects/fmcadc2/vc707/system_constr.xdc
@@ -38,4 +38,6 @@ set_property  -dict {PACKAGE_PIN  L42  IOSTANDARD LVCMOS18} [get_ports adc_fd]
 # clocks
 
 create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
diff --git a/projects/fmcadc2/vc707/system_project.tcl b/projects/fmcadc2/vc707/system_project.tcl
index b19774007..c6847933e 100644
--- a/projects/fmcadc2/vc707/system_project.tcl
+++ b/projects/fmcadc2/vc707/system_project.tcl
@@ -13,8 +13,6 @@ adi_project_files fmcadc2_vc707 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
-
 adi_project_run fmcadc2_vc707
 
 
diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v
index b87f6073e..b41326be4 100644
--- a/projects/fmcadc2/vc707/system_top.v
+++ b/projects/fmcadc2/vc707/system_top.v
@@ -290,11 +290,25 @@ module system_top (
     .mgt_clk_clk_p (mgt_clk_p),
     .phy_rstn (phy_rstn),
     .phy_sd (1'b1),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_data_4_n (rx_data_n[4]),
+    .rx_data_4_p (rx_data_p[4]),
+    .rx_data_5_n (rx_data_n[5]),
+    .rx_data_5_p (rx_data_p[5]),
+    .rx_data_6_n (rx_data_n[6]),
+    .rx_data_6_p (rx_data_p[6]),
+    .rx_data_7_n (rx_data_n[7]),
+    .rx_data_7_p (rx_data_p[7]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .sgmii_rxn (sgmii_rxn),
     .sgmii_rxp (sgmii_rxp),
     .sgmii_txn (sgmii_txn),
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 6323ddb91..6923f55f3 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -22,11 +22,12 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -58,11 +59,12 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9625 clean
 	make -C ../../../library/xilinx/axi_adcfifo clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_jesd_gt clean
 
 
@@ -74,11 +76,12 @@ fmcadc2_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9625
 	make -C ../../../library/xilinx/axi_adcfifo
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
diff --git a/projects/fmcadc2/zc706/system_constr.xdc b/projects/fmcadc2/zc706/system_constr.xdc
index 785565f42..89fc7716d 100644
--- a/projects/fmcadc2/zc706/system_constr.xdc
+++ b/projects/fmcadc2/zc706/system_constr.xdc
@@ -38,4 +38,6 @@ set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVCMOS25} [get_ports adc_fd]
 # clocks
 
 create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
diff --git a/projects/fmcadc2/zc706/system_project.tcl b/projects/fmcadc2/zc706/system_project.tcl
index af5a50cb7..bd8afbab4 100644
--- a/projects/fmcadc2/zc706/system_project.tcl
+++ b/projects/fmcadc2/zc706/system_project.tcl
@@ -1,6 +1,4 @@
 
-
-
 source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
@@ -14,8 +12,4 @@ adi_project_files fmcadc2_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
-
 adi_project_run fmcadc2_zc706
-
-
diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v
index 69025e3bc..6cd3f5422 100644
--- a/projects/fmcadc2/zc706/system_top.v
+++ b/projects/fmcadc2/zc706/system_top.v
@@ -322,11 +322,25 @@ module system_top (
     .ps_intr_10 (1'b0),
     .ps_intr_11 (1'b0),
     .ps_intr_12 (1'b0),
-    .rx_data_n (rx_data_n),
-    .rx_data_p (rx_data_p),
-    .rx_ref_clk (rx_ref_clk),
-    .rx_sync (rx_sync),
-    .rx_sysref (rx_sysref),
+    .rx_data_0_n (rx_data_n[0]),
+    .rx_data_0_p (rx_data_p[0]),
+    .rx_data_1_n (rx_data_n[1]),
+    .rx_data_1_p (rx_data_p[1]),
+    .rx_data_2_n (rx_data_n[2]),
+    .rx_data_2_p (rx_data_p[2]),
+    .rx_data_3_n (rx_data_n[3]),
+    .rx_data_3_p (rx_data_p[3]),
+    .rx_data_4_n (rx_data_n[4]),
+    .rx_data_4_p (rx_data_p[4]),
+    .rx_data_5_n (rx_data_n[5]),
+    .rx_data_5_p (rx_data_p[5]),
+    .rx_data_6_n (rx_data_n[6]),
+    .rx_data_6_p (rx_data_p[6]),
+    .rx_data_7_n (rx_data_n[7]),
+    .rx_data_7_p (rx_data_p[7]),
+    .rx_ref_clk_0 (rx_ref_clk),
+    .rx_sync_0 (rx_sync),
+    .rx_sysref_0 (rx_sysref),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),

From 3d0049d274ef67feb525fcd0391b2d22ec052d6d Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 22 Nov 2016 16:54:13 +0200
Subject: [PATCH 735/972] pzsdr2: ccusb_lvdsr, updated project for the latest
 schematic

---
 projects/pzsdr2/ccusb_lvds/Makefile           |  17 ++-
 projects/pzsdr2/ccusb_lvds/system_bd.tcl      |   4 +-
 projects/pzsdr2/ccusb_lvds/system_project.tcl |  17 +--
 projects/pzsdr2/ccusb_lvds/system_top.v       |  19 ++-
 .../ccusb_constr.xdc}                         | 114 ++++++++++--------
 5 files changed, 93 insertions(+), 78 deletions(-)
 rename projects/pzsdr2/{ccusb_lvds/system_constr.xdc => common/ccusb_constr.xdc} (50%)

diff --git a/projects/pzsdr2/ccusb_lvds/Makefile b/projects/pzsdr2/ccusb_lvds/Makefile
index 79dff492e..7b700ac07 100644
--- a/projects/pzsdr2/ccusb_lvds/Makefile
+++ b/projects/pzsdr2/ccusb_lvds/Makefile
@@ -7,18 +7,15 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr2_constr_lvds.xdc
+M_DEPS += ../common/pzsdr2_constr.xdc
+M_DEPS += ../common/pzsdr2_bd.tcl
+M_DEPS += ../common/ccusb_constr.xdc
 M_DEPS += ../common/ccusb_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
-M_DEPS += ../../common/xilinx/sys_wfifo.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
-M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
-M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -47,7 +44,7 @@ M_FLIST += *.ip_user_files
 
 
 .PHONY: all lib clean clean-all
-all: lib ccusb_lvds_pzsdr.sdk/system_top.hdf
+all: lib pzsdr2_ccusb_lvds.sdk/system_top.hdf
 
 
 clean: 
@@ -64,9 +61,9 @@ clean-all:clean
 	make -C ../../../library/util_wfifo clean
 
 
-ccusb_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
+pzsdr2_ccusb_lvds.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> ccusb_lvds_pzsdr_vivado.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr2_ccusb_lvds_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr2/ccusb_lvds/system_bd.tcl b/projects/pzsdr2/ccusb_lvds/system_bd.tcl
index a4a35835f..40e1e08b3 100644
--- a/projects/pzsdr2/ccusb_lvds/system_bd.tcl
+++ b/projects/pzsdr2/ccusb_lvds/system_bd.tcl
@@ -1,4 +1,6 @@
 
-source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
+source ../common/pzsdr2_bd.tcl
 source ../common/ccusb_bd.tcl
 
+cfg_ad9361_interface LVDS
+
diff --git a/projects/pzsdr2/ccusb_lvds/system_project.tcl b/projects/pzsdr2/ccusb_lvds/system_project.tcl
index 244812979..e74d1e0cc 100644
--- a/projects/pzsdr2/ccusb_lvds/system_project.tcl
+++ b/projects/pzsdr2/ccusb_lvds/system_project.tcl
@@ -3,17 +3,18 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project_create ccusb_lvds_pzsdr
-adi_project_files ccusb_lvds_pzsdr [list \
+set p_device "xc7z035ifbg676-2L"
+adi_project_create pzsdr2_ccusb_lvds
+adi_project_files pzsdr2_ccusb_lvds [list \
   "system_top.v" \
-  "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
+  "../common/pzsdr2_constr.xdc" \
+  "../common/pzsdr2_constr_lvds.xdc" \
+  "../common/ccusb_constr.xdc" ]
 
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
-set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files ../common/pzsdr2_constr.xdc]
+set_property PROCESSING_ORDER LATE [get_files ../common/ccusb_constr.xdc]
 
-adi_project_run ccusb_lvds_pzsdr
+adi_project_run pzsdr2_ccusb_lvds
 
 
diff --git a/projects/pzsdr2/ccusb_lvds/system_top.v b/projects/pzsdr2/ccusb_lvds/system_top.v
index c865d7b8c..7b136adf6 100644
--- a/projects/pzsdr2/ccusb_lvds/system_top.v
+++ b/projects/pzsdr2/ccusb_lvds/system_top.v
@@ -92,18 +92,21 @@ module system_top (
   input           usb_fx3_uart_tx,
   output          usb_fx3_uart_rx,
 
-  input   [ 3:0]  fifo_rdy,
+  input   [ 7:0]  fifo_rdy,
 
   inout   [31:0]  data,
-  output  [1:0]   addr,
+  output  [ 4:0]  addr,
   output          pclk,
   output          slcs_n,
   output          slrd_n,
   output          sloe_n,
   output          slwr_n,
   output          pktend_n,
+  output          epswitch_n,
 
-  output  [ 1:0]  pmode,
+  output          reset_n,
+
+  output  [ 2:0]  pmode,
 
   output          spi_csn,
   output          spi_clk,
@@ -118,7 +121,11 @@ module system_top (
 
   // assignments
 
-  assign pmode = 2'b11;
+  assign pmode      = 3'b111;
+  assign addr[4:2]  = 3'b000;
+
+  assign epswitch_n = 1'b1;
+  assign reset_n = 1'b1;
 
   // instantiations
 
@@ -213,10 +220,10 @@ module system_top (
     .usb_fx3_uart_rx(usb_fx3_uart_rx),
     .dma_rdy(),
     .dma_wmk(),
-    .fifo_rdy(fifo_rdy),
+    .fifo_rdy(fifo_rdy[3:0]),
     .pclk(pclk),
     .data(data),
-    .addr(addr),
+    .addr(addr[1:0]),
     .slcs_n(slcs_n),
     .slrd_n(slrd_n),
     .sloe_n(sloe_n),
diff --git a/projects/pzsdr2/ccusb_lvds/system_constr.xdc b/projects/pzsdr2/common/ccusb_constr.xdc
similarity index 50%
rename from projects/pzsdr2/ccusb_lvds/system_constr.xdc
rename to projects/pzsdr2/common/ccusb_constr.xdc
index 00a92a674..a0ea05764 100644
--- a/projects/pzsdr2/ccusb_lvds/system_constr.xdc
+++ b/projects/pzsdr2/common/ccusb_constr.xdc
@@ -1,63 +1,71 @@
 # Default constraints have LVCMOS25, overwite it
-set_property  -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl]                                           ; ## IO_L5P_T0_13
-set_property  -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda]                                           ; ## IO_L5N_T0_13
+set_property  -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl]                             ;
+set_property  -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda]                             ;
 
 # USB_FX3
 
-set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports data[0]]        ; ## IO_L01_34_JX4_P
-set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports data[1]]        ; ## IO_L01_34_JX4_N
-set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports data[2]]        ; ## IO_L03_34_JX4_P
-set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports data[3]]        ; ## IO_L03_34_JX4_N
-set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports data[4]]        ; ## IO_L05_34_JX4_P
-set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD LVCMOS18} [get_ports data[5]]        ; ## IO_L05_34_JX4_N
-set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD LVCMOS18} [get_ports data[6]]        ; ## IO_L07_34_JX4_P
-set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD LVCMOS18} [get_ports data[7]]        ; ## IO_L07_34_JX4_N
-set_property  -dict {PACKAGE_PIN  F9    IOSTANDARD LVCMOS18} [get_ports data[8]]        ; ## IO_L09_34_JX4_P
-set_property  -dict {PACKAGE_PIN  E8    IOSTANDARD LVCMOS18} [get_ports data[9]]        ; ## IO_L09_34_JX4_N
-set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD LVCMOS18} [get_ports data[10]]       ; ## IO_L11_SRCC_34_JX4_P
-set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD LVCMOS18} [get_ports data[11]]       ; ## IO_L11_SRCC_34_JX4_N
-set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD LVCMOS18} [get_ports data[12]]       ; ## IO_L13_MRCC_34_JX4_P
-set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD LVCMOS18} [get_ports data[13]]       ; ## IO_L13_MRCC_34_JX4_N
-set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD LVCMOS18} [get_ports data[14]]       ; ## IO_L15_34_JX4_P
-set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD LVCMOS18} [get_ports data[15]]       ; ## IO_L15_34_JX4_N
-set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD LVCMOS18} [get_ports data[16]]       ; ## IO_L06_34_JX4_P
-set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD LVCMOS18} [get_ports data[17]]       ; ## IO_L06_34_JX4_N
-set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD LVCMOS18} [get_ports data[18]]       ; ## IO_L08_34_JX4_P
-set_property  -dict {PACKAGE_PIN  D8    IOSTANDARD LVCMOS18} [get_ports data[19]]       ; ## IO_L08_34_JX4_N
-set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD LVCMOS18} [get_ports data[20]]       ; ## IO_L10_34_JX4_P
-set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD LVCMOS18} [get_ports data[21]]       ; ## IO_L10_34_JX4_N
-set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD LVCMOS18} [get_ports data[22]]       ; ## IO_L12_MRCC_34_JX4_P
-set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD LVCMOS18} [get_ports data[23]]       ; ## IO_L12_MRCC_34_JX4_N
-set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD LVCMOS18} [get_ports data[24]]       ; ## IO_L14_SRCC_34_JX4_P
-set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD LVCMOS18} [get_ports data[25]]       ; ## IO_L14_SRCC_34_JX4_N
-set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD LVCMOS18} [get_ports data[26]]       ; ## IO_L16_34_JX4_P
-set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD LVCMOS18} [get_ports data[27]]       ; ## IO_L16_34_JX4_N
-set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD LVCMOS18} [get_ports data[28]]       ; ## IO_L18_34_JX4_P
-set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD LVCMOS18} [get_ports data[29]]       ; ## IO_L18_34_JX4_N
-set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD LVCMOS18} [get_ports data[30]]       ; ## IO_L20_34_JX4_P
-set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD LVCMOS18} [get_ports data[31]]       ; ## IO_L20_34_JX4_N
+set_property  -dict {PACKAGE_PIN  J11   IOSTANDARD LVCMOS18} [get_ports data[30]]         ;
+set_property  -dict {PACKAGE_PIN  H11   IOSTANDARD LVCMOS18} [get_ports data[31]]         ;
+set_property  -dict {PACKAGE_PIN  H9    IOSTANDARD LVCMOS18} [get_ports data[24]]         ;
+set_property  -dict {PACKAGE_PIN  G9    IOSTANDARD LVCMOS18} [get_ports data[27]]         ;
+set_property  -dict {PACKAGE_PIN  J10   IOSTANDARD LVCMOS18} [get_ports data[26]]         ;
+set_property  -dict {PACKAGE_PIN  J9    IOSTANDARD LVCMOS18} [get_ports data[21]]         ;
+set_property  -dict {PACKAGE_PIN  F5    IOSTANDARD LVCMOS18} [get_ports data[18]]         ;
+set_property  -dict {PACKAGE_PIN  E5    IOSTANDARD LVCMOS18} [get_ports data[19]]         ;
+set_property  -dict {PACKAGE_PIN  F9    IOSTANDARD LVCMOS18} [get_ports data[23]]         ;
+set_property  -dict {PACKAGE_PIN  E8    IOSTANDARD LVCMOS18} [get_ports data[20]]         ;
+set_property  -dict {PACKAGE_PIN  E7    IOSTANDARD LVCMOS18} [get_ports data[2]]          ;
+set_property  -dict {PACKAGE_PIN  C8    IOSTANDARD LVCMOS18} [get_ports data[14]]         ;
+set_property  -dict {PACKAGE_PIN  C7    IOSTANDARD LVCMOS18} [get_ports data[13]]         ;
+set_property  -dict {PACKAGE_PIN  C9    IOSTANDARD LVCMOS18} [get_ports data[9]]          ;
+set_property  -dict {PACKAGE_PIN  B9    IOSTANDARD LVCMOS18} [get_ports data[12]]         ;
+set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD LVCMOS18} [get_ports data[8]]          ;
+set_property  -dict {PACKAGE_PIN  A8    IOSTANDARD LVCMOS18} [get_ports data[7]]          ;
+set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD LVCMOS18} [get_ports data[3]]          ;
+set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD LVCMOS18} [get_ports data[0]]          ;
+set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD LVCMOS18} [get_ports data[4]]          ;
+set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD LVCMOS18} [get_ports data[5]]          ;
+set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports data[28]]         ;
+set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports data[29]]         ;
+set_property  -dict {PACKAGE_PIN  J8    IOSTANDARD LVCMOS18} [get_ports data[25]]         ;
+set_property  -dict {PACKAGE_PIN  D9    IOSTANDARD LVCMOS18} [get_ports data[22]]         ;
+set_property  -dict {PACKAGE_PIN  E6    IOSTANDARD LVCMOS18} [get_ports data[16]]         ;
+set_property  -dict {PACKAGE_PIN  G7    IOSTANDARD LVCMOS18} [get_ports data[17]]         ;
+set_property  -dict {PACKAGE_PIN  D6    IOSTANDARD LVCMOS18} [get_ports data[15]]         ;
+set_property  -dict {PACKAGE_PIN  B10   IOSTANDARD LVCMOS18} [get_ports data[11]]         ;
+set_property  -dict {PACKAGE_PIN  B7    IOSTANDARD LVCMOS18} [get_ports data[10]]         ;
+set_property  -dict {PACKAGE_PIN  B5    IOSTANDARD LVCMOS18} [get_ports data[6]]          ;
+set_property  -dict {PACKAGE_PIN  A4    IOSTANDARD LVCMOS18} [get_ports data[1]]          ;
 
-set_property  -dict {PACKAGE_PIN  A9    IOSTANDARD LVCMOS18} [get_ports pclk]           ; ## IO_L17_34_JX4_P
+set_property  -dict {PACKAGE_PIN  F8    IOSTANDARD LVCMOS18} [get_ports pclk]             ;
 
-set_property  -dict {PACKAGE_PIN  G6    IOSTANDARD LVCMOS18} [get_ports addr[0]]        ; ## IO_L02_34_JX4_P
-set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD LVCMOS18} [get_ports addr[1]]        ; ## IO_L17_13_JX2_P
-#set_property  -dict {PACKAGE_PIN  AD29  IOSTANDARD LVCMOS18} [get_ports addr[2]]        ; ## G34   FMC_LPC_LA31_N
-#set_property  -dict {PACKAGE_PIN  AC29  IOSTANDARD LVCMOS18} [get_ports addr[3]]        ; ## G33   FMC_LPC_LA31_P
-#set_property  -dict {PACKAGE_PIN  AF25  IOSTANDARD LVCMOS18} [get_ports addr[4]]        ; ## G31   FMC_LPC_LA29_N
+set_property  -dict {PACKAGE_PIN  A7    IOSTANDARD LVCMOS18} [get_ports addr[0]]          ;
+set_property  -dict {PACKAGE_PIN  A3    IOSTANDARD LVCMOS18} [get_ports addr[1]]          ;
+set_property  -dict {PACKAGE_PIN  AD19  IOSTANDARD LVCMOS18} [get_ports addr[2]]          ;
+set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD LVCMOS18} [get_ports addr[3]]          ;
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS18} [get_ports addr[4]]          ;
 
-set_property  -dict {PACKAGE_PIN  A8    IOSTANDARD LVCMOS18} [get_ports slcs_n]         ; ## IO_L17_34_JX4_N
-set_property  -dict {PACKAGE_PIN  C4    IOSTANDARD LVCMOS18} [get_ports slwr_n]         ; ## IO_L19_34_JX4_P
-set_property  -dict {PACKAGE_PIN  C3    IOSTANDARD LVCMOS18} [get_ports sloe_n]         ; ## IO_L19_34_JX4_N
-set_property  -dict {PACKAGE_PIN  B6    IOSTANDARD LVCMOS18} [get_ports slrd_n]         ; ## IO_L21_34_JX4_P
-set_property  -dict {PACKAGE_PIN  AD20  IOSTANDARD LVCMOS18} [get_ports pktend_n]       ; ## IO_L13_MRCC_13_JX2_P
+set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS18} [get_ports slcs_n]           ;
+set_property  -dict {PACKAGE_PIN  AF20  IOSTANDARD LVCMOS18} [get_ports slwr_n]           ;
+set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVCMOS18} [get_ports sloe_n]           ;
+set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS18} [get_ports slrd_n]           ;
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS18} [get_ports pktend_n]         ;
 
-set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_tx] ; ## IO_L14_SRCC_13_JX2_N
-set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_rx] ; ## IO_L16_13_JX2_P
+set_property  -dict {PACKAGE_PIN  H8    IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_tx]  ;
+set_property  -dict {PACKAGE_PIN  AC24  IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_rx]  ;
 
-set_property  -dict {PACKAGE_PIN  A5    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[0]]       ; ## IO_L21_34_JX4_N
-set_property  -dict {PACKAGE_PIN  AD23  IOSTANDARD LVCMOS18} [get_ports fifo_rdy[1]]       ; ## IO_L11_SRCC_13_JX2_P
-set_property  -dict {PACKAGE_PIN  AD24  IOSTANDARD LVCMOS18} [get_ports fifo_rdy[2]]       ; ## IO_L11_SRCC_13_JX2_N
-set_property  -dict {PACKAGE_PIN  AD21  IOSTANDARD LVCMOS18} [get_ports fifo_rdy[3]]       ; ## IO_L13_MRCC_13_JX2_N
+set_property  -dict {PACKAGE_PIN  AF19  IOSTANDARD LVCMOS18} [get_ports fifo_rdy[0]]      ;
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD LVCMOS18} [get_ports fifo_rdy[1]]      ;
+set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[2]]      ;
+set_property  -dict {PACKAGE_PIN  H6    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[3]]      ;
+set_property  -dict {PACKAGE_PIN  D8    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[4]]      ;
+set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[5]]      ;
+set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[6]]      ;
+set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[7]]      ;
 
-set_property  -dict {PACKAGE_PIN  G5    IOSTANDARD LVCMOS18} [get_ports pmode[0]]       ; ## IO_L02_34_JX4_N
-set_property  -dict {PACKAGE_PIN  H7    IOSTANDARD LVCMOS18} [get_ports pmode[1]]       ; ## IO_L04_34_JX4_P
+set_property  -dict {PACKAGE_PIN  A10    IOSTANDARD LVCMOS18} [get_ports pmode[0]]        ;
+set_property  -dict {PACKAGE_PIN  K10    IOSTANDARD LVCMOS18} [get_ports pmode[1]]        ;
+set_property  -dict {PACKAGE_PIN  B4     IOSTANDARD LVCMOS18} [get_ports pmode[2]]        ;
+
+set_property  -dict {PACKAGE_PIN  AC23   IOSTANDARD LVCMOS18} [get_ports reset_n]         ;
+set_property  -dict {PACKAGE_PIN  AD18   IOSTANDARD LVCMOS18} [get_ports epswitch_n]      ;

From 8c4279f618af33406a1921f1dbe916107dabf5c7 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 22 Nov 2016 16:58:34 +0200
Subject: [PATCH 736/972] pzsdr1: Added ccusb_lvds initial project

---
 projects/pzsdr1/Makefile                      |   3 +
 projects/pzsdr1/ccusb_lvds/system_bd.tcl      |   6 +
 projects/pzsdr1/ccusb_lvds/system_project.tcl |  20 ++
 projects/pzsdr1/ccusb_lvds/system_top.v       | 238 ++++++++++++++++++
 projects/pzsdr1/common/ccusb_bd.tcl           |  71 ++++++
 projects/pzsdr1/common/ccusb_constr.xdc       |  71 ++++++
 6 files changed, 409 insertions(+)
 create mode 100644 projects/pzsdr1/ccusb_lvds/system_bd.tcl
 create mode 100644 projects/pzsdr1/ccusb_lvds/system_project.tcl
 create mode 100644 projects/pzsdr1/ccusb_lvds/system_top.v
 create mode 100644 projects/pzsdr1/common/ccusb_bd.tcl
 create mode 100644 projects/pzsdr1/common/ccusb_constr.xdc

diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile
index d31684d1c..a7e5f4320 100644
--- a/projects/pzsdr1/Makefile
+++ b/projects/pzsdr1/Makefile
@@ -10,18 +10,21 @@ all:
 	-make -C ccbox_lvds all
 	-make -C ccbrk_cmos all
 	-make -C ccbrk_lvds all
+	-make -C ccusb_lvds all
 
 
 clean: 
 	make -C ccbox_lvds clean
 	make -C ccbrk_cmos clean
 	make -C ccbrk_lvds clean
+	make -C ccusb_lvds clean
 
 
 clean-all:
 	make -C ccbox_lvds clean-all
 	make -C ccbrk_cmos clean-all
 	make -C ccbrk_lvds clean-all
+	make -C ccusb_lvds clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/pzsdr1/ccusb_lvds/system_bd.tcl b/projects/pzsdr1/ccusb_lvds/system_bd.tcl
new file mode 100644
index 000000000..4b0e97a6d
--- /dev/null
+++ b/projects/pzsdr1/ccusb_lvds/system_bd.tcl
@@ -0,0 +1,6 @@
+
+source ../common/pzsdr1_bd.tcl
+source ../common/ccusb_bd.tcl
+
+cfg_ad9361_interface LVDS
+
diff --git a/projects/pzsdr1/ccusb_lvds/system_project.tcl b/projects/pzsdr1/ccusb_lvds/system_project.tcl
new file mode 100644
index 000000000..5567bd97b
--- /dev/null
+++ b/projects/pzsdr1/ccusb_lvds/system_project.tcl
@@ -0,0 +1,20 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+set p_device "xc7z020clg400-1"
+adi_project_create pzsdr1_ccusb_lvds
+adi_project_files pzsdr1_ccusb_lvds [list \
+  "system_top.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "../common/pzsdr1_constr.xdc" \
+  "../common/pzsdr1_constr_lvds.xdc" \
+  "../common/ccusb_constr.xdc" ]
+
+set_property PROCESSING_ORDER EARLY [get_files ../common/pzsdr1_constr.xdc]
+set_property PROCESSING_ORDER LATE [get_files ../common/ccusb_constr.xdc]
+
+adi_project_run pzsdr1_ccusb_lvds
+
+
diff --git a/projects/pzsdr1/ccusb_lvds/system_top.v b/projects/pzsdr1/ccusb_lvds/system_top.v
new file mode 100644
index 000000000..7b136adf6
--- /dev/null
+++ b/projects/pzsdr1/ccusb_lvds/system_top.v
@@ -0,0 +1,238 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout           iic_scl,
+  inout           iic_sda,
+
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
+
+  output          enable,
+  output          txnrx,
+  input           clk_out,
+
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
+
+  input           usb_fx3_uart_tx,
+  output          usb_fx3_uart_rx,
+
+  input   [ 7:0]  fifo_rdy,
+
+  inout   [31:0]  data,
+  output  [ 4:0]  addr,
+  output          pclk,
+  output          slcs_n,
+  output          slrd_n,
+  output          sloe_n,
+  output          slwr_n,
+  output          pktend_n,
+  output          epswitch_n,
+
+  output          reset_n,
+
+  output  [ 2:0]  pmode,
+
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso);
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+
+  assign pmode      = 3'b111;
+  assign addr[4:2]  = 3'b000;
+
+  assign epswitch_n = 1'b1;
+  assign reset_n = 1'b1;
+
+  // instantiations
+
+  ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
+    .dio_t ({gpio_t[51], gpio_t[46:32]}),
+    .dio_i ({gpio_o[51], gpio_o[46:32]}),
+    .dio_o ({gpio_i[51], gpio_i[46:32]}),
+    .dio_p ({ gpio_clksel,        // 51:51
+              gpio_resetb,        // 46:46
+              gpio_sync,          // 45:45
+              gpio_en_agc,        // 44:44
+              gpio_ctl,           // 43:40
+              gpio_status}));     // 39:32
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .enable (enable),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .otg_vbusoc (1'b0),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_clk),
+    .spi0_csn_0_o (spi_csn),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_miso),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .tdd_sync_i (1'b0),
+    .tdd_sync_o (),
+    .tdd_sync_t (),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .txnrx (txnrx),
+    .up_enable (gpio_o[47]),
+    .up_txnrx (gpio_o[48]),
+    .usb_fx3_uart_tx(usb_fx3_uart_tx),
+    .usb_fx3_uart_rx(usb_fx3_uart_rx),
+    .dma_rdy(),
+    .dma_wmk(),
+    .fifo_rdy(fifo_rdy[3:0]),
+    .pclk(pclk),
+    .data(data),
+    .addr(addr[1:0]),
+    .slcs_n(slcs_n),
+    .slrd_n(slrd_n),
+    .sloe_n(sloe_n),
+    .slwr_n(slwr_n),
+    // .epswitch_n(epswitch_n),
+    .pktend_n(pktend_n)
+  );
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/pzsdr1/common/ccusb_bd.tcl b/projects/pzsdr1/common/ccusb_bd.tcl
new file mode 100644
index 000000000..dee7493c1
--- /dev/null
+++ b/projects/pzsdr1/common/ccusb_bd.tcl
@@ -0,0 +1,71 @@
+
+create_bd_port -dir I usb_fx3_uart_tx
+create_bd_port -dir O usb_fx3_uart_rx
+
+create_bd_port -dir I dma_rdy
+create_bd_port -dir I dma_wmk
+create_bd_port -dir I -from 3 -to 0 fifo_rdy
+create_bd_port -dir O pclk
+create_bd_port -dir IO -from 31 -to 0 data
+create_bd_port -dir O -from 1 -to 0 addr
+create_bd_port -dir O slcs_n
+create_bd_port -dir O slrd_n
+create_bd_port -dir O sloe_n
+create_bd_port -dir O slwr_n
+create_bd_port -dir O pktend_n
+create_bd_port -dir O epswitch_n
+
+set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
+set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
+
+set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3]
+
+set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma]
+set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma
+set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
+
+set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ]
+
+ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
+
+ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk
+ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn
+
+ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS
+ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS
+
+ad_connect axi_uart/rx usb_fx3_uart_tx
+ad_connect axi_uart/tx usb_fx3_uart_rx
+
+ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk
+ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn
+
+ad_connect axi_usb_fx3/dma_rdy dma_rdy
+ad_connect axi_usb_fx3/dma_wmk dma_wmk
+ad_connect axi_usb_fx3/fifo_rdy fifo_rdy
+ad_connect axi_usb_fx3/pclk pclk
+ad_connect axi_usb_fx3/data data
+ad_connect axi_usb_fx3/addr addr
+ad_connect axi_usb_fx3/slcs_n slcs_n
+ad_connect axi_usb_fx3/slrd_n slrd_n
+ad_connect axi_usb_fx3/sloe_n sloe_n
+ad_connect axi_usb_fx3/slwr_n slwr_n
+ad_connect axi_usb_fx3/pktend_n pktend_n
+ad_connect axi_usb_fx3/epswitch_n epswitch_n
+
+
+ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
+ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
+ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut
+ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt
+
+ad_cpu_interconnect 0x50000000 axi_usb_fx3
+ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma
+ad_cpu_interconnect 0x40600000 axi_uart
+
+ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
+ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG
+ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S
+ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM
diff --git a/projects/pzsdr1/common/ccusb_constr.xdc b/projects/pzsdr1/common/ccusb_constr.xdc
new file mode 100644
index 000000000..de25d854d
--- /dev/null
+++ b/projects/pzsdr1/common/ccusb_constr.xdc
@@ -0,0 +1,71 @@
+# Default constraints have LVCMOS25, overwite it
+#set_property  -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl]                             ;
+#set_property  -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda]                             ;
+
+# USB_FX3
+
+set_property  -dict {PACKAGE_PIN  T11   IOSTANDARD LVCMOS25} [get_ports data[30]]         ;
+set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD LVCMOS25} [get_ports data[31]]         ;
+set_property  -dict {PACKAGE_PIN  U13   IOSTANDARD LVCMOS25} [get_ports data[24]]         ;
+set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD LVCMOS25} [get_ports data[27]]         ;
+set_property  -dict {PACKAGE_PIN  T14   IOSTANDARD LVCMOS25} [get_ports data[26]]         ;
+set_property  -dict {PACKAGE_PIN  T15   IOSTANDARD LVCMOS25} [get_ports data[21]]         ;
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD LVCMOS25} [get_ports data[18]]         ;
+set_property  -dict {PACKAGE_PIN  Y17   IOSTANDARD LVCMOS25} [get_ports data[19]]         ;
+set_property  -dict {PACKAGE_PIN  T16   IOSTANDARD LVCMOS25} [get_ports data[23]]         ;
+set_property  -dict {PACKAGE_PIN  U17   IOSTANDARD LVCMOS25} [get_ports data[20]]         ;
+set_property  -dict {PACKAGE_PIN  U15   IOSTANDARD LVCMOS25} [get_ports data[2]]          ;
+set_property  -dict {PACKAGE_PIN  N18   IOSTANDARD LVCMOS25} [get_ports data[14]]         ;
+set_property  -dict {PACKAGE_PIN  P19   IOSTANDARD LVCMOS25} [get_ports data[13]]         ;
+set_property  -dict {PACKAGE_PIN  T20   IOSTANDARD LVCMOS25} [get_ports data[9]]          ;
+set_property  -dict {PACKAGE_PIN  U20   IOSTANDARD LVCMOS25} [get_ports data[12]]         ;
+set_property  -dict {PACKAGE_PIN  Y18   IOSTANDARD LVCMOS25} [get_ports data[8]]          ;
+set_property  -dict {PACKAGE_PIN  Y19   IOSTANDARD LVCMOS25} [get_ports data[7]]          ;
+set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD LVCMOS25} [get_ports data[3]]          ;
+set_property  -dict {PACKAGE_PIN  R17   IOSTANDARD LVCMOS25} [get_ports data[0]]          ;
+set_property  -dict {PACKAGE_PIN  V17   IOSTANDARD LVCMOS25} [get_ports data[4]]          ;
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD LVCMOS25} [get_ports data[5]]          ;
+set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD LVCMOS25} [get_ports data[28]]         ;
+set_property  -dict {PACKAGE_PIN  V12   IOSTANDARD LVCMOS25} [get_ports data[29]]         ;
+set_property  -dict {PACKAGE_PIN  P14   IOSTANDARD LVCMOS25} [get_ports data[25]]         ;
+set_property  -dict {PACKAGE_PIN  W14   IOSTANDARD LVCMOS25} [get_ports data[22]]         ;
+set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD LVCMOS25} [get_ports data[16]]         ;
+set_property  -dict {PACKAGE_PIN  U18   IOSTANDARD LVCMOS25} [get_ports data[17]]         ;
+set_property  -dict {PACKAGE_PIN  N20   IOSTANDARD LVCMOS25} [get_ports data[15]]         ;
+set_property  -dict {PACKAGE_PIN  V20   IOSTANDARD LVCMOS25} [get_ports data[11]]         ;
+set_property  -dict {PACKAGE_PIN  V16   IOSTANDARD LVCMOS25} [get_ports data[10]]         ;
+set_property  -dict {PACKAGE_PIN  T17   IOSTANDARD LVCMOS25} [get_ports data[6]]          ;
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS25} [get_ports data[1]]          ;
+
+set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD LVCMOS25} [get_ports pclk]             ;
+
+set_property  -dict {PACKAGE_PIN  W16   IOSTANDARD LVCMOS25} [get_ports addr[0]]          ;
+set_property  -dict {PACKAGE_PIN  W19   IOSTANDARD LVCMOS25} [get_ports addr[1]]          ;
+set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD LVCMOS25} [get_ports addr[2]]          ;
+set_property  -dict {PACKAGE_PIN  Y7    IOSTANDARD LVCMOS25} [get_ports addr[3]]          ;
+set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD LVCMOS25} [get_ports addr[4]]          ;
+
+set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD LVCMOS25} [get_ports slcs_n]           ;
+set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD LVCMOS25} [get_ports slwr_n]           ;
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD LVCMOS25} [get_ports sloe_n]           ;
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD LVCMOS25} [get_ports slrd_n]           ;
+set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD LVCMOS25} [get_ports pktend_n]         ;
+
+set_property  -dict {PACKAGE_PIN  R14   IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_tx]  ;
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_rx]  ;
+
+set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD LVCMOS25} [get_ports fifo_rdy[0]]      ;
+set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD LVCMOS25} [get_ports fifo_rdy[1]]      ;
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD LVCMOS25} [get_ports fifo_rdy[2]]      ;
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD LVCMOS25} [get_ports fifo_rdy[3]]      ;
+set_property  -dict {PACKAGE_PIN  Y14   IOSTANDARD LVCMOS25} [get_ports fifo_rdy[4]]      ;
+set_property  -dict {PACKAGE_PIN  W15   IOSTANDARD LVCMOS25} [get_ports fifo_rdy[5]]      ;
+set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD LVCMOS25} [get_ports fifo_rdy[6]]      ;
+set_property  -dict {PACKAGE_PIN  P20   IOSTANDARD LVCMOS25} [get_ports fifo_rdy[7]]      ;
+
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports pmode[0]]         ;
+set_property  -dict {PACKAGE_PIN  T19   IOSTANDARD LVCMOS25} [get_ports pmode[1]]         ;
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD LVCMOS25} [get_ports pmode[2]]         ;
+
+set_property  -dict {PACKAGE_PIN  T9    IOSTANDARD LVCMOS25} [get_ports reset_n]          ;
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD LVCMOS25} [get_ports epswitch_n]       ;

From 4ed7469286ae27c50a3347982191e72da953ca50 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 10:31:55 -0500
Subject: [PATCH 737/972] fmcadc4/zc706- updates

---
 projects/fmcadc4/common/fmcadc4_bd.tcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl
index 5c70a6179..0e7ac1c88 100644
--- a/projects/fmcadc4/common/fmcadc4_bd.tcl
+++ b/projects/fmcadc4/common/fmcadc4_bd.tcl
@@ -38,6 +38,8 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9680_cpack
 
 set util_fmcadc4_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc4_xcvr]
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc4_xcvr
+set_property -dict [list CONFIG.CPLL_TX_OR_RX_N {1}] $util_fmcadc4_xcvr
 
 create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_data
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {128}] [get_bd_cells util_bsplit_rx_data]

From b9795c70330edfede8099559a4a6da0e35c3a383 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 22 Nov 2016 17:33:40 +0200
Subject: [PATCH 738/972] xilinx/util_adxcvr: Update enablement dependencies

---
 library/xilinx/util_adxcvr/util_adxcvr_ip.tcl | 144 ++++++------------
 1 file changed, 48 insertions(+), 96 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
index 06a4ff7ed..980f83842 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
+++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
@@ -131,24 +131,18 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*0* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \
   [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
+   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
   [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
   [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
@@ -173,10 +167,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*1* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \
   [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
@@ -201,10 +193,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*2* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \
   [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
@@ -229,10 +219,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*3* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \
   [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
@@ -257,24 +245,18 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*4* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \
   [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
+   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
   [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \
+   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
   [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
@@ -299,10 +281,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*5* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \
   [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
@@ -327,10 +307,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*6* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \
   [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
@@ -355,10 +333,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*7* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \
   [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
@@ -383,24 +359,18 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*8* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \
   [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
+   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
   [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
+   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
   [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
@@ -425,10 +395,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*9* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \
   [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
@@ -453,10 +421,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*10* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \
   [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
@@ -481,10 +447,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*11* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \
   [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
@@ -509,24 +473,18 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*12* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \
   [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
+   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
   [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \
+   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
   [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
@@ -551,10 +509,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*13* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \
   [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
@@ -579,10 +535,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*14* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \
   [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
@@ -607,10 +561,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
   [ipx::get_ports tx_*15* -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
-  {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
-  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15)) or \
-  ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
-  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15))} \
+  {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \
+   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \
   [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]

From c57ffc93645f35b3a85b4fa6228386d49c890a62 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 11:12:54 -0500
Subject: [PATCH 739/972] axi_adxcvr- separate pll reset from channels

---
 library/xilinx/axi_adxcvr/axi_adxcvr.v      | 36 ++-------------------
 library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl |  1 -
 library/xilinx/axi_adxcvr/axi_adxcvr_up.v   |  4 +--
 3 files changed, 4 insertions(+), 37 deletions(-)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v
index 8153141d0..8d4834469 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v
@@ -56,7 +56,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_0,
   input           up_es_ready_0,
 
-  output          up_ch_pll_rst_0,
   input           up_ch_pll_locked_0,
   output          up_ch_rst_0,
   output          up_ch_user_ready_0,
@@ -81,7 +80,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_1,
   input           up_es_ready_1,
 
-  output          up_ch_pll_rst_1,
   input           up_ch_pll_locked_1,
   output          up_ch_rst_1,
   output          up_ch_user_ready_1,
@@ -106,7 +104,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_2,
   input           up_es_ready_2,
 
-  output          up_ch_pll_rst_2,
   input           up_ch_pll_locked_2,
   output          up_ch_rst_2,
   output          up_ch_user_ready_2,
@@ -131,7 +128,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_3,
   input           up_es_ready_3,
 
-  output          up_ch_pll_rst_3,
   input           up_ch_pll_locked_3,
   output          up_ch_rst_3,
   output          up_ch_user_ready_3,
@@ -164,7 +160,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_4,
   input           up_es_ready_4,
 
-  output          up_ch_pll_rst_4,
   input           up_ch_pll_locked_4,
   output          up_ch_rst_4,
   output          up_ch_user_ready_4,
@@ -189,7 +184,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_5,
   input           up_es_ready_5,
 
-  output          up_ch_pll_rst_5,
   input           up_ch_pll_locked_5,
   output          up_ch_rst_5,
   output          up_ch_user_ready_5,
@@ -214,7 +208,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_6,
   input           up_es_ready_6,
 
-  output          up_ch_pll_rst_6,
   input           up_ch_pll_locked_6,
   output          up_ch_rst_6,
   output          up_ch_user_ready_6,
@@ -239,7 +232,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_7,
   input           up_es_ready_7,
 
-  output          up_ch_pll_rst_7,
   input           up_ch_pll_locked_7,
   output          up_ch_rst_7,
   output          up_ch_user_ready_7,
@@ -272,7 +264,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_8,
   input           up_es_ready_8,
 
-  output          up_ch_pll_rst_8,
   input           up_ch_pll_locked_8,
   output          up_ch_rst_8,
   output          up_ch_user_ready_8,
@@ -297,7 +288,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_9,
   input           up_es_ready_9,
 
-  output          up_ch_pll_rst_9,
   input           up_ch_pll_locked_9,
   output          up_ch_rst_9,
   output          up_ch_user_ready_9,
@@ -322,7 +312,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_10,
   input           up_es_ready_10,
 
-  output          up_ch_pll_rst_10,
   input           up_ch_pll_locked_10,
   output          up_ch_rst_10,
   output          up_ch_user_ready_10,
@@ -347,7 +336,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_11,
   input           up_es_ready_11,
 
-  output          up_ch_pll_rst_11,
   input           up_ch_pll_locked_11,
   output          up_ch_rst_11,
   output          up_ch_user_ready_11,
@@ -380,7 +368,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_12,
   input           up_es_ready_12,
 
-  output          up_ch_pll_rst_12,
   input           up_ch_pll_locked_12,
   output          up_ch_rst_12,
   output          up_ch_user_ready_12,
@@ -405,7 +392,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_13,
   input           up_es_ready_13,
 
-  output          up_ch_pll_rst_13,
   input           up_ch_pll_locked_13,
   output          up_ch_rst_13,
   output          up_ch_user_ready_13,
@@ -430,7 +416,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_14,
   input           up_es_ready_14,
 
-  output          up_ch_pll_rst_14,
   input           up_ch_pll_locked_14,
   output          up_ch_rst_14,
   output          up_ch_user_ready_14,
@@ -455,7 +440,6 @@ module axi_adxcvr (
   input   [15:0]  up_es_rdata_15,
   input           up_es_ready_15,
 
-  output          up_ch_pll_rst_15,
   input           up_ch_pll_locked_15,
   output          up_ch_rst_15,
   output          up_ch_user_ready_15,
@@ -475,6 +459,7 @@ module axi_adxcvr (
   input           axi_clk,
   input           axi_aresetn,
   output          up_status,
+  output          up_pll_rst,
 
   input           s_axi_awvalid,
   input   [31:0]  s_axi_awaddr,
@@ -576,7 +561,6 @@ module axi_adxcvr (
   wire            up_es_ready_14_s;
   wire    [15:0]  up_es_rdata_15_s;
   wire            up_es_ready_15_s;
-  wire            up_ch_pll_rst;
   wire            up_ch_rst;
   wire            up_ch_user_ready;
   wire            up_ch_lpm_dfe_n;
@@ -722,7 +706,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_0_s),
     .up_ready_out (up_es_ready_0_s));
 
-  assign up_ch_pll_rst_0 = up_ch_pll_rst;
   assign up_ch_rst_0 = up_ch_rst;
   assign up_ch_user_ready_0 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_0 = up_ch_lpm_dfe_n;
@@ -785,7 +768,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_1_s),
     .up_ready_out (up_es_ready_1_s));
 
-  assign up_ch_pll_rst_1 = up_ch_pll_rst;
   assign up_ch_rst_1 = up_ch_rst;
   assign up_ch_user_ready_1 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_1 = up_ch_lpm_dfe_n;
@@ -848,7 +830,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_2_s),
     .up_ready_out (up_es_ready_2_s));
 
-  assign up_ch_pll_rst_2 = up_ch_pll_rst;
   assign up_ch_rst_2 = up_ch_rst;
   assign up_ch_user_ready_2 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_2 = up_ch_lpm_dfe_n;
@@ -911,7 +892,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_3_s),
     .up_ready_out (up_es_ready_3_s));
 
-  assign up_ch_pll_rst_3 = up_ch_pll_rst;
   assign up_ch_rst_3 = up_ch_rst;
   assign up_ch_user_ready_3 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_3 = up_ch_lpm_dfe_n;
@@ -995,7 +975,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_4_s),
     .up_ready_out (up_es_ready_4_s));
 
-  assign up_ch_pll_rst_4 = up_ch_pll_rst;
   assign up_ch_rst_4 = up_ch_rst;
   assign up_ch_user_ready_4 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_4 = up_ch_lpm_dfe_n;
@@ -1058,7 +1037,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_5_s),
     .up_ready_out (up_es_ready_5_s));
 
-  assign up_ch_pll_rst_5 = up_ch_pll_rst;
   assign up_ch_rst_5 = up_ch_rst;
   assign up_ch_user_ready_5 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_5 = up_ch_lpm_dfe_n;
@@ -1121,7 +1099,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_6_s),
     .up_ready_out (up_es_ready_6_s));
 
-  assign up_ch_pll_rst_6 = up_ch_pll_rst;
   assign up_ch_rst_6 = up_ch_rst;
   assign up_ch_user_ready_6 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_6 = up_ch_lpm_dfe_n;
@@ -1184,7 +1161,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_7_s),
     .up_ready_out (up_es_ready_7_s));
 
-  assign up_ch_pll_rst_7 = up_ch_pll_rst;
   assign up_ch_rst_7 = up_ch_rst;
   assign up_ch_user_ready_7 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_7 = up_ch_lpm_dfe_n;
@@ -1268,7 +1244,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_8_s),
     .up_ready_out (up_es_ready_8_s));
 
-  assign up_ch_pll_rst_8 = up_ch_pll_rst;
   assign up_ch_rst_8 = up_ch_rst;
   assign up_ch_user_ready_8 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_8 = up_ch_lpm_dfe_n;
@@ -1331,7 +1306,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_9_s),
     .up_ready_out (up_es_ready_9_s));
 
-  assign up_ch_pll_rst_9 = up_ch_pll_rst;
   assign up_ch_rst_9 = up_ch_rst;
   assign up_ch_user_ready_9 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_9 = up_ch_lpm_dfe_n;
@@ -1394,7 +1368,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_10_s),
     .up_ready_out (up_es_ready_10_s));
 
-  assign up_ch_pll_rst_10 = up_ch_pll_rst;
   assign up_ch_rst_10 = up_ch_rst;
   assign up_ch_user_ready_10 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_10 = up_ch_lpm_dfe_n;
@@ -1457,7 +1430,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_11_s),
     .up_ready_out (up_es_ready_11_s));
 
-  assign up_ch_pll_rst_11 = up_ch_pll_rst;
   assign up_ch_rst_11 = up_ch_rst;
   assign up_ch_user_ready_11 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_11 = up_ch_lpm_dfe_n;
@@ -1541,7 +1513,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_12_s),
     .up_ready_out (up_es_ready_12_s));
 
-  assign up_ch_pll_rst_12 = up_ch_pll_rst;
   assign up_ch_rst_12 = up_ch_rst;
   assign up_ch_user_ready_12 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_12 = up_ch_lpm_dfe_n;
@@ -1604,7 +1575,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_13_s),
     .up_ready_out (up_es_ready_13_s));
 
-  assign up_ch_pll_rst_13 = up_ch_pll_rst;
   assign up_ch_rst_13 = up_ch_rst;
   assign up_ch_user_ready_13 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_13 = up_ch_lpm_dfe_n;
@@ -1667,7 +1637,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_14_s),
     .up_ready_out (up_es_ready_14_s));
 
-  assign up_ch_pll_rst_14 = up_ch_pll_rst;
   assign up_ch_rst_14 = up_ch_rst;
   assign up_ch_user_ready_14 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_14 = up_ch_lpm_dfe_n;
@@ -1730,7 +1699,6 @@ module axi_adxcvr (
     .up_rdata_out (up_es_rdata_15_s),
     .up_ready_out (up_es_ready_15_s));
 
-  assign up_ch_pll_rst_15 = up_ch_pll_rst;
   assign up_ch_rst_15 = up_ch_rst;
   assign up_ch_user_ready_15 = up_ch_user_ready;
   assign up_ch_lpm_dfe_n_15 = up_ch_lpm_dfe_n;
@@ -1829,7 +1797,6 @@ module axi_adxcvr (
     .up_cm_wdata (up_cm_wdata),
     .up_cm_rdata (up_cm_rdata_12_s),
     .up_cm_ready (up_cm_ready_12_s),
-    .up_ch_pll_rst (up_ch_pll_rst),
     .up_ch_pll_locked (up_ch_pll_locked_15_s),
     .up_ch_rst (up_ch_rst),
     .up_ch_user_ready (up_ch_user_ready),
@@ -1859,6 +1826,7 @@ module axi_adxcvr (
     .up_es_saddr (up_es_saddr),
     .up_es_status (up_es_status),
     .up_status (up_status),
+    .up_pll_rst (up_pll_rst),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq),
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
index 7d73ae17b..f7c36b090 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -100,7 +100,6 @@ for {set n 0} {$n < 16} {incr n} {
     "ready               up_es_ready_${n}       "]
 
   adi_if_infer_bus ADI:user:if_xcvr_ch master up_ch_${n} [list \
-    "pll_rst             up_ch_pll_rst_${n}     "\
     "pll_locked          up_ch_pll_locked_${n}  "\
     "rst                 up_ch_rst_${n}         "\
     "user_ready          up_ch_user_ready_${n}  "\
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
index 88f050115..80acfb12b 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
@@ -51,7 +51,6 @@ module axi_adxcvr_up (
 
   // channel
 
-  output          up_ch_pll_rst,
   input           up_ch_pll_locked,
   output          up_ch_rst,
   output          up_ch_user_ready,
@@ -87,6 +86,7 @@ module axi_adxcvr_up (
   // status
 
   output          up_status,
+  output          up_pll_rst,
 
   // bus interface
 
@@ -176,7 +176,7 @@ module axi_adxcvr_up (
     end
   end
 
-  assign up_ch_pll_rst = up_pll_rst_cnt[3];
+  assign up_pll_rst = up_pll_rst_cnt[3];
   assign up_ch_rst = up_rst_cnt[3];
   assign up_ch_user_ready = up_user_ready_cnt[6];
   assign up_status = up_status_int;

From 3cbe735bd8a0bd5123178900a7c6517633c2fba5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 11:21:04 -0500
Subject: [PATCH 740/972] util_adxcvr: regenerate from script

---
 library/xilinx/util_adxcvr/util_adxcvr_ip.tcl | 50 +++++++++----------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
index 980f83842..93e75ba99 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
+++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
@@ -132,12 +132,12 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \
   [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
-   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
   [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
@@ -168,7 +168,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \
   [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
@@ -194,7 +194,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \
   [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
@@ -220,7 +220,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \
   [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
@@ -246,17 +246,17 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \
   [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
-   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
   [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \
-   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
   [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
@@ -282,7 +282,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \
   [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
@@ -308,7 +308,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \
   [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
@@ -334,7 +334,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \
   [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
@@ -360,17 +360,17 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \
   [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
-   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
   [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
-   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
   [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
@@ -396,7 +396,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \
   [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
@@ -422,7 +422,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \
   [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
@@ -448,7 +448,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \
   [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
@@ -474,17 +474,17 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \
   [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
-   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
   [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency \
-  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \
-   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
+  {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
+  (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
   [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
@@ -510,7 +510,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \
   [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
@@ -536,7 +536,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \
   [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]]
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
@@ -562,7 +562,7 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \
-   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \
+  (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \
   [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]

From 3dbed492b3cf99b8a07ce11dd4d84a39cf44dfe5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 11:32:37 -0500
Subject: [PATCH 741/972] util_adxcvr: expose cpll/qpll as it is

---
 library/xilinx/util_adxcvr/util_adxcvr.v      | 128 +++++-------------
 library/xilinx/util_adxcvr/util_adxcvr_ip.tcl |   2 -
 library/xilinx/util_adxcvr/util_adxcvr_xch.v  |   6 +-
 3 files changed, 37 insertions(+), 99 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v
index fffe54b67..043cde0a5 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr.v
@@ -55,7 +55,6 @@ module util_adxcvr #(
 
   parameter   integer CPLL_FBDIV = 2,
   parameter   integer CPLL_FBDIV_4_5 = 5,
-  parameter   integer CPLL_TX_OR_RX_N = 0,
 
   // tx-configuration
 
@@ -76,7 +75,9 @@ module util_adxcvr #(
   input           up_clk,
 
   input           qpll_ref_clk_0,
+  input           up_qpll_rst_0,
   input           cpll_ref_clk_0,
+  input           up_cpll_rst_0,
 
   input           rx_0_p,
   input           rx_0_n,
@@ -109,7 +110,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_0,
   output  [15:0]  up_es_rdata_0,
   output          up_es_ready_0,
-  input           up_rx_pll_rst_0,
   output          up_rx_pll_locked_0,
   input           up_rx_rst_0,
   input           up_rx_user_ready_0,
@@ -125,7 +125,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_0,
   output  [15:0]  up_rx_rdata_0,
   output          up_rx_ready_0,
-  input           up_tx_pll_rst_0,
   output          up_tx_pll_locked_0,
   input           up_tx_rst_0,
   input           up_tx_user_ready_0,
@@ -143,6 +142,7 @@ module util_adxcvr #(
   output          up_tx_ready_0,
 
   input           cpll_ref_clk_1,
+  input           up_cpll_rst_1,
 
   input           rx_1_p,
   input           rx_1_n,
@@ -168,7 +168,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_1,
   output  [15:0]  up_es_rdata_1,
   output          up_es_ready_1,
-  input           up_rx_pll_rst_1,
   output          up_rx_pll_locked_1,
   input           up_rx_rst_1,
   input           up_rx_user_ready_1,
@@ -184,7 +183,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_1,
   output  [15:0]  up_rx_rdata_1,
   output          up_rx_ready_1,
-  input           up_tx_pll_rst_1,
   output          up_tx_pll_locked_1,
   input           up_tx_rst_1,
   input           up_tx_user_ready_1,
@@ -202,6 +200,7 @@ module util_adxcvr #(
   output          up_tx_ready_1,
 
   input           cpll_ref_clk_2,
+  input           up_cpll_rst_2,
 
   input           rx_2_p,
   input           rx_2_n,
@@ -227,7 +226,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_2,
   output  [15:0]  up_es_rdata_2,
   output          up_es_ready_2,
-  input           up_rx_pll_rst_2,
   output          up_rx_pll_locked_2,
   input           up_rx_rst_2,
   input           up_rx_user_ready_2,
@@ -243,7 +241,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_2,
   output  [15:0]  up_rx_rdata_2,
   output          up_rx_ready_2,
-  input           up_tx_pll_rst_2,
   output          up_tx_pll_locked_2,
   input           up_tx_rst_2,
   input           up_tx_user_ready_2,
@@ -261,6 +258,7 @@ module util_adxcvr #(
   output          up_tx_ready_2,
 
   input           cpll_ref_clk_3,
+  input           up_cpll_rst_3,
 
   input           rx_3_p,
   input           rx_3_n,
@@ -286,7 +284,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_3,
   output  [15:0]  up_es_rdata_3,
   output          up_es_ready_3,
-  input           up_rx_pll_rst_3,
   output          up_rx_pll_locked_3,
   input           up_rx_rst_3,
   input           up_rx_user_ready_3,
@@ -302,7 +299,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_3,
   output  [15:0]  up_rx_rdata_3,
   output          up_rx_ready_3,
-  input           up_tx_pll_rst_3,
   output          up_tx_pll_locked_3,
   input           up_tx_rst_3,
   input           up_tx_user_ready_3,
@@ -320,7 +316,9 @@ module util_adxcvr #(
   output          up_tx_ready_3,
 
   input           qpll_ref_clk_4,
+  input           up_qpll_rst_4,
   input           cpll_ref_clk_4,
+  input           up_cpll_rst_4,
 
   input           rx_4_p,
   input           rx_4_n,
@@ -353,7 +351,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_4,
   output  [15:0]  up_es_rdata_4,
   output          up_es_ready_4,
-  input           up_rx_pll_rst_4,
   output          up_rx_pll_locked_4,
   input           up_rx_rst_4,
   input           up_rx_user_ready_4,
@@ -369,7 +366,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_4,
   output  [15:0]  up_rx_rdata_4,
   output          up_rx_ready_4,
-  input           up_tx_pll_rst_4,
   output          up_tx_pll_locked_4,
   input           up_tx_rst_4,
   input           up_tx_user_ready_4,
@@ -387,6 +383,7 @@ module util_adxcvr #(
   output          up_tx_ready_4,
 
   input           cpll_ref_clk_5,
+  input           up_cpll_rst_5,
 
   input           rx_5_p,
   input           rx_5_n,
@@ -412,7 +409,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_5,
   output  [15:0]  up_es_rdata_5,
   output          up_es_ready_5,
-  input           up_rx_pll_rst_5,
   output          up_rx_pll_locked_5,
   input           up_rx_rst_5,
   input           up_rx_user_ready_5,
@@ -428,7 +424,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_5,
   output  [15:0]  up_rx_rdata_5,
   output          up_rx_ready_5,
-  input           up_tx_pll_rst_5,
   output          up_tx_pll_locked_5,
   input           up_tx_rst_5,
   input           up_tx_user_ready_5,
@@ -446,6 +441,7 @@ module util_adxcvr #(
   output          up_tx_ready_5,
 
   input           cpll_ref_clk_6,
+  input           up_cpll_rst_6,
 
   input           rx_6_p,
   input           rx_6_n,
@@ -471,7 +467,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_6,
   output  [15:0]  up_es_rdata_6,
   output          up_es_ready_6,
-  input           up_rx_pll_rst_6,
   output          up_rx_pll_locked_6,
   input           up_rx_rst_6,
   input           up_rx_user_ready_6,
@@ -487,7 +482,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_6,
   output  [15:0]  up_rx_rdata_6,
   output          up_rx_ready_6,
-  input           up_tx_pll_rst_6,
   output          up_tx_pll_locked_6,
   input           up_tx_rst_6,
   input           up_tx_user_ready_6,
@@ -505,6 +499,7 @@ module util_adxcvr #(
   output          up_tx_ready_6,
 
   input           cpll_ref_clk_7,
+  input           up_cpll_rst_7,
 
   input           rx_7_p,
   input           rx_7_n,
@@ -530,7 +525,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_7,
   output  [15:0]  up_es_rdata_7,
   output          up_es_ready_7,
-  input           up_rx_pll_rst_7,
   output          up_rx_pll_locked_7,
   input           up_rx_rst_7,
   input           up_rx_user_ready_7,
@@ -546,7 +540,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_7,
   output  [15:0]  up_rx_rdata_7,
   output          up_rx_ready_7,
-  input           up_tx_pll_rst_7,
   output          up_tx_pll_locked_7,
   input           up_tx_rst_7,
   input           up_tx_user_ready_7,
@@ -564,7 +557,9 @@ module util_adxcvr #(
   output          up_tx_ready_7,
 
   input           qpll_ref_clk_8,
+  input           up_qpll_rst_8,
   input           cpll_ref_clk_8,
+  input           up_cpll_rst_8,
 
   input           rx_8_p,
   input           rx_8_n,
@@ -597,7 +592,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_8,
   output  [15:0]  up_es_rdata_8,
   output          up_es_ready_8,
-  input           up_rx_pll_rst_8,
   output          up_rx_pll_locked_8,
   input           up_rx_rst_8,
   input           up_rx_user_ready_8,
@@ -613,7 +607,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_8,
   output  [15:0]  up_rx_rdata_8,
   output          up_rx_ready_8,
-  input           up_tx_pll_rst_8,
   output          up_tx_pll_locked_8,
   input           up_tx_rst_8,
   input           up_tx_user_ready_8,
@@ -631,6 +624,7 @@ module util_adxcvr #(
   output          up_tx_ready_8,
 
   input           cpll_ref_clk_9,
+  input           up_cpll_rst_9,
 
   input           rx_9_p,
   input           rx_9_n,
@@ -656,7 +650,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_9,
   output  [15:0]  up_es_rdata_9,
   output          up_es_ready_9,
-  input           up_rx_pll_rst_9,
   output          up_rx_pll_locked_9,
   input           up_rx_rst_9,
   input           up_rx_user_ready_9,
@@ -672,7 +665,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_9,
   output  [15:0]  up_rx_rdata_9,
   output          up_rx_ready_9,
-  input           up_tx_pll_rst_9,
   output          up_tx_pll_locked_9,
   input           up_tx_rst_9,
   input           up_tx_user_ready_9,
@@ -690,6 +682,7 @@ module util_adxcvr #(
   output          up_tx_ready_9,
 
   input           cpll_ref_clk_10,
+  input           up_cpll_rst_10,
 
   input           rx_10_p,
   input           rx_10_n,
@@ -715,7 +708,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_10,
   output  [15:0]  up_es_rdata_10,
   output          up_es_ready_10,
-  input           up_rx_pll_rst_10,
   output          up_rx_pll_locked_10,
   input           up_rx_rst_10,
   input           up_rx_user_ready_10,
@@ -731,7 +723,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_10,
   output  [15:0]  up_rx_rdata_10,
   output          up_rx_ready_10,
-  input           up_tx_pll_rst_10,
   output          up_tx_pll_locked_10,
   input           up_tx_rst_10,
   input           up_tx_user_ready_10,
@@ -749,6 +740,7 @@ module util_adxcvr #(
   output          up_tx_ready_10,
 
   input           cpll_ref_clk_11,
+  input           up_cpll_rst_11,
 
   input           rx_11_p,
   input           rx_11_n,
@@ -774,7 +766,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_11,
   output  [15:0]  up_es_rdata_11,
   output          up_es_ready_11,
-  input           up_rx_pll_rst_11,
   output          up_rx_pll_locked_11,
   input           up_rx_rst_11,
   input           up_rx_user_ready_11,
@@ -790,7 +781,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_11,
   output  [15:0]  up_rx_rdata_11,
   output          up_rx_ready_11,
-  input           up_tx_pll_rst_11,
   output          up_tx_pll_locked_11,
   input           up_tx_rst_11,
   input           up_tx_user_ready_11,
@@ -808,7 +798,9 @@ module util_adxcvr #(
   output          up_tx_ready_11,
 
   input           qpll_ref_clk_12,
+  input           up_qpll_rst_12,
   input           cpll_ref_clk_12,
+  input           up_cpll_rst_12,
 
   input           rx_12_p,
   input           rx_12_n,
@@ -841,7 +833,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_12,
   output  [15:0]  up_es_rdata_12,
   output          up_es_ready_12,
-  input           up_rx_pll_rst_12,
   output          up_rx_pll_locked_12,
   input           up_rx_rst_12,
   input           up_rx_user_ready_12,
@@ -857,7 +848,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_12,
   output  [15:0]  up_rx_rdata_12,
   output          up_rx_ready_12,
-  input           up_tx_pll_rst_12,
   output          up_tx_pll_locked_12,
   input           up_tx_rst_12,
   input           up_tx_user_ready_12,
@@ -875,6 +865,7 @@ module util_adxcvr #(
   output          up_tx_ready_12,
 
   input           cpll_ref_clk_13,
+  input           up_cpll_rst_13,
 
   input           rx_13_p,
   input           rx_13_n,
@@ -900,7 +891,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_13,
   output  [15:0]  up_es_rdata_13,
   output          up_es_ready_13,
-  input           up_rx_pll_rst_13,
   output          up_rx_pll_locked_13,
   input           up_rx_rst_13,
   input           up_rx_user_ready_13,
@@ -916,7 +906,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_13,
   output  [15:0]  up_rx_rdata_13,
   output          up_rx_ready_13,
-  input           up_tx_pll_rst_13,
   output          up_tx_pll_locked_13,
   input           up_tx_rst_13,
   input           up_tx_user_ready_13,
@@ -934,6 +923,7 @@ module util_adxcvr #(
   output          up_tx_ready_13,
 
   input           cpll_ref_clk_14,
+  input           up_cpll_rst_14,
 
   input           rx_14_p,
   input           rx_14_n,
@@ -959,7 +949,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_14,
   output  [15:0]  up_es_rdata_14,
   output          up_es_ready_14,
-  input           up_rx_pll_rst_14,
   output          up_rx_pll_locked_14,
   input           up_rx_rst_14,
   input           up_rx_user_ready_14,
@@ -975,7 +964,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_14,
   output  [15:0]  up_rx_rdata_14,
   output          up_rx_ready_14,
-  input           up_tx_pll_rst_14,
   output          up_tx_pll_locked_14,
   input           up_tx_rst_14,
   input           up_tx_user_ready_14,
@@ -993,6 +981,7 @@ module util_adxcvr #(
   output          up_tx_ready_14,
 
   input           cpll_ref_clk_15,
+  input           up_cpll_rst_15,
 
   input           rx_15_p,
   input           rx_15_n,
@@ -1018,7 +1007,6 @@ module util_adxcvr #(
   input   [15:0]  up_es_wdata_15,
   output  [15:0]  up_es_rdata_15,
   output          up_es_ready_15,
-  input           up_rx_pll_rst_15,
   output          up_rx_pll_locked_15,
   input           up_rx_rst_15,
   input           up_rx_user_ready_15,
@@ -1034,7 +1022,6 @@ module util_adxcvr #(
   input   [15:0]  up_rx_wdata_15,
   output  [15:0]  up_rx_rdata_15,
   output          up_rx_ready_15,
-  input           up_tx_pll_rst_15,
   output          up_tx_pll_locked_15,
   input           up_tx_rst_15,
   input           up_tx_user_ready_15,
@@ -1061,26 +1048,15 @@ module util_adxcvr #(
   wire            qpll2ch_clk_0;
   wire            qpll2ch_ref_clk_0;
   wire            qpll2ch_locked_0;
-  wire            up_qpll_rst_0;
   wire            qpll2ch_clk_4;
   wire            qpll2ch_ref_clk_4;
   wire            qpll2ch_locked_4;
-  wire            up_qpll_rst_4;
   wire            qpll2ch_clk_8;
   wire            qpll2ch_ref_clk_8;
   wire            qpll2ch_locked_8;
-  wire            up_qpll_rst_8;
   wire            qpll2ch_clk_12;
   wire            qpll2ch_ref_clk_12;
   wire            qpll2ch_locked_12;
-  wire            up_qpll_rst_12;
-
-  // quad controls
-
-  assign up_qpll_rst_0 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_0 : up_rx_pll_rst_0;
-  assign up_qpll_rst_4 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_4 : up_rx_pll_rst_4;
-  assign up_qpll_rst_8 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_8 : up_rx_pll_rst_8;
-  assign up_qpll_rst_12 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_12 : up_rx_pll_rst_12;
 
   // instantiations
 
@@ -1124,7 +1100,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1137,6 +1112,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
     .qpll2ch_locked (qpll2ch_locked_0),
     .cpll_ref_clk (cpll_ref_clk_0),
+    .up_cpll_rst (up_cpll_rst_0),
     .rx_p (rx_0_p),
     .rx_n (rx_0_n),
     .rx_out_clk (rx_out_clk_0),
@@ -1161,7 +1137,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_0),
     .up_es_rdata (up_es_rdata_0),
     .up_es_ready (up_es_ready_0),
-    .up_rx_pll_rst (up_rx_pll_rst_0),
     .up_rx_pll_locked (up_rx_pll_locked_0),
     .up_rx_rst (up_rx_rst_0),
     .up_rx_user_ready (up_rx_user_ready_0),
@@ -1177,7 +1152,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_0),
     .up_rx_rdata (up_rx_rdata_0),
     .up_rx_ready (up_rx_ready_0),
-    .up_tx_pll_rst (up_tx_pll_rst_0),
     .up_tx_pll_locked (up_tx_pll_locked_0),
     .up_tx_rst (up_tx_rst_0),
     .up_tx_user_ready (up_tx_user_ready_0),
@@ -1223,7 +1197,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1236,6 +1209,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
     .qpll2ch_locked (qpll2ch_locked_0),
     .cpll_ref_clk (cpll_ref_clk_1),
+    .up_cpll_rst (up_cpll_rst_1),
     .rx_p (rx_1_p),
     .rx_n (rx_1_n),
     .rx_out_clk (rx_out_clk_1),
@@ -1260,7 +1234,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_1),
     .up_es_rdata (up_es_rdata_1),
     .up_es_ready (up_es_ready_1),
-    .up_rx_pll_rst (up_rx_pll_rst_1),
     .up_rx_pll_locked (up_rx_pll_locked_1),
     .up_rx_rst (up_rx_rst_1),
     .up_rx_user_ready (up_rx_user_ready_1),
@@ -1276,7 +1249,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_1),
     .up_rx_rdata (up_rx_rdata_1),
     .up_rx_ready (up_rx_ready_1),
-    .up_tx_pll_rst (up_tx_pll_rst_1),
     .up_tx_pll_locked (up_tx_pll_locked_1),
     .up_tx_rst (up_tx_rst_1),
     .up_tx_user_ready (up_tx_user_ready_1),
@@ -1322,7 +1294,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1335,6 +1306,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
     .qpll2ch_locked (qpll2ch_locked_0),
     .cpll_ref_clk (cpll_ref_clk_2),
+    .up_cpll_rst (up_cpll_rst_2),
     .rx_p (rx_2_p),
     .rx_n (rx_2_n),
     .rx_out_clk (rx_out_clk_2),
@@ -1359,7 +1331,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_2),
     .up_es_rdata (up_es_rdata_2),
     .up_es_ready (up_es_ready_2),
-    .up_rx_pll_rst (up_rx_pll_rst_2),
     .up_rx_pll_locked (up_rx_pll_locked_2),
     .up_rx_rst (up_rx_rst_2),
     .up_rx_user_ready (up_rx_user_ready_2),
@@ -1375,7 +1346,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_2),
     .up_rx_rdata (up_rx_rdata_2),
     .up_rx_ready (up_rx_ready_2),
-    .up_tx_pll_rst (up_tx_pll_rst_2),
     .up_tx_pll_locked (up_tx_pll_locked_2),
     .up_tx_rst (up_tx_rst_2),
     .up_tx_user_ready (up_tx_user_ready_2),
@@ -1421,7 +1391,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1434,6 +1403,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
     .qpll2ch_locked (qpll2ch_locked_0),
     .cpll_ref_clk (cpll_ref_clk_3),
+    .up_cpll_rst (up_cpll_rst_3),
     .rx_p (rx_3_p),
     .rx_n (rx_3_n),
     .rx_out_clk (rx_out_clk_3),
@@ -1458,7 +1428,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_3),
     .up_es_rdata (up_es_rdata_3),
     .up_es_ready (up_es_ready_3),
-    .up_rx_pll_rst (up_rx_pll_rst_3),
     .up_rx_pll_locked (up_rx_pll_locked_3),
     .up_rx_rst (up_rx_rst_3),
     .up_rx_user_ready (up_rx_user_ready_3),
@@ -1474,7 +1443,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_3),
     .up_rx_rdata (up_rx_rdata_3),
     .up_rx_ready (up_rx_ready_3),
-    .up_tx_pll_rst (up_tx_pll_rst_3),
     .up_tx_pll_locked (up_tx_pll_locked_3),
     .up_tx_rst (up_tx_rst_3),
     .up_tx_user_ready (up_tx_user_ready_3),
@@ -1552,7 +1520,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1565,6 +1532,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
     .qpll2ch_locked (qpll2ch_locked_4),
     .cpll_ref_clk (cpll_ref_clk_4),
+    .up_cpll_rst (up_cpll_rst_4),
     .rx_p (rx_4_p),
     .rx_n (rx_4_n),
     .rx_out_clk (rx_out_clk_4),
@@ -1589,7 +1557,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_4),
     .up_es_rdata (up_es_rdata_4),
     .up_es_ready (up_es_ready_4),
-    .up_rx_pll_rst (up_rx_pll_rst_4),
     .up_rx_pll_locked (up_rx_pll_locked_4),
     .up_rx_rst (up_rx_rst_4),
     .up_rx_user_ready (up_rx_user_ready_4),
@@ -1605,7 +1572,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_4),
     .up_rx_rdata (up_rx_rdata_4),
     .up_rx_ready (up_rx_ready_4),
-    .up_tx_pll_rst (up_tx_pll_rst_4),
     .up_tx_pll_locked (up_tx_pll_locked_4),
     .up_tx_rst (up_tx_rst_4),
     .up_tx_user_ready (up_tx_user_ready_4),
@@ -1651,7 +1617,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1664,6 +1629,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
     .qpll2ch_locked (qpll2ch_locked_4),
     .cpll_ref_clk (cpll_ref_clk_5),
+    .up_cpll_rst (up_cpll_rst_5),
     .rx_p (rx_5_p),
     .rx_n (rx_5_n),
     .rx_out_clk (rx_out_clk_5),
@@ -1688,7 +1654,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_5),
     .up_es_rdata (up_es_rdata_5),
     .up_es_ready (up_es_ready_5),
-    .up_rx_pll_rst (up_rx_pll_rst_5),
     .up_rx_pll_locked (up_rx_pll_locked_5),
     .up_rx_rst (up_rx_rst_5),
     .up_rx_user_ready (up_rx_user_ready_5),
@@ -1704,7 +1669,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_5),
     .up_rx_rdata (up_rx_rdata_5),
     .up_rx_ready (up_rx_ready_5),
-    .up_tx_pll_rst (up_tx_pll_rst_5),
     .up_tx_pll_locked (up_tx_pll_locked_5),
     .up_tx_rst (up_tx_rst_5),
     .up_tx_user_ready (up_tx_user_ready_5),
@@ -1750,7 +1714,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1763,6 +1726,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
     .qpll2ch_locked (qpll2ch_locked_4),
     .cpll_ref_clk (cpll_ref_clk_6),
+    .up_cpll_rst (up_cpll_rst_6),
     .rx_p (rx_6_p),
     .rx_n (rx_6_n),
     .rx_out_clk (rx_out_clk_6),
@@ -1787,7 +1751,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_6),
     .up_es_rdata (up_es_rdata_6),
     .up_es_ready (up_es_ready_6),
-    .up_rx_pll_rst (up_rx_pll_rst_6),
     .up_rx_pll_locked (up_rx_pll_locked_6),
     .up_rx_rst (up_rx_rst_6),
     .up_rx_user_ready (up_rx_user_ready_6),
@@ -1803,7 +1766,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_6),
     .up_rx_rdata (up_rx_rdata_6),
     .up_rx_ready (up_rx_ready_6),
-    .up_tx_pll_rst (up_tx_pll_rst_6),
     .up_tx_pll_locked (up_tx_pll_locked_6),
     .up_tx_rst (up_tx_rst_6),
     .up_tx_user_ready (up_tx_user_ready_6),
@@ -1849,7 +1811,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1862,6 +1823,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
     .qpll2ch_locked (qpll2ch_locked_4),
     .cpll_ref_clk (cpll_ref_clk_7),
+    .up_cpll_rst (up_cpll_rst_7),
     .rx_p (rx_7_p),
     .rx_n (rx_7_n),
     .rx_out_clk (rx_out_clk_7),
@@ -1886,7 +1848,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_7),
     .up_es_rdata (up_es_rdata_7),
     .up_es_ready (up_es_ready_7),
-    .up_rx_pll_rst (up_rx_pll_rst_7),
     .up_rx_pll_locked (up_rx_pll_locked_7),
     .up_rx_rst (up_rx_rst_7),
     .up_rx_user_ready (up_rx_user_ready_7),
@@ -1902,7 +1863,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_7),
     .up_rx_rdata (up_rx_rdata_7),
     .up_rx_ready (up_rx_ready_7),
-    .up_tx_pll_rst (up_tx_pll_rst_7),
     .up_tx_pll_locked (up_tx_pll_locked_7),
     .up_tx_rst (up_tx_rst_7),
     .up_tx_user_ready (up_tx_user_ready_7),
@@ -1980,7 +1940,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -1993,6 +1952,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
     .qpll2ch_locked (qpll2ch_locked_8),
     .cpll_ref_clk (cpll_ref_clk_8),
+    .up_cpll_rst (up_cpll_rst_8),
     .rx_p (rx_8_p),
     .rx_n (rx_8_n),
     .rx_out_clk (rx_out_clk_8),
@@ -2017,7 +1977,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_8),
     .up_es_rdata (up_es_rdata_8),
     .up_es_ready (up_es_ready_8),
-    .up_rx_pll_rst (up_rx_pll_rst_8),
     .up_rx_pll_locked (up_rx_pll_locked_8),
     .up_rx_rst (up_rx_rst_8),
     .up_rx_user_ready (up_rx_user_ready_8),
@@ -2033,7 +1992,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_8),
     .up_rx_rdata (up_rx_rdata_8),
     .up_rx_ready (up_rx_ready_8),
-    .up_tx_pll_rst (up_tx_pll_rst_8),
     .up_tx_pll_locked (up_tx_pll_locked_8),
     .up_tx_rst (up_tx_rst_8),
     .up_tx_user_ready (up_tx_user_ready_8),
@@ -2079,7 +2037,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2092,6 +2049,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
     .qpll2ch_locked (qpll2ch_locked_8),
     .cpll_ref_clk (cpll_ref_clk_9),
+    .up_cpll_rst (up_cpll_rst_9),
     .rx_p (rx_9_p),
     .rx_n (rx_9_n),
     .rx_out_clk (rx_out_clk_9),
@@ -2116,7 +2074,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_9),
     .up_es_rdata (up_es_rdata_9),
     .up_es_ready (up_es_ready_9),
-    .up_rx_pll_rst (up_rx_pll_rst_9),
     .up_rx_pll_locked (up_rx_pll_locked_9),
     .up_rx_rst (up_rx_rst_9),
     .up_rx_user_ready (up_rx_user_ready_9),
@@ -2132,7 +2089,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_9),
     .up_rx_rdata (up_rx_rdata_9),
     .up_rx_ready (up_rx_ready_9),
-    .up_tx_pll_rst (up_tx_pll_rst_9),
     .up_tx_pll_locked (up_tx_pll_locked_9),
     .up_tx_rst (up_tx_rst_9),
     .up_tx_user_ready (up_tx_user_ready_9),
@@ -2178,7 +2134,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2191,6 +2146,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
     .qpll2ch_locked (qpll2ch_locked_8),
     .cpll_ref_clk (cpll_ref_clk_10),
+    .up_cpll_rst (up_cpll_rst_10),
     .rx_p (rx_10_p),
     .rx_n (rx_10_n),
     .rx_out_clk (rx_out_clk_10),
@@ -2215,7 +2171,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_10),
     .up_es_rdata (up_es_rdata_10),
     .up_es_ready (up_es_ready_10),
-    .up_rx_pll_rst (up_rx_pll_rst_10),
     .up_rx_pll_locked (up_rx_pll_locked_10),
     .up_rx_rst (up_rx_rst_10),
     .up_rx_user_ready (up_rx_user_ready_10),
@@ -2231,7 +2186,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_10),
     .up_rx_rdata (up_rx_rdata_10),
     .up_rx_ready (up_rx_ready_10),
-    .up_tx_pll_rst (up_tx_pll_rst_10),
     .up_tx_pll_locked (up_tx_pll_locked_10),
     .up_tx_rst (up_tx_rst_10),
     .up_tx_user_ready (up_tx_user_ready_10),
@@ -2277,7 +2231,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2290,6 +2243,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
     .qpll2ch_locked (qpll2ch_locked_8),
     .cpll_ref_clk (cpll_ref_clk_11),
+    .up_cpll_rst (up_cpll_rst_11),
     .rx_p (rx_11_p),
     .rx_n (rx_11_n),
     .rx_out_clk (rx_out_clk_11),
@@ -2314,7 +2268,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_11),
     .up_es_rdata (up_es_rdata_11),
     .up_es_ready (up_es_ready_11),
-    .up_rx_pll_rst (up_rx_pll_rst_11),
     .up_rx_pll_locked (up_rx_pll_locked_11),
     .up_rx_rst (up_rx_rst_11),
     .up_rx_user_ready (up_rx_user_ready_11),
@@ -2330,7 +2283,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_11),
     .up_rx_rdata (up_rx_rdata_11),
     .up_rx_ready (up_rx_ready_11),
-    .up_tx_pll_rst (up_tx_pll_rst_11),
     .up_tx_pll_locked (up_tx_pll_locked_11),
     .up_tx_rst (up_tx_rst_11),
     .up_tx_user_ready (up_tx_user_ready_11),
@@ -2408,7 +2360,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2421,6 +2372,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
     .qpll2ch_locked (qpll2ch_locked_12),
     .cpll_ref_clk (cpll_ref_clk_12),
+    .up_cpll_rst (up_cpll_rst_12),
     .rx_p (rx_12_p),
     .rx_n (rx_12_n),
     .rx_out_clk (rx_out_clk_12),
@@ -2445,7 +2397,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_12),
     .up_es_rdata (up_es_rdata_12),
     .up_es_ready (up_es_ready_12),
-    .up_rx_pll_rst (up_rx_pll_rst_12),
     .up_rx_pll_locked (up_rx_pll_locked_12),
     .up_rx_rst (up_rx_rst_12),
     .up_rx_user_ready (up_rx_user_ready_12),
@@ -2461,7 +2412,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_12),
     .up_rx_rdata (up_rx_rdata_12),
     .up_rx_ready (up_rx_ready_12),
-    .up_tx_pll_rst (up_tx_pll_rst_12),
     .up_tx_pll_locked (up_tx_pll_locked_12),
     .up_tx_rst (up_tx_rst_12),
     .up_tx_user_ready (up_tx_user_ready_12),
@@ -2507,7 +2457,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2520,6 +2469,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
     .qpll2ch_locked (qpll2ch_locked_12),
     .cpll_ref_clk (cpll_ref_clk_13),
+    .up_cpll_rst (up_cpll_rst_13),
     .rx_p (rx_13_p),
     .rx_n (rx_13_n),
     .rx_out_clk (rx_out_clk_13),
@@ -2544,7 +2494,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_13),
     .up_es_rdata (up_es_rdata_13),
     .up_es_ready (up_es_ready_13),
-    .up_rx_pll_rst (up_rx_pll_rst_13),
     .up_rx_pll_locked (up_rx_pll_locked_13),
     .up_rx_rst (up_rx_rst_13),
     .up_rx_user_ready (up_rx_user_ready_13),
@@ -2560,7 +2509,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_13),
     .up_rx_rdata (up_rx_rdata_13),
     .up_rx_ready (up_rx_ready_13),
-    .up_tx_pll_rst (up_tx_pll_rst_13),
     .up_tx_pll_locked (up_tx_pll_locked_13),
     .up_tx_rst (up_tx_rst_13),
     .up_tx_user_ready (up_tx_user_ready_13),
@@ -2606,7 +2554,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2619,6 +2566,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
     .qpll2ch_locked (qpll2ch_locked_12),
     .cpll_ref_clk (cpll_ref_clk_14),
+    .up_cpll_rst (up_cpll_rst_14),
     .rx_p (rx_14_p),
     .rx_n (rx_14_n),
     .rx_out_clk (rx_out_clk_14),
@@ -2643,7 +2591,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_14),
     .up_es_rdata (up_es_rdata_14),
     .up_es_ready (up_es_ready_14),
-    .up_rx_pll_rst (up_rx_pll_rst_14),
     .up_rx_pll_locked (up_rx_pll_locked_14),
     .up_rx_rst (up_rx_rst_14),
     .up_rx_user_ready (up_rx_user_ready_14),
@@ -2659,7 +2606,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_14),
     .up_rx_rdata (up_rx_rdata_14),
     .up_rx_ready (up_rx_ready_14),
-    .up_tx_pll_rst (up_tx_pll_rst_14),
     .up_tx_pll_locked (up_tx_pll_locked_14),
     .up_tx_rst (up_tx_rst_14),
     .up_tx_user_ready (up_tx_user_ready_14),
@@ -2705,7 +2651,6 @@ module util_adxcvr #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV (CPLL_FBDIV),
     .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
-    .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
     .TX_OUT_DIV (TX_OUT_DIV),
     .TX_CLK25_DIV (TX_CLK25_DIV),
     .RX_OUT_DIV (RX_OUT_DIV),
@@ -2718,6 +2663,7 @@ module util_adxcvr #(
     .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
     .qpll2ch_locked (qpll2ch_locked_12),
     .cpll_ref_clk (cpll_ref_clk_15),
+    .up_cpll_rst (up_cpll_rst_15),
     .rx_p (rx_15_p),
     .rx_n (rx_15_n),
     .rx_out_clk (rx_out_clk_15),
@@ -2742,7 +2688,6 @@ module util_adxcvr #(
     .up_es_wdata (up_es_wdata_15),
     .up_es_rdata (up_es_rdata_15),
     .up_es_ready (up_es_ready_15),
-    .up_rx_pll_rst (up_rx_pll_rst_15),
     .up_rx_pll_locked (up_rx_pll_locked_15),
     .up_rx_rst (up_rx_rst_15),
     .up_rx_user_ready (up_rx_user_ready_15),
@@ -2758,7 +2703,6 @@ module util_adxcvr #(
     .up_rx_wdata (up_rx_wdata_15),
     .up_rx_rdata (up_rx_rdata_15),
     .up_rx_ready (up_rx_ready_15),
-    .up_tx_pll_rst (up_tx_pll_rst_15),
     .up_tx_pll_locked (up_tx_pll_locked_15),
     .up_tx_rst (up_tx_rst_15),
     .up_tx_user_ready (up_tx_user_ready_15),
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
index 93e75ba99..0d64da7f3 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
+++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
@@ -40,7 +40,6 @@ for {set n 0} {$n < 16} {incr n} {
     "ready               up_es_ready_${n}       "]
 
   adi_if_infer_bus ADI:user:if_xcvr_ch slave up_rx_${n} [list \
-    "pll_rst             up_rx_pll_rst_${n}     "\
     "pll_locked          up_rx_pll_locked_${n}  "\
     "rst                 up_rx_rst_${n}         "\
     "user_ready          up_rx_user_ready_${n}  "\
@@ -58,7 +57,6 @@ for {set n 0} {$n < 16} {incr n} {
     "ready               up_rx_ready_${n}       "]
 
   adi_if_infer_bus ADI:user:if_xcvr_ch slave up_tx_${n} [list \
-    "pll_rst             up_tx_pll_rst_${n}     "\
     "pll_locked          up_tx_pll_locked_${n}  "\
     "rst                 up_tx_rst_${n}         "\
     "user_ready          up_tx_user_ready_${n}  "\
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 08066de4b..8c1c50724 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -46,7 +46,6 @@ module util_adxcvr_xch #(
 
   parameter   integer CPLL_FBDIV = 2,
   parameter   integer CPLL_FBDIV_4_5 = 5,
-  parameter   integer CPLL_TX_OR_RX_N = 0,
 
   parameter   integer TX_OUT_DIV = 1,
   parameter   integer TX_CLK25_DIV = 20,
@@ -63,6 +62,7 @@ module util_adxcvr_xch #(
   input           qpll2ch_ref_clk,
   input           qpll2ch_locked,
   input           cpll_ref_clk,
+  input           up_cpll_rst,
 
   // receive
 
@@ -98,7 +98,6 @@ module util_adxcvr_xch #(
   input   [15:0]  up_es_wdata,
   output  [15:0]  up_es_rdata,
   output          up_es_ready,
-  input           up_rx_pll_rst,
   output          up_rx_pll_locked,
   input           up_rx_rst,
   input           up_rx_user_ready,
@@ -114,7 +113,6 @@ module util_adxcvr_xch #(
   input   [15:0]  up_rx_wdata,
   output  [15:0]  up_rx_rdata,
   output          up_rx_ready,
-  input           up_tx_pll_rst,
   output          up_tx_pll_locked,
   input           up_tx_rst,
   input           up_tx_user_ready,
@@ -155,7 +153,6 @@ module util_adxcvr_xch #(
 
   // internal signals
 
-  wire            up_cpll_rst;
   wire            up_es_enb_s;
   wire            up_rx_enb_s;
   wire            up_tx_enb_s;
@@ -177,7 +174,6 @@ module util_adxcvr_xch #(
 
   // pll
 
-  assign up_cpll_rst = (CPLL_TX_OR_RX_N == 1) ? up_tx_pll_rst : up_rx_pll_rst;
   assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s;
   assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s;
 

From 2ea997c3d59f89386959b590c51f9fb49181c8b1 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 11:34:29 -0500
Subject: [PATCH 742/972] interfaces- remove channel based pll reset

---
 library/interfaces/interfaces_ip.tcl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/interfaces/interfaces_ip.tcl b/library/interfaces/interfaces_ip.tcl
index 4e98d5682..18a15f478 100644
--- a/library/interfaces/interfaces_ip.tcl
+++ b/library/interfaces/interfaces_ip.tcl
@@ -13,7 +13,6 @@ adi_if_ports input    16  rdata
 adi_if_ports input     1  ready
 
 adi_if_define if_xcvr_ch
-adi_if_ports output    1  pll_rst
 adi_if_ports input     1  pll_locked
 adi_if_ports output    1  rst
 adi_if_ports output    1  user_ready

From 750b23621bf8ca3b7b443f540fd80c9fec6206fc Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 12:53:02 -0500
Subject: [PATCH 743/972] board-tcl: xcvr qpll/cpll changes

---
 projects/scripts/adi_board.tcl | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 4c5abefc2..d7d025033 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -122,7 +122,6 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
     set index $xcvr_tx_index
   }
 
-  create_bd_port -dir I ${txrx}_ref_clk_${index}
   create_bd_port -dir I ${txrx}_sysref_${index}
   create_bd_port -dir ${ctrl_dir} ${txrx}_sync_${index}
   create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ${a_jesd}_rstgen
@@ -144,14 +143,6 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
     ad_connect  ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx}
     ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
 
-    if {(($m%4) == 0) && ($qpll_enable == 1)} {
-      ad_connect  ${u_xcvr}/qpll_ref_clk_${m} ${txrx}_ref_clk_${index}
-    }
-
-    if {$qpll_enable == 0} {
-      ad_connect  ${u_xcvr}/cpll_ref_clk_${m} ${txrx}_ref_clk_${index}
-    }
-
     create_bd_port -dir ${data_dir} ${txrx}_data_${m}_p
     create_bd_port -dir ${data_dir} ${txrx}_data_${m}_n
     ad_connect  ${u_xcvr}/${txrx}_${m}_p ${txrx}_data_${m}_p

From b1a9bd96f1d2747d715d8eb8bcf7285d2972e3bf Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 12:53:29 -0500
Subject: [PATCH 744/972] daq2: xcvr pll changes

---
 projects/daq2/common/daq2_bd.tcl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index 5fc4f268d..af1ecddcd 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -68,6 +68,23 @@ set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_xcvr
 ad_connect  sys_cpu_resetn util_daq2_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_daq2_xcvr/up_clk
 
+# reference clocks & resets
+
+create_bd_port -dir I tx_ref_clk_0
+create_bd_port -dir I rx_ref_clk_0
+
+ad_connect  tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_0
+ad_connect  axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_0
+
+ad_connect  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_0
+ad_connect  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_1
+ad_connect  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_2
+ad_connect  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_3
+ad_connect  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_0
+ad_connect  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_1
+ad_connect  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_2
+ad_connect  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_3
+
 # connections (dac)
 
 ad_xcvrcon  util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd

From 8f562fd0695c4b8917b3284bf0ab6d25729c88c4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 14:43:36 -0500
Subject: [PATCH 745/972] xcvr updates- board procedure

---
 library/xilinx/util_adxcvr/util_adxcvr_ip.tcl | 68 +++++++++++-------
 projects/fmcadc4/common/fmcadc4_bd.tcl        | 10 ++-
 projects/scripts/adi_board.tcl                | 70 +++++++++++--------
 3 files changed, 93 insertions(+), 55 deletions(-)

diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
index 0d64da7f3..b7f5c03f2 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
+++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
@@ -131,17 +131,19 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \
-  [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
-  [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]]
+  [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_qpll_rst_0 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
-  [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
+  [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
   [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
@@ -167,7 +169,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \
-  [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
   [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
@@ -193,7 +196,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \
-  [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
   [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
@@ -219,7 +223,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \
-  [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
   [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
@@ -245,17 +250,19 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \
-  [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
-  [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]]
+  [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_qpll_rst_4 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
-  [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
+  [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
   [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
@@ -281,7 +288,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \
-  [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
   [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
@@ -307,7 +315,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \
-  [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
   [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
@@ -333,7 +342,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \
-  [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
   [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
@@ -359,17 +369,19 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \
-  [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
-  [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]]
+  [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_qpll_rst_8 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
-  [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
+  [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
   [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
@@ -395,7 +407,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \
-  [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
   [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
@@ -421,7 +434,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \
-  [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
   [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
@@ -447,7 +461,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \
-  [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
   [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
@@ -473,17 +488,19 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \
-  [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
-  [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]]
+  [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_qpll_rst_12 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
   (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
-  [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
+  [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
   [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
@@ -509,7 +526,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \
-  [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
   [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
@@ -535,7 +553,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \
-  [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]] 
 
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
   [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
@@ -561,7 +580,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
 set_property enablement_dependency \
   {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \
   (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \
-  [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]]
+  [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \
+  [ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]] 
 
 ipx::save_core [ipx::current_core]
 
diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl
index 0e7ac1c88..8397df8d0 100644
--- a/projects/fmcadc4/common/fmcadc4_bd.tcl
+++ b/projects/fmcadc4/common/fmcadc4_bd.tcl
@@ -39,12 +39,20 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9680_cpack
 set util_fmcadc4_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc4_xcvr]
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc4_xcvr
-set_property -dict [list CONFIG.CPLL_TX_OR_RX_N {1}] $util_fmcadc4_xcvr
 
 create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_data
 set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {128}] [get_bd_cells util_bsplit_rx_data]
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_data]
 
+# reference clocks & resets
+
+create_bd_port -dir I rx_ref_clk_0
+
+ad_xcvrpll  rx_ref_clk_0 util_fmcadc4_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_fmcadc4_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_cpll_rst_*
+
 # connections (gt)
 
 ad_xcvrcon  util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd
diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index d7d025033..09c11fb5a 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -100,6 +100,43 @@ proc ad_connect {p_name_1 p_name_2} {
   }
 }
 
+proc ad_disconnect {p_name_1 p_name_2} {
+
+  set m_name_1 [ad_connect_type $p_name_1]
+  set m_name_2 [ad_connect_type $p_name_2]
+
+  if {[get_property CLASS $m_name_1] eq "bd_net"} {
+    disconnect_bd_net $m_name_1 $m_name_2
+    return
+  }
+
+}
+
+proc ad_reconct {p_name_1 p_name_2} {
+
+  set m_name_1 [ad_connect_type $p_name_1]
+  set m_name_2 [ad_connect_type $p_name_2]
+
+  if {[get_property CLASS $m_name_1] eq "bd_pin"} {
+    delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
+      [find_bd_objs -relation connected_to $m_name_1]]
+    delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
+      [find_bd_objs -relation connected_to $m_name_2]]
+  }
+
+  if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
+    delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
+      [find_bd_objs -relation connected_to $m_name_1]]
+    delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
+      [find_bd_objs -relation connected_to $m_name_2]]
+  }
+
+  ad_connect $p_name_1 $p_name_2
+}
+
+###################################################################################################
+###################################################################################################
+
 proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
 
   global xcvr_tx_index
@@ -166,38 +203,11 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
   }
 }
 
-proc ad_disconnect {p_name_1 p_name_2} {
+proc ad_xcvrpll {m_src m_dst} {
 
-  set m_name_1 [ad_connect_type $p_name_1]
-  set m_name_2 [ad_connect_type $p_name_2]
-
-  if {[get_property CLASS $m_name_1] eq "bd_net"} {
-    disconnect_bd_net $m_name_1 $m_name_2
-    return
+  foreach p_dst [get_bd_pins -quiet $m_dst] {
+    connect_bd_net [ad_connect_type $m_src] $p_dst
   }
-
-}
-
-proc ad_reconct {p_name_1 p_name_2} {
-
-  set m_name_1 [ad_connect_type $p_name_1]
-  set m_name_2 [ad_connect_type $p_name_2]
-
-  if {[get_property CLASS $m_name_1] eq "bd_pin"} {
-    delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
-      [find_bd_objs -relation connected_to $m_name_1]]
-    delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
-      [find_bd_objs -relation connected_to $m_name_2]]
-  }
-
-  if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
-    delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
-      [find_bd_objs -relation connected_to $m_name_1]]
-    delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
-      [find_bd_objs -relation connected_to $m_name_2]]
-  }
-
-  ad_connect $p_name_1 $p_name_2
 }
 
 ###################################################################################################

From daa3df4b9679f4ce289339062f36d1e7adb5ea62 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 22 Nov 2016 16:23:05 -0500
Subject: [PATCH 746/972] projects/- xcvr updates

---
 projects/daq2/common/daq2_bd.tcl              | 15 +---
 projects/fmcadc2/common/fmcadc2_bd.tcl        | 55 +++++++-----
 .../fmcjesdadc1/common/fmcjesdadc1_bd.tcl     | 86 +++++++++++--------
 projects/fmcomms11/common/fmcomms11_bd.tcl    | 17 +++-
 projects/fmcomms7/common/fmcomms7_bd.tcl      | 40 ++++++---
 5 files changed, 129 insertions(+), 84 deletions(-)

diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index af1ecddcd..0d6e6627d 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -73,17 +73,10 @@ ad_connect  sys_cpu_clk util_daq2_xcvr/up_clk
 create_bd_port -dir I tx_ref_clk_0
 create_bd_port -dir I rx_ref_clk_0
 
-ad_connect  tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_0
-ad_connect  axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_0
-
-ad_connect  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_0
-ad_connect  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_1
-ad_connect  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_2
-ad_connect  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_3
-ad_connect  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_0
-ad_connect  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_1
-ad_connect  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_2
-ad_connect  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_3
+ad_xcvrpll  tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
 
 # connections (dac)
 
diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl
index aa41370e8..fa6a7b7b1 100644
--- a/projects/fmcadc2/common/fmcadc2_bd.tcl
+++ b/projects/fmcadc2/common/fmcadc2_bd.tcl
@@ -25,33 +25,46 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 
 set util_fmcadc2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc2_xcvr]
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.CPLL_TX_OR_RX_N {0}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_fmcadc2_xcvr
 
-# connections (gt)
+# reference clocks & resets
 
-ad_xcvrcon  util_fmcadc2_xcvr                 axi_ad9625_xcvr axi_ad9625_jesd
-ad_connect  sys_cpu_resetn                    util_fmcadc2_xcvr/up_rstn
-ad_connect  sys_cpu_clk                       util_fmcadc2_xcvr/up_clk
-ad_connect  util_fmcadc2_xcvr/rx_out_clk_0    axi_ad9625_core/rx_clk
-ad_connect  axi_ad9625_jesd/rx_tdata          axi_ad9625_core/rx_data
-ad_connect  axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof
+create_bd_port -dir I rx_ref_clk_0
+
+ad_xcvrpll  rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_*
+ad_connect  sys_cpu_resetn util_fmcadc2_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_fmcadc2_xcvr/up_clk
 
 # connections (adc)
 
-ad_connect  sys_cpu_clk                   axi_ad9625_fifo/dma_clk
-ad_connect  sys_cpu_clk                   axi_ad9625_dma/s_axis_aclk
-ad_connect  sys_cpu_resetn                axi_ad9625_dma/m_dest_axi_aresetn
-ad_connect  axi_ad9625_core/adc_clk       axi_ad9625_fifo/adc_clk
-ad_connect  axi_ad9625_fifo/adc_rst       axi_ad9625_core/adc_rst
-ad_connect  axi_ad9625_core/adc_enable    axi_ad9625_fifo/adc_wr
-ad_connect  axi_ad9625_core/adc_data      axi_ad9625_fifo/adc_wdata
-ad_connect  axi_ad9625_core/adc_dovf      axi_ad9625_fifo/adc_wovf
-ad_connect  axi_ad9625_fifo/dma_wr        axi_ad9625_dma/s_axis_valid
-ad_connect  axi_ad9625_fifo/dma_wdata     axi_ad9625_dma/s_axis_data
-ad_connect  axi_ad9625_fifo/dma_wready    axi_ad9625_dma/s_axis_ready
-ad_connect  axi_ad9625_fifo/dma_xfer_req  axi_ad9625_dma/s_axis_xfer_req
+ad_xcvrcon  util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd
+ad_connect  util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk
+ad_connect  axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data
+ad_connect  axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof
+ad_connect  sys_cpu_clk axi_ad9625_fifo/dma_clk
+ad_connect  sys_cpu_clk axi_ad9625_dma/s_axis_aclk
+ad_connect  sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
+ad_connect  axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk
+ad_connect  axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst
+ad_connect  axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr
+ad_connect  axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
+ad_connect  axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
+ad_connect  axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
+ad_connect  axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
+ad_connect  axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
+ad_connect  axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
 
 # interconnect (cpu)
 
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
index fd10f8ec0..8b94fbace 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
@@ -51,52 +51,68 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma
 # transceiver core
 
 set util_fmcjesdadc1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcjesdadc1_xcvr]
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcjesdadc1_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_fmcjesdadc1_xcvr
 
+# reference clocks & resets
+
+create_bd_port -dir I rx_ref_clk_0
+
+ad_xcvrpll  rx_ref_clk_0 util_fmcjesdadc1_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_fmcjesdadc1_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_cpll_rst_*
 ad_connect  sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk
 
 # connections (adc)
 
-ad_xcvrcon  util_fmcjesdadc1_xcvr  axi_ad9250_xcvr axi_ad9250_jesd
-ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0   axi_ad9250_0_core/rx_clk
-ad_connect  axi_ad9250_jesd/rx_start_of_frame   axi_ad9250_0_core/rx_sof
-ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0   axi_ad9250_1_core/rx_clk
-ad_connect  axi_ad9250_jesd/rx_start_of_frame   axi_ad9250_1_core/rx_sof
+ad_xcvrcon  util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk
+ad_connect  axi_ad9250_jesd/rx_start_of_frame axi_ad9250_0_core/rx_sof
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk
+ad_connect  axi_ad9250_jesd/rx_start_of_frame axi_ad9250_1_core/rx_sof
 
-ad_connect  axi_ad9250_jesd/rx_tdata  data_bsplit/data
-ad_connect  axi_ad9250_0_core/rx_data   data_bsplit/split_data_0
-ad_connect  axi_ad9250_1_core/rx_data   data_bsplit/split_data_1
+ad_connect  axi_ad9250_jesd/rx_tdata data_bsplit/data
+ad_connect  axi_ad9250_0_core/rx_data data_bsplit/split_data_0
+ad_connect  axi_ad9250_1_core/rx_data data_bsplit/split_data_1
 
-ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0   axi_ad9250_0_cpack/adc_clk
-ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0   axi_ad9250_1_cpack/adc_clk
-ad_connect  axi_ad9250_jesd_rstgen/peripheral_reset   axi_ad9250_0_cpack/adc_rst
-ad_connect  axi_ad9250_jesd_rstgen/peripheral_reset   axi_ad9250_1_cpack/adc_rst
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_cpack/adc_clk
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_cpack/adc_clk
+ad_connect  axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_0_cpack/adc_rst
+ad_connect  axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_1_cpack/adc_rst
 
-ad_connect  axi_ad9250_0_core/adc_enable_a  axi_ad9250_0_cpack/adc_enable_0
-ad_connect  axi_ad9250_0_core/adc_valid_a   axi_ad9250_0_cpack/adc_valid_0
-ad_connect  axi_ad9250_0_core/adc_data_a  axi_ad9250_0_cpack/adc_data_0
-ad_connect  axi_ad9250_0_core/adc_enable_b  axi_ad9250_0_cpack/adc_enable_1
-ad_connect  axi_ad9250_0_core/adc_valid_b   axi_ad9250_0_cpack/adc_valid_1
-ad_connect  axi_ad9250_0_core/adc_data_b  axi_ad9250_0_cpack/adc_data_1
-ad_connect  axi_ad9250_1_core/adc_enable_a  axi_ad9250_1_cpack/adc_enable_0
-ad_connect  axi_ad9250_1_core/adc_valid_a   axi_ad9250_1_cpack/adc_valid_0
-ad_connect  axi_ad9250_1_core/adc_data_a  axi_ad9250_1_cpack/adc_data_0
-ad_connect  axi_ad9250_1_core/adc_enable_b  axi_ad9250_1_cpack/adc_enable_1
-ad_connect  axi_ad9250_1_core/adc_valid_b   axi_ad9250_1_cpack/adc_valid_1
-ad_connect  axi_ad9250_1_core/adc_data_b  axi_ad9250_1_cpack/adc_data_1
+ad_connect  axi_ad9250_0_core/adc_enable_a axi_ad9250_0_cpack/adc_enable_0
+ad_connect  axi_ad9250_0_core/adc_valid_a axi_ad9250_0_cpack/adc_valid_0
+ad_connect  axi_ad9250_0_core/adc_data_a axi_ad9250_0_cpack/adc_data_0
+ad_connect  axi_ad9250_0_core/adc_enable_b axi_ad9250_0_cpack/adc_enable_1
+ad_connect  axi_ad9250_0_core/adc_valid_b axi_ad9250_0_cpack/adc_valid_1
+ad_connect  axi_ad9250_0_core/adc_data_b axi_ad9250_0_cpack/adc_data_1
+ad_connect  axi_ad9250_1_core/adc_enable_a axi_ad9250_1_cpack/adc_enable_0
+ad_connect  axi_ad9250_1_core/adc_valid_a axi_ad9250_1_cpack/adc_valid_0
+ad_connect  axi_ad9250_1_core/adc_data_a axi_ad9250_1_cpack/adc_data_0
+ad_connect  axi_ad9250_1_core/adc_enable_b axi_ad9250_1_cpack/adc_enable_1
+ad_connect  axi_ad9250_1_core/adc_valid_b axi_ad9250_1_cpack/adc_valid_1
+ad_connect  axi_ad9250_1_core/adc_data_b axi_ad9250_1_cpack/adc_data_1
 
-ad_connect  axi_ad9250_0_core/adc_clk   axi_ad9250_0_dma/fifo_wr_clk
-ad_connect  axi_ad9250_0_dma/fifo_wr_en   axi_ad9250_0_cpack/adc_valid
-ad_connect  axi_ad9250_0_dma/fifo_wr_sync   axi_ad9250_0_cpack/adc_sync
-ad_connect  axi_ad9250_0_dma/fifo_wr_din  axi_ad9250_0_cpack/adc_data
-ad_connect  axi_ad9250_0_core/adc_dovf  axi_ad9250_0_dma/fifo_wr_overflow
-ad_connect  axi_ad9250_1_core/adc_clk   axi_ad9250_1_dma/fifo_wr_clk
-ad_connect  axi_ad9250_1_dma/fifo_wr_en   axi_ad9250_1_cpack/adc_valid
-ad_connect  axi_ad9250_1_dma/fifo_wr_sync   axi_ad9250_1_cpack/adc_sync
-ad_connect  axi_ad9250_1_dma/fifo_wr_din  axi_ad9250_1_cpack/adc_data
-ad_connect  axi_ad9250_1_core/adc_dovf  axi_ad9250_1_dma/fifo_wr_overflow
+ad_connect  axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk
+ad_connect  axi_ad9250_0_dma/fifo_wr_en axi_ad9250_0_cpack/adc_valid
+ad_connect  axi_ad9250_0_dma/fifo_wr_sync axi_ad9250_0_cpack/adc_sync
+ad_connect  axi_ad9250_0_dma/fifo_wr_din axi_ad9250_0_cpack/adc_data
+ad_connect  axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow
+ad_connect  axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk
+ad_connect  axi_ad9250_1_dma/fifo_wr_en axi_ad9250_1_cpack/adc_valid
+ad_connect  axi_ad9250_1_dma/fifo_wr_sync axi_ad9250_1_cpack/adc_sync
+ad_connect  axi_ad9250_1_dma/fifo_wr_din axi_ad9250_1_cpack/adc_data
+ad_connect  axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow
 
 # interconnect (cpu)
 
diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl
index 09f47d2a1..11c1ee9ea 100644
--- a/projects/fmcomms11/common/fmcomms11_bd.tcl
+++ b/projects/fmcomms11/common/fmcomms11_bd.tcl
@@ -53,15 +53,24 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 # shared transceiver core
 
 set util_fmcomms11_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms11_xcvr]
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_fmcomms11_xcvr
-set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.TX_CLK25_DIV {7}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcomms11_xcvr
 set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10400020}] $util_fmcomms11_xcvr
-set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr
 
+# reference clocks & resets
+
+create_bd_port -dir I tx_ref_clk_0
+create_bd_port -dir I rx_ref_clk_0
+
+ad_xcvrpll  tx_ref_clk_0 util_fmcomms11_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_fmcomms11_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9162_xcvr/up_pll_rst util_fmcomms11_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcomms11_xcvr/up_cpll_rst_*
 ad_connect  sys_cpu_resetn util_fmcomms11_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_fmcomms11_xcvr/up_clk
 
diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl
index 7db4d8c02..9f82d1522 100644
--- a/projects/fmcomms7/common/fmcomms7_bd.tcl
+++ b/projects/fmcomms7/common/fmcomms7_bd.tcl
@@ -1,4 +1,13 @@
 
+# spi2
+
+set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi]
+set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi
+set_property -dict [list CONFIG.C_NUM_SS_BITS {12}] $axi_fmcomms7_spi
+set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms7_spi
+
+# connections (spi2)
+
 create_bd_port -dir O -from 11 -to 0 spi2_csn_o
 create_bd_port -dir I -from 11 -to 0 spi2_csn_i
 create_bd_port -dir I spi2_clk_i
@@ -7,6 +16,15 @@ create_bd_port -dir I spi2_sdo_i
 create_bd_port -dir O spi2_sdo_o
 create_bd_port -dir I spi2_sdi_i
 
+ad_connect  spi2_csn_i axi_fmcomms7_spi/ss_i
+ad_connect  spi2_csn_o axi_fmcomms7_spi/ss_o
+ad_connect  spi2_clk_i axi_fmcomms7_spi/sck_i
+ad_connect  spi2_clk_o axi_fmcomms7_spi/sck_o
+ad_connect  spi2_sdo_i axi_fmcomms7_spi/io0_i
+ad_connect  spi2_sdo_o axi_fmcomms7_spi/io0_o
+ad_connect  spi2_sdi_i axi_fmcomms7_spi/io1_i
+ad_connect  sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk
+
 # dac peripherals
 
 set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr]
@@ -73,21 +91,17 @@ set util_fmcomms7_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcv
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_xcvr
 
-set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi]
-set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi
-set_property -dict [list CONFIG.C_NUM_SS_BITS {12}] $axi_fmcomms7_spi
-set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms7_spi
+# reference clocks & resets
 
-# connections (spi2)
+create_bd_port -dir I tx_ref_clk_0
+create_bd_port -dir I rx_ref_clk_0
 
-ad_connect  spi2_csn_i axi_fmcomms7_spi/ss_i
-ad_connect  spi2_csn_o axi_fmcomms7_spi/ss_o
-ad_connect  spi2_clk_i axi_fmcomms7_spi/sck_i
-ad_connect  spi2_clk_o axi_fmcomms7_spi/sck_o
-ad_connect  spi2_sdo_i axi_fmcomms7_spi/io0_i
-ad_connect  spi2_sdo_o axi_fmcomms7_spi/io0_o
-ad_connect  spi2_sdi_i axi_fmcomms7_spi/io1_i
-ad_connect  sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk
+ad_xcvrpll  tx_ref_clk_0 util_fmcomms7_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_fmcomms7_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9144_xcvr/up_pll_rst util_fmcomms7_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9680_xcvr/up_pll_rst util_fmcomms7_xcvr/up_cpll_rst_*
+ad_connect  sys_cpu_resetn util_fmcomms7_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_fmcomms7_xcvr/up_clk
 
 # connections (dac)
 

From e5d3bae54da05835c0d59c6b149bca40227d97b5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 23 Nov 2016 11:06:22 -0500
Subject: [PATCH 747/972] projects/ad6676-adrv9371: xcvr updates

---
 projects/ad6676evb/common/ad6676evb_bd.tcl | 53 ++++++++++++++--------
 projects/adrv9371x/common/adrv9371x_bd.tcl | 14 ++++++
 2 files changed, 48 insertions(+), 19 deletions(-)

diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl
index 52a442b35..cf9b7afdf 100644
--- a/projects/ad6676evb/common/ad6676evb_bd.tcl
+++ b/projects/ad6676evb/common/ad6676evb_bd.tcl
@@ -31,32 +31,47 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
 # transceiver core
 
 set util_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad6676_xcvr]
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_ad6676_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_ad6676_xcvr
 
+# reference clocks & resets
+
+create_bd_port -dir I rx_ref_clk_0
+
+ad_xcvrpll  rx_ref_clk_0 util_ad6676_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_ad6676_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_cpll_rst_*
 ad_connect  sys_cpu_resetn util_ad6676_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_ad6676_xcvr/up_clk
 
 # connections (adc)
 
-ad_xcvrcon  util_ad6676_xcvr  axi_ad6676_xcvr axi_ad6676_jesd
-ad_connect  util_ad6676_xcvr/rx_out_clk_0   axi_ad6676_core/rx_clk
-ad_connect  axi_ad6676_jesd/rx_start_of_frame   axi_ad6676_core/rx_sof
-ad_connect  axi_ad6676_jesd/rx_tdata  axi_ad6676_core/rx_data
-ad_connect  util_ad6676_xcvr/rx_out_clk_0   axi_ad6676_cpack/adc_clk
-ad_connect  axi_ad6676_jesd_rstgen/peripheral_reset   axi_ad6676_cpack/adc_rst
-ad_connect  axi_ad6676_core/adc_enable_0  axi_ad6676_cpack/adc_enable_0
-ad_connect  axi_ad6676_core/adc_valid_0   axi_ad6676_cpack/adc_valid_0
-ad_connect  axi_ad6676_core/adc_data_0  axi_ad6676_cpack/adc_data_0
-ad_connect  axi_ad6676_core/adc_enable_1  axi_ad6676_cpack/adc_enable_1
-ad_connect  axi_ad6676_core/adc_valid_1   axi_ad6676_cpack/adc_valid_1
-ad_connect  axi_ad6676_core/adc_data_1  axi_ad6676_cpack/adc_data_1
-
-ad_connect  axi_ad6676_core/adc_clk   axi_ad6676_dma/fifo_wr_clk
-ad_connect  axi_ad6676_dma/fifo_wr_en   axi_ad6676_cpack/adc_valid
-ad_connect  axi_ad6676_dma/fifo_wr_sync   axi_ad6676_cpack/adc_sync
-ad_connect  axi_ad6676_dma/fifo_wr_din  axi_ad6676_cpack/adc_data
-ad_connect  axi_ad6676_core/adc_dovf  axi_ad6676_dma/fifo_wr_overflow
+ad_xcvrcon  util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd
+ad_connect  util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk
+ad_connect  axi_ad6676_jesd/rx_start_of_frame axi_ad6676_core/rx_sof
+ad_connect  axi_ad6676_jesd/rx_tdata axi_ad6676_core/rx_data
+ad_connect  util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/adc_clk
+ad_connect  axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/adc_rst
+ad_connect  axi_ad6676_core/adc_enable_0 axi_ad6676_cpack/adc_enable_0
+ad_connect  axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/adc_valid_0
+ad_connect  axi_ad6676_core/adc_data_0 axi_ad6676_cpack/adc_data_0
+ad_connect  axi_ad6676_core/adc_enable_1 axi_ad6676_cpack/adc_enable_1
+ad_connect  axi_ad6676_core/adc_valid_1 axi_ad6676_cpack/adc_valid_1
+ad_connect  axi_ad6676_core/adc_data_1 axi_ad6676_cpack/adc_data_1
+ad_connect  axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk
+ad_connect  axi_ad6676_dma/fifo_wr_en axi_ad6676_cpack/adc_valid
+ad_connect  axi_ad6676_dma/fifo_wr_sync axi_ad6676_cpack/adc_sync
+ad_connect  axi_ad6676_dma/fifo_wr_din axi_ad6676_cpack/adc_data
+ad_connect  axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow
 
 # interconnect (cpu)
 
diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index f36ba1345..0e375d72f 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -124,6 +124,20 @@ set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_ad9371_xcvr
 
 # xcvr interfaces
 
+create_bd_port -dir I tx_ref_clk_0
+create_bd_port -dir I rx_ref_clk_0
+create_bd_port -dir I rx_ref_clk_2
+
+ad_xcvrpll  tx_ref_clk_0 util_ad9371_xcvr/qpll_ref_clk_0
+ad_xcvrpll  rx_ref_clk_0 util_ad9371_xcvr/cpll_ref_clk_0
+ad_xcvrpll  rx_ref_clk_0 util_ad9371_xcvr/cpll_ref_clk_1
+ad_xcvrpll  rx_ref_clk_2 util_ad9371_xcvr/cpll_ref_clk_2
+ad_xcvrpll  rx_ref_clk_2 util_ad9371_xcvr/cpll_ref_clk_3
+ad_xcvrpll  axi_ad9371_tx_xcvr/up_pll_rst util_ad9371_xcvr/up_qpll_rst_0
+ad_xcvrpll  axi_ad9371_rx_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_0
+ad_xcvrpll  axi_ad9371_rx_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_1
+ad_xcvrpll  axi_ad9371_rx_os_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_2
+ad_xcvrpll  axi_ad9371_rx_os_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_3
 ad_connect  sys_cpu_resetn util_ad9371_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_ad9371_xcvr/up_clk
 

From 025420d6f868261fd6de58c4bb5249af1cf0cffc Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 23 Nov 2016 12:00:13 -0500
Subject: [PATCH 748/972] library/axi_xcvrlb- xcvr changes

---
 library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
index 9cd02f4a8..8e2c5d4e0 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
@@ -247,18 +247,19 @@ module axi_xcvrlb_1 (
     .XCVR_TYPE (0),
     .CPLL_FBDIV (2),
     .CPLL_FBDIV_4_5 (5),
-    .CPLL_TX_OR_RX_N (0),
     .TX_OUT_DIV (1),
     .TX_CLK25_DIV (10),
     .RX_OUT_DIV (1),
     .RX_CLK25_DIV (10),
+    .RX_DFE_LPM_CFG (16'h0904),
     .RX_PMA_CFG ('h00018480),
-    .RX_CDR_CFG ('h03000023ff20400020))
+    .RX_CDR_CFG ('h03000023ff10200020))
   i_xch (
     .qpll2ch_clk (1'b0),
     .qpll2ch_ref_clk (1'b0),
     .qpll2ch_locked (1'b1),
     .cpll_ref_clk (ref_clk),
+    .up_cpll_rst (up_pll_rst_s),
     .rx_p (rx_p),
     .rx_n (rx_n),
     .rx_out_clk (clk),
@@ -283,7 +284,6 @@ module axi_xcvrlb_1 (
     .up_es_wdata (16'd0),
     .up_es_rdata (),
     .up_es_ready (),
-    .up_rx_pll_rst (up_pll_rst_s),
     .up_rx_pll_locked (up_rx_pll_locked_s),
     .up_rx_rst (up_rst_s),
     .up_rx_user_ready (up_user_ready_s),
@@ -299,7 +299,6 @@ module axi_xcvrlb_1 (
     .up_rx_wdata (16'd0),
     .up_rx_rdata (),
     .up_rx_ready (),
-    .up_tx_pll_rst (up_pll_rst_s),
     .up_tx_pll_locked (up_tx_pll_locked_s),
     .up_tx_rst (up_rst_s),
     .up_tx_user_ready (up_user_ready_s),

From 4e3e623530bb6183d5148478593e2d4e2dd03469 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 23 Nov 2016 14:02:59 -0500
Subject: [PATCH 749/972] pzsdr2/ccpci- updates

---
 projects/pzsdr2/ccpci_lvds/system_constr.xdc |  36 ---
 projects/pzsdr2/ccpci_lvds/system_top.v      | 243 +++++++------------
 projects/pzsdr2/common/ccpci_bd.tcl          |   7 +
 projects/pzsdr2/common/ccpci_constr.xdc      |   6 +-
 4 files changed, 93 insertions(+), 199 deletions(-)
 delete mode 100644 projects/pzsdr2/ccpci_lvds/system_constr.xdc

diff --git a/projects/pzsdr2/ccpci_lvds/system_constr.xdc b/projects/pzsdr2/ccpci_lvds/system_constr.xdc
deleted file mode 100644
index bfc2f8efd..000000000
--- a/projects/pzsdr2/ccpci_lvds/system_constr.xdc
+++ /dev/null
@@ -1,36 +0,0 @@
-
-# constraints
-# reference-only & not-effective
-# (axi_pcie_x0y0.xdc)
-
-set_property  -dict {PACKAGE_PIN  U6 }  [get_ports pcie_ref_clk_p]                                      ; ## MGTREFCLK1P_112 (JX3.2) (P2.A13)
-set_property  -dict {PACKAGE_PIN  U5 }  [get_ports pcie_ref_clk_n]                                      ; ## MGTREFCLK1N_112 (JX3.4) (P2.A14)
-set_property  -dict {PACKAGE_PIN  T4 }  [get_ports pcie_data_rx_p[0]]                                   ; ## MGTXRXP3_112 (JX1.97) (P2.B14)
-set_property  -dict {PACKAGE_PIN  T3 }  [get_ports pcie_data_rx_n[0]]                                   ; ## MGTXRXN3_112 (JX1.99) (P2.B15)
-set_property  -dict {PACKAGE_PIN  V4 }  [get_ports pcie_data_rx_p[1]]                                   ; ## MGTXRXP2_112 (JX1.92) (P2.B19)
-set_property  -dict {PACKAGE_PIN  V3 }  [get_ports pcie_data_rx_n[1]]                                   ; ## MGTXRXN2_112 (JX1.94) (P2.B20)
-set_property  -dict {PACKAGE_PIN  Y4 }  [get_ports pcie_data_rx_p[2]]                                   ; ## MGTXRXP1_112 (JX1.91) (P2.B23)
-set_property  -dict {PACKAGE_PIN  Y3 }  [get_ports pcie_data_rx_n[2]]                                   ; ## MGTXRXN1_112 (JX1.93) (P2.B24)
-set_property  -dict {PACKAGE_PIN  AB4}  [get_ports pcie_data_rx_p[3]]                                   ; ## MGTXRXP0_112 (JX1.88) (P2.B27)
-set_property  -dict {PACKAGE_PIN  AB3}  [get_ports pcie_data_rx_n[3]]                                   ; ## MGTXRXN0_112 (JX1.90) (P2.B28)
-set_property  -dict {PACKAGE_PIN  R2 }  [get_ports pcie_data_tx_p[0]]                                   ; ## MGTXTXP3_112 (JX3.19) (P2.A16)
-set_property  -dict {PACKAGE_PIN  R1 }  [get_ports pcie_data_tx_n[0]]                                   ; ## MGTXTXN3_112 (JX3.21) (P2.A17)
-set_property  -dict {PACKAGE_PIN  U2 }  [get_ports pcie_data_tx_p[1]]                                   ; ## MGTXTXP2_112 (JX3.14) (P2.A21)
-set_property  -dict {PACKAGE_PIN  U1 }  [get_ports pcie_data_tx_n[1]]                                   ; ## MGTXTXN2_112 (JX3.16) (P2.A22)
-set_property  -dict {PACKAGE_PIN  W2 }  [get_ports pcie_data_tx_p[2]]                                   ; ## MGTXTXP1_112 (JX3.13) (P2.A25)
-set_property  -dict {PACKAGE_PIN  W1 }  [get_ports pcie_data_tx_n[2]]                                   ; ## MGTXTXN1_112 (JX3.15) (P2.A26)
-set_property  -dict {PACKAGE_PIN  AA2}  [get_ports pcie_data_tx_p[3]]                                   ; ## MGTXTXP0_112 (JX3.8 ) (P2.A29)
-set_property  -dict {PACKAGE_PIN  AA1}  [get_ports pcie_data_tx_n[3]]                                   ; ## MGTXTXN0_112 (JX3.10) (P2.A30)
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS33} [get_ports pcie_rstn]                      ; ## IO_L19P_T3_13
-set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS33} [get_ports pcie_waken]                     ; ## IO_L20N_T3_13
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS33} [get_ports pcie_rstn_good]                 ; ## IO_L22N_T3_12
-
-# Default constraints have LVCMOS25, overwite it
-
-set_property  -dict {IOSTANDARD LVCMOS33} [get_ports iic_scl]                                           ; ## IO_L5P_T0_13
-set_property  -dict {IOSTANDARD LVCMOS33} [get_ports iic_sda]                                           ; ## IO_L5N_T0_13
-
-set_property PULLUP true [get_ports pcie_rstn]
-create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p]
-
-
diff --git a/projects/pzsdr2/ccpci_lvds/system_top.v b/projects/pzsdr2/ccpci_lvds/system_top.v
index a8bcc2e3b..aa610357b 100644
--- a/projects/pzsdr2/ccpci_lvds/system_top.v
+++ b/projects/pzsdr2/ccpci_lvds/system_top.v
@@ -39,176 +39,97 @@
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  iic_scl,
-  iic_sda,
+  inout           iic_scl,
+  inout           iic_sda,
 
-  rx_clk_in_p,
-  rx_clk_in_n,
-  rx_frame_in_p,
-  rx_frame_in_n,
-  rx_data_in_p,
-  rx_data_in_n,
-  tx_clk_out_p,
-  tx_clk_out_n,
-  tx_frame_out_p,
-  tx_frame_out_n,
-  tx_data_out_p,
-  tx_data_out_n,
+  input           rx_clk_in_p,
+  input           rx_clk_in_n,
+  input           rx_frame_in_p,
+  input           rx_frame_in_n,
+  input   [ 5:0]  rx_data_in_p,
+  input   [ 5:0]  rx_data_in_n,
+  output          tx_clk_out_p,
+  output          tx_clk_out_n,
+  output          tx_frame_out_p,
+  output          tx_frame_out_n,
+  output  [ 5:0]  tx_data_out_p,
+  output  [ 5:0]  tx_data_out_n,
 
-  enable,
-  txnrx,
-  clk_out,
+  output          enable,
+  output          txnrx,
+  input           clkout_in,
 
-  gpio_clksel,
-  gpio_resetb,
-  gpio_sync,
-  gpio_en_agc,
-  gpio_ctl,
-  gpio_status,
+  inout           gpio_clksel,
+  inout           gpio_resetb,
+  inout           gpio_sync,
+  inout           gpio_en_agc,
+  inout   [ 3:0]  gpio_ctl,
+  inout   [ 7:0]  gpio_status,
 
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
+  output          spi_csn,
+  output          spi_clk,
+  output          spi_mosi,
+  input           spi_miso,
 
-  pcie_rstn,
-  pcie_waken,
-  pcie_ref_clk_p,
-  pcie_ref_clk_n,
-  pcie_data_rx_p,
-  pcie_data_rx_n,
-  pcie_data_tx_p,
-  pcie_data_tx_n,
+  input           pcie_rstn,
+  inout           pcie_waken,
+  input           pcie_ref_clk_p,
+  input           pcie_ref_clk_n,
+  input   [ 3:0]  pcie_data_rx_p,
+  input   [ 3:0]  pcie_data_rx_n,
+  output  [ 3:0]  pcie_data_tx_p,
+  output  [ 3:0]  pcie_data_tx_n,
 
-  pcie_rstn_good);
+  output          pcie_reset_done);
 
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
+  // internal registers
 
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  input           rx_clk_in_p;
-  input           rx_clk_in_n;
-  input           rx_frame_in_p;
-  input           rx_frame_in_n;
-  input   [ 5:0]  rx_data_in_p;
-  input   [ 5:0]  rx_data_in_n;
-  output          tx_clk_out_p;
-  output          tx_clk_out_n;
-  output          tx_frame_out_p;
-  output          tx_frame_out_n;
-  output  [ 5:0]  tx_data_out_p;
-  output  [ 5:0]  tx_data_out_n;
-
-  output          enable;
-  output          txnrx;
-  input           clk_out;
-
-  inout           gpio_clksel;
-  inout           gpio_resetb;
-  inout           gpio_sync;
-  inout           gpio_en_agc;
-  inout   [ 3:0]  gpio_ctl;
-  inout   [ 7:0]  gpio_status;
-
-  output          spi_csn;
-  output          spi_clk;
-  output          spi_mosi;
-  input           spi_miso;
-
-  input           pcie_rstn;
-  inout           pcie_waken;
-  input           pcie_ref_clk_p;
-  input           pcie_ref_clk_n;
-  input   [ 3:0]  pcie_data_rx_p;
-  input   [ 3:0]  pcie_data_rx_n;
-  output  [ 3:0]  pcie_data_tx_p;
-  output  [ 3:0]  pcie_data_tx_n;
-
-  output          pcie_rstn_good;
+  reg             pcie_reset_done_int = 1'b0;
 
   // internal signals
 
-  reg [3:0]       pcie_rstn_cnt0 = 'h00;
-  reg [3:0]       pcie_rstn_cnt1 = 'h00;
-  reg             pcie_rstn_good = 1'b0;
-
   wire            pcie_ref_clk;
+  wire            pcie_clk;
+  wire            pcie_rst;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
 
-  wire    [63:0]  gpio_ps_i;
-
   // assignments
 
   assign pcie_waken = 1'bz;
-  assign gpio_ps_i[0] = pcie_rstn_good;
-  assign gpio_ps_i[63:1] = 'h00;
+  assign pcie_reset_done = pcie_reset_done_int;
 
   // PCIe reset monitor
 
-  always @(posedge pcie_ref_clk) begin
-    // If we see a stable low level followed by a stable high level we assume we
-    // got a good PCIe reset
-    if (pcie_rstn_cnt0 != 'hf) begin
-      if (pcie_rstn == 1'b0) begin
-        pcie_rstn_cnt0 <= pcie_rstn_cnt0 + 1'b1;
-      end else begin
-        pcie_rstn_cnt0 <= 'h00;
-      end
-    end else if (pcie_rstn_cnt1 != 'hf) begin
-      if (pcie_rstn == 1'b1) begin
-        pcie_rstn_cnt1 <= pcie_rstn_cnt1 + 1'b1;
-      end else begin
-        pcie_rstn_cnt1 <= 'h00;
-      end
+  always @(posedge pcie_clk or posedge pcie_rst) begin
+    if (pcie_rst == 1'b1) begin
+      pcie_reset_done_int <= 1'b0;
     end else begin
-      pcie_rstn_good <= 1'b1;
+      pcie_reset_done_int <= 1'b1;
     end
   end
 
@@ -255,18 +176,33 @@ module system_top (
     .fixed_io_ps_clk (fixed_io_ps_clk),
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gpio_i (gpio_ps_i),
+    .gpio_i ({63'd0, pcie_reset_done_int}),
     .gpio_o (),
     .gpio_t (),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
+    .pcie_clk (pcie_clk),
     .pcie_data_rxn (pcie_data_rx_n),
     .pcie_data_rxp (pcie_data_rx_p),
     .pcie_data_txn (pcie_data_tx_n),
     .pcie_data_txp (pcie_data_tx_p),
     .pcie_ref_clk (pcie_ref_clk),
+    .pcie_rst (pcie_rst),
     .pcie_rstn (pcie_rstn),
+    .pl_gpio0_i (gpio_i[31:0]),
+    .pl_gpio0_o (gpio_o[31:0]),
+    .pl_gpio0_t (gpio_t[31:0]),
+    .pl_gpio1_i (gpio_i[63:32]),
+    .pl_gpio1_o (gpio_o[63:32]),
+    .pl_gpio1_t (gpio_t[63:32]),
+    .pl_spi_clk_i (spi_clk),
+    .pl_spi_clk_o (spi_clk),
+    .pl_spi_csn_i (spi_csn),
+    .pl_spi_csn_o (spi_csn),
+    .pl_spi_sdi_i (spi_miso),
+    .pl_spi_sdo_i (spi_mosi),
+    .pl_spi_sdo_o (spi_mosi),
     .ps_intr_00 (1'b0),
     .ps_intr_01 (1'b0),
     .ps_intr_02 (1'b0),
@@ -315,20 +251,7 @@ module system_top (
     .tx_frame_out_p (tx_frame_out_p),
     .txnrx (txnrx),
     .up_enable (gpio_o[47]),
-    .up_txnrx (gpio_o[48]),
-    .pl_spi_clk_o(spi_clk),
-    .pl_spi_clk_i(spi_clk),
-    .pl_spi_sdo_o(spi_mosi),
-    .pl_spi_sdo_i(spi_mosi),
-    .pl_spi_sdi_i(spi_miso),
-    .pl_spi_csn_o(spi_csn),
-    .pl_spi_csn_i(spi_csn),
-    .pl_gpio0_o(gpio_o[31:0]),
-    .pl_gpio0_t(gpio_t[31:0]),
-    .pl_gpio0_i(gpio_i[31:0]),
-    .pl_gpio1_o(gpio_o[63:32]),
-    .pl_gpio1_t(gpio_t[63:32]),
-    .pl_gpio1_i(gpio_i[63:32]));
+    .up_txnrx (gpio_o[48]));
 
 endmodule
 
diff --git a/projects/pzsdr2/common/ccpci_bd.tcl b/projects/pzsdr2/common/ccpci_bd.tcl
index c0157b824..d42c21121 100644
--- a/projects/pzsdr2/common/ccpci_bd.tcl
+++ b/projects/pzsdr2/common/ccpci_bd.tcl
@@ -67,6 +67,7 @@ set_property -dict [list CONFIG.PCIEBAR2AXIBAR_0 {0x40000000}] $axi_pcie_x4
 set_property -dict [list CONFIG.AXIBAR2PCIEBAR_0 {0x00000000}] $axi_pcie_x4
 
 set axi_pcie_x4_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_pcie_x4_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {16}] $axi_pcie_x4_rstgen
 
 set axi_pcie_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_pcie_intc]
 set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_pcie_intc
@@ -88,6 +89,12 @@ ad_connect  axi_pcie_x4/mmcm_lock axi_pcie_x4_rstgen/dcm_locked
 ad_connect  axi_pcie_x4/axi_ctl_aclk_out axi_pcie_x4_rstgen/slowest_sync_clk
 ad_connect  pcie_axi_resetn axi_pcie_x4/axi_aresetn
 
+create_bd_port -dir O pcie_rst
+create_bd_port -dir O pcie_clk
+
+ad_connect  axi_pcie_x4_rstgen/bus_struct_reset pcie_rst
+ad_connect  axi_pcie_x4/axi_ctl_aclk_out pcie_clk
+
 # interrupts
 
 ad_connect  axi_pcie_intc/irq axi_pcie_x4/INTX_MSI_Request
diff --git a/projects/pzsdr2/common/ccpci_constr.xdc b/projects/pzsdr2/common/ccpci_constr.xdc
index 759e97b9e..edc2b851a 100644
--- a/projects/pzsdr2/common/ccpci_constr.xdc
+++ b/projects/pzsdr2/common/ccpci_constr.xdc
@@ -21,9 +21,9 @@ set_property  -dict {PACKAGE_PIN  W2 }  [get_ports pcie_data_tx_p[2]]
 set_property  -dict {PACKAGE_PIN  W1 }  [get_ports pcie_data_tx_n[2]]                                   ; ## U1,W1,MGTXTX1_112_JX3_N,JX3,15,MGTXTX1_112_JX3_N,P2,A26
 set_property  -dict {PACKAGE_PIN  AA2}  [get_ports pcie_data_tx_p[3]]                                   ; ## U1,AA2,MGTXTX0_112_JX3_P,JX3,8,MGTXTX0_112_JX3_P,P2,A29
 set_property  -dict {PACKAGE_PIN  AA1}  [get_ports pcie_data_tx_n[3]]                                   ; ## U1,AA1,MGTXTX0_112_JX3_N,JX3,10,MGTXTX0_112_JX3_N,P2,A30
-set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS18} [get_ports pcie_rstn]                      ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,PCIE_PRSNT,P2,A11
-set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS18} [get_ports pcie_waken]                     ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,PCIE_WAKEB,P2,B11
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS18} [get_ports pcie_rstn_good]                 ; ## IO_L22N_T3_12, NOT-CONNECTED ????
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports pcie_rstn]                      ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,PCIE_PRSNT,P2,A11
+set_property  -dict {PACKAGE_PIN  AB20  IOSTANDARD LVCMOS25} [get_ports pcie_waken]                     ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,PCIE_WAKEB,P2,B11
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS25} [get_ports pcie_reset_done]                ; ## IO_L22N_T3_12, NOT-CONNECTED ????
 
 set_property PULLUP true [get_ports pcie_rstn]
 create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p]

From 862bd7ef2cc235fa59446d042fab99b9d5e1b618 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 23 Nov 2016 15:02:20 -0500
Subject: [PATCH 750/972] daq3/zc706- xcvr changes

---
 library/axi_ad9152/axi_ad9152_ip.tcl |  1 +
 projects/daq3/common/daq3_bd.tcl     | 54 +++++++++++++++-------------
 projects/daq3/zc706/system_bd.tcl    | 31 +---------------
 projects/daq3/zc706/system_top.v     |  2 --
 4 files changed, 32 insertions(+), 56 deletions(-)

diff --git a/library/axi_ad9152/axi_ad9152_ip.tcl b/library/axi_ad9152/axi_ad9152_ip.tcl
index 055b8becb..9fb507c42 100644
--- a/library/axi_ad9152/axi_ad9152_ip.tcl
+++ b/library/axi_ad9152/axi_ad9152_ip.tcl
@@ -29,6 +29,7 @@ adi_ip_constraints axi_ad9152 [list \
 
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]
 
diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl
index 35ded3e5f..543fc4ea5 100644
--- a/projects/daq3/common/daq3_bd.tcl
+++ b/projects/daq3/common/daq3_bd.tcl
@@ -6,14 +6,16 @@ set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9152_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9152_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9152_xcvr
 
-set sys_ad9152_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9152_rstgen]
-
-set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
-
 set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9152_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd
 
+set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
+
+set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9152_upack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack
+
 set axi_ad9152_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9152_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9152_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9152_dma
@@ -26,10 +28,6 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9152_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma
 
-set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9152_upack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack
-
 # adc peripherals
 
 set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
@@ -37,14 +35,16 @@ set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
 
-set sys_ad9680_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9680_rstgen]
-
-set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
-
 set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
 set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
 
+set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
+
+set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
+
 set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
@@ -58,10 +58,6 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
 
-set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
-
 # shared transceiver core
 
 set util_daq3_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq3_xcvr]
@@ -71,13 +67,25 @@ set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_xcvr
 ad_connect  sys_cpu_resetn util_daq3_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_daq3_xcvr/up_clk
 
+# reference clocks & resets
+
+create_bd_port -dir I tx_ref_clk_0
+create_bd_port -dir I rx_ref_clk_0
+
+ad_xcvrpll  tx_ref_clk_0 util_daq3_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_daq3_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9152_xcvr/up_pll_rst util_daq3_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_*
+
 # connections (dac)
 
 ad_xcvrcon  util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd
+ad_reconct  util_daq3_xcvr/tx_0 axi_ad9152_jesd/gt0_tx
+ad_reconct  util_daq3_xcvr/tx_1 axi_ad9152_jesd/gt3_tx
+ad_reconct  util_daq3_xcvr/tx_2 axi_ad9152_jesd/gt1_tx
+ad_reconct  util_daq3_xcvr/tx_3 axi_ad9152_jesd/gt2_tx
 ad_connect  util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk
 ad_connect  axi_ad9152_jesd/tx_tdata axi_ad9152_core/tx_data
-ad_connect  util_daq3_xcvr/tx_out_clk_0 sys_ad9152_rstgen/slowest_sync_clk
-ad_connect  util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
 ad_connect  util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk
 ad_connect  axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0
 ad_connect  axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0
@@ -85,6 +93,7 @@ ad_connect  axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0
 ad_connect  axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1
 ad_connect  axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1
 ad_connect  axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1
+ad_connect  util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
 ad_connect  axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid
 ad_connect  axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data
 ad_connect  axi_ad9152_upack/dma_xfer_in axi_ad9152_fifo/dac_xfer_out
@@ -104,17 +113,16 @@ ad_xcvrcon  util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd
 ad_connect  util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
 ad_connect  axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
 ad_connect  axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
-ad_connect  util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
-ad_connect  util_daq3_xcvr/tx_out_clk_0 sys_ad9680_rstgen/slowest_sync_clk
-ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
 ad_connect  util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
-ad_connect  sys_ad9680_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
 ad_connect  axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
 ad_connect  axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
 ad_connect  axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
 ad_connect  axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
 ad_connect  axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
 ad_connect  axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
+ad_connect  util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
+ad_connect  axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
 ad_connect  axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
 ad_connect  axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
 ad_connect  sys_cpu_clk axi_ad9680_fifo/dma_clk
@@ -154,7 +162,5 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
 ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq
 ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
 
-# unused
-
 ad_connect  axi_ad9152_fifo/dac_fifo_bypass GND
 
diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl
index 1c2f1794c..17d016d53 100644
--- a/projects/daq3/zc706/system_bd.tcl
+++ b/projects/daq3/zc706/system_bd.tcl
@@ -3,8 +3,8 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
 source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
-p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
 p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
+p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
 
 create_bd_port -dir I -type rst sys_rst
 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
@@ -23,32 +23,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
 
 source ../common/daq3_bd.tcl
 
-# ila
-
-set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc
-set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
-set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
-
-set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
-set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
-
-ad_connect  util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/din_rst
-ad_connect  util_daq3_xcvr/rx_out_clk_0 mfifo_adc/din_clk
-ad_connect  axi_ad9680_core/adc_valid_0 mfifo_adc/din_valid
-ad_connect  axi_ad9680_core/adc_data_0 mfifo_adc/din_data_0
-ad_connect  axi_ad9680_core/adc_data_1 mfifo_adc/din_data_1
-ad_connect  util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/dout_rst
-ad_connect  util_daq3_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
-ad_connect  util_daq3_xcvr/rx_out_clk_0 ila_adc/clk
-ad_connect  mfifo_adc/dout_valid ila_adc/probe0
-ad_connect  mfifo_adc/dout_data_0 ila_adc/probe1
-ad_connect  mfifo_adc/dout_data_1 ila_adc/probe2
-
-
diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v
index 6273a25a0..217a9ce2c 100644
--- a/projects/daq3/zc706/system_top.v
+++ b/projects/daq3/zc706/system_top.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 

From 22e230618c518c18447a946bf79f3315d0215617 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 23 Nov 2016 16:21:19 -0500
Subject: [PATCH 751/972] scripts/adi_board.tcl- support multiple xcvrs

---
 projects/scripts/adi_board.tcl | 42 ++++++++++++++++++++++++++--------
 1 file changed, 33 insertions(+), 9 deletions(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 09c11fb5a..ced9504c5 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -8,8 +8,10 @@ variable sys_hp2_interconnect_index
 variable sys_hp3_interconnect_index
 variable sys_mem_interconnect_index
 
+variable xcvr_index
 variable xcvr_tx_index
 variable xcvr_rx_index
+variable xcvr_instance
 
 ###################################################################################################
 ###################################################################################################
@@ -21,8 +23,10 @@ set sys_hp2_interconnect_index -1
 set sys_hp3_interconnect_index -1
 set sys_mem_interconnect_index -1
 
+set xcvr_index -1
 set xcvr_tx_index 0
 set xcvr_rx_index 0
+set xcvr_instance NONE
 
 ###################################################################################################
 ###################################################################################################
@@ -138,14 +142,23 @@ proc ad_reconct {p_name_1 p_name_2} {
 ###################################################################################################
 
 proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
-
+  
+  global xcvr_index
   global xcvr_tx_index
   global xcvr_rx_index
+  global xcvr_instance
 
   set no_of_lanes [get_property CONFIG.NUM_OF_LANES [get_bd_cells $a_xcvr]]
   set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
   set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
 
+  if {$xcvr_instance ne $u_xcvr} {
+    set xcvr_index [expr ($xcvr_index + 1)]
+    set xcvr_tx_index 0
+    set xcvr_rx_index 0
+    set xcvr_instance $u_xcvr
+  }
+
   set txrx "rx"
   set data_dir "I"
   set ctrl_dir "O"
@@ -159,8 +172,19 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
     set index $xcvr_tx_index
   }
 
-  create_bd_port -dir I ${txrx}_sysref_${index}
-  create_bd_port -dir ${ctrl_dir} ${txrx}_sync_${index}
+  set m_sysref ${txrx}_sysref_${index}
+  set m_sync ${txrx}_sync_${index}
+  set m_data ${txrx}_data
+
+  if {$xcvr_index >= 1} {
+
+    set m_sysref ${txrx}_sysref_${xcvr_index}_${index}
+    set m_sync ${txrx}_sync_${xcvr_index}_${index}
+    set m_data ${txrx}_data_${xcvr_index}
+  }
+
+  create_bd_port -dir I $m_sysref
+  create_bd_port -dir ${ctrl_dir} $m_sync
   create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ${a_jesd}_rstgen
 
   for {set n 0} {$n < $no_of_lanes} {incr n} {
@@ -180,14 +204,14 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
     ad_connect  ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx}
     ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
 
-    create_bd_port -dir ${data_dir} ${txrx}_data_${m}_p
-    create_bd_port -dir ${data_dir} ${txrx}_data_${m}_n
-    ad_connect  ${u_xcvr}/${txrx}_${m}_p ${txrx}_data_${m}_p
-    ad_connect  ${u_xcvr}/${txrx}_${m}_n ${txrx}_data_${m}_n
+    create_bd_port -dir ${data_dir} ${m_data}_${m}_p
+    create_bd_port -dir ${data_dir} ${m_data}_${m}_n
+    ad_connect  ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
+    ad_connect  ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
   }
 
-  ad_connect  ${a_jesd}/${txrx}_sysref ${txrx}_sysref_${index}
-  ad_connect  ${a_jesd}/${txrx}_sync ${txrx}_sync_${index}
+  ad_connect  ${a_jesd}/${txrx}_sysref $m_sysref
+  ad_connect  ${a_jesd}/${txrx}_sync $m_sync
   ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk
   ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
   ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk

From 11b57290f196104e8fcdee446d7d79c753408977 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 23 Nov 2016 16:21:57 -0500
Subject: [PATCH 752/972] fmcadc5- replaced with axi_adxcvr

---
 projects/fmcadc5/common/fmcadc5_bd.tcl    | 323 ++++++----------------
 projects/fmcadc5/vc707/Makefile           |  12 +-
 projects/fmcadc5/vc707/system_bd.tcl      |  14 +-
 projects/fmcadc5/vc707/system_constr.xdc  |   4 +-
 projects/fmcadc5/vc707/system_project.tcl |  10 +-
 projects/fmcadc5/vc707/system_top.v       | 320 +++++++++------------
 6 files changed, 243 insertions(+), 440 deletions(-)

diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl
index 3ddb1360e..fef366da6 100644
--- a/projects/fmcadc5/common/fmcadc5_bd.tcl
+++ b/projects/fmcadc5/common/fmcadc5_bd.tcl
@@ -1,23 +1,36 @@
-
-# ad9625
-
-create_bd_port -dir I rx_ref_clk_0
-create_bd_port -dir I -from 7 -to 0 rx_data_0_p
-create_bd_port -dir I -from 7 -to 0 rx_data_0_n
-create_bd_port -dir O rx_sync_0
-create_bd_port -dir I rx_ref_clk_1
-create_bd_port -dir I -from 7 -to 0 rx_data_1_p
-create_bd_port -dir I -from 7 -to 0 rx_data_1_n
-create_bd_port -dir O rx_sync_1
-create_bd_port -dir O rx_sysref
-create_bd_port -dir O rx_clk
-
 # adc peripherals
 
-set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
-set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
-set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
-set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
+set util_fmcadc5_0_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc5_0_xcvr]
+set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc5_0_xcvr
+set util_fmcadc5_1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc5_1_xcvr]
+set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc5_1_xcvr
+
+set axi_ad9625_0_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_0_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_0_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_0_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_0_xcvr
+set axi_ad9625_1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_1_xcvr]
+set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_1_xcvr
+set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_1_xcvr
+set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_1_xcvr
 
 set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_0_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
@@ -26,6 +39,15 @@ set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 a
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
 
+set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
+set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
+set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
+set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
+
+set util_ad9625_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9625_cpack]
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {256}] $util_ad9625_cpack
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9625_cpack
+
 set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma
@@ -41,221 +63,58 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 
 p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 512 18
 
-# adc common gt
+# reference clocks & resets
 
-set axi_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_0_gt]
-set_property -dict [list CONFIG.ID {0}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
+create_bd_port -dir I rx_ref_clk_0
+create_bd_port -dir I rx_ref_clk_1
 
-set axi_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_1_gt]
-set_property -dict [list CONFIG.ID {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
-
-set util_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_0_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_0_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_gt
-set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_0_gt
-
-set util_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_1_gt]
-set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_1_gt
-set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_gt
-set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_1_gt
-
-set axi_fmcadc5_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_fmcadc5_cpack]
-set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {256}] $axi_fmcadc5_cpack
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_fmcadc5_cpack
-
-# connections (gt)
-
-ad_connect  util_fmcadc5_0_gt/cpll_ref_clk rx_ref_clk_0
-ad_connect  util_fmcadc5_1_gt/cpll_ref_clk rx_ref_clk_1
-
-ad_connect  axi_fmcadc5_0_gt/gt_qpll_0 util_fmcadc5_0_gt/gt_qpll_0
-ad_connect  axi_fmcadc5_0_gt/gt_qpll_1 util_fmcadc5_0_gt/gt_qpll_1
-ad_connect  axi_fmcadc5_0_gt/gt_pll_0 util_fmcadc5_0_gt/gt_pll_0
-ad_connect  axi_fmcadc5_0_gt/gt_pll_1 util_fmcadc5_0_gt/gt_pll_1
-ad_connect  axi_fmcadc5_0_gt/gt_pll_2 util_fmcadc5_0_gt/gt_pll_2
-ad_connect  axi_fmcadc5_0_gt/gt_pll_3 util_fmcadc5_0_gt/gt_pll_3
-ad_connect  axi_fmcadc5_0_gt/gt_pll_4 util_fmcadc5_0_gt/gt_pll_4
-ad_connect  axi_fmcadc5_0_gt/gt_pll_5 util_fmcadc5_0_gt/gt_pll_5
-ad_connect  axi_fmcadc5_0_gt/gt_pll_6 util_fmcadc5_0_gt/gt_pll_6
-ad_connect  axi_fmcadc5_0_gt/gt_pll_7 util_fmcadc5_0_gt/gt_pll_7
-ad_connect  axi_fmcadc5_1_gt/gt_qpll_0 util_fmcadc5_1_gt/gt_qpll_0
-ad_connect  axi_fmcadc5_1_gt/gt_qpll_1 util_fmcadc5_1_gt/gt_qpll_1
-ad_connect  axi_fmcadc5_1_gt/gt_pll_0 util_fmcadc5_1_gt/gt_pll_0
-ad_connect  axi_fmcadc5_1_gt/gt_pll_1 util_fmcadc5_1_gt/gt_pll_1
-ad_connect  axi_fmcadc5_1_gt/gt_pll_2 util_fmcadc5_1_gt/gt_pll_2
-ad_connect  axi_fmcadc5_1_gt/gt_pll_3 util_fmcadc5_1_gt/gt_pll_3
-ad_connect  axi_fmcadc5_1_gt/gt_pll_4 util_fmcadc5_1_gt/gt_pll_4
-ad_connect  axi_fmcadc5_1_gt/gt_pll_5 util_fmcadc5_1_gt/gt_pll_5
-ad_connect  axi_fmcadc5_1_gt/gt_pll_6 util_fmcadc5_1_gt/gt_pll_6
-ad_connect  axi_fmcadc5_1_gt/gt_pll_7 util_fmcadc5_1_gt/gt_pll_7
-ad_connect  axi_fmcadc5_0_gt/gt_rx_0 util_fmcadc5_0_gt/gt_rx_0
-ad_connect  axi_fmcadc5_0_gt/gt_rx_1 util_fmcadc5_0_gt/gt_rx_1
-ad_connect  axi_fmcadc5_0_gt/gt_rx_2 util_fmcadc5_0_gt/gt_rx_2
-ad_connect  axi_fmcadc5_0_gt/gt_rx_3 util_fmcadc5_0_gt/gt_rx_3
-ad_connect  axi_fmcadc5_0_gt/gt_rx_4 util_fmcadc5_0_gt/gt_rx_4
-ad_connect  axi_fmcadc5_0_gt/gt_rx_5 util_fmcadc5_0_gt/gt_rx_5
-ad_connect  axi_fmcadc5_0_gt/gt_rx_6 util_fmcadc5_0_gt/gt_rx_6
-ad_connect  axi_fmcadc5_0_gt/gt_rx_7 util_fmcadc5_0_gt/gt_rx_7
-ad_connect  axi_fmcadc5_1_gt/gt_rx_0 util_fmcadc5_1_gt/gt_rx_0
-ad_connect  axi_fmcadc5_1_gt/gt_rx_1 util_fmcadc5_1_gt/gt_rx_1
-ad_connect  axi_fmcadc5_1_gt/gt_rx_2 util_fmcadc5_1_gt/gt_rx_2
-ad_connect  axi_fmcadc5_1_gt/gt_rx_3 util_fmcadc5_1_gt/gt_rx_3
-ad_connect  axi_fmcadc5_1_gt/gt_rx_4 util_fmcadc5_1_gt/gt_rx_4
-ad_connect  axi_fmcadc5_1_gt/gt_rx_5 util_fmcadc5_1_gt/gt_rx_5
-ad_connect  axi_fmcadc5_1_gt/gt_rx_6 util_fmcadc5_1_gt/gt_rx_6
-ad_connect  axi_fmcadc5_1_gt/gt_rx_7 util_fmcadc5_1_gt/gt_rx_7
-ad_connect  axi_fmcadc5_0_gt/gt_rx_ip_0 axi_ad9625_0_jesd/gt0_rx
-ad_connect  axi_fmcadc5_0_gt/gt_rx_ip_1 axi_ad9625_0_jesd/gt1_rx
-ad_connect  axi_fmcadc5_0_gt/gt_rx_ip_2 axi_ad9625_0_jesd/gt2_rx
-ad_connect  axi_fmcadc5_0_gt/gt_rx_ip_3 axi_ad9625_0_jesd/gt3_rx
-ad_connect  axi_fmcadc5_0_gt/gt_rx_ip_4 axi_ad9625_0_jesd/gt4_rx
-ad_connect  axi_fmcadc5_0_gt/gt_rx_ip_5 axi_ad9625_0_jesd/gt5_rx
-ad_connect  axi_fmcadc5_0_gt/gt_rx_ip_6 axi_ad9625_0_jesd/gt6_rx
-ad_connect  axi_fmcadc5_0_gt/gt_rx_ip_7 axi_ad9625_0_jesd/gt7_rx
-ad_connect  axi_fmcadc5_1_gt/gt_rx_ip_0 axi_ad9625_1_jesd/gt0_rx
-ad_connect  axi_fmcadc5_1_gt/gt_rx_ip_1 axi_ad9625_1_jesd/gt1_rx
-ad_connect  axi_fmcadc5_1_gt/gt_rx_ip_2 axi_ad9625_1_jesd/gt2_rx
-ad_connect  axi_fmcadc5_1_gt/gt_rx_ip_3 axi_ad9625_1_jesd/gt3_rx
-ad_connect  axi_fmcadc5_1_gt/gt_rx_ip_4 axi_ad9625_1_jesd/gt4_rx
-ad_connect  axi_fmcadc5_1_gt/gt_rx_ip_5 axi_ad9625_1_jesd/gt5_rx
-ad_connect  axi_fmcadc5_1_gt/gt_rx_ip_6 axi_ad9625_1_jesd/gt6_rx
-ad_connect  axi_fmcadc5_1_gt/gt_rx_ip_7 axi_ad9625_1_jesd/gt7_rx
-ad_connect  axi_fmcadc5_0_gt/rx_gt_comma_align_enb_0 axi_ad9625_0_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_0_gt/rx_gt_comma_align_enb_1 axi_ad9625_0_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_0_gt/rx_gt_comma_align_enb_2 axi_ad9625_0_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_0_gt/rx_gt_comma_align_enb_3 axi_ad9625_0_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_0_gt/rx_gt_comma_align_enb_4 axi_ad9625_0_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_0_gt/rx_gt_comma_align_enb_5 axi_ad9625_0_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_0_gt/rx_gt_comma_align_enb_6 axi_ad9625_0_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_0_gt/rx_gt_comma_align_enb_7 axi_ad9625_0_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_1_gt/rx_gt_comma_align_enb_0 axi_ad9625_1_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_1_gt/rx_gt_comma_align_enb_1 axi_ad9625_1_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_1_gt/rx_gt_comma_align_enb_2 axi_ad9625_1_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_1_gt/rx_gt_comma_align_enb_3 axi_ad9625_1_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_1_gt/rx_gt_comma_align_enb_4 axi_ad9625_1_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_1_gt/rx_gt_comma_align_enb_5 axi_ad9625_1_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_1_gt/rx_gt_comma_align_enb_6 axi_ad9625_1_jesd/rxencommaalign_out
-ad_connect  axi_fmcadc5_1_gt/rx_gt_comma_align_enb_7 axi_ad9625_1_jesd/rxencommaalign_out
+ad_xcvrpll  rx_ref_clk_0 util_fmcadc5_0_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_fmcadc5_0_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_cpll_rst_*
+ad_xcvrpll  rx_ref_clk_1 util_fmcadc5_1_xcvr/qpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_1 util_fmcadc5_1_xcvr/cpll_ref_clk_*
+ad_xcvrpll  axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_qpll_rst_*
+ad_xcvrpll  axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_cpll_rst_*
+ad_connect  sys_cpu_resetn util_fmcadc5_0_xcvr/up_rstn
+ad_connect  sys_cpu_resetn util_fmcadc5_1_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_fmcadc5_0_xcvr/up_clk
+ad_connect  sys_cpu_clk util_fmcadc5_1_xcvr/up_clk
 
 # connections (adc)
 
-ad_connect  util_fmcadc5_0_gt/rx_p rx_data_0_p
-ad_connect  util_fmcadc5_0_gt/rx_n rx_data_0_n
-ad_connect  util_fmcadc5_0_gt/rx_sysref GND
-ad_connect  util_fmcadc5_0_gt/rx_sync rx_sync_0
-ad_connect  util_fmcadc5_1_gt/rx_p rx_data_1_p
-ad_connect  util_fmcadc5_1_gt/rx_n rx_data_1_n
-ad_connect  util_fmcadc5_1_gt/rx_sysref GND
-ad_connect  util_fmcadc5_1_gt/rx_sync rx_sync_1
-ad_connect  util_fmcadc5_0_gt/rx_ip_sysref rx_sysref
-ad_connect  util_fmcadc5_0_gt/rx_out_clk rx_clk
-ad_connect  util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_0_gt/rx_clk
-ad_connect  util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_jesd/rx_core_clk
-ad_connect  util_fmcadc5_0_gt/rx_ip_rst axi_ad9625_0_jesd/rx_reset
-ad_connect  util_fmcadc5_0_gt/rx_ip_rst_done axi_ad9625_0_jesd/rx_reset_done
-ad_connect  util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_0_jesd/rx_sysref
-ad_connect  util_fmcadc5_0_gt/rx_ip_sync axi_ad9625_0_jesd/rx_sync
-ad_connect  util_fmcadc5_0_gt/rx_ip_sof axi_ad9625_0_jesd/rx_start_of_frame
-ad_connect  util_fmcadc5_0_gt/rx_ip_data axi_ad9625_0_jesd/rx_tdata
-ad_connect  util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_core/rx_clk
-ad_connect  util_fmcadc5_0_gt/rx_data axi_ad9625_0_core/rx_data
-ad_connect  util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_1_gt/rx_clk
-ad_connect  util_fmcadc5_0_gt/rx_out_clk axi_ad9625_1_jesd/rx_core_clk
-ad_connect  util_fmcadc5_1_gt/rx_ip_rst axi_ad9625_1_jesd/rx_reset
-ad_connect  util_fmcadc5_1_gt/rx_ip_rst_done axi_ad9625_1_jesd/rx_reset_done
-ad_connect  util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_1_jesd/rx_sysref
-ad_connect  util_fmcadc5_1_gt/rx_ip_sync axi_ad9625_1_jesd/rx_sync
-ad_connect  util_fmcadc5_1_gt/rx_ip_sof axi_ad9625_1_jesd/rx_start_of_frame
-ad_connect  util_fmcadc5_1_gt/rx_ip_data axi_ad9625_1_jesd/rx_tdata
-ad_connect  util_fmcadc5_0_gt/rx_out_clk axi_ad9625_1_core/rx_clk
-ad_connect  util_fmcadc5_1_gt/rx_data axi_ad9625_1_core/rx_data
-ad_connect  util_fmcadc5_0_gt/rx_out_clk axi_fmcadc5_cpack/adc_clk
-ad_connect  util_fmcadc5_0_gt/rx_rst axi_fmcadc5_cpack/adc_rst
+ad_xcvrcon  util_fmcadc5_0_xcvr axi_ad9625_0_xcvr axi_ad9625_0_jesd
+ad_xcvrcon  util_fmcadc5_1_xcvr axi_ad9625_1_xcvr axi_ad9625_1_jesd
+
+delete_bd_objs [get_bd_nets -of_objects [get_bd_pins util_fmcadc5_1_xcvr/rx_out_clk_0]]
+delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9625_1_jesd_rstgen/peripheral_reset]]
+delete_bd_objs [get_bd_cells axi_ad9625_1_jesd_rstgen]
+
+ad_xcvrpll  util_fmcadc5_0_xcvr/rx_out_clk_0 util_fmcadc5_1_xcvr/rx_clk_*
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_jesd/rx_core_clk
+ad_connect  axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_1_jesd/rx_reset
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_0_core/rx_clk
+ad_connect  axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_0_core/rx_sof
+ad_connect  axi_ad9625_0_jesd/rx_tdata axi_ad9625_0_core/rx_data
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_core/rx_clk
+ad_connect  axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_1_core/rx_sof
+ad_connect  axi_ad9625_1_jesd/rx_tdata axi_ad9625_1_core/rx_data
 ad_connect  axi_ad9625_0_core/adc_raddr_out axi_ad9625_0_core/adc_raddr_in
 ad_connect  axi_ad9625_0_core/adc_raddr_out axi_ad9625_1_core/adc_raddr_in
-ad_connect  axi_ad9625_0_core/adc_enable axi_fmcadc5_cpack/adc_enable_0
-ad_connect  axi_ad9625_0_core/adc_valid axi_fmcadc5_cpack/adc_valid_0
-ad_connect  axi_ad9625_0_core/adc_data axi_fmcadc5_cpack/adc_data_0
-ad_connect  axi_ad9625_1_core/adc_enable axi_fmcadc5_cpack/adc_enable_1
-ad_connect  axi_ad9625_1_core/adc_valid axi_fmcadc5_cpack/adc_valid_1
-ad_connect  axi_ad9625_1_core/adc_data axi_fmcadc5_cpack/adc_data_1
-ad_connect  util_fmcadc5_0_gt/rx_out_clk axi_ad9625_fifo/adc_clk
-ad_connect  util_fmcadc5_0_gt/rx_rst axi_ad9625_fifo/adc_rst
-ad_connect  axi_fmcadc5_cpack/adc_valid axi_ad9625_fifo/adc_wr
-ad_connect  axi_fmcadc5_cpack/adc_data axi_ad9625_fifo/adc_wdata
-ad_connect  axi_ad9625_0_core/adc_dovf axi_ad9625_fifo/adc_wovf
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 util_ad9625_cpack/adc_clk
+ad_connect  axi_ad9625_0_jesd_rstgen/peripheral_reset util_ad9625_cpack/adc_rst
+ad_connect  axi_ad9625_0_core/adc_enable util_ad9625_cpack/adc_enable_0
+ad_connect  axi_ad9625_0_core/adc_valid util_ad9625_cpack/adc_valid_0
+ad_connect  axi_ad9625_0_core/adc_data util_ad9625_cpack/adc_data_0
+ad_connect  axi_ad9625_1_core/adc_enable util_ad9625_cpack/adc_enable_1
+ad_connect  axi_ad9625_1_core/adc_valid util_ad9625_cpack/adc_valid_1
+ad_connect  axi_ad9625_1_core/adc_data util_ad9625_cpack/adc_data_1
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk
+ad_connect  axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
+ad_connect  util_ad9625_cpack/adc_valid axi_ad9625_fifo/adc_wr
+ad_connect  util_ad9625_cpack/adc_data axi_ad9625_fifo/adc_wdata
+ad_connect  axi_ad9625_fifo/adc_wovf axi_ad9625_0_core/adc_dovf
+ad_connect  axi_ad9625_fifo/adc_wovf axi_ad9625_1_core/adc_dovf
 ad_connect  sys_cpu_clk axi_ad9625_fifo/dma_clk
 ad_connect  sys_cpu_clk axi_ad9625_dma/s_axis_aclk
 ad_connect  sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
@@ -266,8 +125,8 @@ ad_connect  axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
 
 # interconnect (cpu)
 
-ad_cpu_interconnect 0x44a60000 axi_fmcadc5_0_gt
-ad_cpu_interconnect 0x44b60000 axi_fmcadc5_1_gt
+ad_cpu_interconnect 0x44a60000 axi_ad9625_0_xcvr
+ad_cpu_interconnect 0x44b60000 axi_ad9625_1_xcvr
 ad_cpu_interconnect 0x44a10000 axi_ad9625_0_core
 ad_cpu_interconnect 0x44b10000 axi_ad9625_1_core
 ad_cpu_interconnect 0x44a91000 axi_ad9625_0_jesd
@@ -276,21 +135,23 @@ ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
 
 # interconnect (gt/adc)
 
-ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_0_gt/m_axi
-ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_1_gt/m_axi
+ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_0_xcvr/m_axi
+ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_1_xcvr/m_axi
 ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
 
 # interrupts
 
-ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq
+ad_cpu_interrupt ps-12 mb-12 axi_ad9625_dma/irq
 
 # sync
 
+create_bd_port -dir O rx_clk
 create_bd_port -dir O up_clk
 create_bd_port -dir O up_rstn
 create_bd_port -dir O delay_clk
 create_bd_port -dir O delay_rst
 
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 rx_clk
 ad_connect  sys_cpu_clk up_clk
 ad_connect  sys_cpu_resetn up_rstn
 ad_connect  sys_200m_clk delay_clk
diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile
index fe14cf4c2..578fb5cca 100644
--- a/projects/fmcadc5/vc707/Makefile
+++ b/projects/fmcadc5/vc707/Makefile
@@ -22,11 +22,11 @@ M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
+M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
+M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -57,11 +57,11 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9625 clean
+	make -C ../../../library/xilinx/axi_adxcvr clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_jesd_gt clean
 	make -C ../../../library/util_adcfifo clean
+	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_jesd_gt clean
 	make -C ../../../library/util_mfifo clean
 
 
@@ -72,11 +72,11 @@ fmcadc5_vc707.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9625
+	make -C ../../../library/xilinx/axi_adxcvr
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_jesd_gt
 	make -C ../../../library/util_adcfifo
+	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_jesd_gt
 	make -C ../../../library/util_mfifo
 
 ####################################################################################
diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl
index 1a8b7ed36..282184189 100644
--- a/projects/fmcadc5/vc707/system_bd.tcl
+++ b/projects/fmcadc5/vc707/system_bd.tcl
@@ -18,13 +18,13 @@ set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc
 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
 set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
 
-ad_connect  util_fmcadc5_0_gt/rx_rst mfifo_adc/din_rst
-ad_connect  util_fmcadc5_0_gt/rx_out_clk mfifo_adc/din_clk
-ad_connect  axi_fmcadc5_cpack/adc_valid mfifo_adc/din_valid
-ad_connect  axi_fmcadc5_cpack/adc_data mfifo_adc/din_data_0
-ad_connect  util_fmcadc5_0_gt/rx_rst mfifo_adc/dout_rst
-ad_connect  util_fmcadc5_0_gt/rx_out_clk mfifo_adc/dout_clk
-ad_connect  util_fmcadc5_0_gt/rx_out_clk ila_adc/clk
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/din_clk
+ad_connect  axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/din_rst
+ad_connect  util_ad9625_cpack/adc_valid mfifo_adc/din_valid
+ad_connect  util_ad9625_cpack/adc_data mfifo_adc/din_data_0
+ad_connect  axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/dout_rst
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
+ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 ila_adc/clk
 ad_connect  mfifo_adc/dout_valid ila_adc/probe0
 ad_connect  mfifo_adc/dout_data_0 ila_adc/probe1
 
diff --git a/projects/fmcadc5/vc707/system_constr.xdc b/projects/fmcadc5/vc707/system_constr.xdc
index cb7e3c5e7..f87e54d99 100644
--- a/projects/fmcadc5/vc707/system_constr.xdc
+++ b/projects/fmcadc5/vc707/system_constr.xdc
@@ -84,6 +84,8 @@ set_property  -dict {PACKAGE_PIN  P40   IOSTANDARD LVCMOS18} [get_ports psync_1]
 
 create_clock -name rx_ref_clk_0   -period  1.60 [get_ports rx_ref_clk_0_p]
 create_clock -name rx_ref_clk_1   -period  1.60 [get_ports rx_ref_clk_1_p]
-create_clock -name rx_div_clk     -period  6.40 [get_pins i_system_wrapper/system_i/axi_fmcadc5_0_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_div_clk     -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcadc5_0_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
+set_false_path -from  [get_cells i_system_wrapper/system_i/axi_ad9625_0_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
+set_false_path -to    [get_cells rx_sysref_m1_reg]
 
diff --git a/projects/fmcadc5/vc707/system_project.tcl b/projects/fmcadc5/vc707/system_project.tcl
index f9297c0ed..a1436b06d 100644
--- a/projects/fmcadc5/vc707/system_project.tcl
+++ b/projects/fmcadc5/vc707/system_project.tcl
@@ -7,15 +7,13 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project_create fmcadc5_vc707
 adi_project_files fmcadc5_vc707 [list \
+  "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "../common/fmcadc5_spi.v" \
   "../common/fmcadc5_psync.v" \
-  "system_top.v" \
   "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
-  "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
-
-set_property is_enabled false [get_files  *axi_jesd_gt_tx_constr.xdc]
+  "system_top.v"]
 
 adi_project_run fmcadc5_vc707
 
diff --git a/projects/fmcadc5/vc707/system_top.v b/projects/fmcadc5/vc707/system_top.v
index 0173d9e80..2215146c4 100644
--- a/projects/fmcadc5/vc707/system_top.v
+++ b/projects/fmcadc5/vc707/system_top.v
@@ -34,207 +34,113 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
 module system_top (
 
-  sys_rst,
-  sys_clk_p,
-  sys_clk_n,
+  input             sys_rst,
+  input             sys_clk_p,
+  input             sys_clk_n,
 
-  uart_sin,
-  uart_sout,
+  input             uart_sin,
+  output            uart_sout,
 
-  ddr3_addr,
-  ddr3_ba,
-  ddr3_cas_n,
-  ddr3_ck_n,
-  ddr3_ck_p,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_dm,
-  ddr3_dq,
-  ddr3_dqs_n,
-  ddr3_dqs_p,
-  ddr3_odt,
-  ddr3_ras_n,
-  ddr3_reset_n,
-  ddr3_we_n,
+  output  [ 13:0]   ddr3_addr,
+  output  [  2:0]   ddr3_ba,
+  output            ddr3_cas_n,
+  output  [  0:0]   ddr3_ck_n,
+  output  [  0:0]   ddr3_ck_p,
+  output  [  0:0]   ddr3_cke,
+  output  [  0:0]   ddr3_cs_n,
+  output  [  7:0]   ddr3_dm,
+  inout   [ 63:0]   ddr3_dq,
+  inout   [  7:0]   ddr3_dqs_n,
+  inout   [  7:0]   ddr3_dqs_p,
+  output  [  0:0]   ddr3_odt,
+  output            ddr3_ras_n,
+  output            ddr3_reset_n,
+  output            ddr3_we_n,
 
-  sgmii_rxp,
-  sgmii_rxn,
-  sgmii_txp,
-  sgmii_txn,
+  input             sgmii_rxp,
+  input             sgmii_rxn,
+  output            sgmii_txp,
+  output            sgmii_txn,
 
-  phy_rstn,
-  mgt_clk_p,
-  mgt_clk_n,
-  mdio_mdc,
-  mdio_mdio,
+  output            phy_rstn,
+  input             mgt_clk_p,
+  input             mgt_clk_n,
+  output            mdio_mdc,
+  inout             mdio_mdio,
 
-  fan_pwm,
+  output            fan_pwm,
 
-  linear_flash_addr,
-  linear_flash_adv_ldn,
-  linear_flash_ce_n,
-  linear_flash_oen,
-  linear_flash_wen,
-  linear_flash_dq_io,
+  output  [26:1]    linear_flash_addr,
+  output            linear_flash_adv_ldn,
+  output            linear_flash_ce_n,
+  output            linear_flash_oen,
+  output            linear_flash_wen,
+  inout   [15:0]    linear_flash_dq_io,
 
-  gpio_lcd,
-  gpio_bd,
+  inout   [  6:0]   gpio_lcd,
+  inout   [ 20:0]   gpio_bd,
 
-  iic_rstn,
-  iic_scl,
-  iic_sda,
+  output            iic_rstn,
+  inout             iic_scl,
+  inout             iic_sda,
 
-  rx_ref_clk_0_p,
-  rx_ref_clk_0_n,
-  rx_data_0_p,
-  rx_data_0_n,
-  rx_ref_clk_1_p,
-  rx_ref_clk_1_n,
-  rx_data_1_p,
-  rx_data_1_n,
-  rx_sysref_p,
-  rx_sysref_n,
-  rx_sync_0_p,
-  rx_sync_0_n,
-  rx_sync_1_p,
-  rx_sync_1_n,
+  input             rx_ref_clk_0_p,
+  input             rx_ref_clk_0_n,
+  input   [  7:0]   rx_data_0_p,
+  input   [  7:0]   rx_data_0_n,
+  input             rx_ref_clk_1_p,
+  input             rx_ref_clk_1_n,
+  input   [  7:0]   rx_data_1_p,
+  input   [  7:0]   rx_data_1_n,
+  output            rx_sysref_p,
+  output            rx_sysref_n,
+  output            rx_sync_0_p,
+  output            rx_sync_0_n,
+  output            rx_sync_1_p,
+  output            rx_sync_1_n,
 
-  spi_csn_0,
-  spi_csn_1,
-  spi_clk,
-  spi_sdio,
-  spi_dirn,
+  output            spi_csn_0,
+  output            spi_csn_1,
+  output            spi_clk,
+  inout             spi_sdio,
+  output            spi_dirn,
+  output            dac_clk,
+  output            dac_data,
+  output            dac_sync_0,
+  output            dac_sync_1,
 
-  psync_0,
-  psync_1,
-  trig_p,
-  trig_n,
-  vdither_p,
-  vdither_n,
-  pwr_good,
-  dac_clk,
-  dac_data,
-  dac_sync_0,
-  dac_sync_1,
-  fd_1,
-  irq_1,
-  fd_0,
-  irq_0,
-  pwdn_1,
-  rst_1,
-  drst_1,
-  arst_1,
-  pwdn_0,
-  rst_0,
-  drst_0,
-  arst_0);
-
-  input             sys_rst;
-  input             sys_clk_p;
-  input             sys_clk_n;
-
-  input             uart_sin;
-  output            uart_sout;
-
-  output  [ 13:0]   ddr3_addr;
-  output  [  2:0]   ddr3_ba;
-  output            ddr3_cas_n;
-  output  [  0:0]   ddr3_ck_n;
-  output  [  0:0]   ddr3_ck_p;
-  output  [  0:0]   ddr3_cke;
-  output  [  0:0]   ddr3_cs_n;
-  output  [  7:0]   ddr3_dm;
-  inout   [ 63:0]   ddr3_dq;
-  inout   [  7:0]   ddr3_dqs_n;
-  inout   [  7:0]   ddr3_dqs_p;
-  output  [  0:0]   ddr3_odt;
-  output            ddr3_ras_n;
-  output            ddr3_reset_n;
-  output            ddr3_we_n;
-
-  input             sgmii_rxp;
-  input             sgmii_rxn;
-  output            sgmii_txp;
-  output            sgmii_txn;
-
-  output            phy_rstn;
-  input             mgt_clk_p;
-  input             mgt_clk_n;
-  output            mdio_mdc;
-  inout             mdio_mdio;
-
-  output            fan_pwm;
-
-  output  [26:1]    linear_flash_addr;
-  output            linear_flash_adv_ldn;
-  output            linear_flash_ce_n;
-  output            linear_flash_oen;
-  output            linear_flash_wen;
-  inout   [15:0]    linear_flash_dq_io;
-
-  inout   [  6:0]   gpio_lcd;
-  inout   [ 20:0]   gpio_bd;
-
-  output            iic_rstn;
-  inout             iic_scl;
-  inout             iic_sda;
-
-  input             rx_ref_clk_0_p;
-  input             rx_ref_clk_0_n;
-  input   [  7:0]   rx_data_0_p;
-  input   [  7:0]   rx_data_0_n;
-  input             rx_ref_clk_1_p;
-  input             rx_ref_clk_1_n;
-  input   [  7:0]   rx_data_1_p;
-  input   [  7:0]   rx_data_1_n;
-  output            rx_sysref_p;
-  output            rx_sysref_n;
-  output            rx_sync_0_p;
-  output            rx_sync_0_n;
-  output            rx_sync_1_p;
-  output            rx_sync_1_n;
-
-  output            spi_csn_0;
-  output            spi_csn_1;
-  output            spi_clk;
-  inout             spi_sdio;
-  output            spi_dirn;
-  output            dac_clk;
-  output            dac_data;
-  output            dac_sync_0;
-  output            dac_sync_1;
-
-  output            psync_0;
-  output            psync_1;
-  input             trig_p;
-  input             trig_n;
-  output            vdither_p;
-  output            vdither_n;
-  inout             pwr_good;
-  inout             fd_1;
-  inout             irq_1;
-  inout             fd_0;
-  inout             irq_0;
-  inout             pwdn_1;
-  inout             rst_1;
-  output            drst_1;
-  output            arst_1;
-  inout             pwdn_0;
-  inout             rst_0;
-  output            drst_0;
-  output            arst_0;
+  output            psync_0,
+  output            psync_1,
+  input             trig_p,
+  input             trig_n,
+  output            vdither_p,
+  output            vdither_n,
+  inout             pwr_good,
+  inout             fd_1,
+  inout             irq_1,
+  inout             fd_0,
+  inout             irq_0,
+  inout             pwdn_1,
+  inout             rst_1,
+  output            drst_1,
+  output            arst_1,
+  inout             pwdn_0,
+  inout             rst_0,
+  output            drst_0,
+  output            arst_0);
 
   // internal registers
 
   reg     [  4:0]   gpio_o_60_56_d = 'd0;
   reg               gpio_dld = 'd0;
+  reg               rx_sysref_m1 = 'd0;
+  reg               rx_sysref_m2 = 'd0;
+  reg               rx_sysref_int = 'd0;
 
   // internal signals
 
@@ -250,7 +156,6 @@ module system_top (
   wire              rx_clk;
   wire              rx_ref_clk_0;
   wire              rx_ref_clk_1;
-  wire              rx_sysref_s;
   wire              rx_sync_0;
   wire              rx_sync_1;
   wire              up_rstn;
@@ -287,6 +192,14 @@ module system_top (
     end
   end
 
+  // sysref internal
+
+  always @(posedge rx_clk) begin
+    rx_sysref_m1 <= gpio_o[32];
+    rx_sysref_m2 <= rx_sysref_m1;
+    rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
+  end
+
   // instantiations
 
   ad_lvds_out #(
@@ -297,8 +210,8 @@ module system_top (
     .IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"))
   i_rx_sysref (
     .tx_clk (rx_clk),
-    .tx_data_p (rx_sysref_s),
-    .tx_data_n (rx_sysref_s),
+    .tx_data_p (rx_sysref_int),
+    .tx_data_n (rx_sysref_int),
     .tx_data_out_p (rx_sysref_p),
     .tx_data_out_n (rx_sysref_n),
     .up_clk (up_clk),
@@ -424,15 +337,44 @@ module system_top (
     .phy_rstn (phy_rstn),
     .phy_sd (1'b1),
     .rx_clk (rx_clk),
-    .rx_data_0_n (rx_data_0_n),
-    .rx_data_0_p (rx_data_0_p),
-    .rx_data_1_n (rx_data_1_n),
-    .rx_data_1_p (rx_data_1_p),
+    .rx_data_0_n (rx_data_0_n[0]),
+    .rx_data_0_p (rx_data_0_p[0]),
+    .rx_data_1_0_n (rx_data_1_n[0]),
+    .rx_data_1_0_p (rx_data_1_p[0]),
+    .rx_data_1_1_n (rx_data_1_n[1]),
+    .rx_data_1_1_p (rx_data_1_p[1]),
+    .rx_data_1_2_n (rx_data_1_n[2]),
+    .rx_data_1_2_p (rx_data_1_p[2]),
+    .rx_data_1_3_n (rx_data_1_n[3]),
+    .rx_data_1_3_p (rx_data_1_p[3]),
+    .rx_data_1_4_n (rx_data_1_n[4]),
+    .rx_data_1_4_p (rx_data_1_p[4]),
+    .rx_data_1_5_n (rx_data_1_n[5]),
+    .rx_data_1_5_p (rx_data_1_p[5]),
+    .rx_data_1_6_n (rx_data_1_n[6]),
+    .rx_data_1_6_p (rx_data_1_p[6]),
+    .rx_data_1_7_n (rx_data_1_n[7]),
+    .rx_data_1_7_p (rx_data_1_p[7]),
+    .rx_data_1_n (rx_data_0_n[1]),
+    .rx_data_1_p (rx_data_0_p[1]),
+    .rx_data_2_n (rx_data_0_n[2]),
+    .rx_data_2_p (rx_data_0_p[2]),
+    .rx_data_3_n (rx_data_0_n[3]),
+    .rx_data_3_p (rx_data_0_p[3]),
+    .rx_data_4_n (rx_data_0_n[4]),
+    .rx_data_4_p (rx_data_0_p[4]),
+    .rx_data_5_n (rx_data_0_n[5]),
+    .rx_data_5_p (rx_data_0_p[5]),
+    .rx_data_6_n (rx_data_0_n[6]),
+    .rx_data_6_p (rx_data_0_p[6]),
+    .rx_data_7_n (rx_data_0_n[7]),
+    .rx_data_7_p (rx_data_0_p[7]),
     .rx_ref_clk_0 (rx_ref_clk_0),
     .rx_ref_clk_1 (rx_ref_clk_1),
     .rx_sync_0 (rx_sync_0),
-    .rx_sync_1 (rx_sync_1),
-    .rx_sysref (rx_sysref_s),
+    .rx_sync_1_0 (rx_sync_1),
+    .rx_sysref_0 (rx_sysref_int),
+    .rx_sysref_1_0 (rx_sysref_int),
     .sgmii_rxn (sgmii_rxn),
     .sgmii_rxp (sgmii_rxp),
     .sgmii_txn (sgmii_txn),

From c7056231018376563953950ce9bf2cf4788672b6 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 24 Nov 2016 12:01:45 +0200
Subject: [PATCH 753/972] axi_dmac: Fix port connection and port width mismatch

---
 library/axi_dmac/axi_dmac.v | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
index f5332bcfc..7d3753302 100644
--- a/library/axi_dmac/axi_dmac.v
+++ b/library/axi_dmac/axi_dmac.v
@@ -225,6 +225,14 @@ localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
   DMA_DATA_WIDTH_SRC > 32 ? 3 :
   DMA_DATA_WIDTH_SRC > 16 ? 2 :
   DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
+localparam ID_WIDTH = (FIFO_SIZE*2) > 1024 ? 8 :
+  (FIFO_SIZE*2) > 512 ? 7 :
+  (FIFO_SIZE*2) > 256 ? 6 :
+  (FIFO_SIZE*2) > 128 ? 5 :
+  (FIFO_SIZE*2) > 64 ? 4 :
+  (FIFO_SIZE*2) > 32 ? 3 :
+  (FIFO_SIZE*2) > 16 ? 2 :
+  (FIFO_SIZE*2) > 8 ? 1 : 0;
 
 // Register interface signals
 reg  [31:0]  up_rdata = 'd0;
@@ -273,14 +281,14 @@ reg up_dma_cyclic = CYCLIC;
 wire up_dma_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0;
 
 // ID signals from the DMAC, just for debugging
-wire [2:0] dest_request_id;
-wire [2:0] dest_data_id;
-wire [2:0] dest_address_id;
-wire [2:0] dest_response_id;
-wire [2:0] src_request_id;
-wire [2:0] src_data_id;
-wire [2:0] src_address_id;
-wire [2:0] src_response_id;
+wire [ID_WIDTH-1:0] dest_request_id;
+wire [ID_WIDTH-1:0] dest_data_id;
+wire [ID_WIDTH-1:0] dest_address_id;
+wire [ID_WIDTH-1:0] dest_response_id;
+wire [ID_WIDTH-1:0] src_request_id;
+wire [ID_WIDTH-1:0] src_data_id;
+wire [ID_WIDTH-1:0] src_address_id;
+wire [ID_WIDTH-1:0] src_response_id;
 wire [7:0] dbg_status;
 
 assign m_dest_axi_araddr = 'd0;
@@ -528,7 +536,8 @@ dmac_request_arb #(
   .AXI_SLICE_DEST(AXI_SLICE_DEST),
   .AXI_SLICE_SRC(AXI_SLICE_SRC),
   .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
-  .FIFO_SIZE(FIFO_SIZE)
+  .FIFO_SIZE(FIFO_SIZE),
+  .ID_WIDTH(ID_WIDTH)
 ) i_request_arb (
   .req_aclk(s_axi_aclk),
   .req_aresetn(s_axi_aresetn),

From f03675cdab21285d2451f5ce62d0c7c1774789db Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 24 Nov 2016 13:20:45 +0200
Subject: [PATCH 754/972] axi_dmac: ID_WIDTH must be clog2(FIFO_SIZE*2)

---
 library/axi_dmac/axi_dmac.v | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
index 7d3753302..3c1d34498 100644
--- a/library/axi_dmac/axi_dmac.v
+++ b/library/axi_dmac/axi_dmac.v
@@ -225,14 +225,13 @@ localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
   DMA_DATA_WIDTH_SRC > 32 ? 3 :
   DMA_DATA_WIDTH_SRC > 16 ? 2 :
   DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
-localparam ID_WIDTH = (FIFO_SIZE*2) > 1024 ? 8 :
-  (FIFO_SIZE*2) > 512 ? 7 :
-  (FIFO_SIZE*2) > 256 ? 6 :
-  (FIFO_SIZE*2) > 128 ? 5 :
-  (FIFO_SIZE*2) > 64 ? 4 :
-  (FIFO_SIZE*2) > 32 ? 3 :
-  (FIFO_SIZE*2) > 16 ? 2 :
-  (FIFO_SIZE*2) > 8 ? 1 : 0;
+localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :
+  (FIFO_SIZE) > 32 ? 7 :
+  (FIFO_SIZE) > 16 ? 6 :
+  (FIFO_SIZE) > 8 ? 5 :
+  (FIFO_SIZE) > 4 ? 4 :
+  (FIFO_SIZE) > 2 ? 3 :
+  (FIFO_SIZE) > 1 ? 2 : 1;
 
 // Register interface signals
 reg  [31:0]  up_rdata = 'd0;

From 91ee4394e496b7787fd758cc6aa668df0320bcb6 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 24 Nov 2016 15:19:36 +0200
Subject: [PATCH 755/972] axi_intr_monitor: Initial commit

---
 library/axi_intr_monitor/axi_intr_monitor.v   | 227 ++++++++++++++++++
 .../axi_intr_monitor/axi_intr_monitor_ip.tcl  |  17 ++
 2 files changed, 244 insertions(+)
 create mode 100644 library/axi_intr_monitor/axi_intr_monitor.v
 create mode 100644 library/axi_intr_monitor/axi_intr_monitor_ip.tcl

diff --git a/library/axi_intr_monitor/axi_intr_monitor.v b/library/axi_intr_monitor/axi_intr_monitor.v
new file mode 100644
index 000000000..c071fc588
--- /dev/null
+++ b/library/axi_intr_monitor/axi_intr_monitor.v
@@ -0,0 +1,227 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// IP used to monitor interrupt handling latency for a system.
+// Control register, bit 0 enables the core. If it's set to 0, the interrupt
+// won't be activated and all counters will be reset to 0
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_intr_monitor
+(
+  output          irq,
+
+// axi interface
+
+  input           s_axi_aclk,
+  input           s_axi_aresetn,
+  input           s_axi_awvalid,
+  input   [31:0]  s_axi_awaddr,
+  output          s_axi_awready,
+  input           s_axi_wvalid,
+  input   [31:0]  s_axi_wdata,
+  input   [3:0]   s_axi_wstrb,
+  output          s_axi_wready,
+  output          s_axi_bvalid,
+  output  [1:0]   s_axi_bresp,
+  input           s_axi_bready,
+  input           s_axi_arvalid,
+  input   [31:0]  s_axi_araddr,
+  output          s_axi_arready,
+  output          s_axi_rvalid,
+  output  [1:0]   s_axi_rresp,
+  output  [31:0]  s_axi_rdata,
+  input           s_axi_rready,
+  input   [ 2:0]  s_axi_awprot,
+  input   [ 2:0]  s_axi_arprot
+
+);
+
+parameter VERSION = 32'h00010000;
+
+//------------------------------------------------------------------------------
+//----------- Registers Declarations -------------------------------------------
+//------------------------------------------------------------------------------
+
+reg     [31:0]  up_rdata                    = 'd0;
+reg             up_wack                     = 'd0;
+reg             up_rack                     = 'd0;
+reg             pwm_gen_clk                 = 'd0;
+reg     [31:0]  scratch                     = 'd0;
+reg     [31:0]  control                     = 'd0;
+reg             interrupt                   = 'd0;
+reg     [31:0]  counter_to_interrupt        = 'd0;
+reg     [31:0]  counter_to_interrupt_cnt    = 'd0;
+reg     [31:0]  counter_from_interrupt      = 'd0;
+reg     [31:0]  counter_interrupt_handling  = 'd0;
+reg     [31:0]  min_interrupt_handling      = 'd0;
+reg     [31:0]  max_interrupt_handling      = 'd0;
+reg             interrupt_d1                = 'd0;
+
+//------------------------------------------------------------------------------
+//----------- Wires Declarations -----------------------------------------------
+//------------------------------------------------------------------------------
+
+wire            up_rreq_s;
+wire            up_wreq_s;
+wire    [13:0]  up_raddr_s;
+wire    [13:0]  up_waddr_s;
+wire    [31:0]  up_wdata_s;
+
+//------------------------------------------------------------------------------
+//----------- Assign/Always Blocks ---------------------------------------------
+//------------------------------------------------------------------------------
+
+assign irq = interrupt & control[0];
+
+always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
+  if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin
+    counter_to_interrupt_cnt <= 0;
+    counter_interrupt_handling <= 'd0;
+    counter_from_interrupt <= 32'h0;
+    min_interrupt_handling <= 'd0;
+    max_interrupt_handling <= 'd0;
+    interrupt_d1 <= 0;
+  end else begin
+    interrupt_d1 <= irq;
+    if (irq == 1'b1) begin
+      counter_to_interrupt_cnt <= counter_to_interrupt;
+    end else if (counter_to_interrupt_cnt > 0) begin
+      counter_to_interrupt_cnt <= counter_to_interrupt_cnt - 1;
+    end
+    if (irq == 1'b0 && interrupt_d1 == 1'b1) begin
+      counter_from_interrupt <= 32'h0;
+      counter_interrupt_handling <= counter_from_interrupt;
+      if (min_interrupt_handling > counter_from_interrupt) begin
+        min_interrupt_handling <= counter_from_interrupt;
+      end
+      if (max_interrupt_handling < counter_from_interrupt) begin
+        max_interrupt_handling <= counter_from_interrupt;
+      end
+    end else begin
+      counter_from_interrupt <= counter_from_interrupt + 1;
+    end
+  end
+end
+
+always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
+  if (s_axi_aresetn == 0) begin
+    up_wack                    <= 1'b0;
+    scratch                    <= 'd0;
+    control                    <= 'd0;
+    interrupt                  <= 'd0;
+    counter_to_interrupt       <= 'd0;
+  end else begin
+    up_wack  <= up_wreq_s;
+    if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h1)) begin
+      scratch <= up_wdata_s;
+    end
+    if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin
+      control <= up_wdata_s;
+    end
+    if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin
+      interrupt <= interrupt & ~up_wdata_s[0];
+    end else begin
+      if (counter_to_interrupt_cnt == 32'h0 && control[0] == 1'b1) begin
+        interrupt <= 1'b1;
+      end
+    end
+    if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h4)) begin
+      counter_to_interrupt <= up_wdata_s;
+    end
+  end
+end
+
+always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
+  if (s_axi_aresetn == 0) begin
+    up_rack <= 'd0;
+    up_rdata <= 'd0;
+  end else begin
+    up_rack <= up_rreq_s;
+    if (up_rreq_s == 1'b1) begin
+      case (up_raddr_s[3:0])
+        4'h0: up_rdata <= VERSION;
+        4'h1: up_rdata <= scratch;
+        4'h2: up_rdata <= control;
+        4'h3: up_rdata <= {31'h0,interrupt};
+        4'h4: up_rdata <= counter_to_interrupt;
+        4'h5: up_rdata <= counter_from_interrupt;
+        4'h6: up_rdata <= counter_interrupt_handling;
+        4'h7: up_rdata <= min_interrupt_handling;
+        4'h8: up_rdata <= max_interrupt_handling;
+        default: up_rdata <= 0;
+      endcase
+    end else begin
+      up_rdata <= 32'd0;
+    end
+  end
+end
+
+// up bus interface
+
+up_axi i_up_axi(
+  .up_rstn(s_axi_aresetn),
+  .up_clk(s_axi_aclk),
+  .up_axi_awvalid(s_axi_awvalid),
+  .up_axi_awaddr(s_axi_awaddr),
+  .up_axi_awready(s_axi_awready),
+  .up_axi_wvalid(s_axi_wvalid),
+  .up_axi_wdata(s_axi_wdata),
+  .up_axi_wstrb(s_axi_wstrb),
+  .up_axi_wready(s_axi_wready),
+  .up_axi_bvalid(s_axi_bvalid),
+  .up_axi_bresp(s_axi_bresp),
+  .up_axi_bready(s_axi_bready),
+  .up_axi_arvalid(s_axi_arvalid),
+  .up_axi_araddr(s_axi_araddr),
+  .up_axi_arready(s_axi_arready),
+  .up_axi_rvalid(s_axi_rvalid),
+  .up_axi_rresp(s_axi_rresp),
+  .up_axi_rdata(s_axi_rdata),
+  .up_axi_rready(s_axi_rready),
+  .up_wreq (up_wreq_s),
+  .up_waddr (up_waddr_s),
+  .up_wdata (up_wdata_s),
+  .up_wack (up_wack),
+  .up_rreq (up_rreq_s),
+  .up_raddr (up_raddr_s),
+  .up_rdata (up_rdata),
+  .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_intr_monitor/axi_intr_monitor_ip.tcl b/library/axi_intr_monitor/axi_intr_monitor_ip.tcl
new file mode 100644
index 000000000..6352801ed
--- /dev/null
+++ b/library/axi_intr_monitor/axi_intr_monitor_ip.tcl
@@ -0,0 +1,17 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_intr_monitor
+adi_ip_files axi_intr_monitor [list \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "axi_intr_monitor.v" ]
+
+adi_ip_properties axi_intr_monitor
+
+ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+
+

From 609b01f9e43ce9c51577d0cbad402e3259b7da52 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 24 Nov 2016 16:01:37 +0200
Subject: [PATCH 756/972] util_clkdiv: Added division by 2 option

---
 library/util_clkdiv/util_clkdiv.v      | 36 ++++++++++++++++++--------
 library/util_clkdiv/util_clkdiv_ip.tcl |  8 +++---
 2 files changed, 30 insertions(+), 14 deletions(-)

diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v
index a9b96a551..ee20fdb9f 100644
--- a/library/util_clkdiv/util_clkdiv.v
+++ b/library/util_clkdiv/util_clkdiv.v
@@ -34,30 +34,44 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
+// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1 using
+// BUFR and BUFGMUX primitives
 // ***************************************************************************
 // ***************************************************************************
 
 `timescale 1ns/100ps
 
 module util_clkdiv (
-  clk,
-  clk_out
+  input   clk,
+  input   clk_sel,
+  output  clk_out
  );
 
-  input   clk;
-  output  clk_out;
-  
+  wire clk_div_2_s;
+  wire clk_div_4_s;
+
   BUFR #(
-    .BUFR_DIVIDE("4"),
+    .BUFR_DIVIDE("2"),
     .SIM_DEVICE("7SERIES")
-  ) clk_divide (
+  ) clk_divide_2 (
     .I(clk),
     .CE(1),
     .CLR(0),
-    .O(clk_div_s));
-   
-  BUFG i_div_clk_gbuf (
-    .I (clk_div_s),
+    .O(clk_div_2_s));
+
+  BUFR #(
+    .BUFR_DIVIDE("4"),
+    .SIM_DEVICE("7SERIES")
+  ) clk_divide_4 (
+    .I(clk),
+    .CE(1),
+    .CLR(0),
+    .O(clk_div_4_s));
+
+  BUFGMUX i_div_clk_gbuf (
+    .I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
+    .I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
+    .S(clk_sel),
     .O (clk_out));
 
 endmodule  // util_clkdiv
diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl
index 66286de2a..701ca5c96 100644
--- a/library/util_clkdiv/util_clkdiv_ip.tcl
+++ b/library/util_clkdiv/util_clkdiv_ip.tcl
@@ -1,10 +1,12 @@
 source ../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip.tcl
- 
+
 adi_ip_create util_clkdiv
 adi_ip_files util_clkdiv [list \
 "util_clkdiv.v" ]
- 
+
 adi_ip_properties_lite util_clkdiv
- 
+
+set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]

From 45fd4f806d21cd7a7da30c4f966fba8e77361c8d Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 25 Nov 2016 16:33:58 +0200
Subject: [PATCH 757/972] fmcjesdadc1: Fixed RX_PMA_CFG parameter

---
 projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
index 8b94fbace..7c5152a23 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
@@ -60,6 +60,7 @@ set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr
 set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcjesdadc1_xcvr
 set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_fmcjesdadc1_xcvr
 set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcjesdadc1_xcvr
+set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_fmcjesdadc1_xcvr
 set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_fmcjesdadc1_xcvr
 
 # reference clocks & resets

From 284fbac571fcf11daa9f175a1795f8d982add576 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 28 Nov 2016 14:16:07 +0200
Subject: [PATCH 758/972] usdrx1: Xcvr updates, so that the channel parameters
 are correctly configured from boot time

---
 projects/usdrx1/common/usdrx1_bd.tcl     | 105 +++++++++--------
 projects/usdrx1/zc706/Makefile           |   1 +
 projects/usdrx1/zc706/system_project.tcl |   1 +
 projects/usdrx1/zc706/system_top.v       | 139 ++++++-----------------
 4 files changed, 86 insertions(+), 160 deletions(-)

diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl
index c6cdbd191..b2f3a2878 100644
--- a/projects/usdrx1/common/usdrx1_bd.tcl
+++ b/projects/usdrx1/common/usdrx1_bd.tcl
@@ -9,31 +9,6 @@ create_bd_port -dir I spi_sdo_i
 create_bd_port -dir O spi_sdo_o
 create_bd_port -dir I spi_sdi_i
 
-create_bd_port -dir O -from 255 -to 0 gt_rx_data
-create_bd_port -dir I -from 63 -to 0 gt_rx_data_0
-create_bd_port -dir I -from 63 -to 0 gt_rx_data_1
-create_bd_port -dir I -from 63 -to 0 gt_rx_data_2
-create_bd_port -dir I -from 63 -to 0 gt_rx_data_3
-create_bd_port -dir O -from 127 -to 0 adc_data_0
-create_bd_port -dir O -from 127 -to 0 adc_data_1
-create_bd_port -dir O -from 127 -to 0 adc_data_2
-create_bd_port -dir O -from 127 -to 0 adc_data_3
-create_bd_port -dir O -from 7 -to 0 adc_valid_0
-create_bd_port -dir O -from 7 -to 0 adc_valid_1
-create_bd_port -dir O -from 7 -to 0 adc_valid_2
-create_bd_port -dir O -from 7 -to 0 adc_valid_3
-create_bd_port -dir O -from 7 -to 0 adc_enable_0
-create_bd_port -dir O -from 7 -to 0 adc_enable_1
-create_bd_port -dir O -from 7 -to 0 adc_enable_2
-create_bd_port -dir O -from 7 -to 0 adc_enable_3
-create_bd_port -dir I adc_dovf_0
-create_bd_port -dir I adc_dovf_1
-create_bd_port -dir I adc_dovf_2
-create_bd_port -dir I adc_dovf_3
-create_bd_port -dir I -from 511 -to 0 adc_data
-create_bd_port -dir I adc_wr_en
-create_bd_port -dir O adc_dovf
-
 # adc peripherals
 
 set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0]
@@ -66,6 +41,12 @@ set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_usdrx1_xcvr
 set util_usdrx1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_usdrx1_xcvr]
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_usdrx1_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_usdrx1_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_usdrx1_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {3}] $util_usdrx1_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0954}] $util_usdrx1_xcvr
+set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_usdrx1_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023FF20400020}] $util_usdrx1_xcvr
+
 
 set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_usdrx1_dma
@@ -110,6 +91,16 @@ set_property -dict [list CONFIG.DIN_TO {192}] $data_slice_3
 set_property -dict [list CONFIG.DIN_FROM {255}] $data_slice_3
 set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_3
 
+set adc_data_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 adc_data_concat]
+set_property -dict [list CONFIG.NUM_PORTS {4}] $adc_data_concat
+
+set adc_valid_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 adc_valid_concat]
+set_property -dict [list CONFIG.NUM_PORTS {4}] $adc_valid_concat
+
+set adc_valid_reduced_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 adc_valid_reduced_or]
+set_property -dict [list CONFIG.C_SIZE {32}] $adc_valid_reduced_or
+set_property -dict [list CONFIG.C_OPERATION {or} ] $adc_valid_reduced_or
+
 # connections (spi)
 
 ad_connect  spi_csn_i   axi_usdrx1_spi/ss_i
@@ -121,8 +112,18 @@ ad_connect  spi_sdo_o   axi_usdrx1_spi/io0_o
 ad_connect  spi_sdi_i   axi_usdrx1_spi/io1_i
 ad_connect  sys_cpu_clk axi_usdrx1_spi/ext_spi_clk
 
+ad_connect  sys_cpu_resetn util_usdrx1_xcvr/up_rstn
+ad_connect  sys_cpu_clk util_usdrx1_xcvr/up_clk
+
 # connections (adc)
 
+create_bd_port -dir I rx_ref_clk_0
+
+ad_xcvrpll  rx_ref_clk_0 util_usdrx1_xcvr/cpll_ref_clk_*
+ad_xcvrpll  rx_ref_clk_0 util_usdrx1_xcvr/qpll_ref_clk_*
+ad_xcvrpll  axi_usdrx1_xcvr/up_pll_rst util_usdrx1_xcvr/up_cpll_rst_*
+ad_xcvrpll  axi_usdrx1_xcvr/up_pll_rst util_usdrx1_xcvr/up_qpll_rst_*
+
 ad_xcvrcon  util_usdrx1_xcvr axi_usdrx1_xcvr axi_usdrx1_jesd
 ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_0/rx_clk
 ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_1/rx_clk
@@ -144,24 +145,22 @@ ad_connect  data_slice_2/Dout axi_ad9671_core_2/rx_data
 ad_connect  data_slice_3/Dout axi_ad9671_core_3/rx_data
 
 ad_connect util_usdrx1_xcvr/rx_out_clk_0    usdrx1_fifo/adc_clk
-ad_connect adc_data_0                       axi_ad9671_core_0/adc_data
-ad_connect adc_data_1                       axi_ad9671_core_1/adc_data
-ad_connect adc_data_2                       axi_ad9671_core_2/adc_data
-ad_connect adc_data_3                       axi_ad9671_core_3/adc_data
-ad_connect adc_valid_0                      axi_ad9671_core_0/adc_valid
-ad_connect adc_valid_1                      axi_ad9671_core_1/adc_valid
-ad_connect adc_valid_2                      axi_ad9671_core_2/adc_valid
-ad_connect adc_valid_3                      axi_ad9671_core_3/adc_valid
-ad_connect adc_enable_0                     axi_ad9671_core_0/adc_enable
-ad_connect adc_enable_1                     axi_ad9671_core_1/adc_enable
-ad_connect adc_enable_2                     axi_ad9671_core_2/adc_enable
-ad_connect adc_enable_3                     axi_ad9671_core_3/adc_enable
-ad_connect adc_dovf_0                       axi_ad9671_core_0/adc_dovf
-ad_connect adc_dovf_1                       axi_ad9671_core_1/adc_dovf
-ad_connect adc_dovf_2                       axi_ad9671_core_2/adc_dovf
-ad_connect adc_dovf_3                       axi_ad9671_core_3/adc_dovf
-ad_connect adc_wr_en                        usdrx1_fifo/adc_wr
-ad_connect adc_data                         usdrx1_fifo/adc_wdata
+ad_connect adc_data_concat/In0 axi_ad9671_core_0/adc_data
+ad_connect adc_data_concat/In1 axi_ad9671_core_1/adc_data
+ad_connect adc_data_concat/In2 axi_ad9671_core_2/adc_data
+ad_connect adc_data_concat/In3 axi_ad9671_core_3/adc_data
+ad_connect adc_valid_concat/In0 axi_ad9671_core_0/adc_valid
+ad_connect adc_valid_concat/In1 axi_ad9671_core_1/adc_valid
+ad_connect adc_valid_concat/In2 axi_ad9671_core_2/adc_valid
+ad_connect adc_valid_concat/In3 axi_ad9671_core_3/adc_valid
+ad_connect adc_valid_concat/dout adc_valid_reduced_or/Op1
+
+ad_connect usdrx1_fifo/adc_wovf             axi_ad9671_core_0/adc_dovf
+ad_connect usdrx1_fifo/adc_wovf             axi_ad9671_core_1/adc_dovf
+ad_connect usdrx1_fifo/adc_wovf             axi_ad9671_core_2/adc_dovf
+ad_connect usdrx1_fifo/adc_wovf             axi_ad9671_core_3/adc_dovf
+ad_connect adc_valid_reduced_or/Res         usdrx1_fifo/adc_wr
+ad_connect adc_data_concat/dout             usdrx1_fifo/adc_wdata
 ad_connect axi_ad9671_adc_raddr             axi_ad9671_core_0/adc_raddr_out
 ad_connect axi_ad9671_adc_raddr             axi_ad9671_core_1/adc_raddr_in
 ad_connect axi_ad9671_adc_raddr             axi_ad9671_core_2/adc_raddr_in
@@ -173,8 +172,6 @@ ad_connect axi_ad9671_adc_sync              axi_ad9671_core_3/adc_sync_in
 
 ad_connect axi_usdrx1_jesd_rstgen/peripheral_reset   usdrx1_fifo/adc_rst
 
-ad_connect adc_dovf                         usdrx1_fifo/adc_wovf
-
 ad_connect usdrx1_fifo/dma_wdata            axi_usdrx1_dma/s_axis_data
 ad_connect usdrx1_fifo/dma_wr               axi_usdrx1_dma/s_axis_valid
 ad_connect usdrx1_fifo/dma_wready           axi_usdrx1_dma/s_axis_ready
@@ -223,12 +220,12 @@ set_property -dict [list CONFIG.C_PROBE8_WIDTH {1}] $ila_ad9671
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_ad9671
 
 ad_connect axi_ad9671_core_0/adc_clk  ila_ad9671/CLK
-ad_connect adc_data_0                 ila_ad9671/PROBE0
-ad_connect adc_valid_0                ila_ad9671/PROBE1
-ad_connect adc_data_1                 ila_ad9671/PROBE2
-ad_connect adc_valid_1                ila_ad9671/PROBE3
-ad_connect adc_data_2                 ila_ad9671/PROBE4
-ad_connect adc_valid_2                ila_ad9671/PROBE5
-ad_connect adc_data_3                 ila_ad9671/PROBE6
-ad_connect adc_valid_3                ila_ad9671/PROBE7
-ad_connect adc_dovf_0                 ila_ad9671/PROBE8
+ad_connect axi_ad9671_core_0/adc_data   ila_ad9671/PROBE0
+ad_connect axi_ad9671_core_0/adc_valid  ila_ad9671/PROBE1
+ad_connect axi_ad9671_core_1/adc_data   ila_ad9671/PROBE2
+ad_connect axi_ad9671_core_1/adc_valid  ila_ad9671/PROBE3
+ad_connect axi_ad9671_core_2/adc_data   ila_ad9671/PROBE4
+ad_connect axi_ad9671_core_2/adc_valid  ila_ad9671/PROBE5
+ad_connect axi_ad9671_core_3/adc_data   ila_ad9671/PROBE6
+ad_connect axi_ad9671_core_3/adc_valid  ila_ad9671/PROBE7
+ad_connect usdrx1_fifo/adc_wovf         ila_ad9671/PROBE8
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index e1acdb44d..e4d7d74f1 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -19,6 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
diff --git a/projects/usdrx1/zc706/system_project.tcl b/projects/usdrx1/zc706/system_project.tcl
index e022ae874..df7245873 100644
--- a/projects/usdrx1/zc706/system_project.tcl
+++ b/projects/usdrx1/zc706/system_project.tcl
@@ -10,6 +10,7 @@ adi_project_files usdrx1_zc706 [list \
   "system_top.v" \
   "system_constr.xdc" \
   "../common/usdrx1_spi.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v
index 082184c74..334a2ea83 100644
--- a/projects/usdrx1/zc706/system_top.v
+++ b/projects/usdrx1/zc706/system_top.v
@@ -246,25 +246,6 @@ module system_top (
   wire            rx_ref_clk;
   wire            rx_sysref;
   wire            rx_sync;
-  wire   [511:0]  adc_data;
-  wire   [127:0]  adc_data_0;
-  wire   [127:0]  adc_data_1;
-  wire   [127:0]  adc_data_2;
-  wire   [127:0]  adc_data_3;
-  wire            adc_valid;
-  wire   [  7:0]  adc_valid_0;
-  wire   [  7:0]  adc_valid_1;
-  wire   [  7:0]  adc_valid_2;
-  wire   [  7:0]  adc_valid_3;
-  wire   [  7:0]  adc_enable_0;
-  wire   [  7:0]  adc_enable_1;
-  wire   [  7:0]  adc_enable_2;
-  wire   [  7:0]  adc_enable_3;
-  wire            adc_dovf;
-  wire            adc_dovf_0;
-  wire            adc_dovf_1;
-  wire            adc_dovf_2;
-  wire            adc_dovf_3;
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
@@ -285,33 +266,12 @@ module system_top (
   assign spi_afe_clk          = spi_clk;
   assign spi_clk_clk          = spi_clk;
 
-  usdrx1_spi i_spi (
-    .spi_afe_csn (spi_csn[4:1]),
-    .spi_clk_csn (spi_csn[0]),
-    .spi_clk (spi_clk),
-    .spi_mosi (spi_mosi),
-    .spi_miso (spi_miso),
-    .spi_afe_sdio (spi_afe_sdio),
-    .spi_clk_sdio (spi_clk_sdio));
-
-  // single dma for all channels
-
-  assign adc_data   = {adc_data_3, adc_data_2, adc_data_1, adc_data_0};
-  assign adc_valid  = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ;
-  assign adc_dovf_0 = adc_dovf;
-  assign adc_dovf_1 = adc_dovf;
-  assign adc_dovf_2 = adc_dovf;
-  assign adc_dovf_3 = adc_dovf;
-
-  // data interface
-
   IBUFDS_GTE2 i_ibufds_rx_ref_clk (
     .CEB (1'd0),
     .I (rx_ref_clk_p),
     .IB (rx_ref_clk_n),
     .O (rx_ref_clk),
     .ODIV2 ());
-
   OBUFDS i_obufds_rx_sysref (
     .I (rx_sysref),
     .O (rx_sysref_p),
@@ -322,40 +282,6 @@ module system_top (
     .O (rx_sync_p),
     .OB (rx_sync_n));
 
-  // gpio/control interface
-
-  IOBUF i_iobuf_gpio_prc_sdo_q  (
-    .I (gpio_o[43]),
-    .O (gpio_i[43]),
-    .T (gpio_t[43]),
-    .IO (prc_sdo_q));
-
-  IOBUF i_iobuf_gpio_prc_sdo_i  (
-    .I (gpio_o[42]),
-    .O (gpio_i[42]),
-    .T (gpio_t[42]),
-    .IO (prc_sdo_i));
-
-  IOBUF i_iobuf_gpio_prc_cnv    (
-    .I (gpio_o[41]),
-    .O (gpio_i[41]),
-    .T (gpio_t[41]),
-    .IO (prc_cnv));
-
-  IOBUF i_iobuf_gpio_prc_sck    (
-    .I (gpio_o[40]),
-    .O (gpio_i[40]),
-    .T (gpio_t[40]),
-    .IO (prc_sck));
-
-  assign dac_sleep  = gpio_o[44];
-  assign amp_disbn  = gpio_o[39];
-  assign gpio_i[38] = clk_status;
-  assign clk_syncn  = gpio_o[37];
-  assign clk_resetn = gpio_o[36];
-  assign afe_stby   = gpio_o[35];
-  assign afe_pdn    = gpio_o[34];
-
   OBUFDS i_obufds_gpio_afe_trig (
     .I (gpio_o[33]),
     .O (afe_trig_p),
@@ -366,19 +292,39 @@ module system_top (
     .O (afe_rst_p),
     .OB (afe_rst_n));
 
-  genvar n;
-  generate
-  for (n = 0; n <= 13; n = n + 1) begin: g_iobuf_gpio_dac_data
-    assign dac_data[n]   = gpio_o[45+n];
-  end
-  for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
-  IOBUF i_iobuf_gpio_bd (
-    .I (gpio_o[n]),
-    .O (gpio_i[n]),
-    .T (gpio_t[n]),
-    .IO (gpio_bd[n]));
-  end
-  endgenerate
+  assign dac_sleep  = gpio_o[44];
+  assign amp_disbn  = gpio_o[39];
+  assign gpio_i[38] = clk_status;
+  assign clk_syncn  = gpio_o[37];
+  assign clk_resetn = gpio_o[36];
+  assign afe_stby   = gpio_o[35];
+  assign afe_pdn    = gpio_o[34];
+
+  assign dac_data   = gpio_o[59:45];
+
+  ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_prc (
+    .dio_t (gpio_t[43:40]),
+    .dio_i (gpio_o[43:40]),
+    .dio_o (gpio_i[43:40]),
+    .dio_p ({prc_sdo_q,
+            prc_sdo_i,
+            prc_cnv,
+            prc_sck}));
+
+  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
+    .dio_t (gpio_t[14:0]),
+    .dio_i (gpio_o[14:0]),
+    .dio_o (gpio_i[14:0]),
+    .dio_p (gpio_bd));
+
+  usdrx1_spi i_spi (
+    .spi_afe_csn (spi_csn[4:1]),
+    .spi_clk_csn (spi_csn[0]),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_afe_sdio (spi_afe_sdio),
+    .spi_clk_sdio (spi_clk_sdio));
 
   system_wrapper i_system_wrapper (
     .sys_clk_clk_n (sys_clk_n),
@@ -423,25 +369,6 @@ module system_top (
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),
-    .adc_data (adc_data),
-    .adc_data_0 (adc_data_0),
-    .adc_data_1 (adc_data_1),
-    .adc_data_2 (adc_data_2),
-    .adc_data_3 (adc_data_3),
-    .adc_wr_en(adc_valid),
-    .adc_valid_0 (adc_valid_0),
-    .adc_valid_1 (adc_valid_1),
-    .adc_valid_2 (adc_valid_2),
-    .adc_valid_3 (adc_valid_3),
-    .adc_enable_0 (adc_enable_0),
-    .adc_enable_1 (adc_enable_1),
-    .adc_enable_2 (adc_enable_2),
-    .adc_enable_3 (adc_enable_3),
-    .adc_dovf (adc_dovf),
-    .adc_dovf_0 (adc_dovf_0),
-    .adc_dovf_1 (adc_dovf_1),
-    .adc_dovf_2 (adc_dovf_2),
-    .adc_dovf_3 (adc_dovf_3),
     .hdmi_data (hdmi_data),
     .hdmi_data_e (hdmi_data_e),
     .hdmi_hsync (hdmi_hsync),

From 07217740b56160be297b97cfd2e06955aa1be090 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Tue, 29 Nov 2016 13:11:35 +0100
Subject: [PATCH 759/972] imageon: Increase HDMI RX clock constraint

The ADV7611 is rated for a maximum clock rate of 165MHz. Increase the clock rate constraint to match this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/imageon/zc706/system_constr.xdc | 2 +-
 projects/imageon/zed/system_constr.xdc   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/imageon/zc706/system_constr.xdc b/projects/imageon/zc706/system_constr.xdc
index 9d024d35d..9b1b1257d 100644
--- a/projects/imageon/zc706/system_constr.xdc
+++ b/projects/imageon/zc706/system_constr.xdc
@@ -50,7 +50,7 @@ set_property  -dict {PACKAGE_PIN   AG15   IOSTANDARD LVCMOS25}    [get_ports  hd
 
 # clock definition
 
-create_clock -period 6.667  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
+create_clock -period 6.000  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
 
 # default constraints
 
diff --git a/projects/imageon/zed/system_constr.xdc b/projects/imageon/zed/system_constr.xdc
index 220b0da90..f483e514e 100644
--- a/projects/imageon/zed/system_constr.xdc
+++ b/projects/imageon/zed/system_constr.xdc
@@ -50,7 +50,7 @@ set_property  -dict {PACKAGE_PIN   N20    IOSTANDARD LVCMOS25}    [get_ports  hd
 
 # clock definition
 
-create_clock -period 6.667  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
+create_clock -period 6.000  -name hdmi_rx_clk  [get_ports hdmi_rx_clk]
 
 # i2s
 

From 99dae73d96aa0f62112a1d20e8f642e8b41289d3 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Tue, 29 Nov 2016 13:15:15 +0100
Subject: [PATCH 760/972] imageon: Connect hdmi_rx_core output clock to DMA

Connect the HDMI RX core output clock to the DMA rather than connecting the
HDMI RX input clock directly. This will allow the HDMI RX core to modify
the clock and e.g. insert clock buffers or similar.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/imageon/common/imageon_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl
index 8de628c5b..b0d73f449 100644
--- a/projects/imageon/common/imageon_bd.tcl
+++ b/projects/imageon/common/imageon_bd.tcl
@@ -43,7 +43,7 @@ create_bd_port -dir I -from 15 -to 0 hdmi_rx_data
 ad_connect  hdmi_rx_clk axi_hdmi_rx_core/hdmi_rx_clk
 ad_connect  hdmi_rx_data axi_hdmi_rx_core/hdmi_rx_data
 
-ad_connect  hdmi_rx_clk axi_hdmi_rx_dma/fifo_wr_clk
+ad_connect  axi_hdmi_rx_core/hdmi_clk axi_hdmi_rx_dma/fifo_wr_clk
 ad_connect  axi_hdmi_rx_core/hdmi_dma_sof axi_hdmi_rx_dma/fifo_wr_sync
 ad_connect  axi_hdmi_rx_core/hdmi_dma_de axi_hdmi_rx_dma/fifo_wr_en
 ad_connect  axi_hdmi_rx_core/hdmi_dma_data axi_hdmi_rx_dma/fifo_wr_din

From 24cc8d284b57e83fa6f866431c750aa79406e3b2 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Tue, 29 Nov 2016 14:10:59 +0100
Subject: [PATCH 761/972] imageon: Increase RX DMA FIFO size

Increase the RX DMA FIFO to be able to better compensate for momentarily
memory bus contention. This has shown to resolve occasional overflows that
would occur under high system memory load.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/imageon/common/imageon_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl
index b0d73f449..033ea609f 100644
--- a/projects/imageon/common/imageon_bd.tcl
+++ b/projects/imageon/common/imageon_bd.tcl
@@ -36,6 +36,7 @@ set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_hdmi_rx_dma
+set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_hdmi_rx_dma
 
 create_bd_port -dir I hdmi_rx_clk
 create_bd_port -dir I -from 15 -to 0 hdmi_rx_data

From 84a76b9deac363ac5f248801c10df6b9d9cb6c60 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Tue, 29 Nov 2016 15:43:04 +0100
Subject: [PATCH 762/972] imageon: Invert HDMI TX clock

The ADV7511 samples the parallel data bus at the rising edge of sample
clock. Generate the clock so that the falling edge is aligned to updating
the bus data. This creates larger timing margins on each side of the
sampling edge and makes the design more robust.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/imageon/common/imageon_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl
index 033ea609f..4c0caa36c 100644
--- a/projects/imageon/common/imageon_bd.tcl
+++ b/projects/imageon/common/imageon_bd.tcl
@@ -14,6 +14,7 @@ delete_bd_objs [get_bd_ports hdmi_data_e]
 delete_bd_objs [get_bd_ports hdmi_data]
 
 set_property CONFIG.EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core]
+set_property CONFIG.OUT_CLK_POLARITY {1} [get_bd_cells axi_hdmi_core]
 
 create_bd_port -dir O hdmi_tx_clk
 create_bd_port -dir O -from 15 -to 0 hdmi_tx_data

From 0faa1ebff2ed0d0596ab297e9a3ae453ab2be759 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 30 Nov 2016 17:38:04 +0200
Subject: [PATCH 763/972] pzsdr1: ccusb_lvds, add flag_a,flag_b signals

---
 projects/pzsdr1/ccusb_lvds/system_top.v | 3 +++
 projects/pzsdr1/common/ccusb_constr.xdc | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/projects/pzsdr1/ccusb_lvds/system_top.v b/projects/pzsdr1/ccusb_lvds/system_top.v
index 7b136adf6..426658da6 100644
--- a/projects/pzsdr1/ccusb_lvds/system_top.v
+++ b/projects/pzsdr1/ccusb_lvds/system_top.v
@@ -104,6 +104,9 @@ module system_top (
   output          pktend_n,
   output          epswitch_n,
 
+  input           flag_a,
+  input           flag_b,
+
   output          reset_n,
 
   output  [ 2:0]  pmode,
diff --git a/projects/pzsdr1/common/ccusb_constr.xdc b/projects/pzsdr1/common/ccusb_constr.xdc
index de25d854d..fb06ba3ec 100644
--- a/projects/pzsdr1/common/ccusb_constr.xdc
+++ b/projects/pzsdr1/common/ccusb_constr.xdc
@@ -63,6 +63,10 @@ set_property  -dict {PACKAGE_PIN  W15   IOSTANDARD LVCMOS25} [get_ports fifo_rdy
 set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD LVCMOS25} [get_ports fifo_rdy[6]]      ;
 set_property  -dict {PACKAGE_PIN  P20   IOSTANDARD LVCMOS25} [get_ports fifo_rdy[7]]      ;
 
+set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD LVCMOS25} [get_ports flag_a]      ;
+set_property  -dict {PACKAGE_PIN  W9    IOSTANDARD LVCMOS25} [get_ports flag_b]      ;
+
+
 set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports pmode[0]]         ;
 set_property  -dict {PACKAGE_PIN  T19   IOSTANDARD LVCMOS25} [get_ports pmode[1]]         ;
 set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD LVCMOS25} [get_ports pmode[2]]         ;

From 6e89ac3d657b02a756e2ef8fba8c3ede6eba942d Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 30 Nov 2016 17:39:02 +0200
Subject: [PATCH 764/972] pzsdr2: ccusb_lvds, add flag_a,flag_b signals

---
 projects/pzsdr2/ccusb_lvds/system_top.v |  3 +++
 projects/pzsdr2/common/ccusb_constr.xdc | 13 ++++++++-----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/projects/pzsdr2/ccusb_lvds/system_top.v b/projects/pzsdr2/ccusb_lvds/system_top.v
index 7b136adf6..426658da6 100644
--- a/projects/pzsdr2/ccusb_lvds/system_top.v
+++ b/projects/pzsdr2/ccusb_lvds/system_top.v
@@ -104,6 +104,9 @@ module system_top (
   output          pktend_n,
   output          epswitch_n,
 
+  input           flag_a,
+  input           flag_b,
+
   output          reset_n,
 
   output  [ 2:0]  pmode,
diff --git a/projects/pzsdr2/common/ccusb_constr.xdc b/projects/pzsdr2/common/ccusb_constr.xdc
index a0ea05764..3c7d6bdcd 100644
--- a/projects/pzsdr2/common/ccusb_constr.xdc
+++ b/projects/pzsdr2/common/ccusb_constr.xdc
@@ -63,9 +63,12 @@ set_property  -dict {PACKAGE_PIN  D5    IOSTANDARD LVCMOS18} [get_ports fifo_rdy
 set_property  -dict {PACKAGE_PIN  F7    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[6]]      ;
 set_property  -dict {PACKAGE_PIN  C6    IOSTANDARD LVCMOS18} [get_ports fifo_rdy[7]]      ;
 
-set_property  -dict {PACKAGE_PIN  A10    IOSTANDARD LVCMOS18} [get_ports pmode[0]]        ;
-set_property  -dict {PACKAGE_PIN  K10    IOSTANDARD LVCMOS18} [get_ports pmode[1]]        ;
-set_property  -dict {PACKAGE_PIN  B4     IOSTANDARD LVCMOS18} [get_ports pmode[2]]        ;
+set_property  -dict {PACKAGE_PIN  AE20  IOSTANDARD LVCMOS18} [get_ports flag_a]      ;
+set_property  -dict {PACKAGE_PIN  AE21  IOSTANDARD LVCMOS18} [get_ports flag_b]      ;
 
-set_property  -dict {PACKAGE_PIN  AC23   IOSTANDARD LVCMOS18} [get_ports reset_n]         ;
-set_property  -dict {PACKAGE_PIN  AD18   IOSTANDARD LVCMOS18} [get_ports epswitch_n]      ;
+set_property  -dict {PACKAGE_PIN  A10   IOSTANDARD LVCMOS18} [get_ports pmode[0]]        ;
+set_property  -dict {PACKAGE_PIN  K10   IOSTANDARD LVCMOS18} [get_ports pmode[1]]        ;
+set_property  -dict {PACKAGE_PIN  B4    IOSTANDARD LVCMOS18} [get_ports pmode[2]]        ;
+
+set_property  -dict {PACKAGE_PIN  AC23  IOSTANDARD LVCMOS18} [get_ports reset_n]         ;
+set_property  -dict {PACKAGE_PIN  AD18  IOSTANDARD LVCMOS18} [get_ports epswitch_n]      ;

From 95a2e02800381de8a43e2121f8e5ed292143017a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 1 Dec 2016 13:47:02 -0500
Subject: [PATCH 765/972] library/makefile- updates

---
 library/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/Makefile b/library/Makefile
index 775c86da1..56f1feac7 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -37,7 +37,7 @@ clean:
 	make -C axi_hdmi_rx clean
 	make -C axi_hdmi_tx clean
 	make -C axi_i2s_adi clean
-	make -C axi_jesd_gt clean
+	make -C axi_intr_monitor clean
 	make -C axi_mc_controller clean
 	make -C axi_mc_current_monitor clean
 	make -C axi_mc_speed clean
@@ -112,7 +112,7 @@ lib:
 	-make -C axi_hdmi_rx
 	-make -C axi_hdmi_tx
 	-make -C axi_i2s_adi
-	-make -C axi_jesd_gt
+	-make -C axi_intr_monitor
 	-make -C axi_mc_controller
 	-make -C axi_mc_current_monitor
 	-make -C axi_mc_speed

From 170c781d021f087b40c6529412dd3e49f50f08ff Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 1 Dec 2016 13:52:11 -0500
Subject: [PATCH 766/972] hdlmake.pl- updates

---
 library/axi_intr_monitor/Makefile   | 47 +++++++++++++++++
 projects/Makefile                   | 12 ++---
 projects/daq3/zc706/Makefile        |  3 --
 projects/fmcadc2/vc707/Makefile     |  3 --
 projects/fmcadc2/zc706/Makefile     |  3 --
 projects/fmcadc4/zc706/Makefile     |  3 --
 projects/fmcomms2/Makefile          |  3 ++
 projects/fmcomms2/zc706pr/Makefile  | 12 +++--
 projects/pzsdr1/ccbox_lvds/Makefile |  2 +-
 projects/pzsdr1/ccusb_lvds/Makefile | 79 +++++++++++++++++++++++++++++
 projects/usdrx1/a5gt/Makefile       |  1 -
 11 files changed, 143 insertions(+), 25 deletions(-)
 create mode 100644 library/axi_intr_monitor/Makefile
 create mode 100644 projects/pzsdr1/ccusb_lvds/Makefile

diff --git a/library/axi_intr_monitor/Makefile b/library/axi_intr_monitor/Makefile
new file mode 100644
index 000000000..058630d0e
--- /dev/null
+++ b/library/axi_intr_monitor/Makefile
@@ -0,0 +1,47 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := axi_intr_monitor_ip.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../common/up_axi.v
+M_DEPS += axi_intr_monitor.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_intr_monitor.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_intr_monitor.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_intr_monitor_ip.tcl  >> axi_intr_monitor_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/projects/Makefile b/projects/Makefile
index d4ea0ef46..c4d8c5cb7 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -36,9 +36,9 @@ all:
 	-make -C fmcomms7 all
 	-make -C imageon all
 	-make -C motcon2_fmc all
-	-make -C pzsdr all
+	-make -C pluto all
 	-make -C pzsdr1 all
-	-make -C sdrstk all
+	-make -C pzsdr2 all
 	-make -C usb_fx3 all
 	-make -C usdrx1 all
 	-make -C usrpe31x all
@@ -74,9 +74,9 @@ clean:
 	make -C fmcomms7 clean
 	make -C imageon clean
 	make -C motcon2_fmc clean
-	make -C pzsdr clean
+	make -C pluto clean
 	make -C pzsdr1 clean
-	make -C sdrstk clean
+	make -C pzsdr2 clean
 	make -C usb_fx3 clean
 	make -C usdrx1 clean
 	make -C usrpe31x clean
@@ -112,9 +112,9 @@ clean-all:
 	make -C fmcomms7 clean-all
 	make -C imageon clean-all
 	make -C motcon2_fmc clean-all
-	make -C pzsdr clean-all
+	make -C pluto clean-all
 	make -C pzsdr1 clean-all
-	make -C sdrstk clean-all
+	make -C pzsdr2 clean-all
 	make -C usb_fx3 clean-all
 	make -C usdrx1 clean-all
 	make -C usrpe31x clean-all
diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile
index 752c5d6ff..61b1853cd 100644
--- a/projects/daq3/zc706/Makefile
+++ b/projects/daq3/zc706/Makefile
@@ -32,7 +32,6 @@ M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
-M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 
 M_VIVADO := vivado -mode batch -source
@@ -73,7 +72,6 @@ clean-all:clean
 	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_dacfifo clean
-	make -C ../../../library/util_mfifo clean
 	make -C ../../../library/util_upack clean
 
 
@@ -94,7 +92,6 @@ lib:
 	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_dacfifo
-	make -C ../../../library/util_mfifo
 	make -C ../../../library/util_upack
 
 ####################################################################################
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index ffb6405ff..826055268 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -24,7 +24,6 @@ M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
 M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -58,7 +57,6 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/util_adcfifo clean
 	make -C ../../../library/xilinx/util_adxcvr clean
-	make -C ../../../library/util_jesd_gt clean
 
 
 fmcadc2_vc707.sdk/system_top.hdf: $(M_DEPS)
@@ -72,7 +70,6 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/util_adcfifo
 	make -C ../../../library/xilinx/util_adxcvr
-	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 6923f55f3..933a3bd66 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -28,7 +28,6 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
-M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -65,7 +64,6 @@ clean-all:clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/xilinx/util_adxcvr clean
-	make -C ../../../library/util_jesd_gt clean
 
 
 fmcadc2_zc706.sdk/system_top.hdf: $(M_DEPS)
@@ -82,7 +80,6 @@ lib:
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/xilinx/util_adxcvr
-	make -C ../../../library/util_jesd_gt
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile
index 82a79c8d5..a4aa9799c 100644
--- a/projects/fmcadc4/zc706/Makefile
+++ b/projects/fmcadc4/zc706/Makefile
@@ -30,7 +30,6 @@ M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
 M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -69,7 +68,6 @@ clean-all:clean
 	make -C ../../../library/xilinx/util_adxcvr clean
 	make -C ../../../library/util_bsplit clean
 	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_mfifo clean
 
 
 fmcadc4_zc706.sdk/system_top.hdf: $(M_DEPS)
@@ -88,7 +86,6 @@ lib:
 	make -C ../../../library/xilinx/util_adxcvr
 	make -C ../../../library/util_bsplit
 	make -C ../../../library/util_cpack
-	make -C ../../../library/util_mfifo
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcomms2/Makefile b/projects/fmcomms2/Makefile
index a56d97d9b..765002323 100644
--- a/projects/fmcomms2/Makefile
+++ b/projects/fmcomms2/Makefile
@@ -14,6 +14,7 @@ all:
 	-make -C vc707 all
 	-make -C zc702 all
 	-make -C zc706 all
+	-make -C zc706pr all
 	-make -C zcu102 all
 	-make -C zed all
 
@@ -26,6 +27,7 @@ clean:
 	make -C vc707 clean
 	make -C zc702 clean
 	make -C zc706 clean
+	make -C zc706pr clean
 	make -C zcu102 clean
 	make -C zed clean
 
@@ -38,6 +40,7 @@ clean-all:
 	make -C vc707 clean-all
 	make -C zc702 clean-all
 	make -C zc706 clean-all
+	make -C zc706pr clean-all
 	make -C zcu102 clean-all
 	make -C zed clean-all
 
diff --git a/projects/fmcomms2/zc706pr/Makefile b/projects/fmcomms2/zc706pr/Makefile
index ec1850027..b0a0f920e 100644
--- a/projects/fmcomms2/zc706pr/Makefile
+++ b/projects/fmcomms2/zc706pr/Makefile
@@ -7,8 +7,11 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
+M_DEPS += ../zc706/system_constr.xdc
+M_DEPS += ../zc706/system_bd.tcl
+M_DEPS += ../common/prcfg_bd.tcl
+M_DEPS += ../common/prcfg.v
 M_DEPS += ../common/fmcomms2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
@@ -16,6 +19,9 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/prcfg/default/prcfg_dac.v
+M_DEPS += ../../../library/prcfg/default/prcfg_adc.v
+M_DEPS += ../../../library/prcfg/common/prcfg_top.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@@ -25,10 +31,6 @@ M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
-M_DEPS += ../zc706/system_bd.tcl
-M_DEPS += ../zc706/system_constr.xdc
-M_DEPS += ../common/prcfg_bd.tcl
-M_DEPS += ../common/prcfg_bb.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/projects/pzsdr1/ccbox_lvds/Makefile b/projects/pzsdr1/ccbox_lvds/Makefile
index 8174aca03..7384258d4 100644
--- a/projects/pzsdr1/ccbox_lvds/Makefile
+++ b/projects/pzsdr1/ccbox_lvds/Makefile
@@ -63,7 +63,7 @@ clean-all:clean
 
 pzsdr1_ccbox_lvds.sdk/system_top.hdf: $(M_DEPS)
 	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> pzsdr1_ccbox_lvds.log 2>&1
+	$(M_VIVADO) system_project.tcl >> pzsdr1_ccbox_lvds_vivado.log 2>&1
 
 
 lib:
diff --git a/projects/pzsdr1/ccusb_lvds/Makefile b/projects/pzsdr1/ccusb_lvds/Makefile
new file mode 100644
index 000000000..fa74174b0
--- /dev/null
+++ b/projects/pzsdr1/ccusb_lvds/Makefile
@@ -0,0 +1,79 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/pzsdr1_constr_lvds.xdc
+M_DEPS += ../common/pzsdr1_constr.xdc
+M_DEPS += ../common/pzsdr1_bd.tcl
+M_DEPS += ../common/ccusb_constr.xdc
+M_DEPS += ../common/ccusb_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib pzsdr1_ccusb_lvds.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_usb_fx3 clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_tdd_sync clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+pzsdr1_ccusb_lvds.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> pzsdr1_ccusb_lvds_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_usb_fx3
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_tdd_sync
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index 8850eed3e..5ded32c1c 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -14,7 +14,6 @@ export ALT_NIOS_MMU_ENABLED := $(MMU)
 M_DEPS += system_project.tcl
 M_DEPS += ../common/usdrx1_spi.v
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
 M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v
 M_DEPS += ../../../library/common/altera/ad_jesd_align.v

From 334ce5ddc0cfca4fa45ff21f616435d94338baea Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 2 Dec 2016 15:33:35 +0100
Subject: [PATCH 767/972] axi_intr_monitor: Fully register IRQ output signal

The IRQ signal goes to a asynchronous domain. In order to avoid glitches to
be observed in that domain make sure that the output signal is fully
registered.

This means that the IRQ signal is no longer mask when the control enable
bit is not set. Instead modify the code to clear the interrupt when the
control enable bit is not set. This turns it into a true reset for the
internal state.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_intr_monitor/axi_intr_monitor.v | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/library/axi_intr_monitor/axi_intr_monitor.v b/library/axi_intr_monitor/axi_intr_monitor.v
index c071fc588..07e65c5c5 100644
--- a/library/axi_intr_monitor/axi_intr_monitor.v
+++ b/library/axi_intr_monitor/axi_intr_monitor.v
@@ -105,7 +105,7 @@ wire    [31:0]  up_wdata_s;
 //----------- Assign/Always Blocks ---------------------------------------------
 //------------------------------------------------------------------------------
 
-assign irq = interrupt & control[0];
+assign irq = interrupt;
 
 always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
   if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin
@@ -152,10 +152,12 @@ always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
     if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin
       control <= up_wdata_s;
     end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin
+    if (control[0] == 1'b0) begin
+      interrupt <= 1'b0;
+    end else if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin
       interrupt <= interrupt & ~up_wdata_s[0];
     end else begin
-      if (counter_to_interrupt_cnt == 32'h0 && control[0] == 1'b1) begin
+      if (counter_to_interrupt_cnt == 32'h0) begin
         interrupt <= 1'b1;
       end
     end

From 753f4bd06e5714a6307f622ee8a8b5a148e2c5b8 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 2 Dec 2016 17:54:18 +0100
Subject: [PATCH 768/972] axi_intr_monitor: Slightly modify counter start
 points

Start the counter_to_interrupt_cnt counter when the counter_to_interrupt
value is written to the register map. This gives applications better
control over when the counter starts counting.

Also start the counter_from_interrupt on the rising edge of the interrupt
signal to avoid bogus values.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_intr_monitor/axi_intr_monitor.v | 24 ++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/library/axi_intr_monitor/axi_intr_monitor.v b/library/axi_intr_monitor/axi_intr_monitor.v
index 07e65c5c5..c2ae7309f 100644
--- a/library/axi_intr_monitor/axi_intr_monitor.v
+++ b/library/axi_intr_monitor/axi_intr_monitor.v
@@ -90,6 +90,8 @@ reg     [31:0]  counter_interrupt_handling  = 'd0;
 reg     [31:0]  min_interrupt_handling      = 'd0;
 reg     [31:0]  max_interrupt_handling      = 'd0;
 reg             interrupt_d1                = 'd0;
+reg             arm_counter                 = 'd0;
+reg             counter_active              = 'd0;
 
 //------------------------------------------------------------------------------
 //----------- Wires Declarations -----------------------------------------------
@@ -115,15 +117,26 @@ always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
     min_interrupt_handling <= 'd0;
     max_interrupt_handling <= 'd0;
     interrupt_d1 <= 0;
+    counter_active <= 1'b0;
   end else begin
     interrupt_d1 <= irq;
-    if (irq == 1'b1) begin
+
+    if (arm_counter == 1'b1) begin
       counter_to_interrupt_cnt <= counter_to_interrupt;
+      counter_active <= 1'b1;
     end else if (counter_to_interrupt_cnt > 0) begin
       counter_to_interrupt_cnt <= counter_to_interrupt_cnt - 1;
+    end else begin
+      counter_active <= 1'b0;
     end
-    if (irq == 1'b0 && interrupt_d1 == 1'b1) begin
+
+    if (irq == 1'b1 && interrupt_d1 == 1'b0) begin
       counter_from_interrupt <= 32'h0;
+    end else begin
+      counter_from_interrupt <= counter_from_interrupt + 1;
+    end
+
+    if (irq == 1'b0 && interrupt_d1 == 1'b1) begin
       counter_interrupt_handling <= counter_from_interrupt;
       if (min_interrupt_handling > counter_from_interrupt) begin
         min_interrupt_handling <= counter_from_interrupt;
@@ -131,8 +144,6 @@ always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
       if (max_interrupt_handling < counter_from_interrupt) begin
         max_interrupt_handling <= counter_from_interrupt;
       end
-    end else begin
-      counter_from_interrupt <= counter_from_interrupt + 1;
     end
   end
 end
@@ -144,8 +155,10 @@ always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
     control                    <= 'd0;
     interrupt                  <= 'd0;
     counter_to_interrupt       <= 'd0;
+    arm_counter                <= 'd0;
   end else begin
     up_wack  <= up_wreq_s;
+    arm_counter <= 1'b0;
     if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h1)) begin
       scratch <= up_wdata_s;
     end
@@ -157,12 +170,13 @@ always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
     end else if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin
       interrupt <= interrupt & ~up_wdata_s[0];
     end else begin
-      if (counter_to_interrupt_cnt == 32'h0) begin
+      if (counter_to_interrupt_cnt == 32'h0 && counter_active == 1'b1) begin
         interrupt <= 1'b1;
       end
     end
     if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h4)) begin
       counter_to_interrupt <= up_wdata_s;
+      arm_counter <= 1'b1;
     end
   end
 end

From 8b8c37e2e2c46c8b9d6628cf1844eb7fb75ecb48 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 5 Dec 2016 14:33:39 +0200
Subject: [PATCH 769/972] scripts/adi_ip: Remove AXIMM inference from
 adi_ip_infer_interfaces

The AXI Memory Map interface is infered in the adi_ip_properties process.
Infer it again in the adi_ip_infer_interfaces brakes the flow,
the tool will not find the cell's address segment, so there will not be
any address space assigned to the AXI interface.
Affected cores were axi_i2s_adi and axi_spdif_tx.
---
 library/scripts/adi_ip.tcl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl
index f0430eff3..6583736ff 100644
--- a/library/scripts/adi_ip.tcl
+++ b/library/scripts/adi_ip.tcl
@@ -124,7 +124,6 @@ proc adi_ip_infer_interfaces {ip_name} {
 
   ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
   ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
-  ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
   ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
 }
 

From 351811e13fb2a8dc3538363c40f38cce054f763c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 5 Dec 2016 10:18:40 -0500
Subject: [PATCH 770/972] pzsdrx/ccbox- imu intr on gpio

---
 projects/pzsdr1/ccbox_lvds/system_top.v | 6 ++++--
 projects/pzsdr2/ccbox_lvds/system_top.v | 4 +++-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/projects/pzsdr1/ccbox_lvds/system_top.v b/projects/pzsdr1/ccbox_lvds/system_top.v
index 30c536868..2c806a77e 100644
--- a/projects/pzsdr1/ccbox_lvds/system_top.v
+++ b/projects/pzsdr1/ccbox_lvds/system_top.v
@@ -150,7 +150,9 @@ module system_top (
 
   // gpio[31:20] controls misc stuff (keep as io)
 
-  assign gpio_i[31:24] = gpio_o[31:24];
+  assign gpio_i[31:29] = gpio_o[31:29];
+  assign gpio_i[28:28] = imu_ready;
+  assign gpio_i[27:24] = gpio_o[27:24];
 
   ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_misc (
     .dio_t (gpio_t[23:20]),
@@ -261,7 +263,7 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
-    .ps_intr_00 (imu_ready),
+    .ps_intr_00 (1'b0),
     .ps_intr_01 (1'b0),
     .ps_intr_02 (1'b0),
     .ps_intr_03 (1'b0),
diff --git a/projects/pzsdr2/ccbox_lvds/system_top.v b/projects/pzsdr2/ccbox_lvds/system_top.v
index 6f1245eae..a7b3de9b7 100644
--- a/projects/pzsdr2/ccbox_lvds/system_top.v
+++ b/projects/pzsdr2/ccbox_lvds/system_top.v
@@ -152,7 +152,9 @@ module system_top (
 
   // gpio[31:20] controls misc stuff (keep as io)
 
-  assign gpio_i[31:26] = gpio_o[31:26];
+  assign gpio_i[31:29] = gpio_o[31:29];
+  assign gpio_i[28:28] = imu_ready;
+  assign gpio_i[27:26] = gpio_o[27:26];
 
   ad_iobuf #(.DATA_WIDTH(6)) i_iobuf_misc (
     .dio_t (gpio_t[25:20]),

From 4b7bf422eeee412a5fb55201e5c2515391567276 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 5 Dec 2016 10:21:42 -0500
Subject: [PATCH 771/972] pzsdr2/ccbox- remove imu intr on pl

---
 projects/pzsdr2/ccbox_lvds/system_top.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/pzsdr2/ccbox_lvds/system_top.v b/projects/pzsdr2/ccbox_lvds/system_top.v
index a7b3de9b7..a7ab38b4e 100644
--- a/projects/pzsdr2/ccbox_lvds/system_top.v
+++ b/projects/pzsdr2/ccbox_lvds/system_top.v
@@ -267,7 +267,7 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .otg_vbusoc (1'b0),
-    .ps_intr_00 (imu_ready),
+    .ps_intr_00 (1'b0),
     .ps_intr_01 (1'b0),
     .ps_intr_02 (1'b0),
     .ps_intr_03 (1'b0),

From 1e4bdea80c5b4b3bbdecc84563d9cac2df1200bc Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 6 Dec 2016 11:07:42 +0200
Subject: [PATCH 772/972] usrpe31x: Fix Makefile

---
 projects/usrpe31x/Makefile | 60 ++++++++++++++++++++++++++++++++++----
 1 file changed, 54 insertions(+), 6 deletions(-)

diff --git a/projects/usrpe31x/Makefile b/projects/usrpe31x/Makefile
index 620ee8f00..7e38ae702 100644
--- a/projects/usrpe31x/Makefile
+++ b/projects/usrpe31x/Makefile
@@ -5,17 +5,65 @@
 ####################################################################################
 ####################################################################################
 
-.PHONY: all clean clean-all 
-all:
-	-make -C system_project.tcl all
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../scripts/adi_project.tcl
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_board.tcl
+M_DEPS += ../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../library/util_tdd_sync/util_tdd_sync.xpr
+M_DEPS += ../../library/util_upack/util_upack.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib usrpe31x.sdk/system_top.hdf
 
 
 clean: 
-	make -C system_project.tcl clean
+	rm -rf $(M_FLIST)
 
 
-clean-all:
-	make -C system_project.tcl clean-all
+clean-all:clean
+	make -C ../../library/axi_ad9361 clean
+	make -C ../../library/axi_dmac clean
+	make -C ../../library/util_cpack clean
+	make -C ../../library/util_tdd_sync clean
+	make -C ../../library/util_upack clean
+
+
+usrpe31x.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> usrpe31x_vivado.log 2>&1
+
+
+lib:
+	make -C ../../library/axi_ad9361
+	make -C ../../library/axi_dmac
+	make -C ../../library/util_cpack
+	make -C ../../library/util_tdd_sync
+	make -C ../../library/util_upack
 
 ####################################################################################
 ####################################################################################

From 7a8dc92b848bcdc8a88a9f3e9a0519c573e4a90f Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 6 Dec 2016 11:55:28 +0200
Subject: [PATCH 773/972] usb_fx3: Add interrupt monitor and increase ILA data
 depth

---
 projects/usb_fx3/common/usb_fx3_bd.tcl |  10 +-
 projects/usb_fx3/zc706/system_top.v    | 145 ++++++++-----------------
 2 files changed, 49 insertions(+), 106 deletions(-)

diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl
index 9091adbae..3cf47338a 100644
--- a/projects/usb_fx3/common/usb_fx3_bd.tcl
+++ b/projects/usb_fx3/common/usb_fx3_bd.tcl
@@ -15,8 +15,6 @@ create_bd_port -dir O slwr_n
 create_bd_port -dir O pktend_n
 create_bd_port -dir O epswitch_n
 
-set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7
-
 set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
 set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
 
@@ -30,6 +28,8 @@ set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
 
 set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ]
 
+set intr_monitor [ create_bd_cell -type ip -vlnv analog.com:user:axi_intr_monitor:1.0 intr_monitor ]
+
 ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
 
 ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk
@@ -57,15 +57,17 @@ ad_connect axi_usb_fx3/slwr_n slwr_n
 ad_connect axi_usb_fx3/pktend_n pktend_n
 ad_connect axi_usb_fx3/epswitch_n epswitch_n
 
-
 ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
 ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
 ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut
 ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt
+ad_cpu_interrupt ps-9 mb-16 intr_monitor/irq
 
 ad_cpu_interconnect 0x50000000 axi_usb_fx3
 ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma
 ad_cpu_interconnect 0x40600000 axi_uart
+ad_cpu_interconnect 0x43c00000 intr_monitor
+
 ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
 ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG
 ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S
@@ -82,7 +84,7 @@ set_property -dict [list CONFIG.C_PROBE3_WIDTH {2}] $ila
 set_property -dict [list CONFIG.C_PROBE2_WIDTH {15}] $ila
 set_property -dict [list CONFIG.C_PROBE1_WIDTH {74}] $ila
 set_property -dict [list CONFIG.C_PROBE0_WIDTH {75}] $ila
-set_property -dict [list CONFIG.C_DATA_DEPTH {32768}] $ila
+set_property -dict [list CONFIG.C_DATA_DEPTH {65536}] $ila
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila
 set_property -dict [list CONFIG.C_PROBE2_MU_CNT {2}] $ila
 set_property -dict [list CONFIG.C_PROBE1_MU_CNT {2}] $ila
diff --git a/projects/usb_fx3/zc706/system_top.v b/projects/usb_fx3/zc706/system_top.v
index 8a212e3ca..030872a4d 100644
--- a/projects/usb_fx3/zc706/system_top.v
+++ b/projects/usb_fx3/zc706/system_top.v
@@ -34,122 +34,64 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
 module system_top (
 
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
 
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
 
-  gpio_bd,
+  inout   [14:0]  gpio_bd,
 
-  usb_fx3_uart_tx,
-  usb_fx3_uart_rx,
+  input           usb_fx3_uart_tx,
+  output          usb_fx3_uart_rx,
 
-//  dma_rdy,
-//  dma_wmk,
-  fifo_rdy,
+  input   [ 3:0]  fifo_rdy,
 
-  data,
-  addr,
-  pclk,
-  slcs_n,
-  slrd_n,
-  sloe_n,
-  slwr_n,
-  //epswitch_n,
-  pktend_n,
+  inout   [31:0]  data,
+  output  [1:0]   addr,
+  output          pclk,
+  output          slcs_n,
+  output          slrd_n,
+  output          sloe_n,
+  output          slwr_n,
+  output          pktend_n,
 
-  pmode,
+  output  [ 1:0]  pmode,
 
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
+  output          hdmi_out_clk,
+  output          hdmi_vsync,
+  output          hdmi_hsync,
+  output          hdmi_data_e,
+  output  [23:0]  hdmi_data,
 
-  spdif,
+  output          spdif,
 
-  iic_scl,
-  iic_sda);
+  inout           iic_scl,
+  inout           iic_sda
 
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout   [14:0]  gpio_bd;
-
-  input           usb_fx3_uart_tx;
-  output          usb_fx3_uart_rx;
-
-//  input           dma_rdy;
-//  input           dma_wmk;
-  input   [ 3:0]  fifo_rdy;
-
-  inout   [31:0]  data;
-  output  [1:0]   addr;
-  output          pclk;
-  output          slcs_n;
-  output          slrd_n;
-  output          sloe_n;
-  output          slwr_n;
-  //output          epswitch_n;
-  output          pktend_n;
-
-  output  [ 1:0]  pmode;
-
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [23:0]  hdmi_data;
-
-  output          spdif;
-
-  inout           iic_scl;
-  inout           iic_sda;
+);
 
   // internal signals
 
@@ -225,7 +167,6 @@ module system_top (
     .ps_intr_06 (1'b0),
     .ps_intr_07 (1'b0),
     .ps_intr_08 (1'b0),
-    .ps_intr_09 (1'b0),
     .spdif (spdif));
 
 endmodule

From 6cf9df50e3a7bda4427a491748bf19bf5195859f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 10:37:59 +0200
Subject: [PATCH 774/972] altera/ad_serdes: Define DEVICE_FAMILY in hw script

---
 library/altera/alt_serdes/alt_serdes_hw.tcl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl
index e66c515dc..546454ab9 100644
--- a/library/altera/alt_serdes/alt_serdes_hw.tcl
+++ b/library/altera/alt_serdes/alt_serdes_hw.tcl
@@ -38,11 +38,12 @@ set_parameter_property CLKIN_FREQUENCY UNITS None
 set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
 set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
 
-add_parameter DEVICE_FAMILY STRING
+add_parameter DEVICE_FAMILY STRING "Arria 10"
 set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
 set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
 set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
 set_parameter_property DEVICE_FAMILY ENABLED false
+set_parameter_property DEVICE_FAMILY ALLOWED_RANGES {"Arria 10" "Cyclone V"}
 
 proc p_alt_serdes {} {
 

From 0715c962f199c3200327ff80f32d2f3b3fe4d79f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:46:31 +0200
Subject: [PATCH 775/972] altera/ad_serdes: Fix net alignment for rx_out at
 ad_serdes_in

---
 library/altera/common/ad_serdes_in.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 9b147d698..4a99de8ff 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -127,7 +127,7 @@ module __ad_serdes_in__ #(
   generate
   for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
     for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
-      assign data_samples_s[i][n] = data_out_s[n][((SERDES_FACTOR-1)-i)];
+      assign data_samples_s[i][n] = data_out_s[n][i];
     end
   end
   endgenerate

From cedca30cd6de7b474b68cbb8d5f4ae16543f203d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:48:34 +0200
Subject: [PATCH 776/972] axi_ad9122: Update hw tcl script for altera

---
 library/axi_ad9122/axi_ad9122_hw.tcl | 181 +++++----------------------
 1 file changed, 34 insertions(+), 147 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122_hw.tcl b/library/axi_ad9122/axi_ad9122_hw.tcl
index 8d17ab522..62ee04b0b 100644
--- a/library/axi_ad9122/axi_ad9122_hw.tcl
+++ b/library/axi_ad9122/axi_ad9122_hw.tcl
@@ -3,42 +3,27 @@ package require -exact qsys 13.0
 source ../scripts/adi_env.tcl
 source ../scripts/adi_ip_alt.tcl
 
-set_module_property NAME axi_ad9122
-set_module_property DESCRIPTION "AXI AD9122 Interface"
-set_module_property VERSION 1.0
-set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME axi_ad9122
+ad_ip_create axi_ad9122 {AXI AD9122 Interface}
 
-# files
-
-add_fileset quartus_synth QUARTUS_SYNTH "ad9122_fileset_callback" "Quartus Synthesis"
-set_fileset_property quartus_synth TOP_LEVEL axi_ad9122
-
-add_fileset_file ad_mul.v                 VERILOG PATH  $ad_hdl_dir/library/xilinx/common/ad_mul.v
-add_fileset_file ad_dds_sine.v            VERILOG PATH  $ad_hdl_dir/library/common/ad_dds_sine.v
-add_fileset_file ad_dds_1.v               VERILOG PATH  $ad_hdl_dir/library/common/ad_dds_1.v
-add_fileset_file ad_dds.v                 VERILOG PATH  $ad_hdl_dir/library/common/ad_dds.v
-add_fileset_file ad_rst.v                 VERILOG PATH  $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file ad_mmcm_drp.v            VERILOG PATH  $ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v
-add_fileset_file ad_serdes_out.v          VERILOG PATH  $ad_hdl_dir/library/xilinx/common/ad_serdes_out.v
-add_fileset_file up_axi.v                 VERILOG PATH  $ad_hdl_dir/library/common/up_axi.v
-add_fileset_file up_xfer_cntrl.v          VERILOG PATH  $ad_hdl_dir/library/common/up_xfer_cntrl.v
-add_fileset_file up_xfer_status.v         VERILOG PATH  $ad_hdl_dir/library/common/up_xfer_status.v
-add_fileset_file up_clock_mon.v           VERILOG PATH  $ad_hdl_dir/library/common/up_clock_mon.v
-add_fileset_file up_dac_common.v          VERILOG PATH  $ad_hdl_dir/library/common/up_dac_common.v
-add_fileset_file up_dac_channel.v         VERILOG PATH  $ad_hdl_dir/library/common/up_dac_channel.v
-add_fileset_file axi_ad9122_channel.v     VERILOG PATH  axi_ad9122_channel.v
-add_fileset_file axi_ad9122_core.v        VERILOG PATH  axi_ad9122_core.v
-add_fileset_file axi_ad9122_if.v          VERILOG PATH  axi_ad9122_if.v
-add_fileset_file axi_ad9122.v             VERILOG PATH  axi_ad9122.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc     SDC     PATH  $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
-add_fileset_file axi_ad9122_constr.sdc    SDC     PATH  axi_ad9122_constr.sdc
-
-# paramter for fileset callback
-
-add_parameter HDL_LIB_PATH STRING $ad_hdl_dir
-set_parameter_property HDL_LIB_PATH TYPE STRING
-set_parameter_property HDL_LIB_PATH HDL_PARAMETER false
+ad_ip_files axi_ad9122 [list \
+    $ad_hdl_dir/library/common/ad_dds_sine.v \
+    $ad_hdl_dir/library/common/ad_dds_1.v \
+    $ad_hdl_dir/library/common/ad_dds.v \
+    $ad_hdl_dir/library/altera/common/ad_mul.v \
+    $ad_hdl_dir/library/common/ad_rst.v \
+    $ad_hdl_dir/library/common/up_axi.v \
+    $ad_hdl_dir/library/common/up_xfer_cntrl.v \
+    $ad_hdl_dir/library/common/up_xfer_status.v \
+    $ad_hdl_dir/library/common/up_clock_mon.v \
+    $ad_hdl_dir/library/common/up_dac_common.v \
+    $ad_hdl_dir/library/common/up_dac_channel.v \
+    axi_ad9122_channel.v \
+    axi_ad9122_core.v \
+    axi_ad9122_if.v \
+    axi_ad9122.v \
+    $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
+    axi_ad9122_constr.sdc] \
+    axi_ad9122_fileset
 
 # parameters
 
@@ -56,100 +41,9 @@ set_parameter_property DEVICE_TYPE TYPE INTEGER
 set_parameter_property DEVICE_TYPE UNITS None
 set_parameter_property DEVICE_TYPE HDL_PARAMETER true
 
-add_parameter SERDES_OR_DDR_N INTEGER 0
-set_parameter_property SERDES_OR_DDR_N DEFAULT_VALUE 1
-set_parameter_property SERDES_OR_DDR_N DISPLAY_NAME SERDES_OR_DDR_N
-set_parameter_property SERDES_OR_DDR_N TYPE INTEGER
-set_parameter_property SERDES_OR_DDR_N UNITS None
-set_parameter_property SERDES_OR_DDR_N HDL_PARAMETER true
-
-add_parameter MMCM_OR_BUFIO_N INTEGER 0
-set_parameter_property MMCM_OR_BUFIO_N DEFAULT_VALUE 0
-set_parameter_property MMCM_OR_BUFIO_N DISPLAY_NAME MMCM_OR_BUFIO_N
-set_parameter_property MMCM_OR_BUFIO_N TYPE INTEGER
-set_parameter_property MMCM_OR_BUFIO_N UNITS None
-set_parameter_property MMCM_OR_BUFIO_N HDL_PARAMETER false
-
-add_parameter MMCM_CLKIN_PERIOD FLOAT 0
-set_parameter_property MMCM_CLKIN_PERIOD DEFAULT_VALUE 1.667
-set_parameter_property MMCM_CLKIN_PERIOD DISPLAY_NAME MMCM_CLKIN_PERIOD
-set_parameter_property MMCM_CLKIN_PERIOD TYPE INTEGER
-set_parameter_property MMCM_CLKIN_PERIOD UNITS None
-set_parameter_property MMCM_CLKIN_PERIOD HDL_PARAMETER false
-
-add_parameter MMCM_VCO_DIV INTEGER 0
-set_parameter_property MMCM_VCO_DIV DEFAULT_VALUE 2
-set_parameter_property MMCM_VCO_DIV DISPLAY_NAME MMCM_VCO_DIV
-set_parameter_property MMCM_VCO_DIV TYPE INTEGER
-set_parameter_property MMCM_VCO_DIV UNITS None
-set_parameter_property MMCM_VCO_DIV HDL_PARAMETER false
-
-add_parameter MMCM_VCO_MUL INTEGER 0
-set_parameter_property MMCM_VCO_MUL DEFAULT_VALUE 4
-set_parameter_property MMCM_VCO_MUL DISPLAY_NAME MMCM_VCO_MUL
-set_parameter_property MMCM_VCO_MUL TYPE INTEGER
-set_parameter_property MMCM_VCO_MUL UNITS None
-set_parameter_property MMCM_VCO_MUL HDL_PARAMETER false
-
-add_parameter MMCM_CLK0_DIV INTEGER 0
-set_parameter_property MMCM_CLK0_DIV DEFAULT_VALUE 2
-set_parameter_property MMCM_CLK0_DIV DISPLAY_NAME MMCM_CLK0_DIV
-set_parameter_property MMCM_CLK0_DIV TYPE INTEGER
-set_parameter_property MMCM_CLK0_DIV UNITS None
-set_parameter_property MMCM_CLK0_DIV HDL_PARAMETER false
-
-add_parameter MMCM_CLK1_DIV INTEGER 0
-set_parameter_property MMCM_CLK1_DIV DEFAULT_VALUE 8
-set_parameter_property MMCM_CLK1_DIV DISPLAY_NAME MMCM_CLK1_DIV
-set_parameter_property MMCM_CLK1_DIV TYPE INTEGER
-set_parameter_property MMCM_CLK1_DIV UNITS None
-set_parameter_property MMCM_CLK1_DIV HDL_PARAMETER false
-
-add_parameter DAC_DATAPATH_DISABLE INTEGER 0
-set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 8
-set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
-set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
-set_parameter_property DAC_DATAPATH_DISABLE UNITS None
-set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
-
-add_parameter IO_DELAY_GROUP INTEGER 0
-set_parameter_property IO_DELAY_GROUP DEFAULT_VALUE 8
-set_parameter_property IO_DELAY_GROUP DISPLAY_NAME IO_DELAY_GROUP
-set_parameter_property IO_DELAY_GROUP TYPE INTEGER
-set_parameter_property IO_DELAY_GROUP UNITS None
-set_parameter_property IO_DELAY_GROUP HDL_PARAMETER true
-
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # dac device interface
 
@@ -192,29 +86,22 @@ ad_alt_intf signal dac_dunf input 1 unf
 
 # SERDES instances and configurations
 
-add_hdl_instance alt_serdes_clk_core_tx alt_serdes
-set_instance_parameter_value alt_serdes_clk_core_tx {MODE} {CLK}
-set_instance_parameter_value alt_serdes_clk_core_tx {DDR_OR_SDR_N} {1}
-set_instance_parameter_value alt_serdes_clk_core_tx {SERDES_FACTOR} {8}
-set_instance_parameter_value alt_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0}
+add_hdl_instance ad_serdes_clk_core_tx alt_serdes
+set_instance_parameter_value ad_serdes_clk_core_tx {MODE} {CLK}
+set_instance_parameter_value ad_serdes_clk_core_tx {DDR_OR_SDR_N} {1}
+set_instance_parameter_value ad_serdes_clk_core_tx {SERDES_FACTOR} {8}
+set_instance_parameter_value ad_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0}
 
-add_hdl_instance alt_serdes_out_core alt_serdes
-set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
-set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
-set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {8}
-set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {500.0}
+add_hdl_instance ad_serdes_out_core alt_serdes
+set_instance_parameter_value ad_serdes_out_core {MODE} {OUT}
+set_instance_parameter_value ad_serdes_out_core {DDR_OR_SDR_N} {1}
+set_instance_parameter_value ad_serdes_out_core {SERDES_FACTOR} {8}
+set_instance_parameter_value ad_serdes_out_core {CLKIN_FREQUENCY} {500.0}
 
-# fileset callback to create the SERDES CLOCK instances
+proc axi_ad9122_fileset { entityName } {
 
-proc ad9122_fileset_callback { entityName } {
+  ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
+  ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_tx
 
-  send_message INFO "Generating SERDES clock instance for $entityName"
-  set ad_hdl_dir [get_parameter_value HDL_LIB_PATH]
-  exec mkdir -p generated
-
-  # copy the generic ad_serdes_clk into working directory with modified ALT_IOPLL instance name
-  ad_generate_module_inst "alt_serdes_clk_core" "tx" $ad_hdl_dir/library/altera/common/ad_serdes_clk.v generated/ad_serdes_clk.v
-
-  add_fileset_file  generated/ad_serdes_clk.v   VERILOG PATH  generated/ad_serdes_clk.v
 }
 

From b0a5be85653714dbc58ed9d1ce0ead176a97b8f5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:49:33 +0200
Subject: [PATCH 777/972] axi_ad9122: Add loaden port for altera support

---
 library/axi_ad9122/axi_ad9122_if.v | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v
index 7f5a64658..4eb921561 100644
--- a/library/axi_ad9122/axi_ad9122_if.v
+++ b/library/axi_ad9122/axi_ad9122_if.v
@@ -169,6 +169,7 @@ module axi_ad9122_if (
   // internal signals
 
   wire            dac_out_clk;
+  wire            loaden_s;
 
   // dac status
 
@@ -192,7 +193,7 @@ module axi_ad9122_if (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
+    .loaden (loaden_s),
     .data_s0 (dac_data_i0),
     .data_s1 (dac_data_q0),
     .data_s2 (dac_data_i1),
@@ -214,7 +215,7 @@ module axi_ad9122_if (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
+    .loaden (loaden_s),
     .data_s0 (dac_frame_i0),
     .data_s1 (dac_frame_q0),
     .data_s2 (dac_frame_i1),
@@ -234,9 +235,9 @@ module axi_ad9122_if (
     .DATA_WIDTH (1))
   i_serdes_out_clk (
     .rst (dac_rst),
-    .clk (dac_out_clk),
+    .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
+    .loaden (loaden_s),
     .data_s0 (1'b1),
     .data_s1 (1'b0),
     .data_s2 (1'b1),
@@ -266,7 +267,7 @@ module axi_ad9122_if (
     .clk (dac_clk),
     .div_clk (dac_div_clk),
     .out_clk (dac_out_clk),
-    .loaden (),
+    .loaden (loaden_s),
     .phase (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),

From a7d3df875795f8388fa1e94962dc3e502d159b1b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:50:28 +0200
Subject: [PATCH 778/972] axi_ad9684: Update hw tcl script for altera

---
 library/axi_ad9684/axi_ad9684_hw.tcl | 139 +++++++++------------------
 1 file changed, 44 insertions(+), 95 deletions(-)

diff --git a/library/axi_ad9684/axi_ad9684_hw.tcl b/library/axi_ad9684/axi_ad9684_hw.tcl
index cc88b7c67..a6ffcedd5 100644
--- a/library/axi_ad9684/axi_ad9684_hw.tcl
+++ b/library/axi_ad9684/axi_ad9684_hw.tcl
@@ -3,44 +3,36 @@ package require -exact qsys 13.0
 source ../scripts/adi_env.tcl
 source ../scripts/adi_ip_alt.tcl
 
-set_module_property NAME axi_ad9684
-set_module_property DESCRIPTION "AXI ad9684 Interface"
-set_module_property VERSION 1.0
-set_module_property GROUP "Analog Devices"
-set_module_property DISPLAY_NAME axi_ad9684
-set_module_property ELABORATION_CALLBACK p_axi_ad9684
-
-# files
-
-add_fileset quartus_synth QUARTUS_SYNTH "ad9684_fileset_callback" "Quartus Synthesis"
-set_fileset_property quartus_synth TOP_LEVEL axi_ad9684
-
-add_fileset_file  ad_rst.v               VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file  ad_serdes_in.v         VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v
-add_fileset_file  ad_datafmt.v           VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
-add_fileset_file  ad_pnmon.v             VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
-add_fileset_file  up_xfer_status.v       VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
-add_fileset_file  up_xfer_cntrl.v        VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
-add_fileset_file  up_clock_mon.v         VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
-add_fileset_file  up_delay_cntrl.v       VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
-add_fileset_file  up_adc_common.v        VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
-add_fileset_file  up_adc_channel.v       VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
-add_fileset_file  up_axi.v               VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
-add_fileset_file  axi_ad9684_pnmon.v     VERILOG PATH axi_ad9684_pnmon.v
-add_fileset_file  axi_ad9684_if.v        VERILOG PATH axi_ad9684_if.v
-add_fileset_file  axi_ad9684_channel.v   VERILOG PATH axi_ad9684_channel.v
-add_fileset_file  axi_ad9684.v           VERILOG PATH axi_ad9684.v TOP_LEVEL_FILE
-add_fileset_file  ad_axi_ip_constr.sdc   SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
-add_fileset_file  axi_ad9684_constr.sdc  SDC     PATH axi_ad9684_constr.sdc
-
-# paramter for fileset callback
-
-add_parameter HDL_LIB_PATH STRING $ad_hdl_dir
-set_parameter_property HDL_LIB_PATH TYPE STRING
-set_parameter_property HDL_LIB_PATH HDL_PARAMETER false
+ad_ip_create axi_ad9684 {AXI AD9684 Interface} axi_ad9684_elab
+ad_ip_files axi_ad9684 [list \
+    $ad_hdl_dir/library/common/ad_rst.v \
+    $ad_hdl_dir/library/common/ad_datafmt.v \
+    $ad_hdl_dir/library/common/ad_pnmon.v \
+    $ad_hdl_dir/library/common/up_xfer_status.v \
+    $ad_hdl_dir/library/common/up_xfer_cntrl.v \
+    $ad_hdl_dir/library/common/up_clock_mon.v \
+    $ad_hdl_dir/library/common/up_delay_cntrl.v \
+    $ad_hdl_dir/library/common/up_adc_common.v \
+    $ad_hdl_dir/library/common/up_adc_channel.v \
+    $ad_hdl_dir/library/common/up_axi.v \
+    axi_ad9684_pnmon.v \
+    axi_ad9684_if.v \
+    axi_ad9684_channel.v \
+    axi_ad9684.v \
+    $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
+    axi_ad9684_constr.sdc] \
+    axi_ad9684_fileset
 
 # parameters
 
+add_parameter ID INTEGER 0
+set_parameter_property ID DEFAULT_VALUE 0
+set_parameter_property ID DISPLAY_NAME ID
+set_parameter_property ID TYPE INTEGER
+set_parameter_property ID DESCRIPTION "Instance ID"
+set_parameter_property ID UNITS None
+set_parameter_property ID HDL_PARAMETER true
+
 add_parameter DEVICE_TYPE INTEGER 0
 set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
 set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
@@ -49,14 +41,6 @@ set_parameter_property DEVICE_TYPE DESCRIPTION "Specify the FPGA device type"
 set_parameter_property DEVICE_TYPE UNITS None
 set_parameter_property DEVICE_TYPE HDL_PARAMETER true
 
-add_parameter DAC_DATAPATH_DISABLE INTEGER 0
-set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
-set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
-set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
-set_parameter_property DAC_DATAPATH_DISABLE DESCRIPTION "If active, all the data processing logic will be left out from the IP"
-set_parameter_property DAC_DATAPATH_DISABLE UNITS None
-set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
-
 add_parameter OR_STATUS INTEGER 1
 set_parameter_property OR_STATUS DEFAULT_VALUE 1
 set_parameter_property OR_STATUS DISPLAY_NAME OR_STATUS
@@ -67,35 +51,7 @@ set_parameter_property OR_STATUS HDL_PARAMETER true
 
 # axi4 slave
 
-add_interface s_axi_clock clock end
-add_interface_port s_axi_clock s_axi_aclk clk Input 1
-
-add_interface s_axi_reset reset end
-set_interface_property s_axi_reset associatedClock s_axi_clock
-add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
-
-add_interface s_axi axi4lite end
-set_interface_property s_axi associatedClock s_axi_clock
-set_interface_property s_axi associatedReset s_axi_reset
-add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 16
-add_interface_port s_axi s_axi_awprot awprot Input 3
-add_interface_port s_axi s_axi_awready awready Output 1
-add_interface_port s_axi s_axi_wvalid wvalid Input 1
-add_interface_port s_axi s_axi_wdata wdata Input 32
-add_interface_port s_axi s_axi_wstrb wstrb Input 4
-add_interface_port s_axi s_axi_wready wready Output 1
-add_interface_port s_axi s_axi_bvalid bvalid Output 1
-add_interface_port s_axi s_axi_bresp bresp Output 2
-add_interface_port s_axi s_axi_bready bready Input 1
-add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 16
-add_interface_port s_axi s_axi_arprot arprot Input 3
-add_interface_port s_axi s_axi_arready arready Output 1
-add_interface_port s_axi s_axi_rvalid rvalid Output 1
-add_interface_port s_axi s_axi_rresp rresp Output 2
-add_interface_port s_axi s_axi_rdata rdata Output 32
-add_interface_port s_axi s_axi_rready rready Input 1
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
 
 # adc device interface
 
@@ -116,14 +72,14 @@ ad_alt_intf reset adc_rst output 1 if_adc_clk
 add_interface adc_ch_0 conduit end
 add_interface_port adc_ch_0 adc_valid_0   valid   Output 1
 add_interface_port adc_ch_0 adc_enable_0  enable  Output 1
-add_interface_port adc_ch_0 adc_ddata_0   data    Output 32
+add_interface_port adc_ch_0 adc_data_0   data    Output 32
 set_interface_property adc_ch_0 associatedClock if_adc_clk
 set_interface_property adc_ch_0 associatedReset none
 
 add_interface adc_ch_1 conduit end
 add_interface_port adc_ch_1 adc_valid_1   valid   Output 1
 add_interface_port adc_ch_1 adc_enable_1  enable  Output 1
-add_interface_port adc_ch_1 adc_ddata_1   data    Output 32
+add_interface_port adc_ch_1 adc_data_1   data    Output 32
 set_interface_property adc_ch_1 associatedClock if_adc_clk
 set_interface_property adc_ch_1 associatedReset none
 
@@ -132,19 +88,19 @@ ad_alt_intf signal adc_dunf input 1 unf
 
 # SERDES instances and configurations
 
-add_hdl_instance alt_serdes_clk_core_rx alt_serdes
-set_instance_parameter_value alt_serdes_clk_core_rx {MODE} {CLK}
-set_instance_parameter_value alt_serdes_clk_core_rx {DDR_OR_SDR_N} {1}
-set_instance_parameter_value alt_serdes_clk_core_rx {SERDES_FACTOR} {4}
-set_instance_parameter_value alt_serdes_clk_core_rx {CLKIN_FREQUENCY} {500.0}
+add_hdl_instance ad_serdes_clk_core_rx alt_serdes
+set_instance_parameter_value ad_serdes_clk_core_rx {MODE} {CLK}
+set_instance_parameter_value ad_serdes_clk_core_rx {DDR_OR_SDR_N} {1}
+set_instance_parameter_value ad_serdes_clk_core_rx {SERDES_FACTOR} {4}
+set_instance_parameter_value ad_serdes_clk_core_rx {CLKIN_FREQUENCY} {500.0}
 
-add_hdl_instance alt_serdes_in_core alt_serdes
-set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
-set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
-set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
-set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {500.0}
+add_hdl_instance ad_serdes_in_core alt_serdes
+set_instance_parameter_value ad_serdes_in_core {MODE} {IN}
+set_instance_parameter_value ad_serdes_in_core {DDR_OR_SDR_N} {1}
+set_instance_parameter_value ad_serdes_in_core {SERDES_FACTOR} {4}
+set_instance_parameter_value ad_serdes_in_core {CLKIN_FREQUENCY} {500.0}
 
-proc p_axi_ad9684 {} {
+proc axi_ad9684_elab {} {
 
   set or_status [get_parameter_value OR_STATUS]
 
@@ -154,17 +110,10 @@ proc p_axi_ad9684 {} {
   }
 }
 
-# fileset callback to create the SERDES CLOCK instances
+proc axi_ad9684_fileset { entityName } {
 
-proc ad9684_fileset_callback { entityName } {
+  ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
+  ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_rx
 
-  send_message INFO "Generating SERDES clock instance for $entityName"
-  set ad_hdl_dir [get_parameter_value HDL_LIB_PATH]
-  exec mkdir -p generated
-
-  # copy the generic ad_serdes_clk into working directory with modified ALT_IOPLL instance name
-  ad_generate_module_inst "alt_serdes_clk_core" "rx" $ad_hdl_dir/library/altera/common/ad_serdes_clk.v generated/ad_serdes_clk.v
-
-  add_fileset_file  generated/ad_serdes_clk.v   VERILOG PATH  generated/ad_serdes_clk.v
 }
 

From 7876c8ffa4b18d557ece2f04e9ce145c1872b20c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:51:11 +0200
Subject: [PATCH 779/972] axi_ad9684: Add loaden and phase ports for altera
 support

---
 library/axi_ad9684/axi_ad9684_if.v | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v
index d2672bf9a..58e91058c 100644
--- a/library/axi_ad9684/axi_ad9684_if.v
+++ b/library/axi_ad9684/axi_ad9684_if.v
@@ -137,6 +137,9 @@ module axi_ad9684_if (
   wire            adc_div_clk;
   wire  [ 1:0]    adc_data_or_a_s;
   wire  [ 1:0]    adc_data_or_b_s;
+  wire            loaden_s;
+  wire  [ 7:0]    phase_s;
+
 
   genvar          l_inst;
 
@@ -157,8 +160,8 @@ module axi_ad9684_if (
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
-    .loaden(1'b0),
-    .phase(8'b0),
+    .loaden(loaden_s),
+    .phase(phase_s),
     .locked(1'b0),
     .data_s0(adc_data_b[27:14]),
     .data_s1(adc_data_a[27:14]),
@@ -190,8 +193,8 @@ module axi_ad9684_if (
       .rst(adc_rst),
       .clk(adc_clk_in),
       .div_clk(adc_div_clk),
-      .loaden(1'b0),
-      .phase(8'b0),
+      .loaden(loaden_s),
+      .phase(phase_s),
       .locked(1'b0),
       .data_s0(adc_data_or_b_s[1]),
       .data_s1(adc_data_or_a_s[1]),
@@ -238,8 +241,8 @@ module axi_ad9684_if (
     .clk (adc_clk_in),
     .div_clk (adc_div_clk),
     .out_clk (),
-    .loaden (),
-    .phase (),
+    .loaden (loaden_s),
+    .phase (phase_s),
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_drp_sel (up_drp_sel),

From 977e6d918994b7ef8a1203b22b61fcd66c51cd4d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:55:48 +0200
Subject: [PATCH 780/972] adi_ip_alt: Fix some typo

---
 library/scripts/adi_ip_alt.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl
index e00ad3a7a..4cfb9b142 100644
--- a/library/scripts/adi_ip_alt.tcl
+++ b/library/scripts/adi_ip_alt.tcl
@@ -106,7 +106,7 @@ proc ad_ip_create {pname pdesc {pelabfunction ""} {pcomposefunction ""}} {
   }
 
   if {$pcomposefunction ne ""} {
-    set_module_property ELABORATION_CALLBACK $pcomposefunction
+    set_module_property COMPOSITION_CALLBACK $pcomposefunction
   }
 }
 

From e30a80fda046716731bf80e6bcd6e1d13f20ec83 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:57:42 +0200
Subject: [PATCH 781/972] daq1_spi: Delete device specific macro instantiation

---
 projects/daq1/common/daq1_spi.v | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/projects/daq1/common/daq1_spi.v b/projects/daq1/common/daq1_spi.v
index 7cc62389e..449329bbd 100644
--- a/projects/daq1/common/daq1_spi.v
+++ b/projects/daq1/common/daq1_spi.v
@@ -108,13 +108,10 @@ module daq1_spi (
     end
   end
 
-  // io butter
+  // io logic
 
-  IOBUF i_iobuf_sdio (
-    .T (spi_enable_s),
-    .I (spi_mosi),
-    .O (spi_miso),
-    .IO (spi_sdio));
+  assign spi_miso = spi_sdio;
+  assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
 
 endmodule
 

From a4156250694f0cff350ab0d843c83a728dafcdc6 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:59:40 +0200
Subject: [PATCH 782/972] daq1/a10gx: Add spi wrapper file to the project

---
 projects/daq1/a10gx/system_project.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/daq1/a10gx/system_project.tcl b/projects/daq1/a10gx/system_project.tcl
index 64233ee76..124b2b47d 100644
--- a/projects/daq1/a10gx/system_project.tcl
+++ b/projects/daq1/a10gx/system_project.tcl
@@ -6,6 +6,7 @@ project_new daq1_a10gx -overwrite
 
 source "../../common/a10gx/a10gx_system_assign.tcl"
 
+set_global_assignment -name VERILOG_FILE ../common/daq1_spi.v
 set_global_assignment -name VERILOG_FILE system_top.v
 set_global_assignment -name QSYS_FILE system_bd.qsys
 

From b7143a7a3b4c119102279e8bfec0bb8e36755118 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 15:01:14 +0200
Subject: [PATCH 783/972] daq1/a10gx: Update IO pin assignments

---
 projects/daq1/a10gx/system_project.tcl | 145 ++++++++++++-------------
 1 file changed, 72 insertions(+), 73 deletions(-)

diff --git a/projects/daq1/a10gx/system_project.tcl b/projects/daq1/a10gx/system_project.tcl
index 124b2b47d..8862cc6be 100644
--- a/projects/daq1/a10gx/system_project.tcl
+++ b/projects/daq1/a10gx/system_project.tcl
@@ -15,76 +15,75 @@ set_global_assignment -name TOP_LEVEL_ENTITY system_top
 
 # physical interface
 
+set_location_assignment PIN_BA12  -to dac_clk_in                  ; ##  G02  FMC_LPC_CLK1_M2C_P
+set_location_assignment PIN_BA13  -to "dac_clk_in(n)"             ; ##  G03  FMC_LPC_CLK1_M2C_N
+set_location_assignment PIN_AY15  -to dac_clk_out                 ; ##  G27  FMC_LPC_LA25_P
+set_location_assignment PIN_AY14  -to "dac_clk_out(n)"            ; ##  G28  FMC_LPC_LA25_N
+set_location_assignment PIN_AV20  -to dac_frame_out               ; ##  H37  FMC_LPC_LA32_P
+set_location_assignment PIN_AU20  -to "dac_frame_out(n)"          ; ##  H38  FMC_LPC_LA32_N
+set_location_assignment PIN_AR9   -to dac_data_out[0]             ; ##  H19  FMC_LPC_LA15_P
+set_location_assignment PIN_AT9   -to "dac_data_out[0](n)"        ; ##  H20  FMC_LPC_LA15_N
+set_location_assignment PIN_AU8   -to dac_data_out[1]             ; ##  G21  FMC_LPC_LA20_P
+set_location_assignment PIN_AT8   -to "dac_data_out[1](n)"        ; ##  G22  FMC_LPC_LA20_N
+set_location_assignment PIN_AU11  -to dac_data_out[2]             ; ##  H22  FMC_LPC_LA19_P
+set_location_assignment PIN_AU12  -to "dac_data_out[2](n)"        ; ##  H23  FMC_LPC_LA19_N
+set_location_assignment PIN_AV19  -to dac_data_out[3]             ; ##  D20  FMC_LPC_LA17_CC_P
+set_location_assignment PIN_AW19  -to "dac_data_out[3](n)"        ; ##  D21  FMC_LPC_LA17_CC_N
+set_location_assignment PIN_AU18  -to dac_data_out[4]             ; ##  D23  FMC_LPC_LA23_P
+set_location_assignment PIN_AT18  -to "dac_data_out[4](n)"        ; ##  D24  FMC_LPC_LA23_N
+set_location_assignment PIN_AW12  -to dac_data_out[5]             ; ##  G24  FMC_LPC_LA22_P
+set_location_assignment PIN_AY12  -to "dac_data_out[5](n)"        ; ##  G25  FMC_LPC_LA22_N
+set_location_assignment PIN_AU21  -to dac_data_out[6]             ; ##  C22  FMC_LPC_LA18_CC_P
+set_location_assignment PIN_AV21  -to "dac_data_out[6](n)"        ; ##  C23  FMC_LPC_LA18_CC_N
+set_location_assignment PIN_AY10  -to dac_data_out[7]             ; ##  H25  FMC_LPC_LA21_P
+set_location_assignment PIN_AY11  -to "dac_data_out[7](n)"        ; ##  H26  FMC_LPC_LA21_N
+set_location_assignment PIN_AT19  -to dac_data_out[8]             ; ##  D26  FMC_LPC_LA26_P
+set_location_assignment PIN_AT20  -to "dac_data_out[8](n)"        ; ##  D27  FMC_LPC_LA26_N
+set_location_assignment PIN_BB15  -to dac_data_out[9]             ; ##  H28  FMC_LPC_LA24_P
+set_location_assignment PIN_BC15  -to "dac_data_out[9](n)"        ; ##  H29  FMC_LPC_LA24_N
+set_location_assignment PIN_AP21  -to dac_data_out[10]            ; ##  C26  FMC_LPC_LA27_P
+set_location_assignment PIN_AR21  -to "dac_data_out[10](n)"       ; ##  C27  FMC_LPC_LA27_N
+set_location_assignment PIN_BA15  -to dac_data_out[11]            ; ##  G30  FMC_LPC_LA29_P
+set_location_assignment PIN_BA14  -to "dac_data_out[11](n)"       ; ##  G31  FMC_LPC_LA29_N
+set_location_assignment PIN_AY16  -to dac_data_out[12]            ; ##  H31  FMC_LPC_LA28_P
+set_location_assignment PIN_AW16  -to "dac_data_out[12](n)"       ; ##  H32  FMC_LPC_LA28_N
+set_location_assignment PIN_BB17  -to dac_data_out[13]            ; ##  G33  FMC_LPC_LA31_P
+set_location_assignment PIN_BB18  -to "dac_data_out[13](n)"       ; ##  G34  FMC_LPC_LA31_N
+set_location_assignment PIN_BC18  -to dac_data_out[14]            ; ##  H34  FMC_LPC_LA30_P
+set_location_assignment PIN_BD18  -to "dac_data_out[14](n)"       ; ##  H35  FMC_LPC_LA30_N
+set_location_assignment PIN_AY17  -to dac_data_out[15]            ; ##  G36  FMC_LPC_LA33_P
+set_location_assignment PIN_AW17  -to "dac_data_out[15](n)"       ; ##  G37  FMC_LPC_LA33_N
 
-set_location_assignment PIN_AC28  -to dac_clk_in                  ; ##  G02  FMC_LPC_CLK1_M2C_P
-set_location_assignment PIN_AD28  -to "dac_clk_in(n)"             ; ##  G03  FMC_LPC_CLK1_M2C_N
-set_location_assignment PIN_AF29  -to dac_clk_out                 ; ##  G27  FMC_LPC_LA25_P
-set_location_assignment PIN_AG29  -to "dac_clk_out(n)"            ; ##  G28  FMC_LPC_LA25_N
-set_location_assignment PIN_Y26   -to dac_frame_out               ; ##  H37  FMC_LPC_LA32_P
-set_location_assignment PIN_Y27   -to "dac_frame_out(n)"          ; ##  H38  FMC_LPC_LA32_N
-set_location_assignment PIN_AB15  -to dac_data_out[0]             ; ##  H19  FMC_LPC_LA15_P
-set_location_assignment PIN_AB14  -to "dac_data_out[0](n)"        ; ##  H20  FMC_LPC_LA15_N
-set_location_assignment PIN_AG26  -to dac_data_out[1]             ; ##  G21  FMC_LPC_LA20_P
-set_location_assignment PIN_AG27  -to "dac_data_out[1](n)"        ; ##  G22  FMC_LPC_LA20_N
-set_location_assignment PIN_AH26  -to dac_data_out[2]             ; ##  H22  FMC_LPC_LA19_P
-set_location_assignment PIN_AH27  -to "dac_data_out[2](n)"        ; ##  H23  FMC_LPC_LA19_N
-set_location_assignment PIN_AB27  -to dac_data_out[3]             ; ##  D20  FMC_LPC_LA17_CC_P
-set_location_assignment PIN_AC27  -to "dac_data_out[3](n)"        ; ##  D21  FMC_LPC_LA17_CC_N
-set_location_assignment PIN_AJ26  -to dac_data_out[4]             ; ##  D23  FMC_LPC_LA23_P
-set_location_assignment PIN_AK26  -to "dac_data_out[4](n)"        ; ##  D24  FMC_LPC_LA23_N
-set_location_assignment PIN_AK27  -to dac_data_out[5]             ; ##  G24  FMC_LPC_LA22_P
-set_location_assignment PIN_AK28  -to "dac_data_out[5](n)"        ; ##  G25  FMC_LPC_LA22_N
-set_location_assignment PIN_AE27  -to dac_data_out[6]             ; ##  C22  FMC_LPC_LA18_CC_P
-set_location_assignment PIN_AF27  -to "dac_data_out[6](n)"        ; ##  C23  FMC_LPC_LA18_CC_N
-set_location_assignment PIN_AH28  -to dac_data_out[7]             ; ##  H25  FMC_LPC_LA21_P
-set_location_assignment PIN_AH29  -to "dac_data_out[7](n)"        ; ##  H26  FMC_LPC_LA21_N
-set_location_assignment PIN_AJ30  -to dac_data_out[8]             ; ##  D26  FMC_LPC_LA26_P
-set_location_assignment PIN_AK30  -to "dac_data_out[8](n)"        ; ##  D27  FMC_LPC_LA26_N
-set_location_assignment PIN_AF30  -to dac_data_out[9]             ; ##  H28  FMC_LPC_LA24_P
-set_location_assignment PIN_AG30  -to "dac_data_out[9](n)"        ; ##  H29  FMC_LPC_LA24_N
-set_location_assignment PIN_AJ28  -to dac_data_out[10]            ; ##  C26  FMC_LPC_LA27_P
-set_location_assignment PIN_AJ29  -to "dac_data_out[10](n)"       ; ##  C27  FMC_LPC_LA27_N
-set_location_assignment PIN_AE25  -to dac_data_out[11]            ; ##  G30  FMC_LPC_LA29_P
-set_location_assignment PIN_AF25  -to "dac_data_out[11](n)"       ; ##  G31  FMC_LPC_LA29_N
-set_location_assignment PIN_AD25  -to dac_data_out[12]            ; ##  H31  FMC_LPC_LA28_P
-set_location_assignment PIN_AE26  -to "dac_data_out[12](n)"       ; ##  H32  FMC_LPC_LA28_N
-set_location_assignment PIN_AC29  -to dac_data_out[13]            ; ##  G33  FMC_LPC_LA31_P
-set_location_assignment PIN_AD29  -to "dac_data_out[13](n)"       ; ##  G34  FMC_LPC_LA31_N
-set_location_assignment PIN_AB29  -to dac_data_out[14]            ; ##  H34  FMC_LPC_LA30_P
-set_location_assignment PIN_AB30  -to "dac_data_out[14](n)"       ; ##  H35  FMC_LPC_LA30_N
-set_location_assignment PIN_Y30   -to dac_data_out[15]            ; ##  G36  FMC_LPC_LA33_P
-set_location_assignment PIN_AA30  -to "dac_data_out[15](n)"       ; ##  G37  FMC_LPC_LA33_N
-
-set_location_assignment PIN_AE13  -to adc_clk_in                  ; ##    G06  FMC_LPC_LA00_CC_P
-set_location_assignment PIN_AF13  -to "adc_clk_in(n)"             ; ##  G07  FMC_LPC_LA00_CC_N
-set_location_assignment PIN_AC14  -to adc_data_in[0]              ; ##  C14  FMC_LPC_LA10_P
-set_location_assignment PIN_AC13  -to "adc_data_in[0](n)"         ; ##  C15  FMC_LPC_LA10_N
-set_location_assignment PIN_AF18  -to adc_data_in[1]              ; ##  C18  FMC_LPC_LA14_P
-set_location_assignment PIN_AF17  -to "adc_data_in[1](n)"         ; ##  C19  FMC_LPC_LA14_N
-set_location_assignment PIN_AH17  -to adc_data_in[2]              ; ##  D17  FMC_LPC_LA13_P
-set_location_assignment PIN_AH16  -to "adc_data_in[2](n)"         ; ##  D18  FMC_LPC_LA13_N
-set_location_assignment PIN_AJ16  -to adc_data_in[3]              ; ##  H16  FMC_LPC_LA11_P
-set_location_assignment PIN_AK16  -to "adc_data_in[3](n)"         ; ##  H17  FMC_LPC_LA11_N
-set_location_assignment PIN_AD16  -to adc_data_in[4]              ; ##  G15  FMC_LPC_LA12_P
-set_location_assignment PIN_AD15  -to "adc_data_in[4](n)"         ; ##  G16  FMC_LPC_LA12_N
-set_location_assignment PIN_AH14  -to adc_data_in[5]              ; ##  D14  FMC_LPC_LA09_P
-set_location_assignment PIN_AH13  -to "adc_data_in[5](n)"         ; ##  D15  FMC_LPC_LA09_N
-set_location_assignment PIN_AA15  -to adc_data_in[6]              ; ##  H13  FMC_LPC_LA07_P
-set_location_assignment PIN_AA14  -to "adc_data_in[6](n)"         ; ##  H14  FMC_LPC_LA07_N
-set_location_assignment PIN_AD14  -to adc_data_in[7]              ; ##  G12  FMC_LPC_LA08_P
-set_location_assignment PIN_AD13  -to "adc_data_in[7](n)"         ; ##  G13  FMC_LPC_LA08_N
-set_location_assignment PIN_AE16  -to adc_data_in[8]              ; ##  D11  FMC_LPC_LA05_P
-set_location_assignment PIN_AE15  -to "adc_data_in[8](n)"         ; ##  D12  FMC_LPC_LA05_N
-set_location_assignment PIN_AJ15  -to adc_data_in[9]              ; ##  H10  FMC_LPC_LA04_P
-set_location_assignment PIN_AK15  -to "adc_data_in[9](n)"         ; ##  H11  FMC_LPC_LA04_N
-set_location_assignment PIN_AG12  -to adc_data_in[10]             ; ##  G09  FMC_LPC_LA03_P
-set_location_assignment PIN_AH12  -to "adc_data_in[10](n)"        ; ##  G10  FMC_LPC_LA03_N
-set_location_assignment PIN_AB12  -to adc_data_in[11]             ; ##  C10  FMC_LPC_LA06_P
-set_location_assignment PIN_AC12  -to "adc_data_in[11](n)"        ; ##  C11  FMC_LPC_LA06_N
-set_location_assignment PIN_AE12  -to adc_data_in[12]             ; ##  H07  FMC_LPC_LA02_P
-set_location_assignment PIN_AF12  -to "adc_data_in[12](n)"        ; ##  H08  FMC_LPC_LA02_N
-set_location_assignment PIN_AF15  -to adc_data_in[13]             ; ##  D08  FMC_LPC_LA01_CC_P
-set_location_assignment PIN_AG15  -to "adc_data_in[13](n)"        ; ##  D09  FMC_LPC_LA01_CC_N
+set_location_assignment PIN_AV15  -to adc_clk_in                  ; ##  G06  FMC_LPC_LA00_CC_P
+set_location_assignment PIN_AU15  -to "adc_clk_in(n)"             ; ##  G07  FMC_LPC_LA00_CC_N
+set_location_assignment PIN_AR15  -to adc_data_in[0]              ; ##  C14  FMC_LPC_LA10_P
+set_location_assignment PIN_AT15  -to "adc_data_in[0](n)"         ; ##  C15  FMC_LPC_LA10_N
+set_location_assignment PIN_AW18  -to adc_data_in[1]              ; ##  C18  FMC_LPC_LA14_P
+set_location_assignment PIN_AV18  -to "adc_data_in[1](n)"         ; ##  C19  FMC_LPC_LA14_N
+set_location_assignment PIN_AR17  -to adc_data_in[2]              ; ##  D17  FMC_LPC_LA13_P
+set_location_assignment PIN_AP17  -to "adc_data_in[2](n)"         ; ##  D18  FMC_LPC_LA13_N
+set_location_assignment PIN_AT14  -to adc_data_in[3]              ; ##  H16  FMC_LPC_LA11_P
+set_location_assignment PIN_AR14  -to "adc_data_in[3](n)"         ; ##  H17  FMC_LPC_LA11_N
+set_location_assignment PIN_AR16  -to adc_data_in[4]              ; ##  G15  FMC_LPC_LA12_P
+set_location_assignment PIN_AP16  -to "adc_data_in[4](n)"         ; ##  G16  FMC_LPC_LA12_N
+set_location_assignment PIN_AW13  -to adc_data_in[5]              ; ##  D14  FMC_LPC_LA09_P
+set_location_assignment PIN_AV13  -to "adc_data_in[5](n)"         ; ##  D15  FMC_LPC_LA09_N
+set_location_assignment PIN_AT17  -to adc_data_in[6]              ; ##  H13  FMC_LPC_LA07_P
+set_location_assignment PIN_AU17  -to "adc_data_in[6](n)"         ; ##  H14  FMC_LPC_LA07_N
+set_location_assignment PIN_AP18  -to adc_data_in[7]              ; ##  G12  FMC_LPC_LA08_P
+set_location_assignment PIN_AN19  -to "adc_data_in[7](n)"         ; ##  G13  FMC_LPC_LA08_N
+set_location_assignment PIN_AV11  -to adc_data_in[8]              ; ##  D11  FMC_LPC_LA05_P
+set_location_assignment PIN_AW11  -to "adc_data_in[8](n)"         ; ##  D12  FMC_LPC_LA05_N
+set_location_assignment PIN_AN20  -to adc_data_in[9]              ; ##  H10  FMC_LPC_LA04_P
+set_location_assignment PIN_AP19  -to "adc_data_in[9](n)"         ; ##  H11  FMC_LPC_LA04_N
+set_location_assignment PIN_AR20  -to adc_data_in[10]             ; ##  G09  FMC_LPC_LA03_P
+set_location_assignment PIN_AR19  -to "adc_data_in[10](n)"        ; ##  G10  FMC_LPC_LA03_N
+set_location_assignment PIN_AV14  -to adc_data_in[11]             ; ##  C10  FMC_LPC_LA06_P
+set_location_assignment PIN_AW14  -to "adc_data_in[11](n)"        ; ##  C11  FMC_LPC_LA06_N
+set_location_assignment PIN_AR22  -to adc_data_in[12]             ; ##  H07  FMC_LPC_LA02_P
+set_location_assignment PIN_AT22  -to "adc_data_in[12](n)"        ; ##  H08  FMC_LPC_LA02_N
+set_location_assignment PIN_AT10  -to adc_data_in[13]             ; ##  D08  FMC_LPC_LA01_CC_P
+set_location_assignment PIN_AR11  -to "adc_data_in[13](n)"        ; ##  D09  FMC_LPC_LA01_CC_N
 
 set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_in
 set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_out
@@ -125,10 +124,10 @@ set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[15]
 
 # SPI interface
 
-set_location_assignment PIN_AG16  -to spi_csn                                ; ##  H05  FMC_LPC_CLK0_M2C_N
-set_location_assignment PIN_AG17  -to spi_clk                                ; ##  H04  FMC_LPC_CLK0_M2C_P
-set_location_assignment PIN_AE18  -to spi_sdio                               ; ##  G18  FMC_LPC_LA16_P
-set_location_assignment PIN_AE17  -to spi_int                                ; ##  G19  FMC_LPC_LA16_N
+set_location_assignment PIN_AY19  -to spi_csn                                ; ##  H05  FMC_LPC_CLK0_M2C_N
+set_location_assignment PIN_AY20  -to spi_clk                                ; ##  H04  FMC_LPC_CLK0_M2C_P
+set_location_assignment PIN_AT13  -to spi_sdio                               ; ##  G18  FMC_LPC_LA16_P
+set_location_assignment PIN_AU13  -to spi_int                                ; ##  G19  FMC_LPC_LA16_N
 
 set_instance_assignment -name IO_STANDARD "1.8V" -to spi_csn
 set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clk

From 95ee7c093c9cb88ceb6c5c22ac25d7b139de7935 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 15:02:27 +0200
Subject: [PATCH 784/972] daq1/a10gx: Update system_bd port names

---
 projects/daq1/a10gx/system_top.v | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/projects/daq1/a10gx/system_top.v b/projects/daq1/a10gx/system_top.v
index 4d5791245..503691a7d 100644
--- a/projects/daq1/a10gx/system_top.v
+++ b/projects/daq1/a10gx/system_top.v
@@ -172,20 +172,20 @@ module system_top (
     .sys_spi_SCLK (spi_clk),
     .sys_spi_SS_n (spi_csn),
 
-    .spi_int(spi_int),
+    .spi_int_irq(spi_int),
 
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .dac_clk_in_n (dac_clk_in_n),
-    .dac_clk_in_p (dac_clk_in_p),
-    .dac_clk_out_n (dac_clk_out_n),
-    .dac_clk_out_p (dac_clk_out_p),
-    .dac_data_out_n (dac_data_out_n),
-    .dac_data_out_p (dac_data_out_p),
-    .dac_frame_out_n (dac_frame_out_n),
-    .dac_frame_out_p (dac_frame_out_p)
+    .axi_ad9684_device_if_adc_clk_in_n (adc_clk_in_n),
+    .axi_ad9684_device_if_adc_clk_in_p (adc_clk_in_p),
+    .axi_ad9684_device_if_adc_data_in_n (adc_data_in_n),
+    .axi_ad9684_device_if_adc_data_in_p (adc_data_in_p),
+    .axi_ad9122_device_if_dac_clk_in_n (dac_clk_in_n),
+    .axi_ad9122_device_if_dac_clk_in_p (dac_clk_in_p),
+    .axi_ad9122_device_if_dac_clk_out_n (dac_clk_out_n),
+    .axi_ad9122_device_if_dac_clk_out_p (dac_clk_out_p),
+    .axi_ad9122_device_if_dac_data_out_n (dac_data_out_n),
+    .axi_ad9122_device_if_dac_data_out_p (dac_data_out_p),
+    .axi_ad9122_device_if_dac_frame_out_n (dac_frame_out_n),
+    .axi_ad9122_device_if_dac_frame_out_p (dac_frame_out_p)
 );
 
 endmodule

From 8f94103f8bddc536f2110eb879a5ff3f5c0f4473 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 15:04:24 +0200
Subject: [PATCH 785/972] daq1/a10gx: Makefile fix

---
 projects/daq1/a10gx/Makefile | 2 --
 1 file changed, 2 deletions(-)

diff --git a/projects/daq1/a10gx/Makefile b/projects/daq1/a10gx/Makefile
index 8d7088479..722419b55 100644
--- a/projects/daq1/a10gx/Makefile
+++ b/projects/daq1/a10gx/Makefile
@@ -20,13 +20,11 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/common/ad_serdes_in.v
-M_DEPS += ../../../library/axi_ad9122/PATH
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_channel.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_core.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_hw.tcl
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_if.v
-M_DEPS += ../../../library/axi_ad9684/PATH
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684.v
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684_channel.v
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684_hw.tcl

From ad96c5e881a404f6a6277e575ab7cc74b8e2af72 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 15:18:25 +0200
Subject: [PATCH 786/972] daq3/zc706: Change the speed grade of the FPGA to 3

---
 projects/daq3/zc706/system_project.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/daq3/zc706/system_project.tcl b/projects/daq3/zc706/system_project.tcl
index cd6094f43..d36b0079c 100644
--- a/projects/daq3/zc706/system_project.tcl
+++ b/projects/daq3/zc706/system_project.tcl
@@ -14,6 +14,7 @@ adi_project_files daq3_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
+set_property part "xc7z045ffg900-3" [current_project]
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
 

From 2d7fb03b934e300e75890511d3daf9c1189a2070 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 6 Dec 2016 12:30:59 -0500
Subject: [PATCH 787/972] adrv9371x/a10gx- fix os xcvr parameters

---
 projects/adrv9371x/a10gx/system_constr.sdc   | 3 +--
 projects/adrv9371x/common/adrv9371x_qsys.tcl | 8 ++++----
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/projects/adrv9371x/a10gx/system_constr.sdc b/projects/adrv9371x/a10gx/system_constr.sdc
index e4b436327..029e779b7 100644
--- a/projects/adrv9371x/a10gx/system_constr.sdc
+++ b/projects/adrv9371x/a10gx/system_constr.sdc
@@ -12,7 +12,7 @@ set_false_path -from [get_clocks {sys_clk_100mhz}]\
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0k}]
+  -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
@@ -38,4 +38,3 @@ set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll
   -through [get_nets *altera_jesd204_rx_csr_inst*]\
   -to [get_clocks {sys_clk_100mhz}]
 
-
diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index 01df30849..c3e1428ec 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -99,10 +99,10 @@ add_instance avl_ad9371_rx_os_xcvr avl_adxcvr 1.0
 set_instance_parameter_value avl_ad9371_rx_os_xcvr {ID} {1}
 set_instance_parameter_value avl_ad9371_rx_os_xcvr {TX_OR_RX_N} {0}
 set_instance_parameter_value avl_ad9371_rx_os_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
-set_instance_parameter_value avl_ad9371_rx_os_xcvr {LANE_RATE} {10000.0}
-set_instance_parameter_value avl_ad9371_rx_os_xcvr {PLLCLK_FREQUENCY} {5000.0}
-set_instance_parameter_value avl_ad9371_rx_os_xcvr {REFCLK_FREQUENCY} {500.0}
-set_instance_parameter_value avl_ad9371_rx_os_xcvr {CORECLK_FREQUENCY} {250.0}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {LANE_RATE} {4915.2}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {PLLCLK_FREQUENCY} {2457.6}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {REFCLK_FREQUENCY} {122.88}
+set_instance_parameter_value avl_ad9371_rx_os_xcvr {CORECLK_FREQUENCY} {122.88}
 set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_LANES} {2}
 set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_CONVS} {2}
 set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_BCNT} {2}

From 801da3cb25769f8e2db883229892d465067c6147 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 6 Dec 2016 12:31:28 -0500
Subject: [PATCH 788/972] daq3/kcu105- fix timing violations

---
 projects/daq3/kcu105/system_constr.xdc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/daq3/kcu105/system_constr.xdc b/projects/daq3/kcu105/system_constr.xdc
index 2c97c6270..794e614a6 100644
--- a/projects/daq3/kcu105/system_constr.xdc
+++ b/projects/daq3/kcu105/system_constr.xdc
@@ -67,3 +67,6 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *
 set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe3_channel}]
 set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe3_channel}]
 
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+

From 8eaae98728d46265c83435dd2ae684a9e7a735b7 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 7 Dec 2016 21:35:53 +0200
Subject: [PATCH 789/972] fmcadc2: Updates

---
 projects/fmcadc2/common/fmcadc2_bd.tcl    | 14 ++++++++------
 projects/fmcadc2/vc707/system_constr.xdc  |  3 +++
 projects/fmcadc2/vc707/system_top.v       | 19 +++++++++++++++++--
 projects/fmcadc2/zc706/system_project.tcl | 17 +++++++++++++++++
 projects/fmcadc2/zc706/system_top.v       | 17 +++++++++++++++--
 5 files changed, 60 insertions(+), 10 deletions(-)

diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl
index fa6a7b7b1..cb9cdc59f 100644
--- a/projects/fmcadc2/common/fmcadc2_bd.tcl
+++ b/projects/fmcadc2/common/fmcadc2_bd.tcl
@@ -25,20 +25,21 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 
 set util_fmcadc2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc2_xcvr]
-set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc2_xcvr ;# N = 40
+set_property -dict [list CONFIG.CPLL_FBDIV {1}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {25}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc2_xcvr ;# DFE mode refclk +-200
 
 # reference clocks & resets
 
 create_bd_port -dir I rx_ref_clk_0
+create_bd_port -dir O rx_clk
 
 ad_xcvrpll  rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_*
 ad_xcvrpll  rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_*
@@ -46,6 +47,7 @@ ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_*
 ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_*
 ad_connect  sys_cpu_resetn util_fmcadc2_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_fmcadc2_xcvr/up_clk
+ad_connect  util_fmcadc2_xcvr/rx_out_clk_0 rx_clk
 
 # connections (adc)
 
diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc
index 23446dd50..ba3dc4866 100644
--- a/projects/fmcadc2/vc707/system_constr.xdc
+++ b/projects/fmcadc2/vc707/system_constr.xdc
@@ -41,3 +41,6 @@ create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
 create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_sysref_m*}]
+set_false_path -from [get_cells -hier -filter {name =~ *rx_sysref_m1_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *rx_sysref_reg     && IS_SEQUENTIAL}]
diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v
index b41326be4..f69d887c6 100644
--- a/projects/fmcadc2/vc707/system_top.v
+++ b/projects/fmcadc2/vc707/system_top.v
@@ -181,6 +181,13 @@ module system_top (
   output            spi_adf4355_le_or_clk;
   inout             spi_adf4355_ce_or_sdio;
 
+  // internal registers
+
+  reg             rx_sysref = 'd0;
+  reg             rx_sysref_m1 = 'd0;
+  reg             rx_sysref_m2 = 'd0;
+  reg             rx_sysref_m3 = 'd0;
+
   // internal signals
 
   wire    [63:0]    gpio_i;
@@ -190,7 +197,6 @@ module system_top (
   wire              spi_mosi;
   wire              spi_miso;
   wire              rx_ref_clk;
-  wire              rx_sysref;
   wire              rx_sync;
 
   // default logic
@@ -198,6 +204,14 @@ module system_top (
   assign fan_pwm = 1'b1;
   assign iic_rstn = 1'b1;
 
+  // sysref internal
+
+  always @(posedge rx_clk) begin
+    rx_sysref_m1 <= gpio_o[34];
+    rx_sysref_m2 <= rx_sysref_m1;
+    rx_sysref <= rx_sysref_m2;
+  end
+
   // instantiations
 
   IBUFDS_GTE2 i_ibufds_rx_ref_clk (
@@ -324,7 +338,8 @@ module system_top (
     .sys_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
     .uart_sin (uart_sin),
-    .uart_sout (uart_sout));
+    .uart_sout (uart_sout),
+    .rx_clk (rx_clk));
 
 endmodule
 
diff --git a/projects/fmcadc2/zc706/system_project.tcl b/projects/fmcadc2/zc706/system_project.tcl
index bd8afbab4..4f65ab5fb 100644
--- a/projects/fmcadc2/zc706/system_project.tcl
+++ b/projects/fmcadc2/zc706/system_project.tcl
@@ -8,8 +8,25 @@ adi_project_files fmcadc2_zc706 [list \
   "../common/fmcadc2_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 adi_project_run fmcadc2_zc706
+
+set ila_core [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_core]
+set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_core
+set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_core
+set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_core
+set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_core
+set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_core
+set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_core
+set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_core
+set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_core
+
+ad_connect  axi_ad9625_core/adc_clk ila_core/clk
+ad_connect  axi_ad9625_core/adc_rst ila_core/probe0
+ad_connect  axi_ad9625_core/adc_valid ila_core/probe1
+ad_connect  axi_ad9625_core/rx_ready ila_core/probe2
+ad_connect  axi_ad9625_core/adc_data ila_core/probe3
diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v
index 6cd3f5422..7d5ed8355 100644
--- a/projects/fmcadc2/zc706/system_top.v
+++ b/projects/fmcadc2/zc706/system_top.v
@@ -195,6 +195,11 @@ module system_top (
   output          spi_adf4355_le_or_clk;
   inout           spi_adf4355_ce_or_sdio;
 
+  // internal registers
+
+  reg             rx_sysref = 'd0;
+  reg             rx_sysref_d = 'd0;
+
   // internal signals
 
   wire    [63:0]  gpio_i;
@@ -209,8 +214,15 @@ module system_top (
   wire            spi1_mosi;
   wire            spi1_miso;
   wire            rx_ref_clk;
-  wire            rx_sysref;
   wire            rx_sync;
+  wire            rx_clk;
+
+  // sysref internal
+
+  always @(posedge rx_clk) begin
+    rx_sysref_d <= gpio_o[34];
+    rx_sysref <= rx_sysref_d;
+  end
 
   // instantiations
 
@@ -362,7 +374,8 @@ module system_top (
     .spi1_sdo_o (spi1_mosi),
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
-    .sys_rst (sys_rst));
+    .sys_rst (sys_rst),
+    .rx_clk (rx_clk));
 
 endmodule
 

From 3bc9df4c5163038e4fc0a8c112c079e7657cd060 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 7 Dec 2016 21:42:21 +0200
Subject: [PATCH 790/972] fmcomms5: Fixed the wornings created by TDD missing
 connections to axi_ad9361 core

---
 projects/fmcomms5/common/fmcomms5_bd.tcl  | 20 +++++++++++++++
 projects/fmcomms5/zc702/system_constr.xdc |  8 +++---
 projects/fmcomms5/zc702/system_top.v      | 30 ++++++++++++++++-------
 projects/fmcomms5/zc706/system_constr.xdc |  8 +++---
 projects/fmcomms5/zc706/system_top.v      | 30 ++++++++++++++++-------
 5 files changed, 70 insertions(+), 26 deletions(-)

diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl
index 3150ebe0c..9c05875cb 100644
--- a/projects/fmcomms5/common/fmcomms5_bd.tcl
+++ b/projects/fmcomms5/common/fmcomms5_bd.tcl
@@ -16,6 +16,11 @@ create_bd_port -dir O tx_frame_out_0_n
 create_bd_port -dir O -from 5 -to 0 tx_data_out_0_p
 create_bd_port -dir O -from 5 -to 0 tx_data_out_0_n
 
+create_bd_port -dir O enable_0
+create_bd_port -dir O txnrx_0
+create_bd_port -dir I up_enable_0
+create_bd_port -dir I up_txnrx_0
+
 # slave
 
 create_bd_port -dir I rx_clk_in_1_p
@@ -31,6 +36,11 @@ create_bd_port -dir O tx_frame_out_1_n
 create_bd_port -dir O -from 5 -to 0 tx_data_out_1_p
 create_bd_port -dir O -from 5 -to 0 tx_data_out_1_n
 
+create_bd_port -dir O enable_1
+create_bd_port -dir O txnrx_1
+create_bd_port -dir I up_enable_1
+create_bd_port -dir I up_txnrx_1
+
 create_bd_port -dir O sys_100m_resetn
 
 # instances
@@ -224,6 +234,16 @@ ad_connect  util_upack_dac/dac_data     axi_ad9361_dac_dma/fifo_rd_dout
 ad_connect  axi_ad9361_0/adc_dovf       axi_ad9361_adc_dma/fifo_wr_overflow
 ad_connect  axi_ad9361_0/dac_dunf       axi_ad9361_dac_dma/fifo_rd_underflow
 
+ad_connect  axi_ad9361_0/up_enable      up_enable_0
+ad_connect  axi_ad9361_0/up_txnrx       up_txnrx_0
+ad_connect  axi_ad9361_1/up_enable      up_enable_1
+ad_connect  axi_ad9361_1/up_txnrx       up_txnrx_1
+
+ad_connect  axi_ad9361_0/enable         enable_0
+ad_connect  axi_ad9361_0/txnrx          txnrx_0
+ad_connect  axi_ad9361_1/enable         enable_1
+ad_connect  axi_ad9361_1/txnrx          txnrx_1
+
 # address map
 
 ad_cpu_interconnect 0x79020000 axi_ad9361_0
diff --git a/projects/fmcomms5/zc702/system_constr.xdc b/projects/fmcomms5/zc702/system_constr.xdc
index 243ead1a6..914a94303 100755
--- a/projects/fmcomms5/zc702/system_constr.xdc
+++ b/projects/fmcomms5/zc702/system_constr.xdc
@@ -54,8 +54,8 @@ set_property  -dict {PACKAGE_PIN  A22   IOSTANDARD LVCMOS25}  [get_ports gpio_ct
 set_property  -dict {PACKAGE_PIN  C15   IOSTANDARD LVCMOS25}  [get_ports gpio_en_agc_0]                         ; ## G27  FMC1_LPC_LA25_P
 set_property  -dict {PACKAGE_PIN  D20   IOSTANDARD LVCMOS25}  [get_ports mcs_sync]                              ; ## C22  FMC1_LPC_LA18_CC_P
 set_property  -dict {PACKAGE_PIN  C20   IOSTANDARD LVCMOS25}  [get_ports gpio_resetb_0]                         ; ## C23  FMC1_LPC_LA18_CC_N
-set_property  -dict {PACKAGE_PIN  N15   IOSTANDARD LVCMOS25}  [get_ports gpio_enable_0]                         ; ## G18  FMC1_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN  P15   IOSTANDARD LVCMOS25}  [get_ports gpio_txnrx_0]                          ; ## G19  FMC1_LPC_LA16_N   
+set_property  -dict {PACKAGE_PIN  N15   IOSTANDARD LVCMOS25}  [get_ports enable_0]                              ; ## G18  FMC1_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  P15   IOSTANDARD LVCMOS25}  [get_ports txnrx_0]                               ; ## G19  FMC1_LPC_LA16_N
 set_property  -dict {PACKAGE_PIN  C17   IOSTANDARD LVCMOS25}  [get_ports gpio_debug_1_0]                        ; ## C26  FMC1_LPC_LA27_P            
 set_property  -dict {PACKAGE_PIN  C18   IOSTANDARD LVCMOS25}  [get_ports gpio_debug_2_0]                        ; ## C27  FMC1_LPC_LA27_N            
 set_property  -dict {PACKAGE_PIN  F18   IOSTANDARD LVCMOS25}  [get_ports gpio_calsw_1_0]                        ; ## D26  FMC1_LPC_LA26_P
@@ -121,8 +121,8 @@ set_property  -dict {PACKAGE_PIN  U6    IOSTANDARD LVCMOS25}  [get_ports gpio_ct
 set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD LVCMOS25}  [get_ports gpio_ctl_1[3]]                         ; ## H29  FMC2_LPC_LA24_N
 set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS25}  [get_ports gpio_en_agc_1]                         ; ## G27  FMC2_LPC_LA25_P
 set_property  -dict {PACKAGE_PIN  AA11  IOSTANDARD LVCMOS25}  [get_ports gpio_resetb_1]                         ; ## G30  FMC2_LPC_LA29_P
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25}  [get_ports gpio_enable_1]                         ; ## G18  FMC2_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25}  [get_ports gpio_txnrx_1]                          ; ## G19  FMC2_LPC_LA16_N        
+set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVCMOS25}  [get_ports enable_1]                              ; ## G18  FMC2_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS25}  [get_ports txnrx_1]                               ; ## G19  FMC2_LPC_LA16_N
 set_property  -dict {PACKAGE_PIN  AB2   IOSTANDARD LVCMOS25}  [get_ports gpio_debug_3_1]                        ; ## C26  FMC2_LPC_LA27_P
 set_property  -dict {PACKAGE_PIN  AB1   IOSTANDARD LVCMOS25}  [get_ports gpio_debug_4_1]                        ; ## C27  FMC2_LPC_LA27_N
 set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD LVCMOS25}  [get_ports gpio_calsw_3_1]                        ; ## D26  FMC2_LPC_LA26_P
diff --git a/projects/fmcomms5/zc702/system_top.v b/projects/fmcomms5/zc702/system_top.v
index b65ee8c61..5be51a548 100644
--- a/projects/fmcomms5/zc702/system_top.v
+++ b/projects/fmcomms5/zc702/system_top.v
@@ -94,8 +94,8 @@ module system_top (
   gpio_en_agc_0,
   mcs_sync,
   gpio_resetb_0,
-  gpio_enable_0,
-  gpio_txnrx_0,
+  enable_0,
+  txnrx_0,
   gpio_debug_1_0,
   gpio_debug_2_0,
   gpio_calsw_1_0,
@@ -119,8 +119,8 @@ module system_top (
   gpio_ctl_1,
   gpio_en_agc_1,
   gpio_resetb_1,
-  gpio_enable_1,
-  gpio_txnrx_1,
+  enable_1,
+  txnrx_1,
   gpio_debug_3_1,
   gpio_debug_4_1,
   gpio_calsw_3_1,
@@ -189,8 +189,8 @@ module system_top (
   inout           gpio_en_agc_0;
   output          mcs_sync;
   inout           gpio_resetb_0;
-  inout           gpio_enable_0;
-  inout           gpio_txnrx_0;
+  output          enable_0;
+  output          txnrx_0;
   inout           gpio_debug_1_0;
   inout           gpio_debug_2_0;
   inout           gpio_calsw_1_0;
@@ -214,8 +214,8 @@ module system_top (
   inout   [  3:0] gpio_ctl_1;
   inout           gpio_en_agc_1;
   inout           gpio_resetb_1;
-  inout           gpio_enable_1;
-  inout           gpio_txnrx_1;
+  output          enable_1;
+  output          txnrx_1;
   inout           gpio_debug_3_1;
   inout           gpio_debug_4_1;
   inout           gpio_calsw_3_1;
@@ -254,6 +254,10 @@ module system_top (
   wire            spi1_clk;
   wire            spi1_mosi;
   wire            spi1_miso;
+  wire            txnrx_0;
+  wire            enable_0;
+  wire            txnrx_1;
+  wire            enable_1;
 
   // multi-chip synchronization
 
@@ -404,7 +408,15 @@ module system_top (
     .tx_frame_out_0_n (tx_frame_out_0_n),
     .tx_frame_out_0_p (tx_frame_out_0_p),
     .tx_frame_out_1_n (tx_frame_out_1_n),
-    .tx_frame_out_1_p (tx_frame_out_1_p));
+    .tx_frame_out_1_p (tx_frame_out_1_p),
+    .txnrx_0 (txnrx_0),
+    .enable_0 (enable_0),
+    .up_enable_0 (gpio_enable_0),
+    .up_txnrx_0 (gpio_txnrx_0),
+    .txnrx_1 (txnrx_1),
+    .enable_1 (enable_1),
+    .up_enable_1 (gpio_enable_1),
+    .up_txnrx_1 (gpio_txnrx_1));
 
 endmodule
 
diff --git a/projects/fmcomms5/zc706/system_constr.xdc b/projects/fmcomms5/zc706/system_constr.xdc
index 1a6fc5f46..6dd3aa01e 100644
--- a/projects/fmcomms5/zc706/system_constr.xdc
+++ b/projects/fmcomms5/zc706/system_constr.xdc
@@ -54,8 +54,8 @@ set_property  -dict {PACKAGE_PIN  U30   IOSTANDARD LVCMOS25}  [get_ports gpio_ct
 set_property  -dict {PACKAGE_PIN  T29   IOSTANDARD LVCMOS25}  [get_ports gpio_en_agc_0]                         ; ## G27  FMC_HPC_LA25_P            
 set_property  -dict {PACKAGE_PIN  W25   IOSTANDARD LVCMOS25}  [get_ports mcs_sync]                              ; ## C22  FMC_HPC_LA18_CC_P         
 set_property  -dict {PACKAGE_PIN  W26   IOSTANDARD LVCMOS25}  [get_ports gpio_resetb_0]                         ; ## C23  FMC_HPC_LA18_CC_N         
-set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25}  [get_ports gpio_enable_0]                         ; ## G18  FMC_HPC_LA16_P            
-set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25}  [get_ports gpio_txnrx_0]                          ; ## G19  FMC_HPC_LA16_N            
+set_property  -dict {PACKAGE_PIN  AA24  IOSTANDARD LVCMOS25}  [get_ports enable_0]                              ; ## G18  FMC_HPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AB24  IOSTANDARD LVCMOS25}  [get_ports txnrx_0]                               ; ## G19  FMC_HPC_LA16_N
 set_property  -dict {PACKAGE_PIN  V28   IOSTANDARD LVCMOS25}  [get_ports gpio_debug_1_0]                        ; ## C26  FMC_HPC_LA27_P            
 set_property  -dict {PACKAGE_PIN  V29   IOSTANDARD LVCMOS25}  [get_ports gpio_debug_2_0]                        ; ## C27  FMC_HPC_LA27_N            
 set_property  -dict {PACKAGE_PIN  R28   IOSTANDARD LVCMOS25}  [get_ports gpio_calsw_1_0]                        ; ## D26  FMC_HPC_LA26_P            
@@ -121,8 +121,8 @@ set_property  -dict {PACKAGE_PIN  AF30  IOSTANDARD LVCMOS25}  [get_ports gpio_ct
 set_property  -dict {PACKAGE_PIN  AG30  IOSTANDARD LVCMOS25}  [get_ports gpio_ctl_1[3]]                         ; ## H29  FMC_LPC_LA24_N             
 set_property  -dict {PACKAGE_PIN  AF29  IOSTANDARD LVCMOS25}  [get_ports gpio_en_agc_1]                         ; ## G27  FMC_LPC_LA25_P             
 set_property  -dict {PACKAGE_PIN  AE25  IOSTANDARD LVCMOS25}  [get_ports gpio_resetb_1]                         ; ## G30  FMC_LPC_29_P         
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25}  [get_ports gpio_enable_1]                         ; ## G18  FMC_LPC_LA16_P             
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25}  [get_ports gpio_txnrx_1]                          ; ## G19  FMC_LPC_LA16_N                    
+set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVCMOS25}  [get_ports enable_1]                              ; ## G18  FMC_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVCMOS25}  [get_ports txnrx_1]                               ; ## G19  FMC_LPC_LA16_N
 set_property  -dict {PACKAGE_PIN  AJ28  IOSTANDARD LVCMOS25}  [get_ports gpio_debug_3_1]                        ; ## C26  FMC_LPC_LA27_P             
 set_property  -dict {PACKAGE_PIN  AJ29  IOSTANDARD LVCMOS25}  [get_ports gpio_debug_4_1]                        ; ## C27  FMC_LPC_LA27_N             
 set_property  -dict {PACKAGE_PIN  AJ30  IOSTANDARD LVCMOS25}  [get_ports gpio_calsw_3_1]                        ; ## D26  FMC_LPC_LA26_P             
diff --git a/projects/fmcomms5/zc706/system_top.v b/projects/fmcomms5/zc706/system_top.v
index d6766bad1..a708788d5 100644
--- a/projects/fmcomms5/zc706/system_top.v
+++ b/projects/fmcomms5/zc706/system_top.v
@@ -94,8 +94,8 @@ module system_top (
   gpio_en_agc_0,
   mcs_sync,
   gpio_resetb_0,
-  gpio_enable_0,
-  gpio_txnrx_0,
+  enable_0,
+  txnrx_0,
   gpio_debug_1_0,
   gpio_debug_2_0,
   gpio_calsw_1_0,
@@ -119,8 +119,8 @@ module system_top (
   gpio_ctl_1,
   gpio_en_agc_1,
   gpio_resetb_1,
-  gpio_enable_1,
-  gpio_txnrx_1,
+  enable_1,
+  txnrx_1,
   gpio_debug_3_1,
   gpio_debug_4_1,
   gpio_calsw_3_1,
@@ -189,8 +189,8 @@ module system_top (
   inout           gpio_en_agc_0;
   output          mcs_sync;
   inout           gpio_resetb_0;
-  inout           gpio_enable_0;
-  inout           gpio_txnrx_0;
+  output          enable_0;
+  output          txnrx_0;
   inout           gpio_debug_1_0;
   inout           gpio_debug_2_0;
   inout           gpio_calsw_1_0;
@@ -214,8 +214,8 @@ module system_top (
   inout   [  3:0] gpio_ctl_1;
   inout           gpio_en_agc_1;
   inout           gpio_resetb_1;
-  inout           gpio_enable_1;
-  inout           gpio_txnrx_1;
+  output          enable_1;
+  output          txnrx_1;
   inout           gpio_debug_3_1;
   inout           gpio_debug_4_1;
   inout           gpio_calsw_3_1;
@@ -255,6 +255,10 @@ module system_top (
   wire            spi1_clk;
   wire            spi1_mosi;
   wire            spi1_miso;
+  wire            txnrx_0;
+  wire            enable_0;
+  wire            txnrx_1;
+  wire            enable_1;
 
   // multi-chip synchronization
 
@@ -406,7 +410,15 @@ module system_top (
     .tx_frame_out_0_n (tx_frame_out_0_n),
     .tx_frame_out_0_p (tx_frame_out_0_p),
     .tx_frame_out_1_n (tx_frame_out_1_n),
-    .tx_frame_out_1_p (tx_frame_out_1_p));
+    .tx_frame_out_1_p (tx_frame_out_1_p),
+    .txnrx_0 (txnrx_0),
+    .enable_0 (enable_0),
+    .up_enable_0 (gpio_enable_0),
+    .up_txnrx_0 (gpio_txnrx_0),
+    .txnrx_1 (txnrx_1),
+    .enable_1 (enable_1),
+    .up_enable_1 (gpio_enable_1),
+    .up_txnrx_1 (gpio_txnrx_1));
 
 endmodule
 

From fb287d0178e9ea82cde2723cf2585a77e2743f31 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 8 Dec 2016 09:32:22 -0500
Subject: [PATCH 791/972] kcu105- updates to match xilinx trd

---
 projects/common/kcu105/kcu105_system_bd.tcl | 147 +++++++++-----------
 1 file changed, 64 insertions(+), 83 deletions(-)

diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl
index 48a69d2b8..28a967dec 100644
--- a/projects/common/kcu105/kcu105_system_bd.tcl
+++ b/projects/common/kcu105/kcu105_system_bd.tcl
@@ -3,8 +3,8 @@
 # interface ports
 
 create_bd_port -dir I -type rst sys_rst
-create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4
 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4
 
 create_bd_port -dir I phy_sd
 create_bd_port -dir O -type rst phy_rst_n
@@ -78,13 +78,12 @@ set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
 
 set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
 
-# instance: ddr (mig)
+# instance: ddr4
 
-set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.0 axi_ddr_cntrl ]
+set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.0 axi_ddr_cntrl]
 set_property -dict [list CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_300}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_ddr_cntrl
-set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl
 
 set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen]
@@ -92,15 +91,10 @@ set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_r
 # instance: default peripherals
 
 set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet]
-set_property -dict [list CONFIG.SupportLevel {1}] $axi_ethernet
 set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethernet
 set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet
 set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet
-set_property -dict [list CONFIG.lvdsclkrate {625}] $axi_ethernet
-set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
-set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
-set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet
-set_property -dict [list CONFIG.RXMEM {8k}] $axi_ethernet
+set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet
 
 set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
 set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
@@ -133,94 +127,64 @@ set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
 set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
 set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
 
-# connections
+# ddr4
 
-ad_connect  sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst
+ad_connect  sys_rst axi_ddr_cntrl/sys_rst
+ad_connect  sys_clk axi_ddr_cntrl/C0_SYS_CLK
+ad_connect  c0_ddr4 axi_ddr_cntrl/C0_DDR4
+ad_connect  axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in
+ad_connect  axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in
+ad_connect  sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk
+ad_connect  sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk
+ad_connect  sys_cpu_clk axi_ddr_cntrl/addn_ui_clkout1
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn
+ad_connect  sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn
+ad_connect  sys_200m_clk axi_ddr_cntrl/addn_ui_clkout2
+
+# microblaze
+
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_mb/Clk
+ad_connect  sys_cpu_clk sys_dlmb/LMB_Clk
+ad_connect  sys_cpu_clk sys_ilmb/LMB_Clk
+ad_connect  sys_cpu_clk sys_dlmb_cntlr/LMB_Clk
+ad_connect  sys_cpu_clk sys_ilmb_cntlr/LMB_Clk
 ad_connect  sys_rstgen/mb_reset sys_mb/Reset
 ad_connect  sys_rstgen/bus_struct_reset sys_dlmb/SYS_Rst
 ad_connect  sys_rstgen/bus_struct_reset sys_ilmb/SYS_Rst
 ad_connect  sys_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst
 ad_connect  sys_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst
-
-# microblaze local memory
-
 ad_connect  sys_mb/DLMB sys_dlmb/LMB_M
 ad_connect  sys_mb/ILMB sys_ilmb/LMB_M
 ad_connect  sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB
 ad_connect  sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB
 ad_connect  sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA
 ad_connect  sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB
-
-# microblaze debug & interrupt
-
+ad_connect  sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst
 ad_connect  sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG
 ad_connect  axi_intc/interrupt sys_mb/INTERRUPT
 ad_connect  axi_intc/intr sys_concat_intc/dout
 
-# defaults (peripherals)
-
-ad_connect  sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk
-ad_connect  sys_cpu_clk axi_ddr_cntrl/addn_ui_clkout1
-ad_connect  sys_200m_clk axi_ddr_cntrl/addn_ui_clkout2
-ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
-ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
-ad_connect  sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn
-ad_connect  sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn
-
-ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
-ad_connect  sys_cpu_clk sys_mb/Clk
-ad_connect  sys_cpu_clk sys_dlmb/LMB_Clk
-ad_connect  sys_cpu_clk sys_ilmb/LMB_Clk
-ad_connect  sys_cpu_clk sys_dlmb_cntlr/LMB_Clk
-ad_connect  sys_cpu_clk sys_ilmb_cntlr/LMB_Clk
-ad_connect  sys_cpu_clk axi_ethernet/axis_clk
-
-# defaults (interrupts)
-
-ad_connect  sys_concat_intc/In0 axi_timer/interrupt
-ad_connect  sys_concat_intc/In1 axi_ethernet/interrupt
-ad_connect  sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut
-ad_connect  sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut
-ad_connect  sys_concat_intc/In4 axi_uart/interrupt
-ad_connect  sys_concat_intc/In5 mb_intr_05
-ad_connect  sys_concat_intc/In6 mb_intr_06
-ad_connect  sys_concat_intc/In7 mb_intr_07
-ad_connect  sys_concat_intc/In8 mb_intr_08
-ad_connect  sys_concat_intc/In9 axi_iic_main/iic2intc_irpt
-ad_connect  sys_concat_intc/In10 axi_spi/ip2intc_irpt
-ad_connect  sys_concat_intc/In11 axi_gpio/ip2intc_irpt
-ad_connect  sys_concat_intc/In12 mb_intr_12
-ad_connect  sys_concat_intc/In13 mb_intr_13
-ad_connect  sys_concat_intc/In14 mb_intr_14
-ad_connect  sys_concat_intc/In15 mb_intr_15
-
-# defaults (ddr)
-
-ad_connect  sys_rst axi_ddr_cntrl/sys_rst
-ad_connect  c0_ddr4 axi_ddr_cntrl/C0_DDR4
-ad_connect  sys_clk axi_ddr_cntrl/C0_SYS_CLK
-
-ad_connect  axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in
-ad_connect  axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in
-ad_connect  sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk
-
-# defaults (ethernet)
+# ethernet
 
+ad_connect  sgmii axi_ethernet/sgmii
 ad_connect  phy_clk axi_ethernet/lvds_clk
 ad_connect  mdio axi_ethernet/mdio
-ad_connect  sgmii axi_ethernet/sgmii
+ad_connect  phy_sd axi_ethernet/signal_detect
+ad_connect  axi_ethernet/phy_rst_n phy_rst_n
+ad_connect  sys_cpu_clk axi_ethernet/axis_clk
 ad_connect  axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S
 ad_connect  axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL
 ad_connect  axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM
 ad_connect  axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS
-ad_connect  phy_sd axi_ethernet/signal_detect
-ad_connect  sys_cpu_resetn phy_rst_n
 ad_connect  axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n
 ad_connect  axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n
 ad_connect  axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n
 ad_connect  axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n
 
-# defaults (misc)
+# iic, spi and gpio
 
 ad_connect  iic_main axi_iic_main/iic
 ad_connect  uart_sin axi_uart/rx
@@ -240,7 +204,26 @@ ad_connect  gpio1_o axi_gpio/gpio2_io_o
 ad_connect  gpio1_t axi_gpio/gpio2_io_t
 ad_connect  sys_cpu_clk axi_spi/ext_spi_clk
 
-# defaults (interconnect - processor)
+# interrupts
+
+ad_connect  sys_concat_intc/In0 axi_timer/interrupt
+ad_connect  sys_concat_intc/In1 axi_ethernet/interrupt
+ad_connect  sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut
+ad_connect  sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut
+ad_connect  sys_concat_intc/In4 axi_uart/interrupt
+ad_connect  sys_concat_intc/In5 mb_intr_05
+ad_connect  sys_concat_intc/In6 mb_intr_06
+ad_connect  sys_concat_intc/In7 mb_intr_07
+ad_connect  sys_concat_intc/In8 mb_intr_08
+ad_connect  sys_concat_intc/In9 axi_iic_main/iic2intc_irpt
+ad_connect  sys_concat_intc/In10 axi_spi/ip2intc_irpt
+ad_connect  sys_concat_intc/In11 axi_gpio/ip2intc_irpt
+ad_connect  sys_concat_intc/In12 mb_intr_12
+ad_connect  sys_concat_intc/In13 mb_intr_13
+ad_connect  sys_concat_intc/In14 mb_intr_14
+ad_connect  sys_concat_intc/In15 mb_intr_15
+
+# interconnect - processor
 
 ad_cpu_interconnect 0x41400000 sys_mb_debug
 ad_cpu_interconnect 0x40E00000 axi_ethernet
@@ -252,29 +235,27 @@ ad_cpu_interconnect 0x41600000 axi_iic_main
 ad_cpu_interconnect 0x40000000 axi_gpio
 ad_cpu_interconnect 0x44A70000 axi_spi
 
-create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect
-set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect]
-set_property CONFIG.NUM_SI {1} [get_bd_cells axi_ddr_interconnect]
+# interconnect - memory
 
-ad_connect axi_ddr_interconnect/M00_AXI axi_ddr_cntrl/C0_DDR4_S_AXI
-ad_connect sys_mem_clk axi_ddr_interconnect/ACLK
-ad_connect sys_mem_clk axi_ddr_interconnect/M00_ACLK
-ad_connect sys_mem_resetn axi_ddr_interconnect/ARESETN
-ad_connect sys_mem_resetn axi_ddr_interconnect/M00_ARESETN
-ad_connect sys_cpu_resetn axi_ddr_interconnect/S00_ARESETN
+#ad_connect sys_mem_resetn axi_ddr_interconnect/ARESETN
+#ad_connect sys_mem_resetn axi_ddr_interconnect/M00_ARESETN
 
-ad_mem_hp0_interconnect sys_cpu_clk axi_ddr_interconnect/S00_AXI
+ad_mem_hp0_interconnect sys_mem_clk axi_ddr_cntrl/C0_DDR4_S_AXI
 ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_DC
 ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC
 ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG
 ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S
 ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM
 
+ad_disconnect  sys_mem_clk axi_mem_interconnect/ACLK
+ad_disconnect  sys_mem_resetn axi_mem_interconnect/ARESETN
+
+ad_connect  sys_cpu_clk axi_mem_interconnect/ACLK
+ad_connect  sys_cpu_resetn axi_mem_interconnect/ARESETN
+
 create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \
   [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr
 create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \
   [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr
 
 
-
-

From 252c67ceff5442fe1c742b062c113fd9900cfbda Mon Sep 17 00:00:00 2001
From: Istvan <istvan.csomortani@analog.com>
Date: Thu, 8 Dec 2016 16:52:36 +0200
Subject: [PATCH 792/972] fmcomms6: Delete project

This project will not be supported in further releases.
---
 projects/Makefile                          |   3 -
 projects/fmcomms6/Makefile                 |  21 --
 projects/fmcomms6/common/fmcomms6_bd.tcl   |  88 -------
 projects/fmcomms6/common/fmcomms6_spi.v    | 109 ---------
 projects/fmcomms6/zc706/Makefile           |  79 -------
 projects/fmcomms6/zc706/system_bd.tcl      |   4 -
 projects/fmcomms6/zc706/system_constr.xdc  |  57 -----
 projects/fmcomms6/zc706/system_project.tcl |  21 --
 projects/fmcomms6/zc706/system_top.v       | 263 ---------------------
 9 files changed, 645 deletions(-)
 delete mode 100644 projects/fmcomms6/Makefile
 delete mode 100644 projects/fmcomms6/common/fmcomms6_bd.tcl
 delete mode 100644 projects/fmcomms6/common/fmcomms6_spi.v
 delete mode 100644 projects/fmcomms6/zc706/Makefile
 delete mode 100644 projects/fmcomms6/zc706/system_bd.tcl
 delete mode 100644 projects/fmcomms6/zc706/system_constr.xdc
 delete mode 100644 projects/fmcomms6/zc706/system_project.tcl
 delete mode 100644 projects/fmcomms6/zc706/system_top.v

diff --git a/projects/Makefile b/projects/Makefile
index c4d8c5cb7..5b6e63562 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -32,7 +32,6 @@ all:
 	-make -C fmcomms11 all
 	-make -C fmcomms2 all
 	-make -C fmcomms5 all
-	-make -C fmcomms6 all
 	-make -C fmcomms7 all
 	-make -C imageon all
 	-make -C motcon2_fmc all
@@ -70,7 +69,6 @@ clean:
 	make -C fmcomms11 clean
 	make -C fmcomms2 clean
 	make -C fmcomms5 clean
-	make -C fmcomms6 clean
 	make -C fmcomms7 clean
 	make -C imageon clean
 	make -C motcon2_fmc clean
@@ -108,7 +106,6 @@ clean-all:
 	make -C fmcomms11 clean-all
 	make -C fmcomms2 clean-all
 	make -C fmcomms5 clean-all
-	make -C fmcomms6 clean-all
 	make -C fmcomms7 clean-all
 	make -C imageon clean-all
 	make -C motcon2_fmc clean-all
diff --git a/projects/fmcomms6/Makefile b/projects/fmcomms6/Makefile
deleted file mode 100644
index 5b866a1ac..000000000
--- a/projects/fmcomms6/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-.PHONY: all clean clean-all 
-all:
-	-make -C zc706 all
-
-
-clean: 
-	make -C zc706 clean
-
-
-clean-all:
-	make -C zc706 clean-all
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms6/common/fmcomms6_bd.tcl b/projects/fmcomms6/common/fmcomms6_bd.tcl
deleted file mode 100644
index f5349d378..000000000
--- a/projects/fmcomms6/common/fmcomms6_bd.tcl
+++ /dev/null
@@ -1,88 +0,0 @@
-
-# adc interface
-
-create_bd_port -dir I adc_clk_in_p
-create_bd_port -dir I adc_clk_in_n
-create_bd_port -dir I adc_or_in_p
-create_bd_port -dir I adc_or_in_n
-create_bd_port -dir I -from 15 -to 0 adc_data_in_p
-create_bd_port -dir I -from 15 -to 0 adc_data_in_n
-
-# adc peripherals
-
-set axi_ad9652 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9652:1.0 axi_ad9652]
-
-set axi_ad9652_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9652_dma]
-set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9652_dma
-set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9652_dma
-set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9652_dma
-set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9652_dma
-set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma
-set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9652_dma
-
-set axi_ad9652_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 axi_ad9652_adc_fifo]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9652_adc_fifo
-set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $axi_ad9652_adc_fifo
-set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $axi_ad9652_adc_fifo
-set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $axi_ad9652_adc_fifo
-
-set data_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack]
-set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack
-
-# connections (adc)
-
-ad_connect  adc_clk_in_p  axi_ad9652/adc_clk_in_p
-ad_connect  adc_clk_in_n  axi_ad9652/adc_clk_in_n
-ad_connect  adc_or_in_p   axi_ad9652/adc_or_in_p
-ad_connect  adc_or_in_n   axi_ad9652/adc_or_in_n
-ad_connect  adc_data_in_p axi_ad9652/adc_data_in_p
-ad_connect  adc_data_in_n axi_ad9652/adc_data_in_n
-
-ad_connect  axi_ad9652/adc_clk axi_ad9652_adc_fifo/din_clk
-ad_connect  axi_ad9652/adc_rst axi_ad9652_adc_fifo/din_rst
-
-ad_connect  sys_200m_clk axi_ad9652/delay_clk
-ad_connect  sys_200m_clk axi_ad9652_dma/fifo_wr_clk
-
-ad_connect  sys_200m_clk  data_pack/adc_clk
-ad_connect  sys_cpu_reset data_pack/adc_rst
-
-ad_connect  axi_ad9652/adc_enable_0 axi_ad9652_adc_fifo/din_enable_0
-ad_connect  axi_ad9652/adc_valid_0  axi_ad9652_adc_fifo/din_valid_0
-ad_connect  axi_ad9652/adc_data_0   axi_ad9652_adc_fifo/din_data_0
-ad_connect  axi_ad9652/adc_enable_1 axi_ad9652_adc_fifo/din_enable_1
-ad_connect  axi_ad9652/adc_valid_1  axi_ad9652_adc_fifo/din_valid_1
-ad_connect  axi_ad9652/adc_data_1   axi_ad9652_adc_fifo/din_data_1
-
-ad_connect  sys_200m_clk    axi_ad9652_adc_fifo/dout_clk
-ad_connect  sys_cpu_resetn  axi_ad9652_adc_fifo/dout_rstn
-
-ad_connect  axi_ad9652_adc_fifo/dout_valid_0   data_pack/adc_valid_0
-ad_connect  axi_ad9652_adc_fifo/dout_enable_0  data_pack/adc_enable_0
-ad_connect  axi_ad9652_adc_fifo/dout_data_0    data_pack/adc_data_0
-ad_connect  axi_ad9652_adc_fifo/dout_valid_1   data_pack/adc_valid_1
-ad_connect  axi_ad9652_adc_fifo/dout_enable_1  data_pack/adc_enable_1
-ad_connect  axi_ad9652_adc_fifo/dout_data_1    data_pack/adc_data_1
-
-ad_connect  axi_ad9652_adc_fifo/din_ovf    axi_ad9652/adc_dovf
-
-ad_connect  data_pack/adc_valid               axi_ad9652_dma/fifo_wr_en
-ad_connect  data_pack/adc_sync                axi_ad9652_dma/fifo_wr_sync
-ad_connect  data_pack/adc_data                axi_ad9652_dma/fifo_wr_din
-ad_connect  axi_ad9652_adc_fifo/dout_ovf      axi_ad9652_dma/fifo_wr_overflow
-
-# interconnect (cpu)
-
-ad_cpu_interconnect 0x79020000 axi_ad9652
-ad_cpu_interconnect 0x7c420000 axi_ad9652_dma
-
-# interconnect (mem/adc)
-
-ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
-ad_mem_hp1_interconnect sys_200m_clk axi_ad9652_dma/m_dest_axi
-ad_connect  sys_cpu_resetn axi_ad9652_dma/m_dest_axi_aresetn
-
-# interrupts
-
-ad_cpu_interrupt ps-13 mb-13 axi_ad9652_dma/irq
-
diff --git a/projects/fmcomms6/common/fmcomms6_spi.v b/projects/fmcomms6/common/fmcomms6_spi.v
deleted file mode 100644
index bc1fd2cd1..000000000
--- a/projects/fmcomms6/common/fmcomms6_spi.v
+++ /dev/null
@@ -1,109 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module fmcomms6_spi (
-
-  spi_csn,
-  spi_clk,
-  spi_mosi,
-  spi_miso,
-
-  spi_sdio);
-
-  // 4 wire
-
-  input   [ 2:0]  spi_csn;
-  input           spi_clk;
-  input           spi_mosi;
-  output          spi_miso;
-
-  // 3 wire
-
-  inout           spi_sdio;
-
-  // internal registers
-
-  reg     [ 5:0]  spi_count = 'd0;
-  reg             spi_rd_wr_n = 'd0;
-  reg             spi_enable = 'd0;
-
-  // internal signals
-
-  wire            spi_csn_s;
-  wire            spi_enable_s;
-
-  // check on rising edge and change on falling edge
-
-  assign spi_csn_s = & spi_csn;
-  assign spi_enable_s = spi_enable & ~spi_csn_s;
-
-  always @(posedge spi_clk or posedge spi_csn_s) begin
-    if (spi_csn_s == 1'b1) begin
-      spi_count <= 6'd0;
-      spi_rd_wr_n <= 1'd0;
-    end else begin
-      spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
-      if (spi_count == 6'd0) begin
-        spi_rd_wr_n <= spi_mosi;
-      end
-    end
-  end
-
-  always @(negedge spi_clk or posedge spi_csn_s) begin
-    if (spi_csn_s == 1'b1) begin
-      spi_enable <= 1'b0;
-    end else begin
-      if ((spi_count == 6'd16) && (spi_csn[2] == 1'b1)) begin
-        spi_enable <= spi_rd_wr_n;
-      end
-    end
-  end
-
-  // io butter
-
-  IOBUF i_iobuf_sdio (
-    .T (spi_enable_s),
-    .I (spi_mosi),
-    .O (spi_miso),
-    .IO (spi_sdio));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/projects/fmcomms6/zc706/Makefile b/projects/fmcomms6/zc706/Makefile
deleted file mode 100644
index e84934f94..000000000
--- a/projects/fmcomms6/zc706/Makefile
+++ /dev/null
@@ -1,79 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../common/fmcomms6_spi.v
-M_DEPS += ../common/fmcomms6_bd.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_constr.xdc
-M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9652/axi_ad9652.xpr
-M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib fmcomms6_zc706.sdk/system_top.hdf
-
-
-clean: 
-	rm -rf $(M_FLIST)
-
-
-clean-all:clean
-	make -C ../../../library/axi_ad9652 clean
-	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_wfifo clean
-
-
-fmcomms6_zc706.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms6_zc706_vivado.log 2>&1
-
-
-lib:
-	make -C ../../../library/axi_ad9652
-	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_cpack
-	make -C ../../../library/util_wfifo
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms6/zc706/system_bd.tcl b/projects/fmcomms6/zc706/system_bd.tcl
deleted file mode 100644
index 8f853b9cb..000000000
--- a/projects/fmcomms6/zc706/system_bd.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-
-source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source ../common/fmcomms6_bd.tcl
-
diff --git a/projects/fmcomms6/zc706/system_constr.xdc b/projects/fmcomms6/zc706/system_constr.xdc
deleted file mode 100644
index e310f9cdb..000000000
--- a/projects/fmcomms6/zc706/system_constr.xdc
+++ /dev/null
@@ -1,57 +0,0 @@
-
-
-# adc 
-
-set_property  -dict {PACKAGE_PIN  AE13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p]       ; ## G06  FMC_LPC_LA00_CC_P       
-set_property  -dict {PACKAGE_PIN  AF13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n]       ; ## G07  FMC_LPC_LA00_CC_N       
-set_property  -dict {PACKAGE_PIN  AH26  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p]        ; ## H22  FMC_LPC_LA19_P          
-set_property  -dict {PACKAGE_PIN  AH27  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n]        ; ## H23  FMC_LPC_LA19_N          
-set_property  -dict {PACKAGE_PIN  AF15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]   ; ## D08  FMC_LPC_LA01_CC_P       
-set_property  -dict {PACKAGE_PIN  AG15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]   ; ## D09  FMC_LPC_LA01_CC_N       
-set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]   ; ## H07  FMC_LPC_LA02_P          
-set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]]   ; ## H08  FMC_LPC_LA02_N          
-set_property  -dict {PACKAGE_PIN  AG12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]]   ; ## G09  FMC_LPC_LA03_P          
-set_property  -dict {PACKAGE_PIN  AH12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]]   ; ## G10  FMC_LPC_LA03_N          
-set_property  -dict {PACKAGE_PIN  AJ15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]]   ; ## H10  FMC_LPC_LA04_P          
-set_property  -dict {PACKAGE_PIN  AK15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]]   ; ## H11  FMC_LPC_LA04_N          
-set_property  -dict {PACKAGE_PIN  AE16  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]]   ; ## D11  FMC_LPC_LA05_P          
-set_property  -dict {PACKAGE_PIN  AE15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]]   ; ## D12  FMC_LPC_LA05_N          
-set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]]   ; ## C10  FMC_LPC_LA06_P          
-set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]]   ; ## C11  FMC_LPC_LA06_N          
-set_property  -dict {PACKAGE_PIN  AA15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]]   ; ## H13  FMC_LPC_LA07_P          
-set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]]   ; ## H14  FMC_LPC_LA07_N          
-set_property  -dict {PACKAGE_PIN  AD14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]   ; ## G12  FMC_LPC_LA08_P          
-set_property  -dict {PACKAGE_PIN  AD13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]   ; ## G13  FMC_LPC_LA08_N          
-set_property  -dict {PACKAGE_PIN  AH14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]]   ; ## D14  FMC_LPC_LA09_P          
-set_property  -dict {PACKAGE_PIN  AH13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]]   ; ## D15  FMC_LPC_LA09_N          
-set_property  -dict {PACKAGE_PIN  AC14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]]   ; ## C14  FMC_LPC_LA10_P          
-set_property  -dict {PACKAGE_PIN  AC13  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]]   ; ## C15  FMC_LPC_LA10_N          
-set_property  -dict {PACKAGE_PIN  AJ16  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]]  ; ## H16  FMC_LPC_LA11_P          
-set_property  -dict {PACKAGE_PIN  AK16  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]]  ; ## H17  FMC_LPC_LA11_N          
-set_property  -dict {PACKAGE_PIN  AD16  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]]  ; ## G15  FMC_LPC_LA12_P          
-set_property  -dict {PACKAGE_PIN  AD15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]]  ; ## G16  FMC_LPC_LA12_N          
-set_property  -dict {PACKAGE_PIN  AH17  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]]  ; ## D17  FMC_LPC_LA13_P          
-set_property  -dict {PACKAGE_PIN  AH16  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]]  ; ## D18  FMC_LPC_LA13_N          
-set_property  -dict {PACKAGE_PIN  AF18  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]  ; ## C18  FMC_LPC_LA14_P          
-set_property  -dict {PACKAGE_PIN  AF17  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]  ; ## C19  FMC_LPC_LA14_N          
-set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[14]]  ; ## H19  FMC_LPC_LA15_P          
-set_property  -dict {PACKAGE_PIN  AB14  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[14]]  ; ## H20  FMC_LPC_LA15_N          
-set_property  -dict {PACKAGE_PIN  AE18  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[15]]  ; ## G18  FMC_LPC_LA16_P          
-set_property  -dict {PACKAGE_PIN  AE17  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[15]]  ; ## G19  FMC_LPC_LA16_N          
-
-# spi
-
-set_property  -dict {PACKAGE_PIN  AK27  IOSTANDARD LVCMOS25} [get_ports spi_ad9517_csn]                   ; ## G24  FMC_LPC_LA22_P             
-set_property  -dict {PACKAGE_PIN  AH28  IOSTANDARD LVCMOS25} [get_ports spi_ad9652_csn]                   ; ## H25  FMC_LPC_LA21_P             
-set_property  -dict {PACKAGE_PIN  AH29  IOSTANDARD LVCMOS25} [get_ports spi_adf4351_csn]                  ; ## H26  FMC_LPC_LA21_N             
-set_property  -dict {PACKAGE_PIN  AJ26  IOSTANDARD LVCMOS25} [get_ports spi_clk]                          ; ## D23  FMC_LPC_LA23_P             
-set_property  -dict {PACKAGE_PIN  AK28  IOSTANDARD LVCMOS25} [get_ports spi_sdio]                         ; ## G25  FMC_LPC_LA22_N             
-
-# gpio
-
-set_property  -dict {PACKAGE_PIN  AK26  IOSTANDARD LVCMOS25} [get_ports adf4351_ld]                       ; ## D24  FMC_LPC_LA23_N          
-
-# clocks
-
-create_clock -name adc_clk_in   -period  3.22 [get_ports adc_clk_in_p]
-
diff --git a/projects/fmcomms6/zc706/system_project.tcl b/projects/fmcomms6/zc706/system_project.tcl
deleted file mode 100644
index 0ebcebd0d..000000000
--- a/projects/fmcomms6/zc706/system_project.tcl
+++ /dev/null
@@ -1,21 +0,0 @@
-
-
-
-source ../../scripts/adi_env.tcl
-source $ad_hdl_dir/projects/scripts/adi_project.tcl
-source $ad_hdl_dir/projects/scripts/adi_board.tcl
-
-adi_project_create fmcomms6_zc706
-adi_project_files fmcomms6_zc706 [list \
-  "../common/fmcomms6_spi.v" \
-  "system_top.v" \
-  "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run fmcomms6_zc706
-
-
diff --git a/projects/fmcomms6/zc706/system_top.v b/projects/fmcomms6/zc706/system_top.v
deleted file mode 100644
index 4c2565856..000000000
--- a/projects/fmcomms6/zc706/system_top.v
+++ /dev/null
@@ -1,263 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module system_top (
-
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
-
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
-
-  gpio_bd,
-
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
-
-  spdif,
-
-  iic_scl,
-  iic_sda,
-
-  adc_clk_in_p,
-  adc_clk_in_n,
-  adc_or_in_p,
-  adc_or_in_n,
-  adc_data_in_p,
-  adc_data_in_n,
-
-  spi_adf4351_csn,
-  spi_ad9652_csn,
-  spi_ad9517_csn,
-  spi_clk,
-  spi_sdio,
-  adf4351_ld);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout   [14:0]  gpio_bd;
-
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [23:0]  hdmi_data;
-
-  output          spdif;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  input           adc_clk_in_p;
-  input           adc_clk_in_n;
-  input           adc_or_in_p;
-  input           adc_or_in_n;
-  input   [15:0]  adc_data_in_p;
-  input   [15:0]  adc_data_in_n;
-
-  output          spi_adf4351_csn;
-  output          spi_ad9652_csn;
-  output          spi_ad9517_csn;
-  output          spi_clk;
-  inout           spi_sdio;
-  inout           adf4351_ld;
-
-  // internal signals
-
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire    [ 2:0]  spi0_csn;
-  wire            spi0_clk;
-  wire            spi0_mosi;
-  wire            spi0_miso;
-  wire    [ 2:0]  spi1_csn;
-  wire            spi1_clk;
-  wire            spi1_mosi;
-  wire            spi1_miso;
-
-  assign gpio_i[63:33] = gpio_o[63:33];
-  assign gpio_i[31:15] = gpio_o[31:15];
-
-  // spi
-
-  assign spi_clk = spi0_clk;
-  assign spi_ad9517_csn = spi0_csn[0];
-  assign spi_ad9652_csn = spi0_csn[1];
-  assign spi_adf4351_csn = spi0_csn[2];
-
-  // instantiations
-
-  fmcomms6_spi i_spi (
-    .spi_csn (spi0_csn),
-    .spi_clk (spi0_clk),
-    .spi_mosi (spi0_mosi),
-    .spi_miso (spi0_miso),
-    .spi_sdio (spi_sdio));
-
-  ad_iobuf #(.DATA_WIDTH(1)) i_iobuf (
-    .dio_t (gpio_t[32]),
-    .dio_i (gpio_o[32]),
-    .dio_o (gpio_i[32]),
-    .dio_p (adf4351_ld));
-
-  ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
-    .dio_t (gpio_t[14:0]),
-    .dio_i (gpio_o[14:0]),
-    .dio_o (gpio_i[14:0]),
-    .dio_p (gpio_bd));
-
-  system_wrapper i_system_wrapper (
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .adc_or_in_n (adc_or_in_n),
-    .adc_or_in_p (adc_or_in_p),
-    .ddr_addr (ddr_addr),
-    .ddr_ba (ddr_ba),
-    .ddr_cas_n (ddr_cas_n),
-    .ddr_ck_n (ddr_ck_n),
-    .ddr_ck_p (ddr_ck_p),
-    .ddr_cke (ddr_cke),
-    .ddr_cs_n (ddr_cs_n),
-    .ddr_dm (ddr_dm),
-    .ddr_dq (ddr_dq),
-    .ddr_dqs_n (ddr_dqs_n),
-    .ddr_dqs_p (ddr_dqs_p),
-    .ddr_odt (ddr_odt),
-    .ddr_ras_n (ddr_ras_n),
-    .ddr_reset_n (ddr_reset_n),
-    .ddr_we_n (ddr_we_n),
-    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
-    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
-    .fixed_io_mio (fixed_io_mio),
-    .fixed_io_ps_clk (fixed_io_ps_clk),
-    .fixed_io_ps_porb (fixed_io_ps_porb),
-    .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gpio_i (gpio_i),
-    .gpio_o (gpio_o),
-    .gpio_t (gpio_t),
-    .hdmi_data (hdmi_data),
-    .hdmi_data_e (hdmi_data_e),
-    .hdmi_hsync (hdmi_hsync),
-    .hdmi_out_clk (hdmi_out_clk),
-    .hdmi_vsync (hdmi_vsync),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
-    .ps_intr_00 (1'b0),
-    .ps_intr_01 (1'b0),
-    .ps_intr_02 (1'b0),
-    .ps_intr_03 (1'b0),
-    .ps_intr_04 (1'b0),
-    .ps_intr_05 (1'b0),
-    .ps_intr_06 (1'b0),
-    .ps_intr_07 (1'b0),
-    .ps_intr_08 (1'b0),
-    .ps_intr_09 (1'b0),
-    .ps_intr_10 (1'b0),
-    .ps_intr_11 (1'b0),
-    .ps_intr_12 (1'b0),
-    .spdif (spdif),
-    .spi0_clk_i (spi0_clk),
-    .spi0_clk_o (spi0_clk),
-    .spi0_csn_0_o (spi0_csn[0]),
-    .spi0_csn_1_o (spi0_csn[1]),
-    .spi0_csn_2_o (spi0_csn[2]),
-    .spi0_csn_i (1'b1),
-    .spi0_sdi_i (spi0_miso),
-    .spi0_sdo_i (spi0_mosi),
-    .spi0_sdo_o (spi0_mosi),
-    .spi1_clk_i (spi1_clk),
-    .spi1_clk_o (spi1_clk),
-    .spi1_csn_0_o (spi1_csn[0]),
-    .spi1_csn_1_o (spi1_csn[1]),
-    .spi1_csn_2_o (spi1_csn[2]),
-    .spi1_csn_i (1'b1),
-    .spi1_sdi_i (1'b1),
-    .spi1_sdo_i (spi1_mosi),
-    .spi1_sdo_o (spi1_mosi));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From 3dceb53984183c684a59e5d47671286febaa2836 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Thu, 8 Dec 2016 19:51:18 +0200
Subject: [PATCH 793/972] fmcadc2/vc707: Fix timing violations

---
 projects/fmcadc2/vc707/system_constr.xdc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc
index ba3dc4866..0a29e3cd0 100644
--- a/projects/fmcadc2/vc707/system_constr.xdc
+++ b/projects/fmcadc2/vc707/system_constr.xdc
@@ -43,4 +43,4 @@ create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_sysref_m*}]
-set_false_path -from [get_cells -hier -filter {name =~ *rx_sysref_m1_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *rx_sysref_reg     && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_m*  && IS_SEQUENTIAL}]

From b0eff57b0fca8249f33a5a16ec867661277c9b5c Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Thu, 8 Dec 2016 19:54:52 +0200
Subject: [PATCH 794/972] fmcomms2/zc702: Fix critical warnings

---
 projects/fmcomms2/zc702/system_constr.xdc  | 7 +++++++
 projects/fmcomms2/zc702/system_project.tcl | 4 ++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/projects/fmcomms2/zc702/system_constr.xdc b/projects/fmcomms2/zc702/system_constr.xdc
index 2e9fc432f..f48e3319e 100644
--- a/projects/fmcomms2/zc702/system_constr.xdc
+++ b/projects/fmcomms2/zc702/system_constr.xdc
@@ -62,6 +62,13 @@ set_property  -dict {PACKAGE_PIN  C18  IOSTANDARD LVCMOS25} [get_ports spi_miso]
 
 create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
 
+# disconnect gpio_bd 8-11
+
+set_property package_pin "" [get_ports [list  gpio_bd[8]]]
+set_property package_pin "" [get_ports [list  gpio_bd[9]]]
+set_property package_pin "" [get_ports [list  gpio_bd[10]]]
+set_property package_pin "" [get_ports [list  gpio_bd[11]]]
+
 # spi pmod J63
 
 set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS25  PULLTYPE PULLUP} [get_ports spi_udc_csn_tx]  ; ## PMOD1_0_LS
diff --git a/projects/fmcomms2/zc702/system_project.tcl b/projects/fmcomms2/zc702/system_project.tcl
index 6bf5f0282..e3a8db3af 100644
--- a/projects/fmcomms2/zc702/system_project.tcl
+++ b/projects/fmcomms2/zc702/system_project.tcl
@@ -6,9 +6,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create fmcomms2_zc702
 adi_project_files fmcomms2_zc702 [list \
   "system_top.v" \
-  "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" \
+  "system_constr.xdc" ]
 
 adi_project_run fmcomms2_zc702
 

From c1148889569a76e3ba25e47ade9623c48287cdc9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 8 Dec 2016 10:33:35 -0500
Subject: [PATCH 795/972] usdrx1- updates

---
 projects/usdrx1/a5gt/system_qsys.tcl   |   6 +
 projects/usdrx1/common/usdrx1_qsys.tcl | 204 +++++++++++++++++++++++++
 2 files changed, 210 insertions(+)
 create mode 100644 projects/usdrx1/a5gt/system_qsys.tcl
 create mode 100644 projects/usdrx1/common/usdrx1_qsys.tcl

diff --git a/projects/usdrx1/a5gt/system_qsys.tcl b/projects/usdrx1/a5gt/system_qsys.tcl
new file mode 100644
index 000000000..968d1161c
--- /dev/null
+++ b/projects/usdrx1/a5gt/system_qsys.tcl
@@ -0,0 +1,6 @@
+
+source $ad_hdl_dir/projects/common/a5gt/a5gt_system_qsys.tcl
+source ../common/usdrx1_qsys.tcl
+
+save_system "system_bd.qsys"
+
diff --git a/projects/usdrx1/common/usdrx1_qsys.tcl b/projects/usdrx1/common/usdrx1_qsys.tcl
new file mode 100644
index 000000000..a8221c713
--- /dev/null
+++ b/projects/usdrx1/common/usdrx1_qsys.tcl
@@ -0,0 +1,204 @@
+
+# usdrx1-xcvr
+
+add_instance avl_usdrx1_xcvr avl_adxcvr 1.0
+set_instance_parameter_value avl_usdrx1_xcvr {ID} {1}
+set_instance_parameter_value avl_usdrx1_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value avl_usdrx1_xcvr {PCS_CONFIG} {JESD_PCS_CFG1}
+set_instance_parameter_value avl_usdrx1_xcvr {LANE_RATE} {3200.0}
+set_instance_parameter_value avl_usdrx1_xcvr {PLLCLK_FREQUENCY} {1600.0}
+set_instance_parameter_value avl_usdrx1_xcvr {REFCLK_FREQUENCY} {80.0}
+set_instance_parameter_value avl_usdrx1_xcvr {CORECLK_FREQUENCY} {80.0}
+set_instance_parameter_value avl_usdrx1_xcvr {NUM_OF_LANES} {8}
+set_instance_parameter_value avl_usdrx1_xcvr {NUM_OF_CONVS} {32}
+set_instance_parameter_value avl_usdrx1_xcvr {FRM_BCNT} {4}
+set_instance_parameter_value avl_usdrx1_xcvr {FRM_SCNT} {1}
+set_instance_parameter_value avl_usdrx1_xcvr {MF_FCNT} {32}
+set_instance_parameter_value avl_usdrx1_xcvr {HD} {0}
+
+add_connection sys_clk.clk avl_usdrx1_xcvr.sys_clk
+add_connection sys_clk.clk_reset avl_usdrx1_xcvr.sys_resetn
+add_interface rx_ref_clk clock sink
+set_interface_property rx_ref_clk EXPORT_OF avl_usdrx1_xcvr.ref_clk
+add_interface rx_data_0 conduit end
+set_interface_property rx_data_0 EXPORT_OF avl_usdrx1_xcvr.rx_data_0
+add_interface rx_data_1 conduit end
+set_interface_property rx_data_1 EXPORT_OF avl_usdrx1_xcvr.rx_data_1
+add_interface rx_data_2 conduit end
+set_interface_property rx_data_2 EXPORT_OF avl_usdrx1_xcvr.rx_data_2
+add_interface rx_data_3 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_3
+add_interface rx_data_4 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_4
+add_interface rx_data_5 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_5
+add_interface rx_data_6 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_6
+add_interface rx_data_7 conduit end
+set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_7
+add_interface rx_sysref conduit end
+set_interface_property rx_sysref EXPORT_OF avl_usdrx1_xcvr.sysref
+add_interface rx_sync conduit end
+set_interface_property rx_sync EXPORT_OF avl_usdrx1_xcvr.sync
+add_interface rx_ip_sof conduit end
+set_interface_property rx_ip_sof EXPORT_OF avl_usdrx1_xcvr.ip_sof
+add_interface rx_ip_data avalon_streaming source
+set_interface_property rx_ip_data EXPORT_OF avl_usdrx1_xcvr.ip_data
+
+# usdrx1-xcvr
+
+add_instance axi_usdrx1_xcvr axi_adxcvr 1.0
+set_instance_parameter_value axi_usdrx1_xcvr {ID} {1}
+set_instance_parameter_value axi_usdrx1_xcvr {TX_OR_RX_N} {0}
+set_instance_parameter_value axi_usdrx1_xcvr {NUM_OF_LANES} {8}
+
+add_connection sys_clk.clk axi_usdrx1_xcvr.s_axi_clock
+add_connection sys_clk.clk_reset axi_usdrx1_xcvr.s_axi_reset
+add_connection axi_usdrx1_xcvr.if_up_rst avl_usdrx1_xcvr.rst
+add_connection avl_usdrx1_xcvr.ready axi_usdrx1_xcvr.ready
+add_connection axi_usdrx1_xcvr.core_pll_locked avl_usdrx1_xcvr.core_pll_locked
+
+# ad9671
+
+add_instance axi_ad9671_core_0 axi_ad9671 1.0
+
+add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_0.if_rx_clk
+add_interface rx_ip_sof_0 conduit end
+set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9671_core_0.if_rx_sof
+add_interface rx_ip_data_0 avalon_streaming sink
+set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9671_core_0.if_rx_data
+add_connection sys_clk.clk_reset axi_ad9671_core_0.s_axi_reset
+add_connection sys_clk.clk axi_ad9671_core_0.s_axi_clock
+
+add_instance axi_ad9671_core_1 axi_ad9671 1.0
+
+add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_1.if_rx_clk
+add_interface rx_ip_sof_1 conduit end
+set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9671_core_1.if_rx_sof
+add_interface rx_ip_data_1 avalon_streaming sink
+set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9671_core_1.if_rx_data
+add_connection sys_clk.clk_reset axi_ad9671_core_1.s_axi_reset
+add_connection sys_clk.clk axi_ad9671_core_1.s_axi_clock
+
+add_instance axi_ad9671_core_2 axi_ad9671 1.0
+
+add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_2.if_rx_clk
+add_interface rx_ip_sof_2 conduit end
+set_interface_property rx_ip_sof_2 EXPORT_OF axi_ad9671_core_2.if_rx_sof
+add_interface rx_ip_data_2 avalon_streaming sink
+set_interface_property rx_ip_data_2 EXPORT_OF axi_ad9671_core_2.if_rx_data
+add_connection sys_clk.clk_reset axi_ad9671_core_2.s_axi_reset
+add_connection sys_clk.clk axi_ad9671_core_2.s_axi_clock
+
+add_instance axi_ad9671_core_3 axi_ad9671 1.0
+
+add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_3.if_rx_clk
+add_interface rx_ip_sof_3 conduit end
+set_interface_property rx_ip_sof_3 EXPORT_OF axi_ad9671_core_3.if_rx_sof
+add_interface rx_ip_data_3 avalon_streaming sink
+set_interface_property rx_ip_data_3 EXPORT_OF axi_ad9671_core_3.if_rx_data
+add_connection sys_clk.clk_reset axi_ad9671_core_3.s_axi_reset
+add_connection sys_clk.clk axi_ad9671_core_3.s_axi_clock
+
+# usdrx1-pack
+
+add_instance util_usdrx1_cpack util_cpack 1.0
+set_instance_parameter_value util_usdrx1_cpack {CHANNEL_DATA_WIDTH} {128}
+set_instance_parameter_value util_usdrx1_cpack {NUM_OF_CHANNELS} {4}
+
+add_connection sys_clk.clk_reset util_usdrx1_cpack.if_adc_rst
+add_connection sys_dma_clk.clk_reset util_usdrx1_cpack.if_adc_rst
+add_connection avl_usdrx1_xcvr.core_clk util_usdrx1_cpack.if_adc_clk
+add_connection axi_ad9671_core_0.adc_ch util_usdrx1_cpack.adc_ch_0
+add_connection axi_ad9671_core_1.adc_ch util_usdrx1_cpack.adc_ch_1
+add_connection axi_ad9671_core_2.adc_ch util_usdrx1_cpack.adc_ch_2
+add_connection axi_ad9671_core_3.adc_ch util_usdrx1_cpack.adc_ch_3
+
+# usdrx1-fifo
+
+add_instance usdrx1_adcfifo util_adcfifo 1.0
+set_instance_parameter_value usdrx1_adcfifo {ADC_DATA_WIDTH} {512}
+set_instance_parameter_value usdrx1_adcfifo {DMA_DATA_WIDTH} {512}
+set_instance_parameter_value usdrx1_adcfifo {DMA_ADDRESS_WIDTH} {16}
+
+add_connection sys_clk.clk_reset usdrx1_adcfifo.if_adc_rst
+add_connection sys_dma_clk.clk_reset usdrx1_adcfifo.if_adc_rst
+add_connection avl_usdrx1_xcvr.core_clk usdrx1_adcfifo.if_adc_clk
+add_connection util_usdrx1_cpack.if_adc_valid usdrx1_adcfifo.if_adc_wr
+add_connection util_usdrx1_cpack.if_adc_data usdrx1_adcfifo.if_adc_wdata
+add_connection sys_dma_clk.clk usdrx1_adcfifo.if_dma_clk
+
+# usdrx1-dma
+
+add_instance axi_usdrx1_dma axi_dmac 1.0
+set_instance_parameter_value axi_usdrx1_dma {DMA_DATA_WIDTH_SRC} {512}
+set_instance_parameter_value axi_usdrx1_dma {DMA_DATA_WIDTH_DEST} {512}
+set_instance_parameter_value axi_usdrx1_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_usdrx1_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_usdrx1_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_usdrx1_dma {CYCLIC} {0}
+set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_SRC} {1}
+
+add_connection sys_dma_clk.clk axi_usdrx1_dma.if_s_axis_aclk
+add_connection usdrx1_adcfifo.if_dma_wr axi_usdrx1_dma.if_s_axis_valid
+add_connection usdrx1_adcfifo.if_dma_wdata axi_usdrx1_dma.if_s_axis_data
+add_connection usdrx1_adcfifo.if_dma_wready axi_usdrx1_dma.if_s_axis_ready
+add_connection usdrx1_adcfifo.if_dma_xfer_req axi_usdrx1_dma.if_s_axis_xfer_req
+add_connection usdrx1_adcfifo.if_adc_wovf axi_ad9671_core_0.if_adc_dovf
+add_connection sys_clk.clk_reset axi_usdrx1_dma.s_axi_reset
+add_connection sys_clk.clk axi_usdrx1_dma.s_axi_clock
+add_connection sys_dma_clk.clk_reset axi_usdrx1_dma.m_dest_axi_reset
+add_connection sys_dma_clk.clk axi_usdrx1_dma.m_dest_axi_clock
+
+# core-clock
+
+add_instance rx_core_clk altera_clock_bridge 16.0
+add_connection avl_usdrx1_xcvr.core_clk rx_core_clk.in_clk
+add_interface rx_core_clk clock source
+set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk
+
+# phy reconfiguration
+
+add_instance avl_phy_reconfig alt_xcvr_reconfig 16.0
+set_instance_parameter_value avl_phy_reconfig {number_of_reconfig_interfaces} {8}
+set_instance_parameter_value avl_phy_reconfig {gui_split_sizes} {1,1,1,1,1,1,1,1}
+add_connection avl_phy_reconfig.ch0_0_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_0 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_0 avl_phy_reconfig.ch0_0_from_xcvr 
+add_connection avl_phy_reconfig.ch1_1_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_1 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_1 avl_phy_reconfig.ch1_1_from_xcvr 
+add_connection avl_phy_reconfig.ch2_2_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_2 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_2 avl_phy_reconfig.ch2_2_from_xcvr 
+add_connection avl_phy_reconfig.ch3_3_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_3 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_3 avl_phy_reconfig.ch3_3_from_xcvr 
+add_connection avl_phy_reconfig.ch0_4_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_4 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_4 avl_phy_reconfig.ch0_4_from_xcvr 
+add_connection avl_phy_reconfig.ch1_5_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_5 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_5 avl_phy_reconfig.ch1_5_from_xcvr 
+add_connection avl_phy_reconfig.ch2_6_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_6 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_6 avl_phy_reconfig.ch2_6_from_xcvr 
+add_connection avl_phy_reconfig.ch3_7_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_7 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_7 avl_phy_reconfig.ch3_7_from_xcvr 
+add_connection sys_clk.clk_reset avl_phy_reconfig.mgmt_rst_reset
+add_connection sys_clk.clk avl_phy_reconfig.mgmt_clk_clk
+
+# addresses
+
+ad_cpu_interconnect 0x00010000 avl_phy_reconfig.reconfig_mgmt
+ad_cpu_interconnect 0x00018000 avl_usdrx1_xcvr.core_pll_reconfig
+ad_cpu_interconnect 0x00019000 avl_usdrx1_xcvr.ip_reconfig
+ad_cpu_interconnect 0x00020000 axi_usdrx1_xcvr.s_axi
+ad_cpu_interconnect 0x00050000 axi_ad9671_core_0.s_axi
+ad_cpu_interconnect 0x00060000 axi_ad9671_core_1.s_axi
+ad_cpu_interconnect 0x00070000 axi_ad9671_core_2.s_axi
+ad_cpu_interconnect 0x00080000 axi_ad9671_core_3.s_axi
+ad_cpu_interconnect 0x00090000 axi_usdrx1_dma.s_axi
+
+# dma interconnects
+
+ad_dma_interconnect axi_usdrx1_dma.m_dest_axi
+
+# interrupts
+
+ad_cpu_interrupt 11 axi_usdrx1_dma.interrupt_sender
+

From 854cd4402677a0eebb015520bec1d20a8e2c46c9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 8 Dec 2016 16:02:40 -0500
Subject: [PATCH 796/972] ad9671- xcvr interface changes

---
 library/axi_ad9671/axi_ad9671.v      | 33 +++++++++--------
 library/axi_ad9671/axi_ad9671_hw.tcl | 54 ++++++++++++++++------------
 library/axi_ad9671/axi_ad9671_if.v   | 49 ++++++++++++++++---------
 library/axi_ad9671/axi_ad9671_ip.tcl |  2 ++
 4 files changed, 81 insertions(+), 57 deletions(-)

diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v
index 1b524ca70..442476e08 100644
--- a/library/axi_ad9671/axi_ad9671.v
+++ b/library/axi_ad9671/axi_ad9671.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -45,8 +43,10 @@ module axi_ad9671 (
   // rx_clk is (line-rate/40)
 
   rx_clk,
-  rx_data,
   rx_sof,
+  rx_valid,
+  rx_data,
+  rx_ready,
 
   // dma interface
 
@@ -88,14 +88,15 @@ module axi_ad9671 (
   parameter ID = 0;
   parameter DEVICE_TYPE = 0;
   parameter QUAD_OR_DUAL_N = 1;
-  parameter IO_DELAY_GROUP = "adc_if_delay_group";
 
   // jesd interface
   // rx_clk is the jesd clock (ref_clk/2)
 
   input                                 rx_clk;
-  input   [(64*QUAD_OR_DUAL_N)+63:0]     rx_data;
-  input                                 rx_sof;
+  input   [  3:0]                       rx_sof;
+  input                                 rx_valid;
+  input   [(64*QUAD_OR_DUAL_N)+63:0]    rx_data;
+  output                                rx_ready;
 
   // dma interface
 
@@ -172,6 +173,7 @@ module axi_ad9671 (
 
   // signal name changes
 
+  assign rx_ready = 1'b1;
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
 
@@ -201,9 +203,10 @@ module axi_ad9671 (
   // main (device interface)
 
   axi_ad9671_if #(
-    .QUAD_OR_DUAL_N(QUAD_OR_DUAL_N),
-    .ID(ID)
-  ) i_if (
+    .QUAD_OR_DUAL_N (QUAD_OR_DUAL_N),
+    .ID (ID),
+    .DEVICE_TYPE (DEVICE_TYPE))
+  i_if (
     .rx_clk (rx_clk),
     .rx_data (rx_data),
     .rx_sof (rx_sof),
@@ -232,8 +235,8 @@ module axi_ad9671 (
     .adc_sync_out (adc_sync_out),
     .adc_sync_status (adc_sync_status_s),
     .adc_status (adc_status_s),
-    .adc_raddr_in(adc_raddr_in),
-    .adc_raddr_out(adc_raddr_out));
+    .adc_raddr_in (adc_raddr_in),
+    .adc_raddr_out (adc_raddr_out));
 
   // channels
 
@@ -267,9 +270,7 @@ module axi_ad9671 (
 
   // common processor control
 
-  up_adc_common #(
-    .ID(ID)
-  ) i_up_adc_common (
+  up_adc_common #(.ID (ID)) i_up_adc_common (
     .mmcm_rst (),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -310,9 +311,7 @@ module axi_ad9671 (
 
   // up bus interface
 
-  up_axi #(
-    .ADDRESS_WIDTH (14)
-  ) i_up_axi (
+  up_axi i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
diff --git a/library/axi_ad9671/axi_ad9671_hw.tcl b/library/axi_ad9671/axi_ad9671_hw.tcl
index 4d03ba575..ea7c1995b 100644
--- a/library/axi_ad9671/axi_ad9671_hw.tcl
+++ b/library/axi_ad9671/axi_ad9671_hw.tcl
@@ -2,6 +2,7 @@
 
 package require -exact qsys 14.0
 source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
 
 set_module_property NAME axi_ad9671
 set_module_property DESCRIPTION "AXI AD9671 Interface"
@@ -23,11 +24,13 @@ add_fileset_file up_clock_mon.v       VERILOG PATH $ad_hdl_dir/library/common/up
 add_fileset_file up_delay_cntrl.v     VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
 add_fileset_file up_adc_common.v      VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
 add_fileset_file up_adc_channel.v     VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
+add_fileset_file ad_xcvr_rx_if.v      VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
 add_fileset_file ad_mem.v             VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
 add_fileset_file axi_ad9671_pnmon.v   VERILOG PATH axi_ad9671_pnmon.v
 add_fileset_file axi_ad9671_if.v      VERILOG PATH axi_ad9671_if.v
 add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v
 add_fileset_file axi_ad9671.v         VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE
+add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
 
 # parameters
 
@@ -65,7 +68,7 @@ add_interface s_axi axi4lite end
 set_interface_property s_axi associatedClock s_axi_clock
 set_interface_property s_axi associatedReset s_axi_reset
 add_interface_port s_axi s_axi_awvalid awvalid Input 1
-add_interface_port s_axi s_axi_awaddr awaddr Input 14
+add_interface_port s_axi s_axi_awaddr awaddr Input 16
 add_interface_port s_axi s_axi_awprot awprot Input 3
 add_interface_port s_axi s_axi_awready awready Output 1
 add_interface_port s_axi s_axi_wvalid wvalid Input 1
@@ -76,7 +79,7 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1
 add_interface_port s_axi s_axi_bresp bresp Output 2
 add_interface_port s_axi s_axi_bready bready Input 1
 add_interface_port s_axi s_axi_arvalid arvalid Input 1
-add_interface_port s_axi s_axi_araddr araddr Input 14
+add_interface_port s_axi s_axi_araddr araddr Input 16
 add_interface_port s_axi s_axi_arprot arprot Input 3
 add_interface_port s_axi s_axi_arready arready Output 1
 add_interface_port s_axi s_axi_rvalid rvalid Output 1
@@ -86,31 +89,36 @@ add_interface_port s_axi s_axi_rready rready Input 1
 
 # transceiver interface
 
-add_interface xcvr_clk clock end
-add_interface_port xcvr_clk rx_clk clk Input 1
+ad_alt_intf clock   rx_clk        input   1
+ad_alt_intf signal  rx_sof        input   4 export
 
-add_interface xcvr_data conduit end
-set_interface_property xcvr_data associatedClock xcvr_clk
-add_interface_port xcvr_data rx_data data Input 64*QUAD_OR_DUAL_N+64
-add_interface_port xcvr_data rx_sof data_sof Input 1
+add_interface if_rx_data avalon_streaming sink
+add_interface_port if_rx_data rx_data  data  input 64*QUAD_OR_DUAL_N+64
+add_interface_port if_rx_data rx_valid valid input 1
+add_interface_port if_rx_data rx_ready ready output 1
+set_interface_property if_rx_data associatedClock if_rx_clk
+set_interface_property if_rx_data dataBitsPerSymbol 64
 
-add_interface xcvr_sync conduit end
-set_interface_property xcvr_sync associatedClock xcvr_clk
-add_interface_port xcvr_sync adc_sync_in sync_in Input 1
-add_interface_port xcvr_sync adc_sync_out sync_out Output 1
-add_interface_port xcvr_sync adc_raddr_in raddr_in Input 4
-add_interface_port xcvr_sync adc_raddr_out raddr_out Output 4
+add_interface if_sync conduit end
+set_interface_property if_sync associatedClock if_clk
+add_interface_port if_sync adc_sync_in sync_in Input 1
+add_interface_port if_sync adc_sync_out sync_out Output 1
+add_interface_port if_sync adc_raddr_in raddr_in Input 4
+add_interface_port if_sync adc_raddr_out raddr_out Output 4
 
 # dma interface
 
-add_interface adc_clock clock start
-add_interface_port adc_clock adc_clk clk Output 1
+ad_alt_intf clock   adc_clk     output  1
+ad_alt_intf reset   adc_rst     output  1 if_adc_clk
 
-add_interface adc_dma_if conduit end
-set_interface_property adc_dma_if associatedClock adc_clock
-add_interface_port adc_dma_if adc_valid valid Output 8
-add_interface_port adc_dma_if adc_enable enable Output 8
-add_interface_port adc_dma_if adc_data data Output 128
-add_interface_port adc_dma_if adc_dovf dovf Input 1
-add_interface_port adc_dma_if adc_dunf dunf Input 1
+add_interface adc_ch conduit end
+add_interface_port adc_ch adc_enable  enable  Output 8
+add_interface_port adc_ch adc_valid   valid   Output 8
+add_interface_port adc_ch adc_data    data    Output 128
+
+set_interface_property adc_ch associatedClock if_rx_clk
+set_interface_property adc_ch associatedReset none
+
+ad_alt_intf signal  adc_dovf      input   1     ovf
+ad_alt_intf signal  adc_dunf      input   1     unf
 
diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v
index 4e838487f..9b8eaabb6 100644
--- a/library/axi_ad9671/axi_ad9671_if.v
+++ b/library/axi_ad9671/axi_ad9671_if.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -81,14 +79,15 @@ module axi_ad9671_if (
   // parameters
 
   parameter QUAD_OR_DUAL_N = 1;
+  parameter DEVICE_TYPE = 0;
   parameter ID = 0;
 
   // jesd interface 
   // rx_clk is (line-rate/40)
 
   input                                 rx_clk;
-  input                                 rx_sof;
-  input   [(64*QUAD_OR_DUAL_N)+63:0]     rx_data;
+  input   [  3:0]                       rx_sof;
+  input   [(64*QUAD_OR_DUAL_N)+63:0]    rx_data;
 
   // adc data output
 
@@ -122,6 +121,8 @@ module axi_ad9671_if (
 
   // internal wires
 
+  wire    [(2*QUAD_OR_DUAL_N)+1:0]      rx_sof_s;
+  wire    [(64*QUAD_OR_DUAL_N)+63:0]    rx_data_s;
   wire    [127:0]                       adc_wdata;
   wire    [127:0]                       adc_rdata;
   wire    [ 15:0]                       adc_data_a_s;
@@ -142,17 +143,16 @@ module axi_ad9671_if (
   reg                                   adc_status = 'd0;
   reg                                   adc_sync_status = 'd0;
   reg                                   rx_sof_d = 'd0;
-
   reg     [  3:0]                       adc_waddr = 'd0;
   reg     [  3:0]                       adc_raddr_out = 'd0;
-  reg     [ 15:0]                       adc_data_a;
-  reg     [ 15:0]                       adc_data_b;
-  reg     [ 15:0]                       adc_data_c;
-  reg     [ 15:0]                       adc_data_d;
-  reg     [ 15:0]                       adc_data_e;
-  reg     [ 15:0]                       adc_data_f;
-  reg     [ 15:0]                       adc_data_g;
-  reg     [ 15:0]                       adc_data_h;
+  reg     [ 15:0]                       adc_data_a = 'd0;
+  reg     [ 15:0]                       adc_data_b = 'd0;
+  reg     [ 15:0]                       adc_data_c = 'd0;
+  reg     [ 15:0]                       adc_data_d = 'd0;
+  reg     [ 15:0]                       adc_data_e = 'd0;
+  reg     [ 15:0]                       adc_data_f = 'd0;
+  reg     [ 15:0]                       adc_data_g = 'd0;
+  reg     [ 15:0]                       adc_data_h = 'd0;
 
   // adc clock & valid
 
@@ -219,12 +219,12 @@ module axi_ad9671_if (
   always @(posedge rx_clk) begin
     if (QUAD_OR_DUAL_N == 1'b1) begin
       int_valid <= 1'b1;
-      int_data  <= rx_data;
+      int_data  <= rx_data_s;
     end else begin
-      rx_sof_d          <= rx_sof;
+      rx_sof_d          <= &rx_sof_s;
       int_valid         <= rx_sof_d;
-      int_data[63:0]    <= {rx_data[31:0], int_data[63:32]};
-      int_data[127:64]  <= {rx_data[63:32], int_data[127:96]};
+      int_data[63:0]    <= {rx_data_s[31: 0], int_data[ 63:32]};
+      int_data[127:64]  <= {rx_data_s[63:32], int_data[127:96]};
     end
   end
 
@@ -245,6 +245,21 @@ module axi_ad9671_if (
     .addrb(adc_raddr_s),
     .doutb(adc_rdata));
 
+  // frame-alignment
+
+  genvar n;
+
+  generate
+  for (n = 0; n < ((2*QUAD_OR_DUAL_N)+2); n = n + 1) begin: g_xcvr_if
+  ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
+    .rx_clk (rx_clk),
+    .rx_ip_sof (rx_sof),
+    .rx_ip_data (rx_data[((n*32)+31):(n*32)]),
+    .rx_sof (rx_sof_s[n]),
+    .rx_data (rx_data_s[((n*32)+31):(n*32)]));
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/axi_ad9671/axi_ad9671_ip.tcl b/library/axi_ad9671/axi_ad9671_ip.tcl
index a51cccfc9..f7ccf834b 100644
--- a/library/axi_ad9671/axi_ad9671_ip.tcl
+++ b/library/axi_ad9671/axi_ad9671_ip.tcl
@@ -15,6 +15,7 @@ adi_ip_files axi_ad9671 [list \
   "$ad_hdl_dir/library/common/up_adc_common.v" \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
   "$ad_hdl_dir/library/common/ad_mem.v" \
+  "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9671_pnmon.v" \
   "axi_ad9671_channel.v" \
@@ -28,6 +29,7 @@ adi_ip_constraints axi_ad9671 [list \
   "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9671_constr.xdc" ]
 
+set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]

From f799c40cf01ee785760b4e525b2abe69b66cf0e0 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 8 Dec 2016 16:05:07 -0500
Subject: [PATCH 797/972] usdrx1/a5gt- xcvr interface changes

---
 projects/usdrx1/a5gt/Makefile           |    2 -
 projects/usdrx1/a5gt/system_bd.qsys     | 2844 -----------------------
 projects/usdrx1/a5gt/system_constr.sdc  |   42 +-
 projects/usdrx1/a5gt/system_project.tcl |    9 +-
 projects/usdrx1/a5gt/system_top.v       |  685 +++---
 projects/usdrx1/common/usdrx1_qsys.tcl  |   93 +-
 6 files changed, 345 insertions(+), 3330 deletions(-)
 delete mode 100644 projects/usdrx1/a5gt/system_bd.qsys

diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index 5ded32c1c..90b2cb09d 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -15,8 +15,6 @@ M_DEPS += system_project.tcl
 M_DEPS += ../common/usdrx1_spi.v
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
-M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v
-M_DEPS += ../../../library/common/altera/ad_jesd_align.v
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/usdrx1/a5gt/system_bd.qsys b/projects/usdrx1/a5gt/system_bd.qsys
deleted file mode 100644
index bc08c08f3..000000000
--- a/projects/usdrx1/a5gt/system_bd.qsys
+++ /dev/null
@@ -1,2844 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
-   element axi_ad9671_0
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9671_0.s_axi
-   {
-      datum baseAddress
-      {
-         value = "85983232";
-         type = "String";
-      }
-   }
-   element axi_ad9671_1
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9671_1.s_axi
-   {
-      datum baseAddress
-      {
-         value = "86048768";
-         type = "String";
-      }
-   }
-   element axi_ad9671_2
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9671_2.s_axi
-   {
-      datum baseAddress
-      {
-         value = "86114304";
-         type = "String";
-      }
-   }
-   element axi_ad9671_3
-   {
-      datum _sortIndex
-      {
-         value = "21";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9671_3.s_axi
-   {
-      datum baseAddress
-      {
-         value = "86179840";
-         type = "String";
-      }
-   }
-   element axi_dmac
-   {
-      datum _sortIndex
-      {
-         value = "22";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dmac.s_axi
-   {
-      datum baseAddress
-      {
-         value = "85999616";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_cpu
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ddr3_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ddr3_cntrl.avl
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_ddr3_cpuconnect
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ddr3_cpuconnect.cntl
-   {
-      datum baseAddress
-      {
-         value = "86025424";
-         type = "String";
-      }
-   }
-   element sys_ddr3_cpuconnect.windowed_slave
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_ddr3_dmaconnect
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ddr3_dmaconnect.s0
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_ddr3_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ddr3_interconnect.s0
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_ethernet
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet.control_port
-   {
-      datum baseAddress
-      {
-         value = "86024192";
-         type = "String";
-      }
-   }
-   element sys_ethernet_desc_mem
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet_desc_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_rx
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet_dma_rx.csr
-   {
-      datum baseAddress
-      {
-         value = "86025280";
-         type = "String";
-      }
-   }
-   element sys_ethernet_dma_tx
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ethernet_dma_tx.csr
-   {
-      datum baseAddress
-      {
-         value = "86025216";
-         type = "String";
-      }
-   }
-   element sys_gpio
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_gpio.s1
-   {
-      datum baseAddress
-      {
-         value = "86025408";
-         type = "String";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_id.control_slave
-   {
-      datum baseAddress
-      {
-         value = "86025432";
-         type = "String";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_int_mem.s1
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "83886080";
-         type = "String";
-      }
-   }
-   element sys_int_mem.s2
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "83886080";
-         type = "String";
-      }
-   }
-   element sys_jesd204b_s1
-   {
-      datum _sortIndex
-      {
-         value = "26";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_jesd204b_s1.jesd204_rx_avs
-   {
-      datum baseAddress
-      {
-         value = "67108864";
-         type = "String";
-      }
-   }
-   element sys_jesd204b_s1_pll
-   {
-      datum _sortIndex
-      {
-         value = "24";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_jesd204b_s1_ref_clk
-   {
-      datum _sortIndex
-      {
-         value = "23";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_jesd204b_s1_rx_clk
-   {
-      datum _sortIndex
-      {
-         value = "25";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_pll
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_spi
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_spi.spi_control_port
-   {
-      datum baseAddress
-      {
-         value = "86025344";
-         type = "String";
-      }
-   }
-   element sys_tcm_mem
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_tcm_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "86016000";
-         type = "String";
-      }
-   }
-   element sys_tcm_mem.s2
-   {
-      datum baseAddress
-      {
-         value = "86016000";
-         type = "String";
-      }
-   }
-   element sys_timer
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_timer.s1
-   {
-      datum baseAddress
-      {
-         value = "86025376";
-         type = "String";
-      }
-   }
-   element sys_uart
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_uart.avalon_jtag_slave
-   {
-      datum baseAddress
-      {
-         value = "86025440";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5AGTFD7K3F40I3" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="usdrx1_a5gt.qpf" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="axi_ad9671_0_adc_clock"
-   internal="axi_ad9671_0.adc_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="axi_ad9671_0_adc_dma_if"
-   internal="axi_ad9671_0.adc_dma_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_0_xcvr_clk"
-   internal="axi_ad9671_0.xcvr_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_ad9671_0_xcvr_data"
-   internal="axi_ad9671_0.xcvr_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_0_xcvr_sync"
-   internal="axi_ad9671_0.xcvr_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_1_adc_clock"
-   internal="axi_ad9671_1.adc_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="axi_ad9671_1_adc_dma_if"
-   internal="axi_ad9671_1.adc_dma_if"
-   type="conduit"
-   dir="end" />
- <interface name="axi_ad9671_1_adc_mon_if" internal="axi_ad9671_0.adc_mon_if" />
- <interface
-   name="axi_ad9671_1_xcvr_clk"
-   internal="axi_ad9671_1.xcvr_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_ad9671_1_xcvr_data"
-   internal="axi_ad9671_1.xcvr_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_1_xcvr_sync"
-   internal="axi_ad9671_1.xcvr_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_2_adc_clock"
-   internal="axi_ad9671_2.adc_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="axi_ad9671_2_adc_dma_if"
-   internal="axi_ad9671_2.adc_dma_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_2_xcvr_clk"
-   internal="axi_ad9671_2.xcvr_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_ad9671_2_xcvr_data"
-   internal="axi_ad9671_2.xcvr_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_2_xcvr_sync"
-   internal="axi_ad9671_2.xcvr_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_3_adc_clock"
-   internal="axi_ad9671_3.adc_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="axi_ad9671_3_adc_dma_if"
-   internal="axi_ad9671_3.adc_dma_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_3_xcvr_clk"
-   internal="axi_ad9671_3.xcvr_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_ad9671_3_xcvr_data"
-   internal="axi_ad9671_3.xcvr_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9671_3_xcvr_sync"
-   internal="axi_ad9671_3.xcvr_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_dmac_0_fifo_wr_clock"
-   internal="axi_dmac.fifo_wr_clock"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_dmac_0_fifo_wr_if"
-   internal="axi_dmac.fifo_wr_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_125m_clk"
-   internal="sys_pll.outclk2"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_25m_clk"
-   internal="sys_pll.outclk3"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_2m5_clk"
-   internal="sys_pll.outclk4"
-   type="clock"
-   dir="start" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_ddr3_oct"
-   internal="sys_ddr3_cntrl.oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ddr3_phy"
-   internal="sys_ddr3_cntrl.memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_mdio"
-   internal="sys_ethernet.mac_mdio_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_rgmii"
-   internal="sys_ethernet.mac_rgmii_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_rx_clk"
-   internal="sys_ethernet.pcs_mac_rx_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_ethernet_status"
-   internal="sys_ethernet.mac_status_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_tx_clk"
-   internal="sys_ethernet.pcs_mac_tx_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_gpio"
-   internal="sys_gpio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_lane_aligned"
-   internal="sys_jesd204b_s1.dev_lane_aligned"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_lane_aligned_all"
-   internal="sys_jesd204b_s1.alldev_lane_aligned"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_locked"
-   internal="sys_jesd204b_s1.rx_islockedtodata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_pll_locked"
-   internal="sys_jesd204b_s1_pll.locked"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_ref_clk"
-   internal="sys_jesd204b_s1_ref_clk.in_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_analogreset"
-   internal="sys_jesd204b_s1.rx_analogreset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_cal_busy"
-   internal="sys_jesd204b_s1.rx_cal_busy"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_clk"
-   internal="sys_jesd204b_s1_rx_clk.out_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_jesd204b_s1_rx_digitalreset"
-   internal="sys_jesd204b_s1.rx_digitalreset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_ferr"
-   internal="sys_jesd204b_s1.jesd204_rx_frame_error"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_link"
-   internal="sys_jesd204b_s1.jesd204_rx_link"
-   type="avalon_streaming"
-   dir="start" />
- <interface
-   name="sys_jesd204b_s1_rx_sof"
-   internal="sys_jesd204b_s1.sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_xcvr_data"
-   internal="sys_jesd204b_s1.rx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_sync_n"
-   internal="sys_jesd204b_s1.dev_sync_n"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_sysref"
-   internal="sys_jesd204b_s1.sysref"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_pll_locked"
-   internal="sys_pll.locked"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_reset"
-   internal="sys_clk.clk_in_reset"
-   type="reset"
-   dir="end" />
- <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module name="axi_ad9671_0" kind="axi_ad9671" version="1.0" enabled="1">
-  <parameter name="PCORE_4L_2L_N" value="0" />
-  <parameter name="PCORE_DEVICE_TYPE" value="0" />
-  <parameter name="PCORE_ID" value="0" />
- </module>
- <module name="axi_ad9671_1" kind="axi_ad9671" version="1.0" enabled="1">
-  <parameter name="PCORE_4L_2L_N" value="0" />
-  <parameter name="PCORE_DEVICE_TYPE" value="0" />
-  <parameter name="PCORE_ID" value="1" />
- </module>
- <module name="axi_ad9671_2" kind="axi_ad9671" version="1.0" enabled="1">
-  <parameter name="PCORE_4L_2L_N" value="0" />
-  <parameter name="PCORE_DEVICE_TYPE" value="0" />
-  <parameter name="PCORE_ID" value="2" />
- </module>
- <module name="axi_ad9671_3" kind="axi_ad9671" version="1.0" enabled="1">
-  <parameter name="PCORE_4L_2L_N" value="0" />
-  <parameter name="PCORE_DEVICE_TYPE" value="0" />
-  <parameter name="PCORE_ID" value="3" />
- </module>
- <module name="axi_dmac" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="C_2D_TRANSFER" value="1" />
-  <parameter name="C_AXI_SLICE_DEST" value="0" />
-  <parameter name="C_AXI_SLICE_SRC" value="0" />
-  <parameter name="C_CLKS_ASYNC_DEST_REQ" value="1" />
-  <parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
-  <parameter name="C_CLKS_ASYNC_SRC_DEST" value="1" />
-  <parameter name="C_CYCLIC" value="1" />
-  <parameter name="C_DMA_DATA_WIDTH_DEST" value="128" />
-  <parameter name="C_DMA_DATA_WIDTH_SRC" value="512" />
-  <parameter name="C_DMA_LENGTH_WIDTH" value="23" />
-  <parameter name="C_DMA_TYPE_DEST" value="0" />
-  <parameter name="C_DMA_TYPE_SRC" value="2" />
-  <parameter name="C_SYNC_TRANSFER_START" value="0" />
-  <parameter name="PCORE_ID" value="0" />
- </module>
- <module name="sys_clk" kind="clock_source" version="14.1" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="DEASSERT" />
- </module>
- <module name="sys_cpu" kind="altera_nios2_gen2" version="14.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="21" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="21" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="bht_ramBlockType" value="Automatic" />
-  <parameter name="breakOffset" value="32" />
-  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
-  <parameter name="cdx_enabled" value="false" />
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="cpuArchRev" value="1" />
-  <parameter name="cpuID" value="0" />
-  <parameter name="cpuReset" value="false" />
-  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
-  <parameter name="dataAddrWidth" value="27" />
-  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cpuconnect.windowed_slave' start='0x0' end='0x4000000' /><slave name='sys_jesd204b_s1.jesd204_rx_avs' start='0x4000000' end='0x4000400' /><slave name='sys_int_mem.s1' start='0x5000000' end='0x5180000' /><slave name='axi_ad9671_0.s_axi' start='0x5200000' end='0x5204000' /><slave name='axi_dmac.s_axi' start='0x5204000' end='0x5208000' /><slave name='sys_cpu.debug_mem_slave' start='0x5209800' end='0x520A000' /><slave name='sys_ethernet.control_port' start='0x520A000' end='0x520A400' /><slave name='sys_ethernet_dma_tx.csr' start='0x520A400' end='0x520A440' /><slave name='sys_ethernet_dma_rx.csr' start='0x520A440' end='0x520A480' /><slave name='sys_spi.spi_control_port' start='0x520A480' end='0x520A4A0' /><slave name='sys_timer.s1' start='0x520A4A0' end='0x520A4C0' /><slave name='sys_gpio.s1' start='0x520A4C0' end='0x520A4D0' /><slave name='sys_ddr3_cpuconnect.cntl' start='0x520A4D0' end='0x520A4D8' /><slave name='sys_id.control_slave' start='0x520A4D8' end='0x520A4E0' /><slave name='sys_uart.avalon_jtag_slave' start='0x520A4E0' end='0x520A4E8' /><slave name='axi_ad9671_1.s_axi' start='0x5210000' end='0x5214000' /><slave name='axi_ad9671_2.s_axi' start='0x5220000' end='0x5224000' /><slave name='axi_ad9671_3.s_axi' start='0x5230000' end='0x5234000' /></address-map>]]></parameter>
-  <parameter name="data_master_high_performance_paddr_base" value="0" />
-  <parameter name="data_master_high_performance_paddr_size" value="0" />
-  <parameter name="data_master_paddr_base" value="0" />
-  <parameter name="data_master_paddr_size" value="0" />
-  <parameter name="dcache_bursts" value="false" />
-  <parameter name="dcache_numTCDM" value="1" />
-  <parameter name="dcache_ramBlockType" value="Automatic" />
-  <parameter name="dcache_size" value="2048" />
-  <parameter name="dcache_tagramBlockType" value="Automatic" />
-  <parameter name="dcache_victim_buf_impl" value="ram" />
-  <parameter name="debug_OCIOnchipTrace" value="_128" />
-  <parameter name="debug_assignJtagInstanceID" value="false" />
-  <parameter name="debug_datatrigger" value="0" />
-  <parameter name="debug_debugReqSignals" value="false" />
-  <parameter name="debug_enabled" value="true" />
-  <parameter name="debug_hwbreakpoint" value="0" />
-  <parameter name="debug_jtagInstanceID" value="0" />
-  <parameter name="debug_traceStorage" value="onchip_trace" />
-  <parameter name="debug_traceType" value="none" />
-  <parameter name="debug_triggerArming" value="true" />
-  <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dividerType" value="no_div" />
-  <parameter name="exceptionOffset" value="32" />
-  <parameter name="exceptionSlave" value="sys_int_mem.s2" />
-  <parameter name="faAddrWidth" value="1" />
-  <parameter name="faSlaveMapParam" value="" />
-  <parameter name="fa_cache_line" value="2" />
-  <parameter name="fa_cache_linesize" value="0" />
-  <parameter name="flash_instruction_master_paddr_base" value="0" />
-  <parameter name="flash_instruction_master_paddr_size" value="0" />
-  <parameter name="icache_burstType" value="None" />
-  <parameter name="icache_numTCIM" value="1" />
-  <parameter name="icache_ramBlockType" value="Automatic" />
-  <parameter name="icache_size" value="4096" />
-  <parameter name="icache_tagramBlockType" value="Automatic" />
-  <parameter name="impl" value="Fast" />
-  <parameter name="instAddrWidth" value="27" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cpuconnect.windowed_slave' start='0x0' end='0x4000000' /><slave name='sys_int_mem.s2' start='0x5000000' end='0x5180000' /><slave name='sys_cpu.debug_mem_slave' start='0x5209800' end='0x520A000' /></address-map>]]></parameter>
-  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
-  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
-  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
-  <parameter name="instruction_master_paddr_base" value="0" />
-  <parameter name="instruction_master_paddr_size" value="0" />
-  <parameter name="internalIrqMaskSystemInfo" value="63" />
-  <parameter name="io_regionbase" value="0" />
-  <parameter name="io_regionsize" value="0" />
-  <parameter name="master_addr_map" value="false" />
-  <parameter name="mmu_TLBMissExcOffset" value="4096" />
-  <parameter name="mmu_TLBMissExcSlave" value="sys_int_mem.s2" />
-  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
-  <parameter name="mmu_enabled" value="false" />
-  <parameter name="mmu_processIDNumBits" value="8" />
-  <parameter name="mmu_ramBlockType" value="Automatic" />
-  <parameter name="mmu_tlbNumWays" value="16" />
-  <parameter name="mmu_tlbPtrSz" value="7" />
-  <parameter name="mmu_udtlbNumEntries" value="6" />
-  <parameter name="mmu_uitlbNumEntries" value="4" />
-  <parameter name="mpu_enabled" value="true" />
-  <parameter name="mpu_minDataRegionSize" value="12" />
-  <parameter name="mpu_minInstRegionSize" value="12" />
-  <parameter name="mpu_numOfDataRegion" value="8" />
-  <parameter name="mpu_numOfInstRegion" value="8" />
-  <parameter name="mpu_useLimit" value="false" />
-  <parameter name="mpx_enabled" value="false" />
-  <parameter name="mul_32_impl" value="3" />
-  <parameter name="mul_64_impl" value="0" />
-  <parameter name="mul_shift_choice" value="0" />
-  <parameter name="ocimem_ramBlockType" value="Automatic" />
-  <parameter name="ocimem_ramInit" value="false" />
-  <parameter name="regfile_ramBlockType" value="Automatic" />
-  <parameter name="resetOffset" value="0" />
-  <parameter name="resetSlave" value="sys_int_mem.s2" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="setting_HBreakTest" value="false" />
-  <parameter name="setting_HDLSimCachesCleared" value="true" />
-  <parameter name="setting_activateMonitors" value="true" />
-  <parameter name="setting_activateTestEndChecker" value="false" />
-  <parameter name="setting_activateTrace" value="true" />
-  <parameter name="setting_allow_break_inst" value="false" />
-  <parameter name="setting_alwaysEncrypt" value="true" />
-  <parameter name="setting_asic_add_scan_mode_input" value="false" />
-  <parameter name="setting_asic_enabled" value="false" />
-  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
-  <parameter name="setting_asic_third_party_synthesis" value="false" />
-  <parameter name="setting_avalonDebugPortPresent" value="false" />
-  <parameter name="setting_bhtPtrSz" value="8" />
-  <parameter name="setting_bigEndian" value="false" />
-  <parameter name="setting_branchpredictiontype" value="Dynamic" />
-  <parameter name="setting_breakslaveoveride" value="false" />
-  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
-  <parameter name="setting_dc_ecc_present" value="false" />
-  <parameter name="setting_disable_tmr_inj" value="false" />
-  <parameter name="setting_disableocitrace" value="false" />
-  <parameter name="setting_dtcm_ecc_present" value="false" />
-  <parameter name="setting_ecc_present" value="false" />
-  <parameter name="setting_ecc_sim_test_ports" value="false" />
-  <parameter name="setting_exportHostDebugPort" value="false" />
-  <parameter name="setting_exportPCB" value="false" />
-  <parameter name="setting_export_large_RAMs" value="false" />
-  <parameter name="setting_exportdebuginfo" value="false" />
-  <parameter name="setting_exportvectors" value="false" />
-  <parameter name="setting_fast_register_read" value="false" />
-  <parameter name="setting_ic_ecc_present" value="true" />
-  <parameter name="setting_interruptControllerType" value="Internal" />
-  <parameter name="setting_itcm_ecc_present" value="false" />
-  <parameter name="setting_mmu_ecc_present" value="true" />
-  <parameter name="setting_oci_export_jtag_signals" value="false" />
-  <parameter name="setting_oci_version" value="1" />
-  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
-  <parameter name="setting_removeRAMinit" value="false" />
-  <parameter name="setting_rf_ecc_present" value="true" />
-  <parameter name="setting_shadowRegisterSets" value="0" />
-  <parameter name="setting_showInternalSettings" value="false" />
-  <parameter name="setting_showUnpublishedSettings" value="false" />
-  <parameter name="setting_support31bitdcachebypass" value="true" />
-  <parameter name="setting_usedesignware" value="false" />
-  <parameter name="shift_rot_impl" value="0" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="27" />
-  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x5208000' end='0x5209000' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="27" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s2' start='0x5208000' end='0x5209000' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
-  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
-  <parameter name="tmr_enabled" value="false" />
-  <parameter name="tracefilename" value="" />
-  <parameter name="userDefinedSettings" value="" />
- </module>
- <module
-   name="sys_ddr3_cntrl"
-   kind="altera_mem_if_ddr3_emif"
-   version="14.1"
-   enabled="1">
-  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-  <parameter name="AC_PACKAGE_DESKEW" value="false" />
-  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-  <parameter name="ADDR_ORDER" value="0" />
-  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
-  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-  <parameter name="ADVANCED_CK_PHASES" value="false" />
-  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
-  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-  <parameter name="AP_MODE" value="false" />
-  <parameter name="AP_MODE_EN" value="0" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_PD_CYCLES" value="0" />
-  <parameter name="AUTO_POWERDN_EN" value="false" />
-  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-  <parameter name="AVL_MAX_SIZE" value="256" />
-  <parameter name="BYTE_ENABLE" value="true" />
-  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="CALIBRATION_MODE" value="Skip" />
-  <parameter name="CALIB_REG_WIDTH" value="8" />
-  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-  <parameter name="CFG_REORDER_DATA" value="true" />
-  <parameter name="CFG_TCCD_NS" value="2.5" />
-  <parameter name="COMMAND_PHASE" value="0.0" />
-  <parameter name="CONTROLLER_LATENCY" value="5" />
-  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
-  <parameter name="CTL_AUTOPCH_EN" value="false" />
-  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
-  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="CTL_CSR_ENABLED" value="false" />
-  <parameter name="CTL_CSR_READ_ONLY" value="1" />
-  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
-  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-  <parameter name="CTL_ECC_ENABLED" value="false" />
-  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
-  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
-  <parameter name="CTL_HRB_ENABLED" value="false" />
-  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTL_USR_REFRESH_EN" value="false" />
-  <parameter name="CTL_ZQCAL_EN" value="false" />
-  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
-  <parameter name="DAT_DATA_WIDTH" value="32" />
-  <parameter name="DEBUG_MODE" value="false" />
-  <parameter name="DEVICE_DEPTH" value="1" />
-  <parameter name="DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
-  <parameter name="DISCRETE_FLY_BY" value="true" />
-  <parameter name="DLL_SHARING_MODE" value="None" />
-  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
-  <parameter name="DUPLICATE_AC" value="false" />
-  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
-  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-  <parameter name="ENABLE_BONDING" value="false" />
-  <parameter name="ENABLE_BURST_MERGE" value="false" />
-  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
-  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
-  <parameter name="ENABLE_ISS_PROBES" value="false" />
-  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
-  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-  <parameter name="ENABLE_USER_ECC" value="false" />
-  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
-  <parameter name="EXTRA_SETTINGS" value="" />
-  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
-  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
-  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-  <parameter name="HARD_EMIF" value="false" />
-  <parameter name="HCX_COMPAT_MODE" value="false" />
-  <parameter name="HHP_HPS" value="false" />
-  <parameter name="HHP_HPS_SIMULATION" value="false" />
-  <parameter name="HHP_HPS_VERIFICATION" value="false" />
-  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
-  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="IS_ES_DEVICE" value="false" />
-  <parameter name="LOCAL_ID_WIDTH" value="8" />
-  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x0" />
-  <parameter name="MARGIN_VARIATION_TEST" value="false" />
-  <parameter name="MAX_PENDING_RD_CMD" value="32" />
-  <parameter name="MAX_PENDING_WR_CMD" value="16" />
-  <parameter name="MEM_ASR" value="Manual" />
-  <parameter name="MEM_ATCL" value="Disabled" />
-  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
-  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
-  <parameter name="MEM_BL" value="OTF" />
-  <parameter name="MEM_BT" value="Sequential" />
-  <parameter name="MEM_CK_PHASE" value="0.0" />
-  <parameter name="MEM_CK_WIDTH" value="1" />
-  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
-  <parameter name="MEM_CLK_FREQ" value="400.0" />
-  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
-  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_CS_WIDTH" value="1" />
-  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
-  <parameter name="MEM_DLL_EN" value="true" />
-  <parameter name="MEM_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DQ_WIDTH" value="64" />
-  <parameter name="MEM_DRV_STR" value="RZQ/6" />
-  <parameter name="MEM_FORMAT" value="DISCRETE" />
-  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
-  <parameter name="MEM_IF_DQSN_EN" value="true" />
-  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-  <parameter name="MEM_INIT_EN" value="false" />
-  <parameter name="MEM_INIT_FILE" value="" />
-  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
-  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_PD" value="DLL off" />
-  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
-  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
-  <parameter name="MEM_RTT_WR" value="RZQ/4" />
-  <parameter name="MEM_SRT" value="Normal" />
-  <parameter name="MEM_TCL" value="11" />
-  <parameter name="MEM_TFAW_NS" value="30.0" />
-  <parameter name="MEM_TINIT_US" value="500" />
-  <parameter name="MEM_TMRD_CK" value="4" />
-  <parameter name="MEM_TRAS_NS" value="35.0" />
-  <parameter name="MEM_TRCD_NS" value="13.75" />
-  <parameter name="MEM_TREFI_US" value="7.8" />
-  <parameter name="MEM_TRFC_NS" value="110.0" />
-  <parameter name="MEM_TRP_NS" value="13.75" />
-  <parameter name="MEM_TRRD_NS" value="6.0" />
-  <parameter name="MEM_TRTP_NS" value="7.5" />
-  <parameter name="MEM_TWR_NS" value="15.0" />
-  <parameter name="MEM_TWTR" value="6" />
-  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
-  <parameter name="MEM_VENDOR" value="Micron" />
-  <parameter name="MEM_VERBOSE" value="true" />
-  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
-  <parameter name="MEM_WTCL" value="8" />
-  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-  <parameter name="MULTICAST_EN" value="false" />
-  <parameter name="NEXTGEN" value="true" />
-  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
-  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
-  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_OF_PORTS" value="1" />
-  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
-  <parameter name="OCT_SHARING_MODE" value="None" />
-  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="PACKAGE_DESKEW" value="false" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="PHY_CSR_ENABLED" value="false" />
-  <parameter name="PHY_ONLY" value="false" />
-  <parameter name="PINGPONGPHY_EN" value="false" />
-  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
-  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_LOCATION" value="Top_Bottom" />
-  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_SHARING_MODE" value="None" />
-  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="POWER_OF_TWO_BUS" value="false" />
-  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-  <parameter name="RATE" value="Quarter" />
-  <parameter name="RDIMM_CONFIG" value="0" />
-  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-  <parameter name="READ_FIFO_SIZE" value="8" />
-  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
-  <parameter name="REFRESH_INTERVAL" value="15000" />
-  <parameter name="REF_CLK_FREQ" value="100.0" />
-  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-  <parameter name="SEQUENCER_TYPE" value="NIOS" />
-  <parameter name="SEQ_MODE" value="0" />
-  <parameter name="SKIP_MEM_INIT" value="true" />
-  <parameter name="SOPC_COMPAT_RESET" value="false" />
-  <parameter name="SPEED_GRADE" value="3" />
-  <parameter name="STARVE_LIMIT" value="10" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
-  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_TDH" value="0.0" />
-  <parameter name="TIMING_BOARD_TDS" value="0.0" />
-  <parameter name="TIMING_BOARD_TIH" value="0.0" />
-  <parameter name="TIMING_BOARD_TIS" value="0.0" />
-  <parameter name="TIMING_TDH" value="45" />
-  <parameter name="TIMING_TDQSCK" value="255" />
-  <parameter name="TIMING_TDQSCKDL" value="1200" />
-  <parameter name="TIMING_TDQSCKDM" value="900" />
-  <parameter name="TIMING_TDQSCKDS" value="450" />
-  <parameter name="TIMING_TDQSQ" value="100" />
-  <parameter name="TIMING_TDQSS" value="0.27" />
-  <parameter name="TIMING_TDS" value="10" />
-  <parameter name="TIMING_TDSH" value="0.18" />
-  <parameter name="TIMING_TDSS" value="0.18" />
-  <parameter name="TIMING_TIH" value="120" />
-  <parameter name="TIMING_TIS" value="170" />
-  <parameter name="TIMING_TQH" value="0.38" />
-  <parameter name="TIMING_TQSH" value="0.4" />
-  <parameter name="TRACKING_ERROR_TEST" value="false" />
-  <parameter name="TRACKING_WATCH_TEST" value="false" />
-  <parameter name="TREFI" value="35100" />
-  <parameter name="TRFC" value="350" />
-  <parameter name="USER_DEBUG_LEVEL" value="1" />
-  <parameter name="USE_AXI_ADAPTOR" value="false" />
-  <parameter name="USE_FAKE_PHY" value="false" />
-  <parameter name="USE_MEM_CLK_FREQ" value="false" />
-  <parameter name="USE_MM_ADAPTOR" value="true" />
-  <parameter name="USE_SEQUENCER_BFM" value="false" />
-  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
- </module>
- <module
-   name="sys_ddr3_cpuconnect"
-   kind="altera_address_span_extender"
-   version="14.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="BURSTCOUNT_WIDTH" value="1" />
-  <parameter name="DATA_WIDTH" value="512" />
-  <parameter name="MASTER_ADDRESS_DEF" value="0" />
-  <parameter name="MASTER_ADDRESS_WIDTH" value="30" />
-  <parameter name="MAX_PENDING_READS" value="1" />
-  <parameter name="SLAVE_ADDRESS_WIDTH" value="20" />
-  <parameter name="SUB_WINDOW_COUNT" value="1" />
-  <parameter name="TERMINATE_SLAVE_PORT" value="false" />
- </module>
- <module
-   name="sys_ddr3_dmaconnect"
-   kind="altera_avalon_mm_clock_crossing_bridge"
-   version="14.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="30" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="166666666" />
-  <parameter name="COMMAND_FIFO_DEPTH" value="4" />
-  <parameter name="DATA_WIDTH" value="512" />
-  <parameter name="MASTER_SYNC_DEPTH" value="2" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="RESPONSE_FIFO_DEPTH" value="4" />
-  <parameter name="SLAVE_SYNC_DEPTH" value="2" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="30" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_ddr3_interconnect"
-   kind="altera_avalon_mm_clock_crossing_bridge"
-   version="14.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="30" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="COMMAND_FIFO_DEPTH" value="4" />
-  <parameter name="DATA_WIDTH" value="512" />
-  <parameter name="MASTER_SYNC_DEPTH" value="2" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="RESPONSE_FIFO_DEPTH" value="4" />
-  <parameter name="SLAVE_SYNC_DEPTH" value="2" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="30" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
- </module>
- <module name="sys_ethernet" kind="altera_eth_tse" version="14.1" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="core_variation" value="MAC_ONLY" />
-  <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="eg_addr" value="11" />
-  <parameter name="ena_hash" value="false" />
-  <parameter name="enable_alt_reconfig" value="false" />
-  <parameter name="enable_ecc" value="false" />
-  <parameter name="enable_ena" value="32" />
-  <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_hd_logic" value="true" />
-  <parameter name="enable_mac_flow_ctrl" value="true" />
-  <parameter name="enable_mac_vlan" value="false" />
-  <parameter name="enable_magic_detect" value="true" />
-  <parameter name="enable_ptp_1step" value="false" />
-  <parameter name="enable_sgmii" value="false" />
-  <parameter name="enable_shift16" value="true" />
-  <parameter name="enable_sup_addr" value="false" />
-  <parameter name="enable_timestamping" value="false" />
-  <parameter name="enable_use_internal_fifo" value="true" />
-  <parameter name="export_pwrdn" value="false" />
-  <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ifGMII" value="RGMII" />
-  <parameter name="ing_addr" value="11" />
-  <parameter name="max_channels" value="1" />
-  <parameter name="mdio_clk_div" value="30" />
-  <parameter name="nf_phyip_rcfg_enable" value="false" />
-  <parameter name="phy_identifier" value="0" />
-  <parameter name="phyip_en_synce_support" value="false" />
-  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
-  <parameter name="phyip_pll_type" value="CMU" />
-  <parameter name="phyip_pma_bonding_mode" value="x1" />
-  <parameter name="starting_channel_number" value="0" />
-  <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="transceiver_type" value="NONE" />
-  <parameter name="tstamp_fp_width" value="4" />
-  <parameter name="useMDIO" value="true" />
-  <parameter name="use_misc_ports" value="true" />
- </module>
- <module
-   name="sys_ethernet_desc_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="14.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_ethernet_desc_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="4096" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sys_ethernet_dma_rx"
-   kind="altera_avalon_sgdma"
-   version="14.1"
-   enabled="1">
-  <parameter name="addressWidth" value="32" />
-  <parameter name="alwaysDoMaxBurst" value="true" />
-  <parameter name="avalonMMByteReorderMode" value="0" />
-  <parameter name="dataTransferFIFODepth" value="2" />
-  <parameter name="deviceFamilyString" value="Arria V" />
-  <parameter name="enableBurstTransfers" value="false" />
-  <parameter name="enableDescriptorReadMasterBurst" value="false" />
-  <parameter name="enableUnalignedTransfers" value="false" />
-  <parameter name="internalFIFODepth" value="2" />
-  <parameter name="readBlockDataWidth" value="32" />
-  <parameter name="readBurstcountWidth" value="4" />
-  <parameter name="sinkErrorWidth" value="0" />
-  <parameter name="sourceErrorWidth" value="0" />
-  <parameter name="transferMode" value="STREAM_TO_MEMORY" />
-  <parameter name="writeBurstcountWidth" value="4" />
- </module>
- <module
-   name="sys_ethernet_dma_tx"
-   kind="altera_avalon_sgdma"
-   version="14.1"
-   enabled="1">
-  <parameter name="addressWidth" value="32" />
-  <parameter name="alwaysDoMaxBurst" value="true" />
-  <parameter name="avalonMMByteReorderMode" value="0" />
-  <parameter name="dataTransferFIFODepth" value="2" />
-  <parameter name="deviceFamilyString" value="Arria V" />
-  <parameter name="enableBurstTransfers" value="false" />
-  <parameter name="enableDescriptorReadMasterBurst" value="false" />
-  <parameter name="enableUnalignedTransfers" value="false" />
-  <parameter name="internalFIFODepth" value="2" />
-  <parameter name="readBlockDataWidth" value="32" />
-  <parameter name="readBurstcountWidth" value="4" />
-  <parameter name="sinkErrorWidth" value="0" />
-  <parameter name="sourceErrorWidth" value="0" />
-  <parameter name="transferMode" value="MEMORY_TO_STREAM" />
-  <parameter name="writeBurstcountWidth" value="4" />
- </module>
- <module name="sys_gpio" kind="altera_avalon_pio" version="14.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="14.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="id" value="0" />
-  <parameter name="timestamp" value="0" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="14.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="1572864" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sys_jesd204b_s1"
-   kind="altera_jesd204"
-   version="14.1"
-   enabled="1">
-  <parameter name="ADJCNT" value="0" />
-  <parameter name="ADJDIR" value="0" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="BID" value="0" />
-  <parameter name="CF" value="0" />
-  <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX" />
-  <parameter name="DEVICE_FAMILY" value="Arria V" />
-  <parameter name="DID" value="0" />
-  <parameter name="DLB_TEST" value="0" />
-  <parameter name="ECC_EN" value="0" />
-  <parameter name="HD" value="0" />
-  <parameter name="JESDV" value="1" />
-  <parameter name="K" value="4" />
-  <parameter name="L" value="8" />
-  <parameter name="LID0" value="0" />
-  <parameter name="LID1" value="1" />
-  <parameter name="LID2" value="2" />
-  <parameter name="LID3" value="3" />
-  <parameter name="LID4" value="4" />
-  <parameter name="LID5" value="5" />
-  <parameter name="LID6" value="6" />
-  <parameter name="LID7" value="7" />
-  <parameter name="M" value="32" />
-  <parameter name="N" value="14" />
-  <parameter name="N_PRIME" value="16" />
-  <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="80.0" />
-  <parameter name="RES1" value="0" />
-  <parameter name="RES2" value="0" />
-  <parameter name="S" value="1" />
-  <parameter name="SCR" value="1" />
-  <parameter name="SUBCLASSV" value="0" />
-  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
-  <parameter name="TEST_COMPONENTS_EN" value="false" />
-  <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="bonded" />
-  <parameter name="lane_rate" value="3200.0" />
-  <parameter name="part_trait_bd" value="ARRIAVB7" />
-  <parameter name="part_trait_dp" value="5AGTFD7K3F40I3" />
-  <parameter name="pll_reconfig_enable" value="false" />
-  <parameter name="pll_type" value="CMU" />
-  <parameter name="rcfg_jtag_enable" value="false" />
-  <parameter name="sdc_constraint" value="1.0" />
-  <parameter name="wrapper_opt" value="base_phy" />
- </module>
- <module
-   name="sys_jesd204b_s1_pll"
-   kind="altera_pll"
-   version="14.1"
-   enabled="1">
-  <parameter name="debug_print_output" value="false" />
-  <parameter name="debug_use_rbc_taf_method" value="false" />
-  <parameter name="device" value="5AGTFD7K3F40I3" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
-  <parameter name="gui_actual_phase_shift0" value="0" />
-  <parameter name="gui_actual_phase_shift1" value="0" />
-  <parameter name="gui_actual_phase_shift10" value="0" />
-  <parameter name="gui_actual_phase_shift11" value="0" />
-  <parameter name="gui_actual_phase_shift12" value="0" />
-  <parameter name="gui_actual_phase_shift13" value="0" />
-  <parameter name="gui_actual_phase_shift14" value="0" />
-  <parameter name="gui_actual_phase_shift15" value="0" />
-  <parameter name="gui_actual_phase_shift16" value="0" />
-  <parameter name="gui_actual_phase_shift17" value="0" />
-  <parameter name="gui_actual_phase_shift2" value="0" />
-  <parameter name="gui_actual_phase_shift3" value="0" />
-  <parameter name="gui_actual_phase_shift4" value="0" />
-  <parameter name="gui_actual_phase_shift5" value="0" />
-  <parameter name="gui_actual_phase_shift6" value="0" />
-  <parameter name="gui_actual_phase_shift7" value="0" />
-  <parameter name="gui_actual_phase_shift8" value="0" />
-  <parameter name="gui_actual_phase_shift9" value="0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_channel_spacing" value="0.0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_device_speed_grade" value="2" />
-  <parameter name="gui_divide_factor_c0" value="1" />
-  <parameter name="gui_divide_factor_c1" value="1" />
-  <parameter name="gui_divide_factor_c10" value="1" />
-  <parameter name="gui_divide_factor_c11" value="1" />
-  <parameter name="gui_divide_factor_c12" value="1" />
-  <parameter name="gui_divide_factor_c13" value="1" />
-  <parameter name="gui_divide_factor_c14" value="1" />
-  <parameter name="gui_divide_factor_c15" value="1" />
-  <parameter name="gui_divide_factor_c16" value="1" />
-  <parameter name="gui_divide_factor_c17" value="1" />
-  <parameter name="gui_divide_factor_c2" value="1" />
-  <parameter name="gui_divide_factor_c3" value="1" />
-  <parameter name="gui_divide_factor_c4" value="1" />
-  <parameter name="gui_divide_factor_c5" value="1" />
-  <parameter name="gui_divide_factor_c6" value="1" />
-  <parameter name="gui_divide_factor_c7" value="1" />
-  <parameter name="gui_divide_factor_c8" value="1" />
-  <parameter name="gui_divide_factor_c9" value="1" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50" />
-  <parameter name="gui_duty_cycle1" value="50" />
-  <parameter name="gui_duty_cycle10" value="50" />
-  <parameter name="gui_duty_cycle11" value="50" />
-  <parameter name="gui_duty_cycle12" value="50" />
-  <parameter name="gui_duty_cycle13" value="50" />
-  <parameter name="gui_duty_cycle14" value="50" />
-  <parameter name="gui_duty_cycle15" value="50" />
-  <parameter name="gui_duty_cycle16" value="50" />
-  <parameter name="gui_duty_cycle17" value="50" />
-  <parameter name="gui_duty_cycle2" value="50" />
-  <parameter name="gui_duty_cycle3" value="50" />
-  <parameter name="gui_duty_cycle4" value="50" />
-  <parameter name="gui_duty_cycle5" value="50" />
-  <parameter name="gui_duty_cycle6" value="50" />
-  <parameter name="gui_duty_cycle7" value="50" />
-  <parameter name="gui_duty_cycle8" value="50" />
-  <parameter name="gui_duty_cycle9" value="50" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="false" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_number_of_clocks" value="1" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="80.0" />
-  <parameter name="gui_output_clock_frequency1" value="100.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0" />
-  <parameter name="gui_phase_shift1" value="0" />
-  <parameter name="gui_phase_shift10" value="0" />
-  <parameter name="gui_phase_shift11" value="0" />
-  <parameter name="gui_phase_shift12" value="0" />
-  <parameter name="gui_phase_shift13" value="0" />
-  <parameter name="gui_phase_shift14" value="0" />
-  <parameter name="gui_phase_shift15" value="0" />
-  <parameter name="gui_phase_shift16" value="0" />
-  <parameter name="gui_phase_shift17" value="0" />
-  <parameter name="gui_phase_shift2" value="0" />
-  <parameter name="gui_phase_shift3" value="0" />
-  <parameter name="gui_phase_shift4" value="0" />
-  <parameter name="gui_phase_shift5" value="0" />
-  <parameter name="gui_phase_shift6" value="0" />
-  <parameter name="gui_phase_shift7" value="0" />
-  <parameter name="gui_phase_shift8" value="0" />
-  <parameter name="gui_phase_shift9" value="0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="Off" />
-  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
-  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="80.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_locked" value="true" />
- </module>
- <module
-   name="sys_jesd204b_s1_ref_clk"
-   kind="altera_clock_bridge"
-   version="14.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="80000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module
-   name="sys_jesd204b_s1_rx_clk"
-   kind="altera_clock_bridge"
-   version="14.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="80000000" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_pll" kind="altera_pll" version="14.1" enabled="1">
-  <parameter name="debug_print_output" value="false" />
-  <parameter name="debug_use_rbc_taf_method" value="false" />
-  <parameter name="device" value="5AGTFD7K3F40I3" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency1" value="166.666666 MHz" />
-  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
-  <parameter name="gui_actual_phase_shift0" value="0" />
-  <parameter name="gui_actual_phase_shift1" value="0" />
-  <parameter name="gui_actual_phase_shift10" value="0" />
-  <parameter name="gui_actual_phase_shift11" value="0" />
-  <parameter name="gui_actual_phase_shift12" value="0" />
-  <parameter name="gui_actual_phase_shift13" value="0" />
-  <parameter name="gui_actual_phase_shift14" value="0" />
-  <parameter name="gui_actual_phase_shift15" value="0" />
-  <parameter name="gui_actual_phase_shift16" value="0" />
-  <parameter name="gui_actual_phase_shift17" value="0" />
-  <parameter name="gui_actual_phase_shift2" value="0" />
-  <parameter name="gui_actual_phase_shift3" value="0" />
-  <parameter name="gui_actual_phase_shift4" value="0" />
-  <parameter name="gui_actual_phase_shift5" value="0" />
-  <parameter name="gui_actual_phase_shift6" value="0" />
-  <parameter name="gui_actual_phase_shift7" value="0" />
-  <parameter name="gui_actual_phase_shift8" value="0" />
-  <parameter name="gui_actual_phase_shift9" value="0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_channel_spacing" value="0.0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_device_speed_grade" value="2" />
-  <parameter name="gui_divide_factor_c0" value="1" />
-  <parameter name="gui_divide_factor_c1" value="1" />
-  <parameter name="gui_divide_factor_c10" value="1" />
-  <parameter name="gui_divide_factor_c11" value="1" />
-  <parameter name="gui_divide_factor_c12" value="1" />
-  <parameter name="gui_divide_factor_c13" value="1" />
-  <parameter name="gui_divide_factor_c14" value="1" />
-  <parameter name="gui_divide_factor_c15" value="1" />
-  <parameter name="gui_divide_factor_c16" value="1" />
-  <parameter name="gui_divide_factor_c17" value="1" />
-  <parameter name="gui_divide_factor_c2" value="1" />
-  <parameter name="gui_divide_factor_c3" value="1" />
-  <parameter name="gui_divide_factor_c4" value="1" />
-  <parameter name="gui_divide_factor_c5" value="1" />
-  <parameter name="gui_divide_factor_c6" value="1" />
-  <parameter name="gui_divide_factor_c7" value="1" />
-  <parameter name="gui_divide_factor_c8" value="1" />
-  <parameter name="gui_divide_factor_c9" value="1" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50" />
-  <parameter name="gui_duty_cycle1" value="50" />
-  <parameter name="gui_duty_cycle10" value="50" />
-  <parameter name="gui_duty_cycle11" value="50" />
-  <parameter name="gui_duty_cycle12" value="50" />
-  <parameter name="gui_duty_cycle13" value="50" />
-  <parameter name="gui_duty_cycle14" value="50" />
-  <parameter name="gui_duty_cycle15" value="50" />
-  <parameter name="gui_duty_cycle16" value="50" />
-  <parameter name="gui_duty_cycle17" value="50" />
-  <parameter name="gui_duty_cycle2" value="50" />
-  <parameter name="gui_duty_cycle3" value="50" />
-  <parameter name="gui_duty_cycle4" value="50" />
-  <parameter name="gui_duty_cycle5" value="50" />
-  <parameter name="gui_duty_cycle6" value="50" />
-  <parameter name="gui_duty_cycle7" value="50" />
-  <parameter name="gui_duty_cycle8" value="50" />
-  <parameter name="gui_duty_cycle9" value="50" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="false" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_number_of_clocks" value="5" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="100.0" />
-  <parameter name="gui_output_clock_frequency1" value="166.666666" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="125.0" />
-  <parameter name="gui_output_clock_frequency3" value="25.0" />
-  <parameter name="gui_output_clock_frequency4" value="2.5" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0" />
-  <parameter name="gui_phase_shift1" value="0" />
-  <parameter name="gui_phase_shift10" value="0" />
-  <parameter name="gui_phase_shift11" value="0" />
-  <parameter name="gui_phase_shift12" value="0" />
-  <parameter name="gui_phase_shift13" value="0" />
-  <parameter name="gui_phase_shift14" value="0" />
-  <parameter name="gui_phase_shift15" value="0" />
-  <parameter name="gui_phase_shift16" value="0" />
-  <parameter name="gui_phase_shift17" value="0" />
-  <parameter name="gui_phase_shift2" value="0" />
-  <parameter name="gui_phase_shift3" value="0" />
-  <parameter name="gui_phase_shift4" value="0" />
-  <parameter name="gui_phase_shift5" value="0" />
-  <parameter name="gui_phase_shift6" value="0" />
-  <parameter name="gui_phase_shift7" value="0" />
-  <parameter name="gui_phase_shift8" value="0" />
-  <parameter name="gui_phase_shift9" value="0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="Off" />
-  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
-  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="100.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_locked" value="true" />
- </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="14.1" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="0" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="100000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="5" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="12500000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
- <module
-   name="sys_tcm_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="14.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tcm_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="4096" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sys_timer"
-   kind="altera_avalon_timer"
-   version="14.1"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
- </module>
- <module
-   name="sys_uart"
-   kind="altera_avalon_jtag_uart"
-   version="14.1"
-   enabled="1">
-  <parameter name="allowMultipleConnections" value="false" />
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="100000000" />
-  <parameter name="hubInstanceID" value="0" />
-  <parameter name="readBufferDepth" value="64" />
-  <parameter name="readIRQThreshold" value="8" />
-  <parameter name="simInputCharacterStream" value="" />
-  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
-  <parameter name="useRegistersForReadBuffer" value="false" />
-  <parameter name="useRegistersForWriteBuffer" value="false" />
-  <parameter name="useRelativePathForSimFile" value="false" />
-  <parameter name="writeBufferDepth" value="64" />
-  <parameter name="writeIRQThreshold" value="8" />
- </module>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_uart.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a4e0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_ddr3_cpuconnect.cntl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a4d0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet.control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a4d8" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a440" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05209800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_jesd204b_s1.jesd204_rx_avs">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x04000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_timer.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a4a0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_gpio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a4c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="axi_dmac.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05204000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="axi_ad9671_0.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="axi_ad9671_1.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05210000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="axi_ad9671_2.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05220000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="axi_ad9671_3.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05230000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_spi.spi_control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0520a480" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_ddr3_cpuconnect.windowed_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ethernet_dma_tx.descriptor_read"
-   end="sys_ethernet_desc_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ethernet_dma_rx.descriptor_read"
-   end="sys_ethernet_desc_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ethernet_dma_tx.descriptor_write"
-   end="sys_ethernet_desc_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ethernet_dma_rx.descriptor_write"
-   end="sys_ethernet_desc_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ddr3_cpuconnect.expanded_master"
-   end="sys_ddr3_interconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.instruction_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05209800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.instruction_master"
-   end="sys_int_mem.s2">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.instruction_master"
-   end="sys_ddr3_cpuconnect.windowed_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ddr3_interconnect.m0"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ddr3_dmaconnect.m0"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="axi_dmac.m_dest_axi"
-   end="sys_ddr3_dmaconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ethernet_dma_tx.m_read"
-   end="sys_ddr3_interconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_ethernet_dma_rx.m_write"
-   end="sys_ddr3_interconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.tightly_coupled_data_master_0"
-   end="sys_tcm_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05208000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.tightly_coupled_instruction_master_0"
-   end="sys_tcm_mem.s2">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x05208000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon_streaming"
-   version="14.1"
-   start="sys_ethernet_dma_tx.out"
-   end="sys_ethernet.transmit" />
- <connection
-   kind="avalon_streaming"
-   version="14.1"
-   start="sys_ethernet.receive"
-   end="sys_ethernet_dma_rx.in" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_ddr3_cntrl.afi_clk"
-   end="sys_ddr3_interconnect.m0_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_ddr3_cntrl.afi_clk"
-   end="sys_ddr3_dmaconnect.m0_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_clk.clk"
-   end="sys_ddr3_cntrl.pll_ref_clk" />
- <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_pll.refclk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_jesd204b_s1_ref_clk.out_clk"
-   end="sys_jesd204b_s1.pll_ref_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_jesd204b_s1_ref_clk.out_clk"
-   end="sys_jesd204b_s1_pll.refclk" />
- <connection kind="clock" version="14.1" start="sys_pll.outclk0" end="sys_cpu.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_uart.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_timer.clk" />
- <connection kind="clock" version="14.1" start="sys_pll.outclk0" end="sys_id.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ethernet_dma_rx.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ethernet_dma_tx.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_gpio.clk" />
- <connection kind="clock" version="14.1" start="sys_pll.outclk0" end="sys_spi.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ethernet_desc_mem.clk1" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_tcm_mem.clk1" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_int_mem.clk2" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_tcm_mem.clk2" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ddr3_cpuconnect.clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ethernet.control_port_clock_connection" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_jesd204b_s1_pll.outclk0"
-   end="sys_jesd204b_s1_rx_clk.in_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_jesd204b_s1.jesd204_rx_avs_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ethernet.receive_clock_connection" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_jesd204b_s1_pll.outclk0"
-   end="sys_jesd204b_s1.rxlink_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ddr3_interconnect.s0_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="axi_ad9671_0.s_axi_clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="axi_ad9671_1.s_axi_clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="axi_ad9671_2.s_axi_clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="axi_ad9671_3.s_axi_clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ethernet.transmit_clock_connection" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk1"
-   end="axi_dmac.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk1"
-   end="sys_ddr3_dmaconnect.s0_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk1"
-   end="axi_dmac.s_axi_clock" />
- <connection
-   kind="interrupt"
-   version="14.1"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_rx.csr_irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.1"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_tx.csr_irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.1"
-   start="sys_cpu.irq"
-   end="sys_uart.irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.1"
-   start="sys_cpu.irq"
-   end="sys_timer.irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection kind="interrupt" version="14.1" start="sys_cpu.irq" end="sys_spi.irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.1"
-   start="sys_cpu.irq"
-   end="sys_gpio.irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_ddr3_cntrl.afi_reset"
-   end="sys_ddr3_interconnect.m0_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_ddr3_cntrl.afi_reset"
-   end="sys_ddr3_dmaconnect.m0_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_ddr3_cntrl.afi_reset"
-   end="axi_dmac.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_cntrl.global_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_jesd204b_s1.jesd204_rx_avs_rst_n" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="axi_dmac.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_pll.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_uart.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_timer.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet_dma_rx.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet_dma_tx.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_gpio.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_spi.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_jesd204b_s1_pll.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_cpuconnect.reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_int_mem.reset1" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet_desc_mem.reset1" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_tcm_mem.reset1" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_int_mem.reset2" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_tcm_mem.reset2" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet.reset_connection" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_jesd204b_s1.rxlink_rst_n" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_interconnect.s0_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_dmaconnect.s0_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="axi_dmac.s_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="axi_ad9671_0.s_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="axi_ad9671_1.s_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="axi_ad9671_2.s_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="axi_ad9671_3.s_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_cntrl.soft_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
-</system>
diff --git a/projects/usdrx1/a5gt/system_constr.sdc b/projects/usdrx1/a5gt/system_constr.sdc
index 578df95d7..f77cb2bc6 100644
--- a/projects/usdrx1/a5gt/system_constr.sdc
+++ b/projects/usdrx1/a5gt/system_constr.sdc
@@ -1,29 +1,27 @@
 
-create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
-create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_ports {eth_tx_clk_out}]
-create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
-create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}]
+create_clock -period "10.000 ns"  -name sys_clk        [get_ports {sys_clk}]
+create_clock -period "12.500 ns"  -name ref_clk        [get_ports {ref_clk}]
+create_clock -period "8.000 ns"   -name eth_rx_clk     [get_ports {eth_rx_clk}]
 
 derive_pll_clocks
 derive_clock_uncertainty
 
-set clk_100m     {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
-set clk_166m     {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
-set clk_125m     {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}
-set clk_25m      {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}
-set clk_2m5      {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}
-set clk_rxlink   {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
+set_clock_groups -exclusive \
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+  -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
 
-set_clock_groups -asynchronous -group [get_clocks {n_clk_80m} ]
-set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ]
-set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ]
-set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ]
-set_clock_groups -asynchronous -group [get_clocks $clk_100m ]
-set_clock_groups -asynchronous -group [get_clocks $clk_166m ]
-set_clock_groups -asynchronous -group [get_clocks $clk_125m ]
-set_clock_groups -asynchronous -group [get_clocks $clk_25m ]
-set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ]
-set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ]
+set_false_path -to [get_registers {rx_sysref_m1}]
+
+set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\
+  -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
+
+set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
+  -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_clk}]
+
+set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\
+  -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
+
+set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
+  -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk}]
 
-set_false_path -from {sys_resetn} -to *
-set_false_path -from  * -to {sys_resetn}
diff --git a/projects/usdrx1/a5gt/system_project.tcl b/projects/usdrx1/a5gt/system_project.tcl
index 8bf4232aa..75a7e0e78 100644
--- a/projects/usdrx1/a5gt/system_project.tcl
+++ b/projects/usdrx1/a5gt/system_project.tcl
@@ -4,11 +4,14 @@ load_package flow
 source ../../scripts/adi_env.tcl
 project_new usdrx1_a5gt -overwrite
 
-source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
+source "../../common/a5gt/a5gt_system_assign.tcl"
 
-set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
-set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
 set_global_assignment -name VERILOG_FILE ../common/usdrx1_spi.v
+set_global_assignment -name VERILOG_FILE system_top.v
+set_global_assignment -name QSYS_FILE system_bd.qsys
+
+set_global_assignment -name SDC_FILE system_constr.sdc
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
 
 # reference clock
 
diff --git a/projects/usdrx1/a5gt/system_top.v b/projects/usdrx1/a5gt/system_top.v
index 31298ec5c..60e6c4f84 100644
--- a/projects/usdrx1/a5gt/system_top.v
+++ b/projects/usdrx1/a5gt/system_top.v
@@ -41,265 +41,205 @@ module system_top (
 
   // clock and resets
 
-  sys_clk,
-  sys_resetn,
+  input             sys_clk,
+  input             sys_resetn,
 
   // ddr3
 
-  ddr3_a,
-  ddr3_ba,
-  ddr3_clk_p,
-  ddr3_clk_n,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_dm,
-  ddr3_ras_n,
-  ddr3_cas_n,
-  ddr3_we_n,
-  ddr3_reset_n,
-  ddr3_dq,
-  ddr3_dqs_p,
-  ddr3_dqs_n,
-  ddr3_odt,
-  ddr3_rzq,
+  output            ddr3_clk_p,
+  output            ddr3_clk_n,
+  output  [ 13:0]   ddr3_a,
+  output  [  2:0]   ddr3_ba,
+  output            ddr3_cke,
+  output            ddr3_cs_n,
+  output            ddr3_odt,
+  output            ddr3_reset_n,
+  output            ddr3_we_n,
+  output            ddr3_ras_n,
+  output            ddr3_cas_n,
+  inout   [  7:0]   ddr3_dqs_p,
+  inout   [  7:0]   ddr3_dqs_n,
+  inout   [ 63:0]   ddr3_dq,
+  output  [  7:0]   ddr3_dm,
+  input             ddr3_rzq,
 
   // ethernet
 
-  eth_rx_clk,
-  eth_rx_data,
-  eth_rx_cntrl,
-  eth_tx_clk_out,
-  eth_tx_data,
-  eth_tx_cntrl,
-  eth_mdc,
-  eth_mdio_i,
-  eth_mdio_o,
-  eth_mdio_t,
-  eth_phy_resetn,
-  // board gpio
-
-  led_grn,
-  led_red,
-  push_buttons,
-  dip_switches,
-
-  // lane interface
-
-  ref_clk,
-  rx_data,
-  rx_sync,
-  rx_sysref,
-
-  // spi
-
-  spi_fout_enb_clk,
-  spi_fout_enb_mlo,
-  spi_fout_enb_rst,
-  spi_fout_enb_sync,
-  spi_fout_enb_sysref,
-  spi_fout_enb_trig,
-  spi_fout_clk,
-  spi_fout_sdio,
-  spi_afe_csn,
-  spi_afe_clk,
-  spi_afe_sdio,
-  spi_clk_csn,
-  spi_clk_clk,
-  spi_clk_sdio,
-
-  afe_rst,
-  afe_trig,
-
-  // gpio
-
-  dac_sleep,
-  dac_data,
-  afe_pdn,
-  afe_stby,
-  clk_resetn,
-  clk_syncn,
-  clk_status,
-  amp_disbn,
-  prc_sck,
-  prc_cnv,
-  prc_sdo_i,
-  prc_sdo_q);
-
-  // clock and resets
-
-  input             sys_clk;
-  input             sys_resetn;
-
-  // ddr3
-
-  output  [ 13:0]   ddr3_a;
-  output  [  2:0]   ddr3_ba;
-  output            ddr3_clk_p;
-  output            ddr3_clk_n;
-  output            ddr3_cke;
-  output            ddr3_cs_n;
-  output  [  7:0]   ddr3_dm;
-  output            ddr3_ras_n;
-  output            ddr3_cas_n;
-  output            ddr3_we_n;
-  output            ddr3_reset_n;
-  inout   [ 63:0]   ddr3_dq;
-  inout   [  7:0]   ddr3_dqs_p;
-  inout   [  7:0]   ddr3_dqs_n;
-  output            ddr3_odt;
-  input             ddr3_rzq;
-
-  // ethernet
-
-  input             eth_rx_clk;
-  input   [  3:0]   eth_rx_data;
-  input             eth_rx_cntrl;
-  output            eth_tx_clk_out;
-  output  [  3:0]   eth_tx_data;
-  output            eth_tx_cntrl;
-  output            eth_mdc;
-  input             eth_mdio_i;
-  output            eth_mdio_o;
-  output            eth_mdio_t;
-  output            eth_phy_resetn;
+  input             eth_rx_clk,
+  input   [  3:0]   eth_rx_data,
+  input             eth_rx_cntrl,
+  output            eth_tx_clk_out,
+  output  [  3:0]   eth_tx_data,
+  output            eth_tx_cntrl,
+  output            eth_mdc,
+  input             eth_mdio_i,
+  output            eth_mdio_o,
+  output            eth_mdio_t,
+  output            eth_phy_resetn,
 
   // board gpio
 
-  output  [  7:0]   led_grn;
-  output  [  7:0]   led_red;
-  input   [  2:0]   push_buttons;
-  input   [  7:0]   dip_switches;
+  output  [ 15:0]   gpio_bd_o,
+  input   [ 10:0]   gpio_bd_i,
 
   // lane interface
 
-  input             ref_clk;
-  input   [  7:0]   rx_data;
-  output            rx_sysref;
-  output            rx_sync;
+  input             ref_clk,
+  input   [  7:0]   rx_data,
+  output            rx_sync,
+  output            rx_sysref,
 
   // spi
 
-  output            spi_fout_enb_clk;
-  output            spi_fout_enb_mlo;
-  output            spi_fout_enb_rst;
-  output            spi_fout_enb_sync;
-  output            spi_fout_enb_sysref;
-  output            spi_fout_enb_trig;
-  output            spi_fout_clk;
-  output            spi_fout_sdio;
-  output  [  3:0]   spi_afe_csn;
-  output            spi_afe_clk;
-  inout             spi_afe_sdio;
-  output            spi_clk_csn;
-  output            spi_clk_clk;
-  inout             spi_clk_sdio;
-
-  output            afe_rst;
-  output            afe_trig;
+  output            spi_fout_enb_clk,
+  output            spi_fout_enb_mlo,
+  output            spi_fout_enb_rst,
+  output            spi_fout_enb_sync,
+  output            spi_fout_enb_sysref,
+  output            spi_fout_enb_trig,
+  output            spi_fout_clk,
+  output            spi_fout_sdio,
+  output  [  3:0]   spi_afe_csn,
+  output            spi_afe_clk,
+  inout             spi_afe_sdio,
+  output            spi_clk_csn,
+  output            spi_clk_clk,
+  inout             spi_clk_sdio,
 
   // gpio
 
-  output            dac_sleep;
-  output  [ 13:0]   dac_data;
-  output            afe_pdn;
-  output            afe_stby;
-  output            clk_resetn;
-  output            clk_syncn;
-  input             clk_status;
-  output            amp_disbn;
-  inout             prc_sck;
-  inout             prc_cnv;
-  inout             prc_sdo_i;
-  inout             prc_sdo_q;
+  output            clk_resetn,
+  output            clk_syncn,
+  input             clk_status,
+  output            afe_rst,
+  output            afe_trig,
+  output            afe_pdn,
+  output            afe_stby,
+  output  [ 13:0]   dac_data,
+  output            dac_sleep,
+  output            amp_disbn,
+  output            prc_sck,
+  output            prc_cnv,
+  input             prc_sdo_i,
+  input             prc_sdo_q);
 
   // internal registers
 
-  reg               rx_sysref_m1 = 'd0;
-  reg               rx_sysref_m2 = 'd0;
-  reg               rx_sysref_m3 = 'd0;
-  reg               rx_sysref = 'd0;
-  reg               dma_sync = 'd0;
-  reg               dma_wr = 'd0;
-  reg               adc_dovf;
-  reg     [511:0]   dma_data = 'd0;
-  reg               rx_sof_0_s = 'd0;
-  reg               rx_sof_1_s = 'd0;
-  reg               rx_sof_2_s = 'd0;
-  reg               rx_sof_3_s = 'd0;
   reg     [  3:0]   phy_rst_cnt = 0;
   reg               phy_rst_reg = 0;
+  reg               rx_sysref_m1 = 'd0;
+  reg               rx_sysref_m2 = 'd0;
+  reg               rx_sysref_int = 'd0;
 
-  // internal clocks and resets
+  // internal signals
 
   wire              sys_125m_clk;
   wire              sys_25m_clk;
   wire              sys_2m5_clk;
+  wire              sys_pll_locked;
   wire              eth_tx_clk;
+  wire              eth_tx_mode_1g;
+  wire              eth_tx_mode_10m_100m_n;
   wire              rx_clk;
-  wire              adc_clk;
-
-  // internal signals
-
-  wire              sys_pll_locked_s;
-  wire              eth_tx_reset_s;
-  wire              eth_tx_mode_1g_s;
-  wire              eth_tx_mode_10m_100m_n_s;
-  wire    [  4:0]   spi_csn;
+  wire    [ 31:0]   rx_ch_wr;
+  wire    [511:0]   rx_ch_wdata;
+  wire              rx_ch_wovf;
+  wire              rx_ch_sync;
+  wire    [  3:0]   rx_ch_raddr;
+  wire    [  3:0]   rx_ip_sof;
+  wire    [255:0]   rx_ip_data;
+  wire    [  7:0]   spi_csn_s;
   wire              spi_clk;
   wire              spi_mosi;
   wire              spi_miso;
-  wire              rx_ref_clk;
-  wire              rx_sync;
-  wire    [127:0]   adc_data_0;
-  wire    [127:0]   adc_data_1;
-  wire    [127:0]   adc_data_2;
-  wire    [127:0]   adc_data_3;
-  wire              adc_valid;
-  wire    [  7:0]   adc_valid_0;
-  wire    [  7:0]   adc_valid_1;
-  wire    [  7:0]   adc_valid_2;
-  wire    [  7:0]   adc_valid_3;
-  wire    [  7:0]   adc_enable_0;
-  wire    [  7:0]   adc_enable_1;
-  wire    [  7:0]   adc_enable_2;
-  wire    [  7:0]   adc_enable_3;
-  wire              adc_dovf_0;
-  wire              adc_dovf_1;
-  wire              adc_dovf_2;
-  wire              adc_dovf_3;
-  wire    [  3:0]   rx_ip_sof_s;
-  wire    [255:0]   rx_ip_data_s;
-  wire    [255:0]   rx_data_s;
-  wire              rx_sw_rstn_s;
-  wire              rx_sysref_s;
-  wire              rx_err_s;
-  wire              rx_ready_s;
-  wire    [  3:0]   rx_rst_state_s;
-  wire              rx_lane_aligned_s;
-  wire    [  7:0]   rx_analog_reset_s;
-  wire    [  7:0]   rx_digital_reset_s;
-  wire    [  7:0]   rx_cdr_locked_s;
-  wire    [  7:0]   rx_cal_busy_s;
-  wire              rx_pll_locked_s;
-  wire    [ 22:0]   rx_xcvr_status_s;
-  wire    [  7:0]   rx_sof;
-  wire    [  3:0]   sync_raddr;
-  wire              sync_signal;
+  wire    [ 63:0]   gpio_i;
+  wire    [ 63:0]   gpio_o;
 
   // ethernet transmit clock
 
-  assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
-    (eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
+  assign eth_tx_clk = (eth_tx_mode_1g == 1'b1) ? sys_125m_clk :
+    (eth_tx_mode_10m_100m_n == 1'b0) ? sys_25m_clk : sys_2m5_clk;
 
   assign eth_phy_resetn = phy_rst_reg;
 
   always@ (posedge eth_mdc) begin
     phy_rst_cnt <= phy_rst_cnt + 4'd1;
     if (phy_rst_cnt == 4'h0) begin
-      phy_rst_reg <= sys_pll_locked_s;
+      phy_rst_reg <= sys_pll_locked;
     end
   end
 
+  // gpio
+
+  assign gpio_i[63:57] = gpio_o[63:57];
+  assign amp_disbn = gpio_o[56];
+
+  assign gpio_i[55:40] = gpio_o[55:40];
+  assign dac_sleep = gpio_o[54];
+  assign dac_data = gpio_o[53:40];
+
+  assign gpio_i[39:36] = gpio_o[39:36];
+  assign afe_stby = gpio_o[39];
+  assign afe_pdn = gpio_o[38];
+  assign afe_trig = gpio_o[37];
+  assign afe_rst = gpio_o[36];
+
+  assign gpio_i[35:35] = clk_status;
+  assign gpio_i[34:32] = gpio_o[34:32];
+  assign clk_sync = gpio_o[34];
+  assign clk_resetn = gpio_o[33];
+
+  // gpio (bd)
+
+  assign gpio_i[31:11] = gpio_o[31:11];
+  assign gpio_i[10: 0] = gpio_bd_i;
+
+  assign gpio_bd_o = gpio_o[26:11];
+
+  // sysref
+
+  assign rx_sysref = rx_sysref_int;
+
+  always @(posedge rx_clk) begin
+    rx_sysref_m1 <= gpio_o[32];
+    rx_sysref_m2 <= rx_sysref_m1;
+    rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
+  end
+
+  // spi (fanout buffers)
+
+  assign spi_fout_enb_clk     = 1'b0;
+  assign spi_fout_enb_mlo     = 1'b0;
+  assign spi_fout_enb_rst     = 1'b0;
+  assign spi_fout_enb_sync    = 1'b0;
+  assign spi_fout_enb_sysref  = 1'b0;
+  assign spi_fout_enb_trig    = 1'b0;
+  assign spi_fout_clk         = 1'b0;
+  assign spi_fout_sdio        = 1'b0;
+
+  // spi (adc)
+
+  assign prc_sck = 1'b0;
+  assign prc_cnv = 1'b0;
+
+  // spi (main)
+
+  assign spi_afe_csn = spi_csn_s[ 4: 1];
+  assign spi_clk_csn = spi_csn_s[ 0: 0];
+  assign spi_afe_clk = spi_clk;
+  assign spi_clk_clk = spi_clk;
+
+  // instantiations
+
+  usdrx1_spi i_spi (
+    .spi_afe_csn (spi_csn_s[4:1]),
+    .spi_clk_csn (spi_csn_s[0]),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_afe_sdio (spi_afe_sdio),
+    .spi_clk_sdio (spi_clk_sdio));
+
   altddio_out #(.width(1)) i_eth_tx_clk_out (
     .aset (1'b0),
     .sset (1'b0),
@@ -309,231 +249,126 @@ module system_top (
     .datain_h (1'b1),
     .datain_l (1'b0),
     .outclocken (1'b1),
-    .aclr (eth_tx_reset_s),
+    .aclr (~sys_pll_locked),
     .outclock (eth_tx_clk),
     .dataout (eth_tx_clk_out));
 
-  assign eth_tx_reset_s = ~sys_pll_locked_s;
-
-  always @(posedge adc_clk) begin
-    dma_sync <= 1'b1;
-    dma_wr <= (|adc_enable_0)| (| adc_enable_1) | (|adc_enable_2) | (|adc_enable_3);
-    dma_data <= {adc_data_3, adc_data_2, adc_data_1, adc_data_0};
-    adc_dovf <= adc_dovf_3 | adc_dovf_2 | adc_dovf_1 | adc_dovf_0;
-  end
-
-  always @(posedge rx_clk) begin
-    rx_sysref_m1 <= rx_sysref_s;
-    rx_sysref_m2 <= rx_sysref_m1;
-    rx_sysref_m3 <= rx_sysref_m2;
-    rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
-  end
-
-  sld_signaltap #(
-    .sld_advanced_trigger_entity ("basic,1,"),
-    .sld_data_bits (514),
-    .sld_data_bit_cntr_bits (8),
-    .sld_enable_advanced_trigger (0),
-    .sld_mem_address_bits (10),
-    .sld_node_crc_bits (32),
-    .sld_node_crc_hiword (10311),
-    .sld_node_crc_loword (14297),
-    .sld_node_info (1076736),
-    .sld_ram_block_type ("AUTO"),
-    .sld_sample_depth (1024),
-    .sld_storage_qualifier_gap_record (0),
-    .sld_storage_qualifier_mode ("OFF"),
-    .sld_trigger_bits (2),
-    .sld_trigger_in_enabled (0),
-    .sld_trigger_level (1),
-    .sld_trigger_level_pipeline (1))
-  i_signaltap (
-    .acq_clk (adc_clk),
-    .acq_data_in ({rx_sysref, rx_sync, dma_data}),
-    .acq_trigger_in ({rx_sysref, rx_sync}));
-
-  genvar n;
-  generate
-  for (n = 0; n < 8; n = n + 1) begin: g_align_1
-  ad_jesd_align i_jesd_align (
-    .rx_clk (rx_clk),
-    .rx_ip_sof (rx_ip_sof_s),
-    .rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
-    .rx_sof (rx_sof[n]),
-    .rx_data (rx_data_s[n*32+31:n*32]));
-  end
-  endgenerate
-
-  assign rx_xcvr_status_s[22:22] = rx_sync;
-  assign rx_xcvr_status_s[21:21] = rx_ready_s;
-  assign rx_xcvr_status_s[20:20] = rx_pll_locked_s;
-  assign rx_xcvr_status_s[19:16] = rx_rst_state_s;
-  assign rx_xcvr_status_s[15: 8] = rx_cdr_locked_s;
-  assign rx_xcvr_status_s[ 7: 0] = rx_cal_busy_s;
-
-  ad_xcvr_rx_rst #(.NUM_OF_LANES (8)) i_xcvr_rx_rst (
-    .rx_clk (rx_clk),
-    .rx_rstn (sys_resetn),
-    .rx_sw_rstn (rx_sw_rstn_s),
-    .rx_pll_locked (rx_pll_locked_s),
-    .rx_cal_busy (rx_cal_busy_s),
-    .rx_cdr_locked (rx_cdr_locked_s),
-    .rx_analog_reset (rx_analog_reset_s),
-    .rx_digital_reset (rx_digital_reset_s),
-    .rx_ready (rx_ready_s),
-    .rx_rst_state (rx_rst_state_s));
-
-  assign spi_fout_enb_clk     = 1'b0;
-  assign spi_fout_enb_mlo     = 1'b0;
-  assign spi_fout_enb_rst     = 1'b0;
-  assign spi_fout_enb_sync    = 1'b0;
-  assign spi_fout_enb_sysref  = 1'b0;
-  assign spi_fout_enb_trig    = 1'b0;
-  assign spi_fout_clk         = 1'b0;
-  assign spi_fout_sdio        = 1'b0;
-  assign spi_afe_csn          = spi_csn[ 4: 1];
-  assign spi_clk_csn          = spi_csn[ 0: 0];
-  assign spi_afe_clk          = spi_clk;
-  assign spi_clk_clk          = spi_clk;
-
-  always @(posedge rx_clk)
-  begin
-    rx_sof_0_s <= rx_sof[0] | rx_sof[1];
-    rx_sof_1_s <= rx_sof[2] | rx_sof[3];
-    rx_sof_2_s <= rx_sof[4] | rx_sof[5];
-    rx_sof_3_s <= rx_sof[6] | rx_sof[7];
-  end
-
-  usdrx1_spi i_spi (
-    .spi_afe_csn (spi_csn[4:1]),
-    .spi_clk_csn (spi_csn[0]),
-    .spi_clk (spi_clk),
-    .spi_mosi (spi_mosi),
-    .spi_miso (spi_miso),
-    .spi_afe_sdio (spi_afe_sdio),
-    .spi_clk_sdio (spi_clk_sdio));
-
   system_bd i_system_bd (
-    .sys_clk_clk (sys_clk),
-    .sys_reset_reset_n (sys_resetn),
+    .rx_ch_wdata_data (rx_ch_wdata),
+    .rx_ch_wovf_ovf (rx_ch_wovf),
+    .rx_ch_wr_valid (&rx_ch_wr),
+    .rx_core_ch_0_enable (),
+    .rx_core_ch_0_valid (rx_ch_wr[7:0]),
+    .rx_core_ch_0_data (rx_ch_wdata[127:0]),
+    .rx_core_ch_1_enable (),
+    .rx_core_ch_1_valid (rx_ch_wr[15:8]),
+    .rx_core_ch_1_data (rx_ch_wdata[255:128]),
+    .rx_core_ch_2_enable (),
+    .rx_core_ch_2_valid (rx_ch_wr[23:16]),
+    .rx_core_ch_2_data (rx_ch_wdata[383:256]),
+    .rx_core_ch_3_enable (),
+    .rx_core_ch_3_valid (rx_ch_wr[31:24]),
+    .rx_core_ch_3_data (rx_ch_wdata[511:384]),
+    .rx_core_clk_clk (rx_clk),
+    .rx_core_ovf_0_ovf (rx_ch_wovf),
+    .rx_core_ovf_1_ovf (rx_ch_wovf),
+    .rx_core_ovf_2_ovf (rx_ch_wovf),
+    .rx_core_ovf_3_ovf (rx_ch_wovf),
+    .rx_core_sync_0_sync_in (1'b0),
+    .rx_core_sync_0_sync_out (rx_ch_sync),
+    .rx_core_sync_0_raddr_in (4'd0),
+    .rx_core_sync_0_raddr_out (rx_ch_raddr),
+    .rx_core_sync_1_sync_in (rx_ch_sync),
+    .rx_core_sync_1_sync_out (),
+    .rx_core_sync_1_raddr_in (rx_ch_raddr),
+    .rx_core_sync_1_raddr_out (),
+    .rx_core_sync_2_sync_in (rx_ch_sync),
+    .rx_core_sync_2_sync_out (),
+    .rx_core_sync_2_raddr_in (rx_ch_raddr),
+    .rx_core_sync_2_raddr_out (),
+    .rx_core_sync_3_sync_in (rx_ch_sync),
+    .rx_core_sync_3_sync_out (),
+    .rx_core_sync_3_raddr_in (rx_ch_raddr),
+    .rx_core_sync_3_raddr_out (),
+    .rx_core_unf_0_unf (1'd0),
+    .rx_core_unf_1_unf (1'd0),
+    .rx_core_unf_2_unf (1'd0),
+    .rx_core_unf_3_unf (1'd0),
+    .rx_data_0_rx_serial_data (rx_data[0]),
+    .rx_data_1_rx_serial_data (rx_data[1]),
+    .rx_data_2_rx_serial_data (rx_data[2]),
+    .rx_data_3_rx_serial_data (rx_data[3]),
+    .rx_data_4_rx_serial_data (rx_data[4]),
+    .rx_data_5_rx_serial_data (rx_data[5]),
+    .rx_data_6_rx_serial_data (rx_data[6]),
+    .rx_data_7_rx_serial_data (rx_data[7]),
+    .rx_ip_data_data (rx_ip_data),
+    .rx_ip_data_valid (),
+    .rx_ip_data_ready (1'b1),
+    .rx_ip_data_0_data (rx_ip_data[63:0]),
+    .rx_ip_data_0_valid (1'b1),
+    .rx_ip_data_0_ready (),
+    .rx_ip_data_1_data (rx_ip_data[127:64]),
+    .rx_ip_data_1_valid (1'b1),
+    .rx_ip_data_1_ready (),
+    .rx_ip_data_2_data (rx_ip_data[191:128]),
+    .rx_ip_data_2_valid (1'b1),
+    .rx_ip_data_2_ready (),
+    .rx_ip_data_3_data (rx_ip_data[255:192]),
+    .rx_ip_data_3_valid (1'b1),
+    .rx_ip_data_3_ready (),
+    .rx_ip_sof_export (rx_ip_sof),
+    .rx_ip_sof_0_export (rx_ip_sof),
+    .rx_ip_sof_1_export (rx_ip_sof),
+    .rx_ip_sof_2_export (rx_ip_sof),
+    .rx_ip_sof_3_export (rx_ip_sof),
+    .rx_ref_clk_clk (ref_clk),
+    .rx_sync_export (rx_sync),
+    .rx_sysref_export (rx_sysref_int),
     .sys_125m_clk_clk (sys_125m_clk),
     .sys_25m_clk_clk (sys_25m_clk),
     .sys_2m5_clk_clk (sys_2m5_clk),
-    .sys_pll_locked_export (sys_pll_locked_s),
-    .sys_ddr3_phy_mem_a (ddr3_a),
-    .sys_ddr3_phy_mem_ba (ddr3_ba),
-    .sys_ddr3_phy_mem_ck (ddr3_clk_p),
-    .sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
-    .sys_ddr3_phy_mem_cke (ddr3_cke),
-    .sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
-    .sys_ddr3_phy_mem_dm (ddr3_dm),
-    .sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
-    .sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
-    .sys_ddr3_phy_mem_we_n (ddr3_we_n),
-    .sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
-    .sys_ddr3_phy_mem_dq (ddr3_dq),
-    .sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
-    .sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
-    .sys_ddr3_phy_mem_odt (ddr3_odt),
-    .sys_ddr3_oct_rzqin (ddr3_rzq),
-    .sys_ethernet_tx_clk_clk (eth_tx_clk),
-    .sys_ethernet_rx_clk_clk (eth_rx_clk),
-    .sys_ethernet_status_set_10 (),
-    .sys_ethernet_status_set_1000 (),
-    .sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
-    .sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
-    .sys_ethernet_rgmii_rgmii_in (eth_rx_data),
-    .sys_ethernet_rgmii_rgmii_out (eth_tx_data),
-    .sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
-    .sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
+    .sys_clk_clk (sys_clk),
+    .sys_ddr3_cntrl_mem_mem_a (ddr3_a),
+    .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm),
+    .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq),
+    .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p),
+    .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n),
+    .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .sys_ddr3_cntrl_oct_rzqin (ddr3_rzq),
     .sys_ethernet_mdio_mdc (eth_mdc),
     .sys_ethernet_mdio_mdio_in (eth_mdio_i),
     .sys_ethernet_mdio_mdio_out (eth_mdio_o),
     .sys_ethernet_mdio_mdio_oen (eth_mdio_t),
-    .sys_gpio_in_port ({25'h0, clk_status, 6'h0 }),
-    .sys_gpio_out_port ({3'h0, rx_sysref_s,
-      rx_sw_rstn_s, dac_data, dac_sleep,
-      1'b0, 1'b0, 1'b0, 1'b0,
-      amp_disbn, 1'b0, clk_syncn, clk_resetn,
-      afe_stby, afe_pdn, afe_trig, afe_rst}),
+    .sys_ethernet_rgmii_rgmii_in (eth_rx_data),
+    .sys_ethernet_rgmii_rgmii_out (eth_tx_data),
+    .sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
+    .sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
+    .sys_ethernet_rx_clk_clk (eth_rx_clk),
+    .sys_ethernet_status_set_10 (),
+    .sys_ethernet_status_set_1000 (),
+    .sys_ethernet_status_eth_mode (eth_tx_mode_1g),
+    .sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
+    .sys_ethernet_tx_clk_clk (eth_tx_clk),
+    .sys_gpio_bd_in_port (gpio_i[31:0]),
+    .sys_gpio_bd_out_port (gpio_o[31:0]),
+    .sys_gpio_in_export (gpio_i[63:32]),
+    .sys_gpio_out_export (gpio_o[63:32]),
+    .sys_pll_locked_export (sys_pll_locked),
+    .sys_rst_reset_n (sys_resetn),
     .sys_spi_MISO (spi_miso),
     .sys_spi_MOSI (spi_mosi),
     .sys_spi_SCLK (spi_clk),
-    .sys_spi_SS_n (spi_csn),
-    .axi_dmac_if_fifo_wr_clk_clk (adc_clk),
-    .axi_dmac_if_fifo_wr_overflow_adc_dovf (adc_dovf),
-    .axi_dmac_if_fifo_wr_en_adc_valid (dma_wr),
-    .axi_dmac_if_fifo_wr_din_adc_data (dma_data),
-    .axi_dmac_if_fifo_wr_sync_adc_sync (dma_sync),
-    .sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
-    .sys_jesd204b_s1_rx_link_valid (),
-    .sys_jesd204b_s1_rx_link_ready (1'b1),
-    .sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
-    .sys_jesd204b_s1_sysref_export (rx_sysref),
-    .sys_jesd204b_s1_rx_ferr_export (rx_err_s),
-    .sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
-    .sys_jesd204b_s1_sync_n_export (rx_sync),
-    .sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
-    .sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
-    .sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
-    .sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
-    .sys_jesd204b_s1_locked_rx_is_lockedtodata (rx_cdr_locked_s),
-    .sys_jesd204b_s1_rx_cal_busy_rx_cal_busy (rx_cal_busy_s),
-    .sys_jesd204b_s1_ref_clk_clk (ref_clk),
-    .sys_jesd204b_s1_rx_clk_clk (rx_clk),
-    .sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
-    .axi_ad9671_0_xcvr_clk_clk (rx_clk),
-    .axi_ad9671_0_xcvr_data_data (rx_data_s[63:0]),
-    .axi_ad9671_0_xcvr_data_data_sof(rx_sof_0_s),
-    .axi_ad9671_0_adc_clock_clk (adc_clk),
-    .axi_ad9671_0_adc_dma_if_valid (adc_valid_0),
-    .axi_ad9671_0_adc_dma_if_enable (adc_enable_0),
-    .axi_ad9671_0_adc_dma_if_data (adc_data_0),
-    .axi_ad9671_0_adc_dma_if_dovf (adc_dovf_0),
-    .axi_ad9671_0_adc_dma_if_dunf (1'b0),
-    .axi_ad9671_1_xcvr_clk_clk (rx_clk),
-    .axi_ad9671_1_xcvr_data_data (rx_data_s[127:64]),
-    .axi_ad9671_1_xcvr_data_data_sof(rx_sof_1_s),
-    .axi_ad9671_1_adc_clock_clk (),
-    .axi_ad9671_1_adc_dma_if_valid (adc_valid_1),
-    .axi_ad9671_1_adc_dma_if_enable (adc_enable_1),
-    .axi_ad9671_1_adc_dma_if_data (adc_data_1),
-    .axi_ad9671_1_adc_dma_if_dovf (adc_dovf_1),
-    .axi_ad9671_1_adc_dma_if_dunf (1'b0),
-    .axi_ad9671_2_xcvr_clk_clk (rx_clk),
-    .axi_ad9671_2_xcvr_data_data (rx_data_s[191:128]),
-    .axi_ad9671_2_xcvr_data_data_sof(rx_sof_2_s),
-    .axi_ad9671_2_adc_clock_clk (),
-    .axi_ad9671_2_adc_dma_if_valid (adc_valid_2),
-    .axi_ad9671_2_adc_dma_if_enable (adc_enable_2),
-    .axi_ad9671_2_adc_dma_if_data (adc_data_2),
-    .axi_ad9671_2_adc_dma_if_dovf (adc_dovf_2),
-    .axi_ad9671_2_adc_dma_if_dunf (1'b0),
-    .axi_ad9671_3_xcvr_clk_clk (rx_clk),
-    .axi_ad9671_3_xcvr_data_data (rx_data_s[255:192]),
-    .axi_ad9671_3_xcvr_data_data_sof(rx_sof_3_s),
-    .axi_ad9671_3_adc_clock_clk (),
-    .axi_ad9671_3_adc_dma_if_valid (adc_valid_3),
-    .axi_ad9671_3_adc_dma_if_enable (adc_enable_3),
-    .axi_ad9671_3_adc_dma_if_data (adc_data_3),
-    .axi_ad9671_3_adc_dma_if_dovf (adc_dovf_3),
-    .axi_ad9671_3_adc_dma_if_dunf (1'b0),
-    .axi_ad9671_0_xcvr_sync_sync_in (),
-    .axi_ad9671_0_xcvr_sync_sync_out (sync_signal),
-    .axi_ad9671_0_xcvr_sync_raddr_in (),
-    .axi_ad9671_0_xcvr_sync_raddr_out (sync_raddr),
-    .axi_ad9671_1_xcvr_sync_sync_in (sync_signal),
-    .axi_ad9671_1_xcvr_sync_sync_out (),
-    .axi_ad9671_1_xcvr_sync_raddr_in (sync_raddr),
-    .axi_ad9671_1_xcvr_sync_raddr_out(),
-    .axi_ad9671_2_xcvr_sync_sync_in (sync_signal),
-    .axi_ad9671_2_xcvr_sync_sync_out (),
-    .axi_ad9671_2_xcvr_sync_raddr_in (sync_raddr),
-    .axi_ad9671_2_xcvr_sync_raddr_out (),
-    .axi_ad9671_3_xcvr_sync_sync_in (sync_signal),
-    .axi_ad9671_3_xcvr_sync_sync_out (),
-    .axi_ad9671_3_xcvr_sync_raddr_in (sync_raddr),
-    .axi_ad9671_3_xcvr_sync_raddr_out ());
+    .sys_spi_SS_n (spi_csn_s));
 
 endmodule
 
diff --git a/projects/usdrx1/common/usdrx1_qsys.tcl b/projects/usdrx1/common/usdrx1_qsys.tcl
index a8221c713..dd10d8195 100644
--- a/projects/usdrx1/common/usdrx1_qsys.tcl
+++ b/projects/usdrx1/common/usdrx1_qsys.tcl
@@ -29,13 +29,13 @@ set_interface_property rx_data_2 EXPORT_OF avl_usdrx1_xcvr.rx_data_2
 add_interface rx_data_3 conduit end
 set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_3
 add_interface rx_data_4 conduit end
-set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_4
+set_interface_property rx_data_4 EXPORT_OF avl_usdrx1_xcvr.rx_data_4
 add_interface rx_data_5 conduit end
-set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_5
+set_interface_property rx_data_5 EXPORT_OF avl_usdrx1_xcvr.rx_data_5
 add_interface rx_data_6 conduit end
-set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_6
+set_interface_property rx_data_6 EXPORT_OF avl_usdrx1_xcvr.rx_data_6
 add_interface rx_data_7 conduit end
-set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_7
+set_interface_property rx_data_7 EXPORT_OF avl_usdrx1_xcvr.rx_data_7
 add_interface rx_sysref conduit end
 set_interface_property rx_sysref EXPORT_OF avl_usdrx1_xcvr.sysref
 add_interface rx_sync conduit end
@@ -61,7 +61,8 @@ add_connection axi_usdrx1_xcvr.core_pll_locked avl_usdrx1_xcvr.core_pll_locked
 # ad9671
 
 add_instance axi_ad9671_core_0 axi_ad9671 1.0
-
+set_instance_parameter_value axi_ad9671_core_0 {ID} {0}
+set_instance_parameter_value axi_ad9671_core_0 {QUAD_OR_DUAL_N} {0}
 add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_0.if_rx_clk
 add_interface rx_ip_sof_0 conduit end
 set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9671_core_0.if_rx_sof
@@ -69,9 +70,18 @@ add_interface rx_ip_data_0 avalon_streaming sink
 set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9671_core_0.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9671_core_0.s_axi_reset
 add_connection sys_clk.clk axi_ad9671_core_0.s_axi_clock
+add_interface rx_core_ch_0 conduit end
+set_interface_property rx_core_ch_0 EXPORT_OF axi_ad9671_core_0.adc_ch
+add_interface rx_core_sync_0 conduit end
+set_interface_property rx_core_sync_0 EXPORT_OF axi_ad9671_core_0.if_sync
+add_interface rx_core_ovf_0 conduit end
+set_interface_property rx_core_ovf_0 EXPORT_OF axi_ad9671_core_0.if_adc_dovf
+add_interface rx_core_unf_0 conduit end
+set_interface_property rx_core_unf_0 EXPORT_OF axi_ad9671_core_0.if_adc_dunf
 
 add_instance axi_ad9671_core_1 axi_ad9671 1.0
-
+set_instance_parameter_value axi_ad9671_core_1 {ID} {1}
+set_instance_parameter_value axi_ad9671_core_1 {QUAD_OR_DUAL_N} {0}
 add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_1.if_rx_clk
 add_interface rx_ip_sof_1 conduit end
 set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9671_core_1.if_rx_sof
@@ -79,9 +89,18 @@ add_interface rx_ip_data_1 avalon_streaming sink
 set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9671_core_1.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9671_core_1.s_axi_reset
 add_connection sys_clk.clk axi_ad9671_core_1.s_axi_clock
+add_interface rx_core_ch_1 conduit end
+set_interface_property rx_core_ch_1 EXPORT_OF axi_ad9671_core_1.adc_ch
+add_interface rx_core_sync_1 conduit end
+set_interface_property rx_core_sync_1 EXPORT_OF axi_ad9671_core_1.if_sync
+add_interface rx_core_ovf_1 conduit end
+set_interface_property rx_core_ovf_1 EXPORT_OF axi_ad9671_core_1.if_adc_dovf
+add_interface rx_core_unf_1 conduit end
+set_interface_property rx_core_unf_1 EXPORT_OF axi_ad9671_core_1.if_adc_dunf
 
 add_instance axi_ad9671_core_2 axi_ad9671 1.0
-
+set_instance_parameter_value axi_ad9671_core_2 {ID} {2}
+set_instance_parameter_value axi_ad9671_core_2 {QUAD_OR_DUAL_N} {0}
 add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_2.if_rx_clk
 add_interface rx_ip_sof_2 conduit end
 set_interface_property rx_ip_sof_2 EXPORT_OF axi_ad9671_core_2.if_rx_sof
@@ -89,9 +108,18 @@ add_interface rx_ip_data_2 avalon_streaming sink
 set_interface_property rx_ip_data_2 EXPORT_OF axi_ad9671_core_2.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9671_core_2.s_axi_reset
 add_connection sys_clk.clk axi_ad9671_core_2.s_axi_clock
+add_interface rx_core_ch_2 conduit end
+set_interface_property rx_core_ch_2 EXPORT_OF axi_ad9671_core_2.adc_ch
+add_interface rx_core_sync_2 conduit end
+set_interface_property rx_core_sync_2 EXPORT_OF axi_ad9671_core_2.if_sync
+add_interface rx_core_ovf_2 conduit end
+set_interface_property rx_core_ovf_2 EXPORT_OF axi_ad9671_core_2.if_adc_dovf
+add_interface rx_core_unf_2 conduit end
+set_interface_property rx_core_unf_2 EXPORT_OF axi_ad9671_core_2.if_adc_dunf
 
 add_instance axi_ad9671_core_3 axi_ad9671 1.0
-
+set_instance_parameter_value axi_ad9671_core_3 {ID} {3}
+set_instance_parameter_value axi_ad9671_core_3 {QUAD_OR_DUAL_N} {0}
 add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_3.if_rx_clk
 add_interface rx_ip_sof_3 conduit end
 set_interface_property rx_ip_sof_3 EXPORT_OF axi_ad9671_core_3.if_rx_sof
@@ -99,33 +127,31 @@ add_interface rx_ip_data_3 avalon_streaming sink
 set_interface_property rx_ip_data_3 EXPORT_OF axi_ad9671_core_3.if_rx_data
 add_connection sys_clk.clk_reset axi_ad9671_core_3.s_axi_reset
 add_connection sys_clk.clk axi_ad9671_core_3.s_axi_clock
-
-# usdrx1-pack
-
-add_instance util_usdrx1_cpack util_cpack 1.0
-set_instance_parameter_value util_usdrx1_cpack {CHANNEL_DATA_WIDTH} {128}
-set_instance_parameter_value util_usdrx1_cpack {NUM_OF_CHANNELS} {4}
-
-add_connection sys_clk.clk_reset util_usdrx1_cpack.if_adc_rst
-add_connection sys_dma_clk.clk_reset util_usdrx1_cpack.if_adc_rst
-add_connection avl_usdrx1_xcvr.core_clk util_usdrx1_cpack.if_adc_clk
-add_connection axi_ad9671_core_0.adc_ch util_usdrx1_cpack.adc_ch_0
-add_connection axi_ad9671_core_1.adc_ch util_usdrx1_cpack.adc_ch_1
-add_connection axi_ad9671_core_2.adc_ch util_usdrx1_cpack.adc_ch_2
-add_connection axi_ad9671_core_3.adc_ch util_usdrx1_cpack.adc_ch_3
+add_interface rx_core_ch_3 conduit end
+set_interface_property rx_core_ch_3 EXPORT_OF axi_ad9671_core_3.adc_ch
+add_interface rx_core_sync_3 conduit end
+set_interface_property rx_core_sync_3 EXPORT_OF axi_ad9671_core_3.if_sync
+add_interface rx_core_ovf_3 conduit end
+set_interface_property rx_core_ovf_3 EXPORT_OF axi_ad9671_core_3.if_adc_dovf
+add_interface rx_core_unf_3 conduit end
+set_interface_property rx_core_unf_3 EXPORT_OF axi_ad9671_core_3.if_adc_dunf
 
 # usdrx1-fifo
 
 add_instance usdrx1_adcfifo util_adcfifo 1.0
 set_instance_parameter_value usdrx1_adcfifo {ADC_DATA_WIDTH} {512}
 set_instance_parameter_value usdrx1_adcfifo {DMA_DATA_WIDTH} {512}
-set_instance_parameter_value usdrx1_adcfifo {DMA_ADDRESS_WIDTH} {16}
+set_instance_parameter_value usdrx1_adcfifo {DMA_ADDRESS_WIDTH} {10}
 
 add_connection sys_clk.clk_reset usdrx1_adcfifo.if_adc_rst
 add_connection sys_dma_clk.clk_reset usdrx1_adcfifo.if_adc_rst
 add_connection avl_usdrx1_xcvr.core_clk usdrx1_adcfifo.if_adc_clk
-add_connection util_usdrx1_cpack.if_adc_valid usdrx1_adcfifo.if_adc_wr
-add_connection util_usdrx1_cpack.if_adc_data usdrx1_adcfifo.if_adc_wdata
+add_interface rx_ch_wr conduit end
+set_interface_property rx_ch_wr EXPORT_OF usdrx1_adcfifo.if_adc_wr
+add_interface rx_ch_wdata conduit end
+set_interface_property rx_ch_wdata EXPORT_OF usdrx1_adcfifo.if_adc_wdata
+add_interface rx_ch_wovf conduit end
+set_interface_property rx_ch_wovf EXPORT_OF usdrx1_adcfifo.if_adc_wovf
 add_connection sys_dma_clk.clk usdrx1_adcfifo.if_dma_clk
 
 # usdrx1-dma
@@ -145,7 +171,6 @@ add_connection usdrx1_adcfifo.if_dma_wr axi_usdrx1_dma.if_s_axis_valid
 add_connection usdrx1_adcfifo.if_dma_wdata axi_usdrx1_dma.if_s_axis_data
 add_connection usdrx1_adcfifo.if_dma_wready axi_usdrx1_dma.if_s_axis_ready
 add_connection usdrx1_adcfifo.if_dma_xfer_req axi_usdrx1_dma.if_s_axis_xfer_req
-add_connection usdrx1_adcfifo.if_adc_wovf axi_ad9671_core_0.if_adc_dovf
 add_connection sys_clk.clk_reset axi_usdrx1_dma.s_axi_reset
 add_connection sys_clk.clk axi_usdrx1_dma.s_axi_clock
 add_connection sys_dma_clk.clk_reset axi_usdrx1_dma.m_dest_axi_reset
@@ -171,14 +196,14 @@ add_connection avl_phy_reconfig.ch2_2_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xc
 add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_2 avl_phy_reconfig.ch2_2_from_xcvr 
 add_connection avl_phy_reconfig.ch3_3_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_3 
 add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_3 avl_phy_reconfig.ch3_3_from_xcvr 
-add_connection avl_phy_reconfig.ch0_4_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_4 
-add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_4 avl_phy_reconfig.ch0_4_from_xcvr 
-add_connection avl_phy_reconfig.ch1_5_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_5 
-add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_5 avl_phy_reconfig.ch1_5_from_xcvr 
-add_connection avl_phy_reconfig.ch2_6_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_6 
-add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_6 avl_phy_reconfig.ch2_6_from_xcvr 
-add_connection avl_phy_reconfig.ch3_7_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_7 
-add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_7 avl_phy_reconfig.ch3_7_from_xcvr 
+add_connection avl_phy_reconfig.ch4_4_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_4 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_4 avl_phy_reconfig.ch4_4_from_xcvr 
+add_connection avl_phy_reconfig.ch5_5_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_5 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_5 avl_phy_reconfig.ch5_5_from_xcvr 
+add_connection avl_phy_reconfig.ch6_6_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_6 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_6 avl_phy_reconfig.ch6_6_from_xcvr 
+add_connection avl_phy_reconfig.ch7_7_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_7 
+add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_7 avl_phy_reconfig.ch7_7_from_xcvr 
 add_connection sys_clk.clk_reset avl_phy_reconfig.mgmt_rst_reset
 add_connection sys_clk.clk avl_phy_reconfig.mgmt_clk_clk
 

From 23c91ca48a849e5b87e07c1591959840470f01d4 Mon Sep 17 00:00:00 2001
From: Istvan <istvan.csomortani@analog.com>
Date: Fri, 9 Dec 2016 11:45:11 +0200
Subject: [PATCH 798/972] pzsdr1/lvds: The interface runs at max 122.88 MHz

---
 projects/pzsdr1/common/pzsdr1_constr_lvds.xdc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc b/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc
index c5e8e10c4..da996fea6 100644
--- a/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc
+++ b/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc
@@ -37,6 +37,6 @@ set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVDS_25}  [get_ports tx_data_o
 
 # clocks
 
-create_clock -name rx_clk       -period  4 [get_ports rx_clk_in_p]
-create_clock -name ad9361_clk   -period  4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
+create_clock -name rx_clk       -period  8 [get_ports rx_clk_in_p]
+create_clock -name ad9361_clk   -period  8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
 

From 8e69c838e12e681bee2f56d6b3904232a8fbdeb9 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri, 9 Dec 2016 13:54:39 +0200
Subject: [PATCH 799/972] common/ac701: Connect axi_ddr_cntrl/device_temp_i to
 GND

---
 projects/common/ac701/ac701_system_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl
index b35bdcdbd..57afc4be2 100644
--- a/projects/common/ac701/ac701_system_bd.tcl
+++ b/projects/common/ac701/ac701_system_bd.tcl
@@ -152,6 +152,7 @@ ad_connect sys_concat_intc/dout   axi_intc/intr
 # defaults (peripherals)
 
 ad_connect axi_ddr_cntrl/mmcm_locked   sys_rstgen/dcm_locked
+ad_connect axi_ddr_cntrl/device_temp_i GND
 
 ad_connect sys_cpu_clk axi_ddr_cntrl/ui_clk
 ad_connect sys_200m_clk axi_ddr_cntrl/ui_addn_clk_0

From 06aab8ebbd750725fe1db9c8289782c91fcd1637 Mon Sep 17 00:00:00 2001
From: Istvan <istvan.csomortani@analog.com>
Date: Fri, 9 Dec 2016 16:35:46 +0200
Subject: [PATCH 800/972] pzsdr1: Set the device core to 1R1T mode

---
 projects/pzsdr1/common/pzsdr1_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/pzsdr1/common/pzsdr1_bd.tcl b/projects/pzsdr1/common/pzsdr1_bd.tcl
index 4ab1d3de8..000c24bb4 100644
--- a/projects/pzsdr1/common/pzsdr1_bd.tcl
+++ b/projects/pzsdr1/common/pzsdr1_bd.tcl
@@ -334,7 +334,7 @@ ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
 ## 2R2T supports 1R1T as a run time option.
 ## 1R1T allows core to run at a lower rate (1/2 of 2R2T)
 
-set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361] 
+set_property CONFIG.MODE_1R1T 1 [get_bd_cells axi_ad9361]
 
 ## interface type - CMOS (1) or LVDS (0) (default is LVDS)
 ## CMOS allows core to run at a lower rate (1/2 of LVDS)

From 8ebc8fe4e2172d5c7a17d0e2aea1dee20f7e4760 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 9 Dec 2016 23:06:41 +0200
Subject: [PATCH 801/972] updated makefiles

---
 library/axi_ad6676/Makefile                   | 26 ++++----
 library/axi_ad7616/Makefile                   | 21 +++---
 library/axi_ad9122/Makefile                   | 30 ++++-----
 library/axi_ad9144/Makefile                   | 20 +++---
 library/axi_ad9152/Makefile                   | 20 +++---
 library/axi_ad9162/Makefile                   | 20 +++---
 library/axi_ad9234/Makefile                   | 20 +++---
 library/axi_ad9250/Makefile                   | 28 ++++----
 library/axi_ad9265/Makefile                   | 30 ++++-----
 library/axi_ad9361/Makefile                   | 64 +++++++++----------
 library/axi_ad9371/Makefile                   | 40 ++++++------
 library/axi_ad9434/Makefile                   | 34 +++++-----
 library/axi_ad9467/Makefile                   | 30 ++++-----
 library/axi_ad9625/Makefile                   | 26 ++++----
 library/axi_ad9643/Makefile                   | 34 +++++-----
 library/axi_ad9652/Makefile                   | 34 +++++-----
 library/axi_ad9671/Makefile                   | 29 +++++----
 library/axi_ad9680/Makefile                   | 24 +++----
 library/axi_ad9684/Makefile                   | 32 +++++-----
 library/axi_ad9739a/Makefile                  | 28 ++++----
 library/axi_clkgen/Makefile                   | 10 +--
 library/axi_dmac/Makefile                     | 36 ++++++-----
 library/axi_generic_adc/Makefile              | 12 ++--
 library/axi_gpreg/Makefile                    | 12 ++--
 library/axi_hdmi_rx/Makefile                  | 20 +++---
 library/axi_hdmi_tx/Makefile                  | 26 ++++----
 library/axi_i2s_adi/Makefile                  | 23 ++++---
 library/axi_intr_monitor/Makefile             |  4 +-
 library/axi_mc_controller/Makefile            | 23 ++++---
 library/axi_mc_current_monitor/Makefile       | 16 ++---
 library/axi_mc_speed/Makefile                 | 20 +++---
 library/axi_spdif_rx/Makefile                 | 16 ++---
 library/axi_spdif_tx/Makefile                 | 12 ++--
 library/axi_usb_fx3/Makefile                  |  6 +-
 library/cn0363/cn0363_dma_sequencer/Makefile  |  5 +-
 .../cn0363/cn0363_phase_data_sync/Makefile    |  2 +-
 library/cordic_demod/Makefile                 |  2 +-
 library/spi_engine/axi_spi_engine/Makefile    | 16 +++--
 .../spi_engine/spi_engine_execution/Makefile  |  7 +-
 .../spi_engine_interconnect/Makefile          |  5 +-
 .../spi_engine/spi_engine_offload/Makefile    |  9 ++-
 library/util_adcfifo/Makefile                 |  6 +-
 library/util_axis_fifo/Makefile               |  6 +-
 library/util_axis_resize/Makefile             |  2 +-
 library/util_bsplit/Makefile                  |  2 +-
 library/util_ccat/Makefile                    |  2 +-
 library/util_clkdiv/Makefile                  |  2 +-
 library/util_cpack/Makefile                   |  6 +-
 library/util_dacfifo/Makefile                 |  4 +-
 library/util_fir_dec/Makefile                 |  2 +-
 library/util_fir_int/Makefile                 |  2 +-
 library/util_gmii_to_rgmii/Makefile           |  4 +-
 library/util_gtlb/Makefile                    | 11 ++--
 library/util_i2c_mixer/Makefile               |  2 +-
 library/util_jesd_gt/Makefile                 |  7 +-
 library/util_mfifo/Makefile                   |  5 +-
 library/util_pmod_adc/Makefile                |  2 +-
 library/util_pmod_fmeter/Makefile             |  8 +--
 library/util_rfifo/Makefile                   |  5 +-
 library/util_sigma_delta_spi/Makefile         |  5 +-
 library/util_tdd_sync/Makefile                |  5 +-
 library/util_upack/Makefile                   |  6 +-
 library/util_wfifo/Makefile                   |  5 +-
 library/xilinx/axi_adcfifo/Makefile           | 16 ++---
 library/xilinx/axi_adxcvr/Makefile            | 13 ++--
 library/xilinx/axi_dacfifo/Makefile           | 10 +--
 library/xilinx/axi_xcvrlb/Makefile            | 12 ++--
 library/xilinx/util_adxcvr/Makefile           | 13 ++--
 projects/ad7616_sdz/zc706/Makefile            |  2 -
 projects/ad7616_sdz/zed/Makefile              |  2 -
 projects/adrv9371x/a10gx/Makefile             |  7 ++
 projects/adrv9371x/a10soc/Makefile            |  7 ++
 projects/arradio/c5soc/Makefile               | 44 -------------
 projects/common/a5gte/Makefile                |  1 -
 projects/daq1/a10gx/Makefile                  | 15 +++--
 projects/daq2/a10gx/Makefile                  |  7 ++
 projects/daq3/a10gx/Makefile                  |  7 ++
 projects/fmcadc2/zc706/Makefile               |  1 +
 projects/fmcjesdadc1/a5gt/Makefile            |  7 ++
 projects/fmcjesdadc1/a5soc/Makefile           |  7 ++
 projects/fmcomms2/a10gx/Makefile              | 41 ++++++++++++
 projects/fmcomms2/zc706pr/Makefile            | 16 +++++
 projects/usb_fx3/zc706/Makefile               |  3 +
 projects/usdrx1/a5gt/Makefile                 | 63 ++++++++++++++++++
 84 files changed, 715 insertions(+), 550 deletions(-)

diff --git a/library/axi_ad6676/Makefile b/library/axi_ad6676/Makefile
index 7e7660720..596eed550 100644
--- a/library/axi_ad6676/Makefile
+++ b/library/axi_ad6676/Makefile
@@ -5,24 +5,24 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad6676_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/ad_xcvr_rx_if.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad6676_pnmon.v
-M_DEPS += axi_ad6676_channel.v
-M_DEPS += axi_ad6676_if.v
-M_DEPS += axi_ad6676_constr.xdc
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_ad6676.v
+M_DEPS += axi_ad6676_channel.v
+M_DEPS += axi_ad6676_constr.xdc
+M_DEPS += axi_ad6676_if.v
+M_DEPS += axi_ad6676_ip.tcl
+M_DEPS += axi_ad6676_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile
index 4c1cd4690..5189f10d2 100644
--- a/library/axi_ad7616/Makefile
+++ b/library/axi_ad7616/Makefile
@@ -5,19 +5,20 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad7616_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_edge_detect.v
 M_DEPS += ../common/up_axi.v
-M_DEPS += axi_ad7616_control.v
-M_DEPS += axi_ad7616_pif.v
-M_DEPS += axi_ad7616_maxis2wrfifo.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_ad7616.v
-M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
+M_DEPS += axi_ad7616_control.v
+M_DEPS += axi_ad7616_ip.tcl
+M_DEPS += axi_ad7616_maxis2wrfifo.v
+M_DEPS += axi_ad7616_pif.v
+
 M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
-M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
+M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
 M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
+M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
 
 M_VIVADO := vivado -mode batch -source
 
@@ -52,9 +53,9 @@ axi_ad7616.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_ad7616_ip.tcl  >> axi_ad7616_ip.log 2>&1
 
 dep:
-	make -C ../spi_engine/spi_engine_execution/
 	make -C ../spi_engine/axi_spi_engine/
-	make -C ../spi_engine/spi_engine_offload/
+	make -C ../spi_engine/spi_engine_execution/
 	make -C ../spi_engine/spi_engine_interconnect/
+	make -C ../spi_engine/spi_engine_offload/
 ####################################################################################
 ####################################################################################
diff --git a/library/axi_ad9122/Makefile b/library/axi_ad9122/Makefile
index d4ede90f8..8989cf8df 100644
--- a/library/axi_ad9122/Makefile
+++ b/library/axi_ad9122/Makefile
@@ -5,29 +5,29 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9122_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../common/ad_dds_sine.v
-M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_mmcm_drp.v
-M_DEPS += ../xilinx/common/ad_serdes_out.v
-M_DEPS += ../xilinx/common/ad_serdes_clk.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/up_dac_common.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_dac_common.v
-M_DEPS += ../common/up_dac_channel.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_mmcm_drp.v
+M_DEPS += ../xilinx/common/ad_mul.v
+M_DEPS += ../xilinx/common/ad_serdes_clk.v
+M_DEPS += ../xilinx/common/ad_serdes_out.v
+M_DEPS += axi_ad9122.v
 M_DEPS += axi_ad9122_channel.v
+M_DEPS += axi_ad9122_constr.xdc
 M_DEPS += axi_ad9122_core.v
 M_DEPS += axi_ad9122_if.v
-M_DEPS += axi_ad9122_constr.xdc
-M_DEPS += axi_ad9122.v
+M_DEPS += axi_ad9122_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9144/Makefile b/library/axi_ad9144/Makefile
index 79c695e2c..12f3e8fb9 100644
--- a/library/axi_ad9144/Makefile
+++ b/library/axi_ad9144/Makefile
@@ -5,25 +5,25 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9144_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../common/ad_dds_sine.v
-M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_rst.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/up_dac_common.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_dac_common.v
-M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_mul.v
+M_DEPS += axi_ad9144.v
 M_DEPS += axi_ad9144_channel.v
 M_DEPS += axi_ad9144_core.v
 M_DEPS += axi_ad9144_if.v
-M_DEPS += axi_ad9144.v
+M_DEPS += axi_ad9144_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9152/Makefile b/library/axi_ad9152/Makefile
index ae659d94a..1d43a55bc 100644
--- a/library/axi_ad9152/Makefile
+++ b/library/axi_ad9152/Makefile
@@ -5,25 +5,25 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9152_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../common/ad_dds_sine.v
-M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_rst.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/up_dac_common.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_dac_common.v
-M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_mul.v
+M_DEPS += axi_ad9152.v
 M_DEPS += axi_ad9152_channel.v
 M_DEPS += axi_ad9152_core.v
 M_DEPS += axi_ad9152_if.v
-M_DEPS += axi_ad9152.v
+M_DEPS += axi_ad9152_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9162/Makefile b/library/axi_ad9162/Makefile
index ac071973d..874689463 100644
--- a/library/axi_ad9162/Makefile
+++ b/library/axi_ad9162/Makefile
@@ -5,25 +5,25 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9162_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../common/ad_dds_sine.v
-M_DEPS += ../common/ad_dds_1.v
 M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_rst.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/up_dac_common.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_dac_common.v
-M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_mul.v
+M_DEPS += axi_ad9162.v
 M_DEPS += axi_ad9162_channel.v
 M_DEPS += axi_ad9162_core.v
 M_DEPS += axi_ad9162_if.v
-M_DEPS += axi_ad9162.v
+M_DEPS += axi_ad9162_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9234/Makefile b/library/axi_ad9234/Makefile
index b034edda7..ebcef7e79 100644
--- a/library/axi_ad9234/Makefile
+++ b/library/axi_ad9234/Makefile
@@ -5,22 +5,22 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9234_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
 M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += axi_ad9234_pnmon.v
-M_DEPS += axi_ad9234_channel.v
-M_DEPS += axi_ad9234_if.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_ad9234.v
+M_DEPS += axi_ad9234_channel.v
 M_DEPS += axi_ad9234_constr.xdc
+M_DEPS += axi_ad9234_if.v
+M_DEPS += axi_ad9234_ip.tcl
+M_DEPS += axi_ad9234_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9250/Makefile b/library/axi_ad9250/Makefile
index 3db35f835..6d8901ff0 100644
--- a/library/axi_ad9250/Makefile
+++ b/library/axi_ad9250/Makefile
@@ -5,25 +5,25 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9250_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/ad_xcvr_rx_if.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad9250_pnmon.v
-M_DEPS += axi_ad9250_channel.v
-M_DEPS += axi_ad9250_if.v
-M_DEPS += axi_ad9250_constr.xdc
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_ad9250.v
+M_DEPS += axi_ad9250_channel.v
+M_DEPS += axi_ad9250_constr.xdc
+M_DEPS += axi_ad9250_if.v
+M_DEPS += axi_ad9250_ip.tcl
+M_DEPS += axi_ad9250_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9265/Makefile b/library/axi_ad9265/Makefile
index bbff12cb5..d7beb31c9 100644
--- a/library/axi_ad9265/Makefile
+++ b/library/axi_ad9265/Makefile
@@ -5,28 +5,28 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9265_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_lvds_clk.v
-M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_dcfilter.v
 M_DEPS += ../common/ad_pnmon.v
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad9265_pnmon.v
-M_DEPS += axi_ad9265_if.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += axi_ad9265.v
 M_DEPS += axi_ad9265_channel.v
 M_DEPS += axi_ad9265_constr.xdc
-M_DEPS += axi_ad9265.v
+M_DEPS += axi_ad9265_if.v
+M_DEPS += axi_ad9265_ip.tcl
+M_DEPS += axi_ad9265_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile
index 929c08fff..edf2c8ba0 100644
--- a/library/axi_ad9361/Makefile
+++ b/library/axi_ad9361/Makefile
@@ -5,48 +5,48 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9361_ip.tcl
+M_DEPS += ../common/ad_addsub.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_dcfilter.v
+M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds_sine.v
+M_DEPS += ../common/ad_iqcor.v
+M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_tdd_control.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/up_dac_common.v
+M_DEPS += ../common/up_delay_cntrl.v
+M_DEPS += ../common/up_tdd_cntrl.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_lvds_clk.v
-M_DEPS += ../xilinx/common/ad_lvds_in.v
-M_DEPS += ../xilinx/common/ad_lvds_out.v
 M_DEPS += ../xilinx/common/ad_cmos_clk.v
 M_DEPS += ../xilinx/common/ad_cmos_in.v
 M_DEPS += ../xilinx/common/ad_cmos_out.v
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_lvds_out.v
 M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../common/ad_pnmon.v
-M_DEPS += ../common/ad_dds_sine.v
-M_DEPS += ../common/ad_dds_1.v
-M_DEPS += ../common/ad_dds.v
-M_DEPS += ../common/ad_datafmt.v
-M_DEPS += ../common/ad_dcfilter.v
-M_DEPS += ../common/ad_iqcor.v
-M_DEPS += ../common/ad_addsub.v
-M_DEPS += ../common/ad_tdd_control.v
-M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/up_xfer_cntrl.v
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_delay_cntrl.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/up_dac_common.v
-M_DEPS += ../common/up_dac_channel.v
-M_DEPS += ../common/up_tdd_cntrl.v
+M_DEPS += axi_ad9361.v
 M_DEPS += axi_ad9361_constr.xdc
-M_DEPS += xilinx/axi_ad9361_lvds_if.v
-M_DEPS += xilinx/axi_ad9361_cmos_if.v
-M_DEPS += axi_ad9361_rx_pnmon.v
-M_DEPS += axi_ad9361_rx_channel.v
+M_DEPS += axi_ad9361_ip.tcl
 M_DEPS += axi_ad9361_rx.v
-M_DEPS += axi_ad9361_tx_channel.v
-M_DEPS += axi_ad9361_tx.v
+M_DEPS += axi_ad9361_rx_channel.v
+M_DEPS += axi_ad9361_rx_pnmon.v
 M_DEPS += axi_ad9361_tdd.v
 M_DEPS += axi_ad9361_tdd_if.v
-M_DEPS += axi_ad9361.v
+M_DEPS += axi_ad9361_tx.v
+M_DEPS += axi_ad9361_tx_channel.v
+M_DEPS += xilinx/axi_ad9361_cmos_if.v
+M_DEPS += xilinx/axi_ad9361_lvds_if.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9371/Makefile b/library/axi_ad9371/Makefile
index e27d4464c..1b512eb5a 100644
--- a/library/axi_ad9371/Makefile
+++ b/library/axi_ad9371/Makefile
@@ -5,34 +5,34 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9371_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../common/ad_dds_sine.v
-M_DEPS += ../common/ad_dds_1.v
-M_DEPS += ../common/ad_dds.v
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_dcfilter.v
+M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds_sine.v
 M_DEPS += ../common/ad_iqcor.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/up_dac_common.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/up_dac_common.v
-M_DEPS += ../common/up_dac_channel.v
-M_DEPS += ../common/ad_xcvr_rx_if.v
-M_DEPS += axi_ad9371_if.v
-M_DEPS += axi_ad9371_rx_channel.v
-M_DEPS += axi_ad9371_rx.v
-M_DEPS += axi_ad9371_rx_os.v
-M_DEPS += axi_ad9371_tx_channel.v
-M_DEPS += axi_ad9371_tx.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += axi_ad9371.v
+M_DEPS += axi_ad9371_if.v
+M_DEPS += axi_ad9371_ip.tcl
+M_DEPS += axi_ad9371_rx.v
+M_DEPS += axi_ad9371_rx_channel.v
+M_DEPS += axi_ad9371_rx_os.v
+M_DEPS += axi_ad9371_tx.v
+M_DEPS += axi_ad9371_tx_channel.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9434/Makefile b/library/axi_ad9434/Makefile
index b924b1398..f950dc456 100644
--- a/library/axi_ad9434/Makefile
+++ b/library/axi_ad9434/Makefile
@@ -5,28 +5,28 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9434_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../xilinx/common/ad_serdes_clk.v
-M_DEPS += ../xilinx/common/ad_mmcm_drp.v
-M_DEPS += ../xilinx/common/ad_serdes_in.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_pnmon.v
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/up_xfer_cntrl.v
-M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/ad_pnmon.v
-M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad9434_if.v
-M_DEPS += axi_ad9434_pnmon.v
-M_DEPS += axi_ad9434_core.v
-M_DEPS += axi_ad9434_constr.xdc
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_mmcm_drp.v
+M_DEPS += ../xilinx/common/ad_serdes_clk.v
+M_DEPS += ../xilinx/common/ad_serdes_in.v
 M_DEPS += axi_ad9434.v
+M_DEPS += axi_ad9434_constr.xdc
+M_DEPS += axi_ad9434_core.v
+M_DEPS += axi_ad9434_if.v
+M_DEPS += axi_ad9434_ip.tcl
+M_DEPS += axi_ad9434_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9467/Makefile b/library/axi_ad9467/Makefile
index 649976a9e..56e03068e 100644
--- a/library/axi_ad9467/Makefile
+++ b/library/axi_ad9467/Makefile
@@ -5,27 +5,27 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9467_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_lvds_clk.v
-M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_pnmon.v
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad9467_pnmon.v
-M_DEPS += axi_ad9467_if.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += axi_ad9467.v
 M_DEPS += axi_ad9467_channel.v
 M_DEPS += axi_ad9467_constr.xdc
-M_DEPS += axi_ad9467.v
+M_DEPS += axi_ad9467_if.v
+M_DEPS += axi_ad9467_ip.tcl
+M_DEPS += axi_ad9467_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9625/Makefile b/library/axi_ad9625/Makefile
index d8ff97721..e7c9115e4 100644
--- a/library/axi_ad9625/Makefile
+++ b/library/axi_ad9625/Makefile
@@ -5,26 +5,26 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9625_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_mem.v
 M_DEPS += ../common/ad_pnmon.v
-M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../common/ad_xcvr_rx_if.v
-M_DEPS += axi_ad9625_pnmon.v
-M_DEPS += axi_ad9625_channel.v
-M_DEPS += axi_ad9625_if.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_ad9625.v
+M_DEPS += axi_ad9625_channel.v
 M_DEPS += axi_ad9625_constr.xdc
+M_DEPS += axi_ad9625_if.v
+M_DEPS += axi_ad9625_ip.tcl
+M_DEPS += axi_ad9625_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9643/Makefile b/library/axi_ad9643/Makefile
index 834b235cc..a2cc20274 100644
--- a/library/axi_ad9643/Makefile
+++ b/library/axi_ad9643/Makefile
@@ -5,30 +5,30 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9643_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../xilinx/common/ad_lvds_clk.v
-M_DEPS += ../xilinx/common/ad_lvds_in.v
-M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_dcfilter.v
 M_DEPS += ../common/ad_iqcor.v
+M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/up_xfer_cntrl.v
-M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad9643_pnmon.v
-M_DEPS += axi_ad9643_channel.v
-M_DEPS += axi_ad9643_if.v
-M_DEPS += axi_ad9643_constr.xdc
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += axi_ad9643.v
+M_DEPS += axi_ad9643_channel.v
+M_DEPS += axi_ad9643_constr.xdc
+M_DEPS += axi_ad9643_if.v
+M_DEPS += axi_ad9643_ip.tcl
+M_DEPS += axi_ad9643_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9652/Makefile b/library/axi_ad9652/Makefile
index 6a12efda9..baa78f217 100644
--- a/library/axi_ad9652/Makefile
+++ b/library/axi_ad9652/Makefile
@@ -5,29 +5,29 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9652_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../xilinx/common/ad_lvds_clk.v
-M_DEPS += ../xilinx/common/ad_lvds_in.v
-M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_dcfilter.v
 M_DEPS += ../common/ad_iqcor.v
+M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/up_xfer_cntrl.v
-M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad9652_pnmon.v
-M_DEPS += axi_ad9652_channel.v
-M_DEPS += axi_ad9652_if.v
-M_DEPS += axi_ad9652_constr.xdc
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_lvds_clk.v
+M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_mul.v
 M_DEPS += axi_ad9652.v
+M_DEPS += axi_ad9652_channel.v
+M_DEPS += axi_ad9652_constr.xdc
+M_DEPS += axi_ad9652_if.v
+M_DEPS += axi_ad9652_ip.tcl
+M_DEPS += axi_ad9652_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9671/Makefile b/library/axi_ad9671/Makefile
index 48dc964a2..f5424efcc 100644
--- a/library/axi_ad9671/Makefile
+++ b/library/axi_ad9671/Makefile
@@ -5,25 +5,26 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9671_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_mem.v
+M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/ad_mem.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad9671_pnmon.v
-M_DEPS += axi_ad9671_channel.v
-M_DEPS += axi_ad9671_if.v
-M_DEPS += axi_ad9671_constr.xdc
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_ad9671.v
+M_DEPS += axi_ad9671_channel.v
+M_DEPS += axi_ad9671_constr.xdc
+M_DEPS += axi_ad9671_if.v
+M_DEPS += axi_ad9671_ip.tcl
+M_DEPS += axi_ad9671_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9680/Makefile b/library/axi_ad9680/Makefile
index a27151775..6bf938799 100644
--- a/library/axi_ad9680/Makefile
+++ b/library/axi_ad9680/Makefile
@@ -5,24 +5,24 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9680_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_xcvr_rx_if.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/ad_xcvr_rx_if.v
-M_DEPS += axi_ad9680_pnmon.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += axi_ad9680.v
 M_DEPS += axi_ad9680_channel.v
 M_DEPS += axi_ad9680_if.v
-M_DEPS += axi_ad9680.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += axi_ad9680_ip.tcl
+M_DEPS += axi_ad9680_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9684/Makefile b/library/axi_ad9684/Makefile
index 4754a0f74..2a198b631 100644
--- a/library/axi_ad9684/Makefile
+++ b/library/axi_ad9684/Makefile
@@ -5,28 +5,28 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9684_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_serdes_in.v
-M_DEPS += ../xilinx/common/ad_serdes_clk.v
-M_DEPS += ../xilinx/common/ad_mmcm_drp.v
+M_DEPS += ../common/ad_axi_ip_constr.xdc
 M_DEPS += ../common/ad_datafmt.v
 M_DEPS += ../common/ad_pnmon.v
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += axi_ad9684_pnmon.v
-M_DEPS += axi_ad9684_if.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_mmcm_drp.v
+M_DEPS += ../xilinx/common/ad_serdes_clk.v
+M_DEPS += ../xilinx/common/ad_serdes_in.v
+M_DEPS += axi_ad9684.v
 M_DEPS += axi_ad9684_channel.v
 M_DEPS += axi_ad9684_constr.xdc
-M_DEPS += axi_ad9684.v
+M_DEPS += axi_ad9684_if.v
+M_DEPS += axi_ad9684_ip.tcl
+M_DEPS += axi_ad9684_pnmon.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_ad9739a/Makefile b/library/axi_ad9739a/Makefile
index 0728a461e..1fa25b7e9 100644
--- a/library/axi_ad9739a/Makefile
+++ b/library/axi_ad9739a/Makefile
@@ -5,27 +5,27 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_ad9739a_ip.tcl
+M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds_sine.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/up_dac_common.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../xilinx/common/ad_mul.v
-M_DEPS += ../common/ad_dds_sine.v
-M_DEPS += ../common/ad_dds_1.v
-M_DEPS += ../common/ad_dds.v
-M_DEPS += ../common/ad_rst.v
 M_DEPS += ../xilinx/common/ad_serdes_out.v
-M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/up_xfer_cntrl.v
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_dac_common.v
-M_DEPS += ../common/up_dac_channel.v
-M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += axi_ad9739a.v
 M_DEPS += axi_ad9739a_channel.v
+M_DEPS += axi_ad9739a_constr.xdc
 M_DEPS += axi_ad9739a_core.v
 M_DEPS += axi_ad9739a_if.v
-M_DEPS += axi_ad9739a_constr.xdc
-M_DEPS += axi_ad9739a.v
+M_DEPS += axi_ad9739a_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_clkgen/Makefile b/library/axi_clkgen/Makefile
index 2936da44b..785af8fd6 100644
--- a/library/axi_clkgen/Makefile
+++ b/library/axi_clkgen/Makefile
@@ -5,15 +5,15 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_clkgen_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../xilinx/common/ad_mmcm_drp.v
 M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_clkgen.v
-M_DEPS += axi_clkgen_constr.xdc
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_mmcm_drp.v
 M_DEPS += axi_clkgen.v
+M_DEPS += axi_clkgen_constr.xdc
+M_DEPS += axi_clkgen_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile
index df36863dd..cebb500d9 100644
--- a/library/axi_dmac/Makefile
+++ b/library/axi_dmac/Makefile
@@ -5,31 +5,35 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_dmac_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/sync_bits.v
 M_DEPS += ../common/up_axi.v
-M_DEPS += address_generator.v
-M_DEPS += data_mover.v
-M_DEPS += request_arb.v
-M_DEPS += request_generator.v
-M_DEPS += response_handler.v
-M_DEPS += axi_register_slice.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += 2d_transfer.v
+M_DEPS += address_generator.v
+M_DEPS += axi_dmac.v
+M_DEPS += axi_dmac_ip.tcl
+M_DEPS += axi_register_slice.v
+M_DEPS += data_mover.v
 M_DEPS += dest_axi_mm.v
 M_DEPS += dest_axi_stream.v
 M_DEPS += dest_fifo_inf.v
+M_DEPS += request_arb.v
+M_DEPS += request_generator.v
+M_DEPS += response_generator.v
+M_DEPS += response_handler.v
+M_DEPS += splitter.v
 M_DEPS += src_axi_mm.v
 M_DEPS += src_axi_stream.v
 M_DEPS += src_fifo_inf.v
-M_DEPS += splitter.v
-M_DEPS += response_generator.v
-M_DEPS += axi_dmac.v
-M_DEPS += axi_dmac_constr.ttcl
-M_DEPS += bd/bd.tcl
-M_DEPS += ../util_axis_resize/util_axis_resize.xpr
+
 M_DEPS += ../util_axis_fifo/util_axis_fifo.xpr
+M_DEPS += ../util_axis_resize/util_axis_resize.xpr
+
+M_DEPS += ../interfaces/fifo_rd.xml
+M_DEPS += ../interfaces/fifo_rd_rtl.xml
+M_DEPS += ../interfaces/fifo_wr.xml
+M_DEPS += ../interfaces/fifo_wr_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
@@ -64,7 +68,7 @@ axi_dmac.xpr: $(M_DEPS)
 	$(M_VIVADO) axi_dmac_ip.tcl  >> axi_dmac_ip.log 2>&1
 
 dep:
-	make -C ../util_axis_resize/
 	make -C ../util_axis_fifo/
+	make -C ../util_axis_resize/
 ####################################################################################
 ####################################################################################
diff --git a/library/axi_generic_adc/Makefile b/library/axi_generic_adc/Makefile
index 0b493a6f9..2efbcfbf7 100644
--- a/library/axi_generic_adc/Makefile
+++ b/library/axi_generic_adc/Makefile
@@ -5,18 +5,18 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_generic_adc_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_generic_adc.v
+M_DEPS += axi_generic_adc_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_gpreg/Makefile b/library/axi_gpreg/Makefile
index a7d7a1d06..1b61f384d 100644
--- a/library/axi_gpreg/Makefile
+++ b/library/axi_gpreg/Makefile
@@ -5,16 +5,16 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_gpreg_ip.tcl
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_axi.v
+M_DEPS += axi_gpreg.v
+M_DEPS += axi_gpreg_clock_mon.v
 M_DEPS += axi_gpreg_constr.xdc
 M_DEPS += axi_gpreg_io.v
-M_DEPS += axi_gpreg_clock_mon.v
-M_DEPS += axi_gpreg.v
+M_DEPS += axi_gpreg_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_hdmi_rx/Makefile b/library/axi_hdmi_rx/Makefile
index d2df089de..370f3d528 100644
--- a/library/axi_hdmi_rx/Makefile
+++ b/library/axi_hdmi_rx/Makefile
@@ -5,26 +5,26 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_hdmi_rx_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
-M_DEPS += ../common/ad_rst.v
 M_DEPS += ../common/ad_csc_1.v
-M_DEPS += ../common/ad_csc_1_mul.v
 M_DEPS += ../common/ad_csc_1_add.v
-M_DEPS += ../common/ad_ss_422to444.v
+M_DEPS += ../common/ad_csc_1_mul.v
 M_DEPS += ../common/ad_csc_CrYCb2RGB.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/ad_ss_422to444.v
 M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_hdmi_rx.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_hdmi_rx.v
-M_DEPS += axi_hdmi_rx_es.v
-M_DEPS += axi_hdmi_rx_tpm.v
 M_DEPS += axi_hdmi_rx_constr.xdc
 M_DEPS += axi_hdmi_rx_core.v
+M_DEPS += axi_hdmi_rx_es.v
+M_DEPS += axi_hdmi_rx_ip.tcl
+M_DEPS += axi_hdmi_rx_tpm.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_hdmi_tx/Makefile b/library/axi_hdmi_tx/Makefile
index 05ae19233..4bb5e3319 100644
--- a/library/axi_hdmi_tx/Makefile
+++ b/library/axi_hdmi_tx/Makefile
@@ -5,27 +5,27 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_hdmi_tx_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../common/ad_csc_1.v
+M_DEPS += ../common/ad_csc_1_add.v
+M_DEPS += ../common/ad_csc_1_mul.v
+M_DEPS += ../common/ad_csc_RGB2CrYCb.v
 M_DEPS += ../common/ad_mem.v
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/ad_csc_1_mul.v
-M_DEPS += ../common/ad_csc_1_add.v
-M_DEPS += ../common/ad_csc_1.v
-M_DEPS += ../common/ad_csc_RGB2CrYCb.v
 M_DEPS += ../common/ad_ss_444to422.v
 M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/up_xfer_cntrl.v
-M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_hdmi_tx.v
-M_DEPS += axi_hdmi_tx_constr.xdc
-M_DEPS += axi_hdmi_tx_vdma.v
-M_DEPS += axi_hdmi_tx_es.v
-M_DEPS += axi_hdmi_tx_core.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_hdmi_tx.v
+M_DEPS += axi_hdmi_tx_constr.xdc
+M_DEPS += axi_hdmi_tx_core.v
+M_DEPS += axi_hdmi_tx_es.v
+M_DEPS += axi_hdmi_tx_ip.tcl
+M_DEPS += axi_hdmi_tx_vdma.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_i2s_adi/Makefile b/library/axi_i2s_adi/Makefile
index afe04c7fd..1294ce309 100644
--- a/library/axi_i2s_adi/Makefile
+++ b/library/axi_i2s_adi/Makefile
@@ -5,21 +5,24 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_i2s_adi_ip.tcl
+M_DEPS += ../common/axi_ctrlif.vhd
+M_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
+M_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
+M_DEPS += ../common/dma_fifo.vhd
+M_DEPS += ../common/pl330_dma_fifo.vhd
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/axi_ctrlif.vhd
-M_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
-M_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
-M_DEPS += ../common/pl330_dma_fifo.vhd
-M_DEPS += ../common/dma_fifo.vhd
+M_DEPS += axi_i2s_adi.vhd
+M_DEPS += axi_i2s_adi_constr.xdc
+M_DEPS += axi_i2s_adi_ip.tcl
+M_DEPS += fifo_synchronizer.vhd
+M_DEPS += i2s_clkgen.vhd
 M_DEPS += i2s_controller.vhd
 M_DEPS += i2s_rx.vhd
 M_DEPS += i2s_tx.vhd
-M_DEPS += i2s_clkgen.vhd
-M_DEPS += fifo_synchronizer.vhd
-M_DEPS += axi_i2s_adi.vhd
-M_DEPS += axi_i2s_adi_constr.xdc
+
+M_DEPS += ../axi_i2s_adi/i2s.xml
+M_DEPS += ../axi_i2s_adi/i2s_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_intr_monitor/Makefile b/library/axi_intr_monitor/Makefile
index 058630d0e..5a6d5cc98 100644
--- a/library/axi_intr_monitor/Makefile
+++ b/library/axi_intr_monitor/Makefile
@@ -5,11 +5,11 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_intr_monitor_ip.tcl
+M_DEPS += ../common/up_axi.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/up_axi.v
 M_DEPS += axi_intr_monitor.v
+M_DEPS += axi_intr_monitor_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_mc_controller/Makefile b/library/axi_mc_controller/Makefile
index b024ae86c..0b0937a3d 100644
--- a/library/axi_mc_controller/Makefile
+++ b/library/axi_mc_controller/Makefile
@@ -5,23 +5,22 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_mc_controller_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_delay_cntrl.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += motor_driver.v
-M_DEPS += delay.v
-M_DEPS += control_registers.v
-M_DEPS += axi_mc_controller_constr.xdc
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_mc_controller.v
+M_DEPS += axi_mc_controller_constr.xdc
+M_DEPS += axi_mc_controller_ip.tcl
+M_DEPS += control_registers.v
+M_DEPS += delay.v
+M_DEPS += motor_driver.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_mc_current_monitor/Makefile b/library/axi_mc_current_monitor/Makefile
index 90aad4d97..08e2ba4c3 100644
--- a/library/axi_mc_current_monitor/Makefile
+++ b/library/axi_mc_current_monitor/Makefile
@@ -5,21 +5,21 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_mc_current_monitor_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
 M_DEPS += ../common/up_delay_cntrl.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_clock_mon.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += dec256sinc24b.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ad7401.v
-M_DEPS += axi_mc_current_monitor_constr.xdc
 M_DEPS += axi_mc_current_monitor.v
+M_DEPS += axi_mc_current_monitor_constr.xdc
+M_DEPS += axi_mc_current_monitor_ip.tcl
+M_DEPS += dec256sinc24b.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_mc_speed/Makefile b/library/axi_mc_speed/Makefile
index 8b0d8bf69..50a3910b5 100644
--- a/library/axi_mc_speed/Makefile
+++ b/library/axi_mc_speed/Makefile
@@ -5,22 +5,22 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_mc_speed_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
 M_DEPS += ../common/up_axi.v
-M_DEPS += ../common/up_delay_cntrl.v
 M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_delay_cntrl.v
 M_DEPS += ../common/up_xfer_cntrl.v
 M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../common/up_adc_common.v
-M_DEPS += ../common/up_adc_channel.v
-M_DEPS += debouncer.v
-M_DEPS += speed_detector.v
-M_DEPS += delay_30_degrees.v
-M_DEPS += axi_mc_speed_constr.xdc
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_mc_speed.v
+M_DEPS += axi_mc_speed_constr.xdc
+M_DEPS += axi_mc_speed_ip.tcl
+M_DEPS += debouncer.v
+M_DEPS += delay_30_degrees.v
+M_DEPS += speed_detector.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_spdif_rx/Makefile b/library/axi_spdif_rx/Makefile
index 4f0a507df..1504dd869 100644
--- a/library/axi_spdif_rx/Makefile
+++ b/library/axi_spdif_rx/Makefile
@@ -5,19 +5,19 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_spdif_rx_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/axi_ctrlif.vhd
 M_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
-M_DEPS += ../common/pl330_dma_fifo.vhd
 M_DEPS += ../common/dma_fifo.vhd
-M_DEPS += rx_phase_det.vhd
-M_DEPS += rx_package.vhd
-M_DEPS += rx_decode.vhd
-M_DEPS += rx_status_reg.vhd
+M_DEPS += ../common/pl330_dma_fifo.vhd
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_spdif_rx.vhd
 M_DEPS += axi_spdif_rx_constr.xdc
+M_DEPS += axi_spdif_rx_ip.tcl
+M_DEPS += rx_decode.vhd
+M_DEPS += rx_package.vhd
+M_DEPS += rx_phase_det.vhd
+M_DEPS += rx_status_reg.vhd
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_spdif_tx/Makefile b/library/axi_spdif_tx/Makefile
index 8796f7dbd..4e933fff4 100644
--- a/library/axi_spdif_tx/Makefile
+++ b/library/axi_spdif_tx/Makefile
@@ -5,17 +5,17 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_spdif_tx_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/axi_ctrlif.vhd
 M_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
-M_DEPS += ../common/pl330_dma_fifo.vhd
 M_DEPS += ../common/dma_fifo.vhd
-M_DEPS += tx_package.vhd
-M_DEPS += tx_encoder.vhd
+M_DEPS += ../common/pl330_dma_fifo.vhd
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += axi_spdif_tx.vhd
 M_DEPS += axi_spdif_tx_constr.xdc
+M_DEPS += axi_spdif_tx_ip.tcl
+M_DEPS += tx_encoder.vhd
+M_DEPS += tx_package.vhd
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/axi_usb_fx3/Makefile b/library/axi_usb_fx3/Makefile
index 762062712..904d9deb6 100644
--- a/library/axi_usb_fx3/Makefile
+++ b/library/axi_usb_fx3/Makefile
@@ -5,14 +5,14 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_usb_fx3_ip.tcl
+M_DEPS += ../common/up_axi.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/up_axi.v
+M_DEPS += axi_usb_fx3.v
 M_DEPS += axi_usb_fx3_core.v
 M_DEPS += axi_usb_fx3_if.v
+M_DEPS += axi_usb_fx3_ip.tcl
 M_DEPS += axi_usb_fx3_reg.v
-M_DEPS += axi_usb_fx3.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/cn0363/cn0363_dma_sequencer/Makefile b/library/cn0363/cn0363_dma_sequencer/Makefile
index 8121ee0cc..82adb137b 100644
--- a/library/cn0363/cn0363_dma_sequencer/Makefile
+++ b/library/cn0363/cn0363_dma_sequencer/Makefile
@@ -5,10 +5,13 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := cn0363_dma_sequencer_ip.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
 M_DEPS += cn0363_dma_sequencer.v
+M_DEPS += cn0363_dma_sequencer_ip.tcl
+
+M_DEPS += ../../interfaces/fifo_wr.xml
+M_DEPS += ../../interfaces/fifo_wr_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/cn0363/cn0363_phase_data_sync/Makefile b/library/cn0363/cn0363_phase_data_sync/Makefile
index b6be55c46..ff28d4943 100644
--- a/library/cn0363/cn0363_phase_data_sync/Makefile
+++ b/library/cn0363/cn0363_phase_data_sync/Makefile
@@ -5,10 +5,10 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := cn0363_phase_data_sync_ip.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
 M_DEPS += cn0363_phase_data_sync.v
+M_DEPS += cn0363_phase_data_sync_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/cordic_demod/Makefile b/library/cordic_demod/Makefile
index 91c755fa3..dc1ad70ef 100644
--- a/library/cordic_demod/Makefile
+++ b/library/cordic_demod/Makefile
@@ -5,10 +5,10 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := cordic_demod_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += cordic_demod.v
+M_DEPS += cordic_demod_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/spi_engine/axi_spi_engine/Makefile b/library/spi_engine/axi_spi_engine/Makefile
index 74fe28da6..1f3e10406 100644
--- a/library/spi_engine/axi_spi_engine/Makefile
+++ b/library/spi_engine/axi_spi_engine/Makefile
@@ -5,16 +5,22 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_spi_engine_ip.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_ip.tcl
-M_DEPS += axi_spi_engine.v
+M_DEPS += ../../common/ad_rst.v
 M_DEPS += ../../common/sync_bits.v
 M_DEPS += ../../common/sync_gray.v
 M_DEPS += ../../common/up_axi.v
-M_DEPS += ../../common/ad_rst.v
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip.tcl
+M_DEPS += axi_spi_engine.v
+M_DEPS += axi_spi_engine_ip.tcl
+
 M_DEPS += ../../util_axis_fifo/util_axis_fifo.xpr
 
+M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
+
 M_VIVADO := vivado -mode batch -source
 
 M_FLIST := *.cache
diff --git a/library/spi_engine/spi_engine_execution/Makefile b/library/spi_engine/spi_engine_execution/Makefile
index 9e717a20a..0bc6175ef 100644
--- a/library/spi_engine/spi_engine_execution/Makefile
+++ b/library/spi_engine/spi_engine_execution/Makefile
@@ -5,10 +5,15 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := spi_engine_execution_ip.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
 M_DEPS += spi_engine_execution.v
+M_DEPS += spi_engine_execution_ip.tcl
+
+M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_master.xml
+M_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/spi_engine/spi_engine_interconnect/Makefile b/library/spi_engine/spi_engine_interconnect/Makefile
index 36d30eb7f..fc10187e5 100644
--- a/library/spi_engine/spi_engine_interconnect/Makefile
+++ b/library/spi_engine/spi_engine_interconnect/Makefile
@@ -5,10 +5,13 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := spi_engine_interconnect_ip.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
 M_DEPS += spi_engine_interconnect.v
+M_DEPS += spi_engine_interconnect_ip.tcl
+
+M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/spi_engine/spi_engine_offload/Makefile b/library/spi_engine/spi_engine_offload/Makefile
index ebd78e156..17b7b02f8 100644
--- a/library/spi_engine/spi_engine_offload/Makefile
+++ b/library/spi_engine/spi_engine_offload/Makefile
@@ -5,11 +5,16 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := spi_engine_offload_ip.tcl
+M_DEPS += ../../common/sync_bits.v
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
-M_DEPS += ../../common/sync_bits.v
 M_DEPS += spi_engine_offload.v
+M_DEPS += spi_engine_offload_ip.tcl
+
+M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
+M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_adcfifo/Makefile b/library/util_adcfifo/Makefile
index 24af6734e..5b56692d2 100644
--- a/library/util_adcfifo/Makefile
+++ b/library/util_adcfifo/Makefile
@@ -5,13 +5,13 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_adcfifo_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_axis_inf_rx.v
 M_DEPS += ../common/ad_mem_asym.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_adcfifo.v
 M_DEPS += util_adcfifo_constr.xdc
+M_DEPS += util_adcfifo_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_axis_fifo/Makefile b/library/util_axis_fifo/Makefile
index 6a0b72943..d1e77a7b1 100644
--- a/library/util_axis_fifo/Makefile
+++ b/library/util_axis_fifo/Makefile
@@ -5,15 +5,15 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_axis_fifo_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/sync_bits.v
 M_DEPS += ../common/sync_gray.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += address_gray.v
 M_DEPS += address_gray_pipelined.v
 M_DEPS += address_sync.v
 M_DEPS += util_axis_fifo.v
+M_DEPS += util_axis_fifo_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_axis_resize/Makefile b/library/util_axis_resize/Makefile
index 9166b81b7..61cbf3263 100644
--- a/library/util_axis_resize/Makefile
+++ b/library/util_axis_resize/Makefile
@@ -5,10 +5,10 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_axis_resize_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_axis_resize.v
+M_DEPS += util_axis_resize_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_bsplit/Makefile b/library/util_bsplit/Makefile
index 7ac60dd55..41a6dee5d 100644
--- a/library/util_bsplit/Makefile
+++ b/library/util_bsplit/Makefile
@@ -5,11 +5,11 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_bsplit_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_bsplit.v
 M_DEPS += util_bsplit_constr.xdc
+M_DEPS += util_bsplit_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_ccat/Makefile b/library/util_ccat/Makefile
index 65b7325cf..00939b669 100644
--- a/library/util_ccat/Makefile
+++ b/library/util_ccat/Makefile
@@ -5,11 +5,11 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_ccat_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_ccat.v
 M_DEPS += util_ccat_constr.xdc
+M_DEPS += util_ccat_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_clkdiv/Makefile b/library/util_clkdiv/Makefile
index b80a36fd4..97c55259b 100644
--- a/library/util_clkdiv/Makefile
+++ b/library/util_clkdiv/Makefile
@@ -5,10 +5,10 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_clkdiv_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_clkdiv.v
+M_DEPS += util_clkdiv_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_cpack/Makefile b/library/util_cpack/Makefile
index f18473b98..ee2ec01cb 100644
--- a/library/util_cpack/Makefile
+++ b/library/util_cpack/Makefile
@@ -5,13 +5,13 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_cpack_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += util_cpack_mux.v
-M_DEPS += util_cpack_dsf.v
 M_DEPS += util_cpack.v
 M_DEPS += util_cpack_constr.xdc
+M_DEPS += util_cpack_dsf.v
+M_DEPS += util_cpack_ip.tcl
+M_DEPS += util_cpack_mux.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_dacfifo/Makefile b/library/util_dacfifo/Makefile
index 9998c7c8c..796e81932 100644
--- a/library/util_dacfifo/Makefile
+++ b/library/util_dacfifo/Makefile
@@ -5,12 +5,12 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_dacfifo_ip.tcl
+M_DEPS += ../common/ad_mem.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_mem.v
 M_DEPS += util_dacfifo.v
 M_DEPS += util_dacfifo_constr.xdc
+M_DEPS += util_dacfifo_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_fir_dec/Makefile b/library/util_fir_dec/Makefile
index b6ba6e8f6..8bc0a7537 100644
--- a/library/util_fir_dec/Makefile
+++ b/library/util_fir_dec/Makefile
@@ -5,10 +5,10 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_fir_dec_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_fir_dec.v
+M_DEPS += util_fir_dec_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_fir_int/Makefile b/library/util_fir_int/Makefile
index 9bc6768ba..f2724b225 100644
--- a/library/util_fir_int/Makefile
+++ b/library/util_fir_int/Makefile
@@ -5,10 +5,10 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_fir_int_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_fir_int.v
+M_DEPS += util_fir_int_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_gmii_to_rgmii/Makefile b/library/util_gmii_to_rgmii/Makefile
index e162e3fa6..a0be6713b 100644
--- a/library/util_gmii_to_rgmii/Makefile
+++ b/library/util_gmii_to_rgmii/Makefile
@@ -5,12 +5,12 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_gmii_to_rgmii_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += mdc_mdio.v
-M_DEPS += util_gmii_to_rgmii_constr.xdc
 M_DEPS += util_gmii_to_rgmii.v
+M_DEPS += util_gmii_to_rgmii_constr.xdc
+M_DEPS += util_gmii_to_rgmii_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_gtlb/Makefile b/library/util_gtlb/Makefile
index 469e65bc1..ff750ba99 100644
--- a/library/util_gtlb/Makefile
+++ b/library/util_gtlb/Makefile
@@ -5,16 +5,17 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_gtlb_ip.tcl
+M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += util_gtlb_constr.xdc
 M_DEPS += util_gtlb.v
-M_DEPS += ../interfaces/if_gt_qpll.xml
-M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
+M_DEPS += util_gtlb_constr.xdc
+M_DEPS += util_gtlb_ip.tcl
+
 M_DEPS += ../interfaces/if_gt_pll.xml
 M_DEPS += ../interfaces/if_gt_pll_rtl.xml
+M_DEPS += ../interfaces/if_gt_qpll.xml
+M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
 M_DEPS += ../interfaces/if_gt_rx.xml
 M_DEPS += ../interfaces/if_gt_rx_rtl.xml
 M_DEPS += ../interfaces/if_gt_tx.xml
diff --git a/library/util_i2c_mixer/Makefile b/library/util_i2c_mixer/Makefile
index 77651ba2e..267f22929 100644
--- a/library/util_i2c_mixer/Makefile
+++ b/library/util_i2c_mixer/Makefile
@@ -5,10 +5,10 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_i2c_mixer_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_i2c_mixer.vhd
+M_DEPS += util_i2c_mixer_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_jesd_gt/Makefile b/library/util_jesd_gt/Makefile
index 07cb76d1d..6d40e8177 100644
--- a/library/util_jesd_gt/Makefile
+++ b/library/util_jesd_gt/Makefile
@@ -5,14 +5,15 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_jesd_gt_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_jesd_gt.v
-M_DEPS += ../interfaces/if_gt_qpll.xml
-M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
+M_DEPS += util_jesd_gt_ip.tcl
+
 M_DEPS += ../interfaces/if_gt_pll.xml
 M_DEPS += ../interfaces/if_gt_pll_rtl.xml
+M_DEPS += ../interfaces/if_gt_qpll.xml
+M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
 M_DEPS += ../interfaces/if_gt_rx.xml
 M_DEPS += ../interfaces/if_gt_rx_rtl.xml
 M_DEPS += ../interfaces/if_gt_tx.xml
diff --git a/library/util_mfifo/Makefile b/library/util_mfifo/Makefile
index ced8923e6..dc730cf23 100644
--- a/library/util_mfifo/Makefile
+++ b/library/util_mfifo/Makefile
@@ -5,11 +5,12 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_mfifo_ip.tcl
+M_DEPS += ../common/ad_mem.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_mem.v
 M_DEPS += util_mfifo.v
+M_DEPS += util_mfifo_constr.xdc
+M_DEPS += util_mfifo_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_pmod_adc/Makefile b/library/util_pmod_adc/Makefile
index b5650220f..ba1493d14 100644
--- a/library/util_pmod_adc/Makefile
+++ b/library/util_pmod_adc/Makefile
@@ -5,11 +5,11 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_pmod_adc_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_pmod_adc.v
 M_DEPS += util_pmod_adc_constr.xdc
+M_DEPS += util_pmod_adc_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_pmod_fmeter/Makefile b/library/util_pmod_fmeter/Makefile
index eabeba078..7242ef736 100644
--- a/library/util_pmod_fmeter/Makefile
+++ b/library/util_pmod_fmeter/Makefile
@@ -5,15 +5,15 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_pmod_fmeter_ip.tcl
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += ../common/ad_rst.v
-M_DEPS += ../common/up_xfer_status.v
 M_DEPS += ../common/up_axi.v
 M_DEPS += ../common/up_pmod.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_pmod_fmeter.v
 M_DEPS += util_pmod_fmeter_core.v
+M_DEPS += util_pmod_fmeter_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_rfifo/Makefile b/library/util_rfifo/Makefile
index 1ed8ab239..341510d6f 100644
--- a/library/util_rfifo/Makefile
+++ b/library/util_rfifo/Makefile
@@ -5,11 +5,12 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_rfifo_ip.tcl
+M_DEPS += ../common/ad_mem.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_mem.v
 M_DEPS += util_rfifo.v
+M_DEPS += util_rfifo_constr.xdc
+M_DEPS += util_rfifo_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_sigma_delta_spi/Makefile b/library/util_sigma_delta_spi/Makefile
index 2b29bbf71..51e2658ac 100644
--- a/library/util_sigma_delta_spi/Makefile
+++ b/library/util_sigma_delta_spi/Makefile
@@ -5,10 +5,13 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_sigma_delta_spi_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_sigma_delta_spi.v
+M_DEPS += util_sigma_delta_spi_ip.tcl
+
+M_DEPS += ../spi_engine/interfaces/spi_master.xml
+M_DEPS += ../spi_engine/interfaces/spi_master_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_tdd_sync/Makefile b/library/util_tdd_sync/Makefile
index 211ee2a99..fba94e565 100644
--- a/library/util_tdd_sync/Makefile
+++ b/library/util_tdd_sync/Makefile
@@ -5,11 +5,12 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_tdd_sync_ip.tcl
+M_DEPS += ../common/util_pulse_gen.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/util_pulse_gen.v
 M_DEPS += util_tdd_sync.v
+M_DEPS += util_tdd_sync_constr.xdc
+M_DEPS += util_tdd_sync_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_upack/Makefile b/library/util_upack/Makefile
index 5a294b007..4dc0b413c 100644
--- a/library/util_upack/Makefile
+++ b/library/util_upack/Makefile
@@ -5,13 +5,13 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_upack_ip.tcl
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += util_upack_dmx.v
-M_DEPS += util_upack_dsf.v
 M_DEPS += util_upack.v
 M_DEPS += util_upack_constr.xdc
+M_DEPS += util_upack_dmx.v
+M_DEPS += util_upack_dsf.v
+M_DEPS += util_upack_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/util_wfifo/Makefile b/library/util_wfifo/Makefile
index 3ba185305..b145a2fd0 100644
--- a/library/util_wfifo/Makefile
+++ b/library/util_wfifo/Makefile
@@ -5,11 +5,12 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_wfifo_ip.tcl
+M_DEPS += ../common/ad_mem.v
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += ../common/ad_mem.v
 M_DEPS += util_wfifo.v
+M_DEPS += util_wfifo_constr.xdc
+M_DEPS += util_wfifo_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/xilinx/axi_adcfifo/Makefile b/library/xilinx/axi_adcfifo/Makefile
index 75a50ff56..0d957670f 100644
--- a/library/xilinx/axi_adcfifo/Makefile
+++ b/library/xilinx/axi_adcfifo/Makefile
@@ -5,19 +5,19 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_adcfifo_ip.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_ip.tcl
+M_DEPS += ../../common/ad_axis_inf_rx.v
 M_DEPS += ../../common/ad_mem.v
 M_DEPS += ../../common/ad_mem_asym.v
 M_DEPS += ../../common/up_xfer_status.v
-M_DEPS += ../../common/ad_axis_inf_rx.v
-M_DEPS += axi_adcfifo_adc.v
-M_DEPS += axi_adcfifo_dma.v
-M_DEPS += axi_adcfifo_wr.v
-M_DEPS += axi_adcfifo_rd.v
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip.tcl
 M_DEPS += axi_adcfifo.v
+M_DEPS += axi_adcfifo_adc.v
 M_DEPS += axi_adcfifo_constr.xdc
+M_DEPS += axi_adcfifo_dma.v
+M_DEPS += axi_adcfifo_ip.tcl
+M_DEPS += axi_adcfifo_rd.v
+M_DEPS += axi_adcfifo_wr.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/xilinx/axi_adxcvr/Makefile b/library/xilinx/axi_adxcvr/Makefile
index 34d8a9662..c0c41eac9 100644
--- a/library/xilinx/axi_adxcvr/Makefile
+++ b/library/xilinx/axi_adxcvr/Makefile
@@ -5,19 +5,20 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_adxcvr_ip.tcl
+M_DEPS += ../../common/up_axi.v
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
-M_DEPS += ../../common/up_axi.v
+M_DEPS += axi_adxcvr.v
 M_DEPS += axi_adxcvr_es.v
-M_DEPS += axi_adxcvr_up.v
+M_DEPS += axi_adxcvr_ip.tcl
 M_DEPS += axi_adxcvr_mdrp.v
 M_DEPS += axi_adxcvr_mstatus.v
-M_DEPS += axi_adxcvr.v
-M_DEPS += ../../interfaces/if_xcvr_cm.xml
-M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
+M_DEPS += axi_adxcvr_up.v
+
 M_DEPS += ../../interfaces/if_xcvr_ch.xml
 M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
+M_DEPS += ../../interfaces/if_xcvr_cm.xml
+M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/xilinx/axi_dacfifo/Makefile b/library/xilinx/axi_dacfifo/Makefile
index 16c5919b7..6eefaa5ad 100644
--- a/library/xilinx/axi_dacfifo/Makefile
+++ b/library/xilinx/axi_dacfifo/Makefile
@@ -5,17 +5,17 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_dacfifo_ip.tcl
+M_DEPS += ../../common/ad_axis_inf_rx.v
+M_DEPS += ../../common/ad_mem_asym.v
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
-M_DEPS += ../../common/ad_mem_asym.v
-M_DEPS += ../../common/ad_axis_inf_rx.v
 M_DEPS += ../../util_axis_resize/util_axis_resize.v
+M_DEPS += axi_dacfifo.v
 M_DEPS += axi_dacfifo_constr.xdc
 M_DEPS += axi_dacfifo_dac.v
-M_DEPS += axi_dacfifo_wr.v
+M_DEPS += axi_dacfifo_ip.tcl
 M_DEPS += axi_dacfifo_rd.v
-M_DEPS += axi_dacfifo.v
+M_DEPS += axi_dacfifo_wr.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/xilinx/axi_xcvrlb/Makefile b/library/xilinx/axi_xcvrlb/Makefile
index 8cad2cac1..8dee022ba 100644
--- a/library/xilinx/axi_xcvrlb/Makefile
+++ b/library/xilinx/axi_xcvrlb/Makefile
@@ -5,16 +5,16 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := axi_xcvrlb_ip.tcl
+M_DEPS += ../../common/ad_pnmon.v
+M_DEPS += ../../common/up_axi.v
+M_DEPS += ../../common/up_xfer_status.v
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
 M_DEPS += ../../xilinx/util_adxcvr/util_adxcvr_xch.v
-M_DEPS += ../../common/up_xfer_status.v
-M_DEPS += ../../common/ad_pnmon.v
-M_DEPS += ../../common/up_axi.v
-M_DEPS += axi_xcvrlb_constr.xdc
-M_DEPS += axi_xcvrlb_1.v
 M_DEPS += axi_xcvrlb.v
+M_DEPS += axi_xcvrlb_1.v
+M_DEPS += axi_xcvrlb_constr.xdc
+M_DEPS += axi_xcvrlb_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/xilinx/util_adxcvr/Makefile b/library/xilinx/util_adxcvr/Makefile
index 22062b7b4..7df5f8cd8 100644
--- a/library/xilinx/util_adxcvr/Makefile
+++ b/library/xilinx/util_adxcvr/Makefile
@@ -5,17 +5,18 @@
 ####################################################################################
 ####################################################################################
 
-M_DEPS := util_adxcvr_ip.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_ip.tcl
-M_DEPS += util_adxcvr_constr.xdc
-M_DEPS += util_adxcvr_xcm.v
-M_DEPS += util_adxcvr_xch.v
 M_DEPS += util_adxcvr.v
-M_DEPS += ../../interfaces/if_xcvr_cm.xml
-M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
+M_DEPS += util_adxcvr_constr.xdc
+M_DEPS += util_adxcvr_ip.tcl
+M_DEPS += util_adxcvr_xch.v
+M_DEPS += util_adxcvr_xcm.v
+
 M_DEPS += ../../interfaces/if_xcvr_ch.xml
 M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
+M_DEPS += ../../interfaces/if_xcvr_cm.xml
+M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile
index 29e53e7d3..81de40959 100644
--- a/projects/ad7616_sdz/zc706/Makefile
+++ b/projects/ad7616_sdz/zc706/Makefile
@@ -16,10 +16,8 @@ M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
-M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile
index 4b61c5ee4..bf5b20304 100644
--- a/projects/ad7616_sdz/zed/Makefile
+++ b/projects/ad7616_sdz/zed/Makefile
@@ -16,10 +16,8 @@ M_DEPS += ../../scripts/adi_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
-M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile
index ce1259b4a..9ea98e593 100644
--- a/projects/adrv9371x/a10gx/Makefile
+++ b/projects/adrv9371x/a10gx/Makefile
@@ -16,7 +16,9 @@ M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += ../common/adrv9371x_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
@@ -38,6 +40,7 @@ M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx_channel.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
 M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
 M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
 M_DEPS += ../../../library/axi_dmac/data_mover.v
@@ -54,6 +57,7 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
@@ -73,7 +77,10 @@ M_DEPS += ../../../library/common/up_dac_channel.v
 M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile
index 1999474d0..07188ad32 100644
--- a/projects/adrv9371x/a10soc/Makefile
+++ b/projects/adrv9371x/a10soc/Makefile
@@ -16,7 +16,9 @@ M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += ../common/adrv9371x_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
 M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
 M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
@@ -38,6 +40,7 @@ M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx_channel.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
 M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
 M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
 M_DEPS += ../../../library/axi_dmac/data_mover.v
@@ -54,6 +57,7 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
@@ -73,7 +77,10 @@ M_DEPS += ../../../library/common/up_dac_channel.v
 M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index 4de40a701..c29777bfa 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -14,52 +14,8 @@ export ALT_NIOS_MMU_ENABLED := $(MMU)
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
-M_DEPS += system_bd.qsys
-M_DEPS += ../common/arradio_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys
 M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
-M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
-M_DEPS += ../../../library/axi_dmac/2d_transfer.v
-M_DEPS += ../../../library/axi_dmac/address_generator.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac.v
-M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
-M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
-M_DEPS += ../../../library/axi_dmac/data_mover.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
-M_DEPS += ../../../library/axi_dmac/inc_id.h
-M_DEPS += ../../../library/axi_dmac/request_arb.v
-M_DEPS += ../../../library/axi_dmac/request_generator.v
-M_DEPS += ../../../library/axi_dmac/resp.h
-M_DEPS += ../../../library/axi_dmac/response_generator.v
-M_DEPS += ../../../library/axi_dmac/response_handler.v
-M_DEPS += ../../../library/axi_dmac/splitter.v
-M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
-M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
-M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
-M_DEPS += ../../../library/common/ad_mem.v
-M_DEPS += ../../../library/common/sync_bits.v
-M_DEPS += ../../../library/common/sync_gray.v
-M_DEPS += ../../../library/common/up_axi.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray.v
-M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
-M_DEPS += ../../../library/util_axis_fifo/address_sync.v
-M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
-M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
-M_DEPS += ../../../library/util_cpack/util_cpack.v
-M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
-M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
-M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
-M_DEPS += ../../../library/util_rfifo/util_rfifo.v
-M_DEPS += ../../../library/util_rfifo/util_rfifo_hw.tcl
-M_DEPS += ../../../library/util_upack/util_upack.v
-M_DEPS += ../../../library/util_upack/util_upack_dmx.v
-M_DEPS += ../../../library/util_upack/util_upack_dsf.v
-M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
-M_DEPS += ../../../library/util_wfifo/util_wfifo.v
-M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/common/a5gte/Makefile b/projects/common/a5gte/Makefile
index d782facbf..ee7bdeb71 100644
--- a/projects/common/a5gte/Makefile
+++ b/projects/common/a5gte/Makefile
@@ -14,7 +14,6 @@ export ALT_NIOS_MMU_ENABLED := $(MMU)
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../../projects/scripts/adi_tquest.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/daq1/a10gx/Makefile b/projects/daq1/a10gx/Makefile
index 722419b55..b0a3e7b0f 100644
--- a/projects/daq1/a10gx/Makefile
+++ b/projects/daq1/a10gx/Makefile
@@ -15,24 +15,30 @@ M_DEPS += system_top.v
 M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
+M_DEPS += ../common/daq1_spi.v
 M_DEPS += ../common/daq1_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
-M_DEPS += ../../../library/altera/common/ad_serdes_in.v
+M_DEPS += ../../../library/altera/common/ad_mul.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_channel.v
+M_DEPS += ../../../library/axi_ad9122/axi_ad9122_constr.sdc
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_core.v
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_hw.tcl
 M_DEPS += ../../../library/axi_ad9122/axi_ad9122_if.v
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684.v
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684_channel.v
+M_DEPS += ../../../library/axi_ad9684/axi_ad9684_constr.sdc
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684_hw.tcl
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684_if.v
 M_DEPS += ../../../library/axi_ad9684/axi_ad9684_pnmon.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
 M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
 M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
 M_DEPS += ../../../library/axi_dmac/data_mover.v
@@ -49,6 +55,7 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
@@ -68,7 +75,10 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
@@ -83,9 +93,6 @@ M_DEPS += ../../../library/util_upack/util_upack.v
 M_DEPS += ../../../library/util_upack/util_upack_dmx.v
 M_DEPS += ../../../library/util_upack/util_upack_dsf.v
 M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
-M_DEPS += ../../../library/xilinx/common/ad_mmcm_drp.v
-M_DEPS += ../../../library/xilinx/common/ad_mul.v
-M_DEPS += ../../../library/xilinx/common/ad_serdes_out.v
 
 
 M_ALTERA := quartus_sh --64bit -t 
diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile
index b7184d3c7..35c17a9ac 100644
--- a/projects/daq2/a10gx/Makefile
+++ b/projects/daq2/a10gx/Makefile
@@ -17,7 +17,9 @@ M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += ../common/daq2_spi.v
 M_DEPS += ../common/daq2_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
@@ -40,6 +42,7 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
 M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
 M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
 M_DEPS += ../../../library/axi_dmac/data_mover.v
@@ -56,6 +59,7 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
@@ -76,7 +80,10 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
index 1e067a108..9cd5a1ef9 100644
--- a/projects/daq3/a10gx/Makefile
+++ b/projects/daq3/a10gx/Makefile
@@ -17,7 +17,9 @@ M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += ../common/daq3_spi.v
 M_DEPS += ../common/daq3_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
 M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
@@ -40,6 +42,7 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
 M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
 M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
 M_DEPS += ../../../library/axi_dmac/data_mover.v
@@ -56,6 +59,7 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_dds.v
@@ -76,7 +80,10 @@ M_DEPS += ../../../library/common/up_dac_common.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 933a3bd66..3aff736fa 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -19,6 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index f67ee312d..1f0347e13 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -17,7 +17,9 @@ M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += ../common/fmcjesdadc1_spi.v
 M_DEPS += ../common/fmcjesdadc1_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_qsys.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
 M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
@@ -32,6 +34,7 @@ M_DEPS += ../../../library/axi_ad9250/axi_ad9250_pnmon.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
 M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
 M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
 M_DEPS += ../../../library/axi_dmac/data_mover.v
@@ -48,6 +51,7 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_mem_asym.v
@@ -63,7 +67,10 @@ M_DEPS += ../../../library/common/up_clock_mon.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 39f2ebcb6..7eafa8a4e 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -17,7 +17,9 @@ M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += ../common/fmcjesdadc1_spi.v
 M_DEPS += ../common/fmcjesdadc1_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a5soc/a5soc_system_qsys.tcl
 M_DEPS += ../../common/a5soc/a5soc_system_assign.tcl
 M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
@@ -32,6 +34,7 @@ M_DEPS += ../../../library/axi_ad9250/axi_ad9250_pnmon.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
 M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
 M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
 M_DEPS += ../../../library/axi_dmac/data_mover.v
@@ -48,6 +51,7 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
 M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
 M_DEPS += ../../../library/common/ad_mem_asym.v
@@ -63,7 +67,10 @@ M_DEPS += ../../../library/common/up_clock_mon.v
 M_DEPS += ../../../library/common/up_delay_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
 M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile
index 8776a9a5e..17d0a9aca 100644
--- a/projects/fmcomms2/a10gx/Makefile
+++ b/projects/fmcomms2/a10gx/Makefile
@@ -16,13 +16,32 @@ M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
 M_DEPS += ../common/fmcomms2_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
 M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/altera/common/ad_cmos_out_core_c5.v
+M_DEPS += ../../../library/altera/common/ad_dcfilter.v
+M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/altera/common/ad_serdes_in_core_c5.v
+M_DEPS += ../../../library/altera/common/ad_serdes_out_core_c5.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_cmos_if.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_constr.sdc
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
 M_DEPS += ../../../library/axi_dmac/2d_transfer.v
 M_DEPS += ../../../library/axi_dmac/address_generator.v
 M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
 M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
 M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
 M_DEPS += ../../../library/axi_dmac/data_mover.v
@@ -39,10 +58,31 @@ M_DEPS += ../../../library/axi_dmac/splitter.v
 M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_addsub.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_iqcor.v
 M_DEPS += ../../../library/common/ad_mem.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_tdd_control.v
 M_DEPS += ../../../library/common/sync_bits.v
 M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
 M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_tdd_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
@@ -57,6 +97,7 @@ M_DEPS += ../../../library/util_upack/util_upack_dmx.v
 M_DEPS += ../../../library/util_upack/util_upack_dsf.v
 M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
 M_DEPS += ../../../library/util_wfifo/util_wfifo.v
+M_DEPS += ../../../library/util_wfifo/util_wfifo_constr.sdc
 M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl
 
 
diff --git a/projects/fmcomms2/zc706pr/Makefile b/projects/fmcomms2/zc706pr/Makefile
index b0a0f920e..c88d9906c 100644
--- a/projects/fmcomms2/zc706pr/Makefile
+++ b/projects/fmcomms2/zc706pr/Makefile
@@ -7,10 +7,13 @@
 
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
 M_DEPS += system_bd.tcl
 M_DEPS += ../zc706/system_constr.xdc
 M_DEPS += ../zc706/system_bd.tcl
 M_DEPS += ../common/prcfg_bd.tcl
+M_DEPS += ../common/prcfg_bb.v
+M_DEPS += ../common/prcfg.xdc
 M_DEPS += ../common/prcfg.v
 M_DEPS += ../common/fmcomms2_bd.tcl
 M_DEPS += ../../scripts/adi_project.tcl
@@ -19,9 +22,22 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/prcfg/qpsk/qpsk_mod.v
+M_DEPS += ../../../library/prcfg/qpsk/qpsk_demod.v
+M_DEPS += ../../../library/prcfg/qpsk/prcfg_dac.v
+M_DEPS += ../../../library/prcfg/qpsk/prcfg_adc.v
+M_DEPS += ../../../library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v
+M_DEPS += ../../../library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v
+M_DEPS += ../../../library/prcfg/qpsk/QPSK_Modulator_Baseband.v
+M_DEPS += ../../../library/prcfg/qpsk/QPSK_Demodulator_Baseband.v
+M_DEPS += ../../../library/prcfg/qpsk/FIR_Interpolation.v
+M_DEPS += ../../../library/prcfg/qpsk/FIR_Decimation.v
 M_DEPS += ../../../library/prcfg/default/prcfg_dac.v
 M_DEPS += ../../../library/prcfg/default/prcfg_adc.v
 M_DEPS += ../../../library/prcfg/common/prcfg_top.v
+M_DEPS += ../../../library/prcfg/bist/prcfg_dac.v
+M_DEPS += ../../../library/prcfg/bist/prcfg_adc.v
+M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile
index 16c02f1aa..545469501 100644
--- a/projects/usb_fx3/zc706/Makefile
+++ b/projects/usb_fx3/zc706/Makefile
@@ -18,6 +18,7 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_intr_monitor/axi_intr_monitor.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
 
@@ -50,6 +51,7 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_intr_monitor clean
 	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/axi_usb_fx3 clean
 
@@ -62,6 +64,7 @@ usb_fx3_zc706.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_intr_monitor
 	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/axi_usb_fx3
 
diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index 90b2cb09d..a7b511e1c 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -11,10 +11,73 @@ endif
 
 export ALT_NIOS_MMU_ENABLED := $(MMU)
 
+M_DEPS += system_top.v
+M_DEPS += system_qsys.tcl
 M_DEPS += system_project.tcl
+M_DEPS += system_constr.sdc
 M_DEPS += ../common/usdrx1_spi.v
+M_DEPS += ../common/usdrx1_qsys.tcl
+M_DEPS += ../../scripts/adi_tquest.tcl
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/altera/sys_gen.tcl
+M_DEPS += ../../common/a5gt/a5gt_system_qsys.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
+M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671.v
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671_channel.v
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671_hw.tcl
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671_if.v
+M_DEPS += ../../../library/axi_ad9671/axi_ad9671_pnmon.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
+M_DEPS += ../../../library/common/ad_axis_inf_rx.v
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_mem.v
+M_DEPS += ../../../library/common/ad_mem_asym.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/scripts/adi_env.tcl
+M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
 
 
 M_ALTERA := quartus_sh --64bit -t 

From 5c8dde848333df7fa874a607bb61dd383e1d25bd Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 12 Dec 2016 14:15:38 +0200
Subject: [PATCH 802/972] util_jesd_gt: this core is obsoleted

The util_jesd_gt core is obsoleted by xilinx/util_adxcvr and altera/avl_adxcvr
---
 library/util_jesd_gt/Makefile            |  57 --
 library/util_jesd_gt/util_jesd_gt.v      | 914 -----------------------
 library/util_jesd_gt/util_jesd_gt_ip.tcl | 188 -----
 3 files changed, 1159 deletions(-)
 delete mode 100644 library/util_jesd_gt/Makefile
 delete mode 100644 library/util_jesd_gt/util_jesd_gt.v
 delete mode 100644 library/util_jesd_gt/util_jesd_gt_ip.tcl

diff --git a/library/util_jesd_gt/Makefile b/library/util_jesd_gt/Makefile
deleted file mode 100644
index 6d40e8177..000000000
--- a/library/util_jesd_gt/Makefile
+++ /dev/null
@@ -1,57 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += util_jesd_gt.v
-M_DEPS += util_jesd_gt_ip.tcl
-
-M_DEPS += ../interfaces/if_gt_pll.xml
-M_DEPS += ../interfaces/if_gt_pll_rtl.xml
-M_DEPS += ../interfaces/if_gt_qpll.xml
-M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
-M_DEPS += ../interfaces/if_gt_rx.xml
-M_DEPS += ../interfaces/if_gt_rx_rtl.xml
-M_DEPS += ../interfaces/if_gt_tx.xml
-M_DEPS += ../interfaces/if_gt_tx_rtl.xml
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += component.xml
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.ip_user_files
-M_FLIST += *.srcs
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-
-
-
-.PHONY: all dep clean clean-all
-all: dep util_jesd_gt.xpr
-
-
-clean:clean-all
-
-
-clean-all:
-	rm -rf $(M_FLIST)
-
-
-util_jesd_gt.xpr: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) util_jesd_gt_ip.tcl  >> util_jesd_gt_ip.log 2>&1
-
-dep:
-	make -C ../interfaces
-####################################################################################
-####################################################################################
diff --git a/library/util_jesd_gt/util_jesd_gt.v b/library/util_jesd_gt/util_jesd_gt.v
deleted file mode 100644
index 7d74d2045..000000000
--- a/library/util_jesd_gt/util_jesd_gt.v
+++ /dev/null
@@ -1,914 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-// 
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//    
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module util_jesd_gt #(
-
-  parameter   integer QPLL0_ENABLE = 1,
-  parameter   integer QPLL1_ENABLE = 1,
-  parameter   integer QPLL_TX_OR_RX_N = 1,
-  parameter   integer CPLL_TX_OR_RX_N = 0,
-  parameter   integer NUM_OF_LANES = 8,
-  parameter   integer RX_ENABLE = 1,
-  parameter   integer RX_NUM_OF_LANES = 8,
-  parameter   integer TX_ENABLE = 1,
-  parameter   integer TX_NUM_OF_LANES = 8)
-
- (
-
-  // pll clocks & resets
-
-  input                                       qpll_ref_clk,
-  input                                       cpll_ref_clk,
-
-  output                                      qpll0_rst,
-  output                                      qpll0_ref_clk_in,
-  output                                      qpll1_rst,
-  output                                      qpll1_ref_clk_in,
-
-  output                                      cpll_rst_m_0,
-  output                                      cpll_ref_clk_in_0,
-  output                                      cpll_rst_m_1,
-  output                                      cpll_ref_clk_in_1,
-  output                                      cpll_rst_m_2,
-  output                                      cpll_ref_clk_in_2,
-  output                                      cpll_rst_m_3,
-  output                                      cpll_ref_clk_in_3,
-  output                                      cpll_rst_m_4,
-  output                                      cpll_ref_clk_in_4,
-  output                                      cpll_rst_m_5,
-  output                                      cpll_ref_clk_in_5,
-  output                                      cpll_rst_m_6,
-  output                                      cpll_ref_clk_in_6,
-  output                                      cpll_rst_m_7,
-  output                                      cpll_ref_clk_in_7,
-
-  // channel interface (rx)
-  
-  input   [((RX_NUM_OF_LANES* 1)-1):0]        rx_p,
-  input   [((RX_NUM_OF_LANES* 1)-1):0]        rx_n,
-  input                                       rx_sysref,
-  output                                      rx_sync,
-
-  output                                      rx_out_clk,
-  input                                       rx_clk,
-  output                                      rx_rst,
-  output                                      rx_sof,
-  output  [((RX_NUM_OF_LANES*32)-1):0]        rx_data,
-
-  output                                      rx_ip_rst,
-  output                                      rx_ip_rst_done,
-  output                                      rx_ip_sysref,
-  input                                       rx_ip_sync,
-  input   [  3:0]                             rx_ip_sof,
-  input   [((RX_NUM_OF_LANES*32)-1):0]        rx_ip_data,
-
-  output                                      rx_0_p,
-  output                                      rx_0_n,
-  input                                       rx_rst_0,
-  output                                      rx_rst_m_0,
-  input                                       rx_pll_rst_0,
-  input                                       rx_gt_rst_0,
-  output                                      rx_gt_rst_m_0,
-  input                                       rx_pll_locked_0,
-  output                                      rx_pll_locked_m_0,
-  input                                       rx_user_ready_0,
-  output                                      rx_user_ready_m_0,
-  input                                       rx_rst_done_0,
-  output                                      rx_rst_done_m_0,
-  input                                       rx_out_clk_0,
-  output                                      rx_clk_0,
-  output                                      rx_sysref_0,
-  input                                       rx_sync_0,
-  input                                       rx_sof_0,
-  input   [31:0]                              rx_data_0,
-  input                                       rx_ip_rst_0,
-  output  [ 3:0]                              rx_ip_sof_0,
-  output  [31:0]                              rx_ip_data_0,
-  input                                       rx_ip_sysref_0,
-  output                                      rx_ip_sync_0,
-  input                                       rx_ip_rst_done_0,
-
-  output                                      rx_1_p,
-  output                                      rx_1_n,
-  input                                       rx_rst_1,
-  output                                      rx_rst_m_1,
-  input                                       rx_pll_rst_1,
-  input                                       rx_gt_rst_1,
-  output                                      rx_gt_rst_m_1,
-  input                                       rx_pll_locked_1,
-  output                                      rx_pll_locked_m_1,
-  input                                       rx_user_ready_1,
-  output                                      rx_user_ready_m_1,
-  input                                       rx_rst_done_1,
-  output                                      rx_rst_done_m_1,
-  input                                       rx_out_clk_1,
-  output                                      rx_clk_1,
-  output                                      rx_sysref_1,
-  input                                       rx_sync_1,
-  input                                       rx_sof_1,
-  input   [31:0]                              rx_data_1,
-  input                                       rx_ip_rst_1,
-  output  [ 3:0]                              rx_ip_sof_1,
-  output  [31:0]                              rx_ip_data_1,
-  input                                       rx_ip_sysref_1,
-  output                                      rx_ip_sync_1,
-  input                                       rx_ip_rst_done_1,
-
-  output                                      rx_2_p,
-  output                                      rx_2_n,
-  input                                       rx_rst_2,
-  output                                      rx_rst_m_2,
-  input                                       rx_pll_rst_2,
-  input                                       rx_gt_rst_2,
-  output                                      rx_gt_rst_m_2,
-  input                                       rx_pll_locked_2,
-  output                                      rx_pll_locked_m_2,
-  input                                       rx_user_ready_2,
-  output                                      rx_user_ready_m_2,
-  input                                       rx_rst_done_2,
-  output                                      rx_rst_done_m_2,
-  input                                       rx_out_clk_2,
-  output                                      rx_clk_2,
-  output                                      rx_sysref_2,
-  input                                       rx_sync_2,
-  input                                       rx_sof_2,
-  input   [31:0]                              rx_data_2,
-  input                                       rx_ip_rst_2,
-  output  [ 3:0]                              rx_ip_sof_2,
-  output  [31:0]                              rx_ip_data_2,
-  input                                       rx_ip_sysref_2,
-  output                                      rx_ip_sync_2,
-  input                                       rx_ip_rst_done_2,
-
-  output                                      rx_3_p,
-  output                                      rx_3_n,
-  input                                       rx_rst_3,
-  output                                      rx_rst_m_3,
-  input                                       rx_pll_rst_3,
-  input                                       rx_gt_rst_3,
-  output                                      rx_gt_rst_m_3,
-  input                                       rx_pll_locked_3,
-  output                                      rx_pll_locked_m_3,
-  input                                       rx_user_ready_3,
-  output                                      rx_user_ready_m_3,
-  input                                       rx_rst_done_3,
-  output                                      rx_rst_done_m_3,
-  input                                       rx_out_clk_3,
-  output                                      rx_clk_3,
-  output                                      rx_sysref_3,
-  input                                       rx_sync_3,
-  input                                       rx_sof_3,
-  input   [31:0]                              rx_data_3,
-  input                                       rx_ip_rst_3,
-  output  [ 3:0]                              rx_ip_sof_3,
-  output  [31:0]                              rx_ip_data_3,
-  input                                       rx_ip_sysref_3,
-  output                                      rx_ip_sync_3,
-  input                                       rx_ip_rst_done_3,
-
-  output                                      rx_4_p,
-  output                                      rx_4_n,
-  input                                       rx_rst_4,
-  output                                      rx_rst_m_4,
-  input                                       rx_pll_rst_4,
-  input                                       rx_gt_rst_4,
-  output                                      rx_gt_rst_m_4,
-  input                                       rx_pll_locked_4,
-  output                                      rx_pll_locked_m_4,
-  input                                       rx_user_ready_4,
-  output                                      rx_user_ready_m_4,
-  input                                       rx_rst_done_4,
-  output                                      rx_rst_done_m_4,
-  input                                       rx_out_clk_4,
-  output                                      rx_clk_4,
-  output                                      rx_sysref_4,
-  input                                       rx_sync_4,
-  input                                       rx_sof_4,
-  input   [31:0]                              rx_data_4,
-  input                                       rx_ip_rst_4,
-  output  [ 3:0]                              rx_ip_sof_4,
-  output  [31:0]                              rx_ip_data_4,
-  input                                       rx_ip_sysref_4,
-  output                                      rx_ip_sync_4,
-  input                                       rx_ip_rst_done_4,
-
-  output                                      rx_5_p,
-  output                                      rx_5_n,
-  input                                       rx_rst_5,
-  output                                      rx_rst_m_5,
-  input                                       rx_pll_rst_5,
-  input                                       rx_gt_rst_5,
-  output                                      rx_gt_rst_m_5,
-  input                                       rx_pll_locked_5,
-  output                                      rx_pll_locked_m_5,
-  input                                       rx_user_ready_5,
-  output                                      rx_user_ready_m_5,
-  input                                       rx_rst_done_5,
-  output                                      rx_rst_done_m_5,
-  input                                       rx_out_clk_5,
-  output                                      rx_clk_5,
-  output                                      rx_sysref_5,
-  input                                       rx_sync_5,
-  input                                       rx_sof_5,
-  input   [31:0]                              rx_data_5,
-  input                                       rx_ip_rst_5,
-  output  [ 3:0]                              rx_ip_sof_5,
-  output  [31:0]                              rx_ip_data_5,
-  input                                       rx_ip_sysref_5,
-  output                                      rx_ip_sync_5,
-  input                                       rx_ip_rst_done_5,
-
-  output                                      rx_6_p,
-  output                                      rx_6_n,
-  input                                       rx_rst_6,
-  output                                      rx_rst_m_6,
-  input                                       rx_pll_rst_6,
-  input                                       rx_gt_rst_6,
-  output                                      rx_gt_rst_m_6,
-  input                                       rx_pll_locked_6,
-  output                                      rx_pll_locked_m_6,
-  input                                       rx_user_ready_6,
-  output                                      rx_user_ready_m_6,
-  input                                       rx_rst_done_6,
-  output                                      rx_rst_done_m_6,
-  input                                       rx_out_clk_6,
-  output                                      rx_clk_6,
-  output                                      rx_sysref_6,
-  input                                       rx_sync_6,
-  input                                       rx_sof_6,
-  input   [31:0]                              rx_data_6,
-  input                                       rx_ip_rst_6,
-  output  [ 3:0]                              rx_ip_sof_6,
-  output  [31:0]                              rx_ip_data_6,
-  input                                       rx_ip_sysref_6,
-  output                                      rx_ip_sync_6,
-  input                                       rx_ip_rst_done_6,
-
-  output                                      rx_7_p,
-  output                                      rx_7_n,
-  input                                       rx_rst_7,
-  output                                      rx_rst_m_7,
-  input                                       rx_pll_rst_7,
-  input                                       rx_gt_rst_7,
-  output                                      rx_gt_rst_m_7,
-  input                                       rx_pll_locked_7,
-  output                                      rx_pll_locked_m_7,
-  input                                       rx_user_ready_7,
-  output                                      rx_user_ready_m_7,
-  input                                       rx_rst_done_7,
-  output                                      rx_rst_done_m_7,
-  input                                       rx_out_clk_7,
-  output                                      rx_clk_7,
-  output                                      rx_sysref_7,
-  input                                       rx_sync_7,
-  input                                       rx_sof_7,
-  input   [31:0]                              rx_data_7,
-  input                                       rx_ip_rst_7,
-  output  [ 3:0]                              rx_ip_sof_7,
-  output  [31:0]                              rx_ip_data_7,
-  input                                       rx_ip_sysref_7,
-  output                                      rx_ip_sync_7,
-  input                                       rx_ip_rst_done_7,
-
-  // channel interface (tx)
-
-  output  [((TX_NUM_OF_LANES* 1)-1):0]        tx_p,
-  output  [((TX_NUM_OF_LANES* 1)-1):0]        tx_n,
-  input                                       tx_sysref,
-  input                                       tx_sync,
-
-  output                                      tx_out_clk,
-  input                                       tx_clk,
-  output                                      tx_rst,
-  input   [((TX_NUM_OF_LANES*32)-1):0]        tx_data,
-
-  output                                      tx_ip_rst,
-  output                                      tx_ip_rst_done,
-  output                                      tx_ip_sysref,
-  output                                      tx_ip_sync,
-  output  [((TX_NUM_OF_LANES*32)-1):0]        tx_ip_data,
-
-  input                                       tx_0_p,
-  input                                       tx_0_n,
-  input                                       tx_rst_0,
-  output                                      tx_rst_m_0,
-  input                                       tx_pll_rst_0,
-  input                                       tx_gt_rst_0,
-  output                                      tx_gt_rst_m_0,
-  input                                       tx_pll_locked_0,
-  output                                      tx_pll_locked_m_0,
-  input                                       tx_user_ready_0,
-  output                                      tx_user_ready_m_0,
-  input                                       tx_rst_done_0,
-  output                                      tx_rst_done_m_0,
-  input                                       tx_out_clk_0,
-  output                                      tx_clk_0,
-  output                                      tx_sysref_0,
-  output                                      tx_sync_0,
-  output  [31:0]                              tx_data_0,
-  input                                       tx_ip_rst_0,
-  input   [31:0]                              tx_ip_data_0,
-  input                                       tx_ip_sysref_0,
-  input                                       tx_ip_sync_0,
-  input                                       tx_ip_rst_done_0,
-
-  input                                       tx_1_p,
-  input                                       tx_1_n,
-  input                                       tx_rst_1,
-  output                                      tx_rst_m_1,
-  input                                       tx_pll_rst_1,
-  input                                       tx_gt_rst_1,
-  output                                      tx_gt_rst_m_1,
-  input                                       tx_pll_locked_1,
-  output                                      tx_pll_locked_m_1,
-  input                                       tx_user_ready_1,
-  output                                      tx_user_ready_m_1,
-  input                                       tx_rst_done_1,
-  output                                      tx_rst_done_m_1,
-  input                                       tx_out_clk_1,
-  output                                      tx_clk_1,
-  output                                      tx_sysref_1,
-  output                                      tx_sync_1,
-  output  [31:0]                              tx_data_1,
-  input                                       tx_ip_rst_1,
-  input   [31:0]                              tx_ip_data_1,
-  input                                       tx_ip_sysref_1,
-  input                                       tx_ip_sync_1,
-  input                                       tx_ip_rst_done_1,
-
-  input                                       tx_2_p,
-  input                                       tx_2_n,
-  input                                       tx_rst_2,
-  output                                      tx_rst_m_2,
-  input                                       tx_pll_rst_2,
-  input                                       tx_gt_rst_2,
-  output                                      tx_gt_rst_m_2,
-  input                                       tx_pll_locked_2,
-  output                                      tx_pll_locked_m_2,
-  input                                       tx_user_ready_2,
-  output                                      tx_user_ready_m_2,
-  input                                       tx_rst_done_2,
-  output                                      tx_rst_done_m_2,
-  input                                       tx_out_clk_2,
-  output                                      tx_clk_2,
-  output                                      tx_sysref_2,
-  output                                      tx_sync_2,
-  output  [31:0]                              tx_data_2,
-  input                                       tx_ip_rst_2,
-  input   [31:0]                              tx_ip_data_2,
-  input                                       tx_ip_sysref_2,
-  input                                       tx_ip_sync_2,
-  input                                       tx_ip_rst_done_2,
-
-  input                                       tx_3_p,
-  input                                       tx_3_n,
-  input                                       tx_rst_3,
-  output                                      tx_rst_m_3,
-  input                                       tx_pll_rst_3,
-  input                                       tx_gt_rst_3,
-  output                                      tx_gt_rst_m_3,
-  input                                       tx_pll_locked_3,
-  output                                      tx_pll_locked_m_3,
-  input                                       tx_user_ready_3,
-  output                                      tx_user_ready_m_3,
-  input                                       tx_rst_done_3,
-  output                                      tx_rst_done_m_3,
-  input                                       tx_out_clk_3,
-  output                                      tx_clk_3,
-  output                                      tx_sysref_3,
-  output                                      tx_sync_3,
-  output  [31:0]                              tx_data_3,
-  input                                       tx_ip_rst_3,
-  input   [31:0]                              tx_ip_data_3,
-  input                                       tx_ip_sysref_3,
-  input                                       tx_ip_sync_3,
-  input                                       tx_ip_rst_done_3,
-
-  input                                       tx_4_p,
-  input                                       tx_4_n,
-  input                                       tx_rst_4,
-  output                                      tx_rst_m_4,
-  input                                       tx_pll_rst_4,
-  input                                       tx_gt_rst_4,
-  output                                      tx_gt_rst_m_4,
-  input                                       tx_pll_locked_4,
-  output                                      tx_pll_locked_m_4,
-  input                                       tx_user_ready_4,
-  output                                      tx_user_ready_m_4,
-  input                                       tx_rst_done_4,
-  output                                      tx_rst_done_m_4,
-  input                                       tx_out_clk_4,
-  output                                      tx_clk_4,
-  output                                      tx_sysref_4,
-  output                                      tx_sync_4,
-  output  [31:0]                              tx_data_4,
-  input                                       tx_ip_rst_4,
-  input   [31:0]                              tx_ip_data_4,
-  input                                       tx_ip_sysref_4,
-  input                                       tx_ip_sync_4,
-  input                                       tx_ip_rst_done_4,
-
-  input                                       tx_5_p,
-  input                                       tx_5_n,
-  input                                       tx_rst_5,
-  output                                      tx_rst_m_5,
-  input                                       tx_pll_rst_5,
-  input                                       tx_gt_rst_5,
-  output                                      tx_gt_rst_m_5,
-  input                                       tx_pll_locked_5,
-  output                                      tx_pll_locked_m_5,
-  input                                       tx_user_ready_5,
-  output                                      tx_user_ready_m_5,
-  input                                       tx_rst_done_5,
-  output                                      tx_rst_done_m_5,
-  input                                       tx_out_clk_5,
-  output                                      tx_clk_5,
-  output                                      tx_sysref_5,
-  output                                      tx_sync_5,
-  output  [31:0]                              tx_data_5,
-  input                                       tx_ip_rst_5,
-  input   [31:0]                              tx_ip_data_5,
-  input                                       tx_ip_sysref_5,
-  input                                       tx_ip_sync_5,
-  input                                       tx_ip_rst_done_5,
-
-  input                                       tx_6_p,
-  input                                       tx_6_n,
-  input                                       tx_rst_6,
-  output                                      tx_rst_m_6,
-  input                                       tx_pll_rst_6,
-  input                                       tx_gt_rst_6,
-  output                                      tx_gt_rst_m_6,
-  input                                       tx_pll_locked_6,
-  output                                      tx_pll_locked_m_6,
-  input                                       tx_user_ready_6,
-  output                                      tx_user_ready_m_6,
-  input                                       tx_rst_done_6,
-  output                                      tx_rst_done_m_6,
-  input                                       tx_out_clk_6,
-  output                                      tx_clk_6,
-  output                                      tx_sysref_6,
-  output                                      tx_sync_6,
-  output  [31:0]                              tx_data_6,
-  input                                       tx_ip_rst_6,
-  input   [31:0]                              tx_ip_data_6,
-  input                                       tx_ip_sysref_6,
-  input                                       tx_ip_sync_6,
-  input                                       tx_ip_rst_done_6,
-
-  input                                       tx_7_p,
-  input                                       tx_7_n,
-  input                                       tx_rst_7,
-  output                                      tx_rst_m_7,
-  input                                       tx_pll_rst_7,
-  input                                       tx_gt_rst_7,
-  output                                      tx_gt_rst_m_7,
-  input                                       tx_pll_locked_7,
-  output                                      tx_pll_locked_m_7,
-  input                                       tx_user_ready_7,
-  output                                      tx_user_ready_m_7,
-  input                                       tx_rst_done_7,
-  output                                      tx_rst_done_m_7,
-  input                                       tx_out_clk_7,
-  output                                      tx_clk_7,
-  output                                      tx_sysref_7,
-  output                                      tx_sync_7,
-  output  [31:0]                              tx_data_7,
-  input                                       tx_ip_rst_7,
-  input   [31:0]                              tx_ip_data_7,
-  input                                       tx_ip_sysref_7,
-  input                                       tx_ip_sync_7,
-  input                                       tx_ip_rst_done_7);
-
-  // internal signals
-
-  wire    [(( 1*8)-1):0]                      rx_all_p;
-  wire    [(( 1*8)-1):0]                      rx_all_n;
-  wire    [(( 1*8)-1):0]                      rx_pll_locked_all;
-  wire    [(( 1*8)-1):0]                      rx_user_ready_all;
-  wire    [(( 1*8)-1):0]                      rx_rst_done_all;
-  wire    [(( 1*8)-1):0]                      rx_ip_rst_done_all;
-  wire    [((32*8)-1):0]                      rx_data_all;
-  wire    [((32*8)-1):0]                      rx_ip_data_all;
-  wire    [(( 1*8)-1):0]                      tx_all_p;
-  wire    [(( 1*8)-1):0]                      tx_all_n;
-  wire    [(( 1*8)-1):0]                      tx_pll_locked_all;
-  wire    [(( 1*8)-1):0]                      tx_user_ready_all;
-  wire    [(( 1*8)-1):0]                      tx_rst_done_all;
-  wire    [(( 1*8)-1):0]                      tx_ip_rst_done_all;
-  wire    [((32*8)-1):0]                      tx_ip_data_all;
-  wire    [((32*8)-1):0]                      tx_data_all;
-
-  // pll clocks & resets
-
-  assign qpll0_rst = (QPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign qpll0_ref_clk_in = qpll_ref_clk;
-  assign qpll1_rst = (QPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign qpll1_ref_clk_in = qpll_ref_clk;
-  assign cpll_rst_m_0 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign cpll_ref_clk_in_0 = cpll_ref_clk;
-  assign cpll_rst_m_1 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign cpll_ref_clk_in_1 = cpll_ref_clk;
-  assign cpll_rst_m_2 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign cpll_ref_clk_in_2 = cpll_ref_clk;
-  assign cpll_rst_m_3 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign cpll_ref_clk_in_3 = cpll_ref_clk;
-  assign cpll_rst_m_4 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign cpll_ref_clk_in_4 = cpll_ref_clk;
-  assign cpll_rst_m_5 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign cpll_ref_clk_in_5 = cpll_ref_clk;
-  assign cpll_rst_m_6 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign cpll_ref_clk_in_6 = cpll_ref_clk;
-  assign cpll_rst_m_7 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0;
-  assign cpll_ref_clk_in_7 = cpll_ref_clk;
-
-  // channel interface (rx)
-
-  generate
-  if (RX_NUM_OF_LANES < 8) begin
-  assign rx_all_p[((8* 1)-1):(RX_NUM_OF_LANES* 1)] = 'd0;
-  assign rx_all_n[((8* 1)-1):(RX_NUM_OF_LANES* 1)] = 'd0;
-  end
-  endgenerate
-
-  assign rx_all_p[((RX_NUM_OF_LANES* 1)-1):0] = rx_p;
-  assign rx_all_n[((RX_NUM_OF_LANES* 1)-1):0] = rx_n;
-
-  assign rx_pll_locked_all[0] = (RX_NUM_OF_LANES >= 1) ? rx_pll_locked_0 : 1'b1;
-  assign rx_user_ready_all[0] = (RX_NUM_OF_LANES >= 1) ? rx_user_ready_0 : 1'b1;
-  assign rx_rst_done_all[0] = (RX_NUM_OF_LANES >= 1) ? rx_rst_done_0 : 1'b1;
-  assign rx_ip_rst_done_all[0] = (RX_NUM_OF_LANES >= 1) ? rx_ip_rst_done_0 : 1'b1;
-  assign rx_data_all[((32*0)+31):(32*0)] = rx_data_0;
-
-  assign rx_pll_locked_all[1] = (RX_NUM_OF_LANES >= 2) ? rx_pll_locked_1 : 1'b1;
-  assign rx_user_ready_all[1] = (RX_NUM_OF_LANES >= 2) ? rx_user_ready_1 : 1'b1;
-  assign rx_rst_done_all[1] = (RX_NUM_OF_LANES >= 2) ? rx_rst_done_1 : 1'b1;
-  assign rx_ip_rst_done_all[1] = (RX_NUM_OF_LANES >= 2) ? rx_ip_rst_done_1 : 1'b1;
-  assign rx_data_all[((32*1)+31):(32*1)] = rx_data_1;
-
-  assign rx_pll_locked_all[2] = (RX_NUM_OF_LANES >= 3) ? rx_pll_locked_2 : 1'b1;
-  assign rx_user_ready_all[2] = (RX_NUM_OF_LANES >= 3) ? rx_user_ready_2 : 1'b1;
-  assign rx_rst_done_all[2] = (RX_NUM_OF_LANES >= 3) ? rx_rst_done_2 : 1'b1;
-  assign rx_ip_rst_done_all[2] = (RX_NUM_OF_LANES >= 3) ? rx_ip_rst_done_2 : 1'b1;
-  assign rx_data_all[((32*2)+31):(32*2)] = rx_data_2;
-
-  assign rx_pll_locked_all[3] = (RX_NUM_OF_LANES >= 4) ? rx_pll_locked_3 : 1'b1;
-  assign rx_user_ready_all[3] = (RX_NUM_OF_LANES >= 4) ? rx_user_ready_3 : 1'b1;
-  assign rx_rst_done_all[3] = (RX_NUM_OF_LANES >= 4) ? rx_rst_done_3 : 1'b1;
-  assign rx_ip_rst_done_all[3] = (RX_NUM_OF_LANES >= 4) ? rx_ip_rst_done_3 : 1'b1;
-  assign rx_data_all[((32*3)+31):(32*3)] = rx_data_3;
-
-  assign rx_pll_locked_all[4] = (RX_NUM_OF_LANES >= 5) ? rx_pll_locked_4 : 1'b1;
-  assign rx_user_ready_all[4] = (RX_NUM_OF_LANES >= 5) ? rx_user_ready_4 : 1'b1;
-  assign rx_rst_done_all[4] = (RX_NUM_OF_LANES >= 5) ? rx_rst_done_4 : 1'b1;
-  assign rx_ip_rst_done_all[4] = (RX_NUM_OF_LANES >= 5) ? rx_ip_rst_done_4 : 1'b1;
-  assign rx_data_all[((32*4)+31):(32*4)] = rx_data_4;
-
-  assign rx_pll_locked_all[5] = (RX_NUM_OF_LANES >= 6) ? rx_pll_locked_5 : 1'b1;
-  assign rx_user_ready_all[5] = (RX_NUM_OF_LANES >= 6) ? rx_user_ready_5 : 1'b1;
-  assign rx_rst_done_all[5] = (RX_NUM_OF_LANES >= 6) ? rx_rst_done_5 : 1'b1;
-  assign rx_ip_rst_done_all[5] = (RX_NUM_OF_LANES >= 6) ? rx_ip_rst_done_5 : 1'b1;
-  assign rx_data_all[((32*5)+31):(32*5)] = rx_data_5;
-
-  assign rx_pll_locked_all[6] = (RX_NUM_OF_LANES >= 7) ? rx_pll_locked_6 : 1'b1;
-  assign rx_user_ready_all[6] = (RX_NUM_OF_LANES >= 7) ? rx_user_ready_6 : 1'b1;
-  assign rx_rst_done_all[6] = (RX_NUM_OF_LANES >= 7) ? rx_rst_done_6 : 1'b1;
-  assign rx_ip_rst_done_all[6] = (RX_NUM_OF_LANES >= 7) ? rx_ip_rst_done_6 : 1'b1;
-  assign rx_data_all[((32*6)+31):(32*6)] = rx_data_6;
-
-  assign rx_pll_locked_all[7] = (RX_NUM_OF_LANES >= 8) ? rx_pll_locked_7 : 1'b1;
-  assign rx_user_ready_all[7] = (RX_NUM_OF_LANES >= 8) ? rx_user_ready_7 : 1'b1;
-  assign rx_rst_done_all[7] = (RX_NUM_OF_LANES >= 8) ? rx_rst_done_7 : 1'b1;
-  assign rx_ip_rst_done_all[7] = (RX_NUM_OF_LANES >= 8) ? rx_ip_rst_done_7 : 1'b1;
-  assign rx_data_all[((32*7)+31):(32*7)] = rx_data_7;
-
-  generate
-  if (RX_NUM_OF_LANES < 8) begin
-  assign rx_ip_data_all[((8*32)-1):(RX_NUM_OF_LANES*32)] = 'd0;
-  end
-  endgenerate
-
-  assign rx_ip_data_all[((RX_NUM_OF_LANES*32)-1):0] = rx_ip_data;
-
-  assign rx_sync = rx_sync_0;
-
-  assign rx_out_clk = rx_out_clk_0;
-  assign rx_rst = rx_rst_0;
-  assign rx_sof = rx_sof_0;
-  assign rx_data = rx_data_all[((RX_NUM_OF_LANES*32)-1):0];
-
-  assign rx_ip_rst = rx_ip_rst_0;
-  assign rx_ip_rst_done = & rx_ip_rst_done_all;
-  assign rx_ip_sysref = rx_ip_sysref_0;
-
-  assign rx_0_p = rx_all_p[0];
-  assign rx_0_n = rx_all_n[0];
-  assign rx_rst_m_0 = rx_rst_0;
-  assign rx_gt_rst_m_0 = rx_gt_rst_0;
-  assign rx_pll_locked_m_0 = & rx_pll_locked_all;
-  assign rx_user_ready_m_0 = & rx_user_ready_all;
-  assign rx_rst_done_m_0 = & rx_rst_done_all;
-  assign rx_clk_0 = rx_clk;
-  assign rx_sysref_0 = rx_sysref;
-  assign rx_ip_sof_0 = rx_ip_sof;
-  assign rx_ip_data_0 = rx_ip_data_all[((32*0)+31):(32*0)];
-  assign rx_ip_sync_0 = rx_ip_sync;
-
-  assign rx_1_p = rx_all_p[1];
-  assign rx_1_n = rx_all_n[1];
-  assign rx_rst_m_1 = rx_rst_0;
-  assign rx_gt_rst_m_1 = rx_gt_rst_0;
-  assign rx_pll_locked_m_1 = & rx_pll_locked_all;
-  assign rx_user_ready_m_1 = & rx_user_ready_all;
-  assign rx_rst_done_m_1 = & rx_rst_done_all;
-  assign rx_clk_1 = rx_clk;
-  assign rx_sysref_1 = rx_sysref;
-  assign rx_ip_sof_1 = rx_ip_sof;
-  assign rx_ip_data_1 = rx_ip_data_all[((32*1)+31):(32*1)];
-  assign rx_ip_sync_1 = rx_ip_sync;
-
-  assign rx_2_p = rx_all_p[2];
-  assign rx_2_n = rx_all_n[2];
-  assign rx_rst_m_2 = rx_rst_0;
-  assign rx_gt_rst_m_2 = rx_gt_rst_0;
-  assign rx_pll_locked_m_2 = & rx_pll_locked_all;
-  assign rx_user_ready_m_2 = & rx_user_ready_all;
-  assign rx_rst_done_m_2 = & rx_rst_done_all;
-  assign rx_clk_2 = rx_clk;
-  assign rx_sysref_2 = rx_sysref;
-  assign rx_ip_sof_2 = rx_ip_sof;
-  assign rx_ip_data_2 = rx_ip_data_all[((32*2)+31):(32*2)];
-  assign rx_ip_sync_2 = rx_ip_sync;
-
-  assign rx_3_p = rx_all_p[3];
-  assign rx_3_n = rx_all_n[3];
-  assign rx_rst_m_3 = rx_rst_0;
-  assign rx_gt_rst_m_3 = rx_gt_rst_0;
-  assign rx_pll_locked_m_3 = & rx_pll_locked_all;
-  assign rx_user_ready_m_3 = & rx_user_ready_all;
-  assign rx_rst_done_m_3 = & rx_rst_done_all;
-  assign rx_clk_3 = rx_clk;
-  assign rx_sysref_3 = rx_sysref;
-  assign rx_ip_sof_3 = rx_ip_sof;
-  assign rx_ip_data_3 = rx_ip_data_all[((32*3)+31):(32*3)];
-  assign rx_ip_sync_3 = rx_ip_sync;
-
-  assign rx_4_p = rx_all_p[4];
-  assign rx_4_n = rx_all_n[4];
-  assign rx_rst_m_4 = rx_rst_0;
-  assign rx_gt_rst_m_4 = rx_gt_rst_0;
-  assign rx_pll_locked_m_4 = & rx_pll_locked_all;
-  assign rx_user_ready_m_4 = & rx_user_ready_all;
-  assign rx_rst_done_m_4 = & rx_rst_done_all;
-  assign rx_clk_4 = rx_clk;
-  assign rx_sysref_4 = rx_sysref;
-  assign rx_ip_sof_4 = rx_ip_sof;
-  assign rx_ip_data_4 = rx_ip_data_all[((32*4)+31):(32*4)];
-  assign rx_ip_sync_4 = rx_ip_sync;
-
-  assign rx_5_p = rx_all_p[5];
-  assign rx_5_n = rx_all_n[5];
-  assign rx_rst_m_5 = rx_rst_0;
-  assign rx_gt_rst_m_5 = rx_gt_rst_0;
-  assign rx_pll_locked_m_5 = & rx_pll_locked_all;
-  assign rx_user_ready_m_5 = & rx_user_ready_all;
-  assign rx_rst_done_m_5 = & rx_rst_done_all;
-  assign rx_clk_5 = rx_clk;
-  assign rx_sysref_5 = rx_sysref;
-  assign rx_ip_sof_5 = rx_ip_sof;
-  assign rx_ip_data_5 = rx_ip_data_all[((32*5)+31):(32*5)];
-  assign rx_ip_sync_5 = rx_ip_sync;
-
-  assign rx_6_p = rx_all_p[6];
-  assign rx_6_n = rx_all_n[6];
-  assign rx_rst_m_6 = rx_rst_0;
-  assign rx_gt_rst_m_6 = rx_gt_rst_0;
-  assign rx_pll_locked_m_6 = & rx_pll_locked_all;
-  assign rx_user_ready_m_6 = & rx_user_ready_all;
-  assign rx_rst_done_m_6 = & rx_rst_done_all;
-  assign rx_clk_6 = rx_clk;
-  assign rx_sysref_6 = rx_sysref;
-  assign rx_ip_sof_6 = rx_ip_sof;
-  assign rx_ip_data_6 = rx_ip_data_all[((32*6)+31):(32*6)];
-  assign rx_ip_sync_6 = rx_ip_sync;
-
-  assign rx_7_p = rx_all_p[7];
-  assign rx_7_n = rx_all_n[7];
-  assign rx_rst_m_7 = rx_rst_0;
-  assign rx_gt_rst_m_7 = rx_gt_rst_0;
-  assign rx_pll_locked_m_7 = & rx_pll_locked_all;
-  assign rx_user_ready_m_7 = & rx_user_ready_all;
-  assign rx_rst_done_m_7 = & rx_rst_done_all;
-  assign rx_clk_7 = rx_clk;
-  assign rx_sysref_7 = rx_sysref;
-  assign rx_ip_sof_7 = rx_ip_sof;
-  assign rx_ip_data_7 = rx_ip_data_all[((32*7)+31):(32*7)];
-  assign rx_ip_sync_7 = rx_ip_sync;
-
-
-  // channel interface (tx)
-
-  assign tx_all_p[0] = tx_0_p;
-  assign tx_all_n[0] = tx_0_n;
-  assign tx_pll_locked_all[0] = (TX_NUM_OF_LANES >= 1) ? tx_pll_locked_0 : 1'b1;
-  assign tx_user_ready_all[0] = (TX_NUM_OF_LANES >= 1) ? tx_user_ready_0 : 1'b1;
-  assign tx_rst_done_all[0] = (TX_NUM_OF_LANES >= 1) ? tx_rst_done_0 : 1'b1;
-  assign tx_ip_rst_done_all[0] = (TX_NUM_OF_LANES >= 1) ? tx_ip_rst_done_0 : 1'b1;
-  assign tx_ip_data_all[((32*0)+31):(32*0)] = tx_ip_data_0;
-
-  assign tx_all_p[1] = tx_1_p;
-  assign tx_all_n[1] = tx_1_n;
-  assign tx_pll_locked_all[1] = (TX_NUM_OF_LANES >= 2) ? tx_pll_locked_1 : 1'b1;
-  assign tx_user_ready_all[1] = (TX_NUM_OF_LANES >= 2) ? tx_user_ready_1 : 1'b1;
-  assign tx_rst_done_all[1] = (TX_NUM_OF_LANES >= 2) ? tx_rst_done_1 : 1'b1;
-  assign tx_ip_rst_done_all[1] = (TX_NUM_OF_LANES >= 2) ? tx_ip_rst_done_1 : 1'b1;
-  assign tx_ip_data_all[((32*1)+31):(32*1)] = tx_ip_data_1;
-
-  assign tx_all_p[2] = tx_2_p;
-  assign tx_all_n[2] = tx_2_n;
-  assign tx_pll_locked_all[2] = (TX_NUM_OF_LANES >= 3) ? tx_pll_locked_2 : 1'b1;
-  assign tx_user_ready_all[2] = (TX_NUM_OF_LANES >= 3) ? tx_user_ready_2 : 1'b1;
-  assign tx_rst_done_all[2] = (TX_NUM_OF_LANES >= 3) ? tx_rst_done_2 : 1'b1;
-  assign tx_ip_rst_done_all[2] = (TX_NUM_OF_LANES >= 3) ? tx_ip_rst_done_2 : 1'b1;
-  assign tx_ip_data_all[((32*2)+31):(32*2)] = tx_ip_data_2;
-
-  assign tx_all_p[3] = tx_3_p;
-  assign tx_all_n[3] = tx_3_n;
-  assign tx_pll_locked_all[3] = (TX_NUM_OF_LANES >= 4) ? tx_pll_locked_3 : 1'b1;
-  assign tx_user_ready_all[3] = (TX_NUM_OF_LANES >= 4) ? tx_user_ready_3 : 1'b1;
-  assign tx_rst_done_all[3] = (TX_NUM_OF_LANES >= 4) ? tx_rst_done_3 : 1'b1;
-  assign tx_ip_rst_done_all[3] = (TX_NUM_OF_LANES >= 4) ? tx_ip_rst_done_3 : 1'b1;
-  assign tx_ip_data_all[((32*3)+31):(32*3)] = tx_ip_data_3;
-
-  assign tx_all_p[4] = tx_4_p;
-  assign tx_all_n[4] = tx_4_n;
-  assign tx_pll_locked_all[4] = (TX_NUM_OF_LANES >= 5) ? tx_pll_locked_4 : 1'b1;
-  assign tx_user_ready_all[4] = (TX_NUM_OF_LANES >= 5) ? tx_user_ready_4 : 1'b1;
-  assign tx_rst_done_all[4] = (TX_NUM_OF_LANES >= 5) ? tx_rst_done_4 : 1'b1;
-  assign tx_ip_rst_done_all[4] = (TX_NUM_OF_LANES >= 5) ? tx_ip_rst_done_4 : 1'b1;
-  assign tx_ip_data_all[((32*4)+31):(32*4)] = tx_ip_data_4;
-
-  assign tx_all_p[5] = tx_5_p;
-  assign tx_all_n[5] = tx_5_n;
-  assign tx_pll_locked_all[5] = (TX_NUM_OF_LANES >= 6) ? tx_pll_locked_5 : 1'b1;
-  assign tx_user_ready_all[5] = (TX_NUM_OF_LANES >= 6) ? tx_user_ready_5 : 1'b1;
-  assign tx_rst_done_all[5] = (TX_NUM_OF_LANES >= 6) ? tx_rst_done_5 : 1'b1;
-  assign tx_ip_rst_done_all[5] = (TX_NUM_OF_LANES >= 6) ? tx_ip_rst_done_5 : 1'b1;
-  assign tx_ip_data_all[((32*5)+31):(32*5)] = tx_ip_data_5;
-
-  assign tx_all_p[6] = tx_6_p;
-  assign tx_all_n[6] = tx_6_n;
-  assign tx_pll_locked_all[6] = (TX_NUM_OF_LANES >= 7) ? tx_pll_locked_6 : 1'b1;
-  assign tx_user_ready_all[6] = (TX_NUM_OF_LANES >= 7) ? tx_user_ready_6 : 1'b1;
-  assign tx_rst_done_all[6] = (TX_NUM_OF_LANES >= 7) ? tx_rst_done_6 : 1'b1;
-  assign tx_ip_rst_done_all[6] = (TX_NUM_OF_LANES >= 7) ? tx_ip_rst_done_6 : 1'b1;
-  assign tx_ip_data_all[((32*6)+31):(32*6)] = tx_ip_data_6;
-
-  assign tx_all_p[7] = tx_7_p;
-  assign tx_all_n[7] = tx_7_n;
-  assign tx_pll_locked_all[7] = (TX_NUM_OF_LANES >= 8) ? tx_pll_locked_7 : 1'b1;
-  assign tx_user_ready_all[7] = (TX_NUM_OF_LANES >= 8) ? tx_user_ready_7 : 1'b1;
-  assign tx_rst_done_all[7] = (TX_NUM_OF_LANES >= 8) ? tx_rst_done_7 : 1'b1;
-  assign tx_ip_rst_done_all[7] = (TX_NUM_OF_LANES >= 8) ? tx_ip_rst_done_7 : 1'b1;
-  assign tx_ip_data_all[((32*7)+31):(32*7)] = tx_ip_data_7;
-
-  generate
-  if (TX_NUM_OF_LANES < 8) begin
-  assign tx_data_all[((8*32)-1):(TX_NUM_OF_LANES*32)] = 'd0;
-  end
-  endgenerate
-
-  assign tx_data_all[((TX_NUM_OF_LANES*32)-1):0] = tx_data;
-
-  assign tx_p = tx_all_p[((TX_NUM_OF_LANES* 1)-1):0];
-  assign tx_n = tx_all_n[((TX_NUM_OF_LANES* 1)-1):0];
-
-  assign tx_out_clk = tx_out_clk_0;
-  assign tx_rst = tx_rst_0;
-
-  assign tx_ip_rst = tx_ip_rst_0;
-  assign tx_ip_rst_done = & tx_ip_rst_done_all;
-  assign tx_ip_sysref = tx_ip_sysref_0;
-  assign tx_ip_sync = tx_ip_sync_0;
-  assign tx_ip_data = tx_ip_data_all[((TX_NUM_OF_LANES*32)-1):0];
-
-  assign tx_rst_m_0 = tx_rst_0;
-  assign tx_gt_rst_m_0 = tx_gt_rst_0;
-  assign tx_pll_locked_m_0 = & tx_pll_locked_all;
-  assign tx_user_ready_m_0 = & tx_user_ready_all;
-  assign tx_rst_done_m_0 = & tx_rst_done_all;
-  assign tx_clk_0 = tx_clk;
-  assign tx_sysref_0 = tx_sysref;
-  assign tx_sync_0 = tx_sync;
-  assign tx_data_0 = tx_data_all[((32*0)+31):(32*0)];
-
-  assign tx_rst_m_1 = tx_rst_0;
-  assign tx_gt_rst_m_1 = tx_gt_rst_0;
-  assign tx_pll_locked_m_1 = & tx_pll_locked_all;
-  assign tx_user_ready_m_1 = & tx_user_ready_all;
-  assign tx_rst_done_m_1 = & tx_rst_done_all;
-  assign tx_clk_1 = tx_clk;
-  assign tx_sysref_1 = tx_sysref;
-  assign tx_sync_1 = tx_sync;
-  assign tx_data_1 = tx_data_all[((32*1)+31):(32*1)];
-
-  assign tx_rst_m_2 = tx_rst_0;
-  assign tx_gt_rst_m_2 = tx_gt_rst_0;
-  assign tx_pll_locked_m_2 = & tx_pll_locked_all;
-  assign tx_user_ready_m_2 = & tx_user_ready_all;
-  assign tx_rst_done_m_2 = & tx_rst_done_all;
-  assign tx_clk_2 = tx_clk;
-  assign tx_sysref_2 = tx_sysref;
-  assign tx_sync_2 = tx_sync;
-  assign tx_data_2 = tx_data_all[((32*2)+31):(32*2)];
-
-  assign tx_rst_m_3 = tx_rst_0;
-  assign tx_gt_rst_m_3 = tx_gt_rst_0;
-  assign tx_pll_locked_m_3 = & tx_pll_locked_all;
-  assign tx_user_ready_m_3 = & tx_user_ready_all;
-  assign tx_rst_done_m_3 = & tx_rst_done_all;
-  assign tx_clk_3 = tx_clk;
-  assign tx_sysref_3 = tx_sysref;
-  assign tx_sync_3 = tx_sync;
-  assign tx_data_3 = tx_data_all[((32*3)+31):(32*3)];
-
-  assign tx_rst_m_4 = tx_rst_0;
-  assign tx_gt_rst_m_4 = tx_gt_rst_0;
-  assign tx_pll_locked_m_4 = & tx_pll_locked_all;
-  assign tx_user_ready_m_4 = & tx_user_ready_all;
-  assign tx_rst_done_m_4 = & tx_rst_done_all;
-  assign tx_clk_4 = tx_clk;
-  assign tx_sysref_4 = tx_sysref;
-  assign tx_sync_4 = tx_sync;
-  assign tx_data_4 = tx_data_all[((32*4)+31):(32*4)];
-
-  assign tx_rst_m_5 = tx_rst_0;
-  assign tx_gt_rst_m_5 = tx_gt_rst_0;
-  assign tx_pll_locked_m_5 = & tx_pll_locked_all;
-  assign tx_user_ready_m_5 = & tx_user_ready_all;
-  assign tx_rst_done_m_5 = & tx_rst_done_all;
-  assign tx_clk_5 = tx_clk;
-  assign tx_sysref_5 = tx_sysref;
-  assign tx_sync_5 = tx_sync;
-  assign tx_data_5 = tx_data_all[((32*5)+31):(32*5)];
-
-  assign tx_rst_m_6 = tx_rst_0;
-  assign tx_gt_rst_m_6 = tx_gt_rst_0;
-  assign tx_pll_locked_m_6 = & tx_pll_locked_all;
-  assign tx_user_ready_m_6 = & tx_user_ready_all;
-  assign tx_rst_done_m_6 = & tx_rst_done_all;
-  assign tx_clk_6 = tx_clk;
-  assign tx_sysref_6 = tx_sysref;
-  assign tx_sync_6 = tx_sync;
-  assign tx_data_6 = tx_data_all[((32*6)+31):(32*6)];
-
-  assign tx_rst_m_7 = tx_rst_0;
-  assign tx_gt_rst_m_7 = tx_gt_rst_0;
-  assign tx_pll_locked_m_7 = & tx_pll_locked_all;
-  assign tx_user_ready_m_7 = & tx_user_ready_all;
-  assign tx_rst_done_m_7 = & tx_rst_done_all;
-  assign tx_clk_7 = tx_clk;
-  assign tx_sysref_7 = tx_sysref;
-  assign tx_sync_7 = tx_sync;
-  assign tx_data_7 = tx_data_all[((32*7)+31):(32*7)];
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/util_jesd_gt/util_jesd_gt_ip.tcl b/library/util_jesd_gt/util_jesd_gt_ip.tcl
deleted file mode 100644
index 34986ed7b..000000000
--- a/library/util_jesd_gt/util_jesd_gt_ip.tcl
+++ /dev/null
@@ -1,188 +0,0 @@
-# ip
-
-source ../scripts/adi_env.tcl
-source $ad_hdl_dir/library/scripts/adi_ip.tcl
-
-adi_ip_create util_jesd_gt
-adi_ip_files util_jesd_gt [list \
-  "util_jesd_gt.v" ]
-
-adi_ip_properties_lite util_jesd_gt
-
-ipx::remove_all_bus_interface [ipx::current_core]
-
-adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_0 [list \
-  "qpll_rst            qpll0_rst              "\
-  "qpll_ref_clk        qpll0_ref_clk_in       "]
-
-adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_1 [list \
-  "qpll_rst            qpll1_rst              "\
-  "qpll_ref_clk        qpll1_ref_clk_in       "]
-
-for {set n 0} {$n < 8} {incr n} {
-
-  adi_if_infer_bus ADI:user:if_gt_pll master gt_pll_${n} [list \
-    "cpll_rst_m          cpll_rst_m_${n}        "\
-    "cpll_ref_clk_in     cpll_ref_clk_in_${n}   "]
-
-  adi_if_infer_bus ADI:user:if_gt_rx master gt_rx_${n} [list \
-    "rx_p                rx_${n}_p              "\
-    "rx_n                rx_${n}_n              "\
-    "rx_rst              rx_rst_${n}            "\
-    "rx_rst_m            rx_rst_m_${n}          "\
-    "rx_pll_rst          rx_pll_rst_${n}        "\
-    "rx_gt_rst           rx_gt_rst_${n}         "\
-    "rx_gt_rst_m         rx_gt_rst_m_${n}       "\
-    "rx_pll_locked       rx_pll_locked_${n}     "\
-    "rx_pll_locked_m     rx_pll_locked_m_${n}   "\
-    "rx_user_ready       rx_user_ready_${n}     "\
-    "rx_user_ready_m     rx_user_ready_m_${n}   "\
-    "rx_rst_done         rx_rst_done_${n}       "\
-    "rx_rst_done_m       rx_rst_done_m_${n}     "\
-    "rx_out_clk          rx_out_clk_${n}        "\
-    "rx_clk              rx_clk_${n}            "\
-    "rx_sysref           rx_sysref_${n}         "\
-    "rx_sync             rx_sync_${n}           "\
-    "rx_sof              rx_sof_${n}            "\
-    "rx_data             rx_data_${n}           "\
-    "rx_ip_rst           rx_ip_rst_${n}         "\
-    "rx_ip_sof           rx_ip_sof_${n}         "\
-    "rx_ip_data          rx_ip_data_${n}        "\
-    "rx_ip_sysref        rx_ip_sysref_${n}      "\
-    "rx_ip_sync          rx_ip_sync_${n}        "\
-    "rx_ip_rst_done      rx_ip_rst_done_${n}    "]
-
-  adi_if_infer_bus ADI:user:if_gt_tx master gt_tx_${n} [list \
-    "tx_p                tx_${n}_p              "\
-    "tx_n                tx_${n}_n              "\
-    "tx_rst              tx_rst_${n}            "\
-    "tx_rst_m            tx_rst_m_${n}          "\
-    "tx_pll_rst          tx_pll_rst_${n}        "\
-    "tx_gt_rst           tx_gt_rst_${n}         "\
-    "tx_gt_rst_m         tx_gt_rst_m_${n}       "\
-    "tx_pll_locked       tx_pll_locked_${n}     "\
-    "tx_pll_locked_m     tx_pll_locked_m_${n}   "\
-    "tx_user_ready       tx_user_ready_${n}     "\
-    "tx_user_ready_m     tx_user_ready_m_${n}   "\
-    "tx_rst_done         tx_rst_done_${n}       "\
-    "tx_rst_done_m       tx_rst_done_m_${n}     "\
-    "tx_out_clk          tx_out_clk_${n}        "\
-    "tx_clk              tx_clk_${n}            "\
-    "tx_sysref           tx_sysref_${n}         "\
-    "tx_sync             tx_sync_${n}           "\
-    "tx_data             tx_data_${n}           "\
-    "tx_ip_rst           tx_ip_rst_${n}         "\
-    "tx_ip_data          tx_ip_data_${n}        "\
-    "tx_ip_sysref        tx_ip_sysref_${n}      "\
-    "tx_ip_sync          tx_ip_sync_${n}        "\
-    "tx_ip_rst_done      tx_ip_rst_done_${n}    "]
-}
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_ports rx_p -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_n -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_sysref -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_sync -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_out_clk -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_clk -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_rst -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_sof -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_data -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_ip_rst -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_ip_rst_done -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_ip_sysref -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_ip_sync -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_ip_sof -of_objects [ipx::current_core]] \
-  [ipx::get_ports rx_ip_data -of_objects [ipx::current_core]]
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_ports tx_p -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_n -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_sysref -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_sync -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_out_clk -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_clk -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_rst -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_data -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_ip_rst -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_ip_rst_done -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_ip_sysref -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_ip_sync -of_objects [ipx::current_core]] \
-  [ipx::get_ports tx_ip_data -of_objects [ipx::current_core]]
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL0_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_qpll_0 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL1_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_qpll_1 -of_objects [ipx::current_core]] 
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
-  [ipx::get_bus_interfaces gt_pll_0 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
-  [ipx::get_bus_interfaces gt_pll_1 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
-  [ipx::get_bus_interfaces gt_pll_2 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
-  [ipx::get_bus_interfaces gt_pll_3 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
-  [ipx::get_bus_interfaces gt_pll_4 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
-  [ipx::get_bus_interfaces gt_pll_5 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
-  [ipx::get_bus_interfaces gt_pll_6 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
-  [ipx::get_bus_interfaces gt_pll_7 -of_objects [ipx::current_core]] 
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0 and \
-  spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_rx_0 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1 and \
-  spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_rx_1 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2 and \
-  spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_rx_2 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3 and \
-  spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_rx_3 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4 and \
-  spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_rx_4 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5 and \
-  spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_rx_5 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6 and \
-  spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_rx_6 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7 and \
-  spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_rx_7 -of_objects [ipx::current_core]] 
-
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0 and \
-  spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_tx_0 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1 and \
-  spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_tx_1 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2 and \
-  spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_tx_2 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3 and \
-  spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_tx_3 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4 and \
-  spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_tx_4 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5 and \
-  spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_tx_5 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6 and \
-  spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_tx_6 -of_objects [ipx::current_core]] 
-set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7 and \
-  spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \
-  [ipx::get_bus_interfaces gt_tx_7 -of_objects [ipx::current_core]] 
-
-set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
-
-ipx::save_core [ipx::current_core]
-

From 99f72a9b3b7a72e7aa74fc5928f582092b0faf47 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 12 Dec 2016 14:20:45 +0200
Subject: [PATCH 803/972] util_gtlb: this core is obsoleted

The util_gtlb core is obsoleted by xilinx/axi_xcvrlb
---
 library/util_gtlb/Makefile             |  59 ----
 library/util_gtlb/util_gtlb.v          | 387 -------------------------
 library/util_gtlb/util_gtlb_constr.xdc |   9 -
 library/util_gtlb/util_gtlb_ip.tcl     |  93 ------
 4 files changed, 548 deletions(-)
 delete mode 100644 library/util_gtlb/Makefile
 delete mode 100644 library/util_gtlb/util_gtlb.v
 delete mode 100644 library/util_gtlb/util_gtlb_constr.xdc
 delete mode 100644 library/util_gtlb/util_gtlb_ip.tcl

diff --git a/library/util_gtlb/Makefile b/library/util_gtlb/Makefile
deleted file mode 100644
index ff750ba99..000000000
--- a/library/util_gtlb/Makefile
+++ /dev/null
@@ -1,59 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += util_gtlb.v
-M_DEPS += util_gtlb_constr.xdc
-M_DEPS += util_gtlb_ip.tcl
-
-M_DEPS += ../interfaces/if_gt_pll.xml
-M_DEPS += ../interfaces/if_gt_pll_rtl.xml
-M_DEPS += ../interfaces/if_gt_qpll.xml
-M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
-M_DEPS += ../interfaces/if_gt_rx.xml
-M_DEPS += ../interfaces/if_gt_rx_rtl.xml
-M_DEPS += ../interfaces/if_gt_tx.xml
-M_DEPS += ../interfaces/if_gt_tx_rtl.xml
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += component.xml
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.ip_user_files
-M_FLIST += *.srcs
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-
-
-
-.PHONY: all dep clean clean-all
-all: dep util_gtlb.xpr
-
-
-clean:clean-all
-
-
-clean-all:
-	rm -rf $(M_FLIST)
-
-
-util_gtlb.xpr: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) util_gtlb_ip.tcl  >> util_gtlb_ip.log 2>&1
-
-dep:
-	make -C ../interfaces
-####################################################################################
-####################################################################################
diff --git a/library/util_gtlb/util_gtlb.v b/library/util_gtlb/util_gtlb.v
deleted file mode 100644
index 1fc9f9591..000000000
--- a/library/util_gtlb/util_gtlb.v
+++ /dev/null
@@ -1,387 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module util_gtlb (
-
-  // pll clocks & resets
-
-  input                 qpll_ref_clk,
-  input                 cpll_ref_clk,
-
-  output                qpll0_rst,
-  output                qpll0_ref_clk_in,
-
-  output                cpll_rst_m_0,
-  output                cpll_ref_clk_in_0,
-
-  // channel interface (rx)
-  
-  input                 rx_p,
-  input                 rx_n,
-
-  output                rx_clk,
-
-  input       [ 3:0]    rx_gt_charisk_0,
-  input       [ 3:0]    rx_gt_disperr_0,
-  input       [ 3:0]    rx_gt_notintable_0,
-  input       [31:0]    rx_gt_data_0,
-  output  reg           rx_gt_comma_align_enb_0,
-
-  output                rx_0_p,
-  output                rx_0_n,
-  input                 rx_rst_0,
-  output                rx_rst_m_0,
-  input                 rx_pll_rst_0,
-  input                 rx_gt_rst_0,
-  output                rx_gt_rst_m_0,
-  input                 rx_pll_locked_0,
-  output                rx_pll_locked_m_0,
-  input                 rx_user_ready_0,
-  output                rx_user_ready_m_0,
-  input                 rx_rst_done_0,
-  output                rx_rst_done_m_0,
-  input                 rx_out_clk_0,
-  output                rx_clk_0,
-  output                rx_sysref_0,
-  input                 rx_sync_0,
-  input                 rx_sof_0,
-  input       [31:0]    rx_data_0,
-  input                 rx_ip_rst_0,
-  output      [ 3:0]    rx_ip_sof_0,
-  output      [31:0]    rx_ip_data_0,
-  input                 rx_ip_sysref_0,
-  output                rx_ip_sync_0,
-  input                 rx_ip_rst_done_0,
-
-  // channel interface (tx)
-
-  output                tx_p,
-  output                tx_n,
-
-  output                tx_clk,
-
-  output      [ 3:0]    tx_gt_charisk_0,
-  output  reg [31:0]    tx_gt_data_0,
-
-  input                 tx_0_p,
-  input                 tx_0_n,
-  input                 tx_rst_0,
-  output                tx_rst_m_0,
-  input                 tx_pll_rst_0,
-  input                 tx_gt_rst_0,
-  output                tx_gt_rst_m_0,
-  input                 tx_pll_locked_0,
-  output                tx_pll_locked_m_0,
-  input                 tx_user_ready_0,
-  output                tx_user_ready_m_0,
-  input                 tx_rst_done_0,
-  output                tx_rst_done_m_0,
-  input                 tx_out_clk_0,
-  output                tx_clk_0,
-  output                tx_sysref_0,
-  output                tx_sync_0,
-  output      [31:0]    tx_data_0,
-  input                 tx_ip_rst_0,
-  input       [31:0]    tx_ip_data_0,
-  input                 tx_ip_sysref_0,
-  input                 tx_ip_sync_0,
-  input                 tx_ip_rst_done_0,
-
-  // up interface
-
-  input                 up_clk,
-  input                 up_rstn,
-  input       [31:0]    up_gp_in,
-  output      [31:0]    up_gp_out);
-
-  // internal registers
-
-  reg                   tx_sync_m1 = 'd0;
-  reg                   tx_sync_m2 = 'd0;
-  reg                   tx_sync = 'd0;
-  reg         [31:0]    tx_pn_data = 'd0;
-  reg                   tx_charisk_1 = 'd0;
-  reg         [ 3:0]    rx_kcount = 'd0;
-  reg                   rx_sync = 'd0;
-  reg         [31:0]    rx_pn_data = 'd0;
-  reg                   rx_pn_match_d = 'd0;
-  reg                   rx_pn_match_z = 'd0;
-  reg                   rx_pn_err = 'd0;
-  reg                   rx_pn_oos = 'd0;
-  reg         [ 3:0]    rx_pn_oos_count = 'd0;
-  reg                   up_pn_err_clr_d = 'd0;
-  reg                   up_pn_oos_clr_d = 'd0;
-  reg                   up_pn_err = 'd0;
-  reg                   up_pn_oos = 'd0;
-    
-  // internal signals
-
-  wire        [31:0]    rx_gt_data_0_s;
-  wire        [31:0]    rx_pn_data_s;
-  wire                  rx_pn_match_d_s;
-  wire                  rx_pn_match_z_s;
-  wire                  rx_pn_match_s;
-  wire                  rx_pn_update_s;
-  wire                  rx_pn_err_s;
-  wire                  up_pn_err_clr_s;
-  wire                  up_pn_oos_clr_s;
-  wire                  up_pn_err_s;
-  wire                  up_pn_oos_s;
-
-  // pn31 function
-
-  function [31:0] pn31;
-    input [31:0] din;
-    reg   [31:0] dout;
-    begin
-      dout[31] = din[31] ^ din[28];
-      dout[30] = din[30] ^ din[27];
-      dout[29] = din[29] ^ din[26];
-      dout[28] = din[28] ^ din[25];
-      dout[27] = din[27] ^ din[24];
-      dout[26] = din[26] ^ din[23];
-      dout[25] = din[25] ^ din[22];
-      dout[24] = din[24] ^ din[21];
-      dout[23] = din[23] ^ din[20];
-      dout[22] = din[22] ^ din[19];
-      dout[21] = din[21] ^ din[18];
-      dout[20] = din[20] ^ din[17];
-      dout[19] = din[19] ^ din[16];
-      dout[18] = din[18] ^ din[15];
-      dout[17] = din[17] ^ din[14];
-      dout[16] = din[16] ^ din[13];
-      dout[15] = din[15] ^ din[12];
-      dout[14] = din[14] ^ din[11];
-      dout[13] = din[13] ^ din[10];
-      dout[12] = din[12] ^ din[ 9];
-      dout[11] = din[11] ^ din[ 8];
-      dout[10] = din[10] ^ din[ 7];
-      dout[ 9] = din[ 9] ^ din[ 6];
-      dout[ 8] = din[ 8] ^ din[ 5];
-      dout[ 7] = din[ 7] ^ din[ 4];
-      dout[ 6] = din[ 6] ^ din[ 3];
-      dout[ 5] = din[ 5] ^ din[ 2];
-      dout[ 4] = din[ 4] ^ din[ 1];
-      dout[ 3] = din[ 3] ^ din[ 0];
-      dout[ 2] = din[ 2] ^ din[31] ^ din[28];
-      dout[ 1] = din[ 1] ^ din[30] ^ din[27];
-      dout[ 0] = din[ 0] ^ din[29] ^ din[26];
-      pn31 = dout;
-    end
-  endfunction
-
-  // defaults
-
-  assign qpll0_rst = tx_pll_rst_0 | rx_pll_rst_0;
-  assign qpll0_ref_clk_in = qpll_ref_clk;
-  assign cpll_rst_m_0 = tx_pll_rst_0 | rx_pll_rst_0;
-  assign cpll_ref_clk_in_0 = cpll_ref_clk;
-
-  assign rx_0_p = rx_p;
-  assign rx_0_n = rx_n;
-  assign rx_rst_m_0 = rx_rst_0;
-  assign rx_gt_rst_m_0 = rx_gt_rst_0;
-  assign rx_pll_locked_m_0 = rx_pll_locked_0;
-  assign rx_user_ready_m_0 = rx_user_ready_0;
-  assign rx_rst_done_m_0 = & rx_rst_done_0;
-  assign rx_clk_0 = rx_out_clk_0;
-  assign rx_sysref_0 = 1'd0;
-  assign rx_ip_sof_0 = 4'hf;
-  assign rx_ip_data_0 = 32'd0;
-  assign rx_ip_sync_0 = rx_sync;
-  assign rx_clk = rx_out_clk_0;
-
-  assign tx_p = tx_0_p;
-  assign tx_n = tx_0_n;
-  assign tx_rst_m_0 = tx_rst_0;
-  assign tx_gt_rst_m_0 = tx_gt_rst_0;
-  assign tx_pll_locked_m_0 = tx_pll_locked_0;
-  assign tx_user_ready_m_0 = tx_user_ready_0;
-  assign tx_rst_done_m_0 = tx_rst_done_0;
-  assign tx_clk_0 = tx_out_clk_0;
-  assign tx_sysref_0 = 1'd0;
-  assign tx_sync_0 = tx_sync;
-  assign tx_data_0 = 32'd0;
-  assign tx_clk = tx_out_clk_0;
-
-  // gt loop back
-
-  assign tx_gt_charisk_0 = {4{tx_charisk_1}};
-
-  always @(posedge tx_out_clk_0 or posedge tx_rst_0) begin
-    if (tx_rst_0 == 1'b1) begin
-      tx_sync_m1 <= 1'd0;
-      tx_sync_m2 <= 1'd0;
-      tx_sync <= 1'd0;
-      tx_pn_data <= 32'hffffffff;
-      tx_charisk_1 <= 1'd0;
-      tx_gt_data_0 <= 32'd0;
-    end else begin
-      tx_sync_m1 <= rx_sync;
-      tx_sync_m2 <= tx_sync_m1;
-      tx_sync <= tx_sync_m2;
-      tx_pn_data <= pn31(tx_pn_data);
-      if (tx_sync == 1'b1) begin
-        tx_charisk_1 <= 1'd0;
-        tx_gt_data_0[31:24] <= tx_pn_data[ 7: 0];
-        tx_gt_data_0[23:16] <= tx_pn_data[15: 8];
-        tx_gt_data_0[15: 8] <= tx_pn_data[23:16];
-        tx_gt_data_0[ 7: 0] <= tx_pn_data[31:24];
-      end else begin
-        tx_charisk_1 <= 1'd1;
-        tx_gt_data_0[31:24] <= 8'hbc;
-        tx_gt_data_0[23:16] <= 8'hbc;
-        tx_gt_data_0[15: 8] <= 8'hbc;
-        tx_gt_data_0[ 7: 0] <= 8'hbc;
-      end
-    end
-  end
-
-  assign rx_gt_data_0_s[31:24] = rx_gt_data_0[ 7: 0];
-  assign rx_gt_data_0_s[23:16] = rx_gt_data_0[15: 8];
-  assign rx_gt_data_0_s[15: 8] = rx_gt_data_0[23:16];
-  assign rx_gt_data_0_s[ 7: 0] = rx_gt_data_0[31:24];
-
-  always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin
-    if (rx_rst_0 == 1'b1) begin
-      rx_gt_comma_align_enb_0 <= 1'd0;
-      rx_kcount <= 4'd0;
-      rx_sync <= 1'd0;
-    end else begin
-      rx_gt_comma_align_enb_0 <= ~rx_sync;
-      if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0)) begin
-        if ((rx_gt_charisk_0 == 4'hf) && (rx_gt_data_0_s == 32'hbcbcbcbc)) begin
-          rx_kcount <= rx_kcount + 1'b1;
-          if (rx_kcount == 4'hf) begin
-            rx_sync <= 1'b1;
-          end
-        end else begin
-          rx_kcount <= 4'd0;
-          rx_sync <= rx_sync;
-        end
-      end else begin
-        rx_kcount <= 4'd0;
-        rx_sync <= 1'd0;
-      end
-    end
-  end
-
-  assign rx_pn_data_s = (rx_pn_oos == 1'b1) ? rx_gt_data_0_s : rx_pn_data;
-  assign rx_pn_match_d_s = (rx_gt_data_0_s == rx_pn_data) ? 1'b1 : 1'b0;
-  assign rx_pn_match_z_s = (rx_gt_data_0_s == 'd0) ? 1'b0 : 1'b1;
-  assign rx_pn_match_s = rx_pn_match_d & rx_pn_match_z;
-  assign rx_pn_update_s = ~(rx_pn_oos ^ rx_pn_match_s);
-  assign rx_pn_err_s = ~(rx_pn_oos | rx_pn_match_s);
-
-  always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin
-    if (rx_rst_0 == 1'b1) begin
-      rx_pn_data <= 32'd0;
-      rx_pn_match_d <= 'd0;
-      rx_pn_match_z <= 'd0;
-      rx_pn_err <= 'd0;
-      rx_pn_oos <= 'd0;
-      rx_pn_oos_count <= 'd0;
-    end else begin
-      rx_pn_data <= pn31(rx_pn_data_s);
-      rx_pn_match_d <= rx_pn_match_d_s;
-      rx_pn_match_z <= rx_pn_match_z_s;
-      if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0) && (rx_gt_charisk_0 == 0)) begin
-        rx_pn_err <= rx_pn_err_s;
-        if ((rx_pn_update_s == 1'b1) && (rx_pn_oos_count >= 15)) begin
-          rx_pn_oos <= ~rx_pn_oos;
-        end
-        if (rx_pn_update_s == 1'b1) begin
-          rx_pn_oos_count <= rx_pn_oos_count + 1'b1;
-        end else begin
-          rx_pn_oos_count <= 'd0;
-        end
-      end else begin
-        rx_pn_err <= 1'd0;
-        rx_pn_oos <= 1'd1;
-        rx_pn_oos_count <= 'd0;
-      end
-    end
-  end
-
-  // up clock
-
-  assign up_pn_err_clr_s = up_gp_in[1];
-  assign up_pn_oos_clr_s = up_gp_in[0];
-
-  assign up_gp_out[31:2] = 30'd0;
-  assign up_gp_out[1] = up_pn_err;
-  assign up_gp_out[0] = up_pn_oos;
-
-  up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_data_status ({up_pn_err_s, up_pn_oos_s}),
-    .d_rst (rx_rst_0),
-    .d_clk (rx_out_clk_0),
-    .d_data_status ({rx_pn_err, rx_pn_oos}));
-
-  always @(posedge up_clk or negedge up_rstn) begin
-    if (up_rstn == 1'b0) begin
-      up_pn_err_clr_d <= 'd0;
-      up_pn_oos_clr_d <= 'd0;
-      up_pn_err <= 'd0;
-      up_pn_oos <= 'd0;
-    end else begin
-      up_pn_err_clr_d <= up_pn_err_clr_s;
-      up_pn_oos_clr_d <= up_pn_oos_clr_s;
-      if (up_pn_err_s == 1'b1) begin
-        up_pn_err <= 1'b1;
-      end else if ((up_pn_err_clr_s == 1'b1) &&
-        (up_pn_err_clr_d == 1'b0)) begin
-        up_pn_err <= 1'b0;
-      end
-      if (up_pn_oos_s == 1'b1) begin
-        up_pn_oos <= 1'b1;
-      end else if ((up_pn_oos_clr_s == 1'b1) &&
-        (up_pn_oos_clr_d == 1'b0)) begin
-        up_pn_oos <= 1'b0;
-      end
-    end
-  end
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/util_gtlb/util_gtlb_constr.xdc b/library/util_gtlb/util_gtlb_constr.xdc
deleted file mode 100644
index 644f04f85..000000000
--- a/library/util_gtlb/util_gtlb_constr.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-
-set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_sync*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
-
-set_false_path -to [get_cells -hier -filter {name =~ *tx_sync_m1_reg && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg    && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg  && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data*        && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_data_status*        && IS_SEQUENTIAL}]
-
diff --git a/library/util_gtlb/util_gtlb_ip.tcl b/library/util_gtlb/util_gtlb_ip.tcl
deleted file mode 100644
index cf01a575b..000000000
--- a/library/util_gtlb/util_gtlb_ip.tcl
+++ /dev/null
@@ -1,93 +0,0 @@
-# ip
-
-source ../scripts/adi_env.tcl
-source $ad_hdl_dir/library/scripts/adi_ip.tcl
-
-adi_ip_create util_gtlb
-adi_ip_files util_gtlb [list \
-  "$ad_hdl_dir/library/common/up_xfer_status.v" \
-  "util_gtlb_constr.xdc" \
-  "util_gtlb.v" ]
-
-adi_ip_properties_lite util_gtlb
-adi_ip_constraints util_gtlb [list \
-  "util_gtlb_constr.xdc" ]
-
-ipx::remove_all_bus_interface [ipx::current_core]
-
-adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_0 [list \
-  "qpll_rst            qpll0_rst              "\
-  "qpll_ref_clk        qpll0_ref_clk_in       "]
-
-for {set n 0} {$n < 1} {incr n} {
-
-  adi_if_infer_bus ADI:user:if_gt_pll master gt_pll_${n} [list \
-    "cpll_rst_m          cpll_rst_m_${n}        "\
-    "cpll_ref_clk_in     cpll_ref_clk_in_${n}   "]
-
-  adi_if_infer_bus xilinx.com:display_jesd204:jesd204_rx_bus slave gt_rx_ip_${n} [list \
-    "rxcharisk           rx_gt_charisk_${n}     "\
-    "rxdisperr           rx_gt_disperr_${n}     "\
-    "rxnotintable        rx_gt_notintable_${n}  "\
-    "rxdata              rx_gt_data_${n}        "]
-
-  adi_if_infer_bus ADI:user:if_gt_rx master gt_rx_${n} [list \
-    "rx_p                rx_${n}_p              "\
-    "rx_n                rx_${n}_n              "\
-    "rx_rst              rx_rst_${n}            "\
-    "rx_rst_m            rx_rst_m_${n}          "\
-    "rx_pll_rst          rx_pll_rst_${n}        "\
-    "rx_gt_rst           rx_gt_rst_${n}         "\
-    "rx_gt_rst_m         rx_gt_rst_m_${n}       "\
-    "rx_pll_locked       rx_pll_locked_${n}     "\
-    "rx_pll_locked_m     rx_pll_locked_m_${n}   "\
-    "rx_user_ready       rx_user_ready_${n}     "\
-    "rx_user_ready_m     rx_user_ready_m_${n}   "\
-    "rx_rst_done         rx_rst_done_${n}       "\
-    "rx_rst_done_m       rx_rst_done_m_${n}     "\
-    "rx_out_clk          rx_out_clk_${n}        "\
-    "rx_clk              rx_clk_${n}            "\
-    "rx_sysref           rx_sysref_${n}         "\
-    "rx_sync             rx_sync_${n}           "\
-    "rx_sof              rx_sof_${n}            "\
-    "rx_data             rx_data_${n}           "\
-    "rx_ip_rst           rx_ip_rst_${n}         "\
-    "rx_ip_sof           rx_ip_sof_${n}         "\
-    "rx_ip_data          rx_ip_data_${n}        "\
-    "rx_ip_sysref        rx_ip_sysref_${n}      "\
-    "rx_ip_sync          rx_ip_sync_${n}        "\
-    "rx_ip_rst_done      rx_ip_rst_done_${n}    "]
-
-  adi_if_infer_bus xilinx.com:display_jesd204:jesd204_tx_bus master gt_tx_ip_${n} [list \
-    "txcharisk           tx_gt_charisk_${n}     "\
-    "txdata              tx_gt_data_${n}        "]
-
-  adi_if_infer_bus ADI:user:if_gt_tx master gt_tx_${n} [list \
-    "tx_p                tx_${n}_p              "\
-    "tx_n                tx_${n}_n              "\
-    "tx_rst              tx_rst_${n}            "\
-    "tx_rst_m            tx_rst_m_${n}          "\
-    "tx_pll_rst          tx_pll_rst_${n}        "\
-    "tx_gt_rst           tx_gt_rst_${n}         "\
-    "tx_gt_rst_m         tx_gt_rst_m_${n}       "\
-    "tx_pll_locked       tx_pll_locked_${n}     "\
-    "tx_pll_locked_m     tx_pll_locked_m_${n}   "\
-    "tx_user_ready       tx_user_ready_${n}     "\
-    "tx_user_ready_m     tx_user_ready_m_${n}   "\
-    "tx_rst_done         tx_rst_done_${n}       "\
-    "tx_rst_done_m       tx_rst_done_m_${n}     "\
-    "tx_out_clk          tx_out_clk_${n}        "\
-    "tx_clk              tx_clk_${n}            "\
-    "tx_sysref           tx_sysref_${n}         "\
-    "tx_sync             tx_sync_${n}           "\
-    "tx_data             tx_data_${n}           "\
-    "tx_ip_rst           tx_ip_rst_${n}         "\
-    "tx_ip_data          tx_ip_data_${n}        "\
-    "tx_ip_sysref        tx_ip_sysref_${n}      "\
-    "tx_ip_sync          tx_ip_sync_${n}        "\
-    "tx_ip_rst_done      tx_ip_rst_done_${n}    "]
-}
-
-ipx::save_core [ipx::current_core]
-
-

From 9fb7db97dadff0f5ca2c315e475e2485d3880914 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 13 Dec 2016 10:30:24 +0200
Subject: [PATCH 804/972] a5gte: Fixed timing violations

---
 projects/common/a5gte/system_top.v | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/projects/common/a5gte/system_top.v b/projects/common/a5gte/system_top.v
index cf2f47b8f..8891789e6 100644
--- a/projects/common/a5gte/system_top.v
+++ b/projects/common/a5gte/system_top.v
@@ -100,7 +100,8 @@ module system_top (
 
   reg     [ 4:0]  eth_tx_data_h_d;
   reg     [ 4:0]  phy_rx_data_h_d;
-
+  reg     [ 4:0]  phy_rx_data_h_d1;
+  reg     [ 4:0]  phy_rx_data_l_d;
   // RX path
 
   altera_pll #(
@@ -194,9 +195,10 @@ module system_top (
   always @(posedge phy_rx_clk)
   begin
     phy_rx_data_h_d <= phy_rx_data_h;
+    phy_rx_data_h_d1 <= phy_rx_data_h_d;
+    phy_rx_data_l_d <= phy_rx_data_l;
   end
 
-
   altddio_out #(
     .extend_oe_disable("OFF"),
     .intended_device_family("Arria V"),
@@ -207,8 +209,8 @@ module system_top (
     .power_up_high("OFF"),
     .width(5)
   ) eth_rx_path_out (
-    .datain_h (phy_rx_data_h_d),
-    .datain_l (phy_rx_data_l),
+    .datain_h (phy_rx_data_h_d1),
+    .datain_l (phy_rx_data_l_d),
     .outclock (phy_rx_clk),
     .dataout ({eth_rx_cntrl,eth_rx_data}),
     .aclr (~eth_phy_resetn),

From c455d2d64f0ce7a8d349af1b3cd75de2adf73338 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 13 Dec 2016 19:15:44 +0200
Subject: [PATCH 805/972] fmcadc2/vc707: Disabele axi_spi constraint file   The
 interface ports of the AXI SPI IP are not connected   directly to a IOBUF,
 this results in a CRITICAL WARNING

---
 projects/fmcadc2/vc707/system_project.tcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/projects/fmcadc2/vc707/system_project.tcl b/projects/fmcadc2/vc707/system_project.tcl
index c6847933e..a9ca97db1 100644
--- a/projects/fmcadc2/vc707/system_project.tcl
+++ b/projects/fmcadc2/vc707/system_project.tcl
@@ -13,6 +13,8 @@ adi_project_files fmcadc2_vc707 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *system_axi*_spi*.xdc]
+
 adi_project_run fmcadc2_vc707
 
 

From 88461414671fb15a2d89fae0d931b634381ad034 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 13 Dec 2016 19:16:31 +0200
Subject: [PATCH 806/972] fmcomms1/kc705: Disabele axi_spi constraint file  
 The interface ports of the AXI SPI IP are not connected   directly to a
 IOBUF, this results in a CRITICAL WARNING

---
 projects/fmcomms1/kc705/system_project.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/fmcomms1/kc705/system_project.tcl b/projects/fmcomms1/kc705/system_project.tcl
index 34362a542..4e12b6de1 100644
--- a/projects/fmcomms1/kc705/system_project.tcl
+++ b/projects/fmcomms1/kc705/system_project.tcl
@@ -12,6 +12,7 @@ adi_project_files fmcomms1_kc705 [list \
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+set_property is_enabled false [get_files  *system_axi*_spi*.xdc]
 
 adi_project_run fmcomms1_kc705
 

From 1515b6f1afe1b745452621e3745c47d5b205cf4e Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 13 Dec 2016 19:18:18 +0200
Subject: [PATCH 807/972] fmcomms7/zc706: Disabele axi_spi constraint file  
 The interface ports of the AXI SPI IP are not connected   directly to a
 IOBUF, this results in a CRITICAL WARNING

---
 projects/fmcomms7/zc706/system_project.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/fmcomms7/zc706/system_project.tcl b/projects/fmcomms7/zc706/system_project.tcl
index 35fd66fb5..e82dc8160 100644
--- a/projects/fmcomms7/zc706/system_project.tcl
+++ b/projects/fmcomms7/zc706/system_project.tcl
@@ -16,6 +16,7 @@ adi_project_files fmcomms7_zc706 [list \
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
 set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+set_property is_enabled false [get_files  *system_axi*_spi*.xdc]
 
 adi_project_run fmcomms7_zc706
 

From d5165ca81f3ae03fef128ff9892768dd5d2bffa4 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 13 Dec 2016 19:20:13 +0200
Subject: [PATCH 808/972] motcon_fmc: Tie unused pins to GND

---
 projects/motcon2_fmc/common/motcon2_fmc_bd.tcl | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
index ac2ce0bfa..0a5c1dcc9 100644
--- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
+++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
@@ -221,6 +221,10 @@
   ad_connect current_monitor_m1_pack/adc_data current_monitor_m1_dma/fifo_wr_din
   ad_connect current_monitor_m1_pack/adc_valid current_monitor_m1_dma/fifo_wr_en
 
+  ad_connect current_monitor_m1_pack/adc_enable_3 GND
+  ad_connect current_monitor_m1_pack/adc_valid_3  GND
+  ad_connect current_monitor_m1_pack/adc_data_3   GND
+
     # motor 2
   ad_connect  sys_cpu_clk current_monitor_m2/ref_clk
 
@@ -246,6 +250,10 @@
   ad_connect current_monitor_m2_pack/adc_valid    current_monitor_m2_dma/fifo_wr_en
   ad_connect current_monitor_m2_pack/adc_data     current_monitor_m2_dma/fifo_wr_din
 
+  ad_connect current_monitor_m2_pack/adc_enable_3 GND
+  ad_connect current_monitor_m2_pack/adc_valid_3  GND
+  ad_connect current_monitor_m2_pack/adc_data_3   GND
+
   #controller
     # motor 1
   ad_connect sys_cpu_clk controller_m1/ref_clk
@@ -262,6 +270,13 @@
   ad_connect controller_m1/sensors_o          speed_detector_m1/hall_bemf_i
   ad_connect controller_m1/position_i         speed_detector_m1/position_o
 
+  ad_connect controller_m1/pwm_a_i GND
+  ad_connect controller_m1/pwm_b_i GND
+  ad_connect controller_m1/pwm_c_i GND
+  ad_connect controller_m2/pwm_a_i GND
+  ad_connect controller_m2/pwm_b_i GND
+  ad_connect controller_m2/pwm_c_i GND
+
     # motor 2
   ad_connect sys_cpu_clk controller_m2/ref_clk
   ad_connect controller_m2/ctrl_data_clk sys_audio_clkgen/clk_out5

From d962614000760a4dc0350228fee0ea18c0f109c1 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 13 Dec 2016 19:23:51 +0200
Subject: [PATCH 809/972] usdrx1/zc706: Disabele axi_spi constraint file   The
 interface ports of the AXI SPI IP are not connected   directly to a IOBUF,
 this results in a CRITICAL WARNING

---
 projects/usdrx1/zc706/system_project.tcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/projects/usdrx1/zc706/system_project.tcl b/projects/usdrx1/zc706/system_project.tcl
index df7245873..59e382beb 100644
--- a/projects/usdrx1/zc706/system_project.tcl
+++ b/projects/usdrx1/zc706/system_project.tcl
@@ -14,6 +14,8 @@ adi_project_files usdrx1_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
+set_property is_enabled false [get_files  *system_axi*_spi*.xdc]
+
 adi_project_run usdrx1_zc706
 
 

From 3a2c8891157cd989b1f7220826050d6952ee36a5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 14 Dec 2016 17:34:36 +0200
Subject: [PATCH 810/972] ad6676evb: Update GT configuration

---
 projects/ad6676evb/common/ad6676evb_bd.tcl | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl
index cf9b7afdf..7c1f17b72 100644
--- a/projects/ad6676evb/common/ad6676evb_bd.tcl
+++ b/projects/ad6676evb/common/ad6676evb_bd.tcl
@@ -33,14 +33,13 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
 set util_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad6676_xcvr]
 set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_ad6676_xcvr
 set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV_4_5 {5}] $util_ad6676_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_ad6676_xcvr
-set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_ad6676_xcvr
-set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_ad6676_xcvr
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr
 set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_ad6676_xcvr
-set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {8}] $util_ad6676_xcvr
 set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_ad6676_xcvr
-set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_ad6676_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad6676_xcvr
 
 # reference clocks & resets
 

From 557efed5d958f7dea3406c51b597f42b15cf3e3e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 14 Dec 2016 17:35:35 +0200
Subject: [PATCH 811/972] ad6676evb: Update clock constraints

---
 projects/ad6676evb/vc707/system_constr.xdc | 4 ++--
 projects/ad6676evb/zc706/system_constr.xdc | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc
index 4d650e118..cfde1a20c 100644
--- a/projects/ad6676evb/vc707/system_constr.xdc
+++ b/projects/ad6676evb/vc707/system_constr.xdc
@@ -30,8 +30,8 @@ set_property  -dict {PACKAGE_PIN  L42  IOSTANDARD LVCMOS18} [get_ports adc_agc4]
 
 # clocks
 
-create_clock -name rx_ref_clk   -period  3.30 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_ref_clk   -period   5.00 [get_ports rx_ref_clk_p]
+create_clock -name rx_div_clk   -period  10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc
index f5d2f91db..3e7474150 100644
--- a/projects/ad6676evb/zc706/system_constr.xdc
+++ b/projects/ad6676evb/zc706/system_constr.xdc
@@ -30,8 +30,8 @@ set_property  -dict {PACKAGE_PIN  AJ19  IOSTANDARD LVCMOS25} [get_ports adc_agc4
 
 # clocks
 
-create_clock -name rx_ref_clk   -period  3.30 [get_ports rx_ref_clk_p]
-create_clock -name rx_div_clk   -period  6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+create_clock -name rx_ref_clk   -period   5.00 [get_ports rx_ref_clk_p]
+create_clock -name rx_div_clk   -period  10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 

From c0b0f9b7e99b24996352ac34a2675645972a6c06 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 14 Dec 2016 17:38:54 +0200
Subject: [PATCH 812/972] ad6676evb: Connect SYS_REF to GPIO

---
 projects/ad6676evb/vc707/system_top.v | 1 +
 projects/ad6676evb/zc706/system_top.v | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v
index 017dd51e0..04ec673f4 100644
--- a/projects/ad6676evb/vc707/system_top.v
+++ b/projects/ad6676evb/vc707/system_top.v
@@ -219,6 +219,7 @@ module system_top (
     .I (rx_sysref),
     .O (rx_sysref_p),
     .OB (rx_sysref_n));
+  assign rx_sysref = gpio_o[48]
 
   OBUFDS i_obufds_rx_sync (
     .I (rx_sync),
diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v
index d873226f1..f62c5c4bd 100644
--- a/projects/ad6676evb/zc706/system_top.v
+++ b/projects/ad6676evb/zc706/system_top.v
@@ -193,6 +193,8 @@ module system_top (
     .I (rx_sysref),
     .O (rx_sysref_p),
     .OB (rx_sysref_n));
+  assign rx_sysref = gpio_o[48];
+
 
   OBUFDS i_obufds_rx_sync (
     .I (rx_sync),

From a00d9870be445956109c9f14d5e6a4a537d62cb7 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 16 Dec 2016 12:01:38 +0000
Subject: [PATCH 813/972] axi_ip_constr: Fix constraints

Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
---
 library/common/ad_axi_ip_constr.xdc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/common/ad_axi_ip_constr.xdc b/library/common/ad_axi_ip_constr.xdc
index f2a5eeac1..8fccb8018 100644
--- a/library/common/ad_axi_ip_constr.xdc
+++ b/library/common/ad_axi_ip_constr.xdc
@@ -16,5 +16,5 @@ set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data*        && I
 set_false_path -from [get_cells -hier -filter {name =~ *d_count_toggle_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_count_toggle_m1_reg && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {name =~ *d_count_hold*       && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_d_count*            && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {name =~ *up_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_count_toggle_m1_reg  && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *up_core_preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg     && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg     && IS_SEQUENTIAL}]
 

From 596d0fa3fb10d506a3650dbd51f8bc4411b919ab Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 16 Dec 2016 12:07:40 +0000
Subject: [PATCH 814/972] axi_ad9122: Add a constraint for a false path

---
 library/axi_ad9122/axi_ad9122_constr.xdc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/library/axi_ad9122/axi_ad9122_constr.xdc b/library/axi_ad9122/axi_ad9122_constr.xdc
index a8b4a0c99..6ca9c954f 100644
--- a/library/axi_ad9122/axi_ad9122_constr.xdc
+++ b/library/axi_ad9122/axi_ad9122_constr.xdc
@@ -1 +1,3 @@
 set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_status_m1_reg     && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ */axi_ad9122/*/i_core_rst_reg/rst_reg* && IS_SEQUENTIAL}] 
+               -to   [get_cells -hier -filter {name =~ */axi_ad9122/inst/i_if/i_serdes_out_clk/g_data[0].i_serdes && IS_SEQUENTIAL}]

From 8879218502358a83c2924192d1243f2f6b3143e3 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 13 Dec 2016 10:30:24 +0200
Subject: [PATCH 815/972] a5gte: Fixed timing violations

---
 projects/common/a5gte/system_top.v | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/projects/common/a5gte/system_top.v b/projects/common/a5gte/system_top.v
index cf2f47b8f..8891789e6 100644
--- a/projects/common/a5gte/system_top.v
+++ b/projects/common/a5gte/system_top.v
@@ -100,7 +100,8 @@ module system_top (
 
   reg     [ 4:0]  eth_tx_data_h_d;
   reg     [ 4:0]  phy_rx_data_h_d;
-
+  reg     [ 4:0]  phy_rx_data_h_d1;
+  reg     [ 4:0]  phy_rx_data_l_d;
   // RX path
 
   altera_pll #(
@@ -194,9 +195,10 @@ module system_top (
   always @(posedge phy_rx_clk)
   begin
     phy_rx_data_h_d <= phy_rx_data_h;
+    phy_rx_data_h_d1 <= phy_rx_data_h_d;
+    phy_rx_data_l_d <= phy_rx_data_l;
   end
 
-
   altddio_out #(
     .extend_oe_disable("OFF"),
     .intended_device_family("Arria V"),
@@ -207,8 +209,8 @@ module system_top (
     .power_up_high("OFF"),
     .width(5)
   ) eth_rx_path_out (
-    .datain_h (phy_rx_data_h_d),
-    .datain_l (phy_rx_data_l),
+    .datain_h (phy_rx_data_h_d1),
+    .datain_l (phy_rx_data_l_d),
     .outclock (phy_rx_clk),
     .dataout ({eth_rx_cntrl,eth_rx_data}),
     .aclr (~eth_phy_resetn),

From a228c05bd3da870cd2b67def527c97f63d78bd9f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Sat, 17 Dec 2016 11:12:10 +0200
Subject: [PATCH 816/972] common: Add a SYSREF generation module

The SYSREF generator is using a simple free running counter,
which runs on the JESD204 core clock. The period can be
configured using a parameter, it must respect the constraints
defined by the JESD204 standard.
The generator can be enabled through a GPIO line.
---
 library/common/ad_sysref_gen.v | 87 ++++++++++++++++++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 library/common/ad_sysref_gen.v

diff --git a/library/common/ad_sysref_gen.v b/library/common/ad_sysref_gen.v
new file mode 100644
index 000000000..0bf970890
--- /dev/null
+++ b/library/common/ad_sysref_gen.v
@@ -0,0 +1,87 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2016(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_sysref_gen (
+
+    input       core_clk,
+
+    input       sysref_en,
+    output reg  sysref_out
+);
+
+  // SYSREF period is multiple of core_clk, and has a duty cycle of 50%
+  // NOTE: if SYSREF always on (this is a JESD204 IP configuration),
+  // the period must be a correct multiple of the multiframe period
+  parameter    SYSREF_PERIOD = 128;
+
+  localparam   SYSREF_HALFPERIOD = SYSREF_PERIOD/2 - 1;
+
+  reg  [ 7:0]   counter;
+  reg           sysref_en_m1;
+  reg           sysref_en_m2;
+  reg           sysref_en_int;
+
+  // bring the enable signal to JESD core clock domain
+  always @(posedge core_clk) begin
+    sysref_en_m1 <= sysref_en;
+    sysref_en_m2 <= sysref_en_m1;
+    sysref_en_int <= sysref_en_m2;
+  end
+
+  // free running counter for periodic SYSREF generation
+  always @(posedge core_clk) begin
+    if (sysref_en_int) begin
+      counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1 : 0;
+    end else begin
+      counter <= 0;
+    end
+  end
+
+  // generate SYSREF
+  always @(posedge core_clk) begin
+    if (counter == SYSREF_HALFPERIOD) begin
+      sysref_out <= ~sysref_out;
+    end else begin
+      sysref_out <= 1'b0;
+    end
+  end
+
+endmodule

From 67390c2a953be29694ba1e5fbc0815bcaf9c6f6c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Dec 2016 10:52:25 +0000
Subject: [PATCH 817/972] ad6676evb: Update projects with ad_sysref_gen

---
 projects/ad6676evb/common/ad6676evb_bd.tcl  |  2 ++
 projects/ad6676evb/vc707/Makefile           |  1 +
 projects/ad6676evb/vc707/system_constr.xdc  |  3 +++
 projects/ad6676evb/vc707/system_project.tcl |  1 +
 projects/ad6676evb/vc707/system_top.v       |  8 +++++++-
 projects/ad6676evb/zc706/Makefile           |  2 ++
 projects/ad6676evb/zc706/system_constr.xdc  |  3 +++
 projects/ad6676evb/zc706/system_project.tcl |  1 +
 projects/ad6676evb/zc706/system_top.v       | 11 ++++++++---
 9 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl
index 7c1f17b72..b10522601 100644
--- a/projects/ad6676evb/common/ad6676evb_bd.tcl
+++ b/projects/ad6676evb/common/ad6676evb_bd.tcl
@@ -44,6 +44,7 @@ set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad6676_
 # reference clocks & resets
 
 create_bd_port -dir I rx_ref_clk_0
+create_bd_port -dir O rx_core_clk
 
 ad_xcvrpll  rx_ref_clk_0 util_ad6676_xcvr/qpll_ref_clk_*
 ad_xcvrpll  rx_ref_clk_0 util_ad6676_xcvr/cpll_ref_clk_*
@@ -56,6 +57,7 @@ ad_connect  sys_cpu_clk util_ad6676_xcvr/up_clk
 
 ad_xcvrcon  util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd
 ad_connect  util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk
+ad_connect  util_ad6676_xcvr/rx_out_clk_0 rx_core_clk
 ad_connect  axi_ad6676_jesd/rx_start_of_frame axi_ad6676_core/rx_sof
 ad_connect  axi_ad6676_jesd/rx_tdata axi_ad6676_core/rx_data
 ad_connect  util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/adc_clk
diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile
index 3ecc4452d..d7ab4a93c 100644
--- a/projects/ad6676evb/vc707/Makefile
+++ b/projects/ad6676evb/vc707/Makefile
@@ -17,6 +17,7 @@ M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc
index cfde1a20c..e3c798d6d 100644
--- a/projects/ad6676evb/vc707/system_constr.xdc
+++ b/projects/ad6676evb/vc707/system_constr.xdc
@@ -35,3 +35,6 @@ create_clock -name rx_div_clk   -period  10.00 [get_pins i_system_wrapper/system
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
+set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+
diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl
index 8ee83f3a3..ad7d4e5c0 100644
--- a/projects/ad6676evb/vc707/system_project.tcl
+++ b/projects/ad6676evb/vc707/system_project.tcl
@@ -10,6 +10,7 @@ adi_project_files ad6676evb_vc707 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 adi_project_run ad6676evb_vc707
diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v
index 04ec673f4..6a5f4a892 100644
--- a/projects/ad6676evb/vc707/system_top.v
+++ b/projects/ad6676evb/vc707/system_top.v
@@ -200,6 +200,7 @@ module system_top (
   wire            rx_ref_clk;
   wire            rx_sysref;
   wire            rx_sync;
+  wire            rx_clk;
 
   // default logic
 
@@ -219,7 +220,6 @@ module system_top (
     .I (rx_sysref),
     .O (rx_sysref_p),
     .OB (rx_sysref_n));
-  assign rx_sysref = gpio_o[48]
 
   OBUFDS i_obufds_rx_sync (
     .I (rx_sync),
@@ -247,6 +247,11 @@ module system_top (
     .dio_o (gpio_i[20:0]),
     .dio_p (gpio_bd));
 
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[48]),
+    .sysref_out (rx_sysref));
+
   system_wrapper i_system_wrapper (
     .ddr3_addr (ddr3_addr),
     .ddr3_ba (ddr3_ba),
@@ -297,6 +302,7 @@ module system_top (
     .rx_ref_clk_0 (rx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (rx_sysref),
+    .rx_core_clk (rx_clk),
     .sgmii_rxn (sgmii_rxn),
     .sgmii_rxp (sgmii_rxp),
     .sgmii_txn (sgmii_txn),
diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile
index fd9ba7c07..01f2c152a 100644
--- a/projects/ad6676evb/zc706/Makefile
+++ b/projects/ad6676evb/zc706/Makefile
@@ -16,6 +16,8 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc
index 3e7474150..54b6d22d3 100644
--- a/projects/ad6676evb/zc706/system_constr.xdc
+++ b/projects/ad6676evb/zc706/system_constr.xdc
@@ -35,3 +35,6 @@ create_clock -name rx_div_clk   -period  10.00 [get_pins i_system_wrapper/system
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
+set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+
diff --git a/projects/ad6676evb/zc706/system_project.tcl b/projects/ad6676evb/zc706/system_project.tcl
index 22443724f..c5982e29f 100644
--- a/projects/ad6676evb/zc706/system_project.tcl
+++ b/projects/ad6676evb/zc706/system_project.tcl
@@ -10,6 +10,7 @@ adi_project_files ad6676evb_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 adi_project_run ad6676evb_zc706
diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v
index f62c5c4bd..fc387b1d8 100644
--- a/projects/ad6676evb/zc706/system_top.v
+++ b/projects/ad6676evb/zc706/system_top.v
@@ -177,8 +177,9 @@ module system_top (
   wire            spi1_mosi;
   wire            spi1_miso;
   wire            rx_ref_clk;
-  wire            rx_sysref;
   wire            rx_sync;
+  wire            rx_sysref;
+  wire            rx_clk;
 
   // instantiations
 
@@ -193,8 +194,6 @@ module system_top (
     .I (rx_sysref),
     .O (rx_sysref_p),
     .OB (rx_sysref_n));
-  assign rx_sysref = gpio_o[48];
-
 
   OBUFDS i_obufds_rx_sync (
     .I (rx_sync),
@@ -227,6 +226,11 @@ module system_top (
     .dio_o (gpio_i[14:0]),
     .dio_p (gpio_bd));
 
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[48]),
+    .sysref_out (rx_sysref));
+
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),
@@ -279,6 +283,7 @@ module system_top (
     .rx_ref_clk_0 (rx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (rx_sysref),
+    .rx_core_clk (rx_clk),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),

From 0c42e04bc337206972d7f47dbfbb8a247cdaf3f6 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Dec 2016 12:16:05 +0000
Subject: [PATCH 818/972] fmcadc2: Integrate ad_sysref_gen into the project

---
 projects/fmcadc2/common/fmcadc2_bd.tcl    |  6 ++---
 projects/fmcadc2/vc707/Makefile           |  1 +
 projects/fmcadc2/vc707/system_constr.xdc  |  5 ++--
 projects/fmcadc2/vc707/system_project.tcl |  1 +
 projects/fmcadc2/vc707/system_top.v       | 29 +++++++----------------
 projects/fmcadc2/zc706/Makefile           |  1 +
 projects/fmcadc2/zc706/system_constr.xdc  |  4 ++++
 projects/fmcadc2/zc706/system_project.tcl |  1 +
 projects/fmcadc2/zc706/system_top.v       | 24 +++++++------------
 9 files changed, 31 insertions(+), 41 deletions(-)

diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl
index cb9cdc59f..ab24416bb 100644
--- a/projects/fmcadc2/common/fmcadc2_bd.tcl
+++ b/projects/fmcadc2/common/fmcadc2_bd.tcl
@@ -39,7 +39,7 @@ set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc2
 # reference clocks & resets
 
 create_bd_port -dir I rx_ref_clk_0
-create_bd_port -dir O rx_clk
+create_bd_port -dir O rx_core_clk
 
 ad_xcvrpll  rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_*
 ad_xcvrpll  rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_*
@@ -47,19 +47,19 @@ ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_*
 ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_*
 ad_connect  sys_cpu_resetn util_fmcadc2_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_fmcadc2_xcvr/up_clk
-ad_connect  util_fmcadc2_xcvr/rx_out_clk_0 rx_clk
 
 # connections (adc)
 
 ad_xcvrcon  util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd
 ad_connect  util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk
+ad_connect  util_fmcadc2_xcvr/rx_out_clk_0 rx_core_clk
 ad_connect  axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data
 ad_connect  axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof
 ad_connect  sys_cpu_clk axi_ad9625_fifo/dma_clk
 ad_connect  sys_cpu_clk axi_ad9625_dma/s_axis_aclk
 ad_connect  sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
 ad_connect  axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk
-ad_connect  axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst
+ad_connect  axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
 ad_connect  axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr
 ad_connect  axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
 ad_connect  axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile
index 826055268..ab081ce8b 100644
--- a/projects/fmcadc2/vc707/Makefile
+++ b/projects/fmcadc2/vc707/Makefile
@@ -19,6 +19,7 @@ M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc
index 0a29e3cd0..b0a63362c 100644
--- a/projects/fmcadc2/vc707/system_constr.xdc
+++ b/projects/fmcadc2/vc707/system_constr.xdc
@@ -42,5 +42,6 @@ create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
-set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_sysref_m*}]
-set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_m*  && IS_SEQUENTIAL}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+
diff --git a/projects/fmcadc2/vc707/system_project.tcl b/projects/fmcadc2/vc707/system_project.tcl
index a9ca97db1..2d69eb87d 100644
--- a/projects/fmcadc2/vc707/system_project.tcl
+++ b/projects/fmcadc2/vc707/system_project.tcl
@@ -11,6 +11,7 @@ adi_project_files fmcadc2_vc707 [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 set_property is_enabled false [get_files  *system_axi*_spi*.xdc]
diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v
index f69d887c6..be9a8bf87 100644
--- a/projects/fmcadc2/vc707/system_top.v
+++ b/projects/fmcadc2/vc707/system_top.v
@@ -181,13 +181,6 @@ module system_top (
   output            spi_adf4355_le_or_clk;
   inout             spi_adf4355_ce_or_sdio;
 
-  // internal registers
-
-  reg             rx_sysref = 'd0;
-  reg             rx_sysref_m1 = 'd0;
-  reg             rx_sysref_m2 = 'd0;
-  reg             rx_sysref_m3 = 'd0;
-
   // internal signals
 
   wire    [63:0]    gpio_i;
@@ -198,19 +191,14 @@ module system_top (
   wire              spi_miso;
   wire              rx_ref_clk;
   wire              rx_sync;
+  wire              rx_sysref;
+  wire              rx_clk;
 
   // default logic
 
   assign fan_pwm = 1'b1;
   assign iic_rstn = 1'b1;
 
-  // sysref internal
-
-  always @(posedge rx_clk) begin
-    rx_sysref_m1 <= gpio_o[34];
-    rx_sysref_m2 <= rx_sysref_m1;
-    rx_sysref <= rx_sysref_m2;
-  end
 
   // instantiations
 
@@ -231,10 +219,6 @@ module system_top (
     .O (rx_sync_p),
     .OB (rx_sync_n));
 
-    // spi
-
-    assign gpio_i[37:36] = gpio_o[37:36];
-
   fmcadc2_spi i_fmcadc2_spi (
     .spi_adf4355 (gpio_o[36]),
     .spi_adf4355_ce (gpio_o[37]),
@@ -262,6 +246,11 @@ module system_top (
     .dio_o (gpio_i[20:0]),
     .dio_p (gpio_bd));
 
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[34]),
+    .sysref_out (rx_sysref));
+
   system_wrapper i_system_wrapper (
     .ddr3_addr (ddr3_addr),
     .ddr3_ba (ddr3_ba),
@@ -323,6 +312,7 @@ module system_top (
     .rx_ref_clk_0 (rx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (rx_sysref),
+    .rx_core_clk (rx_clk),
     .sgmii_rxn (sgmii_rxn),
     .sgmii_rxp (sgmii_rxp),
     .sgmii_txn (sgmii_txn),
@@ -338,8 +328,7 @@ module system_top (
     .sys_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
     .uart_sin (uart_sin),
-    .uart_sout (uart_sout),
-    .rx_clk (rx_clk));
+    .uart_sout (uart_sout));
 
 endmodule
 
diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile
index 3aff736fa..f90b83008 100644
--- a/projects/fmcadc2/zc706/Makefile
+++ b/projects/fmcadc2/zc706/Makefile
@@ -21,6 +21,7 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
diff --git a/projects/fmcadc2/zc706/system_constr.xdc b/projects/fmcadc2/zc706/system_constr.xdc
index 89fc7716d..f811cf7de 100644
--- a/projects/fmcadc2/zc706/system_constr.xdc
+++ b/projects/fmcadc2/zc706/system_constr.xdc
@@ -41,3 +41,7 @@ create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
 create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+
diff --git a/projects/fmcadc2/zc706/system_project.tcl b/projects/fmcadc2/zc706/system_project.tcl
index 4f65ab5fb..777034487 100644
--- a/projects/fmcadc2/zc706/system_project.tcl
+++ b/projects/fmcadc2/zc706/system_project.tcl
@@ -10,6 +10,7 @@ adi_project_files fmcadc2_zc706 [list \
   "system_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v
index 7d5ed8355..714fdd451 100644
--- a/projects/fmcadc2/zc706/system_top.v
+++ b/projects/fmcadc2/zc706/system_top.v
@@ -195,11 +195,6 @@ module system_top (
   output          spi_adf4355_le_or_clk;
   inout           spi_adf4355_ce_or_sdio;
 
-  // internal registers
-
-  reg             rx_sysref = 'd0;
-  reg             rx_sysref_d = 'd0;
-
   // internal signals
 
   wire    [63:0]  gpio_i;
@@ -216,13 +211,7 @@ module system_top (
   wire            rx_ref_clk;
   wire            rx_sync;
   wire            rx_clk;
-
-  // sysref internal
-
-  always @(posedge rx_clk) begin
-    rx_sysref_d <= gpio_o[34];
-    rx_sysref <= rx_sysref_d;
-  end
+  wire            rx_sysref;
 
   // instantiations
 
@@ -245,8 +234,6 @@ module system_top (
 
   // spi
 
-  assign gpio_i[37:36] = gpio_o[37:36];
-
   fmcadc2_spi i_fmcadc2_spi (
     .spi_adf4355 (gpio_o[36]),
     .spi_adf4355_ce (gpio_o[37]),
@@ -274,6 +261,11 @@ module system_top (
     .dio_o (gpio_i[14:0]),
     .dio_p (gpio_bd));
 
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[34]),
+    .sysref_out (rx_sysref));
+
   system_wrapper i_system_wrapper (
     .ddr3_addr (ddr3_addr),
     .ddr3_ba (ddr3_ba),
@@ -353,6 +345,7 @@ module system_top (
     .rx_ref_clk_0 (rx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (rx_sysref),
+    .rx_core_clk (rx_clk),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),
@@ -374,8 +367,7 @@ module system_top (
     .spi1_sdo_o (spi1_mosi),
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
-    .sys_rst (sys_rst),
-    .rx_clk (rx_clk));
+    .sys_rst (sys_rst));
 
 endmodule
 

From 8d799d03169ad22120ad7e8486c40f5ff33b4821 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Dec 2016 13:37:29 +0000
Subject: [PATCH 819/972] fmcjesdadc1: Intergrate ad_sysref_gen into project

---
 projects/fmcjesdadc1/a5gt/Makefile            |    1 +
 .../fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld     |   14 +
 projects/fmcjesdadc1/a5gt/serv_req_info.txt   |    8 +
 projects/fmcjesdadc1/a5gt/system_bd.qsys      | 2404 +++++++++++++++++
 .../system_bd_sys_ddr3_cntrl_p0_summary.csv   |   34 +
 projects/fmcjesdadc1/a5gt/system_project.tcl  |    1 +
 .../fmcjesdadc1/a5gt/system_qsys_script.tcl   |    4 +
 projects/fmcjesdadc1/a5gt/system_top.v        |   28 +-
 projects/fmcjesdadc1/a5soc/Makefile           |    1 +
 .../fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld   |    9 +
 projects/fmcjesdadc1/a5soc/system_bd.qsys     | 1585 +++++++++++
 projects/fmcjesdadc1/a5soc/system_project.tcl |    1 +
 .../fmcjesdadc1/a5soc/system_qsys_script.tcl  |    4 +
 projects/fmcjesdadc1/a5soc/system_top.v       |   29 +-
 .../fmcjesdadc1/common/fmcjesdadc1_bd.tcl     |    3 +
 projects/fmcjesdadc1/kc705/Makefile           |    1 +
 projects/fmcjesdadc1/kc705/system_constr.xdc  |    3 +
 projects/fmcjesdadc1/kc705/system_project.tcl |    1 +
 projects/fmcjesdadc1/kc705/system_top.v       |    8 +
 projects/fmcjesdadc1/vc707/Makefile           |    1 +
 projects/fmcjesdadc1/vc707/system_constr.xdc  |    4 +
 projects/fmcjesdadc1/vc707/system_project.tcl |    1 +
 projects/fmcjesdadc1/vc707/system_top.v       |    8 +
 projects/fmcjesdadc1/zc706/Makefile           |    1 +
 projects/fmcjesdadc1/zc706/system_constr.xdc  |   13 +-
 projects/fmcjesdadc1/zc706/system_project.tcl |    1 +
 projects/fmcjesdadc1/zc706/system_top.v       |    8 +
 27 files changed, 4135 insertions(+), 41 deletions(-)
 create mode 100644 projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld
 create mode 100644 projects/fmcjesdadc1/a5gt/serv_req_info.txt
 create mode 100644 projects/fmcjesdadc1/a5gt/system_bd.qsys
 create mode 100644 projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv
 create mode 100644 projects/fmcjesdadc1/a5gt/system_qsys_script.tcl
 create mode 100644 projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld
 create mode 100644 projects/fmcjesdadc1/a5soc/system_bd.qsys
 create mode 100644 projects/fmcjesdadc1/a5soc/system_qsys_script.tcl

diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index 1f0347e13..a526b8885 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -22,6 +22,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_qsys.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
 M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
 M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
diff --git a/projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld b/projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld
new file mode 100644
index 000000000..21406e592
--- /dev/null
+++ b/projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld
@@ -0,0 +1,14 @@
+<sld_project_info>
+  <sld_infos>
+    <sld_info hpath="system_bd:i_system_bd" name="i_system_bd">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME system_bd HAS_SOPCINFO 1 GENERATION_ID 1482148783"/>
+      </assignment_values>
+    </sld_info>
+    <sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
+      </assignment_values>
+    </sld_info>
+  </sld_infos>
+</sld_project_info>
diff --git a/projects/fmcjesdadc1/a5gt/serv_req_info.txt b/projects/fmcjesdadc1/a5gt/serv_req_info.txt
new file mode 100644
index 000000000..98d3a1b02
--- /dev/null
+++ b/projects/fmcjesdadc1/a5gt/serv_req_info.txt
@@ -0,0 +1,8 @@
+<internal_error>
+	<executable>quartus_sta</executable>
+	<sub_system>MEM</sub_system>
+	<error>*** Fatal Error: Out of memory in module quartus_sta (4171 megabytes used)</error>
+	<date>Mon Dec 19 12:41:45 2016</date>
+	<version>Version 16.0.2 Build 222 07/20/2016 SJ Standard Edition</version>
+</internal_error>
+
diff --git a/projects/fmcjesdadc1/a5gt/system_bd.qsys b/projects/fmcjesdadc1/a5gt/system_bd.qsys
new file mode 100644
index 000000000..2da679b31
--- /dev/null
+++ b/projects/fmcjesdadc1/a5gt/system_bd.qsys
@@ -0,0 +1,2404 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element ad9250_adcfifo
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element avl_ad9250_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element avl_phy_reconfig
+   {
+      datum _sortIndex
+      {
+         value = "26";
+         type = "int";
+      }
+   }
+   element axi_ad9250_core_0
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element axi_ad9250_core_1
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element axi_ad9250_dma
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
+   element axi_ad9250_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+   }
+   element rx_core_clk
+   {
+      datum _sortIndex
+      {
+         value = "25";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_cpu
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element sys_ddr3_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element sys_dma_clk
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element sys_ethernet
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element sys_ethernet_dma_rx
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element sys_ethernet_dma_tx
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element sys_gpio_bd
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element sys_gpio_in
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element sys_gpio_out
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element sys_pll
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element sys_spi
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element sys_timer_1
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element sys_timer_2
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element sys_tlb_mem
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sys_uart
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element util_ad9250_cpack
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5AGTFD7K3F40I3" />
+ <parameter name="deviceFamily" value="Arria V" />
+ <parameter name="deviceSpeedGrade" value="3_H3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="rx_core_clk"
+   internal="rx_core_clk.out_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="rx_data_0"
+   internal="avl_ad9250_xcvr.rx_data_0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_1"
+   internal="avl_ad9250_xcvr.rx_data_1"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_2"
+   internal="avl_ad9250_xcvr.rx_data_2"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_3"
+   internal="avl_ad9250_xcvr.rx_data_3"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_data"
+   internal="avl_ad9250_xcvr.ip_data"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="rx_ip_data_0"
+   internal="axi_ad9250_core_0.if_rx_data"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="rx_ip_data_1"
+   internal="axi_ad9250_core_1.if_rx_data"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="rx_ip_sof"
+   internal="avl_ad9250_xcvr.ip_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_sof_0"
+   internal="axi_ad9250_core_0.if_rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_sof_1"
+   internal="axi_ad9250_core_1.if_rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ref_clk"
+   internal="avl_ad9250_xcvr.ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="rx_sync"
+   internal="avl_ad9250_xcvr.sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_sysref"
+   internal="avl_ad9250_xcvr.sysref"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_125m_clk"
+   internal="sys_pll.outclk0"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_25m_clk"
+   internal="sys_pll.outclk1"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_2m5_clk"
+   internal="sys_pll.outclk2"
+   type="clock"
+   dir="start" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_mem"
+   internal="sys_ddr3_cntrl.memory"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_oct"
+   internal="sys_ddr3_cntrl.oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_mdio"
+   internal="sys_ethernet.mac_mdio_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_rgmii"
+   internal="sys_ethernet.mac_rgmii_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_rx_clk"
+   internal="sys_ethernet.pcs_mac_rx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_ethernet_status"
+   internal="sys_ethernet.mac_status_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_tx_clk"
+   internal="sys_ethernet.pcs_mac_tx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_gpio_bd"
+   internal="sys_gpio_bd.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_in"
+   internal="sys_gpio_in.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_out"
+   internal="sys_gpio_out.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_pll_locked"
+   internal="sys_pll.locked"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_rst" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
+ <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
+ <module name="ad9250_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
+  <parameter name="ADC_DATA_WIDTH" value="128" />
+  <parameter name="DMA_ADDRESS_WIDTH" value="16" />
+  <parameter name="DMA_DATA_WIDTH" value="128" />
+  <parameter name="DMA_READY_ENABLE" value="1" />
+ </module>
+ <module name="avl_ad9250_xcvr" kind="avl_adxcvr" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="CORECLK_FREQUENCY" value="125.0" />
+  <parameter name="DEVICE_FAMILY" value="Arria V" />
+  <parameter name="FRM_BCNT" value="4" />
+  <parameter name="FRM_SCNT" value="1" />
+  <parameter name="HD" value="0" />
+  <parameter name="ID" value="1" />
+  <parameter name="LANE_RATE" value="5000.0" />
+  <parameter name="MF_FCNT" value="32" />
+  <parameter name="NUM_OF_CONVS" value="4" />
+  <parameter name="NUM_OF_LANES" value="4" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="PLLCLK_FREQUENCY" value="2500.0" />
+  <parameter name="REFCLK_FREQUENCY" value="250.0" />
+  <parameter name="SYSCLK_FREQUENCY" value="100.0" />
+  <parameter name="TX_OR_RX_N" value="0" />
+ </module>
+ <module
+   name="avl_phy_reconfig"
+   kind="alt_xcvr_reconfig"
+   version="16.0"
+   enabled="1">
+  <parameter name="ber_en" value="0" />
+  <parameter name="device_family" value="Arria V" />
+  <parameter name="enable_adce" value="0" />
+  <parameter name="enable_analog" value="1" />
+  <parameter name="enable_dcd" value="0" />
+  <parameter name="enable_dcd_power_up" value="1" />
+  <parameter name="enable_dfe" value="0" />
+  <parameter name="enable_eyemon" value="0" />
+  <parameter name="enable_mif" value="0" />
+  <parameter name="enable_offset" value="1" />
+  <parameter name="gui_cal_status_port" value="false" />
+  <parameter name="gui_enable_pll" value="0" />
+  <parameter name="gui_split_sizes" value="1,1,1,1" />
+  <parameter name="number_of_reconfig_interfaces" value="4" />
+ </module>
+ <module name="axi_ad9250_core_0" kind="axi_ad9250" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="1" />
+  <parameter name="ID" value="0" />
+ </module>
+ <module name="axi_ad9250_core_1" kind="axi_ad9250" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="1" />
+  <parameter name="ID" value="0" />
+ </module>
+ <module name="axi_ad9250_dma" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="0" />
+  <parameter name="DMA_TYPE_SRC" value="1" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
+ </module>
+ <module name="axi_ad9250_xcvr" kind="axi_adxcvr" version="1.0" enabled="1">
+  <parameter name="ID" value="1" />
+  <parameter name="NUM_OF_LANES" value="4" />
+  <parameter name="TX_OR_RX_N" value="0" />
+ </module>
+ <module
+   name="rx_core_clk"
+   kind="altera_clock_bridge"
+   version="16.0"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="125" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_clk" kind="clock_source" version="16.0" enabled="1">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="DEASSERT" />
+ </module>
+ <module name="sys_cpu" kind="altera_nios2_gen2" version="16.0" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='avl_phy_reconfig.reconfig_mgmt' start='0x10010000' end='0x10010200' type='alt_xcvr_reconfig.reconfig_mgmt' /><slave name='avl_ad9250_xcvr.core_pll_reconfig' start='0x10018000' end='0x10018100' type='avl_adxcvr.core_pll_reconfig' /><slave name='avl_ad9250_xcvr.ip_reconfig' start='0x10019000' end='0x10019400' type='avl_adxcvr.ip_reconfig' /><slave name='axi_ad9250_xcvr.s_axi' start='0x10020000' end='0x10030000' type='axi_adxcvr.s_axi' /><slave name='axi_ad9250_core_0.s_axi' start='0x10050000' end='0x10060000' type='axi_ad9250.s_axi' /><slave name='axi_ad9250_core_1.s_axi' start='0x10060000' end='0x10070000' type='axi_ad9250.s_axi' /><slave name='axi_ad9250_dma.s_axi' start='0x10070000' end='0x10074000' type='axi_dmac.s_axi' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer_1.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="1" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="32768" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="Arria V" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="exceptionSlave" value="sys_ddr3_cntrl.avl" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="1" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="32768" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="2303" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="4096" />
+  <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
+  <parameter name="mmu_enabled" value="true" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="3" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave" value="sys_ddr3_cntrl.avl" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="false" />
+  <parameter name="setting_tmr_output_disable" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="0" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+   name="sys_ddr3_cntrl"
+   kind="altera_mem_if_ddr3_emif"
+   version="16.0"
+   enabled="1">
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="AVL_MAX_SIZE" value="256" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="MEM_CLK_FREQ" value="400.0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="666.667" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DQ_WIDTH" value="64" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="12" />
+  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
+  <parameter name="MEM_RTT_WR" value="RZQ/4" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_TCL" value="11" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_VENDOR" value="Micron" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="MEM_WTCL" value="8" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="RATE" value="Quarter" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="REF_CLK_FREQ" value="100.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="SPEED_GRADE" value="3" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="TIMING_TDQSCK" value="255" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+ </module>
+ <module name="sys_dma_clk" kind="clock_source" version="16.0" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="100000000" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module name="sys_ethernet" kind="altera_eth_tse" version="16.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="core_variation" value="MAC_ONLY" />
+  <parameter name="deviceFamilyName" value="Arria V" />
+  <parameter name="eg_addr" value="11" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="enable_gmii_loopback" value="false" />
+  <parameter name="enable_hd_logic" value="true" />
+  <parameter name="enable_mac_flow_ctrl" value="true" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="enable_sgmii" value="false" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="ing_addr" value="11" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="mdio_clk_div" value="30" />
+  <parameter name="nf_phyip_rcfg_enable" value="false" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="transceiver_type" value="NONE" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module
+   name="sys_ethernet_dma_rx"
+   kind="altera_msgdma"
+   version="16.0"
+   enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="BURST_ENABLE" value="1" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="256" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
+  <parameter name="ENHANCED_FEATURES" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="64" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="2" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="0" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="sys_ethernet_dma_tx"
+   kind="altera_msgdma"
+   version="16.0"
+   enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="BURST_ENABLE" value="1" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="256" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
+  <parameter name="ENHANCED_FEATURES" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="64" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="sys_gpio_bd"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_in"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_out"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_id"
+   kind="altera_avalon_sysid_qsys"
+   version="16.0"
+   enabled="1">
+  <parameter name="id" value="182193580" />
+ </module>
+ <module
+   name="sys_int_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="16.0"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">system_bd_sys_int_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="163840" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="sys_pll" kind="altera_pll" version="16.0" enabled="1">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device" value="5AGTFD7K3F40I3" />
+  <parameter name="device_family" value="Arria V" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_device_speed_grade" value="1" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_number_of_clocks" value="3" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_output_clock_frequency0" value="125.0" />
+  <parameter name="gui_output_clock_frequency1" value="25.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="2.5" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="Off" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="100.0" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_locked" value="true" />
+ </module>
+ <module name="sys_spi" kind="altera_avalon_spi" version="16.0" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="0" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="100000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="8" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="128000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
+ <module
+   name="sys_timer_1"
+   kind="altera_avalon_timer"
+   version="16.0"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_timer_2"
+   kind="altera_avalon_timer"
+   version="16.0"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_tlb_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="16.0"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">system_bd_sys_tlb_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="163840" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module
+   name="sys_uart"
+   kind="altera_avalon_jtag_uart"
+   version="16.0"
+   enabled="1">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clkFreq" value="100000000" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module name="util_ad9250_cpack" kind="util_cpack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814f0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet.control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814e8" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="avl_ad9250_xcvr.core_pll_reconfig">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10018000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181480" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10180800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.descriptor_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181440" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.descriptor_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181460" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="avl_ad9250_xcvr.ip_reconfig">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10019000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="avl_phy_reconfig.reconfig_mgmt">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.response">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_timer_1.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181420" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_timer_2.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181520" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_gpio_bd.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_gpio_in.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_gpio_out.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181500" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9250_xcvr.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9250_core_0.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10050000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9250_core_1.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10060000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9250_dma.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10070000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_spi.spi_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.instruction_master"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.instruction_master"
+   end="sys_cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10180800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.instruction_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="axi_ad9250_dma.m_dest_axi"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_ethernet_dma_tx.mm_read"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_ethernet_dma_rx.mm_write"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.tightly_coupled_data_master_0"
+   end="sys_tlb_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.tightly_coupled_instruction_master_0"
+   end="sys_tlb_mem.s2">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="16.0"
+   start="sys_ethernet.receive"
+   end="sys_ethernet_dma_rx.st_sink" />
+ <connection
+   kind="avalon_streaming"
+   version="16.0"
+   start="sys_ethernet_dma_tx.st_source"
+   end="sys_ethernet.transmit" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_ddr3_cntrl.afi_clk"
+   end="sys_dma_clk.clk_in" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_cpu.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_id.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_timer_1.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_timer_2.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_uart.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_bd.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_in.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_gpio_out.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_spi.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_tlb_mem.clk1" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_tlb_mem.clk2" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet_dma_rx.clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet_dma_tx.clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet.control_port_clock_connection" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="ad9250_adcfifo.if_dma_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="axi_ad9250_dma.if_s_axis_aclk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="axi_ad9250_dma.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="avl_phy_reconfig.mgmt_clk_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ddr3_cntrl.pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet.receive_clock_connection" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_pll.refclk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9250_xcvr.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9250_core_0.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9250_core_1.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9250_dma.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="avl_ad9250_xcvr.sys_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet.transmit_clock_connection" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="util_ad9250_cpack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="ad9250_adcfifo.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="axi_ad9250_core_0.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="axi_ad9250_core_1.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="rx_core_clk.in_clk" />
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_core_0.adc_ch_0"
+   end="util_ad9250_cpack.adc_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_core_1.adc_ch_0"
+   end="util_ad9250_cpack.adc_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_core_0.adc_ch_1"
+   end="util_ad9250_cpack.adc_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_core_1.adc_ch_1"
+   end="util_ad9250_cpack.adc_ch_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch0_0_to_xcvr"
+   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch1_1_to_xcvr"
+   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch2_2_to_xcvr"
+   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch3_3_to_xcvr"
+   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_xcvr.core_pll_locked"
+   end="avl_ad9250_xcvr.core_pll_locked">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="util_ad9250_cpack.if_adc_data"
+   end="ad9250_adcfifo.if_adc_wdata">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="util_ad9250_cpack.if_adc_valid"
+   end="ad9250_adcfifo.if_adc_wr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_adc_wovf"
+   end="axi_ad9250_core_0.if_adc_dovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_dma_wdata"
+   end="axi_ad9250_dma.if_s_axis_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_dma_wr"
+   end="axi_ad9250_dma.if_s_axis_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_dma_wready"
+   end="axi_ad9250_dma.if_s_axis_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_dma_xfer_req"
+   end="axi_ad9250_dma.if_s_axis_xfer_req">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_0"
+   end="avl_phy_reconfig.ch0_0_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_1"
+   end="avl_phy_reconfig.ch1_1_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_2"
+   end="avl_phy_reconfig.ch2_2_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_3"
+   end="avl_phy_reconfig.ch3_3_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.ready"
+   end="axi_ad9250_xcvr.ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_ethernet_dma_rx.csr_irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_ethernet_dma_tx.csr_irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="axi_ad9250_dma.interrupt_sender">
+  <parameter name="irqNumber" value="11" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_uart.irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_timer_2.irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_timer_1.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_gpio_in.irq">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_gpio_bd.irq">
+  <parameter name="irqNumber" value="6" />
+ </connection>
+ <connection kind="interrupt" version="16.0" start="sys_cpu.irq" end="sys_spi.irq">
+  <parameter name="irqNumber" value="7" />
+ </connection>
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_ddr3_cntrl.afi_reset"
+   end="sys_dma_clk.clk_in_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_cntrl.global_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="util_ad9250_cpack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_dma_clk.clk_reset"
+   end="util_ad9250_cpack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="ad9250_adcfifo.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_dma_clk.clk_reset"
+   end="ad9250_adcfifo.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_dma_clk.clk_reset"
+   end="axi_ad9250_dma.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="avl_phy_reconfig.mgmt_rst_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_pll.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_id.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_timer_1.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_timer_2.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_uart.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_bd.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_in.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_out.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_spi.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_int_mem.reset1" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_tlb_mem.reset1" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_tlb_mem.reset2" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet.reset_connection" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet_dma_rx.reset_n" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet_dma_tx.reset_n" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_xcvr.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_core_0.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_core_1.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_dma.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_cntrl.soft_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="avl_ad9250_xcvr.sys_resetn" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_cpu.debug_reset_request"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="axi_ad9250_xcvr.if_up_rst"
+   end="avl_ad9250_xcvr.rst" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
+</system>
diff --git a/projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv b/projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv
new file mode 100644
index 000000000..181e3cf9c
--- /dev/null
+++ b/projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv
@@ -0,0 +1,34 @@
+Core: system_bd_sys_ddr3_cntrl_p0 - Instance: i_system_bd|sys_ddr3_cntrl
+Path, Setup Margin, Hold Margin
+"Address Command (Slow 1150mV 100C Model)",0.436,0.635
+"Bus Turnaround Time (Slow 1150mV 100C Model)",5.495,--
+"Core (Slow 1150mV 100C Model)",0.379,0.223
+"Core Recovery/Removal (Slow 1150mV 100C Model)",2.083,0.531
+"DQS vs CK (Slow 1150mV 100C Model)",0.571,0.601
+"Postamble (Slow 1150mV 100C Model)",0.52,0.52
+"Read Capture (Slow 1150mV 100C Model)",0.256,0.245
+"Write (Slow 1150mV 100C Model)",0.358,0.358
+"Address Command (Slow 1150mV -40C Model)",0.522,0.579
+"Bus Turnaround Time (Slow 1150mV -40C Model)",5.599,--
+"Core (Slow 1150mV -40C Model)",0.713,0.163
+"Core Recovery/Removal (Slow 1150mV -40C Model)",2.462,0.454
+"DQS vs CK (Slow 1150mV -40C Model)",0.594,0.645
+"Postamble (Slow 1150mV -40C Model)",0.506,0.506
+"Read Capture (Slow 1150mV -40C Model)",0.29,0.279
+"Write (Slow 1150mV -40C Model)",0.382,0.382
+"Address Command (Fast 1150mV 100C Model)",0.807,0.54
+"Bus Turnaround Time (Fast 1150mV 100C Model)",5.73,--
+"Core (Fast 1150mV 100C Model)",1.331,0.154
+"Core Recovery/Removal (Fast 1150mV 100C Model)",2.959,0.328
+"DQS vs CK (Fast 1150mV 100C Model)",0.641,0.71
+"Postamble (Fast 1150mV 100C Model)",0.685,0.685
+"Read Capture (Fast 1150mV 100C Model)",0.339,0.331
+"Write (Fast 1150mV 100C Model)",0.388,0.388
+"Address Command (Fast 1150mV -40C Model)",0.874,0.483
+"Bus Turnaround Time (Fast 1150mV -40C Model)",5.742,--
+"Core (Fast 1150mV -40C Model)",1.374,0.112
+"Core Recovery/Removal (Fast 1150mV -40C Model)",3.313,0.275
+"DQS vs CK (Fast 1150mV -40C Model)",0.643,0.723
+"Postamble (Fast 1150mV -40C Model)",0.67,0.67
+"Read Capture (Fast 1150mV -40C Model)",0.339,0.331
+"Write (Fast 1150mV -40C Model)",0.385,0.385
diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl
index f1ac15489..b3e33607a 100755
--- a/projects/fmcjesdadc1/a5gt/system_project.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_project.tcl
@@ -7,6 +7,7 @@ project_new fmcjesdadc1_a5gt -overwrite
 source "../../common/a5gt/a5gt_system_assign.tcl"
 
 set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
+set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v
 set_global_assignment -name VERILOG_FILE system_top.v
 set_global_assignment -name QSYS_FILE system_bd.qsys
 
diff --git a/projects/fmcjesdadc1/a5gt/system_qsys_script.tcl b/projects/fmcjesdadc1/a5gt/system_qsys_script.tcl
new file mode 100644
index 000000000..2b3c37731
--- /dev/null
+++ b/projects/fmcjesdadc1/a5gt/system_qsys_script.tcl
@@ -0,0 +1,4 @@
+set mmu_enabled 1
+set ad_hdl_dir /home/icsomort/Git/hdl
+set ad_phdl_dir /home/icsomort/Git/hdl
+source system_qsys.tcl
diff --git a/projects/fmcjesdadc1/a5gt/system_top.v b/projects/fmcjesdadc1/a5gt/system_top.v
index 169e9da1e..af40255ba 100644
--- a/projects/fmcjesdadc1/a5gt/system_top.v
+++ b/projects/fmcjesdadc1/a5gt/system_top.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -99,9 +99,6 @@ module system_top (
 
   reg     [  3:0]   phy_rst_cnt = 0;
   reg               phy_rst_reg = 0;
-  reg               rx_sysref_m1 = 'd0;
-  reg               rx_sysref_m2 = 'd0;
-  reg               rx_sysref_int = 'd0;
 
   // internal signals
 
@@ -144,15 +141,12 @@ module system_top (
 
   // sysref
 
-  assign rx_sysref = rx_sysref_int;
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[32]),
+    .sysref_out (rx_sysref));
 
-  always @(posedge rx_clk) begin
-    rx_sysref_m1 <= gpio_o[32];
-    rx_sysref_m2 <= rx_sysref_m1;
-    rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
-  end
-
-  // instantiations
+ // instantiations
 
   assign spi_csn = spi_csn_s[0];
 
@@ -196,7 +190,7 @@ module system_top (
     .rx_ip_sof_1_export (rx_ip_sof),
     .rx_ref_clk_clk (ref_clk),
     .rx_sync_export (rx_sync),
-    .rx_sysref_export (rx_sysref_int),
+    .rx_sysref_export (rx_sysref),
     .sys_125m_clk_clk (sys_125m_clk),
     .sys_25m_clk_clk (sys_25m_clk),
     .sys_2m5_clk_clk (sys_2m5_clk),
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 7eafa8a4e..109a12bb5 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -22,6 +22,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a5soc/a5soc_system_qsys.tcl
 M_DEPS += ../../common/a5soc/a5soc_system_assign.tcl
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
 M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
 M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
diff --git a/projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld b/projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld
new file mode 100644
index 000000000..7657b5621
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld
@@ -0,0 +1,9 @@
+<sld_project_info>
+  <sld_infos>
+    <sld_info hpath="system_bd:i_system_bd" name="i_system_bd">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME system_bd HAS_SOPCINFO 1 GENERATION_ID 1482152395"/>
+      </assignment_values>
+    </sld_info>
+  </sld_infos>
+</sld_project_info>
diff --git a/projects/fmcjesdadc1/a5soc/system_bd.qsys b/projects/fmcjesdadc1/a5soc/system_bd.qsys
new file mode 100644
index 000000000..56ac104fb
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/system_bd.qsys
@@ -0,0 +1,1585 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element ad9250_adcfifo
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element avl_ad9250_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element avl_phy_reconfig
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element axi_ad9250_core_0
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element axi_ad9250_core_1
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element axi_ad9250_dma
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element axi_ad9250_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element rx_core_clk
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_dma_clk
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sys_gpio_bd
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element sys_gpio_in
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element sys_gpio_out
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element sys_hps
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element util_ad9250_cpack
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5ASTFD5K3F40I3ES" />
+ <parameter name="deviceFamily" value="Arria V" />
+ <parameter name="deviceSpeedGrade" value="3_H3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="rx_core_clk"
+   internal="rx_core_clk.out_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="rx_data_0"
+   internal="avl_ad9250_xcvr.rx_data_0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_1"
+   internal="avl_ad9250_xcvr.rx_data_1"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_2"
+   internal="avl_ad9250_xcvr.rx_data_2"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_3"
+   internal="avl_ad9250_xcvr.rx_data_3"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_data"
+   internal="avl_ad9250_xcvr.ip_data"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="rx_ip_data_0"
+   internal="axi_ad9250_core_0.if_rx_data"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="rx_ip_data_1"
+   internal="axi_ad9250_core_1.if_rx_data"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="rx_ip_sof"
+   internal="avl_ad9250_xcvr.ip_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_sof_0"
+   internal="axi_ad9250_core_0.if_rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_sof_1"
+   internal="axi_ad9250_core_1.if_rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ref_clk"
+   internal="avl_ad9250_xcvr.ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="rx_sync"
+   internal="avl_ad9250_xcvr.sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_sysref"
+   internal="avl_ad9250_xcvr.sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="sys_dma_clk"
+   internal="sys_dma_clk.clk_in"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_dma_rst"
+   internal="sys_dma_clk.clk_in_reset"
+   type="reset"
+   dir="end" />
+ <interface
+   name="sys_gpio_bd"
+   internal="sys_gpio_bd.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_in"
+   internal="sys_gpio_in.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_out"
+   internal="sys_gpio_out.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_cpu_clk"
+   internal="sys_hps.h2f_user0_clock"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_hps_ddr3"
+   internal="sys_hps.memory"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_dma_clk"
+   internal="sys_hps.h2f_user1_clock"
+   type="clock"
+   dir="start" />
+ <interface name="sys_hps_i2c0" internal="sys_hps.i2c0" type="conduit" dir="end" />
+ <interface
+   name="sys_hps_i2c0_clk"
+   internal="sys_hps.i2c0_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_hps_i2c0_scl"
+   internal="sys_hps.i2c0_scl_in"
+   type="clock"
+   dir="end" />
+ <interface name="sys_hps_io" internal="sys_hps.hps_io" type="conduit" dir="end" />
+ <interface
+   name="sys_hps_rstn"
+   internal="sys_hps.h2f_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="sys_hps_spim0"
+   internal="sys_hps.spim0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_spim0_sclk"
+   internal="sys_hps.spim0_sclk_out"
+   type="clock"
+   dir="start" />
+ <interface name="sys_rst" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
+ <module name="ad9250_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
+  <parameter name="ADC_DATA_WIDTH" value="128" />
+  <parameter name="DMA_ADDRESS_WIDTH" value="16" />
+  <parameter name="DMA_DATA_WIDTH" value="128" />
+  <parameter name="DMA_READY_ENABLE" value="1" />
+ </module>
+ <module name="avl_ad9250_xcvr" kind="avl_adxcvr" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="CORECLK_FREQUENCY" value="125.0" />
+  <parameter name="DEVICE_FAMILY" value="Arria V" />
+  <parameter name="FRM_BCNT" value="4" />
+  <parameter name="FRM_SCNT" value="1" />
+  <parameter name="HD" value="0" />
+  <parameter name="ID" value="1" />
+  <parameter name="LANE_RATE" value="5000.0" />
+  <parameter name="MF_FCNT" value="32" />
+  <parameter name="NUM_OF_CONVS" value="4" />
+  <parameter name="NUM_OF_LANES" value="4" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="PLLCLK_FREQUENCY" value="2500.0" />
+  <parameter name="REFCLK_FREQUENCY" value="250.0" />
+  <parameter name="SYSCLK_FREQUENCY" value="50.0" />
+  <parameter name="TX_OR_RX_N" value="0" />
+ </module>
+ <module
+   name="avl_phy_reconfig"
+   kind="alt_xcvr_reconfig"
+   version="16.0"
+   enabled="1">
+  <parameter name="ber_en" value="0" />
+  <parameter name="device_family" value="Arria V" />
+  <parameter name="enable_adce" value="0" />
+  <parameter name="enable_analog" value="1" />
+  <parameter name="enable_dcd" value="0" />
+  <parameter name="enable_dcd_power_up" value="1" />
+  <parameter name="enable_dfe" value="0" />
+  <parameter name="enable_eyemon" value="0" />
+  <parameter name="enable_mif" value="0" />
+  <parameter name="enable_offset" value="1" />
+  <parameter name="gui_cal_status_port" value="false" />
+  <parameter name="gui_enable_pll" value="0" />
+  <parameter name="gui_split_sizes" value="1,1,1,1" />
+  <parameter name="number_of_reconfig_interfaces" value="4" />
+ </module>
+ <module name="axi_ad9250_core_0" kind="axi_ad9250" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="1" />
+  <parameter name="ID" value="0" />
+ </module>
+ <module name="axi_ad9250_core_1" kind="axi_ad9250" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="1" />
+  <parameter name="ID" value="0" />
+ </module>
+ <module name="axi_ad9250_dma" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="0" />
+  <parameter name="DMA_TYPE_SRC" value="1" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
+ </module>
+ <module name="axi_ad9250_xcvr" kind="axi_adxcvr" version="1.0" enabled="1">
+  <parameter name="ID" value="1" />
+  <parameter name="NUM_OF_LANES" value="4" />
+  <parameter name="TX_OR_RX_N" value="0" />
+ </module>
+ <module
+   name="rx_core_clk"
+   kind="altera_clock_bridge"
+   version="16.0"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="125" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_clk" kind="clock_source" version="16.0" enabled="1">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="DEASSERT" />
+ </module>
+ <module name="sys_dma_clk" kind="clock_source" version="16.0" enabled="1">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="DEASSERT" />
+ </module>
+ <module
+   name="sys_gpio_bd"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_in"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_out"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module name="sys_hps" kind="altera_hps" version="16.0" enabled="1">
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="BONDING_OUT_ENABLED" value="false" />
+  <parameter name="BOOTFROMFPGA_Enable" value="false" />
+  <parameter name="BSEL" value="1" />
+  <parameter name="BSEL_EN" value="false" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="CAN0_Mode" value="N/A" />
+  <parameter name="CAN0_PinMuxing" value="Unused" />
+  <parameter name="CAN1_Mode" value="N/A" />
+  <parameter name="CAN1_PinMuxing" value="Unused" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="CSEL" value="0" />
+  <parameter name="CSEL_EN" value="false" />
+  <parameter name="CTI_Enable" value="false" />
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DEBUGAPB_Enable" value="false" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="EMAC0_Mode" value="N/A" />
+  <parameter name="EMAC0_PTP" value="false" />
+  <parameter name="EMAC0_PinMuxing" value="Unused" />
+  <parameter name="EMAC1_Mode" value="RGMII" />
+  <parameter name="EMAC1_PTP" value="false" />
+  <parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="F2H_AXI_CLOCK_FREQ" value="100000000" />
+  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
+  <parameter name="F2SCLK_COLDRST_Enable" value="false" />
+  <parameter name="F2SCLK_DBGRST_Enable" value="false" />
+  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
+  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
+  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
+  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
+  <parameter name="F2SCLK_WARMRST_Enable" value="false" />
+  <parameter name="F2SDRAM_Type" value="" />
+  <parameter name="F2SDRAM_Width" value="" />
+  <parameter name="F2SINTERRUPT_Enable" value="true" />
+  <parameter name="F2S_Width" value="2" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
+  <parameter
+     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
+     value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="0" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="125" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="2.5" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="125" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="2.5" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
+  <parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
+  <parameter name="GP_Enable" value="false" />
+  <parameter name="H2F_AXI_CLOCK_FREQ" value="100000000" />
+  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="100000000" />
+  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
+  <parameter name="HARD_EMIF" value="true" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="HHP_HPS" value="true" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HLGPI_Enable" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DDR3" />
+  <parameter name="I2C0_Mode" value="Full" />
+  <parameter name="I2C0_PinMuxing" value="FPGA" />
+  <parameter name="I2C1_Mode" value="N/A" />
+  <parameter name="I2C1_PinMuxing" value="Unused" />
+  <parameter name="I2C2_Mode" value="N/A" />
+  <parameter name="I2C2_PinMuxing" value="Unused" />
+  <parameter name="I2C3_Mode" value="N/A" />
+  <parameter name="I2C3_PinMuxing" value="Unused" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+  <parameter name="LWH2F_Enable" value="true" />
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="MEM_CLK_FREQ" value="400.0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DQ_WIDTH" value="40" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
+  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_TCL" value="7" />
+  <parameter name="MEM_TFAW_NS" value="35.0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="260.0" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="4" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="MEM_WTCL" value="6" />
+  <parameter name="MPU_EVENTS_Enable" value="false" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="NAND_Mode" value="N/A" />
+  <parameter name="NAND_PinMuxing" value="Unused" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="QSPI_Mode" value="1 SS" />
+  <parameter name="QSPI_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="RATE" value="Full" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="REF_CLK_FREQ" value="25.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
+  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
+  <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
+  <parameter name="S2FCLK_USER1CLK_Enable" value="true" />
+  <parameter name="S2FCLK_USER1CLK_FREQ" value="100.0" />
+  <parameter name="S2FCLK_USER2CLK" value="5" />
+  <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
+  <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
+  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
+  <parameter name="S2F_Width" value="2" />
+  <parameter name="SDIO_Mode" value="4-bit Data" />
+  <parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="SPEED_GRADE" value="7" />
+  <parameter name="SPIM0_Mode" value="Full" />
+  <parameter name="SPIM0_PinMuxing" value="FPGA" />
+  <parameter name="SPIM1_Mode" value="N/A" />
+  <parameter name="SPIM1_PinMuxing" value="Unused" />
+  <parameter name="SPIS0_Mode" value="N/A" />
+  <parameter name="SPIS0_PinMuxing" value="Unused" />
+  <parameter name="SPIS1_Mode" value="N/A" />
+  <parameter name="SPIS1_PinMuxing" value="Unused" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="STM_Enable" value="false" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="TEST_Enable" value="false" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSH" value="0.35" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TQHS" value="300" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TPIUFPGA_Enable" value="false" />
+  <parameter name="TPIUFPGA_alt" value="false" />
+  <parameter name="TRACE_Mode" value="N/A" />
+  <parameter name="TRACE_PinMuxing" value="Unused" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="UART0_Mode" value="No Flow Control" />
+  <parameter name="UART0_PinMuxing" value="HPS I/O Set 1" />
+  <parameter name="UART1_Mode" value="N/A" />
+  <parameter name="UART1_PinMuxing" value="Unused" />
+  <parameter name="USB0_Mode" value="N/A" />
+  <parameter name="USB0_PinMuxing" value="Unused" />
+  <parameter name="USB1_Mode" value="SDR" />
+  <parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+  <parameter name="can0_clk_div" value="1" />
+  <parameter name="can1_clk_div" value="1" />
+  <parameter name="configure_advanced_parameters" value="false" />
+  <parameter name="customize_device_pll_info" value="false" />
+  <parameter name="dbctrl_stayosc1" value="true" />
+  <parameter name="dbg_at_clk_div" value="0" />
+  <parameter name="dbg_clk_div" value="1" />
+  <parameter name="dbg_trace_clk_div" value="0" />
+  <parameter name="desired_can0_clk_mhz" value="100.0" />
+  <parameter name="desired_can1_clk_mhz" value="100.0" />
+  <parameter name="desired_cfg_clk_mhz" value="50.0" />
+  <parameter name="desired_emac0_clk_mhz" value="250.0" />
+  <parameter name="desired_emac1_clk_mhz" value="250.0" />
+  <parameter name="desired_gpio_db_clk_hz" value="32000" />
+  <parameter name="desired_l4_mp_clk_mhz" value="100.0" />
+  <parameter name="desired_l4_sp_clk_mhz" value="100.0" />
+  <parameter name="desired_mpu_clk_mhz" value="800.0" />
+  <parameter name="desired_nand_clk_mhz" value="12.5" />
+  <parameter name="desired_qspi_clk_mhz" value="400.0" />
+  <parameter name="desired_sdmmc_clk_mhz" value="200.0" />
+  <parameter name="desired_spi_m_clk_mhz" value="200.0" />
+  <parameter name="desired_usb_mp_clk_mhz" value="200.0" />
+  <parameter name="device_name" value="5ASTFD5K3F40I3ES" />
+  <parameter name="device_pll_info_manual">{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}</parameter>
+  <parameter name="eosc1_clk_mhz" value="25.0" />
+  <parameter name="eosc2_clk_mhz" value="25.0" />
+  <parameter name="gpio_db_clk_div" value="6249" />
+  <parameter name="l3_mp_clk_div" value="1" />
+  <parameter name="l3_sp_clk_div" value="1" />
+  <parameter name="l4_mp_clk_div" value="1" />
+  <parameter name="l4_mp_clk_source" value="1" />
+  <parameter name="l4_sp_clk_div" value="1" />
+  <parameter name="l4_sp_clk_source" value="1" />
+  <parameter name="main_pll_c3" value="3" />
+  <parameter name="main_pll_c4" value="3" />
+  <parameter name="main_pll_c5" value="15" />
+  <parameter name="main_pll_m" value="63" />
+  <parameter name="main_pll_n" value="0" />
+  <parameter name="nand_clk_source" value="2" />
+  <parameter name="periph_pll_c0" value="3" />
+  <parameter name="periph_pll_c1" value="3" />
+  <parameter name="periph_pll_c2" value="1" />
+  <parameter name="periph_pll_c3" value="19" />
+  <parameter name="periph_pll_c4" value="4" />
+  <parameter name="periph_pll_c5" value="9" />
+  <parameter name="periph_pll_m" value="79" />
+  <parameter name="periph_pll_n" value="1" />
+  <parameter name="periph_pll_source" value="0" />
+  <parameter name="qspi_clk_source" value="1" />
+  <parameter name="quartus_ini_hps_emif_pll" value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
+     value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
+     value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
+     value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
+  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
+  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
+  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
+  <parameter name="sdmmc_clk_source" value="2" />
+  <parameter name="show_advanced_parameters" value="false" />
+  <parameter name="show_debug_info_as_warning_msg" value="false" />
+  <parameter name="show_warning_as_error_msg" value="false" />
+  <parameter name="spi_m_clk_div" value="0" />
+  <parameter name="usb_mp_clk_div" value="0" />
+  <parameter name="use_default_mpu_clk" value="false" />
+ </module>
+ <module
+   name="sys_id"
+   kind="altera_avalon_sysid_qsys"
+   version="16.0"
+   enabled="1">
+  <parameter name="id" value="182193580" />
+ </module>
+ <module
+   name="sys_int_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="16.0"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">system_bd_sys_int_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="64" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="65536" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="util_ad9250_cpack" kind="util_cpack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_axi_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x001814e8" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="avl_ad9250_xcvr.core_pll_reconfig">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00018000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="avl_ad9250_xcvr.ip_reconfig">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00019000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="avl_phy_reconfig.reconfig_mgmt">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_gpio_bd.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x001814d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_gpio_in.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x001814c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_gpio_out.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00181500" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="axi_ad9250_xcvr.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="axi_ad9250_core_0.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00050000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="axi_ad9250_core_1.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00060000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="axi_ad9250_dma.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00070000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="axi_ad9250_dma.m_dest_axi"
+   end="sys_hps.f2h_axi_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_id.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_bd.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_in.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_gpio_out.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="sys_hps.f2h_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_hps.h2f_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_hps.h2f_lw_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="ad9250_adcfifo.if_dma_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="axi_ad9250_dma.if_s_axis_aclk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="axi_ad9250_dma.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="avl_phy_reconfig.mgmt_clk_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9250_xcvr.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9250_core_0.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9250_core_1.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9250_dma.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="avl_ad9250_xcvr.sys_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="util_ad9250_cpack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="ad9250_adcfifo.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="axi_ad9250_core_0.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="axi_ad9250_core_1.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_ad9250_xcvr.core_clk"
+   end="rx_core_clk.in_clk" />
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_core_0.adc_ch_0"
+   end="util_ad9250_cpack.adc_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_core_1.adc_ch_0"
+   end="util_ad9250_cpack.adc_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_core_0.adc_ch_1"
+   end="util_ad9250_cpack.adc_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_core_1.adc_ch_1"
+   end="util_ad9250_cpack.adc_ch_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch0_0_to_xcvr"
+   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch1_1_to_xcvr"
+   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch2_2_to_xcvr"
+   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch3_3_to_xcvr"
+   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9250_xcvr.core_pll_locked"
+   end="avl_ad9250_xcvr.core_pll_locked">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="util_ad9250_cpack.if_adc_data"
+   end="ad9250_adcfifo.if_adc_wdata">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="util_ad9250_cpack.if_adc_valid"
+   end="ad9250_adcfifo.if_adc_wr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_adc_wovf"
+   end="axi_ad9250_core_0.if_adc_dovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_dma_wdata"
+   end="axi_ad9250_dma.if_s_axis_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_dma_wr"
+   end="axi_ad9250_dma.if_s_axis_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_dma_wready"
+   end="axi_ad9250_dma.if_s_axis_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="ad9250_adcfifo.if_dma_xfer_req"
+   end="axi_ad9250_dma.if_s_axis_xfer_req">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_0"
+   end="avl_phy_reconfig.ch0_0_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_1"
+   end="avl_phy_reconfig.ch1_1_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_2"
+   end="avl_phy_reconfig.ch2_2_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_3"
+   end="avl_phy_reconfig.ch3_3_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_ad9250_xcvr.ready"
+   end="axi_ad9250_xcvr.ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="axi_ad9250_dma.interrupt_sender">
+  <parameter name="irqNumber" value="11" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_gpio_in.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_gpio_bd.irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="util_ad9250_cpack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_dma_clk.clk_reset"
+   end="util_ad9250_cpack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="ad9250_adcfifo.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_dma_clk.clk_reset"
+   end="ad9250_adcfifo.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_dma_clk.clk_reset"
+   end="axi_ad9250_dma.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="avl_phy_reconfig.mgmt_rst_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_id.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_bd.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_in.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_out.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_int_mem.reset1" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_xcvr.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_core_0.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_core_1.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_dma.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="avl_ad9250_xcvr.sys_resetn" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="axi_ad9250_xcvr.if_up_rst"
+   end="avl_ad9250_xcvr.rst" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
+</system>
diff --git a/projects/fmcjesdadc1/a5soc/system_project.tcl b/projects/fmcjesdadc1/a5soc/system_project.tcl
index e0e780765..ad17a1013 100755
--- a/projects/fmcjesdadc1/a5soc/system_project.tcl
+++ b/projects/fmcjesdadc1/a5soc/system_project.tcl
@@ -7,6 +7,7 @@ project_new fmcjesdadc1_a5soc -overwrite
 source "../../common/a5soc/a5soc_system_assign.tcl"
 
 set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
+set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v
 set_global_assignment -name VERILOG_FILE system_top.v
 set_global_assignment -name QSYS_FILE system_bd.qsys
 
diff --git a/projects/fmcjesdadc1/a5soc/system_qsys_script.tcl b/projects/fmcjesdadc1/a5soc/system_qsys_script.tcl
new file mode 100644
index 000000000..2b3c37731
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/system_qsys_script.tcl
@@ -0,0 +1,4 @@
+set mmu_enabled 1
+set ad_hdl_dir /home/icsomort/Git/hdl
+set ad_phdl_dir /home/icsomort/Git/hdl
+source system_qsys.tcl
diff --git a/projects/fmcjesdadc1/a5soc/system_top.v b/projects/fmcjesdadc1/a5soc/system_top.v
index f5accbcd5..94b6fb987 100644
--- a/projects/fmcjesdadc1/a5soc/system_top.v
+++ b/projects/fmcjesdadc1/a5soc/system_top.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -121,12 +121,6 @@ module system_top (
   output            spi_clk,
   inout             spi_sdio);
 
-  // internal registers
-
-  reg               rx_sysref_m1 = 'd0;
-  reg               rx_sysref_m2 = 'd0;
-  reg               rx_sysref_int = 'd0;
-
   // internal signals
 
   wire              sys_cpu_clk;
@@ -156,13 +150,10 @@ module system_top (
 
   // sysref
 
-  assign rx_sysref = rx_sysref_int;
-
-  always @(posedge rx_clk) begin
-    rx_sysref_m1 <= gpio_o[32];
-    rx_sysref_m2 <= rx_sysref_m1;
-    rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
-  end
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[32]),
+    .sysref_out (rx_sysref));
 
   // instantiations
 
@@ -193,7 +184,7 @@ module system_top (
     .rx_ip_sof_1_export (rx_ip_sof),
     .rx_ref_clk_clk (ref_clk),
     .rx_sync_export (rx_sync),
-    .rx_sysref_export (rx_sysref_int),
+    .rx_sysref_export (rx_sysref),
     .sys_clk_clk (sys_cpu_clk),
     .sys_dma_clk_clk (sys_dma_clk),
     .sys_dma_rst_reset_n (sys_rstn),
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
index 7c5152a23..5fa81ebe1 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
@@ -74,10 +74,13 @@ ad_xcvrpll  axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_cpll_rst_*
 ad_connect  sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk
 
+create_bd_port -dir O rx_core_clk
+
 # connections (adc)
 
 ad_xcvrcon  util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd
 ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk
+ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0 rx_core_clk
 ad_connect  axi_ad9250_jesd/rx_start_of_frame axi_ad9250_0_core/rx_sof
 ad_connect  util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk
 ad_connect  axi_ad9250_jesd/rx_start_of_frame axi_ad9250_1_core/rx_sof
diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile
index d704ece29..356fcc60a 100644
--- a/projects/fmcjesdadc1/kc705/Makefile
+++ b/projects/fmcjesdadc1/kc705/Makefile
@@ -18,6 +18,7 @@ M_DEPS += ../../common/kc705/kc705_system_mig.prj
 M_DEPS += ../../common/kc705/kc705_system_constr.xdc
 M_DEPS += ../../common/kc705/kc705_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcjesdadc1/kc705/system_constr.xdc b/projects/fmcjesdadc1/kc705/system_constr.xdc
index 8a06d8d97..8a4142a24 100644
--- a/projects/fmcjesdadc1/kc705/system_constr.xdc
+++ b/projects/fmcjesdadc1/kc705/system_constr.xdc
@@ -25,3 +25,6 @@ create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
+set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+
diff --git a/projects/fmcjesdadc1/kc705/system_project.tcl b/projects/fmcjesdadc1/kc705/system_project.tcl
index 33fe320b7..e31aa0af4 100644
--- a/projects/fmcjesdadc1/kc705/system_project.tcl
+++ b/projects/fmcjesdadc1/kc705/system_project.tcl
@@ -9,6 +9,7 @@ adi_project_files fmcjesdadc1_kc705 [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
 
 adi_project_run fmcjesdadc1_kc705
diff --git a/projects/fmcjesdadc1/kc705/system_top.v b/projects/fmcjesdadc1/kc705/system_top.v
index c8b9cbd1c..c45511b45 100644
--- a/projects/fmcjesdadc1/kc705/system_top.v
+++ b/projects/fmcjesdadc1/kc705/system_top.v
@@ -180,6 +180,8 @@ module system_top (
   wire            spi_mosi;
   wire            spi_miso;
   wire            rx_ref_clk;
+  wire            rx_clk;
+  wire            rx_sysref;
 
   assign ddr3_1_p = 2'b11;
   assign ddr3_1_n = 3'b000;
@@ -209,6 +211,11 @@ module system_top (
     .spi_miso (spi_miso),
     .spi_sdio (spi_sdio));
 
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[32]),
+    .sysref_out (rx_sysref));
+
   // instantiations
 
   system_wrapper i_system_wrapper (
@@ -277,6 +284,7 @@ module system_top (
     .rx_ref_clk_0 (rx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (rx_sysref),
+    .rx_core_clk (rx_clk),
     .spi_clk_i (spi_clk),
     .spi_clk_o (spi_clk),
     .spi_csn_i (spi_csn),
diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile
index c62009f4f..34966231f 100644
--- a/projects/fmcjesdadc1/vc707/Makefile
+++ b/projects/fmcjesdadc1/vc707/Makefile
@@ -18,6 +18,7 @@ M_DEPS += ../../common/vc707/vc707_system_mig.prj
 M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcjesdadc1/vc707/system_constr.xdc b/projects/fmcjesdadc1/vc707/system_constr.xdc
index f7ad93138..42de9cede 100644
--- a/projects/fmcjesdadc1/vc707/system_constr.xdc
+++ b/projects/fmcjesdadc1/vc707/system_constr.xdc
@@ -24,4 +24,8 @@ create_clock -name rx_ref_clk   -period  4.00 [get_ports rx_ref_clk_p]
 create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -to [get_cells i_system_wrapper/system_i/axi_ad9250_jesd/inst/rx_sysref_r_reg/D]
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
 
diff --git a/projects/fmcjesdadc1/vc707/system_project.tcl b/projects/fmcjesdadc1/vc707/system_project.tcl
index 7835780ea..f07155002 100644
--- a/projects/fmcjesdadc1/vc707/system_project.tcl
+++ b/projects/fmcjesdadc1/vc707/system_project.tcl
@@ -6,6 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create fmcjesdadc1_vc707
 adi_project_files fmcjesdadc1_vc707 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "../common/fmcjesdadc1_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
diff --git a/projects/fmcjesdadc1/vc707/system_top.v b/projects/fmcjesdadc1/vc707/system_top.v
index 639a85eee..d8a30cfbe 100644
--- a/projects/fmcjesdadc1/vc707/system_top.v
+++ b/projects/fmcjesdadc1/vc707/system_top.v
@@ -174,6 +174,8 @@ module system_top (
   wire            spi_miso;
   wire            rx_ref_clk;
   wire    [31:0]  mb_intrs;
+  wire            rx_clk;
+  wire            rx_sysref;
 
   assign ddr3_1_p = 2'b11;
   assign ddr3_1_n = 3'b000;
@@ -203,6 +205,11 @@ module system_top (
     .spi_miso (spi_miso),
     .spi_sdio (spi_sdio));
 
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[32]),
+    .sysref_out (rx_sysref));
+
   // instantiations
 
   system_wrapper i_system_wrapper (
@@ -267,6 +274,7 @@ module system_top (
     .rx_ref_clk_0 (rx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (rx_sysref),
+    .rx_core_clk (rx_clk),
     .spi_clk_i (1'b0),
     .spi_clk_o (spi_clk),
     .spi_csn_i (8'hff),
diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile
index f472a6ae2..11949d68f 100644
--- a/projects/fmcjesdadc1/zc706/Makefile
+++ b/projects/fmcjesdadc1/zc706/Makefile
@@ -17,6 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library//common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/fmcjesdadc1/zc706/system_constr.xdc b/projects/fmcjesdadc1/zc706/system_constr.xdc
index eff780e85..97d65a600 100644
--- a/projects/fmcjesdadc1/zc706/system_constr.xdc
+++ b/projects/fmcjesdadc1/zc706/system_constr.xdc
@@ -11,12 +11,12 @@ set_property  -dict {PACKAGE_PIN  AG8 } [get_ports rx_data_p[2]]
 set_property  -dict {PACKAGE_PIN  AG7 } [get_ports rx_data_n[2]]                                      ; ## A07  FMC_HPC_DP2_M2C_N
 set_property  -dict {PACKAGE_PIN  AE8 } [get_ports rx_data_p[3]]                                      ; ## A10  FMC_HPC_DP3_M2C_P
 set_property  -dict {PACKAGE_PIN  AE7 } [get_ports rx_data_n[3]]                                      ; ## A11  FMC_HPC_DP3_M2C_N
-set_property  -dict {PACKAGE_PIN  N26   IOSTANDARD LVCMOS25} [get_ports rx_sync]                      ; ## G36  FMC_HPC_LA33_P          
-set_property  -dict {PACKAGE_PIN  N27   IOSTANDARD LVCMOS25} [get_ports rx_sysref]                    ; ## G37  FMC_HPC_LA33_N          
+set_property  -dict {PACKAGE_PIN  N26   IOSTANDARD LVCMOS25} [get_ports rx_sync]                      ; ## G36  FMC_HPC_LA33_P
+set_property  -dict {PACKAGE_PIN  N27   IOSTANDARD LVCMOS25} [get_ports rx_sysref]                    ; ## G37  FMC_HPC_LA33_N
 
-set_property  -dict {PACKAGE_PIN  P29   IOSTANDARD LVCMOS25} [get_ports spi_csn]                      ; ## G34  FMC_HPC_LA31_N          
-set_property  -dict {PACKAGE_PIN  N29   IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## G33  FMC_HPC_LA31_P          
-set_property  -dict {PACKAGE_PIN  P21   IOSTANDARD LVCMOS25} [get_ports spi_sdio]                     ; ## H37  FMC_HPC_LA32_P          
+set_property  -dict {PACKAGE_PIN  P29   IOSTANDARD LVCMOS25} [get_ports spi_csn]                      ; ## G34  FMC_HPC_LA31_N
+set_property  -dict {PACKAGE_PIN  N29   IOSTANDARD LVCMOS25} [get_ports spi_clk]                      ; ## G33  FMC_HPC_LA31_P
+set_property  -dict {PACKAGE_PIN  P21   IOSTANDARD LVCMOS25} [get_ports spi_sdio]                     ; ## H37  FMC_HPC_LA32_P
 
 # clocks
 
@@ -25,3 +25,6 @@ create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
+set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+
diff --git a/projects/fmcjesdadc1/zc706/system_project.tcl b/projects/fmcjesdadc1/zc706/system_project.tcl
index 0a0531c5f..35c69f7bb 100644
--- a/projects/fmcjesdadc1/zc706/system_project.tcl
+++ b/projects/fmcjesdadc1/zc706/system_project.tcl
@@ -6,6 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 adi_project_create fmcjesdadc1_zc706
 adi_project_files fmcjesdadc1_zc706 [list \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "../common/fmcjesdadc1_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
diff --git a/projects/fmcjesdadc1/zc706/system_top.v b/projects/fmcjesdadc1/zc706/system_top.v
index dc4e9f375..82d1a5cef 100644
--- a/projects/fmcjesdadc1/zc706/system_top.v
+++ b/projects/fmcjesdadc1/zc706/system_top.v
@@ -149,6 +149,8 @@ module system_top (
   wire            spi1_clk;
   wire            spi1_mosi;
   wire            spi1_miso;
+  wire            rx_clk;
+  wire            rx_sysref;
 
   assign spi_csn = spi0_csn[0];
   assign spi_clk = spi0_clk;
@@ -180,6 +182,11 @@ module system_top (
     .spi_miso (spi_miso),
     .spi_sdio (spi_sdio));
 
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[32]),
+    .sysref_out (rx_sysref));
+
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),
@@ -235,6 +242,7 @@ module system_top (
     .rx_ref_clk_0 (rx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (rx_sysref),
+    .rx_core_clk (rx_clk),
     .spdif (spdif),
     .spi0_clk_i (spi0_clk),
     .spi0_clk_o (spi0_clk),

From f47863bbcfa0a5a9396a9fe73a78dc99ad703ff7 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Dec 2016 14:36:01 +0000
Subject: [PATCH 820/972] usdrx1: Integrate ad_syref_gen into the project

---
 projects/usdrx1/a5gt/Makefile               |    1 +
 projects/usdrx1/a5gt/serv_req_info.txt      |    8 +
 projects/usdrx1/a5gt/system_bd.qsys         | 2599 +++++++++++++++++++
 projects/usdrx1/a5gt/system_constr.sdc      |    2 +
 projects/usdrx1/a5gt/system_project.tcl     |    1 +
 projects/usdrx1/a5gt/system_qsys_script.tcl |    4 +
 projects/usdrx1/a5gt/system_top.v           |   16 +-
 projects/usdrx1/common/usdrx1_bd.tcl        |    2 +
 projects/usdrx1/zc706/Makefile              |    1 +
 projects/usdrx1/zc706/system_project.tcl    |    1 +
 projects/usdrx1/zc706/system_top.v          |    8 +
 11 files changed, 2632 insertions(+), 11 deletions(-)
 create mode 100644 projects/usdrx1/a5gt/serv_req_info.txt
 create mode 100644 projects/usdrx1/a5gt/system_bd.qsys
 create mode 100644 projects/usdrx1/a5gt/system_qsys_script.tcl

diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile
index a7b511e1c..24970af39 100644
--- a/projects/usdrx1/a5gt/Makefile
+++ b/projects/usdrx1/a5gt/Makefile
@@ -22,6 +22,7 @@ M_DEPS += ../../scripts/adi_env.tcl
 M_DEPS += ../../common/altera/sys_gen.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_qsys.tcl
 M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
 M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
 M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
diff --git a/projects/usdrx1/a5gt/serv_req_info.txt b/projects/usdrx1/a5gt/serv_req_info.txt
new file mode 100644
index 000000000..93337fb66
--- /dev/null
+++ b/projects/usdrx1/a5gt/serv_req_info.txt
@@ -0,0 +1,8 @@
+<internal_error>
+	<executable>quartus_sta</executable>
+	<sub_system>MEM</sub_system>
+	<error>*** Fatal Error: Out of memory in module quartus_sta (4441 megabytes used)</error>
+	<date>Mon Dec 19 13:19:17 2016</date>
+	<version>Version 16.0.2 Build 222 07/20/2016 SJ Standard Edition</version>
+</internal_error>
+
diff --git a/projects/usdrx1/a5gt/system_bd.qsys b/projects/usdrx1/a5gt/system_bd.qsys
new file mode 100644
index 000000000..3c73f2741
--- /dev/null
+++ b/projects/usdrx1/a5gt/system_bd.qsys
@@ -0,0 +1,2599 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element avl_phy_reconfig
+   {
+      datum _sortIndex
+      {
+         value = "27";
+         type = "int";
+      }
+   }
+   element avl_usdrx1_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element axi_ad9671_core_0
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element axi_ad9671_core_1
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element axi_ad9671_core_2
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element axi_ad9671_core_3
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element axi_usdrx1_dma
+   {
+      datum _sortIndex
+      {
+         value = "25";
+         type = "int";
+      }
+   }
+   element axi_usdrx1_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+   }
+   element rx_core_clk
+   {
+      datum _sortIndex
+      {
+         value = "26";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_cpu
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element sys_ddr3_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element sys_dma_clk
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element sys_ethernet
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element sys_ethernet_dma_rx
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element sys_ethernet_dma_tx
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element sys_gpio_bd
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element sys_gpio_in
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element sys_gpio_out
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element sys_pll
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element sys_spi
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element sys_timer_1
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element sys_timer_2
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element sys_tlb_mem
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sys_uart
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element usdrx1_adcfifo
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5AGTFD7K3F40I3" />
+ <parameter name="deviceFamily" value="Arria V" />
+ <parameter name="deviceSpeedGrade" value="3_H3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="rx_ch_wdata"
+   internal="usdrx1_adcfifo.if_adc_wdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ch_wovf"
+   internal="usdrx1_adcfifo.if_adc_wovf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ch_wr"
+   internal="usdrx1_adcfifo.if_adc_wr"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_ch_0"
+   internal="axi_ad9671_core_0.adc_ch"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_ch_1"
+   internal="axi_ad9671_core_1.adc_ch"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_ch_2"
+   internal="axi_ad9671_core_2.adc_ch"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_ch_3"
+   internal="axi_ad9671_core_3.adc_ch"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_clk"
+   internal="rx_core_clk.out_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="rx_core_ovf_0"
+   internal="axi_ad9671_core_0.if_adc_dovf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_ovf_1"
+   internal="axi_ad9671_core_1.if_adc_dovf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_ovf_2"
+   internal="axi_ad9671_core_2.if_adc_dovf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_ovf_3"
+   internal="axi_ad9671_core_3.if_adc_dovf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_sync_0"
+   internal="axi_ad9671_core_0.if_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_sync_1"
+   internal="axi_ad9671_core_1.if_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_sync_2"
+   internal="axi_ad9671_core_2.if_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_sync_3"
+   internal="axi_ad9671_core_3.if_sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_unf_0"
+   internal="axi_ad9671_core_0.if_adc_dunf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_unf_1"
+   internal="axi_ad9671_core_1.if_adc_dunf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_unf_2"
+   internal="axi_ad9671_core_2.if_adc_dunf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_core_unf_3"
+   internal="axi_ad9671_core_3.if_adc_dunf"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_0"
+   internal="avl_usdrx1_xcvr.rx_data_0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_1"
+   internal="avl_usdrx1_xcvr.rx_data_1"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_2"
+   internal="avl_usdrx1_xcvr.rx_data_2"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_3"
+   internal="avl_usdrx1_xcvr.rx_data_3"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_4"
+   internal="avl_usdrx1_xcvr.rx_data_4"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_5"
+   internal="avl_usdrx1_xcvr.rx_data_5"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_6"
+   internal="avl_usdrx1_xcvr.rx_data_6"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_data_7"
+   internal="avl_usdrx1_xcvr.rx_data_7"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_data"
+   internal="avl_usdrx1_xcvr.ip_data"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="rx_ip_data_0"
+   internal="axi_ad9671_core_0.if_rx_data"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="rx_ip_data_1"
+   internal="axi_ad9671_core_1.if_rx_data"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="rx_ip_data_2"
+   internal="axi_ad9671_core_2.if_rx_data"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="rx_ip_data_3"
+   internal="axi_ad9671_core_3.if_rx_data"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="rx_ip_sof"
+   internal="avl_usdrx1_xcvr.ip_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_sof_0"
+   internal="axi_ad9671_core_0.if_rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_sof_1"
+   internal="axi_ad9671_core_1.if_rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_sof_2"
+   internal="axi_ad9671_core_2.if_rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ip_sof_3"
+   internal="axi_ad9671_core_3.if_rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_ref_clk"
+   internal="avl_usdrx1_xcvr.ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="rx_sync"
+   internal="avl_usdrx1_xcvr.sync"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rx_sysref"
+   internal="avl_usdrx1_xcvr.sysref"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_125m_clk"
+   internal="sys_pll.outclk0"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_25m_clk"
+   internal="sys_pll.outclk1"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_2m5_clk"
+   internal="sys_pll.outclk2"
+   type="clock"
+   dir="start" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_mem"
+   internal="sys_ddr3_cntrl.memory"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_oct"
+   internal="sys_ddr3_cntrl.oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_mdio"
+   internal="sys_ethernet.mac_mdio_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_rgmii"
+   internal="sys_ethernet.mac_rgmii_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_rx_clk"
+   internal="sys_ethernet.pcs_mac_rx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_ethernet_status"
+   internal="sys_ethernet.mac_status_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_tx_clk"
+   internal="sys_ethernet.pcs_mac_tx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_gpio_bd"
+   internal="sys_gpio_bd.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_in"
+   internal="sys_gpio_in.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_out"
+   internal="sys_gpio_out.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_pll_locked"
+   internal="sys_pll.locked"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_rst" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
+ <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
+ <module
+   name="avl_phy_reconfig"
+   kind="alt_xcvr_reconfig"
+   version="16.0"
+   enabled="1">
+  <parameter name="ber_en" value="0" />
+  <parameter name="device_family" value="Arria V" />
+  <parameter name="enable_adce" value="0" />
+  <parameter name="enable_analog" value="1" />
+  <parameter name="enable_dcd" value="0" />
+  <parameter name="enable_dcd_power_up" value="1" />
+  <parameter name="enable_dfe" value="0" />
+  <parameter name="enable_eyemon" value="0" />
+  <parameter name="enable_mif" value="0" />
+  <parameter name="enable_offset" value="1" />
+  <parameter name="gui_cal_status_port" value="false" />
+  <parameter name="gui_enable_pll" value="0" />
+  <parameter name="gui_split_sizes" value="1,1,1,1,1,1,1,1" />
+  <parameter name="number_of_reconfig_interfaces" value="8" />
+ </module>
+ <module name="avl_usdrx1_xcvr" kind="avl_adxcvr" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="CORECLK_FREQUENCY" value="80.0" />
+  <parameter name="DEVICE_FAMILY" value="Arria V" />
+  <parameter name="FRM_BCNT" value="4" />
+  <parameter name="FRM_SCNT" value="1" />
+  <parameter name="HD" value="0" />
+  <parameter name="ID" value="1" />
+  <parameter name="LANE_RATE" value="3200.0" />
+  <parameter name="MF_FCNT" value="32" />
+  <parameter name="NUM_OF_CONVS" value="32" />
+  <parameter name="NUM_OF_LANES" value="8" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="PLLCLK_FREQUENCY" value="1600.0" />
+  <parameter name="REFCLK_FREQUENCY" value="80.0" />
+  <parameter name="SYSCLK_FREQUENCY" value="100.0" />
+  <parameter name="TX_OR_RX_N" value="0" />
+ </module>
+ <module name="axi_ad9671_core_0" kind="axi_ad9671" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="0" />
+  <parameter name="QUAD_OR_DUAL_N" value="0" />
+ </module>
+ <module name="axi_ad9671_core_1" kind="axi_ad9671" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="1" />
+  <parameter name="QUAD_OR_DUAL_N" value="0" />
+ </module>
+ <module name="axi_ad9671_core_2" kind="axi_ad9671" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="2" />
+  <parameter name="QUAD_OR_DUAL_N" value="0" />
+ </module>
+ <module name="axi_ad9671_core_3" kind="axi_ad9671" version="1.0" enabled="1">
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="3" />
+  <parameter name="QUAD_OR_DUAL_N" value="0" />
+ </module>
+ <module name="axi_usdrx1_dma" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="512" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="512" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="0" />
+  <parameter name="DMA_TYPE_SRC" value="1" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
+ </module>
+ <module name="axi_usdrx1_xcvr" kind="axi_adxcvr" version="1.0" enabled="1">
+  <parameter name="ID" value="1" />
+  <parameter name="NUM_OF_LANES" value="8" />
+  <parameter name="TX_OR_RX_N" value="0" />
+ </module>
+ <module
+   name="rx_core_clk"
+   kind="altera_clock_bridge"
+   version="16.0"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="80" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_clk" kind="clock_source" version="16.0" enabled="1">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="DEASSERT" />
+ </module>
+ <module name="sys_cpu" kind="altera_nios2_gen2" version="16.0" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='avl_phy_reconfig.reconfig_mgmt' start='0x10010000' end='0x10010200' type='alt_xcvr_reconfig.reconfig_mgmt' /><slave name='avl_usdrx1_xcvr.core_pll_reconfig' start='0x10018000' end='0x10018100' type='avl_adxcvr.core_pll_reconfig' /><slave name='avl_usdrx1_xcvr.ip_reconfig' start='0x10019000' end='0x10019400' type='avl_adxcvr.ip_reconfig' /><slave name='axi_usdrx1_xcvr.s_axi' start='0x10020000' end='0x10030000' type='axi_adxcvr.s_axi' /><slave name='axi_ad9671_core_0.s_axi' start='0x10050000' end='0x10060000' type='axi_ad9671.s_axi' /><slave name='axi_ad9671_core_1.s_axi' start='0x10060000' end='0x10070000' type='axi_ad9671.s_axi' /><slave name='axi_ad9671_core_2.s_axi' start='0x10070000' end='0x10080000' type='axi_ad9671.s_axi' /><slave name='axi_ad9671_core_3.s_axi' start='0x10080000' end='0x10090000' type='axi_ad9671.s_axi' /><slave name='axi_usdrx1_dma.s_axi' start='0x10090000' end='0x10094000' type='axi_dmac.s_axi' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer_1.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="1" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="32768" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="Arria V" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="exceptionSlave" value="sys_ddr3_cntrl.avl" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="1" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="32768" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="2303" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="4096" />
+  <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
+  <parameter name="mmu_enabled" value="true" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="3" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave" value="sys_ddr3_cntrl.avl" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="false" />
+  <parameter name="setting_tmr_output_disable" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="0" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+   name="sys_ddr3_cntrl"
+   kind="altera_mem_if_ddr3_emif"
+   version="16.0"
+   enabled="1">
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="AVL_MAX_SIZE" value="256" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="MEM_CLK_FREQ" value="400.0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="666.667" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DQ_WIDTH" value="64" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="12" />
+  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
+  <parameter name="MEM_RTT_WR" value="RZQ/4" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_TCL" value="11" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_VENDOR" value="Micron" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="MEM_WTCL" value="8" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="RATE" value="Quarter" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="REF_CLK_FREQ" value="100.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="SPEED_GRADE" value="3" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="TIMING_TDQSCK" value="255" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+ </module>
+ <module name="sys_dma_clk" kind="clock_source" version="16.0" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="100000000" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module name="sys_ethernet" kind="altera_eth_tse" version="16.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="core_variation" value="MAC_ONLY" />
+  <parameter name="deviceFamilyName" value="Arria V" />
+  <parameter name="eg_addr" value="11" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="enable_gmii_loopback" value="false" />
+  <parameter name="enable_hd_logic" value="true" />
+  <parameter name="enable_mac_flow_ctrl" value="true" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="enable_sgmii" value="false" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="ing_addr" value="11" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="mdio_clk_div" value="30" />
+  <parameter name="nf_phyip_rcfg_enable" value="false" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="transceiver_type" value="NONE" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module
+   name="sys_ethernet_dma_rx"
+   kind="altera_msgdma"
+   version="16.0"
+   enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="BURST_ENABLE" value="1" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="256" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
+  <parameter name="ENHANCED_FEATURES" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="64" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="2" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="0" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="sys_ethernet_dma_tx"
+   kind="altera_msgdma"
+   version="16.0"
+   enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="BURST_ENABLE" value="1" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="256" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
+  <parameter name="ENHANCED_FEATURES" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="64" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="sys_gpio_bd"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_in"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_out"
+   kind="altera_avalon_pio"
+   version="16.0"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_id"
+   kind="altera_avalon_sysid_qsys"
+   version="16.0"
+   enabled="1">
+  <parameter name="id" value="182193580" />
+ </module>
+ <module
+   name="sys_int_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="16.0"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">system_bd_sys_int_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="163840" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="sys_pll" kind="altera_pll" version="16.0" enabled="1">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device" value="5AGTFD7K3F40I3" />
+  <parameter name="device_family" value="Arria V" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_device_speed_grade" value="1" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_number_of_clocks" value="3" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_output_clock_frequency0" value="125.0" />
+  <parameter name="gui_output_clock_frequency1" value="25.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="2.5" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="Off" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="100.0" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_locked" value="true" />
+ </module>
+ <module name="sys_spi" kind="altera_avalon_spi" version="16.0" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="0" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="100000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="8" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="128000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
+ <module
+   name="sys_timer_1"
+   kind="altera_avalon_timer"
+   version="16.0"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_timer_2"
+   kind="altera_avalon_timer"
+   version="16.0"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_tlb_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="16.0"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">system_bd_sys_tlb_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="163840" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module
+   name="sys_uart"
+   kind="altera_avalon_jtag_uart"
+   version="16.0"
+   enabled="1">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clkFreq" value="100000000" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module name="usdrx1_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
+  <parameter name="ADC_DATA_WIDTH" value="512" />
+  <parameter name="DMA_ADDRESS_WIDTH" value="10" />
+  <parameter name="DMA_DATA_WIDTH" value="512" />
+  <parameter name="DMA_READY_ENABLE" value="1" />
+ </module>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814f0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet.control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814e8" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="avl_usdrx1_xcvr.core_pll_reconfig">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10018000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181480" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10180800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.descriptor_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181440" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.descriptor_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181460" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="avl_usdrx1_xcvr.ip_reconfig">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10019000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="avl_phy_reconfig.reconfig_mgmt">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.response">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_timer_1.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181420" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_timer_2.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181520" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_gpio_bd.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_gpio_in.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_gpio_out.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181500" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_usdrx1_xcvr.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9671_core_0.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10050000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9671_core_1.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10060000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9671_core_2.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10070000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9671_core_3.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10080000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="axi_usdrx1_dma.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10090000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.data_master"
+   end="sys_spi.spi_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.instruction_master"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.instruction_master"
+   end="sys_cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10180800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.instruction_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="axi_usdrx1_dma.m_dest_axi"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_ethernet_dma_tx.mm_read"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_ethernet_dma_rx.mm_write"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.tightly_coupled_data_master_0"
+   end="sys_tlb_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_cpu.tightly_coupled_instruction_master_0"
+   end="sys_tlb_mem.s2">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="16.0"
+   start="sys_ethernet.receive"
+   end="sys_ethernet_dma_rx.st_sink" />
+ <connection
+   kind="avalon_streaming"
+   version="16.0"
+   start="sys_ethernet_dma_tx.st_source"
+   end="sys_ethernet.transmit" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_ddr3_cntrl.afi_clk"
+   end="sys_dma_clk.clk_in" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_cpu.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_id.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_timer_1.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_timer_2.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_uart.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_bd.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_in.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_gpio_out.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_spi.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_tlb_mem.clk1" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_tlb_mem.clk2" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet_dma_rx.clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet_dma_tx.clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet.control_port_clock_connection" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="usdrx1_adcfifo.if_dma_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="axi_usdrx1_dma.if_s_axis_aclk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_dma_clk.clk"
+   end="axi_usdrx1_dma.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="avl_phy_reconfig.mgmt_clk_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ddr3_cntrl.pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet.receive_clock_connection" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_pll.refclk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_usdrx1_xcvr.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9671_core_0.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9671_core_1.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9671_core_2.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_ad9671_core_3.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="axi_usdrx1_dma.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="avl_usdrx1_xcvr.sys_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.clk"
+   end="sys_ethernet.transmit_clock_connection" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_usdrx1_xcvr.core_clk"
+   end="usdrx1_adcfifo.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_usdrx1_xcvr.core_clk"
+   end="axi_ad9671_core_0.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_usdrx1_xcvr.core_clk"
+   end="axi_ad9671_core_1.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_usdrx1_xcvr.core_clk"
+   end="axi_ad9671_core_2.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_usdrx1_xcvr.core_clk"
+   end="axi_ad9671_core_3.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="avl_usdrx1_xcvr.core_clk"
+   end="rx_core_clk.in_clk" />
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch0_0_to_xcvr"
+   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch1_1_to_xcvr"
+   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch2_2_to_xcvr"
+   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch3_3_to_xcvr"
+   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch4_4_to_xcvr"
+   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_4">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch5_5_to_xcvr"
+   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_5">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch6_6_to_xcvr"
+   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_6">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_phy_reconfig.ch7_7_to_xcvr"
+   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_7">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_usdrx1_xcvr.core_pll_locked"
+   end="avl_usdrx1_xcvr.core_pll_locked">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="usdrx1_adcfifo.if_dma_wdata"
+   end="axi_usdrx1_dma.if_s_axis_data">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="usdrx1_adcfifo.if_dma_wr"
+   end="axi_usdrx1_dma.if_s_axis_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="usdrx1_adcfifo.if_dma_wready"
+   end="axi_usdrx1_dma.if_s_axis_ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="usdrx1_adcfifo.if_dma_xfer_req"
+   end="axi_usdrx1_dma.if_s_axis_xfer_req">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_0"
+   end="avl_phy_reconfig.ch0_0_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_1"
+   end="avl_phy_reconfig.ch1_1_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_2"
+   end="avl_phy_reconfig.ch2_2_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_3"
+   end="avl_phy_reconfig.ch3_3_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_4"
+   end="avl_phy_reconfig.ch4_4_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_5"
+   end="avl_phy_reconfig.ch5_5_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_6"
+   end="avl_phy_reconfig.ch6_6_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_7"
+   end="avl_phy_reconfig.ch7_7_from_xcvr">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="avl_usdrx1_xcvr.ready"
+   end="axi_usdrx1_xcvr.ready">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_ethernet_dma_rx.csr_irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_ethernet_dma_tx.csr_irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="axi_usdrx1_dma.interrupt_sender">
+  <parameter name="irqNumber" value="11" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_uart.irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_timer_2.irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_timer_1.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_gpio_in.irq">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_cpu.irq"
+   end="sys_gpio_bd.irq">
+  <parameter name="irqNumber" value="6" />
+ </connection>
+ <connection kind="interrupt" version="16.0" start="sys_cpu.irq" end="sys_spi.irq">
+  <parameter name="irqNumber" value="7" />
+ </connection>
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_ddr3_cntrl.afi_reset"
+   end="sys_dma_clk.clk_in_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_cntrl.global_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="usdrx1_adcfifo.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_dma_clk.clk_reset"
+   end="usdrx1_adcfifo.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_dma_clk.clk_reset"
+   end="axi_usdrx1_dma.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="avl_phy_reconfig.mgmt_rst_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_pll.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_id.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_timer_1.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_timer_2.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_uart.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_bd.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_in.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio_out.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_spi.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_int_mem.reset1" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_tlb_mem.reset1" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_tlb_mem.reset2" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet.reset_connection" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet_dma_rx.reset_n" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet_dma_tx.reset_n" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_usdrx1_xcvr.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9671_core_0.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9671_core_1.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9671_core_2.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9671_core_3.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="axi_usdrx1_dma.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_cntrl.soft_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="avl_usdrx1_xcvr.sys_resetn" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_cpu.debug_reset_request"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="axi_usdrx1_xcvr.if_up_rst"
+   end="avl_usdrx1_xcvr.rst" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
+</system>
diff --git a/projects/usdrx1/a5gt/system_constr.sdc b/projects/usdrx1/a5gt/system_constr.sdc
index f77cb2bc6..fdfd94802 100644
--- a/projects/usdrx1/a5gt/system_constr.sdc
+++ b/projects/usdrx1/a5gt/system_constr.sdc
@@ -25,3 +25,5 @@ set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_r
 set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk}]
 
+set_false_path -from [get_clocks {sys_clk}] [get_nets *sysref_en*] \
+  -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
diff --git a/projects/usdrx1/a5gt/system_project.tcl b/projects/usdrx1/a5gt/system_project.tcl
index 75a7e0e78..8432b7f02 100644
--- a/projects/usdrx1/a5gt/system_project.tcl
+++ b/projects/usdrx1/a5gt/system_project.tcl
@@ -7,6 +7,7 @@ project_new usdrx1_a5gt -overwrite
 source "../../common/a5gt/a5gt_system_assign.tcl"
 
 set_global_assignment -name VERILOG_FILE ../common/usdrx1_spi.v
+set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v
 set_global_assignment -name VERILOG_FILE system_top.v
 set_global_assignment -name QSYS_FILE system_bd.qsys
 
diff --git a/projects/usdrx1/a5gt/system_qsys_script.tcl b/projects/usdrx1/a5gt/system_qsys_script.tcl
new file mode 100644
index 000000000..2b3c37731
--- /dev/null
+++ b/projects/usdrx1/a5gt/system_qsys_script.tcl
@@ -0,0 +1,4 @@
+set mmu_enabled 1
+set ad_hdl_dir /home/icsomort/Git/hdl
+set ad_phdl_dir /home/icsomort/Git/hdl
+source system_qsys.tcl
diff --git a/projects/usdrx1/a5gt/system_top.v b/projects/usdrx1/a5gt/system_top.v
index 60e6c4f84..2e7836be1 100644
--- a/projects/usdrx1/a5gt/system_top.v
+++ b/projects/usdrx1/a5gt/system_top.v
@@ -127,9 +127,6 @@ module system_top (
 
   reg     [  3:0]   phy_rst_cnt = 0;
   reg               phy_rst_reg = 0;
-  reg               rx_sysref_m1 = 'd0;
-  reg               rx_sysref_m2 = 'd0;
-  reg               rx_sysref_int = 'd0;
 
   // internal signals
 
@@ -198,13 +195,10 @@ module system_top (
 
   // sysref
 
-  assign rx_sysref = rx_sysref_int;
-
-  always @(posedge rx_clk) begin
-    rx_sysref_m1 <= gpio_o[32];
-    rx_sysref_m2 <= rx_sysref_m1;
-    rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
-  end
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[60]),
+    .sysref_out (rx_sysref));
 
   // spi (fanout buffers)
 
@@ -324,7 +318,7 @@ module system_top (
     .rx_ip_sof_3_export (rx_ip_sof),
     .rx_ref_clk_clk (ref_clk),
     .rx_sync_export (rx_sync),
-    .rx_sysref_export (rx_sysref_int),
+    .rx_sysref_export (rx_sysref),
     .sys_125m_clk_clk (sys_125m_clk),
     .sys_25m_clk_clk (sys_25m_clk),
     .sys_2m5_clk_clk (sys_2m5_clk),
diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl
index b2f3a2878..e742136c5 100644
--- a/projects/usdrx1/common/usdrx1_bd.tcl
+++ b/projects/usdrx1/common/usdrx1_bd.tcl
@@ -8,6 +8,7 @@ create_bd_port -dir O spi_clk_o
 create_bd_port -dir I spi_sdo_i
 create_bd_port -dir O spi_sdo_o
 create_bd_port -dir I spi_sdi_i
+create_bd_port -dir O rx_core_clk
 
 # adc peripherals
 
@@ -129,6 +130,7 @@ ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_0/rx_clk
 ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_1/rx_clk
 ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_2/rx_clk
 ad_connect  util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_3/rx_clk
+ad_connect  util_usdrx1_xcvr/rx_out_clk_0 rx_core_clk
 ad_connect  axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_0/rx_sof
 ad_connect  axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_1/rx_sof
 ad_connect  axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_2/rx_sof
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index e4d7d74f1..b7c6edfb0 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -19,6 +19,7 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
diff --git a/projects/usdrx1/zc706/system_project.tcl b/projects/usdrx1/zc706/system_project.tcl
index 59e382beb..30bcb0e78 100644
--- a/projects/usdrx1/zc706/system_project.tcl
+++ b/projects/usdrx1/zc706/system_project.tcl
@@ -11,6 +11,7 @@ adi_project_files usdrx1_zc706 [list \
   "system_constr.xdc" \
   "../common/usdrx1_spi.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v
index 334a2ea83..334e6b354 100644
--- a/projects/usdrx1/zc706/system_top.v
+++ b/projects/usdrx1/zc706/system_top.v
@@ -250,6 +250,7 @@ module system_top (
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
   wire    [15:0]  ps_intrs;
+  wire            rx_clk;
 
   // spi assignments
 
@@ -272,6 +273,7 @@ module system_top (
     .IB (rx_ref_clk_n),
     .O (rx_ref_clk),
     .ODIV2 ());
+
   OBUFDS i_obufds_rx_sysref (
     .I (rx_sysref),
     .O (rx_sysref_p),
@@ -326,6 +328,11 @@ module system_top (
     .spi_afe_sdio (spi_afe_sdio),
     .spi_clk_sdio (spi_clk_sdio));
 
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[60]),
+    .sysref_out (rx_sysref));
+
   system_wrapper i_system_wrapper (
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
@@ -407,6 +414,7 @@ module system_top (
     .rx_ref_clk_0 (rx_ref_clk),
     .rx_sync_0 (rx_sync),
     .rx_sysref_0 (rx_sysref),
+    .rx_core_clk (rx_clk),
     .spdif (spdif),
     .spi_clk_i (spi_clk),
     .spi_clk_o (spi_clk),

From da7f4608a842eacb169031eebea0f4b11d6c5b49 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Dec 2016 15:35:20 +0000
Subject: [PATCH 821/972] fmcjesdadc1/usdrx1: Clean up the mess

Delete accidentally commited generated files.
---
 .../fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld     |   14 -
 projects/fmcjesdadc1/a5gt/serv_req_info.txt   |    8 -
 projects/fmcjesdadc1/a5gt/system_bd.qsys      | 2404 ---------------
 .../system_bd_sys_ddr3_cntrl_p0_summary.csv   |   34 -
 .../fmcjesdadc1/a5gt/system_qsys_script.tcl   |    4 -
 .../fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld   |    9 -
 projects/fmcjesdadc1/a5soc/system_bd.qsys     | 1585 ----------
 .../fmcjesdadc1/a5soc/system_qsys_script.tcl  |    4 -
 projects/usdrx1/a5gt/serv_req_info.txt        |    8 -
 projects/usdrx1/a5gt/system_bd.qsys           | 2599 -----------------
 projects/usdrx1/a5gt/system_qsys_script.tcl   |    4 -
 11 files changed, 6673 deletions(-)
 delete mode 100644 projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld
 delete mode 100644 projects/fmcjesdadc1/a5gt/serv_req_info.txt
 delete mode 100644 projects/fmcjesdadc1/a5gt/system_bd.qsys
 delete mode 100644 projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv
 delete mode 100644 projects/fmcjesdadc1/a5gt/system_qsys_script.tcl
 delete mode 100644 projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld
 delete mode 100644 projects/fmcjesdadc1/a5soc/system_bd.qsys
 delete mode 100644 projects/fmcjesdadc1/a5soc/system_qsys_script.tcl
 delete mode 100644 projects/usdrx1/a5gt/serv_req_info.txt
 delete mode 100644 projects/usdrx1/a5gt/system_bd.qsys
 delete mode 100644 projects/usdrx1/a5gt/system_qsys_script.tcl

diff --git a/projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld b/projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld
deleted file mode 100644
index 21406e592..000000000
--- a/projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld
+++ /dev/null
@@ -1,14 +0,0 @@
-<sld_project_info>
-  <sld_infos>
-    <sld_info hpath="system_bd:i_system_bd" name="i_system_bd">
-      <assignment_values>
-        <assignment_value text="QSYS_NAME system_bd HAS_SOPCINFO 1 GENERATION_ID 1482148783"/>
-      </assignment_values>
-    </sld_info>
-    <sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
-      <assignment_values>
-        <assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
-      </assignment_values>
-    </sld_info>
-  </sld_infos>
-</sld_project_info>
diff --git a/projects/fmcjesdadc1/a5gt/serv_req_info.txt b/projects/fmcjesdadc1/a5gt/serv_req_info.txt
deleted file mode 100644
index 98d3a1b02..000000000
--- a/projects/fmcjesdadc1/a5gt/serv_req_info.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-<internal_error>
-	<executable>quartus_sta</executable>
-	<sub_system>MEM</sub_system>
-	<error>*** Fatal Error: Out of memory in module quartus_sta (4171 megabytes used)</error>
-	<date>Mon Dec 19 12:41:45 2016</date>
-	<version>Version 16.0.2 Build 222 07/20/2016 SJ Standard Edition</version>
-</internal_error>
-
diff --git a/projects/fmcjesdadc1/a5gt/system_bd.qsys b/projects/fmcjesdadc1/a5gt/system_bd.qsys
deleted file mode 100644
index 2da679b31..000000000
--- a/projects/fmcjesdadc1/a5gt/system_bd.qsys
+++ /dev/null
@@ -1,2404 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element ad9250_adcfifo
-   {
-      datum _sortIndex
-      {
-         value = "23";
-         type = "int";
-      }
-   }
-   element avl_ad9250_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-   }
-   element avl_phy_reconfig
-   {
-      datum _sortIndex
-      {
-         value = "26";
-         type = "int";
-      }
-   }
-   element axi_ad9250_core_0
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-   }
-   element axi_ad9250_core_1
-   {
-      datum _sortIndex
-      {
-         value = "21";
-         type = "int";
-      }
-   }
-   element axi_ad9250_dma
-   {
-      datum _sortIndex
-      {
-         value = "24";
-         type = "int";
-      }
-   }
-   element axi_ad9250_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-   }
-   element rx_core_clk
-   {
-      datum _sortIndex
-      {
-         value = "25";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_cpu
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element sys_ddr3_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-   element sys_dma_clk
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element sys_ethernet
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element sys_ethernet_dma_rx
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element sys_ethernet_dma_tx
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element sys_gpio_bd
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element sys_gpio_in
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-   }
-   element sys_gpio_out
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element sys_pll
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element sys_spi
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-   }
-   element sys_timer_1
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element sys_timer_2
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element sys_tlb_mem
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element sys_uart
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element util_ad9250_cpack
-   {
-      datum _sortIndex
-      {
-         value = "22";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="5AGTFD7K3F40I3" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="rx_core_clk"
-   internal="rx_core_clk.out_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="rx_data_0"
-   internal="avl_ad9250_xcvr.rx_data_0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_1"
-   internal="avl_ad9250_xcvr.rx_data_1"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_2"
-   internal="avl_ad9250_xcvr.rx_data_2"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_3"
-   internal="avl_ad9250_xcvr.rx_data_3"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_data"
-   internal="avl_ad9250_xcvr.ip_data"
-   type="avalon_streaming"
-   dir="start" />
- <interface
-   name="rx_ip_data_0"
-   internal="axi_ad9250_core_0.if_rx_data"
-   type="avalon_streaming"
-   dir="end" />
- <interface
-   name="rx_ip_data_1"
-   internal="axi_ad9250_core_1.if_rx_data"
-   type="avalon_streaming"
-   dir="end" />
- <interface
-   name="rx_ip_sof"
-   internal="avl_ad9250_xcvr.ip_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_sof_0"
-   internal="axi_ad9250_core_0.if_rx_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_sof_1"
-   internal="axi_ad9250_core_1.if_rx_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ref_clk"
-   internal="avl_ad9250_xcvr.ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="rx_sync"
-   internal="avl_ad9250_xcvr.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sysref"
-   internal="avl_ad9250_xcvr.sysref"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_125m_clk"
-   internal="sys_pll.outclk0"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_25m_clk"
-   internal="sys_pll.outclk1"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_2m5_clk"
-   internal="sys_pll.outclk2"
-   type="clock"
-   dir="start" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_ddr3_cntrl_mem"
-   internal="sys_ddr3_cntrl.memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ddr3_cntrl_oct"
-   internal="sys_ddr3_cntrl.oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_mdio"
-   internal="sys_ethernet.mac_mdio_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_rgmii"
-   internal="sys_ethernet.mac_rgmii_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_rx_clk"
-   internal="sys_ethernet.pcs_mac_rx_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_ethernet_status"
-   internal="sys_ethernet.mac_status_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_tx_clk"
-   internal="sys_ethernet.pcs_mac_tx_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_gpio_bd"
-   internal="sys_gpio_bd.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_in"
-   internal="sys_gpio_in.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_out"
-   internal="sys_gpio_out.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_pll_locked"
-   internal="sys_pll.locked"
-   type="conduit"
-   dir="end" />
- <interface name="sys_rst" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
- <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module name="ad9250_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
-  <parameter name="ADC_DATA_WIDTH" value="128" />
-  <parameter name="DMA_ADDRESS_WIDTH" value="16" />
-  <parameter name="DMA_DATA_WIDTH" value="128" />
-  <parameter name="DMA_READY_ENABLE" value="1" />
- </module>
- <module name="avl_ad9250_xcvr" kind="avl_adxcvr" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="CORECLK_FREQUENCY" value="125.0" />
-  <parameter name="DEVICE_FAMILY" value="Arria V" />
-  <parameter name="FRM_BCNT" value="4" />
-  <parameter name="FRM_SCNT" value="1" />
-  <parameter name="HD" value="0" />
-  <parameter name="ID" value="1" />
-  <parameter name="LANE_RATE" value="5000.0" />
-  <parameter name="MF_FCNT" value="32" />
-  <parameter name="NUM_OF_CONVS" value="4" />
-  <parameter name="NUM_OF_LANES" value="4" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PLLCLK_FREQUENCY" value="2500.0" />
-  <parameter name="REFCLK_FREQUENCY" value="250.0" />
-  <parameter name="SYSCLK_FREQUENCY" value="100.0" />
-  <parameter name="TX_OR_RX_N" value="0" />
- </module>
- <module
-   name="avl_phy_reconfig"
-   kind="alt_xcvr_reconfig"
-   version="16.0"
-   enabled="1">
-  <parameter name="ber_en" value="0" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="enable_adce" value="0" />
-  <parameter name="enable_analog" value="1" />
-  <parameter name="enable_dcd" value="0" />
-  <parameter name="enable_dcd_power_up" value="1" />
-  <parameter name="enable_dfe" value="0" />
-  <parameter name="enable_eyemon" value="0" />
-  <parameter name="enable_mif" value="0" />
-  <parameter name="enable_offset" value="1" />
-  <parameter name="gui_cal_status_port" value="false" />
-  <parameter name="gui_enable_pll" value="0" />
-  <parameter name="gui_split_sizes" value="1,1,1,1" />
-  <parameter name="number_of_reconfig_interfaces" value="4" />
- </module>
- <module name="axi_ad9250_core_0" kind="axi_ad9250" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="1" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_ad9250_core_1" kind="axi_ad9250" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="1" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_ad9250_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="1" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_ad9250_xcvr" kind="axi_adxcvr" version="1.0" enabled="1">
-  <parameter name="ID" value="1" />
-  <parameter name="NUM_OF_LANES" value="4" />
-  <parameter name="TX_OR_RX_N" value="0" />
- </module>
- <module
-   name="rx_core_clk"
-   kind="altera_clock_bridge"
-   version="16.0"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="125" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_clk" kind="clock_source" version="16.0" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="DEASSERT" />
- </module>
- <module name="sys_cpu" kind="altera_nios2_gen2" version="16.0" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="bht_ramBlockType" value="Automatic" />
-  <parameter name="breakOffset" value="32" />
-  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
-  <parameter name="cdx_enabled" value="false" />
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="cpuArchRev" value="1" />
-  <parameter name="cpuID" value="0" />
-  <parameter name="cpuReset" value="false" />
-  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
-  <parameter name="dataAddrWidth" value="29" />
-  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='avl_phy_reconfig.reconfig_mgmt' start='0x10010000' end='0x10010200' type='alt_xcvr_reconfig.reconfig_mgmt' /><slave name='avl_ad9250_xcvr.core_pll_reconfig' start='0x10018000' end='0x10018100' type='avl_adxcvr.core_pll_reconfig' /><slave name='avl_ad9250_xcvr.ip_reconfig' start='0x10019000' end='0x10019400' type='avl_adxcvr.ip_reconfig' /><slave name='axi_ad9250_xcvr.s_axi' start='0x10020000' end='0x10030000' type='axi_adxcvr.s_axi' /><slave name='axi_ad9250_core_0.s_axi' start='0x10050000' end='0x10060000' type='axi_ad9250.s_axi' /><slave name='axi_ad9250_core_1.s_axi' start='0x10060000' end='0x10070000' type='axi_ad9250.s_axi' /><slave name='axi_ad9250_dma.s_axi' start='0x10070000' end='0x10074000' type='axi_dmac.s_axi' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer_1.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
-  <parameter name="data_master_high_performance_paddr_base" value="0" />
-  <parameter name="data_master_high_performance_paddr_size" value="0" />
-  <parameter name="data_master_paddr_base" value="0" />
-  <parameter name="data_master_paddr_size" value="0" />
-  <parameter name="dcache_bursts" value="false" />
-  <parameter name="dcache_numTCDM" value="1" />
-  <parameter name="dcache_ramBlockType" value="Automatic" />
-  <parameter name="dcache_size" value="32768" />
-  <parameter name="dcache_tagramBlockType" value="Automatic" />
-  <parameter name="dcache_victim_buf_impl" value="ram" />
-  <parameter name="debug_OCIOnchipTrace" value="_128" />
-  <parameter name="debug_assignJtagInstanceID" value="false" />
-  <parameter name="debug_datatrigger" value="0" />
-  <parameter name="debug_debugReqSignals" value="false" />
-  <parameter name="debug_enabled" value="true" />
-  <parameter name="debug_hwbreakpoint" value="0" />
-  <parameter name="debug_jtagInstanceID" value="0" />
-  <parameter name="debug_traceStorage" value="onchip_trace" />
-  <parameter name="debug_traceType" value="none" />
-  <parameter name="debug_triggerArming" value="true" />
-  <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dividerType" value="no_div" />
-  <parameter name="exceptionOffset" value="32" />
-  <parameter name="exceptionSlave" value="sys_ddr3_cntrl.avl" />
-  <parameter name="faAddrWidth" value="1" />
-  <parameter name="faSlaveMapParam" value="" />
-  <parameter name="fa_cache_line" value="2" />
-  <parameter name="fa_cache_linesize" value="0" />
-  <parameter name="flash_instruction_master_paddr_base" value="0" />
-  <parameter name="flash_instruction_master_paddr_size" value="0" />
-  <parameter name="icache_burstType" value="None" />
-  <parameter name="icache_numTCIM" value="1" />
-  <parameter name="icache_ramBlockType" value="Automatic" />
-  <parameter name="icache_size" value="32768" />
-  <parameter name="icache_tagramBlockType" value="Automatic" />
-  <parameter name="impl" value="Fast" />
-  <parameter name="instAddrWidth" value="29" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
-  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
-  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
-  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
-  <parameter name="instruction_master_paddr_base" value="0" />
-  <parameter name="instruction_master_paddr_size" value="0" />
-  <parameter name="internalIrqMaskSystemInfo" value="2303" />
-  <parameter name="io_regionbase" value="0" />
-  <parameter name="io_regionsize" value="0" />
-  <parameter name="master_addr_map" value="false" />
-  <parameter name="mmu_TLBMissExcOffset" value="4096" />
-  <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
-  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="true" />
-  <parameter name="mmu_processIDNumBits" value="8" />
-  <parameter name="mmu_ramBlockType" value="Automatic" />
-  <parameter name="mmu_tlbNumWays" value="16" />
-  <parameter name="mmu_tlbPtrSz" value="7" />
-  <parameter name="mmu_udtlbNumEntries" value="6" />
-  <parameter name="mmu_uitlbNumEntries" value="4" />
-  <parameter name="mpu_enabled" value="false" />
-  <parameter name="mpu_minDataRegionSize" value="12" />
-  <parameter name="mpu_minInstRegionSize" value="12" />
-  <parameter name="mpu_numOfDataRegion" value="8" />
-  <parameter name="mpu_numOfInstRegion" value="8" />
-  <parameter name="mpu_useLimit" value="false" />
-  <parameter name="mpx_enabled" value="false" />
-  <parameter name="mul_32_impl" value="3" />
-  <parameter name="mul_64_impl" value="0" />
-  <parameter name="mul_shift_choice" value="0" />
-  <parameter name="ocimem_ramBlockType" value="Automatic" />
-  <parameter name="ocimem_ramInit" value="false" />
-  <parameter name="regfile_ramBlockType" value="Automatic" />
-  <parameter name="resetOffset" value="0" />
-  <parameter name="resetSlave" value="sys_ddr3_cntrl.avl" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="setting_HBreakTest" value="false" />
-  <parameter name="setting_HDLSimCachesCleared" value="true" />
-  <parameter name="setting_activateMonitors" value="true" />
-  <parameter name="setting_activateTestEndChecker" value="false" />
-  <parameter name="setting_activateTrace" value="true" />
-  <parameter name="setting_allow_break_inst" value="false" />
-  <parameter name="setting_alwaysEncrypt" value="true" />
-  <parameter name="setting_asic_add_scan_mode_input" value="false" />
-  <parameter name="setting_asic_enabled" value="false" />
-  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
-  <parameter name="setting_asic_third_party_synthesis" value="false" />
-  <parameter name="setting_avalonDebugPortPresent" value="false" />
-  <parameter name="setting_bhtPtrSz" value="8" />
-  <parameter name="setting_bigEndian" value="false" />
-  <parameter name="setting_branchpredictiontype" value="Dynamic" />
-  <parameter name="setting_breakslaveoveride" value="false" />
-  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
-  <parameter name="setting_dc_ecc_present" value="false" />
-  <parameter name="setting_disable_tmr_inj" value="false" />
-  <parameter name="setting_disableocitrace" value="false" />
-  <parameter name="setting_dtcm_ecc_present" value="false" />
-  <parameter name="setting_ecc_present" value="false" />
-  <parameter name="setting_ecc_sim_test_ports" value="false" />
-  <parameter name="setting_exportHostDebugPort" value="false" />
-  <parameter name="setting_exportPCB" value="false" />
-  <parameter name="setting_export_large_RAMs" value="false" />
-  <parameter name="setting_exportdebuginfo" value="false" />
-  <parameter name="setting_exportvectors" value="false" />
-  <parameter name="setting_fast_register_read" value="false" />
-  <parameter name="setting_ic_ecc_present" value="true" />
-  <parameter name="setting_interruptControllerType" value="Internal" />
-  <parameter name="setting_itcm_ecc_present" value="false" />
-  <parameter name="setting_mmu_ecc_present" value="true" />
-  <parameter name="setting_oci_export_jtag_signals" value="false" />
-  <parameter name="setting_oci_version" value="1" />
-  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
-  <parameter name="setting_removeRAMinit" value="false" />
-  <parameter name="setting_rf_ecc_present" value="true" />
-  <parameter name="setting_shadowRegisterSets" value="0" />
-  <parameter name="setting_showInternalSettings" value="false" />
-  <parameter name="setting_showUnpublishedSettings" value="false" />
-  <parameter name="setting_support31bitdcachebypass" value="false" />
-  <parameter name="setting_tmr_output_disable" value="false" />
-  <parameter name="setting_usedesignware" value="false" />
-  <parameter name="shift_rot_impl" value="0" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
-  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
-  <parameter name="tmr_enabled" value="false" />
-  <parameter name="tracefilename" value="" />
-  <parameter name="userDefinedSettings" value="" />
- </module>
- <module
-   name="sys_ddr3_cntrl"
-   kind="altera_mem_if_ddr3_emif"
-   version="16.0"
-   enabled="1">
-  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-  <parameter name="AC_PACKAGE_DESKEW" value="false" />
-  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-  <parameter name="ADDR_ORDER" value="0" />
-  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
-  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-  <parameter name="ADVANCED_CK_PHASES" value="false" />
-  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
-  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-  <parameter name="AP_MODE" value="false" />
-  <parameter name="AP_MODE_EN" value="0" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_PD_CYCLES" value="0" />
-  <parameter name="AUTO_POWERDN_EN" value="false" />
-  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-  <parameter name="AVL_MAX_SIZE" value="256" />
-  <parameter name="BYTE_ENABLE" value="true" />
-  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="CALIBRATION_MODE" value="Skip" />
-  <parameter name="CALIB_REG_WIDTH" value="8" />
-  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-  <parameter name="CFG_REORDER_DATA" value="true" />
-  <parameter name="CFG_TCCD_NS" value="2.5" />
-  <parameter name="COMMAND_PHASE" value="0.0" />
-  <parameter name="CONTROLLER_LATENCY" value="5" />
-  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
-  <parameter name="CTL_AUTOPCH_EN" value="false" />
-  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
-  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="CTL_CSR_ENABLED" value="false" />
-  <parameter name="CTL_CSR_READ_ONLY" value="1" />
-  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
-  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-  <parameter name="CTL_ECC_ENABLED" value="false" />
-  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
-  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
-  <parameter name="CTL_HRB_ENABLED" value="false" />
-  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTL_USR_REFRESH_EN" value="false" />
-  <parameter name="CTL_ZQCAL_EN" value="false" />
-  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
-  <parameter name="DAT_DATA_WIDTH" value="32" />
-  <parameter name="DEBUG_MODE" value="false" />
-  <parameter name="DEVICE_DEPTH" value="1" />
-  <parameter name="DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
-  <parameter name="DISCRETE_FLY_BY" value="true" />
-  <parameter name="DLL_SHARING_MODE" value="None" />
-  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
-  <parameter name="DUPLICATE_AC" value="false" />
-  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
-  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-  <parameter name="ENABLE_BONDING" value="false" />
-  <parameter name="ENABLE_BURST_MERGE" value="false" />
-  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
-  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
-  <parameter name="ENABLE_ISS_PROBES" value="false" />
-  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
-  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-  <parameter name="ENABLE_USER_ECC" value="false" />
-  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
-  <parameter name="EXTRA_SETTINGS" value="" />
-  <parameter name="FIX_READ_LATENCY" value="8" />
-  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
-  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
-  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-  <parameter name="HARD_EMIF" value="false" />
-  <parameter name="HCX_COMPAT_MODE" value="false" />
-  <parameter name="HHP_HPS" value="false" />
-  <parameter name="HHP_HPS_SIMULATION" value="false" />
-  <parameter name="HHP_HPS_VERIFICATION" value="false" />
-  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
-  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="IS_ES_DEVICE" value="false" />
-  <parameter name="LOCAL_ID_WIDTH" value="8" />
-  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
-  <parameter name="MARGIN_VARIATION_TEST" value="false" />
-  <parameter name="MAX_PENDING_RD_CMD" value="32" />
-  <parameter name="MAX_PENDING_WR_CMD" value="16" />
-  <parameter name="MEM_ASR" value="Manual" />
-  <parameter name="MEM_ATCL" value="Disabled" />
-  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
-  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
-  <parameter name="MEM_BL" value="OTF" />
-  <parameter name="MEM_BT" value="Sequential" />
-  <parameter name="MEM_CK_PHASE" value="0.0" />
-  <parameter name="MEM_CK_WIDTH" value="1" />
-  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
-  <parameter name="MEM_CLK_FREQ" value="400.0" />
-  <parameter name="MEM_CLK_FREQ_MAX" value="666.667" />
-  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_CS_WIDTH" value="1" />
-  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
-  <parameter name="MEM_DLL_EN" value="true" />
-  <parameter name="MEM_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DQ_WIDTH" value="64" />
-  <parameter name="MEM_DRV_STR" value="RZQ/6" />
-  <parameter name="MEM_FORMAT" value="DISCRETE" />
-  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
-  <parameter name="MEM_IF_DQSN_EN" value="true" />
-  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-  <parameter name="MEM_INIT_EN" value="false" />
-  <parameter name="MEM_INIT_FILE" value="" />
-  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
-  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_PD" value="DLL off" />
-  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-  <parameter name="MEM_ROW_ADDR_WIDTH" value="12" />
-  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
-  <parameter name="MEM_RTT_WR" value="RZQ/4" />
-  <parameter name="MEM_SRT" value="Normal" />
-  <parameter name="MEM_TCL" value="11" />
-  <parameter name="MEM_TFAW_NS" value="30.0" />
-  <parameter name="MEM_TINIT_US" value="500" />
-  <parameter name="MEM_TMRD_CK" value="4" />
-  <parameter name="MEM_TRAS_NS" value="35.0" />
-  <parameter name="MEM_TRCD_NS" value="13.75" />
-  <parameter name="MEM_TREFI_US" value="7.8" />
-  <parameter name="MEM_TRFC_NS" value="110.0" />
-  <parameter name="MEM_TRP_NS" value="13.75" />
-  <parameter name="MEM_TRRD_NS" value="6.0" />
-  <parameter name="MEM_TRTP_NS" value="7.5" />
-  <parameter name="MEM_TWR_NS" value="15.0" />
-  <parameter name="MEM_TWTR" value="6" />
-  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
-  <parameter name="MEM_VENDOR" value="Micron" />
-  <parameter name="MEM_VERBOSE" value="true" />
-  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
-  <parameter name="MEM_WTCL" value="8" />
-  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-  <parameter name="MULTICAST_EN" value="false" />
-  <parameter name="NEXTGEN" value="true" />
-  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
-  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
-  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_OF_PORTS" value="1" />
-  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
-  <parameter name="OCT_SHARING_MODE" value="None" />
-  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="PACKAGE_DESKEW" value="false" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="PHY_CSR_ENABLED" value="false" />
-  <parameter name="PHY_ONLY" value="false" />
-  <parameter name="PINGPONGPHY_EN" value="false" />
-  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
-  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_LOCATION" value="Top_Bottom" />
-  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_SHARING_MODE" value="None" />
-  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="POWER_OF_TWO_BUS" value="false" />
-  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-  <parameter name="RATE" value="Quarter" />
-  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-  <parameter name="READ_FIFO_SIZE" value="8" />
-  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
-  <parameter name="REFRESH_INTERVAL" value="15000" />
-  <parameter name="REF_CLK_FREQ" value="100.0" />
-  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-  <parameter name="SEQUENCER_TYPE" value="NIOS" />
-  <parameter name="SEQ_MODE" value="0" />
-  <parameter name="SKIP_MEM_INIT" value="true" />
-  <parameter name="SOPC_COMPAT_RESET" value="false" />
-  <parameter name="SPEED_GRADE" value="3" />
-  <parameter name="STARVE_LIMIT" value="10" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
-  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_TDH" value="0.0" />
-  <parameter name="TIMING_BOARD_TDS" value="0.0" />
-  <parameter name="TIMING_BOARD_TIH" value="0.0" />
-  <parameter name="TIMING_BOARD_TIS" value="0.0" />
-  <parameter name="TIMING_TDH" value="45" />
-  <parameter name="TIMING_TDQSCK" value="255" />
-  <parameter name="TIMING_TDQSCKDL" value="1200" />
-  <parameter name="TIMING_TDQSCKDM" value="900" />
-  <parameter name="TIMING_TDQSCKDS" value="450" />
-  <parameter name="TIMING_TDQSQ" value="100" />
-  <parameter name="TIMING_TDQSS" value="0.27" />
-  <parameter name="TIMING_TDS" value="10" />
-  <parameter name="TIMING_TDSH" value="0.18" />
-  <parameter name="TIMING_TDSS" value="0.18" />
-  <parameter name="TIMING_TIH" value="120" />
-  <parameter name="TIMING_TIS" value="170" />
-  <parameter name="TIMING_TQH" value="0.38" />
-  <parameter name="TIMING_TQSH" value="0.4" />
-  <parameter name="TRACKING_ERROR_TEST" value="false" />
-  <parameter name="TRACKING_WATCH_TEST" value="false" />
-  <parameter name="TREFI" value="35100" />
-  <parameter name="TRFC" value="350" />
-  <parameter name="USER_DEBUG_LEVEL" value="1" />
-  <parameter name="USE_AXI_ADAPTOR" value="false" />
-  <parameter name="USE_FAKE_PHY" value="false" />
-  <parameter name="USE_MEM_CLK_FREQ" value="false" />
-  <parameter name="USE_MM_ADAPTOR" value="true" />
-  <parameter name="USE_SEQUENCER_BFM" value="false" />
-  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
- </module>
- <module name="sys_dma_clk" kind="clock_source" version="16.0" enabled="1">
-  <parameter name="clockFrequency" value="50000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="100000000" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <module name="sys_ethernet" kind="altera_eth_tse" version="16.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="core_variation" value="MAC_ONLY" />
-  <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="eg_addr" value="11" />
-  <parameter name="ena_hash" value="false" />
-  <parameter name="enable_alt_reconfig" value="false" />
-  <parameter name="enable_ecc" value="false" />
-  <parameter name="enable_ena" value="32" />
-  <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_hd_logic" value="true" />
-  <parameter name="enable_mac_flow_ctrl" value="true" />
-  <parameter name="enable_mac_vlan" value="false" />
-  <parameter name="enable_magic_detect" value="true" />
-  <parameter name="enable_ptp_1step" value="false" />
-  <parameter name="enable_sgmii" value="false" />
-  <parameter name="enable_shift16" value="true" />
-  <parameter name="enable_sup_addr" value="false" />
-  <parameter name="enable_timestamping" value="false" />
-  <parameter name="enable_use_internal_fifo" value="true" />
-  <parameter name="export_pwrdn" value="false" />
-  <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ifGMII" value="RGMII" />
-  <parameter name="ing_addr" value="11" />
-  <parameter name="max_channels" value="1" />
-  <parameter name="mdio_clk_div" value="30" />
-  <parameter name="nf_phyip_rcfg_enable" value="false" />
-  <parameter name="phy_identifier" value="0" />
-  <parameter name="phyip_en_synce_support" value="false" />
-  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
-  <parameter name="phyip_pll_type" value="CMU" />
-  <parameter name="phyip_pma_bonding_mode" value="x1" />
-  <parameter name="starting_channel_number" value="0" />
-  <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="transceiver_type" value="NONE" />
-  <parameter name="tstamp_fp_width" value="4" />
-  <parameter name="useMDIO" value="true" />
-  <parameter name="use_mac_clken" value="false" />
-  <parameter name="use_misc_ports" value="true" />
- </module>
- <module
-   name="sys_ethernet_dma_rx"
-   kind="altera_msgdma"
-   version="16.0"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="6" />
-  <parameter name="EXPOSE_ST_PORT" value="0" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="2" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="0" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_ethernet_dma_tx"
-   kind="altera_msgdma"
-   version="16.0"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="1" />
-  <parameter name="EXPOSE_ST_PORT" value="0" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="1" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="2" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_gpio_bd"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_in"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_out"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="16.0"
-   enabled="1">
-  <parameter name="id" value="182193580" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="16.0"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">system_bd_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="dataWidth2" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="enableDiffWidth" value="false" />
-  <parameter name="initMemContent" value="false" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="163840" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module name="sys_pll" kind="altera_pll" version="16.0" enabled="1">
-  <parameter name="debug_print_output" value="false" />
-  <parameter name="debug_use_rbc_taf_method" value="false" />
-  <parameter name="device" value="5AGTFD7K3F40I3" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
-  <parameter name="gui_actual_phase_shift0" value="0" />
-  <parameter name="gui_actual_phase_shift1" value="0" />
-  <parameter name="gui_actual_phase_shift10" value="0" />
-  <parameter name="gui_actual_phase_shift11" value="0" />
-  <parameter name="gui_actual_phase_shift12" value="0" />
-  <parameter name="gui_actual_phase_shift13" value="0" />
-  <parameter name="gui_actual_phase_shift14" value="0" />
-  <parameter name="gui_actual_phase_shift15" value="0" />
-  <parameter name="gui_actual_phase_shift16" value="0" />
-  <parameter name="gui_actual_phase_shift17" value="0" />
-  <parameter name="gui_actual_phase_shift2" value="0" />
-  <parameter name="gui_actual_phase_shift3" value="0" />
-  <parameter name="gui_actual_phase_shift4" value="0" />
-  <parameter name="gui_actual_phase_shift5" value="0" />
-  <parameter name="gui_actual_phase_shift6" value="0" />
-  <parameter name="gui_actual_phase_shift7" value="0" />
-  <parameter name="gui_actual_phase_shift8" value="0" />
-  <parameter name="gui_actual_phase_shift9" value="0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_channel_spacing" value="0.0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_device_speed_grade" value="1" />
-  <parameter name="gui_divide_factor_c0" value="1" />
-  <parameter name="gui_divide_factor_c1" value="1" />
-  <parameter name="gui_divide_factor_c10" value="1" />
-  <parameter name="gui_divide_factor_c11" value="1" />
-  <parameter name="gui_divide_factor_c12" value="1" />
-  <parameter name="gui_divide_factor_c13" value="1" />
-  <parameter name="gui_divide_factor_c14" value="1" />
-  <parameter name="gui_divide_factor_c15" value="1" />
-  <parameter name="gui_divide_factor_c16" value="1" />
-  <parameter name="gui_divide_factor_c17" value="1" />
-  <parameter name="gui_divide_factor_c2" value="1" />
-  <parameter name="gui_divide_factor_c3" value="1" />
-  <parameter name="gui_divide_factor_c4" value="1" />
-  <parameter name="gui_divide_factor_c5" value="1" />
-  <parameter name="gui_divide_factor_c6" value="1" />
-  <parameter name="gui_divide_factor_c7" value="1" />
-  <parameter name="gui_divide_factor_c8" value="1" />
-  <parameter name="gui_divide_factor_c9" value="1" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50" />
-  <parameter name="gui_duty_cycle1" value="50" />
-  <parameter name="gui_duty_cycle10" value="50" />
-  <parameter name="gui_duty_cycle11" value="50" />
-  <parameter name="gui_duty_cycle12" value="50" />
-  <parameter name="gui_duty_cycle13" value="50" />
-  <parameter name="gui_duty_cycle14" value="50" />
-  <parameter name="gui_duty_cycle15" value="50" />
-  <parameter name="gui_duty_cycle16" value="50" />
-  <parameter name="gui_duty_cycle17" value="50" />
-  <parameter name="gui_duty_cycle2" value="50" />
-  <parameter name="gui_duty_cycle3" value="50" />
-  <parameter name="gui_duty_cycle4" value="50" />
-  <parameter name="gui_duty_cycle5" value="50" />
-  <parameter name="gui_duty_cycle6" value="50" />
-  <parameter name="gui_duty_cycle7" value="50" />
-  <parameter name="gui_duty_cycle8" value="50" />
-  <parameter name="gui_duty_cycle9" value="50" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_number_of_clocks" value="3" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="125.0" />
-  <parameter name="gui_output_clock_frequency1" value="25.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="2.5" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0" />
-  <parameter name="gui_phase_shift1" value="0" />
-  <parameter name="gui_phase_shift10" value="0" />
-  <parameter name="gui_phase_shift11" value="0" />
-  <parameter name="gui_phase_shift12" value="0" />
-  <parameter name="gui_phase_shift13" value="0" />
-  <parameter name="gui_phase_shift14" value="0" />
-  <parameter name="gui_phase_shift15" value="0" />
-  <parameter name="gui_phase_shift16" value="0" />
-  <parameter name="gui_phase_shift17" value="0" />
-  <parameter name="gui_phase_shift2" value="0" />
-  <parameter name="gui_phase_shift3" value="0" />
-  <parameter name="gui_phase_shift4" value="0" />
-  <parameter name="gui_phase_shift5" value="0" />
-  <parameter name="gui_phase_shift6" value="0" />
-  <parameter name="gui_phase_shift7" value="0" />
-  <parameter name="gui_phase_shift8" value="0" />
-  <parameter name="gui_phase_shift9" value="0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="Off" />
-  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
-  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="100.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_locked" value="true" />
- </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="16.0" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="0" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="100000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="8" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="128000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
- <module
-   name="sys_timer_1"
-   kind="altera_avalon_timer"
-   version="16.0"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_timer_2"
-   kind="altera_avalon_timer"
-   version="16.0"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_tlb_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="16.0"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">system_bd_sys_tlb_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="dataWidth2" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="enableDiffWidth" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="163840" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sys_uart"
-   kind="altera_avalon_jtag_uart"
-   version="16.0"
-   enabled="1">
-  <parameter name="allowMultipleConnections" value="false" />
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="100000000" />
-  <parameter name="hubInstanceID" value="0" />
-  <parameter name="readBufferDepth" value="64" />
-  <parameter name="readIRQThreshold" value="8" />
-  <parameter name="simInputCharacterStream" value="" />
-  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
-  <parameter name="useRegistersForReadBuffer" value="false" />
-  <parameter name="useRegistersForWriteBuffer" value="false" />
-  <parameter name="useRelativePathForSimFile" value="false" />
-  <parameter name="writeBufferDepth" value="64" />
-  <parameter name="writeIRQThreshold" value="8" />
- </module>
- <module name="util_ad9250_cpack" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_uart.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814f0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet.control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814e8" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="avl_ad9250_xcvr.core_pll_reconfig">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10018000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814a0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181480" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10180800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181440" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181460" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="avl_ad9250_xcvr.ip_reconfig">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10019000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="avl_phy_reconfig.reconfig_mgmt">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.response">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814e0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10140000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_timer_1.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181420" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_timer_2.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181520" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_gpio_bd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814d0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_gpio_in.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_gpio_out.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181500" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_ad9250_xcvr.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_ad9250_core_0.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10050000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_ad9250_core_1.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10060000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_ad9250_dma.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10070000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_spi.spi_control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.instruction_master"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.instruction_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10180800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.instruction_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10140000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="axi_ad9250_dma.m_dest_axi"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_ethernet_dma_tx.mm_read"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_ethernet_dma_rx.mm_write"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.tightly_coupled_data_master_0"
-   end="sys_tlb_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.tightly_coupled_instruction_master_0"
-   end="sys_tlb_mem.s2">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon_streaming"
-   version="16.0"
-   start="sys_ethernet.receive"
-   end="sys_ethernet_dma_rx.st_sink" />
- <connection
-   kind="avalon_streaming"
-   version="16.0"
-   start="sys_ethernet_dma_tx.st_source"
-   end="sys_ethernet.transmit" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_ddr3_cntrl.afi_clk"
-   end="sys_dma_clk.clk_in" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_cpu.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_id.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_timer_1.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_timer_2.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_uart.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_bd.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_in.clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_gpio_out.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_spi.clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_tlb_mem.clk1" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_tlb_mem.clk2" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet_dma_rx.clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet_dma_tx.clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet.control_port_clock_connection" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="ad9250_adcfifo.if_dma_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="axi_ad9250_dma.if_s_axis_aclk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="axi_ad9250_dma.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="avl_phy_reconfig.mgmt_clk_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ddr3_cntrl.pll_ref_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet.receive_clock_connection" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_pll.refclk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9250_xcvr.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9250_core_0.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9250_core_1.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9250_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="avl_ad9250_xcvr.sys_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet.transmit_clock_connection" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="util_ad9250_cpack.if_adc_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="ad9250_adcfifo.if_adc_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="axi_ad9250_core_0.if_rx_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="axi_ad9250_core_1.if_rx_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="rx_core_clk.in_clk" />
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_core_0.adc_ch_0"
-   end="util_ad9250_cpack.adc_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_core_1.adc_ch_0"
-   end="util_ad9250_cpack.adc_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_core_0.adc_ch_1"
-   end="util_ad9250_cpack.adc_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_core_1.adc_ch_1"
-   end="util_ad9250_cpack.adc_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch0_0_to_xcvr"
-   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch1_1_to_xcvr"
-   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch2_2_to_xcvr"
-   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch3_3_to_xcvr"
-   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_xcvr.core_pll_locked"
-   end="avl_ad9250_xcvr.core_pll_locked">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="util_ad9250_cpack.if_adc_data"
-   end="ad9250_adcfifo.if_adc_wdata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="util_ad9250_cpack.if_adc_valid"
-   end="ad9250_adcfifo.if_adc_wr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_adc_wovf"
-   end="axi_ad9250_core_0.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_dma_wdata"
-   end="axi_ad9250_dma.if_s_axis_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_dma_wr"
-   end="axi_ad9250_dma.if_s_axis_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_dma_wready"
-   end="axi_ad9250_dma.if_s_axis_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_dma_xfer_req"
-   end="axi_ad9250_dma.if_s_axis_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_0"
-   end="avl_phy_reconfig.ch0_0_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_1"
-   end="avl_phy_reconfig.ch1_1_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_2"
-   end="avl_phy_reconfig.ch2_2_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_3"
-   end="avl_phy_reconfig.ch3_3_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.ready"
-   end="axi_ad9250_xcvr.ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_rx.csr_irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_tx.csr_irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="axi_ad9250_dma.interrupt_sender">
-  <parameter name="irqNumber" value="11" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_uart.irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_timer_2.irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_timer_1.irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_gpio_in.irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_gpio_bd.irq">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection kind="interrupt" version="16.0" start="sys_cpu.irq" end="sys_spi.irq">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_ddr3_cntrl.afi_reset"
-   end="sys_dma_clk.clk_in_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_cntrl.global_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="util_ad9250_cpack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_dma_clk.clk_reset"
-   end="util_ad9250_cpack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="ad9250_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_dma_clk.clk_reset"
-   end="ad9250_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_dma_clk.clk_reset"
-   end="axi_ad9250_dma.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="avl_phy_reconfig.mgmt_rst_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_pll.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_timer_1.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_timer_2.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_uart.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_bd.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_in.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_out.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_spi.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_int_mem.reset1" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_tlb_mem.reset1" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_tlb_mem.reset2" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet.reset_connection" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet_dma_rx.reset_n" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet_dma_tx.reset_n" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9250_xcvr.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9250_core_0.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9250_core_1.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9250_dma.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_cntrl.soft_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="avl_ad9250_xcvr.sys_resetn" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_cpu.debug_reset_request"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="axi_ad9250_xcvr.if_up_rst"
-   end="avl_ad9250_xcvr.rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
-</system>
diff --git a/projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv b/projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv
deleted file mode 100644
index 181e3cf9c..000000000
--- a/projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv
+++ /dev/null
@@ -1,34 +0,0 @@
-Core: system_bd_sys_ddr3_cntrl_p0 - Instance: i_system_bd|sys_ddr3_cntrl
-Path, Setup Margin, Hold Margin
-"Address Command (Slow 1150mV 100C Model)",0.436,0.635
-"Bus Turnaround Time (Slow 1150mV 100C Model)",5.495,--
-"Core (Slow 1150mV 100C Model)",0.379,0.223
-"Core Recovery/Removal (Slow 1150mV 100C Model)",2.083,0.531
-"DQS vs CK (Slow 1150mV 100C Model)",0.571,0.601
-"Postamble (Slow 1150mV 100C Model)",0.52,0.52
-"Read Capture (Slow 1150mV 100C Model)",0.256,0.245
-"Write (Slow 1150mV 100C Model)",0.358,0.358
-"Address Command (Slow 1150mV -40C Model)",0.522,0.579
-"Bus Turnaround Time (Slow 1150mV -40C Model)",5.599,--
-"Core (Slow 1150mV -40C Model)",0.713,0.163
-"Core Recovery/Removal (Slow 1150mV -40C Model)",2.462,0.454
-"DQS vs CK (Slow 1150mV -40C Model)",0.594,0.645
-"Postamble (Slow 1150mV -40C Model)",0.506,0.506
-"Read Capture (Slow 1150mV -40C Model)",0.29,0.279
-"Write (Slow 1150mV -40C Model)",0.382,0.382
-"Address Command (Fast 1150mV 100C Model)",0.807,0.54
-"Bus Turnaround Time (Fast 1150mV 100C Model)",5.73,--
-"Core (Fast 1150mV 100C Model)",1.331,0.154
-"Core Recovery/Removal (Fast 1150mV 100C Model)",2.959,0.328
-"DQS vs CK (Fast 1150mV 100C Model)",0.641,0.71
-"Postamble (Fast 1150mV 100C Model)",0.685,0.685
-"Read Capture (Fast 1150mV 100C Model)",0.339,0.331
-"Write (Fast 1150mV 100C Model)",0.388,0.388
-"Address Command (Fast 1150mV -40C Model)",0.874,0.483
-"Bus Turnaround Time (Fast 1150mV -40C Model)",5.742,--
-"Core (Fast 1150mV -40C Model)",1.374,0.112
-"Core Recovery/Removal (Fast 1150mV -40C Model)",3.313,0.275
-"DQS vs CK (Fast 1150mV -40C Model)",0.643,0.723
-"Postamble (Fast 1150mV -40C Model)",0.67,0.67
-"Read Capture (Fast 1150mV -40C Model)",0.339,0.331
-"Write (Fast 1150mV -40C Model)",0.385,0.385
diff --git a/projects/fmcjesdadc1/a5gt/system_qsys_script.tcl b/projects/fmcjesdadc1/a5gt/system_qsys_script.tcl
deleted file mode 100644
index 2b3c37731..000000000
--- a/projects/fmcjesdadc1/a5gt/system_qsys_script.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-set mmu_enabled 1
-set ad_hdl_dir /home/icsomort/Git/hdl
-set ad_phdl_dir /home/icsomort/Git/hdl
-source system_qsys.tcl
diff --git a/projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld b/projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld
deleted file mode 100644
index 7657b5621..000000000
--- a/projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld
+++ /dev/null
@@ -1,9 +0,0 @@
-<sld_project_info>
-  <sld_infos>
-    <sld_info hpath="system_bd:i_system_bd" name="i_system_bd">
-      <assignment_values>
-        <assignment_value text="QSYS_NAME system_bd HAS_SOPCINFO 1 GENERATION_ID 1482152395"/>
-      </assignment_values>
-    </sld_info>
-  </sld_infos>
-</sld_project_info>
diff --git a/projects/fmcjesdadc1/a5soc/system_bd.qsys b/projects/fmcjesdadc1/a5soc/system_bd.qsys
deleted file mode 100644
index 56ac104fb..000000000
--- a/projects/fmcjesdadc1/a5soc/system_bd.qsys
+++ /dev/null
@@ -1,1585 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element ad9250_adcfifo
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element avl_ad9250_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element avl_phy_reconfig
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-   }
-   element axi_ad9250_core_0
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-   }
-   element axi_ad9250_core_1
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element axi_ad9250_dma
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element axi_ad9250_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element rx_core_clk
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_dma_clk
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element sys_gpio_bd
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element sys_gpio_in
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element sys_gpio_out
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element sys_hps
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element util_ad9250_cpack
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="5ASTFD5K3F40I3ES" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="rx_core_clk"
-   internal="rx_core_clk.out_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="rx_data_0"
-   internal="avl_ad9250_xcvr.rx_data_0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_1"
-   internal="avl_ad9250_xcvr.rx_data_1"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_2"
-   internal="avl_ad9250_xcvr.rx_data_2"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_3"
-   internal="avl_ad9250_xcvr.rx_data_3"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_data"
-   internal="avl_ad9250_xcvr.ip_data"
-   type="avalon_streaming"
-   dir="start" />
- <interface
-   name="rx_ip_data_0"
-   internal="axi_ad9250_core_0.if_rx_data"
-   type="avalon_streaming"
-   dir="end" />
- <interface
-   name="rx_ip_data_1"
-   internal="axi_ad9250_core_1.if_rx_data"
-   type="avalon_streaming"
-   dir="end" />
- <interface
-   name="rx_ip_sof"
-   internal="avl_ad9250_xcvr.ip_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_sof_0"
-   internal="axi_ad9250_core_0.if_rx_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_sof_1"
-   internal="axi_ad9250_core_1.if_rx_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ref_clk"
-   internal="avl_ad9250_xcvr.ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="rx_sync"
-   internal="avl_ad9250_xcvr.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sysref"
-   internal="avl_ad9250_xcvr.sysref"
-   type="conduit"
-   dir="end" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_dma_clk"
-   internal="sys_dma_clk.clk_in"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_dma_rst"
-   internal="sys_dma_clk.clk_in_reset"
-   type="reset"
-   dir="end" />
- <interface
-   name="sys_gpio_bd"
-   internal="sys_gpio_bd.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_in"
-   internal="sys_gpio_in.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_out"
-   internal="sys_gpio_out.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_cpu_clk"
-   internal="sys_hps.h2f_user0_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_hps_ddr3"
-   internal="sys_hps.memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_dma_clk"
-   internal="sys_hps.h2f_user1_clock"
-   type="clock"
-   dir="start" />
- <interface name="sys_hps_i2c0" internal="sys_hps.i2c0" type="conduit" dir="end" />
- <interface
-   name="sys_hps_i2c0_clk"
-   internal="sys_hps.i2c0_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_hps_i2c0_scl"
-   internal="sys_hps.i2c0_scl_in"
-   type="clock"
-   dir="end" />
- <interface name="sys_hps_io" internal="sys_hps.hps_io" type="conduit" dir="end" />
- <interface
-   name="sys_hps_rstn"
-   internal="sys_hps.h2f_reset"
-   type="reset"
-   dir="start" />
- <interface
-   name="sys_hps_spim0"
-   internal="sys_hps.spim0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_spim0_sclk"
-   internal="sys_hps.spim0_sclk_out"
-   type="clock"
-   dir="start" />
- <interface name="sys_rst" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
- <module name="ad9250_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
-  <parameter name="ADC_DATA_WIDTH" value="128" />
-  <parameter name="DMA_ADDRESS_WIDTH" value="16" />
-  <parameter name="DMA_DATA_WIDTH" value="128" />
-  <parameter name="DMA_READY_ENABLE" value="1" />
- </module>
- <module name="avl_ad9250_xcvr" kind="avl_adxcvr" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="CORECLK_FREQUENCY" value="125.0" />
-  <parameter name="DEVICE_FAMILY" value="Arria V" />
-  <parameter name="FRM_BCNT" value="4" />
-  <parameter name="FRM_SCNT" value="1" />
-  <parameter name="HD" value="0" />
-  <parameter name="ID" value="1" />
-  <parameter name="LANE_RATE" value="5000.0" />
-  <parameter name="MF_FCNT" value="32" />
-  <parameter name="NUM_OF_CONVS" value="4" />
-  <parameter name="NUM_OF_LANES" value="4" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PLLCLK_FREQUENCY" value="2500.0" />
-  <parameter name="REFCLK_FREQUENCY" value="250.0" />
-  <parameter name="SYSCLK_FREQUENCY" value="50.0" />
-  <parameter name="TX_OR_RX_N" value="0" />
- </module>
- <module
-   name="avl_phy_reconfig"
-   kind="alt_xcvr_reconfig"
-   version="16.0"
-   enabled="1">
-  <parameter name="ber_en" value="0" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="enable_adce" value="0" />
-  <parameter name="enable_analog" value="1" />
-  <parameter name="enable_dcd" value="0" />
-  <parameter name="enable_dcd_power_up" value="1" />
-  <parameter name="enable_dfe" value="0" />
-  <parameter name="enable_eyemon" value="0" />
-  <parameter name="enable_mif" value="0" />
-  <parameter name="enable_offset" value="1" />
-  <parameter name="gui_cal_status_port" value="false" />
-  <parameter name="gui_enable_pll" value="0" />
-  <parameter name="gui_split_sizes" value="1,1,1,1" />
-  <parameter name="number_of_reconfig_interfaces" value="4" />
- </module>
- <module name="axi_ad9250_core_0" kind="axi_ad9250" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="1" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_ad9250_core_1" kind="axi_ad9250" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="1" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_ad9250_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="128" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="128" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="1" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_ad9250_xcvr" kind="axi_adxcvr" version="1.0" enabled="1">
-  <parameter name="ID" value="1" />
-  <parameter name="NUM_OF_LANES" value="4" />
-  <parameter name="TX_OR_RX_N" value="0" />
- </module>
- <module
-   name="rx_core_clk"
-   kind="altera_clock_bridge"
-   version="16.0"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="125" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_clk" kind="clock_source" version="16.0" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="DEASSERT" />
- </module>
- <module name="sys_dma_clk" kind="clock_source" version="16.0" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="DEASSERT" />
- </module>
- <module
-   name="sys_gpio_bd"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_in"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_out"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module name="sys_hps" kind="altera_hps" version="16.0" enabled="1">
-  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-  <parameter name="AC_PACKAGE_DESKEW" value="false" />
-  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-  <parameter name="ADDR_ORDER" value="0" />
-  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
-  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-  <parameter name="ADVANCED_CK_PHASES" value="false" />
-  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
-  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-  <parameter name="AP_MODE" value="false" />
-  <parameter name="AP_MODE_EN" value="0" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_PD_CYCLES" value="0" />
-  <parameter name="AUTO_POWERDN_EN" value="false" />
-  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-  <parameter name="AVL_MAX_SIZE" value="4" />
-  <parameter name="BONDING_OUT_ENABLED" value="false" />
-  <parameter name="BOOTFROMFPGA_Enable" value="false" />
-  <parameter name="BSEL" value="1" />
-  <parameter name="BSEL_EN" value="false" />
-  <parameter name="BYTE_ENABLE" value="true" />
-  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="CALIBRATION_MODE" value="Skip" />
-  <parameter name="CALIB_REG_WIDTH" value="8" />
-  <parameter name="CAN0_Mode" value="N/A" />
-  <parameter name="CAN0_PinMuxing" value="Unused" />
-  <parameter name="CAN1_Mode" value="N/A" />
-  <parameter name="CAN1_PinMuxing" value="Unused" />
-  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-  <parameter name="CFG_REORDER_DATA" value="true" />
-  <parameter name="CFG_TCCD_NS" value="2.5" />
-  <parameter name="COMMAND_PHASE" value="0.0" />
-  <parameter name="CONTROLLER_LATENCY" value="5" />
-  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
-  <parameter name="CSEL" value="0" />
-  <parameter name="CSEL_EN" value="false" />
-  <parameter name="CTI_Enable" value="false" />
-  <parameter name="CTL_AUTOPCH_EN" value="false" />
-  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
-  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="CTL_CSR_ENABLED" value="false" />
-  <parameter name="CTL_CSR_READ_ONLY" value="1" />
-  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
-  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-  <parameter name="CTL_ECC_ENABLED" value="false" />
-  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
-  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
-  <parameter name="CTL_HRB_ENABLED" value="false" />
-  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTL_USR_REFRESH_EN" value="false" />
-  <parameter name="CTL_ZQCAL_EN" value="false" />
-  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
-  <parameter name="DAT_DATA_WIDTH" value="32" />
-  <parameter name="DEBUGAPB_Enable" value="false" />
-  <parameter name="DEBUG_MODE" value="false" />
-  <parameter name="DEVICE_DEPTH" value="1" />
-  <parameter name="DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
-  <parameter name="DISCRETE_FLY_BY" value="true" />
-  <parameter name="DLL_SHARING_MODE" value="None" />
-  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
-  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
-  <parameter name="DUPLICATE_AC" value="false" />
-  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
-  <parameter name="EMAC0_Mode" value="N/A" />
-  <parameter name="EMAC0_PTP" value="false" />
-  <parameter name="EMAC0_PinMuxing" value="Unused" />
-  <parameter name="EMAC1_Mode" value="RGMII" />
-  <parameter name="EMAC1_PTP" value="false" />
-  <parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-  <parameter name="ENABLE_BONDING" value="false" />
-  <parameter name="ENABLE_BURST_MERGE" value="false" />
-  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
-  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
-  <parameter name="ENABLE_ISS_PROBES" value="false" />
-  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
-  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-  <parameter name="ENABLE_USER_ECC" value="false" />
-  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
-  <parameter name="EXTRA_SETTINGS" value="" />
-  <parameter name="F2H_AXI_CLOCK_FREQ" value="100000000" />
-  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
-  <parameter name="F2SCLK_COLDRST_Enable" value="false" />
-  <parameter name="F2SCLK_DBGRST_Enable" value="false" />
-  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
-  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
-  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
-  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
-  <parameter name="F2SCLK_WARMRST_Enable" value="false" />
-  <parameter name="F2SDRAM_Type" value="" />
-  <parameter name="F2SDRAM_Width" value="" />
-  <parameter name="F2SINTERRUPT_Enable" value="true" />
-  <parameter name="F2S_Width" value="2" />
-  <parameter name="FIX_READ_LATENCY" value="8" />
-  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
-  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
-  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
-  <parameter
-     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
-     value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="0" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="125" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="2.5" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="125" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="2.5" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
-  <parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
-  <parameter name="GP_Enable" value="false" />
-  <parameter name="H2F_AXI_CLOCK_FREQ" value="100000000" />
-  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="100000000" />
-  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
-  <parameter name="HARD_EMIF" value="true" />
-  <parameter name="HCX_COMPAT_MODE" value="false" />
-  <parameter name="HHP_HPS" value="true" />
-  <parameter name="HHP_HPS_SIMULATION" value="false" />
-  <parameter name="HHP_HPS_VERIFICATION" value="false" />
-  <parameter name="HLGPI_Enable" value="false" />
-  <parameter name="HPS_PROTOCOL" value="DDR3" />
-  <parameter name="I2C0_Mode" value="Full" />
-  <parameter name="I2C0_PinMuxing" value="FPGA" />
-  <parameter name="I2C1_Mode" value="N/A" />
-  <parameter name="I2C1_PinMuxing" value="Unused" />
-  <parameter name="I2C2_Mode" value="N/A" />
-  <parameter name="I2C2_PinMuxing" value="Unused" />
-  <parameter name="I2C3_Mode" value="N/A" />
-  <parameter name="I2C3_PinMuxing" value="Unused" />
-  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="IS_ES_DEVICE" value="false" />
-  <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
-  <parameter name="LOCAL_ID_WIDTH" value="8" />
-  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
-  <parameter name="LWH2F_Enable" value="true" />
-  <parameter name="MARGIN_VARIATION_TEST" value="false" />
-  <parameter name="MAX_PENDING_RD_CMD" value="32" />
-  <parameter name="MAX_PENDING_WR_CMD" value="16" />
-  <parameter name="MEM_ASR" value="Manual" />
-  <parameter name="MEM_ATCL" value="Disabled" />
-  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
-  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
-  <parameter name="MEM_BL" value="OTF" />
-  <parameter name="MEM_BT" value="Sequential" />
-  <parameter name="MEM_CK_PHASE" value="0.0" />
-  <parameter name="MEM_CK_WIDTH" value="1" />
-  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
-  <parameter name="MEM_CLK_FREQ" value="400.0" />
-  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
-  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_CS_WIDTH" value="1" />
-  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
-  <parameter name="MEM_DLL_EN" value="true" />
-  <parameter name="MEM_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DQ_WIDTH" value="40" />
-  <parameter name="MEM_DRV_STR" value="RZQ/6" />
-  <parameter name="MEM_FORMAT" value="DISCRETE" />
-  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
-  <parameter name="MEM_IF_DQSN_EN" value="true" />
-  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-  <parameter name="MEM_INIT_EN" value="false" />
-  <parameter name="MEM_INIT_FILE" value="" />
-  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
-  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_PD" value="DLL off" />
-  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
-  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
-  <parameter name="MEM_SRT" value="Normal" />
-  <parameter name="MEM_TCL" value="7" />
-  <parameter name="MEM_TFAW_NS" value="35.0" />
-  <parameter name="MEM_TINIT_US" value="500" />
-  <parameter name="MEM_TMRD_CK" value="4" />
-  <parameter name="MEM_TRAS_NS" value="35.0" />
-  <parameter name="MEM_TRCD_NS" value="13.75" />
-  <parameter name="MEM_TREFI_US" value="7.8" />
-  <parameter name="MEM_TRFC_NS" value="260.0" />
-  <parameter name="MEM_TRP_NS" value="13.75" />
-  <parameter name="MEM_TRRD_NS" value="6.0" />
-  <parameter name="MEM_TRTP_NS" value="7.5" />
-  <parameter name="MEM_TWR_NS" value="15.0" />
-  <parameter name="MEM_TWTR" value="4" />
-  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
-  <parameter name="MEM_VENDOR" value="JEDEC" />
-  <parameter name="MEM_VERBOSE" value="true" />
-  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
-  <parameter name="MEM_WTCL" value="6" />
-  <parameter name="MPU_EVENTS_Enable" value="false" />
-  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-  <parameter name="MULTICAST_EN" value="false" />
-  <parameter name="NAND_Mode" value="N/A" />
-  <parameter name="NAND_PinMuxing" value="Unused" />
-  <parameter name="NEXTGEN" value="true" />
-  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
-  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
-  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_OF_PORTS" value="1" />
-  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
-  <parameter name="OCT_SHARING_MODE" value="None" />
-  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="PACKAGE_DESKEW" value="false" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="PHY_CSR_ENABLED" value="false" />
-  <parameter name="PHY_ONLY" value="false" />
-  <parameter name="PINGPONGPHY_EN" value="false" />
-  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
-  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_LOCATION" value="Top_Bottom" />
-  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_SHARING_MODE" value="None" />
-  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="POWER_OF_TWO_BUS" value="false" />
-  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-  <parameter name="QSPI_Mode" value="1 SS" />
-  <parameter name="QSPI_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="RATE" value="Full" />
-  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-  <parameter name="READ_FIFO_SIZE" value="8" />
-  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
-  <parameter name="REFRESH_INTERVAL" value="15000" />
-  <parameter name="REF_CLK_FREQ" value="25.0" />
-  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
-  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
-  <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
-  <parameter name="S2FCLK_USER1CLK_Enable" value="true" />
-  <parameter name="S2FCLK_USER1CLK_FREQ" value="100.0" />
-  <parameter name="S2FCLK_USER2CLK" value="5" />
-  <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
-  <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
-  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
-  <parameter name="S2F_Width" value="2" />
-  <parameter name="SDIO_Mode" value="4-bit Data" />
-  <parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="SEQUENCER_TYPE" value="NIOS" />
-  <parameter name="SEQ_MODE" value="0" />
-  <parameter name="SKIP_MEM_INIT" value="true" />
-  <parameter name="SOPC_COMPAT_RESET" value="false" />
-  <parameter name="SPEED_GRADE" value="7" />
-  <parameter name="SPIM0_Mode" value="Full" />
-  <parameter name="SPIM0_PinMuxing" value="FPGA" />
-  <parameter name="SPIM1_Mode" value="N/A" />
-  <parameter name="SPIM1_PinMuxing" value="Unused" />
-  <parameter name="SPIS0_Mode" value="N/A" />
-  <parameter name="SPIS0_PinMuxing" value="Unused" />
-  <parameter name="SPIS1_Mode" value="N/A" />
-  <parameter name="SPIS1_PinMuxing" value="Unused" />
-  <parameter name="STARVE_LIMIT" value="10" />
-  <parameter name="STM_Enable" value="false" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="TEST_Enable" value="false" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
-  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_TDH" value="0.0" />
-  <parameter name="TIMING_BOARD_TDS" value="0.0" />
-  <parameter name="TIMING_BOARD_TIH" value="0.0" />
-  <parameter name="TIMING_BOARD_TIS" value="0.0" />
-  <parameter name="TIMING_TDH" value="45" />
-  <parameter name="TIMING_TDQSCK" value="225" />
-  <parameter name="TIMING_TDQSCKDL" value="1200" />
-  <parameter name="TIMING_TDQSCKDM" value="900" />
-  <parameter name="TIMING_TDQSCKDS" value="450" />
-  <parameter name="TIMING_TDQSH" value="0.35" />
-  <parameter name="TIMING_TDQSQ" value="100" />
-  <parameter name="TIMING_TDQSS" value="0.27" />
-  <parameter name="TIMING_TDS" value="10" />
-  <parameter name="TIMING_TDSH" value="0.18" />
-  <parameter name="TIMING_TDSS" value="0.18" />
-  <parameter name="TIMING_TIH" value="120" />
-  <parameter name="TIMING_TIS" value="170" />
-  <parameter name="TIMING_TQH" value="0.38" />
-  <parameter name="TIMING_TQHS" value="300" />
-  <parameter name="TIMING_TQSH" value="0.4" />
-  <parameter name="TPIUFPGA_Enable" value="false" />
-  <parameter name="TPIUFPGA_alt" value="false" />
-  <parameter name="TRACE_Mode" value="N/A" />
-  <parameter name="TRACE_PinMuxing" value="Unused" />
-  <parameter name="TRACKING_ERROR_TEST" value="false" />
-  <parameter name="TRACKING_WATCH_TEST" value="false" />
-  <parameter name="TREFI" value="35100" />
-  <parameter name="TRFC" value="350" />
-  <parameter name="UART0_Mode" value="No Flow Control" />
-  <parameter name="UART0_PinMuxing" value="HPS I/O Set 1" />
-  <parameter name="UART1_Mode" value="N/A" />
-  <parameter name="UART1_PinMuxing" value="Unused" />
-  <parameter name="USB0_Mode" value="N/A" />
-  <parameter name="USB0_PinMuxing" value="Unused" />
-  <parameter name="USB1_Mode" value="SDR" />
-  <parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="USER_DEBUG_LEVEL" value="1" />
-  <parameter name="USE_AXI_ADAPTOR" value="false" />
-  <parameter name="USE_FAKE_PHY" value="false" />
-  <parameter name="USE_MEM_CLK_FREQ" value="false" />
-  <parameter name="USE_MM_ADAPTOR" value="true" />
-  <parameter name="USE_SEQUENCER_BFM" value="false" />
-  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
-  <parameter name="can0_clk_div" value="1" />
-  <parameter name="can1_clk_div" value="1" />
-  <parameter name="configure_advanced_parameters" value="false" />
-  <parameter name="customize_device_pll_info" value="false" />
-  <parameter name="dbctrl_stayosc1" value="true" />
-  <parameter name="dbg_at_clk_div" value="0" />
-  <parameter name="dbg_clk_div" value="1" />
-  <parameter name="dbg_trace_clk_div" value="0" />
-  <parameter name="desired_can0_clk_mhz" value="100.0" />
-  <parameter name="desired_can1_clk_mhz" value="100.0" />
-  <parameter name="desired_cfg_clk_mhz" value="50.0" />
-  <parameter name="desired_emac0_clk_mhz" value="250.0" />
-  <parameter name="desired_emac1_clk_mhz" value="250.0" />
-  <parameter name="desired_gpio_db_clk_hz" value="32000" />
-  <parameter name="desired_l4_mp_clk_mhz" value="100.0" />
-  <parameter name="desired_l4_sp_clk_mhz" value="100.0" />
-  <parameter name="desired_mpu_clk_mhz" value="800.0" />
-  <parameter name="desired_nand_clk_mhz" value="12.5" />
-  <parameter name="desired_qspi_clk_mhz" value="400.0" />
-  <parameter name="desired_sdmmc_clk_mhz" value="200.0" />
-  <parameter name="desired_spi_m_clk_mhz" value="200.0" />
-  <parameter name="desired_usb_mp_clk_mhz" value="200.0" />
-  <parameter name="device_name" value="5ASTFD5K3F40I3ES" />
-  <parameter name="device_pll_info_manual">{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}</parameter>
-  <parameter name="eosc1_clk_mhz" value="25.0" />
-  <parameter name="eosc2_clk_mhz" value="25.0" />
-  <parameter name="gpio_db_clk_div" value="6249" />
-  <parameter name="l3_mp_clk_div" value="1" />
-  <parameter name="l3_sp_clk_div" value="1" />
-  <parameter name="l4_mp_clk_div" value="1" />
-  <parameter name="l4_mp_clk_source" value="1" />
-  <parameter name="l4_sp_clk_div" value="1" />
-  <parameter name="l4_sp_clk_source" value="1" />
-  <parameter name="main_pll_c3" value="3" />
-  <parameter name="main_pll_c4" value="3" />
-  <parameter name="main_pll_c5" value="15" />
-  <parameter name="main_pll_m" value="63" />
-  <parameter name="main_pll_n" value="0" />
-  <parameter name="nand_clk_source" value="2" />
-  <parameter name="periph_pll_c0" value="3" />
-  <parameter name="periph_pll_c1" value="3" />
-  <parameter name="periph_pll_c2" value="1" />
-  <parameter name="periph_pll_c3" value="19" />
-  <parameter name="periph_pll_c4" value="4" />
-  <parameter name="periph_pll_c5" value="9" />
-  <parameter name="periph_pll_m" value="79" />
-  <parameter name="periph_pll_n" value="1" />
-  <parameter name="periph_pll_source" value="0" />
-  <parameter name="qspi_clk_source" value="1" />
-  <parameter name="quartus_ini_hps_emif_pll" value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
-     value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
-     value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
-     value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
-  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
-  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
-  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
-  <parameter name="sdmmc_clk_source" value="2" />
-  <parameter name="show_advanced_parameters" value="false" />
-  <parameter name="show_debug_info_as_warning_msg" value="false" />
-  <parameter name="show_warning_as_error_msg" value="false" />
-  <parameter name="spi_m_clk_div" value="0" />
-  <parameter name="usb_mp_clk_div" value="0" />
-  <parameter name="use_default_mpu_clk" value="false" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="16.0"
-   enabled="1">
-  <parameter name="id" value="182193580" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="16.0"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">system_bd_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="64" />
-  <parameter name="dataWidth2" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="enableDiffWidth" value="false" />
-  <parameter name="initMemContent" value="false" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="65536" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module name="util_ad9250_cpack" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="32" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_axi_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x001814e8" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="avl_ad9250_xcvr.core_pll_reconfig">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00018000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="avl_ad9250_xcvr.ip_reconfig">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00019000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="avl_phy_reconfig.reconfig_mgmt">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_gpio_bd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x001814d0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_gpio_in.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x001814c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_gpio_out.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00181500" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="axi_ad9250_xcvr.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="axi_ad9250_core_0.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00050000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="axi_ad9250_core_1.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00060000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_hps.h2f_lw_axi_master"
-   end="axi_ad9250_dma.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00070000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="axi_ad9250_dma.m_dest_axi"
-   end="sys_hps.f2h_axi_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_id.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_bd.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_in.clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_gpio_out.clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="sys_hps.f2h_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_hps.h2f_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_hps.h2f_lw_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="ad9250_adcfifo.if_dma_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="axi_ad9250_dma.if_s_axis_aclk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="axi_ad9250_dma.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="avl_phy_reconfig.mgmt_clk_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9250_xcvr.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9250_core_0.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9250_core_1.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9250_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="avl_ad9250_xcvr.sys_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="util_ad9250_cpack.if_adc_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="ad9250_adcfifo.if_adc_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="axi_ad9250_core_0.if_rx_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="axi_ad9250_core_1.if_rx_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_ad9250_xcvr.core_clk"
-   end="rx_core_clk.in_clk" />
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_core_0.adc_ch_0"
-   end="util_ad9250_cpack.adc_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_core_1.adc_ch_0"
-   end="util_ad9250_cpack.adc_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_core_0.adc_ch_1"
-   end="util_ad9250_cpack.adc_ch_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_core_1.adc_ch_1"
-   end="util_ad9250_cpack.adc_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch0_0_to_xcvr"
-   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch1_1_to_xcvr"
-   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch2_2_to_xcvr"
-   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch3_3_to_xcvr"
-   end="avl_ad9250_xcvr.phy_reconfig_to_xcvr_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_ad9250_xcvr.core_pll_locked"
-   end="avl_ad9250_xcvr.core_pll_locked">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="util_ad9250_cpack.if_adc_data"
-   end="ad9250_adcfifo.if_adc_wdata">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="util_ad9250_cpack.if_adc_valid"
-   end="ad9250_adcfifo.if_adc_wr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_adc_wovf"
-   end="axi_ad9250_core_0.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_dma_wdata"
-   end="axi_ad9250_dma.if_s_axis_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_dma_wr"
-   end="axi_ad9250_dma.if_s_axis_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_dma_wready"
-   end="axi_ad9250_dma.if_s_axis_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="ad9250_adcfifo.if_dma_xfer_req"
-   end="axi_ad9250_dma.if_s_axis_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_0"
-   end="avl_phy_reconfig.ch0_0_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_1"
-   end="avl_phy_reconfig.ch1_1_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_2"
-   end="avl_phy_reconfig.ch2_2_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.phy_reconfig_from_xcvr_3"
-   end="avl_phy_reconfig.ch3_3_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_ad9250_xcvr.ready"
-   end="axi_ad9250_xcvr.ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_hps.f2h_irq0"
-   end="axi_ad9250_dma.interrupt_sender">
-  <parameter name="irqNumber" value="11" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_gpio_in.irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_hps.f2h_irq0"
-   end="sys_gpio_bd.irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="util_ad9250_cpack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_dma_clk.clk_reset"
-   end="util_ad9250_cpack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="ad9250_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_dma_clk.clk_reset"
-   end="ad9250_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_dma_clk.clk_reset"
-   end="axi_ad9250_dma.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="avl_phy_reconfig.mgmt_rst_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_bd.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_in.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_out.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_int_mem.reset1" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9250_xcvr.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9250_core_0.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9250_core_1.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9250_dma.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="avl_ad9250_xcvr.sys_resetn" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="axi_ad9250_xcvr.if_up_rst"
-   end="avl_ad9250_xcvr.rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
-</system>
diff --git a/projects/fmcjesdadc1/a5soc/system_qsys_script.tcl b/projects/fmcjesdadc1/a5soc/system_qsys_script.tcl
deleted file mode 100644
index 2b3c37731..000000000
--- a/projects/fmcjesdadc1/a5soc/system_qsys_script.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-set mmu_enabled 1
-set ad_hdl_dir /home/icsomort/Git/hdl
-set ad_phdl_dir /home/icsomort/Git/hdl
-source system_qsys.tcl
diff --git a/projects/usdrx1/a5gt/serv_req_info.txt b/projects/usdrx1/a5gt/serv_req_info.txt
deleted file mode 100644
index 93337fb66..000000000
--- a/projects/usdrx1/a5gt/serv_req_info.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-<internal_error>
-	<executable>quartus_sta</executable>
-	<sub_system>MEM</sub_system>
-	<error>*** Fatal Error: Out of memory in module quartus_sta (4441 megabytes used)</error>
-	<date>Mon Dec 19 13:19:17 2016</date>
-	<version>Version 16.0.2 Build 222 07/20/2016 SJ Standard Edition</version>
-</internal_error>
-
diff --git a/projects/usdrx1/a5gt/system_bd.qsys b/projects/usdrx1/a5gt/system_bd.qsys
deleted file mode 100644
index 3c73f2741..000000000
--- a/projects/usdrx1/a5gt/system_bd.qsys
+++ /dev/null
@@ -1,2599 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element avl_phy_reconfig
-   {
-      datum _sortIndex
-      {
-         value = "27";
-         type = "int";
-      }
-   }
-   element avl_usdrx1_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "18";
-         type = "int";
-      }
-   }
-   element axi_ad9671_core_0
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-   }
-   element axi_ad9671_core_1
-   {
-      datum _sortIndex
-      {
-         value = "21";
-         type = "int";
-      }
-   }
-   element axi_ad9671_core_2
-   {
-      datum _sortIndex
-      {
-         value = "22";
-         type = "int";
-      }
-   }
-   element axi_ad9671_core_3
-   {
-      datum _sortIndex
-      {
-         value = "23";
-         type = "int";
-      }
-   }
-   element axi_usdrx1_dma
-   {
-      datum _sortIndex
-      {
-         value = "25";
-         type = "int";
-      }
-   }
-   element axi_usdrx1_xcvr
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-   }
-   element rx_core_clk
-   {
-      datum _sortIndex
-      {
-         value = "26";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_cpu
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element sys_ddr3_cntrl
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-   element sys_dma_clk
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element sys_ethernet
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element sys_ethernet_dma_rx
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element sys_ethernet_dma_tx
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element sys_gpio_bd
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element sys_gpio_in
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-   }
-   element sys_gpio_out
-   {
-      datum _sortIndex
-      {
-         value = "16";
-         type = "int";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element sys_pll
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element sys_spi
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-   }
-   element sys_timer_1
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element sys_timer_2
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element sys_tlb_mem
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element sys_uart
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element usdrx1_adcfifo
-   {
-      datum _sortIndex
-      {
-         value = "24";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="5AGTFD7K3F40I3" />
- <parameter name="deviceFamily" value="Arria V" />
- <parameter name="deviceSpeedGrade" value="3_H3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="rx_ch_wdata"
-   internal="usdrx1_adcfifo.if_adc_wdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ch_wovf"
-   internal="usdrx1_adcfifo.if_adc_wovf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ch_wr"
-   internal="usdrx1_adcfifo.if_adc_wr"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_ch_0"
-   internal="axi_ad9671_core_0.adc_ch"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_ch_1"
-   internal="axi_ad9671_core_1.adc_ch"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_ch_2"
-   internal="axi_ad9671_core_2.adc_ch"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_ch_3"
-   internal="axi_ad9671_core_3.adc_ch"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_clk"
-   internal="rx_core_clk.out_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="rx_core_ovf_0"
-   internal="axi_ad9671_core_0.if_adc_dovf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_ovf_1"
-   internal="axi_ad9671_core_1.if_adc_dovf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_ovf_2"
-   internal="axi_ad9671_core_2.if_adc_dovf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_ovf_3"
-   internal="axi_ad9671_core_3.if_adc_dovf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_sync_0"
-   internal="axi_ad9671_core_0.if_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_sync_1"
-   internal="axi_ad9671_core_1.if_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_sync_2"
-   internal="axi_ad9671_core_2.if_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_sync_3"
-   internal="axi_ad9671_core_3.if_sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_unf_0"
-   internal="axi_ad9671_core_0.if_adc_dunf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_unf_1"
-   internal="axi_ad9671_core_1.if_adc_dunf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_unf_2"
-   internal="axi_ad9671_core_2.if_adc_dunf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_core_unf_3"
-   internal="axi_ad9671_core_3.if_adc_dunf"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_0"
-   internal="avl_usdrx1_xcvr.rx_data_0"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_1"
-   internal="avl_usdrx1_xcvr.rx_data_1"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_2"
-   internal="avl_usdrx1_xcvr.rx_data_2"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_3"
-   internal="avl_usdrx1_xcvr.rx_data_3"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_4"
-   internal="avl_usdrx1_xcvr.rx_data_4"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_5"
-   internal="avl_usdrx1_xcvr.rx_data_5"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_6"
-   internal="avl_usdrx1_xcvr.rx_data_6"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_data_7"
-   internal="avl_usdrx1_xcvr.rx_data_7"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_data"
-   internal="avl_usdrx1_xcvr.ip_data"
-   type="avalon_streaming"
-   dir="start" />
- <interface
-   name="rx_ip_data_0"
-   internal="axi_ad9671_core_0.if_rx_data"
-   type="avalon_streaming"
-   dir="end" />
- <interface
-   name="rx_ip_data_1"
-   internal="axi_ad9671_core_1.if_rx_data"
-   type="avalon_streaming"
-   dir="end" />
- <interface
-   name="rx_ip_data_2"
-   internal="axi_ad9671_core_2.if_rx_data"
-   type="avalon_streaming"
-   dir="end" />
- <interface
-   name="rx_ip_data_3"
-   internal="axi_ad9671_core_3.if_rx_data"
-   type="avalon_streaming"
-   dir="end" />
- <interface
-   name="rx_ip_sof"
-   internal="avl_usdrx1_xcvr.ip_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_sof_0"
-   internal="axi_ad9671_core_0.if_rx_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_sof_1"
-   internal="axi_ad9671_core_1.if_rx_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_sof_2"
-   internal="axi_ad9671_core_2.if_rx_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ip_sof_3"
-   internal="axi_ad9671_core_3.if_rx_sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_ref_clk"
-   internal="avl_usdrx1_xcvr.ref_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="rx_sync"
-   internal="avl_usdrx1_xcvr.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="rx_sysref"
-   internal="avl_usdrx1_xcvr.sysref"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_125m_clk"
-   internal="sys_pll.outclk0"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_25m_clk"
-   internal="sys_pll.outclk1"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_2m5_clk"
-   internal="sys_pll.outclk2"
-   type="clock"
-   dir="start" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_ddr3_cntrl_mem"
-   internal="sys_ddr3_cntrl.memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ddr3_cntrl_oct"
-   internal="sys_ddr3_cntrl.oct"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_mdio"
-   internal="sys_ethernet.mac_mdio_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_rgmii"
-   internal="sys_ethernet.mac_rgmii_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_rx_clk"
-   internal="sys_ethernet.pcs_mac_rx_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_ethernet_status"
-   internal="sys_ethernet.mac_status_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_ethernet_tx_clk"
-   internal="sys_ethernet.pcs_mac_tx_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_gpio_bd"
-   internal="sys_gpio_bd.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_in"
-   internal="sys_gpio_in.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_gpio_out"
-   internal="sys_gpio_out.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_pll_locked"
-   internal="sys_pll.locked"
-   type="conduit"
-   dir="end" />
- <interface name="sys_rst" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
- <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module
-   name="avl_phy_reconfig"
-   kind="alt_xcvr_reconfig"
-   version="16.0"
-   enabled="1">
-  <parameter name="ber_en" value="0" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="enable_adce" value="0" />
-  <parameter name="enable_analog" value="1" />
-  <parameter name="enable_dcd" value="0" />
-  <parameter name="enable_dcd_power_up" value="1" />
-  <parameter name="enable_dfe" value="0" />
-  <parameter name="enable_eyemon" value="0" />
-  <parameter name="enable_mif" value="0" />
-  <parameter name="enable_offset" value="1" />
-  <parameter name="gui_cal_status_port" value="false" />
-  <parameter name="gui_enable_pll" value="0" />
-  <parameter name="gui_split_sizes" value="1,1,1,1,1,1,1,1" />
-  <parameter name="number_of_reconfig_interfaces" value="8" />
- </module>
- <module name="avl_usdrx1_xcvr" kind="avl_adxcvr" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="CORECLK_FREQUENCY" value="80.0" />
-  <parameter name="DEVICE_FAMILY" value="Arria V" />
-  <parameter name="FRM_BCNT" value="4" />
-  <parameter name="FRM_SCNT" value="1" />
-  <parameter name="HD" value="0" />
-  <parameter name="ID" value="1" />
-  <parameter name="LANE_RATE" value="3200.0" />
-  <parameter name="MF_FCNT" value="32" />
-  <parameter name="NUM_OF_CONVS" value="32" />
-  <parameter name="NUM_OF_LANES" value="8" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
-  <parameter name="PLLCLK_FREQUENCY" value="1600.0" />
-  <parameter name="REFCLK_FREQUENCY" value="80.0" />
-  <parameter name="SYSCLK_FREQUENCY" value="100.0" />
-  <parameter name="TX_OR_RX_N" value="0" />
- </module>
- <module name="axi_ad9671_core_0" kind="axi_ad9671" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="0" />
-  <parameter name="QUAD_OR_DUAL_N" value="0" />
- </module>
- <module name="axi_ad9671_core_1" kind="axi_ad9671" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="1" />
-  <parameter name="QUAD_OR_DUAL_N" value="0" />
- </module>
- <module name="axi_ad9671_core_2" kind="axi_ad9671" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="2" />
-  <parameter name="QUAD_OR_DUAL_N" value="0" />
- </module>
- <module name="axi_ad9671_core_3" kind="axi_ad9671" version="1.0" enabled="1">
-  <parameter name="DEVICE_TYPE" value="0" />
-  <parameter name="ID" value="3" />
-  <parameter name="QUAD_OR_DUAL_N" value="0" />
- </module>
- <module name="axi_usdrx1_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="512" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="512" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="1" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_usdrx1_xcvr" kind="axi_adxcvr" version="1.0" enabled="1">
-  <parameter name="ID" value="1" />
-  <parameter name="NUM_OF_LANES" value="8" />
-  <parameter name="TX_OR_RX_N" value="0" />
- </module>
- <module
-   name="rx_core_clk"
-   kind="altera_clock_bridge"
-   version="16.0"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="80" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_clk" kind="clock_source" version="16.0" enabled="1">
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="DEASSERT" />
- </module>
- <module name="sys_cpu" kind="altera_nios2_gen2" version="16.0" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="bht_ramBlockType" value="Automatic" />
-  <parameter name="breakOffset" value="32" />
-  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
-  <parameter name="cdx_enabled" value="false" />
-  <parameter name="clockFrequency" value="100000000" />
-  <parameter name="cpuArchRev" value="1" />
-  <parameter name="cpuID" value="0" />
-  <parameter name="cpuReset" value="false" />
-  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
-  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
-  <parameter name="dataAddrWidth" value="29" />
-  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='avl_phy_reconfig.reconfig_mgmt' start='0x10010000' end='0x10010200' type='alt_xcvr_reconfig.reconfig_mgmt' /><slave name='avl_usdrx1_xcvr.core_pll_reconfig' start='0x10018000' end='0x10018100' type='avl_adxcvr.core_pll_reconfig' /><slave name='avl_usdrx1_xcvr.ip_reconfig' start='0x10019000' end='0x10019400' type='avl_adxcvr.ip_reconfig' /><slave name='axi_usdrx1_xcvr.s_axi' start='0x10020000' end='0x10030000' type='axi_adxcvr.s_axi' /><slave name='axi_ad9671_core_0.s_axi' start='0x10050000' end='0x10060000' type='axi_ad9671.s_axi' /><slave name='axi_ad9671_core_1.s_axi' start='0x10060000' end='0x10070000' type='axi_ad9671.s_axi' /><slave name='axi_ad9671_core_2.s_axi' start='0x10070000' end='0x10080000' type='axi_ad9671.s_axi' /><slave name='axi_ad9671_core_3.s_axi' start='0x10080000' end='0x10090000' type='axi_ad9671.s_axi' /><slave name='axi_usdrx1_dma.s_axi' start='0x10090000' end='0x10094000' type='axi_dmac.s_axi' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer_1.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
-  <parameter name="data_master_high_performance_paddr_base" value="0" />
-  <parameter name="data_master_high_performance_paddr_size" value="0" />
-  <parameter name="data_master_paddr_base" value="0" />
-  <parameter name="data_master_paddr_size" value="0" />
-  <parameter name="dcache_bursts" value="false" />
-  <parameter name="dcache_numTCDM" value="1" />
-  <parameter name="dcache_ramBlockType" value="Automatic" />
-  <parameter name="dcache_size" value="32768" />
-  <parameter name="dcache_tagramBlockType" value="Automatic" />
-  <parameter name="dcache_victim_buf_impl" value="ram" />
-  <parameter name="debug_OCIOnchipTrace" value="_128" />
-  <parameter name="debug_assignJtagInstanceID" value="false" />
-  <parameter name="debug_datatrigger" value="0" />
-  <parameter name="debug_debugReqSignals" value="false" />
-  <parameter name="debug_enabled" value="true" />
-  <parameter name="debug_hwbreakpoint" value="0" />
-  <parameter name="debug_jtagInstanceID" value="0" />
-  <parameter name="debug_traceStorage" value="onchip_trace" />
-  <parameter name="debug_traceType" value="none" />
-  <parameter name="debug_triggerArming" value="true" />
-  <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dividerType" value="no_div" />
-  <parameter name="exceptionOffset" value="32" />
-  <parameter name="exceptionSlave" value="sys_ddr3_cntrl.avl" />
-  <parameter name="faAddrWidth" value="1" />
-  <parameter name="faSlaveMapParam" value="" />
-  <parameter name="fa_cache_line" value="2" />
-  <parameter name="fa_cache_linesize" value="0" />
-  <parameter name="flash_instruction_master_paddr_base" value="0" />
-  <parameter name="flash_instruction_master_paddr_size" value="0" />
-  <parameter name="icache_burstType" value="None" />
-  <parameter name="icache_numTCIM" value="1" />
-  <parameter name="icache_ramBlockType" value="Automatic" />
-  <parameter name="icache_size" value="32768" />
-  <parameter name="icache_tagramBlockType" value="Automatic" />
-  <parameter name="impl" value="Fast" />
-  <parameter name="instAddrWidth" value="29" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
-  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
-  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
-  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
-  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
-  <parameter name="instruction_master_paddr_base" value="0" />
-  <parameter name="instruction_master_paddr_size" value="0" />
-  <parameter name="internalIrqMaskSystemInfo" value="2303" />
-  <parameter name="io_regionbase" value="0" />
-  <parameter name="io_regionsize" value="0" />
-  <parameter name="master_addr_map" value="false" />
-  <parameter name="mmu_TLBMissExcOffset" value="4096" />
-  <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
-  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="true" />
-  <parameter name="mmu_processIDNumBits" value="8" />
-  <parameter name="mmu_ramBlockType" value="Automatic" />
-  <parameter name="mmu_tlbNumWays" value="16" />
-  <parameter name="mmu_tlbPtrSz" value="7" />
-  <parameter name="mmu_udtlbNumEntries" value="6" />
-  <parameter name="mmu_uitlbNumEntries" value="4" />
-  <parameter name="mpu_enabled" value="false" />
-  <parameter name="mpu_minDataRegionSize" value="12" />
-  <parameter name="mpu_minInstRegionSize" value="12" />
-  <parameter name="mpu_numOfDataRegion" value="8" />
-  <parameter name="mpu_numOfInstRegion" value="8" />
-  <parameter name="mpu_useLimit" value="false" />
-  <parameter name="mpx_enabled" value="false" />
-  <parameter name="mul_32_impl" value="3" />
-  <parameter name="mul_64_impl" value="0" />
-  <parameter name="mul_shift_choice" value="0" />
-  <parameter name="ocimem_ramBlockType" value="Automatic" />
-  <parameter name="ocimem_ramInit" value="false" />
-  <parameter name="regfile_ramBlockType" value="Automatic" />
-  <parameter name="resetOffset" value="0" />
-  <parameter name="resetSlave" value="sys_ddr3_cntrl.avl" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="setting_HBreakTest" value="false" />
-  <parameter name="setting_HDLSimCachesCleared" value="true" />
-  <parameter name="setting_activateMonitors" value="true" />
-  <parameter name="setting_activateTestEndChecker" value="false" />
-  <parameter name="setting_activateTrace" value="true" />
-  <parameter name="setting_allow_break_inst" value="false" />
-  <parameter name="setting_alwaysEncrypt" value="true" />
-  <parameter name="setting_asic_add_scan_mode_input" value="false" />
-  <parameter name="setting_asic_enabled" value="false" />
-  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
-  <parameter name="setting_asic_third_party_synthesis" value="false" />
-  <parameter name="setting_avalonDebugPortPresent" value="false" />
-  <parameter name="setting_bhtPtrSz" value="8" />
-  <parameter name="setting_bigEndian" value="false" />
-  <parameter name="setting_branchpredictiontype" value="Dynamic" />
-  <parameter name="setting_breakslaveoveride" value="false" />
-  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
-  <parameter name="setting_dc_ecc_present" value="false" />
-  <parameter name="setting_disable_tmr_inj" value="false" />
-  <parameter name="setting_disableocitrace" value="false" />
-  <parameter name="setting_dtcm_ecc_present" value="false" />
-  <parameter name="setting_ecc_present" value="false" />
-  <parameter name="setting_ecc_sim_test_ports" value="false" />
-  <parameter name="setting_exportHostDebugPort" value="false" />
-  <parameter name="setting_exportPCB" value="false" />
-  <parameter name="setting_export_large_RAMs" value="false" />
-  <parameter name="setting_exportdebuginfo" value="false" />
-  <parameter name="setting_exportvectors" value="false" />
-  <parameter name="setting_fast_register_read" value="false" />
-  <parameter name="setting_ic_ecc_present" value="true" />
-  <parameter name="setting_interruptControllerType" value="Internal" />
-  <parameter name="setting_itcm_ecc_present" value="false" />
-  <parameter name="setting_mmu_ecc_present" value="true" />
-  <parameter name="setting_oci_export_jtag_signals" value="false" />
-  <parameter name="setting_oci_version" value="1" />
-  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
-  <parameter name="setting_removeRAMinit" value="false" />
-  <parameter name="setting_rf_ecc_present" value="true" />
-  <parameter name="setting_shadowRegisterSets" value="0" />
-  <parameter name="setting_showInternalSettings" value="false" />
-  <parameter name="setting_showUnpublishedSettings" value="false" />
-  <parameter name="setting_support31bitdcachebypass" value="false" />
-  <parameter name="setting_tmr_output_disable" value="false" />
-  <parameter name="setting_usedesignware" value="false" />
-  <parameter name="shift_rot_impl" value="0" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
-  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
-  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
-  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
-  <parameter name="tmr_enabled" value="false" />
-  <parameter name="tracefilename" value="" />
-  <parameter name="userDefinedSettings" value="" />
- </module>
- <module
-   name="sys_ddr3_cntrl"
-   kind="altera_mem_if_ddr3_emif"
-   version="16.0"
-   enabled="1">
-  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-  <parameter name="AC_PACKAGE_DESKEW" value="false" />
-  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-  <parameter name="ADDR_ORDER" value="0" />
-  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
-  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-  <parameter name="ADVANCED_CK_PHASES" value="false" />
-  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
-  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-  <parameter name="AP_MODE" value="false" />
-  <parameter name="AP_MODE_EN" value="0" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_PD_CYCLES" value="0" />
-  <parameter name="AUTO_POWERDN_EN" value="false" />
-  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-  <parameter name="AVL_MAX_SIZE" value="256" />
-  <parameter name="BYTE_ENABLE" value="true" />
-  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="CALIBRATION_MODE" value="Skip" />
-  <parameter name="CALIB_REG_WIDTH" value="8" />
-  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-  <parameter name="CFG_REORDER_DATA" value="true" />
-  <parameter name="CFG_TCCD_NS" value="2.5" />
-  <parameter name="COMMAND_PHASE" value="0.0" />
-  <parameter name="CONTROLLER_LATENCY" value="5" />
-  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
-  <parameter name="CTL_AUTOPCH_EN" value="false" />
-  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
-  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="CTL_CSR_ENABLED" value="false" />
-  <parameter name="CTL_CSR_READ_ONLY" value="1" />
-  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
-  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-  <parameter name="CTL_ECC_ENABLED" value="false" />
-  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
-  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
-  <parameter name="CTL_HRB_ENABLED" value="false" />
-  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTL_USR_REFRESH_EN" value="false" />
-  <parameter name="CTL_ZQCAL_EN" value="false" />
-  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
-  <parameter name="DAT_DATA_WIDTH" value="32" />
-  <parameter name="DEBUG_MODE" value="false" />
-  <parameter name="DEVICE_DEPTH" value="1" />
-  <parameter name="DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
-  <parameter name="DISCRETE_FLY_BY" value="true" />
-  <parameter name="DLL_SHARING_MODE" value="None" />
-  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
-  <parameter name="DUPLICATE_AC" value="false" />
-  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
-  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-  <parameter name="ENABLE_BONDING" value="false" />
-  <parameter name="ENABLE_BURST_MERGE" value="false" />
-  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
-  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
-  <parameter name="ENABLE_ISS_PROBES" value="false" />
-  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
-  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-  <parameter name="ENABLE_USER_ECC" value="false" />
-  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
-  <parameter name="EXTRA_SETTINGS" value="" />
-  <parameter name="FIX_READ_LATENCY" value="8" />
-  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
-  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
-  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-  <parameter name="HARD_EMIF" value="false" />
-  <parameter name="HCX_COMPAT_MODE" value="false" />
-  <parameter name="HHP_HPS" value="false" />
-  <parameter name="HHP_HPS_SIMULATION" value="false" />
-  <parameter name="HHP_HPS_VERIFICATION" value="false" />
-  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
-  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="IS_ES_DEVICE" value="false" />
-  <parameter name="LOCAL_ID_WIDTH" value="8" />
-  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
-  <parameter name="MARGIN_VARIATION_TEST" value="false" />
-  <parameter name="MAX_PENDING_RD_CMD" value="32" />
-  <parameter name="MAX_PENDING_WR_CMD" value="16" />
-  <parameter name="MEM_ASR" value="Manual" />
-  <parameter name="MEM_ATCL" value="Disabled" />
-  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
-  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
-  <parameter name="MEM_BL" value="OTF" />
-  <parameter name="MEM_BT" value="Sequential" />
-  <parameter name="MEM_CK_PHASE" value="0.0" />
-  <parameter name="MEM_CK_WIDTH" value="1" />
-  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
-  <parameter name="MEM_CLK_FREQ" value="400.0" />
-  <parameter name="MEM_CLK_FREQ_MAX" value="666.667" />
-  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_CS_WIDTH" value="1" />
-  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
-  <parameter name="MEM_DLL_EN" value="true" />
-  <parameter name="MEM_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DQ_WIDTH" value="64" />
-  <parameter name="MEM_DRV_STR" value="RZQ/6" />
-  <parameter name="MEM_FORMAT" value="DISCRETE" />
-  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
-  <parameter name="MEM_IF_DQSN_EN" value="true" />
-  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-  <parameter name="MEM_INIT_EN" value="false" />
-  <parameter name="MEM_INIT_FILE" value="" />
-  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
-  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_PD" value="DLL off" />
-  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-  <parameter name="MEM_ROW_ADDR_WIDTH" value="12" />
-  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
-  <parameter name="MEM_RTT_WR" value="RZQ/4" />
-  <parameter name="MEM_SRT" value="Normal" />
-  <parameter name="MEM_TCL" value="11" />
-  <parameter name="MEM_TFAW_NS" value="30.0" />
-  <parameter name="MEM_TINIT_US" value="500" />
-  <parameter name="MEM_TMRD_CK" value="4" />
-  <parameter name="MEM_TRAS_NS" value="35.0" />
-  <parameter name="MEM_TRCD_NS" value="13.75" />
-  <parameter name="MEM_TREFI_US" value="7.8" />
-  <parameter name="MEM_TRFC_NS" value="110.0" />
-  <parameter name="MEM_TRP_NS" value="13.75" />
-  <parameter name="MEM_TRRD_NS" value="6.0" />
-  <parameter name="MEM_TRTP_NS" value="7.5" />
-  <parameter name="MEM_TWR_NS" value="15.0" />
-  <parameter name="MEM_TWTR" value="6" />
-  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
-  <parameter name="MEM_VENDOR" value="Micron" />
-  <parameter name="MEM_VERBOSE" value="true" />
-  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
-  <parameter name="MEM_WTCL" value="8" />
-  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-  <parameter name="MULTICAST_EN" value="false" />
-  <parameter name="NEXTGEN" value="true" />
-  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
-  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
-  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_OF_PORTS" value="1" />
-  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
-  <parameter name="OCT_SHARING_MODE" value="None" />
-  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="PACKAGE_DESKEW" value="false" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="PHY_CSR_ENABLED" value="false" />
-  <parameter name="PHY_ONLY" value="false" />
-  <parameter name="PINGPONGPHY_EN" value="false" />
-  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
-  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_LOCATION" value="Top_Bottom" />
-  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_SHARING_MODE" value="None" />
-  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="POWER_OF_TWO_BUS" value="false" />
-  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-  <parameter name="RATE" value="Quarter" />
-  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-  <parameter name="READ_FIFO_SIZE" value="8" />
-  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
-  <parameter name="REFRESH_INTERVAL" value="15000" />
-  <parameter name="REF_CLK_FREQ" value="100.0" />
-  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-  <parameter name="SEQUENCER_TYPE" value="NIOS" />
-  <parameter name="SEQ_MODE" value="0" />
-  <parameter name="SKIP_MEM_INIT" value="true" />
-  <parameter name="SOPC_COMPAT_RESET" value="false" />
-  <parameter name="SPEED_GRADE" value="3" />
-  <parameter name="STARVE_LIMIT" value="10" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
-  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-  <parameter name="TIMING_BOARD_TDH" value="0.0" />
-  <parameter name="TIMING_BOARD_TDS" value="0.0" />
-  <parameter name="TIMING_BOARD_TIH" value="0.0" />
-  <parameter name="TIMING_BOARD_TIS" value="0.0" />
-  <parameter name="TIMING_TDH" value="45" />
-  <parameter name="TIMING_TDQSCK" value="255" />
-  <parameter name="TIMING_TDQSCKDL" value="1200" />
-  <parameter name="TIMING_TDQSCKDM" value="900" />
-  <parameter name="TIMING_TDQSCKDS" value="450" />
-  <parameter name="TIMING_TDQSQ" value="100" />
-  <parameter name="TIMING_TDQSS" value="0.27" />
-  <parameter name="TIMING_TDS" value="10" />
-  <parameter name="TIMING_TDSH" value="0.18" />
-  <parameter name="TIMING_TDSS" value="0.18" />
-  <parameter name="TIMING_TIH" value="120" />
-  <parameter name="TIMING_TIS" value="170" />
-  <parameter name="TIMING_TQH" value="0.38" />
-  <parameter name="TIMING_TQSH" value="0.4" />
-  <parameter name="TRACKING_ERROR_TEST" value="false" />
-  <parameter name="TRACKING_WATCH_TEST" value="false" />
-  <parameter name="TREFI" value="35100" />
-  <parameter name="TRFC" value="350" />
-  <parameter name="USER_DEBUG_LEVEL" value="1" />
-  <parameter name="USE_AXI_ADAPTOR" value="false" />
-  <parameter name="USE_FAKE_PHY" value="false" />
-  <parameter name="USE_MEM_CLK_FREQ" value="false" />
-  <parameter name="USE_MM_ADAPTOR" value="true" />
-  <parameter name="USE_SEQUENCER_BFM" value="false" />
-  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
- </module>
- <module name="sys_dma_clk" kind="clock_source" version="16.0" enabled="1">
-  <parameter name="clockFrequency" value="50000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="100000000" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <module name="sys_ethernet" kind="altera_eth_tse" version="16.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="core_variation" value="MAC_ONLY" />
-  <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="eg_addr" value="11" />
-  <parameter name="ena_hash" value="false" />
-  <parameter name="enable_alt_reconfig" value="false" />
-  <parameter name="enable_ecc" value="false" />
-  <parameter name="enable_ena" value="32" />
-  <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_hd_logic" value="true" />
-  <parameter name="enable_mac_flow_ctrl" value="true" />
-  <parameter name="enable_mac_vlan" value="false" />
-  <parameter name="enable_magic_detect" value="true" />
-  <parameter name="enable_ptp_1step" value="false" />
-  <parameter name="enable_sgmii" value="false" />
-  <parameter name="enable_shift16" value="true" />
-  <parameter name="enable_sup_addr" value="false" />
-  <parameter name="enable_timestamping" value="false" />
-  <parameter name="enable_use_internal_fifo" value="true" />
-  <parameter name="export_pwrdn" value="false" />
-  <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ifGMII" value="RGMII" />
-  <parameter name="ing_addr" value="11" />
-  <parameter name="max_channels" value="1" />
-  <parameter name="mdio_clk_div" value="30" />
-  <parameter name="nf_phyip_rcfg_enable" value="false" />
-  <parameter name="phy_identifier" value="0" />
-  <parameter name="phyip_en_synce_support" value="false" />
-  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
-  <parameter name="phyip_pll_type" value="CMU" />
-  <parameter name="phyip_pma_bonding_mode" value="x1" />
-  <parameter name="starting_channel_number" value="0" />
-  <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="transceiver_type" value="NONE" />
-  <parameter name="tstamp_fp_width" value="4" />
-  <parameter name="useMDIO" value="true" />
-  <parameter name="use_mac_clken" value="false" />
-  <parameter name="use_misc_ports" value="true" />
- </module>
- <module
-   name="sys_ethernet_dma_rx"
-   kind="altera_msgdma"
-   version="16.0"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="6" />
-  <parameter name="EXPOSE_ST_PORT" value="0" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="2" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="0" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_ethernet_dma_tx"
-   kind="altera_msgdma"
-   version="16.0"
-   enabled="1">
-  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
-  <parameter
-     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
-     value="AddressWidth = -1" />
-  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="BURST_ENABLE" value="1" />
-  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
-  <parameter name="CHANNEL_ENABLE" value="0" />
-  <parameter name="CHANNEL_WIDTH" value="8" />
-  <parameter name="DATA_FIFO_DEPTH" value="256" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
-  <parameter name="ENHANCED_FEATURES" value="1" />
-  <parameter name="ERROR_ENABLE" value="1" />
-  <parameter name="ERROR_WIDTH" value="1" />
-  <parameter name="EXPOSE_ST_PORT" value="0" />
-  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
-  <parameter name="MAX_BURST_COUNT" value="64" />
-  <parameter name="MAX_BYTE" value="2048" />
-  <parameter name="MAX_STRIDE" value="1" />
-  <parameter name="MODE" value="1" />
-  <parameter name="PACKET_ENABLE" value="1" />
-  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
-  <parameter name="PREFETCHER_ENABLE" value="0" />
-  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
-  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
-  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
-  <parameter name="RESPONSE_PORT" value="2" />
-  <parameter name="STRIDE_ENABLE" value="0" />
-  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
-  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
- </module>
- <module
-   name="sys_gpio_bd"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_in"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_gpio_out"
-   kind="altera_avalon_pio"
-   version="16.0"
-   enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="100000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="16.0"
-   enabled="1">
-  <parameter name="id" value="182193580" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="16.0"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">system_bd_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="dataWidth2" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="enableDiffWidth" value="false" />
-  <parameter name="initMemContent" value="false" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="163840" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module name="sys_pll" kind="altera_pll" version="16.0" enabled="1">
-  <parameter name="debug_print_output" value="false" />
-  <parameter name="debug_use_rbc_taf_method" value="false" />
-  <parameter name="device" value="5AGTFD7K3F40I3" />
-  <parameter name="device_family" value="Arria V" />
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
-  <parameter name="gui_actual_phase_shift0" value="0" />
-  <parameter name="gui_actual_phase_shift1" value="0" />
-  <parameter name="gui_actual_phase_shift10" value="0" />
-  <parameter name="gui_actual_phase_shift11" value="0" />
-  <parameter name="gui_actual_phase_shift12" value="0" />
-  <parameter name="gui_actual_phase_shift13" value="0" />
-  <parameter name="gui_actual_phase_shift14" value="0" />
-  <parameter name="gui_actual_phase_shift15" value="0" />
-  <parameter name="gui_actual_phase_shift16" value="0" />
-  <parameter name="gui_actual_phase_shift17" value="0" />
-  <parameter name="gui_actual_phase_shift2" value="0" />
-  <parameter name="gui_actual_phase_shift3" value="0" />
-  <parameter name="gui_actual_phase_shift4" value="0" />
-  <parameter name="gui_actual_phase_shift5" value="0" />
-  <parameter name="gui_actual_phase_shift6" value="0" />
-  <parameter name="gui_actual_phase_shift7" value="0" />
-  <parameter name="gui_actual_phase_shift8" value="0" />
-  <parameter name="gui_actual_phase_shift9" value="0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_channel_spacing" value="0.0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_device_speed_grade" value="1" />
-  <parameter name="gui_divide_factor_c0" value="1" />
-  <parameter name="gui_divide_factor_c1" value="1" />
-  <parameter name="gui_divide_factor_c10" value="1" />
-  <parameter name="gui_divide_factor_c11" value="1" />
-  <parameter name="gui_divide_factor_c12" value="1" />
-  <parameter name="gui_divide_factor_c13" value="1" />
-  <parameter name="gui_divide_factor_c14" value="1" />
-  <parameter name="gui_divide_factor_c15" value="1" />
-  <parameter name="gui_divide_factor_c16" value="1" />
-  <parameter name="gui_divide_factor_c17" value="1" />
-  <parameter name="gui_divide_factor_c2" value="1" />
-  <parameter name="gui_divide_factor_c3" value="1" />
-  <parameter name="gui_divide_factor_c4" value="1" />
-  <parameter name="gui_divide_factor_c5" value="1" />
-  <parameter name="gui_divide_factor_c6" value="1" />
-  <parameter name="gui_divide_factor_c7" value="1" />
-  <parameter name="gui_divide_factor_c8" value="1" />
-  <parameter name="gui_divide_factor_c9" value="1" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50" />
-  <parameter name="gui_duty_cycle1" value="50" />
-  <parameter name="gui_duty_cycle10" value="50" />
-  <parameter name="gui_duty_cycle11" value="50" />
-  <parameter name="gui_duty_cycle12" value="50" />
-  <parameter name="gui_duty_cycle13" value="50" />
-  <parameter name="gui_duty_cycle14" value="50" />
-  <parameter name="gui_duty_cycle15" value="50" />
-  <parameter name="gui_duty_cycle16" value="50" />
-  <parameter name="gui_duty_cycle17" value="50" />
-  <parameter name="gui_duty_cycle2" value="50" />
-  <parameter name="gui_duty_cycle3" value="50" />
-  <parameter name="gui_duty_cycle4" value="50" />
-  <parameter name="gui_duty_cycle5" value="50" />
-  <parameter name="gui_duty_cycle6" value="50" />
-  <parameter name="gui_duty_cycle7" value="50" />
-  <parameter name="gui_duty_cycle8" value="50" />
-  <parameter name="gui_duty_cycle9" value="50" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_number_of_clocks" value="3" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="125.0" />
-  <parameter name="gui_output_clock_frequency1" value="25.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="2.5" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0" />
-  <parameter name="gui_phase_shift1" value="0" />
-  <parameter name="gui_phase_shift10" value="0" />
-  <parameter name="gui_phase_shift11" value="0" />
-  <parameter name="gui_phase_shift12" value="0" />
-  <parameter name="gui_phase_shift13" value="0" />
-  <parameter name="gui_phase_shift14" value="0" />
-  <parameter name="gui_phase_shift15" value="0" />
-  <parameter name="gui_phase_shift16" value="0" />
-  <parameter name="gui_phase_shift17" value="0" />
-  <parameter name="gui_phase_shift2" value="0" />
-  <parameter name="gui_phase_shift3" value="0" />
-  <parameter name="gui_phase_shift4" value="0" />
-  <parameter name="gui_phase_shift5" value="0" />
-  <parameter name="gui_phase_shift6" value="0" />
-  <parameter name="gui_phase_shift7" value="0" />
-  <parameter name="gui_phase_shift8" value="0" />
-  <parameter name="gui_phase_shift9" value="0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="Off" />
-  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
-  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="100.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_locked" value="true" />
- </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="16.0" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="0" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="100000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="8" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="128000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
- <module
-   name="sys_timer_1"
-   kind="altera_avalon_timer"
-   version="16.0"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_timer_2"
-   kind="altera_avalon_timer"
-   version="16.0"
-   enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
-  <parameter name="watchdogPulse" value="2" />
- </module>
- <module
-   name="sys_tlb_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="16.0"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">system_bd_sys_tlb_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="dataWidth2" value="32" />
-  <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="enableDiffWidth" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="163840" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sys_uart"
-   kind="altera_avalon_jtag_uart"
-   version="16.0"
-   enabled="1">
-  <parameter name="allowMultipleConnections" value="false" />
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="100000000" />
-  <parameter name="hubInstanceID" value="0" />
-  <parameter name="readBufferDepth" value="64" />
-  <parameter name="readIRQThreshold" value="8" />
-  <parameter name="simInputCharacterStream" value="" />
-  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
-  <parameter name="useRegistersForReadBuffer" value="false" />
-  <parameter name="useRegistersForWriteBuffer" value="false" />
-  <parameter name="useRelativePathForSimFile" value="false" />
-  <parameter name="writeBufferDepth" value="64" />
-  <parameter name="writeIRQThreshold" value="8" />
- </module>
- <module name="usdrx1_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
-  <parameter name="ADC_DATA_WIDTH" value="512" />
-  <parameter name="DMA_ADDRESS_WIDTH" value="10" />
-  <parameter name="DMA_DATA_WIDTH" value="512" />
-  <parameter name="DMA_READY_ENABLE" value="1" />
- </module>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_uart.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814f0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet.control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814e8" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="avl_usdrx1_xcvr.core_pll_reconfig">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10018000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814a0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.csr">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181480" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10180800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181440" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_tx.descriptor_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181460" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="avl_usdrx1_xcvr.ip_reconfig">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10019000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="avl_phy_reconfig.reconfig_mgmt">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_ethernet_dma_rx.response">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814e0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10140000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_timer_1.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181420" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_timer_2.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181520" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_gpio_bd.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814d0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_gpio_in.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x101814c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_gpio_out.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181500" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_usdrx1_xcvr.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_ad9671_core_0.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10050000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_ad9671_core_1.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10060000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_ad9671_core_2.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10070000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_ad9671_core_3.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10080000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="axi_usdrx1_dma.s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10090000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.data_master"
-   end="sys_spi.spi_control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10181400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.instruction_master"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.instruction_master"
-   end="sys_cpu.debug_mem_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10180800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.instruction_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10140000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="axi_usdrx1_dma.m_dest_axi"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_ethernet_dma_tx.mm_read"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_ethernet_dma_rx.mm_write"
-   end="sys_ddr3_cntrl.avl">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.tightly_coupled_data_master_0"
-   end="sys_tlb_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="16.0"
-   start="sys_cpu.tightly_coupled_instruction_master_0"
-   end="sys_tlb_mem.s2">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10200000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon_streaming"
-   version="16.0"
-   start="sys_ethernet.receive"
-   end="sys_ethernet_dma_rx.st_sink" />
- <connection
-   kind="avalon_streaming"
-   version="16.0"
-   start="sys_ethernet_dma_tx.st_source"
-   end="sys_ethernet.transmit" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_ddr3_cntrl.afi_clk"
-   end="sys_dma_clk.clk_in" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_cpu.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_id.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_timer_1.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_timer_2.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_uart.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_bd.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_gpio_in.clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_gpio_out.clk" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_spi.clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_tlb_mem.clk1" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_tlb_mem.clk2" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet_dma_rx.clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet_dma_tx.clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet.control_port_clock_connection" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="usdrx1_adcfifo.if_dma_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="axi_usdrx1_dma.if_s_axis_aclk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_dma_clk.clk"
-   end="axi_usdrx1_dma.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="avl_phy_reconfig.mgmt_clk_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ddr3_cntrl.pll_ref_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet.receive_clock_connection" />
- <connection kind="clock" version="16.0" start="sys_clk.clk" end="sys_pll.refclk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_usdrx1_xcvr.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9671_core_0.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9671_core_1.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9671_core_2.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_ad9671_core_3.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="axi_usdrx1_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="avl_usdrx1_xcvr.sys_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="sys_clk.clk"
-   end="sys_ethernet.transmit_clock_connection" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_usdrx1_xcvr.core_clk"
-   end="usdrx1_adcfifo.if_adc_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_usdrx1_xcvr.core_clk"
-   end="axi_ad9671_core_0.if_rx_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_usdrx1_xcvr.core_clk"
-   end="axi_ad9671_core_1.if_rx_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_usdrx1_xcvr.core_clk"
-   end="axi_ad9671_core_2.if_rx_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_usdrx1_xcvr.core_clk"
-   end="axi_ad9671_core_3.if_rx_clk" />
- <connection
-   kind="clock"
-   version="16.0"
-   start="avl_usdrx1_xcvr.core_clk"
-   end="rx_core_clk.in_clk" />
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch0_0_to_xcvr"
-   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch1_1_to_xcvr"
-   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch2_2_to_xcvr"
-   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch3_3_to_xcvr"
-   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch4_4_to_xcvr"
-   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_4">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch5_5_to_xcvr"
-   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_5">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch6_6_to_xcvr"
-   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_6">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_phy_reconfig.ch7_7_to_xcvr"
-   end="avl_usdrx1_xcvr.phy_reconfig_to_xcvr_7">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="axi_usdrx1_xcvr.core_pll_locked"
-   end="avl_usdrx1_xcvr.core_pll_locked">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="usdrx1_adcfifo.if_dma_wdata"
-   end="axi_usdrx1_dma.if_s_axis_data">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="usdrx1_adcfifo.if_dma_wr"
-   end="axi_usdrx1_dma.if_s_axis_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="usdrx1_adcfifo.if_dma_wready"
-   end="axi_usdrx1_dma.if_s_axis_ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="usdrx1_adcfifo.if_dma_xfer_req"
-   end="axi_usdrx1_dma.if_s_axis_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_0"
-   end="avl_phy_reconfig.ch0_0_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_1"
-   end="avl_phy_reconfig.ch1_1_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_2"
-   end="avl_phy_reconfig.ch2_2_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_3"
-   end="avl_phy_reconfig.ch3_3_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_4"
-   end="avl_phy_reconfig.ch4_4_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_5"
-   end="avl_phy_reconfig.ch5_5_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_6"
-   end="avl_phy_reconfig.ch6_6_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.phy_reconfig_from_xcvr_7"
-   end="avl_phy_reconfig.ch7_7_from_xcvr">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="16.0"
-   start="avl_usdrx1_xcvr.ready"
-   end="axi_usdrx1_xcvr.ready">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_rx.csr_irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_ethernet_dma_tx.csr_irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="axi_usdrx1_dma.interrupt_sender">
-  <parameter name="irqNumber" value="11" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_uart.irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_timer_2.irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_timer_1.irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_gpio_in.irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="interrupt"
-   version="16.0"
-   start="sys_cpu.irq"
-   end="sys_gpio_bd.irq">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection kind="interrupt" version="16.0" start="sys_cpu.irq" end="sys_spi.irq">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_ddr3_cntrl.afi_reset"
-   end="sys_dma_clk.clk_in_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_cntrl.global_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="usdrx1_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_dma_clk.clk_reset"
-   end="usdrx1_adcfifo.if_adc_rst" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_dma_clk.clk_reset"
-   end="axi_usdrx1_dma.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="avl_phy_reconfig.mgmt_rst_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_pll.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_timer_1.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_timer_2.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_uart.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_bd.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_in.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_gpio_out.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_spi.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_int_mem.reset1" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_tlb_mem.reset1" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_tlb_mem.reset2" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet.reset_connection" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet_dma_rx.reset_n" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ethernet_dma_tx.reset_n" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_usdrx1_xcvr.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9671_core_0.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9671_core_1.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9671_core_2.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_ad9671_core_3.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="axi_usdrx1_dma.s_axi_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="sys_ddr3_cntrl.soft_reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_clk.clk_reset"
-   end="avl_usdrx1_xcvr.sys_resetn" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="sys_cpu.debug_reset_request"
-   end="sys_cpu.reset" />
- <connection
-   kind="reset"
-   version="16.0"
-   start="axi_usdrx1_xcvr.if_up_rst"
-   end="avl_usdrx1_xcvr.rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
-</system>
diff --git a/projects/usdrx1/a5gt/system_qsys_script.tcl b/projects/usdrx1/a5gt/system_qsys_script.tcl
deleted file mode 100644
index 2b3c37731..000000000
--- a/projects/usdrx1/a5gt/system_qsys_script.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-set mmu_enabled 1
-set ad_hdl_dir /home/icsomort/Git/hdl
-set ad_phdl_dir /home/icsomort/Git/hdl
-source system_qsys.tcl

From 180c96bcde226aa3da50860ee44a3060b622c68f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Dec 2016 15:37:05 +0000
Subject: [PATCH 822/972] Update .gitignore

---
 .gitignore | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/.gitignore b/.gitignore
index cb9d2a3cd..fc464ba0c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -29,6 +29,10 @@
 *.xrpt
 *.err
 *_html
+*.sld
+*.txt
+*.qsys
+*.csv
 xst
 netgen
 iseconfig
@@ -55,6 +59,7 @@ db
 *.qpf
 *.qws
 *.sof
+system_qsys_script.tcl
 hc_output
 hps_isw_handoff
 hps_sdram_*.csv

From ce47cf8d3030f371bb295c5b297ff14cfed833f5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Dec 2016 18:02:49 +0200
Subject: [PATCH 823/972] ad_sysref_gen: Fix sysref generation

Toggle sysref output just if the sysref_en is asserted.
---
 library/common/ad_sysref_gen.v | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/library/common/ad_sysref_gen.v b/library/common/ad_sysref_gen.v
index 0bf970890..61173acd1 100644
--- a/library/common/ad_sysref_gen.v
+++ b/library/common/ad_sysref_gen.v
@@ -77,8 +77,10 @@ module ad_sysref_gen (
 
   // generate SYSREF
   always @(posedge core_clk) begin
-    if (counter == SYSREF_HALFPERIOD) begin
-      sysref_out <= ~sysref_out;
+    if (sysref_en_int) begin
+      if (counter == SYSREF_HALFPERIOD) begin
+        sysref_out <= ~sysref_out;
+      end
     end else begin
       sysref_out <= 1'b0;
     end

From 1156aeac16188b9d18a0991a8ee988cc1e2e4135 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 19 Dec 2016 18:07:05 +0200
Subject: [PATCH 824/972] ad_sysref_gen: Update SYSREF related constraints

---
 projects/ad6676evb/vc707/system_constr.xdc   | 2 +-
 projects/ad6676evb/zc706/system_constr.xdc   | 2 +-
 projects/fmcadc2/vc707/system_constr.xdc     | 2 +-
 projects/fmcadc2/zc706/system_constr.xdc     | 2 +-
 projects/fmcjesdadc1/kc705/system_constr.xdc | 2 +-
 projects/fmcjesdadc1/vc707/system_constr.xdc | 2 +-
 projects/fmcjesdadc1/zc706/system_constr.xdc | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc
index e3c798d6d..2113457bd 100644
--- a/projects/ad6676evb/vc707/system_constr.xdc
+++ b/projects/ad6676evb/vc707/system_constr.xdc
@@ -36,5 +36,5 @@ create_clock -name rx_div_clk   -period  10.00 [get_pins i_system_wrapper/system
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
-set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]
 
diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc
index 54b6d22d3..e73918db8 100644
--- a/projects/ad6676evb/zc706/system_constr.xdc
+++ b/projects/ad6676evb/zc706/system_constr.xdc
@@ -36,5 +36,5 @@ create_clock -name rx_div_clk   -period  10.00 [get_pins i_system_wrapper/system
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
-set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]
 
diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc
index b0a63362c..f1caf236e 100644
--- a/projects/fmcadc2/vc707/system_constr.xdc
+++ b/projects/fmcadc2/vc707/system_constr.xdc
@@ -43,5 +43,5 @@ create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
-set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]
 
diff --git a/projects/fmcadc2/zc706/system_constr.xdc b/projects/fmcadc2/zc706/system_constr.xdc
index f811cf7de..1b4c18f41 100644
--- a/projects/fmcadc2/zc706/system_constr.xdc
+++ b/projects/fmcadc2/zc706/system_constr.xdc
@@ -43,5 +43,5 @@ create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
-set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]
 
diff --git a/projects/fmcjesdadc1/kc705/system_constr.xdc b/projects/fmcjesdadc1/kc705/system_constr.xdc
index 8a4142a24..ba04189fa 100644
--- a/projects/fmcjesdadc1/kc705/system_constr.xdc
+++ b/projects/fmcjesdadc1/kc705/system_constr.xdc
@@ -26,5 +26,5 @@ create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
-set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]
 
diff --git a/projects/fmcjesdadc1/vc707/system_constr.xdc b/projects/fmcjesdadc1/vc707/system_constr.xdc
index 42de9cede..ebeded59b 100644
--- a/projects/fmcjesdadc1/vc707/system_constr.xdc
+++ b/projects/fmcjesdadc1/vc707/system_constr.xdc
@@ -27,5 +27,5 @@ set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen
 set_false_path -to [get_cells i_system_wrapper/system_i/axi_ad9250_jesd/inst/rx_sysref_r_reg/D]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
-set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]
 
diff --git a/projects/fmcjesdadc1/zc706/system_constr.xdc b/projects/fmcjesdadc1/zc706/system_constr.xdc
index 97d65a600..963178e90 100644
--- a/projects/fmcjesdadc1/zc706/system_constr.xdc
+++ b/projects/fmcjesdadc1/zc706/system_constr.xdc
@@ -26,5 +26,5 @@ create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
-set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m*  && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]
 

From 3e57ff1fc55480f6d4dcde0488e9d54a9d758501 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 20 Dec 2016 16:14:38 -0500
Subject: [PATCH 825/972] z-mpsoc- map 0x4-0x8,0x7-0x9

---
 projects/scripts/adi_board.tcl | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index ced9504c5..3d7b22b29 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -532,11 +532,19 @@ proc ad_cpu_interconnect {p_address p_name} {
   set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
   set p_index 0
   foreach p_seg_name $p_seg {
-    if {($p_index == 0) && ($sys_zynq < 2)} {
+    if {$p_index == 0} {
       set p_seg_range [get_property range $p_seg_name]
       if {$p_seg_range < 0x1000} {
         set p_seg_range 0x1000
       }
+      if {$sys_zynq == 2} {
+        if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
+          set p_address [expr ($p_address + 0x40000000)]
+        }
+        if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
+          set p_address [expr ($p_address + 0x20000000)]
+        }
+      }
       create_bd_addr_seg -range $p_seg_range \
         -offset $p_address $sys_addr_cntrl_space \
         $p_seg_name "SEG_data_${p_name}"

From c0a2ef1ac43ee4ea9f2d27feaccfa99aa5387798 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 20 Dec 2016 16:18:15 -0500
Subject: [PATCH 826/972] library- altera power up warnings

---
 library/altera/axi_adxcvr/axi_adxcvr_up.v | 2 +-
 library/common/ad_axi_ip_constr.sdc       | 2 +-
 library/common/ad_axi_ip_constr.xdc       | 2 +-
 library/common/up_adc_common.v            | 4 ++--
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v
index 0ef6c3082..0980f19d8 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v
@@ -73,7 +73,7 @@ module axi_adxcvr_up #(
   reg                           up_wreq_d = 'd0;
   reg     [31:0]                up_scratch = 'd0;
   reg                           up_resetn = 'd0;
-  reg     [ 3:0]                up_rst_cnt = 'd0;
+  reg     [ 3:0]                up_rst_cnt = 'd8;
   reg                           up_status_int = 'd0;
   reg                           up_rreq_d = 'd0;
   reg     [31:0]                up_rdata_d = 'd0;
diff --git a/library/common/ad_axi_ip_constr.sdc b/library/common/ad_axi_ip_constr.sdc
index 4decbe86e..40c5058dc 100644
--- a/library/common/ad_axi_ip_constr.sdc
+++ b/library/common/ad_axi_ip_constr.sdc
@@ -8,5 +8,5 @@ set_false_path  -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_data*]
 set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|d_count_toggle*]       -to [get_registers *up_clock_mon:i_clock_mon|up_count_toggle_m1*]
 set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|d_count_hold*]         -to [get_registers *up_clock_mon:i_clock_mon|up_d_count*]
 set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|up_count_toggle*]      -to [get_registers *up_clock_mon:i_clock_mon|d_count_toggle_m1*]
-set_false_path  -from [get_registers *up_core_preset*]                                -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*]
+set_false_path  -from [get_registers *up_*preset*]                                    -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*]
 
diff --git a/library/common/ad_axi_ip_constr.xdc b/library/common/ad_axi_ip_constr.xdc
index 8fccb8018..ee5cfc941 100644
--- a/library/common/ad_axi_ip_constr.xdc
+++ b/library/common/ad_axi_ip_constr.xdc
@@ -16,5 +16,5 @@ set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data*        && I
 set_false_path -from [get_cells -hier -filter {name =~ *d_count_toggle_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_count_toggle_m1_reg && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {name =~ *d_count_hold*       && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_d_count*            && IS_SEQUENTIAL}]
 set_false_path -from [get_cells -hier -filter {name =~ *up_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_count_toggle_m1_reg  && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg     && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg      && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg     && IS_SEQUENTIAL}]
 
diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index 8101fa038..baefdb905 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -108,8 +108,8 @@ module up_adc_common #(
 
   // internal registers
 
-  reg             up_core_preset = 'd0;
-  reg             up_mmcm_preset = 'd0;
+  reg             up_core_preset = 'd1;
+  reg             up_mmcm_preset = 'd1;
   reg             up_wack_int = 'd0;
   reg     [31:0]  up_scratch = 'd0;
   reg             up_mmcm_resetn = 'd0;

From 4a783d523dd105cd3143ce7cace0dba07c446f71 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 20 Dec 2016 16:27:44 -0500
Subject: [PATCH 827/972] projects/altera* - default & common qsys commands

---
 projects/adrv9371x/a10gx/system_qsys.tcl   |  1 -
 projects/adrv9371x/a10soc/system_qsys.tcl  |  1 -
 projects/common/altera/sys_gen.tcl         | 10 ++++++++++
 projects/daq1/a10gx/system_qsys.tcl        |  1 -
 projects/daq2/a10gx/system_qsys.tcl        |  1 -
 projects/daq3/a10gx/system_qsys.tcl        |  1 -
 projects/fmcjesdadc1/a5gt/system_qsys.tcl  |  1 -
 projects/fmcjesdadc1/a5soc/system_qsys.tcl |  1 -
 projects/fmcomms2/a10gx/system_qsys.tcl    |  1 -
 projects/usdrx1/a5gt/system_qsys.tcl       |  1 -
 10 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/projects/adrv9371x/a10gx/system_qsys.tcl b/projects/adrv9371x/a10gx/system_qsys.tcl
index 755fe771c..7bf3e3032 100644
--- a/projects/adrv9371x/a10gx/system_qsys.tcl
+++ b/projects/adrv9371x/a10gx/system_qsys.tcl
@@ -3,5 +3,4 @@
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/adrv9371x_qsys.tcl
 
-save_system "system_bd.qsys"
 
diff --git a/projects/adrv9371x/a10soc/system_qsys.tcl b/projects/adrv9371x/a10soc/system_qsys.tcl
index 2b861df8a..7581f7875 100644
--- a/projects/adrv9371x/a10soc/system_qsys.tcl
+++ b/projects/adrv9371x/a10soc/system_qsys.tcl
@@ -3,5 +3,4 @@
 source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
 source ../common/adrv9371x_qsys.tcl
 
-save_system "system_bd.qsys"
 
diff --git a/projects/common/altera/sys_gen.tcl b/projects/common/altera/sys_gen.tcl
index 25eaa37ad..0b26fb5ab 100644
--- a/projects/common/altera/sys_gen.tcl
+++ b/projects/common/altera/sys_gen.tcl
@@ -28,8 +28,18 @@ puts $QFILE "set mmu_enabled $mmu_enabled"
 puts $QFILE "set ad_hdl_dir $ad_hdl_dir"
 puts $QFILE "set ad_phdl_dir $ad_phdl_dir"
 puts $QFILE "source system_qsys.tcl"
+puts $QFILE "set_interconnect_requirement {\$system} {qsys_mm.clockCrossingAdapter} {FIFO}"
+puts $QFILE "set_interconnect_requirement {\$system} {qsys_mm.maxAdditionalLatency} {2}"
+puts $QFILE "save_system {system_bd.qsys}"
 close $QFILE
 
 exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \
   --script=system_qsys_script.tcl
 
+# remove altshift_taps
+
+set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity up_xfer_cntrl
+set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity up_xfer_status
+set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity up_clock_mon
+set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity ad_rst
+
diff --git a/projects/daq1/a10gx/system_qsys.tcl b/projects/daq1/a10gx/system_qsys.tcl
index aceed4aac..03e9d49f3 100644
--- a/projects/daq1/a10gx/system_qsys.tcl
+++ b/projects/daq1/a10gx/system_qsys.tcl
@@ -2,5 +2,4 @@
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/daq1_qsys.tcl
 
-save_system "system_bd.qsys"
 
diff --git a/projects/daq2/a10gx/system_qsys.tcl b/projects/daq2/a10gx/system_qsys.tcl
index 2216c761a..47d33019c 100644
--- a/projects/daq2/a10gx/system_qsys.tcl
+++ b/projects/daq2/a10gx/system_qsys.tcl
@@ -2,5 +2,4 @@
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/daq2_qsys.tcl
 
-save_system "system_bd.qsys"
 
diff --git a/projects/daq3/a10gx/system_qsys.tcl b/projects/daq3/a10gx/system_qsys.tcl
index b2209593e..9b5d24188 100644
--- a/projects/daq3/a10gx/system_qsys.tcl
+++ b/projects/daq3/a10gx/system_qsys.tcl
@@ -3,5 +3,4 @@
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/daq3_qsys.tcl
 
-save_system "system_bd.qsys"
 
diff --git a/projects/fmcjesdadc1/a5gt/system_qsys.tcl b/projects/fmcjesdadc1/a5gt/system_qsys.tcl
index d0094590a..deb2e98ce 100644
--- a/projects/fmcjesdadc1/a5gt/system_qsys.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_qsys.tcl
@@ -2,5 +2,4 @@
 source $ad_hdl_dir/projects/common/a5gt/a5gt_system_qsys.tcl
 source ../common/fmcjesdadc1_qsys.tcl
 
-save_system "system_bd.qsys"
 
diff --git a/projects/fmcjesdadc1/a5soc/system_qsys.tcl b/projects/fmcjesdadc1/a5soc/system_qsys.tcl
index 72ef9d073..de697ac32 100644
--- a/projects/fmcjesdadc1/a5soc/system_qsys.tcl
+++ b/projects/fmcjesdadc1/a5soc/system_qsys.tcl
@@ -3,5 +3,4 @@ source $ad_hdl_dir/projects/common/a5soc/a5soc_system_qsys.tcl
 source ../common/fmcjesdadc1_qsys.tcl
 
 set_instance_parameter_value avl_ad9250_xcvr {SYSCLK_FREQUENCY} {50.0}
-save_system "system_bd.qsys"
 
diff --git a/projects/fmcomms2/a10gx/system_qsys.tcl b/projects/fmcomms2/a10gx/system_qsys.tcl
index 04e76cacf..0e76976f5 100644
--- a/projects/fmcomms2/a10gx/system_qsys.tcl
+++ b/projects/fmcomms2/a10gx/system_qsys.tcl
@@ -2,5 +2,4 @@
 source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
 source ../common/fmcomms2_qsys.tcl
 
-save_system "system_bd.qsys"
 
diff --git a/projects/usdrx1/a5gt/system_qsys.tcl b/projects/usdrx1/a5gt/system_qsys.tcl
index 968d1161c..cf7c6ae15 100644
--- a/projects/usdrx1/a5gt/system_qsys.tcl
+++ b/projects/usdrx1/a5gt/system_qsys.tcl
@@ -2,5 +2,4 @@
 source $ad_hdl_dir/projects/common/a5gt/a5gt_system_qsys.tcl
 source ../common/usdrx1_qsys.tcl
 
-save_system "system_bd.qsys"
 

From c78c9cf633d8bc44a45232f87f2be750cbf7a908 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 21 Dec 2016 10:06:56 +0200
Subject: [PATCH 828/972] util_fir_int: Updated coefficient file

---
 library/util_fir_int/coefile_int.coe | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/util_fir_int/coefile_int.coe b/library/util_fir_int/coefile_int.coe
index 10c6cfe27..d7aee256a 100644
--- a/library/util_fir_int/coefile_int.coe
+++ b/library/util_fir_int/coefile_int.coe
@@ -1,6 +1,6 @@
 ; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
 ; Generated by MATLAB(R) 9.0 and the DSP System Toolbox 9.2.
-; Generated on: 21-Oct-2016 22:25:08
+; Generated on: 20-Dec-2016 18:03:34
 Radix = 10; 
 Coefficient_Width = 16; 
 CoefData =     0,

From eba30b0cdeddf160cefbcd2b16cffecd5ad3bc07 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Dec 2016 16:11:37 -0500
Subject: [PATCH 829/972] projects/altera- qii_auto_pack option

---
 projects/common/altera/sys_gen.tcl | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/projects/common/altera/sys_gen.tcl b/projects/common/altera/sys_gen.tcl
index 0b26fb5ab..c0f2114e1 100644
--- a/projects/common/altera/sys_gen.tcl
+++ b/projects/common/altera/sys_gen.tcl
@@ -42,4 +42,8 @@ set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity
 set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity up_xfer_status
 set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity up_clock_mon
 set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity ad_rst
+set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
+set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
+set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_clock_mon
+set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity ad_rst
 

From 1ceec2e2a9a507c6fff353e7618cc0a808f9df6b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Dec 2016 16:20:36 -0500
Subject: [PATCH 830/972] projects/a5gt- use 50m afi clock for cpu- xcvr
 reconfig timing

---
 projects/common/a5gt/a5gt_system_assign.tcl |  3 ++
 projects/common/a5gt/a5gt_system_qsys.tcl   | 31 +++++++++++++++++----
 2 files changed, 28 insertions(+), 6 deletions(-)

diff --git a/projects/common/a5gt/a5gt_system_assign.tcl b/projects/common/a5gt/a5gt_system_assign.tcl
index 0d9830885..2c7377bd8 100644
--- a/projects/common/a5gt/a5gt_system_assign.tcl
+++ b/projects/common/a5gt/a5gt_system_assign.tcl
@@ -807,6 +807,9 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[8]
 set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[9]
 set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[10]
 
+set_instance_assignment -name OPTIMIZATION_TECHNIQUE SPEED -to *
+set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -to *
+
 # source defaults
 
 source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
diff --git a/projects/common/a5gt/a5gt_system_qsys.tcl b/projects/common/a5gt/a5gt_system_qsys.tcl
index f79d4d802..9ff874d16 100644
--- a/projects/common/a5gt/a5gt_system_qsys.tcl
+++ b/projects/common/a5gt/a5gt_system_qsys.tcl
@@ -9,12 +9,21 @@ set system_type nios
 
 # clock-&-reset
 
+add_instance sys_ref_clk clock_source 16.0
+add_interface sys_ref_clk clock sink
+add_interface sys_ref_rst reset sink
+set_interface_property sys_ref_clk EXPORT_OF sys_ref_clk.clk_in
+set_interface_property sys_ref_rst EXPORT_OF sys_ref_clk.clk_in_reset
+set_instance_parameter_value sys_ref_clk {clockFrequency} {100000000.0}
+set_instance_parameter_value sys_ref_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_ref_clk {resetSynchronousEdges} {DEASSERT}
+
 add_instance sys_clk clock_source 16.0
 add_interface sys_clk clock sink
 add_interface sys_rst reset sink
 set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
 set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
-set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
+set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
 set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
 set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
 
@@ -27,8 +36,8 @@ set_instance_parameter_value sys_pll {gui_number_of_clocks} {3}
 set_instance_parameter_value sys_pll {gui_output_clock_frequency0} {125.0}
 set_instance_parameter_value sys_pll {gui_output_clock_frequency1} {25.0}
 set_instance_parameter_value sys_pll {gui_output_clock_frequency2} {2.5}
-add_connection sys_clk.clk sys_pll.refclk
-add_connection sys_clk.clk_reset sys_pll.reset
+add_connection sys_ref_clk.clk sys_pll.refclk
+add_connection sys_ref_clk.clk_reset sys_pll.reset
 add_interface sys_125m_clk clock source
 add_interface sys_25m_clk clock source
 add_interface sys_2m5_clk clock source
@@ -67,6 +76,7 @@ set_instance_parameter_value sys_ddr3_cntrl {SPEED_GRADE} {3}
 set_instance_parameter_value sys_ddr3_cntrl {MEM_CLK_FREQ} {400.0}
 set_instance_parameter_value sys_ddr3_cntrl {REF_CLK_FREQ} {100.0}
 set_instance_parameter_value sys_ddr3_cntrl {RATE} {Quarter}
+set_instance_parameter_value sys_ddr3_cntrl {EXPORT_AFI_HALF_CLK} {1}
 set_instance_parameter_value sys_ddr3_cntrl {MEM_VENDOR} {Micron}
 set_instance_parameter_value sys_ddr3_cntrl {MEM_CLK_FREQ_MAX} {666.667}
 set_instance_parameter_value sys_ddr3_cntrl {MEM_DQ_WIDTH} {64}
@@ -100,14 +110,23 @@ set_instance_parameter_value sys_ddr3_cntrl {MEM_TFAW_NS} {30.0}
 set_instance_parameter_value sys_ddr3_cntrl {MEM_TRRD_NS} {6.0}
 set_instance_parameter_value sys_ddr3_cntrl {MEM_TRTP_NS} {7.5}
 set_instance_parameter_value sys_ddr3_cntrl {AVL_MAX_SIZE} {256}
-add_connection sys_clk.clk sys_ddr3_cntrl.pll_ref_clk
-add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset
-add_connection sys_clk.clk_reset sys_ddr3_cntrl.soft_reset
+add_connection sys_ref_clk.clk sys_ddr3_cntrl.pll_ref_clk
+add_connection sys_ref_clk.clk_reset sys_ddr3_cntrl.global_reset
+add_connection sys_ref_clk.clk_reset sys_ddr3_cntrl.soft_reset
 add_interface sys_ddr3_cntrl_mem conduit end
 set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.memory
 add_interface sys_ddr3_cntrl_oct conduit end
 set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct
 
+# cpu clock
+
+add_instance sys_cpu_clk clock_source 16.0
+add_connection sys_ddr3_cntrl.afi_half_clk sys_cpu_clk.clk_in
+add_connection sys_ddr3_cntrl.afi_reset sys_cpu_clk.clk_in_reset
+add_interface sys_cpu_clk clock source
+set_interface_property sys_cpu_clk EXPORT_OF sys_cpu_clk.clk
+add_interface sys_cpu_reset reset source
+set_interface_property sys_cpu_reset EXPORT_OF sys_cpu_clk.clk_reset
 
 # cpu
 

From f1168f9e290db311da289d6f1d4a5223c57e1c0b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Dec 2016 16:21:57 -0500
Subject: [PATCH 831/972] fmcjesdadc1/a5gt- use xilinx setup 2-dma

---
 .../fmcjesdadc1/common/fmcjesdadc1_qsys.tcl   | 109 +++++++++++-------
 1 file changed, 65 insertions(+), 44 deletions(-)

diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
index 14f2ab91e..dc0cada5e 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl
@@ -6,6 +6,7 @@ set_instance_parameter_value avl_ad9250_xcvr {ID} {1}
 set_instance_parameter_value avl_ad9250_xcvr {TX_OR_RX_N} {0}
 set_instance_parameter_value avl_ad9250_xcvr {PCS_CONFIG} {JESD_PCS_CFG1}
 set_instance_parameter_value avl_ad9250_xcvr {LANE_RATE} {5000.0}
+set_instance_parameter_value avl_ad9250_xcvr {SYSCLK_FREQUENCY} {50.0}
 set_instance_parameter_value avl_ad9250_xcvr {PLLCLK_FREQUENCY} {2500.0}
 set_instance_parameter_value avl_ad9250_xcvr {REFCLK_FREQUENCY} {250.0}
 set_instance_parameter_value avl_ad9250_xcvr {CORECLK_FREQUENCY} {125.0}
@@ -74,54 +75,71 @@ add_connection sys_clk.clk axi_ad9250_core_1.s_axi_clock
 
 # ad9250-pack
 
-add_instance util_ad9250_cpack util_cpack 1.0
-set_instance_parameter_value util_ad9250_cpack {CHANNEL_DATA_WIDTH} {32}
-set_instance_parameter_value util_ad9250_cpack {NUM_OF_CHANNELS} {4}
+add_instance util_ad9250_cpack_0 util_cpack 1.0
+set_instance_parameter_value util_ad9250_cpack_0 {CHANNEL_DATA_WIDTH} {32}
+set_instance_parameter_value util_ad9250_cpack_0 {NUM_OF_CHANNELS} {2}
 
-add_connection sys_clk.clk_reset util_ad9250_cpack.if_adc_rst
-add_connection sys_dma_clk.clk_reset util_ad9250_cpack.if_adc_rst
-add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack.if_adc_clk
-add_connection axi_ad9250_core_0.adc_ch_0 util_ad9250_cpack.adc_ch_0
-add_connection axi_ad9250_core_0.adc_ch_1 util_ad9250_cpack.adc_ch_1
-add_connection axi_ad9250_core_1.adc_ch_0 util_ad9250_cpack.adc_ch_2
-add_connection axi_ad9250_core_1.adc_ch_1 util_ad9250_cpack.adc_ch_3
+add_connection sys_clk.clk_reset util_ad9250_cpack_0.if_adc_rst
+add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack_0.if_adc_clk
+add_connection axi_ad9250_core_0.adc_ch_0 util_ad9250_cpack_0.adc_ch_0
+add_connection axi_ad9250_core_0.adc_ch_1 util_ad9250_cpack_0.adc_ch_1
 
-# ad9250-fifo
+add_instance util_ad9250_cpack_1 util_cpack 1.0
+set_instance_parameter_value util_ad9250_cpack_1 {CHANNEL_DATA_WIDTH} {32}
+set_instance_parameter_value util_ad9250_cpack_1 {NUM_OF_CHANNELS} {2}
 
-add_instance ad9250_adcfifo util_adcfifo 1.0
-set_instance_parameter_value ad9250_adcfifo {ADC_DATA_WIDTH} {128}
-set_instance_parameter_value ad9250_adcfifo {DMA_DATA_WIDTH} {128}
-set_instance_parameter_value ad9250_adcfifo {DMA_ADDRESS_WIDTH} {16}
-
-add_connection sys_clk.clk_reset ad9250_adcfifo.if_adc_rst
-add_connection sys_dma_clk.clk_reset ad9250_adcfifo.if_adc_rst
-add_connection avl_ad9250_xcvr.core_clk ad9250_adcfifo.if_adc_clk
-add_connection util_ad9250_cpack.if_adc_valid ad9250_adcfifo.if_adc_wr
-add_connection util_ad9250_cpack.if_adc_data ad9250_adcfifo.if_adc_wdata
-add_connection sys_dma_clk.clk ad9250_adcfifo.if_dma_clk
+add_connection sys_clk.clk_reset util_ad9250_cpack_1.if_adc_rst
+add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack_1.if_adc_clk
+add_connection axi_ad9250_core_1.adc_ch_0 util_ad9250_cpack_1.adc_ch_0
+add_connection axi_ad9250_core_1.adc_ch_1 util_ad9250_cpack_1.adc_ch_1
 
 # ad9250-dma
 
-add_instance axi_ad9250_dma axi_dmac 1.0
-set_instance_parameter_value axi_ad9250_dma {DMA_DATA_WIDTH_SRC} {128}
-set_instance_parameter_value axi_ad9250_dma {DMA_DATA_WIDTH_DEST} {128}
-set_instance_parameter_value axi_ad9250_dma {DMA_LENGTH_WIDTH} {24}
-set_instance_parameter_value axi_ad9250_dma {DMA_2D_TRANSFER} {0}
-set_instance_parameter_value axi_ad9250_dma {SYNC_TRANSFER_START} {1}
-set_instance_parameter_value axi_ad9250_dma {CYCLIC} {0}
-set_instance_parameter_value axi_ad9250_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_ad9250_dma {DMA_TYPE_SRC} {1}
+add_instance axi_ad9250_dma_0 axi_dmac 1.0
+set_instance_parameter_value axi_ad9250_dma_0 {DMA_TYPE_SRC} {2}
+set_instance_parameter_value axi_ad9250_dma_0 {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9250_dma_0 {ID} {0}
+set_instance_parameter_value axi_ad9250_dma_0 {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9250_dma_0 {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_ad9250_dma_0 {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_ad9250_dma_0 {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9250_dma_0 {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9250_dma_0 {CYCLIC} {0}
+set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_DEST} {64}
 
-add_connection sys_dma_clk.clk axi_ad9250_dma.if_s_axis_aclk
-add_connection ad9250_adcfifo.if_dma_wr axi_ad9250_dma.if_s_axis_valid
-add_connection ad9250_adcfifo.if_dma_wdata axi_ad9250_dma.if_s_axis_data
-add_connection ad9250_adcfifo.if_dma_wready axi_ad9250_dma.if_s_axis_ready
-add_connection ad9250_adcfifo.if_dma_xfer_req axi_ad9250_dma.if_s_axis_xfer_req
-add_connection ad9250_adcfifo.if_adc_wovf axi_ad9250_core_0.if_adc_dovf
-add_connection sys_clk.clk_reset axi_ad9250_dma.s_axi_reset
-add_connection sys_clk.clk axi_ad9250_dma.s_axi_clock
-add_connection sys_dma_clk.clk_reset axi_ad9250_dma.m_dest_axi_reset
-add_connection sys_dma_clk.clk axi_ad9250_dma.m_dest_axi_clock
+add_connection avl_ad9250_xcvr.core_clk axi_ad9250_dma_0.if_fifo_wr_clk
+add_connection util_ad9250_cpack_0.if_adc_valid axi_ad9250_dma_0.if_fifo_wr_en
+add_connection util_ad9250_cpack_0.if_adc_sync axi_ad9250_dma_0.if_fifo_wr_sync
+add_connection util_ad9250_cpack_0.if_adc_data axi_ad9250_dma_0.if_fifo_wr_din
+add_connection axi_ad9250_dma_0.if_fifo_wr_overflow axi_ad9250_core_0.if_adc_dovf
+add_connection sys_clk.clk_reset axi_ad9250_dma_0.s_axi_reset
+add_connection sys_clk.clk axi_ad9250_dma_0.s_axi_clock
+add_connection sys_dma_clk.clk_reset axi_ad9250_dma_0.m_dest_axi_reset
+add_connection sys_dma_clk.clk axi_ad9250_dma_0.m_dest_axi_clock
+
+add_instance axi_ad9250_dma_1 axi_dmac 1.0
+set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_SRC} {2}
+set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_ad9250_dma_1 {ID} {0}
+set_instance_parameter_value axi_ad9250_dma_1 {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_ad9250_dma_1 {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_ad9250_dma_1 {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_ad9250_dma_1 {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_ad9250_dma_1 {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_ad9250_dma_1 {CYCLIC} {0}
+set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_DEST} {64}
+
+add_connection avl_ad9250_xcvr.core_clk axi_ad9250_dma_1.if_fifo_wr_clk
+add_connection util_ad9250_cpack_1.if_adc_valid axi_ad9250_dma_1.if_fifo_wr_en
+add_connection util_ad9250_cpack_1.if_adc_sync axi_ad9250_dma_1.if_fifo_wr_sync
+add_connection util_ad9250_cpack_1.if_adc_data axi_ad9250_dma_1.if_fifo_wr_din
+add_connection axi_ad9250_dma_1.if_fifo_wr_overflow axi_ad9250_core_1.if_adc_dovf
+add_connection sys_clk.clk_reset axi_ad9250_dma_1.s_axi_reset
+add_connection sys_clk.clk axi_ad9250_dma_1.s_axi_clock
+add_connection sys_dma_clk.clk_reset axi_ad9250_dma_1.m_dest_axi_reset
+add_connection sys_dma_clk.clk axi_ad9250_dma_1.m_dest_axi_clock
 
 # core-clock
 
@@ -154,13 +172,16 @@ ad_cpu_interconnect 0x00019000 avl_ad9250_xcvr.ip_reconfig
 ad_cpu_interconnect 0x00020000 axi_ad9250_xcvr.s_axi
 ad_cpu_interconnect 0x00050000 axi_ad9250_core_0.s_axi
 ad_cpu_interconnect 0x00060000 axi_ad9250_core_1.s_axi
-ad_cpu_interconnect 0x00070000 axi_ad9250_dma.s_axi
+ad_cpu_interconnect 0x00070000 axi_ad9250_dma_0.s_axi
+ad_cpu_interconnect 0x00080000 axi_ad9250_dma_1.s_axi
 
 # dma interconnects
 
-ad_dma_interconnect axi_ad9250_dma.m_dest_axi
+ad_dma_interconnect axi_ad9250_dma_0.m_dest_axi
+ad_dma_interconnect axi_ad9250_dma_1.m_dest_axi
 
 # interrupts
 
-ad_cpu_interrupt 11 axi_ad9250_dma.interrupt_sender
+ad_cpu_interrupt 11 axi_ad9250_dma_0.interrupt_sender
+ad_cpu_interrupt 12 axi_ad9250_dma_1.interrupt_sender
 

From 5d683943abc9079164ff2b7b375434da2f12d4da Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Dec 2016 16:23:36 -0500
Subject: [PATCH 832/972] fmcjesdadc1/a5gt- remove ad-sysref-gen-pack

---
 projects/fmcjesdadc1/a5gt/system_project.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl
index b3e33607a..2961b1111 100755
--- a/projects/fmcjesdadc1/a5gt/system_project.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_project.tcl
@@ -61,8 +61,8 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
 
 # disable auto-pack
 
-set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
-set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
+set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity ad_sysref_gen
+set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity ad_sysref_gen
 
 execute_flow -compile
 

From 2bea337aa209b86cca190af156f67bb3c0bc8b09 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 21 Dec 2016 16:24:10 -0500
Subject: [PATCH 833/972] fmcjesdadc1/a5gt- use 50m-mem-cpu-clk

---
 projects/fmcjesdadc1/a5gt/system_top.v | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/projects/fmcjesdadc1/a5gt/system_top.v b/projects/fmcjesdadc1/a5gt/system_top.v
index af40255ba..7591642c5 100644
--- a/projects/fmcjesdadc1/a5gt/system_top.v
+++ b/projects/fmcjesdadc1/a5gt/system_top.v
@@ -105,6 +105,9 @@ module system_top (
   wire              sys_125m_clk;
   wire              sys_25m_clk;
   wire              sys_2m5_clk;
+  wire              sys_cpu_clk;
+  wire              sys_cpu_mem_resetn;
+  wire              sys_cpu_resetn;
   wire              sys_pll_locked;
   wire              eth_tx_clk;
   wire              eth_tx_mode_1g;
@@ -118,6 +121,10 @@ module system_top (
   wire    [ 63:0]   gpio_o;
   wire    [  7:0]   spi_csn_s;
 
+  // sys reset
+
+  assign sys_cpu_resetn = sys_resetn & sys_cpu_mem_resetn & sys_pll_locked;
+
   // ethernet transmit clock
 
   assign eth_tx_clk = (eth_tx_mode_1g == 1'b1) ? sys_125m_clk :
@@ -194,7 +201,9 @@ module system_top (
     .sys_125m_clk_clk (sys_125m_clk),
     .sys_25m_clk_clk (sys_25m_clk),
     .sys_2m5_clk_clk (sys_2m5_clk),
-    .sys_clk_clk (sys_clk),
+    .sys_clk_clk (sys_cpu_clk),
+    .sys_cpu_clk_clk (sys_cpu_clk),
+    .sys_cpu_reset_reset_n (sys_cpu_mem_resetn),
     .sys_ddr3_cntrl_mem_mem_a (ddr3_a),
     .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
     .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
@@ -230,7 +239,9 @@ module system_top (
     .sys_gpio_in_export (gpio_i[63:32]),
     .sys_gpio_out_export (gpio_o[63:32]),
     .sys_pll_locked_export (sys_pll_locked),
-    .sys_rst_reset_n (sys_resetn),
+    .sys_ref_clk_clk (sys_clk),
+    .sys_ref_rst_reset_n (sys_resetn),
+    .sys_rst_reset_n (sys_cpu_resetn),
     .sys_spi_MISO (spi_miso),
     .sys_spi_MOSI (spi_mosi),
     .sys_spi_SCLK (spi_clk),

From 18660c7ab4be28ab18c8c72749c6fadc9e2d0d21 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 22 Dec 2016 14:13:14 -0500
Subject: [PATCH 834/972] fmcjesdadc1/a5gt: ddr3 use ip constraints

---
 projects/common/a5gt/a5gt_system_assign.tcl  | 36 --------------------
 projects/fmcjesdadc1/a5gt/system_constr.sdc  | 14 ++++----
 projects/fmcjesdadc1/a5gt/system_project.tcl |  5 +--
 3 files changed, 10 insertions(+), 45 deletions(-)

diff --git a/projects/common/a5gt/a5gt_system_assign.tcl b/projects/common/a5gt/a5gt_system_assign.tcl
index 2c7377bd8..474afa6ca 100644
--- a/projects/common/a5gt/a5gt_system_assign.tcl
+++ b/projects/common/a5gt/a5gt_system_assign.tcl
@@ -659,42 +659,6 @@ set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -
 set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[30] 
 set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[31] 
 
-set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_ddr3_cntrl 
-
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_addr_cmd_clk 
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_avl_clk 
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_config_clk 
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_afi_clk 
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_hr_clk 
-
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[4].read_capture_clk_buffer 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[5].read_capture_clk_buffer 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[6].read_capture_clk_buffer 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[7].read_capture_clk_buffer 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7] 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_mem_stable_n 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_n 
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n 
-
 # ethernet interface
 
 set_location_assignment PIN_A6 -to eth_rx_clk
diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc
index 347372ac5..f6da22797 100644
--- a/projects/fmcjesdadc1/a5gt/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc
@@ -11,17 +11,17 @@ set_clock_groups -exclusive \
   -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
   -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
 
-set_false_path -to [get_registers {rx_sysref_m1}]
+set_false_path -to [get_registers *sysref_en_m1*]
 
-set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\
+set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_ctl_inst*] \
   -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
 
-set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
-  -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_clk}]
+set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
+  -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
 
-set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\
+set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_csr_inst*] \
   -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
 
-set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
-  -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk}]
+set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
+  -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
 
diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl
index 2961b1111..7259c58f5 100755
--- a/projects/fmcjesdadc1/a5gt/system_project.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_project.tcl
@@ -61,8 +61,9 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
 
 # disable auto-pack
 
-set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity ad_sysref_gen
-set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity ad_sysref_gen
+set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS OFF
 
 execute_flow -compile
 

From aa6c94c9938ac93f61cdda75ed31fb26c3b15715 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 22 Dec 2016 14:13:41 -0500
Subject: [PATCH 835/972] usdrx1/a5gt: ddr3 use ip constraints

---
 projects/usdrx1/a5gt/system_constr.sdc  | 16 +++++++---------
 projects/usdrx1/a5gt/system_project.tcl |  6 ++++++
 projects/usdrx1/a5gt/system_top.v       | 15 +++++++++++++--
 projects/usdrx1/common/usdrx1_qsys.tcl  |  1 +
 4 files changed, 27 insertions(+), 11 deletions(-)

diff --git a/projects/usdrx1/a5gt/system_constr.sdc b/projects/usdrx1/a5gt/system_constr.sdc
index fdfd94802..d8320bcbf 100644
--- a/projects/usdrx1/a5gt/system_constr.sdc
+++ b/projects/usdrx1/a5gt/system_constr.sdc
@@ -11,19 +11,17 @@ set_clock_groups -exclusive \
   -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
   -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
 
-set_false_path -to [get_registers {rx_sysref_m1}]
+set_false_path -to [get_registers *sysref_en_m1*]
 
-set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\
+set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_ctl_inst*] \
   -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
 
-set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
-  -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_clk}]
+set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
+  -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
 
-set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\
+set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_csr_inst*] \
   -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
 
-set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\
-  -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk}]
+set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
+  -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
 
-set_false_path -from [get_clocks {sys_clk}] [get_nets *sysref_en*] \
-  -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
diff --git a/projects/usdrx1/a5gt/system_project.tcl b/projects/usdrx1/a5gt/system_project.tcl
index 8432b7f02..369f2e733 100644
--- a/projects/usdrx1/a5gt/system_project.tcl
+++ b/projects/usdrx1/a5gt/system_project.tcl
@@ -167,5 +167,11 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[11]
 set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[12]
 set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[13]
 
+# disable auto-pack
+
+set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS OFF
+
 execute_flow -compile
 
diff --git a/projects/usdrx1/a5gt/system_top.v b/projects/usdrx1/a5gt/system_top.v
index 2e7836be1..99797bf10 100644
--- a/projects/usdrx1/a5gt/system_top.v
+++ b/projects/usdrx1/a5gt/system_top.v
@@ -133,6 +133,9 @@ module system_top (
   wire              sys_125m_clk;
   wire              sys_25m_clk;
   wire              sys_2m5_clk;
+  wire              sys_cpu_clk;
+  wire              sys_cpu_mem_resetn;
+  wire              sys_cpu_resetn;
   wire              sys_pll_locked;
   wire              eth_tx_clk;
   wire              eth_tx_mode_1g;
@@ -152,6 +155,10 @@ module system_top (
   wire    [ 63:0]   gpio_i;
   wire    [ 63:0]   gpio_o;
 
+  // sys reset
+
+  assign sys_cpu_resetn = sys_resetn & sys_cpu_mem_resetn & sys_pll_locked;
+
   // ethernet transmit clock
 
   assign eth_tx_clk = (eth_tx_mode_1g == 1'b1) ? sys_125m_clk :
@@ -322,7 +329,9 @@ module system_top (
     .sys_125m_clk_clk (sys_125m_clk),
     .sys_25m_clk_clk (sys_25m_clk),
     .sys_2m5_clk_clk (sys_2m5_clk),
-    .sys_clk_clk (sys_clk),
+    .sys_clk_clk (sys_cpu_clk),
+    .sys_cpu_clk_clk (sys_cpu_clk),
+    .sys_cpu_reset_reset_n (sys_cpu_mem_resetn),
     .sys_ddr3_cntrl_mem_mem_a (ddr3_a),
     .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
     .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
@@ -358,7 +367,9 @@ module system_top (
     .sys_gpio_in_export (gpio_i[63:32]),
     .sys_gpio_out_export (gpio_o[63:32]),
     .sys_pll_locked_export (sys_pll_locked),
-    .sys_rst_reset_n (sys_resetn),
+    .sys_ref_clk_clk (sys_clk),
+    .sys_ref_rst_reset_n (sys_resetn),
+    .sys_rst_reset_n (sys_cpu_resetn),
     .sys_spi_MISO (spi_miso),
     .sys_spi_MOSI (spi_mosi),
     .sys_spi_SCLK (spi_clk),
diff --git a/projects/usdrx1/common/usdrx1_qsys.tcl b/projects/usdrx1/common/usdrx1_qsys.tcl
index dd10d8195..d30af0ead 100644
--- a/projects/usdrx1/common/usdrx1_qsys.tcl
+++ b/projects/usdrx1/common/usdrx1_qsys.tcl
@@ -6,6 +6,7 @@ set_instance_parameter_value avl_usdrx1_xcvr {ID} {1}
 set_instance_parameter_value avl_usdrx1_xcvr {TX_OR_RX_N} {0}
 set_instance_parameter_value avl_usdrx1_xcvr {PCS_CONFIG} {JESD_PCS_CFG1}
 set_instance_parameter_value avl_usdrx1_xcvr {LANE_RATE} {3200.0}
+set_instance_parameter_value avl_usdrx1_xcvr {SYSCLK_FREQUENCY} {50.0}
 set_instance_parameter_value avl_usdrx1_xcvr {PLLCLK_FREQUENCY} {1600.0}
 set_instance_parameter_value avl_usdrx1_xcvr {REFCLK_FREQUENCY} {80.0}
 set_instance_parameter_value avl_usdrx1_xcvr {CORECLK_FREQUENCY} {80.0}

From b089173b4caac061ccf46d3cfe8a70613a5a316c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 22 Dec 2016 14:14:10 -0500
Subject: [PATCH 836/972] fmcjesdadc1/a5soc- cpu clock is 50m for a5gt also

---
 projects/fmcjesdadc1/a5soc/system_qsys.tcl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/projects/fmcjesdadc1/a5soc/system_qsys.tcl b/projects/fmcjesdadc1/a5soc/system_qsys.tcl
index de697ac32..bcc3f2550 100644
--- a/projects/fmcjesdadc1/a5soc/system_qsys.tcl
+++ b/projects/fmcjesdadc1/a5soc/system_qsys.tcl
@@ -2,5 +2,4 @@
 source $ad_hdl_dir/projects/common/a5soc/a5soc_system_qsys.tcl
 source ../common/fmcjesdadc1_qsys.tcl
 
-set_instance_parameter_value avl_ad9250_xcvr {SYSCLK_FREQUENCY} {50.0}
 

From 14ded4f123409f15716e1342eca218f9323752f4 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 22 Dec 2016 15:59:45 -0500
Subject: [PATCH 837/972] fmcjeadadc1/a5soc- ad_sysref_gen updates

---
 projects/fmcjesdadc1/a5soc/system_constr.sdc  | 2 +-
 projects/fmcjesdadc1/a5soc/system_project.tcl | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/fmcjesdadc1/a5soc/system_constr.sdc b/projects/fmcjesdadc1/a5soc/system_constr.sdc
index cc0a871d7..e2cc1a715 100644
--- a/projects/fmcjesdadc1/a5soc/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5soc/system_constr.sdc
@@ -6,7 +6,7 @@ create_clock -period "10.000 ns" -name sys_dma_clk [get_pins {i_system_bd|sys_hp
 derive_pll_clocks
 derive_clock_uncertainty
 
-set_false_path -to [get_registers {rx_sysref_m1}]
+set_false_path -to [get_registers *sysref_en_m1*]
 
 set_false_path -from [get_clocks {sys_cpu_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\
   -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
diff --git a/projects/fmcjesdadc1/a5soc/system_project.tcl b/projects/fmcjesdadc1/a5soc/system_project.tcl
index ad17a1013..015be89c1 100755
--- a/projects/fmcjesdadc1/a5soc/system_project.tcl
+++ b/projects/fmcjesdadc1/a5soc/system_project.tcl
@@ -61,8 +61,8 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
 
 # disable auto-pack
 
-set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
-set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
+set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity ad_sysref_gen
+set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity ad_sysref_gen
 
 execute_flow -compile
 

From e4e5b30ade2371cd1d59eca0368c81d11b7922f0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 3 Jan 2017 13:52:39 +0200
Subject: [PATCH 838/972] fmcadc5: Integrate ad_sysref_gen into the project

---
 projects/fmcadc5/vc707/Makefile           |  1 +
 projects/fmcadc5/vc707/system_constr.xdc  |  4 +++-
 projects/fmcadc5/vc707/system_project.tcl |  1 +
 projects/fmcadc5/vc707/system_top.v       | 13 +++++--------
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile
index 578fb5cca..99f2911e2 100644
--- a/projects/fmcadc5/vc707/Makefile
+++ b/projects/fmcadc5/vc707/Makefile
@@ -21,6 +21,7 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
 M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
diff --git a/projects/fmcadc5/vc707/system_constr.xdc b/projects/fmcadc5/vc707/system_constr.xdc
index f87e54d99..7bdafaed4 100644
--- a/projects/fmcadc5/vc707/system_constr.xdc
+++ b/projects/fmcadc5/vc707/system_constr.xdc
@@ -87,5 +87,7 @@ create_clock -name rx_ref_clk_1   -period  1.60 [get_ports rx_ref_clk_1_p]
 create_clock -name rx_div_clk     -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcadc5_0_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from  [get_cells i_system_wrapper/system_i/axi_ad9625_0_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
-set_false_path -to    [get_cells rx_sysref_m1_reg]
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
+set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]
 
diff --git a/projects/fmcadc5/vc707/system_project.tcl b/projects/fmcadc5/vc707/system_project.tcl
index a1436b06d..fddee061b 100644
--- a/projects/fmcadc5/vc707/system_project.tcl
+++ b/projects/fmcadc5/vc707/system_project.tcl
@@ -10,6 +10,7 @@ adi_project_files fmcadc5_vc707 [list \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_sysref_gen.v" \
   "../common/fmcadc5_spi.v" \
   "../common/fmcadc5_psync.v" \
   "system_constr.xdc"\
diff --git a/projects/fmcadc5/vc707/system_top.v b/projects/fmcadc5/vc707/system_top.v
index 2215146c4..0a2d6bcb5 100644
--- a/projects/fmcadc5/vc707/system_top.v
+++ b/projects/fmcadc5/vc707/system_top.v
@@ -138,9 +138,6 @@ module system_top (
 
   reg     [  4:0]   gpio_o_60_56_d = 'd0;
   reg               gpio_dld = 'd0;
-  reg               rx_sysref_m1 = 'd0;
-  reg               rx_sysref_m2 = 'd0;
-  reg               rx_sysref_int = 'd0;
 
   // internal signals
 
@@ -160,6 +157,7 @@ module system_top (
   wire              rx_sync_1;
   wire              up_rstn;
   wire              up_clk;
+  wire              rx_sysref_int;
 
   // spi
 
@@ -194,11 +192,10 @@ module system_top (
 
   // sysref internal
 
-  always @(posedge rx_clk) begin
-    rx_sysref_m1 <= gpio_o[32];
-    rx_sysref_m2 <= rx_sysref_m1;
-    rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
-  end
+  ad_sysref_gen i_sysref (
+    .core_clk (rx_clk),
+    .sysref_en (gpio_o[32]),
+    .sysref_out (rx_sysref_int));
 
   // instantiations
 

From 8b74e911b8c69ecfd63d63219d8867bac53e96db Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 Jan 2017 14:10:44 -0500
Subject: [PATCH 839/972] fmcjesdadc1/a5gt- qr to ddio max delay

---
 projects/fmcjesdadc1/a5gt/system_constr.sdc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc
index f6da22797..9d7fdd72a 100644
--- a/projects/fmcjesdadc1/a5gt/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc
@@ -25,3 +25,6 @@ set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPU
 set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
   -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
 
+set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \
+  -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 2
+

From 37d54bb984b29acec38fd2fff9f40aea10ab2423 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 4 Jan 2017 16:04:19 -0500
Subject: [PATCH 840/972] fmcjesdadc1/a5gt- max delay fit only

---
 projects/fmcjesdadc1/a5gt/system_constr.sdc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc
index 9d7fdd72a..b4216038d 100644
--- a/projects/fmcjesdadc1/a5gt/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc
@@ -25,6 +25,8 @@ set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPU
 set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
   -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
 
-set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \
-  -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 2
+if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} {
+  set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \
+    -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 2
+}
 

From 9b29941c77d8cf9fe5c077d250d0fcbed67393a6 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 11 Jan 2017 18:11:53 +0200
Subject: [PATCH 841/972] util_clkdiv: Add constraint file

---
 library/util_clkdiv/util_clkdiv.v          | 4 ++--
 library/util_clkdiv/util_clkdiv_constr.xdc | 1 +
 library/util_clkdiv/util_clkdiv_ip.tcl     | 6 +++++-
 3 files changed, 8 insertions(+), 3 deletions(-)
 create mode 100644 library/util_clkdiv/util_clkdiv_constr.xdc

diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v
index ee20fdb9f..e55399bef 100644
--- a/library/util_clkdiv/util_clkdiv.v
+++ b/library/util_clkdiv/util_clkdiv.v
@@ -34,8 +34,8 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1 using
-// BUFR and BUFGMUX primitives
+// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1
+// IP uses BUFR and BUFGMUX primitives
 // ***************************************************************************
 // ***************************************************************************
 
diff --git a/library/util_clkdiv/util_clkdiv_constr.xdc b/library/util_clkdiv/util_clkdiv_constr.xdc
new file mode 100644
index 000000000..d7713e6a0
--- /dev/null
+++ b/library/util_clkdiv/util_clkdiv_constr.xdc
@@ -0,0 +1 @@
+set_clock_groups -group [get_clocks clk_div_4_s] -group [get_clocks clk_div_2_s] -logically_exclusive
diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl
index 701ca5c96..20f2d1395 100644
--- a/library/util_clkdiv/util_clkdiv_ip.tcl
+++ b/library/util_clkdiv/util_clkdiv_ip.tcl
@@ -3,10 +3,14 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create util_clkdiv
 adi_ip_files util_clkdiv [list \
-"util_clkdiv.v" ]
+  "util_clkdiv_constr.xdc" \
+  "util_clkdiv.v" ]
 
 adi_ip_properties_lite util_clkdiv
 
+adi_ip_constraints util_clkdiv [list \
+  "util_clkdiv_constr.xdc" ]
+
 set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]

From e77428c50e4ac7e6ec3887788f09eb0c9dabba5a Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 11 Jan 2017 18:12:35 +0200
Subject: [PATCH 842/972] fmcomms2: Added FIFOs for DAC and ADC paths so that
 the path works at l_clk / 2 or l_clk /4

- removed ILA
---
 projects/fmcomms2/common/fmcomms2_bd.tcl | 208 ++++++++++++-----------
 1 file changed, 108 insertions(+), 100 deletions(-)

diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl
index 2dbf3d04e..f7e7cb8d9 100644
--- a/projects/fmcomms2/common/fmcomms2_bd.tcl
+++ b/projects/fmcomms2/common/fmcomms2_bd.tcl
@@ -66,88 +66,116 @@ set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
 set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
 set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
 
+set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
+
+set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
+
+set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
+set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
+set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
+set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
+
 # connections
 
-ad_connect  sys_200m_clk axi_ad9361/delay_clk
-ad_connect  axi_ad9361_clk axi_ad9361/l_clk
-ad_connect  axi_ad9361_clk axi_ad9361/clk
-ad_connect  rx_clk_in_p axi_ad9361/rx_clk_in_p
-ad_connect  rx_clk_in_n axi_ad9361/rx_clk_in_n
-ad_connect  rx_frame_in_p axi_ad9361/rx_frame_in_p
-ad_connect  rx_frame_in_n axi_ad9361/rx_frame_in_n
-ad_connect  rx_data_in_p axi_ad9361/rx_data_in_p
-ad_connect  rx_data_in_n axi_ad9361/rx_data_in_n
-ad_connect  tx_clk_out_p axi_ad9361/tx_clk_out_p
-ad_connect  tx_clk_out_n axi_ad9361/tx_clk_out_n
-ad_connect  tx_frame_out_p axi_ad9361/tx_frame_out_p
-ad_connect  tx_frame_out_n axi_ad9361/tx_frame_out_n
-ad_connect  tx_data_out_p axi_ad9361/tx_data_out_p
-ad_connect  tx_data_out_n axi_ad9361/tx_data_out_n
-ad_connect  enable axi_ad9361/enable
-ad_connect  txnrx axi_ad9361/txnrx
-ad_connect  up_enable axi_ad9361/up_enable
-ad_connect  up_txnrx axi_ad9361/up_txnrx
-ad_connect  axi_ad9361_clk util_ad9361_adc_fifo/din_clk
-ad_connect  axi_ad9361/rst util_ad9361_adc_fifo/din_rst
-ad_connect  sys_cpu_clk util_ad9361_adc_fifo/dout_clk
-ad_connect  sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
-ad_connect  sys_cpu_clk util_ad9361_adc_pack/adc_clk
-ad_connect  sys_cpu_reset util_ad9361_adc_pack/adc_rst
-ad_connect  sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
-ad_connect  axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
-ad_connect  axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
-ad_connect  axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
-ad_connect  axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
-ad_connect  axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
-ad_connect  axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
-ad_connect  axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
-ad_connect  axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
-ad_connect  axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
-ad_connect  axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
-ad_connect  axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
-ad_connect  axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
-ad_connect  util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
-ad_connect  util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
-ad_connect  util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
-ad_connect  util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
-ad_connect  util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
-ad_connect  util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
-ad_connect  util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
-ad_connect  util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
-ad_connect  util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
-ad_connect  util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
-ad_connect  util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
-ad_connect  util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
-ad_connect  util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
-ad_connect  util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
-ad_connect  util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
-ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
-ad_connect  util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
-ad_connect  axi_ad9361_clk util_ad9361_dac_upack/dac_clk
-ad_connect  axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
-ad_connect  util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
-ad_connect  util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
-ad_connect  util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
-ad_connect  util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
-ad_connect  util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
-ad_connect  util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
-ad_connect  util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
-ad_connect  util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
-ad_connect  util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
-ad_connect  util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
-ad_connect  util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
-ad_connect  util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
-ad_connect  util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
-ad_connect  util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
-ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
-
-ad_connect  sys_cpu_clk util_ad9361_tdd_sync/clk
-ad_connect  sys_cpu_resetn util_ad9361_tdd_sync/rstn
-ad_connect  util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
-ad_connect  util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
-ad_connect  tdd_sync_t axi_ad9361/tdd_sync_cntr
-ad_connect  tdd_sync_o util_ad9361_tdd_sync/sync_out
-ad_connect  tdd_sync_i util_ad9361_tdd_sync/sync_in
+ad_connect sys_200m_clk axi_ad9361/delay_clk
+ad_connect axi_ad9361_clk axi_ad9361/l_clk
+ad_connect axi_ad9361_clk axi_ad9361/clk
+ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
+ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
+ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
+ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
+ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
+ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
+ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
+ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
+ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
+ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
+ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
+ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
+ad_connect enable axi_ad9361/enable
+ad_connect txnrx axi_ad9361/txnrx
+ad_connect up_enable axi_ad9361/up_enable
+ad_connect up_txnrx axi_ad9361/up_txnrx
+ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
+ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
+ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
+ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
+ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
+ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
+ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
+ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
+ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
+ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
+ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
+ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
+ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
+ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
+ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
+ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
+ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
+ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
+ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
+ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
+ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
+ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
+ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
+ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
+ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
+ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
+ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
+ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
+ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
+ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
+ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
+ad_connect axi_ad9361_clk clkdiv/clk
+ad_connect axi_ad9361/adc_r1_mode clkdiv/clk_sel
+ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
+ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk
+ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
+ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out
+ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset
+ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn
+ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
+ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
+ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
+ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf
+ad_connect dac_fifo/din_clk clkdiv/clk_out
+ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn
+ad_connect axi_ad9361_clk dac_fifo/dout_clk
+ad_connect dac_fifo/dout_rst axi_ad9361/rst
+ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out
+ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0
+ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0
+ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1
+ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1
+ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2
+ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2
+ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3
+ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3
+ad_connect util_ad9361_dac_upack/dac_data_0 dac_fifo/din_data_0
+ad_connect util_ad9361_dac_upack/dac_data_1 dac_fifo/din_data_1
+ad_connect util_ad9361_dac_upack/dac_data_2 dac_fifo/din_data_2
+ad_connect util_ad9361_dac_upack/dac_data_3 dac_fifo/din_data_3
+ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0
+ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0
+ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1
+ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1
+ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2
+ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2
+ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3
+ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3
+ad_connect dac_fifo/dout_data_0 axi_ad9361/dac_data_i0
+ad_connect dac_fifo/dout_data_1 axi_ad9361/dac_data_q0
+ad_connect dac_fifo/dout_data_2 axi_ad9361/dac_data_i1
+ad_connect dac_fifo/dout_data_3 axi_ad9361/dac_data_q1
+ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
+ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
+ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
+ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
+ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr
+ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
+ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in
 
 # interconnects
 
@@ -166,23 +194,3 @@ ad_connect  sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
 ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq
 ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
 
-# ila (adc)
-
-set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
-set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
-set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
-set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_adc
-
-ad_connect  util_ad9361_adc_fifo/dout_data_0 ila_adc/probe0
-ad_connect  util_ad9361_adc_fifo/dout_data_1 ila_adc/probe1
-ad_connect  util_ad9361_adc_fifo/dout_data_2 ila_adc/probe2
-ad_connect  util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3
-ad_connect  util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4
-ad_connect  sys_cpu_clk ila_adc/clk
-

From b59549053c9212adba1384dd8cf2245c622d7c52 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 12 Jan 2017 12:15:33 +0200
Subject: [PATCH 843/972] scripts/adi_ip: Fix adi_ip_infer_interfaces process

This patch is a complementary fix of 8b8c37 patch. And fix
all the 'infer interface' issues.

The adi_ip_infer_interfaces process was renamed to
adi_ip_infer_streaming_interfaces. Now the process just do
what its name suggest.

Affected cores were axi_dmac, axi_spdif_rx, axi_spdif_tx, axi_i2s_adi
and axi_usb_fx3. All these cores scripts were updated.
---
 library/axi_dmac/axi_dmac_ip.tcl         | 2 +-
 library/axi_i2s_adi/axi_i2s_adi_ip.tcl   | 2 +-
 library/axi_spdif_rx/axi_spdif_rx_ip.tcl | 2 +-
 library/axi_spdif_tx/axi_spdif_tx_ip.tcl | 2 +-
 library/axi_usb_fx3/axi_usb_fx3_ip.tcl   | 2 +-
 library/scripts/adi_ip.tcl               | 5 ++---
 6 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl
index 293a6b7a8..877994bd4 100644
--- a/library/axi_dmac/axi_dmac_ip.tcl
+++ b/library/axi_dmac/axi_dmac_ip.tcl
@@ -27,7 +27,7 @@ adi_ip_files axi_dmac [list \
   "bd/bd.tcl" ]
 
 adi_ip_properties axi_dmac
-adi_ip_infer_interfaces axi_dmac
+adi_ip_infer_streaming_interfaces axi_dmac
 adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl"
 adi_ip_bd axi_dmac "bd/bd.tcl"
 
diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
index bc6dedcde..c5b1ae36c 100644
--- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
+++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl
@@ -20,7 +20,7 @@ adi_ip_files axi_i2s_adi [list \
 ]
 
 adi_ip_properties axi_i2s_adi
-adi_ip_infer_interfaces axi_i2s_adi
+adi_ip_infer_streaming_interfaces axi_i2s_adi
 adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late
 
 adi_add_bus "DMA_ACK_RX" "slave" \
diff --git a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl
index ad44ef4ef..c82d1ae97 100644
--- a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl
+++ b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl
@@ -17,7 +17,7 @@ adi_ip_files axi_spdif_rx [list \
   "axi_spdif_rx_constr.xdc"]
 
 adi_ip_properties axi_spdif_rx
-adi_ip_infer_interfaces axi_spdif_rx
+adi_ip_infer_streaming_interfaces axi_spdif_rx
 adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc
 
 adi_add_bus "DMA_ACK" "slave" \
diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl
index eece3075d..6f87d0d5f 100644
--- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl
+++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl
@@ -15,7 +15,7 @@ adi_ip_files axi_spdif_tx [list \
   "axi_spdif_tx_constr.xdc" ]
 
 adi_ip_properties axi_spdif_tx
-adi_ip_infer_interfaces axi_spdif_tx
+adi_ip_infer_streaming_interfaces axi_spdif_tx
 adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc
 
 adi_add_bus "DMA_ACK" "slave" \
diff --git a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
index d7d0d1633..58dcad9f8 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
+++ b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
@@ -12,7 +12,7 @@ adi_ip_files axi_usb_fx3 [list \
   "axi_usb_fx3.v"]
 
 adi_ip_properties axi_usb_fx3
-adi_ip_infer_interfaces axi_usb_fx3
+adi_ip_infer_streaming_interfaces axi_usb_fx3
 
 adi_add_bus_clock "s_axi_aclk" "s_axis"
 adi_add_bus_clock "s_axi_aclk" "m_axis"
diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl
index 6583736ff..a125b8fb4 100644
--- a/library/scripts/adi_ip.tcl
+++ b/library/scripts/adi_ip.tcl
@@ -120,11 +120,10 @@ proc adi_ip_properties {ip_name} {
     -of_objects [ipx::current_core]]]
 }
 
-proc adi_ip_infer_interfaces {ip_name} {
+proc adi_ip_infer_streaming_interfaces {ip_name} {
 
-  ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
-  ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
   ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
+
 }
 
 proc adi_ip_properties_lite {ip_name} {

From 1f7d19688afd981b8867c1c50185c304297a79f5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 12 Jan 2017 15:58:32 +0200
Subject: [PATCH 844/972] Update Makefile

---
 library/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/library/Makefile b/library/Makefile
index 56f1feac7..7b6ae54d3 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -63,7 +63,6 @@ clean:
 	make -C util_fir_dec clean
 	make -C util_fir_int clean
 	make -C util_gmii_to_rgmii clean
-	make -C util_gtlb clean
 	make -C util_i2c_mixer clean
 	make -C util_jesd_gt clean
 	make -C util_mfifo clean

From f003b5b35a1a96f884b3f7c86d8df5f9ac5d7a2a Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 12 Jan 2017 16:10:45 +0200
Subject: [PATCH 845/972] fmcjesdadc1: Reduce SYSREF period

---
 projects/fmcjesdadc1/a5gt/system_top.v  | 2 +-
 projects/fmcjesdadc1/a5soc/system_top.v | 2 +-
 projects/fmcjesdadc1/kc705/system_top.v | 2 +-
 projects/fmcjesdadc1/vc707/system_top.v | 2 +-
 projects/fmcjesdadc1/zc706/system_top.v | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/projects/fmcjesdadc1/a5gt/system_top.v b/projects/fmcjesdadc1/a5gt/system_top.v
index 7591642c5..f19bf1b10 100644
--- a/projects/fmcjesdadc1/a5gt/system_top.v
+++ b/projects/fmcjesdadc1/a5gt/system_top.v
@@ -148,7 +148,7 @@ module system_top (
 
   // sysref
 
-  ad_sysref_gen i_sysref (
+  ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref (
     .core_clk (rx_clk),
     .sysref_en (gpio_o[32]),
     .sysref_out (rx_sysref));
diff --git a/projects/fmcjesdadc1/a5soc/system_top.v b/projects/fmcjesdadc1/a5soc/system_top.v
index 94b6fb987..2520c8e36 100644
--- a/projects/fmcjesdadc1/a5soc/system_top.v
+++ b/projects/fmcjesdadc1/a5soc/system_top.v
@@ -150,7 +150,7 @@ module system_top (
 
   // sysref
 
-  ad_sysref_gen i_sysref (
+  ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref (
     .core_clk (rx_clk),
     .sysref_en (gpio_o[32]),
     .sysref_out (rx_sysref));
diff --git a/projects/fmcjesdadc1/kc705/system_top.v b/projects/fmcjesdadc1/kc705/system_top.v
index c45511b45..60fd19c76 100644
--- a/projects/fmcjesdadc1/kc705/system_top.v
+++ b/projects/fmcjesdadc1/kc705/system_top.v
@@ -211,7 +211,7 @@ module system_top (
     .spi_miso (spi_miso),
     .spi_sdio (spi_sdio));
 
-  ad_sysref_gen i_sysref (
+  ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref (
     .core_clk (rx_clk),
     .sysref_en (gpio_o[32]),
     .sysref_out (rx_sysref));
diff --git a/projects/fmcjesdadc1/vc707/system_top.v b/projects/fmcjesdadc1/vc707/system_top.v
index d8a30cfbe..5fabc10d3 100644
--- a/projects/fmcjesdadc1/vc707/system_top.v
+++ b/projects/fmcjesdadc1/vc707/system_top.v
@@ -205,7 +205,7 @@ module system_top (
     .spi_miso (spi_miso),
     .spi_sdio (spi_sdio));
 
-  ad_sysref_gen i_sysref (
+  ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref (
     .core_clk (rx_clk),
     .sysref_en (gpio_o[32]),
     .sysref_out (rx_sysref));
diff --git a/projects/fmcjesdadc1/zc706/system_top.v b/projects/fmcjesdadc1/zc706/system_top.v
index 82d1a5cef..d41fc4b96 100644
--- a/projects/fmcjesdadc1/zc706/system_top.v
+++ b/projects/fmcjesdadc1/zc706/system_top.v
@@ -182,7 +182,7 @@ module system_top (
     .spi_miso (spi_miso),
     .spi_sdio (spi_sdio));
 
-  ad_sysref_gen i_sysref (
+  ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref (
     .core_clk (rx_clk),
     .sysref_en (gpio_o[32]),
     .sysref_out (rx_sysref));

From 4b2602437f762fa7af56e4881b131540ca7df9bf Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 13 Jan 2017 13:54:07 +0200
Subject: [PATCH 846/972] util_clkdiv: Added Ultrascale support and switch to
 BUFGMUX_CTRL for glitch free switching

---
 library/util_clkdiv/util_clkdiv.v          | 29 ++++++++++++++++++++--
 library/util_clkdiv/util_clkdiv_constr.xdc |  1 +
 library/util_clkdiv/util_clkdiv_ip.tcl     |  3 +++
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v
index e55399bef..e85fd41ed 100644
--- a/library/util_clkdiv/util_clkdiv.v
+++ b/library/util_clkdiv/util_clkdiv.v
@@ -35,7 +35,8 @@
 // ***************************************************************************
 // ***************************************************************************
 // Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1
-// IP uses BUFR and BUFGMUX primitives
+// IP uses BUFR and BUFGMUX_CTRL primitive
+// IP provides a glitch free output clock
 // ***************************************************************************
 // ***************************************************************************
 
@@ -47,9 +48,13 @@ module util_clkdiv (
   output  clk_out
  );
 
+parameter C_SIM_DEVICE = "7SERIES";
+
   wire clk_div_2_s;
   wire clk_div_4_s;
 
+generate if (C_SIM_DEVICE == "7SERIES") begin
+
   BUFR #(
     .BUFR_DIVIDE("2"),
     .SIM_DEVICE("7SERIES")
@@ -68,7 +73,27 @@ module util_clkdiv (
     .CLR(0),
     .O(clk_div_4_s));
 
-  BUFGMUX i_div_clk_gbuf (
+end else if (C_SIM_DEVICE == "ULTRASCALE") begin
+
+  BUFGCE_DIV #(
+    .BUFGCE_DIVIDE("2")
+  ) clk_divide_2 (
+    .I(clk),
+    .CE(1),
+    .CLR(0),
+    .O(clk_div_2_s));
+
+  BUFGCE_DIV #(
+    .BUFGCE_DIVIDE("4")
+  ) clk_divide_4 (
+    .I(clk),
+    .CE(1),
+    .CLR(0),
+    .O(clk_div_4_s));
+
+end endgenerate
+
+  BUFGMUX_CTRL i_div_clk_gbuf (
     .I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
     .I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
     .S(clk_sel),
diff --git a/library/util_clkdiv/util_clkdiv_constr.xdc b/library/util_clkdiv/util_clkdiv_constr.xdc
index d7713e6a0..a988c4d6b 100644
--- a/library/util_clkdiv/util_clkdiv_constr.xdc
+++ b/library/util_clkdiv/util_clkdiv_constr.xdc
@@ -1 +1,2 @@
 set_clock_groups -group [get_clocks clk_div_4_s] -group [get_clocks clk_div_2_s] -logically_exclusive
+set_false_path -to [get_pins i_div_clk_gbuf/S*]
diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl
index 20f2d1395..f3e370a5f 100644
--- a/library/util_clkdiv/util_clkdiv_ip.tcl
+++ b/library/util_clkdiv/util_clkdiv_ip.tcl
@@ -13,4 +13,7 @@ adi_ip_constraints util_clkdiv [list \
 
 set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
 
+set_property value_validation_type list [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
+set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]

From b84325d43f4960468cd8bc0dd091d536772fbd29 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 13 Jan 2017 13:56:04 +0200
Subject: [PATCH 847/972] fmcomms2: take into consideration both adc_r1 and
 dac_r1 for clock division selection

---
 projects/fmcomms2/common/fmcomms2_bd.tcl | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl
index f7e7cb8d9..bfecb54ad 100644
--- a/projects/fmcomms2/common/fmcomms2_bd.tcl
+++ b/projects/fmcomms2/common/fmcomms2_bd.tcl
@@ -75,6 +75,12 @@ set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
 set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
 set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
 
+set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
+set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic
+
+set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
+set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic
+
 # connections
 
 ad_connect sys_200m_clk axi_ad9361/delay_clk
@@ -128,7 +134,12 @@ ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
 ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
 ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
 ad_connect axi_ad9361_clk clkdiv/clk
-ad_connect axi_ad9361/adc_r1_mode clkdiv/clk_sel
+
+ad_connect axi_ad9361/adc_r1_mode concat_logic/In0
+ad_connect axi_ad9361/dac_r1_mode concat_logic/In1
+ad_connect concat_logic/dout clkdiv_sel_logic/Op1
+ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res
+
 ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
 ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
 ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk

From 15c5bc7012c26d21b876c77a5cded10c8258fe32 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 13 Jan 2017 13:57:32 +0200
Subject: [PATCH 848/972] fmcomms2: zcu102, changed clkdiv C_SIM_DEVICE
 parameter to ultrascale

---
 projects/fmcomms2/zcu102/system_bd.tcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/projects/fmcomms2/zcu102/system_bd.tcl b/projects/fmcomms2/zcu102/system_bd.tcl
index c5e28355f..515600a7e 100755
--- a/projects/fmcomms2/zcu102/system_bd.tcl
+++ b/projects/fmcomms2/zcu102/system_bd.tcl
@@ -2,5 +2,7 @@
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
 source ../common/fmcomms2_bd.tcl
 
+set_property -dict [list CONFIG.C_SIM_DEVICE {ULTRASCALE}] $clkdiv
+
 set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361]
 

From a36057679a6c4b5c7075224f41785f68e9e97233 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 13 Jan 2017 14:16:21 +0200
Subject: [PATCH 849/972] fmcomms2: Update Makefiles

---
 projects/fmcomms2/ac701/Makefile   | 6 ++++++
 projects/fmcomms2/kc705/Makefile   | 6 ++++++
 projects/fmcomms2/mitx045/Makefile | 6 ++++++
 projects/fmcomms2/vc707/Makefile   | 6 ++++++
 projects/fmcomms2/zc702/Makefile   | 6 ++++++
 projects/fmcomms2/zc706/Makefile   | 6 ++++++
 projects/fmcomms2/zc706pr/Makefile | 6 ++++++
 projects/fmcomms2/zcu102/Makefile  | 6 ++++++
 projects/fmcomms2/zed/Makefile     | 6 ++++++
 9 files changed, 54 insertions(+)

diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile
index ce1b2c52f..7c6e6a2fd 100644
--- a/projects/fmcomms2/ac701/Makefile
+++ b/projects/fmcomms2/ac701/Makefile
@@ -20,7 +20,9 @@ M_DEPS += ../../common/ac701/ac701_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -54,7 +56,9 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -68,7 +72,9 @@ fmcomms2_ac701.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile
index d3f85e133..4e9485043 100644
--- a/projects/fmcomms2/kc705/Makefile
+++ b/projects/fmcomms2/kc705/Makefile
@@ -20,7 +20,9 @@ M_DEPS += ../../common/kc705/kc705_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -54,7 +56,9 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -68,7 +72,9 @@ fmcomms2_kc705.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile
index 83e16785d..c946394d1 100644
--- a/projects/fmcomms2/mitx045/Makefile
+++ b/projects/fmcomms2/mitx045/Makefile
@@ -24,7 +24,9 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -62,7 +64,9 @@ clean-all:clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_i2s_adi clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -80,7 +84,9 @@ lib:
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_i2s_adi
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile
index 2bba9ecfc..85de2aff5 100644
--- a/projects/fmcomms2/vc707/Makefile
+++ b/projects/fmcomms2/vc707/Makefile
@@ -19,7 +19,9 @@ M_DEPS += ../../common/vc707/vc707_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -53,7 +55,9 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -67,7 +71,9 @@ fmcomms2_vc707.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile
index bb60b6d34..4bc0b073d 100644
--- a/projects/fmcomms2/zc702/Makefile
+++ b/projects/fmcomms2/zc702/Makefile
@@ -22,7 +22,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -59,7 +61,9 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -76,7 +80,9 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile
index 5a761936c..0c6fab01c 100644
--- a/projects/fmcomms2/zc706/Makefile
+++ b/projects/fmcomms2/zc706/Makefile
@@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -58,7 +60,9 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -75,7 +79,9 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/fmcomms2/zc706pr/Makefile b/projects/fmcomms2/zc706pr/Makefile
index c88d9906c..f4d14bac4 100644
--- a/projects/fmcomms2/zc706pr/Makefile
+++ b/projects/fmcomms2/zc706pr/Makefile
@@ -43,7 +43,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -80,7 +82,9 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -97,7 +101,9 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/fmcomms2/zcu102/Makefile b/projects/fmcomms2/zcu102/Makefile
index 96db5feba..ffbf73b78 100644
--- a/projects/fmcomms2/zcu102/Makefile
+++ b/projects/fmcomms2/zcu102/Makefile
@@ -18,7 +18,9 @@ M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -52,7 +54,9 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -66,7 +70,9 @@ fmcomms2_zcu102.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile
index 15b95124a..c6cca6d96 100644
--- a/projects/fmcomms2/zed/Makefile
+++ b/projects/fmcomms2/zed/Makefile
@@ -23,8 +23,10 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
 M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -62,8 +64,10 @@ clean-all:clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_i2s_adi clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
 	make -C ../../../library/util_i2c_mixer clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -81,8 +85,10 @@ lib:
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_i2s_adi
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
 	make -C ../../../library/util_i2c_mixer
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo

From d2e7b6b635f95e4fa91908f5b6f370c4480c8bcc Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 13 Jan 2017 14:18:59 +0200
Subject: [PATCH 850/972] fmcomms5: Added FIFOs for DAC and ADC paths so that
 they work at l_clk/2 or l_clk/4

---
 projects/fmcomms5/common/fmcomms5_bd.tcl | 257 ++++++++++++++---------
 projects/fmcomms5/zc702/Makefile         |   6 +
 projects/fmcomms5/zc706/Makefile         |   6 +
 3 files changed, 169 insertions(+), 100 deletions(-)

diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl
index 9c05875cb..0e0b3fb84 100644
--- a/projects/fmcomms5/common/fmcomms5_bd.tcl
+++ b/projects/fmcomms5/common/fmcomms5_bd.tcl
@@ -99,60 +99,89 @@ set_property -dict [list CONFIG.DIN_DATA_WIDTH {16} ] $adc_wfifo
 set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16} ] $adc_wfifo
 set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $adc_wfifo
 
+set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
+
+set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
+
+set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
+set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
+set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
+set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] $dac_fifo
+
+set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
+set_property -dict [list CONFIG.C_SIZE {4}] $clkdiv_sel_logic
+
+set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
+set_property -dict [list CONFIG.NUM_PORTS {4}] $concat_logic
+
 # connections (ad9361)
 
-ad_connect sys_200m_clk     axi_ad9361_0/delay_clk
-ad_connect sys_200m_clk     axi_ad9361_1/delay_clk
-ad_connect axi_ad9361_0_clk axi_ad9361_0/l_clk
-ad_connect axi_ad9361_1_clk axi_ad9361_1/l_clk
-ad_connect axi_ad9361_0_clk axi_ad9361_0/clk
-ad_connect axi_ad9361_0_clk axi_ad9361_1/clk
-ad_connect axi_ad9361_0/rst adc_wfifo/din_rst
-ad_connect axi_ad9361_0_clk adc_wfifo/din_clk
-ad_connect sys_cpu_clk      adc_wfifo/dout_clk
-ad_connect sys_cpu_resetn   adc_wfifo/dout_rstn
-ad_connect sys_cpu_clk      util_cpack_adc/adc_clk
-ad_connect sys_cpu_clk      axi_ad9361_adc_dma/fifo_wr_clk
-ad_connect axi_ad9361_0_clk util_upack_dac/dac_clk
-ad_connect axi_ad9361_0_clk axi_ad9361_dac_dma/fifo_rd_clk
-ad_connect sys_cpu_resetn   sys_100m_resetn
-ad_connect sys_cpu_resetn   axi_ad9361_adc_dma/m_dest_axi_aresetn
-ad_connect sys_cpu_resetn   axi_ad9361_dac_dma/m_src_axi_aresetn
-ad_connect sys_cpu_reset    util_cpack_adc/adc_rst
+ad_connect  sys_200m_clk      axi_ad9361_0/delay_clk
+ad_connect  sys_200m_clk      axi_ad9361_1/delay_clk
+ad_connect  axi_ad9361_0_clk  axi_ad9361_0/l_clk
+ad_connect  axi_ad9361_1_clk  axi_ad9361_1/l_clk
+ad_connect  axi_ad9361_0_clk  axi_ad9361_0/clk
+ad_connect  axi_ad9361_0_clk  axi_ad9361_1/clk
+ad_connect  axi_ad9361_0_clk  adc_wfifo/din_clk
+ad_connect  axi_ad9361_0_clk  clkdiv/clk
+ad_connect  axi_ad9361_0_clk  dac_fifo/dout_clk
+ad_connect  axi_ad9361_0/rst  adc_wfifo/din_rst
+ad_connect  axi_ad9361_0/rst  dac_fifo/dout_rst
+ad_connect  clkdiv/clk_out    axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  clkdiv/clk_out    adc_wfifo/dout_clk
+ad_connect  clkdiv/clk_out    util_cpack_adc/adc_clk
+ad_connect  clkdiv/clk_out    axi_ad9361_dac_dma/fifo_rd_clk
+ad_connect  clkdiv/clk_out    dac_fifo/din_clk
+ad_connect  clkdiv/clk_out    clkdiv_reset/slowest_sync_clk
+ad_connect  clkdiv/clk_out    util_upack_dac/dac_clk
 
+ad_connect  sys_cpu_resetn    sys_100m_resetn
+ad_connect  sys_cpu_resetn    axi_ad9361_adc_dma/m_dest_axi_aresetn
+ad_connect  sys_cpu_resetn    axi_ad9361_dac_dma/m_src_axi_aresetn
+ad_connect  clkdiv_reset/ext_reset_in       sys_rstgen/peripheral_aresetn
+ad_connect  clkdiv_reset/peripheral_reset   util_cpack_adc/adc_rst
+ad_connect  clkdiv_reset/peripheral_aresetn dac_fifo/din_rstn
+ad_connect  clkdiv_reset/peripheral_aresetn adc_wfifo/dout_rstn
 
-ad_connect  axi_ad9361_0_dac_sync   axi_ad9361_0/dac_sync_out
-ad_connect  axi_ad9361_0_dac_sync   axi_ad9361_0/dac_sync_in
-ad_connect  axi_ad9361_0_dac_sync   axi_ad9361_1/dac_sync_in
+ad_connect  axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_out
+ad_connect  axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_in
+ad_connect  axi_ad9361_0_dac_sync axi_ad9361_1/dac_sync_in
 
-ad_connect  rx_clk_in_0_p               axi_ad9361_0/rx_clk_in_p
-ad_connect  rx_clk_in_0_n               axi_ad9361_0/rx_clk_in_n
-ad_connect  rx_frame_in_0_p             axi_ad9361_0/rx_frame_in_p
-ad_connect  rx_frame_in_0_n             axi_ad9361_0/rx_frame_in_n
-ad_connect  rx_data_in_0_p              axi_ad9361_0/rx_data_in_p
-ad_connect  rx_data_in_0_n              axi_ad9361_0/rx_data_in_n
-ad_connect  tx_clk_out_0_p              axi_ad9361_0/tx_clk_out_p
-ad_connect  tx_clk_out_0_n              axi_ad9361_0/tx_clk_out_n
-ad_connect  tx_frame_out_0_p            axi_ad9361_0/tx_frame_out_p
-ad_connect  tx_frame_out_0_n            axi_ad9361_0/tx_frame_out_n
-ad_connect  tx_data_out_0_p             axi_ad9361_0/tx_data_out_p
-ad_connect  tx_data_out_0_n             axi_ad9361_0/tx_data_out_n
-ad_connect  rx_clk_in_1_p               axi_ad9361_1/rx_clk_in_p
-ad_connect  rx_clk_in_1_n               axi_ad9361_1/rx_clk_in_n
-ad_connect  rx_frame_in_1_p             axi_ad9361_1/rx_frame_in_p
-ad_connect  rx_frame_in_1_n             axi_ad9361_1/rx_frame_in_n
-ad_connect  rx_data_in_1_p              axi_ad9361_1/rx_data_in_p
-ad_connect  rx_data_in_1_n              axi_ad9361_1/rx_data_in_n
-ad_connect  tx_clk_out_1_p              axi_ad9361_1/tx_clk_out_p
-ad_connect  tx_clk_out_1_n              axi_ad9361_1/tx_clk_out_n
-ad_connect  tx_frame_out_1_p            axi_ad9361_1/tx_frame_out_p
-ad_connect  tx_frame_out_1_n            axi_ad9361_1/tx_frame_out_n
-ad_connect  tx_data_out_1_p             axi_ad9361_1/tx_data_out_p
-ad_connect  tx_data_out_1_n             axi_ad9361_1/tx_data_out_n
+ad_connect  rx_clk_in_0_p     axi_ad9361_0/rx_clk_in_p
+ad_connect  rx_clk_in_0_n     axi_ad9361_0/rx_clk_in_n
+ad_connect  rx_frame_in_0_p   axi_ad9361_0/rx_frame_in_p
+ad_connect  rx_frame_in_0_n   axi_ad9361_0/rx_frame_in_n
+ad_connect  rx_data_in_0_p    axi_ad9361_0/rx_data_in_p
+ad_connect  rx_data_in_0_n    axi_ad9361_0/rx_data_in_n
+ad_connect  tx_clk_out_0_p    axi_ad9361_0/tx_clk_out_p
+ad_connect  tx_clk_out_0_n    axi_ad9361_0/tx_clk_out_n
+ad_connect  tx_frame_out_0_p  axi_ad9361_0/tx_frame_out_p
+ad_connect  tx_frame_out_0_n  axi_ad9361_0/tx_frame_out_n
+ad_connect  tx_data_out_0_p   axi_ad9361_0/tx_data_out_p
+ad_connect  tx_data_out_0_n   axi_ad9361_0/tx_data_out_n
+ad_connect  rx_clk_in_1_p     axi_ad9361_1/rx_clk_in_p
+ad_connect  rx_clk_in_1_n     axi_ad9361_1/rx_clk_in_n
+ad_connect  rx_frame_in_1_p   axi_ad9361_1/rx_frame_in_p
+ad_connect  rx_frame_in_1_n   axi_ad9361_1/rx_frame_in_n
+ad_connect  rx_data_in_1_p    axi_ad9361_1/rx_data_in_p
+ad_connect  rx_data_in_1_n    axi_ad9361_1/rx_data_in_n
+ad_connect  tx_clk_out_1_p    axi_ad9361_1/tx_clk_out_p
+ad_connect  tx_clk_out_1_n    axi_ad9361_1/tx_clk_out_n
+ad_connect  tx_frame_out_1_p  axi_ad9361_1/tx_frame_out_p
+ad_connect  tx_frame_out_1_n  axi_ad9361_1/tx_frame_out_n
+ad_connect  tx_data_out_1_p   axi_ad9361_1/tx_data_out_p
+ad_connect  tx_data_out_1_n   axi_ad9361_1/tx_data_out_n
 
+ad_connect  concat_logic/In0     axi_ad9361_0/adc_r1_mode
+ad_connect  concat_logic/In1     axi_ad9361_0/dac_r1_mode
+ad_connect  concat_logic/In2     axi_ad9361_1/adc_r1_mode
+ad_connect  concat_logic/In3     axi_ad9361_1/dac_r1_mode
+ad_connect  concat_logic/dout    clkdiv_sel_logic/Op1
+ad_connect  clkdiv_sel_logic/Res clkdiv/clk_sel
 
-
-ad_connect  axi_ad9361_0/adc_enable_i0  adc_wfifo/din_enable_0 
+ad_connect  adc_wfifo/dout_ovf          axi_ad9361_0/adc_dovf
+ad_connect  axi_ad9361_0/adc_enable_i0  adc_wfifo/din_enable_0
 ad_connect  axi_ad9361_0/adc_valid_i0   adc_wfifo/din_valid_0
 ad_connect  axi_ad9361_0/adc_data_i0    adc_wfifo/din_data_0
 ad_connect  axi_ad9361_0/adc_enable_q0  adc_wfifo/din_enable_1
@@ -175,64 +204,92 @@ ad_connect  axi_ad9361_1/adc_valid_i1   adc_wfifo/din_valid_6
 ad_connect  axi_ad9361_1/adc_data_i1    adc_wfifo/din_data_6
 ad_connect  axi_ad9361_1/adc_enable_q1  adc_wfifo/din_enable_7
 ad_connect  axi_ad9361_1/adc_valid_q1   adc_wfifo/din_valid_7
-ad_connect  axi_ad9361_1/adc_data_q1    adc_wfifo/din_data_7    
+ad_connect  axi_ad9361_1/adc_data_q1    adc_wfifo/din_data_7
 
-ad_connect  util_cpack_adc/adc_enable_0  adc_wfifo/dout_enable_0 
-ad_connect  util_cpack_adc/adc_valid_0   adc_wfifo/dout_valid_0
-ad_connect  util_cpack_adc/adc_data_0    adc_wfifo/dout_data_0
-ad_connect  util_cpack_adc/adc_enable_1  adc_wfifo/dout_enable_1
-ad_connect  util_cpack_adc/adc_valid_1   adc_wfifo/dout_valid_1
-ad_connect  util_cpack_adc/adc_data_1    adc_wfifo/dout_data_1
-ad_connect  util_cpack_adc/adc_enable_2  adc_wfifo/dout_enable_2
-ad_connect  util_cpack_adc/adc_valid_2   adc_wfifo/dout_valid_2
-ad_connect  util_cpack_adc/adc_data_2    adc_wfifo/dout_data_2
-ad_connect  util_cpack_adc/adc_enable_3  adc_wfifo/dout_enable_3
-ad_connect  util_cpack_adc/adc_valid_3   adc_wfifo/dout_valid_3
-ad_connect  util_cpack_adc/adc_data_3    adc_wfifo/dout_data_3
-ad_connect  util_cpack_adc/adc_enable_4  adc_wfifo/dout_enable_4
-ad_connect  util_cpack_adc/adc_valid_4   adc_wfifo/dout_valid_4
-ad_connect  util_cpack_adc/adc_data_4    adc_wfifo/dout_data_4
-ad_connect  util_cpack_adc/adc_enable_5  adc_wfifo/dout_enable_5
-ad_connect  util_cpack_adc/adc_valid_5   adc_wfifo/dout_valid_5
-ad_connect  util_cpack_adc/adc_data_5    adc_wfifo/dout_data_5
-ad_connect  util_cpack_adc/adc_enable_6  adc_wfifo/dout_enable_6
-ad_connect  util_cpack_adc/adc_valid_6   adc_wfifo/dout_valid_6
-ad_connect  util_cpack_adc/adc_data_6    adc_wfifo/dout_data_6
-ad_connect  util_cpack_adc/adc_enable_7  adc_wfifo/dout_enable_7
-ad_connect  util_cpack_adc/adc_valid_7   adc_wfifo/dout_valid_7
-ad_connect  util_cpack_adc/adc_data_7    adc_wfifo/dout_data_7
+ad_connect  util_cpack_adc/adc_enable_0 adc_wfifo/dout_enable_0
+ad_connect  util_cpack_adc/adc_valid_0  adc_wfifo/dout_valid_0
+ad_connect  util_cpack_adc/adc_data_0   adc_wfifo/dout_data_0
+ad_connect  util_cpack_adc/adc_enable_1 adc_wfifo/dout_enable_1
+ad_connect  util_cpack_adc/adc_valid_1  adc_wfifo/dout_valid_1
+ad_connect  util_cpack_adc/adc_data_1   adc_wfifo/dout_data_1
+ad_connect  util_cpack_adc/adc_enable_2 adc_wfifo/dout_enable_2
+ad_connect  util_cpack_adc/adc_valid_2  adc_wfifo/dout_valid_2
+ad_connect  util_cpack_adc/adc_data_2   adc_wfifo/dout_data_2
+ad_connect  util_cpack_adc/adc_enable_3 adc_wfifo/dout_enable_3
+ad_connect  util_cpack_adc/adc_valid_3  adc_wfifo/dout_valid_3
+ad_connect  util_cpack_adc/adc_data_3   adc_wfifo/dout_data_3
+ad_connect  util_cpack_adc/adc_enable_4 adc_wfifo/dout_enable_4
+ad_connect  util_cpack_adc/adc_valid_4  adc_wfifo/dout_valid_4
+ad_connect  util_cpack_adc/adc_data_4   adc_wfifo/dout_data_4
+ad_connect  util_cpack_adc/adc_enable_5 adc_wfifo/dout_enable_5
+ad_connect  util_cpack_adc/adc_valid_5  adc_wfifo/dout_valid_5
+ad_connect  util_cpack_adc/adc_data_5   adc_wfifo/dout_data_5
+ad_connect  util_cpack_adc/adc_enable_6 adc_wfifo/dout_enable_6
+ad_connect  util_cpack_adc/adc_valid_6  adc_wfifo/dout_valid_6
+ad_connect  util_cpack_adc/adc_data_6   adc_wfifo/dout_data_6
+ad_connect  util_cpack_adc/adc_enable_7 adc_wfifo/dout_enable_7
+ad_connect  util_cpack_adc/adc_valid_7  adc_wfifo/dout_valid_7
+ad_connect  util_cpack_adc/adc_data_7   adc_wfifo/dout_data_7
 
 ad_connect  util_cpack_adc/adc_valid    axi_ad9361_adc_dma/fifo_wr_en
 ad_connect  util_cpack_adc/adc_sync     axi_ad9361_adc_dma/fifo_wr_sync
 ad_connect  util_cpack_adc/adc_data     axi_ad9361_adc_dma/fifo_wr_din
-ad_connect  axi_ad9361_0/dac_enable_i0  util_upack_dac/dac_enable_0
-ad_connect  axi_ad9361_0/dac_valid_i0   util_upack_dac/dac_valid_0
-ad_connect  axi_ad9361_0/dac_data_i0    util_upack_dac/dac_data_0
-ad_connect  axi_ad9361_0/dac_enable_q0  util_upack_dac/dac_enable_1
-ad_connect  axi_ad9361_0/dac_valid_q0   util_upack_dac/dac_valid_1
-ad_connect  axi_ad9361_0/dac_data_q0    util_upack_dac/dac_data_1
-ad_connect  axi_ad9361_0/dac_enable_i1  util_upack_dac/dac_enable_2
-ad_connect  axi_ad9361_0/dac_valid_i1   util_upack_dac/dac_valid_2
-ad_connect  axi_ad9361_0/dac_data_i1    util_upack_dac/dac_data_2
-ad_connect  axi_ad9361_0/dac_enable_q1  util_upack_dac/dac_enable_3
-ad_connect  axi_ad9361_0/dac_valid_q1   util_upack_dac/dac_valid_3
-ad_connect  axi_ad9361_0/dac_data_q1    util_upack_dac/dac_data_3
-ad_connect  axi_ad9361_1/dac_enable_i0  util_upack_dac/dac_enable_4
-ad_connect  axi_ad9361_1/dac_valid_i0   util_upack_dac/dac_valid_4
-ad_connect  axi_ad9361_1/dac_data_i0    util_upack_dac/dac_data_4
-ad_connect  axi_ad9361_1/dac_enable_q0  util_upack_dac/dac_enable_5
-ad_connect  axi_ad9361_1/dac_valid_q0   util_upack_dac/dac_valid_5
-ad_connect  axi_ad9361_1/dac_data_q0    util_upack_dac/dac_data_5
-ad_connect  axi_ad9361_1/dac_enable_i1  util_upack_dac/dac_enable_6
-ad_connect  axi_ad9361_1/dac_valid_i1   util_upack_dac/dac_valid_6
-ad_connect  axi_ad9361_1/dac_data_i1    util_upack_dac/dac_data_6
-ad_connect  axi_ad9361_1/dac_enable_q1  util_upack_dac/dac_enable_7
-ad_connect  axi_ad9361_1/dac_valid_q1   util_upack_dac/dac_valid_7
-ad_connect  axi_ad9361_1/dac_data_q1    util_upack_dac/dac_data_7
-ad_connect  util_upack_dac/dac_valid    axi_ad9361_dac_dma/fifo_rd_en
-ad_connect  util_upack_dac/dac_data     axi_ad9361_dac_dma/fifo_rd_dout
-ad_connect  axi_ad9361_0/adc_dovf       axi_ad9361_adc_dma/fifo_wr_overflow
-ad_connect  axi_ad9361_0/dac_dunf       axi_ad9361_dac_dma/fifo_rd_underflow
+
+ad_connect  dac_fifo/din_enable_0 util_upack_dac/dac_enable_0
+ad_connect  dac_fifo/din_valid_0  util_upack_dac/dac_valid_0
+ad_connect  dac_fifo/din_data_0   util_upack_dac/dac_data_0
+ad_connect  dac_fifo/din_enable_1 util_upack_dac/dac_enable_1
+ad_connect  dac_fifo/din_valid_1  util_upack_dac/dac_valid_1
+ad_connect  dac_fifo/din_data_1   util_upack_dac/dac_data_1
+ad_connect  dac_fifo/din_enable_2 util_upack_dac/dac_enable_2
+ad_connect  dac_fifo/din_valid_2  util_upack_dac/dac_valid_2
+ad_connect  dac_fifo/din_data_2   util_upack_dac/dac_data_2
+ad_connect  dac_fifo/din_enable_3 util_upack_dac/dac_enable_3
+ad_connect  dac_fifo/din_valid_3  util_upack_dac/dac_valid_3
+ad_connect  dac_fifo/din_data_3   util_upack_dac/dac_data_3
+ad_connect  dac_fifo/din_enable_4 util_upack_dac/dac_enable_4
+ad_connect  dac_fifo/din_valid_4  util_upack_dac/dac_valid_4
+ad_connect  dac_fifo/din_data_4   util_upack_dac/dac_data_4
+ad_connect  dac_fifo/din_enable_5 util_upack_dac/dac_enable_5
+ad_connect  dac_fifo/din_valid_5  util_upack_dac/dac_valid_5
+ad_connect  dac_fifo/din_data_5   util_upack_dac/dac_data_5
+ad_connect  dac_fifo/din_enable_6 util_upack_dac/dac_enable_6
+ad_connect  dac_fifo/din_valid_6  util_upack_dac/dac_valid_6
+ad_connect  dac_fifo/din_data_6   util_upack_dac/dac_data_6
+ad_connect  dac_fifo/din_enable_7 util_upack_dac/dac_enable_7
+ad_connect  dac_fifo/din_valid_7  util_upack_dac/dac_valid_7
+ad_connect  dac_fifo/din_data_7   util_upack_dac/dac_data_7
+
+ad_connect  util_upack_dac/dac_valid  axi_ad9361_dac_dma/fifo_rd_en
+ad_connect  util_upack_dac/dac_data   axi_ad9361_dac_dma/fifo_rd_dout
+
+ad_connect  axi_ad9361_0/dac_enable_i0  dac_fifo/dout_enable_0
+ad_connect  axi_ad9361_0/dac_valid_i0   dac_fifo/dout_valid_0
+ad_connect  axi_ad9361_0/dac_data_i0    dac_fifo/dout_data_0
+ad_connect  axi_ad9361_0/dac_enable_q0  dac_fifo/dout_enable_1
+ad_connect  axi_ad9361_0/dac_valid_q0   dac_fifo/dout_valid_1
+ad_connect  axi_ad9361_0/dac_data_q0    dac_fifo/dout_data_1
+ad_connect  axi_ad9361_0/dac_enable_i1  dac_fifo/dout_enable_2
+ad_connect  axi_ad9361_0/dac_valid_i1   dac_fifo/dout_valid_2
+ad_connect  axi_ad9361_0/dac_data_i1    dac_fifo/dout_data_2
+ad_connect  axi_ad9361_0/dac_enable_q1  dac_fifo/dout_enable_3
+ad_connect  axi_ad9361_0/dac_valid_q1   dac_fifo/dout_valid_3
+ad_connect  axi_ad9361_0/dac_data_q1    dac_fifo/dout_data_3
+ad_connect  axi_ad9361_1/dac_enable_i0  dac_fifo/dout_enable_4
+ad_connect  axi_ad9361_1/dac_valid_i0   dac_fifo/dout_valid_4
+ad_connect  axi_ad9361_1/dac_data_i0    dac_fifo/dout_data_4
+ad_connect  axi_ad9361_1/dac_enable_q0  dac_fifo/dout_enable_5
+ad_connect  axi_ad9361_1/dac_valid_q0   dac_fifo/dout_valid_5
+ad_connect  axi_ad9361_1/dac_data_q0    dac_fifo/dout_data_5
+ad_connect  axi_ad9361_1/dac_enable_i1  dac_fifo/dout_enable_6
+ad_connect  axi_ad9361_1/dac_valid_i1   dac_fifo/dout_valid_6
+ad_connect  axi_ad9361_1/dac_data_i1    dac_fifo/dout_data_6
+ad_connect  axi_ad9361_1/dac_enable_q1  dac_fifo/dout_enable_7
+ad_connect  axi_ad9361_1/dac_valid_q1   dac_fifo/dout_valid_7
+ad_connect  axi_ad9361_1/dac_data_q1    dac_fifo/dout_data_7
+
+ad_connect  axi_ad9361_0/dac_dunf dac_fifo/dout_unf
+ad_connect  axi_ad9361_1/dac_dunf dac_fifo/dout_unf
 
 ad_connect  axi_ad9361_0/up_enable      up_enable_0
 ad_connect  axi_ad9361_0/up_txnrx       up_txnrx_0
diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile
index 00c7e089a..86ae994b5 100644
--- a/projects/fmcomms5/zc702/Makefile
+++ b/projects/fmcomms5/zc702/Makefile
@@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
 
@@ -57,7 +59,9 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
 
@@ -73,7 +77,9 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
 
diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile
index 069f26c0d..d58052759 100644
--- a/projects/fmcomms5/zc706/Makefile
+++ b/projects/fmcomms5/zc706/Makefile
@@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
 
@@ -57,7 +59,9 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_hdmi_tx clean
 	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
 
@@ -73,7 +77,9 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_hdmi_tx
 	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
 

From b622b6592ebf559907d1f1dbbea2da91ef7a1310 Mon Sep 17 00:00:00 2001
From: Nick Pillitteri <njpillitteri@gmail.com>
Date: Fri, 13 Jan 2017 07:47:16 -0500
Subject: [PATCH 851/972] FMCOMMS5/ZCU102 : Merge from njpillitteri/hdl:dev

Pull request Dev #26
---
 projects/fmcomms5/Makefile                  |   3 +
 projects/fmcomms5/zcu102/Makefile           |  81 +++++
 projects/fmcomms5/zcu102/system_bd.tcl      |  10 +
 projects/fmcomms5/zcu102/system_constr.xdc  | 135 ++++++++
 projects/fmcomms5/zcu102/system_project.tcl |  17 ++
 projects/fmcomms5/zcu102/system_top.v       | 323 ++++++++++++++++++++
 6 files changed, 569 insertions(+)
 create mode 100644 projects/fmcomms5/zcu102/Makefile
 create mode 100644 projects/fmcomms5/zcu102/system_bd.tcl
 create mode 100644 projects/fmcomms5/zcu102/system_constr.xdc
 create mode 100644 projects/fmcomms5/zcu102/system_project.tcl
 create mode 100644 projects/fmcomms5/zcu102/system_top.v

diff --git a/projects/fmcomms5/Makefile b/projects/fmcomms5/Makefile
index 1aadef09e..f7de0659c 100644
--- a/projects/fmcomms5/Makefile
+++ b/projects/fmcomms5/Makefile
@@ -9,16 +9,19 @@
 all:
 	-make -C zc702 all
 	-make -C zc706 all
+	-make -C zcu102 all
 
 
 clean: 
 	make -C zc702 clean
 	make -C zc706 clean
+	make -C zcu102 clean
 
 
 clean-all:
 	make -C zc702 clean-all
 	make -C zc706 clean-all
+	make -C zcu102 clean-all
 
 ####################################################################################
 ####################################################################################
diff --git a/projects/fmcomms5/zcu102/Makefile b/projects/fmcomms5/zcu102/Makefile
new file mode 100644
index 000000000..9ec988e1f
--- /dev/null
+++ b/projects/fmcomms5/zcu102/Makefile
@@ -0,0 +1,81 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/fmcomms5_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
+M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_upack/util_upack.xpr
+M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib fmcomms5_zcu102.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9361 clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_upack clean
+	make -C ../../../library/util_wfifo clean
+
+
+fmcomms5_zcu102.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> fmcomms5_zcu102_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9361
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_upack
+	make -C ../../../library/util_wfifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/fmcomms5/zcu102/system_bd.tcl b/projects/fmcomms5/zcu102/system_bd.tcl
new file mode 100644
index 000000000..202c3155f
--- /dev/null
+++ b/projects/fmcomms5/zcu102/system_bd.tcl
@@ -0,0 +1,10 @@
+
+source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
+
+set_property -dict [list CONFIG.PSU__FPGA_PL2_ENABLE {1}] $sys_ps8
+set_property -dict [list CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {200}] $sys_ps8
+ad_connect  sys_dma_clk sys_ps8/pl_clk2
+source ../common/fmcomms5_bd.tcl
+
+set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_0]
+set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_1]
diff --git a/projects/fmcomms5/zcu102/system_constr.xdc b/projects/fmcomms5/zcu102/system_constr.xdc
new file mode 100644
index 000000000..137c1a62d
--- /dev/null
+++ b/projects/fmcomms5/zcu102/system_constr.xdc
@@ -0,0 +1,135 @@
+
+# constraints
+
+# ad9361 master 
+
+set_property  -dict {PACKAGE_PIN  P11   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports ref_clk_p]             ; ## D20  FMC_HPC0_LA17_CC_P           
+set_property  -dict {PACKAGE_PIN  N11   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports ref_clk_n]             ; ## D21  FMC_HPC0_LA17_CC_N           
+
+set_property  -dict {PACKAGE_PIN  Y4    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_clk_in_0_p]         ; ## G06  FMC_HPC0_LA00_CC_P       
+set_property  -dict {PACKAGE_PIN  Y3    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_clk_in_0_n]         ; ## G07  FMC_HPC0_LA00_CC_N       
+set_property  -dict {PACKAGE_PIN  W2    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_frame_in_0_p]       ; ## D08  FMC_HPC0_LA01_CC_P       
+set_property  -dict {PACKAGE_PIN  W1    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_frame_in_0_n]       ; ## D09  FMC_HPC0_LA01_CC_N       
+set_property  -dict {PACKAGE_PIN  V2    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]]     ; ## H07  FMC_HPC0_LA02_P          
+set_property  -dict {PACKAGE_PIN  V1    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]]     ; ## H08  FMC_HPC0_LA02_N          
+set_property  -dict {PACKAGE_PIN  Y2    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]]     ; ## G09  FMC_HPC0_LA03_P          
+set_property  -dict {PACKAGE_PIN  Y1    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]]     ; ## G10  FMC_HPC0_LA03_N          
+set_property  -dict {PACKAGE_PIN  AA2   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]]     ; ## H10  FMC_HPC0_LA04_P          
+set_property  -dict {PACKAGE_PIN  AA1   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]]     ; ## H11  FMC_HPC0_LA04_N          
+set_property  -dict {PACKAGE_PIN  AB3   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]]     ; ## D11  FMC_HPC0_LA05_P          
+set_property  -dict {PACKAGE_PIN  AC3   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]]     ; ## D12  FMC_HPC0_LA05_N          
+set_property  -dict {PACKAGE_PIN  AC2   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]]     ; ## C10  FMC_HPC0_LA06_P          
+set_property  -dict {PACKAGE_PIN  AC1   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]]     ; ## C11  FMC_HPC0_LA06_N          
+set_property  -dict {PACKAGE_PIN  U5    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]]     ; ## H13  FMC_HPC0_LA07_P          
+set_property  -dict {PACKAGE_PIN  U4    IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]]     ; ## H14  FMC_HPC0_LA07_N          
+set_property  -dict {PACKAGE_PIN  V4    IOSTANDARD LVDS}   [get_ports tx_clk_out_0_p]                        ; ## G12  FMC_HPC0_LA08_P          
+set_property  -dict {PACKAGE_PIN  V3    IOSTANDARD LVDS}   [get_ports tx_clk_out_0_n]                        ; ## G13  FMC_HPC0_LA08_N          
+set_property  -dict {PACKAGE_PIN  AB4   IOSTANDARD LVDS}   [get_ports tx_frame_out_0_p]                      ; ## D14  FMC_HPC0_LA09_P          
+set_property  -dict {PACKAGE_PIN  AC4   IOSTANDARD LVDS}   [get_ports tx_frame_out_0_n]                      ; ## D15  FMC_HPC0_LA09_N          
+set_property  -dict {PACKAGE_PIN  W5    IOSTANDARD LVDS}   [get_ports tx_data_out_0_p[0]]                    ; ## C14  FMC_HPC0_LA10_P          
+set_property  -dict {PACKAGE_PIN  W4    IOSTANDARD LVDS}   [get_ports tx_data_out_0_n[0]]                    ; ## C15  FMC_HPC0_LA10_N          
+set_property  -dict {PACKAGE_PIN  AB6   IOSTANDARD LVDS}   [get_ports tx_data_out_0_p[1]]                    ; ## H16  FMC_HPC0_LA11_P          
+set_property  -dict {PACKAGE_PIN  AB5   IOSTANDARD LVDS}   [get_ports tx_data_out_0_n[1]]                    ; ## H17  FMC_HPC0_LA11_N          
+set_property  -dict {PACKAGE_PIN  W7    IOSTANDARD LVDS}   [get_ports tx_data_out_0_p[2]]                    ; ## G15  FMC_HPC0_LA12_P          
+set_property  -dict {PACKAGE_PIN  W6    IOSTANDARD LVDS}   [get_ports tx_data_out_0_n[2]]                    ; ## G16  FMC_HPC0_LA12_N          
+set_property  -dict {PACKAGE_PIN  AB8   IOSTANDARD LVDS}   [get_ports tx_data_out_0_p[3]]                    ; ## D17  FMC_HPC0_LA13_P          
+set_property  -dict {PACKAGE_PIN  AC8   IOSTANDARD LVDS}   [get_ports tx_data_out_0_n[3]]                    ; ## D18  FMC_HPC0_LA13_N          
+set_property  -dict {PACKAGE_PIN  AC7   IOSTANDARD LVDS}   [get_ports tx_data_out_0_p[4]]                    ; ## C18  FMC_HPC0_LA14_P          
+set_property  -dict {PACKAGE_PIN  AC6   IOSTANDARD LVDS}   [get_ports tx_data_out_0_n[4]]                    ; ## C19  FMC_HPC0_LA14_N          
+set_property  -dict {PACKAGE_PIN  Y10   IOSTANDARD LVDS}   [get_ports tx_data_out_0_p[5]]                    ; ## H19  FMC_HPC0_LA15_P          
+set_property  -dict {PACKAGE_PIN  Y9    IOSTANDARD LVDS}   [get_ports tx_data_out_0_n[5]]                    ; ## H20  FMC_HPC0_LA15_N          
+
+set_property  -dict {PACKAGE_PIN  L13   IOSTANDARD LVCMOS18}  [get_ports gpio_status_0[0]]                      ; ## H22  FMC_HPC0_LA19_P            
+set_property  -dict {PACKAGE_PIN  K13   IOSTANDARD LVCMOS18}  [get_ports gpio_status_0[1]]                      ; ## H23  FMC_HPC0_LA19_N            
+set_property  -dict {PACKAGE_PIN  N13   IOSTANDARD LVCMOS18}  [get_ports gpio_status_0[2]]                      ; ## G21  FMC_HPC0_LA20_P            
+set_property  -dict {PACKAGE_PIN  M13   IOSTANDARD LVCMOS18}  [get_ports gpio_status_0[3]]                      ; ## G22  FMC_HPC0_LA20_N            
+set_property  -dict {PACKAGE_PIN  P12   IOSTANDARD LVCMOS18}  [get_ports gpio_status_0[4]]                      ; ## H25  FMC_HPC0_LA21_P            
+set_property  -dict {PACKAGE_PIN  N12   IOSTANDARD LVCMOS18}  [get_ports gpio_status_0[5]]                      ; ## H26  FMC_HPC0_LA21_N            
+set_property  -dict {PACKAGE_PIN  M15   IOSTANDARD LVCMOS18}  [get_ports gpio_status_0[6]]                      ; ## G24  FMC_HPC0_LA22_P            
+set_property  -dict {PACKAGE_PIN  M14   IOSTANDARD LVCMOS18}  [get_ports gpio_status_0[7]]                      ; ## G25  FMC_HPC0_LA22_N            
+set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD LVCMOS18}  [get_ports gpio_ctl_0[0]]                         ; ## D23  FMC_HPC0_LA23_P            
+set_property  -dict {PACKAGE_PIN  K16   IOSTANDARD LVCMOS18}  [get_ports gpio_ctl_0[1]]                         ; ## D24  FMC_HPC0_LA23_N            
+set_property  -dict {PACKAGE_PIN  L12   IOSTANDARD LVCMOS18}  [get_ports gpio_ctl_0[2]]                         ; ## H28  FMC_HPC0_LA24_P            
+set_property  -dict {PACKAGE_PIN  K12   IOSTANDARD LVCMOS18}  [get_ports gpio_ctl_0[3]]                         ; ## H29  FMC_HPC0_LA24_N            
+set_property  -dict {PACKAGE_PIN  M11   IOSTANDARD LVCMOS18}  [get_ports gpio_en_agc_0]                         ; ## G27  FMC_HPC0_LA25_P            
+set_property  -dict {PACKAGE_PIN  L15   IOSTANDARD LVCMOS18}  [get_ports mcs_sync]                              ; ## C22  FMC_HPC0_LA18_CC_P         
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS18}  [get_ports gpio_resetb_0]                         ; ## C23  FMC_HPC0_LA18_CC_N         
+set_property  -dict {PACKAGE_PIN  Y12   IOSTANDARD LVCMOS18}  [get_ports enable_0]                              ; ## G18  FMC_HPC0_LA16_P
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS18}  [get_ports txnrx_0]                               ; ## G19  FMC_HPC0_LA16_N
+set_property  -dict {PACKAGE_PIN  M10   IOSTANDARD LVCMOS18}  [get_ports gpio_debug_1_0]                        ; ## C26  FMC_HPC0_LA27_P            
+set_property  -dict {PACKAGE_PIN  L10   IOSTANDARD LVCMOS18}  [get_ports gpio_debug_2_0]                        ; ## C27  FMC_HPC0_LA27_N            
+set_property  -dict {PACKAGE_PIN  N9    IOSTANDARD LVCMOS18}  [get_ports gpio_calsw_1_0]                        ; ## D26  FMC_HPC0_LA26_P            
+set_property  -dict {PACKAGE_PIN  N8    IOSTANDARD LVCMOS18}  [get_ports gpio_calsw_2_0]                        ; ## D27  FMC_HPC0_LA26_N            
+set_property  -dict {PACKAGE_PIN  T7    IOSTANDARD LVCMOS18}  [get_ports gpio_ad5355_rfen]                      ; ## H31  FMC_HPC0_LA28_P            
+set_property  -dict {PACKAGE_PIN  T6    IOSTANDARD LVCMOS18}  [get_ports gpio_ad5355_lock]                      ; ## H37  FMC_HPC0_LA32_P            
+
+# spi
+
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD LVCMOS18   PULLTYPE PULLUP} [get_ports spi_ad9361_0]         ; ## G30  FMC_HPC0_LA29_P              
+set_property  -dict {PACKAGE_PIN  U8    IOSTANDARD LVCMOS18   PULLTYPE PULLUP} [get_ports spi_ad9361_1]         ; ## G31  FMC_HPC0_LA29_N              
+set_property  -dict {PACKAGE_PIN  V6    IOSTANDARD LVCMOS18   PULLTYPE PULLUP} [get_ports spi_ad5355]           ; ## H34  FMC_HPC0_LA30_P              
+set_property  -dict {PACKAGE_PIN  U6    IOSTANDARD LVCMOS18}  [get_ports spi_clk]                               ; ## H35  FMC_HPC0_LA30_N              
+set_property  -dict {PACKAGE_PIN  V8    IOSTANDARD LVCMOS18}  [get_ports spi_mosi]                              ; ## G33  FMC_HPC0_LA31_P              
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD LVCMOS18}  [get_ports spi_miso]                              ; ## G34  FMC_HPC0_LA31_N              
+
+# ad9361 slave    
+
+set_property  -dict {PACKAGE_PIN  AE5   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_clk_in_1_p]         ; ## G06  FMC_HPC1_LA00_CC_P          
+set_property  -dict {PACKAGE_PIN  AF5   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_clk_in_1_n]         ; ## G07  FMC_HPC1_LA00_CC_N          
+set_property  -dict {PACKAGE_PIN  AE2   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_frame_in_1_p]       ; ## D08  FMC_HPC1_LA01_CC_P          
+set_property  -dict {PACKAGE_PIN  AE1   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_frame_in_1_n]       ; ## D09  FMC_HPC1_LA01_CC_N          
+set_property  -dict {PACKAGE_PIN  AD2   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]]     ; ## H07  FMC_HPC1_LA02_P             
+set_property  -dict {PACKAGE_PIN  AD1   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]]     ; ## H08  FMC_HPC1_LA02_N             
+set_property  -dict {PACKAGE_PIN  AH1   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]]     ; ## G09  FMC_HPC1_LA03_P             
+set_property  -dict {PACKAGE_PIN  AJ1   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]]     ; ## G10  FMC_HPC1_LA03_N             
+set_property  -dict {PACKAGE_PIN  AF2   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]]     ; ## H10  FMC_HPC1_LA04_P             
+set_property  -dict {PACKAGE_PIN  AF1   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]]     ; ## H11  FMC_HPC1_LA04_N             
+set_property  -dict {PACKAGE_PIN  AG3   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]]     ; ## D11  FMC_HPC1_LA05_P             
+set_property  -dict {PACKAGE_PIN  AH3   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]]     ; ## D12  FMC_HPC1_LA05_N             
+set_property  -dict {PACKAGE_PIN  AH2   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]]     ; ## C10  FMC_HPC1_LA06_P             
+set_property  -dict {PACKAGE_PIN  AJ2   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]]     ; ## C11  FMC_HPC1_LA06_N             
+set_property  -dict {PACKAGE_PIN  AD4   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]]     ; ## H13  FMC_HPC1_LA07_P             
+set_property  -dict {PACKAGE_PIN  AE4   IOSTANDARD LVDS    DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]]     ; ## H14  FMC_HPC1_LA07_N             
+set_property  -dict {PACKAGE_PIN  AE3   IOSTANDARD LVDS}   [get_ports tx_clk_out_1_p]                        ; ## G12  FMC_HPC1_LA08_P             
+set_property  -dict {PACKAGE_PIN  AF3   IOSTANDARD LVDS}   [get_ports tx_clk_out_1_n]                        ; ## G13  FMC_HPC1_LA08_N             
+set_property  -dict {PACKAGE_PIN  AJ6   IOSTANDARD LVDS}   [get_ports tx_frame_out_1_p]                      ; ## D14  FMC_HPC1_LA09_P             
+set_property  -dict {PACKAGE_PIN  AJ5   IOSTANDARD LVDS}   [get_ports tx_frame_out_1_n]                      ; ## D15  FMC_HPC1_LA09_N             
+set_property  -dict {PACKAGE_PIN  AH4   IOSTANDARD LVDS}   [get_ports tx_data_out_1_p[0]]                    ; ## C14  FMC_HPC1_LA10_P             
+set_property  -dict {PACKAGE_PIN  AJ4   IOSTANDARD LVDS}   [get_ports tx_data_out_1_n[0]]                    ; ## C15  FMC_HPC1_LA10_N             
+set_property  -dict {PACKAGE_PIN  AE8   IOSTANDARD LVDS}   [get_ports tx_data_out_1_p[1]]                    ; ## H16  FMC_HPC1_LA11_P             
+set_property  -dict {PACKAGE_PIN  AF8   IOSTANDARD LVDS}   [get_ports tx_data_out_1_n[1]]                    ; ## H17  FMC_HPC1_LA11_N             
+set_property  -dict {PACKAGE_PIN  AD7   IOSTANDARD LVDS}   [get_ports tx_data_out_1_p[2]]                    ; ## G15  FMC_HPC1_LA12_P             
+set_property  -dict {PACKAGE_PIN  AD6   IOSTANDARD LVDS}   [get_ports tx_data_out_1_n[2]]                    ; ## G16  FMC_HPC1_LA12_N             
+set_property  -dict {PACKAGE_PIN  AG8   IOSTANDARD LVDS}   [get_ports tx_data_out_1_p[3]]                    ; ## D17  FMC_HPC1_LA13_P             
+set_property  -dict {PACKAGE_PIN  AH8   IOSTANDARD LVDS}   [get_ports tx_data_out_1_n[3]]                    ; ## D18  FMC_HPC1_LA13_N             
+set_property  -dict {PACKAGE_PIN  AH7   IOSTANDARD LVDS}   [get_ports tx_data_out_1_p[4]]                    ; ## C18  FMC_HPC1_LA14_P             
+set_property  -dict {PACKAGE_PIN  AH6   IOSTANDARD LVDS}   [get_ports tx_data_out_1_n[4]]                    ; ## C19  FMC_HPC1_LA14_N             
+set_property  -dict {PACKAGE_PIN  AD10  IOSTANDARD LVDS}   [get_ports tx_data_out_1_p[5]]                    ; ## H19  FMC_HPC1_LA15_P             
+set_property  -dict {PACKAGE_PIN  AE9   IOSTANDARD LVDS}   [get_ports tx_data_out_1_n[5]]                    ; ## H20  FMC_HPC1_LA15_N             
+
+set_property  -dict {PACKAGE_PIN  AA11  IOSTANDARD LVCMOS18}  [get_ports gpio_status_1[0]]                      ; ## H22  FMC_HPC1_LA19_P             
+set_property  -dict {PACKAGE_PIN  AA10  IOSTANDARD LVCMOS18}  [get_ports gpio_status_1[1]]                      ; ## H23  FMC_HPC1_LA19_N             
+set_property  -dict {PACKAGE_PIN  AB11  IOSTANDARD LVCMOS18}  [get_ports gpio_status_1[2]]                      ; ## G21  FMC_HPC1_LA20_P             
+set_property  -dict {PACKAGE_PIN  AB10  IOSTANDARD LVCMOS18}  [get_ports gpio_status_1[3]]                      ; ## G22  FMC_HPC1_LA20_N             
+set_property  -dict {PACKAGE_PIN  AC12  IOSTANDARD LVCMOS18}  [get_ports gpio_status_1[4]]                      ; ## H25  FMC_HPC1_LA21_P             
+set_property  -dict {PACKAGE_PIN  AC11  IOSTANDARD LVCMOS18}  [get_ports gpio_status_1[5]]                      ; ## H26  FMC_HPC1_LA21_N             
+set_property  -dict {PACKAGE_PIN  AF11  IOSTANDARD LVCMOS18}  [get_ports gpio_status_1[6]]                      ; ## G24  FMC_HPC1_LA22_P             
+set_property  -dict {PACKAGE_PIN  AG11  IOSTANDARD LVCMOS18}  [get_ports gpio_status_1[7]]                      ; ## G25  FMC_HPC1_LA22_N             
+set_property  -dict {PACKAGE_PIN  AE12  IOSTANDARD LVCMOS18}  [get_ports gpio_ctl_1[0]]                         ; ## D23  FMC_HPC1_LA23_P             
+set_property  -dict {PACKAGE_PIN  AF12  IOSTANDARD LVCMOS18}  [get_ports gpio_ctl_1[1]]                         ; ## D24  FMC_HPC1_LA23_N             
+set_property  -dict {PACKAGE_PIN  AH12  IOSTANDARD LVCMOS18}  [get_ports gpio_ctl_1[2]]                         ; ## H28  FMC_HPC1_LA24_P             
+set_property  -dict {PACKAGE_PIN  AH11  IOSTANDARD LVCMOS18}  [get_ports gpio_ctl_1[3]]                         ; ## H29  FMC_HPC1_LA24_N             
+set_property  -dict {PACKAGE_PIN  AE10  IOSTANDARD LVCMOS18}  [get_ports gpio_en_agc_1]                         ; ## G27  FMC_HPC1_LA25_P             
+set_property  -dict {PACKAGE_PIN  W12   IOSTANDARD LVCMOS18}  [get_ports gpio_resetb_1]                         ; ## G30  FMC_HPC1_LA29_P         
+set_property  -dict {PACKAGE_PIN  AG10  IOSTANDARD LVCMOS18}  [get_ports enable_1]                              ; ## G18  FMC_HPC1_LA16_P
+set_property  -dict {PACKAGE_PIN  AG9   IOSTANDARD LVCMOS18}  [get_ports txnrx_1]                               ; ## G19  FMC_HPC1_LA16_N
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD LVCMOS18}  [get_ports gpio_debug_3_1]                        ; ## C26  FMC_HPC1_LA27_P             
+set_property  -dict {PACKAGE_PIN  T10   IOSTANDARD LVCMOS18}  [get_ports gpio_debug_4_1]                        ; ## C27  FMC_HPC1_LA27_N             
+set_property  -dict {PACKAGE_PIN  T12   IOSTANDARD LVCMOS18}  [get_ports gpio_calsw_3_1]                        ; ## D26  FMC_HPC1_LA26_P             
+set_property  -dict {PACKAGE_PIN  R12   IOSTANDARD LVCMOS18}  [get_ports gpio_calsw_4_1]                        ; ## D27  FMC_HPC1_LA26_N             
+
+# clocks
+
+create_clock -name rx_0_clk       -period   4.00 [get_ports rx_clk_in_0_p]
+create_clock -name rx_1_clk       -period   4.00 [get_ports rx_clk_in_1_p]
+create_clock -name ad9361_clk     -period   4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
diff --git a/projects/fmcomms5/zcu102/system_project.tcl b/projects/fmcomms5/zcu102/system_project.tcl
new file mode 100644
index 000000000..053a7b985
--- /dev/null
+++ b/projects/fmcomms5/zcu102/system_project.tcl
@@ -0,0 +1,17 @@
+
+
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create fmcomms5_zcu102
+adi_project_files fmcomms5_zcu102 [list \
+  "system_top.v" \
+  "system_constr.xdc"\
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
+
+adi_project_run fmcomms5_zcu102
+
+
diff --git a/projects/fmcomms5/zcu102/system_top.v b/projects/fmcomms5/zcu102/system_top.v
new file mode 100644
index 000000000..5c665f94e
--- /dev/null
+++ b/projects/fmcomms5/zcu102/system_top.v
@@ -0,0 +1,323 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  gpio_bd_i,
+  gpio_bd_o,
+
+  rx_clk_in_0_p,
+  rx_clk_in_0_n,
+  rx_frame_in_0_p,
+  rx_frame_in_0_n,
+  rx_data_in_0_p,
+  rx_data_in_0_n,
+  tx_clk_out_0_p,
+  tx_clk_out_0_n,
+  tx_frame_out_0_p,
+  tx_frame_out_0_n,
+  tx_data_out_0_p,
+  tx_data_out_0_n,
+  gpio_status_0,
+  gpio_ctl_0,
+  gpio_en_agc_0,
+  mcs_sync,
+  gpio_resetb_0,
+  enable_0,
+  txnrx_0,
+  gpio_debug_1_0,
+  gpio_debug_2_0,
+  gpio_calsw_1_0,
+  gpio_calsw_2_0,
+  gpio_ad5355_rfen,
+  gpio_ad5355_lock,
+
+  rx_clk_in_1_p,
+  rx_clk_in_1_n,
+  rx_frame_in_1_p,
+  rx_frame_in_1_n,
+  rx_data_in_1_p,
+  rx_data_in_1_n,
+  tx_clk_out_1_p,
+  tx_clk_out_1_n,
+  tx_frame_out_1_p,
+  tx_frame_out_1_n,
+  tx_data_out_1_p,
+  tx_data_out_1_n,
+  gpio_status_1,
+  gpio_ctl_1,
+  gpio_en_agc_1,
+  gpio_resetb_1,
+  enable_1,
+  txnrx_1,
+  gpio_debug_3_1,
+  gpio_debug_4_1,
+  gpio_calsw_3_1,
+  gpio_calsw_4_1,
+
+  spi_ad9361_0,
+  spi_ad9361_1,
+  spi_ad5355,
+  spi_clk,
+  spi_mosi,
+  spi_miso,
+
+  ref_clk_p,
+  ref_clk_n);
+
+  input   [12:0]  gpio_bd_i;
+  output  [ 7:0]  gpio_bd_o;
+
+  input           rx_clk_in_0_p;
+  input           rx_clk_in_0_n;
+  input           rx_frame_in_0_p;
+  input           rx_frame_in_0_n;
+  input   [  5:0] rx_data_in_0_p;
+  input   [  5:0] rx_data_in_0_n;
+  output          tx_clk_out_0_p;
+  output          tx_clk_out_0_n;
+  output          tx_frame_out_0_p;
+  output          tx_frame_out_0_n;
+  output  [  5:0] tx_data_out_0_p;
+  output  [  5:0] tx_data_out_0_n;
+  input   [  7:0] gpio_status_0;
+  output  [  3:0] gpio_ctl_0;
+  output          gpio_en_agc_0;
+  output          mcs_sync;
+  output          gpio_resetb_0;
+  output          enable_0;
+  output          txnrx_0;
+  output          gpio_debug_1_0;
+  output          gpio_debug_2_0;
+  output          gpio_calsw_1_0;
+  output          gpio_calsw_2_0;
+  output          gpio_ad5355_rfen;
+  input           gpio_ad5355_lock;
+
+  input           rx_clk_in_1_p;
+  input           rx_clk_in_1_n;
+  input           rx_frame_in_1_p;
+  input           rx_frame_in_1_n;
+  input   [  5:0] rx_data_in_1_p;
+  input   [  5:0] rx_data_in_1_n;
+  output          tx_clk_out_1_p;
+  output          tx_clk_out_1_n;
+  output          tx_frame_out_1_p;
+  output          tx_frame_out_1_n;
+  output  [  5:0] tx_data_out_1_p;
+  output  [  5:0] tx_data_out_1_n;
+  input   [  7:0] gpio_status_1;
+  output  [  3:0] gpio_ctl_1;
+  output          gpio_en_agc_1;
+  output          gpio_resetb_1;
+  output          enable_1;
+  output          txnrx_1;
+  output          gpio_debug_3_1;
+  output          gpio_debug_4_1;
+  output          gpio_calsw_3_1;
+  output          gpio_calsw_4_1;
+
+  output          spi_ad9361_0;
+  output          spi_ad9361_1;
+  output          spi_ad5355;
+  output          spi_clk;
+  output          spi_mosi;
+  input           spi_miso;
+
+  input           ref_clk_p;
+  input           ref_clk_n;
+
+  // internal registers
+
+  reg     [  2:0] mcs_sync_m = 'd0;
+  reg             mcs_sync = 'd0;
+
+  // internal signals
+
+  wire            sys_100m_resetn;
+  wire            ref_clk_s;
+  wire            ref_clk;
+  wire    [ 94:0] gpio_i;
+  wire    [ 94:0] gpio_o;
+  wire            gpio_sync;
+  wire            gpio_open_44_44;
+  wire            gpio_open_15_15;
+  wire    [ 2:0]  spi0_csn;
+  wire            spi0_clk;
+  wire            spi0_mosi;
+  wire            spi0_miso;
+  wire    [ 2:0]  spi1_csn;
+  wire            spi1_clk;
+  wire            spi1_mosi;
+  wire            spi1_miso;
+  wire            txnrx_0;
+  wire            enable_0;
+  wire            txnrx_1;
+  wire            enable_1;
+
+  // multi-chip synchronization
+
+  always @(posedge ref_clk or negedge sys_100m_resetn) begin
+    if (sys_100m_resetn == 1'b0) begin
+      mcs_sync_m <= 3'd0;
+      mcs_sync <= 1'd0;
+    end else begin
+      mcs_sync_m <= {mcs_sync_m[1:0], gpio_sync};
+      mcs_sync <= mcs_sync_m[2] & ~mcs_sync_m[1];
+    end
+  end
+
+  // instantiations
+
+  IBUFGDS i_ref_clk_ibuf (
+    .I (ref_clk_p),
+    .IB (ref_clk_n),
+    .O (ref_clk_s));
+
+  BUFR #(.BUFR_DIVIDE("BYPASS")) i_ref_clk_rbuf (
+    .CLR (1'b0),
+    .CE (1'b1),
+    .I (ref_clk_s),
+    .O (ref_clk));
+
+  assign gpio_resetb_1 = gpio_o[65];
+  assign gpio_i[64] = gpio_ad5355_lock;
+  assign gpio_ad5355_rfen = gpio_o[63];
+  assign gpio_calsw_4_1 = gpio_o[62];
+  assign gpio_calsw_3_1 = gpio_o[61];
+  assign gpio_calsw_2_0 = gpio_o[60];
+  assign gpio_calsw_1_0 = gpio_o[59];
+  assign gpio_txnrx_1 = gpio_o[58];
+  assign gpio_enable_1 = gpio_o[57];
+  assign gpio_en_agc_1 = gpio_o[56];
+  assign gpio_txnrx_0 = gpio_o[55];
+  assign gpio_enable_0 = gpio_o[54];
+  assign gpio_en_agc_0 = gpio_o[53];
+  assign gpio_resetb_0 = gpio_o[52];
+  assign gpio_sync = gpio_o[51];
+  assign gpio_open_44_44 = gpio_o[50];
+  assign gpio_debug_4_0 = gpio_o[49];
+  assign gpio_debug_3_0 = gpio_o[48];
+  assign gpio_debug_2_0 = gpio_o[47];
+  assign gpio_debug_1_0 = gpio_o[46];
+  assign gpio_ctl_1 = gpio_o[45:42];
+  assign gpio_ctl_0 = gpio_o[41:38];
+  assign gpio_i[37:30] = gpio_status_1;
+  assign gpio_i[29:22] = gpio_status_0;
+  assign gpio_open_15_15 = gpio_o[21];
+  assign gpio_bd_o = gpio_o[20:13];
+  assign gpio_i[12: 0] = gpio_bd_i;
+
+  assign gpio_i[94:65] = gpio_o[94:65];
+  assign gpio_i[63:38] = gpio_o[63:38];
+  assign gpio_i[21:14] = gpio_o[21:14];
+
+  assign spi_ad9361_0 = spi0_csn[0];
+  assign spi_ad9361_1 = spi0_csn[1];
+  assign spi_ad5355   = spi0_csn[2];
+  assign spi_clk = spi0_clk;
+  assign spi_mosi = spi0_mosi;
+  assign spi0_miso = spi_miso;
+  assign spi1_miso = 1'b0;
+
+  system_wrapper i_system_wrapper (
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_08 (1'b0),
+    .ps_intr_09 (1'b0),
+    .ps_intr_10 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_14 (1'b0),
+    .ps_intr_15 (1'b0),
+    .rx_clk_in_0_n (rx_clk_in_0_n),
+    .rx_clk_in_0_p (rx_clk_in_0_p),
+    .rx_clk_in_1_n (rx_clk_in_1_n),
+    .rx_clk_in_1_p (rx_clk_in_1_p),
+    .rx_data_in_0_n (rx_data_in_0_n),
+    .rx_data_in_0_p (rx_data_in_0_p),
+    .rx_data_in_1_n (rx_data_in_1_n),
+    .rx_data_in_1_p (rx_data_in_1_p),
+    .rx_frame_in_0_n (rx_frame_in_0_n),
+    .rx_frame_in_0_p (rx_frame_in_0_p),
+    .rx_frame_in_1_n (rx_frame_in_1_n),
+    .rx_frame_in_1_p (rx_frame_in_1_p),
+    .spi0_csn (spi0_csn),
+    .spi0_miso (spi0_miso),
+    .spi0_mosi (spi0_mosi),
+    .spi0_sclk (spi0_clk),
+    .spi1_csn (spi1_csn),
+    .spi1_miso (spi1_miso),
+    .spi1_mosi (spi1_mosi),
+    .spi1_sclk (spi1_clk),
+    .sys_100m_resetn (sys_100m_resetn),
+    .tx_clk_out_0_n (tx_clk_out_0_n),
+    .tx_clk_out_0_p (tx_clk_out_0_p),
+    .tx_clk_out_1_n (tx_clk_out_1_n),
+    .tx_clk_out_1_p (tx_clk_out_1_p),
+    .tx_data_out_0_n (tx_data_out_0_n),
+    .tx_data_out_0_p (tx_data_out_0_p),
+    .tx_data_out_1_n (tx_data_out_1_n),
+    .tx_data_out_1_p (tx_data_out_1_p),
+    .tx_frame_out_0_n (tx_frame_out_0_n),
+    .tx_frame_out_0_p (tx_frame_out_0_p),
+    .tx_frame_out_1_n (tx_frame_out_1_n),
+    .tx_frame_out_1_p (tx_frame_out_1_p),
+    .txnrx_0 (txnrx_0),
+    .enable_0 (enable_0),
+    .up_enable_0 (gpio_enable_0),
+    .up_txnrx_0 (gpio_txnrx_0),
+    .txnrx_1 (txnrx_1),
+    .enable_1 (enable_1),
+    .up_enable_1 (gpio_enable_1),
+    .up_txnrx_1 (gpio_txnrx_1));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 61ee24f26af7808155ba04da0f7683bf3035d781 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 16 Jan 2017 14:35:42 +0200
Subject: [PATCH 852/972] util_clkdiv: Make the clock division parametrizable
 and changed C_SIM_DEVICE to SIM_DEVICE

---
 library/util_clkdiv/Makefile               |  1 +
 library/util_clkdiv/util_clkdiv.v          | 46 +++++++++++-----------
 library/util_clkdiv/util_clkdiv_constr.xdc |  2 +-
 library/util_clkdiv/util_clkdiv_ip.tcl     | 10 ++++-
 4 files changed, 34 insertions(+), 25 deletions(-)

diff --git a/library/util_clkdiv/Makefile b/library/util_clkdiv/Makefile
index 97c55259b..65d7aa1d0 100644
--- a/library/util_clkdiv/Makefile
+++ b/library/util_clkdiv/Makefile
@@ -8,6 +8,7 @@
 M_DEPS += ../scripts/adi_env.tcl
 M_DEPS += ../scripts/adi_ip.tcl
 M_DEPS += util_clkdiv.v
+M_DEPS += util_clkdiv_constr.xdc
 M_DEPS += util_clkdiv_ip.tcl
 
 M_VIVADO := vivado -mode batch -source
diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v
index e85fd41ed..9e8dbd659 100644
--- a/library/util_clkdiv/util_clkdiv.v
+++ b/library/util_clkdiv/util_clkdiv.v
@@ -34,9 +34,9 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1
-// IP uses BUFR and BUFGMUX_CTRL primitive
-// IP provides a glitch free output clock
+// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
+// clk_sel is 1. Provides a glitch free output clock
+// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
 // ***************************************************************************
 // ***************************************************************************
 
@@ -48,54 +48,56 @@ module util_clkdiv (
   output  clk_out
  );
 
-parameter C_SIM_DEVICE = "7SERIES";
+parameter SIM_DEVICE = "7SERIES";
+parameter SEL_0_DIV = "4";
+parameter SEL_1_DIV = "2";
 
-  wire clk_div_2_s;
-  wire clk_div_4_s;
+  wire clk_div_sel_0_s;
+  wire clk_div_sel_1_s;
 
-generate if (C_SIM_DEVICE == "7SERIES") begin
+generate if (SIM_DEVICE == "7SERIES") begin
 
   BUFR #(
-    .BUFR_DIVIDE("2"),
+    .BUFR_DIVIDE(SEL_0_DIV),
     .SIM_DEVICE("7SERIES")
-  ) clk_divide_2 (
+  ) clk_divide_sel_0 (
     .I(clk),
     .CE(1),
     .CLR(0),
-    .O(clk_div_2_s));
+    .O(clk_div_sel_0_s));
 
   BUFR #(
-    .BUFR_DIVIDE("4"),
+    .BUFR_DIVIDE(SEL_1_DIV),
     .SIM_DEVICE("7SERIES")
-  ) clk_divide_4 (
+  ) clk_divide_sel_1 (
     .I(clk),
     .CE(1),
     .CLR(0),
-    .O(clk_div_4_s));
+    .O(clk_div_sel_1_s));
 
-end else if (C_SIM_DEVICE == "ULTRASCALE") begin
+end else if (SIM_DEVICE == "ULTRASCALE") begin
 
   BUFGCE_DIV #(
-    .BUFGCE_DIVIDE("2")
-  ) clk_divide_2 (
+    .BUFGCE_DIVIDE(SEL_0_DIV)
+  ) clk_divide_sel_0 (
     .I(clk),
     .CE(1),
     .CLR(0),
-    .O(clk_div_2_s));
+    .O(clk_div_sel_0_s));
 
   BUFGCE_DIV #(
-    .BUFGCE_DIVIDE("4")
-  ) clk_divide_4 (
+    .BUFGCE_DIVIDE(SEL_1_DIV)
+  ) clk_divide_sel_1 (
     .I(clk),
     .CE(1),
     .CLR(0),
-    .O(clk_div_4_s));
+    .O(clk_div_sel_1_s));
 
 end endgenerate
 
   BUFGMUX_CTRL i_div_clk_gbuf (
-    .I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
-    .I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
+    .I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0)
+    .I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1)
     .S(clk_sel),
     .O (clk_out));
 
diff --git a/library/util_clkdiv/util_clkdiv_constr.xdc b/library/util_clkdiv/util_clkdiv_constr.xdc
index a988c4d6b..5cbe1488e 100644
--- a/library/util_clkdiv/util_clkdiv_constr.xdc
+++ b/library/util_clkdiv/util_clkdiv_constr.xdc
@@ -1,2 +1,2 @@
-set_clock_groups -group [get_clocks clk_div_4_s] -group [get_clocks clk_div_2_s] -logically_exclusive
+set_clock_groups -group [get_clocks clk_div_sel_0_s] -group [get_clocks clk_div_sel_1_s] -logically_exclusive
 set_false_path -to [get_pins i_div_clk_gbuf/S*]
diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl
index f3e370a5f..06ca0e5ea 100644
--- a/library/util_clkdiv/util_clkdiv_ip.tcl
+++ b/library/util_clkdiv/util_clkdiv_ip.tcl
@@ -13,7 +13,13 @@ adi_ip_constraints util_clkdiv [list \
 
 set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
 
-set_property value_validation_type list [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
-set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
+set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
+set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
+
+set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
+set_property value_validation_list {BYPASS 0 1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
+
+set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
+set_property value_validation_list {BYPASS 0 1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]

From 4dcad7e116984c475ab48e6f4450d58318a94d19 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 16 Jan 2017 14:38:37 +0200
Subject: [PATCH 853/972] fmcomms2: zcu102, update clkdiv device parameter

---
 projects/fmcomms2/zcu102/system_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcomms2/zcu102/system_bd.tcl b/projects/fmcomms2/zcu102/system_bd.tcl
index 515600a7e..5bcd5220a 100755
--- a/projects/fmcomms2/zcu102/system_bd.tcl
+++ b/projects/fmcomms2/zcu102/system_bd.tcl
@@ -2,7 +2,7 @@
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
 source ../common/fmcomms2_bd.tcl
 
-set_property -dict [list CONFIG.C_SIM_DEVICE {ULTRASCALE}] $clkdiv
+set_property -dict [list CONFIG.SIM_DEVICE {ULTRASCALE}] $clkdiv
 
 set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361]
 

From 9344dd34dcda19b0631ddfd0fe786dd1b0c2bfed Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 16 Jan 2017 14:47:31 +0200
Subject: [PATCH 854/972] zcu102: Update project to include clkdiv

---
 projects/fmcomms5/zcu102/Makefile      | 15 ++++++---------
 projects/fmcomms5/zcu102/system_bd.tcl |  2 ++
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/projects/fmcomms5/zcu102/Makefile b/projects/fmcomms5/zcu102/Makefile
index 9ec988e1f..f5d102359 100644
--- a/projects/fmcomms5/zcu102/Makefile
+++ b/projects/fmcomms5/zcu102/Makefile
@@ -17,11 +17,10 @@ M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
 M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
-M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
 
@@ -53,11 +52,10 @@ clean:
 
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
-	make -C ../../../library/axi_clkgen clean
 	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
 
@@ -69,11 +67,10 @@ fmcomms5_zcu102.sdk/system_top.hdf: $(M_DEPS)
 
 lib:
 	make -C ../../../library/axi_ad9361
-	make -C ../../../library/axi_clkgen
 	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
 
diff --git a/projects/fmcomms5/zcu102/system_bd.tcl b/projects/fmcomms5/zcu102/system_bd.tcl
index 202c3155f..aa27c93ed 100644
--- a/projects/fmcomms5/zcu102/system_bd.tcl
+++ b/projects/fmcomms5/zcu102/system_bd.tcl
@@ -8,3 +8,5 @@ source ../common/fmcomms5_bd.tcl
 
 set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_0]
 set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_1]
+
+set_property -dict [list CONFIG.SIM_DEVICE {ULTRASCALE}] $clkdiv

From 61afd106b517b1f18cb05786bd9f0a3bababad89 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 18 Jan 2017 11:56:24 +0200
Subject: [PATCH 855/972] util_clkdiv: Keep as valid only settings common for
 7Series and Ultrascale

---
 library/util_clkdiv/util_clkdiv_ip.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl
index 06ca0e5ea..0dd707ae5 100644
--- a/library/util_clkdiv/util_clkdiv_ip.tcl
+++ b/library/util_clkdiv/util_clkdiv_ip.tcl
@@ -17,9 +17,9 @@ set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of
 set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
 
 set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
-set_property value_validation_list {BYPASS 0 1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
+set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
 
 set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
-set_property value_validation_list {BYPASS 0 1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
+set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
 
 ipx::save_core [ipx::current_core]

From 319a883c0079a184a507592a40f95c4cfa48784c Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 18 Jan 2017 12:00:10 +0200
Subject: [PATCH 856/972] pzsdr2: Added FIFOs for DAC and ADC paths so that
 they work at l_clk/2 or l_clk/4

---
 projects/pzsdr2/ccbox_lvds/Makefile      |  6 ++
 projects/pzsdr2/ccbrk_cmos/Makefile      |  6 ++
 projects/pzsdr2/ccbrk_cmos/system_bd.tcl |  3 +
 projects/pzsdr2/ccbrk_lvds/Makefile      |  6 ++
 projects/pzsdr2/ccfmc_lvds/Makefile      |  6 ++
 projects/pzsdr2/ccpci_lvds/Makefile      |  6 ++
 projects/pzsdr2/ccusb_lvds/Makefile      |  6 ++
 projects/pzsdr2/common/pzsdr2_bd.tcl     | 80 +++++++++++++++++-------
 8 files changed, 98 insertions(+), 21 deletions(-)

diff --git a/projects/pzsdr2/ccbox_lvds/Makefile b/projects/pzsdr2/ccbox_lvds/Makefile
index 114c11828..d799a33e0 100644
--- a/projects/pzsdr2/ccbox_lvds/Makefile
+++ b/projects/pzsdr2/ccbox_lvds/Makefile
@@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -55,7 +57,9 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_i2s_adi clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -70,7 +74,9 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_i2s_adi
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr2/ccbrk_cmos/Makefile b/projects/pzsdr2/ccbrk_cmos/Makefile
index f674cda7c..6825ac058 100644
--- a/projects/pzsdr2/ccbrk_cmos/Makefile
+++ b/projects/pzsdr2/ccbrk_cmos/Makefile
@@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
 M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -57,7 +59,9 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_gpreg clean
 	make -C ../../../library/xilinx/axi_xcvrlb clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -73,7 +77,9 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_gpreg
 	make -C ../../../library/xilinx/axi_xcvrlb
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr2/ccbrk_cmos/system_bd.tcl b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
index de8969baf..f89be6423 100644
--- a/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
+++ b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl
@@ -2,5 +2,8 @@
 source ../common/pzsdr2_bd.tcl
 source ../common/ccbrk_bd.tcl
 
+set_property -dict [list CONFIG.SEL_0_DIV {2}] $clkdiv
+set_property -dict [list CONFIG.SEL_1_DIV {1}] $clkdiv
+
 cfg_ad9361_interface CMOS
 
diff --git a/projects/pzsdr2/ccbrk_lvds/Makefile b/projects/pzsdr2/ccbrk_lvds/Makefile
index 5373dd43a..39c09c96f 100644
--- a/projects/pzsdr2/ccbrk_lvds/Makefile
+++ b/projects/pzsdr2/ccbrk_lvds/Makefile
@@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
 M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -57,7 +59,9 @@ clean-all:clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_gpreg clean
 	make -C ../../../library/xilinx/axi_xcvrlb clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -73,7 +77,9 @@ lib:
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_gpreg
 	make -C ../../../library/xilinx/axi_xcvrlb
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr2/ccfmc_lvds/Makefile b/projects/pzsdr2/ccfmc_lvds/Makefile
index 4c251d062..4e53bec3e 100644
--- a/projects/pzsdr2/ccfmc_lvds/Makefile
+++ b/projects/pzsdr2/ccfmc_lvds/Makefile
@@ -25,7 +25,9 @@ M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
 M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
 M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -65,7 +67,9 @@ clean-all:clean
 	make -C ../../../library/axi_i2s_adi clean
 	make -C ../../../library/axi_spdif_tx clean
 	make -C ../../../library/xilinx/axi_xcvrlb clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -85,7 +89,9 @@ lib:
 	make -C ../../../library/axi_i2s_adi
 	make -C ../../../library/axi_spdif_tx
 	make -C ../../../library/xilinx/axi_xcvrlb
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr2/ccpci_lvds/Makefile b/projects/pzsdr2/ccpci_lvds/Makefile
index a51a62c98..593b2cd47 100644
--- a/projects/pzsdr2/ccpci_lvds/Makefile
+++ b/projects/pzsdr2/ccpci_lvds/Makefile
@@ -19,7 +19,9 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -53,7 +55,9 @@ clean:
 clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -67,7 +71,9 @@ pzsdr2_ccpci_lvds.sdk/system_top.hdf: $(M_DEPS)
 lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr2/ccusb_lvds/Makefile b/projects/pzsdr2/ccusb_lvds/Makefile
index 7b700ac07..e5cf5afbf 100644
--- a/projects/pzsdr2/ccusb_lvds/Makefile
+++ b/projects/pzsdr2/ccusb_lvds/Makefile
@@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -55,7 +57,9 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_usb_fx3 clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -70,7 +74,9 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_usb_fx3
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr2/common/pzsdr2_bd.tcl b/projects/pzsdr2/common/pzsdr2_bd.tcl
index bafa5c799..98b769f81 100644
--- a/projects/pzsdr2/common/pzsdr2_bd.tcl
+++ b/projects/pzsdr2/common/pzsdr2_bd.tcl
@@ -242,6 +242,21 @@ set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
 set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
 set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
 
+set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
+
+set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
+
+set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
+set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
+set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
+set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
+
+set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
+set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic
+
+set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
+set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic
+
 # connections
 
 ad_connect  sys_200m_clk axi_ad9361/delay_clk
@@ -253,11 +268,14 @@ ad_connect  up_enable axi_ad9361/up_enable
 ad_connect  up_txnrx axi_ad9361/up_txnrx
 ad_connect  axi_ad9361_clk util_ad9361_adc_fifo/din_clk
 ad_connect  axi_ad9361/rst util_ad9361_adc_fifo/din_rst
-ad_connect  sys_cpu_clk util_ad9361_adc_fifo/dout_clk
-ad_connect  sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
-ad_connect  sys_cpu_clk util_ad9361_adc_pack/adc_clk
-ad_connect  sys_cpu_reset util_ad9361_adc_pack/adc_rst
-ad_connect  sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  axi_ad9361_clk clkdiv/clk
+ad_connect  clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
+ad_connect  clkdiv/clk_out util_ad9361_adc_pack/adc_clk
+ad_connect  clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
+ad_connect  clkdiv_reset/slowest_sync_clk clkdiv/clk_out
+ad_connect  util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset
+ad_connect  util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn
 ad_connect  axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
 ad_connect  axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
 ad_connect  axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
@@ -287,23 +305,43 @@ ad_connect  util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
 ad_connect  util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
 ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
 ad_connect  util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
-ad_connect  axi_ad9361_clk util_ad9361_dac_upack/dac_clk
-ad_connect  axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
-ad_connect  util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
-ad_connect  util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
-ad_connect  util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
-ad_connect  util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
-ad_connect  util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
-ad_connect  util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
-ad_connect  util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
-ad_connect  util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
-ad_connect  util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
-ad_connect  util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
-ad_connect  util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
-ad_connect  util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
+ad_connect  axi_ad9361/adc_r1_mode concat_logic/In0
+ad_connect  axi_ad9361/dac_r1_mode concat_logic/In1
+ad_connect  concat_logic/dout clkdiv_sel_logic/Op1
+ad_connect  clkdiv/clk_sel clkdiv_sel_logic/Res
 ad_connect  util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
 ad_connect  util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
-ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
+ad_connect  clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
+ad_connect  axi_ad9361/dac_dunf dac_fifo/dout_unf
+ad_connect  dac_fifo/din_clk clkdiv/clk_out
+ad_connect  dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn
+ad_connect  axi_ad9361_clk dac_fifo/dout_clk
+ad_connect  dac_fifo/dout_rst axi_ad9361/rst
+ad_connect  util_ad9361_dac_upack/dac_clk clkdiv/clk_out
+ad_connect  dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0
+ad_connect  dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0
+ad_connect  dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0
+ad_connect  dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1
+ad_connect  dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1
+ad_connect  dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1
+ad_connect  dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2
+ad_connect  dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2
+ad_connect  dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2
+ad_connect  dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3
+ad_connect  dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3
+ad_connect  dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3
+ad_connect  axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0
+ad_connect  axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0
+ad_connect  axi_ad9361/dac_data_i0 dac_fifo/dout_data_0
+ad_connect  axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1
+ad_connect  axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1
+ad_connect  axi_ad9361/dac_data_q0 dac_fifo/dout_data_1
+ad_connect  axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2
+ad_connect  axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2
+ad_connect  axi_ad9361/dac_data_i1 dac_fifo/dout_data_2
+ad_connect  axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3
+ad_connect  axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3
+ad_connect  axi_ad9361/dac_data_q1 dac_fifo/dout_data_3
 ad_connect  sys_cpu_clk util_ad9361_tdd_sync/clk
 ad_connect  sys_cpu_resetn util_ad9361_tdd_sync/rstn
 ad_connect  util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
@@ -334,7 +372,7 @@ ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
 ## 2R2T supports 1R1T as a run time option.
 ## 1R1T allows core to run at a lower rate (1/2 of 2R2T)
 
-set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361] 
+set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361]
 
 ## interface type - CMOS (1) or LVDS (0) (default is LVDS)
 ## CMOS allows core to run at a lower rate (1/2 of LVDS)

From 165ba76d9d8eafebbe0ed0aaa9bcddb5797a7518 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 18 Jan 2017 12:01:24 +0200
Subject: [PATCH 857/972] pzsdr1: Added FIFOs for DAC and ADC paths so that
 they work at l_clk or l_clk/2

---
 projects/pzsdr1/ccbox_lvds/Makefile      |  6 ++
 projects/pzsdr1/ccbrk_cmos/Makefile      |  6 ++
 projects/pzsdr1/ccbrk_cmos/system_bd.tcl |  3 +
 projects/pzsdr1/ccbrk_lvds/Makefile      |  6 ++
 projects/pzsdr1/ccusb_lvds/Makefile      |  6 ++
 projects/pzsdr1/common/pzsdr1_bd.tcl     | 78 ++++++++++++++++++------
 6 files changed, 85 insertions(+), 20 deletions(-)

diff --git a/projects/pzsdr1/ccbox_lvds/Makefile b/projects/pzsdr1/ccbox_lvds/Makefile
index 7384258d4..4f99f1cef 100644
--- a/projects/pzsdr1/ccbox_lvds/Makefile
+++ b/projects/pzsdr1/ccbox_lvds/Makefile
@@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -55,7 +57,9 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_i2s_adi clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -70,7 +74,9 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_i2s_adi
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr1/ccbrk_cmos/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile
index b15afc39a..77e805b1b 100644
--- a/projects/pzsdr1/ccbrk_cmos/Makefile
+++ b/projects/pzsdr1/ccbrk_cmos/Makefile
@@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -55,7 +57,9 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -70,7 +74,9 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_gpreg
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr1/ccbrk_cmos/system_bd.tcl b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
index 624697cbe..7a41991dd 100644
--- a/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
+++ b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
@@ -2,5 +2,8 @@
 source ../common/pzsdr1_bd.tcl
 source ../common/ccbrk_bd.tcl
 
+set_property -dict [list CONFIG.SEL_0_DIV {BYPASS}] $clkdiv
+set_property -dict [list CONFIG.SEL_1_DIV {BYPASS}] $clkdiv
+
 cfg_ad9361_interface CMOS
 
diff --git a/projects/pzsdr1/ccbrk_lvds/Makefile b/projects/pzsdr1/ccbrk_lvds/Makefile
index 66bf7abe5..02c1d8180 100644
--- a/projects/pzsdr1/ccbrk_lvds/Makefile
+++ b/projects/pzsdr1/ccbrk_lvds/Makefile
@@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -55,7 +57,9 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_gpreg clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -70,7 +74,9 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_gpreg
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr1/ccusb_lvds/Makefile b/projects/pzsdr1/ccusb_lvds/Makefile
index fa74174b0..04479da8d 100644
--- a/projects/pzsdr1/ccusb_lvds/Makefile
+++ b/projects/pzsdr1/ccusb_lvds/Makefile
@@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
 M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
 M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
+M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
 M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
 M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
 M_DEPS += ../../../library/util_upack/util_upack.xpr
 M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@@ -55,7 +57,9 @@ clean-all:clean
 	make -C ../../../library/axi_ad9361 clean
 	make -C ../../../library/axi_dmac clean
 	make -C ../../../library/axi_usb_fx3 clean
+	make -C ../../../library/util_clkdiv clean
 	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_rfifo clean
 	make -C ../../../library/util_tdd_sync clean
 	make -C ../../../library/util_upack clean
 	make -C ../../../library/util_wfifo clean
@@ -70,7 +74,9 @@ lib:
 	make -C ../../../library/axi_ad9361
 	make -C ../../../library/axi_dmac
 	make -C ../../../library/axi_usb_fx3
+	make -C ../../../library/util_clkdiv
 	make -C ../../../library/util_cpack
+	make -C ../../../library/util_rfifo
 	make -C ../../../library/util_tdd_sync
 	make -C ../../../library/util_upack
 	make -C ../../../library/util_wfifo
diff --git a/projects/pzsdr1/common/pzsdr1_bd.tcl b/projects/pzsdr1/common/pzsdr1_bd.tcl
index 000c24bb4..f955ed8e9 100644
--- a/projects/pzsdr1/common/pzsdr1_bd.tcl
+++ b/projects/pzsdr1/common/pzsdr1_bd.tcl
@@ -242,6 +242,21 @@ set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
 set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
 set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
 
+set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
+
+set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
+
+set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
+set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
+set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
+set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
+
+set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
+set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic
+
+set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
+set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic
+
 # connections
 
 ad_connect  sys_200m_clk axi_ad9361/delay_clk
@@ -253,11 +268,14 @@ ad_connect  up_enable axi_ad9361/up_enable
 ad_connect  up_txnrx axi_ad9361/up_txnrx
 ad_connect  axi_ad9361_clk util_ad9361_adc_fifo/din_clk
 ad_connect  axi_ad9361/rst util_ad9361_adc_fifo/din_rst
-ad_connect  sys_cpu_clk util_ad9361_adc_fifo/dout_clk
-ad_connect  sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
-ad_connect  sys_cpu_clk util_ad9361_adc_pack/adc_clk
-ad_connect  sys_cpu_reset util_ad9361_adc_pack/adc_rst
-ad_connect  sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  axi_ad9361_clk clkdiv/clk
+ad_connect  clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
+ad_connect  clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
+ad_connect  clkdiv/clk_out util_ad9361_adc_pack/adc_clk
+ad_connect  clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
+ad_connect  clkdiv_reset/slowest_sync_clk clkdiv/clk_out
+ad_connect  util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset
+ad_connect  util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn
 ad_connect  axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
 ad_connect  axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
 ad_connect  axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
@@ -287,23 +305,43 @@ ad_connect  util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
 ad_connect  util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
 ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
 ad_connect  util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
-ad_connect  axi_ad9361_clk util_ad9361_dac_upack/dac_clk
-ad_connect  axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
-ad_connect  util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
-ad_connect  util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
-ad_connect  util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
-ad_connect  util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
-ad_connect  util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
-ad_connect  util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
-ad_connect  util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
-ad_connect  util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
-ad_connect  util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
-ad_connect  util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
-ad_connect  util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
-ad_connect  util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
+ad_connect  axi_ad9361/adc_r1_mode concat_logic/In0
+ad_connect  axi_ad9361/dac_r1_mode concat_logic/In1
+ad_connect  concat_logic/dout clkdiv_sel_logic/Op1
+ad_connect  clkdiv/clk_sel clkdiv_sel_logic/Res
 ad_connect  util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
 ad_connect  util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
-ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
+ad_connect  clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
+ad_connect  axi_ad9361/dac_dunf dac_fifo/dout_unf
+ad_connect  dac_fifo/din_clk clkdiv/clk_out
+ad_connect  dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn
+ad_connect  axi_ad9361_clk dac_fifo/dout_clk
+ad_connect  dac_fifo/dout_rst axi_ad9361/rst
+ad_connect  util_ad9361_dac_upack/dac_clk clkdiv/clk_out
+ad_connect  dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0
+ad_connect  dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0
+ad_connect  dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0
+ad_connect  dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1
+ad_connect  dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1
+ad_connect  dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1
+ad_connect  dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2
+ad_connect  dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2
+ad_connect  dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2
+ad_connect  dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3
+ad_connect  dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3
+ad_connect  dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3
+ad_connect  axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0
+ad_connect  axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0
+ad_connect  axi_ad9361/dac_data_i0 dac_fifo/dout_data_0
+ad_connect  axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1
+ad_connect  axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1
+ad_connect  axi_ad9361/dac_data_q0 dac_fifo/dout_data_1
+ad_connect  axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2
+ad_connect  axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2
+ad_connect  axi_ad9361/dac_data_i1 dac_fifo/dout_data_2
+ad_connect  axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3
+ad_connect  axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3
+ad_connect  axi_ad9361/dac_data_q1 dac_fifo/dout_data_3
 ad_connect  sys_cpu_clk util_ad9361_tdd_sync/clk
 ad_connect  sys_cpu_resetn util_ad9361_tdd_sync/rstn
 ad_connect  util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync

From ecd152c90d35c4299d25b3c403579bf8a6a13c8b Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 18 Jan 2017 12:04:04 +0200
Subject: [PATCH 858/972] pzsdr1: ccbrk_cmos, fix clkdiv parameters

---
 projects/pzsdr1/ccbrk_cmos/system_bd.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/pzsdr1/ccbrk_cmos/system_bd.tcl b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
index 7a41991dd..52356bdca 100644
--- a/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
+++ b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl
@@ -2,8 +2,8 @@
 source ../common/pzsdr1_bd.tcl
 source ../common/ccbrk_bd.tcl
 
-set_property -dict [list CONFIG.SEL_0_DIV {BYPASS}] $clkdiv
-set_property -dict [list CONFIG.SEL_1_DIV {BYPASS}] $clkdiv
+set_property -dict [list CONFIG.SEL_0_DIV {2}] $clkdiv
+set_property -dict [list CONFIG.SEL_1_DIV {1}] $clkdiv
 
 cfg_ad9361_interface CMOS
 

From a7bd4e6e824d5864cb6e5d1fb3fe5a2e89d2523d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 19 Jan 2017 14:57:54 +0200
Subject: [PATCH 859/972] scripts/adi_ip: Update the adi_ip_properties process

  - Add a process, which automaticaly infer AXI memory mapped
interfaces (adi_ip_infer_mm_interfaces)
  - Add missign line breaks to the 'set_propery supported_families'
command
  - Fix the deletion of pre-infered memory maps
---
 library/scripts/adi_ip.tcl | 83 +++++++++++++++++++++-----------------
 1 file changed, 46 insertions(+), 37 deletions(-)

diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl
index a125b8fb4..9d5b5ebff 100644
--- a/library/scripts/adi_ip.tcl
+++ b/library/scripts/adi_ip.tcl
@@ -126,56 +126,65 @@ proc adi_ip_infer_streaming_interfaces {ip_name} {
 
 }
 
+proc adi_ip_infer_mm_interfaces {ip_name} {
+
+  ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
+
+}
+
 proc adi_ip_properties_lite {ip_name} {
 
   ipx::package_project -root_dir . \
     -vendor analog.com \
     -library user \
-    -taxonomy /Analog_Devices 
+    -taxonomy /Analog_Devices
 
   set_property vendor_display_name {Analog Devices} [ipx::current_core]
   set_property company_url {www.analog.com} [ipx::current_core]
 
   set_property supported_families {\
-    virtex7       Production
-    qvirtex7      Production
-    kintex7       Production
-    kintex7l      Production
-    qkintex7      Production
-    qkintex7l     Production
-    artix7        Production
-    artix7l       Production
-    aartix7       Production
-    qartix7       Production
-    zynq          Production
-    qzynq         Production
-    azynq         Production
-    virtexu       Production
-    kintexuplus   Production
-    zynquplus     Production
-    kintexu       Production
-    virtex7       Beta
-    qvirtex7      Beta
-    kintex7       Beta
-    kintex7l      Beta
-    qkintex7      Beta
-    qkintex7l     Beta
-    artix7        Beta
-    artix7l       Beta
-    aartix7       Beta
-    qartix7       Beta
-    zynq          Beta 
-    qzynq         Beta
-    azynq         Beta
-    virtexu       Beta
-    virtexuplus   Beta
-    kintexuplus   Beta
-    zynquplus     Beta
+    virtex7       Production \
+    qvirtex7      Production \
+    kintex7       Production \
+    kintex7l      Production \
+    qkintex7      Production \
+    qkintex7l     Production \
+    artix7        Production \
+    artix7l       Production \
+    aartix7       Production \
+    qartix7       Production \
+    zynq          Production \
+    qzynq         Production \
+    azynq         Production \
+    virtexu       Production \
+    kintexuplus   Production \
+    zynquplus     Production \
+    kintexu       Production \
+    virtex7       Beta \
+    qvirtex7      Beta \
+    kintex7       Beta \
+    kintex7l      Beta \
+    qkintex7      Beta \
+    qkintex7l     Beta \
+    artix7        Beta \
+    artix7l       Beta \
+    aartix7       Beta \
+    qartix7       Beta \
+    zynq          Beta \
+    qzynq         Beta \
+    azynq         Beta \
+    virtexu       Beta \
+    virtexuplus   Beta \
+    kintexuplus   Beta \
+    zynquplus     Beta \
     kintexu       Beta}\
   [ipx::current_core]
 
-  ipx::remove_all_bus_interface -quiet [ipx::current_core]
-  ipx::remove_all_address_block -quiet [ipx::get_memory_maps * -of_objects [ipx::current_core]]
+  ipx::remove_all_bus_interface [ipx::current_core]
+  set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
+  foreach map $memory_maps {
+    ipx::remove_memory_map [lindex $map 2] [ipx::current_core ]
+  }
 }
 
 proc adi_set_ports_dependency {port_prefix dependency} {

From 7a7a294865df55a6b1fde64f03913a663894a433 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 19 Jan 2017 15:09:07 +0200
Subject: [PATCH 860/972] axi_dmac: Fix memory map infer issues

Define an address space reference to the m_dest_axi and
m_src_axi interfaces.
---
 library/axi_dmac/axi_dmac_ip.tcl | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl
index 877994bd4..e3f3ff153 100644
--- a/library/axi_dmac/axi_dmac_ip.tcl
+++ b/library/axi_dmac/axi_dmac_ip.tcl
@@ -27,7 +27,7 @@ adi_ip_files axi_dmac [list \
   "bd/bd.tcl" ]
 
 adi_ip_properties axi_dmac
-adi_ip_infer_streaming_interfaces axi_dmac
+adi_ip_infer_mm_interfaces axi_dmac
 adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl"
 adi_ip_bd axi_dmac "bd/bd.tcl"
 
@@ -104,6 +104,13 @@ foreach p $dummy_axi_ports {
 	adi_set_ports_dependency $p "0"
 }
 
+set_property master_address_space_ref m_dest_axi \
+    [ipx::get_bus_interfaces m_dest_axi \
+    -of_objects [ipx::current_core]]
+set_property master_address_space_ref m_src_axi \
+    [ipx::get_bus_interfaces m_src_axi \
+    -of_objects [ipx::current_core]]
+
 adi_add_bus "fifo_wr" "slave" \
 	"analog.com:interface:fifo_wr_rtl:1.0" \
 	"analog.com:interface:fifo_wr:1.0" \

From d3ed417f49d8e6b2cbf11a6b7dc575010ebbd1b3 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 19 Jan 2017 15:16:04 +0200
Subject: [PATCH 861/972] axi_adxcvr: Update the packaging script to fix infer
 mm issues

  - Change the clock and reset port name of the AXI slave interface
to s_axi_aclk and s_axi_aresetn. This way we can use the adi_ip_properties
process to infer the interface.
  - Define an address space reference to the m_axi interface.
---
 library/xilinx/axi_adxcvr/axi_adxcvr.v      |  4 +-
 library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl | 66 ++-------------------
 2 files changed, 7 insertions(+), 63 deletions(-)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v
index 8d4834469..af417379d 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v
@@ -456,8 +456,8 @@ module axi_adxcvr (
   input   [15:0]  up_ch_rdata_15,
   input           up_ch_ready_15,
 
-  input           axi_clk,
-  input           axi_aresetn,
+  input           s_axi_aclk,
+  input           s_axi_aresetn,
   output          up_status,
   output          up_pll_rst,
 
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
index f7c36b090..e38c8b3ae 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -12,70 +12,14 @@ adi_ip_files axi_adxcvr [list \
   "axi_adxcvr_mstatus.v" \
   "axi_adxcvr.v" ]
 
-adi_ip_properties_lite axi_adxcvr
-
-ipx::remove_all_bus_interface [ipx::current_core]
+adi_ip_properties axi_adxcvr
+adi_ip_infer_mm_interfaces axi_adxcvr
 
 set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
 
-ipx::infer_bus_interface {\
-  s_axi_awvalid \
-  s_axi_awaddr \
-  s_axi_awprot \
-  s_axi_awready \
-  s_axi_wvalid \
-  s_axi_wdata \
-  s_axi_wstrb \
-  s_axi_wready \
-  s_axi_bvalid \
-  s_axi_bresp \
-  s_axi_bready \
-  s_axi_arvalid \
-  s_axi_araddr \
-  s_axi_arprot \
-  s_axi_arready \
-  s_axi_rvalid \
-  s_axi_rdata \
-  s_axi_rresp \
-  s_axi_rready} \
-xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
-
-ipx::infer_bus_interface {\
-  m_axi_awvalid \
-  m_axi_awaddr \
-  m_axi_awprot \
-  m_axi_awready \
-  m_axi_wvalid \
-  m_axi_wdata \
-  m_axi_wstrb \
-  m_axi_wready \
-  m_axi_bvalid \
-  m_axi_bresp \
-  m_axi_bready \
-  m_axi_arvalid \
-  m_axi_araddr \
-  m_axi_arprot \
-  m_axi_arready \
-  m_axi_rvalid \
-  m_axi_rdata \
-  m_axi_rresp \
-  m_axi_rready} \
-xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
-
-ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
-ipx::infer_bus_interface axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
-
-ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
-  -of_objects [ipx::current_core]]
-set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-  -of_objects [ipx::get_bus_interfaces axi_clk \
-  -of_objects [ipx::current_core]]]
-
-ipx::add_memory_map {s_axi} [ipx::current_core]
-set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
-ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
-set_property range {4096} [ipx::get_address_blocks axi_lite \
-  -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
+set_property master_address_space_ref m_axi \
+    [ipx::get_bus_interfaces m_axi \
+    -of_objects [ipx::current_core]]
 
 for {set n 0} {$n < 16} {incr n} {
 

From 62792ddaed7147a02afc549e3d07fd18ed4209a0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 19 Jan 2017 15:23:03 +0200
Subject: [PATCH 862/972] adrv9371x: Change the axi_adxcvr cores addresses

Because the S_AXI interface of the axi_adxcvr core was infered
using the process adi_ip_properties, the interface address range
has changed from 4k to 64k. As a result, all the addresses of
the axi_adxcvr cores were changed and realigned.
---
 projects/adrv9371x/common/adrv9371x_bd.tcl | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index 0e375d72f..c655a8c58 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -260,15 +260,15 @@ ad_connect  sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn
 # interconnect (cpu)
 
 ad_cpu_interconnect 0x44A00000 axi_ad9371_core
-ad_cpu_interconnect 0x44A60000 axi_ad9371_tx_xcvr
+ad_cpu_interconnect 0x44A80000 axi_ad9371_tx_xcvr
 ad_cpu_interconnect 0x43C00000 axi_ad9371_tx_clkgen
 ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma
-ad_cpu_interconnect 0x44A61000 axi_ad9371_rx_xcvr
+ad_cpu_interconnect 0x44A60000 axi_ad9371_rx_xcvr
 ad_cpu_interconnect 0x43C10000 axi_ad9371_rx_clkgen
 ad_cpu_interconnect 0x44A91000 axi_ad9371_rx_jesd
 ad_cpu_interconnect 0x7c400000 axi_ad9371_rx_dma
-ad_cpu_interconnect 0x44A62000 axi_ad9371_rx_os_xcvr
+ad_cpu_interconnect 0x44A70000 axi_ad9371_rx_os_xcvr
 ad_cpu_interconnect 0x43C20000 axi_ad9371_rx_os_clkgen
 ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd
 ad_cpu_interconnect 0x7c440000 axi_ad9371_rx_os_dma

From 57bd6acd0fa68720fa705e3619125f7770aa66f2 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 19 Jan 2017 15:27:31 +0200
Subject: [PATCH 863/972] library: Update make file

---
 library/Makefile | 2 --
 1 file changed, 2 deletions(-)

diff --git a/library/Makefile b/library/Makefile
index 7b6ae54d3..56c816b4e 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -64,7 +64,6 @@ clean:
 	make -C util_fir_int clean
 	make -C util_gmii_to_rgmii clean
 	make -C util_i2c_mixer clean
-	make -C util_jesd_gt clean
 	make -C util_mfifo clean
 	make -C util_pmod_adc clean
 	make -C util_pmod_fmeter clean
@@ -139,7 +138,6 @@ lib:
 	-make -C util_gmii_to_rgmii
 	-make -C util_gtlb
 	-make -C util_i2c_mixer
-	-make -C util_jesd_gt
 	-make -C util_mfifo
 	-make -C util_pmod_adc
 	-make -C util_pmod_fmeter

From 746b97dd96e79f51c2ec3071098ca2185c3a3ebc Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 19 Jan 2017 15:46:16 +0200
Subject: [PATCH 864/972] xilin/axi_adxcvr: Fix clock and reset nets[C

---
 library/xilinx/axi_adxcvr/axi_adxcvr.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v
index af417379d..c6055e006 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v
@@ -661,8 +661,8 @@ module axi_adxcvr (
 
   // channel broadcast
 
-  assign up_rstn = axi_aresetn;
-  assign up_clk = axi_clk;
+  assign up_rstn = s_axi_aresetn;
+  assign up_clk = s_axi_aclk;
 
   assign up_cm_sel_0 = up_cm_sel;
   assign up_cm_enb_0 = up_cm_enb;

From afcd11da879479ca0bead11efb2b79884f06fe32 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 19 Jan 2017 12:40:26 -0500
Subject: [PATCH 865/972] adxcvr- add parameters for xcvr config

---
 library/xilinx/axi_adxcvr/axi_adxcvr.v    | 28 +++++++++++++++--------
 library/xilinx/axi_adxcvr/axi_adxcvr_up.v | 23 ++++++++++++-------
 2 files changed, 33 insertions(+), 18 deletions(-)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v
index 8d4834469..a41e89421 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v
@@ -38,7 +38,19 @@
 
 `timescale 1ns/1ps
 
-module axi_adxcvr (
+module axi_adxcvr #(
+
+  // parameters
+
+  parameter   integer ID = 0,
+  parameter   integer NUM_OF_LANES = 8,
+  parameter   integer GTH_OR_GTX_N = 0,
+  parameter   integer TX_OR_RX_N = 0,
+  parameter   integer QPLL_ENABLE = 1,
+  parameter           LPM_OR_DFE_N = 1,
+  parameter   [ 2:0]  RATE = 3'd0,
+  parameter   [ 1:0]  SYS_CLK_SEL = 2'd3,
+  parameter   [ 2:0]  OUT_CLK_SEL = 3'd4) (
 
   output  [ 7:0]  up_cm_sel_0,
   output          up_cm_enb_0,
@@ -501,14 +513,6 @@ module axi_adxcvr (
   input   [ 1:0]  m_axi_rresp,
   output          m_axi_rready);
 
-  // parameters
-
-  parameter   integer ID = 0;
-  parameter   integer NUM_OF_LANES = 8;
-  parameter   integer GTH_OR_GTX_N = 0;
-  parameter   integer TX_OR_RX_N = 0;
-  parameter   integer QPLL_ENABLE = 1;
-
   // internal signals
 
   wire    [ 7:0]  up_cm_sel;
@@ -1788,7 +1792,11 @@ module axi_adxcvr (
   axi_adxcvr_up #(
     .ID (ID),
     .TX_OR_RX_N (TX_OR_RX_N),
-    .QPLL_ENABLE (QPLL_ENABLE))
+    .QPLL_ENABLE (QPLL_ENABLE),
+    .LPM_OR_DFE_N (LPM_OR_DFE_N),
+    .RATE (RATE),
+    .SYS_CLK_SEL (SYS_CLK_SEL),
+    .OUT_CLK_SEL (OUT_CLK_SEL))
   i_up (
     .up_cm_sel (up_cm_sel),
     .up_cm_enb (up_cm_enb),
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
index 80acfb12b..a07219791 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
@@ -37,7 +37,17 @@
 
 `timescale 1ns/100ps
 
-module axi_adxcvr_up (
+module axi_adxcvr_up #(
+
+  // parameters
+
+  parameter   integer ID = 0,
+  parameter   integer TX_OR_RX_N = 0,
+  parameter   integer QPLL_ENABLE = 1,
+  parameter           LPM_OR_DFE_N = 1,
+  parameter   [ 2:0]  RATE = 3'd0,
+  parameter   [ 1:0]  SYS_CLK_SEL = 2'd3,
+  parameter   [ 2:0]  OUT_CLK_SEL = 3'd4) (
 
   // common
 
@@ -104,9 +114,6 @@ module axi_adxcvr_up (
   // parameters
 
   localparam  [31:0]  VERSION = 32'h00100161;
-  parameter   integer ID = 0;
-  parameter   integer TX_OR_RX_N = 0;
-  parameter   integer QPLL_ENABLE = 1;
 
   // internal registers
 
@@ -221,10 +228,10 @@ module axi_adxcvr_up (
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_lpm_dfe_n <= 'd0;
-      up_rate <= 'd0;
-      up_sys_clk_sel <= 'd0;
-      up_out_clk_sel <= 'd0;
+      up_lpm_dfe_n <= LPM_OR_DFE_N;
+      up_rate <= RATE;
+      up_sys_clk_sel <= SYS_CLK_SEL;
+      up_out_clk_sel <= OUT_CLK_SEL;
     end else begin
       if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin
         up_lpm_dfe_n <= up_wdata[12];

From 661413627f0365cd08d9064c15fbbb5ebcfe29b5 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 20 Jan 2017 15:55:33 -0500
Subject: [PATCH 866/972] daq3- round about way to avoid ip getting locked

---
 projects/daq3/zc706/system_constr.xdc  | 11 +++++++----
 projects/daq3/zc706/system_project.tcl |  6 ++----
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/projects/daq3/zc706/system_constr.xdc b/projects/daq3/zc706/system_constr.xdc
index 3728fe6f9..1cfd829a1 100644
--- a/projects/daq3/zc706/system_constr.xdc
+++ b/projects/daq3/zc706/system_constr.xdc
@@ -52,8 +52,11 @@ set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
 
 # clocks
 
-create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
-create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_ref_clk   -period  1.60 [get_ports tx_ref_clk_p]
+create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
+create_clock -name tx_div_clk   -period  3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
+
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
 
diff --git a/projects/daq3/zc706/system_project.tcl b/projects/daq3/zc706/system_project.tcl
index d36b0079c..281ddab91 100644
--- a/projects/daq3/zc706/system_project.tcl
+++ b/projects/daq3/zc706/system_project.tcl
@@ -14,10 +14,8 @@ adi_project_files daq3_zc706 [list \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
-set_property part "xc7z045ffg900-3" [current_project]
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
+set_property part "xc7z045ffg900-3" [get_runs synth_1]
+set_property part "xc7z045ffg900-3" [get_runs impl_1]
 adi_project_run daq3_zc706
 
 

From a2b2ebbed247e7c9f950ab2527fb1025ba603538 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Sat, 21 Jan 2017 20:54:21 -0500
Subject: [PATCH 867/972] ad_lvds_in- ultrascale/ultrascale+ sim device mess

---
 library/xilinx/common/ad_lvds_in.v | 151 +++++++++++++++++++----------
 1 file changed, 100 insertions(+), 51 deletions(-)

diff --git a/library/xilinx/common/ad_lvds_in.v b/library/xilinx/common/ad_lvds_in.v
index b6f6ef257..4e8530ac7 100644
--- a/library/xilinx/common/ad_lvds_in.v
+++ b/library/xilinx/common/ad_lvds_in.v
@@ -34,68 +34,49 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
-module ad_lvds_in (
-
-  // data interface
-
-  rx_clk,
-  rx_data_in_p,
-  rx_data_in_n,
-  rx_data_p,
-  rx_data_n,
-
-  // delay-data interface
-
-  up_clk,
-  up_dld,
-  up_dwdata,
-  up_drdata,
-
-  // delay-cntrl interface
-
-  delay_clk,
-  delay_rst,
-  delay_locked);
+module ad_lvds_in #(
 
   // parameters
 
-  parameter   SINGLE_ENDED = 0;
-  parameter   DEVICE_TYPE = 0;
-  parameter   IODELAY_CTRL = 0;
-  parameter   IODELAY_GROUP = "dev_if_delay_group";
-  localparam  VIRTEX7 = 0;
-  localparam  VIRTEX6 = 1;
-  localparam  ULTRASCALE = 2;
+  parameter   SINGLE_ENDED = 0,
+  parameter   DEVICE_TYPE = 0,
+  parameter   IODELAY_CTRL = 0,
+  parameter   IODELAY_GROUP = "dev_if_delay_group") (
 
   // data interface
 
-  input               rx_clk;
-  input               rx_data_in_p;
-  input               rx_data_in_n;
-  output              rx_data_p;
-  output              rx_data_n;
+  input               rx_clk,
+  input               rx_data_in_p,
+  input               rx_data_in_n,
+  output              rx_data_p,
+  output              rx_data_n,
 
   // delay-data interface
 
-  input               up_clk;
-  input               up_dld;
-  input       [ 4:0]  up_dwdata;
-  output      [ 4:0]  up_drdata;
+  input               up_clk,
+  input               up_dld,
+  input       [ 4:0]  up_dwdata,
+  output      [ 4:0]  up_drdata,
 
   // delay-cntrl interface
 
-  input               delay_clk;
-  input               delay_rst;
-  output              delay_locked;
+  input               delay_clk,
+  input               delay_rst,
+  output              delay_locked);
+
+  // internal parameters
+
+  localparam  VIRTEX7 = 0;
+  localparam  VIRTEX6 = 1;
+  localparam  ULTRASCALE_PLUS = 2;
+  localparam  ULTRASCALE = 3;
 
   // internal registers
 
-  reg                 rx_data_n;
+  reg                 rx_data_n_d = 'd0;
 
   // internal signals
 
@@ -107,21 +88,37 @@ module ad_lvds_in (
   // delay controller
 
   generate
-  if (IODELAY_CTRL == 1) begin
-  if (DEVICE_TYPE == ULTRASCALE) begin
+  if ((IODELAY_CTRL == 1) && (DEVICE_TYPE == ULTRASCALE_PLUS)) begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
   IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl (
     .RST (delay_rst),
     .REFCLK (delay_clk),
     .RDY (delay_locked));
-  end else begin
+  end
+  endgenerate
+
+  generate
+  if ((IODELAY_CTRL == 1) && (DEVICE_TYPE == ULTRASCALE)) begin
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl (
+    .RST (delay_rst),
+    .REFCLK (delay_clk),
+    .RDY (delay_locked));
+  end
+  endgenerate
+
+  generate
+  if ((IODELAY_CTRL == 1) && ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6))) begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
   IDELAYCTRL i_delay_ctrl (
     .RST (delay_rst),
     .REFCLK (delay_clk),
     .RDY (delay_locked));
   end
-  end else begin
+  endgenerate
+
+  generate
+  if (IODELAY_CTRL == 0) begin
   assign delay_locked = 1'b1;
   end
   endgenerate
@@ -141,6 +138,8 @@ module ad_lvds_in (
   end
   endgenerate
 
+  // idelay
+
   generate
   if (DEVICE_TYPE == VIRTEX6) begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
@@ -204,7 +203,7 @@ module ad_lvds_in (
   assign up_drdata = up_drdata_s[8:4];
   (* IODELAY_GROUP = IODELAY_GROUP *)
   IDELAYE3 #(
-    .SIM_DEVICE ("ULTRASCALE_PLUS_ES1"),
+    .SIM_DEVICE ("ULTRASCALE"),
     .DELAY_SRC ("IDATAIN"),
     .DELAY_TYPE ("VAR_LOAD"),
     .REFCLK_FREQUENCY (200.0),
@@ -227,6 +226,36 @@ module ad_lvds_in (
   end
   endgenerate
 
+  generate
+  if (DEVICE_TYPE == ULTRASCALE_PLUS) begin
+  assign up_drdata = up_drdata_s[8:4];
+  (* IODELAY_GROUP = IODELAY_GROUP *)
+  IDELAYE3 #(
+    .SIM_DEVICE ("ULTRASCALE_PLUS_ES1"),
+    .DELAY_SRC ("IDATAIN"),
+    .DELAY_TYPE ("VAR_LOAD"),
+    .REFCLK_FREQUENCY (200.0),
+    .DELAY_FORMAT ("COUNT"))
+  i_rx_data_idelay (
+    .CASC_RETURN (1'b0),
+    .CASC_IN (1'b0),
+    .CASC_OUT (),
+    .CE (1'b0),
+    .CLK (up_clk),
+    .INC (1'b0),
+    .LOAD (up_dld),
+    .CNTVALUEIN ({up_dwdata, 4'd0}),
+    .CNTVALUEOUT (up_drdata_s),
+    .DATAIN (1'b0),
+    .IDATAIN (rx_data_ibuf_s),
+    .DATAOUT (rx_data_idelay_s),
+    .RST (1'b0),
+    .EN_VTC (~up_dld));
+  end
+  endgenerate
+
+  // iddr
+
   generate
   if (DEVICE_TYPE == ULTRASCALE) begin
   IDDRE1 #(
@@ -238,7 +267,25 @@ module ad_lvds_in (
     .D (rx_data_idelay_s),
     .Q1 (rx_data_p),
     .Q2 (rx_data_n_s));
-  end else begin
+  end
+  endgenerate
+
+  generate
+  if (DEVICE_TYPE == ULTRASCALE_PLUS) begin
+  IDDRE1 #(
+    .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
+  i_rx_data_iddr (
+    .R (1'b0),
+    .C (rx_clk),
+    .CB (~rx_clk),
+    .D (rx_data_idelay_s),
+    .Q1 (rx_data_p),
+    .Q2 (rx_data_n_s));
+  end
+  endgenerate
+
+  generate
+  if ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6)) begin
   IDDR #(
     .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
     .INIT_Q1 (1'b0),
@@ -255,8 +302,10 @@ module ad_lvds_in (
   end
   endgenerate
 
+  assign rx_data_n = rx_data_n_d;
+
   always @(posedge rx_clk) begin
-    rx_data_n <= rx_data_n_s;
+    rx_data_n_d <= rx_data_n_s;
   end
 
 endmodule

From be1328c55bd5729b12d926a06a4d8c78c94ea885 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 23 Jan 2017 10:14:09 -0500
Subject: [PATCH 868/972] kcu105- added missing ethernet configurations

---
 projects/common/kcu105/kcu105_system_bd.tcl | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl
index 28a967dec..29abe3d87 100644
--- a/projects/common/kcu105/kcu105_system_bd.tcl
+++ b/projects/common/kcu105/kcu105_system_bd.tcl
@@ -95,6 +95,10 @@ set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethe
 set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet
 set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet
 set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet
+set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
+set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
+set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet
+set_property -dict [list CONFIG.RXMEM {8k}] $axi_ethernet
 
 set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
 set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma

From c8b638e182dc802b44c3c56cc3567b785a727673 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 23 Jan 2017 10:31:45 -0500
Subject: [PATCH 869/972] ad9152- add prbs generators

---
 library/axi_ad9152/axi_ad9152_channel.v | 438 ++++++++----------------
 1 file changed, 146 insertions(+), 292 deletions(-)

diff --git a/library/axi_ad9152/axi_ad9152_channel.v b/library/axi_ad9152/axi_ad9152_channel.v
index 3d77dcaba..56f599594 100644
--- a/library/axi_ad9152/axi_ad9152_channel.v
+++ b/library/axi_ad9152/axi_ad9152_channel.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -104,8 +102,6 @@ module axi_ad9152_channel (
   reg     [63:0]  dac_data = 'd0;
   reg     [63:0]  dac_pn7_data = 'd0;
   reg     [63:0]  dac_pn15_data = 'd0;
-  reg     [63:0]  dac_pn23_data = 'd0;
-  reg     [63:0]  dac_pn31_data = 'd0;
   reg     [15:0]  dac_dds_phase_0_0 = 'd0;
   reg     [15:0]  dac_dds_phase_0_1 = 'd0;
   reg     [15:0]  dac_dds_phase_1_0 = 'd0;
@@ -133,312 +129,174 @@ module axi_ad9152_channel (
   wire    [15:0]  dac_pat_data_1_s;
   wire    [15:0]  dac_pat_data_2_s;
   wire    [ 3:0]  dac_data_sel_s;
+  wire    [63:0]  dac_pn7_data_i_s;
+  wire    [63:0]  dac_pn15_data_i_s;
+  wire    [63:0]  dac_pn7_data_s;
+  wire    [63:0]  dac_pn15_data_s;
 
-  // pn7 function
+  // PN7 function
 
   function [63:0] pn7;
-    input [63:0] din;
+    input [7:0] din;
     reg   [63:0] dout;
     begin
-      dout[63] = din[ 7] ^ din[ 6];
-      dout[62] = din[ 6] ^ din[ 5];
-      dout[61] = din[ 5] ^ din[ 4];
-      dout[60] = din[ 4] ^ din[ 3];
-      dout[59] = din[ 3] ^ din[ 2];
-      dout[58] = din[ 2] ^ din[ 1];
-      dout[57] = din[ 1] ^ din[ 0];
-      dout[56] = din[ 0] ^ din[ 7] ^ din[ 6];
-      dout[55] = din[ 7] ^ din[ 5];
-      dout[54] = din[ 6] ^ din[ 4];
-      dout[53] = din[ 5] ^ din[ 3];
-      dout[52] = din[ 4] ^ din[ 2];
-      dout[51] = din[ 3] ^ din[ 1];
-      dout[50] = din[ 2] ^ din[ 0];
-      dout[49] = din[ 1] ^ din[ 7] ^ din[ 6];
-      dout[48] = din[ 0] ^ din[ 6] ^ din[ 5];
-      dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
-      dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
-      dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
-      dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
-      dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
-      dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6];
-      dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5];
-      dout[40] = din[ 0] ^ din[ 7] ^ din[ 4];
-      dout[39] = din[ 7] ^ din[ 3];
-      dout[38] = din[ 6] ^ din[ 2];
-      dout[37] = din[ 5] ^ din[ 1];
-      dout[36] = din[ 4] ^ din[ 0];
-      dout[35] = din[ 3] ^ din[ 7] ^ din[ 6];
-      dout[34] = din[ 2] ^ din[ 6] ^ din[ 5];
-      dout[33] = din[ 1] ^ din[ 5] ^ din[ 4];
-      dout[32] = din[ 0] ^ din[ 4] ^ din[ 3];
-      dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2];
-      dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
-      dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
-      dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6];
-      dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5];
-      dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4];
-      dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3];
-      dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
-      dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
-      dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
-      dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6];
-      dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
-      dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4];
-      dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3];
-      dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
-      dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1];
-      dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
-      dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7];
-      dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2];
-      dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1];
-      dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0];
-      dout[10] = din[ 0] ^ din[ 1] ^ din[ 7];
-      dout[ 9] = din[ 7] ^ din[ 0];
-      dout[ 8] = din[ 7];
-      dout[ 7] = din[ 6];
-      dout[ 6] = din[ 5];
-      dout[ 5] = din[ 4];
-      dout[ 4] = din[ 3];
-      dout[ 3] = din[ 2];
-      dout[ 2] = din[ 1];
-      dout[ 1] = din[ 0];
-      dout[ 0] = din[ 7] ^ din[ 6];
+      dout[15] = din[ 6] ^ din[ 5];
+      dout[14] = din[ 5] ^ din[ 4];
+      dout[13] = din[ 4] ^ din[ 3];
+      dout[12] = din[ 3] ^ din[ 2];
+      dout[11] = din[ 2] ^ din[ 1];
+      dout[10] = din[ 1] ^ din[ 0];
+      dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5];
+      dout[ 8] = din[ 6] ^ din[ 4];
+      dout[ 7] = din[ 5] ^ din[ 3];
+      dout[ 6] = din[ 4] ^ din[ 2];
+      dout[ 5] = din[ 3] ^ din[ 1];
+      dout[ 4] = din[ 2] ^ din[ 0];
+      dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5];
+      dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4];
+      dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
+      dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
+      dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
+      dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
+      dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
+      dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
+      dout[27] = din[ 0] ^ din[ 6] ^ din[ 3];
+      dout[26] = din[ 6] ^ din[ 2];
+      dout[25] = din[ 5] ^ din[ 1];
+      dout[24] = din[ 4] ^ din[ 0];
+      dout[23] = din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[22] = din[ 2] ^ din[ 5] ^ din[ 4];
+      dout[21] = din[ 1] ^ din[ 4] ^ din[ 3];
+      dout[20] = din[ 0] ^ din[ 3] ^ din[ 2];
+      dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
+      dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
+      dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
+      dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
+      dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
+      dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
+      dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
+      dout[43] = din[ 1] ^ din[ 3] ^ din[ 6];
+      dout[42] = din[ 0] ^ din[ 5] ^ din[ 2];
+      dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
+      dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
+      dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
+      dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
+      dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
+      dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
+      dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
+      dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
+      dout[33] = din[ 0] ^ din[ 2] ^ din[ 6];
+      dout[32] = din[ 6] ^ din[ 1];
+      dout[63] = din[ 5] ^ din[ 0];
+      dout[62] = din[ 4] ^ din[ 6] ^ din[ 5];
+      dout[61] = din[ 3] ^ din[ 5] ^ din[ 4];
+      dout[60] = din[ 2] ^ din[ 4] ^ din[ 3];
+      dout[59] = din[ 1] ^ din[ 3] ^ din[ 2];
+      dout[58] = din[ 0] ^ din[ 2] ^ din[ 1];
+      dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
+      dout[56] = din[ 0] ^ din[ 4] ^ din[ 6];
+      dout[55] = din[ 6] ^ din[ 3];
+      dout[54] = din[ 5] ^ din[ 2];
+      dout[53] = din[ 4] ^ din[ 1];
+      dout[52] = din[ 3] ^ din[ 0];
+      dout[51] = din[ 2] ^ din[ 6] ^ din[ 5];
+      dout[50] = din[ 1] ^ din[ 5] ^ din[ 4];
+      dout[49] = din[ 0] ^ din[ 4] ^ din[ 3];
+      dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
       pn7 = dout;
     end
   endfunction
 
-  // pn15 function
+  // PN15 function
 
   function [63:0] pn15;
-    input [63:0] din;
+    input [15:0] din;
     reg   [63:0] dout;
     begin
-      dout[63] = din[15] ^ din[14];
-      dout[62] = din[14] ^ din[13];
-      dout[61] = din[13] ^ din[12];
-      dout[60] = din[12] ^ din[11];
-      dout[59] = din[11] ^ din[10];
-      dout[58] = din[10] ^ din[ 9];
-      dout[57] = din[ 9] ^ din[ 8];
-      dout[56] = din[ 8] ^ din[ 7];
-      dout[55] = din[ 7] ^ din[ 6];
-      dout[54] = din[ 6] ^ din[ 5];
-      dout[53] = din[ 5] ^ din[ 4];
-      dout[52] = din[ 4] ^ din[ 3];
-      dout[51] = din[ 3] ^ din[ 2];
-      dout[50] = din[ 2] ^ din[ 1];
-      dout[49] = din[ 1] ^ din[ 0];
-      dout[48] = din[ 0] ^ din[15] ^ din[14];
-      dout[47] = din[15] ^ din[13];
-      dout[46] = din[14] ^ din[12];
-      dout[45] = din[13] ^ din[11];
-      dout[44] = din[12] ^ din[10];
-      dout[43] = din[11] ^ din[ 9];
-      dout[42] = din[10] ^ din[ 8];
-      dout[41] = din[ 9] ^ din[ 7];
-      dout[40] = din[ 8] ^ din[ 6];
-      dout[39] = din[ 7] ^ din[ 5];
-      dout[38] = din[ 6] ^ din[ 4];
-      dout[37] = din[ 5] ^ din[ 3];
-      dout[36] = din[ 4] ^ din[ 2];
-      dout[35] = din[ 3] ^ din[ 1];
-      dout[34] = din[ 2] ^ din[ 0];
-      dout[33] = din[ 1] ^ din[15] ^ din[14];
-      dout[32] = din[ 0] ^ din[14] ^ din[13];
-      dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12];
-      dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11];
-      dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10];
-      dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
-      dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
-      dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
-      dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
-      dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
-      dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
-      dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
-      dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
-      dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
-      dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
-      dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14];
-      dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13];
-      dout[16] = din[ 0] ^ din[15] ^ din[12];
-      dout[15] = din[15] ^ din[11];
-      dout[14] = din[14] ^ din[10];
-      dout[13] = din[13] ^ din[ 9];
-      dout[12] = din[12] ^ din[ 8];
-      dout[11] = din[11] ^ din[ 7];
-      dout[10] = din[10] ^ din[ 6];
-      dout[ 9] = din[ 9] ^ din[ 5];
-      dout[ 8] = din[ 8] ^ din[ 4];
-      dout[ 7] = din[ 7] ^ din[ 3];
-      dout[ 6] = din[ 6] ^ din[ 2];
-      dout[ 5] = din[ 5] ^ din[ 1];
-      dout[ 4] = din[ 4] ^ din[ 0];
-      dout[ 3] = din[ 3] ^ din[15] ^ din[14];
-      dout[ 2] = din[ 2] ^ din[14] ^ din[13];
-      dout[ 1] = din[ 1] ^ din[13] ^ din[12];
-      dout[ 0] = din[ 0] ^ din[12] ^ din[11];
+      dout[15] = din[14] ^ din[13];
+      dout[14] = din[13] ^ din[12];
+      dout[13] = din[12] ^ din[11];
+      dout[12] = din[11] ^ din[10];
+      dout[11] = din[10] ^ din[ 9];
+      dout[10] = din[ 9] ^ din[ 8];
+      dout[ 9] = din[ 8] ^ din[ 7];
+      dout[ 8] = din[ 7] ^ din[ 6];
+      dout[ 7] = din[ 6] ^ din[ 5];
+      dout[ 6] = din[ 5] ^ din[ 4];
+      dout[ 5] = din[ 4] ^ din[ 3];
+      dout[ 4] = din[ 3] ^ din[ 2];
+      dout[ 3] = din[ 2] ^ din[ 1];
+      dout[ 2] = din[ 1] ^ din[ 0];
+      dout[ 1] = din[ 0] ^ din[14] ^ din[13];
+      dout[ 0] = din[14] ^ din[12];
+      dout[31] = din[13] ^ din[11];
+      dout[30] = din[12] ^ din[10];
+      dout[29] = din[11] ^ din[ 9];
+      dout[28] = din[10] ^ din[ 8];
+      dout[27] = din[ 9] ^ din[ 7];
+      dout[26] = din[ 8] ^ din[ 6];
+      dout[25] = din[ 7] ^ din[ 5];
+      dout[24] = din[ 6] ^ din[ 4];
+      dout[23] = din[ 5] ^ din[ 3];
+      dout[22] = din[ 4] ^ din[ 2];
+      dout[21] = din[ 3] ^ din[ 1];
+      dout[20] = din[ 2] ^ din[ 0];
+      dout[19] = din[ 1] ^ din[14] ^ din[13];
+      dout[18] = din[ 0] ^ din[13] ^ din[12];
+      dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11];
+      dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10];
+      dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
+      dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
+      dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
+      dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
+      dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
+      dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
+      dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
+      dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
+      dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
+      dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
+      dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
+      dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
+      dout[35] = din[ 0] ^ din[14] ^ din[11];
+      dout[34] = din[14] ^ din[10];
+      dout[33] = din[13] ^ din[ 9];
+      dout[32] = din[12] ^ din[ 8];
+      dout[63] = din[11] ^ din[ 7];
+      dout[62] = din[10] ^ din[ 6];
+      dout[61] = din[ 9] ^ din[ 5];
+      dout[60] = din[ 8] ^ din[ 4];
+      dout[59] = din[ 7] ^ din[ 3];
+      dout[58] = din[ 6] ^ din[ 2];
+      dout[57] = din[ 5] ^ din[ 1];
+      dout[56] = din[ 4] ^ din[ 0];
+      dout[55] = din[ 3] ^ din[14] ^ din[13];
+      dout[54] = din[ 2] ^ din[13] ^ din[12];
+      dout[53] = din[ 1] ^ din[12] ^ din[11];
+      dout[52] = din[ 0] ^ din[11] ^ din[10];
+      dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
+      dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
+      dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
+      dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
       pn15 = dout;
     end
   endfunction
 
-  // pn23 function
+  assign dac_pn7_data_i_s  = ~dac_pn7_data;
+  assign dac_pn15_data_i_s = ~dac_pn15_data;
 
-  function [63:0] pn23;
-    input [63:0] din;
-    reg   [63:0] dout;
-    begin
-      dout[63] = din[23] ^ din[18];
-      dout[62] = din[22] ^ din[17];
-      dout[61] = din[21] ^ din[16];
-      dout[60] = din[20] ^ din[15];
-      dout[59] = din[19] ^ din[14];
-      dout[58] = din[18] ^ din[13];
-      dout[57] = din[17] ^ din[12];
-      dout[56] = din[16] ^ din[11];
-      dout[55] = din[15] ^ din[10];
-      dout[54] = din[14] ^ din[ 9];
-      dout[53] = din[13] ^ din[ 8];
-      dout[52] = din[12] ^ din[ 7];
-      dout[51] = din[11] ^ din[ 6];
-      dout[50] = din[10] ^ din[ 5];
-      dout[49] = din[ 9] ^ din[ 4];
-      dout[48] = din[ 8] ^ din[ 3];
-      dout[47] = din[ 7] ^ din[ 2];
-      dout[46] = din[ 6] ^ din[ 1];
-      dout[45] = din[ 5] ^ din[ 0];
-      dout[44] = din[ 4] ^ din[23] ^ din[18];
-      dout[43] = din[ 3] ^ din[22] ^ din[17];
-      dout[42] = din[ 2] ^ din[21] ^ din[16];
-      dout[41] = din[ 1] ^ din[20] ^ din[15];
-      dout[40] = din[ 0] ^ din[19] ^ din[14];
-      dout[39] = din[23] ^ din[13];
-      dout[38] = din[22] ^ din[12];
-      dout[37] = din[21] ^ din[11];
-      dout[36] = din[20] ^ din[10];
-      dout[35] = din[19] ^ din[ 9];
-      dout[34] = din[18] ^ din[ 8];
-      dout[33] = din[17] ^ din[ 7];
-      dout[32] = din[16] ^ din[ 6];
-      dout[31] = din[15] ^ din[ 5];
-      dout[30] = din[14] ^ din[ 4];
-      dout[29] = din[13] ^ din[ 3];
-      dout[28] = din[12] ^ din[ 2];
-      dout[27] = din[11] ^ din[ 1];
-      dout[26] = din[10] ^ din[ 0];
-      dout[25] = din[ 9] ^ din[23] ^ din[18];
-      dout[24] = din[ 8] ^ din[22] ^ din[17];
-      dout[23] = din[ 7] ^ din[21] ^ din[16];
-      dout[22] = din[ 6] ^ din[20] ^ din[15];
-      dout[21] = din[ 5] ^ din[19] ^ din[14];
-      dout[20] = din[ 4] ^ din[18] ^ din[13];
-      dout[19] = din[ 3] ^ din[17] ^ din[12];
-      dout[18] = din[ 2] ^ din[16] ^ din[11];
-      dout[17] = din[ 1] ^ din[15] ^ din[10];
-      dout[16] = din[ 0] ^ din[14] ^ din[ 9];
-      dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8];
-      dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
-      dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
-      dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
-      dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
-      dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
-      dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
-      dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
-      dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
-      dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18];
-      dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17];
-      dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16];
-      dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15];
-      dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14];
-      dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13];
-      dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12];
-      pn23 = dout;
-    end
-  endfunction
-
-  // pn31 function
-
-  function [63:0] pn31;
-    input [63:0] din;
-    reg   [63:0] dout;
-    begin
-      dout[63] = din[31] ^ din[28];
-      dout[62] = din[30] ^ din[27];
-      dout[61] = din[29] ^ din[26];
-      dout[60] = din[28] ^ din[25];
-      dout[59] = din[27] ^ din[24];
-      dout[58] = din[26] ^ din[23];
-      dout[57] = din[25] ^ din[22];
-      dout[56] = din[24] ^ din[21];
-      dout[55] = din[23] ^ din[20];
-      dout[54] = din[22] ^ din[19];
-      dout[53] = din[21] ^ din[18];
-      dout[52] = din[20] ^ din[17];
-      dout[51] = din[19] ^ din[16];
-      dout[50] = din[18] ^ din[15];
-      dout[49] = din[17] ^ din[14];
-      dout[48] = din[16] ^ din[13];
-      dout[47] = din[15] ^ din[12];
-      dout[46] = din[14] ^ din[11];
-      dout[45] = din[13] ^ din[10];
-      dout[44] = din[12] ^ din[ 9];
-      dout[43] = din[11] ^ din[ 8];
-      dout[42] = din[10] ^ din[ 7];
-      dout[41] = din[ 9] ^ din[ 6];
-      dout[40] = din[ 8] ^ din[ 5];
-      dout[39] = din[ 7] ^ din[ 4];
-      dout[38] = din[ 6] ^ din[ 3];
-      dout[37] = din[ 5] ^ din[ 2];
-      dout[36] = din[ 4] ^ din[ 1];
-      dout[35] = din[ 3] ^ din[ 0];
-      dout[34] = din[ 2] ^ din[31] ^ din[28];
-      dout[33] = din[ 1] ^ din[30] ^ din[27];
-      dout[32] = din[ 0] ^ din[29] ^ din[26];
-      dout[31] = din[31] ^ din[25];
-      dout[30] = din[30] ^ din[24];
-      dout[29] = din[29] ^ din[23];
-      dout[28] = din[28] ^ din[22];
-      dout[27] = din[27] ^ din[21];
-      dout[26] = din[26] ^ din[20];
-      dout[25] = din[25] ^ din[19];
-      dout[24] = din[24] ^ din[18];
-      dout[23] = din[23] ^ din[17];
-      dout[22] = din[22] ^ din[16];
-      dout[21] = din[21] ^ din[15];
-      dout[20] = din[20] ^ din[14];
-      dout[19] = din[19] ^ din[13];
-      dout[18] = din[18] ^ din[12];
-      dout[17] = din[17] ^ din[11];
-      dout[16] = din[16] ^ din[10];
-      dout[15] = din[15] ^ din[ 9];
-      dout[14] = din[14] ^ din[ 8];
-      dout[13] = din[13] ^ din[ 7];
-      dout[12] = din[12] ^ din[ 6];
-      dout[11] = din[11] ^ din[ 5];
-      dout[10] = din[10] ^ din[ 4];
-      dout[ 9] = din[ 9] ^ din[ 3];
-      dout[ 8] = din[ 8] ^ din[ 2];
-      dout[ 7] = din[ 7] ^ din[ 1];
-      dout[ 6] = din[ 6] ^ din[ 0];
-      dout[ 5] = din[ 5] ^ din[31] ^ din[28];
-      dout[ 4] = din[ 4] ^ din[30] ^ din[27];
-      dout[ 3] = din[ 3] ^ din[29] ^ din[26];
-      dout[ 2] = din[ 2] ^ din[28] ^ din[25];
-      dout[ 1] = din[ 1] ^ din[27] ^ din[24];
-      dout[ 0] = din[ 0] ^ din[26] ^ din[23];
-      pn31 = dout;
-    end
-  endfunction
+  assign dac_pn7_data_s    = dac_pn7_data;
+  assign dac_pn15_data_s   = dac_pn15_data;
 
   // dac data select
 
   always @(posedge dac_clk) begin
     dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
     case (dac_data_sel_s)
-      4'h7: dac_data <= dac_pn31_data;
-      4'h6: dac_data <= dac_pn23_data;
-      4'h5: dac_data <= dac_pn15_data;
-      4'h4: dac_data <= dac_pn7_data;
+      4'h7: dac_data <= dac_pn15_data_s;
+      4'h6: dac_data <= dac_pn7_data_s;
+      4'h5: dac_data <= dac_pn15_data_i_s;
+      4'h4: dac_data <= dac_pn7_data_i_s;
       4'h3: dac_data <= 64'd0;
       4'h2: dac_data <= dma_data;
       4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
@@ -453,13 +311,9 @@ module axi_ad9152_channel (
     if (dac_data_sync == 1'b1) begin
       dac_pn7_data <= {64{1'd1}};
       dac_pn15_data <= {64{1'd1}};
-      dac_pn23_data <= {64{1'd1}};
-      dac_pn31_data <= {64{1'd1}};
     end else begin
-      dac_pn7_data <= pn7(dac_pn7_data);
-      dac_pn15_data <= pn15(dac_pn15_data);
-      dac_pn23_data <= pn23(dac_pn23_data);
-      dac_pn31_data <= pn31(dac_pn31_data);
+      dac_pn7_data <= pn7(dac_pn7_data[55:48]);
+      dac_pn15_data <= pn15(dac_pn15_data[63:48]);
     end
   end
 

From 3f3a8bd2678b67e806b6391efcd6b5e00b76971d Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 25 Jan 2017 18:12:04 +0200
Subject: [PATCH 870/972] library: forced ad_mem module to be implemented in
 BRAM for Xilinx devices

---
 library/common/ad_mem.v | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/library/common/ad_mem.v b/library/common/ad_mem.v
index 412e17f8f..a06be19b3 100644
--- a/library/common/ad_mem.v
+++ b/library/common/ad_mem.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -64,6 +64,7 @@ module ad_mem (
   input   [AW:0]  addrb;
   output  [DW:0]  doutb;
 
+  (* ram_style = "block" *)
   reg     [DW:0]  m_ram[0:((2**ADDRESS_WIDTH)-1)];
   reg     [DW:0]  doutb;
 

From 48ad24cdbea3ab39c6541389cd1092e1ebb1e935 Mon Sep 17 00:00:00 2001
From: rejeesh kutty <rejeesh.kutty@analog.com>
Date: Fri, 27 Jan 2017 09:26:53 -0500
Subject: [PATCH 871/972] enable partial reconfiguration mode

---
 projects/fmcomms2/zc706pr/system_project.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/fmcomms2/zc706pr/system_project.tcl b/projects/fmcomms2/zc706pr/system_project.tcl
index 8d60e49bc..f73f3d4a7 100755
--- a/projects/fmcomms2/zc706pr/system_project.tcl
+++ b/projects/fmcomms2/zc706pr/system_project.tcl
@@ -4,7 +4,7 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-set mode 0
+set mode 1
 if {$::argc > 0} {
   set mode [lindex $argv 0]
 }

From 3dd736fe8caf71fffdce99bbb47b0d973c952833 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Sat, 28 Jan 2017 19:23:43 +0100
Subject: [PATCH 872/972] axi_dmac: Add identification register

Add a register to the AXI DMAC register map which functions has a
identification register. The register contains the unique value of "DMAC"
(0x444d4143) and allows software to identify whether the peripheral mapped
at a certain address is an axi_dmac peripheral.

This is useful for detecting cases where the specified address contains an
error or is incorrect.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_dmac/axi_dmac.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
index 3c1d34498..ba4611412 100644
--- a/library/axi_dmac/axi_dmac.v
+++ b/library/axi_dmac/axi_dmac.v
@@ -420,6 +420,7 @@ begin
     12'h000: up_rdata <= PCORE_VERSION;
     12'h001: up_rdata <= ID;
     12'h002: up_rdata <= up_scratch;
+    12'h003: up_rdata <= 32'h444d4143; // "DMAC"
     12'h020: up_rdata <= up_irq_mask;
     12'h021: up_rdata <= up_irq_pending;
     12'h022: up_rdata <= up_irq_source;

From eb8a3fff3c021ea8e9b92ceac3cfd09d6ff864c7 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Mon, 30 Jan 2017 13:33:31 +0100
Subject: [PATCH 873/972] axi_dmac: Set IP core name and description

Add a human readable name and descriptor for the AXI DMAC core.This string
will appear in various places e.g. like the IP catalog. This is a purely
cosmetic change.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_dmac/axi_dmac_ip.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl
index 293a6b7a8..1738351c8 100644
--- a/library/axi_dmac/axi_dmac_ip.tcl
+++ b/library/axi_dmac/axi_dmac_ip.tcl
@@ -36,6 +36,9 @@ adi_ip_add_core_dependencies { \
 	analog.com:user:util_axis_fifo:1.0 \
 }
 
+set_property display_name "ADI AXI DMA Controller" [ipx::current_core]
+set_property description "ADI AXI DMA Controller" [ipx::current_core]
+
 adi_add_bus "s_axis" "slave" \
 	"xilinx.com:interface:axis_rtl:1.0" \
 	"xilinx.com:interface:axis:1.0" \

From b14e7fe4ee710b93b5259c961e3b0e9caca4aa5c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 30 Jan 2017 09:49:44 -0500
Subject: [PATCH 874/972] daq3/kcu105- 1.25GSPS

---
 projects/daq3/kcu105/system_constr.xdc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/projects/daq3/kcu105/system_constr.xdc b/projects/daq3/kcu105/system_constr.xdc
index 794e614a6..a04eb88b0 100644
--- a/projects/daq3/kcu105/system_constr.xdc
+++ b/projects/daq3/kcu105/system_constr.xdc
@@ -38,10 +38,10 @@ set_property  -dict {PACKAGE_PIN  E8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [g
 
 # clocks
 
-create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
-create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
+create_clock -name tx_ref_clk   -period  1.60 [get_ports tx_ref_clk_p]
+create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
+create_clock -name tx_div_clk   -period  3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
 
 # gt pin assignments below are for reference only and are ignored by the tool!
 
@@ -67,6 +67,6 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *
 set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe3_channel}]
 set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe3_channel}]
 
-set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
-set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
+set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
 

From 97d72d2f65719ae9e3bfb22107f5f60b8d5f159a Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 30 Jan 2017 09:59:01 -0500
Subject: [PATCH 875/972] a10gx- xilinx/altera sync-up

---
 projects/daq3/a10gx/system_top.v | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v
index 750e39e3f..488d43065 100644
--- a/projects/daq3/a10gx/system_top.v
+++ b/projects/daq3/a10gx/system_top.v
@@ -209,12 +209,14 @@ module system_top (
 
   // gpio in & out are separate cores
 
-  assign sysref = gpio_o[43];
-  assign adc_pd = gpio_o[42];
-  assign dac_txen = gpio_o[41];
+  assign gpio_i[63:40] = gpio_o[63:40];
+  assign sysref = gpio_o[40];
+  assign gpio_i[39:39] = trig;
+
+  assign gpio_i[38:37] = gpio_o[38:37];
+  assign adc_pd = gpio_o[38];
+  assign dac_txen = gpio_o[37];
 
-  assign gpio_i[63:38] = gpio_o[63:38];
-  assign gpio_i[37:37] = trig;
   assign gpio_i[36:36] = adc_fdb;
   assign gpio_i[35:35] = adc_fda;
   assign gpio_i[34:34] = dac_irq;

From db924953bb93b8bf15495cf5fe23477430debf65 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 30 Jan 2017 10:01:13 -0500
Subject: [PATCH 876/972] altera- warnings about init values

---
 library/altera/avl_adxcfg/avl_adxcfg.v | 4 ++--
 library/common/up_dac_common.v         | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/library/altera/avl_adxcfg/avl_adxcfg.v b/library/altera/avl_adxcfg/avl_adxcfg.v
index 510b077cb..698c7f2a6 100644
--- a/library/altera/avl_adxcfg/avl_adxcfg.v
+++ b/library/altera/avl_adxcfg/avl_adxcfg.v
@@ -80,8 +80,8 @@ module avl_adxcfg (
   reg     [ 9:0]  rcfg_address_int = 'd0;
   reg     [31:0]  rcfg_writedata_int = 'd0;
   reg     [31:0]  rcfg_readdata_int = 'd0;
-  reg             rcfg_waitrequest_int_0 = 'd0;
-  reg             rcfg_waitrequest_int_1 = 'd0;
+  reg             rcfg_waitrequest_int_0 = 'd1;
+  reg             rcfg_waitrequest_int_1 = 'd1;
 
   // internal signals
 
diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index 39c4de5e2..5d0968a7b 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -104,8 +104,8 @@ module up_dac_common #(
 
   // internal registers
 
-  reg             up_core_preset = 'd0;
-  reg             up_mmcm_preset = 'd0;
+  reg             up_core_preset = 'd1;
+  reg             up_mmcm_preset = 'd1;
   reg             up_wack_int = 'd0;
   reg     [31:0]  up_scratch = 'd0;
   reg             up_mmcm_resetn = 'd0;

From fb945ac51c601a3a7b0673b4a946c1f1c7d520dc Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:18:58 +0200
Subject: [PATCH 877/972] axi_ad9963: Initial commit

---
 library/axi_ad9963/Makefile                |  73 ++++
 library/axi_ad9963/axi_ad9963.v            | 322 ++++++++++++++++
 library/axi_ad9963/axi_ad9963_if.v         | 297 +++++++++++++++
 library/axi_ad9963/axi_ad9963_ip.tcl       |  57 +++
 library/axi_ad9963/axi_ad9963_rx.v         | 252 +++++++++++++
 library/axi_ad9963/axi_ad9963_rx_channel.v | 214 +++++++++++
 library/axi_ad9963/axi_ad9963_rx_pnmon.v   | 121 ++++++
 library/axi_ad9963/axi_ad9963_tx.v         | 272 ++++++++++++++
 library/axi_ad9963/axi_ad9963_tx_channel.v | 415 +++++++++++++++++++++
 9 files changed, 2023 insertions(+)
 create mode 100644 library/axi_ad9963/Makefile
 create mode 100644 library/axi_ad9963/axi_ad9963.v
 create mode 100644 library/axi_ad9963/axi_ad9963_if.v
 create mode 100644 library/axi_ad9963/axi_ad9963_ip.tcl
 create mode 100644 library/axi_ad9963/axi_ad9963_rx.v
 create mode 100644 library/axi_ad9963/axi_ad9963_rx_channel.v
 create mode 100644 library/axi_ad9963/axi_ad9963_rx_pnmon.v
 create mode 100644 library/axi_ad9963/axi_ad9963_tx.v
 create mode 100644 library/axi_ad9963/axi_ad9963_tx_channel.v

diff --git a/library/axi_ad9963/Makefile b/library/axi_ad9963/Makefile
new file mode 100644
index 000000000..4c5b88c2a
--- /dev/null
+++ b/library/axi_ad9963/Makefile
@@ -0,0 +1,73 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += ../common/ad_axi_ip_constr.xdc
+M_DEPS += ../common/ad_datafmt.v
+M_DEPS += ../common/ad_dcfilter.v
+M_DEPS += ../common/ad_dds.v
+M_DEPS += ../common/ad_dds_1.v
+M_DEPS += ../common/ad_dds_sine.v
+M_DEPS += ../common/ad_iqcor.v
+M_DEPS += ../common/ad_pnmon.v
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_adc_channel.v
+M_DEPS += ../common/up_adc_common.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_clock_mon.v
+M_DEPS += ../common/up_dac_channel.v
+M_DEPS += ../common/up_dac_common.v
+M_DEPS += ../common/up_delay_cntrl.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += ../xilinx/common/ad_lvds_in.v
+M_DEPS += ../xilinx/common/ad_lvds_out.v
+M_DEPS += ../xilinx/common/ad_mul.v
+M_DEPS += axi_ad9963.v
+M_DEPS += axi_ad9963_if.v
+M_DEPS += axi_ad9963_ip.tcl
+M_DEPS += axi_ad9963_rx.v
+M_DEPS += axi_ad9963_rx_channel.v
+M_DEPS += axi_ad9963_rx_pnmon.v
+M_DEPS += axi_ad9963_tx.v
+M_DEPS += axi_ad9963_tx_channel.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_ad9963.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_ad9963.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_ad9963_ip.tcl  >> axi_ad9963_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/axi_ad9963/axi_ad9963.v b/library/axi_ad9963/axi_ad9963.v
new file mode 100644
index 000000000..1bed35e21
--- /dev/null
+++ b/library/axi_ad9963/axi_ad9963.v
@@ -0,0 +1,322 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9963 #(
+
+  // parameters
+
+  parameter   ID = 0,
+  parameter   DEVICE_TYPE = 0,
+  parameter   DAC_IODELAY_ENABLE = 0,
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group",
+  parameter   DAC_DATAPATH_DISABLE = 0,
+  parameter   ADC_DATAPATH_DISABLE = 0 ) (
+
+  // physical interface (receive)
+
+  input           trx_clk,
+  input           trx_iq,
+  input   [11:0]  trx_data,
+
+  // physical interface (transmit)
+
+  output          tx_clk,
+  output          tx_iq,
+  output  [11:0]  tx_data,
+
+  // transmit master/slave
+
+  input           dac_sync_in,
+  output          dac_sync_out,
+
+  // delay clock
+
+  input           delay_clk,
+
+  // master interface
+
+  output          l_clk,
+  output          dac_clk,
+  output          rst,
+
+  // dma interface
+
+  output          adc_enable_i,
+  output          adc_valid_i,
+  output  [15:0]  adc_data_i,
+  output          adc_enable_q,
+  output          adc_valid_q,
+  output  [15:0]  adc_data_q,
+  input           adc_dovf,
+  input           adc_dunf,
+
+  output          dac_enable_i,
+  output          dac_valid_i,
+  input   [15:0]  dac_data_i,
+  output          dac_enable_q,
+  output          dac_valid_q,
+  input   [15:0]  dac_data_q,
+  input           dac_dovf,
+  input           dac_dunf,
+
+  // axi interface
+
+  input           s_axi_aclk,
+  input           s_axi_aresetn,
+  input           s_axi_awvalid,
+  input   [31:0]  s_axi_awaddr,
+  input   [ 2:0]  s_axi_awprot,
+  output          s_axi_awready,
+  input           s_axi_wvalid,
+  input   [31:0]  s_axi_wdata,
+  input   [ 3:0]  s_axi_wstrb,
+  output          s_axi_wready,
+  output          s_axi_bvalid,
+  output  [ 1:0]  s_axi_bresp,
+  input           s_axi_bready,
+  input           s_axi_arvalid,
+  input   [31:0]  s_axi_araddr,
+  input   [ 2:0]  s_axi_arprot,
+  output          s_axi_arready,
+  output          s_axi_rvalid,
+  output  [31:0]  s_axi_rdata,
+  output  [ 1:0]  s_axi_rresp,
+  input           s_axi_rready);
+
+  // internal registers
+
+  reg             up_wack = 'd0;
+  reg             up_rack = 'd0;
+  reg     [31:0]  up_rdata = 'd0;
+
+  // internal clocks and resets
+
+  wire            up_clk;
+  wire            up_rstn;
+  wire            delay_rst;
+
+  // internal signals
+
+  wire            adc_valid_s;
+  wire    [23:0]  adc_data_s;
+  wire            adc_status_s;
+  wire            dac_valid_s;
+  wire    [23:0]  dac_data_s;
+  wire            dac_valid_i0_s;
+  wire            dac_valid_q0_s;
+  wire            dac_valid_i1_s;
+  wire            dac_valid_q1_s;
+  wire    [12:0]  up_adc_dld_s;
+  wire    [64:0]  up_adc_dwdata_s;
+  wire    [64:0]  up_adc_drdata_s;
+  wire    [13:0]  up_dac_dld_s;
+  wire    [69:0]  up_dac_dwdata_s;
+  wire    [69:0]  up_dac_drdata_s;
+  wire            delay_locked_s;
+  wire            up_wreq_s;
+  wire    [13:0]  up_waddr_s;
+  wire    [31:0]  up_wdata_s;
+  wire            up_wack_rx_s;
+  wire            up_wack_tx_s;
+  wire            up_rreq_s;
+  wire    [13:0]  up_raddr_s;
+  wire    [31:0]  up_rdata_rx_s;
+  wire            up_rack_rx_s;
+  wire    [31:0]  up_rdata_tx_s;
+  wire            up_rack_tx_s;
+
+  // signal name changes
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_wack <= up_wack_rx_s | up_wack_tx_s ;
+      up_rack <= up_rack_rx_s | up_rack_tx_s ;
+      up_rdata <= up_rdata_rx_s | up_rdata_tx_s ;
+    end
+  end
+
+  // device interface
+
+  axi_ad9963_if #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IO_DELAY_GROUP (IO_DELAY_GROUP))
+  i_dev_if (
+    .trx_clk (trx_clk),
+    .trx_iq (trx_iq),
+    .trx_data (trx_data),
+    .tx_clk (tx_clk),
+    .tx_iq (tx_iq),
+    .tx_data (tx_data),
+    .rst (rst),
+    .l_clk (l_clk),
+    .dac_clk (dac_clk),
+    .adc_valid (adc_valid_s),
+    .adc_data (adc_data_s),
+    .adc_status (adc_status_s),
+    .dac_valid (dac_valid_s),
+    .dac_data (dac_data_s),
+    .up_clk (up_clk),
+    .up_adc_dld (up_adc_dld_s),
+    .up_adc_dwdata (up_adc_dwdata_s),
+    .up_adc_drdata (up_adc_drdata_s),
+    .up_dac_dld (up_dac_dld_s),
+    .up_dac_dwdata (up_dac_dwdata_s),
+    .up_dac_drdata (up_dac_drdata_s),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked_s));
+
+  // receive
+
+  axi_ad9963_rx #(
+    .ID (ID),
+    .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
+  i_rx (
+    .adc_rst (rst),
+    .adc_clk (l_clk),
+    .adc_valid (adc_valid_s),
+    .adc_data (adc_data_s),
+    .adc_status (adc_status_s),
+    .up_dld (up_adc_dld_s),
+    .up_dwdata (up_adc_dwdata_s),
+    .up_drdata (up_adc_drdata_s),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked_s),
+    .adc_enable_i (adc_enable_i),
+    .adc_valid_i (adc_valid_i),
+    .adc_data_i (adc_data_i),
+    .adc_enable_q (adc_enable_q),
+    .adc_valid_q (adc_valid_q),
+    .adc_data_q (adc_data_q),
+    .adc_dovf (adc_dovf),
+    .adc_dunf (adc_dunf),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_rx_s),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_rx_s),
+    .up_rack (up_rack_rx_s));
+
+  // transmit
+
+  axi_ad9963_tx #(
+    .ID (ID),
+    .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
+  i_tx (
+    .dac_clk (dac_clk),
+    .dac_valid (dac_valid_s),
+    .dac_data (dac_data_s),
+    .adc_data (adc_data_s),
+    .up_dld (up_dac_dld_s),
+    .up_dwdata (up_dac_dwdata_s),
+    .up_drdata (up_dac_drdata_s),
+    .delay_clk (delay_clk),
+    .delay_rst (),
+    .delay_locked (delay_locked_s),
+    .dac_sync_in (dac_sync_in),
+    .dac_sync_out (dac_sync_out),
+    .dac_enable_i (dac_enable_i),
+    .dac_valid_i (dac_valid_i),
+    .dac_data_i (dac_data_i),
+    .dac_enable_q (dac_enable_q),
+    .dac_valid_q (dac_valid_q),
+    .dac_data_q (dac_data_q),
+    .dac_dovf(dac_dovf),
+    .dac_dunf(dac_dunf),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_tx_s),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_tx_s),
+    .up_rack (up_rack_tx_s));
+
+  // axi interface
+
+  up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v
new file mode 100644
index 000000000..d87467530
--- /dev/null
+++ b/library/axi_ad9963/axi_ad9963_if.v
@@ -0,0 +1,297 @@
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// This interface includes both the transmit and receive components -
+// They both uses the same clock (sourced from the receiving side).
+// assumes RX_IQ is 1 for I and 0 for Q (RX_IFIRST = 1 , RXIQ_HILO = 1)
+
+`timescale 1ns/100ps
+
+module axi_ad9963_if #(
+
+  // this parameter controls the buffer type based on the target device.
+
+  parameter   DEVICE_TYPE = 0,
+  parameter   DAC_IODELAY_ENABLE = 0,
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group") (
+
+  // physical interface (receive)
+
+  input               trx_clk,
+  input               trx_iq,
+  input       [11:0]  trx_data,
+
+  // physical interface (transmit)
+
+  output              tx_clk,
+  output              tx_iq,
+  output      [11:0]  tx_data,
+
+  // clock (common to both receive and transmit)
+
+  input               rst,
+  output              l_clk,
+  output              dac_clk,
+
+  // receive data path interface
+
+  output reg          adc_valid,
+  output reg  [23:0]  adc_data,
+  output reg          adc_status,
+
+  // transmit data path interface
+
+  input           dac_valid,
+  input   [23:0]  dac_data,
+
+  // delay interface
+
+  input           up_clk,
+  input   [12:0]  up_adc_dld,
+  input   [64:0]  up_adc_dwdata,
+  output  [64:0]  up_adc_drdata,
+  input   [13:0]  up_dac_dld,
+  input   [69:0]  up_dac_dwdata,
+  output  [69:0]  up_dac_drdata,
+  input           delay_clk,
+  input           delay_rst,
+  output          delay_locked);
+
+  // internal registers
+
+  reg     [11:0]  rx_data_p = 0;
+  reg     [11:0]  tx_data_p = 'd0;
+  reg     [11:0]  tx_data_n = 'd0;
+  reg             tx_n_iq = 'd0;
+  reg             tx_p_iq = 'd0;
+
+  // internal signals
+
+  wire    [11:0]  rx_data_p_s;
+  wire    [11:0]  rx_data_n_s;
+  wire            rx_iq_p_s;
+  wire            rx_iq_n_s;
+
+  wire            feedback_clk;
+  wire            tx_clk_pll;
+
+  genvar          l_inst;
+
+  always @(posedge l_clk) begin
+    if( rx_iq_p_s == 1'b1) begin
+      adc_data  <= {rx_data_n_s, rx_data_p_s} ;  // data[11:00] I
+      adc_valid <= 1'b1;                        // data[23:12] Q
+    end else begin
+      rx_data_p <= rx_data_p_s;               // if this happens it means that risedge data is sampled on falledge
+      adc_data  <= {rx_data_p, rx_data_n_s} ;  // so we take current N data with previous P data
+      adc_valid <= 1'b1;                      // in order to have data sampled at the same instance sent to the DMA
+    end
+  end
+
+  always @(posedge dac_clk) begin
+    if(dac_valid == 1'b1) begin
+      tx_data_p   <= dac_data[11:0] ;
+      tx_data_n   <= dac_data[23:12];
+      tx_p_iq     <= 1'b1;
+      tx_n_iq     <= 1'b0;
+    end
+  end
+
+  always @(posedge l_clk) begin
+    if (rst == 1'b1) begin
+      adc_status <= 1'b0;
+    end else begin
+      adc_status <= 1'b1;
+    end
+  end
+
+  // device clock interface (receive clock)
+
+  BUFG i_clk_gbuf (
+    .I (trx_clk),
+    .O (l_clk));
+
+  // receive data interface, ibuf -> idelay -> iddr
+
+  generate
+  for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
+  ad_lvds_in #(
+    .SINGLE_ENDED (1),
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_rx_data (
+    .rx_clk (l_clk),
+    .rx_data_in_p (trx_data[l_inst]),
+    .rx_data_in_n (1'b0),
+    .rx_data_p (rx_data_p_s[l_inst]),
+    .rx_data_n (rx_data_n_s[l_inst]),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[l_inst]),
+    .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+  end
+  endgenerate
+
+  // receive iq interface, ibuf -> idelay -> iddr
+
+  ad_lvds_in #(
+    .SINGLE_ENDED (1),
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .IODELAY_CTRL (1),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_rx_iq (
+    .rx_clk (l_clk),
+    .rx_data_in_p (trx_iq),
+    .rx_data_in_n (1'b0),
+    .rx_data_p (rx_iq_p_s),
+    .rx_data_n (rx_iq_n_s),
+    .up_clk (up_clk),
+    .up_dld (up_adc_dld[12]),
+    .up_dwdata (up_adc_dwdata[64:60]),
+    .up_drdata (up_adc_drdata[64:60]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked));
+
+  // transmit data interface, oddr -> obuf
+
+  generate
+  for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
+  ad_lvds_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_data (
+    .tx_clk (dac_clk),
+    .tx_data_p (tx_data_p[l_inst]),
+    .tx_data_n (tx_data_n[l_inst]),
+    .tx_data_out_p (tx_data[l_inst]),
+    .tx_data_out_n (),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[l_inst]),
+    .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+  end
+  endgenerate
+
+  // transmit iq interface, oddr -> obuf
+
+  ad_lvds_out #(
+    .DEVICE_TYPE (DEVICE_TYPE),
+    .SINGLE_ENDED (1),
+    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .IODELAY_CTRL (0),
+    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_tx_iq (
+    .tx_clk (dac_clk),
+    .tx_data_p (tx_p_iq),
+    .tx_data_n (tx_n_iq),
+    .tx_data_out_p (tx_iq),
+    .tx_data_out_n (),
+    .up_clk (up_clk),
+    .up_dld (up_dac_dld[12]),
+    .up_dwdata (up_dac_dwdata[64:60]),
+    .up_drdata (up_dac_drdata[64:60]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked ());
+
+  // transmit clock interface, oddr -> obuf
+  PLLE2_BASE #(
+    .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
+    .CLKFBOUT_MULT(15), // Multiply value for all CLKOUT, (2-64)
+    .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
+    .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
+    // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
+    .CLKOUT0_DIVIDE(20),
+    .CLKOUT1_DIVIDE(20),
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT5_DIVIDE(1),
+    // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
+    .CLKOUT0_PHASE(90.0),
+    .CLKOUT1_PHASE(0.0),
+    .CLKOUT2_PHASE(0.0),
+    .CLKOUT3_PHASE(0.0),
+    .CLKOUT4_PHASE(0.0),
+    .CLKOUT5_PHASE(0.0),
+    .DIVCLK_DIVIDE(1), // Master division value, (1-56)
+    .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
+    .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
+    )
+    PLLE2_BASE_inst (
+    // Clock Outputs: 1-bit (each) output: User configurable clock outputs
+    .CLKOUT0(tx_clk_pll), // 1-bit output: CLKOUT0
+    .CLKOUT1(dac_clk), // 1-bit output: CLKOUT1
+    .CLKOUT2(), // 1-bit output: CLKOUT2
+    .CLKOUT3(), // 1-bit output: CLKOUT3
+    .CLKOUT4(), // 1-bit output: CLKOUT4
+    .CLKOUT5(), // 1-bit output: CLKOUT5
+    // Feedback Clocks: 1-bit (each) output: Clock feedback ports
+    .CLKFBOUT(feedback_clk), // 1-bit output: Feedback clock
+    .LOCKED(), // 1-bit output: LOCK
+    .CLKIN1(l_clk), // 1-bit input: Input clock
+    // Control Ports: 1-bit (each) input: PLL control ports
+    .PWRDWN(1'b0), // 1-bit input: Power-down
+    .RST(rst), // 1-bit input: Reset
+    // Feedback Clocks: 1-bit (each) input: Clock feedback ports
+    .CLKFBIN(feedback_clk) // 1-bit input: Feedback clock
+    );
+
+  ODDR #(
+    .DDR_CLK_EDGE ("SAME_EDGE"),
+    .INIT (1'b0),
+    .SRTYPE ("ASYNC"))
+  i_tx_clk_oddr(
+    .CE (1'b1),
+    .R (1'b0),
+    .S (1'b0),
+    .C (tx_clk_pll),
+    .D1 (1'b1),
+    .D2 (1'b0),
+    .Q (tx_clk));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963_ip.tcl b/library/axi_ad9963/axi_ad9963_ip.tcl
new file mode 100644
index 000000000..860878395
--- /dev/null
+++ b/library/axi_ad9963/axi_ad9963_ip.tcl
@@ -0,0 +1,57 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_ad9963
+adi_ip_files axi_ad9963 [list \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
+  "$ad_hdl_dir/library/common/ad_pnmon.v" \
+  "$ad_hdl_dir/library/common/ad_dds_sine.v" \
+  "$ad_hdl_dir/library/common/ad_dds_1.v" \
+  "$ad_hdl_dir/library/common/ad_dds.v" \
+  "$ad_hdl_dir/library/common/ad_datafmt.v" \
+  "$ad_hdl_dir/library/common/ad_dcfilter.v" \
+  "$ad_hdl_dir/library/common/ad_iqcor.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_xfer_status.v" \
+  "$ad_hdl_dir/library/common/up_clock_mon.v" \
+  "$ad_hdl_dir/library/common/up_delay_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_adc_common.v" \
+  "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/up_dac_common.v" \
+  "$ad_hdl_dir/library/common/up_dac_channel.v" \
+  "axi_ad9963_if.v" \
+  "axi_ad9963_rx_pnmon.v" \
+  "axi_ad9963_rx_channel.v" \
+  "axi_ad9963_rx.v" \
+  "axi_ad9963_tx_channel.v" \
+  "axi_ad9963_tx.v" \
+  "axi_ad9963.v" ]
+
+adi_ip_properties axi_ad9963
+adi_ip_constraints axi_ad9963 [list \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
+
+set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
+set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
+
+ipx::remove_bus_interface rst [ipx::current_core]
+ipx::remove_bus_interface clk [ipx::current_core]
+ipx::remove_bus_interface l_clk [ipx::current_core]
+ipx::remove_bus_interface delay_clk [ipx::current_core]
+
+ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
+  -of_objects [ipx::current_core]]
+set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
+  -of_objects [ipx::get_bus_interfaces s_axi_aclk \
+  -of_objects [ipx::current_core]]]
+
+ipx::save_core [ipx::current_core]
+
diff --git a/library/axi_ad9963/axi_ad9963_rx.v b/library/axi_ad9963/axi_ad9963_rx.v
new file mode 100644
index 000000000..29fea5f15
--- /dev/null
+++ b/library/axi_ad9963/axi_ad9963_rx.v
@@ -0,0 +1,252 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9963_rx #(
+
+  // parameters
+
+  parameter   DATAPATH_DISABLE = 0,
+  parameter   ID = 0) (
+
+  // adc interface
+
+  output              adc_rst,
+  input               adc_clk,
+  input               adc_valid,
+  input       [23:0]  adc_data,
+  input               adc_status,
+
+  // delay interface
+
+  output      [12:0]  up_dld,
+  output      [64:0]  up_dwdata,
+  input       [64:0]  up_drdata,
+  input               delay_clk,
+  output              delay_rst,
+  input               delay_locked,
+
+  // dma interface
+
+  output              adc_enable_i,
+  output              adc_valid_i,
+  output      [15:0]  adc_data_i,
+  output              adc_enable_q,
+  output              adc_valid_q,
+  output      [15:0]  adc_data_q,
+  input               adc_dovf,
+  input               adc_dunf,
+
+  // processor interface
+
+  input               up_rstn,
+  input               up_clk,
+  input               up_wreq,
+  input       [13:0]  up_waddr,
+  input       [31:0]  up_wdata,
+  output reg          up_wack,
+  input               up_rreq,
+  input       [13:0]  up_raddr,
+  output reg  [31:0]  up_rdata,
+  output reg          up_rack);
+
+  // internal registers
+
+  reg             up_status_pn_err = 'd0;
+  reg             up_status_pn_oos = 'd0;
+  reg             up_status_or = 'd0;
+
+  // internal signals
+
+  wire    [15:0]  adc_dcfilter_data_out_0_s;
+  wire    [15:0]  adc_dcfilter_data_out_1_s;
+  wire    [ 1:0]  up_adc_pn_err_s;
+  wire    [ 1:0]  up_adc_pn_oos_s;
+  wire    [ 1:0]  up_adc_or_s;
+  wire    [31:0]  up_rdata_s[0:3];
+  wire            up_rack_s[0:3];
+  wire            up_wack_s[0:3];
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_status_pn_err <= 'd0;
+      up_status_pn_oos <= 'd0;
+      up_status_or <= 'd0;
+      up_rdata <= 'd0;
+      up_rack <= 'd0;
+      up_wack <= 'd0;
+    end else begin
+      up_status_pn_err <= | up_adc_pn_err_s;
+      up_status_pn_oos <= | up_adc_pn_oos_s;
+      up_status_or <= | up_adc_or_s;
+      up_rdata  <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
+      up_rack   <= up_rack_s[0]  | up_rack_s[1]  | up_rack_s[2]  | up_rack_s[3];
+      up_wack   <= up_wack_s[0]  | up_wack_s[1]  | up_wack_s[2]  | up_wack_s[3];
+    end
+  end
+
+  // channel 0 (i)
+
+  axi_ad9963_rx_channel #(
+    .Q_OR_I_N(0),
+    .CHANNEL_ID(0),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+  i_rx_channel_0 (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_valid (adc_valid),
+    .adc_data (adc_data[11:0]),
+    .adc_or (1'b0),
+    .adc_dcfilter_data_out (adc_dcfilter_data_out_0_s),
+    .adc_dcfilter_data_in (adc_dcfilter_data_out_1_s),
+    .adc_iqcor_valid (adc_valid_i),
+    .adc_iqcor_data (adc_data_i),
+    .adc_enable (adc_enable_i),
+    .up_adc_pn_err (up_adc_pn_err_s[0]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[0]),
+    .up_adc_or (up_adc_or_s[0]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  // channel 1 (q)
+
+  axi_ad9963_rx_channel #(
+    .Q_OR_I_N(1),
+    .CHANNEL_ID(1),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+  i_rx_channel_1 (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_valid (adc_valid),
+    .adc_data (adc_data[23:12]),
+    .adc_or (1'b0),
+    .adc_dcfilter_data_out (adc_dcfilter_data_out_1_s),
+    .adc_dcfilter_data_in (adc_dcfilter_data_out_0_s),
+    .adc_iqcor_valid (adc_valid_q),
+    .adc_iqcor_data (adc_data_q),
+    .adc_enable (adc_enable_q),
+    .up_adc_pn_err (up_adc_pn_err_s[1]),
+    .up_adc_pn_oos (up_adc_pn_oos_s[1]),
+    .up_adc_or (up_adc_or_s[1]),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[1]),
+    .up_rack (up_rack_s[1]));
+
+  // common processor control
+
+  up_adc_common #(.ID (ID)) i_up_adc_common (
+    .mmcm_rst (),
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_r1_mode (),
+    .adc_ddr_edgesel (),
+    .adc_pin_mode (),
+    .adc_status (adc_status),
+    .adc_sync_status (1'd0),
+    .adc_status_ovf (adc_dovf),
+    .adc_status_unf (adc_dunf),
+    .adc_clk_ratio (32'd1),
+    .adc_start_code (),
+    .adc_sync (),
+    .up_status_pn_err (up_status_pn_err),
+    .up_status_pn_oos (up_status_pn_oos),
+    .up_status_or (up_status_or),
+    .up_drp_sel (),
+    .up_drp_wr (),
+    .up_drp_addr (),
+    .up_drp_wdata (),
+    .up_drp_rdata (16'd0),
+    .up_drp_ready (1'd0),
+    .up_drp_locked (1'd1),
+    .up_usr_chanmax (),
+    .adc_usr_chanmax (8'd1),
+    .up_adc_gpio_in (32'h0),
+    .up_adc_gpio_out (),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[2]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[2]),
+    .up_rack (up_rack_s[2]));
+
+  // adc delay control
+
+  up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked),
+    .up_dld (up_dld),
+    .up_dwdata (up_dwdata),
+    .up_drdata (up_drdata),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[3]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[3]),
+    .up_rack (up_rack_s[3]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_ad9963/axi_ad9963_rx_channel.v b/library/axi_ad9963/axi_ad9963_rx_channel.v
new file mode 100644
index 000000000..9c26e04fe
--- /dev/null
+++ b/library/axi_ad9963/axi_ad9963_rx_channel.v
@@ -0,0 +1,214 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9963_rx_channel #(
+
+  // parameters
+
+  parameter Q_OR_I_N = 0,
+  parameter CHANNEL_ID = 0,
+  parameter DATAPATH_DISABLE = 0) (
+
+  // adc interface
+
+  input           adc_clk,
+  input           adc_rst,
+  input           adc_valid,
+  input   [11:0]  adc_data,
+  input           adc_or,
+
+  // channel interface
+
+  output  [15:0]  adc_dcfilter_data_out,
+  input   [15:0]  adc_dcfilter_data_in,
+  output          adc_iqcor_valid,
+  output  [15:0]  adc_iqcor_data,
+  output          adc_enable,
+  output          up_adc_pn_err,
+  output          up_adc_pn_oos,
+  output          up_adc_or,
+
+  // processor interface
+
+  input           up_rstn,
+  input           up_clk,
+  input           up_wreq,
+  input   [13:0]  up_waddr,
+  input   [31:0]  up_wdata,
+  output          up_wack,
+  input           up_rreq,
+  input   [13:0]  up_raddr,
+  output  [31:0]  up_rdata,
+  output          up_rack);
+
+  // internal signals
+
+  wire            adc_dfmt_valid_s;
+  wire    [15:0]  adc_dfmt_data_s;
+  wire            adc_dcfilter_valid_s;
+  wire    [15:0]  adc_dcfilter_data_s;
+  wire            adc_iqcor_enb_s;
+  wire            adc_dcfilt_enb_s;
+  wire            adc_dfmt_se_s;
+  wire            adc_dfmt_type_s;
+  wire            adc_dfmt_enable_s;
+  wire    [15:0]  adc_dcfilt_offset_s;
+  wire    [15:0]  adc_dcfilt_coeff_s;
+  wire    [15:0]  adc_iqcor_coeff_1_s;
+  wire    [15:0]  adc_iqcor_coeff_2_s;
+  wire    [ 3:0]  adc_pnseq_sel_s;
+  wire    [ 3:0]  adc_data_sel_s;
+  wire            adc_pn_err_s;
+  wire            adc_pn_oos_s;
+
+  // iq correction inputs
+
+  assign adc_dcfilter_data_out = adc_dcfilter_data_s;
+
+  axi_ad9963_rx_pnmon i_rx_pnmon (
+    .adc_clk (adc_clk),
+    .adc_valid (adc_valid),
+    .adc_data (adc_data),
+    .adc_pnseq_sel (adc_pnseq_sel_s),
+    .adc_pn_oos (adc_pn_oos_s),
+    .adc_pn_err (adc_pn_err_s));
+
+  generate
+  if (DATAPATH_DISABLE == 1) begin
+  assign adc_dfmt_valid_s = adc_valid;
+  assign adc_dfmt_data_s = {4'd0, adc_data};
+  end else begin
+  ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt (
+    .clk (adc_clk),
+    .valid (adc_valid),
+    .data (adc_data),
+    .valid_out (adc_dfmt_valid_s),
+    .data_out (adc_dfmt_data_s),
+    .dfmt_enable (adc_dfmt_enable_s),
+    .dfmt_type (adc_dfmt_type_s),
+    .dfmt_se (adc_dfmt_se_s));
+  end
+  endgenerate
+
+  generate
+  if (DATAPATH_DISABLE == 1) begin
+  assign adc_dcfilter_valid_s = adc_dfmt_valid_s;
+  assign adc_dcfilter_data_s = adc_dfmt_data_s;
+  end else begin
+  ad_dcfilter i_ad_dcfilter (
+    .clk (adc_clk),
+    .valid (adc_dfmt_valid_s),
+    .data (adc_dfmt_data_s),
+    .valid_out (adc_dcfilter_valid_s),
+    .data_out (adc_dcfilter_data_s),
+    .dcfilt_enb (adc_dcfilt_enb_s),
+    .dcfilt_coeff (adc_dcfilt_coeff_s),
+    .dcfilt_offset (adc_dcfilt_offset_s));
+  end
+  endgenerate
+
+  generate
+  if (DATAPATH_DISABLE == 1) begin
+  assign adc_iqcor_valid = adc_dcfilter_valid_s;
+  assign adc_iqcor_data = adc_dcfilter_data_s;
+  end else begin
+  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
+    .clk (adc_clk),
+    .valid (adc_dcfilter_valid_s),
+    .data_in (adc_dcfilter_data_s),
+    .data_iq (adc_dcfilter_data_in),
+    .valid_out (adc_iqcor_valid),
+    .data_out (adc_iqcor_data),
+    .iqcor_enable (adc_iqcor_enb_s),
+    .iqcor_coeff_1 (adc_iqcor_coeff_1_s),
+    .iqcor_coeff_2 (adc_iqcor_coeff_2_s));
+  end
+  endgenerate
+
+  up_adc_channel #(.CHANNEL_ID (CHANNEL_ID)) i_up_adc_channel (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_enable (adc_enable),
+    .adc_iqcor_enb (adc_iqcor_enb_s),
+    .adc_dcfilt_enb (adc_dcfilt_enb_s),
+    .adc_dfmt_se (adc_dfmt_se_s),
+    .adc_dfmt_type (adc_dfmt_type_s),
+    .adc_dfmt_enable (adc_dfmt_enable_s),
+    .adc_dcfilt_offset (adc_dcfilt_offset_s),
+    .adc_dcfilt_coeff (adc_dcfilt_coeff_s),
+    .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
+    .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
+    .adc_pnseq_sel (adc_pnseq_sel_s),
+    .adc_data_sel (adc_data_sel_s),
+    .adc_pn_err (adc_pn_err_s),
+    .adc_pn_oos (adc_pn_oos_s),
+    .adc_or (adc_or),
+    .up_adc_pn_err (up_adc_pn_err),
+    .up_adc_pn_oos (up_adc_pn_oos),
+    .up_adc_or (up_adc_or),
+    .up_usr_datatype_be (),
+    .up_usr_datatype_signed (),
+    .up_usr_datatype_shift (),
+    .up_usr_datatype_total_bits (),
+    .up_usr_datatype_bits (),
+    .up_usr_decimation_m (),
+    .up_usr_decimation_n (),
+    .adc_usr_datatype_be (1'b0),
+    .adc_usr_datatype_signed (1'b1),
+    .adc_usr_datatype_shift (8'd0),
+    .adc_usr_datatype_total_bits (8'd16),
+    .adc_usr_datatype_bits (8'd16),
+    .adc_usr_decimation_m (16'd1),
+    .adc_usr_decimation_n (16'd1),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_ad9963/axi_ad9963_rx_pnmon.v b/library/axi_ad9963/axi_ad9963_rx_pnmon.v
new file mode 100644
index 000000000..6a38eb0f4
--- /dev/null
+++ b/library/axi_ad9963/axi_ad9963_rx_pnmon.v
@@ -0,0 +1,121 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// PN monitors
+
+`timescale 1ns/100ps
+
+module axi_ad9963_rx_pnmon (
+
+  // adc interface
+
+  input           adc_clk,
+  input           adc_valid,
+  input   [11:0]  adc_data,
+
+  // pn out of sync and error
+
+  input   [ 3:0]  adc_pnseq_sel,
+  output          adc_pn_oos,
+  output          adc_pn_err);
+
+  // internal registers
+
+  reg     [23:0]  adc_pn_data_in = 'd0;
+  reg     [23:0]  adc_pn_data_pn = 'd0;
+
+  // internal signals
+
+  wire    [31:0]  adc_pn_data_pn_s;
+
+  // bit reversal function
+
+  function [11:0] brfn;
+    input [11:0] din;
+    reg   [11:0] dout;
+    begin
+      dout[11] = din[ 0];
+      dout[10] = din[ 1];
+      dout[ 9] = din[ 2];
+      dout[ 8] = din[ 3];
+      dout[ 7] = din[ 4];
+      dout[ 6] = din[ 5];
+      dout[ 5] = din[ 6];
+      dout[ 4] = din[ 7];
+      dout[ 3] = din[ 8];
+      dout[ 2] = din[ 9];
+      dout[ 1] = din[10];
+      dout[ 0] = din[11];
+      brfn = dout;
+    end
+  endfunction
+
+  // standard prbs functions
+
+ function [23:0] pn23;
+    input [23:0] din;
+    reg   [23:0] dout;
+    begin
+      dout = {din[22:0], din[22] ^ din[17]};
+      pn23 = dout;
+    end
+  endfunction
+
+  // standard, runs on 24bit
+
+  assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
+
+ always @(posedge adc_clk) begin
+   if(adc_valid == 1'b1) begin
+     adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data};
+     adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
+   end
+ end
+
+  // pn oos & pn err
+
+  ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
+    .adc_clk (adc_clk),
+    .adc_valid_in (adc_valid),
+    .adc_data_in (adc_pn_data_in),
+    .adc_data_pn (adc_pn_data_pn),
+    .adc_pn_oos (adc_pn_oos),
+    .adc_pn_err (adc_pn_err));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963_tx.v b/library/axi_ad9963/axi_ad9963_tx.v
new file mode 100644
index 000000000..f8ab3eb25
--- /dev/null
+++ b/library/axi_ad9963/axi_ad9963_tx.v
@@ -0,0 +1,272 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9963_tx #(
+
+  // parameters
+
+  parameter   DATAPATH_DISABLE = 0,
+  parameter   ID = 0) (
+
+  // dac interface
+
+  input               dac_clk,
+  output reg          dac_valid,
+  output      [23:0]  dac_data,
+  input       [23:0]  adc_data,
+
+  // delay interface
+
+  output      [13:0]  up_dld,
+  output      [69:0]  up_dwdata,
+  input       [69:0]  up_drdata,
+  input               delay_clk,
+  output              delay_rst,
+  input               delay_locked,
+
+  // master/slave
+
+  input               dac_sync_in,
+  output              dac_sync_out,
+
+  // dma interface
+
+  output              dac_enable_i,
+  output reg          dac_valid_i,
+  input       [15:0]  dac_data_i,
+  output              dac_enable_q,
+  output reg          dac_valid_q,
+  input       [15:0]  dac_data_q,
+  input               dac_dovf,
+  input               dac_dunf,
+
+  // processor interface
+
+  input               up_rstn,
+  input               up_clk,
+  input               up_wreq,
+  input       [13:0]  up_waddr,
+  input       [31:0]  up_wdata,
+  output reg          up_wack,
+  input               up_rreq,
+  input       [13:0]  up_raddr,
+  output reg  [31:0]  up_rdata,
+  output reg          up_rack);
+
+  // internal registers
+
+  reg             dac_data_sync = 'd0;
+  reg     [ 7:0]  dac_rate_cnt = 'd0;
+
+  // internal clock and resets
+
+  wire            dac_rst;
+
+  // internal signals
+
+  wire            dac_data_sync_s;
+  wire            dac_dds_format_s;
+  wire    [ 7:0]  dac_datarate_s;
+  wire    [23:0]  dac_data_int_s;
+  wire    [31:0]  up_rdata_s[0:3];
+  wire            up_rack_s[0:3];
+  wire            up_wack_s[0:3];
+
+  // master/slave
+
+  assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
+
+  always @(posedge dac_clk) begin
+    dac_data_sync <= dac_data_sync_s;
+  end
+
+  // rate counters and data sync signals
+
+  always @(posedge dac_clk) begin
+    if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin
+      dac_rate_cnt <= dac_datarate_s;
+    end else begin
+      dac_rate_cnt <= dac_rate_cnt - 1'b1;
+    end
+  end
+
+  // dma interface
+
+  always @(posedge dac_clk) begin
+    dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
+    dac_valid_i <= dac_valid;
+    dac_valid_q <= dac_valid;
+  end
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rdata <= 'd0;
+      up_rack <= 'd0;
+      up_wack <= 'd0;
+    end else begin
+      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
+      up_rack <=  up_rack_s[0]  | up_rack_s[1]  | up_rack_s[2]  | up_rack_s[3];
+      up_wack <=  up_wack_s[0]  | up_wack_s[1]  | up_wack_s[2]  | up_wack_s[3];
+    end
+  end
+
+  // dac channel
+
+  axi_ad9963_tx_channel #(
+    .CHANNEL_ID (0),
+    .Q_OR_I_N (0),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+  i_tx_channel_0 (
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_valid (dac_valid),
+    .dma_data (dac_data_i),
+    .adc_data (adc_data[11:0]),
+    .dac_data (dac_data[11:0]),
+    .dac_data_out (dac_data_int_s[11:0]),
+    .dac_data_in (dac_data_int_s[23:12]),
+    .dac_enable (dac_enable_i),
+    .dac_data_sync (dac_data_sync),
+    .dac_dds_format (dac_dds_format_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  // dac channel
+
+  axi_ad9963_tx_channel #(
+    .CHANNEL_ID (1),
+    .Q_OR_I_N (1),
+    .DATAPATH_DISABLE (DATAPATH_DISABLE))
+  i_tx_channel_1 (
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_valid (dac_valid),
+    .dma_data (dac_data_q),
+    .adc_data (adc_data[23:12]),
+    .dac_data (dac_data[23:12]),
+    .dac_data_out (dac_data_int_s[23:12]),
+    .dac_data_in (dac_data_int_s[11:0]),
+    .dac_enable (dac_enable_q),
+    .dac_data_sync (dac_data_sync),
+    .dac_dds_format (dac_dds_format_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[1]),
+    .up_rack (up_rack_s[1]));
+
+  // dac common processor interface
+
+  up_dac_common #(.ID (ID)) i_up_dac_common (
+    .mmcm_rst (),
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_sync (dac_sync_out),
+    .dac_frame (),
+    .dac_clksel(),
+    .dac_par_type (),
+    .dac_par_enb (),
+    .dac_r1_mode (),
+    .dac_datafmt (dac_dds_format_s),
+    .dac_datarate (dac_datarate_s),
+    .dac_status (1'b1),
+    .dac_status_ovf (dac_dovf),
+    .dac_status_unf (dac_dunf),
+    .dac_clk_ratio (32'd1),
+    .up_drp_sel (),
+    .up_drp_wr (),
+    .up_drp_addr (),
+    .up_drp_wdata (),
+    .up_drp_rdata (16'd0),
+    .up_drp_ready (1'd0),
+    .up_drp_locked (1'd1),
+    .up_usr_chanmax (),
+    .dac_usr_chanmax (8'd2),
+    .up_dac_gpio_in (32'h0),
+    .up_dac_gpio_out (),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[2]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[2]),
+    .up_rack (up_rack_s[2]));
+
+  // dac delay control
+
+  up_delay_cntrl #(.DATA_WIDTH(14), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked),
+    .up_dld (up_dld),
+    .up_dwdata (up_dwdata),
+    .up_drdata (up_drdata),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack_s[3]),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata_s[3]),
+    .up_rack (up_rack_s[3]));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963_tx_channel.v b/library/axi_ad9963/axi_ad9963_tx_channel.v
new file mode 100644
index 000000000..707843659
--- /dev/null
+++ b/library/axi_ad9963/axi_ad9963_tx_channel.v
@@ -0,0 +1,415 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9963_tx_channel #(
+
+  // parameters
+
+  parameter   CHANNEL_ID = 32'h0,
+  parameter   Q_OR_I_N = 0,
+  parameter   DATAPATH_DISABLE = 0,
+  localparam  PRBS_SEL = CHANNEL_ID,
+  localparam  PRBS_P09  = 0,
+  localparam  PRBS_P11  = 1,
+  localparam  PRBS_P15  = 2,
+  localparam  PRBS_P20  = 3) (
+
+  // dac interface
+
+  input               dac_clk,
+  input               dac_rst,
+  input               dac_valid,
+  input       [15:0]  dma_data,
+  input       [11:0]  adc_data,
+  output reg  [11:0]  dac_data,
+  output reg  [11:0]  dac_data_out,
+  input       [11:0]  dac_data_in,
+
+  // processor interface
+
+  output  reg         dac_enable,
+  input               dac_data_sync,
+  input               dac_dds_format,
+
+  // bus interface
+
+  input               up_rstn,
+  input               up_clk,
+  input               up_wreq,
+  input       [13:0]  up_waddr,
+  input       [31:0]  up_wdata,
+  output              up_wack,
+  input               up_rreq,
+  input       [13:0]  up_raddr,
+  output      [31:0]  up_rdata,
+  output              up_rack);
+
+  // internal registers
+
+  reg             dac_valid_sel = 'd0;
+  reg     [23:0]  dac_test_data = 'd0;
+  reg     [15:0]  dac_test_counter = 'd0;
+  reg     [23:0]  dac_pn_seq = 'd0;
+  reg     [11:0]  dac_pn_data = 'd0;
+  reg     [15:0]  dac_pat_data = 'd0;
+  reg     [15:0]  dac_dds_phase_0 = 'd0;
+  reg     [15:0]  dac_dds_phase_1 = 'd0;
+  reg     [15:0]  dac_dds_incr_0 = 'd0;
+  reg     [15:0]  dac_dds_incr_1 = 'd0;
+  reg     [15:0]  dac_dds_data = 'd0;
+
+  // internal signals
+
+  wire            dac_iqcor_valid_s;
+  wire    [15:0]  dac_iqcor_data_s;
+  wire    [15:0]  dac_dds_data_s;
+  wire    [15:0]  dac_dds_scale_1_s;
+  wire    [15:0]  dac_dds_init_1_s;
+  wire    [15:0]  dac_dds_incr_1_s;
+  wire    [15:0]  dac_dds_scale_2_s;
+  wire    [15:0]  dac_dds_init_2_s;
+  wire    [15:0]  dac_dds_incr_2_s;
+  wire    [15:0]  dac_pat_data_1_s;
+  wire    [15:0]  dac_pat_data_2_s;
+  wire    [ 3:0]  dac_data_sel_s;
+  wire            dac_iqcor_enb_s;
+  wire    [15:0]  dac_iqcor_coeff_1_s;
+  wire    [15:0]  dac_iqcor_coeff_2_s;
+
+  // standard prbs functions
+
+  function [23:0] pn1fn;
+    input [23:0] din;
+    reg   [23:0] dout;
+    begin
+      case (PRBS_SEL)
+        PRBS_P09: begin
+          dout[23] = din[ 8] ^ din[ 4];
+          dout[22] = din[ 7] ^ din[ 3];
+          dout[21] = din[ 6] ^ din[ 2];
+          dout[20] = din[ 5] ^ din[ 1];
+          dout[19] = din[ 4] ^ din[ 0];
+          dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
+          dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
+          dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
+          dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
+          dout[14] = din[ 8] ^ din[ 0];
+          dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
+          dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
+          dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
+          dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
+          dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
+          dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
+          dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
+          dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
+          dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
+          dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
+          dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
+          dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
+          dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
+          dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
+        end
+        PRBS_P11: begin
+          dout[23] = din[10] ^ din[ 8];
+          dout[22] = din[ 9] ^ din[ 7];
+          dout[21] = din[ 8] ^ din[ 6];
+          dout[20] = din[ 7] ^ din[ 5];
+          dout[19] = din[ 6] ^ din[ 4];
+          dout[18] = din[ 5] ^ din[ 3];
+          dout[17] = din[ 4] ^ din[ 2];
+          dout[16] = din[ 3] ^ din[ 1];
+          dout[15] = din[ 2] ^ din[ 0];
+          dout[14] = din[ 1] ^ din[10] ^ din[ 8];
+          dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
+          dout[12] = din[10] ^ din[ 6];
+          dout[11] = din[ 9] ^ din[ 5];
+          dout[10] = din[ 8] ^ din[ 4];
+          dout[ 9] = din[ 7] ^ din[ 3];
+          dout[ 8] = din[ 6] ^ din[ 2];
+          dout[ 7] = din[ 5] ^ din[ 1];
+          dout[ 6] = din[ 4] ^ din[ 0];
+          dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
+          dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
+          dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
+          dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
+          dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
+          dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
+        end
+        PRBS_P15: begin
+          dout[23] = din[14] ^ din[13];
+          dout[22] = din[13] ^ din[12];
+          dout[21] = din[12] ^ din[11];
+          dout[20] = din[11] ^ din[10];
+          dout[19] = din[10] ^ din[ 9];
+          dout[18] = din[ 9] ^ din[ 8];
+          dout[17] = din[ 8] ^ din[ 7];
+          dout[16] = din[ 7] ^ din[ 6];
+          dout[15] = din[ 6] ^ din[ 5];
+          dout[14] = din[ 5] ^ din[ 4];
+          dout[13] = din[ 4] ^ din[ 3];
+          dout[12] = din[ 3] ^ din[ 2];
+          dout[11] = din[ 2] ^ din[ 1];
+          dout[10] = din[ 1] ^ din[ 0];
+          dout[ 9] = din[ 0] ^ din[14] ^ din[13];
+          dout[ 8] = din[14] ^ din[12];
+          dout[ 7] = din[13] ^ din[11];
+          dout[ 6] = din[12] ^ din[10];
+          dout[ 5] = din[11] ^ din[ 9];
+          dout[ 4] = din[10] ^ din[ 8];
+          dout[ 3] = din[ 9] ^ din[ 7];
+          dout[ 2] = din[ 8] ^ din[ 6];
+          dout[ 1] = din[ 7] ^ din[ 5];
+          dout[ 0] = din[ 6] ^ din[ 4];
+        end
+        PRBS_P20: begin
+          dout[23] = din[19] ^ din[ 2];
+          dout[22] = din[18] ^ din[ 1];
+          dout[21] = din[17] ^ din[ 0];
+          dout[20] = din[16] ^ din[19] ^ din[ 2];
+          dout[19] = din[15] ^ din[18] ^ din[ 1];
+          dout[18] = din[14] ^ din[17] ^ din[ 0];
+          dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
+          dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
+          dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
+          dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
+          dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
+          dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
+          dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
+          dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
+          dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
+          dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
+          dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
+          dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
+          dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
+          dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
+          dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
+          dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
+          dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
+          dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
+        end
+      endcase
+      pn1fn = dout;
+    end
+  endfunction
+
+  // global toggle
+
+  always @(posedge dac_clk) begin
+    if (dac_data_sync == 1'b1) begin
+      dac_valid_sel <= 1'b0;
+    end else if (dac_valid == 1'b1) begin
+      dac_valid_sel <= ~dac_valid_sel;
+    end
+  end
+
+  // dac iq correction
+
+  always @(posedge dac_clk) begin
+    dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
+    if (dac_iqcor_valid_s == 1'b1) begin
+      dac_data <= dac_iqcor_data_s[15:4];
+    end
+  end
+
+  generate
+  if (DATAPATH_DISABLE == 1) begin
+  assign dac_iqcor_valid_s = dac_valid;
+  assign dac_iqcor_data_s = {dac_data_out, 4'd0};
+  end else begin
+  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
+    .clk (dac_clk),
+    .valid (dac_valid),
+    .data_in ({dac_data_out, 4'd0}),
+    .data_iq ({dac_data_in, 4'd0}),
+    .valid_out (dac_iqcor_valid_s),
+    .data_out (dac_iqcor_data_s),
+    .iqcor_enable (dac_iqcor_enb_s),
+    .iqcor_coeff_1 (dac_iqcor_coeff_1_s),
+    .iqcor_coeff_2 (dac_iqcor_coeff_2_s));
+  end
+  endgenerate
+
+  // dac mux
+
+  always @(posedge dac_clk) begin
+    case (dac_data_sel_s)
+      4'h9: dac_data_out <= dac_pn_data;
+      4'h8: dac_data_out <= 16'h0;
+      4'h6: dac_data_out <= dac_test_data[11:0];
+      4'h5: dac_data_out <= dac_data_out-1;
+      4'h4: dac_data_out <= dac_data_out+1;
+      4'h3: dac_data_out <= 12'd0;
+      4'h2: dac_data_out <= dma_data[15:4];
+      4'h1: dac_data_out <= dac_pat_data[15:4];
+      default: dac_data_out <= dac_dds_data[15:4];
+    endcase
+  end
+
+ function [23:0] pn23;
+    input [23:0] din;
+    reg   [23:0] dout;
+    begin
+      dout = {din[22:0], din[22] ^ din[17]};
+      pn23 = dout;
+    end
+  endfunction
+
+  always @(posedge dac_clk) begin
+    if(dac_data_sel_s != 6) begin
+      dac_test_data <= 24'hffffff;
+      dac_test_counter <= 16'h0;
+    end else if (dac_test_counter == 1024) begin
+      dac_test_data <= 24'h0;
+    end else begin
+      dac_test_data <= pn23(dac_test_data);
+      dac_test_counter <= dac_test_counter + 1;
+    end
+  end
+
+  // prbs sequences
+
+  always @(posedge dac_clk) begin
+    if (dac_data_sync == 1'b1) begin
+      dac_pn_seq <= 24'hffffff;
+      dac_pn_data <= 12'd0;
+    end else if (dac_valid == 1'b1) begin
+      if (dac_valid_sel == 1'b1) begin
+        dac_pn_seq <= pn1fn(dac_pn_seq);
+        dac_pn_data <= dac_pn_seq[11: 0];
+      end else begin
+        dac_pn_seq <= dac_pn_seq;
+        dac_pn_data <= dac_pn_seq[23:12];
+      end
+    end
+  end
+
+  // pattern
+
+  always @(posedge dac_clk) begin
+    if (dac_valid == 1'b1) begin
+      if (dac_valid_sel == 1'b0) begin
+        dac_pat_data <= dac_pat_data_1_s;
+      end else begin
+        dac_pat_data <= dac_pat_data_2_s;
+      end
+    end
+  end
+
+  // dds
+
+  always @(posedge dac_clk) begin
+    if (dac_data_sync == 1'b1) begin
+      dac_dds_phase_0 <= dac_dds_init_1_s;
+      dac_dds_phase_1 <= dac_dds_init_2_s;
+      dac_dds_incr_0 <= dac_dds_incr_1_s;
+      dac_dds_incr_1 <= dac_dds_incr_2_s;
+      dac_dds_data <= 16'd0;
+    end else if (dac_valid == 1'b1) begin
+      dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_0;
+      dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_1;
+      dac_dds_incr_0 <= dac_dds_incr_0;
+      dac_dds_incr_1 <= dac_dds_incr_1;
+      dac_dds_data <= dac_dds_data_s;
+    end
+  end
+
+  // dds
+
+  generate
+  if (DATAPATH_DISABLE == 1) begin
+  assign dac_dds_data_s = 16'd0;
+  end else begin
+  ad_dds i_dds (
+    .clk (dac_clk),
+    .dds_format (dac_dds_format),
+    .dds_phase_0 (dac_dds_phase_0),
+    .dds_scale_0 (dac_dds_scale_1_s),
+    .dds_phase_1 (dac_dds_phase_1),
+    .dds_scale_1 (dac_dds_scale_2_s),
+    .dds_data (dac_dds_data_s));
+  end
+  endgenerate
+
+  // single channel processor
+
+  up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+    .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
+    .dac_dds_scale_1 (dac_dds_scale_1_s),
+    .dac_dds_init_1 (dac_dds_init_1_s),
+    .dac_dds_incr_1 (dac_dds_incr_1_s),
+    .dac_dds_scale_2 (dac_dds_scale_2_s),
+    .dac_dds_init_2 (dac_dds_init_2_s),
+    .dac_dds_incr_2 (dac_dds_incr_2_s),
+    .dac_pat_data_1 (dac_pat_data_1_s),
+    .dac_pat_data_2 (dac_pat_data_2_s),
+    .dac_iq_mode(),
+    .dac_data_sel (dac_data_sel_s),
+    .dac_iqcor_enb (dac_iqcor_enb_s),
+    .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
+    .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
+    .up_usr_datatype_be (),
+    .up_usr_datatype_signed (),
+    .up_usr_datatype_shift (),
+    .up_usr_datatype_total_bits (),
+    .up_usr_datatype_bits (),
+    .up_usr_interpolation_m (),
+    .up_usr_interpolation_n (),
+    .dac_usr_datatype_be (1'b0),
+    .dac_usr_datatype_signed (1'b1),
+    .dac_usr_datatype_shift (8'd0),
+    .dac_usr_datatype_total_bits (8'd16),
+    .dac_usr_datatype_bits (8'd16),
+    .dac_usr_interpolation_m (16'd1),
+    .dac_usr_interpolation_n (16'd1),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 35b97abc6d01a2f1bbf48ed9055fd84fa1d31df3 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:20:13 +0200
Subject: [PATCH 878/972] axi_adc_trigger: Initial commit

---
 library/axi_adc_trigger/Makefile              |  50 +++
 library/axi_adc_trigger/axi_adc_trigger.v     | 413 ++++++++++++++++++
 .../axi_adc_trigger_constr.xdc                |  12 +
 .../axi_adc_trigger/axi_adc_trigger_ip.tcl    |  22 +
 library/axi_adc_trigger/axi_adc_trigger_reg.v | 241 ++++++++++
 5 files changed, 738 insertions(+)
 create mode 100644 library/axi_adc_trigger/Makefile
 create mode 100644 library/axi_adc_trigger/axi_adc_trigger.v
 create mode 100644 library/axi_adc_trigger/axi_adc_trigger_constr.xdc
 create mode 100644 library/axi_adc_trigger/axi_adc_trigger_ip.tcl
 create mode 100644 library/axi_adc_trigger/axi_adc_trigger_reg.v

diff --git a/library/axi_adc_trigger/Makefile b/library/axi_adc_trigger/Makefile
new file mode 100644
index 000000000..c2ab354f1
--- /dev/null
+++ b/library/axi_adc_trigger/Makefile
@@ -0,0 +1,50 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += axi_adc_trigger.v
+M_DEPS += axi_adc_trigger_constr.xdc
+M_DEPS += axi_adc_trigger_ip.tcl
+M_DEPS += axi_adc_trigger_reg.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_adc_trigger.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_adc_trigger.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_adc_trigger_ip.tcl  >> axi_adc_trigger_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v
new file mode 100644
index 000000000..dde4990bc
--- /dev/null
+++ b/library/axi_adc_trigger/axi_adc_trigger.v
@@ -0,0 +1,413 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_adc_trigger(
+
+  input                 clk,
+
+  input       [ 1:0]    trigger_i,
+  output      [ 1:0]    trigger_o,
+  output      [ 1:0]    trigger_t,
+
+  input       [15:0]    data_a,
+  input       [15:0]    data_b,
+  input                 data_valid_a,
+  input                 data_valid_b,
+
+  output      [15:0]    data_a_trig,
+  output      [15:0]    data_b_trig,
+  output                data_valid_a_trig,
+  output                data_valid_b_trig,
+
+  output      [31:0]    trigger_offset,
+
+  // axi interface
+
+  input                 s_axi_aclk,
+  input                 s_axi_aresetn,
+  input                 s_axi_awvalid,
+  input       [31:0]    s_axi_awaddr,
+  input       [ 2:0]    s_axi_awprot,
+  output                s_axi_awready,
+  input                 s_axi_wvalid,
+  input       [31:0]    s_axi_wdata,
+  input       [ 3:0]    s_axi_wstrb,
+  output                s_axi_wready,
+  output                s_axi_bvalid,
+  output      [ 1:0]    s_axi_bresp,
+  input                 s_axi_bready,
+  input                 s_axi_arvalid,
+  input       [31:0]    s_axi_araddr,
+  input       [ 2:0]    s_axi_arprot,
+  output                s_axi_arready,
+  output                s_axi_rvalid,
+  output      [31:0]    s_axi_rdata,
+  output      [ 1:0]    s_axi_rresp,
+  input                 s_axi_rready);
+
+  // internal signals
+
+  wire              up_clk;
+  wire              up_rstn;
+  wire    [13:0]    up_waddr;
+  wire    [31:0]    up_wdata;
+  wire              up_wack;
+  wire              up_wreq;
+  wire              up_rack;
+  wire    [31:0]    up_rdata;
+  wire              up_rreq;
+  wire    [13:0]    up_raddr;
+
+  wire    [ 1:0]    io_selection;
+
+  wire    [ 1:0]    low_level;
+  wire    [ 1:0]    high_level;
+  wire    [ 1:0]    any_edge;
+  wire    [ 1:0]    rise_edge;
+  wire    [ 1:0]    fall_edge;
+
+  wire    [15:0]    limit_a;
+  wire    [ 1:0]    function_a;
+  wire    [31:0]    hysteresis_a;
+  wire    [ 3:0]    trigger_l_mix_a;
+
+  wire    [15:0]    limit_b;
+  wire    [ 1:0]    function_b;
+  wire    [31:0]    hysteresis_b;
+  wire    [ 3:0]    trigger_l_mix_b;
+
+  wire    [ 2:0]    trigger_out_mix;
+  wire    [31:0]    delay_trigger;
+
+  wire    [15:0]    data_a_cmp;
+  wire    [15:0]    data_b_cmp;
+  wire    [15:0]    limit_a_cmp;
+  wire    [15:0]    limit_b_cmp;
+
+  wire              trigger_a_fall_edge;
+  wire              trigger_a_rise_edge;
+  wire              trigger_b_fall_edge;
+  wire              trigger_b_rise_edge;
+  wire              trigger_a_any_edge;
+  wire              trigger_b_any_edge;
+  wire              trigger_out_a;
+  wire              trigger_out_b;
+
+  reg               trigger_a_d1; // synchronization flip flop
+  reg               trigger_a_d2; // synchronization flip flop
+  reg               trigger_a_d3;
+  reg               trigger_b_d1; // synchronization flip flop
+  reg               trigger_b_d2; // synchronization flip flop
+  reg               trigger_b_d3;
+  reg               passthrough_high_a; // trigger when rising through the limit
+  reg               passthrough_low_a;  // trigger when fallingh thorugh the limit
+  reg               low_a; // signal was under the limit, so if it goes through, assert rising
+  reg               high_a; // signal was over the limit, so if it passes through, assert falling
+  reg               comp_high_a;  // signal is over the limit
+  reg               comp_low_a;   // signal is under the limit
+  reg               passthrough_high_b; // trigger when rising through the limit
+  reg               passthrough_low_b;  // trigger when fallingh thorugh the limit
+  reg               low_b;   // signal was under the limit, so if it goes through, assert rising
+  reg               high_b;   // signal was over the limit, so if it passes through, assert falling
+  reg               comp_high_b;  // signal is over the limit
+  reg               comp_low_b;   // signal is under the limit
+
+  reg               trigger_pin_a;
+  reg               trigger_pin_b;
+
+  reg               trigger_adc_a;
+  reg               trigger_adc_b;
+
+  reg               trigger_a;
+  reg               trigger_b;
+
+  reg               trigger_out_mixed;
+
+  reg     [15:0]    data_a_r;
+  reg     [15:0]    data_b_r;
+  reg               data_valid_a_r;
+  reg               data_valid_b_r;
+
+  // signal name changes
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+
+  assign trigger_offset = delay_trigger;
+
+  assign trigger_t = io_selection;
+
+  assign trigger_a_fall_edge = (trigger_a_d2 == 1'b0 && trigger_a_d3 == 1'b1) ? 1'b1: 1'b0;
+  assign trigger_a_rise_edge = (trigger_a_d2 == 1'b1 && trigger_a_d3 == 1'b0) ? 1'b1: 1'b0;
+  assign trigger_a_any_edge = trigger_a_rise_edge | trigger_a_fall_edge;
+  assign trigger_b_fall_edge = (trigger_b_d2 == 1'b0 && trigger_b_d3 == 1'b1) ? 1'b1: 1'b0;
+  assign trigger_b_rise_edge = (trigger_b_d2 == 1'b1 && trigger_b_d3 == 1'b0) ? 1'b1: 1'b0;
+  assign trigger_b_any_edge = trigger_b_rise_edge | trigger_b_fall_edge;
+
+  assign data_a_cmp   = {!data_a[15],data_a[14:0]};
+  assign data_b_cmp   = {!data_b[15],data_b[14:0]};
+  assign limit_a_cmp  = {!limit_a[15],limit_a[14:0]};
+  assign limit_b_cmp  = {!limit_b[15],limit_b[14:0]};
+
+  assign data_a_trig = {trigger_out_mixed, data_a_r[14:0]};
+  assign data_b_trig = {trigger_out_mixed, data_b_r[14:0]};;
+  assign data_valid_a_trig = data_valid_a_r;
+  assign data_valid_b_trig = data_valid_b_r;
+
+  always @(posedge clk) begin
+    data_a_r <= data_a;
+    data_valid_a_r <= data_valid_a;
+    data_b_r <= data_b;
+    data_valid_b_r <= data_valid_b;
+  end
+
+  always @(*) begin
+    case(trigger_l_mix_a)
+      4'h0: trigger_a = 1'b1;
+      4'h1: trigger_a = trigger_pin_a;
+      4'h2: trigger_a = trigger_adc_a;
+      4'h4: trigger_a = trigger_pin_a | trigger_adc_a ;
+      4'h5: trigger_a = trigger_pin_a & trigger_adc_a ;
+      4'h6: trigger_a = trigger_pin_a ^ trigger_adc_a ;
+      4'h7: trigger_a = !(trigger_pin_a | trigger_adc_a) ;
+      4'h8: trigger_a = !(trigger_pin_a & trigger_adc_a) ;
+      4'h9: trigger_a = !(trigger_pin_a ^ trigger_adc_a) ;
+      default: trigger_a = 1'b1;
+    endcase
+  end
+
+  always @(*) begin
+    case(trigger_l_mix_b)
+      4'h0: trigger_b = 1'b1;
+      4'h1: trigger_b = trigger_pin_b;
+      4'h2: trigger_b = trigger_adc_b;
+      4'h4: trigger_b = trigger_pin_b | trigger_adc_b ;
+      4'h5: trigger_b = trigger_pin_b & trigger_adc_b ;
+      4'h6: trigger_b = trigger_pin_b ^ trigger_adc_b ;
+      4'h7: trigger_b = !(trigger_pin_b | trigger_adc_b) ;
+      4'h8: trigger_b = !(trigger_pin_b & trigger_adc_b) ;
+      4'h9: trigger_b = !(trigger_pin_b ^ trigger_adc_b) ;
+      default: trigger_b = 1'b1;
+    endcase
+  end
+
+  always @(*) begin
+    case(function_a)
+      2'h0: trigger_adc_a = comp_low_a;
+      2'h1: trigger_adc_a = comp_high_a;
+      2'h2: trigger_adc_a = passthrough_high_a;
+      2'h3: trigger_adc_a = passthrough_low_a;
+      default: trigger_adc_a = comp_low_a;
+    endcase
+  end
+
+  always @(*) begin
+    case(function_b)
+      2'h0: trigger_adc_b = comp_low_b;
+      2'h1: trigger_adc_b = comp_high_b;
+      2'h2: trigger_adc_b = passthrough_high_b;
+      2'h3: trigger_adc_b = passthrough_low_b;
+      default: trigger_adc_b = comp_low_b;
+    endcase
+  end
+
+  always @(posedge clk) begin
+    trigger_a_d1 <= trigger_i[0];
+    trigger_a_d2 <= trigger_a_d1;
+    trigger_a_d3 <= trigger_a_d2;
+    trigger_b_d1 <= trigger_i[1];
+    trigger_b_d2 <= trigger_b_d1;
+    trigger_b_d3 <= trigger_b_d2;
+  end
+
+  always @(*) begin
+    trigger_pin_a = ((!trigger_a_d3 & low_level[0]) |
+      (trigger_a_d3 & high_level[0]) |
+      (trigger_a_fall_edge & fall_edge[0]) |
+      (trigger_a_rise_edge & rise_edge[0]) |
+      (trigger_a_any_edge & any_edge[0]));
+  end
+
+  always @(*) begin
+    trigger_pin_b = ((!trigger_b_d3 & low_level[1]) |
+      (trigger_b_d3 & high_level[1]) |
+      (trigger_b_fall_edge & fall_edge[1]) |
+      (trigger_b_rise_edge & rise_edge[1]) |
+      (trigger_b_any_edge & any_edge[1]));
+  end
+
+   always @(*) begin
+    case(trigger_out_mix)
+      3'h0: trigger_out_mixed = trigger_a;
+      3'h1: trigger_out_mixed = trigger_b;
+      3'h2: trigger_out_mixed = trigger_a | trigger_b;
+      3'h3: trigger_out_mixed = trigger_a & trigger_b;
+      3'h4: trigger_out_mixed = trigger_a ^ trigger_b;
+      default: trigger_out_mixed = trigger_a;
+    endcase
+  end
+
+  always @(posedge clk) begin
+    if (data_valid_a == 1'b1) begin
+      if (data_a_cmp > limit_a_cmp) begin
+        comp_high_a <= 1'b1;
+        passthrough_high_a <= low_a;
+      end else begin
+        comp_high_a <= 1'b0;
+        passthrough_high_a <= 1'b0;
+      end
+      if (data_a_cmp < limit_a_cmp) begin
+        comp_low_a <= 1'b1;
+        passthrough_low_a <= high_a;
+      end else begin
+        comp_low_a <= 1'b0;
+        passthrough_low_a <= 1'b0;
+      end
+      if (passthrough_high_a == 1'b1) begin
+        low_a <= 1'b0;
+      end else if (data_a_cmp < limit_a_cmp - hysteresis_a) begin
+        low_a <= 1'b1;
+      end
+      if (passthrough_low_a == 1'b1) begin
+        high_a <= 1'b0;
+      end else if (data_a_cmp > limit_a_cmp + hysteresis_a) begin
+        high_a <= 1'b1;
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (data_valid_b == 1'b1) begin
+      if (data_b_cmp > limit_b_cmp) begin
+        comp_high_b <= 1'b1;
+        passthrough_high_b <= low_b;
+      end else begin
+        comp_high_b <= 1'b0;
+        passthrough_high_b <= 1'b0;
+      end
+      if (data_b_cmp < limit_b_cmp) begin
+        comp_low_b <= 1'b1;
+        passthrough_low_b <= high_b;
+      end else begin
+        comp_low_b <= 1'b0;
+        passthrough_low_b <= 1'b0;
+      end
+      if (trigger_b == 1'b1) begin
+        low_b <= 1'b0;
+        high_b <= 1'b0;
+      end else if (data_b_cmp < limit_b_cmp - hysteresis_b) begin
+        low_b <= 1'b1;
+      end else if (data_b_cmp > limit_b_cmp + hysteresis_b) begin
+        high_b <= 1'b1;
+      end
+    end
+  end
+
+  axi_adc_trigger_reg adc_trigger_registers (
+
+  .clk(clk),
+
+  .io_selection(io_selection),
+  .trigger_o(trigger_o),
+
+  .low_level(low_level),
+  .high_level(high_level),
+  .any_edge(any_edge),
+  .rise_edge(rise_edge),
+  .fall_edge(fall_edge),
+
+  .limit_a(limit_a),
+  .function_a(function_a),
+  .hysteresis_a(hysteresis_a),
+  .trigger_l_mix_a(trigger_l_mix_a),
+
+  .limit_b(limit_b),
+  .function_b(function_b),
+  .hysteresis_b(hysteresis_b),
+  .trigger_l_mix_b(trigger_l_mix_b),
+
+  .trigger_out_mix(trigger_out_mix),
+  .delay_trigger(delay_trigger),
+
+  // bus interface
+
+  .up_rstn(up_rstn),
+  .up_clk(up_clk),
+  .up_wreq(up_wreq),
+  .up_waddr(up_waddr),
+  .up_wdata(up_wdata),
+  .up_wack(up_wack),
+  .up_rreq(up_rreq),
+  .up_raddr(up_raddr),
+  .up_rdata(up_rdata),
+  .up_rack(up_rack));
+
+ up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_adc_trigger/axi_adc_trigger_constr.xdc b/library/axi_adc_trigger/axi_adc_trigger_constr.xdc
new file mode 100644
index 000000000..d8c0c576e
--- /dev/null
+++ b/library/axi_adc_trigger/axi_adc_trigger_constr.xdc
@@ -0,0 +1,12 @@
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *trigger_a_d*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *trigger_b_d*}]
+
+set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg   && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg   && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data*       && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl*          && IS_SEQUENTIAL}]
+set_false_path                                                                                 -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg*          && IS_SEQUENTIAL}]
+set_false_path                                                                                 -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg*          && IS_SEQUENTIAL}]
+
diff --git a/library/axi_adc_trigger/axi_adc_trigger_ip.tcl b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl
new file mode 100644
index 000000000..1cefb23be
--- /dev/null
+++ b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl
@@ -0,0 +1,22 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_adc_trigger
+adi_ip_files axi_adc_trigger [list \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "axi_adc_trigger_constr.xdc" \
+  "axi_adc_trigger_reg.v" \
+  "axi_adc_trigger.v" ]
+
+adi_ip_properties axi_adc_trigger
+adi_ip_constraints axi_adc_trigger [list \
+  "axi_adc_trigger_constr.xdc" ]
+
+ipx::remove_bus_interface {clk} [ipx::current_core]
+ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+
diff --git a/library/axi_adc_trigger/axi_adc_trigger_reg.v b/library/axi_adc_trigger/axi_adc_trigger_reg.v
new file mode 100644
index 000000000..62d530553
--- /dev/null
+++ b/library/axi_adc_trigger/axi_adc_trigger_reg.v
@@ -0,0 +1,241 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_adc_trigger_reg (
+
+  input               clk,
+
+  output reg  [ 1:0]  io_selection,
+  output reg  [ 1:0]  trigger_o,
+
+  output      [ 1:0]  low_level,
+  output      [ 1:0]  high_level,
+  output      [ 1:0]  any_edge,
+  output      [ 1:0]  rise_edge,
+  output      [ 1:0]  fall_edge,
+
+  output      [15:0]  limit_a,
+  output      [ 1:0]  function_a,
+  output      [31:0]  hysteresis_a,
+  output      [ 3:0]  trigger_l_mix_a,
+
+  output      [15:0]  limit_b,
+  output      [ 1:0]  function_b,
+  output      [31:0]  hysteresis_b,
+  output      [ 3:0]  trigger_l_mix_b,
+
+  output      [ 2:0]  trigger_out_mix,
+  output      [31:0]  delay_trigger,
+
+ // bus interface
+
+  input               up_rstn,
+  input               up_clk,
+  input               up_wreq,
+  input       [13:0]  up_waddr,
+  input       [31:0]  up_wdata,
+  output reg          up_wack,
+  input               up_rreq,
+  input       [13:0]  up_raddr,
+  output reg  [31:0]  up_rdata,
+  output reg          up_rack);
+
+  // internal signals
+
+  wire            up_wreq_s;
+  wire            up_rreq_s;
+  wire    [ 9:0]  config_trigger;
+
+  // internal registers
+
+  reg     [31:0]  up_version = 32'h00010000;
+  reg     [31:0]  up_scratch = 32'h0;
+  reg     [ 9:0]  up_config_trigger = 10'h0;
+  reg     [15:0]  up_limit_a = 16'h0;
+  reg     [ 1:0]  up_function_a = 2'h0;
+  reg     [31:0]  up_hysteresis_a = 32'h0;
+  reg     [ 3:0]  up_trigger_l_mix_a = 32'h0;
+  reg     [15:0]  up_limit_b = 16'h0;
+  reg     [ 1:0]  up_function_b = 2'h0;
+  reg     [31:0]  up_hysteresis_b = 32'h0;
+  reg     [ 3:0]  up_trigger_l_mix_b = 32'h0;
+  reg     [ 2:0]  up_trigger_out_mix = 32'h0;
+  reg     [31:0]  up_delay_trigger= 32'h0;
+
+  assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
+  assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
+
+  assign low_level  = config_trigger[1:0];
+  assign high_level = config_trigger[3:2];
+  assign any_edge   = config_trigger[5:4];
+  assign rise_edge  = config_trigger[7:6];
+  assign fall_edge  = config_trigger[9:8];
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_scratch <= 'd0;
+      io_selection <= 'd3;
+      trigger_o <= 'd0;
+      up_config_trigger <= 'd0;
+      up_limit_a <= 'd0;
+      up_function_a <= 'd0;
+      up_hysteresis_a <= 'd0;
+      up_limit_b <= 'd0;
+      up_function_b <= 'd0;
+      up_hysteresis_b <= 'd0;
+      up_delay_trigger <= 'd0;
+      up_trigger_l_mix_a <= 'd0;
+      up_trigger_l_mix_b <= 'd0;
+      up_trigger_out_mix <= 'd0;
+    end else begin
+      up_wack <= up_wreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
+        up_scratch <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
+        trigger_o <= up_wdata[1:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
+        io_selection <= up_wdata[1:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
+        up_config_trigger <= up_wdata[9:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
+        up_limit_a <= up_wdata[15:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
+        up_function_a <= up_wdata[1:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
+        up_hysteresis_a <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
+        up_trigger_l_mix_a <= up_wdata[3:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
+        up_limit_b <= up_wdata[15:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
+        up_function_b <= up_wdata[1:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
+        up_hysteresis_b <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
+        up_trigger_l_mix_b <= up_wdata[3:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
+        up_trigger_out_mix <= up_wdata[2:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'he)) begin
+        up_delay_trigger <= up_wdata;
+      end
+    end
+  end
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_rack <= up_rreq_s;
+      if (up_rreq_s == 1'b1) begin
+        case (up_raddr[4:0])
+          5'h0: up_rdata <= up_version;
+          5'h1: up_rdata <= up_scratch;
+          5'h2: up_rdata <= {30'h0,trigger_o};
+          5'h3: up_rdata <= {30'h0,io_selection};
+          5'h4: up_rdata <= {22'h0,up_config_trigger};
+          5'h5: up_rdata <= {16'h0,up_limit_a};
+          5'h6: up_rdata <= {30'h0,up_function_a};
+          5'h7: up_rdata <= up_hysteresis_a;
+          5'h8: up_rdata <= {28'h0,up_trigger_l_mix_a};
+          5'h9: up_rdata <= {16'h0,up_limit_b};
+          5'ha: up_rdata <= {30'h0,up_function_b};
+          5'hb: up_rdata <= up_hysteresis_b;
+          5'hc: up_rdata <= {28'h0,up_trigger_l_mix_b};
+          5'hd: up_rdata <= {29'h0,up_trigger_out_mix};
+          5'he: up_rdata <= up_delay_trigger;
+          default: up_rdata <= 0;
+        endcase
+      end else begin
+        up_rdata <= 32'd0;
+      end
+    end
+  end
+
+   up_xfer_cntrl #(.DATA_WIDTH(153)) i_xfer_cntrl (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_data_cntrl ({ up_config_trigger,    // 10
+                      up_limit_a,           // 16
+                      up_function_a,        // 2
+                      up_hysteresis_a,      // 32
+                      up_trigger_l_mix_a,   // 4
+                      up_limit_b,           // 16
+                      up_function_b,        // 2
+                      up_hysteresis_b,      // 32
+                      up_trigger_l_mix_b,   // 4
+                      up_trigger_out_mix,   // 3
+                      up_delay_trigger}), // 32
+
+    .up_xfer_done (),
+    .d_rst (1'b0),
+    .d_clk (clk),
+    .d_data_cntrl ({  config_trigger,     // 10
+                      limit_a,            // 16
+                      function_a,         // 2
+                      hysteresis_a,       // 32
+                      trigger_l_mix_a,    // 4
+                      limit_b,            // 16
+                      function_b,         // 2
+                      hysteresis_b,       // 32
+                      trigger_l_mix_b,    // 4
+                      trigger_out_mix,    // 3
+                      delay_trigger})); // 32
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+

From 4a7232cbcb48b46b6f3b488d85f715d19f906d80 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:21:39 +0200
Subject: [PATCH 879/972] axi_adc_decimate: Initial commit

---
 library/axi_adc_decimate/Makefile             |  53 ++
 library/axi_adc_decimate/axi_adc_decimate.v   | 272 ++++++++
 .../axi_adc_decimate_constr.xdc               |   8 +
 .../axi_adc_decimate/axi_adc_decimate_ip.tcl  |  25 +
 .../axi_adc_decimate/axi_adc_decimate_reg.v   | 137 ++++
 library/axi_adc_decimate/cic_decim.v          | 610 ++++++++++++++++++
 library/axi_adc_decimate/fir_decim.v          | 331 ++++++++++
 7 files changed, 1436 insertions(+)
 create mode 100644 library/axi_adc_decimate/Makefile
 create mode 100644 library/axi_adc_decimate/axi_adc_decimate.v
 create mode 100644 library/axi_adc_decimate/axi_adc_decimate_constr.xdc
 create mode 100644 library/axi_adc_decimate/axi_adc_decimate_ip.tcl
 create mode 100644 library/axi_adc_decimate/axi_adc_decimate_reg.v
 create mode 100644 library/axi_adc_decimate/cic_decim.v
 create mode 100644 library/axi_adc_decimate/fir_decim.v

diff --git a/library/axi_adc_decimate/Makefile b/library/axi_adc_decimate/Makefile
new file mode 100644
index 000000000..19396d233
--- /dev/null
+++ b/library/axi_adc_decimate/Makefile
@@ -0,0 +1,53 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += axi_adc_decimate.v
+M_DEPS += axi_adc_decimate_constr.xdc
+M_DEPS += axi_adc_decimate_ip.tcl
+M_DEPS += axi_adc_decimate_reg.v
+M_DEPS += cic_decim.v
+M_DEPS += fir_decim.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_adc_decimate.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_adc_decimate.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_adc_decimate_ip.tcl  >> axi_adc_decimate_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/axi_adc_decimate/axi_adc_decimate.v b/library/axi_adc_decimate/axi_adc_decimate.v
new file mode 100644
index 000000000..66cb7c25d
--- /dev/null
+++ b/library/axi_adc_decimate/axi_adc_decimate.v
@@ -0,0 +1,272 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_adc_decimate(
+
+  input                 adc_clk,
+
+  input       [15:0]    adc_data_a,
+  input       [15:0]    adc_data_b,
+  input                 adc_valid_a,
+  input                 adc_valid_b,
+
+  output reg  [15:0]    adc_dec_data_a,
+  output reg  [15:0]    adc_dec_data_b,
+  output reg            adc_dec_valid_a,
+  output reg            adc_dec_valid_b,
+
+  // axi interface
+
+  input                 s_axi_aclk,
+  input                 s_axi_aresetn,
+  input                 s_axi_awvalid,
+  input       [31:0]    s_axi_awaddr,
+  input       [ 2:0]    s_axi_awprot,
+  output                s_axi_awready,
+  input                 s_axi_wvalid,
+  input       [31:0]    s_axi_wdata,
+  input       [ 3:0]    s_axi_wstrb,
+  output                s_axi_wready,
+  output                s_axi_bvalid,
+  output      [ 1:0]    s_axi_bresp,
+  input                 s_axi_bready,
+  input                 s_axi_arvalid,
+  input       [31:0]    s_axi_araddr,
+  input       [ 2:0]    s_axi_arprot,
+  output                s_axi_arready,
+  output                s_axi_rvalid,
+  output      [31:0]    s_axi_rdata,
+  output      [ 1:0]    s_axi_rresp,
+  input                 s_axi_rready);
+
+  // internal signals
+
+  wire              up_clk;
+  wire              up_rstn;
+  wire    [13:0]    up_waddr;
+  wire    [31:0]    up_wdata;
+  wire              up_wack;
+  wire              up_wreq;
+  wire              up_rack;
+  wire    [31:0]    up_rdata;
+  wire              up_rreq;
+  wire    [13:0]    up_raddr;
+
+  wire    [31:0]    decimation_ratio;
+  wire    [31:0]    filter_mask;
+
+  wire    [105:0]   adc_cic_data_a;
+  wire              adc_cic_valid_a;
+  wire    [105:0]   adc_cic_data_b;
+  wire              adc_cic_valid_b;
+
+  wire    [25:0]    adc_fir_data_a;
+  wire              adc_fir_valid_a;
+  wire    [25:0]    adc_fir_data_b;
+  wire              adc_fir_valid_b;
+
+  reg               adc_dec_valid_a_filter;
+  reg               adc_dec_valid_b_filter;
+
+  reg     [31:0]    decimation_counter;
+  reg     [15:0]    decim_rate_cic;
+
+  // signal name changes
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+
+  cic_decim cic_decimation_a (
+    .clk(adc_clk),
+    .clk_enable(adc_valid_a),
+    .reset(adc_rst),
+    .filter_in(adc_data_a[11:0]),
+    .rate(decim_rate_cic),
+    .load_rate(1'b0),
+    .filter_out(adc_cic_data_a),
+    .ce_out(adc_cic_valid_a));
+
+  cic_decim cic_decimation_b (
+    .clk(adc_clk),
+    .clk_enable(adc_valid_b),
+    .reset(adc_rst),
+    .filter_in(adc_data_b[11:0]),
+    .rate(decim_rate_cic),
+    .load_rate(1'b0),
+    .filter_out(adc_cic_data_b),
+    .ce_out(adc_cic_valid_b));
+
+  fir_decim fir_decimation_a (
+    .clk(adc_clk),
+    .clk_enable(adc_cic_valid_a),
+    .reset(adc_rst),
+    .filter_in(adc_cic_data_a[11:0]),
+    .filter_out(adc_fir_data_a),
+    .ce_out(adc_fir_valid_a));
+
+  fir_decim fir_decimation_b (
+    .clk(adc_clk),
+    .clk_enable(adc_cic_valid_b),
+    .reset(adc_rst),
+    .filter_in(adc_cic_data_b[11:0]),
+    .filter_out(adc_fir_data_b),
+    .ce_out(adc_fir_valid_b));
+
+  always @(*) begin
+    case (filter_mask)
+      16'h1: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
+      16'h2: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
+      16'h3: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
+      16'h6: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
+      16'h7: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
+      default: adc_dec_data_a = adc_data_a;
+    endcase
+
+    case (filter_mask)
+      16'h1: adc_dec_valid_a_filter = adc_fir_valid_a;
+      16'h2: adc_dec_valid_a_filter = adc_fir_valid_a;
+      16'h3: adc_dec_valid_a_filter = adc_fir_valid_a;
+      16'h6: adc_dec_valid_a_filter = adc_fir_valid_a;
+      16'h7: adc_dec_valid_a_filter = adc_fir_valid_a;
+      default: adc_dec_valid_a_filter = adc_valid_a;
+    endcase
+
+     case (filter_mask)
+      16'h1: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
+      16'h2: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
+      16'h3: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
+      16'h6: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
+      16'h7: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
+      default: adc_dec_data_b = adc_data_b;
+    endcase
+
+    case (filter_mask)
+      16'h1: adc_dec_valid_b_filter = adc_fir_valid_b;
+      16'h2: adc_dec_valid_b_filter = adc_fir_valid_b;
+      16'h3: adc_dec_valid_b_filter = adc_fir_valid_b;
+      16'h6: adc_dec_valid_b_filter = adc_fir_valid_b;
+      16'h7: adc_dec_valid_b_filter = adc_fir_valid_b;
+      default: adc_dec_valid_b_filter = adc_valid_b;
+    endcase
+
+    case (filter_mask)
+      16'h1: decim_rate_cic = 16'd5;
+      16'h2: decim_rate_cic = 16'd50;
+      16'h3: decim_rate_cic = 16'd500;
+      16'h6: decim_rate_cic = 16'd5000;
+      16'h7: decim_rate_cic = 16'd50000;
+      default: decim_rate_cic = 9'd1;
+    endcase
+  end
+
+  always @(posedge adc_clk) begin
+    if (adc_rst == 1'b1) begin
+      decimation_counter <= 32'b0;
+      adc_dec_valid_a <= 1'b0;
+      adc_dec_valid_b <= 1'b0;
+    end else begin
+      if (adc_dec_valid_a_filter == 1'b1) begin
+        if (decimation_counter < decimation_ratio) begin
+          decimation_counter <= decimation_counter + 1;
+          adc_dec_valid_a <= 1'b0;
+          adc_dec_valid_b <= 1'b0;
+        end else begin
+          decimation_counter <= 0;
+          adc_dec_valid_a <= 1'b1;
+          adc_dec_valid_b <= 1'b1;
+        end
+      end else begin
+          adc_dec_valid_a <= 1'b0;
+          adc_dec_valid_b <= 1'b0;
+      end
+    end
+  end
+
+  axi_adc_decimate_reg axi_adc_decimate_reg (
+
+    .clk (adc_clk),
+    .adc_rst (adc_rst),
+
+    .adc_decimation_ratio (decimation_ratio),
+    .adc_filter_mask (filter_mask),
+
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+ up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_adc_decimate/axi_adc_decimate_constr.xdc b/library/axi_adc_decimate/axi_adc_decimate_constr.xdc
new file mode 100644
index 000000000..3f786eb5d
--- /dev/null
+++ b/library/axi_adc_decimate/axi_adc_decimate_constr.xdc
@@ -0,0 +1,8 @@
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
+
+set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg   && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg   && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data*       && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl*          && IS_SEQUENTIAL}]
diff --git a/library/axi_adc_decimate/axi_adc_decimate_ip.tcl b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl
new file mode 100644
index 000000000..42173905f
--- /dev/null
+++ b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl
@@ -0,0 +1,25 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_adc_decimate
+adi_ip_files axi_adc_decimate [list \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "axi_adc_decimate_constr.xdc" \
+  "fir_decim.v" \
+  "cic_decim.v" \
+  "axi_adc_decimate_reg.v" \
+  "axi_adc_decimate.v" ]
+
+adi_ip_properties axi_adc_decimate
+adi_ip_constraints axi_adc_decimate [list \
+  "axi_adc_decimate_constr.xdc" ]
+
+ipx::remove_bus_interface {clk} [ipx::current_core]
+ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+
diff --git a/library/axi_adc_decimate/axi_adc_decimate_reg.v b/library/axi_adc_decimate/axi_adc_decimate_reg.v
new file mode 100644
index 000000000..47b4b6ab1
--- /dev/null
+++ b/library/axi_adc_decimate/axi_adc_decimate_reg.v
@@ -0,0 +1,137 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_adc_decimate_reg(
+
+  input               clk,
+  output              adc_rst,
+
+  output      [31:0]  adc_decimation_ratio,
+  output      [31:0]  adc_filter_mask,
+
+ // bus interface
+
+  input               up_rstn,
+  input               up_clk,
+  input               up_wreq,
+  input       [13:0]  up_waddr,
+  input       [31:0]  up_wdata,
+  output  reg         up_wack,
+  input               up_rreq,
+  input       [13:0]  up_raddr,
+  output  reg [31:0]  up_rdata,
+  output  reg         up_rack);
+
+  // internal signals
+
+  wire            up_wreq_s;
+  wire            up_rreq_s;
+
+  // internal registers
+
+  reg     [31:0]  up_version = 32'h00010000;
+  reg     [31:0]  up_scratch = 32'h0;
+
+  reg     [31:0]  up_decimation_ratio = 32'h0;
+  reg     [31:0]  up_filter_mask  = 32'h0;
+
+  assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
+  assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
+
+  ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(clk), .rst(adc_rst));
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_scratch <= 'd0;
+      up_decimation_ratio <= 'd0;
+      up_filter_mask <= 'd0;
+    end else begin
+      up_wack <= up_wreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
+        up_scratch <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
+        up_decimation_ratio <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
+        up_filter_mask <= up_wdata;
+      end
+    end
+  end
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_rack <= up_rreq_s;
+      if (up_rreq_s == 1'b1) begin
+        case (up_raddr[4:0])
+          5'h0: up_rdata  <= up_version;
+          5'h1: up_rdata  <= up_scratch;
+          5'h10: up_rdata <= up_decimation_ratio;
+          5'h11: up_rdata <= up_filter_mask;
+          default: up_rdata <= 0;
+        endcase
+      end else begin
+        up_rdata <= 32'd0;
+      end
+    end
+  end
+
+   up_xfer_cntrl #(.DATA_WIDTH(64)) i_xfer_cntrl (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_data_cntrl ({ up_decimation_ratio,  // 32
+                      up_filter_mask}),     // 32
+
+    .up_xfer_done (),
+    .d_rst (1'b0),
+    .d_clk (clk),
+    .d_data_cntrl ({  adc_decimation_ratio, // 32
+                      adc_filter_mask}));   // 32
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_adc_decimate/cic_decim.v b/library/axi_adc_decimate/cic_decim.v
new file mode 100644
index 000000000..bbe15e9b6
--- /dev/null
+++ b/library/axi_adc_decimate/cic_decim.v
@@ -0,0 +1,610 @@
+// -------------------------------------------------------------
+//
+// Module: cic_decim
+// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
+// Generated on: 2016-07-05 15:46:18
+// -------------------------------------------------------------
+
+// -------------------------------------------------------------
+// HDL Code Generation Options:
+//
+// OptimizeForHDL: on
+// EDAScriptGeneration: off
+// AddPipelineRegisters: on
+// Name: cic_decim
+// AddRatePort: on
+// InputDataType: numerictype(1,12,11)
+// TargetLanguage: Verilog
+// TestBenchName: cicdecimfilt_copy_tb
+// TestBenchStimulus: step ramp chirp noise 
+// GenerateHDLTestBench: off
+
+// -------------------------------------------------------------
+// HDL Implementation    : Fully parallel
+// -------------------------------------------------------------
+// Filter Settings:
+//
+// Discrete-Time FIR Multirate Filter (real)
+// -----------------------------------------
+// Filter Structure    : Cascaded Integrator-Comb Decimator
+// Decimation Factor   : 50000
+// Differential Delay  : 1
+// Number of Sections  : 6
+// Stable              : Yes
+// Linear Phase        : No
+//
+// -------------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module cic_decim
+               (
+                clk,
+                clk_enable,
+                reset,
+                filter_in,
+                rate,
+                load_rate,
+                filter_out,
+                ce_out
+                );
+
+  input   clk; 
+  input   clk_enable; 
+  input   reset; 
+  input   signed [11:0] filter_in; //sfix12_En11
+  input   [15:0] rate; //ufix16
+  input   load_rate; 
+  output  signed [105:0] filter_out; //sfix106_En11
+  output  ce_out; 
+
+////////////////////////////////////////////////////////////////
+//Module Architecture: cic_decim
+////////////////////////////////////////////////////////////////
+  // Local Functions
+  // Type Definitions
+  // Constants
+  // Signals
+  reg  [15:0] rate_register; // ufix16
+  reg  [15:0] cur_count; // ufix16
+  wire phase_1; // boolean
+  wire ce_delayline; // boolean
+  reg  int_delay_pipe [0:4] ; // boolean
+  wire ce_gated; // boolean
+  reg  ce_out_reg; // boolean
+  //   
+  reg  signed [11:0] input_register; // sfix12_En11
+  //   -- Section 1 Signals 
+  wire signed [11:0] section_in1; // sfix12_En11
+  wire signed [105:0] section_cast1; // sfix106_En11
+  wire signed [105:0] sum1; // sfix106_En11
+  reg  signed [105:0] section_out1; // sfix106_En11
+  wire signed [105:0] add_cast; // sfix106_En11
+  wire signed [105:0] add_cast_1; // sfix106_En11
+  wire signed [106:0] add_temp; // sfix107_En11
+  //   -- Section 2 Signals 
+  wire signed [105:0] section_in2; // sfix106_En11
+  wire signed [105:0] sum2; // sfix106_En11
+  reg  signed [105:0] section_out2; // sfix106_En11
+  wire signed [105:0] add_cast_2; // sfix106_En11
+  wire signed [105:0] add_cast_3; // sfix106_En11
+  wire signed [106:0] add_temp_1; // sfix107_En11
+  //   -- Section 3 Signals 
+  wire signed [105:0] section_in3; // sfix106_En11
+  wire signed [105:0] sum3; // sfix106_En11
+  reg  signed [105:0] section_out3; // sfix106_En11
+  wire signed [105:0] add_cast_4; // sfix106_En11
+  wire signed [105:0] add_cast_5; // sfix106_En11
+  wire signed [106:0] add_temp_2; // sfix107_En11
+  //   -- Section 4 Signals 
+  wire signed [105:0] section_in4; // sfix106_En11
+  wire signed [105:0] sum4; // sfix106_En11
+  reg  signed [105:0] section_out4; // sfix106_En11
+  wire signed [105:0] add_cast_6; // sfix106_En11
+  wire signed [105:0] add_cast_7; // sfix106_En11
+  wire signed [106:0] add_temp_3; // sfix107_En11
+  //   -- Section 5 Signals 
+  wire signed [105:0] section_in5; // sfix106_En11
+  wire signed [105:0] sum5; // sfix106_En11
+  reg  signed [105:0] section_out5; // sfix106_En11
+  wire signed [105:0] add_cast_8; // sfix106_En11
+  wire signed [105:0] add_cast_9; // sfix106_En11
+  wire signed [106:0] add_temp_4; // sfix107_En11
+  //   -- Section 6 Signals 
+  wire signed [105:0] section_in6; // sfix106_En11
+  wire signed [105:0] sum6; // sfix106_En11
+  reg  signed [105:0] section_out6; // sfix106_En11
+  wire signed [105:0] add_cast_10; // sfix106_En11
+  wire signed [105:0] add_cast_11; // sfix106_En11
+  wire signed [106:0] add_temp_5; // sfix107_En11
+  //   -- Section 7 Signals 
+  wire signed [105:0] section_in7; // sfix106_En11
+  reg  signed [105:0] diff1; // sfix106_En11
+  wire signed [105:0] section_out7; // sfix106_En11
+  wire signed [105:0] sub_cast; // sfix106_En11
+  wire signed [105:0] sub_cast_1; // sfix106_En11
+  wire signed [106:0] sub_temp; // sfix107_En11
+  reg  signed [105:0] cic_pipeline7; // sfix106_En11
+  //   -- Section 8 Signals 
+  wire signed [105:0] section_in8; // sfix106_En11
+  reg  signed [105:0] diff2; // sfix106_En11
+  wire signed [105:0] section_out8; // sfix106_En11
+  wire signed [105:0] sub_cast_2; // sfix106_En11
+  wire signed [105:0] sub_cast_3; // sfix106_En11
+  wire signed [106:0] sub_temp_1; // sfix107_En11
+  reg  signed [105:0] cic_pipeline8; // sfix106_En11
+  //   -- Section 9 Signals 
+  wire signed [105:0] section_in9; // sfix106_En11
+  reg  signed [105:0] diff3; // sfix106_En11
+  wire signed [105:0] section_out9; // sfix106_En11
+  wire signed [105:0] sub_cast_4; // sfix106_En11
+  wire signed [105:0] sub_cast_5; // sfix106_En11
+  wire signed [106:0] sub_temp_2; // sfix107_En11
+  reg  signed [105:0] cic_pipeline9; // sfix106_En11
+  //   -- Section 10 Signals 
+  wire signed [105:0] section_in10; // sfix106_En11
+  reg  signed [105:0] diff4; // sfix106_En11
+  wire signed [105:0] section_out10; // sfix106_En11
+  wire signed [105:0] sub_cast_6; // sfix106_En11
+  wire signed [105:0] sub_cast_7; // sfix106_En11
+  wire signed [106:0] sub_temp_3; // sfix107_En11
+  reg  signed [105:0] cic_pipeline10; // sfix106_En11
+  //   -- Section 11 Signals 
+  wire signed [105:0] section_in11; // sfix106_En11
+  reg  signed [105:0] diff5; // sfix106_En11
+  wire signed [105:0] section_out11; // sfix106_En11
+  wire signed [105:0] sub_cast_8; // sfix106_En11
+  wire signed [105:0] sub_cast_9; // sfix106_En11
+  wire signed [106:0] sub_temp_4; // sfix107_En11
+  reg  signed [105:0] cic_pipeline11; // sfix106_En11
+  //   -- Section 12 Signals 
+  wire signed [105:0] section_in12; // sfix106_En11
+  reg  signed [105:0] diff6; // sfix106_En11
+  wire signed [105:0] section_out12; // sfix106_En11
+  wire signed [105:0] sub_cast_10; // sfix106_En11
+  wire signed [105:0] sub_cast_11; // sfix106_En11
+  wire signed [106:0] sub_temp_5; // sfix107_En11
+  reg  [6:0] bitgain; // ufix7
+  wire signed [105:0] output_typeconvert; // sfix106_En11
+  wire signed [105:0] muxinput_14; // sfix106_E3
+  wire signed [105:0] muxinput_34; // sfix106_E23
+  wire signed [105:0] muxinput_54; // sfix106_E43
+  wire signed [105:0] muxinput_74; // sfix106_E63
+  wire signed [105:0] muxinput_94; // sfix106_E83
+  //   
+  reg  signed [105:0] output_register; // sfix106_En11
+
+  // Block Statements
+  //   ------------------ CE Output Generation ------------------
+
+  always @ (posedge clk or posedge reset)
+    begin: ce_output
+      if (reset == 1'b1) begin
+        cur_count <= 16'b0000000000000000;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          if (load_rate ==  1'b1) begin
+            cur_count <= 16'b0000000000000001;
+          end
+          else if (cur_count == rate_register - 1) begin
+            cur_count <= 16'b0000000000000000;
+          end
+          else begin
+            cur_count <= cur_count + 1;
+          end
+        end
+      end
+    end // ce_output
+
+  assign  phase_1 = (cur_count == 16'b0000000000000001 && clk_enable == 1'b1)? 1 : 0;
+
+  always @ (posedge clk or posedge reset)
+    begin: ce_delay
+      if (reset == 1'b1) begin
+        int_delay_pipe[0] <= 1'b0;
+        int_delay_pipe[1] <= 1'b0;
+        int_delay_pipe[2] <= 1'b0;
+        int_delay_pipe[3] <= 1'b0;
+        int_delay_pipe[4] <= 1'b0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          int_delay_pipe[1] <= int_delay_pipe[0];
+          int_delay_pipe[2] <= int_delay_pipe[1];
+          int_delay_pipe[3] <= int_delay_pipe[2];
+          int_delay_pipe[4] <= int_delay_pipe[3];
+          int_delay_pipe[0] <= clk_enable;
+        end
+      end
+    end // ce_delay
+  assign ce_delayline = int_delay_pipe[4];
+
+  assign ce_gated =  ce_delayline & phase_1;
+
+  //   ------------------ CE Output Register ------------------
+
+  always @ (posedge clk or posedge reset)
+    begin: ce_output_register
+      if (reset == 1'b1) begin
+        ce_out_reg <= 1'b0;
+      end
+      else begin
+          ce_out_reg <= ce_gated;
+      end
+    end // ce_output_register
+
+  //   ------------------ Input Register ------------------
+
+  always @ (posedge clk or posedge reset)
+    begin: input_reg_process
+      if (reset == 1'b1) begin
+        input_register <= 0;
+        rate_register <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          input_register <= filter_in;
+          rate_register <= rate;
+        end
+      end
+    end // input_reg_process
+
+  //   ------------------ Section # 1 : Integrator ------------------
+
+  assign section_in1 = input_register;
+
+  assign section_cast1 = $signed({{94{section_in1[11]}}, section_in1});
+
+  assign add_cast = section_cast1;
+  assign add_cast_1 = section_out1;
+  assign add_temp = add_cast + add_cast_1;
+  assign sum1 = add_temp[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section1
+      if (reset == 1'b1) begin
+        section_out1 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out1 <= sum1;
+        end
+      end
+    end // integrator_delay_section1
+
+  //   ------------------ Section # 2 : Integrator ------------------
+
+  assign section_in2 = section_out1;
+
+  assign add_cast_2 = section_in2;
+  assign add_cast_3 = section_out2;
+  assign add_temp_1 = add_cast_2 + add_cast_3;
+  assign sum2 = add_temp_1[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section2
+      if (reset == 1'b1) begin
+        section_out2 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out2 <= sum2;
+        end
+      end
+    end // integrator_delay_section2
+
+  //   ------------------ Section # 3 : Integrator ------------------
+
+  assign section_in3 = section_out2;
+
+  assign add_cast_4 = section_in3;
+  assign add_cast_5 = section_out3;
+  assign add_temp_2 = add_cast_4 + add_cast_5;
+  assign sum3 = add_temp_2[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section3
+      if (reset == 1'b1) begin
+        section_out3 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out3 <= sum3;
+        end
+      end
+    end // integrator_delay_section3
+
+  //   ------------------ Section # 4 : Integrator ------------------
+
+  assign section_in4 = section_out3;
+
+  assign add_cast_6 = section_in4;
+  assign add_cast_7 = section_out4;
+  assign add_temp_3 = add_cast_6 + add_cast_7;
+  assign sum4 = add_temp_3[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section4
+      if (reset == 1'b1) begin
+        section_out4 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out4 <= sum4;
+        end
+      end
+    end // integrator_delay_section4
+
+  //   ------------------ Section # 5 : Integrator ------------------
+
+  assign section_in5 = section_out4;
+
+  assign add_cast_8 = section_in5;
+  assign add_cast_9 = section_out5;
+  assign add_temp_4 = add_cast_8 + add_cast_9;
+  assign sum5 = add_temp_4[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section5
+      if (reset == 1'b1) begin
+        section_out5 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out5 <= sum5;
+        end
+      end
+    end // integrator_delay_section5
+
+  //   ------------------ Section # 6 : Integrator ------------------
+
+  assign section_in6 = section_out5;
+
+  assign add_cast_10 = section_in6;
+  assign add_cast_11 = section_out6;
+  assign add_temp_5 = add_cast_10 + add_cast_11;
+  assign sum6 = add_temp_5[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section6
+      if (reset == 1'b1) begin
+        section_out6 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out6 <= sum6;
+        end
+      end
+    end // integrator_delay_section6
+
+  //   ------------------ Section # 7 : Comb ------------------
+
+  assign section_in7 = section_out6;
+
+  assign sub_cast = section_in7;
+  assign sub_cast_1 = diff1;
+  assign sub_temp = sub_cast - sub_cast_1;
+  assign section_out7 = sub_temp[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section7
+      if (reset == 1'b1) begin
+        diff1 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          diff1 <= section_in7;
+        end
+      end
+    end // comb_delay_section7
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section7
+      if (reset == 1'b1) begin
+        cic_pipeline7 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          cic_pipeline7 <= section_out7;
+        end
+      end
+    end // cic_pipeline_process_section7
+
+  //   ------------------ Section # 8 : Comb ------------------
+
+  assign section_in8 = cic_pipeline7;
+
+  assign sub_cast_2 = section_in8;
+  assign sub_cast_3 = diff2;
+  assign sub_temp_1 = sub_cast_2 - sub_cast_3;
+  assign section_out8 = sub_temp_1[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section8
+      if (reset == 1'b1) begin
+        diff2 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          diff2 <= section_in8;
+        end
+      end
+    end // comb_delay_section8
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section8
+      if (reset == 1'b1) begin
+        cic_pipeline8 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          cic_pipeline8 <= section_out8;
+        end
+      end
+    end // cic_pipeline_process_section8
+
+  //   ------------------ Section # 9 : Comb ------------------
+
+  assign section_in9 = cic_pipeline8;
+
+  assign sub_cast_4 = section_in9;
+  assign sub_cast_5 = diff3;
+  assign sub_temp_2 = sub_cast_4 - sub_cast_5;
+  assign section_out9 = sub_temp_2[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section9
+      if (reset == 1'b1) begin
+        diff3 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          diff3 <= section_in9;
+        end
+      end
+    end // comb_delay_section9
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section9
+      if (reset == 1'b1) begin
+        cic_pipeline9 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          cic_pipeline9 <= section_out9;
+        end
+      end
+    end // cic_pipeline_process_section9
+
+  //   ------------------ Section # 10 : Comb ------------------
+
+  assign section_in10 = cic_pipeline9;
+
+  assign sub_cast_6 = section_in10;
+  assign sub_cast_7 = diff4;
+  assign sub_temp_3 = sub_cast_6 - sub_cast_7;
+  assign section_out10 = sub_temp_3[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section10
+      if (reset == 1'b1) begin
+        diff4 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          diff4 <= section_in10;
+        end
+      end
+    end // comb_delay_section10
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section10
+      if (reset == 1'b1) begin
+        cic_pipeline10 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          cic_pipeline10 <= section_out10;
+        end
+      end
+    end // cic_pipeline_process_section10
+
+  //   ------------------ Section # 11 : Comb ------------------
+
+  assign section_in11 = cic_pipeline10;
+
+  assign sub_cast_8 = section_in11;
+  assign sub_cast_9 = diff5;
+  assign sub_temp_4 = sub_cast_8 - sub_cast_9;
+  assign section_out11 = sub_temp_4[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section11
+      if (reset == 1'b1) begin
+        diff5 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          diff5 <= section_in11;
+        end
+      end
+    end // comb_delay_section11
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section11
+      if (reset == 1'b1) begin
+        cic_pipeline11 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          cic_pipeline11 <= section_out11;
+        end
+      end
+    end // cic_pipeline_process_section11
+
+  //   ------------------ Section # 12 : Comb ------------------
+
+  assign section_in12 = cic_pipeline11;
+
+  assign sub_cast_10 = section_in12;
+  assign sub_cast_11 = diff6;
+  assign sub_temp_5 = sub_cast_10 - sub_cast_11;
+  assign section_out12 = sub_temp_5[105:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section12
+      if (reset == 1'b1) begin
+        diff6 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          diff6 <= section_in12;
+        end
+      end
+    end // comb_delay_section12
+
+  always @(rate_register)
+  begin
+    case(rate_register)
+      16'b0000000000000101 : bitgain = 7'b0001110;
+      16'b0000000000110010 : bitgain = 7'b0100010;
+      16'b0000000111110100 : bitgain = 7'b0110110;
+      16'b0001001110001000 : bitgain = 7'b1001010;
+      default : bitgain = 7'b1011110;
+    endcase
+  end
+
+  assign muxinput_14 = $signed({{14{section_out12[105]}}, section_out12[105:14]});
+
+  assign muxinput_34 = $signed({{34{section_out12[105]}}, section_out12[105:34]});
+
+  assign muxinput_54 = $signed({{54{section_out12[105]}}, section_out12[105:54]});
+
+  assign muxinput_74 = $signed({{74{section_out12[105]}}, section_out12[105:74]});
+
+  assign muxinput_94 = $signed({{94{section_out12[105]}}, section_out12[105:94]});
+
+  assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 :
+                             (bitgain == 7'b0100010) ? muxinput_34 :
+                             (bitgain == 7'b0110110) ? muxinput_54 :
+                             (bitgain == 7'b1001010) ? muxinput_74 :
+                             muxinput_94;
+  //   ------------------ Output Register ------------------
+
+  always @ (posedge clk or posedge reset)
+    begin: output_reg_process
+      if (reset == 1'b1) begin
+        output_register <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          output_register <= output_typeconvert;
+        end
+      end
+    end // output_reg_process
+
+  // Assignment Statements
+  assign ce_out = ce_out_reg;
+  assign filter_out = output_register;
+endmodule  // cic_decim
diff --git a/library/axi_adc_decimate/fir_decim.v b/library/axi_adc_decimate/fir_decim.v
new file mode 100644
index 000000000..ef23f6924
--- /dev/null
+++ b/library/axi_adc_decimate/fir_decim.v
@@ -0,0 +1,331 @@
+// -------------------------------------------------------------
+//
+// Module: fir_decim
+// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
+// Generated on: 2016-07-05 15:45:22
+// -------------------------------------------------------------
+
+// -------------------------------------------------------------
+// HDL Code Generation Options:
+//
+// FIRAdderStyle: tree
+// OptimizeForHDL: on
+// EDAScriptGeneration: off
+// AddPipelineRegisters: on
+// Name: fir_decim
+// TargetLanguage: Verilog
+// TestBenchName: fo_copy_tb
+// TestBenchStimulus: step ramp chirp noise 
+// GenerateHDLTestBench: off
+
+// -------------------------------------------------------------
+// HDL Implementation    : Fully parallel
+// Multipliers           : 6
+// Folding Factor        : 1
+// -------------------------------------------------------------
+// Filter Settings:
+//
+// Discrete-Time FIR Multirate Filter (real)
+// -----------------------------------------
+// Filter Structure   : Direct-Form FIR Polyphase Decimator
+// Decimation Factor  : 2
+// Polyphase Length   : 3
+// Filter Length      : 6
+// Stable             : Yes
+// Linear Phase       : Yes (Type 2)
+//
+// Arithmetic         : fixed
+// Numerator          : s12,11 -> [-1 1)
+// -------------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module fir_decim
+               (
+                clk,
+                clk_enable,
+                reset,
+                filter_in,
+                filter_out,
+                ce_out
+                );
+
+  input   clk; 
+  input   clk_enable; 
+  input   reset; 
+  input   signed [11:0] filter_in; //sfix12_En11
+  output  signed [25:0] filter_out; //sfix26_En22
+  output  ce_out; 
+
+////////////////////////////////////////////////////////////////
+//Module Architecture: fir_decim
+////////////////////////////////////////////////////////////////
+  // Local Functions
+  // Type Definitions
+  // Constants
+  parameter signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11
+  parameter signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11
+  parameter signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11
+  parameter signed [11:0] coeffphase2_1 = 12'b110000111110; //sfix12_En11
+  parameter signed [11:0] coeffphase2_2 = 12'b011011110010; //sfix12_En11
+  parameter signed [11:0] coeffphase2_3 = 12'b000011010101; //sfix12_En11
+
+  // Signals
+  reg  [1:0] ring_count; // ufix2
+  wire phase_0; // boolean
+  wire phase_1; // boolean
+  reg  ce_out_reg; // boolean
+  reg  signed [11:0] input_register; // sfix12_En11
+  reg  signed [11:0] input_pipeline_phase0 [0:1] ; // sfix12_En11
+  reg  signed [11:0] input_pipeline_phase1 [0:2] ; // sfix12_En11
+  wire signed [23:0] product_phase0_1; // sfix24_En22
+  wire signed [23:0] product_phase0_2; // sfix24_En22
+  wire signed [23:0] product_phase0_3; // sfix24_En22
+  wire signed [23:0] product_phase1_1; // sfix24_En22
+  wire signed [23:0] product_phase1_2; // sfix24_En22
+  wire signed [23:0] product_phase1_3; // sfix24_En22
+  reg  signed [23:0] product_pipeline_phase0_1; // sfix24_En22
+  reg  signed [23:0] product_pipeline_phase0_2; // sfix24_En22
+  reg  signed [23:0] product_pipeline_phase0_3; // sfix24_En22
+  reg  signed [23:0] product_pipeline_phase1_1; // sfix24_En22
+  reg  signed [23:0] product_pipeline_phase1_2; // sfix24_En22
+  reg  signed [23:0] product_pipeline_phase1_3; // sfix24_En22
+  wire signed [25:0] sumvector1 [0:2] ; // sfix26_En22
+  wire signed [23:0] add_signext; // sfix24_En22
+  wire signed [23:0] add_signext_1; // sfix24_En22
+  wire signed [24:0] add_temp; // sfix25_En22
+  wire signed [23:0] add_signext_2; // sfix24_En22
+  wire signed [23:0] add_signext_3; // sfix24_En22
+  wire signed [24:0] add_temp_1; // sfix25_En22
+  wire signed [23:0] add_signext_4; // sfix24_En22
+  wire signed [23:0] add_signext_5; // sfix24_En22
+  wire signed [24:0] add_temp_2; // sfix25_En22
+  reg  signed [25:0] sumdelay_pipeline1 [0:2] ; // sfix26_En22
+  wire signed [25:0] sumvector2 [0:1] ; // sfix26_En22
+  wire signed [25:0] add_signext_6; // sfix26_En22
+  wire signed [25:0] add_signext_7; // sfix26_En22
+  wire signed [26:0] add_temp_3; // sfix27_En22
+  reg  signed [25:0] sumdelay_pipeline2 [0:1] ; // sfix26_En22
+  wire signed [25:0] sum3; // sfix26_En22
+  wire signed [25:0] add_signext_8; // sfix26_En22
+  wire signed [25:0] add_signext_9; // sfix26_En22
+  wire signed [26:0] add_temp_4; // sfix27_En22
+  reg  ce_delayline1; // boolean
+  reg  ce_delayline2; // boolean
+  reg  ce_delayline3; // boolean
+  reg  ce_delayline4; // boolean
+  reg  ce_delayline5; // boolean
+  reg  ce_delayline6; // boolean
+  reg  ce_delayline7; // boolean
+  reg  ce_delayline8; // boolean
+  wire ce_gated; // boolean
+  reg  signed [25:0] output_register; // sfix26_En22
+
+  // Block Statements
+  always @ (posedge clk or posedge reset)
+    begin: ce_output
+      if (reset == 1'b1) begin
+        ring_count <= 1;
+      end
+      else begin
+                if (clk_enable == 1'b1) begin
+        ring_count <= {ring_count[0], ring_count[1]};
+              end
+            end
+    end // ce_output
+
+  assign  phase_0 = ring_count[0]  && clk_enable;
+
+  assign  phase_1 = ring_count[1]  && clk_enable;
+
+  //   ------------------ CE Output Register ------------------
+
+  always @ (posedge clk or posedge reset)
+    begin: ce_output_register
+      if (reset == 1'b1) begin
+        ce_out_reg <= 1'b0;
+      end
+      else begin
+          ce_out_reg <= phase_1;
+      end
+    end // ce_output_register
+
+  always @ (posedge clk or posedge reset)
+    begin: input_reg_process
+      if (reset == 1'b1) begin
+        input_register <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          input_register <= filter_in;
+        end
+      end
+    end // input_reg_process
+
+  always @( posedge clk or posedge reset)
+    begin: Delay_Pipeline_Phase0_process
+      if (reset == 1'b1) begin
+        input_pipeline_phase0[0] <= 0;
+        input_pipeline_phase0[1] <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          input_pipeline_phase0[0] <= input_register;
+          input_pipeline_phase0[1] <= input_pipeline_phase0[0];
+        end
+      end
+    end // Delay_Pipeline_Phase0_process
+
+
+  always @( posedge clk or posedge reset)
+    begin: Delay_Pipeline_Phase1_process
+      if (reset == 1'b1) begin
+        input_pipeline_phase1[0] <= 0;
+        input_pipeline_phase1[1] <= 0;
+        input_pipeline_phase1[2] <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          input_pipeline_phase1[0] <= input_register;
+          input_pipeline_phase1[1] <= input_pipeline_phase1[0];
+          input_pipeline_phase1[2] <= input_pipeline_phase1[1];
+        end
+      end
+    end // Delay_Pipeline_Phase1_process
+
+
+  assign product_phase0_1 = input_register * coeffphase1_1;
+
+  assign product_phase0_2 = input_pipeline_phase0[0] * coeffphase1_2;
+
+  assign product_phase0_3 = input_pipeline_phase0[1] * coeffphase1_3;
+
+  assign product_phase1_1 = input_pipeline_phase1[0] * coeffphase2_1;
+
+  assign product_phase1_2 = input_pipeline_phase1[1] * coeffphase2_2;
+
+  assign product_phase1_3 = input_pipeline_phase1[2] * coeffphase2_3;
+
+  always @ (posedge clk or posedge reset)
+    begin: product_pipeline_process1
+      if (reset == 1'b1) begin
+        product_pipeline_phase0_1 <= 0;
+        product_pipeline_phase1_1 <= 0;
+        product_pipeline_phase0_2 <= 0;
+        product_pipeline_phase1_2 <= 0;
+        product_pipeline_phase0_3 <= 0;
+        product_pipeline_phase1_3 <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          product_pipeline_phase0_1 <= product_phase0_1;
+          product_pipeline_phase1_1 <= product_phase1_1;
+          product_pipeline_phase0_2 <= product_phase0_2;
+          product_pipeline_phase1_2 <= product_phase1_2;
+          product_pipeline_phase0_3 <= product_phase0_3;
+          product_pipeline_phase1_3 <= product_phase1_3;
+        end
+      end
+    end // product_pipeline_process1
+
+  assign add_signext = product_pipeline_phase1_1;
+  assign add_signext_1 = product_pipeline_phase1_2;
+  assign add_temp = add_signext + add_signext_1;
+  assign sumvector1[0] = $signed({{1{add_temp[24]}}, add_temp});
+
+  assign add_signext_2 = product_pipeline_phase1_3;
+  assign add_signext_3 = product_pipeline_phase0_1;
+  assign add_temp_1 = add_signext_2 + add_signext_3;
+  assign sumvector1[1] = $signed({{1{add_temp_1[24]}}, add_temp_1});
+
+  assign add_signext_4 = product_pipeline_phase0_2;
+  assign add_signext_5 = product_pipeline_phase0_3;
+  assign add_temp_2 = add_signext_4 + add_signext_5;
+  assign sumvector1[2] = $signed({{1{add_temp_2[24]}}, add_temp_2});
+
+  always @ (posedge clk or posedge reset)
+    begin: sumdelay_pipeline_process1
+      if (reset == 1'b1) begin
+        sumdelay_pipeline1[0] <= 0;
+        sumdelay_pipeline1[1] <= 0;
+        sumdelay_pipeline1[2] <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          sumdelay_pipeline1[0] <= sumvector1[0];
+          sumdelay_pipeline1[1] <= sumvector1[1];
+          sumdelay_pipeline1[2] <= sumvector1[2];
+        end
+      end
+    end // sumdelay_pipeline_process1
+
+  assign add_signext_6 = sumdelay_pipeline1[0];
+  assign add_signext_7 = sumdelay_pipeline1[1];
+  assign add_temp_3 = add_signext_6 + add_signext_7;
+  assign sumvector2[0] = add_temp_3[25:0];
+
+  assign sumvector2[1] = sumdelay_pipeline1[2];
+
+  always @ (posedge clk or posedge reset)
+    begin: sumdelay_pipeline_process2
+      if (reset == 1'b1) begin
+        sumdelay_pipeline2[0] <= 0;
+        sumdelay_pipeline2[1] <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          sumdelay_pipeline2[0] <= sumvector2[0];
+          sumdelay_pipeline2[1] <= sumvector2[1];
+        end
+      end
+    end // sumdelay_pipeline_process2
+
+  assign add_signext_8 = sumdelay_pipeline2[0];
+  assign add_signext_9 = sumdelay_pipeline2[1];
+  assign add_temp_4 = add_signext_8 + add_signext_9;
+  assign sum3 = add_temp_4[25:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: ce_delay
+      if (reset == 1'b1) begin
+        ce_delayline1 <= 1'b0;
+        ce_delayline2 <= 1'b0;
+        ce_delayline3 <= 1'b0;
+        ce_delayline4 <= 1'b0;
+        ce_delayline5 <= 1'b0;
+        ce_delayline6 <= 1'b0;
+        ce_delayline7 <= 1'b0;
+        ce_delayline8 <= 1'b0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          ce_delayline1 <= clk_enable;
+          ce_delayline2 <= ce_delayline1;
+          ce_delayline3 <= ce_delayline2;
+          ce_delayline4 <= ce_delayline3;
+          ce_delayline5 <= ce_delayline4;
+          ce_delayline6 <= ce_delayline5;
+          ce_delayline7 <= ce_delayline6;
+          ce_delayline8 <= ce_delayline7;
+        end
+      end
+    end // ce_delay
+
+  assign ce_gated =  ce_delayline8 & ce_out_reg;
+
+  always @ (posedge clk or posedge reset)
+    begin: output_register_process
+      if (reset == 1'b1) begin
+        output_register <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          output_register <= sum3;
+        end
+      end
+    end // output_register_process
+
+  // Assignment Statements
+  assign ce_out = ce_gated;
+  assign filter_out = output_register;
+endmodule  // fir_decim

From 9c975211da7933aaf10f911de2b432c0dc6de507 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:22:49 +0200
Subject: [PATCH 880/972] axi_dac_interpolate: Initial commit

---
 library/axi_dac_interpolate/Makefile          |  53 ++
 .../axi_dac_interpolate/axi_dac_interpolate.v | 323 +++++++++
 .../axi_dac_interpolate_constr.xdc            |  11 +
 .../axi_dac_interpolate_ip.tcl                |  25 +
 .../axi_dac_interpolate_reg.v                 | 161 +++++
 library/axi_dac_interpolate/cic_interp.v      | 614 ++++++++++++++++++
 library/axi_dac_interpolate/fir_interp.v      | 390 +++++++++++
 7 files changed, 1577 insertions(+)
 create mode 100644 library/axi_dac_interpolate/Makefile
 create mode 100644 library/axi_dac_interpolate/axi_dac_interpolate.v
 create mode 100644 library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc
 create mode 100644 library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl
 create mode 100644 library/axi_dac_interpolate/axi_dac_interpolate_reg.v
 create mode 100644 library/axi_dac_interpolate/cic_interp.v
 create mode 100644 library/axi_dac_interpolate/fir_interp.v

diff --git a/library/axi_dac_interpolate/Makefile b/library/axi_dac_interpolate/Makefile
new file mode 100644
index 000000000..b080bf3f2
--- /dev/null
+++ b/library/axi_dac_interpolate/Makefile
@@ -0,0 +1,53 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += axi_dac_interpolate.v
+M_DEPS += axi_dac_interpolate_constr.xdc
+M_DEPS += axi_dac_interpolate_ip.tcl
+M_DEPS += axi_dac_interpolate_reg.v
+M_DEPS += cic_interp.v
+M_DEPS += fir_interp.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_dac_interpolate.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_dac_interpolate.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_dac_interpolate_ip.tcl  >> axi_dac_interpolate_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/axi_dac_interpolate/axi_dac_interpolate.v b/library/axi_dac_interpolate/axi_dac_interpolate.v
new file mode 100644
index 000000000..f6541ac4d
--- /dev/null
+++ b/library/axi_dac_interpolate/axi_dac_interpolate.v
@@ -0,0 +1,323 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dac_interpolate(
+
+  input                 dac_clk,
+
+  input       [15:0]    dac_data_a,
+  input       [15:0]    dac_data_b,
+  input                 dac_valid_a,
+  input                 dac_valid_b,
+
+  output  reg [15:0]    dac_int_data_a,
+  output  reg [15:0]    dac_int_data_b,
+  output  reg           dac_int_valid_a,
+  output  reg           dac_int_valid_b,
+
+  // axi interface
+
+  input                 s_axi_aclk,
+  input                 s_axi_aresetn,
+  input                 s_axi_awvalid,
+  input       [31:0]    s_axi_awaddr,
+  input       [ 2:0]    s_axi_awprot,
+  output                s_axi_awready,
+  input                 s_axi_wvalid,
+  input       [31:0]    s_axi_wdata,
+  input       [ 3:0]    s_axi_wstrb,
+  output                s_axi_wready,
+  output                s_axi_bvalid,
+  output      [ 1:0]    s_axi_bresp,
+  input                 s_axi_bready,
+  input                 s_axi_arvalid,
+  input       [31:0]    s_axi_araddr,
+  input       [ 2:0]    s_axi_arprot,
+  output                s_axi_arready,
+  output                s_axi_rvalid,
+  output      [31:0]    s_axi_rdata,
+  output      [ 1:0]    s_axi_rresp,
+  input                 s_axi_rready);
+
+  // internal signals
+
+  wire              up_clk;
+  wire              up_rstn;
+  wire    [13:0]    up_waddr;
+  wire    [31:0]    up_wdata;
+  wire              up_wack;
+  wire              up_wreq;
+  wire              up_rack;
+  wire    [31:0]    up_rdata;
+  wire              up_rreq;
+  wire    [13:0]    up_raddr;
+
+  wire    [31:0]    interpolation_ratio_a;
+  wire    [31:0]    interpolation_ratio_b;
+  wire    [31:0]    filter_mask_a;
+  wire    [31:0]    filter_mask_b;
+
+  wire              dac_fir_valid_a;
+  wire    [35:0]    dac_fir_data_a;
+  wire              dac_fir_valid_b;
+  wire    [35:0]    dac_fir_data_b;
+
+  wire              dac_cic_valid_a;
+  wire    [109:0]   dac_cic_data_a;
+  wire              dac_cic_valid_b;
+  wire    [109:0]   dac_cic_data_b;
+
+  wire              dma_transfer_suspend;
+
+  reg               dac_filt_int_valid_a;
+  reg               dac_filt_int_valid_b;
+  reg     [15:0]    interp_rate_cic_a;
+  reg     [15:0]    interp_rate_cic_b;
+  reg     [31:0]    filter_mask_a_d1;
+  reg     [31:0]    filter_mask_b_d1;
+  reg               cic_change_rate_a;
+  reg               cic_change_rate_b;
+  reg     [31:0]    interpolation_counter_a;
+  reg     [31:0]    interpolation_counter_b;
+
+  // signal name changes
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+
+  ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(dac_clk), .rst(dac_rst));
+
+  fir_interp fir_interpolation_a (
+    .clk (dac_clk),
+    .clk_enable (dac_cic_valid_a),
+    .reset (dac_rst | dma_transfer_suspend),
+    .filter_in (dac_data_a),
+    .filter_out (dac_fir_data_a),
+    .ce_out (dac_fir_valid_a));
+
+  fir_interp fir_interpolation_b (
+    .clk (dac_clk),
+    .clk_enable (dac_cic_valid_b),
+    .reset (dac_rst | dma_transfer_suspend),
+    .filter_in (dac_data_b),
+    .filter_out (dac_fir_data_b),
+    .ce_out (dac_fir_valid_b));
+
+  cic_interp cic_interpolation_a (
+    .clk (dac_clk),
+    .clk_enable (dac_valid_a),
+    .reset (dac_rst | cic_change_rate_a | dma_transfer_suspend),
+    .rate (interp_rate_cic_a),
+    .load_rate (1'b0),
+    .filter_in (dac_fir_data_a[30:0]),
+    .filter_out (dac_cic_data_a),
+    .ce_out (dac_cic_valid_a));
+
+  cic_interp cic_interpolation_b (
+    .clk (dac_clk),
+    .clk_enable (dac_valid_b),
+    .reset (dac_rst | cic_change_rate_b | dma_transfer_suspend),
+    .rate (interp_rate_cic_b),
+    .load_rate (1'b0),
+    .filter_in (dac_fir_data_b[30:0]),
+    .filter_out (dac_cic_data_b),
+    .ce_out (dac_cic_valid_b));
+
+  always @(posedge dac_clk) begin
+    filter_mask_a_d1 <= filter_mask_a;
+    filter_mask_b_d1 <= filter_mask_b;
+    if (filter_mask_a_d1 != filter_mask_a) begin
+      cic_change_rate_a <= 1'b1;
+    end else begin
+      cic_change_rate_a <= 1'b0;
+    end
+    if (filter_mask_b_d1 != filter_mask_b) begin
+      cic_change_rate_b <= 1'b1;
+    end else begin
+      cic_change_rate_b <= 1'b0;
+    end
+  end
+
+  always @(posedge dac_clk) begin
+    if (interpolation_ratio_a == 0 || interpolation_ratio_a == 1) begin
+      dac_int_valid_a <= dac_filt_int_valid_a;
+    end else begin
+      if (dac_filt_int_valid_a == 1'b1) begin
+        if (interpolation_counter_a  < interpolation_ratio_a) begin
+          interpolation_counter_a <= interpolation_counter_a + 1;
+          dac_int_valid_a <= 1'b0;
+        end else begin
+          interpolation_counter_a <= 0;
+          dac_int_valid_a <= 1'b1;
+        end
+      end else begin
+        dac_int_valid_a <= 1'b0;
+      end
+    end
+  end
+
+  always @(posedge dac_clk) begin
+    if (interpolation_ratio_b == 0 || interpolation_ratio_b == 1) begin
+      dac_int_valid_b <= dac_filt_int_valid_b;
+    end else begin
+      if (dac_filt_int_valid_b == 1'b1) begin
+        if (interpolation_counter_b  < interpolation_ratio_b) begin
+          interpolation_counter_b <= interpolation_counter_b + 1;
+          dac_int_valid_b <= 1'b0;
+        end else begin
+          interpolation_counter_b <= 0;
+          dac_int_valid_b <= 1'b1;
+        end
+      end else begin
+        dac_int_valid_b <= 1'b0;
+      end
+    end
+  end
+
+  always @(*) begin
+    case (filter_mask_a)
+      16'h1: dac_int_data_a = dac_cic_data_a[31:16];
+      16'h2: dac_int_data_a = dac_cic_data_a[31:16];
+      16'h3: dac_int_data_a = dac_cic_data_a[31:16];
+      16'h6: dac_int_data_a = dac_cic_data_a[31:16];
+      16'h7: dac_int_data_a = dac_cic_data_a[31:16];
+      default: dac_int_data_a = dac_data_a;
+    endcase
+
+    case (filter_mask_a)
+      16'h1: dac_filt_int_valid_a = dac_fir_valid_a;
+      16'h2: dac_filt_int_valid_a = dac_fir_valid_a;
+      16'h3: dac_filt_int_valid_a = dac_fir_valid_a;
+      16'h6: dac_filt_int_valid_a = dac_fir_valid_a;
+      16'h7: dac_filt_int_valid_a = dac_fir_valid_a;
+      default: dac_filt_int_valid_a = dac_valid_a & !dma_transfer_suspend;
+    endcase
+
+    case (filter_mask_b)
+      16'h1: dac_int_data_b = dac_cic_data_b[31:16];
+      16'h2: dac_int_data_b = dac_cic_data_b[31:16];
+      16'h3: dac_int_data_b = dac_cic_data_b[31:16];
+      16'h6: dac_int_data_b = dac_cic_data_b[31:16];
+      16'h7: dac_int_data_b = dac_cic_data_b[31:16];
+      default: dac_int_data_b = dac_data_b;
+    endcase
+
+    case (filter_mask_b)
+      16'h1: dac_filt_int_valid_b = dac_fir_valid_b;
+      16'h2: dac_filt_int_valid_b = dac_fir_valid_b;
+      16'h3: dac_filt_int_valid_b = dac_fir_valid_b;
+      16'h6: dac_filt_int_valid_b = dac_fir_valid_b;
+      16'h7: dac_filt_int_valid_b = dac_fir_valid_b;
+      default: dac_filt_int_valid_b = dac_valid_b & !dma_transfer_suspend;
+    endcase
+
+    case (filter_mask_a)
+      16'h1: interp_rate_cic_a = 16'd5;
+      16'h2: interp_rate_cic_a = 16'd50;
+      16'h3: interp_rate_cic_a = 16'd500;
+      16'h6: interp_rate_cic_a = 16'd5000;
+      16'h7: interp_rate_cic_a = 16'd50000;
+      default: interp_rate_cic_a = 16'd1;
+    endcase
+
+    case (filter_mask_b)
+      16'h1: interp_rate_cic_b = 16'd5;
+      16'h2: interp_rate_cic_b = 16'd50;
+      16'h3: interp_rate_cic_b = 16'd500;
+      16'h6: interp_rate_cic_b = 16'd5000;
+      16'h7: interp_rate_cic_b = 16'd50000;
+      default: interp_rate_cic_b = 16'd1;
+    endcase
+  end
+
+  axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
+
+    .clk (dac_clk),
+
+    .dac_interpolation_ratio_a (interpolation_ratio_a),
+    .dac_filter_mask_a (filter_mask_a),
+    .dac_interpolation_ratio_b (interpolation_ratio_b),
+    .dac_filter_mask_b (filter_mask_b),
+
+    .dma_transfer_suspend (dma_transfer_suspend),
+
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+  up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc b/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc
new file mode 100644
index 000000000..52097cb82
--- /dev/null
+++ b/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc
@@ -0,0 +1,11 @@
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
+
+set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg   && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg   && IS_SEQUENTIAL}]
+set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data*       && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl*          && IS_SEQUENTIAL}]
+set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg     && IS_SEQUENTIAL}]
+
diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl
new file mode 100644
index 000000000..effd1ce25
--- /dev/null
+++ b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl
@@ -0,0 +1,25 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_dac_interpolate
+adi_ip_files axi_dac_interpolate [list \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "axi_dac_interpolate_constr.xdc" \
+  "cic_interp.v" \
+  "fir_interp.v" \
+  "axi_dac_interpolate_reg.v" \
+  "axi_dac_interpolate.v" ]
+
+adi_ip_properties axi_dac_interpolate
+adi_ip_constraints axi_dac_interpolate [list \
+  "axi_dac_interpolate_constr.xdc" ]
+
+ipx::remove_bus_interface {clk} [ipx::current_core]
+ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+
diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v
new file mode 100644
index 000000000..ad33beb63
--- /dev/null
+++ b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v
@@ -0,0 +1,161 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dac_interpolate_reg(
+
+  input               clk,
+
+  output      [31:0]  dac_interpolation_ratio_a,
+  output      [31:0]  dac_filter_mask_a,
+  output      [31:0]  dac_interpolation_ratio_b,
+  output      [31:0]  dac_filter_mask_b,
+  output              dma_transfer_suspend,
+
+ // bus interface
+
+  input               up_rstn,
+  input               up_clk,
+  input               up_wreq,
+  input       [13:0]  up_waddr,
+  input       [31:0]  up_wdata,
+  output reg          up_wack,
+  input               up_rreq,
+  input       [13:0]  up_raddr,
+  output reg  [31:0]  up_rdata,
+  output reg          up_rack);
+
+  // internal signals
+
+  wire            up_wreq_s;
+  wire            up_rreq_s;
+
+  // internal registers
+
+  reg     [31:0]  up_version = 32'h00020000;
+  reg     [31:0]  up_scratch = 32'h0;
+
+  reg     [31:0]  up_interpolation_ratio_a = 32'h0;
+  reg     [31:0]  up_filter_mask_a  = 32'h0;
+  reg     [31:0]  up_interpolation_ratio_b = 32'h0;
+  reg     [31:0]  up_filter_mask_b  = 32'h0;
+  reg     [31:0]  up_flags  = 32'h0;
+
+  assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
+  assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_scratch <= 'd0;
+      up_interpolation_ratio_a <= 'd0;
+      up_filter_mask_a <= 'd0;
+      up_interpolation_ratio_b <= 'd0;
+      up_filter_mask_b <= 'd0;
+      up_flags <= 'd0;
+    end else begin
+      up_wack <= up_wreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
+        up_scratch <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
+        up_interpolation_ratio_a <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
+        up_filter_mask_a <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
+        up_interpolation_ratio_b <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
+        up_filter_mask_b <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
+        up_flags <= up_wdata;
+      end
+    end
+  end
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_rack <= up_rreq_s;
+      if (up_rreq_s == 1'b1) begin
+        case (up_raddr[4:0])
+          5'h0: up_rdata  <= up_version;
+          5'h1: up_rdata  <= up_scratch;
+          5'h10: up_rdata <= up_interpolation_ratio_a;
+          5'h11: up_rdata <= up_filter_mask_a;
+          5'h12: up_rdata <= up_interpolation_ratio_b;
+          5'h13: up_rdata <= up_filter_mask_b;
+          5'h14: up_rdata <= up_flags;
+          default: up_rdata <= 0;
+        endcase
+      end else begin
+        up_rdata <= 32'd0;
+      end
+    end
+  end
+
+   up_xfer_cntrl #(.DATA_WIDTH(129)) i_xfer_cntrl (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_data_cntrl ({ up_flags[0],              //  1
+                      up_interpolation_ratio_b, // 32
+                      up_interpolation_ratio_a, // 32
+                      up_filter_mask_b,         // 32
+                      up_filter_mask_a}),       // 32
+
+    .up_xfer_done (),
+    .d_rst (1'b0),
+    .d_clk (clk),
+    .d_data_cntrl ({  dma_transfer_suspend,       //  1
+                      dac_interpolation_ratio_b,  // 32
+                      dac_interpolation_ratio_a,  // 32
+                      dac_filter_mask_b,          // 32
+                      dac_filter_mask_a}));       // 32
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_dac_interpolate/cic_interp.v b/library/axi_dac_interpolate/cic_interp.v
new file mode 100644
index 000000000..5b0d3e493
--- /dev/null
+++ b/library/axi_dac_interpolate/cic_interp.v
@@ -0,0 +1,614 @@
+// -------------------------------------------------------------
+//
+// Module: cic_interp
+// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
+// Generated on: 2016-07-05 11:08:04
+// -------------------------------------------------------------
+
+// -------------------------------------------------------------
+// HDL Code Generation Options:
+//
+// OptimizeForHDL: on
+// EDAScriptGeneration: off
+// AddPipelineRegisters: on
+// Name: cic_interp
+// AddRatePort: on
+// InputDataType: numerictype(1,31,30)
+// TargetLanguage: Verilog
+// TestBenchName: cicinterpfilt_copy_tb
+// TestBenchStimulus: step ramp chirp noise
+// GenerateHDLTestBench: off
+
+// -------------------------------------------------------------
+// HDL Implementation    : Fully parallel
+// -------------------------------------------------------------
+// Filter Settings:
+//
+// Discrete-Time FIR Multirate Filter (real)
+// -----------------------------------------
+// Filter Structure      : Cascaded Integrator-Comb Interpolator
+// Interpolation Factor  : 50000
+// Differential Delay    : 1
+// Number of Sections    : 6
+// Stable                : Yes
+// Linear Phase          : No
+//
+// -------------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module cic_interp
+               (
+                clk,
+                clk_enable,
+                reset,
+                filter_in,
+                rate,
+                load_rate,
+                filter_out,
+                ce_out
+                );
+
+  input   clk;
+  input   clk_enable;
+  input   reset;
+  input   signed [30:0] filter_in; //sfix31_En30
+  input   [15:0] rate; //ufix16
+  input   load_rate;
+  output  signed [109:0] filter_out; //sfix110_En30
+  output  ce_out;
+
+////////////////////////////////////////////////////////////////
+//Module Architecture: cic_interp
+////////////////////////////////////////////////////////////////
+  // Local Functions
+  // Type Definitions
+  // Constants
+  parameter signed [35:0] zeroconst = 36'h000000000; //sfix36_En30
+  // Signals
+  wire [15:0] rate_unsigned; // ufix16
+  reg  [15:0] cur_count = 0; // ufix16
+  wire phase_0; // boolean
+  //
+  reg  signed [30:0] input_register = 0; // sfix31_En30
+  //   -- Section 1 Signals
+  wire signed [30:0] section_in1; // sfix31_En30
+  wire signed [31:0] section_cast1; // sfix32_En30
+  reg  signed [31:0] diff1 = 0; // sfix32_En30
+  wire signed [31:0] section_out1; // sfix32_En30
+  wire signed [31:0] sub_cast; // sfix32_En30
+  wire signed [31:0] sub_cast_1; // sfix32_En30
+  wire signed [32:0] sub_temp; // sfix33_En30
+  reg  signed [31:0] cic_pipeline1 = 0; // sfix32_En30
+  //   -- Section 2 Signals
+  wire signed [31:0] section_in2; // sfix32_En30
+  wire signed [32:0] section_cast2; // sfix33_En30
+  reg  signed [32:0] diff2 = 0; // sfix33_En30
+  wire signed [32:0] section_out2; // sfix33_En30
+  wire signed [32:0] sub_cast_2; // sfix33_En30
+  wire signed [32:0] sub_cast_3; // sfix33_En30
+  wire signed [33:0] sub_temp_1; // sfix34_En30
+  reg  signed [32:0] cic_pipeline2 = 0; // sfix33_En30
+  //   -- Section 3 Signals
+  wire signed [32:0] section_in3; // sfix33_En30
+  wire signed [33:0] section_cast3; // sfix34_En30
+  reg  signed [33:0] diff3 = 0; // sfix34_En30
+  wire signed [33:0] section_out3; // sfix34_En30
+  wire signed [33:0] sub_cast_4; // sfix34_En30
+  wire signed [33:0] sub_cast_5; // sfix34_En30
+  wire signed [34:0] sub_temp_2; // sfix35_En30
+  reg  signed [33:0] cic_pipeline3 = 0; // sfix34_En30
+  //   -- Section 4 Signals
+  wire signed [33:0] section_in4; // sfix34_En30
+  wire signed [34:0] section_cast4; // sfix35_En30
+  reg  signed [34:0] diff4 = 0; // sfix35_En30
+  wire signed [34:0] section_out4; // sfix35_En30
+  wire signed [34:0] sub_cast_6; // sfix35_En30
+  wire signed [34:0] sub_cast_7; // sfix35_En30
+  wire signed [35:0] sub_temp_3; // sfix36_En30
+  reg  signed [34:0] cic_pipeline4 = 0; // sfix35_En30
+  //   -- Section 5 Signals
+  wire signed [34:0] section_in5; // sfix35_En30
+  wire signed [35:0] section_cast5; // sfix36_En30
+  reg  signed [35:0] diff5 = 0; // sfix36_En30
+  wire signed [35:0] section_out5; // sfix36_En30
+  wire signed [35:0] sub_cast_8; // sfix36_En30
+  wire signed [35:0] sub_cast_9; // sfix36_En30
+  wire signed [36:0] sub_temp_4; // sfix37_En30
+  reg  signed [35:0] cic_pipeline5 = 0; // sfix36_En30
+  //   -- Section 6 Signals
+  wire signed [35:0] section_in6; // sfix36_En30
+  reg  signed [35:0] diff6 = 0; // sfix36_En30
+  wire signed [35:0] section_out6; // sfix36_En30
+  wire signed [35:0] sub_cast_10; // sfix36_En30
+  wire signed [35:0] sub_cast_11; // sfix36_En30
+  wire signed [36:0] sub_temp_5; // sfix37_En30
+  reg  signed [35:0] cic_pipeline6 = 0; // sfix36_En30
+  wire signed [35:0] upsampling; // sfix36_En30
+  //   -- Section 7 Signals
+  wire signed [35:0] section_in7; // sfix36_En30
+  wire signed [35:0] sum1; // sfix36_En30
+  reg  signed [35:0] section_out7 = 0; // sfix36_En30
+  wire signed [35:0] add_cast; // sfix36_En30
+  wire signed [35:0] add_cast_1; // sfix36_En30
+  wire signed [36:0] add_temp; // sfix37_En30
+  //   -- Section 8 Signals
+  wire signed [35:0] section_in8; // sfix36_En30
+  wire signed [50:0] section_cast8; // sfix51_En30
+  wire signed [50:0] sum2; // sfix51_En30
+  reg  signed [50:0] section_out8 = 0; // sfix51_En30
+  wire signed [50:0] add_cast_2; // sfix51_En30
+  wire signed [50:0] add_cast_3; // sfix51_En30
+  wire signed [51:0] add_temp_1; // sfix52_En30
+  //   -- Section 9 Signals
+  wire signed [50:0] section_in9; // sfix51_En30
+  wire signed [65:0] section_cast9; // sfix66_En30
+  wire signed [65:0] sum3; // sfix66_En30
+  reg  signed [65:0] section_out9 = 0; // sfix66_En30
+  wire signed [65:0] add_cast_4; // sfix66_En30
+  wire signed [65:0] add_cast_5; // sfix66_En30
+  wire signed [66:0] add_temp_2; // sfix67_En30
+  //   -- Section 10 Signals
+  wire signed [65:0] section_in10; // sfix66_En30
+  wire signed [79:0] section_cast10; // sfix80_En30
+  wire signed [79:0] sum4; // sfix80_En30
+  reg  signed [79:0] section_out10 = 0; // sfix80_En30
+  wire signed [79:0] add_cast_6; // sfix80_En30
+  wire signed [79:0] add_cast_7; // sfix80_En30
+  wire signed [80:0] add_temp_3; // sfix81_En30
+  //   -- Section 11 Signals
+  wire signed [79:0] section_in11; // sfix80_En30
+  wire signed [94:0] section_cast11; // sfix95_En30
+  wire signed [94:0] sum5; // sfix95_En30
+  reg  signed [94:0] section_out11 = 0; // sfix95_En30
+  wire signed [94:0] add_cast_8; // sfix95_En30
+  wire signed [94:0] add_cast_9; // sfix95_En30
+  wire signed [95:0] add_temp_4; // sfix96_En30
+  //   -- Section 12 Signals
+  wire signed [94:0] section_in12; // sfix95_En30
+  wire signed [109:0] section_cast12; // sfix110_En30
+  wire signed [109:0] sum6; // sfix110_En30
+  reg  signed [109:0] section_out12 = 0; // sfix110_En30
+  wire signed [109:0] add_cast_10; // sfix110_En30
+  wire signed [109:0] add_cast_11; // sfix110_En30
+  wire signed [110:0] add_temp_5; // sfix111_En30
+  reg  [6:0] bitgain = 0; // ufix7
+  wire signed [109:0] output_typeconvert; // sfix110_En30
+  wire signed [109:0] muxinput_14; // sfix110_En16
+  wire signed [109:0] muxinput_34; // sfix110_E4
+  wire signed [109:0] muxinput_54; // sfix110_E24
+  wire signed [109:0] muxinput_74; // sfix110_E44
+  wire signed [109:0] muxinput_94; // sfix110_E64
+  //
+  reg  signed [109:0] output_register = 0; // sfix110_En30
+
+  // Block Statements
+  assign rate_unsigned = rate;
+
+  always @ (posedge clk or posedge reset)
+    begin: ce_output
+      if (reset == 1'b1) begin
+        cur_count <= 16'b0000000000000000;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          if (load_rate ==  1'b1) begin
+            cur_count <= 16'b0000000000000001;
+          end
+          else if (cur_count == rate_unsigned - 1) begin
+            cur_count <= 16'b0000000000000000;
+          end
+          else begin
+            cur_count <= cur_count + 1;
+          end
+        end
+      end
+    end // ce_output
+
+  assign  phase_0 = (cur_count == 16'b0000000000000000 && clk_enable == 1'b1)? 1 : 0;
+
+  //   ------------------ Input Register ------------------
+
+  always @ (posedge clk or posedge reset)
+    begin: input_reg_process
+      if (reset == 1'b1) begin
+        input_register <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          input_register <= filter_in;
+        end
+      end
+    end // input_reg_process
+
+  //   ------------------ Section # 1 : Comb ------------------
+
+  assign section_in1 = input_register;
+
+  assign section_cast1 = $signed({{1{section_in1[30]}}, section_in1});
+
+  assign sub_cast = section_cast1;
+  assign sub_cast_1 = diff1;
+  assign sub_temp = sub_cast - sub_cast_1;
+  assign section_out1 = sub_temp[31:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section1
+      if (reset == 1'b1) begin
+        diff1 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          diff1 <= section_cast1;
+        end
+      end
+    end // comb_delay_section1
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section1
+      if (reset == 1'b1) begin
+        cic_pipeline1 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          cic_pipeline1 <= section_out1;
+        end
+      end
+    end // cic_pipeline_process_section1
+
+  //   ------------------ Section # 2 : Comb ------------------
+
+  assign section_in2 = cic_pipeline1;
+
+  assign section_cast2 = $signed({{1{section_in2[31]}}, section_in2});
+
+  assign sub_cast_2 = section_cast2;
+  assign sub_cast_3 = diff2;
+  assign sub_temp_1 = sub_cast_2 - sub_cast_3;
+  assign section_out2 = sub_temp_1[32:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section2
+      if (reset == 1'b1) begin
+        diff2 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          diff2 <= section_cast2;
+        end
+      end
+    end // comb_delay_section2
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section2
+      if (reset == 1'b1) begin
+        cic_pipeline2 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          cic_pipeline2 <= section_out2;
+        end
+      end
+    end // cic_pipeline_process_section2
+
+  //   ------------------ Section # 3 : Comb ------------------
+
+  assign section_in3 = cic_pipeline2;
+
+  assign section_cast3 = $signed({{1{section_in3[32]}}, section_in3});
+
+  assign sub_cast_4 = section_cast3;
+  assign sub_cast_5 = diff3;
+  assign sub_temp_2 = sub_cast_4 - sub_cast_5;
+  assign section_out3 = sub_temp_2[33:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section3
+      if (reset == 1'b1) begin
+        diff3 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          diff3 <= section_cast3;
+        end
+      end
+    end // comb_delay_section3
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section3
+      if (reset == 1'b1) begin
+        cic_pipeline3 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          cic_pipeline3 <= section_out3;
+        end
+      end
+    end // cic_pipeline_process_section3
+
+  //   ------------------ Section # 4 : Comb ------------------
+
+  assign section_in4 = cic_pipeline3;
+
+  assign section_cast4 = $signed({{1{section_in4[33]}}, section_in4});
+
+  assign sub_cast_6 = section_cast4;
+  assign sub_cast_7 = diff4;
+  assign sub_temp_3 = sub_cast_6 - sub_cast_7;
+  assign section_out4 = sub_temp_3[34:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section4
+      if (reset == 1'b1) begin
+        diff4 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          diff4 <= section_cast4;
+        end
+      end
+    end // comb_delay_section4
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section4
+      if (reset == 1'b1) begin
+        cic_pipeline4 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          cic_pipeline4 <= section_out4;
+        end
+      end
+    end // cic_pipeline_process_section4
+
+  //   ------------------ Section # 5 : Comb ------------------
+
+  assign section_in5 = cic_pipeline4;
+
+  assign section_cast5 = $signed({{1{section_in5[34]}}, section_in5});
+
+  assign sub_cast_8 = section_cast5;
+  assign sub_cast_9 = diff5;
+  assign sub_temp_4 = sub_cast_8 - sub_cast_9;
+  assign section_out5 = sub_temp_4[35:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section5
+      if (reset == 1'b1) begin
+        diff5 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          diff5 <= section_cast5;
+        end
+      end
+    end // comb_delay_section5
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section5
+      if (reset == 1'b1) begin
+        cic_pipeline5 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          cic_pipeline5 <= section_out5;
+        end
+      end
+    end // cic_pipeline_process_section5
+
+  //   ------------------ Section # 6 : Comb ------------------
+
+  assign section_in6 = cic_pipeline5;
+
+  assign sub_cast_10 = section_in6;
+  assign sub_cast_11 = diff6;
+  assign sub_temp_5 = sub_cast_10 - sub_cast_11;
+  assign section_out6 = sub_temp_5[35:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: comb_delay_section6
+      if (reset == 1'b1) begin
+        diff6 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          diff6 <= section_in6;
+        end
+      end
+    end // comb_delay_section6
+
+  always @ (posedge clk or posedge reset)
+    begin: cic_pipeline_process_section6
+      if (reset == 1'b1) begin
+        cic_pipeline6 <= 0;
+      end
+      else begin
+        if (phase_0 == 1'b1) begin
+          cic_pipeline6 <= section_out6;
+        end
+      end
+    end // cic_pipeline_process_section6
+
+  assign upsampling = (phase_0 == 1'b1) ? cic_pipeline6 :
+                zeroconst;
+  //   ------------------ Section # 7 : Integrator ------------------
+
+  assign section_in7 = upsampling;
+
+  assign add_cast = section_in7;
+  assign add_cast_1 = section_out7;
+  assign add_temp = add_cast + add_cast_1;
+  assign sum1 = add_temp[35:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section7
+      if (reset == 1'b1) begin
+        section_out7 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out7 <= sum1;
+        end
+      end
+    end // integrator_delay_section7
+
+  //   ------------------ Section # 8 : Integrator ------------------
+
+  assign section_in8 = section_out7;
+
+  assign section_cast8 = $signed({{15{section_in8[35]}}, section_in8});
+
+  assign add_cast_2 = section_cast8;
+  assign add_cast_3 = section_out8;
+  assign add_temp_1 = add_cast_2 + add_cast_3;
+  assign sum2 = add_temp_1[50:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section8
+      if (reset == 1'b1) begin
+        section_out8 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out8 <= sum2;
+        end
+      end
+    end // integrator_delay_section8
+
+  //   ------------------ Section # 9 : Integrator ------------------
+
+  assign section_in9 = section_out8;
+
+  assign section_cast9 = $signed({{15{section_in9[50]}}, section_in9});
+
+  assign add_cast_4 = section_cast9;
+  assign add_cast_5 = section_out9;
+  assign add_temp_2 = add_cast_4 + add_cast_5;
+  assign sum3 = add_temp_2[65:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section9
+      if (reset == 1'b1) begin
+        section_out9 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out9 <= sum3;
+        end
+      end
+    end // integrator_delay_section9
+
+  //   ------------------ Section # 10 : Integrator ------------------
+
+  assign section_in10 = section_out9;
+
+  assign section_cast10 = $signed({{14{section_in10[65]}}, section_in10});
+
+  assign add_cast_6 = section_cast10;
+  assign add_cast_7 = section_out10;
+  assign add_temp_3 = add_cast_6 + add_cast_7;
+  assign sum4 = add_temp_3[79:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section10
+      if (reset == 1'b1) begin
+        section_out10 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out10 <= sum4;
+        end
+      end
+    end // integrator_delay_section10
+
+  //   ------------------ Section # 11 : Integrator ------------------
+
+  assign section_in11 = section_out10;
+
+  assign section_cast11 = $signed({{15{section_in11[79]}}, section_in11});
+
+  assign add_cast_8 = section_cast11;
+  assign add_cast_9 = section_out11;
+  assign add_temp_4 = add_cast_8 + add_cast_9;
+  assign sum5 = add_temp_4[94:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section11
+      if (reset == 1'b1) begin
+        section_out11 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out11 <= sum5;
+        end
+      end
+    end // integrator_delay_section11
+
+  //   ------------------ Section # 12 : Integrator ------------------
+
+  assign section_in12 = section_out11;
+
+  assign section_cast12 = $signed({{15{section_in12[94]}}, section_in12});
+
+  assign add_cast_10 = section_cast12;
+  assign add_cast_11 = section_out12;
+  assign add_temp_5 = add_cast_10 + add_cast_11;
+  assign sum6 = add_temp_5[109:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: integrator_delay_section12
+      if (reset == 1'b1) begin
+        section_out12 <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          section_out12 <= sum6;
+        end
+      end
+    end // integrator_delay_section12
+
+  always @(rate_unsigned)
+  begin
+    case(rate_unsigned)
+      16'b0000000000000101 : bitgain = 7'b0001110;
+      16'b0000000000110010 : bitgain = 7'b0100010;
+      16'b0000000111110100 : bitgain = 7'b0110110;
+      16'b0001001110001000 : bitgain = 7'b1001010;
+      16'b1100001101010000 : bitgain = 7'b1011110;
+      default : bitgain = 7'b1011110;
+    endcase
+  end
+
+  assign muxinput_14 = $signed({{10{section_out12[109]}}, section_out12[109:10]});
+
+  assign muxinput_34 = $signed({{27{section_out12[109]}}, section_out12[109:27]});
+
+  assign muxinput_54 = $signed({{43{section_out12[109]}}, section_out12[109:43]});
+
+  assign muxinput_74 = $signed({{60{section_out12[109]}}, section_out12[109:60]});
+
+  assign muxinput_94 = $signed({{77{section_out12[109]}}, section_out12[109:77]});
+
+  assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 :
+                             (bitgain == 7'b0100010) ? muxinput_34 :
+                             (bitgain == 7'b0110110) ? muxinput_54 :
+                             (bitgain == 7'b1001010) ? muxinput_74 :
+                             muxinput_94;
+  //   ------------------ Output Register ------------------
+
+  always @ (posedge clk or posedge reset)
+    begin: output_reg_process
+      if (reset == 1'b1) begin
+        output_register <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          output_register <= output_typeconvert;
+        end
+      end
+    end // output_reg_process
+
+  // Assignment Statements
+  assign ce_out = phase_0;
+  assign filter_out = output_register;
+endmodule  // cic_interp
diff --git a/library/axi_dac_interpolate/fir_interp.v b/library/axi_dac_interpolate/fir_interp.v
new file mode 100644
index 000000000..4d6fd69ba
--- /dev/null
+++ b/library/axi_dac_interpolate/fir_interp.v
@@ -0,0 +1,390 @@
+// -------------------------------------------------------------
+//
+// Module: fir_interp
+// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
+// Generated on: 2016-07-05 15:54:12
+// -------------------------------------------------------------
+
+// -------------------------------------------------------------
+// HDL Code Generation Options:
+//
+// FIRAdderStyle: tree
+// OptimizeForHDL: on
+// EDAScriptGeneration: off
+// AddPipelineRegisters: on
+// Name: fir_interp
+// TargetLanguage: Verilog
+// TestBenchName: fo_copy_tb
+// TestBenchStimulus: step ramp chirp noise
+// GenerateHDLTestBench: off
+
+// -------------------------------------------------------------
+// HDL Implementation    : Fully parallel
+// Multipliers           : 12
+// Folding Factor        : 1
+// -------------------------------------------------------------
+// Filter Settings:
+//
+// Discrete-Time FIR Multirate Filter (real)
+// -----------------------------------------
+// Filter Structure      : Direct-Form FIR Polyphase Interpolator
+// Interpolation Factor  : 2
+// Polyphase Length      : 12
+// Filter Length         : 24
+// Stable                : Yes
+// Linear Phase          : Yes (Type 2)
+//
+// Arithmetic            : fixed
+// Numerator             : s16,15 -> [-1 1)
+// -------------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module fir_interp
+               (
+                clk,
+                clk_enable,
+                reset,
+                filter_in,
+                filter_out,
+                ce_out
+                );
+
+  input   clk;
+  input   clk_enable;
+  input   reset;
+  input   signed [15:0] filter_in; //sfix16_En15
+  output  signed [35:0] filter_out; //sfix36_En30
+  output  ce_out;
+
+////////////////////////////////////////////////////////////////
+//Module Architecture: fir_interp
+////////////////////////////////////////////////////////////////
+  // Local Functions
+  // Type Definitions
+  // Constants
+  parameter signed [15:0] coeffphase1_1 = 16'b1111111110101001; //sfix16_En15
+  parameter signed [15:0] coeffphase1_2 = 16'b1111111101111010; //sfix16_En15
+  parameter signed [15:0] coeffphase1_3 = 16'b0000010011111111; //sfix16_En15
+  parameter signed [15:0] coeffphase1_4 = 16'b1111101010101110; //sfix16_En15
+  parameter signed [15:0] coeffphase1_5 = 16'b1111001001101000; //sfix16_En15
+  parameter signed [15:0] coeffphase1_6 = 16'b0011011010110011; //sfix16_En15
+  parameter signed [15:0] coeffphase1_7 = 16'b0101011100111111; //sfix16_En15
+  parameter signed [15:0] coeffphase1_8 = 16'b0000110010011010; //sfix16_En15
+  parameter signed [15:0] coeffphase1_9 = 16'b1111000000000010; //sfix16_En15
+  parameter signed [15:0] coeffphase1_10 = 16'b0000001110101000; //sfix16_En15
+  parameter signed [15:0] coeffphase1_11 = 16'b0000000111110010; //sfix16_En15
+  parameter signed [15:0] coeffphase1_12 = 16'b1111111100011100; //sfix16_En15
+  parameter signed [15:0] coeffphase2_1 = 16'b1111111100011100; //sfix16_En15
+  parameter signed [15:0] coeffphase2_2 = 16'b0000000111110010; //sfix16_En15
+  parameter signed [15:0] coeffphase2_3 = 16'b0000001110101000; //sfix16_En15
+  parameter signed [15:0] coeffphase2_4 = 16'b1111000000000010; //sfix16_En15
+  parameter signed [15:0] coeffphase2_5 = 16'b0000110010011010; //sfix16_En15
+  parameter signed [15:0] coeffphase2_6 = 16'b0101011100111111; //sfix16_En15
+  parameter signed [15:0] coeffphase2_7 = 16'b0011011010110011; //sfix16_En15
+  parameter signed [15:0] coeffphase2_8 = 16'b1111001001101000; //sfix16_En15
+  parameter signed [15:0] coeffphase2_9 = 16'b1111101010101110; //sfix16_En15
+  parameter signed [15:0] coeffphase2_10 = 16'b0000010011111111; //sfix16_En15
+  parameter signed [15:0] coeffphase2_11 = 16'b1111111101111010; //sfix16_En15
+  parameter signed [15:0] coeffphase2_12 = 16'b1111111110101001; //sfix16_En15
+
+  // Signals
+  reg  [1:0] cur_count = 0; // ufix2
+  wire phase_1; // boolean
+  reg  signed [15:0] delay_pipeline [0:11]; // sfix16_En15
+  wire signed [31:0] product; // sfix32_En30
+  wire signed [15:0] product_mux; // sfix16_En15
+  wire signed [31:0] product_1; // sfix32_En30
+  wire signed [15:0] product_mux_1; // sfix16_En15
+  wire signed [31:0] product_2; // sfix32_En30
+  wire signed [15:0] product_mux_2; // sfix16_En15
+  wire signed [31:0] product_3; // sfix32_En30
+  wire signed [15:0] product_mux_3; // sfix16_En15
+  wire signed [31:0] product_4; // sfix32_En30
+  wire signed [15:0] product_mux_4; // sfix16_En15
+  wire signed [31:0] product_5; // sfix32_En30
+  wire signed [15:0] product_mux_5; // sfix16_En15
+  wire signed [31:0] product_6; // sfix32_En30
+  wire signed [15:0] product_mux_6; // sfix16_En15
+  wire signed [31:0] product_7; // sfix32_En30
+  wire signed [15:0] product_mux_7; // sfix16_En15
+  wire signed [31:0] product_8; // sfix32_En30
+  wire signed [15:0] product_mux_8; // sfix16_En15
+  wire signed [31:0] product_9; // sfix32_En30
+  wire signed [15:0] product_mux_9; // sfix16_En15
+  wire signed [31:0] product_10; // sfix32_En30
+  wire signed [15:0] product_mux_10; // sfix16_En15
+  wire signed [31:0] product_11; // sfix32_En30
+  wire signed [15:0] product_mux_11; // sfix16_En15
+  wire signed [35:0] sumvector1 [0:5] ; // sfix36_En30
+  wire signed [31:0] add_signext; // sfix32_En30
+  wire signed [31:0] add_signext_1; // sfix32_En30
+  wire signed [32:0] add_temp; // sfix33_En30
+  wire signed [31:0] add_signext_2; // sfix32_En30
+  wire signed [31:0] add_signext_3; // sfix32_En30
+  wire signed [32:0] add_temp_1; // sfix33_En30
+  wire signed [31:0] add_signext_4; // sfix32_En30
+  wire signed [31:0] add_signext_5; // sfix32_En30
+  wire signed [32:0] add_temp_2; // sfix33_En30
+  wire signed [31:0] add_signext_6; // sfix32_En30
+  wire signed [31:0] add_signext_7; // sfix32_En30
+  wire signed [32:0] add_temp_3; // sfix33_En30
+  wire signed [31:0] add_signext_8; // sfix32_En30
+  wire signed [31:0] add_signext_9; // sfix32_En30
+  wire signed [32:0] add_temp_4; // sfix33_En30
+  wire signed [31:0] add_signext_10; // sfix32_En30
+  wire signed [31:0] add_signext_11; // sfix32_En30
+  wire signed [32:0] add_temp_5; // sfix33_En30
+  reg  signed [35:0] sumdelay_pipeline1 [0:5]; // sfix36_En30
+  wire signed [35:0] sumvector2 [0:2] ; // sfix36_En30
+  wire signed [35:0] add_signext_12; // sfix36_En30
+  wire signed [35:0] add_signext_13; // sfix36_En30
+  wire signed [36:0] add_temp_6; // sfix37_En30
+  wire signed [35:0] add_signext_14; // sfix36_En30
+  wire signed [35:0] add_signext_15; // sfix36_En30
+  wire signed [36:0] add_temp_7; // sfix37_En30
+  wire signed [35:0] add_signext_16; // sfix36_En30
+  wire signed [35:0] add_signext_17; // sfix36_En30
+  wire signed [36:0] add_temp_8; // sfix37_En30
+  reg  signed [35:0] sumdelay_pipeline2 [0:2]; // sfix36_En30
+  wire signed [35:0] sumvector3 [0:1] ; // sfix36_En30
+  wire signed [35:0] add_signext_18; // sfix36_En30
+  wire signed [35:0] add_signext_19; // sfix36_En30
+  wire signed [36:0] add_temp_9; // sfix37_En30
+  reg  signed [35:0] sumdelay_pipeline3 [0:1]; // sfix36_En30
+  wire signed [35:0] sum4; // sfix36_En30
+  wire signed [35:0] add_signext_20; // sfix36_En30
+  wire signed [35:0] add_signext_21; // sfix36_En30
+  wire signed [36:0] add_temp_10; // sfix37_En30
+  reg  signed [35:0] output_register = 0; // sfix36_En30
+
+  // Block Statements
+  always @ (posedge clk or posedge reset)
+    begin: ce_output
+      if (reset == 1'b1) begin
+        cur_count <= 2'b00;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          if (cur_count == 2'b01) begin
+            cur_count <= 2'b00;
+          end
+          else begin
+            cur_count <= cur_count + 1;
+          end
+        end
+      end
+    end // ce_output
+
+  assign  phase_1 = (cur_count == 2'b01 && clk_enable == 1'b1)? 1 : 0;
+
+  //   ---------------- Delay Registers ----------------
+
+  always @( posedge clk or posedge reset)
+    begin: Delay_Pipeline_process
+      if (reset == 1'b1) begin
+        delay_pipeline[0] <= 0;
+        delay_pipeline[1] <= 0;
+        delay_pipeline[2] <= 0;
+        delay_pipeline[3] <= 0;
+        delay_pipeline[4] <= 0;
+        delay_pipeline[5] <= 0;
+        delay_pipeline[6] <= 0;
+        delay_pipeline[7] <= 0;
+        delay_pipeline[8] <= 0;
+        delay_pipeline[9] <= 0;
+        delay_pipeline[10] <= 0;
+        delay_pipeline[11] <= 0;
+      end
+      else begin
+        if (phase_1 == 1'b1) begin
+          delay_pipeline[0] <= filter_in;
+          delay_pipeline[1] <= delay_pipeline[0];
+          delay_pipeline[2] <= delay_pipeline[1];
+          delay_pipeline[3] <= delay_pipeline[2];
+          delay_pipeline[4] <= delay_pipeline[3];
+          delay_pipeline[5] <= delay_pipeline[4];
+          delay_pipeline[6] <= delay_pipeline[5];
+          delay_pipeline[7] <= delay_pipeline[6];
+          delay_pipeline[8] <= delay_pipeline[7];
+          delay_pipeline[9] <= delay_pipeline[8];
+          delay_pipeline[10] <= delay_pipeline[9];
+          delay_pipeline[11] <= delay_pipeline[10];
+        end
+      end
+    end // Delay_Pipeline_process
+
+
+  assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 :
+                      coeffphase2_12;
+  assign product = delay_pipeline[11] * product_mux;
+
+  assign product_mux_1 = (cur_count == 2'b00) ? coeffphase1_11 :
+                        coeffphase2_11;
+  assign product_1 = delay_pipeline[10] * product_mux_1;
+
+  assign product_mux_2 = (cur_count == 2'b00) ? coeffphase1_10 :
+                        coeffphase2_10;
+  assign product_2 = delay_pipeline[9] * product_mux_2;
+
+  assign product_mux_3 = (cur_count == 2'b00) ? coeffphase1_9 :
+                        coeffphase2_9;
+  assign product_3 = delay_pipeline[8] * product_mux_3;
+
+  assign product_mux_4 = (cur_count == 2'b00) ? coeffphase1_8 :
+                        coeffphase2_8;
+  assign product_4 = delay_pipeline[7] * product_mux_4;
+
+  assign product_mux_5 = (cur_count == 2'b00) ? coeffphase1_7 :
+                        coeffphase2_7;
+  assign product_5 = delay_pipeline[6] * product_mux_5;
+
+  assign product_mux_6 = (cur_count == 2'b00) ? coeffphase1_6 :
+                        coeffphase2_6;
+  assign product_6 = delay_pipeline[5] * product_mux_6;
+
+  assign product_mux_7 = (cur_count == 2'b00) ? coeffphase1_5 :
+                        coeffphase2_5;
+  assign product_7 = delay_pipeline[4] * product_mux_7;
+
+  assign product_mux_8 = (cur_count == 2'b00) ? coeffphase1_4 :
+                        coeffphase2_4;
+  assign product_8 = delay_pipeline[3] * product_mux_8;
+
+  assign product_mux_9 = (cur_count == 2'b00) ? coeffphase1_3 :
+                        coeffphase2_3;
+  assign product_9 = delay_pipeline[2] * product_mux_9;
+
+  assign product_mux_10 = (cur_count == 2'b00) ? coeffphase1_2 :
+                         coeffphase2_2;
+  assign product_10 = delay_pipeline[1] * product_mux_10;
+
+  assign product_mux_11 = (cur_count == 2'b00) ? coeffphase1_1 :
+                         coeffphase2_1;
+  assign product_11 = delay_pipeline[0] * product_mux_11;
+
+  assign add_signext = product;
+  assign add_signext_1 = product_1;
+  assign add_temp = add_signext + add_signext_1;
+  assign sumvector1[0] = $signed({{3{add_temp[32]}}, add_temp});
+
+  assign add_signext_2 = product_2;
+  assign add_signext_3 = product_3;
+  assign add_temp_1 = add_signext_2 + add_signext_3;
+  assign sumvector1[1] = $signed({{3{add_temp_1[32]}}, add_temp_1});
+
+  assign add_signext_4 = product_4;
+  assign add_signext_5 = product_5;
+  assign add_temp_2 = add_signext_4 + add_signext_5;
+  assign sumvector1[2] = $signed({{3{add_temp_2[32]}}, add_temp_2});
+
+  assign add_signext_6 = product_6;
+  assign add_signext_7 = product_7;
+  assign add_temp_3 = add_signext_6 + add_signext_7;
+  assign sumvector1[3] = $signed({{3{add_temp_3[32]}}, add_temp_3});
+
+  assign add_signext_8 = product_8;
+  assign add_signext_9 = product_9;
+  assign add_temp_4 = add_signext_8 + add_signext_9;
+  assign sumvector1[4] = $signed({{3{add_temp_4[32]}}, add_temp_4});
+
+  assign add_signext_10 = product_10;
+  assign add_signext_11 = product_11;
+  assign add_temp_5 = add_signext_10 + add_signext_11;
+  assign sumvector1[5] = $signed({{3{add_temp_5[32]}}, add_temp_5});
+
+  always @ (posedge clk or posedge reset)
+    begin: sumdelay_pipeline_process1
+      if (reset == 1'b1) begin
+        sumdelay_pipeline1[0] <= 0;
+        sumdelay_pipeline1[1] <= 0;
+        sumdelay_pipeline1[2] <= 0;
+        sumdelay_pipeline1[3] <= 0;
+        sumdelay_pipeline1[4] <= 0;
+        sumdelay_pipeline1[5] <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          sumdelay_pipeline1[0] <= sumvector1[0];
+          sumdelay_pipeline1[1] <= sumvector1[1];
+          sumdelay_pipeline1[2] <= sumvector1[2];
+          sumdelay_pipeline1[3] <= sumvector1[3];
+          sumdelay_pipeline1[4] <= sumvector1[4];
+          sumdelay_pipeline1[5] <= sumvector1[5];
+        end
+      end
+    end // sumdelay_pipeline_process1
+
+  assign add_signext_12 = sumdelay_pipeline1[0];
+  assign add_signext_13 = sumdelay_pipeline1[1];
+  assign add_temp_6 = add_signext_12 + add_signext_13;
+  assign sumvector2[0] = add_temp_6[35:0];
+
+  assign add_signext_14 = sumdelay_pipeline1[2];
+  assign add_signext_15 = sumdelay_pipeline1[3];
+  assign add_temp_7 = add_signext_14 + add_signext_15;
+  assign sumvector2[1] = add_temp_7[35:0];
+
+  assign add_signext_16 = sumdelay_pipeline1[4];
+  assign add_signext_17 = sumdelay_pipeline1[5];
+  assign add_temp_8 = add_signext_16 + add_signext_17;
+  assign sumvector2[2] = add_temp_8[35:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: sumdelay_pipeline_process2
+      if (reset == 1'b1) begin
+        sumdelay_pipeline2[0] <= 0;
+        sumdelay_pipeline2[1] <= 0;
+        sumdelay_pipeline2[2] <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          sumdelay_pipeline2[0] <= sumvector2[0];
+          sumdelay_pipeline2[1] <= sumvector2[1];
+          sumdelay_pipeline2[2] <= sumvector2[2];
+        end
+      end
+    end // sumdelay_pipeline_process2
+
+  assign add_signext_18 = sumdelay_pipeline2[0];
+  assign add_signext_19 = sumdelay_pipeline2[1];
+  assign add_temp_9 = add_signext_18 + add_signext_19;
+  assign sumvector3[0] = add_temp_9[35:0];
+
+  assign sumvector3[1] = sumdelay_pipeline2[2];
+
+  always @ (posedge clk or posedge reset)
+    begin: sumdelay_pipeline_process3
+      if (reset == 1'b1) begin
+        sumdelay_pipeline3[0] <= 0;
+        sumdelay_pipeline3[1] <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          sumdelay_pipeline3[0] <= sumvector3[0];
+          sumdelay_pipeline3[1] <= sumvector3[1];
+        end
+      end
+    end // sumdelay_pipeline_process3
+
+  assign add_signext_20 = sumdelay_pipeline3[0];
+  assign add_signext_21 = sumdelay_pipeline3[1];
+  assign add_temp_10 = add_signext_20 + add_signext_21;
+  assign sum4 = add_temp_10[35:0];
+
+  always @ (posedge clk or posedge reset)
+    begin: Output_Register_process
+      if (reset == 1'b1) begin
+        output_register <= 0;
+      end
+      else begin
+        if (clk_enable == 1'b1) begin
+          output_register <= sum4;
+        end
+      end
+    end // Output_Register_process
+
+  // Assignment Statements
+  assign ce_out = phase_1;
+  assign filter_out = output_register;
+endmodule  // fir_interp

From 6604cc7322f13eaf30629fdada743b7e74e7ac54 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:23:56 +0200
Subject: [PATCH 881/972] axi_logic_analyzer: Initial commit

---
 library/axi_logic_analyzer/Makefile           |  53 ++++
 .../axi_logic_analyzer/axi_logic_analyzer.v   | 297 ++++++++++++++++++
 .../axi_logic_analyzer_constr.xdc             |  30 ++
 .../axi_logic_analyzer_ip.tcl                 |  25 ++
 .../axi_logic_analyzer_reg.v                  | 264 ++++++++++++++++
 .../axi_logic_analyzer_trigger.v              | 114 +++++++
 6 files changed, 783 insertions(+)
 create mode 100644 library/axi_logic_analyzer/Makefile
 create mode 100644 library/axi_logic_analyzer/axi_logic_analyzer.v
 create mode 100644 library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
 create mode 100644 library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
 create mode 100644 library/axi_logic_analyzer/axi_logic_analyzer_reg.v
 create mode 100644 library/axi_logic_analyzer/axi_logic_analyzer_trigger.v

diff --git a/library/axi_logic_analyzer/Makefile b/library/axi_logic_analyzer/Makefile
new file mode 100644
index 000000000..f538e037e
--- /dev/null
+++ b/library/axi_logic_analyzer/Makefile
@@ -0,0 +1,53 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += ../common/ad_rst.v
+M_DEPS += ../common/up_axi.v
+M_DEPS += ../common/up_xfer_cntrl.v
+M_DEPS += ../common/up_xfer_status.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += axi_logic_analyzer.v
+M_DEPS += axi_logic_analyzer_constr.xdc
+M_DEPS += axi_logic_analyzer_ip.tcl
+M_DEPS += axi_logic_analyzer_reg.v
+M_DEPS += axi_logic_analyzer_trigger.v
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: axi_logic_analyzer.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+axi_logic_analyzer.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) axi_logic_analyzer_ip.tcl  >> axi_logic_analyzer_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v
new file mode 100644
index 000000000..e00a7920c
--- /dev/null
+++ b/library/axi_logic_analyzer/axi_logic_analyzer.v
@@ -0,0 +1,297 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_logic_analyzer (
+
+  input                 clk,
+  output                clk_out,
+
+  input       [15:0]    data_i,
+  output reg  [15:0]    data_o,
+  output      [15:0]    data_t,
+  input       [ 1:0]    trigger_i,
+
+  output reg            adc_valid,
+  output reg  [15:0]    adc_data,
+
+  input       [15:0]    dac_data,
+  input                 dac_valid,
+  output reg            dac_read,
+
+  output                trigger_out,
+  output      [31:0]    trigger_offset,
+
+  // axi interface
+
+  input                 s_axi_aclk,
+  input                 s_axi_aresetn,
+  input                 s_axi_awvalid,
+  input       [31:0]    s_axi_awaddr,
+  input       [ 2:0]    s_axi_awprot,
+  output                s_axi_awready,
+  input                 s_axi_wvalid,
+  input       [31:0]    s_axi_wdata,
+  input       [ 3:0]    s_axi_wstrb,
+  output                s_axi_wready,
+  output                s_axi_bvalid,
+  output      [ 1:0]    s_axi_bresp,
+  input                 s_axi_bready,
+  input                 s_axi_arvalid,
+  input       [31:0]    s_axi_araddr,
+  input       [ 2:0]    s_axi_arprot,
+  output                s_axi_arready,
+  output                s_axi_rvalid,
+  output      [31:0]    s_axi_rdata,
+  output      [ 1:0]    s_axi_rresp,
+  input                 s_axi_rready);
+
+  // internal registers
+
+  reg     [15:0]    data_m1 = 'd0;
+  reg     [15:0]    data_r = 'd0;
+  reg     [ 1:0]    trigger_m1 = 'd0;
+  reg     [ 1:0]    trigger_m2 = 'd0;
+  reg     [31:0]    downsampler_counter_la = 'd0;
+  reg     [31:0]    upsampler_counter_pg = 'd0;
+
+  reg               sample_valid_la = 'd0;
+  reg               adc_valid_d1 = 'd0;
+  reg               adc_valid_d2 = 'd0;
+
+  // internal signals
+
+  wire              up_clk;
+  wire              up_rstn;
+  wire    [13:0]    up_waddr;
+  wire    [31:0]    up_wdata;
+  wire              up_wack;
+  wire              up_wreq;
+  wire              up_rack;
+  wire    [31:0]    up_rdata;
+  wire              up_rreq;
+  wire    [13:0]    up_raddr;
+
+  wire    [31:0]    divider_counter_la;
+  wire    [31:0]    divider_counter_pg;
+
+  wire    [17:0]    edge_detect_enable;
+  wire    [17:0]    rise_edge_enable;
+  wire    [17:0]    fall_edge_enable;
+  wire    [17:0]    low_level_enable;
+  wire    [17:0]    high_level_enable;
+  wire    [31:0]    trigger_delay;
+  wire              trigger_logic; // 0-OR,1-AND,2-XOR,3-NOR,4-NAND,5-NXOR
+  wire              clock_select;
+  wire    [15:0]    overwrite_enable;
+  wire    [15:0]    overwrite_data;
+
+  wire    [15:0]    io_selection;
+  wire    [15:0]    od_pp_n; // 0 - push/pull, 1 - open drain
+
+  genvar i;
+
+  // signal name changes
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+
+  assign trigger_offset = trigger_delay;
+
+  generate
+  for (i = 0 ; i < 16; i = i + 1) begin
+    assign data_t[i] = od_pp_n[i] ? io_selection[i] & !data_o[i] : io_selection[i];
+    always @(posedge clk) begin
+      data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
+    end
+  end
+  endgenerate
+
+  BUFGMUX BUFGMUX_inst (
+    .O (clk_out),
+    .I0 (data_i[0]),
+    .I1 (trigger_i[0]),
+    .S (clock_select));
+
+  // synchronization
+
+  always @(posedge clk) begin
+    data_m1 <= data_i;
+    trigger_m1 <= trigger_i;
+    trigger_m2 <= trigger_m1;
+  end
+
+  // transfer data at clock frequency
+  // if capture is enabled
+
+  always @(posedge clk) begin
+  adc_valid_d1 <= adc_valid_d2;
+  adc_valid <= adc_valid_d1;
+    if (sample_valid_la == 1'b1) begin
+      adc_data  <= data_m1;
+      adc_valid_d2 <= 1'b1;
+    end else begin
+      adc_valid_d2 <= 1'b0;
+    end
+  end
+
+  // downsampler logic analyzer
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      sample_valid_la <= 1'b0;
+      downsampler_counter_la <= 32'h0;
+    end else begin
+      if (downsampler_counter_la < divider_counter_la ) begin
+        downsampler_counter_la <= downsampler_counter_la + 1;
+        sample_valid_la <= 1'b0;
+      end else begin
+        downsampler_counter_la <= 32'h0;
+        sample_valid_la <= 1'b1;
+      end
+    end
+  end
+
+  // upsampler pattern generator
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      upsampler_counter_pg <= 32'h0;
+      dac_read <= 1'b0;
+    end else begin
+      dac_read <= 1'b0;
+        if (upsampler_counter_pg < divider_counter_pg) begin
+          upsampler_counter_pg <= upsampler_counter_pg + 1;
+        end else begin
+          upsampler_counter_pg <= 32'h0;
+          dac_read <= 1'b1;
+        end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (dac_valid == 1'b1) begin
+      data_r <= dac_data;
+    end
+  end
+
+  axi_logic_analyzer_trigger i_trigger (
+    .clk (clk),
+    .reset (reset),
+
+    .data (adc_data),
+    .trigger (trigger_m2),
+
+    .edge_detect_enable (edge_detect_enable),
+    .rise_edge_enable (rise_edge_enable),
+    .fall_edge_enable (fall_edge_enable),
+    .low_level_enable (low_level_enable),
+    .high_level_enable (high_level_enable),
+    .trigger_logic (trigger_logic),
+    .trigger_out (trigger_out));
+
+   axi_logic_analyzer_reg i_registers (
+
+    .clk (clk),
+    .reset (reset),
+
+    .divider_counter_la (divider_counter_la),
+    .divider_counter_pg (divider_counter_pg),
+    .io_selection (io_selection),
+
+    .edge_detect_enable (edge_detect_enable),
+    .rise_edge_enable (rise_edge_enable),
+    .fall_edge_enable (fall_edge_enable),
+    .low_level_enable (low_level_enable),
+    .high_level_enable (high_level_enable),
+    .trigger_delay (trigger_delay),
+    .trigger_logic (trigger_logic),
+    .clock_select (clock_select),
+    .overwrite_enable (overwrite_enable),
+    .overwrite_data (overwrite_data),
+    .input_data (adc_data),
+    .od_pp_n (od_pp_n),
+
+    // bus interface
+
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+  // axi interface
+
+  up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc b/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
new file mode 100644
index 000000000..794a7cae0
--- /dev/null
+++ b/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
@@ -0,0 +1,30 @@
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
+set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
+
+set_false_path  -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg*   && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg*   && IS_SEQUENTIAL}]
+set_false_path  -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg*  && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg*   && IS_SEQUENTIAL}]
+set_false_path  -from [get_cells -hier -filter {name =~ *up_xfer_data*       && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *d_data_cntrl*          && IS_SEQUENTIAL}]
+
+set_false_path  -from [get_cells -hier -filter {name =~ *d_data_cntrl*       && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *downsampler_counter_*          && IS_SEQUENTIAL}]
+set_false_path  -from [get_cells -hier -filter {name =~ *d_data_cntrl*       && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *data_r_reg*          && IS_SEQUENTIAL}]
+set_false_path  -from [get_cells -hier -filter {name =~ *d_data_cntrl*       && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *dac_read_reg*          && IS_SEQUENTIAL}]
+
+set_false_path  -from [get_cells -hier -filter {name =~ *d_xfer_data*        && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *up_data_status*        && IS_SEQUENTIAL}]
+set_false_path  -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg  && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg*    && IS_SEQUENTIAL}]
+set_false_path  -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg*  && IS_SEQUENTIAL}] \
+                -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg*   && IS_SEQUENTIAL}]
+
+set_false_path  -to [get_cells -hier -filter {name =~ *trigger_m1_reg*     && IS_SEQUENTIAL}]
+
+set_false_path  -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg*     && IS_SEQUENTIAL}]
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl b/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
new file mode 100644
index 000000000..5732ab21d
--- /dev/null
+++ b/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
@@ -0,0 +1,25 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create axi_logic_analyzer
+adi_ip_files axi_logic_analyzer [list \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_xfer_status.v" \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "axi_logic_analyzer_constr.xdc" \
+  "axi_logic_analyzer_reg.v" \
+  "axi_logic_analyzer_trigger.v" \
+  "axi_logic_analyzer.v" ]
+
+adi_ip_properties axi_logic_analyzer
+adi_ip_constraints axi_logic_analyzer [list \
+  "axi_logic_analyzer_constr.xdc" ]
+
+ipx::remove_bus_interface {clk} [ipx::current_core]
+ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_reg.v b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v
new file mode 100644
index 000000000..3de67b7ea
--- /dev/null
+++ b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v
@@ -0,0 +1,264 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_logic_analyzer_reg (
+
+  input               clk,
+  output              reset,
+
+  output      [31:0]  divider_counter_la,
+  output      [31:0]  divider_counter_pg,
+  output      [15:0]  io_selection,
+
+  output      [17:0]  edge_detect_enable,
+  output      [17:0]  rise_edge_enable,
+  output      [17:0]  fall_edge_enable,
+  output      [17:0]  low_level_enable,
+  output      [17:0]  high_level_enable,
+  output      [31:0]  trigger_delay,
+  output              trigger_logic,
+  output              clock_select,
+  output      [15:0]  overwrite_enable,
+  output      [15:0]  overwrite_data,
+  input       [15:0]  input_data,
+  output      [15:0]  od_pp_n,
+
+ // bus interface
+
+  input               up_rstn,
+  input               up_clk,
+  input               up_wreq,
+  input       [13:0]  up_waddr,
+  input       [31:0]  up_wdata,
+  output reg          up_wack,
+  input               up_rreq,
+  input       [13:0]  up_raddr,
+  output reg  [31:0]  up_rdata,
+  output reg          up_rack);
+
+  // internal signals
+
+  wire            up_wreq_s;
+  wire            up_rreq_s;
+
+  // internal registers
+
+  reg     [31:0]  up_version = 32'h00010000;
+  reg     [31:0]  up_scratch = 0;
+  reg     [31:0]  up_divider_counter_la = 0;
+  reg     [31:0]  up_divider_counter_pg = 0;
+  reg     [15:0]  up_io_selection = 16'h0;
+
+  reg     [17:0]  up_edge_detect_enable = 0;
+  reg     [17:0]  up_rise_edge_enable = 0;
+  reg     [17:0]  up_fall_edge_enable = 0;
+  reg     [17:0]  up_low_level_enable = 0;
+  reg     [17:0]  up_high_level_enable = 0;
+  reg     [31:0]  up_trigger_delay = 0;
+  reg             up_trigger_logic = 0;
+  reg             up_clock_select = 0;
+  reg     [15:0]  up_overwrite_enable = 0;
+  reg     [15:0]  up_overwrite_data = 0;
+  reg     [15:0]  up_od_pp_n = 0;
+
+  wire    [15:0]  up_input_data;
+
+  assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
+  assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_wack <= 'd0;
+      up_scratch <= 'd0;
+      up_divider_counter_la <= 'd0;
+      up_divider_counter_pg <= 'd0;
+      up_edge_detect_enable <= 'd0;
+      up_rise_edge_enable <= 'd0;
+      up_fall_edge_enable <= 'd0;
+      up_low_level_enable <= 'd0;
+      up_high_level_enable <= 'd0;
+      up_trigger_delay <= 'd0;
+      up_trigger_logic <= 'd0;
+      up_clock_select <= 'd0;
+      up_overwrite_enable <= 'd0;
+      up_overwrite_data <= 'd0;
+      up_io_selection <= 16'h0;
+      up_od_pp_n <= 16'h0;
+    end else begin
+      up_wack <= up_wreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
+        up_scratch <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
+        up_divider_counter_la <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
+        up_divider_counter_pg <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
+        up_io_selection <= up_wdata[15:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
+        up_edge_detect_enable <= up_wdata[17:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
+        up_rise_edge_enable <= up_wdata[17:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
+        up_fall_edge_enable <= up_wdata[17:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
+        up_low_level_enable <= up_wdata[17:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
+        up_high_level_enable <= up_wdata[17:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
+        up_trigger_delay <= up_wdata;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
+        up_trigger_logic <= up_wdata[0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
+        up_clock_select <= up_wdata[0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
+        up_overwrite_enable <= up_wdata[15:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'he)) begin
+        up_overwrite_data <= up_wdata[15:0];
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
+        up_od_pp_n <= up_wdata[15:0];
+      end
+    end
+  end
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_rack <= up_rreq_s;
+      if (up_rreq_s == 1'b1) begin
+        case (up_raddr[4:0])
+          5'h0: up_rdata <= up_version;
+          5'h1: up_rdata <= up_scratch;
+          5'h2: up_rdata <= up_divider_counter_la;
+          5'h3: up_rdata <= up_divider_counter_pg;
+          5'h4: up_rdata <= {16'h0,up_io_selection};
+          5'h5: up_rdata <= {14'h0,up_edge_detect_enable};
+          5'h6: up_rdata <= {14'h0,up_rise_edge_enable};
+          5'h7: up_rdata <= {14'h0,up_fall_edge_enable};
+          5'h8: up_rdata <= {14'h0,up_low_level_enable};
+          5'h9: up_rdata <= {14'h0,up_high_level_enable};
+          5'ha: up_rdata <= up_trigger_delay;
+          5'hb: up_rdata <= {31'h0,up_trigger_logic};
+          5'hc: up_rdata <= {31'h0,up_clock_select};
+          5'hd: up_rdata <= {16'h0,up_overwrite_enable};
+          5'he: up_rdata <= {16'h0,up_overwrite_data};
+          5'hf: up_rdata <= {16'h0,up_input_data};
+          5'h10: up_rdata <= {16'h0,up_od_pp_n};
+          default: up_rdata <= 0;
+        endcase
+      end else begin
+        up_rdata <= 32'd0;
+      end
+    end
+  end
+
+  ad_rst i_core_rst_reg (.preset(!up_rstn), .clk(clk), .rst(reset));
+
+   up_xfer_cntrl #(.DATA_WIDTH(252)) i_xfer_cntrl (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_data_cntrl ({ up_od_pp_n,               // 16
+                      up_overwrite_data,        // 16
+                      up_overwrite_enable,      // 16
+                      up_clock_select,          // 1
+                      up_trigger_logic,         // 1
+                      up_trigger_delay,         // 32
+                      up_high_level_enable,     // 18
+                      up_low_level_enable,      // 18
+                      up_fall_edge_enable,      // 18
+                      up_rise_edge_enable,      // 18
+                      up_edge_detect_enable,    // 18
+                      up_io_selection,          // 16
+                      up_divider_counter_pg,    // 32
+                      up_divider_counter_la}),  // 32
+
+    .up_xfer_done (),
+    .d_rst (1'b0),
+    .d_clk (clk),
+    .d_data_cntrl ({  od_pp_n,                // 16
+                      overwrite_data,         // 16
+                      overwrite_enable,       // 16
+                      clock_select,           // 1
+                      trigger_logic,          // 1
+                      trigger_delay,          // 32
+                      high_level_enable,      // 18
+                      low_level_enable,       // 18
+                      fall_edge_enable,       // 18
+                      rise_edge_enable,       // 18
+                      edge_detect_enable,     // 18
+                      io_selection,           // 16
+                      divider_counter_pg,     // 32
+                      divider_counter_la}));  // 32
+
+ up_xfer_status #(.DATA_WIDTH(16)) i_xfer_status (
+
+  // up interface
+
+  .up_rstn(up_rstn),
+  .up_clk(up_clk),
+  .up_data_status(up_input_data),
+
+  // device interface
+
+  .d_rst(1'd0),
+  .d_clk(clk),
+  .d_data_status(input_data));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
+
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
new file mode 100644
index 000000000..b634a1f45
--- /dev/null
+++ b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
@@ -0,0 +1,114 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_logic_analyzer_trigger (
+
+  input                 clk,
+  input                 reset,
+
+  input       [15:0]    data,
+  input       [ 1:0]    trigger,
+
+  input       [17:0]    edge_detect_enable,
+  input       [17:0]    rise_edge_enable,
+  input       [17:0]    fall_edge_enable,
+  input       [17:0]    low_level_enable,
+  input       [17:0]    high_level_enable,
+
+  input                 trigger_logic,
+
+  output                trigger_out);
+
+  reg     [ 17:0]   data_m1 = 'd0;
+  reg     [ 17:0]   low_level = 'd0;
+  reg     [ 17:0]   high_level = 'd0;
+  reg     [ 17:0]   edge_detect = 'd0;
+  reg     [ 17:0]   rise_edge = 'd0;
+  reg     [ 17:0]   fall_edge = 'd0;
+  reg     [ 31:0]   delay_count = 'd0;
+
+  reg              trigger_active;
+
+  assign trigger_out = trigger_active;
+
+  // trigger logic:
+  // 0 OR
+  // 1 AND
+
+  always @(*) begin
+    case (trigger_logic)
+      0: trigger_active = | ((edge_detect & edge_detect_enable) |
+                          (rise_edge & rise_edge_enable) |
+                          (fall_edge & fall_edge_enable) |
+                          (low_level & low_level_enable) |
+                          (high_level & high_level_enable));
+      1: trigger_active = | (((edge_detect & edge_detect_enable) | !(|edge_detect_enable)) &
+                          ((rise_edge & rise_edge_enable) | !(|rise_edge_enable)) &
+                          ((fall_edge & fall_edge_enable) | !(|fall_edge_enable)) &
+                          ((low_level & low_level_enable) | !(|low_level_enable)) &
+                          ((high_level & high_level_enable) | !(|high_level_enable)));
+      default: trigger_active = 1'b1;
+    endcase
+  end
+
+  // internal signals
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      data_m1 <= 'd0;
+      edge_detect <= 'd0;
+      rise_edge <= 'd0;
+      fall_edge <= 'd0;
+      low_level <= 'd0;
+      high_level <= 'd0;
+    end else begin
+      data_m1 <= {trigger, data} ;
+      edge_detect <= data_m1 ^ {trigger, data};
+      rise_edge <= (data_m1 ^ {trigger, data} ) & {trigger, data};
+      fall_edge <= (data_m1 ^ {trigger, data}) & ~{trigger, data};
+      low_level <= ~{trigger, data};
+      high_level <= {trigger, data};
+    end
+  end
+
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From b9c94f63a583812ccc2a96c07c2cfbb8c65f4c48 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:26:05 +0200
Subject: [PATCH 882/972] util_extract: Initial commit

---
 library/util_extract/Makefile            | 46 ++++++++++++
 library/util_extract/util_extract.v      | 94 ++++++++++++++++++++++++
 library/util_extract/util_extract_ip.tcl | 15 ++++
 3 files changed, 155 insertions(+)
 create mode 100644 library/util_extract/Makefile
 create mode 100644 library/util_extract/util_extract.v
 create mode 100644 library/util_extract/util_extract_ip.tcl

diff --git a/library/util_extract/Makefile b/library/util_extract/Makefile
new file mode 100644
index 000000000..bd2db55b0
--- /dev/null
+++ b/library/util_extract/Makefile
@@ -0,0 +1,46 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += util_extract.v
+M_DEPS += util_extract_ip.tcl
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: util_extract.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+util_extract.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) util_extract_ip.tcl  >> util_extract_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/util_extract/util_extract.v b/library/util_extract/util_extract.v
new file mode 100644
index 000000000..155a49558
--- /dev/null
+++ b/library/util_extract/util_extract.v
@@ -0,0 +1,94 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_extract (
+
+  clk,
+
+  data_in,
+  data_in_trigger,
+  data_valid,
+
+  data_out,
+  trigger_out
+
+);
+
+  parameter   CHANNELS = 2;
+
+  parameter  DW = CHANNELS * 16;
+  input             clk;
+  input   [DW-1:0]  data_in;
+  input   [DW-1:0]  data_in_trigger;
+  input             data_valid;
+
+  output  [DW-1:0]  data_out;
+  output            trigger_out;
+
+   // loop variables
+
+  genvar  n;
+
+  reg trigger_out;
+  reg trigger_d1;
+
+  wire [15:0] trigger; // 16 maximum channels
+
+  generate
+  for (n = 0; n < CHANNELS; n = n + 1) begin: g_data_out
+    assign data_out[(n+1)*16-1:n*16] = {data_in[(n*16)+14],data_in[(n*16)+14:n*16]};
+    assign trigger[n] = data_in_trigger[(16*n)+15];
+  end
+  for (n = CHANNELS; n < 16; n = n + 1) begin: g_trigger_out
+    assign trigger[n] = 1'b0;
+  end
+  endgenerate
+
+  // compensate delay in the FIFO
+  always @(posedge clk) begin
+    if (data_valid == 1'b1) begin
+      trigger_d1  <= |trigger;
+      trigger_out <= trigger_d1;
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/util_extract/util_extract_ip.tcl b/library/util_extract/util_extract_ip.tcl
new file mode 100644
index 000000000..a6396741e
--- /dev/null
+++ b/library/util_extract/util_extract_ip.tcl
@@ -0,0 +1,15 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create util_extract
+adi_ip_files util_extract [list \
+  "util_extract.v" ]
+
+adi_ip_properties_lite util_extract
+
+ipx::remove_all_bus_interface [ipx::current_core]
+ipx::save_core [ipx::current_core]
+
+

From 7387df9d13c5b214b94d64c67bdac8156d8541c9 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:26:45 +0200
Subject: [PATCH 883/972] util_var_fifo: Initial commit

---
 library/util_var_fifo/Makefile             |  47 ++++++++
 library/util_var_fifo/util_var_fifo.v      | 134 +++++++++++++++++++++
 library/util_var_fifo/util_var_fifo_ip.tcl |  16 +++
 3 files changed, 197 insertions(+)
 create mode 100644 library/util_var_fifo/Makefile
 create mode 100644 library/util_var_fifo/util_var_fifo.v
 create mode 100644 library/util_var_fifo/util_var_fifo_ip.tcl

diff --git a/library/util_var_fifo/Makefile b/library/util_var_fifo/Makefile
new file mode 100644
index 000000000..6b9b6b0c8
--- /dev/null
+++ b/library/util_var_fifo/Makefile
@@ -0,0 +1,47 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += ../common/ad_mem.v
+M_DEPS += ../scripts/adi_env.tcl
+M_DEPS += ../scripts/adi_ip.tcl
+M_DEPS += util_var_fifo.v
+M_DEPS += util_var_fifo_ip.tcl
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += component.xml
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.ip_user_files
+M_FLIST += *.srcs
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+
+
+
+.PHONY: all clean clean-all
+all: util_var_fifo.xpr
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+util_var_fifo.xpr: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) util_var_fifo_ip.tcl  >> util_var_fifo_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/library/util_var_fifo/util_var_fifo.v b/library/util_var_fifo/util_var_fifo.v
new file mode 100644
index 000000000..cc6ad2dd9
--- /dev/null
+++ b/library/util_var_fifo/util_var_fifo.v
@@ -0,0 +1,134 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_var_fifo (
+
+  clk,
+  rst,
+
+  depth,
+
+  data_in,
+  data_in_valid,
+
+  data_out,
+  data_out_valid
+
+);
+
+  parameter       DATA_WIDTH = 32;
+  parameter       ADDRESS_WIDTH =  13;
+
+  localparam      MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1;
+
+  input             clk;
+  input             rst;
+
+  input   [31:0]    depth;
+
+  input   [DATA_WIDTH -1:0]    data_in;
+  input             data_in_valid;
+
+  output  [DATA_WIDTH-1:0]    data_out;
+  output            data_out_valid;
+
+  // internal registers
+
+  reg     [ADDRESS_WIDTH-1:0]    addra = 'd0;
+  reg     [ADDRESS_WIDTH-1:0]    addrb = 'd0;
+
+  reg     [31:0]    depth_d1 = 'd0;
+  reg     [31:0]    data_in_d1 = 'd0;
+  reg     [31:0]    data_in_d2 = 'd0;
+  reg               data_active = 'd0;
+
+  // internal signals
+
+  wire                    reset;
+  wire  [31:0]            depth;
+  wire  [DATA_WIDTH-1:0]  data_out_s;
+  wire                    data_out_valid_s;
+
+  assign reset = ((rst == 1'b1) || (depth != depth_d1)) ? 1 : 0;
+
+  assign data_out = (depth == 0) ? data_in_d2 : data_out_s;
+  assign data_out_valid_s = data_active & data_in_valid;
+  assign data_out_valid = (depth == 0) ? data_in_valid : data_out_valid_s;
+
+  always @(posedge clk) begin
+    depth_d1 <= depth;
+    data_in_d1 <= data_in;
+    data_in_d2 <= data_in_d1;
+  end
+
+  always @(posedge clk) begin
+    if(reset == 1'b1) begin
+      addra <= 0;
+      addrb <= 0;
+      data_active <= 1'b0;
+    end else begin
+      if (data_in_valid == 1'b1) begin
+        addra <= addra + 1;
+        if (data_active == 1'b1) begin
+          addrb <= addrb + 1;
+        end
+      end
+      if (addra >= depth || addra > MAX_DEPTH - 2) begin
+        data_active <= 1'b1;
+      end
+    end
+  end
+
+  ad_mem #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDRESS_WIDTH(ADDRESS_WIDTH)
+  ) data_fifo (
+    .clka(clk),
+    .wea(data_in_valid),
+    .addra(addra),
+    .dina(data_in),
+
+    .clkb(clk),
+    .addrb(addrb),
+    .doutb(data_out_s));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/util_var_fifo/util_var_fifo_ip.tcl b/library/util_var_fifo/util_var_fifo_ip.tcl
new file mode 100644
index 000000000..e9981a442
--- /dev/null
+++ b/library/util_var_fifo/util_var_fifo_ip.tcl
@@ -0,0 +1,16 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create util_var_fifo
+adi_ip_files util_var_fifo [list \
+  "$ad_hdl_dir/library/common/ad_mem.v" \
+  "util_var_fifo.v" ]
+
+adi_ip_properties_lite util_var_fifo
+
+ipx::remove_all_bus_interface [ipx::current_core]
+ipx::save_core [ipx::current_core]
+
+

From b14d740f8769293813ab8b3f0416ab4b28c9e639 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:43:40 +0200
Subject: [PATCH 884/972] M2K: initial commit

---
 projects/Makefile                          |   3 +
 projects/m2k/Makefile                      |  24 ++
 projects/m2k/common/m2k_bd.tcl             | 225 +++++++++++++++++
 projects/m2k/common/m2k_spi.v              |  92 +++++++
 projects/m2k/standalone/Makefile           |  86 +++++++
 projects/m2k/standalone/system_bd.tcl      | 142 +++++++++++
 projects/m2k/standalone/system_constr.xdc  |  66 +++++
 projects/m2k/standalone/system_project.tcl |  16 ++
 projects/m2k/standalone/system_top.v       | 199 +++++++++++++++
 projects/m2k/zed/Makefile                  | 100 ++++++++
 projects/m2k/zed/system_bd.tcl             |   4 +
 projects/m2k/zed/system_constr.xdc         |  85 +++++++
 projects/m2k/zed/system_project.tcl        |  17 ++
 projects/m2k/zed/system_top.v              | 276 +++++++++++++++++++++
 14 files changed, 1335 insertions(+)
 create mode 100644 projects/m2k/Makefile
 create mode 100644 projects/m2k/common/m2k_bd.tcl
 create mode 100644 projects/m2k/common/m2k_spi.v
 create mode 100644 projects/m2k/standalone/Makefile
 create mode 100644 projects/m2k/standalone/system_bd.tcl
 create mode 100644 projects/m2k/standalone/system_constr.xdc
 create mode 100644 projects/m2k/standalone/system_project.tcl
 create mode 100644 projects/m2k/standalone/system_top.v
 create mode 100644 projects/m2k/zed/Makefile
 create mode 100644 projects/m2k/zed/system_bd.tcl
 create mode 100644 projects/m2k/zed/system_constr.xdc
 create mode 100644 projects/m2k/zed/system_project.tcl
 create mode 100644 projects/m2k/zed/system_top.v

diff --git a/projects/Makefile b/projects/Makefile
index 5b6e63562..db53c0806 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -34,6 +34,7 @@ all:
 	-make -C fmcomms5 all
 	-make -C fmcomms7 all
 	-make -C imageon all
+	-make -C m2k all
 	-make -C motcon2_fmc all
 	-make -C pluto all
 	-make -C pzsdr1 all
@@ -71,6 +72,7 @@ clean:
 	make -C fmcomms5 clean
 	make -C fmcomms7 clean
 	make -C imageon clean
+	make -C m2k clean
 	make -C motcon2_fmc clean
 	make -C pluto clean
 	make -C pzsdr1 clean
@@ -108,6 +110,7 @@ clean-all:
 	make -C fmcomms5 clean-all
 	make -C fmcomms7 clean-all
 	make -C imageon clean-all
+	make -C m2k clean-all
 	make -C motcon2_fmc clean-all
 	make -C pluto clean-all
 	make -C pzsdr1 clean-all
diff --git a/projects/m2k/Makefile b/projects/m2k/Makefile
new file mode 100644
index 000000000..882e9f2ee
--- /dev/null
+++ b/projects/m2k/Makefile
@@ -0,0 +1,24 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+.PHONY: all clean clean-all 
+all:
+	-make -C standalone all
+	-make -C zed all
+
+
+clean: 
+	make -C standalone clean
+	make -C zed clean
+
+
+clean-all:
+	make -C standalone clean-all
+	make -C zed clean-all
+
+####################################################################################
+####################################################################################
diff --git a/projects/m2k/common/m2k_bd.tcl b/projects/m2k/common/m2k_bd.tcl
new file mode 100644
index 000000000..236d579c9
--- /dev/null
+++ b/projects/m2k/common/m2k_bd.tcl
@@ -0,0 +1,225 @@
+
+create_bd_port -dir I -from 15 -to 0  data_i
+create_bd_port -dir I -from  1 -to 0  trigger_i
+
+create_bd_port -dir O -from 15 -to 0 data_o
+create_bd_port -dir O -from 15 -to 0 data_t
+create_bd_port -dir O -from  1 -to 0 trigger_o
+create_bd_port -dir O -from  1 -to 0 trigger_t
+
+create_bd_port -dir I rx_clk
+create_bd_port -dir I rxiq
+create_bd_port -dir I -from 11 -to 0 rxd
+create_bd_port -dir O tx_clk
+create_bd_port -dir O txiq
+create_bd_port -dir O -from 11 -to 0 txd
+
+set clk_generator [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 clk_generator]
+set_property -dict [list CONFIG.VCO_DIV {1}] $clk_generator
+set_property -dict [list CONFIG.VCO_MUL {8}] $clk_generator
+set_property -dict [list CONFIG.CLK0_DIV {10}] $clk_generator
+set_property -dict [list CONFIG.CLK1_DIV {5}] $clk_generator
+set_property -dict [list CONFIG.CLK0_PHASE {180}] $clk_generator
+set_property -dict [list CONFIG.CLK1_PHASE {180}] $clk_generator
+set_property -dict [list CONFIG.CLKIN_PERIOD {10}] $clk_generator
+set_property -dict [list CONFIG.CLKIN2_PERIOD {12.5}] $clk_generator
+
+set logic_analyzer [create_bd_cell -type ip -vlnv analog.com:user:axi_logic_analyzer:1.0 logic_analyzer]
+
+set la_trigger_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_var_fifo:1.0 la_trigger_fifo]
+set_property -dict [list CONFIG.DATA_WIDTH {16} ] $la_trigger_fifo
+set_property -dict [list CONFIG.ADDRESS_WIDTH {13} ] $la_trigger_fifo
+
+set logic_analyzer_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 logic_analyzer_dmac]
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16} ] $logic_analyzer_dmac
+set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1} ] $logic_analyzer_dmac
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {true} ] $logic_analyzer_dmac
+
+set pattern_generator_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 pattern_generator_dmac]
+set_property -dict [list CONFIG.DMA_TYPE_DEST {2} ] $pattern_generator_dmac
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $pattern_generator_dmac
+set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {32}] $pattern_generator_dmac
+set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $pattern_generator_dmac
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16} ] $pattern_generator_dmac
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $pattern_generator_dmac
+set_property -dict [list CONFIG.CYCLIC {true}] $pattern_generator_dmac
+
+set axi_ad9963 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9963:1.0 axi_ad9963]
+
+set adc_trigger_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_var_fifo:1.0 adc_trigger_fifo]
+set_property -dict [list CONFIG.DATA_WIDTH {32} ] $adc_trigger_fifo
+set_property -dict [list CONFIG.ADDRESS_WIDTH {13} ] $adc_trigger_fifo
+
+set adc_trigger_extract [create_bd_cell -type ip -vlnv analog.com:user:util_extract:1.0 adc_trigger_extract]
+
+set util_cpack_ad9963 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9963]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9963
+set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_cpack_ad9963
+
+set ad9963_adc_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_adc_dmac]
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_adc_dmac
+set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1}] $ad9963_adc_dmac
+set_property -dict [list CONFIG.SYNC_TRANSFER_START {true}]  $ad9963_adc_dmac
+
+set ad9963_dac_dmac_a [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_dac_dmac_a]
+set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $ad9963_dac_dmac_a
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $ad9963_dac_dmac_a
+set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $ad9963_dac_dmac_a
+set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {64}] $ad9963_dac_dmac_a
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16}] $ad9963_dac_dmac_a
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_dac_dmac_a
+set_property -dict [list CONFIG.CYCLIC {true}] $ad9963_dac_dmac_a
+
+set ad9963_dac_dmac_b [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_dac_dmac_b]
+set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $ad9963_dac_dmac_b
+set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $ad9963_dac_dmac_b
+set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $ad9963_dac_dmac_b
+set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {64}] $ad9963_dac_dmac_b
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16}] $ad9963_dac_dmac_b
+set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_dac_dmac_a
+set_property -dict [list CONFIG.CYCLIC {true}] $ad9963_dac_dmac_b
+
+set adc_trigger [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_trigger:1.0 adc_trigger]
+
+set axi_adc_decimate [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_decimate:1.0 axi_adc_decimate]
+set axi_dac_interpolate [create_bd_cell -type ip -vlnv analog.com:user:axi_dac_interpolate:1.0 axi_dac_interpolate]
+
+ad_connect data_i     logic_analyzer/data_i
+ad_connect trigger_i  logic_analyzer/trigger_i
+ad_connect data_o     logic_analyzer/data_o
+ad_connect data_t     logic_analyzer/data_t
+
+ad_connect sys_cpu_clk            clk_generator/clk
+#ad_connect logic_analyzer/clk_out clk_generator/clk2
+
+ad_connect logic_analyzer/clk     clk_generator/clk_0
+
+ad_connect pattern_generator_dmac/fifo_rd_clk clk_generator/clk_0
+
+ad_connect clk_generator/clk_0  la_trigger_fifo/clk
+ad_connect logic_analyzer_dmac/fifo_wr_clk clk_generator/clk_0
+
+ad_connect la_trigger_fifo/data_in        logic_analyzer/adc_data
+ad_connect la_trigger_fifo/data_in_valid  logic_analyzer/adc_valid
+
+ad_connect logic_analyzer_dmac/fifo_wr_din la_trigger_fifo/data_out
+ad_connect logic_analyzer_dmac/fifo_wr_en  la_trigger_fifo/data_out_valid
+
+ad_connect logic_analyzer/trigger_offset la_trigger_fifo/depth
+
+ad_connect logic_analyzer/trigger_out logic_analyzer_dmac/fifo_wr_sync
+
+ad_connect pattern_generator_dmac/fifo_rd_en      logic_analyzer/dac_read
+ad_connect pattern_generator_dmac/fifo_rd_dout    logic_analyzer/dac_data
+ad_connect pattern_generator_dmac/fifo_rd_valid   logic_analyzer/dac_valid
+
+
+ad_connect sys_cpu_clk logic_analyzer/s_axi_aclk
+ad_connect sys_cpu_resetn logic_analyzer/s_axi_aresetn
+
+ad_connect sys_200m_clk             axi_ad9963/delay_clk
+
+ad_connect axi_ad9963/l_clk  adc_trigger_fifo/clk
+ad_connect axi_ad9963/l_clk  util_cpack_ad9963/adc_clk
+ad_connect axi_adc_decimate/adc_clk axi_ad9963/l_clk
+ad_connect adc_trigger_extract/clk         axi_ad9963/l_clk
+ad_connect ad9963_adc_dmac/fifo_wr_clk     axi_ad9963/l_clk
+
+ad_connect axi_ad9963/rst    util_cpack_ad9963/adc_rst
+ad_connect axi_ad9963/rst    adc_trigger_fifo/rst
+
+ad_connect axi_adc_decimate/adc_data_a axi_ad9963/adc_data_i
+ad_connect axi_adc_decimate/adc_data_b axi_ad9963/adc_data_q
+ad_connect axi_adc_decimate/adc_valid_a axi_ad9963/adc_valid_i
+ad_connect axi_adc_decimate/adc_valid_b axi_ad9963/adc_valid_q
+
+ad_connect axi_ad9963/adc_enable_i        util_cpack_ad9963/adc_enable_0
+ad_connect adc_trigger/data_valid_a_trig  util_cpack_ad9963/adc_valid_0
+ad_connect adc_trigger/data_a_trig        util_cpack_ad9963/adc_data_0
+ad_connect axi_ad9963/adc_enable_q        util_cpack_ad9963/adc_enable_1
+ad_connect adc_trigger/data_valid_b_trig  util_cpack_ad9963/adc_valid_1
+ad_connect adc_trigger/data_b_trig        util_cpack_ad9963/adc_data_1
+
+ad_connect adc_trigger_fifo/data_in        util_cpack_ad9963/adc_data
+ad_connect adc_trigger_fifo/data_in_valid  util_cpack_ad9963/adc_valid
+ad_connect adc_trigger_fifo/depth          adc_trigger/trigger_offset
+
+ad_connect adc_trigger_fifo/data_out       adc_trigger_extract/data_in
+ad_connect adc_trigger_fifo/data_out_valid adc_trigger_extract/data_valid
+ad_connect util_cpack_ad9963/adc_data      adc_trigger_extract/data_in_trigger
+
+ad_connect adc_trigger_extract/data_out     ad9963_adc_dmac/fifo_wr_din
+ad_connect adc_trigger_extract/trigger_out  ad9963_adc_dmac/fifo_wr_sync
+ad_connect adc_trigger_fifo/data_out_valid  ad9963_adc_dmac/fifo_wr_en
+
+ad_connect axi_dac_interpolate/dac_clk      axi_ad9963/dac_clk
+
+ad_connect axi_dac_interpolate/dac_valid_a      axi_ad9963/dac_valid_i
+ad_connect axi_dac_interpolate/dac_valid_b      axi_ad9963/dac_valid_q
+ad_connect axi_dac_interpolate/dac_int_data_a   axi_ad9963/dac_data_i
+ad_connect axi_dac_interpolate/dac_int_data_b   axi_ad9963/dac_data_q
+
+ad_connect ad9963_dac_dmac_a/fifo_rd_clk axi_ad9963/dac_clk
+ad_connect ad9963_dac_dmac_b/fifo_rd_clk axi_ad9963/dac_clk
+
+ad_connect axi_dac_interpolate/dac_data_a         ad9963_dac_dmac_a/fifo_rd_dout
+ad_connect axi_dac_interpolate/dac_int_valid_a    ad9963_dac_dmac_a/fifo_rd_en
+ad_connect axi_dac_interpolate/dac_data_b         ad9963_dac_dmac_b/fifo_rd_dout
+ad_connect axi_dac_interpolate/dac_int_valid_b    ad9963_dac_dmac_b/fifo_rd_en
+
+ad_connect /axi_ad9963/tx_data    txd
+ad_connect /axi_ad9963/tx_iq      txiq
+ad_connect /axi_ad9963/tx_clk     tx_clk
+ad_connect /axi_ad9963/trx_data   rxd
+ad_connect /axi_ad9963/trx_clk    rx_clk
+ad_connect /axi_ad9963/trx_iq     rxiq
+
+ad_connect adc_trigger/data_a axi_adc_decimate/adc_dec_data_a
+ad_connect adc_trigger/data_valid_a axi_adc_decimate/adc_dec_valid_a
+ad_connect adc_trigger/data_b axi_adc_decimate/adc_dec_data_b
+ad_connect adc_trigger/data_valid_b axi_adc_decimate/adc_dec_valid_b
+
+ad_connect adc_trigger/clk axi_ad9963/l_clk
+ad_connect trigger_i adc_trigger/trigger_i
+ad_connect trigger_o adc_trigger/trigger_o
+ad_connect trigger_t adc_trigger/trigger_t
+
+ad_connect axi_ad9963/dac_sync_in axi_ad9963/dac_sync_out
+ad_connect axi_ad9963/adc_dovf    ad9963_adc_dmac/fifo_wr_overflow
+ad_connect axi_ad9963/dac_dunf    ad9963_dac_dmac_a/fifo_rd_underflow
+
+# interconnects
+
+ad_cpu_interconnect 0x70000000 clk_generator
+ad_cpu_interconnect 0x70100000 logic_analyzer
+ad_cpu_interconnect 0x70200000 axi_ad9963
+ad_cpu_interconnect 0x7C400000 logic_analyzer_dmac
+ad_cpu_interconnect 0x7C420000 pattern_generator_dmac
+ad_cpu_interconnect 0x7C440000 ad9963_adc_dmac
+ad_cpu_interconnect 0x7C460000 ad9963_dac_dmac_b
+ad_cpu_interconnect 0x7C480000 ad9963_dac_dmac_a
+ad_cpu_interconnect 0x7C4c0000 adc_trigger
+ad_cpu_interconnect 0x7C500000 axi_adc_decimate
+ad_cpu_interconnect 0x7C5a0000 axi_dac_interpolate
+
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk logic_analyzer_dmac/m_dest_axi
+ad_mem_hp1_interconnect sys_cpu_clk pattern_generator_dmac/m_src_axi
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk ad9963_adc_dmac/m_dest_axi
+ad_mem_hp2_interconnect sys_cpu_clk ad9963_dac_dmac_a/m_src_axi
+ad_mem_hp2_interconnect sys_cpu_clk ad9963_dac_dmac_b/m_src_axi
+ad_connect  sys_cpu_resetn logic_analyzer_dmac/m_dest_axi_aresetn
+ad_connect  sys_cpu_resetn pattern_generator_dmac/m_src_axi_aresetn
+ad_connect  sys_cpu_resetn ad9963_adc_dmac/m_dest_axi_aresetn
+ad_connect  sys_cpu_resetn ad9963_dac_dmac_a/m_src_axi_aresetn
+ad_connect  sys_cpu_resetn ad9963_dac_dmac_b/m_src_axi_aresetn
+
+# interrupts
+
+ad_cpu_interrupt ps-13 mb-12 logic_analyzer_dmac/irq
+ad_cpu_interrupt ps-12 mb-13 pattern_generator_dmac/irq
+ad_cpu_interrupt ps-10 mb-14 ad9963_adc_dmac/irq
+ad_cpu_interrupt ps-9 mb-15 ad9963_dac_dmac_a/irq
+ad_cpu_interrupt ps-8 mb-16 ad9963_dac_dmac_b/irq
+
diff --git a/projects/m2k/common/m2k_spi.v b/projects/m2k/common/m2k_spi.v
new file mode 100644
index 000000000..d7bcc9280
--- /dev/null
+++ b/projects/m2k/common/m2k_spi.v
@@ -0,0 +1,92 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module m2k_spi (
+
+  // 4-wire
+
+  input           ad9963_csn,
+  input           adf4360_cs,
+  input           spi_clk,
+  input           spi_mosi,
+  output          spi_miso,
+
+  // 3-wire
+
+  inout           spi_sdio);
+
+  // internal registers
+
+  reg     [ 5:0]  spi_count = 'd0;
+  reg             spi_rd_wr_n = 'd0;
+  reg             spi_enable = 'd0;
+
+  // check on rising edge and change on falling edge
+
+  always @(posedge spi_clk or posedge ad9963_csn) begin
+    if (ad9963_csn == 1'b1) begin
+      spi_count <= 6'd0;
+      spi_rd_wr_n <= 1'd0;
+    end else begin
+      spi_count <= spi_count + 1'b1;
+      if (spi_count == 6'd0) begin
+        spi_rd_wr_n <= spi_mosi;
+      end
+    end
+  end
+
+  always @(negedge spi_clk or posedge ad9963_csn) begin
+    if (ad9963_csn == 1'b1) begin
+      spi_enable <= 1'b0;
+    end else begin
+      if ((spi_count == 6'd16) && (ad9963_csn == 1'b0)) begin
+        spi_enable <= spi_rd_wr_n;
+      end
+    end
+  end
+
+  // io buffers
+
+  assign spi_miso = spi_sdio;
+  assign spi_sdio = (spi_enable == 1'b1) ? 1'bz : spi_mosi;
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/m2k/standalone/Makefile b/projects/m2k/standalone/Makefile
new file mode 100644
index 000000000..3caeff064
--- /dev/null
+++ b/projects/m2k/standalone/Makefile
@@ -0,0 +1,86 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/m2k_spi.v
+M_DEPS += ../common/m2k_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9963/axi_ad9963.xpr
+M_DEPS += ../../../library/axi_adc_decimate/axi_adc_decimate.xpr
+M_DEPS += ../../../library/axi_adc_trigger/axi_adc_trigger.xpr
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dac_interpolate/axi_dac_interpolate.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_logic_analyzer/axi_logic_analyzer.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_extract/util_extract.xpr
+M_DEPS += ../../../library/util_var_fifo/util_var_fifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib m2k.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9963 clean
+	make -C ../../../library/axi_adc_decimate clean
+	make -C ../../../library/axi_adc_trigger clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dac_interpolate clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_logic_analyzer clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_extract clean
+	make -C ../../../library/util_var_fifo clean
+
+
+m2k.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> m2k_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9963
+	make -C ../../../library/axi_adc_decimate
+	make -C ../../../library/axi_adc_trigger
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dac_interpolate
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_logic_analyzer
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_extract
+	make -C ../../../library/util_var_fifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/m2k/standalone/system_bd.tcl b/projects/m2k/standalone/system_bd.tcl
new file mode 100644
index 000000000..7dbeff4e3
--- /dev/null
+++ b/projects/m2k/standalone/system_bd.tcl
@@ -0,0 +1,142 @@
+
+# create board design
+# default ports
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
+create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
+
+create_bd_port -dir O spi0_csn_2_o
+create_bd_port -dir O spi0_csn_1_o
+create_bd_port -dir O spi0_csn_0_o
+create_bd_port -dir I spi0_csn_i
+create_bd_port -dir I spi0_clk_i
+create_bd_port -dir O spi0_clk_o
+create_bd_port -dir I spi0_sdo_i
+create_bd_port -dir O spi0_sdo_o
+create_bd_port -dir I spi0_sdi_i
+
+create_bd_port -dir I -from 63 -to 0 gpio_i
+create_bd_port -dir O -from 63 -to 0 gpio_o
+create_bd_port -dir O -from 63 -to 0 gpio_t
+
+# interrupts
+
+create_bd_port -dir I -type intr ps_intr_00
+create_bd_port -dir I -type intr ps_intr_01
+create_bd_port -dir I -type intr ps_intr_02
+create_bd_port -dir I -type intr ps_intr_03
+create_bd_port -dir I -type intr ps_intr_04
+create_bd_port -dir I -type intr ps_intr_05
+create_bd_port -dir I -type intr ps_intr_06
+create_bd_port -dir I -type intr ps_intr_07
+create_bd_port -dir I -type intr ps_intr_08
+create_bd_port -dir I -type intr ps_intr_09
+create_bd_port -dir I -type intr ps_intr_10
+create_bd_port -dir I -type intr ps_intr_11
+create_bd_port -dir I -type intr ps_intr_12
+create_bd_port -dir I -type intr ps_intr_13
+create_bd_port -dir I -type intr ps_intr_15
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 3.3V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+
+# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
+
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
+set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+
+set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+
+# system reset/clock definitions
+
+ad_connect  sys_cpu_clk sys_ps7/FCLK_CLK0
+ad_connect  sys_200m_clk sys_ps7/FCLK_CLK1
+ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
+ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
+ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
+ad_connect  sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
+
+# interface connections
+
+ad_connect  ddr sys_ps7/DDR
+ad_connect  gpio_i sys_ps7/GPIO_I
+ad_connect  gpio_o sys_ps7/GPIO_O
+ad_connect  gpio_t sys_ps7/GPIO_T
+ad_connect  fixed_io sys_ps7/FIXED_IO
+ad_connect  iic_main axi_iic_main/iic
+
+# spi connections
+
+ad_connect  spi0_csn_2_o sys_ps7/SPI0_SS2_O
+ad_connect  spi0_csn_1_o sys_ps7/SPI0_SS1_O
+ad_connect  spi0_csn_0_o sys_ps7/SPI0_SS_O
+ad_connect  spi0_csn_i sys_ps7/SPI0_SS_I
+ad_connect  spi0_clk_i sys_ps7/SPI0_SCLK_I
+ad_connect  spi0_clk_o sys_ps7/SPI0_SCLK_O
+ad_connect  spi0_sdo_i sys_ps7/SPI0_MOSI_I
+ad_connect  spi0_sdo_o sys_ps7/SPI0_MOSI_O
+ad_connect  spi0_sdi_i sys_ps7/SPI0_MISO_I
+
+# interrupts
+
+ad_connect  sys_concat_intc/dout sys_ps7/IRQ_F2P
+ad_connect  sys_concat_intc/In15 ps_intr_15
+ad_connect  sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
+ad_connect  sys_concat_intc/In13 ps_intr_13
+ad_connect  sys_concat_intc/In12 ps_intr_12
+ad_connect  sys_concat_intc/In11 ps_intr_11
+ad_connect  sys_concat_intc/In10 ps_intr_10
+ad_connect  sys_concat_intc/In9 ps_intr_09
+ad_connect  sys_concat_intc/In8 ps_intr_08
+ad_connect  sys_concat_intc/In7 ps_intr_07
+ad_connect  sys_concat_intc/In6 ps_intr_06
+ad_connect  sys_concat_intc/In5 ps_intr_05
+ad_connect  sys_concat_intc/In4 ps_intr_04
+ad_connect  sys_concat_intc/In3 ps_intr_03
+ad_connect  sys_concat_intc/In2 ps_intr_02
+ad_connect  sys_concat_intc/In1 ps_intr_01
+ad_connect  sys_concat_intc/In0 ps_intr_00
+
+# interconnects
+
+ad_cpu_interconnect 0x41600000 axi_iic_main
+
+source ../common/m2k_bd.tcl
+
+set_property -dict [list CONFIG.DAC_DATAPATH_DISABLE {1}] $axi_ad9963
+set_property -dict [list CONFIG.ADC_DATAPATH_DISABLE {1}] $axi_ad9963
diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc
new file mode 100644
index 000000000..f0d01adc1
--- /dev/null
+++ b/projects/m2k/standalone/system_constr.xdc
@@ -0,0 +1,66 @@
+
+set_property  -dict {PACKAGE_PIN  F14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  F13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports iic_sda]
+
+set_property  -dict {PACKAGE_PIN  E12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports ad9963_resetn]
+
+set_property  -dict {PACKAGE_PIN  G15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports adf4360_cs]
+set_property  -dict {PACKAGE_PIN  E11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports ad9963_csn]
+set_property  -dict {PACKAGE_PIN  E13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports spi_clk]
+set_property  -dict {PACKAGE_PIN  F12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports spi_sdio]
+
+set_property  -dict {PACKAGE_PIN  F15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports en_power_analog]
+
+set_property  -dict {PACKAGE_PIN  M12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports trigger_bd[0]]
+set_property  -dict {PACKAGE_PIN  N12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports trigger_bd[1]]
+
+set_property  -dict {PACKAGE_PIN  K11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[0]]
+set_property  -dict {PACKAGE_PIN  K12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[1]]
+set_property  -dict {PACKAGE_PIN  K13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[2]]
+set_property  -dict {PACKAGE_PIN  L13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[3]]
+set_property  -dict {PACKAGE_PIN  L14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[4]]
+set_property  -dict {PACKAGE_PIN  M14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[5]]
+set_property  -dict {PACKAGE_PIN  L15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[6]]
+set_property  -dict {PACKAGE_PIN  M15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[7]]
+set_property  -dict {PACKAGE_PIN  N13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[8]]
+set_property  -dict {PACKAGE_PIN  P14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[9]]
+set_property  -dict {PACKAGE_PIN  R12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[10]]
+set_property  -dict {PACKAGE_PIN  R13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[11]]
+set_property  -dict {PACKAGE_PIN  P11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[12]]
+set_property  -dict {PACKAGE_PIN  R11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[13]]
+set_property  -dict {PACKAGE_PIN  P15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[14]]
+set_property  -dict {PACKAGE_PIN  R15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[15]]
+
+set_property  -dict {PACKAGE_PIN  N11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rx_clk]
+set_property  -dict {PACKAGE_PIN  P13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxiq]
+set_property  -dict {PACKAGE_PIN  P10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[0]]
+set_property  -dict {PACKAGE_PIN  R10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[1]]
+set_property  -dict {PACKAGE_PIN  P8  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[2]]
+set_property  -dict {PACKAGE_PIN  P9  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[3]]
+set_property  -dict {PACKAGE_PIN  N7  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[4]]
+set_property  -dict {PACKAGE_PIN  N8  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[5]]
+set_property  -dict {PACKAGE_PIN  M10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[6]]
+set_property  -dict {PACKAGE_PIN  M11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[7]]
+set_property  -dict {PACKAGE_PIN  R7  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[8]]
+set_property  -dict {PACKAGE_PIN  R8  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[9]]
+set_property  -dict {PACKAGE_PIN  M9  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[10]]
+set_property  -dict {PACKAGE_PIN  N9  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[11]]
+
+set_property  -dict {PACKAGE_PIN  L12 IOSTANDARD LVCMOS33} [get_ports tx_clk]
+set_property  -dict {PACKAGE_PIN  N14 IOSTANDARD LVCMOS33} [get_ports txiq]
+set_property  -dict {PACKAGE_PIN  H12 IOSTANDARD LVCMOS33} [get_ports txd[0]]
+set_property  -dict {PACKAGE_PIN  G11 IOSTANDARD LVCMOS33} [get_ports txd[1]]
+set_property  -dict {PACKAGE_PIN  H13 IOSTANDARD LVCMOS33} [get_ports txd[2]]
+set_property  -dict {PACKAGE_PIN  G12 IOSTANDARD LVCMOS33} [get_ports txd[3]]
+set_property  -dict {PACKAGE_PIN  H14 IOSTANDARD LVCMOS33} [get_ports txd[4]]
+set_property  -dict {PACKAGE_PIN  G14 IOSTANDARD LVCMOS33} [get_ports txd[5]]
+set_property  -dict {PACKAGE_PIN  K15 IOSTANDARD LVCMOS33} [get_ports txd[6]]
+set_property  -dict {PACKAGE_PIN  J15 IOSTANDARD LVCMOS33} [get_ports txd[7]]
+set_property  -dict {PACKAGE_PIN  J14 IOSTANDARD LVCMOS33} [get_ports txd[8]]
+set_property  -dict {PACKAGE_PIN  J13 IOSTANDARD LVCMOS33} [get_ports txd[9]]
+set_property  -dict {PACKAGE_PIN  J11 IOSTANDARD LVCMOS33} [get_ports txd[10]]
+set_property  -dict {PACKAGE_PIN  H11 IOSTANDARD LVCMOS33} [get_ports txd[11]]
+
+create_clock -period 10.000 -name rx_clk [get_ports rx_clk]
+create_clock -period 12.500 -name trigger_clk [get_ports {trigger_bd[0]}]
+create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}]
diff --git a/projects/m2k/standalone/system_project.tcl b/projects/m2k/standalone/system_project.tcl
new file mode 100644
index 000000000..38d329e96
--- /dev/null
+++ b/projects/m2k/standalone/system_project.tcl
@@ -0,0 +1,16 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+set p_device "xc7z010clg225-1"
+adi_project_create m2k
+
+adi_project_files m2k [list \
+  "../common/m2k_spi.v" \
+  "system_top.v" \
+  "system_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
+
+adi_project_run m2k
+
diff --git a/projects/m2k/standalone/system_top.v b/projects/m2k/standalone/system_top.v
new file mode 100644
index 000000000..97153f6df
--- /dev/null
+++ b/projects/m2k/standalone/system_top.v
@@ -0,0 +1,199 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 1:0]  ddr_dm,
+  inout   [15:0]  ddr_dq,
+  inout   [ 1:0]  ddr_dqs_n,
+  inout   [ 1:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [31:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout   [15:0]  data_bd,
+  inout   [ 1:0]  trigger_bd,
+
+  input           rx_clk,
+  input           rxiq,
+  input   [11:0]  rxd,
+  output          tx_clk,
+  output          txiq,
+  output  [11:0]  txd,
+
+  output          ad9963_resetn,
+  output          ad9963_csn,
+  output          adf4360_cs,
+  output          spi_clk,
+  inout           spi_sdio,
+
+  output          en_power_analog,
+
+  inout           iic_scl,
+  inout           iic_sda);
+
+  // internal signals
+
+  wire    [63:0]  gpio_o;
+
+  wire    [15:0]  data_i;
+  wire    [15:0]  data_o;
+  wire    [15:0]  data_t;
+
+  wire    [ 1:0]  trigger_i;
+  wire    [ 1:0]  trigger_o;
+  wire    [ 1:0]  trigger_t;
+
+  wire    [ 1:0]  spi0_csn;
+  wire            spi0_clk;
+  wire            spi0_mosi;
+  wire            spi0_miso;
+
+  assign ad9963_resetn = gpio_o[32];
+  assign en_power_analog = gpio_o[33];
+
+  assign ad9963_csn = spi0_csn[0];
+  assign adf4360_cs = spi0_csn[1];
+  assign spi_clk = spi0_clk;
+  assign spi_mosi = spi0_mosi;
+  assign spi0_miso = spi_miso;
+
+  // instantiations
+
+  ad_iobuf #(
+    .DATA_WIDTH(16)
+  ) i_data_bd (
+    .dio_t(data_t[15:0]),
+    .dio_i(data_o[15:0]),
+    .dio_o(data_i[15:0]),
+    .dio_p(data_bd));
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_trigger_bd (
+    .dio_t(trigger_t[1:0]),
+    .dio_i(trigger_o[1:0]),
+    .dio_o(trigger_i[1:0]),
+    .dio_p(trigger_bd));
+
+  m2k_spi i_m2k_spi (
+    .ad9963_csn (ad9963_csn),
+    .adf4360_cs (adf4360_cs),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_sdio (spi_sdio));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (64'h0),
+    .gpio_o (gpio_o),
+    .gpio_t (),
+    .iic_main_scl_io (iic_scl),
+    .iic_main_sda_io (iic_sda),
+    .data_i(data_i),
+    .data_o(data_o),
+    .data_t(data_t),
+    .trigger_i(trigger_i),
+    .trigger_o(trigger_o),
+    .trigger_t(trigger_t),
+    .rx_clk(rx_clk),
+    .rxiq(rxiq),
+    .rxd(rxd),
+    .tx_clk(tx_clk),
+    .txiq(txiq),
+    .txd(txd),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .ps_intr_11 (1'b0),
+    .ps_intr_15 (1'b0),
+    .spi0_clk_i (spi0_clk),
+    .spi0_clk_o (spi0_clk),
+    .spi0_csn_0_o (spi0_csn[0]),
+    .spi0_csn_1_o (spi0_csn[1]),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi0_miso),
+    .spi0_sdo_i (spi0_mosi),
+    .spi0_sdo_o (spi0_mosi));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/projects/m2k/zed/Makefile b/projects/m2k/zed/Makefile
new file mode 100644
index 000000000..e249888ad
--- /dev/null
+++ b/projects/m2k/zed/Makefile
@@ -0,0 +1,100 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.xdc
+M_DEPS += system_bd.tcl
+M_DEPS += ../common/m2k_spi.v
+M_DEPS += ../common/m2k_bd.tcl
+M_DEPS += ../../scripts/adi_project.tcl
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_board.tcl
+M_DEPS += ../../common/zed/zed_system_constr.xdc
+M_DEPS += ../../common/zed/zed_system_bd.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9963/axi_ad9963.xpr
+M_DEPS += ../../../library/axi_adc_decimate/axi_adc_decimate.xpr
+M_DEPS += ../../../library/axi_adc_trigger/axi_adc_trigger.xpr
+M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
+M_DEPS += ../../../library/axi_dac_interpolate/axi_dac_interpolate.xpr
+M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
+M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
+M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
+M_DEPS += ../../../library/axi_logic_analyzer/axi_logic_analyzer.xpr
+M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
+M_DEPS += ../../../library/util_cpack/util_cpack.xpr
+M_DEPS += ../../../library/util_extract/util_extract.xpr
+M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
+M_DEPS += ../../../library/util_var_fifo/util_var_fifo.xpr
+
+M_VIVADO := vivado -mode batch -source
+
+M_FLIST := *.cache
+M_FLIST += *.data
+M_FLIST += *.xpr
+M_FLIST += *.log
+M_FLIST += *.jou
+M_FLIST +=  xgui
+M_FLIST += *.runs
+M_FLIST += *.srcs
+M_FLIST += *.sdk
+M_FLIST += *.hw
+M_FLIST += *.sim
+M_FLIST += .Xil
+M_FLIST += *.ip_user_files
+
+
+
+.PHONY: all lib clean clean-all
+all: lib m2k_fmc_zed.sdk/system_top.hdf
+
+
+clean: 
+	rm -rf $(M_FLIST)
+
+
+clean-all:clean
+	make -C ../../../library/axi_ad9963 clean
+	make -C ../../../library/axi_adc_decimate clean
+	make -C ../../../library/axi_adc_trigger clean
+	make -C ../../../library/axi_clkgen clean
+	make -C ../../../library/axi_dac_interpolate clean
+	make -C ../../../library/axi_dmac clean
+	make -C ../../../library/axi_hdmi_tx clean
+	make -C ../../../library/axi_i2s_adi clean
+	make -C ../../../library/axi_logic_analyzer clean
+	make -C ../../../library/axi_spdif_tx clean
+	make -C ../../../library/util_cpack clean
+	make -C ../../../library/util_extract clean
+	make -C ../../../library/util_i2c_mixer clean
+	make -C ../../../library/util_var_fifo clean
+
+
+m2k_fmc_zed.sdk/system_top.hdf: $(M_DEPS)
+	-rm -rf $(M_FLIST)
+	$(M_VIVADO) system_project.tcl >> m2k_fmc_zed_vivado.log 2>&1
+
+
+lib:
+	make -C ../../../library/axi_ad9963
+	make -C ../../../library/axi_adc_decimate
+	make -C ../../../library/axi_adc_trigger
+	make -C ../../../library/axi_clkgen
+	make -C ../../../library/axi_dac_interpolate
+	make -C ../../../library/axi_dmac
+	make -C ../../../library/axi_hdmi_tx
+	make -C ../../../library/axi_i2s_adi
+	make -C ../../../library/axi_logic_analyzer
+	make -C ../../../library/axi_spdif_tx
+	make -C ../../../library/util_cpack
+	make -C ../../../library/util_extract
+	make -C ../../../library/util_i2c_mixer
+	make -C ../../../library/util_var_fifo
+
+####################################################################################
+####################################################################################
diff --git a/projects/m2k/zed/system_bd.tcl b/projects/m2k/zed/system_bd.tcl
new file mode 100644
index 000000000..dc673a39d
--- /dev/null
+++ b/projects/m2k/zed/system_bd.tcl
@@ -0,0 +1,4 @@
+
+source ../../common/zed/zed_system_bd.tcl
+source ../common/m2k_bd.tcl
+
diff --git a/projects/m2k/zed/system_constr.xdc b/projects/m2k/zed/system_constr.xdc
new file mode 100644
index 000000000..5266b1090
--- /dev/null
+++ b/projects/m2k/zed/system_constr.xdc
@@ -0,0 +1,85 @@
+set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD LVCMOS33} [get_ports otg_vbusoc]
+
+set_property  -dict {PACKAGE_PIN  P16   IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]]       ; ## BTNC
+set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]]       ; ## BTND
+set_property  -dict {PACKAGE_PIN  N15   IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]]       ; ## BTNL
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]]       ; ## BTNR
+set_property  -dict {PACKAGE_PIN  T18   IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]]       ; ## BTNU
+
+set_property  -dict {PACKAGE_PIN  F22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[11]]      ; ## SW0
+set_property  -dict {PACKAGE_PIN  G22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[12]]      ; ## SW1
+set_property  -dict {PACKAGE_PIN  H22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[13]]      ; ## SW2
+set_property  -dict {PACKAGE_PIN  F21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[14]]      ; ## SW3
+set_property  -dict {PACKAGE_PIN  H19   IOSTANDARD LVCMOS33} [get_ports gpio_bd[15]]      ; ## SW4
+set_property  -dict {PACKAGE_PIN  H18   IOSTANDARD LVCMOS33} [get_ports gpio_bd[16]]      ; ## SW5
+set_property  -dict {PACKAGE_PIN  H17   IOSTANDARD LVCMOS33} [get_ports gpio_bd[17]]      ; ## SW6
+set_property  -dict {PACKAGE_PIN  M15   IOSTANDARD LVCMOS33} [get_ports gpio_bd[18]]      ; ## SW7
+
+set_property  -dict {PACKAGE_PIN  H15   IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]]      ; ## XADC-GIO0
+set_property  -dict {PACKAGE_PIN  R15   IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]]      ; ## XADC-GIO1
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]]      ; ## XADC-GIO2
+set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]]      ; ## XADC-GIO3
+
+set_property  -dict {PACKAGE_PIN  G17   IOSTANDARD LVCMOS33} [get_ports gpio_bd[31]]      ; ## OTG-RESETN
+
+set_property  -dict {PACKAGE_PIN  A16   IOSTANDARD LVCMOS33} [get_ports en_power_analog]        ; ## A16  FMC_LPC_LA28_P
+set_property  -dict {PACKAGE_PIN  B16   IOSTANDARD LVCMOS33} [get_ports ad9963_resetn]           ; ## G33  FMC_LPC_LA31_P
+
+set_property  -dict {PACKAGE_PIN  B21  IOSTANDARD LVCMOS33} [get_ports adf4360_cs]               ; ## G36  FMC_LPC_LA33_P
+set_property  -dict {PACKAGE_PIN  B17  IOSTANDARD LVCMOS33} [get_ports ad9963_csn]               ; ## G34  FMC_LPC_LA31_N
+set_property  -dict {PACKAGE_PIN  C17  IOSTANDARD LVCMOS33} [get_ports spi_clk]                  ; ## G30  FMC_LPC_LA29_P
+set_property  -dict {PACKAGE_PIN  C18  IOSTANDARD LVCMOS33} [get_ports spi_sdio]                 ; ## G31  FMC_LPC_LA29_N
+
+set_property  -dict {PACKAGE_PIN  D20  IOSTANDARD LVCMOS33 } [get_ports trigger_bd[0]]            ; ## C22  FMC_LPC_LA18_CC_P
+set_property  -dict {PACKAGE_PIN  C20  IOSTANDARD LVCMOS33 } [get_ports trigger_bd[1]]            ; ## C23  FMC_LPC_LA18_CC_N
+
+set_property  -dict {PACKAGE_PIN  B19  IOSTANDARD LVCMOS33 } [get_ports data_bd[0]]               ; ## D20  FMC_LPC_LA17_CC_P
+set_property  -dict {PACKAGE_PIN  B20  IOSTANDARD LVCMOS33 } [get_ports data_bd[1]]               ; ## D21  FMC_LPC_LA17_CC_N
+set_property  -dict {PACKAGE_PIN  D22  IOSTANDARD LVCMOS33 } [get_ports data_bd[2]]               ; ## D17  FMC_LPC_LA13_P
+set_property  -dict {PACKAGE_PIN  C22  IOSTANDARD LVCMOS33 } [get_ports data_bd[3]]               ; ## D18  FMC_LPC_LA13_N
+set_property  -dict {PACKAGE_PIN  E15  IOSTANDARD LVCMOS33 } [get_ports data_bd[4]]               ; ## D23  FMC_LPC_LA23_P
+set_property  -dict {PACKAGE_PIN  D15  IOSTANDARD LVCMOS33 } [get_ports data_bd[5]]               ; ## D24  FMC_LPC_LA23_N
+set_property  -dict {PACKAGE_PIN  F18  IOSTANDARD LVCMOS33 } [get_ports data_bd[6]]               ; ## D26  FMC_LPC_LA26_P
+set_property  -dict {PACKAGE_PIN  E18  IOSTANDARD LVCMOS33 } [get_ports data_bd[7]]               ; ## D27  FMC_LPC_LA26_N
+set_property  -dict {PACKAGE_PIN  G20  IOSTANDARD LVCMOS33 } [get_ports data_bd[8]]               ; ## C10  FMC_LPC_LA06_P
+set_property  -dict {PACKAGE_PIN  G21  IOSTANDARD LVCMOS33 } [get_ports data_bd[9]]               ; ## C11  FMC_LPC_LA06_N
+set_property  -dict {PACKAGE_PIN  G19  IOSTANDARD LVCMOS33 } [get_ports data_bd[10]]              ; ## C14  FMC_LPC_LA10_P
+set_property  -dict {PACKAGE_PIN  F19  IOSTANDARD LVCMOS33 } [get_ports data_bd[11]]              ; ## C15  FMC_LPC_LA10_N
+set_property  -dict {PACKAGE_PIN  G15  IOSTANDARD LVCMOS33 } [get_ports data_bd[12]]              ; ## C18  FMC_LPC_LA14_P
+set_property  -dict {PACKAGE_PIN  G16  IOSTANDARD LVCMOS33 } [get_ports data_bd[13]]              ; ## C19  FMC_LPC_LA14_N
+set_property  -dict {PACKAGE_PIN  E21  IOSTANDARD LVCMOS33 } [get_ports data_bd[14]]              ; ## C26  FMC_LPC_LA27_P
+set_property  -dict {PACKAGE_PIN  D21  IOSTANDARD LVCMOS33 } [get_ports data_bd[15]]              ; ## C27  FMC_LPC_LA27_P
+
+set_property  -dict {PACKAGE_PIN  M19  IOSTANDARD LVCMOS33} [get_ports rx_clk]                   ; ## G07  FMC_LPC_LA01_CC_P
+set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS33} [get_ports rxiq]                     ; ## G27  FMC_LPC_LA25_P
+set_property  -dict {PACKAGE_PIN  P17  IOSTANDARD LVCMOS33} [get_ports rxd[0]]                   ; ## H07  FMC_LPC_LA02_P
+set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS33} [get_ports rxd[1]]                   ; ## H08  FMC_LPC_LA02_N
+set_property  -dict {PACKAGE_PIN  M21  IOSTANDARD LVCMOS33} [get_ports rxd[2]]                   ; ## H10  FMC_LPC_LA04_P
+set_property  -dict {PACKAGE_PIN  M22  IOSTANDARD LVCMOS33} [get_ports rxd[3]]                   ; ## H11  FMC_LPC_LA04_N
+set_property  -dict {PACKAGE_PIN  T16  IOSTANDARD LVCMOS33} [get_ports rxd[4]]                   ; ## H13  FMC_LPC_LA07_P
+set_property  -dict {PACKAGE_PIN  T17  IOSTANDARD LVCMOS33} [get_ports rxd[5]]                   ; ## H14  FMC_LPC_LA07_N
+set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS33} [get_ports rxd[6]]                   ; ## H16  FMC_LPC_LA11_P
+set_property  -dict {PACKAGE_PIN  N18  IOSTANDARD LVCMOS33} [get_ports rxd[7]]                   ; ## H17  FMC_LPC_LA11_N
+set_property  -dict {PACKAGE_PIN  J16  IOSTANDARD LVCMOS33} [get_ports rxd[8]]                   ; ## H19  FMC_LPC_LA15_P
+set_property  -dict {PACKAGE_PIN  J17  IOSTANDARD LVCMOS33} [get_ports rxd[9]]                   ; ## H20  FMC_LPC_LA15_N
+set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS33} [get_ports rxd[10]]                  ; ## H22  FMC_LPC_LA19_P
+set_property  -dict {PACKAGE_PIN  K20  IOSTANDARD LVCMOS33} [get_ports rxd[11]]                  ; ## H23  FMC_LPC_LA19_N
+
+set_property  -dict {PACKAGE_PIN  N19  IOSTANDARD LVCMOS33} [get_ports tx_clk]                   ; ## G06  FMC_LPC_LA00_CC_P
+set_property  -dict {PACKAGE_PIN  M17  IOSTANDARD LVCMOS33} [get_ports txiq]                     ; ## G28  FMC_LPC_LA25_N
+set_property  -dict {PACKAGE_PIN  N22  IOSTANDARD LVCMOS33} [get_ports txd[0]]                   ; ## G09  FMC_LPC_LA03_P
+set_property  -dict {PACKAGE_PIN  P22  IOSTANDARD LVCMOS33} [get_ports txd[1]]                   ; ## G10  FMC_LPC_LA03_N
+set_property  -dict {PACKAGE_PIN  J21  IOSTANDARD LVCMOS33} [get_ports txd[2]]                   ; ## G12  FMC_LPC_LA08_P
+set_property  -dict {PACKAGE_PIN  J22  IOSTANDARD LVCMOS33} [get_ports txd[3]]                   ; ## G13  FMC_LPC_LA08_N
+set_property  -dict {PACKAGE_PIN  P20  IOSTANDARD LVCMOS33} [get_ports txd[4]]                   ; ## G15  FMC_LPC_LA12_P
+set_property  -dict {PACKAGE_PIN  P21  IOSTANDARD LVCMOS33} [get_ports txd[5]]                   ; ## G16  FMC_LPC_LA12_N
+set_property  -dict {PACKAGE_PIN  J20  IOSTANDARD LVCMOS33} [get_ports txd[6]]                   ; ## G18  FMC_LPC_LA16_P
+set_property  -dict {PACKAGE_PIN  K21  IOSTANDARD LVCMOS33} [get_ports txd[7]]                   ; ## G19  FMC_LPC_LA16_N
+set_property  -dict {PACKAGE_PIN  L21  IOSTANDARD LVCMOS33} [get_ports txd[8]]                   ; ## G21  FMC_LPC_LA20_P
+set_property  -dict {PACKAGE_PIN  L22  IOSTANDARD LVCMOS33} [get_ports txd[9]]                   ; ## G22  FMC_LPC_LA20_N
+set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS33} [get_ports txd[10]]                  ; ## G24  FMC_LPC_LA22_P
+set_property  -dict {PACKAGE_PIN  T19  IOSTANDARD LVCMOS33} [get_ports txd[11]]                  ; ## G25  FMC_LPC_LA22_N
+
+create_clock -name rx_clk       -period   10.00 [get_ports rx_clk]
+create_clock -name trigger_clk  -period   12.5  [get_ports trigger_bd[0]]
+create_clock -name data_clk     -period   12.5  [get_ports data_bd[0]]
diff --git a/projects/m2k/zed/system_project.tcl b/projects/m2k/zed/system_project.tcl
new file mode 100644
index 000000000..698017bb5
--- /dev/null
+++ b/projects/m2k/zed/system_project.tcl
@@ -0,0 +1,17 @@
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project_create m2k_fmc_zed
+adi_project_files m2k_fmc_zed [list \
+  "../common/m2k_spi.v" \
+  "system_top.v" \
+  "system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
+
+set_property PROCESSING_ORDER EARLY [get_files "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
+
+adi_project_run m2k_fmc_zed
+
diff --git a/projects/m2k/zed/system_top.v b/projects/m2k/zed/system_top.v
new file mode 100644
index 000000000..c3ac220f0
--- /dev/null
+++ b/projects/m2k/zed/system_top.v
@@ -0,0 +1,276 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout   [31:0]  gpio_bd,
+
+  output          hdmi_out_clk,
+  output          hdmi_vsync,
+  output          hdmi_hsync,
+  output          hdmi_data_e,
+  output  [15:0]  hdmi_data,
+
+  output          i2s_mclk,
+  output          i2s_bclk,
+  output          i2s_lrclk,
+  output          i2s_sdata_out,
+  input           i2s_sdata_in,
+
+  output          spdif,
+
+  inout   [ 1:0]  iic_mux_scl,
+  inout   [ 1:0]  iic_mux_sda,
+
+  input           otg_vbusoc,
+
+  inout   [15:0]  data_bd,
+  inout   [ 1:0]  trigger_bd,
+
+  input           rx_clk,
+  input           rxiq,
+  input   [11:0]  rxd,
+  output          tx_clk,
+  output          txiq,
+  output  [11:0]  txd,
+
+  output          ad9963_resetn,
+  output          ad9963_csn,
+  output          adf4360_cs,
+  output          spi_clk,
+  inout           spi_sdio,
+
+  output          en_power_analog,
+
+  inout           iic_scl,
+  inout           iic_sda);
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire    [ 1:0]  iic_mux_scl_i_s;
+  wire    [ 1:0]  iic_mux_scl_o_s;
+  wire            iic_mux_scl_t_s;
+  wire    [ 1:0]  iic_mux_sda_i_s;
+  wire    [ 1:0]  iic_mux_sda_o_s;
+  wire            iic_mux_sda_t_s;
+
+  wire    [15:0]  data_i;
+  wire    [15:0]  data_o;
+  wire    [15:0]  data_t;
+
+  wire    [ 1:0]  trigger_i;
+  wire    [ 1:0]  trigger_o;
+  wire    [ 1:0]  trigger_t;
+
+  wire    [ 1:0]  spi0_csn;
+  wire            spi0_clk;
+  wire            spi0_mosi;
+  wire            spi0_miso;
+
+  assign ad9963_resetn = gpio_o[32];
+  assign en_power_analog = gpio_o[33];
+
+  assign ad9963_csn = spi0_csn[0];
+  assign adf4360_cs = spi0_csn[1];
+  assign spi_clk = spi0_clk;
+  assign spi_mosi = spi0_mosi;
+  assign spi0_miso = spi_miso;
+
+  // instantiations
+
+  ad_iobuf #(
+    .DATA_WIDTH(32)
+  ) i_iobuf (
+    .dio_t(gpio_t[31:0]),
+    .dio_i(gpio_o[31:0]),
+    .dio_o(gpio_i[31:0]),
+    .dio_p(gpio_bd));
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_iic_mux_scl (
+    .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
+    .dio_i(iic_mux_scl_o_s),
+    .dio_o(iic_mux_scl_i_s),
+    .dio_p(iic_mux_scl));
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_iic_mux_sda (
+    .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
+    .dio_i(iic_mux_sda_o_s),
+    .dio_o(iic_mux_sda_i_s),
+    .dio_p(iic_mux_sda));
+
+  ad_iobuf #(
+    .DATA_WIDTH(16)
+  ) i_data_bd (
+    .dio_t(data_t[15:0]),
+    .dio_i(data_o[15:0]),
+    .dio_o(data_i[15:0]),
+    .dio_p(data_bd));
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_trigger_bd (
+    .dio_t(trigger_t[1:0]),
+    .dio_i(trigger_o[1:0]),
+    .dio_o(trigger_i[1:0]),
+    .dio_p(trigger_bd));
+
+  m2k_spi i_m2k_spi (
+    .ad9963_csn (ad9963_csn),
+    .adf4360_cs (adf4360_cs),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_sdio (spi_sdio));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .hdmi_data (hdmi_data),
+    .hdmi_data_e (hdmi_data_e),
+    .hdmi_hsync (hdmi_hsync),
+    .hdmi_out_clk (hdmi_out_clk),
+    .hdmi_vsync (hdmi_vsync),
+    .i2s_bclk (i2s_bclk),
+    .i2s_lrclk (i2s_lrclk),
+    .i2s_mclk (i2s_mclk),
+    .i2s_sdata_in (i2s_sdata_in),
+    .i2s_sdata_out (i2s_sdata_out),
+    .iic_fmc_scl_io (iic_scl),
+    .iic_fmc_sda_io (iic_sda),
+    .iic_mux_scl_i (iic_mux_scl_i_s),
+    .iic_mux_scl_o (iic_mux_scl_o_s),
+    .iic_mux_scl_t (iic_mux_scl_t_s),
+    .iic_mux_sda_i (iic_mux_sda_i_s),
+    .iic_mux_sda_o (iic_mux_sda_o_s),
+    .iic_mux_sda_t (iic_mux_sda_t_s),
+    .data_i(data_i),
+    .data_o(data_o),
+    .data_t(data_t),
+    .trigger_i(trigger_i),
+    .trigger_o(trigger_o),
+    .trigger_t(trigger_t),
+    .rx_clk(rx_clk),
+    .rxiq(rxiq),
+    .rxd(rxd),
+    .tx_clk(tx_clk),
+    .txiq(txiq),
+    .txd(txd),
+    .ps_intr_00 (1'b0),
+    .ps_intr_01 (1'b0),
+    .ps_intr_02 (1'b0),
+    .ps_intr_03 (1'b0),
+    .ps_intr_04 (1'b0),
+    .ps_intr_05 (1'b0),
+    .ps_intr_06 (1'b0),
+    .ps_intr_07 (1'b0),
+    .spi0_clk_i (spi0_clk),
+    .spi0_clk_o (spi0_clk),
+    .spi0_csn_0_o (spi0_csn[0]),
+    .spi0_csn_1_o (spi0_csn[1]),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi0_miso),
+    .spi0_sdo_i (spi0_mosi),
+    .spi0_sdo_o (spi0_mosi),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .otg_vbusoc (otg_vbusoc),
+    .spdif (spdif));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************

From 1df6178ab8e764126f50bab49573f53b9330f3dd Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 16:44:32 +0200
Subject: [PATCH 885/972] library: Update common Makefile

---
 library/Makefile | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/library/Makefile b/library/Makefile
index 56c816b4e..74e796dd1 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -30,7 +30,11 @@ clean:
 	make -C axi_ad9680 clean
 	make -C axi_ad9684 clean
 	make -C axi_ad9739a clean
+	make -C axi_ad9963 clean
+	make -C axi_adc_decimate clean
+	make -C axi_adc_trigger clean
 	make -C axi_clkgen clean
+	make -C axi_dac_interpolate clean
 	make -C axi_dmac clean
 	make -C axi_generic_adc clean
 	make -C axi_gpreg clean
@@ -38,6 +42,7 @@ clean:
 	make -C axi_hdmi_tx clean
 	make -C axi_i2s_adi clean
 	make -C axi_intr_monitor clean
+	make -C axi_logic_analyzer clean
 	make -C axi_mc_controller clean
 	make -C axi_mc_current_monitor clean
 	make -C axi_mc_speed clean
@@ -60,6 +65,7 @@ clean:
 	make -C util_clkdiv clean
 	make -C util_cpack clean
 	make -C util_dacfifo clean
+	make -C util_extract clean
 	make -C util_fir_dec clean
 	make -C util_fir_int clean
 	make -C util_gmii_to_rgmii clean
@@ -71,6 +77,7 @@ clean:
 	make -C util_sigma_delta_spi clean
 	make -C util_tdd_sync clean
 	make -C util_upack clean
+	make -C util_var_fifo clean
 	make -C util_wfifo clean
 	make -C xilinx/axi_adcfifo clean
 	make -C xilinx/axi_adxcvr clean
@@ -103,7 +110,11 @@ lib:
 	-make -C axi_ad9680
 	-make -C axi_ad9684
 	-make -C axi_ad9739a
+	-make -C axi_ad9963
+	-make -C axi_adc_decimate
+	-make -C axi_adc_trigger
 	-make -C axi_clkgen
+	-make -C axi_dac_interpolate
 	-make -C axi_dmac
 	-make -C axi_generic_adc
 	-make -C axi_gpreg
@@ -111,6 +122,7 @@ lib:
 	-make -C axi_hdmi_tx
 	-make -C axi_i2s_adi
 	-make -C axi_intr_monitor
+	-make -C axi_logic_analyzer
 	-make -C axi_mc_controller
 	-make -C axi_mc_current_monitor
 	-make -C axi_mc_speed
@@ -133,10 +145,10 @@ lib:
 	-make -C util_clkdiv
 	-make -C util_cpack
 	-make -C util_dacfifo
+	-make -C util_extract
 	-make -C util_fir_dec
 	-make -C util_fir_int
 	-make -C util_gmii_to_rgmii
-	-make -C util_gtlb
 	-make -C util_i2c_mixer
 	-make -C util_mfifo
 	-make -C util_pmod_adc
@@ -145,6 +157,7 @@ lib:
 	-make -C util_sigma_delta_spi
 	-make -C util_tdd_sync
 	-make -C util_upack
+	-make -C util_var_fifo
 	-make -C util_wfifo
 	-make -C xilinx/axi_adcfifo
 	-make -C xilinx/axi_adxcvr

From 6bdd853b884d1d6bf63da694c401db633d6741f9 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 31 Jan 2017 23:08:53 +0200
Subject: [PATCH 886/972] m2k: Updated PS7 configuration

---
 projects/m2k/standalone/system_bd.tcl | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/projects/m2k/standalone/system_bd.tcl b/projects/m2k/standalone/system_bd.tcl
index 7dbeff4e3..fdeab709f 100644
--- a/projects/m2k/standalone/system_bd.tcl
+++ b/projects/m2k/standalone/system_bd.tcl
@@ -41,16 +41,17 @@ create_bd_port -dir I -type intr ps_intr_15
 # instance: sys_ps7
 
 set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
+
 set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}] $sys_ps7
 set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 3.3V}] $sys_ps7
 set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
@@ -58,6 +59,13 @@ set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
 set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7
 
 # DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
 

From cfff70d358ccc53715e3331e5116d79736178cd9 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 1 Feb 2017 14:27:11 +0200
Subject: [PATCH 887/972] M2K: Update standalone project

- configured PS7 similar to pluto. Added specific constraints instead of default PS7
- moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1]
---
 projects/m2k/standalone/system_bd.tcl      |  35 +++---
 projects/m2k/standalone/system_constr.xdc  | 130 +++++++++++++++++++++
 projects/m2k/standalone/system_project.tcl |   1 +
 projects/m2k/standalone/system_top.v       |  18 ++-
 4 files changed, 164 insertions(+), 20 deletions(-)

diff --git a/projects/m2k/standalone/system_bd.tcl b/projects/m2k/standalone/system_bd.tcl
index fdeab709f..ae11b6a2c 100644
--- a/projects/m2k/standalone/system_bd.tcl
+++ b/projects/m2k/standalone/system_bd.tcl
@@ -16,9 +16,9 @@ create_bd_port -dir I spi0_sdo_i
 create_bd_port -dir O spi0_sdo_o
 create_bd_port -dir I spi0_sdi_i
 
-create_bd_port -dir I -from 63 -to 0 gpio_i
-create_bd_port -dir O -from 63 -to 0 gpio_o
-create_bd_port -dir O -from 63 -to 0 gpio_t
+create_bd_port -dir I -from 17 -to 0 gpio_i
+create_bd_port -dir O -from 17 -to 0 gpio_o
+create_bd_port -dir O -from 17 -to 0 gpio_t
 
 # interrupts
 
@@ -42,8 +42,8 @@ create_bd_port -dir I -type intr ps_intr_15
 
 set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
 
-set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}] $sys_ps7
-set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 3.3V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
+set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
 set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7
 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
@@ -52,20 +52,27 @@ set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7
 set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
 
 # DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
 
diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc
index f0d01adc1..09d3fd5a9 100644
--- a/projects/m2k/standalone/system_constr.xdc
+++ b/projects/m2k/standalone/system_constr.xdc
@@ -64,3 +64,133 @@ set_property  -dict {PACKAGE_PIN  H11 IOSTANDARD LVCMOS33} [get_ports txd[11]]
 create_clock -period 10.000 -name rx_clk [get_ports rx_clk]
 create_clock -period 12.500 -name trigger_clk [get_ports {trigger_bd[0]}]
 create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}]
+
+set_input_jitter clk_fpga_0 0.3
+set_input_jitter clk_fpga_1 0.15
+
+set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*]
+set_property SLEW SLOW [get_ports *fixed_io_mio*]
+set_property DRIVE 8 [get_ports *fixed_io_mio*]
+set_property  -dict {PACKAGE_PIN D8   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]]
+set_property  -dict {PACKAGE_PIN A5   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]]
+set_property  -dict {PACKAGE_PIN A8                  } [get_ports fixed_io_mio[ 2]]
+set_property  -dict {PACKAGE_PIN A7                  } [get_ports fixed_io_mio[ 3]]
+set_property  -dict {PACKAGE_PIN C8                  } [get_ports fixed_io_mio[ 4]]
+set_property  -dict {PACKAGE_PIN A9                  } [get_ports fixed_io_mio[ 5]]
+set_property  -dict {PACKAGE_PIN A10                 } [get_ports fixed_io_mio[ 6]]
+set_property  -dict {PACKAGE_PIN D9                  } [get_ports fixed_io_mio[ 7]]
+set_property  -dict {PACKAGE_PIN B6                  } [get_ports fixed_io_mio[ 8]]
+set_property  -dict {PACKAGE_PIN B5   PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]]
+set_property  -dict {PACKAGE_PIN D6   PULLTYPE PULLUP} [get_ports fixed_io_mio[10]]
+set_property  -dict {PACKAGE_PIN B10  PULLTYPE PULLUP} [get_ports fixed_io_mio[11]]
+set_property  -dict {PACKAGE_PIN B7   PULLTYPE PULLUP} [get_ports fixed_io_mio[12]]
+set_property  -dict {PACKAGE_PIN C6   PULLTYPE PULLUP} [get_ports fixed_io_mio[13]]
+set_property  -dict {PACKAGE_PIN B9   PULLTYPE PULLUP} [get_ports fixed_io_mio[14]]
+set_property  -dict {PACKAGE_PIN D10  PULLTYPE PULLUP} [get_ports fixed_io_mio[15]]
+set_property  -dict {PACKAGE_PIN A15  PULLTYPE PULLUP} [get_ports fixed_io_mio[16]]
+set_property  -dict {PACKAGE_PIN D11  PULLTYPE PULLUP} [get_ports fixed_io_mio[17]]
+set_property  -dict {PACKAGE_PIN B15  PULLTYPE PULLUP} [get_ports fixed_io_mio[18]]
+set_property  -dict {PACKAGE_PIN C12  PULLTYPE PULLUP} [get_ports fixed_io_mio[19]]
+set_property  -dict {PACKAGE_PIN E15  PULLTYPE PULLUP} [get_ports fixed_io_mio[20]]
+set_property  -dict {PACKAGE_PIN C11  PULLTYPE PULLUP} [get_ports fixed_io_mio[21]]
+set_property  -dict {PACKAGE_PIN D15  PULLTYPE PULLUP} [get_ports fixed_io_mio[22]]
+set_property  -dict {PACKAGE_PIN A14  PULLTYPE PULLUP} [get_ports fixed_io_mio[23]]
+set_property  -dict {PACKAGE_PIN B14  PULLTYPE PULLUP} [get_ports fixed_io_mio[24]]
+set_property  -dict {PACKAGE_PIN C14  PULLTYPE PULLUP} [get_ports fixed_io_mio[25]]
+set_property  -dict {PACKAGE_PIN A13  PULLTYPE PULLUP} [get_ports fixed_io_mio[26]]
+set_property  -dict {PACKAGE_PIN D14  PULLTYPE PULLUP} [get_ports fixed_io_mio[27]]
+set_property  -dict {PACKAGE_PIN B12  PULLTYPE PULLUP} [get_ports fixed_io_mio[28]]
+set_property  -dict {PACKAGE_PIN D13  PULLTYPE PULLUP} [get_ports fixed_io_mio[29]]
+set_property  -dict {PACKAGE_PIN A12  PULLTYPE PULLUP} [get_ports fixed_io_mio[30]]
+set_property  -dict {PACKAGE_PIN C13  PULLTYPE PULLUP} [get_ports fixed_io_mio[31]]
+
+set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*]
+set_property SLEW SLOW [get_ports *fixed_io_ps*]
+set_property DRIVE 8 [get_ports *fixed_io_ps*]
+set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk]
+set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb]
+
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*]
+set_property SLEW FAST [get_ports *fixed_io_ddr_vr*]
+set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp]
+set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn]
+
+set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*]
+set_property SLEW FAST [get_ports *ddr_ck*]
+set_property PACKAGE_PIN N3 [get_ports ddr_ck_p]
+set_property PACKAGE_PIN N2 [get_ports ddr_ck_n]
+
+set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*]
+set_property SLEW SLOW [get_ports *ddr_addr*]
+set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]]
+set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]]
+set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]]
+set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]]
+set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]]
+set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]]
+set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]]
+set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]]
+set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]]
+set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]]
+set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]]
+set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]]
+set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]]
+set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]]
+set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]]
+
+set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*]
+set_property SLEW SLOW [get_ports *ddr_ba*]
+set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]]
+set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]]
+set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]]
+
+set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n]
+set_property SLEW FAST [get_ports ddr_reset_n]
+set_property PACKAGE_PIN L4 [get_ports ddr_reset_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n]
+set_property SLEW SLOW [get_ports ddr_cs_n]
+set_property PACKAGE_PIN R2 [get_ports ddr_cs_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n]
+set_property SLEW SLOW [get_ports ddr_ras_n]
+set_property PACKAGE_PIN R6 [get_ports ddr_ras_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n]
+set_property SLEW SLOW [get_ports ddr_cas_n]
+set_property PACKAGE_PIN R5 [get_ports ddr_cas_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_we_n]
+set_property SLEW SLOW [get_ports ddr_we_n]
+set_property PACKAGE_PIN R3 [get_ports ddr_we_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr_cke]
+set_property SLEW SLOW [get_ports ddr_cke]
+set_property PACKAGE_PIN L3 [get_ports ddr_cke]
+set_property IOSTANDARD SSTL15 [get_ports ddr_odt]
+set_property SLEW SLOW [get_ports ddr_odt]
+set_property PACKAGE_PIN K3 [get_ports ddr_odt]
+
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]]
+set_property SLEW FAST [get_ports *ddr_dq[*]]
+set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]]
+set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]]
+set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]]
+set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]]
+set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]]
+set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]]
+set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]]
+set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]]
+set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]]
+set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]]
+set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]]
+set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]]
+set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]]
+set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]]
+set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]]
+set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]]
+set_property SLEW FAST [get_ports *ddr_dm[*]]
+set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]]
+set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]]
+set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*]
+set_property SLEW FAST [get_ports *ddr_dqs*]
+set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]]
+set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]]
+set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]]
+set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]]
diff --git a/projects/m2k/standalone/system_project.tcl b/projects/m2k/standalone/system_project.tcl
index 38d329e96..6e349259a 100644
--- a/projects/m2k/standalone/system_project.tcl
+++ b/projects/m2k/standalone/system_project.tcl
@@ -12,5 +12,6 @@ adi_project_files m2k [list \
   "system_constr.xdc" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
 
+set_property is_enabled false [get_files  *system_sys_ps7_0.xdc]
 adi_project_run m2k
 
diff --git a/projects/m2k/standalone/system_top.v b/projects/m2k/standalone/system_top.v
index 97153f6df..166c06e95 100644
--- a/projects/m2k/standalone/system_top.v
+++ b/projects/m2k/standalone/system_top.v
@@ -85,7 +85,9 @@ module system_top (
 
   // internal signals
 
-  wire    [63:0]  gpio_o;
+  wire    [16:0]  gpio_i;
+  wire    [16:0]  gpio_o;
+  wire    [16:0]  gpio_t;
 
   wire    [15:0]  data_i;
   wire    [15:0]  data_o;
@@ -100,9 +102,6 @@ module system_top (
   wire            spi0_mosi;
   wire            spi0_miso;
 
-  assign ad9963_resetn = gpio_o[32];
-  assign en_power_analog = gpio_o[33];
-
   assign ad9963_csn = spi0_csn[0];
   assign adf4360_cs = spi0_csn[1];
   assign spi_clk = spi0_clk;
@@ -111,6 +110,13 @@ module system_top (
 
   // instantiations
 
+  ad_iobuf #(.DATA_WIDTH(2)) i_iobuf (
+    .dio_t (gpio_t[ 1:0]),
+    .dio_i (gpio_o[ 1:0]),
+    .dio_o (gpio_i[ 1:0]),
+    .dio_p ({ en_power_analog,
+              ad9963_resetn}));
+
   ad_iobuf #(
     .DATA_WIDTH(16)
   ) i_data_bd (
@@ -157,9 +163,9 @@ module system_top (
     .fixed_io_ps_clk (fixed_io_ps_clk),
     .fixed_io_ps_porb (fixed_io_ps_porb),
     .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gpio_i (64'h0),
+    .gpio_i (gpio_i),
     .gpio_o (gpio_o),
-    .gpio_t (),
+    .gpio_t (gpio_t),
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .data_i(data_i),

From 5155b3f46d6a176b228dfd0163d514777c4970c2 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 1 Feb 2017 17:43:01 +0200
Subject: [PATCH 888/972] m2k: Fix gpio buswidth

---
 projects/m2k/standalone/system_bd.tcl | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/projects/m2k/standalone/system_bd.tcl b/projects/m2k/standalone/system_bd.tcl
index ae11b6a2c..4d347e002 100644
--- a/projects/m2k/standalone/system_bd.tcl
+++ b/projects/m2k/standalone/system_bd.tcl
@@ -16,9 +16,9 @@ create_bd_port -dir I spi0_sdo_i
 create_bd_port -dir O spi0_sdo_o
 create_bd_port -dir I spi0_sdi_i
 
-create_bd_port -dir I -from 17 -to 0 gpio_i
-create_bd_port -dir O -from 17 -to 0 gpio_o
-create_bd_port -dir O -from 17 -to 0 gpio_t
+create_bd_port -dir I -from 16 -to 0 gpio_i
+create_bd_port -dir O -from 16 -to 0 gpio_o
+create_bd_port -dir O -from 16 -to 0 gpio_t
 
 # interrupts
 

From 1c9d8c4e7cd787eb1e6c12b70b08ffedbb92cdaf Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Feb 2017 13:35:02 -0500
Subject: [PATCH 889/972] axi_adxcvr- add primitive info read

---
 library/xilinx/axi_adxcvr/axi_adxcvr_up.v | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
index a07219791..650b79941 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
@@ -42,6 +42,8 @@ module axi_adxcvr_up #(
   // parameters
 
   parameter   integer ID = 0,
+  parameter   integer NUM_OF_LANES = 8,
+  parameter   integer GTH_OR_GTX_N = 0,
   parameter   integer TX_OR_RX_N = 0,
   parameter   integer QPLL_ENABLE = 1,
   parameter           LPM_OR_DFE_N = 1,
@@ -155,6 +157,10 @@ module axi_adxcvr_up #(
   reg             up_rreq_d = 'd0;
   reg     [31:0]  up_rdata_d = 'd0;
 
+  // internal signals
+
+  wire    [31:0]  up_rparam_s;
+
   // defaults
 
   assign up_wack = up_wreq_d;
@@ -438,6 +444,22 @@ module axi_adxcvr_up #(
   assign up_rack = up_rreq_d;
   assign up_rdata = up_rdata_d;
 
+  // altera specific
+
+  assign up_rparam_s[31:24] = 8'd0;
+
+  // xilinx specific
+ 
+  assign up_rparam_s[23:21] = 3'd0;
+  assign up_rparam_s[20:20] = (QPLL_ENABLE == 0) ? 1'b0 : 1'b1;
+  assign up_rparam_s[19:16] = (GTH_OR_GTX_N == 0) ? 1'b0 : 1'b1;
+
+  // generic
+
+  assign up_rparam_s[15: 9] = 7'd0;
+  assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1;
+  assign up_rparam_s[ 7: 0] = NUM_OF_LANES;
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_rreq_d <= 'd0;
@@ -453,6 +475,7 @@ module axi_adxcvr_up #(
           10'h005: up_rdata_d <= {31'd0, up_status_int};
           10'h006: up_rdata_d <= {17'd0, up_user_ready_cnt, up_rst_cnt, up_pll_rst_cnt};
           10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel};
+          10'h009: up_rdata_d <= up_rparam_s;
           10'h010: up_rdata_d <= {24'd0, up_icm_sel};
           10'h011: up_rdata_d <= {3'd0, up_icm_data};
           10'h012: up_rdata_d <= {15'd0, up_icm_busy, up_icm_rdata};

From 806d19febca33249f2a0faf116c3f3a529dec8ce Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Feb 2017 13:38:29 -0500
Subject: [PATCH 890/972] axi_adxcvr- add primitive info read

---
 library/xilinx/axi_adxcvr/axi_adxcvr.v | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v
index a02787508..98e2b5a92 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v
@@ -1791,6 +1791,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_up #(
     .ID (ID),
+    .NUM_OF_LANES (NUM_OF_LANES),
+    .GTH_OR_GTX_N (GTH_OR_GTX_N),
     .TX_OR_RX_N (TX_OR_RX_N),
     .QPLL_ENABLE (QPLL_ENABLE),
     .LPM_OR_DFE_N (LPM_OR_DFE_N),

From 85ff496c125ccde144f06a61d103877e6a3769fd Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Feb 2017 20:54:56 -0500
Subject: [PATCH 891/972] daq2/a10gx- gpio match with others

---
 projects/daq2/a10gx/system_top.v | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v
index 5b8b15688..790563d09 100644
--- a/projects/daq2/a10gx/system_top.v
+++ b/projects/daq2/a10gx/system_top.v
@@ -211,13 +211,20 @@ module system_top (
 
   // gpio in & out are separate cores
 
+  assign gpio_i[63:44] = gpio_o[63:44];
+  assign gpio_i[43:43] = trig;
+
+  assign gpio_i[42:40] = gpio_o[42:40];
   assign adc_pd = gpio_o[42];
   assign dac_txen = gpio_o[41];
   assign dac_reset = gpio_o[40];
+
+  assign gpio_i[39:39] = gpio_o[39];
+
+  assign gpio_i[38:38] = gpio_o[38];
   assign clkd_sync = gpio_o[38];
 
-  assign gpio_i[63:38] = gpio_o[63:38];
-  assign gpio_i[37:37] = trig;
+  assign gpio_i[37:37] = gpio_o[37];
   assign gpio_i[36:36] = adc_fdb;
   assign gpio_i[35:35] = adc_fda;
   assign gpio_i[34:34] = dac_irq;

From 0d0c3e99fd6535b053302950f46e2807cfee4fd1 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 2 Feb 2017 12:35:46 +0200
Subject: [PATCH 892/972] m2k: Added I2C pull-ul, removed SLEW constraints

---
 projects/m2k/standalone/system_constr.xdc | 80 +++++++++++------------
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc
index 09d3fd5a9..0e09cdf87 100644
--- a/projects/m2k/standalone/system_constr.xdc
+++ b/projects/m2k/standalone/system_constr.xdc
@@ -1,50 +1,50 @@
 
-set_property  -dict {PACKAGE_PIN  F14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports iic_scl]
-set_property  -dict {PACKAGE_PIN  F13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports iic_sda]
+set_property  -dict {PACKAGE_PIN  F14 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  F13 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_sda]
 
-set_property  -dict {PACKAGE_PIN  E12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports ad9963_resetn]
+set_property  -dict {PACKAGE_PIN  E12 IOSTANDARD LVCMOS33 } [get_ports ad9963_resetn]
 
-set_property  -dict {PACKAGE_PIN  G15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports adf4360_cs]
-set_property  -dict {PACKAGE_PIN  E11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports ad9963_csn]
-set_property  -dict {PACKAGE_PIN  E13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports spi_clk]
-set_property  -dict {PACKAGE_PIN  F12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports spi_sdio]
+set_property  -dict {PACKAGE_PIN  G15 IOSTANDARD LVCMOS33} [get_ports adf4360_cs]
+set_property  -dict {PACKAGE_PIN  E11 IOSTANDARD LVCMOS33} [get_ports ad9963_csn]
+set_property  -dict {PACKAGE_PIN  E13 IOSTANDARD LVCMOS33} [get_ports spi_clk]
+set_property  -dict {PACKAGE_PIN  F12 IOSTANDARD LVCMOS33} [get_ports spi_sdio]
 
-set_property  -dict {PACKAGE_PIN  F15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports en_power_analog]
+set_property  -dict {PACKAGE_PIN  F15 IOSTANDARD LVCMOS33} [get_ports en_power_analog]
 
-set_property  -dict {PACKAGE_PIN  M12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports trigger_bd[0]]
-set_property  -dict {PACKAGE_PIN  N12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports trigger_bd[1]]
+set_property  -dict {PACKAGE_PIN  M12 IOSTANDARD LVCMOS33} [get_ports trigger_bd[0]]
+set_property  -dict {PACKAGE_PIN  N12 IOSTANDARD LVCMOS33} [get_ports trigger_bd[1]]
 
-set_property  -dict {PACKAGE_PIN  K11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[0]]
-set_property  -dict {PACKAGE_PIN  K12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[1]]
-set_property  -dict {PACKAGE_PIN  K13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[2]]
-set_property  -dict {PACKAGE_PIN  L13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[3]]
-set_property  -dict {PACKAGE_PIN  L14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[4]]
-set_property  -dict {PACKAGE_PIN  M14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[5]]
-set_property  -dict {PACKAGE_PIN  L15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[6]]
-set_property  -dict {PACKAGE_PIN  M15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[7]]
-set_property  -dict {PACKAGE_PIN  N13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[8]]
-set_property  -dict {PACKAGE_PIN  P14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[9]]
-set_property  -dict {PACKAGE_PIN  R12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[10]]
-set_property  -dict {PACKAGE_PIN  R13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[11]]
-set_property  -dict {PACKAGE_PIN  P11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[12]]
-set_property  -dict {PACKAGE_PIN  R11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[13]]
-set_property  -dict {PACKAGE_PIN  P15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[14]]
-set_property  -dict {PACKAGE_PIN  R15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[15]]
+set_property  -dict {PACKAGE_PIN  K11 IOSTANDARD LVCMOS33} [get_ports data_bd[0]]
+set_property  -dict {PACKAGE_PIN  K12 IOSTANDARD LVCMOS33} [get_ports data_bd[1]]
+set_property  -dict {PACKAGE_PIN  K13 IOSTANDARD LVCMOS33} [get_ports data_bd[2]]
+set_property  -dict {PACKAGE_PIN  L13 IOSTANDARD LVCMOS33} [get_ports data_bd[3]]
+set_property  -dict {PACKAGE_PIN  L14 IOSTANDARD LVCMOS33} [get_ports data_bd[4]]
+set_property  -dict {PACKAGE_PIN  M14 IOSTANDARD LVCMOS33} [get_ports data_bd[5]]
+set_property  -dict {PACKAGE_PIN  L15 IOSTANDARD LVCMOS33} [get_ports data_bd[6]]
+set_property  -dict {PACKAGE_PIN  M15 IOSTANDARD LVCMOS33} [get_ports data_bd[7]]
+set_property  -dict {PACKAGE_PIN  N13 IOSTANDARD LVCMOS33} [get_ports data_bd[8]]
+set_property  -dict {PACKAGE_PIN  P14 IOSTANDARD LVCMOS33} [get_ports data_bd[9]]
+set_property  -dict {PACKAGE_PIN  R12 IOSTANDARD LVCMOS33} [get_ports data_bd[10]]
+set_property  -dict {PACKAGE_PIN  R13 IOSTANDARD LVCMOS33} [get_ports data_bd[11]]
+set_property  -dict {PACKAGE_PIN  P11 IOSTANDARD LVCMOS33} [get_ports data_bd[12]]
+set_property  -dict {PACKAGE_PIN  R11 IOSTANDARD LVCMOS33} [get_ports data_bd[13]]
+set_property  -dict {PACKAGE_PIN  P15 IOSTANDARD LVCMOS33} [get_ports data_bd[14]]
+set_property  -dict {PACKAGE_PIN  R15 IOSTANDARD LVCMOS33} [get_ports data_bd[15]]
 
-set_property  -dict {PACKAGE_PIN  N11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rx_clk]
-set_property  -dict {PACKAGE_PIN  P13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxiq]
-set_property  -dict {PACKAGE_PIN  P10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[0]]
-set_property  -dict {PACKAGE_PIN  R10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[1]]
-set_property  -dict {PACKAGE_PIN  P8  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[2]]
-set_property  -dict {PACKAGE_PIN  P9  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[3]]
-set_property  -dict {PACKAGE_PIN  N7  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[4]]
-set_property  -dict {PACKAGE_PIN  N8  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[5]]
-set_property  -dict {PACKAGE_PIN  M10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[6]]
-set_property  -dict {PACKAGE_PIN  M11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[7]]
-set_property  -dict {PACKAGE_PIN  R7  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[8]]
-set_property  -dict {PACKAGE_PIN  R8  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[9]]
-set_property  -dict {PACKAGE_PIN  M9  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[10]]
-set_property  -dict {PACKAGE_PIN  N9  IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[11]]
+set_property  -dict {PACKAGE_PIN  N11 IOSTANDARD LVCMOS33} [get_ports rx_clk]
+set_property  -dict {PACKAGE_PIN  P13 IOSTANDARD LVCMOS33} [get_ports rxiq]
+set_property  -dict {PACKAGE_PIN  P10 IOSTANDARD LVCMOS33} [get_ports rxd[0]]
+set_property  -dict {PACKAGE_PIN  R10 IOSTANDARD LVCMOS33} [get_ports rxd[1]]
+set_property  -dict {PACKAGE_PIN  P8  IOSTANDARD LVCMOS33} [get_ports rxd[2]]
+set_property  -dict {PACKAGE_PIN  P9  IOSTANDARD LVCMOS33} [get_ports rxd[3]]
+set_property  -dict {PACKAGE_PIN  N7  IOSTANDARD LVCMOS33} [get_ports rxd[4]]
+set_property  -dict {PACKAGE_PIN  N8  IOSTANDARD LVCMOS33} [get_ports rxd[5]]
+set_property  -dict {PACKAGE_PIN  M10 IOSTANDARD LVCMOS33} [get_ports rxd[6]]
+set_property  -dict {PACKAGE_PIN  M11 IOSTANDARD LVCMOS33} [get_ports rxd[7]]
+set_property  -dict {PACKAGE_PIN  R7  IOSTANDARD LVCMOS33} [get_ports rxd[8]]
+set_property  -dict {PACKAGE_PIN  R8  IOSTANDARD LVCMOS33} [get_ports rxd[9]]
+set_property  -dict {PACKAGE_PIN  M9  IOSTANDARD LVCMOS33} [get_ports rxd[10]]
+set_property  -dict {PACKAGE_PIN  N9  IOSTANDARD LVCMOS33} [get_ports rxd[11]]
 
 set_property  -dict {PACKAGE_PIN  L12 IOSTANDARD LVCMOS33} [get_ports tx_clk]
 set_property  -dict {PACKAGE_PIN  N14 IOSTANDARD LVCMOS33} [get_ports txiq]

From 6aadb49e80969596cb0e2db2716cdb821a8c1bdd Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 2 Feb 2017 12:58:58 +0200
Subject: [PATCH 893/972] m2k: Remove use board flow from the standalone
 version

---
 projects/m2k/standalone/system_bd.tcl | 2 --
 1 file changed, 2 deletions(-)

diff --git a/projects/m2k/standalone/system_bd.tcl b/projects/m2k/standalone/system_bd.tcl
index 4d347e002..93f2236af 100644
--- a/projects/m2k/standalone/system_bd.tcl
+++ b/projects/m2k/standalone/system_bd.tcl
@@ -88,8 +88,6 @@ set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7
 
 set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
-set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
 
 set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
 set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc

From 1e54b5230f5eaca173ee6885315d9ca0f6274b2e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 2 Feb 2017 11:15:59 -0500
Subject: [PATCH 894/972] axi_adxcvr- add m_axi associated clock

---
 library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
index e38c8b3ae..5ca8237ed 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -62,6 +62,9 @@ for {set n 0} {$n < 16} {incr n} {
 
 }
 
+set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
+  -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
+
 set_property enablement_dependency \
   {spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \
   [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]

From a57fb5f82ffa93555d7f348a3752b54b4ad43e93 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 2 Feb 2017 14:21:41 -0500
Subject: [PATCH 895/972] library/ad9122- constraints clean-up

---
 library/axi_ad9122/axi_ad9122_constr.sdc | 4 +++-
 library/axi_ad9122/axi_ad9122_constr.xdc | 6 +++---
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122_constr.sdc b/library/axi_ad9122/axi_ad9122_constr.sdc
index ca63ab22f..b562156b6 100644
--- a/library/axi_ad9122/axi_ad9122_constr.sdc
+++ b/library/axi_ad9122/axi_ad9122_constr.sdc
@@ -1 +1,3 @@
-# false path definitions will come here
+
+set_false_path  -from [get_registers *up_drp_locked*] -to [get_registers *dac_status_m1*]
+
diff --git a/library/axi_ad9122/axi_ad9122_constr.xdc b/library/axi_ad9122/axi_ad9122_constr.xdc
index 6ca9c954f..36143c266 100644
--- a/library/axi_ad9122/axi_ad9122_constr.xdc
+++ b/library/axi_ad9122/axi_ad9122_constr.xdc
@@ -1,3 +1,3 @@
-set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_status_m1_reg     && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ */axi_ad9122/*/i_core_rst_reg/rst_reg* && IS_SEQUENTIAL}] 
-               -to   [get_cells -hier -filter {name =~ */axi_ad9122/inst/i_if/i_serdes_out_clk/g_data[0].i_serdes && IS_SEQUENTIAL}]
+
+set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg  && IS_SEQUENTIAL}] \
+	-to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}]

From d46352928a13f9ce1fe2fd29acd37e09ac87b7e8 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 2 Feb 2017 14:24:06 -0500
Subject: [PATCH 896/972] fmcomms5- fix ovf net connections

---
 projects/fmcomms5/common/fmcomms5_bd.tcl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl
index 0e0b3fb84..ba8720273 100644
--- a/projects/fmcomms5/common/fmcomms5_bd.tcl
+++ b/projects/fmcomms5/common/fmcomms5_bd.tcl
@@ -180,7 +180,8 @@ ad_connect  concat_logic/In3     axi_ad9361_1/dac_r1_mode
 ad_connect  concat_logic/dout    clkdiv_sel_logic/Op1
 ad_connect  clkdiv_sel_logic/Res clkdiv/clk_sel
 
-ad_connect  adc_wfifo/dout_ovf          axi_ad9361_0/adc_dovf
+ad_connect  axi_ad9361_adc_dma/fifo_wr_overflow adc_wfifo/dout_ovf          
+ad_connect  adc_wfifo/din_ovf axi_ad9361_0/adc_dovf
 ad_connect  axi_ad9361_0/adc_enable_i0  adc_wfifo/din_enable_0
 ad_connect  axi_ad9361_0/adc_valid_i0   adc_wfifo/din_valid_0
 ad_connect  axi_ad9361_0/adc_data_i0    adc_wfifo/din_data_0

From 35f660fe06367703cb9ef1b3ceca232499be240d Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 2 Feb 2017 15:05:49 -0500
Subject: [PATCH 897/972] fmcjesdadc1/vc707- constraint clean-up

---
 projects/fmcjesdadc1/vc707/system_constr.xdc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/projects/fmcjesdadc1/vc707/system_constr.xdc b/projects/fmcjesdadc1/vc707/system_constr.xdc
index ebeded59b..8bc97de97 100644
--- a/projects/fmcjesdadc1/vc707/system_constr.xdc
+++ b/projects/fmcjesdadc1/vc707/system_constr.xdc
@@ -24,7 +24,6 @@ create_clock -name rx_ref_clk   -period  4.00 [get_ports rx_ref_clk_p]
 create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
-set_false_path -to [get_cells i_system_wrapper/system_i/axi_ad9250_jesd/inst/rx_sysref_r_reg/D]
 
 set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
 set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1*  && IS_SEQUENTIAL}]

From 7c363cd5a7607eea2b341cbebd6cdc98c2c8ba53 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 1 Feb 2017 16:41:21 -0500
Subject: [PATCH 898/972] daq3/a10gx/system_constr.sdc- fix typo

---
 projects/daq3/a10gx/system_constr.sdc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc
index 6fd93ff6b..c1cfc2afe 100644
--- a/projects/daq3/a10gx/system_constr.sdc
+++ b/projects/daq3/a10gx/system_constr.sdc
@@ -23,7 +23,7 @@ set_false_path -from [get_clocks {sys_clk_100mhz}]\
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_tx_ctl_inst*]\
-  -to [get_clocks {i_system_bd||avl_ad9152_xcvr|alt_core_pll|outclk0}]
+  -to [get_clocks {i_system_bd|avl_ad9152_xcvr|alt_core_pll|outclk0}]
 
 set_false_path -from [get_clocks {sys_clk_100mhz}]\
   -through [get_nets *altera_jesd204_rx_csr_inst*]\

From 096274a03302a3441e5b70fda9f7ac85dc9f7feb Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 3 Feb 2017 09:25:53 -0500
Subject: [PATCH 899/972] daq2/zcu102- fix refclock pin swap

---
 projects/daq2/zcu102/system_constr.xdc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/daq2/zcu102/system_constr.xdc b/projects/daq2/zcu102/system_constr.xdc
index 96dcf2313..3763f1963 100644
--- a/projects/daq2/zcu102/system_constr.xdc
+++ b/projects/daq2/zcu102/system_constr.xdc
@@ -1,8 +1,8 @@
 
 # daq2
 
-set_property  -dict {PACKAGE_PIN  L7} [get_ports rx_ref_clk_p]                                              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
-set_property  -dict {PACKAGE_PIN  L8} [get_ports rx_ref_clk_n]                                              ; ## B21  FMC_HPC_GBTCLK1_M2C_N
+set_property  -dict {PACKAGE_PIN  L8} [get_ports rx_ref_clk_p]                                              ; ## B20  FMC_HPC_GBTCLK1_M2C_P
+set_property  -dict {PACKAGE_PIN  L7} [get_ports rx_ref_clk_n]                                              ; ## B21  FMC_HPC_GBTCLK1_M2C_N
 set_property  -dict {PACKAGE_PIN  W2  IOSTANDARD LVDS} [get_ports rx_sync_p]                                ; ## D08  FMC_HPC_LA01_CC_P
 set_property  -dict {PACKAGE_PIN  W1  IOSTANDARD LVDS} [get_ports rx_sync_n]                                ; ## D09  FMC_HPC_LA01_CC_N
 set_property  -dict {PACKAGE_PIN  Y2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p]       ; ## G09  FMC_HPC_LA03_P

From 971bcbb0fc86c2d68dd979ee39b49f9c9ec8e55d Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri, 3 Feb 2017 16:42:44 +0200
Subject: [PATCH 900/972] fmcomms1: Remove project

---
 projects/fmcomms1/Makefile                 |  39 ---
 projects/fmcomms1/ac701/Makefile           |  76 -----
 projects/fmcomms1/ac701/system_bd.tcl      |   5 -
 projects/fmcomms1/ac701/system_constr.xdc  | 158 ----------
 projects/fmcomms1/ac701/system_project.tcl |  18 --
 projects/fmcomms1/ac701/system_top.v       | 268 -----------------
 projects/fmcomms1/common/fmcomms1_bd.tcl   | 169 -----------
 projects/fmcomms1/kc705/Makefile           |  76 -----
 projects/fmcomms1/kc705/system_bd.tcl      |   4 -
 projects/fmcomms1/kc705/system_constr.xdc  |  86 ------
 projects/fmcomms1/kc705/system_project.tcl |  19 --
 projects/fmcomms1/kc705/system_top.v       | 316 -------------------
 projects/fmcomms1/vc707/Makefile           |  76 -----
 projects/fmcomms1/vc707/system_bd.tcl      |   4 -
 projects/fmcomms1/vc707/system_constr.xdc  |  86 ------
 projects/fmcomms1/vc707/system_project.tcl |  18 --
 projects/fmcomms1/vc707/system_top.v       | 302 -------------------
 projects/fmcomms1/zc702/Makefile           |  84 ------
 projects/fmcomms1/zc702/system_bd.tcl      |   5 -
 projects/fmcomms1/zc702/system_constr.xdc  |  86 ------
 projects/fmcomms1/zc702/system_project.tcl |  18 --
 projects/fmcomms1/zc702/system_top.v       | 281 -----------------
 projects/fmcomms1/zc706/Makefile           |  84 ------
 projects/fmcomms1/zc706/system_bd.tcl      |   4 -
 projects/fmcomms1/zc706/system_constr.xdc  |  86 ------
 projects/fmcomms1/zc706/system_project.tcl |  18 --
 projects/fmcomms1/zc706/system_top.v       | 280 -----------------
 projects/fmcomms1/zed/Makefile             |  90 ------
 projects/fmcomms1/zed/system_bd.tcl        |  13 -
 projects/fmcomms1/zed/system_constr.xdc    |  86 ------
 projects/fmcomms1/zed/system_project.tcl   |  18 --
 projects/fmcomms1/zed/system_top.v         | 335 ---------------------
 32 files changed, 3208 deletions(-)
 delete mode 100644 projects/fmcomms1/Makefile
 delete mode 100644 projects/fmcomms1/ac701/Makefile
 delete mode 100644 projects/fmcomms1/ac701/system_bd.tcl
 delete mode 100644 projects/fmcomms1/ac701/system_constr.xdc
 delete mode 100644 projects/fmcomms1/ac701/system_project.tcl
 delete mode 100644 projects/fmcomms1/ac701/system_top.v
 delete mode 100644 projects/fmcomms1/common/fmcomms1_bd.tcl
 delete mode 100644 projects/fmcomms1/kc705/Makefile
 delete mode 100644 projects/fmcomms1/kc705/system_bd.tcl
 delete mode 100644 projects/fmcomms1/kc705/system_constr.xdc
 delete mode 100644 projects/fmcomms1/kc705/system_project.tcl
 delete mode 100644 projects/fmcomms1/kc705/system_top.v
 delete mode 100644 projects/fmcomms1/vc707/Makefile
 delete mode 100644 projects/fmcomms1/vc707/system_bd.tcl
 delete mode 100644 projects/fmcomms1/vc707/system_constr.xdc
 delete mode 100644 projects/fmcomms1/vc707/system_project.tcl
 delete mode 100644 projects/fmcomms1/vc707/system_top.v
 delete mode 100644 projects/fmcomms1/zc702/Makefile
 delete mode 100644 projects/fmcomms1/zc702/system_bd.tcl
 delete mode 100644 projects/fmcomms1/zc702/system_constr.xdc
 delete mode 100644 projects/fmcomms1/zc702/system_project.tcl
 delete mode 100644 projects/fmcomms1/zc702/system_top.v
 delete mode 100644 projects/fmcomms1/zc706/Makefile
 delete mode 100644 projects/fmcomms1/zc706/system_bd.tcl
 delete mode 100644 projects/fmcomms1/zc706/system_constr.xdc
 delete mode 100644 projects/fmcomms1/zc706/system_project.tcl
 delete mode 100644 projects/fmcomms1/zc706/system_top.v
 delete mode 100644 projects/fmcomms1/zed/Makefile
 delete mode 100644 projects/fmcomms1/zed/system_bd.tcl
 delete mode 100644 projects/fmcomms1/zed/system_constr.xdc
 delete mode 100644 projects/fmcomms1/zed/system_project.tcl
 delete mode 100644 projects/fmcomms1/zed/system_top.v

diff --git a/projects/fmcomms1/Makefile b/projects/fmcomms1/Makefile
deleted file mode 100644
index d79fd3853..000000000
--- a/projects/fmcomms1/Makefile
+++ /dev/null
@@ -1,39 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-.PHONY: all clean clean-all 
-all:
-	-make -C ac701 all
-	-make -C kc705 all
-	-make -C vc707 all
-	-make -C zc702 all
-	-make -C zc706 all
-	-make -C zed all
-	-make -C zc706 all
-
-
-clean: 
-	make -C ac701 clean
-	make -C kc705 clean
-	make -C vc707 clean
-	make -C zc702 clean
-	make -C zc706 clean
-	make -C zed clean
-	make -C zc706 clean
-
-
-clean-all:
-	make -C ac701 clean-all
-	make -C kc705 clean-all
-	make -C vc707 clean-all
-	make -C zc702 clean-all
-	make -C zc706 clean-all
-	make -C zed clean-all
-	make -C zc706 clean-all
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms1/ac701/Makefile
deleted file mode 100644
index b75bf5e4d..000000000
--- a/projects/fmcomms1/ac701/Makefile
+++ /dev/null
@@ -1,76 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../common/fmcomms1_bd.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/ac701/ac701_system_mig.prj
-M_DEPS += ../../common/ac701/ac701_system_constr.xdc
-M_DEPS += ../../common/ac701/ac701_system_bd.tcl
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
-M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
-M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_upack/util_upack.xpr
-M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib fmcomms1_ac701.sdk/system_top.hdf
-
-
-clean: 
-	rm -rf $(M_FLIST)
-
-
-clean-all:clean
-	make -C ../../../library/axi_ad9122 clean
-	make -C ../../../library/axi_ad9643 clean
-	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_upack clean
-	make -C ../../../library/util_wfifo clean
-
-
-fmcomms1_ac701.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms1_ac701_vivado.log 2>&1
-
-
-lib:
-	make -C ../../../library/axi_ad9122
-	make -C ../../../library/axi_ad9643
-	make -C ../../../library/axi_dmac
-	make -C ../../../library/util_cpack
-	make -C ../../../library/util_upack
-	make -C ../../../library/util_wfifo
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms1/ac701/system_bd.tcl b/projects/fmcomms1/ac701/system_bd.tcl
deleted file mode 100644
index e398e9ada..000000000
--- a/projects/fmcomms1/ac701/system_bd.tcl
+++ /dev/null
@@ -1,5 +0,0 @@
-
-  source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl
-  source ../common/fmcomms1_bd.tcl
-  set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9643_dma
-
diff --git a/projects/fmcomms1/ac701/system_constr.xdc b/projects/fmcomms1/ac701/system_constr.xdc
deleted file mode 100644
index 64006bbeb..000000000
--- a/projects/fmcomms1/ac701/system_constr.xdc
+++ /dev/null
@@ -1,158 +0,0 @@
-
-# reference
-
-set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_p]
-set_property DIFF_TERM TRUE [get_ports ref_clk_out_p]
-set_property PACKAGE_PIN J21 [get_ports ref_clk_out_n]
-set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_n]
-set_property DIFF_TERM TRUE [get_ports ref_clk_out_n]
-
-# dac 
-
-set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_p]
-set_property DIFF_TERM TRUE [get_ports dac_clk_in_p]
-set_property PACKAGE_PIN C19 [get_ports dac_clk_in_n]
-set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_n]
-set_property DIFF_TERM TRUE [get_ports dac_clk_in_n]
-set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_p]
-set_property PACKAGE_PIN H19 [get_ports dac_clk_out_n]
-set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_n]
-set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_p]
-set_property PACKAGE_PIN A19 [get_ports dac_frame_out_n]
-set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_n]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[0]}]
-set_property PACKAGE_PIN G26 [get_ports {dac_data_out_n[0]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[0]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[1]}]
-set_property PACKAGE_PIN F25 [get_ports {dac_data_out_n[1]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[1]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[2]}]
-set_property PACKAGE_PIN D25 [get_ports {dac_data_out_n[2]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[2]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[3]}]
-set_property PACKAGE_PIN K23 [get_ports {dac_data_out_n[3]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[3]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[4]}]
-set_property PACKAGE_PIN D26 [get_ports {dac_data_out_n[4]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[4]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[5]}]
-set_property PACKAGE_PIN F24 [get_ports {dac_data_out_n[5]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[5]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[6]}]
-set_property PACKAGE_PIN H18 [get_ports {dac_data_out_n[6]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[6]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[7]}]
-set_property PACKAGE_PIN F22 [get_ports {dac_data_out_n[7]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[7]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[8]}]
-set_property PACKAGE_PIN L18 [get_ports {dac_data_out_n[8]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[8]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[9]}]
-set_property PACKAGE_PIN E23 [get_ports {dac_data_out_n[9]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[9]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[10]}]
-set_property PACKAGE_PIN H24 [get_ports {dac_data_out_n[10]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[10]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[11]}]
-set_property PACKAGE_PIN J20 [get_ports {dac_data_out_n[11]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[11]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[12]}]
-set_property PACKAGE_PIN L14 [get_ports {dac_data_out_n[12]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[12]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[13]}]
-set_property PACKAGE_PIN M17 [get_ports {dac_data_out_n[13]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[13]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[14]}]
-set_property PACKAGE_PIN A22 [get_ports {dac_data_out_n[14]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[14]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[15]}]
-set_property PACKAGE_PIN D21 [get_ports {dac_data_out_n[15]}]
-set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[15]}]
-
-# adc 
-
-set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_p]
-set_property DIFF_TERM TRUE [get_ports adc_clk_in_p]
-set_property PACKAGE_PIN H22 [get_ports adc_clk_in_n]
-set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_n]
-set_property DIFF_TERM TRUE [get_ports adc_clk_in_n]
-set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_p]
-set_property DIFF_TERM TRUE [get_ports adc_or_in_p]
-set_property PACKAGE_PIN C18 [get_ports adc_or_in_n]
-set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_n]
-set_property DIFF_TERM TRUE [get_ports adc_or_in_n]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[0]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[0]}]
-set_property PACKAGE_PIN G21 [get_ports {adc_data_in_n[0]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[0]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[0]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[1]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[1]}]
-set_property PACKAGE_PIN B21 [get_ports {adc_data_in_n[1]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[1]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[1]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[2]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[2]}]
-set_property PACKAGE_PIN A20 [get_ports {adc_data_in_n[2]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[2]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[2]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[3]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[3]}]
-set_property PACKAGE_PIN F17 [get_ports {adc_data_in_n[3]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[3]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[3]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[4]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[4]}]
-set_property PACKAGE_PIN F15 [get_ports {adc_data_in_n[4]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[4]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[4]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[5]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[5]}]
-set_property PACKAGE_PIN A18 [get_ports {adc_data_in_n[5]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[5]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[5]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[6]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[6]}]
-set_property PACKAGE_PIN D20 [get_ports {adc_data_in_n[6]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[6]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[6]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[7]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[7]}]
-set_property PACKAGE_PIN G16 [get_ports {adc_data_in_n[7]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[7]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[7]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[8]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[8]}]
-set_property PACKAGE_PIN H15 [get_ports {adc_data_in_n[8]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[8]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[8]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[9]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[9]}]
-set_property PACKAGE_PIN F19 [get_ports {adc_data_in_n[9]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[9]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[9]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[10]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[10]}]
-set_property PACKAGE_PIN D16 [get_ports {adc_data_in_n[10]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[10]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[10]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[11]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[11]}]
-set_property PACKAGE_PIN B17 [get_ports {adc_data_in_n[11]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[11]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[11]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[12]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[12]}]
-set_property PACKAGE_PIN F20 [get_ports {adc_data_in_n[12]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[12]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[12]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[13]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[13]}]
-set_property PACKAGE_PIN E18 [get_ports {adc_data_in_n[13]}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[13]}]
-set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[13]}]
-
-# clocks
-
-create_clock -period 2.000 -name dac_clk_in [get_ports dac_clk_in_p]
-create_clock -period 4.000 -name adc_clk_in [get_ports adc_clk_in_p]
diff --git a/projects/fmcomms1/ac701/system_project.tcl b/projects/fmcomms1/ac701/system_project.tcl
deleted file mode 100644
index c41bf1b5d..000000000
--- a/projects/fmcomms1/ac701/system_project.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-
-source ../../scripts/adi_env.tcl
-source $ad_hdl_dir/projects/scripts/adi_project.tcl
-source $ad_hdl_dir/projects/scripts/adi_board.tcl
-
-adi_project_create fmcomms1_ac701
-adi_project_files fmcomms1_ac701 [list \
-  "system_top.v" \
-  "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run fmcomms1_ac701
-
-
diff --git a/projects/fmcomms1/ac701/system_top.v b/projects/fmcomms1/ac701/system_top.v
deleted file mode 100644
index de6f0517e..000000000
--- a/projects/fmcomms1/ac701/system_top.v
+++ /dev/null
@@ -1,268 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module system_top (
-
-  sys_rst,
-  sys_clk_p,
-  sys_clk_n,
-
-  uart_sin,
-  uart_sout,
-
-  ddr3_addr,
-  ddr3_ba,
-  ddr3_cas_n,
-  ddr3_ck_n,
-  ddr3_ck_p,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_dm,
-  ddr3_dq,
-  ddr3_dqs_n,
-  ddr3_dqs_p,
-  ddr3_odt,
-  ddr3_ras_n,
-  ddr3_reset_n,
-  ddr3_we_n,
-
-  phy_reset_n,
-  phy_mdc,
-  phy_mdio,
-  phy_tx_clk,
-  phy_tx_ctrl,
-  phy_tx_data,
-  phy_rx_clk,
-  phy_rx_ctrl,
-  phy_rx_data,
-
-  fan_pwm,
-
-  gpio_lcd,
-  gpio_bd,
-
-  iic_rstn,
-  iic_scl,
-  iic_sda,
-
-  dac_clk_in_p,
-  dac_clk_in_n,
-  dac_clk_out_p,
-  dac_clk_out_n,
-  dac_frame_out_p,
-  dac_frame_out_n,
-  dac_data_out_p,
-  dac_data_out_n,
-
-  adc_clk_in_p,
-  adc_clk_in_n,
-  adc_or_in_p,
-  adc_or_in_n,
-  adc_data_in_p,
-  adc_data_in_n,
-
-  ref_clk_out_p,
-  ref_clk_out_n);
-
-  input           sys_rst;
-  input           sys_clk_p;
-  input           sys_clk_n;
-
-  input           uart_sin;
-  output          uart_sout;
-
-  output  [13:0]  ddr3_addr;
-  output  [ 2:0]  ddr3_ba;
-  output          ddr3_cas_n;
-  output  [ 0:0]  ddr3_ck_n;
-  output  [ 0:0]  ddr3_ck_p;
-  output  [ 0:0]  ddr3_cke;
-  output  [ 0:0]  ddr3_cs_n;
-  output  [ 7:0]  ddr3_dm;
-  inout   [63:0]  ddr3_dq;
-  inout   [ 7:0]  ddr3_dqs_n;
-  inout   [ 7:0]  ddr3_dqs_p;
-  output  [ 0:0]  ddr3_odt;
-  output          ddr3_ras_n;
-  output          ddr3_reset_n;
-  output          ddr3_we_n;
-
-  output          phy_reset_n;
-  output          phy_mdc;
-  inout           phy_mdio;
-  output          phy_tx_clk;
-  output          phy_tx_ctrl;
-  output  [ 3:0]  phy_tx_data;
-  input           phy_rx_clk;
-  input           phy_rx_ctrl;
-  input   [ 3:0]  phy_rx_data;
-
-  output          fan_pwm;
-
-  inout   [ 6:0]  gpio_lcd;
-  inout   [12:0]  gpio_bd;
-
-  output          iic_rstn;
-  inout           iic_scl;
-  inout           iic_sda;
-
-  input           dac_clk_in_p;
-  input           dac_clk_in_n;
-  output          dac_clk_out_p;
-  output          dac_clk_out_n;
-  output          dac_frame_out_p;
-  output          dac_frame_out_n;
-  output   [15:0] dac_data_out_p;
-  output   [15:0] dac_data_out_n;
-
-  input           adc_clk_in_p;
-  input           adc_clk_in_n;
-  input           adc_or_in_p;
-  input           adc_or_in_n;
-  input   [13:0]  adc_data_in_p;
-  input   [13:0]  adc_data_in_n;
-
-  output          ref_clk_out_p;
-  output          ref_clk_out_n;
-
-  // internal signals
-
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire            ref_clk;
-  wire            oddr_ref_clk;
-
-  // assignments
-
-  assign mgt_clk_sel  = 2'd0;
-  assign fan_pwm      = 1'b1;
-  assign iic_rstn     = 1'b1;
-
-  // instantiations
-
- ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_sw_led (
-    .dio_t (gpio_t[12:0]),
-    .dio_i (gpio_o[12:0]),
-    .dio_o (gpio_i[12:0]),
-    .dio_p (gpio_bd));
-
-  ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_oddr_ref_clk (
-    .S (1'b0),
-    .CE (1'b1),
-    .R (1'b0),
-    .C (ref_clk),
-    .D1 (1'b1),
-    .D2 (1'b0),
-    .Q (oddr_ref_clk));
-
-  OBUFDS i_obufds_ref_clk (
-    .I (oddr_ref_clk),
-    .O (ref_clk_out_p),
-    .OB (ref_clk_out_n));
-
-  system_wrapper i_system_wrapper (
-    .ddr3_addr (ddr3_addr),
-    .ddr3_ba (ddr3_ba),
-    .ddr3_cas_n (ddr3_cas_n),
-    .ddr3_ck_n (ddr3_ck_n),
-    .ddr3_ck_p (ddr3_ck_p),
-    .ddr3_cke (ddr3_cke),
-    .ddr3_cs_n (ddr3_cs_n),
-    .ddr3_dm (ddr3_dm),
-    .ddr3_dq (ddr3_dq),
-    .ddr3_dqs_n (ddr3_dqs_n),
-    .ddr3_dqs_p (ddr3_dqs_p),
-    .ddr3_odt (ddr3_odt),
-    .ddr3_ras_n (ddr3_ras_n),
-    .ddr3_reset_n (ddr3_reset_n),
-    .ddr3_we_n (ddr3_we_n),
-    .gpio_lcd_tri_io (gpio_lcd),
-    .gpio0_o (gpio_o[31:0]),
-    .gpio0_t (gpio_t[31:0]),
-    .gpio0_i (gpio_i[31:0]),
-    .gpio1_o (gpio_o[63:32]),
-    .gpio1_t (gpio_t[63:32]),
-    .gpio1_i (gpio_i[63:32]),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
-    .mb_intr_06 (1'b0),
-    .mb_intr_07 (1'b0),
-    .mb_intr_08 (1'b0),
-    .mb_intr_14 (1'b0),
-    .mb_intr_15 (1'b0),
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .adc_or_in_n (adc_or_in_n),
-    .adc_or_in_p (adc_or_in_p),
-    .dac_clk_in_n (dac_clk_in_n),
-    .dac_clk_in_p (dac_clk_in_p),
-    .dac_clk_out_n (dac_clk_out_n),
-    .dac_clk_out_p (dac_clk_out_p),
-    .dac_data_out_n (dac_data_out_n),
-    .dac_data_out_p (dac_data_out_p),
-    .dac_frame_out_n (dac_frame_out_n),
-    .dac_frame_out_p (dac_frame_out_p),
-    .ref_clk (ref_clk),
-    .mdio_mdio_io (phy_mdio),
-    .mdio_mdc (phy_mdc),
-    .phy_rst_n (phy_reset_n),
-    .rgmii_rd (phy_rx_data),
-    .rgmii_rx_ctl (phy_rx_ctrl),
-    .rgmii_rxc (phy_rx_clk),
-    .rgmii_td (phy_tx_data),
-    .rgmii_tx_ctl (phy_tx_ctrl),
-    .rgmii_txc (phy_tx_clk),
-    .sys_clk_n (sys_clk_n),
-    .sys_clk_p (sys_clk_p),
-    .sys_rst (sys_rst),
-    .uart_sin (uart_sin),
-    .uart_sout (uart_sout));
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl
deleted file mode 100644
index 2e3eef67a..000000000
--- a/projects/fmcomms1/common/fmcomms1_bd.tcl
+++ /dev/null
@@ -1,169 +0,0 @@
-
-  # dac interface
-
-  create_bd_port -dir I dac_clk_in_p
-  create_bd_port -dir I dac_clk_in_n
-  create_bd_port -dir O dac_clk_out_p
-  create_bd_port -dir O dac_clk_out_n
-  create_bd_port -dir O dac_frame_out_p
-  create_bd_port -dir O dac_frame_out_n
-  create_bd_port -dir O -from 15 -to 0 dac_data_out_p
-  create_bd_port -dir O -from 15 -to 0 dac_data_out_n
-
-  # adc interface
-
-  create_bd_port -dir I adc_clk_in_p
-  create_bd_port -dir I adc_clk_in_n
-  create_bd_port -dir I adc_or_in_p
-  create_bd_port -dir I adc_or_in_n
-  create_bd_port -dir I -from 13 -to 0 adc_data_in_p
-  create_bd_port -dir I -from 13 -to 0 adc_data_in_n
-
-  # reference clock
-
-  create_bd_port -dir O ref_clk
-
-  # dac peripherals
-
-  set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122]
-
-  set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
-  set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma
-  set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma
-  set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9122_dma
-  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma
-  set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma
-  set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9122_dma
-  set_property -dict [list CONFIG.AXI_SLICE_SRC {1}]  $axi_ad9122_dma
-  set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma
-
-  set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122]
-  set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $util_upack_ad9122
-  set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_upack_ad9122
-
-  # adc peripherals
-
-  set axi_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9643:1.0 axi_ad9643]
-
-  set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma]
-  set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9643_dma
-  set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9643_dma
-  set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9643_dma
-  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9643_dma
-  set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9643_dma
-  set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9643_dma
-  set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9643_dma
-  set_property -dict [list CONFIG.AXI_SLICE_SRC {1}]  $axi_ad9643_dma
-  set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
-
-  set util_cpack_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9643]
-  set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_cpack_ad9643
-  set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9643
-
-  set util_ad9643_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9643_adc_fifo]
-  set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9643_adc_fifo
-  set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9643_adc_fifo
-  set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9643_adc_fifo
-  set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $util_ad9643_adc_fifo
-
-  # reference clock
-
-  set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 refclk_clkgen]
-  set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen
-  set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen
-  set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen
-  set_property -dict [list CONFIG.USE_LOCKED {false} ] $refclk_clkgen
-  set_property -dict [list CONFIG.USE_RESET {false} ] $refclk_clkgen
-
-  # reference clock connections
-
-  ad_connect sys_200m_clk refclk_clkgen/clk_in1
-  ad_connect ref_clk      refclk_clkgen/clk_out1
-
-  # connections (dac)
-
-  ad_connect dac_clk axi_ad9122/dac_div_clk
-  ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk
-  ad_connect dac_clk util_upack_ad9122/dac_clk
-
-  ad_connect dac_clk_in_p     axi_ad9122/dac_clk_in_p
-  ad_connect dac_clk_in_n     axi_ad9122/dac_clk_in_n
-  ad_connect dac_clk_out_p    axi_ad9122/dac_clk_out_p
-  ad_connect dac_clk_out_n    axi_ad9122/dac_clk_out_n
-  ad_connect dac_frame_out_p  axi_ad9122/dac_frame_out_p
-  ad_connect dac_frame_out_n  axi_ad9122/dac_frame_out_n
-  ad_connect dac_data_out_p   axi_ad9122/dac_data_out_p
-  ad_connect dac_data_out_n   axi_ad9122/dac_data_out_n
-
-  ad_connect axi_ad9122/dac_valid_0   util_upack_ad9122/dac_valid_0
-  ad_connect axi_ad9122/dac_enable_0  util_upack_ad9122/dac_enable_0
-  ad_connect axi_ad9122/dac_ddata_0   util_upack_ad9122/dac_data_0
-  ad_connect axi_ad9122/dac_valid_1   util_upack_ad9122/dac_valid_1
-  ad_connect axi_ad9122/dac_enable_1  util_upack_ad9122/dac_enable_1
-  ad_connect axi_ad9122/dac_ddata_1   util_upack_ad9122/dac_data_1
-  ad_connect axi_ad9122/dac_dunf      axi_ad9122_dma/fifo_rd_underflow
-
-  ad_connect util_upack_ad9122/dac_valid  axi_ad9122_dma/fifo_rd_en
-  ad_connect util_upack_ad9122/dac_data   axi_ad9122_dma/fifo_rd_dout
-  ad_connect util_upack_ad9122/dac_sync   axi_ad9122/dac_sync_in
-
-  # connections (adc)
-
-  ad_connect  adc_clk             axi_ad9643/adc_clk
-  ad_connect  adc_clk             util_ad9643_adc_fifo/din_clk
-  ad_connect  sys_200m_clk        util_cpack_ad9643/adc_clk
-  ad_connect  sys_200m_clk        axi_ad9643/delay_clk
-  ad_connect  sys_200m_clk        axi_ad9643_dma/fifo_wr_clk
-  ad_connect  sys_200m_clk        util_ad9643_adc_fifo/dout_clk
-  ad_connect  adc_rst             axi_ad9643/adc_rst
-  ad_connect  adc_rst             util_ad9643_adc_fifo/din_rst
-  ad_connect  sys_cpu_resetn      util_ad9643_adc_fifo/dout_rstn
-  ad_connect  sys_cpu_reset       util_cpack_ad9643/adc_rst
-
-  ad_connect  adc_clk_in_p  axi_ad9643/adc_clk_in_p
-  ad_connect  adc_clk_in_n  axi_ad9643/adc_clk_in_n
-  ad_connect  adc_or_in_p   axi_ad9643/adc_or_in_p
-  ad_connect  adc_or_in_n   axi_ad9643/adc_or_in_n
-  ad_connect  adc_data_in_p axi_ad9643/adc_data_in_p
-  ad_connect  adc_data_in_n axi_ad9643/adc_data_in_n
-
-  ad_connect  axi_ad9643/adc_valid_0  util_ad9643_adc_fifo/din_valid_0
-  ad_connect  axi_ad9643/adc_enable_0 util_ad9643_adc_fifo/din_enable_0
-  ad_connect  axi_ad9643/adc_data_0   util_ad9643_adc_fifo/din_data_0
-  ad_connect  axi_ad9643/adc_valid_1  util_ad9643_adc_fifo/din_valid_1
-  ad_connect  axi_ad9643/adc_enable_1 util_ad9643_adc_fifo/din_enable_1
-  ad_connect  axi_ad9643/adc_data_1   util_ad9643_adc_fifo/din_data_1
-
-  ad_connect  util_ad9643_adc_fifo/dout_valid_0   util_cpack_ad9643/adc_valid_0
-  ad_connect  util_ad9643_adc_fifo/dout_enable_0  util_cpack_ad9643/adc_enable_0
-  ad_connect  util_ad9643_adc_fifo/dout_data_0    util_cpack_ad9643/adc_data_0
-  ad_connect  util_ad9643_adc_fifo/dout_valid_1   util_cpack_ad9643/adc_valid_1
-  ad_connect  util_ad9643_adc_fifo/dout_enable_1  util_cpack_ad9643/adc_enable_1
-  ad_connect  util_ad9643_adc_fifo/dout_data_1    util_cpack_ad9643/adc_data_1
-
-  ad_connect  util_ad9643_adc_fifo/din_ovf    axi_ad9643/adc_dovf
-
-  ad_connect  util_cpack_ad9643/adc_valid     axi_ad9643_dma/fifo_wr_en
-  ad_connect  util_cpack_ad9643/adc_sync      axi_ad9643_dma/fifo_wr_sync
-  ad_connect  util_cpack_ad9643/adc_data      axi_ad9643_dma/fifo_wr_din
-  ad_connect  util_ad9643_adc_fifo/dout_ovf   axi_ad9643_dma/fifo_wr_overflow
-
-  ad_connect  sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
-  ad_connect  sys_cpu_resetn axi_ad9643_dma/m_dest_axi_aresetn
-
-  # address map
-
-  ad_cpu_interconnect 0x74200000  axi_ad9122
-  ad_cpu_interconnect 0x79020000  axi_ad9643
-  ad_cpu_interconnect 0x7c400000  axi_ad9643_dma
-  ad_cpu_interconnect 0x7c420000  axi_ad9122_dma
-  ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
-  ad_mem_hp1_interconnect sys_200m_clk axi_ad9643_dma/m_dest_axi
-  ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
-  ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
-
-  # interrupts
-
-  ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq
-  ad_cpu_interrupt ps-13 mb-13 axi_ad9643_dma/irq
-
diff --git a/projects/fmcomms1/kc705/Makefile b/projects/fmcomms1/kc705/Makefile
deleted file mode 100644
index aa1633c2a..000000000
--- a/projects/fmcomms1/kc705/Makefile
+++ /dev/null
@@ -1,76 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../common/fmcomms1_bd.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/kc705/kc705_system_mig.prj
-M_DEPS += ../../common/kc705/kc705_system_constr.xdc
-M_DEPS += ../../common/kc705/kc705_system_bd.tcl
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
-M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
-M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_upack/util_upack.xpr
-M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib fmcomms1_kc705.sdk/system_top.hdf
-
-
-clean: 
-	rm -rf $(M_FLIST)
-
-
-clean-all:clean
-	make -C ../../../library/axi_ad9122 clean
-	make -C ../../../library/axi_ad9643 clean
-	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_upack clean
-	make -C ../../../library/util_wfifo clean
-
-
-fmcomms1_kc705.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms1_kc705_vivado.log 2>&1
-
-
-lib:
-	make -C ../../../library/axi_ad9122
-	make -C ../../../library/axi_ad9643
-	make -C ../../../library/axi_dmac
-	make -C ../../../library/util_cpack
-	make -C ../../../library/util_upack
-	make -C ../../../library/util_wfifo
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms1/kc705/system_bd.tcl b/projects/fmcomms1/kc705/system_bd.tcl
deleted file mode 100644
index 5790fe398..000000000
--- a/projects/fmcomms1/kc705/system_bd.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-
-  source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
-  source ../common/fmcomms1_bd.tcl
-
diff --git a/projects/fmcomms1/kc705/system_constr.xdc b/projects/fmcomms1/kc705/system_constr.xdc
deleted file mode 100644
index ccdbcaffe..000000000
--- a/projects/fmcomms1/kc705/system_constr.xdc
+++ /dev/null
@@ -1,86 +0,0 @@
-
-# reference
-
-set_property  -dict {PACKAGE_PIN AB27   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p]      ; ## FMC_LPC_LA17_CC_P
-set_property  -dict {PACKAGE_PIN AC27   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n]      ; ## FMC_LPC_LA17_CC_N
-
-# dac 
-
-set_property  -dict {PACKAGE_PIN AF22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p]       ; ## FMC_LPC_CLK0_M2C_P
-set_property  -dict {PACKAGE_PIN AG23   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n]       ; ## FMC_LPC_CLK0_M2C_N
-set_property  -dict {PACKAGE_PIN AG27   IOSTANDARD LVDS_25} [get_ports dac_clk_out_p]                     ; ## FMC_LPC_LA21_P
-set_property  -dict {PACKAGE_PIN AG28   IOSTANDARD LVDS_25} [get_ports dac_clk_out_n]                     ; ## FMC_LPC_LA21_N
-set_property  -dict {PACKAGE_PIN AE25   IOSTANDARD LVDS_25} [get_ports dac_frame_out_p]                   ; ## FMC_LPC_LA11_P
-set_property  -dict {PACKAGE_PIN AF25   IOSTANDARD LVDS_25} [get_ports dac_frame_out_n]                   ; ## FMC_LPC_LA11_N
-set_property  -dict {PACKAGE_PIN Y30    IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]]                 ; ## FMC_LPC_LA32_P
-set_property  -dict {PACKAGE_PIN AA30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]]                ; ## FMC_LPC_LA32_N
-set_property  -dict {PACKAGE_PIN AC29   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]]                 ; ## FMC_LPC_LA33_P
-set_property  -dict {PACKAGE_PIN AC30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]]                 ; ## FMC_LPC_LA33_N
-set_property  -dict {PACKAGE_PIN AB29   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]]                 ; ## FMC_LPC_LA30_P
-set_property  -dict {PACKAGE_PIN AB30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]]                 ; ## FMC_LPC_LA30_N
-set_property  -dict {PACKAGE_PIN AE30   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]]                 ; ## FMC_LPC_LA28_P
-set_property  -dict {PACKAGE_PIN AF30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]]                 ; ## FMC_LPC_LA28_N
-set_property  -dict {PACKAGE_PIN AD29   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]]                 ; ## FMC_LPC_LA31_P
-set_property  -dict {PACKAGE_PIN AE29   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]]                 ; ## FMC_LPC_LA31_N
-set_property  -dict {PACKAGE_PIN AE28   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]]                 ; ## FMC_LPC_LA29_P
-set_property  -dict {PACKAGE_PIN AF28   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]]                 ; ## FMC_LPC_LA29_N
-set_property  -dict {PACKAGE_PIN AG30   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]]                 ; ## FMC_LPC_LA24_P
-set_property  -dict {PACKAGE_PIN AH30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]]                 ; ## FMC_LPC_LA24_N
-set_property  -dict {PACKAGE_PIN AC26   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]]                 ; ## FMC_LPC_LA25_P
-set_property  -dict {PACKAGE_PIN AD26   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]]                 ; ## FMC_LPC_LA25_N
-set_property  -dict {PACKAGE_PIN AJ27   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]]                 ; ## FMC_LPC_LA22_P
-set_property  -dict {PACKAGE_PIN AK28   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]]                 ; ## FMC_LPC_LA22_N
-set_property  -dict {PACKAGE_PIN AJ28   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]]                 ; ## FMC_LPC_LA27_P
-set_property  -dict {PACKAGE_PIN AJ29   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]]                 ; ## FMC_LPC_LA27_N
-set_property  -dict {PACKAGE_PIN AK29   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]]                ; ## FMC_LPC_LA26_P
-set_property  -dict {PACKAGE_PIN AK30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]]                ; ## FMC_LPC_LA26_N
-set_property  -dict {PACKAGE_PIN AH26   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]]                ; ## FMC_LPC_LA23_P
-set_property  -dict {PACKAGE_PIN AH27   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]]                ; ## FMC_LPC_LA23_N
-set_property  -dict {PACKAGE_PIN AJ26   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]]                ; ## FMC_LPC_LA19_P
-set_property  -dict {PACKAGE_PIN AK26   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]]                ; ## FMC_LPC_LA19_N
-set_property  -dict {PACKAGE_PIN AF26   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]]                ; ## FMC_LPC_LA20_P
-set_property  -dict {PACKAGE_PIN AF27   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]]                ; ## FMC_LPC_LA20_N
-set_property  -dict {PACKAGE_PIN AC24   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]]                ; ## FMC_LPC_LA15_P
-set_property  -dict {PACKAGE_PIN AD24   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]]                ; ## FMC_LPC_LA15_N
-set_property  -dict {PACKAGE_PIN AC22   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]]                ; ## FMC_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN AD22   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]]                ; ## FMC_LPC_LA16_N
-
-# adc 
-
-set_property  -dict {PACKAGE_PIN AG29   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p]       ; ## FMC_LPC_CLK1_M2C_P
-set_property  -dict {PACKAGE_PIN AH29   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n]       ; ## FMC_LPC_CLK1_M2C_N
-set_property  -dict {PACKAGE_PIN AD23   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p]        ; ## FMC_LPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN AE24   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n]        ; ## FMC_LPC_LA00_CC_N
-set_property  -dict {PACKAGE_PIN AD27   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]   ; ## FMC_LPC_LA18_CC_P
-set_property  -dict {PACKAGE_PIN AD28   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]   ; ## FMC_LPC_LA18_CC_N
-set_property  -dict {PACKAGE_PIN AD21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]   ; ## FMC_LPC_LA14_P
-set_property  -dict {PACKAGE_PIN AE21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]]   ; ## FMC_LPC_LA14_N
-set_property  -dict {PACKAGE_PIN AB24   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]]   ; ## FMC_LPC_LA13_P
-set_property  -dict {PACKAGE_PIN AC25   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]]   ; ## FMC_LPC_LA13_N
-set_property  -dict {PACKAGE_PIN AG20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]]   ; ## FMC_LPC_LA03_P
-set_property  -dict {PACKAGE_PIN AH20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]]   ; ## FMC_LPC_LA03_N
-set_property  -dict {PACKAGE_PIN AG22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]]   ; ## FMC_LPC_LA05_P
-set_property  -dict {PACKAGE_PIN AH22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]]   ; ## FMC_LPC_LA05_N
-set_property  -dict {PACKAGE_PIN AJ24   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]]   ; ## FMC_LPC_LA10_P
-set_property  -dict {PACKAGE_PIN AK25   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]]   ; ## FMC_LPC_LA10_N
-set_property  -dict {PACKAGE_PIN AA20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]]   ; ## FMC_LPC_LA12_P
-set_property  -dict {PACKAGE_PIN AB20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]]   ; ## FMC_LPC_LA12_N
-set_property  -dict {PACKAGE_PIN AG25   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]   ; ## FMC_LPC_LA07_P
-set_property  -dict {PACKAGE_PIN AH25   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]   ; ## FMC_LPC_LA07_N
-set_property  -dict {PACKAGE_PIN AF20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]]   ; ## FMC_LPC_LA02_P
-set_property  -dict {PACKAGE_PIN AF21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]]   ; ## FMC_LPC_LA02_N
-set_property  -dict {PACKAGE_PIN AH21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]]   ; ## FMC_LPC_LA04_P
-set_property  -dict {PACKAGE_PIN AJ21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]]   ; ## FMC_LPC_LA04_N
-set_property  -dict {PACKAGE_PIN AK23   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]]  ; ## FMC_LPC_LA09_P
-set_property  -dict {PACKAGE_PIN AK24   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]]  ; ## FMC_LPC_LA09_N
-set_property  -dict {PACKAGE_PIN AJ22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]]  ; ## FMC_LPC_LA08_P
-set_property  -dict {PACKAGE_PIN AJ23   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]]  ; ## FMC_LPC_LA08_N
-set_property  -dict {PACKAGE_PIN AK20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]]  ; ## FMC_LPC_LA06_P
-set_property  -dict {PACKAGE_PIN AK21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]]  ; ## FMC_LPC_LA06_N
-set_property  -dict {PACKAGE_PIN AE23   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]  ; ## FMC_LPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN AF23   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]  ; ## FMC_LPC_LA01_CC_N
-
-# clocks
-
-create_clock -name dac_clk_in   -period  2.00  [get_ports dac_clk_in_p]
-create_clock -name adc_clk_in   -period  4.00  [get_ports adc_clk_in_p]
diff --git a/projects/fmcomms1/kc705/system_project.tcl b/projects/fmcomms1/kc705/system_project.tcl
deleted file mode 100644
index 4e12b6de1..000000000
--- a/projects/fmcomms1/kc705/system_project.tcl
+++ /dev/null
@@ -1,19 +0,0 @@
-
-source ../../scripts/adi_env.tcl
-source $ad_hdl_dir/projects/scripts/adi_project.tcl
-source $ad_hdl_dir/projects/scripts/adi_board.tcl
-
-adi_project_create fmcomms1_kc705
-adi_project_files fmcomms1_kc705 [list \
-  "system_top.v" \
-  "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-set_property is_enabled false [get_files  *system_axi*_spi*.xdc]
-
-adi_project_run fmcomms1_kc705
-
-
diff --git a/projects/fmcomms1/kc705/system_top.v b/projects/fmcomms1/kc705/system_top.v
deleted file mode 100644
index b0a73e89c..000000000
--- a/projects/fmcomms1/kc705/system_top.v
+++ /dev/null
@@ -1,316 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module system_top (
-
-  sys_rst,
-  sys_clk_p,
-  sys_clk_n,
-
-  uart_sin,
-  uart_sout,
-
-  ddr3_1_n,
-  ddr3_1_p,
-  ddr3_reset_n,
-  ddr3_addr,
-  ddr3_ba,
-  ddr3_cas_n,
-  ddr3_ras_n,
-  ddr3_we_n,
-  ddr3_ck_n,
-  ddr3_ck_p,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_dm,
-  ddr3_dq,
-  ddr3_dqs_n,
-  ddr3_dqs_p,
-  ddr3_odt,
-
-  mdio_mdc,
-  mdio_mdio,
-  mii_rst_n,
-  mii_col,
-  mii_crs,
-  mii_rx_clk,
-  mii_rx_er,
-  mii_rx_dv,
-  mii_rxd,
-  mii_tx_clk,
-  mii_tx_en,
-  mii_txd,
-
-  linear_flash_addr,
-  linear_flash_adv_ldn,
-  linear_flash_ce_n,
-  linear_flash_dq_io,
-  linear_flash_oen,
-  linear_flash_wen,
-
-  fan_pwm,
-
-  gpio_lcd,
-  gpio_bd,
-
-  iic_rstn,
-  iic_scl,
-  iic_sda,
-
-  dac_clk_in_p,
-  dac_clk_in_n,
-  dac_clk_out_p,
-  dac_clk_out_n,
-  dac_frame_out_p,
-  dac_frame_out_n,
-  dac_data_out_p,
-  dac_data_out_n,
-
-  adc_clk_in_p,
-  adc_clk_in_n,
-  adc_or_in_p,
-  adc_or_in_n,
-  adc_data_in_p,
-  adc_data_in_n,
-
-  ref_clk_out_p,
-  ref_clk_out_n);
-
-  input           sys_rst;
-  input           sys_clk_p;
-  input           sys_clk_n;
-
-  input           uart_sin;
-  output          uart_sout;
-
-  output  [ 2:0]  ddr3_1_n;
-  output  [ 1:0]  ddr3_1_p;
-  output          ddr3_reset_n;
-  output  [13:0]  ddr3_addr;
-  output  [ 2:0]  ddr3_ba;
-  output          ddr3_cas_n;
-  output          ddr3_ras_n;
-  output          ddr3_we_n;
-  output  [ 0:0]  ddr3_ck_n;
-  output  [ 0:0]  ddr3_ck_p;
-  output  [ 0:0]  ddr3_cke;
-  output  [ 0:0]  ddr3_cs_n;
-  output  [ 7:0]  ddr3_dm;
-  inout   [63:0]  ddr3_dq;
-  inout   [ 7:0]  ddr3_dqs_n;
-  inout   [ 7:0]  ddr3_dqs_p;
-  output  [ 0:0]  ddr3_odt;
-
-  output          mdio_mdc;
-  inout           mdio_mdio;
-  output          mii_rst_n;
-  input           mii_col;
-  input           mii_crs;
-  input           mii_rx_clk;
-  input           mii_rx_er;
-  input           mii_rx_dv;
-  input   [ 3:0]  mii_rxd;
-  input           mii_tx_clk;
-  output          mii_tx_en;
-  output  [ 3:0]  mii_txd;
-
-  output [26:1]  linear_flash_addr;
-  output         linear_flash_adv_ldn;
-  output         linear_flash_ce_n;
-  inout   [15:0] linear_flash_dq_io;
-  output         linear_flash_oen;
-  output         linear_flash_wen;
-
-  output          fan_pwm;
-
-  inout   [ 6:0]  gpio_lcd;
-  inout   [16:0]  gpio_bd;
-
-  output          iic_rstn;
-  inout           iic_scl;
-  inout           iic_sda;
-
-  input           dac_clk_in_p;
-  input           dac_clk_in_n;
-  output          dac_clk_out_p;
-  output          dac_clk_out_n;
-  output          dac_frame_out_p;
-  output          dac_frame_out_n;
-  output   [15:0] dac_data_out_p;
-  output   [15:0] dac_data_out_n;
-
-  input           adc_clk_in_p;
-  input           adc_clk_in_n;
-  input           adc_or_in_p;
-  input           adc_or_in_n;
-  input   [13:0]  adc_data_in_p;
-  input   [13:0]  adc_data_in_n;
-
-  output          ref_clk_out_p;
-  output          ref_clk_out_n;
-
-  // internal signals
-
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire    [ 7:0]  spi_csn;
-  wire            spi_clk;
-  wire            spi_mosi;
-  wire            spi_miso;
-  wire            ref_clk;
-  wire            oddr_ref_clk;
-
-  // default logic
-
-  assign ddr3_1_p = 2'b11;
-  assign ddr3_1_n = 3'b000;
-  assign fan_pwm = 1'b1;
-  assign iic_rstn = 1'b1;
-
-  // instantiations
-
-   ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_oddr_ref_clk (
-    .S (1'b0),
-    .CE (1'b1),
-    .R (1'b0),
-    .C (ref_clk),
-    .D1 (1'b1),
-    .D2 (1'b0),
-    .Q (oddr_ref_clk));
-
-  OBUFDS i_obufds_ref_clk (
-    .I (oddr_ref_clk),
-    .O (ref_clk_out_p),
-    .OB (ref_clk_out_n));
-
-  ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
-    .dio_t (gpio_t[16:0]),
-    .dio_i (gpio_o[16:0]),
-    .dio_o (gpio_i[16:0]),
-    .dio_p (gpio_bd));
-
-  system_wrapper i_system_wrapper (
-    .ddr3_addr (ddr3_addr),
-    .ddr3_ba (ddr3_ba),
-    .ddr3_cas_n (ddr3_cas_n),
-    .ddr3_ck_n (ddr3_ck_n),
-    .ddr3_ck_p (ddr3_ck_p),
-    .ddr3_cke (ddr3_cke),
-    .ddr3_cs_n (ddr3_cs_n),
-    .ddr3_dm (ddr3_dm),
-    .ddr3_dq (ddr3_dq),
-    .ddr3_dqs_n (ddr3_dqs_n),
-    .ddr3_dqs_p (ddr3_dqs_p),
-    .ddr3_odt (ddr3_odt),
-    .ddr3_ras_n (ddr3_ras_n),
-    .ddr3_reset_n (ddr3_reset_n),
-    .ddr3_we_n (ddr3_we_n),
-    .gpio0_i (gpio_i[31:0]),
-    .gpio0_o (gpio_o[31:0]),
-    .gpio0_t (gpio_t[31:0]),
-    .gpio1_i (gpio_i[63:32]),
-    .gpio1_o (gpio_o[63:32]),
-    .gpio1_t (gpio_t[63:32]),
-    .gpio_lcd_tri_io (gpio_lcd),
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .adc_or_in_n (adc_or_in_n),
-    .adc_or_in_p (adc_or_in_p),
-    .dac_clk_in_n (dac_clk_in_n),
-    .dac_clk_in_p (dac_clk_in_p),
-    .dac_clk_out_n (dac_clk_out_n),
-    .dac_clk_out_p (dac_clk_out_p),
-    .dac_data_out_n (dac_data_out_n),
-    .dac_data_out_p (dac_data_out_p),
-    .dac_frame_out_n (dac_frame_out_n),
-    .dac_frame_out_p (dac_frame_out_p),
-    .ref_clk (ref_clk),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
-    .mb_intr_02 (1'd0),
-    .mb_intr_03 (1'd0),
-    .mb_intr_06 (1'd0),
-    .mb_intr_07 (1'd0),
-    .mb_intr_08 (1'd0),
-    .mb_intr_14 (1'd0),
-    .mb_intr_15 (1'd0),
-    .mdio_mdc (mdio_mdc),
-    .mdio_mdio_io (mdio_mdio),
-    .mii_col (mii_col),
-    .mii_crs (mii_crs),
-    .mii_rst_n (mii_rst_n),
-    .mii_rx_clk (mii_rx_clk),
-    .mii_rx_dv (mii_rx_dv),
-    .mii_rx_er (mii_rx_er),
-    .mii_rxd (mii_rxd),
-    .mii_tx_clk (mii_tx_clk),
-    .mii_tx_en (mii_tx_en),
-    .mii_txd (mii_txd),
-    .linear_flash_addr (linear_flash_addr),
-    .linear_flash_adv_ldn (linear_flash_adv_ldn),
-    .linear_flash_ce_n (linear_flash_ce_n),
-    .linear_flash_dq_io (linear_flash_dq_io),
-    .linear_flash_oen (linear_flash_oen),
-    .linear_flash_wen (linear_flash_wen),
-    .spi_clk_i (spi_clk),
-    .spi_clk_o (spi_clk),
-    .spi_csn_i (spi_csn),
-    .spi_csn_o (spi_csn),
-    .spi_sdi_i (spi_miso),
-    .spi_sdo_i (spi_mosi),
-    .spi_sdo_o (spi_mosi),
-    .sys_clk_n (sys_clk_n),
-    .sys_clk_p (sys_clk_p),
-    .sys_rst (sys_rst),
-    .uart_sin (uart_sin),
-    .uart_sout (uart_sout));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/projects/fmcomms1/vc707/Makefile b/projects/fmcomms1/vc707/Makefile
deleted file mode 100644
index b1648171d..000000000
--- a/projects/fmcomms1/vc707/Makefile
+++ /dev/null
@@ -1,76 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../common/fmcomms1_bd.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/vc707/vc707_system_mig.prj
-M_DEPS += ../../common/vc707/vc707_system_constr.xdc
-M_DEPS += ../../common/vc707/vc707_system_bd.tcl
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
-M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
-M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_upack/util_upack.xpr
-M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib fmcomms1_vc707.sdk/system_top.hdf
-
-
-clean: 
-	rm -rf $(M_FLIST)
-
-
-clean-all:clean
-	make -C ../../../library/axi_ad9122 clean
-	make -C ../../../library/axi_ad9643 clean
-	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_upack clean
-	make -C ../../../library/util_wfifo clean
-
-
-fmcomms1_vc707.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms1_vc707_vivado.log 2>&1
-
-
-lib:
-	make -C ../../../library/axi_ad9122
-	make -C ../../../library/axi_ad9643
-	make -C ../../../library/axi_dmac
-	make -C ../../../library/util_cpack
-	make -C ../../../library/util_upack
-	make -C ../../../library/util_wfifo
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms1/vc707/system_bd.tcl b/projects/fmcomms1/vc707/system_bd.tcl
deleted file mode 100644
index 4fd21b543..000000000
--- a/projects/fmcomms1/vc707/system_bd.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-
-  source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
-  source ../common/fmcomms1_bd.tcl
-
diff --git a/projects/fmcomms1/vc707/system_constr.xdc b/projects/fmcomms1/vc707/system_constr.xdc
deleted file mode 100644
index 083d2f1a1..000000000
--- a/projects/fmcomms1/vc707/system_constr.xdc
+++ /dev/null
@@ -1,86 +0,0 @@
-
-# reference
-
-set_property  -dict {PACKAGE_PIN U37    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_p]      ; ## FMC_LPC_LA17_CC_P
-set_property  -dict {PACKAGE_PIN U38    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_n]      ; ## FMC_LPC_LA17_CC_N
-
-# dac 
-
-set_property  -dict {PACKAGE_PIN AF39   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_p]       ; ## FMC_LPC_CLK0_M2C_P
-set_property  -dict {PACKAGE_PIN AF40   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_n]       ; ## FMC_LPC_CLK0_M2C_N
-set_property  -dict {PACKAGE_PIN P35    IOSTANDARD LVDS} [get_ports dac_clk_out_p]                     ; ## FMC_LPC_LA21_P
-set_property  -dict {PACKAGE_PIN P36    IOSTANDARD LVDS} [get_ports dac_clk_out_n]                     ; ## FMC_LPC_LA21_N
-set_property  -dict {PACKAGE_PIN Y42    IOSTANDARD LVDS} [get_ports dac_frame_out_p]                   ; ## FMC_LPC_LA11_P
-set_property  -dict {PACKAGE_PIN AA42   IOSTANDARD LVDS} [get_ports dac_frame_out_n]                   ; ## FMC_LPC_LA11_N
-set_property  -dict {PACKAGE_PIN P37    IOSTANDARD LVDS} [get_ports dac_data_out_p[0]]                 ; ## FMC_LPC_LA32_P
-set_property  -dict {PACKAGE_PIN P38    IOSTANDARD LVDS} [get_ports dac_data_out_n[0]]                ; ## FMC_LPC_LA32_N
-set_property  -dict {PACKAGE_PIN T36    IOSTANDARD LVDS} [get_ports dac_data_out_p[1]]                 ; ## FMC_LPC_LA33_P
-set_property  -dict {PACKAGE_PIN R37    IOSTANDARD LVDS} [get_ports dac_data_out_n[1]]                 ; ## FMC_LPC_LA33_N
-set_property  -dict {PACKAGE_PIN T32    IOSTANDARD LVDS} [get_ports dac_data_out_p[2]]                 ; ## FMC_LPC_LA30_P
-set_property  -dict {PACKAGE_PIN R32    IOSTANDARD LVDS} [get_ports dac_data_out_n[2]]                 ; ## FMC_LPC_LA30_N
-set_property  -dict {PACKAGE_PIN V35    IOSTANDARD LVDS} [get_ports dac_data_out_p[3]]                 ; ## FMC_LPC_LA28_P
-set_property  -dict {PACKAGE_PIN V36    IOSTANDARD LVDS} [get_ports dac_data_out_n[3]]                 ; ## FMC_LPC_LA28_N
-set_property  -dict {PACKAGE_PIN V39    IOSTANDARD LVDS} [get_ports dac_data_out_p[4]]                 ; ## FMC_LPC_LA31_P
-set_property  -dict {PACKAGE_PIN V40    IOSTANDARD LVDS} [get_ports dac_data_out_n[4]]                 ; ## FMC_LPC_LA31_N
-set_property  -dict {PACKAGE_PIN W36    IOSTANDARD LVDS} [get_ports dac_data_out_p[5]]                 ; ## FMC_LPC_LA29_P
-set_property  -dict {PACKAGE_PIN W37    IOSTANDARD LVDS} [get_ports dac_data_out_n[5]]                 ; ## FMC_LPC_LA29_N
-set_property  -dict {PACKAGE_PIN U34    IOSTANDARD LVDS} [get_ports dac_data_out_p[6]]                 ; ## FMC_LPC_LA24_P
-set_property  -dict {PACKAGE_PIN T35    IOSTANDARD LVDS} [get_ports dac_data_out_n[6]]                 ; ## FMC_LPC_LA24_N
-set_property  -dict {PACKAGE_PIN R33    IOSTANDARD LVDS} [get_ports dac_data_out_p[7]]                 ; ## FMC_LPC_LA25_P
-set_property  -dict {PACKAGE_PIN R34    IOSTANDARD LVDS} [get_ports dac_data_out_n[7]]                 ; ## FMC_LPC_LA25_N
-set_property  -dict {PACKAGE_PIN W32    IOSTANDARD LVDS} [get_ports dac_data_out_p[8]]                 ; ## FMC_LPC_LA22_P
-set_property  -dict {PACKAGE_PIN W33    IOSTANDARD LVDS} [get_ports dac_data_out_n[8]]                 ; ## FMC_LPC_LA22_N
-set_property  -dict {PACKAGE_PIN P32    IOSTANDARD LVDS} [get_ports dac_data_out_p[9]]                 ; ## FMC_LPC_LA27_P
-set_property  -dict {PACKAGE_PIN P33    IOSTANDARD LVDS} [get_ports dac_data_out_n[9]]                 ; ## FMC_LPC_LA27_N
-set_property  -dict {PACKAGE_PIN N33    IOSTANDARD LVDS} [get_ports dac_data_out_p[10]]                ; ## FMC_LPC_LA26_P
-set_property  -dict {PACKAGE_PIN N34    IOSTANDARD LVDS} [get_ports dac_data_out_n[10]]                ; ## FMC_LPC_LA26_N
-set_property  -dict {PACKAGE_PIN R38    IOSTANDARD LVDS} [get_ports dac_data_out_p[11]]                ; ## FMC_LPC_LA23_P
-set_property  -dict {PACKAGE_PIN R39    IOSTANDARD LVDS} [get_ports dac_data_out_n[11]]                ; ## FMC_LPC_LA23_N
-set_property  -dict {PACKAGE_PIN U32    IOSTANDARD LVDS} [get_ports dac_data_out_p[12]]                ; ## FMC_LPC_LA19_P
-set_property  -dict {PACKAGE_PIN U33    IOSTANDARD LVDS} [get_ports dac_data_out_n[12]]                ; ## FMC_LPC_LA19_N
-set_property  -dict {PACKAGE_PIN V33    IOSTANDARD LVDS} [get_ports dac_data_out_p[13]]                ; ## FMC_LPC_LA20_P
-set_property  -dict {PACKAGE_PIN V34    IOSTANDARD LVDS} [get_ports dac_data_out_n[13]]                ; ## FMC_LPC_LA20_N
-set_property  -dict {PACKAGE_PIN AC38   IOSTANDARD LVDS} [get_ports dac_data_out_p[14]]                ; ## FMC_LPC_LA15_P
-set_property  -dict {PACKAGE_PIN AC39   IOSTANDARD LVDS} [get_ports dac_data_out_n[14]]                ; ## FMC_LPC_LA15_N
-set_property  -dict {PACKAGE_PIN AJ40   IOSTANDARD LVDS} [get_ports dac_data_out_p[15]]                ; ## FMC_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN AJ41   IOSTANDARD LVDS} [get_ports dac_data_out_n[15]]                ; ## FMC_LPC_LA16_N
-
-# adc 
-
-set_property  -dict {PACKAGE_PIN U39    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_p]       ; ## FMC_LPC_CLK1_M2C_P
-set_property  -dict {PACKAGE_PIN T39    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_n]       ; ## FMC_LPC_CLK1_M2C_N
-set_property  -dict {PACKAGE_PIN AD40   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_p]        ; ## FMC_LPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN AD41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_n]        ; ## FMC_LPC_LA00_CC_N
-set_property  -dict {PACKAGE_PIN U36    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]   ; ## FMC_LPC_LA18_CC_P
-set_property  -dict {PACKAGE_PIN T37    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]   ; ## FMC_LPC_LA18_CC_N
-set_property  -dict {PACKAGE_PIN AB38   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]   ; ## FMC_LPC_LA14_P
-set_property  -dict {PACKAGE_PIN AB39   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[1]]   ; ## FMC_LPC_LA14_N
-set_property  -dict {PACKAGE_PIN W40    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[2]]   ; ## FMC_LPC_LA13_P
-set_property  -dict {PACKAGE_PIN Y40    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[2]]   ; ## FMC_LPC_LA13_N
-set_property  -dict {PACKAGE_PIN AJ42   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[3]]   ; ## FMC_LPC_LA03_P
-set_property  -dict {PACKAGE_PIN AK42   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[3]]   ; ## FMC_LPC_LA03_N
-set_property  -dict {PACKAGE_PIN AF42   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[4]]   ; ## FMC_LPC_LA05_P
-set_property  -dict {PACKAGE_PIN AG42   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[4]]   ; ## FMC_LPC_LA05_N
-set_property  -dict {PACKAGE_PIN AB41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[5]]   ; ## FMC_LPC_LA10_P
-set_property  -dict {PACKAGE_PIN AB42   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[5]]   ; ## FMC_LPC_LA10_N
-set_property  -dict {PACKAGE_PIN Y39    IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[6]]   ; ## FMC_LPC_LA12_P
-set_property  -dict {PACKAGE_PIN AA39   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[6]]   ; ## FMC_LPC_LA12_N
-set_property  -dict {PACKAGE_PIN AC40   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]   ; ## FMC_LPC_LA07_P
-set_property  -dict {PACKAGE_PIN AC41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]   ; ## FMC_LPC_LA07_N
-set_property  -dict {PACKAGE_PIN AK39   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[8]]   ; ## FMC_LPC_LA02_P
-set_property  -dict {PACKAGE_PIN AL39   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[8]]   ; ## FMC_LPC_LA02_N
-set_property  -dict {PACKAGE_PIN AL41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[9]]   ; ## FMC_LPC_LA04_P
-set_property  -dict {PACKAGE_PIN AL42   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[9]]   ; ## FMC_LPC_LA04_N
-set_property  -dict {PACKAGE_PIN AJ38   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[10]]  ; ## FMC_LPC_LA09_P
-set_property  -dict {PACKAGE_PIN AK38   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[10]]  ; ## FMC_LPC_LA09_N
-set_property  -dict {PACKAGE_PIN AD42   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[11]]  ; ## FMC_LPC_LA08_P
-set_property  -dict {PACKAGE_PIN AE42   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[11]]  ; ## FMC_LPC_LA08_N
-set_property  -dict {PACKAGE_PIN AD38   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[12]]  ; ## FMC_LPC_LA06_P
-set_property  -dict {PACKAGE_PIN AE38   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[12]]  ; ## FMC_LPC_LA06_N
-set_property  -dict {PACKAGE_PIN AF41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]  ; ## FMC_LPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN AG41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]  ; ## FMC_LPC_LA01_CC_N
-
-# clocks
-
-create_clock -name dac_clk_in   -period  2.00  [get_ports dac_clk_in_p]
-create_clock -name adc_clk_in   -period  4.00  [get_ports adc_clk_in_p]
diff --git a/projects/fmcomms1/vc707/system_project.tcl b/projects/fmcomms1/vc707/system_project.tcl
deleted file mode 100644
index 4ab9b41b3..000000000
--- a/projects/fmcomms1/vc707/system_project.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-
-source ../../scripts/adi_env.tcl
-source $ad_hdl_dir/projects/scripts/adi_project.tcl
-source $ad_hdl_dir/projects/scripts/adi_board.tcl
-
-adi_project_create fmcomms1_vc707
-adi_project_files fmcomms1_vc707 [list \
-  "system_top.v" \
-  "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run fmcomms1_vc707
-
-
diff --git a/projects/fmcomms1/vc707/system_top.v b/projects/fmcomms1/vc707/system_top.v
deleted file mode 100644
index 23d006bfe..000000000
--- a/projects/fmcomms1/vc707/system_top.v
+++ /dev/null
@@ -1,302 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module system_top (
-
-  sys_rst,
-  sys_clk_p,
-  sys_clk_n,
-
-  uart_sin,
-  uart_sout,
-
-  ddr3_addr,
-  ddr3_ba,
-  ddr3_cas_n,
-  ddr3_ck_n,
-  ddr3_ck_p,
-  ddr3_cke,
-  ddr3_cs_n,
-  ddr3_dm,
-  ddr3_dq,
-  ddr3_dqs_n,
-  ddr3_dqs_p,
-  ddr3_odt,
-  ddr3_ras_n,
-  ddr3_reset_n,
-  ddr3_we_n,
-
-  sgmii_rxp,
-  sgmii_rxn,
-  sgmii_txp,
-  sgmii_txn,
-
-  phy_rstn,
-  mgt_clk_p,
-  mgt_clk_n,
-  mdio_mdc,
-  mdio_mdio,
-
-  fan_pwm,
-
-  linear_flash_addr,
-  linear_flash_adv_ldn,
-  linear_flash_ce_n,
-  linear_flash_oen,
-  linear_flash_wen,
-  linear_flash_dq_io,
-
-  gpio_lcd,
-  gpio_bd,
-
-  iic_rstn,
-  iic_scl,
-  iic_sda,
-
-  dac_clk_in_p,
-  dac_clk_in_n,
-  dac_clk_out_p,
-  dac_clk_out_n,
-  dac_frame_out_p,
-  dac_frame_out_n,
-  dac_data_out_p,
-  dac_data_out_n,
-
-  adc_clk_in_p,
-  adc_clk_in_n,
-  adc_or_in_p,
-  adc_or_in_n,
-  adc_data_in_p,
-  adc_data_in_n,
-
-  ref_clk_out_p,
-  ref_clk_out_n );
-
-  input           sys_rst;
-  input           sys_clk_p;
-  input           sys_clk_n;
-
-  input           uart_sin;
-  output          uart_sout;
-
-  output  [13:0]  ddr3_addr;
-  output  [ 2:0]  ddr3_ba;
-  output          ddr3_cas_n;
-  output  [ 0:0]  ddr3_ck_n;
-  output  [ 0:0]  ddr3_ck_p;
-  output  [ 0:0]  ddr3_cke;
-  output  [ 0:0]  ddr3_cs_n;
-  output  [ 7:0]  ddr3_dm;
-  inout   [63:0]  ddr3_dq;
-  inout   [ 7:0]  ddr3_dqs_n;
-  inout   [ 7:0]  ddr3_dqs_p;
-  output  [ 0:0]  ddr3_odt;
-  output          ddr3_ras_n;
-  output          ddr3_reset_n;
-  output          ddr3_we_n;
-
-  input           sgmii_rxp;
-  input           sgmii_rxn;
-  output          sgmii_txp;
-  output          sgmii_txn;
-
-  output          phy_rstn;
-  input           mgt_clk_p;
-  input           mgt_clk_n;
-  output          mdio_mdc;
-  inout           mdio_mdio;
-
-  output          fan_pwm;
-
-  output  [26:1]  linear_flash_addr;
-  output          linear_flash_adv_ldn;
-  output          linear_flash_ce_n;
-  output          linear_flash_oen;
-  output          linear_flash_wen;
-  inout   [15:0]  linear_flash_dq_io;
-
-  inout   [ 6:0]  gpio_lcd;
-  inout   [20:0]  gpio_bd;
-
-  output          iic_rstn;
-  inout           iic_scl;
-  inout           iic_sda;
-
-  input           dac_clk_in_p;
-  input           dac_clk_in_n;
-  output          dac_clk_out_p;
-  output          dac_clk_out_n;
-  output          dac_frame_out_p;
-  output          dac_frame_out_n;
-  output   [15:0] dac_data_out_p;
-  output   [15:0] dac_data_out_n;
-
-  input           adc_clk_in_p;
-  input           adc_clk_in_n;
-  input           adc_or_in_p;
-  input           adc_or_in_n;
-  input   [13:0]  adc_data_in_p;
-  input   [13:0]  adc_data_in_n;
-
-  output          ref_clk_out_p;
-  output          ref_clk_out_n;
-
-  // internal signals
-
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire    [ 7:0]  spi_csn;
-  wire            spi_clk;
-  wire            spi_mosi;
-  wire            spi_miso;
-  wire            ref_clk;
-  wire            oddr_ref_clk;
-
-  // assignments
-
-  assign fan_pwm  = 1'b1;
-  assign iic_rstn = 1'b1;
-
-  // instantiations
-
-  ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_oddr_ref_clk (
-    .S (1'b0),
-    .CE (1'b1),
-    .R (1'b0),
-    .C (ref_clk),
-    .D1 (1'b1),
-    .D2 (1'b0),
-    .Q (oddr_ref_clk));
-
-  OBUFDS i_obufds_ref_clk (
-    .I (oddr_ref_clk),
-    .O (ref_clk_out_p),
-    .OB (ref_clk_out_n));
-
-  ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
-    .dio_t (gpio_t[20:0]),
-    .dio_i (gpio_o[20:0]),
-    .dio_o (gpio_i[20:0]),
-    .dio_p (gpio_bd));
-
-  system_wrapper i_system_wrapper (
-    .ddr3_addr (ddr3_addr),
-    .ddr3_ba (ddr3_ba),
-    .ddr3_cas_n (ddr3_cas_n),
-    .ddr3_ck_n (ddr3_ck_n),
-    .ddr3_ck_p (ddr3_ck_p),
-    .ddr3_cke (ddr3_cke),
-    .ddr3_cs_n (ddr3_cs_n),
-    .ddr3_dm (ddr3_dm),
-    .ddr3_dq (ddr3_dq),
-    .ddr3_dqs_n (ddr3_dqs_n),
-    .ddr3_dqs_p (ddr3_dqs_p),
-    .ddr3_odt (ddr3_odt),
-    .ddr3_ras_n (ddr3_ras_n),
-    .ddr3_reset_n (ddr3_reset_n),
-    .ddr3_we_n (ddr3_we_n),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
-    .linear_flash_addr (linear_flash_addr),
-    .linear_flash_adv_ldn (linear_flash_adv_ldn),
-    .linear_flash_ce_n (linear_flash_ce_n),
-    .linear_flash_oen (linear_flash_oen),
-    .linear_flash_wen (linear_flash_wen),
-    .linear_flash_dq_io(linear_flash_dq_io),
-    .gpio0_i (gpio_i[31:0]),
-    .gpio0_o (gpio_o[31:0]),
-    .gpio0_t (gpio_t[31:0]),
-    .gpio1_i (gpio_i[63:32]),
-    .gpio1_o (gpio_o[63:32]),
-    .gpio1_t (gpio_t[63:32]),
-    .gpio_lcd_tri_io (gpio_lcd),
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .adc_or_in_n (adc_or_in_n),
-    .adc_or_in_p (adc_or_in_p),
-    .dac_clk_in_n (dac_clk_in_n),
-    .dac_clk_in_p (dac_clk_in_p),
-    .dac_clk_out_n (dac_clk_out_n),
-    .dac_clk_out_p (dac_clk_out_p),
-    .dac_data_out_n (dac_data_out_n),
-    .dac_data_out_p (dac_data_out_p),
-    .dac_frame_out_n (dac_frame_out_n),
-    .dac_frame_out_p (dac_frame_out_p),
-    .ref_clk (ref_clk),
-    .mb_intr_06 (1'b0),
-    .mb_intr_07 (1'b0),
-    .mb_intr_08 (1'b0),
-    .mb_intr_14 (1'b0),
-    .mb_intr_15 (1'b0),
-    .mdio_mdc (mdio_mdc),
-    .mdio_mdio_io (mdio_mdio),
-    .mgt_clk_clk_n (mgt_clk_n),
-    .mgt_clk_clk_p (mgt_clk_p),
-    .phy_rstn (phy_rstn),
-    .phy_sd (1'b1),
-    .sgmii_rxn (sgmii_rxn),
-    .sgmii_rxp (sgmii_rxp),
-    .sgmii_txn (sgmii_txn),
-    .sgmii_txp (sgmii_txp),
-    .spi_clk_i (1'b0),
-    .spi_clk_o (spi_clk),
-    .spi_csn_i (8'hff),
-    .spi_csn_o (spi_csn),
-    .spi_sdi_i (spi_miso),
-    .spi_sdo_i (1'b0),
-    .spi_sdo_o (spi_mosi),
-    .sys_clk_n (sys_clk_n),
-    .sys_clk_p (sys_clk_p),
-    .sys_rst (sys_rst),
-    .uart_sin (uart_sin),
-    .uart_sout (uart_sout));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/projects/fmcomms1/zc702/Makefile b/projects/fmcomms1/zc702/Makefile
deleted file mode 100644
index e6e0c6fa5..000000000
--- a/projects/fmcomms1/zc702/Makefile
+++ /dev/null
@@ -1,84 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../common/fmcomms1_bd.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc702/zc702_system_constr.xdc
-M_DEPS += ../../common/zc702/zc702_system_bd.tcl
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
-M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
-M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_upack/util_upack.xpr
-M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib fmcomms1_zc702.sdk/system_top.hdf
-
-
-clean: 
-	rm -rf $(M_FLIST)
-
-
-clean-all:clean
-	make -C ../../../library/axi_ad9122 clean
-	make -C ../../../library/axi_ad9643 clean
-	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_upack clean
-	make -C ../../../library/util_wfifo clean
-
-
-fmcomms1_zc702.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms1_zc702_vivado.log 2>&1
-
-
-lib:
-	make -C ../../../library/axi_ad9122
-	make -C ../../../library/axi_ad9643
-	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_cpack
-	make -C ../../../library/util_upack
-	make -C ../../../library/util_wfifo
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms1/zc702/system_bd.tcl b/projects/fmcomms1/zc702/system_bd.tcl
deleted file mode 100644
index 053c55f62..000000000
--- a/projects/fmcomms1/zc702/system_bd.tcl
+++ /dev/null
@@ -1,5 +0,0 @@
-
-  source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
-  source ../common/fmcomms1_bd.tcl
-
-
diff --git a/projects/fmcomms1/zc702/system_constr.xdc b/projects/fmcomms1/zc702/system_constr.xdc
deleted file mode 100644
index 594ec0d6a..000000000
--- a/projects/fmcomms1/zc702/system_constr.xdc
+++ /dev/null
@@ -1,86 +0,0 @@
-
-# reference
-
-set_property  -dict {PACKAGE_PIN B19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p]       ; ## FMC1_LPC_LA17_CC_P
-set_property  -dict {PACKAGE_PIN B20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n]       ; ## FMC1_LPC_LA17_CC_N
-
-# dac 
-
-set_property  -dict {PACKAGE_PIN L18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p]        ; ## FMC1_LPC_CLK0_M2C_P
-set_property  -dict {PACKAGE_PIN L19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n]        ; ## FMC1_LPC_CLK0_M2C_N
-set_property  -dict {PACKAGE_PIN F21   IOSTANDARD LVDS_25} [get_ports dac_clk_out_p]                      ; ## FMC1_LPC_LA21_P
-set_property  -dict {PACKAGE_PIN F22   IOSTANDARD LVDS_25} [get_ports dac_clk_out_n]                      ; ## FMC1_LPC_LA21_N
-set_property  -dict {PACKAGE_PIN R20   IOSTANDARD LVDS_25} [get_ports dac_frame_out_p]                    ; ## FMC1_LPC_LA11_P
-set_property  -dict {PACKAGE_PIN R21   IOSTANDARD LVDS_25} [get_ports dac_frame_out_n]                    ; ## FMC1_LPC_LA11_N
-set_property  -dict {PACKAGE_PIN B21   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]]                  ; ## FMC1_LPC_LA32_P
-set_property  -dict {PACKAGE_PIN B22   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]]                  ; ## FMC1_LPC_LA32_N
-set_property  -dict {PACKAGE_PIN A18   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]]                  ; ## FMC1_LPC_LA33_P
-set_property  -dict {PACKAGE_PIN A19   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]]                  ; ## FMC1_LPC_LA33_N
-set_property  -dict {PACKAGE_PIN E21   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]]                  ; ## FMC1_LPC_LA30_P
-set_property  -dict {PACKAGE_PIN D21   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]]                  ; ## FMC1_LPC_LA30_N
-set_property  -dict {PACKAGE_PIN D22   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]]                  ; ## FMC1_LPC_LA28_P
-set_property  -dict {PACKAGE_PIN C22   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]]                  ; ## FMC1_LPC_LA28_N
-set_property  -dict {PACKAGE_PIN A16   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]]                  ; ## FMC1_LPC_LA31_P
-set_property  -dict {PACKAGE_PIN A17   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]]                  ; ## FMC1_LPC_LA31_N
-set_property  -dict {PACKAGE_PIN B16   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]]                  ; ## FMC1_LPC_LA29_P
-set_property  -dict {PACKAGE_PIN B17   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]]                  ; ## FMC1_LPC_LA29_N
-set_property  -dict {PACKAGE_PIN A21   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]]                  ; ## FMC1_LPC_LA24_P
-set_property  -dict {PACKAGE_PIN A22   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]]                  ; ## FMC1_LPC_LA24_N
-set_property  -dict {PACKAGE_PIN C15   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]]                  ; ## FMC1_LPC_LA25_P
-set_property  -dict {PACKAGE_PIN B15   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]]                  ; ## FMC1_LPC_LA25_N
-set_property  -dict {PACKAGE_PIN G17   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]]                  ; ## FMC1_LPC_LA22_P
-set_property  -dict {PACKAGE_PIN F17   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]]                  ; ## FMC1_LPC_LA22_N
-set_property  -dict {PACKAGE_PIN C17   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]]                  ; ## FMC1_LPC_LA27_P
-set_property  -dict {PACKAGE_PIN C18   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]]                  ; ## FMC1_LPC_LA27_N
-set_property  -dict {PACKAGE_PIN F18   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]]                 ; ## FMC1_LPC_LA26_P
-set_property  -dict {PACKAGE_PIN E18   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]]                 ; ## FMC1_LPC_LA26_N
-set_property  -dict {PACKAGE_PIN G15   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]]                 ; ## FMC1_LPC_LA23_P
-set_property  -dict {PACKAGE_PIN G16   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]]                 ; ## FMC1_LPC_LA23_N
-set_property  -dict {PACKAGE_PIN E19   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]]                 ; ## FMC1_LPC_LA19_P
-set_property  -dict {PACKAGE_PIN E20   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]]                 ; ## FMC1_LPC_LA19_N
-set_property  -dict {PACKAGE_PIN G20   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]]                 ; ## FMC1_LPC_LA20_P
-set_property  -dict {PACKAGE_PIN G21   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]]                 ; ## FMC1_LPC_LA20_N
-set_property  -dict {PACKAGE_PIN P20   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]]                 ; ## FMC1_LPC_LA15_P
-set_property  -dict {PACKAGE_PIN P21   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]]                 ; ## FMC1_LPC_LA15_N
-set_property  -dict {PACKAGE_PIN N15   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]]                 ; ## FMC1_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN P15   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]]                 ; ## FMC1_LPC_LA16_N
-
-# adc 
-
-set_property  -dict {PACKAGE_PIN M19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p]        ; ## FMC1_LPC_CLK1_M2C_P
-set_property  -dict {PACKAGE_PIN M20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n]        ; ## FMC1_LPC_CLK1_M2C_N
-set_property  -dict {PACKAGE_PIN K19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p]         ; ## FMC1_LPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN K20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n]         ; ## FMC1_LPC_LA00_CC_N
-set_property  -dict {PACKAGE_PIN D20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]    ; ## FMC1_LPC_LA18_CC_P
-set_property  -dict {PACKAGE_PIN C20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]    ; ## FMC1_LPC_LA18_CC_N
-set_property  -dict {PACKAGE_PIN J16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]    ; ## FMC1_LPC_LA14_P
-set_property  -dict {PACKAGE_PIN J17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]]    ; ## FMC1_LPC_LA14_N
-set_property  -dict {PACKAGE_PIN P16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]]    ; ## FMC1_LPC_LA13_P
-set_property  -dict {PACKAGE_PIN R16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]]    ; ## FMC1_LPC_LA13_N
-set_property  -dict {PACKAGE_PIN J20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]]    ; ## FMC1_LPC_LA03_P
-set_property  -dict {PACKAGE_PIN K21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]]    ; ## FMC1_LPC_LA03_N
-set_property  -dict {PACKAGE_PIN N17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]]    ; ## FMC1_LPC_LA05_P
-set_property  -dict {PACKAGE_PIN N18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]]    ; ## FMC1_LPC_LA05_N
-set_property  -dict {PACKAGE_PIN L17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]]    ; ## FMC1_LPC_LA10_P
-set_property  -dict {PACKAGE_PIN M17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]]    ; ## FMC1_LPC_LA10_N
-set_property  -dict {PACKAGE_PIN N22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]]    ; ## FMC1_LPC_LA12_P
-set_property  -dict {PACKAGE_PIN P22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]]    ; ## FMC1_LPC_LA12_N
-set_property  -dict {PACKAGE_PIN J15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]    ; ## FMC1_LPC_LA07_P
-set_property  -dict {PACKAGE_PIN K15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]    ; ## FMC1_LPC_LA07_N
-set_property  -dict {PACKAGE_PIN L21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]]    ; ## FMC1_LPC_LA02_P
-set_property  -dict {PACKAGE_PIN L22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]]    ; ## FMC1_LPC_LA02_N
-set_property  -dict {PACKAGE_PIN M21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]]    ; ## FMC1_LPC_LA04_P
-set_property  -dict {PACKAGE_PIN M22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]]    ; ## FMC1_LPC_LA04_N
-set_property  -dict {PACKAGE_PIN M15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]]   ; ## FMC1_LPC_LA09_P
-set_property  -dict {PACKAGE_PIN M16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]]   ; ## FMC1_LPC_LA09_N
-set_property  -dict {PACKAGE_PIN J21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]]   ; ## FMC1_LPC_LA08_P
-set_property  -dict {PACKAGE_PIN J22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]]   ; ## FMC1_LPC_LA08_N
-set_property  -dict {PACKAGE_PIN J18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]]   ; ## FMC1_LPC_LA06_P
-set_property  -dict {PACKAGE_PIN K18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]]   ; ## FMC1_LPC_LA06_N
-set_property  -dict {PACKAGE_PIN N19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]   ; ## FMC1_LPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN N20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]   ; ## FMC1_LPC_LA01_CC_N
-
-# clocks
-
-create_clock -name dac_clk_in   -period  2.16 [get_ports dac_clk_in_p]
-create_clock -name adc_clk_in   -period  4.00 [get_ports adc_clk_in_p]
diff --git a/projects/fmcomms1/zc702/system_project.tcl b/projects/fmcomms1/zc702/system_project.tcl
deleted file mode 100644
index fc13dc6d2..000000000
--- a/projects/fmcomms1/zc702/system_project.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-
-source ../../scripts/adi_env.tcl
-source $ad_hdl_dir/projects/scripts/adi_project.tcl
-source $ad_hdl_dir/projects/scripts/adi_board.tcl
-
-adi_project_create fmcomms1_zc702
-adi_project_files fmcomms1_zc702 [list \
-  "system_top.v" \
-  "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run fmcomms1_zc702
-
-
diff --git a/projects/fmcomms1/zc702/system_top.v b/projects/fmcomms1/zc702/system_top.v
deleted file mode 100644
index c1ddc048b..000000000
--- a/projects/fmcomms1/zc702/system_top.v
+++ /dev/null
@@ -1,281 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module system_top (
-
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
-
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
-
-  gpio_bd,
-
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
-
-  spdif,
-
-  dac_clk_in_p,
-  dac_clk_in_n,
-  dac_clk_out_p,
-  dac_clk_out_n,
-  dac_frame_out_p,
-  dac_frame_out_n,
-  dac_data_out_p,
-  dac_data_out_n,
-
-  adc_clk_in_p,
-  adc_clk_in_n,
-  adc_or_in_p,
-  adc_or_in_n,
-  adc_data_in_p,
-  adc_data_in_n,
-
-  ref_clk_out_p,
-  ref_clk_out_n,
-
-  iic_scl,
-  iic_sda);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout   [15:0]  gpio_bd;
-
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [15:0]  hdmi_data;
-
-  output          spdif;
-
-  input           dac_clk_in_p;
-  input           dac_clk_in_n;
-  output          dac_clk_out_p;
-  output          dac_clk_out_n;
-  output          dac_frame_out_p;
-  output          dac_frame_out_n;
-  output  [15:0]  dac_data_out_p;
-  output  [15:0]  dac_data_out_n;
-
-  input           adc_clk_in_p;
-  input           adc_clk_in_n;
-  input           adc_or_in_n;
-  input           adc_or_in_p;
-  input   [13:0]  adc_data_in_n;
-  input   [13:0]  adc_data_in_p;
-
-  output          ref_clk_out_p;
-  output          ref_clk_out_n;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  // internal signals
-
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire    [ 2:0]  spi0_csn;
-  wire            spi0_clk;
-  wire            spi0_mosi;
-  wire            spi0_miso;
-  wire    [ 2:0]  spi1_csn;
-  wire            spi1_clk;
-  wire            spi1_mosi;
-  wire            spi1_miso;
-  wire            ref_clk;
-  wire            oddr_ref_clk;
-  wire    [15:0]  ps_intrs;
-
-  // instantiations
-
-  ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_oddr_ref_clk (
-    .S (1'b0),
-    .CE (1'b1),
-    .R (1'b0),
-    .C (ref_clk),
-    .D1 (1'b1),
-    .D2 (1'b0),
-    .Q (oddr_ref_clk));
-
-  OBUFDS i_obufds_ref_clk (
-    .I (oddr_ref_clk),
-    .O (ref_clk_out_p),
-    .OB (ref_clk_out_n));
-
-  ad_iobuf #(
-    .DATA_WIDTH(16))
-  i_gpio_bd (
-    .dio_t(gpio_t[15:0]),
-    .dio_i(gpio_o[15:0]),
-    .dio_o(gpio_i[15:0]),
-    .dio_p(gpio_bd));
-
-  system_wrapper i_system_wrapper (
-    .ddr_addr (ddr_addr),
-    .ddr_ba (ddr_ba),
-    .ddr_cas_n (ddr_cas_n),
-    .ddr_ck_n (ddr_ck_n),
-    .ddr_ck_p (ddr_ck_p),
-    .ddr_cke (ddr_cke),
-    .ddr_cs_n (ddr_cs_n),
-    .ddr_dm (ddr_dm),
-    .ddr_dq (ddr_dq),
-    .ddr_dqs_n (ddr_dqs_n),
-    .ddr_dqs_p (ddr_dqs_p),
-    .ddr_odt (ddr_odt),
-    .ddr_ras_n (ddr_ras_n),
-    .ddr_reset_n (ddr_reset_n),
-    .ddr_we_n (ddr_we_n),
-    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
-    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
-    .fixed_io_mio (fixed_io_mio),
-    .fixed_io_ps_clk (fixed_io_ps_clk),
-    .fixed_io_ps_porb (fixed_io_ps_porb),
-    .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gpio_i (gpio_i),
-    .gpio_o (gpio_o),
-    .gpio_t (gpio_t),
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .adc_or_in_n (adc_or_in_n),
-    .adc_or_in_p (adc_or_in_p),
-    .dac_clk_in_n (dac_clk_in_n),
-    .dac_clk_in_p (dac_clk_in_p),
-    .dac_clk_out_n (dac_clk_out_n),
-    .dac_clk_out_p (dac_clk_out_p),
-    .dac_data_out_n (dac_data_out_n),
-    .dac_data_out_p (dac_data_out_p),
-    .dac_frame_out_n (dac_frame_out_n),
-    .dac_frame_out_p (dac_frame_out_p),
-    .hdmi_data (hdmi_data),
-    .hdmi_data_e (hdmi_data_e),
-    .hdmi_hsync (hdmi_hsync),
-    .hdmi_out_clk (hdmi_out_clk),
-    .hdmi_vsync (hdmi_vsync),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
-    .ps_intr_00 (1'b0),
-    .ps_intr_01 (1'b0),
-    .ps_intr_02 (1'b0),
-    .ps_intr_03 (1'b0),
-    .ps_intr_04 (1'b0),
-    .ps_intr_05 (1'b0),
-    .ps_intr_06 (1'b0),
-    .ps_intr_07 (1'b0),
-    .ps_intr_08 (1'b0),
-    .ps_intr_09 (1'b0),
-    .ps_intr_10 (1'b0),
-    .ps_intr_11 (1'b0),
-    .ref_clk (ref_clk),
-    .spdif (spdif),
-    .spi0_clk_i (spi0_clk),
-    .spi0_clk_o (spi0_clk),
-    .spi0_csn_0_o (spi0_csn[0]),
-    .spi0_csn_1_o (spi0_csn[1]),
-    .spi0_csn_2_o (spi0_csn[2]),
-    .spi0_csn_i (1'b1),
-    .spi0_sdi_i (spi0_miso),
-    .spi0_sdo_i (spi0_mosi),
-    .spi0_sdo_o (spi0_mosi),
-    .spi1_clk_i (spi1_clk),
-    .spi1_clk_o (spi1_clk),
-    .spi1_csn_0_o (spi1_csn[0]),
-    .spi1_csn_1_o (spi1_csn[1]),
-    .spi1_csn_2_o (spi1_csn[2]),
-    .spi1_csn_i (1'b1),
-    .spi1_sdi_i (1'b1),
-    .spi1_sdo_i (spi1_mosi),
-    .spi1_sdo_o (spi1_mosi));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/projects/fmcomms1/zc706/Makefile b/projects/fmcomms1/zc706/Makefile
deleted file mode 100644
index c0e2e5068..000000000
--- a/projects/fmcomms1/zc706/Makefile
+++ /dev/null
@@ -1,84 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../common/fmcomms1_bd.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zc706/zc706_system_constr.xdc
-M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
-M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
-M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_upack/util_upack.xpr
-M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib fmcomms1_zc706.sdk/system_top.hdf
-
-
-clean: 
-	rm -rf $(M_FLIST)
-
-
-clean-all:clean
-	make -C ../../../library/axi_ad9122 clean
-	make -C ../../../library/axi_ad9643 clean
-	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_upack clean
-	make -C ../../../library/util_wfifo clean
-
-
-fmcomms1_zc706.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms1_zc706_vivado.log 2>&1
-
-
-lib:
-	make -C ../../../library/axi_ad9122
-	make -C ../../../library/axi_ad9643
-	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_cpack
-	make -C ../../../library/util_upack
-	make -C ../../../library/util_wfifo
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms1/zc706/system_bd.tcl b/projects/fmcomms1/zc706/system_bd.tcl
deleted file mode 100644
index dca59af34..000000000
--- a/projects/fmcomms1/zc706/system_bd.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-
-  source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-  source ../common/fmcomms1_bd.tcl
-
diff --git a/projects/fmcomms1/zc706/system_constr.xdc b/projects/fmcomms1/zc706/system_constr.xdc
deleted file mode 100644
index c93d464d3..000000000
--- a/projects/fmcomms1/zc706/system_constr.xdc
+++ /dev/null
@@ -1,86 +0,0 @@
-
-# reference
-
-set_property  -dict {PACKAGE_PIN AB27   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p]      ; ## FMC1_LPC_LA17_CC_P
-set_property  -dict {PACKAGE_PIN AC27   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n]      ; ## FMC1_LPC_LA17_CC_N
-
-# dac 
-
-set_property  -dict {PACKAGE_PIN AG17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p]       ; ## FMC1_LPC_CLK0_M2C_P
-set_property  -dict {PACKAGE_PIN AG16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n]       ; ## FMC1_LPC_CLK0_M2C_N
-set_property  -dict {PACKAGE_PIN AH28   IOSTANDARD LVDS_25} [get_ports dac_clk_out_p]                     ; ## FMC1_LPC_LA21_P
-set_property  -dict {PACKAGE_PIN AH29   IOSTANDARD LVDS_25} [get_ports dac_clk_out_n]                     ; ## FMC1_LPC_LA21_N
-set_property  -dict {PACKAGE_PIN AJ16   IOSTANDARD LVDS_25} [get_ports dac_frame_out_p]                   ; ## FMC1_LPC_LA11_P
-set_property  -dict {PACKAGE_PIN AK16   IOSTANDARD LVDS_25} [get_ports dac_frame_out_n]                   ; ## FMC1_LPC_LA11_N
-set_property  -dict {PACKAGE_PIN Y26    IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]]                 ; ## FMC1_LPC_LA32_P
-set_property  -dict {PACKAGE_PIN Y27    IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]]                 ; ## FMC1_LPC_LA32_N
-set_property  -dict {PACKAGE_PIN Y30    IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]]                 ; ## FMC1_LPC_LA33_P
-set_property  -dict {PACKAGE_PIN AA30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]]                 ; ## FMC1_LPC_LA33_N
-set_property  -dict {PACKAGE_PIN AB29   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]]                 ; ## FMC1_LPC_LA30_P
-set_property  -dict {PACKAGE_PIN AB30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]]                 ; ## FMC1_LPC_LA30_N
-set_property  -dict {PACKAGE_PIN AD25   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]]                 ; ## FMC1_LPC_LA28_P
-set_property  -dict {PACKAGE_PIN AE26   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]]                 ; ## FMC1_LPC_LA28_N
-set_property  -dict {PACKAGE_PIN AC29   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]]                 ; ## FMC1_LPC_LA31_P
-set_property  -dict {PACKAGE_PIN AD29   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]]                 ; ## FMC1_LPC_LA31_N
-set_property  -dict {PACKAGE_PIN AE25   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]]                 ; ## FMC1_LPC_LA29_P
-set_property  -dict {PACKAGE_PIN AF25   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]]                 ; ## FMC1_LPC_LA29_N
-set_property  -dict {PACKAGE_PIN AF30   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]]                 ; ## FMC1_LPC_LA24_P
-set_property  -dict {PACKAGE_PIN AG30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]]                 ; ## FMC1_LPC_LA24_N
-set_property  -dict {PACKAGE_PIN AF29   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]]                 ; ## FMC1_LPC_LA25_P
-set_property  -dict {PACKAGE_PIN AG29   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]]                 ; ## FMC1_LPC_LA25_N
-set_property  -dict {PACKAGE_PIN AK27   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]]                 ; ## FMC1_LPC_LA22_P
-set_property  -dict {PACKAGE_PIN AK28   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]]                 ; ## FMC1_LPC_LA22_N
-set_property  -dict {PACKAGE_PIN AJ28   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]]                 ; ## FMC1_LPC_LA27_P
-set_property  -dict {PACKAGE_PIN AJ29   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]]                 ; ## FMC1_LPC_LA27_N
-set_property  -dict {PACKAGE_PIN AJ30   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]]                ; ## FMC1_LPC_LA26_P
-set_property  -dict {PACKAGE_PIN AK30   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]]                ; ## FMC1_LPC_LA26_N
-set_property  -dict {PACKAGE_PIN AJ26   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]]                ; ## FMC1_LPC_LA23_P
-set_property  -dict {PACKAGE_PIN AK26   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]]                ; ## FMC1_LPC_LA23_N
-set_property  -dict {PACKAGE_PIN AH26   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]]                ; ## FMC1_LPC_LA19_P
-set_property  -dict {PACKAGE_PIN AH27   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]]                ; ## FMC1_LPC_LA19_N
-set_property  -dict {PACKAGE_PIN AG26   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]]                ; ## FMC1_LPC_LA20_P
-set_property  -dict {PACKAGE_PIN AG27   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]]                ; ## FMC1_LPC_LA20_N
-set_property  -dict {PACKAGE_PIN AB15   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]]                ; ## FMC1_LPC_LA15_P
-set_property  -dict {PACKAGE_PIN AB14   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]]                ; ## FMC1_LPC_LA15_N
-set_property  -dict {PACKAGE_PIN AE18   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]]                ; ## FMC1_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN AE17   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]]                ; ## FMC1_LPC_LA16_N
-
-# adc 
-
-set_property  -dict {PACKAGE_PIN AC28   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p]       ; ## FMC1_LPC_CLK1_M2C_P
-set_property  -dict {PACKAGE_PIN AD28   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n]       ; ## FMC1_LPC_CLK1_M2C_N
-set_property  -dict {PACKAGE_PIN AE13   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p]        ; ## FMC1_LPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN AF13   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n]        ; ## FMC1_LPC_LA00_CC_N
-set_property  -dict {PACKAGE_PIN AE27   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]   ; ## FMC1_LPC_LA18_CC_P
-set_property  -dict {PACKAGE_PIN AF27   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]   ; ## FMC1_LPC_LA18_CC_N
-set_property  -dict {PACKAGE_PIN AF18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]   ; ## FMC1_LPC_LA14_P
-set_property  -dict {PACKAGE_PIN AF17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]]   ; ## FMC1_LPC_LA14_N
-set_property  -dict {PACKAGE_PIN AH17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]]   ; ## FMC1_LPC_LA13_P
-set_property  -dict {PACKAGE_PIN AH16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]]   ; ## FMC1_LPC_LA13_N
-set_property  -dict {PACKAGE_PIN AG12   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]]   ; ## FMC1_LPC_LA03_P
-set_property  -dict {PACKAGE_PIN AH12   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]]   ; ## FMC1_LPC_LA03_N
-set_property  -dict {PACKAGE_PIN AE16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]]   ; ## FMC1_LPC_LA05_P
-set_property  -dict {PACKAGE_PIN AE15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]]   ; ## FMC1_LPC_LA05_N
-set_property  -dict {PACKAGE_PIN AC14   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]]   ; ## FMC1_LPC_LA10_P
-set_property  -dict {PACKAGE_PIN AC13   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]]   ; ## FMC1_LPC_LA10_N
-set_property  -dict {PACKAGE_PIN AD16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]]   ; ## FMC1_LPC_LA12_P
-set_property  -dict {PACKAGE_PIN AD15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]]   ; ## FMC1_LPC_LA12_N
-set_property  -dict {PACKAGE_PIN AA15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]   ; ## FMC1_LPC_LA07_P
-set_property  -dict {PACKAGE_PIN AA14   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]   ; ## FMC1_LPC_LA07_N
-set_property  -dict {PACKAGE_PIN AE12   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]]   ; ## FMC1_LPC_LA02_P
-set_property  -dict {PACKAGE_PIN AF12   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]]   ; ## FMC1_LPC_LA02_N
-set_property  -dict {PACKAGE_PIN AJ15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]]   ; ## FMC1_LPC_LA04_P
-set_property  -dict {PACKAGE_PIN AK15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]]   ; ## FMC1_LPC_LA04_N
-set_property  -dict {PACKAGE_PIN AH14   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]]  ; ## FMC1_LPC_LA09_P
-set_property  -dict {PACKAGE_PIN AH13   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]]  ; ## FMC1_LPC_LA09_N
-set_property  -dict {PACKAGE_PIN AD14   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]]  ; ## FMC1_LPC_LA08_P
-set_property  -dict {PACKAGE_PIN AD13   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]]  ; ## FMC1_LPC_LA08_N
-set_property  -dict {PACKAGE_PIN AB12   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]]  ; ## FMC1_LPC_LA06_P
-set_property  -dict {PACKAGE_PIN AC12   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]]  ; ## FMC1_LPC_LA06_N
-set_property  -dict {PACKAGE_PIN AF15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]  ; ## FMC1_LPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN AG15   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]  ; ## FMC1_LPC_LA01_CC_N
-
-# clocks
-
-create_clock -name dac_clk_in   -period  2.00 [get_ports dac_clk_in_p]
-create_clock -name adc_clk_in   -period  4.00 [get_ports adc_clk_in_p]
diff --git a/projects/fmcomms1/zc706/system_project.tcl b/projects/fmcomms1/zc706/system_project.tcl
deleted file mode 100644
index f104736d4..000000000
--- a/projects/fmcomms1/zc706/system_project.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-
-source ../../scripts/adi_env.tcl
-source $ad_hdl_dir/projects/scripts/adi_project.tcl
-source $ad_hdl_dir/projects/scripts/adi_board.tcl
-
-adi_project_create fmcomms1_zc706
-adi_project_files fmcomms1_zc706 [list \
-  "system_top.v" \
-  "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run fmcomms1_zc706
-
-
diff --git a/projects/fmcomms1/zc706/system_top.v b/projects/fmcomms1/zc706/system_top.v
deleted file mode 100644
index 298adf428..000000000
--- a/projects/fmcomms1/zc706/system_top.v
+++ /dev/null
@@ -1,280 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module system_top (
-
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
-
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
-
-  gpio_bd,
-
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
-
-  spdif,
-
-  dac_clk_in_p,
-  dac_clk_in_n,
-  dac_clk_out_p,
-  dac_clk_out_n,
-  dac_frame_out_p,
-  dac_frame_out_n,
-  dac_data_out_p,
-  dac_data_out_n,
-
-  adc_clk_in_p,
-  adc_clk_in_n,
-  adc_or_in_p,
-  adc_or_in_n,
-  adc_data_in_p,
-  adc_data_in_n,
-
-  ref_clk_out_p,
-  ref_clk_out_n,
-
-  iic_scl,
-  iic_sda);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout   [14:0]  gpio_bd;
-
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [23:0]  hdmi_data;
-
-  output          spdif;
-
-  input           dac_clk_in_p;
-  input           dac_clk_in_n;
-  output          dac_clk_out_p;
-  output          dac_clk_out_n;
-  output          dac_frame_out_p;
-  output          dac_frame_out_n;
-  output   [15:0] dac_data_out_p;
-  output   [15:0] dac_data_out_n;
-
-  input           adc_clk_in_p;
-  input           adc_clk_in_n;
-  input           adc_or_in_p;
-  input           adc_or_in_n;
-  input   [13:0]  adc_data_in_p;
-  input   [13:0]  adc_data_in_n;
-
-  output          ref_clk_out_p;
-  output          ref_clk_out_n;
-
-  inout           iic_scl;
-  inout           iic_sda;
-
-  // internal signals
-
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire    [ 2:0]  spi0_csn;
-  wire            spi0_clk;
-  wire            spi0_mosi;
-  wire            spi0_miso;
-  wire    [ 2:0]  spi1_csn;
-  wire            spi1_clk;
-  wire            spi1_mosi;
-  wire            spi1_miso;
-  wire            ref_clk;
-  wire            oddr_ref_clk;
-
-  // instantiations
-
-  ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_oddr_ref_clk (
-    .S (1'b0),
-    .CE (1'b1),
-    .R (1'b0),
-    .C (ref_clk),
-    .D1 (1'b1),
-    .D2 (1'b0),
-    .Q (oddr_ref_clk));
-
-  OBUFDS i_obufds_ref_clk (
-    .I (oddr_ref_clk),
-    .O (ref_clk_out_p),
-    .OB (ref_clk_out_n));
-
- ad_iobuf #(
-    .DATA_WIDTH(15))
-  i_gpio_bd (
-    .dio_t(gpio_t[14:0]),
-    .dio_i(gpio_o[14:0]),
-    .dio_o(gpio_i[14:0]),
-    .dio_p(gpio_bd));
-
-  system_wrapper i_system_wrapper (
-    .ddr_addr (ddr_addr),
-    .ddr_ba (ddr_ba),
-    .ddr_cas_n (ddr_cas_n),
-    .ddr_ck_n (ddr_ck_n),
-    .ddr_ck_p (ddr_ck_p),
-    .ddr_cke (ddr_cke),
-    .ddr_cs_n (ddr_cs_n),
-    .ddr_dm (ddr_dm),
-    .ddr_dq (ddr_dq),
-    .ddr_dqs_n (ddr_dqs_n),
-    .ddr_dqs_p (ddr_dqs_p),
-    .ddr_odt (ddr_odt),
-    .ddr_ras_n (ddr_ras_n),
-    .ddr_reset_n (ddr_reset_n),
-    .ddr_we_n (ddr_we_n),
-    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
-    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
-    .fixed_io_mio (fixed_io_mio),
-    .fixed_io_ps_clk (fixed_io_ps_clk),
-    .fixed_io_ps_porb (fixed_io_ps_porb),
-    .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gpio_i (gpio_i),
-    .gpio_o (gpio_o),
-    .gpio_t (gpio_t),
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .adc_or_in_n (adc_or_in_n),
-    .adc_or_in_p (adc_or_in_p),
-    .dac_clk_in_n (dac_clk_in_n),
-    .dac_clk_in_p (dac_clk_in_p),
-    .dac_clk_out_n (dac_clk_out_n),
-    .dac_clk_out_p (dac_clk_out_p),
-    .dac_data_out_n (dac_data_out_n),
-    .dac_data_out_p (dac_data_out_p),
-    .dac_frame_out_n (dac_frame_out_n),
-    .dac_frame_out_p (dac_frame_out_p),
-    .hdmi_data (hdmi_data),
-    .hdmi_data_e (hdmi_data_e),
-    .hdmi_hsync (hdmi_hsync),
-    .hdmi_out_clk (hdmi_out_clk),
-    .hdmi_vsync (hdmi_vsync),
-    .iic_main_scl_io (iic_scl),
-    .iic_main_sda_io (iic_sda),
-    .ps_intr_00 (1'b0),
-    .ps_intr_01 (1'b0),
-    .ps_intr_02 (1'b0),
-    .ps_intr_03 (1'b0),
-    .ps_intr_04 (1'b0),
-    .ps_intr_05 (1'b0),
-    .ps_intr_06 (1'b0),
-    .ps_intr_07 (1'b0),
-    .ps_intr_08 (1'b0),
-    .ps_intr_09 (1'b0),
-    .ps_intr_10 (1'b0),
-    .ps_intr_11 (1'b0),
-    .ref_clk (ref_clk),
-    .spdif (spdif),
-    .spi0_clk_i (spi0_clk),
-    .spi0_clk_o (spi0_clk),
-    .spi0_csn_0_o (spi0_csn[0]),
-    .spi0_csn_1_o (spi0_csn[1]),
-    .spi0_csn_2_o (spi0_csn[2]),
-    .spi0_csn_i (1'b1),
-    .spi0_sdi_i (spi0_miso),
-    .spi0_sdo_i (spi0_mosi),
-    .spi0_sdo_o (spi0_mosi),
-    .spi1_clk_i (spi1_clk),
-    .spi1_clk_o (spi1_clk),
-    .spi1_csn_0_o (spi1_csn[0]),
-    .spi1_csn_1_o (spi1_csn[1]),
-    .spi1_csn_2_o (spi1_csn[2]),
-    .spi1_csn_i (1'b1),
-    .spi1_sdi_i (1'b1),
-    .spi1_sdo_i (spi1_mosi),
-    .spi1_sdo_o (spi1_mosi));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/projects/fmcomms1/zed/Makefile b/projects/fmcomms1/zed/Makefile
deleted file mode 100644
index 6d3fd1ac3..000000000
--- a/projects/fmcomms1/zed/Makefile
+++ /dev/null
@@ -1,90 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += system_top.v
-M_DEPS += system_project.tcl
-M_DEPS += system_constr.xdc
-M_DEPS += system_bd.tcl
-M_DEPS += ../common/fmcomms1_bd.tcl
-M_DEPS += ../../scripts/adi_project.tcl
-M_DEPS += ../../scripts/adi_env.tcl
-M_DEPS += ../../scripts/adi_board.tcl
-M_DEPS += ../../common/zed/zed_system_constr.xdc
-M_DEPS += ../../common/zed/zed_system_bd.tcl
-M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr
-M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr
-M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
-M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
-M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
-M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
-M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
-M_DEPS += ../../../library/util_cpack/util_cpack.xpr
-M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
-M_DEPS += ../../../library/util_upack/util_upack.xpr
-M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.runs
-M_FLIST += *.srcs
-M_FLIST += *.sdk
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-M_FLIST += *.ip_user_files
-
-
-
-.PHONY: all lib clean clean-all
-all: lib fmcomms1_zed.sdk/system_top.hdf
-
-
-clean: 
-	rm -rf $(M_FLIST)
-
-
-clean-all:clean
-	make -C ../../../library/axi_ad9122 clean
-	make -C ../../../library/axi_ad9643 clean
-	make -C ../../../library/axi_clkgen clean
-	make -C ../../../library/axi_dmac clean
-	make -C ../../../library/axi_hdmi_tx clean
-	make -C ../../../library/axi_i2s_adi clean
-	make -C ../../../library/axi_spdif_tx clean
-	make -C ../../../library/util_cpack clean
-	make -C ../../../library/util_i2c_mixer clean
-	make -C ../../../library/util_upack clean
-	make -C ../../../library/util_wfifo clean
-
-
-fmcomms1_zed.sdk/system_top.hdf: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) system_project.tcl >> fmcomms1_zed_vivado.log 2>&1
-
-
-lib:
-	make -C ../../../library/axi_ad9122
-	make -C ../../../library/axi_ad9643
-	make -C ../../../library/axi_clkgen
-	make -C ../../../library/axi_dmac
-	make -C ../../../library/axi_hdmi_tx
-	make -C ../../../library/axi_i2s_adi
-	make -C ../../../library/axi_spdif_tx
-	make -C ../../../library/util_cpack
-	make -C ../../../library/util_i2c_mixer
-	make -C ../../../library/util_upack
-	make -C ../../../library/util_wfifo
-
-####################################################################################
-####################################################################################
diff --git a/projects/fmcomms1/zed/system_bd.tcl b/projects/fmcomms1/zed/system_bd.tcl
deleted file mode 100644
index 4032107bf..000000000
--- a/projects/fmcomms1/zed/system_bd.tcl
+++ /dev/null
@@ -1,13 +0,0 @@
-
-  source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
-  source ../common/fmcomms1_bd.tcl
-
-  # Add extra register slice between ADC DMA and HP1 to meet timing
-  #delete_bd_objs [get_bd_intf_nets axi_ad9643_dma_axi]
-  #create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0
-  #set_property -dict [list CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_W {1} CONFIG.REG_R {0} CONFIG.REG_B {0}] [get_bd_cells axi_register_slice_0]
-  #ad_connect [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
-  #connect_bd_intf_net [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_register_slice_0/M_AXI]
-  #connect_bd_net -net [get_bd_nets sys_200m_clk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins sys_ps7/FCLK_CLK1]
-  #connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn]
-  #assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM }]
diff --git a/projects/fmcomms1/zed/system_constr.xdc b/projects/fmcomms1/zed/system_constr.xdc
deleted file mode 100644
index e2a84680e..000000000
--- a/projects/fmcomms1/zed/system_constr.xdc
+++ /dev/null
@@ -1,86 +0,0 @@
-
-# reference
-
-set_property  -dict {PACKAGE_PIN B19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p]       ; ## FMC1_LPC_LA17_CC_P
-set_property  -dict {PACKAGE_PIN B20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n]       ; ## FMC1_LPC_LA17_CC_N
-                                                                                                                                   
-# dac                                                                                                                              
-                                                                                                                                   
-set_property  -dict {PACKAGE_PIN L18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p]        ; ## FMC1_LPC_CLK0_M2C_P
-set_property  -dict {PACKAGE_PIN L19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n]        ; ## FMC1_LPC_CLK0_M2C_N
-set_property  -dict {PACKAGE_PIN E19   IOSTANDARD LVDS_25} [get_ports dac_clk_out_p]                      ; ## FMC1_LPC_LA21_P
-set_property  -dict {PACKAGE_PIN E20   IOSTANDARD LVDS_25} [get_ports dac_clk_out_n]                      ; ## FMC1_LPC_LA21_N
-set_property  -dict {PACKAGE_PIN N17   IOSTANDARD LVDS_25} [get_ports dac_frame_out_p]                    ; ## FMC1_LPC_LA11_P
-set_property  -dict {PACKAGE_PIN N18   IOSTANDARD LVDS_25} [get_ports dac_frame_out_n]                    ; ## FMC1_LPC_LA11_N
-set_property  -dict {PACKAGE_PIN A21   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]]                  ; ## FMC1_LPC_LA32_P
-set_property  -dict {PACKAGE_PIN A22   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]]                  ; ## FMC1_LPC_LA32_N
-set_property  -dict {PACKAGE_PIN B21   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]]                  ; ## FMC1_LPC_LA33_P
-set_property  -dict {PACKAGE_PIN B22   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]]                  ; ## FMC1_LPC_LA33_N
-set_property  -dict {PACKAGE_PIN C15   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]]                  ; ## FMC1_LPC_LA30_P
-set_property  -dict {PACKAGE_PIN B15   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]]                  ; ## FMC1_LPC_LA30_N
-set_property  -dict {PACKAGE_PIN A16   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]]                  ; ## FMC1_LPC_LA28_P
-set_property  -dict {PACKAGE_PIN A17   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]]                  ; ## FMC1_LPC_LA28_N
-set_property  -dict {PACKAGE_PIN B16   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]]                  ; ## FMC1_LPC_LA31_P
-set_property  -dict {PACKAGE_PIN B17   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]]                  ; ## FMC1_LPC_LA31_N
-set_property  -dict {PACKAGE_PIN C17   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]]                  ; ## FMC1_LPC_LA29_P
-set_property  -dict {PACKAGE_PIN C18   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]]                  ; ## FMC1_LPC_LA29_N
-set_property  -dict {PACKAGE_PIN A18   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]]                  ; ## FMC1_LPC_LA24_P
-set_property  -dict {PACKAGE_PIN A19   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]]                  ; ## FMC1_LPC_LA24_N
-set_property  -dict {PACKAGE_PIN D22   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]]                  ; ## FMC1_LPC_LA25_P
-set_property  -dict {PACKAGE_PIN C22   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]]                  ; ## FMC1_LPC_LA25_N
-set_property  -dict {PACKAGE_PIN G19   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]]                  ; ## FMC1_LPC_LA22_P
-set_property  -dict {PACKAGE_PIN F19   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]]                  ; ## FMC1_LPC_LA22_N
-set_property  -dict {PACKAGE_PIN E21   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]]                  ; ## FMC1_LPC_LA27_P
-set_property  -dict {PACKAGE_PIN D21   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]]                  ; ## FMC1_LPC_LA27_N
-set_property  -dict {PACKAGE_PIN F18   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]]                 ; ## FMC1_LPC_LA26_P
-set_property  -dict {PACKAGE_PIN E18   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]]                 ; ## FMC1_LPC_LA26_N
-set_property  -dict {PACKAGE_PIN E15   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]]                 ; ## FMC1_LPC_LA23_P
-set_property  -dict {PACKAGE_PIN D15   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]]                 ; ## FMC1_LPC_LA23_N
-set_property  -dict {PACKAGE_PIN G15   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]]                 ; ## FMC1_LPC_LA19_P
-set_property  -dict {PACKAGE_PIN G16   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]]                 ; ## FMC1_LPC_LA19_N
-set_property  -dict {PACKAGE_PIN G20   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]]                 ; ## FMC1_LPC_LA20_P
-set_property  -dict {PACKAGE_PIN G21   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]]                 ; ## FMC1_LPC_LA20_N
-set_property  -dict {PACKAGE_PIN J16   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]]                 ; ## FMC1_LPC_LA15_P
-set_property  -dict {PACKAGE_PIN J17   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]]                 ; ## FMC1_LPC_LA15_N
-set_property  -dict {PACKAGE_PIN J20   IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]]                 ; ## FMC1_LPC_LA16_P
-set_property  -dict {PACKAGE_PIN K21   IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]]                 ; ## FMC1_LPC_LA16_N
-                                                                                                                                   
-# adc                                                                                                                              
-                                                                                                                                   
-set_property  -dict {PACKAGE_PIN D18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p]        ; ## FMC1_LPC_CLK1_M2C_P
-set_property  -dict {PACKAGE_PIN C19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n]        ; ## FMC1_LPC_CLK1_M2C_N
-set_property  -dict {PACKAGE_PIN M19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p]         ; ## FMC1_LPC_LA00_CC_P
-set_property  -dict {PACKAGE_PIN M20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n]         ; ## FMC1_LPC_LA00_CC_N
-set_property  -dict {PACKAGE_PIN D20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]]    ; ## FMC1_LPC_LA18_CC_P
-set_property  -dict {PACKAGE_PIN C20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]]    ; ## FMC1_LPC_LA18_CC_N
-set_property  -dict {PACKAGE_PIN K19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]]    ; ## FMC1_LPC_LA14_P
-set_property  -dict {PACKAGE_PIN K20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]]    ; ## FMC1_LPC_LA14_N
-set_property  -dict {PACKAGE_PIN L17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]]    ; ## FMC1_LPC_LA13_P
-set_property  -dict {PACKAGE_PIN M17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]]    ; ## FMC1_LPC_LA13_N
-set_property  -dict {PACKAGE_PIN N22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]]    ; ## FMC1_LPC_LA03_P
-set_property  -dict {PACKAGE_PIN P22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]]    ; ## FMC1_LPC_LA03_N
-set_property  -dict {PACKAGE_PIN J18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]]    ; ## FMC1_LPC_LA05_P
-set_property  -dict {PACKAGE_PIN K18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]]    ; ## FMC1_LPC_LA05_N
-set_property  -dict {PACKAGE_PIN R19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]]    ; ## FMC1_LPC_LA10_P
-set_property  -dict {PACKAGE_PIN T19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]]    ; ## FMC1_LPC_LA10_N
-set_property  -dict {PACKAGE_PIN P20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]]    ; ## FMC1_LPC_LA12_P
-set_property  -dict {PACKAGE_PIN P21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]]    ; ## FMC1_LPC_LA12_N
-set_property  -dict {PACKAGE_PIN T16   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]]    ; ## FMC1_LPC_LA07_P
-set_property  -dict {PACKAGE_PIN T17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]]    ; ## FMC1_LPC_LA07_N
-set_property  -dict {PACKAGE_PIN P17   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]]    ; ## FMC1_LPC_LA02_P
-set_property  -dict {PACKAGE_PIN P18   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]]    ; ## FMC1_LPC_LA02_N
-set_property  -dict {PACKAGE_PIN M21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]]    ; ## FMC1_LPC_LA04_P
-set_property  -dict {PACKAGE_PIN M22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]]    ; ## FMC1_LPC_LA04_N
-set_property  -dict {PACKAGE_PIN R20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]]   ; ## FMC1_LPC_LA09_P
-set_property  -dict {PACKAGE_PIN R21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]]   ; ## FMC1_LPC_LA09_N
-set_property  -dict {PACKAGE_PIN J21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]]   ; ## FMC1_LPC_LA08_P
-set_property  -dict {PACKAGE_PIN J22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]]   ; ## FMC1_LPC_LA08_N
-set_property  -dict {PACKAGE_PIN L21   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]]   ; ## FMC1_LPC_LA06_P
-set_property  -dict {PACKAGE_PIN L22   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]]   ; ## FMC1_LPC_LA06_N
-set_property  -dict {PACKAGE_PIN N19   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]]   ; ## FMC1_LPC_LA01_CC_P
-set_property  -dict {PACKAGE_PIN N20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]]   ; ## FMC1_LPC_LA01_CC_N
-
-# clocks
-
-create_clock -name dac_clk_in   -period  2.16 [get_ports dac_clk_in_p]
-create_clock -name adc_clk_in   -period  4.00 [get_ports adc_clk_in_p]
diff --git a/projects/fmcomms1/zed/system_project.tcl b/projects/fmcomms1/zed/system_project.tcl
deleted file mode 100644
index 1e5eb5bd0..000000000
--- a/projects/fmcomms1/zed/system_project.tcl
+++ /dev/null
@@ -1,18 +0,0 @@
-
-source ../../scripts/adi_env.tcl
-source $ad_hdl_dir/projects/scripts/adi_project.tcl
-source $ad_hdl_dir/projects/scripts/adi_board.tcl
-
-adi_project_create fmcomms1_zed
-adi_project_files fmcomms1_zed [list \
-  "system_top.v" \
-  "system_constr.xdc"\
-  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
-
-set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zed/zed_system_constr.xdc]
-set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
-
-adi_project_run fmcomms1_zed
-
-
diff --git a/projects/fmcomms1/zed/system_top.v b/projects/fmcomms1/zed/system_top.v
deleted file mode 100644
index 8bf4fc58a..000000000
--- a/projects/fmcomms1/zed/system_top.v
+++ /dev/null
@@ -1,335 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module system_top (
-
-  ddr_addr,
-  ddr_ba,
-  ddr_cas_n,
-  ddr_ck_n,
-  ddr_ck_p,
-  ddr_cke,
-  ddr_cs_n,
-  ddr_dm,
-  ddr_dq,
-  ddr_dqs_n,
-  ddr_dqs_p,
-  ddr_odt,
-  ddr_ras_n,
-  ddr_reset_n,
-  ddr_we_n,
-
-  fixed_io_ddr_vrn,
-  fixed_io_ddr_vrp,
-  fixed_io_mio,
-  fixed_io_ps_clk,
-  fixed_io_ps_porb,
-  fixed_io_ps_srstb,
-
-  gpio_bd,
-
-  hdmi_out_clk,
-  hdmi_vsync,
-  hdmi_hsync,
-  hdmi_data_e,
-  hdmi_data,
-
-  i2s_mclk,
-  i2s_bclk,
-  i2s_lrclk,
-  i2s_sdata_out,
-  i2s_sdata_in,
-
-  spdif,
-
-  dac_clk_in_p,
-  dac_clk_in_n,
-  dac_clk_out_p,
-  dac_clk_out_n,
-  dac_frame_out_p,
-  dac_frame_out_n,
-  dac_data_out_p,
-  dac_data_out_n,
-
-  adc_clk_in_p,
-  adc_clk_in_n,
-  adc_or_in_p,
-  adc_or_in_n,
-  adc_data_in_p,
-  adc_data_in_n,
-
-  ref_clk_out_p,
-  ref_clk_out_n,
-
-  iic_scl,
-  iic_sda,
-  iic_mux_scl,
-  iic_mux_sda,
-
-  otg_vbusoc);
-
-  inout   [14:0]  ddr_addr;
-  inout   [ 2:0]  ddr_ba;
-  inout           ddr_cas_n;
-  inout           ddr_ck_n;
-  inout           ddr_ck_p;
-  inout           ddr_cke;
-  inout           ddr_cs_n;
-  inout   [ 3:0]  ddr_dm;
-  inout   [31:0]  ddr_dq;
-  inout   [ 3:0]  ddr_dqs_n;
-  inout   [ 3:0]  ddr_dqs_p;
-  inout           ddr_odt;
-  inout           ddr_ras_n;
-  inout           ddr_reset_n;
-  inout           ddr_we_n;
-
-  inout           fixed_io_ddr_vrn;
-  inout           fixed_io_ddr_vrp;
-  inout   [53:0]  fixed_io_mio;
-  inout           fixed_io_ps_clk;
-  inout           fixed_io_ps_porb;
-  inout           fixed_io_ps_srstb;
-
-  inout   [31:0]  gpio_bd;
-
-  output          hdmi_out_clk;
-  output          hdmi_vsync;
-  output          hdmi_hsync;
-  output          hdmi_data_e;
-  output  [15:0]  hdmi_data;
-
-  output          spdif;
-
-  output          i2s_mclk;
-  output          i2s_bclk;
-  output          i2s_lrclk;
-  output          i2s_sdata_out;
-  input           i2s_sdata_in;
-
-  input           dac_clk_in_p;
-  input           dac_clk_in_n;
-  output          dac_clk_out_p;
-  output          dac_clk_out_n;
-  output          dac_frame_out_p;
-  output          dac_frame_out_n;
-  output  [15:0]  dac_data_out_p;
-  output  [15:0]  dac_data_out_n;
-
-  input           adc_clk_in_p;
-  input           adc_clk_in_n;
-  input           adc_or_in_p;
-  input           adc_or_in_n;
-  input   [13:0]  adc_data_in_p;
-  input   [13:0]  adc_data_in_n;
-
-  output          ref_clk_out_p;
-  output          ref_clk_out_n;
-
-  inout           iic_scl;
-  inout           iic_sda;
-  inout   [ 1:0]  iic_mux_scl;
-  inout   [ 1:0]  iic_mux_sda;
-
-  input           otg_vbusoc;
-
-  // internal signals
-
-  wire    [63:0]  gpio_i;
-  wire    [63:0]  gpio_o;
-  wire    [63:0]  gpio_t;
-  wire    [ 2:0]  spi0_csn;
-  wire            spi0_clk;
-  wire            spi0_mosi;
-  wire            spi0_miso;
-  wire    [ 2:0]  spi1_csn;
-  wire            spi1_clk;
-  wire            spi1_mosi;
-  wire            spi1_miso;
-  wire            ref_clk;
-  wire            oddr_ref_clk;
-
-  wire    [ 1:0]  iic_mux_scl_i_s;
-  wire    [ 1:0]  iic_mux_scl_o_s;
-  wire            iic_mux_scl_t_s;
-  wire    [ 1:0]  iic_mux_sda_i_s;
-  wire    [ 1:0]  iic_mux_sda_o_s;
-  wire            iic_mux_sda_t_s;
-  wire    [15:0]  ps_intrs;
-
-  // instantiations
-
-  ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_oddr_ref_clk (
-    .S (1'b0),
-    .CE (1'b1),
-    .R (1'b0),
-    .C (ref_clk),
-    .D1 (1'b1),
-    .D2 (1'b0),
-    .Q (oddr_ref_clk));
-
-  OBUFDS i_obufds_ref_clk (
-    .I (oddr_ref_clk),
-    .O (ref_clk_out_p),
-    .OB (ref_clk_out_n));
-
-  ad_iobuf #(
-    .DATA_WIDTH(32))
-  i_gpio_bd (
-    .dio_t(gpio_t[31:0]),
-    .dio_i(gpio_o[31:0]),
-    .dio_o(gpio_i[31:0]),
-    .dio_p(gpio_bd));
-
- ad_iobuf #(
-    .DATA_WIDTH(2))
- i_iic_mux_scl (
-    .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
-    .dio_i(iic_mux_scl_o_s),
-    .dio_o(iic_mux_scl_i_s),
-    .dio_p(iic_mux_scl));
-
-  ad_iobuf #(
-    .DATA_WIDTH(2))
-  i_iic_mux_sda (
-    .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
-    .dio_i(iic_mux_sda_o_s),
-    .dio_o(iic_mux_sda_i_s),
-    .dio_p(iic_mux_sda));
-
-  system_wrapper i_system_wrapper (
-    .ddr_addr (ddr_addr),
-    .ddr_ba (ddr_ba),
-    .ddr_cas_n (ddr_cas_n),
-    .ddr_ck_n (ddr_ck_n),
-    .ddr_ck_p (ddr_ck_p),
-    .ddr_cke (ddr_cke),
-    .ddr_cs_n (ddr_cs_n),
-    .ddr_dm (ddr_dm),
-    .ddr_dq (ddr_dq),
-    .ddr_dqs_n (ddr_dqs_n),
-    .ddr_dqs_p (ddr_dqs_p),
-    .ddr_odt (ddr_odt),
-    .ddr_ras_n (ddr_ras_n),
-    .ddr_reset_n (ddr_reset_n),
-    .ddr_we_n (ddr_we_n),
-    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
-    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
-    .fixed_io_mio (fixed_io_mio),
-    .fixed_io_ps_clk (fixed_io_ps_clk),
-    .fixed_io_ps_porb (fixed_io_ps_porb),
-    .fixed_io_ps_srstb (fixed_io_ps_srstb),
-    .gpio_i (gpio_i),
-    .gpio_o (gpio_o),
-    .gpio_t (gpio_t),
-    .adc_clk_in_n (adc_clk_in_n),
-    .adc_clk_in_p (adc_clk_in_p),
-    .adc_data_in_n (adc_data_in_n),
-    .adc_data_in_p (adc_data_in_p),
-    .adc_or_in_n (adc_or_in_n),
-    .adc_or_in_p (adc_or_in_p),
-    .dac_clk_in_n (dac_clk_in_n),
-    .dac_clk_in_p (dac_clk_in_p),
-    .dac_clk_out_n (dac_clk_out_n),
-    .dac_clk_out_p (dac_clk_out_p),
-    .dac_data_out_n (dac_data_out_n),
-    .dac_data_out_p (dac_data_out_p),
-    .dac_frame_out_n (dac_frame_out_n),
-    .dac_frame_out_p (dac_frame_out_p),
-    .hdmi_data (hdmi_data),
-    .hdmi_data_e (hdmi_data_e),
-    .hdmi_hsync (hdmi_hsync),
-    .hdmi_out_clk (hdmi_out_clk),
-    .hdmi_vsync (hdmi_vsync),
-    .i2s_bclk (i2s_bclk),
-    .i2s_lrclk (i2s_lrclk),
-    .i2s_mclk (i2s_mclk),
-    .i2s_sdata_in (i2s_sdata_in),
-    .i2s_sdata_out (i2s_sdata_out),
-    .iic_fmc_scl_io (iic_scl),
-    .iic_fmc_sda_io (iic_sda),
-    .iic_mux_scl_i (iic_mux_scl_i_s),
-    .iic_mux_scl_o (iic_mux_scl_o_s),
-    .iic_mux_scl_t (iic_mux_scl_t_s),
-    .iic_mux_sda_i (iic_mux_sda_i_s),
-    .iic_mux_sda_o (iic_mux_sda_o_s),
-    .iic_mux_sda_t (iic_mux_sda_t_s),
-    .ps_intr_00 (1'b0),
-    .ps_intr_01 (1'b0),
-    .ps_intr_02 (1'b0),
-    .ps_intr_03 (1'b0),
-    .ps_intr_04 (1'b0),
-    .ps_intr_05 (1'b0),
-    .ps_intr_06 (1'b0),
-    .ps_intr_07 (1'b0),
-    .ps_intr_08 (1'b0),
-    .ps_intr_09 (1'b0),
-    .ps_intr_10 (1'b0),
-    .ref_clk (ref_clk),
-    .otg_vbusoc (otg_vbusoc),
-    .spdif (spdif),
-    .spi0_clk_i (spi0_clk),
-    .spi0_clk_o (spi0_clk),
-    .spi0_csn_0_o (spi0_csn[0]),
-    .spi0_csn_1_o (spi0_csn[1]),
-    .spi0_csn_2_o (spi0_csn[2]),
-    .spi0_csn_i (1'b1),
-    .spi0_sdi_i (spi0_miso),
-    .spi0_sdo_i (spi0_mosi),
-    .spi0_sdo_o (spi0_mosi),
-    .spi1_clk_i (spi1_clk),
-    .spi1_clk_o (spi1_clk),
-    .spi1_csn_0_o (spi1_csn[0]),
-    .spi1_csn_1_o (spi1_csn[1]),
-    .spi1_csn_2_o (spi1_csn[2]),
-    .spi1_csn_i (1'b1),
-    .spi1_sdi_i (1'b1),
-    .spi1_sdo_i (spi1_mosi),
-    .spi1_sdo_o (spi1_mosi));
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************

From 58872aa3ef66f0e87364244bb791a4db655b805e Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 6 Feb 2017 10:59:18 -0500
Subject: [PATCH 901/972] fmcomms2/zc706pr- prcfg is a single clock synchronous
 design

---
 projects/fmcomms2/zc706pr/system_constr.xdc | 44 ---------------------
 1 file changed, 44 deletions(-)

diff --git a/projects/fmcomms2/zc706pr/system_constr.xdc b/projects/fmcomms2/zc706pr/system_constr.xdc
index 53377ada7..e69de29bb 100644
--- a/projects/fmcomms2/zc706pr/system_constr.xdc
+++ b/projects/fmcomms2/zc706pr/system_constr.xdc
@@ -1,44 +0,0 @@
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \
-                -to [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}]
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}]
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*i_pn_mon* && IS_SEQUENTIAL}]
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*input_pipeline_phase* && IS_SEQUENTIAL}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*ddata_reg* && IS_SEQUENTIAL}]
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation* && IS_SEQUENTIAL}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_adc_ddata_reg*}]
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg*}]
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_re_reg* && IS_SEQUENTIAL}]
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_im_reg* && IS_SEQUENTIAL}]
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}]
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}]
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}]
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}]
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}]
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}]
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}]
-
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_re_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}]
-set_false_path  -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_im_reg*}] \
-                -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}]
-

From c39ed08edd16107b93e25443bbbc43bbea1c5895 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 6 Feb 2017 12:53:47 -0500
Subject: [PATCH 902/972] zcu102/*- actual clock == desired clock

---
 projects/common/zcu102/zcu102_system_bd.tcl | 2 ++
 projects/fmcomms5/zcu102/system_bd.tcl      | 6 ++++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/projects/common/zcu102/zcu102_system_bd.tcl b/projects/common/zcu102/zcu102_system_bd.tcl
index f79590967..0631b0fa3 100644
--- a/projects/common/zcu102/zcu102_system_bd.tcl
+++ b/projects/common/zcu102/zcu102_system_bd.tcl
@@ -2448,6 +2448,8 @@ set_property CONFIG.PSU__FPGA_PL0_ENABLE {1} $sys_ps8
 set_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} $sys_ps8
 set_property CONFIG.PSU__FPGA_PL1_ENABLE {1} $sys_ps8
 set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {200} $sys_ps8
+set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {3} $sys_ps8
+set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {2} $sys_ps8
 set_property CONFIG.PSU__USE__IRQ0 {1} $sys_ps8
 set_property CONFIG.PSU__USE__IRQ1 {1} $sys_ps8
 set_property CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} $sys_ps8
diff --git a/projects/fmcomms5/zcu102/system_bd.tcl b/projects/fmcomms5/zcu102/system_bd.tcl
index aa27c93ed..1d61e5e87 100644
--- a/projects/fmcomms5/zcu102/system_bd.tcl
+++ b/projects/fmcomms5/zcu102/system_bd.tcl
@@ -1,8 +1,10 @@
 
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
 
-set_property -dict [list CONFIG.PSU__FPGA_PL2_ENABLE {1}] $sys_ps8
-set_property -dict [list CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {200}] $sys_ps8
+set_property CONFIG.PSU__FPGA_PL2_ENABLE {1} $sys_ps8
+set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {200} $sys_ps8
+set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {3} $sys_ps8
+set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {2} $sys_ps8
 ad_connect  sys_dma_clk sys_ps8/pl_clk2
 source ../common/fmcomms5_bd.tcl
 

From 47db0d80feb9cd36060f00114cf84d645dccfdb5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 7 Feb 2017 12:29:21 +0200
Subject: [PATCH 903/972] axi_ad7616: Set up default driver value for input
 ports

---
 library/axi_ad7616/axi_ad7616_ip.tcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/library/axi_ad7616/axi_ad7616_ip.tcl b/library/axi_ad7616/axi_ad7616_ip.tcl
index 328ac97e5..36e16530f 100644
--- a/library/axi_ad7616/axi_ad7616_ip.tcl
+++ b/library/axi_ad7616/axi_ad7616_ip.tcl
@@ -21,5 +21,7 @@ adi_ip_add_core_dependencies { \
     analog.com:user:spi_engine_interconnect:1.0 \
 }
 
+set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i]
+
 ipx::save_core [ipx::current_core]
 

From 24daffcf5c97b2b3ae3abe62d1673aec4324bd49 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 7 Feb 2017 12:30:46 +0200
Subject: [PATCH 904/972] spi_engine: Set up default driver value for input
 ports

---
 library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl       | 4 ++++
 .../spi_engine_execution/spi_engine_execution_ip.tcl          | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
index 22084b53b..bb4e0e1c5 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
@@ -56,4 +56,8 @@ adi_add_bus "spi_engine_offload_ctrl0" "master" \
 
 adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"
 
+foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} {
+  set_property DRIVER_VALUE "0" [ipx::get_ports $port]
+}
+
 ipx::save_core [ipx::current_core]
diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
index d7a51e00b..f0100f65c 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
@@ -43,4 +43,8 @@ adi_add_bus "spi" "master" \
 	}
 adi_add_bus_clock "clk" "spi" "resetn"
 
+foreach port {"sdi_1" "sdi_2" "sdi_3"} {
+  set_property DRIVER_VALUE "0" [ipx::get_ports $port]
+}
+
 ipx::save_core [ipx::current_core]

From 0dae754f2d0fce3104a30041fb9cd5e5cbbf9cd3 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 10 Feb 2017 16:19:17 +0200
Subject: [PATCH 905/972] axi_adxcvr: Add rparam register to Altera XCVR

---
 library/altera/axi_adxcvr/axi_adxcvr_up.v | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v
index 0980f19d8..d09db1a5d 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v
@@ -82,6 +82,7 @@ module axi_adxcvr_up #(
 
   wire                          up_ready_s;
   wire    [31:0]                up_status_32_s;
+  wire    [31:0]                up_rparam_s;
 
   // defaults
 
@@ -135,6 +136,20 @@ module axi_adxcvr_up #(
     end
   end
 
+  // altera specific
+
+  assign up_rparam_s[31:24] = 8'd0;
+
+  // xilinx specific
+
+  assign up_rparam_s[23:16] = 8'd0;
+
+  // generic
+
+  assign up_rparam_s[15: 9] = 7'd0;
+  assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1;
+  assign up_rparam_s[ 7: 0] = NUM_OF_LANES;
+
   // read interface
 
   assign up_rack = up_rreq_d;
@@ -154,6 +169,7 @@ module axi_adxcvr_up #(
           10'h004: up_rdata_d <= {31'd0, up_resetn};
           10'h005: up_rdata_d <= {31'd0, up_status_int};
           10'h006: up_rdata_d <= up_status_32_s;
+          10'h009: up_rdata_d <= up_rparam_s;
           default: up_rdata_d <= 32'd0;
         endcase
       end else begin

From f5f1f476915d7598e017b7a376582dcbd8a0614d Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 10 Feb 2017 16:21:35 +0200
Subject: [PATCH 906/972] ad9467_fmc: Delete asynchronous clock group
 definition

This is a very bad way to handle timing. All the false path
should be defined explicitly, rather than define asynchronous clock
domains.
---
 projects/ad9467_fmc/kc705/system_constr.xdc | 3 ---
 projects/ad9467_fmc/zed/system_constr.xdc   | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/projects/ad9467_fmc/kc705/system_constr.xdc b/projects/ad9467_fmc/kc705/system_constr.xdc
index 8406a49fe..dcdcd551a 100644
--- a/projects/ad9467_fmc/kc705/system_constr.xdc
+++ b/projects/ad9467_fmc/kc705/system_constr.xdc
@@ -32,6 +32,3 @@ set_property -dict {PACKAGE_PIN Y30     IOSTANDARD LVCMOS25} [get_ports spi_sdio
 # clocks
 create_clock -name adc_clk      -period 4.00 [get_ports adc_clk_in_p]
 
-set_clock_groups -asynchronous  -group {adc_clk}
-
-
diff --git a/projects/ad9467_fmc/zed/system_constr.xdc b/projects/ad9467_fmc/zed/system_constr.xdc
index 444a99fed..8b1d5c7d3 100644
--- a/projects/ad9467_fmc/zed/system_constr.xdc
+++ b/projects/ad9467_fmc/zed/system_constr.xdc
@@ -32,6 +32,3 @@ set_property -dict {PACKAGE_PIN A21     IOSTANDARD LVCMOS25} [get_ports spi_sdio
 # clocks
 create_clock -name adc_clk      -period 4.00 [get_ports adc_clk_in_p]
 
-set_clock_groups -asynchronous  -group {adc_clk}
-
-

From 5fa6dba33373a16dbfae7dd1971216d4f2953a83 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 10 Feb 2017 16:32:58 +0200
Subject: [PATCH 907/972] Make: Update Makefiles

---
 library/Makefile                    | 6 ++++--
 library/xilinx/axi_adxcvr/Makefile  | 6 ++----
 library/xilinx/util_adxcvr/Makefile | 6 ++----
 projects/Makefile                   | 3 ---
 projects/ad6676evb/zc706/Makefile   | 1 -
 projects/fmcjesdadc1/a5gt/Makefile  | 5 -----
 projects/fmcjesdadc1/a5soc/Makefile | 5 -----
 projects/fmcjesdadc1/zc706/Makefile | 2 +-
 projects/usdrx1/zc706/Makefile      | 2 +-
 9 files changed, 10 insertions(+), 26 deletions(-)

diff --git a/library/Makefile b/library/Makefile
index 74e796dd1..c5fcf3222 100644
--- a/library/Makefile
+++ b/library/Makefile
@@ -52,7 +52,6 @@ clean:
 	make -C cn0363/cn0363_dma_sequencer clean
 	make -C cn0363/cn0363_phase_data_sync clean
 	make -C cordic_demod clean
-	make -C interfaces clean
 	make -C spi_engine/axi_spi_engine clean
 	make -C spi_engine/spi_engine_execution clean
 	make -C spi_engine/spi_engine_interconnect clean
@@ -85,6 +84,8 @@ clean:
 	make -C xilinx/axi_xcvrlb clean
 	make -C xilinx/util_adxcvr clean
 
+	make -C interfaces clean
+
 
 clean-all:clean
 
@@ -132,7 +133,6 @@ lib:
 	-make -C cn0363/cn0363_dma_sequencer
 	-make -C cn0363/cn0363_phase_data_sync
 	-make -C cordic_demod
-	-make -C interfaces
 	-make -C spi_engine/axi_spi_engine
 	-make -C spi_engine/spi_engine_execution
 	-make -C spi_engine/spi_engine_interconnect
@@ -165,5 +165,7 @@ lib:
 	-make -C xilinx/axi_xcvrlb
 	-make -C xilinx/util_adxcvr
 
+	-make -C interfaces
+
 ####################################################################################
 ####################################################################################
diff --git a/library/xilinx/axi_adxcvr/Makefile b/library/xilinx/axi_adxcvr/Makefile
index c0c41eac9..2fc386a5c 100644
--- a/library/xilinx/axi_adxcvr/Makefile
+++ b/library/xilinx/axi_adxcvr/Makefile
@@ -37,8 +37,8 @@ M_FLIST += .Xil
 
 
 
-.PHONY: all dep clean clean-all
-all: dep axi_adxcvr.xpr
+.PHONY: all clean clean-all
+all: axi_adxcvr.xpr
 
 
 clean:clean-all
@@ -52,7 +52,5 @@ axi_adxcvr.xpr: $(M_DEPS)
 	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_adxcvr_ip.tcl  >> axi_adxcvr_ip.log 2>&1
 
-dep:
-	make -C ../../interfaces
 ####################################################################################
 ####################################################################################
diff --git a/library/xilinx/util_adxcvr/Makefile b/library/xilinx/util_adxcvr/Makefile
index 7df5f8cd8..aeb58ad91 100644
--- a/library/xilinx/util_adxcvr/Makefile
+++ b/library/xilinx/util_adxcvr/Makefile
@@ -35,8 +35,8 @@ M_FLIST += .Xil
 
 
 
-.PHONY: all dep clean clean-all
-all: dep util_adxcvr.xpr
+.PHONY: all clean clean-all
+all: util_adxcvr.xpr
 
 
 clean:clean-all
@@ -50,7 +50,5 @@ util_adxcvr.xpr: $(M_DEPS)
 	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_adxcvr_ip.tcl  >> util_adxcvr_ip.log 2>&1
 
-dep:
-	make -C ../../interfaces
 ####################################################################################
 ####################################################################################
diff --git a/projects/Makefile b/projects/Makefile
index db53c0806..e3a53b392 100644
--- a/projects/Makefile
+++ b/projects/Makefile
@@ -28,7 +28,6 @@ all:
 	-make -C fmcadc4 all
 	-make -C fmcadc5 all
 	-make -C fmcjesdadc1 all
-	-make -C fmcomms1 all
 	-make -C fmcomms11 all
 	-make -C fmcomms2 all
 	-make -C fmcomms5 all
@@ -66,7 +65,6 @@ clean:
 	make -C fmcadc4 clean
 	make -C fmcadc5 clean
 	make -C fmcjesdadc1 clean
-	make -C fmcomms1 clean
 	make -C fmcomms11 clean
 	make -C fmcomms2 clean
 	make -C fmcomms5 clean
@@ -104,7 +102,6 @@ clean-all:
 	make -C fmcadc4 clean-all
 	make -C fmcadc5 clean-all
 	make -C fmcjesdadc1 clean-all
-	make -C fmcomms1 clean-all
 	make -C fmcomms11 clean-all
 	make -C fmcomms2 clean-all
 	make -C fmcomms5 clean-all
diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile
index 01f2c152a..62979f9e8 100644
--- a/projects/ad6676evb/zc706/Makefile
+++ b/projects/ad6676evb/zc706/Makefile
@@ -17,7 +17,6 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../../library/common/ad_sysref_gen.v
-M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile
index a526b8885..4b7a52062 100644
--- a/projects/fmcjesdadc1/a5gt/Makefile
+++ b/projects/fmcjesdadc1/a5gt/Makefile
@@ -53,9 +53,7 @@ M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
 M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
-M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
@@ -70,9 +68,6 @@ M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
 M_DEPS += ../../../library/scripts/adi_env.tcl
 M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile
index 109a12bb5..a66d9d27c 100644
--- a/projects/fmcjesdadc1/a5soc/Makefile
+++ b/projects/fmcjesdadc1/a5soc/Makefile
@@ -53,9 +53,7 @@ M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
 M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
 M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
 M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc
-M_DEPS += ../../../library/common/ad_axis_inf_rx.v
 M_DEPS += ../../../library/common/ad_datafmt.v
-M_DEPS += ../../../library/common/ad_mem_asym.v
 M_DEPS += ../../../library/common/ad_pnmon.v
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
@@ -70,9 +68,6 @@ M_DEPS += ../../../library/common/up_xfer_cntrl.v
 M_DEPS += ../../../library/common/up_xfer_status.v
 M_DEPS += ../../../library/scripts/adi_env.tcl
 M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
-M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
 M_DEPS += ../../../library/util_axis_fifo/address_gray.v
 M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
 M_DEPS += ../../../library/util_axis_fifo/address_sync.v
diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile
index 11949d68f..86be56155 100644
--- a/projects/fmcjesdadc1/zc706/Makefile
+++ b/projects/fmcjesdadc1/zc706/Makefile
@@ -17,7 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
-M_DEPS += ../../../library//common/ad_sysref_gen.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
 M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile
index b7c6edfb0..0d892b3f2 100644
--- a/projects/usdrx1/zc706/Makefile
+++ b/projects/usdrx1/zc706/Makefile
@@ -19,8 +19,8 @@ M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_mig.prj
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_sysref_gen.v
 M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr
 M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
 M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr

From 4e62fb0ef35bc9218871c19eca6a01c793c493d7 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 13 Feb 2017 12:02:11 +0200
Subject: [PATCH 908/972] m2k: Add reset circuitry on the logic_analyzer clock
 domain

---
 projects/m2k/common/m2k_bd.tcl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/projects/m2k/common/m2k_bd.tcl b/projects/m2k/common/m2k_bd.tcl
index 236d579c9..9ced421ff 100644
--- a/projects/m2k/common/m2k_bd.tcl
+++ b/projects/m2k/common/m2k_bd.tcl
@@ -84,6 +84,9 @@ set adc_trigger [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_trigger:1
 set axi_adc_decimate [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_decimate:1.0 axi_adc_decimate]
 set axi_dac_interpolate [create_bd_cell -type ip -vlnv analog.com:user:axi_dac_interpolate:1.0 axi_dac_interpolate]
 
+set logic_analyzer_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 logic_analyzer_reset]
+
+
 ad_connect data_i     logic_analyzer/data_i
 ad_connect trigger_i  logic_analyzer/trigger_i
 ad_connect data_o     logic_analyzer/data_o
@@ -98,6 +101,9 @@ ad_connect pattern_generator_dmac/fifo_rd_clk clk_generator/clk_0
 
 ad_connect clk_generator/clk_0  la_trigger_fifo/clk
 ad_connect logic_analyzer_dmac/fifo_wr_clk clk_generator/clk_0
+ad_connect logic_analyzer_reset/slowest_sync_clk clk_generator/clk_0
+ad_connect logic_analyzer_reset/ext_reset_in sys_rstgen/peripheral_aresetn
+ad_connect logic_analyzer_reset/bus_struct_reset la_trigger_fifo/rst
 
 ad_connect la_trigger_fifo/data_in        logic_analyzer/adc_data
 ad_connect la_trigger_fifo/data_in_valid  logic_analyzer/adc_valid

From e215a091b22832eae00b125c0bb463bf4871a12e Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 13 Feb 2017 12:02:59 +0200
Subject: [PATCH 909/972] m2k: standalone, added explicit fclk_clk0 and
 fclk_clk1 constraints

---
 projects/m2k/standalone/system_constr.xdc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc
index 0e09cdf87..ab5624d7c 100644
--- a/projects/m2k/standalone/system_constr.xdc
+++ b/projects/m2k/standalone/system_constr.xdc
@@ -65,6 +65,9 @@ create_clock -period 10.000 -name rx_clk [get_ports rx_clk]
 create_clock -period 12.500 -name trigger_clk [get_ports {trigger_bd[0]}]
 create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}]
 
+create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"]
+create_clock -name clk_fpga_1 -period  5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"]
+
 set_input_jitter clk_fpga_0 0.3
 set_input_jitter clk_fpga_1 0.15
 

From 7c86b038efc4ec6508c1bb5c18ac809a356a7c18 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 13 Feb 2017 18:05:59 +0200
Subject: [PATCH 910/972] util_fir_int: manually request data at 1/8 clock
 frequency

---
 library/util_fir_int/util_fir_int.v      | 20 ++++++++++++++++----
 library/util_fir_int/util_fir_int_ip.tcl |  1 +
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v
index 3cb7ddcad..44af4643a 100644
--- a/library/util_fir_int/util_fir_int.v
+++ b/library/util_fir_int/util_fir_int.v
@@ -42,6 +42,7 @@
 
 module util_fir_int (
   input               aclk,
+  input               s_axis_data_tvalid,
   output              s_axis_data_tready,
   input       [31:0]  s_axis_data_tdata,
   output      [15:0]  channel_0,
@@ -51,15 +52,26 @@ module util_fir_int (
   input               dac_read);
 
   wire [31:0] m_axis_data_tdata_s;
-  wire        s_axis_data_tready_s;
+
+  reg         s_axis_data_tready_r;
+  reg   [2:0] ready_counter;
+
+  always @(posedge aclk) begin
+    ready_counter <= ready_counter + 1;
+    if (ready_counter == 0) begin
+      s_axis_data_tready_r <= 1'b1;
+    end else begin
+      s_axis_data_tready_r <= 1'b0;
+    end
+  end
 
   assign {channel_1, channel_0} = (interpolate == 1'b1) ? m_axis_data_tdata_s : s_axis_data_tdata;
-  assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_s : dac_read;
+  assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_r : dac_read;
 
   fir_interp interpolator (
     .aclk(aclk),
-    .s_axis_data_tvalid(1'b1),
-    .s_axis_data_tready(s_axis_data_tready_s),
+    .s_axis_data_tvalid(s_axis_data_tvalid),
+    .s_axis_data_tready(),
     .s_axis_data_tdata(s_axis_data_tdata),
     .m_axis_data_tvalid(m_axis_data_tvalid),
     .m_axis_data_tdata(m_axis_data_tdata_s)
diff --git a/library/util_fir_int/util_fir_int_ip.tcl b/library/util_fir_int/util_fir_int_ip.tcl
index 83d0b2dac..9c44dbab0 100644
--- a/library/util_fir_int/util_fir_int_ip.tcl
+++ b/library/util_fir_int/util_fir_int_ip.tcl
@@ -12,6 +12,7 @@ CONFIG.Coefficient_Fractional_Bits {0} \
 CONFIG.Data_Fractional_Bits {15} \
 CONFIG.Coefficient_Sets {1} \
 CONFIG.Coefficient_Sign {Signed} \
+CONFIG.S_DATA_Has_FIFO {true} \
 CONFIG.Coefficient_Structure {Inferred} \
 CONFIG.Coefficient_Width {16} \
 CONFIG.ColumnConfig {5} \

From a569b6bf0c69129c4f669a6f0be29f328ef7d9b0 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 13 Feb 2017 18:08:52 +0200
Subject: [PATCH 911/972] pluto: Interpolation, connect fifo_rd_valid to
 s_axis_data_tvalid

---
 projects/pluto/system_bd.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/projects/pluto/system_bd.tcl b/projects/pluto/system_bd.tcl
index aab659151..2708403a4 100644
--- a/projects/pluto/system_bd.tcl
+++ b/projects/pluto/system_bd.tcl
@@ -228,6 +228,7 @@ ad_connect fir_decimator/decimate decim_slice/Dout
 
 ad_connect axi_ad9361/l_clk fir_interpolator/aclk
 ad_connect axi_ad9361_dac_dma/fifo_rd_dout fir_interpolator/s_axis_data_tdata
+ad_connect axi_ad9361_dac_dma/fifo_rd_valid fir_interpolator/s_axis_data_tvalid
 ad_connect axi_ad9361/dac_valid_i0 fir_interpolator/dac_read
 ad_connect axi_ad9361_dac_dma/fifo_rd_en fir_interpolator/s_axis_data_tready
 ad_connect axi_ad9361/dac_data_i0 fir_interpolator/channel_0

From c6ee76421b257787b8d18496612e161117da3220 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 14 Feb 2017 11:48:07 +0200
Subject: [PATCH 912/972] axi_usb_fx3: Fixed clock domain association

---
 library/axi_usb_fx3/axi_usb_fx3_ip.tcl | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
index 58dcad9f8..cd4a33526 100644
--- a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
+++ b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl
@@ -12,9 +12,10 @@ adi_ip_files axi_usb_fx3 [list \
   "axi_usb_fx3.v"]
 
 adi_ip_properties axi_usb_fx3
+
 adi_ip_infer_streaming_interfaces axi_usb_fx3
 
-adi_add_bus_clock "s_axi_aclk" "s_axis"
-adi_add_bus_clock "s_axi_aclk" "m_axis"
+ipx::associate_bus_interfaces -busif m_axis -clock s_axi_aclk [ipx::current_core]
+ipx::associate_bus_interfaces -busif s_axis -clock s_axi_aclk [ipx::current_core]
 
 ipx::save_core [ipx::current_core]

From 46883731eb77b86dd78a0856c1f401f3f7a98a05 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 14 Feb 2017 11:50:06 +0200
Subject: [PATCH 913/972] pzsdr1: Don't set a disabled parameter

---
 projects/pzsdr1/common/pzsdr1_bd.tcl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/projects/pzsdr1/common/pzsdr1_bd.tcl b/projects/pzsdr1/common/pzsdr1_bd.tcl
index f955ed8e9..e99c558b4 100644
--- a/projects/pzsdr1/common/pzsdr1_bd.tcl
+++ b/projects/pzsdr1/common/pzsdr1_bd.tcl
@@ -209,7 +209,6 @@ set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
-set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma

From acef0113d1039c33d955a778af9bc300c886d29e Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 14 Feb 2017 11:50:37 +0200
Subject: [PATCH 914/972] pzsdr1: ccusb, connect unused clock pins to GND

---
 projects/pzsdr1/common/ccusb_bd.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/pzsdr1/common/ccusb_bd.tcl b/projects/pzsdr1/common/ccusb_bd.tcl
index dee7493c1..c656a53dd 100644
--- a/projects/pzsdr1/common/ccusb_bd.tcl
+++ b/projects/pzsdr1/common/ccusb_bd.tcl
@@ -1,4 +1,7 @@
 
+ad_connect  sys_ps7/ENET1_GMII_RX_CLK GND
+ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
+
 create_bd_port -dir I usb_fx3_uart_tx
 create_bd_port -dir O usb_fx3_uart_rx
 

From 6a9b7580dee465bf929ea62ae4f832ba15929357 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 14 Feb 2017 11:54:46 +0200
Subject: [PATCH 915/972] pzsdr1: ccusb, renamed clk_out to clkout_in

---
 projects/pzsdr1/ccusb_lvds/system_top.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/pzsdr1/ccusb_lvds/system_top.v b/projects/pzsdr1/ccusb_lvds/system_top.v
index 426658da6..77536b9da 100644
--- a/projects/pzsdr1/ccusb_lvds/system_top.v
+++ b/projects/pzsdr1/ccusb_lvds/system_top.v
@@ -80,7 +80,7 @@ module system_top (
 
   output          enable,
   output          txnrx,
-  input           clk_out,
+  input           clkout_in,
 
   inout           gpio_clksel,
   inout           gpio_resetb,

From fa37f4dd0aefcb17e032ebfad90249e689aee49e Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 14 Feb 2017 11:56:08 +0200
Subject: [PATCH 916/972] pzsdr2: Don't set a disabled parameter

---
 projects/pzsdr2/common/pzsdr2_bd.tcl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/projects/pzsdr2/common/pzsdr2_bd.tcl b/projects/pzsdr2/common/pzsdr2_bd.tcl
index 98b769f81..f265bcfb6 100644
--- a/projects/pzsdr2/common/pzsdr2_bd.tcl
+++ b/projects/pzsdr2/common/pzsdr2_bd.tcl
@@ -209,7 +209,6 @@ set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
-set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma

From 27119343f21d1e5305f5bc6862e4dfe86742d9ab Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 14 Feb 2017 11:56:54 +0200
Subject: [PATCH 917/972] pzsdr2: ccusb, connect unused clock pins to GND

---
 projects/pzsdr2/common/ccusb_bd.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/pzsdr2/common/ccusb_bd.tcl b/projects/pzsdr2/common/ccusb_bd.tcl
index dee7493c1..c656a53dd 100644
--- a/projects/pzsdr2/common/ccusb_bd.tcl
+++ b/projects/pzsdr2/common/ccusb_bd.tcl
@@ -1,4 +1,7 @@
 
+ad_connect  sys_ps7/ENET1_GMII_RX_CLK GND
+ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
+
 create_bd_port -dir I usb_fx3_uart_tx
 create_bd_port -dir O usb_fx3_uart_rx
 

From 46290193f39f93b2d0ea3a1c0e35d54ace10f137 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 14 Feb 2017 11:58:11 +0200
Subject: [PATCH 918/972] pzsdr2: ccusb, renamed clk_out to clkout_in

---
 projects/pzsdr2/ccusb_lvds/system_top.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/pzsdr2/ccusb_lvds/system_top.v b/projects/pzsdr2/ccusb_lvds/system_top.v
index 426658da6..77536b9da 100644
--- a/projects/pzsdr2/ccusb_lvds/system_top.v
+++ b/projects/pzsdr2/ccusb_lvds/system_top.v
@@ -80,7 +80,7 @@ module system_top (
 
   output          enable,
   output          txnrx,
-  input           clk_out,
+  input           clkout_in,
 
   inout           gpio_clksel,
   inout           gpio_resetb,

From 86c279c238efe1d6c08f993512f80fc39101154e Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 14 Feb 2017 14:51:49 +0200
Subject: [PATCH 919/972] pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix
 critical warnings

---
 projects/pzsdr1/common/ccbox_bd.tcl | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/projects/pzsdr1/common/ccbox_bd.tcl b/projects/pzsdr1/common/ccbox_bd.tcl
index a60e9dd58..0b2c89ea0 100644
--- a/projects/pzsdr1/common/ccbox_bd.tcl
+++ b/projects/pzsdr1/common/ccbox_bd.tcl
@@ -8,8 +8,8 @@ ad_connect  sys_ps7/ENET1_GMII_TX_CLK GND
 
 set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
+set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7]
 set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
-set_property CONFIG.PCW_USE_DMA2 1 [get_bd_cells sys_ps7]
 
 # i2s
 
@@ -30,14 +30,14 @@ ad_connect  sys_200m_clk sys_audio_clkgen/clk_in1
 ad_connect  sys_cpu_resetn sys_audio_clkgen/resetn
 ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
 ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
+ad_connect  sys_cpu_clk sys_ps7/DMA0_ACLK
 ad_connect  sys_cpu_clk sys_ps7/DMA1_ACLK
-ad_connect  sys_cpu_clk sys_ps7/DMA2_ACLK
 ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
 ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
-ad_connect  sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
-ad_connect  sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
-ad_connect  sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
-ad_connect  sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
+ad_connect  sys_ps7/DMA0_REQ axi_i2s_adi/DMA_REQ_TX
+ad_connect  sys_ps7/DMA0_ACK axi_i2s_adi/DMA_ACK_TX
+ad_connect  sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_RX
+ad_connect  sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_RX
 ad_connect  sys_audio_clkgen/clk_out1 i2s_mclk
 ad_connect  sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
 ad_connect  i2s axi_i2s_adi/I2S

From 358aa48c7675f05207dcb25de870308be75bcbd0 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 15 Feb 2017 11:38:12 +0200
Subject: [PATCH 920/972] axi_adc_decimate: Fix assignment width

---
 library/axi_adc_decimate/axi_adc_decimate.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_adc_decimate/axi_adc_decimate.v b/library/axi_adc_decimate/axi_adc_decimate.v
index 66cb7c25d..03908a42d 100644
--- a/library/axi_adc_decimate/axi_adc_decimate.v
+++ b/library/axi_adc_decimate/axi_adc_decimate.v
@@ -191,7 +191,7 @@ module axi_adc_decimate(
       16'h3: decim_rate_cic = 16'd500;
       16'h6: decim_rate_cic = 16'd5000;
       16'h7: decim_rate_cic = 16'd50000;
-      default: decim_rate_cic = 9'd1;
+      default: decim_rate_cic = 16'd1;
     endcase
   end
 

From 07184b31d291b3388c36f7a9d7a275cf94c83a20 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 16 Feb 2017 12:35:24 +0200
Subject: [PATCH 921/972] fmcadc2: Define default clock selection for Xilinx
 GTs

---
 projects/fmcadc2/vc707/system_bd.tcl | 3 +++
 projects/fmcadc2/zc706/system_bd.tcl | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/projects/fmcadc2/vc707/system_bd.tcl b/projects/fmcadc2/vc707/system_bd.tcl
index b9644f373..e01b765fd 100644
--- a/projects/fmcadc2/vc707/system_bd.tcl
+++ b/projects/fmcadc2/vc707/system_bd.tcl
@@ -6,4 +6,7 @@ p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 18
 
 source ../common/fmcadc2_bd.tcl
 
+set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] [get_bd_cells axi_ad9625_xcvr]
+set_property -dict [list CONFIG.SYS_CLK_SEL {0}] [get_bd_cells axi_ad9625_xcvr]
+set_property -dict [list CONFIG.OUT_CLK_SEL {2}] [get_bd_cells axi_ad9625_xcvr]
 
diff --git a/projects/fmcadc2/zc706/system_bd.tcl b/projects/fmcadc2/zc706/system_bd.tcl
index f7567d53a..b122c4b2e 100644
--- a/projects/fmcadc2/zc706/system_bd.tcl
+++ b/projects/fmcadc2/zc706/system_bd.tcl
@@ -21,3 +21,7 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
 
 source ../common/fmcadc2_bd.tcl
 
+set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] [get_bd_cells axi_ad9625_xcvr]
+set_property -dict [list CONFIG.SYS_CLK_SEL {0}] [get_bd_cells axi_ad9625_xcvr]
+set_property -dict [list CONFIG.OUT_CLK_SEL {2}] [get_bd_cells axi_ad9625_xcvr]
+

From 343d0472d484e1d14f5a407db84b5d848efe2986 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 16 Feb 2017 14:56:25 +0200
Subject: [PATCH 922/972] fmcadc2: Move GT setting to common/system_bd.tcl

---
 projects/fmcadc2/common/fmcadc2_bd.tcl | 3 +++
 projects/fmcadc2/vc707/system_bd.tcl   | 4 ----
 projects/fmcadc2/zc706/system_bd.tcl   | 4 ----
 3 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl
index ab24416bb..0d81a4f6d 100644
--- a/projects/fmcadc2/common/fmcadc2_bd.tcl
+++ b/projects/fmcadc2/common/fmcadc2_bd.tcl
@@ -10,6 +10,9 @@ set axi_ad9625_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.
 set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_xcvr
+set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] $axi_ad9625_xcvr
+set_property -dict [list CONFIG.SYS_CLK_SEL {0}] $axi_ad9625_xcvr
+set_property -dict [list CONFIG.OUT_CLK_SEL {2}] $axi_ad9625_xcvr
 
 set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
diff --git a/projects/fmcadc2/vc707/system_bd.tcl b/projects/fmcadc2/vc707/system_bd.tcl
index e01b765fd..b92c89f02 100644
--- a/projects/fmcadc2/vc707/system_bd.tcl
+++ b/projects/fmcadc2/vc707/system_bd.tcl
@@ -6,7 +6,3 @@ p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 18
 
 source ../common/fmcadc2_bd.tcl
 
-set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] [get_bd_cells axi_ad9625_xcvr]
-set_property -dict [list CONFIG.SYS_CLK_SEL {0}] [get_bd_cells axi_ad9625_xcvr]
-set_property -dict [list CONFIG.OUT_CLK_SEL {2}] [get_bd_cells axi_ad9625_xcvr]
-
diff --git a/projects/fmcadc2/zc706/system_bd.tcl b/projects/fmcadc2/zc706/system_bd.tcl
index b122c4b2e..f7567d53a 100644
--- a/projects/fmcadc2/zc706/system_bd.tcl
+++ b/projects/fmcadc2/zc706/system_bd.tcl
@@ -21,7 +21,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
 
 source ../common/fmcadc2_bd.tcl
 
-set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] [get_bd_cells axi_ad9625_xcvr]
-set_property -dict [list CONFIG.SYS_CLK_SEL {0}] [get_bd_cells axi_ad9625_xcvr]
-set_property -dict [list CONFIG.OUT_CLK_SEL {2}] [get_bd_cells axi_ad9625_xcvr]
-

From 8453d758c207503d5e0d28752729f3a039f963cd Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 16 Feb 2017 19:20:49 +0200
Subject: [PATCH 923/972] scripts: If an altera project doesn't meet timing,
 rename the sof

---
 projects/scripts/adi_tquest.tcl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/projects/scripts/adi_tquest.tcl b/projects/scripts/adi_tquest.tcl
index 59abc8c0a..1b4b520d8 100755
--- a/projects/scripts/adi_tquest.tcl
+++ b/projects/scripts/adi_tquest.tcl
@@ -14,5 +14,11 @@ if {$slack > 0} {
 }
 
 if {$slack < 0} {
+  set sof_files [glob *.sof]
+  foreach sof_file in sof_files {
+    set root_sof_file [file rootname $sof_file]
+    set new_sof_file [append root_sof_file "_timing.sof"]
+    file rename -force $sof_file $new_sof_file
+  }
   return -code error [format "ERROR: Timing Constraints NOT met!"]
 }

From 95a4ea20c8456677e46aa2762ab6aac6c23e57f7 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 16 Feb 2017 19:53:44 +0200
Subject: [PATCH 924/972] axi_dacfifo: Delete redundant parameter BYPASS_EN

---
 library/xilinx/axi_dacfifo/axi_dacfifo.v      | 44 +++++++------------
 .../zc706/zc706_system_plddr3_dacfifo.tcl     |  1 -
 2 files changed, 16 insertions(+), 29 deletions(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index 496360775..88077d018 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -118,7 +118,6 @@ module axi_dacfifo (
   parameter   AXI_ADDRESS = 32'h00000000;
   parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
   parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
-  parameter   BYPASS_EN = 1;
 
   // dma interface
 
@@ -311,34 +310,23 @@ module axi_dacfifo (
 
   // bypass logic
 
-  generate if (BYPASS_EN == 1) begin
+  util_axis_resize #(
+    .MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
+    .SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
+  ) i_util_axis_resize (
+    .clk (axi_clk),
+    .resetn (axi_resetn),
+    .s_valid (dma_valid),
+    .s_ready (dma_ready_bp_s),
+    .s_data (dma_data),
+    .m_valid (dma_valid_bp_s),
+    .m_ready (axi_rd_ready_s),
+    .m_data (dma_data_bp_s)
+  );
 
-    util_axis_resize #(
-      .MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
-      .SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
-    ) i_util_axis_resize (
-      .clk (axi_clk),
-      .resetn (axi_resetn),
-      .s_valid (dma_valid),
-      .s_ready (dma_ready_bp_s),
-      .s_data (dma_data),
-      .m_valid (dma_valid_bp_s),
-      .m_ready (axi_rd_ready_s),
-      .m_data (dma_data_bp_s)
-    );
-
-    assign  dac_rd_valid_s = (dac_fifo_bypass) ? dma_valid_bp_s : axi_rd_valid_s;
-    assign  dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
-    assign  dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
-
-  end else begin
-
-    assign  dac_rd_valid_s = axi_rd_valid_s;
-    assign  dac_rd_data_s = axi_rd_data_s;
-    assign  dma_ready = dma_ready_s;
-
-  end
-  endgenerate
+  assign  dac_rd_valid_s = (dac_fifo_bypass) ? dma_valid_bp_s : axi_rd_valid_s;
+  assign  dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
+  assign  dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
 
 endmodule
 
diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index 13cc3cb3f..735870609 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -50,7 +50,6 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   set_property -dict [list CONFIG.AXI_LENGTH {15}] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo
-  set_property -dict [list CONFIG.BYPASS_EN {1}] $axi_dacfifo
 
   ## clock and reset
 

From f10866e4c3b1744d326b7dc26c9275b5e73be4af Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 16 Feb 2017 19:54:41 +0200
Subject: [PATCH 925/972] axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter

---
 library/xilinx/axi_adcfifo/axi_adcfifo.v | 3 +--
 library/xilinx/axi_dacfifo/axi_dacfifo.v | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo.v b/library/xilinx/axi_adcfifo/axi_adcfifo.v
index 99b1f2a1b..831ff4c33 100644
--- a/library/xilinx/axi_adcfifo/axi_adcfifo.v
+++ b/library/xilinx/axi_adcfifo/axi_adcfifo.v
@@ -115,7 +115,6 @@ module axi_adcfifo (
   parameter   AXI_LENGTH = 16;
   parameter   AXI_ADDRESS = 32'h00000000;
   parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
-  parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
 
   // adc interface
 
@@ -152,7 +151,7 @@ module axi_adcfifo (
   input                           axi_awready;
   output                          axi_wvalid;
   output  [AXI_DATA_WIDTH-1:0]    axi_wdata;
-  output  [AXI_BYTE_WIDTH-1:0]    axi_wstrb;
+  output  [(AXI_DATA_WIDTH/8)-1:0]  axi_wstrb;
   output                          axi_wlast;
   output  [  3:0]                 axi_wuser;
   input                           axi_wready;
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index 88077d018..2194b797a 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -117,7 +117,6 @@ module axi_dacfifo (
   parameter   AXI_LENGTH = 15;
   parameter   AXI_ADDRESS = 32'h00000000;
   parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
-  parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
 
   // dma interface
 
@@ -157,7 +156,7 @@ module axi_dacfifo (
   input                               axi_awready;
   output                              axi_wvalid;
   output  [(AXI_DATA_WIDTH-1):0]      axi_wdata;
-  output  [(AXI_BYTE_WIDTH-1):0]      axi_wstrb;
+  output  [(AXI_DATA_WIDTH/8-1):0]    axi_wstrb;
   output                              axi_wlast;
   output  [  3:0]                     axi_wuser;
   input                               axi_wready;

From e8bcbb74da91529911ee991f6730d6fee1d71ccc Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 16 Feb 2017 21:21:51 +0200
Subject: [PATCH 926/972] scripts: fixed tcl syntax for altera projects not
 meeting timing

---
 projects/scripts/adi_tquest.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/scripts/adi_tquest.tcl b/projects/scripts/adi_tquest.tcl
index 1b4b520d8..a8f5d4a7f 100755
--- a/projects/scripts/adi_tquest.tcl
+++ b/projects/scripts/adi_tquest.tcl
@@ -15,7 +15,7 @@ if {$slack > 0} {
 
 if {$slack < 0} {
   set sof_files [glob *.sof]
-  foreach sof_file in sof_files {
+  foreach sof_file $sof_files {
     set root_sof_file [file rootname $sof_file]
     set new_sof_file [append root_sof_file "_timing.sof"]
     file rename -force $sof_file $new_sof_file

From 3e5054247b26982fa220ee382747e4a576cf744b Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 17 Feb 2017 11:08:50 +0200
Subject: [PATCH 927/972] scripts: For altera projects, when it doesn't meet
 timing rename the generated sof

---
 projects/scripts/adi_tquest.tcl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/projects/scripts/adi_tquest.tcl b/projects/scripts/adi_tquest.tcl
index 59abc8c0a..a8f5d4a7f 100755
--- a/projects/scripts/adi_tquest.tcl
+++ b/projects/scripts/adi_tquest.tcl
@@ -14,5 +14,11 @@ if {$slack > 0} {
 }
 
 if {$slack < 0} {
+  set sof_files [glob *.sof]
+  foreach sof_file $sof_files {
+    set root_sof_file [file rootname $sof_file]
+    set new_sof_file [append root_sof_file "_timing.sof"]
+    file rename -force $sof_file $new_sof_file
+  }
   return -code error [format "ERROR: Timing Constraints NOT met!"]
 }

From 981a61bf162c10c287d729422a1de6046e6fa91e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 17 Feb 2017 18:40:02 +0200
Subject: [PATCH 928/972] axi_dacfifo: Clean up the axi_dacfifo_wr.v module

---
 library/xilinx/axi_dacfifo/axi_dacfifo_wr.v | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
index e3e4ddb7d..332f9b006 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
@@ -198,7 +198,7 @@ module axi_dacfifo_wr (
   reg                                       axi_reset = 1'b0;
   reg                                       axi_xfer_out = 1'b0;
   reg     [31:0]                            axi_last_addr = 32'b0;
-  reg     [ 3:0]                            axi_last_beats = 15'b0;
+  reg     [ 3:0]                            axi_last_beats = 4'b0;
   reg                                       axi_awvalid = 1'b0;
   reg     [31:0]                            axi_awaddr = 32'b0;
   reg                                       axi_xfer_init = 1'b0;
@@ -317,7 +317,7 @@ module axi_dacfifo_wr (
       dma_last_beats <= 4'b0;
     end else begin
       if ((dma_ready == 1'b1) && (dma_valid == 1'b1)) begin
-        dma_last_beats <= (dma_last_beats < MEM_RATIO-1) ? dma_last_beats + 1 : 0;
+        dma_last_beats <= (dma_last_beats < MEM_RATIO-1) ? dma_last_beats + 4'b1 : 4'b0;
       end
     end
   end
@@ -341,7 +341,7 @@ module axi_dacfifo_wr (
     end else begin
       dma_mem_last_read_toggle_m = {dma_mem_last_read_toggle_m[1:0], axi_mem_last_read_toggle};
       if (dma_mem_wea_s == 1'b1) begin
-        dma_mem_waddr <= dma_mem_waddr + 8'b1;
+        dma_mem_waddr <= dma_mem_waddr + 1;
         if (dma_xfer_last == 1'b1) begin
           if (dma_last_beats != (MEM_RATIO - 1)) begin
             dma_mem_waddr <= dma_mem_waddr + (MEM_RATIO - dma_last_beats);
@@ -417,9 +417,7 @@ module axi_dacfifo_wr (
     if (axi_resetn == 1'b0) begin
       axi_endof_transaction <= 1'b0;
       axi_endof_transaction_d <= 1'b0;
-      axi_mem_addr_diff <= 'b0;
     end else begin
-     axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0];
      axi_endof_transaction_d <= axi_endof_transaction;
      if ((axi_xfer_req_m[4] == 1'b1) && (axi_xfer_last_m[4] == 1'b1) && (axi_xfer_last_m[3] == 1'b0)) begin
         axi_endof_transaction <= 1'b1;
@@ -470,7 +468,7 @@ module axi_dacfifo_wr (
       axi_mem_raddr <= 'b0;
       axi_wvalid_counter <= 4'b0;
       axi_mem_last_read_toggle <= 1'b1;
-      axi_mem_raddr_g <= 8'b0;
+      axi_mem_raddr_g <= 'b0;
     end else begin
       axi_mem_rvalid <= axi_mem_rvalid_s;
       axi_mem_rvalid_d <= axi_mem_rvalid;
@@ -479,7 +477,7 @@ module axi_dacfifo_wr (
       axi_mem_rdata <= axi_mem_rdata_s;
       if (axi_mem_rvalid_s == 1'b1) begin
         axi_mem_raddr <= axi_mem_raddr + 1;
-        axi_wvalid_counter <= ((axi_wvalid_counter == axi_awlen) || (axi_xfer_init == 1'b1)) ? 4'b0 : axi_wvalid_counter + 1;
+        axi_wvalid_counter <= ((axi_wvalid_counter == axi_awlen) || (axi_xfer_init == 1'b1)) ? 4'b0 : axi_wvalid_counter + 4'b1;
       end
       if ((axi_endof_transaction == 1'b0) && (axi_endof_transaction_d == 1'b1)) begin
         axi_mem_raddr <= 'b0;

From cb3d1883bc59b418fa45cc04da6cd0466d3502ac Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 17 Feb 2017 15:21:33 -0500
Subject: [PATCH 929/972] fmcjesdadc1/a5gt- hard placement of ddr hr/qr
 registers

---
 projects/common/a5gt/a5gt_system_assign.tcl | 47 +++++++++++++++++++++
 projects/fmcjesdadc1/a5gt/system_constr.sdc |  4 +-
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/projects/common/a5gt/a5gt_system_assign.tcl b/projects/common/a5gt/a5gt_system_assign.tcl
index 474afa6ca..2247d763c 100644
--- a/projects/common/a5gt/a5gt_system_assign.tcl
+++ b/projects/common/a5gt/a5gt_system_assign.tcl
@@ -774,6 +774,53 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[10]
 set_instance_assignment -name OPTIMIZATION_TECHNIQUE SPEED -to *
 set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -to *
 
+set_location_assignment FF_X25_Y136_N31  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucke_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X25_Y136_N1   -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucke_qr_to_hr|dataout_r[0][1]
+set_location_assignment FF_X15_Y136_N56  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucs_n_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X15_Y136_N2   -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucs_n_qr_to_hr|dataout_r[0][1]
+set_location_assignment FF_X18_Y136_N5   -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X18_Y136_N14  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][1]
+set_location_assignment FF_X18_Y136_N35  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][2]
+set_location_assignment FF_X18_Y136_N56  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][3]
+set_location_assignment FF_X18_Y136_N38  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][4]
+set_location_assignment FF_X18_Y136_N29  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][5]
+set_location_assignment FF_X25_Y136_N14  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X25_Y136_N17  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][1]
+set_location_assignment FF_X25_Y136_N50  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][2]
+set_location_assignment FF_X25_Y136_N44  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][3]
+set_location_assignment FF_X21_Y136_N31  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][4]
+set_location_assignment FF_X21_Y136_N55  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][5]
+set_location_assignment FF_X21_Y136_N43  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][6]
+set_location_assignment FF_X21_Y136_N16  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][7]
+set_location_assignment FF_X20_Y136_N13  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][8]
+set_location_assignment FF_X20_Y136_N37  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][9]
+set_location_assignment FF_X20_Y136_N43  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][10]
+set_location_assignment FF_X20_Y136_N55  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][11]
+set_location_assignment FF_X18_Y136_N22  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][12]
+set_location_assignment FF_X25_Y136_N41  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][13]
+set_location_assignment FF_X25_Y136_N38  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][14]
+set_location_assignment FF_X25_Y136_N35  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][15]
+set_location_assignment FF_X25_Y136_N8   -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][16]
+set_location_assignment FF_X21_Y136_N58  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][17]
+set_location_assignment FF_X21_Y136_N40  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][18]
+set_location_assignment FF_X21_Y136_N7   -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][19]
+set_location_assignment FF_X21_Y136_N49  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][20]
+set_location_assignment FF_X20_Y136_N7   -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][21]
+set_location_assignment FF_X20_Y136_N49  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][22]
+set_location_assignment FF_X20_Y136_N25  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][23]
+set_location_assignment FF_X20_Y136_N31  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][24]
+set_location_assignment FF_X18_Y136_N49  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][25]
+set_location_assignment FF_X28_Y136_N47  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ureset_n_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X28_Y136_N26  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ureset_n_qr_to_hr|dataout_r[0][1]
+set_location_assignment FF_X18_Y136_N47  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uras_n_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X18_Y136_N8   -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uras_n_qr_to_hr|dataout_r[0][1]
+set_location_assignment FF_X15_Y136_N7   -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucas_n_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X15_Y136_N34  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucas_n_qr_to_hr|dataout_r[0][1]
+set_location_assignment FF_X15_Y136_N52  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uwe_n_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X15_Y136_N40  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uwe_n_qr_to_hr|dataout_r[0][1]
+set_location_assignment FF_X15_Y136_N13  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uodt_qr_to_hr|dataout_r[0][0]
+set_location_assignment FF_X15_Y136_N43  -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uodt_qr_to_hr|dataout_r[0][1]
+
 # source defaults
 
 source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc
index b4216038d..d9369ae46 100644
--- a/projects/fmcjesdadc1/a5gt/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc
@@ -27,6 +27,8 @@ set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|alter
 
 if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} {
   set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \
-    -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 2
+    -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 0.150
+  set_min_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \
+    -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 0.000
 }
 

From a15e05c4977b3d14c8d8416dcb3e02e87c77dd4b Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Fri, 17 Feb 2017 15:29:10 -0500
Subject: [PATCH 930/972] adcfifo- remove axi-byte-width parameter

---
 projects/common/zc706/zc706_system_plddr3_adcfifo.tcl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
index 4460b7d72..23c2c95d3 100644
--- a/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
@@ -47,7 +47,6 @@ proc p_plddr3_adcfifo {p_name m_name adc_data_width} {
   set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_adcfifo
   set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_adcfifo
   set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_adcfifo
-  set_property -dict [list CONFIG.AXI_BYTE_WIDTH {64}] $axi_adcfifo
 
   ad_connect  sys_rst axi_ddr_cntrl/sys_rst
   ad_connect  sys_clk axi_ddr_cntrl/SYS_CLK

From 040b61de608ddda16fb8788ff68ab0d2a0fa44b3 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 20 Feb 2017 17:13:58 +0200
Subject: [PATCH 931/972] fmcadc5: Updated default parameters

---
 projects/fmcadc5/common/fmcadc5_bd.tcl | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl
index fef366da6..e1f008564 100644
--- a/projects/fmcadc5/common/fmcadc5_bd.tcl
+++ b/projects/fmcadc5/common/fmcadc5_bd.tcl
@@ -2,35 +2,44 @@
 
 set util_fmcadc5_0_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc5_0_xcvr]
 set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc5_0_xcvr
-set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {1}] $util_fmcadc5_0_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc5_0_xcvr
 set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc5_0_xcvr
 set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc5_0_xcvr
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_xcvr
 set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc5_0_xcvr
 set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc5_0_xcvr
-set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0954}] $util_fmcadc5_0_xcvr
 set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc5_0_xcvr
+set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_fmcadc5_0_xcvr
 set util_fmcadc5_1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc5_1_xcvr]
 set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc5_1_xcvr
-set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {1}] $util_fmcadc5_1_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc5_1_xcvr
 set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc5_1_xcvr
 set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc5_1_xcvr
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_xcvr
 set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc5_1_xcvr
 set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc5_1_xcvr
-set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0954}] $util_fmcadc5_1_xcvr
 set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc5_1_xcvr
+set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_fmcadc5_1_xcvr
 
 set axi_ad9625_0_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_0_xcvr]
 set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_0_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_0_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_0_xcvr
+set_property -dict [list CONFIG.LPM_OR_DFE_N {0}] $axi_ad9625_0_xcvr
+set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] $axi_ad9625_0_xcvr
+set_property -dict [list CONFIG.OUT_CLK_SEL {"010"}] $axi_ad9625_0_xcvr
+
 set axi_ad9625_1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_1_xcvr]
 set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_1_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_1_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_1_xcvr
+set_property -dict [list CONFIG.LPM_OR_DFE_N {0}] $axi_ad9625_1_xcvr
+set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] $axi_ad9625_1_xcvr
+set_property -dict [list CONFIG.OUT_CLK_SEL {"010"}] $axi_ad9625_1_xcvr
 
 set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_0_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd

From 434d1ea52cc7344ce668622b93dcfa47e71a6c2b Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 21 Feb 2017 14:45:18 +0200
Subject: [PATCH 932/972] axi_dacfifo: Fix constraints

---
 library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
index 8942ef3d9..d3ea6a0a4 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
@@ -1,8 +1,10 @@
 
-set_property shreg_extract no [get_cells -hier -filter {name =~ *xfer_req_m*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *xfer_last_m*}]
+set_property ASYNC_REG TRUE \
+  [get_cells -hier *_xfer_req_m[0]*] \
+  [get_cells -hier *_xfer_last_m[0]*]
 
-set_false_path -to [get_cells axi_xfer_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -to [get_cells *_xfer_req_m[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -to [get_cells *_xfer_last_m[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
 set_false_path -to [get_cells *dma_rst_m1* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
 
 set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \

From b30041f7f382cffc3b78c0707f27a2fd86514c80 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 23 Feb 2017 17:32:31 +0200
Subject: [PATCH 933/972] axi_dacfifo: Redesign the bypass functionality

---
 library/xilinx/axi_dacfifo/Makefile           |   1 +
 library/xilinx/axi_dacfifo/axi_dacfifo.v      |  89 ++++--
 .../xilinx/axi_dacfifo/axi_dacfifo_bypass.v   | 292 ++++++++++++++++++
 .../xilinx/axi_dacfifo/axi_dacfifo_constr.xdc |  39 ++-
 library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl |   1 +
 library/xilinx/axi_dacfifo/axi_dacfifo_wr.v   |  12 +-
 .../zc706/zc706_system_plddr3_dacfifo.tcl     |   2 +-
 7 files changed, 390 insertions(+), 46 deletions(-)
 create mode 100644 library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v

diff --git a/library/xilinx/axi_dacfifo/Makefile b/library/xilinx/axi_dacfifo/Makefile
index 6eefaa5ad..468a9e6d0 100644
--- a/library/xilinx/axi_dacfifo/Makefile
+++ b/library/xilinx/axi_dacfifo/Makefile
@@ -16,6 +16,7 @@ M_DEPS += axi_dacfifo_dac.v
 M_DEPS += axi_dacfifo_ip.tcl
 M_DEPS += axi_dacfifo_rd.v
 M_DEPS += axi_dacfifo_wr.v
+M_DEPS += axi_dacfifo_bypass.v
 
 M_VIVADO := vivado -mode batch -source
 
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index 2194b797a..e619ef07a 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -59,7 +59,7 @@ module axi_dacfifo (
   dac_dunf,
   dac_xfer_out,
 
-  dac_fifo_bypass,
+  bypass,
 
   // axi interface
 
@@ -136,7 +136,7 @@ module axi_dacfifo (
   output                              dac_dunf;
   output                              dac_xfer_out;
 
-  input                               dac_fifo_bypass;
+  input                               bypass;
 
   // axi interface
 
@@ -185,6 +185,17 @@ module axi_dacfifo (
   input   [(AXI_DATA_WIDTH-1):0]      axi_rdata;
   output                              axi_rready;
 
+  reg                                 dma_ready = 1'b0;
+  reg                                 dma_bypass_m1 = 1'b0;
+  reg                                 dma_bypass = 1'b0;
+  reg                                 dac_bypass_m1 = 1'b0;
+  reg                                 dac_bypass = 1'b0;
+  reg                                 dac_xfer_out = 1'b0;
+  reg                                 dac_xfer_out_m1 = 1'b0;
+  reg                                 dac_xfer_out_bypass = 1'b0;
+  reg                                 dac_dunf = 1'b0;
+  reg     [(DAC_DATA_WIDTH-1):0]      dac_data = 'b0;
+
   // internal signals
 
   wire    [(AXI_DATA_WIDTH-1):0]      axi_wr_data_s;
@@ -206,6 +217,12 @@ module axi_dacfifo (
   wire                                dma_valid_bp_s;
   wire    [(AXI_DATA_WIDTH-1):0]      dma_data_bp_s;
   wire                                dma_ready_bp_s;
+  wire    [(DAC_DATA_WIDTH-1):0]      dac_data_fifo_s;
+  wire    [(DAC_DATA_WIDTH-1):0]      dac_data_bypass_s;
+  wire                                dac_xfer_fifo_out_s;
+  wire                                dac_dunf_fifo_s;
+  wire                                dac_dunf_bypass_s;
+  wire                                dma_ready_wr_s;
 
   axi_dacfifo_wr #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@@ -217,7 +234,8 @@ module axi_dacfifo (
   ) i_wr (
     .dma_clk (dma_clk),
     .dma_data (dma_data),
-    .dma_ready (dma_ready_s),
+    .dma_ready (dma_ready),
+    .dma_ready_out (dma_ready_wr_s),
     .dma_valid (dma_valid),
     .dma_xfer_req (dma_xfer_req),
     .dma_xfer_last (dma_xfer_last),
@@ -294,8 +312,8 @@ module axi_dacfifo (
     .DAC_DATA_WIDTH (DAC_DATA_WIDTH)
   ) i_dac (
     .axi_clk (axi_clk),
-    .axi_dvalid (dac_rd_valid_s),
-    .axi_ddata (dac_rd_data_s),
+    .axi_dvalid (dac_valid),
+    .axi_ddata (axi_rd_data_s),
     .axi_dready (axi_rd_ready_s),
     .axi_dlast (axi_dlast_s),
     .axi_xfer_req (axi_xfer_req_s),
@@ -303,29 +321,54 @@ module axi_dacfifo (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid),
-    .dac_data (dac_data),
-    .dac_xfer_out (dac_xfer_out),
-    .dac_dunf (dac_dunf));
+    .dac_data (dac_data_fifo_s),
+    .dac_xfer_out (dac_xfer_fifo_out_s),
+    .dac_dunf (dac_dunf_fifo_s));
 
   // bypass logic
 
-  util_axis_resize #(
-    .MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
-    .SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
-  ) i_util_axis_resize (
-    .clk (axi_clk),
-    .resetn (axi_resetn),
-    .s_valid (dma_valid),
-    .s_ready (dma_ready_bp_s),
-    .s_data (dma_data),
-    .m_valid (dma_valid_bp_s),
-    .m_ready (axi_rd_ready_s),
-    .m_data (dma_data_bp_s)
+  axi_dacfifo_bypass #(
+    .DAC_DATA_WIDTH (DAC_DATA_WIDTH),
+    .DMA_DATA_WIDTH (DMA_DATA_WIDTH)
+  ) i_dacfifo_bypass (
+    .dma_clk(dma_clk),
+    .dma_data(dma_data),
+    .dma_ready(dma_ready),
+    .dma_ready_out(dma_ready_bypass_s),
+    .dma_valid(dma_valid),
+    .dma_xfer_req(dma_xfer_req),
+    .dac_clk(dac_clk),
+    .dac_rst(dac_rst),
+    .dac_valid(dac_valid),
+    .dac_data(dac_data_bypass_s),
+    .dac_dunf(dac_dunf_bypass_s)
   );
 
-  assign  dac_rd_valid_s = (dac_fifo_bypass) ? dma_valid_bp_s : axi_rd_valid_s;
-  assign  dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
-  assign  dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
+  always @(posedge dma_clk) begin
+    dma_bypass_m1 <= bypass;
+    dma_bypass <= dma_bypass_m1;
+  end
+
+  always @(posedge dac_clk) begin
+    dac_bypass_m1 <= bypass;
+    dac_bypass <= dac_bypass_m1;
+    dac_xfer_out_m1 <= dma_xfer_req;
+    dac_xfer_out_bypass <= dac_xfer_out_m1;
+  end
+
+  // mux for the dma_ready
+
+  always @(posedge dma_clk) begin
+    dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s;
+  end
+
+  // mux for dac data
+
+  always @(posedge dac_clk) begin
+    dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s;
+    dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s;
+    dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s;
+  end
 
 endmodule
 
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v b/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v
new file mode 100644
index 000000000..9ea262434
--- /dev/null
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v
@@ -0,0 +1,292 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2016(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_dacfifo_bypass #(
+
+  parameter   DAC_DATA_WIDTH = 64,
+  parameter   DMA_DATA_WIDTH = 64) (
+
+  // dma fifo interface
+
+  input                               dma_clk,
+  input       [(DMA_DATA_WIDTH-1):0]  dma_data,
+  input                               dma_ready,
+  output  reg                         dma_ready_out,
+  input                               dma_valid,
+
+  // request and syncronizaiton
+
+  input                               dma_xfer_req,
+
+  // dac fifo interface
+
+  input                               dac_clk,
+  input                               dac_rst,
+  input                               dac_valid,
+  output  reg [(DAC_DATA_WIDTH-1):0]  dac_data,
+  output  reg                         dac_dunf
+);
+
+  // suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
+
+  localparam  MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
+                                                              DAC_DATA_WIDTH/DMA_DATA_WIDTH;
+  localparam  DAC_ADDRESS_WIDTH = 10;
+  localparam  DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
+                                  (MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) :
+                                  (MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) :
+                                                     ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3));
+  localparam  DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4;
+  localparam  DAC_BUF_THRESHOLD_LO = 4;
+
+  reg     [(DMA_ADDRESS_WIDTH-1):0]     dma_mem_waddr = 'd0;
+  reg     [(DMA_ADDRESS_WIDTH-1):0]     dma_mem_waddr_g = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]     dac_mem_raddr = 'd0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]     dac_mem_raddr_g = 'd0;
+  reg                                   dma_rst_m1 = 1'b0;
+  reg                                   dma_rst = 1'b0;
+  reg     [DMA_ADDRESS_WIDTH-1:0]       dma_mem_addr_diff = 1'b0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m1 = 1'b0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m2 = 1'b0;
+  reg     [(DAC_ADDRESS_WIDTH-1):0]     dma_mem_raddr = 1'b0;
+  reg     [DAC_ADDRESS_WIDTH-1:0]       dac_mem_addr_diff = 1'b0;
+  reg     [(DMA_ADDRESS_WIDTH-1):0]     dac_mem_waddr_m1 = 1'b0;
+  reg     [(DMA_ADDRESS_WIDTH-1):0]     dac_mem_waddr_m2 = 1'b0;
+  reg     [(DMA_ADDRESS_WIDTH-1):0]     dac_mem_waddr = 1'b0;
+  reg                                   dac_mem_ready = 1'b0;
+  reg                                   dac_xfer_out = 1'b0;
+  reg                                   dac_xfer_out_m1 = 1'b0;
+
+  // internal signals
+
+  wire                                  dma_mem_last_read_s;
+  wire    [(DMA_ADDRESS_WIDTH):0]       dma_mem_addr_diff_s;
+  wire    [(DAC_ADDRESS_WIDTH):0]       dac_mem_addr_diff_s;
+  wire    [(DMA_ADDRESS_WIDTH-1):0]     dma_mem_raddr_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]     dac_mem_waddr_s;
+  wire                                  dma_mem_wea_s;
+  wire                                  dac_mem_rea_s;
+  wire    [(DAC_DATA_WIDTH-1):0]        dac_mem_rdata_s;
+  wire    [DMA_ADDRESS_WIDTH:0]         dma_address_diff_s;
+  wire    [DAC_ADDRESS_WIDTH:0]         dac_address_diff_s;
+
+  // binary to grey conversion
+
+  function [7:0] b2g;
+    input [7:0] b;
+    reg   [7:0] g;
+    begin
+      g[7] = b[7];
+      g[6] = b[7] ^ b[6];
+      g[5] = b[6] ^ b[5];
+      g[4] = b[5] ^ b[4];
+      g[3] = b[4] ^ b[3];
+      g[2] = b[3] ^ b[2];
+      g[1] = b[2] ^ b[1];
+      g[0] = b[1] ^ b[0];
+      b2g = g;
+    end
+  endfunction
+
+  // grey to binary conversion
+
+  function [7:0] g2b;
+    input [7:0] g;
+    reg   [7:0] b;
+    begin
+      b[7] = g[7];
+      b[6] = b[7] ^ g[6];
+      b[5] = b[6] ^ g[5];
+      b[4] = b[5] ^ g[4];
+      b[3] = b[4] ^ g[3];
+      b[2] = b[3] ^ g[2];
+      b[1] = b[2] ^ g[1];
+      b[0] = b[1] ^ g[0];
+      g2b = b;
+    end
+  endfunction
+
+  // An asymmetric memory to transfer data from DMAC interface to DAC interface
+
+  ad_mem_asym #(
+    .A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
+    .A_DATA_WIDTH (DMA_DATA_WIDTH),
+    .B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH),
+    .B_DATA_WIDTH (DAC_DATA_WIDTH))
+  i_mem_asym (
+    .clka (dma_clk),
+    .wea (dma_mem_wea_s),
+    .addra (dma_mem_waddr),
+    .dina (dma_data),
+    .clkb (dac_clk),
+    .addrb (dac_mem_raddr),
+    .doutb (dac_mem_rdata_s));
+
+  // dma reset is brought from dac domain
+
+  always @(posedge dma_clk) begin
+    dma_rst_m1 <= dac_rst;
+    dma_rst <= dma_rst_m1;
+  end
+
+  // Write address generation for the asymmetric memory
+
+  assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
+
+  always @(posedge dma_clk) begin
+    if (dma_rst == 1'b1) begin
+      dma_mem_waddr <= 'h0;
+      dma_mem_waddr_g <= 'h0;
+    end else begin
+      if (dma_mem_wea_s == 1'b1) begin
+        dma_mem_waddr <= dma_mem_waddr + 1;
+      end
+      dma_mem_waddr_g <= b2g(dma_mem_waddr);
+    end
+  end
+
+  // The memory module request data until reaches the high threshold.
+
+  always @(posedge dma_clk) begin
+    if (dma_rst == 1'b1) begin
+      dma_mem_addr_diff <= 'b0;
+      dma_mem_raddr_m1 <= 'b0;
+      dma_mem_raddr_m2 <= 'b0;
+      dma_mem_raddr <= 'b0;
+      dma_ready_out <= 1'b0;
+    end else begin
+      dma_mem_raddr_m1 <= dac_mem_raddr_g;
+      dma_mem_raddr_m2 <= dma_mem_raddr_m1;
+      dma_mem_raddr <= g2b(dma_mem_raddr_m2);
+      dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0];
+      if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
+        dma_ready_out <= 1'b0;
+      end else begin
+        dma_ready_out <= 1'b1;
+      end
+    end
+  end
+
+  // relative address offset on dma domain
+  assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
+  assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
+                                ((MEM_RATIO == 1) ? (dma_mem_raddr) :
+                                 (MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) :
+                                 (MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) :
+                                ((MEM_RATIO == 1) ? (dma_mem_raddr) :
+                                 (MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) :
+                                 (MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0}));
+
+
+  // relative address offset on dac domain
+  assign dac_address_diff_s = {1'b1, dac_mem_raddr} - dac_mem_waddr_s;
+  assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ?
+                                ((MEM_RATIO == 1) ? (dac_mem_waddr) :
+                                 (MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) :
+                                 (MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) :
+                                ((MEM_RATIO == 1) ? (dac_mem_waddr) :
+                                 (MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) :
+                                 (MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0}));
+
+  // Read address generation for the asymmetric memory
+
+  assign dac_mem_rea_s = dac_valid & dac_mem_ready;
+
+  always @(posedge dma_clk) begin
+    if (dac_rst == 1'b1) begin
+      dac_mem_raddr <= 'h0;
+      dac_mem_raddr_g <= 'h0;
+    end else begin
+      if (dac_mem_rea_s == 1'b1) begin
+        dac_mem_raddr <= dac_mem_raddr + 1;
+      end
+      dac_mem_raddr_g <= b2g(dac_mem_raddr);
+    end
+  end
+
+  // The memory module is ready if it's not empty
+
+  always @(posedge dac_clk) begin
+    if (dac_rst == 1'b1) begin
+      dac_mem_addr_diff <= 'b0;
+      dac_mem_waddr_m1 <= 'b0;
+      dac_mem_waddr_m2 <= 'b0;
+      dac_mem_waddr <= 'b0;
+      dac_mem_ready <= 1'b0;
+    end else begin
+      dac_mem_waddr_m1 <= dma_mem_waddr_g;
+      dac_mem_waddr_m2 <= dac_mem_waddr_m1;
+      dac_mem_waddr <= g2b(dac_mem_waddr_m2);
+      dac_mem_addr_diff <= dac_address_diff_s[DAC_ADDRESS_WIDTH-1:0];
+      if (dac_mem_addr_diff > 0) begin
+        dac_mem_ready <= 1'b1;
+      end else begin
+        dac_mem_ready <= 1'b0;
+      end
+    end
+  end
+
+  // define underflow
+
+  always @(posedge dac_clk) begin
+    if (dac_rst == 1'b1) begin
+      dac_xfer_out_m1 <= 1'b0;
+      dac_xfer_out <= 1'b0;
+      dac_dunf <= 1'b0;
+    end else begin
+      dac_xfer_out_m1 <= dma_xfer_req;
+      dac_xfer_out <= dac_xfer_out_m1;
+      dac_dunf <= (dac_valid == 1'b1) ? (dac_xfer_out & ~dac_mem_ready) : dac_dunf;
+    end
+  end
+
+  // DAC data output logic
+
+  always @(posedge dac_clk) begin
+    if (dac_rst == 1'b1) begin
+      dac_data <= 0;
+    end else begin
+      dac_data <= dac_mem_rdata_s;
+    end
+  end
+
+endmodule
+
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
index d3ea6a0a4..bc1fdb2fa 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
@@ -1,24 +1,29 @@
 
 set_property ASYNC_REG TRUE \
-  [get_cells -hier *_xfer_req_m[0]*] \
-  [get_cells -hier *_xfer_last_m[0]*]
+  [get_cells -hier *_xfer_req_m*] \
+  [get_cells -hier *_xfer_last_m*] \
+  [get_cells -hier *dac_xfer_out*] \
+  [get_cells -hier *dac_bypass_*] \
+  [get_cells -hier *dma_bypass_*]
 
-set_false_path -to [get_cells *_xfer_req_m[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
-set_false_path -to [get_cells *_xfer_last_m[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
-set_false_path -to [get_cells *dma_rst_m1* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
 
-set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-  -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
-set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-  -to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -to [get_cells  -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells  -hier -filter {name =~ *_xfer_last_m_reg[0]* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells  -hier -filter {name =~ *dac_xfer_out_m1* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells  -hier -filter {name =~ *_bypass_m1* && IS_SEQUENTIAL}]
+set_false_path -to [get_cells  -hier -filter {name =~ *dma_rst_m1* && IS_SEQUENTIAL}]
 
-set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-  -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
-set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-  -to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -from [get_cells  -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
+  -to [get_cells  -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells  -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
+  -to [get_cells  -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
 
-set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-  -to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
-set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-  -to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -from [get_cells  -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
+  -to [get_cells  -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells  -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
+  -to [get_cells  -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]
 
+set_false_path -from [get_cells  -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
+  -to [get_cells  -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells  -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
+  -to [get_cells  -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
index be08c967a..0bb293baa 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
@@ -13,6 +13,7 @@ adi_ip_files axi_dacfifo [list \
   "axi_dacfifo_dac.v" \
   "axi_dacfifo_wr.v" \
   "axi_dacfifo_rd.v" \
+  "axi_dacfifo_bypass.v" \
   "axi_dacfifo.v"]
 
 adi_ip_properties_lite axi_dacfifo
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
index 332f9b006..13c0b3007 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
@@ -46,6 +46,7 @@ module axi_dacfifo_wr (
   dma_clk,
   dma_data,
   dma_ready,
+  dma_ready_out,
   dma_valid,
 
   // request and syncronizaiton
@@ -120,7 +121,8 @@ module axi_dacfifo_wr (
 
   input                                     dma_clk;
   input   [(DMA_DATA_WIDTH-1):0]            dma_data;
-  output                                    dma_ready;
+  input                                     dma_ready;
+  output                                    dma_ready_out;
   input                                     dma_valid;
 
   input                                     dma_xfer_req;
@@ -169,7 +171,7 @@ module axi_dacfifo_wr (
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m1 = 'd0;
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m2 = 'd0;
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0]     dma_mem_raddr = 'd0;
-  reg                                       dma_ready = 1'b0;
+  reg                                       dma_ready_out = 1'b0;
   reg                                       dma_rst_m1 = 1'b0;
   reg                                       dma_rst_m2 = 1'b0;
   reg     [ 2:0]                            dma_mem_last_read_toggle_m = 3'b0;
@@ -363,16 +365,16 @@ module axi_dacfifo_wr (
       dma_mem_raddr_m1 <= 'b0;
       dma_mem_raddr_m2 <= 'b0;
       dma_mem_raddr <= 'b0;
-      dma_ready <= 1'b0;
+      dma_ready_out <= 1'b0;
     end else begin
       dma_mem_raddr_m1 <= axi_mem_raddr_g;
       dma_mem_raddr_m2 <= dma_mem_raddr_m1;
       dma_mem_raddr <= g2b(dma_mem_raddr_m2);
       dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
       if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
-        dma_ready <= 1'b0;
+        dma_ready_out <= 1'b0;
       end else begin
-        dma_ready <= 1'b1;
+        dma_ready_out <= 1'b1;
       end
     end
   end
diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index 735870609..44a3c9d30 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -79,7 +79,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   ad_connect  dma_xfer_req axi_dacfifo/dma_xfer_req
   ad_connect  dma_xfer_last axi_dacfifo/dma_xfer_last
 
-  ad_connect  dac_fifo_bypass axi_dacfifo/dac_fifo_bypass
+  ad_connect  dac_fifo_bypass axi_dacfifo/bypass
   ad_connect  dac_valid axi_dacfifo/dac_valid
   ad_connect  dac_data axi_dacfifo/dac_data
   ad_connect  dac_dunf axi_dacfifo/dac_dunf

From af3a4f5fc9aff7b17ed090ce843b3bf5f5394578 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 24 Feb 2017 12:28:46 +0200
Subject: [PATCH 934/972] axi_dacfifo: axi_dvalid should come from dacfifo_rd
 module

---
 library/xilinx/axi_dacfifo/axi_dacfifo.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index e619ef07a..a41dd5cfc 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -312,7 +312,7 @@ module axi_dacfifo (
     .DAC_DATA_WIDTH (DAC_DATA_WIDTH)
   ) i_dac (
     .axi_clk (axi_clk),
-    .axi_dvalid (dac_valid),
+    .axi_dvalid (axi_rd_valid_s),
     .axi_ddata (axi_rd_data_s),
     .axi_dready (axi_rd_ready_s),
     .axi_dlast (axi_dlast_s),

From 77081a6233872e31f58fcb60e521e42f4a27aaa6 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 24 Feb 2017 12:32:25 +0200
Subject: [PATCH 935/972] axi_dacfifo: Data from DMA is validated with
 dma_ready too

---
 library/xilinx/axi_dacfifo/axi_dacfifo_wr.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
index 13c0b3007..513c1a7af 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
@@ -333,7 +333,7 @@ module axi_dacfifo_wr (
                            (MEM_RATIO == 8) ? {dma_mem_raddr, 3'b0} :
                                               {dma_mem_raddr, 4'b0};
   assign dma_mem_last_read_s = dma_mem_last_read_toggle_m[2] ^ dma_mem_last_read_toggle_m[1];
-  assign dma_mem_wea_s = dma_xfer_req & dma_valid;
+  assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
 
   always @(posedge dma_clk) begin
     if (dma_rst_s == 1'b1) begin

From 06605ed1e1bafb7d573b319d98cccf152448fedc Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 24 Feb 2017 12:34:58 +0200
Subject: [PATCH 936/972] axi_dacfifo: Register the dac_valid signals

---
 library/xilinx/axi_dacfifo/axi_dacfifo_dac.v | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v
index 2ef272ab3..5042abfb6 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v
@@ -135,6 +135,7 @@ module axi_dacfifo_dac (
   reg                                 dac_dlast_m1 = 1'b0;
   reg                                 dac_dlast_m2 = 1'b0;
   reg                                 dac_dlast_inmem = 1'b0;
+  reg                                 dac_mem_valid = 1'b0;
 
   // internal signals
 
@@ -144,7 +145,6 @@ module axi_dacfifo_dac (
   wire    [(DAC_ADDRESS_WIDTH-1):0]   axi_mem_laddr_s;
 
   wire    [DAC_ADDRESS_WIDTH:0]       dac_mem_addr_diff_s;
-  wire                                dac_mem_valid_s;
   wire                                dac_xfer_init_s;
   wire                                dac_last_axi_beats_s;
 
@@ -303,7 +303,9 @@ module axi_dacfifo_dac (
   end
 
   assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr} - dac_mem_raddr;
-  assign dac_mem_valid_s = (dac_mem_enable) ? dac_valid : 1'b0;
+  always @(posedge dac_clk) begin
+    dac_mem_valid <= (dac_mem_enable) ? dac_valid : 1'b0;
+  end
 
   // CDC for the dma_last_beats
 
@@ -335,7 +337,7 @@ module axi_dacfifo_dac (
       end else if (dac_mem_raddr == dac_mem_laddr + MEM_RATIO) begin
         dac_dlast_inmem <= 1'b0;
       end
-      if (dac_mem_valid_s == 1'b1) begin
+      if (dac_mem_valid == 1'b1) begin
         dac_beat_cnt <= ((dac_beat_cnt >= MEM_RATIO-1) ||
                          ((dac_last_beats > 1'b1) && (dac_last_axi_beats_s > 1'b0) && (dac_beat_cnt == dac_last_beats-1))) ? 0 : dac_beat_cnt + 1;
         dac_mem_raddr <= ((dac_last_axi_beats_s) && (dac_beat_cnt == dac_last_beats-1)) ? (dac_mem_laddr + MEM_RATIO) : dac_mem_raddr + 1'b1;

From 14b4c4cf5ff16a1878683c53fc9074d0473325ae Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 24 Feb 2017 12:35:42 +0200
Subject: [PATCH 937/972] axi_dacfifo: Define constraint for bypass

The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
---
 library/xilinx/axi_dacfifo/axi_dacfifo.v | 107 ++++++++++++++---------
 1 file changed, 65 insertions(+), 42 deletions(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index a41dd5cfc..f25f74974 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -110,7 +110,7 @@ module axi_dacfifo (
 
   // parameters
 
-  parameter   DAC_DATA_WIDTH = 128;
+  parameter   DAC_DATA_WIDTH = 64;
   parameter   DMA_DATA_WIDTH = 64;
   parameter   AXI_DATA_WIDTH = 512;
   parameter   AXI_SIZE = 2;
@@ -118,6 +118,8 @@ module axi_dacfifo (
   parameter   AXI_ADDRESS = 32'h00000000;
   parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
 
+  localparam  FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;
+
   // dma interface
 
   input                               dma_clk;
@@ -325,50 +327,71 @@ module axi_dacfifo (
     .dac_xfer_out (dac_xfer_fifo_out_s),
     .dac_dunf (dac_dunf_fifo_s));
 
-  // bypass logic
+  // bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH
 
-  axi_dacfifo_bypass #(
-    .DAC_DATA_WIDTH (DAC_DATA_WIDTH),
-    .DMA_DATA_WIDTH (DMA_DATA_WIDTH)
-  ) i_dacfifo_bypass (
-    .dma_clk(dma_clk),
-    .dma_data(dma_data),
-    .dma_ready(dma_ready),
-    .dma_ready_out(dma_ready_bypass_s),
-    .dma_valid(dma_valid),
-    .dma_xfer_req(dma_xfer_req),
-    .dac_clk(dac_clk),
-    .dac_rst(dac_rst),
-    .dac_valid(dac_valid),
-    .dac_data(dac_data_bypass_s),
-    .dac_dunf(dac_dunf_bypass_s)
-  );
+  generate
+  if (FIFO_BYPASS) begin
+
+    axi_dacfifo_bypass #(
+      .DAC_DATA_WIDTH (DAC_DATA_WIDTH),
+      .DMA_DATA_WIDTH (DMA_DATA_WIDTH)
+    ) i_dacfifo_bypass (
+      .dma_clk(dma_clk),
+      .dma_data(dma_data),
+      .dma_ready(dma_ready),
+      .dma_ready_out(dma_ready_bypass_s),
+      .dma_valid(dma_valid),
+      .dma_xfer_req(dma_xfer_req),
+      .dac_clk(dac_clk),
+      .dac_rst(dac_rst),
+      .dac_valid(dac_valid),
+      .dac_data(dac_data_bypass_s),
+      .dac_dunf(dac_dunf_bypass_s)
+    );
+
+    always @(posedge dma_clk) begin
+      dma_bypass_m1 <= bypass;
+      dma_bypass <= dma_bypass_m1;
+    end
+
+    always @(posedge dac_clk) begin
+      dac_bypass_m1 <= bypass;
+      dac_bypass <= dac_bypass_m1;
+      dac_xfer_out_m1 <= dma_xfer_req;
+      dac_xfer_out_bypass <= dac_xfer_out_m1;
+    end
+
+    // mux for the dma_ready
+
+    always @(posedge dma_clk) begin
+      dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s;
+    end
+
+    // mux for dac data
+
+    always @(posedge dac_clk) begin
+      if (dac_valid) begin
+        dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s;
+      end
+      dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s;
+      dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s;
+    end
+
+  end else begin /* if (~FIFO_BYPASS) */
+
+    always @(posedge dma_clk) begin
+      dma_ready <= dma_ready_wr_s;
+    end
+    always @(posedge dac_clk) begin
+      if (dac_valid) begin
+        dac_data <= dac_data_fifo_s;
+      end
+      dac_xfer_out <= dac_xfer_fifo_out_s;
+      dac_dunf <= dac_dunf_fifo_s;
+    end
 
-  always @(posedge dma_clk) begin
-    dma_bypass_m1 <= bypass;
-    dma_bypass <= dma_bypass_m1;
-  end
-
-  always @(posedge dac_clk) begin
-    dac_bypass_m1 <= bypass;
-    dac_bypass <= dac_bypass_m1;
-    dac_xfer_out_m1 <= dma_xfer_req;
-    dac_xfer_out_bypass <= dac_xfer_out_m1;
-  end
-
-  // mux for the dma_ready
-
-  always @(posedge dma_clk) begin
-    dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s;
-  end
-
-  // mux for dac data
-
-  always @(posedge dac_clk) begin
-    dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s;
-    dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s;
-    dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s;
   end
+  endgenerate
 
 endmodule
 

From 7cb7bc111eefa6d931554165b0e4fd3835fcf1e7 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 24 Feb 2017 15:45:51 +0200
Subject: [PATCH 938/972] axi_dacfifo: Delete unused wires

---
 library/xilinx/axi_dacfifo/axi_dacfifo.v | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index f25f74974..c20632d85 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -200,25 +200,14 @@ module axi_dacfifo (
 
   // internal signals
 
-  wire    [(AXI_DATA_WIDTH-1):0]      axi_wr_data_s;
-  wire                                axi_wr_ready_s;
-  wire                                axi_wr_valid_s;
   wire    [(AXI_DATA_WIDTH-1):0]      axi_rd_data_s;
   wire                                axi_rd_ready_s;
   wire                                axi_rd_valid_s;
   wire                                axi_xfer_req_s;
-  wire    [(AXI_DATA_WIDTH-1):0]      dac_rd_data_s;
-  wire                                dac_rd_ready_s;
-  wire                                dac_rd_valid_s;
   wire    [31:0]                      axi_last_addr_s;
   wire    [ 3:0]                      axi_last_beats_s;
   wire                                axi_dlast_s;
   wire    [ 3:0]                      dma_last_beats_s;
-  wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
-  wire                                dma_ready_s;
-  wire                                dma_valid_bp_s;
-  wire    [(AXI_DATA_WIDTH-1):0]      dma_data_bp_s;
-  wire                                dma_ready_bp_s;
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_fifo_s;
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_bypass_s;
   wire                                dac_xfer_fifo_out_s;

From fa5f81f6c67f84a6459bb2407d45e9a1bce5c407 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 24 Feb 2017 15:47:04 +0200
Subject: [PATCH 939/972] axi_dacfifo: Fix clock for read address generation

---
 library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v b/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v
index 9ea262434..b4adeb401 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v
@@ -230,7 +230,7 @@ module axi_dacfifo_bypass #(
 
   assign dac_mem_rea_s = dac_valid & dac_mem_ready;
 
-  always @(posedge dma_clk) begin
+  always @(posedge dac_clk) begin
     if (dac_rst == 1'b1) begin
       dac_mem_raddr <= 'h0;
       dac_mem_raddr_g <= 'h0;

From f7190dbbfd94b4c70265c5f5e58025dbb38bdb8f Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 3 Apr 2017 12:38:40 +0300
Subject: [PATCH 940/972] adxcvr: Update Makefiles

---
 library/xilinx/axi_adxcvr/Makefile  | 6 ++++--
 library/xilinx/util_adxcvr/Makefile | 6 ++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/library/xilinx/axi_adxcvr/Makefile b/library/xilinx/axi_adxcvr/Makefile
index 2fc386a5c..c0c41eac9 100644
--- a/library/xilinx/axi_adxcvr/Makefile
+++ b/library/xilinx/axi_adxcvr/Makefile
@@ -37,8 +37,8 @@ M_FLIST += .Xil
 
 
 
-.PHONY: all clean clean-all
-all: axi_adxcvr.xpr
+.PHONY: all dep clean clean-all
+all: dep axi_adxcvr.xpr
 
 
 clean:clean-all
@@ -52,5 +52,7 @@ axi_adxcvr.xpr: $(M_DEPS)
 	-rm -rf $(M_FLIST)
 	$(M_VIVADO) axi_adxcvr_ip.tcl  >> axi_adxcvr_ip.log 2>&1
 
+dep:
+	make -C ../../interfaces
 ####################################################################################
 ####################################################################################
diff --git a/library/xilinx/util_adxcvr/Makefile b/library/xilinx/util_adxcvr/Makefile
index aeb58ad91..7df5f8cd8 100644
--- a/library/xilinx/util_adxcvr/Makefile
+++ b/library/xilinx/util_adxcvr/Makefile
@@ -35,8 +35,8 @@ M_FLIST += .Xil
 
 
 
-.PHONY: all clean clean-all
-all: util_adxcvr.xpr
+.PHONY: all dep clean clean-all
+all: dep util_adxcvr.xpr
 
 
 clean:clean-all
@@ -50,5 +50,7 @@ util_adxcvr.xpr: $(M_DEPS)
 	-rm -rf $(M_FLIST)
 	$(M_VIVADO) util_adxcvr_ip.tcl  >> util_adxcvr_ip.log 2>&1
 
+dep:
+	make -C ../../interfaces
 ####################################################################################
 ####################################################################################

From 096aadbf9121de038f60e22024645459e1d59ab5 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 9 Mar 2017 16:33:17 +0200
Subject: [PATCH 941/972] util_fir_dec: Changed output rounding mode to
 Symmetric rounding to Zero

This removes the added DC component that was introduced by the previous rounding mode
---
 library/util_fir_dec/util_fir_dec_ip.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/util_fir_dec/util_fir_dec_ip.tcl b/library/util_fir_dec/util_fir_dec_ip.tcl
index 3fa105477..1267759dd 100644
--- a/library/util_fir_dec/util_fir_dec_ip.tcl
+++ b/library/util_fir_dec/util_fir_dec_ip.tcl
@@ -21,7 +21,7 @@ CONFIG.Filter_Type {Decimation} \
 CONFIG.Interpolation_Rate {1} \
 CONFIG.Number_Channels {1} \
 CONFIG.Number_Paths {2} \
-CONFIG.Output_Rounding_Mode {Truncate_LSBs} \
+CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \
 CONFIG.Output_Width {16} \
 CONFIG.Quantization {Integer_Coefficients} \
 CONFIG.RateSpecification {Frequency_Specification} \

From 75409eeb38f38ac194d679636d05a56cb6e6552a Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 8 Mar 2017 14:29:26 +0200
Subject: [PATCH 942/972] util_fir_int: Shifted data so that the amplitude at
 the output of the filter is the same with the input

---
 library/util_fir_int/util_fir_int.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v
index 44af4643a..79a0b457b 100644
--- a/library/util_fir_int/util_fir_int.v
+++ b/library/util_fir_int/util_fir_int.v
@@ -65,7 +65,7 @@ module util_fir_int (
     end
   end
 
-  assign {channel_1, channel_0} = (interpolate == 1'b1) ? m_axis_data_tdata_s : s_axis_data_tdata;
+  assign {channel_1, channel_0} = (interpolate == 1'b1) ? {m_axis_data_tdata_s[30:16],1'b0,m_axis_data_tdata_s[14:0], 1'b0} : s_axis_data_tdata;
   assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_r : dac_read;
 
   fir_interp interpolator (

From 7c191a089ff7f4d2e81a3af9918470a203fe3709 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 23 Mar 2017 11:31:00 +0200
Subject: [PATCH 943/972] fmcjesdadc1: Update xcvr configuration to the default
 one used for this board

---
 projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
index 5fa81ebe1..e9321934a 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
@@ -5,6 +5,9 @@ set axi_ad9250_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.
 set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9250_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9250_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9250_xcvr
+set_property -dict [list CONFIG.LPM_OR_DFE_N {0}] $axi_ad9250_xcvr
+set_property -dict [list CONFIG.OUT_CLK_SEL {"010"}] $axi_ad9250_xcvr
+set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] $axi_ad9250_xcvr
 
 set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9250_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd

From ee398b4703e008a8c63921552ef0fe520039aab2 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 12 Apr 2017 14:17:35 +0200
Subject: [PATCH 944/972] spi_engine: Fix CMD_FIFO_VALID generation

Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
---
 library/spi_engine/axi_spi_engine/axi_spi_engine.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
index 9cff99264..875654d14 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
@@ -311,7 +311,7 @@ endgenerate
 `define axi_spi_engine_check_watermark(x, n) \
         (x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
 
-assign cmd_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h38;
+assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
 assign cmd_fifo_in_data = up_wdata_s[15:0];
 assign cmd_fifo_almost_empty =
         `axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);

From 01165c926cf12463d1d6e54895b81884a237a720 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 1 Mar 2017 11:31:09 +0200
Subject: [PATCH 945/972] ad6676evb: Set default xcvr parameters to common
 design

---
 projects/ad6676evb/common/ad6676evb_bd.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl
index b10522601..0990c2bc4 100644
--- a/projects/ad6676evb/common/ad6676evb_bd.tcl
+++ b/projects/ad6676evb/common/ad6676evb_bd.tcl
@@ -5,6 +5,9 @@ set axi_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.
 set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_xcvr
 set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad6676_xcvr
 set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad6676_xcvr
+set_property -dict [list CONFIG.LPM_OR_DFE_N {0}] $axi_ad6676_xcvr
+set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] $axi_ad6676_xcvr
+set_property -dict [list CONFIG.OUT_CLK_SEL {"100"}] $axi_ad6676_xcvr
 
 set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad6676_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd

From 03dcbc6a7dd6a165ca4fabae93a039e6bcc6a54e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 20 Apr 2017 18:43:37 +0300
Subject: [PATCH 946/972] ad_mmcm_drp: Fix generate block

Can not be multiple 'if' statements inside a generate block. If there are
multiple cases use if/esle statement, but always should be one single
if/else inside a generate.
---
 library/xilinx/common/ad_mmcm_drp.v | 265 ++++++++++++++--------------
 1 file changed, 136 insertions(+), 129 deletions(-)

diff --git a/library/xilinx/common/ad_mmcm_drp.v b/library/xilinx/common/ad_mmcm_drp.v
index e9d5f0e37..a8201cc05 100644
--- a/library/xilinx/common/ad_mmcm_drp.v
+++ b/library/xilinx/common/ad_mmcm_drp.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -138,134 +138,141 @@ module ad_mmcm_drp (
   // instantiations
 
   generate
-  if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin
-  MMCM_ADV #(
-    .BANDWIDTH ("OPTIMIZED"),
-    .CLKOUT4_CASCADE ("FALSE"),
-    .CLOCK_HOLD ("FALSE"),
-    .COMPENSATION ("ZHOLD"),
-    .STARTUP_WAIT ("FALSE"),
-    .DIVCLK_DIVIDE (MMCM_VCO_DIV),
-    .CLKFBOUT_MULT_F (MMCM_VCO_MUL),
-    .CLKFBOUT_PHASE (0.000),
-    .CLKFBOUT_USE_FINE_PS ("FALSE"),
-    .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
-    .CLKOUT0_PHASE (MMCM_CLK0_PHASE),
-    .CLKOUT0_DUTY_CYCLE (0.500),
-    .CLKOUT0_USE_FINE_PS ("FALSE"),
-    .CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
-    .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
-    .CLKOUT1_DUTY_CYCLE (0.500),
-    .CLKOUT1_USE_FINE_PS ("FALSE"),
-    .CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
-    .CLKOUT2_PHASE (MMCM_CLK2_PHASE),
-    .CLKOUT2_DUTY_CYCLE (0.500),
-    .CLKOUT2_USE_FINE_PS ("FALSE"),
-    .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
-    .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
-    .REF_JITTER1 (0.010))
-  i_mmcm (
-    .CLKIN1 (clk),
-    .CLKFBIN (bufg_fb_clk_s),
-    .CLKFBOUT (mmcm_fb_clk_s),
-    .CLKOUT0 (mmcm_clk_0_s),
-    .CLKOUT1 (mmcm_clk_1_s),
-    .CLKOUT2 (mmcm_clk_2_s),
-    .LOCKED (mmcm_locked_s),
-    .DCLK (up_clk),
-    .DEN (up_drp_sel),
-    .DADDR (up_drp_addr[6:0]),
-    .DWE (up_drp_wr),
-    .DI (up_drp_wdata),
-    .DO (up_drp_rdata_s),
-    .DRDY (up_drp_ready_s),
-    .CLKFBOUTB (),
-    .CLKOUT0B (),
-    .CLKOUT1B (),
-    .CLKOUT2B (),
-    .CLKOUT3 (),
-    .CLKOUT3B (),
-    .CLKOUT4 (),
-    .CLKOUT5 (),
-    .CLKOUT6 (),
-    .CLKIN2 (clk2),
-    .CLKINSEL (clk_sel),
-    .PSCLK (1'b0),
-    .PSEN (1'b0),
-    .PSINCDEC (1'b0),
-    .PSDONE (),
-    .CLKINSTOPPED (),
-    .CLKFBSTOPPED (),
-    .PWRDWN (1'b0),
-    .RST (mmcm_rst));
-  end
-
   if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
-  MMCME2_ADV #(
-    .BANDWIDTH ("OPTIMIZED"),
-    .CLKOUT4_CASCADE ("FALSE"),
-    .COMPENSATION ("ZHOLD"),
-    .STARTUP_WAIT ("FALSE"),
-    .DIVCLK_DIVIDE (MMCM_VCO_DIV),
-    .CLKFBOUT_MULT_F (MMCM_VCO_MUL),
-    .CLKFBOUT_PHASE (0.000),
-    .CLKFBOUT_USE_FINE_PS ("FALSE"),
-    .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
-    .CLKOUT0_PHASE (MMCM_CLK0_PHASE),
-    .CLKOUT0_DUTY_CYCLE (0.500),
-    .CLKOUT0_USE_FINE_PS ("FALSE"),
-    .CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
-    .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
-    .CLKOUT1_DUTY_CYCLE (0.500),
-    .CLKOUT1_USE_FINE_PS ("FALSE"),
-    .CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
-    .CLKOUT2_PHASE (MMCM_CLK2_PHASE),
-    .CLKOUT2_DUTY_CYCLE (0.500),
-    .CLKOUT2_USE_FINE_PS ("FALSE"),
-    .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
-    .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
-    .REF_JITTER1 (0.010))
-  i_mmcm (
-    .CLKIN1 (clk),
-    .CLKFBIN (bufg_fb_clk_s),
-    .CLKFBOUT (mmcm_fb_clk_s),
-    .CLKOUT0 (mmcm_clk_0_s),
-    .CLKOUT1 (mmcm_clk_1_s),
-    .CLKOUT2 (mmcm_clk_2_s),
-    .LOCKED (mmcm_locked_s),
-    .DCLK (up_clk),
-    .DEN (up_drp_sel),
-    .DADDR (up_drp_addr[6:0]),
-    .DWE (up_drp_wr),
-    .DI (up_drp_wdata),
-    .DO (up_drp_rdata_s),
-    .DRDY (up_drp_ready_s),
-    .CLKFBOUTB (),
-    .CLKOUT0B (),
-    .CLKOUT1B (),
-    .CLKOUT2B (),
-    .CLKOUT3 (),
-    .CLKOUT3B (),
-    .CLKOUT4 (),
-    .CLKOUT5 (),
-    .CLKOUT6 (),
-    .CLKIN2 (clk2),
-    .CLKINSEL (clk_sel),
-    .PSCLK (1'b0),
-    .PSEN (1'b0),
-    .PSINCDEC (1'b0),
-    .PSDONE (),
-    .CLKINSTOPPED (),
-    .CLKFBSTOPPED (),
-    .PWRDWN (1'b0),
-    .RST (mmcm_rst));
+    MMCME2_ADV #(
+      .BANDWIDTH ("OPTIMIZED"),
+      .CLKOUT4_CASCADE ("FALSE"),
+      .COMPENSATION ("ZHOLD"),
+      .STARTUP_WAIT ("FALSE"),
+      .DIVCLK_DIVIDE (MMCM_VCO_DIV),
+      .CLKFBOUT_MULT_F (MMCM_VCO_MUL),
+      .CLKFBOUT_PHASE (0.000),
+      .CLKFBOUT_USE_FINE_PS ("FALSE"),
+      .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
+      .CLKOUT0_PHASE (MMCM_CLK0_PHASE),
+      .CLKOUT0_DUTY_CYCLE (0.500),
+      .CLKOUT0_USE_FINE_PS ("FALSE"),
+      .CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
+      .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
+      .CLKOUT1_DUTY_CYCLE (0.500),
+      .CLKOUT1_USE_FINE_PS ("FALSE"),
+      .CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
+      .CLKOUT2_PHASE (MMCM_CLK2_PHASE),
+      .CLKOUT2_DUTY_CYCLE (0.500),
+      .CLKOUT2_USE_FINE_PS ("FALSE"),
+      .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
+      .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
+      .REF_JITTER1 (0.010))
+    i_mmcm (
+      .CLKIN1 (clk),
+      .CLKFBIN (bufg_fb_clk_s),
+      .CLKFBOUT (mmcm_fb_clk_s),
+      .CLKOUT0 (mmcm_clk_0_s),
+      .CLKOUT1 (mmcm_clk_1_s),
+      .CLKOUT2 (mmcm_clk_2_s),
+      .LOCKED (mmcm_locked_s),
+      .DCLK (up_clk),
+      .DEN (up_drp_sel),
+      .DADDR (up_drp_addr[6:0]),
+      .DWE (up_drp_wr),
+      .DI (up_drp_wdata),
+      .DO (up_drp_rdata_s),
+      .DRDY (up_drp_ready_s),
+      .CLKFBOUTB (),
+      .CLKOUT0B (),
+      .CLKOUT1B (),
+      .CLKOUT2B (),
+      .CLKOUT3 (),
+      .CLKOUT3B (),
+      .CLKOUT4 (),
+      .CLKOUT5 (),
+      .CLKOUT6 (),
+      .CLKIN2 (clk2),
+      .CLKINSEL (clk_sel),
+      .PSCLK (1'b0),
+      .PSEN (1'b0),
+      .PSINCDEC (1'b0),
+      .PSDONE (),
+      .CLKINSTOPPED (),
+      .CLKFBSTOPPED (),
+      .PWRDWN (1'b0),
+      .RST (mmcm_rst));
+
+      BUFG i_fb_clk_bufg  (.I (mmcm_fb_clk_s),  .O (bufg_fb_clk_s));
+      BUFG i_clk_0_bufg   (.I (mmcm_clk_0_s),   .O (mmcm_clk_0));
+      BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
+      BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
+
+  end else begin /* MMCM_DEVICE_TYPE == 1 */
+
+    MMCM_ADV #(
+      .BANDWIDTH ("OPTIMIZED"),
+      .CLKOUT4_CASCADE ("FALSE"),
+      .CLOCK_HOLD ("FALSE"),
+      .COMPENSATION ("ZHOLD"),
+      .STARTUP_WAIT ("FALSE"),
+      .DIVCLK_DIVIDE (MMCM_VCO_DIV),
+      .CLKFBOUT_MULT_F (MMCM_VCO_MUL),
+      .CLKFBOUT_PHASE (0.000),
+      .CLKFBOUT_USE_FINE_PS ("FALSE"),
+      .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
+      .CLKOUT0_PHASE (MMCM_CLK0_PHASE),
+      .CLKOUT0_DUTY_CYCLE (0.500),
+      .CLKOUT0_USE_FINE_PS ("FALSE"),
+      .CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
+      .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
+      .CLKOUT1_DUTY_CYCLE (0.500),
+      .CLKOUT1_USE_FINE_PS ("FALSE"),
+      .CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
+      .CLKOUT2_PHASE (MMCM_CLK2_PHASE),
+      .CLKOUT2_DUTY_CYCLE (0.500),
+      .CLKOUT2_USE_FINE_PS ("FALSE"),
+      .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
+      .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
+      .REF_JITTER1 (0.010))
+    i_mmcm (
+      .CLKIN1 (clk),
+      .CLKFBIN (bufg_fb_clk_s),
+      .CLKFBOUT (mmcm_fb_clk_s),
+      .CLKOUT0 (mmcm_clk_0_s),
+      .CLKOUT1 (mmcm_clk_1_s),
+      .CLKOUT2 (mmcm_clk_2_s),
+      .LOCKED (mmcm_locked_s),
+      .DCLK (up_clk),
+      .DEN (up_drp_sel),
+      .DADDR (up_drp_addr[6:0]),
+      .DWE (up_drp_wr),
+      .DI (up_drp_wdata),
+      .DO (up_drp_rdata_s),
+      .DRDY (up_drp_ready_s),
+      .CLKFBOUTB (),
+      .CLKOUT0B (),
+      .CLKOUT1B (),
+      .CLKOUT2B (),
+      .CLKOUT3 (),
+      .CLKOUT3B (),
+      .CLKOUT4 (),
+      .CLKOUT5 (),
+      .CLKOUT6 (),
+      .CLKIN2 (clk2),
+      .CLKINSEL (clk_sel),
+      .PSCLK (1'b0),
+      .PSEN (1'b0),
+      .PSINCDEC (1'b0),
+      .PSDONE (),
+      .CLKINSTOPPED (),
+      .CLKFBSTOPPED (),
+      .PWRDWN (1'b0),
+      .RST (mmcm_rst));
+
+      BUFG i_fb_clk_bufg  (.I (mmcm_fb_clk_s),  .O (bufg_fb_clk_s));
+      BUFG i_clk_0_bufg   (.I (mmcm_clk_0_s),   .O (mmcm_clk_0));
+      BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
+      BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
+
   end
   endgenerate
 
-  BUFG i_fb_clk_bufg  (.I (mmcm_fb_clk_s),  .O (bufg_fb_clk_s));
-  BUFG i_clk_0_bufg   (.I (mmcm_clk_0_s),   .O (mmcm_clk_0)); 
-  BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
-  BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
 
 endmodule
 

From 7659700719b6e8d7f2c5643429655418c9f8407e Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 20 Apr 2017 18:49:00 +0300
Subject: [PATCH 947/972] ad_serdes_clk: Fix generate block

---
 library/xilinx/common/ad_serdes_clk.v | 84 ++++++++++++++-------------
 1 file changed, 44 insertions(+), 40 deletions(-)

diff --git a/library/xilinx/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v
index 495f584f6..b0aa9e2e4 100644
--- a/library/xilinx/common/ad_serdes_clk.v
+++ b/library/xilinx/common/ad_serdes_clk.v
@@ -92,49 +92,53 @@ module ad_serdes_clk #(
 
   generate
   if (MMCM_OR_BUFR_N == 1) begin
-  ad_mmcm_drp #(
-    .MMCM_DEVICE_TYPE (DEVICE_TYPE),
-    .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
-    .MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD),
-    .MMCM_VCO_DIV (MMCM_VCO_DIV),
-    .MMCM_VCO_MUL (MMCM_VCO_MUL),
-    .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
-    .MMCM_CLK0_PHASE (0.0),
-    .MMCM_CLK1_DIV (MMCM_CLK1_DIV),
-    .MMCM_CLK1_PHASE (0.0),
-    .MMCM_CLK2_DIV (MMCM_CLK0_DIV),
-    .MMCM_CLK2_PHASE (90.0))
-  i_mmcm_drp (
-    .clk (clk_in_s),
-    .clk2 (1'b0),
-    .clk_sel (1'b1),
-    .mmcm_rst (rst),
-    .mmcm_clk_0 (clk),
-    .mmcm_clk_1 (div_clk),
-    .mmcm_clk_2 (out_clk),
-    .up_clk (up_clk),
-    .up_rstn (up_rstn),
-    .up_drp_sel (up_drp_sel),
-    .up_drp_wr (up_drp_wr),
-    .up_drp_addr (up_drp_addr),
-    .up_drp_wdata (up_drp_wdata[15:0]),
-    .up_drp_rdata (up_drp_rdata[15:0]),
-    .up_drp_ready (up_drp_ready),
-    .up_drp_locked (up_drp_locked));
-  end
+    ad_mmcm_drp #(
+      .MMCM_DEVICE_TYPE (DEVICE_TYPE),
+      .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
+      .MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD),
+      .MMCM_VCO_DIV (MMCM_VCO_DIV),
+      .MMCM_VCO_MUL (MMCM_VCO_MUL),
+      .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
+      .MMCM_CLK0_PHASE (0.0),
+      .MMCM_CLK1_DIV (MMCM_CLK1_DIV),
+      .MMCM_CLK1_PHASE (0.0),
+      .MMCM_CLK2_DIV (MMCM_CLK0_DIV),
+      .MMCM_CLK2_PHASE (90.0))
+    i_mmcm_drp (
+      .clk (clk_in_s),
+      .clk2 (1'b0),
+      .clk_sel (1'b1),
+      .mmcm_rst (rst),
+      .mmcm_clk_0 (clk),
+      .mmcm_clk_1 (div_clk),
+      .mmcm_clk_2 (out_clk),
+      .up_clk (up_clk),
+      .up_rstn (up_rstn),
+      .up_drp_sel (up_drp_sel),
+      .up_drp_wr (up_drp_wr),
+      .up_drp_addr (up_drp_addr),
+      .up_drp_wdata (up_drp_wdata[15:0]),
+      .up_drp_rdata (up_drp_rdata[15:0]),
+      .up_drp_ready (up_drp_ready),
+      .up_drp_locked (up_drp_locked));
 
-  if (MMCM_OR_BUFR_N == 0) begin
-  BUFIO i_clk_buf (
-    .I (clk_in_s),
-    .O (clk));
+    end else if (MMCM_OR_BUFR_N == 0) begin
 
-  BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
-    .CLR (1'b0),
-    .CE (1'b1),
-    .I (clk_in_s),
-    .O (div_clk));
+      BUFIO i_clk_buf (
+        .I (clk_in_s),
+        .O (clk));
+
+      BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
+        .CLR (1'b0),
+        .CE (1'b1),
+        .I (clk_in_s),
+        .O (div_clk));
+
+      assign out_clk = clk;
+      assign up_drp_rdata[15:0] = 'd0;
+      assign up_drp_ready = 'd0;
+      assign up_drp_locked = 'd0;
 
-  assign out_clk = clk;
   end
   endgenerate
 

From 54ff4d7bd017a5ca6f115b2c7a8f6ffab44923f4 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Thu, 20 Apr 2017 18:50:00 +0300
Subject: [PATCH 948/972] ad_serdes_in: Fix generate block

---
 library/xilinx/common/ad_serdes_in.v | 399 ++++++++++++++-------------
 1 file changed, 203 insertions(+), 196 deletions(-)

diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v
index 84520379f..dccc0d5e6 100644
--- a/library/xilinx/common/ad_serdes_in.v
+++ b/library/xilinx/common/ad_serdes_in.v
@@ -110,208 +110,215 @@ module ad_serdes_in #(
   // received data interface: ibuf -> idelay -> iserdes
 
   genvar l_inst;
-  generate
-  for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
+  generate if (DEVICE_TYPE == 0) begin
+    for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
 
-  IBUFDS i_ibuf (
-    .I (data_in_p[l_inst]),
-    .IB (data_in_n[l_inst]),
-    .O (data_in_ibuf_s[l_inst]));
+      IBUFDS i_ibuf (
+        .I (data_in_p[l_inst]),
+        .IB (data_in_n[l_inst]),
+        .O (data_in_ibuf_s[l_inst]));
 
-  if (DEVICE_TYPE == DEVICE_7SERIES) begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYE2 #(
-    .CINVCTRL_SEL ("FALSE"),
-    .DELAY_SRC ("IDATAIN"),
-    .HIGH_PERFORMANCE_MODE ("FALSE"),
-    .IDELAY_TYPE ("VAR_LOAD"),
-    .IDELAY_VALUE (0),
-    .REFCLK_FREQUENCY (200.0),
-    .PIPE_SEL ("FALSE"),
-    .SIGNAL_PATTERN ("DATA"))
-  i_idelay (
-    .CE (1'b0),
-    .INC (1'b0),
-    .DATAIN (1'b0),
-    .LDPIPEEN (1'b0),
-    .CINVCTRL (1'b0),
-    .REGRST (1'b0),
-    .C (up_clk),
-    .IDATAIN (data_in_ibuf_s[l_inst]),
-    .DATAOUT (data_in_idelay_s[l_inst]),
-    .LD (up_dld[l_inst]),
-    .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
-    .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
-  end
-  if(DEVICE_TYPE == DEVICE_6SERIES) begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IODELAYE1 #(
-    .CINVCTRL_SEL ("FALSE"),
-    .DELAY_SRC ("I"),
-    .HIGH_PERFORMANCE_MODE ("TRUE"),
-    .IDELAY_TYPE ("VAR_LOADABLE"),
-    .IDELAY_VALUE (0),
-    .ODELAY_TYPE ("FIXED"),
-    .ODELAY_VALUE (0),
-    .REFCLK_FREQUENCY (200.0),
-    .SIGNAL_PATTERN ("DATA"))
-  i_idelay (
-    .T (1'b1),
-    .CE (1'b0),
-    .INC (1'b0),
-    .CLKIN (1'b0),
-    .DATAIN (1'b0),
-    .ODATAIN (1'b0),
-    .CINVCTRL (1'b0),
-    .C (up_clk),
-    .IDATAIN (data_in_ibuf_s[l_inst]),
-    .DATAOUT (data_in_idelay_s[l_inst]),
-    .RST (up_dld[l_inst]),
-    .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
-    .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
-  end
+      (* IODELAY_GROUP = IODELAY_GROUP *)
+      IDELAYE2 #(
+        .CINVCTRL_SEL ("FALSE"),
+        .DELAY_SRC ("IDATAIN"),
+        .HIGH_PERFORMANCE_MODE ("FALSE"),
+        .IDELAY_TYPE ("VAR_LOAD"),
+        .IDELAY_VALUE (0),
+        .REFCLK_FREQUENCY (200.0),
+        .PIPE_SEL ("FALSE"),
+        .SIGNAL_PATTERN ("DATA"))
+      i_idelay (
+        .CE (1'b0),
+        .INC (1'b0),
+        .DATAIN (1'b0),
+        .LDPIPEEN (1'b0),
+        .CINVCTRL (1'b0),
+        .REGRST (1'b0),
+        .C (up_clk),
+        .IDATAIN (data_in_ibuf_s[l_inst]),
+        .DATAOUT (data_in_idelay_s[l_inst]),
+        .LD (up_dld[l_inst]),
+        .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
+        .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
 
-  if (DEVICE_TYPE == DEVICE_7SERIES) begin
-  ISERDESE2  #(
-    .DATA_RATE (DATA_RATE),
-    .DATA_WIDTH (SERDES_FACTOR),
-    .DYN_CLKDIV_INV_EN ("FALSE"),
-    .DYN_CLK_INV_EN ("FALSE"),
-    .INIT_Q1 (1'b0),
-    .INIT_Q2 (1'b0),
-    .INIT_Q3 (1'b0),
-    .INIT_Q4 (1'b0),
-    .INTERFACE_TYPE ("NETWORKING"),
-    .IOBDELAY ("IFD"),
-    .NUM_CE (2),
-    .OFB_USED ("FALSE"),
-    .SERDES_MODE ("MASTER"),
-    .SRVAL_Q1 (1'b0),
-    .SRVAL_Q2 (1'b0),
-    .SRVAL_Q3 (1'b0),
-    .SRVAL_Q4 (1'b0))
-  i_iserdes (
-    .O (),
-    .Q1 (data_s0[l_inst]),
-    .Q2 (data_s1[l_inst]),
-    .Q3 (data_s2[l_inst]),
-    .Q4 (data_s3[l_inst]),
-    .Q5 (data_s4[l_inst]),
-    .Q6 (data_s5[l_inst]),
-    .Q7 (data_s6[l_inst]),
-    .Q8 (data_s7[l_inst]),
-    .SHIFTOUT1 (),
-    .SHIFTOUT2 (),
-    .BITSLIP (1'b0),
-    .CE1 (1'b1),
-    .CE2 (1'b1),
-    .CLKDIVP (1'b0),
-    .CLK (clk),
-    .CLKB (~clk),
-    .CLKDIV (div_clk),
-    .OCLK (1'b0),
-    .DYNCLKDIVSEL (1'b0),
-    .DYNCLKSEL (1'b0),
-    .D (1'b0),
-    .DDLY (data_in_idelay_s[l_inst]),
-    .OFB (1'b0),
-    .OCLKB (1'b0),
-    .RST (rst),
-    .SHIFTIN1 (1'b0),
-    .SHIFTIN2 (1'b0));
-  end
-  if (DEVICE_TYPE == DEVICE_6SERIES) begin
-  ISERDESE1 #(
-    .DATA_RATE (DATA_RATE),
-    .DATA_WIDTH (SERDES_FACTOR),
-    .DYN_CLKDIV_INV_EN ("FALSE"),
-    .DYN_CLK_INV_EN ("FALSE"),
-    .INIT_Q1 (1'b0),
-    .INIT_Q2 (1'b0),
-    .INIT_Q3 (1'b0),
-    .INIT_Q4 (1'b0),
-    .INTERFACE_TYPE ("NETWORKING"),
-    .IOBDELAY ("NONE"),
-    .NUM_CE (1),
-    .OFB_USED ("FALSE"),
-    .SERDES_MODE ("MASTER"),
-    .SRVAL_Q1 (1'b0),
-    .SRVAL_Q2 (1'b0),
-    .SRVAL_Q3 (1'b0),
-    .SRVAL_Q4 (1'b0))
-  i_iserdes_m (
-    .O (),
-    .Q1 (data_s0[l_inst]),
-    .Q2 (data_s1[l_inst]),
-    .Q3 (data_s2[l_inst]),
-    .Q4 (data_s3[l_inst]),
-    .Q5 (data_s4[l_inst]),
-    .Q6 (data_s5[l_inst]),
-    .SHIFTOUT1 (data_shift1_s[l_inst]),
-    .SHIFTOUT2 (data_shift2_s[l_inst]),
-    .BITSLIP (1'b0),
-    .CE1 (1'b1),
-    .CE2 (1'b1),
-    .CLK (clk),
-    .CLKB (~clk),
-    .CLKDIV (div_clk),
-    .OCLK (1'b0),
-    .DYNCLKDIVSEL (1'b0),
-    .DYNCLKSEL (1'b0),
-    .D (1'b0),
-    .DDLY (data_in_idelay_s[l_inst]),
-    .OFB (1'b0),
-    .RST (rst),
-    .SHIFTIN1 (1'b0),
-    .SHIFTIN2 (1'b0));
+      ISERDESE2  #(
+        .DATA_RATE (DATA_RATE),
+        .DATA_WIDTH (SERDES_FACTOR),
+        .DYN_CLKDIV_INV_EN ("FALSE"),
+        .DYN_CLK_INV_EN ("FALSE"),
+        .INIT_Q1 (1'b0),
+        .INIT_Q2 (1'b0),
+        .INIT_Q3 (1'b0),
+        .INIT_Q4 (1'b0),
+        .INTERFACE_TYPE ("NETWORKING"),
+        .IOBDELAY ("IFD"),
+        .NUM_CE (2),
+        .OFB_USED ("FALSE"),
+        .SERDES_MODE ("MASTER"),
+        .SRVAL_Q1 (1'b0),
+        .SRVAL_Q2 (1'b0),
+        .SRVAL_Q3 (1'b0),
+        .SRVAL_Q4 (1'b0))
+      i_iserdes (
+        .O (),
+        .Q1 (data_s0[l_inst]),
+        .Q2 (data_s1[l_inst]),
+        .Q3 (data_s2[l_inst]),
+        .Q4 (data_s3[l_inst]),
+        .Q5 (data_s4[l_inst]),
+        .Q6 (data_s5[l_inst]),
+        .Q7 (data_s6[l_inst]),
+        .Q8 (data_s7[l_inst]),
+        .SHIFTOUT1 (),
+        .SHIFTOUT2 (),
+        .BITSLIP (1'b0),
+        .CE1 (1'b1),
+        .CE2 (1'b1),
+        .CLKDIVP (1'b0),
+        .CLK (clk),
+        .CLKB (~clk),
+        .CLKDIV (div_clk),
+        .OCLK (1'b0),
+        .DYNCLKDIVSEL (1'b0),
+        .DYNCLKSEL (1'b0),
+        .D (1'b0),
+        .DDLY (data_in_idelay_s[l_inst]),
+        .OFB (1'b0),
+        .OCLKB (1'b0),
+        .RST (rst),
+        .SHIFTIN1 (1'b0),
+        .SHIFTIN2 (1'b0));
+      end /* g_data */
 
-  ISERDESE1 #(
-    .DATA_RATE (DATA_RATE),
-    .DATA_WIDTH (SERDES_FACTOR),
-    .DYN_CLKDIV_INV_EN ("FALSE"),
-    .DYN_CLK_INV_EN ("FALSE"),
-    .INIT_Q1 (1'b0),
-    .INIT_Q2 (1'b0),
-    .INIT_Q3 (1'b0),
-    .INIT_Q4 (1'b0),
-    .INTERFACE_TYPE ("NETWORKING"),
-    .IOBDELAY ("NONE"),
-    .NUM_CE (1),
-    .OFB_USED ("FALSE"),
-    .SERDES_MODE ("SLAVE"),
-    .SRVAL_Q1 (1'b0),
-    .SRVAL_Q2 (1'b0),
-    .SRVAL_Q3 (1'b0),
-    .SRVAL_Q4 (1'b0))
-  i_iserdes_s (
-    .O (),
-    .Q1 (),
-    .Q2 (),
-    .Q3 (data_s6[l_inst]),
-    .Q4 (data_s7[l_inst]),
-    .Q5 (),
-    .Q6 (),
-    .SHIFTOUT1 (),
-    .SHIFTOUT2 (),
-    .BITSLIP (1'b0),
-    .CE1 (1'b1),
-    .CE2 (1'b1),
-    .CLK (clk),
-    .CLKB (~clk),
-    .CLKDIV (div_clk),
-    .OCLK (1'b0),
-    .DYNCLKDIVSEL (1'b0),
-    .DYNCLKSEL (1'b0),
-    .D (1'b0),
-    .DDLY (data_in_idelay_s[l_inst]),
-    .OFB (1'b0),
-    .RST (rst),
-    .SHIFTIN1 (data_shift1_s[l_inst]),
-    .SHIFTIN2 (data_shift2_s[l_inst]));
-  end
-  end
+    end else begin
+
+    for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
+
+      IBUFDS i_ibuf (
+        .I (data_in_p[l_inst]),
+        .IB (data_in_n[l_inst]),
+        .O (data_in_ibuf_s[l_inst]));
+
+      (* IODELAY_GROUP = IODELAY_GROUP *)
+      IODELAYE1 #(
+        .CINVCTRL_SEL ("FALSE"),
+        .DELAY_SRC ("I"),
+        .HIGH_PERFORMANCE_MODE ("TRUE"),
+        .IDELAY_TYPE ("VAR_LOADABLE"),
+        .IDELAY_VALUE (0),
+        .ODELAY_TYPE ("FIXED"),
+        .ODELAY_VALUE (0),
+        .REFCLK_FREQUENCY (200.0),
+        .SIGNAL_PATTERN ("DATA"))
+      i_idelay (
+        .T (1'b1),
+        .CE (1'b0),
+        .INC (1'b0),
+        .CLKIN (1'b0),
+        .DATAIN (1'b0),
+        .ODATAIN (1'b0),
+        .CINVCTRL (1'b0),
+        .C (up_clk),
+        .IDATAIN (data_in_ibuf_s[l_inst]),
+        .DATAOUT (data_in_idelay_s[l_inst]),
+        .RST (up_dld[l_inst]),
+        .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
+        .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
+
+      ISERDESE1 #(
+        .DATA_RATE (DATA_RATE),
+        .DATA_WIDTH (SERDES_FACTOR),
+        .DYN_CLKDIV_INV_EN ("FALSE"),
+        .DYN_CLK_INV_EN ("FALSE"),
+        .INIT_Q1 (1'b0),
+        .INIT_Q2 (1'b0),
+        .INIT_Q3 (1'b0),
+        .INIT_Q4 (1'b0),
+        .INTERFACE_TYPE ("NETWORKING"),
+        .IOBDELAY ("NONE"),
+        .NUM_CE (1),
+        .OFB_USED ("FALSE"),
+        .SERDES_MODE ("MASTER"),
+        .SRVAL_Q1 (1'b0),
+        .SRVAL_Q2 (1'b0),
+        .SRVAL_Q3 (1'b0),
+        .SRVAL_Q4 (1'b0))
+      i_iserdes_m (
+        .O (),
+        .Q1 (data_s0[l_inst]),
+        .Q2 (data_s1[l_inst]),
+        .Q3 (data_s2[l_inst]),
+        .Q4 (data_s3[l_inst]),
+        .Q5 (data_s4[l_inst]),
+        .Q6 (data_s5[l_inst]),
+        .SHIFTOUT1 (data_shift1_s[l_inst]),
+        .SHIFTOUT2 (data_shift2_s[l_inst]),
+        .BITSLIP (1'b0),
+        .CE1 (1'b1),
+        .CE2 (1'b1),
+        .CLK (clk),
+        .CLKB (~clk),
+        .CLKDIV (div_clk),
+        .OCLK (1'b0),
+        .DYNCLKDIVSEL (1'b0),
+        .DYNCLKSEL (1'b0),
+        .D (1'b0),
+        .DDLY (data_in_idelay_s[l_inst]),
+        .OFB (1'b0),
+        .RST (rst),
+        .SHIFTIN1 (1'b0),
+        .SHIFTIN2 (1'b0));
+
+      ISERDESE1 #(
+        .DATA_RATE (DATA_RATE),
+        .DATA_WIDTH (SERDES_FACTOR),
+        .DYN_CLKDIV_INV_EN ("FALSE"),
+        .DYN_CLK_INV_EN ("FALSE"),
+        .INIT_Q1 (1'b0),
+        .INIT_Q2 (1'b0),
+        .INIT_Q3 (1'b0),
+        .INIT_Q4 (1'b0),
+        .INTERFACE_TYPE ("NETWORKING"),
+        .IOBDELAY ("NONE"),
+        .NUM_CE (1),
+        .OFB_USED ("FALSE"),
+        .SERDES_MODE ("SLAVE"),
+        .SRVAL_Q1 (1'b0),
+        .SRVAL_Q2 (1'b0),
+        .SRVAL_Q3 (1'b0),
+        .SRVAL_Q4 (1'b0))
+      i_iserdes_s (
+        .O (),
+        .Q1 (),
+        .Q2 (),
+        .Q3 (data_s6[l_inst]),
+        .Q4 (data_s7[l_inst]),
+        .Q5 (),
+        .Q6 (),
+        .SHIFTOUT1 (),
+        .SHIFTOUT2 (),
+        .BITSLIP (1'b0),
+        .CE1 (1'b1),
+        .CE2 (1'b1),
+        .CLK (clk),
+        .CLKB (~clk),
+        .CLKDIV (div_clk),
+        .OCLK (1'b0),
+        .DYNCLKDIVSEL (1'b0),
+        .DYNCLKSEL (1'b0),
+        .D (1'b0),
+        .DDLY (data_in_idelay_s[l_inst]),
+        .OFB (1'b0),
+        .RST (rst),
+        .SHIFTIN1 (data_shift1_s[l_inst]),
+        .SHIFTIN2 (data_shift2_s[l_inst]));
+
+      end /* g_data */
+    end
   endgenerate
 
+
 endmodule
 
 // ***************************************************************************

From edefb9df442f9c91e2b3516436efe1fa194212c0 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Fri, 21 Apr 2017 09:06:54 +0300
Subject: [PATCH 949/972] axi_hdmi_tx: Fix assignment type

The general rule of thumb is to use nonblocking assignments for
sequential always blocks.
---
 library/axi_hdmi_tx/axi_hdmi_tx_core.v | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
index 6a3ff7bb9..4f50cdb36 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
@@ -1,9 +1,9 @@
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2011(c) Analog Devices, Inc.
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -21,16 +21,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -540,12 +540,12 @@ module axi_hdmi_tx_core (
 
   always @(posedge hdmi_clk) begin
 
-    hdmi_36_hsync = hdmi_clip_hs_d;
-    hdmi_36_vsync = hdmi_clip_vs_d;
-    hdmi_36_data_e = hdmi_clip_de_d;
-    hdmi_36_data[35:24] = {hdmi_clip_data[23:16], hdmi_clip_data[23:20]};
-    hdmi_36_data[23:12] = {hdmi_clip_data[15: 8], hdmi_clip_data[15:12]};
-    hdmi_36_data[11: 0] = {hdmi_clip_data[ 7: 0], hdmi_clip_data[ 7: 4]};
+    hdmi_36_hsync <= hdmi_clip_hs_d;
+    hdmi_36_vsync <= hdmi_clip_vs_d;
+    hdmi_36_data_e <= hdmi_clip_de_d;
+    hdmi_36_data[35:24] <= {hdmi_clip_data[23:16], hdmi_clip_data[23:20]};
+    hdmi_36_data[23:12] <= {hdmi_clip_data[15: 8], hdmi_clip_data[15:12]};
+    hdmi_36_data[11: 0] <= {hdmi_clip_data[ 7: 0], hdmi_clip_data[ 7: 4]};
 
     hdmi_24_hsync <= hdmi_clip_hs_d;
     hdmi_24_vsync <= hdmi_clip_vs_d;

From db459d96e9153c19808c65f769eec66989d4bf58 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 28 Apr 2017 11:29:12 +0200
Subject: [PATCH 950/972] daq2: zc706: Increase DAC FIFO size

Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.

In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 projects/daq2/zc706/system_bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl
index f958ed1b2..3e588e70f 100644
--- a/projects/daq2/zc706/system_bd.tcl
+++ b/projects/daq2/zc706/system_bd.tcl
@@ -3,7 +3,7 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
 source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
 source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
 
-p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
+p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 16
 p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
 
 create_bd_port -dir I -type rst sys_rst

From e2ef47015072e9f9a9bd7f7c9a5a73c8c5ead1f1 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Thu, 4 May 2017 16:38:21 +0300
Subject: [PATCH 951/972] axi_ad9434: Fix input data rate

---
 library/axi_ad9434/axi_ad9434_if.v | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v
index bb4da7915..1d30a232c 100644
--- a/library/axi_ad9434/axi_ad9434_if.v
+++ b/library/axi_ad9434/axi_ad9434_if.v
@@ -152,7 +152,8 @@ module axi_ad9434_if (
     .IODELAY_CTRL(0),
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(SDR),
-    .DATA_WIDTH(12))
+    .DATA_WIDTH(12),
+    .SERDES_FACTOR(4))
   i_adc_data (
     .rst(adc_rst),
     .clk(adc_clk_in),
@@ -184,7 +185,8 @@ module axi_ad9434_if (
     .IODELAY_CTRL(1),
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(SDR),
-    .DATA_WIDTH(1))
+    .DATA_WIDTH(1),
+    .SERDES_FACTOR(4))
   i_adc_or (
     .rst(adc_rst),
     .clk(adc_clk_in),
@@ -217,7 +219,8 @@ module axi_ad9434_if (
     .MMCM_VCO_DIV (6),
     .MMCM_VCO_MUL (12),
     .MMCM_CLK0_DIV (2),
-    .MMCM_CLK1_DIV (8))
+    .MMCM_CLK1_DIV (8),
+    .SERDES_FACTOR(4))
   i_serdes_clk (
     .rst (mmcm_rst),
     .clk_in_p (adc_clk_in_p),

From d3c6771ad63fe0ccf4f9883b5ebf8133390e9cec Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 10 May 2017 11:12:45 +0300
Subject: [PATCH 952/972] axi_ad9371: Update dac_clk_ratio to 2

DAC sampling frequency is two times of the JESD204
core clock.
---
 library/axi_ad9371/axi_ad9371_tx.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v
index ce64c0e6a..853b4fec4 100644
--- a/library/axi_ad9371/axi_ad9371_tx.v
+++ b/library/axi_ad9371/axi_ad9371_tx.v
@@ -301,7 +301,7 @@ module axi_ad9371_tx (
     .dac_status (1'b1),
     .dac_status_ovf (dac_dovf),
     .dac_status_unf (dac_dunf),
-    .dac_clk_ratio (32'd1),
+    .dac_clk_ratio (32'd2),
     .up_drp_sel (),
     .up_drp_wr (),
     .up_drp_addr (),

From e99244b041cd85f919d1f85b6f28f0fc75b4f0f9 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 10 May 2017 17:30:15 +0300
Subject: [PATCH 953/972] axi_ad9739a: Fix DDS set frequency

- DDS out frequency was 4 times greater than the desired frequency
---
 library/axi_ad9739a/axi_ad9739a_core.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v
index 0e8ed94f7..f23524a60 100644
--- a/library/axi_ad9739a/axi_ad9739a_core.v
+++ b/library/axi_ad9739a/axi_ad9739a_core.v
@@ -223,7 +223,7 @@ module axi_ad9739a_core (
     .dac_status (dac_status),
     .dac_status_ovf (dac_dovf),
     .dac_status_unf (dac_dunf),
-    .dac_clk_ratio (32'd4),
+    .dac_clk_ratio (32'd16),
     .up_drp_sel (),
     .up_drp_wr (),
     .up_drp_addr (),

From ce90769cd8426917b407315e09269a9421ba64c4 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Jun 2017 16:44:04 +0300
Subject: [PATCH 954/972] pzsdr1: Fix IO definition for enable/en_agc

---
 projects/pzsdr1/common/pzsdr1_constr.xdc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/pzsdr1/common/pzsdr1_constr.xdc b/projects/pzsdr1/common/pzsdr1_constr.xdc
index ebfafbf8a..a334553a2 100644
--- a/projects/pzsdr1/common/pzsdr1_constr.xdc
+++ b/projects/pzsdr1/common/pzsdr1_constr.xdc
@@ -2,7 +2,7 @@
 # constraints (pzsdr1.b)
 # ad9361
 
-set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L11P_T1_SRCC_35           U1,L16,IO_L11_35_ENABLE
+set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports enable]                            ; ## IO_L10P_T1_AD11P_35          U1,L16,IO_L11_35_ENABLE
 set_property  -dict {PACKAGE_PIN  L17  IOSTANDARD LVCMOS25} [get_ports txnrx]                             ; ## IO_L11N_T1_SRCC_35           U1,L17,IO_L11_35_TXNRX
 
 set_property  -dict {PACKAGE_PIN  H15  IOSTANDARD LVCMOS25} [get_ports gpio_status[0]]                    ; ## IO_L19P_T3_35                U1,H15,IO_L19_35_CTRL_OUT0
@@ -17,7 +17,7 @@ set_property  -dict {PACKAGE_PIN  N17  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
 set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]]                       ; ## IO_L23N_T3_34                U1,P18,IO_L23_34_CTRL_IN1
 set_property  -dict {PACKAGE_PIN  P15  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]]                       ; ## IO_L24P_T3_34                U1,P15,IO_L24_34_CTRL_IN2
 set_property  -dict {PACKAGE_PIN  P16  IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]]                       ; ## IO_L24N_T3_34                U1,P16,IO_L24_34_CTRL_IN3
-set_property  -dict {PACKAGE_PIN  K19  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L10P_T1_AD11P_35          U1,K19,IO_L10_35_EN_AGC
+set_property  -dict {PACKAGE_PIN  L16  IOSTANDARD LVCMOS25} [get_ports gpio_en_agc]                       ; ## IO_L11P_T1_SRCC_35           U1,K19,IO_L10_35_EN_AGC
 set_property  -dict {PACKAGE_PIN  J19  IOSTANDARD LVCMOS25} [get_ports gpio_sync]                         ; ## IO_L10N_T1_AD11N_35          U1,J19,IO_L10_35_SYNC_IN
 set_property  -dict {PACKAGE_PIN  G14  IOSTANDARD LVCMOS25} [get_ports gpio_resetb]                       ; ## IO_0_35                      U1,G14,IO_00_35_AD9364_RST
 set_property  -dict {PACKAGE_PIN  R19  IOSTANDARD LVCMOS25} [get_ports gpio_clksel]                       ; ## IO_0_34                      U1,R19,IO_00_34_AD9364_CLKSEL

From 0b450a3dd732ddd7c0b9208689183ea533195e63 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 8 Jun 2017 10:16:43 -0400
Subject: [PATCH 955/972] adi_board.tcl: reset xilinx ip using cpu clock

---
 projects/scripts/adi_board.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 3d7b22b29..1448a0690 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -214,7 +214,7 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
   ad_connect  ${a_jesd}/${txrx}_sync $m_sync
   ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk
   ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
-  ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk
+  ad_connect  sys_cpu_clk ${a_jesd}_rstgen/slowest_sync_clk
   ad_connect  sys_cpu_resetn ${a_jesd}_rstgen/ext_reset_in
   ad_connect  ${a_jesd}_rstgen/peripheral_reset ${a_jesd}/${txrx}_reset
 

From 9feeb726310af7fe6c0ba2bec3dd24d2115ae41c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 8 Jun 2017 10:49:37 -0400
Subject: [PATCH 956/972] adrv9371x- reset jesd ip using cpu clock

---
 projects/adrv9371x/common/adrv9371x_bd.tcl | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index c655a8c58..8ae261605 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -148,7 +148,6 @@ ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_1
 ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_2
 ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_3
 ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk
-ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd_rstgen/slowest_sync_clk
 ad_reconct  util_ad9371_xcvr/tx_0 axi_ad9371_tx_jesd/gt3_tx
 ad_reconct  util_ad9371_xcvr/tx_1 axi_ad9371_tx_jesd/gt0_tx
 ad_reconct  util_ad9371_xcvr/tx_2 axi_ad9371_tx_jesd/gt1_tx
@@ -158,13 +157,11 @@ ad_reconct  util_ad9371_xcvr/rx_out_clk_0 axi_ad9371_rx_clkgen/clk
 ad_connect  axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_0
 ad_connect  axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_1
 ad_connect  axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk
-ad_connect  axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd_rstgen/slowest_sync_clk
 ad_xcvrcon  util_ad9371_xcvr axi_ad9371_rx_os_xcvr axi_ad9371_rx_os_jesd
 ad_reconct  util_ad9371_xcvr/rx_out_clk_2 axi_ad9371_rx_os_clkgen/clk
 ad_connect  axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_2
 ad_connect  axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_3
 ad_connect  axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk
-ad_connect  axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd_rstgen/slowest_sync_clk
 
 # dma clock & reset
 

From b14c3fb00d3f82f4967db6405bb7bf27f9d1a63d Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri, 9 Jun 2017 19:12:36 +0300
Subject: [PATCH 957/972] Revert "adrv9371x- reset jesd ip using cpu clock"

This reverts commit 9feeb726310af7fe6c0ba2bec3dd24d2115ae41c.
---
 projects/adrv9371x/common/adrv9371x_bd.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl
index 8ae261605..c655a8c58 100644
--- a/projects/adrv9371x/common/adrv9371x_bd.tcl
+++ b/projects/adrv9371x/common/adrv9371x_bd.tcl
@@ -148,6 +148,7 @@ ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_1
 ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_2
 ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_3
 ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk
+ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd_rstgen/slowest_sync_clk
 ad_reconct  util_ad9371_xcvr/tx_0 axi_ad9371_tx_jesd/gt3_tx
 ad_reconct  util_ad9371_xcvr/tx_1 axi_ad9371_tx_jesd/gt0_tx
 ad_reconct  util_ad9371_xcvr/tx_2 axi_ad9371_tx_jesd/gt1_tx
@@ -157,11 +158,13 @@ ad_reconct  util_ad9371_xcvr/rx_out_clk_0 axi_ad9371_rx_clkgen/clk
 ad_connect  axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_0
 ad_connect  axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_1
 ad_connect  axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk
+ad_connect  axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd_rstgen/slowest_sync_clk
 ad_xcvrcon  util_ad9371_xcvr axi_ad9371_rx_os_xcvr axi_ad9371_rx_os_jesd
 ad_reconct  util_ad9371_xcvr/rx_out_clk_2 axi_ad9371_rx_os_clkgen/clk
 ad_connect  axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_2
 ad_connect  axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_3
 ad_connect  axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk
+ad_connect  axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd_rstgen/slowest_sync_clk
 
 # dma clock & reset
 

From 033737d6bfb5d4e9a275e90319a3a9cfa8279b31 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri, 9 Jun 2017 19:16:19 +0300
Subject: [PATCH 958/972] adi_board.tcl: reset xilinx ip second commit

---
 projects/scripts/adi_board.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 1448a0690..347c4c2bb 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -214,9 +214,9 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
   ad_connect  ${a_jesd}/${txrx}_sync $m_sync
   ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk
   ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
-  ad_connect  sys_cpu_clk ${a_jesd}_rstgen/slowest_sync_clk
+  ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk
   ad_connect  sys_cpu_resetn ${a_jesd}_rstgen/ext_reset_in
-  ad_connect  ${a_jesd}_rstgen/peripheral_reset ${a_jesd}/${txrx}_reset
+  ad_connect  sys_cpu_reset ${a_jesd}/${txrx}_reset
 
   if {$tx_or_rx_n == 0} {
     set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]

From 105b9e7114ef58baa44aa0c8949d8a49669ca5fc Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Wed, 14 Jun 2017 11:33:11 +0300
Subject: [PATCH 959/972] fmcadc5: Delete clock and reset duplicate connection

---
 projects/fmcadc5/common/fmcadc5_bd.tcl | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl
index e1f008564..bb5f8d6d2 100644
--- a/projects/fmcadc5/common/fmcadc5_bd.tcl
+++ b/projects/fmcadc5/common/fmcadc5_bd.tcl
@@ -95,13 +95,8 @@ ad_connect  sys_cpu_clk util_fmcadc5_1_xcvr/up_clk
 ad_xcvrcon  util_fmcadc5_0_xcvr axi_ad9625_0_xcvr axi_ad9625_0_jesd
 ad_xcvrcon  util_fmcadc5_1_xcvr axi_ad9625_1_xcvr axi_ad9625_1_jesd
 
-delete_bd_objs [get_bd_nets -of_objects [get_bd_pins util_fmcadc5_1_xcvr/rx_out_clk_0]]
-delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9625_1_jesd_rstgen/peripheral_reset]]
 delete_bd_objs [get_bd_cells axi_ad9625_1_jesd_rstgen]
 
-ad_xcvrpll  util_fmcadc5_0_xcvr/rx_out_clk_0 util_fmcadc5_1_xcvr/rx_clk_*
-ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_jesd/rx_core_clk
-ad_connect  axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_1_jesd/rx_reset
 ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_0_core/rx_clk
 ad_connect  axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_0_core/rx_sof
 ad_connect  axi_ad9625_0_jesd/rx_tdata axi_ad9625_0_core/rx_data

From 25a99498999e8de32460f103dab1aeeeec623d80 Mon Sep 17 00:00:00 2001
From: Matthew Fornero <mfornero@mathworks.com>
Date: Mon, 19 Jun 2017 02:40:53 -0400
Subject: [PATCH 960/972] util_clkdiv: Register output port as a clock (#33)

If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
---
 library/util_clkdiv/util_clkdiv_ip.tcl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl
index 0dd707ae5..998098dd4 100644
--- a/library/util_clkdiv/util_clkdiv_ip.tcl
+++ b/library/util_clkdiv/util_clkdiv_ip.tcl
@@ -22,4 +22,7 @@ set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters S
 set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
 set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
 
+adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \
+  [list {"clk_out" "CLK"}]
+
 ipx::save_core [ipx::current_core]

From 4ccaeffc8f265d39a1475017fc207d4bbc30a6e3 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 20 Mar 2017 12:15:18 -0400
Subject: [PATCH 961/972] arradio/c5soc- updated to new framework/16.0

---
 projects/arradio/common/arradio_qsys.tcl    | 151 ++++++++++
 projects/common/c5soc/c5soc_system_qsys.tcl | 302 ++++++++++++++++++++
 2 files changed, 453 insertions(+)
 create mode 100755 projects/arradio/common/arradio_qsys.tcl
 create mode 100755 projects/common/c5soc/c5soc_system_qsys.tcl

diff --git a/projects/arradio/common/arradio_qsys.tcl b/projects/arradio/common/arradio_qsys.tcl
new file mode 100755
index 000000000..49cb57b51
--- /dev/null
+++ b/projects/arradio/common/arradio_qsys.tcl
@@ -0,0 +1,151 @@
+
+# ad9361
+
+add_instance axi_ad9361 axi_ad9361 1.0
+set_instance_parameter_value axi_ad9361 {ID} {0}
+set_instance_parameter_value axi_ad9361 {MODE_1R1T} {0}
+set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {1}
+set_instance_parameter_value axi_ad9361 {TDD_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {CMOS_OR_LVDS_N} {0}
+set_instance_parameter_value axi_ad9361 {ADC_DATAPATH_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {DAC_DATAPATH_DISABLE} {0}
+add_interface axi_ad9361_device_if conduit end
+set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
+add_interface axi_ad9361_up_enable conduit end
+set_interface_property axi_ad9361_up_enable EXPORT_OF axi_ad9361.if_up_enable
+add_interface axi_ad9361_up_txnrx conduit end
+set_interface_property axi_ad9361_up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
+add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk
+add_connection sys_clk.clk axi_ad9361.if_delay_clk
+add_connection sys_clk.clk axi_ad9361.s_axi_clock
+add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
+
+# adc-wfifo & dac-rfifo
+
+add_instance util_adc_wfifo util_wfifo 1.0
+set_instance_parameter_value util_adc_wfifo {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value util_adc_wfifo {DIN_DATA_WIDTH} {16}
+set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
+set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
+add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
+add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
+add_connection sys_dma_clk.clk util_adc_wfifo.if_dout_clk
+add_connection sys_dma_clk.clk_reset util_adc_wfifo.if_dout_rstn
+add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
+add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
+add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
+add_connection axi_ad9361.adc_ch_3 util_adc_wfifo.din_3
+add_connection util_adc_wfifo.if_din_ovf axi_ad9361.if_adc_dovf
+
+# adc-wfifo & dac-rfifo
+
+add_instance util_dac_rfifo util_rfifo 1.0
+set_instance_parameter_value util_dac_rfifo {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value util_dac_rfifo {DIN_DATA_WIDTH} {16}
+set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
+set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
+add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
+add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
+add_connection sys_dma_clk.clk util_dac_rfifo.if_din_clk
+add_connection sys_dma_clk.clk_reset util_dac_rfifo.if_din_rstn
+add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
+add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
+add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
+add_connection util_dac_rfifo.dout_3 axi_ad9361.dac_ch_3
+add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
+
+# adc-pack & dac-unpack
+
+add_instance util_adc_pack util_cpack 1.0
+set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value util_adc_pack {CHANNEL_DATA_WIDTH} {16}
+add_connection sys_dma_clk.clk util_adc_pack.if_adc_clk
+add_connection sys_dma_clk.clk_reset util_adc_pack.if_adc_rst
+add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
+add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
+add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
+add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
+
+# adc-pack & dac-unpack
+
+add_instance util_dac_upack util_upack 1.0
+set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value util_dac_upack {CHANNEL_DATA_WIDTH} {16}
+add_connection sys_dma_clk.clk util_dac_upack.if_dac_clk
+add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
+add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
+add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
+add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
+
+# adc-dma & dac-dma
+
+add_instance axi_adc_dma axi_dmac 1.0
+set_instance_parameter_value axi_adc_dma {ID} {0}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
+set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
+set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
+add_connection sys_clk.clk axi_adc_dma.s_axi_clock
+add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
+add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
+add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
+add_connection sys_dma_clk.clk axi_adc_dma.if_fifo_wr_clk
+add_connection util_adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
+add_connection util_adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
+add_connection util_adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
+add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_wfifo.if_dout_ovf
+
+# adc-dma & dac-dma
+
+add_instance axi_dac_dma axi_dmac 1.0
+set_instance_parameter_value axi_dac_dma {ID} {0}
+set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
+set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
+set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
+add_connection sys_clk.clk axi_dac_dma.s_axi_clock
+add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
+add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
+add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
+add_connection sys_dma_clk.clk axi_dac_dma.if_fifo_rd_clk
+add_connection util_dac_upack.if_dac_valid axi_dac_dma.if_fifo_rd_en
+add_connection axi_dac_dma.if_fifo_rd_dout util_dac_upack.if_dac_data
+add_connection axi_dac_dma.if_fifo_rd_xfer_req util_dac_upack.if_dma_xfer_in
+add_connection axi_dac_dma.if_fifo_rd_underflow util_dac_rfifo.if_din_unf
+
+# interrupts
+
+ad_cpu_interrupt 2 axi_adc_dma.interrupt_sender
+ad_cpu_interrupt 3 axi_dac_dma.interrupt_sender
+
+# cpu interconnects
+
+ad_cpu_interconnect 0x00120000 axi_ad9361.s_axi
+ad_cpu_interconnect 0x00100000 axi_adc_dma.s_axi
+ad_cpu_interconnect 0x00104000 axi_dac_dma.s_axi
+
+# mem interconnects
+
+ad_dma_interconnect axi_adc_dma.m_dest_axi 0
+ad_dma_interconnect axi_dac_dma.m_src_axi 1
+
diff --git a/projects/common/c5soc/c5soc_system_qsys.tcl b/projects/common/c5soc/c5soc_system_qsys.tcl
new file mode 100755
index 000000000..c3f4ea573
--- /dev/null
+++ b/projects/common/c5soc/c5soc_system_qsys.tcl
@@ -0,0 +1,302 @@
+
+package require qsys
+
+set_module_property NAME {system_bd}
+set_project_property DEVICE_FAMILY {Cyclone V}
+set_project_property DEVICE {5CSXFC6D6F31C8ES}
+
+# system clock
+
+add_instance sys_clk clock_source 16.0
+set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
+set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
+add_interface sys_clk clock sink
+add_interface sys_rst reset sink
+set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
+set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
+
+# hps
+
+add_instance sys_hps altera_hps 16.0
+set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value sys_hps {F2SDRAM_Type} {Avalon-MM\ Bidirectional AXI-3 AXI-3}
+set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 64 64}
+set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
+set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A}
+set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
+set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
+set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
+set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {USB0_Mode} {N/A}
+set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
+set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {SPIM0_Mode} {N/A}
+set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select}
+set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
+set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
+set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
+set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
+set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
+set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
+set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
+set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
+set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
+set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3}
+set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
+set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32}
+set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
+set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
+set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
+set_instance_parameter_value sys_hps {MEM_TCL} {11}
+set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/7}
+set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
+set_instance_parameter_value sys_hps {MEM_WTCL} {8}
+set_instance_parameter_value sys_hps {MEM_RTT_WR} {RZQ/4}
+set_instance_parameter_value sys_hps {TIMING_TIS} {180}
+set_instance_parameter_value sys_hps {TIMING_TIH} {140}
+set_instance_parameter_value sys_hps {TIMING_TDS} {30}
+set_instance_parameter_value sys_hps {TIMING_TDH} {65}
+set_instance_parameter_value sys_hps {TIMING_TDQSQ} {125}
+set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
+set_instance_parameter_value sys_hps {TIMING_TDQSCK} {255}
+set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25}
+set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
+set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2}
+set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2}
+set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
+set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
+set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
+set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
+set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
+set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
+set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
+set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
+set_instance_parameter_value sys_hps {MEM_TWTR} {4}
+set_instance_parameter_value sys_hps {MEM_TFAW_NS} {30.0}
+set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5}
+set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
+set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.03}
+set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.02}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {0.09}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.16}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.01}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.08}
+set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.03}
+set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
+add_interface sys_hps_memory conduit end
+set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory
+add_interface sys_hps_hps_io conduit end
+set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io
+add_interface sys_hps_h2f_reset reset source
+set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset
+add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
+add_connection sys_clk.clk sys_hps.h2f_axi_clock
+add_connection sys_clk.clk sys_hps.f2h_axi_clock
+add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
+
+# cpu/hps handling
+
+proc ad_cpu_interrupt {m_irq m_port} {
+
+  add_connection sys_hps.f2h_irq0 ${m_port}
+  set_connection_parameter_value sys_hsp.f2h_irq0/${m_port} irqNumber ${m_irq}
+}
+
+proc ad_cpu_interconnect {m_base m_port} {
+
+  add_connection sys_hps.h2f_lw_axi_master ${m_port}
+  set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
+}
+
+proc ad_dma_interconnect {m_port m_id} {
+
+  if {${id} == 1} {
+    add_connection ${m_port} sys_hps.f2h_sdram1_data
+    set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram1_data baseAddress {0x0000}
+  }
+
+  add_connection ${m_port} sys_hps.f2h_sdram2_data
+  set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram2_data baseAddress {0x0000}
+}
+
+# common dma interfaces
+
+add_instance sys_dma_clk clock_source 16.0
+add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
+add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
+add_connection sys_dma_clk.clk sys_hps.f2h_sdram1_clock
+add_connection sys_dma_clk.clk sys_hps.f2h_sdram2_clock
+
+# internal memory
+
+add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
+set_instance_parameter_value sys_int_mem {dualPort} {0}
+set_instance_parameter_value sys_int_mem {dataWidth} {64}
+set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
+set_instance_parameter_value sys_int_mem {initMemContent} {0}
+add_connection sys_clk.clk sys_int_mem.clk1
+add_connection sys_clk.clk_reset sys_int_mem.reset1
+add_connection sys_hps.h2f_axi_master sys_int_mem.s1
+set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000}
+
+# display (vga-pll)
+
+add_instance vga_pll altera_pll 16.0
+set_instance_parameter_value vga_pll {gui_device_speed_grade} {2}
+set_instance_parameter_value vga_pll {gui_reference_clock_frequency} {50.0}
+set_instance_parameter_value vga_pll {gui_use_locked} {0}
+set_instance_parameter_value vga_pll {gui_number_of_clocks} {2}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency0} {85.5}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency1} {171.0}
+add_connection sys_clk.clk vga_pll.refclk
+add_connection sys_clk.clk_reset vga_pll.reset
+
+# display (vga-frame-reader)
+
+add_instance vga_frame_reader alt_vip_vfr 16.0
+set_instance_parameter_value vga_frame_reader {BITS_PER_PIXEL_PER_COLOR_PLANE} {8}
+set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_PARALLEL} {4}
+set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_SEQUENCE} {1}
+set_instance_parameter_value vga_frame_reader {MAX_IMAGE_WIDTH} {1360}
+set_instance_parameter_value vga_frame_reader {MAX_IMAGE_HEIGHT} {768}
+set_instance_parameter_value vga_frame_reader {MEM_PORT_WIDTH} {128}
+set_instance_parameter_value vga_frame_reader {RMASTER_FIFO_DEPTH} {64}
+set_instance_parameter_value vga_frame_reader {RMASTER_BURST_TARGET} {32}
+set_instance_parameter_value vga_frame_reader {CLOCKS_ARE_SEPARATE} {1}
+add_connection sys_clk.clk vga_frame_reader.clock_master
+add_connection sys_clk.clk_reset vga_frame_reader.clock_master_reset
+add_connection vga_frame_reader.avalon_master sys_hps.f2h_sdram0_data
+set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data baseAddress {0x0000}
+add_connection vga_pll.outclk0 vga_frame_reader.clock_reset
+add_connection sys_clk.clk_reset vga_frame_reader.clock_reset_reset
+
+# display (vga-out-clock)
+
+add_instance vga_out_clock altera_clock_bridge 16.0
+set_instance_parameter_value vga_out_clock {NUM_CLOCK_OUTPUTS} {1}
+add_connection vga_pll.outclk0 vga_out_clock.in_clk
+add_interface vga_out_clk clock source
+set_interface_property vga_out_clk EXPORT_OF vga_out_clock.out_clk
+
+# display (vga-out-data)
+
+add_instance vga_out_data alt_vip_itc 14.0
+set_instance_parameter_value vga_out_data {H_ACTIVE_PIXELS} {1360}
+set_instance_parameter_value vga_out_data {V_ACTIVE_LINES} {768}
+set_instance_parameter_value vga_out_data {BPS} {8}
+set_instance_parameter_value vga_out_data {NUMBER_OF_COLOUR_PLANES} {4}
+set_instance_parameter_value vga_out_data {COLOUR_PLANES_ARE_IN_PARALLEL} {1}
+set_instance_parameter_value vga_out_data {ACCEPT_COLOURS_IN_SEQ} {0}
+set_instance_parameter_value vga_out_data {INTERLACED} {0}
+set_instance_parameter_value vga_out_data {USE_EMBEDDED_SYNCS} {0}
+set_instance_parameter_value vga_out_data {AP_LINE} {0}
+set_instance_parameter_value vga_out_data {ANC_LINE} {0}
+set_instance_parameter_value vga_out_data {H_BLANK} {0}
+set_instance_parameter_value vga_out_data {V_BLANK} {0}
+set_instance_parameter_value vga_out_data {H_SYNC_LENGTH} {112}
+set_instance_parameter_value vga_out_data {H_FRONT_PORCH} {64}
+set_instance_parameter_value vga_out_data {H_BACK_PORCH} {256}
+set_instance_parameter_value vga_out_data {V_SYNC_LENGTH} {6}
+set_instance_parameter_value vga_out_data {V_FRONT_PORCH} {3}
+set_instance_parameter_value vga_out_data {V_BACK_PORCH} {18}
+set_instance_parameter_value vga_out_data {F_RISING_EDGE} {0}
+set_instance_parameter_value vga_out_data {F_FALLING_EDGE} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_RISING_EDGE} {0}
+set_instance_parameter_value vga_out_data {FIELD0_ANC_LINE} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_BLANK} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_SYNC_LENGTH} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_FRONT_PORCH} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_BACK_PORCH} {0}
+set_instance_parameter_value vga_out_data {FIFO_DEPTH} {1920}
+set_instance_parameter_value vga_out_data {THRESHOLD} {1919}
+set_instance_parameter_value vga_out_data {CLOCKS_ARE_SAME} {0}
+set_instance_parameter_value vga_out_data {USE_CONTROL} {0}
+set_instance_parameter_value vga_out_data {GENERATE_SYNC} {0}
+set_instance_parameter_value vga_out_data {NO_OF_MODES} {1}
+set_instance_parameter_value vga_out_data {STD_WIDTH} {1}
+add_connection vga_pll.outclk0 vga_out_data.is_clk_rst
+add_connection sys_clk.clk_reset vga_out_data.is_clk_rst_reset
+add_connection vga_frame_reader.avalon_streaming_source vga_out_data.din
+add_interface vga_out_data conduit end
+set_interface_property vga_out_data EXPORT_OF vga_out_data.clocked_video
+
+# id
+
+add_instance sys_id altera_avalon_sysid_qsys 16.0
+set_instance_parameter_value sys_id {id} {-1395322110}
+add_connection sys_clk.clk sys_id.clk
+add_connection sys_clk.clk_reset sys_id.reset
+
+# gpio-bd
+
+add_instance sys_gpio_bd altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_bd {direction} {InOut}
+set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_bd {width} {32}
+add_connection sys_clk.clk sys_gpio_bd.clk
+add_connection sys_clk.clk_reset sys_gpio_bd.reset
+add_interface sys_gpio_bd conduit end
+set_interface_property sys_gpio_bd EXPORT_OF sys_gpio.external_connection
+
+# gpio-in
+
+add_instance sys_gpio_in altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_in {direction} {Input}
+set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_in {width} {32}
+add_connection sys_clk.clk_reset sys_gpio_in.reset
+add_connection sys_clk.clk sys_gpio_in.clk
+add_interface sys_gpio_in conduit end
+set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
+
+# gpio-out
+
+add_instance sys_gpio_out altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_out {direction} {Output}
+set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
+set_instance_parameter_value sys_gpio_out {width} {32}
+add_connection sys_clk.clk_reset sys_gpio_out.reset
+add_connection sys_clk.clk sys_gpio_out.clk
+add_interface sys_gpio_out conduit end
+set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
+
+# spi
+
+add_instance sys_spi altera_avalon_spi 16.0
+set_instance_parameter_value sys_spi {clockPhase} {0}
+set_instance_parameter_value sys_spi {clockPolarity} {1}
+set_instance_parameter_value sys_spi {dataWidth} {8}
+set_instance_parameter_value sys_spi {masterSPI} {1}
+set_instance_parameter_value sys_spi {numberOfSlaves} {1}
+set_instance_parameter_value sys_spi {targetClockRate} {50000000.0}
+add_connection sys_clk.clk sys_spi.clk
+add_connection sys_clk.clk_reset sys_spi.reset
+add_interface sys_spi conduit end
+set_interface_property sys_spi EXPORT_OF sys_spi.external
+
+# interrupts
+
+ad_cpu_interrupt 0 sys_gpio_bd.irq
+ad_cpu_interrupt 1 sys_spi.irq
+ad_cpu_interrupt 4 vga_frame_reader.interrupt_sender
+
+# cpu interconnects
+
+ad_cpu_interconnect 0x00108000 sys_spi.spi_control_port
+ad_cpu_interconnect 0x00009000 vga_frame_reader.avalon_slave
+ad_cpu_interconnect 0x00010000 sys_id.control_slave
+ad_cpu_interconnect 0x00010080 sys_gpio_bd.s1
+ad_cpu_interconnect 0x00010100 sys_gpio_in.s1
+ad_cpu_interconnect 0x00109000 sys_gpio_out.s1
+

From 2554677123d2258d01d87b1172f3255aa9407ef6 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 20 Mar 2017 15:56:07 -0400
Subject: [PATCH 962/972] arradio/c5soc- remove qsys files

---
 projects/arradio/c5soc/system_bd.qsys      |  390 ----
 projects/arradio/common/arradio_bd.qsys    |  936 ----------
 projects/common/c5soc/c5soc_system_bd.qsys | 1864 --------------------
 3 files changed, 3190 deletions(-)
 delete mode 100644 projects/arradio/c5soc/system_bd.qsys
 delete mode 100755 projects/arradio/common/arradio_bd.qsys
 delete mode 100644 projects/common/c5soc/c5soc_system_bd.qsys

diff --git a/projects/arradio/c5soc/system_bd.qsys b/projects/arradio/c5soc/system_bd.qsys
deleted file mode 100644
index 15acbb0a3..000000000
--- a/projects/arradio/c5soc/system_bd.qsys
+++ /dev/null
@@ -1,390 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element arradio
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element arradio.axi_ad9361_s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element arradio.axi_dmac_adc_s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element arradio.axi_dmac_dac_s_axi
-   {
-      datum baseAddress
-      {
-         value = "16384";
-         type = "String";
-      }
-   }
-   element arradio.gpio_s1
-   {
-      datum baseAddress
-      {
-         value = "36864";
-         type = "String";
-      }
-   }
-   element arradio.spi_ad9361_spi_control_port
-   {
-      datum baseAddress
-      {
-         value = "32768";
-         type = "String";
-      }
-   }
-   element c5soc
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5CSXFC6D6F31C8ES" />
- <parameter name="deviceFamily" value="Cyclone V" />
- <parameter name="deviceSpeedGrade" value="8_H6" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="arradio_c5soc.qpf" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="axi_ad9361_delay_clk"
-   internal="arradio.axi_ad9361_delay_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_ad9361_device_clock"
-   internal="arradio.axi_ad9361_device_clock" />
- <interface
-   name="axi_ad9361_device_if"
-   internal="arradio.axi_ad9361_device_if"
-   type="conduit"
-   dir="end" />
- <interface name="axi_ad9361_l_clk" internal="arradio.axi_ad9361_l_clk" />
- <interface
-   name="axi_ad9361_up_enable"
-   internal="arradio.axi_ad9361_up_enable"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9361_up_txnrx"
-   internal="arradio.axi_ad9361_up_txnrx"
-   type="conduit"
-   dir="end" />
- <interface
-   name="gpio"
-   internal="arradio.gpio_external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="spi"
-   internal="arradio.spi_ad9361_external"
-   type="conduit"
-   dir="end" />
- <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
- <interface
-   name="sys_gpio"
-   internal="c5soc.sys_gpio_external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_io"
-   internal="c5soc.sys_hps_hps_io"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_mem"
-   internal="c5soc.sys_hps_memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_reset"
-   internal="c5soc.sys_hps_h2f_reset"
-   type="reset"
-   dir="start" />
- <interface name="sys_hps_spim0" internal="c5soc.sys_hps_spim0" />
- <interface name="sys_hps_spim0_sclk_out" internal="c5soc.sys_hps_spim0_sclk_out" />
- <interface
-   name="sys_reset"
-   internal="sys_clk.clk_in_reset"
-   type="reset"
-   dir="end" />
- <interface
-   name="vga_clk"
-   internal="c5soc.vga_pixel_clock_bridge_out_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="vga_if"
-   internal="c5soc.vga_clock_video_output_clocked_video"
-   type="conduit"
-   dir="end" />
- <module name="arradio" kind="arradio_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 32" />
-  <parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram2_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
-     value="AddressWidth = 32" />
-  <parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="6" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="80000000" />
-  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
-  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_arradio</parameter>
- </module>
- <module name="c5soc" kind="c5soc_system_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
-  <parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
-  <parameter
-     name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
-     value="AddressWidth = 18" />
-  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" />
-  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" />
- </module>
- <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
-  <parameter name="clockFrequency" value="50000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="arradio.axi_dmac_adc_m_dest_axi"
-   end="c5soc.sys_mem_interconnect_axi0_s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="arradio.axi_dmac_dac_m_src_axi"
-   end="c5soc.sys_mem_interconnect_axi1_s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="c5soc.sys_cpu_interconnect_m0"
-   end="arradio.axi_ad9361_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="c5soc.sys_cpu_interconnect_m0"
-   end="arradio.axi_dmac_adc_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="c5soc.sys_cpu_interconnect_m0"
-   end="arradio.axi_dmac_dac_s_axi">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x4000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="c5soc.sys_cpu_interconnect_m0"
-   end="arradio.gpio_s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x9000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="c5soc.sys_cpu_interconnect_m0"
-   end="arradio.spi_ad9361_spi_control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x8000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection kind="clock" version="15.1" start="sys_clk.clk" end="c5soc.sys_clk" />
- <connection kind="clock" version="15.1" start="sys_clk.clk" end="arradio.sys_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="c5soc.mem_clk"
-   end="arradio.mem_clk" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="c5soc.sys_intr"
-   end="arradio.axi_dmac_adc_intr">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="c5soc.sys_intr"
-   end="arradio.axi_dmac_dac_intr">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="c5soc.sys_intr"
-   end="arradio.spi_ad9361_irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="c5soc.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_clk.clk_reset"
-   end="arradio.sys_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="c5soc.mem_rst"
-   end="arradio.mem_rst" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
- <interconnectRequirement
-   for="mm_interconnect_0|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_2|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
-</system>
diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys
deleted file mode 100755
index dbd04f1ef..000000000
--- a/projects/arradio/common/arradio_bd.qsys
+++ /dev/null
@@ -1,936 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element arradio_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element axi_ad9361
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9361.s_axi
-   {
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element axi_adc_dma
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_adc_dma.s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element axi_dac_dma
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_dac_dma.s_axi
-   {
-      datum baseAddress
-      {
-         value = "16384";
-         type = "String";
-      }
-   }
-   element gpio
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element mem_clk
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element mem_rst
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element spi_ad9361
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element spi_ad9361.spi_control_port
-   {
-      datum baseAddress
-      {
-         value = "32768";
-         type = "String";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element util_adc_pack
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element util_adc_wfifo
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element util_dac_rfifo
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element util_dac_upack
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5CSXFC6D6F31C8ES" />
- <parameter name="deviceFamily" value="Cyclone V" />
- <parameter name="deviceSpeedGrade" value="8_H6" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="axi_ad9361_delay_clk"
-   internal="axi_ad9361.if_delay_clk"
-   type="clock"
-   dir="end" />
- <interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
- <interface
-   name="axi_ad9361_device_if"
-   internal="axi_ad9361.device_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9361_s_axi"
-   internal="axi_ad9361.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_ad9361_up_enable"
-   internal="axi_ad9361.if_up_enable"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9361_up_txnrx"
-   internal="axi_ad9361.if_up_txnrx"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_dmac_adc_fifo_wr_clock"
-   internal="axi_adc_dma.fifo_wr_clock" />
- <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_adc_dma.fifo_wr_if" />
- <interface
-   name="axi_dmac_adc_intr"
-   internal="axi_adc_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_adc_m_dest_axi"
-   internal="axi_adc_dma.m_dest_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_adc_s_axi"
-   internal="axi_adc_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="axi_dmac_dac_fifo_rd_clock"
-   internal="axi_dac_dma.fifo_rd_clock" />
- <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dac_dma.fifo_rd_if" />
- <interface
-   name="axi_dmac_dac_intr"
-   internal="axi_dac_dma.interrupt_sender"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="axi_dmac_dac_m_src_axi"
-   internal="axi_dac_dma.m_src_axi"
-   type="axi4"
-   dir="start" />
- <interface
-   name="axi_dmac_dac_s_axi"
-   internal="axi_dac_dma.s_axi"
-   type="axi4lite"
-   dir="end" />
- <interface
-   name="gpio_external_connection"
-   internal="gpio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface name="gpio_s1" internal="gpio.s1" type="avalon" dir="end" />
- <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
- <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="spi_ad9361_external"
-   internal="spi_ad9361.external"
-   type="conduit"
-   dir="end" />
- <interface
-   name="spi_ad9361_irq"
-   internal="spi_ad9361.irq"
-   type="interrupt"
-   dir="end" />
- <interface
-   name="spi_ad9361_spi_control_port"
-   internal="spi_ad9361.spi_control_port"
-   type="avalon"
-   dir="end" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
-  <parameter name="ADC_DATAPATH_DISABLE" value="0" />
-  <parameter name="CMOS_OR_LVDS_N" value="0" />
-  <parameter name="DAC_DATAPATH_DISABLE" value="0" />
-  <parameter name="DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="DEVICE_TYPE" value="1" />
-  <parameter name="ID" value="0" />
- </module>
- <module name="axi_adc_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="0" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="0" />
-  <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="1" />
- </module>
- <module name="axi_dac_dma" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
-  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
-  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
-  <parameter name="AXI_SLICE_DEST" value="0" />
-  <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="1" />
-  <parameter name="DMA_2D_TRANSFER" value="0" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="24" />
-  <parameter name="DMA_TYPE_DEST" value="2" />
-  <parameter name="DMA_TYPE_SRC" value="0" />
-  <parameter name="FIFO_SIZE" value="4" />
-  <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
- </module>
- <module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="50000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="5" />
- </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="1" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="50000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="1" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="50000000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="util_adc_pack" kind="util_cpack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="util_adc_wfifo" kind="util_wfifo" version="1.0" enabled="1">
-  <parameter name="DIN_ADDRESS_WIDTH" value="5" />
-  <parameter name="DIN_DATA_WIDTH" value="16" />
-  <parameter name="DOUT_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="util_dac_rfifo" kind="util_rfifo" version="1.0" enabled="1">
-  <parameter name="DIN_ADDRESS_WIDTH" value="5" />
-  <parameter name="DIN_DATA_WIDTH" value="16" />
-  <parameter name="DOUT_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <module name="util_dac_upack" kind="util_upack" version="1.0" enabled="1">
-  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
-  <parameter name="NUM_OF_CHANNELS" value="4" />
- </module>
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="axi_ad9361.if_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="util_adc_wfifo.if_din_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="axi_ad9361.if_l_clk"
-   end="util_dac_rfifo.if_dout_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="spi_ad9361.clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="util_adc_pack.if_adc_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="util_dac_upack.if_dac_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="util_dac_rfifo.if_din_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="util_adc_wfifo.if_dout_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_dac_dma.if_fifo_rd_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_adc_dma.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_adc_dma.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="mem_clk.out_clk"
-   end="axi_dac_dma.m_src_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_ad9361.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_adc_dma.s_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="axi_dac_dma.s_axi_clock" />
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.adc_ch_0"
-   end="util_adc_wfifo.din_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.adc_ch_1"
-   end="util_adc_wfifo.din_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_adc_pack.adc_ch_1"
-   end="util_adc_wfifo.dout_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.adc_ch_2"
-   end="util_adc_wfifo.din_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_adc_pack.adc_ch_2"
-   end="util_adc_wfifo.dout_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.adc_ch_3"
-   end="util_adc_wfifo.din_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_upack.dac_ch_0"
-   end="util_dac_rfifo.din_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_upack.dac_ch_1"
-   end="util_dac_rfifo.din_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.dac_ch_1"
-   end="util_dac_rfifo.dout_1">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_upack.dac_ch_2"
-   end="util_dac_rfifo.din_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_upack.dac_ch_3"
-   end="util_dac_rfifo.din_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_ad9361.dac_ch_3"
-   end="util_dac_rfifo.dout_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_adc_wfifo.dout_0"
-   end="util_adc_pack.adc_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_rfifo.dout_0"
-   end="axi_ad9361.dac_ch_0">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_rfifo.dout_2"
-   end="axi_ad9361.dac_ch_2">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_adc_wfifo.dout_3"
-   end="util_adc_pack.adc_ch_3">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_adc_pack.if_adc_data"
-   end="axi_adc_dma.if_fifo_wr_din">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_adc_pack.if_adc_sync"
-   end="axi_adc_dma.if_fifo_wr_sync">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_adc_pack.if_adc_valid"
-   end="axi_adc_dma.if_fifo_wr_en">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_upack.if_dac_data"
-   end="axi_dac_dma.if_fifo_rd_dout">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_adc_wfifo.if_din_ovf"
-   end="axi_ad9361.if_adc_dovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_upack.if_dma_xfer_in"
-   end="axi_dac_dma.if_fifo_rd_xfer_req">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="util_dac_rfifo.if_dout_unf"
-   end="axi_ad9361.if_dac_dunf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dac_dma.if_fifo_rd_en"
-   end="util_dac_upack.if_dac_valid">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_dac_dma.if_fifo_rd_underflow"
-   end="util_dac_rfifo.if_din_unf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="conduit"
-   version="15.1"
-   start="axi_adc_dma.if_fifo_wr_overflow"
-   end="util_adc_wfifo.if_dout_ovf">
-  <parameter name="endPort" value="" />
-  <parameter name="endPortLSB" value="0" />
-  <parameter name="startPort" value="" />
-  <parameter name="startPortLSB" value="0" />
-  <parameter name="width" value="0" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_ad9361.if_rst"
-   end="util_adc_wfifo.if_din_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="axi_ad9361.if_rst"
-   end="util_dac_rfifo.if_dout_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="util_adc_pack.if_adc_rst" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="util_dac_rfifo.if_din_rstn" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="util_adc_wfifo.if_dout_rstn" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="axi_adc_dma.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="mem_rst.out_reset"
-   end="axi_dac_dma.m_src_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="spi_ad9361.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="gpio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_ad9361.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_adc_dma.s_axi_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="axi_dac_dma.s_axi_reset" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
- <interconnectRequirement
-   for="mm_interconnect_0|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_2|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
-</system>
diff --git a/projects/common/c5soc/c5soc_system_bd.qsys b/projects/common/c5soc/c5soc_system_bd.qsys
deleted file mode 100644
index 51cbefb5e..000000000
--- a/projects/common/c5soc/c5soc_system_bd.qsys
+++ /dev/null
@@ -1,1864 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element mem_clk
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element mem_rst
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-   }
-   element sys_clk
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_cpu_interconnect
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_cpu_interconnect.s0
-   {
-      datum baseAddress
-      {
-         value = "1048576";
-         type = "String";
-      }
-   }
-   element sys_gpio
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_gpio.external_connection
-   {
-      datum _tags
-      {
-         value = "";
-         type = "String";
-      }
-   }
-   element sys_gpio.s1
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "65664";
-         type = "String";
-      }
-   }
-   element sys_hps
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_hps.f2h_sdram0_data
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_id.control_slave
-   {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-   element sys_int_mem
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_int_mem.s1
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_intr
-   {
-      datum _sortIndex
-      {
-         value = "15";
-         type = "int";
-      }
-   }
-   element sys_mem_interconnect_axi0
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_mem_interconnect_axi1
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_rst
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element system_bd
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element vga_clock_video_output
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element vga_frame_reader
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element vga_frame_reader.avalon_slave
-   {
-      datum baseAddress
-      {
-         value = "36864";
-         type = "String";
-      }
-   }
-   element vga_pixel_clock_bridge
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element vga_pll
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="FIFO" />
- <parameter name="device" value="5CSXFC6D6F31C8ES" />
- <parameter name="deviceFamily" value="Cyclone V" />
- <parameter name="deviceSpeedGrade" value="8_H6" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="hps_0_f2h_cold_reset_req" internal="sys_hps.f2h_cold_reset_req" />
- <interface
-   name="hps_0_f2h_debug_reset_req"
-   internal="sys_hps.f2h_debug_reset_req" />
- <interface name="hps_0_f2h_warm_reset_req" internal="sys_hps.f2h_warm_reset_req" />
- <interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
- <interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface
-   name="sys_cpu_interconnect_m0"
-   internal="sys_cpu_interconnect.m0"
-   type="axi"
-   dir="start" />
- <interface
-   name="sys_gpio_external_connection"
-   internal="sys_gpio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface name="sys_hps_f2h_stm_hw_events" internal="sys_hps.f2h_stm_hw_events" />
- <interface
-   name="sys_hps_h2f_reset"
-   internal="sys_hps.h2f_reset"
-   type="reset"
-   dir="start" />
- <interface
-   name="sys_hps_hps_io"
-   internal="sys_hps.hps_io"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_hps_memory"
-   internal="sys_hps.memory"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_intr"
-   internal="sys_intr.receiver_irq"
-   type="interrupt"
-   dir="start" />
- <interface
-   name="sys_mem_interconnect_axi0_s0"
-   internal="sys_mem_interconnect_axi0.s0"
-   type="axi"
-   dir="end" />
- <interface
-   name="sys_mem_interconnect_axi1_s0"
-   internal="sys_mem_interconnect_axi1.s0"
-   type="axi"
-   dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
- <interface
-   name="vga_clock_video_output_clocked_video"
-   internal="vga_clock_video_output.clocked_video"
-   type="conduit"
-   dir="end" />
- <interface
-   name="vga_pixel_clock_bridge_out_clk"
-   internal="vga_pixel_clock_bridge.out_clk"
-   type="clock"
-   dir="start" />
- <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="80000000" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module
-   name="sys_cpu_interconnect"
-   kind="altera_axi_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDR_WIDTH" value="20" />
-  <parameter name="AXI_VERSION" value="AXI3" />
-  <parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="COMBINED_ISSUING_CAPABILITY" value="16" />
-  <parameter name="DATA_WIDTH" value="32" />
-  <parameter name="M0_ID_WIDTH" value="12" />
-  <parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="READ_ADDR_USER_WIDTH" value="64" />
-  <parameter name="READ_DATA_REORDERING_DEPTH" value="1" />
-  <parameter name="READ_DATA_USER_WIDTH" value="64" />
-  <parameter name="READ_ISSUING_CAPABILITY" value="16" />
-  <parameter name="S0_ID_WIDTH" value="12" />
-  <parameter name="USE_M0_ARBURST" value="1" />
-  <parameter name="USE_M0_ARCACHE" value="1" />
-  <parameter name="USE_M0_ARID" value="1" />
-  <parameter name="USE_M0_ARLEN" value="1" />
-  <parameter name="USE_M0_ARLOCK" value="1" />
-  <parameter name="USE_M0_ARQOS" value="1" />
-  <parameter name="USE_M0_ARREGION" value="1" />
-  <parameter name="USE_M0_ARSIZE" value="1" />
-  <parameter name="USE_M0_ARUSER" value="0" />
-  <parameter name="USE_M0_AWBURST" value="1" />
-  <parameter name="USE_M0_AWCACHE" value="1" />
-  <parameter name="USE_M0_AWID" value="1" />
-  <parameter name="USE_M0_AWLEN" value="1" />
-  <parameter name="USE_M0_AWLOCK" value="1" />
-  <parameter name="USE_M0_AWQOS" value="1" />
-  <parameter name="USE_M0_AWREGION" value="1" />
-  <parameter name="USE_M0_AWSIZE" value="1" />
-  <parameter name="USE_M0_AWUSER" value="0" />
-  <parameter name="USE_M0_BID" value="1" />
-  <parameter name="USE_M0_BRESP" value="1" />
-  <parameter name="USE_M0_BUSER" value="0" />
-  <parameter name="USE_M0_RID" value="1" />
-  <parameter name="USE_M0_RLAST" value="1" />
-  <parameter name="USE_M0_RRESP" value="1" />
-  <parameter name="USE_M0_RUSER" value="0" />
-  <parameter name="USE_M0_WSTRB" value="1" />
-  <parameter name="USE_M0_WUSER" value="0" />
-  <parameter name="USE_PIPELINE" value="1" />
-  <parameter name="USE_S0_ARCACHE" value="1" />
-  <parameter name="USE_S0_ARLOCK" value="1" />
-  <parameter name="USE_S0_ARPROT" value="1" />
-  <parameter name="USE_S0_ARQOS" value="1" />
-  <parameter name="USE_S0_ARREGION" value="1" />
-  <parameter name="USE_S0_ARUSER" value="0" />
-  <parameter name="USE_S0_AWCACHE" value="1" />
-  <parameter name="USE_S0_AWLOCK" value="1" />
-  <parameter name="USE_S0_AWPROT" value="1" />
-  <parameter name="USE_S0_AWQOS" value="1" />
-  <parameter name="USE_S0_AWREGION" value="1" />
-  <parameter name="USE_S0_AWUSER" value="0" />
-  <parameter name="USE_S0_BRESP" value="1" />
-  <parameter name="USE_S0_BUSER" value="0" />
-  <parameter name="USE_S0_RRESP" value="1" />
-  <parameter name="USE_S0_RUSER" value="0" />
-  <parameter name="USE_S0_WLAST" value="1" />
-  <parameter name="USE_S0_WUSER" value="0" />
-  <parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="WRITE_ADDR_USER_WIDTH" value="64" />
-  <parameter name="WRITE_DATA_USER_WIDTH" value="64" />
-  <parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
-  <parameter name="WRITE_RESP_USER_WIDTH" value="64" />
- </module>
- <module name="sys_gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="true" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="true" />
-  <parameter name="clockRate" value="0" />
-  <parameter name="direction" value="InOut" />
-  <parameter name="edgeType" value="ANY" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="EDGE" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="32" />
- </module>
- <module name="sys_hps" kind="altera_hps" version="15.1" enabled="1">
-  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-  <parameter name="AC_PACKAGE_DESKEW" value="false" />
-  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-  <parameter name="ADDR_ORDER" value="0" />
-  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
-  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-  <parameter name="ADVANCED_CK_PHASES" value="false" />
-  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
-  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-  <parameter name="AP_MODE" value="false" />
-  <parameter name="AP_MODE_EN" value="0" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
-  <parameter name="AUTO_PD_CYCLES" value="0" />
-  <parameter name="AUTO_POWERDN_EN" value="false" />
-  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-  <parameter name="AVL_MAX_SIZE" value="4" />
-  <parameter name="BONDING_OUT_ENABLED" value="false" />
-  <parameter name="BOOTFROMFPGA_Enable" value="false" />
-  <parameter name="BSEL" value="1" />
-  <parameter name="BSEL_EN" value="false" />
-  <parameter name="BYTE_ENABLE" value="true" />
-  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="CALIBRATION_MODE" value="Skip" />
-  <parameter name="CALIB_REG_WIDTH" value="8" />
-  <parameter name="CAN0_Mode" value="N/A" />
-  <parameter name="CAN0_PinMuxing" value="Unused" />
-  <parameter name="CAN1_Mode" value="N/A" />
-  <parameter name="CAN1_PinMuxing" value="Unused" />
-  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-  <parameter name="CFG_REORDER_DATA" value="true" />
-  <parameter name="CFG_TCCD_NS" value="2.5" />
-  <parameter name="COMMAND_PHASE" value="0.0" />
-  <parameter name="CONTROLLER_LATENCY" value="5" />
-  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
-  <parameter name="CSEL" value="0" />
-  <parameter name="CSEL_EN" value="false" />
-  <parameter name="CTI_Enable" value="false" />
-  <parameter name="CTL_AUTOPCH_EN" value="false" />
-  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
-  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="CTL_CSR_ENABLED" value="false" />
-  <parameter name="CTL_CSR_READ_ONLY" value="1" />
-  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
-  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-  <parameter name="CTL_ECC_ENABLED" value="false" />
-  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
-  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="true" />
-  <parameter name="CTL_HRB_ENABLED" value="false" />
-  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTL_USR_REFRESH_EN" value="false" />
-  <parameter name="CTL_ZQCAL_EN" value="false" />
-  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
-  <parameter name="DAT_DATA_WIDTH" value="32" />
-  <parameter name="DEBUGAPB_Enable" value="false" />
-  <parameter name="DEBUG_MODE" value="false" />
-  <parameter name="DEVICE_DEPTH" value="1" />
-  <parameter name="DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
-  <parameter name="DISCRETE_FLY_BY" value="true" />
-  <parameter name="DLL_SHARING_MODE" value="None" />
-  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
-  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
-  <parameter name="DUPLICATE_AC" value="false" />
-  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
-  <parameter name="EMAC0_Mode" value="N/A" />
-  <parameter name="EMAC0_PinMuxing" value="Unused" />
-  <parameter name="EMAC1_Mode" value="RGMII" />
-  <parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-  <parameter name="ENABLE_BONDING" value="false" />
-  <parameter name="ENABLE_BURST_MERGE" value="false" />
-  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
-  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
-  <parameter name="ENABLE_ISS_PROBES" value="false" />
-  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
-  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-  <parameter name="ENABLE_USER_ECC" value="false" />
-  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
-  <parameter name="EXTRA_SETTINGS" value="" />
-  <parameter name="F2H_AXI_CLOCK_FREQ" value="0" />
-  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="0" />
-  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="80000000" />
-  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="80000000" />
-  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
-  <parameter name="F2SCLK_COLDRST_Enable" value="false" />
-  <parameter name="F2SCLK_DBGRST_Enable" value="false" />
-  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
-  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
-  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
-  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
-  <parameter name="F2SCLK_WARMRST_Enable" value="false" />
-  <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional,AXI-3,AXI-3</parameter>
-  <parameter name="F2SDRAM_Width" value="64,64,64" />
-  <parameter name="F2SINTERRUPT_Enable" value="true" />
-  <parameter name="F2S_Width" value="2" />
-  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
-  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
-  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
-  <parameter
-     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
-     value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="100.0" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="100.0" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
-  <parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
-  <parameter name="GP_Enable" value="false" />
-  <parameter name="H2F_AXI_CLOCK_FREQ" value="0" />
-  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="0" />
-  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
-  <parameter name="HARD_EMIF" value="true" />
-  <parameter name="HCX_COMPAT_MODE" value="false" />
-  <parameter name="HHP_HPS" value="true" />
-  <parameter name="HHP_HPS_SIMULATION" value="false" />
-  <parameter name="HHP_HPS_VERIFICATION" value="false" />
-  <parameter name="HLGPI_Enable" value="false" />
-  <parameter name="HPS_PROTOCOL" value="DDR3" />
-  <parameter name="I2C0_Mode" value="N/A" />
-  <parameter name="I2C0_PinMuxing" value="Unused" />
-  <parameter name="I2C1_Mode" value="N/A" />
-  <parameter name="I2C1_PinMuxing" value="Unused" />
-  <parameter name="I2C2_Mode" value="N/A" />
-  <parameter name="I2C2_PinMuxing" value="Unused" />
-  <parameter name="I2C3_Mode" value="N/A" />
-  <parameter name="I2C3_PinMuxing" value="Unused" />
-  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="IS_ES_DEVICE" value="false" />
-  <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
-  <parameter name="LOCAL_ID_WIDTH" value="8" />
-  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
-  <parameter name="LWH2F_Enable" value="true" />
-  <parameter name="MARGIN_VARIATION_TEST" value="false" />
-  <parameter name="MAX_PENDING_RD_CMD" value="16" />
-  <parameter name="MAX_PENDING_WR_CMD" value="8" />
-  <parameter name="MEM_ASR" value="Manual" />
-  <parameter name="MEM_ATCL" value="Disabled" />
-  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
-  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
-  <parameter name="MEM_BL" value="OTF" />
-  <parameter name="MEM_BT" value="Sequential" />
-  <parameter name="MEM_CK_PHASE" value="0.0" />
-  <parameter name="MEM_CK_WIDTH" value="1" />
-  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
-  <parameter name="MEM_CLK_FREQ" value="400.0" />
-  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
-  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_CS_WIDTH" value="1" />
-  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
-  <parameter name="MEM_DLL_EN" value="true" />
-  <parameter name="MEM_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DQ_WIDTH" value="32" />
-  <parameter name="MEM_DRV_STR" value="RZQ/7" />
-  <parameter name="MEM_FORMAT" value="DISCRETE" />
-  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
-  <parameter name="MEM_IF_DQSN_EN" value="true" />
-  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-  <parameter name="MEM_INIT_EN" value="false" />
-  <parameter name="MEM_INIT_FILE" value="" />
-  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
-  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_PD" value="DLL off" />
-  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
-  <parameter name="MEM_RTT_WR" value="RZQ/4" />
-  <parameter name="MEM_SRT" value="Normal" />
-  <parameter name="MEM_TCL" value="11" />
-  <parameter name="MEM_TFAW_NS" value="30.0" />
-  <parameter name="MEM_TINIT_US" value="500" />
-  <parameter name="MEM_TMRD_CK" value="4" />
-  <parameter name="MEM_TRAS_NS" value="35.0" />
-  <parameter name="MEM_TRCD_NS" value="13.75" />
-  <parameter name="MEM_TREFI_US" value="7.8" />
-  <parameter name="MEM_TRFC_NS" value="260.0" />
-  <parameter name="MEM_TRP_NS" value="13.75" />
-  <parameter name="MEM_TRRD_NS" value="7.5" />
-  <parameter name="MEM_TRTP_NS" value="7.5" />
-  <parameter name="MEM_TWR_NS" value="15.0" />
-  <parameter name="MEM_TWTR" value="4" />
-  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
-  <parameter name="MEM_VENDOR" value="JEDEC" />
-  <parameter name="MEM_VERBOSE" value="true" />
-  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
-  <parameter name="MEM_WTCL" value="8" />
-  <parameter name="MPU_EVENTS_Enable" value="false" />
-  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-  <parameter name="MULTICAST_EN" value="false" />
-  <parameter name="NAND_Mode" value="N/A" />
-  <parameter name="NAND_PinMuxing" value="Unused" />
-  <parameter name="NEXTGEN" value="true" />
-  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
-  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
-  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_OF_PORTS" value="1" />
-  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
-  <parameter name="OCT_SHARING_MODE" value="None" />
-  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="PACKAGE_DESKEW" value="false" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="PHY_CSR_ENABLED" value="false" />
-  <parameter name="PHY_ONLY" value="false" />
-  <parameter name="PINGPONGPHY_EN" value="false" />
-  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
-  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_LOCATION" value="Top_Bottom" />
-  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_SHARING_MODE" value="None" />
-  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="POWER_OF_TWO_BUS" value="false" />
-  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-  <parameter name="QSPI_Mode" value="1 SS" />
-  <parameter name="QSPI_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="RATE" value="Full" />
-  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-  <parameter name="READ_FIFO_SIZE" value="8" />
-  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
-  <parameter name="REFRESH_INTERVAL" value="15000" />
-  <parameter name="REF_CLK_FREQ" value="25.0" />
-  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
-  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
-  <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
-  <parameter name="S2FCLK_USER1CLK_Enable" value="false" />
-  <parameter name="S2FCLK_USER1CLK_FREQ" value="100.0" />
-  <parameter name="S2FCLK_USER2CLK" value="4" />
-  <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
-  <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
-  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
-  <parameter name="S2F_Width" value="2" />
-  <parameter name="SDIO_Mode" value="4-bit Data" />
-  <parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="SEQUENCER_TYPE" value="NIOS" />
-  <parameter name="SEQ_MODE" value="0" />
-  <parameter name="SKIP_MEM_INIT" value="true" />
-  <parameter name="SOPC_COMPAT_RESET" value="false" />
-  <parameter name="SPEED_GRADE" value="7" />
-  <parameter name="SPIM0_Mode" value="N/A" />
-  <parameter name="SPIM0_PinMuxing" value="Unused" />
-  <parameter name="SPIM1_Mode" value="Single Slave Select" />
-  <parameter name="SPIM1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="SPIS0_Mode" value="N/A" />
-  <parameter name="SPIS0_PinMuxing" value="Unused" />
-  <parameter name="SPIS1_Mode" value="N/A" />
-  <parameter name="SPIS1_PinMuxing" value="Unused" />
-  <parameter name="STARVE_LIMIT" value="10" />
-  <parameter name="STM_Enable" value="false" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="TEST_Enable" value="false" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_SKEW" value="0.03" />
-  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
-  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.02" />
-  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.16" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.09" />
-  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
-  <parameter name="TIMING_BOARD_TDH" value="0.0" />
-  <parameter name="TIMING_BOARD_TDS" value="0.0" />
-  <parameter name="TIMING_BOARD_TIH" value="0.0" />
-  <parameter name="TIMING_BOARD_TIS" value="0.0" />
-  <parameter name="TIMING_TDH" value="65" />
-  <parameter name="TIMING_TDQSCK" value="255" />
-  <parameter name="TIMING_TDQSCKDL" value="1200" />
-  <parameter name="TIMING_TDQSCKDM" value="900" />
-  <parameter name="TIMING_TDQSCKDS" value="450" />
-  <parameter name="TIMING_TDQSH" value="0.35" />
-  <parameter name="TIMING_TDQSQ" value="125" />
-  <parameter name="TIMING_TDQSS" value="0.25" />
-  <parameter name="TIMING_TDS" value="30" />
-  <parameter name="TIMING_TDSH" value="0.2" />
-  <parameter name="TIMING_TDSS" value="0.2" />
-  <parameter name="TIMING_TIH" value="140" />
-  <parameter name="TIMING_TIS" value="180" />
-  <parameter name="TIMING_TQH" value="0.38" />
-  <parameter name="TIMING_TQHS" value="300" />
-  <parameter name="TIMING_TQSH" value="0.4" />
-  <parameter name="TPIUFPGA_Enable" value="false" />
-  <parameter name="TPIUFPGA_alt" value="false" />
-  <parameter name="TRACE_Mode" value="N/A" />
-  <parameter name="TRACE_PinMuxing" value="Unused" />
-  <parameter name="TRACKING_ERROR_TEST" value="false" />
-  <parameter name="TRACKING_WATCH_TEST" value="false" />
-  <parameter name="TREFI" value="35100" />
-  <parameter name="TRFC" value="350" />
-  <parameter name="UART0_Mode" value="No Flow Control" />
-  <parameter name="UART0_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="UART1_Mode" value="N/A" />
-  <parameter name="UART1_PinMuxing" value="Unused" />
-  <parameter name="USB0_Mode" value="N/A" />
-  <parameter name="USB0_PinMuxing" value="Unused" />
-  <parameter name="USB1_Mode" value="SDR" />
-  <parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="USER_DEBUG_LEVEL" value="1" />
-  <parameter name="USE_AXI_ADAPTOR" value="false" />
-  <parameter name="USE_FAKE_PHY" value="false" />
-  <parameter name="USE_MEM_CLK_FREQ" value="false" />
-  <parameter name="USE_MM_ADAPTOR" value="true" />
-  <parameter name="USE_SEQUENCER_BFM" value="false" />
-  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
-  <parameter name="can0_clk_div" value="1" />
-  <parameter name="can1_clk_div" value="1" />
-  <parameter name="configure_advanced_parameters" value="false" />
-  <parameter name="customize_device_pll_info" value="false" />
-  <parameter name="dbctrl_stayosc1" value="true" />
-  <parameter name="dbg_at_clk_div" value="0" />
-  <parameter name="dbg_clk_div" value="1" />
-  <parameter name="dbg_trace_clk_div" value="0" />
-  <parameter name="desired_can0_clk_mhz" value="100.0" />
-  <parameter name="desired_can1_clk_mhz" value="100.0" />
-  <parameter name="desired_cfg_clk_mhz" value="80.0" />
-  <parameter name="desired_emac0_clk_mhz" value="250.0" />
-  <parameter name="desired_emac1_clk_mhz" value="250.0" />
-  <parameter name="desired_gpio_db_clk_hz" value="32000" />
-  <parameter name="desired_l4_mp_clk_mhz" value="100.0" />
-  <parameter name="desired_l4_sp_clk_mhz" value="100.0" />
-  <parameter name="desired_mpu_clk_mhz" value="800.0" />
-  <parameter name="desired_nand_clk_mhz" value="12.5" />
-  <parameter name="desired_qspi_clk_mhz" value="400.0" />
-  <parameter name="desired_sdmmc_clk_mhz" value="200.0" />
-  <parameter name="desired_spi_m_clk_mhz" value="200.0" />
-  <parameter name="desired_usb_mp_clk_mhz" value="200.0" />
-  <parameter name="device_name" value="5CSXFC6D6F31C8ES" />
-  <parameter name="device_pll_info_manual">{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}</parameter>
-  <parameter name="eosc1_clk_mhz" value="25.0" />
-  <parameter name="eosc2_clk_mhz" value="25.0" />
-  <parameter name="gpio_db_clk_div" value="6249" />
-  <parameter name="l3_mp_clk_div" value="1" />
-  <parameter name="l3_sp_clk_div" value="1" />
-  <parameter name="l4_mp_clk_div" value="1" />
-  <parameter name="l4_mp_clk_source" value="1" />
-  <parameter name="l4_sp_clk_div" value="1" />
-  <parameter name="l4_sp_clk_source" value="1" />
-  <parameter name="main_pll_c3" value="3" />
-  <parameter name="main_pll_c4" value="3" />
-  <parameter name="main_pll_c5" value="15" />
-  <parameter name="main_pll_m" value="63" />
-  <parameter name="main_pll_n" value="0" />
-  <parameter name="nand_clk_source" value="2" />
-  <parameter name="periph_pll_c0" value="3" />
-  <parameter name="periph_pll_c1" value="3" />
-  <parameter name="periph_pll_c2" value="1" />
-  <parameter name="periph_pll_c3" value="19" />
-  <parameter name="periph_pll_c4" value="4" />
-  <parameter name="periph_pll_c5" value="9" />
-  <parameter name="periph_pll_m" value="79" />
-  <parameter name="periph_pll_n" value="1" />
-  <parameter name="periph_pll_source" value="0" />
-  <parameter name="qspi_clk_source" value="1" />
-  <parameter name="quartus_ini_hps_emif_pll" value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
-     value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
-     value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
-     value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
-  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
-  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
-  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
-  <parameter name="sdmmc_clk_source" value="2" />
-  <parameter name="show_advanced_parameters" value="false" />
-  <parameter name="show_debug_info_as_warning_msg" value="false" />
-  <parameter name="show_warning_as_error_msg" value="false" />
-  <parameter name="spi_m_clk_div" value="0" />
-  <parameter name="usb_mp_clk_div" value="0" />
-  <parameter name="use_default_mpu_clk" value="true" />
- </module>
- <module
-   name="sys_id"
-   kind="altera_avalon_sysid_qsys"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="id" value="-1395322110" />
- </module>
- <module
-   name="sys_int_mem"
-   kind="altera_avalon_onchip_memory2"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="64" />
-  <parameter name="deviceFamily" value="Cyclone V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_memory2_0" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="65536" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module name="sys_intr" kind="altera_irq_bridge" version="15.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
-  <parameter name="IRQ_N" value="0" />
-  <parameter name="IRQ_WIDTH" value="8" />
- </module>
- <module
-   name="sys_mem_interconnect_axi0"
-   kind="altera_axi_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDR_WIDTH" value="32" />
-  <parameter name="AXI_VERSION" value="AXI3" />
-  <parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="COMBINED_ISSUING_CAPABILITY" value="16" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="M0_ID_WIDTH" value="4" />
-  <parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="READ_ADDR_USER_WIDTH" value="64" />
-  <parameter name="READ_DATA_REORDERING_DEPTH" value="1" />
-  <parameter name="READ_DATA_USER_WIDTH" value="64" />
-  <parameter name="READ_ISSUING_CAPABILITY" value="16" />
-  <parameter name="S0_ID_WIDTH" value="4" />
-  <parameter name="USE_M0_ARBURST" value="1" />
-  <parameter name="USE_M0_ARCACHE" value="1" />
-  <parameter name="USE_M0_ARID" value="1" />
-  <parameter name="USE_M0_ARLEN" value="1" />
-  <parameter name="USE_M0_ARLOCK" value="1" />
-  <parameter name="USE_M0_ARQOS" value="1" />
-  <parameter name="USE_M0_ARREGION" value="1" />
-  <parameter name="USE_M0_ARSIZE" value="1" />
-  <parameter name="USE_M0_ARUSER" value="0" />
-  <parameter name="USE_M0_AWBURST" value="1" />
-  <parameter name="USE_M0_AWCACHE" value="1" />
-  <parameter name="USE_M0_AWID" value="1" />
-  <parameter name="USE_M0_AWLEN" value="1" />
-  <parameter name="USE_M0_AWLOCK" value="1" />
-  <parameter name="USE_M0_AWQOS" value="1" />
-  <parameter name="USE_M0_AWREGION" value="1" />
-  <parameter name="USE_M0_AWSIZE" value="1" />
-  <parameter name="USE_M0_AWUSER" value="0" />
-  <parameter name="USE_M0_BID" value="1" />
-  <parameter name="USE_M0_BRESP" value="1" />
-  <parameter name="USE_M0_BUSER" value="0" />
-  <parameter name="USE_M0_RID" value="1" />
-  <parameter name="USE_M0_RLAST" value="1" />
-  <parameter name="USE_M0_RRESP" value="1" />
-  <parameter name="USE_M0_RUSER" value="0" />
-  <parameter name="USE_M0_WSTRB" value="1" />
-  <parameter name="USE_M0_WUSER" value="0" />
-  <parameter name="USE_PIPELINE" value="1" />
-  <parameter name="USE_S0_ARCACHE" value="1" />
-  <parameter name="USE_S0_ARLOCK" value="1" />
-  <parameter name="USE_S0_ARPROT" value="1" />
-  <parameter name="USE_S0_ARQOS" value="1" />
-  <parameter name="USE_S0_ARREGION" value="1" />
-  <parameter name="USE_S0_ARUSER" value="0" />
-  <parameter name="USE_S0_AWCACHE" value="1" />
-  <parameter name="USE_S0_AWLOCK" value="1" />
-  <parameter name="USE_S0_AWPROT" value="1" />
-  <parameter name="USE_S0_AWQOS" value="1" />
-  <parameter name="USE_S0_AWREGION" value="1" />
-  <parameter name="USE_S0_AWUSER" value="0" />
-  <parameter name="USE_S0_BRESP" value="1" />
-  <parameter name="USE_S0_BUSER" value="0" />
-  <parameter name="USE_S0_RRESP" value="1" />
-  <parameter name="USE_S0_RUSER" value="0" />
-  <parameter name="USE_S0_WLAST" value="1" />
-  <parameter name="USE_S0_WUSER" value="0" />
-  <parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="WRITE_ADDR_USER_WIDTH" value="64" />
-  <parameter name="WRITE_DATA_USER_WIDTH" value="64" />
-  <parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
-  <parameter name="WRITE_RESP_USER_WIDTH" value="64" />
- </module>
- <module
-   name="sys_mem_interconnect_axi1"
-   kind="altera_axi_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDR_WIDTH" value="32" />
-  <parameter name="AXI_VERSION" value="AXI3" />
-  <parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="COMBINED_ISSUING_CAPABILITY" value="16" />
-  <parameter name="DATA_WIDTH" value="64" />
-  <parameter name="M0_ID_WIDTH" value="8" />
-  <parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="READ_ADDR_USER_WIDTH" value="64" />
-  <parameter name="READ_DATA_REORDERING_DEPTH" value="1" />
-  <parameter name="READ_DATA_USER_WIDTH" value="64" />
-  <parameter name="READ_ISSUING_CAPABILITY" value="16" />
-  <parameter name="S0_ID_WIDTH" value="8" />
-  <parameter name="USE_M0_ARBURST" value="1" />
-  <parameter name="USE_M0_ARCACHE" value="1" />
-  <parameter name="USE_M0_ARID" value="1" />
-  <parameter name="USE_M0_ARLEN" value="1" />
-  <parameter name="USE_M0_ARLOCK" value="1" />
-  <parameter name="USE_M0_ARQOS" value="1" />
-  <parameter name="USE_M0_ARREGION" value="1" />
-  <parameter name="USE_M0_ARSIZE" value="1" />
-  <parameter name="USE_M0_ARUSER" value="0" />
-  <parameter name="USE_M0_AWBURST" value="1" />
-  <parameter name="USE_M0_AWCACHE" value="1" />
-  <parameter name="USE_M0_AWID" value="1" />
-  <parameter name="USE_M0_AWLEN" value="1" />
-  <parameter name="USE_M0_AWLOCK" value="1" />
-  <parameter name="USE_M0_AWQOS" value="1" />
-  <parameter name="USE_M0_AWREGION" value="1" />
-  <parameter name="USE_M0_AWSIZE" value="1" />
-  <parameter name="USE_M0_AWUSER" value="0" />
-  <parameter name="USE_M0_BID" value="1" />
-  <parameter name="USE_M0_BRESP" value="1" />
-  <parameter name="USE_M0_BUSER" value="0" />
-  <parameter name="USE_M0_RID" value="1" />
-  <parameter name="USE_M0_RLAST" value="1" />
-  <parameter name="USE_M0_RRESP" value="1" />
-  <parameter name="USE_M0_RUSER" value="0" />
-  <parameter name="USE_M0_WSTRB" value="1" />
-  <parameter name="USE_M0_WUSER" value="0" />
-  <parameter name="USE_PIPELINE" value="1" />
-  <parameter name="USE_S0_ARCACHE" value="1" />
-  <parameter name="USE_S0_ARLOCK" value="1" />
-  <parameter name="USE_S0_ARPROT" value="1" />
-  <parameter name="USE_S0_ARQOS" value="1" />
-  <parameter name="USE_S0_ARREGION" value="1" />
-  <parameter name="USE_S0_ARUSER" value="0" />
-  <parameter name="USE_S0_AWCACHE" value="1" />
-  <parameter name="USE_S0_AWLOCK" value="1" />
-  <parameter name="USE_S0_AWPROT" value="1" />
-  <parameter name="USE_S0_AWQOS" value="1" />
-  <parameter name="USE_S0_AWREGION" value="1" />
-  <parameter name="USE_S0_AWUSER" value="0" />
-  <parameter name="USE_S0_BRESP" value="1" />
-  <parameter name="USE_S0_BUSER" value="0" />
-  <parameter name="USE_S0_RRESP" value="1" />
-  <parameter name="USE_S0_RUSER" value="0" />
-  <parameter name="USE_S0_WLAST" value="1" />
-  <parameter name="USE_S0_WUSER" value="0" />
-  <parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" />
-  <parameter name="WRITE_ADDR_USER_WIDTH" value="64" />
-  <parameter name="WRITE_DATA_USER_WIDTH" value="64" />
-  <parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
-  <parameter name="WRITE_RESP_USER_WIDTH" value="64" />
- </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
-  <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="none" />
-  <parameter name="USE_RESET_REQUEST" value="0" />
- </module>
- <module
-   name="vga_clock_video_output"
-   kind="alt_vip_itc"
-   version="14.0"
-   enabled="1">
-  <parameter name="ACCEPT_COLOURS_IN_SEQ" value="0" />
-  <parameter name="ANC_LINE" value="0" />
-  <parameter name="AP_LINE" value="0" />
-  <parameter name="BPS" value="8" />
-  <parameter name="CLOCKS_ARE_SAME" value="0" />
-  <parameter name="COLOUR_PLANES_ARE_IN_PARALLEL" value="1" />
-  <parameter name="FAMILY" value="Cyclone V" />
-  <parameter name="FIELD0_ANC_LINE" value="0" />
-  <parameter name="FIELD0_V_BACK_PORCH" value="0" />
-  <parameter name="FIELD0_V_BLANK" value="0" />
-  <parameter name="FIELD0_V_FRONT_PORCH" value="0" />
-  <parameter name="FIELD0_V_RISING_EDGE" value="0" />
-  <parameter name="FIELD0_V_SYNC_LENGTH" value="0" />
-  <parameter name="FIFO_DEPTH" value="1920" />
-  <parameter name="F_FALLING_EDGE" value="0" />
-  <parameter name="F_RISING_EDGE" value="0" />
-  <parameter name="GENERATE_SYNC" value="0" />
-  <parameter name="H_ACTIVE_PIXELS" value="1360" />
-  <parameter name="H_BACK_PORCH" value="256" />
-  <parameter name="H_BLANK" value="0" />
-  <parameter name="H_FRONT_PORCH" value="64" />
-  <parameter name="H_SYNC_LENGTH" value="112" />
-  <parameter name="INTERLACED" value="0" />
-  <parameter name="NO_OF_MODES" value="1" />
-  <parameter name="NUMBER_OF_COLOUR_PLANES" value="4" />
-  <parameter name="STD_WIDTH" value="1" />
-  <parameter name="THRESHOLD" value="1919" />
-  <parameter name="USE_CONTROL" value="0" />
-  <parameter name="USE_EMBEDDED_SYNCS" value="0" />
-  <parameter name="V_ACTIVE_LINES" value="768" />
-  <parameter name="V_BACK_PORCH" value="18" />
-  <parameter name="V_BLANK" value="0" />
-  <parameter name="V_FRONT_PORCH" value="3" />
-  <parameter name="V_SYNC_LENGTH" value="6" />
- </module>
- <module name="vga_frame_reader" kind="alt_vip_vfr" version="14.0" enabled="1">
-  <parameter name="AUTO_CLOCK_MASTER_CLOCK_RATE" value="0" />
-  <parameter name="AUTO_CLOCK_RESET_CLOCK_RATE" value="85500000" />
-  <parameter name="BITS_PER_PIXEL_PER_COLOR_PLANE" value="8" />
-  <parameter name="CLOCKS_ARE_SEPARATE" value="1" />
-  <parameter name="FAMILY" value="Cyclone V" />
-  <parameter name="MAX_IMAGE_HEIGHT" value="768" />
-  <parameter name="MAX_IMAGE_WIDTH" value="1360" />
-  <parameter name="MEM_PORT_WIDTH" value="128" />
-  <parameter name="NUMBER_OF_CHANNELS_IN_PARALLEL" value="4" />
-  <parameter name="NUMBER_OF_CHANNELS_IN_SEQUENCE" value="1" />
-  <parameter name="RMASTER_BURST_TARGET" value="32" />
-  <parameter name="RMASTER_FIFO_DEPTH" value="64" />
- </module>
- <module
-   name="vga_pixel_clock_bridge"
-   kind="altera_clock_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="85500000" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="vga_pll" kind="altera_pll" version="15.1" enabled="1">
-  <parameter name="debug_print_output" value="false" />
-  <parameter name="debug_use_rbc_taf_method" value="false" />
-  <parameter name="device" value="5CSXFC6D6F31C8ES" />
-  <parameter name="device_family" value="Cyclone V" />
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
-  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
-  <parameter name="gui_actual_phase_shift0" value="0" />
-  <parameter name="gui_actual_phase_shift1" value="0" />
-  <parameter name="gui_actual_phase_shift10" value="0" />
-  <parameter name="gui_actual_phase_shift11" value="0" />
-  <parameter name="gui_actual_phase_shift12" value="0" />
-  <parameter name="gui_actual_phase_shift13" value="0" />
-  <parameter name="gui_actual_phase_shift14" value="0" />
-  <parameter name="gui_actual_phase_shift15" value="0" />
-  <parameter name="gui_actual_phase_shift16" value="0" />
-  <parameter name="gui_actual_phase_shift17" value="0" />
-  <parameter name="gui_actual_phase_shift2" value="0" />
-  <parameter name="gui_actual_phase_shift3" value="0" />
-  <parameter name="gui_actual_phase_shift4" value="0" />
-  <parameter name="gui_actual_phase_shift5" value="0" />
-  <parameter name="gui_actual_phase_shift6" value="0" />
-  <parameter name="gui_actual_phase_shift7" value="0" />
-  <parameter name="gui_actual_phase_shift8" value="0" />
-  <parameter name="gui_actual_phase_shift9" value="0" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_channel_spacing" value="0.0" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_device_speed_grade" value="2" />
-  <parameter name="gui_divide_factor_c0" value="1" />
-  <parameter name="gui_divide_factor_c1" value="1" />
-  <parameter name="gui_divide_factor_c10" value="1" />
-  <parameter name="gui_divide_factor_c11" value="1" />
-  <parameter name="gui_divide_factor_c12" value="1" />
-  <parameter name="gui_divide_factor_c13" value="1" />
-  <parameter name="gui_divide_factor_c14" value="1" />
-  <parameter name="gui_divide_factor_c15" value="1" />
-  <parameter name="gui_divide_factor_c16" value="1" />
-  <parameter name="gui_divide_factor_c17" value="1" />
-  <parameter name="gui_divide_factor_c2" value="1" />
-  <parameter name="gui_divide_factor_c3" value="1" />
-  <parameter name="gui_divide_factor_c4" value="1" />
-  <parameter name="gui_divide_factor_c5" value="1" />
-  <parameter name="gui_divide_factor_c6" value="1" />
-  <parameter name="gui_divide_factor_c7" value="1" />
-  <parameter name="gui_divide_factor_c8" value="1" />
-  <parameter name="gui_divide_factor_c9" value="1" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_duty_cycle0" value="50" />
-  <parameter name="gui_duty_cycle1" value="50" />
-  <parameter name="gui_duty_cycle10" value="50" />
-  <parameter name="gui_duty_cycle11" value="50" />
-  <parameter name="gui_duty_cycle12" value="50" />
-  <parameter name="gui_duty_cycle13" value="50" />
-  <parameter name="gui_duty_cycle14" value="50" />
-  <parameter name="gui_duty_cycle15" value="50" />
-  <parameter name="gui_duty_cycle16" value="50" />
-  <parameter name="gui_duty_cycle17" value="50" />
-  <parameter name="gui_duty_cycle2" value="50" />
-  <parameter name="gui_duty_cycle3" value="50" />
-  <parameter name="gui_duty_cycle4" value="50" />
-  <parameter name="gui_duty_cycle5" value="50" />
-  <parameter name="gui_duty_cycle6" value="50" />
-  <parameter name="gui_duty_cycle7" value="50" />
-  <parameter name="gui_duty_cycle8" value="50" />
-  <parameter name="gui_duty_cycle9" value="50" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_en_reconf" value="false" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_number_of_clocks" value="2" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="85.5" />
-  <parameter name="gui_output_clock_frequency1" value="171.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="100.0" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_phase_shift0" value="0" />
-  <parameter name="gui_phase_shift1" value="0" />
-  <parameter name="gui_phase_shift10" value="0" />
-  <parameter name="gui_phase_shift11" value="0" />
-  <parameter name="gui_phase_shift12" value="0" />
-  <parameter name="gui_phase_shift13" value="0" />
-  <parameter name="gui_phase_shift14" value="0" />
-  <parameter name="gui_phase_shift15" value="0" />
-  <parameter name="gui_phase_shift16" value="0" />
-  <parameter name="gui_phase_shift17" value="0" />
-  <parameter name="gui_phase_shift2" value="0" />
-  <parameter name="gui_phase_shift3" value="0" />
-  <parameter name="gui_phase_shift4" value="0" />
-  <parameter name="gui_phase_shift5" value="0" />
-  <parameter name="gui_phase_shift6" value="0" />
-  <parameter name="gui_phase_shift7" value="0" />
-  <parameter name="gui_phase_shift8" value="0" />
-  <parameter name="gui_phase_shift9" value="0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_pll_auto_reset" value="Off" />
-  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
-  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="50.0" />
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_use_locked" value="false" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="vga_frame_reader.avalon_master"
-   end="sys_hps.f2h_sdram0_data">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_hps.h2f_axi_master"
-   end="sys_int_mem.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_hps.h2f_lw_axi_master"
-   end="vga_frame_reader.avalon_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x9000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_id.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_cpu_interconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00100000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_hps.h2f_lw_axi_master"
-   end="sys_gpio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010080" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_mem_interconnect_axi0.m0"
-   end="sys_hps.f2h_sdram1_data">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="sys_mem_interconnect_axi1.m0"
-   end="sys_hps.f2h_sdram2_data">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon_streaming"
-   version="15.1"
-   start="vga_frame_reader.avalon_streaming_source"
-   end="vga_clock_video_output.din" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_mem_interconnect_axi0.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_mem_interconnect_axi1.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_hps.f2h_sdram1_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_hps.h2f_user0_clock"
-   end="sys_hps.f2h_sdram2_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_hps.h2f_user0_clock"
-   end="mem_clk.in_clk" />
- <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_id.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_gpio.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_cpu_interconnect.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_intr.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="vga_frame_reader.clock_master" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_hps.f2h_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_hps.f2h_sdram0_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_hps.h2f_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="sys_hps.h2f_lw_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="sys_clk.out_clk"
-   end="vga_pll.refclk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="vga_pll.outclk0"
-   end="vga_frame_reader.clock_reset" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="vga_pll.outclk0"
-   end="vga_pixel_clock_bridge.in_clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="vga_pll.outclk0"
-   end="vga_clock_video_output.is_clk_rst" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="vga_frame_reader.interrupt_sender">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_gpio.irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender0_irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender1_irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender2_irq">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender3_irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender4_irq">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender5_irq">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender6_irq">
-  <parameter name="irqNumber" value="8" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="sys_hps.f2h_irq0"
-   end="sys_intr.sender7_irq">
-  <parameter name="irqNumber" value="9" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_cpu_interconnect.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_mem_interconnect_axi0.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_mem_interconnect_axi1.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_intr.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="vga_frame_reader.clock_master_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="vga_frame_reader.clock_reset_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="mem_rst.in_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="vga_clock_video_output.is_clk_rst_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_id.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_gpio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="vga_pll.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="sys_rst.out_reset"
-   end="sys_int_mem.reset1" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
- <interconnectRequirement
-   for="mm_interconnect_0|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_2|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_3|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
- <interconnectRequirement
-   for="mm_interconnect_4|cmd_mux_001"
-   name="qsys_mm.postTransform.pipelineCount"
-   value="0" />
-</system>

From 3c49470e08b1749bf5b5ed54b19894857d037e06 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 20 Mar 2017 15:42:33 -0400
Subject: [PATCH 963/972] arradio/c5soc- qsys-script flow

---
 projects/arradio/c5soc/system_qsys.tcl        |   5 +
 projects/arradio/c5soc/system_top.v           | 183 +++++++++---------
 projects/common/c5soc/c5soc_system_assign.tcl |  12 +-
 projects/common/c5soc/c5soc_system_qsys.tcl   |   9 +-
 4 files changed, 104 insertions(+), 105 deletions(-)
 create mode 100644 projects/arradio/c5soc/system_qsys.tcl

diff --git a/projects/arradio/c5soc/system_qsys.tcl b/projects/arradio/c5soc/system_qsys.tcl
new file mode 100644
index 000000000..7d0e88262
--- /dev/null
+++ b/projects/arradio/c5soc/system_qsys.tcl
@@ -0,0 +1,5 @@
+
+source $ad_hdl_dir/projects/common/c5soc/c5soc_system_qsys.tcl
+source ../common/arradio_qsys.tcl
+
+
diff --git a/projects/arradio/c5soc/system_top.v b/projects/arradio/c5soc/system_top.v
index 72475bbed..8a9956ae5 100644
--- a/projects/arradio/c5soc/system_top.v
+++ b/projects/arradio/c5soc/system_top.v
@@ -148,28 +148,28 @@ module system_top (
   // internal signals
 
   wire              sys_resetn;
+  wire    [ 31:0]   sys_gpio_bd_i;
+  wire    [ 31:0]   sys_gpio_bd_o;
   wire    [ 31:0]   sys_gpio_i;
   wire    [ 31:0]   sys_gpio_o;
-  wire    [  4:0]   gpio;
 
   // defaults
 
-  assign gpio_bd_o = sys_gpio_o[3:0];
-
-  assign sys_gpio_i[31:8] = sys_gpio_o[31:8];
-  assign sys_gpio_i[ 7:0] = gpio_bd_i;
-  
   assign vga_blank_n = 1'b1;
   assign vga_sync_n = 1'b0;
 
-  assign ad9361_resetb = gpio[4];
-  assign ad9361_en_agc = gpio[3];
-  assign ad9361_sync = gpio[2];
+  assign gpio_bd_o = sys_gpio_bd_o[3:0];
+
+  assign sys_gpio_bd_i[31:8] = sys_gpio_bd_o[31:8];
+  assign sys_gpio_bd_i[ 7:0] = gpio_bd_i;
+  
+  assign ad9361_resetb = sys_gpio_o[4];
+  assign ad9361_en_agc = sys_gpio_o[3];
+  assign ad9361_sync = sys_gpio_o[2];
 
   // instantiations
 
   system_bd i_system_bd (
-    .axi_ad9361_delay_clk_clk (1'd0),
     .axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
     .axi_ad9361_device_if_rx_clk_in_n (1'd0),
     .axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
@@ -184,88 +184,89 @@ module system_top (
     .axi_ad9361_device_if_tx_data_out_n (),
     .axi_ad9361_device_if_enable (enable),
     .axi_ad9361_device_if_txnrx (txnrx),
-    .axi_ad9361_up_enable_up_enable (gpio[1]),
-    .axi_ad9361_up_txnrx_up_txnrx (gpio[0]),
-    .gpio_export (gpio),
-    .spi_MISO (spi_miso),
-    .spi_MOSI (spi_mosi),
-    .spi_SCLK (spi_clk),
-    .spi_SS_n (spi_csn),
+    .axi_ad9361_up_enable_up_enable (sys_gpio_o[1]),
+    .axi_ad9361_up_txnrx_up_txnrx (sys_gpio_o[0]),
     .sys_clk_clk (sys_clk),
-    .sys_gpio_in_port (sys_gpio_i),
-    .sys_gpio_out_port (sys_gpio_o),
-    .sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
-    .sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
-    .sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
-    .sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
-    .sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
-    .sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
-    .sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
-    .sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
-    .sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
-    .sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
-    .sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
-    .sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
-    .sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
-    .sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
-    .sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]),
-    .sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]),
-    .sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]),
-    .sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]),
-    .sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
-    .sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
-    .sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
-    .sys_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
-    .sys_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
-    .sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
-    .sys_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
-    .sys_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
-    .sys_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
-    .sys_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
-    .sys_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
-    .sys_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
-    .sys_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
-    .sys_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
-    .sys_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
-    .sys_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
-    .sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
-    .sys_hps_io_hps_io_usb1_inst_STP (usb1_stp),
-    .sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
-    .sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
-    .sys_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
-    .sys_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
-    .sys_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
-    .sys_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
-    .sys_hps_io_hps_io_uart0_inst_RX (uart0_rx),
-    .sys_hps_io_hps_io_uart0_inst_TX (uart0_tx),
-    .sys_hps_mem_mem_a (ddr3_a),
-    .sys_hps_mem_mem_ba (ddr3_ba),
-    .sys_hps_mem_mem_ck (ddr3_ck_p),
-    .sys_hps_mem_mem_ck_n (ddr3_ck_n),
-    .sys_hps_mem_mem_cke (ddr3_cke),
-    .sys_hps_mem_mem_cs_n (ddr3_cs_n),
-    .sys_hps_mem_mem_ras_n (ddr3_ras_n),
-    .sys_hps_mem_mem_cas_n (ddr3_cas_n),
-    .sys_hps_mem_mem_we_n (ddr3_we_n),
-    .sys_hps_mem_mem_reset_n (ddr3_reset_n),
-    .sys_hps_mem_mem_dq (ddr3_dq),
-    .sys_hps_mem_mem_dqs (ddr3_dqs_p),
-    .sys_hps_mem_mem_dqs_n (ddr3_dqs_n),
-    .sys_hps_mem_mem_odt (ddr3_odt),
-    .sys_hps_mem_mem_dm (ddr3_dm),
-    .sys_hps_mem_oct_rzqin (ddr3_rzq),
-    .sys_hps_reset_reset_n (sys_resetn),
-    .sys_reset_reset_n (sys_resetn),
-    .vga_clk_clk (vga_clk),
-    .vga_if_vid_clk (vga_clk),
-    .vga_if_vid_data ({vga_red, vga_grn, vga_blu}),
-    .vga_if_underflow (),
-    .vga_if_vid_datavalid (),
-    .vga_if_vid_v_sync (vga_vsync),
-    .vga_if_vid_h_sync (vga_hsync),
-    .vga_if_vid_f (),
-    .vga_if_vid_h (),
-    .vga_if_vid_v ());
+    .sys_gpio_bd_in_port (sys_gpio_bd_i),
+    .sys_gpio_bd_out_port (sys_gpio_bd_o),
+    .sys_gpio_in_export (sys_gpio_i),
+    .sys_gpio_out_export (sys_gpio_o),
+    .sys_hps_h2f_reset_reset_n (sys_resetn),
+    .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
+    .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
+    .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
+    .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
+    .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
+    .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
+    .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
+    .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
+    .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
+    .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
+    .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
+    .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
+    .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
+    .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
+    .sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]),
+    .sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]),
+    .sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]),
+    .sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]),
+    .sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
+    .sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
+    .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
+    .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
+    .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
+    .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
+    .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
+    .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
+    .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
+    .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
+    .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
+    .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
+    .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
+    .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
+    .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
+    .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
+    .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
+    .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
+    .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
+    .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
+    .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
+    .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
+    .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
+    .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
+    .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
+    .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
+    .sys_hps_memory_mem_a (ddr3_a),
+    .sys_hps_memory_mem_ba (ddr3_ba),
+    .sys_hps_memory_mem_ck (ddr3_ck_p),
+    .sys_hps_memory_mem_ck_n (ddr3_ck_n),
+    .sys_hps_memory_mem_cke (ddr3_cke),
+    .sys_hps_memory_mem_cs_n (ddr3_cs_n),
+    .sys_hps_memory_mem_ras_n (ddr3_ras_n),
+    .sys_hps_memory_mem_cas_n (ddr3_cas_n),
+    .sys_hps_memory_mem_we_n (ddr3_we_n),
+    .sys_hps_memory_mem_reset_n (ddr3_reset_n),
+    .sys_hps_memory_mem_dq (ddr3_dq),
+    .sys_hps_memory_mem_dqs (ddr3_dqs_p),
+    .sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
+    .sys_hps_memory_mem_odt (ddr3_odt),
+    .sys_hps_memory_mem_dm (ddr3_dm),
+    .sys_hps_memory_oct_rzqin (ddr3_rzq),
+    .sys_rst_reset_n (sys_resetn),
+    .sys_spi_MISO (spi_miso),
+    .sys_spi_MOSI (spi_mosi),
+    .sys_spi_SCLK (spi_clk),
+    .sys_spi_SS_n (spi_csn),
+    .vga_out_clk_clk (vga_clk),
+    .vga_out_data_vid_clk (vga_clk),
+    .vga_out_data_vid_data ({vga_red, vga_grn, vga_blu}),
+    .vga_out_data_underflow (),
+    .vga_out_data_vid_datavalid (),
+    .vga_out_data_vid_v_sync (vga_vsync),
+    .vga_out_data_vid_h_sync (vga_hsync),
+    .vga_out_data_vid_f (),
+    .vga_out_data_vid_h (),
+    .vga_out_data_vid_v ());
 
 endmodule
 
diff --git a/projects/common/c5soc/c5soc_system_assign.tcl b/projects/common/c5soc/c5soc_system_assign.tcl
index 46d7f375b..dc7d69968 100755
--- a/projects/common/c5soc/c5soc_system_assign.tcl
+++ b/projects/common/c5soc/c5soc_system_assign.tcl
@@ -461,14 +461,6 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
 set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
-# set libraries
-
-set ad_lib_folders "../common/;../../common/c5soc/;../../../library/**/*"
-
-set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders
-set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders
-
-
-
-
+# source defaults
 
+source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
diff --git a/projects/common/c5soc/c5soc_system_qsys.tcl b/projects/common/c5soc/c5soc_system_qsys.tcl
index c3f4ea573..63349c195 100755
--- a/projects/common/c5soc/c5soc_system_qsys.tcl
+++ b/projects/common/c5soc/c5soc_system_qsys.tcl
@@ -110,7 +110,7 @@ add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
 proc ad_cpu_interrupt {m_irq m_port} {
 
   add_connection sys_hps.f2h_irq0 ${m_port}
-  set_connection_parameter_value sys_hsp.f2h_irq0/${m_port} irqNumber ${m_irq}
+  set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
 }
 
 proc ad_cpu_interconnect {m_base m_port} {
@@ -121,9 +121,10 @@ proc ad_cpu_interconnect {m_base m_port} {
 
 proc ad_dma_interconnect {m_port m_id} {
 
-  if {${id} == 1} {
+  if {${m_id} == 1} {
     add_connection ${m_port} sys_hps.f2h_sdram1_data
     set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram1_data baseAddress {0x0000}
+    return
   }
 
   add_connection ${m_port} sys_hps.f2h_sdram2_data
@@ -164,7 +165,7 @@ add_connection sys_clk.clk_reset vga_pll.reset
 
 # display (vga-frame-reader)
 
-add_instance vga_frame_reader alt_vip_vfr 16.0
+add_instance vga_frame_reader alt_vip_vfr 14.0
 set_instance_parameter_value vga_frame_reader {BITS_PER_PIXEL_PER_COLOR_PLANE} {8}
 set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_PARALLEL} {4}
 set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_SEQUENCE} {1}
@@ -247,7 +248,7 @@ set_instance_parameter_value sys_gpio_bd {width} {32}
 add_connection sys_clk.clk sys_gpio_bd.clk
 add_connection sys_clk.clk_reset sys_gpio_bd.reset
 add_interface sys_gpio_bd conduit end
-set_interface_property sys_gpio_bd EXPORT_OF sys_gpio.external_connection
+set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
 
 # gpio-in
 

From c21c6813a5d268a61d91a21f5b7bfff63b1f5ffd Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri, 23 Jun 2017 15:53:43 +0300
Subject: [PATCH 964/972] arradio c5soc: Update project to tcl flow.

 -Update to tcl flow
 -Add missing i2c interface
---
 projects/arradio/c5soc/Makefile               |    2 +
 projects/arradio/c5soc/soc_system.rbf         |  Bin 0 -> 7007204 bytes
 projects/arradio/c5soc/system_bd.tcl          | 1321 +++++++++++++++++
 projects/arradio/c5soc/system_project.tcl     |   12 +
 projects/arradio/c5soc/system_top.v           |   25 +-
 projects/common/c5soc/c5soc_system_assign.tcl |   75 +
 projects/common/c5soc/c5soc_system_qsys.tcl   |    8 +
 7 files changed, 1442 insertions(+), 1 deletion(-)
 create mode 100644 projects/arradio/c5soc/soc_system.rbf
 create mode 100644 projects/arradio/c5soc/system_bd.tcl

diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index c29777bfa..fccd09735 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -34,6 +34,7 @@ M_FLIST += *.sta.*
 M_FLIST += *.qsf
 M_FLIST += *.qpf
 M_FLIST += *.qws
+M_FLIST += *.qsys
 M_FLIST += *.sof
 M_FLIST += *.cdf
 M_FLIST += *.sld
@@ -50,6 +51,7 @@ M_FLIST +=  *.jdi
 M_FLIST += *.pin
 M_FLIST += *_summary.csv
 M_FLIST += *.dpf
+M_FLIST += system_qsys_script.tcl
 
 
 
diff --git a/projects/arradio/c5soc/soc_system.rbf b/projects/arradio/c5soc/soc_system.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..60cf3e074e46d690def31d77ca464346fd382719
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HcmV?d00001

diff --git a/projects/arradio/c5soc/system_bd.tcl b/projects/arradio/c5soc/system_bd.tcl
new file mode 100644
index 000000000..a9b62774a
--- /dev/null
+++ b/projects/arradio/c5soc/system_bd.tcl
@@ -0,0 +1,1321 @@
+# qsys scripting (.tcl) file for system_bd
+package require -exact qsys 16.0
+
+create_system {system_bd}
+
+set_project_property DEVICE_FAMILY {Cyclone V}
+set_project_property DEVICE {5CSXFC6D6F31C8ES}
+set_project_property HIDE_FROM_IP_CATALOG {false}
+
+# Instances and instance parameters
+# (disabled instances are intentionally culled)
+add_instance axi_ad9361 axi_ad9361 1.0
+set_instance_parameter_value axi_ad9361 {ID} {0}
+set_instance_parameter_value axi_ad9361 {MODE_1R1T} {0}
+set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {1}
+set_instance_parameter_value axi_ad9361 {TDD_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {CMOS_OR_LVDS_N} {0}
+set_instance_parameter_value axi_ad9361 {ADC_DATAPATH_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {ADC_USERPORTS_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {ADC_DATAFORMAT_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {ADC_DCFILTER_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {ADC_IQCORRECTION_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {DAC_IODELAY_ENABLE} {0}
+set_instance_parameter_value axi_ad9361 {DAC_DATAPATH_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {DAC_DDS_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {DAC_USERPORTS_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {DAC_IQCORRECTION_DISABLE} {0}
+set_instance_parameter_value axi_ad9361 {IO_DELAY_GROUP} {dev_if_delay_group}
+
+add_instance axi_adc_dma axi_dmac 1.0
+set_instance_parameter_value axi_adc_dma {ID} {0}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
+set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
+set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
+set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
+
+add_instance axi_dac_dma axi_dmac 1.0
+set_instance_parameter_value axi_dac_dma {ID} {0}
+set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {64}
+set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {64}
+set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
+set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1}
+set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1}
+set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
+set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
+set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
+set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
+set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
+set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
+set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
+
+add_instance sys_clk clock_source 16.0
+set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
+set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
+
+add_instance sys_dma_clk clock_source 16.0
+set_instance_parameter_value sys_dma_clk {clockFrequency} {50000000.0}
+set_instance_parameter_value sys_dma_clk {clockFrequencyKnown} {1}
+set_instance_parameter_value sys_dma_clk {resetSynchronousEdges} {NONE}
+
+add_instance sys_gpio_bd altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_bd {bitClearingEdgeCapReg} {0}
+set_instance_parameter_value sys_gpio_bd {bitModifyingOutReg} {0}
+set_instance_parameter_value sys_gpio_bd {captureEdge} {0}
+set_instance_parameter_value sys_gpio_bd {direction} {InOut}
+set_instance_parameter_value sys_gpio_bd {edgeType} {RISING}
+set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_bd {irqType} {LEVEL}
+set_instance_parameter_value sys_gpio_bd {resetValue} {0.0}
+set_instance_parameter_value sys_gpio_bd {simDoTestBenchWiring} {0}
+set_instance_parameter_value sys_gpio_bd {simDrivenValue} {0.0}
+set_instance_parameter_value sys_gpio_bd {width} {32}
+
+add_instance sys_gpio_in altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_in {bitClearingEdgeCapReg} {0}
+set_instance_parameter_value sys_gpio_in {bitModifyingOutReg} {0}
+set_instance_parameter_value sys_gpio_in {captureEdge} {0}
+set_instance_parameter_value sys_gpio_in {direction} {Input}
+set_instance_parameter_value sys_gpio_in {edgeType} {RISING}
+set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
+set_instance_parameter_value sys_gpio_in {irqType} {LEVEL}
+set_instance_parameter_value sys_gpio_in {resetValue} {0.0}
+set_instance_parameter_value sys_gpio_in {simDoTestBenchWiring} {0}
+set_instance_parameter_value sys_gpio_in {simDrivenValue} {0.0}
+set_instance_parameter_value sys_gpio_in {width} {32}
+
+add_instance sys_gpio_out altera_avalon_pio 16.0
+set_instance_parameter_value sys_gpio_out {bitClearingEdgeCapReg} {0}
+set_instance_parameter_value sys_gpio_out {bitModifyingOutReg} {0}
+set_instance_parameter_value sys_gpio_out {captureEdge} {0}
+set_instance_parameter_value sys_gpio_out {direction} {Output}
+set_instance_parameter_value sys_gpio_out {edgeType} {RISING}
+set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
+set_instance_parameter_value sys_gpio_out {irqType} {LEVEL}
+set_instance_parameter_value sys_gpio_out {resetValue} {0.0}
+set_instance_parameter_value sys_gpio_out {simDoTestBenchWiring} {0}
+set_instance_parameter_value sys_gpio_out {simDrivenValue} {0.0}
+set_instance_parameter_value sys_gpio_out {width} {32}
+
+add_instance sys_hps altera_hps 16.0
+set_instance_parameter_value sys_hps {MEM_VENDOR} {JEDEC}
+set_instance_parameter_value sys_hps {MEM_FORMAT} {DISCRETE}
+set_instance_parameter_value sys_hps {RDIMM_CONFIG} {0000000000000000}
+set_instance_parameter_value sys_hps {LRDIMM_EXTENDED_CONFIG} {0x000000000000000000}
+set_instance_parameter_value sys_hps {DISCRETE_FLY_BY} {1}
+set_instance_parameter_value sys_hps {DEVICE_DEPTH} {1}
+set_instance_parameter_value sys_hps {MEM_MIRROR_ADDRESSING} {0}
+set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
+set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
+set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
+set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32}
+set_instance_parameter_value sys_hps {MEM_DQ_PER_DQS} {8}
+set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
+set_instance_parameter_value sys_hps {MEM_IF_DM_PINS_EN} {1}
+set_instance_parameter_value sys_hps {MEM_IF_DQSN_EN} {1}
+set_instance_parameter_value sys_hps {MEM_NUMBER_OF_DIMMS} {1}
+set_instance_parameter_value sys_hps {MEM_NUMBER_OF_RANKS_PER_DIMM} {1}
+set_instance_parameter_value sys_hps {MEM_NUMBER_OF_RANKS_PER_DEVICE} {1}
+set_instance_parameter_value sys_hps {MEM_RANK_MULTIPLICATION_FACTOR} {1}
+set_instance_parameter_value sys_hps {MEM_CK_WIDTH} {1}
+set_instance_parameter_value sys_hps {MEM_CS_WIDTH} {1}
+set_instance_parameter_value sys_hps {MEM_CLK_EN_WIDTH} {1}
+set_instance_parameter_value sys_hps {ALTMEMPHY_COMPATIBLE_MODE} {0}
+set_instance_parameter_value sys_hps {NEXTGEN} {1}
+set_instance_parameter_value sys_hps {MEM_IF_BOARD_BASE_DELAY} {10}
+set_instance_parameter_value sys_hps {MEM_IF_SIM_VALID_WINDOW} {0}
+set_instance_parameter_value sys_hps {MEM_GUARANTEED_WRITE_INIT} {0}
+set_instance_parameter_value sys_hps {MEM_VERBOSE} {1}
+set_instance_parameter_value sys_hps {PINGPONGPHY_EN} {0}
+set_instance_parameter_value sys_hps {DUPLICATE_AC} {0}
+set_instance_parameter_value sys_hps {REFRESH_BURST_VALIDATION} {0}
+set_instance_parameter_value sys_hps {AP_MODE_EN} {0}
+set_instance_parameter_value sys_hps {AP_MODE} {0}
+set_instance_parameter_value sys_hps {MEM_BL} {OTF}
+set_instance_parameter_value sys_hps {MEM_BT} {Sequential}
+set_instance_parameter_value sys_hps {MEM_ASR} {Manual}
+set_instance_parameter_value sys_hps {MEM_SRT} {Normal}
+set_instance_parameter_value sys_hps {MEM_PD} {DLL off}
+set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/7}
+set_instance_parameter_value sys_hps {MEM_DLL_EN} {1}
+set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
+set_instance_parameter_value sys_hps {MEM_RTT_WR} {RZQ/4}
+set_instance_parameter_value sys_hps {MEM_WTCL} {8}
+set_instance_parameter_value sys_hps {MEM_ATCL} {Disabled}
+set_instance_parameter_value sys_hps {MEM_TCL} {11}
+set_instance_parameter_value sys_hps {MEM_AUTO_LEVELING_MODE} {1}
+set_instance_parameter_value sys_hps {MEM_USER_LEVELING_MODE} {Leveling}
+set_instance_parameter_value sys_hps {MEM_INIT_EN} {0}
+set_instance_parameter_value sys_hps {MEM_INIT_FILE} {}
+set_instance_parameter_value sys_hps {DAT_DATA_WIDTH} {32}
+set_instance_parameter_value sys_hps {TIMING_TIS} {180}
+set_instance_parameter_value sys_hps {TIMING_TIH} {140}
+set_instance_parameter_value sys_hps {TIMING_TDS} {30}
+set_instance_parameter_value sys_hps {TIMING_TDH} {65}
+set_instance_parameter_value sys_hps {TIMING_TDQSQ} {125}
+set_instance_parameter_value sys_hps {TIMING_TQHS} {300}
+set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
+set_instance_parameter_value sys_hps {TIMING_TDQSCK} {255}
+set_instance_parameter_value sys_hps {TIMING_TDQSCKDS} {450}
+set_instance_parameter_value sys_hps {TIMING_TDQSCKDM} {900}
+set_instance_parameter_value sys_hps {TIMING_TDQSCKDL} {1200}
+set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25}
+set_instance_parameter_value sys_hps {TIMING_TDQSH} {0.35}
+set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
+set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2}
+set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2}
+set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
+set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
+set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
+set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
+set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
+set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
+set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
+set_instance_parameter_value sys_hps {CFG_TCCD_NS} {2.5}
+set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
+set_instance_parameter_value sys_hps {MEM_TWTR} {4}
+set_instance_parameter_value sys_hps {MEM_TFAW_NS} {30.0}
+set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5}
+set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
+set_instance_parameter_value sys_hps {POWER_OF_TWO_BUS} {0}
+set_instance_parameter_value sys_hps {SOPC_COMPAT_RESET} {0}
+set_instance_parameter_value sys_hps {AVL_MAX_SIZE} {4}
+set_instance_parameter_value sys_hps {BYTE_ENABLE} {1}
+set_instance_parameter_value sys_hps {ENABLE_CTRL_AVALON_INTERFACE} {1}
+set_instance_parameter_value sys_hps {CTL_DEEP_POWERDN_EN} {0}
+set_instance_parameter_value sys_hps {CTL_SELF_REFRESH_EN} {0}
+set_instance_parameter_value sys_hps {AUTO_POWERDN_EN} {0}
+set_instance_parameter_value sys_hps {AUTO_PD_CYCLES} {0}
+set_instance_parameter_value sys_hps {CTL_USR_REFRESH_EN} {0}
+set_instance_parameter_value sys_hps {CTL_AUTOPCH_EN} {0}
+set_instance_parameter_value sys_hps {CTL_ZQCAL_EN} {0}
+set_instance_parameter_value sys_hps {ADDR_ORDER} {0}
+set_instance_parameter_value sys_hps {CTL_LOOK_AHEAD_DEPTH} {4}
+set_instance_parameter_value sys_hps {CONTROLLER_LATENCY} {5}
+set_instance_parameter_value sys_hps {CFG_REORDER_DATA} {1}
+set_instance_parameter_value sys_hps {STARVE_LIMIT} {10}
+set_instance_parameter_value sys_hps {CTL_CSR_ENABLED} {0}
+set_instance_parameter_value sys_hps {CTL_CSR_CONNECTION} {INTERNAL_JTAG}
+set_instance_parameter_value sys_hps {CTL_ECC_ENABLED} {0}
+set_instance_parameter_value sys_hps {CTL_HRB_ENABLED} {0}
+set_instance_parameter_value sys_hps {CTL_ECC_AUTO_CORRECTION_ENABLED} {0}
+set_instance_parameter_value sys_hps {MULTICAST_EN} {0}
+set_instance_parameter_value sys_hps {CTL_DYNAMIC_BANK_ALLOCATION} {0}
+set_instance_parameter_value sys_hps {CTL_DYNAMIC_BANK_NUM} {4}
+set_instance_parameter_value sys_hps {DEBUG_MODE} {0}
+set_instance_parameter_value sys_hps {ENABLE_BURST_MERGE} {0}
+set_instance_parameter_value sys_hps {CTL_ENABLE_BURST_INTERRUPT} {0}
+set_instance_parameter_value sys_hps {CTL_ENABLE_BURST_TERMINATE} {0}
+set_instance_parameter_value sys_hps {LOCAL_ID_WIDTH} {8}
+set_instance_parameter_value sys_hps {WRBUFFER_ADDR_WIDTH} {6}
+set_instance_parameter_value sys_hps {MAX_PENDING_WR_CMD} {16}
+set_instance_parameter_value sys_hps {MAX_PENDING_RD_CMD} {32}
+set_instance_parameter_value sys_hps {USE_MM_ADAPTOR} {1}
+set_instance_parameter_value sys_hps {USE_AXI_ADAPTOR} {0}
+set_instance_parameter_value sys_hps {HCX_COMPAT_MODE} {0}
+set_instance_parameter_value sys_hps {CTL_CMD_QUEUE_DEPTH} {8}
+set_instance_parameter_value sys_hps {CTL_CSR_READ_ONLY} {1}
+set_instance_parameter_value sys_hps {CFG_DATA_REORDERING_TYPE} {INTER_BANK}
+set_instance_parameter_value sys_hps {NUM_OF_PORTS} {1}
+set_instance_parameter_value sys_hps {ENABLE_BONDING} {0}
+set_instance_parameter_value sys_hps {ENABLE_USER_ECC} {0}
+set_instance_parameter_value sys_hps {AVL_DATA_WIDTH_PORT} {32 32 32 32 32 32}
+set_instance_parameter_value sys_hps {PRIORITY_PORT} {1 1 1 1 1 1}
+set_instance_parameter_value sys_hps {WEIGHT_PORT} {0 0 0 0 0 0}
+set_instance_parameter_value sys_hps {CPORT_TYPE_PORT} {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional}
+set_instance_parameter_value sys_hps {ENABLE_EMIT_BFM_MASTER} {0}
+set_instance_parameter_value sys_hps {FORCE_SEQUENCER_TCL_DEBUG_MODE} {0}
+set_instance_parameter_value sys_hps {ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT} {0}
+set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
+set_instance_parameter_value sys_hps {REF_CLK_FREQ_PARAM_VALID} {0}
+set_instance_parameter_value sys_hps {REF_CLK_FREQ_MIN_PARAM} {0.0}
+set_instance_parameter_value sys_hps {REF_CLK_FREQ_MAX_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_DR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_DR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_DR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_DR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_DR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_MEM_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_MEM_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_MEM_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_MEM_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_MEM_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_AFI_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_AFI_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_AFI_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_NIOS_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_NIOS_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_NIOS_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_NIOS_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_NIOS_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_HR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_HR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_HR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_HR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_HR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_MULT_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_DIV_PARAM} {0}
+set_instance_parameter_value sys_hps {PLL_CLK_PARAM_VALID} {0}
+set_instance_parameter_value sys_hps {ENABLE_EXTRA_REPORTING} {0}
+set_instance_parameter_value sys_hps {NUM_EXTRA_REPORT_PATH} {10}
+set_instance_parameter_value sys_hps {ENABLE_ISS_PROBES} {0}
+set_instance_parameter_value sys_hps {CALIB_REG_WIDTH} {8}
+set_instance_parameter_value sys_hps {USE_SEQUENCER_BFM} {0}
+set_instance_parameter_value sys_hps {PLL_SHARING_MODE} {None}
+set_instance_parameter_value sys_hps {NUM_PLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value sys_hps {EXPORT_AFI_HALF_CLK} {0}
+set_instance_parameter_value sys_hps {ABSTRACT_REAL_COMPARE_TEST} {0}
+set_instance_parameter_value sys_hps {INCLUDE_BOARD_DELAY_MODEL} {0}
+set_instance_parameter_value sys_hps {INCLUDE_MULTIRANK_BOARD_DELAY_MODEL} {0}
+set_instance_parameter_value sys_hps {USE_FAKE_PHY} {0}
+set_instance_parameter_value sys_hps {FORCE_MAX_LATENCY_COUNT_WIDTH} {0}
+set_instance_parameter_value sys_hps {ENABLE_NON_DESTRUCTIVE_CALIB} {0}
+set_instance_parameter_value sys_hps {FIX_READ_LATENCY} {8}
+set_instance_parameter_value sys_hps {ENABLE_DELAY_CHAIN_WRITE} {0}
+set_instance_parameter_value sys_hps {TRACKING_ERROR_TEST} {0}
+set_instance_parameter_value sys_hps {TRACKING_WATCH_TEST} {0}
+set_instance_parameter_value sys_hps {MARGIN_VARIATION_TEST} {0}
+set_instance_parameter_value sys_hps {AC_ROM_USER_ADD_0} {0_0000_0000_0000}
+set_instance_parameter_value sys_hps {AC_ROM_USER_ADD_1} {0_0000_0000_1000}
+set_instance_parameter_value sys_hps {TREFI} {35100}
+set_instance_parameter_value sys_hps {REFRESH_INTERVAL} {15000}
+set_instance_parameter_value sys_hps {ENABLE_NON_DES_CAL_TEST} {0}
+set_instance_parameter_value sys_hps {TRFC} {350}
+set_instance_parameter_value sys_hps {ENABLE_NON_DES_CAL} {0}
+set_instance_parameter_value sys_hps {EXTRA_SETTINGS} {}
+set_instance_parameter_value sys_hps {MEM_DEVICE} {MISSING_MODEL}
+set_instance_parameter_value sys_hps {FORCE_SYNTHESIS_LANGUAGE} {}
+set_instance_parameter_value sys_hps {FORCED_NUM_WRITE_FR_CYCLE_SHIFTS} {0}
+set_instance_parameter_value sys_hps {SEQUENCER_TYPE} {NIOS}
+set_instance_parameter_value sys_hps {ADVERTIZE_SEQUENCER_SW_BUILD_FILES} {0}
+set_instance_parameter_value sys_hps {FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT} {0}
+set_instance_parameter_value sys_hps {PHY_ONLY} {0}
+set_instance_parameter_value sys_hps {SEQ_MODE} {0}
+set_instance_parameter_value sys_hps {ADVANCED_CK_PHASES} {0}
+set_instance_parameter_value sys_hps {COMMAND_PHASE} {0.0}
+set_instance_parameter_value sys_hps {MEM_CK_PHASE} {0.0}
+set_instance_parameter_value sys_hps {P2C_READ_CLOCK_ADD_PHASE} {0.0}
+set_instance_parameter_value sys_hps {C2P_WRITE_CLOCK_ADD_PHASE} {0.0}
+set_instance_parameter_value sys_hps {ACV_PHY_CLK_ADD_FR_PHASE} {0.0}
+set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3}
+set_instance_parameter_value sys_hps {PLL_LOCATION} {Top_Bottom}
+set_instance_parameter_value sys_hps {SKIP_MEM_INIT} {1}
+set_instance_parameter_value sys_hps {READ_DQ_DQS_CLOCK_SOURCE} {INVERTED_DQS_BUS}
+set_instance_parameter_value sys_hps {DQ_INPUT_REG_USE_CLKN} {0}
+set_instance_parameter_value sys_hps {DQS_DQSN_MODE} {DIFFERENTIAL}
+set_instance_parameter_value sys_hps {AFI_DEBUG_INFO_WIDTH} {32}
+set_instance_parameter_value sys_hps {CALIBRATION_MODE} {Skip}
+set_instance_parameter_value sys_hps {NIOS_ROM_DATA_WIDTH} {32}
+set_instance_parameter_value sys_hps {READ_FIFO_SIZE} {8}
+set_instance_parameter_value sys_hps {PHY_CSR_ENABLED} {0}
+set_instance_parameter_value sys_hps {PHY_CSR_CONNECTION} {INTERNAL_JTAG}
+set_instance_parameter_value sys_hps {USER_DEBUG_LEVEL} {1}
+set_instance_parameter_value sys_hps {TIMING_BOARD_DERATE_METHOD} {AUTO}
+set_instance_parameter_value sys_hps {TIMING_BOARD_CK_CKN_SLEW_RATE} {2.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SLEW_RATE} {1.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_DQS_DQSN_SLEW_RATE} {2.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_SLEW_RATE} {1.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_TIS} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_TIH} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_TDS} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_TDH} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_ISI_METHOD} {AUTO}
+set_instance_parameter_value sys_hps {TIMING_BOARD_AC_EYE_REDUCTION_SU} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_AC_EYE_REDUCTION_H} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_READ_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value sys_hps {PACKAGE_DESKEW} {0}
+set_instance_parameter_value sys_hps {AC_PACKAGE_DESKEW} {0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.03}
+set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.02}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {0.09}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.16}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DIMMS} {0.05}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.01}
+set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.08}
+set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
+set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.03}
+set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
+set_instance_parameter_value sys_hps {RATE} {Full}
+set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
+set_instance_parameter_value sys_hps {USE_MEM_CLK_FREQ} {0}
+set_instance_parameter_value sys_hps {FORCE_DQS_TRACKING} {AUTO}
+set_instance_parameter_value sys_hps {FORCE_SHADOW_REGS} {AUTO}
+set_instance_parameter_value sys_hps {MRS_MIRROR_PING_PONG_ATSO} {0}
+set_instance_parameter_value sys_hps {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID} {0}
+set_instance_parameter_value sys_hps {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM} {}
+set_instance_parameter_value sys_hps {DEVICE_FAMILY_PARAM} {}
+set_instance_parameter_value sys_hps {SPEED_GRADE} {7}
+set_instance_parameter_value sys_hps {IS_ES_DEVICE} {0}
+set_instance_parameter_value sys_hps {DISABLE_CHILD_MESSAGING} {0}
+set_instance_parameter_value sys_hps {HARD_EMIF} {1}
+set_instance_parameter_value sys_hps {HHP_HPS} {1}
+set_instance_parameter_value sys_hps {HHP_HPS_VERIFICATION} {0}
+set_instance_parameter_value sys_hps {HHP_HPS_SIMULATION} {0}
+set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
+set_instance_parameter_value sys_hps {CUT_NEW_FAMILY_TIMING} {1}
+set_instance_parameter_value sys_hps {ENABLE_EXPORT_SEQ_DEBUG_BRIDGE} {0}
+set_instance_parameter_value sys_hps {CORE_DEBUG_CONNECTION} {EXPORT}
+set_instance_parameter_value sys_hps {ADD_EXTERNAL_SEQ_DEBUG_NIOS} {0}
+set_instance_parameter_value sys_hps {ED_EXPORT_SEQ_DEBUG} {0}
+set_instance_parameter_value sys_hps {ADD_EFFICIENCY_MONITOR} {0}
+set_instance_parameter_value sys_hps {ENABLE_ABS_RAM_MEM_INIT} {0}
+set_instance_parameter_value sys_hps {ABS_RAM_MEM_INIT_FILENAME} {meminit}
+set_instance_parameter_value sys_hps {DLL_SHARING_MODE} {None}
+set_instance_parameter_value sys_hps {NUM_DLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value sys_hps {OCT_SHARING_MODE} {None}
+set_instance_parameter_value sys_hps {NUM_OCT_SHARING_INTERFACES} {1}
+set_instance_parameter_value sys_hps {show_advanced_parameters} {0}
+set_instance_parameter_value sys_hps {configure_advanced_parameters} {0}
+set_instance_parameter_value sys_hps {customize_device_pll_info} {0}
+set_instance_parameter_value sys_hps {device_pll_info_manual} {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}}
+set_instance_parameter_value sys_hps {show_debug_info_as_warning_msg} {0}
+set_instance_parameter_value sys_hps {show_warning_as_error_msg} {0}
+set_instance_parameter_value sys_hps {eosc1_clk_mhz} {25.0}
+set_instance_parameter_value sys_hps {eosc2_clk_mhz} {25.0}
+set_instance_parameter_value sys_hps {F2SCLK_SDRAMCLK_Enable} {0}
+set_instance_parameter_value sys_hps {F2SCLK_PERIPHCLK_Enable} {0}
+set_instance_parameter_value sys_hps {periph_pll_source} {0}
+set_instance_parameter_value sys_hps {sdmmc_clk_source} {2}
+set_instance_parameter_value sys_hps {nand_clk_source} {2}
+set_instance_parameter_value sys_hps {qspi_clk_source} {1}
+set_instance_parameter_value sys_hps {l4_mp_clk_source} {1}
+set_instance_parameter_value sys_hps {l4_sp_clk_source} {1}
+set_instance_parameter_value sys_hps {use_default_mpu_clk} {1}
+set_instance_parameter_value sys_hps {desired_mpu_clk_mhz} {800.0}
+set_instance_parameter_value sys_hps {l3_mp_clk_div} {1}
+set_instance_parameter_value sys_hps {l3_sp_clk_div} {1}
+set_instance_parameter_value sys_hps {dbctrl_stayosc1} {1}
+set_instance_parameter_value sys_hps {dbg_at_clk_div} {0}
+set_instance_parameter_value sys_hps {dbg_clk_div} {1}
+set_instance_parameter_value sys_hps {dbg_trace_clk_div} {0}
+set_instance_parameter_value sys_hps {desired_l4_mp_clk_mhz} {100.0}
+set_instance_parameter_value sys_hps {desired_l4_sp_clk_mhz} {100.0}
+set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
+set_instance_parameter_value sys_hps {desired_sdmmc_clk_mhz} {200.0}
+set_instance_parameter_value sys_hps {desired_nand_clk_mhz} {12.5}
+set_instance_parameter_value sys_hps {desired_qspi_clk_mhz} {400.0}
+set_instance_parameter_value sys_hps {desired_emac0_clk_mhz} {250.0}
+set_instance_parameter_value sys_hps {desired_emac1_clk_mhz} {250.0}
+set_instance_parameter_value sys_hps {desired_usb_mp_clk_mhz} {200.0}
+set_instance_parameter_value sys_hps {desired_spi_m_clk_mhz} {200.0}
+set_instance_parameter_value sys_hps {desired_can0_clk_mhz} {100.0}
+set_instance_parameter_value sys_hps {desired_can1_clk_mhz} {100.0}
+set_instance_parameter_value sys_hps {desired_gpio_db_clk_hz} {32000}
+set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
+set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_Enable} {0}
+set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
+set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
+set_instance_parameter_value sys_hps {S2FCLK_USER2CLK} {5}
+set_instance_parameter_value sys_hps {main_pll_m} {63}
+set_instance_parameter_value sys_hps {main_pll_n} {0}
+set_instance_parameter_value sys_hps {main_pll_c3} {3}
+set_instance_parameter_value sys_hps {main_pll_c4} {3}
+set_instance_parameter_value sys_hps {main_pll_c5} {15}
+set_instance_parameter_value sys_hps {periph_pll_m} {79}
+set_instance_parameter_value sys_hps {periph_pll_n} {1}
+set_instance_parameter_value sys_hps {periph_pll_c0} {3}
+set_instance_parameter_value sys_hps {periph_pll_c1} {3}
+set_instance_parameter_value sys_hps {periph_pll_c2} {1}
+set_instance_parameter_value sys_hps {periph_pll_c3} {19}
+set_instance_parameter_value sys_hps {periph_pll_c4} {4}
+set_instance_parameter_value sys_hps {periph_pll_c5} {9}
+set_instance_parameter_value sys_hps {usb_mp_clk_div} {0}
+set_instance_parameter_value sys_hps {spi_m_clk_div} {0}
+set_instance_parameter_value sys_hps {can0_clk_div} {1}
+set_instance_parameter_value sys_hps {can1_clk_div} {1}
+set_instance_parameter_value sys_hps {gpio_db_clk_div} {6249}
+set_instance_parameter_value sys_hps {l4_mp_clk_div} {1}
+set_instance_parameter_value sys_hps {l4_sp_clk_div} {1}
+set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value sys_hps {GP_Enable} {0}
+set_instance_parameter_value sys_hps {DEBUGAPB_Enable} {0}
+set_instance_parameter_value sys_hps {STM_Enable} {0}
+set_instance_parameter_value sys_hps {CTI_Enable} {0}
+set_instance_parameter_value sys_hps {TPIUFPGA_Enable} {0}
+set_instance_parameter_value sys_hps {TPIUFPGA_alt} {0}
+set_instance_parameter_value sys_hps {BOOTFROMFPGA_Enable} {0}
+set_instance_parameter_value sys_hps {TEST_Enable} {0}
+set_instance_parameter_value sys_hps {HLGPI_Enable} {0}
+set_instance_parameter_value sys_hps {BSEL_EN} {0}
+set_instance_parameter_value sys_hps {BSEL} {1}
+set_instance_parameter_value sys_hps {CSEL_EN} {0}
+set_instance_parameter_value sys_hps {CSEL} {0}
+set_instance_parameter_value sys_hps {F2S_Width} {2}
+set_instance_parameter_value sys_hps {S2F_Width} {2}
+set_instance_parameter_value sys_hps {LWH2F_Enable} {true}
+set_instance_parameter_value sys_hps {F2SDRAM_Type} {Avalon-MM\ Bidirectional AXI-3 AXI-3}
+set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 64 64}
+set_instance_parameter_value sys_hps {BONDING_OUT_ENABLED} {0}
+set_instance_parameter_value sys_hps {S2FCLK_COLDRST_Enable} {0}
+set_instance_parameter_value sys_hps {S2FCLK_PENDINGRST_Enable} {0}
+set_instance_parameter_value sys_hps {F2SCLK_DBGRST_Enable} {0}
+set_instance_parameter_value sys_hps {F2SCLK_WARMRST_Enable} {0}
+set_instance_parameter_value sys_hps {F2SCLK_COLDRST_Enable} {0}
+set_instance_parameter_value sys_hps {DMA_Enable} {No No No No No No No No}
+set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_CAN_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_CTI_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_DMA_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_EMAC_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_GPIO_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_I2CEMAC_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_I2CPERIPHERAL_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_L4TIMER_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_NAND_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_OSCTIMER_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_QSPI_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_SDMMC_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_SPIMASTER_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_SPISLAVE_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_UART_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_USB_Enable} {0}
+set_instance_parameter_value sys_hps {S2FINTERRUPT_WATCHDOG_Enable} {0}
+set_instance_parameter_value sys_hps {EMAC0_PTP} {0}
+set_instance_parameter_value sys_hps {EMAC1_PTP} {0}
+set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A}
+set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
+set_instance_parameter_value sys_hps {NAND_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {NAND_Mode} {N/A}
+set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
+set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
+set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {USB0_Mode} {N/A}
+set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
+set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {SPIM0_Mode} {N/A}
+set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select}
+set_instance_parameter_value sys_hps {SPIS0_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {SPIS0_Mode} {N/A}
+set_instance_parameter_value sys_hps {SPIS1_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {SPIS1_Mode} {N/A}
+set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
+set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
+set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
+set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
+set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
+set_instance_parameter_value sys_hps {I2C1_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {I2C1_Mode} {N/A}
+set_instance_parameter_value sys_hps {I2C2_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {I2C2_Mode} {N/A}
+set_instance_parameter_value sys_hps {I2C3_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {I2C3_Mode} {N/A}
+set_instance_parameter_value sys_hps {CAN0_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {CAN0_Mode} {N/A}
+set_instance_parameter_value sys_hps {CAN1_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {CAN1_Mode} {N/A}
+set_instance_parameter_value sys_hps {TRACE_PinMuxing} {Unused}
+set_instance_parameter_value sys_hps {TRACE_Mode} {N/A}
+set_instance_parameter_value sys_hps {GPIO_Enable} {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No}
+set_instance_parameter_value sys_hps {LOANIO_Enable} {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK} {2.5}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK} {125}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK} {2.5}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK} {125}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT} {100}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK} {100}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT} {100}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT} {100}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK} {100}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK} {100}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK} {100}
+set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK} {100}
+
+add_instance sys_id altera_avalon_sysid_qsys 16.0
+set_instance_parameter_value sys_id {id} {-1395322110}
+
+add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
+set_instance_parameter_value sys_int_mem {allowInSystemMemoryContentEditor} {0}
+set_instance_parameter_value sys_int_mem {blockType} {AUTO}
+set_instance_parameter_value sys_int_mem {dataWidth} {64}
+set_instance_parameter_value sys_int_mem {dataWidth2} {32}
+set_instance_parameter_value sys_int_mem {dualPort} {0}
+set_instance_parameter_value sys_int_mem {enableDiffWidth} {0}
+set_instance_parameter_value sys_int_mem {initMemContent} {0}
+set_instance_parameter_value sys_int_mem {initializationFileName} {onchip_mem.hex}
+set_instance_parameter_value sys_int_mem {instanceID} {NONE}
+set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
+set_instance_parameter_value sys_int_mem {readDuringWriteMode} {DONT_CARE}
+set_instance_parameter_value sys_int_mem {simAllowMRAMContentsFile} {0}
+set_instance_parameter_value sys_int_mem {simMemInitOnlyFilename} {0}
+set_instance_parameter_value sys_int_mem {singleClockOperation} {0}
+set_instance_parameter_value sys_int_mem {slave1Latency} {1}
+set_instance_parameter_value sys_int_mem {slave2Latency} {1}
+set_instance_parameter_value sys_int_mem {useNonDefaultInitFile} {0}
+set_instance_parameter_value sys_int_mem {copyInitFile} {0}
+set_instance_parameter_value sys_int_mem {useShallowMemBlocks} {0}
+set_instance_parameter_value sys_int_mem {writable} {1}
+set_instance_parameter_value sys_int_mem {ecc_enabled} {0}
+set_instance_parameter_value sys_int_mem {resetrequest_enabled} {1}
+
+add_instance sys_spi altera_avalon_spi 16.0
+set_instance_parameter_value sys_spi {clockPhase} {0}
+set_instance_parameter_value sys_spi {clockPolarity} {1}
+set_instance_parameter_value sys_spi {dataWidth} {8}
+set_instance_parameter_value sys_spi {disableAvalonFlowControl} {0}
+set_instance_parameter_value sys_spi {insertDelayBetweenSlaveSelectAndSClk} {0}
+set_instance_parameter_value sys_spi {insertSync} {0}
+set_instance_parameter_value sys_spi {lsbOrderedFirst} {0}
+set_instance_parameter_value sys_spi {masterSPI} {1}
+set_instance_parameter_value sys_spi {numberOfSlaves} {1}
+set_instance_parameter_value sys_spi {syncRegDepth} {2}
+set_instance_parameter_value sys_spi {targetClockRate} {50000000.0}
+set_instance_parameter_value sys_spi {targetSlaveSelectToSClkDelay} {0.0}
+
+add_instance util_adc_pack util_cpack 1.0
+set_instance_parameter_value util_adc_pack {CHANNEL_DATA_WIDTH} {16}
+set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
+
+add_instance util_adc_wfifo util_wfifo 1.0
+set_instance_parameter_value util_adc_wfifo {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value util_adc_wfifo {DIN_DATA_WIDTH} {16}
+set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
+set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
+
+add_instance util_dac_rfifo util_rfifo 1.0
+set_instance_parameter_value util_dac_rfifo {NUM_OF_CHANNELS} {4}
+set_instance_parameter_value util_dac_rfifo {DIN_DATA_WIDTH} {16}
+set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
+set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
+
+add_instance util_dac_upack util_upack 1.0
+set_instance_parameter_value util_dac_upack {CHANNEL_DATA_WIDTH} {16}
+set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
+
+add_instance vga_frame_reader alt_vip_vfr 14.0
+set_instance_parameter_value vga_frame_reader {BITS_PER_PIXEL_PER_COLOR_PLANE} {8}
+set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_PARALLEL} {4}
+set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_SEQUENCE} {1}
+set_instance_parameter_value vga_frame_reader {MAX_IMAGE_WIDTH} {1360}
+set_instance_parameter_value vga_frame_reader {MAX_IMAGE_HEIGHT} {768}
+set_instance_parameter_value vga_frame_reader {MEM_PORT_WIDTH} {128}
+set_instance_parameter_value vga_frame_reader {RMASTER_FIFO_DEPTH} {64}
+set_instance_parameter_value vga_frame_reader {RMASTER_BURST_TARGET} {32}
+set_instance_parameter_value vga_frame_reader {CLOCKS_ARE_SEPARATE} {1}
+
+add_instance vga_out_clock altera_clock_bridge 16.0
+set_instance_parameter_value vga_out_clock {EXPLICIT_CLOCK_RATE} {0.0}
+set_instance_parameter_value vga_out_clock {NUM_CLOCK_OUTPUTS} {1}
+
+add_instance vga_out_data alt_vip_itc 14.0
+set_instance_parameter_value vga_out_data {NUMBER_OF_COLOUR_PLANES} {4}
+set_instance_parameter_value vga_out_data {COLOUR_PLANES_ARE_IN_PARALLEL} {1}
+set_instance_parameter_value vga_out_data {BPS} {8}
+set_instance_parameter_value vga_out_data {INTERLACED} {0}
+set_instance_parameter_value vga_out_data {H_ACTIVE_PIXELS} {1360}
+set_instance_parameter_value vga_out_data {V_ACTIVE_LINES} {768}
+set_instance_parameter_value vga_out_data {ACCEPT_COLOURS_IN_SEQ} {0}
+set_instance_parameter_value vga_out_data {FIFO_DEPTH} {1920}
+set_instance_parameter_value vga_out_data {CLOCKS_ARE_SAME} {0}
+set_instance_parameter_value vga_out_data {USE_CONTROL} {0}
+set_instance_parameter_value vga_out_data {NO_OF_MODES} {1}
+set_instance_parameter_value vga_out_data {THRESHOLD} {1919}
+set_instance_parameter_value vga_out_data {STD_WIDTH} {1}
+set_instance_parameter_value vga_out_data {GENERATE_SYNC} {0}
+set_instance_parameter_value vga_out_data {USE_EMBEDDED_SYNCS} {0}
+set_instance_parameter_value vga_out_data {AP_LINE} {0}
+set_instance_parameter_value vga_out_data {V_BLANK} {0}
+set_instance_parameter_value vga_out_data {H_BLANK} {0}
+set_instance_parameter_value vga_out_data {H_SYNC_LENGTH} {112}
+set_instance_parameter_value vga_out_data {H_FRONT_PORCH} {64}
+set_instance_parameter_value vga_out_data {H_BACK_PORCH} {256}
+set_instance_parameter_value vga_out_data {V_SYNC_LENGTH} {6}
+set_instance_parameter_value vga_out_data {V_FRONT_PORCH} {3}
+set_instance_parameter_value vga_out_data {V_BACK_PORCH} {18}
+set_instance_parameter_value vga_out_data {F_RISING_EDGE} {0}
+set_instance_parameter_value vga_out_data {F_FALLING_EDGE} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_RISING_EDGE} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_BLANK} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_SYNC_LENGTH} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_FRONT_PORCH} {0}
+set_instance_parameter_value vga_out_data {FIELD0_V_BACK_PORCH} {0}
+set_instance_parameter_value vga_out_data {ANC_LINE} {0}
+set_instance_parameter_value vga_out_data {FIELD0_ANC_LINE} {0}
+
+add_instance vga_pll altera_pll 16.0
+set_instance_parameter_value vga_pll {debug_print_output} {0}
+set_instance_parameter_value vga_pll {debug_use_rbc_taf_method} {0}
+set_instance_parameter_value vga_pll {gui_device_speed_grade} {2}
+set_instance_parameter_value vga_pll {gui_pll_mode} {Integer-N PLL}
+set_instance_parameter_value vga_pll {gui_reference_clock_frequency} {50.0}
+set_instance_parameter_value vga_pll {gui_channel_spacing} {0.0}
+set_instance_parameter_value vga_pll {gui_operation_mode} {direct}
+set_instance_parameter_value vga_pll {gui_feedback_clock} {Global Clock}
+set_instance_parameter_value vga_pll {gui_fractional_cout} {32}
+set_instance_parameter_value vga_pll {gui_dsm_out_sel} {1st_order}
+set_instance_parameter_value vga_pll {gui_use_locked} {0}
+set_instance_parameter_value vga_pll {gui_en_adv_params} {0}
+set_instance_parameter_value vga_pll {gui_number_of_clocks} {2}
+set_instance_parameter_value vga_pll {gui_multiply_factor} {1}
+set_instance_parameter_value vga_pll {gui_frac_multiply_factor} {1.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_n} {1}
+set_instance_parameter_value vga_pll {gui_cascade_counter0} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency0} {85.5}
+set_instance_parameter_value vga_pll {gui_divide_factor_c0} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency0} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units0} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift0} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg0} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift0} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle0} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter1} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency1} {171.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c1} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency1} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units1} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift1} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg1} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift1} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle1} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter2} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency2} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c2} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency2} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units2} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift2} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg2} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift2} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle2} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter3} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency3} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c3} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency3} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units3} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift3} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg3} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift3} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle3} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter4} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency4} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c4} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency4} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units4} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift4} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg4} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift4} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle4} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter5} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency5} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c5} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency5} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units5} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift5} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg5} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift5} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle5} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter6} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency6} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c6} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency6} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units6} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift6} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg6} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift6} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle6} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter7} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency7} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c7} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency7} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units7} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift7} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg7} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift7} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle7} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter8} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency8} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c8} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency8} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units8} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift8} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg8} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift8} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle8} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter9} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency9} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c9} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency9} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units9} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift9} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg9} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift9} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle9} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter10} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency10} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c10} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency10} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units10} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift10} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg10} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift10} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle10} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter11} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency11} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c11} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency11} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units11} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift11} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg11} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift11} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle11} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter12} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency12} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c12} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency12} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units12} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift12} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg12} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift12} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle12} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter13} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency13} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c13} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency13} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units13} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift13} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg13} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift13} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle13} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter14} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency14} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c14} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency14} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units14} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift14} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg14} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift14} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle14} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter15} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency15} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c15} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency15} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units15} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift15} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg15} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift15} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle15} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter16} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency16} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c16} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency16} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units16} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift16} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg16} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift16} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle16} {50}
+set_instance_parameter_value vga_pll {gui_cascade_counter17} {0}
+set_instance_parameter_value vga_pll {gui_output_clock_frequency17} {100.0}
+set_instance_parameter_value vga_pll {gui_divide_factor_c17} {1}
+set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency17} {0 MHz}
+set_instance_parameter_value vga_pll {gui_ps_units17} {ps}
+set_instance_parameter_value vga_pll {gui_phase_shift17} {0}
+set_instance_parameter_value vga_pll {gui_phase_shift_deg17} {0.0}
+set_instance_parameter_value vga_pll {gui_actual_phase_shift17} {0}
+set_instance_parameter_value vga_pll {gui_duty_cycle17} {50}
+set_instance_parameter_value vga_pll {gui_pll_auto_reset} {Off}
+set_instance_parameter_value vga_pll {gui_pll_bandwidth_preset} {Auto}
+set_instance_parameter_value vga_pll {gui_en_reconf} {0}
+set_instance_parameter_value vga_pll {gui_en_dps_ports} {0}
+set_instance_parameter_value vga_pll {gui_en_phout_ports} {0}
+set_instance_parameter_value vga_pll {gui_phout_division} {1}
+set_instance_parameter_value vga_pll {gui_mif_generate} {0}
+set_instance_parameter_value vga_pll {gui_enable_mif_dps} {0}
+set_instance_parameter_value vga_pll {gui_dps_cntr} {C0}
+set_instance_parameter_value vga_pll {gui_dps_num} {1}
+set_instance_parameter_value vga_pll {gui_dps_dir} {Positive}
+set_instance_parameter_value vga_pll {gui_refclk_switch} {0}
+set_instance_parameter_value vga_pll {gui_refclk1_frequency} {100.0}
+set_instance_parameter_value vga_pll {gui_switchover_mode} {Automatic Switchover}
+set_instance_parameter_value vga_pll {gui_switchover_delay} {0}
+set_instance_parameter_value vga_pll {gui_active_clk} {0}
+set_instance_parameter_value vga_pll {gui_clk_bad} {0}
+set_instance_parameter_value vga_pll {gui_enable_cascade_out} {0}
+set_instance_parameter_value vga_pll {gui_cascade_outclk_index} {0}
+set_instance_parameter_value vga_pll {gui_enable_cascade_in} {0}
+set_instance_parameter_value vga_pll {gui_pll_cascading_mode} {Create an adjpllin signal to connect with an upstream PLL}
+
+# exported interfaces
+add_interface axi_ad9361_device_if conduit end
+set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
+add_interface axi_ad9361_up_enable conduit end
+set_interface_property axi_ad9361_up_enable EXPORT_OF axi_ad9361.if_up_enable
+add_interface axi_ad9361_up_txnrx conduit end
+set_interface_property axi_ad9361_up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
+add_interface sys_clk clock sink
+set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
+add_interface sys_gpio_bd conduit end
+set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
+add_interface sys_gpio_in conduit end
+set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
+add_interface sys_gpio_out conduit end
+set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
+add_interface sys_hps_h2f_reset reset source
+set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset
+add_interface sys_hps_hps_io conduit end
+set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io
+add_interface sys_hps_memory conduit end
+set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory
+add_interface sys_rst reset sink
+set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
+add_interface sys_spi conduit end
+set_interface_property sys_spi EXPORT_OF sys_spi.external
+add_interface vga_out_clk clock source
+set_interface_property vga_out_clk EXPORT_OF vga_out_clock.out_clk
+add_interface vga_out_data conduit end
+set_interface_property vga_out_data EXPORT_OF vga_out_data.clocked_video
+add_interface sys_hps_i2c0 conduit end
+set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
+add_interface sys_hps_i2c0_clk clock source
+set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
+add_interface sys_hps_i2c0_scl_in clock sink
+set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
+
+# connections and connection parameters
+add_connection vga_frame_reader.avalon_master sys_hps.f2h_sdram0_data
+set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data arbitrationPriority {1}
+set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data baseAddress {0x0000}
+set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data defaultConnection {0}
+
+add_connection sys_hps.h2f_axi_master sys_int_mem.s1
+set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000}
+set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master vga_frame_reader.avalon_slave
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/vga_frame_reader.avalon_slave arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/vga_frame_reader.avalon_slave baseAddress {0x9000}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/vga_frame_reader.avalon_slave defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master sys_id.control_slave
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_id.control_slave arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_id.control_slave baseAddress {0x00010000}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_id.control_slave defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master sys_gpio_bd.s1
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_bd.s1 arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_bd.s1 baseAddress {0x00010080}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_bd.s1 defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master sys_gpio_in.s1
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_in.s1 arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_in.s1 baseAddress {0x00010100}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_in.s1 defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master sys_gpio_out.s1
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_out.s1 arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_out.s1 baseAddress {0x00109000}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_out.s1 defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master axi_ad9361.s_axi
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_ad9361.s_axi arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_ad9361.s_axi baseAddress {0x00120000}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_ad9361.s_axi defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master axi_adc_dma.s_axi
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_adc_dma.s_axi arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_adc_dma.s_axi baseAddress {0x00100000}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_adc_dma.s_axi defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master axi_dac_dma.s_axi
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_dac_dma.s_axi arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_dac_dma.s_axi baseAddress {0x00104000}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_dac_dma.s_axi defaultConnection {0}
+
+add_connection sys_hps.h2f_lw_axi_master sys_spi.spi_control_port
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_spi.spi_control_port arbitrationPriority {1}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_spi.spi_control_port baseAddress {0x00108000}
+set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_spi.spi_control_port defaultConnection {0}
+
+add_connection axi_adc_dma.m_dest_axi sys_hps.f2h_sdram2_data
+set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_hps.f2h_sdram2_data arbitrationPriority {1}
+set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_hps.f2h_sdram2_data baseAddress {0x0000}
+set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_hps.f2h_sdram2_data defaultConnection {0}
+
+add_connection axi_dac_dma.m_src_axi sys_hps.f2h_sdram1_data
+set_connection_parameter_value axi_dac_dma.m_src_axi/sys_hps.f2h_sdram1_data arbitrationPriority {1}
+set_connection_parameter_value axi_dac_dma.m_src_axi/sys_hps.f2h_sdram1_data baseAddress {0x0000}
+set_connection_parameter_value axi_dac_dma.m_src_axi/sys_hps.f2h_sdram1_data defaultConnection {0}
+
+add_connection vga_frame_reader.avalon_streaming_source vga_out_data.din
+
+add_connection sys_clk.clk sys_id.clk
+
+add_connection sys_clk.clk sys_gpio_bd.clk
+
+add_connection sys_clk.clk sys_gpio_in.clk
+
+add_connection sys_clk.clk sys_gpio_out.clk
+
+add_connection sys_clk.clk sys_spi.clk
+
+add_connection sys_clk.clk sys_int_mem.clk1
+
+add_connection sys_clk.clk vga_frame_reader.clock_master
+
+add_connection sys_clk.clk sys_hps.f2h_axi_clock
+
+add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
+
+add_connection sys_dma_clk.clk sys_hps.f2h_sdram1_clock
+
+add_connection sys_dma_clk.clk sys_hps.f2h_sdram2_clock
+
+add_connection sys_clk.clk sys_hps.h2f_axi_clock
+
+add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
+
+add_connection sys_dma_clk.clk util_adc_pack.if_adc_clk
+
+add_connection sys_dma_clk.clk util_dac_upack.if_dac_clk
+
+add_connection sys_clk.clk axi_ad9361.if_delay_clk
+
+add_connection sys_dma_clk.clk util_dac_rfifo.if_din_clk
+
+add_connection sys_dma_clk.clk util_adc_wfifo.if_dout_clk
+
+add_connection sys_dma_clk.clk axi_dac_dma.if_fifo_rd_clk
+
+add_connection sys_dma_clk.clk axi_adc_dma.if_fifo_wr_clk
+
+add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
+
+add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
+
+add_connection sys_clk.clk vga_pll.refclk
+
+add_connection sys_clk.clk axi_ad9361.s_axi_clock
+
+add_connection sys_clk.clk axi_adc_dma.s_axi_clock
+
+add_connection sys_clk.clk axi_dac_dma.s_axi_clock
+
+add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
+
+add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk
+
+add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
+
+add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
+
+add_connection vga_pll.outclk0 vga_frame_reader.clock_reset
+
+add_connection vga_pll.outclk0 vga_out_clock.in_clk
+
+add_connection vga_pll.outclk0 vga_out_data.is_clk_rst
+
+add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
+set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 endPort {}
+set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 endPortLSB {0}
+set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 startPort {}
+set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 startPortLSB {0}
+set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 width {0}
+
+add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
+set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 endPort {}
+set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 endPortLSB {0}
+set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 startPort {}
+set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 startPortLSB {0}
+set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 width {0}
+
+add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
+set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 endPort {}
+set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 endPortLSB {0}
+set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 startPort {}
+set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 startPortLSB {0}
+set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 width {0}
+
+add_connection axi_ad9361.adc_ch_3 util_adc_wfifo.din_3
+set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 endPort {}
+set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 endPortLSB {0}
+set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 startPort {}
+set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 startPortLSB {0}
+set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 width {0}
+
+add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
+set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 endPort {}
+set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 endPortLSB {0}
+set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 startPort {}
+set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 startPortLSB {0}
+set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 width {0}
+
+add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
+set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 endPort {}
+set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 endPortLSB {0}
+set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 startPort {}
+set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 startPortLSB {0}
+set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 width {0}
+
+add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
+set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 endPort {}
+set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 endPortLSB {0}
+set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 startPort {}
+set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 startPortLSB {0}
+set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 width {0}
+
+add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
+set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 endPort {}
+set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 endPortLSB {0}
+set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 startPort {}
+set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 startPortLSB {0}
+set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 width {0}
+
+add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
+set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 endPort {}
+set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 endPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 startPort {}
+set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 startPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 width {0}
+
+add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
+set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 endPort {}
+set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 endPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 startPort {}
+set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 startPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 width {0}
+
+add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
+set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 endPort {}
+set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 endPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 startPort {}
+set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 startPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 width {0}
+
+add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
+set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 endPort {}
+set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 endPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 startPort {}
+set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 startPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 width {0}
+
+add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
+set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 endPort {}
+set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 endPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 startPort {}
+set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 startPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 width {0}
+
+add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
+set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 endPort {}
+set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 endPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 startPort {}
+set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 startPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 width {0}
+
+add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
+set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 endPort {}
+set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 endPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 startPort {}
+set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 startPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 width {0}
+
+add_connection util_dac_rfifo.dout_3 axi_ad9361.dac_ch_3
+set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 endPort {}
+set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 endPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 startPort {}
+set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 startPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 width {0}
+
+add_connection util_adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
+set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din endPort {}
+set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din endPortLSB {0}
+set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din startPort {}
+set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din startPortLSB {0}
+set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din width {0}
+
+add_connection util_adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
+set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync endPort {}
+set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync endPortLSB {0}
+set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync startPort {}
+set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync startPortLSB {0}
+set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync width {0}
+
+add_connection util_adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
+set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en endPort {}
+set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en endPortLSB {0}
+set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en startPort {}
+set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en startPortLSB {0}
+set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en width {0}
+
+add_connection util_dac_upack.if_dac_valid axi_dac_dma.if_fifo_rd_en
+set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en endPort {}
+set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en endPortLSB {0}
+set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en startPort {}
+set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en startPortLSB {0}
+set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en width {0}
+
+add_connection util_adc_wfifo.if_din_ovf axi_ad9361.if_adc_dovf
+set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf endPort {}
+set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf endPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf startPort {}
+set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf startPortLSB {0}
+set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf width {0}
+
+add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
+set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf endPort {}
+set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf endPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf startPort {}
+set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf startPortLSB {0}
+set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf width {0}
+
+add_connection axi_dac_dma.if_fifo_rd_dout util_dac_upack.if_dac_data
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data endPort {}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data endPortLSB {0}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data startPort {}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data startPortLSB {0}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data width {0}
+
+add_connection axi_dac_dma.if_fifo_rd_underflow util_dac_rfifo.if_din_unf
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf endPort {}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf endPortLSB {0}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf startPort {}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf startPortLSB {0}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf width {0}
+
+add_connection axi_dac_dma.if_fifo_rd_xfer_req util_dac_upack.if_dma_xfer_in
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in endPort {}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in endPortLSB {0}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in startPort {}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in startPortLSB {0}
+set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in width {0}
+
+add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_wfifo.if_dout_ovf
+set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf endPort {}
+set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf endPortLSB {0}
+set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf startPort {}
+set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf startPortLSB {0}
+set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf width {0}
+
+add_connection sys_hps.f2h_irq0 vga_frame_reader.interrupt_sender
+set_connection_parameter_value sys_hps.f2h_irq0/vga_frame_reader.interrupt_sender irqNumber {4}
+
+add_connection sys_hps.f2h_irq0 axi_adc_dma.interrupt_sender
+set_connection_parameter_value sys_hps.f2h_irq0/axi_adc_dma.interrupt_sender irqNumber {2}
+
+add_connection sys_hps.f2h_irq0 axi_dac_dma.interrupt_sender
+set_connection_parameter_value sys_hps.f2h_irq0/axi_dac_dma.interrupt_sender irqNumber {3}
+
+add_connection sys_hps.f2h_irq0 sys_gpio_bd.irq
+set_connection_parameter_value sys_hps.f2h_irq0/sys_gpio_bd.irq irqNumber {0}
+
+add_connection sys_hps.f2h_irq0 sys_spi.irq
+set_connection_parameter_value sys_hps.f2h_irq0/sys_spi.irq irqNumber {1}
+
+add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
+
+add_connection sys_clk.clk_reset vga_frame_reader.clock_master_reset
+
+add_connection sys_clk.clk_reset vga_frame_reader.clock_reset_reset
+
+add_connection sys_dma_clk.clk_reset util_adc_pack.if_adc_rst
+
+add_connection sys_dma_clk.clk_reset util_dac_rfifo.if_din_rstn
+
+add_connection sys_dma_clk.clk_reset util_adc_wfifo.if_dout_rstn
+
+add_connection sys_clk.clk_reset vga_out_data.is_clk_rst_reset
+
+add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
+
+add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
+
+add_connection sys_clk.clk_reset vga_pll.reset
+
+add_connection sys_clk.clk_reset sys_id.reset
+
+add_connection sys_clk.clk_reset sys_gpio_bd.reset
+
+add_connection sys_clk.clk_reset sys_gpio_in.reset
+
+add_connection sys_clk.clk_reset sys_gpio_out.reset
+
+add_connection sys_clk.clk_reset sys_spi.reset
+
+add_connection sys_clk.clk_reset sys_int_mem.reset1
+
+add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
+
+add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
+
+add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
+
+add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
+
+add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
+
+# interconnect requirements
+set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {FIFO}
+set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {2}
+
+save_system {system_bd.qsys}
diff --git a/projects/arradio/c5soc/system_project.tcl b/projects/arradio/c5soc/system_project.tcl
index 70c4b16bd..2c23d8a4c 100644
--- a/projects/arradio/c5soc/system_project.tcl
+++ b/projects/arradio/c5soc/system_project.tcl
@@ -91,6 +91,18 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_mosi
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_miso
 
+set_location_assignment PIN_F15 -to scl
+set_location_assignment PIN_G13 -to sda
+set_location_assignment PIN_C7  -to ga0
+set_location_assignment PIN_H14 -to ga1
+set_instance_assignment -name IO_STANDARD "2.5 V" -to scl
+set_instance_assignment -name IO_STANDARD "2.5 V" -to sda
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ga0
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ga1
+
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to scl
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sda
+
 set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity axi_ad9361
 
 execute_flow -compile
diff --git a/projects/arradio/c5soc/system_top.v b/projects/arradio/c5soc/system_top.v
index 8a9956ae5..78d6cc07e 100644
--- a/projects/arradio/c5soc/system_top.v
+++ b/projects/arradio/c5soc/system_top.v
@@ -100,6 +100,13 @@ module system_top (
   output            spim1_mosi,
   input             spim1_miso,
 
+  // iic interface
+
+  inout             scl,
+  inout             sda,
+  output            ga0,
+  output            ga1,
+
   // hps-uart
 
   input             uart0_rx,
@@ -153,6 +160,11 @@ module system_top (
   wire    [ 31:0]   sys_gpio_i;
   wire    [ 31:0]   sys_gpio_o;
 
+  wire              i2c0_out_data;
+  wire              i2c0_sda;
+  wire              i2c0_out_clk;
+  wire              i2c0_scl_in_clk;
+
   // defaults
 
   assign vga_blank_n = 1'b1;
@@ -166,6 +178,11 @@ module system_top (
   assign ad9361_resetb = sys_gpio_o[4];
   assign ad9361_en_agc = sys_gpio_o[3];
   assign ad9361_sync = sys_gpio_o[2];
+  assign ga0 = 1'b0;
+  assign ga1 = 1'b0;
+
+ ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl));
+ ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda));
 
   // instantiations
 
@@ -236,6 +253,10 @@ module system_top (
     .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
     .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
     .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
+    .sys_hps_i2c0_out_data(i2c0_out_data),
+    .sys_hps_i2c0_sda(i2c0_sda),
+    .sys_hps_i2c0_clk_clk(i2c0_out_clk),
+    .sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk),
     .sys_hps_memory_mem_a (ddr3_a),
     .sys_hps_memory_mem_ba (ddr3_ba),
     .sys_hps_memory_mem_ck (ddr3_ck_p),
@@ -266,7 +287,9 @@ module system_top (
     .vga_out_data_vid_h_sync (vga_hsync),
     .vga_out_data_vid_f (),
     .vga_out_data_vid_h (),
-    .vga_out_data_vid_v ());
+    .vga_out_data_vid_v (),
+    .vga_if_vid_v ()
+	 );
 
 endmodule
 
diff --git a/projects/common/c5soc/c5soc_system_assign.tcl b/projects/common/c5soc/c5soc_system_assign.tcl
index dc7d69968..6ed0afc1d 100755
--- a/projects/common/c5soc/c5soc_system_assign.tcl
+++ b/projects/common/c5soc/c5soc_system_assign.tcl
@@ -444,6 +444,81 @@ set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_we_n
 set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst
 set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|pll0|fbout
 
+# ddr3 pin locations (quartus critical warnings)
+
+set_location_assignment PIN_F26   -to ddr3_a[0]
+set_location_assignment PIN_G30   -to ddr3_a[1]
+set_location_assignment PIN_F28   -to ddr3_a[2]
+set_location_assignment PIN_F30   -to ddr3_a[3]
+set_location_assignment PIN_J25   -to ddr3_a[4]
+set_location_assignment PIN_J27   -to ddr3_a[5]
+set_location_assignment PIN_F29   -to ddr3_a[6]
+set_location_assignment PIN_E28   -to ddr3_a[7]
+set_location_assignment PIN_H27   -to ddr3_a[8]
+set_location_assignment PIN_G26   -to ddr3_a[9]
+set_location_assignment PIN_D29   -to ddr3_a[10]
+set_location_assignment PIN_C30   -to ddr3_a[11]
+set_location_assignment PIN_B30   -to ddr3_a[12]
+set_location_assignment PIN_C29   -to ddr3_a[13]
+set_location_assignment PIN_H25   -to ddr3_a[14]
+set_location_assignment PIN_E29   -to ddr3_ba[0]
+set_location_assignment PIN_J24   -to ddr3_ba[1]
+set_location_assignment PIN_J23   -to ddr3_ba[2]
+set_location_assignment PIN_E27   -to ddr3_cas_n
+set_location_assignment PIN_M23   -to ddr3_ck_p
+set_location_assignment PIN_L23   -to ddr3_ck_n
+set_location_assignment PIN_L29   -to ddr3_cke
+set_location_assignment PIN_H24   -to ddr3_cs_n
+set_location_assignment PIN_K28   -to ddr3_dm[0]
+set_location_assignment PIN_M28   -to ddr3_dm[1]
+set_location_assignment PIN_R28   -to ddr3_dm[2]
+set_location_assignment PIN_W30   -to ddr3_dm[3]
+set_location_assignment PIN_K23   -to ddr3_dq[0]
+set_location_assignment PIN_K22   -to ddr3_dq[1]
+set_location_assignment PIN_H30   -to ddr3_dq[2]
+set_location_assignment PIN_G28   -to ddr3_dq[3]
+set_location_assignment PIN_L25   -to ddr3_dq[4]
+set_location_assignment PIN_L24   -to ddr3_dq[5]
+set_location_assignment PIN_J30   -to ddr3_dq[6]
+set_location_assignment PIN_J29   -to ddr3_dq[7]
+set_location_assignment PIN_K26   -to ddr3_dq[8]
+set_location_assignment PIN_L26   -to ddr3_dq[9]
+set_location_assignment PIN_K29   -to ddr3_dq[10]
+set_location_assignment PIN_K27   -to ddr3_dq[11]
+set_location_assignment PIN_M26   -to ddr3_dq[12]
+set_location_assignment PIN_M27   -to ddr3_dq[13]
+set_location_assignment PIN_L28   -to ddr3_dq[14]
+set_location_assignment PIN_M30   -to ddr3_dq[15]
+set_location_assignment PIN_U26   -to ddr3_dq[16]
+set_location_assignment PIN_T26   -to ddr3_dq[17]
+set_location_assignment PIN_N29   -to ddr3_dq[18]
+set_location_assignment PIN_N28   -to ddr3_dq[19]
+set_location_assignment PIN_P26   -to ddr3_dq[20]
+set_location_assignment PIN_P27   -to ddr3_dq[21]
+set_location_assignment PIN_N27   -to ddr3_dq[22]
+set_location_assignment PIN_R29   -to ddr3_dq[23]
+set_location_assignment PIN_P24   -to ddr3_dq[24]
+set_location_assignment PIN_P25   -to ddr3_dq[25]
+set_location_assignment PIN_T29   -to ddr3_dq[26]
+set_location_assignment PIN_T28   -to ddr3_dq[27]
+set_location_assignment PIN_R27   -to ddr3_dq[28]
+set_location_assignment PIN_R26   -to ddr3_dq[29]
+set_location_assignment PIN_V30   -to ddr3_dq[30]
+set_location_assignment PIN_W29   -to ddr3_dq[31]
+set_location_assignment PIN_N18   -to ddr3_dqs_p[0]
+set_location_assignment PIN_M19   -to ddr3_dqs_n[0]
+set_location_assignment PIN_N25   -to ddr3_dqs_p[1]
+set_location_assignment PIN_N24   -to ddr3_dqs_n[1]
+set_location_assignment PIN_R19   -to ddr3_dqs_p[2]
+set_location_assignment PIN_R18   -to ddr3_dqs_n[2]
+set_location_assignment PIN_R22   -to ddr3_dqs_p[3]
+set_location_assignment PIN_R21   -to ddr3_dqs_n[3]
+set_location_assignment PIN_H28   -to ddr3_odt
+set_location_assignment PIN_D30   -to ddr3_ras_n
+set_location_assignment PIN_P30   -to ddr3_reset_n
+set_location_assignment PIN_C28   -to ddr3_we_n
+set_location_assignment PIN_D27   -to ddr3_rzq
+
 # globals
 
 set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
diff --git a/projects/common/c5soc/c5soc_system_qsys.tcl b/projects/common/c5soc/c5soc_system_qsys.tcl
index 63349c195..47f47fa36 100755
--- a/projects/common/c5soc/c5soc_system_qsys.tcl
+++ b/projects/common/c5soc/c5soc_system_qsys.tcl
@@ -43,6 +43,8 @@ set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
 set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
 set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
 set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
+set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
+set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
 set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
 set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
 set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
@@ -104,6 +106,12 @@ add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
 add_connection sys_clk.clk sys_hps.h2f_axi_clock
 add_connection sys_clk.clk sys_hps.f2h_axi_clock
 add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
+add_interface sys_hps_i2c0 conduit end
+set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
+add_interface sys_hps_i2c0_clk clock source
+set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
+add_interface sys_hps_i2c0_scl_in clock sink
+set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
 
 # cpu/hps handling
 

From 8e2237b7ef810c67938cfd72f1f07c89dc0748fd Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri, 23 Jun 2017 17:46:25 +0300
Subject: [PATCH 965/972] arradio: remove binary file

---
 projects/arradio/c5soc/soc_system.rbf | Bin 7007204 -> 0 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 projects/arradio/c5soc/soc_system.rbf

diff --git a/projects/arradio/c5soc/soc_system.rbf b/projects/arradio/c5soc/soc_system.rbf
deleted file mode 100644
index 60cf3e074e46d690def31d77ca464346fd382719..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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From 0761bc4f79874dd8ae93d384e0fd56c910c74bdb Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 20 Jun 2017 11:58:59 +0100
Subject: [PATCH 966/972] adrv9371_alt: Delete the fifos from the RX path

  + Delete the rx_fifo and rx_os_fifo from the RX datapath
  + Change the receive DMA's source interface type to wr_fifo
---
 projects/adrv9371x/common/adrv9371x_qsys.tcl | 51 +++++---------------
 1 file changed, 12 insertions(+), 39 deletions(-)

diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index c3e1428ec..ebbf33fb2 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -177,31 +177,6 @@ add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_cpack.if_adc_clk
 add_connection axi_ad9371.adc_os_ch_0 axi_ad9371_rx_os_cpack.adc_ch_0
 add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1
 
-# dac & adc fifos
-
-add_instance axi_ad9371_rx_fifo util_adcfifo 1.0
-set_instance_parameter_value axi_ad9371_rx_fifo {ADC_DATA_WIDTH} {64}
-set_instance_parameter_value axi_ad9371_rx_fifo {DMA_DATA_WIDTH} {64}
-set_instance_parameter_value axi_ad9371_rx_fifo {DMA_READY_ENABLE} {1}
-set_instance_parameter_value axi_ad9371_rx_fifo {DMA_ADDRESS_WIDTH} {16}
-add_connection sys_clk.clk_reset axi_ad9371_rx_fifo.if_adc_rst
-add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_fifo.if_adc_clk
-add_connection axi_ad9371_rx_cpack.if_adc_valid axi_ad9371_rx_fifo.if_adc_wr
-add_connection axi_ad9371_rx_cpack.if_adc_data axi_ad9371_rx_fifo.if_adc_wdata
-add_connection axi_ad9371_rx_fifo.if_adc_wovf axi_ad9371.if_adc_dovf
-
-add_instance axi_ad9371_rx_os_fifo util_adcfifo 1.0
-set_instance_parameter_value axi_ad9371_rx_os_fifo {ADC_DATA_WIDTH} {64}
-set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_DATA_WIDTH} {64}
-set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_READY_ENABLE} {1}
-set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_ADDRESS_WIDTH} {16}
-
-add_connection sys_clk.clk_reset axi_ad9371_rx_os_fifo.if_adc_rst
-add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_fifo.if_adc_clk
-add_connection axi_ad9371_rx_os_cpack.if_adc_valid axi_ad9371_rx_os_fifo.if_adc_wr
-add_connection axi_ad9371_rx_os_cpack.if_adc_data axi_ad9371_rx_os_fifo.if_adc_wdata
-add_connection axi_ad9371_rx_os_fifo.if_adc_wovf axi_ad9371.if_adc_dovf
-
 # dac & adc dma
 
 add_instance axi_ad9371_tx_dma axi_dmac 1.0
@@ -243,14 +218,13 @@ set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_SRC} {0}
 set_instance_parameter_value axi_ad9371_rx_dma {SYNC_TRANSFER_START} {0}
 set_instance_parameter_value axi_ad9371_rx_dma {CYCLIC} {0}
 set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_SRC} {1}
+set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_SRC} {2}
 set_instance_parameter_value axi_ad9371_rx_dma {FIFO_SIZE} {16}
-add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_fifo.if_dma_clk
-add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_dma.if_s_axis_aclk
-add_connection axi_ad9371_rx_fifo.if_dma_wr axi_ad9371_rx_dma.if_s_axis_valid
-add_connection axi_ad9371_rx_fifo.if_dma_wdata axi_ad9371_rx_dma.if_s_axis_data
-add_connection axi_ad9371_rx_dma.if_s_axis_ready axi_ad9371_rx_fifo.if_dma_wready
-add_connection axi_ad9371_rx_dma.if_s_axis_xfer_req axi_ad9371_rx_fifo.if_dma_xfer_req
+add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_dma.if_fifo_wr_clk
+add_connection axi_ad9371_rx_cpack.if_adc_valid axi_ad9371_rx_dma.if_fifo_wr_en
+add_connection axi_ad9371_rx_cpack.if_adc_sync axi_ad9371_rx_dma.if_fifo_wr_sync
+add_connection axi_ad9371_rx_cpack.if_adc_data axi_ad9371_rx_dma.if_fifo_wr_din
+add_connection axi_ad9371_rx_dma.if_fifo_wr_overflow axi_ad9371.if_adc_dovf
 add_connection sys_clk.clk axi_ad9371_rx_dma.s_axi_clock
 add_connection sys_clk.clk_reset axi_ad9371_rx_dma.s_axi_reset
 add_connection sys_dma_clk.clk axi_ad9371_rx_dma.m_dest_axi_clock
@@ -270,14 +244,13 @@ set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_SRC} {0}
 set_instance_parameter_value axi_ad9371_rx_os_dma {SYNC_TRANSFER_START} {0}
 set_instance_parameter_value axi_ad9371_rx_os_dma {CYCLIC} {0}
 set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_SRC} {1}
+set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_SRC} {2}
 set_instance_parameter_value axi_ad9371_rx_os_dma {FIFO_SIZE} {16}
-add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_fifo.if_dma_clk
-add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_dma.if_s_axis_aclk
-add_connection axi_ad9371_rx_os_fifo.if_dma_wr axi_ad9371_rx_os_dma.if_s_axis_valid
-add_connection axi_ad9371_rx_os_fifo.if_dma_wdata axi_ad9371_rx_os_dma.if_s_axis_data
-add_connection axi_ad9371_rx_os_dma.if_s_axis_ready axi_ad9371_rx_os_fifo.if_dma_wready
-add_connection axi_ad9371_rx_os_dma.if_s_axis_xfer_req axi_ad9371_rx_os_fifo.if_dma_xfer_req
+add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_dma.if_fifo_wr_clk
+add_connection axi_ad9371_rx_os_cpack.if_adc_valid axi_ad9371_rx_os_dma.if_fifo_wr_en
+add_connection axi_ad9371_rx_os_cpack.if_adc_sync axi_ad9371_rx_os_dma.if_fifo_wr_sync
+add_connection axi_ad9371_rx_os_cpack.if_adc_data axi_ad9371_rx_os_dma.if_fifo_wr_din
+add_connection axi_ad9371_rx_os_dma.if_fifo_wr_overflow axi_ad9371.if_adc_os_dovf
 add_connection sys_clk.clk axi_ad9371_rx_os_dma.s_axi_clock
 add_connection sys_clk.clk_reset axi_ad9371_rx_os_dma.s_axi_reset
 add_connection sys_dma_clk.clk axi_ad9371_rx_os_dma.m_dest_axi_clock

From cd29807edc52f3fe88d60257c70831a9da1bb1f3 Mon Sep 17 00:00:00 2001
From: Andrei Grozav <andrei.grozav@analog.com>
Date: Thu, 29 Jun 2017 09:25:04 +0100
Subject: [PATCH 967/972] Revert "altera/ad_serdes: Fix net alignment for
 rx_out at ad_serdes_in"

This reverts commit 0715c962f199c3200327ff80f32d2f3b3fe4d79f.
---
 library/altera/common/ad_serdes_in.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index 4a99de8ff..9b147d698 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -127,7 +127,7 @@ module __ad_serdes_in__ #(
   generate
   for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
     for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
-      assign data_samples_s[i][n] = data_out_s[n][i];
+      assign data_samples_s[i][n] = data_out_s[n][((SERDES_FACTOR-1)-i)];
     end
   end
   endgenerate

From 43a06950aa4d29ea6b3301ad574cb2e93fc5bad7 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Thu, 29 Jun 2017 15:03:54 +0300
Subject: [PATCH 968/972] axi_ad9361: Altera fix lvds interface

 - use internal serdes pll
---
 .../altera/axi_ad9361_alt_lvds_rx.v           | 202 +++++++
 .../altera/axi_ad9361_alt_lvds_tx.v           | 186 ++++++
 .../axi_ad9361/altera/axi_ad9361_lvds_if.v    | 557 +++++-------------
 library/axi_ad9361/axi_ad9361_hw.tcl          |  12 +-
 4 files changed, 538 insertions(+), 419 deletions(-)
 create mode 100644 library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v
 create mode 100644 library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v

diff --git a/library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v
new file mode 100644
index 000000000..9f48dd55a
--- /dev/null
+++ b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v
@@ -0,0 +1,202 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9361_alt_lvds_rx (
+
+  // physical interface (receive)
+
+  rx_clk_in_p,
+  rx_clk_in_n,
+  rx_frame_in_p,
+  rx_frame_in_n,
+  rx_data_in_p,
+  rx_data_in_n,
+
+  // data interface
+
+  clk,
+  rx_frame,
+  rx_data_0,
+  rx_data_1,
+  rx_data_2,
+  rx_data_3,
+  rx_locked);
+
+  // physical interface (receive)
+
+  input           rx_clk_in_p;
+  input           rx_clk_in_n;
+  input           rx_frame_in_p;
+  input           rx_frame_in_n;
+  input   [ 5:0]  rx_data_in_p;
+  input   [ 5:0]  rx_data_in_n;
+
+  // data interface
+
+  output          clk;
+  output  [ 3:0]  rx_frame;
+  output  [ 5:0]  rx_data_0;
+  output  [ 5:0]  rx_data_1;
+  output  [ 5:0]  rx_data_2;
+  output  [ 5:0]  rx_data_3;
+  output          rx_locked;
+
+  // internal signals
+
+  wire    [27:0]  rx_data_s;
+ 
+  // instantiations
+
+  assign rx_frame[3] = rx_data_s[24];
+  assign rx_frame[2] = rx_data_s[25];
+  assign rx_frame[1] = rx_data_s[26];
+  assign rx_frame[0] = rx_data_s[27];
+  assign rx_data_3[5] = rx_data_s[20];
+  assign rx_data_3[4] = rx_data_s[16];
+  assign rx_data_3[3] = rx_data_s[12];
+  assign rx_data_3[2] = rx_data_s[ 8];
+  assign rx_data_3[1] = rx_data_s[ 4];
+  assign rx_data_3[0] = rx_data_s[ 0];
+  assign rx_data_2[5] = rx_data_s[21];
+  assign rx_data_2[4] = rx_data_s[17];
+  assign rx_data_2[3] = rx_data_s[13];
+  assign rx_data_2[2] = rx_data_s[ 9];
+  assign rx_data_2[1] = rx_data_s[ 5];
+  assign rx_data_2[0] = rx_data_s[ 1];
+  assign rx_data_1[5] = rx_data_s[22];
+  assign rx_data_1[4] = rx_data_s[18];
+  assign rx_data_1[3] = rx_data_s[14];
+  assign rx_data_1[2] = rx_data_s[10];
+  assign rx_data_1[1] = rx_data_s[ 6];
+  assign rx_data_1[0] = rx_data_s[ 2];
+  assign rx_data_0[5] = rx_data_s[23];
+  assign rx_data_0[4] = rx_data_s[19];
+  assign rx_data_0[3] = rx_data_s[15];
+  assign rx_data_0[2] = rx_data_s[11];
+  assign rx_data_0[1] = rx_data_s[ 7];
+  assign rx_data_0[0] = rx_data_s[ 3];
+
+  altlvds_rx #(
+    .buffer_implementation ("RAM"),
+    .cds_mode ("UNUSED"),
+    .common_rx_tx_pll ("ON"),
+    .data_align_rollover (4),
+    .data_rate ("500.0 Mbps"),
+    .deserialization_factor (4),
+    .dpa_initial_phase_value (0),
+    .dpll_lock_count (0),
+    .dpll_lock_window (0),
+    .enable_clock_pin_mode ("UNUSED"),
+    .enable_dpa_align_to_rising_edge_only ("OFF"),
+    .enable_dpa_calibration ("ON"),
+    .enable_dpa_fifo ("UNUSED"),
+    .enable_dpa_initial_phase_selection ("OFF"),
+    .enable_dpa_mode ("OFF"),
+    .enable_dpa_pll_calibration ("OFF"),
+    .enable_soft_cdr_mode ("OFF"),
+    .implement_in_les ("OFF"),
+    .inclock_boost (0),
+    .inclock_data_alignment ("EDGE_ALIGNED"),
+    .inclock_period (4000),
+    .inclock_phase_shift (0),
+    .input_data_rate (500),
+    .intended_device_family ("Cyclone V"),
+    .lose_lock_on_one_change ("UNUSED"),
+    .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"),
+    .lpm_type ("altlvds_rx"),
+    .number_of_channels (7),
+    .outclock_resource ("Regional clock"),
+    .pll_operation_mode ("NORMAL"),
+    .pll_self_reset_on_loss_lock ("UNUSED"),
+    .port_rx_channel_data_align ("PORT_UNUSED"),
+    .port_rx_data_align ("PORT_UNUSED"),
+    .refclk_frequency ("250.000000 MHz"),
+    .registered_data_align_input ("UNUSED"),
+    .registered_output ("ON"),
+    .reset_fifo_at_first_lock ("UNUSED"),
+    .rx_align_data_reg ("RISING_EDGE"),
+    .sim_dpa_is_negative_ppm_drift ("OFF"),
+    .sim_dpa_net_ppm_variation (0),
+    .sim_dpa_output_clock_phase_shift (0),
+    .use_coreclock_input ("OFF"),
+    .use_dpll_rawperror ("OFF"),
+    .use_external_pll ("OFF"),
+    .use_no_phase_shift ("ON"),
+    .x_on_bitslip ("ON"),
+    .clk_src_is_pll ("off"))
+  i_altlvds_rx (
+    .rx_inclock (rx_clk_in_p),
+    .rx_in ({rx_frame_in_p, rx_data_in_p}),
+    .rx_outclock (clk),
+    .rx_out (rx_data_s),
+    .rx_locked (rx_locked),
+    .dpa_pll_cal_busy (),
+    .dpa_pll_recal (1'b0),
+    .pll_areset (1'b0),
+    .pll_phasecounterselect (),
+    .pll_phasedone (1'b1),
+    .pll_phasestep (),
+    .pll_phaseupdown (),
+    .pll_scanclk (),
+    .rx_cda_max (),
+    .rx_cda_reset ({7{1'b0}}),
+    .rx_channel_data_align ({7{1'b0}}),
+    .rx_coreclk ({7{1'b1}}),
+    .rx_data_align (1'b0),
+    .rx_data_align_reset (1'b0),
+    .rx_data_reset (1'b0),
+    .rx_deskew (1'b0),
+    .rx_divfwdclk (),
+    .rx_dpa_lock_reset ({7{1'b0}}),
+    .rx_dpa_locked (),
+    .rx_dpaclock (1'b0),
+    .rx_dpll_enable ({7{1'b1}}),
+    .rx_dpll_hold ({7{1'b0}}),
+    .rx_dpll_reset ({7{1'b0}}),
+    .rx_enable (1'b1),
+    .rx_fifo_reset ({7{1'b0}}),
+    .rx_pll_enable (1'b1),
+    .rx_readclock (1'b0),
+    .rx_reset ({7{1'b0}}),
+    .rx_syncclock (1'b0));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v
new file mode 100644
index 000000000..2b96fccb6
--- /dev/null
+++ b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v
@@ -0,0 +1,186 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_ad9361_alt_lvds_tx (
+
+  // physical interface (transmit)
+
+  tx_clk_out_p,
+  tx_clk_out_n,
+  tx_frame_out_p,
+  tx_frame_out_n,
+  tx_data_out_p,
+  tx_data_out_n,
+
+  // data interface
+
+  tx_clk,
+  clk,
+  tx_frame,
+  tx_data_0,
+  tx_data_1,
+  tx_data_2,
+  tx_data_3,
+  tx_locked);
+
+  // physical interface (transmit)
+
+  output          tx_clk_out_p;
+  output          tx_clk_out_n;
+  output          tx_frame_out_p;
+  output          tx_frame_out_n;
+  output  [ 5:0]  tx_data_out_p;
+  output  [ 5:0]  tx_data_out_n;
+
+  // data interface
+
+  input           tx_clk;
+  input           clk;
+  input   [ 3:0]  tx_frame;
+  input   [ 5:0]  tx_data_0;
+  input   [ 5:0]  tx_data_1;
+  input   [ 5:0]  tx_data_2;
+  input   [ 5:0]  tx_data_3;
+  output          tx_locked;
+
+  // internal registers
+
+  reg     [27:0]  tx_data_n = 'd0;
+  reg     [27:0]  tx_data_p = 'd0;
+
+  // internal signals
+
+  wire            core_clk;
+  wire    [27:0]  tx_data_s;
+ 
+  // instantiations
+
+  assign tx_clk_out_n = 1'd0;
+  assign tx_frame_out_n = 1'd0;
+  assign tx_data_out_n = 6'd0;
+
+  assign tx_data_s[24] = tx_frame[3];
+  assign tx_data_s[25] = tx_frame[2];
+  assign tx_data_s[26] = tx_frame[1];
+  assign tx_data_s[27] = tx_frame[0];
+  assign tx_data_s[20] = tx_data_3[5];
+  assign tx_data_s[16] = tx_data_3[4];
+  assign tx_data_s[12] = tx_data_3[3];
+  assign tx_data_s[ 8] = tx_data_3[2];
+  assign tx_data_s[ 4] = tx_data_3[1];
+  assign tx_data_s[ 0] = tx_data_3[0];
+  assign tx_data_s[21] = tx_data_2[5];
+  assign tx_data_s[17] = tx_data_2[4];
+  assign tx_data_s[13] = tx_data_2[3];
+  assign tx_data_s[ 9] = tx_data_2[2];
+  assign tx_data_s[ 5] = tx_data_2[1];
+  assign tx_data_s[ 1] = tx_data_2[0];
+  assign tx_data_s[22] = tx_data_1[5];
+  assign tx_data_s[18] = tx_data_1[4];
+  assign tx_data_s[14] = tx_data_1[3];
+  assign tx_data_s[10] = tx_data_1[2];
+  assign tx_data_s[ 6] = tx_data_1[1];
+  assign tx_data_s[ 2] = tx_data_1[0];
+  assign tx_data_s[23] = tx_data_0[5];
+  assign tx_data_s[19] = tx_data_0[4];
+  assign tx_data_s[15] = tx_data_0[3];
+  assign tx_data_s[11] = tx_data_0[2];
+  assign tx_data_s[ 7] = tx_data_0[1];
+  assign tx_data_s[ 3] = tx_data_0[0];
+
+  always @(negedge clk) begin
+    tx_data_n <= tx_data_s;
+  end
+
+  always @(posedge core_clk) begin
+    tx_data_p <= tx_data_n;
+  end
+
+  altlvds_tx #(
+    .center_align_msb ("UNUSED"),
+    .common_rx_tx_pll ("ON"),
+    .coreclock_divide_by (1),
+    .data_rate ("500.0 Mbps"),
+    .deserialization_factor (4),
+    .differential_drive (0),
+    .enable_clock_pin_mode ("UNUSED"),
+    .implement_in_les ("OFF"),
+    .inclock_boost (0),
+    .inclock_data_alignment ("EDGE_ALIGNED"),
+    .inclock_period (4000),
+    .inclock_phase_shift (0),
+    .intended_device_family ("Cyclone V"),
+    .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"),
+    .lpm_type ("altlvds_tx"),
+    .multi_clock ("OFF"),
+    .number_of_channels (7),
+    .outclock_alignment ("EDGE_ALIGNED"),
+    .outclock_divide_by (2),
+    .outclock_duty_cycle (50),
+    .outclock_multiply_by (1),
+    .outclock_phase_shift (0),
+    .outclock_resource ("Regional clock"),
+    .output_data_rate (500),
+    .pll_compensation_mode ("AUTO"),
+    .pll_self_reset_on_loss_lock ("OFF"),
+    .preemphasis_setting (0),
+    .refclk_frequency ("250.000000 MHz"),
+    .registered_input ("TX_CORECLK"),
+    .use_external_pll ("OFF"),
+    .use_no_phase_shift ("ON"),
+    .vod_setting (0),
+    .clk_src_is_pll ("off"))
+  i_altlvds_tx (
+    .tx_inclock (tx_clk),
+    .tx_coreclock (core_clk),
+    .tx_in (tx_data_p),
+    .tx_outclock (tx_clk_out_p),
+    .tx_out ({tx_frame_out_p, tx_data_out_p}),
+    .tx_locked (tx_locked),
+    .pll_areset (1'b0),
+    .sync_inclock (1'b0),
+    .tx_data_reset (1'b0),
+    .tx_enable (1'b1),
+    .tx_pll_enable (1'b1),
+    .tx_syncclock (1'b0));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
index f9ebfbcba..67461e8db 100644
--- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
@@ -1,37 +1,35 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
+// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
 //
-// All rights reserved.
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
 //
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
+// The user should read each of these license terms, and understand the
+// freedoms and responsabilities that he or she has by using this source/core.
 //
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
 //
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
 
@@ -123,434 +121,167 @@ module axi_ad9361_lvds_if #(
   // internal registers
 
   reg     [ 3:0]  rx_frame = 'd0;
-  reg             rx_error = 'd0;
-  reg             rx_valid = 'd0;
   reg     [ 5:0]  rx_data_3 = 'd0;
   reg     [ 5:0]  rx_data_2 = 'd0;
   reg     [ 5:0]  rx_data_1 = 'd0;
   reg     [ 5:0]  rx_data_0 = 'd0;
-  reg     [23:0]  rx_data = 'd0;
+  reg             rx_error_r2 = 'd0;
+  reg             rx_valid_r2 = 'd0;
+  reg     [23:0]  rx_data_r2 = 'd0;
+  reg             tx_data_sel = 'd0;
+  reg     [47:0]  tx_data = 'd0;
   reg     [ 3:0]  tx_frame = 'd0;
-  reg     [ 3:0]  tx_p_frame = 'd0;
-  reg     [ 3:0]  tx_n_frame = 'd0;
-  reg     [ 5:0]  tx_data_d_0 = 'd0;
-  reg     [ 5:0]  tx_data_d_1 = 'd0;
-  reg     [ 5:0]  tx_data_d_2 = 'd0;
-  reg     [ 5:0]  tx_data_d_3 = 'd0;
-  reg             tx_data_sel  = 'd0;
-  reg             up_enable_int = 'd0;
-  reg             up_txnrx_int = 'd0;
-  reg             enable_up_m1 = 'd0;
-  reg             txnrx_up_m1 = 'd0;
-  reg             enable_up = 'd0;
-  reg             txnrx_up = 'd0;
-  reg             enable_int = 'd0;
-  reg             txnrx_int = 'd0;
-  reg             enable_n_int = 'd0;
-  reg             txnrx_n_int = 'd0;
-  reg             enable_p_int = 'd0;
-  reg             txnrx_p_int = 'd0;
-  reg    [ 5:0]   tx_p_data_d_0 = 'd0;
-  reg    [ 5:0]   tx_p_data_d_1 = 'd0;
-  reg    [ 5:0]   tx_p_data_d_2 = 'd0;
-  reg    [ 5:0]   tx_p_data_d_3 = 'd0;
-  reg    [ 5:0]   tx_n_data_d_0 = 'd0;
-  reg    [ 5:0]   tx_n_data_d_1 = 'd0;
-  reg    [ 5:0]   tx_n_data_d_2 = 'd0;
-  reg    [ 5:0]   tx_n_data_d_3 = 'd0;
-  reg             adc_n_valid = 'd0;
-  reg             adc_p_valid = 'd0;
-  reg             adc_n_status = 'd0;
-  reg             adc_p_status = 'd0;
-  reg    [47:0]   adc_n_data = 'd0;
-  reg    [47:0]   adc_p_data = 'd0;
+  reg     [ 5:0]  tx_data_0 = 'd0;
+  reg     [ 5:0]  tx_data_1 = 'd0;
+  reg     [ 5:0]  tx_data_2 = 'd0;
+  reg     [ 5:0]  tx_data_3 = 'd0;
 
   // internal signals
 
-  wire            s_clk;
-  wire            loaden;
-  wire    [ 7:0]  phase_s;
-  wire    [ 3:0]  rx_frame_s;
-  wire    [ 5:0]  rx_data_s_3;
-  wire    [ 5:0]  rx_data_s_2;
-  wire    [ 5:0]  rx_data_s_1;
-  wire    [ 5:0]  rx_data_s_0;
   wire    [ 3:0]  rx_frame_inv_s;
+  wire            tx_locked_s;
+  wire    [ 3:0]  rx_frame_s;
+  wire    [ 5:0]  rx_data_0_s;
+  wire    [ 5:0]  rx_data_1_s;
+  wire    [ 5:0]  rx_data_2_s;
+  wire    [ 5:0]  rx_data_3_s;
+  wire            rx_locked_s;
 
-  // unused interface signals
+  // tdd support-
 
-  assign up_adc_drdata = 35'b0;
-  assign up_dac_drdata = 50'b0;
-  assign delay_locked = 1'b1;
+  assign enable = up_enable;
+  assign txnrx = up_txnrx;
+
+  // defaults
+
+  assign delay_locked = 1'd1;
+
+  // receive data path interface
 
   assign rx_frame_inv_s = ~rx_frame;
 
   always @(posedge l_clk) begin
     rx_frame <= rx_frame_s;
-    rx_data_3 <= rx_data_s_3;
-    rx_data_2 <= rx_data_s_2;
-    rx_data_1 <= rx_data_s_1;
-    rx_data_0 <= rx_data_s_0;
+    rx_data_3 <= rx_data_3_s;
+    rx_data_2 <= rx_data_2_s;
+    rx_data_1 <= rx_data_1_s;
+    rx_data_0 <= rx_data_0_s;
     if (rx_frame_inv_s == rx_frame_s) begin
-      rx_error <= 1'b0;
+      rx_error_r2 <= 1'b0;
     end else begin
-      rx_error <= 1'b1;
+      rx_error_r2 <= 1'b1;
     end
-    case ({adc_r1_mode, rx_frame})
-      // R2 Mode
-      5'b01111: begin
-        rx_valid <= 1'b1;
-        rx_data[23:12] <= {rx_data_1,   rx_data_3};
-        rx_data[11: 0] <= {rx_data_0,   rx_data_2};
+    case (rx_frame)
+      4'b1111: begin
+        rx_valid_r2 <= 1'b1;
+        rx_data_r2[23:12] <= {rx_data_1,   rx_data_3};
+        rx_data_r2[11: 0] <= {rx_data_0,   rx_data_2};
       end
-      5'b01110: begin
-        rx_valid <= 1'b1;
-        rx_data[23:12] <= {rx_data_2,   rx_data_s_0};
-        rx_data[11: 0] <= {rx_data_1,   rx_data_3};
+      4'b1110: begin
+        rx_valid_r2 <= 1'b1;
+        rx_data_r2[23:12] <= {rx_data_2,   rx_data_0_s};
+        rx_data_r2[11: 0] <= {rx_data_1,   rx_data_3};
       end
-      5'b01100: begin
-        rx_valid <= 1'b1;
-        rx_data[23:12] <= {rx_data_3,   rx_data_s_1};
-        rx_data[11: 0] <= {rx_data_2,   rx_data_s_0};
+      4'b1100: begin
+        rx_valid_r2 <= 1'b1;
+        rx_data_r2[23:12] <= {rx_data_3,   rx_data_1_s};
+        rx_data_r2[11: 0] <= {rx_data_2,   rx_data_0_s};
       end
-      5'b01000: begin
-        rx_valid <= 1'b1;
-        rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
-        rx_data[11: 0] <= {rx_data_3,   rx_data_s_1};
+      4'b1000: begin
+        rx_valid_r2 <= 1'b1;
+        rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s};
+        rx_data_r2[11: 0] <= {rx_data_3,   rx_data_1_s};
       end
-      5'b00000: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= {rx_data_1,   rx_data_3};
-        rx_data[11: 0] <= {rx_data_0,   rx_data_2};
+      4'b0000: begin
+        rx_valid_r2 <= 1'b0;
+        rx_data_r2[23:12] <= {rx_data_1,   rx_data_3};
+        rx_data_r2[11: 0] <= {rx_data_0,   rx_data_2};
       end
-      5'b00001: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= {rx_data_2,   rx_data_s_0};
-        rx_data[11: 0] <= {rx_data_1,   rx_data_3};
+      4'b0001: begin
+        rx_valid_r2 <= 1'b0;
+        rx_data_r2[23:12] <= {rx_data_2,   rx_data_0_s};
+        rx_data_r2[11: 0] <= {rx_data_1,   rx_data_3};
       end
-      5'b00011: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= {rx_data_3,   rx_data_s_1};
-        rx_data[11: 0] <= {rx_data_2,   rx_data_s_0};
+      4'b0011: begin
+        rx_valid_r2 <= 1'b0;
+        rx_data_r2[23:12] <= {rx_data_3,   rx_data_1_s};
+        rx_data_r2[11: 0] <= {rx_data_2,   rx_data_0_s};
       end
-      5'b00111: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
-        rx_data[11: 0] <= {rx_data_3,   rx_data_s_1};
-      end
-      // R1 Mode
-      5'b11100: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= {rx_data_s_1, rx_data_s_3};
-        rx_data[11: 0] <= {rx_data_s_0, rx_data_s_2};
-      end
-      5'b10110: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= {rx_data_2, rx_data_s_0};
-        rx_data[11: 0] <= {rx_data_1, rx_data_3};
-      end
-      5'b11001: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
-        rx_data[11: 0] <= {rx_data_3, rx_data_s_1};
-      end
-      5'b10011: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= {rx_data_3, rx_data_s_1};
-        rx_data[11: 0] <= {rx_data_2, rx_data_s_0};
+      4'b0111: begin
+        rx_valid_r2 <= 1'b0;
+        rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s};
+        rx_data_r2[11: 0] <= {rx_data_3,   rx_data_1_s};
       end
       default: begin
-        rx_valid <= 1'b0;
-        rx_data[23:12] <= 12'd0;
-        rx_data[11: 0] <= 12'd0;
+        rx_valid_r2 <= 1'b0;
+        rx_data_r2[23:12] <= 12'd0;
+        rx_data_r2[11: 0] <= 12'd0;
       end
     endcase
-    if (rx_valid == 1'b1) begin
-      adc_p_valid <= 1'b0;
-      adc_p_data <= {24'd0, rx_data};
+    if (rx_valid_r2 == 1'b1) begin
+      adc_valid <= 1'b0;
+      adc_data <= {24'd0, rx_data_r2};
     end else begin
-      adc_p_valid <= 1'b1;
-      adc_p_data <= (adc_r1_mode) ? {24'd0, rx_data} : {rx_data, adc_p_data[23:0]};
+      adc_valid <= 1'b1;
+      adc_data <= {rx_data_r2, adc_data[23:0]};
     end
-    adc_p_status <= ~rx_error & up_drp_locked;
+    adc_status <= ~rx_error_r2 & rx_locked_s & tx_locked_s;
   end
 
-  // transfer to a synchronous common clock
-
-  always @(negedge l_clk) begin
-    adc_n_valid <= adc_p_valid;
-    adc_n_data <= adc_p_data;
-    adc_n_status <= adc_p_status;
-  end
-
-  always @(posedge clk) begin
-    adc_valid <= adc_n_valid;
-    adc_data <= adc_n_data;
-    adc_status <= adc_n_status;
-  end
-
-  always @(posedge clk) begin
-    if (dac_r1_mode == 1'b0) begin
-      tx_data_sel <= ~tx_data_sel;
-    end else begin
-      tx_data_sel <= 1'b0;
-    end
-
-    case ({dac_r1_mode, tx_data_sel})
-      2'b10: begin
-         tx_frame <= 4'b1100;
-         tx_data_d_0 <= dac_data[11: 6]; // i msb
-         tx_data_d_1 <= dac_data[23:18]; // q msb
-         tx_data_d_2 <= dac_data[ 5: 0]; // i lsb
-         tx_data_d_3 <= dac_data[17:12]; // q lsb
-      end
-      2'b00: begin
-         tx_frame <= 4'b1111;
-         tx_data_d_0 <= dac_data[11: 6]; // i msb 0
-         tx_data_d_1 <= dac_data[23:18]; // q msb 0
-         tx_data_d_2 <= dac_data[ 5: 0]; // i lsb 0
-         tx_data_d_3 <= dac_data[17:12]; // q lsb 0
-      end
-      2'b01: begin
-         tx_frame <= 4'b0000;
-         tx_data_d_0 <= dac_data[35:30]; // i msb 1
-         tx_data_d_1 <= dac_data[47:42]; // q msb 1
-         tx_data_d_2 <= dac_data[29:24]; // i lsb 1
-         tx_data_d_3 <= dac_data[41:36]; // q lsb 1
-      end
-    endcase
-
-  end
-
-  // transfer data from a synchronous clock (skew less than 2ns)
-
-  always @(negedge clk) begin
-    tx_n_frame <= tx_frame;
-    tx_n_data_d_0 <= tx_data_d_0;
-    tx_n_data_d_1 <= tx_data_d_1;
-    tx_n_data_d_2 <= tx_data_d_2;
-    tx_n_data_d_3 <= tx_data_d_3;
-  end
+  // transmit data path mux
 
   always @(posedge l_clk) begin
-    tx_p_frame <= tx_n_frame;
-    tx_p_data_d_0 <= tx_n_data_d_0;
-    tx_p_data_d_1 <= tx_n_data_d_1;
-    tx_p_data_d_2 <= tx_n_data_d_2;
-    tx_p_data_d_3 <= tx_n_data_d_3;
-  end
-
-  // tdd/ensm control
-
-  always @(posedge up_clk) begin
-    up_enable_int <= up_enable;
-    up_txnrx_int <= up_txnrx;
-  end
-
-  always @(posedge clk or posedge rst) begin
-    if (rst == 1'b1) begin
-      enable_up_m1 <= 1'b0;
-      txnrx_up_m1 <= 1'b0;
-      enable_up <= 1'b0;
-      txnrx_up <= 1'b0;
+    tx_data_sel <= dac_valid;
+    tx_data <= dac_data;
+    if (tx_data_sel == 1'b1) begin
+      tx_frame <= 4'b1111;
+      tx_data_0 <= tx_data[11: 6];
+      tx_data_1 <= tx_data[23:18];
+      tx_data_2 <= tx_data[ 5: 0];
+      tx_data_3 <= tx_data[17:12];
     end else begin
-      enable_up_m1 <= up_enable_int;
-      txnrx_up_m1 <= up_txnrx_int;
-      enable_up <= enable_up_m1;
-      txnrx_up <= txnrx_up_m1;
+      tx_frame <= 4'b0000;
+      tx_data_0 <= tx_data[35:30];
+      tx_data_1 <= tx_data[47:42];
+      tx_data_2 <= tx_data[29:24];
+      tx_data_3 <= tx_data[41:36];
     end
   end
 
-  always @(posedge clk) begin
-    if (tdd_mode == 1'b1) begin
-      enable_int <= tdd_enable;
-      txnrx_int <= tdd_txnrx;
-    end else begin
-      enable_int <= enable_up;
-      txnrx_int <= txnrx_up;
-    end
-  end
+  // interface (transmit)
 
-  always @(negedge clk) begin
-    enable_n_int <= enable_int;
-    txnrx_n_int <= txnrx_int;
-  end
+  axi_ad9361_alt_lvds_tx i_tx (
+    .tx_clk_out_p (tx_clk_out_p),
+    .tx_clk_out_n (tx_clk_out_n),
+    .tx_frame_out_p (tx_frame_out_p),
+    .tx_frame_out_n (tx_frame_out_n),
+    .tx_data_out_p (tx_data_out_p),
+    .tx_data_out_n (tx_data_out_n),
+    .tx_clk (rx_clk_in_p),
+    .clk (l_clk),
+    .tx_frame (tx_frame),
+    .tx_data_0 (tx_data_0),
+    .tx_data_1 (tx_data_1),
+    .tx_data_2 (tx_data_2),
+    .tx_data_3 (tx_data_3),
+    .tx_locked (tx_locked_s));
 
-  always @(posedge l_clk) begin
-    enable_p_int <= enable_n_int;
-    txnrx_p_int <= txnrx_n_int;
-  end
+  // interface (receive)
 
-  // receive data path interface
-
-  ad_serdes_in #(
-    .DATA_WIDTH (6),
-    .SERDES_FACTOR (4),
-    .DEVICE_TYPE (DEVICE_TYPE))
-  ad_serdes_data_in (
-    .rst (mmcm_rst),
-    .clk (s_clk),
-    .div_clk (l_clk),
-    .loaden (loaden),
-    .locked (up_drp_locked),
-    .phase (phase_s),
-    .data_s0 (rx_data_s_0),
-    .data_s1 (rx_data_s_1),
-    .data_s2 (rx_data_s_2),
-    .data_s3 (rx_data_s_3),
-    .data_s4 (),
-    .data_s5 (),
-    .data_s6 (),
-    .data_s7 (),
-    .data_in_p (rx_data_in_p),
-    .data_in_n (rx_data_in_n),
-    .up_clk (1'd0),
-    .up_dld (6'd0),
-    .up_dwdata (30'd0),
-    .up_drdata (),
-    .delay_clk (1'd0),
-    .delay_rst (1'd0),
-    .delay_locked ());
-
-  // receive frame interface
-
-  ad_serdes_in #(
-    .DATA_WIDTH (1),
-    .SERDES_FACTOR (4),
-    .DEVICE_TYPE (DEVICE_TYPE))
-  ad_serdes_frame_in (
-    .rst (mmcm_rst),
-    .clk (s_clk),
-    .div_clk (l_clk),
-    .loaden (loaden),
-    .locked (up_drp_locked),
-    .phase (phase_s),
-    .data_s0 (rx_frame_s[0]),
-    .data_s1 (rx_frame_s[1]),
-    .data_s2 (rx_frame_s[2]),
-    .data_s3 (rx_frame_s[3]),
-    .data_s4 (),
-    .data_s5 (),
-    .data_s6 (),
-    .data_s7 (),
-    .data_in_p (rx_frame_in_p),
-    .data_in_n (rx_frame_in_n),
-    .up_clk (1'd0),
-    .up_dld (1'd0),
-    .up_dwdata (5'd0),
-    .up_drdata (),
-    .delay_clk (1'd0),
-    .delay_rst (1'd0),
-    .delay_locked ());
-
-  // transmit data interface
-
-  ad_serdes_out #(
-    .DATA_WIDTH (6),
-    .SERDES_FACTOR (4),
-    .DEVICE_TYPE (DEVICE_TYPE))
-  ad_serdes_data_out (
-    .rst (mmcm_rst),
-    .clk (s_clk),
-    .div_clk (l_clk),
-    .loaden (loaden),
-    .data_s0 (tx_p_data_d_0),
-    .data_s1 (tx_p_data_d_1),
-    .data_s2 (tx_p_data_d_2),
-    .data_s3 (tx_p_data_d_3),
-    .data_s4 (6'd0),
-    .data_s5 (6'd0),
-    .data_s6 (6'd0),
-    .data_s7 (6'd0),
-    .data_out_p (tx_data_out_p),
-    .data_out_n (tx_data_out_n));
-
-  // transmit frame interface
-
-  ad_serdes_out #(
-    .DATA_WIDTH (1),
-    .SERDES_FACTOR (4),
-    .DEVICE_TYPE (DEVICE_TYPE))
-  ad_serdes_frame_out (
-    .rst (mmcm_rst),
-    .clk (s_clk),
-    .div_clk (l_clk),
-    .loaden (loaden),
-    .data_s0 (tx_p_frame[0]),
-    .data_s1 (tx_p_frame[1]),
-    .data_s2 (tx_p_frame[2]),
-    .data_s3 (tx_p_frame[3]),
-    .data_s4 (1'd0),
-    .data_s5 (1'd0),
-    .data_s6 (1'd0),
-    .data_s7 (1'd0),
-    .data_out_p (tx_frame_out_p),
-    .data_out_n (tx_frame_out_n));
-
-  // transmit clock interface
-
-  ad_serdes_out #(
-    .DATA_WIDTH(1),
-    .SERDES_FACTOR(4),
-    .DEVICE_TYPE(DEVICE_TYPE))
-  ad_serdes_tx_clock_out(
-    .rst (mmcm_rst),
-    .clk (s_clk),
-    .div_clk (l_clk),
-    .loaden (loaden),
-    .data_s0 (dac_clksel),
-    .data_s1 (~dac_clksel),
-    .data_s2 (dac_clksel),
-    .data_s3 (~dac_clksel),
-    .data_s4 (1'd0),
-    .data_s5 (1'd0),
-    .data_s6 (1'd0),
-    .data_s7 (1'd0),
-    .data_out_p (tx_clk_out_p),
-    .data_out_n (tx_clk_out_n));
-
-  // serdes clock interface
-
-  ad_serdes_clk #(
-    .DEVICE_TYPE (DEVICE_TYPE))
-  ad_serdes_clk (
-    .rst (mmcm_rst),
-    .clk_in_p (rx_clk_in_p),
-    .clk_in_n (rx_clk_in_n),
-    .clk (s_clk),
-    .div_clk (l_clk),
-    .out_clk (),
-    .loaden (loaden),
-    .phase (phase_s),
-    .up_clk (up_clk),
-    .up_rstn (up_rstn),
-    .up_drp_sel (up_drp_sel),
-    .up_drp_wr (up_drp_wr),
-    .up_drp_addr (up_drp_addr),
-    .up_drp_wdata (up_drp_wdata),
-    .up_drp_rdata (up_drp_rdata),
-    .up_drp_ready (up_drp_ready),
-    .up_drp_locked (up_drp_locked));
-
- // enable
-
-  ad_cmos_out #(
-    .DEVICE_TYPE (DEVICE_TYPE))
-  i_enable (
-    .tx_clk (l_clk),
-    .tx_data_p (enable_p_int),
-    .tx_data_n (enable_p_int),
-    .tx_data_out (enable));
-
-  // txnrx
-
-  ad_cmos_out #(
-    .DEVICE_TYPE (DEVICE_TYPE))
-  i_txnrx (
-    .tx_clk (l_clk),
-    .tx_data_p (txnrx_p_int),
-    .tx_data_n (txnrx_p_int),
-    .tx_data_out (txnrx));
+  axi_ad9361_alt_lvds_rx i_rx (
+    .rx_clk_in_p (rx_clk_in_p),
+    .rx_clk_in_n (rx_clk_in_n),
+    .rx_frame_in_p (rx_frame_in_p),
+    .rx_frame_in_n (rx_frame_in_n),
+    .rx_data_in_p (rx_data_in_p),
+    .rx_data_in_n (rx_data_in_n),
+    .clk (l_clk),
+    .rx_frame (rx_frame_s),
+    .rx_data_0 (rx_data_0_s),
+    .rx_data_1 (rx_data_1_s),
+    .rx_data_2 (rx_data_2_s),
+    .rx_data_3 (rx_data_3_s),
+    .rx_locked (rx_locked_s));
 
 endmodule
 
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index eb936d355..3f8e62b56 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -5,9 +5,9 @@ source ../scripts/adi_ip_alt.tcl
 
 ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab
 ad_ip_files axi_ad9361 [list\
-  $ad_hdl_dir/library/altera/common/ad_cmos_out_core_c5.v \
-  $ad_hdl_dir/library/altera/common/ad_serdes_in_core_c5.v \
-  $ad_hdl_dir/library/altera/common/ad_serdes_out_core_c5.v \
+  $ad_hdl_dir/library/altera/common/ad_lvds_clk.v \
+  $ad_hdl_dir/library/altera/common/ad_lvds_in.v \
+  $ad_hdl_dir/library/altera/common/ad_lvds_out.v \
   $ad_hdl_dir/library/altera/common/ad_mul.v \
   $ad_hdl_dir/library/altera/common/ad_dcfilter.v \
   $ad_hdl_dir/library/common/ad_rst.v \
@@ -29,8 +29,9 @@ ad_ip_files axi_ad9361 [list\
   $ad_hdl_dir/library/common/up_dac_common.v \
   $ad_hdl_dir/library/common/up_dac_channel.v \
   $ad_hdl_dir/library/common/up_tdd_cntrl.v \
+  altera/axi_ad9361_alt_lvds_tx.v \
+  altera/axi_ad9361_alt_lvds_rx.v \
   altera/axi_ad9361_lvds_if.v \
-  altera/axi_ad9361_cmos_if.v \
   axi_ad9361_rx_pnmon.v \
   axi_ad9361_rx_channel.v \
   axi_ad9361_rx.v \
@@ -40,8 +41,7 @@ ad_ip_files axi_ad9361 [list\
   axi_ad9361_tdd_if.v \
   axi_ad9361.v \
   $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
-  axi_ad9361_constr.sdc] \
-  axi_ad9361_fileset
+  axi_ad9361_constr.sdc]
 
 # parameters
 

From 1c1856140e1fca02f0a9539f78080fabd22704dc Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 30 Jun 2017 14:20:39 +0300
Subject: [PATCH 969/972] kc705: Fix ethernet address span

---
 projects/common/kc705/kc705_system_bd.tcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl
index 3067eca3a..d97d57bb8 100644
--- a/projects/common/kc705/kc705_system_bd.tcl
+++ b/projects/common/kc705/kc705_system_bd.tcl
@@ -262,6 +262,8 @@ create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruc
   [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr
 
 set_property range 0x2000000 [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_linear_flash}]
+set_property range 0x2000    [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_ethernet}]
+
 
 ad_connect axi_ddr_cntrl/device_temp_i GND
 

From f6f7cff8a0bd11c19cd101cf2f66c09b5a1c40ea Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 12 Jul 2017 12:12:30 +0300
Subject: [PATCH 970/972] util_clkdiv: Added altera version

---
 library/util_clkdiv/util_clkdiv_alt.v  | 82 ++++++++++++++++++++++++++
 library/util_clkdiv/util_clkdiv_hw.tcl | 25 ++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 library/util_clkdiv/util_clkdiv_alt.v
 create mode 100644 library/util_clkdiv/util_clkdiv_hw.tcl

diff --git a/library/util_clkdiv/util_clkdiv_alt.v b/library/util_clkdiv/util_clkdiv_alt.v
new file mode 100644
index 000000000..3c79f1fce
--- /dev/null
+++ b/library/util_clkdiv/util_clkdiv_alt.v
@@ -0,0 +1,82 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
+// clk_sel is 1. Provides a glitch free output clock
+// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_clkdiv_alt #(
+  parameter SIM_DEVICE = "CYCLONE5",
+  parameter CLOCK_TYPE = "Global Clock") (
+
+  input   clk,
+  input   reset,
+  output  clk_out,
+  output  reset_out
+ );
+
+reg enable;
+reg reset_d1;
+
+assign reset_out = reset | reset_d1;
+
+always @(posedge clk) begin
+  reset_d1 <= reset;
+end
+
+always @(posedge clk) begin
+  enable <= ~enable;
+end
+  
+generate if (SIM_DEVICE == "CYCLONE5") begin
+	cyclonev_clkena #(
+		.clock_type ("Global Clock"),
+		.ena_register_mode ("falling edge"),
+		.lpm_type ("cyclonev_clkena")
+  ) clock_divider_by_2 ( 
+	.ena(enable),
+	.enaout(),
+	.inclk(clk),
+//	.clkselect (2'b0),
+	.outclk(clk_out));
+
+end endgenerate
+
+endmodule  // util_clkdiv_alt
diff --git a/library/util_clkdiv/util_clkdiv_hw.tcl b/library/util_clkdiv/util_clkdiv_hw.tcl
new file mode 100644
index 000000000..310801727
--- /dev/null
+++ b/library/util_clkdiv/util_clkdiv_hw.tcl
@@ -0,0 +1,25 @@
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+
+set_module_property NAME util_clkdiv
+set_module_property DESCRIPTION "Clock Division Utility"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME util_clkdiv
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL util_clkdiv_alt
+add_fileset_file util_clkdiv_alt.v       VERILOG PATH util_clkdiv_alt.v TOP_LEVEL_FILE
+
+# defaults
+
+ad_alt_intf clock   clk             input   1
+ad_alt_intf reset   reset           input 1 if_clk
+ad_alt_intf clock   clk_out         output  1
+ad_alt_intf reset   reset_out       output 1 if_clk_out
+

From 128be6fb69bd30f7baa481665f321f1135c309b6 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 12 Jul 2017 15:59:12 +0300
Subject: [PATCH 971/972] arradio: Changed clock domain of the ADC and DAC path
 to half the interface clock

---
 projects/arradio/common/arradio_qsys.tcl | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/projects/arradio/common/arradio_qsys.tcl b/projects/arradio/common/arradio_qsys.tcl
index 49cb57b51..ddb5607b8 100755
--- a/projects/arradio/common/arradio_qsys.tcl
+++ b/projects/arradio/common/arradio_qsys.tcl
@@ -20,6 +20,12 @@ add_connection sys_clk.clk axi_ad9361.if_delay_clk
 add_connection sys_clk.clk axi_ad9361.s_axi_clock
 add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
 
+# clk division
+
+add_instance util_clkdiv_ad9361 util_clkdiv 1.0
+add_connection axi_ad9361.if_l_clk util_clkdiv_ad9361.if_clk
+add_connection axi_ad9361.if_rst util_clkdiv_ad9361.if_reset
+
 # adc-wfifo & dac-rfifo
 
 add_instance util_adc_wfifo util_wfifo 1.0
@@ -29,8 +35,8 @@ set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
 set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
 add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
 add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
-add_connection sys_dma_clk.clk util_adc_wfifo.if_dout_clk
-add_connection sys_dma_clk.clk_reset util_adc_wfifo.if_dout_rstn
+add_connection util_clkdiv_ad9361.if_clk_out util_adc_wfifo.if_dout_clk
+add_connection util_clkdiv_ad9361.if_reset_out util_adc_wfifo.if_dout_rstn
 add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
 add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
 add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
@@ -46,8 +52,8 @@ set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
 set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
 add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
 add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
-add_connection sys_dma_clk.clk util_dac_rfifo.if_din_clk
-add_connection sys_dma_clk.clk_reset util_dac_rfifo.if_din_rstn
+add_connection util_clkdiv_ad9361.if_clk_out util_dac_rfifo.if_din_clk
+add_connection util_clkdiv_ad9361.if_reset_out util_dac_rfifo.if_din_rstn
 add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
 add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
 add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
@@ -59,8 +65,8 @@ add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
 add_instance util_adc_pack util_cpack 1.0
 set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
 set_instance_parameter_value util_adc_pack {CHANNEL_DATA_WIDTH} {16}
-add_connection sys_dma_clk.clk util_adc_pack.if_adc_clk
-add_connection sys_dma_clk.clk_reset util_adc_pack.if_adc_rst
+add_connection util_clkdiv_ad9361.if_clk_out util_adc_pack.if_adc_clk
+add_connection util_clkdiv_ad9361.if_reset_out util_adc_pack.if_adc_rst
 add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
 add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
 add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
@@ -71,7 +77,7 @@ add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
 add_instance util_dac_upack util_upack 1.0
 set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
 set_instance_parameter_value util_dac_upack {CHANNEL_DATA_WIDTH} {16}
-add_connection sys_dma_clk.clk util_dac_upack.if_dac_clk
+add_connection util_clkdiv_ad9361.if_clk_out util_dac_upack.if_dac_clk
 add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
 add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
 add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
@@ -99,7 +105,7 @@ add_connection sys_clk.clk axi_adc_dma.s_axi_clock
 add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
 add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
 add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
-add_connection sys_dma_clk.clk axi_adc_dma.if_fifo_wr_clk
+add_connection util_clkdiv_ad9361.if_clk_out axi_adc_dma.if_fifo_wr_clk
 add_connection util_adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
 add_connection util_adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
 add_connection util_adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
@@ -127,7 +133,7 @@ add_connection sys_clk.clk axi_dac_dma.s_axi_clock
 add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
 add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
 add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
-add_connection sys_dma_clk.clk axi_dac_dma.if_fifo_rd_clk
+add_connection util_clkdiv_ad9361.if_clk_out axi_dac_dma.if_fifo_rd_clk
 add_connection util_dac_upack.if_dac_valid axi_dac_dma.if_fifo_rd_en
 add_connection axi_dac_dma.if_fifo_rd_dout util_dac_upack.if_dac_data
 add_connection axi_dac_dma.if_fifo_rd_xfer_req util_dac_upack.if_dma_xfer_in

From ed12efc6203eb08f9c015eb18e9d0fa4d1fb5a38 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 19 Jul 2017 15:17:55 +0300
Subject: [PATCH 972/972] arradio: Revert tcl related changes, to fix DDR
 Bandwidth related issue

---
 projects/arradio/c5soc/Makefile               |   83 +-
 projects/arradio/c5soc/system_bd.qsys         |  430 ++++
 projects/arradio/c5soc/system_bd.tcl          | 1321 ------------
 projects/arradio/c5soc/system_constr.sdc      |  113 +-
 projects/arradio/c5soc/system_project.tcl     |  106 +-
 projects/arradio/c5soc/system_qsys.tcl        |    5 -
 projects/arradio/c5soc/system_top.v           |  575 +++--
 projects/arradio/common/arradio_bd.qsys       |  780 +++++++
 projects/arradio/common/arradio_qsys.tcl      |  157 --
 projects/common/c5soc/c5soc_system_assign.tcl |  286 +--
 projects/common/c5soc/c5soc_system_bd.qsys    | 1887 +++++++++++++++++
 projects/common/c5soc/c5soc_system_qsys.tcl   |  311 ---
 12 files changed, 3754 insertions(+), 2300 deletions(-)
 create mode 100755 projects/arradio/c5soc/system_bd.qsys
 delete mode 100644 projects/arradio/c5soc/system_bd.tcl
 delete mode 100644 projects/arradio/c5soc/system_qsys.tcl
 create mode 100755 projects/arradio/common/arradio_bd.qsys
 delete mode 100755 projects/arradio/common/arradio_qsys.tcl
 create mode 100755 projects/common/c5soc/c5soc_system_bd.qsys
 delete mode 100755 projects/common/c5soc/c5soc_system_qsys.tcl

diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile
index fccd09735..1fbc2a606 100644
--- a/projects/arradio/c5soc/Makefile
+++ b/projects/arradio/c5soc/Makefile
@@ -5,17 +5,82 @@
 ####################################################################################
 ####################################################################################
 
-ifeq ($(MMU),)
-  MMU := 1
-endif
-
-export ALT_NIOS_MMU_ENABLED := $(MMU)
-
 M_DEPS += system_top.v
 M_DEPS += system_project.tcl
 M_DEPS += system_constr.sdc
+M_DEPS += system_bd.qsys
+M_DEPS += ../common/arradio_bd.qsys
 M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys
 M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
+M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v
+M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
+M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/common/ad_addsub.v
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dcfilter.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_iqcor.v
+M_DEPS += ../../../library/altera/common/ad_mul.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/ad_tdd_control.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_tdd_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
 
 
 M_ALTERA := quartus_sh --64bit -t 
@@ -34,7 +99,6 @@ M_FLIST += *.sta.*
 M_FLIST += *.qsf
 M_FLIST += *.qpf
 M_FLIST += *.qws
-M_FLIST += *.qsys
 M_FLIST += *.sof
 M_FLIST += *.cdf
 M_FLIST += *.sld
@@ -49,9 +113,6 @@ M_FLIST += reconfig_mif
 M_FLIST += *.sopcinfo
 M_FLIST +=  *.jdi
 M_FLIST += *.pin
-M_FLIST += *_summary.csv
-M_FLIST += *.dpf
-M_FLIST += system_qsys_script.tcl
 
 
 
@@ -68,7 +129,7 @@ clean-all:
 
 
 arradio_c5soc.sof: $(M_DEPS)
-	-rm -rf $(M_FLIST)
+	rm -rf $(M_FLIST)
 	$(M_ALTERA) system_project.tcl  >> arradio_c5soc_quartus.log 2>&1
 
 ####################################################################################
diff --git a/projects/arradio/c5soc/system_bd.qsys b/projects/arradio/c5soc/system_bd.qsys
new file mode 100755
index 000000000..7f5780e09
--- /dev/null
+++ b/projects/arradio/c5soc/system_bd.qsys
@@ -0,0 +1,430 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element arradio
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element arradio.axi_ad9361_s_axi
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element arradio.axi_dmac_adc_s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element arradio.axi_dmac_dac_s_axi
+   {
+      datum baseAddress
+      {
+         value = "16384";
+         type = "String";
+      }
+   }
+   element arradio.gpio_s1
+   {
+      datum baseAddress
+      {
+         value = "36864";
+         type = "String";
+      }
+   }
+   element arradio.spi_ad9361_spi_control_port
+   {
+      datum baseAddress
+      {
+         value = "32768";
+         type = "String";
+      }
+   }
+   element c5soc
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="5CSXFC6D6F31C8ES" />
+ <parameter name="deviceFamily" value="Cyclone V" />
+ <parameter name="deviceSpeedGrade" value="8_H6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="arradio_c5soc.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="axi_ad9361_device_clock"
+   internal="arradio.axi_ad9361_device_clock" />
+ <interface
+   name="axi_ad9361_device_if"
+   internal="arradio.axi_ad9361_device_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9361_l_clk"
+   internal="arradio.axi_ad9361_l_clk"
+   type="clock"
+   dir="start" />
+ <interface name="clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="gpio_external_connection"
+   internal="arradio.gpio_external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
+ <interface
+   name="spi_ad9361_external"
+   internal="arradio.spi_ad9361_external"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_external_connection"
+   internal="c5soc.sys_gpio_external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_h2f_reset"
+   internal="c5soc.sys_hps_h2f_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="sys_hps_hps_io"
+   internal="c5soc.sys_hps_hps_io"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_i2c0"
+   internal="c5soc.sys_hps_i2c0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_i2c0_clk"
+   internal="c5soc.sys_hps_i2c0_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_hps_i2c0_scl_in"
+   internal="c5soc.sys_hps_i2c0_scl_in"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_hps_memory"
+   internal="c5soc.sys_hps_memory"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_spim0"
+   internal="c5soc.sys_hps_spim0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_spim0_sclk_out"
+   internal="c5soc.sys_hps_spim0_sclk_out"
+   type="clock"
+   dir="start" />
+ <interface
+   name="vga_clock_video_output_clocked_video"
+   internal="c5soc.vga_clock_video_output_clocked_video"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="vga_pixel_clock_bridge_out_clk"
+   internal="c5soc.vga_pixel_clock_bridge_out_clk"
+   type="clock"
+   dir="start" />
+ <module name="arradio" kind="arradio_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 32" />
+  <parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram2_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 32" />
+  <parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="9" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="80000000" />
+  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="9" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
+  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_arradio</parameter>
+ </module>
+ <module name="c5soc" kind="c5soc_system_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
+     value="AddressWidth = 18" />
+  <parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" />
+  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" />
+ </module>
+ <module name="sys_clk" kind="clock_source" version="16.0" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="arradio.axi_dmac_adc_m_dest_axi"
+   end="c5soc.sys_mem_interconnect_axi0_s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="arradio.axi_dmac_dac_m_src_axi"
+   end="c5soc.sys_mem_interconnect_axi1_s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="c5soc.sys_cpu_interconnect_m0"
+   end="arradio.axi_ad9361_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="c5soc.sys_cpu_interconnect_m0"
+   end="arradio.axi_dmac_adc_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="c5soc.sys_cpu_interconnect_m0"
+   end="arradio.axi_dmac_dac_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x4000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="c5soc.sys_cpu_interconnect_m0"
+   end="arradio.gpio_s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x9000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="c5soc.sys_cpu_interconnect_m0"
+   end="arradio.spi_ad9361_spi_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x8000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="c5soc.sys_clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.clk" end="arradio.sys_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="c5soc.mem_clk"
+   end="arradio.mem_clk" />
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="c5soc.sys_intr"
+   end="arradio.axi_dmac_adc_intr">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="c5soc.sys_intr"
+   end="arradio.axi_dmac_dac_intr">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="c5soc.sys_intr"
+   end="arradio.spi_ad9361_irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="c5soc.sys_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_clk.clk_reset"
+   end="arradio.sys_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="c5soc.mem_rst"
+   end="arradio.mem_rst" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+ <interconnectRequirement
+   for="mm_interconnect_0|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_2|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+</system>
diff --git a/projects/arradio/c5soc/system_bd.tcl b/projects/arradio/c5soc/system_bd.tcl
deleted file mode 100644
index a9b62774a..000000000
--- a/projects/arradio/c5soc/system_bd.tcl
+++ /dev/null
@@ -1,1321 +0,0 @@
-# qsys scripting (.tcl) file for system_bd
-package require -exact qsys 16.0
-
-create_system {system_bd}
-
-set_project_property DEVICE_FAMILY {Cyclone V}
-set_project_property DEVICE {5CSXFC6D6F31C8ES}
-set_project_property HIDE_FROM_IP_CATALOG {false}
-
-# Instances and instance parameters
-# (disabled instances are intentionally culled)
-add_instance axi_ad9361 axi_ad9361 1.0
-set_instance_parameter_value axi_ad9361 {ID} {0}
-set_instance_parameter_value axi_ad9361 {MODE_1R1T} {0}
-set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {1}
-set_instance_parameter_value axi_ad9361 {TDD_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {CMOS_OR_LVDS_N} {0}
-set_instance_parameter_value axi_ad9361 {ADC_DATAPATH_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {ADC_USERPORTS_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {ADC_DATAFORMAT_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {ADC_DCFILTER_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {ADC_IQCORRECTION_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {DAC_IODELAY_ENABLE} {0}
-set_instance_parameter_value axi_ad9361 {DAC_DATAPATH_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {DAC_DDS_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {DAC_USERPORTS_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {DAC_IQCORRECTION_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {IO_DELAY_GROUP} {dev_if_delay_group}
-
-add_instance axi_adc_dma axi_dmac 1.0
-set_instance_parameter_value axi_adc_dma {ID} {0}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
-set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
-set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
-set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
-set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
-set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
-set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
-set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
-
-add_instance axi_dac_dma axi_dmac 1.0
-set_instance_parameter_value axi_dac_dma {ID} {0}
-set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {64}
-set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
-set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1}
-set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
-set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
-set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
-set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
-set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
-set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
-
-add_instance sys_clk clock_source 16.0
-set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
-set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
-set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
-
-add_instance sys_dma_clk clock_source 16.0
-set_instance_parameter_value sys_dma_clk {clockFrequency} {50000000.0}
-set_instance_parameter_value sys_dma_clk {clockFrequencyKnown} {1}
-set_instance_parameter_value sys_dma_clk {resetSynchronousEdges} {NONE}
-
-add_instance sys_gpio_bd altera_avalon_pio 16.0
-set_instance_parameter_value sys_gpio_bd {bitClearingEdgeCapReg} {0}
-set_instance_parameter_value sys_gpio_bd {bitModifyingOutReg} {0}
-set_instance_parameter_value sys_gpio_bd {captureEdge} {0}
-set_instance_parameter_value sys_gpio_bd {direction} {InOut}
-set_instance_parameter_value sys_gpio_bd {edgeType} {RISING}
-set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
-set_instance_parameter_value sys_gpio_bd {irqType} {LEVEL}
-set_instance_parameter_value sys_gpio_bd {resetValue} {0.0}
-set_instance_parameter_value sys_gpio_bd {simDoTestBenchWiring} {0}
-set_instance_parameter_value sys_gpio_bd {simDrivenValue} {0.0}
-set_instance_parameter_value sys_gpio_bd {width} {32}
-
-add_instance sys_gpio_in altera_avalon_pio 16.0
-set_instance_parameter_value sys_gpio_in {bitClearingEdgeCapReg} {0}
-set_instance_parameter_value sys_gpio_in {bitModifyingOutReg} {0}
-set_instance_parameter_value sys_gpio_in {captureEdge} {0}
-set_instance_parameter_value sys_gpio_in {direction} {Input}
-set_instance_parameter_value sys_gpio_in {edgeType} {RISING}
-set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
-set_instance_parameter_value sys_gpio_in {irqType} {LEVEL}
-set_instance_parameter_value sys_gpio_in {resetValue} {0.0}
-set_instance_parameter_value sys_gpio_in {simDoTestBenchWiring} {0}
-set_instance_parameter_value sys_gpio_in {simDrivenValue} {0.0}
-set_instance_parameter_value sys_gpio_in {width} {32}
-
-add_instance sys_gpio_out altera_avalon_pio 16.0
-set_instance_parameter_value sys_gpio_out {bitClearingEdgeCapReg} {0}
-set_instance_parameter_value sys_gpio_out {bitModifyingOutReg} {0}
-set_instance_parameter_value sys_gpio_out {captureEdge} {0}
-set_instance_parameter_value sys_gpio_out {direction} {Output}
-set_instance_parameter_value sys_gpio_out {edgeType} {RISING}
-set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
-set_instance_parameter_value sys_gpio_out {irqType} {LEVEL}
-set_instance_parameter_value sys_gpio_out {resetValue} {0.0}
-set_instance_parameter_value sys_gpio_out {simDoTestBenchWiring} {0}
-set_instance_parameter_value sys_gpio_out {simDrivenValue} {0.0}
-set_instance_parameter_value sys_gpio_out {width} {32}
-
-add_instance sys_hps altera_hps 16.0
-set_instance_parameter_value sys_hps {MEM_VENDOR} {JEDEC}
-set_instance_parameter_value sys_hps {MEM_FORMAT} {DISCRETE}
-set_instance_parameter_value sys_hps {RDIMM_CONFIG} {0000000000000000}
-set_instance_parameter_value sys_hps {LRDIMM_EXTENDED_CONFIG} {0x000000000000000000}
-set_instance_parameter_value sys_hps {DISCRETE_FLY_BY} {1}
-set_instance_parameter_value sys_hps {DEVICE_DEPTH} {1}
-set_instance_parameter_value sys_hps {MEM_MIRROR_ADDRESSING} {0}
-set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
-set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
-set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
-set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32}
-set_instance_parameter_value sys_hps {MEM_DQ_PER_DQS} {8}
-set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
-set_instance_parameter_value sys_hps {MEM_IF_DM_PINS_EN} {1}
-set_instance_parameter_value sys_hps {MEM_IF_DQSN_EN} {1}
-set_instance_parameter_value sys_hps {MEM_NUMBER_OF_DIMMS} {1}
-set_instance_parameter_value sys_hps {MEM_NUMBER_OF_RANKS_PER_DIMM} {1}
-set_instance_parameter_value sys_hps {MEM_NUMBER_OF_RANKS_PER_DEVICE} {1}
-set_instance_parameter_value sys_hps {MEM_RANK_MULTIPLICATION_FACTOR} {1}
-set_instance_parameter_value sys_hps {MEM_CK_WIDTH} {1}
-set_instance_parameter_value sys_hps {MEM_CS_WIDTH} {1}
-set_instance_parameter_value sys_hps {MEM_CLK_EN_WIDTH} {1}
-set_instance_parameter_value sys_hps {ALTMEMPHY_COMPATIBLE_MODE} {0}
-set_instance_parameter_value sys_hps {NEXTGEN} {1}
-set_instance_parameter_value sys_hps {MEM_IF_BOARD_BASE_DELAY} {10}
-set_instance_parameter_value sys_hps {MEM_IF_SIM_VALID_WINDOW} {0}
-set_instance_parameter_value sys_hps {MEM_GUARANTEED_WRITE_INIT} {0}
-set_instance_parameter_value sys_hps {MEM_VERBOSE} {1}
-set_instance_parameter_value sys_hps {PINGPONGPHY_EN} {0}
-set_instance_parameter_value sys_hps {DUPLICATE_AC} {0}
-set_instance_parameter_value sys_hps {REFRESH_BURST_VALIDATION} {0}
-set_instance_parameter_value sys_hps {AP_MODE_EN} {0}
-set_instance_parameter_value sys_hps {AP_MODE} {0}
-set_instance_parameter_value sys_hps {MEM_BL} {OTF}
-set_instance_parameter_value sys_hps {MEM_BT} {Sequential}
-set_instance_parameter_value sys_hps {MEM_ASR} {Manual}
-set_instance_parameter_value sys_hps {MEM_SRT} {Normal}
-set_instance_parameter_value sys_hps {MEM_PD} {DLL off}
-set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/7}
-set_instance_parameter_value sys_hps {MEM_DLL_EN} {1}
-set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
-set_instance_parameter_value sys_hps {MEM_RTT_WR} {RZQ/4}
-set_instance_parameter_value sys_hps {MEM_WTCL} {8}
-set_instance_parameter_value sys_hps {MEM_ATCL} {Disabled}
-set_instance_parameter_value sys_hps {MEM_TCL} {11}
-set_instance_parameter_value sys_hps {MEM_AUTO_LEVELING_MODE} {1}
-set_instance_parameter_value sys_hps {MEM_USER_LEVELING_MODE} {Leveling}
-set_instance_parameter_value sys_hps {MEM_INIT_EN} {0}
-set_instance_parameter_value sys_hps {MEM_INIT_FILE} {}
-set_instance_parameter_value sys_hps {DAT_DATA_WIDTH} {32}
-set_instance_parameter_value sys_hps {TIMING_TIS} {180}
-set_instance_parameter_value sys_hps {TIMING_TIH} {140}
-set_instance_parameter_value sys_hps {TIMING_TDS} {30}
-set_instance_parameter_value sys_hps {TIMING_TDH} {65}
-set_instance_parameter_value sys_hps {TIMING_TDQSQ} {125}
-set_instance_parameter_value sys_hps {TIMING_TQHS} {300}
-set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
-set_instance_parameter_value sys_hps {TIMING_TDQSCK} {255}
-set_instance_parameter_value sys_hps {TIMING_TDQSCKDS} {450}
-set_instance_parameter_value sys_hps {TIMING_TDQSCKDM} {900}
-set_instance_parameter_value sys_hps {TIMING_TDQSCKDL} {1200}
-set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25}
-set_instance_parameter_value sys_hps {TIMING_TDQSH} {0.35}
-set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
-set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2}
-set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2}
-set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
-set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
-set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
-set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
-set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
-set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
-set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
-set_instance_parameter_value sys_hps {CFG_TCCD_NS} {2.5}
-set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
-set_instance_parameter_value sys_hps {MEM_TWTR} {4}
-set_instance_parameter_value sys_hps {MEM_TFAW_NS} {30.0}
-set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5}
-set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
-set_instance_parameter_value sys_hps {POWER_OF_TWO_BUS} {0}
-set_instance_parameter_value sys_hps {SOPC_COMPAT_RESET} {0}
-set_instance_parameter_value sys_hps {AVL_MAX_SIZE} {4}
-set_instance_parameter_value sys_hps {BYTE_ENABLE} {1}
-set_instance_parameter_value sys_hps {ENABLE_CTRL_AVALON_INTERFACE} {1}
-set_instance_parameter_value sys_hps {CTL_DEEP_POWERDN_EN} {0}
-set_instance_parameter_value sys_hps {CTL_SELF_REFRESH_EN} {0}
-set_instance_parameter_value sys_hps {AUTO_POWERDN_EN} {0}
-set_instance_parameter_value sys_hps {AUTO_PD_CYCLES} {0}
-set_instance_parameter_value sys_hps {CTL_USR_REFRESH_EN} {0}
-set_instance_parameter_value sys_hps {CTL_AUTOPCH_EN} {0}
-set_instance_parameter_value sys_hps {CTL_ZQCAL_EN} {0}
-set_instance_parameter_value sys_hps {ADDR_ORDER} {0}
-set_instance_parameter_value sys_hps {CTL_LOOK_AHEAD_DEPTH} {4}
-set_instance_parameter_value sys_hps {CONTROLLER_LATENCY} {5}
-set_instance_parameter_value sys_hps {CFG_REORDER_DATA} {1}
-set_instance_parameter_value sys_hps {STARVE_LIMIT} {10}
-set_instance_parameter_value sys_hps {CTL_CSR_ENABLED} {0}
-set_instance_parameter_value sys_hps {CTL_CSR_CONNECTION} {INTERNAL_JTAG}
-set_instance_parameter_value sys_hps {CTL_ECC_ENABLED} {0}
-set_instance_parameter_value sys_hps {CTL_HRB_ENABLED} {0}
-set_instance_parameter_value sys_hps {CTL_ECC_AUTO_CORRECTION_ENABLED} {0}
-set_instance_parameter_value sys_hps {MULTICAST_EN} {0}
-set_instance_parameter_value sys_hps {CTL_DYNAMIC_BANK_ALLOCATION} {0}
-set_instance_parameter_value sys_hps {CTL_DYNAMIC_BANK_NUM} {4}
-set_instance_parameter_value sys_hps {DEBUG_MODE} {0}
-set_instance_parameter_value sys_hps {ENABLE_BURST_MERGE} {0}
-set_instance_parameter_value sys_hps {CTL_ENABLE_BURST_INTERRUPT} {0}
-set_instance_parameter_value sys_hps {CTL_ENABLE_BURST_TERMINATE} {0}
-set_instance_parameter_value sys_hps {LOCAL_ID_WIDTH} {8}
-set_instance_parameter_value sys_hps {WRBUFFER_ADDR_WIDTH} {6}
-set_instance_parameter_value sys_hps {MAX_PENDING_WR_CMD} {16}
-set_instance_parameter_value sys_hps {MAX_PENDING_RD_CMD} {32}
-set_instance_parameter_value sys_hps {USE_MM_ADAPTOR} {1}
-set_instance_parameter_value sys_hps {USE_AXI_ADAPTOR} {0}
-set_instance_parameter_value sys_hps {HCX_COMPAT_MODE} {0}
-set_instance_parameter_value sys_hps {CTL_CMD_QUEUE_DEPTH} {8}
-set_instance_parameter_value sys_hps {CTL_CSR_READ_ONLY} {1}
-set_instance_parameter_value sys_hps {CFG_DATA_REORDERING_TYPE} {INTER_BANK}
-set_instance_parameter_value sys_hps {NUM_OF_PORTS} {1}
-set_instance_parameter_value sys_hps {ENABLE_BONDING} {0}
-set_instance_parameter_value sys_hps {ENABLE_USER_ECC} {0}
-set_instance_parameter_value sys_hps {AVL_DATA_WIDTH_PORT} {32 32 32 32 32 32}
-set_instance_parameter_value sys_hps {PRIORITY_PORT} {1 1 1 1 1 1}
-set_instance_parameter_value sys_hps {WEIGHT_PORT} {0 0 0 0 0 0}
-set_instance_parameter_value sys_hps {CPORT_TYPE_PORT} {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional}
-set_instance_parameter_value sys_hps {ENABLE_EMIT_BFM_MASTER} {0}
-set_instance_parameter_value sys_hps {FORCE_SEQUENCER_TCL_DEBUG_MODE} {0}
-set_instance_parameter_value sys_hps {ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT} {0}
-set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
-set_instance_parameter_value sys_hps {REF_CLK_FREQ_PARAM_VALID} {0}
-set_instance_parameter_value sys_hps {REF_CLK_FREQ_MIN_PARAM} {0.0}
-set_instance_parameter_value sys_hps {REF_CLK_FREQ_MAX_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_DR_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_DR_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_DR_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_DR_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_DR_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_MEM_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_MEM_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_MEM_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_MEM_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_MEM_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_AFI_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_AFI_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_AFI_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_WRITE_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_WRITE_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_WRITE_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_WRITE_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_ADDR_CMD_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_HALF_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_NIOS_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_NIOS_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_NIOS_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_NIOS_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_NIOS_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_CONFIG_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_P2C_READ_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_C2P_WRITE_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_HR_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_HR_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_HR_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_HR_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_HR_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_FREQ_PARAM} {0.0}
-set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_PHASE_PS_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM} {}
-set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_MULT_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_AFI_PHY_CLK_DIV_PARAM} {0}
-set_instance_parameter_value sys_hps {PLL_CLK_PARAM_VALID} {0}
-set_instance_parameter_value sys_hps {ENABLE_EXTRA_REPORTING} {0}
-set_instance_parameter_value sys_hps {NUM_EXTRA_REPORT_PATH} {10}
-set_instance_parameter_value sys_hps {ENABLE_ISS_PROBES} {0}
-set_instance_parameter_value sys_hps {CALIB_REG_WIDTH} {8}
-set_instance_parameter_value sys_hps {USE_SEQUENCER_BFM} {0}
-set_instance_parameter_value sys_hps {PLL_SHARING_MODE} {None}
-set_instance_parameter_value sys_hps {NUM_PLL_SHARING_INTERFACES} {1}
-set_instance_parameter_value sys_hps {EXPORT_AFI_HALF_CLK} {0}
-set_instance_parameter_value sys_hps {ABSTRACT_REAL_COMPARE_TEST} {0}
-set_instance_parameter_value sys_hps {INCLUDE_BOARD_DELAY_MODEL} {0}
-set_instance_parameter_value sys_hps {INCLUDE_MULTIRANK_BOARD_DELAY_MODEL} {0}
-set_instance_parameter_value sys_hps {USE_FAKE_PHY} {0}
-set_instance_parameter_value sys_hps {FORCE_MAX_LATENCY_COUNT_WIDTH} {0}
-set_instance_parameter_value sys_hps {ENABLE_NON_DESTRUCTIVE_CALIB} {0}
-set_instance_parameter_value sys_hps {FIX_READ_LATENCY} {8}
-set_instance_parameter_value sys_hps {ENABLE_DELAY_CHAIN_WRITE} {0}
-set_instance_parameter_value sys_hps {TRACKING_ERROR_TEST} {0}
-set_instance_parameter_value sys_hps {TRACKING_WATCH_TEST} {0}
-set_instance_parameter_value sys_hps {MARGIN_VARIATION_TEST} {0}
-set_instance_parameter_value sys_hps {AC_ROM_USER_ADD_0} {0_0000_0000_0000}
-set_instance_parameter_value sys_hps {AC_ROM_USER_ADD_1} {0_0000_0000_1000}
-set_instance_parameter_value sys_hps {TREFI} {35100}
-set_instance_parameter_value sys_hps {REFRESH_INTERVAL} {15000}
-set_instance_parameter_value sys_hps {ENABLE_NON_DES_CAL_TEST} {0}
-set_instance_parameter_value sys_hps {TRFC} {350}
-set_instance_parameter_value sys_hps {ENABLE_NON_DES_CAL} {0}
-set_instance_parameter_value sys_hps {EXTRA_SETTINGS} {}
-set_instance_parameter_value sys_hps {MEM_DEVICE} {MISSING_MODEL}
-set_instance_parameter_value sys_hps {FORCE_SYNTHESIS_LANGUAGE} {}
-set_instance_parameter_value sys_hps {FORCED_NUM_WRITE_FR_CYCLE_SHIFTS} {0}
-set_instance_parameter_value sys_hps {SEQUENCER_TYPE} {NIOS}
-set_instance_parameter_value sys_hps {ADVERTIZE_SEQUENCER_SW_BUILD_FILES} {0}
-set_instance_parameter_value sys_hps {FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT} {0}
-set_instance_parameter_value sys_hps {PHY_ONLY} {0}
-set_instance_parameter_value sys_hps {SEQ_MODE} {0}
-set_instance_parameter_value sys_hps {ADVANCED_CK_PHASES} {0}
-set_instance_parameter_value sys_hps {COMMAND_PHASE} {0.0}
-set_instance_parameter_value sys_hps {MEM_CK_PHASE} {0.0}
-set_instance_parameter_value sys_hps {P2C_READ_CLOCK_ADD_PHASE} {0.0}
-set_instance_parameter_value sys_hps {C2P_WRITE_CLOCK_ADD_PHASE} {0.0}
-set_instance_parameter_value sys_hps {ACV_PHY_CLK_ADD_FR_PHASE} {0.0}
-set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3}
-set_instance_parameter_value sys_hps {PLL_LOCATION} {Top_Bottom}
-set_instance_parameter_value sys_hps {SKIP_MEM_INIT} {1}
-set_instance_parameter_value sys_hps {READ_DQ_DQS_CLOCK_SOURCE} {INVERTED_DQS_BUS}
-set_instance_parameter_value sys_hps {DQ_INPUT_REG_USE_CLKN} {0}
-set_instance_parameter_value sys_hps {DQS_DQSN_MODE} {DIFFERENTIAL}
-set_instance_parameter_value sys_hps {AFI_DEBUG_INFO_WIDTH} {32}
-set_instance_parameter_value sys_hps {CALIBRATION_MODE} {Skip}
-set_instance_parameter_value sys_hps {NIOS_ROM_DATA_WIDTH} {32}
-set_instance_parameter_value sys_hps {READ_FIFO_SIZE} {8}
-set_instance_parameter_value sys_hps {PHY_CSR_ENABLED} {0}
-set_instance_parameter_value sys_hps {PHY_CSR_CONNECTION} {INTERNAL_JTAG}
-set_instance_parameter_value sys_hps {USER_DEBUG_LEVEL} {1}
-set_instance_parameter_value sys_hps {TIMING_BOARD_DERATE_METHOD} {AUTO}
-set_instance_parameter_value sys_hps {TIMING_BOARD_CK_CKN_SLEW_RATE} {2.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SLEW_RATE} {1.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_DQS_DQSN_SLEW_RATE} {2.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_SLEW_RATE} {1.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_TIS} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_TIH} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_TDS} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_TDH} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_ISI_METHOD} {AUTO}
-set_instance_parameter_value sys_hps {TIMING_BOARD_AC_EYE_REDUCTION_SU} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_AC_EYE_REDUCTION_H} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_EYE_REDUCTION} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_READ_DQ_EYE_REDUCTION} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME} {0.0}
-set_instance_parameter_value sys_hps {PACKAGE_DESKEW} {0}
-set_instance_parameter_value sys_hps {AC_PACKAGE_DESKEW} {0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.03}
-set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.02}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {0.09}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.16}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DIMMS} {0.05}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.01}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.08}
-set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.03}
-set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
-set_instance_parameter_value sys_hps {RATE} {Full}
-set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
-set_instance_parameter_value sys_hps {USE_MEM_CLK_FREQ} {0}
-set_instance_parameter_value sys_hps {FORCE_DQS_TRACKING} {AUTO}
-set_instance_parameter_value sys_hps {FORCE_SHADOW_REGS} {AUTO}
-set_instance_parameter_value sys_hps {MRS_MIRROR_PING_PONG_ATSO} {0}
-set_instance_parameter_value sys_hps {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID} {0}
-set_instance_parameter_value sys_hps {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM} {}
-set_instance_parameter_value sys_hps {DEVICE_FAMILY_PARAM} {}
-set_instance_parameter_value sys_hps {SPEED_GRADE} {7}
-set_instance_parameter_value sys_hps {IS_ES_DEVICE} {0}
-set_instance_parameter_value sys_hps {DISABLE_CHILD_MESSAGING} {0}
-set_instance_parameter_value sys_hps {HARD_EMIF} {1}
-set_instance_parameter_value sys_hps {HHP_HPS} {1}
-set_instance_parameter_value sys_hps {HHP_HPS_VERIFICATION} {0}
-set_instance_parameter_value sys_hps {HHP_HPS_SIMULATION} {0}
-set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
-set_instance_parameter_value sys_hps {CUT_NEW_FAMILY_TIMING} {1}
-set_instance_parameter_value sys_hps {ENABLE_EXPORT_SEQ_DEBUG_BRIDGE} {0}
-set_instance_parameter_value sys_hps {CORE_DEBUG_CONNECTION} {EXPORT}
-set_instance_parameter_value sys_hps {ADD_EXTERNAL_SEQ_DEBUG_NIOS} {0}
-set_instance_parameter_value sys_hps {ED_EXPORT_SEQ_DEBUG} {0}
-set_instance_parameter_value sys_hps {ADD_EFFICIENCY_MONITOR} {0}
-set_instance_parameter_value sys_hps {ENABLE_ABS_RAM_MEM_INIT} {0}
-set_instance_parameter_value sys_hps {ABS_RAM_MEM_INIT_FILENAME} {meminit}
-set_instance_parameter_value sys_hps {DLL_SHARING_MODE} {None}
-set_instance_parameter_value sys_hps {NUM_DLL_SHARING_INTERFACES} {1}
-set_instance_parameter_value sys_hps {OCT_SHARING_MODE} {None}
-set_instance_parameter_value sys_hps {NUM_OCT_SHARING_INTERFACES} {1}
-set_instance_parameter_value sys_hps {show_advanced_parameters} {0}
-set_instance_parameter_value sys_hps {configure_advanced_parameters} {0}
-set_instance_parameter_value sys_hps {customize_device_pll_info} {0}
-set_instance_parameter_value sys_hps {device_pll_info_manual} {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}}
-set_instance_parameter_value sys_hps {show_debug_info_as_warning_msg} {0}
-set_instance_parameter_value sys_hps {show_warning_as_error_msg} {0}
-set_instance_parameter_value sys_hps {eosc1_clk_mhz} {25.0}
-set_instance_parameter_value sys_hps {eosc2_clk_mhz} {25.0}
-set_instance_parameter_value sys_hps {F2SCLK_SDRAMCLK_Enable} {0}
-set_instance_parameter_value sys_hps {F2SCLK_PERIPHCLK_Enable} {0}
-set_instance_parameter_value sys_hps {periph_pll_source} {0}
-set_instance_parameter_value sys_hps {sdmmc_clk_source} {2}
-set_instance_parameter_value sys_hps {nand_clk_source} {2}
-set_instance_parameter_value sys_hps {qspi_clk_source} {1}
-set_instance_parameter_value sys_hps {l4_mp_clk_source} {1}
-set_instance_parameter_value sys_hps {l4_sp_clk_source} {1}
-set_instance_parameter_value sys_hps {use_default_mpu_clk} {1}
-set_instance_parameter_value sys_hps {desired_mpu_clk_mhz} {800.0}
-set_instance_parameter_value sys_hps {l3_mp_clk_div} {1}
-set_instance_parameter_value sys_hps {l3_sp_clk_div} {1}
-set_instance_parameter_value sys_hps {dbctrl_stayosc1} {1}
-set_instance_parameter_value sys_hps {dbg_at_clk_div} {0}
-set_instance_parameter_value sys_hps {dbg_clk_div} {1}
-set_instance_parameter_value sys_hps {dbg_trace_clk_div} {0}
-set_instance_parameter_value sys_hps {desired_l4_mp_clk_mhz} {100.0}
-set_instance_parameter_value sys_hps {desired_l4_sp_clk_mhz} {100.0}
-set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
-set_instance_parameter_value sys_hps {desired_sdmmc_clk_mhz} {200.0}
-set_instance_parameter_value sys_hps {desired_nand_clk_mhz} {12.5}
-set_instance_parameter_value sys_hps {desired_qspi_clk_mhz} {400.0}
-set_instance_parameter_value sys_hps {desired_emac0_clk_mhz} {250.0}
-set_instance_parameter_value sys_hps {desired_emac1_clk_mhz} {250.0}
-set_instance_parameter_value sys_hps {desired_usb_mp_clk_mhz} {200.0}
-set_instance_parameter_value sys_hps {desired_spi_m_clk_mhz} {200.0}
-set_instance_parameter_value sys_hps {desired_can0_clk_mhz} {100.0}
-set_instance_parameter_value sys_hps {desired_can1_clk_mhz} {100.0}
-set_instance_parameter_value sys_hps {desired_gpio_db_clk_hz} {32000}
-set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
-set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
-set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_Enable} {0}
-set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
-set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
-set_instance_parameter_value sys_hps {S2FCLK_USER2CLK} {5}
-set_instance_parameter_value sys_hps {main_pll_m} {63}
-set_instance_parameter_value sys_hps {main_pll_n} {0}
-set_instance_parameter_value sys_hps {main_pll_c3} {3}
-set_instance_parameter_value sys_hps {main_pll_c4} {3}
-set_instance_parameter_value sys_hps {main_pll_c5} {15}
-set_instance_parameter_value sys_hps {periph_pll_m} {79}
-set_instance_parameter_value sys_hps {periph_pll_n} {1}
-set_instance_parameter_value sys_hps {periph_pll_c0} {3}
-set_instance_parameter_value sys_hps {periph_pll_c1} {3}
-set_instance_parameter_value sys_hps {periph_pll_c2} {1}
-set_instance_parameter_value sys_hps {periph_pll_c3} {19}
-set_instance_parameter_value sys_hps {periph_pll_c4} {4}
-set_instance_parameter_value sys_hps {periph_pll_c5} {9}
-set_instance_parameter_value sys_hps {usb_mp_clk_div} {0}
-set_instance_parameter_value sys_hps {spi_m_clk_div} {0}
-set_instance_parameter_value sys_hps {can0_clk_div} {1}
-set_instance_parameter_value sys_hps {can1_clk_div} {1}
-set_instance_parameter_value sys_hps {gpio_db_clk_div} {6249}
-set_instance_parameter_value sys_hps {l4_mp_clk_div} {1}
-set_instance_parameter_value sys_hps {l4_sp_clk_div} {1}
-set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
-set_instance_parameter_value sys_hps {GP_Enable} {0}
-set_instance_parameter_value sys_hps {DEBUGAPB_Enable} {0}
-set_instance_parameter_value sys_hps {STM_Enable} {0}
-set_instance_parameter_value sys_hps {CTI_Enable} {0}
-set_instance_parameter_value sys_hps {TPIUFPGA_Enable} {0}
-set_instance_parameter_value sys_hps {TPIUFPGA_alt} {0}
-set_instance_parameter_value sys_hps {BOOTFROMFPGA_Enable} {0}
-set_instance_parameter_value sys_hps {TEST_Enable} {0}
-set_instance_parameter_value sys_hps {HLGPI_Enable} {0}
-set_instance_parameter_value sys_hps {BSEL_EN} {0}
-set_instance_parameter_value sys_hps {BSEL} {1}
-set_instance_parameter_value sys_hps {CSEL_EN} {0}
-set_instance_parameter_value sys_hps {CSEL} {0}
-set_instance_parameter_value sys_hps {F2S_Width} {2}
-set_instance_parameter_value sys_hps {S2F_Width} {2}
-set_instance_parameter_value sys_hps {LWH2F_Enable} {true}
-set_instance_parameter_value sys_hps {F2SDRAM_Type} {Avalon-MM\ Bidirectional AXI-3 AXI-3}
-set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 64 64}
-set_instance_parameter_value sys_hps {BONDING_OUT_ENABLED} {0}
-set_instance_parameter_value sys_hps {S2FCLK_COLDRST_Enable} {0}
-set_instance_parameter_value sys_hps {S2FCLK_PENDINGRST_Enable} {0}
-set_instance_parameter_value sys_hps {F2SCLK_DBGRST_Enable} {0}
-set_instance_parameter_value sys_hps {F2SCLK_WARMRST_Enable} {0}
-set_instance_parameter_value sys_hps {F2SCLK_COLDRST_Enable} {0}
-set_instance_parameter_value sys_hps {DMA_Enable} {No No No No No No No No}
-set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_CAN_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_CTI_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_DMA_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_EMAC_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_GPIO_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_I2CEMAC_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_I2CPERIPHERAL_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_L4TIMER_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_NAND_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_OSCTIMER_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_QSPI_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_SDMMC_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_SPIMASTER_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_SPISLAVE_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_UART_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_USB_Enable} {0}
-set_instance_parameter_value sys_hps {S2FINTERRUPT_WATCHDOG_Enable} {0}
-set_instance_parameter_value sys_hps {EMAC0_PTP} {0}
-set_instance_parameter_value sys_hps {EMAC1_PTP} {0}
-set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A}
-set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
-set_instance_parameter_value sys_hps {NAND_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {NAND_Mode} {N/A}
-set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
-set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
-set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {USB0_Mode} {N/A}
-set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
-set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {SPIM0_Mode} {N/A}
-set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select}
-set_instance_parameter_value sys_hps {SPIS0_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {SPIS0_Mode} {N/A}
-set_instance_parameter_value sys_hps {SPIS1_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {SPIS1_Mode} {N/A}
-set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
-set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
-set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
-set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
-set_instance_parameter_value sys_hps {I2C1_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {I2C1_Mode} {N/A}
-set_instance_parameter_value sys_hps {I2C2_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {I2C2_Mode} {N/A}
-set_instance_parameter_value sys_hps {I2C3_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {I2C3_Mode} {N/A}
-set_instance_parameter_value sys_hps {CAN0_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {CAN0_Mode} {N/A}
-set_instance_parameter_value sys_hps {CAN1_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {CAN1_Mode} {N/A}
-set_instance_parameter_value sys_hps {TRACE_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {TRACE_Mode} {N/A}
-set_instance_parameter_value sys_hps {GPIO_Enable} {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No}
-set_instance_parameter_value sys_hps {LOANIO_Enable} {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK} {2.5}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK} {125}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK} {2.5}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK} {125}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT} {100}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK} {100}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT} {100}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT} {100}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK} {100}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK} {100}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK} {100}
-set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK} {100}
-
-add_instance sys_id altera_avalon_sysid_qsys 16.0
-set_instance_parameter_value sys_id {id} {-1395322110}
-
-add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
-set_instance_parameter_value sys_int_mem {allowInSystemMemoryContentEditor} {0}
-set_instance_parameter_value sys_int_mem {blockType} {AUTO}
-set_instance_parameter_value sys_int_mem {dataWidth} {64}
-set_instance_parameter_value sys_int_mem {dataWidth2} {32}
-set_instance_parameter_value sys_int_mem {dualPort} {0}
-set_instance_parameter_value sys_int_mem {enableDiffWidth} {0}
-set_instance_parameter_value sys_int_mem {initMemContent} {0}
-set_instance_parameter_value sys_int_mem {initializationFileName} {onchip_mem.hex}
-set_instance_parameter_value sys_int_mem {instanceID} {NONE}
-set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
-set_instance_parameter_value sys_int_mem {readDuringWriteMode} {DONT_CARE}
-set_instance_parameter_value sys_int_mem {simAllowMRAMContentsFile} {0}
-set_instance_parameter_value sys_int_mem {simMemInitOnlyFilename} {0}
-set_instance_parameter_value sys_int_mem {singleClockOperation} {0}
-set_instance_parameter_value sys_int_mem {slave1Latency} {1}
-set_instance_parameter_value sys_int_mem {slave2Latency} {1}
-set_instance_parameter_value sys_int_mem {useNonDefaultInitFile} {0}
-set_instance_parameter_value sys_int_mem {copyInitFile} {0}
-set_instance_parameter_value sys_int_mem {useShallowMemBlocks} {0}
-set_instance_parameter_value sys_int_mem {writable} {1}
-set_instance_parameter_value sys_int_mem {ecc_enabled} {0}
-set_instance_parameter_value sys_int_mem {resetrequest_enabled} {1}
-
-add_instance sys_spi altera_avalon_spi 16.0
-set_instance_parameter_value sys_spi {clockPhase} {0}
-set_instance_parameter_value sys_spi {clockPolarity} {1}
-set_instance_parameter_value sys_spi {dataWidth} {8}
-set_instance_parameter_value sys_spi {disableAvalonFlowControl} {0}
-set_instance_parameter_value sys_spi {insertDelayBetweenSlaveSelectAndSClk} {0}
-set_instance_parameter_value sys_spi {insertSync} {0}
-set_instance_parameter_value sys_spi {lsbOrderedFirst} {0}
-set_instance_parameter_value sys_spi {masterSPI} {1}
-set_instance_parameter_value sys_spi {numberOfSlaves} {1}
-set_instance_parameter_value sys_spi {syncRegDepth} {2}
-set_instance_parameter_value sys_spi {targetClockRate} {50000000.0}
-set_instance_parameter_value sys_spi {targetSlaveSelectToSClkDelay} {0.0}
-
-add_instance util_adc_pack util_cpack 1.0
-set_instance_parameter_value util_adc_pack {CHANNEL_DATA_WIDTH} {16}
-set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
-
-add_instance util_adc_wfifo util_wfifo 1.0
-set_instance_parameter_value util_adc_wfifo {NUM_OF_CHANNELS} {4}
-set_instance_parameter_value util_adc_wfifo {DIN_DATA_WIDTH} {16}
-set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
-set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
-
-add_instance util_dac_rfifo util_rfifo 1.0
-set_instance_parameter_value util_dac_rfifo {NUM_OF_CHANNELS} {4}
-set_instance_parameter_value util_dac_rfifo {DIN_DATA_WIDTH} {16}
-set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
-set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
-
-add_instance util_dac_upack util_upack 1.0
-set_instance_parameter_value util_dac_upack {CHANNEL_DATA_WIDTH} {16}
-set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
-
-add_instance vga_frame_reader alt_vip_vfr 14.0
-set_instance_parameter_value vga_frame_reader {BITS_PER_PIXEL_PER_COLOR_PLANE} {8}
-set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_PARALLEL} {4}
-set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_SEQUENCE} {1}
-set_instance_parameter_value vga_frame_reader {MAX_IMAGE_WIDTH} {1360}
-set_instance_parameter_value vga_frame_reader {MAX_IMAGE_HEIGHT} {768}
-set_instance_parameter_value vga_frame_reader {MEM_PORT_WIDTH} {128}
-set_instance_parameter_value vga_frame_reader {RMASTER_FIFO_DEPTH} {64}
-set_instance_parameter_value vga_frame_reader {RMASTER_BURST_TARGET} {32}
-set_instance_parameter_value vga_frame_reader {CLOCKS_ARE_SEPARATE} {1}
-
-add_instance vga_out_clock altera_clock_bridge 16.0
-set_instance_parameter_value vga_out_clock {EXPLICIT_CLOCK_RATE} {0.0}
-set_instance_parameter_value vga_out_clock {NUM_CLOCK_OUTPUTS} {1}
-
-add_instance vga_out_data alt_vip_itc 14.0
-set_instance_parameter_value vga_out_data {NUMBER_OF_COLOUR_PLANES} {4}
-set_instance_parameter_value vga_out_data {COLOUR_PLANES_ARE_IN_PARALLEL} {1}
-set_instance_parameter_value vga_out_data {BPS} {8}
-set_instance_parameter_value vga_out_data {INTERLACED} {0}
-set_instance_parameter_value vga_out_data {H_ACTIVE_PIXELS} {1360}
-set_instance_parameter_value vga_out_data {V_ACTIVE_LINES} {768}
-set_instance_parameter_value vga_out_data {ACCEPT_COLOURS_IN_SEQ} {0}
-set_instance_parameter_value vga_out_data {FIFO_DEPTH} {1920}
-set_instance_parameter_value vga_out_data {CLOCKS_ARE_SAME} {0}
-set_instance_parameter_value vga_out_data {USE_CONTROL} {0}
-set_instance_parameter_value vga_out_data {NO_OF_MODES} {1}
-set_instance_parameter_value vga_out_data {THRESHOLD} {1919}
-set_instance_parameter_value vga_out_data {STD_WIDTH} {1}
-set_instance_parameter_value vga_out_data {GENERATE_SYNC} {0}
-set_instance_parameter_value vga_out_data {USE_EMBEDDED_SYNCS} {0}
-set_instance_parameter_value vga_out_data {AP_LINE} {0}
-set_instance_parameter_value vga_out_data {V_BLANK} {0}
-set_instance_parameter_value vga_out_data {H_BLANK} {0}
-set_instance_parameter_value vga_out_data {H_SYNC_LENGTH} {112}
-set_instance_parameter_value vga_out_data {H_FRONT_PORCH} {64}
-set_instance_parameter_value vga_out_data {H_BACK_PORCH} {256}
-set_instance_parameter_value vga_out_data {V_SYNC_LENGTH} {6}
-set_instance_parameter_value vga_out_data {V_FRONT_PORCH} {3}
-set_instance_parameter_value vga_out_data {V_BACK_PORCH} {18}
-set_instance_parameter_value vga_out_data {F_RISING_EDGE} {0}
-set_instance_parameter_value vga_out_data {F_FALLING_EDGE} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_RISING_EDGE} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_BLANK} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_SYNC_LENGTH} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_FRONT_PORCH} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_BACK_PORCH} {0}
-set_instance_parameter_value vga_out_data {ANC_LINE} {0}
-set_instance_parameter_value vga_out_data {FIELD0_ANC_LINE} {0}
-
-add_instance vga_pll altera_pll 16.0
-set_instance_parameter_value vga_pll {debug_print_output} {0}
-set_instance_parameter_value vga_pll {debug_use_rbc_taf_method} {0}
-set_instance_parameter_value vga_pll {gui_device_speed_grade} {2}
-set_instance_parameter_value vga_pll {gui_pll_mode} {Integer-N PLL}
-set_instance_parameter_value vga_pll {gui_reference_clock_frequency} {50.0}
-set_instance_parameter_value vga_pll {gui_channel_spacing} {0.0}
-set_instance_parameter_value vga_pll {gui_operation_mode} {direct}
-set_instance_parameter_value vga_pll {gui_feedback_clock} {Global Clock}
-set_instance_parameter_value vga_pll {gui_fractional_cout} {32}
-set_instance_parameter_value vga_pll {gui_dsm_out_sel} {1st_order}
-set_instance_parameter_value vga_pll {gui_use_locked} {0}
-set_instance_parameter_value vga_pll {gui_en_adv_params} {0}
-set_instance_parameter_value vga_pll {gui_number_of_clocks} {2}
-set_instance_parameter_value vga_pll {gui_multiply_factor} {1}
-set_instance_parameter_value vga_pll {gui_frac_multiply_factor} {1.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_n} {1}
-set_instance_parameter_value vga_pll {gui_cascade_counter0} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency0} {85.5}
-set_instance_parameter_value vga_pll {gui_divide_factor_c0} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency0} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units0} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift0} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg0} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift0} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle0} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter1} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency1} {171.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c1} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency1} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units1} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift1} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg1} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift1} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle1} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter2} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency2} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c2} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency2} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units2} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift2} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg2} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift2} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle2} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter3} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency3} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c3} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency3} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units3} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift3} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg3} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift3} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle3} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter4} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency4} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c4} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency4} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units4} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift4} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg4} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift4} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle4} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter5} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency5} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c5} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency5} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units5} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift5} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg5} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift5} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle5} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter6} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency6} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c6} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency6} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units6} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift6} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg6} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift6} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle6} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter7} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency7} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c7} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency7} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units7} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift7} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg7} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift7} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle7} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter8} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency8} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c8} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency8} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units8} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift8} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg8} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift8} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle8} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter9} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency9} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c9} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency9} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units9} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift9} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg9} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift9} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle9} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter10} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency10} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c10} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency10} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units10} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift10} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg10} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift10} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle10} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter11} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency11} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c11} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency11} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units11} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift11} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg11} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift11} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle11} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter12} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency12} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c12} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency12} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units12} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift12} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg12} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift12} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle12} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter13} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency13} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c13} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency13} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units13} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift13} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg13} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift13} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle13} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter14} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency14} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c14} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency14} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units14} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift14} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg14} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift14} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle14} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter15} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency15} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c15} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency15} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units15} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift15} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg15} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift15} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle15} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter16} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency16} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c16} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency16} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units16} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift16} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg16} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift16} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle16} {50}
-set_instance_parameter_value vga_pll {gui_cascade_counter17} {0}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency17} {100.0}
-set_instance_parameter_value vga_pll {gui_divide_factor_c17} {1}
-set_instance_parameter_value vga_pll {gui_actual_output_clock_frequency17} {0 MHz}
-set_instance_parameter_value vga_pll {gui_ps_units17} {ps}
-set_instance_parameter_value vga_pll {gui_phase_shift17} {0}
-set_instance_parameter_value vga_pll {gui_phase_shift_deg17} {0.0}
-set_instance_parameter_value vga_pll {gui_actual_phase_shift17} {0}
-set_instance_parameter_value vga_pll {gui_duty_cycle17} {50}
-set_instance_parameter_value vga_pll {gui_pll_auto_reset} {Off}
-set_instance_parameter_value vga_pll {gui_pll_bandwidth_preset} {Auto}
-set_instance_parameter_value vga_pll {gui_en_reconf} {0}
-set_instance_parameter_value vga_pll {gui_en_dps_ports} {0}
-set_instance_parameter_value vga_pll {gui_en_phout_ports} {0}
-set_instance_parameter_value vga_pll {gui_phout_division} {1}
-set_instance_parameter_value vga_pll {gui_mif_generate} {0}
-set_instance_parameter_value vga_pll {gui_enable_mif_dps} {0}
-set_instance_parameter_value vga_pll {gui_dps_cntr} {C0}
-set_instance_parameter_value vga_pll {gui_dps_num} {1}
-set_instance_parameter_value vga_pll {gui_dps_dir} {Positive}
-set_instance_parameter_value vga_pll {gui_refclk_switch} {0}
-set_instance_parameter_value vga_pll {gui_refclk1_frequency} {100.0}
-set_instance_parameter_value vga_pll {gui_switchover_mode} {Automatic Switchover}
-set_instance_parameter_value vga_pll {gui_switchover_delay} {0}
-set_instance_parameter_value vga_pll {gui_active_clk} {0}
-set_instance_parameter_value vga_pll {gui_clk_bad} {0}
-set_instance_parameter_value vga_pll {gui_enable_cascade_out} {0}
-set_instance_parameter_value vga_pll {gui_cascade_outclk_index} {0}
-set_instance_parameter_value vga_pll {gui_enable_cascade_in} {0}
-set_instance_parameter_value vga_pll {gui_pll_cascading_mode} {Create an adjpllin signal to connect with an upstream PLL}
-
-# exported interfaces
-add_interface axi_ad9361_device_if conduit end
-set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
-add_interface axi_ad9361_up_enable conduit end
-set_interface_property axi_ad9361_up_enable EXPORT_OF axi_ad9361.if_up_enable
-add_interface axi_ad9361_up_txnrx conduit end
-set_interface_property axi_ad9361_up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
-add_interface sys_clk clock sink
-set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
-add_interface sys_gpio_bd conduit end
-set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
-add_interface sys_gpio_in conduit end
-set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
-add_interface sys_gpio_out conduit end
-set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
-add_interface sys_hps_h2f_reset reset source
-set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset
-add_interface sys_hps_hps_io conduit end
-set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io
-add_interface sys_hps_memory conduit end
-set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory
-add_interface sys_rst reset sink
-set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
-add_interface sys_spi conduit end
-set_interface_property sys_spi EXPORT_OF sys_spi.external
-add_interface vga_out_clk clock source
-set_interface_property vga_out_clk EXPORT_OF vga_out_clock.out_clk
-add_interface vga_out_data conduit end
-set_interface_property vga_out_data EXPORT_OF vga_out_data.clocked_video
-add_interface sys_hps_i2c0 conduit end
-set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
-add_interface sys_hps_i2c0_clk clock source
-set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
-add_interface sys_hps_i2c0_scl_in clock sink
-set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
-
-# connections and connection parameters
-add_connection vga_frame_reader.avalon_master sys_hps.f2h_sdram0_data
-set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data arbitrationPriority {1}
-set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data baseAddress {0x0000}
-set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data defaultConnection {0}
-
-add_connection sys_hps.h2f_axi_master sys_int_mem.s1
-set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000}
-set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master vga_frame_reader.avalon_slave
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/vga_frame_reader.avalon_slave arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/vga_frame_reader.avalon_slave baseAddress {0x9000}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/vga_frame_reader.avalon_slave defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master sys_id.control_slave
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_id.control_slave arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_id.control_slave baseAddress {0x00010000}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_id.control_slave defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master sys_gpio_bd.s1
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_bd.s1 arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_bd.s1 baseAddress {0x00010080}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_bd.s1 defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master sys_gpio_in.s1
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_in.s1 arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_in.s1 baseAddress {0x00010100}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_in.s1 defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master sys_gpio_out.s1
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_out.s1 arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_out.s1 baseAddress {0x00109000}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_gpio_out.s1 defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master axi_ad9361.s_axi
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_ad9361.s_axi arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_ad9361.s_axi baseAddress {0x00120000}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_ad9361.s_axi defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master axi_adc_dma.s_axi
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_adc_dma.s_axi arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_adc_dma.s_axi baseAddress {0x00100000}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_adc_dma.s_axi defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master axi_dac_dma.s_axi
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_dac_dma.s_axi arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_dac_dma.s_axi baseAddress {0x00104000}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/axi_dac_dma.s_axi defaultConnection {0}
-
-add_connection sys_hps.h2f_lw_axi_master sys_spi.spi_control_port
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_spi.spi_control_port arbitrationPriority {1}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_spi.spi_control_port baseAddress {0x00108000}
-set_connection_parameter_value sys_hps.h2f_lw_axi_master/sys_spi.spi_control_port defaultConnection {0}
-
-add_connection axi_adc_dma.m_dest_axi sys_hps.f2h_sdram2_data
-set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_hps.f2h_sdram2_data arbitrationPriority {1}
-set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_hps.f2h_sdram2_data baseAddress {0x0000}
-set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_hps.f2h_sdram2_data defaultConnection {0}
-
-add_connection axi_dac_dma.m_src_axi sys_hps.f2h_sdram1_data
-set_connection_parameter_value axi_dac_dma.m_src_axi/sys_hps.f2h_sdram1_data arbitrationPriority {1}
-set_connection_parameter_value axi_dac_dma.m_src_axi/sys_hps.f2h_sdram1_data baseAddress {0x0000}
-set_connection_parameter_value axi_dac_dma.m_src_axi/sys_hps.f2h_sdram1_data defaultConnection {0}
-
-add_connection vga_frame_reader.avalon_streaming_source vga_out_data.din
-
-add_connection sys_clk.clk sys_id.clk
-
-add_connection sys_clk.clk sys_gpio_bd.clk
-
-add_connection sys_clk.clk sys_gpio_in.clk
-
-add_connection sys_clk.clk sys_gpio_out.clk
-
-add_connection sys_clk.clk sys_spi.clk
-
-add_connection sys_clk.clk sys_int_mem.clk1
-
-add_connection sys_clk.clk vga_frame_reader.clock_master
-
-add_connection sys_clk.clk sys_hps.f2h_axi_clock
-
-add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
-
-add_connection sys_dma_clk.clk sys_hps.f2h_sdram1_clock
-
-add_connection sys_dma_clk.clk sys_hps.f2h_sdram2_clock
-
-add_connection sys_clk.clk sys_hps.h2f_axi_clock
-
-add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
-
-add_connection sys_dma_clk.clk util_adc_pack.if_adc_clk
-
-add_connection sys_dma_clk.clk util_dac_upack.if_dac_clk
-
-add_connection sys_clk.clk axi_ad9361.if_delay_clk
-
-add_connection sys_dma_clk.clk util_dac_rfifo.if_din_clk
-
-add_connection sys_dma_clk.clk util_adc_wfifo.if_dout_clk
-
-add_connection sys_dma_clk.clk axi_dac_dma.if_fifo_rd_clk
-
-add_connection sys_dma_clk.clk axi_adc_dma.if_fifo_wr_clk
-
-add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
-
-add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
-
-add_connection sys_clk.clk vga_pll.refclk
-
-add_connection sys_clk.clk axi_ad9361.s_axi_clock
-
-add_connection sys_clk.clk axi_adc_dma.s_axi_clock
-
-add_connection sys_clk.clk axi_dac_dma.s_axi_clock
-
-add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
-
-add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk
-
-add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
-
-add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
-
-add_connection vga_pll.outclk0 vga_frame_reader.clock_reset
-
-add_connection vga_pll.outclk0 vga_out_clock.in_clk
-
-add_connection vga_pll.outclk0 vga_out_data.is_clk_rst
-
-add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
-set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 endPort {}
-set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 endPortLSB {0}
-set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 startPort {}
-set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 startPortLSB {0}
-set_connection_parameter_value axi_ad9361.adc_ch_0/util_adc_wfifo.din_0 width {0}
-
-add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
-set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 endPort {}
-set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 endPortLSB {0}
-set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 startPort {}
-set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 startPortLSB {0}
-set_connection_parameter_value axi_ad9361.adc_ch_1/util_adc_wfifo.din_1 width {0}
-
-add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
-set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 endPort {}
-set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 endPortLSB {0}
-set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 startPort {}
-set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 startPortLSB {0}
-set_connection_parameter_value axi_ad9361.adc_ch_2/util_adc_wfifo.din_2 width {0}
-
-add_connection axi_ad9361.adc_ch_3 util_adc_wfifo.din_3
-set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 endPort {}
-set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 endPortLSB {0}
-set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 startPort {}
-set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 startPortLSB {0}
-set_connection_parameter_value axi_ad9361.adc_ch_3/util_adc_wfifo.din_3 width {0}
-
-add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
-set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 endPort {}
-set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 endPortLSB {0}
-set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 startPort {}
-set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 startPortLSB {0}
-set_connection_parameter_value util_dac_upack.dac_ch_0/util_dac_rfifo.din_0 width {0}
-
-add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
-set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 endPort {}
-set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 endPortLSB {0}
-set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 startPort {}
-set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 startPortLSB {0}
-set_connection_parameter_value util_dac_upack.dac_ch_1/util_dac_rfifo.din_1 width {0}
-
-add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
-set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 endPort {}
-set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 endPortLSB {0}
-set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 startPort {}
-set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 startPortLSB {0}
-set_connection_parameter_value util_dac_upack.dac_ch_2/util_dac_rfifo.din_2 width {0}
-
-add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
-set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 endPort {}
-set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 endPortLSB {0}
-set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 startPort {}
-set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 startPortLSB {0}
-set_connection_parameter_value util_dac_upack.dac_ch_3/util_dac_rfifo.din_3 width {0}
-
-add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
-set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 endPort {}
-set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 endPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 startPort {}
-set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 startPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.dout_0/util_adc_pack.adc_ch_0 width {0}
-
-add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
-set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 endPort {}
-set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 endPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 startPort {}
-set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 startPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.dout_0/axi_ad9361.dac_ch_0 width {0}
-
-add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
-set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 endPort {}
-set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 endPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 startPort {}
-set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 startPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.dout_1/util_adc_pack.adc_ch_1 width {0}
-
-add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
-set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 endPort {}
-set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 endPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 startPort {}
-set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 startPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.dout_1/axi_ad9361.dac_ch_1 width {0}
-
-add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
-set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 endPort {}
-set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 endPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 startPort {}
-set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 startPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.dout_2/util_adc_pack.adc_ch_2 width {0}
-
-add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
-set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 endPort {}
-set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 endPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 startPort {}
-set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 startPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.dout_2/axi_ad9361.dac_ch_2 width {0}
-
-add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
-set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 endPort {}
-set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 endPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 startPort {}
-set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 startPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.dout_3/util_adc_pack.adc_ch_3 width {0}
-
-add_connection util_dac_rfifo.dout_3 axi_ad9361.dac_ch_3
-set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 endPort {}
-set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 endPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 startPort {}
-set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 startPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.dout_3/axi_ad9361.dac_ch_3 width {0}
-
-add_connection util_adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
-set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din endPort {}
-set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din endPortLSB {0}
-set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din startPort {}
-set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din startPortLSB {0}
-set_connection_parameter_value util_adc_pack.if_adc_data/axi_adc_dma.if_fifo_wr_din width {0}
-
-add_connection util_adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
-set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync endPort {}
-set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync endPortLSB {0}
-set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync startPort {}
-set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync startPortLSB {0}
-set_connection_parameter_value util_adc_pack.if_adc_sync/axi_adc_dma.if_fifo_wr_sync width {0}
-
-add_connection util_adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
-set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en endPort {}
-set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en endPortLSB {0}
-set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en startPort {}
-set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en startPortLSB {0}
-set_connection_parameter_value util_adc_pack.if_adc_valid/axi_adc_dma.if_fifo_wr_en width {0}
-
-add_connection util_dac_upack.if_dac_valid axi_dac_dma.if_fifo_rd_en
-set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en endPort {}
-set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en endPortLSB {0}
-set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en startPort {}
-set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en startPortLSB {0}
-set_connection_parameter_value util_dac_upack.if_dac_valid/axi_dac_dma.if_fifo_rd_en width {0}
-
-add_connection util_adc_wfifo.if_din_ovf axi_ad9361.if_adc_dovf
-set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf endPort {}
-set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf endPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf startPort {}
-set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf startPortLSB {0}
-set_connection_parameter_value util_adc_wfifo.if_din_ovf/axi_ad9361.if_adc_dovf width {0}
-
-add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
-set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf endPort {}
-set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf endPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf startPort {}
-set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf startPortLSB {0}
-set_connection_parameter_value util_dac_rfifo.if_dout_unf/axi_ad9361.if_dac_dunf width {0}
-
-add_connection axi_dac_dma.if_fifo_rd_dout util_dac_upack.if_dac_data
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data endPort {}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data endPortLSB {0}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data startPort {}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data startPortLSB {0}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_dout/util_dac_upack.if_dac_data width {0}
-
-add_connection axi_dac_dma.if_fifo_rd_underflow util_dac_rfifo.if_din_unf
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf endPort {}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf endPortLSB {0}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf startPort {}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf startPortLSB {0}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_underflow/util_dac_rfifo.if_din_unf width {0}
-
-add_connection axi_dac_dma.if_fifo_rd_xfer_req util_dac_upack.if_dma_xfer_in
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in endPort {}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in endPortLSB {0}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in startPort {}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in startPortLSB {0}
-set_connection_parameter_value axi_dac_dma.if_fifo_rd_xfer_req/util_dac_upack.if_dma_xfer_in width {0}
-
-add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_wfifo.if_dout_ovf
-set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf endPort {}
-set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf endPortLSB {0}
-set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf startPort {}
-set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf startPortLSB {0}
-set_connection_parameter_value axi_adc_dma.if_fifo_wr_overflow/util_adc_wfifo.if_dout_ovf width {0}
-
-add_connection sys_hps.f2h_irq0 vga_frame_reader.interrupt_sender
-set_connection_parameter_value sys_hps.f2h_irq0/vga_frame_reader.interrupt_sender irqNumber {4}
-
-add_connection sys_hps.f2h_irq0 axi_adc_dma.interrupt_sender
-set_connection_parameter_value sys_hps.f2h_irq0/axi_adc_dma.interrupt_sender irqNumber {2}
-
-add_connection sys_hps.f2h_irq0 axi_dac_dma.interrupt_sender
-set_connection_parameter_value sys_hps.f2h_irq0/axi_dac_dma.interrupt_sender irqNumber {3}
-
-add_connection sys_hps.f2h_irq0 sys_gpio_bd.irq
-set_connection_parameter_value sys_hps.f2h_irq0/sys_gpio_bd.irq irqNumber {0}
-
-add_connection sys_hps.f2h_irq0 sys_spi.irq
-set_connection_parameter_value sys_hps.f2h_irq0/sys_spi.irq irqNumber {1}
-
-add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
-
-add_connection sys_clk.clk_reset vga_frame_reader.clock_master_reset
-
-add_connection sys_clk.clk_reset vga_frame_reader.clock_reset_reset
-
-add_connection sys_dma_clk.clk_reset util_adc_pack.if_adc_rst
-
-add_connection sys_dma_clk.clk_reset util_dac_rfifo.if_din_rstn
-
-add_connection sys_dma_clk.clk_reset util_adc_wfifo.if_dout_rstn
-
-add_connection sys_clk.clk_reset vga_out_data.is_clk_rst_reset
-
-add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
-
-add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
-
-add_connection sys_clk.clk_reset vga_pll.reset
-
-add_connection sys_clk.clk_reset sys_id.reset
-
-add_connection sys_clk.clk_reset sys_gpio_bd.reset
-
-add_connection sys_clk.clk_reset sys_gpio_in.reset
-
-add_connection sys_clk.clk_reset sys_gpio_out.reset
-
-add_connection sys_clk.clk_reset sys_spi.reset
-
-add_connection sys_clk.clk_reset sys_int_mem.reset1
-
-add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
-
-add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
-
-add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
-
-add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
-
-add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
-
-# interconnect requirements
-set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {FIFO}
-set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {2}
-
-save_system {system_bd.qsys}
diff --git a/projects/arradio/c5soc/system_constr.sdc b/projects/arradio/c5soc/system_constr.sdc
index a641e75ca..26a1241ec 100644
--- a/projects/arradio/c5soc/system_constr.sdc
+++ b/projects/arradio/c5soc/system_constr.sdc
@@ -1,77 +1,58 @@
 
-create_clock -period "20.000 ns" -name sys_clk  [get_ports {sys_clk}]
-create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}]
+create_clock -period "20.000 ns" -name clk_50m  [get_ports {sys_clk}]
+create_clock -period  "4.000 ns" -name clk_250m [get_ports {rx_clk_in}]
+create_clock -period "12.500 ns" -name clk_80m  [get_pins {i_system_bd|c5soc|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
 
 derive_pll_clocks
 derive_clock_uncertainty
 
+set clk_125m [get_clocks {i_system_bd|arradio|axi_ad9361|i_dev_if|i_rx|i_altlvds_rx|auto_generated|pll_sclk~PLL_OUTPUT_COUNTER|divclk}]
+
+set clk_vga [get_clocks {i_system_bd|c5soc|vga_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
+
+set_false_path -from clk_50m     -to clk_80m
+set_false_path -from clk_50m     -to $clk_125m
+set_false_path -from clk_80m     -to clk_50m 
+set_false_path -from clk_80m     -to $clk_125m
+set_false_path -from $clk_125m   -to clk_50m 
+set_false_path -from $clk_125m   -to clk_80m 
+set_false_path -from clk_50m     -to $clk_vga
+set_false_path -from $clk_vga    -to clk_50m
+
 create_clock -period 4.0 -name v_rx_clk
 
-set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_frame_in}]
-set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
-set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
-set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
-set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
-set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
-set_input_delay -add_delay -rise -max  1.2  -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
-set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_frame_in}]
-set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
-set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
-set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
-set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
-set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
-set_input_delay -add_delay -rise -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
-set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_frame_in}]  
-set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
-set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
-set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
-set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
-set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
-set_input_delay -add_delay -fall -max  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
-set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_frame_in}]  
-set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
-set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
-set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
-set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
-set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
-set_input_delay -add_delay -fall -min  0.2  -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
+set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_frame_in}]
+set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[0]}]
+set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[1]}]
+set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[2]}]
+set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[3]}]
+set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[4]}]
+set_input_delay   -clock {v_rx_clk} -max  1.2 [get_ports {rx_data_in[5]}]
+set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_frame_in}]     -clock_fall -add_delay
+set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[0]}]   -clock_fall -add_delay
+set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[1]}]   -clock_fall -add_delay
+set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[2]}]   -clock_fall -add_delay
+set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[3]}]   -clock_fall -add_delay
+set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[4]}]   -clock_fall -add_delay
+set_input_delay   -clock {v_rx_clk} -min  0.2 [get_ports {rx_data_in[5]}]   -clock_fall -add_delay
 
-create_generated_clock -name v_tx_clk_reg \
-  -source [get_pins -hierarchical *counter\[0\]*divclk*] \
-  [get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*]
-
-create_generated_clock -name v_tx_clk \
-  -source [get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*] \
-  [get_ports {tx_clk_out}]
-
-set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
-set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
-set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
-set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
-set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
-set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
-set_output_delay -add_delay -rise -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
-set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
-set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
-set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
-set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
-set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
-set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
-set_output_delay -add_delay -rise -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
-set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
-set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
-set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
-set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
-set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
-set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
-set_output_delay -add_delay -fall -max  1.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
-set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
-set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
-set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
-set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
-set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
-set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
-set_output_delay -add_delay -fall -min  0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
+create_generated_clock -source [get_ports {rx_clk_in}] -name v_tx_clk [get_ports {tx_clk_out}] -phase 90
 
+set_false_path -from clk_250m    -to v_tx_clk
+set_false_path -from v_tx_clk    -to clk_250m
 
+set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_frame_out}]
+set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[0]}]
+set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[1]}]
+set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[2]}]
+set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[3]}]
+set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[4]}]
+set_output_delay  -clock {v_tx_clk} -max  1.2 [get_ports {tx_data_out[5]}]
+set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_frame_out}]    -clock_fall -add_delay
+set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[0]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[1]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[2]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[3]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[4]}]  -clock_fall -add_delay
+set_output_delay  -clock {v_tx_clk} -min  0.2 [get_ports {tx_data_out[5]}]  -clock_fall -add_delay
 
diff --git a/projects/arradio/c5soc/system_project.tcl b/projects/arradio/c5soc/system_project.tcl
index 2c23d8a4c..9c3eb0d9a 100644
--- a/projects/arradio/c5soc/system_project.tcl
+++ b/projects/arradio/c5soc/system_project.tcl
@@ -5,45 +5,16 @@ source ../../scripts/adi_env.tcl
 project_new arradio_c5soc -overwrite
 
 source "../../common/c5soc/c5soc_system_assign.tcl"
-
+set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
+set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
 set_global_assignment -name QSYS_FILE system_bd.qsys
+
+set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
 set_global_assignment -name VERILOG_FILE system_top.v
+
 set_global_assignment -name SDC_FILE system_constr.sdc
 set_global_assignment -name TOP_LEVEL_ENTITY system_top
 
-set_location_assignment PIN_H15 -to rx_clk_in
-set_location_assignment PIN_G15 -to "rx_clk_in(n)"
-set_location_assignment PIN_F13 -to rx_frame_in
-set_location_assignment PIN_E13 -to "rx_frame_in(n)"
-set_location_assignment PIN_D11 -to rx_data_in[0]
-set_location_assignment PIN_D10 -to "rx_data_in[0](n)"
-set_location_assignment PIN_E12 -to rx_data_in[1]
-set_location_assignment PIN_D12 -to "rx_data_in[1](n)"
-set_location_assignment PIN_E9  -to rx_data_in[2]
-set_location_assignment PIN_D9  -to "rx_data_in[2](n)"
-set_location_assignment PIN_B6  -to rx_data_in[3]
-set_location_assignment PIN_B5  -to "rx_data_in[3](n)"
-set_location_assignment PIN_F11 -to rx_data_in[4]
-set_location_assignment PIN_E11 -to "rx_data_in[4](n)"
-set_location_assignment PIN_C13 -to rx_data_in[5]
-set_location_assignment PIN_B12 -to "rx_data_in[5](n)"
-set_location_assignment PIN_A11 -to tx_clk_out
-set_location_assignment PIN_A10 -to "tx_clk_out(n)"
-set_location_assignment PIN_E3  -to tx_frame_out
-set_location_assignment PIN_E2  -to "tx_frame_out(n)"
-set_location_assignment PIN_E1  -to tx_data_out[0]
-set_location_assignment PIN_D1  -to "tx_data_out[0](n)"
-set_location_assignment PIN_D2  -to tx_data_out[1]
-set_location_assignment PIN_C2  -to "tx_data_out[1](n)"
-set_location_assignment PIN_C3  -to tx_data_out[2]
-set_location_assignment PIN_B3  -to "tx_data_out[2](n)"
-set_location_assignment PIN_B2  -to tx_data_out[3]
-set_location_assignment PIN_B1  -to "tx_data_out[3](n)"
-set_location_assignment PIN_A4  -to tx_data_out[4]
-set_location_assignment PIN_A3  -to "tx_data_out[4](n)"
-set_location_assignment PIN_E4  -to tx_data_out[5]
-set_location_assignment PIN_D4  -to "tx_data_out[5](n)"
-
 set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
 set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
 set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
@@ -70,40 +41,73 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[3]
 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[4]
 set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[5]
 
-set_location_assignment PIN_B11 -to enable
-set_location_assignment PIN_C12 -to txnrx
-set_instance_assignment -name IO_STANDARD "2.5 V" -to enable
-set_instance_assignment -name IO_STANDARD "2.5 V" -to txnrx
+set_location_assignment PIN_H15 -to rx_clk_in
+set_location_assignment PIN_G15 -to "rx_clk_in(n)"
+set_location_assignment PIN_F13 -to rx_frame_in
+set_location_assignment PIN_E13 -to "rx_frame_in(n)"
+set_location_assignment PIN_D11 -to rx_data_in[0]
+set_location_assignment PIN_D10 -to "rx_data_in[0](n)"
+set_location_assignment PIN_E12 -to rx_data_in[1]
+set_location_assignment PIN_D12 -to "rx_data_in[1](n)"
+set_location_assignment PIN_E9  -to rx_data_in[2]
+set_location_assignment PIN_D9  -to "rx_data_in[2](n)"
+set_location_assignment PIN_B6  -to rx_data_in[3]
+set_location_assignment PIN_B5  -to "rx_data_in[3](n)"
+set_location_assignment PIN_F11 -to rx_data_in[4]
+set_location_assignment PIN_E11 -to "rx_data_in[4](n)"
+set_location_assignment PIN_C13 -to rx_data_in[5]
+set_location_assignment PIN_B12 -to "rx_data_in[5](n)"
+
+set_location_assignment PIN_A11 -to tx_clk_out
+set_location_assignment PIN_A10 -to "tx_clk_out(n)"
+set_location_assignment PIN_E3  -to tx_frame_out
+set_location_assignment PIN_E2  -to "tx_frame_out(n)"
+set_location_assignment PIN_E1  -to tx_data_out[0]
+set_location_assignment PIN_D1  -to "tx_data_out[0](n)"
+set_location_assignment PIN_D2  -to tx_data_out[1]
+set_location_assignment PIN_C2  -to "tx_data_out[1](n)"
+set_location_assignment PIN_C3  -to tx_data_out[2]
+set_location_assignment PIN_B3  -to "tx_data_out[2](n)"
+set_location_assignment PIN_B2  -to tx_data_out[3]
+set_location_assignment PIN_B1  -to "tx_data_out[3](n)"
+set_location_assignment PIN_A4  -to tx_data_out[4]
+set_location_assignment PIN_A3  -to "tx_data_out[4](n)"
+set_location_assignment PIN_E4  -to tx_data_out[5]
+set_location_assignment PIN_D4  -to "tx_data_out[5](n)"
 
-set_location_assignment PIN_C4  -to ad9361_resetb
-set_location_assignment PIN_C5  -to ad9361_en_agc
-set_location_assignment PIN_D5  -to ad9361_sync
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_resetb
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_en_agc
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_sync
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_enable
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_txnrx
 
-set_location_assignment PIN_A8  -to spi_csn
-set_location_assignment PIN_H12 -to spi_clk
-set_location_assignment PIN_H13 -to spi_mosi
-set_location_assignment PIN_G11 -to spi_miso
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_mosi
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_miso
 
-set_location_assignment PIN_F15 -to scl
-set_location_assignment PIN_G13 -to sda
-set_location_assignment PIN_C7  -to ga0
-set_location_assignment PIN_H14 -to ga1
+set_location_assignment PIN_C4  -to ad9361_resetb
+set_location_assignment PIN_C5  -to ad9361_en_agc
+set_location_assignment PIN_D5  -to ad9361_sync
+set_location_assignment PIN_B11 -to ad9361_enable
+set_location_assignment PIN_C12 -to ad9361_txnrx
+set_location_assignment PIN_A8  -to spi_csn
+set_location_assignment PIN_H12 -to spi_clk
+set_location_assignment PIN_H13 -to spi_mosi
+set_location_assignment PIN_G11 -to spi_miso
+
 set_instance_assignment -name IO_STANDARD "2.5 V" -to scl
 set_instance_assignment -name IO_STANDARD "2.5 V" -to sda
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ga0
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ga1
 
+set_location_assignment PIN_F15 -to scl
+set_location_assignment PIN_G13 -to sda
+set_location_assignment PIN_C7  -to ga0
+set_location_assignment PIN_H14 -to ga1
+
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to scl
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sda
 
-set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity axi_ad9361
-
 execute_flow -compile
 
diff --git a/projects/arradio/c5soc/system_qsys.tcl b/projects/arradio/c5soc/system_qsys.tcl
deleted file mode 100644
index 7d0e88262..000000000
--- a/projects/arradio/c5soc/system_qsys.tcl
+++ /dev/null
@@ -1,5 +0,0 @@
-
-source $ad_hdl_dir/projects/common/c5soc/c5soc_system_qsys.tcl
-source ../common/arradio_qsys.tcl
-
-
diff --git a/projects/arradio/c5soc/system_top.v b/projects/arradio/c5soc/system_top.v
index 78d6cc07e..183359e50 100644
--- a/projects/arradio/c5soc/system_top.v
+++ b/projects/arradio/c5soc/system_top.v
@@ -41,124 +41,279 @@ module system_top (
 
   // clock and resets
 
-  input             sys_clk,
+  sys_clk,
 
-  // hps-ddr
+  // hps
 
-  output  [ 14:0]   ddr3_a,
-  output  [  2:0]   ddr3_ba,
-  output            ddr3_reset_n,
-  output            ddr3_ck_p,
-  output            ddr3_ck_n,
-  output            ddr3_cke,
-  output            ddr3_cs_n,
-  output            ddr3_ras_n,
-  output            ddr3_cas_n,
-  output            ddr3_we_n,
-  inout   [ 31:0]   ddr3_dq,
-  inout   [  3:0]   ddr3_dqs_p,
-  inout   [  3:0]   ddr3_dqs_n,
-  output  [  3:0]   ddr3_dm,
-  output            ddr3_odt,
-  input             ddr3_rzq,
-
-  // hps-ethernet
-
-  output            eth1_tx_clk,
-  output            eth1_tx_ctl,
-  output  [  3:0]   eth1_tx_d,
-  input             eth1_rx_clk,
-  input             eth1_rx_ctl,
-  input   [  3:0]   eth1_rx_d,
-  output            eth1_mdc,
-  inout             eth1_mdio,
-
-  // hps-qspi
-
-  output            qspi_ss0,
-  output            qspi_clk,
-  inout   [  3:0]   qspi_io,
-
-  // hps-sdio
-
-  output            sdio_clk,
-  inout             sdio_cmd,
-  inout   [  3:0]   sdio_d,
-
-  // hps-usb
-
-  input             usb1_clk,
-  output            usb1_stp,
-  input             usb1_dir,
-  input             usb1_nxt,
-  inout   [  7:0]   usb1_d,
-
-  // hps-spim1-lcd
-
-  output            spim1_ss0,
-  output            spim1_clk,
-  output            spim1_mosi,
-  input             spim1_miso,
-
-  // iic interface
-
-  inout             scl,
-  inout             sda,
-  output            ga0,
-  output            ga1,
-
-  // hps-uart
-
-  input             uart0_rx,
-  output            uart0_tx,
+  ddr3_a,
+  ddr3_ba,
+  ddr3_ck_p,
+  ddr3_ck_n,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_ras_n,
+  ddr3_cas_n,
+  ddr3_we_n,
+  ddr3_reset_n,
+  ddr3_dq,
+  ddr3_dqs_p,
+  ddr3_dqs_n,
+  ddr3_odt,
+  ddr3_dm,
+  ddr3_oct_rzqin,
+  eth1_tx_clk,
+  eth1_tx_ctl,
+  eth1_txd0,
+  eth1_txd1,
+  eth1_txd2,
+  eth1_txd3,
+  eth1_rx_clk,
+  eth1_rx_ctl,
+  eth1_rxd0,
+  eth1_rxd1,
+  eth1_rxd2,
+  eth1_rxd3,
+  eth1_mdc,
+  eth1_mdio,
+  qspi_ss0,
+  qspi_clk,
+  qspi_io0,
+  qspi_io1,
+  qspi_io2,
+  qspi_io3,
+  sdio_clk,
+  sdio_cmd,
+  sdio_d0,
+  sdio_d1,
+  sdio_d2,
+  sdio_d3,
+  usb1_clk,
+  usb1_stp,
+  usb1_dir,
+  usb1_nxt,
+  usb1_d0,
+  usb1_d1,
+  usb1_d2,
+  usb1_d3,
+  usb1_d4,
+  usb1_d5,
+  usb1_d6,
+  usb1_d7,
+  spim1_ss0,
+  spim1_clk,
+  spim1_mosi,
+  spim1_miso,
+  uart0_rx,
+  uart0_tx,
 
   // board gpio
 
-  output  [  3:0]   gpio_bd_o,
-  input   [  7:0]   gpio_bd_i,
+  led,
+  push_buttons,
+  dip_switches,
 
   // display
 
-  output            vga_clk,
-  output            vga_blank_n,
-  output            vga_sync_n,
-  output            vga_hsync,
-  output            vga_vsync,
-  output  [  7:0]   vga_red,
-  output  [  7:0]   vga_grn,
-  output  [  7:0]   vga_blu,
+  vga_clk,
+  vga_blank_n,
+  vga_sync_n,
+  vga_hs,
+  vga_vs,
+  vga_r,
+  vga_g,
+  vga_b,
 
-  // ad9361
+  // data interface
 
-  input             rx_clk_in,
-  input             rx_frame_in,
-  input   [  5:0]   rx_data_in,
-  output            tx_clk_out,
-  output            tx_frame_out,
-  output  [  5:0]   tx_data_out,
-  output            enable,
-  output            txnrx,
+  rx_clk_in,
+  rx_frame_in,
+  rx_data_in,
+  tx_clk_out,
+  tx_frame_out,
+  tx_data_out,
 
   // gpio interface
 
-  output            ad9361_resetb,
-  output            ad9361_en_agc,
-  output            ad9361_sync,
+  ad9361_resetb,
+  ad9361_en_agc,
+  ad9361_sync,
+  ad9361_enable,
+  ad9361_txnrx,
+
+  // iic interface
+
+  scl,
+  sda,
+  ga0,
+  ga1,
+
+  // spi
+
+  spi_csn,
+  spi_clk,
+  spi_mosi,
+  spi_miso);
+
+  // clock and resets
+
+  input             sys_clk;
+
+  // hps
+
+  output  [ 14:0]   ddr3_a;
+  output  [  2:0]   ddr3_ba;
+  output            ddr3_ck_p;
+  output            ddr3_ck_n;
+  output            ddr3_cke;
+  output            ddr3_cs_n;
+  output            ddr3_ras_n;
+  output            ddr3_cas_n;
+  output            ddr3_we_n;
+  output            ddr3_reset_n;
+  inout   [ 31:0]   ddr3_dq;
+  inout   [  3:0]   ddr3_dqs_p;
+  inout   [  3:0]   ddr3_dqs_n;
+  output            ddr3_odt;
+  output  [  3:0]   ddr3_dm;
+  input             ddr3_oct_rzqin;
+  output            eth1_tx_clk;
+  output            eth1_tx_ctl;
+  output            eth1_txd0;
+  output            eth1_txd1;
+  output            eth1_txd2;
+  output            eth1_txd3;
+  input             eth1_rx_clk;
+  input             eth1_rx_ctl;
+  input             eth1_rxd0;
+  input             eth1_rxd1;
+  input             eth1_rxd2;
+  input             eth1_rxd3;
+  output            eth1_mdc;
+  inout             eth1_mdio;
+  output            qspi_ss0;
+  output            qspi_clk;
+  inout             qspi_io0;
+  inout             qspi_io1;
+  inout             qspi_io2;
+  inout             qspi_io3;
+  output            sdio_clk;
+  inout             sdio_cmd;
+  inout             sdio_d0;
+  inout             sdio_d1;
+  inout             sdio_d2;
+  inout             sdio_d3;
+  input             usb1_clk;
+  output            usb1_stp;
+  input             usb1_dir;
+  input             usb1_nxt;
+  inout             usb1_d0;
+  inout             usb1_d1;
+  inout             usb1_d2;
+  inout             usb1_d3;
+  inout             usb1_d4;
+  inout             usb1_d5;
+  inout             usb1_d6;
+  inout             usb1_d7;
+  output            spim1_ss0;
+  output            spim1_clk;
+  output            spim1_mosi;
+  input             spim1_miso;
+  input             uart0_rx;
+  output            uart0_tx;
+
+  // board gpio
+
+  output  [  3:0]   led;
+  input   [  3:0]   push_buttons;
+  input   [  3:0]   dip_switches;
+
+  // display
+
+  output            vga_clk;
+  output            vga_blank_n;
+  output            vga_sync_n;
+  output            vga_hs;
+  output            vga_vs;
+  output  [  7:0]   vga_r;
+  output  [  7:0]   vga_g;
+  output  [  7:0]   vga_b;
+
+  // data interface
+
+  input             rx_clk_in;
+  input             rx_frame_in;
+  input   [  5:0]   rx_data_in;
+  output            tx_clk_out;
+  output            tx_frame_out;
+  output  [  5:0]   tx_data_out;
+
+  // gpio interface
+
+  output            ad9361_resetb;
+  output            ad9361_en_agc;
+  output            ad9361_sync;
+  output            ad9361_enable;
+  output            ad9361_txnrx;
+
+  // iic interface
+
+  inout             scl;
+  inout             sda;
+  output            ga0;
+  output            ga1;
+
 
   // spi interface
 
-  output            spi_csn,
-  output            spi_clk,
-  output            spi_mosi,
-  input             spi_miso);
+  output            spi_csn;
+  output            spi_clk;
+  output            spi_mosi;
+  input             spi_miso;
+
+  // internal clocks and resets
+
+  wire    [ 31:0]   gpio_open;
+  wire              sys_resetn;
+  wire              clk;
 
   // internal signals
 
-  wire              sys_resetn;
-  wire    [ 31:0]   sys_gpio_bd_i;
-  wire    [ 31:0]   sys_gpio_bd_o;
-  wire    [ 31:0]   sys_gpio_i;
-  wire    [ 31:0]   sys_gpio_o;
+  wire              adc_enable_i0;
+  wire              adc_enable_q0;
+  wire              adc_enable_i1;
+  wire              adc_enable_q1;
+  wire              adc_valid_i0;
+  wire              adc_valid_q0;
+  wire              adc_valid_i1;
+  wire              adc_valid_q1;
+  wire              adc_dwr;
+  wire              adc_dsync;
+  wire    [ 15:0]   adc_chan_i0;
+  wire    [ 15:0]   adc_chan_q0;
+  wire    [ 15:0]   adc_chan_i1;
+  wire    [ 15:0]   adc_chan_q1;
+  wire    [ 63:0]   adc_ddata;
+  wire              adc_dovf;
+  wire              dac_enable_i0;
+  wire              dac_enable_q0;
+  wire              dac_enable_i1;
+  wire              dac_enable_q1;
+  wire              dac_valid_i0;
+  wire              dac_valid_q0;
+  wire              dac_valid_i1;
+  wire              dac_valid_q1;
+  wire    [ 15:0]   dac_data_i0;
+  wire    [ 15:0]   dac_data_q0;
+  wire    [ 15:0]   dac_data_i1;
+  wire    [ 15:0]   dac_data_q1;
+  wire    [ 63:0]   dac_ddata;
+  wire              dac_dunf;
+  wire              dac_rd_en;
+  wire              dac_fifo_valid;  
+  wire              vga_pixel_clock;
+  wire              vid_v_sync;
+  wire              vid_h_sync;
+  wire    [7:0]     vid_r,vid_g,vid_b;
 
   wire              i2c0_out_data;
   wire              i2c0_sda;
@@ -167,96 +322,48 @@ module system_top (
 
   // defaults
 
+  assign vga_clk = vga_pixel_clock;
   assign vga_blank_n = 1'b1;
   assign vga_sync_n = 1'b0;
-
-  assign gpio_bd_o = sys_gpio_bd_o[3:0];
-
-  assign sys_gpio_bd_i[31:8] = sys_gpio_bd_o[31:8];
-  assign sys_gpio_bd_i[ 7:0] = gpio_bd_i;
-  
-  assign ad9361_resetb = sys_gpio_o[4];
-  assign ad9361_en_agc = sys_gpio_o[3];
-  assign ad9361_sync = sys_gpio_o[2];
+  assign vga_hs = vid_h_sync;
+  assign vga_vs = vid_v_sync;
+  assign {vga_b,vga_g,vga_r} =  {vid_b,vid_g,vid_r};
   assign ga0 = 1'b0;
   assign ga1 = 1'b0;
 
- ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl));
- ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda));
+
+ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl)); //
+ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda)); //
+
 
   // instantiations
 
+  sld_signaltap #(
+    .sld_advanced_trigger_entity ("basic,1,"),
+    .sld_data_bits (64),
+    .sld_data_bit_cntr_bits (7),
+    .sld_enable_advanced_trigger (0),
+    .sld_mem_address_bits (10),
+    .sld_node_crc_bits (32),
+    .sld_node_crc_hiword (13323),
+    .sld_node_crc_loword (24084),
+    .sld_node_info (1076736),
+    .sld_ram_block_type ("AUTO"),
+    .sld_sample_depth (1024),
+    .sld_storage_qualifier_gap_record (0),
+    .sld_storage_qualifier_mode ("OFF"),
+    .sld_trigger_bits (1),
+    .sld_trigger_in_enabled (0),
+    .sld_trigger_level (1),
+    .sld_trigger_level_pipeline (1))
+  i_ila_adc (
+    .acq_clk (clk),
+    .acq_data_in (adc_ddata),
+    .acq_trigger_in (adc_valid_i0));
+
   system_bd i_system_bd (
-    .axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
-    .axi_ad9361_device_if_rx_clk_in_n (1'd0),
-    .axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
-    .axi_ad9361_device_if_rx_frame_in_n (1'd0),
-    .axi_ad9361_device_if_rx_data_in_p (rx_data_in),
-    .axi_ad9361_device_if_rx_data_in_n (6'd0),
-    .axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
-    .axi_ad9361_device_if_tx_clk_out_n (),
-    .axi_ad9361_device_if_tx_frame_out_p (tx_frame_out),
-    .axi_ad9361_device_if_tx_frame_out_n (),
-    .axi_ad9361_device_if_tx_data_out_p (tx_data_out),
-    .axi_ad9361_device_if_tx_data_out_n (),
-    .axi_ad9361_device_if_enable (enable),
-    .axi_ad9361_device_if_txnrx (txnrx),
-    .axi_ad9361_up_enable_up_enable (sys_gpio_o[1]),
-    .axi_ad9361_up_txnrx_up_txnrx (sys_gpio_o[0]),
-    .sys_clk_clk (sys_clk),
-    .sys_gpio_bd_in_port (sys_gpio_bd_i),
-    .sys_gpio_bd_out_port (sys_gpio_bd_o),
-    .sys_gpio_in_export (sys_gpio_i),
-    .sys_gpio_out_export (sys_gpio_o),
-    .sys_hps_h2f_reset_reset_n (sys_resetn),
-    .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
-    .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
-    .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
-    .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
-    .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
-    .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
-    .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
-    .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
-    .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
-    .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
-    .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
-    .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
-    .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
-    .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
-    .sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]),
-    .sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]),
-    .sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]),
-    .sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]),
-    .sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
-    .sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
-    .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
-    .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
-    .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
-    .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
-    .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
-    .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
-    .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
-    .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
-    .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
-    .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
-    .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
-    .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
-    .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
-    .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
-    .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
-    .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
-    .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
-    .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
-    .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
-    .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
-    .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
-    .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
-    .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
-    .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
-    .sys_hps_i2c0_out_data(i2c0_out_data),
-    .sys_hps_i2c0_sda(i2c0_sda),
-    .sys_hps_i2c0_clk_clk(i2c0_out_clk),
-    .sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk),
+    .clk_clk (sys_clk),
+    .reset_reset_n (sys_resetn),
     .sys_hps_memory_mem_a (ddr3_a),
     .sys_hps_memory_mem_ba (ddr3_ba),
     .sys_hps_memory_mem_ck (ddr3_ck_p),
@@ -272,24 +379,96 @@ module system_top (
     .sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
     .sys_hps_memory_mem_odt (ddr3_odt),
     .sys_hps_memory_mem_dm (ddr3_dm),
-    .sys_hps_memory_oct_rzqin (ddr3_rzq),
-    .sys_rst_reset_n (sys_resetn),
-    .sys_spi_MISO (spi_miso),
-    .sys_spi_MOSI (spi_mosi),
-    .sys_spi_SCLK (spi_clk),
-    .sys_spi_SS_n (spi_csn),
-    .vga_out_clk_clk (vga_clk),
-    .vga_out_data_vid_clk (vga_clk),
-    .vga_out_data_vid_data ({vga_red, vga_grn, vga_blu}),
-    .vga_out_data_underflow (),
-    .vga_out_data_vid_datavalid (),
-    .vga_out_data_vid_v_sync (vga_vsync),
-    .vga_out_data_vid_h_sync (vga_hsync),
-    .vga_out_data_vid_f (),
-    .vga_out_data_vid_h (),
-    .vga_out_data_vid_v (),
-    .vga_if_vid_v ()
-	 );
+    .sys_hps_memory_oct_rzqin (ddr3_oct_rzqin),
+    .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
+    .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
+    .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
+    .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
+    .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
+    .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
+    .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
+    .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
+    .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
+    .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
+    .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
+    .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
+    .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
+    .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
+    .sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
+    .sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
+    .sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
+    .sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
+    .sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
+    .sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
+    .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
+    .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
+    .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
+    .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
+    .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
+    .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
+    .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
+    .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
+    .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
+    .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
+    .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
+    .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
+    .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
+    .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
+    .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
+    .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
+    .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
+    .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
+    .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
+    .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
+    .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
+    .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
+    .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
+    .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
+    .sys_gpio_external_connection_in_port ({16'd0, 4'd0, led, push_buttons, dip_switches}),
+    .sys_gpio_external_connection_out_port ({gpio_open[31:16], gpio_open[15:12], led, gpio_open[7:0]}),
+    .sys_hps_h2f_reset_reset_n (sys_resetn),
+    .sys_hps_spim0_txd (),
+    .sys_hps_spim0_rxd (),
+    .sys_hps_spim0_ss_in_n (1'b1),
+    .sys_hps_spim0_ssi_oe_n (),
+    .sys_hps_spim0_ss_0_n (),
+    .sys_hps_spim0_ss_1_n (),
+    .sys_hps_spim0_ss_2_n (),
+    .sys_hps_spim0_ss_3_n (),
+    .sys_hps_spim0_sclk_out_clk (),
+    .axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
+    .axi_ad9361_device_if_rx_clk_in_n (1'b0),
+    .axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
+    .axi_ad9361_device_if_rx_frame_in_n (1'b0),
+    .axi_ad9361_device_if_rx_data_in_p (rx_data_in),
+    .axi_ad9361_device_if_rx_data_in_n (6'd0),
+    .axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
+    .axi_ad9361_device_if_tx_clk_out_n (),
+    .axi_ad9361_device_if_tx_frame_out_p (tx_frame_out),
+    .axi_ad9361_device_if_tx_frame_out_n (),
+    .axi_ad9361_device_if_tx_data_out_p (tx_data_out),
+    .axi_ad9361_device_if_tx_data_out_n (),
+    .axi_ad9361_l_clk_clk (clk),
+    .spi_ad9361_external_MISO (spi_miso),
+    .spi_ad9361_external_MOSI (spi_mosi),
+    .spi_ad9361_external_SCLK (spi_clk),
+    .spi_ad9361_external_SS_n (spi_csn),
+    .vga_pixel_clock_bridge_out_clk_clk (vga_pixel_clock),
+    .vga_clock_video_output_clocked_video_vid_clk (vga_pixel_clock),
+    .vga_clock_video_output_clocked_video_vid_data ({vid_r,vid_g,vid_b}),
+    .vga_clock_video_output_clocked_video_underflow (),
+    .vga_clock_video_output_clocked_video_vid_datavalid (),
+    .vga_clock_video_output_clocked_video_vid_v_sync (vid_v_sync),
+    .vga_clock_video_output_clocked_video_vid_h_sync (vid_h_sync),
+    .vga_clock_video_output_clocked_video_vid_f (),
+    .vga_clock_video_output_clocked_video_vid_h (),
+    .vga_clock_video_output_clocked_video_vid_v (),
+    .sys_hps_i2c0_out_data(i2c0_out_data),
+    .sys_hps_i2c0_sda(i2c0_sda),
+    .sys_hps_i2c0_clk_clk(i2c0_out_clk),
+    .sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk),
+    .gpio_external_connection_export ({ad9361_resetb, ad9361_en_agc, ad9361_sync, ad9361_enable, ad9361_txnrx})
+  );
 
 endmodule
 
diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys
new file mode 100755
index 000000000..b3e2d51e0
--- /dev/null
+++ b/projects/arradio/common/arradio_bd.qsys
@@ -0,0 +1,780 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element ad9361_clk_bridge
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element adc_pack
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element axi_ad9361
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_ad9361.s_axi
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element axi_dmac_adc
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_dmac_adc.s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element axi_dmac_dac
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_dmac_dac.s_axi
+   {
+      datum baseAddress
+      {
+         value = "16384";
+         type = "String";
+      }
+   }
+   element dac_upack
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element gpio
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element mem_clk
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element mem_rst
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element spi_ad9361
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element spi_ad9361.spi_control_port
+   {
+      datum baseAddress
+      {
+         value = "32768";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_rst
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="5CSXFC6D6F31C8ES" />
+ <parameter name="deviceFamily" value="Cyclone V" />
+ <parameter name="deviceSpeedGrade" value="8_H6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
+ <interface
+   name="axi_ad9361_device_if"
+   internal="axi_ad9361.device_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9361_l_clk"
+   internal="ad9361_clk_bridge.out_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="axi_ad9361_s_axi"
+   internal="axi_ad9361.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_dmac_adc_fifo_wr_clock"
+   internal="axi_dmac_adc.fifo_wr_clock" />
+ <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
+ <interface
+   name="axi_dmac_adc_intr"
+   internal="axi_dmac_adc.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_dmac_adc_m_dest_axi"
+   internal="axi_dmac_adc.m_dest_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_dmac_adc_s_axi"
+   internal="axi_dmac_adc.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="axi_dmac_dac_fifo_rd_clock"
+   internal="axi_dmac_dac.fifo_rd_clock" />
+ <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
+ <interface
+   name="axi_dmac_dac_intr"
+   internal="axi_dmac_dac.interrupt_sender"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="axi_dmac_dac_m_src_axi"
+   internal="axi_dmac_dac.m_src_axi"
+   type="axi4"
+   dir="start" />
+ <interface
+   name="axi_dmac_dac_s_axi"
+   internal="axi_dmac_dac.s_axi"
+   type="axi4lite"
+   dir="end" />
+ <interface
+   name="gpio_external_connection"
+   internal="gpio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="gpio_s1" internal="gpio.s1" type="avalon" dir="end" />
+ <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
+ <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
+ <interface
+   name="spi_ad9361_external"
+   internal="spi_ad9361.external"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="spi_ad9361_irq"
+   internal="spi_ad9361.irq"
+   type="interrupt"
+   dir="end" />
+ <interface
+   name="spi_ad9361_spi_control_port"
+   internal="spi_ad9361.spi_control_port"
+   type="avalon"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
+ <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
+ <module
+   name="ad9361_clk_bridge"
+   kind="altera_clock_bridge"
+   version="16.0"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
+  <parameter name="ADC_DATAFORMAT_DISABLE" value="0" />
+  <parameter name="ADC_DATAPATH_DISABLE" value="0" />
+  <parameter name="ADC_DCFILTER_DISABLE" value="0" />
+  <parameter name="ADC_IQCORRECTION_DISABLE" value="0" />
+  <parameter name="ADC_USERPORTS_DISABLE" value="0" />
+  <parameter name="CMOS_OR_LVDS_N" value="0" />
+  <parameter name="DAC_DATAPATH_DISABLE" value="0" />
+  <parameter name="DAC_DDS_DISABLE" value="0" />
+  <parameter name="DAC_IODELAY_ENABLE" value="0" />
+  <parameter name="DAC_IQCORRECTION_DISABLE" value="0" />
+  <parameter name="DAC_USERPORTS_DISABLE" value="0" />
+  <parameter name="DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="DEVICE_TYPE" value="0" />
+  <parameter name="ID" value="0" />
+  <parameter name="IO_DELAY_GROUP" value="dev_if_delay_group" />
+  <parameter name="MODE_1R1T" value="0" />
+  <parameter name="TDD_DISABLE" value="0" />
+ </module>
+ <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="0" />
+  <parameter name="DMA_TYPE_SRC" value="2" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
+ </module>
+ <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
+  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
+  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
+  <parameter name="AXI_SLICE_DEST" value="0" />
+  <parameter name="AXI_SLICE_SRC" value="0" />
+  <parameter name="CYCLIC" value="1" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
+  <parameter name="DMA_TYPE_DEST" value="2" />
+  <parameter name="DMA_TYPE_SRC" value="0" />
+  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="ID" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="0" />
+ </module>
+ <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
+  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
+  <parameter name="NUM_OF_CHANNELS" value="4" />
+ </module>
+ <module name="gpio" kind="altera_avalon_pio" version="16.0" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="5" />
+ </module>
+ <module name="mem_clk" kind="altera_clock_bridge" version="16.0" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="mem_rst" kind="altera_reset_bridge" version="16.0" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="spi_ad9361" kind="altera_avalon_spi" version="16.0" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="1" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="50000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="1" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="50000000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
+ <module name="sys_clk" kind="altera_clock_bridge" version="16.0" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_rst" kind="altera_reset_bridge" version="16.0" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <connection
+   kind="clock"
+   version="16.0"
+   start="axi_ad9361.if_l_clk"
+   end="adc_pack.if_adc_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="axi_ad9361.if_l_clk"
+   end="axi_ad9361.if_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="axi_ad9361.if_l_clk"
+   end="dac_upack.if_dac_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="axi_ad9361.if_l_clk"
+   end="axi_dmac_dac.if_fifo_rd_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="axi_ad9361.if_l_clk"
+   end="axi_dmac_adc.if_fifo_wr_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="axi_ad9361.if_l_clk"
+   end="ad9361_clk_bridge.in_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="spi_ad9361.clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.out_clk" end="gpio.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="axi_ad9361.if_delay_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="mem_clk.out_clk"
+   end="axi_dmac_adc.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="mem_clk.out_clk"
+   end="axi_dmac_dac.m_src_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="axi_ad9361.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="axi_dmac_adc.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="axi_dmac_dac.s_axi_clock" />
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="adc_pack.adc_ch_0"
+   end="axi_ad9361.adc_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9361.adc_ch_1"
+   end="adc_pack.adc_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9361.adc_ch_2"
+   end="adc_pack.adc_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="adc_pack.adc_ch_3"
+   end="axi_ad9361.adc_ch_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9361.dac_ch_0"
+   end="dac_upack.dac_ch_0">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="dac_upack.dac_ch_1"
+   end="axi_ad9361.dac_ch_1">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_ad9361.dac_ch_2"
+   end="dac_upack.dac_ch_2">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="dac_upack.dac_ch_3"
+   end="axi_ad9361.dac_ch_3">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="adc_pack.if_adc_data"
+   end="axi_dmac_adc.if_fifo_wr_din">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="adc_pack.if_adc_sync"
+   end="axi_dmac_adc.if_fifo_wr_sync">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="adc_pack.if_adc_valid"
+   end="axi_dmac_adc.if_fifo_wr_en">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="dac_upack.if_dac_data"
+   end="axi_dmac_dac.if_fifo_rd_dout">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="dac_upack.if_dma_xfer_in"
+   end="axi_dmac_dac.if_fifo_rd_xfer_req">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_dmac_dac.if_fifo_rd_en"
+   end="dac_upack.if_dac_valid">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_dmac_dac.if_fifo_rd_underflow"
+   end="axi_ad9361.if_dac_dunf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="16.0"
+   start="axi_dmac_adc.if_fifo_wr_overflow"
+   end="axi_ad9361.if_adc_dovf">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="16.0"
+   start="axi_ad9361.if_rst"
+   end="adc_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="adc_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="mem_rst.out_reset"
+   end="adc_pack.if_adc_rst" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="mem_rst.out_reset"
+   end="axi_dmac_adc.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="mem_rst.out_reset"
+   end="axi_dmac_dac.m_src_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="spi_ad9361.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="gpio.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="axi_ad9361.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="axi_dmac_adc.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="axi_dmac_dac.s_axi_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+ <interconnectRequirement
+   for="mm_interconnect_0|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_2|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+</system>
diff --git a/projects/arradio/common/arradio_qsys.tcl b/projects/arradio/common/arradio_qsys.tcl
deleted file mode 100755
index ddb5607b8..000000000
--- a/projects/arradio/common/arradio_qsys.tcl
+++ /dev/null
@@ -1,157 +0,0 @@
-
-# ad9361
-
-add_instance axi_ad9361 axi_ad9361 1.0
-set_instance_parameter_value axi_ad9361 {ID} {0}
-set_instance_parameter_value axi_ad9361 {MODE_1R1T} {0}
-set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {1}
-set_instance_parameter_value axi_ad9361 {TDD_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {CMOS_OR_LVDS_N} {0}
-set_instance_parameter_value axi_ad9361 {ADC_DATAPATH_DISABLE} {0}
-set_instance_parameter_value axi_ad9361 {DAC_DATAPATH_DISABLE} {0}
-add_interface axi_ad9361_device_if conduit end
-set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
-add_interface axi_ad9361_up_enable conduit end
-set_interface_property axi_ad9361_up_enable EXPORT_OF axi_ad9361.if_up_enable
-add_interface axi_ad9361_up_txnrx conduit end
-set_interface_property axi_ad9361_up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
-add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk
-add_connection sys_clk.clk axi_ad9361.if_delay_clk
-add_connection sys_clk.clk axi_ad9361.s_axi_clock
-add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
-
-# clk division
-
-add_instance util_clkdiv_ad9361 util_clkdiv 1.0
-add_connection axi_ad9361.if_l_clk util_clkdiv_ad9361.if_clk
-add_connection axi_ad9361.if_rst util_clkdiv_ad9361.if_reset
-
-# adc-wfifo & dac-rfifo
-
-add_instance util_adc_wfifo util_wfifo 1.0
-set_instance_parameter_value util_adc_wfifo {NUM_OF_CHANNELS} {4}
-set_instance_parameter_value util_adc_wfifo {DIN_DATA_WIDTH} {16}
-set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
-set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
-add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
-add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
-add_connection util_clkdiv_ad9361.if_clk_out util_adc_wfifo.if_dout_clk
-add_connection util_clkdiv_ad9361.if_reset_out util_adc_wfifo.if_dout_rstn
-add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
-add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
-add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
-add_connection axi_ad9361.adc_ch_3 util_adc_wfifo.din_3
-add_connection util_adc_wfifo.if_din_ovf axi_ad9361.if_adc_dovf
-
-# adc-wfifo & dac-rfifo
-
-add_instance util_dac_rfifo util_rfifo 1.0
-set_instance_parameter_value util_dac_rfifo {NUM_OF_CHANNELS} {4}
-set_instance_parameter_value util_dac_rfifo {DIN_DATA_WIDTH} {16}
-set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
-set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
-add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
-add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
-add_connection util_clkdiv_ad9361.if_clk_out util_dac_rfifo.if_din_clk
-add_connection util_clkdiv_ad9361.if_reset_out util_dac_rfifo.if_din_rstn
-add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
-add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
-add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
-add_connection util_dac_rfifo.dout_3 axi_ad9361.dac_ch_3
-add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
-
-# adc-pack & dac-unpack
-
-add_instance util_adc_pack util_cpack 1.0
-set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
-set_instance_parameter_value util_adc_pack {CHANNEL_DATA_WIDTH} {16}
-add_connection util_clkdiv_ad9361.if_clk_out util_adc_pack.if_adc_clk
-add_connection util_clkdiv_ad9361.if_reset_out util_adc_pack.if_adc_rst
-add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
-add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
-add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
-add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
-
-# adc-pack & dac-unpack
-
-add_instance util_dac_upack util_upack 1.0
-set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
-set_instance_parameter_value util_dac_upack {CHANNEL_DATA_WIDTH} {16}
-add_connection util_clkdiv_ad9361.if_clk_out util_dac_upack.if_dac_clk
-add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
-add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
-add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
-add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
-
-# adc-dma & dac-dma
-
-add_instance axi_adc_dma axi_dmac 1.0
-set_instance_parameter_value axi_adc_dma {ID} {0}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
-set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
-set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
-set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
-set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
-set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
-set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
-set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
-set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
-add_connection sys_clk.clk axi_adc_dma.s_axi_clock
-add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
-add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
-add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
-add_connection util_clkdiv_ad9361.if_clk_out axi_adc_dma.if_fifo_wr_clk
-add_connection util_adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
-add_connection util_adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
-add_connection util_adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
-add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_wfifo.if_dout_ovf
-
-# adc-dma & dac-dma
-
-add_instance axi_dac_dma axi_dmac 1.0
-set_instance_parameter_value axi_dac_dma {ID} {0}
-set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {64}
-set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {64}
-set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
-set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1}
-set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1}
-set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
-set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
-set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
-set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
-set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
-set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
-set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
-add_connection sys_clk.clk axi_dac_dma.s_axi_clock
-add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
-add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
-add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
-add_connection util_clkdiv_ad9361.if_clk_out axi_dac_dma.if_fifo_rd_clk
-add_connection util_dac_upack.if_dac_valid axi_dac_dma.if_fifo_rd_en
-add_connection axi_dac_dma.if_fifo_rd_dout util_dac_upack.if_dac_data
-add_connection axi_dac_dma.if_fifo_rd_xfer_req util_dac_upack.if_dma_xfer_in
-add_connection axi_dac_dma.if_fifo_rd_underflow util_dac_rfifo.if_din_unf
-
-# interrupts
-
-ad_cpu_interrupt 2 axi_adc_dma.interrupt_sender
-ad_cpu_interrupt 3 axi_dac_dma.interrupt_sender
-
-# cpu interconnects
-
-ad_cpu_interconnect 0x00120000 axi_ad9361.s_axi
-ad_cpu_interconnect 0x00100000 axi_adc_dma.s_axi
-ad_cpu_interconnect 0x00104000 axi_dac_dma.s_axi
-
-# mem interconnects
-
-ad_dma_interconnect axi_adc_dma.m_dest_axi 0
-ad_dma_interconnect axi_dac_dma.m_src_axi 1
-
diff --git a/projects/common/c5soc/c5soc_system_assign.tcl b/projects/common/c5soc/c5soc_system_assign.tcl
index 6ed0afc1d..9c25eda56 100755
--- a/projects/common/c5soc/c5soc_system_assign.tcl
+++ b/projects/common/c5soc/c5soc_system_assign.tcl
@@ -14,95 +14,95 @@ set_instance_assignment -name IO_STANDARD "1.5 V" -to sys_clk
 set_location_assignment PIN_W20   -to vga_clk
 set_location_assignment PIN_AH3   -to vga_blank_n
 set_location_assignment PIN_AG2   -to vga_sync_n
-set_location_assignment PIN_AD12  -to vga_hsync
-set_location_assignment PIN_AC12  -to vga_vsync
-set_location_assignment PIN_AG5   -to vga_red[0]
-set_location_assignment PIN_AA12  -to vga_red[1]
-set_location_assignment PIN_AB12  -to vga_red[2]
-set_location_assignment PIN_AF6   -to vga_red[3]
-set_location_assignment PIN_AG6   -to vga_red[4]
-set_location_assignment PIN_AJ2   -to vga_red[5]
-set_location_assignment PIN_AH5   -to vga_red[6]
-set_location_assignment PIN_AJ1   -to vga_red[7]
-set_location_assignment PIN_Y21   -to vga_grn[0]
-set_location_assignment PIN_AA25  -to vga_grn[1]
-set_location_assignment PIN_AB26  -to vga_grn[2]
-set_location_assignment PIN_AB22  -to vga_grn[3]
-set_location_assignment PIN_AB23  -to vga_grn[4]
-set_location_assignment PIN_AA24  -to vga_grn[5]
-set_location_assignment PIN_AB25  -to vga_grn[6]
-set_location_assignment PIN_AE27  -to vga_grn[7]
-set_location_assignment PIN_AE28  -to vga_blu[0]
-set_location_assignment PIN_Y23   -to vga_blu[1]
-set_location_assignment PIN_Y24   -to vga_blu[2]
-set_location_assignment PIN_AG28  -to vga_blu[3]
-set_location_assignment PIN_AF28  -to vga_blu[4]
-set_location_assignment PIN_V23   -to vga_blu[5]
-set_location_assignment PIN_W24   -to vga_blu[6]
-set_location_assignment PIN_AF29  -to vga_blu[7]
-
+set_location_assignment PIN_AD12  -to vga_hs
+set_location_assignment PIN_AC12  -to vga_vs
+set_location_assignment PIN_AF29 -to vga_b[7]
+set_location_assignment PIN_AE28 -to vga_b[0]
+set_location_assignment PIN_Y23 -to vga_b[1]
+set_location_assignment PIN_Y24 -to vga_b[2]
+set_location_assignment PIN_AG28 -to vga_b[3]
+set_location_assignment PIN_AF28 -to vga_b[4]
+set_location_assignment PIN_V23 -to vga_b[5]
+set_location_assignment PIN_W24 -to vga_b[6]
+set_location_assignment PIN_Y21 -to vga_g[0]
+set_location_assignment PIN_AA25 -to vga_g[1]
+set_location_assignment PIN_AB26 -to vga_g[2]
+set_location_assignment PIN_AB22 -to vga_g[3]
+set_location_assignment PIN_AB23 -to vga_g[4]
+set_location_assignment PIN_AA24 -to vga_g[5]
+set_location_assignment PIN_AB25 -to vga_g[6]
+set_location_assignment PIN_AE27 -to vga_g[7]
+set_location_assignment PIN_AG5 -to vga_r[0]
+set_location_assignment PIN_AA12 -to vga_r[1]
+set_location_assignment PIN_AB12 -to vga_r[2]
+set_location_assignment PIN_AF6 -to vga_r[3]
+set_location_assignment PIN_AG6 -to vga_r[4]
+set_location_assignment PIN_AJ2 -to vga_r[5]
+set_location_assignment PIN_AH5 -to vga_r[6]
+set_location_assignment PIN_AJ1 -to vga_r[7]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blank_n
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_sync_n
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hsync
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vsync
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hs
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vs
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[7]
 
 # led & switches
 
-set_location_assignment PIN_AD7  -to gpio_bd_o[3]
-set_location_assignment PIN_AE11 -to gpio_bd_o[2]
-set_location_assignment PIN_AD10 -to gpio_bd_o[1]
-set_location_assignment PIN_AF10 -to gpio_bd_o[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[0]
+set_location_assignment PIN_AD7  -to led[3]
+set_location_assignment PIN_AE11 -to led[2]
+set_location_assignment PIN_AD10 -to led[1]
+set_location_assignment PIN_AF10 -to led[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[0]
 
-set_location_assignment PIN_AD11 -to gpio_bd_i[0]
-set_location_assignment PIN_AD9  -to gpio_bd_i[1]
-set_location_assignment PIN_AE12 -to gpio_bd_i[2]
-set_location_assignment PIN_AE9  -to gpio_bd_i[3]
-set_location_assignment PIN_AC29 -to gpio_bd_i[4]
-set_location_assignment PIN_AC28 -to gpio_bd_i[5]
-set_location_assignment PIN_V25  -to gpio_bd_i[6]
-set_location_assignment PIN_W25  -to gpio_bd_i[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[7]
+set_location_assignment PIN_AD11 -to push_buttons[3]
+set_location_assignment PIN_AD9  -to push_buttons[2]
+set_location_assignment PIN_AE12 -to push_buttons[1]
+set_location_assignment PIN_AE9  -to push_buttons[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[0]
+
+set_location_assignment PIN_AC29 -to dip_switches[3]
+set_location_assignment PIN_AC28 -to dip_switches[2]
+set_location_assignment PIN_V25  -to dip_switches[1]
+set_location_assignment PIN_W25  -to dip_switches[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[0]
 
 # uart
 
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_rx
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_tx
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_rx
 
 # spim1 (lcd)
 
@@ -117,47 +117,47 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_stp
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_dir
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_nxt
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d7
 
 # sdio
 
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_cmd
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d0
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d3
 
 # qspi
 
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_ss0
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io0
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io1
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io3
 
 # ethernet
 
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_ctl
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd3
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_clk
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_ctl
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd3
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdc
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdio
 
@@ -320,7 +320,7 @@ set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_reset_n
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_rzq
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_oct_rzqin
 
 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
@@ -444,81 +444,6 @@ set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_we_n
 set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst
 set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|pll0|fbout
 
-# ddr3 pin locations (quartus critical warnings)
-
-set_location_assignment PIN_F26   -to ddr3_a[0]
-set_location_assignment PIN_G30   -to ddr3_a[1]
-set_location_assignment PIN_F28   -to ddr3_a[2]
-set_location_assignment PIN_F30   -to ddr3_a[3]
-set_location_assignment PIN_J25   -to ddr3_a[4]
-set_location_assignment PIN_J27   -to ddr3_a[5]
-set_location_assignment PIN_F29   -to ddr3_a[6]
-set_location_assignment PIN_E28   -to ddr3_a[7]
-set_location_assignment PIN_H27   -to ddr3_a[8]
-set_location_assignment PIN_G26   -to ddr3_a[9]
-set_location_assignment PIN_D29   -to ddr3_a[10]
-set_location_assignment PIN_C30   -to ddr3_a[11]
-set_location_assignment PIN_B30   -to ddr3_a[12]
-set_location_assignment PIN_C29   -to ddr3_a[13]
-set_location_assignment PIN_H25   -to ddr3_a[14]
-set_location_assignment PIN_E29   -to ddr3_ba[0]
-set_location_assignment PIN_J24   -to ddr3_ba[1]
-set_location_assignment PIN_J23   -to ddr3_ba[2]
-set_location_assignment PIN_E27   -to ddr3_cas_n
-set_location_assignment PIN_M23   -to ddr3_ck_p
-set_location_assignment PIN_L23   -to ddr3_ck_n
-set_location_assignment PIN_L29   -to ddr3_cke
-set_location_assignment PIN_H24   -to ddr3_cs_n
-set_location_assignment PIN_K28   -to ddr3_dm[0]
-set_location_assignment PIN_M28   -to ddr3_dm[1]
-set_location_assignment PIN_R28   -to ddr3_dm[2]
-set_location_assignment PIN_W30   -to ddr3_dm[3]
-set_location_assignment PIN_K23   -to ddr3_dq[0]
-set_location_assignment PIN_K22   -to ddr3_dq[1]
-set_location_assignment PIN_H30   -to ddr3_dq[2]
-set_location_assignment PIN_G28   -to ddr3_dq[3]
-set_location_assignment PIN_L25   -to ddr3_dq[4]
-set_location_assignment PIN_L24   -to ddr3_dq[5]
-set_location_assignment PIN_J30   -to ddr3_dq[6]
-set_location_assignment PIN_J29   -to ddr3_dq[7]
-set_location_assignment PIN_K26   -to ddr3_dq[8]
-set_location_assignment PIN_L26   -to ddr3_dq[9]
-set_location_assignment PIN_K29   -to ddr3_dq[10]
-set_location_assignment PIN_K27   -to ddr3_dq[11]
-set_location_assignment PIN_M26   -to ddr3_dq[12]
-set_location_assignment PIN_M27   -to ddr3_dq[13]
-set_location_assignment PIN_L28   -to ddr3_dq[14]
-set_location_assignment PIN_M30   -to ddr3_dq[15]
-set_location_assignment PIN_U26   -to ddr3_dq[16]
-set_location_assignment PIN_T26   -to ddr3_dq[17]
-set_location_assignment PIN_N29   -to ddr3_dq[18]
-set_location_assignment PIN_N28   -to ddr3_dq[19]
-set_location_assignment PIN_P26   -to ddr3_dq[20]
-set_location_assignment PIN_P27   -to ddr3_dq[21]
-set_location_assignment PIN_N27   -to ddr3_dq[22]
-set_location_assignment PIN_R29   -to ddr3_dq[23]
-set_location_assignment PIN_P24   -to ddr3_dq[24]
-set_location_assignment PIN_P25   -to ddr3_dq[25]
-set_location_assignment PIN_T29   -to ddr3_dq[26]
-set_location_assignment PIN_T28   -to ddr3_dq[27]
-set_location_assignment PIN_R27   -to ddr3_dq[28]
-set_location_assignment PIN_R26   -to ddr3_dq[29]
-set_location_assignment PIN_V30   -to ddr3_dq[30]
-set_location_assignment PIN_W29   -to ddr3_dq[31]
-set_location_assignment PIN_N18   -to ddr3_dqs_p[0]
-set_location_assignment PIN_M19   -to ddr3_dqs_n[0]
-set_location_assignment PIN_N25   -to ddr3_dqs_p[1]
-set_location_assignment PIN_N24   -to ddr3_dqs_n[1]
-set_location_assignment PIN_R19   -to ddr3_dqs_p[2]
-set_location_assignment PIN_R18   -to ddr3_dqs_n[2]
-set_location_assignment PIN_R22   -to ddr3_dqs_p[3]
-set_location_assignment PIN_R21   -to ddr3_dqs_n[3]
-set_location_assignment PIN_H28   -to ddr3_odt
-set_location_assignment PIN_D30   -to ddr3_ras_n
-set_location_assignment PIN_P30   -to ddr3_reset_n
-set_location_assignment PIN_C28   -to ddr3_we_n
-set_location_assignment PIN_D27   -to ddr3_rzq
-
 # globals
 
 set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
@@ -536,6 +461,7 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
 set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
-# source defaults
 
-source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
+
+
+
diff --git a/projects/common/c5soc/c5soc_system_bd.qsys b/projects/common/c5soc/c5soc_system_bd.qsys
new file mode 100755
index 000000000..ad63dfc44
--- /dev/null
+++ b/projects/common/c5soc/c5soc_system_bd.qsys
@@ -0,0 +1,1887 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element mem_clk
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element mem_rst
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_cpu_interconnect
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_cpu_interconnect.s0
+   {
+      datum baseAddress
+      {
+         value = "1048576";
+         type = "String";
+      }
+   }
+   element sys_gpio
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_gpio.external_connection
+   {
+      datum _tags
+      {
+         value = "";
+         type = "String";
+      }
+   }
+   element sys_gpio.s1
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "65664";
+         type = "String";
+      }
+   }
+   element sys_hps
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_hps.f2h_sdram0_data
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_id.control_slave
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_int_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_intr
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element sys_mem_interconnect_axi0
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_mem_interconnect_axi1
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_rst
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vga_clock_video_output
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element vga_frame_reader
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element vga_frame_reader.avalon_slave
+   {
+      datum baseAddress
+      {
+         value = "36864";
+         type = "String";
+      }
+   }
+   element vga_pixel_clock_bridge
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element vga_pll
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="5CSXFC6D6F31C8ES" />
+ <parameter name="deviceFamily" value="Cyclone V" />
+ <parameter name="deviceSpeedGrade" value="8_H6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="hps_0_f2h_cold_reset_req" internal="sys_hps.f2h_cold_reset_req" />
+ <interface
+   name="hps_0_f2h_debug_reset_req"
+   internal="sys_hps.f2h_debug_reset_req" />
+ <interface name="hps_0_f2h_warm_reset_req" internal="sys_hps.f2h_warm_reset_req" />
+ <interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
+ <interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
+ <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
+ <interface
+   name="sys_cpu_interconnect_m0"
+   internal="sys_cpu_interconnect.m0"
+   type="axi"
+   dir="start" />
+ <interface
+   name="sys_gpio_external_connection"
+   internal="sys_gpio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_hps_f2h_stm_hw_events" internal="sys_hps.f2h_stm_hw_events" />
+ <interface
+   name="sys_hps_h2f_reset"
+   internal="sys_hps.h2f_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="sys_hps_hps_io"
+   internal="sys_hps.hps_io"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_hps_i2c0" internal="sys_hps.i2c0" type="conduit" dir="end" />
+ <interface
+   name="sys_hps_i2c0_clk"
+   internal="sys_hps.i2c0_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_hps_i2c0_scl_in"
+   internal="sys_hps.i2c0_scl_in"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_hps_memory"
+   internal="sys_hps.memory"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_spim0"
+   internal="sys_hps.spim0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_spim0_sclk_out"
+   internal="sys_hps.spim0_sclk_out"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_intr"
+   internal="sys_intr.receiver_irq"
+   type="interrupt"
+   dir="start" />
+ <interface
+   name="sys_mem_interconnect_axi0_s0"
+   internal="sys_mem_interconnect_axi0.s0"
+   type="axi"
+   dir="end" />
+ <interface
+   name="sys_mem_interconnect_axi1_s0"
+   internal="sys_mem_interconnect_axi1.s0"
+   type="axi"
+   dir="end" />
+ <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
+ <interface
+   name="vga_clock_video_output_clocked_video"
+   internal="vga_clock_video_output.clocked_video"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="vga_pixel_clock_bridge_out_clk"
+   internal="vga_pixel_clock_bridge.out_clk"
+   type="clock"
+   dir="start" />
+ <module name="mem_clk" kind="altera_clock_bridge" version="16.0" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="80000000" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="mem_rst" kind="altera_reset_bridge" version="16.0" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="sys_clk" kind="altera_clock_bridge" version="16.0" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module
+   name="sys_cpu_interconnect"
+   kind="altera_axi_bridge"
+   version="16.0"
+   enabled="1">
+  <parameter name="ADDR_WIDTH" value="20" />
+  <parameter name="AXI_VERSION" value="AXI3" />
+  <parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="COMBINED_ISSUING_CAPABILITY" value="16" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="M0_ID_WIDTH" value="12" />
+  <parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="READ_ADDR_USER_WIDTH" value="64" />
+  <parameter name="READ_DATA_REORDERING_DEPTH" value="1" />
+  <parameter name="READ_DATA_USER_WIDTH" value="64" />
+  <parameter name="READ_ISSUING_CAPABILITY" value="16" />
+  <parameter name="S0_ID_WIDTH" value="12" />
+  <parameter name="USE_M0_ARBURST" value="1" />
+  <parameter name="USE_M0_ARCACHE" value="1" />
+  <parameter name="USE_M0_ARID" value="1" />
+  <parameter name="USE_M0_ARLEN" value="1" />
+  <parameter name="USE_M0_ARLOCK" value="1" />
+  <parameter name="USE_M0_ARQOS" value="1" />
+  <parameter name="USE_M0_ARREGION" value="1" />
+  <parameter name="USE_M0_ARSIZE" value="1" />
+  <parameter name="USE_M0_ARUSER" value="0" />
+  <parameter name="USE_M0_AWBURST" value="1" />
+  <parameter name="USE_M0_AWCACHE" value="1" />
+  <parameter name="USE_M0_AWID" value="1" />
+  <parameter name="USE_M0_AWLEN" value="1" />
+  <parameter name="USE_M0_AWLOCK" value="1" />
+  <parameter name="USE_M0_AWQOS" value="1" />
+  <parameter name="USE_M0_AWREGION" value="1" />
+  <parameter name="USE_M0_AWSIZE" value="1" />
+  <parameter name="USE_M0_AWUSER" value="0" />
+  <parameter name="USE_M0_BID" value="1" />
+  <parameter name="USE_M0_BRESP" value="1" />
+  <parameter name="USE_M0_BUSER" value="0" />
+  <parameter name="USE_M0_RID" value="1" />
+  <parameter name="USE_M0_RLAST" value="1" />
+  <parameter name="USE_M0_RRESP" value="1" />
+  <parameter name="USE_M0_RUSER" value="0" />
+  <parameter name="USE_M0_WSTRB" value="1" />
+  <parameter name="USE_M0_WUSER" value="0" />
+  <parameter name="USE_PIPELINE" value="1" />
+  <parameter name="USE_S0_ARCACHE" value="1" />
+  <parameter name="USE_S0_ARLOCK" value="1" />
+  <parameter name="USE_S0_ARPROT" value="1" />
+  <parameter name="USE_S0_ARQOS" value="1" />
+  <parameter name="USE_S0_ARREGION" value="1" />
+  <parameter name="USE_S0_ARUSER" value="0" />
+  <parameter name="USE_S0_AWCACHE" value="1" />
+  <parameter name="USE_S0_AWLOCK" value="1" />
+  <parameter name="USE_S0_AWPROT" value="1" />
+  <parameter name="USE_S0_AWQOS" value="1" />
+  <parameter name="USE_S0_AWREGION" value="1" />
+  <parameter name="USE_S0_AWUSER" value="0" />
+  <parameter name="USE_S0_BRESP" value="1" />
+  <parameter name="USE_S0_BUSER" value="0" />
+  <parameter name="USE_S0_RRESP" value="1" />
+  <parameter name="USE_S0_RUSER" value="0" />
+  <parameter name="USE_S0_WLAST" value="1" />
+  <parameter name="USE_S0_WUSER" value="0" />
+  <parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="WRITE_ADDR_USER_WIDTH" value="64" />
+  <parameter name="WRITE_DATA_USER_WIDTH" value="64" />
+  <parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
+  <parameter name="WRITE_RESP_USER_WIDTH" value="64" />
+ </module>
+ <module name="sys_gpio" kind="altera_avalon_pio" version="16.0" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="true" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="true" />
+  <parameter name="clockRate" value="0" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="ANY" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="EDGE" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module name="sys_hps" kind="altera_hps" version="16.0" enabled="1">
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="BONDING_OUT_ENABLED" value="false" />
+  <parameter name="BOOTFROMFPGA_Enable" value="false" />
+  <parameter name="BSEL" value="1" />
+  <parameter name="BSEL_EN" value="false" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="CAN0_Mode" value="N/A" />
+  <parameter name="CAN0_PinMuxing" value="Unused" />
+  <parameter name="CAN1_Mode" value="N/A" />
+  <parameter name="CAN1_PinMuxing" value="Unused" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="CSEL" value="0" />
+  <parameter name="CSEL_EN" value="false" />
+  <parameter name="CTI_Enable" value="false" />
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="true" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DEBUGAPB_Enable" value="false" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="EMAC0_Mode" value="N/A" />
+  <parameter name="EMAC0_PTP" value="false" />
+  <parameter name="EMAC0_PinMuxing" value="Unused" />
+  <parameter name="EMAC1_Mode" value="RGMII" />
+  <parameter name="EMAC1_PTP" value="false" />
+  <parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="F2H_AXI_CLOCK_FREQ" value="0" />
+  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="0" />
+  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="80000000" />
+  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="80000000" />
+  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
+  <parameter name="F2SCLK_COLDRST_Enable" value="false" />
+  <parameter name="F2SCLK_DBGRST_Enable" value="false" />
+  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
+  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
+  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
+  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
+  <parameter name="F2SCLK_WARMRST_Enable" value="false" />
+  <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional,AXI-3,AXI-3</parameter>
+  <parameter name="F2SDRAM_Width" value="64,64,64" />
+  <parameter name="F2SINTERRUPT_Enable" value="true" />
+  <parameter name="F2S_Width" value="2" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
+  <parameter
+     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
+     value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="0" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="100.0" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="100.0" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
+  <parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
+  <parameter name="GP_Enable" value="false" />
+  <parameter name="H2F_AXI_CLOCK_FREQ" value="0" />
+  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="0" />
+  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
+  <parameter name="HARD_EMIF" value="true" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="HHP_HPS" value="true" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HLGPI_Enable" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DDR3" />
+  <parameter name="I2C0_Mode" value="Full" />
+  <parameter name="I2C0_PinMuxing" value="FPGA" />
+  <parameter name="I2C1_Mode" value="N/A" />
+  <parameter name="I2C1_PinMuxing" value="Unused" />
+  <parameter name="I2C2_Mode" value="N/A" />
+  <parameter name="I2C2_PinMuxing" value="Unused" />
+  <parameter name="I2C3_Mode" value="N/A" />
+  <parameter name="I2C3_PinMuxing" value="Unused" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+  <parameter name="LWH2F_Enable" value="true" />
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="MAX_PENDING_RD_CMD" value="16" />
+  <parameter name="MAX_PENDING_WR_CMD" value="8" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="MEM_CLK_FREQ" value="400.0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DQ_WIDTH" value="32" />
+  <parameter name="MEM_DRV_STR" value="RZQ/7" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
+  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
+  <parameter name="MEM_RTT_WR" value="RZQ/4" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_TCL" value="11" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="260.0" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TRRD_NS" value="7.5" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="4" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="MEM_WTCL" value="8" />
+  <parameter name="MPU_EVENTS_Enable" value="false" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="NAND_Mode" value="N/A" />
+  <parameter name="NAND_PinMuxing" value="Unused" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="QSPI_Mode" value="1 SS" />
+  <parameter name="QSPI_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="RATE" value="Full" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="REF_CLK_FREQ" value="25.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
+  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
+  <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
+  <parameter name="S2FCLK_USER1CLK_Enable" value="false" />
+  <parameter name="S2FCLK_USER1CLK_FREQ" value="100.0" />
+  <parameter name="S2FCLK_USER2CLK" value="4" />
+  <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
+  <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
+  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
+  <parameter name="S2F_Width" value="2" />
+  <parameter name="SDIO_Mode" value="4-bit Data" />
+  <parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="SPEED_GRADE" value="7" />
+  <parameter name="SPIM0_Mode" value="Full" />
+  <parameter name="SPIM0_PinMuxing" value="FPGA" />
+  <parameter name="SPIM1_Mode" value="Single Slave Select" />
+  <parameter name="SPIM1_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="SPIS0_Mode" value="N/A" />
+  <parameter name="SPIS0_PinMuxing" value="Unused" />
+  <parameter name="SPIS1_Mode" value="N/A" />
+  <parameter name="SPIS1_PinMuxing" value="Unused" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="STM_Enable" value="false" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="TEST_Enable" value="false" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.03" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.02" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.16" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.09" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_TDH" value="65" />
+  <parameter name="TIMING_TDQSCK" value="255" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSH" value="0.35" />
+  <parameter name="TIMING_TDQSQ" value="125" />
+  <parameter name="TIMING_TDQSS" value="0.25" />
+  <parameter name="TIMING_TDS" value="30" />
+  <parameter name="TIMING_TDSH" value="0.2" />
+  <parameter name="TIMING_TDSS" value="0.2" />
+  <parameter name="TIMING_TIH" value="140" />
+  <parameter name="TIMING_TIS" value="180" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TQHS" value="300" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TPIUFPGA_Enable" value="false" />
+  <parameter name="TPIUFPGA_alt" value="false" />
+  <parameter name="TRACE_Mode" value="N/A" />
+  <parameter name="TRACE_PinMuxing" value="Unused" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="UART0_Mode" value="No Flow Control" />
+  <parameter name="UART0_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="UART1_Mode" value="N/A" />
+  <parameter name="UART1_PinMuxing" value="Unused" />
+  <parameter name="USB0_Mode" value="N/A" />
+  <parameter name="USB0_PinMuxing" value="Unused" />
+  <parameter name="USB1_Mode" value="SDR" />
+  <parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+  <parameter name="can0_clk_div" value="1" />
+  <parameter name="can1_clk_div" value="1" />
+  <parameter name="configure_advanced_parameters" value="false" />
+  <parameter name="customize_device_pll_info" value="false" />
+  <parameter name="dbctrl_stayosc1" value="true" />
+  <parameter name="dbg_at_clk_div" value="0" />
+  <parameter name="dbg_clk_div" value="1" />
+  <parameter name="dbg_trace_clk_div" value="0" />
+  <parameter name="desired_can0_clk_mhz" value="100.0" />
+  <parameter name="desired_can1_clk_mhz" value="100.0" />
+  <parameter name="desired_cfg_clk_mhz" value="80.0" />
+  <parameter name="desired_emac0_clk_mhz" value="250.0" />
+  <parameter name="desired_emac1_clk_mhz" value="250.0" />
+  <parameter name="desired_gpio_db_clk_hz" value="32000" />
+  <parameter name="desired_l4_mp_clk_mhz" value="100.0" />
+  <parameter name="desired_l4_sp_clk_mhz" value="100.0" />
+  <parameter name="desired_mpu_clk_mhz" value="800.0" />
+  <parameter name="desired_nand_clk_mhz" value="12.5" />
+  <parameter name="desired_qspi_clk_mhz" value="400.0" />
+  <parameter name="desired_sdmmc_clk_mhz" value="200.0" />
+  <parameter name="desired_spi_m_clk_mhz" value="200.0" />
+  <parameter name="desired_usb_mp_clk_mhz" value="200.0" />
+  <parameter name="device_name" value="5CSXFC6D6F31C8ES" />
+  <parameter name="device_pll_info_manual">{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}</parameter>
+  <parameter name="eosc1_clk_mhz" value="25.0" />
+  <parameter name="eosc2_clk_mhz" value="25.0" />
+  <parameter name="gpio_db_clk_div" value="6249" />
+  <parameter name="l3_mp_clk_div" value="1" />
+  <parameter name="l3_sp_clk_div" value="1" />
+  <parameter name="l4_mp_clk_div" value="1" />
+  <parameter name="l4_mp_clk_source" value="1" />
+  <parameter name="l4_sp_clk_div" value="1" />
+  <parameter name="l4_sp_clk_source" value="1" />
+  <parameter name="main_pll_c3" value="3" />
+  <parameter name="main_pll_c4" value="3" />
+  <parameter name="main_pll_c5" value="15" />
+  <parameter name="main_pll_m" value="63" />
+  <parameter name="main_pll_n" value="0" />
+  <parameter name="nand_clk_source" value="2" />
+  <parameter name="periph_pll_c0" value="3" />
+  <parameter name="periph_pll_c1" value="3" />
+  <parameter name="periph_pll_c2" value="1" />
+  <parameter name="periph_pll_c3" value="19" />
+  <parameter name="periph_pll_c4" value="4" />
+  <parameter name="periph_pll_c5" value="9" />
+  <parameter name="periph_pll_m" value="79" />
+  <parameter name="periph_pll_n" value="1" />
+  <parameter name="periph_pll_source" value="0" />
+  <parameter name="qspi_clk_source" value="1" />
+  <parameter name="quartus_ini_hps_emif_pll" value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
+     value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
+     value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
+     value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
+  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
+  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
+  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
+  <parameter name="sdmmc_clk_source" value="2" />
+  <parameter name="show_advanced_parameters" value="false" />
+  <parameter name="show_debug_info_as_warning_msg" value="false" />
+  <parameter name="show_warning_as_error_msg" value="false" />
+  <parameter name="spi_m_clk_div" value="0" />
+  <parameter name="usb_mp_clk_div" value="0" />
+  <parameter name="use_default_mpu_clk" value="true" />
+ </module>
+ <module
+   name="sys_id"
+   kind="altera_avalon_sysid_qsys"
+   version="16.0"
+   enabled="1">
+  <parameter name="id" value="-1395322110" />
+ </module>
+ <module
+   name="sys_int_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="16.0"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="64" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="Cyclone V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_memory2_0" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="65536" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="sys_intr" kind="altera_irq_bridge" version="16.0" enabled="1">
+  <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
+  <parameter name="IRQ_N" value="0" />
+  <parameter name="IRQ_WIDTH" value="8" />
+ </module>
+ <module
+   name="sys_mem_interconnect_axi0"
+   kind="altera_axi_bridge"
+   version="16.0"
+   enabled="1">
+  <parameter name="ADDR_WIDTH" value="32" />
+  <parameter name="AXI_VERSION" value="AXI3" />
+  <parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="COMBINED_ISSUING_CAPABILITY" value="16" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="M0_ID_WIDTH" value="4" />
+  <parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="READ_ADDR_USER_WIDTH" value="64" />
+  <parameter name="READ_DATA_REORDERING_DEPTH" value="1" />
+  <parameter name="READ_DATA_USER_WIDTH" value="64" />
+  <parameter name="READ_ISSUING_CAPABILITY" value="16" />
+  <parameter name="S0_ID_WIDTH" value="4" />
+  <parameter name="USE_M0_ARBURST" value="1" />
+  <parameter name="USE_M0_ARCACHE" value="1" />
+  <parameter name="USE_M0_ARID" value="1" />
+  <parameter name="USE_M0_ARLEN" value="1" />
+  <parameter name="USE_M0_ARLOCK" value="1" />
+  <parameter name="USE_M0_ARQOS" value="1" />
+  <parameter name="USE_M0_ARREGION" value="1" />
+  <parameter name="USE_M0_ARSIZE" value="1" />
+  <parameter name="USE_M0_ARUSER" value="0" />
+  <parameter name="USE_M0_AWBURST" value="1" />
+  <parameter name="USE_M0_AWCACHE" value="1" />
+  <parameter name="USE_M0_AWID" value="1" />
+  <parameter name="USE_M0_AWLEN" value="1" />
+  <parameter name="USE_M0_AWLOCK" value="1" />
+  <parameter name="USE_M0_AWQOS" value="1" />
+  <parameter name="USE_M0_AWREGION" value="1" />
+  <parameter name="USE_M0_AWSIZE" value="1" />
+  <parameter name="USE_M0_AWUSER" value="0" />
+  <parameter name="USE_M0_BID" value="1" />
+  <parameter name="USE_M0_BRESP" value="1" />
+  <parameter name="USE_M0_BUSER" value="0" />
+  <parameter name="USE_M0_RID" value="1" />
+  <parameter name="USE_M0_RLAST" value="1" />
+  <parameter name="USE_M0_RRESP" value="1" />
+  <parameter name="USE_M0_RUSER" value="0" />
+  <parameter name="USE_M0_WSTRB" value="1" />
+  <parameter name="USE_M0_WUSER" value="0" />
+  <parameter name="USE_PIPELINE" value="1" />
+  <parameter name="USE_S0_ARCACHE" value="1" />
+  <parameter name="USE_S0_ARLOCK" value="1" />
+  <parameter name="USE_S0_ARPROT" value="1" />
+  <parameter name="USE_S0_ARQOS" value="1" />
+  <parameter name="USE_S0_ARREGION" value="1" />
+  <parameter name="USE_S0_ARUSER" value="0" />
+  <parameter name="USE_S0_AWCACHE" value="1" />
+  <parameter name="USE_S0_AWLOCK" value="1" />
+  <parameter name="USE_S0_AWPROT" value="1" />
+  <parameter name="USE_S0_AWQOS" value="1" />
+  <parameter name="USE_S0_AWREGION" value="1" />
+  <parameter name="USE_S0_AWUSER" value="0" />
+  <parameter name="USE_S0_BRESP" value="1" />
+  <parameter name="USE_S0_BUSER" value="0" />
+  <parameter name="USE_S0_RRESP" value="1" />
+  <parameter name="USE_S0_RUSER" value="0" />
+  <parameter name="USE_S0_WLAST" value="1" />
+  <parameter name="USE_S0_WUSER" value="0" />
+  <parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="WRITE_ADDR_USER_WIDTH" value="64" />
+  <parameter name="WRITE_DATA_USER_WIDTH" value="64" />
+  <parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
+  <parameter name="WRITE_RESP_USER_WIDTH" value="64" />
+ </module>
+ <module
+   name="sys_mem_interconnect_axi1"
+   kind="altera_axi_bridge"
+   version="16.0"
+   enabled="1">
+  <parameter name="ADDR_WIDTH" value="32" />
+  <parameter name="AXI_VERSION" value="AXI3" />
+  <parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="COMBINED_ISSUING_CAPABILITY" value="16" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="M0_ID_WIDTH" value="8" />
+  <parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="READ_ADDR_USER_WIDTH" value="64" />
+  <parameter name="READ_DATA_REORDERING_DEPTH" value="1" />
+  <parameter name="READ_DATA_USER_WIDTH" value="64" />
+  <parameter name="READ_ISSUING_CAPABILITY" value="16" />
+  <parameter name="S0_ID_WIDTH" value="8" />
+  <parameter name="USE_M0_ARBURST" value="1" />
+  <parameter name="USE_M0_ARCACHE" value="1" />
+  <parameter name="USE_M0_ARID" value="1" />
+  <parameter name="USE_M0_ARLEN" value="1" />
+  <parameter name="USE_M0_ARLOCK" value="1" />
+  <parameter name="USE_M0_ARQOS" value="1" />
+  <parameter name="USE_M0_ARREGION" value="1" />
+  <parameter name="USE_M0_ARSIZE" value="1" />
+  <parameter name="USE_M0_ARUSER" value="0" />
+  <parameter name="USE_M0_AWBURST" value="1" />
+  <parameter name="USE_M0_AWCACHE" value="1" />
+  <parameter name="USE_M0_AWID" value="1" />
+  <parameter name="USE_M0_AWLEN" value="1" />
+  <parameter name="USE_M0_AWLOCK" value="1" />
+  <parameter name="USE_M0_AWQOS" value="1" />
+  <parameter name="USE_M0_AWREGION" value="1" />
+  <parameter name="USE_M0_AWSIZE" value="1" />
+  <parameter name="USE_M0_AWUSER" value="0" />
+  <parameter name="USE_M0_BID" value="1" />
+  <parameter name="USE_M0_BRESP" value="1" />
+  <parameter name="USE_M0_BUSER" value="0" />
+  <parameter name="USE_M0_RID" value="1" />
+  <parameter name="USE_M0_RLAST" value="1" />
+  <parameter name="USE_M0_RRESP" value="1" />
+  <parameter name="USE_M0_RUSER" value="0" />
+  <parameter name="USE_M0_WSTRB" value="1" />
+  <parameter name="USE_M0_WUSER" value="0" />
+  <parameter name="USE_PIPELINE" value="1" />
+  <parameter name="USE_S0_ARCACHE" value="1" />
+  <parameter name="USE_S0_ARLOCK" value="1" />
+  <parameter name="USE_S0_ARPROT" value="1" />
+  <parameter name="USE_S0_ARQOS" value="1" />
+  <parameter name="USE_S0_ARREGION" value="1" />
+  <parameter name="USE_S0_ARUSER" value="0" />
+  <parameter name="USE_S0_AWCACHE" value="1" />
+  <parameter name="USE_S0_AWLOCK" value="1" />
+  <parameter name="USE_S0_AWPROT" value="1" />
+  <parameter name="USE_S0_AWQOS" value="1" />
+  <parameter name="USE_S0_AWREGION" value="1" />
+  <parameter name="USE_S0_AWUSER" value="0" />
+  <parameter name="USE_S0_BRESP" value="1" />
+  <parameter name="USE_S0_BUSER" value="0" />
+  <parameter name="USE_S0_RRESP" value="1" />
+  <parameter name="USE_S0_RUSER" value="0" />
+  <parameter name="USE_S0_WLAST" value="1" />
+  <parameter name="USE_S0_WUSER" value="0" />
+  <parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" />
+  <parameter name="WRITE_ADDR_USER_WIDTH" value="64" />
+  <parameter name="WRITE_DATA_USER_WIDTH" value="64" />
+  <parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
+  <parameter name="WRITE_RESP_USER_WIDTH" value="64" />
+ </module>
+ <module name="sys_rst" kind="altera_reset_bridge" version="16.0" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module
+   name="vga_clock_video_output"
+   kind="alt_vip_itc"
+   version="14.0"
+   enabled="1">
+  <parameter name="ACCEPT_COLOURS_IN_SEQ" value="0" />
+  <parameter name="ANC_LINE" value="0" />
+  <parameter name="AP_LINE" value="0" />
+  <parameter name="BPS" value="8" />
+  <parameter name="CLOCKS_ARE_SAME" value="0" />
+  <parameter name="COLOUR_PLANES_ARE_IN_PARALLEL" value="1" />
+  <parameter name="FAMILY" value="Cyclone V" />
+  <parameter name="FIELD0_ANC_LINE" value="0" />
+  <parameter name="FIELD0_V_BACK_PORCH" value="0" />
+  <parameter name="FIELD0_V_BLANK" value="0" />
+  <parameter name="FIELD0_V_FRONT_PORCH" value="0" />
+  <parameter name="FIELD0_V_RISING_EDGE" value="0" />
+  <parameter name="FIELD0_V_SYNC_LENGTH" value="0" />
+  <parameter name="FIFO_DEPTH" value="1920" />
+  <parameter name="F_FALLING_EDGE" value="0" />
+  <parameter name="F_RISING_EDGE" value="0" />
+  <parameter name="GENERATE_SYNC" value="0" />
+  <parameter name="H_ACTIVE_PIXELS" value="1360" />
+  <parameter name="H_BACK_PORCH" value="256" />
+  <parameter name="H_BLANK" value="0" />
+  <parameter name="H_FRONT_PORCH" value="64" />
+  <parameter name="H_SYNC_LENGTH" value="112" />
+  <parameter name="INTERLACED" value="0" />
+  <parameter name="NO_OF_MODES" value="1" />
+  <parameter name="NUMBER_OF_COLOUR_PLANES" value="4" />
+  <parameter name="STD_WIDTH" value="1" />
+  <parameter name="THRESHOLD" value="1919" />
+  <parameter name="USE_CONTROL" value="0" />
+  <parameter name="USE_EMBEDDED_SYNCS" value="0" />
+  <parameter name="V_ACTIVE_LINES" value="768" />
+  <parameter name="V_BACK_PORCH" value="18" />
+  <parameter name="V_BLANK" value="0" />
+  <parameter name="V_FRONT_PORCH" value="3" />
+  <parameter name="V_SYNC_LENGTH" value="6" />
+ </module>
+ <module name="vga_frame_reader" kind="alt_vip_vfr" version="14.0" enabled="1">
+  <parameter name="AUTO_CLOCK_MASTER_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_CLOCK_RESET_CLOCK_RATE" value="85500000" />
+  <parameter name="BITS_PER_PIXEL_PER_COLOR_PLANE" value="8" />
+  <parameter name="CLOCKS_ARE_SEPARATE" value="1" />
+  <parameter name="FAMILY" value="Cyclone V" />
+  <parameter name="MAX_IMAGE_HEIGHT" value="768" />
+  <parameter name="MAX_IMAGE_WIDTH" value="1360" />
+  <parameter name="MEM_PORT_WIDTH" value="128" />
+  <parameter name="NUMBER_OF_CHANNELS_IN_PARALLEL" value="4" />
+  <parameter name="NUMBER_OF_CHANNELS_IN_SEQUENCE" value="1" />
+  <parameter name="RMASTER_BURST_TARGET" value="32" />
+  <parameter name="RMASTER_FIFO_DEPTH" value="64" />
+ </module>
+ <module
+   name="vga_pixel_clock_bridge"
+   kind="altera_clock_bridge"
+   version="16.0"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="85500000" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="vga_pll" kind="altera_pll" version="16.0" enabled="1">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device" value="5CSXFC6D6F31C8ES" />
+  <parameter name="device_family" value="Cyclone V" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_device_speed_grade" value="2" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_number_of_clocks" value="2" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_output_clock_frequency0" value="85.5" />
+  <parameter name="gui_output_clock_frequency1" value="171.0" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_pll_auto_reset" value="Off" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_reference_clock_frequency" value="50.0" />
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_locked" value="false" />
+ </module>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="vga_frame_reader.avalon_master"
+   end="sys_hps.f2h_sdram0_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_axi_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="vga_frame_reader.avalon_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x9000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_cpu_interconnect.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00100000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_gpio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010080" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_mem_interconnect_axi0.m0"
+   end="sys_hps.f2h_sdram1_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="16.0"
+   start="sys_mem_interconnect_axi1.m0"
+   end="sys_hps.f2h_sdram2_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="16.0"
+   start="vga_frame_reader.avalon_streaming_source"
+   end="vga_clock_video_output.din" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_hps.h2f_user0_clock"
+   end="sys_mem_interconnect_axi0.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_hps.h2f_user0_clock"
+   end="sys_mem_interconnect_axi1.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_hps.h2f_user0_clock"
+   end="sys_hps.f2h_sdram1_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_hps.h2f_user0_clock"
+   end="sys_hps.f2h_sdram2_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_hps.h2f_user0_clock"
+   end="mem_clk.in_clk" />
+ <connection kind="clock" version="16.0" start="sys_clk.out_clk" end="sys_id.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="sys_gpio.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="sys_cpu_interconnect.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="sys_intr.clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="vga_frame_reader.clock_master" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="sys_hps.f2h_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="sys_hps.f2h_sdram0_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="sys_hps.h2f_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="sys_hps.h2f_lw_axi_clock" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="sys_clk.out_clk"
+   end="vga_pll.refclk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="vga_pll.outclk0"
+   end="vga_frame_reader.clock_reset" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="vga_pll.outclk0"
+   end="vga_pixel_clock_bridge.in_clk" />
+ <connection
+   kind="clock"
+   version="16.0"
+   start="vga_pll.outclk0"
+   end="vga_clock_video_output.is_clk_rst" />
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="vga_frame_reader.interrupt_sender">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_gpio.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_intr.sender0_irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_intr.sender1_irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_intr.sender2_irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_intr.sender3_irq">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_intr.sender4_irq">
+  <parameter name="irqNumber" value="6" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_intr.sender5_irq">
+  <parameter name="irqNumber" value="7" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_intr.sender6_irq">
+  <parameter name="irqNumber" value="8" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="16.0"
+   start="sys_hps.f2h_irq0"
+   end="sys_intr.sender7_irq">
+  <parameter name="irqNumber" value="9" />
+ </connection>
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="sys_cpu_interconnect.clk_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="sys_mem_interconnect_axi0.clk_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="sys_mem_interconnect_axi1.clk_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="sys_intr.clk_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="vga_frame_reader.clock_master_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="vga_frame_reader.clock_reset_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="mem_rst.in_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="vga_clock_video_output.is_clk_rst_reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="sys_id.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="sys_gpio.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="vga_pll.reset" />
+ <connection
+   kind="reset"
+   version="16.0"
+   start="sys_rst.out_reset"
+   end="sys_int_mem.reset1" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+ <interconnectRequirement
+   for="mm_interconnect_0|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_2|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_3|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+ <interconnectRequirement
+   for="mm_interconnect_4|cmd_mux_001"
+   name="qsys_mm.postTransform.pipelineCount"
+   value="0" />
+</system>
diff --git a/projects/common/c5soc/c5soc_system_qsys.tcl b/projects/common/c5soc/c5soc_system_qsys.tcl
deleted file mode 100755
index 47f47fa36..000000000
--- a/projects/common/c5soc/c5soc_system_qsys.tcl
+++ /dev/null
@@ -1,311 +0,0 @@
-
-package require qsys
-
-set_module_property NAME {system_bd}
-set_project_property DEVICE_FAMILY {Cyclone V}
-set_project_property DEVICE {5CSXFC6D6F31C8ES}
-
-# system clock
-
-add_instance sys_clk clock_source 16.0
-set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
-set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
-set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
-add_interface sys_clk clock sink
-add_interface sys_rst reset sink
-set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
-set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
-
-# hps
-
-add_instance sys_hps altera_hps 16.0
-set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
-set_instance_parameter_value sys_hps {F2SDRAM_Type} {Avalon-MM\ Bidirectional AXI-3 AXI-3}
-set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 64 64}
-set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
-set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A}
-set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
-set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
-set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
-set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {USB0_Mode} {N/A}
-set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
-set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {SPIM0_Mode} {N/A}
-set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select}
-set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
-set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
-set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
-set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
-set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
-set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
-set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
-set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
-set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
-set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
-set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
-set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
-set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
-set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
-set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3}
-set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
-set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32}
-set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
-set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
-set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
-set_instance_parameter_value sys_hps {MEM_TCL} {11}
-set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/7}
-set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
-set_instance_parameter_value sys_hps {MEM_WTCL} {8}
-set_instance_parameter_value sys_hps {MEM_RTT_WR} {RZQ/4}
-set_instance_parameter_value sys_hps {TIMING_TIS} {180}
-set_instance_parameter_value sys_hps {TIMING_TIH} {140}
-set_instance_parameter_value sys_hps {TIMING_TDS} {30}
-set_instance_parameter_value sys_hps {TIMING_TDH} {65}
-set_instance_parameter_value sys_hps {TIMING_TDQSQ} {125}
-set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
-set_instance_parameter_value sys_hps {TIMING_TDQSCK} {255}
-set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25}
-set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
-set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2}
-set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2}
-set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
-set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
-set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
-set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
-set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
-set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
-set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
-set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
-set_instance_parameter_value sys_hps {MEM_TWTR} {4}
-set_instance_parameter_value sys_hps {MEM_TFAW_NS} {30.0}
-set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5}
-set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
-set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.03}
-set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.02}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {0.09}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.16}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.01}
-set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.08}
-set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
-set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.03}
-set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
-add_interface sys_hps_memory conduit end
-set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory
-add_interface sys_hps_hps_io conduit end
-set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io
-add_interface sys_hps_h2f_reset reset source
-set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset
-add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
-add_connection sys_clk.clk sys_hps.h2f_axi_clock
-add_connection sys_clk.clk sys_hps.f2h_axi_clock
-add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
-add_interface sys_hps_i2c0 conduit end
-set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
-add_interface sys_hps_i2c0_clk clock source
-set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
-add_interface sys_hps_i2c0_scl_in clock sink
-set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
-
-# cpu/hps handling
-
-proc ad_cpu_interrupt {m_irq m_port} {
-
-  add_connection sys_hps.f2h_irq0 ${m_port}
-  set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
-}
-
-proc ad_cpu_interconnect {m_base m_port} {
-
-  add_connection sys_hps.h2f_lw_axi_master ${m_port}
-  set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
-}
-
-proc ad_dma_interconnect {m_port m_id} {
-
-  if {${m_id} == 1} {
-    add_connection ${m_port} sys_hps.f2h_sdram1_data
-    set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram1_data baseAddress {0x0000}
-    return
-  }
-
-  add_connection ${m_port} sys_hps.f2h_sdram2_data
-  set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram2_data baseAddress {0x0000}
-}
-
-# common dma interfaces
-
-add_instance sys_dma_clk clock_source 16.0
-add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
-add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
-add_connection sys_dma_clk.clk sys_hps.f2h_sdram1_clock
-add_connection sys_dma_clk.clk sys_hps.f2h_sdram2_clock
-
-# internal memory
-
-add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
-set_instance_parameter_value sys_int_mem {dualPort} {0}
-set_instance_parameter_value sys_int_mem {dataWidth} {64}
-set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
-set_instance_parameter_value sys_int_mem {initMemContent} {0}
-add_connection sys_clk.clk sys_int_mem.clk1
-add_connection sys_clk.clk_reset sys_int_mem.reset1
-add_connection sys_hps.h2f_axi_master sys_int_mem.s1
-set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000}
-
-# display (vga-pll)
-
-add_instance vga_pll altera_pll 16.0
-set_instance_parameter_value vga_pll {gui_device_speed_grade} {2}
-set_instance_parameter_value vga_pll {gui_reference_clock_frequency} {50.0}
-set_instance_parameter_value vga_pll {gui_use_locked} {0}
-set_instance_parameter_value vga_pll {gui_number_of_clocks} {2}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency0} {85.5}
-set_instance_parameter_value vga_pll {gui_output_clock_frequency1} {171.0}
-add_connection sys_clk.clk vga_pll.refclk
-add_connection sys_clk.clk_reset vga_pll.reset
-
-# display (vga-frame-reader)
-
-add_instance vga_frame_reader alt_vip_vfr 14.0
-set_instance_parameter_value vga_frame_reader {BITS_PER_PIXEL_PER_COLOR_PLANE} {8}
-set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_PARALLEL} {4}
-set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_SEQUENCE} {1}
-set_instance_parameter_value vga_frame_reader {MAX_IMAGE_WIDTH} {1360}
-set_instance_parameter_value vga_frame_reader {MAX_IMAGE_HEIGHT} {768}
-set_instance_parameter_value vga_frame_reader {MEM_PORT_WIDTH} {128}
-set_instance_parameter_value vga_frame_reader {RMASTER_FIFO_DEPTH} {64}
-set_instance_parameter_value vga_frame_reader {RMASTER_BURST_TARGET} {32}
-set_instance_parameter_value vga_frame_reader {CLOCKS_ARE_SEPARATE} {1}
-add_connection sys_clk.clk vga_frame_reader.clock_master
-add_connection sys_clk.clk_reset vga_frame_reader.clock_master_reset
-add_connection vga_frame_reader.avalon_master sys_hps.f2h_sdram0_data
-set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data baseAddress {0x0000}
-add_connection vga_pll.outclk0 vga_frame_reader.clock_reset
-add_connection sys_clk.clk_reset vga_frame_reader.clock_reset_reset
-
-# display (vga-out-clock)
-
-add_instance vga_out_clock altera_clock_bridge 16.0
-set_instance_parameter_value vga_out_clock {NUM_CLOCK_OUTPUTS} {1}
-add_connection vga_pll.outclk0 vga_out_clock.in_clk
-add_interface vga_out_clk clock source
-set_interface_property vga_out_clk EXPORT_OF vga_out_clock.out_clk
-
-# display (vga-out-data)
-
-add_instance vga_out_data alt_vip_itc 14.0
-set_instance_parameter_value vga_out_data {H_ACTIVE_PIXELS} {1360}
-set_instance_parameter_value vga_out_data {V_ACTIVE_LINES} {768}
-set_instance_parameter_value vga_out_data {BPS} {8}
-set_instance_parameter_value vga_out_data {NUMBER_OF_COLOUR_PLANES} {4}
-set_instance_parameter_value vga_out_data {COLOUR_PLANES_ARE_IN_PARALLEL} {1}
-set_instance_parameter_value vga_out_data {ACCEPT_COLOURS_IN_SEQ} {0}
-set_instance_parameter_value vga_out_data {INTERLACED} {0}
-set_instance_parameter_value vga_out_data {USE_EMBEDDED_SYNCS} {0}
-set_instance_parameter_value vga_out_data {AP_LINE} {0}
-set_instance_parameter_value vga_out_data {ANC_LINE} {0}
-set_instance_parameter_value vga_out_data {H_BLANK} {0}
-set_instance_parameter_value vga_out_data {V_BLANK} {0}
-set_instance_parameter_value vga_out_data {H_SYNC_LENGTH} {112}
-set_instance_parameter_value vga_out_data {H_FRONT_PORCH} {64}
-set_instance_parameter_value vga_out_data {H_BACK_PORCH} {256}
-set_instance_parameter_value vga_out_data {V_SYNC_LENGTH} {6}
-set_instance_parameter_value vga_out_data {V_FRONT_PORCH} {3}
-set_instance_parameter_value vga_out_data {V_BACK_PORCH} {18}
-set_instance_parameter_value vga_out_data {F_RISING_EDGE} {0}
-set_instance_parameter_value vga_out_data {F_FALLING_EDGE} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_RISING_EDGE} {0}
-set_instance_parameter_value vga_out_data {FIELD0_ANC_LINE} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_BLANK} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_SYNC_LENGTH} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_FRONT_PORCH} {0}
-set_instance_parameter_value vga_out_data {FIELD0_V_BACK_PORCH} {0}
-set_instance_parameter_value vga_out_data {FIFO_DEPTH} {1920}
-set_instance_parameter_value vga_out_data {THRESHOLD} {1919}
-set_instance_parameter_value vga_out_data {CLOCKS_ARE_SAME} {0}
-set_instance_parameter_value vga_out_data {USE_CONTROL} {0}
-set_instance_parameter_value vga_out_data {GENERATE_SYNC} {0}
-set_instance_parameter_value vga_out_data {NO_OF_MODES} {1}
-set_instance_parameter_value vga_out_data {STD_WIDTH} {1}
-add_connection vga_pll.outclk0 vga_out_data.is_clk_rst
-add_connection sys_clk.clk_reset vga_out_data.is_clk_rst_reset
-add_connection vga_frame_reader.avalon_streaming_source vga_out_data.din
-add_interface vga_out_data conduit end
-set_interface_property vga_out_data EXPORT_OF vga_out_data.clocked_video
-
-# id
-
-add_instance sys_id altera_avalon_sysid_qsys 16.0
-set_instance_parameter_value sys_id {id} {-1395322110}
-add_connection sys_clk.clk sys_id.clk
-add_connection sys_clk.clk_reset sys_id.reset
-
-# gpio-bd
-
-add_instance sys_gpio_bd altera_avalon_pio 16.0
-set_instance_parameter_value sys_gpio_bd {direction} {InOut}
-set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
-set_instance_parameter_value sys_gpio_bd {width} {32}
-add_connection sys_clk.clk sys_gpio_bd.clk
-add_connection sys_clk.clk_reset sys_gpio_bd.reset
-add_interface sys_gpio_bd conduit end
-set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
-
-# gpio-in
-
-add_instance sys_gpio_in altera_avalon_pio 16.0
-set_instance_parameter_value sys_gpio_in {direction} {Input}
-set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
-set_instance_parameter_value sys_gpio_in {width} {32}
-add_connection sys_clk.clk_reset sys_gpio_in.reset
-add_connection sys_clk.clk sys_gpio_in.clk
-add_interface sys_gpio_in conduit end
-set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
-
-# gpio-out
-
-add_instance sys_gpio_out altera_avalon_pio 16.0
-set_instance_parameter_value sys_gpio_out {direction} {Output}
-set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
-set_instance_parameter_value sys_gpio_out {width} {32}
-add_connection sys_clk.clk_reset sys_gpio_out.reset
-add_connection sys_clk.clk sys_gpio_out.clk
-add_interface sys_gpio_out conduit end
-set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
-
-# spi
-
-add_instance sys_spi altera_avalon_spi 16.0
-set_instance_parameter_value sys_spi {clockPhase} {0}
-set_instance_parameter_value sys_spi {clockPolarity} {1}
-set_instance_parameter_value sys_spi {dataWidth} {8}
-set_instance_parameter_value sys_spi {masterSPI} {1}
-set_instance_parameter_value sys_spi {numberOfSlaves} {1}
-set_instance_parameter_value sys_spi {targetClockRate} {50000000.0}
-add_connection sys_clk.clk sys_spi.clk
-add_connection sys_clk.clk_reset sys_spi.reset
-add_interface sys_spi conduit end
-set_interface_property sys_spi EXPORT_OF sys_spi.external
-
-# interrupts
-
-ad_cpu_interrupt 0 sys_gpio_bd.irq
-ad_cpu_interrupt 1 sys_spi.irq
-ad_cpu_interrupt 4 vga_frame_reader.interrupt_sender
-
-# cpu interconnects
-
-ad_cpu_interconnect 0x00108000 sys_spi.spi_control_port
-ad_cpu_interconnect 0x00009000 vga_frame_reader.avalon_slave
-ad_cpu_interconnect 0x00010000 sys_id.control_slave
-ad_cpu_interconnect 0x00010080 sys_gpio_bd.s1
-ad_cpu_interconnect 0x00010100 sys_gpio_in.s1
-ad_cpu_interconnect 0x00109000 sys_gpio_out.s1
-